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authorIngo Molnar <mingo@kernel.org>2018-04-12 10:42:34 +0300
committerIngo Molnar <mingo@kernel.org>2018-04-12 10:42:34 +0300
commitef389b734691cdc8beb009dd402135dcdcb86a56 (patch)
tree9523a37db93cb7c7874a5f18b4d9a7014898b814 /arch
parenta774635db5c430cbf21fa5d2f2df3d23aaa8e782 (diff)
parentc76fc98260751e71c884dc1a18a07e427ef033b5 (diff)
downloadlinux-ef389b734691cdc8beb009dd402135dcdcb86a56.tar.xz
Merge branch 'WIP.x86/asm' into x86/urgent, because the topic is ready
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/include/asm/cmpxchg.h20
-rw-r--r--arch/alpha/include/asm/xchg.h27
-rw-r--r--arch/alpha/kernel/osf_sys.c2
-rw-r--r--arch/alpha/kernel/perf_event.c2
-rw-r--r--arch/arm/Kconfig.debug1
-rwxr-xr-xarch/arm/boot/deflate_xip_data.sh6
-rw-r--r--arch/arm/boot/dts/aspeed-g4.dtsi5
-rw-r--r--arch/arm/boot/dts/aspeed-g5.dtsi5
-rw-r--r--arch/arm/boot/dts/imx7d-sdb.dts2
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi2
-rw-r--r--arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts63
-rw-r--r--arch/arm/include/asm/dma-direct.h4
-rw-r--r--arch/arm/include/asm/vdso.h2
-rw-r--r--arch/arm/kernel/sys_arm.c2
-rw-r--r--arch/arm/kernel/vdso.c12
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c4
-rw-r--r--arch/arm/mach-imx/mmdc.c2
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c3
-rw-r--r--arch/arm/mm/cache-l2x0-pmu.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c7
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h11
-rw-r--r--arch/arm/plat-omap/sram.c36
-rw-r--r--arch/arm/vfp/vfpmodule.c2
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi16
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi8
-rw-r--r--arch/arm64/include/asm/efi.h4
-rw-r--r--arch/arm64/kernel/Makefile3
-rw-r--r--arch/arm64/kernel/cpu_errata.c4
-rw-r--r--arch/arm64/kernel/efi-rt-wrapper.S41
-rw-r--r--arch/arm64/kernel/efi.c6
-rw-r--r--arch/arm64/kernel/sys.c2
-rw-r--r--arch/arm64/kvm/guest.c3
-rw-r--r--arch/arm64/mm/mmu.c18
-rw-r--r--arch/blackfin/Clear_BSD.txt33
-rw-r--r--arch/blackfin/Kconfig1463
-rw-r--r--arch/blackfin/Kconfig.debug258
-rw-r--r--arch/blackfin/Makefile168
-rw-r--r--arch/blackfin/boot/.gitignore3
-rw-r--r--arch/blackfin/boot/Makefile71
-rw-r--r--arch/blackfin/boot/install.sh57
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig121
-rw-r--r--arch/blackfin/configs/BF526-EZBRD_defconfig158
-rw-r--r--arch/blackfin/configs/BF527-AD7160-EVAL_defconfig104
-rw-r--r--arch/blackfin/configs/BF527-EZKIT-V2_defconfig188
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig181
-rw-r--r--arch/blackfin/configs/BF527-TLL6527M_defconfig178
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig114
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig124
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig136
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig133
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig207
-rw-r--r--arch/blackfin/configs/BF561-ACVILON_defconfig149
-rw-r--r--arch/blackfin/configs/BF561-EZKIT-SMP_defconfig112
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig114
-rw-r--r--arch/blackfin/configs/BF609-EZKIT_defconfig154
-rw-r--r--arch/blackfin/configs/BlackStamp_defconfig108
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig129
-rw-r--r--arch/blackfin/configs/CM-BF533_defconfig76
-rw-r--r--arch/blackfin/configs/CM-BF537E_defconfig107
-rw-r--r--arch/blackfin/configs/CM-BF537U_defconfig96
-rw-r--r--arch/blackfin/configs/CM-BF548_defconfig170
-rw-r--r--arch/blackfin/configs/CM-BF561_defconfig104
-rw-r--r--arch/blackfin/configs/DNP5370_defconfig118
-rw-r--r--arch/blackfin/configs/H8606_defconfig87
-rw-r--r--arch/blackfin/configs/IP0X_defconfig91
-rw-r--r--arch/blackfin/configs/PNAV-10_defconfig111
-rw-r--r--arch/blackfin/configs/SRV1_defconfig88
-rw-r--r--arch/blackfin/configs/TCM-BF518_defconfig131
-rw-r--r--arch/blackfin/configs/TCM-BF537_defconfig95
-rw-r--r--arch/blackfin/include/asm/Kbuild28
-rw-r--r--arch/blackfin/include/asm/asm-offsets.h1
-rw-r--r--arch/blackfin/include/asm/atomic.h47
-rw-r--r--arch/blackfin/include/asm/barrier.h86
-rw-r--r--arch/blackfin/include/asm/bfin-global.h95
-rw-r--r--arch/blackfin/include/asm/bfin-lq035q1.h40
-rw-r--r--arch/blackfin/include/asm/bfin5xx_spi.h86
-rw-r--r--arch/blackfin/include/asm/bfin_can.h728
-rw-r--r--arch/blackfin/include/asm/bfin_dma.h165
-rw-r--r--arch/blackfin/include/asm/bfin_pfmon.h44
-rw-r--r--arch/blackfin/include/asm/bfin_ppi.h181
-rw-r--r--arch/blackfin/include/asm/bfin_sdh.h161
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h429
-rw-r--r--arch/blackfin/include/asm/bfin_simple_timer.h27
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h71
-rw-r--r--arch/blackfin/include/asm/bfin_sport3.h107
-rw-r--r--arch/blackfin/include/asm/bfin_twi.h214
-rw-r--r--arch/blackfin/include/asm/bfin_watchdog.h30
-rw-r--r--arch/blackfin/include/asm/bfrom.h90
-rw-r--r--arch/blackfin/include/asm/bitops.h140
-rw-r--r--arch/blackfin/include/asm/blackfin.h88
-rw-r--r--arch/blackfin/include/asm/bug.h73
-rw-r--r--arch/blackfin/include/asm/cache.h70
-rw-r--r--arch/blackfin/include/asm/cacheflush.h118
-rw-r--r--arch/blackfin/include/asm/cdef_LPBlackfin.h309
-rw-r--r--arch/blackfin/include/asm/checksum.h44
-rw-r--r--arch/blackfin/include/asm/clocks.h74
-rw-r--r--arch/blackfin/include/asm/cmpxchg.h132
-rw-r--r--arch/blackfin/include/asm/context.S407
-rw-r--r--arch/blackfin/include/asm/cplb.h153
-rw-r--r--arch/blackfin/include/asm/cplbinit.h66
-rw-r--r--arch/blackfin/include/asm/cpu.h24
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h697
-rw-r--r--arch/blackfin/include/asm/delay.h51
-rw-r--r--arch/blackfin/include/asm/dma-mapping.h46
-rw-r--r--arch/blackfin/include/asm/dma.h349
-rw-r--r--arch/blackfin/include/asm/dpmc.h794
-rw-r--r--arch/blackfin/include/asm/early_printk.h36
-rw-r--r--arch/blackfin/include/asm/elf.h135
-rw-r--r--arch/blackfin/include/asm/entry.h178
-rw-r--r--arch/blackfin/include/asm/exec.h1
-rw-r--r--arch/blackfin/include/asm/fixed_code.h30
-rw-r--r--arch/blackfin/include/asm/flat.h62
-rw-r--r--arch/blackfin/include/asm/ftrace.h73
-rw-r--r--arch/blackfin/include/asm/gpio.h234
-rw-r--r--arch/blackfin/include/asm/gptimers.h337
-rw-r--r--arch/blackfin/include/asm/hardirq.h17
-rw-r--r--arch/blackfin/include/asm/io.h49
-rw-r--r--arch/blackfin/include/asm/ipipe.h209
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h75
-rw-r--r--arch/blackfin/include/asm/irq.h41
-rw-r--r--arch/blackfin/include/asm/irq_handler.h66
-rw-r--r--arch/blackfin/include/asm/irqflags.h289
-rw-r--r--arch/blackfin/include/asm/kgdb.h169
-rw-r--r--arch/blackfin/include/asm/l1layout.h37
-rw-r--r--arch/blackfin/include/asm/linkage.h13
-rw-r--r--arch/blackfin/include/asm/mem_init.h500
-rw-r--r--arch/blackfin/include/asm/mem_map.h84
-rw-r--r--arch/blackfin/include/asm/mmu.h36
-rw-r--r--arch/blackfin/include/asm/mmu_context.h218
-rw-r--r--arch/blackfin/include/asm/module.h22
-rw-r--r--arch/blackfin/include/asm/nand.h40
-rw-r--r--arch/blackfin/include/asm/nmi.h14
-rw-r--r--arch/blackfin/include/asm/page.h22
-rw-r--r--arch/blackfin/include/asm/page_offset.h11
-rw-r--r--arch/blackfin/include/asm/pci.h13
-rw-r--r--arch/blackfin/include/asm/pda.h73
-rw-r--r--arch/blackfin/include/asm/perf_event.h1
-rw-r--r--arch/blackfin/include/asm/pgtable.h104
-rw-r--r--arch/blackfin/include/asm/pm.h31
-rw-r--r--arch/blackfin/include/asm/portmux.h1204
-rw-r--r--arch/blackfin/include/asm/processor.h145
-rw-r--r--arch/blackfin/include/asm/pseudo_instructions.h18
-rw-r--r--arch/blackfin/include/asm/ptrace.h42
-rw-r--r--arch/blackfin/include/asm/reboot.h20
-rw-r--r--arch/blackfin/include/asm/rwlock.h7
-rw-r--r--arch/blackfin/include/asm/scb.h21
-rw-r--r--arch/blackfin/include/asm/sections.h67
-rw-r--r--arch/blackfin/include/asm/segment.h13
-rw-r--r--arch/blackfin/include/asm/smp.h54
-rw-r--r--arch/blackfin/include/asm/spinlock.h81
-rw-r--r--arch/blackfin/include/asm/spinlock_types.h28
-rw-r--r--arch/blackfin/include/asm/string.h38
-rw-r--r--arch/blackfin/include/asm/switch_to.h39
-rw-r--r--arch/blackfin/include/asm/syscall.h96
-rw-r--r--arch/blackfin/include/asm/thread_info.h98
-rw-r--r--arch/blackfin/include/asm/time.h46
-rw-r--r--arch/blackfin/include/asm/timex.h23
-rw-r--r--arch/blackfin/include/asm/tlb.h22
-rw-r--r--arch/blackfin/include/asm/tlbflush.h2
-rw-r--r--arch/blackfin/include/asm/trace.h106
-rw-r--r--arch/blackfin/include/asm/traps.h131
-rw-r--r--arch/blackfin/include/asm/uaccess.h234
-rw-r--r--arch/blackfin/include/asm/unistd.h22
-rw-r--r--arch/blackfin/include/asm/vga.h1
-rw-r--r--arch/blackfin/include/mach-common/irq.h58
-rw-r--r--arch/blackfin/include/mach-common/pll.h86
-rw-r--r--arch/blackfin/include/mach-common/ports-a.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-b.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-c.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-d.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-e.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-f.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-g.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-h.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-i.h26
-rw-r--r--arch/blackfin/include/mach-common/ports-j.h26
-rw-r--r--arch/blackfin/include/uapi/asm/Kbuild25
-rw-r--r--arch/blackfin/include/uapi/asm/bfin_sport.h137
-rw-r--r--arch/blackfin/include/uapi/asm/byteorder.h7
-rw-r--r--arch/blackfin/include/uapi/asm/cachectl.h21
-rw-r--r--arch/blackfin/include/uapi/asm/fcntl.h18
-rw-r--r--arch/blackfin/include/uapi/asm/fixed_code.h39
-rw-r--r--arch/blackfin/include/uapi/asm/ioctls.h8
-rw-r--r--arch/blackfin/include/uapi/asm/poll.h17
-rw-r--r--arch/blackfin/include/uapi/asm/posix_types.h31
-rw-r--r--arch/blackfin/include/uapi/asm/ptrace.h171
-rw-r--r--arch/blackfin/include/uapi/asm/sigcontext.h62
-rw-r--r--arch/blackfin/include/uapi/asm/siginfo.h16
-rw-r--r--arch/blackfin/include/uapi/asm/signal.h8
-rw-r--r--arch/blackfin/include/uapi/asm/stat.h70
-rw-r--r--arch/blackfin/include/uapi/asm/swab.h51
-rw-r--r--arch/blackfin/include/uapi/asm/unistd.h448
-rw-r--r--arch/blackfin/kernel/.gitignore1
-rw-r--r--arch/blackfin/kernel/Makefile44
-rw-r--r--arch/blackfin/kernel/asm-offsets.c164
-rw-r--r--arch/blackfin/kernel/bfin_dma.c612
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c1208
-rw-r--r--arch/blackfin/kernel/bfin_ksyms.c126
-rw-r--r--arch/blackfin/kernel/cplb-mpu/Makefile10
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinit.c102
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c379
-rw-r--r--arch/blackfin/kernel/cplb-nompu/Makefile11
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c212
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbmgr.c227
-rw-r--r--arch/blackfin/kernel/cplbinfo.c180
-rw-r--r--arch/blackfin/kernel/debug-mmrs.c1891
-rw-r--r--arch/blackfin/kernel/dma-mapping.c172
-rw-r--r--arch/blackfin/kernel/dumpstack.c177
-rw-r--r--arch/blackfin/kernel/early_printk.c271
-rw-r--r--arch/blackfin/kernel/entry.S59
-rw-r--r--arch/blackfin/kernel/exception.c45
-rw-r--r--arch/blackfin/kernel/fixed_code.S155
-rw-r--r--arch/blackfin/kernel/flat.c84
-rw-r--r--arch/blackfin/kernel/ftrace-entry.S207
-rw-r--r--arch/blackfin/kernel/ftrace.c125
-rw-r--r--arch/blackfin/kernel/gptimers.c383
-rw-r--r--arch/blackfin/kernel/ipipe.c397
-rw-r--r--arch/blackfin/kernel/irqchip.c132
-rw-r--r--arch/blackfin/kernel/kgdb.c473
-rw-r--r--arch/blackfin/kernel/kgdb_test.c114
-rw-r--r--arch/blackfin/kernel/module.c292
-rw-r--r--arch/blackfin/kernel/nmi.c287
-rw-r--r--arch/blackfin/kernel/perf_event.c482
-rw-r--r--arch/blackfin/kernel/process.c438
-rw-r--r--arch/blackfin/kernel/pseudodbg.c191
-rw-r--r--arch/blackfin/kernel/ptrace.c413
-rw-r--r--arch/blackfin/kernel/reboot.c115
-rw-r--r--arch/blackfin/kernel/setup.c1468
-rw-r--r--arch/blackfin/kernel/shadow_console.c111
-rw-r--r--arch/blackfin/kernel/signal.c287
-rw-r--r--arch/blackfin/kernel/stacktrace.c54
-rw-r--r--arch/blackfin/kernel/sys_bfin.c88
-rw-r--r--arch/blackfin/kernel/time-ts.c400
-rw-r--r--arch/blackfin/kernel/time.c160
-rw-r--r--arch/blackfin/kernel/trace.c988
-rw-r--r--arch/blackfin/kernel/traps.c585
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S271
-rw-r--r--arch/blackfin/lib/Makefile12
-rw-r--r--arch/blackfin/lib/ashldi3.c35
-rw-r--r--arch/blackfin/lib/ashrdi3.c36
-rw-r--r--arch/blackfin/lib/divsi3.S199
-rw-r--r--arch/blackfin/lib/gcclib.h24
-rw-r--r--arch/blackfin/lib/ins.S118
-rw-r--r--arch/blackfin/lib/lshrdi3.c35
-rw-r--r--arch/blackfin/lib/memchr.S47
-rw-r--r--arch/blackfin/lib/memcmp.S92
-rw-r--r--arch/blackfin/lib/memcpy.S124
-rw-r--r--arch/blackfin/lib/memmove.S93
-rw-r--r--arch/blackfin/lib/memset.S87
-rw-r--r--arch/blackfin/lib/modsi3.S57
-rw-r--r--arch/blackfin/lib/muldi3.S74
-rw-r--r--arch/blackfin/lib/outs.S68
-rw-r--r--arch/blackfin/lib/smulsi3_highpart.S38
-rw-r--r--arch/blackfin/lib/strcmp.S43
-rw-r--r--arch/blackfin/lib/strcpy.S35
-rw-r--r--arch/blackfin/lib/strncmp.S52
-rw-r--r--arch/blackfin/lib/strncpy.S85
-rw-r--r--arch/blackfin/lib/udivsi3.S277
-rw-r--r--arch/blackfin/lib/umodsi3.S49
-rw-r--r--arch/blackfin/lib/umulsi3_highpart.S31
-rw-r--r--arch/blackfin/mach-bf518/Kconfig320
-rw-r--r--arch/blackfin/mach-bf518/Makefile5
-rw-r--r--arch/blackfin/mach-bf518/boards/Kconfig18
-rw-r--r--arch/blackfin/mach-bf518/boards/Makefile6
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c794
-rw-r--r--arch/blackfin/mach-bf518/boards/tcm-bf518.c739
-rw-r--r--arch/blackfin/mach-bf518/dma.c98
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h170
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bf518.h214
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf518/include/mach/blackfin.h43
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF512.h1043
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF514.h80
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF516.h178
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF518.h56
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF512.h1304
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h48
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF516.h392
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF518.h67
-rw-r--r--arch/blackfin/mach-bf518/include/mach/dma.h33
-rw-r--r--arch/blackfin/mach-bf518/include/mach/gpio.h62
-rw-r--r--arch/blackfin/mach-bf518/include/mach/irq.h205
-rw-r--r--arch/blackfin/mach-bf518/include/mach/mem_map.h70
-rw-r--r--arch/blackfin/mach-bf518/include/mach/pll.h1
-rw-r--r--arch/blackfin/mach-bf518/include/mach/portmux.h223
-rw-r--r--arch/blackfin/mach-bf518/ints-priority.c78
-rw-r--r--arch/blackfin/mach-bf527/Kconfig325
-rw-r--r--arch/blackfin/mach-bf527/Makefile5
-rw-r--r--arch/blackfin/mach-bf527/boards/Kconfig38
-rw-r--r--arch/blackfin/mach-bf527/boards/Makefile11
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c868
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c992
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c891
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c1335
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c946
-rw-r--r--arch/blackfin/mach-bf527/dma.c98
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h290
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bf527.h237
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial.h14
-rw-r--r--arch/blackfin/mach-bf527/include/mach/blackfin.h37
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF522.h1095
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF525.h421
-rw-r--r--arch/blackfin/mach-bf527/include/mach/cdefBF527.h178
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h1309
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF525.h678
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF527.h391
-rw-r--r--arch/blackfin/mach-bf527/include/mach/dma.h38
-rw-r--r--arch/blackfin/mach-bf527/include/mach/gpio.h69
-rw-r--r--arch/blackfin/mach-bf527/include/mach/irq.h204
-rw-r--r--arch/blackfin/mach-bf527/include/mach/mem_map.h70
-rw-r--r--arch/blackfin/mach-bf527/include/mach/pll.h1
-rw-r--r--arch/blackfin/mach-bf527/include/mach/portmux.h220
-rw-r--r--arch/blackfin/mach-bf527/ints-priority.c79
-rw-r--r--arch/blackfin/mach-bf533/Kconfig96
-rw-r--r--arch/blackfin/mach-bf533/Makefile5
-rw-r--r--arch/blackfin/mach-bf533/boards/H8606.c452
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-rw-r--r--arch/x86/mm/dump_pagetables.c125
-rw-r--r--arch/x86/mm/fault.c67
-rw-r--r--arch/x86/mm/ident_map.c2
-rw-r--r--arch/x86/mm/init_64.c92
-rw-r--r--arch/x86/mm/kasan_init_64.c20
-rw-r--r--arch/x86/mm/kaslr.c29
-rw-r--r--arch/x86/mm/mem_encrypt.c668
-rw-r--r--arch/x86/mm/mem_encrypt_identity.c564
-rw-r--r--arch/x86/mm/numa_32.c11
-rw-r--r--arch/x86/mm/pgtable.c48
-rw-r--r--arch/x86/mm/pti.c2
-rw-r--r--arch/x86/mm/tlb.c4
-rw-r--r--arch/x86/net/bpf_jit_comp.c3
-rw-r--r--arch/x86/pci/acpi.c8
-rw-r--r--arch/x86/pci/direct.c5
-rw-r--r--arch/x86/pci/legacy.c4
-rw-r--r--arch/x86/pci/mmconfig-shared.c13
-rw-r--r--arch/x86/pci/sta2x11-fixup.c52
-rw-r--r--arch/x86/platform/atom/punit_atom_debug.c17
-rw-r--r--arch/x86/platform/efi/efi_64.c68
-rw-r--r--arch/x86/platform/efi/efi_thunk_64.S2
-rw-r--r--arch/x86/platform/efi/quirks.c10
-rw-r--r--arch/x86/platform/intel-mid/intel-mid.c6
-rw-r--r--arch/x86/platform/intel-quark/imr.c24
-rw-r--r--arch/x86/platform/uv/tlb_uv.c2
-rw-r--r--arch/x86/power/hibernate_64.c6
-rw-r--r--arch/x86/purgatory/Makefile2
-rw-r--r--arch/x86/um/asm/barrier.h4
-rw-r--r--arch/x86/xen/Kconfig5
-rw-r--r--arch/x86/xen/apic.c2
-rw-r--r--arch/x86/xen/enlighten_pvh.c14
-rw-r--r--arch/x86/xen/mmu_pv.c21
-rw-r--r--arch/xtensa/include/asm/io.h1
-rw-r--r--arch/xtensa/kernel/syscall.c2
2589 files changed, 16194 insertions, 417469 deletions
diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h
index 8a2b331e43fe..6c7c39452471 100644
--- a/arch/alpha/include/asm/cmpxchg.h
+++ b/arch/alpha/include/asm/cmpxchg.h
@@ -38,19 +38,31 @@
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
#include <asm/xchg.h>
+/*
+ * The leading and the trailing memory barriers guarantee that these
+ * operations are fully ordered.
+ */
#define xchg(ptr, x) \
({ \
+ __typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) _x_ = (x); \
- (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \
- sizeof(*(ptr))); \
+ smp_mb(); \
+ __ret = (__typeof__(*(ptr))) \
+ __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
+ smp_mb(); \
+ __ret; \
})
#define cmpxchg(ptr, o, n) \
({ \
+ __typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
- (unsigned long)_n_, sizeof(*(ptr)));\
+ smp_mb(); \
+ __ret = (__typeof__(*(ptr))) __cmpxchg((ptr), \
+ (unsigned long)_o_, (unsigned long)_n_, sizeof(*(ptr)));\
+ smp_mb(); \
+ __ret; \
})
#define cmpxchg64(ptr, o, n) \
diff --git a/arch/alpha/include/asm/xchg.h b/arch/alpha/include/asm/xchg.h
index e2b59fac5257..7adb80c6746a 100644
--- a/arch/alpha/include/asm/xchg.h
+++ b/arch/alpha/include/asm/xchg.h
@@ -12,10 +12,6 @@
* Atomic exchange.
* Since it can be used to implement critical sections
* it must clobber "memory" (also for interrupts in UP).
- *
- * The leading and the trailing memory barriers guarantee that these
- * operations are fully ordered.
- *
*/
static inline unsigned long
@@ -23,7 +19,6 @@ ____xchg(_u8, volatile char *m, unsigned long val)
{
unsigned long ret, tmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %4,7,%3\n"
" insbl %1,%4,%1\n"
@@ -38,7 +33,6 @@ ____xchg(_u8, volatile char *m, unsigned long val)
".previous"
: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
: "r" ((long)m), "1" (val) : "memory");
- smp_mb();
return ret;
}
@@ -48,7 +42,6 @@ ____xchg(_u16, volatile short *m, unsigned long val)
{
unsigned long ret, tmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %4,7,%3\n"
" inswl %1,%4,%1\n"
@@ -63,7 +56,6 @@ ____xchg(_u16, volatile short *m, unsigned long val)
".previous"
: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
: "r" ((long)m), "1" (val) : "memory");
- smp_mb();
return ret;
}
@@ -73,7 +65,6 @@ ____xchg(_u32, volatile int *m, unsigned long val)
{
unsigned long dummy;
- smp_mb();
__asm__ __volatile__(
"1: ldl_l %0,%4\n"
" bis $31,%3,%1\n"
@@ -84,7 +75,6 @@ ____xchg(_u32, volatile int *m, unsigned long val)
".previous"
: "=&r" (val), "=&r" (dummy), "=m" (*m)
: "rI" (val), "m" (*m) : "memory");
- smp_mb();
return val;
}
@@ -94,7 +84,6 @@ ____xchg(_u64, volatile long *m, unsigned long val)
{
unsigned long dummy;
- smp_mb();
__asm__ __volatile__(
"1: ldq_l %0,%4\n"
" bis $31,%3,%1\n"
@@ -105,7 +94,6 @@ ____xchg(_u64, volatile long *m, unsigned long val)
".previous"
: "=&r" (val), "=&r" (dummy), "=m" (*m)
: "rI" (val), "m" (*m) : "memory");
- smp_mb();
return val;
}
@@ -135,13 +123,6 @@ ____xchg(, volatile void *ptr, unsigned long x, int size)
* Atomic compare and exchange. Compare OLD with MEM, if identical,
* store NEW in MEM. Return the initial value in MEM. Success is
* indicated by comparing RETURN with OLD.
- *
- * The leading and the trailing memory barriers guarantee that these
- * operations are fully ordered.
- *
- * The trailing memory barrier is placed in SMP unconditionally, in
- * order to guarantee that dependency ordering is preserved when a
- * dependency is headed by an unsuccessful operation.
*/
static inline unsigned long
@@ -149,7 +130,6 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
{
unsigned long prev, tmp, cmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %5,7,%4\n"
" insbl %1,%5,%1\n"
@@ -167,7 +147,6 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
".previous"
: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
: "r" ((long)m), "Ir" (old), "1" (new) : "memory");
- smp_mb();
return prev;
}
@@ -177,7 +156,6 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
{
unsigned long prev, tmp, cmp, addr64;
- smp_mb();
__asm__ __volatile__(
" andnot %5,7,%4\n"
" inswl %1,%5,%1\n"
@@ -195,7 +173,6 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
".previous"
: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
: "r" ((long)m), "Ir" (old), "1" (new) : "memory");
- smp_mb();
return prev;
}
@@ -205,7 +182,6 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
{
unsigned long prev, cmp;
- smp_mb();
__asm__ __volatile__(
"1: ldl_l %0,%5\n"
" cmpeq %0,%3,%1\n"
@@ -219,7 +195,6 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
".previous"
: "=&r"(prev), "=&r"(cmp), "=m"(*m)
: "r"((long) old), "r"(new), "m"(*m) : "memory");
- smp_mb();
return prev;
}
@@ -229,7 +204,6 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
{
unsigned long prev, cmp;
- smp_mb();
__asm__ __volatile__(
"1: ldq_l %0,%5\n"
" cmpeq %0,%3,%1\n"
@@ -243,7 +217,6 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
".previous"
: "=&r"(prev), "=&r"(cmp), "=m"(*m)
: "r"((long) old), "r"(new), "m"(*m) : "memory");
- smp_mb();
return prev;
}
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index fa1a392ca9a2..89faa6f4de47 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -189,7 +189,7 @@ SYSCALL_DEFINE6(osf_mmap, unsigned long, addr, unsigned long, len,
goto out;
if (off & ~PAGE_MASK)
goto out;
- ret = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ ret = ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
out:
return ret;
}
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index a1f6bc7f1e4c..5613aa378a83 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -351,7 +351,7 @@ static int collect_events(struct perf_event *group, int max_count,
evtype[n] = group->hw.event_base;
current_idx[n++] = PMC_NO_INDEX;
}
- list_for_each_entry(pe, &group->sibling_list, group_entry) {
+ for_each_sibling_event(pe, group) {
if (!is_software_event(pe) && pe->state != PERF_EVENT_STATE_OFF) {
if (n >= max_count)
return -1;
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 78a647080ebc..199ebc1c4538 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -22,6 +22,7 @@ config ARM_PTDUMP_DEBUGFS
config DEBUG_WX
bool "Warn on W+X mappings at boot"
+ depends on MMU
select ARM_PTDUMP_CORE
---help---
Generate a warning if any W+X mappings are found at boot.
diff --git a/arch/arm/boot/deflate_xip_data.sh b/arch/arm/boot/deflate_xip_data.sh
index 1189598a25eb..5e7d758ebdd6 100755
--- a/arch/arm/boot/deflate_xip_data.sh
+++ b/arch/arm/boot/deflate_xip_data.sh
@@ -30,7 +30,7 @@ esac
sym_val() {
# extract hex value for symbol in $1
- local val=$($NM "$VMLINUX" | sed -n "/ $1$/{s/ .*$//p;q}")
+ local val=$($NM "$VMLINUX" 2>/dev/null | sed -n "/ $1\$/{s/ .*$//p;q}")
[ "$val" ] || { echo "can't find $1 in $VMLINUX" 1>&2; exit 1; }
# convert from hex to decimal
echo $((0x$val))
@@ -48,12 +48,12 @@ data_end=$(($_edata_loc - $base_offset))
file_end=$(stat -c "%s" "$XIPIMAGE")
if [ "$file_end" != "$data_end" ]; then
printf "end of xipImage doesn't match with _edata_loc (%#x vs %#x)\n" \
- $(($file_end + $base_offset)) $_edata_loc 2>&1
+ $(($file_end + $base_offset)) $_edata_loc 1>&2
exit 1;
fi
# be ready to clean up
-trap 'rm -f "$XIPIMAGE.tmp"' 0 1 2 3
+trap 'rm -f "$XIPIMAGE.tmp"; exit 1' 1 2 3
# substitute the data section by a compressed version
$DD if="$XIPIMAGE" count=$data_start iflag=count_bytes of="$XIPIMAGE.tmp"
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b0d8431a3700..ae2b8c952e80 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -42,6 +42,11 @@
};
};
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0>;
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 40de3b66c33f..2477ebc11d9d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -42,6 +42,11 @@
};
};
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>;
+ };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index a7a5dc7b2700..e7d2db839d70 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -82,7 +82,7 @@
enable-active-high;
};
- reg_usb_otg2_vbus: regulator-usb-otg1-vbus {
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 6102e4e7f35c..354aff45c1af 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -927,6 +927,7 @@
i2s: i2s@ff890000 {
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x10000>;
+ #sound-dai-cells = <0>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1176,6 +1177,7 @@
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>;
reg-io-width = <4>;
+ #sound-dai-cells = <0>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..b2758dd8ce43 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -42,7 +42,6 @@
/dts-v1/;
#include "sun6i-a31s.dtsi"
-#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
@@ -99,6 +98,7 @@
pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>;
phy = <&phy1>;
phy-mode = "rgmii";
+ phy-supply = <&reg_dldo1>;
snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
snps,reset-active-low;
snps,reset-delays-us = <0 10000 30000>;
@@ -118,7 +118,7 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
- vmmc-supply = <&reg_vcc3v0>;
+ vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
cd-inverted;
@@ -132,7 +132,7 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_a>;
- vmmc-supply = <&reg_vcc3v0>;
+ vmmc-supply = <&reg_aldo1>;
mmc-pwrseq = <&mmc2_pwrseq>;
bus-width = <4>;
non-removable;
@@ -163,6 +163,8 @@
reg = <0x68>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ eldoin-supply = <&reg_dcdc1>;
+ x-powers,drive-vbus-en;
};
};
@@ -193,7 +195,28 @@
#include "axp22x.dtsi"
+&reg_aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-gmac";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
&reg_dc5ldo {
+ regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd-cpus";
@@ -233,6 +256,40 @@
regulator-name = "vcc-dram";
};
+&reg_dldo1 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-mac";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-csi";
+};
+
+&reg_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pb";
+};
+
+&reg_eldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vdd-csi";
+ status = "okay";
+};
+
+&reg_ldo_io1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pm-cpus";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/include/asm/dma-direct.h b/arch/arm/include/asm/dma-direct.h
index 5b0a8a421894..b67e5fc1fe43 100644
--- a/arch/arm/include/asm/dma-direct.h
+++ b/arch/arm/include/asm/dma-direct.h
@@ -2,13 +2,13 @@
#ifndef ASM_ARM_DMA_DIRECT_H
#define ASM_ARM_DMA_DIRECT_H 1
-static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
unsigned int offset = paddr & ~PAGE_MASK;
return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset;
}
-static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
+static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dev_addr)
{
unsigned int offset = dev_addr & ~PAGE_MASK;
return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset;
diff --git a/arch/arm/include/asm/vdso.h b/arch/arm/include/asm/vdso.h
index 9c99e817535e..5b85889f82ee 100644
--- a/arch/arm/include/asm/vdso.h
+++ b/arch/arm/include/asm/vdso.h
@@ -12,8 +12,6 @@ struct mm_struct;
void arm_install_vdso(struct mm_struct *mm, unsigned long addr);
-extern char vdso_start, vdso_end;
-
extern unsigned int vdso_total_pages;
#else /* CONFIG_VDSO */
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 3151f5623d0e..bdf7514204ab 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -35,5 +35,5 @@
asmlinkage long sys_arm_fadvise64_64(int fd, int advice,
loff_t offset, loff_t len)
{
- return sys_fadvise64_64(fd, offset, len, advice);
+ return ksys_fadvise64_64(fd, offset, len, advice);
}
diff --git a/arch/arm/kernel/vdso.c b/arch/arm/kernel/vdso.c
index a4d6dc0f2427..f4dd7f9663c1 100644
--- a/arch/arm/kernel/vdso.c
+++ b/arch/arm/kernel/vdso.c
@@ -39,6 +39,8 @@
static struct page **vdso_text_pagelist;
+extern char vdso_start[], vdso_end[];
+
/* Total number of pages needed for the data and text portions of the VDSO. */
unsigned int vdso_total_pages __ro_after_init;
@@ -197,13 +199,13 @@ static int __init vdso_init(void)
unsigned int text_pages;
int i;
- if (memcmp(&vdso_start, "\177ELF", 4)) {
+ if (memcmp(vdso_start, "\177ELF", 4)) {
pr_err("VDSO is not a valid ELF object!\n");
return -ENOEXEC;
}
- text_pages = (&vdso_end - &vdso_start) >> PAGE_SHIFT;
- pr_debug("vdso: %i text pages at base %p\n", text_pages, &vdso_start);
+ text_pages = (vdso_end - vdso_start) >> PAGE_SHIFT;
+ pr_debug("vdso: %i text pages at base %p\n", text_pages, vdso_start);
/* Allocate the VDSO text pagelist */
vdso_text_pagelist = kcalloc(text_pages, sizeof(struct page *),
@@ -218,7 +220,7 @@ static int __init vdso_init(void)
for (i = 0; i < text_pages; i++) {
struct page *page;
- page = virt_to_page(&vdso_start + i * PAGE_SIZE);
+ page = virt_to_page(vdso_start + i * PAGE_SIZE);
vdso_text_pagelist[i] = page;
}
@@ -229,7 +231,7 @@ static int __init vdso_init(void)
cntvct_ok = cntvct_functional();
- patch_vdso(&vdso_start);
+ patch_vdso(vdso_start);
return 0;
}
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index a3e78074be70..62eb7d668890 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -127,8 +127,8 @@ static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/
- GPIO_LOOKUP("davinci_gpio.1", 28, "cd", GPIO_ACTIVE_LOW),
- GPIO_LOOKUP("davinci_gpio.1", 29, "wp", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("davinci_gpio.0", 28, "cd", GPIO_ACTIVE_LOW),
+ GPIO_LOOKUP("davinci_gpio.0", 29, "wp", GPIO_ACTIVE_LOW),
},
};
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index 5fb1d2254b5e..04b3bf71de94 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -269,7 +269,7 @@ static bool mmdc_pmu_group_is_valid(struct perf_event *event)
return false;
}
- list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+ for_each_sibling_event(sibling, leader) {
if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask))
return false;
}
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 7e5d7a083707..36cd23c8be9b 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -133,6 +133,9 @@ static void __init u8500_init_machine(void)
if (of_machine_is_compatible("st-ericsson,u8540"))
of_platform_populate(NULL, u8500_local_bus_nodes,
u8540_auxdata_lookup, NULL);
+ else
+ of_platform_populate(NULL, u8500_local_bus_nodes,
+ NULL, NULL);
}
static const char * stericsson_dt_platform_compat[] = {
diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c
index 0a1e2280141f..afe5b4c7b164 100644
--- a/arch/arm/mm/cache-l2x0-pmu.c
+++ b/arch/arm/mm/cache-l2x0-pmu.c
@@ -293,7 +293,7 @@ static bool l2x0_pmu_group_is_valid(struct perf_event *event)
else if (!is_software_event(leader))
return false;
- list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+ for_each_sibling_event(sibling, leader) {
if (sibling->pmu == pmu)
num_hw++;
else if (!is_software_event(sibling))
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index d443e481c3e9..8805a59bae53 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -888,11 +888,8 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
timer->irq = irq->start;
timer->pdev = pdev;
- /* Skip pm_runtime_enable for OMAP1 */
- if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
- pm_runtime_enable(dev);
- pm_runtime_irq_safe(dev);
- }
+ pm_runtime_enable(dev);
+ pm_runtime_irq_safe(dev);
if (!timer->reserved) {
ret = pm_runtime_get_sync(dev);
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index fb061cf0d736..30a07730807a 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -5,13 +5,4 @@ void omap_map_sram(unsigned long start, unsigned long size,
unsigned long skip, int cached);
void omap_sram_reset(void);
-extern void *omap_sram_push_address(unsigned long size);
-
-/* Macro to push a function to the internal SRAM, using the fncpy API */
-#define omap_sram_push(funcp, size) ({ \
- typeof(&(funcp)) _res = NULL; \
- void *_sram_address = omap_sram_push_address(size); \
- if (_sram_address) \
- _res = fncpy(_sram_address, &(funcp), size); \
- _res; \
-})
+extern void *omap_sram_push(void *funcp, unsigned long size);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index a5bc92d7e476..921840acf65c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -23,6 +23,7 @@
#include <asm/fncpy.h>
#include <asm/tlb.h>
#include <asm/cacheflush.h>
+#include <asm/set_memory.h>
#include <asm/mach/map.h>
@@ -42,7 +43,7 @@ static void __iomem *omap_sram_ceil;
* Note that fncpy requires the returned address to be aligned
* to an 8-byte boundary.
*/
-void *omap_sram_push_address(unsigned long size)
+static void *omap_sram_push_address(unsigned long size)
{
unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
@@ -60,6 +61,30 @@ void *omap_sram_push_address(unsigned long size)
return (void *)omap_sram_ceil;
}
+void *omap_sram_push(void *funcp, unsigned long size)
+{
+ void *sram;
+ unsigned long base;
+ int pages;
+ void *dst = NULL;
+
+ sram = omap_sram_push_address(size);
+ if (!sram)
+ return NULL;
+
+ base = (unsigned long)sram & PAGE_MASK;
+ pages = PAGE_ALIGN(size) / PAGE_SIZE;
+
+ set_memory_rw(base, pages);
+
+ dst = fncpy(sram, funcp, size);
+
+ set_memory_ro(base, pages);
+ set_memory_x(base, pages);
+
+ return dst;
+}
+
/*
* The SRAM context is lost during off-idle and stack
* needs to be reset.
@@ -75,6 +100,9 @@ void omap_sram_reset(void)
void __init omap_map_sram(unsigned long start, unsigned long size,
unsigned long skip, int cached)
{
+ unsigned long base;
+ int pages;
+
if (size == 0)
return;
@@ -95,4 +123,10 @@ void __init omap_map_sram(unsigned long start, unsigned long size,
*/
memset_io(omap_sram_base + omap_sram_skip, 0,
omap_sram_size - omap_sram_skip);
+
+ base = (unsigned long)omap_sram_base;
+ pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE;
+
+ set_memory_ro(base, pages);
+ set_memory_x(base, pages);
}
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 03c6a3c72f9c..4c375e11ae95 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -648,7 +648,7 @@ int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
*/
static int vfp_dying_cpu(unsigned int cpu)
{
- vfp_force_reload(cpu, current_thread_info());
+ vfp_current_hw_state[cpu] = NULL;
return 0;
}
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 03f195025390..204bdb9857b9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -406,8 +406,9 @@
wlan_pd_n: wlan-pd-n {
compatible = "regulator-fixed";
regulator-name = "wlan_pd_n";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wlan_module_reset_l>;
- /* Note the wlan_module_reset_l pinctrl */
enable-active-high;
gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
@@ -983,12 +984,6 @@ ap_i2c_audio: &i2c8 {
pinctrl-0 = <
&ap_pwroff /* AP will auto-assert this when in S3 */
&clk_32k /* This pin is always 32k on gru boards */
-
- /*
- * We want this driven low ASAP; firmware should help us, but
- * we can help ourselves too.
- */
- &wlan_module_reset_l
>;
pcfg_output_low: pcfg-output-low {
@@ -1168,12 +1163,7 @@ ap_i2c_audio: &i2c8 {
};
wlan_module_reset_l: wlan-module-reset-l {
- /*
- * We want this driven low ASAP (As {Soon,Strongly} As
- * Possible), to avoid leakage through the powered-down
- * WiFi.
- */
- rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_output_low>;
+ rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_host_wake_l: bt-host-wake-l {
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 2605118d4b4c..0b81ca1d07e7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -411,8 +411,8 @@
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy0_otg>, <&tcphy0_usb3>;
- phy-names = "usb2-phy", "usb3-phy";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -444,8 +444,8 @@
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy1_otg>, <&tcphy1_usb3>;
- phy-names = "usb2-phy", "usb3-phy";
+ phys = <&u2phy1_otg>;
+ phy-names = "usb2-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h
index 8389050328bb..192d791f1103 100644
--- a/arch/arm64/include/asm/efi.h
+++ b/arch/arm64/include/asm/efi.h
@@ -31,7 +31,7 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md);
({ \
efi_##f##_t *__f; \
__f = p->f; \
- __f(args); \
+ __efi_rt_asm_wrapper(__f, #f, args); \
})
#define arch_efi_call_virt_teardown() \
@@ -40,6 +40,8 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md);
efi_virtmap_unload(); \
})
+efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...);
+
#define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
/* arch specific definitions used by the stub code */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index b87541360f43..6a4bd80c75bd 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -38,7 +38,8 @@ arm64-obj-$(CONFIG_CPU_PM) += sleep.o suspend.o
arm64-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
arm64-obj-$(CONFIG_KGDB) += kgdb.o
-arm64-obj-$(CONFIG_EFI) += efi.o efi-entry.stub.o
+arm64-obj-$(CONFIG_EFI) += efi.o efi-entry.stub.o \
+ efi-rt-wrapper.o
arm64-obj-$(CONFIG_PCI) += pci.o
arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o
arm64-obj-$(CONFIG_ACPI) += acpi.o
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 52f15cd896e1..b5a28336c077 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -178,7 +178,7 @@ static int enable_smccc_arch_workaround_1(void *data)
case PSCI_CONDUIT_HVC:
arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
- if (res.a0)
+ if ((int)res.a0 < 0)
return 0;
cb = call_hvc_arch_workaround_1;
smccc_start = __smccc_workaround_1_hvc_start;
@@ -188,7 +188,7 @@ static int enable_smccc_arch_workaround_1(void *data)
case PSCI_CONDUIT_SMC:
arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
ARM_SMCCC_ARCH_WORKAROUND_1, &res);
- if (res.a0)
+ if ((int)res.a0 < 0)
return 0;
cb = call_smc_arch_workaround_1;
smccc_start = __smccc_workaround_1_smc_start;
diff --git a/arch/arm64/kernel/efi-rt-wrapper.S b/arch/arm64/kernel/efi-rt-wrapper.S
new file mode 100644
index 000000000000..05235ebb336d
--- /dev/null
+++ b/arch/arm64/kernel/efi-rt-wrapper.S
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(__efi_rt_asm_wrapper)
+ stp x29, x30, [sp, #-32]!
+ mov x29, sp
+
+ /*
+ * Register x18 is designated as the 'platform' register by the AAPCS,
+ * which means firmware running at the same exception level as the OS
+ * (such as UEFI) should never touch it.
+ */
+ stp x1, x18, [sp, #16]
+
+ /*
+ * We are lucky enough that no EFI runtime services take more than
+ * 5 arguments, so all are passed in registers rather than via the
+ * stack.
+ */
+ mov x8, x0
+ mov x0, x2
+ mov x1, x3
+ mov x2, x4
+ mov x3, x5
+ mov x4, x6
+ blr x8
+
+ ldp x1, x2, [sp, #16]
+ cmp x2, x18
+ ldp x29, x30, [sp], #32
+ b.ne 0f
+ ret
+0: b efi_handle_corrupted_x18 // tail call
+ENDPROC(__efi_rt_asm_wrapper)
diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c
index a8bf1c892b90..4f9acb5fbe97 100644
--- a/arch/arm64/kernel/efi.c
+++ b/arch/arm64/kernel/efi.c
@@ -126,3 +126,9 @@ bool efi_poweroff_required(void)
{
return efi_enabled(EFI_RUNTIME_SERVICES);
}
+
+asmlinkage efi_status_t efi_handle_corrupted_x18(efi_status_t s, const char *f)
+{
+ pr_err_ratelimited(FW_BUG "register x18 corrupted by EFI %s\n", f);
+ return s;
+}
diff --git a/arch/arm64/kernel/sys.c b/arch/arm64/kernel/sys.c
index 26fe8ea93ea2..72981bae10eb 100644
--- a/arch/arm64/kernel/sys.c
+++ b/arch/arm64/kernel/sys.c
@@ -34,7 +34,7 @@ asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
if (offset_in_page(off) != 0)
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
}
SYSCALL_DEFINE1(arm64_personality, unsigned int, personality)
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index d7e3299a7734..959e50d2588c 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -363,8 +363,6 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
{
int ret = 0;
- vcpu_load(vcpu);
-
trace_kvm_set_guest_debug(vcpu, dbg->control);
if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) {
@@ -386,7 +384,6 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
}
out:
- vcpu_put(vcpu);
return ret;
}
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 84a019f55022..2dbb2c9f1ec1 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -108,7 +108,7 @@ static bool pgattr_change_is_safe(u64 old, u64 new)
* The following mapping attributes may be updated in live
* kernel mappings without the need for break-before-make.
*/
- static const pteval_t mask = PTE_PXN | PTE_RDONLY | PTE_WRITE;
+ static const pteval_t mask = PTE_PXN | PTE_RDONLY | PTE_WRITE | PTE_NG;
/* creating or taking down mappings is always safe */
if (old == 0 || new == 0)
@@ -118,9 +118,9 @@ static bool pgattr_change_is_safe(u64 old, u64 new)
if ((old | new) & PTE_CONT)
return false;
- /* Transitioning from Global to Non-Global is safe */
- if (((old ^ new) == PTE_NG) && (new & PTE_NG))
- return true;
+ /* Transitioning from Non-Global to Global is unsafe */
+ if (old & ~new & PTE_NG)
+ return false;
return ((old ^ new) & ~mask) == 0;
}
@@ -972,3 +972,13 @@ int pmd_clear_huge(pmd_t *pmdp)
pmd_clear(pmdp);
return 1;
}
+
+int pud_free_pmd_page(pud_t *pud)
+{
+ return pud_none(*pud);
+}
+
+int pmd_free_pte_page(pmd_t *pmd)
+{
+ return pmd_none(*pmd);
+}
diff --git a/arch/blackfin/Clear_BSD.txt b/arch/blackfin/Clear_BSD.txt
deleted file mode 100644
index bfa4b378a368..000000000000
--- a/arch/blackfin/Clear_BSD.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-The Clear BSD license:
-
-Copyright (c) 2012, Analog Devices, Inc. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted (subject to the limitations in the
-disclaimer below) provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the
- distribution.
-
-* Neither the name of Analog Devices, Inc. nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
-NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
-GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
deleted file mode 100644
index d9c2866ba618..000000000000
--- a/arch/blackfin/Kconfig
+++ /dev/null
@@ -1,1463 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config MMU
- def_bool n
-
-config FPU
- def_bool n
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config RWSEM_XCHGADD_ALGORITHM
- def_bool n
-
-config BLACKFIN
- def_bool y
- select HAVE_ARCH_KGDB
- select HAVE_ARCH_TRACEHOOK
- select HAVE_DYNAMIC_FTRACE
- select HAVE_FTRACE_MCOUNT_RECORD
- select HAVE_FUNCTION_GRAPH_TRACER
- select HAVE_FUNCTION_TRACER
- select HAVE_IDE
- select HAVE_KERNEL_GZIP if RAMKERNEL
- select HAVE_KERNEL_BZIP2 if RAMKERNEL
- select HAVE_KERNEL_LZMA if RAMKERNEL
- select HAVE_KERNEL_LZO if RAMKERNEL
- select HAVE_OPROFILE
- select HAVE_PERF_EVENTS
- select ARCH_HAVE_CUSTOM_GPIO_H
- select GPIOLIB
- select HAVE_UID16
- select HAVE_UNDERSCORE_SYMBOL_PREFIX
- select VIRT_TO_BUS
- select ARCH_WANT_IPC_PARSE_VERSION
- select GENERIC_ATOMIC64
- select GENERIC_IRQ_PROBE
- select GENERIC_IRQ_SHOW
- select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
- select GENERIC_SMP_IDLE_THREAD
- select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
- select HAVE_MOD_ARCH_SPECIFIC
- select MODULES_USE_ELF_RELA
- select HAVE_DEBUG_STACKOVERFLOW
- select HAVE_NMI
- select ARCH_NO_COHERENT_DMA_MMAP
-
-config GENERIC_CSUM
- def_bool y
-
-config GENERIC_BUG
- def_bool y
- depends on BUG
-
-config ZONE_DMA
- def_bool y
-
-config FORCE_MAX_ZONEORDER
- int
- default "14"
-
-config GENERIC_CALIBRATE_DELAY
- def_bool y
-
-config LOCKDEP_SUPPORT
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-config TRACE_IRQFLAGS_SUPPORT
- def_bool y
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.preempt"
-
-source "kernel/Kconfig.freezer"
-
-menu "Blackfin Processor Options"
-
-comment "Processor and Board Settings"
-
-choice
- prompt "CPU"
- default BF533
-
-config BF512
- bool "BF512"
- help
- BF512 Processor Support.
-
-config BF514
- bool "BF514"
- help
- BF514 Processor Support.
-
-config BF516
- bool "BF516"
- help
- BF516 Processor Support.
-
-config BF518
- bool "BF518"
- help
- BF518 Processor Support.
-
-config BF522
- bool "BF522"
- help
- BF522 Processor Support.
-
-config BF523
- bool "BF523"
- help
- BF523 Processor Support.
-
-config BF524
- bool "BF524"
- help
- BF524 Processor Support.
-
-config BF525
- bool "BF525"
- help
- BF525 Processor Support.
-
-config BF526
- bool "BF526"
- help
- BF526 Processor Support.
-
-config BF527
- bool "BF527"
- help
- BF527 Processor Support.
-
-config BF531
- bool "BF531"
- help
- BF531 Processor Support.
-
-config BF532
- bool "BF532"
- help
- BF532 Processor Support.
-
-config BF533
- bool "BF533"
- help
- BF533 Processor Support.
-
-config BF534
- bool "BF534"
- help
- BF534 Processor Support.
-
-config BF536
- bool "BF536"
- help
- BF536 Processor Support.
-
-config BF537
- bool "BF537"
- help
- BF537 Processor Support.
-
-config BF538
- bool "BF538"
- help
- BF538 Processor Support.
-
-config BF539
- bool "BF539"
- help
- BF539 Processor Support.
-
-config BF542_std
- bool "BF542"
- help
- BF542 Processor Support.
-
-config BF542M
- bool "BF542m"
- help
- BF542 Processor Support.
-
-config BF544_std
- bool "BF544"
- help
- BF544 Processor Support.
-
-config BF544M
- bool "BF544m"
- help
- BF544 Processor Support.
-
-config BF547_std
- bool "BF547"
- help
- BF547 Processor Support.
-
-config BF547M
- bool "BF547m"
- help
- BF547 Processor Support.
-
-config BF548_std
- bool "BF548"
- help
- BF548 Processor Support.
-
-config BF548M
- bool "BF548m"
- help
- BF548 Processor Support.
-
-config BF549_std
- bool "BF549"
- help
- BF549 Processor Support.
-
-config BF549M
- bool "BF549m"
- help
- BF549 Processor Support.
-
-config BF561
- bool "BF561"
- help
- BF561 Processor Support.
-
-config BF609
- bool "BF609"
- select CLKDEV_LOOKUP
- help
- BF609 Processor Support.
-
-endchoice
-
-config SMP
- depends on BF561
- select TICKSOURCE_CORETMR
- bool "Symmetric multi-processing support"
- ---help---
- This enables support for systems with more than one CPU,
- like the dual core BF561. If you have a system with only one
- CPU, say N. If you have a system with more than one CPU, say Y.
-
- If you don't know what to do here, say N.
-
-config NR_CPUS
- int
- depends on SMP
- default 2 if BF561
-
-config HOTPLUG_CPU
- bool "Support for hot-pluggable CPUs"
- depends on SMP
- default y
-
-config BF_REV_MIN
- int
- default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 2 if (BF537 || BF536 || BF534)
- default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
- default 4 if (BF538 || BF539)
-
-config BF_REV_MAX
- int
- default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
- default 3 if (BF537 || BF536 || BF534 || BF54xM)
- default 5 if (BF561 || BF538 || BF539)
- default 6 if (BF533 || BF532 || BF531)
-
-choice
- prompt "Silicon Rev"
- default BF_REV_0_0 if (BF51x || BF52x || BF60x)
- default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
- default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
-
-config BF_REV_0_0
- bool "0.0"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_1
- bool "0.1"
- depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
-
-config BF_REV_0_2
- bool "0.2"
- depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
-
-config BF_REV_0_3
- bool "0.3"
- depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
-
-config BF_REV_0_4
- bool "0.4"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
-
-config BF_REV_0_5
- bool "0.5"
- depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
-
-config BF_REV_0_6
- bool "0.6"
- depends on (BF533 || BF532 || BF531)
-
-config BF_REV_ANY
- bool "any"
-
-config BF_REV_NONE
- bool "none"
-
-endchoice
-
-config BF53x
- bool
- depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
- default y
-
-config GPIO_ADI
- def_bool y
- depends on !PINCTRL
- depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
-
-config PINCTRL_BLACKFIN_ADI2
- def_bool y
- depends on (BF54x || BF60x)
- select PINCTRL
- select PINCTRL_ADI2
-
-config MEM_MT48LC64M4A2FB_7E
- bool
- depends on (BFIN533_STAMP)
- default y
-
-config MEM_MT48LC16M16A2TG_75
- bool
- depends on (BFIN533_EZKIT || BFIN561_EZKIT \
- || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
- || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
- || BFIN527_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M8A2_75
- bool
- depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
- default y
-
-config MEM_MT48LC8M32B2B5_7
- bool
- depends on (BFIN561_BLUETECHNIX_CM)
- default y
-
-config MEM_MT48LC32M16A2TG_75
- bool
- depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
- default y
-
-config MEM_MT48H32M16LFCJ_75
- bool
- depends on (BFIN526_EZBRD)
- default y
-
-config MEM_MT47H64M16
- bool
- depends on (BFIN609_EZKIT)
- default y
-
-source "arch/blackfin/mach-bf518/Kconfig"
-source "arch/blackfin/mach-bf527/Kconfig"
-source "arch/blackfin/mach-bf533/Kconfig"
-source "arch/blackfin/mach-bf561/Kconfig"
-source "arch/blackfin/mach-bf537/Kconfig"
-source "arch/blackfin/mach-bf538/Kconfig"
-source "arch/blackfin/mach-bf548/Kconfig"
-source "arch/blackfin/mach-bf609/Kconfig"
-
-menu "Board customizations"
-
-config CMDLINE_BOOL
- bool "Default bootloader kernel arguments"
-
-config CMDLINE
- string "Initial kernel command string"
- depends on CMDLINE_BOOL
- default "console=ttyBF0,57600"
- help
- If you don't have a boot loader capable of passing a command line string
- to the kernel, you may specify one here. As a minimum, you should specify
- the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
-
-config BOOT_LOAD
- hex "Kernel load address for booting"
- default "0x1000"
- range 0x1000 0x20000000
- help
- This option allows you to set the load address of the kernel.
- This can be useful if you are on a board which has a small amount
- of memory or you wish to reserve some memory at the beginning of
- the address space.
-
- Note that you need to keep this value above 4k (0x1000) as this
- memory region is used to capture NULL pointer references as well
- as some core kernel functions.
-
-config PHY_RAM_BASE_ADDRESS
- hex "Physical RAM Base"
- default 0x0
- help
- set BF609 FPGA physical SRAM base address
-
-config ROM_BASE
- hex "Kernel ROM Base"
- depends on ROMKERNEL
- default "0x20040040"
- range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
- range 0x20000000 0x30000000 if (BF54x || BF561)
- range 0xB0000000 0xC0000000 if (BF60x)
- help
- Make sure your ROM base does not include any file-header
- information that is prepended to the kernel.
-
- For example, the bootable U-Boot format (created with
- mkimage) has a 64 byte header (0x40). So while the image
- you write to flash might start at say 0x20080000, you have
- to add 0x40 to get the kernel's ROM base as it will come
- after the header.
-
-comment "Clock/PLL Setup"
-
-config CLKIN_HZ
- int "Frequency of the crystal on the board in Hz"
- default "10000000" if BFIN532_IP0X
- default "11059200" if BFIN533_STAMP
- default "24576000" if PNAV10
- default "25000000" # most people use this
- default "27000000" if BFIN533_EZKIT
- default "30000000" if BFIN561_EZKIT
- default "24000000" if BFIN527_AD7160EVAL
- help
- The frequency of CLKIN crystal oscillator on the board in Hz.
- Warning: This value should match the crystal on the board. Otherwise,
- peripherals won't work properly.
-
-config BFIN_KERNEL_CLOCK
- bool "Re-program Clocks while Kernel boots?"
- default n
- help
- This option decides if kernel clocks are re-programed from the
- bootloader settings. If the clocks are not set, the SDRAM settings
- are also not changed, and the Bootloader does 100% of the hardware
- configuration.
-
-config PLL_BYPASS
- bool "Bypass PLL"
- depends on BFIN_KERNEL_CLOCK && (!BF60x)
- default n
-
-config CLKIN_HALF
- bool "Half Clock In"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- default n
- help
- If this is set the clock will be divided by 2, before it goes to the PLL.
-
-config VCO_MULT
- int "VCO Multiplier"
- depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
- range 1 64
- default "22" if BFIN533_EZKIT
- default "45" if BFIN533_STAMP
- default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
- default "22" if BFIN533_BLUETECHNIX_CM
- default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
- default "20" if (BFIN561_EZKIT || BF609)
- default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
- default "25" if BFIN527_AD7160EVAL
- help
- This controls the frequency of the on-chip PLL. This can be between 1 and 64.
- PLL Frequency = (Crystal Frequency) * (this setting)
-
-choice
- prompt "Core Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- default CCLK_DIV_1
- help
- This sets the frequency of the core. It can be 1, 2, 4 or 8
- Core Frequency = (PLL frequency) / (this setting)
-
-config CCLK_DIV_1
- bool "1"
-
-config CCLK_DIV_2
- bool "2"
-
-config CCLK_DIV_4
- bool "4"
-
-config CCLK_DIV_8
- bool "8"
-endchoice
-
-config SCLK_DIV
- int "System Clock Divider"
- depends on BFIN_KERNEL_CLOCK
- range 1 15
- default 4
- help
- This sets the frequency of the system clock (including SDRAM or DDR) on
- !BF60x else it set the clock for system buses and provides the
- source from which SCLK0 and SCLK1 are derived.
- This can be between 1 and 15
- System Clock = (PLL frequency) / (this setting)
-
-config SCLK0_DIV
- int "System Clock0 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock0 for PVP and all other
- peripherals not clocked by SCLK1.
- This can be between 1 and 15
- System Clock0 = (System Clock) / (this setting)
-
-config SCLK1_DIV
- int "System Clock1 Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 1
- help
- This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
- This can be between 1 and 15
- System Clock1 = (System Clock) / (this setting)
-
-config DCLK_DIV
- int "DDR Clock Divider"
- depends on BFIN_KERNEL_CLOCK && BF60x
- range 1 15
- default 2
- help
- This sets the frequency of the DDR memory.
- This can be between 1 and 15
- DDR Clock = (PLL frequency) / (this setting)
-
-choice
- prompt "DDR SDRAM Chip Type"
- depends on BFIN_KERNEL_CLOCK
- depends on BF54x
- default MEM_MT46V32M16_5B
-
-config MEM_MT46V32M16_6T
- bool "MT46V32M16_6T"
-
-config MEM_MT46V32M16_5B
- bool "MT46V32M16_5B"
-endchoice
-
-choice
- prompt "DDR/SDRAM Timing"
- depends on BFIN_KERNEL_CLOCK && !BF60x
- default BFIN_KERNEL_CLOCK_MEMINIT_CALC
- help
- This option allows you to specify Blackfin SDRAM/DDR Timing parameters
- The calculated SDRAM timing parameters may not be 100%
- accurate - This option is therefore marked experimental.
-
-config BFIN_KERNEL_CLOCK_MEMINIT_CALC
- bool "Calculate Timings"
-
-config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
- bool "Provide accurate Timings based on target SCLK"
- help
- Please consult the Blackfin Hardware Reference Manuals as well
- as the memory device datasheet.
- http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
-endchoice
-
-menu "Memory Init Control"
- depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
-
-config MEM_DDRCTL0
- depends on BF54x
- hex "DDRCTL0"
- default 0x0
-
-config MEM_DDRCTL1
- depends on BF54x
- hex "DDRCTL1"
- default 0x0
-
-config MEM_DDRCTL2
- depends on BF54x
- hex "DDRCTL2"
- default 0x0
-
-config MEM_EBIU_DDRQUE
- depends on BF54x
- hex "DDRQUE"
- default 0x0
-
-config MEM_SDRRC
- depends on !BF54x
- hex "SDRRC"
- default 0x0
-
-config MEM_SDGCTL
- depends on !BF54x
- hex "SDGCTL"
- default 0x0
-endmenu
-
-#
-# Max & Min Speeds for various Chips
-#
-config MAX_VCO_HZ
- int
- default 400000000 if BF512
- default 400000000 if BF514
- default 400000000 if BF516
- default 400000000 if BF518
- default 400000000 if BF522
- default 600000000 if BF523
- default 400000000 if BF524
- default 600000000 if BF525
- default 400000000 if BF526
- default 600000000 if BF527
- default 400000000 if BF531
- default 400000000 if BF532
- default 750000000 if BF533
- default 500000000 if BF534
- default 400000000 if BF536
- default 600000000 if BF537
- default 533333333 if BF538
- default 533333333 if BF539
- default 600000000 if BF542
- default 533333333 if BF544
- default 600000000 if BF547
- default 600000000 if BF548
- default 533333333 if BF549
- default 600000000 if BF561
- default 800000000 if BF609
-
-config MIN_VCO_HZ
- int
- default 50000000
-
-config MAX_SCLK_HZ
- int
- default 200000000 if BF609
- default 133333333
-
-config MIN_SCLK_HZ
- int
- default 27000000
-
-comment "Kernel Timer/Scheduler"
-
-source kernel/Kconfig.hz
-
-config SET_GENERIC_CLOCKEVENTS
- bool "Generic clock events"
- default y
- select GENERIC_CLOCKEVENTS
-
-menu "Clock event device"
- depends on GENERIC_CLOCKEVENTS
-config TICKSOURCE_GPTMR0
- bool "GPTimer0"
- depends on !SMP
- select BFIN_GPTIMERS
-
-config TICKSOURCE_CORETMR
- bool "Core timer"
- default y
-endmenu
-
-menu "Clock source"
- depends on GENERIC_CLOCKEVENTS
-config CYCLES_CLOCKSOURCE
- bool "CYCLES"
- default y
- depends on !BFIN_SCRATCH_REG_CYCLES
- depends on !SMP
- help
- If you say Y here, you will enable support for using the 'cycles'
- registers as a clock source. Doing so means you will be unable to
- safely write to the 'cycles' register during runtime. You will
- still be able to read it (such as for performance monitoring), but
- writing the registers will most likely crash the kernel.
-
-config GPTMR0_CLOCKSOURCE
- bool "GPTimer0"
- select BFIN_GPTIMERS
- depends on !TICKSOURCE_GPTMR0
-endmenu
-
-comment "Misc"
-
-choice
- prompt "Blackfin Exception Scratch Register"
- default BFIN_SCRATCH_REG_RETN
- help
- Select the resource to reserve for the Exception handler:
- - RETN: Non-Maskable Interrupt (NMI)
- - RETE: Exception Return (JTAG/ICE)
- - CYCLES: Performance counter
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETN
- bool "RETN"
- help
- Use the RETN register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use NMI on the Blackfin while running Linux, but
- you can debug the system with a JTAG ICE and use the
- CYCLES performance registers.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_RETE
- bool "RETE"
- help
- Use the RETE register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use a JTAG ICE while debugging a Blackfin board,
- but you can safely use the CYCLES performance registers
- and the NMI.
-
- If you are unsure, please select "RETN".
-
-config BFIN_SCRATCH_REG_CYCLES
- bool "CYCLES"
- help
- Use the CYCLES register in the Blackfin exception handler
- as a stack scratch register. This means you cannot
- safely use the CYCLES performance registers on a Blackfin
- board at anytime, but you can debug the system with a JTAG
- ICE and use the NMI.
-
- If you are unsure, please select "RETN".
-
-endchoice
-
-endmenu
-
-
-menu "Blackfin Kernel Optimizations"
-
-comment "Memory Optimizations"
-
-config I_ENTRY_L1
- bool "Locate interrupt entry code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
- into L1 instruction memory. (less latency)
-
-config EXCPT_IRQ_SYSC_L1
- bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the entire ASM lowlevel exception and interrupt entry code
- (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
- (less latency)
-
-config DO_IRQ_L1
- bool "Locate frequently called do_irq dispatcher function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called do_irq dispatcher function is linked
- into L1 instruction memory. (less latency)
-
-config CORE_TIMER_IRQ_L1
- bool "Locate frequently called timer_interrupt() function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called timer_interrupt() function is linked
- into L1 instruction memory. (less latency)
-
-config IDLE_L1
- bool "Locate frequently idle function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called idle function is linked
- into L1 instruction memory. (less latency)
-
-config SCHEDULE_L1
- bool "Locate kernel schedule function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the frequently called kernel schedule is linked
- into L1 instruction memory. (less latency)
-
-config ARITHMETIC_OPS_L1
- bool "Locate kernel owned arithmetic functions in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, arithmetic functions are linked
- into L1 instruction memory. (less latency)
-
-config ACCESS_OK_L1
- bool "Locate access_ok function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the access_ok function is linked
- into L1 instruction memory. (less latency)
-
-config MEMSET_L1
- bool "Locate memset function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memset function is linked
- into L1 instruction memory. (less latency)
-
-config MEMCPY_L1
- bool "Locate memcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the memcpy function is linked
- into L1 instruction memory. (less latency)
-
-config STRCMP_L1
- bool "locate strcmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcmp function is linked
- into L1 instruction memory (less latency).
-
-config STRNCMP_L1
- bool "locate strncmp function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncmp function is linked
- into L1 instruction memory (less latency).
-
-config STRCPY_L1
- bool "locate strcpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strcpy function is linked
- into L1 instruction memory (less latency).
-
-config STRNCPY_L1
- bool "locate strncpy function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, the strncpy function is linked
- into L1 instruction memory (less latency).
-
-config SYS_BFIN_SPINLOCK_L1
- bool "Locate sys_bfin_spinlock function in L1 Memory"
- default y
- depends on !SMP
- help
- If enabled, sys_bfin_spinlock function is linked
- into L1 instruction memory. (less latency)
-
-config CACHELINE_ALIGNED_L1
- bool "Locate cacheline_aligned data to L1 Data Memory"
- default y if !BF54x
- default n if BF54x
- depends on !SMP && !BF531 && !CRC32
- help
- If enabled, cacheline_aligned data is linked
- into L1 data memory. (less latency)
-
-config SYSCALL_TAB_L1
- bool "Locate Syscall Table L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the Syscall LUT is linked
- into L1 data memory. (less latency)
-
-config CPLB_SWITCH_TAB_L1
- bool "Locate CPLB Switch Tables L1 Data Memory"
- default n
- depends on !SMP && !BF531
- help
- If enabled, the CPLB Switch Tables are linked
- into L1 data memory. (less latency)
-
-config ICACHE_FLUSH_L1
- bool "Locate icache flush funcs in L1 Inst Memory"
- default y
- help
- If enabled, the Blackfin icache flushing functions are linked
- into L1 instruction memory.
-
- Note that this might be required to address anomalies, but
- these functions are pretty small, so it shouldn't be too bad.
- If you are using a processor affected by an anomaly, the build
- system will double check for you and prevent it.
-
-config DCACHE_FLUSH_L1
- bool "Locate dcache flush funcs in L1 Inst Memory"
- default y
- depends on !SMP
- help
- If enabled, the Blackfin dcache flushing functions are linked
- into L1 instruction memory.
-
-config APP_STACK_L1
- bool "Support locating application stack in L1 Scratch Memory"
- default y
- depends on !SMP
- help
- If enabled the application stack can be located in L1
- scratch memory (less latency).
-
- Currently only works with FLAT binaries.
-
-config EXCEPTION_L1_SCRATCH
- bool "Locate exception stack in L1 Scratch Memory"
- default n
- depends on !SMP && !APP_STACK_L1
- help
- Whenever an exception occurs, use the L1 Scratch memory for
- stack storage. You cannot place the stacks of FLAT binaries
- in L1 when using this option.
-
- If you don't use L1 Scratch, then you should say Y here.
-
-comment "Speed Optimizations"
-config BFIN_INS_LOWOVERHEAD
- bool "ins[bwl] low overhead, higher interrupt latency"
- default y
- depends on !SMP
- help
- Reads on the Blackfin are speculative. In Blackfin terms, this means
- they can be interrupted at any time (even after they have been issued
- on to the external bus), and re-issued after the interrupt occurs.
- For memory - this is not a big deal, since memory does not change if
- it sees a read.
-
- If a FIFO is sitting on the end of the read, it will see two reads,
- when the core only sees one since the FIFO receives both the read
- which is cancelled (and not delivered to the core) and the one which
- is re-issued (which is delivered to the core).
-
- To solve this, interrupts are turned off before reads occur to
- I/O space. This option controls which the overhead/latency of
- controlling interrupts during this time
- "n" turns interrupts off every read
- (higher overhead, but lower interrupt latency)
- "y" turns interrupts off every loop
- (low overhead, but longer interrupt latency)
-
- default behavior is to leave this set to on (type "Y"). If you are experiencing
- interrupt latency issues, it is safe and OK to turn this off.
-
-endmenu
-
-choice
- prompt "Kernel executes from"
- help
- Choose the memory type that the kernel will be running in.
-
-config RAMKERNEL
- bool "RAM"
- help
- The kernel will be resident in RAM when running.
-
-config ROMKERNEL
- bool "ROM"
- help
- The kernel will be resident in FLASH/ROM when running.
-
-endchoice
-
-# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
-config XIP_KERNEL
- bool
- default y
- depends on ROMKERNEL
-
-source "mm/Kconfig"
-
-config BFIN_GPTIMERS
- tristate "Enable Blackfin General Purpose Timers API"
- default n
- help
- Enable support for the General Purpose Timers API. If you
- are unsure, say N.
-
- To compile this driver as a module, choose M here: the module
- will be called gptimers.
-
-choice
- prompt "Uncached DMA region"
- default DMA_UNCACHED_1M
-config DMA_UNCACHED_32M
- bool "Enable 32M DMA region"
-config DMA_UNCACHED_16M
- bool "Enable 16M DMA region"
-config DMA_UNCACHED_8M
- bool "Enable 8M DMA region"
-config DMA_UNCACHED_4M
- bool "Enable 4M DMA region"
-config DMA_UNCACHED_2M
- bool "Enable 2M DMA region"
-config DMA_UNCACHED_1M
- bool "Enable 1M DMA region"
-config DMA_UNCACHED_512K
- bool "Enable 512K DMA region"
-config DMA_UNCACHED_256K
- bool "Enable 256K DMA region"
-config DMA_UNCACHED_128K
- bool "Enable 128K DMA region"
-config DMA_UNCACHED_NONE
- bool "Disable DMA region"
-endchoice
-
-
-comment "Cache Support"
-
-config BFIN_ICACHE
- bool "Enable ICACHE"
- default y
-config BFIN_EXTMEM_ICACHEABLE
- bool "Enable ICACHE for external memory"
- depends on BFIN_ICACHE
- default y
-config BFIN_L2_ICACHEABLE
- bool "Enable ICACHE for L2 SRAM"
- depends on BFIN_ICACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-
-config BFIN_DCACHE
- bool "Enable DCACHE"
- default y
-config BFIN_DCACHE_BANKA
- bool "Enable only 16k BankA DCACHE - BankB is SRAM"
- depends on BFIN_DCACHE && !BF531
- default n
-config BFIN_EXTMEM_DCACHEABLE
- bool "Enable DCACHE for external memory"
- depends on BFIN_DCACHE
- default y
-choice
- prompt "External memory DCACHE policy"
- depends on BFIN_EXTMEM_DCACHEABLE
- default BFIN_EXTMEM_WRITEBACK if !SMP
- default BFIN_EXTMEM_WRITETHROUGH if SMP
-config BFIN_EXTMEM_WRITEBACK
- bool "Write back"
- depends on !SMP
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-config BFIN_EXTMEM_WRITETHROUGH
- bool "Write through"
- help
- Write Back Policy:
- Cached data will be written back to SDRAM only when needed.
- This can give a nice increase in performance, but beware of
- broken drivers that do not properly invalidate/flush their
- cache.
-
- Write Through Policy:
- Cached data will always be written back to SDRAM when the
- cache is updated. This is a completely safe setting, but
- performance is worse than Write Back.
-
- If you are unsure of the options and you want to be safe,
- then go with Write Through.
-
-endchoice
-
-config BFIN_L2_DCACHEABLE
- bool "Enable DCACHE for L2 SRAM"
- depends on BFIN_DCACHE
- depends on (BF54x || BF561 || BF60x) && !SMP
- default n
-choice
- prompt "L2 SRAM DCACHE policy"
- depends on BFIN_L2_DCACHEABLE
- default BFIN_L2_WRITEBACK
-config BFIN_L2_WRITEBACK
- bool "Write back"
-
-config BFIN_L2_WRITETHROUGH
- bool "Write through"
-endchoice
-
-
-comment "Memory Protection Unit"
-config MPU
- bool "Enable the memory protection unit"
- default n
- help
- Use the processor's MPU to protect applications from accessing
- memory they do not own. This comes at a performance penalty
- and is recommended only for debugging.
-
-comment "Asynchronous Memory Configuration"
-
-menu "EBIU_AMGCTL Global Control"
- depends on !BF60x
-config C_AMCKEN
- bool "Enable CLKOUT"
- default y
-
-config C_CDPRIO
- bool "DMA has priority over core for ext. accesses"
- default n
-
-config C_B0PEN
- depends on BF561
- bool "Bank 0 16 bit packing enable"
- default y
-
-config C_B1PEN
- depends on BF561
- bool "Bank 1 16 bit packing enable"
- default y
-
-config C_B2PEN
- depends on BF561
- bool "Bank 2 16 bit packing enable"
- default y
-
-config C_B3PEN
- depends on BF561
- bool "Bank 3 16 bit packing enable"
- default n
-
-choice
- prompt "Enable Asynchronous Memory Banks"
- default C_AMBEN_ALL
-
-config C_AMBEN
- bool "Disable All Banks"
-
-config C_AMBEN_B0
- bool "Enable Bank 0"
-
-config C_AMBEN_B0_B1
- bool "Enable Bank 0 & 1"
-
-config C_AMBEN_B0_B1_B2
- bool "Enable Bank 0 & 1 & 2"
-
-config C_AMBEN_ALL
- bool "Enable All Banks"
-endchoice
-endmenu
-
-menu "EBIU_AMBCTL Control"
- depends on !BF60x
-config BANK_0
- hex "Bank 0 (AMBCTL0.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 0 settings.
-
-config BANK_1
- hex "Bank 1 (AMBCTL0.H)"
- default 0x7BB0
- default 0x5558 if BF54x
- help
- These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
- used to control the Asynchronous Memory Bank 1 settings.
-
-config BANK_2
- hex "Bank 2 (AMBCTL1.L)"
- default 0x7BB0
- help
- These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 2 settings.
-
-config BANK_3
- hex "Bank 3 (AMBCTL1.H)"
- default 0x99B3
- help
- These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
- used to control the Asynchronous Memory Bank 3 settings.
-
-endmenu
-
-config EBIU_MBSCTLVAL
- hex "EBIU Bank Select Control Register"
- depends on BF54x
- default 0
-
-config EBIU_MODEVAL
- hex "Flash Memory Mode Control Register"
- depends on BF54x
- default 1
-
-config EBIU_FCTLVAL
- hex "Flash Memory Bank Control Register"
- depends on BF54x
- default 6
-endmenu
-
-#############################################################################
-menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
-
-config PCI
- bool "PCI support"
- depends on BROKEN
- help
- Support for PCI bus.
-
-source "drivers/pci/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-endmenu
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-menu "Power management options"
-
-source "kernel/power/Kconfig"
-
-config ARCH_SUSPEND_POSSIBLE
- def_bool y
-
-choice
- prompt "Standby Power Saving Mode"
- depends on PM && !BF60x
- default PM_BFIN_SLEEP_DEEPER
-config PM_BFIN_SLEEP_DEEPER
- bool "Sleep Deeper"
- help
- Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
- power dissipation by disabling the clock to the processor core (CCLK).
- Furthermore, Standby sets the internal power supply voltage (VDDINT)
- to 0.85 V to provide the greatest power savings, while preserving the
- processor state.
- The PLL and system clock (SCLK) continue to operate at a very low
- frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
- the SDRAM is put into Self Refresh Mode. Typically an external event
- such as GPIO interrupt or RTC activity wakes up the processor.
- Various Peripherals such as UART, SPORT, PPI may not function as
- normal during Sleep Deeper, due to the reduced SCLK frequency.
- When in the sleep mode, system DMA access to L1 memory is not supported.
-
- If unsure, select "Sleep Deeper".
-
-config PM_BFIN_SLEEP
- bool "Sleep"
- help
- Sleep Mode (High Power Savings) - The sleep mode reduces power
- dissipation by disabling the clock to the processor core (CCLK).
- The PLL and system clock (SCLK), however, continue to operate in
- this mode. Typically an external event or RTC activity will wake
- up the processor. When in the sleep mode, system DMA access to L1
- memory is not supported.
-
- If unsure, select "Sleep Deeper".
-endchoice
-
-comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
- depends on PM
-
-config PM_BFIN_WAKE_PH6
- bool "Allow Wake-Up from on-chip PHY or PH6 GP"
- depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
- default n
- help
- Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
-
-config PM_BFIN_WAKE_GP
- bool "Allow Wake-Up from GPIOs"
- depends on PM && BF54x
- default n
- help
- Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
- (all processors, except ADSP-BF549). This option sets
- the general-purpose wake-up enable (GPWE) control bit to enable
- wake-up upon detection of an active low signal on the /GPW (PH7) pin.
- On ADSP-BF549 this option enables the same functionality on the
- /MRXON pin also PH7.
-
-config PM_BFIN_WAKE_PA15
- bool "Allow Wake-Up from PA15"
- depends on PM && BF60x
- default n
- help
- Enable PA15 Wake-Up
-
-config PM_BFIN_WAKE_PA15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PA15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PB15
- bool "Allow Wake-Up from PB15"
- depends on PM && BF60x
- default n
- help
- Enable PB15 Wake-Up
-
-config PM_BFIN_WAKE_PB15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PB15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PC15
- bool "Allow Wake-Up from PC15"
- depends on PM && BF60x
- default n
- help
- Enable PC15 Wake-Up
-
-config PM_BFIN_WAKE_PC15_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PC15
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PD06
- bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
- depends on PM && BF60x
- default n
- help
- Enable PD06(ETH0_PHYINT) Wake-up
-
-config PM_BFIN_WAKE_PD06_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PD06
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PE12
- bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
- depends on PM && BF60x
- default n
- help
- Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
-
-config PM_BFIN_WAKE_PE12_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PE12
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG04
- bool "Allow Wake-Up from PG04(CAN0_RX)"
- depends on PM && BF60x
- default n
- help
- Enable PG04(CAN0_RX) Wake-up
-
-config PM_BFIN_WAKE_PG04_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG04
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_PG13
- bool "Allow Wake-Up from PG13"
- depends on PM && BF60x
- default n
- help
- Enable PG13 Wake-Up
-
-config PM_BFIN_WAKE_PG13_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_PG13
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-config PM_BFIN_WAKE_USB
- bool "Allow Wake-Up from (USB)"
- depends on PM && BF60x
- default n
- help
- Enable (USB) Wake-up
-
-config PM_BFIN_WAKE_USB_POL
- int "Wake-up priority"
- depends on PM_BFIN_WAKE_USB
- default 0
- help
- Wake-Up priority 0(low) 1(high)
-
-endmenu
-
-menu "CPU Frequency scaling"
-
-source "drivers/cpufreq/Kconfig"
-
-config BFIN_CPU_FREQ
- bool
- depends on CPU_FREQ
- default y
-
-config CPU_VOLTAGE
- bool "CPU Voltage scaling"
- depends on CPU_FREQ
- default n
- help
- Say Y here if you want CPU voltage scaling according to the CPU frequency.
- This option violates the PLL BYPASS recommendation in the Blackfin Processor
- manuals. There is a theoretical risk that during VDDINT transitions
- the PLL may unlock.
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "drivers/firmware/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/blackfin/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
deleted file mode 100644
index c8d957274cc2..000000000000
--- a/arch/blackfin/Kconfig.debug
+++ /dev/null
@@ -1,258 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config DEBUG_VERBOSE
- bool "Verbose fault messages"
- default y
- select PRINTK
- help
- When a program crashes due to an exception, or the kernel detects
- an internal error, the kernel can print a not so brief message
- explaining what the problem was. This debugging information is
- useful to developers and kernel hackers when tracking down problems,
- but mostly meaningless to other people. This is always helpful for
- debugging but serves no purpose on a production system.
- Most people should say N here.
-
-config DEBUG_MMRS
- tristate "Generate Blackfin MMR tree"
- depends on !PINCTRL
- select DEBUG_FS
- help
- Create a tree of Blackfin MMRs via the debugfs tree. If
- you enable this, you will find all MMRs laid out in the
- /sys/kernel/debug/blackfin/ directory where you can read/write
- MMRs directly from userspace. This is obviously just a debug
- feature.
-
-config DEBUG_HWERR
- bool "Hardware error interrupt debugging"
- depends on DEBUG_KERNEL
- help
- When enabled, the hardware error interrupt is never disabled, and
- will happen immediately when an error condition occurs. This comes
- at a slight cost in code size, but is necessary if you are getting
- hardware error interrupts and need to know where they are coming
- from.
-
-config EXACT_HWERR
- bool "Try to make Hardware errors exact"
- depends on DEBUG_HWERR
- help
- By default, the Blackfin hardware errors are not exact - the error
- be reported multiple cycles after the error happens. This delay
- can cause the wrong application, or even the kernel to receive a
- signal to be killed. If you are getting HW errors in your system,
- try turning this on to ensure they are at least coming from the
- proper thread.
-
- On production systems, it is safe (and a small optimization) to say N.
-
-config DEBUG_DOUBLEFAULT
- bool "Debug Double Faults"
- default n
- help
- If an exception is caused while executing code within the exception
- handler, the NMI handler, the reset vector, or in emulator mode,
- a double fault occurs. On the Blackfin, this is a unrecoverable
- event. You have two options:
- - RESET exactly when double fault occurs. The excepting
- instruction address is stored in RETX, where the next kernel
- boot will print it out.
- - Print debug message. This is much more error prone, although
- easier to handle. It is error prone since:
- - The excepting instruction is not committed.
- - All writebacks from the instruction are prevented.
- - The generated exception is not taken.
- - The EXCAUSE field is updated with an unrecoverable event
- The only way to check this is to see if EXCAUSE contains the
- unrecoverable event value at every exception return. By selecting
- this option, you are skipping over the faulting instruction, and
- hoping things stay together enough to print out a debug message.
-
- This does add a little kernel code, but is the only method to debug
- double faults - if unsure say "Y"
-
-choice
- prompt "Double Fault Failure Method"
- default DEBUG_DOUBLEFAULT_PRINT
- depends on DEBUG_DOUBLEFAULT
-
-config DEBUG_DOUBLEFAULT_PRINT
- bool "Print"
-
-config DEBUG_DOUBLEFAULT_RESET
- bool "Reset"
-
-endchoice
-
-config DEBUG_HUNT_FOR_ZERO
- bool "Catch NULL pointer reads/writes"
- default y
- help
- Say Y here to catch reads/writes to anywhere in the memory range
- from 0x0000 - 0x0FFF (the first 4k) of memory. This is useful in
- catching common programming errors such as NULL pointer dereferences.
-
- Misbehaving applications will be killed (generate a SEGV) while the
- kernel will trigger a panic.
-
- Enabling this option will take up an extra entry in CPLB table.
- Otherwise, there is no extra overhead.
-
-config DEBUG_BFIN_HWTRACE_ON
- bool "Turn on Blackfin's Hardware Trace"
- default y
- help
- All Blackfins include a Trace Unit which stores a history of the last
- 16 changes in program flow taken by the program sequencer. The history
- allows the user to recreate the program sequencer’s recent path. This
- can be handy when an application dies - we print out the execution
- path of how it got to the offending instruction.
-
- By turning this off, you may save a tiny amount of power.
-
-choice
- prompt "Omit loop Tracing"
- default DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- depends on DEBUG_BFIN_HWTRACE_ON
- help
- The trace buffer can be configured to omit recording of changes in
- program flow that match either the last entry or one of the last
- two entries. Omitting one of these entries from the record prevents
- the trace buffer from overflowing because of any sort of loop (for, do
- while, etc) in the program.
-
- Because zero-overhead Hardware loops are not recorded in the trace buffer,
- this feature can be used to prevent trace overflow from loops that
- are nested four deep.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- bool "Trace all Loops"
- help
- The trace buffer records all changes of flow
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- bool "Compress single-level loops"
- help
- The trace buffer does not record single loops - helpful if trace
- is spinning on a while or do loop.
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
- bool "Compress two-level loops"
- help
- The trace buffer does not record loops two levels deep. Helpful if
- the trace is spinning in a nested loop
-
-endchoice
-
-config DEBUG_BFIN_HWTRACE_COMPRESSION
- int
- depends on DEBUG_BFIN_HWTRACE_ON
- default 0 if DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
- default 1 if DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
- default 2 if DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
-
-
-config DEBUG_BFIN_HWTRACE_EXPAND
- bool "Expand Trace Buffer greater than 16 entries"
- depends on DEBUG_BFIN_HWTRACE_ON
- default n
- help
- By selecting this option, every time the 16 hardware entries in
- the Blackfin's HW Trace buffer are full, the kernel will move them
- into a software buffer, for dumping when there is an issue. This
- has a great impact on performance, (an interrupt every 16 change of
- flows) and should normally be turned off, except in those nasty
- debugging sessions
-
-config DEBUG_BFIN_HWTRACE_EXPAND_LEN
- int "Size of Trace buffer (in power of 2k)"
- range 0 4
- depends on DEBUG_BFIN_HWTRACE_EXPAND
- default 1
- help
- This sets the size of the software buffer that the trace information
- is kept in.
- 0 for (2^0) 1k, or 256 entries,
- 1 for (2^1) 2k, or 512 entries,
- 2 for (2^2) 4k, or 1024 entries,
- 3 for (2^3) 8k, or 2048 entries,
- 4 for (2^4) 16k, or 4096 entries
-
-config DEBUG_BFIN_NO_KERN_HWTRACE
- bool "Turn off hwtrace in CPLB handlers"
- depends on DEBUG_BFIN_HWTRACE_ON
- default y
- help
- The CPLB error handler contains a lot of flow changes which can
- quickly fill up the hardware trace buffer. When debugging crashes,
- the hardware trace may indicate that the problem lies in kernel
- space when in reality an application is buggy.
-
- Say Y here to disable hardware tracing in some known "jumpy" pieces
- of code so that the trace buffer will extend further back.
-
-config EARLY_PRINTK
- bool "Early printk"
- default n
- select SERIAL_CORE_CONSOLE
- help
- This option enables special console drivers which allow the kernel
- to print messages very early in the bootup process.
-
- This is useful for kernel debugging when your machine crashes very
- early before the console code is initialized. After enabling this
- feature, you must add "earlyprintk=serial,uart0,57600" to the
- command line (bootargs). It is safe to say Y here in all cases, as
- all of this lives in the init section and is thrown away after the
- kernel boots completely.
-
-config NMI_WATCHDOG
- bool "Enable NMI watchdog to help debugging lockup on SMP"
- default n
- depends on SMP
- help
- If any CPU in the system does not execute the period local timer
- interrupt for more than 5 seconds, then the NMI handler dumps debug
- information. This information can be used to debug the lockup.
-
-config CPLB_INFO
- bool "Display the CPLB information"
- help
- Display the CPLB information via /proc/cplbinfo.
-
-config ACCESS_CHECK
- bool "Check the user pointer address"
- default y
- help
- Usually the pointer transfer from user space is checked to see if its
- address is in the kernel space.
-
- Say N here to disable that check to improve the performance.
-
-config BFIN_ISRAM_SELF_TEST
- bool "isram boot self tests"
- default n
- help
- Run some self tests of the isram driver code at boot.
-
-config BFIN_PSEUDODBG_INSNS
- bool "Support pseudo debug instructions"
- default n
- help
- This option allows the kernel to emulate some pseudo instructions which
- allow simulator test cases to be run under Linux with no changes.
-
- Most people should say N here.
-
-config BFIN_PM_WAKEUP_TIME_BENCH
- bool "Display the total time for kernel to resume from power saving mode"
- default n
- help
- Display the total time when kernel resumes normal from standby or
- suspend to mem mode.
-
-endmenu
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
deleted file mode 100644
index 1fce08632ad7..000000000000
--- a/arch/blackfin/Makefile
+++ /dev/null
@@ -1,168 +0,0 @@
-#
-# arch/blackfin/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := bfin-uclinux-
-endif
-LDFLAGS_vmlinux := -X
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-GZFLAGS := -9
-
-KBUILD_CFLAGS += $(call cc-option,-mno-fdpic)
-ifeq ($(CONFIG_ROMKERNEL),y)
-KBUILD_CFLAGS += -mlong-calls
-endif
-KBUILD_AFLAGS += $(call cc-option,-mno-fdpic)
-KBUILD_CFLAGS_MODULE += -mlong-calls
-LDFLAGS += -m elf32bfin
-
-KBUILD_DEFCONFIG := BF537-STAMP_defconfig
-
-# setup the machine name and the machine dependent settings
-machine-$(CONFIG_BF512) := bf518
-machine-$(CONFIG_BF514) := bf518
-machine-$(CONFIG_BF516) := bf518
-machine-$(CONFIG_BF518) := bf518
-machine-$(CONFIG_BF522) := bf527
-machine-$(CONFIG_BF523) := bf527
-machine-$(CONFIG_BF524) := bf527
-machine-$(CONFIG_BF525) := bf527
-machine-$(CONFIG_BF526) := bf527
-machine-$(CONFIG_BF527) := bf527
-machine-$(CONFIG_BF531) := bf533
-machine-$(CONFIG_BF532) := bf533
-machine-$(CONFIG_BF533) := bf533
-machine-$(CONFIG_BF534) := bf537
-machine-$(CONFIG_BF536) := bf537
-machine-$(CONFIG_BF537) := bf537
-machine-$(CONFIG_BF538) := bf538
-machine-$(CONFIG_BF539) := bf538
-machine-$(CONFIG_BF542) := bf548
-machine-$(CONFIG_BF542M) := bf548
-machine-$(CONFIG_BF544) := bf548
-machine-$(CONFIG_BF544M) := bf548
-machine-$(CONFIG_BF547) := bf548
-machine-$(CONFIG_BF547M) := bf548
-machine-$(CONFIG_BF548) := bf548
-machine-$(CONFIG_BF548M) := bf548
-machine-$(CONFIG_BF549) := bf548
-machine-$(CONFIG_BF549M) := bf548
-machine-$(CONFIG_BF561) := bf561
-machine-$(CONFIG_BF609) := bf609
-MACHINE := $(machine-y)
-export MACHINE
-
-cpu-$(CONFIG_BF512) := bf512
-cpu-$(CONFIG_BF514) := bf514
-cpu-$(CONFIG_BF516) := bf516
-cpu-$(CONFIG_BF518) := bf518
-cpu-$(CONFIG_BF522) := bf522
-cpu-$(CONFIG_BF523) := bf523
-cpu-$(CONFIG_BF524) := bf524
-cpu-$(CONFIG_BF525) := bf525
-cpu-$(CONFIG_BF526) := bf526
-cpu-$(CONFIG_BF527) := bf527
-cpu-$(CONFIG_BF531) := bf531
-cpu-$(CONFIG_BF532) := bf532
-cpu-$(CONFIG_BF533) := bf533
-cpu-$(CONFIG_BF534) := bf534
-cpu-$(CONFIG_BF536) := bf536
-cpu-$(CONFIG_BF537) := bf537
-cpu-$(CONFIG_BF538) := bf538
-cpu-$(CONFIG_BF539) := bf539
-cpu-$(CONFIG_BF542) := bf542
-cpu-$(CONFIG_BF542M) := bf542m
-cpu-$(CONFIG_BF544) := bf544
-cpu-$(CONFIG_BF544M) := bf544m
-cpu-$(CONFIG_BF547) := bf547
-cpu-$(CONFIG_BF547M) := bf547m
-cpu-$(CONFIG_BF548) := bf548
-cpu-$(CONFIG_BF548M) := bf548m
-cpu-$(CONFIG_BF549) := bf549
-cpu-$(CONFIG_BF549M) := bf549m
-cpu-$(CONFIG_BF561) := bf561
-cpu-$(CONFIG_BF609) := bf609
-
-rev-$(CONFIG_BF_REV_0_0) := 0.0
-rev-$(CONFIG_BF_REV_0_1) := 0.1
-rev-$(CONFIG_BF_REV_0_2) := 0.2
-rev-$(CONFIG_BF_REV_0_3) := 0.3
-rev-$(CONFIG_BF_REV_0_4) := 0.4
-rev-$(CONFIG_BF_REV_0_5) := 0.5
-rev-$(CONFIG_BF_REV_0_6) := 0.6
-rev-$(CONFIG_BF_REV_NONE) := none
-rev-$(CONFIG_BF_REV_ANY) := any
-
-CPU_REV := $(cpu-y)-$(rev-y)
-export CPU_REV
-
-KBUILD_CFLAGS += -mcpu=$(CPU_REV)
-KBUILD_AFLAGS += -mcpu=$(CPU_REV)
-
-# - we utilize the silicon rev from the toolchain, so move it over to the checkflags
-CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
-CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__
-
-core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/
-
-# If we have a machine-specific directory, then include it in the build.
-ifneq ($(machine-y),)
-core-y += arch/$(ARCH)/mach-$(MACHINE)/
-core-y += arch/$(ARCH)/mach-$(MACHINE)/boards/
-endif
-
-ifeq ($(CONFIG_MPU),y)
-core-y += arch/$(ARCH)/kernel/cplb-mpu/
-else
-core-y += arch/$(ARCH)/kernel/cplb-nompu/
-endif
-
-drivers-$(CONFIG_OPROFILE) += arch/$(ARCH)/oprofile/
-
-libs-y += arch/$(ARCH)/lib/
-
-machdirs := $(patsubst %,arch/blackfin/mach-%/, $(machine-y))
-
-KBUILD_CFLAGS += -Iarch/$(ARCH)/include/
-KBUILD_CFLAGS += -Iarch/$(ARCH)/mach-$(MACHINE)/include
-
-KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
-
-CLEAN_FILES += \
- arch/$(ARCH)/kernel/asm-offsets.s \
-
-archclean:
- $(Q)$(MAKE) $(clean)=$(boot)
-
-INSTALL_PATH ?= /tftpboot
-boot := arch/$(ARCH)/boot
-BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-PHONY += $(BOOT_TARGETS) install
-KBUILD_IMAGE := $(boot)/uImage
-
-all: uImage
-
-$(BOOT_TARGETS): vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-install:
- $(Q)$(MAKE) $(build)=$(boot) BOOTIMAGE=$(KBUILD_IMAGE) install
-
-define archhelp
- echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)'
- echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)'
- echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
- echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
- echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
- echo ' vmImage.lzo - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzo)'
- echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)'
- echo ' install - Install kernel using'
- echo ' (your) ~/bin/$(INSTALLKERNEL) or'
- echo ' (distribution) PATH: $(INSTALLKERNEL) or'
- echo ' install to $$(INSTALL_PATH)'
-endef
diff --git a/arch/blackfin/boot/.gitignore b/arch/blackfin/boot/.gitignore
deleted file mode 100644
index 1287a5487e7d..000000000000
--- a/arch/blackfin/boot/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-vmImage*
-vmlinux*
-uImage*
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
deleted file mode 100644
index 3efaa094fb90..000000000000
--- a/arch/blackfin/boot/Makefile
+++ /dev/null
@@ -1,71 +0,0 @@
-#
-# arch/blackfin/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
-extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
-
-ifeq ($(CONFIG_RAMKERNEL),y)
-UIMAGE_LOADADDR = $(CONFIG_BOOT_LOAD)
-else # CONFIG_ROMKERNEL must be set
-UIMAGE_LOADADDR = $(CONFIG_ROM_BASE)
-endif
-UIMAGE_ENTRYADDR = $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}')
-UIMAGE_NAME = '$(CPU_REV)-$(KERNELRELEASE)'
-UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -x
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
- $(call if_changed,bzip2)
-
-$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzma)
-
-$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzo)
-
-# The mkimage tool wants 64bytes prepended to the image
-quiet_cmd_mk_bin_xip = BIN $@
- cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@
-$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE
- $(call if_changed,mk_bin_xip)
-
-$(obj)/uImage.bin: $(obj)/vmlinux.bin
- $(call if_changed,uimage,none)
-
-$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
- $(call if_changed,uimage,bzip2)
-
-$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
- $(call if_changed,uimage,gzip)
-
-$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
- $(call if_changed,uimage,lzma)
-
-$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
- $(call if_changed,uimage,lzo)
-
-$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip
- $(call if_changed,uimage,none)
-
-suffix-y := bin
-suffix-$(CONFIG_KERNEL_GZIP) := gz
-suffix-$(CONFIG_KERNEL_BZIP2) := bz2
-suffix-$(CONFIG_KERNEL_LZMA) := lzma
-suffix-$(CONFIG_KERNEL_LZO) := lzo
-suffix-$(CONFIG_ROMKERNEL) := xip
-
-$(obj)/uImage: $(obj)/uImage.$(suffix-y)
- @ln -sf $(notdir $<) $@
-
-install:
- sh $(srctree)/$(src)/install.sh $(KERNELRELEASE) $(BOOTIMAGE) System.map "$(INSTALL_PATH)"
diff --git a/arch/blackfin/boot/install.sh b/arch/blackfin/boot/install.sh
deleted file mode 100644
index e2c6e40902b7..000000000000
--- a/arch/blackfin/boot/install.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/sh
-#
-# arch/blackfin/boot/install.sh
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995 by Linus Torvalds
-#
-# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
-# Adapted from code in arch/i386/boot/install.sh by Mike Frysinger
-#
-# "make install" script for Blackfin architecture
-#
-# Arguments:
-# $1 - kernel version
-# $2 - kernel image file
-# $3 - kernel map file
-# $4 - default install path (blank if root directory)
-#
-
-verify () {
- if [ ! -f "$1" ]; then
- echo "" 1>&2
- echo " *** Missing file: $1" 1>&2
- echo ' *** You need to run "make" before "make install".' 1>&2
- echo "" 1>&2
- exit 1
- fi
-}
-
-# Make sure the files actually exist
-verify "$2"
-verify "$3"
-
-# User may have a custom install script
-
-if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi
-if which ${INSTALLKERNEL} >/dev/null 2>&1; then
- exec ${INSTALLKERNEL} "$@"
-fi
-
-# Default install - same as make zlilo
-
-back_it_up() {
- local file=$1
- [ -f ${file} ] || return 0
- local stamp=$(stat -c %Y ${file} 2>/dev/null)
- mv ${file} ${file}.${stamp:-old}
-}
-
-back_it_up $4/uImage
-back_it_up $4/System.map
-
-cat $2 > $4/uImage
-cp $3 $4/System.map
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
deleted file mode 100644
index 99c00d835f47..000000000000
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
deleted file mode 100644
index e66ba31ef84d..000000000000
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF526=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN526_EZBRD=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
deleted file mode 100644
index d95658fc3127..000000000000
--- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_IRQ_TWI=7
-CONFIG_IRQ_PORTH_INTA=7
-CONFIG_IRQ_PORTH_INTB=7
-CONFIG_BFIN527_AD7160EVAL=y
-CONFIG_BF527_SPORT0_PORTF=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="bootargs=root=/dev/mtdblock0 rw clkin_hz=24000000 earlyprintk=serial,uart0,57600 console=tty0 console=ttyBF0,57600"
-CONFIG_CLKIN_HZ=24000000
-CONFIG_HZ_300=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x5554
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7160=y
-CONFIG_TOUCHSCREEN_AD7160_FW=y
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_BFIN_OTP is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=400
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_USB_G_SERIAL=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
deleted file mode 100644
index 0207c588c19f..000000000000
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ /dev/null
@@ -1,188 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_EZKIT_V2=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_ADP5520=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_I2C=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_PMIC_ADP5520=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_LQ035Q1=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_ADP5520=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
deleted file mode 100644
index 99c131ba7d90..000000000000
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ /dev/null
@@ -1,181 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=m
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FB_BFIN_T350MCQB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_LTV350QV=m
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF527-TLL6527M_defconfig b/arch/blackfin/configs/BF527-TLL6527M_defconfig
deleted file mode 100644
index cdeb51856f26..000000000000
--- a/arch/blackfin/configs/BF527-TLL6527M_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DEV_0-1_pre2010"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_2=y
-CONFIG_BFIN527_TLL6527M=y
-CONFIG_BF527_UART1_PORTG=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-CONFIG_BOOT_LOAD=0x400000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xFFC2
-CONFIG_BANK_1=0xFFC2
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR0=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_AD714X=y
-CONFIG_INPUT_ADXL34X=y
-# CONFIG_SERIO is not set
-CONFIG_BFIN_PPI=m
-CONFIG_BFIN_SIMPLE_TIMER=m
-CONFIG_BFIN_SPORT=m
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_SMBUS=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_BLACKFIN_CAM=m
-CONFIG_OV9655=y
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SOC_SSM2602=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC7=m
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
deleted file mode 100644
index ed7d2c096739..000000000000
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BFIN533_EZKIT=y
-CONFIG_TIMER0=11
-CONFIG_CLKIN_HZ=27000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
deleted file mode 100644
index 0c241f4d28d7..000000000000
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ /dev/null
@@ -1,124 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_TIMER0=11
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
deleted file mode 100644
index e5360b30e39a..000000000000
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ /dev/null
@@ -1,136 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR1=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_BFIN=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_AD73311=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
deleted file mode 100644
index 60f6fb86125c..000000000000
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ /dev/null
@@ -1,133 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF538=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_IRQ_TIMER1=12
-CONFIG_IRQ_TIMER2=12
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_DEV=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7879=y
-CONFIG_TOUCHSCREEN_AD7879_SPI=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-CONFIG_SERIAL_BFIN_UART2=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=m
-CONFIG_FB_BFIN_LQ035Q1=m
-# CONFIG_USB_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
deleted file mode 100644
index 38cb17d218d4..000000000000
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ /dev/null
@@ -1,207 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF548_std=y
-CONFIG_IRQ_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_3=0x99B2
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_BFIN=m
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRTTY_SIR=m
-CONFIG_BFIN_SIR=m
-CONFIG_BFIN_SIR3=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_BF5XX=y
-# CONFIG_MTD_NAND_BF5XX_HWECC is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_ATA=y
-# CONFIG_SATA_PMP is not set
-CONFIG_PATA_BF54X=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_BFIN=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=m
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_BF54X_LQ043=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_AC97=y
-CONFIG_SND_BF5XX_SOC_AD1980=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_PANTHERLORD=y
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=m
-CONFIG_SDH_BFIN=y
-CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig
deleted file mode 100644
index 78f6bc79f910..000000000000
--- a/arch/blackfin/configs/BF561-ACVILON_defconfig
+++ /dev/null
@@ -1,149 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_BF_REV_0_5=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_ACVILON=y
-# CONFIG_BF561_COREB is not set
-CONFIG_CLKIN_HZ=12000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_DMA_UNCACHED_4M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0x99b2
-CONFIG_BANK_1=0x3350
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_PHRAM=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=2
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PCA_PLATFORM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_BF5XX_I2S=y
-CONFIG_SND_BF5XX_SPORT_NUM=1
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="cp1251"
-CONFIG_NTFS_FS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-# CONFIG_JFFS2_ZLIB is not set
-CONFIG_JFFS2_LZO=y
-# CONFIG_JFFS2_RTIME is not set
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_DEFAULT="cp1251"
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_UTF8=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
deleted file mode 100644
index fac8bb578249..000000000000
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ /dev/null
@@ -1,112 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_SMP=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
deleted file mode 100644
index 2a2e4d0cebc1..000000000000
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ /dev/null
@@ -1,114 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_CLKIN_HZ=30000000
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BFIN_L2_DCACHEABLE=y
-CONFIG_BFIN_L2_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-CONFIG_SMC91X=y
-# CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_JTAG_COMM=m
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
deleted file mode 100644
index 3ce77f07208a..000000000000
--- a/arch/blackfin/configs/BF609-EZKIT_defconfig
+++ /dev/null
@@ -1,154 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF609=y
-CONFIG_PINT1_ASSIGN=0x01010000
-CONFIG_PINT2_ASSIGN=0x07000101
-CONFIG_PINT3_ASSIGN=0x02020303
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-# CONFIG_APP_STACK_L1 is not set
-# CONFIG_BFIN_INS_LOWOVERHEAD is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM_BFIN_WAKE_PE12=y
-CONFIG_PM_BFIN_WAKE_PE12_POL=1
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_CAN=y
-CONFIG_CAN_BFIN=y
-CONFIG_IRDA=y
-CONFIG_IRTTY_SIR=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=m
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_IEEE1588=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_BFIN_ROTARY=y
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_BFIN_SIMPLE_TIMER=m
-# CONFIG_BFIN_CRC is not set
-CONFIG_BFIN_LINKPORT=y
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_ADI_V3=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_PINCTRL_MCP23S08=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_USB=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_BLACKFIN=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_ZERO=y
-CONFIG_MMC=y
-CONFIG_SDH_BFIN=y
-# CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=m
-CONFIG_UBIFS_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_BFIN_PSEUDODBG_INSNS=y
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_DEV_BFIN_CRC=m
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
deleted file mode 100644
index f4a9200e1ab1..000000000000
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BLACKSTAMP=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_ROMKERNEL=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xAAC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=m
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_SMB_FS=y
-CONFIG_CIFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
deleted file mode 100644
index 1902bb05d086..000000000000
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ /dev/null
@@ -1,129 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF527=y
-CONFIG_BF_REV_0_1=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN527_BLUETECHNIX_CM=y
-CONFIG_IRQ_USB_INT0=11
-CONFIG_IRQ_USB_INT1=11
-CONFIG_IRQ_USB_INT2=11
-CONFIG_IRQ_USB_DMA=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC0
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB=m
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OTG_BLACKLIST_HUB=y
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_MUSB_PIO_ONLY=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig
deleted file mode 100644
index 9a5716d57ebc..000000000000
--- a/arch/blackfin/configs/CM-BF533_defconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BFIN533_BLUETECHNIX_CM=y
-CONFIG_TIMER0=11
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF537E_defconfig b/arch/blackfin/configs/CM-BF537E_defconfig
deleted file mode 100644
index 684592884349..000000000000
--- a/arch/blackfin/configs/CM-BF537E_defconfig
+++ /dev/null
@@ -1,107 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_E=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF537U_defconfig b/arch/blackfin/configs/CM-BF537U_defconfig
deleted file mode 100644
index d9915e984787..000000000000
--- a/arch/blackfin/configs/CM-BF537U_defconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_CM_U=y
-CONFIG_CLKIN_HZ=30000000
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_2=0xFFC2
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
deleted file mode 100644
index 92d8130cdb51..000000000000
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ /dev/null
@@ -1,170 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF548_std=y
-CONFIG_BF_REV_ANY=y
-CONFIG_IRQ_TIMER0=11
-CONFIG_BFIN548_BLUETECHNIX_CM=y
-# CONFIG_DEB_DMA_URGENT is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_CACHELINE_ALIGNED_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BANK_1=0x5554
-CONFIG_EBIU_MBSCTLVAL=0x0
-CONFIG_EBIU_MODEVAL=0x1
-CONFIG_EBIU_FCTLVAL=0x6
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_PIO=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=m
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=m
-CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
-CONFIG_USB_GADGET_MUSB_HDRC=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=m
-CONFIG_SDH_BFIN=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=m
-CONFIG_EXT2_FS=m
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_CIFS=m
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/CM-BF561_defconfig b/arch/blackfin/configs/CM-BF561_defconfig
deleted file mode 100644
index fa8d91132a57..000000000000
--- a/arch/blackfin/configs/CM-BF561_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF561=y
-CONFIG_IRQ_TIMER0=10
-CONFIG_BFIN561_BLUETECHNIX_CM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMSC911X=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_PRINTER=m
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
deleted file mode 100644
index 88600593c731..000000000000
--- a/arch/blackfin/configs/DNP5370_defconfig
+++ /dev/null
@@ -1,118 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="DNP5370"
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLOB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_BF537=y
-CONFIG_BF_REV_0_3=y
-CONFIG_DNP5370=y
-CONFIG_IRQ_ERROR=7
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_C_AMBEN_B0_B1_B2=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_LLC2=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
-CONFIG_MTD_BLOCK=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_ABSENT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_BFIN_DMA_INTERFACE is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=y
-CONFIG_BFIN_JTAG_COMM_CONSOLE=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_SENSORS_LM75=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_SPI=y
-CONFIG_DMADEVICES=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_ROMFS_BACKED_BY_BOTH=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_OBJECTS=y
-CONFIG_DEBUG_LOCK_ALLOC=y
-CONFIG_DEBUG_KOBJECT=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_LIST=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_PAGE_POISONING=y
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig
deleted file mode 100644
index 0ff97d8d047a..000000000000
--- a/arch/blackfin/configs/H8606_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_H8606_HVSISTEMAS=y
-CONFIG_TIMER0=11
-# CONFIG_CACHELINE_ALIGNED_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_WATCHDOG=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS=m
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
deleted file mode 100644
index 9e3ae4b36d20..000000000000
--- a/arch/blackfin/configs/IP0X_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_BF532=y
-CONFIG_BF_REV_0_5=y
-CONFIG_BFIN532_IP0X=y
-CONFIG_TIMER0=11
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-# CONFIG_BFIN_ICACHE is not set
-# CONFIG_BFIN_DCACHE is not set
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_0=0xffc2
-CONFIG_BANK_1=0xffc2
-CONFIG_BANK_2=0xffc2
-CONFIG_BANK_3=0xffc2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_XT_MATCH_MAC=y
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_MANGLE=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_PLATRAM=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_USB=y
-CONFIG_USB_OTG_WHITELIST=y
-CONFIG_USB_MON=y
-CONFIG_USB_ISP1362_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
deleted file mode 100644
index c7926812971c..000000000000
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_PNAV10=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=y
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_1=0x33B0
-CONFIG_BANK_2=0x33B0
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_BFIN_MAC_USE_L1 is not set
-CONFIG_BFIN_TX_DESC_NUM=100
-CONFIG_BFIN_RX_DESC_NUM=100
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_AD7877=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_SOUND=y
-CONFIG_SND=m
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SOUND_PRIME=y
-# CONFIG_HID is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_DEBUG_HUNT_FOR_ZERO is not set
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-# CONFIG_ACCESS_CHECK is not set
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
deleted file mode 100644
index 23fdc57d657a..000000000000
--- a/arch/blackfin/configs/SRV1_defconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BOOT_LOAD=0x400000
-CONFIG_CLKIN_HZ=22118400
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_DMA_UNCACHED_2M=y
-CONFIG_C_CDPRIO=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-CONFIG_IRDA=m
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRTTY_SIR=m
-# CONFIG_WIRELESS is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_UCLINUX=y
-CONFIG_MTD_NAND=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT25=m
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_HWMON=m
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_SMB_FS=m
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_CPLB_INFO=y
diff --git a/arch/blackfin/configs/TCM-BF518_defconfig b/arch/blackfin/configs/TCM-BF518_defconfig
deleted file mode 100644
index e28959479fe0..000000000000
--- a/arch/blackfin/configs/TCM-BF518_defconfig
+++ /dev/null
@@ -1,131 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_BF518=y
-CONFIG_BF_REV_0_1=y
-CONFIG_BFIN518F_TCM=y
-CONFIG_IRQ_TIMER0=12
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-# CONFIG_SCHEDULE_L1 is not set
-# CONFIG_MEMSET_L1 is not set
-# CONFIG_MEMCPY_L1 is not set
-# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_BFIN_GPTIMERS=m
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0x99B2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_BFIN_JTAG_COMM=m
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_BLACKFIN_TWI=y
-CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_SPI=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_BFIN=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_VFAT_FS=m
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_MMRS=y
-CONFIG_DEBUG_HWERR=y
-CONFIG_EXACT_HWERR=y
-CONFIG_DEBUG_DOUBLEFAULT=y
-CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/TCM-BF537_defconfig b/arch/blackfin/configs/TCM-BF537_defconfig
deleted file mode 100644
index 39e85cce95d7..000000000000
--- a/arch/blackfin/configs/TCM-BF537_defconfig
+++ /dev/null
@@ -1,95 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_KERNEL_LZMA=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_GZIP is not set
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_UID16 is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_FUTEX is not set
-# CONFIG_AIO is not set
-CONFIG_SLAB=y
-CONFIG_MMAP_ALLOW_UNINITIALIZED=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_BF537=y
-CONFIG_IRQ_TIMER0=12
-CONFIG_BFIN537_BLUETECHNIX_TCM=y
-# CONFIG_CYCLES_CLOCKSOURCE is not set
-CONFIG_IP_CHECKSUM_L1=y
-CONFIG_SYSCALL_TAB_L1=y
-CONFIG_CPLB_SWITCH_TAB_L1=y
-CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
-CONFIG_C_CDPRIO=y
-CONFIG_BANK_3=0xFFC2
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-CONFIG_BINFMT_SHARED_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_GPIO_ADDR=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_BFIN_MAC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_BFIN=y
-CONFIG_SERIAL_BFIN_CONSOLE=y
-CONFIG_SERIAL_BFIN_UART0=y
-CONFIG_SERIAL_BFIN_UART1=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_SPI=y
-CONFIG_SPI_BFIN5XX=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_BFIN_WDT=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=y
-CONFIG_MMC=y
-CONFIG_MMC_SPI=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_CPLB_INFO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC7=y
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
deleted file mode 100644
index fe736973630f..000000000000
--- a/arch/blackfin/include/asm/Kbuild
+++ /dev/null
@@ -1,28 +0,0 @@
-generic-y += bugs.h
-generic-y += current.h
-generic-y += device.h
-generic-y += div64.h
-generic-y += emergency-restart.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += futex.h
-generic-y += hw_irq.h
-generic-y += irq_regs.h
-generic-y += irq_work.h
-generic-y += kdebug.h
-generic-y += kmap_types.h
-generic-y += kprobes.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += percpu.h
-generic-y += pgalloc.h
-generic-y += preempt.h
-generic-y += serial.h
-generic-y += topology.h
-generic-y += trace_clock.h
-generic-y += unaligned.h
-generic-y += user.h
-generic-y += word-at-a-time.h
-generic-y += xor.h
diff --git a/arch/blackfin/include/asm/asm-offsets.h b/arch/blackfin/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/blackfin/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
deleted file mode 100644
index 63c7deceeeb6..000000000000
--- a/arch/blackfin/include/asm/atomic.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_ATOMIC__
-#define __ARCH_BLACKFIN_ATOMIC__
-
-#include <asm/cmpxchg.h>
-
-#ifdef CONFIG_SMP
-
-#include <asm/barrier.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
-asmlinkage int __raw_atomic_add_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xadd_asm(volatile int *ptr, int value);
-
-asmlinkage int __raw_atomic_and_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_or_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value);
-
-#define atomic_read(v) __raw_uncached_fetch_asm(&(v)->counter)
-
-#define atomic_add_return(i, v) __raw_atomic_add_asm(&(v)->counter, i)
-#define atomic_sub_return(i, v) __raw_atomic_add_asm(&(v)->counter, -(i))
-
-#define atomic_fetch_add(i, v) __raw_atomic_xadd_asm(&(v)->counter, i)
-#define atomic_fetch_sub(i, v) __raw_atomic_xadd_asm(&(v)->counter, -(i))
-
-#define atomic_or(i, v) (void)__raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_and(i, v) (void)__raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_xor(i, v) (void)__raw_atomic_xor_asm(&(v)->counter, i)
-
-#define atomic_fetch_or(i, v) __raw_atomic_or_asm(&(v)->counter, i)
-#define atomic_fetch_and(i, v) __raw_atomic_and_asm(&(v)->counter, i)
-#define atomic_fetch_xor(i, v) __raw_atomic_xor_asm(&(v)->counter, i)
-
-#endif
-
-#include <asm-generic/atomic.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/barrier.h b/arch/blackfin/include/asm/barrier.h
deleted file mode 100644
index 7cca51cae5ff..000000000000
--- a/arch/blackfin/include/asm/barrier.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko@lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_BARRIER_H
-#define _BLACKFIN_BARRIER_H
-
-#include <asm/cache.h>
-
-#define nop() __asm__ __volatile__ ("nop;\n\t" : : )
-
-/*
- * Force strict CPU ordering.
- */
-#ifdef CONFIG_SMP
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-/* Force Core data cache coherence */
-# define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0)
-# define rmb() do { barrier(); smp_check_barrier(); } while (0)
-# define wmb() do { barrier(); smp_mark_barrier(); } while (0)
-/*
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier. All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads. This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies. See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * b = 2;
- * memory_barrier();
- * p = &b; q = p;
- * read_barrier_depends();
- * d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends(). However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- * CPU 0 CPU 1
- *
- * a = 2;
- * memory_barrier();
- * b = 3; y = b;
- * read_barrier_depends();
- * x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b". Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
- * in cases like this where there are no data dependencies.
- */
-# define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0)
-#endif
-
-#endif /* !CONFIG_SMP */
-
-#define __smp_mb__before_atomic() barrier()
-#define __smp_mb__after_atomic() barrier()
-
-#include <asm-generic/barrier.h>
-
-#endif /* _BLACKFIN_BARRIER_H */
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
deleted file mode 100644
index dc47d79287f9..000000000000
--- a/arch/blackfin/include/asm/bfin-global.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Global extern defines for blackfin
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_GLOBAL_H_
-#define _BFIN_GLOBAL_H_
-
-#ifndef __ASSEMBLY__
-
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_DMA_UNCACHED_32M)
-# define DMA_UNCACHED_REGION (32 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_16M)
-# define DMA_UNCACHED_REGION (16 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_8M)
-# define DMA_UNCACHED_REGION (8 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_4M)
-# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_2M)
-# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_1M)
-# define DMA_UNCACHED_REGION (1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_512K)
-# define DMA_UNCACHED_REGION (512 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_256K)
-# define DMA_UNCACHED_REGION (256 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_128K)
-# define DMA_UNCACHED_REGION (128 * 1024)
-#else
-# define DMA_UNCACHED_REGION (0)
-#endif
-
-extern void bfin_setup_caches(unsigned int cpu);
-extern void bfin_setup_cpudata(unsigned int cpu);
-
-extern unsigned long get_cclk(void);
-extern unsigned long get_sclk(void);
-#ifdef CONFIG_BF60x
-extern unsigned long get_sclk0(void);
-extern unsigned long get_sclk1(void);
-extern unsigned long get_dclk(void);
-#endif
-extern unsigned long sclk_to_usecs(unsigned long sclk);
-extern unsigned long usecs_to_sclk(unsigned long usecs);
-
-struct pt_regs;
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(struct pt_regs *regs);
-extern void dump_bfin_trace_buffer(void);
-#else
-#define dump_bfin_process(regs)
-#define dump_bfin_mem(regs)
-#define dump_bfin_trace_buffer()
-#endif
-
-extern void *l1_data_A_sram_alloc(size_t);
-extern void *l1_data_B_sram_alloc(size_t);
-extern void *l1_inst_sram_alloc(size_t);
-extern void *l1_data_sram_alloc(size_t);
-extern void *l1_data_sram_zalloc(size_t);
-extern void *l2_sram_alloc(size_t);
-extern void *l2_sram_zalloc(size_t);
-extern int l1_data_A_sram_free(const void*);
-extern int l1_data_B_sram_free(const void*);
-extern int l1_inst_sram_free(const void*);
-extern int l1_data_sram_free(const void*);
-extern int l2_sram_free(const void *);
-extern int sram_free(const void*);
-
-#define L1_INST_SRAM 0x00000001
-#define L1_DATA_A_SRAM 0x00000002
-#define L1_DATA_B_SRAM 0x00000004
-#define L1_DATA_SRAM 0x00000006
-#define L2_SRAM 0x00000008
-extern void *sram_alloc_with_lsl(size_t, unsigned long);
-extern int sram_free_with_lsl(const void*);
-
-extern void *isram_memcpy(void *dest, const void *src, size_t n);
-
-extern const char bfin_board_name[];
-
-extern unsigned long bfin_sic_iwr[];
-extern unsigned vr_wakeup;
-extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
-
-#endif
-
-#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bfin-lq035q1.h b/arch/blackfin/include/asm/bfin-lq035q1.h
deleted file mode 100644
index 836895156b5b..000000000000
--- a/arch/blackfin/include/asm/bfin-lq035q1.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02
- *
- * Copyright 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BFIN_LQ035Q1_H
-#define BFIN_LQ035Q1_H
-
-/*
- * LCD Modes
- */
-#define LQ035_RL (0 << 8) /* Right -> Left Scan */
-#define LQ035_LR (1 << 8) /* Left -> Right Scan */
-#define LQ035_TB (1 << 9) /* Top -> Botton Scan */
-#define LQ035_BT (0 << 9) /* Botton -> Top Scan */
-#define LQ035_BGR (1 << 11) /* Use BGR format */
-#define LQ035_RGB (0 << 11) /* Use RGB format */
-#define LQ035_NORM (1 << 13) /* Reversal */
-#define LQ035_REV (0 << 13) /* Reversal */
-
-/*
- * PPI Modes
- */
-
-#define USE_RGB565_16_BIT_PPI 1
-#define USE_RGB565_8_BIT_PPI 2
-#define USE_RGB888_8_BIT_PPI 3
-
-struct bfin_lq035q1fb_disp_info {
-
- unsigned mode;
- unsigned ppi_mode;
- /* GPIOs */
- int use_bl;
- unsigned gpio_bl;
-};
-
-#endif /* BFIN_LQ035Q1_H */
diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h
deleted file mode 100644
index fb95c853bb1e..000000000000
--- a/arch/blackfin/include/asm/bfin5xx_spi.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Blackfin On-Chip SPI Driver
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#define MIN_SPI_BAUD_VAL 2
-
-#define BIT_CTL_ENABLE 0x4000
-#define BIT_CTL_OPENDRAIN 0x2000
-#define BIT_CTL_MASTER 0x1000
-#define BIT_CTL_CPOL 0x0800
-#define BIT_CTL_CPHA 0x0400
-#define BIT_CTL_LSBF 0x0200
-#define BIT_CTL_WORDSIZE 0x0100
-#define BIT_CTL_EMISO 0x0020
-#define BIT_CTL_PSSE 0x0010
-#define BIT_CTL_GM 0x0008
-#define BIT_CTL_SZ 0x0004
-#define BIT_CTL_RXMOD 0x0000
-#define BIT_CTL_TXMOD 0x0001
-#define BIT_CTL_TIMOD_DMA_TX 0x0003
-#define BIT_CTL_TIMOD_DMA_RX 0x0002
-#define BIT_CTL_SENDOPT 0x0004
-#define BIT_CTL_TIMOD 0x0003
-
-#define BIT_STAT_SPIF 0x0001
-#define BIT_STAT_MODF 0x0002
-#define BIT_STAT_TXE 0x0004
-#define BIT_STAT_TXS 0x0008
-#define BIT_STAT_RBSY 0x0010
-#define BIT_STAT_RXS 0x0020
-#define BIT_STAT_TXCOL 0x0040
-#define BIT_STAT_CLR 0xFFFF
-
-#define BIT_STU_SENDOVER 0x0001
-#define BIT_STU_RECVFULL 0x0020
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin spi registers layout
- */
-struct bfin_spi_regs {
- __BFP(ctl);
- __BFP(flg);
- __BFP(stat);
- __BFP(tdbr);
- __BFP(rdbr);
- __BFP(baud);
- __BFP(shadow);
-};
-
-#undef __BFP
-
-#define MAX_CTRL_CS 8 /* cs in spi controller */
-
-/* device.platform_data for SSP controller devices */
-struct bfin5xx_spi_master {
- u16 num_chipselect;
- u8 enable_dma;
- u16 pin_req[7];
-};
-
-/* spi_board_info.controller_data for SPI slave devices,
- * copied to spi_device.platform_data ... mostly for dma tuning
- */
-struct bfin5xx_spi_chip {
- u16 ctl_reg;
- u8 enable_dma;
- u16 cs_chg_udelay; /* Some devices require 16-bit delays */
- /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
- u16 idle_tx_val;
- u8 pio_interrupt; /* Enable spi data irq */
-};
-
-#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h
deleted file mode 100644
index b1492e0bcabb..000000000000
--- a/arch/blackfin/include/asm/bfin_can.h
+++ /dev/null
@@ -1,728 +0,0 @@
-/*
- * bfin_can.h - interface to Blackfin CANs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_CAN_H__
-#define __ASM_BFIN_CAN_H__
-
-/*
- * transmit and receive channels
- */
-#define TRANSMIT_CHL 24
-#define RECEIVE_STD_CHL 0
-#define RECEIVE_EXT_CHL 4
-#define RECEIVE_RTR_CHL 8
-#define RECEIVE_EXT_RTR_CHL 12
-#define MAX_CHL_NUMBER 32
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin can registers layout
- */
-struct bfin_can_mask_regs {
- __BFP(aml);
- __BFP(amh);
-};
-
-struct bfin_can_channel_regs {
- /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
- u16 data[8];
- __BFP(dlc);
- __BFP(tsv);
- __BFP(id0);
- __BFP(id1);
-};
-
-struct bfin_can_regs {
- /*
- * global control and status registers
- */
- __BFP(mc1); /* offset 0x00 */
- __BFP(md1); /* offset 0x04 */
- __BFP(trs1); /* offset 0x08 */
- __BFP(trr1); /* offset 0x0c */
- __BFP(ta1); /* offset 0x10 */
- __BFP(aa1); /* offset 0x14 */
- __BFP(rmp1); /* offset 0x18 */
- __BFP(rml1); /* offset 0x1c */
- __BFP(mbtif1); /* offset 0x20 */
- __BFP(mbrif1); /* offset 0x24 */
- __BFP(mbim1); /* offset 0x28 */
- __BFP(rfh1); /* offset 0x2c */
- __BFP(opss1); /* offset 0x30 */
- u32 __pad1[3];
- __BFP(mc2); /* offset 0x40 */
- __BFP(md2); /* offset 0x44 */
- __BFP(trs2); /* offset 0x48 */
- __BFP(trr2); /* offset 0x4c */
- __BFP(ta2); /* offset 0x50 */
- __BFP(aa2); /* offset 0x54 */
- __BFP(rmp2); /* offset 0x58 */
- __BFP(rml2); /* offset 0x5c */
- __BFP(mbtif2); /* offset 0x60 */
- __BFP(mbrif2); /* offset 0x64 */
- __BFP(mbim2); /* offset 0x68 */
- __BFP(rfh2); /* offset 0x6c */
- __BFP(opss2); /* offset 0x70 */
- u32 __pad2[3];
- __BFP(clock); /* offset 0x80 */
- __BFP(timing); /* offset 0x84 */
- __BFP(debug); /* offset 0x88 */
- __BFP(status); /* offset 0x8c */
- __BFP(cec); /* offset 0x90 */
- __BFP(gis); /* offset 0x94 */
- __BFP(gim); /* offset 0x98 */
- __BFP(gif); /* offset 0x9c */
- __BFP(control); /* offset 0xa0 */
- __BFP(intr); /* offset 0xa4 */
- __BFP(version); /* offset 0xa8 */
- __BFP(mbtd); /* offset 0xac */
- __BFP(ewr); /* offset 0xb0 */
- __BFP(esr); /* offset 0xb4 */
- u32 __pad3[2];
- __BFP(ucreg); /* offset 0xc0 */
- __BFP(uccnt); /* offset 0xc4 */
- __BFP(ucrc); /* offset 0xc8 */
- __BFP(uccnf); /* offset 0xcc */
- u32 __pad4[1];
- __BFP(version2); /* offset 0xd4 */
- u32 __pad5[10];
-
- /*
- * channel(mailbox) mask and message registers
- */
- struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
- struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
-};
-
-#undef __BFP
-
-/* CAN_CONTROL Masks */
-#define SRS 0x0001 /* Software Reset */
-#define DNM 0x0002 /* Device Net Mode */
-#define ABO 0x0004 /* Auto-Bus On Enable */
-#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
-#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
-#define SMR 0x0020 /* Sleep Mode Request */
-#define CSR 0x0040 /* CAN Suspend Mode Request */
-#define CCR 0x0080 /* CAN Configuration Mode Request */
-
-/* CAN_STATUS Masks */
-#define WT 0x0001 /* TX Warning Flag */
-#define WR 0x0002 /* RX Warning Flag */
-#define EP 0x0004 /* Error Passive Mode */
-#define EBO 0x0008 /* Error Bus Off Mode */
-#define SMA 0x0020 /* Sleep Mode Acknowledge */
-#define CSA 0x0040 /* Suspend Mode Acknowledge */
-#define CCA 0x0080 /* Configuration Mode Acknowledge */
-#define MBPTR 0x1F00 /* Mailbox Pointer */
-#define TRM 0x4000 /* Transmit Mode */
-#define REC 0x8000 /* Receive Mode */
-
-/* CAN_CLOCK Masks */
-#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
-
-/* CAN_TIMING Masks */
-#define TSEG1 0x000F /* Time Segment 1 */
-#define TSEG2 0x0070 /* Time Segment 2 */
-#define SAM 0x0080 /* Sampling */
-#define SJW 0x0300 /* Synchronization Jump Width */
-
-/* CAN_DEBUG Masks */
-#define DEC 0x0001 /* Disable CAN Error Counters */
-#define DRI 0x0002 /* Disable CAN RX Input */
-#define DTO 0x0004 /* Disable CAN TX Output */
-#define DIL 0x0008 /* Disable CAN Internal Loop */
-#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
-#define MRB 0x0020 /* Mode Read Back Enable */
-#define CDE 0x8000 /* CAN Debug Enable */
-
-/* CAN_CEC Masks */
-#define RXECNT 0x00FF /* Receive Error Counter */
-#define TXECNT 0xFF00 /* Transmit Error Counter */
-
-/* CAN_INTR Masks */
-#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
-#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
-#define GIRQ 0x0004 /* Global Interrupt */
-#define SMACK 0x0008 /* Sleep Mode Acknowledge */
-#define CANTX 0x0040 /* CAN TX Bus Value */
-#define CANRX 0x0080 /* CAN RX Bus Value */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
-#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define IDE 0x2000 /* Identifier Extension */
-#define RTR 0x4000 /* Remote Frame Transmission Request */
-#define AME 0x8000 /* Acceptance Mask Enable */
-
-/* CAN_MBxx_TIMESTAMP Masks */
-#define TSV 0xFFFF /* Timestamp */
-
-/* CAN_MBxx_LENGTH Masks */
-#define DLC 0x000F /* Data Length Code */
-
-/* CAN_AMxxH and CAN_AMxxL Masks */
-#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
-#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
-#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
-#define BASEID 0x1FFC /* Base Identifier */
-#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
-#define FMD 0x4000 /* Full Mask Data Field Enable */
-#define FDF 0x8000 /* Filter On Data Field Enable */
-
-/* CAN_MC1 Masks */
-#define MC0 0x0001 /* Enable Mailbox 0 */
-#define MC1 0x0002 /* Enable Mailbox 1 */
-#define MC2 0x0004 /* Enable Mailbox 2 */
-#define MC3 0x0008 /* Enable Mailbox 3 */
-#define MC4 0x0010 /* Enable Mailbox 4 */
-#define MC5 0x0020 /* Enable Mailbox 5 */
-#define MC6 0x0040 /* Enable Mailbox 6 */
-#define MC7 0x0080 /* Enable Mailbox 7 */
-#define MC8 0x0100 /* Enable Mailbox 8 */
-#define MC9 0x0200 /* Enable Mailbox 9 */
-#define MC10 0x0400 /* Enable Mailbox 10 */
-#define MC11 0x0800 /* Enable Mailbox 11 */
-#define MC12 0x1000 /* Enable Mailbox 12 */
-#define MC13 0x2000 /* Enable Mailbox 13 */
-#define MC14 0x4000 /* Enable Mailbox 14 */
-#define MC15 0x8000 /* Enable Mailbox 15 */
-
-/* CAN_MC2 Masks */
-#define MC16 0x0001 /* Enable Mailbox 16 */
-#define MC17 0x0002 /* Enable Mailbox 17 */
-#define MC18 0x0004 /* Enable Mailbox 18 */
-#define MC19 0x0008 /* Enable Mailbox 19 */
-#define MC20 0x0010 /* Enable Mailbox 20 */
-#define MC21 0x0020 /* Enable Mailbox 21 */
-#define MC22 0x0040 /* Enable Mailbox 22 */
-#define MC23 0x0080 /* Enable Mailbox 23 */
-#define MC24 0x0100 /* Enable Mailbox 24 */
-#define MC25 0x0200 /* Enable Mailbox 25 */
-#define MC26 0x0400 /* Enable Mailbox 26 */
-#define MC27 0x0800 /* Enable Mailbox 27 */
-#define MC28 0x1000 /* Enable Mailbox 28 */
-#define MC29 0x2000 /* Enable Mailbox 29 */
-#define MC30 0x4000 /* Enable Mailbox 30 */
-#define MC31 0x8000 /* Enable Mailbox 31 */
-
-/* CAN_MD1 Masks */
-#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
-#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
-#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
-#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
-#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
-#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
-#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
-#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
-#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
-#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
-#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
-#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
-#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
-#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
-#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
-#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
-
-/* CAN_MD2 Masks */
-#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
-#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
-#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
-#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
-#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
-#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
-#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
-#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
-#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
-#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
-#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
-#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
-#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
-#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
-#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
-#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
-
-/* CAN_RMP1 Masks */
-#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
-#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
-#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
-#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
-#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
-#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
-#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
-#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
-#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
-#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
-#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
-#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
-#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
-#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
-#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
-#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
-
-/* CAN_RMP2 Masks */
-#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
-#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
-#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
-#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
-#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
-#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
-#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
-#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
-#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
-#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
-#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
-#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
-#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
-#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
-#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
-#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
-
-/* CAN_RML1 Masks */
-#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
-#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
-#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
-#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
-#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
-#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
-#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
-#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
-#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
-#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
-#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
-#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
-#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
-#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
-#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
-#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
-
-/* CAN_RML2 Masks */
-#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
-#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
-#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
-#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
-#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
-#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
-#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
-#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
-#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
-#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
-#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
-#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
-#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
-#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
-#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
-#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
-
-/* CAN_OPSS1 Masks */
-#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
-#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
-#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
-#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
-#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
-#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
-#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
-#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
-#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
-#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
-#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
-#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
-#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
-#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
-#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
-#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
-
-/* CAN_OPSS2 Masks */
-#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
-#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
-#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
-#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
-#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
-#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
-#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
-#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
-#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
-#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
-#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
-#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
-#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
-#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
-#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
-#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
-
-/* CAN_TRR1 Masks */
-#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
-#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
-#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
-#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
-#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
-#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
-#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
-#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
-#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
-#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
-#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
-#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
-#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
-#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
-#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
-#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
-
-/* CAN_TRR2 Masks */
-#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
-#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
-#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
-#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
-#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
-#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
-#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
-#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
-#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
-#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
-#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
-#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
-#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
-#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
-#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
-#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
-
-/* CAN_TRS1 Masks */
-#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
-#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
-#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
-#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
-#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
-#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
-#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
-#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
-#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
-#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
-#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
-#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
-#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
-#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
-#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
-#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
-
-/* CAN_TRS2 Masks */
-#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
-#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
-#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
-#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
-#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
-#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
-#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
-#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
-#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
-#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
-#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
-#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
-#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
-#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
-#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
-#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
-
-/* CAN_AA1 Masks */
-#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
-#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
-#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
-#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
-#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
-#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
-#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
-#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
-#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
-#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
-#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
-#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
-#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
-#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
-#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
-#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
-
-/* CAN_AA2 Masks */
-#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
-#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
-#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
-#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
-#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
-#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
-#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
-#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
-#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
-#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
-#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
-#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
-#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
-#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
-#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
-#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
-
-/* CAN_TA1 Masks */
-#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
-#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
-#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
-#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
-#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
-#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
-#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
-#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
-#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
-#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
-#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
-#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
-#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
-#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
-#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
-#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
-
-/* CAN_TA2 Masks */
-#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
-#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
-#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
-#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
-#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
-#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
-#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
-#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
-#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
-#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
-#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
-#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
-#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
-#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
-#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
-#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
-
-/* CAN_MBTD Masks */
-#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
-#define TDA 0x0040 /* Temporary Disable Acknowledge */
-#define TDR 0x0080 /* Temporary Disable Request */
-
-/* CAN_RFH1 Masks */
-#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
-#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
-#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
-#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
-#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
-#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
-#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
-#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
-#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
-#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
-#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
-#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
-#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
-#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
-#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
-#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
-
-/* CAN_RFH2 Masks */
-#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
-#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
-#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
-#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
-#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
-#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
-#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
-#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
-#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
-#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
-#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
-#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
-#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
-#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
-#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
-#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
-
-/* CAN_MBTIF1 Masks */
-#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
-#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
-#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
-#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
-#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
-#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
-#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
-#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
-#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
-#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
-#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
-#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
-#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
-#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
-#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
-#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBTIF2 Masks */
-#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
-#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
-#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
-#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
-#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
-#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
-#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
-#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
-#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
-#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
-#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
-#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
-#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
-#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
-#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
-#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBRIF1 Masks */
-#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
-#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
-#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
-#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
-#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
-#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
-#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
-#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
-#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
-#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
-#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
-#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
-#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
-#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
-#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
-#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
-
-/* CAN_MBRIF2 Masks */
-#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
-#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
-#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
-#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
-#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
-#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
-#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
-#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
-#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
-#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
-#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
-#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
-#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
-#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
-#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
-#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
-
-/* CAN_MBIM1 Masks */
-#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
-#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
-#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
-#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
-#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
-#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
-#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
-#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
-#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
-#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
-#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
-#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
-#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
-#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
-#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
-#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
-
-/* CAN_MBIM2 Masks */
-#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
-#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
-#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
-#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
-#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
-#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
-#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
-#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
-#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
-#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
-#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
-#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
-#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
-#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
-#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
-#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
-
-/* CAN_GIM Masks */
-#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
-#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
-#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
-#define BOIM 0x0008 /* Enable Bus Off Interrupt */
-#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
-#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
-#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
-#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
-#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
-#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
-#define ADIM 0x0400 /* Enable Access Denied Interrupt */
-
-/* CAN_GIS Masks */
-#define EWTIS 0x0001 /* TX Error Count IRQ Status */
-#define EWRIS 0x0002 /* RX Error Count IRQ Status */
-#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
-#define BOIS 0x0008 /* Bus Off IRQ Status */
-#define WUIS 0x0010 /* Wake-Up IRQ Status */
-#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
-#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
-#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
-#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
-#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
-#define ADIS 0x0400 /* Access Denied IRQ Status */
-
-/* CAN_GIF Masks */
-#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
-#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
-#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
-#define BOIF 0x0008 /* Bus Off IRQ Flag */
-#define WUIF 0x0010 /* Wake-Up IRQ Flag */
-#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
-#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
-#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
-#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
-#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
-#define ADIF 0x0400 /* Access Denied IRQ Flag */
-
-/* CAN_UCCNF Masks */
-#define UCCNF 0x000F /* Universal Counter Mode */
-#define UC_STAMP 0x0001 /* Timestamp Mode */
-#define UC_WDOG 0x0002 /* Watchdog Mode */
-#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
-#define UC_ERROR 0x0006 /* CAN Error Frame Count */
-#define UC_OVER 0x0007 /* CAN Overload Frame Count */
-#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
-#define UC_AA 0x0009 /* TX Abort Count */
-#define UC_TA 0x000A /* TX Successful Count */
-#define UC_REJECT 0x000B /* RX Message Rejected Count */
-#define UC_RML 0x000C /* RX Message Lost Count */
-#define UC_RX 0x000D /* Total Successful RX Messages Count */
-#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
-#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
-#define UCRC 0x0020 /* Universal Counter Reload/Clear */
-#define UCCT 0x0040 /* Universal Counter CAN Trigger */
-#define UCE 0x0080 /* Universal Counter Enable */
-
-/* CAN_ESR Masks */
-#define ACKE 0x0004 /* Acknowledge Error */
-#define SER 0x0008 /* Stuff Error */
-#define CRCE 0x0010 /* CRC Error */
-#define SA0 0x0020 /* Stuck At Dominant Error */
-#define BEF 0x0040 /* Bit Error Flag */
-#define FER 0x0080 /* Form Error Flag */
-
-/* CAN_EWR Masks */
-#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
-#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
deleted file mode 100644
index 6319f4e49083..000000000000
--- a/arch/blackfin/include/asm/bfin_dma.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * bfin_dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_DMA_H__
-#define __ASM_BFIN_DMA_H__
-
-#include <linux/types.h>
-
-/* DMA_CONFIG Masks */
-#define DMAEN 0x0001 /* DMA Channel Enable */
-#define WNR 0x0002 /* Channel Direction (W/R*) */
-#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
-#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
-
-#ifdef CONFIG_BF60x
-
-#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
-#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
-#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
-#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
-#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
-#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
-#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
-#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
-#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
-#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
-#define DI_EN DI_EN_X /* Data Interrupt Enable */
-#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
-#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
-#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
-#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
-#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
-#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
-#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
-#define NDSIZE 0x00070000 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
-#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
-#define DMAFLOW_LARGE DMAFLOW_LIST
-#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
-#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
-#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
-#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
-#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
-#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
-#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
-
-#else
-
-#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
-#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
-#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
-#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
-#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
-#define RESTART 0x0020 /* DMA Buffer Clear */
-#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
-#define DI_EN 0x0080 /* Data Interrupt Enable */
-#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
-#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
-#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
-#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
-#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
-#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
-#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
-#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
-#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
-#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
-#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
-#define NDSIZE 0x0f00 /* Next Descriptor Size */
-#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
-#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
-#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
-#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
-
-#endif
-#define DMAFLOW 0x7000 /* Flow Control */
-#define DMAFLOW_STOP 0x0000 /* Stop Mode */
-#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
-
-/* DMA_IRQ_STATUS Masks */
-#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
-#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
-#ifdef CONFIG_BF60x
-#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
-#else
-#define DMA_PIRQ 0
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin dma registers layout
- */
-struct bfin_dma_regs {
- u32 next_desc_ptr;
- u32 start_addr;
-#ifdef CONFIG_BF60x
- u32 cfg;
- u32 x_count;
- u32 x_modify;
- u32 y_count;
- u32 y_modify;
- u32 pad1;
- u32 pad2;
- u32 curr_desc_ptr;
- u32 prev_desc_ptr;
- u32 curr_addr;
- u32 irq_status;
- u32 curr_x_count;
- u32 curr_y_count;
- u32 pad3;
- u32 bw_limit_count;
- u32 curr_bw_limit_count;
- u32 bw_monitor_count;
- u32 curr_bw_monitor_count;
-#else
- __BFP(config);
- u32 __pad0;
- __BFP(x_count);
- __BFP(x_modify);
- __BFP(y_count);
- __BFP(y_modify);
- u32 curr_desc_ptr;
- u32 curr_addr;
- __BFP(irq_status);
- __BFP(peripheral_map);
- __BFP(curr_x_count);
- u32 __pad1;
- __BFP(curr_y_count);
- u32 __pad2;
-#endif
-};
-
-#ifndef CONFIG_BF60x
-/*
- * bfin handshake mdma registers layout
- */
-struct bfin_hmdma_regs {
- __BFP(control);
- __BFP(ecinit);
- __BFP(bcinit);
- __BFP(ecurgent);
- __BFP(ecoverflow);
- __BFP(ecount);
- __BFP(bcount);
-};
-#endif
-
-#undef __BFP
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
deleted file mode 100644
index bf52e1f32257..000000000000
--- a/arch/blackfin/include/asm/bfin_pfmon.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Blackfin Performance Monitor definitions
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef __ASM_BFIN_PFMON_H__
-#define __ASM_BFIN_PFMON_H__
-
-/* PFCTL Masks */
-#define PFMON_MASK 0xff
-#define PFCEN_MASK 0x3
-#define PFCEN_DISABLE 0x0
-#define PFCEN_ENABLE_USER 0x1
-#define PFCEN_ENABLE_SUPV 0x2
-#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
-
-#define PFPWR_P 0
-#define PEMUSW0_P 2
-#define PFCEN0_P 3
-#define PFMON0_P 5
-#define PEMUSW1_P 13
-#define PFCEN1_P 14
-#define PFMON1_P 16
-#define PFCNT0_P 24
-#define PFCNT1_P 25
-
-#define PFPWR (1 << PFPWR_P)
-#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
-#define PEMUSW0 PEMUSW(0, 1)
-#define PEMUSW1 PEMUSW(1, 1)
-#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
-#define PFCEN0 PFCEN(0, PFCEN_MASK)
-#define PFCEN1 PFCEN(1, PFCEN_MASK)
-#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
-#define PFCNT0 PFCNT(0, 1)
-#define PFCNT1 PFCNT(1, 1)
-#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
-#define PFMON0 PFMON(0, PFMON_MASK)
-#define PFMON1 PFMON(1, PFMON_MASK)
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
deleted file mode 100644
index a4e872e16e75..000000000000
--- a/arch/blackfin/include/asm/bfin_ppi.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * bfin_ppi.h - interface to Blackfin PPIs
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PPI_H__
-#define __ASM_BFIN_PPI_H__
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin ppi registers layout
- */
-struct bfin_ppi_regs {
- __BFP(control);
- __BFP(status);
- __BFP(count);
- __BFP(delay);
- __BFP(frame);
-};
-
-/*
- * bfin eppi registers layout
- */
-struct bfin_eppi_regs {
- __BFP(status);
- __BFP(hcount);
- __BFP(hdelay);
- __BFP(vcount);
- __BFP(vdelay);
- __BFP(frame);
- __BFP(line);
- __BFP(clkdiv);
- u32 control;
- u32 fs1w_hbl;
- u32 fs1p_avpl;
- u32 fs2w_lvb;
- u32 fs2p_lavf;
- u32 clip;
-};
-
-/*
- * bfin eppi3 registers layout
- */
-struct bfin_eppi3_regs {
- u32 stat;
- u32 hcnt;
- u32 hdly;
- u32 vcnt;
- u32 vdly;
- u32 frame;
- u32 line;
- u32 clkdiv;
- u32 ctl;
- u32 fs1_wlhb;
- u32 fs1_paspl;
- u32 fs2_wlvb;
- u32 fs2_palpf;
- u32 imsk;
- u32 oddclip;
- u32 evenclip;
- u32 fs1_dly;
- u32 fs2_dly;
- u32 ctl2;
-};
-
-#undef __BFP
-
-#ifdef EPPI0_CTL2
-#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
-#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
-#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
-#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
-#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
-#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
-#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
-#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
-#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
-#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
-
-#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
-
-#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
-
-#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
-
-#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
-
-#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
-
-#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
-
-#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
-
-#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
-#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
-#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
-#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
-#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
-#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
-#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
-#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
-#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
-#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
-#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
-#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
-#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
-#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
-#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
-#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
-#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
-#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
-#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
-#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
-#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
-#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
-#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
-#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
-#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
-#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
-#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
-#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
-#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
-#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
-#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
-#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
-#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
-#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
-#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
-#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
-#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
-#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
-#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
-#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
-#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
-#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
-#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
-#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
-#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
-#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
-#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
-#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
-
-#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
-#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
-#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
-#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
-
-#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
-#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
-
-#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
-#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
-#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
-#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
-#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
-#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
-#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
-
-#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
-#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
-
-#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
-#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
-
-#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
deleted file mode 100644
index a99957ea9e9b..000000000000
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Blackfin Secure Digital Host (SDH) definitions
- *
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SDH_H__
-#define __BFIN_SDH_H__
-
-/* Platform resources */
-struct bfin_sd_host {
- int dma_chan;
- int irq_int0;
- int irq_int1;
- u16 pin_req[7];
-};
-
-/* SDH_COMMAND bitmasks */
-#define CMD_IDX 0x3f /* Command Index */
-#define CMD_RSP (1 << 6) /* Response */
-#define CMD_L_RSP (1 << 7) /* Long Response */
-#define CMD_INT_E (1 << 8) /* Command Interrupt */
-#define CMD_PEND_E (1 << 9) /* Command Pending */
-#define CMD_E (1 << 10) /* Command Enable */
-#ifdef RSI_BLKSZ
-#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */
-#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */
-#endif
-
-/* SDH_PWR_CTL bitmasks */
-#ifndef RSI_BLKSZ
-#define PWR_ON 0x3 /* Power On */
-#define SD_CMD_OD (1 << 6) /* Open Drain Output */
-#define ROD_CTL (1 << 7) /* Rod Control */
-#endif
-
-/* SDH_CLK_CTL bitmasks */
-#define CLKDIV 0xff /* MC_CLK Divisor */
-#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
-#define PWR_SV_E (1 << 9) /* Power Save Enable */
-#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
-#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
-#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
-#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
-#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
-
-/* SDH_RESP_CMD bitmasks */
-#define RESP_CMD 0x3f /* Response Command */
-
-/* SDH_DATA_CTL bitmasks */
-#define DTX_E (1 << 0) /* Data Transfer Enable */
-#define DTX_DIR (1 << 1) /* Data Transfer Direction */
-#define DTX_MODE (1 << 2) /* Data Transfer Mode */
-#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
-#ifndef RSI_BLKSZ
-#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
-#else
-
-/* Bit masks for SDH_BLK_SIZE */
-#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
-#endif
-
-/* SDH_STATUS bitmasks */
-#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
-#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
-#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
-#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
-#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
-#define RX_OVERRUN (1 << 5) /* Receive Overrun */
-#define CMD_RESP_END (1 << 6) /* CMD Response End */
-#define CMD_SENT (1 << 7) /* CMD Sent */
-#define DAT_END (1 << 8) /* Data End */
-#define START_BIT_ERR (1 << 9) /* Start Bit Error */
-#define DAT_BLK_END (1 << 10) /* Data Block End */
-#define CMD_ACT (1 << 11) /* CMD Active */
-#define TX_ACT (1 << 12) /* Transmit Active */
-#define RX_ACT (1 << 13) /* Receive Active */
-#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
-#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
-#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
-#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
-#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
-#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
-#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
-#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
-
-/* SDH_STATUS_CLR bitmasks */
-#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
-#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
-#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
-#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
-#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
-#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
-#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
-#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
-#define DAT_END_STAT (1 << 8) /* Data End Status */
-#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
-#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
-
-/* SDH_MASK0 bitmasks */
-#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
-#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
-#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
-#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
-#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
-#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
-#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
-#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
-#define DAT_END_MASK (1 << 8) /* Data End Mask */
-#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
-#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
-#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
-#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
-#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
-#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
-#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
-#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
-#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
-#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
-#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
-#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
-#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
-
-/* SDH_FIFO_CNT bitmasks */
-#define FIFO_COUNT 0x7fff /* FIFO Count */
-
-/* SDH_E_STATUS bitmasks */
-#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
-#define SD_CARD_DET (1 << 4) /* SD Card Detect */
-#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */
-#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
-#define SD_CARD_READY (1 << 17) /* Card Ready */
-
-/* SDH_E_MASK bitmasks */
-#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
-#define SCD_MSK (1 << 4) /* Mask Card Detect */
-#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */
-
-/* SDH_CFG bitmasks */
-#define CLKS_EN (1 << 0) /* Clocks Enable */
-#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
-#define MWE (1 << 3) /* Moving Window Enable */
-#define SD_RST (1 << 4) /* SDMMC Reset */
-#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
-#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
-#ifndef RSI_BLKSZ
-#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
-#else
-#define PWR_ON 0x600 /* Power On */
-#define SD_CMD_OD (1 << 11) /* Open Drain Output */
-#define BOOT_EN (1 << 12) /* Boot Enable */
-#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
-#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */
-#endif
-
-/* SDH_RD_WAIT_EN bitmasks */
-#define RWR (1 << 0) /* Read Wait Request */
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
deleted file mode 100644
index b550ada7321b..000000000000
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/*
- * bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ASM_SERIAL_H__
-#define __BFIN_ASM_SERIAL_H__
-
-#include <linux/circ_buf.h>
-#include <linux/serial_core.h>
-#include <linux/spinlock.h>
-#include <linux/timer.h>
-#include <linux/workqueue.h>
-#include <mach/anomaly.h>
-#include <mach/bfin_serial.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
- defined(CONFIG_BFIN_UART1_CTSRTS) || \
- defined(CONFIG_BFIN_UART2_CTSRTS) || \
- defined(CONFIG_BFIN_UART3_CTSRTS)
-# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
-# define SERIAL_BFIN_HARD_CTSRTS
-# else
-# define SERIAL_BFIN_CTSRTS
-# endif
-#endif
-
-struct bfin_serial_port {
- struct uart_port port;
- unsigned int old_status;
- int tx_irq;
- int rx_irq;
- int status_irq;
-#ifndef BFIN_UART_BF54X_STYLE
- unsigned int lsr;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_DMA
- int tx_done;
- int tx_count;
- struct circ_buf rx_dma_buf;
- struct timer_list rx_dma_timer;
- int rx_dma_nrows;
- spinlock_t rx_lock;
- unsigned int tx_dma_channel;
- unsigned int rx_dma_channel;
- struct work_struct tx_dma_workqueue;
-#elif ANOMALY_05000363
- unsigned int anomaly_threshold;
-#endif
-#if defined(SERIAL_BFIN_CTSRTS) || \
- defined(SERIAL_BFIN_HARD_CTSRTS)
- int cts_pin;
- int rts_pin;
-#endif
-};
-
-#ifdef BFIN_UART_BF60X_STYLE
-
-/* UART_CTL Masks */
-#define UCEN 0x1 /* Enable UARTx Clocks */
-#define LOOP_ENA 0x2 /* Loopback Mode Enable */
-#define UMOD_MDB 0x10 /* Enable MDB Mode */
-#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
-#define UMOD_MASK 0x30 /* Uart Mode Mask */
-#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
-#define WLS_MASK 0x300 /* Word length Select Mask */
-#define WLS_OFFSET 8 /* Word length Select Offset */
-#define STB 0x1000 /* Stop Bits */
-#define STBH 0x2000 /* Half Stop Bits */
-#define PEN 0x4000 /* Parity Enable */
-#define EPS 0x8000 /* Even Parity Select */
-#define STP 0x10000 /* Stick Parity */
-#define FPE 0x20000 /* Force Parity Error On Transmit */
-#define FFE 0x40000 /* Force Framing Error On Transmit */
-#define SB 0x80000 /* Set Break */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-#define FCPOL 0x400000 /* Flow Control Pin Polarity */
-#define RPOLC 0x800000 /* IrDA RX Polarity Change */
-#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
-#define MRTS 0x2000000 /* Manual Request To Send */
-#define XOFF 0x4000000 /* Transmitter Off */
-#define ARTS 0x8000000 /* Automatic Request To Send */
-#define ACTS 0x10000000 /* Automatic Clear To Send */
-#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
-
-/* UART_STAT Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x80 /* TSR and UART_THR Empty */
-#define TFI 0x100 /* Transmission Finished Indicator */
-
-#define ASTKY 0x200 /* Address Sticky */
-#define ADDR 0x400 /* Address bit status */
-#define RO 0x800 /* Reception Ongoing */
-#define SCTS 0x1000 /* Sticky CTS */
-#define CTS 0x10000 /* Clear To Send */
-#define RFCS 0x20000 /* Receive FIFO Count Status */
-
-/* UART_CLOCK Masks */
-#define EDBO 0x80000000 /* Enable Devide by One */
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-/* UART_LCR Masks */
-#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
-#define WLS_MASK 0x03 /* Word length Select Mask */
-#define WLS_OFFSET 0 /* Word length Select Offset */
-#define STB 0x04 /* Stop Bits */
-#define PEN 0x08 /* Parity Enable */
-#define EPS 0x10 /* Even Parity Select */
-#define STP 0x20 /* Stick Parity */
-#define SB 0x40 /* Set Break */
-#define DLAB 0x80 /* Divisor Latch Access */
-#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
-
-/* UART_LSR Masks */
-#define DR 0x01 /* Data Ready */
-#define OE 0x02 /* Overrun Error */
-#define PE 0x04 /* Parity Error */
-#define FE 0x08 /* Framing Error */
-#define BI 0x10 /* Break Interrupt */
-#define THRE 0x20 /* THR Empty */
-#define TEMT 0x40 /* TSR and UART_THR Empty */
-#define TFI 0x80 /* Transmission Finished Indicator */
-
-/* UART_MCR Masks */
-#define XOFF 0x01 /* Transmitter Off */
-#define MRTS 0x02 /* Manual Request To Send */
-#define RFIT 0x04 /* Receive FIFO IRQ Threshold */
-#define RFRT 0x08 /* Receive FIFO RTS Threshold */
-#define LOOP_ENA 0x10 /* Loopback Mode Enable */
-#define FCPOL 0x20 /* Flow Control Pin Polarity */
-#define ARTS 0x40 /* Automatic Request To Send */
-#define ACTS 0x80 /* Automatic Clear To Send */
-
-/* UART_MSR Masks */
-#define SCTS 0x01 /* Sticky CTS */
-#define CTS 0x10 /* Clear To Send */
-#define RFCS 0x20 /* Receive FIFO Count Status */
-
-/* UART_GCTL Masks */
-#define UCEN 0x01 /* Enable UARTx Clocks */
-#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
-#define UMOD_MASK 0x02 /* Uart Mode Mask */
-#define TPOLC 0x04 /* IrDA TX Polarity Change */
-#define RPOLC 0x08 /* IrDA RX Polarity Change */
-#define FPE 0x10 /* Force Parity Error On Transmit */
-#define FFE 0x20 /* Force Framing Error On Transmit */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-/* UART_IER Masks */
-#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
-#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI 0x04 /* Enable RX Status Interrupt */
-#define EDSSI 0x08 /* Enable Modem Status Interrupt */
-#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
-#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
-#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
-
-#if defined(BFIN_UART_BF60X_STYLE)
-# define OFFSET_REDIV 0x00 /* Version ID Register */
-# define OFFSET_CTL 0x04 /* Control Register */
-# define OFFSET_STAT 0x08 /* Status Register */
-# define OFFSET_SCR 0x0C /* SCR Scratch Register */
-# define OFFSET_CLK 0x10 /* Clock Rate Register */
-# define OFFSET_IER 0x14 /* Interrupt Enable Register */
-# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
-# define OFFSET_RBR 0x20 /* Receive Buffer register */
-# define OFFSET_THR 0x24 /* Transmit Holding register */
-#elif defined(BFIN_UART_BF54X_STYLE)
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_GCTL 0x08 /* Global Control Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
-# define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
-# define OFFSET_THR 0x28 /* Transmit Holding register */
-# define OFFSET_RBR 0x2C /* Receive Buffer register */
-#else /* BF533 style */
-# define OFFSET_THR 0x00 /* Transmit Holding register */
-# define OFFSET_RBR 0x00 /* Receive Buffer register */
-# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-# define OFFSET_IER 0x04 /* Interrupt Enable Register */
-# define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-# define OFFSET_LCR 0x0C /* Line Control Register */
-# define OFFSET_MCR 0x10 /* Modem Control Register */
-# define OFFSET_LSR 0x14 /* Line Status Register */
-# define OFFSET_MSR 0x18 /* Modem Status Register */
-# define OFFSET_SCR 0x1C /* SCR Scratch Register */
-# define OFFSET_GCTL 0x24 /* Global Control Register */
-/* code should not need IIR, so force build error if they use it */
-# undef OFFSET_IIR
-#endif
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct bfin_uart_regs {
-#if defined(BFIN_UART_BF60X_STYLE)
- u32 revid;
- u32 ctl;
- u32 stat;
- u32 scr;
- u32 clk;
- u32 ier;
- u32 ier_set;
- u32 ier_clear;
- u32 rbr;
- u32 thr;
- u32 taip;
- u32 tsr;
- u32 rsr;
- u32 txdiv;
- u32 rxdiv;
-#elif defined(BFIN_UART_BF54X_STYLE)
- __BFP(dll);
- __BFP(dlh);
- __BFP(gctl);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- __BFP(ier_set);
- __BFP(ier_clear);
- __BFP(thr);
- __BFP(rbr);
-#else
- union {
- u16 dll;
- u16 thr;
- const u16 rbr;
- };
- const u16 __pad0;
- union {
- u16 dlh;
- u16 ier;
- };
- const u16 __pad1;
- const __BFP(iir);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- const u32 __pad2;
- __BFP(gctl);
-#endif
-};
-#undef __BFP
-
-#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
-
-/*
-#ifndef port_membase
-# define port_membase(p) 0
-#endif
-*/
-#ifdef BFIN_UART_BF60X_STYLE
-
-#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
-#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
-#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
-#define UART_GET_GCTL(p) UART_GET_CTL(p)
-#define UART_GET_LCR(p) UART_GET_CTL(p)
-#define UART_GET_MCR(p) UART_GET_CTL(p)
-#if ANOMALY_16000030
-#define UART_GET_STAT(p) \
-({ \
- u32 __ret; \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
- hard_local_irq_restore(flags); \
- __ret; \
-})
-#else
-#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
-#endif
-#define UART_GET_MSR(p) UART_GET_STAT(p)
-
-#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
-#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
-#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
-#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
-
-#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
-#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
-
-#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
-#define UART_GET_LSR(p) UART_GET_STAT(p)
-#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BFIN_UART_BF60X_STYLE */
-
-#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
-#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
-#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
-#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
-#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
-#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
-#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
-#define UART_GET_MSR(p) bfin_read16(port_membase(p) + OFFSET_MSR)
-
-#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
-#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
-#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
-#define UART_PUT_CLK(p, v) do \
-{\
-UART_PUT_DLL(p, v & 0xFF); \
-UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
-
-#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
-#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
-#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
-
-#ifdef BFIN_UART_BF54X_STYLE
-
-#define UART_CLEAR_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER_SET)
-#define UART_SET_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
-
-#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF54x */
-#define UART_SET_DLAB(p) /* MMRs not muxed on BF54x */
-
-#define UART_CLEAR_LSR(p) bfin_write16(port_membase(p) + OFFSET_LSR, -1)
-#define UART_GET_LSR(p) bfin_read16(port_membase(p) + OFFSET_LSR)
-#define UART_PUT_LSR(p, v) bfin_write16(port_membase(p) + OFFSET_LSR, v)
-
-/* This handles hard CTS/RTS */
-#define BFIN_UART_CTSRTS_HARD
-#define UART_CLEAR_SCTS(p) bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#else /* BF533 style */
-
-#define UART_CLEAR_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
-#define UART_GET_IER(p) bfin_read16(port_membase(p) + OFFSET_IER)
-#define UART_PUT_IER(p, v) bfin_write16(port_membase(p) + OFFSET_IER, v)
-#define UART_SET_IER(p, v) UART_PUT_IER(p, UART_GET_IER(p) | (v))
-
-#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
-#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
-
-#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
-#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
-
-/*
-#ifndef put_lsr_cache
-# define put_lsr_cache(p, v)
-#endif
-#ifndef get_lsr_cache
-# define get_lsr_cache(p) 0
-#endif
-*/
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline void UART_CLEAR_LSR(void *p)
-{
- put_lsr_cache(p, 0);
- bfin_write16(port_membase(p) + OFFSET_LSR, -1);
-}
-static inline unsigned int UART_GET_LSR(void *p)
-{
- unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
- put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
- return lsr | get_lsr_cache(p);
-}
-static inline void UART_PUT_LSR(void *p, uint16_t val)
-{
- put_lsr_cache(p, get_lsr_cache(p) & ~val);
-}
-
-/* This handles soft CTS/RTS */
-#define UART_GET_CTS(x) gpio_get_value((x)->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value((x)->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value((x)->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#endif /* BFIN_UART_BF54X_STYLE */
-
-#endif /* BFIN_UART_BF60X_STYLE */
-
-#ifndef BFIN_UART_TX_FIFO_SIZE
-# define BFIN_UART_TX_FIFO_SIZE 2
-#endif
-
-#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
deleted file mode 100644
index b2d5e733079e..000000000000
--- a/arch/blackfin/include/asm/bfin_simple_timer.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _bfin_simple_timer_h_
-#define _bfin_simple_timer_h_
-
-#include <linux/ioctl.h>
-
-#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
-
-#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 2)
-#define BFIN_SIMPLE_TIMER_SET_WIDTH _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 3)
-#define BFIN_SIMPLE_TIMER_SET_MODE _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 4)
-#define BFIN_SIMPLE_TIMER_START _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 6)
-#define BFIN_SIMPLE_TIMER_STOP _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 8)
-#define BFIN_SIMPLE_TIMER_READ _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
-#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11)
-
-#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT 0
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT 1
-#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP 2
-#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ 3
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
deleted file mode 100644
index 50b9dfd4839f..000000000000
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_SPORT_H__
-#define __BFIN_SPORT_H__
-
-
-#include <linux/types.h>
-#include <uapi/asm/bfin_sport.h>
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct sport_register {
- __BFP(tcr1);
- __BFP(tcr2);
- __BFP(tclkdiv);
- __BFP(tfsdiv);
- union {
- u32 tx32;
- u16 tx16;
- };
- u32 __pad_tx;
- union {
- u32 rx32; /* use the anomaly wrapper below */
- u16 rx16;
- };
- u32 __pad_rx;
- __BFP(rcr1);
- __BFP(rcr2);
- __BFP(rclkdiv);
- __BFP(rfsdiv);
- __BFP(stat);
- __BFP(chnl);
- __BFP(mcmc1);
- __BFP(mcmc2);
- u32 mtcs0;
- u32 mtcs1;
- u32 mtcs2;
- u32 mtcs3;
- u32 mrcs0;
- u32 mrcs1;
- u32 mrcs2;
- u32 mrcs3;
-};
-#undef __BFP
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#define bfin_read_sport_rx32(base) \
-({ \
- struct sport_register *__mmrs = (void *)base; \
- u32 __ret; \
- unsigned long flags; \
- if (ANOMALY_05000473) \
- local_irq_save(flags); \
- __ret = __mmrs->rx32; \
- if (ANOMALY_05000473) \
- local_irq_restore(flags); \
- __ret; \
-})
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h
deleted file mode 100644
index d82f5fa0ad9f..000000000000
--- a/arch/blackfin/include/asm/bfin_sport3.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * bfin_sport - Analog Devices BF6XX SPORT registers
- *
- * Copyright (c) 2012 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _BFIN_SPORT3_H_
-#define _BFIN_SPORT3_H_
-
-#include <linux/types.h>
-
-#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
-#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
-#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
-#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
-#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
-#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
-#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
-#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
-#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
-#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
-#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
-#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
-#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
-#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
-#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
-#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
-#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
-#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
-#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
-#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrupt enable select */
-#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
-#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
-#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
-#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
-#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
-#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
-#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
-#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
-#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
-#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
-#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
-#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
-#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
-
-#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
-#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
-
-#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
-#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
-#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
-#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
-#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
-
-#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
-#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
-
-#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
-#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
-#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
-#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
-#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
-#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
-
-#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
-
-#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
-#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
-#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
-
-struct sport_register {
- u32 spctl;
- u32 div;
- u32 spmctl;
- u32 spcs0;
- u32 spcs1;
- u32 spcs2;
- u32 spcs3;
- u32 spcnt;
- u32 sperrctl;
- u32 spmstat;
- u32 spctl2;
- u32 txa;
- u32 rxa;
- u32 txb;
- u32 rxb;
- u32 revid;
-};
-
-struct bfin_snd_platform_data {
- const unsigned short *pin_req;
-};
-
-#endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
deleted file mode 100644
index 211e9c78f6fb..000000000000
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * bfin_twi.h - interface to Blackfin TWIs
- *
- * Copyright 2005-2014 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_TWI_H__
-#define __ASM_BFIN_TWI_H__
-
-#include <asm/blackfin.h>
-#include <linux/types.h>
-#include <linux/i2c.h>
-
-/*
- * ADI twi registers layout
- */
-struct bfin_twi_regs {
- u16 clkdiv;
- u16 dummy1;
- u16 control;
- u16 dummy2;
- u16 slave_ctl;
- u16 dummy3;
- u16 slave_stat;
- u16 dummy4;
- u16 slave_addr;
- u16 dummy5;
- u16 master_ctl;
- u16 dummy6;
- u16 master_stat;
- u16 dummy7;
- u16 master_addr;
- u16 dummy8;
- u16 int_stat;
- u16 dummy9;
- u16 int_mask;
- u16 dummy10;
- u16 fifo_ctl;
- u16 dummy11;
- u16 fifo_stat;
- u16 dummy12;
- u32 __pad[20];
- u16 xmt_data8;
- u16 dummy13;
- u16 xmt_data16;
- u16 dummy14;
- u16 rcv_data8;
- u16 dummy15;
- u16 rcv_data16;
- u16 dummy16;
-};
-
-struct bfin_twi_iface {
- int irq;
- spinlock_t lock;
- char read_write;
- u8 command;
- u8 *transPtr;
- int readNum;
- int writeNum;
- int cur_mode;
- int manual_stop;
- int result;
- struct i2c_adapter adap;
- struct completion complete;
- struct i2c_msg *pmsg;
- int msg_num;
- int cur_msg;
- u16 saved_clkdiv;
- u16 saved_control;
- struct bfin_twi_regs __iomem *regs_base;
-};
-
-/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
-#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
-#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA 0x0080 /* TWI Enable */
-#define SCCB 0x0200 /* SCCB Compatibility Enable */
-
-/* TWI_SLAVE_CTL Masks */
-#define SEN 0x0001 /* Slave Enable */
-#define SADD_LEN 0x0002 /* Slave Address Length */
-#define STDVAL 0x0004 /* Slave Transmit Data Valid */
-#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */
-#define GEN 0x0010 /* General Call Address Matching Enabled */
-
-/* TWI_SLAVE_STAT Masks */
-#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */
-#define GCALL 0x0002 /* General Call Indicator */
-
-/* TWI_MASTER_CTL Masks */
-#define MEN 0x0001 /* Master Mode Enable */
-#define MADD_LEN 0x0002 /* Master Address Length */
-#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
-#define FAST 0x0008 /* Use Fast Mode Timing Specs */
-#define STOP 0x0010 /* Issue Stop Condition */
-#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT 0x3FC0 /* Data Bytes To Transfer */
-#define SDAOVR 0x4000 /* Serial Data Override */
-#define SCLOVR 0x8000 /* Serial Clock Override */
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG 0x0001 /* Master Transfer In Progress */
-#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK 0x0004 /* Address Not Acknowledged */
-#define DNAK 0x0008 /* Data Not Acknowledged */
-#define BUFRDERR 0x0010 /* Buffer Read Error */
-#define BUFWRERR 0x0020 /* Buffer Write Error */
-#define SDASEN 0x0040 /* Serial Data Sense */
-#define SCLSEN 0x0080 /* Serial Clock Sense */
-#define BUSBUSY 0x0100 /* Bus Busy Indicator */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT 0x0001 /* Slave Transfer Initiated */
-#define SCOMP 0x0002 /* Slave Transfer Complete */
-#define SERR 0x0004 /* Slave Transfer Error */
-#define SOVF 0x0008 /* Slave Overflow */
-#define MCOMP 0x0010 /* Master Transfer Complete */
-#define MERR 0x0020 /* Master Transfer Error */
-#define XMTSERV 0x0040 /* Transmit FIFO Service */
-#define RCVSERV 0x0080 /* Receive FIFO Service */
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
-#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
-#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT 0x0003 /* Transmit FIFO Status */
-#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
-#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT 0x000C /* Receive FIFO Status */
-#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
-#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
-
-#define DEFINE_TWI_REG(reg_name, reg) \
-static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
- { return bfin_read16(&iface->regs_base->reg); } \
-static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
- { bfin_write16(&iface->regs_base->reg, v); }
-
-DEFINE_TWI_REG(CLKDIV, clkdiv)
-DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
-DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
-DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
-DEFINE_TWI_REG(MASTER_CTL, master_ctl)
-DEFINE_TWI_REG(MASTER_STAT, master_stat)
-DEFINE_TWI_REG(MASTER_ADDR, master_addr)
-DEFINE_TWI_REG(INT_STAT, int_stat)
-DEFINE_TWI_REG(INT_MASK, int_mask)
-DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
-DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
-DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
-#if !ANOMALY_16000030
-DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
-DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
-#else
-static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data8);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-
-static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
-{
- u16 ret;
- unsigned long flags;
-
- flags = hard_local_irq_save();
- ret = bfin_read16(&iface->regs_base->rcv_data16);
- hard_local_irq_restore(flags);
-
- return ret;
-}
-#endif
-
-static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->fifo_ctl);
-}
-
-static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
-{
- bfin_write16(&iface->regs_base->fifo_ctl, v);
- SSYNC();
-}
-
-static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
-{
- return bfin_read16(&iface->regs_base->control);
-}
-
-static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
-{
- SSYNC();
- bfin_write16(&iface->regs_base->control, v);
-}
-#endif
diff --git a/arch/blackfin/include/asm/bfin_watchdog.h b/arch/blackfin/include/asm/bfin_watchdog.h
deleted file mode 100644
index dce09829a095..000000000000
--- a/arch/blackfin/include/asm/bfin_watchdog.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * bfin_watchdog.h - Blackfin watchdog definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_WATCHDOG_H
-#define _BFIN_WATCHDOG_H
-
-/* Bit in SWRST that indicates boot caused by watchdog */
-#define SWRST_RESET_WDOG 0x4000
-
-/* Bit in WDOG_CTL that indicates watchdog has expired (WDR0) */
-#define WDOG_EXPIRED 0x8000
-
-/* Masks for WDEV field in WDOG_CTL register */
-#define ICTL_RESET 0x0
-#define ICTL_NMI 0x2
-#define ICTL_GPI 0x4
-#define ICTL_NONE 0x6
-#define ICTL_MASK 0x6
-
-/* Masks for WDEN field in WDOG_CTL register */
-#define WDEN_MASK 0x0FF0
-#define WDEN_ENABLE 0x0000
-#define WDEN_DISABLE 0x0AD0
-
-#endif
diff --git a/arch/blackfin/include/asm/bfrom.h b/arch/blackfin/include/asm/bfrom.h
deleted file mode 100644
index 9e4be5e5e767..000000000000
--- a/arch/blackfin/include/asm/bfrom.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Blackfin on-chip ROM API
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFROM_H__
-#define __BFROM_H__
-
-#include <linux/types.h>
-
-/* Possible syscontrol action flags */
-#define SYSCTRL_READ 0x00000000 /* read registers */
-#define SYSCTRL_WRITE 0x00000001 /* write registers */
-#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
-#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
-#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
-#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
-#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
-#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
-#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
-#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
-#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
-#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
-#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
-
-typedef struct ADI_SYSCTRL_VALUES {
- uint16_t uwVrCtl;
- uint16_t uwPllCtl;
- uint16_t uwPllDiv;
- uint16_t uwPllLockCnt;
- uint16_t uwPllStat;
-} ADI_SYSCTRL_VALUES;
-
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
-
-/* We need a dedicated function since we need to screw with the stack pointer
- * when resetting. The on-chip ROM will save/restore registers on the stack
- * when doing a system reset, so the stack cannot be outside of the chip.
- */
-__attribute__((__noreturn__))
-static inline void bfrom_SoftReset(void *new_stack)
-{
- while (1)
- /*
- * We don't declare the SP as clobbered on purpose, since
- * it confuses the heck out of the compiler, and this function
- * never returns
- */
- __asm__ __volatile__(
- "sp = %[stack];"
- "jump (%[bfrom_syscontrol]);"
- : : [bfrom_syscontrol] "p"(bfrom_SysControl),
- "q0"(SYSCTRL_SOFTRESET),
- "q1"(0),
- "q2"(NULL),
- [stack] "p"(new_stack)
- );
-}
-
-/* OTP Functions */
-static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
-static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
-static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
-
-/* otp command: defines for "command" */
-#define OTP_INIT 0x00000001
-#define OTP_CLOSE 0x00000002
-
-/* otp read/write: defines for "flags" */
-#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
-#define OTP_UPPER_HALF 0x00000001
-#define OTP_NO_ECC 0x00000010 /* do not use ECC */
-#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
-#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
-
-/* Return values for all functions */
-#define OTP_SUCCESS 0x00000000
-#define OTP_MASTER_ERROR 0x001
-#define OTP_WRITE_ERROR 0x003
-#define OTP_READ_ERROR 0x005
-#define OTP_ACC_VIO_ERROR 0x009
-#define OTP_DATA_MULT_ERROR 0x011
-#define OTP_ECC_MULT_ERROR 0x021
-#define OTP_PREV_WR_ERROR 0x041
-#define OTP_DATA_SB_WARN 0x100
-#define OTP_ECC_SB_WARN 0x200
-
-#endif
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
deleted file mode 100644
index b298b654a26f..000000000000
--- a/arch/blackfin/include/asm/bitops.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-#include <linux/compiler.h>
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/find.h>
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/const_hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#include <asm/barrier.h>
-
-#ifndef CONFIG_SMP
-#include <linux/irqflags.h>
-/*
- * clear_bit may not imply a memory barrier
- */
-#include <asm-generic/bitops/atomic.h>
-#include <asm-generic/bitops/non-atomic.h>
-#else
-
-#include <asm/byteorder.h> /* swab32 */
-#include <linux/linkage.h>
-
-asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr);
-
-asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr);
-
-static inline void set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_set_asm(a, nr & 0x1f);
-}
-
-static inline void clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_clear_asm(a, nr & 0x1f);
-}
-
-static inline void change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- __raw_bit_toggle_asm(a, nr & 0x1f);
-}
-
-static inline int test_bit(int nr, const volatile unsigned long *addr)
-{
- volatile const unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_asm(a, nr & 0x1f) != 0;
-}
-
-static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_set_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_clear_asm(a, nr & 0x1f);
-}
-
-static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
- volatile unsigned long *a = addr + (nr >> 5);
- return __raw_bit_test_toggle_asm(a, nr & 0x1f);
-}
-
-#define test_bit __skip_test_bit
-#include <asm-generic/bitops/non-atomic.h>
-#undef test_bit
-
-#endif /* CONFIG_SMP */
-
-/* Needs to be after test_bit and friends */
-#include <asm-generic/bitops/le.h>
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-static inline unsigned int __arch_hweight32(unsigned int w)
-{
- unsigned int res;
-
- __asm__ ("%0.l = ONES %1;"
- "%0 = %0.l (Z);"
- : "=d" (res) : "d" (w));
- return res;
-}
-
-static inline unsigned int __arch_hweight64(__u64 w)
-{
- return __arch_hweight32((unsigned int)(w >> 32)) +
- __arch_hweight32((unsigned int)w);
-}
-
-static inline unsigned int __arch_hweight16(unsigned int w)
-{
- return __arch_hweight32(w & 0xffff);
-}
-
-static inline unsigned int __arch_hweight8(unsigned int w)
-{
- return __arch_hweight32(w & 0xff);
-}
-
-#endif /* _BLACKFIN_BITOPS_H */
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
deleted file mode 100644
index f111f366d758..000000000000
--- a/arch/blackfin/include/asm/blackfin.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Common header file for Blackfin family of processors.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_H_
-#define _BLACKFIN_H_
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "ssync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
- int _tmp;
- if (ANOMALY_05000312 || ANOMALY_05000244)
- __asm__ __volatile__(
- "cli %0;"
- "nop;"
- "nop;"
- "nop;"
- "csync;"
- "sti %0;"
- : "=d" (_tmp)
- );
- else
- __asm__ __volatile__("csync;");
-}
-
-#else /* __ASSEMBLY__ */
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312 || ANOMALY_05000244
-#define SSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- SSYNC; \
- sti scratch;
-
-#define CSYNC(scratch) \
- cli scratch; \
- nop; nop; nop; \
- CSYNC; \
- sti scratch;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/mem_map.h>
-#include <mach/blackfin.h>
-#include <asm/bfin-global.h>
-
-#endif /* _BLACKFIN_H_ */
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
deleted file mode 100644
index 76b2e82ee730..000000000000
--- a/arch/blackfin/include/asm/bug.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_BUG_H
-#define _BLACKFIN_BUG_H
-
-#ifdef CONFIG_BUG
-
-/*
- * This can be any undefined 16-bit opcode, meaning
- * ((opcode & 0xc000) != 0xc000)
- * Anything from 0x0001 to 0x000A (inclusive) will work
- */
-#define BFIN_BUG_OPCODE 0x0001
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\",@progbits\n" \
- "2: .long 1b\n" \
- " .long %1\n" \
- " .short %2\n" \
- " .short %3\n" \
- " .org 2b + %4\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(__FILE__), \
- "i"(__LINE__), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#else
-
-#define _BUG_OR_WARN(flags) \
- asm volatile( \
- "1: .hword %0\n" \
- " .section __bug_table,\"aw\",@progbits\n" \
- "2: .long 1b\n" \
- " .short %1\n" \
- " .org 2b + %2\n" \
- " .previous" \
- : \
- : "i"(BFIN_BUG_OPCODE), "i"(flags), \
- "i"(sizeof(struct bug_entry)))
-
-#endif /* CONFIG_DEBUG_BUGVERBOSE */
-
-#define BUG() \
- do { \
- _BUG_OR_WARN(0); \
- unreachable(); \
- } while (0)
-
-#define WARN_ON(condition) \
- ({ \
- int __ret_warn_on = !!(condition); \
- if (unlikely(__ret_warn_on)) \
- _BUG_OR_WARN(BUGFLAG_WARNING); \
- unlikely(__ret_warn_on); \
- })
-
-#define HAVE_ARCH_BUG
-#define HAVE_ARCH_WARN_ON
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
deleted file mode 100644
index 568885a2c286..000000000000
--- a/arch/blackfin/include/asm/cache.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-#include <linux/linkage.h> /* for asmlinkage */
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-
-#ifdef CONFIG_SMP
-#define __cacheline_aligned
-#else
-#define ____cacheline_aligned
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned \
- __attribute__((__aligned__(L1_CACHE_BYTES), \
- __section__(".data_l1.cacheline_aligned")))
-#endif
-
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX 5
-
-#if defined(CONFIG_SMP) && \
- !defined(CONFIG_BFIN_CACHE_COHERENT)
-# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define __ARCH_SYNC_CORE_ICACHE
-# endif
-# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
-# define __ARCH_SYNC_CORE_DCACHE
-# endif
-#ifndef __ASSEMBLY__
-asmlinkage void __raw_smp_mark_barrier_asm(void);
-asmlinkage void __raw_smp_check_barrier_asm(void);
-
-static inline void smp_mark_barrier(void)
-{
- __raw_smp_mark_barrier_asm();
-}
-static inline void smp_check_barrier(void)
-{
- __raw_smp_check_barrier_asm();
-}
-
-void resync_core_dcache(void);
-void resync_core_icache(void);
-#endif
-#endif
-
-
-#endif
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
deleted file mode 100644
index 9a5b2c572ebf..000000000000
--- a/arch/blackfin/include/asm/cacheflush.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Blackfin low-level cache routines
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_CACHEFLUSH_H
-#define _BLACKFIN_CACHEFLUSH_H
-
-#include <asm/blackfin.h> /* for SSYNC() */
-#include <asm/sections.h> /* for _ramend */
-#ifdef CONFIG_SMP
-#include <asm/smp.h>
-#endif
-
-extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
-extern void blackfin_dflush_page(void *page);
-extern void blackfin_invalidate_entire_dcache(void);
-extern void blackfin_invalidate_entire_icache(void);
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#ifdef CONFIG_SMP
-#define flush_icache_range_others(start, end) \
- smp_icache_flush_range_others((start), (end))
-#else
-#define flush_icache_range_others(start, end) do { } while (0)
-#endif
-
-static inline void flush_icache_range(unsigned start, unsigned end)
-{
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- if (end <= physical_mem_end)
- blackfin_dcache_flush_range(start, end);
-#endif
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- if (start >= L2_START && end <= L2_START + L2_LENGTH)
- blackfin_dcache_flush_range(start, end);
-#endif
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory at the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- if (end <= physical_mem_end) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- if (start >= L2_START && end <= L2_START + L2_LENGTH) {
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
- }
-#endif
-}
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
- flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
-} while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
-
-#if defined(CONFIG_BFIN_DCACHE)
-# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
-#else
-# define invalidate_dcache_range(start,end) do { } while (0)
-#endif
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
-#else
-# define flush_dcache_range(start,end) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-# define flush_dcache_page(page) do { } while (0)
-#endif
-
-extern unsigned long reserved_mem_dcache_on;
-extern unsigned long reserved_mem_icache_on;
-
-static inline int bfin_addr_dcacheable(unsigned long addr)
-{
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (addr < (_ramend - DMA_UNCACHED_REGION))
- return 1;
-#endif
-
- if (reserved_mem_dcache_on &&
- addr >= _ramend && addr < physical_mem_end)
- return 1;
-
-#ifdef CONFIG_BFIN_L2_DCACHEABLE
- if (addr >= L2_START && addr < L2_START + L2_LENGTH)
- return 1;
-#endif
-
- return 0;
-}
-
-#endif /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h
deleted file mode 100644
index 59af63c0c2be..000000000000
--- a/arch/blackfin/include/asm/cdef_LPBlackfin.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-/*#if !defined(__ADSPLPBLACKFIN__)
-#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-*/
-#include <asm/def_LPBlackfin.h>
-
-/*Cache & SRAM Memory*/
-#define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)
-#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
-#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
-#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val)
-#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR,val)
-/*
-#define MMR_TIMEOUT 0xFFE00010
-*/
-#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0,val)
-#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1,val)
-#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2,val)
-#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3,val)
-#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4,val)
-#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5,val)
-#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6,val)
-#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7,val)
-#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8,val)
-#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9,val)
-#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10,val)
-#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11,val)
-#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12,val)
-#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13,val)
-#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14,val)
-#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15,val)
-#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0,val)
-#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1,val)
-#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2,val)
-#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3,val)
-#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4,val)
-#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5,val)
-#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6,val)
-#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7,val)
-#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8,val)
-#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9,val)
-#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10,val)
-#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11,val)
-#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12,val)
-#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13,val)
-#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14,val)
-#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15,val)
-#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND,val)
-/*
-#define DTEST_INDEX 0xFFE00304
-*/
-#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0,val)
-#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1,val)
-/*
-#define DTEST_DATA2 0xFFE00408
-#define DTEST_DATA3 0xFFE0040C
-*/
-#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
-#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val)
-#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR,val)
-#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0,val)
-#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1,val)
-#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2,val)
-#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3,val)
-#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4,val)
-#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5,val)
-#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6,val)
-#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7,val)
-#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8,val)
-#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9,val)
-#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10,val)
-#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11,val)
-#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12,val)
-#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13,val)
-#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14,val)
-#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15,val)
-#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0,val)
-#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1,val)
-#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2,val)
-#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3,val)
-#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4,val)
-#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5,val)
-#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6,val)
-#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7,val)
-#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8,val)
-#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9,val)
-#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10,val)
-#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11,val)
-#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12,val)
-#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13,val)
-#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val)
-#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val)
-#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val)
-#if 0
-#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
-#endif
-#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val)
-#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val)
-
-#if !ANOMALY_05000481
-#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
-#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
-#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
-#endif
-
-/* Event/Interrupt Registers*/
-
-#define bfin_read_EVT0() bfin_read32(EVT0)
-#define bfin_write_EVT0(val) bfin_write32(EVT0,val)
-#define bfin_read_EVT1() bfin_read32(EVT1)
-#define bfin_write_EVT1(val) bfin_write32(EVT1,val)
-#define bfin_read_EVT2() bfin_read32(EVT2)
-#define bfin_write_EVT2(val) bfin_write32(EVT2,val)
-#define bfin_read_EVT3() bfin_read32(EVT3)
-#define bfin_write_EVT3(val) bfin_write32(EVT3,val)
-#define bfin_read_EVT4() bfin_read32(EVT4)
-#define bfin_write_EVT4(val) bfin_write32(EVT4,val)
-#define bfin_read_EVT5() bfin_read32(EVT5)
-#define bfin_write_EVT5(val) bfin_write32(EVT5,val)
-#define bfin_read_EVT6() bfin_read32(EVT6)
-#define bfin_write_EVT6(val) bfin_write32(EVT6,val)
-#define bfin_read_EVT7() bfin_read32(EVT7)
-#define bfin_write_EVT7(val) bfin_write32(EVT7,val)
-#define bfin_read_EVT8() bfin_read32(EVT8)
-#define bfin_write_EVT8(val) bfin_write32(EVT8,val)
-#define bfin_read_EVT9() bfin_read32(EVT9)
-#define bfin_write_EVT9(val) bfin_write32(EVT9,val)
-#define bfin_read_EVT10() bfin_read32(EVT10)
-#define bfin_write_EVT10(val) bfin_write32(EVT10,val)
-#define bfin_read_EVT11() bfin_read32(EVT11)
-#define bfin_write_EVT11(val) bfin_write32(EVT11,val)
-#define bfin_read_EVT12() bfin_read32(EVT12)
-#define bfin_write_EVT12(val) bfin_write32(EVT12,val)
-#define bfin_read_EVT13() bfin_read32(EVT13)
-#define bfin_write_EVT13(val) bfin_write32(EVT13,val)
-#define bfin_read_EVT14() bfin_read32(EVT14)
-#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
-#define bfin_read_EVT15() bfin_read32(EVT15)
-#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
-#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
-#define bfin_read_IMASK() bfin_read32(IMASK)
-#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
-#define bfin_read_IPEND() bfin_read32(IPEND)
-#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
-#define bfin_read_ILAT() bfin_read32(ILAT)
-#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
-#define bfin_read_IPRIO() bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
-
-/*Core Timer Registers*/
-#define bfin_read_TCNTL() bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val) bfin_write32(TCNTL,val)
-#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD,val)
-#define bfin_read_TSCALE() bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val) bfin_write32(TSCALE,val)
-#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT,val)
-
-/*Debug/MP/Emulation Registers*/
-#define bfin_read_DSPID() bfin_read32(DSPID)
-#define bfin_write_DSPID(val) bfin_write32(DSPID,val)
-#define bfin_read_DBGCTL() bfin_read32(DBGCTL)
-#define bfin_write_DBGCTL(val) bfin_write32(DBGCTL,val)
-#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT,val)
-#define bfin_read_EMUDAT() bfin_read32(EMUDAT)
-#define bfin_write_EMUDAT(val) bfin_write32(EMUDAT,val)
-
-/*Trace Buffer Registers*/
-#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL,val)
-#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT,val)
-#define bfin_read_TBUF() bfin_read32(TBUF)
-#define bfin_write_TBUF(val) bfin_write32(TBUF,val)
-
-/*Watch Point Control Registers*/
-#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL,val)
-#define bfin_read_WPIA0() bfin_read32(WPIA0)
-#define bfin_write_WPIA0(val) bfin_write32(WPIA0,val)
-#define bfin_read_WPIA1() bfin_read32(WPIA1)
-#define bfin_write_WPIA1(val) bfin_write32(WPIA1,val)
-#define bfin_read_WPIA2() bfin_read32(WPIA2)
-#define bfin_write_WPIA2(val) bfin_write32(WPIA2,val)
-#define bfin_read_WPIA3() bfin_read32(WPIA3)
-#define bfin_write_WPIA3(val) bfin_write32(WPIA3,val)
-#define bfin_read_WPIA4() bfin_read32(WPIA4)
-#define bfin_write_WPIA4(val) bfin_write32(WPIA4,val)
-#define bfin_read_WPIA5() bfin_read32(WPIA5)
-#define bfin_write_WPIA5(val) bfin_write32(WPIA5,val)
-#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0,val)
-#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1,val)
-#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2,val)
-#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3,val)
-#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4,val)
-#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5,val)
-#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL,val)
-#define bfin_read_WPDA0() bfin_read32(WPDA0)
-#define bfin_write_WPDA0(val) bfin_write32(WPDA0,val)
-#define bfin_read_WPDA1() bfin_read32(WPDA1)
-#define bfin_write_WPDA1(val) bfin_write32(WPDA1,val)
-#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0,val)
-#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1,val)
-#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT,val)
-
-/*Performance Monitor Registers*/
-#define bfin_read_PFCTL() bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val) bfin_write32(PFCTL,val)
-#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0,val)
-#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
-
-#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/checksum.h b/arch/blackfin/include/asm/checksum.h
deleted file mode 100644
index e7134bf94e3c..000000000000
--- a/arch/blackfin/include/asm/checksum.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * akbar.hussain@lineo.com
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CHECKSUM_H
-#define _BFIN_CHECKSUM_H
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- unsigned int carry;
-
- __asm__ ("%0 = %0 + %2;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %3;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- "%0 = %0 + %4;\n\t"
- "CC = AC0;\n\t"
- "%1 = CC;\n\t"
- "%0 = %0 + %1;\n\t"
- : "=d" (sum), "=&d" (carry)
- : "d" (daddr), "d" (saddr), "d" ((len + proto) << 8), "0"(sum)
- : "CC");
-
- return (sum);
-}
-#define csum_tcpudp_nofold __csum_tcpudp_nofold
-
-#include <asm-generic/checksum.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
deleted file mode 100644
index 9b3c85b3c288..000000000000
--- a/arch/blackfin/include/asm/clocks.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Common Clock definitions for various kernel files
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_CLOCKS_H
-#define _BFIN_CLOCKS_H
-
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_CCLK_DIV_1
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-# define CONFIG_CCLK_DIV 1
-#endif
-
-#ifdef CONFIG_CCLK_DIV_2
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-# define CONFIG_CCLK_DIV 2
-#endif
-
-#ifdef CONFIG_CCLK_DIV_4
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-# define CONFIG_CCLK_DIV 4
-#endif
-
-#ifdef CONFIG_CCLK_DIV_8
-# define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-# define CONFIG_CCLK_DIV 8
-#endif
-
-#ifndef CONFIG_PLL_BYPASS
-# ifndef CONFIG_CLKIN_HALF
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-# define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-# endif
-
-# define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-# define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-
-#else
-# define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_CCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_SCLK_HZ (CONFIG_CLKIN_HZ)
-# define CONFIG_VCO_MULT 0
-#endif
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- struct clk *parent;
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-int clk_init(void);
-#endif
diff --git a/arch/blackfin/include/asm/cmpxchg.h b/arch/blackfin/include/asm/cmpxchg.h
deleted file mode 100644
index 253928854299..000000000000
--- a/arch/blackfin/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CMPXCHG__
-#define __ARCH_BLACKFIN_CMPXCHG__
-
-#ifdef CONFIG_SMP
-
-#include <linux/linkage.h>
-
-asmlinkage unsigned long __raw_xchg_1_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_2_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_xchg_4_asm(volatile void *ptr, unsigned long value);
-asmlinkage unsigned long __raw_cmpxchg_1_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_2_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-asmlinkage unsigned long __raw_cmpxchg_4_asm(volatile void *ptr,
- unsigned long new, unsigned long old);
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_xchg_1_asm(ptr, x);
- break;
- case 2:
- tmp = __raw_xchg_2_asm(ptr, x);
- break;
- case 4:
- tmp = __raw_xchg_4_asm(ptr, x);
- break;
- }
-
- return tmp;
-}
-
-/*
- * Atomic compare and exchange. Compare OLD with MEM, if identical,
- * store NEW in MEM. Return the initial value in MEM. Success is
- * indicated by comparing RETURN with OLD.
- */
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
- unsigned long new, int size)
-{
- unsigned long tmp;
-
- switch (size) {
- case 1:
- tmp = __raw_cmpxchg_1_asm(ptr, new, old);
- break;
- case 2:
- tmp = __raw_cmpxchg_2_asm(ptr, new, old);
- break;
- case 4:
- tmp = __raw_cmpxchg_4_asm(ptr, new, old);
- break;
- }
-
- return tmp;
-}
-#define cmpxchg(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-
-#else /* !CONFIG_SMP */
-
-#include <mach/blackfin.h>
-#include <asm/irqflags.h>
-
-struct __xchg_dummy {
- unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
- int size)
-{
- unsigned long tmp = 0;
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- switch (size) {
- case 1:
- __asm__ __volatile__
- ("%0 = b%2 (z);\n\t"
- "b%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 2:
- __asm__ __volatile__
- ("%0 = w%2 (z);\n\t"
- "w%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- case 4:
- __asm__ __volatile__
- ("%0 = %2;\n\t"
- "%2 = %1;\n\t"
- : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
- break;
- }
- hard_local_irq_restore(flags);
- return tmp;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#define cmpxchg(ptr, o, n) cmpxchg_local((ptr), (o), (n))
-#define cmpxchg64(ptr, o, n) cmpxchg64_local((ptr), (o), (n))
-
-#endif /* !CONFIG_SMP */
-
-#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
-
-#endif /* __ARCH_BLACKFIN_CMPXCHG__ */
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
deleted file mode 100644
index 507e7aa6a561..000000000000
--- a/arch/blackfin/include/asm/context.S
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
-
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r0 = 0x3f;
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
-#endif
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_syscall
- [--sp] = SYSCFG;
-
- [--sp] = P0; /*orig_p0*/
- [--sp] = R0; /*orig_r0*/
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r0; /* Skip IPEND as well. */
- [--sp] = RETI; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro save_context_no_interrupts
- [--sp] = SYSCFG;
- [--sp] = P0; /* orig_p0 */
- [--sp] = R0; /* orig_r0 */
- [--sp] = ( R7:0, P5:0 );
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
-#ifdef CONFIG_KGDB
- fp = 0(Z);
- r1 = sp;
- r1 += 60;
- r1 += 60;
- r1 += 60;
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip reserved */
-#endif
- [--sp] = RETS;
- r0 = RETI;
- [--sp] = r0;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
-#ifdef CONFIG_DEBUG_KERNEL
- p1.l = lo(IPEND);
- p1.h = hi(IPEND);
- r1 = [p1];
- [--sp] = r1;
-#else
- [--sp] = r0; /* Skip IPEND as well. */
-#endif
- [--sp] = r0; /*orig_pc*/
- /* Clear all L registers. */
- r0 = 0 (x);
- l0 = r0;
- l1 = r0;
- l2 = r0;
- l3 = r0;
-.endm
-
-.macro restore_context_no_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- r0 = [sp++];
- RETI = r0; /* Restore RETI indirectly when in exception */
- RETS = [sp++];
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- SYSCFG = [sp++];
-.endm
-
-.macro restore_context_with_interrupts
- sp += 4; /* Skip orig_pc */
- sp += 4; /* Skip IPEND */
- SEQSTAT = [sp++];
- RETE = [sp++];
- RETN = [sp++];
- RETX = [sp++];
- RETI = [sp++];
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-
- RETS = [sp++];
-
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.h = _bfin_irq_flags;
- p0.l = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- sp += 4; /* Skip Reserved */
-
- ASTAT = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- sp += 4;
- fp = [sp++];
-
- ( R7 : 0, P5 : 0) = [ SP ++ ];
- sp += 8; /* Skip orig_r0/orig_p0 */
- csync;
- SYSCFG = [sp++];
- csync;
-.endm
-
-.macro save_context_cplb
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
-
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = RETS;
-.endm
-
-.macro restore_context_cplb
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
-
- fp = [sp++];
-
- (R7:0, P5:0) = [SP++];
-.endm
-
-.macro pseudo_long_call func:req, scratch:req
-#ifdef CONFIG_ROMKERNEL
- \scratch\().l = \func;
- \scratch\().h = \func;
- call (\scratch);
-#else
- call \func;
-#endif
-.endm
-
-#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
-# define EX_SCRATCH_REG RETN
-#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
-# define EX_SCRATCH_REG RETE
-#else
-# define EX_SCRATCH_REG CYCLES
-#endif
-
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
deleted file mode 100644
index 5c37f620c4b3..000000000000
--- a/arch/blackfin/include/asm/cplb.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#include <mach/anomaly.h>
-
-#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
-
-#if ANOMALY_05000158
-#define ANOMALY_05000158_WORKAROUND 0x200
-#else
-#define ANOMALY_05000158_WORKAROUND 0x0
-#endif
-
-#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
-#else
-#define SDRAM_DGENERIC (CPLB_COMMON)
-#endif
-
-#define SDRAM_DNON_CHBL (CPLB_COMMON)
-#define SDRAM_EBIU (CPLB_COMMON)
-#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-
-#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
-
-#ifdef CONFIG_SMP
-#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
-#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
-
-#else
-#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
-# if defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# else
-# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
-# endif
-
-# if defined(CONFIG_BFIN_L2_WRITEBACK)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
-# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
-# else
-# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
-# endif
-#endif /* CONFIG_SMP */
-
-#define SIZE_1K 0x00000400 /* 1K */
-#define SIZE_4K 0x00001000 /* 4K */
-#define SIZE_1M 0x00100000 /* 1M */
-#define SIZE_4M 0x00400000 /* 4M */
-#define SIZE_16K 0x00004000 /* 16K */
-#define SIZE_64K 0x00010000 /* 64K */
-#define SIZE_16M 0x01000000 /* 16M */
-#define SIZE_64M 0x04000000 /* 64M */
-
-#define MAX_CPLBS 16
-
-#define CPLB_ENABLE_ICACHE_P 0
-#define CPLB_ENABLE_DCACHE_P 1
-#define CPLB_ENABLE_DCACHE2_P 2
-#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P 4
-#define CPLB_ENABLE_DCPLBS_P 5
-
-#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
- CPLB_ENABLE_ICPLBS | \
- CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED 0x0000
-#define CPLB_NO_UNLOCKED 0x0001
-#define CPLB_NO_ADDR_MATCH 0x0002
-#define CPLB_PROT_VIOL 0x0003
-#define CPLB_UNKNOWN_ERR 0x0004
-
-#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
-
-#define FAULT_RW (1 << 16)
-#define FAULT_USERSUPV (1 << 17)
-#define FAULT_CPLBBITS 0x0000ffff
-
-#ifndef __ASSEMBLY__
-
-static inline void _disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void disable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) & ~mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
-#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
-
-static inline void _enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- /* CSYNC to ensure load store ordering */
- __builtin_bfin_csync();
- bfin_write32(mmr, ctrl);
- __builtin_bfin_ssync();
-}
-static inline void enable_cplb(u32 mmr, u32 mask)
-{
- u32 ctrl = bfin_read32(mmr) | mask;
- CSYNC();
- bfin_write32(mmr, ctrl);
- SSYNC();
-}
-#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
-#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
-#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _CPLB_H */
diff --git a/arch/blackfin/include/asm/cplbinit.h b/arch/blackfin/include/asm/cplbinit.h
deleted file mode 100644
index f315c83a015d..000000000000
--- a/arch/blackfin/include/asm/cplbinit.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Common CPLB definitions for CPLB init
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_CPLBINIT_H__
-#define __ASM_CPLBINIT_H__
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <linux/threads.h>
-
-#ifdef CONFIG_CPLB_SWITCH_TAB_L1
-# define PDT_ATTR __attribute__((l1_data))
-#else
-# define PDT_ATTR
-#endif
-
-struct cplb_entry {
- unsigned long data, addr;
-};
-
-struct cplb_boundary {
- unsigned long eaddr; /* End of this region. */
- unsigned long data; /* CPLB data value. */
-};
-
-extern struct cplb_boundary dcplb_bounds[];
-extern struct cplb_boundary icplb_bounds[];
-extern int dcplb_nr_bounds, icplb_nr_bounds;
-
-extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-extern int first_switched_icplb;
-extern int first_switched_dcplb;
-
-extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
-extern int nr_dcplb_prot[], nr_cplb_flush[];
-
-#ifdef CONFIG_MPU
-
-extern int first_mask_dcplb;
-
-extern int page_mask_order;
-extern int page_mask_nelts;
-
-extern unsigned long *current_rwx_mask[NR_CPUS];
-
-extern void flush_switched_cplbs(unsigned int);
-extern void set_mask_dcplbs(unsigned long *, unsigned int);
-
-extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
-
-#endif /* CONFIG_MPU */
-
-extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
-extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-extern void generate_cplb_tables_all(void);
-extern void generate_cplb_tables_cpu(unsigned int cpu);
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
deleted file mode 100644
index e349631c8299..000000000000
--- a/arch/blackfin/include/asm/cpu.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CPU_H
-#define __ASM_BLACKFIN_CPU_H
-
-#include <linux/percpu.h>
-
-struct blackfin_cpudata {
- struct cpu cpu;
- unsigned int imemctl;
- unsigned int dmemctl;
-#ifdef CONFIG_SMP
- struct task_struct *idle;
-#endif
-};
-
-DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-#endif
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
deleted file mode 100644
index c5c8d8a3a5fa..000000000000
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/*
- * Blackfin core register bit & address definitions
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or GPL-2 (or later).
- */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-#include <mach/anomaly.h>
-
-#define MK_BMSK_(x) (1<<x)
-#define BFIN_DEPOSIT(mask, x) (((x) << __ffs(mask)) & (mask))
-#define BFIN_EXTRACT(mask, x) (((x) & (mask)) >> __ffs(mask))
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
- u32 __v; \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- "%0 = " #asm_size "[%1]" #asm_ext ";" \
- : "=d" (__v) \
- : "a" (addr) \
- ); \
- __v; })
-#define _bfin_writeX(addr, val, size, asm_size) \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000198 \
- #asm_size "[%0] = %1;" \
- : \
- : "a" (addr), "d" ((u##size)(val)) \
- : "memory" \
- )
-
-#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z))
-#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
-#define bfin_read32(addr) _bfin_readX(addr, 32, , )
-#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b)
-#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
-#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
-
-#define bfin_read(addr) \
-({ \
- sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
- sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
- sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
- ({ BUG(); 0; }); \
-})
-#define bfin_write(addr, val) \
-do { \
- switch (sizeof(*(addr))) { \
- case 1: bfin_write8(addr, val); break; \
- case 2: bfin_write16(addr, val); break; \
- case 4: bfin_write32(addr, val); break; \
- default: BUG(); \
- } \
-} while (0)
-
-#define bfin_write_or(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) | (bits)); \
-} while (0)
-
-#define bfin_write_and(addr, bits) \
-do { \
- typeof(addr) __addr = (addr); \
- bfin_write(__addr, bfin_read(__addr) & (bits)); \
-} while (0)
-
-#endif /* __ASSEMBLY__ */
-
-/**************************************************
- * System Register Bits
- **************************************************/
-
-/**************************************************
- * ASTAT register
- **************************************************/
-
-/* definitions of ASTAT bit positions*/
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ_P 0x00000000
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN_P 0x00000001
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC_P 0x00000005
-/*Quotient Bit*/
-#define ASTAT_AQ_P 0x00000006
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD_P 0x00000008
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_P 0x0000000C
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY_P 0x00000002
-/*Result of last ALU1 operation generated a carry*/
-#define ASTAT_AC1_P 0x0000000D
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0_P 0x00000010
-/*Sticky version of ASTAT_AV0 */
-#define ASTAT_AV0S_P 0x00000011
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1_P 0x00000012
-/*Sticky version of ASTAT_AV1 */
-#define ASTAT_AV1S_P 0x00000013
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_P 0x00000018
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_COPY_P 0x00000003
-/*Sticky version of ASTAT_V*/
-#define ASTAT_VS_P 0x00000019
-
-/* Masks */
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
-/*Quotient Bit*/
-#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
-/*Overflow Bit*/
-#define ASTAT_V MK_BMSK_(ASTAT_V_P)
-/*Overflow Bit*/
-#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
-
-/**************************************************
- * SEQSTAT register
- **************************************************/
-
-/* Bit Positions */
-#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
- * set by IDLE instruction.
- */
-#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
- * reset was a software reset
- * (=1)
- */
-#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
-/* Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
- MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
- 0)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
- MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
- 0)
-
-/* Translate bits to something useful */
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE_SHIFT (14)
-#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
-
-/**************************************************
- * SYSCFG register
- **************************************************/
-
-/* Bit Positions */
-#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
- * set it forces an exception
- * for each instruction executed
- */
-#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
-
-/* Masks */
-
-/* Supervisor single step, when set it forces an exception for each
- *instruction executed
- */
-#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
-/* Enable cycle counter (=1) */
-#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
-/* Self Nesting Interrupt Enable */
-#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
-#define SYSCFG_CCCEN SYSCFG_CCEN
-
-/****************************************************
- * Core MMR Register Map
- ****************************************************/
-
-/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
-
-#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
-#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
- * Buffer Status
- */
-#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
-#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
- * Buffer Fault Address
- */
-#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
- * Buffer 0
- */
-#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
- * Buffer 1
- */
-#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
- * Buffer 2
- */
-#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
- * Lookaside Buffer 3
- */
-#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
- * Lookaside Buffer 4
- */
-#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
- * Lookaside Buffer 5
- */
-#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
- * Lookaside Buffer 6
- */
-#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
- * Lookaside Buffer 7
- */
-#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
- * Lookaside Buffer 8
- */
-#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
- * Lookaside Buffer 9
- */
-#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
- * Lookaside Buffer 10
- */
-#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
- * Lookaside Buffer 11
- */
-#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
- * Lookaside Buffer 12
- */
-#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
- * Lookaside Buffer 13
- */
-#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
- * Lookaside Buffer 14
- */
-#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
- * Lookaside Buffer 15
- */
-#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
-#define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
-
-#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
-
-#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
-#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
-#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
-#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
-#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
- * Protection Lookaside Buffer 0
- */
-#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
- * Protection Lookaside Buffer 1
- */
-#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
- * Protection Lookaside Buffer 2
- */
-#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
- * Protection Lookaside Buffer 3
- */
-#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
- * Protection Lookaside Buffer 4
- */
-#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
- * Protection Lookaside Buffer 5
- */
-#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
- * Protection Lookaside Buffer 6
- */
-#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
- * Protection Lookaside Buffer 7
- */
-#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
- * Protection Lookaside Buffer 8
- */
-#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
- * Protection Lookaside Buffer 9
- */
-#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
- * Protection Lookaside Buffer 10
- */
-#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
- * Protection Lookaside Buffer 11
- */
-#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
- * Protection Lookaside Buffer 12
- */
-#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
- * Protection Lookaside Buffer 13
- */
-#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
- * Protection Lookaside Buffer 14
- */
-#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
- * Protection Lookaside Buffer 15
- */
-#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
-
-#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
-#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
-#define IMASK 0xFFE02104 /* Interrupt Mask Register */
-#define IPEND 0xFFE02108 /* Interrupt Pending Register */
-#define ILAT 0xFFE0210C /* Interrupt Latch Register */
-#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
-
-/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
-
-#define TCNTL 0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
-#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
-#define DSPID 0xFFE05000 /* DSP Processor ID Register for
- * MP implementations
- */
-
-#define DBGSTAT 0xFFE05008 /* Debug Status Register */
-
-/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
-
-#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF 0xFFE06100 /* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-
-/* Watchpoint Instruction Address Control Register */
-#define WPIACTL 0xFFE07000
-/* Watchpoint Instruction Address Register 0 */
-#define WPIA0 0xFFE07040
-/* Watchpoint Instruction Address Register 1 */
-#define WPIA1 0xFFE07044
-/* Watchpoint Instruction Address Register 2 */
-#define WPIA2 0xFFE07048
-/* Watchpoint Instruction Address Register 3 */
-#define WPIA3 0xFFE0704C
-/* Watchpoint Instruction Address Register 4 */
-#define WPIA4 0xFFE07050
-/* Watchpoint Instruction Address Register 5 */
-#define WPIA5 0xFFE07054
-/* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT0 0xFFE07080
-/* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT1 0xFFE07084
-/* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT2 0xFFE07088
-/* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT3 0xFFE0708C
-/* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT4 0xFFE07090
-/* Watchpoint Instruction Address Count Register 5 */
-#define WPIACNT5 0xFFE07094
-/* Watchpoint Data Address Control Register */
-#define WPDACTL 0xFFE07100
-/* Watchpoint Data Address Register 0 */
-#define WPDA0 0xFFE07140
-/* Watchpoint Data Address Register 1 */
-#define WPDA1 0xFFE07144
-/* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT0 0xFFE07180
-/* Watchpoint Data Address Count Value Register 1 */
-#define WPDACNT1 0xFFE07184
-/* Watchpoint Status Register */
-#define WPSTAT 0xFFE07200
-
-/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
-
-/* Performance Monitor Control Register */
-#define PFCTL 0xFFE08000
-/* Performance Monitor Counter Register 0 */
-#define PFCNTR0 0xFFE08100
-/* Performance Monitor Counter Register 1 */
-#define PFCNTR1 0xFFE08104
-
-/****************************************************
- * Core MMR Register Bits
- ****************************************************/
-
-/**************************************************
- * EVT registers (ILAT, IMASK, and IPEND).
- **************************************************/
-
-/* Bit Positions */
-#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
-#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
-#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
-#define EVT_EVX_P 0x00000003 /* Exception bit position */
-#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
-#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
-#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
-#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
-#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
-#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
-#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
-#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
-#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
-#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
-#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
-
-/* Masks */
-#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
-#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
-#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
-#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
-#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
-#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
-#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
-#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
-#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
-#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
-#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
-#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
-#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
-#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
-#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
-#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
-
-/**************************************************
- * DMEM_CONTROL Register
- **************************************************/
-/* Bit Positions */
-#define ENDM_P 0x00 /* (doesn't really exist) Enable
- *Data Memory L1
- */
-#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
-
-#define ENDCPLB_P 0x01 /* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
-#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
-#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
-#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
-#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
-#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
-#define RDCHK 0x9 /* Enable L1 Parity Check */
-
-/* Masks */
-#define ENDM 0x00000001 /* (doesn't really exist) Enable
- * Data Memory L1
- */
-#define ENDCPLB 0x00000002 /* Enable DCPLB */
-#define ASRAM_BSRAM 0x00000000
-#define ACACHE_BSRAM 0x00000008
-#define ACACHE_BCACHE 0x0000000C
-#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
-#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
-#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* Bit Positions */
-#define ENIM_P 0x00 /* Enable L1 Code Memory */
-#define IMCTL_ENIM_P 0x00 /* "" (older define) */
-#define ENICPLB_P 0x01 /* Enable ICPLB */
-#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
-#define IMC_P 0x02 /* Enable */
-#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0_P 0x03 /* Lock Way 0 */
-#define ILOC1_P 0x04 /* Lock Way 1 */
-#define ILOC2_P 0x05 /* Lock Way 2 */
-#define ILOC3_P 0x06 /* Lock Way 3 */
-#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
- * Priority
- */
-/* Masks */
-#define ENIM 0x00000001 /* Enable L1 Code Memory */
-#define ENICPLB 0x00000002 /* Enable ICPLB */
-#define IMC 0x00000004 /* Configure L1 code memory as
- * cache (0=SRAM)
- */
-#define ILOC0 0x00000008 /* Lock Way 0 */
-#define ILOC1 0x00000010 /* Lock Way 1 */
-#define ILOC2 0x00000020 /* Lock Way 2 */
-#define ILOC3 0x00000040 /* Lock Way 3 */
-#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
- * Priority
- */
-
-/* TCNTL Masks */
-#define TMPWR 0x00000001 /* Timer Low Power Control,
- * 0=low power mode, 1=active state
- */
-#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD 0x00000004 /* Timer auto reload */
-#define TINT 0x00000008 /* Timer generated interrupt 0=no
- * interrupt has been generated,
- * 1=interrupt has been generated
- * (sticky)
- */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* Bit Positions */
-#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-/* Masks */
-#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
- * locked
- */
-#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
- * allowed (user mode)
- */
-
-#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
-#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
-#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
-#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
-#ifdef CONFIG_BF60x
-#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
-#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
-#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
-#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
-#endif
-#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
- * mapped to L1
- */
-#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
- * priority port
- */
-#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
- * in L1
- */
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
- * 1=priority for non-replacement
- */
-/* DCPLB_DATA only */
-#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
- * access allowed (user mode)
- */
-#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
- * access allowed (supervisor mode)
- */
-#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
- * write-through writes,
- * 1= allocate cache lines on
- * write-through writes.
- */
-#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
-
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-/* TBUFCTL Masks */
-#define TBUFPWR 0x0001
-#define TBUFEN 0x0002
-#define TBUFOVF 0x0004
-#define TBUFCMPLP_SINGLE 0x0008
-#define TBUFCMPLP_DOUBLE 0x0010
-#define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
-
-/* TBUFSTAT Masks */
-#define TBUFCNT 0x001F
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* Masks */
-#define TEST_READ 0x00000000 /* Read Access */
-#define TEST_WRITE 0x00000002 /* Write Access */
-#define TEST_TAG 0x00000000 /* Access TAG */
-#define TEST_DATA 0x00000004 /* Access DATA */
-#define TEST_DW0 0x00000000 /* Select Double Word 0 */
-#define TEST_DW1 0x00000008 /* Select Double Word 1 */
-#define TEST_DW2 0x00000010 /* Select Double Word 2 */
-#define TEST_DW3 0x00000018 /* Select Double Word 3 */
-#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
-#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
-#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
-#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
-#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
-#define TEST_WAY0 0x00000000 /* Access Way0 */
-#define TEST_WAY1 0x04000000 /* Access Way1 */
-/* ITEST_COMMAND only */
-#define TEST_WAY2 0x08000000 /* Access Way2 */
-#define TEST_WAY3 0x0C000000 /* Access Way3 */
-/* DTEST_COMMAND only */
-#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
-#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
-
-#endif /* _DEF_LPBLACKFIN_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
deleted file mode 100644
index 171d8deb04a5..000000000000
--- a/arch/blackfin/include/asm/delay.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * delay.h - delay functions
- *
- * Copyright (c) 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_DELAY_H__
-#define __ASM_DELAY_H__
-
-#include <mach/anomaly.h>
-
-static inline void __delay(unsigned long loops)
-{
-__asm__ __volatile__ (
- "LSETUP(1f, 1f) LC0 = %0;"
- "1: NOP;"
- :
- : "a" (loops)
- : "LT0", "LB0", "LC0"
- );
-}
-
-#include <linux/param.h> /* needed for HZ */
-
-/*
- * close approximation borrowed from m68knommu to avoid 64-bit math
- */
-
-#define HZSCALE (268435456 / (1000000/HZ))
-
-static inline unsigned long __to_delay(unsigned long scale)
-{
- extern unsigned long loops_per_jiffy;
- return (((scale * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6;
-}
-
-static inline void udelay(unsigned long usecs)
-{
- __delay(__to_delay(usecs));
-}
-
-static inline void ndelay(unsigned long nsecs)
-{
- __delay(__to_delay(1) * nsecs / 1000);
-}
-
-#define ndelay ndelay
-
-#endif
diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h
deleted file mode 100644
index 04254ac36bed..000000000000
--- a/arch/blackfin/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_MAPPING_H
-#define _BLACKFIN_DMA_MAPPING_H
-
-#include <asm/cacheflush.h>
-
-extern void
-__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir);
-static inline void
-__dma_sync_inline(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- switch (dir) {
- case DMA_NONE:
- BUG();
- case DMA_TO_DEVICE: /* writeback only */
- flush_dcache_range(addr, addr + size);
- break;
- case DMA_FROM_DEVICE: /* invalidate only */
- case DMA_BIDIRECTIONAL: /* flush and invalidate */
- /* Blackfin has no dedicated invalidate (it includes a flush) */
- invalidate_dcache_range(addr, addr + size);
- break;
- }
-}
-static inline void
-_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir)
-{
- if (__builtin_constant_p(dir))
- __dma_sync_inline(addr, size, dir);
- else
- __dma_sync(addr, size, dir);
-}
-
-extern const struct dma_map_ops bfin_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &bfin_dma_ops;
-}
-
-#endif /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
deleted file mode 100644
index 40e9c2bbc6e3..000000000000
--- a/arch/blackfin/include/asm/dma.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <linux/interrupt.h>
-#include <mach/dma.h>
-#include <linux/atomic.h>
-#include <asm/blackfin.h>
-#include <asm/page.h>
-#include <asm-generic/dma.h>
-#include <asm/bfin_dma.h>
-
-/*-------------------------
- * config reg bits value
- *-------------------------*/
-#define DATA_SIZE_8 0
-#define DATA_SIZE_16 1
-#define DATA_SIZE_32 2
-#ifdef CONFIG_BF60x
-#define DATA_SIZE_64 3
-#endif
-
-#define DMA_FLOW_STOP 0
-#define DMA_FLOW_AUTO 1
-#ifdef CONFIG_BF60x
-#define DMA_FLOW_LIST 4
-#define DMA_FLOW_ARRAY 5
-#define DMA_FLOW_LIST_DEMAND 6
-#define DMA_FLOW_ARRAY_DEMAND 7
-#else
-#define DMA_FLOW_ARRAY 4
-#define DMA_FLOW_SMALL 6
-#define DMA_FLOW_LARGE 7
-#endif
-
-#define DIMENSION_LINEAR 0
-#define DIMENSION_2D 1
-
-#define DIR_READ 0
-#define DIR_WRITE 1
-
-#define INTR_DISABLE 0
-#ifdef CONFIG_BF60x
-#define INTR_ON_PERI 1
-#endif
-#define INTR_ON_BUF 2
-#define INTR_ON_ROW 3
-
-#define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART 1
-
-#ifdef DMA_MMR_SIZE_32
-#define DMA_MMR_SIZE_TYPE long
-#define DMA_MMR_READ bfin_read32
-#define DMA_MMR_WRITE bfin_write32
-#else
-#define DMA_MMR_SIZE_TYPE short
-#define DMA_MMR_READ bfin_read16
-#define DMA_MMR_WRITE bfin_write16
-#endif
-
-struct dma_desc_array {
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
-} __attribute__((packed));
-
-struct dmasg {
- void *next_desc_addr;
- unsigned long start_addr;
- unsigned DMA_MMR_SIZE_TYPE cfg;
- unsigned DMA_MMR_SIZE_TYPE x_count;
- DMA_MMR_SIZE_TYPE x_modify;
- unsigned DMA_MMR_SIZE_TYPE y_count;
- DMA_MMR_SIZE_TYPE y_modify;
-} __attribute__((packed));
-
-struct dma_register {
- void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
- unsigned long start_addr; /* DMA Start address register */
-#ifdef CONFIG_BF60x
- unsigned long cfg; /* DMA Configuration register */
-
- unsigned long x_count; /* DMA x_count register */
-
- long x_modify; /* DMA x_modify register */
-
- unsigned long y_count; /* DMA y_count register */
-
- long y_modify; /* DMA y_modify register */
-
- unsigned long reserved;
- unsigned long reserved2;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned long irq_status; /* DMA irq status register */
-
- unsigned long curr_x_count; /* DMA Current x-count register */
-
- unsigned long curr_y_count; /* DMA Current y-count register */
-
- unsigned long reserved3;
-
- unsigned long bw_limit_count; /* DMA band width limit count register */
- unsigned long curr_bw_limit_count; /* DMA Current band width limit
- count register */
- unsigned long bw_monitor_count; /* DMA band width limit count register */
- unsigned long curr_bw_monitor_count; /* DMA Current band width limit
- count register */
-#else
- unsigned short cfg; /* DMA Configuration register */
- unsigned short dummy1; /* DMA Configuration register */
-
- unsigned long reserved;
-
- unsigned short x_count; /* DMA x_count register */
- unsigned short dummy2;
-
- short x_modify; /* DMA x_modify register */
- unsigned short dummy3;
-
- unsigned short y_count; /* DMA y_count register */
- unsigned short dummy4;
-
- short y_modify; /* DMA y_modify register */
- unsigned short dummy5;
-
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned short irq_status; /* DMA irq status register */
- unsigned short dummy6;
-
- unsigned short peripheral_map; /* DMA peripheral map register */
- unsigned short dummy7;
-
- unsigned short curr_x_count; /* DMA Current x-count register */
- unsigned short dummy8;
-
- unsigned long reserved2;
-
- unsigned short curr_y_count; /* DMA Current y-count register */
- unsigned short dummy9;
-
- unsigned long reserved3;
-#endif
-
-};
-
-struct dma_channel {
- const char *device_id;
- atomic_t chan_status;
- volatile struct dma_register *regs;
- struct dmasg *sg; /* large mode descriptor */
- unsigned int irq;
- void *data;
-#ifdef CONFIG_PM
- unsigned short saved_peripheral_map;
-#endif
-};
-
-#ifdef CONFIG_PM
-int blackfin_dma_suspend(void);
-void blackfin_dma_resume(void);
-#endif
-
-/*******************************************************************************
-* DMA API's
-*******************************************************************************/
-extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
-extern int channel2irq(unsigned int channel);
-
-static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->start_addr = addr;
-}
-static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->next_desc_ptr = addr;
-}
-static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
-{
- dma_ch[channel].regs->curr_desc_ptr = addr;
-}
-static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
-{
- dma_ch[channel].regs->x_count = x_count;
-}
-static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
-{
- dma_ch[channel].regs->y_count = y_count;
-}
-static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
-{
- dma_ch[channel].regs->x_modify = x_modify;
-}
-static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
-{
- dma_ch[channel].regs->y_modify = y_modify;
-}
-static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
-{
- dma_ch[channel].regs->cfg = config;
-}
-static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
-{
- dma_ch[channel].regs->curr_addr_ptr = addr;
-}
-
-#ifdef CONFIG_BF60x
-static inline unsigned long
-set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
- char dma_mode, char mem_width, char syncmode, char peri_width)
-{
- unsigned long config = 0;
-
- switch (intr_mode) {
- case INTR_ON_BUF:
- if (dma_mode == DIMENSION_2D)
- config = DI_EN_Y;
- else
- config = DI_EN_X;
- break;
- case INTR_ON_ROW:
- config = DI_EN_X;
- break;
- case INTR_ON_PERI:
- config = DI_EN_P;
- break;
- };
-
- return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
- (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
-}
-#endif
-
-static inline unsigned DMA_MMR_SIZE_TYPE
-set_bfin_dma_config(char direction, char flow_mode,
- char intr_mode, char dma_mode, char mem_width, char syncmode)
-{
-#ifdef CONFIG_BF60x
- return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
- mem_width, syncmode, mem_width);
-#else
- return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
- (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
-#endif
-}
-
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
-{
- return dma_ch[channel].regs->irq_status;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_x_count;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_y_count;
-}
-static inline void *get_dma_next_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->next_desc_ptr;
-}
-static inline void *get_dma_curr_desc_ptr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_desc_ptr;
-}
-static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
-{
- return dma_ch[channel].regs->cfg;
-}
-static inline unsigned long get_dma_curr_addr(unsigned int channel)
-{
- return dma_ch[channel].regs->curr_addr_ptr;
-}
-
-static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
-{
- /* Make sure the internal data buffers in the core are drained
- * so that the DMA descriptors are completely written when the
- * DMA engine goes to fetch them below.
- */
- SSYNC();
-
- dma_ch[channel].regs->next_desc_ptr = sg;
- dma_ch[channel].regs->cfg =
- (dma_ch[channel].regs->cfg & ~NDSIZE) |
- ((ndsize << NDSIZE_OFFSET) & NDSIZE);
-}
-
-static inline int dma_channel_active(unsigned int channel)
-{
- return atomic_read(&dma_ch[channel].chan_status);
-}
-
-static inline void disable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->cfg &= ~DMAEN;
- SSYNC();
-}
-static inline void enable_dma(unsigned int channel)
-{
- dma_ch[channel].regs->curr_x_count = 0;
- dma_ch[channel].regs->curr_y_count = 0;
- dma_ch[channel].regs->cfg |= DMAEN;
-}
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
-
-static inline void dma_disable_irq(unsigned int channel)
-{
- disable_irq(dma_ch[channel].irq);
-}
-static inline void dma_disable_irq_nosync(unsigned int channel)
-{
- disable_irq_nosync(dma_ch[channel].irq);
-}
-static inline void dma_enable_irq(unsigned int channel)
-{
- enable_irq(dma_ch[channel].irq);
-}
-static inline void clear_dma_irqstat(unsigned int channel)
-{
- dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
-}
-
-void *dma_memcpy(void *dest, const void *src, size_t count);
-void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
-void *safe_dma_memcpy(void *dest, const void *src, size_t count);
-void blackfin_dma_early_init(void);
-void early_dma_memcpy(void *dest, const void *src, size_t count);
-void early_dma_memcpy_done(void);
-
-#endif
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
deleted file mode 100644
index 2673b11376f4..000000000000
--- a/arch/blackfin/include/asm/dpmc.h
+++ /dev/null
@@ -1,794 +0,0 @@
-/*
- * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
- *
- * Copyright (C) 2004-2009 Analog Device Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BLACKFIN_DPMC_H_
-#define _BLACKFIN_DPMC_H_
-
-#ifdef __ASSEMBLY__
-#define PM_REG0 R7
-#define PM_REG1 R6
-#define PM_REG2 R5
-#define PM_REG3 R4
-#define PM_REG4 R3
-#define PM_REG5 R2
-#define PM_REG6 R1
-#define PM_REG7 R0
-#define PM_REG8 P5
-#define PM_REG9 P4
-#define PM_REG10 P3
-#define PM_REG11 P2
-#define PM_REG12 P1
-#define PM_REG13 P0
-
-#define PM_REGSET0 R7:7
-#define PM_REGSET1 R7:6
-#define PM_REGSET2 R7:5
-#define PM_REGSET3 R7:4
-#define PM_REGSET4 R7:3
-#define PM_REGSET5 R7:2
-#define PM_REGSET6 R7:1
-#define PM_REGSET7 R7:0
-#define PM_REGSET8 R7:0, P5:5
-#define PM_REGSET9 R7:0, P5:4
-#define PM_REGSET10 R7:0, P5:3
-#define PM_REGSET11 R7:0, P5:2
-#define PM_REGSET12 R7:0, P5:1
-#define PM_REGSET13 R7:0, P5:0
-
-#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
-#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
-#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
-#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
-#define PM_PUSH(n, x) PM_REG##n = [FP++];
-#define PM_POP(n, x) [FP--] = PM_REG##n;
-#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
-#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
-#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
-#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
-#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
-#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
-
- .macro bfin_init_pm_bench_cycles
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- R4 = 0;
- CYCLES = R4;
- CYCLES2 = R4;
- R4 = SYSCFG;
- BITSET(R4, 1);
- SYSCFG = R4;
-#endif
- .endm
-
- .macro bfin_cpu_reg_save
- /*
- * Save the core regs early so we can blow them away when
- * saving/restoring MMR states
- */
- [--sp] = (R7:0, P5:0);
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- /* We can't push RETI directly as that'll change IPEND[4] */
- r7 = RETI;
- [--sp] = RETS;
- [--sp] = ASTAT;
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- [--sp] = CYCLES;
- [--sp] = CYCLES2;
-#endif
- [--sp] = SYSCFG;
- [--sp] = RETX;
- [--sp] = SEQSTAT;
- [--sp] = r7;
-
- /* Save first func arg in M3 */
- M3 = R0;
- .endm
-
- .macro bfin_cpu_reg_restore
- /* Restore Core Registers */
- RETI = [sp++];
- SEQSTAT = [sp++];
- RETX = [sp++];
- SYSCFG = [sp++];
-#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- CYCLES2 = [sp++];
- CYCLES = [sp++];
-#endif
- ASTAT = [sp++];
- RETS = [sp++];
-
- LB1 = [sp++];
- LB0 = [sp++];
- LT1 = [sp++];
- LT0 = [sp++];
- LC1 = [sp++];
- LC0 = [sp++];
-
- a1.w = [sp++];
- a1.x = [sp++];
- a0.w = [sp++];
- a0.x = [sp++];
- b3 = [sp++];
- b2 = [sp++];
- b1 = [sp++];
- b0 = [sp++];
-
- l3 = [sp++];
- l2 = [sp++];
- l1 = [sp++];
- l0 = [sp++];
-
- m3 = [sp++];
- m2 = [sp++];
- m1 = [sp++];
- m0 = [sp++];
-
- i3 = [sp++];
- i2 = [sp++];
- i1 = [sp++];
- i0 = [sp++];
-
- usp = [sp++];
- fp = [sp++];
- (R7:0, P5:0) = [sp++];
-
- .endm
-
- .macro bfin_sys_mmr_save
- /* Save system MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-#ifdef SIC_IMASK0
- PM_SYS_PUSH(0, SIC_IMASK0)
- PM_SYS_PUSH(1, SIC_IMASK1)
-# ifdef SIC_IMASK2
- PM_SYS_PUSH(2, SIC_IMASK2)
-# endif
-#else
-# ifdef SIC_IMASK
- PM_SYS_PUSH(0, SIC_IMASK)
-# endif
-#endif
-
-#ifdef SIC_IAR0
- PM_SYS_PUSH(3, SIC_IAR0)
- PM_SYS_PUSH(4, SIC_IAR1)
- PM_SYS_PUSH(5, SIC_IAR2)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_PUSH(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR4
- PM_SYS_PUSH(7, SIC_IAR4)
- PM_SYS_PUSH(8, SIC_IAR5)
- PM_SYS_PUSH(9, SIC_IAR6)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_PUSH(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR8
- PM_SYS_PUSH(11, SIC_IAR8)
- PM_SYS_PUSH(12, SIC_IAR9)
- PM_SYS_PUSH(13, SIC_IAR10)
-#endif
- PM_PUSH_SYNC(13)
-#ifdef SIC_IAR11
- PM_SYS_PUSH(0, SIC_IAR11)
-#endif
-
-#ifdef SIC_IWR
- PM_SYS_PUSH(1, SIC_IWR)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_PUSH(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_PUSH(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR2
- PM_SYS_PUSH(3, SIC_IWR2)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_PUSH(4, PINT0_MASK_SET)
- PM_SYS_PUSH(5, PINT1_MASK_SET)
- PM_SYS_PUSH(6, PINT2_MASK_SET)
- PM_SYS_PUSH(7, PINT3_MASK_SET)
- PM_SYS_PUSH(8, PINT0_ASSIGN)
- PM_SYS_PUSH(9, PINT1_ASSIGN)
- PM_SYS_PUSH(10, PINT2_ASSIGN)
- PM_SYS_PUSH(11, PINT3_ASSIGN)
- PM_SYS_PUSH(12, PINT0_INVERT_SET)
- PM_SYS_PUSH(13, PINT1_INVERT_SET)
- PM_PUSH_SYNC(13)
- PM_SYS_PUSH(0, PINT2_INVERT_SET)
- PM_SYS_PUSH(1, PINT3_INVERT_SET)
- PM_SYS_PUSH(2, PINT0_EDGE_SET)
- PM_SYS_PUSH(3, PINT1_EDGE_SET)
- PM_SYS_PUSH(4, PINT2_EDGE_SET)
- PM_SYS_PUSH(5, PINT3_EDGE_SET)
-#endif
-
-#ifdef SYSCR
- PM_SYS_PUSH16(6, SYSCR)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_PUSH16(7, EBIU_AMGCTL)
- PM_SYS_PUSH(8, EBIU_AMBCTL0)
- PM_SYS_PUSH(9, EBIU_AMBCTL1)
-#endif
-#ifdef EBIU_FCTL
- PM_SYS_PUSH(10, EBIU_MBSCTL)
- PM_SYS_PUSH(11, EBIU_MODE)
- PM_SYS_PUSH(12, EBIU_FCTL)
- PM_PUSH_SYNC(12)
-#else
- PM_PUSH_SYNC(9)
-#endif
- .endm
-
-
- .macro bfin_sys_mmr_restore
-/* Restore System MMRs */
- FP.H = hi(SYSMMR_BASE);
- FP.L = lo(SYSMMR_BASE);
-
-#ifdef EBIU_FCTL
- PM_POP_SYNC(12)
- PM_SYS_POP(12, EBIU_FCTL)
- PM_SYS_POP(11, EBIU_MODE)
- PM_SYS_POP(10, EBIU_MBSCTL)
-#else
- PM_POP_SYNC(9)
-#endif
-
-#ifdef EBIU_AMGCTL
- PM_SYS_POP(9, EBIU_AMBCTL1)
- PM_SYS_POP(8, EBIU_AMBCTL0)
- PM_SYS_POP16(7, EBIU_AMGCTL)
-#endif
-
-#ifdef SYSCR
- PM_SYS_POP16(6, SYSCR)
-#endif
-
-#ifdef PINT0_ASSIGN
- PM_SYS_POP(5, PINT3_EDGE_SET)
- PM_SYS_POP(4, PINT2_EDGE_SET)
- PM_SYS_POP(3, PINT1_EDGE_SET)
- PM_SYS_POP(2, PINT0_EDGE_SET)
- PM_SYS_POP(1, PINT3_INVERT_SET)
- PM_SYS_POP(0, PINT2_INVERT_SET)
- PM_POP_SYNC(13)
- PM_SYS_POP(13, PINT1_INVERT_SET)
- PM_SYS_POP(12, PINT0_INVERT_SET)
- PM_SYS_POP(11, PINT3_ASSIGN)
- PM_SYS_POP(10, PINT2_ASSIGN)
- PM_SYS_POP(9, PINT1_ASSIGN)
- PM_SYS_POP(8, PINT0_ASSIGN)
- PM_SYS_POP(7, PINT3_MASK_SET)
- PM_SYS_POP(6, PINT2_MASK_SET)
- PM_SYS_POP(5, PINT1_MASK_SET)
- PM_SYS_POP(4, PINT0_MASK_SET)
-#endif
-
-#ifdef SIC_IWR2
- PM_SYS_POP(3, SIC_IWR2)
-#endif
-#ifdef SIC_IWR1
- PM_SYS_POP(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR0
- PM_SYS_POP(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR
- PM_SYS_POP(1, SIC_IWR)
-#endif
-
-#ifdef SIC_IAR11
- PM_SYS_POP(0, SIC_IAR11)
-#endif
- PM_POP_SYNC(13)
-#ifdef SIC_IAR8
- PM_SYS_POP(13, SIC_IAR10)
- PM_SYS_POP(12, SIC_IAR9)
- PM_SYS_POP(11, SIC_IAR8)
-#endif
-#ifdef SIC_IAR7
- PM_SYS_POP(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR6
- PM_SYS_POP(9, SIC_IAR6)
- PM_SYS_POP(8, SIC_IAR5)
- PM_SYS_POP(7, SIC_IAR4)
-#endif
-#ifdef SIC_IAR3
- PM_SYS_POP(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR0
- PM_SYS_POP(5, SIC_IAR2)
- PM_SYS_POP(4, SIC_IAR1)
- PM_SYS_POP(3, SIC_IAR0)
-#endif
-#ifdef SIC_IMASK0
-# ifdef SIC_IMASK2
- PM_SYS_POP(2, SIC_IMASK2)
-# endif
- PM_SYS_POP(1, SIC_IMASK1)
- PM_SYS_POP(0, SIC_IMASK0)
-#else
-# ifdef SIC_IMASK
- PM_SYS_POP(0, SIC_IMASK)
-# endif
-#endif
- .endm
-
- .macro bfin_core_mmr_save
- /* Save Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR0);
- I2.L = lo(DCPLB_DATA0);
- I3.L = lo(ICPLB_ADDR0);
- B0.L = lo(ICPLB_DATA0);
- B1.L = lo(EVT2);
- B2.L = lo(IMASK);
- B3.L = lo(TCNTL);
-
- /* Event Vectors */
- FP = B1;
- PM_PUSH(0, EVT2)
- PM_PUSH(1, EVT3)
- FP += 4; /* EVT4 */
- PM_PUSH(2, EVT5)
- PM_PUSH(3, EVT6)
- PM_PUSH(4, EVT7)
- PM_PUSH(5, EVT8)
- PM_PUSH_SYNC(5)
-
- PM_PUSH(0, EVT9)
- PM_PUSH(1, EVT10)
- PM_PUSH(2, EVT11)
- PM_PUSH(3, EVT12)
- PM_PUSH(4, EVT13)
- PM_PUSH(5, EVT14)
- PM_PUSH(6, EVT15)
-
- /* CEC */
- FP = B2;
- PM_PUSH(7, IMASK)
- FP += 4; /* IPEND */
- PM_PUSH(8, ILAT)
- PM_PUSH(9, IPRIO)
-
- /* Core Timer */
- FP = B3;
- PM_PUSH(10, TCNTL)
- PM_PUSH(11, TPERIOD)
- PM_PUSH(12, TSCALE)
- PM_PUSH(13, TCOUNT)
- PM_PUSH_SYNC(13)
-
- /* Misc non-contiguous registers */
- FP = I0;
- PM_CORE_PUSH(0, DMEM_CONTROL);
- PM_CORE_PUSH(1, IMEM_CONTROL);
- PM_CORE_PUSH(2, TBUFCTL);
- PM_PUSH_SYNC(2)
-
- /* DCPLB Addr */
- FP = I1;
- PM_PUSH(0, DCPLB_ADDR0)
- PM_PUSH(1, DCPLB_ADDR1)
- PM_PUSH(2, DCPLB_ADDR2)
- PM_PUSH(3, DCPLB_ADDR3)
- PM_PUSH(4, DCPLB_ADDR4)
- PM_PUSH(5, DCPLB_ADDR5)
- PM_PUSH(6, DCPLB_ADDR6)
- PM_PUSH(7, DCPLB_ADDR7)
- PM_PUSH(8, DCPLB_ADDR8)
- PM_PUSH(9, DCPLB_ADDR9)
- PM_PUSH(10, DCPLB_ADDR10)
- PM_PUSH(11, DCPLB_ADDR11)
- PM_PUSH(12, DCPLB_ADDR12)
- PM_PUSH(13, DCPLB_ADDR13)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_ADDR14)
- PM_PUSH(1, DCPLB_ADDR15)
-
- /* DCPLB Data */
- FP = I2;
- PM_PUSH(2, DCPLB_DATA0)
- PM_PUSH(3, DCPLB_DATA1)
- PM_PUSH(4, DCPLB_DATA2)
- PM_PUSH(5, DCPLB_DATA3)
- PM_PUSH(6, DCPLB_DATA4)
- PM_PUSH(7, DCPLB_DATA5)
- PM_PUSH(8, DCPLB_DATA6)
- PM_PUSH(9, DCPLB_DATA7)
- PM_PUSH(10, DCPLB_DATA8)
- PM_PUSH(11, DCPLB_DATA9)
- PM_PUSH(12, DCPLB_DATA10)
- PM_PUSH(13, DCPLB_DATA11)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, DCPLB_DATA12)
- PM_PUSH(1, DCPLB_DATA13)
- PM_PUSH(2, DCPLB_DATA14)
- PM_PUSH(3, DCPLB_DATA15)
-
- /* ICPLB Addr */
- FP = I3;
- PM_PUSH(4, ICPLB_ADDR0)
- PM_PUSH(5, ICPLB_ADDR1)
- PM_PUSH(6, ICPLB_ADDR2)
- PM_PUSH(7, ICPLB_ADDR3)
- PM_PUSH(8, ICPLB_ADDR4)
- PM_PUSH(9, ICPLB_ADDR5)
- PM_PUSH(10, ICPLB_ADDR6)
- PM_PUSH(11, ICPLB_ADDR7)
- PM_PUSH(12, ICPLB_ADDR8)
- PM_PUSH(13, ICPLB_ADDR9)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_ADDR10)
- PM_PUSH(1, ICPLB_ADDR11)
- PM_PUSH(2, ICPLB_ADDR12)
- PM_PUSH(3, ICPLB_ADDR13)
- PM_PUSH(4, ICPLB_ADDR14)
- PM_PUSH(5, ICPLB_ADDR15)
-
- /* ICPLB Data */
- FP = B0;
- PM_PUSH(6, ICPLB_DATA0)
- PM_PUSH(7, ICPLB_DATA1)
- PM_PUSH(8, ICPLB_DATA2)
- PM_PUSH(9, ICPLB_DATA3)
- PM_PUSH(10, ICPLB_DATA4)
- PM_PUSH(11, ICPLB_DATA5)
- PM_PUSH(12, ICPLB_DATA6)
- PM_PUSH(13, ICPLB_DATA7)
- PM_PUSH_SYNC(13)
- PM_PUSH(0, ICPLB_DATA8)
- PM_PUSH(1, ICPLB_DATA9)
- PM_PUSH(2, ICPLB_DATA10)
- PM_PUSH(3, ICPLB_DATA11)
- PM_PUSH(4, ICPLB_DATA12)
- PM_PUSH(5, ICPLB_DATA13)
- PM_PUSH(6, ICPLB_DATA14)
- PM_PUSH(7, ICPLB_DATA15)
- PM_PUSH_SYNC(7)
- .endm
-
- .macro bfin_core_mmr_restore
- /* Restore Core MMRs */
- I0.H = hi(COREMMR_BASE);
- I0.L = lo(COREMMR_BASE);
- I1 = I0;
- I2 = I0;
- I3 = I0;
- B0 = I0;
- B1 = I0;
- B2 = I0;
- B3 = I0;
- I1.L = lo(DCPLB_ADDR15);
- I2.L = lo(DCPLB_DATA15);
- I3.L = lo(ICPLB_ADDR15);
- B0.L = lo(ICPLB_DATA15);
- B1.L = lo(EVT15);
- B2.L = lo(IPRIO);
- B3.L = lo(TCOUNT);
-
- /* ICPLB Data */
- FP = B0;
- PM_POP_SYNC(7)
- PM_POP(7, ICPLB_DATA15)
- PM_POP(6, ICPLB_DATA14)
- PM_POP(5, ICPLB_DATA13)
- PM_POP(4, ICPLB_DATA12)
- PM_POP(3, ICPLB_DATA11)
- PM_POP(2, ICPLB_DATA10)
- PM_POP(1, ICPLB_DATA9)
- PM_POP(0, ICPLB_DATA8)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_DATA7)
- PM_POP(12, ICPLB_DATA6)
- PM_POP(11, ICPLB_DATA5)
- PM_POP(10, ICPLB_DATA4)
- PM_POP(9, ICPLB_DATA3)
- PM_POP(8, ICPLB_DATA2)
- PM_POP(7, ICPLB_DATA1)
- PM_POP(6, ICPLB_DATA0)
-
- /* ICPLB Addr */
- FP = I3;
- PM_POP(5, ICPLB_ADDR15)
- PM_POP(4, ICPLB_ADDR14)
- PM_POP(3, ICPLB_ADDR13)
- PM_POP(2, ICPLB_ADDR12)
- PM_POP(1, ICPLB_ADDR11)
- PM_POP(0, ICPLB_ADDR10)
- PM_POP_SYNC(13)
- PM_POP(13, ICPLB_ADDR9)
- PM_POP(12, ICPLB_ADDR8)
- PM_POP(11, ICPLB_ADDR7)
- PM_POP(10, ICPLB_ADDR6)
- PM_POP(9, ICPLB_ADDR5)
- PM_POP(8, ICPLB_ADDR4)
- PM_POP(7, ICPLB_ADDR3)
- PM_POP(6, ICPLB_ADDR2)
- PM_POP(5, ICPLB_ADDR1)
- PM_POP(4, ICPLB_ADDR0)
-
- /* DCPLB Data */
- FP = I2;
- PM_POP(3, DCPLB_DATA15)
- PM_POP(2, DCPLB_DATA14)
- PM_POP(1, DCPLB_DATA13)
- PM_POP(0, DCPLB_DATA12)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_DATA11)
- PM_POP(12, DCPLB_DATA10)
- PM_POP(11, DCPLB_DATA9)
- PM_POP(10, DCPLB_DATA8)
- PM_POP(9, DCPLB_DATA7)
- PM_POP(8, DCPLB_DATA6)
- PM_POP(7, DCPLB_DATA5)
- PM_POP(6, DCPLB_DATA4)
- PM_POP(5, DCPLB_DATA3)
- PM_POP(4, DCPLB_DATA2)
- PM_POP(3, DCPLB_DATA1)
- PM_POP(2, DCPLB_DATA0)
-
- /* DCPLB Addr */
- FP = I1;
- PM_POP(1, DCPLB_ADDR15)
- PM_POP(0, DCPLB_ADDR14)
- PM_POP_SYNC(13)
- PM_POP(13, DCPLB_ADDR13)
- PM_POP(12, DCPLB_ADDR12)
- PM_POP(11, DCPLB_ADDR11)
- PM_POP(10, DCPLB_ADDR10)
- PM_POP(9, DCPLB_ADDR9)
- PM_POP(8, DCPLB_ADDR8)
- PM_POP(7, DCPLB_ADDR7)
- PM_POP(6, DCPLB_ADDR6)
- PM_POP(5, DCPLB_ADDR5)
- PM_POP(4, DCPLB_ADDR4)
- PM_POP(3, DCPLB_ADDR3)
- PM_POP(2, DCPLB_ADDR2)
- PM_POP(1, DCPLB_ADDR1)
- PM_POP(0, DCPLB_ADDR0)
-
-
- /* Misc non-contiguous registers */
-
- /* icache & dcache will enable later
- drop IMEM_CONTROL, DMEM_CONTROL pop
- */
- FP = I0;
- PM_POP_SYNC(2)
- PM_CORE_POP(2, TBUFCTL)
- PM_CORE_POP(1, IMEM_CONTROL)
- PM_CORE_POP(0, DMEM_CONTROL)
-
- /* Core Timer */
- FP = B3;
- R0 = 0x1;
- [FP - 0xC] = R0;
-
- PM_POP_SYNC(13)
- FP = B3;
- PM_POP(13, TCOUNT)
- PM_POP(12, TSCALE)
- PM_POP(11, TPERIOD)
- PM_POP(10, TCNTL)
-
- /* CEC */
- FP = B2;
- PM_POP(9, IPRIO)
- PM_POP(8, ILAT)
- FP += -4; /* IPEND */
- PM_POP(7, IMASK)
-
- /* Event Vectors */
- FP = B1;
- PM_POP(6, EVT15)
- PM_POP(5, EVT14)
- PM_POP(4, EVT13)
- PM_POP(3, EVT12)
- PM_POP(2, EVT11)
- PM_POP(1, EVT10)
- PM_POP(0, EVT9)
- PM_POP_SYNC(5)
- PM_POP(5, EVT8)
- PM_POP(4, EVT7)
- PM_POP(3, EVT6)
- PM_POP(2, EVT5)
- FP += -4; /* EVT4 */
- PM_POP(1, EVT3)
- PM_POP(0, EVT2)
- .endm
-#endif
-
-#include <mach/pll.h>
-
-/* PLL_CTL Masks */
-#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define PLL_OFF 0x0002 /* PLL Not Powered */
-#define STOPCK 0x0008 /* Core Clock Off */
-#define PDWN 0x0020 /* Enter Deep Sleep Mode */
-#ifdef __ADSPBF539__
-# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
-#else
-# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
-#endif
-#define BYPASS 0x0100 /* Bypass the PLL */
-#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
-#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
-#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-
-/* PLL_DIV Masks */
-#define SSEL 0x000F /* System Select */
-#define CSEL 0x0030 /* Core Select */
-#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
-#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
-#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
-#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
-
-#define CCLK_DIV1 CSEL_DIV1
-#define CCLK_DIV2 CSEL_DIV2
-#define CCLK_DIV4 CSEL_DIV4
-#define CCLK_DIV8 CSEL_DIV8
-
-#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
-
-/* PLL_STAT Masks */
-#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
-#define FULL_ON 0x0002 /* Processor In Full On Mode */
-#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
-#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
-
-#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
-#define CANWS 0x0800 /* CAN Wake-Up Status */
-#define USBWS 0x2000 /* USB Wake-Up Status */
-#define KPADWS 0x4000 /* Keypad Wake-Up Status */
-#define ROTWS 0x8000 /* Rotary Wake-Up Status */
-#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
-
-/* VR_CTL Masks */
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
-#else
-#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
-#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
-#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
-#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
-#endif
-#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
-
-#define GAIN 0x000C /* Voltage Level Gain */
-#define GAIN_5 0x0000 /* GAIN = 5 */
-#define GAIN_10 0x0004 /* GAIN = 1 */
-#define GAIN_20 0x0008 /* GAIN = 2 */
-#define GAIN_50 0x000C /* GAIN = 5 */
-
-#define VLEV 0x00F0 /* Internal Voltage Level */
-#ifdef __ADSPBF52x__
-#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#else
-#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-#endif
-
-#ifdef CONFIG_BF60x
-#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */
-#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */
-#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */
-#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
-#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
-#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
-#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */
-#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */
-#else
-#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
-#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
-#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
-#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
-#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
-#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
-#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
-#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
-#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
-
-#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
-#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
-#else
-#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
-#endif
-#endif
-
-#ifndef __ASSEMBLY__
-
-void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void do_hibernate(int wakeup);
-void set_dram_srfs(void);
-void unset_dram_srfs(void);
-
-#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
-
-#ifdef CONFIG_CPU_FREQ
-#define CPUFREQ_CPU 0
-#endif
-struct bfin_dpmc_platform_data {
- const unsigned int *tuple_tab;
- unsigned short tabsize;
- unsigned short vr_settling_time; /* in us */
-};
-
-#endif
-
-#endif /*_BLACKFIN_DPMC_H_*/
diff --git a/arch/blackfin/include/asm/early_printk.h b/arch/blackfin/include/asm/early_printk.h
deleted file mode 100644
index 68a910db8864..000000000000
--- a/arch/blackfin/include/asm/early_printk.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * function prototpyes for early printk
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_EARLY_PRINTK_H__
-#define __ASM_EARLY_PRINTK_H__
-
-#ifdef CONFIG_EARLY_PRINTK
-/* For those that don't include it already */
-#include <linux/console.h>
-
-extern int setup_early_printk(char *);
-extern void enable_shadow_console(void);
-extern int shadow_console_enabled(void);
-extern void mark_shadow_error(void);
-extern void early_shadow_reg(unsigned long reg, unsigned int n);
-extern void early_shadow_write(struct console *con, const char *s,
- unsigned int n) __attribute__((nonnull(2)));
-#define early_shadow_puts(str) early_shadow_write(NULL, str, strlen(str))
-#define early_shadow_stamp() \
- do { \
- early_shadow_puts(__FILE__ " : " __stringify(__LINE__) " ["); \
- early_shadow_puts(__func__); \
- early_shadow_puts("]\n"); \
- } while (0)
-#else
-#define setup_early_printk(fmt) do { } while (0)
-#define enable_shadow_console(fmt) do { } while (0)
-#define early_shadow_stamp() do { } while (0)
-#endif /* CONFIG_EARLY_PRINTK */
-
-#endif /* __ASM_EARLY_PRINTK_H__ */
diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h
deleted file mode 100644
index d15cb9b5d52c..000000000000
--- a/arch/blackfin/include/asm/elf.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASMBFIN_ELF_H
-#define __ASMBFIN_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/* Processor specific flags for the ELF header e_flags field. */
-#define EF_BFIN_PIC 0x00000001 /* -fpic */
-#define EF_BFIN_FDPIC 0x00000002 /* -mfdpic */
-#define EF_BFIN_CODE_IN_L1 0x00000010 /* --code-in-l1 */
-#define EF_BFIN_DATA_IN_L1 0x00000020 /* --data-in-l1 */
-#define EF_BFIN_CODE_IN_L2 0x00000040 /* --code-in-l2 */
-#define EF_BFIN_DATA_IN_L2 0x00000080 /* --data-in-l2 */
-
-#if 1 /* core dumps not supported, but linux/elfcore.h needs these */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct { } elf_fpregset_t;
-#endif
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
-
-/* EM_BLACKFIN defined in linux/elf.h */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_BLACKFIN
-
-#define ELF_PLAT_INIT(_r) _r->p1 = 0
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
-do { \
- _regs->r7 = 0; \
- _regs->p0 = _exec_map_addr; \
- _regs->p1 = _interp_map_addr; \
- _regs->p2 = _dynamic_addr; \
-} while(0)
-
-#if 0
-#define CORE_DUMP_USE_REGSET
-#endif
-#define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC
-#define ELF_EXEC_PAGESIZE 4096
-
-#define R_BFIN_UNUSED0 0 /* relocation type 0 is not defined */
-#define R_BFIN_PCREL5M2 1 /* LSETUP part a */
-#define R_BFIN_UNUSED1 2 /* relocation type 2 is not defined */
-#define R_BFIN_PCREL10 3 /* type 3, if cc jump <target> */
-#define R_BFIN_PCREL12_JUMP 4 /* type 4, jump <target> */
-#define R_BFIN_RIMM16 5 /* type 0x5, rN = <target> */
-#define R_BFIN_LUIMM16 6 /* # 0x6, preg.l=<target> Load imm 16 to lower half */
-#define R_BFIN_HUIMM16 7 /* # 0x7, preg.h=<target> Load imm 16 to upper half */
-#define R_BFIN_PCREL12_JUMP_S 8 /* # 0x8 jump.s <target> */
-#define R_BFIN_PCREL24_JUMP_X 9 /* # 0x9 jump.x <target> */
-#define R_BFIN_PCREL24 10 /* # 0xa call <target> , not expandable */
-#define R_BFIN_UNUSEDB 11 /* # 0xb not generated */
-#define R_BFIN_UNUSEDC 12 /* # 0xc not used */
-#define R_BFIN_PCREL24_JUMP_L 13 /* 0xd jump.l <target> */
-#define R_BFIN_PCREL24_CALL_X 14 /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
-#define R_BFIN_VAR_EQ_SYMB 15 /* 0xf, linker should treat it same as 0x12 */
-#define R_BFIN_BYTE_DATA 16 /* 0x10, .byte var = symbol */
-#define R_BFIN_BYTE2_DATA 17 /* 0x11, .byte2 var = symbol */
-#define R_BFIN_BYTE4_DATA 18 /* 0x12, .byte4 var = symbol and .var var=symbol */
-#define R_BFIN_PCREL11 19 /* 0x13, lsetup part b */
-#define R_BFIN_UNUSED14 20 /* 0x14, undefined */
-#define R_BFIN_UNUSED15 21 /* not generated by VDSP 3.5 */
-
-/* arithmetic relocations */
-#define R_BFIN_PUSH 0xE0
-#define R_BFIN_CONST 0xE1
-#define R_BFIN_ADD 0xE2
-#define R_BFIN_SUB 0xE3
-#define R_BFIN_MULT 0xE4
-#define R_BFIN_DIV 0xE5
-#define R_BFIN_MOD 0xE6
-#define R_BFIN_LSHIFT 0xE7
-#define R_BFIN_RSHIFT 0xE8
-#define R_BFIN_AND 0xE9
-#define R_BFIN_OR 0xEA
-#define R_BFIN_XOR 0xEB
-#define R_BFIN_LAND 0xEC
-#define R_BFIN_LOR 0xED
-#define R_BFIN_LEN 0xEE
-#define R_BFIN_NEG 0xEF
-#define R_BFIN_COMP 0xF0
-#define R_BFIN_PAGE 0xF1
-#define R_BFIN_HWPAGE 0xF2
-#define R_BFIN_ADDR 0xF3
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- memcpy((char *) &pr_reg, (char *)regs, \
- sizeof(struct pt_regs));
-#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
deleted file mode 100644
index 4104d5783e2c..000000000000
--- a/arch/blackfin/include/asm/entry.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_ENTRY_H
-#define __BFIN_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#ifdef __ASSEMBLY__
-
-#define LFLUSH_I_AND_D 0x00000808
-#define LSIGTRAP 5
-
-/*
- * NOTE! The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/* This one is used for exceptions, emulation, and NMI. It doesn't push
- RETI and doesn't do cli. */
-#define SAVE_ALL_SYS save_context_no_interrupts
-/* This is used for all normal interrupts. It saves a minimum of registers
- to the stack, loads the IRQ number, and jumps to common code. */
-#ifdef CONFIG_IPIPE
-# define LOAD_IPIPE_IPEND \
- P0.l = lo(IPEND); \
- P0.h = hi(IPEND); \
- R1 = [P0];
-#else
-# define LOAD_IPIPE_IPEND
-#endif
-
-/*
- * Workaround for anomalies 05000283 and 05000315
- */
-#if ANOMALY_05000283 || ANOMALY_05000315
-# define ANOMALY_283_315_WORKAROUND(preg, dreg) \
- cc = dreg == dreg; \
- preg.h = HI(CHIPID); \
- preg.l = LO(CHIPID); \
- if cc jump 1f; \
- dreg.l = W[preg]; \
-1:
-#else
-# define ANOMALY_283_315_WORKAROUND(preg, dreg)
-#endif /* ANOMALY_05000283 || ANOMALY_05000315 */
-
-#ifndef CONFIG_EXACT_HWERR
-/* As a debugging aid - we save IPEND when DEBUG_KERNEL is on,
- * otherwise it is a waste of cycles.
- */
-# ifndef CONFIG_DEBUG_KERNEL
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# else /* CONFIG_DEBUG_KERNEL */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry;
-# endif /* CONFIG_DEBUG_KERNEL */
-
-/* For timer interrupts, we need to save IPEND, since the user_mode
- *macro accesses it to determine where to account time.
- */
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry;
-#else /* CONFIG_EXACT_HWERR is defined */
-
-/* if we want hardware error to be exact, we need to do a SSYNC (which forces
- * read/writes to complete to the memory controllers), and check to see that
- * caused a pending HW error condition. If so, we assume it was caused by user
- * space, by setting the same interrupt that we are in (so it goes off again)
- * and context restore, and a RTI (without servicing anything). This should
- * cause the pending HWERR to fire, and when that is done, this interrupt will
- * be re-serviced properly.
- * As you can see by the code - we actually need to do two SSYNCS - one to
- * make sure the read/writes complete, and another to make sure the hardware
- * error is recognized by the core.
- *
- * The extra nop before the SSYNC is to make sure we work around 05000244,
- * since the 283/315 workaround includes a branch to the end
- */
-#define INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- LOAD_IPIPE_IPEND \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-
-#define TIMER_INTERRUPT_ENTRY(N) \
- [--sp] = SYSCFG; \
- [--sp] = P0; /*orig_p0*/ \
- [--sp] = R0; /*orig_r0*/ \
- [--sp] = (R7:0,P5:0); \
- R1 = ASTAT; \
- ANOMALY_283_315_WORKAROUND(p0, r0) \
- P0.L = LO(ILAT); \
- P0.H = HI(ILAT); \
- NOP; \
- SSYNC; \
- SSYNC; \
- R0 = [P0]; \
- CC = BITTST(R0, EVT_IVHW_P); \
- IF CC JUMP 1f; \
- ASTAT = R1; \
- p0.l = lo(IPEND); \
- p0.h = hi(IPEND); \
- r1 = [p0]; \
- R0 = (N); \
- jump __common_int_entry; \
-1: ASTAT = R1; \
- RAISE N; \
- (R7:0, P5:0) = [SP++]; \
- SP += 0x8; \
- SYSCFG = [SP++]; \
- CSYNC; \
- RTI;
-#endif /* CONFIG_EXACT_HWERR */
-
-/* This one pushes RETI without using CLI. Interrupts are enabled. */
-#define SAVE_CONTEXT_SYSCALL save_context_syscall
-#define SAVE_CONTEXT save_context_with_interrupts
-#define SAVE_CONTEXT_CPLB save_context_cplb
-
-#define RESTORE_ALL_SYS restore_context_no_interrupts
-#define RESTORE_CONTEXT restore_context_with_interrupts
-#define RESTORE_CONTEXT_CPLB restore_context_cplb
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BFIN_ENTRY_H */
diff --git a/arch/blackfin/include/asm/exec.h b/arch/blackfin/include/asm/exec.h
deleted file mode 100644
index 54c2e1db274a..000000000000
--- a/arch/blackfin/include/asm/exec.h
+++ /dev/null
@@ -1 +0,0 @@
-/* define arch_align_stack() here */
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
deleted file mode 100644
index bc330f06207b..000000000000
--- a/arch/blackfin/include/asm/fixed_code.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __BFIN_ASM_FIXED_CODE_H__
-#define __BFIN_ASM_FIXED_CODE_H__
-
-#include <uapi/asm/fixed_code.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/linkage.h>
-#include <linux/ptrace.h>
-extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
-extern char fixed_code_start;
-extern char fixed_code_end;
-extern int atomic_xchg32(void);
-extern int atomic_cas32(void);
-extern int atomic_add32(void);
-extern int atomic_sub32(void);
-extern int atomic_ior32(void);
-extern int atomic_and32(void);
-extern int atomic_xor32(void);
-extern void safe_user_instruction(void);
-extern void sigreturn_stub(void);
-#endif
-#endif
diff --git a/arch/blackfin/include/asm/flat.h b/arch/blackfin/include/asm/flat.h
deleted file mode 100644
index f1d6ba7afbf2..000000000000
--- a/arch/blackfin/include/asm/flat.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * uClinux flat-format executables
- *
- * Copyright 2003-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __BLACKFIN_FLAT_H__
-#define __BLACKFIN_FLAT_H__
-
-#include <asm/unaligned.h>
-
-#define flat_argvp_envp_on_stack() 0
-#define flat_old_ram_flag(flags) (flags)
-
-extern unsigned long bfin_get_addr_from_rp (u32 *ptr, u32 relval,
- u32 flags, u32 *persistent);
-
-extern void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval);
-
-/* The amount by which a relocation can exceed the program image limits
- without being regarded as an error. */
-
-#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
-
-static inline int flat_get_addr_from_rp(u32 __user *rp, u32 relval, u32 flags,
- u32 *addr, u32 *persistent)
-{
- *addr = bfin_get_addr_from_rp(rp, relval, flags, persistent);
- return 0;
-}
-
-static inline int flat_put_addr_at_rp(u32 __user *rp, u32 val, u32 relval)
-{
- bfin_put_addr_at_rp(rp, val, relval);
- return 0;
-}
-
-/* Convert a relocation entry into an address. */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
- return relval & 0x03ffffff; /* Mask out top 6 bits */
-}
-
-static inline int flat_set_persistent(u32 relval, u32 *persistent)
-{
- int type = (relval >> 26) & 7;
- if (type == 3) {
- *persistent = relval << 16;
- return 1;
- }
- return 0;
-}
-
-static inline int flat_addr_absolute(unsigned long relval)
-{
- return (relval & (1 << 29)) != 0;
-}
-
-#endif /* __BLACKFIN_FLAT_H__ */
diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h
deleted file mode 100644
index 2f1c3c2657ad..000000000000
--- a/arch/blackfin/include/asm/ftrace.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Blackfin ftrace code
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_FTRACE_H__
-#define __ASM_BFIN_FTRACE_H__
-
-#define MCOUNT_INSN_SIZE 6 /* sizeof "[++sp] = rets; call __mcount;" */
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void _mcount(void);
-#define MCOUNT_ADDR ((unsigned long)_mcount)
-
-static inline unsigned long ftrace_call_adjust(unsigned long addr)
-{
- return addr;
-}
-
-struct dyn_arch_ftrace {
- /* No extra data needed for Blackfin */
-};
-
-#endif
-
-#ifdef CONFIG_FRAME_POINTER
-#include <linux/mm.h>
-
-extern inline void *return_address(unsigned int level)
-{
- unsigned long *endstack, *fp, *ret_addr;
- unsigned int current_level = 0;
-
- if (level == 0)
- return __builtin_return_address(0);
-
- fp = (unsigned long *)__builtin_frame_address(0);
- endstack = (unsigned long *)PAGE_ALIGN((unsigned long)&level);
-
- while (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack && current_level < level) {
- fp = (unsigned long *)*fp;
- current_level++;
- }
-
- if (((unsigned long)fp & 0x3) == 0 && fp &&
- (fp + 1) < endstack)
- ret_addr = (unsigned long *)*(fp + 1);
- else
- ret_addr = NULL;
-
- return ret_addr;
-}
-
-#else
-
-extern inline void *return_address(unsigned int level)
-{
- return NULL;
-}
-
-#endif /* CONFIG_FRAME_POINTER */
-
-#define ftrace_return_address(n) return_address(n)
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
deleted file mode 100644
index a2579321c7f1..000000000000
--- a/arch/blackfin/include/asm/gpio.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x) (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
-
-#define GPIO_BANKSIZE 16
-#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
-
-#include <mach/gpio.h>
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-
-#ifndef BFIN_GPIO_PINT
-# define BFIN_GPIO_PINT 0
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifndef CONFIG_PINCTRL
-
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/irq_handler.h>
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
- unsigned short data;
- unsigned short dummy1;
- unsigned short data_clear;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short toggle;
- unsigned short dummy4;
- unsigned short maska;
- unsigned short dummy5;
- unsigned short maska_clear;
- unsigned short dummy6;
- unsigned short maska_set;
- unsigned short dummy7;
- unsigned short maska_toggle;
- unsigned short dummy8;
- unsigned short maskb;
- unsigned short dummy9;
- unsigned short maskb_clear;
- unsigned short dummy10;
- unsigned short maskb_set;
- unsigned short dummy11;
- unsigned short maskb_toggle;
- unsigned short dummy12;
- unsigned short dir;
- unsigned short dummy13;
- unsigned short polar;
- unsigned short dummy14;
- unsigned short edge;
- unsigned short dummy15;
- unsigned short both;
- unsigned short dummy16;
- unsigned short inen;
-};
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-void bfin_special_gpio_free(unsigned gpio);
-int bfin_special_gpio_request(unsigned gpio, const char *label);
-# ifdef CONFIG_PM
-void bfin_special_gpio_pm_hibernate_restore(void);
-void bfin_special_gpio_pm_hibernate_suspend(void);
-# endif
-#endif
-
-#ifdef CONFIG_PM
-void bfin_gpio_pm_hibernate_restore(void);
-void bfin_gpio_pm_hibernate_suspend(void);
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
-
-static inline int bfin_pm_standby_setup(void)
-{
- return bfin_gpio_pm_standby_ctrl(1);
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
- bfin_gpio_pm_standby_ctrl(0);
-}
-
-
-struct gpio_port_s {
- unsigned short data;
- unsigned short maska;
- unsigned short maskb;
- unsigned short dir;
- unsigned short polar;
- unsigned short edge;
- unsigned short both;
- unsigned short inen;
-
- unsigned short fer;
- unsigned short reserved;
- unsigned short mux;
-};
-#endif /*CONFIG_PM*/
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_irq_request(unsigned gpio, const char *label);
-void bfin_gpio_irq_free(unsigned gpio);
-void bfin_gpio_irq_prepare(unsigned gpio);
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq - GPIO_IRQ_BASE;
-}
-
-#else /* CONFIG_PINCTRL */
-
-/*
- * CONFIG_PM is not working with pin control and should probably
- * avoid being selected when pin control is active, but so far,
- * these stubs are here to make allyesconfig and allmodconfig
- * compile properly. These functions are normally backed by the
- * CONFIG_ADI_GPIO custom GPIO implementation.
- */
-
-static inline int bfin_pm_standby_setup(void)
-{
- return 0;
-}
-
-static inline void bfin_pm_standby_restore(void)
-{
-}
-
-#endif /* CONFIG_PINCTRL */
-
-#include <asm/irq.h>
-#include <asm/errno.h>
-
-#include <asm-generic/gpio.h> /* cansleep wrappers */
-
-static inline int gpio_get_value(unsigned int gpio)
-{
- return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int value)
-{
- __gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
- return __gpio_cansleep(gpio);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return __gpio_to_irq(gpio);
-}
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
deleted file mode 100644
index 381e3d621a4c..000000000000
--- a/arch/blackfin/include/asm/gptimers.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _BLACKFIN_TIMERS_H_
-#define _BLACKFIN_TIMERS_H_
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * BF51x/BF52x/BF537: 8 timers:
- */
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || defined(BF537_FAMILY)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-/*
- * BF54x: 11 timers (BF542: 8 timers):
- */
-#if defined(CONFIG_BF54x)
-# ifdef CONFIG_BF542
-# define MAX_BLACKFIN_GPTIMERS 8
-# else
-# define MAX_BLACKFIN_GPTIMERS 11
-# define TIMER8_GROUP_REG TIMER_ENABLE1
-# define TIMER_GROUP2 1
-# endif
-# define TIMER0_GROUP_REG TIMER_ENABLE0
-#endif
-/*
- * BF561: 12 timers:
- */
-#if defined(CONFIG_BF561)
-# define MAX_BLACKFIN_GPTIMERS 12
-# define TIMER0_GROUP_REG TMRS8_ENABLE
-# define TIMER8_GROUP_REG TMRS4_ENABLE
-# define TIMER_GROUP2 1
-#endif
-/*
- * BF609: 8 timers:
- */
-#if defined(CONFIG_BF60x)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG TIMER_RUN
-#endif
-/*
- * All others: 3 timers:
- */
-#define TIMER_GROUP1 0
-#if !defined(MAX_BLACKFIN_GPTIMERS)
-# define MAX_BLACKFIN_GPTIMERS 3
-# define TIMER0_GROUP_REG TIMER_ENABLE
-#endif
-
-#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
-#define BFIN_TIMER_OCTET(x) ((x) >> 3)
-
-/* used in masks for timer_enable() and timer_disable() */
-#define TIMER0bit 0x0001 /* 0001b */
-#define TIMER1bit 0x0002 /* 0010b */
-#define TIMER2bit 0x0004 /* 0100b */
-#define TIMER3bit 0x0008
-#define TIMER4bit 0x0010
-#define TIMER5bit 0x0020
-#define TIMER6bit 0x0040
-#define TIMER7bit 0x0080
-#define TIMER8bit 0x0100
-#define TIMER9bit 0x0200
-#define TIMER10bit 0x0400
-#define TIMER11bit 0x0800
-
-#define TIMER0_id 0
-#define TIMER1_id 1
-#define TIMER2_id 2
-#define TIMER3_id 3
-#define TIMER4_id 4
-#define TIMER5_id 5
-#define TIMER6_id 6
-#define TIMER7_id 7
-#define TIMER8_id 8
-#define TIMER9_id 9
-#define TIMER10_id 10
-#define TIMER11_id 11
-
-/* associated timers for ppi framesync: */
-
-#if defined(CONFIG_BF561)
-# define FS0_1_TIMER_ID TIMER8_id
-# define FS0_2_TIMER_ID TIMER9_id
-# define FS1_1_TIMER_ID TIMER10_id
-# define FS1_2_TIMER_ID TIMER11_id
-# define FS0_1_TIMER_BIT TIMER8bit
-# define FS0_2_TIMER_BIT TIMER9bit
-# define FS1_1_TIMER_BIT TIMER10bit
-# define FS1_2_TIMER_BIT TIMER11bit
-# undef FS1_TIMER_ID
-# undef FS2_TIMER_ID
-# undef FS1_TIMER_BIT
-# undef FS2_TIMER_BIT
-#else
-# define FS1_TIMER_ID TIMER0_id
-# define FS2_TIMER_ID TIMER1_id
-# define FS1_TIMER_BIT TIMER0bit
-# define FS2_TIMER_BIT TIMER1bit
-#endif
-
-#ifdef CONFIG_BF60x
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_EMU_RUN 0x8000
-#define TIMER_BPER_EN 0x4000
-#define TIMER_BWID_EN 0x2000
-#define TIMER_BDLY_EN 0x1000
-#define TIMER_OUT_DIS 0x0800
-#define TIMER_TIN_SEL 0x0400
-#define TIMER_CLK_SEL 0x0300
-#define TIMER_CLK_SCLK 0x0000
-#define TIMER_CLK_ALT_CLK0 0x0100
-#define TIMER_CLK_ALT_CLK1 0x0300
-#define TIMER_PULSE_HI 0x0080
-#define TIMER_SLAVE_TRIG 0x0040
-#define TIMER_IRQ_MODE 0x0030
-#define TIMER_IRQ_ACT_EDGE 0x0000
-#define TIMER_IRQ_DLY 0x0010
-#define TIMER_IRQ_WID_DLY 0x0020
-#define TIMER_IRQ_PER 0x0030
-#define TIMER_MODE 0x000f
-#define TIMER_MODE_WDOG_P 0x0008
-#define TIMER_MODE_WDOG_W 0x0009
-#define TIMER_MODE_PWM_CONT 0x000c
-#define TIMER_MODE_PWM 0x000d
-#define TIMER_MODE_WDTH 0x000a
-#define TIMER_MODE_WDTH_D 0x000b
-#define TIMER_MODE_EXT_CLK 0x000e
-#define TIMER_MODE_PININT 0x000f
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x0008
-#define TIMER_STATUS_TIMIL4 0x0010
-#define TIMER_STATUS_TIMIL5 0x0020
-#define TIMER_STATUS_TIMIL6 0x0040
-#define TIMER_STATUS_TIMIL7 0x0080
-
-#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0002
-#define TIMER_STATUS_TOVF2 0x0004
-#define TIMER_STATUS_TOVF3 0x0008
-#define TIMER_STATUS_TOVF4 0x0010
-#define TIMER_STATUS_TOVF5 0x0020
-#define TIMER_STATUS_TOVF6 0x0040
-#define TIMER_STATUS_TOVF7 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x0001
-#define TIMER_STATUS_TRUN1 0x0002
-#define TIMER_STATUS_TRUN2 0x0004
-#define TIMER_STATUS_TRUN3 0x0008
-#define TIMER_STATUS_TRUN4 0x0010
-#define TIMER_STATUS_TRUN5 0x0020
-#define TIMER_STATUS_TRUN6 0x0040
-#define TIMER_STATUS_TRUN7 0x0080
-
-#else
-
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_ERR 0xC000
-#define TIMER_ERR_OVFL 0x4000
-#define TIMER_ERR_PROG_PER 0x8000
-#define TIMER_ERR_PROG_PW 0xC000
-#define TIMER_EMU_RUN 0x0200
-#define TIMER_TOGGLE_HI 0x0100
-#define TIMER_CLK_SEL 0x0080
-#define TIMER_OUT_DIS 0x0040
-#define TIMER_TIN_SEL 0x0020
-#define TIMER_IRQ_ENA 0x0010
-#define TIMER_PERIOD_CNT 0x0008
-#define TIMER_PULSE_HI 0x0004
-#define TIMER_MODE 0x0003
-#define TIMER_MODE_PWM 0x0001
-#define TIMER_MODE_WDTH 0x0002
-#define TIMER_MODE_EXT_CLK 0x0003
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0 0x0001
-#define TIMER_STATUS_TIMIL1 0x0002
-#define TIMER_STATUS_TIMIL2 0x0004
-#define TIMER_STATUS_TIMIL3 0x00000008
-#define TIMER_STATUS_TIMIL4 0x00010000
-#define TIMER_STATUS_TIMIL5 0x00020000
-#define TIMER_STATUS_TIMIL6 0x00040000
-#define TIMER_STATUS_TIMIL7 0x00080000
-#define TIMER_STATUS_TIMIL8 0x0001
-#define TIMER_STATUS_TIMIL9 0x0002
-#define TIMER_STATUS_TIMIL10 0x0004
-#define TIMER_STATUS_TIMIL11 0x0008
-
-#define TIMER_STATUS_TOVF0 0x0010 /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1 0x0020
-#define TIMER_STATUS_TOVF2 0x0040
-#define TIMER_STATUS_TOVF3 0x00000080
-#define TIMER_STATUS_TOVF4 0x00100000
-#define TIMER_STATUS_TOVF5 0x00200000
-#define TIMER_STATUS_TOVF6 0x00400000
-#define TIMER_STATUS_TOVF7 0x00800000
-#define TIMER_STATUS_TOVF8 0x0010
-#define TIMER_STATUS_TOVF9 0x0020
-#define TIMER_STATUS_TOVF10 0x0040
-#define TIMER_STATUS_TOVF11 0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0 0x1000
-#define TIMER_STATUS_TRUN1 0x2000
-#define TIMER_STATUS_TRUN2 0x4000
-#define TIMER_STATUS_TRUN3 0x00008000
-#define TIMER_STATUS_TRUN4 0x10000000
-#define TIMER_STATUS_TRUN5 0x20000000
-#define TIMER_STATUS_TRUN6 0x40000000
-#define TIMER_STATUS_TRUN7 0x80000000
-#define TIMER_STATUS_TRUN 0xF000F000
-#define TIMER_STATUS_TRUN8 0x1000
-#define TIMER_STATUS_TRUN9 0x2000
-#define TIMER_STATUS_TRUN10 0x4000
-#define TIMER_STATUS_TRUN11 0x8000
-
-#endif
-
-/* The actual gptimer API */
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth(unsigned int timer_id);
-void set_gptimer_period(unsigned int timer_id, uint32_t period);
-uint32_t get_gptimer_period(unsigned int timer_id);
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
-uint32_t get_gptimer_delay(unsigned int timer_id);
-#endif
-uint32_t get_gptimer_count(unsigned int timer_id);
-int get_gptimer_intr(unsigned int timer_id);
-void clear_gptimer_intr(unsigned int timer_id);
-int get_gptimer_over(unsigned int timer_id);
-void clear_gptimer_over(unsigned int timer_id);
-void set_gptimer_config(unsigned int timer_id, uint16_t config);
-uint16_t get_gptimer_config(unsigned int timer_id);
-int get_gptimer_run(unsigned int timer_id);
-void set_gptimer_pulse_hi(unsigned int timer_id);
-void clear_gptimer_pulse_hi(unsigned int timer_id);
-void enable_gptimers(uint16_t mask);
-void disable_gptimers(uint16_t mask);
-void disable_gptimers_sync(uint16_t mask);
-uint16_t get_enabled_gptimers(void);
-uint32_t get_gptimer_status(unsigned int group);
-void set_gptimer_status(unsigned int group, uint32_t value);
-
-static inline void enable_gptimer(unsigned int timer_id)
-{
- enable_gptimers(1 << timer_id);
-}
-
-static inline void disable_gptimer(unsigned int timer_id)
-{
- disable_gptimers(1 << timer_id);
-}
-
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-
-/*
- * bfin timer registers layout
- */
-struct bfin_gptimer_regs {
- __BFP(config);
- u32 counter;
- u32 period;
- u32 width;
-#ifdef CONFIG_BF60x
- u32 delay;
-#endif
-};
-
-/*
- * bfin group timer registers layout
- */
-#ifndef CONFIG_BF60x
-struct bfin_gptimer_group_regs {
- __BFP(enable);
- __BFP(disable);
- u32 status;
-};
-#else
-struct bfin_gptimer_group_regs {
- __BFP(run);
- __BFP(enable);
- __BFP(disable);
- __BFP(stop_cfg);
- __BFP(stop_cfg_set);
- __BFP(stop_cfg_clr);
- __BFP(data_imsk);
- __BFP(stat_imsk);
- __BFP(tr_msk);
- __BFP(tr_ie);
- __BFP(data_ilat);
- __BFP(stat_ilat);
- __BFP(err_status);
- __BFP(bcast_per);
- __BFP(bcast_wid);
- __BFP(bcast_dly);
-
-};
-#endif
-
-#undef __BFP
-
-#endif
diff --git a/arch/blackfin/include/asm/hardirq.h b/arch/blackfin/include/asm/hardirq.h
deleted file mode 100644
index 58b54a6d5a16..000000000000
--- a/arch/blackfin/include/asm/hardirq.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_HARDIRQ_H
-#define __BFIN_HARDIRQ_H
-
-#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
-
-extern void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
-
-#include <asm-generic/hardirq.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
deleted file mode 100644
index 6abebe82d4e9..000000000000
--- a/arch/blackfin/include/asm/io.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_IO_H
-#define _BFIN_IO_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <asm/byteorder.h>
-#include <asm/def_LPBlackfin.h>
-
-#define __raw_readb bfin_read8
-#define __raw_readw bfin_read16
-#define __raw_readl bfin_read32
-#define __raw_writeb(val, addr) bfin_write8(addr, val)
-#define __raw_writew(val, addr) bfin_write16(addr, val)
-#define __raw_writel(val, addr) bfin_write32(addr, val)
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-#define outsb outsb
-#define outsw outsw
-#define outsl outsl
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-#define insb insb
-#define insw insw
-#define insl insl
-
-/**
- * I/O write barrier
- *
- * Ensure ordering of I/O space writes. This will make sure that writes
- * following the barrier will arrive after all previous writes.
- */
-#define mmiowb() do { SSYNC(); wmb(); } while (0)
-
-#include <asm-generic/io.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
deleted file mode 100644
index fe1160fbff91..000000000000
--- a/arch/blackfin/include/asm/ipipe.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe.h
- *
- * Copyright (C) 2002-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_H
-#define __ASM_BLACKFIN_IPIPE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <linux/cpumask.h>
-#include <linux/list.h>
-#include <linux/threads.h>
-#include <linux/irq.h>
-#include <linux/ipipe_percpu.h>
-#include <asm/ptrace.h>
-#include <asm/irq.h>
-#include <asm/bitops.h>
-#include <linux/atomic.h>
-#include <asm/traps.h>
-#include <asm/bitsperlong.h>
-
-#define IPIPE_ARCH_STRING "1.16-01"
-#define IPIPE_MAJOR_NUMBER 1
-#define IPIPE_MINOR_NUMBER 16
-#define IPIPE_PATCH_NUMBER 1
-
-#ifdef CONFIG_SMP
-#error "I-pipe/blackfin: SMP not implemented"
-#else /* !CONFIG_SMP */
-#define ipipe_processor_id() 0
-#endif /* CONFIG_SMP */
-
-#define prepare_arch_switch(next) \
-do { \
- ipipe_schedule_notify(current, next); \
- hard_local_irq_disable(); \
-} while (0)
-
-#define task_hijacked(p) \
- ({ \
- int __x__ = __ipipe_root_domain_p; \
- if (__x__) \
- hard_local_irq_enable(); \
- !__x__; \
- })
-
-struct ipipe_domain;
-
-struct ipipe_sysinfo {
- int sys_nr_cpus; /* Number of CPUs on board */
- int sys_hrtimer_irq; /* hrtimer device IRQ */
- u64 sys_hrtimer_freq; /* hrtimer device frequency */
- u64 sys_hrclock_freq; /* hrclock device frequency */
- u64 sys_cpu_freq; /* CPU frequency (Hz) */
-};
-
-#define ipipe_read_tsc(t) \
- ({ \
- unsigned long __cy2; \
- __asm__ __volatile__ ("1: %0 = CYCLES2\n" \
- "%1 = CYCLES\n" \
- "%2 = CYCLES2\n" \
- "CC = %2 == %0\n" \
- "if ! CC jump 1b\n" \
- : "=d,a" (((unsigned long *)&t)[1]), \
- "=d,a" (((unsigned long *)&t)[0]), \
- "=d,a" (__cy2) \
- : /*no input*/ : "CC"); \
- t; \
- })
-
-#define ipipe_cpu_freq() __ipipe_core_clock
-#define ipipe_tsc2ns(_t) (((unsigned long)(_t)) * __ipipe_freq_scale)
-#define ipipe_tsc2us(_t) (ipipe_tsc2ns(_t) / 1000 + 1)
-
-/* Private interface -- Internal use only */
-
-#define __ipipe_check_platform() do { } while (0)
-
-#define __ipipe_init_platform() do { } while (0)
-
-extern atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-extern unsigned long __ipipe_irq_lvmask;
-
-extern struct ipipe_domain ipipe_root;
-
-/* enable/disable_irqdesc _must_ be used in pairs. */
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
- unsigned irq);
-
-#define __ipipe_enable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_unmask(&desc->irq_data); \
- } while (0)
-
-#define __ipipe_disable_irq(irq) \
- do { \
- struct irq_desc *desc = irq_to_desc(irq); \
- struct irq_chip *chip = get_irq_desc_chip(desc); \
- chip->irq_mask(&desc->irq_data); \
- } while (0)
-
-static inline int __ipipe_check_tickdev(const char *devname)
-{
- return 1;
-}
-
-void __ipipe_enable_pipeline(void);
-
-#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
-
-void ___ipipe_sync_pipeline(void);
-
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
-
-int __ipipe_get_irq_priority(unsigned int irq);
-
-void __ipipe_serial_debug(const char *fmt, ...);
-
-asmlinkage void __ipipe_call_irqtail(unsigned long addr);
-
-DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-extern unsigned long __ipipe_core_clock;
-
-extern unsigned long __ipipe_freq_scale;
-
-extern unsigned long __ipipe_irq_tail_hook;
-
-static inline unsigned long __ipipe_ffnz(unsigned long ul)
-{
- return ffs(ul) - 1;
-}
-
-#define __ipipe_do_root_xirq(ipd, irq) \
- ((ipd)->irqs[irq].handler(irq, raw_cpu_ptr(&__ipipe_tick_regs)))
-
-#define __ipipe_run_irqtail(irq) /* Must be a macro */ \
- do { \
- unsigned long __pending; \
- CSYNC(); \
- __pending = bfin_read_IPEND(); \
- if (__pending & 0x8000) { \
- __pending &= ~0x8010; \
- if (__pending && (__pending & (__pending - 1)) == 0) \
- __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
- } \
- } while (0)
-
-#define __ipipe_syscall_watched_p(p, sc) \
- (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls)
-
-#ifdef CONFIG_BF561
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
-#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
-#elif defined(CONFIG_BF54x)
-#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
-#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
-#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
-#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
-#endif
-
-#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
-
-#else /* !CONFIG_IPIPE */
-
-#define task_hijacked(p) 0
-#define ipipe_trap_notify(t, r) 0
-#define __ipipe_root_tick_p(regs) 1
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
-#define IRQ_SYSTMR IRQ_CORETMR
-#define IRQ_PRIOTMR IRQ_CORETMR
-#else
-#define IRQ_SYSTMR IRQ_TIMER0
-#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
-#endif
-
-#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
-
-#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
deleted file mode 100644
index 84a4ffd36747..000000000000
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* -*- linux-c -*-
- * include/asm-blackfin/ipipe_base.h
- *
- * Copyright (C) 2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __ASM_BLACKFIN_IPIPE_BASE_H
-#define __ASM_BLACKFIN_IPIPE_BASE_H
-
-#ifdef CONFIG_IPIPE
-
-#include <asm/bitsperlong.h>
-#include <mach/irq.h>
-
-#define IPIPE_NR_XIRQS NR_IRQS
-
-/* Blackfin-specific, per-cpu pipeline status */
-#define IPIPE_SYNCDEFER_FLAG 15
-#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
-
- /* Blackfin traps -- i.e. exception vector numbers */
-#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
-/* Pseudo-vectors used for kernel events */
-#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS
-#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT)
-#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1)
-#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2)
-#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3)
-#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
-#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
-#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
-#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7)
-#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN
-#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
-
-#define IPIPE_TIMER_IRQ IRQ_CORETMR
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#ifndef __ASSEMBLY__
-
-extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
-
-void __ipipe_stall_root(void);
-
-unsigned long __ipipe_test_and_stall_root(void);
-
-unsigned long __ipipe_test_root(void);
-
-void __ipipe_lock_root(void);
-
-void __ipipe_unlock_root(void);
-
-#endif /* !__ASSEMBLY__ */
-
-#define __IPIPE_FEATURE_SYSINFO_V2 1
-
-#endif /* CONFIG_IPIPE */
-
-#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
deleted file mode 100644
index 89de539ed010..000000000000
--- a/arch/blackfin/include/asm/irq.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 HuTao
- * 2002 Arcturus Networks Inc. (www.arcturusnetworks.com
- * Ted Ma <mated@sympatico.ca>
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_IRQ_H_
-#define _BFIN_IRQ_H_
-
-#include <linux/irqflags.h>
-
-/* IRQs that may be used by external irq_chip controllers */
-#define NR_SPARE_IRQS 32
-
-#include <mach/anomaly.h>
-
-/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
-#include <mach/irq.h>
-
-#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-#else
-# define NOP_PAD_ANOMALY_05000244
-#endif
-
-#define idle_with_irq_disabled() \
- __asm__ __volatile__( \
- NOP_PAD_ANOMALY_05000244 \
- ".align 8;" \
- "sti %0;" \
- "idle;" \
- : \
- : "d" (bfin_irq_flags) \
- )
-
-#include <asm-generic/irq.h>
-
-#endif /* _BFIN_IRQ_H_ */
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
deleted file mode 100644
index d2f90c72378e..000000000000
--- a/arch/blackfin/include/asm/irq_handler.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _IRQ_HANDLER_H
-#define _IRQ_HANDLER_H
-
-#include <linux/types.h>
-#include <linux/linkage.h>
-#include <mach/irq.h>
-
-/* init functions only */
-extern int init_arch_irq(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-#ifdef init_mach_irq
-extern void init_mach_irq(void);
-#else
-# define init_mach_irq()
-#endif
-
-/* BASE LEVEL interrupt handler routines */
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_evt14(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-asmlinkage void init_exception_buff(void);
-asmlinkage void trap_c(struct pt_regs *fp);
-asmlinkage void ex_replaceable(void);
-asmlinkage void early_trap(void);
-
-extern void *ex_table[];
-extern void return_from_exception(void);
-
-extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
-extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
-
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-struct irq_data;
-extern void bfin_handle_irq(unsigned irq);
-extern void bfin_ack_noop(struct irq_data *);
-extern void bfin_internal_mask_irq(unsigned int irq);
-extern void bfin_internal_unmask_irq(unsigned int irq);
-
-struct irq_desc;
-extern void bfin_demux_mac_status_irq(struct irq_desc *);
-extern void bfin_demux_gpio_irq(struct irq_desc *);
-
-#endif
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
deleted file mode 100644
index 07aff230a812..000000000000
--- a/arch/blackfin/include/asm/irqflags.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * interface to Blackfin CEC
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_IRQFLAGS_H__
-#define __ASM_BFIN_IRQFLAGS_H__
-
-#include <mach/blackfin.h>
-
-#ifdef CONFIG_SMP
-# include <asm/pda.h>
-# include <asm/processor.h>
-# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
-#else
-extern unsigned long bfin_irq_flags;
-#endif
-
-static inline notrace void bfin_sti(unsigned long flags)
-{
- asm volatile("sti %0;" : : "d" (flags));
-}
-
-static inline notrace unsigned long bfin_cli(void)
-{
- unsigned long flags;
- asm volatile("cli %0;" : "=d" (flags));
- return flags;
-}
-
-#ifdef CONFIG_DEBUG_HWERR
-# define bfin_no_irqs 0x3f
-#else
-# define bfin_no_irqs 0x1f
-#endif
-
-/*****************************************************************************/
-/*
- * Hard, untraced CPU interrupt flag manipulation and access.
- */
-static inline notrace void __hard_local_irq_disable(void)
-{
- bfin_cli();
-}
-
-static inline notrace void __hard_local_irq_enable(void)
-{
- bfin_sti(bfin_irq_flags);
-}
-
-static inline notrace unsigned long hard_local_save_flags(void)
-{
- return bfin_read_IMASK();
-}
-
-static inline notrace unsigned long __hard_local_irq_save(void)
-{
- unsigned long flags;
- flags = bfin_cli();
-#ifdef CONFIG_DEBUG_HWERR
- bfin_sti(0x3f);
-#endif
- return flags;
-}
-
-static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
-{
-#ifdef CONFIG_BF60x
- return (flags & IMASK_IVG11) == 0;
-#else
- return (flags & ~0x3f) == 0;
-#endif
-}
-
-static inline notrace int hard_irqs_disabled(void)
-{
- unsigned long flags = hard_local_save_flags();
- return hard_irqs_disabled_flags(flags);
-}
-
-static inline notrace void __hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags))
- __hard_local_irq_enable();
-}
-
-/*****************************************************************************/
-/*
- * Interrupt pipe handling.
- */
-#ifdef CONFIG_IPIPE
-
-#include <linux/compiler.h>
-#include <linux/ipipe_trace.h>
-/*
- * Way too many inter-deps between low-level headers in this port, so
- * we redeclare the required bits we cannot pick from
- * <asm/ipipe_base.h> to prevent circular dependencies.
- */
-void __ipipe_stall_root(void);
-void __ipipe_unstall_root(void);
-unsigned long __ipipe_test_root(void);
-unsigned long __ipipe_test_and_stall_root(void);
-void __ipipe_restore_root(unsigned long flags);
-
-#ifdef CONFIG_IPIPE_DEBUG_CONTEXT
-struct ipipe_domain;
-extern struct ipipe_domain ipipe_root;
-void ipipe_check_context(struct ipipe_domain *ipd);
-#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root)
-#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-#define __check_irqop_context(ipd) do { } while (0)
-#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */
-
-/*
- * Interrupt pipe interface to linux/irqflags.h.
- */
-static inline notrace void arch_local_irq_disable(void)
-{
- __check_irqop_context();
- __ipipe_stall_root();
- barrier();
-}
-
-static inline notrace void arch_local_irq_enable(void)
-{
- barrier();
- __check_irqop_context();
- __ipipe_unstall_root();
-}
-
-static inline notrace unsigned long arch_local_save_flags(void)
-{
- return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags;
-}
-
-static inline notrace int arch_irqs_disabled_flags(unsigned long flags)
-{
- return flags == bfin_no_irqs;
-}
-
-static inline notrace unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
- __check_irqop_context();
- flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
- barrier();
-
- return flags;
-}
-
-static inline notrace void arch_local_irq_restore(unsigned long flags)
-{
- __check_irqop_context();
- __ipipe_restore_root(flags == bfin_no_irqs);
-}
-
-static inline notrace unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
-{
- /*
- * Merge virtual and real interrupt mask bits into a single
- * 32bit word.
- */
- return (real & ~(1 << 31)) | ((virt != 0) << 31);
-}
-
-static inline notrace int arch_demangle_irq_bits(unsigned long *x)
-{
- int virt = (*x & (1 << 31)) != 0;
- *x &= ~(1L << 31);
- return virt;
-}
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#ifdef CONFIG_IPIPE_TRACE_IRQSOFF
-static inline notrace void hard_local_irq_disable(void)
-{
- if (!hard_irqs_disabled()) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000000);
- }
-}
-
-static inline notrace void hard_local_irq_enable(void)
-{
- if (hard_irqs_disabled()) {
- ipipe_trace_end(0x80000000);
- __hard_local_irq_enable();
- }
-}
-
-static inline notrace unsigned long hard_local_irq_save(void)
-{
- unsigned long flags = hard_local_save_flags();
- if (!hard_irqs_disabled_flags(flags)) {
- __hard_local_irq_disable();
- ipipe_trace_begin(0x80000001);
- }
- return flags;
-}
-
-static inline notrace void hard_local_irq_restore(unsigned long flags)
-{
- if (!hard_irqs_disabled_flags(flags)) {
- ipipe_trace_end(0x80000001);
- __hard_local_irq_enable();
- }
-}
-
-#else /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-# define hard_local_irq_disable() __hard_local_irq_disable()
-# define hard_local_irq_enable() __hard_local_irq_enable()
-# define hard_local_irq_save() __hard_local_irq_save()
-# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
-
-#define hard_local_irq_save_cond() hard_local_irq_save()
-#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags)
-
-#else /* !CONFIG_IPIPE */
-
-/*
- * Direct interface to linux/irqflags.h.
- */
-#define arch_local_save_flags() hard_local_save_flags()
-#define arch_local_irq_save() __hard_local_irq_save()
-#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define arch_local_irq_enable() __hard_local_irq_enable()
-#define arch_local_irq_disable() __hard_local_irq_disable()
-#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags)
-#define arch_irqs_disabled() hard_irqs_disabled()
-
-/*
- * Interface to various arch routines that may be traced.
- */
-#define hard_local_irq_save() __hard_local_irq_save()
-#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
-#define hard_local_irq_enable() __hard_local_irq_enable()
-#define hard_local_irq_disable() __hard_local_irq_disable()
-#define hard_local_irq_save_cond() hard_local_save_flags()
-#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0)
-
-#endif /* !CONFIG_IPIPE */
-
-#ifdef CONFIG_SMP
-#define hard_local_irq_save_smp() hard_local_irq_save()
-#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags)
-#else
-#define hard_local_irq_save_smp() hard_local_save_flags()
-#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0)
-#endif
-
-/*
- * Remap the arch-neutral IRQ state manipulation macros to the
- * blackfin-specific hard_local_irq_* API.
- */
-#define local_irq_save_hw(flags) \
- do { \
- (flags) = hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw(flags) \
- do { \
- hard_local_irq_restore(flags); \
- } while (0)
-#define local_irq_disable_hw() \
- do { \
- hard_local_irq_disable(); \
- } while (0)
-#define local_irq_enable_hw() \
- do { \
- hard_local_irq_enable(); \
- } while (0)
-#define local_irq_save_hw_notrace(flags) \
- do { \
- (flags) = __hard_local_irq_save(); \
- } while (0)
-#define local_irq_restore_hw_notrace(flags) \
- do { \
- __hard_local_irq_restore(flags); \
- } while (0)
-
-#define irqs_disabled_hw() hard_irqs_disabled()
-
-#endif
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
deleted file mode 100644
index 2703ddeeb5db..000000000000
--- a/arch/blackfin/include/asm/kgdb.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* Blackfin KGDB header
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-#include <linux/ptrace.h>
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
- * At least NUMREGBYTES*2 are needed for register packets.
- * Longer buffer is needed to list all threads.
- */
-#define BUFMAX 2048
-
-/*
- * Note that this register image is different from
- * the register image that Linux produces at interrupt time.
- *
- * Linux's register image is defined by struct pt_regs in ptrace.h.
- */
-enum regnames {
- /* Core Registers */
- BFIN_R0 = 0,
- BFIN_R1,
- BFIN_R2,
- BFIN_R3,
- BFIN_R4,
- BFIN_R5,
- BFIN_R6,
- BFIN_R7,
- BFIN_P0,
- BFIN_P1,
- BFIN_P2,
- BFIN_P3,
- BFIN_P4,
- BFIN_P5,
- BFIN_SP,
- BFIN_FP,
- BFIN_I0,
- BFIN_I1,
- BFIN_I2,
- BFIN_I3,
- BFIN_M0,
- BFIN_M1,
- BFIN_M2,
- BFIN_M3,
- BFIN_B0,
- BFIN_B1,
- BFIN_B2,
- BFIN_B3,
- BFIN_L0,
- BFIN_L1,
- BFIN_L2,
- BFIN_L3,
- BFIN_A0_DOT_X,
- BFIN_A0_DOT_W,
- BFIN_A1_DOT_X,
- BFIN_A1_DOT_W,
- BFIN_ASTAT,
- BFIN_RETS,
- BFIN_LC0,
- BFIN_LT0,
- BFIN_LB0,
- BFIN_LC1,
- BFIN_LT1,
- BFIN_LB1,
- BFIN_CYCLES,
- BFIN_CYCLES2,
- BFIN_USP,
- BFIN_SEQSTAT,
- BFIN_SYSCFG,
- BFIN_RETI,
- BFIN_RETX,
- BFIN_RETN,
- BFIN_RETE,
-
- /* Pseudo Registers */
- BFIN_PC,
- BFIN_CC,
- BFIN_EXTRA1, /* Address of .text section. */
- BFIN_EXTRA2, /* Address of .data section. */
- BFIN_EXTRA3, /* Address of .bss section. */
- BFIN_FDPIC_EXEC,
- BFIN_FDPIC_INTERP,
-
- /* MMRs */
- BFIN_IPEND,
-
- /* LAST ENTRY SHOULD NOT BE CHANGED. */
- BFIN_NUM_REGS /* The number of all registers. */
-};
-
-/* Number of bytes of registers. */
-#define NUMREGBYTES BFIN_NUM_REGS*4
-
-static inline void arch_kgdb_breakpoint(void)
-{
- asm("EXCPT 2;");
-}
-#define BREAK_INSTR_SIZE 2
-#ifdef CONFIG_SMP
-# define CACHE_FLUSH_IS_SAFE 0
-#else
-# define CACHE_FLUSH_IS_SAFE 1
-#endif
-#define GDB_ADJUSTS_BREAK_OFFSET
-#define GDB_SKIP_HW_WATCH_TEST
-#define HW_INST_WATCHPOINT_NUM 6
-#define HW_WATCHPOINT_NUM 8
-#define TYPE_INST_WATCHPOINT 0
-#define TYPE_DATA_WATCHPOINT 1
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR 0x1
-#define WPIREN01 0x2
-#define WPIRINV01 0x4
-#define WPIAEN0 0x8
-#define WPIAEN1 0x10
-#define WPICNTEN0 0x20
-#define WPICNTEN1 0x40
-#define EMUSW0 0x80
-#define EMUSW1 0x100
-#define WPIREN23 0x200
-#define WPIRINV23 0x400
-#define WPIAEN2 0x800
-#define WPIAEN3 0x1000
-#define WPICNTEN2 0x2000
-#define WPICNTEN3 0x4000
-#define EMUSW2 0x8000
-#define EMUSW3 0x10000
-#define WPIREN45 0x20000
-#define WPIRINV45 0x40000
-#define WPIAEN4 0x80000
-#define WPIAEN5 0x100000
-#define WPICNTEN4 0x200000
-#define WPICNTEN5 0x400000
-#define EMUSW4 0x800000
-#define EMUSW5 0x1000000
-#define WPAND 0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01 0x1
-#define WPDRINV01 0x2
-#define WPDAEN0 0x4
-#define WPDAEN1 0x8
-#define WPDCNTEN0 0x10
-#define WPDCNTEN1 0x20
-
-#define WPDSRC0 0xc0
-#define WPDACC0_OFFSET 8
-#define WPDSRC1 0xc00
-#define WPDACC1_OFFSET 12
-
-/* Watchpoint status register bits mask */
-#define STATIA0 0x1
-#define STATIA1 0x2
-#define STATIA2 0x4
-#define STATIA3 0x8
-#define STATIA4 0x10
-#define STATIA5 0x20
-#define STATDA0 0x40
-#define STATDA1 0x80
-
-#endif
diff --git a/arch/blackfin/include/asm/l1layout.h b/arch/blackfin/include/asm/l1layout.h
deleted file mode 100644
index c87e68647a2b..000000000000
--- a/arch/blackfin/include/asm/l1layout.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Defines a layout of L1 scratchpad memory that userspace can rely on.
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _L1LAYOUT_H_
-#define _L1LAYOUT_H_
-
-#include <asm/blackfin.h>
-
-#ifndef CONFIG_SMP
-#ifndef __ASSEMBLY__
-
-/* Data that is "mapped" into the process VM at the start of the L1 scratch
- memory, so that each process can access it at a fixed address. Used for
- stack checking. */
-struct l1_scratch_task_info
-{
- /* Points to the start of the stack. */
- void *stack_start;
- /* Not updated by the kernel; a user process can modify this to
- keep track of the lowest address of the stack pointer during its
- runtime. */
- void *lowest_sp;
-};
-
-/* A pointer to the structure in memory. */
-#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)\
- get_l1_scratch_start())
-
-#endif
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
deleted file mode 100644
index f7d6d47a048d..000000000000
--- a/arch/blackfin/include/asm/linkage.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
deleted file mode 100644
index c865b33eeb68..000000000000
--- a/arch/blackfin/include/asm/mem_init.h
+++ /dev/null
@@ -1,500 +0,0 @@
-/*
- * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MEM_INIT_H__
-#define __MEM_INIT_H__
-
-#if defined(EBIU_SDGCTL)
-#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_1
-#define SDRAM_tRAS_num 1
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-/*
- * The BF526-EZ-Board changed SDRAM chips between revisions,
- * so we use below timings to accommodate both.
- */
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_8
-#define SDRAM_tRAS_num 8
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_7
-#define SDRAM_tRAS_num 7
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_6
-#define SDRAM_tRAS_num 6
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_5
-#define SDRAM_tRAS_num 5
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_2
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_4
-#define SDRAM_tRAS_num 4
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP TRP_2
-#define SDRAM_tRP_num 2
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_3
-#define SDRAM_tRAS_num 3
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP TRP_1
-#define SDRAM_tRP_num 1
-#define SDRAM_tRAS TRAS_2
-#define SDRAM_tRAS_num 2
-#define SDRAM_tRCD TRCD_1
-#define SDRAM_tWR TWR_2
-#endif
-#endif
-
-#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
- defined(CONFIG_MEM_MT48LC8M32B2B5_7)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
- defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
- defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
- defined(CONFIG_MEM_MT48LC32M8A2_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_3
-#endif
-
-#if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
- /*SDRAM INFORMATION: */
-#define SDRAM_Tref 64 /* Refresh period in milliseconds */
-#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
-#define SDRAM_CL CL_2
-#endif
-
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-#else
-#define mem_SDRRC CONFIG_MEM_SDRRC
-#define mem_SDGCTL CONFIG_MEM_SDGCTL
-#endif
-#endif
-
-
-#if defined(EBIU_DDRCTL0)
-#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
-#define DDR_CLK_HZ(x) (1000*1000*1000/x)
-
-#if defined(CONFIG_MEM_MT46V32M16_6T)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(1)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if defined(CONFIG_MEM_MT46V32M16_5B)
-#define DDR_SIZE DEVSZ_512
-#define DDR_WIDTH DEVWD_16
-#define DDR_MAX_tCK 13
-
-#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
-#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
-#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR DDR_TWTR(2)
-#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
-#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
-# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
-#elif(CONFIG_SCLK_HZ <= 133333333)
-# define DDR_CL CL_2
-#else
-# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
-#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
-#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
- | DDR_tMRD | DDR_tWR | DDR_tRCD)
-#define mem_DDRCTL2 DDR_CL
-#else
-#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
-#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
-#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
-#endif
-#endif
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF 1
-#else
-#define CLKIN_HALF 0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS 1
-#else
-#define PLL_BYPASS 0
-#endif
-
-#ifdef CONFIG_BF60x
-
-/* DMC status bits */
-#define IDLE 0x1
-#define MEMINITDONE 0x4
-#define SRACK 0x8
-#define PDACK 0x10
-#define DPDACK 0x20
-#define DLLCALDONE 0x2000
-#define PENDREF 0xF0000
-#define PHYRDPHASE 0xF00000
-#define PHYRDPHASE_OFFSET 20
-
-/* DMC control bits */
-#define LPDDR 0x2
-#define INIT 0x4
-#define SRREQ 0x8
-#define PDREQ 0x10
-#define DPDREQ 0x20
-#define PREC 0x40
-#define ADDRMODE 0x100
-#define RDTOWR 0xE00
-#define PPREF 0x1000
-#define DLLCAL 0x2000
-
-/* DMC DLL control bits */
-#define DLLCALRDCNT 0xFF
-#define DATACYC 0xF00
-#define DATACYC_OFFSET 8
-
-/* CGU Divisor bits */
-#define CSEL_OFFSET 0
-#define S0SEL_OFFSET 5
-#define SYSSEL_OFFSET 8
-#define S1SEL_OFFSET 13
-#define DSEL_OFFSET 16
-#define OSEL_OFFSET 22
-#define ALGN 0x20000000
-#define UPDT 0x40000000
-#define LOCK 0x80000000
-
-/* CGU Status bits */
-#define PLLEN 0x1
-#define PLLBP 0x2
-#define PLOCK 0x4
-#define CLKSALGN 0x8
-
-/* CGU Control bits */
-#define MSEL_MASK 0x7F00
-#define DF_MASK 0x1
-
-struct ddr_config {
- u32 ddr_clk;
- u32 dmc_ddrctl;
- u32 dmc_effctl;
- u32 dmc_ddrcfg;
- u32 dmc_ddrtr0;
- u32 dmc_ddrtr1;
- u32 dmc_ddrtr2;
- u32 dmc_ddrmr;
- u32 dmc_ddrmr1;
-};
-
-#if defined(CONFIG_MEM_MT47H64M16)
-static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
- [0] = {
- .ddr_clk = 125,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20705212,
- .dmc_ddrtr1 = 0x201003CF,
- .dmc_ddrtr2 = 0x00320107,
- .dmc_ddrmr = 0x00000422,
- .dmc_ddrmr1 = 0x4,
- },
- [1] = {
- .ddr_clk = 133,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20806313,
- .dmc_ddrtr1 = 0x2013040D,
- .dmc_ddrtr2 = 0x00320108,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [2] = {
- .ddr_clk = 150,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x20160492,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [3] = {
- .ddr_clk = 166,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20A07323,
- .dmc_ddrtr1 = 0x2016050E,
- .dmc_ddrtr2 = 0x00320209,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [4] = {
- .ddr_clk = 200,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20a07323,
- .dmc_ddrtr1 = 0x2016050f,
- .dmc_ddrtr2 = 0x00320509,
- .dmc_ddrmr = 0x00000632,
- .dmc_ddrmr1 = 0x4,
- },
- [5] = {
- .ddr_clk = 225,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x302006DB,
- .dmc_ddrtr2 = 0x0032020D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
- [6] = {
- .ddr_clk = 250,
- .dmc_ddrctl = 0x00000904,
- .dmc_effctl = 0x004400C0,
- .dmc_ddrcfg = 0x00000422,
- .dmc_ddrtr0 = 0x20E0A424,
- .dmc_ddrtr1 = 0x3020079E,
- .dmc_ddrtr2 = 0x0032050D,
- .dmc_ddrmr = 0x00000842,
- .dmc_ddrmr1 = 0x4,
- },
-};
-#endif
-
-static inline void dmc_enter_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
- while (!(bfin_read_DMC0_STAT() & SRACK))
- continue;
- }
-}
-
-static inline void dmc_exit_self_refresh(void)
-{
- if (bfin_read_DMC0_STAT() & MEMINITDONE) {
- bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
- while (bfin_read_DMC0_STAT() & SRACK)
- continue;
- }
-}
-
-static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
-{
- dmc_enter_self_refresh();
-
- /* Don't set the same value of MSEL and DF to CGU_CTL */
- if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
- != cgu_ctl) {
- bfin_write32(CGU0_DIV, cgu_div);
- bfin_write32(CGU0_CTL, cgu_ctl);
- while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
- !(bfin_read32(CGU0_STAT) & PLOCK))
- continue;
- }
-
- bfin_write32(CGU0_DIV, cgu_div | UPDT);
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-
- dmc_exit_self_refresh();
-}
-
-static inline void init_dmc(u32 dmc_clk)
-{
- int i, dlldatacycle, dll_ctl;
-
- for (i = 0; i < 7; i++) {
- if (ddr_config_table[i].ddr_clk == dmc_clk) {
- bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
- bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
- bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
- bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
- bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
- bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
- bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
- bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
- break;
- }
- }
-
- while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
- continue;
-
- dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
- dll_ctl = bfin_read_DMC0_DLLCTL();
- dll_ctl &= ~DATACYC;
- bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
-
- while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
- continue;
-}
-#endif
-
-#endif /*__MEM_INIT_H__*/
-
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
deleted file mode 100644
index 5e21627c9ba2..000000000000
--- a/arch/blackfin/include/asm/mem_map.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MEM_MAP_H__
-#define __BFIN_MEM_MAP_H__
-
-#include <mach/mem_map.h>
-
-/* Every Blackfin so far has MMRs like this */
-#ifndef COREMMR_BASE
-# define COREMMR_BASE 0xFFE00000
-#endif
-#ifndef SYSMMR_BASE
-# define SYSMMR_BASE 0xFFC00000
-#endif
-
-/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
-#ifndef L1_SCRATCH_START
-# define L1_SCRATCH_START 0xFFB00000
-# define L1_SCRATCH_LENGTH 0x1000
-#endif
-
-/* Most parts lack on-chip L2 SRAM */
-#ifndef L2_START
-# define L2_START 0
-# define L2_LENGTH 0
-#endif
-
-/* Most parts lack on-chip L1 ROM */
-#ifndef L1_ROM_START
-# define L1_ROM_START 0
-# define L1_ROM_LENGTH 0
-#endif
-
-/* Allow wonky SMP ports to override this */
-#ifndef GET_PDA_SAFE
-# define GET_PDA_SAFE(preg) \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda;
-# define GET_PDA(preg, dreg) GET_PDA_SAFE(preg)
-
-# ifndef __ASSEMBLY__
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return L1_DATA_B_START;
-}
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(0);
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(0);
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(0);
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(0);
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* !GET_PDA_SAFE */
-
-#endif
diff --git a/arch/blackfin/include/asm/mmu.h b/arch/blackfin/include/asm/mmu.h
deleted file mode 100644
index 26f6b70b11e2..000000000000
--- a/arch/blackfin/include/asm/mmu.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2002 David McCullough <davidm@snapgear.com>
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef __MMU_H
-#define __MMU_H
-
-struct sram_list_struct {
- struct sram_list_struct *next;
- void *addr;
- size_t length;
-};
-
-typedef struct {
- unsigned long end_brk;
- unsigned long stack_start;
-
- /* Points to the location in SDRAM where the L1 stack is normally
- saved, or NULL if the stack is always in SDRAM. */
- void *l1_stack_save;
-
- struct sram_list_struct *sram_list;
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
- unsigned long exec_fdpic_loadmap;
- unsigned long interp_fdpic_loadmap;
-#endif
-#ifdef CONFIG_MPU
- unsigned long *page_rwx_mask;
-#endif
-} mm_context_t;
-
-#endif
diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h
deleted file mode 100644
index 0ce6de873b27..000000000000
--- a/arch/blackfin/include/asm/mmu_context.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_MMU_CONTEXT_H__
-#define __BLACKFIN_MMU_CONTEXT_H__
-
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/cplbinit.h>
-#include <asm/sections.h>
-
-/* Note: L1 stacks are CPU-private things, so we bluntly disable this
- feature in SMP mode, and use the per-CPU scratch SRAM bank only to
- store the PDA instead. */
-
-extern void *current_l1_stack_save;
-extern int nr_l1stack_tasks;
-extern void *l1_stack_base;
-extern unsigned long l1_stack_len;
-
-extern int l1sram_free(const void*);
-extern void *l1sram_alloc_max(void*);
-
-static inline void free_l1stack(void)
-{
- nr_l1stack_tasks--;
- if (nr_l1stack_tasks == 0) {
- l1sram_free(l1_stack_base);
- l1_stack_base = NULL;
- l1_stack_len = 0;
- }
-}
-
-static inline unsigned long
-alloc_l1stack(unsigned long length, unsigned long *stack_base)
-{
- if (nr_l1stack_tasks == 0) {
- l1_stack_base = l1sram_alloc_max(&l1_stack_len);
- if (!l1_stack_base)
- return 0;
- }
-
- if (l1_stack_len < length) {
- if (nr_l1stack_tasks == 0)
- l1sram_free(l1_stack_base);
- return 0;
- }
- *stack_base = (unsigned long)l1_stack_base;
- nr_l1stack_tasks++;
- return l1_stack_len;
-}
-
-static inline int
-activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
-{
- if (current_l1_stack_save)
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
- return 1;
-}
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-#define activate_mm(prev, next) switch_mm(prev, next, NULL)
-
-static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
- struct task_struct *tsk)
-{
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
- if (prev_mm == next_mm)
- return;
-#ifdef CONFIG_MPU
- if (prev_mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(next_mm->context.page_rwx_mask, cpu);
- }
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- /* L1 stack switching. */
- if (!next_mm->context.l1_stack_save)
- return;
- if (next_mm->context.l1_stack_save == current_l1_stack_save)
- return;
- if (current_l1_stack_save) {
- memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
- }
- current_l1_stack_save = next_mm->context.l1_stack_save;
- memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-#endif
-}
-
-#ifdef CONFIG_IPIPE
-#define lock_mm_switch(flags) flags = hard_local_irq_save_cond()
-#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags)
-#else
-#define lock_mm_switch(flags) do { (void)(flags); } while (0)
-#define unlock_mm_switch(flags) do { (void)(flags); } while (0)
-#endif /* CONFIG_IPIPE */
-
-#ifdef CONFIG_MPU
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- unsigned long flags;
- lock_mm_switch(flags);
- __switch_mm(prev, next, tsk);
- unlock_mm_switch(flags);
-}
-
-static inline void protect_page(struct mm_struct *mm, unsigned long addr,
- unsigned long flags)
-{
- unsigned long *mask = mm->context.page_rwx_mask;
- unsigned long page;
- unsigned long idx;
- unsigned long bit;
-
- if (unlikely(addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> 12;
- else
- page = addr >> 12;
- idx = page >> 5;
- bit = 1 << (page & 31);
-
- if (flags & VM_READ)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_WRITE)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
- mask += page_mask_nelts;
- if (flags & VM_EXEC)
- mask[idx] |= bit;
- else
- mask[idx] &= ~bit;
-}
-
-static inline void update_protections(struct mm_struct *mm)
-{
- unsigned int cpu = smp_processor_id();
- if (mm->context.page_rwx_mask == current_rwx_mask[cpu]) {
- flush_switched_cplbs(cpu);
- set_mask_dcplbs(mm->context.page_rwx_mask, cpu);
- }
-}
-#else /* !CONFIG_MPU */
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- __switch_mm(prev, next, tsk);
-}
-#endif
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/* Called when creating a new context during fork() or execve(). */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-#ifdef CONFIG_MPU
- unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
- mm->context.page_rwx_mask = (unsigned long *)p;
- memset(mm->context.page_rwx_mask, 0,
- page_mask_nelts * 3 * sizeof(long));
-#endif
- return 0;
-}
-
-static inline void destroy_context(struct mm_struct *mm)
-{
- struct sram_list_struct *tmp;
-#ifdef CONFIG_MPU
- unsigned int cpu = smp_processor_id();
-#endif
-
-#ifdef CONFIG_APP_STACK_L1
- if (current_l1_stack_save == mm->context.l1_stack_save)
- current_l1_stack_save = 0;
- if (mm->context.l1_stack_save)
- free_l1stack();
-#endif
-
- while ((tmp = mm->context.sram_list)) {
- mm->context.sram_list = tmp->next;
- sram_free(tmp->addr);
- kfree(tmp);
- }
-#ifdef CONFIG_MPU
- if (current_rwx_mask[cpu] == mm->context.page_rwx_mask)
- current_rwx_mask[cpu] = NULL;
- free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
-#endif
-}
-
-#define ipipe_mm_switch_protect(flags) \
- flags = hard_local_irq_save_cond()
-
-#define ipipe_mm_switch_unprotect(flags) \
- hard_local_irq_restore_cond(flags)
-
-#endif
diff --git a/arch/blackfin/include/asm/module.h b/arch/blackfin/include/asm/module.h
deleted file mode 100644
index 231a149b3f77..000000000000
--- a/arch/blackfin/include/asm/module.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BFIN_MODULE_H
-#define _ASM_BFIN_MODULE_H
-
-#include <asm-generic/module.h>
-
-struct mod_arch_specific {
- Elf_Shdr *text_l1;
- Elf_Shdr *data_a_l1;
- Elf_Shdr *bss_a_l1;
- Elf_Shdr *data_b_l1;
- Elf_Shdr *bss_b_l1;
- Elf_Shdr *text_l2;
- Elf_Shdr *data_l2;
- Elf_Shdr *bss_l2;
-};
-#endif /* _ASM_BFIN_MODULE_H */
diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h
deleted file mode 100644
index 256c50d8d465..000000000000
--- a/arch/blackfin/include/asm/nand.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * BF5XX - NAND flash controller platform_device info
- *
- * Copyright 2007-2008 Analog Devices, Inc.
- *
- * Licensed under the GPL-2
- */
-
-/* struct bf5xx_nand_platform
- *
- * define a interface between platform board specific code and
- * bf54x NFC driver.
- *
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * partitions = mtd partition list
- */
-
-#define NFC_PG_SIZE_OFFSET 9
-
-#define NFC_NWIDTH_8 0
-#define NFC_NWIDTH_16 1
-#define NFC_NWIDTH_OFFSET 8
-
-#define NFC_RDDLY_OFFSET 4
-#define NFC_WRDLY_OFFSET 0
-
-#define NFC_STAT_NBUSY 1
-
-struct bf5xx_nand_platform {
- /* NAND chip information */
- unsigned short data_width;
-
- /* RD/WR strobe delay timing information, all times in SCLK cycles */
- unsigned short rd_dly;
- unsigned short wr_dly;
-
- /* NAND MTD partition information */
- int nr_partitions;
- struct mtd_partition *partitions;
-};
diff --git a/arch/blackfin/include/asm/nmi.h b/arch/blackfin/include/asm/nmi.h
deleted file mode 100644
index 107d23705f46..000000000000
--- a/arch/blackfin/include/asm/nmi.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_NMI_H_
-#define _BFIN_NMI_H_
-
-#include <linux/nmi.h>
-
-extern void arch_touch_nmi_watchdog(void);
-
-#endif
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
deleted file mode 100644
index b93474d5be75..000000000000
--- a/arch/blackfin/include/asm/page.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
-#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | \
- ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/page.h>
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/page_offset.h b/arch/blackfin/include/asm/page_offset.h
deleted file mode 100644
index d06a89b89d20..000000000000
--- a/arch/blackfin/include/asm/page_offset.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * This handles the memory map
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifdef CONFIG_BLACKFIN
-#define PAGE_OFFSET_RAW 0x00000000
-#endif
diff --git a/arch/blackfin/include/asm/pci.h b/arch/blackfin/include/asm/pci.h
deleted file mode 100644
index e6458ddbaf7e..000000000000
--- a/arch/blackfin/include/asm/pci.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Changed from asm-m68k version, Lineo Inc. May 2001 */
-
-#ifndef _ASM_BFIN_PCI_H
-#define _ASM_BFIN_PCI_H
-
-#include <linux/scatterlist.h>
-#include <asm-generic/pci.h>
-
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#endif /* _ASM_BFIN_PCI_H */
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
deleted file mode 100644
index 68d6f6618f2a..000000000000
--- a/arch/blackfin/include/asm/pda.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_PDA_H
-#define _ASM_BLACKFIN_PDA_H
-
-#include <mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-struct blackfin_pda { /* Per-processor Data Area */
-#ifdef CONFIG_SMP
- struct blackfin_pda *next;
-#endif
-
- unsigned long syscfg;
-#ifdef CONFIG_SMP
- unsigned long imask; /* Current IMASK value */
-#endif
-
- unsigned long *ipdt; /* Start of switchable I-CPLB table */
- unsigned long *ipdt_swapcount; /* Number of swaps in ipdt */
- unsigned long *dpdt; /* Start of switchable D-CPLB table */
- unsigned long *dpdt_swapcount; /* Number of swaps in dpdt */
-
- /*
- * Single instructions can have multiple faults, which
- * need to be handled by traps.c, in irq5. We store
- * the exception cause to ensure we don't miss a
- * double fault condition
- */
- unsigned long ex_iptr;
- unsigned long ex_optr;
- unsigned long ex_buf[4];
- unsigned long ex_imask; /* Saved imask from exception */
- unsigned long ex_ipend; /* Saved IPEND from exception */
- unsigned long *ex_stack; /* Exception stack space */
-
-#ifdef ANOMALY_05000261
- unsigned long last_cplb_fault_retx;
-#endif
- unsigned long dcplb_fault_addr;
- unsigned long icplb_fault_addr;
- unsigned long retx;
- unsigned long seqstat;
- unsigned int __nmi_count; /* number of times NMI asserted on this CPU */
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- unsigned long dcplb_doublefault_addr;
- unsigned long icplb_doublefault_addr;
- unsigned long retx_doublefault;
- unsigned long seqstat_doublefault;
-#endif
-};
-
-struct blackfin_initial_pda {
- void *retx;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- void *dcplb_doublefault_addr;
- void *icplb_doublefault_addr;
- void *retx_doublefault;
- unsigned seqstat_doublefault;
-#endif
-};
-
-extern struct blackfin_pda cpu_pda[];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_BLACKFIN_PDA_H */
diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h
deleted file mode 100644
index 3d2b1716322f..000000000000
--- a/arch/blackfin/include/asm/perf_event.h
+++ /dev/null
@@ -1 +0,0 @@
-#define MAX_HWEVENTS 2
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
deleted file mode 100644
index c1ee3d6533fb..000000000000
--- a/arch/blackfin/include/asm/pgtable.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PGTABLE_H
-#define _BLACKFIN_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <asm/page.h>
-#include <asm/def_LPBlackfin.h>
-
-typedef pte_t *pte_addr_t;
-/*
-* Trivial page table functions.
-*/
-#define pgd_present(pgd) (1)
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-
-#define pmd_offset(a, b) ((void *)0)
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x))
-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
-
-#define kern_addr_valid(addr) (1)
-
-#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
-#define pgprot_noncached(prot) (prot)
-
-extern void paging_init(void);
-
-#define __swp_type(x) (0)
-#define __swp_offset(x) (0)
-#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-/*
- * Page assess control based on Blackfin CPLB management
- */
-#define _PAGE_RD (CPLB_USER_RD)
-#define _PAGE_WR (CPLB_USER_WR)
-#define _PAGE_USER (CPLB_USER_RD | CPLB_USER_WR)
-#define _PAGE_ACCESSED CPLB_ALL_ACCESS
-#define _PAGE_DIRTY (CPLB_DIRTY)
-
-#define PTE_BIT_FUNC(fn, op) \
- static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
-
-PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
-PTE_BIT_FUNC(mkread, |= _PAGE_RD);
-PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
-PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
-PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
-PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
-PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
-PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
-PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
-PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
-extern char empty_zero_page[];
-
-#define swapper_pg_dir ((pgd_t *) 0)
-/*
- * No page table caches to initialise.
- */
-#define pgtable_cache_init() do { } while (0)
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START 0
-#define VMALLOC_END 0xffffffff
-
-/* provide a special get_unmapped_area for framebuffer mmaps of nommu */
-extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
- unsigned long, unsigned long,
- unsigned long);
-#define HAVE_ARCH_FB_UNMAPPED_AREA
-
-#define pgprot_writecombine pgprot_noncached
-
-#include <asm-generic/pgtable.h>
-
-#endif /* _BLACKFIN_PGTABLE_H */
diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h
deleted file mode 100644
index f72239bf3638..000000000000
--- a/arch/blackfin/include/asm/pm.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __PM_H__
-#define __PM_H__
-
-#include <linux/suspend.h>
-
-struct bfin_cpu_pm_fns {
- void (*save)(unsigned long *);
- void (*restore)(unsigned long *);
- int (*valid)(suspend_state_t state);
- void (*enter)(suspend_state_t state);
- int (*prepare)(void);
- void (*finish)(void);
-};
-
-extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
-
-# ifdef CONFIG_BFIN_COREB
-void bfin_coreb_start(void);
-void bfin_coreb_stop(void);
-void bfin_coreb_reset(void);
-# endif
-
-#endif
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
deleted file mode 100644
index c8f0939419be..000000000000
--- a/arch/blackfin/include/asm/portmux.h
+++ /dev/null
@@ -1,1204 +0,0 @@
-/*
- * Common header file for Blackfin family of processors
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x) ((x) & 0x1FF)
-#define P_FUNCT(x) (((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
-#define P_DEFINED 0x8000
-#define P_UNDEF 0x4000
-#define P_MAYSHARE 0x2000
-#define P_DONTCARE 0x1000
-
-#ifdef CONFIG_PINCTRL
-int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-#define gpio_pint_regs bfin_pint_regs
-#define adi_internal_set_wake bfin_internal_set_wake
-
-#define peripheral_request(per, label) (0)
-#define peripheral_free(per)
-#define peripheral_request_list(per, label) (0)
-#define peripheral_free_list(per)
-#else
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-#endif
-
-#include <linux/err.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <mach/portmux.h>
-#include <mach/gpio.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef P_TMRCLK
-#define P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif /* _PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
deleted file mode 100644
index dbdbb8a558df..000000000000
--- a/arch/blackfin/include/asm/processor.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BFIN_PROCESSOR_H
-#define __ASM_BFIN_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <asm/ptrace.h>
-#include <mach/blackfin.h>
-
-static inline unsigned long rdusp(void)
-{
- unsigned long usp;
-
- __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
- return usp;
-}
-
-static inline void wrusp(unsigned long usp)
-{
- __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
-}
-
-static inline unsigned long __get_SP(void)
-{
- unsigned long sp;
-
- __asm__ __volatile__("%0 = sp;\n\t" : "=da"(sp));
- return sp;
-}
-
-/*
- * User space process size: 1st byte beyond user address space.
- * Fairly meaningless on nommu. Parts of user programs can be scattered
- * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
- */
-#define TASK_SIZE 0xFFFFFFFF
-
-#ifdef __KERNEL__
-#define STACK_TOP TASK_SIZE
-#endif
-
-#define TASK_UNMAPPED_BASE 0
-
-struct thread_struct {
- unsigned long ksp; /* kernel stack pointer */
- unsigned long usp; /* user stack pointer */
- unsigned short seqstat; /* saved status register */
- unsigned long esp0; /* points to SR of stack frame pt_regs */
- unsigned long pc; /* instruction pointer */
- void * debuggerinfo;
-};
-
-#define INIT_THREAD { \
- sizeof(init_stack) + (unsigned long) init_stack, 0, \
- PS_S, 0, 0 \
-}
-
-extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
- unsigned long new_sp);
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) \
- ({ \
- unsigned long eip = 0; \
- if ((tsk)->thread.esp0 > PAGE_SIZE && \
- MAP_NR((tsk)->thread.esp0) < max_mapnr) \
- eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
- eip; })
-#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax() smp_mb()
-
-/* Get the Silicon Revision of the chip */
-static inline uint32_t __pure bfin_revid(void)
-{
- /* Always use CHIPID, to work around ANOMALY_05000234 */
- uint32_t revid = (bfin_read_CHIPID() & CHIPID_VERSION) >> 28;
-
-#ifdef _BOOTROM_GET_DXE_ADDRESS_TWI
- /*
- * ANOMALY_05000364
- * Incorrect Revision Number in DSPID Register
- */
- if (ANOMALY_05000364 &&
- bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI) == 0x2796)
- revid = 1;
-#endif
-
- return revid;
-}
-
-static inline uint16_t __pure bfin_cpuid(void)
-{
- return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12;
-}
-
-static inline uint32_t __pure bfin_dspid(void)
-{
- return bfin_read_DSPID();
-}
-
-#define blackfin_core_id() (bfin_dspid() & 0xff)
-
-static inline uint32_t __pure bfin_compiled_revid(void)
-{
-#if defined(CONFIG_BF_REV_0_0)
- return 0;
-#elif defined(CONFIG_BF_REV_0_1)
- return 1;
-#elif defined(CONFIG_BF_REV_0_2)
- return 2;
-#elif defined(CONFIG_BF_REV_0_3)
- return 3;
-#elif defined(CONFIG_BF_REV_0_4)
- return 4;
-#elif defined(CONFIG_BF_REV_0_5)
- return 5;
-#elif defined(CONFIG_BF_REV_0_6)
- return 6;
-#elif defined(CONFIG_BF_REV_ANY)
- return 0xffff;
-#else
- return -1;
-#endif
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/pseudo_instructions.h b/arch/blackfin/include/asm/pseudo_instructions.h
deleted file mode 100644
index b00adfa08169..000000000000
--- a/arch/blackfin/include/asm/pseudo_instructions.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * header file for pseudo instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_PSEUDO_
-#define _BLACKFIN_PSEUDO_
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-
-extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode);
-extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode);
-
-#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
deleted file mode 100644
index c00491594b46..000000000000
--- a/arch/blackfin/include/asm/ptrace.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-#ifndef __ASSEMBLY__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
- master interrupt enable. */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-
-#define arch_has_single_step() (1)
-/* common code demands this function */
-#define ptrace_disable(child) user_disable_single_step(child)
-#define current_user_stack_pointer() rdusp()
-
-extern int is_user_addr_valid(struct task_struct *child,
- unsigned long start, unsigned long len);
-
-/*
- * Get the address of the live pt_regs for the specified task.
- * These are saved onto the top kernel stack when the process
- * is not running.
- *
- * Note: if a user thread is execve'd from kernel space, the
- * kernel stack will not be empty on entry to the kernel, so
- * ptracing these tasks will fail.
- */
-#define task_pt_regs(task) \
- (struct pt_regs *) \
- ((unsigned long)task_stack_page(task) + \
- (THREAD_SIZE - sizeof(struct pt_regs)))
-
-#include <asm-generic/ptrace.h>
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/reboot.h b/arch/blackfin/include/asm/reboot.h
deleted file mode 100644
index ae1e36329bec..000000000000
--- a/arch/blackfin/include/asm/reboot.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * reboot.h - shutdown/reboot header
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_REBOOT_H__
-#define __ASM_REBOOT_H__
-
-/* optional board specific hooks */
-extern void native_machine_restart(char *cmd);
-extern void native_machine_halt(void);
-extern void native_machine_power_off(void);
-
-/* common reboot workarounds */
-extern void bfin_reset_boot_spi_cs(unsigned short pin);
-
-#endif
diff --git a/arch/blackfin/include/asm/rwlock.h b/arch/blackfin/include/asm/rwlock.h
deleted file mode 100644
index 98ebc07cb283..000000000000
--- a/arch/blackfin/include/asm/rwlock.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_BLACKFIN_RWLOCK_H
-#define _ASM_BLACKFIN_RWLOCK_H
-
-#define RW_LOCK_BIAS 0x01000000
-
-#endif
diff --git a/arch/blackfin/include/asm/scb.h b/arch/blackfin/include/asm/scb.h
deleted file mode 100644
index a294cc0d1a4a..000000000000
--- a/arch/blackfin/include/asm/scb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define SCB_SLOT_OFFSET 24
-#define SCB_MI_MAX_SLOT 32
-
-struct scb_mi_prio {
- unsigned long scb_mi_arbr;
- unsigned long scb_mi_arbw;
- unsigned char scb_mi_slots;
- unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
-};
-
-extern struct scb_mi_prio scb_data[];
-
-extern void init_scb(void);
diff --git a/arch/blackfin/include/asm/sections.h b/arch/blackfin/include/asm/sections.h
deleted file mode 100644
index fbd408475725..000000000000
--- a/arch/blackfin/include/asm/sections.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_SECTIONS_H
-#define _BLACKFIN_SECTIONS_H
-
-/* only used when MTD_UCLINUX */
-extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
-
-extern unsigned long _ramstart, _ramend, _rambase;
-extern unsigned long memory_start, memory_end, physical_mem_end;
-
-/*
- * The weak markings on the lengths might seem weird, but this is required
- * in order to make gcc accept the fact that these may actually have a value
- * of 0 (since they aren't actually addresses, but sizes of sections).
- */
-extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[];
-extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[],
- _data_l1_lma[], __weak _data_l1_len[];
-#ifdef CONFIG_ROMKERNEL
-extern char _data_lma[], _data_len[], _sinitdata[], _einitdata[], _init_data_lma[], _init_data_len[];
-#endif
-extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[],
- _data_b_l1_lma[], __weak _data_b_l1_len[];
-extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[],
- _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[];
-
-#include <asm/mem_map.h>
-
-/* Blackfin systems have discontinuous memory map and no virtualized memory */
-static inline int arch_is_kernel_text(unsigned long addr)
-{
- return
- (L1_CODE_LENGTH &&
- addr >= (unsigned long)_stext_l1 &&
- addr < (unsigned long)_etext_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_stext_l2 &&
- addr < (unsigned long)_etext_l2);
-}
-#define arch_is_kernel_text(addr) arch_is_kernel_text(addr)
-
-static inline int arch_is_kernel_data(unsigned long addr)
-{
- return
- (L1_DATA_A_LENGTH &&
- addr >= (unsigned long)_sdata_l1 &&
- addr < (unsigned long)_ebss_l1)
- ||
- (L1_DATA_B_LENGTH &&
- addr >= (unsigned long)_sdata_b_l1 &&
- addr < (unsigned long)_ebss_b_l1)
- ||
- (L2_LENGTH &&
- addr >= (unsigned long)_sdata_l2 &&
- addr < (unsigned long)_ebss_l2);
-}
-#define arch_is_kernel_data(addr) arch_is_kernel_data(addr)
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/arch/blackfin/include/asm/segment.h b/arch/blackfin/include/asm/segment.h
deleted file mode 100644
index f8e1984ffc7e..000000000000
--- a/arch/blackfin/include/asm/segment.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_SEGMENT_H
-#define _BFIN_SEGMENT_H
-
-#define KERNEL_DS (0x5)
-#define USER_DS (0x1)
-
-#endif /* _BFIN_SEGMENT_H */
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
deleted file mode 100644
index 9631598dcc5d..000000000000
--- a/arch/blackfin/include/asm/smp.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SMP_H
-#define __ASM_BLACKFIN_SMP_H
-
-#include <linux/kernel.h>
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/cache.h>
-#include <asm/blackfin.h>
-#include <mach/smp.h>
-
-#define raw_smp_processor_id() blackfin_core_id()
-
-extern void bfin_relocate_coreb_l1_mem(void);
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
-asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr);
-extern unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct corelock_slot {
- int lock;
-};
-extern struct corelock_slot corelock;
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-extern unsigned long icache_invld_count[NR_CPUS];
-#endif
-#ifdef __ARCH_SYNC_CORE_DCACHE
-extern unsigned long dcache_invld_count[NR_CPUS];
-#endif
-
-void smp_icache_flush_range_others(unsigned long start,
- unsigned long end);
-#ifdef CONFIG_HOTPLUG_CPU
-void coreb_die(void);
-void cpu_die(void);
-void platform_cpu_die(void);
-int __cpu_disable(void);
-int __cpu_die(unsigned int cpu);
-#endif
-
-void smp_timer_broadcast(const struct cpumask *mask);
-
-
-#endif /* !__ASM_BLACKFIN_SMP_H */
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
deleted file mode 100644
index 839d1441af3a..000000000000
--- a/arch/blackfin/include/asm/spinlock.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_SPINLOCK_H
-#define __BFIN_SPINLOCK_H
-
-#ifndef CONFIG_SMP
-# include <asm-generic/spinlock.h>
-#else
-
-#include <linux/atomic.h>
-#include <asm/processor.h>
-#include <asm/barrier.h>
-
-asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
-asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
-asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_read_lock_asm(volatile int *ptr);
-asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
-asmlinkage void __raw_write_lock_asm(volatile int *ptr);
-asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
-asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
-
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- return __raw_spin_is_locked_asm(&lock->lock);
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- __raw_spin_lock_asm(&lock->lock);
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- return __raw_spin_trylock_asm(&lock->lock);
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- __raw_spin_unlock_asm(&lock->lock);
-}
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- __raw_read_lock_asm(&rw->lock);
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
- return __raw_read_trylock_asm(&rw->lock);
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- __raw_read_unlock_asm(&rw->lock);
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- __raw_write_lock_asm(&rw->lock);
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
- return __raw_write_trylock_asm(&rw->lock);
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- __raw_write_unlock_asm(&rw->lock);
-}
-
-#endif
-
-#endif /* !__BFIN_SPINLOCK_H */
diff --git a/arch/blackfin/include/asm/spinlock_types.h b/arch/blackfin/include/asm/spinlock_types.h
deleted file mode 100644
index 1a33608c958b..000000000000
--- a/arch/blackfin/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-#include <asm/rwlock.h>
-
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
-
-#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
deleted file mode 100644
index 423c099aa988..000000000000
--- a/arch/blackfin/include/asm/string.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_STRING_H_
-#define _BLACKFIN_STRING_H_
-
-#include <linux/types.h>
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-extern char *strcpy(char *dest, const char *src);
-
-#define __HAVE_ARCH_STRNCPY
-extern char *strncpy(char *dest, const char *src, size_t n);
-
-#define __HAVE_ARCH_STRCMP
-extern int strcmp(const char *cs, const char *ct);
-
-#define __HAVE_ARCH_STRNCMP
-extern int strncmp(const char *cs, const char *ct, size_t count);
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t count);
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *d, const void *s, size_t count);
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *, const void *, __kernel_size_t);
-#define __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *s, int c, size_t n);
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#endif /*__KERNEL__*/
-#endif /* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/switch_to.h b/arch/blackfin/include/asm/switch_to.h
deleted file mode 100644
index aaf671be9242..000000000000
--- a/arch/blackfin/include/asm/switch_to.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * Tony Kou (tonyko@lineo.ca)
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BLACKFIN_SWITCH_TO_H
-#define _BLACKFIN_SWITCH_TO_H
-
-#define prepare_to_switch() do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.
- */
-
-#include <asm/l1layout.h>
-#include <asm/mem_map.h>
-
-asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
-
-#ifndef CONFIG_SMP
-#define switch_to(prev,next,last) \
-do { \
- memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
- sizeof *L1_SCRATCH_TASK_INFO); \
- (last) = resume (prev, next); \
-} while (0)
-#else
-#define switch_to(prev, next, last) \
-do { \
- (last) = resume(prev, next); \
-} while (0)
-#endif
-
-#endif /* _BLACKFIN_SWITCH_TO_H */
diff --git a/arch/blackfin/include/asm/syscall.h b/arch/blackfin/include/asm/syscall.h
deleted file mode 100644
index 4921a4815cce..000000000000
--- a/arch/blackfin/include/asm/syscall.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Magic syscall break down functions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_SYSCALL_H__
-#define __ASM_BLACKFIN_SYSCALL_H__
-
-/*
- * Blackfin syscalls are simple:
- * enter:
- * p0: syscall number
- * r{0,1,2,3,4,5}: syscall args 0,1,2,3,4,5
- * exit:
- * r0: return/error value
- */
-
-#include <linux/err.h>
-#include <linux/sched.h>
-#include <asm/ptrace.h>
-
-static inline long
-syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->p0;
-}
-
-static inline void
-syscall_rollback(struct task_struct *task, struct pt_regs *regs)
-{
- regs->p0 = regs->orig_p0;
-}
-
-static inline long
-syscall_get_error(struct task_struct *task, struct pt_regs *regs)
-{
- return IS_ERR_VALUE(regs->r0) ? regs->r0 : 0;
-}
-
-static inline long
-syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->r0;
-}
-
-static inline void
-syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
- int error, long val)
-{
- regs->r0 = error ? -error : val;
-}
-
-/**
- * syscall_get_arguments()
- * @task: unused
- * @regs: the register layout to extract syscall arguments from
- * @i: first syscall argument to extract
- * @n: number of syscall arguments to extract
- * @args: array to return the syscall arguments in
- *
- * args[0] gets i'th argument, args[n - 1] gets the i+n-1'th argument
- */
-static inline void
-syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, unsigned long *args)
-{
- /*
- * Assume the ptrace layout doesn't change -- r5 is first in memory,
- * then r4, ..., then r0. So we simply reverse the ptrace register
- * array in memory to store into the args array.
- */
- long *aregs = &regs->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *args++ = *aregs--;
-}
-
-/* See syscall_get_arguments() comments */
-static inline void
-syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
- unsigned int i, unsigned int n, const unsigned long *args)
-{
- long *aregs = &regs->r0 - i;
-
- BUG_ON(i > 5 || i + n > 6);
-
- while (n--)
- *aregs-- = *args++;
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
deleted file mode 100644
index a5aeab4e5f2d..000000000000
--- a/arch/blackfin/include/asm/thread_info.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-#include <asm/entry.h>
-#include <asm/l1layout.h>
-#include <linux/compiler.h>
-
-#ifdef __KERNEL__
-
-/* Thread Align Mask to reach to the top of the stack
- * for any process
- */
-#define ALIGN_PAGE_MASK 0xffffe000
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE_ORDER 1
-#define THREAD_SIZE 8192 /* 2 pages */
-#define STACK_WARN (THREAD_SIZE/8)
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long mm_segment_t;
-
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- int cpu; /* cpu we're on */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
- mm_segment_t addr_limit; /* address limit */
-#ifndef CONFIG_SMP
- struct l1_scratch_task_info l1_task_info;
-#endif
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
-}
-
-/* Given a task stack pointer, you can find its corresponding
- * thread_info structure just by masking it to the THREAD_SIZE
- * boundary (currently 8K as you can see above).
- */
-__attribute_const__
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
- __asm__("%0 = sp;" : "=da"(ti));
- return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
-}
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_MEMDIE 4 /* is terminating due to OOM killer */
-#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
-#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
-#define TIF_SINGLESTEP 9
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-
-#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/blackfin/include/asm/time.h b/arch/blackfin/include/asm/time.h
deleted file mode 100644
index 9ca7db844d10..000000000000
--- a/arch/blackfin/include/asm/time.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * asm-blackfin/time.h:
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIME_H
-#define _ASM_BLACKFIN_TIME_H
-
-/*
- * The way that the Blackfin core timer works is:
- * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
- * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
- *
- * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
- * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
- * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
- * to use TSCALE, and program it to zero (which is pass CCLK through).
- * If you feel like using it, try to keep HZ * TIMESCALE to some
- * value that divides easy (like power of 2).
- */
-
-#ifndef CONFIG_CPU_FREQ
-# define TIME_SCALE 1
-#else
-/*
- * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
- * Whenever we change the Core Clock frequency changes we immediately
- * adjust the Core Timer Presale Register. This way we don't lose time.
- */
-#define TIME_SCALE 4
-
-# ifdef CONFIG_CYCLES_CLOCKSOURCE
-extern unsigned long long __bfin_cycles_off;
-extern unsigned int __bfin_cycles_mod;
-# endif
-#endif
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-extern void bfin_coretmr_init(void);
-extern void bfin_coretmr_clockevent_init(void);
-#endif
-
-#endif
diff --git a/arch/blackfin/include/asm/timex.h b/arch/blackfin/include/asm/timex.h
deleted file mode 100644
index 248aeb066805..000000000000
--- a/arch/blackfin/include/asm/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * asm-blackfin/timex.h: cpu cycles!
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIMEX_H
-#define _ASM_BLACKFIN_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- unsigned long tmp, tmp2;
- __asm__ __volatile__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
- return tmp | ((cycles_t)tmp2 << 32);
-}
-
-#endif
diff --git a/arch/blackfin/include/asm/tlb.h b/arch/blackfin/include/asm/tlb.h
deleted file mode 100644
index a74ae08af1a7..000000000000
--- a/arch/blackfin/include/asm/tlb.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TLB_H
-#define _BLACKFIN_TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _BLACKFIN_TLB_H */
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h
deleted file mode 100644
index 7c368682c0a3..000000000000
--- a/arch/blackfin/include/asm/tlbflush.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#include <asm-generic/tlbflush.h>
-#define flush_tlb_kernel_range(s, e) do { } while (0)
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
deleted file mode 100644
index 33589a29b8d8..000000000000
--- a/arch/blackfin/include/asm/trace.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * header file for hardware trace functions
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_TRACE_
-#define _BLACKFIN_TRACE_
-
-/* Normally, we use ON, but you can't turn on software expansion until
- * interrupts subsystem is ready
- */
-
-#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
-#else
-#define BFIN_TRACE_ON (BFIN_TRACE_INIT)
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long trace_buff_offset;
-extern unsigned long software_trace_buff[];
-#if defined(CONFIG_DEBUG_VERBOSE)
-extern void decode_address(char *buf, unsigned long address);
-extern bool get_instruction(unsigned int *val, unsigned short *address);
-#else
-static inline void decode_address(char *buf, unsigned long address) { }
-static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; }
-#endif
-
-/* Trace Macros for C files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_init() bfin_write_TBUFCTL(BFIN_TRACE_INIT)
-
-#define trace_buffer_save(x) \
- do { \
- (x) = bfin_read_TBUFCTL(); \
- bfin_write_TBUFCTL((x) & ~TBUFEN); \
- } while (0)
-
-#define trace_buffer_restore(x) \
- do { \
- bfin_write_TBUFCTL((x)); \
- } while (0)
-#else /* DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_save(x)
-#define trace_buffer_restore(x)
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#else
-/* Trace Macros for Assembly files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_stop(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_init(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = BFIN_TRACE_INIT; \
- [preg] = dreg;
-
-#define trace_buffer_save(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [preg]; \
- [--sp] = dreg; \
- dreg = 0x1; \
- [preg] = dreg;
-
-#define trace_buffer_restore(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = [sp++]; \
- [preg] = dreg;
-
-#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_stop(preg, dreg)
-#define trace_buffer_init(preg, dreg)
-#define trace_buffer_save(preg, dreg)
-#define trace_buffer_restore(preg, dreg)
-
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
-#else
-# define DEBUG_HWTRACE_SAVE(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg)
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _BLACKFIN_TRACE_ */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
deleted file mode 100644
index cec771b8100c..000000000000
--- a/arch/blackfin/include/asm/traps.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2001 Lineo, Inc
- * Tony Kou
- * 1993 Hamish Macdonald
- *
- * Licensed under the GPL-2
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS (0)
-#define VEC_EXCPT01 (1)
-#define VEC_EXCPT02 (2)
-#define VEC_EXCPT03 (3)
-#define VEC_EXCPT04 (4)
-#define VEC_EXCPT05 (5)
-#define VEC_EXCPT06 (6)
-#define VEC_EXCPT07 (7)
-#define VEC_EXCPT08 (8)
-#define VEC_EXCPT09 (9)
-#define VEC_EXCPT10 (10)
-#define VEC_EXCPT11 (11)
-#define VEC_EXCPT12 (12)
-#define VEC_EXCPT13 (13)
-#define VEC_EXCPT14 (14)
-#define VEC_EXCPT15 (15)
-#define VEC_STEP (16)
-#define VEC_OVFLOW (17)
-#define VEC_UNDEF_I (33)
-#define VEC_ILGAL_I (34)
-#define VEC_CPLB_VL (35)
-#define VEC_MISALI_D (36)
-#define VEC_UNCOV (37)
-#define VEC_CPLB_M (38)
-#define VEC_CPLB_MHIT (39)
-#define VEC_WATCH (40)
-#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I (42)
-#define VEC_CPLB_I_VL (43)
-#define VEC_CPLB_I_M (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR (63)
-
-#ifndef __ASSEMBLY__
-
-#define HWC_x2(level) \
- "System MMR Error\n" \
- level " - An error occurred due to an invalid access to an System MMR location\n" \
- level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
- level " or a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3(level) \
- "External Memory Addressing Error\n"
-#define EXC_0x04(level) \
- "Unimplmented exception occurred\n" \
- level " - Maybe you forgot to install a custom exception handler?\n"
-#define HWC_x12(level) \
- "Performance Monitor Overflow\n"
-#define HWC_x18(level) \
- "RAISE 5 instruction\n" \
- level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default(level) \
- "Reserved\n"
-#define EXC_0x03(level) \
- "Application stack overflow\n" \
- level " - Please increase the stack size of the application using elf2flt -s option,\n" \
- level " and/or reduce the stack use of the application.\n"
-#define EXC_0x10(level) \
- "Single step\n" \
- level " - When the processor is in single step mode, every instruction\n" \
- level " generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11(level) \
- "Exception caused by a trace buffer full condition\n" \
- level " - The processor takes this exception when the trace\n" \
- level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21(level) \
- "Undefined instruction\n" \
- level " - May be used to emulate instructions that are not defined for\n" \
- level " a particular processor implementation.\n"
-#define EXC_0x22(level) \
- "Illegal instruction combination\n" \
- level " - See section for multi-issue rules in the Blackfin\n" \
- level " Processor Instruction Set Reference.\n"
-#define EXC_0x23(level) \
- "Data access CPLB protection violation\n" \
- level " - Attempted read or write to Supervisor resource,\n" \
- level " or illegal data memory access. \n"
-#define EXC_0x24(level) \
- "Data access misaligned address violation\n" \
- level " - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25(level) \
- "Unrecoverable event\n" \
- level " - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26(level) \
- "Data access CPLB miss\n" \
- level " - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27(level) \
- "Data access multiple CPLB hits\n" \
- level " - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28(level) \
- "Program Sequencer Exception caused by an emulation watchpoint match\n" \
- level " - There is a watchpoint match, and one of the EMUSW\n" \
- level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A(level) \
- "Instruction fetch misaligned address violation\n" \
- level " - Attempted misaligned instruction cache fetch.\n"
-#define EXC_0x2B(level) \
- "CPLB protection violation\n" \
- level " - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C(level) \
- "Instruction fetch CPLB miss\n" \
- level " - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D(level) \
- "Instruction fetch multiple CPLB hits\n" \
- level " - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E(level) \
- "Illegal use of supervisor resource\n" \
- level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
- level " Supervisor resources are registers and instructions that are reserved\n" \
- level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
- level " only instructions.\n"
-
-extern void double_fault_c(struct pt_regs *fp);
-
-#endif /* __ASSEMBLY__ */
-#endif /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h
deleted file mode 100644
index 45da4bcb050e..000000000000
--- a/arch/blackfin/include/asm/uaccess.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Based on: include/asm-m68knommu/uaccess.h
- */
-
-#ifndef __BLACKFIN_UACCESS_H
-#define __BLACKFIN_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-#include <asm/sections.h>
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-
-static inline void set_fs(mm_segment_t fs)
-{
- current_thread_info()->addr_limit = fs;
-}
-
-#define segment_eq(a, b) ((a) == (b))
-
-#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- */
-
-#ifndef CONFIG_ACCESS_CHECK
-static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
-#else
-extern int _access_ok(unsigned long addr, unsigned long size);
-#endif
-
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x, p) \
- ({ \
- int _err = 0; \
- typeof(*(p)) _x = (x); \
- typeof(*(p)) __user *_p = (p); \
- if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
- _err = -EFAULT; \
- } \
- else { \
- switch (sizeof (*(_p))) { \
- case 1: \
- __put_user_asm(_x, _p, B); \
- break; \
- case 2: \
- __put_user_asm(_x, _p, W); \
- break; \
- case 4: \
- __put_user_asm(_x, _p, ); \
- break; \
- case 8: { \
- long _xl, _xh; \
- _xl = ((__force long *)&_x)[0]; \
- _xh = ((__force long *)&_x)[1]; \
- __put_user_asm(_xl, ((__force long __user *)_p)+0, );\
- __put_user_asm(_xh, ((__force long __user *)_p)+1, );\
- } break; \
- default: \
- _err = __put_user_bad(); \
- break; \
- } \
- } \
- _err; \
- })
-
-#define __put_user(x, p) put_user(x, p)
-static inline int bad_user_access_length(void)
-{
- panic("bad_user_access_length");
- return -1;
-}
-
-#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
- __FILE__, __LINE__, __func__),\
- bad_user_access_length(), (-EFAULT))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long __force *)(x))
-
-#define __put_user_asm(x, p, bhw) \
- __asm__ (#bhw"[%1] = %0;\n\t" \
- : /* no outputs */ \
- :"d" (x), "a" (__ptr(p)) : "memory")
-
-#define get_user(x, ptr) \
-({ \
- int _err = 0; \
- unsigned long _val = 0; \
- const typeof(*(ptr)) __user *_p = (ptr); \
- const size_t ptr_size = sizeof(*(_p)); \
- if (likely(access_ok(VERIFY_READ, _p, ptr_size))) { \
- BUILD_BUG_ON(ptr_size >= 8); \
- switch (ptr_size) { \
- case 1: \
- __get_user_asm(_val, _p, B, (Z)); \
- break; \
- case 2: \
- __get_user_asm(_val, _p, W, (Z)); \
- break; \
- case 4: \
- __get_user_asm(_val, _p, , ); \
- break; \
- } \
- } else \
- _err = -EFAULT; \
- x = (__force typeof(*(ptr)))_val; \
- _err; \
-})
-
-#define __get_user(x, p) get_user(x, p)
-
-#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
-
-#define __get_user_asm(x, ptr, bhw, option) \
-({ \
- __asm__ __volatile__ ( \
- "%0 =" #bhw "[%1]" #option ";" \
- : "=d" (x) \
- : "a" (__ptr(ptr))); \
-})
-
-static inline unsigned long __must_check
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- memcpy(to, (const void __force *)from, n);
- return 0;
-}
-
-static inline unsigned long __must_check
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- memcpy((void __force *)to, from, n);
- SSYNC();
- return 0;
-}
-
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long __must_check
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- char *tmp;
- if (!access_ok(VERIFY_READ, src, 1))
- return -EFAULT;
- strncpy(dst, (const char __force *)src, count);
- for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
- return (tmp - dst);
-}
-
-/*
- * Get the size of a string in user space.
- * src: The string to measure
- * n: The maximum valid length
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- * If the string is too long, returns a value greater than n.
- */
-static inline long __must_check strnlen_user(const char __user *src, long n)
-{
- if (!access_ok(VERIFY_READ, src, 1))
- return 0;
- return strnlen((const char __force *)src, n) + 1;
-}
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long __must_check
-__clear_user(void __user *to, unsigned long n)
-{
- if (!access_ok(VERIFY_WRITE, to, n))
- return n;
- memset((void __force *)to, 0, n);
- return 0;
-}
-
-#define clear_user(to, n) __clear_user(to, n)
-
-/* How to interpret these return values:
- * CORE: can be accessed by core load or dma memcpy
- * CORE_ONLY: can only be accessed by core load
- * DMA: can only be accessed by dma memcpy
- * IDMA: can only be accessed by interprocessor dma memcpy (BF561)
- * ITEST: can be accessed by isram memcpy or dma memcpy
- */
-enum {
- BFIN_MEM_ACCESS_CORE = 0,
- BFIN_MEM_ACCESS_CORE_ONLY,
- BFIN_MEM_ACCESS_DMA,
- BFIN_MEM_ACCESS_IDMA,
- BFIN_MEM_ACCESS_ITEST,
-};
-/**
- * bfin_mem_access_type() - what kind of memory access is required
- * @addr: the address to check
- * @size: number of bytes needed
- * @return: <0 is error, >=0 is BFIN_MEM_ACCESS_xxx enum (see above)
- */
-int bfin_mem_access_type(unsigned long addr, unsigned long size);
-
-#endif /* _BLACKFIN_UACCESS_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
deleted file mode 100644
index c8c8ff9eff61..000000000000
--- a/arch/blackfin/include/asm/unistd.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-#ifndef __ASM_BFIN_UNISTD_H
-#define __ASM_BFIN_UNISTD_H
-
-#include <uapi/asm/unistd.h>
-
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_VFORK
-
-#endif /* __ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/include/asm/vga.h b/arch/blackfin/include/asm/vga.h
deleted file mode 100644
index 89d82fd8fcf1..000000000000
--- a/arch/blackfin/include/asm/vga.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/vga.h>
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
deleted file mode 100644
index af9fc8171ebc..000000000000
--- a/arch/blackfin/include/mach-common/irq.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Common Blackfin IRQ definitions (i.e. the CEC)
- *
- * Copyright 2005-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_COMMON_IRQ_H_
-#define _MACH_COMMON_IRQ_H_
-
-/*
- * Core events interrupt source definitions
- *
- * Event Source Event Name
- * Emulation EMU 0 (highest priority)
- * Reset RST 1
- * NMI NMI 2
- * Exception EVX 3
- * Reserved -- 4
- * Hardware Error IVHW 5
- * Core Timer IVTMR 6
- * Peripherals IVG7 7
- * Peripherals IVG8 8
- * Peripherals IVG9 9
- * Peripherals IVG10 10
- * Peripherals IVG11 11
- * Peripherals IVG12 12
- * Peripherals IVG13 13
- * Softirq IVG14 14
- * System Call IVG15 15 (lowest priority)
- */
-
-/* The ABSTRACT IRQ definitions */
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
-#define BFIN_IRQ(x) ((x) + IVG7)
-#define BFIN_SYSIRQ(x) ((x) - IVG7)
-
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
deleted file mode 100644
index 382178b361af..000000000000
--- a/arch/blackfin/include/mach-common/pll.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_COMMON_PLL_H
-#define _MACH_COMMON_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-#ifndef bfin_iwr_restore
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
-#ifdef SIC_IWR
- bfin_write_SIC_IWR(iwr0);
-#else
- bfin_write_SIC_IWR0(iwr0);
-# ifdef SIC_IWR1
- bfin_write_SIC_IWR1(iwr1);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(iwr2);
-# endif
-#endif
-}
-#endif
-
-#ifndef bfin_iwr_save
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
-#ifdef SIC_IWR
- *iwr0 = bfin_read_SIC_IWR();
-#else
- *iwr0 = bfin_read_SIC_IWR0();
-# ifdef SIC_IWR1
- *iwr1 = bfin_read_SIC_IWR1();
-# endif
-# ifdef SIC_IWR2
- *iwr2 = bfin_read_SIC_IWR2();
-# endif
-#endif
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#endif
-
-static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
-{
- unsigned long flags, iwr0, iwr1, iwr2;
-
- if (val == bfin_read_PLL_CTL())
- return;
-
- flags = hard_local_irq_save();
- /* Enable the PLL Wakeup bit in SIC IWR */
- bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
-
- bfin_write16(addr, val);
- SSYNC();
- asm("IDLE;");
-
- bfin_iwr_restore(iwr0, iwr1, iwr2);
- hard_local_irq_restore(flags);
-}
-
-/* Writing to PLL_CTL initiates a PLL relock sequence */
-static inline void bfin_write_PLL_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(PLL_CTL, val);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence */
-static inline void bfin_write_VR_CTL(unsigned int val)
-{
- _bfin_write_pll_relock(VR_CTL, val);
-}
-
-#endif
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
deleted file mode 100644
index 71bcd74f83fd..000000000000
--- a/arch/blackfin/include/mach-common/ports-a.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port A Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_A__
-#define __BFIN_PERIPHERAL_PORT_A__
-
-#define PA0 (1 << 0)
-#define PA1 (1 << 1)
-#define PA2 (1 << 2)
-#define PA3 (1 << 3)
-#define PA4 (1 << 4)
-#define PA5 (1 << 5)
-#define PA6 (1 << 6)
-#define PA7 (1 << 7)
-#define PA8 (1 << 8)
-#define PA9 (1 << 9)
-#define PA10 (1 << 10)
-#define PA11 (1 << 11)
-#define PA12 (1 << 12)
-#define PA13 (1 << 13)
-#define PA14 (1 << 14)
-#define PA15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
deleted file mode 100644
index 8013cc8e839b..000000000000
--- a/arch/blackfin/include/mach-common/ports-b.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port B Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_B__
-#define __BFIN_PERIPHERAL_PORT_B__
-
-#define PB0 (1 << 0)
-#define PB1 (1 << 1)
-#define PB2 (1 << 2)
-#define PB3 (1 << 3)
-#define PB4 (1 << 4)
-#define PB5 (1 << 5)
-#define PB6 (1 << 6)
-#define PB7 (1 << 7)
-#define PB8 (1 << 8)
-#define PB9 (1 << 9)
-#define PB10 (1 << 10)
-#define PB11 (1 << 11)
-#define PB12 (1 << 12)
-#define PB13 (1 << 13)
-#define PB14 (1 << 14)
-#define PB15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
deleted file mode 100644
index 94e71010ffe9..000000000000
--- a/arch/blackfin/include/mach-common/ports-c.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port C Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_C__
-#define __BFIN_PERIPHERAL_PORT_C__
-
-#define PC0 (1 << 0)
-#define PC1 (1 << 1)
-#define PC2 (1 << 2)
-#define PC3 (1 << 3)
-#define PC4 (1 << 4)
-#define PC5 (1 << 5)
-#define PC6 (1 << 6)
-#define PC7 (1 << 7)
-#define PC8 (1 << 8)
-#define PC9 (1 << 9)
-#define PC10 (1 << 10)
-#define PC11 (1 << 11)
-#define PC12 (1 << 12)
-#define PC13 (1 << 13)
-#define PC14 (1 << 14)
-#define PC15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
deleted file mode 100644
index ba84a9fb3450..000000000000
--- a/arch/blackfin/include/mach-common/ports-d.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port D Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_D__
-#define __BFIN_PERIPHERAL_PORT_D__
-
-#define PD0 (1 << 0)
-#define PD1 (1 << 1)
-#define PD2 (1 << 2)
-#define PD3 (1 << 3)
-#define PD4 (1 << 4)
-#define PD5 (1 << 5)
-#define PD6 (1 << 6)
-#define PD7 (1 << 7)
-#define PD8 (1 << 8)
-#define PD9 (1 << 9)
-#define PD10 (1 << 10)
-#define PD11 (1 << 11)
-#define PD12 (1 << 12)
-#define PD13 (1 << 13)
-#define PD14 (1 << 14)
-#define PD15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
deleted file mode 100644
index 2264fb58bc2b..000000000000
--- a/arch/blackfin/include/mach-common/ports-e.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port E Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_E__
-#define __BFIN_PERIPHERAL_PORT_E__
-
-#define PE0 (1 << 0)
-#define PE1 (1 << 1)
-#define PE2 (1 << 2)
-#define PE3 (1 << 3)
-#define PE4 (1 << 4)
-#define PE5 (1 << 5)
-#define PE6 (1 << 6)
-#define PE7 (1 << 7)
-#define PE8 (1 << 8)
-#define PE9 (1 << 9)
-#define PE10 (1 << 10)
-#define PE11 (1 << 11)
-#define PE12 (1 << 12)
-#define PE13 (1 << 13)
-#define PE14 (1 << 14)
-#define PE15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
deleted file mode 100644
index 2b8ca3ae2a8e..000000000000
--- a/arch/blackfin/include/mach-common/ports-f.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port F Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_F__
-#define __BFIN_PERIPHERAL_PORT_F__
-
-#define PF0 (1 << 0)
-#define PF1 (1 << 1)
-#define PF2 (1 << 2)
-#define PF3 (1 << 3)
-#define PF4 (1 << 4)
-#define PF5 (1 << 5)
-#define PF6 (1 << 6)
-#define PF7 (1 << 7)
-#define PF8 (1 << 8)
-#define PF9 (1 << 9)
-#define PF10 (1 << 10)
-#define PF11 (1 << 11)
-#define PF12 (1 << 12)
-#define PF13 (1 << 13)
-#define PF14 (1 << 14)
-#define PF15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
deleted file mode 100644
index 11ad917fcf91..000000000000
--- a/arch/blackfin/include/mach-common/ports-g.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port G Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_G__
-#define __BFIN_PERIPHERAL_PORT_G__
-
-#define PG0 (1 << 0)
-#define PG1 (1 << 1)
-#define PG2 (1 << 2)
-#define PG3 (1 << 3)
-#define PG4 (1 << 4)
-#define PG5 (1 << 5)
-#define PG6 (1 << 6)
-#define PG7 (1 << 7)
-#define PG8 (1 << 8)
-#define PG9 (1 << 9)
-#define PG10 (1 << 10)
-#define PG11 (1 << 11)
-#define PG12 (1 << 12)
-#define PG13 (1 << 13)
-#define PG14 (1 << 14)
-#define PG15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
deleted file mode 100644
index 511d088b8094..000000000000
--- a/arch/blackfin/include/mach-common/ports-h.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port H Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_H__
-#define __BFIN_PERIPHERAL_PORT_H__
-
-#define PH0 (1 << 0)
-#define PH1 (1 << 1)
-#define PH2 (1 << 2)
-#define PH3 (1 << 3)
-#define PH4 (1 << 4)
-#define PH5 (1 << 5)
-#define PH6 (1 << 6)
-#define PH7 (1 << 7)
-#define PH8 (1 << 8)
-#define PH9 (1 << 9)
-#define PH10 (1 << 10)
-#define PH11 (1 << 11)
-#define PH12 (1 << 12)
-#define PH13 (1 << 13)
-#define PH14 (1 << 14)
-#define PH15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
deleted file mode 100644
index 21bbab166ae8..000000000000
--- a/arch/blackfin/include/mach-common/ports-i.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port I Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_I__
-#define __BFIN_PERIPHERAL_PORT_I__
-
-#define PI0 (1 << 0)
-#define PI1 (1 << 1)
-#define PI2 (1 << 2)
-#define PI3 (1 << 3)
-#define PI4 (1 << 4)
-#define PI5 (1 << 5)
-#define PI6 (1 << 6)
-#define PI7 (1 << 7)
-#define PI8 (1 << 8)
-#define PI9 (1 << 9)
-#define PI10 (1 << 10)
-#define PI11 (1 << 11)
-#define PI12 (1 << 12)
-#define PI13 (1 << 13)
-#define PI14 (1 << 14)
-#define PI15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
deleted file mode 100644
index 96a252b0b0bd..000000000000
--- a/arch/blackfin/include/mach-common/ports-j.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Port J Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT_J__
-#define __BFIN_PERIPHERAL_PORT_J__
-
-#define PJ0 (1 << 0)
-#define PJ1 (1 << 1)
-#define PJ2 (1 << 2)
-#define PJ3 (1 << 3)
-#define PJ4 (1 << 4)
-#define PJ5 (1 << 5)
-#define PJ6 (1 << 6)
-#define PJ7 (1 << 7)
-#define PJ8 (1 << 8)
-#define PJ9 (1 << 9)
-#define PJ10 (1 << 10)
-#define PJ11 (1 << 11)
-#define PJ12 (1 << 12)
-#define PJ13 (1 << 13)
-#define PJ14 (1 << 14)
-#define PJ15 (1 << 15)
-
-#endif
diff --git a/arch/blackfin/include/uapi/asm/Kbuild b/arch/blackfin/include/uapi/asm/Kbuild
deleted file mode 100644
index 2240b38c2915..000000000000
--- a/arch/blackfin/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,25 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += auxvec.h
-generic-y += bitsperlong.h
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += ioctl.h
-generic-y += ipcbuf.h
-generic-y += kvm_para.h
-generic-y += mman.h
-generic-y += msgbuf.h
-generic-y += param.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += setup.h
-generic-y += shmbuf.h
-generic-y += shmparam.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += termbits.h
-generic-y += termios.h
-generic-y += types.h
-generic-y += ucontext.h
diff --git a/arch/blackfin/include/uapi/asm/bfin_sport.h b/arch/blackfin/include/uapi/asm/bfin_sport.h
deleted file mode 100644
index 86c36a208dc5..000000000000
--- a/arch/blackfin/include/uapi/asm/bfin_sport.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * bfin_sport.h - interface to Blackfin SPORTs
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_SPORT_H__
-#define _UAPI__BFIN_SPORT_H__
-
-/* Sport mode: it can be set to TDM, i2s or others */
-#define NORM_MODE 0x0
-#define TDM_MODE 0x1
-#define I2S_MODE 0x2
-#define NDSO_MODE 0x3
-
-/* Data format, normal, a-law or u-law */
-#define NORM_FORMAT 0x0
-#define ALAW_FORMAT 0x2
-#define ULAW_FORMAT 0x3
-
-/* Function driver which use sport must initialize the structure */
-struct sport_config {
- /* TDM (multichannels), I2S or other mode */
- unsigned int mode:3;
- unsigned int polled; /* use poll instead of irq when set */
-
- /* if TDM mode is selected, channels must be set */
- int channels; /* Must be in 8 units */
- unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
-
- /* I2S mode */
- unsigned int right_first:1; /* Right stereo channel first */
-
- /* In mormal mode, the following item need to be set */
- unsigned int lsb_first:1; /* order of transmit or receive data */
- unsigned int fsync:1; /* Frame sync required */
- unsigned int data_indep:1; /* data independent frame sync generated */
- unsigned int act_low:1; /* Active low TFS */
- unsigned int late_fsync:1; /* Late frame sync */
- unsigned int tckfe:1;
- unsigned int sec_en:1; /* Secondary side enabled */
-
- /* Choose clock source */
- unsigned int int_clk:1; /* Internal or external clock */
-
- /* If external clock is used, the following fields are ignored */
- int serial_clk;
- int fsync_clk;
-
- unsigned int data_format:2; /* Normal, u-law or a-law */
-
- int word_len; /* How length of the word in bits, 3-32 bits */
- int dma_enabled;
-};
-
-/* Userspace interface */
-#define SPORT_IOC_MAGIC 'P'
-#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
-#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long)
-#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long)
-
-
-/* SPORT_TCR1 Masks */
-#define TSPEN 0x0001 /* TX enable */
-#define ITCLK 0x0002 /* Internal TX Clock Select */
-#define TDTYPE 0x000C /* TX Data Formatting Select */
-#define DTYPE_NORM 0x0000 /* Data Format Normal */
-#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
-#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
-#define TLSBIT 0x0010 /* TX Bit Order */
-#define ITFS 0x0200 /* Internal TX Frame Sync Select */
-#define TFSR 0x0400 /* TX Frame Sync Required Select */
-#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
-#define LTFS 0x1000 /* Low TX Frame Sync Select */
-#define LATFS 0x2000 /* Late TX Frame Sync Select */
-#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
-
-/* SPORT_TCR2 Masks */
-#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
-#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
-#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
-#define TXSE 0x0100 /* TX Secondary Enable */
-#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
-#define TRFST 0x0400 /* TX Right-First Data Order */
-
-/* SPORT_RCR1 Masks */
-#define RSPEN 0x0001 /* RX enable */
-#define IRCLK 0x0002 /* Internal RX Clock Select */
-#define RDTYPE 0x000C /* RX Data Formatting Select */
-/* DTYPE_* defined above */
-#define RLSBIT 0x0010 /* RX Bit Order */
-#define IRFS 0x0200 /* Internal RX Frame Sync Select */
-#define RFSR 0x0400 /* RX Frame Sync Required Select */
-#define LRFS 0x1000 /* Low RX Frame Sync Select */
-#define LARFS 0x2000 /* Late RX Frame Sync Select */
-#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
-
-/* SPORT_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE 0x0100 /* RX Secondary Enable */
-#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
-#define RRFST 0x0400 /* Right-First Data Order */
-
-/* SPORT_STAT Masks */
-#define RXNE 0x0001 /* RX FIFO Not Empty Status */
-#define RUVF 0x0002 /* RX Underflow Status */
-#define ROVF 0x0004 /* RX Overflow Status */
-#define TXF 0x0008 /* TX FIFO Full Status */
-#define TUVF 0x0010 /* TX Underflow Status */
-#define TOVF 0x0020 /* TX Overflow Status */
-#define TXHRE 0x0040 /* TX Hold Register Empty */
-
-/* SPORT_MCMC1 Masks */
-#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
-#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
-#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
-#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
-#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
-#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
-
-/* SPORT_MCMC2 Masks */
-#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
-#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
-#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
-#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
-#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
-#define MFD 0xF000 /* Multichannel Frame Delay */
-#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
-#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
-
-#endif /* _UAPI__BFIN_SPORT_H__ */
diff --git a/arch/blackfin/include/uapi/asm/byteorder.h b/arch/blackfin/include/uapi/asm/byteorder.h
deleted file mode 100644
index bcab6670c7fe..000000000000
--- a/arch/blackfin/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__BFIN_ASM_BYTEORDER_H
-#define _UAPI__BFIN_ASM_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _UAPI__BFIN_ASM_BYTEORDER_H */
diff --git a/arch/blackfin/include/uapi/asm/cachectl.h b/arch/blackfin/include/uapi/asm/cachectl.h
deleted file mode 100644
index b5c86fbbca94..000000000000
--- a/arch/blackfin/include/uapi/asm/cachectl.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * based on the mips/cachectl.h
- *
- * Copyright 2010 Analog Devices Inc.
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_CACHECTL
-#define _UAPI_ASM_CACHECTL
-
-/*
- * Options for cacheflush system call
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-#endif /* _UAPI_ASM_CACHECTL */
diff --git a/arch/blackfin/include/uapi/asm/fcntl.h b/arch/blackfin/include/uapi/asm/fcntl.h
deleted file mode 100644
index 0b02954f06c3..000000000000
--- a/arch/blackfin/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_FCNTL_H
-#define _UAPI_BFIN_FCNTL_H
-
-#define O_DIRECTORY 040000 /* must be a directory */
-#define O_NOFOLLOW 0100000 /* don't follow links */
-#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE 0400000
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _UAPI_BFIN_FCNTL_H */
diff --git a/arch/blackfin/include/uapi/asm/fixed_code.h b/arch/blackfin/include/uapi/asm/fixed_code.h
deleted file mode 100644
index 707b9214bb26..000000000000
--- a/arch/blackfin/include/uapi/asm/fixed_code.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * This file defines the fixed addresses where userspace programs
- * can find atomic code sequences.
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__BFIN_ASM_FIXED_CODE_H__
-#define _UAPI__BFIN_ASM_FIXED_CODE_H__
-
-
-#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
-#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
-#endif
-
-#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-
-#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-
-#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
-#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
-#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
-#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
-#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
-#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
-
-#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-
-#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
-
-#endif /* _UAPI__BFIN_ASM_FIXED_CODE_H__ */
diff --git a/arch/blackfin/include/uapi/asm/ioctls.h b/arch/blackfin/include/uapi/asm/ioctls.h
deleted file mode 100644
index 422fee3e4776..000000000000
--- a/arch/blackfin/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI__ARCH_BFIN_IOCTLS_H__
-#define _UAPI__ARCH_BFIN_IOCTLS_H__
-
-#define FIOQSIZE 0x545E
-#include <asm-generic/ioctls.h>
-
-#endif /* _UAPI__ARCH_BFIN_IOCTLS_H__ */
diff --git a/arch/blackfin/include/uapi/asm/poll.h b/arch/blackfin/include/uapi/asm/poll.h
deleted file mode 100644
index cd2f1a78aba5..000000000000
--- a/arch/blackfin/include/uapi/asm/poll.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#ifndef _UAPI__BFIN_POLL_H
-#define _UAPI__BFIN_POLL_H
-
-#define POLLWRNORM POLLOUT
-#define POLLWRBAND 256
-
-#include <asm-generic/poll.h>
-
-#endif /* _UAPI__BFIN_POLL_H */
diff --git a/arch/blackfin/include/uapi/asm/posix_types.h b/arch/blackfin/include/uapi/asm/posix_types.h
deleted file mode 100644
index 8947c75cf638..000000000000
--- a/arch/blackfin/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ARCH_BFIN_POSIX_TYPES_H
-#define _UAPI__ARCH_BFIN_POSIX_TYPES_H
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned int __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-#define __kernel_size_t __kernel_size_t
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-#define __kernel_old_uid_t __kernel_old_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _UAPI__ARCH_BFIN_POSIX_TYPES_H */
diff --git a/arch/blackfin/include/uapi/asm/ptrace.h b/arch/blackfin/include/uapi/asm/ptrace.h
deleted file mode 100644
index e4423d5560da..000000000000
--- a/arch/blackfin/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_PTRACE_H
-#define _UAPI_BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- * 0 - 7 are data registers R0-R7
- * 8 - 15 are address registers P0-P7
- * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- * 32 - 33 A registers A0 & A1
- * 34 - status register
- * -----------------------------
- *
- * We follows above, except:
- * 32-33 --- Low 32-bit of A0&1
- * 34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-struct pt_regs {
- long orig_pc;
- long ipend;
- long seqstat;
- long rete;
- long retn;
- long retx;
- long pc; /* PC == RETI */
- long rets;
- long reserved; /* Used as scratch during system calls */
- long astat;
- long lb1;
- long lb0;
- long lt1;
- long lt0;
- long lc1;
- long lc0;
- long a1w;
- long a1x;
- long a0w;
- long a0x;
- long b3;
- long b2;
- long b1;
- long b0;
- long l3;
- long l2;
- long l1;
- long l0;
- long m3;
- long m2;
- long m1;
- long m0;
- long i3;
- long i2;
- long i1;
- long i0;
- long usp;
- long fp;
- long p5;
- long p4;
- long p3;
- long p2;
- long p1;
- long p0;
- long r7;
- long r6;
- long r5;
- long r4;
- long r3;
- long r2;
- long r1;
- long r0;
- long orig_r0;
- long orig_p0;
- long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13 /* ptrace signal */
-
-#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
-#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
-
-#define PS_S (0x0002)
-
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_ORIG_R0 208
-#define PT_ORIG_P0 212
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#define PT_LAST_PSEUDO PT_FDPIC_INTERP
-
-#endif /* _UAPI_BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/uapi/asm/sigcontext.h b/arch/blackfin/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 66b4d32af89c..000000000000
--- a/arch/blackfin/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-#define _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
-
-/* Add new entries at the end of the structure only. */
-struct sigcontext {
- unsigned long sc_r0;
- unsigned long sc_r1;
- unsigned long sc_r2;
- unsigned long sc_r3;
- unsigned long sc_r4;
- unsigned long sc_r5;
- unsigned long sc_r6;
- unsigned long sc_r7;
- unsigned long sc_p0;
- unsigned long sc_p1;
- unsigned long sc_p2;
- unsigned long sc_p3;
- unsigned long sc_p4;
- unsigned long sc_p5;
- unsigned long sc_usp;
- unsigned long sc_a0w;
- unsigned long sc_a1w;
- unsigned long sc_a0x;
- unsigned long sc_a1x;
- unsigned long sc_astat;
- unsigned long sc_rets;
- unsigned long sc_pc;
- unsigned long sc_retx;
- unsigned long sc_fp;
- unsigned long sc_i0;
- unsigned long sc_i1;
- unsigned long sc_i2;
- unsigned long sc_i3;
- unsigned long sc_m0;
- unsigned long sc_m1;
- unsigned long sc_m2;
- unsigned long sc_m3;
- unsigned long sc_l0;
- unsigned long sc_l1;
- unsigned long sc_l2;
- unsigned long sc_l3;
- unsigned long sc_b0;
- unsigned long sc_b1;
- unsigned long sc_b2;
- unsigned long sc_b3;
- unsigned long sc_lc0;
- unsigned long sc_lc1;
- unsigned long sc_lt0;
- unsigned long sc_lt1;
- unsigned long sc_lb0;
- unsigned long sc_lb1;
- unsigned long sc_seqstat;
-};
-
-#endif /* _UAPI_ASM_BLACKFIN_SIGCONTEXT_H */
diff --git a/arch/blackfin/include/uapi/asm/siginfo.h b/arch/blackfin/include/uapi/asm/siginfo.h
deleted file mode 100644
index 2dd8c9c39248..000000000000
--- a/arch/blackfin/include/uapi/asm/siginfo.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BFIN_SIGINFO_H
-#define _UAPI_BFIN_SIGINFO_H
-
-#include <linux/types.h>
-#include <asm-generic/siginfo.h>
-
-#define si_uid16 _sifields._kill._uid
-
-#endif /* _UAPI_BFIN_SIGINFO_H */
diff --git a/arch/blackfin/include/uapi/asm/signal.h b/arch/blackfin/include/uapi/asm/signal.h
deleted file mode 100644
index f8e3b99ba0a2..000000000000
--- a/arch/blackfin/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_BLACKFIN_SIGNAL_H
-#define _UAPI_BLACKFIN_SIGNAL_H
-
-#define SA_RESTORER 0x04000000
-#include <asm-generic/signal.h>
-
-#endif /* _UAPI_BLACKFIN_SIGNAL_H */
diff --git a/arch/blackfin/include/uapi/asm/stat.h b/arch/blackfin/include/uapi/asm/stat.h
deleted file mode 100644
index 458959d1a5ec..000000000000
--- a/arch/blackfin/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _UAPI_BFIN_STAT_H
-#define _UAPI_BFIN_STAT_H
-
-struct stat {
- unsigned short st_dev;
- unsigned short __pad1;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned short __pad2;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long __unused1;
- unsigned long st_mtime;
- unsigned long __unused2;
- unsigned long st_ctime;
- unsigned long __unused3;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad1[4];
-
-#define STAT64_HAS_BROKEN_ST_INO 1
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad2[4];
-
- long long st_size;
- unsigned long st_blksize;
-
- long long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
-
- unsigned long long st_ino;
-};
-
-#endif /* _UAPI_BFIN_STAT_H */
diff --git a/arch/blackfin/include/uapi/asm/swab.h b/arch/blackfin/include/uapi/asm/swab.h
deleted file mode 100644
index d3437933b95f..000000000000
--- a/arch/blackfin/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI_BLACKFIN_SWAB_H
-#define _UAPI_BLACKFIN_SWAB_H
-
-#include <linux/types.h>
-#include <asm-generic/swab.h>
-
-#ifdef __GNUC__
-
-static __inline__ __attribute_const__ __u32 __arch_swahb32(__u32 xx)
-{
- __u32 tmp;
- __asm__("%1 = %0 >> 8 (V);\n\t"
- "%0 = %0 << 8 (V);\n\t"
- "%0 = %0 | %1;\n\t"
- : "+d"(xx), "=&d"(tmp));
- return xx;
-}
-#define __arch_swahb32 __arch_swahb32
-
-static __inline__ __attribute_const__ __u32 __arch_swahw32(__u32 xx)
-{
- __u32 rv;
- __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
- return rv;
-}
-#define __arch_swahw32 __arch_swahw32
-
-static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 xx)
-{
- return __arch_swahb32(__arch_swahw32(xx));
-}
-#define __arch_swab32 __arch_swab32
-
-static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx)
-{
- __u32 xw = xx;
- __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
- return (__u16)xw;
-}
-#define __arch_swab16 __arch_swab16
-
-#endif /* __GNUC__ */
-
-#endif /* _UAPI_BLACKFIN_SWAB_H */
diff --git a/arch/blackfin/include/uapi/asm/unistd.h b/arch/blackfin/include/uapi/asm/unistd.h
deleted file mode 100644
index 2d392c09323c..000000000000
--- a/arch/blackfin/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _UAPI__ASM_BFIN_UNISTD_H
-#define _UAPI__ASM_BFIN_UNISTD_H
-/*
- * This file contains the system call numbers.
- */
-#define __NR_restart_syscall 0
-#define __NR_exit 1
- /* 2 __NR_fork not supported on nommu */
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
- /* 7 __NR_waitpid obsolete */
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_chown 16
- /* 17 __NR_break obsolete */
- /* 18 __NR_oldstat obsolete */
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
- /* 22 __NR_umount obsolete */
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
- /* 28 __NR_oldfstat obsolete */
-#define __NR_pause 29
- /* 30 __NR_utime obsolete */
- /* 31 __NR_stty obsolete */
- /* 32 __NR_gtty obsolete */
-#define __NR_access 33
-#define __NR_nice 34
- /* 35 __NR_ftime obsolete */
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
- /* 44 __NR_prof obsolete */
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
- /* 48 __NR_signal obsolete */
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
- /* 53 __NR_lock obsolete */
-#define __NR_ioctl 54
-#define __NR_fcntl 55
- /* 56 __NR_mpx obsolete */
-#define __NR_setpgid 57
- /* 58 __NR_ulimit obsolete */
- /* 59 __NR_oldolduname obsolete */
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
- /* 67 __NR_sigaction obsolete */
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
- /* 72 __NR_sigsuspend obsolete */
- /* 73 __NR_sigpending obsolete */
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
- /* 76 __NR_old_getrlimit obsolete */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
- /* 82 __NR_select obsolete */
-#define __NR_symlink 83
- /* 84 __NR_oldlstat obsolete */
-#define __NR_readlink 85
- /* 86 __NR_uselib obsolete */
- /* 87 __NR_swapon obsolete */
-#define __NR_reboot 88
- /* 89 __NR_readdir obsolete */
- /* 90 __NR_mmap obsolete */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
- /* 98 __NR_profil obsolete */
-#define __NR_statfs 99
-#define __NR_fstatfs 100
- /* 101 __NR_ioperm */
- /* 102 __NR_socketcall obsolete */
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
- /* 109 __NR_olduname obsolete */
- /* 110 __NR_iopl obsolete */
-#define __NR_vhangup 111
- /* 112 __NR_idle obsolete */
- /* 113 __NR_vm86old */
-#define __NR_wait4 114
- /* 115 __NR_swapoff obsolete */
-#define __NR_sysinfo 116
- /* 117 __NR_ipc oboslete */
-#define __NR_fsync 118
- /* 119 __NR_sigreturn obsolete */
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
- /* 123 __NR_modify_ldt obsolete */
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
- /* 126 __NR_sigprocmask obsolete */
- /* 127 __NR_create_module obsolete */
-#define __NR_init_module 128
-#define __NR_delete_module 129
- /* 130 __NR_get_kernel_syms obsolete */
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
- /* 135 was sysfs */
-#define __NR_personality 136
- /* 137 __NR_afs_syscall */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
- /* 142 __NR__newselect obsolete */
-#define __NR_flock 143
- /* 144 __NR_msync obsolete */
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
- /* 150 __NR_mlock */
- /* 151 __NR_munlock */
- /* 152 __NR_mlockall */
- /* 153 __NR_munlockall */
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
- /* 166 __NR_vm86 */
- /* 167 __NR_query_module */
- /* 168 __NR_poll */
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread 180
-#define __NR_pwrite 181
-#define __NR_lchown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
- /* 188 __NR_getpmsg */
- /* 189 __NR_putpmsg */
-#define __NR_vfork 190
-#define __NR_getrlimit 191
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_chown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_lchown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
- /* 218 __NR_mincore */
- /* 219 __NR_madvise */
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
- /* 222 reserved for TUX */
- /* 223 reserved for TUX */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
- /* 243 __NR_set_thread_area */
- /* 244 __NR_get_thread_area */
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
- /* 250 __NR_alloc_hugepages */
- /* 251 __NR_free_hugepages */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_bfin_spinlock 254
-
-#define __NR_epoll_create 255
-#define __NR_epoll_ctl 256
-#define __NR_epoll_wait 257
- /* 258 __NR_remap_file_pages */
-#define __NR_set_tid_address 259
-#define __NR_timer_create 260
-#define __NR_timer_settime 261
-#define __NR_timer_gettime 262
-#define __NR_timer_getoverrun 263
-#define __NR_timer_delete 264
-#define __NR_clock_settime 265
-#define __NR_clock_gettime 266
-#define __NR_clock_getres 267
-#define __NR_clock_nanosleep 268
-#define __NR_statfs64 269
-#define __NR_fstatfs64 270
-#define __NR_tgkill 271
-#define __NR_utimes 272
-#define __NR_fadvise64_64 273
- /* 274 __NR_vserver */
- /* 275 __NR_mbind */
- /* 276 __NR_get_mempolicy */
- /* 277 __NR_set_mempolicy */
-#define __NR_mq_open 278
-#define __NR_mq_unlink 279
-#define __NR_mq_timedsend 280
-#define __NR_mq_timedreceive 281
-#define __NR_mq_notify 282
-#define __NR_mq_getsetattr 283
-#define __NR_kexec_load 284
-#define __NR_waitid 285
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
- /* 294 __NR_migrate_pages */
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-
-/* Blackfin private syscalls */
-#define __NR_sram_alloc 311
-#define __NR_sram_free 312
-#define __NR_dma_memcpy 313
-
-/* socket syscalls */
-#define __NR_accept 314
-#define __NR_bind 315
-#define __NR_connect 316
-#define __NR_getpeername 317
-#define __NR_getsockname 318
-#define __NR_getsockopt 319
-#define __NR_listen 320
-#define __NR_recv 321
-#define __NR_recvfrom 322
-#define __NR_recvmsg 323
-#define __NR_send 324
-#define __NR_sendmsg 325
-#define __NR_sendto 326
-#define __NR_setsockopt 327
-#define __NR_shutdown 328
-#define __NR_socket 329
-#define __NR_socketpair 330
-
-/* sysv ipc syscalls */
-#define __NR_semctl 331
-#define __NR_semget 332
-#define __NR_semop 333
-#define __NR_msgctl 334
-#define __NR_msgget 335
-#define __NR_msgrcv 336
-#define __NR_msgsnd 337
-#define __NR_shmat 338
-#define __NR_shmctl 339
-#define __NR_shmdt 340
-#define __NR_shmget 341
-
-#define __NR_splice 342
-#define __NR_sync_file_range 343
-#define __NR_tee 344
-#define __NR_vmsplice 345
-
-#define __NR_epoll_pwait 346
-#define __NR_utimensat 347
-#define __NR_signalfd 348
-#define __NR_timerfd_create 349
-#define __NR_eventfd 350
-#define __NR_pread64 351
-#define __NR_pwrite64 352
-#define __NR_fadvise64 353
-#define __NR_set_robust_list 354
-#define __NR_get_robust_list 355
-#define __NR_fallocate 356
-#define __NR_semtimedop 357
-#define __NR_timerfd_settime 358
-#define __NR_timerfd_gettime 359
-#define __NR_signalfd4 360
-#define __NR_eventfd2 361
-#define __NR_epoll_create1 362
-#define __NR_dup3 363
-#define __NR_pipe2 364
-#define __NR_inotify_init1 365
-#define __NR_preadv 366
-#define __NR_pwritev 367
-#define __NR_rt_tgsigqueueinfo 368
-#define __NR_perf_event_open 369
-#define __NR_recvmmsg 370
-#define __NR_fanotify_init 371
-#define __NR_fanotify_mark 372
-#define __NR_prlimit64 373
-#define __NR_cacheflush 374
-#define __NR_name_to_handle_at 375
-#define __NR_open_by_handle_at 376
-#define __NR_clock_adjtime 377
-#define __NR_syncfs 378
-#define __NR_setns 379
-#define __NR_sendmmsg 380
-#define __NR_process_vm_readv 381
-#define __NR_process_vm_writev 382
-#define __NR_kcmp 383
-#define __NR_finit_module 384
-#define __NR_sched_setattr 385
-#define __NR_sched_getattr 386
-#define __NR_renameat2 387
-#define __NR_seccomp 388
-#define __NR_getrandom 389
-#define __NR_memfd_create 390
-#define __NR_bpf 391
-#define __NR_execveat 392
-
-#define __NR_syscall 393 /* For internal using, not implemented */
-#define NR_syscalls __NR_syscall
-
-/* Old optional stuff no one actually uses */
-#define __IGNORE_sysfs
-#define __IGNORE_uselib
-
-/* Implement the newer interfaces */
-#define __IGNORE_mmap
-#define __IGNORE_poll
-#define __IGNORE_select
-#define __IGNORE_utime
-
-/* Not relevant on no-mmu */
-#define __IGNORE_swapon
-#define __IGNORE_swapoff
-#define __IGNORE_msync
-#define __IGNORE_mlock
-#define __IGNORE_munlock
-#define __IGNORE_mlockall
-#define __IGNORE_munlockall
-#define __IGNORE_mincore
-#define __IGNORE_madvise
-#define __IGNORE_remap_file_pages
-#define __IGNORE_mbind
-#define __IGNORE_get_mempolicy
-#define __IGNORE_set_mempolicy
-#define __IGNORE_migrate_pages
-#define __IGNORE_move_pages
-#define __IGNORE_getcpu
-
-
-#endif /* _UAPI__ASM_BFIN_UNISTD_H */
diff --git a/arch/blackfin/kernel/.gitignore b/arch/blackfin/kernel/.gitignore
deleted file mode 100644
index c5f676c3c224..000000000000
--- a/arch/blackfin/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
deleted file mode 100644
index 1580791f0e3a..000000000000
--- a/arch/blackfin/kernel/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/Makefile
-#
-
-extra-y := vmlinux.lds
-
-obj-y := \
- entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
- sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
- fixed_code.o reboot.o bfin_dma.o \
- exception.o dumpstack.o
-
-ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
- obj-y += time-ts.o
-else
- obj-y += time.o
-endif
-
-obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
-obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
-obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
-obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
-CFLAGS_REMOVE_ftrace.o = -pg
-
-obj-$(CONFIG_IPIPE) += ipipe.o
-obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
-obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_KGDB) += kgdb.o
-obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
-obj-$(CONFIG_NMI_WATCHDOG) += nmi.o
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o
-obj-$(CONFIG_STACKTRACE) += stacktrace.o
-obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
-obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
-obj-$(CONFIG_PERF_EVENTS) += perf_event.o
-
-# the kgdb test puts code into L2 and without linker
-# relaxation, we need to force long calls to/from it
-CFLAGS_kgdb_test.o := -mlong-calls
-
-obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
deleted file mode 100644
index 486560aea050..000000000000
--- a/arch/blackfin/kernel/asm-offsets.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * generate definitions needed by assembly language modules
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/irq.h>
-#include <linux/thread_info.h>
-#include <linux/kbuild.h>
-#include <asm/pda.h>
-
-int main(void)
-{
- /* offsets into the task struct */
- DEFINE(TASK_STATE, offsetof(struct task_struct, state));
- DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
- DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
- DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked));
- DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
- DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack));
- DEFINE(TASK_MM, offsetof(struct task_struct, mm));
- DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
- DEFINE(TASK_SIGPENDING, offsetof(struct task_struct, pending));
-
- /* offsets into the irq_cpustat_t struct */
- DEFINE(CPUSTAT_SOFTIRQ_PENDING,
- offsetof(irq_cpustat_t, __softirq_pending));
-
- /* offsets into the thread struct */
- DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
- DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
- DEFINE(THREAD_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(PT_SR, offsetof(struct thread_struct, seqstat));
- DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
- DEFINE(THREAD_PC, offsetof(struct thread_struct, pc));
- DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
-
- /* offsets in thread_info struct */
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PREEMPT, thread_info, preempt_count);
-
- /* offsets into the pt_regs */
- DEFINE(PT_ORIG_R0, offsetof(struct pt_regs, orig_r0));
- DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0));
- DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc));
- DEFINE(PT_R0, offsetof(struct pt_regs, r0));
- DEFINE(PT_R1, offsetof(struct pt_regs, r1));
- DEFINE(PT_R2, offsetof(struct pt_regs, r2));
- DEFINE(PT_R3, offsetof(struct pt_regs, r3));
- DEFINE(PT_R4, offsetof(struct pt_regs, r4));
- DEFINE(PT_R5, offsetof(struct pt_regs, r5));
- DEFINE(PT_R6, offsetof(struct pt_regs, r6));
- DEFINE(PT_R7, offsetof(struct pt_regs, r7));
-
- DEFINE(PT_P0, offsetof(struct pt_regs, p0));
- DEFINE(PT_P1, offsetof(struct pt_regs, p1));
- DEFINE(PT_P2, offsetof(struct pt_regs, p2));
- DEFINE(PT_P3, offsetof(struct pt_regs, p3));
- DEFINE(PT_P4, offsetof(struct pt_regs, p4));
- DEFINE(PT_P5, offsetof(struct pt_regs, p5));
-
- DEFINE(PT_FP, offsetof(struct pt_regs, fp));
- DEFINE(PT_USP, offsetof(struct pt_regs, usp));
- DEFINE(PT_I0, offsetof(struct pt_regs, i0));
- DEFINE(PT_I1, offsetof(struct pt_regs, i1));
- DEFINE(PT_I2, offsetof(struct pt_regs, i2));
- DEFINE(PT_I3, offsetof(struct pt_regs, i3));
- DEFINE(PT_M0, offsetof(struct pt_regs, m0));
- DEFINE(PT_M1, offsetof(struct pt_regs, m1));
- DEFINE(PT_M2, offsetof(struct pt_regs, m2));
- DEFINE(PT_M3, offsetof(struct pt_regs, m3));
- DEFINE(PT_L0, offsetof(struct pt_regs, l0));
- DEFINE(PT_L1, offsetof(struct pt_regs, l1));
- DEFINE(PT_L2, offsetof(struct pt_regs, l2));
- DEFINE(PT_L3, offsetof(struct pt_regs, l3));
- DEFINE(PT_B0, offsetof(struct pt_regs, b0));
- DEFINE(PT_B1, offsetof(struct pt_regs, b1));
- DEFINE(PT_B2, offsetof(struct pt_regs, b2));
- DEFINE(PT_B3, offsetof(struct pt_regs, b3));
- DEFINE(PT_A0X, offsetof(struct pt_regs, a0x));
- DEFINE(PT_A0W, offsetof(struct pt_regs, a0w));
- DEFINE(PT_A1X, offsetof(struct pt_regs, a1x));
- DEFINE(PT_A1W, offsetof(struct pt_regs, a1w));
- DEFINE(PT_LC0, offsetof(struct pt_regs, lc0));
- DEFINE(PT_LC1, offsetof(struct pt_regs, lc1));
- DEFINE(PT_LT0, offsetof(struct pt_regs, lt0));
- DEFINE(PT_LT1, offsetof(struct pt_regs, lt1));
- DEFINE(PT_LB0, offsetof(struct pt_regs, lb0));
- DEFINE(PT_LB1, offsetof(struct pt_regs, lb1));
- DEFINE(PT_ASTAT, offsetof(struct pt_regs, astat));
- DEFINE(PT_RESERVED, offsetof(struct pt_regs, reserved));
- DEFINE(PT_RETS, offsetof(struct pt_regs, rets));
- DEFINE(PT_PC, offsetof(struct pt_regs, pc));
- DEFINE(PT_RETX, offsetof(struct pt_regs, retx));
- DEFINE(PT_RETN, offsetof(struct pt_regs, retn));
- DEFINE(PT_RETE, offsetof(struct pt_regs, rete));
- DEFINE(PT_SEQSTAT, offsetof(struct pt_regs, seqstat));
- DEFINE(PT_SYSCFG, offsetof(struct pt_regs, syscfg));
- DEFINE(PT_IPEND, offsetof(struct pt_regs, ipend));
- DEFINE(SIZEOF_PTREGS, sizeof(struct pt_regs));
- DEFINE(PT_TEXT_ADDR, sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_TEXT_END_ADDR, 4 + sizeof(struct pt_regs));/* Needed by gdb */
- DEFINE(PT_DATA_ADDR, 8 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_EXEC, 12 + sizeof(struct pt_regs)); /* Needed by gdb */
- DEFINE(PT_FDPIC_INTERP, 16 + sizeof(struct pt_regs));/* Needed by gdb */
-
- /* signal defines */
- DEFINE(SIGSEGV, SIGSEGV);
- DEFINE(SIGTRAP, SIGTRAP);
-
- /* PDA management (in L1 scratchpad) */
- DEFINE(PDA_SYSCFG, offsetof(struct blackfin_pda, syscfg));
-#ifdef CONFIG_SMP
- DEFINE(PDA_IRQFLAGS, offsetof(struct blackfin_pda, imask));
-#endif
- DEFINE(PDA_IPDT, offsetof(struct blackfin_pda, ipdt));
- DEFINE(PDA_IPDT_SWAPCOUNT, offsetof(struct blackfin_pda, ipdt_swapcount));
- DEFINE(PDA_DPDT, offsetof(struct blackfin_pda, dpdt));
- DEFINE(PDA_DPDT_SWAPCOUNT, offsetof(struct blackfin_pda, dpdt_swapcount));
- DEFINE(PDA_EXIPTR, offsetof(struct blackfin_pda, ex_iptr));
- DEFINE(PDA_EXOPTR, offsetof(struct blackfin_pda, ex_optr));
- DEFINE(PDA_EXBUF, offsetof(struct blackfin_pda, ex_buf));
- DEFINE(PDA_EXIMASK, offsetof(struct blackfin_pda, ex_imask));
- DEFINE(PDA_EXSTACK, offsetof(struct blackfin_pda, ex_stack));
- DEFINE(PDA_EXIPEND, offsetof(struct blackfin_pda, ex_ipend));
-#ifdef ANOMALY_05000261
- DEFINE(PDA_LFRETX, offsetof(struct blackfin_pda, last_cplb_fault_retx));
-#endif
- DEFINE(PDA_DCPLB, offsetof(struct blackfin_pda, dcplb_fault_addr));
- DEFINE(PDA_ICPLB, offsetof(struct blackfin_pda, icplb_fault_addr));
- DEFINE(PDA_RETX, offsetof(struct blackfin_pda, retx));
- DEFINE(PDA_SEQSTAT, offsetof(struct blackfin_pda, seqstat));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_DF_DCPLB, offsetof(struct blackfin_pda, dcplb_doublefault_addr));
- DEFINE(PDA_DF_ICPLB, offsetof(struct blackfin_pda, icplb_doublefault_addr));
- DEFINE(PDA_DF_SEQSTAT, offsetof(struct blackfin_pda, seqstat_doublefault));
- DEFINE(PDA_DF_RETX, offsetof(struct blackfin_pda, retx_doublefault));
-#endif
-
- /* PDA initial management */
- DEFINE(PDA_INIT_RETX, offsetof(struct blackfin_initial_pda, retx));
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- DEFINE(PDA_INIT_DF_DCPLB, offsetof(struct blackfin_initial_pda, dcplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_ICPLB, offsetof(struct blackfin_initial_pda, icplb_doublefault_addr));
- DEFINE(PDA_INIT_DF_SEQSTAT, offsetof(struct blackfin_initial_pda, seqstat_doublefault));
- DEFINE(PDA_INIT_DF_RETX, offsetof(struct blackfin_initial_pda, retx_doublefault));
-#endif
-
-#ifdef CONFIG_SMP
- /* Inter-core lock (in L2 SRAM) */
- DEFINE(SIZEOF_CORELOCK, sizeof(struct corelock_slot));
-#endif
-
- return 0;
-}
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
deleted file mode 100644
index 9d3eb0cf8ccc..000000000000
--- a/arch/blackfin/kernel/bfin_dma.c
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
- * bfin_dma.c - Blackfin DMA implementation
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/proc_fs.h>
-#include <linux/sched.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <linux/uaccess.h>
-#include <asm/early_printk.h>
-
-/*
- * To make sure we work around 05000119 - we always check DMA_DONE bit,
- * never the DMA_RUN bit
- */
-
-struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-EXPORT_SYMBOL(dma_ch);
-
-static int __init blackfin_dma_init(void)
-{
- int i;
-
- printk(KERN_INFO "Blackfin DMA Controller\n");
-
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-
- for (i = 0; i < MAX_DMA_CHANNELS; i++) {
- atomic_set(&dma_ch[i].chan_status, 0);
- dma_ch[i].regs = dma_io_base_addr[i];
- }
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
- /* Mark MEMDMA Channel 3 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
-#else
- /* Mark MEMDMA Channel 0 as requested since we're using it internally */
- request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
- request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
-#endif
-
-#if defined(CONFIG_DEB_DMA_URGENT)
- bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
- | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
-#endif
-
- return 0;
-}
-arch_initcall(blackfin_dma_init);
-
-#ifdef CONFIG_PROC_FS
-static int proc_dma_show(struct seq_file *m, void *v)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i)
- if (dma_channel_active(i))
- seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
-
- return 0;
-}
-
-static int proc_dma_open(struct inode *inode, struct file *file)
-{
- return single_open(file, proc_dma_show, NULL);
-}
-
-static const struct file_operations proc_dma_operations = {
- .open = proc_dma_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init proc_dma_init(void)
-{
- proc_create("dma", 0, NULL, &proc_dma_operations);
- return 0;
-}
-late_initcall(proc_dma_init);
-#endif
-
-static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
-{
-#ifdef CONFIG_BF54x
- unsigned int per_map;
-
- switch (channel) {
- case CH_UART2_RX: per_map = 0xC << 12; break;
- case CH_UART2_TX: per_map = 0xD << 12; break;
- case CH_UART3_RX: per_map = 0xE << 12; break;
- case CH_UART3_TX: per_map = 0xF << 12; break;
- default: return;
- }
-
- if (strncmp(device_id, "BFIN_UART", 9) == 0)
- dma_ch[channel].regs->peripheral_map = per_map;
-#endif
-}
-
-/**
- * request_dma - request a DMA channel
- *
- * Request the specific DMA channel from the system if it's available.
- */
-int request_dma(unsigned int channel, const char *device_id)
-{
- pr_debug("request_dma() : BEGIN\n");
-
- if (device_id == NULL)
- printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
-
-#if defined(CONFIG_BF561) && ANOMALY_05000182
- if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
- if (get_cclk() > 500000000) {
- printk(KERN_WARNING
- "Request IMDMA failed due to ANOMALY 05000182\n");
- return -EFAULT;
- }
- }
-#endif
-
- if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
- pr_debug("DMA CHANNEL IN USE\n");
- return -EBUSY;
- }
-
- set_dma_peripheral_map(channel, device_id);
- dma_ch[channel].device_id = device_id;
- dma_ch[channel].irq = 0;
-
- /* This is to be enabled by putting a restriction -
- * you have to request DMA, before doing any operations on
- * descriptor/channel
- */
- pr_debug("request_dma() : END\n");
- return 0;
-}
-EXPORT_SYMBOL(request_dma);
-
-int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
-{
- int ret;
- unsigned int irq;
-
- BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- irq = channel2irq(channel);
- ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
- if (ret)
- return ret;
-
- dma_ch[channel].irq = irq;
- dma_ch[channel].data = data;
-
- return 0;
-}
-EXPORT_SYMBOL(set_dma_callback);
-
-/**
- * clear_dma_buffer - clear DMA fifos for specified channel
- *
- * Set the Buffer Clear bit in the Configuration register of specific DMA
- * channel. This will stop the descriptor based DMA operation.
- */
-static void clear_dma_buffer(unsigned int channel)
-{
- dma_ch[channel].regs->cfg |= RESTART;
- SSYNC();
- dma_ch[channel].regs->cfg &= ~RESTART;
-}
-
-void free_dma(unsigned int channel)
-{
- pr_debug("freedma() : BEGIN\n");
- BUG_ON(channel >= MAX_DMA_CHANNELS ||
- !atomic_read(&dma_ch[channel].chan_status));
-
- /* Halt the DMA */
- disable_dma(channel);
- clear_dma_buffer(channel);
-
- if (dma_ch[channel].irq)
- free_irq(dma_ch[channel].irq, dma_ch[channel].data);
-
- /* Clear the DMA Variable in the Channel */
- atomic_set(&dma_ch[channel].chan_status, 0);
-
- pr_debug("freedma() : END\n");
-}
-EXPORT_SYMBOL(free_dma);
-
-#ifdef CONFIG_PM
-# ifndef MAX_DMA_SUSPEND_CHANNELS
-# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
-# endif
-# ifndef CONFIG_BF60x
-int blackfin_dma_suspend(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- if (dma_ch[i].regs->cfg & DMAEN) {
- printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
- return -EBUSY;
- }
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
- }
-
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0);
-#endif
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
- int i;
-
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- dma_ch[i].regs->cfg = 0;
- if (i < MAX_DMA_SUSPEND_CHANNELS)
- dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
- }
-#if ANOMALY_05000480
- bfin_write_DMAC_TC_PER(0x0111);
-#endif
-}
-# else
-int blackfin_dma_suspend(void)
-{
- return 0;
-}
-
-void blackfin_dma_resume(void)
-{
-}
-#endif
-#endif
-
-/**
- * blackfin_dma_early_init - minimal DMA init
- *
- * Setup a few DMA registers so we can safely do DMA transfers early on in
- * the kernel booting process. Really this just means using dma_memcpy().
- */
-void __init blackfin_dma_early_init(void)
-{
- early_shadow_stamp();
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
-}
-
-void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
- struct dma_register *dst_ch, *src_ch;
-
- early_shadow_stamp();
-
- /* We assume that everything is 4 byte aligned, so include
- * a basic sanity check
- */
- BUG_ON(dst % 4);
- BUG_ON(src % 4);
- BUG_ON(size % 4);
-
- src_ch = 0;
- /* Find an avalible memDMA channel */
- while (1) {
- if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
- dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
- } else {
- dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
- src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
- }
-
- if (!DMA_MMR_READ(&src_ch->cfg))
- break;
- else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
- DMA_MMR_WRITE(&src_ch->cfg, 0);
- break;
- }
- }
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted.
- */
- __builtin_bfin_ssync();
-
- /* Destination */
- bfin_write32(&dst_ch->start_addr, dst);
- DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Source */
- bfin_write32(&src_ch->start_addr, src);
- DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
- DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
- DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
-
- /* Enable */
- DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
- DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
-
- /* Since we are atomic now, don't use the workaround ssync */
- __builtin_bfin_ssync();
-
-#ifdef CONFIG_BF60x
- /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
- * transfer DDR data to L1 SRAM may corrupt data.
- * Should be reverted after this issue is root caused.
- */
- while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
- continue;
-#endif
-}
-
-void __init early_dma_memcpy_done(void)
-{
- early_shadow_stamp();
-
- while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
- (bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
- continue;
-
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
- bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
- /*
- * Now that DMA is done, we would normally flush cache, but
- * i/d cache isn't running this early, so we don't bother,
- * and just clear out the DMA channel for next time
- */
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_S1_CONFIG(0);
- bfin_write_MDMA_D0_CONFIG(0);
- bfin_write_MDMA_D1_CONFIG(0);
-
- __builtin_bfin_ssync();
-}
-
-#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
-#else
-#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
-#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
-#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
-#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
-#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
-#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
-#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
-#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
-#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
-#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
-#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
-#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
-#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
-#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
-#endif
-
-/**
- * __dma_memcpy - program the MDMA registers
- *
- * Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
- * while programming registers so that everything is fully configured. Wait
- * for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE
- * check will make sure we don't clobber any existing transfer.
- */
-static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
-{
- static DEFINE_SPINLOCK(mdma_lock);
- unsigned long flags;
-
- spin_lock_irqsave(&mdma_lock, flags);
-
- /* Force a sync in case a previous config reset on this channel
- * occurred. This is needed so subsequent writes to DMA registers
- * are not spuriously lost/corrupted. Do it under irq lock and
- * without the anomaly version (because we are atomic already).
- */
- __builtin_bfin_ssync();
-
- if (bfin_read_MDMA_S_CONFIG())
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- continue;
-
- if (conf & DMA2D) {
- /* For larger bit sizes, we've already divided down cnt so it
- * is no longer a multiple of 64k. So we have to break down
- * the limit here so it is a multiple of the incoming size.
- * There is no limitation here in terms of total size other
- * than the hardware though as the bits lost in the shift are
- * made up by MODIFY (== we can hit the whole address space).
- * X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
- */
- u32 shift = abs(dmod) >> 1;
- size_t ycnt = cnt >> (16 - shift);
- cnt = 1 << (16 - shift);
- bfin_write_MDMA_D_Y_COUNT(ycnt);
- bfin_write_MDMA_S_Y_COUNT(ycnt);
- bfin_write_MDMA_D_Y_MODIFY(dmod);
- bfin_write_MDMA_S_Y_MODIFY(smod);
- }
-
- bfin_write_MDMA_D_START_ADDR(daddr);
- bfin_write_MDMA_D_X_COUNT(cnt);
- bfin_write_MDMA_D_X_MODIFY(dmod);
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_START_ADDR(saddr);
- bfin_write_MDMA_S_X_COUNT(cnt);
- bfin_write_MDMA_S_X_MODIFY(smod);
- bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(DMAEN | conf);
- if (conf & DMA2D)
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
- else
- bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
-
- spin_unlock_irqrestore(&mdma_lock, flags);
-
- SSYNC();
-
- while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
- if (bfin_read_MDMA_S_CONFIG())
- continue;
- else
- return;
-
- bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
- bfin_write_MDMA_S_CONFIG(0);
- bfin_write_MDMA_D_CONFIG(0);
-}
-
-/**
- * _dma_memcpy - translate C memcpy settings into MDMA settings
- *
- * Handle all the high level steps before we touch the MDMA registers. So
- * handle direction, tweaking of sizes, and formatting of addresses.
- */
-static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- u32 conf, shift;
- s16 mod;
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (size == 0)
- return NULL;
-
- if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
- conf = WDSIZE_32;
- shift = 2;
- } else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
- conf = WDSIZE_16;
- shift = 1;
- } else {
- conf = WDSIZE_8;
- shift = 0;
- }
-
- /* If the two memory regions have a chance of overlapping, make
- * sure the memcpy still works as expected. Do this by having the
- * copy run backwards instead.
- */
- mod = 1 << shift;
- if (src < dst) {
- mod *= -1;
- dst += size + mod;
- src += size + mod;
- }
- size >>= shift;
-
-#ifndef DMA_MMR_SIZE_32
- if (size > 0x10000)
- conf |= DMA2D;
-#endif
-
- __dma_memcpy(dst, mod, src, mod, size, conf);
-
- return pdst;
-}
-
-/**
- * dma_memcpy - DMA memcpy under mutex lock
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy(void *pdst, const void *psrc, size_t size)
-{
- unsigned long dst = (unsigned long)pdst;
- unsigned long src = (unsigned long)psrc;
-
- if (bfin_addr_dcacheable(src))
- blackfin_dcache_flush_range(src, src + size);
-
- if (bfin_addr_dcacheable(dst))
- blackfin_dcache_invalidate_range(dst, dst + size);
-
- return dma_memcpy_nocache(pdst, psrc, size);
-}
-EXPORT_SYMBOL(dma_memcpy);
-
-/**
- * dma_memcpy_nocache - DMA memcpy under mutex lock
- * - No cache flush/invalidate
- *
- * Do not check arguments before starting the DMA memcpy. Break the transfer
- * up into two pieces. The first transfer is in multiples of 64k and the
- * second transfer is the piece smaller than 64k.
- */
-void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
-{
-#ifdef DMA_MMR_SIZE_32
- _dma_memcpy(pdst, psrc, size);
-#else
- size_t bulk, rest;
-
- bulk = size & ~0xffff;
- rest = size - bulk;
- if (bulk)
- _dma_memcpy(pdst, psrc, bulk);
- _dma_memcpy(pdst + bulk, psrc + bulk, rest);
-#endif
- return pdst;
-}
-EXPORT_SYMBOL(dma_memcpy_nocache);
-
-/**
- * safe_dma_memcpy - DMA memcpy w/argument checking
- *
- * Verify arguments are safe before heading to dma_memcpy().
- */
-void *safe_dma_memcpy(void *dst, const void *src, size_t size)
-{
- if (!access_ok(VERIFY_WRITE, dst, size))
- return NULL;
- if (!access_ok(VERIFY_READ, src, size))
- return NULL;
- return dma_memcpy(dst, src, size);
-}
-EXPORT_SYMBOL(safe_dma_memcpy);
-
-static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_flush_range(buf, buf + len * size);
- __dma_memcpy(addr, 0, buf, size, len, dma_size);
-}
-
-static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
- u16 size, u16 dma_size)
-{
- blackfin_dcache_invalidate_range(buf, buf + len * size);
- __dma_memcpy(buf, size, addr, 0, len, dma_size);
-}
-
-#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
-void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
-{ \
- _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
-} \
-EXPORT_SYMBOL(dma_##io##s##bwl)
-MAKE_DMA_IO(out, b, 1, 8, const);
-MAKE_DMA_IO(in, b, 1, 8, );
-MAKE_DMA_IO(out, w, 2, 16, const);
-MAKE_DMA_IO(in, w, 2, 16, );
-MAKE_DMA_IO(out, l, 4, 32, const);
-MAKE_DMA_IO(in, l, 4, 32, );
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
deleted file mode 100644
index 63da80bbadf6..000000000000
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ /dev/null
@@ -1,1208 +0,0 @@
-/*
- * GPIO Abstraction Layer
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/gpio/driver.h>
-/* FIXME: consumer API required for gpio_set_value() etc, get rid of this */
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <asm/gpio.h>
-#include <asm/irq_handler.h>
-#include <asm/portmux.h>
-
-#if ANOMALY_05000311 || ANOMALY_05000323
-enum {
- AWA_data = SYSCR,
- AWA_data_clear = SYSCR,
- AWA_data_set = SYSCR,
- AWA_toggle = SYSCR,
- AWA_maska = BFIN_UART_SCR,
- AWA_maska_clear = BFIN_UART_SCR,
- AWA_maska_set = BFIN_UART_SCR,
- AWA_maska_toggle = BFIN_UART_SCR,
- AWA_maskb = BFIN_UART_GCTL,
- AWA_maskb_clear = BFIN_UART_GCTL,
- AWA_maskb_set = BFIN_UART_GCTL,
- AWA_maskb_toggle = BFIN_UART_GCTL,
- AWA_dir = SPORT1_STAT,
- AWA_polar = SPORT1_STAT,
- AWA_edge = SPORT1_STAT,
- AWA_both = SPORT1_STAT,
-#if ANOMALY_05000311
- AWA_inen = TIMER_ENABLE,
-#elif ANOMALY_05000323
- AWA_inen = DMA1_1_CONFIG,
-#endif
-};
- /* Anomaly Workaround */
-#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
-#else
-#define AWA_DUMMY_READ(...) do { } while (0)
-#endif
-
-static struct gpio_port_t * const gpio_array[] = {
-#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
- (struct gpio_port_t *) FIO_FLAG_D,
-#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- (struct gpio_port_t *) PORTFIO,
- (struct gpio_port_t *) PORTGIO,
- (struct gpio_port_t *) PORTHIO,
-#elif defined(BF561_FAMILY)
- (struct gpio_port_t *) FIO0_FLAG_D,
- (struct gpio_port_t *) FIO1_FLAG_D,
- (struct gpio_port_t *) FIO2_FLAG_D,
-#else
-# error no gpio arrays defined
-#endif
-};
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTF_FER,
- (unsigned short *) PORTG_FER,
- (unsigned short *) PORTH_FER,
-};
-
-# if !defined(BF537_FAMILY)
-static unsigned short * const port_mux[] = {
- (unsigned short *) PORTF_MUX,
- (unsigned short *) PORTG_MUX,
- (unsigned short *) PORTH_MUX,
-};
-
-static const
-u8 pmux_offset[][16] = {
-# if defined(CONFIG_BF52x)
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
- { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
- { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
-# elif defined(CONFIG_BF51x)
- { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
- { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
- { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
-# endif
-};
-# endif
-
-#elif defined(BF538_FAMILY)
-static unsigned short * const port_fer[] = {
- (unsigned short *) PORTCIO_FER,
- (unsigned short *) PORTDIO_FER,
- (unsigned short *) PORTEIO_FER,
-};
-#endif
-
-#define RESOURCE_LABEL_SIZE 16
-
-static struct str_ident {
- char name[RESOURCE_LABEL_SIZE];
-} str_ident[MAX_RESOURCES];
-
-#if defined(CONFIG_PM)
-static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
-# ifdef BF538_FAMILY
-static unsigned short port_fer_saved[3];
-# endif
-#endif
-
-static void gpio_error(unsigned gpio)
-{
- printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
-}
-
-static void set_label(unsigned short ident, const char *label)
-{
- if (label) {
- strncpy(str_ident[ident].name, label,
- RESOURCE_LABEL_SIZE);
- str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
- }
-}
-
-static char *get_label(unsigned short ident)
-{
- return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-}
-
-static int cmp_label(unsigned short ident, const char *label)
-{
- if (label == NULL) {
- dump_stack();
- printk(KERN_ERR "Please provide none-null label\n");
- }
-
- if (label)
- return strcmp(str_ident[ident].name, label);
- else
- return -EINVAL;
-}
-
-#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
-#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
-#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
-#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
-#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
-
-DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
-DECLARE_RESERVED_MAP(peri, DIV_ROUND_UP(MAX_RESOURCES, GPIO_BANKSIZE));
-DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
-
-inline int check_gpio(unsigned gpio)
-{
- if (gpio >= MAX_BLACKFIN_GPIOS)
- return -EINVAL;
- return 0;
-}
-
-static void port_setup(unsigned gpio, unsigned short usage)
-{
-#if defined(BF538_FAMILY)
- /*
- * BF538/9 Port C,D and E are special.
- * Inverted PORT_FER polarity on CDE and no PORF_FER on F
- * Regular PORT F GPIOs are handled here, CDE are exclusively
- * managed by GPIOLIB
- */
-
- if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
- return;
-
- gpio -= MAX_BLACKFIN_GPIOS;
-
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- SSYNC();
- return;
-#endif
-
- if (check_gpio(gpio))
- return;
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- if (usage == GPIO_USAGE)
- *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
- else
- *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
- SSYNC();
-#endif
-}
-
-#ifdef BF537_FAMILY
-static const s8 port_mux[] = {
- [GPIO_PF0] = 3,
- [GPIO_PF1] = 3,
- [GPIO_PF2] = 4,
- [GPIO_PF3] = 4,
- [GPIO_PF4] = 5,
- [GPIO_PF5] = 6,
- [GPIO_PF6] = 7,
- [GPIO_PF7] = 8,
- [GPIO_PF8 ... GPIO_PF15] = -1,
- [GPIO_PG0 ... GPIO_PG7] = -1,
- [GPIO_PG8] = 9,
- [GPIO_PG9] = 9,
- [GPIO_PG10] = 10,
- [GPIO_PG11] = 10,
- [GPIO_PG12] = 10,
- [GPIO_PG13] = 11,
- [GPIO_PG14] = 11,
- [GPIO_PG15] = 11,
- [GPIO_PH0 ... GPIO_PH15] = -1,
- [PORT_PJ0 ... PORT_PJ3] = -1,
- [PORT_PJ4] = 1,
- [PORT_PJ5] = 1,
- [PORT_PJ6 ... PORT_PJ9] = -1,
- [PORT_PJ10] = 0,
- [PORT_PJ11] = 0,
-};
-
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 m, pmux, pfunc, mask;
-
- if (offset < 0)
- return 0;
-
- pmux = bfin_read_PORT_MUX();
- for (m = 0; m < ARRAY_SIZE(port_mux); ++m) {
- if (m == ident)
- continue;
- if (port_mux[m] != offset)
- continue;
- if (!is_reserved(peri, m, 1))
- continue;
-
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pfunc = (pmux >> offset) & mask;
- if (pfunc != (function & mask)) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, m, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-static void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- s8 offset = port_mux[ident];
- u16 pmux, mask;
-
- if (offset == -1)
- return;
-
- pmux = bfin_read_PORT_MUX();
- if (offset == 1)
- mask = 3;
- else
- mask = 1;
-
- pmux &= ~(mask << offset);
- pmux |= ((function & mask) << offset);
-
- bfin_write_PORT_MUX(pmux);
-}
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
-static int portmux_group_check(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pin, gpiopin, pfunc;
-
- for (pin = 0; pin < GPIO_BANKSIZE; ++pin) {
- if (offset != pmux_offset[gpio_bank(ident)][pin])
- continue;
-
- gpiopin = gpio_bank(ident) * GPIO_BANKSIZE + pin;
- if (gpiopin == ident)
- continue;
- if (!is_reserved(peri, gpiopin, 1))
- continue;
-
- pfunc = *port_mux[gpio_bank(ident)];
- pfunc = (pfunc >> offset) & 3;
- if (pfunc != function) {
- pr_err("pin group conflict! request pin %d func %d conflict with pin %d func %d\n",
- ident, function, gpiopin, pfunc);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-inline void portmux_setup(unsigned short per)
-{
- u16 ident = P_IDENT(per);
- u16 function = P_FUNCT2MUX(per);
- u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
- u16 pmux;
-
- pmux = *port_mux[gpio_bank(ident)];
- if (((pmux >> offset) & 3) == function)
- return;
- pmux &= ~(3 << offset);
- pmux |= (function & 3) << offset;
- *port_mux[gpio_bank(ident)] = pmux;
- SSYNC();
-}
-#else
-# define portmux_setup(...) do { } while (0)
-static int portmux_group_check(unsigned short per)
-{
- return 0;
-}
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-* to Blackfin processor General Purpose
-* Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-/* Set a specific bit */
-
-#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO(dir) /* set_gpio_dir() */
-SET_GPIO(inen) /* set_gpio_inen() */
-SET_GPIO(polar) /* set_gpio_polar() */
-SET_GPIO(edge) /* set_gpio_edge() */
-SET_GPIO(both) /* set_gpio_both() */
-
-
-#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- if (arg) \
- gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
- else \
- gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpio_ ## name);
-
-SET_GPIO_SC(maska)
-SET_GPIO_SC(maskb)
-SET_GPIO_SC(data)
-
-void set_gpio_toggle(unsigned gpio)
-{
- unsigned long flags;
- if (ANOMALY_05000311 || ANOMALY_05000323)
- flags = hard_local_irq_save();
- gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
- if (ANOMALY_05000311 || ANOMALY_05000323) {
- AWA_DUMMY_READ(toggle);
- hard_local_irq_restore(flags);
- }
-}
-EXPORT_SYMBOL(set_gpio_toggle);
-
-
-/*Set current PORT date (16-bit word)*/
-
-#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
-{ \
- unsigned long flags; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- gpio_array[gpio_bank(gpio)]->name = arg; \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
-} \
-EXPORT_SYMBOL(set_gpiop_ ## name);
-
-SET_GPIO_P(data)
-SET_GPIO_P(dir)
-SET_GPIO_P(inen)
-SET_GPIO_P(polar)
-SET_GPIO_P(edge)
-SET_GPIO_P(both)
-SET_GPIO_P(maska)
-SET_GPIO_P(maskb)
-
-/* Get a specific bit */
-#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpio_ ## name);
-
-GET_GPIO(data)
-GET_GPIO(dir)
-GET_GPIO(inen)
-GET_GPIO(polar)
-GET_GPIO(edge)
-GET_GPIO(both)
-GET_GPIO(maska)
-GET_GPIO(maskb)
-
-/*Get current PORT date (16-bit word)*/
-
-#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned gpio) \
-{ \
- unsigned long flags; \
- unsigned short ret; \
- if (ANOMALY_05000311 || ANOMALY_05000323) \
- flags = hard_local_irq_save(); \
- ret = (gpio_array[gpio_bank(gpio)]->name); \
- if (ANOMALY_05000311 || ANOMALY_05000323) { \
- AWA_DUMMY_READ(name); \
- hard_local_irq_restore(flags); \
- } \
- return ret; \
-} \
-EXPORT_SYMBOL(get_gpiop_ ## name);
-
-GET_GPIO_P(data)
-GET_GPIO_P(dir)
-GET_GPIO_P(inen)
-GET_GPIO_P(polar)
-GET_GPIO_P(edge)
-GET_GPIO_P(both)
-GET_GPIO_P(maska)
-GET_GPIO_P(maskb)
-
-
-#ifdef CONFIG_PM
-DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM);
-
-static const unsigned int sic_iwr_irqs[] = {
-#if defined(BF533_FAMILY)
- IRQ_PROG_INTB
-#elif defined(BF537_FAMILY)
- IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
-#elif defined(BF538_FAMILY)
- IRQ_PORTF_INTB
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
-#elif defined(BF561_FAMILY)
- IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
-#else
-# error no SIC_IWR defined
-#endif
-};
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin PM Setup API
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-* type -
-* PM_WAKE_RISING
-* PM_WAKE_FALLING
-* PM_WAKE_HIGH
-* PM_WAKE_LOW
-* PM_WAKE_BOTH_EDGES
-*
-* DESCRIPTION: Blackfin PM Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
- if (ctrl)
- reserve(wakeup, gpio);
- else
- unreserve(wakeup, gpio);
-
- set_gpio_maskb(gpio, ctrl);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-int bfin_gpio_pm_standby_ctrl(unsigned ctrl)
-{
- u16 bank, mask, i;
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- mask = map_entry(wakeup, i);
- bank = gpio_bank(i);
-
- if (mask)
- bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl);
- }
- return 0;
-}
-
-void bfin_gpio_pm_hibernate_suspend(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- port_fer_saved[i] = *port_fer[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].fer = *port_fer[bank];
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- gpio_bank_saved[bank].mux = *port_mux[bank];
-#else
- if (bank == 0)
- gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
-#endif
-#endif
- gpio_bank_saved[bank].data = gpio_array[bank]->data;
- gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
- gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
- gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
- gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
- gpio_bank_saved[bank].both = gpio_array[bank]->both;
- gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_suspend();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-void bfin_gpio_pm_hibernate_restore(void)
-{
- int i, bank;
-
-#ifdef BF538_FAMILY
- for (i = 0; i < ARRAY_SIZE(port_fer_saved); ++i)
- *port_fer[i] = port_fer_saved[i];
-#endif
-
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- bank = gpio_bank(i);
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- *port_mux[bank] = gpio_bank_saved[bank].mux;
-#else
- if (bank == 0)
- bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
-#endif
- *port_fer[bank] = gpio_bank_saved[bank].fer;
-#endif
- gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
- gpio_array[bank]->data_set = gpio_bank_saved[bank].data
- & gpio_bank_saved[bank].dir;
- gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
- gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
- gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
- gpio_array[bank]->both = gpio_bank_saved[bank].both;
- gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
- }
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
- bfin_special_gpio_pm_hibernate_restore();
-#endif
-
- AWA_DUMMY_READ(maska);
-}
-
-
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin Peripheral Resource Allocation
-* and PortMux Setup
-*
-* INPUTS/OUTPUTS:
-* per Peripheral Identifier
-* label String
-*
-* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int peripheral_request(unsigned short per, const char *label)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- /*
- * Don't cares are pins with only one dedicated function
- */
-
- if (per & P_DONTCARE)
- return 0;
-
- if (!(per & P_DEFINED))
- return -ENODEV;
-
- BUG_ON(ident >= MAX_RESOURCES);
-
- flags = hard_local_irq_save();
-
- /* If a pin can be muxed as either GPIO or peripheral, make
- * sure it is not already a GPIO pin when we request it.
- */
- if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d is already reserved as GPIO by %s !\n",
- __func__, ident, get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
-
- if (unlikely(is_reserved(peri, ident, 1))) {
-
- /*
- * Pin functions like AMC address strobes my
- * be requested and used by several drivers
- */
-
- if (!(per & P_MAYSHARE)) {
- /*
- * Allow that the identical pin function can
- * be requested from the same driver twice
- */
-
- if (cmp_label(ident, label) == 0)
- goto anyway;
-
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "%s: Peripheral %d function %d is already reserved by %s !\n",
- __func__, ident, P_FUNCT2MUX(per), get_label(ident));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- }
-
- if (unlikely(portmux_group_check(per))) {
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- anyway:
- reserve(peri, ident);
-
- portmux_setup(per);
- port_setup(ident, PERIPHERAL_USAGE);
-
- hard_local_irq_restore(flags);
- set_label(ident, label);
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request);
-
-int peripheral_request_list(const unsigned short per[], const char *label)
-{
- u16 cnt;
- int ret;
-
- for (cnt = 0; per[cnt] != 0; cnt++) {
-
- ret = peripheral_request(per[cnt], label);
-
- if (ret < 0) {
- for ( ; cnt > 0; cnt--)
- peripheral_free(per[cnt - 1]);
-
- return ret;
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL(peripheral_request_list);
-
-void peripheral_free(unsigned short per)
-{
- unsigned long flags;
- unsigned short ident = P_IDENT(per);
-
- if (per & P_DONTCARE)
- return;
-
- if (!(per & P_DEFINED))
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(peri, ident, 0))) {
- hard_local_irq_restore(flags);
- return;
- }
-
- if (!(per & P_MAYSHARE))
- port_setup(ident, GPIO_USAGE);
-
- unreserve(peri, ident);
-
- set_label(ident, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(peripheral_free);
-
-void peripheral_free_list(const unsigned short per[])
-{
- u16 cnt;
- for (cnt = 0; per[cnt] != 0; cnt++)
- peripheral_free(per[cnt]);
-}
-EXPORT_SYMBOL(peripheral_free_list);
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
-* label String
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int bfin_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(gpio, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
- " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
- } else { /* Reset POLAR setting when acquiring a gpio for the first time */
- set_gpio_polar(gpio, 0);
- }
-
- reserve(gpio, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_request);
-
-void bfin_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_gpio_free);
-
-#ifdef BFIN_SPECIAL_GPIO_BANKS
-DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
-
-int bfin_special_gpio_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- flags = hard_local_irq_save();
-
- /*
- * Allow that the identical GPIO can
- * be requested from the same driver twice
- * Do nothing and return -
- */
-
- if (cmp_label(gpio, label) == 0) {
- hard_local_irq_restore(flags);
- return 0;
- }
-
- if (unlikely(is_reserved(special_gpio, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
- if (unlikely(is_reserved(peri, gpio, 1))) {
- hard_local_irq_restore(flags);
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
-
- return -EBUSY;
- }
-
- reserve(special_gpio, gpio);
- reserve(peri, gpio);
-
- set_label(gpio, label);
- hard_local_irq_restore(flags);
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_special_gpio_request);
-
-void bfin_special_gpio_free(unsigned gpio)
-{
- unsigned long flags;
-
- might_sleep();
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(special_gpio, gpio);
- unreserve(peri, gpio);
- set_label(gpio, "free");
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(bfin_special_gpio_free);
-#endif
-
-
-int bfin_gpio_irq_request(unsigned gpio, const char *label)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return -EINVAL;
-
- flags = hard_local_irq_save();
-
- if (unlikely(is_reserved(peri, gpio, 1))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- printk(KERN_ERR
- "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
- gpio, get_label(gpio));
- hard_local_irq_restore(flags);
- return -EBUSY;
- }
- if (unlikely(is_reserved(gpio, gpio, 1)))
- printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
- "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
- gpio, get_label(gpio));
-
- reserve(gpio_irq, gpio);
- set_label(gpio, label);
-
- hard_local_irq_restore(flags);
-
- port_setup(gpio, GPIO_USAGE);
-
- return 0;
-}
-
-void bfin_gpio_irq_free(unsigned gpio)
-{
- unsigned long flags;
-
- if (check_gpio(gpio) < 0)
- return;
-
- flags = hard_local_irq_save();
-
- if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
- if (system_state == SYSTEM_BOOTING)
- dump_stack();
- gpio_error(gpio);
- hard_local_irq_restore(flags);
- return;
- }
-
- unreserve(gpio_irq, gpio);
-
- set_label(gpio, "free");
-
- hard_local_irq_restore(flags);
-}
-
-static inline void __bfin_gpio_direction_input(unsigned gpio)
-{
- gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
- gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-}
-
-int bfin_gpio_direction_input(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
- __bfin_gpio_direction_input(gpio);
- AWA_DUMMY_READ(inen);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_input);
-
-void bfin_gpio_irq_prepare(unsigned gpio)
-{
- port_setup(gpio, GPIO_USAGE);
-}
-
-void bfin_gpio_set_value(unsigned gpio, int arg)
-{
- if (arg)
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- else
- gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_set_value);
-
-int bfin_gpio_direction_output(unsigned gpio, int value)
-{
- unsigned long flags;
-
- if (unlikely(!is_reserved(gpio, gpio, 0))) {
- gpio_error(gpio);
- return -EINVAL;
- }
-
- flags = hard_local_irq_save();
-
- gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
- gpio_set_value(gpio, value);
- gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-
- AWA_DUMMY_READ(dir);
- hard_local_irq_restore(flags);
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_gpio_direction_output);
-
-int bfin_gpio_get_value(unsigned gpio)
-{
- unsigned long flags;
-
- if (unlikely(get_gpio_edge(gpio))) {
- int ret;
- flags = hard_local_irq_save();
- set_gpio_edge(gpio, 0);
- ret = get_gpio_data(gpio);
- set_gpio_edge(gpio, 1);
- hard_local_irq_restore(flags);
- return ret;
- } else
- return get_gpio_data(gpio);
-}
-EXPORT_SYMBOL(bfin_gpio_get_value);
-
-/* If we are booting from SPI and our board lacks a strong enough pull up,
- * the core can reset and execute the bootrom faster than the resistor can
- * pull the signal logically high. To work around this (common) error in
- * board design, we explicitly set the pin back to GPIO mode, force /CS
- * high, and wait for the electrons to do their thing.
- *
- * This function only makes sense to be called from reset code, but it
- * lives here as we need to force all the GPIO states w/out going through
- * BUG() checks and such.
- */
-void bfin_reset_boot_spi_cs(unsigned short pin)
-{
- unsigned short gpio = P_IDENT(pin);
- port_setup(gpio, GPIO_USAGE);
- gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
- AWA_DUMMY_READ(data_set);
- udelay(1);
-}
-
-#if defined(CONFIG_PROC_FS)
-static int gpio_proc_show(struct seq_file *m, void *v)
-{
- int c, irq, gpio;
-
- for (c = 0; c < MAX_RESOURCES; c++) {
- irq = is_reserved(gpio_irq, c, 1);
- gpio = is_reserved(gpio, c, 1);
- if (!check_gpio(c) && (gpio || irq))
- seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
- get_label(c), (gpio && irq) ? " *" : "",
- get_gpio_dir(c) ? "OUTPUT" : "INPUT");
- else if (is_reserved(peri, c, 1))
- seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
- else
- continue;
- }
-
- return 0;
-}
-
-static int gpio_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, gpio_proc_show, NULL);
-}
-
-static const struct file_operations gpio_proc_ops = {
- .open = gpio_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static __init int gpio_register_proc(void)
-{
- struct proc_dir_entry *proc_gpio;
-
- proc_gpio = proc_create("gpio", 0, NULL, &gpio_proc_ops);
- return proc_gpio == NULL;
-}
-__initcall(gpio_register_proc);
-#endif
-
-#ifdef CONFIG_GPIOLIB
-static int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_direction_input(gpio);
-}
-
-static int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
-{
- return bfin_gpio_direction_output(gpio, level);
-}
-
-static int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- return !!bfin_gpio_get_value(gpio);
-}
-
-static void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- return bfin_gpio_set_value(gpio, value);
-}
-
-static int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_request(gpio, chip->label);
-}
-
-static void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_gpio_free(gpio);
-}
-
-static int bfin_gpiolib_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-{
- return gpio + GPIO_IRQ_BASE;
-}
-
-static struct gpio_chip bfin_chip = {
- .label = "BFIN-GPIO",
- .direction_input = bfin_gpiolib_direction_input,
- .get = bfin_gpiolib_get_value,
- .direction_output = bfin_gpiolib_direction_output,
- .set = bfin_gpiolib_set_value,
- .request = bfin_gpiolib_gpio_request,
- .free = bfin_gpiolib_gpio_free,
- .to_irq = bfin_gpiolib_gpio_to_irq,
- .base = 0,
- .ngpio = MAX_BLACKFIN_GPIOS,
-};
-
-static int __init bfin_gpiolib_setup(void)
-{
- return gpiochip_add_data(&bfin_chip, NULL);
-}
-arch_initcall(bfin_gpiolib_setup);
-#endif
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
deleted file mode 100644
index 68096e8f787f..000000000000
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * arch/blackfin/kernel/bfin_ksyms.c - exports for random symbols
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <asm/irq_handler.h>
-
-/* Allow people to have their own Blackfin exception handler in a module */
-EXPORT_SYMBOL(bfin_return_from_exception);
-
-/* All the Blackfin cache functions: mach-common/cache.S */
-EXPORT_SYMBOL(blackfin_dcache_invalidate_range);
-EXPORT_SYMBOL(blackfin_icache_flush_range);
-EXPORT_SYMBOL(blackfin_dcache_flush_range);
-EXPORT_SYMBOL(blackfin_dflush_page);
-
-/* The following are special because they're not called
- * explicitly (the C compiler generates them). Fortunately,
- * their interface isn't gonna change any time soon now, so
- * it's OK to leave it out of version control.
- */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-EXPORT_SYMBOL(memcmp);
-EXPORT_SYMBOL(memmove);
-EXPORT_SYMBOL(memchr);
-
-/*
- * Because string functions are both inline and exported functions and
- * folder arch/blackfin/lib is configured as a library path in Makefile,
- * symbols exported in folder lib is not linked into built-in.o but
- * inlined only. In order to export string symbols to kernel module
- * properly, they should be exported here.
- */
-EXPORT_SYMBOL(strcpy);
-EXPORT_SYMBOL(strncpy);
-EXPORT_SYMBOL(strcmp);
-EXPORT_SYMBOL(strncmp);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler... (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __smulsi3_highpart(void);
-extern void __umulsi3_highpart(void);
-extern void __divsi3(void);
-extern void __lshrdi3(void);
-extern void __modsi3(void);
-extern void __muldi3(void);
-extern void __udivsi3(void);
-extern void __umodsi3(void);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__umulsi3_highpart);
-EXPORT_SYMBOL(__smulsi3_highpart);
-EXPORT_SYMBOL(__divsi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__modsi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__udivsi3);
-EXPORT_SYMBOL(__umodsi3);
-
-/* Input/output symbols: lib/{in,out}s.S */
-EXPORT_SYMBOL(outsb);
-EXPORT_SYMBOL(insb);
-EXPORT_SYMBOL(outsw);
-EXPORT_SYMBOL(outsw_8);
-EXPORT_SYMBOL(insw);
-EXPORT_SYMBOL(insw_8);
-EXPORT_SYMBOL(outsl);
-EXPORT_SYMBOL(insl);
-EXPORT_SYMBOL(insl_16);
-
-#ifdef CONFIG_SMP
-EXPORT_SYMBOL(__raw_atomic_add_asm);
-EXPORT_SYMBOL(__raw_atomic_xadd_asm);
-EXPORT_SYMBOL(__raw_atomic_and_asm);
-EXPORT_SYMBOL(__raw_atomic_or_asm);
-EXPORT_SYMBOL(__raw_atomic_xor_asm);
-EXPORT_SYMBOL(__raw_atomic_test_asm);
-
-EXPORT_SYMBOL(__raw_xchg_1_asm);
-EXPORT_SYMBOL(__raw_xchg_2_asm);
-EXPORT_SYMBOL(__raw_xchg_4_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_1_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_2_asm);
-EXPORT_SYMBOL(__raw_cmpxchg_4_asm);
-EXPORT_SYMBOL(__raw_spin_is_locked_asm);
-EXPORT_SYMBOL(__raw_spin_lock_asm);
-EXPORT_SYMBOL(__raw_spin_trylock_asm);
-EXPORT_SYMBOL(__raw_spin_unlock_asm);
-EXPORT_SYMBOL(__raw_read_lock_asm);
-EXPORT_SYMBOL(__raw_read_trylock_asm);
-EXPORT_SYMBOL(__raw_read_unlock_asm);
-EXPORT_SYMBOL(__raw_write_lock_asm);
-EXPORT_SYMBOL(__raw_write_trylock_asm);
-EXPORT_SYMBOL(__raw_write_unlock_asm);
-EXPORT_SYMBOL(__raw_bit_set_asm);
-EXPORT_SYMBOL(__raw_bit_clear_asm);
-EXPORT_SYMBOL(__raw_bit_toggle_asm);
-EXPORT_SYMBOL(__raw_bit_test_asm);
-EXPORT_SYMBOL(__raw_bit_test_set_asm);
-EXPORT_SYMBOL(__raw_bit_test_clear_asm);
-EXPORT_SYMBOL(__raw_bit_test_toggle_asm);
-EXPORT_SYMBOL(__raw_uncached_fetch_asm);
-#ifdef __ARCH_SYNC_CORE_DCACHE
-EXPORT_SYMBOL(__raw_smp_mark_barrier_asm);
-EXPORT_SYMBOL(__raw_smp_check_barrier_asm);
-#endif
-#endif
-
-#ifdef CONFIG_FUNCTION_TRACER
-extern void _mcount(void);
-EXPORT_SYMBOL(_mcount);
-#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/Makefile b/arch/blackfin/kernel/cplb-mpu/Makefile
deleted file mode 100644
index 394d0b1b28fe..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
deleted file mode 100644
index c15fd05f0b09..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
-
-int first_switched_icplb, first_switched_dcplb;
-int first_mask_dcplb;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long d_data, i_data;
- unsigned long d_cache = 0, i_cache = 0;
-
- printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_cache = CPLB_L1_CHBL;
-#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_cache |= CPLB_L1_AOW | CPLB_WT;
-#endif
-#endif
-
- i_d = i_i = 0;
-
- /* Set up the zero page. */
- dcplb_tbl[cpu][i_d].addr = 0;
- dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-
- icplb_tbl[cpu][i_i].addr = 0;
- icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
- d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
- i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
-
- for (; addr < memory_start; addr += 4 * 1024 * 1024) {
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- dcplb_tbl[cpu][i_d].addr = addr;
- dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD;
- icplb_tbl[cpu][i_i].addr = addr;
- icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD;
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
-#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
- dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
-#endif
-#if L1_CODE_LENGTH > 0
- icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
- icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
-#endif
-
- /* Cover L2 memory */
-#if L2_LENGTH > 0
- dcplb_tbl[cpu][i_d].addr = L2_START;
- dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
- icplb_tbl[cpu][i_i].addr = L2_START;
- icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
-#endif
-
- first_mask_dcplb = i_d;
- first_switched_dcplb = i_d + (1 << page_mask_order);
- first_switched_icplb = i_i;
-
- while (i_d < MAX_CPLBS)
- dcplb_tbl[cpu][i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- icplb_tbl[cpu][i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
-}
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
deleted file mode 100644
index b56bd8514b7c..000000000000
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * Blackfin CPLB exception handling for when MPU in on
- *
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/mm.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mmu_context.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int page_mask_nelts;
-int page_mask_order;
-unsigned long *current_rwx_mask[NR_CPUS];
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-int nr_cplb_flush[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-/*
- * Given the contents of the status register, return the index of the
- * CPLB that caused the fault.
- */
-static inline int faulting_cplb_index(int status)
-{
- int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
- return 30 - signbits;
-}
-
-/*
- * Given the contents of the status register and the DCPLB_DATA contents,
- * return true if a write access should be permitted.
- */
-static inline int write_permitted(int status, unsigned long data)
-{
- if (status & FAULT_USERSUPV)
- return !!(data & CPLB_SUPV_WR);
- else
- return !!(data & CPLB_USER_WR);
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-MGR_ATTR static int evict_one_icplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_icplb; i < MAX_CPLBS; i++)
- if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int evict_one_dcplb(unsigned int cpu)
-{
- int i;
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
- if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
- return i;
- i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- unsigned long *mask;
- int idx;
- unsigned long d_data;
-
- nr_dcplb_miss[cpu]++;
-
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- if (bfin_addr_dcacheable(addr)) {
- d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
- }
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
- }
-#endif
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
- addr &= ~(1 * 1024 * 1024 - 1);
- d_data &= ~PAGE_SIZE_4KB;
- d_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- d_data |= CPLB_USER_RD | CPLB_USER_WR;
- if (reserved_mem_dcache_on)
- d_data |= CPLB_L1_CHBL;
- } else {
- mask = current_rwx_mask[cpu];
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- if (mask[idx] & bit)
- d_data |= CPLB_USER_RD;
-
- mask += page_mask_nelts;
- if (mask[idx] & bit)
- d_data |= CPLB_USER_WR;
- }
- }
- idx = evict_one_dcplb(cpu);
-
- addr &= PAGE_MASK;
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = d_data;
-
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int icplb_miss(unsigned int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data;
-
- nr_icplb_miss[cpu]++;
-
- /* If inside the uncached DMA region, fault. */
- if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
- return CPLB_PROT_VIOL;
-
- if (status & FAULT_USERSUPV)
- nr_icplb_supv_miss[cpu]++;
-
- /*
- * First, try to find a CPLB that matches this address. If we
- * find one, then the fact that we're in the miss handler means
- * that the instruction crosses a page boundary.
- */
- for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
- if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
- unsigned long this_addr = icplb_tbl[cpu][idx].addr;
- if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
- addr += PAGE_SIZE;
- break;
- }
- }
- }
-
- i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
-
-#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- /*
- * Normal RAM, and possibly the reserved memory area, are
- * cacheable.
- */
- if (addr < _ramend ||
- (addr < physical_mem_end && reserved_mem_icache_on))
- i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
-#endif
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- i_data = L2_IMEMORY;
- } else if (addr >= physical_mem_end) {
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
- && (status & FAULT_USERSUPV)) {
- addr &= ~(1 * 1024 * 1024 - 1);
- i_data &= ~PAGE_SIZE_4KB;
- i_data |= PAGE_SIZE_1MB;
- } else
- return CPLB_PROT_VIOL;
- } else if (addr >= _ramend) {
- i_data |= CPLB_USER_RD;
- if (reserved_mem_icache_on)
- i_data |= CPLB_L1_CHBL;
- } else {
- /*
- * Two cases to distinguish - a supervisor access must
- * necessarily be for a module page; we grant it
- * unconditionally (could do better here in the future).
- * Otherwise, check the x bitmap of the current process.
- */
- if (!(status & FAULT_USERSUPV)) {
- unsigned long *mask = current_rwx_mask[cpu];
-
- if (mask) {
- int page = addr >> PAGE_SHIFT;
- int idx = page >> 5;
- int bit = 1 << (page & 31);
-
- mask += 2 * page_mask_nelts;
- if (mask[idx] & bit)
- i_data |= CPLB_USER_RD;
- }
- }
- }
- idx = evict_one_icplb(cpu);
- addr &= PAGE_MASK;
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = i_data;
-
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
- return 0;
-}
-
-MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu)
-{
- int status = bfin_read_DCPLB_STATUS();
-
- nr_dcplb_prot[cpu]++;
-
- if (status & FAULT_RW) {
- int idx = faulting_cplb_index(status);
- unsigned long data = dcplb_tbl[cpu][idx].data;
- if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
- write_permitted(status, data)) {
- data |= CPLB_DIRTY;
- dcplb_tbl[cpu][idx].data = data;
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- return 0;
- }
- }
- return CPLB_PROT_VIOL;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case 0x23:
- return dcplb_protection_fault(cpu);
- case 0x2C:
- return icplb_miss(cpu);
- case 0x26:
- return dcplb_miss(cpu);
- default:
- return 1;
- }
-}
-
-void flush_switched_cplbs(unsigned int cpu)
-{
- int i;
- unsigned long flags;
-
- nr_cplb_flush[cpu]++;
-
- flags = hard_local_irq_save();
- _disable_icplb();
- for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
- icplb_tbl[cpu][i].data = 0;
- bfin_write32(ICPLB_DATA0 + i * 4, 0);
- }
- _enable_icplb();
-
- _disable_dcplb();
- for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
- dcplb_tbl[cpu][i].data = 0;
- bfin_write32(DCPLB_DATA0 + i * 4, 0);
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-
-}
-
-void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
-{
- int i;
- unsigned long addr = (unsigned long)masks;
- unsigned long d_data;
- unsigned long flags;
-
- if (!masks) {
- current_rwx_mask[cpu] = masks;
- return;
- }
-
- flags = hard_local_irq_save();
- current_rwx_mask[cpu] = masks;
-
- if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
- addr = L2_START;
- d_data = L2_DMEMORY;
- } else {
- d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
-#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
- d_data |= CPLB_L1_CHBL;
-# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
- d_data |= CPLB_L1_AOW | CPLB_WT;
-# endif
-#endif
- }
-
- _disable_dcplb();
- for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
- dcplb_tbl[cpu][i].addr = addr;
- dcplb_tbl[cpu][i].data = d_data;
- bfin_write32(DCPLB_DATA0 + i * 4, d_data);
- bfin_write32(DCPLB_ADDR0 + i * 4, addr);
- addr += PAGE_SIZE;
- }
- _enable_dcplb();
- hard_local_irq_restore(flags);
-}
diff --git a/arch/blackfin/kernel/cplb-nompu/Makefile b/arch/blackfin/kernel/cplb-nompu/Makefile
deleted file mode 100644
index 81baa27bc389..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/kernel/cplb-nompu/Makefile
-#
-
-obj-y := cplbinit.o cplbmgr.o
-
-CFLAGS_cplbmgr.o := -ffixed-I0 -ffixed-I1 -ffixed-I2 -ffixed-I3 \
- -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
- -ffixed-M0 -ffixed-M1 -ffixed-M2 -ffixed-M3 \
- -ffixed-B0 -ffixed-B1 -ffixed-B2 -ffixed-B3
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
deleted file mode 100644
index b49a53b583d5..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * Blackfin CPLB initialization
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <asm/cplb.h>
-#include <asm/cplbinit.h>
-#include <asm/mem_map.h>
-
-struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
-
-int first_switched_icplb PDT_ATTR;
-int first_switched_dcplb PDT_ATTR;
-
-struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
-struct cplb_boundary icplb_bounds[9] PDT_ATTR;
-
-int icplb_nr_bounds PDT_ATTR;
-int dcplb_nr_bounds PDT_ATTR;
-
-void __init generate_cplb_tables_cpu(unsigned int cpu)
-{
- int i_d, i_i;
- unsigned long addr;
- unsigned long cplb_pageflags, cplb_pagesize;
-
- struct cplb_entry *d_tbl = dcplb_tbl[cpu];
- struct cplb_entry *i_tbl = icplb_tbl[cpu];
-
- printk(KERN_INFO "NOMPU: setting up cplb tables\n");
-
- i_d = i_i = 0;
-
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- /* Set up the zero page. */
- d_tbl[i_d].addr = 0;
- d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
- i_tbl[i_i].addr = 0;
- i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
-#endif
-
- /* Cover kernel memory with 4M pages. */
- addr = 0;
-
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-
- for (; addr < memory_start; addr += cplb_pagesize) {
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
- }
-
-#ifdef CONFIG_ROMKERNEL
- /* Cover kernel XIP flash area */
-#ifdef CONFIG_BF60x
- addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
-#else
- addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
- d_tbl[i_d].addr = addr;
- d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
- i_tbl[i_i].addr = addr;
- i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
-#endif
-#endif
-
- /* Cover L1 memory. One 4M area for code and data each is enough. */
- if (cpu == 0) {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#ifdef CONFIG_SMP
- else {
- if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
- d_tbl[i_d].addr = COREB_L1_DATA_A_START;
- d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
- }
- i_tbl[i_i].addr = COREB_L1_CODE_START;
- i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
- }
-#endif
- first_switched_dcplb = i_d;
- first_switched_icplb = i_i;
-
- BUG_ON(first_switched_dcplb > MAX_CPLBS);
- BUG_ON(first_switched_icplb > MAX_CPLBS);
-
- while (i_d < MAX_CPLBS)
- d_tbl[i_d++].data = 0;
- while (i_i < MAX_CPLBS)
- i_tbl[i_i++].data = 0;
-}
-
-void __init generate_cplb_tables_all(void)
-{
- unsigned long uncached_end;
- int i_d, i_i;
-
- i_d = 0;
- /* Normal RAM, including MTD FS. */
-#ifdef CONFIG_MTD_UCLINUX
- uncached_end = memory_mtd_start + mtd_size;
-#else
- uncached_end = memory_end;
-#endif
- /*
- * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached
- * so that we don't have to use 4kB pages and cause CPLB thrashing
- */
- if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION ||
- ((_ramend - uncached_end) >= 1 * 1024 * 1024))
- dcplb_bounds[i_d].eaddr = uncached_end;
- else
- dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- dcplb_bounds[i_d].eaddr = _ramend;
- dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
- }
- if (_ramend != physical_mem_end) {
- /* Reserved memory. */
- dcplb_bounds[i_d].eaddr = physical_mem_end;
- dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
- SDRAM_DGENERIC : SDRAM_DNON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
- dcplb_bounds[i_d++].data = 0;
- /* ASYNC banks. */
- dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- dcplb_bounds[i_d++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
- dcplb_bounds[i_d++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START;
- dcplb_bounds[i_d++].data = 0;
- /* L2 SRAM. */
- dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
- dcplb_bounds[i_d++].data = L2_DMEMORY;
- }
- dcplb_nr_bounds = i_d;
- BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
-
- i_i = 0;
- /* Normal RAM, including MTD FS. */
- icplb_bounds[i_i].eaddr = uncached_end;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
- if (_ramend != physical_mem_end) {
- /* DMA uncached region. */
- if (DMA_UNCACHED_REGION) {
- /* Normally this hole is caught by the async below. */
- icplb_bounds[i_i].eaddr = _ramend;
- icplb_bounds[i_i++].data = 0;
- }
- /* Reserved memory. */
- icplb_bounds[i_i].eaddr = physical_mem_end;
- icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
- SDRAM_IGENERIC : SDRAM_INON_CHBL);
- }
- /* Addressing hole up to the async bank. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE;
- icplb_bounds[i_i++].data = 0;
- /* ASYNC banks. */
- icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
- icplb_bounds[i_i++].data = SDRAM_EBIU;
- /* Addressing hole up to BootROM. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START;
- icplb_bounds[i_i++].data = 0;
- /* BootROM -- largest one should be less than 1 meg. */
- icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
- icplb_bounds[i_i++].data = SDRAM_IGENERIC;
-
- if (L2_LENGTH) {
- /* Addressing hole up to L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START;
- icplb_bounds[i_i++].data = 0;
- /* L2 SRAM. */
- icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
- icplb_bounds[i_i++].data = L2_IMEMORY;
- }
- icplb_nr_bounds = i_i;
- BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
-}
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
deleted file mode 100644
index 79cc0f6dcdd5..000000000000
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c
- * Author: Michael McTernan <mmcternan@airvana.com>
- *
- * Description: CPLB miss handler.
- *
- * Modified:
- * Copyright 2008 Airvana Inc.
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/cplb.h>
-#include <asm/mmu_context.h>
-#include <asm/traps.h>
-
-/*
- * WARNING
- *
- * This file is compiled with certain -ffixed-reg options. We have to
- * make sure not to call any functions here that could clobber these
- * registers.
- */
-
-int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
-int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
-int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-#define MGR_ATTR __attribute__((l1_text))
-#else
-#define MGR_ATTR
-#endif
-
-static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_dcplb();
- bfin_write32(DCPLB_DATA0 + idx * 4, data);
- bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
- _enable_dcplb();
-
-#ifdef CONFIG_CPLB_INFO
- dcplb_tbl[cpu][idx].addr = addr;
- dcplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-static inline void write_icplb_data(int cpu, int idx, unsigned long data,
- unsigned long addr)
-{
- _disable_icplb();
- bfin_write32(ICPLB_DATA0 + idx * 4, data);
- bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
- _enable_icplb();
-
-#ifdef CONFIG_CPLB_INFO
- icplb_tbl[cpu][idx].addr = addr;
- icplb_tbl[cpu][idx].data = data;
-#endif
-}
-
-/* Counters to implement round-robin replacement. */
-static int icplb_rr_index[NR_CPUS] PDT_ATTR;
-static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
-
-/*
- * Find an ICPLB entry to be evicted and return its index.
- */
-static int evict_one_icplb(int cpu)
-{
- int i = first_switched_icplb + icplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_icplb;
- icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
- }
- icplb_rr_index[cpu]++;
- return i;
-}
-
-static int evict_one_dcplb(int cpu)
-{
- int i = first_switched_dcplb + dcplb_rr_index[cpu];
- if (i >= MAX_CPLBS) {
- i -= MAX_CPLBS - first_switched_dcplb;
- dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
- }
- dcplb_rr_index[cpu]++;
- return i;
-}
-
-MGR_ATTR static int icplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
- int status = bfin_read_ICPLB_STATUS();
- int idx;
- unsigned long i_data, base, addr1, eaddr;
-
- nr_icplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_icplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = icplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < icplb_nr_bounds);
-
- if (unlikely(idx == icplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- i_data = icplb_bounds[idx].data;
- if (unlikely(i_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr1 = addr & ~(SIZE_4M - 1);
- addr &= ~(SIZE_1M - 1);
- i_data |= PAGE_SIZE_1MB;
- if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- i_data |= PAGE_SIZE_4MB;
- addr = addr1;
- }
-
- /* Pick entry to evict */
- idx = evict_one_icplb(cpu);
-
- write_icplb_data(cpu, idx, i_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR static int dcplb_miss(int cpu)
-{
- unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
- int status = bfin_read_DCPLB_STATUS();
- int idx;
- unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
-
- nr_dcplb_miss[cpu]++;
- if (unlikely(status & FAULT_USERSUPV))
- nr_dcplb_supv_miss[cpu]++;
-
- base = 0;
- idx = 0;
- do {
- eaddr = dcplb_bounds[idx].eaddr;
- if (addr < eaddr)
- break;
- base = eaddr;
- } while (++idx < dcplb_nr_bounds);
-
- if (unlikely(idx == dcplb_nr_bounds))
- return CPLB_NO_ADDR_MATCH;
-
- d_data = dcplb_bounds[idx].data;
- if (unlikely(d_data == 0))
- return CPLB_NO_ADDR_MATCH;
-
- addr &= ~(SIZE_1M - 1);
- d_data |= PAGE_SIZE_1MB;
-
- /* BF60x support large than 4M CPLB page size */
-#ifdef PAGE_SIZE_16MB
- cplb_pageflags = PAGE_SIZE_16MB;
- cplb_pagesize = SIZE_16M;
-#else
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
-#endif
-
-find_pagesize:
- addr1 = addr & ~(cplb_pagesize - 1);
- if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
- /*
- * This works because
- * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
- */
- d_data |= cplb_pageflags;
- addr = addr1;
- goto found_pagesize;
- } else {
- if (cplb_pagesize > SIZE_4M) {
- cplb_pageflags = PAGE_SIZE_4MB;
- cplb_pagesize = SIZE_4M;
- goto find_pagesize;
- }
- }
-
-found_pagesize:
-#ifdef CONFIG_BF60x
- if ((addr >= ASYNC_BANK0_BASE)
- && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
- d_data |= PAGE_SIZE_64MB;
-#endif
-
- /* Pick entry to evict */
- idx = evict_one_dcplb(cpu);
-
- write_dcplb_data(cpu, idx, d_data, addr);
-
- return CPLB_RELOADED;
-}
-
-MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
-{
- int cause = seqstat & 0x3f;
- unsigned int cpu = raw_smp_processor_id();
- switch (cause) {
- case VEC_CPLB_I_M:
- return icplb_miss(cpu);
- case VEC_CPLB_M:
- return dcplb_miss(cpu);
- default:
- return CPLB_UNKNOWN_ERR;
- }
-}
diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c
deleted file mode 100644
index 5b80d59e66e5..000000000000
--- a/arch/blackfin/kernel/cplbinfo.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/blackfin/kernel/cplbinfo.c - display CPLB status
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ctype.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/uaccess.h>
-
-#include <asm/cplbinit.h>
-#include <asm/blackfin.h>
-
-static char const page_strtbl[][4] = {
- "1K", "4K", "1M", "4M",
-#ifdef CONFIG_BF60x
- "16K", "64K", "16M", "64M",
-#endif
-};
-#define page(flags) (((flags) & 0x70000) >> 16)
-#define strpage(flags) page_strtbl[page(flags)]
-
-struct cplbinfo_data {
- loff_t pos;
- char cplb_type;
- u32 mem_control;
- struct cplb_entry *tbl;
- int switched;
-};
-
-static void cplbinfo_print_header(struct seq_file *m)
-{
- seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n");
-}
-
-static int cplbinfo_nomore(struct cplbinfo_data *cdata)
-{
- return cdata->pos >= MAX_CPLBS;
-}
-
-static int cplbinfo_show(struct seq_file *m, void *p)
-{
- struct cplbinfo_data *cdata;
- unsigned long data, addr;
- loff_t pos;
-
- cdata = p;
- pos = cdata->pos;
- addr = cdata->tbl[pos].addr;
- data = cdata->tbl[pos].data;
-
- seq_printf(m,
- "%d\t0x%08lx\t%05lx\t%s\t%c\t%c\t%c\t%c\n",
- (int)pos, addr, data, strpage(data),
- (data & CPLB_USER_RD) ? 'Y' : 'N',
- (data & CPLB_USER_WR) ? 'Y' : 'N',
- (data & CPLB_SUPV_WR) ? 'Y' : 'N',
- pos < cdata->switched ? 'N' : 'Y');
-
- return 0;
-}
-
-static void cplbinfo_seq_init(struct cplbinfo_data *cdata, unsigned int cpu)
-{
- if (cdata->cplb_type == 'I') {
- cdata->mem_control = bfin_read_IMEM_CONTROL();
- cdata->tbl = icplb_tbl[cpu];
- cdata->switched = first_switched_icplb;
- } else {
- cdata->mem_control = bfin_read_DMEM_CONTROL();
- cdata->tbl = dcplb_tbl[cpu];
- cdata->switched = first_switched_dcplb;
- }
-}
-
-static void *cplbinfo_start(struct seq_file *m, loff_t *pos)
-{
- struct cplbinfo_data *cdata = m->private;
-
- if (!*pos) {
- seq_printf(m, "%cCPLBs are %sabled: 0x%x\n", cdata->cplb_type,
- (cdata->mem_control & ENDCPLB ? "en" : "dis"),
- cdata->mem_control);
- cplbinfo_print_header(m);
- } else if (cplbinfo_nomore(cdata))
- return NULL;
-
- get_cpu();
- return cdata;
-}
-
-static void *cplbinfo_next(struct seq_file *m, void *p, loff_t *pos)
-{
- struct cplbinfo_data *cdata = p;
- cdata->pos = ++(*pos);
- if (cplbinfo_nomore(cdata))
- return NULL;
- else
- return cdata;
-}
-
-static void cplbinfo_stop(struct seq_file *m, void *p)
-{
- put_cpu();
-}
-
-static const struct seq_operations cplbinfo_sops = {
- .start = cplbinfo_start,
- .next = cplbinfo_next,
- .stop = cplbinfo_stop,
- .show = cplbinfo_show,
-};
-
-#define CPLBINFO_DCPLB_FLAG 0x80000000
-
-static int cplbinfo_open(struct inode *inode, struct file *file)
-{
- char cplb_type;
- unsigned int cpu = (unsigned long)PDE_DATA(file_inode(file));
- int ret;
- struct seq_file *m;
- struct cplbinfo_data *cdata;
-
- cplb_type = cpu & CPLBINFO_DCPLB_FLAG ? 'D' : 'I';
- cpu &= ~CPLBINFO_DCPLB_FLAG;
-
- if (!cpu_online(cpu))
- return -ENODEV;
-
- ret = seq_open_private(file, &cplbinfo_sops, sizeof(*cdata));
- if (ret)
- return ret;
- m = file->private_data;
- cdata = m->private;
-
- cdata->pos = 0;
- cdata->cplb_type = cplb_type;
- cplbinfo_seq_init(cdata, cpu);
-
- return 0;
-}
-
-static const struct file_operations cplbinfo_fops = {
- .open = cplbinfo_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = seq_release_private,
-};
-
-static int __init cplbinfo_init(void)
-{
- struct proc_dir_entry *cplb_dir, *cpu_dir;
- char buf[10];
- unsigned int cpu;
-
- cplb_dir = proc_mkdir("cplbinfo", NULL);
- if (!cplb_dir)
- return -ENOMEM;
-
- for_each_possible_cpu(cpu) {
- sprintf(buf, "cpu%i", cpu);
- cpu_dir = proc_mkdir(buf, cplb_dir);
- if (!cpu_dir)
- return -ENOMEM;
-
- proc_create_data("icplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)cpu);
- proc_create_data("dcplb", S_IRUGO, cpu_dir, &cplbinfo_fops,
- (void *)(cpu | CPLBINFO_DCPLB_FLAG));
- }
-
- return 0;
-}
-late_initcall(cplbinfo_init);
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
deleted file mode 100644
index 194773ce109e..000000000000
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ /dev/null
@@ -1,1891 +0,0 @@
-/*
- * debugfs interface to core/system MMRs
- *
- * Copyright 2007-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/debugfs.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/bfin_ppi.h>
-#include <asm/bfin_serial.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_twi.h>
-#include <asm/gpio.h>
-
-/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
-#ifdef BFIN_PORT_MUX
-#undef PORT_MUX
-#define PORT_MUX BFIN_PORT_MUX
-#endif
-
-#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
-#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
-#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
-#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
-
-#define D_RO(name, bits) d_RO(#name, bits, name)
-#define D_WO(name, bits) d_WO(#name, bits, name)
-#define D32(name) d(#name, 32, name)
-#define D16(name) d(#name, 16, name)
-
-#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
-#define __REGS(peri, sname, rname) \
- do { \
- struct bfin_##peri##_regs r; \
- void *addr = (void *)(base + REGS_OFF(peri, rname)); \
- strcpy(_buf, sname); \
- if (sizeof(r.rname) == 2) \
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
- else \
- debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
- } while (0)
-#define REGS_STR_PFX(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%i_", num) : \
- sprintf(buf, #pfx "_")); \
- })
-#define REGS_STR_PFX_C(buf, pfx, num) \
- ({ \
- buf + (num >= 0 ? \
- sprintf(buf, #pfx "%c_", 'A' + num) : \
- sprintf(buf, #pfx "_")); \
- })
-
-/*
- * Core registers (not memory mapped)
- */
-extern u32 last_seqstat;
-
-static int debug_cclk_get(void *data, u64 *val)
-{
- *val = get_cclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
-
-static int debug_sclk_get(void *data, u64 *val)
-{
- *val = get_sclk();
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
-
-#define DEFINE_SYSREG(sr, pre, post) \
-static int sysreg_##sr##_get(void *data, u64 *val) \
-{ \
- unsigned long tmp; \
- pre; \
- __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
- *val = tmp; \
- return 0; \
-} \
-static int sysreg_##sr##_set(void *data, u64 val) \
-{ \
- unsigned long tmp = val; \
- __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
- post; \
- return 0; \
-} \
-DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
-
-DEFINE_SYSREG(cycles, , );
-DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
-DEFINE_SYSREG(emudat, , );
-DEFINE_SYSREG(seqstat, , );
-DEFINE_SYSREG(syscfg, , CSYNC());
-#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
-
-#ifndef CONFIG_BF60x
-/*
- * CAN
- */
-#define CAN_OFF(mmr) REGS_OFF(can, mmr)
-#define __CAN(uname, lname) __REGS(can, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
-{
- static struct dentry *am, *mb;
- int i, j;
- char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
-
- if (!am) {
- am = debugfs_create_dir("am", parent);
- mb = debugfs_create_dir("mb", parent);
- }
-
- __CAN(MC1, mc1);
- __CAN(MD1, md1);
- __CAN(TRS1, trs1);
- __CAN(TRR1, trr1);
- __CAN(TA1, ta1);
- __CAN(AA1, aa1);
- __CAN(RMP1, rmp1);
- __CAN(RML1, rml1);
- __CAN(MBTIF1, mbtif1);
- __CAN(MBRIF1, mbrif1);
- __CAN(MBIM1, mbim1);
- __CAN(RFH1, rfh1);
- __CAN(OPSS1, opss1);
-
- __CAN(MC2, mc2);
- __CAN(MD2, md2);
- __CAN(TRS2, trs2);
- __CAN(TRR2, trr2);
- __CAN(TA2, ta2);
- __CAN(AA2, aa2);
- __CAN(RMP2, rmp2);
- __CAN(RML2, rml2);
- __CAN(MBTIF2, mbtif2);
- __CAN(MBRIF2, mbrif2);
- __CAN(MBIM2, mbim2);
- __CAN(RFH2, rfh2);
- __CAN(OPSS2, opss2);
-
- __CAN(CLOCK, clock);
- __CAN(TIMING, timing);
- __CAN(DEBUG, debug);
- __CAN(STATUS, status);
- __CAN(CEC, cec);
- __CAN(GIS, gis);
- __CAN(GIM, gim);
- __CAN(GIF, gif);
- __CAN(CONTROL, control);
- __CAN(INTR, intr);
- __CAN(VERSION, version);
- __CAN(MBTD, mbtd);
- __CAN(EWR, ewr);
- __CAN(ESR, esr);
- /*__CAN(UCREG, ucreg); no longer exists */
- __CAN(UCCNT, uccnt);
- __CAN(UCRC, ucrc);
- __CAN(UCCNF, uccnf);
- __CAN(VERSION2, version2);
-
- for (i = 0; i < 32; ++i) {
- sprintf(_buf, "AM%02iL", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].aml)));
- sprintf(_buf, "AM%02iH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
- (u16 *)(base + CAN_OFF(msk[i].amh)));
-
- for (j = 0; j < 3; ++j) {
- sprintf(_buf, "MB%02i_DATA%i", i, j);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
- }
- sprintf(_buf, "MB%02i_LENGTH", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].dlc)));
- sprintf(_buf, "MB%02i_TIMESTAMP", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].tsv)));
- sprintf(_buf, "MB%02i_ID0", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id0)));
- sprintf(_buf, "MB%02i_ID1", i);
- debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
- (u16 *)(base + CAN_OFF(chl[i].id1)));
- }
-}
-#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
-
-/*
- * DMA
- */
-#define __DMA(uname, lname) __REGS(dma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
-{
- char buf[32], *_buf;
-
- if (mdma)
- _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
- else
- _buf = buf + sprintf(buf, "%s%i_", pfx, num);
-
- __DMA(NEXT_DESC_PTR, next_desc_ptr);
- __DMA(START_ADDR, start_addr);
- __DMA(CONFIG, config);
- __DMA(X_COUNT, x_count);
- __DMA(X_MODIFY, x_modify);
- __DMA(Y_COUNT, y_count);
- __DMA(Y_MODIFY, y_modify);
- __DMA(CURR_DESC_PTR, curr_desc_ptr);
- __DMA(CURR_ADDR, curr_addr);
- __DMA(IRQ_STATUS, irq_status);
-#ifndef CONFIG_BF60x
- if (strcmp(pfx, "IMDMA") != 0)
- __DMA(PERIPHERAL_MAP, peripheral_map);
-#endif
- __DMA(CURR_X_COUNT, curr_x_count);
- __DMA(CURR_Y_COUNT, curr_y_count);
-}
-#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
-#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
-#define _MDMA(num, x) \
- do { \
- _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
- _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
- } while (0)
-#define MDMA(num) _MDMA(num, M)
-#define IMDMA(num) _MDMA(num, IM)
-
-/*
- * EPPI
- */
-#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
- __EPPI(STATUS, status);
- __EPPI(HCOUNT, hcount);
- __EPPI(HDELAY, hdelay);
- __EPPI(VCOUNT, vcount);
- __EPPI(VDELAY, vdelay);
- __EPPI(FRAME, frame);
- __EPPI(LINE, line);
- __EPPI(CLKDIV, clkdiv);
- __EPPI(CONTROL, control);
- __EPPI(FS1W_HBL, fs1w_hbl);
- __EPPI(FS1P_AVPL, fs1p_avpl);
- __EPPI(FS2W_LVB, fs2w_lvb);
- __EPPI(FS2P_LAVF, fs2p_lavf);
- __EPPI(CLIP, clip);
-}
-#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
-
-/*
- * General Purpose Timers
- */
-#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
- __GPTIMER(CONFIG, config);
- __GPTIMER(COUNTER, counter);
- __GPTIMER(PERIOD, period);
- __GPTIMER(WIDTH, width);
-}
-#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
-
-#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
-#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-
- if (num == -1) {
- _buf = buf + sprintf(buf, "TIMER_");
- __GPTIMER_GROUP(ENABLE, enable);
- __GPTIMER_GROUP(DISABLE, disable);
- __GPTIMER_GROUP(STATUS, status);
- } else {
- /* These MMRs are a bit odd as the group # is a suffix */
- _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
-
- _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
- d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
-
- _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
- d(buf, 32, base + GPTIMER_GROUP_OFF(status));
- }
-}
-#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
-
-/*
- * Handshake MDMA
- */
-#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
- __HMDMA(CONTROL, control);
- __HMDMA(ECINIT, ecinit);
- __HMDMA(BCINIT, bcinit);
- __HMDMA(ECURGENT, ecurgent);
- __HMDMA(ECOVERFLOW, ecoverflow);
- __HMDMA(ECOUNT, ecount);
- __HMDMA(BCOUNT, bcount);
-}
-#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
-
-/*
- * Peripheral Interrupts (PINT/GPIO)
- */
-#ifdef PINT0_MASK_SET
-#define __PINT(uname, lname) __REGS(pint, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
- __PINT(MASK_SET, mask_set);
- __PINT(MASK_CLEAR, mask_clear);
- __PINT(REQUEST, request);
- __PINT(ASSIGN, assign);
- __PINT(EDGE_SET, edge_set);
- __PINT(EDGE_CLEAR, edge_clear);
- __PINT(INVERT_SET, invert_set);
- __PINT(INVERT_CLEAR, invert_clear);
- __PINT(PINSTATE, pinstate);
- __PINT(LATCH, latch);
-}
-#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
-#endif
-
-/*
- * Port/GPIO
- */
-#define bfin_gpio_regs gpio_port_t
-#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf;
-#ifdef __ADSPBF54x__
- _buf = REGS_STR_PFX_C(buf, PORT, num);
- __PORT(FER, port_fer);
- __PORT(SET, data_set);
- __PORT(CLEAR, data_clear);
- __PORT(DIR_SET, dir_set);
- __PORT(DIR_CLEAR, dir_clear);
- __PORT(INEN, inen);
- __PORT(MUX, port_mux);
-#else
- _buf = buf + sprintf(buf, "PORT%cIO_", num);
- __PORT(CLEAR, data_clear);
- __PORT(SET, data_set);
- __PORT(TOGGLE, toggle);
- __PORT(MASKA, maska);
- __PORT(MASKA_CLEAR, maska_clear);
- __PORT(MASKA_SET, maska_set);
- __PORT(MASKA_TOGGLE, maska_toggle);
- __PORT(MASKB, maskb);
- __PORT(MASKB_CLEAR, maskb_clear);
- __PORT(MASKB_SET, maskb_set);
- __PORT(MASKB_TOGGLE, maskb_toggle);
- __PORT(DIR, dir);
- __PORT(POLAR, polar);
- __PORT(EDGE, edge);
- __PORT(BOTH, both);
- __PORT(INEN, inen);
-#endif
- _buf[-1] = '\0';
- d(buf, 16, base + REGS_OFF(gpio, data));
-}
-#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
-
-/*
- * PPI
- */
-#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
- __PPI(CONTROL, control);
- __PPI(STATUS, status);
- __PPI(COUNT, count);
- __PPI(DELAY, delay);
- __PPI(FRAME, frame);
-}
-#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
-
-/*
- * SPI
- */
-#define __SPI(uname, lname) __REGS(spi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
- __SPI(CTL, ctl);
- __SPI(FLG, flg);
- __SPI(STAT, stat);
- __SPI(TDBR, tdbr);
- __SPI(RDBR, rdbr);
- __SPI(BAUD, baud);
- __SPI(SHADOW, shadow);
-}
-#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
-
-/*
- * SPORT
- */
-static inline int sport_width(void *mmr)
-{
- unsigned long lmmr = (unsigned long)mmr;
- if ((lmmr & 0xff) == 0x10)
- /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
- lmmr -= 0xc;
- else
- /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
- lmmr += 0xc;
- /* extract SLEN field from control register 2 and add 1 */
- return (bfin_read16(lmmr) & 0x1f) + 1;
-}
-static int sport_set(void *mmr, u64 val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- bfin_write16(mmr, val);
- else
- bfin_write32(mmr, val);
- local_irq_restore(flags);
- return 0;
-}
-static int sport_get(void *mmr, u64 *val)
-{
- unsigned long flags;
- local_irq_save(flags);
- if (sport_width(mmr) <= 16)
- *val = bfin_read16(mmr);
- else
- *val = bfin_read32(mmr);
- local_irq_restore(flags);
- return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
-/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
-DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
-#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
-#define _D_SPORT(name, perms, fops) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
- } while (0)
-#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
-#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
-#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
-#define __SPORT(name, bits) \
- do { \
- strcpy(_buf, #name); \
- debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
- } while (0)
-static void __init __maybe_unused
-bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
- __SPORT(CHNL, 16);
- __SPORT(MCMC1, 16);
- __SPORT(MCMC2, 16);
- __SPORT(MRCS0, 32);
- __SPORT(MRCS1, 32);
- __SPORT(MRCS2, 32);
- __SPORT(MRCS3, 32);
- __SPORT(MTCS0, 32);
- __SPORT(MTCS1, 32);
- __SPORT(MTCS2, 32);
- __SPORT(MTCS3, 32);
- __SPORT(RCLKDIV, 16);
- __SPORT(RCR1, 16);
- __SPORT(RCR2, 16);
- __SPORT(RFSDIV, 16);
- __SPORT_RW(RX);
- __SPORT(STAT, 16);
- __SPORT(TCLKDIV, 16);
- __SPORT(TCR1, 16);
- __SPORT(TCR2, 16);
- __SPORT(TFSDIV, 16);
- __SPORT_WO(TX);
-}
-#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
-
-/*
- * TWI
- */
-#define __TWI(uname, lname) __REGS(twi, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
- __TWI(CLKDIV, clkdiv);
- __TWI(CONTROL, control);
- __TWI(SLAVE_CTL, slave_ctl);
- __TWI(SLAVE_STAT, slave_stat);
- __TWI(SLAVE_ADDR, slave_addr);
- __TWI(MASTER_CTL, master_ctl);
- __TWI(MASTER_STAT, master_stat);
- __TWI(MASTER_ADDR, master_addr);
- __TWI(INT_STAT, int_stat);
- __TWI(INT_MASK, int_mask);
- __TWI(FIFO_CTL, fifo_ctl);
- __TWI(FIFO_STAT, fifo_stat);
- __TWI(XMT_DATA8, xmt_data8);
- __TWI(XMT_DATA16, xmt_data16);
- __TWI(RCV_DATA8, rcv_data8);
- __TWI(RCV_DATA16, rcv_data16);
-}
-#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
-
-/*
- * UART
- */
-#define __UART(uname, lname) __REGS(uart, #uname, lname)
-static void __init __maybe_unused
-bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
-{
- char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
-#ifdef BFIN_UART_BF54X_STYLE
- __UART(DLL, dll);
- __UART(DLH, dlh);
- __UART(GCTL, gctl);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(IER_SET, ier_set);
- __UART(IER_CLEAR, ier_clear);
- __UART(THR, thr);
- __UART(RBR, rbr);
-#else
- __UART(DLL, dll);
- __UART(THR, thr);
- __UART(RBR, rbr);
- __UART(DLH, dlh);
- __UART(IER, ier);
- __UART(IIR, iir);
- __UART(LCR, lcr);
- __UART(MCR, mcr);
- __UART(LSR, lsr);
- __UART(MSR, msr);
- __UART(SCR, scr);
- __UART(GCTL, gctl);
-#endif
-}
-#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
-#endif /* CONFIG_BF60x */
-/*
- * The actual debugfs generation
- */
-static struct dentry *debug_mmrs_dentry;
-
-static int __init bfin_debug_mmrs_init(void)
-{
- struct dentry *top, *parent;
-
- pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
-
- top = debugfs_create_dir("blackfin", NULL);
- if (top == NULL)
- return -1;
-
- parent = debugfs_create_dir("core_regs", top);
- debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
- debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
- debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
- D_SYSREG(cycles);
- D_SYSREG(cycles2);
- D_SYSREG(emudat);
- D_SYSREG(seqstat);
- D_SYSREG(syscfg);
-
- /* Core MMRs */
- parent = debugfs_create_dir("ctimer", top);
- D32(TCNTL);
- D32(TCOUNT);
- D32(TPERIOD);
- D32(TSCALE);
-
- parent = debugfs_create_dir("cec", top);
- D32(EVT0);
- D32(EVT1);
- D32(EVT2);
- D32(EVT3);
- D32(EVT4);
- D32(EVT5);
- D32(EVT6);
- D32(EVT7);
- D32(EVT8);
- D32(EVT9);
- D32(EVT10);
- D32(EVT11);
- D32(EVT12);
- D32(EVT13);
- D32(EVT14);
- D32(EVT15);
- D32(EVT_OVERRIDE);
- D32(IMASK);
- D32(IPEND);
- D32(ILAT);
- D32(IPRIO);
-
- parent = debugfs_create_dir("debug", top);
- D32(DBGSTAT);
- D32(DSPID);
-
- parent = debugfs_create_dir("mmu", top);
- D32(SRAM_BASE_ADDRESS);
- D32(DCPLB_ADDR0);
- D32(DCPLB_ADDR10);
- D32(DCPLB_ADDR11);
- D32(DCPLB_ADDR12);
- D32(DCPLB_ADDR13);
- D32(DCPLB_ADDR14);
- D32(DCPLB_ADDR15);
- D32(DCPLB_ADDR1);
- D32(DCPLB_ADDR2);
- D32(DCPLB_ADDR3);
- D32(DCPLB_ADDR4);
- D32(DCPLB_ADDR5);
- D32(DCPLB_ADDR6);
- D32(DCPLB_ADDR7);
- D32(DCPLB_ADDR8);
- D32(DCPLB_ADDR9);
- D32(DCPLB_DATA0);
- D32(DCPLB_DATA10);
- D32(DCPLB_DATA11);
- D32(DCPLB_DATA12);
- D32(DCPLB_DATA13);
- D32(DCPLB_DATA14);
- D32(DCPLB_DATA15);
- D32(DCPLB_DATA1);
- D32(DCPLB_DATA2);
- D32(DCPLB_DATA3);
- D32(DCPLB_DATA4);
- D32(DCPLB_DATA5);
- D32(DCPLB_DATA6);
- D32(DCPLB_DATA7);
- D32(DCPLB_DATA8);
- D32(DCPLB_DATA9);
- D32(DCPLB_FAULT_ADDR);
- D32(DCPLB_STATUS);
- D32(DMEM_CONTROL);
- D32(DTEST_COMMAND);
- D32(DTEST_DATA0);
- D32(DTEST_DATA1);
-
- D32(ICPLB_ADDR0);
- D32(ICPLB_ADDR1);
- D32(ICPLB_ADDR2);
- D32(ICPLB_ADDR3);
- D32(ICPLB_ADDR4);
- D32(ICPLB_ADDR5);
- D32(ICPLB_ADDR6);
- D32(ICPLB_ADDR7);
- D32(ICPLB_ADDR8);
- D32(ICPLB_ADDR9);
- D32(ICPLB_ADDR10);
- D32(ICPLB_ADDR11);
- D32(ICPLB_ADDR12);
- D32(ICPLB_ADDR13);
- D32(ICPLB_ADDR14);
- D32(ICPLB_ADDR15);
- D32(ICPLB_DATA0);
- D32(ICPLB_DATA1);
- D32(ICPLB_DATA2);
- D32(ICPLB_DATA3);
- D32(ICPLB_DATA4);
- D32(ICPLB_DATA5);
- D32(ICPLB_DATA6);
- D32(ICPLB_DATA7);
- D32(ICPLB_DATA8);
- D32(ICPLB_DATA9);
- D32(ICPLB_DATA10);
- D32(ICPLB_DATA11);
- D32(ICPLB_DATA12);
- D32(ICPLB_DATA13);
- D32(ICPLB_DATA14);
- D32(ICPLB_DATA15);
- D32(ICPLB_FAULT_ADDR);
- D32(ICPLB_STATUS);
- D32(IMEM_CONTROL);
- if (!ANOMALY_05000481) {
- D32(ITEST_COMMAND);
- D32(ITEST_DATA0);
- D32(ITEST_DATA1);
- }
-
- parent = debugfs_create_dir("perf", top);
- D32(PFCNTR0);
- D32(PFCNTR1);
- D32(PFCTL);
-
- parent = debugfs_create_dir("trace", top);
- D32(TBUF);
- D32(TBUFCTL);
- D32(TBUFSTAT);
-
- parent = debugfs_create_dir("watchpoint", top);
- D32(WPIACTL);
- D32(WPIA0);
- D32(WPIA1);
- D32(WPIA2);
- D32(WPIA3);
- D32(WPIA4);
- D32(WPIA5);
- D32(WPIACNT0);
- D32(WPIACNT1);
- D32(WPIACNT2);
- D32(WPIACNT3);
- D32(WPIACNT4);
- D32(WPIACNT5);
- D32(WPDACTL);
- D32(WPDA0);
- D32(WPDA1);
- D32(WPDACNT0);
- D32(WPDACNT1);
- D32(WPSTAT);
-#ifndef CONFIG_BF60x
- /* System MMRs */
-#ifdef ATAPI_CONTROL
- parent = debugfs_create_dir("atapi", top);
- D16(ATAPI_CONTROL);
- D16(ATAPI_DEV_ADDR);
- D16(ATAPI_DEV_RXBUF);
- D16(ATAPI_DEV_TXBUF);
- D16(ATAPI_DMA_TFRCNT);
- D16(ATAPI_INT_MASK);
- D16(ATAPI_INT_STATUS);
- D16(ATAPI_LINE_STATUS);
- D16(ATAPI_MULTI_TIM_0);
- D16(ATAPI_MULTI_TIM_1);
- D16(ATAPI_MULTI_TIM_2);
- D16(ATAPI_PIO_TFRCNT);
- D16(ATAPI_PIO_TIM_0);
- D16(ATAPI_PIO_TIM_1);
- D16(ATAPI_REG_TIM_0);
- D16(ATAPI_SM_STATE);
- D16(ATAPI_STATUS);
- D16(ATAPI_TERMINATE);
- D16(ATAPI_UDMAOUT_TFRCNT);
- D16(ATAPI_ULTRA_TIM_0);
- D16(ATAPI_ULTRA_TIM_1);
- D16(ATAPI_ULTRA_TIM_2);
- D16(ATAPI_ULTRA_TIM_3);
- D16(ATAPI_UMAIN_TFRCNT);
- D16(ATAPI_XFER_LEN);
-#endif
-
-#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
- parent = debugfs_create_dir("can", top);
-# ifdef CAN_MC1
- bfin_debug_mmrs_can(parent, CAN_MC1, -1);
-# endif
-# ifdef CAN0_MC1
- CAN(0);
-# endif
-# ifdef CAN1_MC1
- CAN(1);
-# endif
-#endif
-
-#ifdef CNT_COMMAND
- parent = debugfs_create_dir("counter", top);
- D16(CNT_COMMAND);
- D16(CNT_CONFIG);
- D32(CNT_COUNTER);
- D16(CNT_DEBOUNCE);
- D16(CNT_IMASK);
- D32(CNT_MAX);
- D32(CNT_MIN);
- D16(CNT_STATUS);
-#endif
-
- parent = debugfs_create_dir("dmac", top);
-#ifdef DMAC_TC_CNT
- D16(DMAC_TC_CNT);
- D16(DMAC_TC_PER);
-#endif
-#ifdef DMAC0_TC_CNT
- D16(DMAC0_TC_CNT);
- D16(DMAC0_TC_PER);
-#endif
-#ifdef DMAC1_TC_CNT
- D16(DMAC1_TC_CNT);
- D16(DMAC1_TC_PER);
-#endif
-#ifdef DMAC1_PERIMUX
- D16(DMAC1_PERIMUX);
-#endif
-
-#ifdef __ADSPBF561__
- /* XXX: should rewrite the MMR map */
-# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
-# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
-# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
-# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
-# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
-# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
-# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
-# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
-# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
-# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
-# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
-# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
-# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
-# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
-# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
-# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
-# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
-# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
-# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
-# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
-# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
-# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
-# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
-# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
-#endif
- parent = debugfs_create_dir("dma", top);
- DMA(0);
- DMA(1);
- DMA(1);
- DMA(2);
- DMA(3);
- DMA(4);
- DMA(5);
- DMA(6);
- DMA(7);
-#ifdef DMA8_NEXT_DESC_PTR
- DMA(8);
- DMA(9);
- DMA(10);
- DMA(11);
-#endif
-#ifdef DMA12_NEXT_DESC_PTR
- DMA(12);
- DMA(13);
- DMA(14);
- DMA(15);
- DMA(16);
- DMA(17);
- DMA(18);
- DMA(19);
-#endif
-#ifdef DMA20_NEXT_DESC_PTR
- DMA(20);
- DMA(21);
- DMA(22);
- DMA(23);
-#endif
-
- parent = debugfs_create_dir("ebiu_amc", top);
- D32(EBIU_AMBCTL0);
- D32(EBIU_AMBCTL1);
- D16(EBIU_AMGCTL);
-#ifdef EBIU_MBSCTL
- D16(EBIU_MBSCTL);
- D32(EBIU_ARBSTAT);
- D32(EBIU_MODE);
- D16(EBIU_FCTL);
-#endif
-
-#ifdef EBIU_SDGCTL
- parent = debugfs_create_dir("ebiu_sdram", top);
-# ifdef __ADSPBF561__
- D32(EBIU_SDBCTL);
-# else
- D16(EBIU_SDBCTL);
-# endif
- D32(EBIU_SDGCTL);
- D16(EBIU_SDRRC);
- D16(EBIU_SDSTAT);
-#endif
-
-#ifdef EBIU_DDRACCT
- parent = debugfs_create_dir("ebiu_ddr", top);
- D32(EBIU_DDRACCT);
- D32(EBIU_DDRARCT);
- D32(EBIU_DDRBRC0);
- D32(EBIU_DDRBRC1);
- D32(EBIU_DDRBRC2);
- D32(EBIU_DDRBRC3);
- D32(EBIU_DDRBRC4);
- D32(EBIU_DDRBRC5);
- D32(EBIU_DDRBRC6);
- D32(EBIU_DDRBRC7);
- D32(EBIU_DDRBWC0);
- D32(EBIU_DDRBWC1);
- D32(EBIU_DDRBWC2);
- D32(EBIU_DDRBWC3);
- D32(EBIU_DDRBWC4);
- D32(EBIU_DDRBWC5);
- D32(EBIU_DDRBWC6);
- D32(EBIU_DDRBWC7);
- D32(EBIU_DDRCTL0);
- D32(EBIU_DDRCTL1);
- D32(EBIU_DDRCTL2);
- D32(EBIU_DDRCTL3);
- D32(EBIU_DDRGC0);
- D32(EBIU_DDRGC1);
- D32(EBIU_DDRGC2);
- D32(EBIU_DDRGC3);
- D32(EBIU_DDRMCCL);
- D32(EBIU_DDRMCEN);
- D32(EBIU_DDRQUE);
- D32(EBIU_DDRTACT);
- D32(EBIU_ERRADD);
- D16(EBIU_ERRMST);
- D16(EBIU_RSTCTL);
-#endif
-
-#ifdef EMAC_ADDRHI
- parent = debugfs_create_dir("emac", top);
- D32(EMAC_ADDRHI);
- D32(EMAC_ADDRLO);
- D32(EMAC_FLC);
- D32(EMAC_HASHHI);
- D32(EMAC_HASHLO);
- D32(EMAC_MMC_CTL);
- D32(EMAC_MMC_RIRQE);
- D32(EMAC_MMC_RIRQS);
- D32(EMAC_MMC_TIRQE);
- D32(EMAC_MMC_TIRQS);
- D32(EMAC_OPMODE);
- D32(EMAC_RXC_ALIGN);
- D32(EMAC_RXC_ALLFRM);
- D32(EMAC_RXC_ALLOCT);
- D32(EMAC_RXC_BROAD);
- D32(EMAC_RXC_DMAOVF);
- D32(EMAC_RXC_EQ64);
- D32(EMAC_RXC_FCS);
- D32(EMAC_RXC_GE1024);
- D32(EMAC_RXC_LNERRI);
- D32(EMAC_RXC_LNERRO);
- D32(EMAC_RXC_LONG);
- D32(EMAC_RXC_LT1024);
- D32(EMAC_RXC_LT128);
- D32(EMAC_RXC_LT256);
- D32(EMAC_RXC_LT512);
- D32(EMAC_RXC_MACCTL);
- D32(EMAC_RXC_MULTI);
- D32(EMAC_RXC_OCTET);
- D32(EMAC_RXC_OK);
- D32(EMAC_RXC_OPCODE);
- D32(EMAC_RXC_PAUSE);
- D32(EMAC_RXC_SHORT);
- D32(EMAC_RXC_TYPED);
- D32(EMAC_RXC_UNICST);
- D32(EMAC_RX_IRQE);
- D32(EMAC_RX_STAT);
- D32(EMAC_RX_STKY);
- D32(EMAC_STAADD);
- D32(EMAC_STADAT);
- D32(EMAC_SYSCTL);
- D32(EMAC_SYSTAT);
- D32(EMAC_TXC_1COL);
- D32(EMAC_TXC_ABORT);
- D32(EMAC_TXC_ALLFRM);
- D32(EMAC_TXC_ALLOCT);
- D32(EMAC_TXC_BROAD);
- D32(EMAC_TXC_CRSERR);
- D32(EMAC_TXC_DEFER);
- D32(EMAC_TXC_DMAUND);
- D32(EMAC_TXC_EQ64);
- D32(EMAC_TXC_GE1024);
- D32(EMAC_TXC_GT1COL);
- D32(EMAC_TXC_LATECL);
- D32(EMAC_TXC_LT1024);
- D32(EMAC_TXC_LT128);
- D32(EMAC_TXC_LT256);
- D32(EMAC_TXC_LT512);
- D32(EMAC_TXC_MACCTL);
- D32(EMAC_TXC_MULTI);
- D32(EMAC_TXC_OCTET);
- D32(EMAC_TXC_OK);
- D32(EMAC_TXC_UNICST);
- D32(EMAC_TXC_XS_COL);
- D32(EMAC_TXC_XS_DFR);
- D32(EMAC_TX_IRQE);
- D32(EMAC_TX_STAT);
- D32(EMAC_TX_STKY);
- D32(EMAC_VLAN1);
- D32(EMAC_VLAN2);
- D32(EMAC_WKUP_CTL);
- D32(EMAC_WKUP_FFCMD);
- D32(EMAC_WKUP_FFCRC0);
- D32(EMAC_WKUP_FFCRC1);
- D32(EMAC_WKUP_FFMSK0);
- D32(EMAC_WKUP_FFMSK1);
- D32(EMAC_WKUP_FFMSK2);
- D32(EMAC_WKUP_FFMSK3);
- D32(EMAC_WKUP_FFOFF);
-# ifdef EMAC_PTP_ACCR
- D32(EMAC_PTP_ACCR);
- D32(EMAC_PTP_ADDEND);
- D32(EMAC_PTP_ALARMHI);
- D32(EMAC_PTP_ALARMLO);
- D16(EMAC_PTP_CTL);
- D32(EMAC_PTP_FOFF);
- D32(EMAC_PTP_FV1);
- D32(EMAC_PTP_FV2);
- D32(EMAC_PTP_FV3);
- D16(EMAC_PTP_ID_OFF);
- D32(EMAC_PTP_ID_SNAP);
- D16(EMAC_PTP_IE);
- D16(EMAC_PTP_ISTAT);
- D32(EMAC_PTP_OFFSET);
- D32(EMAC_PTP_PPS_PERIOD);
- D32(EMAC_PTP_PPS_STARTHI);
- D32(EMAC_PTP_PPS_STARTLO);
- D32(EMAC_PTP_RXSNAPHI);
- D32(EMAC_PTP_RXSNAPLO);
- D32(EMAC_PTP_TIMEHI);
- D32(EMAC_PTP_TIMELO);
- D32(EMAC_PTP_TXSNAPHI);
- D32(EMAC_PTP_TXSNAPLO);
-# endif
-#endif
-
-#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
- parent = debugfs_create_dir("eppi", top);
-# ifdef EPPI0_STATUS
- EPPI(0);
-# endif
-# ifdef EPPI1_STATUS
- EPPI(1);
-# endif
-# ifdef EPPI2_STATUS
- EPPI(2);
-# endif
-#endif
-
- parent = debugfs_create_dir("gptimer", top);
-#ifdef TIMER_ENABLE
- GPTIMER_GROUP(TIMER_ENABLE, -1);
-#endif
-#ifdef TIMER_ENABLE0
- GPTIMER_GROUP(TIMER_ENABLE0, 0);
-#endif
-#ifdef TIMER_ENABLE1
- GPTIMER_GROUP(TIMER_ENABLE1, 1);
-#endif
- /* XXX: Should convert BF561 MMR names */
-#ifdef TMRS4_DISABLE
- GPTIMER_GROUP(TMRS4_ENABLE, 0);
- GPTIMER_GROUP(TMRS8_ENABLE, 1);
-#endif
- GPTIMER(0);
- GPTIMER(1);
- GPTIMER(2);
-#ifdef TIMER3_CONFIG
- GPTIMER(3);
- GPTIMER(4);
- GPTIMER(5);
- GPTIMER(6);
- GPTIMER(7);
-#endif
-#ifdef TIMER8_CONFIG
- GPTIMER(8);
- GPTIMER(9);
- GPTIMER(10);
-#endif
-#ifdef TIMER11_CONFIG
- GPTIMER(11);
-#endif
-
-#ifdef HMDMA0_CONTROL
- parent = debugfs_create_dir("hmdma", top);
- HMDMA(0);
- HMDMA(1);
-#endif
-
-#ifdef HOST_CONTROL
- parent = debugfs_create_dir("hostdp", top);
- D16(HOST_CONTROL);
- D16(HOST_STATUS);
- D16(HOST_TIMEOUT);
-#endif
-
-#ifdef IMDMA_S0_CONFIG
- parent = debugfs_create_dir("imdma", top);
- IMDMA(0);
- IMDMA(1);
-#endif
-
-#ifdef KPAD_CTL
- parent = debugfs_create_dir("keypad", top);
- D16(KPAD_CTL);
- D16(KPAD_PRESCALE);
- D16(KPAD_MSEL);
- D16(KPAD_ROWCOL);
- D16(KPAD_STAT);
- D16(KPAD_SOFTEVAL);
-#endif
-
- parent = debugfs_create_dir("mdma", top);
- MDMA(0);
- MDMA(1);
-#ifdef MDMA_D2_CONFIG
- MDMA(2);
- MDMA(3);
-#endif
-
-#ifdef MXVR_CONFIG
- parent = debugfs_create_dir("mxvr", top);
- D16(MXVR_CONFIG);
-# ifdef MXVR_PLL_CTL_0
- D32(MXVR_PLL_CTL_0);
-# endif
- D32(MXVR_STATE_0);
- D32(MXVR_STATE_1);
- D32(MXVR_INT_STAT_0);
- D32(MXVR_INT_STAT_1);
- D32(MXVR_INT_EN_0);
- D32(MXVR_INT_EN_1);
- D16(MXVR_POSITION);
- D16(MXVR_MAX_POSITION);
- D16(MXVR_DELAY);
- D16(MXVR_MAX_DELAY);
- D32(MXVR_LADDR);
- D16(MXVR_GADDR);
- D32(MXVR_AADDR);
- D32(MXVR_ALLOC_0);
- D32(MXVR_ALLOC_1);
- D32(MXVR_ALLOC_2);
- D32(MXVR_ALLOC_3);
- D32(MXVR_ALLOC_4);
- D32(MXVR_ALLOC_5);
- D32(MXVR_ALLOC_6);
- D32(MXVR_ALLOC_7);
- D32(MXVR_ALLOC_8);
- D32(MXVR_ALLOC_9);
- D32(MXVR_ALLOC_10);
- D32(MXVR_ALLOC_11);
- D32(MXVR_ALLOC_12);
- D32(MXVR_ALLOC_13);
- D32(MXVR_ALLOC_14);
- D32(MXVR_SYNC_LCHAN_0);
- D32(MXVR_SYNC_LCHAN_1);
- D32(MXVR_SYNC_LCHAN_2);
- D32(MXVR_SYNC_LCHAN_3);
- D32(MXVR_SYNC_LCHAN_4);
- D32(MXVR_SYNC_LCHAN_5);
- D32(MXVR_SYNC_LCHAN_6);
- D32(MXVR_SYNC_LCHAN_7);
- D32(MXVR_DMA0_CONFIG);
- D32(MXVR_DMA0_START_ADDR);
- D16(MXVR_DMA0_COUNT);
- D32(MXVR_DMA0_CURR_ADDR);
- D16(MXVR_DMA0_CURR_COUNT);
- D32(MXVR_DMA1_CONFIG);
- D32(MXVR_DMA1_START_ADDR);
- D16(MXVR_DMA1_COUNT);
- D32(MXVR_DMA1_CURR_ADDR);
- D16(MXVR_DMA1_CURR_COUNT);
- D32(MXVR_DMA2_CONFIG);
- D32(MXVR_DMA2_START_ADDR);
- D16(MXVR_DMA2_COUNT);
- D32(MXVR_DMA2_CURR_ADDR);
- D16(MXVR_DMA2_CURR_COUNT);
- D32(MXVR_DMA3_CONFIG);
- D32(MXVR_DMA3_START_ADDR);
- D16(MXVR_DMA3_COUNT);
- D32(MXVR_DMA3_CURR_ADDR);
- D16(MXVR_DMA3_CURR_COUNT);
- D32(MXVR_DMA4_CONFIG);
- D32(MXVR_DMA4_START_ADDR);
- D16(MXVR_DMA4_COUNT);
- D32(MXVR_DMA4_CURR_ADDR);
- D16(MXVR_DMA4_CURR_COUNT);
- D32(MXVR_DMA5_CONFIG);
- D32(MXVR_DMA5_START_ADDR);
- D16(MXVR_DMA5_COUNT);
- D32(MXVR_DMA5_CURR_ADDR);
- D16(MXVR_DMA5_CURR_COUNT);
- D32(MXVR_DMA6_CONFIG);
- D32(MXVR_DMA6_START_ADDR);
- D16(MXVR_DMA6_COUNT);
- D32(MXVR_DMA6_CURR_ADDR);
- D16(MXVR_DMA6_CURR_COUNT);
- D32(MXVR_DMA7_CONFIG);
- D32(MXVR_DMA7_START_ADDR);
- D16(MXVR_DMA7_COUNT);
- D32(MXVR_DMA7_CURR_ADDR);
- D16(MXVR_DMA7_CURR_COUNT);
- D16(MXVR_AP_CTL);
- D32(MXVR_APRB_START_ADDR);
- D32(MXVR_APRB_CURR_ADDR);
- D32(MXVR_APTB_START_ADDR);
- D32(MXVR_APTB_CURR_ADDR);
- D32(MXVR_CM_CTL);
- D32(MXVR_CMRB_START_ADDR);
- D32(MXVR_CMRB_CURR_ADDR);
- D32(MXVR_CMTB_START_ADDR);
- D32(MXVR_CMTB_CURR_ADDR);
- D32(MXVR_RRDB_START_ADDR);
- D32(MXVR_RRDB_CURR_ADDR);
- D32(MXVR_PAT_DATA_0);
- D32(MXVR_PAT_EN_0);
- D32(MXVR_PAT_DATA_1);
- D32(MXVR_PAT_EN_1);
- D16(MXVR_FRAME_CNT_0);
- D16(MXVR_FRAME_CNT_1);
- D32(MXVR_ROUTING_0);
- D32(MXVR_ROUTING_1);
- D32(MXVR_ROUTING_2);
- D32(MXVR_ROUTING_3);
- D32(MXVR_ROUTING_4);
- D32(MXVR_ROUTING_5);
- D32(MXVR_ROUTING_6);
- D32(MXVR_ROUTING_7);
- D32(MXVR_ROUTING_8);
- D32(MXVR_ROUTING_9);
- D32(MXVR_ROUTING_10);
- D32(MXVR_ROUTING_11);
- D32(MXVR_ROUTING_12);
- D32(MXVR_ROUTING_13);
- D32(MXVR_ROUTING_14);
-# ifdef MXVR_PLL_CTL_1
- D32(MXVR_PLL_CTL_1);
-# endif
- D16(MXVR_BLOCK_CNT);
-# ifdef MXVR_CLK_CTL
- D32(MXVR_CLK_CTL);
-# endif
-# ifdef MXVR_CDRPLL_CTL
- D32(MXVR_CDRPLL_CTL);
-# endif
-# ifdef MXVR_FMPLL_CTL
- D32(MXVR_FMPLL_CTL);
-# endif
-# ifdef MXVR_PIN_CTL
- D16(MXVR_PIN_CTL);
-# endif
-# ifdef MXVR_SCLK_CNT
- D16(MXVR_SCLK_CNT);
-# endif
-#endif
-
-#ifdef NFC_ADDR
- parent = debugfs_create_dir("nfc", top);
- D_WO(NFC_ADDR, 16);
- D_WO(NFC_CMD, 16);
- D_RO(NFC_COUNT, 16);
- D16(NFC_CTL);
- D_WO(NFC_DATA_RD, 16);
- D_WO(NFC_DATA_WR, 16);
- D_RO(NFC_ECC0, 16);
- D_RO(NFC_ECC1, 16);
- D_RO(NFC_ECC2, 16);
- D_RO(NFC_ECC3, 16);
- D16(NFC_IRQMASK);
- D16(NFC_IRQSTAT);
- D_WO(NFC_PGCTL, 16);
- D_RO(NFC_READ, 16);
- D16(NFC_RST);
- D_RO(NFC_STAT, 16);
-#endif
-
-#ifdef OTP_CONTROL
- parent = debugfs_create_dir("otp", top);
- D16(OTP_CONTROL);
- D16(OTP_BEN);
- D16(OTP_STATUS);
- D32(OTP_TIMING);
- D32(OTP_DATA0);
- D32(OTP_DATA1);
- D32(OTP_DATA2);
- D32(OTP_DATA3);
-#endif
-
-#ifdef PINT0_MASK_SET
- parent = debugfs_create_dir("pint", top);
- PINT(0);
- PINT(1);
- PINT(2);
- PINT(3);
-#endif
-
-#ifdef PIXC_CTL
- parent = debugfs_create_dir("pixc", top);
- D16(PIXC_CTL);
- D16(PIXC_PPL);
- D16(PIXC_LPF);
- D16(PIXC_AHSTART);
- D16(PIXC_AHEND);
- D16(PIXC_AVSTART);
- D16(PIXC_AVEND);
- D16(PIXC_ATRANSP);
- D16(PIXC_BHSTART);
- D16(PIXC_BHEND);
- D16(PIXC_BVSTART);
- D16(PIXC_BVEND);
- D16(PIXC_BTRANSP);
- D16(PIXC_INTRSTAT);
- D32(PIXC_RYCON);
- D32(PIXC_GUCON);
- D32(PIXC_BVCON);
- D32(PIXC_CCBIAS);
- D32(PIXC_TC);
-#endif
-
- parent = debugfs_create_dir("pll", top);
- D16(PLL_CTL);
- D16(PLL_DIV);
- D16(PLL_LOCKCNT);
- D16(PLL_STAT);
- D16(VR_CTL);
- D32(CHIPID); /* it's part of this hardware block */
-
-#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
- parent = debugfs_create_dir("ppi", top);
-# ifdef PPI_CONTROL
- bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
-# endif
-# ifdef PPI0_CONTROL
- PPI(0);
-# endif
-# ifdef PPI1_CONTROL
- PPI(1);
-# endif
-#endif
-
-#ifdef PWM_CTRL
- parent = debugfs_create_dir("pwm", top);
- D16(PWM_CTRL);
- D16(PWM_STAT);
- D16(PWM_TM);
- D16(PWM_DT);
- D16(PWM_GATE);
- D16(PWM_CHA);
- D16(PWM_CHB);
- D16(PWM_CHC);
- D16(PWM_SEG);
- D16(PWM_SYNCWT);
- D16(PWM_CHAL);
- D16(PWM_CHBL);
- D16(PWM_CHCL);
- D16(PWM_LSI);
- D16(PWM_STAT2);
-#endif
-
-#ifdef RSI_CONFIG
- parent = debugfs_create_dir("rsi", top);
- D32(RSI_ARGUMENT);
- D16(RSI_CEATA_CONTROL);
- D16(RSI_CLK_CONTROL);
- D16(RSI_COMMAND);
- D16(RSI_CONFIG);
- D16(RSI_DATA_CNT);
- D16(RSI_DATA_CONTROL);
- D16(RSI_DATA_LGTH);
- D32(RSI_DATA_TIMER);
- D16(RSI_EMASK);
- D16(RSI_ESTAT);
- D32(RSI_FIFO);
- D16(RSI_FIFO_CNT);
- D32(RSI_MASK0);
- D32(RSI_MASK1);
- D16(RSI_PID0);
- D16(RSI_PID1);
- D16(RSI_PID2);
- D16(RSI_PID3);
- D16(RSI_PID4);
- D16(RSI_PID5);
- D16(RSI_PID6);
- D16(RSI_PID7);
- D16(RSI_PWR_CONTROL);
- D16(RSI_RD_WAIT_EN);
- D32(RSI_RESPONSE0);
- D32(RSI_RESPONSE1);
- D32(RSI_RESPONSE2);
- D32(RSI_RESPONSE3);
- D16(RSI_RESP_CMD);
- D32(RSI_STATUS);
- D_WO(RSI_STATUSCL, 16);
-#endif
-
-#ifdef RTC_ALARM
- parent = debugfs_create_dir("rtc", top);
- D32(RTC_ALARM);
- D16(RTC_ICTL);
- D16(RTC_ISTAT);
- D16(RTC_PREN);
- D32(RTC_STAT);
- D16(RTC_SWCNT);
-#endif
-
-#ifdef SDH_CFG
- parent = debugfs_create_dir("sdh", top);
- D32(SDH_ARGUMENT);
- D16(SDH_CFG);
- D16(SDH_CLK_CTL);
- D16(SDH_COMMAND);
- D_RO(SDH_DATA_CNT, 16);
- D16(SDH_DATA_CTL);
- D16(SDH_DATA_LGTH);
- D32(SDH_DATA_TIMER);
- D16(SDH_E_MASK);
- D16(SDH_E_STATUS);
- D32(SDH_FIFO);
- D_RO(SDH_FIFO_CNT, 16);
- D32(SDH_MASK0);
- D32(SDH_MASK1);
- D_RO(SDH_PID0, 16);
- D_RO(SDH_PID1, 16);
- D_RO(SDH_PID2, 16);
- D_RO(SDH_PID3, 16);
- D_RO(SDH_PID4, 16);
- D_RO(SDH_PID5, 16);
- D_RO(SDH_PID6, 16);
- D_RO(SDH_PID7, 16);
- D16(SDH_PWR_CTL);
- D16(SDH_RD_WAIT_EN);
- D_RO(SDH_RESPONSE0, 32);
- D_RO(SDH_RESPONSE1, 32);
- D_RO(SDH_RESPONSE2, 32);
- D_RO(SDH_RESPONSE3, 32);
- D_RO(SDH_RESP_CMD, 16);
- D_RO(SDH_STATUS, 32);
- D_WO(SDH_STATUS_CLR, 16);
-#endif
-
-#ifdef SECURE_CONTROL
- parent = debugfs_create_dir("security", top);
- D16(SECURE_CONTROL);
- D16(SECURE_STATUS);
- D32(SECURE_SYSSWT);
-#endif
-
- parent = debugfs_create_dir("sic", top);
- D16(SWRST);
- D16(SYSCR);
- D16(SIC_RVECT);
- D32(SIC_IAR0);
- D32(SIC_IAR1);
- D32(SIC_IAR2);
-#ifdef SIC_IAR3
- D32(SIC_IAR3);
-#endif
-#ifdef SIC_IAR4
- D32(SIC_IAR4);
- D32(SIC_IAR5);
- D32(SIC_IAR6);
-#endif
-#ifdef SIC_IAR7
- D32(SIC_IAR7);
-#endif
-#ifdef SIC_IAR8
- D32(SIC_IAR8);
- D32(SIC_IAR9);
- D32(SIC_IAR10);
- D32(SIC_IAR11);
-#endif
-#ifdef SIC_IMASK
- D32(SIC_IMASK);
- D32(SIC_ISR);
- D32(SIC_IWR);
-#endif
-#ifdef SIC_IMASK0
- D32(SIC_IMASK0);
- D32(SIC_IMASK1);
- D32(SIC_ISR0);
- D32(SIC_ISR1);
- D32(SIC_IWR0);
- D32(SIC_IWR1);
-#endif
-#ifdef SIC_IMASK2
- D32(SIC_IMASK2);
- D32(SIC_ISR2);
- D32(SIC_IWR2);
-#endif
-#ifdef SICB_RVECT
- D16(SICB_SWRST);
- D16(SICB_SYSCR);
- D16(SICB_RVECT);
- D32(SICB_IAR0);
- D32(SICB_IAR1);
- D32(SICB_IAR2);
- D32(SICB_IAR3);
- D32(SICB_IAR4);
- D32(SICB_IAR5);
- D32(SICB_IAR6);
- D32(SICB_IAR7);
- D32(SICB_IMASK0);
- D32(SICB_IMASK1);
- D32(SICB_ISR0);
- D32(SICB_ISR1);
- D32(SICB_IWR0);
- D32(SICB_IWR1);
-#endif
-
- parent = debugfs_create_dir("spi", top);
-#ifdef SPI0_REGBASE
- SPI(0);
-#endif
-#ifdef SPI1_REGBASE
- SPI(1);
-#endif
-#ifdef SPI2_REGBASE
- SPI(2);
-#endif
-
- parent = debugfs_create_dir("sport", top);
-#ifdef SPORT0_STAT
- SPORT(0);
-#endif
-#ifdef SPORT1_STAT
- SPORT(1);
-#endif
-#ifdef SPORT2_STAT
- SPORT(2);
-#endif
-#ifdef SPORT3_STAT
- SPORT(3);
-#endif
-
-#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
- parent = debugfs_create_dir("twi", top);
-# ifdef TWI_CLKDIV
- bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
-# endif
-# ifdef TWI0_CLKDIV
- TWI(0);
-# endif
-# ifdef TWI1_CLKDIV
- TWI(1);
-# endif
-#endif
-
- parent = debugfs_create_dir("uart", top);
-#ifdef BFIN_UART_DLL
- bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
-#endif
-#ifdef UART0_DLL
- UART(0);
-#endif
-#ifdef UART1_DLL
- UART(1);
-#endif
-#ifdef UART2_DLL
- UART(2);
-#endif
-#ifdef UART3_DLL
- UART(3);
-#endif
-
-#ifdef USB_FADDR
- parent = debugfs_create_dir("usb", top);
- D16(USB_FADDR);
- D16(USB_POWER);
- D16(USB_INTRTX);
- D16(USB_INTRRX);
- D16(USB_INTRTXE);
- D16(USB_INTRRXE);
- D16(USB_INTRUSB);
- D16(USB_INTRUSBE);
- D16(USB_FRAME);
- D16(USB_INDEX);
- D16(USB_TESTMODE);
- D16(USB_GLOBINTR);
- D16(USB_GLOBAL_CTL);
- D16(USB_TX_MAX_PACKET);
- D16(USB_CSR0);
- D16(USB_TXCSR);
- D16(USB_RX_MAX_PACKET);
- D16(USB_RXCSR);
- D16(USB_COUNT0);
- D16(USB_RXCOUNT);
- D16(USB_TXTYPE);
- D16(USB_NAKLIMIT0);
- D16(USB_TXINTERVAL);
- D16(USB_RXTYPE);
- D16(USB_RXINTERVAL);
- D16(USB_TXCOUNT);
- D16(USB_EP0_FIFO);
- D16(USB_EP1_FIFO);
- D16(USB_EP2_FIFO);
- D16(USB_EP3_FIFO);
- D16(USB_EP4_FIFO);
- D16(USB_EP5_FIFO);
- D16(USB_EP6_FIFO);
- D16(USB_EP7_FIFO);
- D16(USB_OTG_DEV_CTL);
- D16(USB_OTG_VBUS_IRQ);
- D16(USB_OTG_VBUS_MASK);
- D16(USB_LINKINFO);
- D16(USB_VPLEN);
- D16(USB_HS_EOF1);
- D16(USB_FS_EOF1);
- D16(USB_LS_EOF1);
- D16(USB_APHY_CNTRL);
- D16(USB_APHY_CALIB);
- D16(USB_APHY_CNTRL2);
- D16(USB_PLLOSC_CTRL);
- D16(USB_SRP_CLKDIV);
- D16(USB_EP_NI0_TXMAXP);
- D16(USB_EP_NI0_TXCSR);
- D16(USB_EP_NI0_RXMAXP);
- D16(USB_EP_NI0_RXCSR);
- D16(USB_EP_NI0_RXCOUNT);
- D16(USB_EP_NI0_TXTYPE);
- D16(USB_EP_NI0_TXINTERVAL);
- D16(USB_EP_NI0_RXTYPE);
- D16(USB_EP_NI0_RXINTERVAL);
- D16(USB_EP_NI0_TXCOUNT);
- D16(USB_EP_NI1_TXMAXP);
- D16(USB_EP_NI1_TXCSR);
- D16(USB_EP_NI1_RXMAXP);
- D16(USB_EP_NI1_RXCSR);
- D16(USB_EP_NI1_RXCOUNT);
- D16(USB_EP_NI1_TXTYPE);
- D16(USB_EP_NI1_TXINTERVAL);
- D16(USB_EP_NI1_RXTYPE);
- D16(USB_EP_NI1_RXINTERVAL);
- D16(USB_EP_NI1_TXCOUNT);
- D16(USB_EP_NI2_TXMAXP);
- D16(USB_EP_NI2_TXCSR);
- D16(USB_EP_NI2_RXMAXP);
- D16(USB_EP_NI2_RXCSR);
- D16(USB_EP_NI2_RXCOUNT);
- D16(USB_EP_NI2_TXTYPE);
- D16(USB_EP_NI2_TXINTERVAL);
- D16(USB_EP_NI2_RXTYPE);
- D16(USB_EP_NI2_RXINTERVAL);
- D16(USB_EP_NI2_TXCOUNT);
- D16(USB_EP_NI3_TXMAXP);
- D16(USB_EP_NI3_TXCSR);
- D16(USB_EP_NI3_RXMAXP);
- D16(USB_EP_NI3_RXCSR);
- D16(USB_EP_NI3_RXCOUNT);
- D16(USB_EP_NI3_TXTYPE);
- D16(USB_EP_NI3_TXINTERVAL);
- D16(USB_EP_NI3_RXTYPE);
- D16(USB_EP_NI3_RXINTERVAL);
- D16(USB_EP_NI3_TXCOUNT);
- D16(USB_EP_NI4_TXMAXP);
- D16(USB_EP_NI4_TXCSR);
- D16(USB_EP_NI4_RXMAXP);
- D16(USB_EP_NI4_RXCSR);
- D16(USB_EP_NI4_RXCOUNT);
- D16(USB_EP_NI4_TXTYPE);
- D16(USB_EP_NI4_TXINTERVAL);
- D16(USB_EP_NI4_RXTYPE);
- D16(USB_EP_NI4_RXINTERVAL);
- D16(USB_EP_NI4_TXCOUNT);
- D16(USB_EP_NI5_TXMAXP);
- D16(USB_EP_NI5_TXCSR);
- D16(USB_EP_NI5_RXMAXP);
- D16(USB_EP_NI5_RXCSR);
- D16(USB_EP_NI5_RXCOUNT);
- D16(USB_EP_NI5_TXTYPE);
- D16(USB_EP_NI5_TXINTERVAL);
- D16(USB_EP_NI5_RXTYPE);
- D16(USB_EP_NI5_RXINTERVAL);
- D16(USB_EP_NI5_TXCOUNT);
- D16(USB_EP_NI6_TXMAXP);
- D16(USB_EP_NI6_TXCSR);
- D16(USB_EP_NI6_RXMAXP);
- D16(USB_EP_NI6_RXCSR);
- D16(USB_EP_NI6_RXCOUNT);
- D16(USB_EP_NI6_TXTYPE);
- D16(USB_EP_NI6_TXINTERVAL);
- D16(USB_EP_NI6_RXTYPE);
- D16(USB_EP_NI6_RXINTERVAL);
- D16(USB_EP_NI6_TXCOUNT);
- D16(USB_EP_NI7_TXMAXP);
- D16(USB_EP_NI7_TXCSR);
- D16(USB_EP_NI7_RXMAXP);
- D16(USB_EP_NI7_RXCSR);
- D16(USB_EP_NI7_RXCOUNT);
- D16(USB_EP_NI7_TXTYPE);
- D16(USB_EP_NI7_TXINTERVAL);
- D16(USB_EP_NI7_RXTYPE);
- D16(USB_EP_NI7_RXINTERVAL);
- D16(USB_EP_NI7_TXCOUNT);
- D16(USB_DMA_INTERRUPT);
- D16(USB_DMA0CONTROL);
- D16(USB_DMA0ADDRLOW);
- D16(USB_DMA0ADDRHIGH);
- D16(USB_DMA0COUNTLOW);
- D16(USB_DMA0COUNTHIGH);
- D16(USB_DMA1CONTROL);
- D16(USB_DMA1ADDRLOW);
- D16(USB_DMA1ADDRHIGH);
- D16(USB_DMA1COUNTLOW);
- D16(USB_DMA1COUNTHIGH);
- D16(USB_DMA2CONTROL);
- D16(USB_DMA2ADDRLOW);
- D16(USB_DMA2ADDRHIGH);
- D16(USB_DMA2COUNTLOW);
- D16(USB_DMA2COUNTHIGH);
- D16(USB_DMA3CONTROL);
- D16(USB_DMA3ADDRLOW);
- D16(USB_DMA3ADDRHIGH);
- D16(USB_DMA3COUNTLOW);
- D16(USB_DMA3COUNTHIGH);
- D16(USB_DMA4CONTROL);
- D16(USB_DMA4ADDRLOW);
- D16(USB_DMA4ADDRHIGH);
- D16(USB_DMA4COUNTLOW);
- D16(USB_DMA4COUNTHIGH);
- D16(USB_DMA5CONTROL);
- D16(USB_DMA5ADDRLOW);
- D16(USB_DMA5ADDRHIGH);
- D16(USB_DMA5COUNTLOW);
- D16(USB_DMA5COUNTHIGH);
- D16(USB_DMA6CONTROL);
- D16(USB_DMA6ADDRLOW);
- D16(USB_DMA6ADDRHIGH);
- D16(USB_DMA6COUNTLOW);
- D16(USB_DMA6COUNTHIGH);
- D16(USB_DMA7CONTROL);
- D16(USB_DMA7ADDRLOW);
- D16(USB_DMA7ADDRHIGH);
- D16(USB_DMA7COUNTLOW);
- D16(USB_DMA7COUNTHIGH);
-#endif
-
-#ifdef WDOG_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOG_CNT);
- D16(WDOG_CTL);
- D32(WDOG_STAT);
-#endif
-#ifdef WDOGA_CNT
- parent = debugfs_create_dir("watchdog", top);
- D32(WDOGA_CNT);
- D16(WDOGA_CTL);
- D32(WDOGA_STAT);
- D32(WDOGB_CNT);
- D16(WDOGB_CTL);
- D32(WDOGB_STAT);
-#endif
-
- /* BF533 glue */
-#ifdef FIO_FLAG_D
-#define PORTFIO FIO_FLAG_D
-#endif
- /* BF561 glue */
-#ifdef FIO0_FLAG_D
-#define PORTFIO FIO0_FLAG_D
-#endif
-#ifdef FIO1_FLAG_D
-#define PORTGIO FIO1_FLAG_D
-#endif
-#ifdef FIO2_FLAG_D
-#define PORTHIO FIO2_FLAG_D
-#endif
- parent = debugfs_create_dir("port", top);
-#ifdef PORTFIO
- PORT(PORTFIO, 'F');
-#endif
-#ifdef PORTGIO
- PORT(PORTGIO, 'G');
-#endif
-#ifdef PORTHIO
- PORT(PORTHIO, 'H');
-#endif
-
-#ifdef __ADSPBF51x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
-#endif /* BF51x */
-
-#ifdef __ADSPBF52x__
- D16(PORTF_FER);
- D16(PORTF_DRIVE);
- D16(PORTF_HYSTERESIS);
- D16(PORTF_MUX);
- D16(PORTF_SLEW);
-
- D16(PORTG_FER);
- D16(PORTG_DRIVE);
- D16(PORTG_HYSTERESIS);
- D16(PORTG_MUX);
- D16(PORTG_SLEW);
-
- D16(PORTH_FER);
- D16(PORTH_DRIVE);
- D16(PORTH_HYSTERESIS);
- D16(PORTH_MUX);
- D16(PORTH_SLEW);
-
- D16(MISCPORT_DRIVE);
- D16(MISCPORT_HYSTERESIS);
- D16(MISCPORT_SLEW);
-#endif /* BF52x */
-
-#ifdef BF537_FAMILY
- D16(PORTF_FER);
- D16(PORTG_FER);
- D16(PORTH_FER);
- D16(PORT_MUX);
-#endif /* BF534 BF536 BF537 */
-
-#ifdef BF538_FAMILY
- D16(PORTCIO_FER);
- D16(PORTCIO);
- D16(PORTCIO_CLEAR);
- D16(PORTCIO_SET);
- D16(PORTCIO_TOGGLE);
- D16(PORTCIO_DIR);
- D16(PORTCIO_INEN);
-
- D16(PORTDIO);
- D16(PORTDIO_CLEAR);
- D16(PORTDIO_DIR);
- D16(PORTDIO_FER);
- D16(PORTDIO_INEN);
- D16(PORTDIO_SET);
- D16(PORTDIO_TOGGLE);
-
- D16(PORTEIO);
- D16(PORTEIO_CLEAR);
- D16(PORTEIO_DIR);
- D16(PORTEIO_FER);
- D16(PORTEIO_INEN);
- D16(PORTEIO_SET);
- D16(PORTEIO_TOGGLE);
-#endif /* BF538 BF539 */
-
-#ifdef __ADSPBF54x__
- {
- int num;
- unsigned long base;
-
- base = PORTA_FER;
- for (num = 0; num < 10; ++num) {
- PORT(base, num);
- base += sizeof(struct bfin_gpio_regs);
- }
-
- }
-#endif /* BF54x */
-#endif /* CONFIG_BF60x */
- debug_mmrs_dentry = top;
-
- return 0;
-}
-module_init(bfin_debug_mmrs_init);
-
-static void __exit bfin_debug_mmrs_exit(void)
-{
- debugfs_remove_recursive(debug_mmrs_dentry);
-}
-module_exit(bfin_debug_mmrs_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
deleted file mode 100644
index 477bb29a7987..000000000000
--- a/arch/blackfin/kernel/dma-mapping.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Dynamic DMA mapping support
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/gfp.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <linux/scatterlist.h>
-#include <linux/export.h>
-#include <linux/bitmap.h>
-
-static spinlock_t dma_page_lock;
-static unsigned long *dma_page;
-static unsigned int dma_pages;
-static unsigned long dma_base;
-static unsigned long dma_size;
-static unsigned int dma_initialized;
-
-static void dma_alloc_init(unsigned long start, unsigned long end)
-{
- spin_lock_init(&dma_page_lock);
- dma_initialized = 0;
-
- dma_page = (unsigned long *)__get_free_page(GFP_KERNEL);
- memset(dma_page, 0, PAGE_SIZE);
- dma_base = PAGE_ALIGN(start);
- dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start);
- dma_pages = dma_size >> PAGE_SHIFT;
- memset((void *)dma_base, 0, DMA_UNCACHED_REGION);
- dma_initialized = 1;
-
- printk(KERN_INFO "%s: dma_page @ 0x%p - %d pages at 0x%08lx\n", __func__,
- dma_page, dma_pages, dma_base);
-}
-
-static inline unsigned int get_pages(size_t size)
-{
- return ((size - 1) >> PAGE_SHIFT) + 1;
-}
-
-static unsigned long __alloc_dma_pages(unsigned int pages)
-{
- unsigned long ret = 0, flags;
- unsigned long start;
-
- if (dma_initialized == 0)
- dma_alloc_init(_ramend - DMA_UNCACHED_REGION, _ramend);
-
- spin_lock_irqsave(&dma_page_lock, flags);
-
- start = bitmap_find_next_zero_area(dma_page, dma_pages, 0, pages, 0);
- if (start < dma_pages) {
- ret = dma_base + (start << PAGE_SHIFT);
- bitmap_set(dma_page, start, pages);
- }
- spin_unlock_irqrestore(&dma_page_lock, flags);
- return ret;
-}
-
-static void __free_dma_pages(unsigned long addr, unsigned int pages)
-{
- unsigned long page = (addr - dma_base) >> PAGE_SHIFT;
- unsigned long flags;
-
- if ((page + pages) > dma_pages) {
- printk(KERN_ERR "%s: freeing outside range.\n", __func__);
- BUG();
- }
-
- spin_lock_irqsave(&dma_page_lock, flags);
- bitmap_clear(dma_page, page, pages);
- spin_unlock_irqrestore(&dma_page_lock, flags);
-}
-
-static void *bfin_dma_alloc(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- void *ret;
-
- ret = (void *)__alloc_dma_pages(get_pages(size));
-
- if (ret) {
- memset(ret, 0, size);
- *dma_handle = virt_to_phys(ret);
- }
-
- return ret;
-}
-
-static void bfin_dma_free(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- __free_dma_pages((unsigned long)vaddr, get_pages(size));
-}
-
-/*
- * Streaming DMA mappings
- */
-void __dma_sync(dma_addr_t addr, size_t size,
- enum dma_data_direction dir)
-{
- __dma_sync_inline(addr, size, dir);
-}
-EXPORT_SYMBOL(__dma_sync);
-
-static int bfin_dma_map_sg(struct device *dev, struct scatterlist *sg_list,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nents, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
-
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-
- return nents;
-}
-
-static void bfin_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg_list, int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sg_list, sg, nelems, i) {
- sg->dma_address = (dma_addr_t) sg_virt(sg);
- __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
- }
-}
-
-static dma_addr_t bfin_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size, enum dma_data_direction dir,
- unsigned long attrs)
-{
- dma_addr_t handle = (dma_addr_t)(page_address(page) + offset);
-
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- _dma_sync(handle, size, dir);
-
- return handle;
-}
-
-static inline void bfin_dma_sync_single_for_device(struct device *dev,
- dma_addr_t handle, size_t size, enum dma_data_direction dir)
-{
- _dma_sync(handle, size, dir);
-}
-
-const struct dma_map_ops bfin_dma_ops = {
- .alloc = bfin_dma_alloc,
- .free = bfin_dma_free,
-
- .map_page = bfin_dma_map_page,
- .map_sg = bfin_dma_map_sg,
-
- .sync_single_for_device = bfin_dma_sync_single_for_device,
- .sync_sg_for_device = bfin_dma_sync_sg_for_device,
-};
-EXPORT_SYMBOL(bfin_dma_ops);
diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c
deleted file mode 100644
index 3c992c1f8ef2..000000000000
--- a/arch/blackfin/kernel/dumpstack.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Provide basic stack dumping functions
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/debug.h>
-
-#include <asm/trace.h>
-
-/*
- * Checks to see if the address pointed to is either a
- * 16-bit CALL instruction, or a 32-bit CALL instruction
- */
-static bool is_bfin_call(unsigned short *addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, addr))
- return false;
-
- if ((opcode >= 0x0060 && opcode <= 0x0067) ||
- (opcode >= 0x0070 && opcode <= 0x0077) ||
- (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
- return true;
-
- return false;
-
-}
-
-void show_stack(struct task_struct *task, unsigned long *stack)
-{
-#ifdef CONFIG_PRINTK
- unsigned int *addr, *endstack, *fp = 0, *frame;
- unsigned short *ins_addr;
- char buf[150];
- unsigned int i, j, ret_addr, frame_no = 0;
-
- /*
- * If we have been passed a specific stack, use that one otherwise
- * if we have been passed a task structure, use that, otherwise
- * use the stack of where the variable "stack" exists
- */
-
- if (stack == NULL) {
- if (task) {
- /* We know this is a kernel stack, so this is the start/end */
- stack = (unsigned long *)task->thread.ksp;
- endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
- } else {
- /* print out the existing stack info */
- stack = (unsigned long *)&stack;
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
- }
- } else
- endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
-
- printk(KERN_NOTICE "Stack info:\n");
- decode_address(buf, (unsigned int)stack);
- printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
-
- if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
- printk(KERN_NOTICE "Invalid stack pointer\n");
- return;
- }
-
- /* First thing is to look for a frame pointer */
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
- if (*addr & 0x1)
- continue;
- ins_addr = (unsigned short *)*addr;
- ins_addr--;
- if (is_bfin_call(ins_addr))
- fp = addr - 1;
-
- if (fp) {
- /* Let's check to see if it is a frame pointer */
- while (fp >= (addr - 1) && fp < endstack
- && fp && ((unsigned int) fp & 0x3) == 0)
- fp = (unsigned int *)*fp;
- if (fp == 0 || fp == endstack) {
- fp = addr - 1;
- break;
- }
- fp = 0;
- }
- }
- if (fp) {
- frame = fp;
- printk(KERN_NOTICE " FP: (0x%p)\n", fp);
- } else
- frame = 0;
-
- /*
- * Now that we think we know where things are, we
- * walk the stack again, this time printing things out
- * incase there is no frame pointer, we still look for
- * valid return addresses
- */
-
- /* First time print out data, next time, print out symbols */
- for (j = 0; j <= 1; j++) {
- if (j)
- printk(KERN_NOTICE "Return addresses in stack:\n");
- else
- printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
-
- fp = frame;
- frame_no = 0;
-
- for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
- addr < endstack; addr++, i++) {
-
- ret_addr = 0;
- if (!j && i % 8 == 0)
- printk(KERN_NOTICE "%p:", addr);
-
- /* if it is an odd address, or zero, just skip it */
- if (*addr & 0x1 || !*addr)
- goto print;
-
- ins_addr = (unsigned short *)*addr;
-
- /* Go back one instruction, and see if it is a CALL */
- ins_addr--;
- ret_addr = is_bfin_call(ins_addr);
- print:
- if (!j && stack == (unsigned long *)addr)
- printk("[%08x]", *addr);
- else if (ret_addr)
- if (j) {
- decode_address(buf, (unsigned int)*addr);
- if (frame == addr) {
- printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
- continue;
- }
- printk(KERN_NOTICE " address : %s\n", buf);
- } else
- printk("<%08x>", *addr);
- else if (fp == addr) {
- if (j)
- frame = addr+1;
- else
- printk("(%08x)", *addr);
-
- fp = (unsigned int *)*addr;
- frame_no++;
-
- } else if (!j)
- printk(" %08x ", *addr);
- }
- if (!j)
- printk("\n");
- }
-#endif
-}
-EXPORT_SYMBOL(show_stack);
-
-void dump_stack(void)
-{
- unsigned long stack;
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags;
-#endif
- trace_buffer_save(tflags);
- dump_bfin_trace_buffer();
- dump_stack_print_info(KERN_DEFAULT);
- show_stack(current, &stack);
- trace_buffer_restore(tflags);
-}
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
deleted file mode 100644
index 4b89af9243d3..000000000000
--- a/arch/blackfin/kernel/early_printk.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * allow a console to be used for early printk
- * derived from arch/x86/kernel/early_printk.c
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched/debug.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <linux/reboot.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#ifdef CONFIG_SERIAL_BFIN
-extern struct console *bfin_earlyserial_init(unsigned int port,
- unsigned int cflag);
-#endif
-#ifdef CONFIG_BFIN_JTAG_COMM
-extern struct console *bfin_jc_early_init(void);
-#endif
-
-/* Default console */
-#define DEFAULT_PORT 0
-#define DEFAULT_CFLAG CS8|B57600
-
-/* Default console for early crashes */
-#define DEFAULT_EARLY_PORT "serial,uart0,57600"
-
-#ifdef CONFIG_SERIAL_CORE
-/* What should get here is "0,57600" */
-static struct console * __init earlyserial_init(char *buf)
-{
- int baud, bit;
- char parity;
- unsigned int serial_port = DEFAULT_PORT;
- unsigned int cflag = DEFAULT_CFLAG;
-
- serial_port = simple_strtoul(buf, &buf, 10);
- buf++;
-
- cflag = 0;
- baud = simple_strtoul(buf, &buf, 10);
- switch (baud) {
- case 1200:
- cflag |= B1200;
- break;
- case 2400:
- cflag |= B2400;
- break;
- case 4800:
- cflag |= B4800;
- break;
- case 9600:
- cflag |= B9600;
- break;
- case 19200:
- cflag |= B19200;
- break;
- case 38400:
- cflag |= B38400;
- break;
- case 115200:
- cflag |= B115200;
- break;
- default:
- cflag |= B57600;
- }
-
- parity = buf[0];
- buf++;
- switch (parity) {
- case 'e':
- cflag |= PARENB;
- break;
- case 'o':
- cflag |= PARODD;
- break;
- }
-
- bit = simple_strtoul(buf, &buf, 10);
- switch (bit) {
- case 5:
- cflag |= CS5;
- break;
- case 6:
- cflag |= CS6;
- break;
- case 7:
- cflag |= CS7;
- break;
- default:
- cflag |= CS8;
- }
-
-#ifdef CONFIG_SERIAL_BFIN
- return bfin_earlyserial_init(serial_port, cflag);
-#else
- return NULL;
-#endif
-
-}
-#endif
-
-int __init setup_early_printk(char *buf)
-{
-
- /* Crashing in here would be really bad, so check both the var
- and the pointer before we start using it
- */
- if (!buf)
- return 0;
-
- if (!*buf)
- return 0;
-
- if (early_console != NULL)
- return 0;
-
-#ifdef CONFIG_SERIAL_BFIN
- /* Check for Blackfin Serial */
- if (!strncmp(buf, "serial,uart", 11)) {
- buf += 11;
- early_console = earlyserial_init(buf);
- }
-#endif
-
-#ifdef CONFIG_BFIN_JTAG_COMM
- /* Check for Blackfin JTAG */
- if (!strncmp(buf, "jtag", 4)) {
- buf += 4;
- early_console = bfin_jc_early_init();
- }
-#endif
-
-#ifdef CONFIG_FB
- /* TODO: add framebuffer console support */
-#endif
-
- if (likely(early_console)) {
- early_console->flags |= CON_BOOT;
-
- register_console(early_console);
- printk(KERN_INFO "early printk enabled on %s%d\n",
- early_console->name,
- early_console->index);
- }
-
- return 0;
-}
-
-/*
- * Set up a temporary Event Vector Table, so if something bad happens before
- * the kernel is fully started, it doesn't vector off into somewhere we don't
- * know
- */
-
-asmlinkage void __init init_early_exception_vectors(void)
-{
- u32 evt;
- SSYNC();
-
- /*
- * This starts up the shadow buffer, incase anything crashes before
- * setup arch
- */
- mark_shadow_error();
- early_shadow_puts(linux_banner);
- early_shadow_stamp();
-
- if (CPUID != bfin_cpuid()) {
- early_shadow_puts("Running on wrong machine type, expected");
- early_shadow_reg(CPUID, 16);
- early_shadow_puts(", but running on");
- early_shadow_reg(bfin_cpuid(), 16);
- early_shadow_puts("\n");
- }
-
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- for (evt = EVT2; evt <= EVT15; evt += 4)
- bfin_write32(evt, early_trap);
- CSYNC();
-
- /* Set all the return from interrupt, exception, NMI to a known place
- * so if we do a RETI, RETX or RETN by mistake - we go somewhere known
- * Note - don't change RETS - we are in a subroutine, or
- * RETE - since it might screw up if emulator is attached
- */
- asm("\tRETI = %0; RETX = %0; RETN = %0;\n"
- : : "p"(early_trap));
-
-}
-
-__attribute__((__noreturn__))
-asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr)
-{
- /* This can happen before the uart is initialized, so initialize
- * the UART now (but only if we are running on the processor we think
- * we are compiled for - otherwise we write to MMRs that don't exist,
- * and cause other problems. Nothing comes out the UART, but it does
- * end up in the __buf_log.
- */
- if (likely(early_console == NULL) && CPUID == bfin_cpuid())
- setup_early_printk(DEFAULT_EARLY_PORT);
-
- if (!shadow_console_enabled()) {
- /* crap - we crashed before setup_arch() */
- early_shadow_puts("panic before setup_arch\n");
- early_shadow_puts("IPEND:");
- early_shadow_reg(fp->ipend, 16);
- if (fp->seqstat & SEQSTAT_EXCAUSE) {
- early_shadow_puts("\nEXCAUSE:");
- early_shadow_reg(fp->seqstat & SEQSTAT_EXCAUSE, 8);
- }
- if (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- early_shadow_puts("\nHWERRCAUSE:");
- early_shadow_reg(
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14, 8);
- }
- early_shadow_puts("\nErr @");
- if (fp->ipend & EVT_EVX)
- early_shadow_reg(fp->retx, 32);
- else
- early_shadow_reg(fp->pc, 32);
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- early_shadow_puts("\nTrace:");
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- while (bfin_read_TBUFSTAT() & TBUFCNT) {
- early_shadow_puts("\nT :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- early_shadow_puts("\n S :");
- early_shadow_reg(bfin_read_TBUF(), 32);
- }
- }
-#endif
- early_shadow_puts("\nUse bfin-elf-addr2line to determine "
- "function names\n");
- /*
- * We should panic(), but we can't - since panic calls printk,
- * and printk uses memcpy.
- * we want to reboot, but if the machine type is different,
- * can't due to machine specific reboot sequences
- */
- if (CPUID == bfin_cpuid()) {
- early_shadow_puts("Trying to restart\n");
- machine_restart("");
- }
-
- early_shadow_puts("Halting, since it is not safe to restart\n");
- while (1)
- asm volatile ("EMUEXCPT; IDLE;\n");
-
- } else {
- printk(KERN_EMERG "Early panic\n");
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-
- panic("Died early");
-}
-
-early_param("earlyprintk", setup_early_printk);
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
deleted file mode 100644
index 4071265fc4fe..000000000000
--- a/arch/blackfin/kernel/entry.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/errno.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-
-#include <asm/context.S>
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-ENTRY(_ret_from_fork)
-#ifdef CONFIG_IPIPE
- /*
- * Hw IRQs are off on entry, and we don't want the scheduling tail
- * code to starve high priority domains from interrupts while it
- * runs. Therefore we first stall the root stage to have the
- * virtual interrupt state reflect IMASK.
- */
- p0.l = ___ipipe_root_status;
- p0.h = ___ipipe_root_status;
- r4 = [p0];
- bitset(r4, 0);
- [p0] = r4;
- /*
- * Then we may enable hw IRQs, allowing preemption from high
- * priority domains. schedule_tail() will do local_irq_enable()
- * since Blackfin does not define __ARCH_WANT_UNLOCKED_CTXSW, so
- * there is no need to unstall the root domain by ourselves
- * afterwards.
- */
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r4 = [p0];
- sti r4;
-#endif /* CONFIG_IPIPE */
- SP += -12;
- pseudo_long_call _schedule_tail, p5;
- SP += 12;
- p1 = [sp++];
- r0 = [sp++];
- cc = p1 == 0;
- if cc jump .Lfork;
- sp += -12;
- call (p1);
- sp += 12;
-.Lfork:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_ret_from_fork)
diff --git a/arch/blackfin/kernel/exception.c b/arch/blackfin/kernel/exception.c
deleted file mode 100644
index 9208b5fd5186..000000000000
--- a/arch/blackfin/kernel/exception.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Basic functions for adding/removing custom exception handlers
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <asm/irq_handler.h>
-
-int bfin_request_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != ex_replaceable)
- return -EBUSY;
-
- ex_table[exception] = handler;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_request_exception);
-
-int bfin_free_exception(unsigned int exception, void (*handler)(void))
-{
- void (*curr_handler)(void);
-
- if (exception > 0x3F)
- return -EINVAL;
-
- curr_handler = ex_table[exception];
-
- if (curr_handler != handler)
- return -EBUSY;
-
- ex_table[exception] = ex_replaceable;
-
- return 0;
-}
-EXPORT_SYMBOL(bfin_free_exception);
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S
deleted file mode 100644
index 0565917f23ba..000000000000
--- a/arch/blackfin/kernel/fixed_code.S
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file contains sequences of code that will be copied to a
- * fixed location, defined in <asm/fixed_code.h>. The interrupt
- * handlers ensure that these sequences appear to be atomic when
- * executed from userspace.
- * These are aligned to 16 bytes, so that we have some space to replace
- * these sequences with something else (e.g. kernel traps if we ever do
- * BF561 SMP).
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <linux/unistd.h>
-#include <asm/entry.h>
-
-__INIT
-
-ENTRY(_fixed_code_start)
-
-.align 16
-ENTRY(_sigreturn_stub)
- P0 = __NR_rt_sigreturn;
- EXCPT 0;
- /* Speculative execution paranoia. */
-0: JUMP.S 0b;
-ENDPROC (_sigreturn_stub)
-
-.align 16
- /*
- * Atomic swap, 8 bit.
- * Inputs: P0: memory address to use
- * R1: value to store
- * Output: R0: old contents of the memory address, zero extended.
- */
-ENTRY(_atomic_xchg32)
- R0 = [P0];
- [P0] = R1;
- rts;
-ENDPROC (_atomic_xchg32)
-
-.align 16
- /*
- * Compare and swap, 32 bit.
- * Inputs: P0: memory address to use
- * R1: compare value
- * R2: new value to store
- * The new value is stored if the contents of the memory
- * address is equal to the compare value.
- * Output: R0: old contents of the memory address.
- */
-ENTRY(_atomic_cas32)
- R0 = [P0];
- CC = R0 == R1;
- IF !CC JUMP 1f;
- [P0] = R2;
-1:
- rts;
-ENDPROC (_atomic_cas32)
-
-.align 16
- /*
- * Atomic add, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to add
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_add32)
- R1 = [P0];
- R0 = R1 + R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_add32)
-
-.align 16
- /*
- * Atomic sub, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to subtract
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_sub32)
- R1 = [P0];
- R0 = R1 - R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_sub32)
-
-.align 16
- /*
- * Atomic ior, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to ior
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_ior32)
- R1 = [P0];
- R0 = R1 | R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_ior32)
-
-.align 16
- /*
- * Atomic and, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to and
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_and32)
- R1 = [P0];
- R0 = R1 & R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_and32)
-
-.align 16
- /*
- * Atomic xor, 32 bit.
- * Inputs: P0: memory address to use
- * R0: value to xor
- * Outputs: R0: new contents of the memory address.
- * R1: previous contents of the memory address.
- */
-ENTRY(_atomic_xor32)
- R1 = [P0];
- R0 = R1 ^ R0;
- [P0] = R0;
- rts;
-ENDPROC (_atomic_xor32)
-
-.align 16
- /*
- * safe_user_instruction
- * Four NOPS are enough to allow the pipeline to speculativily load
- * execute anything it wants. After that, things have gone bad, and
- * we are stuck - so panic. Since we might be in user space, we can't
- * call panic, so just cause a unhandled exception, this should cause
- * a dump of the trace buffer so we can tell were we are, and a reboot
- */
-ENTRY(_safe_user_instruction)
- NOP; NOP; NOP; NOP;
- EXCPT 0x4;
-ENDPROC(_safe_user_instruction)
-
-ENTRY(_fixed_code_end)
-
-__FINIT
diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c
deleted file mode 100644
index 8ebc54daaa8e..000000000000
--- a/arch/blackfin/kernel/flat.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-#include <linux/flat.h>
-
-#define FLAT_BFIN_RELOC_TYPE_16_BIT 0
-#define FLAT_BFIN_RELOC_TYPE_16H_BIT 1
-#define FLAT_BFIN_RELOC_TYPE_32_BIT 2
-
-unsigned long bfin_get_addr_from_rp(u32 *ptr,
- u32 relval,
- u32 flags,
- u32 *persistent)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
- u32 val;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- usptr = (unsigned short *)ptr;
- pr_debug("*usptr = %x", get_unaligned(usptr));
- val = get_unaligned(usptr);
- val += *persistent;
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- pr_debug("*ptr = %x", get_unaligned(ptr));
- val = get_unaligned(ptr);
- break;
-
- default:
- pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
- return 0;
- }
-
- /*
- * Stack-relative relocs contain the offset into the stack, we
- * have to add the stack's start address here and return 1 from
- * flat_addr_absolute to prevent the normal address calculations
- */
- if (relval & (1 << 29))
- return val + current->mm->context.end_brk;
-
- if ((flags & FLAT_FLAG_GOTPIC) == 0)
- val = htonl(val);
- return val;
-}
-EXPORT_SYMBOL(bfin_get_addr_from_rp);
-
-/*
- * Insert the address ADDR into the symbol reference at RP;
- * RELVAL is the raw relocation-table entry from which RP is derived
- */
-void bfin_put_addr_at_rp(u32 *ptr, u32 addr, u32 relval)
-{
- unsigned short *usptr = (unsigned short *)ptr;
- int type = (relval >> 26) & 7;
-
- switch (type) {
- case FLAT_BFIN_RELOC_TYPE_16_BIT:
- put_unaligned(addr, usptr);
- pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
- break;
-
- case FLAT_BFIN_RELOC_TYPE_16H_BIT:
- put_unaligned(addr >> 16, usptr);
- pr_debug("new value %x", get_unaligned(usptr));
- break;
-
- case FLAT_BFIN_RELOC_TYPE_32_BIT:
- put_unaligned(addr, ptr);
- pr_debug("new ptr =%x", get_unaligned(ptr));
- break;
- }
-}
-EXPORT_SYMBOL(bfin_put_addr_at_rp);
diff --git a/arch/blackfin/kernel/ftrace-entry.S b/arch/blackfin/kernel/ftrace-entry.S
deleted file mode 100644
index 3b8bdcbb7da3..000000000000
--- a/arch/blackfin/kernel/ftrace-entry.S
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * mcount and friends -- ftrace stuff
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/ftrace.h>
-
-.text
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-/* Simple stub so we can boot the kernel until runtime patching has
- * disabled all calls to this. Then it'll be unused.
- */
-ENTRY(__mcount)
-# if ANOMALY_05000371
- nop; nop; nop; nop;
-# endif
- rts;
-ENDPROC(__mcount)
-
-/* GCC will have called us before setting up the function prologue, so we
- * can clobber the normal scratch registers, but we need to make sure to
- * save/restore the registers used for argument passing (R0-R2) in case
- * the profiled function is using them. With data registers, R3 is the
- * only one we can blow away. With pointer registers, we have P0-P2.
- *
- * Upon entry, the RETS will point to the top of the current profiled
- * function. And since GCC pushed the previous RETS for us, the previous
- * function will be waiting there. mmmm pie.
- */
-ENTRY(_ftrace_caller)
- /* save first/second/third function arg and the return register */
- [--sp] = r2;
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
-.globl _ftrace_call
-_ftrace_call:
- call _ftrace_stub
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
-.globl _ftrace_graph_call
-_ftrace_graph_call:
- nop; /* jump _ftrace_graph_caller; */
-# endif
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(_ftrace_caller)
-
-#else
-
-/* See documentation for _ftrace_caller */
-ENTRY(__mcount)
- /* save third function arg early so we can do testing below */
- [--sp] = r2;
-
- /* load the function pointer to the tracer */
- p0.l = _ftrace_trace_function;
- p0.h = _ftrace_trace_function;
- r3 = [p0];
-
- /* optional micro optimization: don't call the stub tracer */
- r2.l = _ftrace_stub;
- r2.h = _ftrace_stub;
- cc = r2 == r3;
- if ! cc jump .Ldo_trace;
-
-# ifdef CONFIG_FUNCTION_GRAPH_TRACER
- /* if the ftrace_graph_return function pointer is not set to
- * the ftrace_stub entry, call prepare_ftrace_return().
- */
- p0.l = _ftrace_graph_return;
- p0.h = _ftrace_graph_return;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-
- /* similarly, if the ftrace_graph_entry function pointer is not
- * set to the ftrace_graph_entry_stub entry, ...
- */
- p0.l = _ftrace_graph_entry;
- p0.h = _ftrace_graph_entry;
- r2.l = _ftrace_graph_entry_stub;
- r2.h = _ftrace_graph_entry_stub;
- r3 = [p0];
- cc = r2 == r3;
- if ! cc jump _ftrace_graph_caller;
-# endif
-
- r2 = [sp++];
- rts;
-
-.Ldo_trace:
-
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* setup the tracer function */
- p0 = r3;
-
- /* function_trace_call(unsigned long ip, unsigned long parent_ip):
- * ip: this point was called by ...
- * parent_ip: ... this function
- * the ip itself will need adjusting for the mcount call
- */
- r0 = rets;
- r1 = [sp + 16]; /* skip the 4 local regs on stack */
- r0 += -MCOUNT_INSN_SIZE;
-
- /* call the tracer */
- call (p0);
-
- /* restore state and get out of dodge */
-.Lfinish_trace:
- rets = [sp++];
- r1 = [sp++];
- r0 = [sp++];
- r2 = [sp++];
-
-.globl _ftrace_stub
-_ftrace_stub:
- rts;
-ENDPROC(__mcount)
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-/* The prepare_ftrace_return() function is similar to the trace function
- * except it takes a pointer to the location of the frompc. This is so
- * the prepare_ftrace_return() can hijack it temporarily for probing
- * purposes.
- */
-ENTRY(_ftrace_graph_caller)
-# ifndef CONFIG_DYNAMIC_FTRACE
- /* save first/second function arg and the return register */
- [--sp] = r0;
- [--sp] = r1;
- [--sp] = rets;
-
- /* prepare_ftrace_return(parent, self_addr, frame_pointer) */
- r0 = sp; /* unsigned long *parent */
- r1 = rets; /* unsigned long self_addr */
-# else
- r0 = sp; /* unsigned long *parent */
- r1 = [sp]; /* unsigned long self_addr */
-# endif
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r2 = fp; /* unsigned long frame_pointer */
-# endif
- r0 += 16; /* skip the 4 local regs on stack */
- r1 += -MCOUNT_INSN_SIZE;
- call _prepare_ftrace_return;
-
- jump .Lfinish_trace;
-ENDPROC(_ftrace_graph_caller)
-
-/* Undo the rewrite caused by ftrace_graph_caller(). The common function
- * ftrace_return_to_handler() will return the original rets so we can
- * restore it and be on our way.
- */
-ENTRY(_return_to_handler)
- /* make sure original return values are saved */
- [--sp] = p0;
- [--sp] = r0;
- [--sp] = r1;
-
- /* get original return address */
-# ifdef HAVE_FUNCTION_GRAPH_FP_TEST
- r0 = fp; /* Blackfin is sane, so omit this */
-# endif
- call _ftrace_return_to_handler;
- rets = r0;
-
- /* anomaly 05000371 - make sure we have at least three instructions
- * between rets setting and the return
- */
- r1 = [sp++];
- r0 = [sp++];
- p0 = [sp++];
- rts;
-ENDPROC(_return_to_handler)
-#endif
diff --git a/arch/blackfin/kernel/ftrace.c b/arch/blackfin/kernel/ftrace.c
deleted file mode 100644
index 8dad7589b843..000000000000
--- a/arch/blackfin/kernel/ftrace.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * ftrace graph code
- *
- * Copyright (C) 2009-2010 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ftrace.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/uaccess.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-static const unsigned char mnop[] = {
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
- 0x03, 0xc0, 0x00, 0x18, /* MNOP; */
-};
-
-static void bfin_make_pcrel24(unsigned char *insn, unsigned long src,
- unsigned long dst)
-{
- uint32_t pcrel = (dst - src) >> 1;
- insn[0] = pcrel >> 16;
- insn[1] = 0xe3;
- insn[2] = pcrel;
- insn[3] = pcrel >> 8;
-}
-#define bfin_make_pcrel24(insn, src, dst) bfin_make_pcrel24(insn, src, (unsigned long)(dst))
-
-static int ftrace_modify_code(unsigned long ip, const unsigned char *code,
- unsigned long len)
-{
- int ret = probe_kernel_write((void *)ip, (void *)code, len);
- flush_icache_range(ip, ip + len);
- return ret;
-}
-
-int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
- unsigned long addr)
-{
- /* Turn the mcount call site into two MNOPs as those are 32bit insns */
- return ftrace_modify_code(rec->ip, mnop, sizeof(mnop));
-}
-
-int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
-{
- /* Restore the mcount call site */
- unsigned char call[8];
- call[0] = 0x67; /* [--SP] = RETS; */
- call[1] = 0x01;
- bfin_make_pcrel24(&call[2], rec->ip + 2, addr);
- call[6] = 0x27; /* RETS = [SP++]; */
- call[7] = 0x01;
- return ftrace_modify_code(rec->ip, call, sizeof(call));
-}
-
-int ftrace_update_ftrace_func(ftrace_func_t func)
-{
- unsigned char call[4];
- unsigned long ip = (unsigned long)&ftrace_call;
- bfin_make_pcrel24(call, ip, func);
- return ftrace_modify_code(ip, call, sizeof(call));
-}
-
-int __init ftrace_dyn_arch_init(void)
-{
- return 0;
-}
-
-#endif
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-
-# ifdef CONFIG_DYNAMIC_FTRACE
-
-extern void ftrace_graph_call(void);
-
-int ftrace_enable_ftrace_graph_caller(void)
-{
- unsigned long ip = (unsigned long)&ftrace_graph_call;
- uint16_t jump_pcrel12 = ((unsigned long)&ftrace_graph_caller - ip) >> 1;
- jump_pcrel12 |= 0x2000;
- return ftrace_modify_code(ip, (void *)&jump_pcrel12, sizeof(jump_pcrel12));
-}
-
-int ftrace_disable_ftrace_graph_caller(void)
-{
- return ftrace_modify_code((unsigned long)&ftrace_graph_call, empty_zero_page, 2);
-}
-
-# endif
-
-/*
- * Hook the return address and push it in the stack of return addrs
- * in current thread info.
- */
-void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
- unsigned long frame_pointer)
-{
- struct ftrace_graph_ent trace;
- unsigned long return_hooker = (unsigned long)&return_to_handler;
-
- if (unlikely(atomic_read(&current->tracing_graph_pause)))
- return;
-
- if (ftrace_push_return_trace(*parent, self_addr, &trace.depth,
- frame_pointer, NULL) == -EBUSY)
- return;
-
- trace.func = self_addr;
-
- /* Only trace if the calling function expects to */
- if (!ftrace_graph_entry(&trace)) {
- current->curr_ret_stack--;
- return;
- }
-
- /* all is well in the world ! hijack RETS ... */
- *parent = return_hooker;
-}
-
-#endif
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
deleted file mode 100644
index d776773d3869..000000000000
--- a/arch/blackfin/kernel/gptimers.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * gptimers.c - Blackfin General Purpose Timer core API
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPLv2.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-
-#include <asm/blackfin.h>
-#include <asm/gptimers.h>
-
-#ifdef DEBUG
-# define tassert(expr)
-#else
-# define tassert(expr) \
- if (!(expr)) \
- printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
-#endif
-
-#ifndef CONFIG_BF60x
-# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
-#else
-# define BFIN_TIMER_NUM_GROUP 1
-#endif
-
-static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
-{
- (void *)TIMER0_CONFIG,
- (void *)TIMER1_CONFIG,
- (void *)TIMER2_CONFIG,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- (void *)TIMER3_CONFIG,
- (void *)TIMER4_CONFIG,
- (void *)TIMER5_CONFIG,
- (void *)TIMER6_CONFIG,
- (void *)TIMER7_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_CONFIG,
- (void *)TIMER9_CONFIG,
- (void *)TIMER10_CONFIG,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- (void *)TIMER11_CONFIG,
-# endif
-# endif
-#endif
-};
-
-static struct bfin_gptimer_group_regs * const group_regs[BFIN_TIMER_NUM_GROUP] =
-{
- (void *)TIMER0_GROUP_REG,
-#if (MAX_BLACKFIN_GPTIMERS > 8)
- (void *)TIMER8_GROUP_REG,
-#endif
-};
-
-static uint32_t const trun_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TRUN0,
- TIMER_STATUS_TRUN1,
- TIMER_STATUS_TRUN2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TRUN3,
- TIMER_STATUS_TRUN4,
- TIMER_STATUS_TRUN5,
- TIMER_STATUS_TRUN6,
- TIMER_STATUS_TRUN7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TRUN8,
- TIMER_STATUS_TRUN9,
- TIMER_STATUS_TRUN10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TRUN11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const tovf_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TOVF0,
- TIMER_STATUS_TOVF1,
- TIMER_STATUS_TOVF2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TOVF3,
- TIMER_STATUS_TOVF4,
- TIMER_STATUS_TOVF5,
- TIMER_STATUS_TOVF6,
- TIMER_STATUS_TOVF7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TOVF8,
- TIMER_STATUS_TOVF9,
- TIMER_STATUS_TOVF10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TOVF11,
-# endif
-# endif
-#endif
-};
-
-static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] =
-{
- TIMER_STATUS_TIMIL0,
- TIMER_STATUS_TIMIL1,
- TIMER_STATUS_TIMIL2,
-#if (MAX_BLACKFIN_GPTIMERS > 3)
- TIMER_STATUS_TIMIL3,
- TIMER_STATUS_TIMIL4,
- TIMER_STATUS_TIMIL5,
- TIMER_STATUS_TIMIL6,
- TIMER_STATUS_TIMIL7,
-# if (MAX_BLACKFIN_GPTIMERS > 8)
- TIMER_STATUS_TIMIL8,
- TIMER_STATUS_TIMIL9,
- TIMER_STATUS_TIMIL10,
-# if (MAX_BLACKFIN_GPTIMERS > 11)
- TIMER_STATUS_TIMIL11,
-# endif
-# endif
-#endif
-};
-
-void set_gptimer_pwidth(unsigned int timer_id, uint32_t value)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->width, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pwidth);
-
-uint32_t get_gptimer_pwidth(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->width);
-}
-EXPORT_SYMBOL(get_gptimer_pwidth);
-
-void set_gptimer_period(unsigned int timer_id, uint32_t period)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->period, period);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_period);
-
-uint32_t get_gptimer_period(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->period);
-}
-EXPORT_SYMBOL(get_gptimer_period);
-
-uint32_t get_gptimer_count(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->counter);
-}
-EXPORT_SYMBOL(get_gptimer_count);
-
-#ifdef CONFIG_BF60x
-void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->delay, delay);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_delay);
-
-uint32_t get_gptimer_delay(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->delay);
-}
-EXPORT_SYMBOL(get_gptimer_delay);
-#endif
-
-#ifdef CONFIG_BF60x
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->data_ilat);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->data_ilat, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-#else
-uint32_t get_gptimer_status(unsigned int group)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- return bfin_read(&group_regs[group]->status);
-}
-EXPORT_SYMBOL(get_gptimer_status);
-
-void set_gptimer_status(unsigned int group, uint32_t value)
-{
- tassert(group < BFIN_TIMER_NUM_GROUP);
- bfin_write(&group_regs[group]->status, value);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_status);
-
-static uint32_t read_gptimer_status(unsigned int timer_id)
-{
- return bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status);
-}
-
-int get_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_intr);
-
-void clear_gptimer_intr(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, timil_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_intr);
-
-int get_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_over);
-
-void clear_gptimer_over(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->status, tovf_mask[timer_id]);
-}
-EXPORT_SYMBOL(clear_gptimer_over);
-
-int get_gptimer_run(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
-}
-EXPORT_SYMBOL(get_gptimer_run);
-#endif
-
-void set_gptimer_config(unsigned int timer_id, uint16_t config)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write(&timer_regs[timer_id]->config, config);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_config);
-
-uint16_t get_gptimer_config(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- return bfin_read(&timer_regs[timer_id]->config);
-}
-EXPORT_SYMBOL(get_gptimer_config);
-
-void enable_gptimers(uint16_t mask)
-{
- int i;
-#ifdef CONFIG_BF60x
- uint16_t imask;
- imask = bfin_read16(TIMER_DATA_IMSK);
- imask &= ~mask;
- bfin_write16(TIMER_DATA_IMSK, imask);
-#endif
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->enable, mask & 0xFF);
- mask >>= 8;
- }
- SSYNC();
-}
-EXPORT_SYMBOL(enable_gptimers);
-
-static void _disable_gptimers(uint16_t mask)
-{
- int i;
- uint16_t m = mask;
- tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
- bfin_write(&group_regs[i]->disable, m & 0xFF);
- m >>= 8;
- }
-}
-
-void disable_gptimers(uint16_t mask)
-{
-#ifndef CONFIG_BF60x
- int i;
- _disable_gptimers(mask);
- for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
- if (mask & (1 << i))
- bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
- SSYNC();
-#else
- _disable_gptimers(mask);
-#endif
-}
-EXPORT_SYMBOL(disable_gptimers);
-
-void disable_gptimers_sync(uint16_t mask)
-{
- _disable_gptimers(mask);
- SSYNC();
-}
-EXPORT_SYMBOL(disable_gptimers_sync);
-
-void set_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_or(&timer_regs[timer_id]->config, TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(set_gptimer_pulse_hi);
-
-void clear_gptimer_pulse_hi(unsigned int timer_id)
-{
- tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
- bfin_write_and(&timer_regs[timer_id]->config, ~TIMER_PULSE_HI);
- SSYNC();
-}
-EXPORT_SYMBOL(clear_gptimer_pulse_hi);
-
-uint16_t get_enabled_gptimers(void)
-{
- int i;
- uint16_t result = 0;
- for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i)
- result |= (bfin_read(&group_regs[i]->enable) << (i << 3));
- return result;
-}
-EXPORT_SYMBOL(get_enabled_gptimers);
-
-MODULE_AUTHOR("Axel Weiss (awe@aglaia-gmbh.de)");
-MODULE_DESCRIPTION("Blackfin General Purpose Timers API");
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
deleted file mode 100644
index f657b38163e3..000000000000
--- a/arch/blackfin/kernel/ipipe.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* -*- linux-c -*-
- * linux/arch/blackfin/kernel/ipipe.c
- *
- * Copyright (C) 2005-2007 Philippe Gerum.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
- * USA; either version 2 of the License, or (at your option) any later
- * version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- * Architecture-dependent I-pipe support for the Blackfin.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/percpu.h>
-#include <linux/bitops.h>
-#include <linux/errno.h>
-#include <linux/kthread.h>
-#include <linux/unistd.h>
-#include <linux/io.h>
-#include <linux/atomic.h>
-#include <asm/irq_handler.h>
-
-DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-
-static void __ipipe_no_irqtail(void);
-
-unsigned long __ipipe_irq_tail_hook = (unsigned long)&__ipipe_no_irqtail;
-EXPORT_SYMBOL(__ipipe_irq_tail_hook);
-
-unsigned long __ipipe_core_clock;
-EXPORT_SYMBOL(__ipipe_core_clock);
-
-unsigned long __ipipe_freq_scale;
-EXPORT_SYMBOL(__ipipe_freq_scale);
-
-atomic_t __ipipe_irq_lvdepth[IVG15 + 1];
-
-unsigned long __ipipe_irq_lvmask = bfin_no_irqs;
-EXPORT_SYMBOL(__ipipe_irq_lvmask);
-
-static void __ipipe_ack_irq(unsigned irq, struct irq_desc *desc)
-{
- desc->ipipe_ack(irq, desc);
-}
-
-/*
- * __ipipe_enable_pipeline() -- We are running on the boot CPU, hw
- * interrupts are off, and secondary CPUs are still lost in space.
- */
-void __ipipe_enable_pipeline(void)
-{
- unsigned irq;
-
- __ipipe_core_clock = get_cclk(); /* Fetch this once. */
- __ipipe_freq_scale = 1000000000UL / __ipipe_core_clock;
-
- for (irq = 0; irq < NR_IRQS; ++irq)
- ipipe_virtualize_irq(ipipe_root_domain,
- irq,
- (ipipe_irq_handler_t)&asm_do_IRQ,
- NULL,
- &__ipipe_ack_irq,
- IPIPE_HANDLE_MASK | IPIPE_PASS_MASK);
-}
-
-/*
- * __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic
- * interrupt protection log is maintained here for each domain. Hw
- * interrupts are masked on entry.
- */
-void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain, *next_domain;
- struct list_head *head, *pos;
- struct ipipe_irqdesc *idesc;
- int m_ack, s = -1;
-
- /*
- * Software-triggered IRQs do not need any ack. The contents
- * of the register frame should only be used when processing
- * the timer interrupt, but not for handling any other
- * interrupt.
- */
- m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
- this_domain = __ipipe_current_domain;
- idesc = &this_domain->irqs[irq];
-
- if (unlikely(test_bit(IPIPE_STICKY_FLAG, &idesc->control)))
- head = &this_domain->p_link;
- else {
- head = __ipipe_pipeline.next;
- next_domain = list_entry(head, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (likely(test_bit(IPIPE_WIRED_FLAG, &idesc->control))) {
- if (!m_ack && idesc->acknowledge != NULL)
- idesc->acknowledge(irq, irq_to_desc(irq));
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG,
- &p->status);
- __ipipe_dispatch_wired(next_domain, irq);
- goto out;
- }
- }
-
- /* Ack the interrupt. */
-
- pos = head;
- while (pos != &__ipipe_pipeline) {
- next_domain = list_entry(pos, struct ipipe_domain, p_link);
- idesc = &next_domain->irqs[irq];
- if (test_bit(IPIPE_HANDLE_FLAG, &idesc->control)) {
- __ipipe_set_irq_pending(next_domain, irq);
- if (!m_ack && idesc->acknowledge != NULL) {
- idesc->acknowledge(irq, irq_to_desc(irq));
- m_ack = 1;
- }
- }
- if (!test_bit(IPIPE_PASS_FLAG, &idesc->control))
- break;
- pos = next_domain->p_link.next;
- }
-
- /*
- * Now walk the pipeline, yielding control to the highest
- * priority domain that has pending interrupt(s) or
- * immediately to the current domain if the interrupt has been
- * marked as 'sticky'. This search does not go beyond the
- * current domain in the pipeline. We also enforce the
- * additional root stage lock (blackfin-specific).
- */
- if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
- s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
-
- /*
- * If the interrupt preempted the head domain, then do not
- * even try to walk the pipeline, unless an interrupt is
- * pending for it.
- */
- if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
- !__ipipe_ipending_p(ipipe_head_cpudom_ptr()))
- goto out;
-
- __ipipe_walk_pipeline(head);
-out:
- if (!s)
- __clear_bit(IPIPE_STALL_FLAG, &p->status);
-}
-
-void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- struct irq_desc *desc = irq_to_desc(irq);
- int prio = __ipipe_get_irq_priority(irq);
-
- desc->depth = 0;
- if (ipd != &ipipe_root &&
- atomic_inc_return(&__ipipe_irq_lvdepth[prio]) == 1)
- __set_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_enable_irqdesc);
-
-void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
-{
- int prio = __ipipe_get_irq_priority(irq);
-
- if (ipd != &ipipe_root &&
- atomic_dec_and_test(&__ipipe_irq_lvdepth[prio]))
- __clear_bit(prio, &__ipipe_irq_lvmask);
-}
-EXPORT_SYMBOL(__ipipe_disable_irqdesc);
-
-asmlinkage int __ipipe_syscall_root(struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p;
- void (*hook)(void);
- int ret;
-
- WARN_ON_ONCE(irqs_disabled_hw());
-
- /*
- * We need to run the IRQ tail hook each time we intercept a
- * syscall, because we know that important operations might be
- * pending there (e.g. Xenomai deferred rescheduling).
- */
- hook = (__typeof__(hook))__ipipe_irq_tail_hook;
- hook();
-
- /*
- * This routine either returns:
- * 0 -- if the syscall is to be passed to Linux;
- * >0 -- if the syscall should not be passed to Linux, and no
- * tail work should be performed;
- * <0 -- if the syscall should not be passed to Linux but the
- * tail work has to be performed (for handling signals etc).
- */
-
- if (!__ipipe_syscall_watched_p(current, regs->orig_p0) ||
- !__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL))
- return 0;
-
- ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
-
- hard_local_irq_disable();
-
- /*
- * This is the end of the syscall path, so we may
- * safely assume a valid Linux task stack here.
- */
- if (current->ipipe_flags & PF_EVTRET) {
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (!__ipipe_root_domain_p)
- ret = -1;
- else {
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
- }
-
- hard_local_irq_enable();
-
- return -ret;
-}
-
-static void __ipipe_no_irqtail(void)
-{
-}
-
-int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
-{
- info->sys_nr_cpus = num_online_cpus();
- info->sys_cpu_freq = ipipe_cpu_freq();
- info->sys_hrtimer_irq = IPIPE_TIMER_IRQ;
- info->sys_hrtimer_freq = __ipipe_core_clock;
- info->sys_hrclock_freq = __ipipe_core_clock;
-
- return 0;
-}
-
-/*
- * ipipe_trigger_irq() -- Push the interrupt at front of the pipeline
- * just like if it has been actually received from a hw source. Also
- * works for virtual interrupts.
- */
-int ipipe_trigger_irq(unsigned irq)
-{
- unsigned long flags;
-
-#ifdef CONFIG_IPIPE_DEBUG
- if (irq >= IPIPE_NR_IRQS ||
- (ipipe_virtual_irq_p(irq)
- && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
- return -EINVAL;
-#endif
-
- flags = hard_local_irq_save();
- __ipipe_handle_irq(irq, NULL);
- hard_local_irq_restore(flags);
-
- return 1;
-}
-
-asmlinkage void __ipipe_sync_root(void)
-{
- void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
- struct ipipe_percpu_domain_data *p;
- unsigned long flags;
-
- BUG_ON(irqs_disabled());
-
- flags = hard_local_irq_save();
-
- if (irq_tail_hook)
- irq_tail_hook();
-
- clear_thread_flag(TIF_IRQ_SYNC);
-
- p = ipipe_root_cpudom_ptr();
- if (__ipipe_ipending_p(p))
- __ipipe_sync_pipeline();
-
- hard_local_irq_restore(flags);
-}
-
-void ___ipipe_sync_pipeline(void)
-{
- if (__ipipe_root_domain_p &&
- test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
- return;
-
- __ipipe_sync_stage();
-}
-
-void __ipipe_disable_root_irqs_hw(void)
-{
- /*
- * This code is called by the ins{bwl} routines (see
- * arch/blackfin/lib/ins.S), which are heavily used by the
- * network stack. It masks all interrupts but those handled by
- * non-root domains, so that we keep decent network transfer
- * rates for Linux without inducing pathological jitter for
- * the real-time domain.
- */
- bfin_sti(__ipipe_irq_lvmask);
- __set_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
-}
-
-void __ipipe_enable_root_irqs_hw(void)
-{
- __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
- bfin_sti(bfin_irq_flags);
-}
-
-/*
- * We could use standard atomic bitops in the following root status
- * manipulation routines, but let's prepare for SMP support in the
- * same move, preventing CPU migration as required.
- */
-void __ipipe_stall_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_stall_root);
-
-unsigned long __ipipe_test_and_stall_root(void)
-{
- unsigned long *p, flags;
- int x;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- x = __test_and_set_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_and_stall_root);
-
-unsigned long __ipipe_test_root(void)
-{
- const unsigned long *p;
- unsigned long flags;
- int x;
-
- flags = hard_local_irq_save_smp();
- p = &__ipipe_root_status;
- x = test_bit(IPIPE_STALL_FLAG, p);
- hard_local_irq_restore_smp(flags);
-
- return x;
-}
-EXPORT_SYMBOL(__ipipe_test_root);
-
-void __ipipe_lock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __set_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_lock_root);
-
-void __ipipe_unlock_root(void)
-{
- unsigned long *p, flags;
-
- flags = hard_local_irq_save();
- p = &__ipipe_root_status;
- __clear_bit(IPIPE_SYNCDEFER_FLAG, p);
- hard_local_irq_restore(flags);
-}
-EXPORT_SYMBOL(__ipipe_unlock_root);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
deleted file mode 100644
index 052cde5ed2e4..000000000000
--- a/arch/blackfin/kernel/irqchip.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/random.h>
-#include <linux/seq_file.h>
-#include <linux/kallsyms.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/seq_file.h>
-#include <asm/irq_handler.h>
-#include <asm/trace.h>
-#include <asm/pda.h>
-
-static atomic_t irq_err_count;
-void ack_bad_irq(unsigned int irq)
-{
- atomic_inc(&irq_err_count);
- printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
-}
-
-static struct irq_desc bad_irq_desc = {
- .handle_irq = handle_bad_irq,
- .lock = __RAW_SPIN_LOCK_UNLOCKED(bad_irq_desc.lock),
-};
-
-#ifdef CONFIG_CPUMASK_OFFSTACK
-/* We are not allocating a variable-sized bad_irq_desc.affinity */
-#error "Blackfin architecture does not support CONFIG_CPUMASK_OFFSTACK."
-#endif
-
-#ifdef CONFIG_PROC_FS
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
- int j;
-
- seq_printf(p, "%*s: ", prec, "NMI");
- for_each_online_cpu(j)
- seq_printf(p, "%10u ", cpu_pda[j].__nmi_count);
- seq_printf(p, " CORE Non Maskable Interrupt\n");
- seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
-static void check_stack_overflow(int irq)
-{
- /* Debugging check for stack overflow: is there less than STACK_WARN free? */
- long sp = __get_SP() & (THREAD_SIZE - 1);
-
- if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
- dump_stack();
- pr_emerg("irq%i: possible stack overflow only %ld bytes free\n",
- irq, sp - sizeof(struct thread_info));
- }
-}
-#else
-static inline void check_stack_overflow(int irq) { }
-#endif
-
-#ifndef CONFIG_IPIPE
-static void maybe_lower_to_irq14(void)
-{
- unsigned short pending, other_ints;
-
- /*
- * If we're the only interrupt running (ignoring IRQ15 which
- * is for syscalls), lower our priority to IRQ14 so that
- * softirqs run at that level. If there's another,
- * lower-level interrupt, irq_exit will defer softirqs to
- * that. If the interrupt pipeline is enabled, we are already
- * running at IRQ14 priority, so we don't need this code.
- */
- CSYNC();
- pending = bfin_read_IPEND() & ~0x8000;
- other_ints = pending & (pending - 1);
- if (other_ints == 0)
- lower_to_irq14();
-}
-#else
-static inline void maybe_lower_to_irq14(void) { }
-#endif
-
-/*
- * do_IRQ handles all hardware IRQs. Decoded IRQs should not
- * come via this function. Instead, they should provide their
- * own 'handler'
- */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
-{
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- check_stack_overflow(irq);
-
- /*
- * Some hardware gives randomly wrong interrupts. Rather
- * than crashing, do something sensible.
- */
- if (irq >= NR_IRQS)
- handle_bad_irq(&bad_irq_desc);
- else
- generic_handle_irq(irq);
-
- maybe_lower_to_irq14();
-
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-void __init init_IRQ(void)
-{
- init_arch_irq();
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- /* Now that evt_ivhw is set up, turn this on */
- trace_buff_offset = 0;
- bfin_write_TBUFCTL(BFIN_TRACE_ON);
- printk(KERN_INFO "Hardware Trace expanded to %ik\n",
- 1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN);
-#endif
-}
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
deleted file mode 100644
index cf773f0f1f30..000000000000
--- a/arch/blackfin/kernel/kgdb.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/ptrace.h> /* for linux pt_regs struct */
-#include <linux/kgdb.h>
-#include <linux/uaccess.h>
-#include <asm/irq_regs.h>
-
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- gdb_regs[BFIN_R0] = regs->r0;
- gdb_regs[BFIN_R1] = regs->r1;
- gdb_regs[BFIN_R2] = regs->r2;
- gdb_regs[BFIN_R3] = regs->r3;
- gdb_regs[BFIN_R4] = regs->r4;
- gdb_regs[BFIN_R5] = regs->r5;
- gdb_regs[BFIN_R6] = regs->r6;
- gdb_regs[BFIN_R7] = regs->r7;
- gdb_regs[BFIN_P0] = regs->p0;
- gdb_regs[BFIN_P1] = regs->p1;
- gdb_regs[BFIN_P2] = regs->p2;
- gdb_regs[BFIN_P3] = regs->p3;
- gdb_regs[BFIN_P4] = regs->p4;
- gdb_regs[BFIN_P5] = regs->p5;
- gdb_regs[BFIN_SP] = regs->reserved;
- gdb_regs[BFIN_FP] = regs->fp;
- gdb_regs[BFIN_I0] = regs->i0;
- gdb_regs[BFIN_I1] = regs->i1;
- gdb_regs[BFIN_I2] = regs->i2;
- gdb_regs[BFIN_I3] = regs->i3;
- gdb_regs[BFIN_M0] = regs->m0;
- gdb_regs[BFIN_M1] = regs->m1;
- gdb_regs[BFIN_M2] = regs->m2;
- gdb_regs[BFIN_M3] = regs->m3;
- gdb_regs[BFIN_B0] = regs->b0;
- gdb_regs[BFIN_B1] = regs->b1;
- gdb_regs[BFIN_B2] = regs->b2;
- gdb_regs[BFIN_B3] = regs->b3;
- gdb_regs[BFIN_L0] = regs->l0;
- gdb_regs[BFIN_L1] = regs->l1;
- gdb_regs[BFIN_L2] = regs->l2;
- gdb_regs[BFIN_L3] = regs->l3;
- gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
- gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
- gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
- gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
- gdb_regs[BFIN_ASTAT] = regs->astat;
- gdb_regs[BFIN_RETS] = regs->rets;
- gdb_regs[BFIN_LC0] = regs->lc0;
- gdb_regs[BFIN_LT0] = regs->lt0;
- gdb_regs[BFIN_LB0] = regs->lb0;
- gdb_regs[BFIN_LC1] = regs->lc1;
- gdb_regs[BFIN_LT1] = regs->lt1;
- gdb_regs[BFIN_LB1] = regs->lb1;
- gdb_regs[BFIN_CYCLES] = 0;
- gdb_regs[BFIN_CYCLES2] = 0;
- gdb_regs[BFIN_USP] = regs->usp;
- gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
- gdb_regs[BFIN_SYSCFG] = regs->syscfg;
- gdb_regs[BFIN_RETI] = regs->pc;
- gdb_regs[BFIN_RETX] = regs->retx;
- gdb_regs[BFIN_RETN] = regs->retn;
- gdb_regs[BFIN_RETE] = regs->rete;
- gdb_regs[BFIN_PC] = regs->pc;
- gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
- gdb_regs[BFIN_EXTRA1] = 0;
- gdb_regs[BFIN_EXTRA2] = 0;
- gdb_regs[BFIN_EXTRA3] = 0;
- gdb_regs[BFIN_IPEND] = regs->ipend;
-}
-
-/*
- * Extracts ebp, esp and eip values understandable by gdb from the values
- * saved by switch_to.
- * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
- * prior to entering switch_to is 8 greater than the value that is saved.
- * If switch_to changes, change following code appropriately.
- */
-void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
-{
- gdb_regs[BFIN_SP] = p->thread.ksp;
- gdb_regs[BFIN_PC] = p->thread.pc;
- gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
-}
-
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- regs->r0 = gdb_regs[BFIN_R0];
- regs->r1 = gdb_regs[BFIN_R1];
- regs->r2 = gdb_regs[BFIN_R2];
- regs->r3 = gdb_regs[BFIN_R3];
- regs->r4 = gdb_regs[BFIN_R4];
- regs->r5 = gdb_regs[BFIN_R5];
- regs->r6 = gdb_regs[BFIN_R6];
- regs->r7 = gdb_regs[BFIN_R7];
- regs->p0 = gdb_regs[BFIN_P0];
- regs->p1 = gdb_regs[BFIN_P1];
- regs->p2 = gdb_regs[BFIN_P2];
- regs->p3 = gdb_regs[BFIN_P3];
- regs->p4 = gdb_regs[BFIN_P4];
- regs->p5 = gdb_regs[BFIN_P5];
- regs->fp = gdb_regs[BFIN_FP];
- regs->i0 = gdb_regs[BFIN_I0];
- regs->i1 = gdb_regs[BFIN_I1];
- regs->i2 = gdb_regs[BFIN_I2];
- regs->i3 = gdb_regs[BFIN_I3];
- regs->m0 = gdb_regs[BFIN_M0];
- regs->m1 = gdb_regs[BFIN_M1];
- regs->m2 = gdb_regs[BFIN_M2];
- regs->m3 = gdb_regs[BFIN_M3];
- regs->b0 = gdb_regs[BFIN_B0];
- regs->b1 = gdb_regs[BFIN_B1];
- regs->b2 = gdb_regs[BFIN_B2];
- regs->b3 = gdb_regs[BFIN_B3];
- regs->l0 = gdb_regs[BFIN_L0];
- regs->l1 = gdb_regs[BFIN_L1];
- regs->l2 = gdb_regs[BFIN_L2];
- regs->l3 = gdb_regs[BFIN_L3];
- regs->a0x = gdb_regs[BFIN_A0_DOT_X];
- regs->a0w = gdb_regs[BFIN_A0_DOT_W];
- regs->a1x = gdb_regs[BFIN_A1_DOT_X];
- regs->a1w = gdb_regs[BFIN_A1_DOT_W];
- regs->rets = gdb_regs[BFIN_RETS];
- regs->lc0 = gdb_regs[BFIN_LC0];
- regs->lt0 = gdb_regs[BFIN_LT0];
- regs->lb0 = gdb_regs[BFIN_LB0];
- regs->lc1 = gdb_regs[BFIN_LC1];
- regs->lt1 = gdb_regs[BFIN_LT1];
- regs->lb1 = gdb_regs[BFIN_LB1];
- regs->usp = gdb_regs[BFIN_USP];
- regs->syscfg = gdb_regs[BFIN_SYSCFG];
- regs->retx = gdb_regs[BFIN_RETX];
- regs->retn = gdb_regs[BFIN_RETN];
- regs->rete = gdb_regs[BFIN_RETE];
- regs->pc = gdb_regs[BFIN_PC];
-
-#if 0 /* can't change these */
- regs->astat = gdb_regs[BFIN_ASTAT];
- regs->seqstat = gdb_regs[BFIN_SEQSTAT];
- regs->ipend = gdb_regs[BFIN_IPEND];
-#endif
-}
-
-static struct hw_breakpoint {
- unsigned int occupied:1;
- unsigned int skip:1;
- unsigned int enabled:1;
- unsigned int type:1;
- unsigned int dataacc:2;
- unsigned short count;
- unsigned int addr;
-} breakinfo[HW_WATCHPOINT_NUM];
-
-static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
- int dataacc = 0;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- dataacc = 1;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_READ_WATCHPOINT:
- dataacc = 2;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- case BP_ACCESS_WATCHPOINT:
- dataacc = 3;
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return -ENOSPC;
- }
-
- /* Because hardware data watchpoint impelemented in current
- * Blackfin can not trigger an exception event as the hardware
- * instrction watchpoint does, we ignaore all data watch point here.
- * They can be turned on easily after future blackfin design
- * supports this feature.
- */
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && !breakinfo[breakno].occupied) {
- breakinfo[breakno].occupied = 1;
- breakinfo[breakno].skip = 0;
- breakinfo[breakno].enabled = 1;
- breakinfo[breakno].addr = addr;
- breakinfo[breakno].dataacc = dataacc;
- breakinfo[breakno].count = 0;
- return 0;
- }
-
- return -ENOSPC;
-}
-
-static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
-{
- int breakno;
- int bfin_type;
-
- switch (type) {
- case BP_HARDWARE_BREAKPOINT:
- bfin_type = TYPE_INST_WATCHPOINT;
- break;
- case BP_WRITE_WATCHPOINT:
- case BP_READ_WATCHPOINT:
- case BP_ACCESS_WATCHPOINT:
- bfin_type = TYPE_DATA_WATCHPOINT;
- break;
- default:
- return 0;
- }
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (bfin_type == breakinfo[breakno].type
- && breakinfo[breakno].occupied
- && breakinfo[breakno].addr == addr) {
- breakinfo[breakno].occupied = 0;
- breakinfo[breakno].enabled = 0;
- }
-
- return 0;
-}
-
-static void bfin_remove_all_hw_break(void)
-{
- int breakno;
-
- memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
-
- for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
- for (; breakno < HW_WATCHPOINT_NUM; breakno++)
- breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
-}
-
-static void bfin_correct_hw_break(void)
-{
- int breakno;
- unsigned int wpiactl = 0;
- unsigned int wpdactl = 0;
- int enable_wp = 0;
-
- for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
- if (breakinfo[breakno].enabled) {
- enable_wp = 1;
-
- switch (breakno) {
- case 0:
- wpiactl |= WPIAEN0|WPICNTEN0;
- bfin_write_WPIA0(breakinfo[breakno].addr);
- bfin_write_WPIACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 1:
- wpiactl |= WPIAEN1|WPICNTEN1;
- bfin_write_WPIA1(breakinfo[breakno].addr);
- bfin_write_WPIACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 2:
- wpiactl |= WPIAEN2|WPICNTEN2;
- bfin_write_WPIA2(breakinfo[breakno].addr);
- bfin_write_WPIACNT2(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 3:
- wpiactl |= WPIAEN3|WPICNTEN3;
- bfin_write_WPIA3(breakinfo[breakno].addr);
- bfin_write_WPIACNT3(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 4:
- wpiactl |= WPIAEN4|WPICNTEN4;
- bfin_write_WPIA4(breakinfo[breakno].addr);
- bfin_write_WPIACNT4(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 5:
- wpiactl |= WPIAEN5|WPICNTEN5;
- bfin_write_WPIA5(breakinfo[breakno].addr);
- bfin_write_WPIACNT5(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 6:
- wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC0_OFFSET;
- bfin_write_WPDA0(breakinfo[breakno].addr);
- bfin_write_WPDACNT0(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- case 7:
- wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
- wpdactl |= breakinfo[breakno].dataacc
- << WPDACC1_OFFSET;
- bfin_write_WPDA1(breakinfo[breakno].addr);
- bfin_write_WPDACNT1(breakinfo[breakno].count
- + breakinfo->skip);
- break;
- }
- }
-
- /* Should enable WPPWR bit first before set any other
- * WPIACTL and WPDACTL bits */
- if (enable_wp) {
- bfin_write_WPIACTL(WPPWR);
- CSYNC();
- bfin_write_WPIACTL(wpiactl|WPPWR);
- bfin_write_WPDACTL(wpdactl);
- CSYNC();
- }
-}
-
-static void bfin_disable_hw_debug(struct pt_regs *regs)
-{
- /* Disable hardware debugging while we are in kgdb */
- bfin_write_WPIACTL(0);
- bfin_write_WPDACTL(0);
- CSYNC();
-}
-
-#ifdef CONFIG_SMP
-void kgdb_passive_cpu_callback(void *info)
-{
- kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
-}
-
-void kgdb_roundup_cpus(unsigned long flags)
-{
- unsigned int cpu;
-
- for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids;
- cpu = cpumask_next(cpu, cpu_online_mask))
- smp_call_function_single(cpu, kgdb_passive_cpu_callback,
- NULL, 0);
-}
-
-void kgdb_roundup_cpu(int cpu, unsigned long flags)
-{
- smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
-}
-#endif
-
-#ifdef CONFIG_IPIPE
-static unsigned long kgdb_arch_imask;
-#endif
-
-int kgdb_arch_handle_exception(int vector, int signo,
- int err_code, char *remcom_in_buffer,
- char *remcom_out_buffer,
- struct pt_regs *regs)
-{
- long addr;
- char *ptr;
- int newPC;
- int i;
-
- switch (remcom_in_buffer[0]) {
- case 'c':
- case 's':
- if (kgdb_contthread && kgdb_contthread != current) {
- strcpy(remcom_out_buffer, "E00");
- break;
- }
-
- kgdb_contthread = NULL;
-
- /* try to read optional parameter, pc unchanged if no parm */
- ptr = &remcom_in_buffer[1];
- if (kgdb_hex2long(&ptr, &addr)) {
- regs->retx = addr;
- }
- newPC = regs->retx;
-
- /* clear the trace bit */
- regs->syscfg &= 0xfffffffe;
-
- /* set the trace bit if we're stepping */
- if (remcom_in_buffer[0] == 's') {
- regs->syscfg |= 0x1;
- kgdb_single_step = regs->ipend;
- kgdb_single_step >>= 6;
- for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
- if (kgdb_single_step & 1)
- break;
- /* i indicate event priority of current stopped instruction
- * user space instruction is 0, IVG15 is 1, IVTMR is 10.
- * kgdb_single_step > 0 means in single step mode
- */
- kgdb_single_step = i + 1;
-
- preempt_disable();
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
- cpu_pda[raw_smp_processor_id()].ex_imask = 0;
-#endif
- }
-
- bfin_correct_hw_break();
-
- return 0;
- } /* switch */
- return -1; /* this means that we do not want to exit from the handler */
-}
-
-struct kgdb_arch arch_kgdb_ops = {
- .gdb_bpt_instr = {0xa1},
- .flags = KGDB_HW_BREAKPOINT,
- .set_hw_breakpoint = bfin_set_hw_break,
- .remove_hw_breakpoint = bfin_remove_hw_break,
- .disable_hw_break = bfin_disable_hw_debug,
- .remove_all_hw_break = bfin_remove_all_hw_break,
- .correct_hw_break = bfin_correct_hw_break,
-};
-
-#define IN_MEM(addr, size, l1_addr, l1_size) \
-({ \
- unsigned long __addr = (unsigned long)(addr); \
- (l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
-})
-#define ASYNC_BANK_SIZE \
- (ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
- ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
-
-int kgdb_validate_break_address(unsigned long addr)
-{
- int cpu = raw_smp_processor_id();
-
- if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
- return 0;
- if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
- return 0;
- if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#ifdef CONFIG_SMP
- else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
- return 0;
-#endif
- if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
- return 0;
-
- return -EFAULT;
-}
-
-void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
-{
- regs->retx = ip;
-}
-
-int kgdb_arch_init(void)
-{
- kgdb_single_step = 0;
-#ifdef CONFIG_IPIPE
- kgdb_arch_imask = 0;
-#endif
-
- bfin_remove_all_hw_break();
- return 0;
-}
-
-void kgdb_arch_exit(void)
-{
-}
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
deleted file mode 100644
index b8b785dc4e3b..000000000000
--- a/arch/blackfin/kernel/kgdb_test.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * arch/blackfin/kernel/kgdb_test.c - Blackfin kgdb tests
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/proc_fs.h>
-
-#include <asm/current.h>
-#include <linux/uaccess.h>
-
-#include <asm/blackfin.h>
-
-/* Symbols are here for kgdb test to poke directly */
-static char cmdline[256];
-static size_t len;
-
-#ifndef CONFIG_SMP
-static int num1 __attribute__((l1_data));
-
-void kgdb_l1_test(void) __attribute__((l1_text));
-
-void kgdb_l1_test(void)
-{
- pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
- pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test);
- num1 = num1 + 10;
- pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
-}
-#endif
-
-#if L2_LENGTH
-
-static int num2 __attribute__((l2));
-void kgdb_l2_test(void) __attribute__((l2));
-
-void kgdb_l2_test(void)
-{
- pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
- pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test);
- num2 = num2 + 20;
- pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2);
-}
-
-#endif
-
-noinline int kgdb_test(char *name, int len, int count, int z)
-{
- pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z);
- count = z;
- return count;
-}
-
-static ssize_t
-kgdb_test_proc_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- kgdb_test("hello world!", 12, 0x55, 0x10);
-#ifndef CONFIG_SMP
- kgdb_l1_test();
-#endif
-#if L2_LENGTH
- kgdb_l2_test();
-#endif
-
- return 0;
-}
-
-static ssize_t
-kgdb_test_proc_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *pos)
-{
- len = min_t(size_t, 255, count);
- memcpy(cmdline, buffer, count);
- cmdline[len] = 0;
-
- return len;
-}
-
-static const struct file_operations kgdb_test_proc_fops = {
- .owner = THIS_MODULE,
- .read = kgdb_test_proc_read,
- .write = kgdb_test_proc_write,
- .llseek = noop_llseek,
-};
-
-static int __init kgdbtest_init(void)
-{
- struct proc_dir_entry *entry;
-
-#if L2_LENGTH
- num2 = 0;
-#endif
-
- entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
- if (entry == NULL)
- return -ENOMEM;
-
- return 0;
-}
-
-static void __exit kgdbtest_exit(void)
-{
- remove_proc_entry("kgdbtest", NULL);
-}
-
-module_init(kgdbtest_init);
-module_exit(kgdbtest_exit);
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
deleted file mode 100644
index 15af5768c403..000000000000
--- a/arch/blackfin/kernel/module.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/dma.h>
-#include <asm/cacheflush.h>
-#include <linux/uaccess.h>
-
-#define mod_err(mod, fmt, ...) \
- pr_err("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-#define mod_debug(mod, fmt, ...) \
- pr_debug("module %s: " fmt, (mod)->name, ##__VA_ARGS__)
-
-/* Transfer the section to the L1 memory */
-int
-module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
- char *secstrings, struct module *mod)
-{
- /*
- * XXX: sechdrs are vmalloced in kernel/module.c
- * and would be vfreed just after module is loaded,
- * so we hack to keep the only information we needed
- * in mod->arch to correctly free L1 I/D sram later.
- * NOTE: this breaks the semantic of mod->arch structure.
- */
- Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
- void *dest;
-
- for (s = sechdrs; s < sechdrs_end; ++s) {
- const char *shname = secstrings + s->sh_name;
-
- if (s->sh_size == 0)
- continue;
-
- if (!strcmp(".l1.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L1))) {
-
- dest = l1_inst_sram_alloc(s->sh_size);
- mod->arch.text_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 inst memory allocation failed\n");
- return -1;
- }
- dma_memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_alloc(s->sh_size);
- mod->arch.data_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L1))) {
-
- dest = l1_data_sram_zalloc(s->sh_size);
- mod->arch.bss_a_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
-
- } else if (!strcmp(".l1.data.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.data_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l1.bss.B", shname)) {
-
- dest = l1_data_B_sram_alloc(s->sh_size);
- mod->arch.bss_b_l1 = dest;
- if (dest == NULL) {
- mod_err(mod, "L1 data memory allocation failed\n");
- return -1;
- }
- memset(dest, 0, s->sh_size);
-
- } else if (!strcmp(".l2.text", shname) ||
- (!strcmp(".text", shname) &&
- (hdr->e_flags & EF_BFIN_CODE_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.text_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.data", shname) ||
- (!strcmp(".data", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_alloc(s->sh_size);
- mod->arch.data_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
- memcpy(dest, (void *)s->sh_addr, s->sh_size);
-
- } else if (!strcmp(".l2.bss", shname) ||
- (!strcmp(".bss", shname) &&
- (hdr->e_flags & EF_BFIN_DATA_IN_L2))) {
-
- dest = l2_sram_zalloc(s->sh_size);
- mod->arch.bss_l2 = dest;
- if (dest == NULL) {
- mod_err(mod, "L2 SRAM allocation failed\n");
- return -1;
- }
-
- } else
- continue;
-
- s->sh_flags &= ~SHF_ALLOC;
- s->sh_addr = (unsigned long)dest;
- }
-
- return 0;
-}
-
-/*************************************************************************/
-/* FUNCTION : apply_relocate_add */
-/* ABSTRACT : Blackfin specific relocation handling for the loadable */
-/* modules. Modules are expected to be .o files. */
-/* Arithmetic relocations are handled. */
-/* We do not expect LSETUP to be split and hence is not */
-/* handled. */
-/* R_BFIN_BYTE and R_BFIN_BYTE2 are also not handled as the */
-/* gas does not generate it. */
-/*************************************************************************/
-int
-apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
- unsigned int symindex, unsigned int relsec,
- struct module *mod)
-{
- unsigned int i;
- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf32_Sym *sym;
- unsigned long location, value, size;
-
- mod_debug(mod, "applying relocate section %u to %u\n",
- relsec, sechdrs[relsec].sh_info);
-
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* This is where to make the change */
- location = sechdrs[sechdrs[relsec].sh_info].sh_addr +
- rel[i].r_offset;
-
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- sym = (Elf32_Sym *) sechdrs[symindex].sh_addr
- + ELF32_R_SYM(rel[i].r_info);
- value = sym->st_value;
- value += rel[i].r_addend;
-
-#ifdef CONFIG_SMP
- if (location >= COREB_L1_DATA_A_START) {
- mod_err(mod, "cannot relocate in L1: %u (SMP kernel)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-#endif
-
- mod_debug(mod, "location is %lx, value is %lx type is %d\n",
- location, value, ELF32_R_TYPE(rel[i].r_info));
-
- switch (ELF32_R_TYPE(rel[i].r_info)) {
-
- case R_BFIN_HUIMM16:
- value >>= 16;
- case R_BFIN_LUIMM16:
- case R_BFIN_RIMM16:
- size = 2;
- break;
- case R_BFIN_BYTE4_DATA:
- size = 4;
- break;
-
- case R_BFIN_PCREL24:
- case R_BFIN_PCREL24_JUMP_L:
- case R_BFIN_PCREL12_JUMP:
- case R_BFIN_PCREL12_JUMP_S:
- case R_BFIN_PCREL10:
- mod_err(mod, "unsupported relocation: %u (no -mlong-calls?)\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
-
- default:
- mod_err(mod, "unknown relocation: %u\n",
- ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
-
- switch (bfin_mem_access_type(location, size)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy((void *)location, &value, size);
- break;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy((void *)location, &value, size);
- break;
- default:
- mod_err(mod, "invalid relocation for %#lx\n", location);
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-int
-module_finalize(const Elf_Ehdr * hdr,
- const Elf_Shdr * sechdrs, struct module *mod)
-{
- unsigned int i, strindex = 0, symindex = 0;
- char *secstrings;
- long err = 0;
-
- secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
-
- for (i = 1; i < hdr->e_shnum; i++) {
- /* Internal symbols and strings. */
- if (sechdrs[i].sh_type == SHT_SYMTAB) {
- symindex = i;
- strindex = sechdrs[i].sh_link;
- }
- }
-
- for (i = 1; i < hdr->e_shnum; i++) {
- const char *strtab = (char *)sechdrs[strindex].sh_addr;
- unsigned int info = sechdrs[i].sh_info;
- const char *shname = secstrings + sechdrs[i].sh_name;
-
- /* Not a valid relocation section? */
- if (info >= hdr->e_shnum)
- continue;
-
- /* Only support RELA relocation types */
- if (sechdrs[i].sh_type != SHT_RELA)
- continue;
-
- if (!strcmp(".rela.l2.text", shname) ||
- !strcmp(".rela.l1.text", shname) ||
- (!strcmp(".rela.text", shname) &&
- (hdr->e_flags & (EF_BFIN_CODE_IN_L1 | EF_BFIN_CODE_IN_L2)))) {
-
- err = apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
- symindex, i, mod);
- if (err < 0)
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-void module_arch_cleanup(struct module *mod)
-{
- l1_inst_sram_free(mod->arch.text_l1);
- l1_data_A_sram_free(mod->arch.data_a_l1);
- l1_data_A_sram_free(mod->arch.bss_a_l1);
- l1_data_B_sram_free(mod->arch.data_b_l1);
- l1_data_B_sram_free(mod->arch.bss_b_l1);
- l2_sram_free(mod->arch.text_l2);
- l2_sram_free(mod->arch.data_l2);
- l2_sram_free(mod->arch.bss_l2);
-}
diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c
deleted file mode 100644
index 8a211d95821f..000000000000
--- a/arch/blackfin/kernel/nmi.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Blackfin nmi_watchdog Driver
- *
- * Originally based on bfin_wdt.c
- * Copyright 2010-2010 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/bitops.h>
-#include <linux/hardirq.h>
-#include <linux/syscore_ops.h>
-#include <linux/pm.h>
-#include <linux/nmi.h>
-#include <linux/smp.h>
-#include <linux/timer.h>
-#include <linux/sched/debug.h>
-#include <asm/blackfin.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/bfin_watchdog.h>
-
-#define DRV_NAME "nmi-wdt"
-
-#define NMI_WDT_TIMEOUT 5 /* 5 seconds */
-#define NMI_CHECK_TIMEOUT (4 * HZ) /* 4 seconds in jiffies */
-static int nmi_wdt_cpu = 1;
-
-static unsigned int timeout = NMI_WDT_TIMEOUT;
-static int nmi_active;
-
-static unsigned short wdoga_ctl;
-static unsigned int wdoga_cnt;
-static struct corelock_slot saved_corelock;
-static atomic_t nmi_touched[NR_CPUS];
-static struct timer_list ntimer;
-
-enum {
- COREA_ENTER_NMI = 0,
- COREA_EXIT_NMI,
- COREB_EXIT_NMI,
-
- NMI_EVENT_NR,
-};
-static unsigned long nmi_event __attribute__ ((__section__(".l2.bss")));
-
-/* we are in nmi, non-atomic bit ops is safe */
-static inline void set_nmi_event(int event)
-{
- __set_bit(event, &nmi_event);
-}
-
-static inline void wait_nmi_event(int event)
-{
- while (!test_bit(event, &nmi_event))
- barrier();
- __clear_bit(event, &nmi_event);
-}
-
-static inline void send_corea_nmi(void)
-{
- wdoga_ctl = bfin_read_WDOGA_CTL();
- wdoga_cnt = bfin_read_WDOGA_CNT();
-
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CNT(0);
- bfin_write_WDOGA_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline void restore_corea_nmi(void)
-{
- bfin_write_WDOGA_CTL(WDEN_DISABLE);
- bfin_write_WDOGA_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-
- bfin_write_WDOGA_CNT(wdoga_cnt);
- bfin_write_WDOGA_CTL(wdoga_ctl);
-}
-
-static inline void save_corelock(void)
-{
- saved_corelock = corelock;
- corelock.lock = 0;
-}
-
-static inline void restore_corelock(void)
-{
- corelock = saved_corelock;
-}
-
-
-static inline void nmi_wdt_keepalive(void)
-{
- bfin_write_WDOGB_STAT(0);
-}
-
-static inline void nmi_wdt_stop(void)
-{
- bfin_write_WDOGB_CTL(WDEN_DISABLE);
-}
-
-/* before calling this function, you must stop the WDT */
-static inline void nmi_wdt_clear(void)
-{
- /* clear TRO bit, disable event generation */
- bfin_write_WDOGB_CTL(WDOG_EXPIRED | WDEN_DISABLE | ICTL_NONE);
-}
-
-static inline void nmi_wdt_start(void)
-{
- bfin_write_WDOGB_CTL(WDEN_ENABLE | ICTL_NMI);
-}
-
-static inline int nmi_wdt_running(void)
-{
- return ((bfin_read_WDOGB_CTL() & WDEN_MASK) != WDEN_DISABLE);
-}
-
-static inline int nmi_wdt_set_timeout(unsigned long t)
-{
- u32 cnt, max_t, sclk;
- int run;
-
- sclk = get_sclk();
- max_t = -1 / sclk;
- cnt = t * sclk;
- if (t > max_t) {
- pr_warning("NMI: timeout value is too large\n");
- return -EINVAL;
- }
-
- run = nmi_wdt_running();
- nmi_wdt_stop();
- bfin_write_WDOGB_CNT(cnt);
- if (run)
- nmi_wdt_start();
-
- timeout = t;
-
- return 0;
-}
-
-int check_nmi_wdt_touched(void)
-{
- unsigned int this_cpu = smp_processor_id();
- unsigned int cpu;
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- if (!atomic_read(&nmi_touched[this_cpu]))
- return 0;
-
- atomic_set(&nmi_touched[this_cpu], 0);
-
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask) {
- invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
- (unsigned long)(&nmi_touched[cpu]));
- if (!atomic_read(&nmi_touched[cpu]))
- return 0;
- atomic_set(&nmi_touched[cpu], 0);
- }
-
- return 1;
-}
-
-static void nmi_wdt_timer(struct timer_list *unused)
-{
- if (check_nmi_wdt_touched())
- nmi_wdt_keepalive();
-
- mod_timer(&ntimer, jiffies + NMI_CHECK_TIMEOUT);
-}
-
-static int __init init_nmi_wdt(void)
-{
- nmi_wdt_set_timeout(timeout);
- nmi_wdt_start();
- nmi_active = true;
-
- timer_setup(&ntimer, nmi_wdt_timer, 0);
- ntimer.expires = jiffies + NMI_CHECK_TIMEOUT;
- add_timer(&ntimer);
-
- pr_info("nmi_wdt: initialized: timeout=%d sec\n", timeout);
- return 0;
-}
-device_initcall(init_nmi_wdt);
-
-void arch_touch_nmi_watchdog(void)
-{
- atomic_set(&nmi_touched[smp_processor_id()], 1);
-}
-
-/* Suspend/resume support */
-#ifdef CONFIG_PM
-static int nmi_wdt_suspend(void)
-{
- nmi_wdt_stop();
- return 0;
-}
-
-static void nmi_wdt_resume(void)
-{
- if (nmi_active)
- nmi_wdt_start();
-}
-
-static struct syscore_ops nmi_syscore_ops = {
- .resume = nmi_wdt_resume,
- .suspend = nmi_wdt_suspend,
-};
-
-static int __init init_nmi_wdt_syscore(void)
-{
- if (nmi_active)
- register_syscore_ops(&nmi_syscore_ops);
-
- return 0;
-}
-late_initcall(init_nmi_wdt_syscore);
-
-#endif /* CONFIG_PM */
-
-
-asmlinkage notrace void do_nmi(struct pt_regs *fp)
-{
- unsigned int cpu = smp_processor_id();
- nmi_enter();
-
- cpu_pda[cpu].__nmi_count += 1;
-
- if (cpu == nmi_wdt_cpu) {
- /* CoreB goes here first */
-
- /* reload the WDOG_STAT */
- nmi_wdt_keepalive();
-
- /* clear nmi interrupt for CoreB */
- nmi_wdt_stop();
- nmi_wdt_clear();
-
- /* trigger NMI interrupt of CoreA */
- send_corea_nmi();
-
- /* waiting CoreB to enter NMI */
- wait_nmi_event(COREA_ENTER_NMI);
-
- /* recover WDOGA's settings */
- restore_corea_nmi();
-
- save_corelock();
-
- /* corelock is save/cleared, CoreA is dummping messages */
-
- wait_nmi_event(COREA_EXIT_NMI);
- } else {
- /* OK, CoreA entered NMI */
- set_nmi_event(COREA_ENTER_NMI);
- }
-
- pr_emerg("\nNMI Watchdog detected LOCKUP, dump for CPU %d\n", cpu);
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- show_stack(current, (unsigned long *)fp);
-
- if (cpu == nmi_wdt_cpu) {
- pr_emerg("This fault is not recoverable, sorry!\n");
-
- /* CoreA dump finished, restore the corelock */
- restore_corelock();
-
- set_nmi_event(COREB_EXIT_NMI);
- } else {
- /* CoreB dump finished, notice the CoreA we are done */
- set_nmi_event(COREA_EXIT_NMI);
-
- /* synchronize with CoreA */
- wait_nmi_event(COREB_EXIT_NMI);
- }
-
- nmi_exit();
-}
diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c
deleted file mode 100644
index 6a9524ad04a5..000000000000
--- a/arch/blackfin/kernel/perf_event.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Blackfin performance counters
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Ripped from SuperH version:
- *
- * Copyright (C) 2009 Paul Mundt
- *
- * Heavily based on the x86 and PowerPC implementations.
- *
- * x86:
- * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
- * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
- * Copyright (C) 2009 Jaswinder Singh Rajput
- * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
- * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
- * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
- *
- * ppc:
- * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/perf_event.h>
-#include <asm/bfin_pfmon.h>
-
-/*
- * We have two counters, and each counter can support an event type.
- * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
- *
- * 0x04 o pc invariant branches
- * 0x06 o mispredicted branches
- * 0x09 o predicted branches taken
- * 0x0B o EXCPT insn
- * 0x0C o CSYNC/SSYNC insn
- * 0x0D o Insns committed
- * 0x0E o Interrupts taken
- * 0x0F o Misaligned address exceptions
- * 0x80 o Code memory fetches stalled due to DMA
- * 0x83 o 64bit insn fetches delivered
- * 0x9A o data cache fills (bank a)
- * 0x9B o data cache fills (bank b)
- * 0x9C o data cache lines evicted (bank a)
- * 0x9D o data cache lines evicted (bank b)
- * 0x9E o data cache high priority fills
- * 0x9F o data cache low priority fills
- * 0x00 s loop 0 iterations
- * 0x01 s loop 1 iterations
- * 0x0A s CSYNC/SSYNC stalls
- * 0x10 s DAG read/after write hazards
- * 0x13 s RAW data hazards
- * 0x81 s code TAG stalls
- * 0x82 s code fill stalls
- * 0x90 s processor to memory stalls
- * 0x91 s data memory stalls not hidden by 0x90
- * 0x92 s data store buffer full stalls
- * 0x93 s data memory write buffer full stalls due to high->low priority
- * 0x95 s data memory fill buffer stalls
- * 0x96 s data TAG collision stalls
- * 0x97 s data collision stalls
- * 0x98 s data stalls
- * 0x99 s data stalls sent to processor
- */
-
-static const int event_map[] = {
- /* use CYCLES cpu register */
- [PERF_COUNT_HW_CPU_CYCLES] = -1,
- [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
- [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
- [PERF_COUNT_HW_CACHE_MISSES] = 0x83,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
- [PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
- [PERF_COUNT_HW_BUS_CYCLES] = -1,
-};
-
-#define C(x) PERF_COUNT_HW_CACHE_##x
-
-static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [C(L1D)] = { /* Data bank A */
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x9A,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0x83,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = 0,
- [C(RESULT_MISS) ] = 0,
- },
- },
-
- [C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(DTLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-
- [C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = -1,
- [C(RESULT_MISS) ] = -1,
- },
- },
-};
-
-const char *perf_pmu_name(void)
-{
- return "bfin";
-}
-EXPORT_SYMBOL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
- return ARRAY_SIZE(event_map);
-}
-EXPORT_SYMBOL(perf_num_counters);
-
-static u64 bfin_pfmon_read(int idx)
-{
- return bfin_read32(PFCNTR0 + (idx * 4));
-}
-
-static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
-}
-
-static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
-{
- u32 val, mask;
-
- val = PFPWR;
- if (idx) {
- mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
- /* The packed config is for event0, so shift it to event1 slots */
- val |= (hwc->config << (PFMON1_P - PFMON0_P));
- val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
- bfin_write_PFCNTR1(0);
- } else {
- mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
- val |= hwc->config;
- bfin_write_PFCNTR0(0);
- }
-
- bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
-}
-
-static void bfin_pfmon_disable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
-}
-
-static void bfin_pfmon_enable_all(void)
-{
- bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
-}
-
-struct cpu_hw_events {
- struct perf_event *events[MAX_HWEVENTS];
- unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
-};
-DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-static int hw_perf_cache_event(int config, int *evp)
-{
- unsigned long type, op, result;
- int ev;
-
- /* unpack config */
- type = config & 0xff;
- op = (config >> 8) & 0xff;
- result = (config >> 16) & 0xff;
-
- if (type >= PERF_COUNT_HW_CACHE_MAX ||
- op >= PERF_COUNT_HW_CACHE_OP_MAX ||
- result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
- return -EINVAL;
-
- ev = cache_events[type][op][result];
- if (ev == 0)
- return -EOPNOTSUPP;
- if (ev == -1)
- return -EINVAL;
- *evp = ev;
- return 0;
-}
-
-static void bfin_perf_event_update(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- u64 prev_raw_count, new_raw_count;
- s64 delta;
- int shift = 0;
-
- /*
- * Depending on the counter configuration, they may or may not
- * be chained, in which case the previous counter value can be
- * updated underneath us if the lower-half overflows.
- *
- * Our tactic to handle this is to first atomically read and
- * exchange a new raw count - then add that new-prev delta
- * count to the generic counter atomically.
- *
- * As there is no interrupt associated with the overflow events,
- * this is the simplest approach for maintaining consistency.
- */
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = bfin_pfmon_read(idx);
-
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count)
- goto again;
-
- /*
- * Now we have the new raw value and have updated the prev
- * timestamp already. We can now calculate the elapsed delta
- * (counter-)time and add that to the generic counter.
- *
- * Careful, not all hw sign-extends above the physical width
- * of the count.
- */
- delta = (new_raw_count << shift) - (prev_raw_count << shift);
- delta >>= shift;
-
- local64_add(delta, &event->count);
-}
-
-static void bfin_pmu_stop(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (!(event->hw.state & PERF_HES_STOPPED)) {
- bfin_pfmon_disable(hwc, idx);
- cpuc->events[idx] = NULL;
- event->hw.state |= PERF_HES_STOPPED;
- }
-
- if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
- bfin_perf_event_update(event, &event->hw, idx);
- event->hw.state |= PERF_HES_UPTODATE;
- }
-}
-
-static void bfin_pmu_start(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (WARN_ON_ONCE(idx == -1))
- return;
-
- if (flags & PERF_EF_RELOAD)
- WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
-
- cpuc->events[idx] = event;
- event->hw.state = 0;
- bfin_pfmon_enable(hwc, idx);
-}
-
-static void bfin_pmu_del(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
-
- bfin_pmu_stop(event, PERF_EF_UPDATE);
- __clear_bit(event->hw.idx, cpuc->used_mask);
-
- perf_event_update_userpage(event);
-}
-
-static int bfin_pmu_add(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- int ret = -EAGAIN;
-
- perf_pmu_disable(event->pmu);
-
- if (__test_and_set_bit(idx, cpuc->used_mask)) {
- idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
- if (idx == MAX_HWEVENTS)
- goto out;
-
- __set_bit(idx, cpuc->used_mask);
- hwc->idx = idx;
- }
-
- bfin_pfmon_disable(hwc, idx);
-
- event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
- if (flags & PERF_EF_START)
- bfin_pmu_start(event, PERF_EF_RELOAD);
-
- perf_event_update_userpage(event);
- ret = 0;
-out:
- perf_pmu_enable(event->pmu);
- return ret;
-}
-
-static void bfin_pmu_read(struct perf_event *event)
-{
- bfin_perf_event_update(event, &event->hw, event->hw.idx);
-}
-
-static int bfin_pmu_event_init(struct perf_event *event)
-{
- struct perf_event_attr *attr = &event->attr;
- struct hw_perf_event *hwc = &event->hw;
- int config = -1;
- int ret;
-
- if (attr->exclude_hv || attr->exclude_idle)
- return -EPERM;
-
- ret = 0;
- switch (attr->type) {
- case PERF_TYPE_RAW:
- config = PFMON(0, attr->config & PFMON_MASK) |
- PFCNT(0, !(attr->config & 0x100));
- break;
- case PERF_TYPE_HW_CACHE:
- ret = hw_perf_cache_event(attr->config, &config);
- break;
- case PERF_TYPE_HARDWARE:
- if (attr->config >= ARRAY_SIZE(event_map))
- return -EINVAL;
-
- config = event_map[attr->config];
- break;
- }
-
- if (config == -1)
- return -EINVAL;
-
- if (!attr->exclude_kernel)
- config |= PFCEN(0, PFCEN_ENABLE_SUPV);
- if (!attr->exclude_user)
- config |= PFCEN(0, PFCEN_ENABLE_USER);
-
- hwc->config |= config;
-
- return ret;
-}
-
-static void bfin_pmu_enable(struct pmu *pmu)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct perf_event *event;
- struct hw_perf_event *hwc;
- int i;
-
- for (i = 0; i < MAX_HWEVENTS; ++i) {
- event = cpuc->events[i];
- if (!event)
- continue;
- hwc = &event->hw;
- bfin_pfmon_enable(hwc, hwc->idx);
- }
-
- bfin_pfmon_enable_all();
-}
-
-static void bfin_pmu_disable(struct pmu *pmu)
-{
- bfin_pfmon_disable_all();
-}
-
-static struct pmu pmu = {
- .pmu_enable = bfin_pmu_enable,
- .pmu_disable = bfin_pmu_disable,
- .event_init = bfin_pmu_event_init,
- .add = bfin_pmu_add,
- .del = bfin_pmu_del,
- .start = bfin_pmu_start,
- .stop = bfin_pmu_stop,
- .read = bfin_pmu_read,
-};
-
-static int bfin_pmu_prepare_cpu(unsigned int cpu)
-{
- struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
-
- bfin_write_PFCTL(0);
- memset(cpuhw, 0, sizeof(struct cpu_hw_events));
- return 0;
-}
-
-static int __init bfin_pmu_init(void)
-{
- int ret;
-
- /*
- * All of the on-chip counters are "limited", in that they have
- * no interrupts, and are therefore unable to do sampling without
- * further work and timer assistance.
- */
- pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
-
- ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
- if (!ret)
- cpuhp_setup_state(CPUHP_PERF_BFIN,"perf/bfin:starting",
- bfin_pmu_prepare_cpu, NULL);
- return ret;
-}
-early_initcall(bfin_pmu_init);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
deleted file mode 100644
index 89814850b08b..000000000000
--- a/arch/blackfin/kernel/process.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * Blackfin architecture-dependent process handling
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/module.h>
-#include <linux/unistd.h>
-#include <linux/user.h>
-#include <linux/uaccess.h>
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm_types.h>
-#include <linux/tick.h>
-#include <linux/fs.h>
-#include <linux/err.h>
-
-#include <asm/blackfin.h>
-#include <asm/fixed_code.h>
-#include <asm/mem_map.h>
-#include <asm/irq.h>
-
-asmlinkage void ret_from_fork(void);
-
-/* Points to the SDRAM backup memory for the stack that is currently in
- * L1 scratchpad memory.
- */
-void *current_l1_stack_save;
-
-/* The number of tasks currently using a L1 stack area. The SRAM is
- * allocated/deallocated whenever this changes from/to zero.
- */
-int nr_l1stack_tasks;
-
-/* Start and length of the area in L1 scratchpad memory which we've allocated
- * for process stacks.
- */
-void *l1_stack_base;
-unsigned long l1_stack_len;
-
-void (*pm_power_off)(void) = NULL;
-EXPORT_SYMBOL(pm_power_off);
-
-/*
- * The idle loop on BFIN
- */
-#ifdef CONFIG_IDLE_L1
-void arch_cpu_idle(void)__attribute__((l1_text));
-#endif
-
-/*
- * This is our default idle handler. We need to disable
- * interrupts here to ensure we don't miss a wakeup call.
- */
-void arch_cpu_idle(void)
-{
-#ifdef CONFIG_IPIPE
- ipipe_suspend_domain();
-#endif
- hard_local_irq_disable();
- if (!need_resched())
- idle_with_irq_disabled();
-
- hard_local_irq_enable();
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-void arch_cpu_idle_dead(void)
-{
- cpu_die();
-}
-#endif
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
-{
- regs->pc = new_ip;
- if (current->mm)
- regs->p5 = current->mm->start_data;
-#ifndef CONFIG_SMP
- task_thread_info(current)->l1_task_info.stack_start =
- (void *)current->mm->context.stack_start;
- task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
- memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
- sizeof(*L1_SCRATCH_TASK_INFO));
-#endif
- wrusp(new_sp);
-}
-EXPORT_SYMBOL_GPL(start_thread);
-
-void flush_thread(void)
-{
-}
-
-asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
-{
-#ifdef __ARCH_SYNC_CORE_DCACHE
- if (current->nr_cpus_allowed == num_possible_cpus())
- set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
-#endif
- if (newsp)
- newsp -= 12;
- return do_fork(clone_flags, newsp, 0, NULL, NULL);
-}
-
-int
-copy_thread(unsigned long clone_flags,
- unsigned long usp, unsigned long topstk,
- struct task_struct *p)
-{
- struct pt_regs *childregs;
- unsigned long *v;
-
- childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
- v = ((unsigned long *)childregs) - 2;
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(childregs, 0, sizeof(struct pt_regs));
- v[0] = usp;
- v[1] = topstk;
- childregs->orig_p0 = -1;
- childregs->ipend = 0x8000;
- __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
- p->thread.usp = 0;
- } else {
- *childregs = *current_pt_regs();
- childregs->r0 = 0;
- p->thread.usp = usp ? : rdusp();
- v[0] = v[1] = 0;
- }
-
- p->thread.ksp = (unsigned long)v;
- p->thread.pc = (unsigned long)ret_from_fork;
-
- return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
- unsigned long fp, pc;
- unsigned long stack_page;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
-
- stack_page = (unsigned long)p;
- fp = p->thread.usp;
- do {
- if (fp < stack_page + sizeof(struct thread_info) ||
- fp >= 8184 + stack_page)
- return 0;
- pc = ((unsigned long *)fp)[1];
- if (!in_sched_functions(pc))
- return pc;
- fp = *(unsigned long *)fp;
- }
- while (count++ < 16);
- return 0;
-}
-
-void finish_atomic_sections (struct pt_regs *regs)
-{
- int __user *up0 = (int __user *)regs->p0;
-
- switch (regs->pc) {
- default:
- /* not in middle of an atomic step, so resume like normal */
- return;
-
- case ATOMIC_XCHG32 + 2:
- put_user(regs->r1, up0);
- break;
-
- case ATOMIC_CAS32 + 2:
- case ATOMIC_CAS32 + 4:
- if (regs->r0 == regs->r1)
- case ATOMIC_CAS32 + 6:
- put_user(regs->r2, up0);
- break;
-
- case ATOMIC_ADD32 + 2:
- regs->r0 = regs->r1 + regs->r0;
- /* fall through */
- case ATOMIC_ADD32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_SUB32 + 2:
- regs->r0 = regs->r1 - regs->r0;
- /* fall through */
- case ATOMIC_SUB32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_IOR32 + 2:
- regs->r0 = regs->r1 | regs->r0;
- /* fall through */
- case ATOMIC_IOR32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_AND32 + 2:
- regs->r0 = regs->r1 & regs->r0;
- /* fall through */
- case ATOMIC_AND32 + 4:
- put_user(regs->r0, up0);
- break;
-
- case ATOMIC_XOR32 + 2:
- regs->r0 = regs->r1 ^ regs->r0;
- /* fall through */
- case ATOMIC_XOR32 + 4:
- put_user(regs->r0, up0);
- break;
- }
-
- /*
- * We've finished the atomic section, and the only thing left for
- * userspace is to do a RTS, so we might as well handle that too
- * since we need to update the PC anyways.
- */
- regs->pc = regs->rets;
-}
-
-static inline
-int in_mem(unsigned long addr, unsigned long size,
- unsigned long start, unsigned long end)
-{
- return addr >= start && addr + size <= end;
-}
-static inline
-int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
- unsigned long const_addr, unsigned long const_size)
-{
- return const_size &&
- in_mem(addr, size, const_addr + off, const_addr + const_size);
-}
-static inline
-int in_mem_const(unsigned long addr, unsigned long size,
- unsigned long const_addr, unsigned long const_size)
-{
- return in_mem_const_off(addr, size, 0, const_addr, const_size);
-}
-#ifdef CONFIG_BF60x
-#define ASYNC_ENABLED(bnum, bctlnum) 1
-#else
-#define ASYNC_ENABLED(bnum, bctlnum) \
-({ \
- (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
- bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
- 1; \
-})
-#endif
-/*
- * We can't read EBIU banks that aren't enabled or we end up hanging
- * on the access to the async space. Make sure we validate accesses
- * that cross async banks too.
- * 0 - found, but unusable
- * 1 - found & usable
- * 2 - not found
- */
-static
-int in_async(unsigned long addr, unsigned long size)
-{
- if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
- if (!ASYNC_ENABLED(0, 0))
- return 0;
- if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
- return 1;
- size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
- addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
- }
- if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
- if (!ASYNC_ENABLED(1, 0))
- return 0;
- if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
- return 1;
- size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
- addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
- }
- if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
- if (!ASYNC_ENABLED(2, 1))
- return 0;
- if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
- return 1;
- size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
- addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
- }
- if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
- if (ASYNC_ENABLED(3, 1))
- return 0;
- if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
- return 1;
- return 0;
- }
-
- /* not within async bounds */
- return 2;
-}
-
-int bfin_mem_access_type(unsigned long addr, unsigned long size)
-{
- int cpu = raw_smp_processor_id();
-
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return -EFAULT;
-
- if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
- return BFIN_MEM_ACCESS_CORE;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
-#endif
- if (in_mem_const(addr, size, L2_START, L2_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
-
- if (addr >= SYSMMR_BASE)
- return BFIN_MEM_ACCESS_CORE_ONLY;
-
- switch (in_async(addr, size)) {
- case 0: return -EFAULT;
- case 1: return BFIN_MEM_ACCESS_CORE;
- case 2: /* fall through */;
- }
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return BFIN_MEM_ACCESS_CORE;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return BFIN_MEM_ACCESS_DMA;
-
- return -EFAULT;
-}
-
-#if defined(CONFIG_ACCESS_CHECK)
-#ifdef CONFIG_ACCESS_OK_L1
-__attribute__((l1_text))
-#endif
-/* Return 1 if access to memory range is OK, 0 otherwise */
-int _access_ok(unsigned long addr, unsigned long size)
-{
- int aret;
-
- if (size == 0)
- return 1;
- /* Check that things do not wrap around */
- if (addr > ULONG_MAX - size)
- return 0;
- if (uaccess_kernel())
- return 1;
-#ifdef CONFIG_MTD_UCLINUX
- if (1)
-#else
- if (0)
-#endif
- {
- if (in_mem(addr, size, memory_start, memory_end))
- return 1;
- if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
- return 1;
-# ifndef CONFIG_ROMFS_ON_MTD
- if (0)
-# endif
- /* For XIP, allow user space to use pointers within the ROMFS. */
- if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
- return 1;
- } else {
- if (in_mem(addr, size, memory_start, physical_mem_end))
- return 1;
- }
-
- if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
- return 1;
-
- if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
- return 1;
-#ifdef COREB_L1_CODE_START
- if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
- return 1;
- if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
- return 1;
-#endif
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
- if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
- return 1;
-#endif
-
- aret = in_async(addr, size);
- if (aret < 2)
- return aret;
-
- if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
- return 1;
-
- if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
- return 1;
- if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
- return 1;
-
- return 0;
-}
-EXPORT_SYMBOL(_access_ok);
-#endif /* CONFIG_ACCESS_CHECK */
diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c
deleted file mode 100644
index db85bc94334e..000000000000
--- a/arch/blackfin/kernel/pseudodbg.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* The fake debug assert instructions
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-
-const char * const greg_names[] = {
- "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
- "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP",
- "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3",
- "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
- "A0.X", "A0.W", "A1.X", "A1.W", "<res>", "<res>", "ASTAT", "RETS",
- "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>",
- "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2",
- "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT",
-};
-
-static const char *get_allreg_name(int grp, int reg)
-{
- return greg_names[(grp << 3) | reg];
-}
-
-/*
- * Unfortunately, the pt_regs structure is not laid out the same way as the
- * hardware register file, so we need to do some fix ups.
- *
- * CYCLES is not stored in the pt_regs structure - so, we just read it from
- * the hardware.
- *
- * Don't support:
- * - All reserved registers
- * - All in group 7 are (supervisors only)
- */
-
-static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
-{
- long *val = &fp->r0;
- unsigned long tmp;
-
- /* Only do Dregs and Pregs for now */
- if (grp == 5 ||
- (grp == 4 && (reg == 4 || reg == 5)) ||
- (grp == 7))
- return false;
-
- if (grp == 0 || (grp == 1 && reg < 6))
- val -= (reg + 8 * grp);
- else if (grp == 1 && reg == 6)
- val = &fp->usp;
- else if (grp == 1 && reg == 7)
- val = &fp->fp;
- else if (grp == 2) {
- val = &fp->i0;
- val -= reg;
- } else if (grp == 3 && reg >= 4) {
- val = &fp->l0;
- val -= (reg - 4);
- } else if (grp == 3 && reg < 4) {
- val = &fp->b0;
- val -= reg;
- } else if (grp == 4 && reg < 4) {
- val = &fp->a0x;
- val -= reg;
- } else if (grp == 4 && reg == 6)
- val = &fp->astat;
- else if (grp == 4 && reg == 7)
- val = &fp->rets;
- else if (grp == 6 && reg < 6) {
- val = &fp->lc0;
- val -= reg;
- } else if (grp == 6 && reg == 6) {
- __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp));
- val = &tmp;
- } else if (grp == 6 && reg == 7) {
- __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp));
- val = &tmp;
- }
-
- *value = *val;
- return true;
-
-}
-
-#define PseudoDbg_Assert_opcode 0xf0000000
-#define PseudoDbg_Assert_expected_bits 0
-#define PseudoDbg_Assert_expected_mask 0xffff
-#define PseudoDbg_Assert_regtest_bits 16
-#define PseudoDbg_Assert_regtest_mask 0x7
-#define PseudoDbg_Assert_grp_bits 19
-#define PseudoDbg_Assert_grp_mask 0x7
-#define PseudoDbg_Assert_dbgop_bits 22
-#define PseudoDbg_Assert_dbgop_mask 0x3
-#define PseudoDbg_Assert_dontcare_bits 24
-#define PseudoDbg_Assert_dontcare_mask 0x7
-#define PseudoDbg_Assert_code_bits 27
-#define PseudoDbg_Assert_code_mask 0x1f
-
-/*
- * DBGA - debug assert
- */
-bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
-{
- int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
- int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
- int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
- int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
- long value;
-
- if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
- return false;
-
- if (!fix_up_reg(fp, &value, grp, regtest))
- return false;
-
- if (dbgop == 0 || dbgop == 2) {
- /* DBGA ( regs_lo , uimm16 ) */
- /* DBGAL ( regs , uimm16 ) */
- if (expected != (value & 0xFFFF)) {
- pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)(value & 0xFFFF));
- return false;
- }
-
- } else if (dbgop == 1 || dbgop == 3) {
- /* DBGA ( regs_hi , uimm16 ) */
- /* DBGAH ( regs , uimm16 ) */
- if (expected != ((value >> 16) & 0xFFFF)) {
- pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n",
- get_allreg_name(grp, regtest),
- expected, (unsigned int)((value >> 16) & 0xFFFF));
- return false;
- }
- }
-
- fp->pc += 4;
- return true;
-}
-
-#define PseudoDbg_opcode 0xf8000000
-#define PseudoDbg_reg_bits 0
-#define PseudoDbg_reg_mask 0x7
-#define PseudoDbg_grp_bits 3
-#define PseudoDbg_grp_mask 0x7
-#define PseudoDbg_fn_bits 6
-#define PseudoDbg_fn_mask 0x3
-#define PseudoDbg_code_bits 8
-#define PseudoDbg_code_mask 0xff
-
-/*
- * DBG - debug (dump a register value out)
- */
-bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
-{
- int grp, fn, reg;
- long value, value1;
-
- if ((opcode & 0xFF000000) != PseudoDbg_opcode)
- return false;
-
- opcode >>= 16;
- grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
- fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
- reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
-
- if (fn == 3 && (reg == 0 || reg == 1)) {
- if (!fix_up_reg(fp, &value, 4, 2 * reg))
- return false;
- if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1))
- return false;
-
- pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1);
- fp->pc += 2;
- return true;
-
- } else if (fn == 0) {
- if (!fix_up_reg(fp, &value, grp, reg))
- return false;
-
- pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value);
- fp->pc += 2;
- return true;
- }
-
- return false;
-}
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
deleted file mode 100644
index a6827095b99a..000000000000
--- a/arch/blackfin/kernel/ptrace.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
- * these modifications are Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/elf.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/regset.h>
-#include <linux/signal.h>
-#include <linux/tracehook.h>
-#include <linux/uaccess.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/asm-offsets.h>
-#include <asm/dma.h>
-#include <asm/fixed_code.h>
-#include <asm/cacheflush.h>
-#include <asm/mem_map.h>
-#include <asm/mmu_context.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long
-get_reg(struct task_struct *task, unsigned long regno,
- unsigned long __user *datap)
-{
- long tmp;
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_TEXT_ADDR:
- tmp = task->mm->start_code;
- break;
- case PT_TEXT_END_ADDR:
- tmp = task->mm->end_code;
- break;
- case PT_DATA_ADDR:
- tmp = task->mm->start_data;
- break;
- case PT_USP:
- tmp = task->thread.usp;
- break;
- default:
- if (regno < sizeof(*regs)) {
- void *reg_ptr = regs;
- tmp = *(long *)(reg_ptr + regno);
- } else
- return -EIO;
- }
-
- return put_user(tmp, datap);
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int
-put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
-{
- struct pt_regs *regs = task_pt_regs(task);
-
- if (regno & 3 || regno > PT_LAST_PSEUDO)
- return -EIO;
-
- switch (regno) {
- case PT_PC:
- /*********************************************************************/
- /* At this point the kernel is most likely in exception. */
- /* The RETX register will be used to populate the pc of the process. */
- /*********************************************************************/
- regs->retx = data;
- regs->pc = data;
- break;
- case PT_RETX:
- break; /* regs->retx = data; break; */
- case PT_USP:
- regs->usp = data;
- task->thread.usp = data;
- break;
- case PT_SYSCFG: /* don't let userspace screw with this */
- if ((data & ~1) != 0x6)
- pr_warning("ptrace: ignore syscfg write of %#lx\n", data);
- break; /* regs->syscfg = data; break; */
- default:
- if (regno < sizeof(*regs)) {
- void *reg_offset = regs;
- *(long *)(reg_offset + regno) = data;
- }
- /* Ignore writes to pseudo registers */
- }
-
- return 0;
-}
-
-/*
- * check that an address falls within the bounds of the target process's memory mappings
- */
-int
-is_user_addr_valid(struct task_struct *child, unsigned long start, unsigned long len)
-{
- bool valid;
- struct vm_area_struct *vma;
- struct sram_list_struct *sraml;
-
- /* overflow */
- if (start + len < start)
- return -EIO;
-
- down_read(&child->mm->mmap_sem);
- vma = find_vma(child->mm, start);
- valid = vma && start >= vma->vm_start && start + len <= vma->vm_end;
- up_read(&child->mm->mmap_sem);
- if (valid)
- return 0;
-
- for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next)
- if (start >= (unsigned long)sraml->addr
- && start + len < (unsigned long)sraml->addr + sraml->length)
- return 0;
-
- if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
- return 0;
-
-#ifdef CONFIG_APP_STACK_L1
- if (child->mm->context.l1_stack_save)
- if (start >= (unsigned long)l1_stack_base &&
- start + len < (unsigned long)l1_stack_base + l1_stack_len)
- return 0;
-#endif
-
- return -EIO;
-}
-
-/*
- * retrieve the contents of Blackfin userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* This sucks ... */
- regs->usp = target->thread.usp;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs, 0, sizeof(*regs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*regs), -1);
-}
-
-/*
- * update the contents of the Blackfin userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* Don't let people set SYSCFG (it's at the end of pt_regs) */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs, 0, PT_SYSCFG);
- if (ret < 0)
- return ret;
-
- /* This sucks ... */
- target->thread.usp = regs->usp;
- /* regs->retx = regs->pc; */
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- PT_SYSCFG, -1);
-}
-
-/*
- * Define the register sets available on the Blackfin under Linux
- */
-enum bfin_regset {
- REGSET_GENERAL,
-};
-
-static const struct user_regset bfin_regsets[] = {
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = sizeof(struct pt_regs) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
-};
-
-static const struct user_regset_view user_bfin_native_view = {
- .name = "Blackfin",
- .e_machine = EM_BLACKFIN,
- .regsets = bfin_regsets,
- .n = ARRAY_SIZE(bfin_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_bfin_native_view;
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg |= SYSCFG_SSSTEP;
-
- set_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- struct pt_regs *regs = task_pt_regs(child);
- regs->syscfg &= ~SYSCFG_SSSTEP;
-
- clear_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned long __user *datap = (unsigned long __user *)data;
- void *paddr = (void *)addr;
-
- switch (request) {
- /* when I and D space are separate, these will need to be fixed. */
- case PTRACE_PEEKDATA:
- pr_debug("ptrace: PEEKDATA\n");
- /* fall through */
- case PTRACE_PEEKTEXT: /* read word at location addr. */
- {
- unsigned long tmp = 0;
- int copied = 0, to_copy = sizeof(tmp);
-
- ret = -EIO;
- pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %i\n", addr, to_copy);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &tmp,
- to_copy, FOLL_FORCE);
- if (copied)
- break;
-
- /* hrm, why didn't that work ... maybe no mapping */
- if (addr >= FIXED_CODE_START &&
- addr + to_copy <= FIXED_CODE_END) {
- copy_from_user_page(0, 0, 0, &tmp, paddr, to_copy);
- copied = to_copy;
- } else if (addr >= BOOT_ROM_START) {
- memcpy(&tmp, paddr, to_copy);
- copied = to_copy;
- }
-
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(&tmp, paddr, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp);
- if (copied == to_copy)
- ret = put_user(tmp, datap);
- break;
- }
-
- /* when I and D space are separate, this will have to be fixed. */
- case PTRACE_POKEDATA:
- pr_debug("ptrace: PTRACE_PEEKDATA\n");
- /* fall through */
- case PTRACE_POKETEXT: /* write the word at location addr. */
- {
- int copied = 0, to_copy = sizeof(data);
-
- ret = -EIO;
- pr_debug("ptrace: POKETEXT at addr 0x%08lx + %i bytes %lx\n",
- addr, to_copy, data);
- if (is_user_addr_valid(child, addr, to_copy) < 0)
- break;
- pr_debug("ptrace: user address is valid\n");
-
- switch (bfin_mem_access_type(addr, to_copy)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- copied = ptrace_access_vm(child, addr, &data,
- to_copy,
- FOLL_FORCE | FOLL_WRITE);
- break;
- case BFIN_MEM_ACCESS_DMA:
- if (safe_dma_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(paddr, &data, to_copy))
- copied = to_copy;
- break;
- default:
- copied = 0;
- break;
- }
-
- pr_debug("ptrace: copied size %d\n", copied);
- if (copied == to_copy)
- ret = 0;
- break;
- }
-
- case PTRACE_PEEKUSR:
- switch (addr) {
-#ifdef CONFIG_BINFMT_ELF_FDPIC /* backwards compat */
- case PT_FDPIC_EXEC:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_EXEC;
- goto case_default;
- case PT_FDPIC_INTERP:
- request = PTRACE_GETFDPIC;
- addr = PTRACE_GETFDPIC_INTERP;
- goto case_default;
-#endif
- default:
- ret = get_reg(child, addr, datap);
- }
- pr_debug("ptrace: PEEKUSR reg %li with %#lx = %i\n", addr, data, ret);
- break;
-
- case PTRACE_POKEUSR:
- ret = put_reg(child, addr, data);
- pr_debug("ptrace: POKEUSR reg %li with %li = %i\n", addr, data, ret);
- break;
-
- case PTRACE_GETREGS:
- pr_debug("ptrace: PTRACE_GETREGS\n");
- return copy_regset_to_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case PTRACE_SETREGS:
- pr_debug("ptrace: PTRACE_SETREGS\n");
- return copy_regset_from_user(child, &user_bfin_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
-
- case_default:
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-asmlinkage int syscall_trace_enter(struct pt_regs *regs)
-{
- int ret = 0;
-
- if (test_thread_flag(TIF_SYSCALL_TRACE))
- ret = tracehook_report_syscall_entry(regs);
-
- return ret;
-}
-
-asmlinkage void syscall_trace_leave(struct pt_regs *regs)
-{
- int step;
-
- step = test_thread_flag(TIF_SINGLESTEP);
- if (step || test_thread_flag(TIF_SYSCALL_TRACE))
- tracehook_report_syscall_exit(regs, step);
-}
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
deleted file mode 100644
index c4f50a328501..000000000000
--- a/arch/blackfin/kernel/reboot.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <asm/bfin-global.h>
-#include <asm/reboot.h>
-#include <asm/bfrom.h>
-
-/* A system soft reset makes external memory unusable so force
- * this function into L1. We use the compiler ssync here rather
- * than SSYNC() because it's safe (no interrupts and such) and
- * we save some L1. We do not need to force sanity in the SYSCR
- * register as the BMODE selection bit is cleared by the soft
- * reset while the Core B bit (on dual core parts) is cleared by
- * the core reset.
- */
-__attribute__ ((__l1_text__, __noreturn__))
-static void bfin_reset(void)
-{
-#ifndef CONFIG_BF60x
- if (!ANOMALY_05000353 && !ANOMALY_05000386)
- bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
-
- /* Wait for completion of "system" events such as cache line
- * line fills so that we avoid infinite stalls later on as
- * much as possible. This code is in L1, so it won't trigger
- * any such event after this point in time.
- */
- __builtin_bfin_ssync();
-
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
-
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
-
- /* Clear System software reset */
- bfin_write_SWRST(0);
-
- /* The BF526 ROM will crash during reset */
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- /* Seems to be fixed with newer parts though ... */
- if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
- bfin_read_SWRST();
-#endif
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
-
- while (1)
- /* Issue core reset */
- asm("raise 1");
-#else
- while (1)
- bfin_write_RCU0_CTL(0x1);
-#endif
-}
-
-__attribute__((weak))
-void native_machine_restart(char *cmd)
-{
-}
-
-void machine_restart(char *cmd)
-{
- native_machine_restart(cmd);
- if (smp_processor_id())
- smp_call_function((void *)bfin_reset, 0, 1);
- else
- bfin_reset();
-}
-
-__attribute__((weak))
-void native_machine_halt(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_halt(void)
-{
- native_machine_halt();
-}
-
-__attribute__((weak))
-void native_machine_power_off(void)
-{
- idle_with_irq_disabled();
-}
-
-void machine_power_off(void)
-{
- native_machine_power_off();
-}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
deleted file mode 100644
index ad82468bd94d..000000000000
--- a/arch/blackfin/kernel/setup.c
+++ /dev/null
@@ -1,1468 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/delay.h>
-#include <linux/console.h>
-#include <linux/bootmem.h>
-#include <linux/seq_file.h>
-#include <linux/cpu.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/tty.h>
-#include <linux/pfn.h>
-
-#ifdef CONFIG_MTD_UCLINUX
-#include <linux/mtd/map.h>
-#include <linux/ext2_fs.h>
-#include <uapi/linux/cramfs_fs.h>
-#include <linux/romfs_fs.h>
-#endif
-
-#include <asm/cplb.h>
-#include <asm/cacheflush.h>
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-#include <asm/clocks.h>
-#include <asm/div64.h>
-#include <asm/cpu.h>
-#include <asm/fixed_code.h>
-#include <asm/early_printk.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-#ifdef CONFIG_BF60x
-#include <mach/pm.h>
-#endif
-#ifdef CONFIG_SCB_PRIORITY
-#include <asm/scb.h>
-#endif
-
-u16 _bfin_swrst;
-EXPORT_SYMBOL(_bfin_swrst);
-
-unsigned long memory_start, memory_end, physical_mem_end;
-unsigned long _rambase, _ramstart, _ramend;
-unsigned long reserved_mem_dcache_on;
-unsigned long reserved_mem_icache_on;
-EXPORT_SYMBOL(memory_start);
-EXPORT_SYMBOL(memory_end);
-EXPORT_SYMBOL(physical_mem_end);
-EXPORT_SYMBOL(_ramend);
-EXPORT_SYMBOL(reserved_mem_dcache_on);
-
-#ifdef CONFIG_MTD_UCLINUX
-extern struct map_info uclinux_ram_map;
-unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
-EXPORT_SYMBOL(memory_mtd_end);
-EXPORT_SYMBOL(memory_mtd_start);
-EXPORT_SYMBOL(mtd_size);
-#endif
-
-char __initdata command_line[COMMAND_LINE_SIZE];
-struct blackfin_initial_pda __initdata initial_pda;
-
-/* boot memmap, for parsing "memmap=" */
-#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
-#define BFIN_MEMMAP_RAM 1
-#define BFIN_MEMMAP_RESERVED 2
-static struct bfin_memmap {
- int nr_map;
- struct bfin_memmap_entry {
- unsigned long long addr; /* start of memory segment */
- unsigned long long size;
- unsigned long type;
- } map[BFIN_MEMMAP_MAX];
-} bfin_memmap __initdata;
-
-/* for memmap sanitization */
-struct change_member {
- struct bfin_memmap_entry *pentry; /* pointer to original entry */
- unsigned long long addr; /* address for this change point */
-};
-static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
-static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
-static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
-
-DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
-
-static int early_init_clkin_hz(char *buf);
-
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
-void __init generate_cplb_tables(void)
-{
- unsigned int cpu;
-
- generate_cplb_tables_all();
- /* Generate per-CPU I&D CPLB tables */
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- generate_cplb_tables_cpu(cpu);
-}
-#endif
-
-void bfin_setup_caches(unsigned int cpu)
-{
-#ifdef CONFIG_BFIN_ICACHE
- bfin_icache_init(icplb_tbl[cpu]);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- bfin_dcache_init(dcplb_tbl[cpu]);
-#endif
-
- bfin_setup_cpudata(cpu);
-
- /*
- * In cache coherence emulation mode, we need to have the
- * D-cache enabled before running any atomic operation which
- * might involve cache invalidation (i.e. spinlock, rwlock).
- * So printk's are deferred until then.
- */
-#ifdef CONFIG_BFIN_ICACHE
- printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# ifdef CONFIG_BFIN_L2_ICACHEABLE
- " cacheable"
-# else
- " uncacheable"
-# endif
- " in instruction cache\n");
-
-#else
- printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
- printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
- printk(KERN_INFO " External memory:"
-# if defined CONFIG_BFIN_EXTMEM_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
- if (L2_LENGTH)
- printk(KERN_INFO " L2 SRAM :"
-# if defined CONFIG_BFIN_L2_WRITEBACK
- " cacheable (write-back)"
-# elif defined CONFIG_BFIN_L2_WRITETHROUGH
- " cacheable (write-through)"
-# else
- " uncacheable"
-# endif
- " in data cache\n");
-#else
- printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
-#endif
-}
-
-void bfin_setup_cpudata(unsigned int cpu)
-{
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
-
- cpudata->imemctl = bfin_read_IMEM_CONTROL();
- cpudata->dmemctl = bfin_read_DMEM_CONTROL();
-}
-
-void __init bfin_cache_init(void)
-{
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
- generate_cplb_tables();
-#endif
- bfin_setup_caches(0);
-}
-
-void __init bfin_relocate_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
- unsigned long l2_len = (unsigned long)_l2_len;
-
- early_shadow_stamp();
-
- /*
- * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
- * we know that everything about l1 text/data is nice and aligned,
- * so copy by 4 byte chunks, and don't worry about overlapping
- * src/dest.
- *
- * We can't use the dma_memcpy functions, since they can call
- * scheduler functions which might be in L1 :( and core writes
- * into L1 instruction cause bad access errors, so we are stuck,
- * we are required to use DMA, but can't use the common dma
- * functions. We can't use memcpy either - since that might be
- * going to be in the relocated L1
- */
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
- blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
-#endif
-
- /* if necessary, copy L2 text/data to L2 SRAM */
- if (L2_LENGTH && l2_len)
- memcpy(_stext_l2, _l2_lma, l2_len);
-}
-
-#ifdef CONFIG_SMP
-void __init bfin_relocate_coreb_l1_mem(void)
-{
- unsigned long text_l1_len = (unsigned long)_text_l1_len;
- unsigned long data_l1_len = (unsigned long)_data_l1_len;
- unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
-
- blackfin_dma_early_init();
-
- /* if necessary, copy L1 text to L1 instruction SRAM */
- if (L1_CODE_LENGTH && text_l1_len)
- early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
- text_l1_len);
-
- /* if necessary, copy L1 data to L1 data bank A SRAM */
- if (L1_DATA_A_LENGTH && data_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
- data_l1_len);
-
- /* if necessary, copy L1 data B to L1 data bank B SRAM */
- if (L1_DATA_B_LENGTH && data_b_l1_len)
- early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
- data_b_l1_len);
-
- early_dma_memcpy_done();
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
- blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
- (unsigned long)_stext_l1 + COREB_L1_CODE_START;
-#endif
-}
-#endif
-
-#ifdef CONFIG_ROMKERNEL
-void __init bfin_relocate_xip_data(void)
-{
- early_shadow_stamp();
-
- memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
- memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
-}
-#endif
-
-/* add_memory_region to memmap */
-static void __init add_memory_region(unsigned long long start,
- unsigned long long size, int type)
-{
- int i;
-
- i = bfin_memmap.nr_map;
-
- if (i == BFIN_MEMMAP_MAX) {
- printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
- return;
- }
-
- bfin_memmap.map[i].addr = start;
- bfin_memmap.map[i].size = size;
- bfin_memmap.map[i].type = type;
- bfin_memmap.nr_map++;
-}
-
-/*
- * Sanitize the boot memmap, removing overlaps.
- */
-static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
-{
- struct change_member *change_tmp;
- unsigned long current_type, last_type;
- unsigned long long last_addr;
- int chgidx, still_changing;
- int overlap_entries;
- int new_entry;
- int old_nr, new_nr, chg_nr;
- int i;
-
- /*
- Visually we're performing the following (1,2,3,4 = memory types)
-
- Sample memory map (w/overlaps):
- ____22__________________
- ______________________4_
- ____1111________________
- _44_____________________
- 11111111________________
- ____________________33__
- ___________44___________
- __________33333_________
- ______________22________
- ___________________2222_
- _________111111111______
- _____________________11_
- _________________4______
-
- Sanitized equivalent (no overlap):
- 1_______________________
- _44_____________________
- ___1____________________
- ____22__________________
- ______11________________
- _________1______________
- __________3_____________
- ___________44___________
- _____________33_________
- _______________2________
- ________________1_______
- _________________4______
- ___________________2____
- ____________________33__
- ______________________4_
- */
- /* if there's only one memory region, don't bother */
- if (*pnr_map < 2)
- return -1;
-
- old_nr = *pnr_map;
-
- /* bail out if we find any unreasonable addresses in memmap */
- for (i = 0; i < old_nr; i++)
- if (map[i].addr + map[i].size < map[i].addr)
- return -1;
-
- /* create pointers for initial change-point information (for sorting) */
- for (i = 0; i < 2*old_nr; i++)
- change_point[i] = &change_point_list[i];
-
- /* record all known change-points (starting and ending addresses),
- omitting those that are for empty memory regions */
- chgidx = 0;
- for (i = 0; i < old_nr; i++) {
- if (map[i].size != 0) {
- change_point[chgidx]->addr = map[i].addr;
- change_point[chgidx++]->pentry = &map[i];
- change_point[chgidx]->addr = map[i].addr + map[i].size;
- change_point[chgidx++]->pentry = &map[i];
- }
- }
- chg_nr = chgidx; /* true number of change-points */
-
- /* sort change-point list by memory addresses (low -> high) */
- still_changing = 1;
- while (still_changing) {
- still_changing = 0;
- for (i = 1; i < chg_nr; i++) {
- /* if <current_addr> > <last_addr>, swap */
- /* or, if current=<start_addr> & last=<end_addr>, swap */
- if ((change_point[i]->addr < change_point[i-1]->addr) ||
- ((change_point[i]->addr == change_point[i-1]->addr) &&
- (change_point[i]->addr == change_point[i]->pentry->addr) &&
- (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
- ) {
- change_tmp = change_point[i];
- change_point[i] = change_point[i-1];
- change_point[i-1] = change_tmp;
- still_changing = 1;
- }
- }
- }
-
- /* create a new memmap, removing overlaps */
- overlap_entries = 0; /* number of entries in the overlap table */
- new_entry = 0; /* index for creating new memmap entries */
- last_type = 0; /* start with undefined memory type */
- last_addr = 0; /* start with 0 as last starting address */
- /* loop through change-points, determining affect on the new memmap */
- for (chgidx = 0; chgidx < chg_nr; chgidx++) {
- /* keep track of all overlapping memmap entries */
- if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
- /* add map entry to overlap list (> 1 entry implies an overlap) */
- overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
- } else {
- /* remove entry from list (order independent, so swap with last) */
- for (i = 0; i < overlap_entries; i++) {
- if (overlap_list[i] == change_point[chgidx]->pentry)
- overlap_list[i] = overlap_list[overlap_entries-1];
- }
- overlap_entries--;
- }
- /* if there are overlapping entries, decide which "type" to use */
- /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
- current_type = 0;
- for (i = 0; i < overlap_entries; i++)
- if (overlap_list[i]->type > current_type)
- current_type = overlap_list[i]->type;
- /* continue building up new memmap based on this information */
- if (current_type != last_type) {
- if (last_type != 0) {
- new_map[new_entry].size =
- change_point[chgidx]->addr - last_addr;
- /* move forward only if the new size was non-zero */
- if (new_map[new_entry].size != 0)
- if (++new_entry >= BFIN_MEMMAP_MAX)
- break; /* no more space left for new entries */
- }
- if (current_type != 0) {
- new_map[new_entry].addr = change_point[chgidx]->addr;
- new_map[new_entry].type = current_type;
- last_addr = change_point[chgidx]->addr;
- }
- last_type = current_type;
- }
- }
- new_nr = new_entry; /* retain count for new entries */
-
- /* copy new mapping into original location */
- memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
- *pnr_map = new_nr;
-
- return 0;
-}
-
-static void __init print_memory_map(char *who)
-{
- int i;
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
- bfin_memmap.map[i].addr,
- bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
- switch (bfin_memmap.map[i].type) {
- case BFIN_MEMMAP_RAM:
- printk(KERN_CONT "(usable)\n");
- break;
- case BFIN_MEMMAP_RESERVED:
- printk(KERN_CONT "(reserved)\n");
- break;
- default:
- printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
- break;
- }
- }
-}
-
-static __init int parse_memmap(char *arg)
-{
- unsigned long long start_at, mem_size;
-
- if (!arg)
- return -EINVAL;
-
- mem_size = memparse(arg, &arg);
- if (*arg == '@') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
- } else if (*arg == '$') {
- start_at = memparse(arg+1, &arg);
- add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
- }
-
- return 0;
-}
-
-/*
- * Initial parsing of the command line. Currently, we support:
- * - Controlling the linux memory size: mem=xxx[KMG]
- * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
- * $ -> reserved memory is dcacheable
- * # -> reserved memory is icacheable
- * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
- * @ from <start> to <start>+<mem>, type RAM
- * $ from <start> to <start>+<mem>, type RESERVED
- */
-static __init void parse_cmdline_early(char *cmdline_p)
-{
- char c = ' ', *to = cmdline_p;
- unsigned int memsize;
- for (;;) {
- if (c == ' ') {
- if (!memcmp(to, "mem=", 4)) {
- to += 4;
- memsize = memparse(to, &to);
- if (memsize)
- _ramend = memsize;
-
- } else if (!memcmp(to, "max_mem=", 8)) {
- to += 8;
- memsize = memparse(to, &to);
- if (memsize) {
- physical_mem_end = memsize;
- if (*to != ' ') {
- if (*to == '$'
- || *(to + 1) == '$')
- reserved_mem_dcache_on = 1;
- if (*to == '#'
- || *(to + 1) == '#')
- reserved_mem_icache_on = 1;
- }
- }
- } else if (!memcmp(to, "clkin_hz=", 9)) {
- to += 9;
- early_init_clkin_hz(to);
-#ifdef CONFIG_EARLY_PRINTK
- } else if (!memcmp(to, "earlyprintk=", 12)) {
- to += 12;
- setup_early_printk(to);
-#endif
- } else if (!memcmp(to, "memmap=", 7)) {
- to += 7;
- parse_memmap(to);
- }
- }
- c = *(to++);
- if (!c)
- break;
- }
-}
-
-/*
- * Setup memory defaults from user config.
- * The physical memory layout looks like:
- *
- * [_rambase, _ramstart]: kernel image
- * [memory_start, memory_end]: dynamic memory managed by kernel
- * [memory_end, _ramend]: reserved memory
- * [memory_mtd_start(memory_end),
- * memory_mtd_start + mtd_size]: rootfs (if any)
- * [_ramend - DMA_UNCACHED_REGION,
- * _ramend]: uncached DMA region
- * [_ramend, physical_mem_end]: memory not managed by kernel
- */
-static __init void memory_setup(void)
-{
-#ifdef CONFIG_MTD_UCLINUX
- unsigned long mtd_phys = 0;
-#endif
- unsigned long max_mem;
-
- _rambase = CONFIG_BOOT_LOAD;
- _ramstart = (unsigned long)_end;
-
- if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
- console_init();
- panic("DMA region exceeds memory limit: %lu.",
- _ramend - _ramstart);
- }
- max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
-
-#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
- /* Due to a Hardware Anomaly we need to limit the size of usable
- * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
- * 05000263 - Hardware loop corrupted when taking an ICPLB exception
- */
-# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
- if (max_mem >= 56 * 1024 * 1024)
- max_mem = 56 * 1024 * 1024;
-# else
- if (max_mem >= 60 * 1024 * 1024)
- max_mem = 60 * 1024 * 1024;
-# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
-#endif /* ANOMALY_05000263 */
-
-
-#ifdef CONFIG_MPU
- /* Round up to multiple of 4MB */
- memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
-#else
- memory_start = PAGE_ALIGN(_ramstart);
-#endif
-
-#if defined(CONFIG_MTD_UCLINUX)
- /* generic memory mapped MTD driver */
- memory_mtd_end = memory_end;
-
- mtd_phys = _ramstart;
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
-
-# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
- if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
- mtd_size =
- PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
-# endif
-
-# if defined(CONFIG_CRAMFS)
- if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
- mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
-# endif
-
-# if defined(CONFIG_ROMFS_FS)
- if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
- && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
- mtd_size =
- PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
-
- /* ROM_FS is XIP, so if we found it, we need to limit memory */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
- }
-# endif /* CONFIG_ROMFS_FS */
-
- /* Since the default MTD_UCLINUX has no magic number, we just blindly
- * read 8 past the end of the kernel's image, and look at it.
- * When no image is attached, mtd_size is set to a random number
- * Do some basic sanity checks before operating on things
- */
- if (mtd_size == 0 || memory_end <= mtd_size) {
- pr_emerg("Could not find valid ram mtd attached.\n");
- } else {
- memory_end -= mtd_size;
-
- /* Relocate MTD image to the top of memory after the uncached memory area */
- uclinux_ram_map.phys = memory_mtd_start = memory_end;
- uclinux_ram_map.size = mtd_size;
- pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
- _end, mtd_size, (void *)memory_mtd_start);
- dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
- }
-#endif /* CONFIG_MTD_UCLINUX */
-
- /* We need lo limit memory, since everything could have a text section
- * of userspace in it, and expose anomaly 05000263. If the anomaly
- * doesn't exist, or we don't need to - then dont.
- */
- if (memory_end > max_mem) {
- pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
- (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- memory_end = max_mem;
- }
-
-#ifdef CONFIG_MPU
-#if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
- page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
- ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
-#else
- page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
-#endif
- page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
-#endif
-
- init_mm.start_code = (unsigned long)_stext;
- init_mm.end_code = (unsigned long)_etext;
- init_mm.end_data = (unsigned long)_edata;
- init_mm.brk = (unsigned long)0;
-
- printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
- printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
-
- printk(KERN_INFO "Memory map:\n"
- " fixedcode = 0x%p-0x%p\n"
- " text = 0x%p-0x%p\n"
- " rodata = 0x%p-0x%p\n"
- " bss = 0x%p-0x%p\n"
- " data = 0x%p-0x%p\n"
- " stack = 0x%p-0x%p\n"
- " init = 0x%p-0x%p\n"
- " available = 0x%p-0x%p\n"
-#ifdef CONFIG_MTD_UCLINUX
- " rootfs = 0x%p-0x%p\n"
-#endif
-#if DMA_UNCACHED_REGION > 0
- " DMA Zone = 0x%p-0x%p\n"
-#endif
- , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
- _stext, _etext,
- __start_rodata, __end_rodata,
- __bss_start, __bss_stop,
- _sdata, _edata,
- (void *)&init_thread_union,
- (void *)((int)(&init_thread_union) + THREAD_SIZE),
- __init_begin, __init_end,
- (void *)_ramstart, (void *)memory_end
-#ifdef CONFIG_MTD_UCLINUX
- , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
-#endif
-#if DMA_UNCACHED_REGION > 0
- , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
-#endif
- );
-}
-
-/*
- * Find the lowest, highest page frame number we have available
- */
-void __init find_min_max_pfn(void)
-{
- int i;
-
- max_pfn = 0;
- min_low_pfn = PFN_DOWN(memory_end);
-
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- unsigned long start, end;
- /* RAM? */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- start = PFN_UP(bfin_memmap.map[i].addr);
- end = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
- if (start >= end)
- continue;
- if (end > max_pfn)
- max_pfn = end;
- if (start < min_low_pfn)
- min_low_pfn = start;
- }
-}
-
-static __init void setup_bootmem_allocator(void)
-{
- int bootmap_size;
- int i;
- unsigned long start_pfn, end_pfn;
- unsigned long curr_pfn, last_pfn, size;
-
- /* mark memory between memory_start and memory_end usable */
- add_memory_region(memory_start,
- memory_end - memory_start, BFIN_MEMMAP_RAM);
- /* sanity check for overlap */
- sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
- print_memory_map("boot memmap");
-
- /* initialize globals in linux/bootmem.h */
- find_min_max_pfn();
- /* pfn of the last usable page frame */
- if (max_pfn > memory_end >> PAGE_SHIFT)
- max_pfn = memory_end >> PAGE_SHIFT;
- /* pfn of last page frame directly mapped by kernel */
- max_low_pfn = max_pfn;
- /* pfn of the first usable page frame after kernel image*/
- if (min_low_pfn < memory_start >> PAGE_SHIFT)
- min_low_pfn = memory_start >> PAGE_SHIFT;
- start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
- end_pfn = memory_end >> PAGE_SHIFT;
-
- /*
- * give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map at the start of memory.
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- memory_start >> PAGE_SHIFT, /* map goes here */
- start_pfn, end_pfn);
-
- /* register the memmap regions with the bootmem allocator */
- for (i = 0; i < bfin_memmap.nr_map; i++) {
- /*
- * Reserve usable memory
- */
- if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
- continue;
- /*
- * We are rounding up the start address of usable memory:
- */
- curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
- if (curr_pfn >= end_pfn)
- continue;
- /*
- * ... and at the end of the usable range downwards:
- */
- last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
- bfin_memmap.map[i].size);
-
- if (last_pfn > end_pfn)
- last_pfn = end_pfn;
-
- /*
- * .. finally, did all the rounding and playing
- * around just make the area go away?
- */
- if (last_pfn <= curr_pfn)
- continue;
-
- size = last_pfn - curr_pfn;
- free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
- }
-
- /* reserve memory before memory_start, including bootmap */
- reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
- memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
- BOOTMEM_DEFAULT);
-}
-
-#define EBSZ_TO_MEG(ebsz) \
-({ \
- int meg = 0; \
- switch (ebsz & 0xf) { \
- case 0x1: meg = 16; break; \
- case 0x3: meg = 32; break; \
- case 0x5: meg = 64; break; \
- case 0x7: meg = 128; break; \
- case 0x9: meg = 256; break; \
- case 0xb: meg = 512; break; \
- } \
- meg; \
-})
-static inline int __init get_mem_size(void)
-{
-#if defined(EBIU_SDBCTL)
-# if defined(BF561_FAMILY)
- int ret = 0;
- u32 sdbctl = bfin_read_EBIU_SDBCTL();
- ret += EBSZ_TO_MEG(sdbctl >> 0);
- ret += EBSZ_TO_MEG(sdbctl >> 8);
- ret += EBSZ_TO_MEG(sdbctl >> 16);
- ret += EBSZ_TO_MEG(sdbctl >> 24);
- return ret;
-# else
- return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
-# endif
-#elif defined(EBIU_DDRCTL1)
- u32 ddrctl = bfin_read_EBIU_DDRCTL1();
- int ret = 0;
- switch (ddrctl & 0xc0000) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- }
- switch (ddrctl & 0x30000) {
- case DEVWD_4:
- ret *= 2;
- case DEVWD_8:
- ret *= 2;
- case DEVWD_16:
- break;
- }
- if ((ddrctl & 0xc000) == 0x4000)
- ret *= 2;
- return ret;
-#elif defined(CONFIG_BF60x)
- u32 ddrctl = bfin_read_DMC0_CFG();
- int ret;
- switch (ddrctl & 0xf00) {
- case DEVSZ_64:
- ret = 64 / 8;
- break;
- case DEVSZ_128:
- ret = 128 / 8;
- break;
- case DEVSZ_256:
- ret = 256 / 8;
- break;
- case DEVSZ_512:
- ret = 512 / 8;
- break;
- case DEVSZ_1G:
- ret = 1024 / 8;
- break;
- case DEVSZ_2G:
- ret = 2048 / 8;
- break;
- }
- return ret;
-#endif
- BUG();
-}
-
-__attribute__((weak))
-void __init native_machine_early_platform_add_devices(void)
-{
-}
-
-#ifdef CONFIG_BF60x
-static inline u_long bfin_get_clk(char *name)
-{
- struct clk *clk;
- u_long clk_rate;
-
- clk = clk_get(NULL, name);
- if (IS_ERR(clk))
- return 0;
-
- clk_rate = clk_get_rate(clk);
- clk_put(clk);
- return clk_rate;
-}
-#endif
-
-void __init setup_arch(char **cmdline_p)
-{
- u32 mmr;
- unsigned long sclk, cclk;
-
- native_machine_early_platform_add_devices();
-
- enable_shadow_console();
-
- /* Check to make sure we are running on the right processor */
- mmr = bfin_cpuid();
- if (unlikely(CPUID != bfin_cpuid()))
- printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
- CPU, bfin_cpuid(), bfin_revid());
-
-#ifdef CONFIG_DUMMY_CONSOLE
- conswitchp = &dummy_con;
-#endif
-
-#if defined(CONFIG_CMDLINE_BOOL)
- strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
- command_line[sizeof(command_line) - 1] = 0;
-#endif
-
- /* Keep a copy of command line */
- *cmdline_p = &command_line[0];
- memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-
- memset(&bfin_memmap, 0, sizeof(bfin_memmap));
-
-#ifdef CONFIG_BF60x
- /* Should init clock device before parse command early */
- clk_init();
-#endif
- /* If the user does not specify things on the command line, use
- * what the bootloader set things up as
- */
- physical_mem_end = 0;
- parse_cmdline_early(&command_line[0]);
-
- if (_ramend == 0)
- _ramend = get_mem_size() * 1024 * 1024;
-
- if (physical_mem_end == 0)
- physical_mem_end = _ramend;
-
- memory_setup();
-
-#ifndef CONFIG_BF60x
- /* Initialize Async memory banks */
- bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
- bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
- bfin_write_EBIU_AMGCTL(AMGCTLVAL);
-#ifdef CONFIG_EBIU_MBSCTLVAL
- bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
- bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
- bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
-#endif
-#endif
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
- bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
- bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
- bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
- bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
- ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
-#endif
-
- cclk = get_cclk();
- sclk = get_sclk();
-
- if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
- panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
-
-#ifdef BF561_FAMILY
- if (ANOMALY_05000266) {
- bfin_read_IMDMA_D0_IRQ_STATUS();
- bfin_read_IMDMA_D1_IRQ_STATUS();
- }
-#endif
-
- mmr = bfin_read_TBUFCTL();
- printk(KERN_INFO "Hardware Trace %s and %sabled\n",
- (mmr & 0x1) ? "active" : "off",
- (mmr & 0x2) ? "en" : "dis");
-#ifndef CONFIG_BF60x
- mmr = bfin_read_SYSCR();
- printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
-
- /* Newer parts mirror SWRST bits in SYSCR */
-#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- _bfin_swrst = bfin_read_SWRST();
-#else
- /* Clear boot mode field */
- _bfin_swrst = mmr & ~0xf;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
-#endif
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
- bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
-#endif
-
-#ifdef CONFIG_SMP
- if (_bfin_swrst & SWRST_DBL_FAULT_A) {
-#else
- if (_bfin_swrst & RESET_DOUBLE) {
-#endif
- printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* We assume the crashing kernel, and the current symbol table match */
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda.retx);
- } else if (_bfin_swrst & RESET_WDOG)
- printk(KERN_INFO "Recovering from Watchdog event\n");
- else if (_bfin_swrst & RESET_SOFTWARE)
- printk(KERN_NOTICE "Reset caused by Software reset\n");
-#endif
- printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
- if (bfin_compiled_revid() == 0xffff)
- printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
- else if (bfin_compiled_revid() == -1)
- printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
- else
- printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
-
- if (likely(CPUID == bfin_cpuid())) {
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
- bfin_revid());
- else if (bfin_compiled_revid() != 0xffff) {
- printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
- bfin_compiled_revid(), bfin_revid());
- if (bfin_compiled_revid() > bfin_revid())
- panic("Error: you are missing anomaly workarounds for this rev");
- }
- }
- if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
- printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
- CPU, bfin_revid());
- }
-
- printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
-
-#ifdef CONFIG_BF60x
- printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
- cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
-#else
- printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
- cclk / 1000000, sclk / 1000000);
-#endif
-
- setup_bootmem_allocator();
-
- paging_init();
-
- /* Copy atomic sequences to their fixed location, and sanity check that
- these locations are the ones that we advertise to userspace. */
- memcpy((void *)FIXED_CODE_START, &fixed_code_start,
- FIXED_CODE_END - FIXED_CODE_START);
- BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
- != SIGRETURN_STUB - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
- != ATOMIC_XCHG32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
- != ATOMIC_CAS32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
- != ATOMIC_ADD32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
- != ATOMIC_SUB32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
- != ATOMIC_IOR32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
- != ATOMIC_AND32 - FIXED_CODE_START);
- BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
- != ATOMIC_XOR32 - FIXED_CODE_START);
- BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
- != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
-
-#ifdef CONFIG_SMP
- platform_init_cpus();
-#endif
- init_exception_vectors();
- bfin_cache_init(); /* Initialize caches for the boot CPU */
-#ifdef CONFIG_SCB_PRIORITY
- init_scb();
-#endif
-}
-
-static int __init topology_init(void)
-{
- unsigned int cpu;
-
- for_each_possible_cpu(cpu) {
- register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
- }
-
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-/* Get the input clock frequency */
-static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
-#ifndef CONFIG_BF60x
-static u_long get_clkin_hz(void)
-{
- return cached_clkin_hz;
-}
-#endif
-static int __init early_init_clkin_hz(char *buf)
-{
- cached_clkin_hz = simple_strtoul(buf, NULL, 0);
-#ifdef BFIN_KERNEL_CLOCK
- if (cached_clkin_hz != CONFIG_CLKIN_HZ)
- panic("cannot change clkin_hz when reprogramming clocks");
-#endif
- return 1;
-}
-early_param("clkin_hz=", early_init_clkin_hz);
-
-#ifndef CONFIG_BF60x
-/* Get the voltage input multiplier */
-static u_long get_vco(void)
-{
- static u_long cached_vco;
- u_long msel, pll_ctl;
-
- /* The assumption here is that VCO never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_vco)
- return cached_vco;
-
- pll_ctl = bfin_read_PLL_CTL();
- msel = (pll_ctl >> 9) & 0x3F;
- if (0 == msel)
- msel = 64;
-
- cached_vco = get_clkin_hz();
- cached_vco >>= (1 & pll_ctl); /* DF bit */
- cached_vco *= msel;
- return cached_vco;
-}
-#endif
-
-/* Get the Core clock */
-u_long get_cclk(void)
-{
-#ifdef CONFIG_BF60x
- return bfin_get_clk("CCLK");
-#else
- static u_long cached_cclk_pll_div, cached_cclk;
- u_long csel, ssel;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV();
- if (ssel == cached_cclk_pll_div)
- return cached_cclk;
- else
- cached_cclk_pll_div = ssel;
-
- csel = ((ssel >> 4) & 0x03);
- ssel &= 0xf;
- if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
- cached_cclk = get_vco() / ssel;
- else
- cached_cclk = get_vco() >> csel;
- return cached_cclk;
-#endif
-}
-EXPORT_SYMBOL(get_cclk);
-
-#ifdef CONFIG_BF60x
-/* Get the bf60x clock of SCLK0 domain */
-u_long get_sclk0(void)
-{
- return bfin_get_clk("SCLK0");
-}
-EXPORT_SYMBOL(get_sclk0);
-
-/* Get the bf60x clock of SCLK1 domain */
-u_long get_sclk1(void)
-{
- return bfin_get_clk("SCLK1");
-}
-EXPORT_SYMBOL(get_sclk1);
-
-/* Get the bf60x DRAM clock */
-u_long get_dclk(void)
-{
- return bfin_get_clk("DCLK");
-}
-EXPORT_SYMBOL(get_dclk);
-#endif
-
-/* Get the default system clock */
-u_long get_sclk(void)
-{
-#ifdef CONFIG_BF60x
- return get_sclk0();
-#else
- static u_long cached_sclk;
- u_long ssel;
-
- /* The assumption here is that SCLK never changes at runtime.
- * If, someday, we support that, then we'll have to change this.
- */
- if (cached_sclk)
- return cached_sclk;
-
- if (bfin_read_PLL_STAT() & 0x1)
- return get_clkin_hz();
-
- ssel = bfin_read_PLL_DIV() & 0xf;
- if (0 == ssel) {
- printk(KERN_WARNING "Invalid System Clock\n");
- ssel = 1;
- }
-
- cached_sclk = get_vco() / ssel;
- return cached_sclk;
-#endif
-}
-EXPORT_SYMBOL(get_sclk);
-
-unsigned long sclk_to_usecs(unsigned long sclk)
-{
- u64 tmp = USEC_PER_SEC * (u64)sclk;
- do_div(tmp, get_sclk());
- return tmp;
-}
-EXPORT_SYMBOL(sclk_to_usecs);
-
-unsigned long usecs_to_sclk(unsigned long usecs)
-{
- u64 tmp = get_sclk() * (u64)usecs;
- do_div(tmp, USEC_PER_SEC);
- return tmp;
-}
-EXPORT_SYMBOL(usecs_to_sclk);
-
-/*
- * Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- char *cpu, *mmu, *fpu, *vendor, *cache;
- uint32_t revid;
- int cpu_num = *(unsigned int *)v;
- u_long sclk, cclk;
- u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
- struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
-
- cpu = CPU;
- mmu = "none";
- fpu = "none";
- revid = bfin_revid();
-
- sclk = get_sclk();
- cclk = get_cclk();
-
- switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
- case 0xca:
- vendor = "Analog Devices";
- break;
- default:
- vendor = "unknown";
- break;
- }
-
- seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
-
- if (CPUID == bfin_cpuid())
- seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
- else
- seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
- CPUID, bfin_cpuid());
-
- seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
- "stepping\t: %d ",
- cpu, cclk/1000000, sclk/1000000,
-#ifdef CONFIG_MPU
- "mpu on",
-#else
- "mpu off",
-#endif
- revid);
-
- if (bfin_revid() != bfin_compiled_revid()) {
- if (bfin_compiled_revid() == -1)
- seq_printf(m, "(Compiled for Rev none)");
- else if (bfin_compiled_revid() == 0xffff)
- seq_printf(m, "(Compiled for Rev any)");
- else
- seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
- }
-
- seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
- cclk/1000000, cclk%1000000,
- sclk/1000000, sclk%1000000);
- seq_printf(m, "bogomips\t: %lu.%02lu\n"
- "Calibration\t: %lu loops\n",
- (loops_per_jiffy * HZ) / 500000,
- ((loops_per_jiffy * HZ) / 5000) % 100,
- (loops_per_jiffy * HZ));
-
- /* Check Cache configutation */
- switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
- case ACACHE_BSRAM:
- cache = "dbank-A/B\t: cache/sram";
- dcache_size = 16;
- dsup_banks = 1;
- break;
- case ACACHE_BCACHE:
- cache = "dbank-A/B\t: cache/cache";
- dcache_size = 32;
- dsup_banks = 2;
- break;
- case ASRAM_BSRAM:
- cache = "dbank-A/B\t: sram/sram";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- default:
- cache = "unknown";
- dcache_size = 0;
- dsup_banks = 0;
- break;
- }
-
- /* Is it turned on? */
- if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
- dcache_size = 0;
-
- if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
- icache_size = 0;
-
- seq_printf(m, "cache size\t: %d KB(L1 icache) "
- "%d KB(L1 dcache) %d KB(L2 cache)\n",
- icache_size, dcache_size, 0);
- seq_printf(m, "%s\n", cache);
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "external memory\t: "
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
-
- if (icache_size)
- seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
- BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
- else
- seq_printf(m, "icache setup\t: off\n");
-
- seq_printf(m,
- "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
- dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
- BFIN_DLINES);
-#ifdef __ARCH_SYNC_CORE_DCACHE
- seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
-#endif
-#ifdef __ARCH_SYNC_CORE_ICACHE
- seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
-#endif
-
- seq_printf(m, "\n");
-
- if (cpu_num != num_possible_cpus() - 1)
- return 0;
-
- if (L2_LENGTH) {
- seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_ICACHEABLE)
- "cacheable"
-#else
- "uncacheable"
-#endif
- " in instruction cache\n");
- seq_printf(m, "L2 SRAM\t\t: "
-#if defined(CONFIG_BFIN_L2_WRITEBACK)
- "cacheable (write-back)"
-#elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
- "cacheable (write-through)"
-#else
- "uncacheable"
-#endif
- " in data cache\n");
- }
- seq_printf(m, "board name\t: %s\n", bfin_board_name);
- seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
- physical_mem_end >> 10, 0ul, physical_mem_end);
- seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
- ((int)memory_end - (int)_rambase) >> 10,
- _rambase, memory_end);
-
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- if (*pos == 0)
- *pos = cpumask_first(cpu_online_mask);
- if (*pos >= num_online_cpus())
- return NULL;
-
- return pos;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- *pos = cpumask_next(*pos, cpu_online_mask);
-
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-void __init cmdline_init(const char *r0)
-{
- early_shadow_stamp();
- if (r0)
- strlcpy(command_line, r0, COMMAND_LINE_SIZE);
-}
diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c
deleted file mode 100644
index aeb8343eeb03..000000000000
--- a/arch/blackfin/kernel/shadow_console.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * manage a small early shadow of the log buffer which we can pass between the
- * bootloader so early crash messages are communicated properly and easily
- *
- * Copyright 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/string.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/early_printk.h>
-
-#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
-#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
-#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
-#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
-
-static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
-
-__init void early_shadow_write(struct console *con, const char *s,
- unsigned int n)
-{
- unsigned int i;
- /*
- * save 2 bytes for the double null at the end
- * once we fail on a long line, make sure we don't write a short line afterwards
- */
- if ((shadow_console_buffer + n) <= (char *)(SHADOW_CONSOLE_END - 2)) {
- /* can't use memcpy - it may not be relocated yet */
- for (i = 0; i <= n; i++)
- shadow_console_buffer[i] = s[i];
- shadow_console_buffer += n;
- shadow_console_buffer[0] = 0;
- shadow_console_buffer[1] = 0;
- } else
- shadow_console_buffer = (char *)SHADOW_CONSOLE_END;
-}
-
-static __initdata struct console early_shadow_console = {
- .name = "early_shadow",
- .write = early_shadow_write,
- .flags = CON_BOOT | CON_PRINTBUFFER,
- .index = -1,
- .device = 0,
-};
-
-__init int shadow_console_enabled(void)
-{
- return early_shadow_console.flags & CON_ENABLED;
-}
-
-__init void mark_shadow_error(void)
-{
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
- loc[0] = SHADOW_CONSOLE_MAGIC;
- loc[1] = SHADOW_CONSOLE_START;
-}
-
-__init void enable_shadow_console(void)
-{
- if (!shadow_console_enabled()) {
- register_console(&early_shadow_console);
- /* for now, assume things are going to fail */
- mark_shadow_error();
- }
-}
-
-static __init int disable_shadow_console(void)
-{
- /*
- * by the time pure_initcall runs, the standard console is enabled,
- * and the early_console is off, so unset the magic numbers
- * unregistering the console is taken care of in common code (See
- * ./kernel/printk:disable_boot_consoles() )
- */
- int *loc = (int *)SHADOW_CONSOLE_MAGIC_LOC;
-
- loc[0] = 0;
-
- return 0;
-}
-pure_initcall(disable_shadow_console);
-
-/*
- * since we can't use printk, dump numbers (as hex), n = # bits
- */
-__init void early_shadow_reg(unsigned long reg, unsigned int n)
-{
- /*
- * can't use any "normal" kernel features, since thay
- * may not be relocated to their execute address yet
- */
- int i;
- char ascii[11] = " 0x";
-
- n = n / 4;
- reg = reg << ((8 - n) * 4);
- n += 3;
-
- for (i = 3; i <= n ; i++) {
- ascii[i] = hex_asc_lo(reg >> 28);
- reg <<= 4;
- }
- early_shadow_write(NULL, ascii, n);
-
-}
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
deleted file mode 100644
index 5f5172779204..000000000000
--- a/arch/blackfin/kernel/signal.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/signal.h>
-#include <linux/syscalls.h>
-#include <linux/ptrace.h>
-#include <linux/tty.h>
-#include <linux/personality.h>
-#include <linux/binfmts.h>
-#include <linux/uaccess.h>
-#include <linux/tracehook.h>
-#include <linux/sched/task_stack.h>
-
-#include <asm/cacheflush.h>
-#include <asm/ucontext.h>
-#include <asm/fixed_code.h>
-#include <asm/syscall.h>
-
-/* Location of the trace bit in SYSCFG. */
-#define TRACE_BITS 0x0001
-
-struct fdpic_func_descriptor {
- unsigned long text;
- unsigned long GOT;
-};
-
-struct rt_sigframe {
- int sig;
- struct siginfo *pinfo;
- void *puc;
- /* This is no longer needed by the kernel, but unfortunately userspace
- * code expects it to be there. */
- char retcode[8];
- struct siginfo info;
- struct ucontext uc;
-};
-
-static inline int
-rt_restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *pr0)
-{
- unsigned long usp = 0;
- int err = 0;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
-#define RESTORE(x) err |= __get_user(regs->x, &sc->sc_##x)
-
- /* restore passed registers */
- RESTORE(r0); RESTORE(r1); RESTORE(r2); RESTORE(r3);
- RESTORE(r4); RESTORE(r5); RESTORE(r6); RESTORE(r7);
- RESTORE(p0); RESTORE(p1); RESTORE(p2); RESTORE(p3);
- RESTORE(p4); RESTORE(p5);
- err |= __get_user(usp, &sc->sc_usp);
- wrusp(usp);
- RESTORE(a0w); RESTORE(a1w);
- RESTORE(a0x); RESTORE(a1x);
- RESTORE(astat);
- RESTORE(rets);
- RESTORE(pc);
- RESTORE(retx);
- RESTORE(fp);
- RESTORE(i0); RESTORE(i1); RESTORE(i2); RESTORE(i3);
- RESTORE(m0); RESTORE(m1); RESTORE(m2); RESTORE(m3);
- RESTORE(l0); RESTORE(l1); RESTORE(l2); RESTORE(l3);
- RESTORE(b0); RESTORE(b1); RESTORE(b2); RESTORE(b3);
- RESTORE(lc0); RESTORE(lc1);
- RESTORE(lt0); RESTORE(lt1);
- RESTORE(lb0); RESTORE(lb1);
- RESTORE(seqstat);
-
- regs->orig_p0 = -1; /* disable syscall checks */
-
- *pr0 = regs->r0;
- return err;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- unsigned long usp = rdusp();
- struct rt_sigframe *frame = (struct rt_sigframe *)(usp);
- sigset_t set;
- int r0;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (rt_restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return r0;
-
- badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-static inline int rt_setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs)
-{
- int err = 0;
-
-#define SETUP(x) err |= __put_user(regs->x, &sc->sc_##x)
-
- SETUP(r0); SETUP(r1); SETUP(r2); SETUP(r3);
- SETUP(r4); SETUP(r5); SETUP(r6); SETUP(r7);
- SETUP(p0); SETUP(p1); SETUP(p2); SETUP(p3);
- SETUP(p4); SETUP(p5);
- err |= __put_user(rdusp(), &sc->sc_usp);
- SETUP(a0w); SETUP(a1w);
- SETUP(a0x); SETUP(a1x);
- SETUP(astat);
- SETUP(rets);
- SETUP(pc);
- SETUP(retx);
- SETUP(fp);
- SETUP(i0); SETUP(i1); SETUP(i2); SETUP(i3);
- SETUP(m0); SETUP(m1); SETUP(m2); SETUP(m3);
- SETUP(l0); SETUP(l1); SETUP(l2); SETUP(l3);
- SETUP(b0); SETUP(b1); SETUP(b2); SETUP(b3);
- SETUP(lc0); SETUP(lc1);
- SETUP(lt0); SETUP(lt1);
- SETUP(lb0); SETUP(lb1);
- SETUP(seqstat);
-
- return err;
-}
-
-static inline void *get_sigframe(struct ksignal *ksig,
- size_t frame_size)
-{
- unsigned long usp = sigsp(rdusp(), ksig);
-
- return (void *)((usp - frame_size) & -8UL);
-}
-
-static int
-setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- struct rt_sigframe *frame;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- err |= __put_user(ksig->sig, &frame->sig);
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
-
- /* Create the ucontext. */
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(0, &frame->uc.uc_link);
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
- err |= rt_setup_sigcontext(&frame->uc.uc_mcontext, regs);
- err |= copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor *) ksig->ka.sa.sa_handler;
- u32 pc, p3;
- err |= __get_user(pc, &funcptr->text);
- err |= __get_user(p3, &funcptr->GOT);
- if (err)
- return -EFAULT;
- regs->pc = pc;
- regs->p3 = p3;
- } else
- regs->pc = (unsigned long)ksig->ka.sa.sa_handler;
- wrusp((unsigned long)frame);
- regs->rets = SIGRETURN_STUB;
-
- regs->r0 = frame->sig;
- regs->r1 = (unsigned long)(&frame->info);
- regs->r2 = (unsigned long)(&frame->uc);
-
- return 0;
-}
-
-static inline void
-handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
-{
- switch (regs->r0) {
- case -ERESTARTNOHAND:
- if (!has_handler)
- goto do_restart;
- regs->r0 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
- regs->r0 = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- do_restart:
- regs->p0 = regs->orig_p0;
- regs->r0 = regs->orig_r0;
- regs->pc -= 2;
- break;
-
- case -ERESTART_RESTARTBLOCK:
- regs->p0 = __NR_restart_syscall;
- regs->pc -= 2;
- break;
- }
-}
-
-/*
- * OK, we're invoking a handler
- */
-static void
-handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- int ret;
-
- /* are we from a system call? to see pt_regs->orig_p0 */
- if (regs->orig_p0 >= 0)
- /* If so, check system call restarting.. */
- handle_restart(regs, &ksig->ka, 1);
-
- /* set up the stack frame */
- ret = setup_rt_frame(ksig, sigmask_to_save(), regs);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Note that we go through the signals twice: once to check the signals
- * that the kernel can handle, and then we build all the user-level signal
- * handling stack-frames in one go after that.
- */
-asmlinkage void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- current->thread.esp0 = (unsigned long)regs;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(&ksig, regs);
- return;
- }
-
- /* Did we come from a system call? */
- if (regs->orig_p0 >= 0)
- /* Restart the system call - no handlers present */
- handle_restart(regs, NULL, 0);
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
-
-/*
- * notification of userspace execution resumption
- */
-asmlinkage void do_notify_resume(struct pt_regs *regs)
-{
- if (test_thread_flag(TIF_SIGPENDING))
- do_signal(regs);
-
- if (test_thread_flag(TIF_NOTIFY_RESUME)) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
-
diff --git a/arch/blackfin/kernel/stacktrace.c b/arch/blackfin/kernel/stacktrace.c
deleted file mode 100644
index 17198f3650b6..000000000000
--- a/arch/blackfin/kernel/stacktrace.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Blackfin stacktrace code (mostly copied from avr32)
- *
- * Copyright 2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/stacktrace.h>
-#include <linux/thread_info.h>
-#include <linux/module.h>
-
-register unsigned long current_frame_pointer asm("FP");
-
-struct stackframe {
- unsigned long fp;
- unsigned long rets;
-};
-
-/*
- * Save stack-backtrace addresses into a stack_trace buffer.
- */
-void save_stack_trace(struct stack_trace *trace)
-{
- unsigned long low, high;
- unsigned long fp;
- struct stackframe *frame;
- int skip = trace->skip;
-
- low = (unsigned long)task_stack_page(current);
- high = low + THREAD_SIZE;
- fp = current_frame_pointer;
-
- while (fp >= low && fp <= (high - sizeof(*frame))) {
- frame = (struct stackframe *)fp;
-
- if (skip) {
- skip--;
- } else {
- trace->entries[trace->nr_entries++] = frame->rets;
- if (trace->nr_entries >= trace->max_entries)
- break;
- }
-
- /*
- * The next frame must be at a higher address than the
- * current frame.
- */
- low = fp + sizeof(*frame);
- fp = frame->fp;
- }
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
deleted file mode 100644
index d998383cb956..000000000000
--- a/arch/blackfin/kernel/sys_bfin.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * contains various random system calls that have a non-standard
- * calling sequence on the Linux/Blackfin platform.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/spinlock.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/ipc.h>
-#include <linux/unistd.h>
-
-#include <asm/cacheflush.h>
-#include <asm/dma.h>
-#include <asm/cachectl.h>
-#include <asm/ptrace.h>
-
-asmlinkage void *sys_sram_alloc(size_t size, unsigned long flags)
-{
- return sram_alloc_with_lsl(size, flags);
-}
-
-asmlinkage int sys_sram_free(const void *addr)
-{
- return sram_free_with_lsl(addr);
-}
-
-asmlinkage void *sys_dma_memcpy(void *dest, const void *src, size_t len)
-{
- return safe_dma_memcpy(dest, src, len);
-}
-
-#if defined(CONFIG_FB) || defined(CONFIG_FB_MODULE)
-#include <linux/fb.h>
-#include <linux/export.h>
-unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr,
- unsigned long len, unsigned long pgoff, unsigned long flags)
-{
- struct fb_info *info = filp->private_data;
- return (unsigned long)info->screen_base;
-}
-EXPORT_SYMBOL(get_fb_unmapped_area);
-#endif
-
-/* Needed for legacy userspace atomic emulation */
-static DEFINE_SPINLOCK(bfin_spinlock_lock);
-
-#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int sys_bfin_spinlock(int *p)
-{
- int ret, tmp = 0;
-
- spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
- ret = get_user(tmp, p);
- if (likely(ret == 0)) {
- if (unlikely(tmp))
- ret = 1;
- else
- put_user(1, p);
- }
- spin_unlock(&bfin_spinlock_lock);
-
- return ret;
-}
-
-SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len, int, op)
-{
- if (is_user_addr_valid(current, addr, len) != 0)
- return -EINVAL;
-
- if (op & DCACHE)
- blackfin_dcache_flush_range(addr, addr + len);
- if (op & ICACHE)
- blackfin_icache_flush_range(addr, addr + len);
-
- return 0;
-}
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
deleted file mode 100644
index 01350557fbd7..000000000000
--- a/arch/blackfin/kernel/time-ts.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * Based on arm clockevents implementation and old bfin time tick.
- *
- * Copyright 2008-2009 Analog Devics Inc.
- * 2008 GeoTechnologies
- * Vitja Makarov
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/cpufreq.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-#include <asm/nmi.h>
-
-
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
-
-static notrace u64 bfin_read_cycles(struct clocksource *cs)
-{
-#ifdef CONFIG_CPU_FREQ
- return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
-#else
- return get_cycles();
-#endif
-}
-
-static struct clocksource bfin_cs_cycles = {
- .name = "bfin_cs_cycles",
- .rating = 400,
- .read = bfin_read_cycles,
- .mask = CLOCKSOURCE_MASK(64),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_cycles_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles),
- bfin_cs_cycles.mult, bfin_cs_cycles.shift);
-}
-
-static int __init bfin_cs_cycles_init(void)
-{
- if (clocksource_register_hz(&bfin_cs_cycles, get_cclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_cycles_init()
-#endif
-
-#ifdef CONFIG_GPTMR0_CLOCKSOURCE
-
-void __init setup_gptimer0(void)
-{
- disable_gptimers(TIMER0bit);
-
-#ifdef CONFIG_BF60x
- bfin_write16(TIMER_DATA_IMSK, 0);
- set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
- | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
-#else
- set_gptimer_config(TIMER0_id, \
- TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#endif
- set_gptimer_period(TIMER0_id, -1);
- set_gptimer_pwidth(TIMER0_id, -2);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-
-static u64 bfin_read_gptimer0(struct clocksource *cs)
-{
- return bfin_read_TIMER0_COUNTER();
-}
-
-static struct clocksource bfin_cs_gptimer0 = {
- .name = "bfin_cs_gptimer0",
- .rating = 350,
- .read = bfin_read_gptimer0,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static inline unsigned long long bfin_cs_gptimer0_sched_clock(void)
-{
- return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(),
- bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift);
-}
-
-static int __init bfin_cs_gptimer0_init(void)
-{
- setup_gptimer0();
-
- if (clocksource_register_hz(&bfin_cs_gptimer0, get_sclk()))
- panic("failed to register clocksource");
-
- return 0;
-}
-#else
-# define bfin_cs_gptimer0_init()
-#endif
-
-#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE)
-/* prefer to use cycles since it has higher rating */
-notrace unsigned long long sched_clock(void)
-{
-#if defined(CONFIG_CYCLES_CLOCKSOURCE)
- return bfin_cs_cycles_sched_clock();
-#else
- return bfin_cs_gptimer0_sched_clock();
-#endif
-}
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
-static int bfin_gptmr0_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-
- /* it starts counting three SCLK cycles after the TIMENx bit is set */
- set_gptimer_pwidth(TIMER0_id, cycles - 3);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_periodic(struct clock_event_device *evt)
-{
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA |
- TIMER_PERIOD_CNT | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM_CONT |
- TIMER_PULSE_HI | TIMER_IRQ_PER);
-#endif
-
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
- enable_gptimers(TIMER0bit);
- return 0;
-}
-
-static int bfin_gptmr0_set_oneshot(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
-#ifndef CONFIG_BF60x
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
-#else
- set_gptimer_config(TIMER0_id,
- TIMER_OUT_DIS | TIMER_MODE_PWM | TIMER_PULSE_HI |
- TIMER_IRQ_WID_DLY);
-#endif
-
- set_gptimer_period(TIMER0_id, 0);
- return 0;
-}
-
-static int bfin_gptmr0_shutdown(struct clock_event_device *evt)
-{
- disable_gptimers(TIMER0bit);
- return 0;
-}
-
-static void bfin_gptmr0_ack(void)
-{
- clear_gptimer_intr(TIMER0_id);
-}
-
-static void __init bfin_gptmr0_init(void)
-{
- disable_gptimers(TIMER0bit);
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t bfin_gptmr0_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
- smp_mb();
- /*
- * We want to ACK before we handle so that we can handle smaller timer
- * intervals. This way if the timer expires again while we're handling
- * things, we're more likely to see that 2nd int rather than swallowing
- * it by ACKing the int at the end of this handler.
- */
- bfin_gptmr0_ack();
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static struct irqaction gptmr0_irq = {
- .name = "Blackfin GPTimer0",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_gptmr0_interrupt,
-};
-
-static struct clock_event_device clockevent_gptmr0 = {
- .name = "bfin_gptimer0",
- .rating = 300,
- .irq = IRQ_TIMER0,
- .shift = 32,
- .features = CLOCK_EVT_FEAT_PERIODIC |
- CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = bfin_gptmr0_set_next_event,
- .set_state_shutdown = bfin_gptmr0_shutdown,
- .set_state_periodic = bfin_gptmr0_set_periodic,
- .set_state_oneshot = bfin_gptmr0_set_oneshot,
-};
-
-static void __init bfin_gptmr0_clockevent_init(struct clock_event_device *evt)
-{
- unsigned long clock_tick;
-
- clock_tick = get_sclk();
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(0);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_GPTMR0 */
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
-/* per-cpu local core timer */
-DEFINE_PER_CPU(struct clock_event_device, coretmr_events);
-
-static int bfin_coretmr_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TCOUNT(cycles);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN);
- return 0;
-}
-
-static int bfin_coretmr_set_periodic(struct clock_event_device *evt)
-{
- unsigned long tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
-
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
- CSYNC();
- bfin_write_TCNTL(TMPWR | TMREN | TAUTORLD);
- return 0;
-}
-
-static int bfin_coretmr_set_oneshot(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(TMPWR);
- CSYNC();
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
- return 0;
-}
-
-static int bfin_coretmr_shutdown(struct clock_event_device *evt)
-{
- bfin_write_TCNTL(0);
- CSYNC();
- return 0;
-}
-
-void bfin_coretmr_init(void)
-{
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter. */
- bfin_write_TSCALE(TIME_SCALE - 1);
- bfin_write_TPERIOD(0);
- bfin_write_TCOUNT(0);
-
- CSYNC();
-}
-
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-
-irqreturn_t bfin_coretmr_interrupt(int irq, void *dev_id)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
- smp_mb();
- evt->event_handler(evt);
-
- touch_nmi_watchdog();
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction coretmr_irq = {
- .name = "Blackfin CoreTimer",
- .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
- .handler = bfin_coretmr_interrupt,
-};
-
-void bfin_coretmr_clockevent_init(void)
-{
- unsigned long clock_tick;
- unsigned int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
-
-#ifdef CONFIG_SMP
- evt->broadcast = smp_timer_broadcast;
-#endif
-
- evt->name = "bfin_core_timer";
- evt->rating = 350;
- evt->irq = -1;
- evt->shift = 32;
- evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
- evt->set_next_event = bfin_coretmr_set_next_event;
- evt->set_state_shutdown = bfin_coretmr_shutdown;
- evt->set_state_periodic = bfin_coretmr_set_periodic;
- evt->set_state_oneshot = bfin_coretmr_set_oneshot;
-
- clock_tick = get_cclk() / TIME_SCALE;
- evt->mult = div_sc(clock_tick, NSEC_PER_SEC, evt->shift);
- evt->max_delta_ns = clockevent_delta2ns(-1, evt);
- evt->max_delta_ticks = (unsigned long)-1;
- evt->min_delta_ns = clockevent_delta2ns(100, evt);
- evt->min_delta_ticks = 100;
-
- evt->cpumask = cpumask_of(cpu);
-
- clockevents_register_device(evt);
-}
-#endif /* CONFIG_TICKSOURCE_CORETMR */
-
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- bfin_cs_cycles_init();
- bfin_cs_gptimer0_init();
-
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- bfin_coretmr_init();
- setup_irq(IRQ_CORETMR, &coretmr_irq);
- bfin_coretmr_clockevent_init();
-#endif
-
-#if defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_gptmr0_init();
- setup_irq(IRQ_TIMER0, &gptmr0_irq);
- gptmr0_irq.dev_id = &clockevent_gptmr0;
- bfin_gptmr0_clockevent_init(&clockevent_gptmr0);
-#endif
-
-#if !defined(CONFIG_TICKSOURCE_CORETMR) && !defined(CONFIG_TICKSOURCE_GPTMR0)
-# error at least one clock event device is required
-#endif
-}
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
deleted file mode 100644
index 3126b920a4a5..000000000000
--- a/arch/blackfin/kernel/time.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * arch/blackfin/kernel/time.c
- *
- * This file contains the Blackfin-specific time handling details.
- * Most of the stuff is located in the machine specific files.
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/profile.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-
-#include <asm/blackfin.h>
-#include <asm/time.h>
-#include <asm/gptimers.h>
-
-/* This is an NTP setting */
-#define TICK_SIZE (tick_nsec / 1000)
-
-static struct irqaction bfin_timer_irq = {
- .name = "Blackfin Timer Tick",
-};
-
-#if defined(CONFIG_IPIPE)
-void __init setup_system_timer0(void)
-{
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-
- disable_gptimers(TIMER0bit);
- set_gptimer_status(0, TIMER_STATUS_TRUN0);
- while (get_gptimer_status(0) & TIMER_STATUS_TRUN0)
- udelay(10);
-
- set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */
- set_gptimer_period(TIMER0_id, get_sclk() / HZ);
- set_gptimer_pwidth(TIMER0_id, 1);
- SSYNC();
- enable_gptimers(TIMER0bit);
-}
-#else
-void __init setup_core_timer(void)
-{
- u32 tcount;
-
- /* power up the timer, but don't enable it just yet */
- bfin_write_TCNTL(TMPWR);
- CSYNC();
-
- /* the TSCALE prescaler counter */
- bfin_write_TSCALE(TIME_SCALE - 1);
-
- tcount = ((get_cclk() / (HZ * TIME_SCALE)) - 1);
- bfin_write_TPERIOD(tcount);
- bfin_write_TCOUNT(tcount);
-
- /* now enable the timer */
- CSYNC();
-
- bfin_write_TCNTL(TAUTORLD | TMREN | TMPWR);
-}
-#endif
-
-static void __init
-time_sched_init(irqreturn_t(*timer_routine) (int, void *))
-{
-#if defined(CONFIG_IPIPE)
- setup_system_timer0();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_TIMER0, &bfin_timer_irq);
-#else
- setup_core_timer();
- bfin_timer_irq.handler = timer_routine;
- setup_irq(IRQ_CORETMR, &bfin_timer_irq);
-#endif
-}
-
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
-/*
- * Should return useconds since last timer tick
- */
-static u32 blackfin_gettimeoffset(void)
-{
- unsigned long offset;
- unsigned long clocks_per_jiffy;
-
-#if defined(CONFIG_IPIPE)
- clocks_per_jiffy = bfin_read_TIMER0_PERIOD();
- offset = bfin_read_TIMER0_COUNTER() / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- if ((get_gptimer_status(0) & TIMER_STATUS_TIMIL0) && offset < (100000 / HZ / 2))
- offset += (USEC_PER_SEC / HZ);
-#else
- clocks_per_jiffy = bfin_read_TPERIOD();
- offset = (clocks_per_jiffy - bfin_read_TCOUNT()) / \
- (((clocks_per_jiffy + 1) * HZ) / USEC_PER_SEC);
-
- /* Check if we just wrapped the counters and maybe missed a tick */
- if ((bfin_read_ILAT() & (1 << IRQ_CORETMR))
- && (offset < (100000 / HZ / 2)))
- offset += (USEC_PER_SEC / HZ);
-#endif
- return offset;
-}
-#endif
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-#ifdef CONFIG_CORE_TIMER_IRQ_L1
-__attribute__((l1_text))
-#endif
-irqreturn_t timer_interrupt(int irq, void *dummy)
-{
- xtime_update(1);
-
-#ifdef CONFIG_IPIPE
- update_root_process_times(get_irq_regs());
-#else
- update_process_times(user_mode(get_irq_regs()));
-#endif
- profile_tick(CPU_PROFILING);
-
- return IRQ_HANDLED;
-}
-
-void read_persistent_clock(struct timespec *ts)
-{
- time_t secs_since_1970 = (365 * 37 + 9) * 24 * 60 * 60; /* 1 Jan 2007 */
- ts->tv_sec = secs_since_1970;
- ts->tv_nsec = 0;
-}
-
-void __init time_init(void)
-{
-#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
- arch_gettimeoffset = blackfin_gettimeoffset;
-#endif
-
-#ifdef CONFIG_RTC_DRV_BFIN
- /* [#2663] hack to filter junk RTC values that would cause
- * userspace to have to deal with time values greater than
- * 2^31 seconds (which uClibc cannot cope with yet)
- */
- if ((bfin_read_RTC_STAT() & 0xC0000000) == 0xC0000000) {
- printk(KERN_NOTICE "bfin-rtc: invalid date; resetting\n");
- bfin_write_RTC_STAT(0);
- }
-#endif
-
- time_sched_init(timer_interrupt);
-}
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
deleted file mode 100644
index 151f22196ab6..000000000000
--- a/arch/blackfin/kernel/trace.c
+++ /dev/null
@@ -1,988 +0,0 @@
-/* provide some functions which dump the trace buffer, in a nice way for people
- * to read it, and understand what is going on
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/kernel.h>
-#include <linux/hardirq.h>
-#include <linux/thread_info.h>
-#include <linux/mm.h>
-#include <linux/oom.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/traps.h>
-#include <asm/irq_handler.h>
-#include <asm/pda.h>
-
-void decode_address(char *buf, unsigned long address)
-{
- struct task_struct *p;
- struct mm_struct *mm;
- unsigned long offset;
- struct rb_node *n;
-
-#ifdef CONFIG_KALLSYMS
- unsigned long symsize;
- const char *symname;
- char *modname;
- char *delim = ":";
- char namebuf[128];
-#endif
-
- buf += sprintf(buf, "<0x%08lx> ", address);
-
-#ifdef CONFIG_KALLSYMS
- /* look up the address and see if we are in kernel space */
- symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
-
- if (symname) {
- /* yeah! kernel space! */
- if (!modname)
- modname = delim = "";
- sprintf(buf, "{ %s%s%s%s + 0x%lx }",
- delim, modname, delim, symname,
- (unsigned long)offset);
- return;
- }
-#endif
-
- if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
- /* Problem in fixed code section? */
- strcat(buf, "/* Maybe fixed code section */");
- return;
-
- } else if (address < CONFIG_BOOT_LOAD) {
- /* Problem somewhere before the kernel start address */
- strcat(buf, "/* Maybe null pointer? */");
- return;
-
- } else if (address >= COREMMR_BASE) {
- strcat(buf, "/* core mmrs */");
- return;
-
- } else if (address >= SYSMMR_BASE) {
- strcat(buf, "/* system mmrs */");
- return;
-
- } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
- strcat(buf, "/* on-chip L1 ROM */");
- return;
-
- } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
- strcat(buf, "/* on-chip scratchpad */");
- return;
-
- } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
- strcat(buf, "/* unconnected memory */");
- return;
-
- } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
- strcat(buf, "/* reserved memory */");
- return;
-
- } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
- strcat(buf, "/* on-chip Data Bank A */");
- return;
-
- } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
- strcat(buf, "/* on-chip Data Bank B */");
- return;
- }
-
- /*
- * Don't walk any of the vmas if we are oopsing, it has been known
- * to cause problems - corrupt vmas (kernel crashes) cause double faults
- */
- if (oops_in_progress) {
- strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
- return;
- }
-
- /* looks like we're off in user-land, so let's walk all the
- * mappings of all our processes and see if we can't be a whee
- * bit more specific
- */
- read_lock(&tasklist_lock);
- for_each_process(p) {
- struct task_struct *t;
-
- t = find_lock_task_mm(p);
- if (!t)
- continue;
-
- mm = t->mm;
- if (!down_read_trylock(&mm->mmap_sem))
- goto __continue;
-
- for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
- struct vm_area_struct *vma;
-
- vma = rb_entry(n, struct vm_area_struct, vm_rb);
-
- if (address >= vma->vm_start && address < vma->vm_end) {
- char _tmpbuf[256];
- char *name = t->comm;
- struct file *file = vma->vm_file;
-
- if (file) {
- char *d_name = file_path(file, _tmpbuf,
- sizeof(_tmpbuf));
- if (!IS_ERR(d_name))
- name = d_name;
- }
-
- /* FLAT does not have its text aligned to the start of
- * the map while FDPIC ELF does ...
- */
-
- /* before we can check flat/fdpic, we need to
- * make sure current is valid
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3)) {
- if (current->mm &&
- (address > current->mm->start_code) &&
- (address < current->mm->end_code))
- offset = address - current->mm->start_code;
- else
- offset = (address - vma->vm_start) +
- (vma->vm_pgoff << PAGE_SHIFT);
-
- sprintf(buf, "[ %s + 0x%lx ]", name, offset);
- } else
- sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
- name, vma->vm_start, vma->vm_end);
-
- up_read(&mm->mmap_sem);
- task_unlock(t);
-
- if (buf[0] == '\0')
- sprintf(buf, "[ %s ] dynamic memory", name);
-
- goto done;
- }
- }
-
- up_read(&mm->mmap_sem);
-__continue:
- task_unlock(t);
- }
-
- /*
- * we were unable to find this address anywhere,
- * or some MMs were skipped because they were in use.
- */
- sprintf(buf, "/* kernel dynamic memory */");
-
-done:
- read_unlock(&tasklist_lock);
-}
-
-#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
-
-/*
- * Similar to get_user, do some address checking, then dereference
- * Return true on success, false on bad address
- */
-bool get_mem16(unsigned short *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- switch (bfin_mem_access_type(addr, 2)) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- *val = *address;
- return true;
- case BFIN_MEM_ACCESS_DMA:
- dma_memcpy(val, address, 2);
- return true;
- case BFIN_MEM_ACCESS_ITEST:
- isram_memcpy(val, address, 2);
- return true;
- default: /* invalid access */
- return false;
- }
-}
-
-bool get_instruction(unsigned int *val, unsigned short *address)
-{
- unsigned long addr = (unsigned long)address;
- unsigned short opcode0, opcode1;
-
- /* Check for odd addresses */
- if (addr & 0x1)
- return false;
-
- /* MMR region will never have instructions */
- if (addr >= SYSMMR_BASE)
- return false;
-
- /* Scratchpad will never have instructions */
- if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
- return false;
-
- /* Data banks will never have instructions */
- if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
- return false;
-
- if (!get_mem16(&opcode0, address))
- return false;
-
- /* was this a 32-bit instruction? If so, get the next 16 bits */
- if ((opcode0 & 0xc000) == 0xc000) {
- if (!get_mem16(&opcode1, address + 1))
- return false;
- *val = (opcode0 << 16) + opcode1;
- } else
- *val = opcode0;
-
- return true;
-}
-
-#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
-/*
- * decode the instruction if we are printing out the trace, as it
- * makes things easier to follow, without running it through objdump
- * Decode the change of flow, and the common load/store instructions
- * which are the main cause for faults, and discontinuities in the trace
- * buffer.
- */
-
-#define ProgCtrl_opcode 0x0000
-#define ProgCtrl_poprnd_bits 0
-#define ProgCtrl_poprnd_mask 0xf
-#define ProgCtrl_prgfunc_bits 4
-#define ProgCtrl_prgfunc_mask 0xf
-#define ProgCtrl_code_bits 8
-#define ProgCtrl_code_mask 0xff
-
-static void decode_ProgCtrl_0(unsigned int opcode)
-{
- int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
- int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
-
- if (prgfunc == 0 && poprnd == 0)
- pr_cont("NOP");
- else if (prgfunc == 1 && poprnd == 0)
- pr_cont("RTS");
- else if (prgfunc == 1 && poprnd == 1)
- pr_cont("RTI");
- else if (prgfunc == 1 && poprnd == 2)
- pr_cont("RTX");
- else if (prgfunc == 1 && poprnd == 3)
- pr_cont("RTN");
- else if (prgfunc == 1 && poprnd == 4)
- pr_cont("RTE");
- else if (prgfunc == 2 && poprnd == 0)
- pr_cont("IDLE");
- else if (prgfunc == 2 && poprnd == 3)
- pr_cont("CSYNC");
- else if (prgfunc == 2 && poprnd == 4)
- pr_cont("SSYNC");
- else if (prgfunc == 2 && poprnd == 5)
- pr_cont("EMUEXCPT");
- else if (prgfunc == 3)
- pr_cont("CLI R%i", poprnd);
- else if (prgfunc == 4)
- pr_cont("STI R%i", poprnd);
- else if (prgfunc == 5)
- pr_cont("JUMP (P%i)", poprnd);
- else if (prgfunc == 6)
- pr_cont("CALL (P%i)", poprnd);
- else if (prgfunc == 7)
- pr_cont("CALL (PC + P%i)", poprnd);
- else if (prgfunc == 8)
- pr_cont("JUMP (PC + P%i", poprnd);
- else if (prgfunc == 9)
- pr_cont("RAISE %i", poprnd);
- else if (prgfunc == 10)
- pr_cont("EXCPT %i", poprnd);
- else
- pr_cont("0x%04x", opcode);
-
-}
-
-#define BRCC_opcode 0x1000
-#define BRCC_offset_bits 0
-#define BRCC_offset_mask 0x3ff
-#define BRCC_B_bits 10
-#define BRCC_B_mask 0x1
-#define BRCC_T_bits 11
-#define BRCC_T_mask 0x1
-#define BRCC_code_bits 12
-#define BRCC_code_mask 0xf
-
-static void decode_BRCC_0(unsigned int opcode)
-{
- int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
- int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
-
- pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
-}
-
-#define CALLa_opcode 0xe2000000
-#define CALLa_addr_bits 0
-#define CALLa_addr_mask 0xffffff
-#define CALLa_S_bits 24
-#define CALLa_S_mask 0x1
-#define CALLa_code_bits 25
-#define CALLa_code_mask 0x7f
-
-static void decode_CALLa_0(unsigned int opcode)
-{
- int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
-
- if (S)
- pr_cont("CALL pcrel");
- else
- pr_cont("JUMP.L");
-}
-
-#define LoopSetup_opcode 0xe0800000
-#define LoopSetup_eoffset_bits 0
-#define LoopSetup_eoffset_mask 0x3ff
-#define LoopSetup_dontcare_bits 10
-#define LoopSetup_dontcare_mask 0x3
-#define LoopSetup_reg_bits 12
-#define LoopSetup_reg_mask 0xf
-#define LoopSetup_soffset_bits 16
-#define LoopSetup_soffset_mask 0xf
-#define LoopSetup_c_bits 20
-#define LoopSetup_c_mask 0x1
-#define LoopSetup_rop_bits 21
-#define LoopSetup_rop_mask 0x3
-#define LoopSetup_code_bits 23
-#define LoopSetup_code_mask 0x1ff
-
-static void decode_LoopSetup_0(unsigned int opcode)
-{
- int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
- int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
- int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
-
- pr_cont("LSETUP <> LC%i", c);
- if ((rop & 1) == 1)
- pr_cont("= P%i", reg);
- if ((rop & 2) == 2)
- pr_cont(" >> 0x1");
-}
-
-#define DspLDST_opcode 0x9c00
-#define DspLDST_reg_bits 0
-#define DspLDST_reg_mask 0x7
-#define DspLDST_i_bits 3
-#define DspLDST_i_mask 0x3
-#define DspLDST_m_bits 5
-#define DspLDST_m_mask 0x3
-#define DspLDST_aop_bits 7
-#define DspLDST_aop_mask 0x3
-#define DspLDST_W_bits 9
-#define DspLDST_W_mask 0x1
-#define DspLDST_code_bits 10
-#define DspLDST_code_mask 0x3f
-
-static void decode_dspLDST_0(unsigned int opcode)
-{
- int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
- int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
- int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
- int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
- int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
-
- if (W == 0) {
- pr_cont("R%i", reg);
- switch (m) {
- case 0:
- pr_cont(" = ");
- break;
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-
- pr_cont("[ I%i", i);
-
- switch (aop) {
- case 0:
- pr_cont("++ ]");
- break;
- case 1:
- pr_cont("-- ]");
- break;
- }
-
- if (W == 1) {
- pr_cont(" = R%i", reg);
- switch (m) {
- case 1:
- pr_cont(".L = ");
- break;
- case 2:
- pr_cont(".W = ");
- break;
- }
- }
-}
-
-#define LDST_opcode 0x9000
-#define LDST_reg_bits 0
-#define LDST_reg_mask 0x7
-#define LDST_ptr_bits 3
-#define LDST_ptr_mask 0x7
-#define LDST_Z_bits 6
-#define LDST_Z_mask 0x1
-#define LDST_aop_bits 7
-#define LDST_aop_mask 0x3
-#define LDST_W_bits 9
-#define LDST_W_mask 0x1
-#define LDST_sz_bits 10
-#define LDST_sz_mask 0x3
-#define LDST_code_bits 12
-#define LDST_code_mask 0xf
-
-static void decode_LDST_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
- int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
- int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
- int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
- int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
- int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- switch (sz) {
- case 1:
- pr_cont("W");
- break;
- case 2:
- pr_cont("B");
- break;
- }
-
- pr_cont("[P%i", ptr);
-
- switch (aop) {
- case 0:
- pr_cont("++");
- break;
- case 1:
- pr_cont("--");
- break;
- }
- pr_cont("]");
-
- if (W == 1)
- pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
- if (sz) {
- if (Z)
- pr_cont(" (X)");
- else
- pr_cont(" (Z)");
- }
-}
-
-#define LDSTii_opcode 0xa000
-#define LDSTii_reg_bit 0
-#define LDSTii_reg_mask 0x7
-#define LDSTii_ptr_bit 3
-#define LDSTii_ptr_mask 0x7
-#define LDSTii_offset_bit 6
-#define LDSTii_offset_mask 0xf
-#define LDSTii_op_bit 10
-#define LDSTii_op_mask 0x3
-#define LDSTii_W_bit 12
-#define LDSTii_W_mask 0x1
-#define LDSTii_code_bit 13
-#define LDSTii_code_mask 0x7
-
-static void decode_LDSTii_0(unsigned int opcode)
-{
- int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
- int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
- int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
- int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
- int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
-
- if (W == 0) {
- pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
- op == 1 || op == 2 ? "" : "W", ptr, offset);
- if (op == 2)
- pr_cont("(Z)");
- if (op == 3)
- pr_cont("(X)");
- } else {
- pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
- offset, op == 3 ? "P" : "R", reg);
- }
-}
-
-#define LDSTidxI_opcode 0xe4000000
-#define LDSTidxI_offset_bits 0
-#define LDSTidxI_offset_mask 0xffff
-#define LDSTidxI_reg_bits 16
-#define LDSTidxI_reg_mask 0x7
-#define LDSTidxI_ptr_bits 19
-#define LDSTidxI_ptr_mask 0x7
-#define LDSTidxI_sz_bits 22
-#define LDSTidxI_sz_mask 0x3
-#define LDSTidxI_Z_bits 24
-#define LDSTidxI_Z_mask 0x1
-#define LDSTidxI_W_bits 25
-#define LDSTidxI_W_mask 0x1
-#define LDSTidxI_code_bits 26
-#define LDSTidxI_code_mask 0x3f
-
-static void decode_LDSTidxI_0(unsigned int opcode)
-{
- int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
- int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
- int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
- int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
- int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
- int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
-
- if (W == 0)
- pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
-
- if (sz == 1)
- pr_cont("W");
- if (sz == 2)
- pr_cont("B");
-
- pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
- (offset & 0x1f) << 2);
-
- if (W == 0 && sz != 0) {
- if (Z)
- pr_cont("(X)");
- else
- pr_cont("(Z)");
- }
-
- if (W == 1)
- pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
-
-}
-
-static void decode_opcode(unsigned int opcode)
-{
-#ifdef CONFIG_BUG
- if (opcode == BFIN_BUG_OPCODE)
- pr_cont("BUG");
- else
-#endif
- if ((opcode & 0xffffff00) == ProgCtrl_opcode)
- decode_ProgCtrl_0(opcode);
- else if ((opcode & 0xfffff000) == BRCC_opcode)
- decode_BRCC_0(opcode);
- else if ((opcode & 0xfffff000) == 0x2000)
- pr_cont("JUMP.S");
- else if ((opcode & 0xfe000000) == CALLa_opcode)
- decode_CALLa_0(opcode);
- else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
- decode_LoopSetup_0(opcode);
- else if ((opcode & 0xfffffc00) == DspLDST_opcode)
- decode_dspLDST_0(opcode);
- else if ((opcode & 0xfffff000) == LDST_opcode)
- decode_LDST_0(opcode);
- else if ((opcode & 0xffffe000) == LDSTii_opcode)
- decode_LDSTii_0(opcode);
- else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
- decode_LDSTidxI_0(opcode);
- else if (opcode & 0xffff0000)
- pr_cont("0x%08x", opcode);
- else
- pr_cont("0x%04x", opcode);
-}
-
-#define BIT_MULTI_INS 0x08000000
-static void decode_instruction(unsigned short *address)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, address))
- return;
-
- decode_opcode(opcode);
-
- /* If things are a 32-bit instruction, it has the possibility of being
- * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
- * This test collidates with the unlink instruction, so disallow that
- */
- if ((opcode & 0xc0000000) == 0xc0000000 &&
- (opcode & BIT_MULTI_INS) &&
- (opcode & 0xe8000000) != 0xe8000000) {
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 2))
- return;
- decode_opcode(opcode);
- pr_cont(" || ");
- if (!get_instruction(&opcode, address + 3))
- return;
- decode_opcode(opcode);
- }
-}
-#endif
-
-void dump_bfin_trace_buffer(void)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int tflags, i = 0, fault = 0;
- char buf[150];
- unsigned short *addr;
- unsigned int cpu = raw_smp_processor_id();
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- int j, index;
-#endif
-
- trace_buffer_save(tflags);
-
- pr_notice("Hardware Trace:\n");
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
-#endif
-
- if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
- for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice("%4i Target : %s\n", i, buf);
- /* Normally, the faulting instruction doesn't go into
- * the trace buffer, (since it doesn't commit), so
- * we print out the fault address here
- */
- if (!fault && addr == ((unsigned short *)evt_ivhw)) {
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- fault = 1;
- continue;
- }
- if (!fault && addr == (unsigned short *)trap &&
- (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice(" FAULT : %s ", buf);
- decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
- pr_cont("\n");
- fault = 1;
- }
- addr = (unsigned short *)bfin_read_TBUF();
- decode_address(buf, (unsigned long)addr);
- pr_notice(" Source : %s ", buf);
- decode_instruction(addr);
- pr_cont("\n");
- }
- }
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- if (trace_buff_offset)
- index = trace_buff_offset / 4;
- else
- index = EXPAND_LEN;
-
- j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
- while (j) {
- decode_address(buf, software_trace_buff[index]);
- pr_notice("%4i Target : %s\n", i, buf);
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- decode_address(buf, software_trace_buff[index]);
- pr_notice(" Source : %s ", buf);
- decode_instruction((unsigned short *)software_trace_buff[index]);
- pr_cont("\n");
- index -= 1;
- if (index < 0)
- index = EXPAND_LEN;
- j--;
- i++;
- }
-#endif
-
- trace_buffer_restore(tflags);
-#endif
-}
-EXPORT_SYMBOL(dump_bfin_trace_buffer);
-
-void dump_bfin_process(struct pt_regs *fp)
-{
- /* We should be able to look at fp->ipend, but we don't push it on the
- * stack all the time, so do this until we fix that */
- unsigned int context = bfin_read_IPEND();
-
- if (oops_in_progress)
- pr_emerg("Kernel OOPS in progress\n");
-
- if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
- pr_notice("HW Error context\n");
- else if (context & 0x0020)
- pr_notice("Deferred Exception context\n");
- else if (context & 0x3FC0)
- pr_notice("Interrupt context\n");
- else if (context & 0x4000)
- pr_notice("Deferred Interrupt context\n");
- else if (context & 0x8000)
- pr_notice("Kernel process context\n");
-
- /* Because we are crashing, and pointers could be bad, we check things
- * pretty closely before we use them
- */
- if ((unsigned long)current >= FIXED_CODE_START &&
- !((unsigned long)current & 0x3) && current->pid) {
- pr_notice("CURRENT PROCESS:\n");
- if (current->comm >= (char *)FIXED_CODE_START)
- pr_notice("COMM=%s PID=%d",
- current->comm, current->pid);
- else
- pr_notice("COMM= invalid");
-
- pr_cont(" CPU=%d\n", current_thread_info()->cpu);
- if (!((unsigned long)current->mm & 0x3) &&
- (unsigned long)current->mm >= FIXED_CODE_START) {
- pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
- (void *)current->mm->start_code,
- (void *)current->mm->end_code,
- (void *)current->mm->start_data,
- (void *)current->mm->end_data);
- pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
- (void *)current->mm->end_data,
- (void *)current->mm->brk,
- (void *)current->mm->start_stack);
- } else
- pr_notice("invalid mm\n");
- } else
- pr_notice("No Valid process in current context\n");
-}
-
-void dump_bfin_mem(struct pt_regs *fp)
-{
- unsigned short *addr, *erraddr, val = 0, err = 0;
- char sti = 0, buf[6];
-
- erraddr = (void *)fp->pc;
-
- pr_notice("return address: [0x%p]; contents of:", erraddr);
-
- for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
- addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
- addr++) {
- if (!((unsigned long)addr & 0xF))
- pr_notice("0x%p: ", addr);
-
- if (!get_mem16(&val, addr)) {
- val = 0;
- sprintf(buf, "????");
- } else
- sprintf(buf, "%04x", val);
-
- if (addr == erraddr) {
- pr_cont("[%s]", buf);
- err = val;
- } else
- pr_cont(" %s ", buf);
-
- /* Do any previous instructions turn on interrupts? */
- if (addr <= erraddr && /* in the past */
- ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
- val == 0x017b)) /* [SP++] = RETI */
- sti = 1;
- }
-
- pr_cont("\n");
-
- /* Hardware error interrupts can be deferred */
- if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
- oops_in_progress)){
- pr_notice("Looks like this was a deferred error - sorry\n");
-#ifndef CONFIG_DEBUG_HWERR
- pr_notice("The remaining message may be meaningless\n");
- pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
-#else
- /* If we are handling only one peripheral interrupt
- * and current mm and pid are valid, and the last error
- * was in that user space process's text area
- * print it out - because that is where the problem exists
- */
- if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
- (current->pid && current->mm)) {
- /* And the last RETI points to the current userspace context */
- if ((fp + 1)->pc >= current->mm->start_code &&
- (fp + 1)->pc <= current->mm->end_code) {
- pr_notice("It might be better to look around here :\n");
- pr_notice("-------------------------------------------\n");
- show_regs(fp + 1);
- pr_notice("-------------------------------------------\n");
- }
- }
-#endif
- }
-}
-
-void show_regs(struct pt_regs *fp)
-{
- char buf[150];
- struct irqaction *action;
- unsigned int i;
- unsigned long flags = 0;
- unsigned int cpu = raw_smp_processor_id();
- unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
-
- pr_notice("\n");
- show_regs_print_info(KERN_NOTICE);
-
- if (CPUID != bfin_cpuid())
- pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
- "but running on:0x%04x (Rev %d)\n",
- CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
-
- pr_notice("ADSP-%s-0.%d",
- CPU, bfin_compiled_revid());
-
- if (bfin_compiled_revid() != bfin_revid())
- pr_cont("(Detected 0.%d)", bfin_revid());
-
- pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
- get_cclk()/1000000, get_sclk()/1000000,
-#ifdef CONFIG_MPU
- "mpu on"
-#else
- "mpu off"
-#endif
- );
-
- pr_notice("%s", linux_banner);
-
- pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
- pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
- (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
- if (fp->ipend & EVT_IRPTEN)
- pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
- EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
- pr_notice(" Peripheral interrupts masked off\n");
- if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
- pr_notice(" Kernel interrupts masked off\n");
- if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
- pr_notice(" HWERRCAUSE: 0x%lx\n",
- (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
-#ifdef EBIU_ERRMST
- /* If the error was from the EBIU, print it out */
- if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
- pr_notice(" EBIU Error Reason : 0x%04x\n",
- bfin_read_EBIU_ERRMST());
- pr_notice(" EBIU Error Address : 0x%08x\n",
- bfin_read_EBIU_ERRADD());
- }
-#endif
- }
- pr_notice(" EXCAUSE : 0x%lx\n",
- fp->seqstat & SEQSTAT_EXCAUSE);
- for (i = 2; i <= 15 ; i++) {
- if (fp->ipend & (1 << i)) {
- if (i != 4) {
- decode_address(buf, bfin_read32(EVT0 + 4*i));
- pr_notice(" physical IVG%i asserted : %s\n", i, buf);
- } else
- pr_notice(" interrupts disabled\n");
- }
- }
-
- /* if no interrupts are going off, don't print this out */
- if (fp->ipend & ~0x3F) {
- for (i = 0; i < (NR_IRQS - 1); i++) {
- struct irq_desc *desc = irq_to_desc(i);
- if (!in_atomic)
- raw_spin_lock_irqsave(&desc->lock, flags);
-
- action = desc->action;
- if (!action)
- goto unlock;
-
- decode_address(buf, (unsigned int)action->handler);
- pr_notice(" logical irq %3d mapped : %s", i, buf);
- for (action = action->next; action; action = action->next) {
- decode_address(buf, (unsigned int)action->handler);
- pr_cont(", %s", buf);
- }
- pr_cont("\n");
-unlock:
- if (!in_atomic)
- raw_spin_unlock_irqrestore(&desc->lock, flags);
- }
- }
-
- decode_address(buf, fp->rete);
- pr_notice(" RETE: %s\n", buf);
- decode_address(buf, fp->retn);
- pr_notice(" RETN: %s\n", buf);
- decode_address(buf, fp->retx);
- pr_notice(" RETX: %s\n", buf);
- decode_address(buf, fp->rets);
- pr_notice(" RETS: %s\n", buf);
- decode_address(buf, fp->pc);
- pr_notice(" PC : %s\n", buf);
-
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
- (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
- decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
- pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
- pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
- }
-
- pr_notice("PROCESSOR STATE:\n");
- pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
- fp->r0, fp->r1, fp->r2, fp->r3);
- pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
- fp->r4, fp->r5, fp->r6, fp->r7);
- pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
- fp->p0, fp->p1, fp->p2, fp->p3);
- pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
- fp->p4, fp->p5, fp->fp, (long)fp);
- pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
- fp->lb0, fp->lt0, fp->lc0);
- pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
- fp->lb1, fp->lt1, fp->lc1);
- pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
- fp->b0, fp->l0, fp->m0, fp->i0);
- pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
- fp->b1, fp->l1, fp->m1, fp->i1);
- pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
- fp->b2, fp->l2, fp->m2, fp->i2);
- pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
- fp->b3, fp->l3, fp->m3, fp->i3);
- pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
- fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
- pr_notice("USP : %08lx ASTAT: %08lx\n",
- rdusp(), fp->astat);
-
- pr_notice("\n");
-}
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
deleted file mode 100644
index a323a40a46e9..000000000000
--- a/arch/blackfin/kernel/traps.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- * Main exception handling logic.
- *
- * Copyright 2004-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <linux/bug.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <asm/traps.h>
-#include <asm/cplb.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <linux/irq.h>
-#include <asm/trace.h>
-#include <asm/fixed_code.h>
-#include <asm/pseudo_instructions.h>
-#include <asm/pda.h>
-#include <asm/asm-offsets.h>
-
-#ifdef CONFIG_KGDB
-# include <linux/kgdb.h>
-
-# define CHK_DEBUGGER_TRAP() \
- do { \
- kgdb_handle_exception(trapnr, sig, info.si_code, fp); \
- } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() \
- do { \
- if (kgdb_connected) \
- CHK_DEBUGGER_TRAP(); \
- } while (0)
-#else
-# define CHK_DEBUGGER_TRAP() do { } while (0)
-# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
-#endif
-
-
-#ifdef CONFIG_DEBUG_VERBOSE
-#define verbose_printk(fmt, arg...) \
- printk(fmt, ##arg)
-#else
-#define verbose_printk(fmt, arg...) \
- ({ if (0) printk(fmt, ##arg); 0; })
-#endif
-
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
-u32 last_seqstat;
-#ifdef CONFIG_DEBUG_MMRS_MODULE
-EXPORT_SYMBOL(last_seqstat);
-#endif
-#endif
-
-/* Initiate the event table handler */
-void __init trap_init(void)
-{
- CSYNC();
- bfin_write_EVT3(trap);
- CSYNC();
-}
-
-static int kernel_mode_regs(struct pt_regs *regs)
-{
- return regs->ipend & 0xffc0;
-}
-
-asmlinkage notrace void trap_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- int opcode;
-#endif
- unsigned int cpu = raw_smp_processor_id();
- const char *strerror = NULL;
- int sig = 0;
- siginfo_t info;
- unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
-
- trace_buffer_save(j);
-#if defined(CONFIG_DEBUG_MMRS) || defined(CONFIG_DEBUG_MMRS_MODULE)
- last_seqstat = (u32)fp->seqstat;
-#endif
-
- /* Important - be very careful dereferncing pointers - will lead to
- * double faults if the stack has become corrupt
- */
-
- /* trap_c() will be called for exceptions. During exceptions
- * processing, the pc value should be set with retx value.
- * With this change we can cleanup some code in signal.c- TODO
- */
- fp->orig_pc = fp->retx;
- /* printk("exception: 0x%x, ipend=%x, reti=%x, retx=%x\n",
- trapnr, fp->ipend, fp->pc, fp->retx); */
-
- /* send the appropriate signal to the user program */
- switch (trapnr) {
-
- /* This table works in conjunction with the one in ./mach-common/entry.S
- * Some exceptions are handled there (in assembly, in exception space)
- * Some are handled here, (in C, in interrupt space)
- * Some, like CPLB, are handled in both, where the normal path is
- * handled in assembly/exception space, and the error path is handled
- * here
- */
-
- /* 0x00 - Linux Syscall, getting here is an error */
- /* 0x01 - userspace gdb breakpoint, handled here */
- case VEC_EXCPT01:
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a breakpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x03 - User Defined, userspace stack overflow */
- case VEC_EXCPT03:
- info.si_code = SEGV_STACKFLOW;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x03(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x02 - KGDB initial connection and break signal trap */
- case VEC_EXCPT02:
-#ifdef CONFIG_KGDB
- info.si_code = TRAP_ILLTRAP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP();
- goto traps_done;
-#endif
- /* 0x04 - User Defined */
- /* 0x05 - User Defined */
- /* 0x06 - User Defined */
- /* 0x07 - User Defined */
- /* 0x08 - User Defined */
- /* 0x09 - User Defined */
- /* 0x0A - User Defined */
- /* 0x0B - User Defined */
- /* 0x0C - User Defined */
- /* 0x0D - User Defined */
- /* 0x0E - User Defined */
- /* 0x0F - User Defined */
- /* If we got here, it is most likely that someone was trying to use a
- * custom exception handler, and it is not actually installed properly
- */
- case VEC_EXCPT04 ... VEC_EXCPT15:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x04(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x10 HW Single step, handled here */
- case VEC_STEP:
- info.si_code = TRAP_STEP;
- sig = SIGTRAP;
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a single step in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
- /* 0x11 - Trace Buffer Full, handled here */
- case VEC_OVFLOW:
- info.si_code = TRAP_TRACEFLOW;
- sig = SIGTRAP;
- strerror = KERN_NOTICE EXC_0x11(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x12 - Reserved, Caught by default */
- /* 0x13 - Reserved, Caught by default */
- /* 0x14 - Reserved, Caught by default */
- /* 0x15 - Reserved, Caught by default */
- /* 0x16 - Reserved, Caught by default */
- /* 0x17 - Reserved, Caught by default */
- /* 0x18 - Reserved, Caught by default */
- /* 0x19 - Reserved, Caught by default */
- /* 0x1A - Reserved, Caught by default */
- /* 0x1B - Reserved, Caught by default */
- /* 0x1C - Reserved, Caught by default */
- /* 0x1D - Reserved, Caught by default */
- /* 0x1E - Reserved, Caught by default */
- /* 0x1F - Reserved, Caught by default */
- /* 0x20 - Reserved, Caught by default */
- /* 0x21 - Undefined Instruction, handled here */
- case VEC_UNDEF_I:
-#ifdef CONFIG_BUG
- if (kernel_mode_regs(fp)) {
- switch (report_bug(fp->pc, fp)) {
- case BUG_TRAP_TYPE_NONE:
- break;
- case BUG_TRAP_TYPE_WARN:
- dump_bfin_trace_buffer();
- fp->pc += 2;
- goto traps_done;
- case BUG_TRAP_TYPE_BUG:
- /* call to panic() will dump trace, and it is
- * off at this point, so it won't be clobbered
- */
- panic("BUG()");
- }
- }
-#endif
-#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
- /*
- * Support for the fake instructions, if the instruction fails,
- * then just execute a illegal opcode failure (like normal).
- * Don't support these instructions inside the kernel
- */
- if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) {
- if (execute_pseudodbg_assert(fp, opcode))
- goto traps_done;
- if (execute_pseudodbg(fp, opcode))
- goto traps_done;
- }
-#endif
- info.si_code = ILL_ILLOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x22 - Illegal Instruction Combination, handled here */
- case VEC_ILGAL_I:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x22(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x23 - Data CPLB protection violation, handled here */
- case VEC_CPLB_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGSEGV;
- strerror = KERN_NOTICE EXC_0x23(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x24 - Data access misaligned, handled here */
- case VEC_MISALI_D:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x24(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x25 - Unrecoverable Event, handled here */
- case VEC_UNCOV:
- info.si_code = ILL_ILLEXCPT;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x25(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
- error case is handled here */
- case VEC_CPLB_M:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x26(KERN_NOTICE);
- break;
- /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
- case VEC_CPLB_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].dcplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "NULL pointer access\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x27(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x28 - Emulation Watchpoint, handled here */
- case VEC_WATCH:
- info.si_code = TRAP_WATCHPT;
- sig = SIGTRAP;
- pr_debug(EXC_0x28(KERN_DEBUG));
- CHK_DEBUGGER_TRAP_MAYBE();
- /* Check if this is a watchpoint in kernel space */
- if (kernel_mode_regs(fp))
- goto traps_done;
- else
- break;
-#ifdef CONFIG_BF535
- /* 0x29 - Instruction fetch access error (535 only) */
- case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */
- info.si_code = BUS_OPFETCH;
- sig = SIGBUS;
- strerror = KERN_NOTICE "BF535: VEC_ISTRU_VL\n";
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
-#else
- /* 0x29 - Reserved, Caught by default */
-#endif
- /* 0x2A - Instruction fetch misaligned, handled here */
- case VEC_MISALI_I:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2A(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2B - Instruction CPLB protection violation, handled here */
- case VEC_CPLB_I_VL:
- info.si_code = ILL_CPLB_VI;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2B(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
- case VEC_CPLB_I_M:
- info.si_code = ILL_CPLB_MISS;
- sig = SIGBUS;
- strerror = KERN_NOTICE EXC_0x2C(KERN_NOTICE);
- break;
- /* 0x2D - Instruction CPLB Multiple Hits, handled here */
- case VEC_CPLB_I_MHIT:
- info.si_code = ILL_CPLB_MULHIT;
- sig = SIGSEGV;
-#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
- if (cpu_pda[cpu].icplb_fault_addr < FIXED_CODE_START)
- strerror = KERN_NOTICE "Jump to NULL address\n";
- else
-#endif
- strerror = KERN_NOTICE EXC_0x2D(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2E - Illegal use of Supervisor Resource, handled here */
- case VEC_ILL_RES:
- info.si_code = ILL_PRVOPC;
- sig = SIGILL;
- strerror = KERN_NOTICE EXC_0x2E(KERN_NOTICE);
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /* 0x2F - Reserved, Caught by default */
- /* 0x30 - Reserved, Caught by default */
- /* 0x31 - Reserved, Caught by default */
- /* 0x32 - Reserved, Caught by default */
- /* 0x33 - Reserved, Caught by default */
- /* 0x34 - Reserved, Caught by default */
- /* 0x35 - Reserved, Caught by default */
- /* 0x36 - Reserved, Caught by default */
- /* 0x37 - Reserved, Caught by default */
- /* 0x38 - Reserved, Caught by default */
- /* 0x39 - Reserved, Caught by default */
- /* 0x3A - Reserved, Caught by default */
- /* 0x3B - Reserved, Caught by default */
- /* 0x3C - Reserved, Caught by default */
- /* 0x3D - Reserved, Caught by default */
- /* 0x3E - Reserved, Caught by default */
- /* 0x3F - Reserved, Caught by default */
- case VEC_HWERR:
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- switch (fp->seqstat & SEQSTAT_HWERRCAUSE) {
- /* System MMR Error */
- case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
- info.si_code = BUS_ADRALN;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x2(KERN_NOTICE);
- break;
- /* External Memory Addressing Error */
- case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
- if (ANOMALY_05000310) {
- static unsigned long anomaly_rets;
-
- if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * A false hardware error will happen while fetching at
- * the L1 instruction SRAM boundary. Ignore it.
- */
- anomaly_rets = fp->rets;
- goto traps_done;
- } else if (fp->rets == anomaly_rets) {
- /*
- * While boundary code returns to a function, at the ret
- * point, a new false hardware error might occur too based
- * on tests. Ignore it too.
- */
- goto traps_done;
- } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) &&
- (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) {
- /*
- * If boundary code calls a function, at the entry point,
- * a new false hardware error maybe happen based on tests.
- * Ignore it too.
- */
- goto traps_done;
- } else
- anomaly_rets = 0;
- }
-
- info.si_code = BUS_ADRERR;
- sig = SIGBUS;
- strerror = KERN_NOTICE HWC_x3(KERN_NOTICE);
- break;
- /* Performance Monitor Overflow */
- case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
- strerror = KERN_NOTICE HWC_x12(KERN_NOTICE);
- break;
- /* RAISE 5 instruction */
- case (SEQSTAT_HWERRCAUSE_RAISE_5):
- printk(KERN_NOTICE HWC_x18(KERN_NOTICE));
- break;
- default: /* Reserved */
- printk(KERN_NOTICE HWC_default(KERN_NOTICE));
- break;
- }
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- /*
- * We should be handling all known exception types above,
- * if we get here we hit a reserved one, so panic
- */
- default:
- info.si_code = ILL_ILLPARAOP;
- sig = SIGILL;
- verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
- (fp->seqstat & SEQSTAT_EXCAUSE));
- CHK_DEBUGGER_TRAP_MAYBE();
- break;
- }
-
- BUG_ON(sig == 0);
-
- /* If the fault was caused by a kernel thread, or interrupt handler
- * we will kernel panic, so the system reboots.
- */
- if (kernel_mode_regs(fp) || (current && !current->mm)) {
- console_verbose();
- oops_in_progress = 1;
- }
-
- if (sig != SIGTRAP) {
- if (strerror)
- verbose_printk(strerror);
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
-
- /* Print out the trace buffer if it makes sense */
-#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
- if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M)
- verbose_printk(KERN_NOTICE "No trace since you do not have "
- "CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n\n");
- else
-#endif
- dump_bfin_trace_buffer();
-
- if (oops_in_progress) {
- /* Dump the current kernel stack */
- verbose_printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
-#ifndef CONFIG_ACCESS_CHECK
- verbose_printk(KERN_EMERG "Please turn on "
- "CONFIG_ACCESS_CHECK\n");
-#endif
- panic("Kernel exception");
- } else {
-#ifdef CONFIG_DEBUG_VERBOSE
- unsigned long *stack;
- /* Dump the user space stack */
- stack = (unsigned long *)rdusp();
- verbose_printk(KERN_NOTICE "Userspace Stack\n");
- show_stack(NULL, stack);
-#endif
- }
- }
-
-#ifdef CONFIG_IPIPE
- if (!ipipe_trap_notify(fp->seqstat & 0x3f, fp))
-#endif
- {
- info.si_signo = sig;
- info.si_errno = 0;
- switch (trapnr) {
- case VEC_CPLB_VL:
- case VEC_MISALI_D:
- case VEC_CPLB_M:
- case VEC_CPLB_MHIT:
- info.si_addr = (void __user *)cpu_pda[cpu].dcplb_fault_addr;
- break;
- default:
- info.si_addr = (void __user *)fp->pc;
- break;
- }
- force_sig_info(sig, &info, current);
- }
-
- if ((ANOMALY_05000461 && trapnr == VEC_HWERR && !access_ok(VERIFY_READ, fp->pc, 8)) ||
- (ANOMALY_05000281 && trapnr == VEC_HWERR) ||
- (ANOMALY_05000189 && (trapnr == VEC_CPLB_I_VL || trapnr == VEC_CPLB_VL)))
- fp->pc = SAFE_USER_INSTRUCTION;
-
- traps_done:
- trace_buffer_restore(j);
-}
-
-asmlinkage void double_fault_c(struct pt_regs *fp)
-{
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
- int j;
- trace_buffer_save(j);
-#endif
-
- console_verbose();
- oops_in_progress = 1;
-#ifdef CONFIG_DEBUG_VERBOSE
- printk(KERN_EMERG "Double Fault\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
- if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
- unsigned int cpu = raw_smp_processor_id();
- char buf[150];
- decode_address(buf, cpu_pda[cpu].retx_doublefault);
- printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
- (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
- decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
- decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
-
- decode_address(buf, fp->retx);
- printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
- } else
-#endif
- {
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_bfin_trace_buffer();
- }
-#endif
- panic("Double Fault - unrecoverable event");
-
-}
-
-
-void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
-{
- switch (cplb_panic) {
- case CPLB_NO_UNLOCKED:
- printk(KERN_EMERG "All CPLBs are locked\n");
- break;
- case CPLB_PROT_VIOL:
- return;
- case CPLB_NO_ADDR_MATCH:
- return;
- case CPLB_UNKNOWN_ERR:
- printk(KERN_EMERG "Unknown CPLB Exception\n");
- break;
- }
-
- oops_in_progress = 1;
-
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- dump_stack();
- panic("Unrecoverable event");
-}
-
-#ifdef CONFIG_BUG
-int is_valid_bugaddr(unsigned long addr)
-{
- unsigned int opcode;
-
- if (!get_instruction(&opcode, (unsigned short *)addr))
- return 0;
-
- return opcode == BFIN_BUG_OPCODE;
-}
-#endif
-
-/* stub this out */
-#ifndef CONFIG_DEBUG_VERBOSE
-void show_regs(struct pt_regs *fp)
-{
-
-}
-#endif
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
deleted file mode 100644
index 334ef8139b35..000000000000
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/mem_map.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
-OUTPUT_FORMAT("elf32-bfin")
-ENTRY(__start)
-_jiffies = _jiffies_64;
-
-SECTIONS
-{
-#ifdef CONFIG_RAMKERNEL
- . = CONFIG_BOOT_LOAD;
-#else
- . = CONFIG_ROM_BASE;
-#endif
-
- /* Neither the text, ro_data or bss section need to be aligned
- * So pack them back to back
- */
- .text :
- {
- __text = .;
- _text = .;
- __stext = .;
- TEXT_TEXT
-#ifndef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- CPUIDLE_TEXT
- LOCK_TEXT
- IRQENTRY_TEXT
- SOFTIRQENTRY_TEXT
- KPROBES_TEXT
-#ifdef CONFIG_ROMKERNEL
- __sinittext = .;
- INIT_TEXT
- __einittext = .;
- EXIT_TEXT
-#endif
- *(.text.*)
- *(.fixup)
-
-#if !L1_CODE_LENGTH
- *(.l1.text)
-#endif
- __etext = .;
- }
-
- EXCEPTION_TABLE(4)
- NOTES
-
- /* Just in case the first read only is a 32-bit access */
- RO_DATA(4)
- __rodata_end = .;
-
-#ifdef CONFIG_ROMKERNEL
- . = CONFIG_BOOT_LOAD;
- .bss : AT(__rodata_end)
-#else
- .bss :
-#endif
- {
- . = ALIGN(4);
- ___bss_start = .;
- *(.bss .bss.*)
- *(COMMON)
-#if !L1_DATA_A_LENGTH
- *(.l1.bss)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.bss.B)
-#endif
- . = ALIGN(4);
- ___bss_stop = .;
- }
-
-#if defined(CONFIG_ROMKERNEL)
- .data : AT(LOADADDR(.bss) + SIZEOF(.bss))
-#else
- .data :
-#endif
- {
- __sdata = .;
- /* This gets done first, so the glob doesn't suck it in */
- CACHELINE_ALIGNED_DATA(32)
-
-#if !L1_DATA_A_LENGTH
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
- *(.l1.data)
-#endif
-#if !L1_DATA_B_LENGTH
- *(.l1.data.B)
-#endif
-#if !L2_LENGTH
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
- *(.l2.data)
-#endif
-
- DATA_DATA
- CONSTRUCTORS
-
- INIT_TASK_DATA(THREAD_SIZE)
-
- __edata = .;
- }
- __data_lma = LOADADDR(.data);
- __data_len = SIZEOF(.data);
-
- BUG_TABLE
-
- /* The init section should be last, so when we free it, it goes into
- * the general memory pool, and (hopefully) will decrease fragmentation
- * a tiny bit. The init section has a _requirement_ that it be
- * PAGE_SIZE aligned
- */
- . = ALIGN(PAGE_SIZE);
- ___init_begin = .;
-
-#ifdef CONFIG_RAMKERNEL
- INIT_TEXT_SECTION(PAGE_SIZE)
-
- /* We have to discard exit text and such at runtime, not link time, to
- * handle embedded cross-section references (alt instructions, bug
- * table, eh_frame, etc...). We need all of our .text up front and
- * .data after it for PCREL call issues.
- */
- .exit.text :
- {
- EXIT_TEXT
- }
-
- . = ALIGN(16);
- INIT_DATA_SECTION(16)
- PERCPU_SECTION(32)
-
- .exit.data :
- {
- EXIT_DATA
- }
-
- .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
-#else
- .init.data : AT(__data_lma + __data_len + 32)
- {
- __sinitdata = .;
- INIT_DATA
- INIT_SETUP(16)
- INIT_CALLS
- CON_INITCALL
- SECURITY_INITCALL
- INIT_RAM_FS
-
- . = ALIGN(PAGE_SIZE);
- ___per_cpu_load = .;
- PERCPU_INPUT(32)
-
- EXIT_DATA
- __einitdata = .;
- }
- __init_data_lma = LOADADDR(.init.data);
- __init_data_len = SIZEOF(.init.data);
- __init_data_end = .;
-
- .text_l1 L1_CODE_START : AT(__init_data_lma + __init_data_len)
-#endif
- {
- . = ALIGN(4);
- __stext_l1 = .;
- *(.l1.text.head)
- *(.l1.text)
-#ifdef CONFIG_SCHEDULE_L1
- SCHED_TEXT
-#endif
- . = ALIGN(4);
- __etext_l1 = .;
- }
- __text_l1_lma = LOADADDR(.text_l1);
- __text_l1_len = SIZEOF(.text_l1);
- ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
-
- .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
- {
- . = ALIGN(4);
- __sdata_l1 = .;
- *(.l1.data)
- __edata_l1 = .;
-
- . = ALIGN(32);
- *(.data_l1.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l1 = .;
- *(.l1.bss)
- . = ALIGN(4);
- __ebss_l1 = .;
- }
- __data_l1_lma = LOADADDR(.data_l1);
- __data_l1_len = SIZEOF(.data_l1);
- ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
-
- .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
- {
- . = ALIGN(4);
- __sdata_b_l1 = .;
- *(.l1.data.B)
- __edata_b_l1 = .;
-
- . = ALIGN(4);
- __sbss_b_l1 = .;
- *(.l1.bss.B)
- . = ALIGN(4);
- __ebss_b_l1 = .;
- }
- __data_b_l1_lma = LOADADDR(.data_b_l1);
- __data_b_l1_len = SIZEOF(.data_b_l1);
- ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
-
- .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
- {
- . = ALIGN(4);
- __stext_l2 = .;
- *(.l2.text)
- . = ALIGN(4);
- __etext_l2 = .;
-
- . = ALIGN(4);
- __sdata_l2 = .;
- *(.l2.data)
- __edata_l2 = .;
-
- . = ALIGN(32);
- *(.data_l2.cacheline_aligned)
-
- . = ALIGN(4);
- __sbss_l2 = .;
- *(.l2.bss)
- . = ALIGN(4);
- __ebss_l2 = .;
- }
- __l2_lma = LOADADDR(.text_data_l2);
- __l2_len = SIZEOF(.text_data_l2);
- ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
-
- /* Force trailing alignment of our init section so that when we
- * free our init memory, we don't leave behind a partial page.
- */
-#ifdef CONFIG_RAMKERNEL
- . = __l2_lma + __l2_len;
-#else
- . = __init_data_end;
-#endif
- . = ALIGN(PAGE_SIZE);
- ___init_end = .;
-
- __end =.;
-
- STABS_DEBUG
-
- DWARF_DEBUG
-
- DISCARDS
-}
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
deleted file mode 100644
index 74ddde0eb2e7..000000000000
--- a/arch/blackfin/lib/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/lib/Makefile
-#
-
-lib-y := \
- ashldi3.o ashrdi3.o lshrdi3.o \
- muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
- memcpy.o memset.o memcmp.o memchr.o memmove.o \
- strcmp.o strcpy.o strncmp.o strncpy.o \
- umulsi3_highpart.o smulsi3_highpart.o \
- ins.o outs.o
diff --git a/arch/blackfin/lib/ashldi3.c b/arch/blackfin/lib/ashldi3.c
deleted file mode 100644
index ab69d8768afc..000000000000
--- a/arch/blackfin/lib/ashldi3.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashldi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashldi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.low = 0;
- w.s.high = (USItype) uu.s.low << -bm;
- } else {
- USItype carries = (USItype) uu.s.low >> bm;
- w.s.low = (USItype) uu.s.low << b;
- w.s.high = ((USItype) uu.s.high << b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/ashrdi3.c b/arch/blackfin/lib/ashrdi3.c
deleted file mode 100644
index b5b351e82e10..000000000000
--- a/arch/blackfin/lib/ashrdi3.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __ashrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- /* w.s.high = 1..1 or 0..0 */
- w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
- w.s.low = uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S
deleted file mode 100644
index ef2cd99efb89..000000000000
--- a/arch/blackfin/lib/divsi3.S
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- *
- * 16 / 32 bit signed division.
- * Special cases :
- * 1) If(numerator == 0)
- * return 0
- * 2) If(denominator ==0)
- * return positive max = 0x7fffffff
- * 3) If(numerator == denominator)
- * return 1
- * 4) If(denominator ==1)
- * return numerator
- * 5) If(denominator == -1)
- * return -numerator
- *
- * Operand : R0 - Numerator (i)
- * R1 - Denominator (i)
- * R0 - Quotient (o)
- * Registers Used : R2-R7,P0-P2
- *
- */
-
-.global ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2;
-___divsi3 :
-
-
- R3 = R0 ^ R1;
- R0 = ABS R0;
-
- CC = V;
-
- r3 = rot r3 by -1;
- r1 = abs r1; /* now both positive, r3.30 means "negate result",
- ** r3.31 means overflow, add one to result
- */
- cc = r0 < r1;
- if cc jump .Lret_zero;
- r2 = r1 >> 15;
- cc = r2;
- if cc jump .Lidents;
- r2 = r1 << 16;
- cc = r2 <= r0;
- if cc jump .Lidents;
-
- DIVS(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
- DIVQ(R0, R1);
-
- R0 = R0.L (Z);
- r1 = r3 >> 31; /* add overflow issue back in */
- r0 = r0 + r1;
- r1 = -r0;
- cc = bittst(r3, 30);
- if cc r0 = r1;
- RTS;
-
-/* Can't use the primitives. Test common identities.
-** If the identity is true, return the value in R2.
-*/
-
-.Lidents:
- CC = R1 == 0; /* check for divide by zero */
- IF CC JUMP .Lident_return;
-
- CC = R0 == 0; /* check for division of zero */
- IF CC JUMP .Lzero_return;
-
- CC = R0 == R1; /* check for identical operands */
- IF CC JUMP .Lident_return;
-
- CC = R1 == 1; /* check for divide by 1 */
- IF CC JUMP .Lident_return;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- /* Identities haven't helped either.
- ** Perform the full division process.
- */
-
- P1 = 31; /* Set loop counter */
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
- R2 = -R1;
- [--SP] = R2;
- R2 = R0 << 1; /* R2 lsw of dividend */
- R6 = R0 ^ R1; /* Get sign */
- R5 = R6 >> 31; /* Shift sign to LSB */
-
- R0 = 0 ; /* Clear msw partial remainder */
- R2 = R2 | R5; /* Shift quotient bit */
- R6 = R0 ^ R1; /* Get new quotient bit */
-
- LSETUP(.Llst,.Llend) LC0 = P1; /* Setup loop */
-.Llst: R7 = R2 >> 31; /* record copy of carry from R2 */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R0 = R0 << 1 || R5 = [SP];
- R0 = R0 | R7; /* and add carry */
- CC = R6 < 0; /* Check quotient(AQ) */
- /* we might be subtracting divisor (AQ==0) */
- IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
- R0 = R0 + R5; /* do add or subtract, as indicated by AQ */
- R6 = R0 ^ R1; /* Generate next quotient bit */
- R5 = R6 >> 31;
- /* Assume AQ==1, shift in zero */
- BITTGL(R5,0); /* tweak AQ to be what we want to shift in */
-.Llend: R2 = R2 + R5; /* and then set shifted-in value to
- ** tweaked AQ.
- */
- r1 = r3 >> 31;
- r2 = r2 + r1;
- cc = bittst(r3,30);
- r0 = -r2;
- if !cc r0 = r2;
- SP += 4;
- (R7:5)= [SP++]; /* Pop registers R6-R7 */
- RTS;
-
-.Lident_return:
- CC = R1 == 0; /* check for divide by zero => 0x7fffffff */
- R2 = -1 (X);
- R2 >>= 1;
- IF CC JUMP .Ltrue_ident_return;
-
- CC = R0 == R1; /* check for identical operands => 1 */
- R2 = 1 (Z);
- IF CC JUMP .Ltrue_ident_return;
-
- R2 = R0; /* assume divide by 1 => numerator */
- /*FALLTHRU*/
-
-.Ltrue_ident_return:
- R0 = R2; /* Return an identity value */
- R2 = -R2;
- CC = bittst(R3,30);
- IF CC R0 = R2;
-.Lzero_return:
- RTS; /* ...including zero */
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_ident_return;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- r1 = r3 >> 31;
- r0 = r0 + r1;
- R2 = -R0; // negate result if necessary
- CC = bittst(R3,30);
- IF CC R0 = R2;
- RTS;
-
-.Lret_zero:
- R0 = 0;
- RTS;
-
-.size ___divsi3, .-___divsi3
diff --git a/arch/blackfin/lib/gcclib.h b/arch/blackfin/lib/gcclib.h
deleted file mode 100644
index 724f07f14f8d..000000000000
--- a/arch/blackfin/lib/gcclib.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define BITS_PER_UNIT 8
-#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
-
-typedef unsigned int UQItype __attribute__ ((mode(QI)));
-typedef int SItype __attribute__ ((mode(SI)));
-typedef unsigned int USItype __attribute__ ((mode(SI)));
-typedef int DItype __attribute__ ((mode(DI)));
-typedef int word_type __attribute__ ((mode(__word__)));
-typedef unsigned int UDItype __attribute__ ((mode(DI)));
-
-struct DIstruct {
- SItype low, high;
-};
-
-typedef union {
- struct DIstruct s;
- DItype ll;
-} DIunion;
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
deleted file mode 100644
index d59608deccc1..000000000000
--- a/arch/blackfin/lib/ins.S
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.align 2
-
-#ifdef CONFIG_IPIPE
-# define DO_CLI \
- [--sp] = rets; \
- [--sp] = (P5:0); \
- sp += -12; \
- call ___ipipe_disable_root_irqs_hw; \
- sp += 12; \
- (P5:0) = [sp++];
-# define CLI_INNER_NOP
-#else
-# define DO_CLI cli R3;
-# define CLI_INNER_NOP nop; nop; nop;
-#endif
-
-#ifdef CONFIG_IPIPE
-# define DO_STI \
- sp += -12; \
- call ___ipipe_enable_root_irqs_hw; \
- sp += 12; \
-2: rets = [sp++];
-#else
-# define DO_STI 2: sti R3;
-#endif
-
-#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
-# define CLI_OUTER DO_CLI;
-# define STI_OUTER DO_STI;
-# define CLI_INNER 1:
-# if ANOMALY_05000416
-# define STI_INNER nop; 2: nop;
-# else
-# define STI_INNER 2:
-# endif
-#else
-# define CLI_OUTER
-# define STI_OUTER
-# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
-# define STI_INNER DO_STI;
-#endif
-
-/*
- * Reads on the Blackfin are speculative. In Blackfin terms, this means they
- * can be interrupted at any time (even after they have been issued on to the
- * external bus), and re-issued after the interrupt occurs.
- *
- * If a FIFO is sitting on the end of the read, it will see two reads,
- * when the core only sees one. The FIFO receives the read which is cancelled,
- * and not delivered to the core.
- *
- * To solve this, interrupts are turned off before reads occur to I/O space.
- * There are 3 versions of all these functions
- * - turns interrupts off every read (higher overhead, but lower latency)
- * - turns interrupts off every loop (low overhead, but longer latency)
- * - DMA version, which do not suffer from this issue. DMA versions have
- * different name (prefixed by dma_ ), and are located in
- * ../kernel/bfin_dma.c
- * Using the dma related functions are recommended for transferring large
- * buffers in/out of FIFOs.
- */
-
-#define COMMON_INS(func, ops) \
-ENTRY(_ins##func) \
- P0 = R0; /* P0 = port */ \
- CLI_OUTER; /* 3 instructions before first read access */ \
- P1 = R1; /* P1 = address */ \
- P2 = R2; /* P2 = count */ \
- SSYNC; \
- \
- LSETUP(1f, 2f) LC0 = P2; \
- CLI_INNER; \
- ops; \
- STI_INNER; \
- \
- STI_OUTER; \
- RTS; \
-ENDPROC(_ins##func)
-
-COMMON_INS(l, \
- R0 = [P0]; \
- [P1++] = R0; \
-)
-
-COMMON_INS(w, \
- R0 = W[P0]; \
- W[P1++] = R0; \
-)
-
-COMMON_INS(w_8, \
- R0 = W[P0]; \
- B[P1++] = R0; \
- R0 = R0 >> 8; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(b, \
- R0 = B[P0]; \
- B[P1++] = R0; \
-)
-
-COMMON_INS(l_16, \
- R0 = [P0]; \
- W[P1++] = R0; \
- R0 = R0 >> 16; \
- W[P1++] = R0; \
-)
diff --git a/arch/blackfin/lib/lshrdi3.c b/arch/blackfin/lib/lshrdi3.c
deleted file mode 100644
index 53f1741047e5..000000000000
--- a/arch/blackfin/lib/lshrdi3.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include "gcclib.h"
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-DItype __lshrdi3(DItype u, word_type b)__attribute__((l1_text));
-#endif
-
-DItype __lshrdi3(DItype u, word_type b)
-{
- DIunion w;
- word_type bm;
- DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.high = 0;
- w.s.low = (USItype) uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = (USItype) uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/blackfin/lib/memchr.S b/arch/blackfin/lib/memchr.S
deleted file mode 100644
index bcfc8a14c3f2..000000000000
--- a/arch/blackfin/lib/memchr.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memchr(const void *s, int c, size_t n);
- * R0 = address (s)
- * R1 = sought byte (c)
- * R2 = count (n)
- *
- * Returns pointer to located character.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memchr)
- P0 = R0; /* P0 = address */
- P2 = R2; /* P2 = count */
- R1 = R1.B(Z);
- CC = R2 == 0;
- IF CC JUMP .Lfailed;
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-
-.Lbyte_loop_s:
- R3 = B[P0++](Z);
- CC = R3 == R1;
- IF CC JUMP .Lfound;
-.Lbyte_loop_e:
- NOP;
-
-.Lfailed:
- R0=0;
- RTS;
-
-.Lfound:
- R0 = P0;
- R0 += -1;
- RTS;
-
-ENDPROC(_memchr)
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
deleted file mode 100644
index 2e1c9477f2f7..000000000000
--- a/arch/blackfin/lib/memcmp.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* int memcmp(const void *s1, const void *s2, size_t n);
- * R0 = First Address (s1)
- * R1 = Second Address (s2)
- * R2 = count (n)
- *
- * Favours word aligned data.
- */
-
-.text
-
-.align 2
-
-ENTRY(_memcmp)
- I1 = P3;
- P0 = R0; /* P0 = s1 address */
- P3 = R1; /* P3 = s2 Address */
- P2 = R2 ; /* P2 = count */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- I0 = R1; /* s2 */
- R1 = R1 | R0; /* OR addresses together */
- R1 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero. */
- IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */
-
- P1 = P2 >> 2; /* count = n/4 */
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
-
- LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
-.Lquad_loop_s:
-#if ANOMALY_05000202
- R0 = [P0++];
- R1 = [I0++];
-#else
- MNOP || R0 = [P0++] || R1 = [I0++];
-#endif
- CC = R0 == R1;
- IF !CC JUMP .Lquad_different;
-.Lquad_loop_e:
- NOP;
-
- P3 = I0; /* s2 */
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely*/
-
-.Lbytes:
- LSETUP (.Lbyte_loop_s, .Lbyte_loop_e) LC0=P2;
-.Lbyte_loop_s:
- R1 = B[P3++](Z); /* *s2 */
- R0 = B[P0++](Z); /* *s1 */
- CC = R0 == R1;
- IF !CC JUMP .Ldifferent;
-.Lbyte_loop_e:
- NOP;
-
-.Ldifferent:
- R0 = R0 - R1;
- P3 = I1;
- RTS;
-
-.Lquad_different:
- /* We've read two quads which don't match.
- * Can't just compare them, because we're
- * a little-endian machine, so the MSBs of
- * the regs occur at later addresses in the
- * string.
- * Arrange to re-read those two quads again,
- * byte-by-byte.
- */
- P0 += -4; /* back up to the start of the */
- P3 = I0; /* quads, and increase the*/
- P2 += 4; /* remainder count*/
- P3 += -4;
- JUMP .Lbytes;
-
-.Lfinished:
- R0 = 0;
- P3 = I1;
- RTS;
-
-ENDPROC(_memcmp)
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
deleted file mode 100644
index 53cb3698ab33..000000000000
--- a/arch/blackfin/lib/memcpy.S
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * internal version of memcpy(), issued by the compiler to copy blocks of
- * data around. This is really memmove() - it has to be able to deal with
- * possible overlaps, because that ambiguity is when the compiler gives up
- * and calls a function. We have our own, internal version so that we get
- * something we trust, even if the user has redefined the normal symbol.
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *memcpy(void *dest, const void *src, size_t n);
- * R0 = To Address (dest) (leave unchanged to form result)
- * R1 = From Address (src)
- * R2 = count
- *
- * Note: Favours word alignment
- */
-
-#ifdef CONFIG_MEMCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_memcpy)
- CC = R2 <= 0; /* length not positive? */
- IF CC JUMP .L_P1L2147483647; /* Nothing to do */
-
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
- P2 = R2 ; /* length */
-
- /* check for overlapping data */
- CC = R1 < R0; /* src < dst */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 < R3; /* and dst < src+len */
- IF CC JUMP .Lhas_overlap;
-
-.Lno_overlap:
- /* Check for aligned data.*/
-
- R3 = R1 | R0;
- R1 = 0x3;
- R3 = R3 & R1;
- CC = R3; /* low bits set on either address? */
- IF CC JUMP .Lnot_aligned;
-
- /* Both addresses are word-aligned, so we can copy
- at least part of the data using word copies.*/
- P2 = P2 >> 2;
- CC = P2 <= 2;
- IF !CC JUMP .Lmore_than_seven;
- /* less than eight bytes... */
- P2 = R2;
- LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
-.Lthree_start:
- R3 = B[P1++] (X);
-.Lthree_end:
- B[P0++] = R3;
-
- RTS;
-
-.Lmore_than_seven:
- /* There's at least eight bytes to copy. */
- P2 += -1; /* because we unroll one iteration */
- LSETUP(.Lword_loops, .Lword_loope) LC0=P2;
- I1 = P1;
- R3 = [I1++];
-#if ANOMALY_05000202
-.Lword_loops:
- [P0++] = R3;
-.Lword_loope:
- R3 = [I1++];
-#else
-.Lword_loops:
-.Lword_loope:
- MNOP || [P0++] = R3 || R3 = [I1++];
-#endif
- [P0++] = R3;
- /* Any remaining bytes to copy? */
- R3 = 0x3;
- R3 = R2 & R3;
- CC = R3 == 0;
- P1 = I1; /* in case there's something left, */
- IF !CC JUMP .Lbytes_left;
- RTS;
-.Lbytes_left: P2 = R3;
-.Lnot_aligned:
- /* From here, we're copying byte-by-byte. */
- LSETUP (.Lbyte_start, .Lbyte_end) LC0=P2;
-.Lbyte_start:
- R1 = B[P1++] (X);
-.Lbyte_end:
- B[P0++] = R1;
-
-.L_P1L2147483647:
- RTS;
-
-.Lhas_overlap:
- /* Need to reverse the copying, because the
- * dst would clobber the src.
- * Don't bother to work out alignment for
- * the reverse case.
- */
- P0 = P0 + P2;
- P0 += -1;
- P1 = P1 + P2;
- P1 += -1;
- LSETUP(.Lover_start, .Lover_end) LC0=P2;
-.Lover_start:
- R1 = B[P1--] (X);
-.Lover_end:
- B[P0--] = R1;
-
- RTS;
-
-ENDPROC(_memcpy)
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
deleted file mode 100644
index e0b78208f1d6..000000000000
--- a/arch/blackfin/lib/memmove.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-/*
- * C Library function MEMMOVE
- * R0 = To Address (leave unchanged to form result)
- * R1 = From Address
- * R2 = count
- * Data may overlap
- */
-
-ENTRY(_memmove)
- I1 = P3;
- P0 = R0; /* P0 = To address */
- P3 = R1; /* P3 = From Address */
- P2 = R2; /* P2 = count */
- CC = P2 == 0; /* Check zero count*/
- IF CC JUMP .Lfinished; /* very unlikely */
-
- CC = R1 < R0 (IU); /* From < To */
- IF !CC JUMP .Lno_overlap;
- R3 = R1 + R2;
- CC = R0 <= R3 (IU); /* (From+len) >= To */
- IF CC JUMP .Loverlap;
-.Lno_overlap:
- R3 = 11;
- CC = R2 <= R3;
- IF CC JUMP .Lbytes;
- R3 = R1 | R0; /* OR addresses together */
- R3 <<= 30; /* check bottom two bits */
- CC = AZ; /* AZ set if zero.*/
- IF !CC JUMP .Lbytes; /* Jump if addrs not aligned.*/
-
- I0 = P3;
- P1 = P2 >> 2; /* count = n/4 */
- P1 += -1;
- R3 = 3;
- R2 = R2 & R3; /* remainder */
- P2 = R2; /* set remainder */
- R1 = [I0++];
-
- LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
-#if ANOMALY_05000202
-.Lquad_loops:
- [P0++] = R1;
-.Lquad_loope:
- R1 = [I0++];
-#else
-.Lquad_loops:
-.Lquad_loope:
- MNOP || [P0++] = R1 || R1 = [I0++];
-#endif
- [P0++] = R1;
-
- CC = P2 == 0; /* any remaining bytes? */
- P3 = I0; /* Amend P3 to updated ptr. */
- IF !CC JUMP .Lbytes;
- P3 = I1;
- RTS;
-
-.Lbytes: LSETUP (.Lbyte2_s, .Lbyte2_e) LC0=P2;
-.Lbyte2_s: R1 = B[P3++](Z);
-.Lbyte2_e: B[P0++] = R1;
-
-.Lfinished: P3 = I1;
- RTS;
-
-.Loverlap:
- P2 += -1;
- P0 = P0 + P2;
- P3 = P3 + P2;
- R1 = B[P3--] (Z);
- CC = P2 == 0;
- IF CC JUMP .Lno_loop;
-#if ANOMALY_05000245
- NOP;
- NOP;
-#endif
- LSETUP (.Lol_s, .Lol_e) LC0 = P2;
-.Lol_s: B[P0--] = R1;
-.Lol_e: R1 = B[P3--] (Z);
-.Lno_loop: B[P0] = R1;
- P3 = I1;
- RTS;
-
-ENDPROC(_memmove)
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
deleted file mode 100644
index cdcf9148ea20..000000000000
--- a/arch/blackfin/lib/memset.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-#ifdef CONFIG_MEMSET_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- * C Library function MEMSET
- * R0 = address (leave unchanged to form result)
- * R1 = filler byte
- * R2 = count
- * Favours word aligned data.
- * The strncpy assumes that I0 and I1 are not used in this function
- */
-
-ENTRY(_memset)
- P0 = R0 ; /* P0 = address */
- P2 = R2 ; /* P2 = count */
- R3 = R0 + R2; /* end */
- CC = R2 <= 7(IU);
- IF CC JUMP .Ltoo_small;
- R1 = R1.B (Z); /* R1 = fill char */
- R2 = 3;
- R2 = R0 & R2; /* addr bottom two bits */
- CC = R2 == 0; /* AZ set if zero. */
- IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
-
-.Laligned:
- P1 = P2 >> 2; /* count = n/4 */
- R2 = R1 << 8; /* create quad filler */
- R2.L = R2.L + R1.L(NS);
- R2.H = R2.L + R1.H(NS);
- P2 = R3;
-
- LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
-.Lquad_loop:
- [P0++] = R2;
-
- CC = P0 == P2;
- IF !CC JUMP .Lbytes_left;
- RTS;
-
-.Lbytes_left:
- R2 = R3; /* end point */
- R3 = P0; /* current position */
- R2 = R2 - R3; /* bytes left */
- P2 = R2;
-
-.Ltoo_small:
- CC = P2 == 0; /* Check zero count */
- IF CC JUMP .Lfinished; /* Unusual */
-
-.Lbytes:
- LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
-.Lbyte_loop:
- B[P0++] = R1;
-
-.Lfinished:
- RTS;
-
-.Lforce_align:
- CC = BITTST (R0, 0); /* odd byte */
- R0 = 4;
- R0 = R0 - R2;
- P1 = R0;
- R0 = P0; /* Recover return address */
- IF !CC JUMP .Lskip1;
- B[P0++] = R1;
-.Lskip1:
- CC = R2 <= 2; /* 2 bytes */
- P2 -= P1; /* reduce count */
- IF !CC JUMP .Laligned;
- B[P0++] = R1;
- B[P0++] = R1;
- JUMP .Laligned;
-
-ENDPROC(_memset)
diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S
deleted file mode 100644
index f7026ce1fa0e..000000000000
--- a/arch/blackfin/lib/modsi3.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This program computes 32 bit signed remainder. It calls div32 function
- * for quotient estimation.
- * Registers in: R0, R1 = Numerator/ Denominator
- * Registers out: R0 = Remainder
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.global ___modsi3;
-.type ___modsi3, STT_FUNC;
-.extern ___divsi3;
-.type ___divsi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___modsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if numerator == 0 */
- CC=R1==0;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if numerator == denominator */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == 1 */
- CC = R1 == -1;
- IF CC JUMP .LRETURN_ZERO; /* Return 0, if denominator == -1 */
-
- /* Valid input. Use __divsi3() to compute the quotient, and then
- * derive the remainder from that. */
-
- [--SP] = (R7:6); /* Push R7 and R6 */
- [--SP] = RETS; /* and return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1; /* Save for later */
- SP += -12; /* Should always provide this space */
- CALL ___divsi3; /* Compute signed quotient using ___divsi3()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Get back return address */
- (R7:6) = [SP++]; /* Pop registers R7 and R4 */
- RTS; /* Store remainder */
-
-.LRETURN_ZERO:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___modsi3, .-___modsi3
diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S
deleted file mode 100644
index abf9b2a515b2..000000000000
--- a/arch/blackfin/lib/muldi3.S
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___muldi3;
-.type ___muldi3, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/*
- R1:R0 * R3:R2
- = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
-[X] = (R1.h * R3.h) * 2^96
-[X] + (R1.h * R3.l + R1.l * R3.h) * 2^80
-[X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
-[T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
-[T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
-[T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16
-[T4] + (R0.l * R2.l)
-
- We can discard the first three lines marked "X" since we produce
- only a 64 bit result. So, we need ten 16-bit multiplies.
-
- Individual mul-acc results:
-[E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
-[E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
-[E3] = R0.l * R2.h + R2.l * R0.h
-[E4] = R0.l * R2.l
-
- We also need to add high parts from lower-level results to higher ones:
- E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4
-
- One interesting property is that all parts of the result that depend
- on the sign of the multiplication are discarded. Those would be the
- multiplications involving R1.h and R3.h, but only the top 16 bit of
- the 32 bit result depend on the sign, and since R1.h and R3.h only
- occur in E1, the top half of these results is cut off.
- So, we can just use FU mode for all of the 16-bit multiplies, and
- ignore questions of when to use mixed mode. */
-
-___muldi3:
- /* [SP] technically is part of the caller's frame, but we can
- use it as scratch space. */
- A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
- A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
- A0 += A1; /* E1 */
- R4 = A0.w;
- A0 = R0.l * R3.l (FU); /* E2 */
- A0 += R2.l * R1.l (FU); /* E2 */
-
- A1 = R2.L * R0.L (FU); /* E4 */
- R3 = A1.w;
- A1 = A1 >> 16; /* E3c */
- A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
- A1 += R0.L * R2.H (FU); /* E3c */
- R0 = A1.w;
- A1 = A1 >> 16; /* E2c */
- A0 += A1; /* E2c */
- R1 = A0.w;
-
- /* low(result) = low(E3c):low(E4) */
- R0 = PACK (R0.l, R3.l);
- /* high(result) = E2c + (E1 << 16) */
- R1.h = R1.h + R4.l (NS) || R4 = [SP];
- RTS;
-
-.size ___muldi3, .-___muldi3
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
deleted file mode 100644
index 06a5e674401f..000000000000
--- a/arch/blackfin/lib/outs.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * 2005 BuyWays BV
- * Bas Vermeulen <bas@buyways.nl>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/linkage.h>
-
-.align 2
-
-ENTRY(_outsl)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
-.Llong_loop_s: R0 = [P1++];
-.Llong_loop_e: [P0] = R0;
-1: RTS;
-ENDPROC(_outsl)
-
-ENTRY(_outsw)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
-.Lword_loop_s: R0 = W[P1++];
-.Lword_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw)
-
-ENTRY(_outsb)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
-.Lbyte_loop_s: R0 = B[P1++];
-.Lbyte_loop_e: B[P0] = R0;
-1: RTS;
-ENDPROC(_outsb)
-
-ENTRY(_outsw_8)
- CC = R2 == 0;
- IF CC JUMP 1f;
- P0 = R0; /* P0 = port */
- P1 = R1; /* P1 = address */
- P2 = R2; /* P2 = count */
-
- LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
-.Lword8_loop_s: R1 = B[P1++];
- R0 = B[P1++];
- R0 = R0 << 8;
- R0 = R0 + R1;
-.Lword8_loop_e: W[P0] = R0;
-1: RTS;
-ENDPROC(_outsw_8)
diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S
deleted file mode 100644
index e50d6c4ac2a5..000000000000
--- a/arch/blackfin/lib/smulsi3_highpart.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___smulsi3_highpart;
-.type ___smulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___smulsi3_highpart:
- R2 = R1.L * R0.L (FU);
- R3 = R1.H * R0.L (IS,M);
- R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
-
- R1.L = R2.H + R1.L;
- cc = ac0;
- R2 = cc;
-
- R1.L = R1.L + R3.L;
- cc = ac0;
- R1 >>>= 16;
- R3 >>>= 16;
- R1 = R1 + R3;
- R1 = R1 + R2;
- R2 = cc;
- R1 = R1 + R2;
-
- R0 = R0 + R1;
- RTS;
-
-.size ___smulsi3_highpart, .-___smulsi3_highpart
diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S
deleted file mode 100644
index 9c8b9863713e..000000000000
--- a/arch/blackfin/lib/strcmp.S
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcmp(char *s1, const char *s2);
- * R0 = address (s1)
- * R1 = address (s2)
- *
- * Returns an integer less than, equal to, or greater than zero if s1
- * (or the first n bytes thereof) is found, respectively, to be less
- * than, to match, or be greater than s2.
- */
-
-#ifdef CONFIG_STRCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcmp)
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 2f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if cc jump 1b (bp); /* no, keep going */
- jump.s 3f; /* strings are equal */
-2:
- R0 = R0 - R1; /* *s1 - *s2 */
-3:
- RTS;
-
-ENDPROC(_strcmp)
diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S
deleted file mode 100644
index 9495aa77cc40..000000000000
--- a/arch/blackfin/lib/strcpy.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strcpy(char *dest, const char *src);
- * R0 = address (dest)
- * R1 = address (src)
- *
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strcpy)
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1;
- if cc jump 1b (bp);
- RTS;
-
-ENDPROC(_strcpy)
diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S
deleted file mode 100644
index 3bfaedce893e..000000000000
--- a/arch/blackfin/lib/strncmp.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-/* void *strncpy(char *s1, const char *s2, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size (n)
- * Returns a pointer to the destination string dest
- */
-
-#ifdef CONFIG_STRNCMP_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncmp)
- CC = R2 == 0;
- if CC JUMP 5f;
-
- P0 = R0 ; /* s1 */
- P1 = R1 ; /* s2 */
-1:
- R0 = B[P0++] (Z); /* get *s1 */
- R1 = B[P1++] (Z); /* get *s2 */
- CC = R0 == R1; /* compare a byte */
- if ! cc jump 3f; /* not equal, break out */
- CC = R0; /* at end of s1? */
- if ! cc jump 4f; /* yes, all done */
- R2 += -1; /* no, adjust count */
- CC = R2 == 0;
- if ! cc jump 1b (bp); /* more to do, keep going */
-2:
- R0 = 0; /* strings are equal */
- jump.s 4f;
-3:
- R0 = R0 - R1; /* *s1 - *s2 */
-4:
- RTS;
-
-5:
- R0 = 0;
- RTS;
-
-ENDPROC(_strncmp)
diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S
deleted file mode 100644
index 92fd1823bbee..000000000000
--- a/arch/blackfin/lib/strncpy.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-#include <asm/context.S>
-
-/* void *strncpy(char *dest, const char *src, size_t n);
- * R0 = address (dest)
- * R1 = address (src)
- * R2 = size
- * Returns a pointer (R0) to the destination string dest
- * we do this by not changing R0
- */
-
-#ifdef CONFIG_STRNCPY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 2
-
-ENTRY(_strncpy)
- CC = R2 == 0;
- if CC JUMP 6f;
-
- P2 = R2 ; /* size */
- P0 = R0 ; /* dst*/
- P1 = R1 ; /* src*/
-
- LSETUP (1f, 2f) LC0 = P2;
-1:
- R1 = B [P1++] (Z);
- B [P0++] = R1;
- CC = R1 == 0;
-2:
- if CC jump 3f;
-
- RTS;
-
- /* if src is shorter than n, we need to null pad bytes in dest
- * but, we can get here when the last byte is zero, and we don't
- * want to copy an extra byte at the end, so we need to check
- */
-3:
- R2 = LC0;
- CC = R2
- if ! CC jump 6f;
-
- /* if the required null padded portion is small, do it here, rather than
- * handling the overhead of memset (which is OK when things are big).
- */
- R3 = 0x20;
- CC = R2 < R3;
- IF CC jump 4f;
-
- R2 += -1;
-
- /* Set things up for memset
- * R0 = address
- * R1 = filler byte (this case it's zero, set above)
- * R2 = count (set above)
- */
-
- I1 = R0;
- R0 = RETS;
- I0 = R0;
- R0 = P0;
- pseudo_long_call _memset, p0;
- R0 = I0;
- RETS = R0;
- R0 = I1;
- RTS;
-
-4:
- LSETUP(5f, 5f) LC0;
-5:
- B [P0++] = R1;
-6:
- RTS;
-
-ENDPROC(_strncpy)
diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S
deleted file mode 100644
index 90bfa809b392..000000000000
--- a/arch/blackfin/lib/udivsi3.S
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#include <linux/linkage.h>
-
-#define CARRY AC0
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-
-ENTRY(___udivsi3)
-
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- IF CC JUMP .Lreturn_ident;
-
- R2 = R1 << 16;
- CC = R2 <= R0 (IU);
- IF CC JUMP .Lidents;
-
- R2 = R0 >> 31; /* if X is a 31-bit number */
- R3 = R1 >> 15; /* and Y is a 15-bit number */
- R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/
- CC = R2;
- IF CC JUMP .Ly_16bit;
-
-/* METHOD 1: FAST DIVQ
- We know we have a 31-bit dividend, and 15-bit divisor so we can use the
- simple divq approach (first setting AQ to 0 - implying unsigned division,
- then 16 DIVQ's).
-*/
-
- AQ = CC; /* Clear AQ (CC==0) */
-
-/* ISR States: When dividing two integers (32.0/16.0) using divide primitives,
- we need to shift the dividend one bit to the left.
- We have already checked that we have a 31-bit number so we are safe to do
- that.
-*/
- R0 <<= 1;
- DIVQ(R0, R1); // 1
- DIVQ(R0, R1); // 2
- DIVQ(R0, R1); // 3
- DIVQ(R0, R1); // 4
- DIVQ(R0, R1); // 5
- DIVQ(R0, R1); // 6
- DIVQ(R0, R1); // 7
- DIVQ(R0, R1); // 8
- DIVQ(R0, R1); // 9
- DIVQ(R0, R1); // 10
- DIVQ(R0, R1); // 11
- DIVQ(R0, R1); // 12
- DIVQ(R0, R1); // 13
- DIVQ(R0, R1); // 14
- DIVQ(R0, R1); // 15
- DIVQ(R0, R1); // 16
- R0 = R0.L (Z);
- RTS;
-
-.Ly_16bit:
- /* We know that the upper 17 bits of Y might have bits set,
- ** or that the sign bit of X might have a bit. If Y is a
- ** 16-bit number, but not bigger, then we can use the builtins
- ** with a post-divide correction.
- ** R3 currently holds Y>>15, which means R3's LSB is the
- ** bit we're interested in.
- */
-
- /* According to the ISR, to use the Divide primitives for
- ** unsigned integer divide, the useable range is 31 bits
- */
- CC = ! BITTST(R0, 31);
-
- /* IF condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 += -1; /* if so, Y is 0x00008nnn */
- CC &= AZ;
-
- /* If condition is true we can scale our inputs and use the divide primitives,
- ** with some post-adjustment
- */
- R3 = R1 >> 1; /* Pre-scaled divisor for primitive case */
- R2 = R0 >> 16;
-
- R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */
- CC &= CARRY;
- IF CC JUMP .Lshift_and_correct;
-
- /* Fall through to the identities */
-
-/* METHOD 2: identities and manual calculation
- We are not able to use the divide primites, but may still catch some special
- cases.
-*/
-.Lidents:
- /* Test for common identities. Value to be returned is placed in R2. */
- CC = R0 == 0; /* 0/Y => 0 */
- IF CC JUMP .Lreturn_r0;
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Lreturn_ident;
- CC = R1 == 1; /* X/1 => X */
- IF CC JUMP .Lreturn_ident;
-
- R2.L = ONES R1;
- R2 = R2.L (Z);
- CC = R2 == 1;
- IF CC JUMP .Lpower_of_two;
-
- [--SP] = (R7:5); /* Push registers R5-R7 */
-
- /* Idents don't match. Go for the full operation. */
-
-
- R6 = 2; /* assume we'll shift two */
- R3 = 1;
-
- P2 = R1;
- /* If either R0 or R1 have sign set, */
- /* divide them by two, and note it's */
- /* been done. */
- CC = R1 < 0;
- R2 = R1 >> 1;
- IF CC R1 = R2; /* Possibly-shifted R1 */
- IF !CC R6 = R3; /* R1 doesn't, so at most 1 shifted */
-
- P0 = 0;
- R3 = -R1;
- [--SP] = R3;
- R2 = R0 >> 1;
- R2 = R0 >> 1;
- CC = R0 < 0;
- IF CC P0 = R6; /* Number of values divided */
- IF !CC R2 = R0; /* Shifted R0 */
-
- /* P0 is 0, 1 (NR/=2) or 2 (NR/=2, DR/=2) */
-
- /* r2 holds Copy dividend */
- R3 = 0; /* Clear partial remainder */
- R7 = 0; /* Initialise quotient bit */
-
- P1 = 32; /* Set loop counter */
- LSETUP(.Lulst, .Lulend) LC0 = P1; /* Set loop counter */
-.Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */
- R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */
- R3 = R3 << 1 || R5 = [SP];
- R3 = R3 | R6; /* Include any carry */
- CC = R7 < 0; /* Check quotient(AQ) */
- /* If AQ==0, we'll sub divisor */
- IF CC R5 = R1; /* and if AQ==1, we'll add it. */
- R3 = R3 + R5; /* Add/sub divisor to partial remainder */
- R7 = R3 ^ R1; /* Generate next quotient bit */
-
- R5 = R7 >> 31; /* Get AQ */
- BITTGL(R5, 0); /* Invert it, to get what we'll shift */
-.Lulend: R2 = R2 + R5; /* and "shift" it in. */
-
- CC = P0 == 0; /* Check how many inputs we shifted */
- IF CC JUMP .Lno_mult; /* if none... */
- R6 = R2 << 1;
- CC = P0 == 1;
- IF CC R2 = R6; /* if 1, Q = Q*2 */
- IF !CC R1 = P2; /* if 2, restore stored divisor */
-
- R3 = R2; /* Copy of R2 */
- R3 *= R1; /* Q * divisor */
- R5 = R0 - R3; /* Z = (dividend - Q * divisor) */
- CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
- R6 = CC; /* if yes, R6 = 1 */
- R2 = R2 + R6; /* if yes, add one to quotient(Q) */
-.Lno_mult:
- SP += 4;
- (R7:5) = [SP++]; /* Pop registers R5-R7 */
- R0 = R2; /* Store quotient */
- RTS;
-
-.Lreturn_ident:
- CC = R0 < R1 (IU); /* If X < Y, always return 0 */
- R2 = 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -1 (X); /* X/0 => 0xFFFFFFFF */
- CC = R1 == 0;
- IF CC JUMP .Ltrue_return_ident;
- R2 = -R2; /* R2 now 1 */
- CC = R0 == R1; /* X==Y => 1 */
- IF CC JUMP .Ltrue_return_ident;
- R2 = R0; /* X/1 => X */
- /*FALLTHRU*/
-
-.Ltrue_return_ident:
- R0 = R2;
-.Lreturn_r0:
- RTS;
-
-.Lpower_of_two:
- /* Y has a single bit set, which means it's a power of two.
- ** That means we can perform the division just by shifting
- ** X to the right the appropriate number of bits
- */
-
- /* signbits returns the number of sign bits, minus one.
- ** 1=>30, 2=>29, ..., 0x40000000=>0. Which means we need
- ** to shift right n-signbits spaces. It also means 0x80000000
- ** is a special case, because that *also* gives a signbits of 0
- */
-
- R2 = R0 >> 31;
- CC = R1 < 0;
- IF CC JUMP .Ltrue_return_ident;
-
- R1.l = SIGNBITS R1;
- R1 = R1.L (Z);
- R1 += -30;
- R0 = LSHIFT R0 by R1.L;
- RTS;
-
-/* METHOD 3: PRESCALE AND USE THE DIVIDE PRIMITIVES WITH SOME POST-CORRECTION
- Two scaling operations are required to use the divide primitives with a
- divisor > 0x7FFFF.
- Firstly (as in method 1) we need to shift the dividend 1 to the left for
- integer division.
- Secondly we need to shift both the divisor and dividend 1 to the right so
- both are in range for the primitives.
- The left/right shift of the dividend does nothing so we can skip it.
-*/
-.Lshift_and_correct:
- R2 = R0;
- // R3 is already R1 >> 1
- CC=!CC;
- AQ = CC; /* Clear AQ, got here with CC = 0 */
- DIVQ(R2, R3); // 1
- DIVQ(R2, R3); // 2
- DIVQ(R2, R3); // 3
- DIVQ(R2, R3); // 4
- DIVQ(R2, R3); // 5
- DIVQ(R2, R3); // 6
- DIVQ(R2, R3); // 7
- DIVQ(R2, R3); // 8
- DIVQ(R2, R3); // 9
- DIVQ(R2, R3); // 10
- DIVQ(R2, R3); // 11
- DIVQ(R2, R3); // 12
- DIVQ(R2, R3); // 13
- DIVQ(R2, R3); // 14
- DIVQ(R2, R3); // 15
- DIVQ(R2, R3); // 16
-
- /* According to the Instruction Set Reference:
- To divide by a divisor > 0x7FFF,
- 1. prescale and perform divide to obtain quotient (Q) (done above),
- 2. multiply quotient by unscaled divisor (result M)
- 3. subtract the product from the divident to get an error (E = X - M)
- 4. if E < divisor (Y) subtract 1, if E > divisor (Y) add 1, else return quotient (Q)
- */
- R3 = R2.L (Z); /* Q = X' / Y' */
- R2 = R3; /* Preserve Q */
- R2 *= R1; /* M = Q * Y */
- R2 = R0 - R2; /* E = X - M */
- R0 = R3; /* Copy Q into result reg */
-
-/* Correction: If result of the multiply is negative, we overflowed
- and need to correct the result by subtracting 1 from the result.*/
- R3 = 0xFFFF (Z);
- R2 = R2 >> 16; /* E >> 16 */
- CC = R2 == R3;
- R3 = 1 ;
- R1 = R0 - R3;
- IF CC R0 = R1;
- RTS;
-
-ENDPROC(___udivsi3)
diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S
deleted file mode 100644
index 3794c00d859d..000000000000
--- a/arch/blackfin/lib/umodsi3.S
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * libgcc1 routines for Blackfin 5xx
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.extern ___udivsi3;
-.type ___udivsi3, STT_FUNC;
-.globl ___umodsi3
-.type ___umodsi3, STT_FUNC;
-___umodsi3:
-
- CC=R0==0;
- IF CC JUMP .LRETURN_R0; /* Return 0, if NR == 0 */
- CC= R1==0;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 0 */
- CC=R0==R1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if NR == DR */
- CC = R1 == 1;
- IF CC JUMP .LRETURN_ZERO_VAL; /* Return 0, if DR == 1 */
- CC = R0<R1 (IU);
- IF CC JUMP .LRETURN_R0; /* Return dividend (R0),IF NR<DR */
-
- [--SP] = (R7:6); /* Push registers and */
- [--SP] = RETS; /* Return address */
- R7 = R0; /* Copy of R0 */
- R6 = R1;
- SP += -12; /* Should always provide this space */
- CALL ___udivsi3; /* Compute unsigned quotient using ___udiv32()*/
- SP += 12;
- R0 *= R6; /* Quotient * divisor */
- R0 = R7 - R0; /* Dividend - (quotient * divisor) */
- RETS = [SP++]; /* Pop return address */
- ( R7:6) = [SP++]; /* And registers */
- RTS; /* Return remainder */
-.LRETURN_ZERO_VAL:
- R0 = 0;
-.LRETURN_R0:
- RTS;
-
-.size ___umodsi3, .-___umodsi3
diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S
deleted file mode 100644
index 0dcace96e4e7..000000000000
--- a/arch/blackfin/lib/umulsi3_highpart.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2007 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-.align 2
-.global ___umulsi3_highpart;
-.type ___umulsi3_highpart, STT_FUNC;
-
-#ifdef CONFIG_ARITHMETIC_OPS_L1
-.section .l1.text
-#else
-.text
-#endif
-
-___umulsi3_highpart:
- R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
- R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
- R0 >>= 16;
- /* Unsigned multiplication has the nice property that we can
- ignore carry on this first addition. */
- R0 = R0 + R3;
- R0 = R0 + R1;
- cc = ac0;
- R1 = cc;
- R1 = PACK(R1.l,R0.h);
- R0 = R1 + R2;
- RTS;
-
-.size ___umulsi3_highpart, .-___umulsi3_highpart
diff --git a/arch/blackfin/mach-bf518/Kconfig b/arch/blackfin/mach-bf518/Kconfig
deleted file mode 100644
index 4731f6b27e47..000000000000
--- a/arch/blackfin/mach-bf518/Kconfig
+++ /dev/null
@@ -1,320 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF51x
- def_bool y
- depends on (BF512 || BF514 || BF516 || BF518)
-
-if (BF51x)
-
-source "arch/blackfin/mach-bf518/boards/Kconfig"
-
-menu "BF518 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "PWM Channel Pins"
- default BF518_PWM_ALL_PORTF
- help
- Select pins used for the PWM channels:
- PWM_AH PWM_AL PWM_BH PWM_BL PWM_CH PWM_CL
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_ALL_PORTF
- bool "PF1 - PF6"
- help
- PF{1,2,3,4,5,6} <-> PWM_{AH,AL,BH,BL,CH,CL}
-
-config BF518_PWM_PORTF_PORTG
- bool "PF11 - PF14 / PG1 - PG2"
- help
- PF{11,12,13,14} <-> PWM_{AH,AL,BH,BL}
- PG{1,2} <-> PWM_{CH,CL}
-
-endchoice
-
-choice
- prompt "PWM Sync Pin"
- default BF518_PWM_SYNC_PF7
- help
- Select the pin used for PWM_SYNC.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_SYNC_PF7
- bool "PF7"
-config BF518_PWM_SYNC_PF15
- bool "PF15"
-endchoice
-
-choice
- prompt "PWM Trip B Pin"
- default BF518_PWM_TRIPB_PG10
- help
- Select the pin used for PWM_TRIPB.
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PWM_TRIPB_PG10
- bool "PG10"
-config BF518_PWM_TRIPB_PG14
- bool "PG14"
-endchoice
-
-choice
- prompt "PPI / Timer Pins"
- default BF518_PPI_TMR_PG5
- help
- Select pins used for PPI/Timer:
- PPICLK PPIFS1 PPIFS2
- TMRCLK TMR0 TMR1
-
- See the Hardware Reference Manual for more details.
-
-config BF518_PPI_TMR_PG5
- bool "PG5 - PG7"
- help
- PG{5,6,7} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-config BF518_PPI_TMR_PG12
- bool "PG12 - PG14"
- help
- PG{12,13,14} <-> {PPICLK/TMRCLK,TMR0/PPIFS1,TMR1/PPIFS2}
-
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF51x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_PTP_ERROR
- int "IRQ_PTP_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI0
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_RSI_INT0
- int "IRQ_RSI_INT0"
- default 7
-config IRQ_RSI_INT1
- int "IRQ_RSI_INT1"
- default 7
-config IRQ_PWM_TRIP
- int "IRQ_PWM_TRIP"
- default 10
-config IRQ_PWM_SYNC
- int "IRQ_PWM_SYNC"
- default 10
-config IRQ_PTP_STAT
- int "IRQ_PTP_STAT"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf518/Makefile b/arch/blackfin/mach-bf518/Makefile
deleted file mode 100644
index 168a193f9f9a..000000000000
--- a/arch/blackfin/mach-bf518/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf518/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf518/boards/Kconfig b/arch/blackfin/mach-bf518/boards/Kconfig
deleted file mode 100644
index f7b93b950ef4..000000000000
--- a/arch/blackfin/mach-bf518/boards/Kconfig
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN518F_EZBRD
- help
- Select your board!
-
-config BFIN518F_EZBRD
- bool "BF518F-EZBRD"
- help
- BF518-EZBRD board support.
-
-config BFIN518F_TCM
- bool "Bluetechnix TCM-BF518"
- help
- Bluetechnix TCM-BF518 board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf518/boards/Makefile b/arch/blackfin/mach-bf518/boards/Makefile
deleted file mode 100644
index a9ef25c6b302..000000000000
--- a/arch/blackfin/mach-bf518/boards/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf518/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN518F_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN518F_TCM) += tcm-bf518.o
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
deleted file mode 100644
index c51d1b810ac3..000000000000
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ /dev/null
@@ -1,794 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF518F-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = {
- P_MII0_ETxD0,
- P_MII0_ETxD1,
- P_MII0_ETxEN,
- P_MII0_ERxD0,
- P_MII0_ERxD1,
- P_MII0_TxCLK,
- P_MII0_PHYINT,
- P_MII0_CRS,
- P_MII0_MDC,
- P_MII0_MDIO,
- 0
-};
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
- .vlan1_mask = 1,
- .vlan2_mask = 2,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
- peripheral_request(P_AMS2, "ParaFlash");
-#if !IS_ENABLED(CONFIG_SPI_BFIN5XX)
- peripheral_request(P_AMS3, "ParaFlash");
-#endif
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
deleted file mode 100644
index 37d868085f6a..000000000000
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ /dev/null
@@ -1,739 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sdh.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM-BF518";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition tcm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- },
- {
- .name = "linux(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tcm_flash_data = {
- .width = 2,
- .parts = tcm_partitions,
- .nr_parts = ARRAY_SIZE(tcm_partitions),
-};
-
-static struct resource tcm_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device tcm_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &tcm_flash_data,
- },
- .num_resources = 1,
- .resource = &tcm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* SPI0_SSEL2 */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-/* SPI controller data */
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-
-/* SPI (1) */
-static struct bfin5xx_spi_master bfin_spi1_info = {
- .num_chipselect = 6,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi1_device = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bfin_spi1_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bf51x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tcm_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
- &bfin_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf51x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &tcm_flash_device,
-#endif
-};
-
-static int __init tcm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tcm_devices, ARRAY_SIZE(tcm_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tcm_init);
-
-static struct platform_device *tcm_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tcm_early_devices,
- ARRAY_SIZE(tcm_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
deleted file mode 100644
index bcd1fbc8c543..000000000000
--- a/arch/blackfin/mach-bf518/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
deleted file mode 100644
index 46cb88231d66..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF518 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
-/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
-#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* Incorrect L1 Instruction Bank B Memory Map Location */
-#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-/* PWM_TRIPB Signal Not Available on PG10 */
-#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
-/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
-#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bf518.h b/arch/blackfin/mach-bf518/include/mach/bf518.h
deleted file mode 100644
index 6906dee4f4cc..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/bf518.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF518_H__
-#define __MACH_BF518_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
-
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3C)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF518
-#define CPU "BF518"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF516
-#define CPU "BF516"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF514
-#define CPU "BF514"
-#define CPUID 0x27e8
-#endif
-#ifdef CONFIG_BF512
-#define CPU "BF512"
-#define CPUID 0x27e8
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF518_H__ */
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603fe8218..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
deleted file mode 100644
index a8828863226e..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf518.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF512
-# include "defBF512.h"
-#endif
-#ifdef CONFIG_BF514
-# include "defBF514.h"
-#endif
-#ifdef CONFIG_BF516
-# include "defBF516.h"
-#endif
-#ifdef CONFIG_BF518
-# include "defBF518.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF512
-# include "cdefBF512.h"
-# endif
-# ifdef CONFIG_BF514
-# include "cdefBF514.h"
-# endif
-# ifdef CONFIG_BF516
-# include "cdefBF516.h"
-# endif
-# ifdef CONFIG_BF518
-# include "cdefBF518.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
deleted file mode 100644
index 1c03ad4bcb72..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF512_H
-#define _CDEF_BF512_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-#endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
deleted file mode 100644
index 861221d1dcc9..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF514_H
-#define _CDEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "cdefBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
-#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
-#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
-#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
-#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
-#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
-#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
-#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
-
-#endif /* _CDEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
deleted file mode 100644
index cc9bf0d378c3..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF516_H
-#define _CDEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "cdefBF514.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
deleted file mode 100644
index 96a82fd62ef1..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _CDEF_BF518_H
-#define _CDEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "cdefBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
-#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
-#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
-#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
-#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
-#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
-#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
-#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
-#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
-#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
-#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
-#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
-#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
-#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
-#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
-#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
-#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
-#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
-#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
-#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
-#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
-#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
-#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
-#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
-#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
-#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
-#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
-#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
-#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
-#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
-#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
-#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
-#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
-#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
-#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
-#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
-#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
-#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
-#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
-#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
-
-#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
deleted file mode 100644
index e6a017faad01..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ /dev/null
@@ -1,1304 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF512_H
-#define _DEF_BF512_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
-/* ************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI0_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
-#define SPI1_REGBASE 0xFFC03400
-#define SPI1_CTL 0xFFC03400 /* SPI Control Register */
-#define SPI1_FLG 0xFFC03404 /* SPI Flag register */
-#define SPI1_STAT 0xFFC03408 /* SPI Status register */
-#define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
-#define SPI1_SHADOW 0xFFC03418 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Motor Control PWM Registers */
-
-#define PWM_CTRL 0xffc03700 /* PWM Control Register */
-#define PWM_STAT 0xffc03704 /* PWM Status Register */
-#define PWM_TM 0xffc03708 /* PWM Period Register */
-#define PWM_DT 0xffc0370c /* PWM Dead Time Register */
-#define PWM_GATE 0xffc03710 /* PWM Chopping Control */
-#define PWM_CHA 0xffc03714 /* PWM Channel A Duty Control */
-#define PWM_CHB 0xffc03718 /* PWM Channel B Duty Control */
-#define PWM_CHC 0xffc0371c /* PWM Channel C Duty Control */
-#define PWM_SEG 0xffc03720 /* PWM Crossover and Output Enable */
-#define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
-#define PWM_CHAL 0xffc03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM_CHBL 0xffc0372c /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM_CHCL 0xffc03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM_LSI 0xffc03734 /* PWM Low Side Invert (SR mode only) */
-#define PWM_STAT2 0xffc03738 /* PWM Status Register 2 */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
deleted file mode 100644
index 97feaa629ed7..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF514_H
-#define _DEF_BF514_H
-
-/* BF514 is BF512 + RSI */
-#include "defBF512.h"
-
-/* Removable Storage Interface Registers */
-
-#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
-#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
-
-#endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
deleted file mode 100644
index 7c79cb6a03b1..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF516_H
-#define _DEF_BF516_H
-
-/* BF516 is BF514 + EMAC */
-#include "defBF514.h"
-
-/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
deleted file mode 100644
index 12042ff13601..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF518_H
-#define _DEF_BF518_H
-
-/* BF518 is BF516 + IEEE-1588 */
-#include "defBF516.h"
-
-/* PTP TSYNC Registers */
-
-#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
-#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
-#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
-#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
-#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
-#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
-#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
-#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
-#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
-#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
-#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
-#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
-#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
-#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
-#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
-#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
-#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
-#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
-#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
-#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
-#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
-#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
-#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
-
-/* Bit masks for EMAC_PTP_CTL */
-
-#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
-#define TL 0x2 /* Timestamp lock control */
-#define ASEN 0x10 /* Auxiliary snapshot control */
-#define PPSEN 0x80 /* Pulse-per-second (PPS) control */
-#define CKOEN 0x2000 /* Clock output control */
-
-/* Bit masks for EMAC_PTP_IE */
-
-#define ALIE 0x1 /* Alarm interrupt enable */
-#define RXEIE 0x2 /* Receive event interrupt enable */
-#define RXGIE 0x4 /* Receive general interrupt enable */
-#define TXIE 0x8 /* Transmit interrupt enable */
-#define RXOVE 0x10 /* Receive overrun error interrupt enable */
-#define TXOVE 0x20 /* Transmit overrun error interrupt enable */
-#define ASIE 0x40 /* Auxiliary snapshot interrupt enable */
-
-/* Bit masks for EMAC_PTP_ISTAT */
-
-#define ALS 0x1 /* Alarm status */
-#define RXEL 0x2 /* Receive event interrupt status */
-#define RXGL 0x4 /* Receive general interrupt status */
-#define TXTL 0x8 /* Transmit snapshot status */
-#define RXOV 0x10 /* Receive snapshot overrun status */
-#define TXOV 0x20 /* Transmit snapshot overrun status */
-#define ASL 0x40 /* Auxiliary snapshot interrupt status */
-
-#endif /* _DEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/dma.h b/arch/blackfin/mach-bf518/include/mach/dma.h
deleted file mode 100644
index bbd33c1706e2..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/dma.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_RSI 4 /* RSI */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPI1 5 /* SPI1 transmit/receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI0 7 /* SPI0 transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_SRC 12 /* RX */
-#define CH_MEM_STREAM0_DEST 13 /* TX */
-#define CH_MEM_STREAM1_SRC 14 /* RX */
-#define CH_MEM_STREAM1_DEST 15 /* TX */
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
deleted file mode 100644
index b480705bfc2e..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 41
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
deleted file mode 100644
index edf8efd457dc..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF518_IRQ_H_
-#define _BF518_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
-#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
-#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
-#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
-#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
-#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_PTP_ERROR_POS 8
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_RSI_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPI1_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI0_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS 0
-#define IRQ_RSI_INT0_POS 12
-#define IRQ_RSI_INT1_POS 16
-#define IRQ_PWM_TRIP_POS 20
-#define IRQ_PWM_SYNC_POS 24
-#define IRQ_PTP_STAT_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/mem_map.h b/arch/blackfin/mach-bf518/include/mach/mem_map.h
deleted file mode 100644
index 073b5d73d391..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/mem_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BF51x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF518/6/4/2 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16 * 1024)
-#else
-#define BFIN_ICACHESIZE (0)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0x8000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16 * 1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32 * 1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE 0
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/portmux.h b/arch/blackfin/mach-bf518/include/mach/portmux.h
deleted file mode 100644
index b3b806f468da..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/portmux.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-/* EMAC MII/RMII Port Mux */
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#else
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#endif
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-
-/* Timer */
-#ifndef CONFIG_BF518_PPI_TMR_PG12
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#else
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-
-/* DMA */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-
-/* PWM */
-#ifndef CONFIG_BF518_PWM_PORTF_PORTG
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#else
-#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_SYNC_PF15
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#else
-#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#endif
-
-#ifndef CONFIG_BF518_PWM_TRIPB_PG14
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
-#else
-#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#endif
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-
-/* AMS */
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf518/ints-priority.c b/arch/blackfin/mach-bf518/ints-priority.c
deleted file mode 100644
index bb05bef34ec0..000000000000
--- a/arch/blackfin/mach-bf518/ints-priority.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_PTP_ERROR - 7) << IRQ_PTP_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_RSI_INT0 - 7) << IRQ_RSI_INT0_POS) |
- ((CONFIG_IRQ_RSI_INT1 - 7) << IRQ_RSI_INT1_POS) |
- ((CONFIG_IRQ_PWM_TRIP - 7) << IRQ_PWM_TRIP_POS) |
- ((CONFIG_IRQ_PWM_SYNC - 7) << IRQ_PWM_SYNC_POS) |
- ((CONFIG_IRQ_PTP_STAT - 7) << IRQ_PTP_STAT_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf527/Kconfig b/arch/blackfin/mach-bf527/Kconfig
deleted file mode 100644
index 6df20f9c7bd4..000000000000
--- a/arch/blackfin/mach-bf527/Kconfig
+++ /dev/null
@@ -1,325 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF52x
- def_bool y
- depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
-
-if (BF52x)
-
-source "arch/blackfin/mach-bf527/boards/Kconfig"
-
-menu "BF527 Specific Configuration"
-
-comment "Alternative Multiplexing Scheme"
-
-choice
- prompt "SPORT0"
- default BF527_SPORT0_PORTG
- help
- Select PORT used for SPORT0. See Hardware Reference Manual
-
-config BF527_SPORT0_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_SPORT0_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "SPORT0 TSCLK Location"
- depends on BF527_SPORT0_PORTG
- default BF527_SPORT0_TSCLK_PG10
- help
- Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
-
-config BF527_SPORT0_TSCLK_PG10
- bool "PORT PG10"
- help
- PORT PG10
-
-config BF527_SPORT0_TSCLK_PG14
- bool "PORT PG14"
- help
- PORT PG14
-endchoice
-
-choice
- prompt "UART1"
- default BF527_UART1_PORTF
- help
- Select PORT used for UART1. See Hardware Reference Manual
-
-config BF527_UART1_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_UART1_PORTG
- bool "PORT G"
- help
- PORT G
-endchoice
-
-choice
- prompt "NAND (NFC) Data"
- default BF527_NAND_D_PORTH
- help
- Select PORT used for NAND Data Bus. See Hardware Reference Manual
-
-config BF527_NAND_D_PORTF
- bool "PORT F"
- help
- PORT F
-
-config BF527_NAND_D_PORTH
- bool "PORT H"
- help
- PORT H
-endchoice
-
-comment "Hysteresis/Schmitt Trigger Control"
-config BFIN_HYSTERESIS_CONTROL
- bool "Enable Hysteresis Control"
- help
- The ADSP-BF52x allows to control input hysteresis for Port F,
- Port G and Port H and other processor signal inputs.
- The Schmitt trigger enables can be set only for pin groups.
- Saying Y will overwrite the default reset or boot loader
- initialization.
-
-menu "PORT F"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTF_0_7
- bool "Enable Hysteresis on PORTF {0...7}"
-config GPIO_HYST_PORTF_8_9
- bool "Enable Hysteresis on PORTF {8, 9}"
-config GPIO_HYST_PORTF_10
- bool "Enable Hysteresis on PORTF 10"
-config GPIO_HYST_PORTF_11
- bool "Enable Hysteresis on PORTF 11"
-config GPIO_HYST_PORTF_12_13
- bool "Enable Hysteresis on PORTF {12, 13}"
-config GPIO_HYST_PORTF_14_15
- bool "Enable Hysteresis on PORTF {14, 15}"
-endmenu
-
-menu "PORT G"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTG_0
- bool "Enable Hysteresis on PORTG 0"
-config GPIO_HYST_PORTG_1_4
- bool "Enable Hysteresis on PORTG {1...4}"
-config GPIO_HYST_PORTG_5_6
- bool "Enable Hysteresis on PORTG {5, 6}"
-config GPIO_HYST_PORTG_7_8
- bool "Enable Hysteresis on PORTG {7, 8}"
-config GPIO_HYST_PORTG_9
- bool "Enable Hysteresis on PORTG 9"
-config GPIO_HYST_PORTG_10
- bool "Enable Hysteresis on PORTG 10"
-config GPIO_HYST_PORTG_11_13
- bool "Enable Hysteresis on PORTG {11...13}"
-config GPIO_HYST_PORTG_14_15
- bool "Enable Hysteresis on PORTG {14, 15}"
-endmenu
-
-menu "PORT H"
- depends on BFIN_HYSTERESIS_CONTROL
-config GPIO_HYST_PORTH_0_7
- bool "Enable Hysteresis on PORTH {0...7}"
-config GPIO_HYST_PORTH_8
- bool "Enable Hysteresis on PORTH 8"
-config GPIO_HYST_PORTH_9_15
- bool "Enable Hysteresis on PORTH {9...15}"
-endmenu
-
-menu "None-GPIO"
- depends on BFIN_HYSTERESIS_CONTROL
-config NONEGPIO_HYST_TMR0_FS1_PPICLK
- bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
-config NONEGPIO_HYST_NMI_RST_BMODE
- bool "Enable Hysteresis on {NMI, RESET, BMODE}"
-config NONEGPIO_HYST_JTAG
- bool "Enable Hysteresis on JTAG"
-endmenu
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_DMAR0_BLK
- int "IRQ_DMAR0_BLK"
- default 7
-config IRQ_DMAR1_BLK
- int "IRQ_DMAR1_BLK"
- default 7
-config IRQ_DMAR0_OVR
- int "IRQ_DMAR0_OVR"
- default 7
-config IRQ_DMAR1_OVR
- int "IRQ_DMAR1_OVR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_MAC_ERROR
- int "IRQ_MAC_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_OPTSEC
- int "IRQ_OPTSEC"
- default 11
-config IRQ_CNT
- int "IRQ_CNT"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_PORTH_INTA
- int "IRQ_PORTH_INTA"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX/NFC"
- default 11
-config IRQ_PORTH_INTB
- int "IRQ_PORTH_INTB"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PORTG_INTA
- int "IRQ_PORTG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 13
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 13
-config IRQ_SPI_ERROR
- int "IRQ_SPI_ERROR"
- default 7
-config IRQ_NFC_ERROR
- int "IRQ_NFC_ERROR"
- default 7
-config IRQ_HDMA_ERROR
- int "IRQ_HDMA_ERROR"
- default 7
-config IRQ_HDMA
- int "IRQ_HDMA"
- default 7
-config IRQ_USB_EINT
- int "IRQ_USB_EINT"
- default 10
-config IRQ_USB_INT0
- int "IRQ_USB_INT0"
- default 10
-config IRQ_USB_INT1
- int "IRQ_USB_INT1"
- default 10
-config IRQ_USB_INT2
- int "IRQ_USB_INT2"
- default 10
-config IRQ_USB_DMA
- int "IRQ_USB_DMA"
- default 10
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf527/Makefile b/arch/blackfin/mach-bf527/Makefile
deleted file mode 100644
index 4a6cdafab8ce..000000000000
--- a/arch/blackfin/mach-bf527/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf527/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf527/boards/Kconfig b/arch/blackfin/mach-bf527/boards/Kconfig
deleted file mode 100644
index a76f02fae11c..000000000000
--- a/arch/blackfin/mach-bf527/boards/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN527_EZKIT
- help
- Select your board!
-
-config BFIN527_EZKIT
- bool "BF527-EZKIT"
- help
- BF527-EZKIT-LITE board support.
-
-config BFIN527_EZKIT_V2
- bool "BF527-EZKIT-V2"
- help
- BF527-EZKIT-LITE V2.1+ board support.
-
-config BFIN527_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF527"
- help
- CM-BF527 support for EVAL- and DEV-Board.
-
-config BFIN526_EZBRD
- bool "BF526-EZBRD"
- help
- BF526-EZBRD/EZKIT Lite board support.
-
-config BFIN527_AD7160EVAL
- bool "BF527-AD7160-EVAL"
- help
- BF527-AD7160-EVAL board support.
-
-config BFIN527_TLL6527M
- bool "The Learning Labs TLL6527M"
- help
- TLL6527M V1.0 platform support
-
-endchoice
diff --git a/arch/blackfin/mach-bf527/boards/Makefile b/arch/blackfin/mach-bf527/boards/Makefile
deleted file mode 100644
index 6ada1537e20a..000000000000
--- a/arch/blackfin/mach-bf527/boards/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf527/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN527_EZKIT_V2) += ezkit.o
-obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
-obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o
-obj-$(CONFIG_BFIN527_AD7160EVAL) += ad7160eval.o
-obj-$(CONFIG_BFIN527_TLL6527M) += tll6527m.o
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
deleted file mode 100644
index 68f2a8a806ea..000000000000
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ /dev/null
@@ -1,868 +0,0 @@
-/*
- * Copyright 2004-20010 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
-static struct resource bf52x_ra158z_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_ra158z_device = {
- .name = "bfin-ra158z",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_ra158z_resources),
- .resource = bf52x_ra158z_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ad7160eval_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ad7160eval_flash_data = {
- .width = 2,
- .parts = ad7160eval_partitions,
- .nr_parts = ARRAY_SIZE(ad7160eval_partitions),
-};
-
-static struct resource ad7160eval_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ad7160eval_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ad7160eval_flash_data,
- },
- .num_resources = 1,
- .resource = &ad7160eval_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 30000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PH3 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
-#include <linux/input/ad7160.h>
-static const struct ad7160_platform_data bfin_ad7160_ts_info = {
- .sensor_x_res = 854,
- .sensor_y_res = 480,
- .pressure = 100,
- .filter_coef = 3,
- .coord_pref = AD7160_ORIG_TOP_LEFT,
- .first_touch_window = 5,
- .move_window = 3,
- .event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
- AD7160_EMIT_ABS_MT_PRESSURE |
- AD7160_TRACKING_ID_ASCENDING,
- .finger_act_ctrl = 0x64,
- .haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(60) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW,
-
- .haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
- AD7160_HAPTIC_SLOT_A_LVL_HIGH |
- AD7160_HAPTIC_SLOT_B(80) |
- AD7160_HAPTIC_SLOT_B_LVL_LOW |
- AD7160_HAPTIC_SLOT_C(120) |
- AD7160_HAPTIC_SLOT_C_LVL_HIGH |
- AD7160_HAPTIC_SLOT_D(30) |
- AD7160_HAPTIC_SLOT_D_LVL_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
- {
- I2C_BOARD_INFO("ad7160", 0x33),
- .irq = IRQ_PH1,
- .platform_data = (void *)&bfin_ad7160_ts_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
- &bf52x_ra158z_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ad7160eval_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-};
-
-static int __init ad7160eval_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ad7160eval_init);
-
-static struct platform_device *ad7160eval_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ad7160eval_early_devices,
- ARRAY_SIZE(ad7160eval_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
deleted file mode 100644
index b1004b35db36..000000000000
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ /dev/null
@@ -1,992 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/etherdevice.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF527";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PF11,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cmbf527_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init cm_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(cm_init);
-
-static struct platform_device *cmbf527_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cmbf527_early_devices,
- ARRAY_SIZE(cmbf527_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
deleted file mode 100644
index 80bcfd1d023e..000000000000
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ /dev/null
@@ -1,891 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF526-EZBRD";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezbrd_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezbrd_flash_data = {
- .width = 2,
- .parts = ezbrd_partitions,
- .nr_parts = ARRAY_SIZE(ezbrd_partitions),
-};
-
-static struct resource ezbrd_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezbrd_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezbrd_flash_data,
- },
- .num_resources = 1,
- .resource = &ezbrd_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "sst25wf040",
-};
-
-/* SPI flash chip (sst25wf040) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PG0,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_WM8731) \
- && defined(CONFIG_SND_SOC_WM8731_SPI)
- {
- .modalias = "wm8731",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG0,
- .end = GPIO_PG0,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = GPIO_PG12,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezbrd_flash_device,
-#endif
-};
-
-static int __init ezbrd_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezbrd_init);
-
-static struct platform_device *ezbrd_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezbrd_early_devices,
- ARRAY_SIZE(ezbrd_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
deleted file mode 100644
index 571edfd2ecf3..000000000000
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ /dev/null
@@ -1,1335 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/ad7877.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-#ifdef CONFIG_BFIN527_EZKIT_V2
-const char bfin_board_name[] = "ADI BF527-EZKIT V2";
-#else
-const char bfin_board_name[] = "ADI BF527-EZKIT";
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PG13,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
-
-static struct resource bf52x_t350mcqb_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf52x_t350mcqb_device = {
- .name = "bfin-t350mcqb",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf52x_t350mcqb_resources),
- .resource = bf52x_t350mcqb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_8_BIT_PPI,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x40000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = NFC_CTL,
- .end = NFC_DATA_RD + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB800 + 4,
- .end = 0x203FB800 + 5,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 0, /* Export GPIO to gpiolib */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-
-static const u16 bfin_snd_pin[][7] = {
- {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
- {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836",
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF8,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(3, 3)] = KEY_1,
- [ADP5520_KEY(2, 3)] = KEY_2,
- [ADP5520_KEY(1, 3)] = KEY_3,
- [ADP5520_KEY(0, 3)] = KEY_UP,
- [ADP5520_KEY(3, 2)] = KEY_4,
- [ADP5520_KEY(2, 2)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(0, 2)] = KEY_DOWN,
- [ADP5520_KEY(3, 1)] = KEY_7,
- [ADP5520_KEY(2, 1)] = KEY_8,
- [ADP5520_KEY(1, 1)] = KEY_9,
- [ADP5520_KEY(0, 1)] = KEY_DOT,
- [ADP5520_KEY(3, 0)] = KEY_BACKSPACE,
- [ADP5520_KEY(2, 0)] = KEY_0,
- [ADP5520_KEY(1, 0)] = KEY_HELP,
- [ADP5520_KEY(0, 0)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .leds = &adp5520_leds_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PF8,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PF8,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PF9,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static const u16 per_cnt[] = {
- P_CNT_CUD,
- P_CNT_CDG,
- P_CNT_CZM,
- 0
-};
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
- .pin_list = per_cnt,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_T350MCQB)
- &bf52x_t350mcqb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
deleted file mode 100644
index ce5488e8226b..000000000000
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ /dev/null
@@ -1,946 +0,0 @@
-/* File: arch/blackfin/mach-bf527/boards/tll6527m.c
- * Based on: arch/blackfin/mach-bf527/boards/ezkit.c
- * Author: Ashish Gupta
- *
- * Copyright: 2010 - The Learning Labs Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-#define LCD_BACKLIGHT_GPIO 0x40
-/* TLL6527M uses TLL7UIQ35 / ADI LCD EZ Extender. AD7879 AUX GPIO is used for
- * LCD Backlight Enable
- */
-#endif
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "TLL6527M";
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xffc03800,
- .end = 0xffc03cff,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- /*.gpio_vrsel = GPIO_PG13,*/
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 1,
- .gpio_bl = LCD_BACKLIGHT_GPIO,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition tll6527m_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0xA0000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0xD00000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data tll6527m_flash_data = {
- .width = 2,
- .parts = tll6527m_partitions,
- .nr_parts = ARRAY_SIZE(tll6527m_partitions),
-};
-
-static unsigned tll6527m_flash_gpios[] = { GPIO_PG11, GPIO_PH11, GPIO_PH12 };
-
-static struct resource tll6527m_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)tll6527m_flash_gpios,
- .end = ARRAY_SIZE(tll6527m_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device tll6527m_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &tll6527m_flash_data,
- },
- .num_resources = ARRAY_SIZE(tll6527m_flash_resource),
- .resource = tll6527m_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
-/* An SN74LVC138A 3:8 decoder chip has been used to generate 7 augmented
- * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
- * EXP_GPIO_SPISEL_BASE is the base number for the expanded outputs being
- * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
- */
-#include <linux/gpio-decoder.h>
-#define EXP_GPIO_SPISEL_BASE 0x64
-static unsigned gpio_addr_inputs[] = {
- GPIO_PG1, GPIO_PH9, GPIO_PH10
-};
-
-static struct gpio_decoder_platform_data spi_decoded_cs = {
- .base = EXP_GPIO_SPISEL_BASE,
- .input_addrs = gpio_addr_inputs,
- .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
- .default_output = 0,
-/* .default_output = (1 << ARRAY_SIZE(gpio_addr_inputs)) - 1 */
-};
-
-static struct platform_device spi_decoded_gpio = {
- .name = "gpio-decoder",
- .id = 0,
- .dev = {
- .platform_data = &spi_decoded_cs,
- },
-};
-
-#else
-#define EXP_GPIO_SPISEL_BASE 0x0
-
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl345_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 2,
- .inactivity_time = 2,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
- .ev_code_act_inactivity = KEY_A, /* EV_KEY */
- .use_int2 = 1,
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3,
- /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1,
- /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* configure AUX as GPIO output*/
- .gpio_base = LCD_BACKLIGHT_GPIO,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = {
- .spi_present_mask = BIT(0),
- .base = 0x30,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = {
- .spi_present_mask = BIT(2),
- .base = 0x38,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x04 + MAX_CTRL_CS,
- /* Can be connected to TLL6527M GPIO connector */
- /* Either SPI_ADC or M25P80 FLASH can be installed at a time */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
-/*
- * TLL6527M V1.0 does not support SD Card at SPI Clock > 10 MHz due to
- * SPI buffer limitations
- */
- .max_speed_hz = 10000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x05 + MAX_CTRL_CS,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PH14,
- .max_speed_hz = 5000000,
- /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x07 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 10000000,
- /* TLL6527Mv1-0 supports max spi clock (SCK) speed = 10 MHz */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x03 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x06 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_sys_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x01 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
- {
- .modalias = "mcp23s08",
- .platform_data = &bfin_mcp23s08_usr_gpio_info,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = EXP_GPIO_SPISEL_BASE + 0x02 + MAX_CTRL_CS,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = EXP_GPIO_SPISEL_BASE + 8 + MAX_CTRL_CS,
- /* EXP_GPIO_SPISEL_BASE will be > MAX_BLACKFIN_GPIOS */
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin */
- .start = GPIO_PF9,
- .end = GPIO_PF9,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PF10,
- .end = GPIO_PF10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2C),
- .irq = IRQ_PH14,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
- {
- I2C_BOARD_INFO("adm1192", 0x2e),
- },
-
- {
- I2C_BOARD_INFO("ltc3576", 0x09),
- },
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PH13,
- .platform_data = (void *)&adxl345_info,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals,
- /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_100, 400000000),
- VRPAIR(VLEV_105, 426000000),
- VRPAIR(VLEV_110, 500000000),
- VRPAIR(VLEV_115, 533000000),
- VRPAIR(VLEV_120, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *tll6527m_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &tll6527m_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_DECODER)
- &spi_decoded_gpio,
-#endif
-};
-
-static int __init tll6527m_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- platform_add_devices(tll6527m_devices, ARRAY_SIZE(tll6527m_devices));
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(tll6527m_init);
-
-static struct platform_device *tll6527m_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tll6527m_early_devices,
- ARRAY_SIZE(tll6527m_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- /* the MAC is stored in OTP memory page 0xDF */
- u32 ret;
- u64 otp_mac;
- u32 (*otp_read)(u32 page, u32 flags,
- u64 *page_content) = (void *)0xEF00001A;
-
- ret = otp_read(0xDF, 0x00, &otp_mac);
- if (!(ret & 0x1)) {
- char *otp_mac_p = (char *)&otp_mac;
- for (ret = 0; ret < 6; ++ret)
- addr[ret] = otp_mac_p[5 - ret];
- }
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
deleted file mode 100644
index 1fabdefea73a..000000000000
--- a/arch/blackfin/mach-bf527/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * This file contains the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
deleted file mode 100644
index 2f9cc33deec4..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bf527.h b/arch/blackfin/mach-bf527/include/mach/bf527.h
deleted file mode 100644
index 8ff155b34f64..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bf527.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF527_H__
-#define __MACH_BF527_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-/**************************** Hysteresis Settings ****************************/
-
-#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-#ifdef CONFIG_GPIO_HYST_PORTF_0_7
-#define HYST_PORTF_0_7 (1 << 0)
-#else
-#define HYST_PORTF_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_8_9
-#define HYST_PORTF_8_9 (1 << 2)
-#else
-#define HYST_PORTF_8_9 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_10
-#define HYST_PORTF_10 (1 << 4)
-#else
-#define HYST_PORTF_10 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_11
-#define HYST_PORTF_11 (1 << 6)
-#else
-#define HYST_PORTF_11 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_12_13
-#define HYST_PORTF_12_13 (1 << 8)
-#else
-#define HYST_PORTF_12_13 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTF_14_15
-#define HYST_PORTF_14_15 (1 << 10)
-#else
-#define HYST_PORTF_14_15 (0 << 10)
-#endif
-
-#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
- HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTG_0
-#define HYST_PORTG_0 (1 << 0)
-#else
-#define HYST_PORTG_0 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_1_4
-#define HYST_PORTG_1_4 (1 << 2)
-#else
-#define HYST_PORTG_1_4 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_5_6
-#define HYST_PORTG_5_6 (1 << 4)
-#else
-#define HYST_PORTG_5_6 (0 << 4)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_7_8
-#define HYST_PORTG_7_8 (1 << 6)
-#else
-#define HYST_PORTG_7_8 (0 << 6)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_9
-#define HYST_PORTG_9 (1 << 8)
-#else
-#define HYST_PORTG_9 (0 << 8)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_10
-#define HYST_PORTG_10 (1 << 10)
-#else
-#define HYST_PORTG_10 (0 << 10)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_11_13
-#define HYST_PORTG_11_13 (1 << 12)
-#else
-#define HYST_PORTG_11_13 (0 << 12)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTG_14_15
-#define HYST_PORTG_14_15 (1 << 14)
-#else
-#define HYST_PORTG_14_15 (0 << 14)
-#endif
-
-#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
- HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
- HYST_PORTG_11_13 | HYST_PORTG_14_15)
-
-#ifdef CONFIG_GPIO_HYST_PORTH_0_7
-#define HYST_PORTH_0_7 (1 << 0)
-#else
-#define HYST_PORTH_0_7 (0 << 0)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_8
-#define HYST_PORTH_8 (1 << 2)
-#else
-#define HYST_PORTH_8 (0 << 2)
-#endif
-#ifdef CONFIG_GPIO_HYST_PORTH_9_15
-#define HYST_PORTH_9_15 (1 << 4)
-#else
-#define HYST_PORTH_9_15 (0 << 4)
-#endif
-
-#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
-
-#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
-#define HYST_TMR0_FS1_PPICLK (1 << 0)
-#else
-#define HYST_TMR0_FS1_PPICLK (0 << 0)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
-#define HYST_NMI_RST_BMODE (1 << 2)
-#else
-#define HYST_NMI_RST_BMODE (0 << 2)
-#endif
-#ifdef CONFIG_NONEGPIO_HYST_JTAG
-#define HYST_JTAG (1 << 4)
-#else
-#define HYST_JTAG (0 << 4)
-#endif
-
-#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
-#define HYST_NONEGPIO_MASK (0x3F)
-#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
-
-#ifdef CONFIG_BF527
-#define CPU "BF527"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF526
-#define CPU "BF526"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF525
-#define CPU "BF525"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF524
-#define CPU "BF524"
-#define CPUID 0x27e4
-#endif
-#ifdef CONFIG_BF523
-#define CPU "BF523"
-#define CPUID 0x27e0
-#endif
-#ifdef CONFIG_BF522
-#define CPU "BF522"
-#define CPUID 0x27e4
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF527_H__ */
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603fe8218..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
deleted file mode 100644
index e1d279274487..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf527.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "defBF522.h"
-#endif
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "defBF525.h"
-#endif
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "defBF527.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
-# include "cdefBF522.h"
-# endif
-# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-# include "cdefBF525.h"
-# endif
-# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-# include "cdefBF527.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
deleted file mode 100644
index 2c12e879aa4e..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ /dev/null
@@ -1,1095 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
-#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-#endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
deleted file mode 100644
index bd045318a250..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "cdefBF522.h"
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
deleted file mode 100644
index eb22f5866105..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "cdefBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* _CDEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
deleted file mode 100644
index e007017cf958..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ /dev/null
@@ -1,1309 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
-#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX 0xFFC03210 /* Port F mux control */
-#define PORTG_MUX 0xFFC03214 /* Port G mux control */
-#define PORTH_MUX 0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
-#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-
-#if 0
-#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
-
-#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
-#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
-#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
-#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
-#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
-
-#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
-#define IRQ_TWI 0x00000200 /* TWI Interrupt */
-#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
-#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
-#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
-#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
-#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
-#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
-
-#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
-#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
-#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
-#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
-#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
-#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
-#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
-#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
-#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
-#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
-
-#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
-#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
-#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
-#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
-#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
-#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
-#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
-#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
-#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
-#endif
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
-#define HOST_STATUS 0xffc03404 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc03500 /* Configuration Register */
-#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc03508 /* Status Register */
-#define CNT_COMMAND 0xffc0350c /* Command Register */
-#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
-#define CNT_COUNTER 0xffc03514 /* Counter Register */
-#define CNT_MAX 0xffc03518 /* Maximal Count Register */
-#define CNT_MIN 0xffc0351c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc03624 /* Secure Control */
-#define SECURE_STATUS 0xffc03628 /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03700 /* NAND Control Register */
-#define NFC_STAT 0xffc03704 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
-#define NFC_READ 0xffc0372c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03740 /* NAND Address Register */
-#define NFC_CMD 0xffc03744 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
-#define HOST_CNTR_nHOST_EN 0x0
-#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
-#define HOST_CNTR_nHOST_END 0x0
-#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
-#define HOST_CNTR_nDATA_SIZE 0x0
-#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
-#define HOST_CNTR_nHOST_RST 0x0
-#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
-#define HOST_CNTR_nHRDY_OVR 0x0
-#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
-#define HOST_CNTR_nINT_MODE 0x0
-#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
-#define HOST_CNTR_ nBT_EN 0x0
-#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
-#define HOST_CNTR_nEHW 0x0
-#define HOST_CNTR_EHR 0x200 /* Enable Host Read */
-#define HOST_CNTR_nEHR 0x0
-#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */
-#define HOST_CNTR_nBDR 0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define HOST_STAT_READY 0x1 /* DMA Ready */
-#define HOST_STAT_nREADY 0x0
-#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */
-#define HOST_STAT_nFIFOFULL 0x0
-#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */
-#define HOST_STAT_nFIFOEMPTY 0x0
-#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */
-#define HOST_STAT_nCOMPLETE 0x0
-#define HOST_STAT_HSHK 0x10 /* Host Handshake */
-#define HOST_STAT_nHSHK 0x0
-#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */
-#define HOST_STAT_nTIMEOUT 0x0
-#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */
-#define HOST_STAT_nHIRQ 0x0
-#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */
-#define HOST_STAT_nALLOW_CNFG 0x0
-#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */
-#define HOST_STAT_nDMA_DIR 0x0
-#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */
-#define HOST_STAT_nBTE 0x0
-#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
-#define HOST_STAT_nHOSTRD_DONE 0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define nEMUDABL 0x0
-#define RSTDABL 0x2 /* Reset Disable */
-#define nRSTDABL 0x0
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define nDMA0OVR 0x0
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define nDMA1OVR 0x0
-#define EMUOVR 0x4000 /* Emulation Override */
-#define nEMUOVR 0x0
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define nOTPSEN 0x0
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define nSECURE0 0x0
-#define SECURE1 0x2 /* SECURE 1 */
-#define nSECURE1 0x0
-#define SECURE2 0x4 /* SECURE 2 */
-#define nSECURE2 0x0
-#define SECURE3 0x8 /* SECURE 3 */
-#define nSECURE3 0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define nNMI 0x0
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define nAFVALID 0x0
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define nAFEXIT 0x0
-#define SECSTAT 0xe0 /* Secure Status */
-
-#endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
deleted file mode 100644
index 591e00ff620a..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* BF525 is BF522 + USB */
-#include "defBF522.h"
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03800 /* Function address register */
-#define USB_POWER 0xffc03804 /* Power management register */
-#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03820 /* USB frame number */
-#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
-
-#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define nENABLE_SUSPENDM 0x0
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define nSUSPEND_MODE 0x0
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define nRESUME_MODE 0x0
-#define RESET 0x8 /* Reset indicator */
-#define nRESET 0x0
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define nHS_MODE 0x0
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define nHS_ENABLE 0x0
-#define SOFT_CONN 0x40 /* Soft connect */
-#define nSOFT_CONN 0x0
-#define ISO_UPDATE 0x80 /* Isochronous update */
-#define nISO_UPDATE 0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define nEP0_TX 0x0
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define nEP1_TX 0x0
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define nEP2_TX 0x0
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define nEP3_TX 0x0
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define nEP4_TX 0x0
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define nEP5_TX 0x0
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define nEP6_TX 0x0
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-#define nEP7_TX 0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define nEP1_RX 0x0
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define nEP2_RX 0x0
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define nEP3_RX 0x0
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define nEP4_RX 0x0
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define nEP5_RX 0x0
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define nEP6_RX 0x0
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-#define nEP7_RX 0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define nEP0_TX_E 0x0
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define nEP1_TX_E 0x0
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define nEP2_TX_E 0x0
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define nEP3_TX_E 0x0
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define nEP4_TX_E 0x0
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define nEP5_TX_E 0x0
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define nEP6_TX_E 0x0
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-#define nEP7_TX_E 0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define nEP1_RX_E 0x0
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define nEP2_RX_E 0x0
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define nEP3_RX_E 0x0
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define nEP4_RX_E 0x0
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define nEP5_RX_E 0x0
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define nEP6_RX_E 0x0
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-#define nEP7_RX_E 0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define nSUSPEND_B 0x0
-#define RESUME_B 0x2 /* Resume indicator */
-#define nRESUME_B 0x0
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define nRESET_OR_BABLE_B 0x0
-#define SOF_B 0x8 /* Start of frame */
-#define nSOF_B 0x0
-#define CONN_B 0x10 /* Connection indicator */
-#define nCONN_B 0x0
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define nDISCON_B 0x0
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define nSESSION_REQ_B 0x0
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-#define nVBUS_ERROR_B 0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define nSUSPEND_BE 0x0
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define nRESUME_BE 0x0
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define nRESET_OR_BABLE_BE 0x0
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define nSOF_BE 0x0
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define nCONN_BE 0x0
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define nDISCON_BE 0x0
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define nSESSION_REQ_BE 0x0
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-#define nVBUS_ERROR_BE 0x0
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define nGLOBAL_ENA 0x0
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define nEP1_TX_ENA 0x0
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define nEP2_TX_ENA 0x0
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define nEP3_TX_ENA 0x0
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define nEP4_TX_ENA 0x0
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define nEP5_TX_ENA 0x0
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define nEP6_TX_ENA 0x0
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define nEP7_TX_ENA 0x0
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define nEP1_RX_ENA 0x0
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define nEP2_RX_ENA 0x0
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define nEP3_RX_ENA 0x0
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define nEP4_RX_ENA 0x0
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define nEP5_RX_ENA 0x0
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define nEP6_RX_ENA 0x0
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-#define nEP7_RX_ENA 0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define nSESSION 0x0
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define nHOST_REQ 0x0
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define nHOST_MODE 0x0
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define nVBUS0 0x0
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define nVBUS1 0x0
-#define LSDEV 0x20 /* Low-speed indicator */
-#define nLSDEV 0x0
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define nFSDEV 0x0
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-#define nB_DEVICE 0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define nDRIVE_VBUS_ON 0x0
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define nDRIVE_VBUS_OFF 0x0
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define nCHRG_VBUS_START 0x0
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define nCHRG_VBUS_END 0x0
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define nDISCHRG_VBUS_START 0x0
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-#define nDISCHRG_VBUS_END 0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define nDRIVE_VBUS_ON_ENA 0x0
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define nDRIVE_VBUS_OFF_ENA 0x0
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define nCHRG_VBUS_START_ENA 0x0
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define nCHRG_VBUS_END_ENA 0x0
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define nDISCHRG_VBUS_START_ENA 0x0
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-#define nDISCHRG_VBUS_END_ENA 0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define nRXPKTRDY 0x0
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define nTXPKTRDY 0x0
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define nSTALL_SENT 0x0
-#define DATAEND 0x8 /* Data end indicator */
-#define nDATAEND 0x0
-#define SETUPEND 0x10 /* Setup end */
-#define nSETUPEND 0x0
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define nSENDSTALL 0x0
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define nSERVICED_RXPKTRDY 0x0
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define nSERVICED_SETUPEND 0x0
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define nFLUSHFIFO 0x0
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define nSTALL_RECEIVED_H 0x0
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define nSETUPPKT_H 0x0
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define nERROR_H 0x0
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define nREQPKT_H 0x0
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define nSTATUSPKT_H 0x0
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-#define nNAK_TIMEOUT_H 0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define nTXPKTRDY_T 0x0
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define nFIFO_NOT_EMPTY_T 0x0
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define nUNDERRUN_T 0x0
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define nFLUSHFIFO_T 0x0
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define nSTALL_SEND_T 0x0
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define nSTALL_SENT_T 0x0
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_T 0x0
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define nINCOMPTX_T 0x0
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_T 0x0
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define nFORCE_DATATOGGLE_T 0x0
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_T 0x0
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define nISO_T 0x0
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOSET_T 0x0
-#define ERROR_TH 0x4 /* error condition host mode */
-#define nERROR_TH 0x0
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_TH 0x0
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-#define nNAK_TIMEOUT_TH 0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define nRXPKTRDY_R 0x0
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define nFIFO_FULL_R 0x0
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define nOVERRUN_R 0x0
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define nDATAERROR_R 0x0
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define nFLUSHFIFO_R 0x0
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define nSTALL_SEND_R 0x0
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define nSTALL_SENT_R 0x0
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define nCLEAR_DATATOGGLE_R 0x0
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define nINCOMPRX_R 0x0
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define nDMAREQMODE_R 0x0
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define nDISNYET_R 0x0
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define nDMAREQ_ENA_R 0x0
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define nISO_R 0x0
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define nAUTOCLEAR_R 0x0
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define nERROR_RH 0x0
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define nREQPKT_RH 0x0
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define nSTALL_RECEIVED_RH 0x0
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define nINCOMPRX_RH 0x0
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define nDMAREQMODE_RH 0x0
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-#define nAUTOREQ_RH 0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define nDMA0_INT 0x0
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define nDMA1_INT 0x0
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define nDMA2_INT 0x0
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define nDMA3_INT 0x0
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define nDMA4_INT 0x0
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define nDMA5_INT 0x0
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define nDMA6_INT 0x0
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-#define nDMA7_INT 0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define nDMA_ENA 0x0
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define nDIRECTION 0x0
-#define MODE 0x4 /* DMA Bus error */
-#define nMODE 0x0
-#define INT_ENA 0x8 /* Interrupt enable */
-#define nINT_ENA 0x0
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-#define nBUSERROR 0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
deleted file mode 100644
index aeb84795b35e..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ /dev/null
@@ -1,391 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* BF527 is BF525 + EMAC */
-#include "defBF525.h"
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF527_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/dma.h b/arch/blackfin/mach-bf527/include/mach/dma.h
deleted file mode 100644
index eb287da101a2..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/dma.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0 /* PPI receive/transmit or NFC */
-#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
-#define CH_SPORT0_RX 3 /* SPORT0 receive */
-#define CH_SPORT0_TX 4 /* SPORT0 transmit */
-#define CH_SPORT1_RX 5 /* SPORT1 receive */
-#define CH_SPORT1_TX 6 /* SPORT1 transmit */
-#define CH_SPI 7 /* SPI transmit/receive */
-#define CH_UART0_RX 8 /* UART0 receive */
-#define CH_UART0_TX 9 /* UART0 transmit */
-#define CH_UART1_RX 10 /* UART1 receive */
-#define CH_UART1_TX 11 /* UART1 transmit */
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
deleted file mode 100644
index fba606b699c3..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
deleted file mode 100644
index ed7310ff819b..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF527_IRQ_H_
-#define _BF527_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
-#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
-#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
-#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
-#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
-#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
-#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
-#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
-#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
-#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
-#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
-#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
-
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS 0
-#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS 0
-#define IRQ_SPORT0_TX_POS 4
-#define IRQ_SPORT1_RX_POS 8
-#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
-#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
-#define IRQ_PORTH_INTB_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_TIMER3_POS 12
-#define IRQ_TIMER4_POS 16
-#define IRQ_TIMER5_POS 20
-#define IRQ_TIMER6_POS 24
-#define IRQ_TIMER7_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS 0
-#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
-#define IRQ_PORTF_INTA_POS 20
-#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI_ERROR_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS 0
-#define IRQ_HDMA_ERROR_POS 4
-#define IRQ_HDMA_POS 8
-#define IRQ_USB_EINT_POS 12
-#define IRQ_USB_INT0_POS 16
-#define IRQ_USB_INT1_POS 20
-#define IRQ_USB_INT2_POS 24
-#define IRQ_USB_DMA_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/mem_map.h b/arch/blackfin/mach-bf527/include/mach/mem_map.h
deleted file mode 100644
index d96e894afd2c..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/mem_map.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BF52x memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE */
-
-#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/portmux.h b/arch/blackfin/mach-bf527/include/mach/portmux.h
deleted file mode 100644
index 08bae421f5c9..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/portmux.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if defined(CONFIG_BF527_SPORT0_PORTF)
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_UART1_PORTF)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT (P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf527/ints-priority.c b/arch/blackfin/mach-bf527/ints-priority.c
deleted file mode 100644
index 44ca215bf164..000000000000
--- a/arch/blackfin/mach-bf527/ints-priority.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
- ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
- ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
- ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
-
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
- ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
- ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
- ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf533/Kconfig b/arch/blackfin/mach-bf533/Kconfig
deleted file mode 100644
index 4e1a05be7137..000000000000
--- a/arch/blackfin/mach-bf533/Kconfig
+++ /dev/null
@@ -1,96 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF533 || BF532 || BF531)
-
-source "arch/blackfin/mach-bf533/boards/Kconfig"
-
-menu "BF533/2/1 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config UART_ERROR
- int "UART ERROR"
- default 7
-config SPORT0_ERROR
- int "SPORT0 ERROR"
- default 7
-config SPI_ERROR
- int "SPI ERROR"
- default 7
-config SPORT1_ERROR
- int "SPORT1 ERROR"
- default 7
-config PPI_ERROR
- int "PPI ERROR"
- default 7
-config DMA_ERROR
- int "DMA ERROR"
- default 7
-config PLLWAKE_ERROR
- int "PLL WAKEUP ERROR"
- default 7
-
-config RTC_ERROR
- int "RTC ERROR"
- default 8
-config DMA0_PPI
- int "DMA0 PPI"
- default 8
-
-config DMA1_SPORT0RX
- int "DMA1 (SPORT0 RX)"
- default 9
-config DMA2_SPORT0TX
- int "DMA2 (SPORT0 TX)"
- default 9
-config DMA3_SPORT1RX
- int "DMA3 (SPORT1 RX)"
- default 9
-config DMA4_SPORT1TX
- int "DMA4 (SPORT1 TX)"
- default 9
-config DMA5_SPI
- int "DMA5 (SPI)"
- default 10
-config DMA6_UARTRX
- int "DMA6 (UART0 RX)"
- default 10
-config DMA7_UARTTX
- int "DMA7 (UART0 TX)"
- default 10
-config TIMER0
- int "TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config TIMER1
- int "TIMER1"
- default 11
-config TIMER2
- int "TIMER2"
- default 11
-config PFA
- int "PF Interrupt A"
- default 12
-config PFB
- int "PF Interrupt B"
- default 12
-config MEMDMA0
- int "MEMORY DMA0"
- default 13
-config MEMDMA1
- int "MEMORY DMA1"
- default 13
-config WDTIMER
- int "WATCH DOG TIMER"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
deleted file mode 100644
index 874840f76028..000000000000
--- a/arch/blackfin/mach-bf533/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf533/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
deleted file mode 100644
index 01300f40db15..000000000000
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007-2008 HV Sistemas S.L.
- * Javier Herrero <jherrero@hvsistemas.es>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "HV Sistemas H8606";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
-* Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x20300000,
- .end = 0x20300002,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x20300004,
- .end = 0x20300006,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
- IORESOURCE_IRQ_SHAREABLE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .id = 0,
- .name = "dm9000",
- .resource = dm9000_resources,
- .num_resources = ARRAY_SIZE(dm9000_resources),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader (spi)",
- .size = 0x40000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "fpga (spi)",
- .size = 0x30000,
- .offset = 0x40000
- }, {
- .name = "linux kernel (spi)",
- .size = 0x150000,
- .offset = 0x70000
- }, {
- .name = "jffs2 root file system (spi)",
- .size = 0x640000,
- .offset = 0x1c0000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- /* this value is the baudrate divisor */
- .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 16,
- .bus_num = 1,
- .chip_select = 4,
- },
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
-
-#include <linux/serial_8250.h>
-#include <linux/serial.h>
-
-/*
- * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
- * running at half system clock, both with interrupt output or-ed to PF8. Change to
- * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
- */
-
-static struct plat_serial8250_port serial8250_platform_data [] = {
- {
- .membase = (void *)0x20200000,
- .mapbase = 0x20200000,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- .membase = (void *)0x20200010,
- .mapbase = 0x20200010,
- .irq = IRQ_PF8,
- .irqflags = IRQF_TRIGGER_HIGH,
- .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
- .iotype = UPIO_MEM,
- .regshift = 1,
- .uartclk = 66666667,
- }, {
- }
-};
-
-static struct platform_device serial8250_device = {
- .id = PLAT8250_DEV_PLATFORM,
- .name = "serial8250",
- .dev = {
- .platform_data = serial8250_platform_data,
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
-
-/*
- * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
- * interrupt output wired to PF9. Change to suit different FPGA configuration
- */
-
-static struct resource opencores_kbd_resources[] = {
- [0] = {
- .start = 0x20200030,
- .end = 0x20300030 + 2,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct platform_device opencores_kbd_device = {
- .id = -1,
- .name = "opencores-kbd",
- .resource = opencores_kbd_resources,
- .num_resources = ARRAY_SIZE(opencores_kbd_resources),
-};
-#endif
-
-static struct platform_device *h8606_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_8250)
- &serial8250_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_OPENCORES)
- &opencores_kbd_device,
-#endif
-};
-
-static int __init H8606_init(void)
-{
- printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(H8606_init);
-
-static struct platform_device *H8606_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(H8606_early_devices,
- ARRAY_SIZE(H8606_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig
deleted file mode 100644
index 3fde0df1b5f2..000000000000
--- a/arch/blackfin/mach-bf533/boards/Kconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN533_STAMP
- help
- Select your board!
-
-config BFIN533_EZKIT
- bool "BF533-EZKIT"
- help
- BF533-EZKIT-LITE board support.
-
-config BFIN533_STAMP
- bool "BF533-STAMP"
- help
- BF533-STAMP board support.
-
-config BLACKSTAMP
- bool "BlackStamp"
- help
- Support for the BlackStamp board. Hardware info available at
- http://blackfin.uclinux.org/gf/project/blackstamp/
-
-config BFIN533_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF533"
- depends on (BF533)
- help
- CM-BF533 support for EVAL- and DEV-Board.
-
-config H8606_HVSISTEMAS
- bool "HV Sistemas H8606"
- depends on (BF532)
- help
- HV Sistemas H8606 board support.
-
-config BFIN532_IP0X
- bool "IP04/IP08 IP-PBX"
- depends on (BF532)
- help
- Core support for IP04/IP04 open hardware IP-PBX.
-
-endchoice
diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile
deleted file mode 100644
index 35256d2fc040..000000000000
--- a/arch/blackfin/mach-bf533/boards/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf533/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN533_STAMP) += stamp.o
-obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
-obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o
-obj-$(CONFIG_BLACKSTAMP) += blackstamp.o
-obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
deleted file mode 100644
index fab69c736515..000000000000
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
- * Board Info File for the BlackStamp
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * 2008 Benjamin Matthews <bmat@lle.rochester.edu>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * More info about the BlackStamp at:
- * http://blackfin.uclinux.org/gf/project/blackstamp/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "BlackStamp";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. */
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 7,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF4, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF5, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF6, 0, "gpio-keys: BTN2"},
-}; /* Mapped to the first three PF Test Points */
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF8, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF9, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-}; /* This hasn't actually been used these pins
- * are (currently) free pins on the expansion connector */
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-};
-
-static int __init blackstamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(blackstamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
deleted file mode 100644
index 4ef2fb0e48d5..000000000000
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF533";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x20308000,
- .end = 0x20308000 + 0xFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF6,
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux+rootfs(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &para_flash_data,
- },
- .num_resources = 1,
- .resource = &para_flash_resource,
-};
-#endif
-
-
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf533_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &para_flash_device,
-#endif
-};
-
-static int __init cm_bf533_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(cm_bf533_init);
-
-static struct platform_device *cm_bf533_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf533_early_devices,
- ARRAY_SIZE(cm_bf533_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
deleted file mode 100644
index d64d270e9e62..000000000000
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ /dev/null
@@ -1,551 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-EZKIT";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions_a[] = {
- {
- .name = "bootloader(nor a)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor a)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_a = {
- .width = 2,
- .parts = ezkit_partitions_a,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_a),
-};
-
-static struct resource ezkit_flash_resource_a = {
- .start = 0x20000000,
- .end = 0x200fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_a = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data_a,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_a,
-};
-
-static struct mtd_partition ezkit_partitions_b[] = {
- {
- .name = "file system(nor b)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct physmap_flash_data ezkit_flash_data_b = {
- .width = 2,
- .parts = ezkit_partitions_b,
- .nr_parts = ARRAY_SIZE(ezkit_partitions_b),
-};
-
-static struct resource ezkit_flash_resource_b = {
- .start = 0x20100000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device_b = {
- .name = "physmap-flash",
- .id = 4,
- .dev = {
- .platform_data = &ezkit_flash_data_b,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram sram_data_a = {
- .mapname = "Flash A SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_a = {
- .start = 0x20240000,
- .end = 0x2024ffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_a = {
- .name = "mtd-ram",
- .id = 8,
- .dev = {
- .platform_data = &sram_data_a,
- },
- .num_resources = 1,
- .resource = &sram_resource_a,
-};
-
-static struct platdata_mtd_ram sram_data_b = {
- .mapname = "Flash B SRAM",
- .bankwidth = 2,
-};
-
-static struct resource sram_resource_b = {
- .start = 0x202c0000,
- .end = 0x202cffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device sram_device_b = {
- .name = "mtd-ram",
- .id = 9,
- .dev = {
- .platform_data = &sram_data_b,
- },
- .num_resources = 1,
- .resource = &sram_resource_b,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF7, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF8, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF9, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF10, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 40,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device_a,
- &ezkit_flash_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &sram_device_a,
- &sram_device_b,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
deleted file mode 100644
index 39c8e8547b82..000000000000
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2007 David Rowe
- * 2006 Intratrade Ltd.
- * Ivan Danov <idanov@gmail.com>
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "IP04/IP08";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
-
-#include <linux/dm9000.h>
-
-static struct resource dm9000_resource1[] = {
- {
- .start = 0x20100000,
- .end = 0x20100000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20100000 + 2,
- .end = 0x20100000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-static struct resource dm9000_resource2[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 1,
- .flags = IORESOURCE_MEM
- },{
- .start = 0x20200000 + 2,
- .end = 0x20200000 + 3,
- .flags = IORESOURCE_MEM
- },{
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
- }
-};
-
-/*
-* for the moment we limit ourselves to 16bit IO until some
-* better IO routines can be written and tested
-*/
-static struct dm9000_plat_data dm9000_platdata1 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device1 = {
- .name = "dm9000",
- .id = 0,
- .num_resources = ARRAY_SIZE(dm9000_resource1),
- .resource = dm9000_resource1,
- .dev = {
- .platform_data = &dm9000_platdata1,
- }
-};
-
-static struct dm9000_plat_data dm9000_platdata2 = {
- .flags = DM9000_PLATF_16BITONLY,
-};
-
-static struct platform_device dm9000_device2 = {
- .name = "dm9000",
- .id = 1,
- .num_resources = ARRAY_SIZE(dm9000_resource2),
- .resource = dm9000_resource2,
- .dev = {
- .platform_data = &dm9000_platdata2,
- }
-};
-
-#endif
-#endif
-
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* if 1 - block!!! */
-};
-#endif
-
-/* Notice: for blackfin, the speed_hz is the value of register
- * SPI_BAUD, not the real baudrate */
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 2,
- .bus_num = 1,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi-master",
- .id = 1, /* Bus number */
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 1,
- .flags = IORESOURCE_MEM,
- },{
- .start = 0x20300000 + 2,
- .end = 0x20300000 + 3,
- .flags = IORESOURCE_MEM,
- },{
- .start = IRQ_PF11,
- .end = IRQ_PF11,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0, /* external OC */
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-
-static struct platform_device *ip0x_devices[] __initdata = {
-#if defined(CONFIG_BFIN532_IP0X)
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device1,
- &dm9000_device2,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-};
-
-static int __init ip0x_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ip0x_init);
-
-static struct platform_device *ip0x_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ip0x_early_devices,
- ARRAY_SIZE(ip0x_early_devices));
-}
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
deleted file mode 100644
index 27cbf2fa2c62..000000000000
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ /dev/null
@@ -1,919 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/mmc_spi.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF533-STAMP";
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-};
-
-static struct resource stamp_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x7BB07BB0, /* AMBCTL0 setting when accessing flash */
- .end = 0x7BB07BB0, /* AMBCTL1 setting when accessing flash */
- .flags = IORESOURCE_MEM,
- }, {
- .start = GPIO_PF0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "bfin-async-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = ARRAY_SIZE(stamp_flash_resource),
- .resource = stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
- "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF2, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF3, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#if IS_ENABLED(CONFIG_JOYSTICK_AD7142)
- {
- I2C_BOARD_INFO("ad7142_joystick", 0x2C),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 39,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 600000000),
- VRPAIR(VLEV_125, 600000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#include <asm/bfin_sport.h>
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
-static struct platform_device bfin_ad74111_codec_device = {
- .name = "ad74111",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources =
- ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_BFIN_ASYNC)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD74111)
- &bfin_ad74111_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- /* Set PF0 to 0, PF1 to 1 make /AMS3 work properly */
- ret = gpio_request(GPIO_PF0, "net2272");
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PF1, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- return ret;
- }
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret) {
- gpio_free(GPIO_PF0);
- gpio_free(GPIO_PF1);
- return ret;
- }
-
- gpio_direction_output(GPIO_PF0, 0);
- gpio_direction_output(GPIO_PF1, 1);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
-
- ret = platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- /*
- * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
- * the bfin-async-map driver takes care of flipping between
- * flash and ethernet when necessary.
- */
- ret = gpio_request(GPIO_PF0, "enet_cpld");
- if (!ret) {
- gpio_direction_output(GPIO_PF0, 1);
- gpio_free(GPIO_PF0);
- }
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround pull up on cpld / flash pin not being strong enough */
- gpio_request(GPIO_PF0, "flash_cpld");
- gpio_direction_output(GPIO_PF0, 0);
-}
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
deleted file mode 100644
index 1f5988d43139..000000000000
--- a/arch/blackfin/mach-bf533/dma.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
deleted file mode 100644
index 0e754efc3cf6..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent False Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Internal voltage regulator can't be modified via register writes */
-#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
-#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
-/* Writing FIO_DIR can corrupt a programmable flag's data */
-#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
-#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
-/* Internal Clocking Modes on SPORT0 not supported */
-#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
-/* Internal voltage regulator does not wake up from an RTC wakeup */
-#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
-#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
-#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
-#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
-/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
-#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
-/* 32-bit SPORT DMA will be word reversed */
-#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
-/* Incorrect status in the UART_IIR register */
-#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
-/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
-#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
-#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect Value Written to the Cycle Counters */
-#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
-#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
-/* Programmable Flag (PF3) functionality not supported in all PPI modes */
-#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
-/* Data store can be lost when targeting a cache line fill */
-#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved Bits in SYSCFG Register Not Set at Power-On */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Infinite Core Stall */
-#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers. */
-#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
-#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
-/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
-#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> Is Not Set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
-#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bf533.h b/arch/blackfin/mach-bf533/include/mach/bf533.h
deleted file mode 100644
index e3e05f8f7af9..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/bf533.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF533_H__
-#define __MACH_BF533_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_BIT 0x0FFFFFFF
-#define UART_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0xFF0FFFFF
-#define SPI_ERROR_BIT 0xFFF0FFFF
-#define SPORT0_ERROR_BIT 0xFFFF0FFF
-#define PPI_ERROR_BIT 0xFFFFF0FF
-#define DMA_ERROR_BIT 0xFFFFFF0F
-#define PLLWAKE_ERROR_BIT 0xFFFFFFFF
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_BIT 0x0FFFFFFF
-#define DMA6_UARTRX_BIT 0xF0FFFFFF
-#define DMA5_SPI_BIT 0xFF0FFFFF
-#define DMA4_SPORT1TX_BIT 0xFFF0FFFF
-#define DMA3_SPORT1RX_BIT 0xFFFF0FFF
-#define DMA2_SPORT0TX_BIT 0xFFFFF0FF
-#define DMA1_SPORT0RX_BIT 0xFFFFFF0F
-#define DMA0_PPI_BIT 0xFFFFFFFF
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_BIT 0x0FFFFFFF
-#define MEMDMA1_BIT 0xF0FFFFFF
-#define MEMDMA0_BIT 0xFF0FFFFF
-#define PFB_BIT 0xFFF0FFFF
-#define PFA_BIT 0xFFFF0FFF
-#define TIMER2_BIT 0xFFFFF0FF
-#define TIMER1_BIT 0xFFFFFF0F
-#define TIMER0_BIT 0xFFFFFFFF
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF533
-#define CPU "BF533"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF532
-#define CPU "BF532"
-#define CPUID 0x27a5
-#endif
-#ifdef CONFIG_BF531
-#define CPU "BF531"
-#define CPUID 0x27a5
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF533_H__ */
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
deleted file mode 100644
index 08072c86d5dc..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
deleted file mode 100644
index e366207fbf12..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF533_FAMILY
-
-#include "bf533.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF532.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF532.h"
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
deleted file mode 100644
index fd0cbe4df21a..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ /dev/null
@@ -1,682 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* DMA Traffic controls */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
-#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val)
-#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val)
-#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val)
-#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val)
-#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val)
-#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val)
-#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val)
-#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val)
-#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val)
-#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val)
-#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val)
-#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
-
-#if ANOMALY_05000311
-/* Keep at the CPP expansion to avoid circular header dependency loops */
-#define BFIN_WRITE_FIO_FLAG(name, val) \
- do { \
- unsigned long __flags; \
- __flags = hard_local_irq_save(); \
- bfin_write16(FIO_FLAG_##name, val); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- } while (0)
-#define bfin_write_FIO_FLAG_D(val) BFIN_WRITE_FIO_FLAG(D, val)
-#define bfin_write_FIO_FLAG_C(val) BFIN_WRITE_FIO_FLAG(C, val)
-#define bfin_write_FIO_FLAG_S(val) BFIN_WRITE_FIO_FLAG(S, val)
-#define bfin_write_FIO_FLAG_T(val) BFIN_WRITE_FIO_FLAG(T, val)
-
-#define BFIN_READ_FIO_FLAG(name) \
- ({ \
- unsigned long __flags; \
- u16 __ret; \
- __flags = hard_local_irq_save(); \
- __ret = bfin_read16(FIO_FLAG_##name); \
- bfin_read_CHIPID(); \
- hard_local_irq_restore(__flags); \
- __ret; \
- })
-#define bfin_read_FIO_FLAG_D() BFIN_READ_FIO_FLAG(D)
-#define bfin_read_FIO_FLAG_C() BFIN_READ_FIO_FLAG(C)
-#define bfin_read_FIO_FLAG_S() BFIN_READ_FIO_FLAG(S)
-#define bfin_read_FIO_FLAG_T() BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
-#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
-#endif
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-
-/* UART Controller */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-/*
-#define UART_MSR
-*/
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER 0, 1, 2 Registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val)
-
-/* SPORT0 Controller */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* Parallel Peripheral Interface (PPI) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-#endif /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
deleted file mode 100644
index d438150b1025..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ /dev/null
@@ -1,831 +0,0 @@
-/*
- * System & MMR bit and Address definitions for ADSP-BF532
- *
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#if 0
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
-#endif
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic controls */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
- /* SIC_IAR0 Masks */
-
-#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Masks */
-
-#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
-#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001
-#define TIMIL1 0x0002
-#define TIMIL2 0x0004
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000
-#define TRUN1 0x2000
-#define TRUN2 0x4000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x00000001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
-#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-
-#endif /* _DEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/dma.h b/arch/blackfin/mach-bf533/include/mach/dma.h
deleted file mode 100644
index fb34934c5ba8..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 12
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_MEM_STREAM0_DEST 8 /* TX */
-#define CH_MEM_STREAM0_SRC 9 /* RX */
-#define CH_MEM_STREAM1_DEST 10 /* TX */
-#define CH_MEM_STREAM1_SRC 11 /* RX */
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
deleted file mode 100644
index cce4f8fb3785..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/gpio.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-
-#define PORT_F GPIO_PF0
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
deleted file mode 100644
index 709733754142..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF533_IRQ_H_
-#define _BF533_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 24
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */
-#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */
-#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */
-
-#define SYS_IRQS 31
-
-#define IRQ_PF0 33
-#define IRQ_PF1 34
-#define IRQ_PF2 35
-#define IRQ_PF3 36
-#define IRQ_PF4 37
-#define IRQ_PF5 38
-#define IRQ_PF6 39
-#define IRQ_PF7 40
-#define IRQ_PF8 41
-#define IRQ_PF9 42
-#define IRQ_PF10 43
-#define IRQ_PF11 44
-#define IRQ_PF12 45
-#define IRQ_PF13 46
-#define IRQ_PF14 47
-#define IRQ_PF15 48
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define RTC_ERROR_POS 28
-#define UART_ERROR_POS 24
-#define SPORT1_ERROR_POS 20
-#define SPI_ERROR_POS 16
-#define SPORT0_ERROR_POS 12
-#define PPI_ERROR_POS 8
-#define DMA_ERROR_POS 4
-#define PLLWAKE_ERROR_POS 0
-
-/* IAR1 BIT FIELDS */
-#define DMA7_UARTTX_POS 28
-#define DMA6_UARTRX_POS 24
-#define DMA5_SPI_POS 20
-#define DMA4_SPORT1TX_POS 16
-#define DMA3_SPORT1RX_POS 12
-#define DMA2_SPORT0TX_POS 8
-#define DMA1_SPORT0RX_POS 4
-#define DMA0_PPI_POS 0
-
-/* IAR2 BIT FIELDS */
-#define WDTIMER_POS 28
-#define MEMDMA1_POS 24
-#define MEMDMA0_POS 20
-#define PFB_POS 16
-#define PFA_POS 12
-#define TIMER2_POS 8
-#define TIMER1_POS 4
-#define TIMER0_POS 0
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/mem_map.h b/arch/blackfin/mach-bf533/include/mach/mem_map.h
deleted file mode 100644
index 197af1a398ac..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/mem_map.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * BF533 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF533 processors */
-
-#ifdef CONFIG_BF533
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF532 processors */
-
-#ifdef CONFIG_BF532
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0xC000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0xC000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF531 processors */
-
-#ifdef CONFIG_BF531
-#define L1_CODE_START 0xFFA08000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-#define L1_CODE_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x0000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/portmux.h b/arch/blackfin/mach-bf533/include/mach/portmux.h
deleted file mode 100644
index 96f5d9129f20..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/portmux.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c
deleted file mode 100644
index 8f714cf8135b..000000000000
--- a/arch/blackfin/mach-bf533/ints-priority.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) |
- ((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) |
- ((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) |
- ((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) |
- ((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) |
- ((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) |
- ((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) |
- ((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) |
- ((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) |
- ((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) |
- ((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) |
- ((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) |
- ((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) |
- ((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) |
- ((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) |
- ((CONFIG_TIMER1 - 7) << TIMER1_POS) |
- ((CONFIG_TIMER2 - 7) << TIMER2_POS) |
- ((CONFIG_PFA - 7) << PFA_POS) |
- ((CONFIG_PFB - 7) << PFB_POS) |
- ((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) |
- ((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) |
- ((CONFIG_WDTIMER - 7) << WDTIMER_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
deleted file mode 100644
index 1d69b043afd4..000000000000
--- a/arch/blackfin/mach-bf537/Kconfig
+++ /dev/null
@@ -1,118 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF537 || BF534 || BF536)
-
-source "arch/blackfin/mach-bf537/boards/Kconfig"
-
-menu "BF537 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA_ERROR
- int "IRQ_DMA_ERROR Generic"
- default 7
-config IRQ_ERROR
- int "IRQ_ERROR: PPI CAN MAC SPORT0 SPORT1 SPI UART0 UART1"
- default 11
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_TWI
- int "IRQ_TWI"
- default 10
-config IRQ_SPI
- int "IRQ_SPI"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MAC_RX
- int "IRQ_MAC_RX"
- default 11
-config IRQ_MAC_TX
- int "IRQ_MAC_TX"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 12
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 12
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 12
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 12
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 12
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 12
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 12
-config IRQ_PROG_INTA
- int "IRQ_PROG_INTA"
- default 12
-config IRQ_PORTG_INTB
- int "IRQ_PORTG_INTB"
- default 12
-config IRQ_MEM_DMA0
- int "IRQ_MEM_DMA0"
- default 13
-config IRQ_MEM_DMA1
- int "IRQ_MEM_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
deleted file mode 100644
index 56994b675f9c..000000000000
--- a/arch/blackfin/mach-bf537/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
deleted file mode 100644
index 60b7b29e512e..000000000000
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN537_STAMP
- help
- Select your board!
-
-config BFIN537_STAMP
- bool "BF537-STAMP"
- help
- BF537-STAMP board support.
-
-config BFIN537_BLUETECHNIX_CM_E
- bool "Bluetechnix CM-BF537E"
- depends on (BF537)
- help
- CM-BF537E support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_CM_U
- bool "Bluetechnix CM-BF537U"
- depends on (BF537)
- help
- CM-BF537U support for EVAL- and DEV-Board.
-
-config BFIN537_BLUETECHNIX_TCM
- bool "Bluetechnix TCM-BF537"
- depends on (BF537)
- help
- TCM-BF537 support for EVAL- and DEV-Board.
-
-config PNAV10
- bool "PNAV board"
- depends on (BF537)
- help
- PNAV board support.
-
-config CAMSIG_MINOTAUR
- bool "Cambridge Signal Processing LTD Minotaur"
- depends on (BF537)
- help
- Board supply package for CSP Minotaur
-
-config DNP5370
- bool "SSV Dil/NetPC DNP/5370"
- depends on (BF537)
- help
- Board supply package for DNP/5370 DIL64 module
-
-endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
deleted file mode 100644
index 47a1acc5f389..000000000000
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-bf537/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN537_STAMP) += stamp.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_E) += cm_bf537e.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
-obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
-obj-$(CONFIG_PNAV10) += pnav10.o
-obj-$(CONFIG_CAMSIG_MINOTAUR) += minotaur.o
-obj-$(CONFIG_DNP5370) += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
deleted file mode 100644
index 1e1014df5e9e..000000000000
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537E";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
- {
- /*
- * Refer to arch/blackfin/mach-xxx/include/mach/gpio.h for the GPIO map.
- */
- .start = -1,
- .end = -1,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537e_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537e_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537e_devices, ARRAY_SIZE(cm_bf537e_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537e_init);
-
-static struct platform_device *cm_bf537e_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537e_early_devices,
- ARRAY_SIZE(cm_bf537e_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
deleted file mode 100644
index d056db9e5592..000000000000
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ /dev/null
@@ -1,802 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF537U";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20200000,
- .end = 0x20200000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PH14,
- .end = IRQ_PH14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PH0 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537u_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PH15, driver_name);
- if (ret)
- return ret;
-
- ret = gpio_request(GPIO_PH13, "net2272");
- if (ret) {
- gpio_free(GPIO_PH15);
- return ret;
- }
-
- /* Set PH15 Low make /AMS2 work properly */
- gpio_direction_output(GPIO_PH15, 0);
-
- /* enable CLKBUF output */
- bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PH13, 0);
- mdelay(2);
- gpio_set_value(GPIO_PH13, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf537u_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf537u_init);
-
-static struct platform_device *cm_bf537u_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537u_early_devices,
- ARRAY_SIZE(cm_bf537u_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
deleted file mode 100644
index c4a8ffb15417..000000000000
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * This is the configuration for SSV Dil/NetPC DNP/5370 board.
- *
- * DIL module: http://www.dilnetpc.com/dnp0086.htm
- * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
- *
- * Copyright 2010 3ality Digital Systems
- * Copyright 2005 National ICT Australia (NICTA)
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/phy.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "DNP/5370";
-#define FLASH_MAC 0x202f0000
-#define CONFIG_MTD_PHYSMAP_LEN 0x300000
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition asmb_flash_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x30000,
- .offset = 0,
- }, {
- .name = "linux kernel and rootfs(nor)",
- .size = 0x300000 - 0x30000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC address(nor)",
- .size = 0x10000,
- .offset = MTDPART_OFS_APPEND,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data asmb_flash_data = {
- .width = 1,
- .parts = asmb_flash_partitions,
- .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
-};
-
-static struct resource asmb_flash_resource = {
- .start = 0x20000000,
- .end = 0x202fffff,
- .flags = IORESOURCE_MEM,
-};
-
-/* 4 MB NOR flash attached to async memory banks 0-2,
- * therefore only 3 MB visible.
- */
-static struct platform_device asmb_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &asmb_flash_data,
- },
- .num_resources = 1,
- .resource = &asmb_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-/* This mapping is for at45db642 it has 1056 page size,
- * partition size and offset should be page aligned
- */
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "JFFS2 dataflash(nor)",
-#ifdef CONFIG_MTD_PAGESIZE_1024
- .offset = 0x40000,
- .size = 0x7C0000,
-#else
- .offset = 0x0,
- .size = 0x840000,
-#endif
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "mtd_dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
- .type = "mtd_dataflash",
-};
-
-static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
- .enable_dma = 0, /* use no dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-/* SD/MMC card reader at SPI bus */
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000,
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-/* 8 Megabyte Atmel NOR flash chip at SPI bus */
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- {
- .modalias = "mtd_dataflash",
- .max_speed_hz = 16700000,
- .bus_num = 0,
- .chip_select = 2,
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &spi_dataflash_chip_info,
- .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
- },
-#endif
-};
-
-/* SPI controller data */
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct bfin5xx_spi_master spi_bfin_master_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device spi_bfin_master_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &spi_bfin_master_info, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-static struct platform_device *dnp5370_devices[] __initdata = {
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &asmb_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &spi_bfin_master_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-};
-
-static int __init dnp5370_init(void)
-{
- printk(KERN_INFO "DNP/5370: registering device resources\n");
- platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
- printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
- ARRAY_SIZE(bfin_spi_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
- return 0;
-}
-arch_initcall(dnp5370_init);
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
deleted file mode 100644
index dd7bda07bf90..000000000000
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Cambridge Signal Processing
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "CamSig Minotaur BF537";
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = IRQ_PF6, /* Card Detect PF6 */
- .end = IRQ_PF6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-
-/* Partition sizes */
-#define FLASH_SIZE 0x00400000
-#define PSIZE_UBOOT 0x00030000
-#define PSIZE_INITRAMFS 0x00240000
-
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = PSIZE_UBOOT,
- .offset = 0x000000,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "initramfs(spi)",
- .size = PSIZE_INITRAMFS,
- .offset = PSIZE_UBOOT
- }, {
- .name = "opt(spi)",
- .size = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
- .offset = PSIZE_UBOOT + PSIZE_INITRAMFS,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-static struct platform_device *minotaur_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-};
-
-static int __init minotaur_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(minotaur_init);
-
-static struct platform_device *minotaur_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(minotaur_early_devices,
- ARRAY_SIZE(minotaur_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
deleted file mode 100644
index 06a50ddb54c0..000000000000
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI PNAV-1.0";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_RMII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_RMII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF2,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
-},
-#endif
-
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537-lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-};
-
-static int __init pnav_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
-#endif
- return 0;
-}
-
-arch_initcall(pnav_init);
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
deleted file mode 100644
index 400e6693643e..000000000000
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ /dev/null
@@ -1,3019 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/i2c.h>
-#include <linux/platform_data/adp5588.h>
-#include <linux/etherdevice.h>
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/sl811.h>
-#include <linux/spi/mmc_spi.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/reboot.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
-#include <linux/regulator/fixed.h>
-#endif
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/regulator/userspace-consumer.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF537-STAMP";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x203C0000,
- .end = 0x203C0000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF2, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF3, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF4, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF5, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
-static struct resource bfin_pcmcia_cf_resources[] = {
- {
- .start = 0x20310000, /* IO PORT */
- .end = 0x20312000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20311000, /* Attribute Memory */
- .end = 0x20311FFF,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- }, {
- .start = 6, /* Card Detect PF6 */
- .end = 6,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pcmcia_cf_device = {
- .name = "bfin_cf_pcmcia",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
- .resource = bfin_pcmcia_cf_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20300300,
- .end = 0x20300300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
-static struct resource dm9000_resources[] = {
- [0] = {
- .start = 0x203FB800,
- .end = 0x203FB800 + 1,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x203FB804,
- .end = 0x203FB804 + 1,
- .flags = IORESOURCE_MEM,
- },
- [2] = {
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
- },
-};
-
-static struct platform_device dm9000_device = {
- .name = "dm9000",
- .id = -1,
- .num_resources = ARRAY_SIZE(dm9000_resources),
- .resource = dm9000_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
-static struct resource sl811_hcd_resources[] = {
- {
- .start = 0x20340000,
- .end = 0x20340000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20340004,
- .end = 0x20340004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF4,
- .end = IRQ_PF4,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
-void sl811_port_power(struct device *dev, int is_on)
-{
- gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
- gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
-}
-#endif
-
-static struct sl811_platform_data sl811_priv = {
- .potpg = 10,
- .power = 250, /* == 500mA */
-#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
- .port_power = &sl811_port_power,
-#endif
-};
-
-static struct platform_device sl811_hcd_device = {
- .name = "sl811-hcd",
- .id = 0,
- .dev = {
- .platform_data = &sl811_priv,
- },
- .num_resources = ARRAY_SIZE(sl811_hcd_resources),
- .resource = sl811_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20360000,
- .end = 0x20360000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20360004,
- .end = 0x20360004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF3,
- .end = IRQ_PF3,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "linux kernel(nand)",
- .size = 0x400000,
- .offset = 0,
- }, {
- .name = "file system(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 1
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF3
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .part_probe_types = part_probes,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x20212000,
- .end = 0x20212000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
- gpio_direction_input(BFIN_NAND_PLAT_READY);
-}
-#else
-static void bfin_plat_nand_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition stamp_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x400000 - 0x40000 - 0x180000 - 0x10000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "MAC Address(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x3F0000,
- .mask_flags = MTD_WRITEABLE,
- }
-};
-
-static struct physmap_flash_data stamp_flash_data = {
- .width = 2,
- .parts = stamp_partitions,
- .nr_parts = ARRAY_SIZE(stamp_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource stamp_flash_resource = {
- .start = 0x20000000,
- .end = 0x203fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device stamp_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &stamp_flash_data,
- },
- .num_resources = 1,
- .resource = &stamp_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- /* .type = "m25p64", */
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
-#include <linux/input/ad714x.h>
-
-static struct ad714x_slider_plat ad7147_spi_slider_plat[] = {
- {
- .start_stage = 0,
- .end_stage = 7,
- .max_coord = 128,
- },
-};
-
-static struct ad714x_button_plat ad7147_spi_button_plat[] = {
- {
- .keycode = BTN_FORWARD,
- .l_mask = 0,
- .h_mask = 0x600,
- },
- {
- .keycode = BTN_LEFT,
- .l_mask = 0,
- .h_mask = 0x500,
- },
- {
- .keycode = BTN_MIDDLE,
- .l_mask = 0,
- .h_mask = 0x800,
- },
- {
- .keycode = BTN_RIGHT,
- .l_mask = 0x100,
- .h_mask = 0x400,
- },
- {
- .keycode = BTN_BACK,
- .l_mask = 0x200,
- .h_mask = 0x400,
- },
-};
-static struct ad714x_platform_data ad7147_spi_platform_data = {
- .slider_num = 1,
- .button_num = 5,
- .slider = ad7147_spi_slider_plat,
- .button = ad7147_spi_button_plat,
- .stage_cfg_reg = {
- {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFE, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FFB, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FEF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1FBF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1EFF, 0, 0x2626, 1650, 1650, 1650, 1650},
- {0xFFFF, 0x1BFF, 0, 0x2626, 1600, 1600, 1600, 1600},
- {0xFF7B, 0x3FFF, 0x506, 0x2626, 1100, 1100, 1150, 1150},
- {0xFDFE, 0x3FFF, 0x606, 0x2626, 1100, 1100, 1150, 1150},
- {0xFEBA, 0x1FFF, 0x1400, 0x2626, 1200, 1200, 1300, 1300},
- {0xFFEF, 0x1FFF, 0x0, 0x2626, 1100, 1100, 1150, 1150},
- },
- .sys_cfg_reg = {0x2B2, 0x0, 0x3233, 0x819, 0x832, 0xCFF, 0xCFF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
-#include <linux/input/ad714x.h>
-static struct ad714x_button_plat ad7142_i2c_button_plat[] = {
- {
- .keycode = BTN_1,
- .l_mask = 0,
- .h_mask = 0x1,
- },
- {
- .keycode = BTN_2,
- .l_mask = 0,
- .h_mask = 0x2,
- },
- {
- .keycode = BTN_3,
- .l_mask = 0,
- .h_mask = 0x4,
- },
- {
- .keycode = BTN_4,
- .l_mask = 0x0,
- .h_mask = 0x8,
- },
-};
-static struct ad714x_platform_data ad7142_i2c_platform_data = {
- .button_num = 4,
- .button = ad7142_i2c_button_plat,
- .stage_cfg_reg = {
- /* fixme: figure out right setting for all comoponent according
- * to hardware feature of EVAL-AD7142EB board */
- {0xE7FF, 0x3FFF, 0x0005, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFDBF, 0x3FFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x2DFF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x37BF, 0x0001, 0x2626, 0x01F4, 0x01F4, 0x028A, 0x028A},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- {0xFFFF, 0x3FFF, 0x0000, 0x0606, 0x01F4, 0x01F4, 0x0320, 0x0320},
- },
- .sys_cfg_reg = {0x0B2, 0x0, 0x690, 0x664, 0x290F, 0xF, 0xF, 0x0},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
-static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
-static unsigned short ad2s1200_platform_data[] = {
- /* used as SAMPLE and RDVEL */
- GPIO_PF5, GPIO_PF6, 0
-};
-
-static struct bfin5xx_spi_chip ad2s1200_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
-static unsigned short ad2s1210_platform_data[] = {
- /* use as SAMPLE, A0, A1 */
- GPIO_PF7, GPIO_PF8, GPIO_PF9,
-# if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
- /* the RES0 and RES1 pins */
- GPIO_PF4, GPIO_PF5,
-# endif
- 0,
-};
-
-static struct bfin5xx_spi_chip ad2s1210_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
-static struct bfin5xx_spi_chip ad7314_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
-static unsigned short ad7816_platform_data[] = {
- GPIO_PF4, /* rdwr_pin */
- GPIO_PF5, /* convert_pin */
- GPIO_PF7, /* busy_pin */
- 0,
-};
-
-static struct bfin5xx_spi_chip ad7816_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
-static unsigned long adt7310_platform_data[3] = {
-/* INT bound temperature alarm event. line 1 */
- IRQ_PG4, IRQF_TRIGGER_LOW,
-/* CT bound temperature alarm event irq_flags. line 0 */
- IRQF_TRIGGER_LOW,
-};
-
-static struct bfin5xx_spi_chip adt7310_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
-static unsigned short ad7298_platform_data[] = {
- GPIO_PF7, /* busy_pin */
- 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
-static unsigned long adt7316_spi_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF7, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-
-static struct bfin5xx_spi_chip adt7316_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
-
-static int bfin_mmc_spi_init(struct device *dev,
- irqreturn_t (*detect_int)(int, void *), void *data)
-{
- return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
- IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
-}
-
-static void bfin_mmc_spi_exit(struct device *dev, void *data)
-{
- free_irq(MMC_SPI_CARD_DETECT_INT, data);
-}
-
-static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
- .init = bfin_mmc_spi_init,
- .exit = bfin_mmc_spi_exit,
- .detect_delay = 100, /* msecs */
-};
-
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
- .pio_interrupt = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-#include <linux/spi/ad7877.h>
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ENC28J60)
-static struct bfin5xx_spi_chip enc28j60_spi_chip_info = {
- .enable_dma = 1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADF702X)
-#include <linux/spi/adf702x.h>
-#define TXREG 0x0160A470
-static const u32 adf7021_regs[] = {
- 0x09608FA0,
- 0x00575011,
- 0x00A7F092,
- 0x2B141563,
- 0x81F29E94,
- 0x00003155,
- 0x050A4F66,
- 0x00000007,
- 0x00000008,
- 0x000231E9,
- 0x3296354A,
- 0x891A2B3B,
- 0x00000D9C,
- 0x0000000D,
- 0x0000000E,
- 0x0000000F,
-};
-
-static struct adf702x_platform_data adf7021_platform_data = {
- .regs_base = (void *)SPORT1_TCR1,
- .dma_ch_rx = CH_SPORT1_RX,
- .dma_ch_tx = CH_SPORT1_TX,
- .irq_sport_err = IRQ_SPORT1_ERROR,
- .gpio_int_rfs = GPIO_PF8,
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0},
- .adf702x_model = MODEL_ADF7021,
- .adf702x_regs = adf7021_regs,
- .tx_reg = TXREG,
-};
-static inline void adf702x_mac_init(void)
-{
- eth_random_addr(adf7021_platform_data.mac_addr);
-}
-#else
-static inline void adf702x_mac_init(void) {}
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
-#include <linux/spi/ads7846.h>
-static int ads7873_get_pendown_state(void)
-{
- return gpio_get_value(GPIO_PF6);
-}
-
-static struct ads7846_platform_data __initdata ad7873_pdata = {
- .model = 7873, /* AD7873 */
- .x_max = 0xfff,
- .y_max = 0xfff,
- .x_plate_ohms = 620,
- .debounce_max = 1,
- .debounce_rep = 0,
- .debounce_tol = (~0),
- .get_pendown_state = ads7873_get_pendown_state,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_AD7476)
-static struct bfin5xx_spi_chip spi_ad7476_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- {
- .modalias = "ad1836",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-
-#ifdef CONFIG_SND_SOC_AD193X_SPI
- {
- .modalias = "ad193x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- .modalias = "adav801",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_SPI)
- {
- .modalias = "ad714x_captouch",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF4,
- .bus_num = 0,
- .chip_select = 5,
- .mode = SPI_MODE_3,
- .platform_data = &ad7147_spi_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S90)
- {
- .modalias = "ad2s90",
- .bus_num = 0,
- .chip_select = 3, /* change it for your board */
- .mode = SPI_MODE_3,
- .platform_data = NULL,
- .controller_data = &ad2s90_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1200)
- {
- .modalias = "ad2s1200",
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1200_platform_data,
- .controller_data = &ad2s1200_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD2S1210)
- {
- .modalias = "ad2s1210",
- .max_speed_hz = 8192000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad2s1210_platform_data,
- .controller_data = &ad2s1210_spi_chip_info,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_AD7314)
- {
- .modalias = "ad7314",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .controller_data = &ad7314_spi_chip_info,
- .mode = SPI_MODE_1,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7816)
- {
- .modalias = "ad7818",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7816_platform_data,
- .controller_data = &ad7816_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7310)
- {
- .modalias = "adt7310",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* CT alarm event. Line 0 */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7310_platform_data,
- .controller_data = &adt7310_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7298)
- {
- .modalias = "ad7298",
- .max_speed_hz = 1000000,
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = ad7298_platform_data,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_SPI)
- {
- .modalias = "adt7316",
- .max_speed_hz = 1000000,
- .irq = IRQ_PG5, /* interrupt line */
- .bus_num = 0,
- .chip_select = 4, /* CS, change it for your board */
- .platform_data = adt7316_spi_data,
- .controller_data = &adt7316_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = &bfin_mmc_spi_pdata,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF7,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif
-#if IS_ENABLED(CONFIG_ENC28J60)
- {
- .modalias = "enc28j60",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .irq = IRQ_PF6,
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .controller_data = &enc28j60_spi_chip_info,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PF6,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADF702X)
- {
- .modalias = "adf702x",
- .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &adf7021_platform_data,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_ADS7846)
- {
- .modalias = "ads7846",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .irq = IRQ_PF6,
- .chip_select = GPIO_PF10 + MAX_CTRL_CS, /* GPIO controlled SSEL */
- .platform_data = &ad7873_pdata,
- .mode = SPI_MODE_0,
- },
-#endif
-#if IS_ENABLED(CONFIG_AD7476)
- {
- .modalias = "ad7476", /* Name of spi_driver for this device */
- .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. */
- .platform_data = NULL, /* No spi_driver specific config */
- .controller_data = &spi_ad7476_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7753)
- {
- .modalias = "ade7753",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7754)
- {
- .modalias = "ade7754",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7758)
- {
- .modalias = "ade7758",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7759)
- {
- .modalias = "ade7759",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADE7854_SPI)
- {
- .modalias = "ade7854",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16060)
- {
- .modalias = "adis16060_r",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_0,
- },
- {
- .modalias = "adis16060_w",
- .max_speed_hz = 2900000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2, /* CS for write, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_1,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16130)
- {
- .modalias = "adis16130",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS for read, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16201)
- {
- .modalias = "adis16201",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16203)
- {
- .modalias = "adis16203",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16204)
- {
- .modalias = "adis16204",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16209)
- {
- .modalias = "adis16209",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16220)
- {
- .modalias = "adis16220",
- .max_speed_hz = 2000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16240)
- {
- .modalias = "adis16240",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16260)
- {
- .modalias = "adis16260",
- .max_speed_hz = 1500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16261)
- {
- .modalias = "adis16261",
- .max_speed_hz = 2500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16300)
- {
- .modalias = "adis16300",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16350)
- {
- .modalias = "adis16364",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 5, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- .irq = IRQ_PF4,
- },
-#endif
-#if IS_ENABLED(CONFIG_ADIS16400)
- {
- .modalias = "adis16400",
- .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1, /* CS, change it for your board */
- .platform_data = NULL, /* No spi_driver specific config */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
-
-/* SPORT SPI controller data */
-static struct bfin5xx_spi_master bfin_sport_spi0_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
- P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
-};
-
-static struct resource bfin_sport_spi0_resource[] = {
- [0] = {
- .start = SPORT0_TCR1,
- .end = SPORT0_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi0_device = {
- .name = "bfin-sport-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
- .resource = bfin_sport_spi0_resource,
- .dev = {
- .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bfin_sport_spi1_info = {
- .num_chipselect = MAX_BLACKFIN_GPIOS,
- .enable_dma = 0, /* master don't support DMA */
- .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
- P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
-};
-
-static struct resource bfin_sport_spi1_resource[] = {
- [0] = {
- .start = SPORT1_TCR1,
- .end = SPORT1_TCR1 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport_spi1_device = {
- .name = "bfin-sport-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
- .resource = bfin_sport_spi1_resource,
- .dev = {
- .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
- },
-};
-
-#endif /* sport spi master and devices */
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
-static struct platform_device bfin_fb_device = {
- .name = "bf537_lq035",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI,
- .irq_err = IRQ_PPI_ERROR,
- .base = (void __iomem *)PPI_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PF10;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF537",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | XFR_TYPE | 0x0020),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
-static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = {
- [0] = KEY_GRAVE,
- [1] = KEY_1,
- [2] = KEY_2,
- [3] = KEY_3,
- [4] = KEY_4,
- [5] = KEY_5,
- [6] = KEY_6,
- [7] = KEY_7,
- [8] = KEY_8,
- [9] = KEY_9,
- [10] = KEY_0,
- [11] = KEY_MINUS,
- [12] = KEY_EQUAL,
- [13] = KEY_BACKSLASH,
- [15] = KEY_KP0,
- [16] = KEY_Q,
- [17] = KEY_W,
- [18] = KEY_E,
- [19] = KEY_R,
- [20] = KEY_T,
- [21] = KEY_Y,
- [22] = KEY_U,
- [23] = KEY_I,
- [24] = KEY_O,
- [25] = KEY_P,
- [26] = KEY_LEFTBRACE,
- [27] = KEY_RIGHTBRACE,
- [29] = KEY_KP1,
- [30] = KEY_KP2,
- [31] = KEY_KP3,
- [32] = KEY_A,
- [33] = KEY_S,
- [34] = KEY_D,
- [35] = KEY_F,
- [36] = KEY_G,
- [37] = KEY_H,
- [38] = KEY_J,
- [39] = KEY_K,
- [40] = KEY_L,
- [41] = KEY_SEMICOLON,
- [42] = KEY_APOSTROPHE,
- [43] = KEY_BACKSLASH,
- [45] = KEY_KP4,
- [46] = KEY_KP5,
- [47] = KEY_KP6,
- [48] = KEY_102ND,
- [49] = KEY_Z,
- [50] = KEY_X,
- [51] = KEY_C,
- [52] = KEY_V,
- [53] = KEY_B,
- [54] = KEY_N,
- [55] = KEY_M,
- [56] = KEY_COMMA,
- [57] = KEY_DOT,
- [58] = KEY_SLASH,
- [60] = KEY_KPDOT,
- [61] = KEY_KP7,
- [62] = KEY_KP8,
- [63] = KEY_KP9,
- [64] = KEY_SPACE,
- [65] = KEY_BACKSPACE,
- [66] = KEY_TAB,
- [67] = KEY_KPENTER,
- [68] = KEY_ENTER,
- [69] = KEY_ESC,
- [70] = KEY_DELETE,
- [74] = KEY_KPMINUS,
- [76] = KEY_UP,
- [77] = KEY_DOWN,
- [78] = KEY_RIGHT,
- [79] = KEY_LEFT,
-};
-
-static struct adp5588_kpad_platform_data adp5588_kpad_data = {
- .rows = 8,
- .cols = 10,
- .keymap = adp5588_keymap,
- .keymapsize = ARRAY_SIZE(adp5588_keymap),
- .repeat = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
-#include <linux/mfd/adp5520.h>
-
- /*
- * ADP5520/5501 Backlight Data
- */
-
-static struct adp5520_backlight_platform_data adp5520_backlight_data = {
- .fade_in = ADP5520_FADE_T_1200ms,
- .fade_out = ADP5520_FADE_T_1200ms,
- .fade_led_law = ADP5520_BL_LAW_LINEAR,
- .en_ambl_sens = 1,
- .abml_filt = ADP5520_BL_AMBL_FILT_640ms,
- .l1_daylight_max = ADP5520_BL_CUR_mA(15),
- .l1_daylight_dim = ADP5520_BL_CUR_mA(0),
- .l2_office_max = ADP5520_BL_CUR_mA(7),
- .l2_office_dim = ADP5520_BL_CUR_mA(0),
- .l3_dark_max = ADP5520_BL_CUR_mA(3),
- .l3_dark_dim = ADP5520_BL_CUR_mA(0),
- .l2_trip = ADP5520_L2_COMP_CURR_uA(700),
- .l2_hyst = ADP5520_L2_COMP_CURR_uA(50),
- .l3_trip = ADP5520_L3_COMP_CURR_uA(80),
- .l3_hyst = ADP5520_L3_COMP_CURR_uA(20),
-};
-
- /*
- * ADP5520/5501 LEDs Data
- */
-
-static struct led_info adp5520_leds[] = {
- {
- .name = "adp5520-led1",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms,
- },
-#ifdef ADP5520_EN_ALL_LEDS
- {
- .name = "adp5520-led2",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED2_ADP5501_LED1,
- },
- {
- .name = "adp5520-led3",
- .default_trigger = "none",
- .flags = FLAG_ID_ADP5520_LED3_ADP5501_LED2,
- },
-#endif
-};
-
-static struct adp5520_leds_platform_data adp5520_leds_data = {
- .num_leds = ARRAY_SIZE(adp5520_leds),
- .leds = adp5520_leds,
- .fade_in = ADP5520_FADE_T_600ms,
- .fade_out = ADP5520_FADE_T_600ms,
- .led_on_time = ADP5520_LED_ONT_600ms,
-};
-
- /*
- * ADP5520 GPIO Data
- */
-
-static struct adp5520_gpio_platform_data adp5520_gpio_data = {
- .gpio_start = 50,
- .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
- .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2,
-};
-
- /*
- * ADP5520 Keypad Data
- */
-
-static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = {
- [ADP5520_KEY(0, 0)] = KEY_GRAVE,
- [ADP5520_KEY(0, 1)] = KEY_1,
- [ADP5520_KEY(0, 2)] = KEY_2,
- [ADP5520_KEY(0, 3)] = KEY_3,
- [ADP5520_KEY(1, 0)] = KEY_4,
- [ADP5520_KEY(1, 1)] = KEY_5,
- [ADP5520_KEY(1, 2)] = KEY_6,
- [ADP5520_KEY(1, 3)] = KEY_7,
- [ADP5520_KEY(2, 0)] = KEY_8,
- [ADP5520_KEY(2, 1)] = KEY_9,
- [ADP5520_KEY(2, 2)] = KEY_0,
- [ADP5520_KEY(2, 3)] = KEY_MINUS,
- [ADP5520_KEY(3, 0)] = KEY_EQUAL,
- [ADP5520_KEY(3, 1)] = KEY_BACKSLASH,
- [ADP5520_KEY(3, 2)] = KEY_BACKSPACE,
- [ADP5520_KEY(3, 3)] = KEY_ENTER,
-};
-
-static struct adp5520_keys_platform_data adp5520_keys_data = {
- .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0,
- .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0,
- .keymap = adp5520_keymap,
- .keymapsize = ARRAY_SIZE(adp5520_keymap),
- .repeat = 0,
-};
-
- /*
- * ADP5520/5501 Multifunction Device Init Data
- */
-
-static struct adp5520_platform_data adp5520_pdev_data = {
- .backlight = &adp5520_backlight_data,
- .leds = &adp5520_leds_data,
- .gpio = &adp5520_gpio_data,
- .keys = &adp5520_keys_data,
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
-static struct adp5588_gpio_platform_data adp5588_gpio_data = {
- .gpio_start = 50,
- .pullup_dis_mask = 0,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
-#include <linux/platform_data/adp8870.h>
-static struct led_info adp8870_leds[] = {
- {
- .name = "adp8870-led7",
- .default_trigger = "none",
- .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms,
- },
-};
-
-
-static struct adp8870_backlight_platform_data adp8870_pdata = {
- .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 |
- ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */
- .pwm_assign = 0, /* 1 = Enables PWM mode */
-
- .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */
- .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */
- .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8870_leds,
- .num_leds = ARRAY_SIZE(adp8870_leds),
- .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8870_FADE_T_600ms,
- .led_fade_out = ADP8870_FADE_T_600ms,
- .led_on_time = ADP8870_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
-#include <linux/platform_data/adp8860.h>
-static struct led_info adp8860_leds[] = {
- {
- .name = "adp8860-led7",
- .default_trigger = "none",
- .flags = ADP8860_LED_D7 | ADP8860_LED_OFFT_600ms,
- },
-};
-
-static struct adp8860_backlight_platform_data adp8860_pdata = {
- .bl_led_assign = ADP8860_BL_D1 | ADP8860_BL_D2 | ADP8860_BL_D3 |
- ADP8860_BL_D4 | ADP8860_BL_D5 | ADP8860_BL_D6, /* 1 = Backlight 0 = Individual LED */
-
- .bl_fade_in = ADP8860_FADE_T_1200ms, /* Backlight Fade-In Timer */
- .bl_fade_out = ADP8860_FADE_T_1200ms, /* Backlight Fade-Out Timer */
- .bl_fade_law = ADP8860_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */
-
- .en_ambl_sens = 1, /* 1 = enable ambient light sensor */
- .abml_filt = ADP8860_BL_AMBL_FILT_320ms, /* Light sensor filter time */
-
- .l1_daylight_max = ADP8860_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l1_daylight_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_max = ADP8860_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l2_office_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_max = ADP8860_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
- .l3_dark_dim = ADP8860_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
-
- .l2_trip = ADP8860_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l2_hyst = ADP8860_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */
- .l3_trip = ADP8860_L3_COMP_CURR_uA(43), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
- .l3_hyst = ADP8860_L3_COMP_CURR_uA(11), /* use L3_COMP_CURR_uA(I) 0 <= I <= 138 uA */
-
- .leds = adp8860_leds,
- .num_leds = ARRAY_SIZE(adp8860_leds),
- .led_fade_law = ADP8860_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */
- .led_fade_in = ADP8860_FADE_T_600ms,
- .led_fade_out = ADP8860_FADE_T_600ms,
- .led_on_time = ADP8860_LED_ONT_200ms,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-static struct regulator_consumer_supply ad5398_consumer = {
- .supply = "current",
-};
-
-static struct regulator_init_data ad5398_regulator_data = {
- .constraints = {
- .name = "current range",
- .max_uA = 120000,
- .valid_ops_mask = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &ad5398_consumer,
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
-static struct platform_device ad5398_virt_consumer_device = {
- .name = "reg-virt-consumer",
- .id = 0,
- .dev = {
- .platform_data = "current", /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data ad5398_bulk_data = {
- .supply = "current",
-};
-
-static struct regulator_userspace_consumer_data ad5398_userspace_comsumer_data = {
- .name = "ad5398",
- .num_supplies = 1,
- .supplies = &ad5398_bulk_data,
-};
-
-static struct platform_device ad5398_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &ad5398_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7410_platform_data[2] = {
- IRQ_PG4, IRQF_TRIGGER_LOW,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
-/* INT bound temperature alarm event. line 1 */
-static unsigned long adt7316_i2c_data[2] = {
- IRQF_TRIGGER_LOW, /* interrupt flags */
- GPIO_PF4, /* ldac_pin, 0 means DAC/LDAC registers control DAC update */
-};
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
-#ifdef CONFIG_SND_SOC_AD193X_I2C
- {
- I2C_BOARD_INFO("ad1937", 0x04),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAV80X)
- {
- I2C_BOARD_INFO("adav803", 0x10),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_AD714X_I2C)
- {
- I2C_BOARD_INFO("ad7142_captouch", 0x2C),
- .irq = IRQ_PG5,
- .platform_data = (void *)&ad7142_i2c_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7150)
- {
- I2C_BOARD_INFO("ad7150", 0x48),
- .irq = IRQ_PG5, /* fixme: use real interrupt number */
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7152)
- {
- I2C_BOARD_INFO("ad7152", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD774X)
- {
- I2C_BOARD_INFO("ad774x", 0x48),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADE7854_I2C)
- {
- I2C_BOARD_INFO("ade7854", 0x38),
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SENSORS_LM75)
- {
- I2C_BOARD_INFO("adt75", 0x9),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7410)
- {
- I2C_BOARD_INFO("adt7410", 0x48),
- /* CT critical temperature event. line 0 */
- .irq = IRQ_PG5,
- .platform_data = (void *)&adt7410_platform_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_AD7291)
- {
- I2C_BOARD_INFO("ad7291", 0x20),
- .irq = IRQ_PG5,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_ADT7316_I2C)
- {
- I2C_BOARD_INFO("adt7316", 0x48),
- .irq = IRQ_PG6,
- .platform_data = (void *)&adt7316_i2c_data,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = IRQ_PG6,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_I2C)
- {
- I2C_BOARD_INFO("ad7879", 0x2F),
- .irq = IRQ_PG5,
- .platform_data = (void *)&bfin_ad7879_ts_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_KEYBOARD_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-keys", 0x34),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5588_kpad_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_PMIC_ADP5520)
- {
- I2C_BOARD_INFO("pmic-adp5520", 0x32),
- .irq = IRQ_PG0,
- .platform_data = (void *)&adp5520_pdev_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PG3,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_GPIO_ADP5588)
- {
- I2C_BOARD_INFO("adp5588-gpio", 0x34),
- .platform_data = (void *)&adp5588_gpio_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BFIN_7393)
- {
- I2C_BOARD_INFO("bfin-adv7393", 0x2B),
- },
-#endif
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- {
- I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2F),
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8870)
- {
- I2C_BOARD_INFO("adp8870", 0x2B),
- .platform_data = (void *)&adp8870_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1371)
- {
- I2C_BOARD_INFO("adau1371", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1361)
- {
- I2C_BOARD_INFO("adau1361", 0x38),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1701)
- {
- I2C_BOARD_INFO("adau1701", 0x34),
- },
-#endif
-#if IS_ENABLED(CONFIG_AD525X_DPOT)
- {
- I2C_BOARD_INFO("ad5258", 0x18),
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
- {
- I2C_BOARD_INFO("ad5398", 0xC),
- .platform_data = (void *)&ad5398_regulator_data,
- },
-#endif
-#if IS_ENABLED(CONFIG_BACKLIGHT_ADP8860)
- {
- I2C_BOARD_INFO("adp8860", 0x2A),
- .platform_data = (void *)&adp8860_pdata,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1373)
- {
- I2C_BOARD_INFO("adau1373", 0x1A),
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2e),
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) \
-|| IS_ENABLED(CONFIG_BFIN_SPORT)
-unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
-};
-#endif
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
-static struct resource bfin_sport0_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_TX,
- .end = IRQ_SPORT0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sport0_device = {
- .name = "bfin_sport_raw",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_resources),
- .resource = bfin_sport0_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
-
-#ifdef CF_IDE_NAND_CARD_USE_HDD_INTERFACE
-#define PATA_INT IRQ_PF5
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 1,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20314020,
- .end = 0x2031403F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2031401C,
- .end = 0x2031401F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-#elif defined(CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE)
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 0,
-};
-/* CompactFlash Storage Card Memory Mapped Addressing
- * /REG = A11 = 1
- */
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x20211800,
- .end = 0x20211807,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2021180E, /* Device Ctl */
- .end = 0x2021180E,
- .flags = IORESOURCE_MEM,
- },
-};
-#endif
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static const unsigned ad73311_gpio[] = {
- GPIO_PF4,
-};
-
-static struct platform_device bfin_ad73311_machine = {
- .name = "bfin-snd-ad73311",
- .id = 1,
- .dev = {
- .platform_data = (void *)ad73311_gpio,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
-static struct platform_device bfin_eval_adav801_device = {
- .name = "bfin-eval-adav801",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
-#define REGULATOR_ADP122 "adp122"
-#define REGULATOR_ADP122_UV 2500000
-
-static struct regulator_consumer_supply adp122_consumers = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_init_data adp_switch_regulator_data = {
- .constraints = {
- .name = REGULATOR_ADP122,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .min_uV = REGULATOR_ADP122_UV,
- .max_uV = REGULATOR_ADP122_UV,
- .min_uA = 0,
- .max_uA = 300000,
- },
- .num_consumer_supplies = 1, /* only 1 */
- .consumer_supplies = &adp122_consumers,
-};
-
-static struct fixed_voltage_config adp_switch_pdata = {
- .supply_name = REGULATOR_ADP122,
- .microvolts = REGULATOR_ADP122_UV,
- .gpio = GPIO_PF2,
- .enable_high = 1,
- .enabled_at_boot = 0,
- .init_data = &adp_switch_regulator_data,
-};
-
-static struct platform_device adp_switch_device = {
- .name = "reg-fixed-voltage",
- .id = 0,
- .dev = {
- .platform_data = &adp_switch_pdata,
- },
-};
-
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
-static struct regulator_bulk_data adp122_bulk_data = {
- .supply = REGULATOR_ADP122,
-};
-
-static struct regulator_userspace_consumer_data adp122_userspace_comsumer_data = {
- .name = REGULATOR_ADP122,
- .num_supplies = 1,
- .supplies = &adp122_bulk_data,
-};
-
-static struct platform_device adp122_userspace_consumer_device = {
- .name = "reg-userspace-consumer",
- .id = 0,
- .dev = {
- .platform_data = &adp122_userspace_comsumer_data,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
-
-static struct resource iio_gpio_trigger_resources[] = {
- [0] = {
- .start = IRQ_PF5,
- .end = IRQ_PF5,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct platform_device iio_gpio_trigger = {
- .name = "iio_gpio_trigger",
- .num_resources = ARRAY_SIZE(iio_gpio_trigger_resources),
- .resource = iio_gpio_trigger_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
-static struct platform_device bf5xx_adau1373_device = {
- .name = "bfin-eval-adau1373",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
-static struct platform_device bf5xx_adau1701_device = {
- .name = "bfin-eval-adau1701",
-};
-#endif
-
-static struct platform_device *stamp_devices[] __initdata = {
-
- &bfin_dpmc,
-#if IS_ENABLED(CONFIG_BFIN_SPORT)
- &bfin_sport0_device,
-#endif
-#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
- &bfin_pcmcia_cf_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_SL811_HCD)
- &sl811_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_DM9000)
- &dm9000_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN_SPORT)
- &bfin_sport_spi0_device,
- &bfin_sport_spi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF537_LQ035)
- &bfin_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &stamp_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
- &bfin_ad73311_machine,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_AD73311)
- &bfin_ad73311_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_AD5398)
-#if IS_ENABLED(CONFIG_REGULATOR_VIRTUAL_CONSUMER)
- &ad5398_virt_consumer_device,
-#endif
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &ad5398_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_REGULATOR_FIXED_VOLTAGE)
- &adp_switch_device,
-#if IS_ENABLED(CONFIG_REGULATOR_USERSPACE_CONSUMER)
- &adp122_userspace_consumer_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_IIO_GPIO_TRIGGER)
- &iio_gpio_trigger,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1373)
- &bf5xx_adau1373_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1701)
- &bf5xx_adau1701_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAV80X)
- &bfin_eval_adav801_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF6, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF6, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF6, 1);
-#endif
-
- return 0;
-}
-
-static int __init stamp_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- bfin_plat_nand_init();
- adf702x_mac_init();
- platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
- i2c_register_board_info(0, bfin_i2c_board_info,
- ARRAY_SIZE(bfin_i2c_board_info));
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(stamp_init);
-
-
-static struct platform_device *stamp_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(stamp_early_devices,
- ARRAY_SIZE(stamp_early_devices));
-}
-
-void native_machine_restart(char *cmd)
-{
- /* workaround reboot hang when booting from SPI */
- if ((bfin_read_SYSCR() & 0x7) == 0x3)
- bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
-}
-
-/*
- * Currently the MAC address is saved in Flash by U-Boot
- */
-#define FLASH_MAC 0x203f0000
-int bfin_get_ether_addr(char *addr)
-{
- *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
- *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
- return 0;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
deleted file mode 100644
index ed309c9a62b6..000000000000
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ /dev/null
@@ -1,792 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/etherdevice.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/spi/mmc_spi.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix TCM BF537";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
-static struct bfin5xx_spi_chip mmc_spi_chip_info = {
- .enable_dma = 0,
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .controller_data = &mmc_spi_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .start = 0x20200300,
- .end = 0x20200300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF14,
- .end = IRQ_PF14,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x20308000,
- .end = 0x20308000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x20308004,
- .end = 0x20308004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG15,
- .end = IRQ_PG15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x20300000,
- .end = 0x20300000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PG13,
- .end = IRQ_PG13,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
-static struct mtd_partition cm_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data cm_flash_data = {
- .width = 2,
- .parts = cm_partitions,
- .nr_parts = ARRAY_SIZE(cm_partitions),
-};
-
-static unsigned cm_flash_gpios[] = { GPIO_PF4, GPIO_PF5 };
-
-static struct resource cm_flash_resource[] = {
- {
- .name = "cfi_probe",
- .start = 0x20000000,
- .end = 0x201fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = (unsigned long)cm_flash_gpios,
- .end = ARRAY_SIZE(cm_flash_gpios),
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device cm_flash_device = {
- .name = "gpio-addr-flash",
- .id = 0,
- .dev = {
- .platform_data = &cm_flash_data,
- },
- .num_resources = ARRAY_SIZE(cm_flash_resource),
- .resource = cm_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI,
- .end = IRQ_TWI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
-#include <linux/bfin_mac.h>
-static const unsigned short bfin_mac_peripherals[] = P_MII0;
-
-static struct bfin_phydev_platform_data bfin_phydev_data[] = {
- {
- .addr = 1,
- .irq = IRQ_MAC_PHYINT,
- },
-};
-
-static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
- .phydev_number = 1,
- .phydev_data = bfin_phydev_data,
- .phy_mode = PHY_INTERFACE_MODE_MII,
- .mac_peripherals = bfin_mac_peripherals,
-};
-
-static struct platform_device bfin_mii_bus = {
- .name = "bfin_mii_bus",
- .dev = {
- .platform_data = &bfin_mii_bus_data,
- }
-};
-
-static struct platform_device bfin_mac_device = {
- .name = "bfin_mac",
- .dev = {
- .platform_data = &bfin_mii_bus,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF14
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2030C000,
- .end = 0x2030C01F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2030D018,
- .end = 0x2030D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 376000000),
- VRPAIR(VLEV_095, 426000000),
- VRPAIR(VLEV_100, 426000000),
- VRPAIR(VLEV_105, 476000000),
- VRPAIR(VLEV_110, 476000000),
- VRPAIR(VLEV_115, 476000000),
- VRPAIR(VLEV_120, 500000000),
- VRPAIR(VLEV_125, 533000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf537_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_MAC)
- &bfin_mii_bus,
- &bfin_mac_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_GPIO_ADDR)
- &cm_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PG14, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PG14 */
- gpio_direction_output(GPIO_PG14, 0);
- mdelay(2);
- gpio_set_value(GPIO_PG14, 1);
-#endif
-
- return 0;
-}
-
-static int __init tcm_bf537_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(tcm_bf537_init);
-
-static struct platform_device *cm_bf537_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf537_early_devices,
- ARRAY_SIZE(cm_bf537_early_devices));
-}
-
-int bfin_get_ether_addr(char *addr)
-{
- return 1;
-}
-EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
deleted file mode 100644
index 5c62e99c9fac..000000000000
--- a/arch/blackfin/mach-bf537/dma.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * This file contains the simple DMA Implementation for Blackfin
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_EMAC_RX:
- ret_irq = IRQ_MAC_RX;
- break;
-
- case CH_EMAC_TX:
- ret_irq = IRQ_MAC_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
-
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
deleted file mode 100644
index 2bc70c5b9415..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC TX DMA Error After an Early Frame Abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO Input Latched on Wrong MDC Edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* UART Gets Disabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
-#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* Buffered CLKIN Output Is Disabled by Default */
-#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bf537.h b/arch/blackfin/mach-bf537/include/mach/bf537.h
deleted file mode 100644
index 8b291418ca32..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/bf537.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * System MMR Register and memory map for ADSP-BF537
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF537_H__
-#define __MACH_BF537_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF537
-#define CPU "BF537"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF536
-#define CPU "BF536"
-#define CPUID 0x27c8
-#endif
-#ifdef CONFIG_BF534
-#define CPU "BF534"
-#define CPUID 0x27c6
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF537_H__ */
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
deleted file mode 100644
index 00c603fe8218..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
deleted file mode 100644
index baa096fc724a..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF537_FAMILY
-
-#include "bf537.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF534
-# include "defBF534.h"
-#endif
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "defBF537.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF534
-# include "cdefBF534.h"
-# endif
-# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-# include "cdefBF537.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
deleted file mode 100644
index 563ede907336..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ /dev/null
@@ -1,1736 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF534_H
-#define _CDEF_BF534_H
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR,val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR,val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL,val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER,val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH,val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR,val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR,val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR,val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR,val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR,val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR,val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS,val)
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO,val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR,val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET,val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA,val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR,val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET,val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB,val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR,val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET,val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR,val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR,val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE,val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH,val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN,val)
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-
-/* DMA Traffic Control Registers */
-#define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
-#define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
-#define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
-#define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG,val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR,val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT,val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT,val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY,val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY,val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR,val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR,val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT,val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT,val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS,val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG,val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR,val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT,val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT,val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY,val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY,val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR,val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR,val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT,val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT,val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS,val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG,val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR,val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT,val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT,val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY,val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY,val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR,val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR,val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT,val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT,val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS,val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG,val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR,val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT,val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT,val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY,val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY,val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR,val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR,val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT,val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT,val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS,val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val)
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO,val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR,val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET,val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA,val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR,val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET,val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB,val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR,val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET,val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR,val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR,val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE,val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH,val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN,val)
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO,val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR,val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET,val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA,val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR,val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET,val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB,val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR,val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET,val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR,val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR,val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE,val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH,val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN,val)
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR,val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL,val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER,val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH,val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR,val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR,val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR,val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR,val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR,val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR,val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL,val)
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1,val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1,val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1,val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1,val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1,val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1,val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1,val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1,val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1,val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1,val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1,val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1,val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1,val)
-
-/* For Mailboxes 16-31 */
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2,val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2,val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2,val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2,val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2,val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2,val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2,val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2,val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2,val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2,val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2,val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2,val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2,val)
-
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK,val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING,val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG,val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS,val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC,val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS,val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM,val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF,val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL,val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR,val)
-#define bfin_read_CAN_SFCMVER() bfin_read16(CAN_SFCMVER)
-#define bfin_write_CAN_SFCMVER(val) bfin_write16(CAN_SFCMVER,val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD,val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR,val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR,val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG,val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT,val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
-
-/* Mailbox Acceptance Masks */
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L,val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H,val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L,val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H,val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L,val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H,val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L,val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H,val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L,val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H,val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L,val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H,val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L,val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H,val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L,val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H,val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L,val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H,val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L,val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H,val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L,val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H,val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L,val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H,val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L,val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H,val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L,val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H,val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L,val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H,val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L,val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H,val)
-
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L,val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H,val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L,val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H,val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L,val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H,val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L,val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H,val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L,val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H,val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L,val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H,val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L,val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H,val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L,val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H,val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L,val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H,val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L,val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H,val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L,val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H,val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L,val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H,val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L,val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H,val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L,val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H,val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L,val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H,val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L,val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H,val)
-
-/* CAN Acceptance Mask Area Macros */
-#define bfin_read_CAN_AM_L(x)() bfin_read16(CAN_AM_L(x))
-#define bfin_write_CAN_AM_L(x)(val) bfin_write16(CAN_AM_L(x),val)
-#define bfin_read_CAN_AM_H(x)() bfin_read16(CAN_AM_H(x))
-#define bfin_write_CAN_AM_H(x)(val) bfin_write16(CAN_AM_H(x),val)
-
-/* Mailbox Registers */
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1,val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0,val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP,val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH,val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3,val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2,val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1,val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0,val)
-
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1,val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0,val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP,val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH,val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3,val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2,val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1,val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0,val)
-
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1,val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0,val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP,val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH,val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3,val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2,val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1,val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0,val)
-
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1,val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0,val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP,val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH,val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3,val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2,val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1,val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0,val)
-
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1,val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0,val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP,val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH,val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3,val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2,val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1,val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0,val)
-
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1,val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0,val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP,val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH,val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3,val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2,val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1,val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0,val)
-
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1,val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0,val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP,val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH,val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3,val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2,val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1,val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0,val)
-
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1,val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0,val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP,val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH,val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3,val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2,val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1,val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0,val)
-
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1,val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0,val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP,val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH,val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3,val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2,val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1,val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0,val)
-
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1,val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0,val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP,val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH,val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3,val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2,val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1,val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0,val)
-
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1,val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0,val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP,val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH,val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3,val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2,val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1,val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0,val)
-
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1,val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0,val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP,val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH,val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3,val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2,val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1,val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0,val)
-
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1,val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0,val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP,val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH,val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3,val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2,val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1,val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0,val)
-
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1,val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0,val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP,val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH,val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3,val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2,val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1,val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0,val)
-
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1,val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0,val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP,val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH,val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3,val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2,val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1,val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0,val)
-
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1,val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0,val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP,val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH,val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3,val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2,val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1,val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0,val)
-
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1,val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0,val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP,val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH,val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3,val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2,val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1,val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0,val)
-
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1,val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0,val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP,val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH,val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3,val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2,val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1,val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0,val)
-
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1,val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0,val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP,val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH,val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3,val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2,val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1,val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0,val)
-
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1,val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0,val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP,val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH,val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3,val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2,val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1,val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0,val)
-
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1,val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0,val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP,val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH,val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3,val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2,val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1,val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0,val)
-
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1,val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0,val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP,val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH,val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3,val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2,val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1,val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0,val)
-
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1,val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0,val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP,val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH,val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3,val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2,val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1,val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0,val)
-
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1,val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0,val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP,val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH,val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3,val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2,val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1,val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0,val)
-
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1,val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0,val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP,val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH,val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3,val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2,val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1,val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0,val)
-
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1,val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0,val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP,val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH,val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3,val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2,val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1,val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0,val)
-
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1,val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0,val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP,val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH,val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3,val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2,val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1,val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0,val)
-
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1,val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0,val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP,val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH,val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3,val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2,val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1,val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0,val)
-
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1,val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0,val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP,val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH,val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3,val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2,val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1,val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0,val)
-
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1,val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0,val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP,val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH,val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3,val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2,val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1,val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0,val)
-
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1,val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0,val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP,val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH,val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3,val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2,val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1,val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0,val)
-
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1,val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0,val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP,val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH,val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3,val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2,val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1,val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0,val)
-
-/* CAN Mailbox Area Macros */
-#define bfin_read_CAN_MB_ID1(x)() bfin_read16(CAN_MB_ID1(x))
-#define bfin_write_CAN_MB_ID1(x)(val) bfin_write16(CAN_MB_ID1(x),val)
-#define bfin_read_CAN_MB_ID0(x)() bfin_read16(CAN_MB_ID0(x))
-#define bfin_write_CAN_MB_ID0(x)(val) bfin_write16(CAN_MB_ID0(x),val)
-#define bfin_read_CAN_MB_TIMESTAMP(x)() bfin_read16(CAN_MB_TIMESTAMP(x))
-#define bfin_write_CAN_MB_TIMESTAMP(x)(val) bfin_write16(CAN_MB_TIMESTAMP(x),val)
-#define bfin_read_CAN_MB_LENGTH(x)() bfin_read16(CAN_MB_LENGTH(x))
-#define bfin_write_CAN_MB_LENGTH(x)(val) bfin_write16(CAN_MB_LENGTH(x),val)
-#define bfin_read_CAN_MB_DATA3(x)() bfin_read16(CAN_MB_DATA3(x))
-#define bfin_write_CAN_MB_DATA3(x)(val) bfin_write16(CAN_MB_DATA3(x),val)
-#define bfin_read_CAN_MB_DATA2(x)() bfin_read16(CAN_MB_DATA2(x))
-#define bfin_write_CAN_MB_DATA2(x)(val) bfin_write16(CAN_MB_DATA2(x),val)
-#define bfin_read_CAN_MB_DATA1(x)() bfin_read16(CAN_MB_DATA1(x))
-#define bfin_write_CAN_MB_DATA1(x)(val) bfin_write16(CAN_MB_DATA1(x),val)
-#define bfin_read_CAN_MB_DATA0(x)() bfin_read16(CAN_MB_DATA0(x))
-#define bfin_write_CAN_MB_DATA0(x)(val) bfin_write16(CAN_MB_DATA0(x),val)
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER,val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER,val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER,val)
-#define bfin_read_PORT_MUX() bfin_read16(BFIN_PORT_MUX)
-#define bfin_write_PORT_MUX(val) bfin_write16(BFIN_PORT_MUX,val)
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL,val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT,val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT,val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT,val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW,val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT,val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT,val)
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL,val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT,val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT,val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT,val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW,val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT,val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT,val)
-
-#endif /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
deleted file mode 100644
index 19ec21ea150a..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF537_H
-#define _CDEF_BF537_H
-
-/* Include MMRs Common to BF534 */
-#include "cdefBF534.h"
-
-/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE,val)
-#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO,val)
-#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI,val)
-#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO,val)
-#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI,val)
-#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD,val)
-#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT,val)
-#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC,val)
-#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1,val)
-#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2,val)
-#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL,val)
-#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0,val)
-#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1,val)
-#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2,val)
-#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3,val)
-#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD,val)
-#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF,val)
-#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0,val)
-#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1,val)
-
-#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL,val)
-#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT,val)
-#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT,val)
-#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY,val)
-#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE,val)
-#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT,val)
-#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY,val)
-#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE,val)
-
-#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL,val)
-#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS,val)
-#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE,val)
-#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS,val)
-#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE,val)
-
-#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK,val)
-#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS,val)
-#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN,val)
-#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET,val)
-#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF,val)
-#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST,val)
-#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI,val)
-#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD,val)
-#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI,val)
-#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO,val)
-#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG,val)
-#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL,val)
-#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE,val)
-#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE,val)
-#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM,val)
-#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT,val)
-#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED,val)
-#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT,val)
-#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64,val)
-#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128,val)
-#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256,val)
-#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512,val)
-#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024,val)
-#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024,val)
-
-#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK,val)
-#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL,val)
-#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL,val)
-#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET,val)
-#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER,val)
-#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL,val)
-#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL,val)
-#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND,val)
-#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR,val)
-#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST,val)
-#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI,val)
-#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD,val)
-#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR,val)
-#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL,val)
-#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM,val)
-#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT,val)
-#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64,val)
-#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128,val)
-#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256,val)
-#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512,val)
-#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024,val)
-#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024,val)
-#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT,val)
-
-#endif /* _CDEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
deleted file mode 100644
index ef6a98cdfd44..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ /dev/null
@@ -1,1470 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF534_H
-#define _DEF_BF534_H
-
-/************************************************************************************
-** System MMR Register Map
-*************************************************************************************/
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control Register */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register */
-#define SYSCR 0xFFC00104 /* System Configuration Register */
-#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_MSR 0xFFC00418 /* Modem Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
-
-#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* DMA Traffic Control Registers */
-#define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
-#define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_REGBASE 0xFFC01400
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_MSR 0xFFC02018 /* Modem Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
-
-/* CAN Configuration, Control, and Status Registers */
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
-
-/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
-#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
-
-#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
-#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
-#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
-#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
-#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
-#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
-#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
-#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
-#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
-#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
-#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
-#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
-#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
-#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
-#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
-#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
-#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
-#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
-#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
-#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
-#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
-#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
-#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
-#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
-#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
-#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
-#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
-#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
-#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-
-/* **************** GENERAL PURPOSE TIMER MASKS **********************/
-/* TIMER_ENABLE Masks */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-#define TIMEN3 0x0008 /* Enable Timer 3 */
-#define TIMEN4 0x0010 /* Enable Timer 4 */
-#define TIMEN5 0x0020 /* Enable Timer 5 */
-#define TIMEN6 0x0040 /* Enable Timer 6 */
-#define TIMEN7 0x0080 /* Enable Timer 7 */
-
-/* TIMER_DISABLE Masks */
-#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
-#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
-#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
-#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
-#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
-#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
-#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
-#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
-
-/* TIMER_STATUS Masks */
-#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
-#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
-#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
-#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
-#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
-#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
-#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
-#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
-#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
-#define EXT_CLK 0x0003 /* External Clock Mode */
-#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
-#define PERIOD_CNT 0x0008 /* Period Count */
-#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
-#define TIN_SEL 0x0020 /* Timer Input Select */
-#define OUT_DIS 0x0040 /* Output Pad Disable */
-#define CLK_SEL 0x0080 /* Timer Clock Select */
-#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
-#define EMU_RUN 0x0200 /* Emulation Behavior Select */
-#define ERR_TYP 0xC000 /* Error Type */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
-#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
-#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
-#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
-#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
-#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
-#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
-
-#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
-#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
-#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
-#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
-#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
-#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
-#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
-#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
-#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
-#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
-#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
-#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
-#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
-
-#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
-#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
-#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
-#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
-#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
-#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
-#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
-#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
-#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
-#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
-#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
-#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
-#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
-#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
-#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS **********************************************/
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SDRAM Signals */
-#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
-#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
-#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
-#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
-#define EBUFE 0x02000000 /* Enable External Buffering Timing */
-#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
-#define EMREN 0x10000000 /* Extended Mode Register Enable */
-#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
-#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x0001 /* Enable SDRAM External Bank */
-#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
-#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
-#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
-#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
-#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
-#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
-#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
-#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x0001 /* SDRAM Controller Idle */
-#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
-#define SDPUA 0x0004 /* SDRAM Power-Up Active */
-#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
-#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
-#define BGSTAT 0x0020 /* Bus Grant Status */
-
-/* ************************** DMA CONTROLLER MASKS ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
-#define PMAP_PPI 0x0000 /* PPI Port DMA */
-#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
-#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
-#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
-#define PMAP_SPI 0x7000 /* SPI Port DMA */
-#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
-#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
-#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
-#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
-
-/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0000 /* Data Length = 8 Bits */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ******************* PIN CONTROL REGISTER MASKS ************************/
-/* PORT_MUX Masks */
-#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
-#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
-#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
-
-#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
-#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
-#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
-#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
-
-#define PFDE 0x0008 /* Port F DMA Request Enable */
-#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
-#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
-
-#define PFTE 0x0010 /* Port F Timer Enable */
-#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
-#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
-
-#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
-#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
-#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
-
-#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
-#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
-#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
-
-#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
-#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
-#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
-
-#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
-#define PFFE_TIMER 0x0000 /* Enable TMR2 */
-#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
-
-#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
-#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
-#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
-
-#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
-#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
-#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
-
-#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
-#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
-#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART PFDE_UART
-#define PGDE_DMA PFDE_DMA
-#define CKELOW SCKELOW
-#endif /* _DEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
deleted file mode 100644
index e10332c9f660..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF537_H
-#define _DEF_BF537_H
-
-/* Include all MMR and bit defines common to BF534 */
-#include "defBF534.h"
-
-/************************************************************************************
-** Define EMAC Section Unique to BF536/BF537
-*************************************************************************************/
-
-/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
-#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-
-#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-
-#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
-
-#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
-#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-/* Listing for IEEE-Supported Count Registers */
-#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
-#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
-#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
-#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
-#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
-#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
-#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
-#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
-#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
-#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
-#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
-#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
-#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
-#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
-#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
-#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
-#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
-#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
-#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
-
-#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
-#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
-#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
-#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
-#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
-#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
-#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
-#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
-#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
-#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
-#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
-#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
-#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
-#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
-#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
-#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
-#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
-#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer: All macros are intended to make C and Assembly code more readable.
-** Use these macros carefully, as any that do left shifts for field
-** depositing will result in the lower order bits being destroyed. Any
-** macro that shifts left to properly position the bit-field should be
-** used as part of an OR to initialize a register and NOT as a dynamic
-** modifier UNLESS the lower order bits are saved and ORed back in when
-** the macro is used.
-*************************************************************************************/
-/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
-/* EMAC_OPMODE Masks */
-#define RE 0x00000001 /* Receiver Enable */
-#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
-#define HU 0x00000010 /* Hash Filter Unicast Address */
-#define HM 0x00000020 /* Hash Filter Multicast Address */
-#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
-#define PR 0x00000080 /* Promiscuous Mode Enable */
-#define IFE 0x00000100 /* Inverse Filtering Enable */
-#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
-#define PBF 0x00000400 /* Pass Bad Frames Enable */
-#define PSF 0x00000800 /* Pass Short Frames Enable */
-#define RAF 0x00001000 /* Receive-All Mode */
-#define TE 0x00010000 /* Transmitter Enable */
-#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
-#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
-#define DC 0x00080000 /* Deferral Check */
-#define BOLMT 0x00300000 /* Back-Off Limit */
-#define BOLMT_10 0x00000000 /* 10-bit range */
-#define BOLMT_8 0x00100000 /* 8-bit range */
-#define BOLMT_4 0x00200000 /* 4-bit range */
-#define BOLMT_1 0x00300000 /* 1-bit range */
-#define DRTY 0x00400000 /* Disable TX Retry On Collision */
-#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
-#define RMII 0x01000000 /* RMII/MII* Mode */
-#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
-#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
-#define LB 0x08000000 /* Internal Loopback Enable */
-#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
-
-/* EMAC_STAADD Masks */
-#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
-#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
-#define STADISPRE 0x00000004 /* Disable Preamble Generation */
-#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
-#define REGAD 0x000007C0 /* STA Register Address */
-#define PHYAD 0x0000F800 /* PHY Device Address */
-
-#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
-
-/* EMAC_STADAT Mask */
-#define STADATA 0x0000FFFF /* Station Management Data */
-
-/* EMAC_FLC Masks */
-#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
-#define FLCE 0x00000002 /* Flow Control Enable */
-#define PCF 0x00000004 /* Pass Control Frames */
-#define BKPRSEN 0x00000008 /* Enable Backpressure */
-#define FLCPAUSE 0xFFFF0000 /* Pause Time */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
-
-/* EMAC_WKUP_CTL Masks */
-#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
-#define MPKE 0x00000002 /* Magic Packet Enable */
-#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
-#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
-#define MPKS 0x00000020 /* Magic Packet Received Status */
-#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
-
-/* EMAC_WKUP_FFCMD Masks */
-#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
-#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
-#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
-#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
-#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
-#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
-#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
-#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
-
-/* EMAC_WKUP_FFOFF Masks */
-#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
-#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
-#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
-#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
-#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
-#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
-#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
-
-/* EMAC_SYSCTL Masks */
-#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
-#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
-#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
-#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
-#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
-
-/* EMAC_SYSTAT Masks */
-#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
-#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
-#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
-#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
-#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
-#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
-#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
-#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
-#define RX_COMP 0x00001000 /* RX Frame Complete */
-#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
-#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
-#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
-#define RX_CRC 0x00010000 /* RX Frame CRC Error */
-#define RX_LEN 0x00020000 /* RX Frame Length Error */
-#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
-#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
-#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
-#define RX_PHY 0x00200000 /* RX Frame PHY Error */
-#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
-#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
-#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
-#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
-#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
-#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
-#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
-#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
-#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
-#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
-
-/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
-#define TX_COMP 0x00000001 /* TX Frame Complete */
-#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
-#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
-#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
-#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
-#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
-#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
-#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
-#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
-#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
-#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
-#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
-#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
-#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
-#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC 0x00000001 /* Reset All Counters */
-#define CROLL 0x00000002 /* Counter Roll-Over Enable */
-#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
-#define MMCE 0x00000008 /* Enable MMC Counter Operation */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
-#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
-#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
-#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
-#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
-#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
-#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
-#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
-#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
-#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
-#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
-#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
-#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
-#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
-#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
-#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
-#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
-#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
-#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
-#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
-#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
-#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
-#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
-#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
-#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
-#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
-#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
-#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
-#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
-#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
-#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
-#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
-#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
-#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
-#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
-#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
-#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
-#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
-#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
-#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
-#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
-#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
-#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
-#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
-#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
-#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
-#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
-
-#endif /* _DEF_BF537_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/dma.h b/arch/blackfin/mach-bf537/include/mach/dma.h
deleted file mode 100644
index 5ae83b1183a1..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/dma.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 16
-
-#define CH_PPI 0
-#define CH_EMAC_RX 1
-#define CH_EMAC_TX 2
-#define CH_SPORT0_RX 3
-#define CH_SPORT0_TX 4
-#define CH_SPORT1_RX 5
-#define CH_SPORT1_TX 6
-#define CH_SPI 7
-#define CH_UART0_RX 8
-#define CH_UART0_TX 9
-#define CH_UART1_RX 10
-#define CH_UART1_TX 11
-
-#define CH_MEM_STREAM0_DEST 12 /* TX */
-#define CH_MEM_STREAM0_SRC 13 /* RX */
-#define CH_MEM_STREAM1_DEST 14 /* TX */
-#define CH_MEM_STREAM1_SRC 15 /* RX */
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
deleted file mode 100644
index fba606b699c3..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PG0 16
-#define GPIO_PG1 17
-#define GPIO_PG2 18
-#define GPIO_PG3 19
-#define GPIO_PG4 20
-#define GPIO_PG5 21
-#define GPIO_PG6 22
-#define GPIO_PG7 23
-#define GPIO_PG8 24
-#define GPIO_PG9 25
-#define GPIO_PG10 26
-#define GPIO_PG11 27
-#define GPIO_PG12 28
-#define GPIO_PG13 29
-#define GPIO_PG14 30
-#define GPIO_PG15 31
-#define GPIO_PH0 32
-#define GPIO_PH1 33
-#define GPIO_PH2 34
-#define GPIO_PH3 35
-#define GPIO_PH4 36
-#define GPIO_PH5 37
-#define GPIO_PH6 38
-#define GPIO_PH7 39
-#define GPIO_PH8 40
-#define GPIO_PH9 41
-#define GPIO_PH10 42
-#define GPIO_PH11 43
-#define GPIO_PH12 44
-#define GPIO_PH13 45
-#define GPIO_PH14 46
-#define GPIO_PH15 47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
deleted file mode 100644
index b6ed8235bda4..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _BF537_IRQ_H_
-#define _BF537_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS 32
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
-#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
-#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
-#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
-#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
-#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
-#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
-#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
-#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
-#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
-#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
-#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
-#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
-#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
-#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
-#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
-
-#define SYS_IRQS 39
-
-#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
-#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
-#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
-#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
-#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
-#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
-
-#define IRQ_PF0 50
-#define IRQ_PF1 51
-#define IRQ_PF2 52
-#define IRQ_PF3 53
-#define IRQ_PF4 54
-#define IRQ_PF5 55
-#define IRQ_PF6 56
-#define IRQ_PF7 57
-#define IRQ_PF8 58
-#define IRQ_PF9 59
-#define IRQ_PF10 60
-#define IRQ_PF11 61
-#define IRQ_PF12 62
-#define IRQ_PF13 63
-#define IRQ_PF14 64
-#define IRQ_PF15 65
-
-#define IRQ_PG0 66
-#define IRQ_PG1 67
-#define IRQ_PG2 68
-#define IRQ_PG3 69
-#define IRQ_PG4 70
-#define IRQ_PG5 71
-#define IRQ_PG6 72
-#define IRQ_PG7 73
-#define IRQ_PG8 74
-#define IRQ_PG9 75
-#define IRQ_PG10 76
-#define IRQ_PG11 77
-#define IRQ_PG12 78
-#define IRQ_PG13 79
-#define IRQ_PG14 80
-#define IRQ_PG15 81
-
-#define IRQ_PH0 82
-#define IRQ_PH1 83
-#define IRQ_PH2 84
-#define IRQ_PH3 85
-#define IRQ_PH4 86
-#define IRQ_PH5 87
-#define IRQ_PH6 88
-#define IRQ_PH7 89
-#define IRQ_PH8 90
-#define IRQ_PH9 91
-#define IRQ_PH10 92
-#define IRQ_PH11 93
-#define IRQ_PH12 94
-#define IRQ_PH13 95
-#define IRQ_PH14 96
-#define IRQ_PH15 97
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
-
-#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
-#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
-#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
-#else
-#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
-#endif
-
-#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
-#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
-
-#if 0 /* No Interrupt B support (yet) */
-#define IRQ_WATCH 112 /* Watchdog Timer */
-#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
-#else
-#define IRQ_WATCH IRQ_PF_INTB_WATCH
-#endif
-
-#define NR_MACH_IRQS (113 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA_ERROR_POS 4
-#define IRQ_ERROR_POS 8
-#define IRQ_RTC_POS 12
-#define IRQ_PPI_POS 16
-#define IRQ_SPORT0_RX_POS 20
-#define IRQ_SPORT0_TX_POS 24
-#define IRQ_SPORT1_RX_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT1_TX_POS 0
-#define IRQ_TWI_POS 4
-#define IRQ_SPI_POS 8
-#define IRQ_UART0_RX_POS 12
-#define IRQ_UART0_TX_POS 16
-#define IRQ_UART1_RX_POS 20
-#define IRQ_UART1_TX_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MAC_RX_POS 4
-#define IRQ_MAC_TX_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_PROG_INTA_POS 12
-#define IRQ_PORTG_INTB_POS 16
-#define IRQ_MEM_DMA0_POS 20
-#define IRQ_MEM_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-#define init_mach_irq init_mach_irq
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/mem_map.h b/arch/blackfin/mach-bf537/include/mach/mem_map.h
deleted file mode 100644
index 942f08de306b..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/mem_map.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * BF537 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF537 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-
-#ifdef CONFIG_BF537
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif /*CONFIG_BF537*/
-
-/* Memory Map for ADSP-BF536 processors */
-
-#ifdef CONFIG_BF536
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF804000
-#define L1_DATA_B_START 0xFF904000
-
-#define L1_CODE_LENGTH 0xC000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x4000
-#define L1_DATA_B_LENGTH 0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Memory Map for ADSP-BF534 processors */
-
-#ifdef CONFIG_BF534
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/portmux.h b/arch/blackfin/mach-bf537/include/mach/portmux.h
deleted file mode 100644
index 71d9eaeb579e..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/portmux.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
-
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0 (GPIO_PH15 + 1)
-#define PORT_PJ1 (GPIO_PH15 + 2)
-#define PORT_PJ2 (GPIO_PH15 + 3)
-#define PORT_PJ3 (GPIO_PH15 + 4)
-#define PORT_PJ4 (GPIO_PH15 + 5)
-#define PORT_PJ5 (GPIO_PH15 + 6)
-#define PORT_PJ6 (GPIO_PH15 + 7)
-#define PORT_PJ7 (GPIO_PH15 + 8)
-#define PORT_PJ8 (GPIO_PH15 + 9)
-#define PORT_PJ9 (GPIO_PH15 + 10)
-#define PORT_PJ10 (GPIO_PH15 + 11)
-#define PORT_PJ11 (GPIO_PH15 + 12)
-
-#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxD2, \
- P_MII0_ETxD3, \
- P_MII0_ETxEN, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_COL, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxD2, \
- P_MII0_ERxD3, \
- P_MII0_ERxDV, \
- P_MII0_ERxCLK, \
- P_MII0_ERxER, \
- P_MII0_CRS, \
- P_MDC, \
- P_MDIO, 0}
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_RMII0_REF_CLK, \
- P_RMII0_MDINT, \
- P_RMII0_CRS_DV, \
- P_MDC, \
- P_MDIO, 0}
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
deleted file mode 100644
index a48baae4384d..000000000000
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-#include <asm/irq_handler.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_sport.h>
-#include <asm/bfin_can.h>
-#include <asm/bfin_dma.h>
-#include <asm/dpmc.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
- ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
- ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
- ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
- ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
- ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
- ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
- ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- SSYNC();
-}
-
-#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
-#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
-#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
-#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
-#define UART_ERR_MASK (0x6) /* UART_IIR */
-#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
-
-static int error_int_mask;
-
-static void bf537_generic_error_mask_irq(struct irq_data *d)
-{
- error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
- if (!error_int_mask)
- bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
-}
-
-static void bf537_generic_error_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
- error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
-}
-
-static struct irq_chip bf537_generic_error_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_generic_error_mask_irq,
- .irq_mask = bf537_generic_error_mask_irq,
- .irq_unmask = bf537_generic_error_unmask_irq,
-};
-
-static void bf537_demux_error_irq(struct irq_desc *inta_desc)
-{
- int irq = 0;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
- irq = IRQ_MAC_ERROR;
- else
-#endif
- if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT0_ERROR;
- else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT1_ERROR;
- else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
- irq = IRQ_PPI_ERROR;
- else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
- irq = IRQ_CAN_ERROR;
- else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
- irq = IRQ_SPI_ERROR;
- else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART0_ERROR;
- else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART1_ERROR;
-
- if (irq) {
- if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
- bfin_handle_irq(irq);
- else {
-
- switch (irq) {
- case IRQ_PPI_ERROR:
- bfin_write_PPI_STATUS(PPI_ERR_MASK);
- break;
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- case IRQ_MAC_ERROR:
- bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
- break;
-#endif
- case IRQ_SPORT0_ERROR:
- bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_SPORT1_ERROR:
- bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_CAN_ERROR:
- bfin_write_CAN_GIS(CAN_ERR_MASK);
- break;
-
- case IRQ_SPI_ERROR:
- bfin_write_SPI_STAT(SPI_ERR_MASK);
- break;
-
- default:
- break;
- }
-
- pr_debug("IRQ %d:"
- " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
- __func__);
-
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_rx_int_mask;
-
-static void bf537_mac_rx_mask_irq(struct irq_data *d)
-{
- mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
- if (!mac_rx_int_mask)
- bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
-}
-
-static void bf537_mac_rx_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
- mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
-}
-
-static struct irq_chip bf537_mac_rx_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bf537_mac_rx_mask_irq,
- .irq_mask = bf537_mac_rx_mask_irq,
- .irq_unmask = bf537_mac_rx_unmask_irq,
-};
-
-static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
-{
- if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
- bfin_handle_irq(IRQ_MAC_RX);
- else
- bfin_demux_gpio_irq(desc);
-}
-#endif
-
-void __init init_mach_irq(void)
-{
- int irq;
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
- /* Clear EMAC Interrupt Status bits so we can demux it later */
- bfin_write_EMAC_SYSTAT(-1);
-#endif
-
- irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
- for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
- irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
- handle_level_irq);
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
- irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
- irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
-
- irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
-#endif
-}
diff --git a/arch/blackfin/mach-bf538/Kconfig b/arch/blackfin/mach-bf538/Kconfig
deleted file mode 100644
index 4aea85e4e5cf..000000000000
--- a/arch/blackfin/mach-bf538/Kconfig
+++ /dev/null
@@ -1,166 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF538 || BF539)
-
-source "arch/blackfin/mach-bf538/boards/Kconfig"
-
-menu "BF538 Specific Configuration"
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMA0_ERROR
- int "IRQ_DMA0_ERROR"
- default 7
-config IRQ_PPI_ERROR
- int "IRQ_PPI_ERROR"
- default 7
-config IRQ_SPORT0_ERROR
- int "IRQ_SPORT0_ERROR"
- default 7
-config IRQ_SPORT1_ERROR
- int "IRQ_SPORT1_ERROR"
- default 7
-config IRQ_SPI0_ERROR
- int "IRQ_SPI0_ERROR"
- default 7
-config IRQ_UART0_ERROR
- int "IRQ_UART0_ERROR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_PPI
- int "IRQ_PPI"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_PORTF_INTA
- int "IRQ_PORTF_INTA"
- default 12
-config IRQ_PORTF_INTB
- int "IRQ_PORTF_INTB"
- default 12
-config IRQ_MEM0_DMA0
- int "IRQ_MEM0_DMA0"
- default 13
-config IRQ_MEM0_DMA1
- int "IRQ_MEM0_DMA1"
- default 13
-config IRQ_WATCH
- int "IRQ_WATCH"
- default 13
-config IRQ_DMA1_ERROR
- int "IRQ_DMA1_ERROR"
- default 7
-config IRQ_SPORT2_ERROR
- int "IRQ_SPORT2_ERROR"
- default 7
-config IRQ_SPORT3_ERROR
- int "IRQ_SPORT3_ERROR"
- default 7
-config IRQ_SPI1_ERROR
- int "IRQ_SPI1_ERROR"
- default 7
-config IRQ_SPI2_ERROR
- int "IRQ_SPI2_ERROR"
- default 7
-config IRQ_UART1_ERROR
- int "IRQ_UART1_ERROR"
- default 7
-config IRQ_UART2_ERROR
- int "IRQ_UART2_ERROR"
- default 7
-config IRQ_CAN_ERROR
- int "IRQ_CAN_ERROR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_UART2_RX
- int "IRQ_UART2_RX"
- default 10
-config IRQ_UART2_TX
- int "IRQ_UART2_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MEM1_DMA0
- int "IRQ_MEM1_DMA0"
- default 13
-config IRQ_MEM1_DMA1
- int "IRQ_MEM1_DMA1"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf538/Makefile b/arch/blackfin/mach-bf538/Makefile
deleted file mode 100644
index c0be54f2cd2b..000000000000
--- a/arch/blackfin/mach-bf538/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf538/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-obj-$(CONFIG_GPIOLIB) += ext-gpio.o
diff --git a/arch/blackfin/mach-bf538/boards/Kconfig b/arch/blackfin/mach-bf538/boards/Kconfig
deleted file mode 100644
index 114cff440d43..000000000000
--- a/arch/blackfin/mach-bf538/boards/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN538_EZKIT
- help
- Select your board!
-
-config BFIN538_EZKIT
- bool "BF538-EZKIT"
- help
- BF538-EZKIT-LITE board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf538/boards/Makefile b/arch/blackfin/mach-bf538/boards/Makefile
deleted file mode 100644
index 6143b320d585..000000000000
--- a/arch/blackfin/mach-bf538/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf538/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN538_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
deleted file mode 100644
index 1b6a52ad8a0e..000000000000
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ /dev/null
@@ -1,987 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF538-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif /* CONFIG_RTC_DRV_BFIN */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_THR,
- .end = UART0_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin */
- .start = GPIO_PG7,
- .end = GPIO_PG7,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin */
- .start = GPIO_PG6,
- .end = GPIO_PG6,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART0 */
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_THR,
- .end = UART1_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX, 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART1 */
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_THR,
- .end = UART2_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_UART2 */
-#endif /* CONFIG_SERIAL_BFIN */
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif /* CONFIG_BFIN_SIR0 */
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif /* CONFIG_BFIN_SIR1 */
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif /* CONFIG_BFIN_SIR2 */
-#endif /* CONFIG_BFIN_SIR */
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
-#endif /* CONFIG_SERIAL_BFIN_SPORT */
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN_RX,
- .end = IRQ_CAN_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_TX,
- .end = IRQ_CAN_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN_ERROR,
- .end = IRQ_CAN_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif /* CONFIG_CAN_BFIN */
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x20310300,
- .end = 0x20310300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif /* CONFIG_SMC91X */
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif /* CONFIG_MTD_M25P80 */
-#endif /* CONFIG_SPI_BFIN5XX */
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879)
-#include <linux/platform_data/ad7879.h>
-static const struct ad7879_platform_data bfin_ad7879_ts_info = {
- .model = 7879, /* Model = AD7879 */
- .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
- .pressure_max = 10000,
- .pressure_min = 0,
- .first_conversion_delay = 3, /* wait 512us before do a first conversion */
- .acquisition_time = 1, /* 4us acquisition time per sample */
- .median = 2, /* do 8 measurements */
- .averaging = 1, /* take the average of 4 middle samples */
- .pen_down_acc_interval = 255, /* 9.4 ms */
- .gpio_export = 1, /* Export GPIO to gpiolib */
- .gpio_base = -1, /* Dynamic allocation */
-};
-#endif /* CONFIG_TOUCHSCREEN_AD7879 */
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
-#include <asm/bfin-lq035q1.h>
-
-static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
- .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
- .ppi_mode = USE_RGB565_16_BIT_PPI,
- .use_bl = 0, /* let something else control the LCD Blacklight */
- .gpio_bl = GPIO_PF7,
-};
-
-static struct resource bfin_lq035q1_resources[] = {
- {
- .start = IRQ_PPI_ERROR,
- .end = IRQ_PPI_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_lq035q1_device = {
- .name = "bfin-lq035q1",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
- .resource = bfin_lq035q1_resources,
- .dev = {
- .platform_data = &bfin_lq035q1_data,
- },
-};
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-
-static struct spi_board_info bf538_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif /* CONFIG_MTD_M25P80 */
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7879_SPI)
- {
- .modalias = "ad7879",
- .platform_data = &bfin_ad7879_ts_info,
- .irq = IRQ_PF3,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- {
- .modalias = "bfin-lq035q1-spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
- .mode = SPI_CPHA | SPI_CPOL,
- },
-#endif /* CONFIG_FB_BFIN_LQ035Q1 */
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif /* CONFIG_SPI_SPIDEV */
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (2) */
-static struct resource bfin_spi2_resource[] = {
- [0] = {
- .start = SPI2_REGBASE,
- .end = SPI2_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI2,
- .end = CH_SPI2,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI2,
- .end = IRQ_SPI2,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf538_spi_master_info0 = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info1 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info1, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf538_spi_master_info2 = {
- .num_chipselect = 2,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
-};
-
-static struct platform_device bf538_spi_master2 = {
- .name = "bfin-spi",
- .id = 2, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi2_resource),
- .resource = bfin_spi2_resource,
- .dev = {
- .platform_data = &bf538_spi_master_info2, /* Passed to driver */
- },
-};
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
-};
-#endif /* CONFIG_I2C_BLACKFIN_TWI */
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF538SBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_100, 150000000),
- VRPAIR(VLEV_100, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
-#if IS_ENABLED(CONFIG_SMC91X)
- .end = 0x202fffff,
-#else
- .end = 0x203fffff,
-#endif
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-static struct platform_device *cm_bf538_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf538_spi_master0,
- &bf538_spi_master1,
- &bf538_spi_master2,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
- &i2c_bfin_twi1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BFIN_LQ035Q1)
- &bfin_lq035q1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf538_spi_board_info,
- ARRAY_SIZE(bf538_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c
deleted file mode 100644
index cce8ef5a5cec..000000000000
--- a/arch/blackfin/mach-bf538/dma.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI:
- ret_irq = IRQ_PPI;
- break;
-
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
-
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
-
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
-
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
-
- case CH_UART2_RX:
- ret_irq = IRQ_UART2_RX;
- break;
-
- case CH_UART2_TX:
- ret_irq = IRQ_UART2_TX;
- break;
-
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
-
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
-
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
-
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
-
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
-
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
-
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
-
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
-
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
-
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
-
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM0_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM0_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM1_DMA0;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM1_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf538/ext-gpio.c b/arch/blackfin/mach-bf538/ext-gpio.c
deleted file mode 100644
index 48c100228f2d..000000000000
--- a/arch/blackfin/mach-bf538/ext-gpio.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs
- *
- * Copyright 2009-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-#define DEFINE_REG(reg, off) \
-static inline u16 read_##reg(void __iomem *port) \
- { return bfin_read16(port + off); } \
-static inline void write_##reg(void __iomem *port, u16 v) \
- { bfin_write16(port + off, v); }
-
-DEFINE_REG(PORTIO, 0x00)
-DEFINE_REG(PORTIO_CLEAR, 0x10)
-DEFINE_REG(PORTIO_SET, 0x20)
-DEFINE_REG(PORTIO_DIR, 0x40)
-DEFINE_REG(PORTIO_INEN, 0x50)
-
-static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip)
-{
- switch (chip->base) {
- default: /* not really needed, but keeps gcc happy */
- case GPIO_PC0: return (void __iomem *)PORTCIO;
- case GPIO_PD0: return (void __iomem *)PORTDIO;
- case GPIO_PE0: return (void __iomem *)PORTEIO;
- }
-}
-
-static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- return !!(read_PORTIO(port) & (1u << gpio));
-}
-
-static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- if (value)
- write_PORTIO_SET(port, (1u << gpio));
- else
- write_PORTIO_CLEAR(port, (1u << gpio));
-}
-
-static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio));
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
-{
- void __iomem *port = gpio_chip_to_mmr(chip);
- write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio));
- bf538_gpio_set_value(port, gpio, value);
- write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio));
- return 0;
-}
-
-static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_request(chip->base + gpio, chip->label);
-}
-
-static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio)
-{
- return bfin_special_gpio_free(chip->base + gpio);
-}
-
-/* We don't set the irq fields as these banks cannot generate interrupts */
-
-static struct gpio_chip bf538_portc_chip = {
- .label = "GPIO-PC",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PC0,
- .ngpio = GPIO_PC9 - GPIO_PC0 + 1,
-};
-
-static struct gpio_chip bf538_portd_chip = {
- .label = "GPIO-PD",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PD0,
- .ngpio = GPIO_PD13 - GPIO_PD0 + 1,
-};
-
-static struct gpio_chip bf538_porte_chip = {
- .label = "GPIO-PE",
- .direction_input = bf538_gpio_direction_input,
- .get = bf538_gpio_get_value,
- .direction_output = bf538_gpio_direction_output,
- .set = bf538_gpio_set_value,
- .request = bf538_gpio_request,
- .free = bf538_gpio_free,
- .base = GPIO_PE0,
- .ngpio = GPIO_PE15 - GPIO_PE0 + 1,
-};
-
-static int __init bf538_extgpio_setup(void)
-{
- return gpiochip_add_data(&bf538_portc_chip, NULL) |
- gpiochip_add_data(&bf538_portd_chip, NULL) |
- gpiochip_add_data(&bf538_porte_chip, NULL);
-}
-arch_initcall(bf538_extgpio_setup);
-
-#ifdef CONFIG_PM
-static struct {
- u16 data, dir, inen;
-} gpio_bank_saved[3];
-
-static void __iomem * const port_bases[3] = {
- (void *)PORTCIO,
- (void *)PORTDIO,
- (void *)PORTEIO,
-};
-
-void bfin_special_gpio_pm_hibernate_suspend(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- gpio_bank_saved[i].data = read_PORTIO(port_bases[i]);
- gpio_bank_saved[i].inen = read_PORTIO_INEN(port_bases[i]);
- gpio_bank_saved[i].dir = read_PORTIO_DIR(port_bases[i]);
- }
-}
-
-void bfin_special_gpio_pm_hibernate_restore(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(port_bases); ++i) {
- write_PORTIO_INEN(port_bases[i], gpio_bank_saved[i].inen);
- write_PORTIO_SET(port_bases[i],
- gpio_bank_saved[i].data & gpio_bank_saved[i].dir);
- write_PORTIO_DIR(port_bases[i], gpio_bank_saved[i].dir);
- }
-}
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
deleted file mode 100644
index eaac26973f6a..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 4
-# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3
-#endif
-
-#if defined(__ADSPBF538__)
-# define ANOMALY_BF538 1
-#else
-# define ANOMALY_BF538 0
-#endif
-#if defined(__ADSPBF539__)
-# define ANOMALY_BF539 1
-#else
-# define ANOMALY_BF539 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (1)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (1)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (ANOMALY_BF538)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 4)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 4)
-/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */
-#define ANOMALY_05000291 (__SILICON_REVISION__ < 4)
-/* Hibernate Leakage Current Is Higher Than Specified */
-#define ANOMALY_05000293 (__SILICON_REVISION__ < 4)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000294 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 4)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 4)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 4)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 5)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
-/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
-#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
-/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
-#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 5)
-/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
-#define ANOMALY_05000374 (__SILICON_REVISION__ == 4)
-/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
-#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Specific GPIO Pins May Change State when Entering Hibernate */
-#define ANOMALY_05000436 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bf538.h b/arch/blackfin/mach-bf538/include/mach/bf538.h
deleted file mode 100644
index 0cf5bf8dab84..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/bf538.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF538_H__
-#define __MACH_BF538_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF538
-#define CPU "BF538"
-#define CPUID 0x27C4
-#endif
-#ifdef CONFIG_BF539
-#define CPU "BF539"
-#define CPUID 0x27C4 /* FXIME:? */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF538_H__ */
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
deleted file mode 100644
index c66e2760aad3..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 3
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
deleted file mode 100644
index 791d08400cf0..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF538_FAMILY
-
-#include "bf538.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF538
-# include "defBF538.h"
-#endif
-#ifdef CONFIG_BF539
-# include "defBF539.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF538
-# include "cdefBF538.h"
-# endif
-# ifdef CONFIG_BF539
-# include "cdefBF539.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
deleted file mode 100644
index f6a56792180b..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ /dev/null
@@ -1,1960 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF538_H
-#define _CDEF_BF538_H
-
-#define bfin_writePTR(addr, val) bfin_write32(addr, val)
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0), val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))
-#define bfin_write_SIC_IWR(x, val) bfin_write32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0), val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART2_THR() bfin_read16(UART2_THR)
-#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_IER() bfin_read16(UART2_IER)
-#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val)
-#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR)
-#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER)
-#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val)
-#define bfin_read_PORTCIO() bfin_read16(PORTCIO)
-#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val)
-#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR)
-#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val)
-#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET)
-#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val)
-#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE)
-#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val)
-#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR)
-#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val)
-#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN)
-#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val)
-#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER)
-#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val)
-#define bfin_read_PORTDIO() bfin_read16(PORTDIO)
-#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val)
-#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR)
-#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val)
-#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET)
-#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val)
-#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE)
-#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val)
-#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR)
-#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val)
-#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN)
-#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val)
-#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER)
-#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val)
-#define bfin_read_PORTEIO() bfin_read16(PORTEIO)
-#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val)
-#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR)
-#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val)
-#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET)
-#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val)
-#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE)
-#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val)
-#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR)
-#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val)
-#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN)
-#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
deleted file mode 100644
index acc15f3aba38..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF539_H
-#define _CDEF_BF539_H
-
-/* Include MMRs Common to BF538 */
-#include "cdefBF538.h"
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0)
-#define bfin_write_MXVR_PLL_CTL_0(val) bfin_write32(MXVR_PLL_CTL_0, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define bfin_read_MXVR_PLL_CTL_1() bfin_read32(MXVR_PLL_CTL_1)
-#define bfin_write_MXVR_PLL_CTL_1(val) bfin_write32(MXVR_PLL_CTL_1, val)
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-
-#endif /* _CDEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
deleted file mode 100644
index 876a77028001..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/defBF538.h
+++ /dev/null
@@ -1,1749 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF538_H
-#define _DEF_BF538_H
-
-/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR 0xFFC00104 /* System Configuration registe */
-#define SIC_RVECT 0xFFC00108
-#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
-#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
-#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
-#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT 0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
-#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR 0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR 0xFFC0040C /* Line Control Register */
-#define UART0_MCR 0xFFC00410 /* Modem Control Register */
-#define UART0_LSR 0xFFC00414 /* Line Status Register */
-#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL 0xFFC00424 /* Global Control Register */
-
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-
-#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define SPI0_REGBASE SPI0_CTL
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
-
-#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
-#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
-#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
-
-
-/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
-#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
-#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
-#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
-#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-
-
-/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
-
-#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
-
-#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
-
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
-#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
-#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
-#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-
-#define TWI0_REGBASE TWI0_CLKDIV
-
-/* the following are for backwards compatibility */
-#define TWI0_PRESCALE TWI0_CONTROL
-#define TWI0_INT_SRC TWI0_INT_STAT
-#define TWI0_INT_ENABLE TWI0_INT_MASK
-
-
-/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
-
-/* GPIO Port C Register Names */
-#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
-#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
-#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
-#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
-#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
-#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
-#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
-
-/* GPIO Port D Register Names */
-#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
-#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
-#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
-#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
-#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
-#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
-#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
-
-/* GPIO Port E Register Names */
-#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
-#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
-#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
-#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
-#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
-#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
-#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
-
-/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
-
-#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
-
-
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
-#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
-
-#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
-
-#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
-
-#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
-
-#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
-
-#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
-
-#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
-
-#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
-
-#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
-
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
-
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
-
-
-/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
-#define UART1_THR 0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR 0xFFC0200C /* Line Control Register */
-#define UART1_MCR 0xFFC02010 /* Modem Control Register */
-#define UART1_LSR 0xFFC02014 /* Line Status Register */
-#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL 0xFFC02024 /* Global Control Register */
-
-
-/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
-#define UART2_THR 0xFFC02100 /* Transmit Holding register */
-#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
-#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
-#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
-#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
-#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
-#define UART2_LCR 0xFFC0210C /* Line Control Register */
-#define UART2_MCR 0xFFC02110 /* Modem Control Register */
-#define UART2_LSR 0xFFC02114 /* Line Status Register */
-#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
-#define UART2_GCTL 0xFFC02124 /* Global Control Register */
-
-
-/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
-#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
-#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
-#define TWI1_REGBASE TWI1_CLKDIV
-
-
-/* the following are for backwards compatibility */
-#define TWI1_PRESCALE TWI1_CONTROL
-#define TWI1_INT_SRC TWI1_INT_STAT
-#define TWI1_INT_ENABLE TWI1_INT_MASK
-
-
-/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
-#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
-#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
-#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
-#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
-#define SPI1_REGBASE SPI1_CTL
-
-/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
-#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
-#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
-#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
-#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
-#define SPI2_REGBASE SPI2_CTL
-
-/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
-#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
-#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
-#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
-#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
-#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
-#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
-#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
-#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
-#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
-#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
-#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
-#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
-#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
-#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
-
-
-/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
-#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
-#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
-#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
-#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
-#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
-#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
-#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
-
-/* For Mailboxes 16-31 */
-#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
-#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
-#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
-#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
-#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
-#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
-#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
-#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
-
-#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
-#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
-
-#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
-/* the following is for backwards compatibility */
-#define CAN_CNF CAN_DEBUG
-
-#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
-#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
-#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
-#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
-#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
-#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
-#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
-#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
-#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
-#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
-#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
-#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */
-#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks */
-#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers */
-#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits and Macros */
-/******************************************************************************* */
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks */
-#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
-#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
-#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
-#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
-#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
-#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
-#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
-#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
-#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
-#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
-#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
-#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
-
-/* the following are for backwards compatibility */
-#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
-#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
-#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
-#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
-#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
-#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
-#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
-#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
-#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
-#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
-#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
-
-/* the following are for backwards compatibility */
-#define MDMA0_IRQ MDMA1_0_IRQ
-#define MDMA1_IRQ MDMA1_1_IRQ
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASKx Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWRx Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
-#endif /* _MISRA_RULES */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x0001 /* PPI Port Enable */
-#define PORT_DIR 0x0002 /* PPI Port Direction */
-#define XFR_TYPE 0x000C /* PPI Transfer Type */
-#define PORT_CFG 0x0030 /* PPI Port Configuration */
-#define FLD_SEL 0x0040 /* PPI Active Field Select */
-#define PACK_EN 0x0080 /* PPI Packing Mode */
-/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x3800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10 0x0800 /* Data Length = 10 Bits */
-#define DLEN_11 0x1000 /* Data Length = 11 Bits */
-#define DLEN_12 0x1800 /* Data Length = 12 Bits */
-#define DLEN_13 0x2000 /* Data Length = 13 Bits */
-#define DLEN_14 0x2800 /* Data Length = 14 Bits */
-#define DLEN_15 0x3000 /* Data Length = 15 Bits */
-#define DLEN_16 0x3800 /* Data Length = 16 Bits */
-#ifdef _MISRA_RULES
-#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL 0xC000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-
-/* PPI_STATUS Masks */
-#define FLD 0x0400 /* Field Indicator */
-#define FT_ERR 0x0800 /* Frame Track Error */
-#define OVR 0x1000 /* FIFO Overflow Error */
-#define UNDR 0x2000 /* FIFO Underrun Error */
-#define ERR_DET 0x4000 /* Error Detected Indicator */
-#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
-
-
-/* ********** DMA CONTROLLER MASKS ***********************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x0040 /* DMA Channel Type Indicator */
-#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
-#define PMAP 0xF000 /* DMA Peripheral Map Field */
-
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
-#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
-#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
-
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
-#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
-#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
-#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
-#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
-
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001 /* Enable Timer 0 */
-#define TIMEN1 0x0002 /* Enable Timer 1 */
-#define TIMEN2 0x0004 /* Enable Timer 2 */
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001 /* Disable Timer 0 */
-#define TIMDIS1 0x0002 /* Disable Timer 1 */
-#define TIMDIS2 0x0004 /* Disable Timer 2 */
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x0001 /* Timer 0 Interrupt */
-#define TIMIL1 0x0002 /* Timer 1 Interrupt */
-#define TIMIL2 0x0004 /* Timer 2 Interrupt */
-#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x) (((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x) (((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P 0x0000 /* Enable CLKOUT */
-#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE 0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
deleted file mode 100644
index 199e871634b4..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF539_H
-#define _DEF_BF539_H
-
-#include "defBF538.h"
-
-/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
-
-#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
-#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
-
-#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
-
-#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
-
-#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
-
-#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
-
-#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
-
-#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
-
-#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
-
-#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
-#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
-#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
-
-#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
-#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
-#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
-
-#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
-#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
-#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
-
-#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
-#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
-#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
-
-#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
-#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
-#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
-
-#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
-#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
-#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
-
-#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
-#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
-#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
-
-#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
-#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
-#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
-
-#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
-
-#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
-
-#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
-
-#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
-
-#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
-#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
-#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
-
-#endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/dma.h b/arch/blackfin/mach-bf538/include/mach/dma.h
deleted file mode 100644
index eb05cacbf4d3..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/dma.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_PPI 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT0_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT1_TX 4
-#define CH_SPI0 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_SPORT2_RX 8
-#define CH_SPORT2_TX 9
-#define CH_SPORT3_RX 10
-#define CH_SPORT3_TX 11
-#define CH_SPI1 14
-#define CH_SPI2 15
-#define CH_UART1_RX 16
-#define CH_UART1_TX 17
-#define CH_UART2_RX 18
-#define CH_UART2_TX 19
-
-#define CH_MEM_STREAM0_DEST 20
-#define CH_MEM_STREAM0_SRC 21
-#define CH_MEM_STREAM1_DEST 22
-#define CH_MEM_STREAM1_SRC 23
-#define CH_MEM_STREAM2_DEST 24
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM3_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-
-#define MAX_DMA_CHANNELS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
deleted file mode 100644
index 3561c7d8935b..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-#ifdef CONFIG_GPIOLIB
-/* We only use the special logic with GPIOLIB devices */
-#define BFIN_SPECIAL_GPIO_BANKS 3
-#endif
-
-#define GPIO_PF0 0 /* PF */
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PC0 16 /* PC */
-#define GPIO_PC1 17
-#define GPIO_PC4 20
-#define GPIO_PC5 21
-#define GPIO_PC6 22
-#define GPIO_PC7 23
-#define GPIO_PC8 24
-#define GPIO_PC9 25
-#define GPIO_PD0 32 /* PD */
-#define GPIO_PD1 33
-#define GPIO_PD2 34
-#define GPIO_PD3 35
-#define GPIO_PD4 36
-#define GPIO_PD5 37
-#define GPIO_PD6 38
-#define GPIO_PD7 39
-#define GPIO_PD8 40
-#define GPIO_PD9 41
-#define GPIO_PD10 42
-#define GPIO_PD11 43
-#define GPIO_PD12 44
-#define GPIO_PD13 45
-#define GPIO_PE0 48 /* PE */
-#define GPIO_PE1 49
-#define GPIO_PE2 50
-#define GPIO_PE3 51
-#define GPIO_PE4 52
-#define GPIO_PE5 53
-#define GPIO_PE6 54
-#define GPIO_PE7 55
-#define GPIO_PE8 56
-#define GPIO_PE9 57
-#define GPIO_PE10 58
-#define GPIO_PE11 59
-#define GPIO_PE12 60
-#define GPIO_PE13 61
-#define GPIO_PE14 62
-#define GPIO_PE15 63
-
-#define PORT_F GPIO_PF0
-#define PORT_C GPIO_PC0
-#define PORT_D GPIO_PD0
-#define PORT_E GPIO_PE0
-
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
deleted file mode 100644
index 07ca069d37cd..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF538_IRQ_H_
-#define _BF538_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
-#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC */
-#define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
-#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
-#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
-#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
-#define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
-#define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
-#define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
-#define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
-#define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
-#define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
-#define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
-#define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
-#define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
-#define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
-#define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
-#define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
-#define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
-#define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
-#define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
-
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_PPI_ERROR_POS 8
-#define IRQ_SPORT0_ERROR_POS 12
-#define IRQ_SPORT1_ERROR_POS 16
-#define IRQ_SPI0_ERROR_POS 20
-#define IRQ_UART0_ERROR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_PPI_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER0_POS 0
-#define IRQ_TIMER1_POS 4
-#define IRQ_TIMER2_POS 8
-#define IRQ_PORTF_INTA_POS 12
-#define IRQ_PORTF_INTB_POS 16
-#define IRQ_MEM0_DMA0_POS 20
-#define IRQ_MEM0_DMA1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA1_ERROR_POS 0
-#define IRQ_SPORT2_ERROR_POS 4
-#define IRQ_SPORT3_ERROR_POS 8
-#define IRQ_SPI1_ERROR_POS 16
-#define IRQ_SPI2_ERROR_POS 20
-#define IRQ_UART1_ERROR_POS 24
-#define IRQ_UART2_ERROR_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_CAN_ERROR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_UART2_RX_POS 12
-#define IRQ_UART2_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MEM1_DMA0_POS 4
-#define IRQ_MEM1_DMA1_POS 8
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/mem_map.h b/arch/blackfin/mach-bf538/include/mach/mem_map.h
deleted file mode 100644
index aff00f453e9e..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/mem_map.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * BF538 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF538/9 processors */
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/portmux.h b/arch/blackfin/mach-bf538/include/mach/portmux.h
deleted file mode 100644
index b773c5fdbc72..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/portmux.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES 64
-
-#define P_TMR2 (P_DONTCARE)
-#define P_TMR1 (P_DONTCARE)
-#define P_TMR0 (P_DONTCARE)
-#define P_TMRCLK (P_DONTCARE)
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-#define P_SPORT1_TSCLK (P_DONTCARE)
-#define P_SPORT1_RSCLK (P_DONTCARE)
-#define P_SPORT0_TSCLK (P_DONTCARE)
-#define P_SPORT0_RSCLK (P_DONTCARE)
-#define P_SPORT1_DRSEC (P_DONTCARE)
-#define P_SPORT1_RFS (P_DONTCARE)
-#define P_SPORT1_DTPRI (P_DONTCARE)
-#define P_SPORT1_DTSEC (P_DONTCARE)
-#define P_SPORT1_TFS (P_DONTCARE)
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DONTCARE)
-#define P_SPORT0_RFS (P_DONTCARE)
-#define P_SPORT0_DTPRI (P_DONTCARE)
-#define P_SPORT0_DTSEC (P_DONTCARE)
-#define P_SPORT0_TFS (P_DONTCARE)
-#define P_SPORT0_DRPRI (P_DONTCARE)
-
-#define P_UART0_RX (P_DONTCARE)
-#define P_UART0_TX (P_DONTCARE)
-
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1))
-
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10))
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13))
-
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4))
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15))
-
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
-
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf538/ints-priority.c b/arch/blackfin/mach-bf538/ints-priority.c
deleted file mode 100644
index 1fa793ced347..000000000000
--- a/arch/blackfin/mach-bf538/ints-priority.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
-
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
- ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
- ((CONFIG_IRQ_SPI0_ERROR - 7) << IRQ_SPI0_ERROR_POS) |
- ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
- ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
- ((CONFIG_IRQ_MEM0_DMA0 - 7) << IRQ_MEM0_DMA0_POS) |
- ((CONFIG_IRQ_MEM0_DMA1 - 7) << IRQ_MEM0_DMA1_POS) |
- ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_ERROR - 7) << IRQ_SPORT2_ERROR_POS) |
- ((CONFIG_IRQ_SPORT3_ERROR - 7) << IRQ_SPORT3_ERROR_POS) |
- ((CONFIG_IRQ_SPI1_ERROR - 7) << IRQ_SPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPI2_ERROR - 7) << IRQ_SPI2_ERROR_POS) |
- ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
- ((CONFIG_IRQ_UART2_ERROR - 7) << IRQ_UART2_ERROR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN_ERROR - 7) << IRQ_CAN_ERROR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_UART2_RX - 7) << IRQ_UART2_RX_POS) |
- ((CONFIG_IRQ_UART2_TX - 7) << IRQ_UART2_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
- ((CONFIG_IRQ_MEM1_DMA0 - 7) << IRQ_MEM1_DMA0_POS) |
- ((CONFIG_IRQ_MEM1_DMA1 - 7) << IRQ_MEM1_DMA1_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
deleted file mode 100644
index 71c2a765af1d..000000000000
--- a/arch/blackfin/mach-bf548/Kconfig
+++ /dev/null
@@ -1,383 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF542
- def_bool y
- depends on BF542_std || BF542M
-config BF544
- def_bool y
- depends on BF544_std || BF544M
-config BF547
- def_bool y
- depends on BF547_std || BF547M
-config BF548
- def_bool y
- depends on BF548_std || BF548M
-config BF549
- def_bool y
- depends on BF549_std || BF549M
-
-config BF54xM
- def_bool y
- depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
-
-config BF54x
- def_bool y
- depends on (BF542 || BF544 || BF547 || BF548 || BF549)
-
-if (BF54x)
-
-source "arch/blackfin/mach-bf548/boards/Kconfig"
-
-menu "BF548 Specific Configuration"
-
-config DEB_DMA_URGENT
- bool "DMA has priority over core for ext. accesses"
- depends on BF54x
- default y
- help
- Treat any DEB1, DEB2 and DEB3 request as Urgent
-
-config BF548_ATAPI_ALTERNATIVE_PORT
- bool "BF548 ATAPI alternative port via GPIO"
- help
- BF548 ATAPI data and address PINs can be routed through
- async address or GPIO port F and G. Select y to route it
- to GPIO.
-
-choice
- prompt "UART2 DMA channel selection"
- depends on SERIAL_BFIN_UART2
- default UART2_DMA_RX_ON_DMA18
- help
- UART2 DMA channel selection
- RX -> DMA18
- TX -> DMA19
- or
- RX -> DMA13
- TX -> DMA14
-
-config UART2_DMA_RX_ON_DMA18
- bool "UART2 DMA RX -> DMA18 TX -> DMA19"
- help
- UART2 DMA channel assignment
- RX -> DMA18
- TX -> DMA19
- use SPORT2 default DMA channel
-
-config UART2_DMA_RX_ON_DMA13
- bool "UART2 DMA RX -> DMA13 TX -> DMA14"
- help
- UART2 DMA channel assignment
- RX -> DMA13
- TX -> DMA14
- use EPPI1 EPPI2 default DMA channel
-endchoice
-
-choice
- prompt "UART3 DMA channel selection"
- depends on SERIAL_BFIN_UART3
- default UART3_DMA_RX_ON_DMA20
- help
- UART3 DMA channel selection
- RX -> DMA20
- TX -> DMA21
- or
- RX -> DMA15
- TX -> DMA16
-
-config UART3_DMA_RX_ON_DMA20
- bool "UART3 DMA RX -> DMA20 TX -> DMA21"
- help
- UART3 DMA channel assignment
- RX -> DMA20
- TX -> DMA21
- use SPORT3 default DMA channel
-
-config UART3_DMA_RX_ON_DMA15
- bool "UART3 DMA RX -> DMA15 TX -> DMA16"
- help
- UART3 DMA channel assignment
- RX -> DMA15
- TX -> DMA16
- use PIXC default DMA channel
-
-endchoice
-
-comment "Interrupt Priority Assignment"
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "IRQ_PLL_WAKEUP"
- default 7
-config IRQ_DMAC0_ERR
- int "IRQ_DMAC0_ERR"
- default 7
-config IRQ_EPPI0_ERR
- int "IRQ_EPPI0_ERR"
- default 7
-config IRQ_SPORT0_ERR
- int "IRQ_SPORT0_ERR"
- default 7
-config IRQ_SPORT1_ERR
- int "IRQ_SPORT1_ERR"
- default 7
-config IRQ_SPI0_ERR
- int "IRQ_SPI0_ERR"
- default 7
-config IRQ_UART0_ERR
- int "IRQ_UART0_ERR"
- default 7
-config IRQ_RTC
- int "IRQ_RTC"
- default 8
-config IRQ_EPPI0
- int "IRQ_EPPI0"
- default 8
-config IRQ_SPORT0_RX
- int "IRQ_SPORT0_RX"
- default 9
-config IRQ_SPORT0_TX
- int "IRQ_SPORT0_TX"
- default 9
-config IRQ_SPORT1_RX
- int "IRQ_SPORT1_RX"
- default 9
-config IRQ_SPORT1_TX
- int "IRQ_SPORT1_TX"
- default 9
-config IRQ_SPI0
- int "IRQ_SPI0"
- default 10
-config IRQ_UART0_RX
- int "IRQ_UART0_RX"
- default 10
-config IRQ_UART0_TX
- int "IRQ_UART0_TX"
- default 10
-config IRQ_TIMER8
- int "IRQ_TIMER8"
- default 11
-config IRQ_TIMER9
- int "IRQ_TIMER9"
- default 11
-config IRQ_TIMER10
- int "IRQ_TIMER10"
- default 11
-config IRQ_PINT0
- int "IRQ_PINT0"
- default 12
-config IRQ_PINT1
- int "IRQ_PINT0"
- default 12
-config IRQ_MDMAS0
- int "IRQ_MDMAS0"
- default 13
-config IRQ_MDMAS1
- int "IRQ_DMDMAS1"
- default 13
-config IRQ_WATCHDOG
- int "IRQ_WATCHDOG"
- default 13
-config IRQ_DMAC1_ERR
- int "IRQ_DMAC1_ERR"
- default 7
-config IRQ_SPORT2_ERR
- int "IRQ_SPORT2_ERR"
- default 7
-config IRQ_SPORT3_ERR
- int "IRQ_SPORT3_ERR"
- default 7
-config IRQ_MXVR_DATA
- int "IRQ MXVR Data"
- default 7
-config IRQ_SPI1_ERR
- int "IRQ_SPI1_ERR"
- default 7
-config IRQ_SPI2_ERR
- int "IRQ_SPI2_ERR"
- default 7
-config IRQ_UART1_ERR
- int "IRQ_UART1_ERR"
- default 7
-config IRQ_UART2_ERR
- int "IRQ_UART2_ERR"
- default 7
-config IRQ_CAN0_ERR
- int "IRQ_CAN0_ERR"
- default 7
-config IRQ_SPORT2_RX
- int "IRQ_SPORT2_RX"
- default 9
-config IRQ_SPORT2_TX
- int "IRQ_SPORT2_TX"
- default 9
-config IRQ_SPORT3_RX
- int "IRQ_SPORT3_RX"
- default 9
-config IRQ_SPORT3_TX
- int "IRQ_SPORT3_TX"
- default 9
-config IRQ_EPPI1
- int "IRQ_EPPI1"
- default 9
-config IRQ_EPPI2
- int "IRQ_EPPI2"
- default 9
-config IRQ_SPI1
- int "IRQ_SPI1"
- default 10
-config IRQ_SPI2
- int "IRQ_SPI2"
- default 10
-config IRQ_UART1_RX
- int "IRQ_UART1_RX"
- default 10
-config IRQ_UART1_TX
- int "IRQ_UART1_TX"
- default 10
-config IRQ_ATAPI_RX
- int "IRQ_ATAPI_RX"
- default 10
-config IRQ_ATAPI_TX
- int "IRQ_ATAPI_TX"
- default 10
-config IRQ_TWI0
- int "IRQ_TWI0"
- default 11
-config IRQ_TWI1
- int "IRQ_TWI1"
- default 11
-config IRQ_CAN0_RX
- int "IRQ_CAN_RX"
- default 11
-config IRQ_CAN0_TX
- int "IRQ_CAN_TX"
- default 11
-config IRQ_MDMAS2
- int "IRQ_MDMAS2"
- default 13
-config IRQ_MDMAS3
- int "IRQ_DMMAS3"
- default 13
-config IRQ_MXVR_ERR
- int "IRQ_MXVR_ERR"
- default 11
-config IRQ_MXVR_MSG
- int "IRQ_MXVR_MSG"
- default 11
-config IRQ_MXVR_PKT
- int "IRQ_MXVR_PKT"
- default 11
-config IRQ_EPPI1_ERR
- int "IRQ_EPPI1_ERR"
- default 7
-config IRQ_EPPI2_ERR
- int "IRQ_EPPI2_ERR"
- default 7
-config IRQ_UART3_ERR
- int "IRQ_UART3_ERR"
- default 7
-config IRQ_HOST_ERR
- int "IRQ_HOST_ERR"
- default 7
-config IRQ_PIXC_ERR
- int "IRQ_PIXC_ERR"
- default 7
-config IRQ_NFC_ERR
- int "IRQ_NFC_ERR"
- default 7
-config IRQ_ATAPI_ERR
- int "IRQ_ATAPI_ERR"
- default 7
-config IRQ_CAN1_ERR
- int "IRQ_CAN1_ERR"
- default 7
-config IRQ_HS_DMA_ERR
- int "IRQ Handshake DMA Status"
- default 7
-config IRQ_PIXC_IN0
- int "IRQ PIXC IN0"
- default 8
-config IRQ_PIXC_IN1
- int "IRQ PIXC IN1"
- default 8
-config IRQ_PIXC_OUT
- int "IRQ PIXC OUT"
- default 8
-config IRQ_SDH
- int "IRQ SDH"
- default 8
-config IRQ_CNT
- int "IRQ CNT"
- default 8
-config IRQ_KEY
- int "IRQ KEY"
- default 8
-config IRQ_CAN1_RX
- int "IRQ CAN1 RX"
- default 11
-config IRQ_CAN1_TX
- int "IRQ_CAN1_TX"
- default 11
-config IRQ_SDH_MASK0
- int "IRQ_SDH_MASK0"
- default 11
-config IRQ_SDH_MASK1
- int "IRQ_SDH_MASK1"
- default 11
-config IRQ_USB_INT0
- int "IRQ USB INT0"
- default 11
-config IRQ_USB_INT1
- int "IRQ USB INT1"
- default 11
-config IRQ_USB_INT2
- int "IRQ USB INT2"
- default 11
-config IRQ_USB_DMA
- int "IRQ USB DMA"
- default 11
-config IRQ_OTPSEC
- int "IRQ OPTSEC"
- default 11
-config IRQ_TIMER0
- int "IRQ_TIMER0"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "IRQ_TIMER1"
- default 11
-config IRQ_TIMER2
- int "IRQ_TIMER2"
- default 11
-config IRQ_TIMER3
- int "IRQ_TIMER3"
- default 11
-config IRQ_TIMER4
- int "IRQ_TIMER4"
- default 11
-config IRQ_TIMER5
- int "IRQ_TIMER5"
- default 11
-config IRQ_TIMER6
- int "IRQ_TIMER6"
- default 11
-config IRQ_TIMER7
- int "IRQ_TIMER7"
- default 11
-config IRQ_PINT2
- int "IRQ_PIN2"
- default 11
-config IRQ_PINT3
- int "IRQ_PIN3"
- default 11
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
deleted file mode 100644
index 56994b675f9c..000000000000
--- a/arch/blackfin/mach-bf548/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf537/Makefile
-#
-
-obj-y := ints-priority.o dma.o
diff --git a/arch/blackfin/mach-bf548/boards/Kconfig b/arch/blackfin/mach-bf548/boards/Kconfig
deleted file mode 100644
index e8ce579ae8f0..000000000000
--- a/arch/blackfin/mach-bf548/boards/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN548_EZKIT
- help
- Select your board!
-
-config BFIN548_EZKIT
- bool "BF548-EZKIT"
- help
- BFIN548-EZKIT board support.
-
-config BFIN548_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF548"
- depends on (BF548)
- help
- CM-BF548 support for DEV-Board.
-
-endchoice
diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile
deleted file mode 100644
index 319ef54c4221..000000000000
--- a/arch/blackfin/mach-bf548/boards/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# arch/blackfin/mach-bf548/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN548_BLUETECHNIX_CM) += cm_bf548.o
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
deleted file mode 100644
index 120c9941c242..000000000000
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ /dev/null
@@ -1,1268 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <asm/dpmc.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM-BF548";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 480,
- .height = 272,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE6,
- .end = IRQ_PE6,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PH6,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "linux kernel(nand)",
- .offset = 0,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = 4 * 1024 * 1024,
- .size = (256 - 4) * 1024 * 1024,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-static unsigned short bfin_can_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can_device = {
- .name = "bfin_can",
- .num_resources = ARRAY_SIZE(bfin_can_resources),
- .resource = bfin_can_resources,
- .dev = {
- .platform_data = &bfin_can_peripherals, /* Passed to driver */
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &para_flash_data,
- },
- .num_resources = 1,
- .resource = &para_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x1c0000,
- .offset = 0x40000
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-static struct spi_board_info bf54x_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-{
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PJ11,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 2,
-},
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = 4,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf548_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &para_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can_device,
-#endif
-
-};
-
-static int __init cm_bf548_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bf54x_spi_board_info,
- ARRAY_SIZE(bf54x_spi_board_info));
-#endif
-
- return 0;
-}
-
-arch_initcall(cm_bf548_init);
-
-static struct platform_device *cm_bf548_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf548_early_devices,
- ARRAY_SIZE(cm_bf548_early_devices));
-}
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
deleted file mode 100644
index 3cdd4835a9f7..000000000000
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ /dev/null
@@ -1,2199 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/gpio.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/bfin_sport.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <mach/bf54x_keys.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF548-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
-
-#include <mach/bf54x-lq043.h>
-
-static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
- .width = 95,
- .height = 54,
- .xres = {480, 480, 480},
- .yres = {272, 272, 272},
- .bpp = {24, 24, 24},
- .disp = GPIO_PE3,
-};
-
-static struct resource bf54x_lq043_resources[] = {
- {
- .start = IRQ_EPPI0_ERR,
- .end = IRQ_EPPI0_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_lq043_device = {
- .name = "bf54x-lq043",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
- .resource = bf54x_lq043_resources,
- .dev = {
- .platform_data = &bf54x_lq043_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
-static const unsigned int bf548_keymap[] = {
- KEYVAL(0, 0, KEY_ENTER),
- KEYVAL(0, 1, KEY_HELP),
- KEYVAL(0, 2, KEY_0),
- KEYVAL(0, 3, KEY_BACKSPACE),
- KEYVAL(1, 0, KEY_TAB),
- KEYVAL(1, 1, KEY_9),
- KEYVAL(1, 2, KEY_8),
- KEYVAL(1, 3, KEY_7),
- KEYVAL(2, 0, KEY_DOWN),
- KEYVAL(2, 1, KEY_6),
- KEYVAL(2, 2, KEY_5),
- KEYVAL(2, 3, KEY_4),
- KEYVAL(3, 0, KEY_UP),
- KEYVAL(3, 1, KEY_3),
- KEYVAL(3, 2, KEY_2),
- KEYVAL(3, 3, KEY_1),
-};
-
-static struct bfin_kpad_platform_data bf54x_kpad_data = {
- .rows = 4,
- .cols = 4,
- .keymap = bf548_keymap,
- .keymapsize = ARRAY_SIZE(bf548_keymap),
- .repeat = 0,
- .debounce_time = 5000, /* ns (5ms) */
- .coldrive_time = 1000, /* ns (1ms) */
- .keyup_test_interval = 50, /* ms (50ms) */
-};
-
-static struct resource bf54x_kpad_resources[] = {
- {
- .start = IRQ_KEY,
- .end = IRQ_KEY,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf54x_kpad_device = {
- .name = "bf54x-keys",
- .id = -1,
- .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
- .resource = bf54x_kpad_resources,
- .dev = {
- .platform_data = &bf54x_kpad_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
- .pm_wakeup = 1,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_DLL,
- .end = UART0_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTE_FER,
- .end = PORTE_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_ERROR,
- .end = IRQ_UART0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_DLL,
- .end = UART1_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTH_FER,
- .end = PORTH_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_ERROR,
- .end = IRQ_UART1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PE10,
- .end = GPIO_PE10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PE9,
- .end = GPIO_PE9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-static struct resource bfin_uart2_resources[] = {
- {
- .start = UART2_DLL,
- .end = UART2_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART2_TX,
- .end = IRQ_UART2_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART2_ERROR,
- .end = IRQ_UART2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_TX,
- .end = CH_UART2_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart2_peripherals[] = {
- P_UART2_TX, P_UART2_RX, 0
-};
-
-static struct platform_device bfin_uart2_device = {
- .name = "bfin-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_uart2_resources),
- .resource = bfin_uart2_resources,
- .dev = {
- .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-static struct resource bfin_uart3_resources[] = {
- {
- .start = UART3_DLL,
- .end = UART3_RBR+2,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTB_FER,
- .end = PORTB_FER+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART3_TX,
- .end = IRQ_UART3_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART3_ERROR,
- .end = IRQ_UART3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_TX,
- .end = CH_UART3_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PB3,
- .end = GPIO_PB3,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PB2,
- .end = GPIO_PB2,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart3_peripherals[] = {
- P_UART3_TX, P_UART3_RX,
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- P_UART3_RTS, P_UART3_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart3_device = {
- .name = "bfin-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_uart3_resources),
- .resource = bfin_uart3_resources,
- .dev = {
- .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR2
-static struct resource bfin_sir2_resources[] = {
- {
- .start = 0xFFC02100,
- .end = 0xFFC021FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART2_RX,
- .end = IRQ_UART2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART2_RX,
- .end = CH_UART2_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir2_device = {
- .name = "bfin_sir",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sir2_resources),
- .resource = bfin_sir2_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR3
-static struct resource bfin_sir3_resources[] = {
- {
- .start = 0xFFC03100,
- .end = 0xFFC031FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART3_RX,
- .end = IRQ_UART3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART3_RX,
- .end = CH_UART3_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir3_device = {
- .name = "bfin_sir",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sir3_resources),
- .resource = bfin_sir3_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24000000,
- .end = 0x24000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE8,
- .end = IRQ_PE8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFC03C00,
- .end = 0xFFC040FF,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_INT0,
- .end = IRQ_USB_INT0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 0,
- .dyn_fifo = 0,
- .soft_con = 1,
- .dma = 1,
- .num_eps = 8,
- .dma_channels = 8,
- .gpio_vrsel = GPIO_PE7,
- /* Some custom boards need to be active low, just set it to "0"
- * if it is the case.
- */
- .gpio_vrsel_active = 1,
- .clkin = 24, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
-static struct resource bfin_sport3_uart_resources[] = {
- {
- .start = SPORT3_TCR1,
- .end = SPORT3_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT3_RX,
- .end = IRQ_SPORT3_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT3_ERROR,
- .end = IRQ_SPORT3_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport3_peripherals[] = {
- P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
- P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
-};
-
-static struct platform_device bfin_sport3_uart_device = {
- .name = "bfin-sport-uart",
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
- .resource = bfin_sport3_uart_resources,
- .dev = {
- .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC02A00,
- .end = 0xFFC02FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_ERROR,
- .end = IRQ_CAN0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-static unsigned short bfin_can1_peripherals[] = {
- P_CAN1_RX, P_CAN1_TX, 0
-};
-
-static struct resource bfin_can1_resources[] = {
- {
- .start = 0xFFC03200,
- .end = 0xFFC037FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN1_RX,
- .end = IRQ_CAN1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_TX,
- .end = IRQ_CAN1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN1_ERROR,
- .end = IRQ_CAN1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can1_device = {
- .name = "bfin_can",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_can1_resources),
- .resource = bfin_can1_resources,
- .dev = {
- .platform_data = &bfin_can1_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
-static struct resource bfin_atapi_resources[] = {
- {
- .start = 0xFFC03800,
- .end = 0xFFC0386F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_ATAPI_ERR,
- .end = IRQ_ATAPI_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_atapi_device = {
- .name = "pata-bf54x",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_atapi_resources),
- .resource = bfin_atapi_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bf5xx_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bf5xx_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bf5xx_nand_device = {
- .name = "bf5xx-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
- .resource = bf5xx_nand_resources,
- .dev = {
- .platform_data = &bf5xx_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_SDH,
- .irq_int0 = IRQ_SDH_MASK0,
- .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
-};
-
-static struct platform_device bf54x_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x8000 * 3,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x8000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x21ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (m25p16) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p16",
-};
-
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_gpio_base = GPIO_PA0, /* Optional */
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_gpio_base = GPIO_PB0,
- .port_pin_base = GPIO_PB0,
- .port_width = 15,
- .pint_id = 0,
- .pint_assign = true,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_gpio_base = GPIO_PC0,
- .port_pin_base = GPIO_PC0,
- .port_width = 14,
- .pint_id = 2,
- .pint_assign = true,
- .pint_map = 0,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_gpio_base = GPIO_PD0,
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_gpio_base = GPIO_PE0,
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = true,
- .pint_map = 2,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_gpio_base = GPIO_PF0,
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 3,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_gpio_base = GPIO_PG0,
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gph_resources[] = {
- {
- .start = PORTH_FER,
- .end = PORTH_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PH0,
- .end = IRQ_PH0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = {
- .port_gpio_base = GPIO_PH0,
- .port_pin_base = GPIO_PH0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gph_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 7,
- .num_resources = ARRAY_SIZE(bfin_gph_resources),
- .resource = bfin_gph_resources,
- .dev = {
- .platform_data = &bfin_gph_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpi_resources[] = {
- {
- .start = PORTI_FER,
- .end = PORTI_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PI0,
- .end = IRQ_PI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = {
- .port_gpio_base = GPIO_PI0,
- .port_pin_base = GPIO_PI0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpi_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 8,
- .num_resources = ARRAY_SIZE(bfin_gpi_resources),
- .resource = bfin_gpi_resources,
- .dev = {
- .platform_data = &bfin_gpi_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpj_resources[] = {
- {
- .start = PORTJ_FER,
- .end = PORTJ_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PJ0,
- .end = IRQ_PJ0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = {
- .port_gpio_base = GPIO_PJ0,
- .port_pin_base = GPIO_PJ0,
- .port_width = 14,
- .pint_id = -1,
-};
-
-static struct platform_device bfin_gpj_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 9,
- .num_resources = ARRAY_SIZE(bfin_gpj_resources),
- .resource = bfin_gpj_resources,
- .dev = {
- .platform_data = &bfin_gpj_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI0,
- .end = CH_SPI0,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI0,
- .end = IRQ_SPI0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- [0] = {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI1,
- .end = CH_SPI1,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI1,
- .end = IRQ_SPI1,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master0 = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf54x_spi_master1 = {
- .name = "bfin-spi",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
- P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
- P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI,
- .dma_ch = CH_EPPI1,
- .irq_err = IRQ_EPPI1_ERROR,
- .base = (void __iomem *)EPPI1_STATUS,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PG6;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF548",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20),
- .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */
- .blank_clocks = 8, /* 8 clocks as SAV and EAV */
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_REGBASE,
- .end = TWI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_REGBASE,
- .end = TWI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-};
-
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("pcf8574_lcd", 0x22),
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_PCF8574)
- {
- I2C_BOARD_INFO("pcf8574_keypad", 0x27),
- .irq = 212,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_BFIN_TWI_LCD)
- {
- I2C_BOARD_INFO("ad5252", 0x2f),
- },
-#endif
-};
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \
- IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-
-#define SPORT_REQ(x) \
- [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
- P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
-
-static const u16 bfin_snd_pin[][7] = {
- SPORT_REQ(0),
- SPORT_REQ(1),
- SPORT_REQ(2),
- SPORT_REQ(3),
-};
-
-static struct bfin_snd_platform_data bfin_snd_data[] = {
- {
- .pin_req = &bfin_snd_pin[0][0],
- },
- {
- .pin_req = &bfin_snd_pin[1][0],
- },
- {
- .pin_req = &bfin_snd_pin[2][0],
- },
- {
- .pin_req = &bfin_snd_pin[3][0],
- },
-};
-
-#define BFIN_SND_RES(x) \
- [x] = { \
- { \
- .start = SPORT##x##_TCR1, \
- .end = SPORT##x##_TCR1, \
- .flags = IORESOURCE_MEM \
- }, \
- { \
- .start = CH_SPORT##x##_RX, \
- .end = CH_SPORT##x##_RX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = CH_SPORT##x##_TX, \
- .end = CH_SPORT##x##_TX, \
- .flags = IORESOURCE_DMA, \
- }, \
- { \
- .start = IRQ_SPORT##x##_ERROR, \
- .end = IRQ_SPORT##x##_ERROR, \
- .flags = IORESOURCE_IRQ, \
- } \
- }
-
-static struct resource bfin_snd_resources[][4] = {
- BFIN_SND_RES(0),
- BFIN_SND_RES(1),
- BFIN_SND_RES(2),
- BFIN_SND_RES(3),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97_pcm = {
- .name = "bfin-ac97-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311)
-static struct platform_device bfin_ad73311_codec_device = {
- .name = "ad73311",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
-static struct platform_device bfin_ad1980_codec_device = {
- .name = "ad1980",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
- .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
- .dev = {
- .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
- &bfin_gph_device,
- &bfin_gpi_device,
- &bfin_gpj_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#ifdef CONFIG_BFIN_SIR2
- &bfin_sir2_device,
-#endif
-#ifdef CONFIG_BFIN_SIR3
- &bfin_sir3_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_FB_BF54X_LQ043)
- &bf54x_lq043_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
- &bfin_sport3_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
- &bfin_can1_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_BF54X)
- &bfin_atapi_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bf5xx_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bf54x_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bf54x_spi_master0,
- &bf54x_spi_master1,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_BFIN)
- &bf54x_kpad_device,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97_pcm,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980)
- &bfin_ad1980_codec_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"),
-#ifdef CONFIG_BFIN_UART3_CTSRTS
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"),
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"),
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
- PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"),
-#endif
- PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "4bit", "pinctrl-adi2.0", "keys_4x4grp", "keys"),
- PIN_MAP_MUX_GROUP("bf54x-keys", "8bit", "pinctrl-adi2.0", "keys_8x8grp", "keys"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
-#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-#endif
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
- &bfin_uart2_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
- &bfin_uart3_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
deleted file mode 100644
index 69ead33cbf91..000000000000
--- a/arch/blackfin/mach-bf548/dma.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) DMA21_NEXT_DESC_PTR,
- (struct dma_register *) DMA22_NEXT_DESC_PTR,
- (struct dma_register *) DMA23_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI0:
- ret_irq = IRQ_SPI0;
- break;
- case CH_SPI1:
- ret_irq = IRQ_SPI1;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0:
- ret_irq = IRQ_EPPI0;
- break;
- case CH_EPPI1:
- ret_irq = IRQ_EPPI1;
- break;
- case CH_EPPI2:
- ret_irq = IRQ_EPPI2;
- break;
- case CH_PIXC_IMAGE:
- ret_irq = IRQ_PIXC_IN0;
- break;
- case CH_PIXC_OVERLAY:
- ret_irq = IRQ_PIXC_IN1;
- break;
- case CH_PIXC_OUTPUT:
- ret_irq = IRQ_PIXC_OUT;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPORT3_RX:
- ret_irq = IRQ_SPORT3_RX;
- break;
- case CH_SPORT3_TX:
- ret_irq = IRQ_SPORT3_TX;
- break;
- case CH_SDH:
- ret_irq = IRQ_SDH;
- break;
- case CH_SPI2:
- ret_irq = IRQ_SPI2;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
deleted file mode 100644
index 098fad63e03b..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.0 or 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF548 silicon version 0.0, or 0.1
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* FIFO Boot Mode Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-/*
- * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
- * shows that the fix itself does not cover all cases.
- */
-#define ANOMALY_05000353 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
-/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
-#define ANOMALY_05000379 (1)
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
-#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
-/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
-#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
-#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
-#define ANOMALY_05000446 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
-#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
-/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
-#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
-/* USB DMA RX Data Corruption */
-#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
-/* USB TX DMA Hang */
-#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
-#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
-#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
-#define ANOMALY_05000500 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
-#define ANOMALY_05000502 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0x5411
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
-/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
-#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
-/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
-#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
-/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
-#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
-/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
-#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
-/* Changed Meaning of BCODE Field in SYSCR Register */
-#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
-/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
-#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000254 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bf548.h b/arch/blackfin/mach-bf548/include/mach/bf548.h
deleted file mode 100644
index 751e5e11ecf8..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bf548.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF548_H__
-#define __MACH_BF548_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF542)
-# define CPU "BF542"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF544)
-# define CPU "BF544"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF547)
-# define CPU "BF547"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF548)
-# define CPU "BF548"
-# define CPUID 0x27de
-#elif defined(CONFIG_BF549)
-# define CPU "BF549"
-# define CPUID 0x27de
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF48_H__ */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h b/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
deleted file mode 100644
index 8821efe57fbc..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bf54x-lq043.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef BF54X_LQ043_H
-#define BF54X_LQ043_H
-
-struct bfin_bf54xfb_val {
- unsigned int defval;
- unsigned int min;
- unsigned int max;
-};
-
-struct bfin_bf54xfb_mach_info {
- unsigned char fixed_syncs; /* do not update sync/border */
-
- /* LCD types */
- int type;
-
- /* Screen size */
- int width;
- int height;
-
- /* Screen info */
- struct bfin_bf54xfb_val xres;
- struct bfin_bf54xfb_val yres;
- struct bfin_bf54xfb_val bpp;
-
- /* GPIOs */
- unsigned short disp;
-
-};
-
-#endif /* BF54X_LQ043_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h b/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
deleted file mode 100644
index 49338ae299ab..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bf54x_keys.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BFIN_KPAD_H
-#define _BFIN_KPAD_H
-
-struct bfin_kpad_platform_data {
- int rows;
- int cols;
- const unsigned int *keymap;
- unsigned short keymapsize;
- unsigned short repeat;
- u32 debounce_time; /* in ns */
- u32 coldrive_time; /* in ns */
- u32 keyup_test_interval; /* in ms */
-};
-
-#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
deleted file mode 100644
index a77109f99720..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 4
-
-#define BFIN_UART_BF54X_STYLE
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
deleted file mode 100644
index 72da721a77f5..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf548.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF542
-# include "defBF542.h"
-#endif
-#ifdef CONFIG_BF544
-# include "defBF544.h"
-#endif
-#ifdef CONFIG_BF547
-# include "defBF547.h"
-#endif
-#ifdef CONFIG_BF548
-# include "defBF548.h"
-#endif
-#ifdef CONFIG_BF549
-# include "defBF549.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF542
-# include "cdefBF542.h"
-# endif
-# ifdef CONFIG_BF544
-# include "cdefBF544.h"
-# endif
-# ifdef CONFIG_BF547
-# include "cdefBF547.h"
-# endif
-# ifdef CONFIG_BF548
-# include "cdefBF548.h"
-# endif
-# ifdef CONFIG_BF549
-# include "cdefBF549.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
deleted file mode 100644
index 916347901d5a..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF542_H
-#define _CDEF_BF542_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-#endif /* _CDEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
deleted file mode 100644
index 33ec8102ceda..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
+++ /dev/null
@@ -1,913 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF544_H
-#define _CDEF_BF544_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
deleted file mode 100644
index be83f645bba8..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ /dev/null
@@ -1,796 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF547_H
-#define _CDEF_BF547_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2 Registers */
-
-#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
deleted file mode 100644
index bae67a65633e..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ /dev/null
@@ -1,761 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "cdefBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
-
-#endif /* _CDEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
deleted file mode 100644
index 002136ad5a44..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF549_H
-#define _CDEF_BF549_H
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "cdefBF547.h"
-
-/* MXVR Registers */
-
-#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
-
-/* MXVR Allocation Table Registers */
-
-#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
-
-/* MXVR Channel Assign Registers */
-
-#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-
-/* MXVR DMA0 Registers */
-
-#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
-#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
-#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-
-/* MXVR DMA1 Registers */
-
-#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
-#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
-#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-
-/* MXVR DMA2 Registers */
-
-#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
-#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
-#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-
-/* MXVR DMA3 Registers */
-
-#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
-#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
-#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-
-/* MXVR DMA4 Registers */
-
-#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
-#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
-#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-
-/* MXVR DMA5 Registers */
-
-#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
-#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
-#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-
-/* MXVR DMA6 Registers */
-
-#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
-#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
-#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-
-/* MXVR DMA7 Registers */
-
-#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
-#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
-#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-
-/* MXVR Asynch Packet Registers */
-
-#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
-#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
-#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
-#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
-
-/* MXVR Control Message Registers */
-
-#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
-#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
-#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
-#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
-
-/* MXVR Remote Read Registers */
-
-#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
-#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
-
-/* MXVR Pattern Data Registers */
-
-#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
-
-/* MXVR Frame Counter Registers */
-
-#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-
-/* MXVR Routing Table Registers */
-
-#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
-
-#endif /* _CDEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
deleted file mode 100644
index 50c89c8052f3..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ /dev/null
@@ -1,2633 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF54X_H
-#define _CDEF_BF54X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-
-/* SIC Registers */
-
-#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
-
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
-
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
-
-/* Watchdog Timer Registers */
-
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-
-/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPORT1 Registers */
-
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-
-/* Asynchronous Memory Control Registers */
-
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
-
-/* DDR Memory Control Registers */
-
-#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
-
-/* DMAC0 Registers */
-
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-
-/* MDMA Stream 0 Registers */
-
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers */
-
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-
-/* EPPI1 Registers */
-
-#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA() bfin_read16(PORTA)
-#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-
-/* Port B Registers */
-
-#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB() bfin_read16(PORTB)
-#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-
-/* Port C Registers */
-
-#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC() bfin_read16(PORTC)
-#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-
-/* Port D Registers */
-
-#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD() bfin_read16(PORTD)
-#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-
-/* Port E Registers */
-
-#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE() bfin_read16(PORTE)
-#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-
-/* Port F Registers */
-
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF() bfin_read16(PORTF)
-#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-
-/* Port G Registers */
-
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG() bfin_read16(PORTG)
-#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-
-/* Port H Registers */
-
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH() bfin_read16(PORTH)
-#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
-
-/* Port I Registers */
-
-#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI() bfin_read16(PORTI)
-#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
-
-/* Port J Registers */
-
-#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ() bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
-
-/* PWM Timer Registers */
-
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-/* Timer Groubfin_read_() of 8 */
-
-#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
-
-/* DMAC1 Registers */
-
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-
-/* DMA Channel 21 Registers */
-
-#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-
-/* DMA Channel 22 Registers */
-
-#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-
-/* DMA Channel 23 Registers */
-
-#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-
-/* MDMA Stream 2 Registers */
-
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers */
-
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-
-/* SPORT2 Registers */
-
-#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
-
-/* SPORT3 Registers */
-
-#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
-
-/* EPPI2 Registers */
-
-#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* UART3 Registers */
-
-#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
-
-/* DMA Peribfin_read_()heral Mux Register */
-
-#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
-
-#endif /* _CDEF_BF54X_H */
-
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
deleted file mode 100644
index ae4b889e3606..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF542_H
-#define _DEF_BF542_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF542_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
deleted file mode 100644
index 018ebfc27f5a..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF544_H
-#define _DEF_BF544_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-#endif /* _DEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
deleted file mode 100644
index 7cc7928a3c73..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ /dev/null
@@ -1,1034 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF547_H
-#define _DEF_BF547_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
-#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
-#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
-#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
-#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
-#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
-#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
-#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
-#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
-#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
-#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
-#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
-#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
-#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
-#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
-#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
-#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
-#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
-#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
-#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
-#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
-#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
-#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
-#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
-#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
-#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
-#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
-#define UART2_GCTL 0xffc02108 /* Global Control Register */
-#define UART2_LCR 0xffc0210c /* Line Control Register */
-#define UART2_MCR 0xffc02110 /* Modem Control Register */
-#define UART2_LSR 0xffc02114 /* Line Status Register */
-#define UART2_MSR 0xffc02118 /* Modem Status Register */
-#define UART2_SCR 0xffc0211c /* Scratch Register */
-#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
-#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
-#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define TWI1_REGBASE 0xffc02200
-#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
-#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
-#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
-#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
-#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
-#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
-#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
-#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2 Registers */
-
-#define SPI2_REGBASE 0xffc02400
-#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
-#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
-#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
-#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
-#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
-
-/* ATAPI Registers */
-
-#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
-#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
-#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
-#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
-#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
-#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
-#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
-#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
-#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
-#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
-#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
-#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
-#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
-#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
-#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
-#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
-#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
-#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
-#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
-#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
-#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
-#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
-#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
-#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
-#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
-#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
-#define SDH_COMMAND 0xffc0390c /* SDH Command */
-#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
-#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
-#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
-#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
-#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
-#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
-#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
-#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
-#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
-#define SDH_STATUS 0xffc03934 /* SDH Status */
-#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
-#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
-#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
-#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
-#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
-#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
-#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
-#define SDH_CFG 0xffc039c8 /* SDH Configuration */
-#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
-#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
-#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
-#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
-#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
-#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
-#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
-#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
-#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
-#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
-#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define USB_FADDR 0xffc03c00 /* Function address register */
-#define USB_POWER 0xffc03c04 /* Power management register */
-#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
-#define USB_FRAME 0xffc03c20 /* USB frame number */
-#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
-#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
-#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
-#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
-#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
-#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
-#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
-#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
-#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
-#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
-#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
-#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
-#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
-#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
-#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
-#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
-#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
-#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
-#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
-#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
-#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
-#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
-#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
-#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
-#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
-#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
-#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
-#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */
-#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */
-#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define PIXC_EN 0x1 /* Pixel Compositor Enable */
-#define OVR_A_EN 0x2 /* Overlay A Enable */
-#define OVR_B_EN 0x4 /* Overlay B Enable */
-#define IMG_FORM 0x8 /* Image Data Format */
-#define OVR_FORM 0x10 /* Overlay Data Format */
-#define OUT_FORM 0x20 /* Output Data Format */
-#define UDS_MOD 0x40 /* Resampling Mode */
-#define TC_EN 0x80 /* Transparent Color Enable */
-#define IMG_STAT 0x300 /* Image FIFO Status */
-#define OVR_STAT 0xc00 /* Overlay FIFO Status */
-#define WM_LVL 0x3000 /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define A_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define A_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define A_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define A_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define A_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define B_HSTART 0xfff /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define B_HEND 0xfff /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define B_VSTART 0x3ff /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define B_VEND 0x3ff /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define B_TRANSP 0xf /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
-#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
-#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
-#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define A11 0x3ff /* A11 in the Coefficient Matrix */
-#define A12 0xffc00 /* A12 in the Coefficient Matrix */
-#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
-#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define A21 0x3ff /* A21 in the Coefficient Matrix */
-#define A22 0xffc00 /* A22 in the Coefficient Matrix */
-#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
-#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define A31 0x3ff /* A31 in the Coefficient Matrix */
-#define A32 0xffc00 /* A32 in the Coefficient Matrix */
-#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
-#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define A14 0x3ff /* A14 in the Bias Vector */
-#define A24 0xffc00 /* A24 in the Bias Vector */
-#define A34 0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
-#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
-#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
-
-/* Bit masks for KPAD_CTL */
-
-#define KPAD_EN 0x1 /* Keypad Enable */
-#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
-#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
-#define KPAD_COLEN 0xe000 /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define DBON_SCALE 0xff /* Debounce Scale Value */
-#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define KPAD_ROW 0xff /* Rows Pressed */
-#define KPAD_COL 0xff00 /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
-#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
-#define KPAD_PRESSED 0x8 /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define PIO_START 0x1 /* Start PIO/Reg Op */
-#define MULTI_START 0x2 /* Start Multi-DMA Op */
-#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
-#define XFER_DIR 0x8 /* Transfer Direction */
-#define IORDY_EN 0x10 /* IORDY Enable */
-#define FIFO_FLUSH 0x20 /* Flush FIFOs */
-#define SOFT_RST 0x40 /* Soft Reset */
-#define DEV_RST 0x80 /* Device Reset */
-#define TFRCNT_RST 0x100 /* Trans Count Reset */
-#define END_ON_TERM 0x200 /* End/Terminate Select */
-#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
-#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
-#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
-#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
-#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define DEV_ADDR 0x1f /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
-#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
-#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
-#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
-#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
-#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
-#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
-#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
-#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
-#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
-#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
-#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
-#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
-#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
-#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
-#define ATAPI_DASP 0x2 /* Device dasp to host line status */
-#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
-#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
-#define ATAPI_ADDR 0x70 /* ATAPI address line status */
-#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
-#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
-#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
-#define ATAPI_DIORN 0x400 /* ATAPI read line status */
-#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define PIO_CSTATE 0xf /* PIO mode state machine current state */
-#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
-#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
-#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define T2_REG 0xff /* End of cycle time for register access transfers */
-#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
-#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
-#define T4_REG 0xf000 /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
-#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define TKW 0xff /* Selects DIOW negated pulsewidth */
-#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define TH 0xff /* Selects DIOW data hold */
-#define TEOC 0xff00 /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define TACK 0xff /* Selects setup and hold times for TACK */
-#define TENV 0xff00 /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define TDVS 0xff /* Selects data valid setup time */
-#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define TMLI 0xff00 /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define TZAH 0xff /* Selects minimum delay required for output */
-#define READY_PAUSE 0xff00 /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define TIMEN8 0x1 /* Timer 8 Enable */
-#define TIMEN9 0x2 /* Timer 9 Enable */
-#define TIMEN10 0x4 /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define TIMDIS8 0x1 /* Timer 8 Disable */
-#define TIMDIS9 0x2 /* Timer 9 Disable */
-#define TIMDIS10 0x4 /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define TIMIL8 0x1 /* Timer 8 Interrupt */
-#define TIMIL9 0x2 /* Timer 9 Interrupt */
-#define TIMIL10 0x4 /* Timer 10 Interrupt */
-#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
-#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
-#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
-#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
-#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
-#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define FUNCTION_ADDRESS 0x7f /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
-#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
-#define RESUME_MODE 0x4 /* DMA Mode */
-#define RESET 0x8 /* Reset indicator */
-#define HS_MODE 0x10 /* High Speed mode indicator */
-#define HS_ENABLE 0x20 /* high Speed Enable */
-#define SOFT_CONN 0x40 /* Soft connect */
-#define ISO_UPDATE 0x80 /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
-#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
-#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
-#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
-#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
-#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
-#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
-#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
-#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
-#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
-#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
-#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
-#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
-#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
-#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
-#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
-#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
-#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
-#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
-#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
-#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
-#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
-#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
-#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
-#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
-#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
-#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define SUSPEND_B 0x1 /* Suspend indicator */
-#define RESUME_B 0x2 /* Resume indicator */
-#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
-#define SOF_B 0x8 /* Start of frame */
-#define CONN_B 0x10 /* Connection indicator */
-#define DISCON_B 0x20 /* Disconnect indicator */
-#define SESSION_REQ_B 0x40 /* Session Request */
-#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
-#define RESUME_BE 0x2 /* Resume indicator int enable */
-#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
-#define SOF_BE 0x8 /* Start of frame int enable */
-#define CONN_BE 0x10 /* Connection indicator int enable */
-#define DISCON_BE 0x20 /* Disconnect indicator int enable */
-#define SESSION_REQ_BE 0x40 /* Session Request int enable */
-#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define FRAME_NUMBER 0x7ff /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define SELECTED_ENDPOINT 0xf /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define GLOBAL_ENA 0x1 /* enables USB module */
-#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
-#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
-#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
-#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
-#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
-#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
-#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
-#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
-#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
-#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
-#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
-#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
-#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
-#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define SESSION 0x1 /* session indicator */
-#define HOST_REQ 0x2 /* Host negotiation request */
-#define HOST_MODE 0x4 /* indicates USBDRC is a host */
-#define VBUS0 0x8 /* Vbus level indicator[0] */
-#define VBUS1 0x10 /* Vbus level indicator[1] */
-#define LSDEV 0x20 /* Low-speed indicator */
-#define FSDEV 0x40 /* Full or High-speed indicator */
-#define B_DEVICE 0x80 /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
-#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
-#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
-#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
-#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
-#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
-#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
-#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
-#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
-#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
-#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define RXPKTRDY 0x1 /* data packet receive indicator */
-#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
-#define STALL_SENT 0x4 /* STALL handshake sent */
-#define DATAEND 0x8 /* Data end indicator */
-#define SETUPEND 0x10 /* Setup end */
-#define SENDSTALL 0x20 /* Send STALL handshake */
-#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
-#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
-#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
-#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
-#define SETUPPKT_H 0x8 /* send Setup token host mode */
-#define ERROR_H 0x10 /* timeout error indicator host mode */
-#define REQPKT_H 0x20 /* Request an IN transaction host mode */
-#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
-#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
-#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
-#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
-#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
-#define STALL_SEND_T 0x10 /* issue a Stall handshake */
-#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
-#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
-#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
-#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
-#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
-#define ISO_T 0x4000 /* enable Isochronous transfers */
-#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_TH 0x4 /* error condition host mode */
-#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
-#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
-#define FIFO_FULL_R 0x2 /* FIFO not empty */
-#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
-#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
-#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
-#define STALL_SEND_R 0x20 /* issue a Stall handshake */
-#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
-#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
-#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
-#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
-#define DISNYET_R 0x1000 /* disable Nyet handshakes */
-#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
-#define ISO_R 0x4000 /* enable Isochronous transfers */
-#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
-#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
-#define REQPKT_RH 0x20 /* request an IN transaction host mode */
-#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
-#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
-#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
-#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define TARGET_EP_NO_T 0xf /* EP number */
-#define PROTOCOL_T 0xc /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define TARGET_EP_NO_R 0xf /* EP number */
-#define PROTOCOL_R 0xc /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define DMA0_INT 0x1 /* DMA0 pending interrupt */
-#define DMA1_INT 0x2 /* DMA1 pending interrupt */
-#define DMA2_INT 0x4 /* DMA2 pending interrupt */
-#define DMA3_INT 0x8 /* DMA3 pending interrupt */
-#define DMA4_INT 0x10 /* DMA4 pending interrupt */
-#define DMA5_INT 0x20 /* DMA5 pending interrupt */
-#define DMA6_INT 0x40 /* DMA6 pending interrupt */
-#define DMA7_INT 0x80 /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define DMA_ENA 0x1 /* DMA enable */
-#define DIRECTION 0x2 /* direction of DMA transfer */
-#define MODE 0x4 /* DMA Bus error */
-#define INT_ENA 0x8 /* Interrupt enable */
-#define EPNUM 0xf0 /* EP number */
-#define BUSERROR 0x100 /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
deleted file mode 100644
index 27f29481e283..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ /dev/null
@@ -1,399 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF548 is like the BF547, but has additional CANs */
-#include "defBF547.h"
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
-#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
-#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
-#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
-#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
-#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
-#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
-#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
-#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
-#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
-#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
-#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
-#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
-#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
-#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
-#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
-#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
-#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
-#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
-#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
-#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
-#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
-#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
-#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
-#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
-#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
-#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
-#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
-#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
-#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
-#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
-#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
-#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
-#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
-#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
-#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
-#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
-#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
-#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
-#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
-#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
-#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
-#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
-#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
-#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
-#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
-#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
-#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
-#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
-#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
-#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
-#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
-#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
-#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
-#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-#endif /* _DEF_BF548_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
deleted file mode 100644
index ac569fc12972..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The BF549 is like the BF544, but has MXVR */
-#include "defBF547.h"
-
-/* MXVR Registers */
-
-#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
-#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
-#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
-#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
-#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
-#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
-#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
-#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
-#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
-#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
-#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
-#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
-#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
-#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
-#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
-#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
-#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
-#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
-#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
-#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
-#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
-#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
-#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
-#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
-#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
-#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
-#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
-#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
-#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
-#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
-#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
-
-#endif /* _DEF_BF549_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
deleted file mode 100644
index 8f6e1925779d..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ /dev/null
@@ -1,2294 +0,0 @@
-/*
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF54X_H
-#define _DEF_BF54X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define PLL_CTL 0xffc00000 /* PLL Control Register */
-#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
-#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
-#define PLL_STAT 0xffc0000c /* PLL Status Register */
-#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define SWRST 0xffc00100 /* Software Reset Register */
-#define SYSCR 0xffc00104 /* System Configuration register */
-
-/* SIC Registers */
-
-#define SIC_RVECT 0xffc00108
-#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
-#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
-#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
-#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
-#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
-#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
-#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
-#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
-#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
-#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
-#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
-#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
-#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
-#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
-
-/* Watchdog Timer Registers */
-
-#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
-#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
-#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
-
-/* RTC Registers */
-
-#define RTC_STAT 0xffc00300 /* RTC Status Register */
-#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
-#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
-#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
-
-/* UART0 Registers */
-
-#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
-#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
-#define UART0_GCTL 0xffc00408 /* Global Control Register */
-#define UART0_LCR 0xffc0040c /* Line Control Register */
-#define UART0_MCR 0xffc00410 /* Modem Control Register */
-#define UART0_LSR 0xffc00414 /* Line Status Register */
-#define UART0_MSR 0xffc00418 /* Modem Status Register */
-#define UART0_SCR 0xffc0041c /* Scratch Register */
-#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
-#define UART0_THR 0xffc00428 /* Transmit Hold Register */
-#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
-
-/* SPI0 Registers */
-
-#define SPI0_REGBASE 0xffc00500
-#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
-#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
-#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
-#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
-#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define TWI0_REGBASE 0xffc00700
-#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
-#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
-#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
-#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
-#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
-#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
-#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
-#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
-#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
-#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
-#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
-#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
-#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
-#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
-#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
-
-/* Asynchronous Memory Control Registers */
-
-#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
-#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
-#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
-#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
-#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
-#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
-
-/* DDR Memory Control Registers */
-
-#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
-#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
-#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
-#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
-#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
-#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
-#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
-#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
-
-/* DDR BankRead and Write Count Registers */
-
-#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
-#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
-#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
-#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
-#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
-#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
-#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
-#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
-#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
-#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
-#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
-#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
-#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
-#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
-#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
-#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
-#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
-#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
-#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
-#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
-#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
-#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
-#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
-#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
-#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
-
-/* DMAC0 Registers */
-
-#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
-
-/* DMA Channel 0 Registers */
-
-#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
-
-/* DMA Channel 1 Registers */
-
-#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
-
-/* DMA Channel 2 Registers */
-
-#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
-
-/* DMA Channel 3 Registers */
-
-#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
-
-/* DMA Channel 4 Registers */
-
-#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
-
-/* DMA Channel 5 Registers */
-
-#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
-
-/* DMA Channel 6 Registers */
-
-#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
-
-/* DMA Channel 7 Registers */
-
-#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
-
-/* DMA Channel 8 Registers */
-
-#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
-
-/* DMA Channel 9 Registers */
-
-#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
-
-/* DMA Channel 10 Registers */
-
-#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
-
-/* DMA Channel 11 Registers */
-
-#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
-
-/* MDMA Stream 0 Registers */
-
-#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
-
-/* MDMA Stream 1 Registers */
-
-#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* EPPI1 Registers */
-
-#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
-#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
-#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
-#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
-#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
-#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
-#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
-#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
-#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
-#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
-#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
-#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
-#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
-#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
-#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
-#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
-#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
-#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
-#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
-#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
-#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
-#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
-#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
-#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
-#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
-#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
-#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
-#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
-#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
-#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
-#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
-#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
-#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
-#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
-
-/* Port A Registers */
-
-#define PORTA_FER 0xffc014c0 /* Function Enable Register */
-#define PORTA 0xffc014c4 /* GPIO Data Register */
-#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
-#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
-#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
-#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
-#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
-
-/* Port B Registers */
-
-#define PORTB_FER 0xffc014e0 /* Function Enable Register */
-#define PORTB 0xffc014e4 /* GPIO Data Register */
-#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
-#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
-#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
-#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
-#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
-
-/* Port C Registers */
-
-#define PORTC_FER 0xffc01500 /* Function Enable Register */
-#define PORTC 0xffc01504 /* GPIO Data Register */
-#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
-#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
-#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
-#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
-#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
-
-/* Port D Registers */
-
-#define PORTD_FER 0xffc01520 /* Function Enable Register */
-#define PORTD 0xffc01524 /* GPIO Data Register */
-#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
-#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
-#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
-#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
-#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
-
-/* Port E Registers */
-
-#define PORTE_FER 0xffc01540 /* Function Enable Register */
-#define PORTE 0xffc01544 /* GPIO Data Register */
-#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
-#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
-#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
-#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
-#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
-
-/* Port F Registers */
-
-#define PORTF_FER 0xffc01560 /* Function Enable Register */
-#define PORTF 0xffc01564 /* GPIO Data Register */
-#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
-#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
-#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
-#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
-#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
-
-/* Port G Registers */
-
-#define PORTG_FER 0xffc01580 /* Function Enable Register */
-#define PORTG 0xffc01584 /* GPIO Data Register */
-#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
-#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
-#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
-#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
-#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
-
-/* Port H Registers */
-
-#define PORTH_FER 0xffc015a0 /* Function Enable Register */
-#define PORTH 0xffc015a4 /* GPIO Data Register */
-#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
-#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
-#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
-#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
-#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
-#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
-
-/* Port I Registers */
-
-#define PORTI_FER 0xffc015c0 /* Function Enable Register */
-#define PORTI 0xffc015c4 /* GPIO Data Register */
-#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
-#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
-#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
-#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
-#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
-#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
-
-/* Port J Registers */
-
-#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
-#define PORTJ 0xffc015e4 /* GPIO Data Register */
-#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
-#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
-#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
-#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
-#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
-#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
-
-/* PWM Timer Registers */
-
-#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
-#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
-#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
-#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
-#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
-#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
-#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
-#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
-
-/* Timer Group of 8 */
-
-#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
-#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
-#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
-
-/* DMAC1 Registers */
-
-#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
-
-/* DMA Channel 12 Registers */
-
-#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
-
-/* DMA Channel 13 Registers */
-
-#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
-
-/* DMA Channel 14 Registers */
-
-#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
-
-/* DMA Channel 15 Registers */
-
-#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
-
-/* DMA Channel 16 Registers */
-
-#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
-
-/* DMA Channel 17 Registers */
-
-#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
-
-/* DMA Channel 18 Registers */
-
-#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
-
-/* DMA Channel 19 Registers */
-
-#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
-
-/* DMA Channel 20 Registers */
-
-#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
-#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
-#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
-#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
-#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
-#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
-#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
-#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
-#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
-#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
-#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
-#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
-#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
-
-/* DMA Channel 21 Registers */
-
-#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
-#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
-#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
-#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
-#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
-#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
-#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
-#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
-#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
-#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
-#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
-#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
-#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
-
-/* DMA Channel 22 Registers */
-
-#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
-#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
-#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
-#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
-#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
-#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
-#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
-#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
-#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
-#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
-#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
-#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
-#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
-
-/* DMA Channel 23 Registers */
-
-#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
-#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
-#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
-#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
-#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
-#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
-#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
-#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
-#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
-#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
-#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
-#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
-#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
-
-/* MDMA Stream 2 Registers */
-
-#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
-#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
-#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
-#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
-#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
-#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
-#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
-#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
-#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
-#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
-#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
-#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
-#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
-#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
-#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
-#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
-#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
-
-/* MDMA Stream 3 Registers */
-
-#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
-#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
-#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
-#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
-#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
-#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
-#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
-#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
-#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
-#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
-#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
-#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
-#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
-#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
-#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
-#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
-#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
-
-/* UART1 Registers */
-
-#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
-#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
-#define UART1_GCTL 0xffc02008 /* Global Control Register */
-#define UART1_LCR 0xffc0200c /* Line Control Register */
-#define UART1_MCR 0xffc02010 /* Modem Control Register */
-#define UART1_LSR 0xffc02014 /* Line Status Register */
-#define UART1_MSR 0xffc02018 /* Modem Status Register */
-#define UART1_SCR 0xffc0201c /* Scratch Register */
-#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
-#define UART1_THR 0xffc02028 /* Transmit Hold Register */
-#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define SPI1_REGBASE 0xffc02300
-#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
-#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
-#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
-#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
-#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
-
-/* SPORT2 Registers */
-
-#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
-#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
-#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
-#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
-#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
-#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
-#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
-#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
-#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
-#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
-#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
-#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
-#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
-#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
-#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
-#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
-#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
-#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
-#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
-
-/* SPORT3 Registers */
-
-#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
-#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
-#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
-#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
-#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
-#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
-#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
-#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
-#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
-#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
-#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
-#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
-#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
-#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
-#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
-#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
-#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
-#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
-#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
-
-/* EPPI2 Registers */
-
-#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
-#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
-#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
-#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
-#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
-#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
-#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
-#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
-#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
-#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
-#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
-#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
-#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
-#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
-
-/* UART3 Registers */
-
-#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
-#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
-#define UART3_GCTL 0xffc03108 /* Global Control Register */
-#define UART3_LCR 0xffc0310c /* Line Control Register */
-#define UART3_MCR 0xffc03110 /* Modem Control Register */
-#define UART3_LSR 0xffc03114 /* Line Status Register */
-#define UART3_MSR 0xffc03118 /* Modem Status Register */
-#define UART3_SCR 0xffc0311c /* Scratch Register */
-#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
-#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
-#define UART3_THR 0xffc03128 /* Transmit Hold Register */
-#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
-
-/* NFC Registers */
-
-#define NFC_CTL 0xffc03b00 /* NAND Control Register */
-#define NFC_STAT 0xffc03b04 /* NAND Status Register */
-#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
-#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
-#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
-#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
-#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
-#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
-#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
-#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
-#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
-#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
-#define NFC_CMD 0xffc03b44 /* NAND Command Register */
-#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
-#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
-
-/* Counter Registers */
-
-#define CNT_CONFIG 0xffc04200 /* Configuration Register */
-#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
-#define CNT_STATUS 0xffc04208 /* Status Register */
-#define CNT_COMMAND 0xffc0420c /* Command Register */
-#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
-#define CNT_COUNTER 0xffc04214 /* Counter Register */
-#define CNT_MAX 0xffc04218 /* Maximal Count Register */
-#define CNT_MIN 0xffc0421c /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
-#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
-#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
-#define SECURE_CONTROL 0xffc04324 /* Secure Control */
-#define SECURE_STATUS 0xffc04328 /* Secure Status */
-
-/* DMA Peripheral Mux Register */
-
-#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
-
-/* ********************************************************** */
-/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
-/* and MULTI BIT READ MACROS */
-/* ********************************************************** */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* Bit masks for SIC_IAR0 */
-
-#define PLL_WAKEUP 0x1 /* PLL Wakeup */
-
-/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-
-#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
-#define EPPI0_ERR 0x4 /* EPPI0 Error */
-#define SPORT0_ERR 0x8 /* SPORT0 Error */
-#define SPORT1_ERR 0x10 /* SPORT1 Error */
-#define SPI0_ERR 0x20 /* SPI0 Error */
-#define UART0_ERR 0x40 /* UART0 Error */
-#define RTC 0x80 /* Real-Time Clock */
-#define DMA12 0x100 /* DMA Channel 12 */
-#define DMA0 0x200 /* DMA Channel 0 */
-#define DMA1 0x400 /* DMA Channel 1 */
-#define DMA2 0x800 /* DMA Channel 2 */
-#define DMA3 0x1000 /* DMA Channel 3 */
-#define DMA4 0x2000 /* DMA Channel 4 */
-#define DMA6 0x4000 /* DMA Channel 6 */
-#define DMA7 0x8000 /* DMA Channel 7 */
-#define PINT0 0x80000 /* Pin Interrupt 0 */
-#define PINT1 0x100000 /* Pin Interrupt 1 */
-#define MDMA0 0x200000 /* Memory DMA Stream 0 */
-#define MDMA1 0x400000 /* Memory DMA Stream 1 */
-#define WDOG 0x800000 /* Watchdog Timer */
-#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
-#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
-#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
-#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
-#define SPI1_ERR 0x10000000 /* SPI1 Error */
-#define SPI2_ERR 0x20000000 /* SPI2 Error */
-#define UART1_ERR 0x40000000 /* UART1 Error */
-#define UART2_ERR 0x80000000 /* UART2 Error */
-
-/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-
-#define CAN0_ERR 0x1 /* CAN0 Error */
-#define DMA18 0x2 /* DMA Channel 18 */
-#define DMA19 0x4 /* DMA Channel 19 */
-#define DMA20 0x8 /* DMA Channel 20 */
-#define DMA21 0x10 /* DMA Channel 21 */
-#define DMA13 0x20 /* DMA Channel 13 */
-#define DMA14 0x40 /* DMA Channel 14 */
-#define DMA5 0x80 /* DMA Channel 5 */
-#define DMA23 0x100 /* DMA Channel 23 */
-#define DMA8 0x200 /* DMA Channel 8 */
-#define DMA9 0x400 /* DMA Channel 9 */
-#define DMA10 0x800 /* DMA Channel 10 */
-#define DMA11 0x1000 /* DMA Channel 11 */
-#define TWI0 0x2000 /* TWI0 */
-#define TWI1 0x4000 /* TWI1 */
-#define CAN0_RX 0x8000 /* CAN0 Receive */
-#define CAN0_TX 0x10000 /* CAN0 Transmit */
-#define MDMA2 0x20000 /* Memory DMA Stream 0 */
-#define MDMA3 0x40000 /* Memory DMA Stream 1 */
-#define MXVR_STAT 0x80000 /* MXVR Status */
-#define MXVR_CM 0x100000 /* MXVR Control Message */
-#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
-#define EPPI1_ERR 0x400000 /* EPPI1 Error */
-#define EPPI2_ERR 0x800000 /* EPPI2 Error */
-#define UART3_ERR 0x1000000 /* UART3 Error */
-#define HOST_ERR 0x2000000 /* Host DMA Port Error */
-#define USB_ERR 0x4000000 /* USB Error */
-#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
-#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
-#define ATAPI_ERR 0x20000000 /* ATAPI Error */
-#define CAN1_ERR 0x40000000 /* CAN1 Error */
-#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
-#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
-#define DMAR0 0x80000000 /* DMAR0 Block */
-#define DMAR1 0x80000000 /* DMAR1 Block */
-
-/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-
-#define DMA15 0x1 /* DMA Channel 15 */
-#define DMA16 0x2 /* DMA Channel 16 */
-#define DMA17 0x4 /* DMA Channel 17 */
-#define DMA22 0x8 /* DMA Channel 22 */
-#define CNT 0x10 /* Counter */
-#define KEY 0x20 /* Keypad */
-#define CAN1_RX 0x40 /* CAN1 Receive */
-#define CAN1_TX 0x80 /* CAN1 Transmit */
-#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
-#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
-#define USB_EINT 0x400 /* USB Exception */
-#define USB_INT0 0x800 /* USB Interrupt 0 */
-#define USB_INT1 0x1000 /* USB Interrupt 1 */
-#define USB_INT2 0x2000 /* USB Interrupt 2 */
-#define USB_DMAINT 0x4000 /* USB DMA */
-#define OTPSEC 0x8000 /* OTP Access Complete */
-#define TIMER0 0x400000 /* Timer 0 */
-#define TIMER1 0x800000 /* Timer 1 */
-#define TIMER2 0x1000000 /* Timer 2 */
-#define TIMER3 0x2000000 /* Timer 3 */
-#define TIMER4 0x4000000 /* Timer 4 */
-#define TIMER5 0x8000000 /* Timer 5 */
-#define TIMER6 0x10000000 /* Timer 6 */
-#define TIMER7 0x20000000 /* Timer 7 */
-#define PINT2 0x40000000 /* Pin Interrupt 2 */
-#define PINT3 0x80000000 /* Pin Interrupt 3 */
-
-/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define CTYPE 0x40 /* DMA Channel Type */
-#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
-
-/* Bit masks for DMACx_TC_PER */
-
-#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
-#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
-#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
-#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
-
-/* Bit masks for DMACx_TC_CNT */
-
-#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
-#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
-#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
-#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
-
-/* Bit masks for DMAC1_PERIMUX */
-
-#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
-/* EBIU_AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_NONE 0x0000 /* All Banks Disabled */
-#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
-
-
-/* Bit masks for EBIU_AMBCTL0 */
-
-#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
-#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
-#define B0TT 0xc /* Bank 0 transition time */
-#define B0ST 0x30 /* Bank 0 Setup time */
-#define B0HT 0xc0 /* Bank 0 Hold time */
-#define B0RAT 0xf00 /* Bank 0 Read access time */
-#define B0WAT 0xf000 /* Bank 0 write access time */
-#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
-#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
-#define B1TT 0xc0000 /* Bank 1 transition time */
-#define B1ST 0x300000 /* Bank 1 Setup time */
-#define B1HT 0xc00000 /* Bank 1 Hold time */
-#define B1RAT 0xf000000 /* Bank 1 Read access time */
-#define B1WAT 0xf0000000 /* Bank 1 write access time */
-
-/* Bit masks for EBIU_AMBCTL1 */
-
-#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
-#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
-#define B2TT 0xc /* Bank 2 transition time */
-#define B2ST 0x30 /* Bank 2 Setup time */
-#define B2HT 0xc0 /* Bank 2 Hold time */
-#define B2RAT 0xf00 /* Bank 2 Read access time */
-#define B2WAT 0xf000 /* Bank 2 write access time */
-#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
-#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
-#define B3TT 0xc0000 /* Bank 3 transition time */
-#define B3ST 0x300000 /* Bank 3 Setup time */
-#define B3HT 0xc00000 /* Bank 3 Hold time */
-#define B3RAT 0xf000000 /* Bank 3 Read access time */
-#define B3WAT 0xf0000000 /* Bank 3 write access time */
-
-/* Bit masks for EBIU_MBSCTL */
-
-#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
-#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
-#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
-#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
-
-/* Bit masks for EBIU_MODE */
-
-#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
-#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
-#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
-#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
-
-/* Bit masks for EBIU_FCTL */
-
-#define TESTSETLOCK 0x1 /* Test set lock */
-#define BCLK 0x6 /* Burst clock frequency */
-#define PGWS 0x38 /* Page wait states */
-#define PGSZ 0x40 /* Page size */
-#define RDDL 0x380 /* Read data delay */
-
-/* Bit masks for EBIU_ARBSTAT */
-
-#define ARBSTAT 0x1 /* Arbitration status */
-#define BGSTAT 0x2 /* Bus grant status */
-
-/* Bit masks for EBIU_DDRCTL0 */
-
-#define TREFI 0x3fff /* Refresh Interval */
-#define TRFC 0x3c000 /* Auto-refresh command period */
-#define TRP 0x3c0000 /* Pre charge-to-active command period */
-#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
-#define TRC 0x3c000000 /* Active-to-active time */
-#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
-#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
-#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
-#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
-#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
-
-/* Bit masks for EBIU_DDRCTL1 */
-
-#define TRCD 0xf /* Active-to-Read/write delay */
-#define TMRD 0xf0 /* Mode register set to active */
-#define TWR 0x300 /* Write Recovery time */
-#define DDRDATWIDTH 0x3000 /* DDR data width */
-#define EXTBANKS 0xc000 /* External banks */
-#define DDRDEVWIDTH 0x30000 /* DDR device width */
-#define DDRDEVSIZE 0xc0000 /* DDR device size */
-#define TWTR 0xf0000000 /* Write-to-read delay */
-#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
-#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
-#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
-#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
-#define DDR_DATWIDTH 0x2000 /* DDR data width */
-#define EXTBANK_1 0 /* 1 external bank */
-#define EXTBANK_2 0x4000 /* 2 external banks */
-#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
-#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
-#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
-#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
-#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
-#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
-#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
-
-/* Bit masks for EBIU_DDRCTL2 */
-
-#define BURSTLENGTH 0x7 /* Burst length */
-#define CASLATENCY 0x70 /* CAS latency */
-#define DLLRESET 0x100 /* DLL Reset */
-#define REGE 0x1000 /* Register mode enable */
-#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
-#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
-#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
-#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
-
-/* Bit masks for EBIU_DDRCTL3 */
-
-#define PASR 0x7 /* Partial array self-refresh */
-
-/* Bit masks for EBIU_DDRQUE */
-
-#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
-#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
-#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
-#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
-#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
-#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
-#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
-
-/* Bit masks for EBIU_ERRMST */
-
-#define DEB1_ERROR 0x1 /* DEB1 Error */
-#define DEB2_ERROR 0x2 /* DEB2 Error */
-#define DEB3_ERROR 0x4 /* DEB3 Error */
-#define CORE_ERROR 0x8 /* Core error */
-#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
-#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
-#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
-#define CORE_MERROR 0x80 /* Core Error (2nd) */
-
-/* Bit masks for EBIU_RSTCTL */
-
-#define DDRSRESET 0x1 /* DDR soft reset */
-#define PFTCHSRESET 0x4 /* DDR prefetch reset */
-#define SRREQ 0x8 /* Self-refresh request */
-#define SRACK 0x10 /* Self-refresh acknowledge */
-#define MDDRENABLE 0x20 /* Mobile DDR enable */
-
-/* Bit masks for EBIU_DDRMCEN */
-
-#define B0WCENABLE 0x1 /* Bank 0 write count enable */
-#define B1WCENABLE 0x2 /* Bank 1 write count enable */
-#define B2WCENABLE 0x4 /* Bank 2 write count enable */
-#define B3WCENABLE 0x8 /* Bank 3 write count enable */
-#define B4WCENABLE 0x10 /* Bank 4 write count enable */
-#define B5WCENABLE 0x20 /* Bank 5 write count enable */
-#define B6WCENABLE 0x40 /* Bank 6 write count enable */
-#define B7WCENABLE 0x80 /* Bank 7 write count enable */
-#define B0RCENABLE 0x100 /* Bank 0 read count enable */
-#define B1RCENABLE 0x200 /* Bank 1 read count enable */
-#define B2RCENABLE 0x400 /* Bank 2 read count enable */
-#define B3RCENABLE 0x800 /* Bank 3 read count enable */
-#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
-#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
-#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
-#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
-#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
-#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
-#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
-#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
-#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
-#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
-#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
-#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
-
-/* Bit masks for EBIU_DDRMCCL */
-
-#define CB0WCOUNT 0x1 /* Clear write count 0 */
-#define CB1WCOUNT 0x2 /* Clear write count 1 */
-#define CB2WCOUNT 0x4 /* Clear write count 2 */
-#define CB3WCOUNT 0x8 /* Clear write count 3 */
-#define CB4WCOUNT 0x10 /* Clear write count 4 */
-#define CB5WCOUNT 0x20 /* Clear write count 5 */
-#define CB6WCOUNT 0x40 /* Clear write count 6 */
-#define CB7WCOUNT 0x80 /* Clear write count 7 */
-#define CBRCOUNT 0x100 /* Clear read count 0 */
-#define CB1RCOUNT 0x200 /* Clear read count 1 */
-#define CB2RCOUNT 0x400 /* Clear read count 2 */
-#define CB3RCOUNT 0x800 /* Clear read count 3 */
-#define CB4RCOUNT 0x1000 /* Clear read count 4 */
-#define CB5RCOUNT 0x2000 /* Clear read count 5 */
-#define CB6RCOUNT 0x4000 /* Clear read count 6 */
-#define CB7RCOUNT 0x8000 /* Clear read count 7 */
-#define CRACOUNT 0x10000 /* Clear row activation count */
-#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
-#define CARCOUNT 0x40000 /* Clear auto-refresh count */
-#define CG0COUNT 0x100000 /* Clear grant count 0 */
-#define CG1COUNT 0x200000 /* Clear grant count 1 */
-#define CG2COUNT 0x400000 /* Clear grant count 2 */
-#define CG3COUNT 0x800000 /* Clear grant count 3 */
-
-/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
-
-#define Px0 0x1 /* GPIO 0 */
-#define Px1 0x2 /* GPIO 1 */
-#define Px2 0x4 /* GPIO 2 */
-#define Px3 0x8 /* GPIO 3 */
-#define Px4 0x10 /* GPIO 4 */
-#define Px5 0x20 /* GPIO 5 */
-#define Px6 0x40 /* GPIO 6 */
-#define Px7 0x80 /* GPIO 7 */
-#define Px8 0x100 /* GPIO 8 */
-#define Px9 0x200 /* GPIO 9 */
-#define Px10 0x400 /* GPIO 10 */
-#define Px11 0x800 /* GPIO 11 */
-#define Px12 0x1000 /* GPIO 12 */
-#define Px13 0x2000 /* GPIO 13 */
-#define Px14 0x4000 /* GPIO 14 */
-#define Px15 0x8000 /* GPIO 15 */
-
-/* Bit masks for PORTA_MUX - PORTJ_MUX */
-
-#define PxM0 0x3 /* GPIO Mux 0 */
-#define PxM1 0xc /* GPIO Mux 1 */
-#define PxM2 0x30 /* GPIO Mux 2 */
-#define PxM3 0xc0 /* GPIO Mux 3 */
-#define PxM4 0x300 /* GPIO Mux 4 */
-#define PxM5 0xc00 /* GPIO Mux 5 */
-#define PxM6 0x3000 /* GPIO Mux 6 */
-#define PxM7 0xc000 /* GPIO Mux 7 */
-#define PxM8 0x30000 /* GPIO Mux 8 */
-#define PxM9 0xc0000 /* GPIO Mux 9 */
-#define PxM10 0x300000 /* GPIO Mux 10 */
-#define PxM11 0xc00000 /* GPIO Mux 11 */
-#define PxM12 0x3000000 /* GPIO Mux 12 */
-#define PxM13 0xc000000 /* GPIO Mux 13 */
-#define PxM14 0x30000000 /* GPIO Mux 14 */
-#define PxM15 0xc0000000 /* GPIO Mux 15 */
-
-
-/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
-
-#define IB0 0x1 /* Interrupt Bit 0 */
-#define IB1 0x2 /* Interrupt Bit 1 */
-#define IB2 0x4 /* Interrupt Bit 2 */
-#define IB3 0x8 /* Interrupt Bit 3 */
-#define IB4 0x10 /* Interrupt Bit 4 */
-#define IB5 0x20 /* Interrupt Bit 5 */
-#define IB6 0x40 /* Interrupt Bit 6 */
-#define IB7 0x80 /* Interrupt Bit 7 */
-#define IB8 0x100 /* Interrupt Bit 8 */
-#define IB9 0x200 /* Interrupt Bit 9 */
-#define IB10 0x400 /* Interrupt Bit 10 */
-#define IB11 0x800 /* Interrupt Bit 11 */
-#define IB12 0x1000 /* Interrupt Bit 12 */
-#define IB13 0x2000 /* Interrupt Bit 13 */
-#define IB14 0x4000 /* Interrupt Bit 14 */
-#define IB15 0x8000 /* Interrupt Bit 15 */
-
-/* Bit masks for TIMERx_CONFIG */
-
-#define TMODE 0x3 /* Timer Mode */
-#define PULSE_HI 0x4 /* Pulse Polarity */
-#define PERIOD_CNT 0x8 /* Period Count */
-#define IRQ_ENA 0x10 /* Interrupt Request Enable */
-#define TIN_SEL 0x20 /* Timer Input Select */
-#define OUT_DIS 0x40 /* Output Pad Disable */
-#define CLK_SEL 0x80 /* Timer Clock Select */
-#define TOGGLE_HI 0x100 /* Toggle Mode */
-#define EMU_RUN 0x200 /* Emulation Behavior Select */
-#define ERR_TYP 0xc000 /* Error Type */
-
-/* Bit masks for TIMER_ENABLE0 */
-
-#define TIMEN0 0x1 /* Timer 0 Enable */
-#define TIMEN1 0x2 /* Timer 1 Enable */
-#define TIMEN2 0x4 /* Timer 2 Enable */
-#define TIMEN3 0x8 /* Timer 3 Enable */
-#define TIMEN4 0x10 /* Timer 4 Enable */
-#define TIMEN5 0x20 /* Timer 5 Enable */
-#define TIMEN6 0x40 /* Timer 6 Enable */
-#define TIMEN7 0x80 /* Timer 7 Enable */
-
-/* Bit masks for TIMER_DISABLE0 */
-
-#define TIMDIS0 0x1 /* Timer 0 Disable */
-#define TIMDIS1 0x2 /* Timer 1 Disable */
-#define TIMDIS2 0x4 /* Timer 2 Disable */
-#define TIMDIS3 0x8 /* Timer 3 Disable */
-#define TIMDIS4 0x10 /* Timer 4 Disable */
-#define TIMDIS5 0x20 /* Timer 5 Disable */
-#define TIMDIS6 0x40 /* Timer 6 Disable */
-#define TIMDIS7 0x80 /* Timer 7 Disable */
-
-/* Bit masks for TIMER_STATUS0 */
-
-#define TIMIL0 0x1 /* Timer 0 Interrupt */
-#define TIMIL1 0x2 /* Timer 1 Interrupt */
-#define TIMIL2 0x4 /* Timer 2 Interrupt */
-#define TIMIL3 0x8 /* Timer 3 Interrupt */
-#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
-#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
-#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
-#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
-#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
-#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
-#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
-#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
-#define TIMIL4 0x10000 /* Timer 4 Interrupt */
-#define TIMIL5 0x20000 /* Timer 5 Interrupt */
-#define TIMIL6 0x40000 /* Timer 6 Interrupt */
-#define TIMIL7 0x80000 /* Timer 7 Interrupt */
-#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
-#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
-#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
-#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
-#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
-#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
-#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
-#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define EMUDABL 0x1 /* Emulation Disable. */
-#define RSTDABL 0x2 /* Reset Disable */
-#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
-#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
-#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
-#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
-#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
-#define EMUOVR 0x4000 /* Emulation Override */
-#define OTPSEN 0x8000 /* OTP Secrets Enable. */
-#define L2DABL 0x70000 /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define SECURE0 0x1 /* SECURE 0 */
-#define SECURE1 0x2 /* SECURE 1 */
-#define SECURE2 0x4 /* SECURE 2 */
-#define SECURE3 0x8 /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-
-#define SECMODE 0x3 /* Secured Mode Control State */
-#define NMI 0x4 /* Non Maskable Interrupt */
-#define AFVALID 0x8 /* Authentication Firmware Valid */
-#define AFEXIT 0x10 /* Authentication Firmware Exit */
-#define SECSTAT 0xe0 /* Secure Status */
-
-/* SWRST Masks */
-#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
-#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* Bit masks for EPPIx_STATUS */
-
-#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
-#define YFIFO_ERR 0x2 /* Luma FIFO Error */
-#define LTERR_OVR 0x4 /* Line Track Overflow */
-#define LTERR_UNDR 0x8 /* Line Track Underflow */
-#define FTERR_OVR 0x10 /* Frame Track Overflow */
-#define FTERR_UNDR 0x20 /* Frame Track Underflow */
-#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
-#define DMA1URQ 0x80 /* DMA1 Urgent Request */
-#define DMA0URQ 0x100 /* DMA0 Urgent Request */
-#define ERR_DET 0x4000 /* Preamble Error Detected */
-#define FLD 0x8000 /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-
-#define EPPI_EN 0x1 /* Enable */
-#define EPPI_DIR 0x2 /* Direction */
-#define XFR_TYPE 0xc /* Operating Mode */
-#define FS_CFG 0x30 /* Frame Sync Configuration */
-#define FLD_SEL 0x40 /* Field Select/Trigger */
-#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
-#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
-#define ICLKGEN 0x200 /* Internal Clock Generation */
-#define IFSGEN 0x400 /* Internal Frame Sync Generation */
-#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
-#define POLS 0x6000 /* Frame Sync Polarity */
-#define DLENGTH 0x38000 /* Data Length */
-#define SKIP_EN 0x40000 /* Skip Enable */
-#define SKIP_EO 0x80000 /* Skip Even or Odd */
-#define PACKEN 0x100000 /* Packing/Unpacking Enable */
-#define SWAPEN 0x200000 /* Swap Enable */
-#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
-#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
-#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
-#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
-#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
-#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
-#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
-
-#define DLEN_8 (0 << 15) /* 000 - 8 bits */
-#define DLEN_10 (1 << 15) /* 001 - 10 bits */
-#define DLEN_12 (2 << 15) /* 010 - 12 bits */
-#define DLEN_14 (3 << 15) /* 011 - 14 bits */
-#define DLEN_16 (4 << 15) /* 100 - 16 bits */
-#define DLEN_18 (5 << 15) /* 101 - 18 bits */
-#define DLEN_24 (6 << 15) /* 110 - 24 bits */
-
-
-/* Bit masks for EPPIx_FS2W_LVB */
-
-#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
-#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
-#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
-#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-
-#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
-#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-
-#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
-#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
-#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
-#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-
-/* ******************************************* */
-/* MULTI BIT MACRO ENUMERATIONS */
-/* ******************************************* */
-
-/* BCODE bit field options (SYSCFG register) */
-
-#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
-#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
-#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
-#define BCODE_NOBOOT 0x0030 /* always perform full boot */
-
-/* TMODE in TIMERx_CONFIG bit field options */
-
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-
-/* PINTx Register Bit Definitions */
-
-#define PIQ0 0x00000001
-#define PIQ1 0x00000002
-#define PIQ2 0x00000004
-#define PIQ3 0x00000008
-
-#define PIQ4 0x00000010
-#define PIQ5 0x00000020
-#define PIQ6 0x00000040
-#define PIQ7 0x00000080
-
-#define PIQ8 0x00000100
-#define PIQ9 0x00000200
-#define PIQ10 0x00000400
-#define PIQ11 0x00000800
-
-#define PIQ12 0x00001000
-#define PIQ13 0x00002000
-#define PIQ14 0x00004000
-#define PIQ15 0x00008000
-
-#define PIQ16 0x00010000
-#define PIQ17 0x00020000
-#define PIQ18 0x00040000
-#define PIQ19 0x00080000
-
-#define PIQ20 0x00100000
-#define PIQ21 0x00200000
-#define PIQ22 0x00400000
-#define PIQ23 0x00800000
-
-#define PIQ24 0x01000000
-#define PIQ25 0x02000000
-#define PIQ26 0x04000000
-#define PIQ27 0x08000000
-
-#define PIQ28 0x10000000
-#define PIQ29 0x20000000
-#define PIQ30 0x40000000
-#define PIQ31 0x80000000
-
-/* Port Muxing Bit Fields for PORTx_MUX Registers */
-
-#define MUX0 0x00000003
-#define MUX0_0 0x00000000
-#define MUX0_1 0x00000001
-#define MUX0_2 0x00000002
-#define MUX0_3 0x00000003
-
-#define MUX1 0x0000000C
-#define MUX1_0 0x00000000
-#define MUX1_1 0x00000004
-#define MUX1_2 0x00000008
-#define MUX1_3 0x0000000C
-
-#define MUX2 0x00000030
-#define MUX2_0 0x00000000
-#define MUX2_1 0x00000010
-#define MUX2_2 0x00000020
-#define MUX2_3 0x00000030
-
-#define MUX3 0x000000C0
-#define MUX3_0 0x00000000
-#define MUX3_1 0x00000040
-#define MUX3_2 0x00000080
-#define MUX3_3 0x000000C0
-
-#define MUX4 0x00000300
-#define MUX4_0 0x00000000
-#define MUX4_1 0x00000100
-#define MUX4_2 0x00000200
-#define MUX4_3 0x00000300
-
-#define MUX5 0x00000C00
-#define MUX5_0 0x00000000
-#define MUX5_1 0x00000400
-#define MUX5_2 0x00000800
-#define MUX5_3 0x00000C00
-
-#define MUX6 0x00003000
-#define MUX6_0 0x00000000
-#define MUX6_1 0x00001000
-#define MUX6_2 0x00002000
-#define MUX6_3 0x00003000
-
-#define MUX7 0x0000C000
-#define MUX7_0 0x00000000
-#define MUX7_1 0x00004000
-#define MUX7_2 0x00008000
-#define MUX7_3 0x0000C000
-
-#define MUX8 0x00030000
-#define MUX8_0 0x00000000
-#define MUX8_1 0x00010000
-#define MUX8_2 0x00020000
-#define MUX8_3 0x00030000
-
-#define MUX9 0x000C0000
-#define MUX9_0 0x00000000
-#define MUX9_1 0x00040000
-#define MUX9_2 0x00080000
-#define MUX9_3 0x000C0000
-
-#define MUX10 0x00300000
-#define MUX10_0 0x00000000
-#define MUX10_1 0x00100000
-#define MUX10_2 0x00200000
-#define MUX10_3 0x00300000
-
-#define MUX11 0x00C00000
-#define MUX11_0 0x00000000
-#define MUX11_1 0x00400000
-#define MUX11_2 0x00800000
-#define MUX11_3 0x00C00000
-
-#define MUX12 0x03000000
-#define MUX12_0 0x00000000
-#define MUX12_1 0x01000000
-#define MUX12_2 0x02000000
-#define MUX12_3 0x03000000
-
-#define MUX13 0x0C000000
-#define MUX13_0 0x00000000
-#define MUX13_1 0x04000000
-#define MUX13_2 0x08000000
-#define MUX13_3 0x0C000000
-
-#define MUX14 0x30000000
-#define MUX14_0 0x00000000
-#define MUX14_1 0x10000000
-#define MUX14_2 0x20000000
-#define MUX14_3 0x30000000
-
-#define MUX15 0xC0000000
-#define MUX15_0 0x00000000
-#define MUX15_1 0x40000000
-#define MUX15_2 0x80000000
-#define MUX15_3 0xC0000000
-
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
- ((((b15)&3) << 30) | \
- (((b14)&3) << 28) | \
- (((b13)&3) << 26) | \
- (((b12)&3) << 24) | \
- (((b11)&3) << 22) | \
- (((b10)&3) << 20) | \
- (((b9) &3) << 18) | \
- (((b8) &3) << 16) | \
- (((b7) &3) << 14) | \
- (((b6) &3) << 12) | \
- (((b5) &3) << 10) | \
- (((b4) &3) << 8) | \
- (((b3) &3) << 6) | \
- (((b2) &3) << 4) | \
- (((b1) &3) << 2) | \
- (((b0) &3)))
-
-/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
-
-#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
-#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
-#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
-#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
-#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
-#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
-#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
-#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
-#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
-#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
-#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
-#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
-
-/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
-
-#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
-#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
-#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
-#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
-#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
-#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
-#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
-#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
-
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
-#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
-#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
-#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
-#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
-#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
-#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
-#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
-
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
-
-#endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
deleted file mode 100644
index 1a1091b071fd..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_RX 0
-#define CH_SPORT0_TX 1
-#define CH_SPORT1_RX 2
-#define CH_SPORT1_TX 3
-#define CH_SPI0 4
-#define CH_SPI1 5
-#define CH_UART0_RX 6
-#define CH_UART0_TX 7
-#define CH_UART1_RX 8
-#define CH_UART1_TX 9
-#define CH_ATAPI_RX 10
-#define CH_ATAPI_TX 11
-#define CH_EPPI0 12
-#define CH_EPPI1 13
-#define CH_EPPI2 14
-#define CH_PIXC_IMAGE 15
-#define CH_PIXC_OVERLAY 16
-#define CH_PIXC_OUTPUT 17
-#define CH_SPORT2_RX 18
-#define CH_SPORT2_TX 19
-#define CH_SPORT3_RX 20
-#define CH_SPORT3_TX 21
-#define CH_SDH 22
-#define CH_NFC 22
-#define CH_SPI2 23
-
-#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
-#define CH_UART2_RX 13
-#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
-#define CH_UART2_TX 14
-#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
-#else /* Default USE SPORT2's DMA Channel */
-#define CH_UART2_RX 18
-#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
-#define CH_UART2_TX 19
-#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
-#endif
-
-#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
-#define CH_UART3_RX 15
-#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
-#define CH_UART3_TX 16
-#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
-#else /* Default USE SPORT3's DMA Channel */
-#define CH_UART3_RX 20
-#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
-#define CH_UART3_TX 21
-#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
-#endif
-
-#define CH_MEM_STREAM0_DEST 24
-#define CH_MEM_STREAM0_SRC 25
-#define CH_MEM_STREAM1_DEST 26
-#define CH_MEM_STREAM1_SRC 27
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-
-#define MAX_DMA_CHANNELS 32
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
deleted file mode 100644
index 006da1edcf84..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31 /* N/A */
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46 /* N/A */
-#define GPIO_PC15 47 /* N/A */
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-#define GPIO_PH0 112
-#define GPIO_PH1 113
-#define GPIO_PH2 114
-#define GPIO_PH3 115
-#define GPIO_PH4 116
-#define GPIO_PH5 117
-#define GPIO_PH6 118
-#define GPIO_PH7 119
-#define GPIO_PH8 120
-#define GPIO_PH9 121
-#define GPIO_PH10 122
-#define GPIO_PH11 123
-#define GPIO_PH12 124
-#define GPIO_PH13 125
-#define GPIO_PH14 126 /* N/A */
-#define GPIO_PH15 127 /* N/A */
-#define GPIO_PI0 128
-#define GPIO_PI1 129
-#define GPIO_PI2 130
-#define GPIO_PI3 131
-#define GPIO_PI4 132
-#define GPIO_PI5 133
-#define GPIO_PI6 134
-#define GPIO_PI7 135
-#define GPIO_PI8 136
-#define GPIO_PI9 137
-#define GPIO_PI10 138
-#define GPIO_PI11 139
-#define GPIO_PI12 140
-#define GPIO_PI13 141
-#define GPIO_PI14 142
-#define GPIO_PI15 143
-#define GPIO_PJ0 144
-#define GPIO_PJ1 145
-#define GPIO_PJ2 146
-#define GPIO_PJ3 147
-#define GPIO_PJ4 148
-#define GPIO_PJ5 149
-#define GPIO_PJ6 150
-#define GPIO_PJ7 151
-#define GPIO_PJ8 152
-#define GPIO_PJ9 153
-#define GPIO_PJ10 154
-#define GPIO_PJ11 155
-#define GPIO_PJ12 156
-#define GPIO_PJ13 157
-#define GPIO_PJ14 158 /* N/A */
-#define GPIO_PJ15 159 /* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 4
-#define NR_PINTS 160
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned short port_fer;
- unsigned short dummy1;
- unsigned short data;
- unsigned short dummy2;
- unsigned short data_set;
- unsigned short dummy3;
- unsigned short data_clear;
- unsigned short dummy4;
- unsigned short dir_set;
- unsigned short dummy5;
- unsigned short dir_clear;
- unsigned short dummy6;
- unsigned short inen;
- unsigned short dummy7;
- unsigned int port_mux;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-#include <mach-common/ports-h.h>
-#include <mach-common/ports-i.h>
-#include <mach-common/ports-j.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
deleted file mode 100644
index cf7cb725cfa2..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF548_IRQ_H_
-#define _BF548_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (3 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
-#define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
-#define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
-#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
-#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
-#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
-#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
-#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
-#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
-#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
-#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
-#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
-#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
-#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
-#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
-#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
-#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
-#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
-#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
-#define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
-#define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
-#define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
-#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
-#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
-#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
-#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
-#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
-#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
-#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
-#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
-#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
-#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
-#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
-#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
-#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
-#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
-#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
-#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
-#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
-#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
-#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
-#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
-#define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
-#define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
-#define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
-#define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
-#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
-#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
-#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
-#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
-#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
-#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
-#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
-#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
-#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
-#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
-#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
-#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
-#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
-#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
-
-#define SYS_IRQS IRQ_PINT3
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
-#define IRQ_PH0 BFIN_PH_IRQ(0)
-#define IRQ_PH1 BFIN_PH_IRQ(1)
-#define IRQ_PH2 BFIN_PH_IRQ(2)
-#define IRQ_PH3 BFIN_PH_IRQ(3)
-#define IRQ_PH4 BFIN_PH_IRQ(4)
-#define IRQ_PH5 BFIN_PH_IRQ(5)
-#define IRQ_PH6 BFIN_PH_IRQ(6)
-#define IRQ_PH7 BFIN_PH_IRQ(7)
-#define IRQ_PH8 BFIN_PH_IRQ(8)
-#define IRQ_PH9 BFIN_PH_IRQ(9)
-#define IRQ_PH10 BFIN_PH_IRQ(10)
-#define IRQ_PH11 BFIN_PH_IRQ(11)
-#define IRQ_PH12 BFIN_PH_IRQ(12)
-#define IRQ_PH13 BFIN_PH_IRQ(13)
-#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
-#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
-
-#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
-#define IRQ_PI0 BFIN_PI_IRQ(0)
-#define IRQ_PI1 BFIN_PI_IRQ(1)
-#define IRQ_PI2 BFIN_PI_IRQ(2)
-#define IRQ_PI3 BFIN_PI_IRQ(3)
-#define IRQ_PI4 BFIN_PI_IRQ(4)
-#define IRQ_PI5 BFIN_PI_IRQ(5)
-#define IRQ_PI6 BFIN_PI_IRQ(6)
-#define IRQ_PI7 BFIN_PI_IRQ(7)
-#define IRQ_PI8 BFIN_PI_IRQ(8)
-#define IRQ_PI9 BFIN_PI_IRQ(9)
-#define IRQ_PI10 BFIN_PI_IRQ(10)
-#define IRQ_PI11 BFIN_PI_IRQ(11)
-#define IRQ_PI12 BFIN_PI_IRQ(12)
-#define IRQ_PI13 BFIN_PI_IRQ(13)
-#define IRQ_PI14 BFIN_PI_IRQ(14)
-#define IRQ_PI15 BFIN_PI_IRQ(15)
-
-#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
-#define IRQ_PJ0 BFIN_PJ_IRQ(0)
-#define IRQ_PJ1 BFIN_PJ_IRQ(1)
-#define IRQ_PJ2 BFIN_PJ_IRQ(2)
-#define IRQ_PJ3 BFIN_PJ_IRQ(3)
-#define IRQ_PJ4 BFIN_PJ_IRQ(4)
-#define IRQ_PJ5 BFIN_PJ_IRQ(5)
-#define IRQ_PJ6 BFIN_PJ_IRQ(6)
-#define IRQ_PJ7 BFIN_PJ_IRQ(7)
-#define IRQ_PJ8 BFIN_PJ_IRQ(8)
-#define IRQ_PJ9 BFIN_PJ_IRQ(9)
-#define IRQ_PJ10 BFIN_PJ_IRQ(10)
-#define IRQ_PJ11 BFIN_PJ_IRQ(11)
-#define IRQ_PJ12 BFIN_PJ_IRQ(12)
-#define IRQ_PJ13 BFIN_PJ_IRQ(13)
-#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
-#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PJ15 + 1)
-
-/* For compatibility reasons with existing code */
-
-#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
-#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
-#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
-#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
-#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR IRQ_UART1_ERROR
-#define IRQ_UART2_ERR IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
-#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
-#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
-#define IRQ_UART3_ERR IRQ_UART3_ERROR
-#define IRQ_HOST_ERR IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
-#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMAC0_ERR_POS 4
-#define IRQ_EPPI0_ERR_POS 8
-#define IRQ_SPORT0_ERR_POS 12
-#define IRQ_SPORT1_ERR_POS 16
-#define IRQ_SPI0_ERR_POS 20
-#define IRQ_UART0_ERR_POS 24
-#define IRQ_RTC_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_EPPI0_POS 0
-#define IRQ_SPORT0_RX_POS 4
-#define IRQ_SPORT0_TX_POS 8
-#define IRQ_SPORT1_RX_POS 12
-#define IRQ_SPORT1_TX_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER8_POS 0
-#define IRQ_TIMER9_POS 4
-#define IRQ_TIMER10_POS 8
-#define IRQ_PINT0_POS 12
-#define IRQ_PINT1_POS 16
-#define IRQ_MDMAS0_POS 20
-#define IRQ_MDMAS1_POS 24
-#define IRQ_WATCH_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMAC1_ERR_POS 0
-#define IRQ_SPORT2_ERR_POS 4
-#define IRQ_SPORT3_ERR_POS 8
-#define IRQ_MXVR_DATA_POS 12
-#define IRQ_SPI1_ERR_POS 16
-#define IRQ_SPI2_ERR_POS 20
-#define IRQ_UART1_ERR_POS 24
-#define IRQ_UART2_ERR_POS 28
-
-/* IAR4 BIT FILEDS */
-#define IRQ_CAN0_ERR_POS 0
-#define IRQ_SPORT2_RX_POS 4
-#define IRQ_UART2_RX_POS 4
-#define IRQ_SPORT2_TX_POS 8
-#define IRQ_UART2_TX_POS 8
-#define IRQ_SPORT3_RX_POS 12
-#define IRQ_UART3_RX_POS 12
-#define IRQ_SPORT3_TX_POS 16
-#define IRQ_UART3_TX_POS 16
-#define IRQ_EPPI1_POS 20
-#define IRQ_EPPI2_POS 24
-#define IRQ_SPI1_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS 0
-#define IRQ_UART1_RX_POS 4
-#define IRQ_UART1_TX_POS 8
-#define IRQ_ATAPI_RX_POS 12
-#define IRQ_ATAPI_TX_POS 16
-#define IRQ_TWI0_POS 20
-#define IRQ_TWI1_POS 24
-#define IRQ_CAN0_RX_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN0_TX_POS 0
-#define IRQ_MDMAS2_POS 4
-#define IRQ_MDMAS3_POS 8
-#define IRQ_MXVR_ERR_POS 12
-#define IRQ_MXVR_MSG_POS 16
-#define IRQ_MXVR_PKT_POS 20
-#define IRQ_EPPI1_ERR_POS 24
-#define IRQ_EPPI2_ERR_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_UART3_ERR_POS 0
-#define IRQ_HOST_ERR_POS 4
-#define IRQ_PIXC_ERR_POS 12
-#define IRQ_NFC_ERR_POS 16
-#define IRQ_ATAPI_ERR_POS 20
-#define IRQ_CAN1_ERR_POS 24
-#define IRQ_HS_DMA_ERR_POS 28
-
-/* IAR8 BIT FIELDS */
-#define IRQ_PIXC_IN0_POS 0
-#define IRQ_PIXC_IN1_POS 4
-#define IRQ_PIXC_OUT_POS 8
-#define IRQ_SDH_POS 12
-#define IRQ_CNT_POS 16
-#define IRQ_KEY_POS 20
-#define IRQ_CAN1_RX_POS 24
-#define IRQ_CAN1_TX_POS 28
-
-/* IAR9 BIT FIELDS */
-#define IRQ_SDH_MASK0_POS 0
-#define IRQ_SDH_MASK1_POS 4
-#define IRQ_USB_INT0_POS 12
-#define IRQ_USB_INT1_POS 16
-#define IRQ_USB_INT2_POS 20
-#define IRQ_USB_DMA_POS 24
-#define IRQ_OTPSEC_POS 28
-
-/* IAR10 BIT FIELDS */
-#define IRQ_TIMER0_POS 24
-#define IRQ_TIMER1_POS 28
-
-/* IAR11 BIT FIELDS */
-#define IRQ_TIMER2_POS 0
-#define IRQ_TIMER3_POS 4
-#define IRQ_TIMER4_POS 8
-#define IRQ_TIMER5_POS 12
-#define IRQ_TIMER6_POS 16
-#define IRQ_TIMER7_POS 20
-#define IRQ_PINT2_POS 24
-#define IRQ_PINT3_POS 28
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/mem_map.h b/arch/blackfin/mach-bf548/include/mach/mem_map.h
deleted file mode 100644
index caac2dfb41eb..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/mem_map.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * BF548 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x1000
-
-/* L1 Instruction ROM */
-
-#define L1_ROM_START 0xFFA14000
-#define L1_ROM_LENGTH 0x10000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF548 processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-#define L1_CODE_LENGTH 0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#if defined(CONFIG_BF542)
-# define L2_LENGTH 0
-#elif defined(CONFIG_BF544)
-# define L2_LENGTH 0x10000
-#else
-# define L2_LENGTH 0x20000
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
deleted file mode 100644
index 94cca674d835..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
deleted file mode 100644
index d9f8632d7d09..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-# define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-# define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-# define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-# define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-# define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-# define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-# define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-# define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-# define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-# define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-# define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-# define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-# define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-# define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-# define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#else
-# define P_ATAPI_D0A (P_DONTCARE)
-# define P_ATAPI_D1A (P_DONTCARE)
-# define P_ATAPI_D2A (P_DONTCARE)
-# define P_ATAPI_D3A (P_DONTCARE)
-# define P_ATAPI_D4A (P_DONTCARE)
-# define P_ATAPI_D5A (P_DONTCARE)
-# define P_ATAPI_D6A (P_DONTCARE)
-# define P_ATAPI_D7A (P_DONTCARE)
-# define P_ATAPI_D8A (P_DONTCARE)
-# define P_ATAPI_D9A (P_DONTCARE)
-# define P_ATAPI_D10A (P_DONTCARE)
-# define P_ATAPI_D11A (P_DONTCARE)
-# define P_ATAPI_D12A (P_DONTCARE)
-# define P_ATAPI_D13A (P_DONTCARE)
-# define P_ATAPI_D14A (P_DONTCARE)
-# define P_ATAPI_D15A (P_DONTCARE)
-#endif
-
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT
-# define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-# define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-# define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#else
-# define P_ATAPI_A0A (P_DONTCARE)
-# define P_ATAPI_A1A (P_DONTCARE)
-# define P_ATAPI_A2A (P_DONTCARE)
-#endif
-#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0 (P_DONTCARE)
-#define P_NAND_D1 (P_DONTCARE)
-#define P_NAND_D2 (P_DONTCARE)
-#define P_NAND_D3 (P_DONTCARE)
-#define P_NAND_D4 (P_DONTCARE)
-#define P_NAND_D5 (P_DONTCARE)
-#define P_NAND_D6 (P_DONTCARE)
-#define P_NAND_D7 (P_DONTCARE)
-#define P_NAND_WE (P_DONTCARE)
-#define P_NAND_RE (P_DONTCARE)
-#define P_NAND_CLE (P_DONTCARE)
-#define P_NAND_ALE (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
deleted file mode 100644
index 48dd3a4bc4a5..000000000000
--- a/arch/blackfin/mach-bf548/ints-priority.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
- ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
- ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
- ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
- ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
- ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
- ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
- ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
- ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
- ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
- ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
- ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
- ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
- ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
- ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
- ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
- ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
- ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
- ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
- ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
- ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
- ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
- ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
- ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
- ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
- ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
- ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
- ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
- ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
- ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
- ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
- ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
- ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
- ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
- ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
- ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
- ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
- ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
- ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
- ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
- ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
- ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
- ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
- ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
- ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
- ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
- ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
- ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
- ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
- ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
- ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
-
- bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
- ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
- ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
- ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
- ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
- ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
- ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
-
- bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
- ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
- ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
- ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
- ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
- ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
- ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
-
- bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
-
- bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
- ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
- ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf561/Kconfig b/arch/blackfin/mach-bf561/Kconfig
deleted file mode 100644
index 059c3cbdb5ec..000000000000
--- a/arch/blackfin/mach-bf561/Kconfig
+++ /dev/null
@@ -1,213 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if (BF561)
-
-source "arch/blackfin/mach-bf561/boards/Kconfig"
-
-menu "BF561 Specific Configuration"
-
-if (!SMP)
-
-comment "Core B Support"
-
-config BF561_COREB
- bool "Enable Core B loader"
- default y
-
-endif
-
-comment "Interrupt Priority Assignment"
-
-menu "Priority"
-
-config IRQ_PLL_WAKEUP
- int "PLL Wakeup Interrupt"
- default 7
-config IRQ_DMA1_ERROR
- int "DMA1 Error (generic)"
- default 7
-config IRQ_DMA2_ERROR
- int "DMA2 Error (generic)"
- default 7
-config IRQ_IMDMA_ERROR
- int "IMDMA Error (generic)"
- default 7
-config IRQ_PPI0_ERROR
- int "PPI0 Error Interrupt"
- default 7
-config IRQ_PPI1_ERROR
- int "PPI1 Error Interrupt"
- default 7
-config IRQ_SPORT0_ERROR
- int "SPORT0 Error Interrupt"
- default 7
-config IRQ_SPORT1_ERROR
- int "SPORT1 Error Interrupt"
- default 7
-config IRQ_SPI_ERROR
- int "SPI Error Interrupt"
- default 7
-config IRQ_UART_ERROR
- int "UART Error Interrupt"
- default 7
-config IRQ_RESERVED_ERROR
- int "Reserved Interrupt"
- default 7
-config IRQ_DMA1_0
- int "DMA1 0 Interrupt(PPI1)"
- default 8
-config IRQ_DMA1_1
- int "DMA1 1 Interrupt(PPI2)"
- default 8
-config IRQ_DMA1_2
- int "DMA1 2 Interrupt"
- default 8
-config IRQ_DMA1_3
- int "DMA1 3 Interrupt"
- default 8
-config IRQ_DMA1_4
- int "DMA1 4 Interrupt"
- default 8
-config IRQ_DMA1_5
- int "DMA1 5 Interrupt"
- default 8
-config IRQ_DMA1_6
- int "DMA1 6 Interrupt"
- default 8
-config IRQ_DMA1_7
- int "DMA1 7 Interrupt"
- default 8
-config IRQ_DMA1_8
- int "DMA1 8 Interrupt"
- default 8
-config IRQ_DMA1_9
- int "DMA1 9 Interrupt"
- default 8
-config IRQ_DMA1_10
- int "DMA1 10 Interrupt"
- default 8
-config IRQ_DMA1_11
- int "DMA1 11 Interrupt"
- default 8
-config IRQ_DMA2_0
- int "DMA2 0 (SPORT0 RX)"
- default 9
-config IRQ_DMA2_1
- int "DMA2 1 (SPORT0 TX)"
- default 9
-config IRQ_DMA2_2
- int "DMA2 2 (SPORT1 RX)"
- default 9
-config IRQ_DMA2_3
- int "DMA2 3 (SPORT2 TX)"
- default 9
-config IRQ_DMA2_4
- int "DMA2 4 (SPI)"
- default 9
-config IRQ_DMA2_5
- int "DMA2 5 (UART RX)"
- default 9
-config IRQ_DMA2_6
- int "DMA2 6 (UART TX)"
- default 9
-config IRQ_DMA2_7
- int "DMA2 7 Interrupt"
- default 9
-config IRQ_DMA2_8
- int "DMA2 8 Interrupt"
- default 9
-config IRQ_DMA2_9
- int "DMA2 9 Interrupt"
- default 9
-config IRQ_DMA2_10
- int "DMA2 10 Interrupt"
- default 9
-config IRQ_DMA2_11
- int "DMA2 11 Interrupt"
- default 9
-config IRQ_TIMER0
- int "TIMER 0 Interrupt"
- default 7 if TICKSOURCE_GPTMR0
- default 8
-config IRQ_TIMER1
- int "TIMER 1 Interrupt"
- default 10
-config IRQ_TIMER2
- int "TIMER 2 Interrupt"
- default 10
-config IRQ_TIMER3
- int "TIMER 3 Interrupt"
- default 10
-config IRQ_TIMER4
- int "TIMER 4 Interrupt"
- default 10
-config IRQ_TIMER5
- int "TIMER 5 Interrupt"
- default 10
-config IRQ_TIMER6
- int "TIMER 6 Interrupt"
- default 10
-config IRQ_TIMER7
- int "TIMER 7 Interrupt"
- default 10
-config IRQ_TIMER8
- int "TIMER 8 Interrupt"
- default 10
-config IRQ_TIMER9
- int "TIMER 9 Interrupt"
- default 10
-config IRQ_TIMER10
- int "TIMER 10 Interrupt"
- default 10
-config IRQ_TIMER11
- int "TIMER 11 Interrupt"
- default 10
-config IRQ_PROG0_INTA
- int "Programmable Flags0 A (8)"
- default 11
-config IRQ_PROG0_INTB
- int "Programmable Flags0 B (8)"
- default 11
-config IRQ_PROG1_INTA
- int "Programmable Flags1 A (8)"
- default 11
-config IRQ_PROG1_INTB
- int "Programmable Flags1 B (8)"
- default 11
-config IRQ_PROG2_INTA
- int "Programmable Flags2 A (8)"
- default 11
-config IRQ_PROG2_INTB
- int "Programmable Flags2 B (8)"
- default 11
-config IRQ_DMA1_WRRD0
- int "MDMA1 0 write/read INT"
- default 8
-config IRQ_DMA1_WRRD1
- int "MDMA1 1 write/read INT"
- default 8
-config IRQ_DMA2_WRRD0
- int "MDMA2 0 write/read INT"
- default 9
-config IRQ_DMA2_WRRD1
- int "MDMA2 1 write/read INT"
- default 9
-config IRQ_IMDMA_WRRD0
- int "IMDMA 0 write/read INT"
- default 12
-config IRQ_IMDMA_WRRD1
- int "IMDMA 1 write/read INT"
- default 12
-config IRQ_WDTIMER
- int "Watch Dog Timer"
- default 13
-
- help
- Enter the priority numbers between 7-13 ONLY. Others are Reserved.
- This applies to all the above. It is not recommended to assign the
- highest priority number 7 to UART or any other device.
-
-endmenu
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
deleted file mode 100644
index b34029718318..000000000000
--- a/arch/blackfin/mach-bf561/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# arch/blackfin/mach-bf561/Makefile
-#
-
-obj-y := ints-priority.o dma.o
-
-obj-$(CONFIG_BF561_COREB) += coreb.o
-obj-$(CONFIG_SMP) += smp.o secondary.o atomic.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
deleted file mode 100644
index 1e2989c5d6b2..000000000000
--- a/arch/blackfin/mach-bf561/atomic.S
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/asm-offsets.h>
-#include <asm/rwlock.h>
-#include <asm/cplb.h>
-
-.text
-
-.macro coreslot_loadaddr reg:req
- \reg\().l = _corelock;
- \reg\().h = _corelock;
-.endm
-
-.macro safe_testset addr:req, scratch:req
-#if ANOMALY_05000477
- cli \scratch;
- testset (\addr);
- sti \scratch;
-#else
- testset (\addr);
-#endif
-.endm
-
-/*
- * r0 = address of atomic data to flush and invalidate (32bit).
- *
- * Clear interrupts and return the old mask.
- * We assume that no atomic data can span cachelines.
- *
- * Clobbers: r2:0, p0
- */
-ENTRY(_get_core_lock)
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock;
- SSYNC(r2);
- jump .Lretry_corelock
-.Ldone_corelock:
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- rts;
-ENDPROC(_get_core_lock)
-
-/*
- * r0 = address of atomic data in uncacheable memory region (32bit).
- *
- * Clear interrupts and return the old mask.
- *
- * Clobbers: r0, p0
- */
-ENTRY(_get_core_lock_noflush)
- cli r0;
- coreslot_loadaddr p0;
-.Lretry_corelock_noflush:
- safe_testset p0, r2;
- if cc jump .Ldone_corelock_noflush;
- SSYNC(r2);
- jump .Lretry_corelock_noflush
-.Ldone_corelock_noflush:
- /*
- * SMP kgdb runs into dead loop without NOP here, when one core
- * single steps over get_core_lock_noflush and the other executes
- * get_core_lock as a slave node.
- */
- nop;
- CSYNC(r2);
- rts;
-ENDPROC(_get_core_lock_noflush)
-
-/*
- * r0 = interrupt mask to restore.
- * r1 = address of atomic data to flush and invalidate (32bit).
- *
- * Interrupts are masked on entry (see _get_core_lock).
- * Clobbers: r2:0, p0
- */
-ENTRY(_put_core_lock)
- /* Write-through cache assumed, so no flush needed here. */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
- SSYNC(r2);
- sti r0;
- rts;
-ENDPROC(_put_core_lock)
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-
-ENTRY(___raw_smp_mark_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Set bit of other cores in barrier mask. Don't change current core bit.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- r7 = ~r6;
- cc = r5 == 0;
- if cc jump 1f;
- r7 = r7 | r6;
-1:
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_mark_barrier_asm)
-
-ENTRY(___raw_smp_check_barrier_asm)
- [--sp] = rets;
- [--sp] = ( r7:5 );
- [--sp] = r0;
- [--sp] = p1;
- [--sp] = p0;
- call _get_core_lock_noflush;
-
- /*
- * Calculate current core mask
- */
- GET_CPUID(p1, r7);
- r6 = 1;
- r6 <<= r7;
-
- /*
- * Clear current core bit in barrier mask if it is set.
- */
- p1.l = _barrier_mask;
- p1.h = _barrier_mask;
- r7 = [p1];
- r5 = r7 & r6;
- cc = r5 == 0;
- if cc jump 1f;
- r6 = ~r6;
- r7 = r7 & r6;
- [p1] = r7;
- SSYNC(r2);
-
- call _put_core_lock;
-
- /*
- * Invalidate the entire D-cache of current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
- jump 2f;
-1:
- call _put_core_lock;
-2:
- p0 = [sp++];
- p1 = [sp++];
- r0 = [sp++];
- ( r7:5 ) = [sp++];
- rets = [sp++];
- rts;
-ENDPROC(___raw_smp_check_barrier_asm)
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_start_lock_coherent:
-
- [--sp] = rets;
- [--sp] = ( r7:6 );
- r7 = r0;
- p1 = r1;
-
- /*
- * Determine whether the atomic data was previously
- * owned by another CPU (=r6).
- */
- GET_CPUID(p0, r2);
- r1 = 1;
- r1 <<= r2;
- r2 = ~r1;
-
- r1 = [p1];
- r1 >>= 28; /* CPU fingerprints are stored in the high nibble. */
- r6 = r1 & r2;
- r1 = [p1];
- r1 <<= 4;
- r1 >>= 4;
- [p1] = r1;
-
- /*
- * Release the core lock now, but keep IRQs disabled while we are
- * performing the remaining housekeeping chores for the current CPU.
- */
- coreslot_loadaddr p0;
- r1 = 0;
- [p0] = r1;
-
- /*
- * If another CPU has owned the same atomic section before us,
- * then our D-cached copy of the shared data protected by the
- * current spin/write_lock may be obsolete.
- */
- cc = r6 == 0;
- if cc jump .Lcache_synced
-
- /*
- * Invalidate the entire D-cache of the current core.
- */
- sp += -12;
- call _resync_core_dcache
- sp += 12;
-
-.Lcache_synced:
- SSYNC(r2);
- sti r7;
- ( r7:6 ) = [sp++];
- rets = [sp++];
- rts
-
-/*
- * r0 = irqflags
- * r1 = address of atomic data
- *
- * Clobbers: r2:0, p1:0
- */
-_end_lock_coherent:
-
- p1 = r1;
- GET_CPUID(p0, r2);
- r2 += 28;
- r1 = 1;
- r1 <<= r2;
- r2 = [p1];
- r2 = r1 | r2;
- [p1] = r2;
- r1 = p1;
- jump _put_core_lock;
-
-#endif /* __ARCH_SYNC_CORE_DCACHE */
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_is_locked_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- cc = bittst( r3, 0 );
- r3 = cc;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = r3;
- rts;
-ENDPROC(___raw_spin_is_locked_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_lock_asm)
- p1 = r0;
- [--sp] = rets;
-.Lretry_spinlock:
- call _get_core_lock;
- r1 = p1;
- r2 = [p1];
- cc = bittst( r2, 0 );
- if cc jump .Lbusy_spinlock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r3 = p1;
- bitset ( r2, 0 ); /* Raise the lock bit. */
- [p1] = r2;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lbusy_spinlock:
- /* We don't touch the atomic area if busy, so that flush
- will behave like nop in _put_core_lock. */
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- jump .Lretry_spinlock
-ENDPROC(___raw_spin_lock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_spin_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = p1;
- r3 = [p1];
- cc = bittst( r3, 0 );
- if cc jump .Lfailed_trylock
-#ifdef __ARCH_SYNC_CORE_DCACHE
- bitset ( r3, 0 ); /* Raise the lock bit. */
- [p1] = r3;
- call _start_lock_coherent
-#else
- r2 = 1;
- [p1] = r2;
- call _put_core_lock;
-#endif
- r0 = 1;
- rets = [sp++];
- rts;
-.Lfailed_trylock:
- call _put_core_lock;
- r0 = 0;
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_trylock_asm)
-
-/*
- * r0 = &spinlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_spin_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- bitclr ( r2, 0 );
- [p1] = r2;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_spin_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_read_lock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
-.Lrdlock_try:
- r1 = [p1];
- r1 += -1;
- [p1] = r1;
- cc = r1 < 0;
- if cc jump .Lrdlock_failed
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lrdlock_failed:
- r1 += 1;
- [p1] = r1;
-.Lrdlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 < 2;
- if cc jump .Lrdlock_wait;
- jump .Lrdlock_try
-ENDPROC(___raw_read_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- cc = r1 <= 0;
- if cc jump .Lfailed_tryrdlock;
- r1 += -1;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-.Lfailed_tryrdlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_read_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Note: Processing controlled by a reader lock should not have
- * any side-effect on cache issues with the other core, so we
- * just release the core lock and exit (no _end_lock_coherent).
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_read_unlock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 += 1;
- [p1] = r1;
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- rts;
-ENDPROC(___raw_read_unlock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_lock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
-.Lwrlock_try:
- r1 = [p1];
- r1 = r1 - r3;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r2 = r1;
- r2 <<= 4;
- r2 >>= 4;
- cc = r2 == 0;
-#else
- cc = r1 == 0;
-#endif
- if !cc jump .Lwrlock_wait
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-
-.Lwrlock_wait:
- r1 = p1;
- call _put_core_lock;
- SSYNC(r2);
- r0 = p1;
- call _get_core_lock;
- r1 = [p1];
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 <<= 4;
- r1 >>= 4;
-#endif
- cc = r1 == r3;
- if !cc jump .Lwrlock_wait;
- jump .Lwrlock_try
-ENDPROC(___raw_write_lock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_trylock_asm)
- p1 = r0;
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r2.l = lo(RW_LOCK_BIAS);
- r2.h = hi(RW_LOCK_BIAS);
- cc = r1 == r2;
- if !cc jump .Lfailed_trywrlock;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- r1 >>= 28;
- r1 <<= 28;
-#else
- r1 = 0;
-#endif
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _start_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- r0 = 1;
- rts;
-
-.Lfailed_trywrlock:
- r1 = p1;
- call _put_core_lock;
- rets = [sp++];
- r0 = 0;
- rts;
-ENDPROC(___raw_write_trylock_asm)
-
-/*
- * r0 = &rwlock->lock
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_write_unlock_asm)
- p1 = r0;
- r3.l = lo(RW_LOCK_BIAS);
- r3.h = hi(RW_LOCK_BIAS);
- [--sp] = rets;
- call _get_core_lock;
- r1 = [p1];
- r1 = r1 + r3;
- [p1] = r1;
- r1 = p1;
-#ifdef __ARCH_SYNC_CORE_DCACHE
- call _end_lock_coherent
-#else
- call _put_core_lock;
-#endif
- rets = [sp++];
- rts;
-ENDPROC(___raw_write_unlock_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the new value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_add_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r2 = [p1];
- r3 = r3 + r2;
- [p1] = r3;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * ADD a signed value to a 32bit word and return the old value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xadd_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r3 + r2;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_add_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * AND the mask bits from a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_and_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 & r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_and_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * OR the mask bits into a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_or_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 | r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_or_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * XOR the mask bits with a 32bit word and return the old 32bit value
- * atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_xor_asm)
- p1 = r0;
- r3 = r1;
- [--sp] = rets;
- call _get_core_lock;
- r3 = [p1];
- r2 = r2 ^ r3;
- [p1] = r2;
- r1 = p1;
- call _put_core_lock;
- r0 = r3;
- rets = [sp++];
- rts;
-ENDPROC(___raw_atomic_xor_asm)
-
-/*
- * r0 = ptr
- * r1 = mask
- *
- * Perform a logical AND between the mask bits and a 32bit word, and
- * return the masked value. We need this on this architecture in
- * order to invalidate the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_atomic_test_asm)
- p1 = r0;
- r3 = r1;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- r0 = r0 & r3;
- rts;
-ENDPROC(___raw_atomic_test_asm)
-
-/*
- * r0 = ptr
- * r1 = value
- *
- * Swap *ptr with value and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-#define __do_xchg(src, dst) \
- p1 = r0; \
- r3 = r1; \
- [--sp] = rets; \
- call _get_core_lock; \
- r2 = src; \
- dst = r3; \
- r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_xchg_1_asm)
- __do_xchg(b[p1] (z), b[p1])
-ENDPROC(___raw_xchg_1_asm)
-
-ENTRY(___raw_xchg_2_asm)
- __do_xchg(w[p1] (z), w[p1])
-ENDPROC(___raw_xchg_2_asm)
-
-ENTRY(___raw_xchg_4_asm)
- __do_xchg([p1], [p1])
-ENDPROC(___raw_xchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = new
- * r2 = old
- *
- * Swap *ptr with new if *ptr == old and return the previous *ptr
- * value atomically.
- *
- * Clobbers: r3:0, p1:0
- */
-#define __do_cmpxchg(src, dst) \
- [--sp] = rets; \
- [--sp] = r4; \
- p1 = r0; \
- r3 = r1; \
- r4 = r2; \
- call _get_core_lock; \
- r2 = src; \
- cc = r2 == r4; \
- if !cc jump 1f; \
- dst = r3; \
- 1: r3 = r2; \
- r1 = p1; \
- call _put_core_lock; \
- r0 = r3; \
- r4 = [sp++]; \
- rets = [sp++]; \
- rts;
-
-ENTRY(___raw_cmpxchg_1_asm)
- __do_cmpxchg(b[p1] (z), b[p1])
-ENDPROC(___raw_cmpxchg_1_asm)
-
-ENTRY(___raw_cmpxchg_2_asm)
- __do_cmpxchg(w[p1] (z), w[p1])
-ENDPROC(___raw_cmpxchg_2_asm)
-
-ENTRY(___raw_cmpxchg_4_asm)
- __do_cmpxchg([p1], [p1])
-ENDPROC(___raw_cmpxchg_4_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Set a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_set_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_or_asm
-ENDPROC(___raw_bit_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Clear a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_clear_asm)
- r2 = 1;
- r2 <<= r1;
- r1 = ~r2;
- jump ___raw_atomic_and_asm
-ENDPROC(___raw_bit_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Toggle a bit in a 32bit word and return the old 32bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_toggle_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_xor_asm
-ENDPROC(___raw_bit_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-set a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_set_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_set_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_set_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-clear a bit in a 32bit word and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_clear_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_clear_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_clear_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test-and-toggle a bit in a 32bit word,
- * and return the old bit value atomically.
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_toggle_asm)
- [--sp] = rets;
- [--sp] = r1;
- call ___raw_bit_toggle_asm
- r1 = [sp++];
- r2 = 1;
- r2 <<= r1;
- r0 = r0 & r2;
- cc = r0 == 0;
- if cc jump 1f
- r0 = 1;
-1:
- rets = [sp++];
- rts;
-ENDPROC(___raw_bit_test_toggle_asm)
-
-/*
- * r0 = ptr
- * r1 = bitnr
- *
- * Test a bit in a 32bit word and return its value.
- * We need this on this architecture in order to invalidate
- * the local cache before testing.
- *
- * Clobbers: r3:0, p1:0
- */
-ENTRY(___raw_bit_test_asm)
- r2 = r1;
- r1 = 1;
- r1 <<= r2;
- jump ___raw_atomic_test_asm
-ENDPROC(___raw_bit_test_asm)
-
-/*
- * r0 = ptr
- *
- * Fetch and return an uncached 32bit value.
- *
- * Clobbers: r2:0, p1:0
- */
-ENTRY(___raw_uncached_fetch_asm)
- p1 = r0;
- r1 = -L1_CACHE_BYTES;
- r1 = r0 & r1;
- p0 = r1;
- /* flush core internal write buffer before invalidate dcache */
- CSYNC(r2);
- flushinv[p0];
- SSYNC(r2);
- r0 = [p1];
- rts;
-ENDPROC(___raw_uncached_fetch_asm)
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
deleted file mode 100644
index 10e977b56710..000000000000
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN561_EZKIT
- help
- Select your board!
-
-config BFIN561_EZKIT
- bool "BF561-EZKIT"
- help
- BF561-EZKIT-LITE board support.
-
-config BFIN561_TEPLA
- bool "BF561-TEPLA"
- help
- BF561-TEPLA board support.
-
-config BFIN561_BLUETECHNIX_CM
- bool "Bluetechnix CM-BF561"
- help
- CM-BF561 support for EVAL- and DEV-Board.
-
-config BFIN561_ACVILON
- bool "BF561-ACVILON"
- help
- BF561-ACVILON System On Module support (SO-DIMM 144).
- For more information about Acvilon BF561 SoM
- please go to http://www.niistt.ru/
-
-endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
deleted file mode 100644
index a5879f7857ad..000000000000
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# arch/blackfin/mach-bf561/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o
-obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
-obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
-obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
deleted file mode 100644
index 696cc9d7820a..000000000000
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * File: arch/blackfin/mach-bf561/acvilon.c
- * Based on: arch/blackfin/mach-bf561/ezkit.c
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- * Copyright 2004-2006 Analog Devices Inc.
- * Copyright 2009 CJSC "NII STT"
- *
- * Bugs:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
- *
- * For more information about Acvilon BF561 SoM please
- * go to http://www.niistt.ru/
- *
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/jiffies.h>
-#include <linux/i2c-pca-platform.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <asm/cacheflush.h>
-#include <linux/i2c.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Acvilon board";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x20000000,
- .end = 0x20000000 + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF15,
- .end = IRQ_PF15,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .port1_disable = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-static struct resource bfin_i2c_pca_resources[] = {
- {
- .name = "pca9564-regs",
- .start = 0x2C000000,
- .end = 0x2C000000 + 16,
- .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
- }, {
-
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
- .gpio = -1,
- .i2c_clock_speed = 330000,
- .timeout = HZ,
-};
-
-/* PCA9564 I2C Bus driver */
-static struct platform_device bfin_i2c_pca_device = {
- .name = "i2c-pca-platform",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
- .resource = bfin_i2c_pca_resources,
- .dev = {
- .platform_data = &pca9564_platform_data,
- }
-};
-
-/* I2C devices fitted. */
-static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
- {
- I2C_BOARD_INFO("ds1339", 0x68),
- },
- {
- I2C_BOARD_INFO("tcn75", 0x49),
- },
-};
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
-static struct platdata_mtd_ram mtd_ram_data = {
- .mapname = "rootfs(RAM)",
- .bankwidth = 4,
-};
-
-static struct resource mtd_ram_resource = {
- .start = 0x4000000,
- .end = 0x5ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mtd_ram_device = {
- .name = "mtd-ram",
- .id = 0,
- .dev = {
- .platform_data = &mtd_ram_data,
- },
- .num_resources = 1,
- .resource = &mtd_ram_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x28000000,
- .end = 0x28000000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL + 2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- /* Passed to driver */
- .platform_data = &bfin_uart0_peripherals,
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
-
-static struct mtd_partition bfin_plat_nand_partitions[] = {
- {
- .name = "params(nand)",
- .size = 32 * 1024 * 1024,
- .offset = 0,
- }, {
- .name = "userfs(nand)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-#define BFIN_NAND_PLAT_CLE 2
-#define BFIN_NAND_PLAT_ALE 3
-
-static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- struct nand_chip *this = mtd_to_nand(mtd);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
- else
- writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
-}
-
-#define BFIN_NAND_PLAT_READY GPIO_PF10
-static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(BFIN_NAND_PLAT_READY);
-}
-
-static struct platform_nand_data bfin_plat_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 30,
- .partitions = bfin_plat_nand_partitions,
- .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
- },
- .ctrl = {
- .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
- .dev_ready = bfin_plat_nand_dev_ready,
- },
-};
-
-#define MAX(x, y) (x > y ? x : y)
-static struct resource bfin_plat_nand_resources = {
- .start = 0x24000000,
- .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device bfin_async_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_plat_nand_resources,
- .dev = {
- .platform_data = &bfin_plat_nand_data,
- },
-};
-
-static void bfin_plat_nand_init(void)
-{
- gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
-}
-#else
-static void bfin_plat_nand_init(void)
-{
-}
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
-static struct mtd_partition bfin_spi_dataflash_partitions[] = {
- {
- .name = "bootloader",
- .size = 0x4200,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM},
- {
- .name = "u-boot",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "u-boot(params)",
- .size = 0x4200,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "kernel",
- .size = 0x294000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "params",
- .size = 0x42000,
- .offset = MTDPART_OFS_APPEND,
- },
- {
- .name = "rootfs",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_dataflash_data = {
- .name = "SPI Dataflash",
- .parts = bfin_spi_dataflash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
-};
-
-/* DataFlash chip */
-static struct bfin5xx_spi_chip data_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 3,
- },
-#endif
-#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
- { /* DataFlash chip */
- .modalias = "mtd_dataflash",
- .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 2, /* Framework chip select */
- .platform_data = &bfin_spi_dataflash_data,
- .controller_data = &data_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-static struct resource bfin_gpios_resources = {
- .start = 31,
-/* .end = MAX_BLACKFIN_GPIOS - 1, */
- .end = 32,
- .flags = IORESOURCE_IRQ,
-};
-
-static struct platform_device bfin_gpios_device = {
- .name = "simple-gpio",
- .id = -1,
- .num_resources = 1,
- .resource = &bfin_gpios_resources,
-};
-
-static const unsigned int cclk_vlev_datasheet[] = {
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */ ,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *acvilon_devices[] __initdata = {
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
- &bfin_gpios_device,
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
- &bfin_i2c_pca_device,
-
-#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
- &bfin_async_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PLATRAM)
- &mtd_ram_device,
-#endif
-
-};
-
-static int __init acvilon_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- bfin_plat_nand_init();
- ret =
- platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
- if (ret < 0)
- return ret;
-
- i2c_register_board_info(0, acvilon_i2c_devs,
- ARRAY_SIZE(acvilon_i2c_devs));
-
- bfin_write_FIO0_FLAG_C(1 << 14);
- msleep(5);
- bfin_write_FIO0_FLAG_S(1 << 14);
-
- spi_register_board_info(bfin_spi_board_info,
- ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(acvilon_init);
-
-static struct platform_device *acvilon_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(acvilon_early_devices,
- ARRAY_SIZE(acvilon_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
deleted file mode 100644
index 10c57771822d..000000000000
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ /dev/null
@@ -1,556 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2008-2009 Bluetechnix
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-#endif
-#include <linux/ata_platform.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-#include <linux/mtd/physmap.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "Bluetechnix CM BF561";
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* all SPI peripherals info goes here */
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00020000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0xe0000,
- .offset = 0x20000
- }, {
- .name = "file system(spi)",
- .size = 0x700000,
- .offset = 0x00100000,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "m25p64",
-};
-
-/* SPI flash chip (m25p64) */
-static struct bfin5xx_spi_chip spi_flash_chip_info = {
- .enable_dma = 0, /* use dma transfer with this chip*/
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- },
-#endif
-#if IS_ENABLED(CONFIG_MMC_SPI)
- {
- .modalias = "mmc_spi",
- .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
-static struct platform_device hitachi_fb_device = {
- .name = "hitachi-tx09",
-};
-#endif
-
-
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x28000300,
- .end = 0x28000300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
-#include <linux/smsc911x.h>
-
-static struct resource smsc911x_resources[] = {
- {
- .name = "smsc911x-memory",
- .start = 0x24008000,
- .end = 0x24008000 + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF43,
- .end = IRQ_PF43,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x24000000,
- .end = 0x24000000 + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF45,
- .end = IRQ_PF45,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x24008000,
- .end = 0x24008000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x24008004,
- .end = 0x24008004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF47,
- .end = IRQ_PF47,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
-#define PATA_INT IRQ_PF46
-
-static struct pata_platform_info bfin_pata_platform_data = {
- .ioport_shift = 2,
-};
-
-static struct resource bfin_pata_resources[] = {
- {
- .start = 0x2400C000,
- .end = 0x2400C001F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = 0x2400D018,
- .end = 0x2400D01B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = PATA_INT,
- .end = PATA_INT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device bfin_pata_device = {
- .name = "pata_platform",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_pata_resources),
- .resource = bfin_pata_resources,
- .dev = {
- .platform_data = &bfin_pata_platform_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition para_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x100000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data para_flash_data = {
- .width = 2,
- .parts = para_partitions,
- .nr_parts = ARRAY_SIZE(para_partitions),
-};
-
-static struct resource para_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device para_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &para_flash_data,
- },
- .num_resources = 1,
- .resource = &para_flash_resource,
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *cm_bf561_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_FB_HITACHI_TX09)
- &hitachi_fb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SMSC911X)
- &smsc911x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- &bfin_pata_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &para_flash_device,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF46, "net2272");
- if (ret)
- return ret;
-
- /* Reset USB Chip, PF46 */
- gpio_direction_output(GPIO_PF46, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF46, 1);
-#endif
-
- return 0;
-}
-
-static int __init cm_bf561_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
-
-#if IS_ENABLED(CONFIG_PATA_PLATFORM)
- irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- return 0;
-}
-
-arch_initcall(cm_bf561_init);
-
-static struct platform_device *cm_bf561_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(cm_bf561_early_devices,
- ARRAY_SIZE(cm_bf561_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
deleted file mode 100644
index acc5363f60c6..000000000000
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ /dev/null
@@ -1,688 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/gpio/machine.h>
-#include <asm/dma.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/portmux.h>
-#include <asm/dpmc.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF561-EZKIT";
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0F0000,
- .end = 0x203C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
-#include <linux/usb/isp1362.h>
-
-static struct resource isp1362_hcd_resources[] = {
- {
- .start = 0x2c060000,
- .end = 0x2c060000,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0x2c060004,
- .end = 0x2c060004,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PF8,
- .end = IRQ_PF8,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-static struct isp1362_platform_data isp1362_priv = {
- .sel15Kres = 1,
- .clknotstop = 0,
- .oc_enable = 0,
- .int_act_high = 0,
- .int_edge_triggered = 0,
- .remote_wakeup_connected = 0,
- .no_power_switching = 1,
- .power_switching_mode = 0,
-};
-
-static struct platform_device isp1362_hcd_device = {
- .name = "isp1362-hcd",
- .id = 0,
- .dev = {
- .platform_data = &isp1362_priv,
- },
- .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
- .resource = isp1362_hcd_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
-static struct resource net2272_bfin_resources[] = {
- {
- .start = 0x2C000000,
- .end = 0x2C000000 + 0x7F,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 1,
- .flags = IORESOURCE_BUS,
- }, {
- .start = IRQ_PF10,
- .end = IRQ_PF10,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct platform_device net2272_bfin_device = {
- .name = "net2272",
- .id = -1,
- .num_resources = ARRAY_SIZE(net2272_bfin_resources),
- .resource = net2272_bfin_resources,
-};
-#endif
-
-/*
- * USB-LAN EzExtender board
- * Driver needs to know address, irq and flag pin.
- */
-#if IS_ENABLED(CONFIG_SMC91X)
-#include <linux/smc91x.h>
-
-static struct smc91x_platdata smc91x_info = {
- .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
- SMC91X_NOWAIT,
- .leda = RPC_LED_100_10,
- .ledb = RPC_LED_TX_RX,
-};
-
-static struct resource smc91x_resources[] = {
- {
- .name = "smc91x-regs",
- .start = 0x2C010300,
- .end = 0x2C010300 + 16,
- .flags = IORESOURCE_MEM,
- }, {
-
- .start = IRQ_PF9,
- .end = IRQ_PF9,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
- .dev = {
- .platform_data = &smc91x_info,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x40000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x1C0000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "config(nor)",
- .size = 0x2000 * 7,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "u-boot env(nor)",
- .size = 0x2000,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0x20000000,
- .end = 0x207fffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- [0] = {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = CH_SPI,
- .end = CH_SPI,
- .flags = IORESOURCE_DMA,
- },
- [2] = {
- .start = IRQ_SPI,
- .end = IRQ_SPI,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-/* SPI controller data */
-static struct bfin5xx_spi_master bfin_spi0_info = {
- .num_chipselect = 8,
- .enable_dma = 1, /* master has the ability to do dma transfer */
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bfin_spi0_device = {
- .name = "bfin-spi",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bfin_spi0_info, /* Passed to driver */
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- {
- .modalias = "ad183x",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 4,
- .platform_data = "ad1836", /* only includes chip name for the moment */
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = 1,
- },
-#endif
-};
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF7, 1, "gpio-keys: BTN2"},
- {BTN_3, GPIO_PF8, 1, "gpio-keys: BTN3"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
-#include <linux/i2c-gpio.h>
-
-static struct gpiod_lookup_table bfin_i2c_gpiod_table = {
- .dev_id = "i2c-gpio",
- .table = {
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF1, NULL, 0,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- GPIO_LOOKUP_IDX("BFIN-GPIO", GPIO_PF0, NULL, 1,
- GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
- },
-};
-
-static struct i2c_gpio_platform_data i2c_gpio_data = {
- .udelay = 10,
-};
-
-static struct platform_device i2c_gpio_device = {
- .name = "i2c-gpio",
- .id = 0,
- .dev = {
- .platform_data = &i2c_gpio_data,
- },
-};
-#endif
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
- VRPAIR(VLEV_085, 250000000),
- VRPAIR(VLEV_090, 300000000),
- VRPAIR(VLEV_095, 313000000),
- VRPAIR(VLEV_100, 350000000),
- VRPAIR(VLEV_105, 400000000),
- VRPAIR(VLEV_110, 444000000),
- VRPAIR(VLEV_115, 450000000),
- VRPAIR(VLEV_120, 475000000),
- VRPAIR(VLEV_125, 500000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_PPI,
- .dma_ch = CH_PPI0,
- .irq_err = IRQ_PPI1_ERROR,
- .base = (void __iomem *)PPI0_CONTROL,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7183)
-#include <media/i2c/adv7183.h>
-static struct v4l2_input adv7183_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
-};
-
-static struct bcap_route adv7183_routes[] = {
- {
- .input = ADV7183_COMPOSITE4,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_SVIDEO0,
- .output = ADV7183_8BIT_OUT,
- },
- {
- .input = ADV7183_COMPONENT0,
- .output = ADV7183_8BIT_OUT,
- },
-};
-
-
-static const unsigned adv7183_gpio[] = {
- GPIO_PF13, /* reset pin */
- GPIO_PF2, /* output enable pin */
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF561",
- .inputs = adv7183_inputs,
- .num_inputs = ARRAY_SIZE(adv7183_inputs),
- .routes = adv7183_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7183",
- .addr = 0x20,
- .platform_data = (void *)adv7183_gpio,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | DMA32 | FLD_SEL),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
-static struct platform_device bfin_ac97 = {
- .name = "bfin-ac97",
- .id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.4",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-
-#if IS_ENABLED(CONFIG_SMC91X)
- &smc91x_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_NET2272)
- &net2272_bfin_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
- &bfin_spi0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- &i2c_gpio_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
- &isp1362_hcd_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
- &bfin_i2s,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_AC97)
- &bfin_ac97,
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-};
-
-static int __init net2272_init(void)
-{
-#if IS_ENABLED(CONFIG_USB_NET2272)
- int ret;
-
- ret = gpio_request(GPIO_PF11, "net2272");
- if (ret)
- return ret;
-
- /* Reset the USB chip */
- gpio_direction_output(GPIO_PF11, 0);
- mdelay(2);
- gpio_set_value(GPIO_PF11, 1);
-#endif
-
- return 0;
-}
-
-static int __init ezkit_init(void)
-{
- int ret;
-
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
-#if IS_ENABLED(CONFIG_I2C_GPIO)
- gpiod_add_lookup_table(&bfin_i2c_gpiod_table);
-#endif
- ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
- if (ret < 0)
- return ret;
-
-#if IS_ENABLED(CONFIG_SMC91X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
- SSYNC();
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
- bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 15));
- bfin_write_FIO0_FLAG_S(1 << 15);
- SSYNC();
- /*
- * This initialization lasts for approximately 4500 MCLKs.
- * MCLK = 12.288MHz
- */
- udelay(400);
-#endif
-
- if (net2272_init())
- pr_warning("unable to configure net2272; it probably won't work\n");
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
deleted file mode 100644
index f87b8cc0cd4c..000000000000
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2004-2007 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Thanks to Jamey Hicks.
- *
- * Only SMSC91C1111 was registered, may do more later.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-
-const char bfin_board_name[] = "Tepla-BF561";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-static struct resource smc91x_resources[] = {
- {
- .start = 0x2C000300,
- .end = 0x2C000320,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_PROG_INTB,
- .end = IRQ_PROG_INTB,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- }, {
- .start = IRQ_PF7,
- .end = IRQ_PF7,
- .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = BFIN_UART_THR,
- .end = BFIN_UART_GCTL+2,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART_TX,
- .end = IRQ_UART_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_RX,
- .end = IRQ_UART_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART_ERROR,
- .end = IRQ_UART_ERROR,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART_TX,
- .end = CH_UART_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART_RX,
- .end = CH_UART_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX, 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#endif
-
-static struct platform_device *tepla_devices[] __initdata = {
- &smc91x_device,
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#endif
-};
-
-static int __init tepla_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
- return platform_add_devices(tepla_devices, ARRAY_SIZE(tepla_devices));
-}
-
-arch_initcall(tepla_init);
-
-static struct platform_device *tepla_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(tepla_early_devices,
- ARRAY_SIZE(tepla_early_devices));
-}
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
deleted file mode 100644
index cf27554e76bf..000000000000
--- a/arch/blackfin/mach-bf561/coreb.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Load firmware into Core B on a BF561
- *
- * Author: Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* The Core B reset func requires code in the application that is loaded into
- * Core B. In order to reset, the application needs to install an interrupt
- * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and
- * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core
- * B to stall when Supplemental Interrupt 0 is set, and will reset PC to
- * 0xff600000 when COREB_SRAM_INIT is cleared.
- */
-
-#include <linux/device.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/miscdevice.h>
-
-#define CMD_COREB_START _IO('b', 0)
-#define CMD_COREB_STOP _IO('b', 1)
-#define CMD_COREB_RESET _IO('b', 2)
-
-static long
-coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- int ret = 0;
-
- switch (cmd) {
- case CMD_COREB_START:
- bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
- break;
- case CMD_COREB_STOP:
- bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020);
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- case CMD_COREB_RESET:
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080);
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- CSYNC();
-
- return ret;
-}
-
-static const struct file_operations coreb_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = coreb_ioctl,
- .llseek = noop_llseek,
-};
-
-static struct miscdevice coreb_dev = {
- .minor = MISC_DYNAMIC_MINOR,
- .name = "coreb",
- .fops = &coreb_fops,
-};
-builtin_misc_device(coreb_dev);
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
deleted file mode 100644
index 8ffdd6b4a242..000000000000
--- a/arch/blackfin/mach-bf561/dma.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
- (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
- (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_PPI0:
- ret_irq = IRQ_PPI0;
- break;
- case CH_PPI1:
- ret_irq = IRQ_PPI1;
- break;
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPI:
- ret_irq = IRQ_SPI;
- break;
- case CH_UART_RX:
- ret_irq = IRQ_UART_RX;
- break;
- case CH_UART_TX:
- ret_irq = IRQ_UART_TX;
- break;
-
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MEM_DMA0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MEM_DMA1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MEM_DMA2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MEM_DMA3;
- break;
-
- case CH_IMEM_STREAM0_SRC:
- case CH_IMEM_STREAM0_DEST:
- ret_irq = IRQ_IMEM_DMA0;
- break;
- case CH_IMEM_STREAM1_SRC:
- case CH_IMEM_STREAM1_DEST:
- ret_irq = IRQ_IMEM_DMA1;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
deleted file mode 100644
index 0123117b8ff2..000000000000
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Graff Yang <graf.yang@analog.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/smp.h>
-#include <asm/blackfin.h>
-#include <asm/cacheflush.h>
-#include <mach/pll.h>
-
-int hotplug_coreb;
-
-void platform_cpu_die(void)
-{
- unsigned long iwr;
-
- hotplug_coreb = 1;
-
- /*
- * When CoreB wakes up, the code in _coreb_trampoline_start cannot
- * turn off the data cache. This causes the CoreB failed to boot.
- * As a workaround, we invalidate all the data cache before sleep.
- */
- blackfin_invalidate_entire_dcache();
-
- /* disable core timer */
- bfin_write_TCNTL(0);
-
- /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
- SSYNC();
-
- /* set CoreB wakeup by ipi0, iwr will be discarded */
- bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
- SSYNC();
-
- coreb_die();
-}
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
deleted file mode 100644
index 038249c1d0d4..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* SIGNBITS Instruction Not Functional under Certain Conditions */
-#define ANOMALY_05000127 (1)
-/* IMDMA S1/D1 Channel May Stall */
-#define ANOMALY_05000149 (1)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* Internal Memory DMA Does Not Operate at Full Speed */
-#define ANOMALY_05000182 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI Not Functional at Core Voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET Operation Forces Stall on the Other Core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
- * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
- * after the behavior and the root cause are confirmed with hardware team.
- */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA May Corrupt Data under Certain Conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data Cache Write Back to External Synchronous Memory May Be Lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error when ISR Context Is Not Restored */
-/* Temporarily walk around for bug 5423 till this issue is confirmed by
- * official anomaly document. It looks 05000281 still exists on bf561
- * v0.5.
- */
-#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* Reads Will Receive Incorrect Data under Certain Conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted after SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* 24-Bit SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* Slave SPI Boot Mode Is Not Functional */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
-#define ANOMALY_05000412 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
-#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* SCKELOW Feature Is Not Functional */
-#define ANOMALY_05000458 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000119 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-#define ANOMALY_16000030 (0)
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bf561.h b/arch/blackfin/mach-bf561/include/mach/bf561.h
deleted file mode 100644
index 9f9a367e6a24..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bf561.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF561_H__
-#define __MACH_BF561_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************
- * Blackfin Cache setup
- */
-
-
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS */
-#define PLL_WAKEUP_BIT 0xFFFFFFFF
-#define DMA1_ERROR_BIT 0xFFFFFF0F
-#define DMA2_ERROR_BIT 0xFFFFF0FF
-#define IMDMA_ERROR_BIT 0xFFFF0FFF
-#define PPI1_ERROR_BIT 0xFFF0FFFF
-#define PPI2_ERROR_BIT 0xFF0FFFFF
-#define SPORT0_ERROR_BIT 0xF0FFFFFF
-#define SPORT1_ERROR_BIT 0x0FFFFFFF
-/* IAR1 BIT FIELDS */
-#define SPI_ERROR_BIT 0xFFFFFFFF
-#define UART_ERROR_BIT 0xFFFFFF0F
-#define RESERVED_ERROR_BIT 0xFFFFF0FF
-#define DMA1_0_BIT 0xFFFF0FFF
-#define DMA1_1_BIT 0xFFF0FFFF
-#define DMA1_2_BIT 0xFF0FFFFF
-#define DMA1_3_BIT 0xF0FFFFFF
-#define DMA1_4_BIT 0x0FFFFFFF
-/* IAR2 BIT FIELDS */
-#define DMA1_5_BIT 0xFFFFFFFF
-#define DMA1_6_BIT 0xFFFFFF0F
-#define DMA1_7_BIT 0xFFFFF0FF
-#define DMA1_8_BIT 0xFFFF0FFF
-#define DMA1_9_BIT 0xFFF0FFFF
-#define DMA1_10_BIT 0xFF0FFFFF
-#define DMA1_11_BIT 0xF0FFFFFF
-#define DMA2_0_BIT 0x0FFFFFFF
-/* IAR3 BIT FIELDS */
-#define DMA2_1_BIT 0xFFFFFFFF
-#define DMA2_2_BIT 0xFFFFFF0F
-#define DMA2_3_BIT 0xFFFFF0FF
-#define DMA2_4_BIT 0xFFFF0FFF
-#define DMA2_5_BIT 0xFFF0FFFF
-#define DMA2_6_BIT 0xFF0FFFFF
-#define DMA2_7_BIT 0xF0FFFFFF
-#define DMA2_8_BIT 0x0FFFFFFF
-/* IAR4 BIT FIELDS */
-#define DMA2_9_BIT 0xFFFFFFFF
-#define DMA2_10_BIT 0xFFFFFF0F
-#define DMA2_11_BIT 0xFFFFF0FF
-#define TIMER0_BIT 0xFFFF0FFF
-#define TIMER1_BIT 0xFFF0FFFF
-#define TIMER2_BIT 0xFF0FFFFF
-#define TIMER3_BIT 0xF0FFFFFF
-#define TIMER4_BIT 0x0FFFFFFF
-/* IAR5 BIT FIELDS */
-#define TIMER5_BIT 0xFFFFFFFF
-#define TIMER6_BIT 0xFFFFFF0F
-#define TIMER7_BIT 0xFFFFF0FF
-#define TIMER8_BIT 0xFFFF0FFF
-#define TIMER9_BIT 0xFFF0FFFF
-#define TIMER10_BIT 0xFF0FFFFF
-#define TIMER11_BIT 0xF0FFFFFF
-#define PROG0_INTA_BIT 0x0FFFFFFF
-/* IAR6 BIT FIELDS */
-#define PROG0_INTB_BIT 0xFFFFFFFF
-#define PROG1_INTA_BIT 0xFFFFFF0F
-#define PROG1_INTB_BIT 0xFFFFF0FF
-#define PROG2_INTA_BIT 0xFFFF0FFF
-#define PROG2_INTB_BIT 0xFFF0FFFF
-#define DMA1_WRRD0_BIT 0xFF0FFFFF
-#define DMA1_WRRD1_BIT 0xF0FFFFFF
-#define DMA2_WRRD0_BIT 0x0FFFFFFF
-/* IAR7 BIT FIELDS */
-#define DMA2_WRRD1_BIT 0xFFFFFFFF
-#define IMDMA_WRRD0_BIT 0xFFFFFF0F
-#define IMDMA_WRRD1_BIT 0xFFFFF0FF
-#define WATCH_BIT 0xFFFF0FFF
-#define RESERVED_1_BIT 0xFFF0FFFF
-#define RESERVED_2_BIT 0xFF0FFFFF
-#define SUPPLE_0_BIT 0xF0FFFFFF
-#define SUPPLE_1_BIT 0x0FFFFFFF
-
-/* Miscellaneous Values */
-
-/****************************** EBIU Settings ********************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#if defined(CONFIG_C_AMBEN_ALL)
-#define V_AMBEN AMBEN_ALL
-#elif defined(CONFIG_C_AMBEN)
-#define V_AMBEN 0x0
-#elif defined(CONFIG_C_AMBEN_B0)
-#define V_AMBEN AMBEN_B0
-#elif defined(CONFIG_C_AMBEN_B0_B1)
-#define V_AMBEN AMBEN_B0_B1
-#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#ifdef CONFIG_C_B0PEN
-#define V_B0PEN 0x10
-#else
-#define V_B0PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B1PEN
-#define V_B1PEN 0x20
-#else
-#define V_B1PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B2PEN
-#define V_B2PEN 0x40
-#else
-#define V_B2PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B3PEN
-#define V_B3PEN 0x80
-#else
-#define V_B3PEN 0x00
-#endif
-
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
-
-#ifdef CONFIG_BF561
-#define CPU "BF561"
-#define CPUID 0x27bb
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF561_H__ */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
deleted file mode 100644
index 08072c86d5dc..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 1
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
deleted file mode 100644
index dc470534c085..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF561_FAMILY
-
-#include "bf561.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#include "defBF561.h"
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# include "cdefBF561.h"
-#endif
-
-#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
-#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
-#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
-
-/* Weird muxer funcs which pick SIC regs from IMASK base */
-#define __SIC_MUX(base, x) ((base) + ((x) << 2))
-#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
-#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
-#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
-#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
-#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
-#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
-#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
-#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
-
-#endif /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
deleted file mode 100644
index 753331597207..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ /dev/null
@@ -1,1460 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0,val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1,val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4,val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5,val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6,val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7,val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0,val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1,val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0,val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1,val)
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST,val)
-#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR,val)
-#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT,val)
-#define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0,val)
-#define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
-#define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0,val)
-#define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1,val)
-#define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2,val)
-#define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3,val)
-#define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4,val)
-#define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5,val)
-#define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6,val)
-#define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7,val)
-#define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0,val)
-#define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1,val)
-#define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
-#define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1,val)
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL,val)
-#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT,val)
-#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT,val)
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL,val)
-#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT,val)
-#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT,val)
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART_THR() bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val) bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER() bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val) bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val)
-#define bfin_read_UART_MSR() bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val) bfin_write16(UART_MSR,val)
-#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val)
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH,val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH,val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH,val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH,val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH,val)
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define bfin_read_TMRS8_ENABLE() bfin_read16(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val) bfin_write16(TMRS8_ENABLE,val)
-#define bfin_read_TMRS8_DISABLE() bfin_read16(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val) bfin_write16(TMRS8_DISABLE,val)
-#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS,val)
-#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG,val)
-#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER,val)
-#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD,val)
-#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH,val)
-#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG,val)
-#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER,val)
-#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD,val)
-#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH,val)
-#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG,val)
-#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER,val)
-#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD,val)
-#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH,val)
-#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG,val)
-#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER,val)
-#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD,val)
-#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH,val)
-#define bfin_read_TMRS4_ENABLE() bfin_read16(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val) bfin_write16(TMRS4_ENABLE,val)
-#define bfin_read_TMRS4_DISABLE() bfin_read16(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val) bfin_write16(TMRS4_DISABLE,val)
-#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS,val)
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D,val)
-#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C,val)
-#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S,val)
-#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T,val)
-#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D,val)
-#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C,val)
-#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S,val)
-#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T,val)
-#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D,val)
-#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C,val)
-#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S,val)
-#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T,val)
-#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR,val)
-#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR,val)
-#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE,val)
-#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH,val)
-#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN,val)
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D,val)
-#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C,val)
-#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S,val)
-#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T,val)
-#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D,val)
-#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C,val)
-#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S,val)
-#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T,val)
-#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D,val)
-#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C,val)
-#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S,val)
-#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T,val)
-#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR,val)
-#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR,val)
-#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE,val)
-#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH,val)
-#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN,val)
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D,val)
-#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C,val)
-#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S,val)
-#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T,val)
-#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D,val)
-#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C,val)
-#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S,val)
-#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T,val)
-#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D,val)
-#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C,val)
-#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S,val)
-#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T,val)
-#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR,val)
-#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR,val)
-#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE,val)
-#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH,val)
-#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN,val)
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
-#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
-#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
-#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
-#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
-#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
-#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
-#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
-#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
-#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
-#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
-/*DMA traffic control registers */
-#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
-#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
-#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
-#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
-#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
-#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
-#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
-#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_0_START_ADDR() bfin_read32(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val) bfin_write32(DMA1_0_START_ADDR,val)
-#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT,val)
-#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT,val)
-#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY,val)
-#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY,val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_read32(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_0_CURR_ADDR() bfin_read32(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_write32(DMA1_0_CURR_ADDR,val)
-#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT,val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS,val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG,val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_read32(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_1_START_ADDR() bfin_read32(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val) bfin_write32(DMA1_1_START_ADDR,val)
-#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT,val)
-#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT,val)
-#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY,val)
-#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY,val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_read32(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_1_CURR_ADDR() bfin_read32(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_write32(DMA1_1_CURR_ADDR,val)
-#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS,val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG,val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_read32(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_2_START_ADDR() bfin_read32(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val) bfin_write32(DMA1_2_START_ADDR,val)
-#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT,val)
-#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT,val)
-#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY,val)
-#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY,val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_read32(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_2_CURR_ADDR() bfin_read32(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_write32(DMA1_2_CURR_ADDR,val)
-#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT,val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS,val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG,val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_read32(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_3_START_ADDR() bfin_read32(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val) bfin_write32(DMA1_3_START_ADDR,val)
-#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT,val)
-#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT,val)
-#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY,val)
-#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY,val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_read32(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_3_CURR_ADDR() bfin_read32(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_write32(DMA1_3_CURR_ADDR,val)
-#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT,val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS,val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG,val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_read32(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_4_START_ADDR() bfin_read32(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val) bfin_write32(DMA1_4_START_ADDR,val)
-#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT,val)
-#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT,val)
-#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY,val)
-#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY,val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_read32(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_4_CURR_ADDR() bfin_read32(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_write32(DMA1_4_CURR_ADDR,val)
-#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT,val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS,val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG,val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_read32(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_5_START_ADDR() bfin_read32(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val) bfin_write32(DMA1_5_START_ADDR,val)
-#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT,val)
-#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT,val)
-#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY,val)
-#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY,val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_read32(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_5_CURR_ADDR() bfin_read32(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_write32(DMA1_5_CURR_ADDR,val)
-#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT,val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS,val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG,val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_read32(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_6_START_ADDR() bfin_read32(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val) bfin_write32(DMA1_6_START_ADDR,val)
-#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT,val)
-#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT,val)
-#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY,val)
-#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY,val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_read32(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_6_CURR_ADDR() bfin_read32(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_write32(DMA1_6_CURR_ADDR,val)
-#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT,val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS,val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG,val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_read32(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_7_START_ADDR() bfin_read32(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val) bfin_write32(DMA1_7_START_ADDR,val)
-#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT,val)
-#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT,val)
-#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY,val)
-#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY,val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_read32(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_7_CURR_ADDR() bfin_read32(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_write32(DMA1_7_CURR_ADDR,val)
-#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT,val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS,val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG,val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_read32(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_8_START_ADDR() bfin_read32(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val) bfin_write32(DMA1_8_START_ADDR,val)
-#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT,val)
-#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT,val)
-#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY,val)
-#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY,val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_read32(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_8_CURR_ADDR() bfin_read32(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_write32(DMA1_8_CURR_ADDR,val)
-#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT,val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS,val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG,val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_read32(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_9_START_ADDR() bfin_read32(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val) bfin_write32(DMA1_9_START_ADDR,val)
-#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT,val)
-#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT,val)
-#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY,val)
-#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY,val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_read32(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_9_CURR_ADDR() bfin_read32(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_write32(DMA1_9_CURR_ADDR,val)
-#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT,val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS,val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG,val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_read32(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_10_START_ADDR() bfin_read32(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val) bfin_write32(DMA1_10_START_ADDR,val)
-#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT,val)
-#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT,val)
-#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY,val)
-#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY,val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_read32(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_10_CURR_ADDR() bfin_read32(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_write32(DMA1_10_CURR_ADDR,val)
-#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS,val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG,val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_read32(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_11_START_ADDR() bfin_read32(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val) bfin_write32(DMA1_11_START_ADDR,val)
-#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT,val)
-#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT,val)
-#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY,val)
-#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY,val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_read32(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_11_CURR_ADDR() bfin_read32(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_write32(DMA1_11_CURR_ADDR,val)
-#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS,val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG,val)
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR,val)
-#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT,val)
-#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT,val)
-#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY,val)
-#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY,val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR,val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS,val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG,val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR,val)
-#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT,val)
-#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT,val)
-#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY,val)
-#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY,val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR,val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS,val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG,val)
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR,val)
-#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT,val)
-#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT,val)
-#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY,val)
-#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY,val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR,val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS,val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG,val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR,val)
-#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT,val)
-#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT,val)
-#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY,val)
-#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY,val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR,val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS,val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG,val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_read32(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_0_START_ADDR() bfin_read32(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val) bfin_write32(DMA2_0_START_ADDR,val)
-#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT,val)
-#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT,val)
-#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY,val)
-#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY,val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_read32(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_0_CURR_ADDR() bfin_read32(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_write32(DMA2_0_CURR_ADDR,val)
-#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT,val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS,val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG,val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_read32(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_1_START_ADDR() bfin_read32(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val) bfin_write32(DMA2_1_START_ADDR,val)
-#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT,val)
-#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT,val)
-#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY,val)
-#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY,val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_read32(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_1_CURR_ADDR() bfin_read32(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_write32(DMA2_1_CURR_ADDR,val)
-#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT,val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS,val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG,val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_read32(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_2_START_ADDR() bfin_read32(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val) bfin_write32(DMA2_2_START_ADDR,val)
-#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT,val)
-#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT,val)
-#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY,val)
-#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY,val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_read32(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_2_CURR_ADDR() bfin_read32(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_write32(DMA2_2_CURR_ADDR,val)
-#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS,val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG,val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_read32(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_3_START_ADDR() bfin_read32(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val) bfin_write32(DMA2_3_START_ADDR,val)
-#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT,val)
-#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT,val)
-#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY,val)
-#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY,val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_read32(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_3_CURR_ADDR() bfin_read32(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_write32(DMA2_3_CURR_ADDR,val)
-#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT,val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS,val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG,val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_read32(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_4_START_ADDR() bfin_read32(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val) bfin_write32(DMA2_4_START_ADDR,val)
-#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT,val)
-#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT,val)
-#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY,val)
-#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY,val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_read32(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_4_CURR_ADDR() bfin_read32(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_write32(DMA2_4_CURR_ADDR,val)
-#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT,val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS,val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG,val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_read32(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_5_START_ADDR() bfin_read32(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val) bfin_write32(DMA2_5_START_ADDR,val)
-#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT,val)
-#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT,val)
-#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY,val)
-#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY,val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_read32(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_5_CURR_ADDR() bfin_read32(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_write32(DMA2_5_CURR_ADDR,val)
-#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT,val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS,val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG,val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_read32(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_6_START_ADDR() bfin_read32(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val) bfin_write32(DMA2_6_START_ADDR,val)
-#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT,val)
-#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT,val)
-#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY,val)
-#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY,val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_read32(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_6_CURR_ADDR() bfin_read32(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_write32(DMA2_6_CURR_ADDR,val)
-#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT,val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS,val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG,val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_read32(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_7_START_ADDR() bfin_read32(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val) bfin_write32(DMA2_7_START_ADDR,val)
-#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT,val)
-#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT,val)
-#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY,val)
-#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY,val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_read32(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_7_CURR_ADDR() bfin_read32(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_write32(DMA2_7_CURR_ADDR,val)
-#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT,val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS,val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG,val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_read32(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_8_START_ADDR() bfin_read32(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val) bfin_write32(DMA2_8_START_ADDR,val)
-#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT,val)
-#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT,val)
-#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY,val)
-#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY,val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_read32(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_8_CURR_ADDR() bfin_read32(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_write32(DMA2_8_CURR_ADDR,val)
-#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT,val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS,val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG,val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_read32(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_9_START_ADDR() bfin_read32(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val) bfin_write32(DMA2_9_START_ADDR,val)
-#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT,val)
-#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT,val)
-#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY,val)
-#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY,val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_read32(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_9_CURR_ADDR() bfin_read32(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_write32(DMA2_9_CURR_ADDR,val)
-#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT,val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS,val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG,val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_read32(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_10_START_ADDR() bfin_read32(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val) bfin_write32(DMA2_10_START_ADDR,val)
-#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT,val)
-#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT,val)
-#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY,val)
-#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY,val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_read32(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_10_CURR_ADDR() bfin_read32(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_write32(DMA2_10_CURR_ADDR,val)
-#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS,val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG,val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_read32(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_11_START_ADDR() bfin_read32(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val) bfin_write32(DMA2_11_START_ADDR,val)
-#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT,val)
-#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT,val)
-#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY,val)
-#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY,val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_read32(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_11_CURR_ADDR() bfin_read32(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_write32(DMA2_11_CURR_ADDR,val)
-#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS,val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG,val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_START_ADDR() bfin_read32(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_write32(IMDMA_D0_START_ADDR,val)
-#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT,val)
-#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY,val)
-#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY,val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_read32(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_read32(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_write32(IMDMA_D0_CURR_ADDR,val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG,val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_START_ADDR() bfin_read32(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_write32(IMDMA_S0_START_ADDR,val)
-#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT,val)
-#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY,val)
-#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY,val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_read32(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_read32(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_write32(IMDMA_S0_CURR_ADDR,val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG,val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_START_ADDR() bfin_read32(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_write32(IMDMA_D1_START_ADDR,val)
-#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT,val)
-#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY,val)
-#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY,val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_read32(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_read32(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_write32(IMDMA_D1_CURR_ADDR,val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG,val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_START_ADDR() bfin_read32(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_write32(IMDMA_S1_START_ADDR,val)
-#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT,val)
-#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY,val)
-#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY,val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_read32(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_read32(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_write32(IMDMA_S1_CURR_ADDR,val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS,val)
-
-#endif /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
deleted file mode 100644
index 9f21f768c63a..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ /dev/null
@@ -1,1402 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define CHIPID 0xFFC00014 /* Chip ID Register */
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
-#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
-#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
-#define RESET_SOFTWARE (SWRST_OCCURRED)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define SWRST 0xFFC00100 /* Software Reset register */
-#define SYSCR 0xFFC00104 /* System Reset Configuration register */
-#define SIC_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
-#define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
-#define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
-#define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
-#define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
-#define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
-#define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
-#define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
-#define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
-#define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
-#define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
-#define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
-#define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
-#define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define SICB_SWRST 0xFFC01100 /* reserved */
-#define SICB_SYSCR 0xFFC01104 /* reserved */
-#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
-#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
-#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
-#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
-#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
-#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
-#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
-#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
-#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
-#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
-#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
-#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
-#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
-#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
-#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
-#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
-#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
-#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART0_*.
- */
-#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
-#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
-#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
-#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
-#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register */
-#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE 0xFFC00500
-#define SPI_CTL 0xFFC00500 /* SPI Control Register */
-#define SPI_FLG 0xFFC00504 /* SPI Flag register */
-#define SPI_STAT 0xFFC00508 /* SPI Status register */
-#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
-#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
-#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
-#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
-
-#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
-#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
-#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
-#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
-
-#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
-#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
-#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
-#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
-
-#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
-#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
-#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
-#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
-
-#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
-#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
-#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
-#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
-
-#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
-#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
-#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
-#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
-
-#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
-#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
-#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
-#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
-
-#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
-#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
-#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
-#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
-
-#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
-#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
-#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
-#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
-#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
-#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
-
-#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
-#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
-#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
-#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
-
-#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
-#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
-#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
-#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
-
-#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
-#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
-#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
-#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
-
-#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
-#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
-#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
-#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
-#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
-#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
-#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
-#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
-#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
-#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
-#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
-#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
-#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
-#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
-#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
-#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
-#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
-#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
-#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
-#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
-#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
-#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
-#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
-#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
-#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
-#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
-#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
-#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
-#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
-#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
-#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
-#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
-#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
-#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
-#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
-#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
-#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
-#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
-#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
-#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
-#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
-#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
-#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
-#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
-#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
-#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
-#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
-#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
-#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
-#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
-#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
-#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
-#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
-#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
-#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
-
-/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
-#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
-#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
-#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
-#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
-
-/*DMA traffic control registers */
-#define DMAC0_TC_PER 0xFFC00B0C /* Traffic control periods */
-#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic control current counts */
-#define DMAC1_TC_PER 0xFFC01B0C /* Traffic control periods */
-#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
-#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
-#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
-#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
-#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
-#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
-#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
-#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
-
-#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
-#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
-#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
-#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
-#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
-#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
-#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
-#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
-
-#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
-#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
-#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
-#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
-#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
-#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
-#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
-
-#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
-#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
-#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
-#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
-#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
-#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
-#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
-
-#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
-#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
-#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
-#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
-#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
-#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
-#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
-#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
-
-#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
-#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
-#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
-#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
-#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
-#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
-#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
-#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
-
-#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
-#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
-#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
-#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
-#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
-#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
-#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
-
-#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
-#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
-#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
-#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
-#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
-#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
-#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
-
-#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
-#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
-#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
-#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
-#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
-#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
-#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
-#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
-
-#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
-#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
-#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
-#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
-#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
-#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
-#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
-#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
-
-#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
-#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
-#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
-#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
-#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
-#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
-#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
-
-#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
-#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
-#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
-#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
-#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
-#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
-#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
-#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
-#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
-#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
-#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
-#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
-#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
-#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
-
-#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
-#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
-#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
-#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
-#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
-#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
-#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
-#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
-
-#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
-#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
-#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
-#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
-#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
-#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
-#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
-
-#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
-#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
-#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
-#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
-#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
-#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
-#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
-
-#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
-#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
-#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
-#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
-#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
-#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
-#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
-#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
-
-#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
-#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
-#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
-#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
-#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
-#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
-#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
-#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
-
-#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
-#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
-#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
-#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
-#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
-#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
-#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
-
-#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
-#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
-#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
-#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
-#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
-#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
-#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
-
-#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
-#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
-#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
-#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
-#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
-#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
-#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
-#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
-
-#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
-#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
-#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
-#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
-#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
-#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
-#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
-#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
-
-#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
-#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
-#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
-#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
-#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
-#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
-#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
-
-#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
-#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
-#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
-#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
-#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
-#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
-#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA_D2_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA_D2_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA_D2_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA_D2_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA_D2_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA_D2_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA_D2_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA_D2_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA_D2_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA_S2_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA_S2_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA_S2_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA_S2_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA_S2_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA_S2_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA_S2_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA_S2_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA_S2_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA_D3_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA_D3_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA_D3_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA_D3_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA_D3_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA_D3_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA_D3_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA_D3_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA_D3_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA_S3_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA_S3_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA_S3_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA_S3_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA_S3_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA_S3_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA_S3_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA_S3_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA_S3_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
-#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
-#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
-#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
-#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
-
-#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
-#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
-#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
-#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
-#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
-#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
-
-#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
-#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
-#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
-#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
-
-#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
-#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
-#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
-#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
-#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-/* SICA_SYSCR Masks */
-#define COREB_SRAM_INIT 0x0020
-
-/* SWRST Mask */
-#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
-#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
-#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
-#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
-#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
-#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
-#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
-#define SWRST_OCCURRED 0x8000 /* SWRST Status */
-
-/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* SICu_IARv Masks */
-/* u = A or B */
-/* v = 0 to 7 */
-/* w = 0 or 1 */
-
-/* Per_number = 0 to 63 */
-/* IVG_number = 7 to 15 */
-#define Peripheral_IVG(Per_number, IVG_number) \
- ((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number */
- /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
- /* r0.h = hi(Peripheral_IVG(62, 10)); */
-
-/* SICx_IMASKw Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
-#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
-#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
-
-/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
-
-/* PPI_CONTROL Masks */
-#define PORT_EN 0x00000001 /* PPI Port Enable */
-#define PORT_DIR 0x00000002 /* PPI Port Direction */
-#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
-#define PORT_CFG 0x00000030 /* PPI Port Configuration */
-#define FLD_SEL 0x00000040 /* PPI Active Field Select */
-#define PACK_EN 0x00000080 /* PPI Packing Mode */
-#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH 0x00003800 /* PPI Data Length */
-#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
-#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
-#define DLEN_10 0x00000800 /* Data Length = 10 Bits */
-#define DLEN_11 0x00001000 /* Data Length = 11 Bits */
-#define DLEN_12 0x00001800 /* Data Length = 12 Bits */
-#define DLEN_13 0x00002000 /* Data Length = 13 Bits */
-#define DLEN_14 0x00002800 /* Data Length = 14 Bits */
-#define DLEN_15 0x00003000 /* Data Length = 15 Bits */
-#define DLEN_16 0x00003800 /* Data Length = 16 Bits */
-#define POL 0x0000C000 /* PPI Signal Polarities */
-#define POLC 0x4000 /* PPI Clock Polarity */
-#define POLS 0x8000 /* PPI Frame Sync Polarity */
-
-/* PPI_STATUS Masks */
-#define FLD 0x00000400 /* Field Indicator */
-#define FT_ERR 0x00000800 /* Frame Track Error */
-#define OVR 0x00001000 /* FIFO Overflow Error */
-#define UNDR 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET 0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
-
-/* ********** DMA CONTROLLER MASKS *********************8 */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
-#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
-#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
-#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
-#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
-#define PMAP 0x00007000 /* DMA Peripheral Map Field */
-
-/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0 0x0001
-#define TIMEN1 0x0002
-#define TIMEN2 0x0004
-#define TIMEN3 0x0008
-#define TIMEN4 0x0010
-#define TIMEN5 0x0020
-#define TIMEN6 0x0040
-#define TIMEN7 0x0080
-#define TIMEN8 0x0001
-#define TIMEN9 0x0002
-#define TIMEN10 0x0004
-#define TIMEN11 0x0008
-
-#define TIMEN0_P 0x00
-#define TIMEN1_P 0x01
-#define TIMEN2_P 0x02
-#define TIMEN3_P 0x03
-#define TIMEN4_P 0x04
-#define TIMEN5_P 0x05
-#define TIMEN6_P 0x06
-#define TIMEN7_P 0x07
-#define TIMEN8_P 0x00
-#define TIMEN9_P 0x01
-#define TIMEN10_P 0x02
-#define TIMEN11_P 0x03
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-#define TIMDIS3 0x0008
-#define TIMDIS4 0x0010
-#define TIMDIS5 0x0020
-#define TIMDIS6 0x0040
-#define TIMDIS7 0x0080
-#define TIMDIS8 0x0001
-#define TIMDIS9 0x0002
-#define TIMDIS10 0x0004
-#define TIMDIS11 0x0008
-
-#define TIMDIS0_P 0x00
-#define TIMDIS1_P 0x01
-#define TIMDIS2_P 0x02
-#define TIMDIS3_P 0x03
-#define TIMDIS4_P 0x04
-#define TIMDIS5_P 0x05
-#define TIMDIS6_P 0x06
-#define TIMDIS7_P 0x07
-#define TIMDIS8_P 0x00
-#define TIMDIS9_P 0x01
-#define TIMDIS10_P 0x02
-#define TIMDIS11_P 0x03
-
-/* TIMER_STATUS Register */
-#define TIMIL0 0x00000001
-#define TIMIL1 0x00000002
-#define TIMIL2 0x00000004
-#define TIMIL3 0x00000008
-#define TIMIL4 0x00010000
-#define TIMIL5 0x00020000
-#define TIMIL6 0x00040000
-#define TIMIL7 0x00080000
-#define TIMIL8 0x0001
-#define TIMIL9 0x0002
-#define TIMIL10 0x0004
-#define TIMIL11 0x0008
-#define TOVF_ERR0 0x00000010
-#define TOVF_ERR1 0x00000020
-#define TOVF_ERR2 0x00000040
-#define TOVF_ERR3 0x00000080
-#define TOVF_ERR4 0x00100000
-#define TOVF_ERR5 0x00200000
-#define TOVF_ERR6 0x00400000
-#define TOVF_ERR7 0x00800000
-#define TOVF_ERR8 0x0010
-#define TOVF_ERR9 0x0020
-#define TOVF_ERR10 0x0040
-#define TOVF_ERR11 0x0080
-#define TRUN0 0x00001000
-#define TRUN1 0x00002000
-#define TRUN2 0x00004000
-#define TRUN3 0x00008000
-#define TRUN4 0x10000000
-#define TRUN5 0x20000000
-#define TRUN6 0x40000000
-#define TRUN7 0x80000000
-#define TRUN8 0x1000
-#define TRUN9 0x2000
-#define TRUN10 0x4000
-#define TRUN11 0x8000
-
-#define TIMIL0_P 0x00
-#define TIMIL1_P 0x01
-#define TIMIL2_P 0x02
-#define TIMIL3_P 0x03
-#define TIMIL4_P 0x10
-#define TIMIL5_P 0x11
-#define TIMIL6_P 0x12
-#define TIMIL7_P 0x13
-#define TIMIL8_P 0x00
-#define TIMIL9_P 0x01
-#define TIMIL10_P 0x02
-#define TIMIL11_P 0x03
-#define TOVF_ERR0_P 0x04
-#define TOVF_ERR1_P 0x05
-#define TOVF_ERR2_P 0x06
-#define TOVF_ERR3_P 0x07
-#define TOVF_ERR4_P 0x14
-#define TOVF_ERR5_P 0x15
-#define TOVF_ERR6_P 0x16
-#define TOVF_ERR7_P 0x17
-#define TOVF_ERR8_P 0x04
-#define TOVF_ERR9_P 0x05
-#define TOVF_ERR10_P 0x06
-#define TOVF_ERR11_P 0x07
-#define TRUN0_P 0x0C
-#define TRUN1_P 0x0D
-#define TRUN2_P 0x0E
-#define TRUN3_P 0x0F
-#define TRUN4_P 0x1C
-#define TRUN5_P 0x1D
-#define TRUN6_P 0x1E
-#define TRUN7_P 0x1F
-#define TRUN8_P 0x0C
-#define TRUN9_P 0x0D
-#define TRUN10_P 0x0E
-#define TRUN11_P 0x0F
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-#define TOVL_ERR8 TOVF_ERR8
-#define TOVL_ERR9 TOVF_ERR9
-#define TOVL_ERR10 TOVF_ERR10
-#define TOVL_ERR11 TOVF_ERR11
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-#define TOVL_ERR3_P TOVF_ERR3_P
-#define TOVL_ERR4_P TOVF_ERR4_P
-#define TOVL_ERR5_P TOVF_ERR5_P
-#define TOVL_ERR6_P TOVF_ERR6_P
-#define TOVL_ERR7_P TOVF_ERR7_P
-#define TOVL_ERR8_P TOVF_ERR8_P
-#define TOVL_ERR9_P TOVF_ERR9_P
-#define TOVL_ERR10_P TOVF_ERR10_P
-#define TOVL_ERR11_P TOVF_ERR11_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT 0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK 0x0003
-#define PULSE_HI 0x0004
-#define PERIOD_CNT 0x0008
-#define IRQ_ENA 0x0010
-#define TIN_SEL 0x0020
-#define OUT_DIS 0x0040
-#define CLK_SEL 0x0080
-#define TOGGLE_HI 0x0100
-#define EMU_RUN 0x0200
-#define ERR_TYP(x) ((x & 0x03) << 14)
-
-#define TMODE_P0 0x00
-#define TMODE_P1 0x01
-#define PULSE_HI_P 0x02
-#define PERIOD_CNT_P 0x03
-#define IRQ_ENA_P 0x04
-#define TIN_SEL_P 0x05
-#define OUT_DIS_P 0x06
-#define CLK_SEL_P 0x07
-#define TOGGLE_HI_P 0x08
-#define EMU_RUN_P 0x09
-#define ERR_TYP_P0 0x0E
-#define ERR_TYP_P1 0x0F
-
-/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN 0x0001 /* Enable CLKOUT */
-#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
-#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
-#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
-#define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
-#define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
-#define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
-
-/* ********************** SDRAM CONTROLLER MASKS *************************** */
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE 0x00000010 /* Enable SDRAM prefetch */
-#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
-#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD 0x00200000 /*Power-up start delay */
-#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE 0x02000000 /* Enable external buffering timing */
-#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
-#define EMREN 0x10000000 /* Extended mode register enable */
-#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
-#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
-#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
-#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
-#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
-#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
-#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
-#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
-#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
-#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
-#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
-#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
-#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
-#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
-#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
-#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
-#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
-#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI 0x00000001 /* SDRAM controller is idle */
-#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA 0x00000004 /* SDRAM power up active */
-#define SDRS 0x00000008 /* SDRAM is in reset state */
-#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT 0x00000020 /* Bus granted */
-
-#endif /* _DEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/dma.h b/arch/blackfin/mach-bf561/include/mach/dma.h
deleted file mode 100644
index 13647c71f1c7..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/dma.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_DMA_CHANNELS 36
-
-/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
-#define MAX_DMA_SUSPEND_CHANNELS 32
-
-#define CH_PPI0 0
-#define CH_PPI (CH_PPI0)
-#define CH_PPI1 1
-#define CH_SPORT0_RX 12
-#define CH_SPORT0_TX 13
-#define CH_SPORT1_RX 14
-#define CH_SPORT1_TX 15
-#define CH_SPI 16
-#define CH_UART_RX 17
-#define CH_UART_TX 18
-#define CH_MEM_STREAM0_DEST 24 /* TX */
-#define CH_MEM_STREAM0_SRC 25 /* RX */
-#define CH_MEM_STREAM1_DEST 26 /* TX */
-#define CH_MEM_STREAM1_SRC 27 /* RX */
-#define CH_MEM_STREAM2_DEST 28
-#define CH_MEM_STREAM2_SRC 29
-#define CH_MEM_STREAM3_DEST 30
-#define CH_MEM_STREAM3_SRC 31
-#define CH_IMEM_STREAM0_DEST 32
-#define CH_IMEM_STREAM0_SRC 33
-#define CH_IMEM_STREAM1_DEST 34
-#define CH_IMEM_STREAM1_SRC 35
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
deleted file mode 100644
index f9f8b2adf4ba..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0 0
-#define GPIO_PF1 1
-#define GPIO_PF2 2
-#define GPIO_PF3 3
-#define GPIO_PF4 4
-#define GPIO_PF5 5
-#define GPIO_PF6 6
-#define GPIO_PF7 7
-#define GPIO_PF8 8
-#define GPIO_PF9 9
-#define GPIO_PF10 10
-#define GPIO_PF11 11
-#define GPIO_PF12 12
-#define GPIO_PF13 13
-#define GPIO_PF14 14
-#define GPIO_PF15 15
-#define GPIO_PF16 16
-#define GPIO_PF17 17
-#define GPIO_PF18 18
-#define GPIO_PF19 19
-#define GPIO_PF20 20
-#define GPIO_PF21 21
-#define GPIO_PF22 22
-#define GPIO_PF23 23
-#define GPIO_PF24 24
-#define GPIO_PF25 25
-#define GPIO_PF26 26
-#define GPIO_PF27 27
-#define GPIO_PF28 28
-#define GPIO_PF29 29
-#define GPIO_PF30 30
-#define GPIO_PF31 31
-#define GPIO_PF32 32
-#define GPIO_PF33 33
-#define GPIO_PF34 34
-#define GPIO_PF35 35
-#define GPIO_PF36 36
-#define GPIO_PF37 37
-#define GPIO_PF38 38
-#define GPIO_PF39 39
-#define GPIO_PF40 40
-#define GPIO_PF41 41
-#define GPIO_PF42 42
-#define GPIO_PF43 43
-#define GPIO_PF44 44
-#define GPIO_PF45 45
-#define GPIO_PF46 46
-#define GPIO_PF47 47
-
-#define PORT_FIO0 GPIO_PF0
-#define PORT_FIO1 GPIO_PF16
-#define PORT_FIO2 GPIO_PF32
-
-#include <mach-common/ports-f.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
deleted file mode 100644
index d6998520f70f..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF561_IRQ_H_
-#define _BF561_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (2 * 32)
-
-#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
-#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
-#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
-#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
-#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
-#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
-#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
-#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
-#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
-#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
-#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
-#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
-#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
-#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
-#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
-#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
-#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
-#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
-#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
-#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
-#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
-#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
-#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
-#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
-#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
-#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
-#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
-#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
-#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
-#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
-#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
-#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
-#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
-#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
-#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
-#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
-#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
-#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
-#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
-#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
-#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
-#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
-#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
-#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
-#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
-#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
-#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
-#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
-#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
-#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
-#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
-#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
-#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
-#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
-#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
-#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
-#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
-#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
-
-#define SYS_IRQS 71
-
-#define IRQ_PF0 73
-#define IRQ_PF1 74
-#define IRQ_PF2 75
-#define IRQ_PF3 76
-#define IRQ_PF4 77
-#define IRQ_PF5 78
-#define IRQ_PF6 79
-#define IRQ_PF7 80
-#define IRQ_PF8 81
-#define IRQ_PF9 82
-#define IRQ_PF10 83
-#define IRQ_PF11 84
-#define IRQ_PF12 85
-#define IRQ_PF13 86
-#define IRQ_PF14 87
-#define IRQ_PF15 88
-#define IRQ_PF16 89
-#define IRQ_PF17 90
-#define IRQ_PF18 91
-#define IRQ_PF19 92
-#define IRQ_PF20 93
-#define IRQ_PF21 94
-#define IRQ_PF22 95
-#define IRQ_PF23 96
-#define IRQ_PF24 97
-#define IRQ_PF25 98
-#define IRQ_PF26 99
-#define IRQ_PF27 100
-#define IRQ_PF28 101
-#define IRQ_PF29 102
-#define IRQ_PF30 103
-#define IRQ_PF31 104
-#define IRQ_PF32 105
-#define IRQ_PF33 106
-#define IRQ_PF34 107
-#define IRQ_PF35 108
-#define IRQ_PF36 109
-#define IRQ_PF37 110
-#define IRQ_PF38 111
-#define IRQ_PF39 112
-#define IRQ_PF40 113
-#define IRQ_PF41 114
-#define IRQ_PF42 115
-#define IRQ_PF43 116
-#define IRQ_PF44 117
-#define IRQ_PF45 118
-#define IRQ_PF46 119
-#define IRQ_PF47 120
-
-#define GPIO_IRQ_BASE IRQ_PF0
-
-#define NR_MACH_IRQS (IRQ_PF47 + 1)
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA1_ERROR_POS 4
-#define IRQ_DMA2_ERROR_POS 8
-#define IRQ_IMDMA_ERROR_POS 12
-#define IRQ_PPI0_ERROR_POS 16
-#define IRQ_PPI1_ERROR_POS 20
-#define IRQ_SPORT0_ERROR_POS 24
-#define IRQ_SPORT1_ERROR_POS 28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS 0
-#define IRQ_UART_ERROR_POS 4
-#define IRQ_RESERVED_ERROR_POS 8
-#define IRQ_DMA1_0_POS 12
-#define IRQ_DMA1_1_POS 16
-#define IRQ_DMA1_2_POS 20
-#define IRQ_DMA1_3_POS 24
-#define IRQ_DMA1_4_POS 28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS 0
-#define IRQ_DMA1_6_POS 4
-#define IRQ_DMA1_7_POS 8
-#define IRQ_DMA1_8_POS 12
-#define IRQ_DMA1_9_POS 16
-#define IRQ_DMA1_10_POS 20
-#define IRQ_DMA1_11_POS 24
-#define IRQ_DMA2_0_POS 28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS 0
-#define IRQ_DMA2_2_POS 4
-#define IRQ_DMA2_3_POS 8
-#define IRQ_DMA2_4_POS 12
-#define IRQ_DMA2_5_POS 16
-#define IRQ_DMA2_6_POS 20
-#define IRQ_DMA2_7_POS 24
-#define IRQ_DMA2_8_POS 28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS 0
-#define IRQ_DMA2_10_POS 4
-#define IRQ_DMA2_11_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_TIMER8_POS 12
-#define IRQ_TIMER9_POS 16
-#define IRQ_TIMER10_POS 20
-#define IRQ_TIMER11_POS 24
-#define IRQ_PROG0_INTA_POS 28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS 0
-#define IRQ_PROG1_INTA_POS 4
-#define IRQ_PROG1_INTB_POS 8
-#define IRQ_PROG2_INTA_POS 12
-#define IRQ_PROG2_INTB_POS 16
-#define IRQ_DMA1_WRRD0_POS 20
-#define IRQ_DMA1_WRRD1_POS 24
-#define IRQ_DMA2_WRRD0_POS 28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS 0
-#define IRQ_IMDMA_WRRD0_POS 4
-#define IRQ_IMDMA_WRRD1_POS 8
-#define IRQ_WDTIMER_POS 12
-#define IRQ_RESERVED_1_POS 16
-#define IRQ_RESERVED_2_POS 20
-#define IRQ_SUPPLE_0_POS 24
-#define IRQ_SUPPLE_1_POS 28
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
deleted file mode 100644
index 4cc91995f781..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * BF561 memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xEF000000
-#define BOOT_ROM_LENGTH 0x800
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF561 processors */
-
-#define COREA_L1_CODE_START 0xFFA00000
-#define COREA_L1_DATA_A_START 0xFF800000
-#define COREA_L1_DATA_B_START 0xFF900000
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define L1_CODE_START COREA_L1_CODE_START
-#define L1_DATA_A_START COREA_L1_DATA_A_START
-#define L1_DATA_B_START COREA_L1_DATA_B_START
-
-#define L1_CODE_LENGTH 0x4000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/*
- * If we are in SMP mode, then the cache settings of Core B will match
- * the settings of Core A. If we aren't, then we assume Core B is not
- * using any cache. This allows the rest of the kernel to work with
- * the core in either mode as we are only loading user code into it and
- * it is the user's problem to make sure they aren't doing something
- * stupid there.
- *
- * Note that we treat the L1 code region as a contiguous blob to make
- * the rest of the kernel simpler. Easier to check one region than a
- * bunch of small ones. Again, possible misbehavior here is the fault
- * of the user -- don't try to use memory that doesn't exist.
- */
-#ifdef CONFIG_SMP
-# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
-# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
-# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
-#else
-# define COREB_L1_CODE_LENGTH 0x14000
-# define COREB_L1_DATA_A_LENGTH 0x8000
-# define COREB_L1_DATA_B_LENGTH 0x8000
-#endif
-
-/* Level 2 Memory */
-#define L2_START 0xFEB00000
-#define L2_LENGTH 0x20000
-
-/* Scratch Pad Memory */
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#ifdef CONFIG_SMP
-
-/*
- * The following macros both return the address of the PDA for the
- * current core.
- *
- * In its first safe (and hairy) form, the macro neither clobbers any
- * register aside of the output Preg, nor uses the stack, since it
- * could be called with an invalid stack pointer, or the current stack
- * space being uncovered by any CPLB (e.g. early exception handling).
- *
- * The constraints on the second form are a bit relaxed, and the code
- * is allowed to use the specified Dreg for determining the PDA
- * address to be returned into Preg.
- */
-# define GET_PDA_SAFE(preg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- preg = [preg]; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- preg = preg << 2; \
- if cc jump 2f; \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if !cc jump 3f; \
-1: \
- /* preg = 0x0; */ \
- cc = !cc; /* restore cc to 0 */ \
- jump 4f; \
-2: \
- cc = preg == 0x0; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- if cc jump 4f; \
- /* preg = 0x1000000; */ \
- cc = !cc; /* restore cc to 1 */ \
-3: \
- preg = [preg]; \
-4:
-
-# define GET_PDA(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- preg.l = _cpu_pda; \
- preg.h = _cpu_pda; \
- cc = bittst(dreg, 0); \
- if !cc jump 1f; \
- preg = [preg]; \
-1: \
-
-# define GET_CPUID(preg, dreg) \
- preg.l = lo(DSPID); \
- preg.h = hi(DSPID); \
- dreg = [preg]; \
- dreg = ROT dreg BY -1; \
- dreg = CC;
-
-# ifndef __ASSEMBLY__
-
-# include <asm/processor.h>
-
-static inline unsigned long get_l1_scratch_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
-}
-static inline unsigned long get_l1_code_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
-}
-static inline unsigned long get_l1_data_a_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
-}
-static inline unsigned long get_l1_data_b_start_cpu(int cpu)
-{
- return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
-}
-
-static inline unsigned long get_l1_scratch_start(void)
-{
- return get_l1_scratch_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_code_start(void)
-{
- return get_l1_code_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_a_start(void)
-{
- return get_l1_data_a_start_cpu(blackfin_core_id());
-}
-static inline unsigned long get_l1_data_b_start(void)
-{
- return get_l1_data_b_start_cpu(blackfin_core_id());
-}
-
-# endif /* __ASSEMBLY__ */
-#endif /* CONFIG_SMP */
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
deleted file mode 100644
index 00bdacee9cc2..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2005-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_SMP
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-#include <mach/irq.h>
-
-#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
-#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32)
-
-static inline void
-bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
- bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
-}
-#define bfin_iwr_restore bfin_iwr_restore
-
-static inline void
-bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
- unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
-
- *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
- *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
- bfin_iwr_restore(niwr0, niwr1, niwr2);
-}
-#define bfin_iwr_save bfin_iwr_save
-
-static inline void
-bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
-{
- bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) |
- IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2);
-}
-
-#endif
-
-#endif
-
-#include <mach-common/pll.h>
-
-#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/portmux.h b/arch/blackfin/mach-bf561/include/mach/portmux.h
deleted file mode 100644
index 2339ffd0dde8..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/portmux.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK (P_DONTCARE)
-#define P_PPI0_FS1 (P_DONTCARE)
-#define P_PPI0_FS2 (P_DONTCARE)
-#define P_PPI0_FS3 (P_DONTCARE)
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0 (P_DONTCARE)
-#define P_PPI0_D1 (P_DONTCARE)
-#define P_PPI0_D2 (P_DONTCARE)
-#define P_PPI0_D3 (P_DONTCARE)
-#define P_PPI0_D4 (P_DONTCARE)
-#define P_PPI0_D5 (P_DONTCARE)
-#define P_PPI0_D6 (P_DONTCARE)
-#define P_PPI0_D7 (P_DONTCARE)
-#define P_PPI1_CLK (P_DONTCARE)
-#define P_PPI1_FS1 (P_DONTCARE)
-#define P_PPI1_FS2 (P_DONTCARE)
-#define P_PPI1_FS3 (P_DONTCARE)
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0 (P_DONTCARE)
-#define P_PPI1_D1 (P_DONTCARE)
-#define P_PPI1_D2 (P_DONTCARE)
-#define P_PPI1_D3 (P_DONTCARE)
-#define P_PPI1_D4 (P_DONTCARE)
-#define P_PPI1_D5 (P_DONTCARE)
-#define P_PPI1_D6 (P_DONTCARE)
-#define P_PPI1_D7 (P_DONTCARE)
-#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI (P_DONTCARE)
-#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI (P_DONTCARE)
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11 (P_DONTCARE)
-#define P_TMR10 (P_DONTCARE)
-#define P_TMR9 (P_DONTCARE)
-#define P_TMR8 (P_DONTCARE)
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI (P_DONTCARE)
-#define P_SPI0_MISO (P_DONTCARE)
-#define P_SPI0_SCK (P_DONTCARE)
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
deleted file mode 100644
index 346c60589be6..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/smp.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BF561_SMP
-#define _MACH_BF561_SMP
-
-/* This header has to stand alone to avoid circular deps */
-
-struct task_struct;
-
-void platform_init_cpus(void);
-
-void platform_prepare_cpus(unsigned int max_cpus);
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
-
-void platform_secondary_init(unsigned int cpu);
-
-void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
-
-void platform_send_ipi(cpumask_t callmap, int irq);
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq);
-
-void platform_clear_ipi(unsigned int cpu, int irq);
-
-void bfin_local_timer_setup(void);
-
-#endif /* !_MACH_BF561_SMP */
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
deleted file mode 100644
index 7ee9262fe132..000000000000
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-void __init program_IAR(void)
-{
- /* Program the IAR0 Register with the configured priority */
- bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
- ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
- ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
- ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
- ((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) |
- ((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) |
- ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
- ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
-
- bfin_write_SIC_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
- ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
- ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
- ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
- ((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) |
- ((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) |
- ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
- ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
-
- bfin_write_SIC_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
- ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
- ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
- ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
- ((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) |
- ((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) |
- ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
- ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
-
- bfin_write_SIC_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
- ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
- ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
- ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
- ((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) |
- ((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) |
- ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
- ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
-
- bfin_write_SIC_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
- ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
- ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
- ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
- ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
- ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
- ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
- ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
-
- bfin_write_SIC_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
- ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
- ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
- ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
- ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
- ((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) |
- ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
- ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
-
- bfin_write_SIC_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
- ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
- ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
- ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
- ((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) |
- ((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) |
- ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
- ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
-
- bfin_write_SIC_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
- ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
- ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
- (0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) |
- (0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS));
-
- SSYNC();
-}
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
deleted file mode 100644
index 01e5408620ac..000000000000
--- a/arch/blackfin/mach-bf561/secondary.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * BF561 coreB bootstrap file
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-
-/*
- * This code must come first as CoreB is hardcoded (in hardware)
- * to start at the beginning of its L1 instruction memory.
- */
-.section .l1.text.head
-
-/* Lay the initial stack into the L1 scratch area of Core B */
-#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-ENTRY(_coreb_trampoline_start)
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda_coreb;
- p1.h = _initial_pda_coreb;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- /* This section keeps the processor in supervisor mode
- * during core B startup. Branches to the idle task.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _coreb_start;
- p1.h = _coreb_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
- r0 = EVT_IVG15 (z);
- sti r0;
-
- raise 15;
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
- reti = p0;
-#if defined(ANOMALY_05000281)
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(_coreb_trampoline_start)
-
-#ifdef CONFIG_HOTPLUG_CPU
-.section ".text"
-ENTRY(_coreb_die)
- sp.l = lo(INITIAL_STACK);
- sp.h = hi(INITIAL_STACK);
- fp = sp;
- usp = sp;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- R0 = IWR_DISABLE_ALL;
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
- SSYNC;
-
- p0.h = hi(COREB_L1_CODE_START);
- p0.l = lo(COREB_L1_CODE_START);
- jump (p0);
-ENDPROC(_coreb_die)
-#endif
-
-__INIT
-ENTRY(_coreb_start)
- [--sp] = reti;
-
- p0.l = lo(WDOGB_CTL);
- p0.h = hi(WDOGB_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0; /* Clear the watchdog. */
- ssync;
-
- /*
- * switch to IDLE stack.
- */
- p0.l = _secondary_stack;
- p0.h = _secondary_stack;
- sp = [p0];
- usp = sp;
- fp = sp;
-#ifdef CONFIG_HOTPLUG_CPU
- p0.l = _hotplug_coreb;
- p0.h = _hotplug_coreb;
- r0 = [p0];
- cc = BITTST(r0, 0);
- if cc jump 3f;
-#endif
- sp += -12;
- call _init_pda
- sp += 12;
-#ifdef CONFIG_HOTPLUG_CPU
-3:
-#endif
- call _secondary_start_kernel;
-.L_exit:
- jump.s .L_exit;
-ENDPROC(_coreb_start)
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
deleted file mode 100644
index 8c0c80fd1a45..000000000000
--- a/arch/blackfin/mach-bf561/smp.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <asm/smp.h>
-#include <asm/dma.h>
-#include <asm/time.h>
-
-static DEFINE_SPINLOCK(boot_lock);
-
-/*
- * platform_init_cpus() - Tell the world about how many cores we
- * have. This is called while setting up the architecture support
- * (setup_arch()), so don't be too demanding here with respect to
- * available kernel services.
- */
-
-void __init platform_init_cpus(void)
-{
- struct cpumask mask;
-
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_possible(&mask);
-}
-
-void __init platform_prepare_cpus(unsigned int max_cpus)
-{
- struct cpumask mask;
-
- bfin_relocate_coreb_l1_mem();
-
- /* Both cores ought to be present on a bf561! */
- cpumask_set_cpu(0, &mask); /* CoreA */
- cpumask_set_cpu(1, &mask); /* CoreB */
- init_cpu_present(&mask);
-}
-
-int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
-{
- return -EINVAL;
-}
-
-void platform_secondary_init(unsigned int cpu)
-{
- /* Clone setup for peripheral interrupt sources from CoreA. */
- bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
- bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
- SSYNC();
-
- /* Clone setup for IARs from CoreA. */
- bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
- bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
- bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
- bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
- bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
- bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
- bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
- bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
- bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
- bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
- SSYNC();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
-}
-
-int platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- unsigned long timeout;
-
- printk(KERN_INFO "Booting Core B.\n");
-
- spin_lock(&boot_lock);
-
- if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
- /* CoreB already running, sending ipi to wakeup it */
- smp_send_reschedule(cpu);
- } else {
- /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
- bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
- SSYNC();
- }
-
- timeout = jiffies + HZ;
- /* release the lock and let coreb run */
- spin_unlock(&boot_lock);
- while (time_before(jiffies, timeout)) {
- if (cpu_online(cpu))
- break;
- udelay(100);
- barrier();
- }
-
- if (cpu_online(cpu)) {
- return 0;
- } else
- panic("CPU%u: processor failed to boot\n", cpu);
-}
-
-static const char supple0[] = "IRQ_SUPPLE_0";
-static const char supple1[] = "IRQ_SUPPLE_1";
-void __init platform_request_ipi(int irq, void *handler)
-{
- int ret;
- const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
-
- ret = request_irq(irq, handler, IRQF_PERCPU | IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, name, handler);
- if (ret)
- panic("Cannot request %s for IPI service", name);
-}
-
-void platform_send_ipi(cpumask_t callmap, int irq)
-{
- unsigned int cpu;
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
-
- for_each_cpu(cpu, &callmap) {
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
- }
-}
-
-void platform_send_ipi_cpu(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-void platform_clear_ipi(unsigned int cpu, int irq)
-{
- int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
- BUG_ON(cpu >= 2);
- SSYNC();
- bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
- SSYNC();
-}
-
-/*
- * Setup core B's local core timer.
- * In SMP, core timer is used for clock event device.
- */
-void bfin_local_timer_setup(void)
-{
-#if defined(CONFIG_TICKSOURCE_CORETMR)
- struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
- struct irq_chip *chip = irq_data_get_irq_chip(data);
-
- bfin_coretmr_init();
- bfin_coretmr_clockevent_init();
-
- chip->irq_unmask(data);
-#else
- /* Power down the core timer, just to play safe. */
- bfin_write_TCNTL(0);
-#endif
-
-}
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
deleted file mode 100644
index 7d6a8b8926ba..000000000000
--- a/arch/blackfin/mach-bf609/Kconfig
+++ /dev/null
@@ -1,1684 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config BF60x
- def_bool y
- depends on (BF609)
- select IRQ_PREFLOW_FASTEOI
-
-if (BF60x)
-
-source "arch/blackfin/mach-bf609/boards/Kconfig"
-
-menu "BF609 Specific Configuration"
-
-config SEC_IRQ_PRIORITY_LEVELS
- int "SEC interrupt priority levels"
- default 7
- range 0 7
- help
- Divide the total number of interrupt priority levels into sub-levels.
- There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
-
-config L1_PARITY_CHECK
- bool "Enable L1 parity check"
- default n
- help
- Enable the L1 parity check in L1 sram. A fault event is raised
- when L1 parity error is found.
-
-comment "System Cross Bar Priority Assignment"
-
-config SCB_PRIORITY
- bool "Init System Cross Bar Priority"
- default n
-
-menuconfig SCB0_MI0
- bool "SCB0 Master Interface 0 (DDR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI0
-
-config SCB0_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI0_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI0_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI0_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI0_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI0_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI0_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI0_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI0_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI0_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI0_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI0_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI0_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI0
-
-menuconfig SCB0_MI1
- bool "SCB0 Master Interface 1 (SMC)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI1
-
-config SCB0_MI1_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT1
- int "Slot 1 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT2
- int "Slot 2 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT3
- int "Slot 3 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT4
- int "Slot 4 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT5
- int "Slot 5 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT6
- int "Slot 6 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT7
- int "Slot 7 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT8
- int "Slot 8 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT9
- int "Slot 9 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT10
- int "Slot 10 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT12
- int "Slot 12 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT13
- int "Slot 13 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI1_SLOT20
- int "Slot 20 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI1_SLOT21
- int "Slot 21 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI1_SLOT22
- int "Slot 22 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI1_SLOT23
- int "Slot 23 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI1_SLOT24
- int "Slot 24 slave interface id"
- default 0
- range 0 13
-
-config SCB0_MI1_SLOT25
- int "Slot 25 slave interface id"
- default 2
- range 0 13
-
-config SCB0_MI1_SLOT26
- int "Slot 26 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI1_SLOT27
- int "Slot 27 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI1_SLOT28
- int "Slot 28 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI1_SLOT29
- int "Slot 29 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI1_SLOT30
- int "Slot 30 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI1_SLOT31
- int "Slot 31 slave interface id"
- default 13
- range 0 13
-
-endif # SCB0_MI1
-
-menuconfig SCB0_MI2
- bool "SCB0 Master Interface 2 (Data L2)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI2
-
-config SCB0_MI2_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI2_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI2_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI2_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI2_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI2_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI2_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI2_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI2_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI2_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI2_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI2
-
-menuconfig SCB0_MI3
- bool "SCB0 Master Interface 3 (L1A)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI3
-
-config SCB0_MI3_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI3_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI3_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI3_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI3_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI3_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI3_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI3_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI3_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI3_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI3_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI3
-
-menuconfig SCB0_MI4
- bool "SCB0 Master Interface 4 (L1B)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- Core 0 -- 0
- Core 1 -- 2
- SCB1 -- 9
- SCB2 -- 10
- SCB3 -- 11
- SCB4 -- 12
- SCB5 -- 5
- SCB6 -- 6
- SCB7 -- 8
- SCB8 -- 7
- SCB9 -- 4
- USB -- 13
-
-if SCB0_MI4
-
-config SCB0_MI4_SLOT0
- int "Slot 0 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT1
- int "Slot 1 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT2
- int "Slot 2 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT3
- int "Slot 3 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT4
- int "Slot 4 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT5
- int "Slot 5 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT7
- int "Slot 7 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT8
- int "Slot 8 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT9
- int "Slot 9 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT10
- int "Slot 10 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT11
- int "Slot 11 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT12
- int "Slot 12 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT13
- int "Slot 13 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT14
- int "Slot 14 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT15
- int "Slot 15 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT16
- int "Slot 16 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT17
- int "Slot 17 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT18
- int "Slot 18 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT19
- int "Slot 19 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT20
- int "Slot 20 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT21
- int "Slot 21 slave interface id"
- default 5
- range 0 13
-
-config SCB0_MI4_SLOT22
- int "Slot 22 slave interface id"
- default 6
- range 0 13
-
-config SCB0_MI4_SLOT23
- int "Slot 23 slave interface id"
- default 7
- range 0 13
-
-config SCB0_MI4_SLOT24
- int "Slot 24 slave interface id"
- default 8
- range 0 13
-
-config SCB0_MI4_SLOT25
- int "Slot 25 slave interface id"
- default 9
- range 0 13
-
-config SCB0_MI4_SLOT26
- int "Slot 26 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI4_SLOT27
- int "Slot 27 slave interface id"
- default 11
- range 0 13
-
-config SCB0_MI4_SLOT28
- int "Slot 28 slave interface id"
- default 13
- range 0 13
-
-config SCB0_MI4_SLOT29
- int "Slot 29 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI4_SLOT30
- int "Slot 30 slave interface id"
- default 4
- range 0 13
-
-config SCB0_MI4_SLOT31
- int "Slot 31 slave interface id"
- default 7
- range 0 13
-
-endif # SCB0_MI4
-
-menuconfig SCB0_MI5
- bool "SCB0 Master Interface 5 (SMMR)"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MMR0 -- 1
- MMR1 -- 3
- SCB2 -- 10
- SCB4 -- 12
-
-if SCB0_MI5
-
-config SCB0_MI5_SLOT0
- int "Slot 0 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT1
- int "Slot 1 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT2
- int "Slot 2 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT3
- int "Slot 3 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT5
- int "Slot 5 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT6
- int "Slot 6 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT7
- int "Slot 7 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT8
- int "Slot 8 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT9
- int "Slot 9 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT10
- int "Slot 10 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT11
- int "Slot 11 slave interface id"
- default 12
- range 0 13
-
-config SCB0_MI5_SLOT12
- int "Slot 12 slave interface id"
- default 1
- range 0 13
-
-config SCB0_MI5_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 13
-
-config SCB0_MI5_SLOT14
- int "Slot 14 slave interface id"
- default 10
- range 0 13
-
-config SCB0_MI5_SLOT15
- int "Slot 15 slave interface id"
- default 12
- range 0 13
-
-endif # SCB0_MI5
-
-menuconfig SCB1_MI0
- bool "SCB1 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- SPORT0A -- 0
- SPORT0B -- 1
- SPORT1A -- 2
- SPORT1B -- 3
- SPORT2A -- 4
- SPORT2B -- 5
- SPI0TX -- 6
- SPI0RX -- 7
- SPI1TX -- 8
- SPI1RX -- 9
-
-if SCB1_MI0
-
-config SCB1_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 9
-
-config SCB1_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 9
-
-config SCB1_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 8
- range 0 9
-
-config SCB1_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 9
- range 0 9
-
-config SCB1_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 0
- range 0 9
-
-config SCB1_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 1
- range 0 9
-
-config SCB1_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 2
- range 0 9
-
-config SCB1_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 3
- range 0 9
-
-config SCB1_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 4
- range 0 9
-
-config SCB1_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 5
- range 0 9
-
-config SCB1_MI0_SLOT16
- int "Slot 16 slave interface id"
- default 6
- range 0 13
-
-config SCB1_MI0_SLOT17
- int "Slot 17 slave interface id"
- default 7
- range 0 13
-
-config SCB1_MI0_SLOT18
- int "Slot 18 slave interface id"
- default 8
- range 0 13
-
-config SCB1_MI0_SLOT19
- int "Slot 19 slave interface id"
- default 9
- range 0 13
-
-endif # SCB1_MI0
-
-menuconfig SCB2_MI0
- bool "SCB2 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- RSI -- 0
- SDU DMA -- 1
- SDU -- 2
- EMAC0 -- 3
- EMAC1 -- 4
-
-if SCB2_MI0
-
-config SCB2_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB2_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB2_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB2_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB2_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB2_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB2_MI0
-
-menuconfig SCB3_MI0
- bool "SCB3 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- LP0 -- 0
- LP1 -- 1
- LP2 -- 2
- LP3 -- 3
- UART0TX -- 4
- UART0RX -- 5
- UART1TX -- 4
- UART1RX -- 5
-
-if SCB3_MI0
-
-config SCB3_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB3_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB3_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB3_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB3_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB3_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB3_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB3_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB3_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB3_MI0
-
-menuconfig SCB4_MI0
- bool "SCB4 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- MDA21 -- 0
- MDA22 -- 1
- MDA23 -- 2
- MDA24 -- 3
- MDA25 -- 4
- MDA26 -- 5
- MDA27 -- 6
- MDA28 -- 7
-
-if SCB4_MI0
-
-config SCB4_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 7
- range 0 7
-
-config SCB4_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 0
- range 0 7
-
-config SCB4_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 1
- range 0 7
-
-config SCB4_MI0_SLOT10
- int "Slot 10 slave interface id"
- default 2
- range 0 7
-
-config SCB4_MI0_SLOT11
- int "Slot 11 slave interface id"
- default 3
- range 0 7
-
-config SCB4_MI0_SLOT12
- int "Slot 12 slave interface id"
- default 4
- range 0 7
-
-config SCB4_MI0_SLOT13
- int "Slot 13 slave interface id"
- default 5
- range 0 7
-
-config SCB4_MI0_SLOT14
- int "Slot 14 slave interface id"
- default 6
- range 0 7
-
-config SCB4_MI0_SLOT15
- int "Slot 15 slave interface id"
- default 7
- range 0 7
-
-endif # SCB4_MI0
-
-menuconfig SCB5_MI0
- bool "SCB5 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI0 MDA29 -- 0
- PPI0 MDA30 -- 1
- PPI2 MDA31 -- 2
- PPI2 MDA32 -- 3
-
-if SCB5_MI0
-
-config SCB5_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB5_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB5_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB5_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB5_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB5_MI0
-
-menuconfig SCB6_MI0
- bool "SCB6 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PPI1 MDA33 -- 0
- PPI1 MDA34 -- 1
-
-if SCB6_MI0
-
-config SCB6_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 1
-
-config SCB6_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 0
- range 0 1
-
-config SCB6_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 1
- range 0 1
-
-endif # SCB6_MI0
-
-menuconfig SCB7_MI0
- bool "SCB7 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PIXC0 -- 0
- PIXC1 -- 1
- PIXC2 -- 2
-
-if SCB7_MI0
-
-config SCB7_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 2
-
-config SCB7_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 0
- range 0 2
-
-config SCB7_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 1
- range 0 2
-
-config SCB7_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 2
- range 0 2
-
-endif # SCB7_MI0
-
-menuconfig SCB8_MI0
- bool "SCB8 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP CPDOB -- 0
- PVP CPDOC -- 1
- PVP CPCO -- 2
- PVP CPCI -- 3
-
-if SCB8_MI0
-
-config SCB8_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 3
-
-config SCB8_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 0
- range 0 3
-
-config SCB8_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 1
- range 0 3
-
-config SCB8_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 2
- range 0 3
-
-config SCB8_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 3
- range 0 3
-
-endif # SCB8_MI0
-
-menuconfig SCB9_MI0
- bool "SCB9 Master Interface 0"
- default n
- depends on SCB_PRIORITY
- help
- The slave interface id of each slot should be set according following table.
- PVP MPDO -- 0
- PVP MPDI -- 1
- PVP MPCO -- 2
- PVP MPCI -- 3
- PVP CPDOA -- 4
-
-if SCB9_MI0
-
-config SCB9_MI0_SLOT0
- int "Slot 0 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT1
- int "Slot 1 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT2
- int "Slot 2 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT3
- int "Slot 3 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT4
- int "Slot 4 slave interface id"
- default 4
- range 0 4
-
-config SCB9_MI0_SLOT5
- int "Slot 5 slave interface id"
- default 0
- range 0 4
-
-config SCB9_MI0_SLOT6
- int "Slot 6 slave interface id"
- default 1
- range 0 4
-
-config SCB9_MI0_SLOT7
- int "Slot 7 slave interface id"
- default 2
- range 0 4
-
-config SCB9_MI0_SLOT8
- int "Slot 8 slave interface id"
- default 3
- range 0 4
-
-config SCB9_MI0_SLOT9
- int "Slot 9 slave interface id"
- default 4
- range 0 4
-
-endif # SCB9_MI0
-
-endmenu
-
-endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
deleted file mode 100644
index 60ffaf85d303..000000000000
--- a/arch/blackfin/mach-bf609/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# arch/blackfin/mach-bf609/Makefile
-#
-
-obj-y := dma.o clock.o ints-priority.o
-obj-$(CONFIG_PM) += pm.o dpm.o
-obj-$(CONFIG_SCB_PRIORITY) += scb.o
diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig
deleted file mode 100644
index 350154b2a3ee..000000000000
--- a/arch/blackfin/mach-bf609/boards/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "System type"
- default BFIN609_EZKIT
- help
- Select your board!
-
-config BFIN609_EZKIT
- bool "BF609-EZKIT"
- help
- BFIN609-EZKIT board support.
-
-endchoice
diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile
deleted file mode 100644
index 11f98b0882ea..000000000000
--- a/arch/blackfin/mach-bf609/boards/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mach-bf609/boards/Makefile
-#
-
-obj-$(CONFIG_BFIN609_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
deleted file mode 100644
index 51157a255824..000000000000
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ /dev/null
@@ -1,2191 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- * 2005 National ICT Australia (NICTA)
- * Aidan Williams <aidan@nicta.com.au>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/interrupt.h>
-#include <linux/usb/musb.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-adi2.h>
-#include <linux/spi/adi_spi3.h>
-#include <linux/gpio.h>
-#include <asm/dma.h>
-#include <asm/nand.h>
-#include <asm/dpmc.h>
-#include <asm/portmux.h>
-#include <asm/bfin_sdh.h>
-#include <linux/input.h>
-#include <linux/spi/ad7877.h>
-
-/*
- * Name the Board for the /proc/cpuinfo
- */
-const char bfin_board_name[] = "ADI BF609-EZKIT";
-
-/*
- * Driver needs to know address, irq and flag pin.
- */
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
-#include <linux/usb/isp1760.h>
-static struct resource bfin_isp1760_resources[] = {
- [0] = {
- .start = 0x2C0C0000,
- .end = 0x2C0C0000 + 0xfffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_PG7,
- .end = IRQ_PG7,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct isp1760_platform_data isp1760_priv = {
- .is_isp1761 = 0,
- .bus_width_16 = 1,
- .port1_otg = 0,
- .analog_oc = 0,
- .dack_polarity_high = 0,
- .dreq_polarity_high = 0,
-};
-
-static struct platform_device bfin_isp1760_device = {
- .name = "isp1760",
- .id = 0,
- .dev = {
- .platform_data = &isp1760_priv,
- },
- .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
- .resource = bfin_isp1760_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
-#include <linux/platform_data/bfin_rotary.h>
-
-static struct bfin_rotary_platform_data bfin_rotary_data = {
- /*.rotary_up_key = KEY_UP,*/
- /*.rotary_down_key = KEY_DOWN,*/
- .rotary_rel_code = REL_WHEEL,
- .rotary_button_key = KEY_ENTER,
- .debounce = 10, /* 0..17 */
- .mode = ROT_QUAD_ENC | ROT_DEBE,
-};
-
-static struct resource bfin_rotary_resources[] = {
- {
- .start = CNT_CONFIG,
- .end = CNT_CONFIG + 0xff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CNT,
- .end = IRQ_CNT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_rotary_device = {
- .name = "bfin-rotary",
- .id = -1,
- .num_resources = ARRAY_SIZE(bfin_rotary_resources),
- .resource = bfin_rotary_resources,
- .dev = {
- .platform_data = &bfin_rotary_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
-#include <linux/stmmac.h>
-#include <linux/phy.h>
-
-static struct stmmac_mdio_bus_data phy_private_data = {
- .phy_mask = 1,
-};
-
-static struct stmmac_dma_cfg eth_dma_cfg = {
- .pbl = 2,
-};
-
-int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
-{
- bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
- return 0;
-}
-
-static struct plat_stmmacenet_data eth_private_data = {
- .has_gmac = 1,
- .bus_id = 0,
- .enh_desc = 1,
- .phy_addr = 1,
- .mdio_bus_data = &phy_private_data,
- .dma_cfg = &eth_dma_cfg,
- .force_thresh_dma_mode = 1,
- .interface = PHY_INTERFACE_MODE_RMII,
- .init = stmmac_ptp_clk_init,
-};
-
-static struct platform_device bfin_eth_device = {
- .name = "stmmaceth",
- .id = 0,
- .num_resources = 2,
- .resource = (struct resource[]) {
- {
- .start = EMAC0_MACCFG,
- .end = EMAC0_MACCFG + 0x1274,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "macirq",
- .start = IRQ_EMAC0_STAT,
- .end = IRQ_EMAC0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- },
- .dev = {
- .power.can_wakeup = 1,
- .platform_data = &eth_private_data,
- }
-};
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
-#include <linux/input/adxl34x.h>
-static const struct adxl34x_platform_data adxl34x_info = {
- .x_axis_offset = 0,
- .y_axis_offset = 0,
- .z_axis_offset = 0,
- .tap_threshold = 0x31,
- .tap_duration = 0x10,
- .tap_latency = 0x60,
- .tap_window = 0xF0,
- .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
- .act_axis_control = 0xFF,
- .activity_threshold = 5,
- .inactivity_threshold = 3,
- .inactivity_time = 4,
- .free_fall_threshold = 0x7,
- .free_fall_time = 0x20,
- .data_rate = 0x8,
- .data_range = ADXL_FULL_RES,
-
- .ev_type = EV_ABS,
- .ev_code_x = ABS_X, /* EV_REL */
- .ev_code_y = ABS_Y, /* EV_REL */
- .ev_code_z = ABS_Z, /* EV_REL */
-
- .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
-
-/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
-/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
- .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
- .fifo_mode = ADXL_FIFO_STREAM,
- .orientation_enable = ADXL_EN_ORIENTATION_3D,
- .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
- .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
- /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
- .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
-};
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
-static struct platform_device rtc_device = {
- .name = "rtc-bfin",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
-static struct resource bfin_uart0_resources[] = {
- {
- .start = UART0_REVID,
- .end = UART0_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTD_FER,
- .end = PORTD_FER+2,
- .flags = IORESOURCE_REG,
- },
- {
- .start = PORTD_MUX,
- .end = PORTD_MUX+3,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_RX,
- .end = IRQ_UART0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART0_STAT,
- .end = IRQ_UART0_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART0_RX,
- .end = CH_UART0_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PD10,
- .end = GPIO_PD10,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PD9,
- .end = GPIO_PD9,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart0_peripherals[] = {
- P_UART0_TX, P_UART0_RX,
-#ifdef CONFIG_BFIN_UART0_CTSRTS
- P_UART0_RTS, P_UART0_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart0_device = {
- .name = "bfin-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_uart0_resources),
- .resource = bfin_uart0_resources,
- .dev = {
- .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-static struct resource bfin_uart1_resources[] = {
- {
- .start = UART1_REVID,
- .end = UART1_RXDIV+4,
- .flags = IORESOURCE_MEM,
- },
-#ifdef CONFIG_EARLY_PRINTK
- {
- .start = PORTG_FER_SET,
- .end = PORTG_FER_SET+2,
- .flags = IORESOURCE_REG,
- },
-#endif
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_RX,
- .end = IRQ_UART1_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_UART1_STAT,
- .end = IRQ_UART1_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_UART1_RX,
- .end = CH_UART1_RX,
- .flags = IORESOURCE_DMA,
- },
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- { /* CTS pin -- 0 means not supported */
- .start = GPIO_PG13,
- .end = GPIO_PG13,
- .flags = IORESOURCE_IO,
- },
- { /* RTS pin -- 0 means not supported */
- .start = GPIO_PG10,
- .end = GPIO_PG10,
- .flags = IORESOURCE_IO,
- },
-#endif
-};
-
-static unsigned short bfin_uart1_peripherals[] = {
- P_UART1_TX, P_UART1_RX,
-#ifdef CONFIG_BFIN_UART1_CTSRTS
- P_UART1_RTS, P_UART1_CTS,
-#endif
- 0
-};
-
-static struct platform_device bfin_uart1_device = {
- .name = "bfin-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_uart1_resources),
- .resource = bfin_uart1_resources,
- .dev = {
- .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
-static struct resource bfin_sir0_resources[] = {
- {
- .start = 0xFFC00400,
- .end = 0xFFC004FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART0_TX,
- .end = IRQ_UART0_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART0_TX,
- .end = CH_UART0_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir0_device = {
- .name = "bfin_sir",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sir0_resources),
- .resource = bfin_sir0_resources,
-};
-#endif
-#ifdef CONFIG_BFIN_SIR1
-static struct resource bfin_sir1_resources[] = {
- {
- .start = 0xFFC02000,
- .end = 0xFFC020FF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_UART1_TX,
- .end = IRQ_UART1_TX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_UART1_TX,
- .end = CH_UART1_TX+1,
- .flags = IORESOURCE_DMA,
- },
-};
-static struct platform_device bfin_sir1_device = {
- .name = "bfin_sir",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sir1_resources),
- .resource = bfin_sir1_resources,
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
-static struct resource musb_resources[] = {
- [0] = {
- .start = 0xFFCC1000,
- .end = 0xFFCC1398,
- .flags = IORESOURCE_MEM,
- },
- [1] = { /* general IRQ */
- .start = IRQ_USB_STAT,
- .end = IRQ_USB_STAT,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "mc"
- },
- [2] = { /* DMA IRQ */
- .start = IRQ_USB_DMA,
- .end = IRQ_USB_DMA,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
- .name = "dma"
- },
-};
-
-static struct musb_hdrc_config musb_config = {
- .multipoint = 1,
- .dyn_fifo = 0,
- .dma = 1,
- .num_eps = 16,
- .dma_channels = 8,
- .clkin = 48, /* musb CLKIN in MHZ */
-};
-
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC)
- .mode = MUSB_HOST,
-#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
-};
-
-static u64 musb_dmamask = ~(u32)0;
-
-static struct platform_device musb_device = {
- .name = "musb-blackfin",
- .id = 0,
- .dev = {
- .dma_mask = &musb_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &musb_plat,
- },
- .num_resources = ARRAY_SIZE(musb_resources),
- .resource = musb_resources,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
-static struct resource bfin_sport0_uart_resources[] = {
- {
- .start = SPORT0_TCR1,
- .end = SPORT0_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT0_RX,
- .end = IRQ_SPORT0_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_ERROR,
- .end = IRQ_SPORT0_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport0_peripherals[] = {
- P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
- P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
-
-static struct platform_device bfin_sport0_uart_device = {
- .name = "bfin-sport-uart",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
- .resource = bfin_sport0_uart_resources,
- .dev = {
- .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
-static struct resource bfin_sport1_uart_resources[] = {
- {
- .start = SPORT1_TCR1,
- .end = SPORT1_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT1_RX,
- .end = IRQ_SPORT1_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT1_ERROR,
- .end = IRQ_SPORT1_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport1_peripherals[] = {
- P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
- P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
-};
-
-static struct platform_device bfin_sport1_uart_device = {
- .name = "bfin-sport-uart",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
- .resource = bfin_sport1_uart_resources,
- .dev = {
- .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
- },
-};
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
-static struct resource bfin_sport2_uart_resources[] = {
- {
- .start = SPORT2_TCR1,
- .end = SPORT2_MRCS3+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_SPORT2_RX,
- .end = IRQ_SPORT2_RX+1,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT2_ERROR,
- .end = IRQ_SPORT2_ERROR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static unsigned short bfin_sport2_peripherals[] = {
- P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
- P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
-};
-
-static struct platform_device bfin_sport2_uart_device = {
- .name = "bfin-sport-uart",
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
- .resource = bfin_sport2_uart_resources,
- .dev = {
- .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
- },
-};
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
-
-static unsigned short bfin_can0_peripherals[] = {
- P_CAN0_RX, P_CAN0_TX, 0
-};
-
-static struct resource bfin_can0_resources[] = {
- {
- .start = 0xFFC00A00,
- .end = 0xFFC00FFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CAN0_RX,
- .end = IRQ_CAN0_RX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_TX,
- .end = IRQ_CAN0_TX,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_CAN0_STAT,
- .end = IRQ_CAN0_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_can0_device = {
- .name = "bfin_can",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_can0_resources),
- .resource = bfin_can0_resources,
- .dev = {
- .platform_data = &bfin_can0_peripherals, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
-static struct mtd_partition partition_info[] = {
- {
- .name = "bootloader(nand)",
- .offset = 0,
- .size = 0x80000,
- }, {
- .name = "linux kernel(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = 4 * 1024 * 1024,
- },
- {
- .name = "file system(nand)",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-
-static struct bf5xx_nand_platform bfin_nand_platform = {
- .data_width = NFC_NWIDTH_8,
- .partitions = partition_info,
- .nr_partitions = ARRAY_SIZE(partition_info),
- .rd_dly = 3,
- .wr_dly = 3,
-};
-
-static struct resource bfin_nand_resources[] = {
- {
- .start = 0xFFC03B00,
- .end = 0xFFC03B4F,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_NFC,
- .end = CH_NFC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_nand_device = {
- .name = "bfin-nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_nand_resources),
- .resource = bfin_nand_resources,
- .dev = {
- .platform_data = &bfin_nand_platform,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
-
-static struct bfin_sd_host bfin_sdh_data = {
- .dma_chan = CH_RSI,
- .irq_int0 = IRQ_RSI_INT0,
- .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
-};
-
-static struct platform_device bfin_sdh_device = {
- .name = "bfin-sdh",
- .id = 0,
- .dev = {
- .platform_data = &bfin_sdh_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
-static struct mtd_partition ezkit_partitions[] = {
- {
- .name = "bootloader(nor)",
- .size = 0x80000,
- .offset = 0,
- }, {
- .name = "linux kernel(nor)",
- .size = 0x400000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(nor)",
- .size = 0x1000000 - 0x80000 - 0x400000,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-int bf609_nor_flash_init(struct platform_device *pdev)
-{
-#define CONFIG_SMC_GCTL_VAL 0x00000010
-
- bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
- bfin_write32(SMC_B0CTL, 0x01002011);
- bfin_write32(SMC_B0TIM, 0x08170977);
- bfin_write32(SMC_B0ETIM, 0x00092231);
- return 0;
-}
-
-void bf609_nor_flash_exit(struct platform_device *pdev)
-{
- bfin_write32(SMC_GCTL, 0);
-}
-
-static struct physmap_flash_data ezkit_flash_data = {
- .width = 2,
- .parts = ezkit_partitions,
- .init = bf609_nor_flash_init,
- .exit = bf609_nor_flash_exit,
- .nr_parts = ARRAY_SIZE(ezkit_partitions),
-#ifdef CONFIG_ROMKERNEL
- .probe_type = "map_rom",
-#endif
-};
-
-static struct resource ezkit_flash_resource = {
- .start = 0xb0000000,
- .end = 0xb0ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ezkit_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &ezkit_flash_data,
- },
- .num_resources = 1,
- .resource = &ezkit_flash_resource,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_M25P80)
-/* SPI flash chip (w25q32) */
-static struct mtd_partition bfin_spi_flash_partitions[] = {
- {
- .name = "bootloader(spi)",
- .size = 0x00080000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM
- }, {
- .name = "linux kernel(spi)",
- .size = 0x00180000,
- .offset = MTDPART_OFS_APPEND,
- }, {
- .name = "file system(spi)",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- }
-};
-
-static struct flash_platform_data bfin_spi_flash_data = {
- .name = "m25p80",
- .parts = bfin_spi_flash_partitions,
- .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
- .type = "w25q32",
-};
-
-static struct adi_spi3_chip spi_flash_chip_info = {
- .enable_dma = true, /* use dma transfer with this chip*/
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
-static struct adi_spi3_chip spidev_chip_info = {
- .enable_dma = true,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
-static struct platform_device bfin_pcm = {
- .name = "bfin-i2s-pcm-audio",
- .id = -1,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
-#include <asm/bfin_sport3.h>
-static struct resource bfin_snd_resources[] = {
- {
- .start = SPORT0_CTL_A,
- .end = SPORT0_CTL_A,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = SPORT0_CTL_B,
- .end = SPORT0_CTL_B,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPORT0_TX,
- .end = CH_SPORT0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPORT0_RX,
- .end = CH_SPORT0_RX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_SPORT0_TX_STAT,
- .end = IRQ_SPORT0_TX_STAT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = IRQ_SPORT0_RX_STAT,
- .end = IRQ_SPORT0_RX_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static const unsigned short bfin_snd_pin[] = {
- P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
- P_SPORT0_BFS, P_SPORT0_BD0, 0,
-};
-
-static struct bfin_snd_platform_data bfin_snd_data = {
- .pin_req = bfin_snd_pin,
-};
-
-static struct platform_device bfin_i2s = {
- .name = "bfin-i2s",
- .num_resources = ARRAY_SIZE(bfin_snd_resources),
- .resource = bfin_snd_resources,
- .dev = {
- .platform_data = &bfin_snd_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
-static const char * const ad1836_link[] = {
- "bfin-i2s.0",
- "spi0.76",
-};
-static struct platform_device bfin_ad1836_machine = {
- .name = "bfin-snd-ad1836",
- .id = -1,
- .dev = {
- .platform_data = (void *)ad1836_link,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
-static struct platform_device adau1761_device = {
- .name = "bfin-eval-adau1x61",
-};
-#endif
-
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
-#include <sound/adau17x1.h>
-static struct adau1761_platform_data adau1761_info = {
- .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
- .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_capture.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
-#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
- P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
- P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
-#endif
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_VS6624)
-static struct v4l2_input vs6624_inputs[] = {
- {
- .index = 0,
- .name = "Camera",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_UNKNOWN,
- },
-};
-
-static struct bcap_route vs6624_routes[] = {
- {
- .input = 0,
- .output = 0,
- },
-};
-
-static const unsigned vs6624_ce_pin = GPIO_PE4;
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = vs6624_inputs,
- .num_inputs = ARRAY_SIZE(vs6624_inputs),
- .routes = vs6624_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "vs6624",
- .addr = 0x10,
- .platform_data = (void *)&vs6624_ce_pin,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
- | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- .blank_pixels = 4,
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-#include <media/i2c/adv7842.h>
-
-static struct v4l2_input adv7842_inputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_IN_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 3,
- .name = "VGA",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
- {
- .index = 4,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_IN_CAP_DV_TIMINGS,
- },
-};
-
-static struct bcap_route adv7842_routes[] = {
- {
- .input = 3,
- .output = 0,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
- },
- {
- .input = 4,
- .output = 0,
- },
- {
- .input = 2,
- .output = 0,
- },
- {
- .input = 1,
- .output = 0,
- },
- {
- .input = 0,
- .output = 1,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
- | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
- },
-};
-
-static struct adv7842_output_format adv7842_opf[] = {
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
- .blank_data = 1,
- .insert_av_codes = 1,
- },
- {
- .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
- .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
- .blank_data = 1,
- },
-};
-
-static struct adv7842_platform_data adv7842_data = {
- .opf = adv7842_opf,
- .num_opf = ARRAY_SIZE(adv7842_opf),
- .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
- .prim_mode = ADV7842_PRIM_MODE_SDP,
- .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
- .hdmi_free_run_enable = 1,
- .sdp_free_run_auto = 1,
- .llc_dll_phase = 0x10,
- .i2c_sdp_io = 0x40,
- .i2c_sdp = 0x41,
- .i2c_cp = 0x42,
- .i2c_vdp = 0x43,
- .i2c_afe = 0x44,
- .i2c_hdmi = 0x45,
- .i2c_repeater = 0x46,
- .i2c_edid = 0x47,
- .i2c_infoframe = 0x48,
- .i2c_cec = 0x49,
- .i2c_avlink = 0x4a,
-};
-
-static struct bfin_capture_config bfin_capture_data = {
- .card_name = "BF609",
- .inputs = adv7842_inputs,
- .num_inputs = ARRAY_SIZE(adv7842_inputs),
- .routes = adv7842_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7842",
- .addr = 0x20,
- .platform_data = (void *)&adv7842_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
- | EPPI_CTL_ACTIVE656),
-};
-#endif
-
-static struct platform_device bfin_capture_device = {
- .name = "bfin_capture",
- .dev = {
- .platform_data = &bfin_capture_data,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
-#include <linux/videodev2.h>
-#include <media/blackfin/bfin_display.h>
-#include <media/blackfin/ppi.h>
-
-static const unsigned short ppi_req_disp[] = {
- P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
- P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
- P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
- P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
- P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
- 0,
-};
-
-static const struct ppi_info ppi_info = {
- .type = PPI_TYPE_EPPI3,
- .dma_ch = CH_EPPI0_CH0,
- .irq_err = IRQ_EPPI0_STAT,
- .base = (void __iomem *)EPPI0_STAT,
- .pin_req = ppi_req_disp,
-};
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
-#include <media/i2c/adv7511.h>
-
-static struct v4l2_output adv7511_outputs[] = {
- {
- .index = 0,
- .name = "HDMI",
- .type = V4L2_INPUT_TYPE_CAMERA,
- .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
- },
-};
-
-static struct disp_route adv7511_routes[] = {
- {
- .output = 0,
- },
-};
-
-static struct adv7511_platform_data adv7511_data = {
- .edid_addr = 0x7e,
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7511_outputs,
- .num_outputs = ARRAY_SIZE(adv7511_outputs),
- .routes = adv7511_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7511",
- .addr = 0x39,
- .platform_data = (void *)&adv7511_data,
- },
- .ppi_info = &ppi_info,
- .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
- | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
- | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
-#include <media/i2c/adv7343.h>
-
-static struct v4l2_output adv7343_outputs[] = {
- {
- .index = 0,
- .name = "Composite",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 1,
- .name = "S-Video",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
- {
- .index = 2,
- .name = "Component",
- .type = V4L2_OUTPUT_TYPE_ANALOG,
- .std = V4L2_STD_ALL,
- .capabilities = V4L2_OUT_CAP_STD,
- },
-
-};
-
-static struct disp_route adv7343_routes[] = {
- {
- .output = ADV7343_COMPOSITE_ID,
- },
- {
- .output = ADV7343_SVIDEO_ID,
- },
- {
- .output = ADV7343_COMPONENT_ID,
- },
-};
-
-static struct adv7343_platform_data adv7343_data = {
- .mode_config = {
- .sleep_mode = false,
- .pll_control = false,
- .dac_1 = true,
- .dac_2 = true,
- .dac_3 = true,
- .dac_4 = true,
- .dac_5 = true,
- .dac_6 = true,
- },
- .sd_config = {
- .sd_dac_out1 = false,
- .sd_dac_out2 = false,
- },
-};
-
-static struct bfin_display_config bfin_display_data = {
- .card_name = "BF609",
- .outputs = adv7343_outputs,
- .num_outputs = ARRAY_SIZE(adv7343_outputs),
- .routes = adv7343_routes,
- .i2c_adapter_id = 0,
- .board_info = {
- .type = "adv7343",
- .addr = 0x2b,
- .platform_data = (void *)&adv7343_data,
- },
- .ppi_info = &ppi_info_disp,
- .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
- | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
- | EPPI_CTL_NON656 | EPPI_CTL_DIR),
-};
-#endif
-
-static struct platform_device bfin_display_device = {
- .name = "bfin_display",
- .dev = {
- .platform_data = &bfin_display_data,
- },
-};
-#endif
-
-#if defined(CONFIG_FB_BF609_NL8048) \
- || defined(CONFIG_FB_BF609_NL8048_MODULE)
-static struct resource nl8048_resources[] = {
- {
- .start = EPPI2_STAT,
- .end = EPPI2_STAT,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_EPPI2_CH0,
- .end = CH_EPPI2_CH0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = IRQ_EPPI2_STAT,
- .end = IRQ_EPPI2_STAT,
- .flags = IORESOURCE_IRQ,
- },
-};
-static struct platform_device bfin_fb_device = {
- .name = "bf609_nl8048",
- .num_resources = ARRAY_SIZE(nl8048_resources),
- .resource = nl8048_resources,
- .dev = {
- .platform_data = (void *)GPIO_PC15,
- },
-};
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
-#define BFIN_CRC_NAME "bfin-crc"
-
-static struct resource bfin_crc0_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM0_DEST_CRC0,
- .end = CH_MEM_STREAM0_DEST_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc0_device = {
- .name = BFIN_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crc0_resources),
- .resource = bfin_crc0_resources,
-};
-
-static struct resource bfin_crc1_resources[] = {
- {
- .start = REG_CRC1_CTL,
- .end = REG_CRC1_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC1_DCNTEXP,
- .end = IRQ_CRC1_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM1_SRC_CRC1,
- .end = CH_MEM_STREAM1_SRC_CRC1,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_MEM_STREAM1_DEST_CRC1,
- .end = CH_MEM_STREAM1_DEST_CRC1,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crc1_device = {
- .name = BFIN_CRC_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_crc1_resources),
- .resource = bfin_crc1_resources,
-};
-#endif
-
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
-#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
-#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
-
-static struct resource bfin_crypto_crc_resources[] = {
- {
- .start = REG_CRC0_CTL,
- .end = REG_CRC0_REVID+4,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_CRC0_DCNTEXP,
- .end = IRQ_CRC0_DCNTEXP,
- .flags = IORESOURCE_IRQ,
- },
- {
- .start = CH_MEM_STREAM0_SRC_CRC0,
- .end = CH_MEM_STREAM0_SRC_CRC0,
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct platform_device bfin_crypto_crc_device = {
- .name = BFIN_CRYPTO_CRC_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
- .resource = bfin_crypto_crc_resources,
- .dev = {
- .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
-static const struct ad7877_platform_data bfin_ad7877_ts_info = {
- .model = 7877,
- .vref_delay_usecs = 50, /* internal, no capacitor */
- .x_plate_ohms = 419,
- .y_plate_ohms = 486,
- .pressure_max = 1000,
- .pressure_min = 0,
- .stopacq_polarity = 1,
- .first_conversion_delay = 3,
- .acquisition_time = 1,
- .averaging = 1,
- .pen_down_acc_interval = 1,
-};
-#endif
-
-#ifdef CONFIG_PINCTRL_ADI2
-
-# define ADI_PINT_DEVNAME "adi-gpio-pint"
-# define ADI_GPIO_DEVNAME "adi-gpio"
-# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
-
-static struct platform_device bfin_pinctrl_device = {
- .name = ADI_PINCTRL_DEVNAME,
- .id = 0,
-};
-
-static struct resource bfin_pint0_resources[] = {
- {
- .start = PINT0_MASK_SET,
- .end = PINT0_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT0,
- .end = IRQ_PINT0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint0_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_pint0_resources),
- .resource = bfin_pint0_resources,
-};
-
-static struct resource bfin_pint1_resources[] = {
- {
- .start = PINT1_MASK_SET,
- .end = PINT1_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT1,
- .end = IRQ_PINT1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint1_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_pint1_resources),
- .resource = bfin_pint1_resources,
-};
-
-static struct resource bfin_pint2_resources[] = {
- {
- .start = PINT2_MASK_SET,
- .end = PINT2_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT2,
- .end = IRQ_PINT2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint2_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_pint2_resources),
- .resource = bfin_pint2_resources,
-};
-
-static struct resource bfin_pint3_resources[] = {
- {
- .start = PINT3_MASK_SET,
- .end = PINT3_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT3,
- .end = IRQ_PINT3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint3_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_pint3_resources),
- .resource = bfin_pint3_resources,
-};
-
-static struct resource bfin_pint4_resources[] = {
- {
- .start = PINT4_MASK_SET,
- .end = PINT4_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT4,
- .end = IRQ_PINT4,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint4_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_pint4_resources),
- .resource = bfin_pint4_resources,
-};
-
-static struct resource bfin_pint5_resources[] = {
- {
- .start = PINT5_MASK_SET,
- .end = PINT5_LATCH + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PINT5,
- .end = IRQ_PINT5,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device bfin_pint5_device = {
- .name = ADI_PINT_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_pint5_resources),
- .resource = bfin_pint5_resources,
-};
-
-static struct resource bfin_gpa_resources[] = {
- {
- .start = PORTA_FER,
- .end = PORTA_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- { /* optional */
- .start = IRQ_PA0,
- .end = IRQ_PA0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
- .port_pin_base = GPIO_PA0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0, /* PINT0 */
- .pint_assign = true, /* PINT upper 16 bit */
- .pint_map = 0, /* mapping mask in PINT */
-};
-
-static struct platform_device bfin_gpa_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_gpa_resources),
- .resource = bfin_gpa_resources,
- .dev = {
- .platform_data = &bfin_gpa_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpb_resources[] = {
- {
- .start = PORTB_FER,
- .end = PORTB_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PB0,
- .end = IRQ_PB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
- .port_pin_base = GPIO_PB0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 0,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpb_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_gpb_resources),
- .resource = bfin_gpb_resources,
- .dev = {
- .platform_data = &bfin_gpb_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpc_resources[] = {
- {
- .start = PORTC_FER,
- .end = PORTC_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PC0,
- .end = IRQ_PC0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
- .port_pin_base = GPIO_PC0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 1,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpc_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(bfin_gpc_resources),
- .resource = bfin_gpc_resources,
- .dev = {
- .platform_data = &bfin_gpc_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpd_resources[] = {
- {
- .start = PORTD_FER,
- .end = PORTD_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PD0,
- .end = IRQ_PD0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
- .port_pin_base = GPIO_PD0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 2,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpd_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(bfin_gpd_resources),
- .resource = bfin_gpd_resources,
- .dev = {
- .platform_data = &bfin_gpd_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpe_resources[] = {
- {
- .start = PORTE_FER,
- .end = PORTE_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PE0,
- .end = IRQ_PE0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
- .port_pin_base = GPIO_PE0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 3,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpe_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 4,
- .num_resources = ARRAY_SIZE(bfin_gpe_resources),
- .resource = bfin_gpe_resources,
- .dev = {
- .platform_data = &bfin_gpe_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpf_resources[] = {
- {
- .start = PORTF_FER,
- .end = PORTF_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PF0,
- .end = IRQ_PF0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
- .port_pin_base = GPIO_PF0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 4,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpf_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 5,
- .num_resources = ARRAY_SIZE(bfin_gpf_resources),
- .resource = bfin_gpf_resources,
- .dev = {
- .platform_data = &bfin_gpf_pdata, /* Passed to driver */
- },
-};
-
-static struct resource bfin_gpg_resources[] = {
- {
- .start = PORTG_FER,
- .end = PORTG_MUX + 3,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IRQ_PG0,
- .end = IRQ_PG0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
- .port_pin_base = GPIO_PG0,
- .port_width = GPIO_BANKSIZE,
- .pint_id = 5,
- .pint_assign = false,
- .pint_map = 1,
-};
-
-static struct platform_device bfin_gpg_device = {
- .name = ADI_GPIO_DEVNAME,
- .id = 6,
- .num_resources = ARRAY_SIZE(bfin_gpg_resources),
- .resource = bfin_gpg_resources,
- .dev = {
- .platform_data = &bfin_gpg_pdata, /* Passed to driver */
- },
-};
-
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-
-static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
-};
-
-static struct gpio_keys_platform_data bfin_gpio_keys_data = {
- .buttons = bfin_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
-};
-
-static struct platform_device bfin_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &bfin_gpio_keys_data,
- },
-};
-#endif
-
-static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if IS_ENABLED(CONFIG_MTD_M25P80)
- {
- /* the modalias must be the same as spi device driver name */
- .modalias = "m25p80", /* Name of spi_driver for this device */
- .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0, /* Framework bus number */
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .platform_data = &bfin_spi_flash_data,
- .controller_data = &spi_flash_chip_info,
- .mode = SPI_MODE_3,
- },
-#endif
-#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
- {
- .modalias = "ad7877",
- .platform_data = &bfin_ad7877_ts_info,
- .irq = IRQ_PD9,
- .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
- },
-#endif
-#if IS_ENABLED(CONFIG_SPI_SPIDEV)
- {
- .modalias = "spidev",
- .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 0,
- .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
- .controller_data = &spidev_chip_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
- {
- .modalias = "adxl34x",
- .platform_data = &adxl34x_info,
- .irq = IRQ_PC5,
- .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
- .bus_num = 1,
- .chip_select = 2,
- .mode = SPI_MODE_3,
- },
-#endif
-};
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
-/* SPI (0) */
-static struct resource bfin_spi0_resource[] = {
- {
- .start = SPI0_REGBASE,
- .end = SPI0_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI0_TX,
- .end = CH_SPI0_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI0_RX,
- .end = CH_SPI0_RX,
- .flags = IORESOURCE_DMA,
- },
-};
-
-/* SPI (1) */
-static struct resource bfin_spi1_resource[] = {
- {
- .start = SPI1_REGBASE,
- .end = SPI1_REGBASE + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = CH_SPI1_TX,
- .end = CH_SPI1_TX,
- .flags = IORESOURCE_DMA,
- },
- {
- .start = CH_SPI1_RX,
- .end = CH_SPI1_RX,
- .flags = IORESOURCE_DMA,
- },
-
-};
-
-/* SPI controller data */
-static struct adi_spi3_master bf60x_spi_master_info0 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master0 = {
- .name = "adi-spi3",
- .id = 0, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi0_resource),
- .resource = bfin_spi0_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
- },
-};
-
-static struct adi_spi3_master bf60x_spi_master_info1 = {
- .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
- .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
-};
-
-static struct platform_device bf60x_spi_master1 = {
- .name = "adi-spi3",
- .id = 1, /* Bus number */
- .num_resources = ARRAY_SIZE(bfin_spi1_resource),
- .resource = bfin_spi1_resource,
- .dev = {
- .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
- },
-};
-#endif /* spi master and devices */
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
-static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
-
-static struct resource bfin_twi0_resource[] = {
- [0] = {
- .start = TWI0_CLKDIV,
- .end = TWI0_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI0,
- .end = IRQ_TWI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi0_device = {
- .name = "i2c-bfin-twi",
- .id = 0,
- .num_resources = ARRAY_SIZE(bfin_twi0_resource),
- .resource = bfin_twi0_resource,
- .dev = {
- .platform_data = &bfin_twi0_pins,
- },
-};
-
-static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
-
-static struct resource bfin_twi1_resource[] = {
- [0] = {
- .start = TWI1_CLKDIV,
- .end = TWI1_CLKDIV + 0xFF,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_TWI1,
- .end = IRQ_TWI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c_bfin_twi1_device = {
- .name = "i2c-bfin-twi",
- .id = 1,
- .num_resources = ARRAY_SIZE(bfin_twi1_resource),
- .resource = bfin_twi1_resource,
- .dev = {
- .platform_data = &bfin_twi1_pins,
- },
-};
-#endif
-
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
-#include <linux/spi/mcp23s08.h>
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = {
- .base = 120,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch1 = {
- .base = 130,
-};
-static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch2 = {
- .base = 140,
-};
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
-static const struct mcp23s08_platform_data bfin_adv7842_soft_switch = {
- .base = 150,
-};
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
-static const struct mcp23s08_platform_data bfin_adv7511_soft_switch = {
- .base = 160,
-};
-# endif
-#endif
-
-static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
-#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
- {
- I2C_BOARD_INFO("adxl34x", 0x53),
- .irq = IRQ_PC5,
- .platform_data = (void *)&adxl34x_info,
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
- {
- I2C_BOARD_INFO("adau1761", 0x38),
- .platform_data = (void *)&adau1761_info
- },
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
- {
- I2C_BOARD_INFO("ssm2602", 0x1b),
- },
-#endif
-#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08)
- {
- I2C_BOARD_INFO("mcp23017", 0x21),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch0
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x22),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch1
- },
- {
- I2C_BOARD_INFO("mcp23017", 0x23),
- .platform_data = (void *)&bfin_mcp23s08_soft_switch2
- },
-# if IS_ENABLED(CONFIG_VIDEO_ADV7842)
- {
- I2C_BOARD_INFO("mcp23017", 0x26),
- .platform_data = (void *)&bfin_adv7842_soft_switch
- },
-# endif
-# if IS_ENABLED(CONFIG_VIDEO_ADV7511) || IS_ENABLED(CONFIG_VIDEO_ADV7343)
- {
- I2C_BOARD_INFO("mcp23017", 0x25),
- .platform_data = (void *)&bfin_adv7511_soft_switch
- },
-# endif
-#endif
-};
-
-static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
-};
-
-static const unsigned int cclk_vlev_datasheet[] =
-{
-/*
- * Internal VLEV BF54XSBBC1533
- ****temporarily using these values until data sheet is updated
- */
- VRPAIR(VLEV_085, 150000000),
- VRPAIR(VLEV_090, 250000000),
- VRPAIR(VLEV_110, 276000000),
- VRPAIR(VLEV_115, 301000000),
- VRPAIR(VLEV_120, 525000000),
- VRPAIR(VLEV_125, 550000000),
- VRPAIR(VLEV_130, 600000000),
-};
-
-static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
- .tuple_tab = cclk_vlev_datasheet,
- .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
- .vr_settling_time = 25 /* us */,
-};
-
-static struct platform_device bfin_dpmc = {
- .name = "bfin dpmc",
- .dev = {
- .platform_data = &bfin_dmpc_vreg_data,
- },
-};
-
-static struct platform_device *ezkit_devices[] __initdata = {
-
- &bfin_dpmc,
-#if defined(CONFIG_PINCTRL_ADI2)
- &bfin_pinctrl_device,
- &bfin_pint0_device,
- &bfin_pint1_device,
- &bfin_pint2_device,
- &bfin_pint3_device,
- &bfin_pint4_device,
- &bfin_pint5_device,
- &bfin_gpa_device,
- &bfin_gpb_device,
- &bfin_gpc_device,
- &bfin_gpd_device,
- &bfin_gpe_device,
- &bfin_gpf_device,
- &bfin_gpg_device,
-#endif
-
-#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
- &rtc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_BFIN_SIR)
-#ifdef CONFIG_BFIN_SIR0
- &bfin_sir0_device,
-#endif
-#ifdef CONFIG_BFIN_SIR1
- &bfin_sir1_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_STMMAC_ETH)
- &bfin_eth_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
- &musb_device,
-#endif
-
-#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
- &bfin_isp1760_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
-#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
- &bfin_sport0_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
- &bfin_sport1_uart_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
- &bfin_sport2_uart_device,
-#endif
-#endif
-
-#if IS_ENABLED(CONFIG_CAN_BFIN)
- &bfin_can0_device,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
- &bfin_nand_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SDH_BFIN)
- &bfin_sdh_device,
-#endif
-
-#if IS_ENABLED(CONFIG_SPI_ADI_V3)
- &bf60x_spi_master0,
- &bf60x_spi_master1,
-#endif
-
-#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
- &bfin_rotary_device,
-#endif
-
-#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
- &i2c_bfin_twi0_device,
-#if !defined(CONFIG_BF542)
- &i2c_bfin_twi1_device,
-#endif
-#endif
-
-#if defined(CONFIG_BFIN_CRC)
- &bfin_crc0_device,
- &bfin_crc1_device,
-#endif
-#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
- &bfin_crypto_crc_device,
-#endif
-
-#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
- &bfin_device_gpiokeys,
-#endif
-
-#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
- &ezkit_flash_device,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_PCM)
- &bfin_pcm,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
- &bfin_i2s,
-#endif
-#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
- &bfin_ad1836_machine,
-#endif
-#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
- &adau1761_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
- &bfin_capture_device,
-#endif
-#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
- &bfin_display_device,
-#endif
-
-};
-
-/* Pin control settings */
-static struct pinctrl_map __initdata bfin_pinmux_map[] = {
- /* per-device maps */
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
- PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "8bit", "pinctrl-adi2.0", "ppi2_8bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_display.0", "16bit", "pinctrl-adi2.0", "ppi2_16bgrp", "ppi2"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "8bit", "pinctrl-adi2.0", "ppi0_8bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "16bit", "pinctrl-adi2.0", "ppi0_16bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP("bfin_capture.0", "24bit", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
- PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
-};
-
-static int __init ezkit_init(void)
-{
- printk(KERN_INFO "%s(): registering device resources\n", __func__);
-
- /* Initialize pinmuxing */
- pinctrl_register_mappings(bfin_pinmux_map,
- ARRAY_SIZE(bfin_pinmux_map));
-
- i2c_register_board_info(0, bfin_i2c_board_info0,
- ARRAY_SIZE(bfin_i2c_board_info0));
- i2c_register_board_info(1, bfin_i2c_board_info1,
- ARRAY_SIZE(bfin_i2c_board_info1));
-
- platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
-
- spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-
- return 0;
-}
-
-arch_initcall(ezkit_init);
-
-static struct platform_device *ezkit_early_devices[] __initdata = {
-#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
-#ifdef CONFIG_SERIAL_BFIN_UART0
- &bfin_uart0_device,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
- &bfin_uart1_device,
-#endif
-#endif
-};
-
-void __init native_machine_early_platform_add_devices(void)
-{
- printk(KERN_INFO "register early platform devices\n");
- early_platform_add_devices(ezkit_early_devices,
- ARRAY_SIZE(ezkit_early_devices));
-}
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
deleted file mode 100644
index 16e0b09e2197..000000000000
--- a/arch/blackfin/mach-bf609/clock.c
+++ /dev/null
@@ -1,409 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/spinlock.h>
-#include <linux/debugfs.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <linux/seq_file.h>
-#include <linux/clkdev.h>
-
-#include <asm/clocks.h>
-
-#define CGU0_CTL_DF (1 << 0)
-
-#define CGU0_CTL_MSEL_SHIFT 8
-#define CGU0_CTL_MSEL_MASK (0x7f << 8)
-
-#define CGU0_STAT_PLLEN (1 << 0)
-#define CGU0_STAT_PLLBP (1 << 1)
-#define CGU0_STAT_PLLLK (1 << 2)
-#define CGU0_STAT_CLKSALGN (1 << 3)
-#define CGU0_STAT_CCBF0 (1 << 4)
-#define CGU0_STAT_CCBF1 (1 << 5)
-#define CGU0_STAT_SCBF0 (1 << 6)
-#define CGU0_STAT_SCBF1 (1 << 7)
-#define CGU0_STAT_DCBF (1 << 8)
-#define CGU0_STAT_OCBF (1 << 9)
-#define CGU0_STAT_ADDRERR (1 << 16)
-#define CGU0_STAT_LWERR (1 << 17)
-#define CGU0_STAT_DIVERR (1 << 18)
-#define CGU0_STAT_WDFMSERR (1 << 19)
-#define CGU0_STAT_WDIVERR (1 << 20)
-#define CGU0_STAT_PLOCKERR (1 << 21)
-
-#define CGU0_DIV_CSEL_SHIFT 0
-#define CGU0_DIV_CSEL_MASK 0x0000001F
-#define CGU0_DIV_S0SEL_SHIFT 5
-#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
-#define CGU0_DIV_SYSSEL_SHIFT 8
-#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
-#define CGU0_DIV_S1SEL_SHIFT 13
-#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
-#define CGU0_DIV_DSEL_SHIFT 16
-#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
-#define CGU0_DIV_OSEL_SHIFT 22
-#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
-
-#define CLK(_clk, _devname, _conname) \
- { \
- .clk = &_clk, \
- .dev_id = _devname, \
- .con_id = _conname, \
- }
-
-#define NEEDS_INITIALIZATION 0x11
-
-static LIST_HEAD(clk_list);
-
-static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
-{
- u32 val2;
-
- val2 = bfin_read32(reg);
- val2 &= ~mask;
- val2 |= val;
- bfin_write32(reg, val2);
-}
-
-int wait_for_pll_align(void)
-{
- int i = 10000;
- while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
-
- if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
- printk(KERN_CRIT "fail to align clk\n");
- return -1;
- }
-
- return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->enable)
- ret = clk->ops->enable(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- if (!clk)
- return;
-
- if (clk->ops && clk->ops->disable)
- clk->ops->disable(clk);
-}
-EXPORT_SYMBOL(clk_disable);
-
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long ret = 0;
- if (clk->ops && clk->ops->get_rate)
- ret = clk->ops->get_rate(clk);
- return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- long ret = 0;
- if (clk->ops && clk->ops->round_rate)
- ret = clk->ops->round_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EIO;
- if (clk->ops && clk->ops->set_rate)
- ret = clk->ops->set_rate(clk, rate);
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long vco_get_rate(struct clk *clk)
-{
- return clk->rate;
-}
-
-unsigned long pll_get_rate(struct clk *clk)
-{
- u32 df;
- u32 msel;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 stat = bfin_read32(CGU0_STAT);
- if (stat & CGU0_STAT_PLLBP)
- return 0;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / (df + 1) * msel * 2;
-}
-
-unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 div;
- div = rate / clk->parent->rate;
- return clk->parent->rate * div;
-}
-
-int pll_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 msel;
- u32 stat = bfin_read32(CGU0_STAT);
- if (!(stat & CGU0_STAT_PLLEN))
- return -EBUSY;
- if (!(stat & CGU0_STAT_PLLLK))
- return -EBUSY;
- if (wait_for_pll_align())
- return -EBUSY;
- msel = rate / clk->parent->rate / 2;
- clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
- CGU0_CTL_MSEL_MASK);
- clk->rate = rate;
- return 0;
-}
-
-unsigned long cclk_get_rate(struct clk *clk)
-{
- if (clk->parent)
- return clk->parent->rate;
- else
- return 0;
-}
-
-unsigned long sys_clk_get_rate(struct clk *clk)
-{
- unsigned long drate;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
-
- if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
- drate = clk->parent->rate / (df + 1);
- drate *= msel;
- drate /= div;
- return drate;
- } else {
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate / div;
- }
-}
-
-unsigned long dummy_get_rate(struct clk *clk)
-{
- clk->parent->rate = clk_get_rate(clk->parent);
- return clk->parent->rate;
-}
-
-unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long max_rate;
- unsigned long drate;
- int i;
- u32 msel;
- u32 df;
- u32 ctl = bfin_read32(CGU0_CTL);
-
- msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
- df = (ctl & CGU0_CTL_DF);
- max_rate = clk->parent->rate / (df + 1) * msel;
-
- if (rate > max_rate)
- return 0;
-
- for (i = 1; i < clk->mask; i++) {
- drate = max_rate / i;
- if (rate >= drate)
- return drate;
- }
- return 0;
-}
-
-int sys_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 div = bfin_read32(CGU0_DIV);
- div = (div & clk->mask) >> clk->shift;
-
- rate = clk_round_rate(clk, rate);
-
- if (!rate)
- return -EINVAL;
-
- div = (clk_get_rate(clk) * div) / rate;
-
- if (wait_for_pll_align())
- return -EBUSY;
- clk_reg_write_mask(CGU0_DIV, div << clk->shift,
- clk->mask);
- clk->rate = rate;
- return 0;
-}
-
-static struct clk_ops vco_ops = {
- .get_rate = vco_get_rate,
-};
-
-static struct clk_ops pll_ops = {
- .get_rate = pll_get_rate,
- .set_rate = pll_set_rate,
-};
-
-static struct clk_ops cclk_ops = {
- .get_rate = cclk_get_rate,
-};
-
-static struct clk_ops sys_clk_ops = {
- .get_rate = sys_clk_get_rate,
- .set_rate = sys_clk_set_rate,
- .round_rate = sys_clk_round_rate,
-};
-
-static struct clk_ops dummy_clk_ops = {
- .get_rate = dummy_get_rate,
-};
-
-static struct clk sys_clkin = {
- .name = "SYS_CLKIN",
- .rate = CONFIG_CLKIN_HZ,
- .ops = &vco_ops,
-};
-
-static struct clk pll_clk = {
- .name = "PLLCLK",
- .rate = 500000000,
- .parent = &sys_clkin,
- .ops = &pll_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk = {
- .name = "CCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_CSEL_MASK,
- .shift = CGU0_DIV_CSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk cclk0 = {
- .name = "CCLK0",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk cclk1 = {
- .name = "CCLK1",
- .parent = &cclk,
- .ops = &cclk_ops,
-};
-
-static struct clk sysclk = {
- .name = "SYSCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_SYSSEL_MASK,
- .shift = CGU0_DIV_SYSSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
- .flags = NEEDS_INITIALIZATION,
-};
-
-static struct clk sclk0 = {
- .name = "SCLK0",
- .rate = 500000000,
- .mask = CGU0_DIV_S0SEL_MASK,
- .shift = CGU0_DIV_S0SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk sclk1 = {
- .name = "SCLK1",
- .rate = 500000000,
- .mask = CGU0_DIV_S1SEL_MASK,
- .shift = CGU0_DIV_S1SEL_SHIFT,
- .parent = &sysclk,
- .ops = &sys_clk_ops,
-};
-
-static struct clk dclk = {
- .name = "DCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_DSEL_MASK,
- .shift = CGU0_DIV_DSEL_SHIFT,
- .parent = &sys_clkin,
- .ops = &sys_clk_ops,
-};
-
-static struct clk oclk = {
- .name = "OCLK",
- .rate = 500000000,
- .mask = CGU0_DIV_OSEL_MASK,
- .shift = CGU0_DIV_OSEL_SHIFT,
- .parent = &pll_clk,
-};
-
-static struct clk ethclk = {
- .name = "stmmaceth",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk ethpclk = {
- .name = "pclk",
- .parent = &sclk0,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk spiclk = {
- .name = "spi",
- .parent = &sclk1,
- .ops = &dummy_clk_ops,
-};
-
-static struct clk_lookup bf609_clks[] = {
- CLK(sys_clkin, NULL, "SYS_CLKIN"),
- CLK(pll_clk, NULL, "PLLCLK"),
- CLK(cclk, NULL, "CCLK"),
- CLK(cclk0, NULL, "CCLK0"),
- CLK(cclk1, NULL, "CCLK1"),
- CLK(sysclk, NULL, "SYSCLK"),
- CLK(sclk0, NULL, "SCLK0"),
- CLK(sclk1, NULL, "SCLK1"),
- CLK(dclk, NULL, "DCLK"),
- CLK(oclk, NULL, "OCLK"),
- CLK(ethclk, NULL, "stmmaceth"),
- CLK(ethpclk, NULL, "pclk"),
- CLK(spiclk, NULL, "spi"),
-};
-
-int __init clk_init(void)
-{
- int i;
- struct clk *clkp;
- for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
- clkp = bf609_clks[i].clk;
- if (clkp->flags & NEEDS_INITIALIZATION)
- clk_get_rate(clkp);
- }
- clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
- return 0;
-}
diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c
deleted file mode 100644
index 1da4b38ac22c..000000000000
--- a/arch/blackfin/mach-bf609/dma.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * the simple DMA Implementation for Blackfin
- *
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
- (struct dma_register *) DMA0_NEXT_DESC_PTR,
- (struct dma_register *) DMA1_NEXT_DESC_PTR,
- (struct dma_register *) DMA2_NEXT_DESC_PTR,
- (struct dma_register *) DMA3_NEXT_DESC_PTR,
- (struct dma_register *) DMA4_NEXT_DESC_PTR,
- (struct dma_register *) DMA5_NEXT_DESC_PTR,
- (struct dma_register *) DMA6_NEXT_DESC_PTR,
- (struct dma_register *) DMA7_NEXT_DESC_PTR,
- (struct dma_register *) DMA8_NEXT_DESC_PTR,
- (struct dma_register *) DMA9_NEXT_DESC_PTR,
- (struct dma_register *) DMA10_NEXT_DESC_PTR,
- (struct dma_register *) DMA11_NEXT_DESC_PTR,
- (struct dma_register *) DMA12_NEXT_DESC_PTR,
- (struct dma_register *) DMA13_NEXT_DESC_PTR,
- (struct dma_register *) DMA14_NEXT_DESC_PTR,
- (struct dma_register *) DMA15_NEXT_DESC_PTR,
- (struct dma_register *) DMA16_NEXT_DESC_PTR,
- (struct dma_register *) DMA17_NEXT_DESC_PTR,
- (struct dma_register *) DMA18_NEXT_DESC_PTR,
- (struct dma_register *) DMA19_NEXT_DESC_PTR,
- (struct dma_register *) DMA20_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
- (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
- (struct dma_register *) DMA29_NEXT_DESC_PTR,
- (struct dma_register *) DMA30_NEXT_DESC_PTR,
- (struct dma_register *) DMA31_NEXT_DESC_PTR,
- (struct dma_register *) DMA32_NEXT_DESC_PTR,
- (struct dma_register *) DMA33_NEXT_DESC_PTR,
- (struct dma_register *) DMA34_NEXT_DESC_PTR,
- (struct dma_register *) DMA35_NEXT_DESC_PTR,
- (struct dma_register *) DMA36_NEXT_DESC_PTR,
- (struct dma_register *) DMA37_NEXT_DESC_PTR,
- (struct dma_register *) DMA38_NEXT_DESC_PTR,
- (struct dma_register *) DMA39_NEXT_DESC_PTR,
- (struct dma_register *) DMA40_NEXT_DESC_PTR,
- (struct dma_register *) DMA41_NEXT_DESC_PTR,
- (struct dma_register *) DMA42_NEXT_DESC_PTR,
- (struct dma_register *) DMA43_NEXT_DESC_PTR,
- (struct dma_register *) DMA44_NEXT_DESC_PTR,
- (struct dma_register *) DMA45_NEXT_DESC_PTR,
- (struct dma_register *) DMA46_NEXT_DESC_PTR,
-};
-EXPORT_SYMBOL(dma_io_base_addr);
-
-int channel2irq(unsigned int channel)
-{
- int ret_irq = -1;
-
- switch (channel) {
- case CH_SPORT0_RX:
- ret_irq = IRQ_SPORT0_RX;
- break;
- case CH_SPORT0_TX:
- ret_irq = IRQ_SPORT0_TX;
- break;
- case CH_SPORT1_RX:
- ret_irq = IRQ_SPORT1_RX;
- break;
- case CH_SPORT1_TX:
- ret_irq = IRQ_SPORT1_TX;
- break;
- case CH_SPORT2_RX:
- ret_irq = IRQ_SPORT2_RX;
- break;
- case CH_SPORT2_TX:
- ret_irq = IRQ_SPORT2_TX;
- break;
- case CH_SPI0_TX:
- ret_irq = IRQ_SPI0_TX;
- break;
- case CH_SPI0_RX:
- ret_irq = IRQ_SPI0_RX;
- break;
- case CH_SPI1_TX:
- ret_irq = IRQ_SPI1_TX;
- break;
- case CH_SPI1_RX:
- ret_irq = IRQ_SPI1_RX;
- break;
- case CH_RSI:
- ret_irq = IRQ_RSI;
- break;
- case CH_SDU:
- ret_irq = IRQ_SDU;
- break;
- case CH_LP0:
- ret_irq = IRQ_LP0;
- break;
- case CH_LP1:
- ret_irq = IRQ_LP1;
- break;
- case CH_LP2:
- ret_irq = IRQ_LP2;
- break;
- case CH_LP3:
- ret_irq = IRQ_LP3;
- break;
- case CH_UART0_RX:
- ret_irq = IRQ_UART0_RX;
- break;
- case CH_UART0_TX:
- ret_irq = IRQ_UART0_TX;
- break;
- case CH_UART1_RX:
- ret_irq = IRQ_UART1_RX;
- break;
- case CH_UART1_TX:
- ret_irq = IRQ_UART1_TX;
- break;
- case CH_EPPI0_CH0:
- ret_irq = IRQ_EPPI0_CH0;
- break;
- case CH_EPPI0_CH1:
- ret_irq = IRQ_EPPI0_CH1;
- break;
- case CH_EPPI1_CH0:
- ret_irq = IRQ_EPPI1_CH0;
- break;
- case CH_EPPI1_CH1:
- ret_irq = IRQ_EPPI1_CH1;
- break;
- case CH_EPPI2_CH0:
- ret_irq = IRQ_EPPI2_CH0;
- break;
- case CH_EPPI2_CH1:
- ret_irq = IRQ_EPPI2_CH1;
- break;
- case CH_PIXC_CH0:
- ret_irq = IRQ_PIXC_CH0;
- break;
- case CH_PIXC_CH1:
- ret_irq = IRQ_PIXC_CH1;
- break;
- case CH_PIXC_CH2:
- ret_irq = IRQ_PIXC_CH2;
- break;
- case CH_PVP_CPDOB:
- ret_irq = IRQ_PVP_CPDOB;
- break;
- case CH_PVP_CPDOC:
- ret_irq = IRQ_PVP_CPDOC;
- break;
- case CH_PVP_CPSTAT:
- ret_irq = IRQ_PVP_CPSTAT;
- break;
- case CH_PVP_CPCI:
- ret_irq = IRQ_PVP_CPCI;
- break;
- case CH_PVP_MPDO:
- ret_irq = IRQ_PVP_MPDO;
- break;
- case CH_PVP_MPDI:
- ret_irq = IRQ_PVP_MPDI;
- break;
- case CH_PVP_MPSTAT:
- ret_irq = IRQ_PVP_MPSTAT;
- break;
- case CH_PVP_MPCI:
- ret_irq = IRQ_PVP_MPCI;
- break;
- case CH_PVP_CPDOA:
- ret_irq = IRQ_PVP_CPDOA;
- break;
- case CH_MEM_STREAM0_SRC:
- case CH_MEM_STREAM0_DEST:
- ret_irq = IRQ_MDMAS0;
- break;
- case CH_MEM_STREAM1_SRC:
- case CH_MEM_STREAM1_DEST:
- ret_irq = IRQ_MDMAS1;
- break;
- case CH_MEM_STREAM2_SRC:
- case CH_MEM_STREAM2_DEST:
- ret_irq = IRQ_MDMAS2;
- break;
- case CH_MEM_STREAM3_SRC:
- case CH_MEM_STREAM3_DEST:
- ret_irq = IRQ_MDMAS3;
- break;
- }
- return ret_irq;
-}
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S
deleted file mode 100644
index fcb8f688a8b2..000000000000
--- a/arch/blackfin/mach-bf609/dpm.S
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#include <asm/context.S>
-
-#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
- /* switch stack to L1 scratch, prepare for ddr srfr */
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
- SP = P0;
-
- call _bf609_ddr_sr;
- call _bfin_hibernate_syscontrol;
-
- P0.H = HI(DPM0_RESTORE4);
- P0.L = LO(DPM0_RESTORE4);
- P1.H = _bf609_pm_data;
- P1.L = _bf609_pm_data;
- [P0] = P1;
-
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000010);
- R3.L = LO(0x00000010);
-
- bfin_init_pm_bench_cycles;
-
- [P0] = R3;
-
- SSYNC;
-ENDPROC(_enter_hibernate)
-
-/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
- * is disabled. This behavior differ from bf5xx serial processor.
- */
-ENTRY(_dummy_deepsleep)
- [--sp] = SYSCFG;
- [--sp] = (R7:0,P5:0);
- cli r0;
-
- /* get wake up interrupt ID */
- P0.l = LO(SEC_SCI_BASE + SEC_CSID);
- P0.h = HI(SEC_SCI_BASE + SEC_CSID);
- R0 = [P0];
-
- /* ACK wake up interrupt in SEC */
- P1.l = LO(SEC_END);
- P1.h = HI(SEC_END);
-
- [P1] = R0;
- SSYNC;
-
- /* restore EVT 11 entry */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _evt_evt11;
- p1.l = _evt_evt11;
-
- [p0] = p1;
- SSYNC;
-
- (R7:0,P5:0) = [sp++];
- SYSCFG = [sp++];
- RTI;
-ENDPROC(_dummy_deepsleep)
-
-ENTRY(_enter_deepsleep)
- LINK 0xC;
- [--sp] = (R7:0,P5:0);
-
- /* Change EVT 11 entry to dummy handler for wake up event */
- p0.h = hi(EVT11);
- p0.l = lo(EVT11);
- p1.h = _dummy_deepsleep;
- p1.l = _dummy_deepsleep;
-
- [p0] = p1;
-
- P0.H = HI(PM_STACK);
- P0.L = LO(PM_STACK);
-
- EX_SCRATCH_REG = SP;
- SP = P0;
-
- SSYNC;
-
- /* should put ddr to self refresh mode before sleep */
- call _bf609_ddr_sr;
-
- /* Set DPM controller to deep sleep mode */
- P0.H = HI(DPM0_CTL);
- P0.L = LO(DPM0_CTL);
- R3.H = HI(0x00000008);
- R3.L = LO(0x00000008);
- [P0] = R3;
- CSYNC;
-
- /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
- r0.l = 0x800;
- r0.h = 0;
- sti r0;
- SSYNC;
-
- bfin_init_pm_bench_cycles;
-
- /* Fall into deep sleep in idle*/
- idle;
- SSYNC;
-
- /* Restore PLL after wake up from deep sleep */
- call _bf609_resume_ccbuf;
-
- /* turn ddr out of self refresh mode */
- call _bf609_ddr_sr_exit;
-
- SP = EX_SCRATCH_REG;
-
- (R7:0,P5:0) = [SP++];
- UNLINK;
- RTS;
-ENDPROC(_enter_deepsleep)
-
-.section .text
-ENTRY(_bf609_hibernate)
- bfin_cpu_reg_save;
- bfin_core_mmr_save;
-
- P0.H = _bf609_pm_data;
- P0.L = _bf609_pm_data;
- R1.H = 0xDEAD;
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1;
- [P0++] = R2;
- [P0++] = SP;
-
- P1.H = _enter_hibernate;
- P1.L = _enter_hibernate;
-
- call (P1);
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-
-ENDPROC(_bf609_hibernate)
-
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
deleted file mode 100644
index 696786e9a531..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2012 Analog Devices Inc.
- * Licensed under the Clear BSD license.
- */
-
-/* This file should be up to date with:
- * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF609 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
-#define ANOMALY_16000003 (1)
-/* The EPPI Data Enable (DEN) Signal is Not Functional */
-#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
-/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
-#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
-/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
-#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
-/* DDR2 Memory Reads May Fail Intermittently */
-#define ANOMALY_16000007 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_16000008 (1)
-/* TestSET Instruction Cannot Be Interrupted */
-#define ANOMALY_16000009 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_16000010 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_16000011 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_16000012 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_16000013 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_16000014 (1)
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_16000015 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_16000017 (1)
-/* RSI Boot Cleanup Routine Does Not Clear Registers */
-#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
-/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
-#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
-#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
-/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
-#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
-/* Boot Code Fails to Enable Parity Fault Detection */
-#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
-/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
-#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
-/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
-#define ANOMALY_16000024 (1)
-/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
-#define ANOMALY_16000025 (1)
-/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Default SPI Master Boot Mode Setting is Incorrect */
-#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
-/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
-#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
-/* Interrupted Core Reads of MMRs May Cause Data Loss */
-#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
-/* Incorrect Default USB_PLL_OSC.PLLM Value */
-#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
-/* Core Reads of System MMRs May Cause the Core to Hang */
-#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
-/* PPI Data Underflow on First Word Not Reported in Certain Modes */
-#define ANOMALY_16000033 (1)
-/* CNV1 Red Pixel Substitution feature not functional in the PVP */
-#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
-/* IPF0 Output Port Color Separation feature not functional */
-#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
-/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
-#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
-/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
-#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
-/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
-#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
-/* CGU_STAT.PLOCKERR Bit May be Unreliable */
-#define ANOMALY_16000039 (1)
-/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
-#define ANOMALY_16000040 (1)
-/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
-#define ANOMALY_16000041 (1)
-/* Instruction Cache Failure When Parity Is Enabled */
-#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000481 (1)
-
-/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
-#define ANOMALY_05000491 ANOMALY_16000008
-#define ANOMALY_05000477 ANOMALY_16000009
-#define ANOMALY_05000443 ANOMALY_16000010
-#define ANOMALY_05000461 ANOMALY_16000011
-#define ANOMALY_05000426 ANOMALY_16000012
-#define ANOMALY_05000310 ANOMALY_16000013
-#define ANOMALY_05000245 ANOMALY_16000014
-#define ANOMALY_05000074 ANOMALY_16000015
-#define ANOMALY_05000416 ANOMALY_16000017
-
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h
deleted file mode 100644
index c897c2a2fbfa..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/bf609.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __MACH_BF609_H__
-#define __MACH_BF609_H__
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15 0x8000
-#define IMASK_IVG14 0x4000
-#define IMASK_IVG13 0x2000
-#define IMASK_IVG12 0x1000
-
-#define IMASK_IVG11 0x0800
-#define IMASK_IVG10 0x0400
-#define IMASK_IVG9 0x0200
-#define IMASK_IVG8 0x0100
-
-#define IMASK_IVG7 0x0080
-#define IMASK_IVGTMR 0x0040
-#define IMASK_IVGHW 0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS 4
-#define BFIN_DWAYS 2
-#define BFIN_DLINES 64
-#define BFIN_ISUBBANKS 4
-#define BFIN_IWAYS 4
-#define BFIN_ILINES 32
-
-#define WAY0_L 0x1
-#define WAY1_L 0x2
-#define WAY01_L 0x3
-#define WAY2_L 0x4
-#define WAY02_L 0x5
-#define WAY12_L 0x6
-#define WAY012_L 0x7
-
-#define WAY3_L 0x8
-#define WAY03_L 0x9
-#define WAY13_L 0xA
-#define WAY013_L 0xB
-
-#define WAY32_L 0xC
-#define WAY320_L 0xD
-#define WAY321_L 0xE
-#define WAYALL_L 0xF
-
-#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF609)
-# define CPU "BF609"
-# define CPUID 0x27fe /* temperary fake value */
-#endif
-
-#ifndef CPU
-#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
-#endif
-
-#endif /* __MACH_BF609_H__ */
diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
deleted file mode 100644
index 1fd398147fd9..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * mach/bfin_serial.h - Blackfin UART/Serial definitions
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_SERIAL_H__
-#define __BFIN_MACH_SERIAL_H__
-
-#define BFIN_UART_NR_PORTS 2
-#define BFIN_UART_TX_FIFO_SIZE 8
-
-#define BFIN_UART_BF60X_STYLE
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h
deleted file mode 100644
index b1a48c410711..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/blackfin.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#include "bf609.h"
-#include "anomaly.h"
-
-#include <asm/def_LPBlackfin.h>
-#ifdef CONFIG_BF609
-# include "defBF609.h"
-#endif
-
-#ifndef __ASSEMBLY__
-# include <asm/cdef_LPBlackfin.h>
-# ifdef CONFIG_BF609
-# include "cdefBF609.h"
-# endif
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
deleted file mode 100644
index c4f3fe19acda..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF609_H
-#define _CDEF_BF609_H
-
-/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
-#include "cdefBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-
-#endif /* _CDEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
deleted file mode 100644
index 102ee4025ac9..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
+++ /dev/null
@@ -1,3254 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _CDEF_BF60X_H
-#define _CDEF_BF60X_H
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-/* SEC0 Registers */
-#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL)
-#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
-#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID)
-#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
-#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL)
-#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
-
-#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL)
-#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
-
-#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8))
-#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
-
-#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8))
-#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
-
-/* RCU0 Registers */
-#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
-#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
-
-/* Watchdog Timer Registers */
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID)
-#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val)
-#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val)
-#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT)
-#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val)
-#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val)
-#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK)
-#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val)
-#define bfin_read_UART0_IER() bfin_read32(UART0_IER)
-#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val)
-#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val)
-#define bfin_read_UART0_THR() bfin_read32(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val)
-#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP)
-#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val)
-#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR)
-#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val)
-#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR)
-#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val)
-#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT)
-#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val)
-#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT)
-#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID)
-#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val)
-#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val)
-#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT)
-#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val)
-#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val)
-#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK)
-#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val)
-#define bfin_read_UART1_IER() bfin_read32(UART1_IER)
-#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val)
-#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val)
-#define bfin_read_UART1_THR() bfin_read32(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val)
-#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP)
-#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val)
-#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR)
-#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val)
-#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR)
-#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val)
-#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT)
-#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val)
-#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT)
-#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val)
-
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val)
-#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL)
-#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val)
-#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL)
-#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val)
-#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)
-#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)
-#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY)
-#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val)
-#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL)
-#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val)
-#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC)
-#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val)
-#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR)
-#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val)
-#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC)
-#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val)
-#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR)
-#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val)
-#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK)
-#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val)
-#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR)
-#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val)
-#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET)
-#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val)
-#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val)
-#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT)
-#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val)
-#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR)
-#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val)
-#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO)
-#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val)
-#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO)
-#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val)
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)
-#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL)
-#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val)
-#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL)
-#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val)
-#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK)
-#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)
-#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY)
-#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val)
-#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL)
-#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val)
-#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC)
-#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val)
-#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR)
-#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val)
-#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC)
-#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val)
-#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR)
-#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val)
-#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK)
-#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val)
-#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR)
-#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)
-#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET)
-#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val)
-#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val)
-#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT)
-#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val)
-#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR)
-#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val)
-#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO)
-#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val)
-#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO)
-#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val)
-
-/* Timer 0-7 registers */
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-
-
-
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT1 Registers */
-
-
-/* SMC Registers */
-#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
-#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
-#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
-#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
-#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
-#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
-#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
-#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
-#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
-#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
-#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
-#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
-#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
-#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
-#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
-#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
-#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
-#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
-#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
-#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
-#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
-#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
-#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
-#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
-#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
-#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
-#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
-
-/* DDR2 Memory Control Registers */
-#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
-#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
-#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
-#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
-#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
-#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
-#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
-#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
-#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
-#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
-#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
-#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
-#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
-#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
-#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
-#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
-#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
-#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
-#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
-#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR)
-#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT)
-#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val)
-#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT)
-#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val)
-#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT)
-#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val)
-#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT)
-#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR)
-#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT)
-#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val)
-#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT)
-#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val)
-#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT)
-#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val)
-#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT)
-#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR)
-#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT)
-#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val)
-#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT)
-#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val)
-#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT)
-#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val)
-#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT)
-#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR)
-#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT)
-#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val)
-#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT)
-#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val)
-#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT)
-#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val)
-#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT)
-#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR)
-#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT)
-#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val)
-#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT)
-#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val)
-#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT)
-#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val)
-#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT)
-#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR)
-#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT)
-#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val)
-#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT)
-#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val)
-#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT)
-#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val)
-#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT)
-#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR)
-#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT)
-#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val)
-#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT)
-#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val)
-#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT)
-#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val)
-#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT)
-#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR)
-#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT)
-#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val)
-#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT)
-#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val)
-#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT)
-#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val)
-#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT)
-#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR)
-#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT)
-#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val)
-#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT)
-#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val)
-#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT)
-#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val)
-#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT)
-#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR)
-#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT)
-#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val)
-#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT)
-#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val)
-#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT)
-#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val)
-#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT)
-#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR)
-#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT)
-#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val)
-#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT)
-#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val)
-#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT)
-#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val)
-#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT)
-#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR)
-#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT)
-#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val)
-#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT)
-#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val)
-#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT)
-#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val)
-#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT)
-#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR)
-#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val)
-#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT)
-#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val)
-#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT)
-#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val)
-#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT)
-#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val)
-#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT)
-#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR)
-#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val)
-#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT)
-#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val)
-#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT)
-#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val)
-#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT)
-#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val)
-#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT)
-#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR)
-#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val)
-#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT)
-#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val)
-#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT)
-#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val)
-#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT)
-#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val)
-#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT)
-#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR)
-#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val)
-#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT)
-#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val)
-#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT)
-#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val)
-#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT)
-#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val)
-#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT)
-#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR)
-#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val)
-#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT)
-#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val)
-#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT)
-#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val)
-#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT)
-#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val)
-#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT)
-#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR)
-#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
-#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT)
-#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
-#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT)
-#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
-#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT)
-#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
-#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT)
-#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR)
-#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
-#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT)
-#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
-#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT)
-#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
-#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT)
-#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
-#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT)
-#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR)
-#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT)
-#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
-#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT)
-#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
-#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT)
-#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
-#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT)
-#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR)
-#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
-#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT)
-#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
-#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT)
-#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
-#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT)
-#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
-#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT)
-#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
-
-
-/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
-
-#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG)
-#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG)
-#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
-#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
-#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
-#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
-#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
-
-#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG)
-#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG)
-#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
-#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
-#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
-#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
-#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
-
-
-/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
-
-#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR)
-#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val)
-#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG)
-#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val)
-#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT)
-#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY)
-#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val)
-#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT)
-#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val)
-#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY)
-#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR)
-#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS)
-#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR)
-#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val)
-#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG)
-#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val)
-#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT)
-#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY)
-#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val)
-#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT)
-#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val)
-#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY)
-#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR)
-#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS)
-#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
-
-#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR)
-#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val)
-#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG)
-#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val)
-#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT)
-#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY)
-#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val)
-#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT)
-#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val)
-#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY)
-#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val)
-#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
-#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
-#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR)
-#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val)
-#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS)
-#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
-#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
-#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
-#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR)
-#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val)
-#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG)
-#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val)
-#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT)
-#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY)
-#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val)
-#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT)
-#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val)
-#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY)
-#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val)
-#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
-#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
-#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
-#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR)
-#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val)
-#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS)
-#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
-#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
-#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
-#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
-
-
-/* DMA Channel 29 Registers */
-
-#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR)
-#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val)
-#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR)
-#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val)
-#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG)
-#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val)
-#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT)
-#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val)
-#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY)
-#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val)
-#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT)
-#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val)
-#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY)
-#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val)
-#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR)
-#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val)
-#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR)
-#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val)
-#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR)
-#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val)
-#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS)
-#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val)
-#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT)
-#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val)
-#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT)
-#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val)
-#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT)
-#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val)
-#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT)
-#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val)
-#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT)
-#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
-#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT)
-#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
-
-/* DMA Channel 30 Registers */
-
-#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR)
-#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
-#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR)
-#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
-#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG)
-#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
-#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT)
-#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
-#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY)
-#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
-#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT)
-#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
-#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY)
-#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
-#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR)
-#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
-#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR)
-#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
-#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR)
-#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
-#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS)
-#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
-#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT)
-#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
-#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT)
-#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
-#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT)
-#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
-#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT)
-#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
-#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT)
-#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
-#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT)
-#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
-
-/* DMA Channel 31 Registers */
-
-#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR)
-#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
-#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR)
-#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
-#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG)
-#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
-#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT)
-#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
-#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY)
-#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
-#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT)
-#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
-#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY)
-#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
-#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR)
-#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
-#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR)
-#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
-#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR)
-#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
-#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS)
-#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
-#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT)
-#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
-#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT)
-#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
-#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT)
-#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
-#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT)
-#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
-#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT)
-#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
-#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT)
-#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
-
-/* DMA Channel 32 Registers */
-
-#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
-#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
-#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR)
-#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
-#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG)
-#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
-#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT)
-#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
-#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY)
-#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
-#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT)
-#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
-#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY)
-#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
-#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR)
-#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
-#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR)
-#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
-#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR)
-#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
-#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS)
-#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
-#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT)
-#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
-#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT)
-#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
-#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT)
-#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
-#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT)
-#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
-#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT)
-#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
-#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT)
-#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
-
-/* DMA Channel 33 Registers */
-
-#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR)
-#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
-#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR)
-#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
-#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG)
-#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
-#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT)
-#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
-#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY)
-#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
-#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT)
-#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
-#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY)
-#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
-#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR)
-#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
-#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR)
-#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
-#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR)
-#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
-#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS)
-#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
-#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT)
-#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
-#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT)
-#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
-#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT)
-#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
-#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT)
-#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
-#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT)
-#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
-#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT)
-#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
-
-/* DMA Channel 34 Registers */
-
-#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR)
-#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
-#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR)
-#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
-#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG)
-#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
-#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT)
-#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
-#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY)
-#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
-#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT)
-#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
-#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY)
-#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
-#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR)
-#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
-#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR)
-#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
-#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR)
-#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
-#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS)
-#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
-#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT)
-#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
-#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT)
-#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
-#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT)
-#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
-#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT)
-#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
-#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT)
-#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
-#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT)
-#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
-
-/* DMA Channel 35 Registers */
-
-#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR)
-#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
-#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR)
-#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
-#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG)
-#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
-#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT)
-#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
-#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY)
-#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
-#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT)
-#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
-#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY)
-#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
-#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR)
-#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
-#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR)
-#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
-#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
-#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
-#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
-#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
-#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT)
-#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
-#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT)
-#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
-#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT)
-#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
-#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT)
-#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
-#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT)
-#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
-#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT)
-#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
-
-/* DMA Channel 36 Registers */
-
-#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR)
-#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
-#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR)
-#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
-#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG)
-#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
-#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT)
-#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
-#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY)
-#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
-#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT)
-#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
-#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY)
-#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
-#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR)
-#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
-#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR)
-#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
-#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR)
-#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
-#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS)
-#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
-#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT)
-#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
-#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT)
-#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
-#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT)
-#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
-#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT)
-#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
-#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT)
-#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
-#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT)
-#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
-
-/* DMA Channel 37 Registers */
-
-#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR)
-#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
-#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR)
-#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
-#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG)
-#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
-#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT)
-#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
-#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY)
-#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
-#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT)
-#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
-#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY)
-#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
-#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR)
-#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
-#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR)
-#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
-#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR)
-#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
-#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS)
-#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
-#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT)
-#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
-#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT)
-#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
-#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT)
-#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
-#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT)
-#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
-#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT)
-#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
-#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT)
-#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
-
-/* DMA Channel 38 Registers */
-
-#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR)
-#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
-#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR)
-#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
-#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG)
-#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
-#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT)
-#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
-#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY)
-#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
-#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT)
-#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
-#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY)
-#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
-#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR)
-#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
-#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR)
-#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
-#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR)
-#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
-#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS)
-#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
-#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT)
-#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
-#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT)
-#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
-#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT)
-#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
-#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT)
-#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
-#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT)
-#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
-#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT)
-#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
-
-/* DMA Channel 39 Registers */
-
-#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR)
-#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
-#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR)
-#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
-#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG)
-#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
-#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT)
-#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
-#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY)
-#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
-#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT)
-#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
-#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY)
-#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
-#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR)
-#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
-#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR)
-#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
-#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR)
-#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
-#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS)
-#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
-#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT)
-#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
-#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT)
-#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
-#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT)
-#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val)
-#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT)
-#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val)
-#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT)
-#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val)
-#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT)
-#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val)
-
-/* DMA Channel 40 Registers */
-
-#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR)
-#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val)
-#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR)
-#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val)
-#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG)
-#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val)
-#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT)
-#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val)
-#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY)
-#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val)
-#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT)
-#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val)
-#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY)
-#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val)
-#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR)
-#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val)
-#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR)
-#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val)
-#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR)
-#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val)
-#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS)
-#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val)
-#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT)
-#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val)
-#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT)
-#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val)
-#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT)
-#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val)
-#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT)
-#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val)
-#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT)
-#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val)
-#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT)
-#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val)
-
-/* DMA Channel 41 Registers */
-
-#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR)
-#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val)
-#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR)
-#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val)
-#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG)
-#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val)
-#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT)
-#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val)
-#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY)
-#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val)
-#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT)
-#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val)
-#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY)
-#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val)
-#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR)
-#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val)
-#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR)
-#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val)
-#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR)
-#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val)
-#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS)
-#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val)
-#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT)
-#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val)
-#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT)
-#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val)
-#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT)
-#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val)
-#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT)
-#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val)
-#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT)
-#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val)
-#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT)
-#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val)
-
-/* DMA Channel 42 Registers */
-
-#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR)
-#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val)
-#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR)
-#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val)
-#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG)
-#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val)
-#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT)
-#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val)
-#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY)
-#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val)
-#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT)
-#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val)
-#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY)
-#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val)
-#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR)
-#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val)
-#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR)
-#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val)
-#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR)
-#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val)
-#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS)
-#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val)
-#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT)
-#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val)
-#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT)
-#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val)
-#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT)
-#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val)
-#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT)
-#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val)
-#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT)
-#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val)
-#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT)
-#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val)
-
-/* DMA Channel 43 Registers */
-
-#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR)
-#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val)
-#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR)
-#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val)
-#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG)
-#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val)
-#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT)
-#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val)
-#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY)
-#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val)
-#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT)
-#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val)
-#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY)
-#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val)
-#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR)
-#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val)
-#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR)
-#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val)
-#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR)
-#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val)
-#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS)
-#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val)
-#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT)
-#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val)
-#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT)
-#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val)
-#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT)
-#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val)
-#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT)
-#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val)
-#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT)
-#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val)
-#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT)
-#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val)
-
-/* DMA Channel 44 Registers */
-
-#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR)
-#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val)
-#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR)
-#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val)
-#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG)
-#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val)
-#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT)
-#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val)
-#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY)
-#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val)
-#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT)
-#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val)
-#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY)
-#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val)
-#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR)
-#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val)
-#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR)
-#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val)
-#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR)
-#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val)
-#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS)
-#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
-#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT)
-#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
-#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT)
-#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
-#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT)
-#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
-#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT)
-#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
-#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT)
-#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
-#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT)
-#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
-
-/* DMA Channel 45 Registers */
-
-#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR)
-#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
-#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR)
-#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
-#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG)
-#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
-#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT)
-#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
-#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY)
-#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
-#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT)
-#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
-#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY)
-#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
-#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR)
-#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
-#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR)
-#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
-#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR)
-#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
-#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS)
-#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
-#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT)
-#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
-#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT)
-#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
-#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT)
-#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
-#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT)
-#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
-#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT)
-#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
-#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT)
-#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
-
-/* DMA Channel 46 Registers */
-
-#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR)
-#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
-#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR)
-#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
-#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG)
-#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
-#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT)
-#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
-#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY)
-#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
-#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT)
-#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
-#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY)
-#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
-#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR)
-#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
-#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR)
-#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
-#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR)
-#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
-#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS)
-#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
-#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT)
-#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
-#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT)
-#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
-#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT)
-#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
-#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT)
-#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
-#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT)
-#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
-#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT)
-#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
-
-
-/* EPPI1 Registers */
-
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
-
-/* Port Interrubfin_read_()t 4 Registers (32-bit) */
-
-#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET)
-#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val)
-#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR)
-#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val)
-#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST)
-#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val)
-#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN)
-#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val)
-#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET)
-#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val)
-#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR)
-#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val)
-#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET)
-#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val)
-#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR)
-#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val)
-#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE)
-#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val)
-#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH)
-#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val)
-
-/* Port Interrubfin_read_()t 5 Registers (32-bit) */
-
-#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET)
-#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val)
-#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR)
-#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val)
-#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST)
-#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val)
-#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN)
-#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val)
-#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET)
-#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val)
-#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR)
-#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val)
-#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET)
-#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val)
-#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR)
-#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val)
-#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE)
-#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val)
-#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH)
-#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER)
-#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val)
-#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET)
-#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val)
-#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR)
-#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
-#define bfin_read_PORTA() bfin_read32(PORTA)
-#define bfin_write_PORTA(val) bfin_write32(PORTA, val)
-#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET)
-#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR)
-#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val)
-#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val)
-#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET)
-#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val)
-#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR)
-#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val)
-#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
-#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL)
-#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val)
-#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL)
-#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val)
-#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET)
-#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val)
-#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR)
-#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
-#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK)
-#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val)
-#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID)
-#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val)
-
-
-
-/* Port B Registers */
-#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER)
-#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val)
-#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET)
-#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val)
-#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR)
-#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
-#define bfin_read_PORTB() bfin_read32(PORTB)
-#define bfin_write_PORTB(val) bfin_write32(PORTB, val)
-#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET)
-#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR)
-#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val)
-#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val)
-#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET)
-#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val)
-#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR)
-#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val)
-#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
-#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL)
-#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val)
-#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL)
-#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val)
-#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET)
-#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val)
-#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR)
-#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
-#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK)
-#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val)
-#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID)
-#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val)
-
-
-/* Port C Registers */
-#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER)
-#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val)
-#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET)
-#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val)
-#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR)
-#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
-#define bfin_read_PORTC() bfin_read32(PORTC)
-#define bfin_write_PORTC(val) bfin_write32(PORTC, val)
-#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET)
-#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR)
-#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val)
-#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val)
-#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET)
-#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val)
-#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR)
-#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val)
-#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
-#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL)
-#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val)
-#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL)
-#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val)
-#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET)
-#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val)
-#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR)
-#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
-#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK)
-#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val)
-#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID)
-#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val)
-
-
-/* Port D Registers */
-#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
-#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val)
-#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET)
-#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
-#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR)
-#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
-#define bfin_read_PORTD() bfin_read32(PORTD)
-#define bfin_write_PORTD(val) bfin_write32(PORTD, val)
-#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET)
-#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR)
-#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val)
-#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val)
-#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET)
-#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val)
-#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR)
-#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val)
-#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
-#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL)
-#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val)
-#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL)
-#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val)
-#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET)
-#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val)
-#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR)
-#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
-#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK)
-#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val)
-#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID)
-#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val)
-
-
-/* Port E Registers */
-#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER)
-#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val)
-#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET)
-#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val)
-#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR)
-#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
-#define bfin_read_PORTE() bfin_read32(PORTE)
-#define bfin_write_PORTE(val) bfin_write32(PORTE, val)
-#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET)
-#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR)
-#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val)
-#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val)
-#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET)
-#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val)
-#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR)
-#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val)
-#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
-#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL)
-#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val)
-#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL)
-#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val)
-#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET)
-#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val)
-#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR)
-#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
-#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK)
-#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val)
-#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID)
-#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val)
-
-
-/* Port F Registers */
-#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val)
-#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET)
-#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val)
-#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR)
-#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
-#define bfin_read_PORTF() bfin_read32(PORTF)
-#define bfin_write_PORTF(val) bfin_write32(PORTF, val)
-#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET)
-#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR)
-#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val)
-#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val)
-#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET)
-#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val)
-#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR)
-#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val)
-#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
-#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL)
-#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val)
-#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL)
-#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val)
-#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET)
-#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val)
-#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR)
-#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
-#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK)
-#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val)
-#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID)
-#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val)
-
-
-/* Port G Registers */
-#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val)
-#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET)
-#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
-#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR)
-#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
-#define bfin_read_PORTG() bfin_read32(PORTG)
-#define bfin_write_PORTG(val) bfin_write32(PORTG, val)
-#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET)
-#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR)
-#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val)
-#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val)
-#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET)
-#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val)
-#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR)
-#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val)
-#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
-#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL)
-#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val)
-#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL)
-#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val)
-#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET)
-#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val)
-#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR)
-#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
-#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK)
-#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val)
-#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID)
-#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val)
-
-
-
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
-
-/* RSI Register */
-#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
-#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT)
-#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val)
-#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK)
-#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val)
-#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-
-/* usb register */
-#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
-#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
-#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
-
-#endif /* _CDEF_BF60X_H */
-
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
deleted file mode 100644
index 8045ade34370..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF609.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF609_H
-#define _DEF_BF609_H
-
-/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
-#include "defBF60x_base.h"
-
-/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
-/* =========================
- PIXC Registers
- ========================= */
-
-/* =========================
- PIXC0
- ========================= */
-#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */
-#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */
-#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */
-#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
-#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */
-#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
-#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */
-#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */
-#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
-#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */
-#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
-#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */
-#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */
-#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */
-#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */
-#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */
-#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */
-#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */
-#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */
-#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */
-
-/* =========================
- PVP Registers
- ========================= */
-
-/* =========================
- PVP0
- ========================= */
-#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */
-#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */
-#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */
-#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */
-#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */
-#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */
-#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */
-#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */
-#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */
-#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */
-#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */
-#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */
-#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */
-#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */
-#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */
-#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */
-#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */
-#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */
-#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */
-#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */
-#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */
-#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */
-#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */
-#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */
-#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */
-#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */
-#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */
-#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */
-#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */
-#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */
-#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */
-#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */
-#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */
-#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */
-#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */
-#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */
-#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */
-#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */
-#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */
-#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */
-#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */
-#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */
-#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */
-#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */
-#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */
-#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */
-#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */
-#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */
-#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */
-#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */
-#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */
-#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */
-#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */
-#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */
-#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */
-#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */
-#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */
-#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */
-#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */
-#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */
-#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */
-#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */
-#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */
-#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */
-#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */
-#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */
-#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */
-#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */
-#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */
-#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */
-#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */
-#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */
-#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */
-#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */
-#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */
-#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
-#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
-#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */
-#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */
-#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
-#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV3_C34 0xFFC1A3B4 /* PVP0 Coefficient 3, 4 */
-#define PVP0_CNV0_C40C41 0xFFC1A238 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV1_C40C41 0xFFC1A2B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV2_C40C41 0xFFC1A338 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV3_C40C41 0xFFC1A3B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
-#define PVP0_CNV0_C42C43 0xFFC1A23C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV1_C42C43 0xFFC1A2BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV2_C42C43 0xFFC1A33C /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV3_C42C43 0xFFC1A3BC /* PVP0 Coefficients 4, 2 and 4, 3 */
-#define PVP0_CNV0_C44 0xFFC1A240 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV1_C44 0xFFC1A2C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV2_C44 0xFFC1A340 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV3_C44 0xFFC1A3C0 /* PVP0 Coefficient 4, 4 */
-#define PVP0_CNV0_SCALE 0xFFC1A244 /* PVP0 Scaling factor */
-#define PVP0_CNV1_SCALE 0xFFC1A2C4 /* PVP0 Scaling factor */
-#define PVP0_CNV2_SCALE 0xFFC1A344 /* PVP0 Scaling factor */
-#define PVP0_CNV3_SCALE 0xFFC1A3C4 /* PVP0 Scaling factor */
-#define PVP0_THC0_CFG 0xFFC1A400 /* PVP0 Configuration */
-#define PVP0_THC1_CFG 0xFFC1A500 /* PVP0 Configuration */
-#define PVP0_THC0_CTL 0xFFC1A404 /* PVP0 Control */
-#define PVP0_THC1_CTL 0xFFC1A504 /* PVP0 Control */
-#define PVP0_THC0_HFCNT 0xFFC1A408 /* PVP0 Number of frames */
-#define PVP0_THC1_HFCNT 0xFFC1A508 /* PVP0 Number of frames */
-#define PVP0_THC0_RMAXREP 0xFFC1A40C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC1_RMAXREP 0xFFC1A50C /* PVP0 Maximum number of RLE reports */
-#define PVP0_THC0_CMINVAL 0xFFC1A410 /* PVP0 Min clip value */
-#define PVP0_THC1_CMINVAL 0xFFC1A510 /* PVP0 Min clip value */
-#define PVP0_THC0_CMINTH 0xFFC1A414 /* PVP0 Clip Min Threshold */
-#define PVP0_THC1_CMINTH 0xFFC1A514 /* PVP0 Clip Min Threshold */
-#define PVP0_THC0_CMAXTH 0xFFC1A418 /* PVP0 Clip Max Threshold */
-#define PVP0_THC1_CMAXTH 0xFFC1A518 /* PVP0 Clip Max Threshold */
-#define PVP0_THC0_CMAXVAL 0xFFC1A41C /* PVP0 Max clip value */
-#define PVP0_THC1_CMAXVAL 0xFFC1A51C /* PVP0 Max clip value */
-#define PVP0_THC0_TH0 0xFFC1A420 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH0 0xFFC1A520 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH1 0xFFC1A424 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH1 0xFFC1A524 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH2 0xFFC1A428 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH2 0xFFC1A528 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH3 0xFFC1A42C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH3 0xFFC1A52C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH4 0xFFC1A430 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH4 0xFFC1A530 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH5 0xFFC1A434 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH5 0xFFC1A534 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH6 0xFFC1A438 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH6 0xFFC1A538 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH7 0xFFC1A43C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH7 0xFFC1A53C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH8 0xFFC1A440 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH8 0xFFC1A540 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH9 0xFFC1A444 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH9 0xFFC1A544 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH10 0xFFC1A448 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH10 0xFFC1A548 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH11 0xFFC1A44C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH11 0xFFC1A54C /* PVP0 Threshold Value */
-#define PVP0_THC0_TH12 0xFFC1A450 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH12 0xFFC1A550 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH13 0xFFC1A454 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH13 0xFFC1A554 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH14 0xFFC1A458 /* PVP0 Threshold Value */
-#define PVP0_THC1_TH14 0xFFC1A558 /* PVP0 Threshold Value */
-#define PVP0_THC0_TH15 0xFFC1A45C /* PVP0 Threshold Value */
-#define PVP0_THC1_TH15 0xFFC1A55C /* PVP0 Threshold Value */
-#define PVP0_THC0_HHPOS 0xFFC1A460 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_HHPOS 0xFFC1A560 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_HVPOS 0xFFC1A464 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_HVPOS 0xFFC1A564 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_HHCNT 0xFFC1A468 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_HHCNT 0xFFC1A568 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_HVCNT 0xFFC1A46C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_HVCNT 0xFFC1A56C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_RHPOS 0xFFC1A470 /* PVP0 Window start X-coordinate */
-#define PVP0_THC1_RHPOS 0xFFC1A570 /* PVP0 Window start X-coordinate */
-#define PVP0_THC0_RVPOS 0xFFC1A474 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC1_RVPOS 0xFFC1A574 /* PVP0 Window start Y-coordinate */
-#define PVP0_THC0_RHCNT 0xFFC1A478 /* PVP0 Window width in X dimension */
-#define PVP0_THC1_RHCNT 0xFFC1A578 /* PVP0 Window width in X dimension */
-#define PVP0_THC0_RVCNT 0xFFC1A47C /* PVP0 Window width in Y dimension */
-#define PVP0_THC1_RVCNT 0xFFC1A57C /* PVP0 Window width in Y dimension */
-#define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */
-#define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */
-#define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */
-#define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */
-#define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */
-#define PVP0_THC0_RREP_STAT 0xFFC1A4C4 /* PVP0 Number of RLE Reports */
-#define PVP0_THC1_RREP_STAT 0xFFC1A5C4 /* PVP0 Number of RLE Reports */
-#define PVP0_PMA_CFG 0xFFC1A600 /* PVP0 PMA Configuration Register */
-
-#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
deleted file mode 100644
index 3933e912cacd..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ /dev/null
@@ -1,3596 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the Clear BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF60X_H
-#define _DEF_BF60X_H
-
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
-/* ************************************************************** */
-
-
-/* =========================
- CNT Registers
- ========================= */
-
-/* =========================
- CNT0
- ========================= */
-#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */
-#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */
-#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */
-#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */
-#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */
-#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */
-#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */
-#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */
-
-
-/* =========================
- RSI Registers
- ========================= */
-
-#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
-#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
-#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
-#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
-#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
-#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
-#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
-#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
-#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
-#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
-#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
-#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
-#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
-#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
-#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
-#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
-#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */
-#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
-#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */
-#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
-#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
-#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
-#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
-#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
-#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
-#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
-#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */
-#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */
-#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */
-#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */
-
-/* =========================
- CAN Registers
- ========================= */
-
-/* =========================
- CAN0
- ========================= */
-#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */
-#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */
-#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */
-#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */
-#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */
-#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */
-#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */
-#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */
-#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */
-#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */
-#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
-#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */
-#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */
-#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */
-#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */
-#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */
-#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */
-#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */
-#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */
-#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */
-#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */
-#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
-#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */
-#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */
-#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */
-#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */
-#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */
-#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */
-#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */
-#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */
-#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */
-#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */
-#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */
-#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */
-#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */
-#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */
-#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */
-#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */
-#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */
-#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */
-#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */
-#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */
-#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */
-#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */
-#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */
-#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */
-#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */
-#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */
-#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */
-
-/* =========================
- LINK PORT Registers
- ========================= */
-#define LP0_CTL 0xFFC01000 /* LP0 Control Register */
-#define LP0_STAT 0xFFC01004 /* LP0 Status Register */
-#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */
-#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */
-#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */
-#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */
-#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */
-#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */
-#define LP1_CTL 0xFFC01100 /* LP1 Control Register */
-#define LP1_STAT 0xFFC01104 /* LP1 Status Register */
-#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */
-#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */
-#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */
-#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */
-#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */
-#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */
-#define LP2_CTL 0xFFC01200 /* LP2 Control Register */
-#define LP2_STAT 0xFFC01204 /* LP2 Status Register */
-#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */
-#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */
-#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */
-#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */
-#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */
-#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */
-#define LP3_CTL 0xFFC01300 /* LP3 Control Register */
-#define LP3_STAT 0xFFC01304 /* LP3 Status Register */
-#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */
-#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */
-#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */
-#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */
-#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */
-#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
- TIMER Registers
- ========================= */
-#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */
-#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */
-#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */
-#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */
-#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */
-#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */
-#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */
-#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */
-#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */
-#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */
-#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */
-#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */
-#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */
-#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */
-#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */
-#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */
-#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */
-
-/* =========================
- TIMER0~7
- ========================= */
-#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */
-#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */
-#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */
-#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */
-#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */
-
-#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */
-#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */
-#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */
-#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */
-#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */
-
-#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */
-#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */
-#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */
-#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */
-#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */
-
-#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */
-#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */
-#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */
-#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */
-#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */
-
-#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */
-#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */
-#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */
-#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */
-#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */
-
-#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */
-#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */
-#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */
-#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */
-#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */
-
-#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */
-#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */
-#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */
-#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */
-#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */
-
-#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */
-#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */
-#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */
-#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */
-#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */
-
-/* =========================
- CRC Registers
- ========================= */
-
-/* =========================
- CRC0
- ========================= */
-#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */
-#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */
-#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */
-#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */
-#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */
-#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */
-#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */
-
-/* =========================
- CRC1
- ========================= */
-#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */
-#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */
-#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */
-#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */
-#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */
-#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */
-#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */
-
-/* =========================
- TWI Registers
- ========================= */
-
-/* =========================
- TWI0
- ========================= */
-#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
-#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */
-#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */
-#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */
-#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */
-#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */
-#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */
-#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */
-#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */
-#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */
-#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */
-#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */
-#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */
-
-/* =========================
- TWI1
- ========================= */
-#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
-#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */
-#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
-#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
-#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
-#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
-#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
-#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
-#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */
-#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */
-#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */
-#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */
-#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */
-
-
-/* =========================
- UART Registers
- ========================= */
-
-/* =========================
- UART0
- ========================= */
-#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
-#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
-#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
-#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
-#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
-#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */
-#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
-#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
-#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
-#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
-#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */
-#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
-#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
-#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */
-#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */
-
-/* =========================
- UART1
- ========================= */
-#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
-#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
-#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
-#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
-#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
-#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */
-#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
-#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
-#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
-#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
-#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */
-#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
-#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
-#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */
-#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */
-
-
-/* =========================
- PORT Registers
- ========================= */
-
-/* =========================
- PORTA
- ========================= */
-#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */
-#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */
-#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */
-#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */
-#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */
-#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */
-#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */
-#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */
-#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */
-#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */
-#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */
-#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */
-#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */
-#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */
-#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */
-#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */
-#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */
-#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */
-#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */
-
-/* =========================
- PORTB
- ========================= */
-#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */
-#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */
-#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */
-#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */
-#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */
-#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */
-#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */
-#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */
-#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */
-#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */
-#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */
-#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */
-#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */
-#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */
-#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */
-#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */
-#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */
-#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */
-#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */
-
-/* =========================
- PORTC
- ========================= */
-#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */
-#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */
-#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */
-#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */
-#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */
-#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */
-#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */
-#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */
-#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */
-#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */
-#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */
-#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */
-#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */
-#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */
-#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */
-#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */
-#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */
-#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */
-#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */
-
-/* =========================
- PORTD
- ========================= */
-#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */
-#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */
-#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */
-#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */
-#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */
-#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */
-#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */
-#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */
-#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */
-#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */
-#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */
-#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */
-#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */
-#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */
-#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */
-#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */
-#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */
-#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */
-#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */
-
-/* =========================
- PORTE
- ========================= */
-#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */
-#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */
-#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */
-#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */
-#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */
-#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */
-#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */
-#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */
-#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */
-#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */
-#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */
-#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */
-#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */
-#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */
-#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */
-#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */
-#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */
-#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */
-#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */
-
-/* =========================
- PORTF
- ========================= */
-#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */
-#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */
-#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */
-#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */
-#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */
-#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */
-#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */
-#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */
-#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */
-#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */
-#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */
-#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */
-#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */
-#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */
-#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */
-#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */
-#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */
-#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */
-#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */
-
-/* =========================
- PORTG
- ========================= */
-#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */
-#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */
-#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */
-#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */
-#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */
-#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */
-#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */
-#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */
-#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */
-#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */
-#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */
-#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */
-#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */
-#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */
-#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */
-#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */
-#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */
-#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
-#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
-
-/* ==================================================
- Pads Controller Registers
- ================================================== */
-
-/* =========================
- PADS0
- ========================= */
-#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */
-#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */
-#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */
-
-/* =========================
- PINT Registers
- ========================= */
-
-/* =========================
- PINT0
- ========================= */
-#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */
-#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */
-#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */
-#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */
-#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */
-#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */
-#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */
-#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */
-#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */
-#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */
-
-/* =========================
- PINT1
- ========================= */
-#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
-#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
-#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */
-#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
-#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
-#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
-#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
-#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
-#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
-#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
-
-/* =========================
- PINT2
- ========================= */
-#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */
-#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */
-#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */
-#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */
-#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */
-#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */
-#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */
-#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */
-#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */
-#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */
-
-/* =========================
- PINT3
- ========================= */
-#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */
-#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */
-#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */
-#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */
-#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */
-#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */
-#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */
-#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */
-#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */
-#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */
-
-/* =========================
- PINT4
- ========================= */
-#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */
-#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */
-#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */
-#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */
-#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */
-#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */
-#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */
-#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */
-#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */
-#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */
-
-/* =========================
- PINT5
- ========================= */
-#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */
-#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */
-#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */
-#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */
-#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */
-#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */
-#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */
-#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */
-#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */
-#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */
-
-
-/* =========================
- SMC Registers
- ========================= */
-
-/* =========================
- SMC0
- ========================= */
-#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */
-#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */
-#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */
-#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */
-#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */
-#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */
-#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */
-#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */
-#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */
-#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */
-#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */
-#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */
-#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */
-#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */
-
-
-/* =========================
- WDOG Registers
- ========================= */
-
-/* =========================
- WDOG0
- ========================= */
-#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */
-#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */
-#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
-#define WDOG_CTL WDOG0_CTL
-#define WDOG_CNT WDOG0_CNT
-#define WDOG_STAT WDOG0_STAT
-
-/* =========================
- WDOG1
- ========================= */
-#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
-#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
-#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================
- SDU Registers
- ========================= */
-
-/* =========================
- SDU0
- ========================= */
-#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */
-#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */
-#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */
-#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */
-#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */
-#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */
-#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */
-#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */
-#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */
-#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
-#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */
-#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */
-
-
-/* =========================
- EMAC Registers
- ========================= */
-/* =========================
- EMAC0
- ========================= */
-#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
-#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */
-#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */
-#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */
-#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */
-#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */
-#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */
-#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */
-#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */
-#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */
-#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */
-#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */
-#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */
-#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */
-#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */
-#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */
-#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */
-#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */
-#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */
-#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */
-#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */
-#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */
-#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */
-#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */
-#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */
-#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */
-#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */
-#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */
-#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */
-#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */
-#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */
-#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */
-#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */
-#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */
-#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */
-#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */
-#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */
-#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */
-#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */
-#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */
-#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */
-#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */
-#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */
-#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */
-#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */
-#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */
-#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */
-#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */
-#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */
-#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */
-#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */
-#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */
-#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */
-#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */
-#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */
-#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */
-#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */
-#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */
-#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */
-#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */
-#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */
-#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */
-#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */
-#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */
-#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */
-#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */
-#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */
-#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */
-#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */
-#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */
-#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */
-#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */
-#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */
-#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */
-#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */
-#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */
-#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */
-#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */
-#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */
-#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */
-#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */
-#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */
-#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */
-#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */
-#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */
-#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */
-#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */
-#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */
-#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */
-#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */
-#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */
-#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */
-#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */
-#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */
-#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */
-#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */
-#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */
-#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */
-#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */
-#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */
-#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */
-#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */
-#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */
-#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */
-#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */
-#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */
-#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */
-#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */
-#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */
-#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */
-
-/* =========================
- EMAC1
- ========================= */
-#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
-#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */
-#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */
-#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */
-#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */
-#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */
-#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */
-#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */
-#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */
-#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */
-#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */
-#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */
-#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */
-#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */
-#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */
-#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */
-#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */
-#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */
-#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */
-#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */
-#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */
-#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */
-#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */
-#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */
-#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */
-#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */
-#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
-#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
-#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
-#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
-#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
-#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */
-#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */
-#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */
-#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */
-#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */
-#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */
-#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */
-#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */
-#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */
-#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */
-#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */
-#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */
-#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */
-#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */
-#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */
-#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */
-#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */
-#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */
-#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */
-#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */
-#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */
-#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */
-#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */
-#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */
-#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */
-#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */
-#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */
-#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
-#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
-#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
-#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */
-#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */
-#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */
-#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */
-#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */
-#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */
-#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
-#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */
-#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */
-#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */
-#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */
-#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */
-#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */
-#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */
-#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
-#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
-#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */
-#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
-#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */
-#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */
-#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */
-#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */
-#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */
-#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
-#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
-#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */
-#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
-#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */
-#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */
-#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */
-#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */
-#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
-#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */
-#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */
-#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */
-#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */
-#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */
-#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */
-#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */
-#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */
-#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */
-#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */
-#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */
-#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */
-#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */
-#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */
-#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
-#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */
-#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */
-#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */
-#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
-#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
-#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */
-#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */
-#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */
-#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */
-#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */
-#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */
-#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */
-#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */
-#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */
-#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */
-#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */
-#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */
-#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */
-#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */
-#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */
-#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */
-#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */
-
-
-/* =========================
- SPI Registers
- ========================= */
-
-/* =========================
- SPI0
- ========================= */
-#define SPI0_REGBASE 0xFFC40400
-#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */
-#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */
-#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */
-#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */
-#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */
-#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */
-#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */
-#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */
-#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */
-#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */
-#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */
-#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */
-#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */
-#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */
-#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */
-#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */
-#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */
-#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
- SPI1
- ========================= */
-#define SPI1_REGBASE 0xFFC40500
-#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */
-#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */
-#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */
-#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */
-#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */
-#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */
-#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */
-#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */
-#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */
-#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */
-#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */
-#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */
-#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */
-#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */
-#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */
-#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */
-#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */
-#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
- SPORT Registers
- ========================= */
-
-/* =========================
- SPORT0
- ========================= */
-#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */
-#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */
-#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */
-#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */
-#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */
-#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */
-#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */
-#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */
-#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */
-#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */
-#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */
-#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */
-#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */
-#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */
-#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */
-#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT1
- ========================= */
-#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */
-#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */
-#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */
-#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */
-#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */
-#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */
-#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */
-#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */
-#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */
-#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */
-#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */
-#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */
-#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */
-#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */
-#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */
-#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- SPORT2
- ========================= */
-#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */
-#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */
-#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */
-#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */
-#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */
-#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */
-#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */
-#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */
-#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */
-#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */
-#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
-#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
-#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
-#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
-#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
-#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */
-#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */
-#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */
-#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */
-#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */
-#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
-#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */
-
-/* =========================
- EPPI Registers
- ========================= */
-
-/* =========================
- EPPI0
- ========================= */
-#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */
-#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */
-#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */
-#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */
-#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */
-#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */
-#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */
-#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */
-#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */
-#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */
-#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */
-#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */
-#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */
-
-/* =========================
- EPPI1
- ========================= */
-#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */
-#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */
-#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */
-#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */
-#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */
-#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */
-#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */
-#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */
-#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */
-#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */
-#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */
-#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */
-#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */
-
-/* =========================
- EPPI2
- ========================= */
-#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */
-#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */
-#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */
-#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */
-#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */
-#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */
-#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */
-#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */
-#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */
-#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */
-#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */
-#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */
-#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */
-
-
-
-/* =========================
- DDE Registers
- ========================= */
-
-/* =========================
- DMA0
- ========================= */
-#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */
-#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */
-#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */
-#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
-#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */
-#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
-#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */
-#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */
-#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */
-#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */
-#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */
-#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */
-#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */
-#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */
-#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */
-#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA1
- ========================= */
-#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */
-#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */
-#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */
-#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
-#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */
-#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
-#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */
-#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */
-#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */
-#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */
-#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */
-#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */
-#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */
-#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */
-#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */
-#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA2
- ========================= */
-#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */
-#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */
-#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */
-#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
-#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */
-#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
-#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */
-#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */
-#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */
-#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */
-#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */
-#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */
-#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */
-#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */
-#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */
-#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA3
- ========================= */
-#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */
-#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */
-#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */
-#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
-#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */
-#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
-#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */
-#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */
-#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */
-#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */
-#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */
-#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */
-#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */
-#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */
-#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */
-#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA4
- ========================= */
-#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */
-#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */
-#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */
-#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
-#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */
-#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
-#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */
-#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */
-#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */
-#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */
-#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */
-#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */
-#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */
-#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */
-#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */
-#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA5
- ========================= */
-#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */
-#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */
-#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */
-#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
-#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */
-#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
-#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */
-#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */
-#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */
-#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */
-#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */
-#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */
-#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */
-#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */
-#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */
-#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA6
- ========================= */
-#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
-#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
-#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */
-#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
-#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */
-#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
-#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
-#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
-#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
-#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */
-#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */
-#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */
-#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
-#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
-#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
-#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA7
- ========================= */
-#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */
-#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */
-#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */
-#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
-#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */
-#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
-#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */
-#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */
-#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */
-#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */
-#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */
-#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */
-#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */
-#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */
-#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */
-#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA8
- ========================= */
-#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */
-#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */
-#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */
-#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
-#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */
-#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
-#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */
-#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */
-#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */
-#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */
-#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */
-#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */
-#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */
-#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */
-#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */
-#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA9
- ========================= */
-#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */
-#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */
-#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */
-#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
-#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */
-#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
-#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */
-#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */
-#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */
-#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */
-#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */
-#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */
-#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */
-#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */
-#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */
-#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA10
- ========================= */
-#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
-#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
-#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */
-#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
-#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */
-#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
-#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
-#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
-#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
-#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */
-#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */
-#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */
-#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
-#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
-#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
-#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA11
- ========================= */
-#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */
-#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */
-#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */
-#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
-#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */
-#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
-#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */
-#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */
-#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */
-#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */
-#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */
-#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */
-#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */
-#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */
-#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */
-#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA12
- ========================= */
-#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */
-#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */
-#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */
-#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
-#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */
-#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
-#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */
-#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */
-#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */
-#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */
-#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */
-#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */
-#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */
-#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */
-#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */
-#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA13
- ========================= */
-#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */
-#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */
-#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */
-#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
-#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */
-#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
-#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */
-#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */
-#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */
-#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */
-#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */
-#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */
-#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */
-#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */
-#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */
-#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA14
- ========================= */
-#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */
-#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */
-#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */
-#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
-#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */
-#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
-#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */
-#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */
-#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */
-#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */
-#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */
-#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */
-#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */
-#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */
-#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */
-#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA15
- ========================= */
-#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */
-#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */
-#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */
-#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
-#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */
-#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
-#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */
-#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */
-#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */
-#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */
-#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */
-#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */
-#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */
-#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */
-#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */
-#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA16
- ========================= */
-#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */
-#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */
-#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */
-#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
-#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */
-#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
-#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */
-#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */
-#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */
-#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */
-#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */
-#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */
-#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */
-#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */
-#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */
-#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA17
- ========================= */
-#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */
-#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */
-#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */
-#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
-#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */
-#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
-#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */
-#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */
-#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */
-#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */
-#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */
-#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */
-#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */
-#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */
-#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */
-#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA18
- ========================= */
-#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */
-#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */
-#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */
-#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
-#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */
-#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
-#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */
-#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */
-#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */
-#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */
-#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */
-#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */
-#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */
-#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */
-#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */
-#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA19
- ========================= */
-#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */
-#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */
-#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */
-#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
-#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */
-#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
-#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */
-#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */
-#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */
-#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */
-#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */
-#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */
-#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */
-#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */
-#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */
-#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA20
- ========================= */
-#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
-#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
-#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */
-#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
-#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */
-#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
-#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
-#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
-#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
-#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */
-#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */
-#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
-#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
-#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
-#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
-#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA21
- ========================= */
-#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
-#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
-#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */
-#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
-#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */
-#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
-#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
-#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
-#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
-#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */
-#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */
-#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */
-#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
-#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
-#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
-#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA22
- ========================= */
-#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */
-#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */
-#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */
-#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
-#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */
-#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
-#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */
-#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */
-#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */
-#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */
-#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */
-#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */
-#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */
-#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */
-#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */
-#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA23
- ========================= */
-#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
-#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
-#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */
-#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
-#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */
-#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
-#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
-#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
-#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
-#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */
-#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */
-#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */
-#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
-#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
-#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
-#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA24
- ========================= */
-#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */
-#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */
-#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */
-#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
-#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */
-#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
-#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */
-#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */
-#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */
-#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */
-#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */
-#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */
-#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */
-#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */
-#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */
-#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA25
- ========================= */
-#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */
-#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */
-#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */
-#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
-#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */
-#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
-#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */
-#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */
-#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */
-#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */
-#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */
-#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */
-#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */
-#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */
-#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */
-#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA26
- ========================= */
-#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */
-#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */
-#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */
-#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
-#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */
-#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
-#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */
-#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */
-#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */
-#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */
-#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */
-#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */
-#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */
-#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */
-#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */
-#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA27
- ========================= */
-#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */
-#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */
-#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */
-#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
-#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */
-#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
-#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */
-#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */
-#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */
-#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */
-#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */
-#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */
-#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */
-#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */
-#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */
-#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA28
- ========================= */
-#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */
-#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */
-#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */
-#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
-#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */
-#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
-#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */
-#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */
-#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */
-#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */
-#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */
-#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */
-#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */
-#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */
-#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */
-#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA29
- ========================= */
-#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */
-#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
-#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */
-#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
-#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */
-#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
-#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */
-#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */
-#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */
-#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */
-#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */
-#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */
-#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */
-#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */
-#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */
-#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA30
- ========================= */
-#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */
-#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
-#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */
-#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
-#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */
-#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
-#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */
-#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */
-#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */
-#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */
-#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */
-#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */
-#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */
-#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */
-#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */
-#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA31
- ========================= */
-#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */
-#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
-#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */
-#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
-#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */
-#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
-#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */
-#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */
-#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */
-#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */
-#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */
-#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */
-#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */
-#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */
-#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */
-#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA32
- ========================= */
-#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */
-#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
-#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */
-#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
-#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */
-#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
-#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */
-#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */
-#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */
-#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */
-#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */
-#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */
-#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */
-#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */
-#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */
-#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA33
- ========================= */
-#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */
-#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
-#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */
-#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
-#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */
-#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
-#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */
-#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */
-#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */
-#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */
-#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */
-#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */
-#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */
-#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */
-#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */
-#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA34
- ========================= */
-#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */
-#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
-#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */
-#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
-#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */
-#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
-#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */
-#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */
-#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */
-#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */
-#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */
-#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */
-#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */
-#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */
-#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */
-#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA35
- ========================= */
-#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */
-#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */
-#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */
-#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
-#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */
-#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
-#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */
-#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */
-#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */
-#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */
-#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */
-#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */
-#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */
-#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */
-#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */
-#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA36
- ========================= */
-#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */
-#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */
-#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */
-#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
-#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */
-#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
-#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */
-#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */
-#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */
-#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */
-#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */
-#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */
-#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */
-#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */
-#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */
-#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA37
- ========================= */
-#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */
-#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */
-#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */
-#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
-#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */
-#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
-#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */
-#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */
-#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */
-#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */
-#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */
-#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */
-#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */
-#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */
-#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */
-#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA38
- ========================= */
-#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */
-#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */
-#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */
-#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
-#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */
-#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
-#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */
-#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */
-#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */
-#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */
-#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */
-#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */
-#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */
-#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */
-#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */
-#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA39
- ========================= */
-#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */
-#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */
-#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */
-#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
-#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */
-#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
-#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */
-#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */
-#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */
-#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */
-#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */
-#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */
-#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */
-#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */
-#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */
-#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA40
- ========================= */
-#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */
-#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */
-#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */
-#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
-#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */
-#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
-#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */
-#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */
-#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */
-#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */
-#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */
-#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */
-#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */
-#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */
-#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */
-#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA41
- ========================= */
-#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */
-#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */
-#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */
-#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
-#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */
-#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
-#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */
-#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */
-#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */
-#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */
-#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */
-#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */
-#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */
-#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */
-#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */
-#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA42
- ========================= */
-#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */
-#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */
-#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */
-#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
-#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */
-#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
-#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */
-#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */
-#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */
-#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */
-#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */
-#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */
-#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */
-#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */
-#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */
-#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA43
- ========================= */
-#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */
-#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */
-#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */
-#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
-#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */
-#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
-#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */
-#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */
-#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */
-#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */
-#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */
-#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */
-#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */
-#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */
-#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */
-#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA44
- ========================= */
-#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */
-#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */
-#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */
-#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
-#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */
-#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
-#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */
-#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */
-#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */
-#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */
-#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */
-#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */
-#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */
-#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */
-#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */
-#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA45
- ========================= */
-#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */
-#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */
-#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */
-#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
-#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */
-#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
-#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */
-#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */
-#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */
-#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */
-#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */
-#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */
-#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */
-#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */
-#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */
-#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
- DMA46
- ========================= */
-#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */
-#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */
-#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */
-#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
-#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */
-#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
-#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */
-#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */
-#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */
-#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */
-#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */
-#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */
-#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */
-#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */
-#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */
-#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */
-
-
-/********************************************************************************
- DMA Alias Definitions
- ********************************************************************************/
-#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR)
-#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR)
-#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG)
-#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT)
-#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY)
-#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT)
-#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY)
-#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR)
-#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR)
-#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR)
-#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS)
-#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT)
-#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT)
-#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT)
-#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT)
-#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT)
-#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR)
-#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR)
-#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG)
-#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT)
-#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY)
-#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT)
-#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY)
-#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR)
-#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR)
-#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR)
-#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS)
-#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT)
-#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT)
-#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT)
-#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT)
-#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT)
-#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR)
-#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR)
-#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG)
-#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT)
-#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY)
-#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT)
-#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY)
-#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR)
-#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR)
-#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR)
-#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS)
-#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT)
-#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT)
-#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT)
-#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT)
-#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT)
-#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR)
-#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR)
-#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG)
-#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT)
-#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY)
-#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT)
-#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY)
-#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR)
-#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR)
-#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR)
-#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS)
-#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT)
-#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT)
-#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT)
-#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT)
-#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT)
-#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR)
-#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR)
-#define MDMA2_DEST_CONFIG (DMA26_CONFIG)
-#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT)
-#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY)
-#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT)
-#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY)
-#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR)
-#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR)
-#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR)
-#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS)
-#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT)
-#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT)
-#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT)
-#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT)
-#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT)
-#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT)
-#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR)
-#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR)
-#define MDMA2_SRC_CONFIG (DMA25_CONFIG)
-#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT)
-#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY)
-#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT)
-#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY)
-#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR)
-#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR)
-#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR)
-#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS)
-#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT)
-#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT)
-#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT)
-#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT)
-#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT)
-#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT)
-#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR)
-#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR)
-#define MDMA3_DEST_CONFIG (DMA28_CONFIG)
-#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT)
-#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY)
-#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT)
-#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY)
-#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR)
-#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR)
-#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR)
-#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS)
-#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT)
-#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT)
-#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT)
-#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT)
-#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT)
-#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT)
-#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR)
-#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR)
-#define MDMA3_SRC_CONFIG (DMA27_CONFIG)
-#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT)
-#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY)
-#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT)
-#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY)
-#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR)
-#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR)
-#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR)
-#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS)
-#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT)
-#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT)
-#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT)
-#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT)
-#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT)
-#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT)
-
-
-/* =========================
- DMC Registers
- ========================= */
-
-/* =========================
- DMC0
- ========================= */
-#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
-#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
-#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
-#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
-#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
-#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
-#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
-#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
-#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
-#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
-#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
-#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
-#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
-#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
-#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
-#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
-#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
-
-#define DEVSZ_64 0x000 /* DMC External Bank Size = 64Mbit */
-#define DEVSZ_128 0x100 /* DMC External Bank Size = 128Mbit */
-#define DEVSZ_256 0x200 /* DMC External Bank Size = 256Mbit */
-#define DEVSZ_512 0x300 /* DMC External Bank Size = 512Mbit */
-#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
-#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
-
-/* =========================
- L2CTL Registers
- ========================= */
-
-/* =========================
- L2CTL0
- ========================= */
-#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */
-#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */
-#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */
-#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */
-#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */
-#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */
-#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */
-#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Register */
-#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */
-#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */
-#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */
-#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */
-#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */
-#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */
-#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */
-#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */
-#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */
-#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */
-#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */
-#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */
-
-
-/* =========================
- SEC Registers
- ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Core Interface (SCI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-
-#define SEC_SCI_BASE 0xFFCA4400
-#define SEC_SCI_OFF 0x40
-#define SEC_CCTL 0x0 /* SEC Core Control Register n */
-#define SEC_CSTAT 0x4 /* SEC Core Status Register n */
-#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */
-#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */
-#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */
-#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */
-#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */
-#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */
-
-#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
-#define bfin_write_SEC_SCI(n, reg, val) \
- bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Fault Management Interface (SFI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */
-#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */
-#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */
-#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */
-#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */
-#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */
-#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */
-#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */
-#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */
-#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Global Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */
-#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */
-#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */
-#define SEC_END 0xFFCA400C /* SEC Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC Source Interface (SSI) Register Definitions
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */
-#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */
-#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */
-#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */
-#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */
-#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_CCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */
-#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */
-#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */
-#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */
-#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */
-#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */
-#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */
-#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CACT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */
-#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CGMSK Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */
-#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CPLVL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_CSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_CSID_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */
-#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */
-#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */
-#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */
-#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */
-#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */
-#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */
-#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */
-#define SEC_FCTL_EN 0x00000001 /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */
-#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */
-#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */
-#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FSID Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FSID_SID 0x000000FF /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_FEND Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */
-#define SEC_FEND_SID 0x000000FF /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GCTL_LOCK 0x80000000 /* Lock */
-#define SEC_GCTL_RESET 0x00000002 /* Reset */
-#define SEC_GCTL_EN 0x00000001 /* Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_GSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */
-#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */
-#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */
-#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */
-#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */
-#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */
-#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_RAISE Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_END Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SCTL Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SCTL_LOCK 0x80000000 /* Lock */
-#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */
-#define SEC_SCTL_GRP 0x000F0000 /* Group Select */
-#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */
-#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */
-#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */
-#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */
-#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */
-#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
- SEC_SSTAT Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------ */
-#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */
-#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */
-#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */
-#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */
-#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */
-#define SEC_SSTAT_ERR 0x00000002 /* Error */
-
-
-/* =========================
- RCU Registers
- ========================= */
-
-/* =========================
- RCU0
- ========================= */
-#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
-#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
-#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
-#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
-#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */
-#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */
-#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
-#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
-#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
-#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
-
-
-/* =========================
- CGU0
- ========================= */
-#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */
-#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */
-#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */
-#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
-
-
-/* =========================
- DPM Registers
- ========================= */
-
-/* =========================
- DPM0
- ========================= */
-#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
-#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
-#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
-#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
-#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
-#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
-#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
-#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
-#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
-#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
-#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
-#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
-#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
-#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
-#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
-#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
-#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
-#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
-#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
-#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
-#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
-#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
-#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
-#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
-#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
-#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
-#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
-#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
-
-
-/* =========================
- DBG Registers
- ========================= */
-
-/* USB register */
-#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */
-#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */
-#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */
-#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */
-#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */
-#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */
-#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */
-#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */
-#define USB_FRAME 0xFFCC100C /* USB Frame Number */
-#define USB_INDEX 0xFFCC100E /* USB Index */
-#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */
-#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */
-#define USB_EP_NI0_TXMAXP 0xFFCC1010
-#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */
-#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */
-#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */
-#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */
-#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */
-#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */
-#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */
-#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */
-#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */
-#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */
-#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */
-#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */
-#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */
-#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */
-#define USB_EP0_FIFO 0xFFCC1020
-#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */
-#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */
-#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */
-#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */
-#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */
-#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */
-#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */
-#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */
-#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */
-#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */
-#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */
-#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */
-#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */
-#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */
-#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */
-#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */
-#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */
-#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */
-#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */
-#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */
-#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */
-#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */
-#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */
-#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */
-#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */
-#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */
-#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */
-#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */
-#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */
-#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */
-#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */
-#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */
-#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */
-#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */
-#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */
-#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */
-#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */
-#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */
-#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */
-#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */
-#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */
-#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */
-#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */
-#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */
-#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */
-#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */
-#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */
-#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */
-#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */
-#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */
-#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */
-#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */
-#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */
-#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */
-#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */
-#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */
-#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */
-#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */
-#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */
-#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */
-#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */
-#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */
-#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */
-#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */
-#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */
-#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */
-#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */
-#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */
-#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */
-#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */
-#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */
-#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */
-#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */
-#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */
-#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */
-#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */
-#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */
-#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */
-#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */
-#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */
-#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */
-#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */
-#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */
-#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */
-#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */
-#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */
-#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */
-#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */
-#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */
-#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */
-#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */
-#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */
-#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */
-#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */
-#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */
-#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */
-#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */
-#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */
-#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */
-#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */
-#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */
-#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */
-#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */
-#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */
-#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */
-#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */
-#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */
-#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */
-#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */
-#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */
-#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
-#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */
-#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */
-#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */
-#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */
-#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */
-#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */
-#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */
-#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */
-#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */
-#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */
-#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */
-#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */
-#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */
-#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */
-#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */
-#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */
-#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */
-#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */
-#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */
-#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */
-#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */
-#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */
-#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */
-#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */
-#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */
-#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */
-#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */
-#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */
-#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */
-#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */
-#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */
-#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */
-#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */
-#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */
-#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */
-#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */
-#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */
-#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */
-#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */
-#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */
-#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */
-#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */
-#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */
-#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
-#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */
-#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
-#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */
-#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
-
-
-
-/* =========================
- CHIPID
- ========================= */
-
-#define CHIPID 0xffc00014
-/* CHIPID Masks */
-#define CHIPID_VERSION 0xF0000000
-#define CHIPID_FAMILY 0x0FFFF000
-#define CHIPID_MANUFACTURE 0x00000FFE
-
-
-#endif /* _DEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h
deleted file mode 100644
index 872d141ca119..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/dma.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* mach/dma.h - arch-specific DMA defines
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_TX 0
-#define CH_SPORT0_RX 1
-#define CH_SPORT1_TX 2
-#define CH_SPORT1_RX 3
-#define CH_SPORT2_TX 4
-#define CH_SPORT2_RX 5
-#define CH_SPI0_TX 6
-#define CH_SPI0_RX 7
-#define CH_SPI1_TX 8
-#define CH_SPI1_RX 9
-#define CH_RSI 10
-#define CH_SDU 11
-#define CH_LP0 13
-#define CH_LP1 14
-#define CH_LP2 15
-#define CH_LP3 16
-#define CH_UART0_TX 17
-#define CH_UART0_RX 18
-#define CH_UART1_TX 19
-#define CH_UART1_RX 20
-#define CH_MEM_STREAM0_SRC_CRC0 21
-#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
-#define CH_MEM_STREAM0_DEST_CRC0 22
-#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
-#define CH_MEM_STREAM1_SRC_CRC1 23
-#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
-#define CH_MEM_STREAM1_DEST_CRC1 24
-#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
-#define CH_MEM_STREAM2_SRC 25
-#define CH_MEM_STREAM2_DEST 26
-#define CH_MEM_STREAM3_SRC 27
-#define CH_MEM_STREAM3_DEST 28
-#define CH_EPPI0_CH0 29
-#define CH_EPPI0_CH1 30
-#define CH_EPPI1_CH0 31
-#define CH_EPPI1_CH1 32
-#define CH_EPPI2_CH0 33
-#define CH_EPPI2_CH1 34
-#define CH_PIXC_CH0 35
-#define CH_PIXC_CH1 36
-#define CH_PIXC_CH2 37
-#define CH_PVP_CPDOB 38
-#define CH_PVP_CPDOC 39
-#define CH_PVP_CPSTAT 40
-#define CH_PVP_CPCI 41
-#define CH_PVP_MPDO 42
-#define CH_PVP_MPDI 43
-#define CH_PVP_MPSTAT 44
-#define CH_PVP_MPCI 45
-#define CH_PVP_CPDOA 46
-
-#define MAX_DMA_CHANNELS 47
-#define MAX_DMA_SUSPEND_CHANNELS 0
-#define DMA_MMR_SIZE_32
-
-#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
-#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
-#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
-#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
-#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
-#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
-#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
-#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
-#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
-#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
-#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
-#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
-#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
-#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
-#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
-
-#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
-#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
-#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
-#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
-#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
-#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
-
-#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
-#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
-#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
-#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
-#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
-#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
-#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
-#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
-#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
-#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
-#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
-#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
-#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
-#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
-#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
-#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
-#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
-#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
-#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
deleted file mode 100644
index 07182513e794..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 112
-
-#define GPIO_PA0 0
-#define GPIO_PA1 1
-#define GPIO_PA2 2
-#define GPIO_PA3 3
-#define GPIO_PA4 4
-#define GPIO_PA5 5
-#define GPIO_PA6 6
-#define GPIO_PA7 7
-#define GPIO_PA8 8
-#define GPIO_PA9 9
-#define GPIO_PA10 10
-#define GPIO_PA11 11
-#define GPIO_PA12 12
-#define GPIO_PA13 13
-#define GPIO_PA14 14
-#define GPIO_PA15 15
-#define GPIO_PB0 16
-#define GPIO_PB1 17
-#define GPIO_PB2 18
-#define GPIO_PB3 19
-#define GPIO_PB4 20
-#define GPIO_PB5 21
-#define GPIO_PB6 22
-#define GPIO_PB7 23
-#define GPIO_PB8 24
-#define GPIO_PB9 25
-#define GPIO_PB10 26
-#define GPIO_PB11 27
-#define GPIO_PB12 28
-#define GPIO_PB13 29
-#define GPIO_PB14 30
-#define GPIO_PB15 31
-#define GPIO_PC0 32
-#define GPIO_PC1 33
-#define GPIO_PC2 34
-#define GPIO_PC3 35
-#define GPIO_PC4 36
-#define GPIO_PC5 37
-#define GPIO_PC6 38
-#define GPIO_PC7 39
-#define GPIO_PC8 40
-#define GPIO_PC9 41
-#define GPIO_PC10 42
-#define GPIO_PC11 43
-#define GPIO_PC12 44
-#define GPIO_PC13 45
-#define GPIO_PC14 46
-#define GPIO_PC15 47
-#define GPIO_PD0 48
-#define GPIO_PD1 49
-#define GPIO_PD2 50
-#define GPIO_PD3 51
-#define GPIO_PD4 52
-#define GPIO_PD5 53
-#define GPIO_PD6 54
-#define GPIO_PD7 55
-#define GPIO_PD8 56
-#define GPIO_PD9 57
-#define GPIO_PD10 58
-#define GPIO_PD11 59
-#define GPIO_PD12 60
-#define GPIO_PD13 61
-#define GPIO_PD14 62
-#define GPIO_PD15 63
-#define GPIO_PE0 64
-#define GPIO_PE1 65
-#define GPIO_PE2 66
-#define GPIO_PE3 67
-#define GPIO_PE4 68
-#define GPIO_PE5 69
-#define GPIO_PE6 70
-#define GPIO_PE7 71
-#define GPIO_PE8 72
-#define GPIO_PE9 73
-#define GPIO_PE10 74
-#define GPIO_PE11 75
-#define GPIO_PE12 76
-#define GPIO_PE13 77
-#define GPIO_PE14 78
-#define GPIO_PE15 79
-#define GPIO_PF0 80
-#define GPIO_PF1 81
-#define GPIO_PF2 82
-#define GPIO_PF3 83
-#define GPIO_PF4 84
-#define GPIO_PF5 85
-#define GPIO_PF6 86
-#define GPIO_PF7 87
-#define GPIO_PF8 88
-#define GPIO_PF9 89
-#define GPIO_PF10 90
-#define GPIO_PF11 91
-#define GPIO_PF12 92
-#define GPIO_PF13 93
-#define GPIO_PF14 94
-#define GPIO_PF15 95
-#define GPIO_PG0 96
-#define GPIO_PG1 97
-#define GPIO_PG2 98
-#define GPIO_PG3 99
-#define GPIO_PG4 100
-#define GPIO_PG5 101
-#define GPIO_PG6 102
-#define GPIO_PG7 103
-#define GPIO_PG8 104
-#define GPIO_PG9 105
-#define GPIO_PG10 106
-#define GPIO_PG11 107
-#define GPIO_PG12 108
-#define GPIO_PG13 109
-#define GPIO_PG14 110
-#define GPIO_PG15 111
-
-
-#define BFIN_GPIO_PINT 1
-#define NR_PINT_SYS_IRQS 6
-#define NR_PINTS 112
-
-
-#ifndef __ASSEMBLY__
-
-struct gpio_port_t {
- unsigned long port_fer;
- unsigned long port_fer_set;
- unsigned long port_fer_clear;
- unsigned long data;
- unsigned long data_set;
- unsigned long data_clear;
- unsigned long dir;
- unsigned long dir_set;
- unsigned long dir_clear;
- unsigned long inen;
- unsigned long inen_set;
- unsigned long inen_clear;
- unsigned long port_mux;
- unsigned long toggle;
- unsigned long polar;
- unsigned long polar_set;
- unsigned long polar_clear;
- unsigned long lock;
- unsigned long spare;
- unsigned long revid;
-};
-
-#endif
-
-#include <mach-common/ports-a.h>
-#include <mach-common/ports-b.h>
-#include <mach-common/ports-c.h>
-#include <mach-common/ports-d.h>
-#include <mach-common/ports-e.h>
-#include <mach-common/ports-f.h>
-#include <mach-common/ports-g.h>
-
-#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
deleted file mode 100644
index d1cb6a86f80a..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BF60x_IRQ_H_
-#define _BF60x_IRQ_H_
-
-#include <mach-common/irq.h>
-
-#define NR_PERI_INTS (5 * 32)
-
-#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */
-#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */
-#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */
-#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */
-#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
-#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */
-#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */
-#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */
-#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */
-#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */
-#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)
-
-#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */
-#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */
-#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */
-#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */
-#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */
-#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */
-#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */
-#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */
-#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */
-#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */
-#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
-#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */
-#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */
-#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */
-#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */
-#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
-#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
-#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */
-#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */
-#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */
-#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
-#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */
-#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */
-#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */
-#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */
-#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */
-#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */
-#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */
-#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */
-#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */
-#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */
-#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */
-#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */
-#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
-#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */
-#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */
-#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */
-#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */
-#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */
-#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
-#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */
-#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */
-#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */
-#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */
-#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */
-#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
-#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */
-#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */
-#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */
-/* -- RESERVED -- 65 DMA12 Data (Reserved) */
-/* -- RESERVED -- 66 Reserved */
-/* -- RESERVED -- 67 Reserved */
-#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */
-/* -- RESERVED -- 69 EMAC0 Power (Reserved) */
-#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */
-/* -- RESERVED -- 71 EMAC1 Power (Reserved) */
-#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */
-#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */
-#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */
-#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */
-#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */
-#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */
-#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */
-#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */
-#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */
-#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */
-#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */
-#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */
-#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
-#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */
-#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
-#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
-#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0
-#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */
-#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */
-#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
-#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
-#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1
-#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */
-#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */
-#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */
-#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */
-#define IRQ_MDMAS2 IRQ_MDMA2_DEST
-#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */
-#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */
-#define IRQ_MDMAS3 IRQ_MDMA3_DEST
-#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */
-#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */
-#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */
-#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */
-#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */
-#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */
-#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */
-#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */
-#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */
-#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */
-#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */
-#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */
-#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */
-#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
-#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
-#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */
-#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */
-#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */
-#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
-#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
-#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
-#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
-#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
-#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */
-#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */
-#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */
-#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */
-#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */
-#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */
-#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */
-#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */
-#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */
-/* -- RESERVED -- 130 Reserved */
-#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */
-/* -- RESERVED -- 132 Reserved */
-#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */
-#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */
-#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */
-#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */
-#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */
-#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */
-#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */
-
-#define SYS_IRQS IRQ_SWU6
-
-#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
-#define IRQ_PA0 BFIN_PA_IRQ(0)
-#define IRQ_PA1 BFIN_PA_IRQ(1)
-#define IRQ_PA2 BFIN_PA_IRQ(2)
-#define IRQ_PA3 BFIN_PA_IRQ(3)
-#define IRQ_PA4 BFIN_PA_IRQ(4)
-#define IRQ_PA5 BFIN_PA_IRQ(5)
-#define IRQ_PA6 BFIN_PA_IRQ(6)
-#define IRQ_PA7 BFIN_PA_IRQ(7)
-#define IRQ_PA8 BFIN_PA_IRQ(8)
-#define IRQ_PA9 BFIN_PA_IRQ(9)
-#define IRQ_PA10 BFIN_PA_IRQ(10)
-#define IRQ_PA11 BFIN_PA_IRQ(11)
-#define IRQ_PA12 BFIN_PA_IRQ(12)
-#define IRQ_PA13 BFIN_PA_IRQ(13)
-#define IRQ_PA14 BFIN_PA_IRQ(14)
-#define IRQ_PA15 BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0 BFIN_PB_IRQ(0)
-#define IRQ_PB1 BFIN_PB_IRQ(1)
-#define IRQ_PB2 BFIN_PB_IRQ(2)
-#define IRQ_PB3 BFIN_PB_IRQ(3)
-#define IRQ_PB4 BFIN_PB_IRQ(4)
-#define IRQ_PB5 BFIN_PB_IRQ(5)
-#define IRQ_PB6 BFIN_PB_IRQ(6)
-#define IRQ_PB7 BFIN_PB_IRQ(7)
-#define IRQ_PB8 BFIN_PB_IRQ(8)
-#define IRQ_PB9 BFIN_PB_IRQ(9)
-#define IRQ_PB10 BFIN_PB_IRQ(10)
-#define IRQ_PB11 BFIN_PB_IRQ(11)
-#define IRQ_PB12 BFIN_PB_IRQ(12)
-#define IRQ_PB13 BFIN_PB_IRQ(13)
-#define IRQ_PB14 BFIN_PB_IRQ(14)
-#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
-
-#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0 BFIN_PC_IRQ(0)
-#define IRQ_PC1 BFIN_PC_IRQ(1)
-#define IRQ_PC2 BFIN_PC_IRQ(2)
-#define IRQ_PC3 BFIN_PC_IRQ(3)
-#define IRQ_PC4 BFIN_PC_IRQ(4)
-#define IRQ_PC5 BFIN_PC_IRQ(5)
-#define IRQ_PC6 BFIN_PC_IRQ(6)
-#define IRQ_PC7 BFIN_PC_IRQ(7)
-#define IRQ_PC8 BFIN_PC_IRQ(8)
-#define IRQ_PC9 BFIN_PC_IRQ(9)
-#define IRQ_PC10 BFIN_PC_IRQ(10)
-#define IRQ_PC11 BFIN_PC_IRQ(11)
-#define IRQ_PC12 BFIN_PC_IRQ(12)
-#define IRQ_PC13 BFIN_PC_IRQ(13)
-#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
-#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
-
-#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0 BFIN_PD_IRQ(0)
-#define IRQ_PD1 BFIN_PD_IRQ(1)
-#define IRQ_PD2 BFIN_PD_IRQ(2)
-#define IRQ_PD3 BFIN_PD_IRQ(3)
-#define IRQ_PD4 BFIN_PD_IRQ(4)
-#define IRQ_PD5 BFIN_PD_IRQ(5)
-#define IRQ_PD6 BFIN_PD_IRQ(6)
-#define IRQ_PD7 BFIN_PD_IRQ(7)
-#define IRQ_PD8 BFIN_PD_IRQ(8)
-#define IRQ_PD9 BFIN_PD_IRQ(9)
-#define IRQ_PD10 BFIN_PD_IRQ(10)
-#define IRQ_PD11 BFIN_PD_IRQ(11)
-#define IRQ_PD12 BFIN_PD_IRQ(12)
-#define IRQ_PD13 BFIN_PD_IRQ(13)
-#define IRQ_PD14 BFIN_PD_IRQ(14)
-#define IRQ_PD15 BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0 BFIN_PE_IRQ(0)
-#define IRQ_PE1 BFIN_PE_IRQ(1)
-#define IRQ_PE2 BFIN_PE_IRQ(2)
-#define IRQ_PE3 BFIN_PE_IRQ(3)
-#define IRQ_PE4 BFIN_PE_IRQ(4)
-#define IRQ_PE5 BFIN_PE_IRQ(5)
-#define IRQ_PE6 BFIN_PE_IRQ(6)
-#define IRQ_PE7 BFIN_PE_IRQ(7)
-#define IRQ_PE8 BFIN_PE_IRQ(8)
-#define IRQ_PE9 BFIN_PE_IRQ(9)
-#define IRQ_PE10 BFIN_PE_IRQ(10)
-#define IRQ_PE11 BFIN_PE_IRQ(11)
-#define IRQ_PE12 BFIN_PE_IRQ(12)
-#define IRQ_PE13 BFIN_PE_IRQ(13)
-#define IRQ_PE14 BFIN_PE_IRQ(14)
-#define IRQ_PE15 BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0 BFIN_PF_IRQ(0)
-#define IRQ_PF1 BFIN_PF_IRQ(1)
-#define IRQ_PF2 BFIN_PF_IRQ(2)
-#define IRQ_PF3 BFIN_PF_IRQ(3)
-#define IRQ_PF4 BFIN_PF_IRQ(4)
-#define IRQ_PF5 BFIN_PF_IRQ(5)
-#define IRQ_PF6 BFIN_PF_IRQ(6)
-#define IRQ_PF7 BFIN_PF_IRQ(7)
-#define IRQ_PF8 BFIN_PF_IRQ(8)
-#define IRQ_PF9 BFIN_PF_IRQ(9)
-#define IRQ_PF10 BFIN_PF_IRQ(10)
-#define IRQ_PF11 BFIN_PF_IRQ(11)
-#define IRQ_PF12 BFIN_PF_IRQ(12)
-#define IRQ_PF13 BFIN_PF_IRQ(13)
-#define IRQ_PF14 BFIN_PF_IRQ(14)
-#define IRQ_PF15 BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0 BFIN_PG_IRQ(0)
-#define IRQ_PG1 BFIN_PG_IRQ(1)
-#define IRQ_PG2 BFIN_PG_IRQ(2)
-#define IRQ_PG3 BFIN_PG_IRQ(3)
-#define IRQ_PG4 BFIN_PG_IRQ(4)
-#define IRQ_PG5 BFIN_PG_IRQ(5)
-#define IRQ_PG6 BFIN_PG_IRQ(6)
-#define IRQ_PG7 BFIN_PG_IRQ(7)
-#define IRQ_PG8 BFIN_PG_IRQ(8)
-#define IRQ_PG9 BFIN_PG_IRQ(9)
-#define IRQ_PG10 BFIN_PG_IRQ(10)
-#define IRQ_PG11 BFIN_PG_IRQ(11)
-#define IRQ_PG12 BFIN_PG_IRQ(12)
-#define IRQ_PG13 BFIN_PG_IRQ(13)
-#define IRQ_PG14 BFIN_PG_IRQ(14)
-#define IRQ_PG15 BFIN_PG_IRQ(15)
-
-#define GPIO_IRQ_BASE IRQ_PA0
-
-#define NR_MACH_IRQS (IRQ_PG15 + 1)
-
-#define SEC_SCTL_PRIO_OFFSET 8
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-
-extern u8 sec_int_priority[];
-
-/*
- * gpio pint registers layout
- */
-struct bfin_pint_regs {
- u32 mask_set;
- u32 mask_clear;
- u32 request;
- u32 assign;
- u32 edge_set;
- u32 edge_clear;
- u32 invert_set;
- u32 invert_clear;
- u32 pinstate;
- u32 latch;
- u32 __pad0[2];
-};
-
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h
deleted file mode 100644
index 20b65bfc5311..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/mem_map.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * BF60x memory map
- *
- * Copyright 2011 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_MACH_MEM_MAP_H__
-#define __BFIN_MACH_MEM_MAP_H__
-
-#ifndef __BFIN_MEM_MAP_H__
-# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
-#endif
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
-#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START 0xC8000000
-#define BOOT_ROM_LENGTH 0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF60x processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#define L1_CODE_LENGTH 0x10000
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#define L1_CODE_LENGTH 0x14000
-#endif
-
-#define L1_CODE_START 0xFFA00000
-#define L1_DATA_A_START 0xFF800000
-#define L1_DATA_B_START 0xFF900000
-
-
-#define COREA_L1_SCRATCH_START 0xFFB00000
-#define COREB_L1_SCRATCH_START 0xFF700000
-
-#define COREB_L1_CODE_START 0xFF600000
-#define COREB_L1_DATA_A_START 0xFF400000
-#define COREB_L1_DATA_B_START 0xFF500000
-
-#define COREB_L1_CODE_LENGTH 0x14000
-#define COREB_L1_DATA_A_LENGTH 0x8000
-#define COREB_L1_DATA_B_LENGTH 0x8000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS 1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS 2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH 0x8000
-#define L1_DATA_B_LENGTH 0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS 0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#define L2_START 0xC8080000
-#define L2_LENGTH 0x40000
-
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h
deleted file mode 100644
index 1857a4a0f262..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/pll.h
+++ /dev/null
@@ -1 +0,0 @@
-/* #include <mach-common/pll.h> */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
deleted file mode 100644
index a1efd936dd30..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/pm.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#ifndef __MACH_BF609_PM_H__
-#define __MACH_BF609_PM_H__
-
-#include <linux/suspend.h>
-#include <linux/platform_device.h>
-
-extern int bfin609_pm_enter(suspend_state_t state);
-extern int bf609_pm_prepare(void);
-extern void bf609_pm_finish(void);
-
-void bf609_hibernate(void);
-void bfin_sec_raise_irq(unsigned int sid);
-void coreb_enable(void);
-
-int bf609_nor_flash_init(struct platform_device *pdev);
-void bf609_nor_flash_exit(struct platform_device *pdev);
-#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
deleted file mode 100644
index c48bb71a55ce..000000000000
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/*
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-/* EMAC RMII Port Mux */
-#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_MII0_PTPPPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-
-#define P_RMII0 {\
- P_MII0_ETxD0, \
- P_MII0_ETxD1, \
- P_MII0_ETxEN, \
- P_MII0_ERxD0, \
- P_MII0_ERxD1, \
- P_MII0_ERxER, \
- P_MII0_TxCLK, \
- P_MII0_PHYINT, \
- P_MII0_CRS, \
- P_MII0_PTPPPS, \
- P_MII0_MDC, \
- P_MII0_MDIO, 0}
-
-#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_MII1_PTPPPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-
-#define P_RMII1 {\
- P_MII1_ETxD0, \
- P_MII1_ETxD1, \
- P_MII1_ETxEN, \
- P_MII1_ERxD0, \
- P_MII1_ERxD1, \
- P_MII1_ERxER, \
- P_MII1_TxCLK, \
- P_MII1_PHYINT, \
- P_MII1_CRS, \
- P_MII1_PTPPPS, \
- P_MII1_MDC, \
- P_MII1_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
-#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
-#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-
-#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
-#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
-#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
-#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
-#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
-#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
-#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
-#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
-#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
-#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
-#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
-#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
-#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
-#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
-#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
-#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
-#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
-
-#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
-#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
-#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
-#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
-#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
-#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
-#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
-#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
-#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
-#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
-#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
-#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
-#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
-#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
-#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
-#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
-#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
-#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-
-#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS
-#define P_DEFAULT_BOOT_SPI_CS
-
-/* CORE IDLE */
-#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-/* UART Port Mux */
-#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-
-#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
-#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
-#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-
-/* RSI */
-#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
-#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
-#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
-#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
-#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
-#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
-#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
-#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
-
-/* SMC Port Mux */
-#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-
-#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-
-/* CAN */
-#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-
-/* SPORT */
-#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
-#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
-#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
-#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
-#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
-#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
-#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
-#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
-#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
-#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
-
-#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
-#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
-#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
-#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
-#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
-#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
-#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-
-#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
-#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-
-/* LINK PORT */
-#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
-#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
-#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
-#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
-#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
-#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
-#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
-#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
-#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
-#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
-
-#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
-#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
-#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
-#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
-#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
-#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
-#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
-#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
-#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
-#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
-
-#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
-#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
-#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
-#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
-#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-/* TWI */
-#define P_TWI0_SCL (P_DONTCARE)
-#define P_TWI0_SDA (P_DONTCARE)
-#define P_TWI1_SCL (P_DONTCARE)
-#define P_TWI1_SDA (P_DONTCARE)
-
-/* Rotary Encoder */
-#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
-#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
-#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c
deleted file mode 100644
index f68abb9aa79e..000000000000
--- a/arch/blackfin/mach-bf609/ints-priority.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- *
- * Set up the interrupt priorities
- */
-
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <asm/blackfin.h>
-
-u8 sec_int_priority[] = {
- 255, /* IRQ_SEC_ERR */
- 255, /* IRQ_CGU_EVT */
- 254, /* IRQ_WATCH0 */
- 254, /* IRQ_WATCH1 */
- 253, /* IRQ_L2CTL0_ECC_ERR */
- 253, /* IRQ_L2CTL0_ECC_WARN */
- 253, /* IRQ_C0_DBL_FAULT */
- 253, /* IRQ_C1_DBL_FAULT */
- 252, /* IRQ_C0_HW_ERR */
- 252, /* IRQ_C1_HW_ERR */
- 255, /* IRQ_C0_NMI_L1_PARITY_ERR */
- 255, /* IRQ_C1_NMI_L1_PARITY_ERR */
-
- 50, /* IRQ_TIMER0 */
- 50, /* IRQ_TIMER1 */
- 50, /* IRQ_TIMER2 */
- 50, /* IRQ_TIMER3 */
- 50, /* IRQ_TIMER4 */
- 50, /* IRQ_TIMER5 */
- 50, /* IRQ_TIMER6 */
- 50, /* IRQ_TIMER7 */
- 50, /* IRQ_TIMER_STAT */
- 0, /* IRQ_PINT0 */
- 0, /* IRQ_PINT1 */
- 0, /* IRQ_PINT2 */
- 0, /* IRQ_PINT3 */
- 0, /* IRQ_PINT4 */
- 0, /* IRQ_PINT5 */
- 0, /* IRQ_CNT */
- 50, /* RQ_PWM0_TRIP */
- 50, /* IRQ_PWM0_SYNC */
- 50, /* IRQ_PWM1_TRIP */
- 50, /* IRQ_PWM1_SYNC */
- 0, /* IRQ_TWI0 */
- 0, /* IRQ_TWI1 */
- 10, /* IRQ_SOFT0 */
- 10, /* IRQ_SOFT1 */
- 10, /* IRQ_SOFT2 */
- 10, /* IRQ_SOFT3 */
- 0, /* IRQ_ACM_EVT_MISS */
- 0, /* IRQ_ACM_EVT_COMPLETE */
- 0, /* IRQ_CAN0_RX */
- 0, /* IRQ_CAN0_TX */
- 0, /* IRQ_CAN0_STAT */
- 100, /* IRQ_SPORT0_TX */
- 100, /* IRQ_SPORT0_TX_STAT */
- 100, /* IRQ_SPORT0_RX */
- 100, /* IRQ_SPORT0_RX_STAT */
- 100, /* IRQ_SPORT1_TX */
- 100, /* IRQ_SPORT1_TX_STAT */
- 100, /* IRQ_SPORT1_RX */
- 100, /* IRQ_SPORT1_RX_STAT */
- 100, /* IRQ_SPORT2_TX */
- 100, /* IRQ_SPORT2_TX_STAT */
- 100, /* IRQ_SPORT2_RX */
- 100, /* IRQ_SPORT2_RX_STAT */
- 0, /* IRQ_SPI0_TX */
- 0, /* IRQ_SPI0_RX */
- 0, /* IRQ_SPI0_STAT */
- 0, /* IRQ_SPI1_TX */
- 0, /* IRQ_SPI1_RX */
- 0, /* IRQ_SPI1_STAT */
- 0, /* IRQ_RSI */
- 0, /* IRQ_RSI_INT0 */
- 0, /* IRQ_RSI_INT1 */
- 0, /* DMA11 Data (SDU) */
- 0, /* DMA12 Data (Reserved) */
- 0, /* Reserved */
- 0, /* Reserved */
- 30, /* IRQ_EMAC0_STAT */
- 0, /* EMAC0 Power (Reserved) */
- 30, /* IRQ_EMAC1_STAT */
- 0, /* EMAC1 Power (Reserved) */
- 0, /* IRQ_LP0 */
- 0, /* IRQ_LP0_STAT */
- 0, /* IRQ_LP1 */
- 0, /* IRQ_LP1_STAT */
- 0, /* IRQ_LP2 */
- 0, /* IRQ_LP2_STAT */
- 0, /* IRQ_LP3 */
- 0, /* IRQ_LP3_STAT */
- 0, /* IRQ_UART0_TX */
- 0, /* IRQ_UART0_RX */
- 0, /* IRQ_UART0_STAT */
- 0, /* IRQ_UART1_TX */
- 0, /* IRQ_UART1_RX */
- 0, /* IRQ_UART1_STAT */
- 0, /* IRQ_MDMA0_SRC_CRC0 */
- 0, /* IRQ_MDMA0_DEST_CRC0 */
- 0, /* IRQ_CRC0_DCNTEXP */
- 0, /* IRQ_CRC0_ERR */
- 0, /* IRQ_MDMA1_SRC_CRC1 */
- 0, /* IRQ_MDMA1_DEST_CRC1 */
- 0, /* IRQ_CRC1_DCNTEXP */
- 0, /* IRQ_CRC1_ERR */
- 0, /* IRQ_MDMA2_SRC */
- 0, /* IRQ_MDMA2_DEST */
- 0, /* IRQ_MDMA3_SRC */
- 0, /* IRQ_MDMA3_DEST */
- 120, /* IRQ_EPPI0_CH0 */
- 120, /* IRQ_EPPI0_CH1 */
- 120, /* IRQ_EPPI0_STAT */
- 120, /* IRQ_EPPI2_CH0 */
- 120, /* IRQ_EPPI2_CH1 */
- 120, /* IRQ_EPPI2_STAT */
- 120, /* IRQ_EPPI1_CH0 */
- 120, /* IRQ_EPPI1_CH1 */
- 120, /* IRQ_EPPI1_STAT */
- 120, /* IRQ_PIXC_CH0 */
- 120, /* IRQ_PIXC_CH1 */
- 120, /* IRQ_PIXC_CH2 */
- 120, /* IRQ_PIXC_STAT */
- 120, /* IRQ_PVP_CPDOB */
- 120, /* IRQ_PVP_CPDOC */
- 120, /* IRQ_PVP_CPSTAT */
- 120, /* IRQ_PVP_CPCI */
- 120, /* IRQ_PVP_STAT0 */
- 120, /* IRQ_PVP_MPDO */
- 120, /* IRQ_PVP_MPDI */
- 120, /* IRQ_PVP_MPSTAT */
- 120, /* IRQ_PVP_MPCI */
- 120, /* IRQ_PVP_CPDOA */
- 120, /* IRQ_PVP_STAT1 */
- 0, /* IRQ_USB_STAT */
- 0, /* IRQ_USB_DMA */
- 0, /* IRQ_TRU_INT0 */
- 0, /* IRQ_TRU_INT1 */
- 0, /* IRQ_TRU_INT2 */
- 0, /* IRQ_TRU_INT3 */
- 0, /* IRQ_DMAC0_ERROR */
- 0, /* IRQ_CGU0_ERROR */
- 0, /* Reserved */
- 0, /* IRQ_DPM */
- 0, /* Reserved */
- 0, /* IRQ_SWU0 */
- 0, /* IRQ_SWU1 */
- 0, /* IRQ_SWU2 */
- 0, /* IRQ_SWU3 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU4 */
- 0, /* IRQ_SWU6 */
-};
-
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
deleted file mode 100644
index b1bfcf434d16..000000000000
--- a/arch/blackfin/mach-bf609/pm.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Blackfin bf609 power management
- *
- * Copyright 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <mach/pm.h>
-#include <asm/blackfin.h>
-#include <asm/mem_init.h>
-
-/***********************************************************/
-/* */
-/* Wakeup Actions for DPM_RESTORE */
-/* */
-/***********************************************************/
-#define BITP_ROM_WUA_CHKHDR 24
-#define BITP_ROM_WUA_DDRLOCK 7
-#define BITP_ROM_WUA_DDRDLLEN 6
-#define BITP_ROM_WUA_DDR 5
-#define BITP_ROM_WUA_CGU 4
-#define BITP_ROM_WUA_MEMBOOT 2
-#define BITP_ROM_WUA_EN 1
-
-#define BITM_ROM_WUA_CHKHDR (0xFF000000)
-#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
-
-#define BITM_ROM_WUA_DDRLOCK (0x00000080)
-#define BITM_ROM_WUA_DDRDLLEN (0x00000040)
-#define BITM_ROM_WUA_DDR (0x00000020)
-#define BITM_ROM_WUA_CGU (0x00000010)
-#define BITM_ROM_WUA_MEMBOOT (0x00000002)
-#define BITM_ROM_WUA_EN (0x00000001)
-
-/***********************************************************/
-/* */
-/* Syscontrol */
-/* */
-/***********************************************************/
-#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
-#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
-#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
-#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
-#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
-#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
-#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
-#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
-#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
-#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
-#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
-#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
-#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
-#define BITP_ROM_SYSCTRL_READ 0 /* read registers */
-
-#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
-#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
-#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
-#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
-#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
-#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
-#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
-#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
-#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
-#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
-#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
-#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
-#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
-#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
-#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
-#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
-
-
-/* Structures for the syscontrol() function */
-struct STRUCT_ROM_SYSCTRL {
- uint32_t ulCGU_CTL;
- uint32_t ulCGU_STAT;
- uint32_t ulCGU_DIV;
- uint32_t ulCGU_CLKOUTSEL;
- uint32_t ulWUA_Flags;
- uint32_t ulWUA_BootAddr;
- uint32_t ulWUA_User;
- uint32_t ulDDR_CTL;
- uint32_t ulDDR_CFG;
- uint32_t ulDDR_TR0;
- uint32_t ulDDR_TR1;
- uint32_t ulDDR_TR2;
- uint32_t ulDDR_MR;
- uint32_t ulDDR_EMR1;
- uint32_t ulDDR_EMR2;
- uint32_t ulDDR_PADCTL;
- uint32_t ulDDR_DLLCTL;
- uint32_t ulReserved;
-};
-
-struct bfin_pm_data {
- uint32_t magic;
- uint32_t resume_addr;
- uint32_t sp;
-};
-
-struct bfin_pm_data bf609_pm_data;
-
-struct STRUCT_ROM_SYSCTRL configvalues;
-uint32_t dactionflags;
-
-#define FUNC_ROM_SYSCONTROL 0xC8000080
-__attribute__((l1_data))
-static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
-
-__attribute__((l1_text))
-void bfin_cpu_suspend(void)
-{
- __asm__ __volatile__( \
- ".align 8;" \
- "idle;" \
- : : \
- );
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr(void)
-{
- dmc_enter_self_refresh();
-}
-
-__attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
-{
- dmc_exit_self_refresh();
-
- /* After wake up from deep sleep and exit DDR from self refress mode,
- * should wait till CGU PLL is locked.
- */
- while (bfin_read32(CGU0_STAT) & CLKSALGN)
- continue;
-}
-
-__attribute__((l1_text))
-void bf609_resume_ccbuf(void)
-{
- bfin_write32(DPM0_CCBF_EN, 3);
- bfin_write32(DPM0_CTL, 2);
-
- while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
-}
-
-__attribute__((l1_text))
-void bfin_hibernate_syscontrol(void)
-{
- configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
- | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
-
- dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
- | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
- | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
-
- bfrom_SysControl(dactionflags, &configvalues, NULL);
-
- bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
-}
-
-asmlinkage void enter_deepsleep(void);
-
-__attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- SSYNC();
- enter_deepsleep();
-}
-
-void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
-{
- bfin_write32(DPM0_WAKE_EN, mask);
- bfin_write32(DPM0_WAKE_POL, pol_mask);
- bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
- bfin_write32(DPM0_HIB_DIS, 0xFFFF);
-
- bf609_hibernate();
-}
-
-void bf609_cpu_pm_enter(suspend_state_t state)
-{
- int error;
- unsigned long wakeup = 0;
- unsigned long wakeup_pol = 0;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PA15
- wakeup |= PA15WE;
-# if CONFIG_PM_BFIN_WAKE_PA15_POL
- wakeup_pol |= PA15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PB15
- wakeup |= PB15WE;
-# if CONFIG_PM_BFIN_WAKE_PB15_POL
- wakeup_pol |= PB15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PC15
- wakeup |= PC15WE;
-# if CONFIG_PM_BFIN_WAKE_PC15_POL
- wakeup_pol |= PC15WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PD06
- wakeup |= PD06WE;
-# if CONFIG_PM_BFIN_WAKE_PD06_POL
- wakeup_pol |= PD06WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- wakeup |= PE12WE;
-# if CONFIG_PM_BFIN_WAKE_PE12_POL
- wakeup_pol |= PE12WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG04
- wakeup |= PG04WE;
-# if CONFIG_PM_BFIN_WAKE_PG04_POL
- wakeup_pol |= PG04WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PG13
- wakeup |= PG13WE;
-# if CONFIG_PM_BFIN_WAKE_PG13_POL
- wakeup_pol |= PG13WE;
-# endif
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_USB
- wakeup |= USBWE;
-# if CONFIG_PM_BFIN_WAKE_USB_POL
- wakeup_pol |= USBWE;
-# endif
-#endif
-
- error = irq_set_irq_wake(255, 1);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
- error = irq_set_irq_wake(231, 1);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq wake\n");
-
- if (state == PM_SUSPEND_STANDBY)
- bfin_deepsleep(wakeup, wakeup_pol);
- else {
- bfin_hibernate(wakeup, wakeup_pol);
- }
-
-}
-
-int bf609_cpu_pm_prepare(void)
-{
- return 0;
-}
-
-void bf609_cpu_pm_finish(void)
-{
-
-}
-
-static struct bfin_cpu_pm_fns bf609_cpu_pm = {
- .enter = bf609_cpu_pm_enter,
- .prepare = bf609_cpu_pm_prepare,
- .finish = bf609_cpu_pm_finish,
-};
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
-static int smc_pm_syscore_suspend(void)
-{
- bf609_nor_flash_exit(NULL);
- return 0;
-}
-
-static void smc_pm_syscore_resume(void)
-{
- bf609_nor_flash_init(NULL);
-}
-
-static struct syscore_ops smc_pm_syscore_ops = {
- .suspend = smc_pm_syscore_suspend,
- .resume = smc_pm_syscore_resume,
-};
-#endif
-
-static irqreturn_t test_isr(int irq, void *dev_id)
-{
- printk(KERN_DEBUG "gpio irq %d\n", irq);
- if (irq == 231)
- bfin_sec_raise_irq(BFIN_SYSIRQ(IRQ_SOFT1));
- return IRQ_HANDLED;
-}
-
-static irqreturn_t dpm0_isr(int irq, void *dev_id)
-{
- bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
- bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
- return IRQ_HANDLED;
-}
-
-static int __init bf609_init_pm(void)
-{
- int irq;
- int error;
-
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
- register_syscore_ops(&smc_pm_syscore_ops);
-#endif
-
-#ifdef CONFIG_PM_BFIN_WAKE_PE12
- irq = gpio_to_irq(GPIO_PE12);
- if (irq < 0) {
- error = irq;
- printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
- GPIO_PE12, error);
- }
-
- error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
- | IRQF_FORCE_RESUME, "gpiope12", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-#endif
-
- error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "cgu0 event", NULL);
- if(error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
- IRQF_FORCE_RESUME, "dpm0 event", NULL);
- if (error < 0)
- printk(KERN_DEBUG "Unable to get irq\n");
-
- bfin_cpu_pm = &bf609_cpu_pm;
- return 0;
-}
-
-late_initcall(bf609_init_pm);
diff --git a/arch/blackfin/mach-bf609/scb.c b/arch/blackfin/mach-bf609/scb.c
deleted file mode 100644
index ac1f07c33594..000000000000
--- a/arch/blackfin/mach-bf609/scb.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/scb.h>
-
-struct scb_mi_prio scb_data[] = {
-#ifdef CONFIG_SCB0_MI0
- { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
- CONFIG_SCB0_MI0_SLOT0,
- CONFIG_SCB0_MI0_SLOT1,
- CONFIG_SCB0_MI0_SLOT2,
- CONFIG_SCB0_MI0_SLOT3,
- CONFIG_SCB0_MI0_SLOT4,
- CONFIG_SCB0_MI0_SLOT5,
- CONFIG_SCB0_MI0_SLOT6,
- CONFIG_SCB0_MI0_SLOT7,
- CONFIG_SCB0_MI0_SLOT8,
- CONFIG_SCB0_MI0_SLOT9,
- CONFIG_SCB0_MI0_SLOT10,
- CONFIG_SCB0_MI0_SLOT11,
- CONFIG_SCB0_MI0_SLOT12,
- CONFIG_SCB0_MI0_SLOT13,
- CONFIG_SCB0_MI0_SLOT14,
- CONFIG_SCB0_MI0_SLOT15,
- CONFIG_SCB0_MI0_SLOT16,
- CONFIG_SCB0_MI0_SLOT17,
- CONFIG_SCB0_MI0_SLOT18,
- CONFIG_SCB0_MI0_SLOT19,
- CONFIG_SCB0_MI0_SLOT20,
- CONFIG_SCB0_MI0_SLOT21,
- CONFIG_SCB0_MI0_SLOT22,
- CONFIG_SCB0_MI0_SLOT23,
- CONFIG_SCB0_MI0_SLOT24,
- CONFIG_SCB0_MI0_SLOT25,
- CONFIG_SCB0_MI0_SLOT26,
- CONFIG_SCB0_MI0_SLOT27,
- CONFIG_SCB0_MI0_SLOT28,
- CONFIG_SCB0_MI0_SLOT29,
- CONFIG_SCB0_MI0_SLOT30,
- CONFIG_SCB0_MI0_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI1
- { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
- CONFIG_SCB0_MI1_SLOT0,
- CONFIG_SCB0_MI1_SLOT1,
- CONFIG_SCB0_MI1_SLOT2,
- CONFIG_SCB0_MI1_SLOT3,
- CONFIG_SCB0_MI1_SLOT4,
- CONFIG_SCB0_MI1_SLOT5,
- CONFIG_SCB0_MI1_SLOT6,
- CONFIG_SCB0_MI1_SLOT7,
- CONFIG_SCB0_MI1_SLOT8,
- CONFIG_SCB0_MI1_SLOT9,
- CONFIG_SCB0_MI1_SLOT10,
- CONFIG_SCB0_MI1_SLOT11,
- CONFIG_SCB0_MI1_SLOT12,
- CONFIG_SCB0_MI1_SLOT13,
- CONFIG_SCB0_MI1_SLOT14,
- CONFIG_SCB0_MI1_SLOT15,
- CONFIG_SCB0_MI1_SLOT16,
- CONFIG_SCB0_MI1_SLOT17,
- CONFIG_SCB0_MI1_SLOT18,
- CONFIG_SCB0_MI1_SLOT19,
- CONFIG_SCB0_MI1_SLOT20,
- CONFIG_SCB0_MI1_SLOT21,
- CONFIG_SCB0_MI1_SLOT22,
- CONFIG_SCB0_MI1_SLOT23,
- CONFIG_SCB0_MI1_SLOT24,
- CONFIG_SCB0_MI1_SLOT25,
- CONFIG_SCB0_MI1_SLOT26,
- CONFIG_SCB0_MI1_SLOT27,
- CONFIG_SCB0_MI1_SLOT28,
- CONFIG_SCB0_MI1_SLOT29,
- CONFIG_SCB0_MI1_SLOT30,
- CONFIG_SCB0_MI1_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI2
- { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
- CONFIG_SCB0_MI2_SLOT0,
- CONFIG_SCB0_MI2_SLOT1,
- CONFIG_SCB0_MI2_SLOT2,
- CONFIG_SCB0_MI2_SLOT3,
- CONFIG_SCB0_MI2_SLOT4,
- CONFIG_SCB0_MI2_SLOT5,
- CONFIG_SCB0_MI2_SLOT6,
- CONFIG_SCB0_MI2_SLOT7,
- CONFIG_SCB0_MI2_SLOT8,
- CONFIG_SCB0_MI2_SLOT9,
- CONFIG_SCB0_MI2_SLOT10,
- CONFIG_SCB0_MI2_SLOT11,
- CONFIG_SCB0_MI2_SLOT12,
- CONFIG_SCB0_MI2_SLOT13,
- CONFIG_SCB0_MI2_SLOT14,
- CONFIG_SCB0_MI2_SLOT15,
- CONFIG_SCB0_MI2_SLOT16,
- CONFIG_SCB0_MI2_SLOT17,
- CONFIG_SCB0_MI2_SLOT18,
- CONFIG_SCB0_MI2_SLOT19,
- CONFIG_SCB0_MI2_SLOT20,
- CONFIG_SCB0_MI2_SLOT21,
- CONFIG_SCB0_MI2_SLOT22,
- CONFIG_SCB0_MI2_SLOT23,
- CONFIG_SCB0_MI2_SLOT24,
- CONFIG_SCB0_MI2_SLOT25,
- CONFIG_SCB0_MI2_SLOT26,
- CONFIG_SCB0_MI2_SLOT27,
- CONFIG_SCB0_MI2_SLOT28,
- CONFIG_SCB0_MI2_SLOT29,
- CONFIG_SCB0_MI2_SLOT30,
- CONFIG_SCB0_MI2_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI3
- { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
- CONFIG_SCB0_MI3_SLOT0,
- CONFIG_SCB0_MI3_SLOT1,
- CONFIG_SCB0_MI3_SLOT2,
- CONFIG_SCB0_MI3_SLOT3,
- CONFIG_SCB0_MI3_SLOT4,
- CONFIG_SCB0_MI3_SLOT5,
- CONFIG_SCB0_MI3_SLOT6,
- CONFIG_SCB0_MI3_SLOT7,
- CONFIG_SCB0_MI3_SLOT8,
- CONFIG_SCB0_MI3_SLOT9,
- CONFIG_SCB0_MI3_SLOT10,
- CONFIG_SCB0_MI3_SLOT11,
- CONFIG_SCB0_MI3_SLOT12,
- CONFIG_SCB0_MI3_SLOT13,
- CONFIG_SCB0_MI3_SLOT14,
- CONFIG_SCB0_MI3_SLOT15,
- CONFIG_SCB0_MI3_SLOT16,
- CONFIG_SCB0_MI3_SLOT17,
- CONFIG_SCB0_MI3_SLOT18,
- CONFIG_SCB0_MI3_SLOT19,
- CONFIG_SCB0_MI3_SLOT20,
- CONFIG_SCB0_MI3_SLOT21,
- CONFIG_SCB0_MI3_SLOT22,
- CONFIG_SCB0_MI3_SLOT23,
- CONFIG_SCB0_MI3_SLOT24,
- CONFIG_SCB0_MI3_SLOT25,
- CONFIG_SCB0_MI3_SLOT26,
- CONFIG_SCB0_MI3_SLOT27,
- CONFIG_SCB0_MI3_SLOT28,
- CONFIG_SCB0_MI3_SLOT29,
- CONFIG_SCB0_MI3_SLOT30,
- CONFIG_SCB0_MI3_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI4
- { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
- CONFIG_SCB0_MI4_SLOT0,
- CONFIG_SCB0_MI4_SLOT1,
- CONFIG_SCB0_MI4_SLOT2,
- CONFIG_SCB0_MI4_SLOT3,
- CONFIG_SCB0_MI4_SLOT4,
- CONFIG_SCB0_MI4_SLOT5,
- CONFIG_SCB0_MI4_SLOT6,
- CONFIG_SCB0_MI4_SLOT7,
- CONFIG_SCB0_MI4_SLOT8,
- CONFIG_SCB0_MI4_SLOT9,
- CONFIG_SCB0_MI4_SLOT10,
- CONFIG_SCB0_MI4_SLOT11,
- CONFIG_SCB0_MI4_SLOT12,
- CONFIG_SCB0_MI4_SLOT13,
- CONFIG_SCB0_MI4_SLOT14,
- CONFIG_SCB0_MI4_SLOT15,
- CONFIG_SCB0_MI4_SLOT16,
- CONFIG_SCB0_MI4_SLOT17,
- CONFIG_SCB0_MI4_SLOT18,
- CONFIG_SCB0_MI4_SLOT19,
- CONFIG_SCB0_MI4_SLOT20,
- CONFIG_SCB0_MI4_SLOT21,
- CONFIG_SCB0_MI4_SLOT22,
- CONFIG_SCB0_MI4_SLOT23,
- CONFIG_SCB0_MI4_SLOT24,
- CONFIG_SCB0_MI4_SLOT25,
- CONFIG_SCB0_MI4_SLOT26,
- CONFIG_SCB0_MI4_SLOT27,
- CONFIG_SCB0_MI4_SLOT28,
- CONFIG_SCB0_MI4_SLOT29,
- CONFIG_SCB0_MI4_SLOT30,
- CONFIG_SCB0_MI4_SLOT31
- },
- },
-#endif
-#ifdef CONFIG_SCB0_MI5
- { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
- CONFIG_SCB0_MI5_SLOT0,
- CONFIG_SCB0_MI5_SLOT1,
- CONFIG_SCB0_MI5_SLOT2,
- CONFIG_SCB0_MI5_SLOT3,
- CONFIG_SCB0_MI5_SLOT4,
- CONFIG_SCB0_MI5_SLOT5,
- CONFIG_SCB0_MI5_SLOT6,
- CONFIG_SCB0_MI5_SLOT7,
- CONFIG_SCB0_MI5_SLOT8,
- CONFIG_SCB0_MI5_SLOT9,
- CONFIG_SCB0_MI5_SLOT10,
- CONFIG_SCB0_MI5_SLOT11,
- CONFIG_SCB0_MI5_SLOT12,
- CONFIG_SCB0_MI5_SLOT13,
- CONFIG_SCB0_MI5_SLOT14,
- CONFIG_SCB0_MI5_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB1_MI0
- { REG_SCB1_ARBR0, REG_SCB1_ARBW0, 20, {
- CONFIG_SCB1_MI0_SLOT0,
- CONFIG_SCB1_MI0_SLOT1,
- CONFIG_SCB1_MI0_SLOT2,
- CONFIG_SCB1_MI0_SLOT3,
- CONFIG_SCB1_MI0_SLOT4,
- CONFIG_SCB1_MI0_SLOT5,
- CONFIG_SCB1_MI0_SLOT6,
- CONFIG_SCB1_MI0_SLOT7,
- CONFIG_SCB1_MI0_SLOT8,
- CONFIG_SCB1_MI0_SLOT9,
- CONFIG_SCB1_MI0_SLOT10,
- CONFIG_SCB1_MI0_SLOT11,
- CONFIG_SCB1_MI0_SLOT12,
- CONFIG_SCB1_MI0_SLOT13,
- CONFIG_SCB1_MI0_SLOT14,
- CONFIG_SCB1_MI0_SLOT15,
- CONFIG_SCB1_MI0_SLOT16,
- CONFIG_SCB1_MI0_SLOT17,
- CONFIG_SCB1_MI0_SLOT18,
- CONFIG_SCB1_MI0_SLOT19
- },
- },
-#endif
-#ifdef CONFIG_SCB2_MI0
- { REG_SCB2_ARBR0, REG_SCB2_ARBW0, 10, {
- CONFIG_SCB2_MI0_SLOT0,
- CONFIG_SCB2_MI0_SLOT1,
- CONFIG_SCB2_MI0_SLOT2,
- CONFIG_SCB2_MI0_SLOT3,
- CONFIG_SCB2_MI0_SLOT4,
- CONFIG_SCB2_MI0_SLOT5,
- CONFIG_SCB2_MI0_SLOT6,
- CONFIG_SCB2_MI0_SLOT7,
- CONFIG_SCB2_MI0_SLOT8,
- CONFIG_SCB2_MI0_SLOT9
- },
- },
-#endif
-#ifdef CONFIG_SCB3_MI0
- { REG_SCB3_ARBR0, REG_SCB3_ARBW0, 16, {
- CONFIG_SCB3_MI0_SLOT0,
- CONFIG_SCB3_MI0_SLOT1,
- CONFIG_SCB3_MI0_SLOT2,
- CONFIG_SCB3_MI0_SLOT3,
- CONFIG_SCB3_MI0_SLOT4,
- CONFIG_SCB3_MI0_SLOT5,
- CONFIG_SCB3_MI0_SLOT6,
- CONFIG_SCB3_MI0_SLOT7,
- CONFIG_SCB3_MI0_SLOT8,
- CONFIG_SCB3_MI0_SLOT9,
- CONFIG_SCB3_MI0_SLOT10,
- CONFIG_SCB3_MI0_SLOT11,
- CONFIG_SCB3_MI0_SLOT12,
- CONFIG_SCB3_MI0_SLOT13,
- CONFIG_SCB3_MI0_SLOT14,
- CONFIG_SCB3_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB4_MI0
- { REG_SCB4_ARBR0, REG_SCB4_ARBW0, 16, {
- CONFIG_SCB4_MI0_SLOT0,
- CONFIG_SCB4_MI0_SLOT1,
- CONFIG_SCB4_MI0_SLOT2,
- CONFIG_SCB4_MI0_SLOT3,
- CONFIG_SCB4_MI0_SLOT4,
- CONFIG_SCB4_MI0_SLOT5,
- CONFIG_SCB4_MI0_SLOT6,
- CONFIG_SCB4_MI0_SLOT7,
- CONFIG_SCB4_MI0_SLOT8,
- CONFIG_SCB4_MI0_SLOT9,
- CONFIG_SCB4_MI0_SLOT10,
- CONFIG_SCB4_MI0_SLOT11,
- CONFIG_SCB4_MI0_SLOT12,
- CONFIG_SCB4_MI0_SLOT13,
- CONFIG_SCB4_MI0_SLOT14,
- CONFIG_SCB4_MI0_SLOT15
- },
- },
-#endif
-#ifdef CONFIG_SCB5_MI0
- { REG_SCB5_ARBR0, REG_SCB5_ARBW0, 8, {
- CONFIG_SCB5_MI0_SLOT0,
- CONFIG_SCB5_MI0_SLOT1,
- CONFIG_SCB5_MI0_SLOT2,
- CONFIG_SCB5_MI0_SLOT3,
- CONFIG_SCB5_MI0_SLOT4,
- CONFIG_SCB5_MI0_SLOT5,
- CONFIG_SCB5_MI0_SLOT6,
- CONFIG_SCB5_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB6_MI0
- { REG_SCB6_ARBR0, REG_SCB6_ARBW0, 4, {
- CONFIG_SCB6_MI0_SLOT0,
- CONFIG_SCB6_MI0_SLOT1,
- CONFIG_SCB6_MI0_SLOT2,
- CONFIG_SCB6_MI0_SLOT3
- },
- },
-#endif
-#ifdef CONFIG_SCB7_MI0
- { REG_SCB7_ARBR0, REG_SCB7_ARBW0, 6, {
- CONFIG_SCB7_MI0_SLOT0,
- CONFIG_SCB7_MI0_SLOT1,
- CONFIG_SCB7_MI0_SLOT2,
- CONFIG_SCB7_MI0_SLOT3,
- CONFIG_SCB7_MI0_SLOT4,
- CONFIG_SCB7_MI0_SLOT5
- },
- },
-#endif
-#ifdef CONFIG_SCB8_MI0
- { REG_SCB8_ARBR0, REG_SCB8_ARBW0, 8, {
- CONFIG_SCB8_MI0_SLOT0,
- CONFIG_SCB8_MI0_SLOT1,
- CONFIG_SCB8_MI0_SLOT2,
- CONFIG_SCB8_MI0_SLOT3,
- CONFIG_SCB8_MI0_SLOT4,
- CONFIG_SCB8_MI0_SLOT5,
- CONFIG_SCB8_MI0_SLOT6,
- CONFIG_SCB8_MI0_SLOT7
- },
- },
-#endif
-#ifdef CONFIG_SCB9_MI0
- { REG_SCB9_ARBR0, REG_SCB9_ARBW0, 10, {
- CONFIG_SCB9_MI0_SLOT0,
- CONFIG_SCB9_MI0_SLOT1,
- CONFIG_SCB9_MI0_SLOT2,
- CONFIG_SCB9_MI0_SLOT3,
- CONFIG_SCB9_MI0_SLOT4,
- CONFIG_SCB9_MI0_SLOT5,
- CONFIG_SCB9_MI0_SLOT6,
- CONFIG_SCB9_MI0_SLOT7,
- CONFIG_SCB9_MI0_SLOT8,
- CONFIG_SCB9_MI0_SLOT9
- },
- },
-#endif
- { 0, }
-};
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
deleted file mode 100644
index fcef1c8e117f..000000000000
--- a/arch/blackfin/mach-common/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/mach-common/Makefile
-#
-
-obj-y := \
- cache.o cache-c.o entry.o head.o \
- interrupt.o arch_checks.o ints-priority.o
-
-obj-$(CONFIG_PM) += pm.o
-ifneq ($(CONFIG_BF60x),y)
-obj-$(CONFIG_PM) += dpmc_modes.o
-endif
-obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
-obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
deleted file mode 100644
index d8643fdd0fcf..000000000000
--- a/arch/blackfin/mach-common/arch_checks.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Do some checking to make sure things are OK
- *
- * Copyright 2007-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/fixed_code.h>
-#include <mach/anomaly.h>
-#include <asm/clocks.h>
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-
-# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
-# error "VCO selected is more than maximum value. Please change the VCO multipler"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
-# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
-# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-# endif
-
-# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
-# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
-# endif
-
-# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-# error "Please select sclk less than cclk"
-# endif
-
-#endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-#if CONFIG_BOOT_LOAD < FIXED_CODE_END
-# error "The kernel load address must be after the fixed code section"
-#endif
-
-#if (CONFIG_BOOT_LOAD & 0x3)
-# error "The kernel load address must be 4 byte aligned"
-#endif
-
-/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
-#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
-# error "The kernel load address is too high; keep it below 10meg for safety"
-#endif
-
-#if ANOMALY_05000263 && defined(CONFIG_MPU)
-# error the MPU will not function safely while Anomaly 05000263 applies
-#endif
-
-#if ANOMALY_05000448
-# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
-#endif
-
-/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
-#if ANOMALY_05000220 && \
- (defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
-# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
-#endif
-
-#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
-# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
-#endif
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c
deleted file mode 100644
index f4adedc92895..000000000000
--- a/arch/blackfin/mach-common/cache-c.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Blackfin cache control code (simpler control-style functions)
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <asm/cplbinit.h>
-
-/* Invalidate the Entire Data cache by
- * clearing DMC[1:0] bits
- */
-void blackfin_invalidate_entire_dcache(void)
-{
- u32 dmem = bfin_read_DMEM_CONTROL();
- bfin_write_DMEM_CONTROL(dmem & ~0xc);
- SSYNC();
- bfin_write_DMEM_CONTROL(dmem);
- SSYNC();
-}
-
-/* Invalidate the Entire Instruction cache by
- * clearing IMC bit
- */
-void blackfin_invalidate_entire_icache(void)
-{
- u32 imem = bfin_read_IMEM_CONTROL();
- bfin_write_IMEM_CONTROL(imem & ~0x4);
- SSYNC();
- bfin_write_IMEM_CONTROL(imem);
- SSYNC();
-}
-
-#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
-
-static void
-bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
- unsigned long cplb_data, unsigned long mem_control,
- unsigned long mem_mask)
-{
- int i;
-#ifdef CONFIG_L1_PARITY_CHECK
- u32 ctrl;
-
- if (cplb_addr == DCPLB_ADDR0) {
- ctrl = bfin_read32(mem_control) | (1 << RDCHK);
- CSYNC();
- bfin_write32(mem_control, ctrl);
- SSYNC();
- }
-#endif
-
- for (i = 0; i < MAX_CPLBS; i++) {
- bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
- bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
- }
-
- _enable_cplb(mem_control, mem_mask);
-}
-
-#ifdef CONFIG_BFIN_ICACHE
-void bfin_icache_init(struct cplb_entry *icplb_tbl)
-{
- bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
- (IMC | ENICPLB));
-}
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
-{
- /*
- * Anomaly notes:
- * 05000287 - We implement workaround #2 - Change the DMEM_CONTROL
- * register, so that the port preferences for DAG0 and DAG1 are set
- * to port B
- */
- bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
- (DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
-}
-#endif
-
-#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
deleted file mode 100644
index 9f4dd35bfd74..000000000000
--- a/arch/blackfin/mach-common/cache.S
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Blackfin cache control code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/cache.h>
-#include <asm/page.h>
-
-/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
-#if ANOMALY_05000443
-# define BROK_FLUSH_INST "IFLUSH"
-#else
-# define BROK_FLUSH_INST "no anomaly! yeah!"
-#endif
-
-/* Since all L1 caches work the same way, we use the same method for flushing
- * them. Only the actual flush instruction differs. We write this in asm as
- * GCC can be hard to coax into writing nice hardware loops.
- *
- * Also, we assume the following register setup:
- * R0 = start address
- * R1 = end address
- */
-.macro do_flush flushins:req label
-
- R2 = -L1_CACHE_BYTES;
-
- /* start = (start & -L1_CACHE_BYTES) */
- R0 = R0 & R2;
-
- /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
- R1 += -1;
- R1 = R1 & R2;
- R1 += L1_CACHE_BYTES;
-
- /* count = (end - start) >> L1_CACHE_SHIFT */
- R2 = R1 - R0;
- R2 >>= L1_CACHE_SHIFT;
- P1 = R2;
-
-.ifnb \label
-\label :
-.endif
- P0 = R0;
-
- LSETUP (1f, 2f) LC1 = P1;
-1:
-.ifeqs "\flushins", BROK_FLUSH_INST
- \flushins [P0++];
- nop;
- nop;
-2: nop;
-.else
-2: \flushins [P0++];
-.endif
-
- RTS;
-.endm
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Invalidate all instruction cache lines assocoiated with this memory area */
-#ifdef CONFIG_SMP
-# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1
-#endif
-ENTRY(_blackfin_icache_flush_range)
- do_flush IFLUSH
-ENDPROC(_blackfin_icache_flush_range)
-
-#ifdef CONFIG_SMP
-.text
-# undef _blackfin_icache_flush_range
-ENTRY(_blackfin_icache_flush_range)
- p0.L = LO(DSPID);
- p0.H = HI(DSPID);
- r3 = [p0];
- r3 = r3.b (z);
- p2 = r3;
- p0.L = _blackfin_iflush_l1_entry;
- p0.H = _blackfin_iflush_l1_entry;
- p0 = p0 + (p2 << 2);
- p1 = [p0];
- jump (p1);
-ENDPROC(_blackfin_icache_flush_range)
-#endif
-
-#ifdef CONFIG_DCACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Throw away all D-cached data in specified region without any obligation to
- * write them back. Since the Blackfin ISA does not have an "invalidate"
- * instruction, we use flush/invalidate. Perhaps as a speed optimization we
- * could bang on the DTEST MMRs ...
- */
-ENTRY(_blackfin_dcache_invalidate_range)
- do_flush FLUSHINV
-ENDPROC(_blackfin_dcache_invalidate_range)
-
-/* Flush all data cache lines assocoiated with this memory area */
-ENTRY(_blackfin_dcache_flush_range)
- do_flush FLUSH, .Ldfr
-ENDPROC(_blackfin_dcache_flush_range)
-
-/* Our headers convert the page structure to an address, so just need to flush
- * its contents like normal. We know the start address is page aligned (which
- * greater than our cache alignment), as is the end address. So just jump into
- * the middle of the dcache flush function.
- */
-ENTRY(_blackfin_dflush_page)
- P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
- jump .Ldfr;
-ENDPROC(_blackfin_dflush_page)
diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h
deleted file mode 100644
index fed851a51aaf..000000000000
--- a/arch/blackfin/mach-common/clock.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MACH_COMMON_CLKDEV_H
-#define __MACH_COMMON_CLKDEV_H
-
-#include <linux/clk.h>
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
-};
-
-struct clk {
- const char *name;
- unsigned long rate;
- spinlock_t lock;
- u32 flags;
- const struct clk_ops *ops;
- const struct params *params;
- void __iomem *reg;
- u32 mask;
- u32 shift;
-};
-
-#endif
-
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
deleted file mode 100644
index d436bd907fc8..000000000000
--- a/arch/blackfin/mach-common/clocks-init.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-#include <asm/dma.h>
-#include <asm/clocks.h>
-#include <asm/mem_init.h>
-#include <asm/dpmc.h>
-
-#ifdef CONFIG_BF60x
-
-#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
-#define CGU_DIV_VAL \
- ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \
- (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \
- (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \
- (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \
- (CONFIG_DCLK_DIV << DSEL_OFFSET))
-
-#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
-#if ((CONFIG_BFIN_DCLK != 125) && \
- (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
- (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
- (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
-#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
-#endif
-
-#else
-#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
-#define PLL_CTL_VAL \
- (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
- (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
-#endif
-
-__attribute__((l1_text))
-static void do_sync(void)
-{
- __builtin_bfin_ssync();
-}
-
-__attribute__((l1_text))
-void init_clocks(void)
-{
- /* Kill any active DMAs as they may trigger external memory accesses
- * in the middle of reprogramming things, and that'll screw us up.
- * For example, any automatic DMAs left by U-Boot for splash screens.
- */
-#ifdef CONFIG_BF60x
- init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
- init_dmc(CONFIG_BFIN_DCLK);
-#else
- size_t i;
- for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
- struct dma_register *dma = dma_io_base_addr[i];
- dma->cfg = 0;
- }
-
- do_sync();
-
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_ENABLE(0));
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_ENABLE(0));
-#endif
- do_sync();
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
- do_sync();
-#endif
-
-#ifdef CLKBUFOE
- bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
- do_sync();
- __asm__ __volatile__("IDLE;");
-#endif
- bfin_write_PLL_LOCKCNT(0x300);
- do_sync();
- /* We always write PLL_CTL thus avoiding Anomaly 05000242 */
- bfin_write16(PLL_CTL, PLL_CTL_VAL);
- __asm__ __volatile__("IDLE;");
- bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-#ifdef EBIU_SDGCTL
- bfin_write_EBIU_SDRRC(mem_SDRRC);
- bfin_write_EBIU_SDGCTL((bfin_read_EBIU_SDGCTL() & SDGCTL_WIDTH) | mem_SDGCTL);
-#else
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
- do_sync();
- bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
- bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
- bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
- bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
-#ifdef CONFIG_MEM_EBIU_DDRQUE
- bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
-#endif
-#endif
-#endif
- do_sync();
- bfin_read16(0);
-
-}
diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c
deleted file mode 100644
index 724a8c5f5578..000000000000
--- a/arch/blackfin/mach-common/dpmc.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/cdev.h>
-#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/cpufreq.h>
-
-#include <asm/delay.h>
-#include <asm/dpmc.h>
-
-#define DRIVER_NAME "bfin dpmc"
-
-struct bfin_dpmc_platform_data *pdata;
-
-/**
- * bfin_set_vlev - Update VLEV field in VR_CTL Reg.
- * Avoid BYPASS sequence
- */
-static void bfin_set_vlev(unsigned int vlev)
-{
- unsigned pll_lcnt;
-
- pll_lcnt = bfin_read_PLL_LOCKCNT();
-
- bfin_write_PLL_LOCKCNT(1);
- bfin_write_VR_CTL((bfin_read_VR_CTL() & ~VLEV) | vlev);
- bfin_write_PLL_LOCKCNT(pll_lcnt);
-}
-
-/**
- * bfin_get_vlev - Get CPU specific VLEV from platform device data
- */
-static unsigned int bfin_get_vlev(unsigned int freq)
-{
- int i;
-
- if (!pdata)
- goto err_out;
-
- freq >>= 16;
-
- for (i = 0; i < pdata->tabsize; i++)
- if (freq <= (pdata->tuple_tab[i] & 0xFFFF))
- return pdata->tuple_tab[i] >> 16;
-
-err_out:
- printk(KERN_WARNING "DPMC: No suitable CCLK VDDINT voltage pair found\n");
- return VLEV_120;
-}
-
-#ifdef CONFIG_CPU_FREQ
-# ifdef CONFIG_SMP
-static void bfin_idle_this_cpu(void *info)
-{
- unsigned long flags = 0;
- unsigned long iwr0, iwr1, iwr2;
- unsigned int cpu = smp_processor_id();
-
- local_irq_save_hw(flags);
- bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2);
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- SSYNC();
- asm("IDLE;");
- bfin_iwr_restore(iwr0, iwr1, iwr2);
-
- local_irq_restore_hw(flags);
-}
-
-static void bfin_idle_cpu(void)
-{
- smp_call_function(bfin_idle_this_cpu, NULL, 0);
-}
-
-static void bfin_wakeup_cpu(void)
-{
- unsigned int cpu;
- unsigned int this_cpu = smp_processor_id();
- cpumask_t mask;
-
- cpumask_copy(&mask, cpu_online_mask);
- cpumask_clear_cpu(this_cpu, &mask);
- for_each_cpu(cpu, &mask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
-}
-
-# else
-static void bfin_idle_cpu(void) {}
-static void bfin_wakeup_cpu(void) {}
-# endif
-
-static int
-vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
-{
- struct cpufreq_freqs *freq = data;
-
- if (freq->cpu != CPUFREQ_CPU)
- return 0;
-
- if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- udelay(pdata->vr_settling_time); /* Wait until Volatge settled */
- bfin_wakeup_cpu();
- } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) {
- bfin_idle_cpu();
- bfin_set_vlev(bfin_get_vlev(freq->new));
- bfin_wakeup_cpu();
- }
-
- return 0;
-}
-
-static struct notifier_block vreg_cpufreq_notifier_block = {
- .notifier_call = vreg_cpufreq_notifier
-};
-#endif /* CONFIG_CPU_FREQ */
-
-/**
- * bfin_dpmc_probe -
- *
- */
-static int bfin_dpmc_probe(struct platform_device *pdev)
-{
- if (pdev->dev.platform_data)
- pdata = pdev->dev.platform_data;
- else
- return -EINVAL;
-
- return cpufreq_register_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-/**
- * bfin_dpmc_remove -
- */
-static int bfin_dpmc_remove(struct platform_device *pdev)
-{
- pdata = NULL;
- return cpufreq_unregister_notifier(&vreg_cpufreq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-}
-
-struct platform_driver bfin_dpmc_device_driver = {
- .probe = bfin_dpmc_probe,
- .remove = bfin_dpmc_remove,
- .driver = {
- .name = DRIVER_NAME,
- }
-};
-module_platform_driver(bfin_dpmc_device_driver);
-
-MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("cpu power management driver for Blackfin");
-MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
deleted file mode 100644
index de99f3aac2c5..000000000000
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <asm/dpmc.h>
-
-.section .l1.text
-ENTRY(_sleep_mode)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R1 = W[P0](z);
- BITSET (R1, 3);
- W[P0] = R1.L;
-
- CLI R2;
- SSYNC;
- IDLE;
- STI R2;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R7 = w[p0](z);
- BITCLR (R7, 3);
- BITCLR (R7, 5);
- w[p0] = R7.L;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_mode)
-
-/*
- * This func never returns as it puts the part into hibernate, and
- * is only called from do_hibernate, so we don't bother saving or
- * restoring any of the normal C runtime state. When we wake up,
- * the entry point will be in do_hibernate and not here.
- *
- * We accept just one argument -- the value to write to VR_CTL.
- */
-
-ENTRY(_hibernate_mode)
- /* Save/setup the regs we need early for minor pipeline optimization */
- R4 = R0;
-
- P3.H = hi(VR_CTL);
- P3.L = lo(VR_CTL);
- /* Disable all wakeup sources */
- R0 = IWR_DISABLE_ALL;
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
- call _set_sic_iwr;
- call _set_dram_srfs;
- SSYNC;
-
- /* Finally, we climb into our cave to hibernate */
- W[P3] = R4.L;
-
- bfin_init_pm_bench_cycles;
-
- CLI R2;
- IDLE;
-.Lforever:
- jump .Lforever;
-ENDPROC(_hibernate_mode)
-
-ENTRY(_sleep_deeper)
- [--SP] = (R7:4, P5:3);
- [--SP] = RETS;
-
- CLI R4;
-
- P3 = R0;
- P4 = R1;
- P5 = R2;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr;
- call _set_dram_srfs; /* Set SDRAM Self Refresh */
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- R6 = W[P0](z);
- R0.L = 0xF;
- W[P0] = R0.l; /* Set Max VCO to SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R5 = W[P0](z);
- R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
- W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- R7 = W[P0](z);
- R1 = 0x6;
- R1 <<= 16;
- R2 = 0x0404(Z);
- R1 = R1|R2;
-
- R2 = DEPOSIT(R7, R1);
- W[P0] = R2; /* Set Min Core Voltage */
-
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = P3;
- R1 = P4;
- R3 = P5;
- call _set_sic_iwr; /* Set Awake from IDLE */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- R0 = W[P0](z);
- BITSET (R0, 3);
- W[P0] = R0.L; /* Turn CCLK OFF */
- SSYNC;
- IDLE;
-
- call _test_pll_locked;
-
- R0 = IWR_ENABLE(0);
- R1 = IWR_DISABLE_ALL;
- R2 = IWR_DISABLE_ALL;
-
- call _set_sic_iwr; /* Set Awake from IDLE PLL */
-
- P0.H = hi(VR_CTL);
- P0.L = lo(VR_CTL);
- W[P0]= R7;
-
- SSYNC;
- IDLE;
-
- bfin_init_pm_bench_cycles;
-
- call _test_pll_locked;
-
- P0.H = hi(PLL_DIV);
- P0.L = lo(PLL_DIV);
- W[P0]= R6; /* Restore CCLK and SCLK divider */
-
- P0.H = hi(PLL_CTL);
- P0.L = lo(PLL_CTL);
- w[p0] = R5; /* Restore VCO multiplier */
- IDLE;
- call _test_pll_locked;
-
- call _unset_dram_srfs; /* SDRAM Self Refresh Off */
-
- STI R4;
-
- RETS = [SP++];
- (R7:4, P5:3) = [SP++];
- RTS;
-ENDPROC(_sleep_deeper)
-
-ENTRY(_set_dram_srfs)
- /* set the dram to self refresh mode */
- SSYNC;
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITSET(R2, 3); /* SRREQ enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-1:
- R2 = [P0];
- CC = BITTST(R2, 4);
- if !CC JUMP 1b;
-#else /* SDRAM */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
- P1.L = lo(EBIU_SDSTAT);
- P1.H = hi(EBIU_SDSTAT);
-
- R2 = [P0];
- BITSET(R2, 24); /* SRFS enter self-refresh mode */
- [P0] = R2;
- SSYNC;
-
-1:
- R2 = w[P1];
- SSYNC;
- cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
- if !cc jump 1b;
-
- R2 = [P0];
- BITCLR(R2, 0); /* SCTLE disable CLKOUT */
- [P0] = R2;
-#endif
- RTS;
-ENDPROC(_set_dram_srfs)
-
-ENTRY(_unset_dram_srfs)
- /* set the dram out of self refresh mode */
-
-#if defined(EBIU_RSTCTL) /* DDR */
- P0.H = hi(EBIU_RSTCTL);
- P0.L = lo(EBIU_RSTCTL);
- R2 = [P0];
- BITCLR(R2, 3); /* clear SRREQ bit */
- [P0] = R2;
-#elif defined(EBIU_SDGCTL) /* SDRAM */
- /* release CLKOUT from self-refresh */
- P0.L = lo(EBIU_SDGCTL);
- P0.H = hi(EBIU_SDGCTL);
-
- R2 = [P0];
- BITSET(R2, 0); /* SCTLE enable CLKOUT */
- [P0] = R2
- SSYNC;
-
- /* release SDRAM from self-refresh */
- R2 = [P0];
- BITCLR(R2, 24); /* clear SRFS bit */
- [P0] = R2
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_unset_dram_srfs)
-
-ENTRY(_set_sic_iwr)
-#ifdef SIC_IWR0
- P0.H = hi(SYSMMR_BASE);
- P0.L = lo(SYSMMR_BASE);
- [P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
- [P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
-# ifdef SIC_IWR2
- [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
-# endif
-#else
- P0.H = hi(SIC_IWR);
- P0.L = lo(SIC_IWR);
- [P0] = R0;
-#endif
-
- SSYNC;
- RTS;
-ENDPROC(_set_sic_iwr)
-
-ENTRY(_test_pll_locked)
- P0.H = hi(PLL_STAT);
- P0.L = lo(PLL_STAT);
-1:
- R0 = W[P0] (Z);
- CC = BITTST(R0,5);
- IF !CC JUMP 1b;
- RTS;
-ENDPROC(_test_pll_locked)
-
-.section .text
-ENTRY(_do_hibernate)
- bfin_cpu_reg_save;
- bfin_sys_mmr_save;
- bfin_core_mmr_save;
-
- /* Setup args to hibernate mode early for pipeline optimization */
- R0 = M3;
- P1.H = _hibernate_mode;
- P1.L = _hibernate_mode;
-
- /* Save Magic, return address and Stack Pointer */
- P0 = 0;
- R1.H = 0xDEAD; /* Hibernate Magic */
- R1.L = 0xBEEF;
- R2.H = .Lpm_resume_here;
- R2.L = .Lpm_resume_here;
- [P0++] = R1; /* Store Hibernate Magic */
- [P0++] = R2; /* Save Return Address */
- [P0++] = SP; /* Save Stack Pointer */
-
- /* Must use an indirect call as we need to jump to L1 */
- call (P1); /* Goodbye */
-
-.Lpm_resume_here:
-
- bfin_core_mmr_restore;
- bfin_sys_mmr_restore;
- bfin_cpu_reg_restore;
-
- [--sp] = RETI; /* Clear Global Interrupt Disable */
- SP += 4;
-
- RTS;
-ENDPROC(_do_hibernate)
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
deleted file mode 100644
index 8d9431e22e8c..000000000000
--- a/arch/blackfin/mach-common/entry.S
+++ /dev/null
@@ -1,1711 +0,0 @@
-/*
- * Contains the system-call and fault low-level handling routines.
- * This also contains the timer-interrupt handler, as well as all
- * interrupts and faults that can result in a task-switch.
- *
- * Copyright 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-/* NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- */
-
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/unistd.h>
-#include <asm/blackfin.h>
-#include <asm/errno.h>
-#include <asm/fixed_code.h>
-#include <asm/thread_info.h> /* TIF_NEED_RESCHED */
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-
-#include <asm/context.S>
-
-
-#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
-.section .l1.text
-#else
-.text
-#endif
-
-/* Slightly simplified and streamlined entry point for CPLB misses.
- * This one does not lower the level to IRQ5, and thus can be used to
- * patch up CPLB misses on the kernel stack.
- */
-#if ANOMALY_05000261
-#define _ex_dviol _ex_workaround_261
-#define _ex_dmiss _ex_workaround_261
-#define _ex_dmult _ex_workaround_261
-
-ENTRY(_ex_workaround_261)
- /*
- * Work around an anomaly: if we see a new DCPLB fault, return
- * without doing anything. Then, if we get the same fault again,
- * handle it.
- */
- P4 = R7; /* Store EXCAUSE */
-
- GET_PDA(p5, r7);
- r7 = [p5 + PDA_LFRETX];
- r6 = retx;
- [p5 + PDA_LFRETX] = r6;
- cc = r6 == r7;
- if !cc jump _bfin_return_from_exception;
- /* fall through */
- R7 = P4;
- R6 = VEC_CPLB_M; /* Data CPLB Miss */
- cc = R6 == R7;
- if cc jump _ex_dcplb_miss (BP);
-#ifdef CONFIG_MPU
- R6 = VEC_CPLB_VL; /* Data CPLB Violation */
- cc = R6 == R7;
- if cc jump _ex_dcplb_viol (BP);
-#endif
- /* Handle Data CPLB Protection Violation
- * and Data CPLB Multiple Hits - Linux Trap Zero
- */
- jump _ex_trap_c;
-ENDPROC(_ex_workaround_261)
-
-#else
-#ifdef CONFIG_MPU
-#define _ex_dviol _ex_dcplb_viol
-#else
-#define _ex_dviol _ex_trap_c
-#endif
-#define _ex_dmiss _ex_dcplb_miss
-#define _ex_dmult _ex_trap_c
-#endif
-
-
-ENTRY(_ex_dcplb_viol)
-ENTRY(_ex_dcplb_miss)
-ENTRY(_ex_icplb_miss)
- (R7:6,P5:4) = [sp++];
- /* We leave the previously pushed ASTAT on the stack. */
- SAVE_CONTEXT_CPLB
-
- /* We must load R1 here, _before_ DEBUG_HWTRACE_SAVE, since that
- * will change the stack pointer. */
- R0 = SEQSTAT;
- R1 = SP;
-
- DEBUG_HWTRACE_SAVE(p5, r7)
-
- sp += -12;
- call _cplb_hdr;
- sp += 12;
- CC = R0 == 0;
- IF !CC JUMP _handle_bad_cplb;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing this, did we double fault? */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = 0x25;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- DEBUG_HWTRACE_RESTORE(p5, r7)
- RESTORE_CONTEXT_CPLB
- ASTAT = [SP++];
- SP = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_ex_icplb_miss)
-
-ENTRY(_ex_syscall)
- raise 15; /* invoked by TRAP #0, for sys call */
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_syscall)
-
-ENTRY(_ex_single_step)
- /* If we just returned from an interrupt, the single step event is
- for the RTI instruction. */
- r7 = retx;
- r6 = reti;
- cc = r7 == r6;
- if cc jump _bfin_return_from_exception;
-
-#ifdef CONFIG_KGDB
- /* Don't do single step in hardware exception handler */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- cc = bittst(r6, 4);
- if cc jump _bfin_return_from_exception;
- cc = bittst(r6, 5);
- if cc jump _bfin_return_from_exception;
-
- /* skip single step if current interrupt priority is higher than
- * that of the first instruction, from which gdb starts single step */
- r6 >>= 6;
- r7 = 10;
-.Lfind_priority_start:
- cc = bittst(r6, 0);
- if cc jump .Lfind_priority_done;
- r6 >>= 1;
- r7 += -1;
- cc = r7 == 0;
- if cc jump .Lfind_priority_done;
- jump.s .Lfind_priority_start;
-.Lfind_priority_done:
- p4.l = _kgdb_single_step;
- p4.h = _kgdb_single_step;
- r6 = [p4];
- cc = r6 == 0;
- if cc jump .Ldo_single_step;
- r6 += -1;
- cc = r6 < r7;
- if cc jump 1f;
-.Ldo_single_step:
-#else
- /* If we were in user mode, do the single step normally. */
- p5.l = lo(IPEND);
- p5.h = hi(IPEND);
- r6 = [p5];
- r7 = 0xffe0 (z);
- r7 = r7 & r6;
- cc = r7 == 0;
- if !cc jump 1f;
-#endif
-#ifdef CONFIG_EXACT_HWERR
- /* Read the ILAT, and to check to see if the process we are
- * single stepping caused a previous hardware error
- * If so, do not single step, (which lowers to IRQ5, and makes
- * us miss the error).
- */
- p5.l = lo(ILAT);
- p5.h = hi(ILAT);
- r7 = [p5];
- cc = bittst(r7, EVT_IVHW_P);
- if cc jump 1f;
-#endif
- /* Single stepping only a single instruction, so clear the trace
- * bit here. */
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P);
- syscfg = R7;
- jump _ex_trap_c;
-
-1:
- /*
- * We were in an interrupt handler. By convention, all of them save
- * SYSCFG with their first instruction, so by checking whether our
- * RETX points at the entry point, we can determine whether to allow
- * a single step, or whether to clear SYSCFG.
- *
- * First, find out the interrupt level and the event vector for it.
- */
- p5.l = lo(EVT0);
- p5.h = hi(EVT0);
- p5 += -4;
-2:
- r7 = rot r7 by -1;
- p5 += 4;
- if !cc jump 2b;
-
- /* What we actually do is test for the _second_ instruction in the
- * IRQ handler. That way, if there are insns following the restore
- * of SYSCFG after leaving the handler, we will not turn off SYSCFG
- * for them. */
-
- r7 = [p5];
- r7 += 2;
- r6 = RETX;
- cc = R7 == R6;
- if !cc jump _bfin_return_from_exception;
-
- r7 = syscfg;
- bitclr (r7, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = R7;
-
- /* Fall through to _bfin_return_from_exception. */
-ENDPROC(_ex_single_step)
-
-ENTRY(_bfin_return_from_exception)
-#if ANOMALY_05000257
- R7=LC0;
- LC0=R7;
- R7=LC1;
- LC1=R7;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* While we were processing the current exception,
- * did we cause another, and double fault?
- */
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- r6 = VEC_UNCOV;
- CC = R7 == R6;
- if CC JUMP _double_fault;
-#endif
-
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- sp = EX_SCRATCH_REG;
- rtx;
-ENDPROC(_bfin_return_from_exception)
-
-ENTRY(_handle_bad_cplb)
- DEBUG_HWTRACE_RESTORE(p5, r7)
- /* To get here, we just tried and failed to change a CPLB
- * so, handle things in trap_c (C code), by lowering to
- * IRQ5, just like we normally do. Since this is not a
- * "normal" return path, we have a do a lot of stuff to
- * the stack to get ready so, we can fall through - we
- * need to make a CPLB exception look like a normal exception
- */
- RESTORE_CONTEXT_CPLB
- /* ASTAT is still on the stack, where it is needed. */
- [--sp] = (R7:6,P5:4);
-
-ENTRY(_ex_replaceable)
- nop;
-
-ENTRY(_ex_trap_c)
- /* The only thing that has been saved in this context is
- * (R7:6,P5:4), ASTAT & SP - don't use anything else
- */
-
- GET_PDA(p5, r6);
-
- /* Make sure we are not in a double fault */
- p4.l = lo(IPEND);
- p4.h = hi(IPEND);
- r7 = [p4];
- CC = BITTST (r7, 5);
- if CC jump _double_fault;
- [p5 + PDA_EXIPEND] = r7;
-
- /* Call C code (trap_c) to handle the exception, which most
- * likely involves sending a signal to the current process.
- * To avoid double faults, lower our priority to IRQ5 first.
- */
- r7.h = _exception_to_level5;
- r7.l = _exception_to_level5;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r6 = [p4];
- [p5 + PDA_ICPLB] = r6;
-
- r6 = retx;
- [p5 + PDA_RETX] = r6;
-
- r6 = SEQSTAT;
- [p5 + PDA_SEQSTAT] = r6;
-
- /* Save the state of single stepping */
- r6 = SYSCFG;
- [p5 + PDA_SYSCFG] = r6;
- /* Clear it while we handle the exception in IRQ5 mode */
- BITCLR(r6, SYSCFG_SSSTEP_P);
- SYSCFG = r6;
-
- /* Save the current IMASK, since we change in order to jump to level 5 */
- cli r6;
- [p5 + PDA_EXIMASK] = r6;
-
- p4.l = lo(SAFE_USER_INSTRUCTION);
- p4.h = hi(SAFE_USER_INSTRUCTION);
- retx = p4;
-
- /* Disable all interrupts, but make sure level 5 is enabled so
- * we can switch to that level.
- */
- r6 = 0x3f;
- sti r6;
-
- /* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
- * clear it (re-enabling interrupts again) by the special sequence of pushing
- * RETI onto the stack. This way we can lower ourselves to IVG5 even if the
- * exception was taken after the interrupt handler was called but before it
- * got a chance to enable global interrupts itself.
- */
- [--sp] = reti;
- sp += 4;
-
- raise 5;
- jump.s _bfin_return_from_exception;
-ENDPROC(_ex_trap_c)
-
-/* We just realized we got an exception, while we were processing a different
- * exception. This is a unrecoverable event, so crash.
- * Note: this cannot be ENTRY() as we jump here with "if cc jump" ...
- */
-ENTRY(_double_fault)
- /* Turn caches & protection off, to ensure we don't get any more
- * double exceptions
- */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- /* Fix up the stack */
- (R7:6,P5:4) = [sp++];
- ASTAT = [sp++];
- SP = EX_SCRATCH_REG;
-
- /* We should be out of the exception stack, and back down into
- * kernel or user space stack
- */
- SAVE_ALL_SYS
-
- /* The dumping functions expect the return address in the RETI
- * slot. */
- r6 = retx;
- [sp + PT_PC] = r6;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _double_fault_c, p5;
- SP += 12;
-.L_double_fault_panic:
- JUMP .L_double_fault_panic
-
-ENDPROC(_double_fault)
-
-ENTRY(_exception_to_level5)
- SAVE_ALL_SYS
-
- GET_PDA(p5, r7); /* Fetch current PDA */
- r6 = [p5 + PDA_RETX];
- [sp + PT_PC] = r6;
-
- r6 = [p5 + PDA_SYSCFG];
- [sp + PT_SYSCFG] = r6;
-
- r6 = [p5 + PDA_SEQSTAT]; /* Read back seqstat */
- [sp + PT_SEQSTAT] = r6;
-
- /* Restore the hardware error vector. */
- r7.h = _evt_ivhw;
- r7.l = _evt_ivhw;
- p4.l = lo(EVT5);
- p4.h = hi(EVT5);
- [p4] = r7;
- csync;
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Now that we have the hardware error vector programmed properly
- * we can re-enable interrupts (IPEND[4]), so if the _trap_c causes
- * another hardware error, we can catch it (self-nesting).
- */
- [--sp] = reti;
- sp += 4;
-#endif
-
- r7 = [p5 + PDA_EXIPEND] /* Read the IPEND from the Exception state */
- [sp + PT_IPEND] = r7; /* Store IPEND onto the stack */
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p4;
- SP += 12;
-
- /* If interrupts were off during the exception (IPEND[4] = 1), turn them off
- * before we return.
- */
- CC = BITTST(r7, EVT_IRPTEN_P)
- if !CC jump 1f;
- /* this will load a random value into the reti register - but that is OK,
- * since we do restore it to the correct value in the 'RESTORE_ALL_SYS' macro
- */
- sp += -4;
- reti = [sp++];
-1:
- /* restore the interrupt mask (IMASK) */
- r6 = [p5 + PDA_EXIMASK];
- sti r6;
-
- call _ret_from_exception;
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_exception_to_level5)
-
-ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
- /* Since the kernel stack can be anywhere, it's not guaranteed to be
- * covered by a CPLB. Switch to an exception stack; use RETN as a
- * scratch register (for want of a better option).
- */
- EX_SCRATCH_REG = sp;
- GET_PDA_SAFE(sp);
- sp = [sp + PDA_EXSTACK];
- /* Try to deal with syscalls quickly. */
- [--sp] = ASTAT;
- [--sp] = (R7:6,P5:4);
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
-#ifdef CONFIG_EXACT_HWERR
- /* Make sure all pending read/writes complete. This will ensure any
- * accesses which could cause hardware errors completes, and signal
- * the the hardware before we do something silly, like crash the
- * kernel. We don't need to work around anomaly 05000312, since
- * we are already atomic
- */
- ssync;
-#endif
-
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /*
- * Save these registers, as they are only valid in exception context
- * (where we are now - as soon as we defer to IRQ5, they can change)
- * DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
- * but they are not very interesting, so don't save them
- */
-
- GET_PDA(p5, r7);
- p4.l = lo(DCPLB_FAULT_ADDR);
- p4.h = hi(DCPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_DCPLB] = r7;
-
- p4.l = lo(ICPLB_FAULT_ADDR);
- p4.h = hi(ICPLB_FAULT_ADDR);
- r7 = [p4];
- [p5 + PDA_DF_ICPLB] = r7;
-
- r7 = retx;
- [p5 + PDA_DF_RETX] = r7;
-
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
- [p5 + PDA_DF_SEQSTAT] = r7;
-#else
- r7 = SEQSTAT; /* reason code is in bit 5:0 */
-#endif
- r6.l = lo(SEQSTAT_EXCAUSE);
- r6.h = hi(SEQSTAT_EXCAUSE);
- r7 = r7 & r6;
- p5.h = _ex_table;
- p5.l = _ex_table;
- p4 = r7;
- p5 = p5 + (p4 << 2);
- p4 = [p5];
- jump (p4);
-
-.Lbadsys:
- r7 = -ENOSYS; /* signextending enough */
- [sp + PT_R0] = r7; /* return value from system call */
- jump .Lsyscall_really_exit;
-ENDPROC(_trap)
-
-ENTRY(_system_call)
- /* Store IPEND */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* Store RETS for now */
- r0 = rets;
- [sp + PT_RESERVED] = r0;
- /* Set the stack for the current process */
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6; /* thread_info */
- p2 = r7;
- p2 = [p2];
-
- [p2+(TASK_THREAD+THREAD_KSP)] = sp;
-#ifdef CONFIG_IPIPE
- r0 = sp;
- SP += -12;
- pseudo_long_call ___ipipe_syscall_root, p0;
- SP += 12;
- cc = r0 == 1;
- if cc jump .Lsyscall_really_exit;
- cc = r0 == -1;
- if cc jump .Lresume_userspace;
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- p0 = [sp + PT_ORIG_P0];
-#endif /* CONFIG_IPIPE */
-
- /* are we tracing syscalls?*/
- r7 = sp;
- r6.l = lo(ALIGN_PAGE_MASK);
- r6.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r6;
- p2 = r7;
- r7 = [p2+TI_FLAGS];
- CC = BITTST(r7,TIF_SYSCALL_TRACE);
- if CC JUMP _sys_trace;
- CC = BITTST(r7,TIF_SINGLESTEP);
- if CC JUMP _sys_trace;
-
- /* Make sure the system call # is valid */
- p4 = __NR_syscall;
- /* System call number is passed in P0 */
- cc = p4 <= p0;
- if cc jump .Lbadsys;
-
- /* Execute the appropriate system call */
-
- p4 = p0;
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
- [sp + PT_R0] = r0;
-
-.Lresume_userspace:
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
-.Lresume_userspace_1:
- /* Disable interrupts. */
- [--sp] = reti;
- reti = [sp++];
-
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
-
-.Lsyscall_resched:
-#ifdef CONFIG_IPIPE
- cc = BITTST(r7, TIF_IRQ_SYNC);
- if !cc jump .Lsyscall_no_irqsync;
- /*
- * Clear IPEND[4] manually to undo what resume_userspace_1 just did;
- * we need this so that high priority domain interrupts may still
- * preempt the current domain while the pipeline log is being played
- * back.
- */
- [--sp] = reti;
- SP += 4; /* don't merge with next insn to keep the pattern obvious */
- SP += -12;
- pseudo_long_call ___ipipe_sync_root, p4;
- SP += 12;
- jump .Lresume_userspace_1;
-.Lsyscall_no_irqsync:
-#endif
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lsyscall_sigpending;
-
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- SP += -12;
- pseudo_long_call _schedule, p4;
- SP += 12;
-
- jump .Lresume_userspace_1;
-
-.Lsyscall_sigpending:
- cc = BITTST(r7, TIF_SIGPENDING);
- if cc jump .Lsyscall_do_signals;
- cc = BITTST(r7, TIF_NOTIFY_RESUME);
- if !cc jump .Lsyscall_really_exit;
-.Lsyscall_do_signals:
- /* Reenable interrupts. */
- [--sp] = reti;
- sp += 4;
-
- r0 = sp;
- SP += -12;
- pseudo_long_call _do_notify_resume, p5;
- SP += 12;
-
-.Lsyscall_really_exit:
- r5 = [sp + PT_RESERVED];
- rets = r5;
- rts;
-ENDPROC(_system_call)
-
-/* Do not mark as ENTRY() to avoid error in assembler ...
- * this symbol need not be global anyways, so ...
- */
-_sys_trace:
- r0 = sp;
- pseudo_long_call _syscall_trace_enter, p5;
-
- /* Make sure the system call # is valid */
- p4 = [SP + PT_P0];
- p3 = __NR_syscall;
- cc = p3 <= p4;
- r0 = -ENOSYS;
- if cc jump .Lsys_trace_badsys;
-
- /* Execute the appropriate system call */
- p5.l = _sys_call_table;
- p5.h = _sys_call_table;
- p5 = p5 + (p4 << 2);
- r0 = [sp + PT_R0];
- r1 = [sp + PT_R1];
- r2 = [sp + PT_R2];
- r3 = [sp + PT_R3];
- r4 = [sp + PT_R4];
- r5 = [sp + PT_R5];
- p5 = [p5];
-
- [--sp] = r5;
- [--sp] = r4;
- [--sp] = r3;
- SP += -12;
- call (p5);
- SP += 24;
-.Lsys_trace_badsys:
- [sp + PT_R0] = r0;
-
- r0 = sp;
- pseudo_long_call _syscall_trace_leave, p5;
- jump .Lresume_userspace;
-ENDPROC(_sys_trace)
-
-ENTRY(_resume)
- /*
- * Beware - when entering resume, prev (the current task) is
- * in r0, next (the new task) is in r1.
- */
- p0 = r0;
- p1 = r1;
- [--sp] = rets;
- [--sp] = fp;
- [--sp] = (r7:4, p5:3);
-
- /* save usp */
- p2 = usp;
- [p0+(TASK_THREAD+THREAD_USP)] = p2;
-
- /* save current kernel stack pointer */
- [p0+(TASK_THREAD+THREAD_KSP)] = sp;
-
- /* save program counter */
- r1.l = _new_old_task;
- r1.h = _new_old_task;
- [p0+(TASK_THREAD+THREAD_PC)] = r1;
-
- /* restore the kernel stack pointer */
- sp = [p1+(TASK_THREAD+THREAD_KSP)];
-
- /* restore user stack pointer */
- p0 = [p1+(TASK_THREAD+THREAD_USP)];
- usp = p0;
-
- /* restore pc */
- p0 = [p1+(TASK_THREAD+THREAD_PC)];
- jump (p0);
-
- /*
- * Following code actually lands up in a new (old) task.
- */
-
-_new_old_task:
- (r7:4, p5:3) = [sp++];
- fp = [sp++];
- rets = [sp++];
-
- /*
- * When we come out of resume, r0 carries "old" task, because we are
- * in "new" task.
- */
- rts;
-ENDPROC(_resume)
-
-ENTRY(_ret_from_exception)
-#ifdef CONFIG_IPIPE
- p2.l = _ipipe_percpu_domain;
- p2.h = _ipipe_percpu_domain;
- r0.l = _ipipe_root;
- r0.h = _ipipe_root;
- r2 = [p2];
- cc = r0 == r2;
- if !cc jump 4f; /* not on behalf of the root domain, get out */
-#endif /* CONFIG_IPIPE */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
-
- csync;
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
-1:
- r2 = LO(~0x37) (Z);
- r0 = r2 & r0;
- cc = r0 == 0;
- if !cc jump 4f; /* if not return to user mode, get out */
-
- /* Make sure any pending system call or deferred exception
- * return in ILAT for this process to get executed, otherwise
- * in case context switch happens, system call of
- * first process (i.e in ILAT) will be carried
- * forward to the switched process
- */
-
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- r1 = (EVT_IVG14 | EVT_IVG15) (z);
- r0 = r0 & r1;
- cc = r0 == 0;
- if !cc jump 5f;
-
- /* Set the stack for the current process */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4; /* thread_info->flags */
- p5 = r7;
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = r7 == 0;
- if cc jump 4f;
-
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal;
- p1.h = _schedule_and_signal;
- [p0] = p1;
- csync;
- raise 15; /* raise evt15 to do signal or reschedule */
-4:
- r0 = syscfg;
- bitclr(r0, SYSCFG_SSSTEP_P); /* Turn off single step */
- syscfg = r0;
-5:
- rts;
-ENDPROC(_ret_from_exception)
-
-#if defined(CONFIG_PREEMPT)
-
-ENTRY(_up_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
-
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_up_evt14;
- p1.h = _evt_up_evt14;
- [p0] = p1;
- csync;
-
- raise 14;
-1:
- jump 1b;
-ENDPROC(_up_to_irq14)
-
-ENTRY(_evt_up_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
-
- /* restore normal evt14 */
- p0.l = lo(EVT14);
- p0.h = hi(EVT14);
- p1.l = _evt_evt14;
- p1.h = _evt_evt14;
- [p0] = p1;
- csync;
-
- rts;
-ENDPROC(_evt_up_evt14)
-
-#endif
-
-#ifdef CONFIG_IPIPE
-
-_resume_kernel_from_int:
- r1 = LO(~0x8000) (Z);
- r1 = r0 & r1;
- r0 = 1;
- r0 = r1 - r0;
- r2 = r1 & r0;
- cc = r2 == 0;
- /* Sync the root stage only from the outer interrupt level. */
- if !cc jump .Lnosync;
- r0.l = ___ipipe_sync_root;
- r0.h = ___ipipe_sync_root;
- [--sp] = reti;
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- SP += -12;
- call ___ipipe_call_irqtail
- SP += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
- reti = [sp++];
-.Lnosync:
- rts
-#elif defined(CONFIG_PREEMPT)
-
-_resume_kernel_from_int:
- /* check preempt_count */
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT];
- cc = r7 == 0x0;
- if !cc jump .Lreturn_to_kernel;
-.Lneed_schedule:
- r7 = [p5 + TI_FLAGS];
- r4.l = lo(_TIF_WORK_MASK);
- r4.h = hi(_TIF_WORK_MASK);
- r7 = r7 & r4;
- cc = BITTST(r7, TIF_NEED_RESCHED);
- if !cc jump .Lreturn_to_kernel;
- /*
- * let schedule done at level 15, otherwise sheduled process will run
- * at high level and block low level interrupt
- */
- r6 = reti; /* save reti */
- r5.l = .Lkernel_schedule;
- r5.h = .Lkernel_schedule;
- reti = r5;
- rti;
-.Lkernel_schedule:
- [--sp] = rets;
- sp += -12;
- pseudo_long_call _preempt_schedule_irq, p4;
- sp += 12;
- rets = [sp++];
-
- [--sp] = rets;
- sp += -12;
- /* up to irq14 so that reti after restore_all can return to irq15(kernel) */
- pseudo_long_call _up_to_irq14, p4;
- sp += 12;
- rets = [sp++];
-
- reti = r6; /* restore reti so that origin process can return to interrupted point */
-
- jump .Lneed_schedule;
-#else
-
-#define _resume_kernel_from_int .Lreturn_to_kernel
-#endif
-
-ENTRY(_return_from_int)
- /* If someone else already raised IRQ 15, do nothing. */
- csync;
- p2.l = lo(ILAT);
- p2.h = hi(ILAT);
- r0 = [p2];
- cc = bittst (r0, EVT_IVG15_P);
- if cc jump .Lreturn_to_kernel;
-
- /* if not return to user mode, get out */
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- r1 = 0x17(Z);
- r2 = ~r1;
- r2.h = 0;
- r0 = r2 & r0;
- r1 = 1;
- r1 = r0 - r1;
- r2 = r0 & r1;
- cc = r2 == 0;
- if !cc jump _resume_kernel_from_int;
-
- /* Lower the interrupt level to 15. */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _schedule_and_signal_from_int;
- p1.h = _schedule_and_signal_from_int;
- [p0] = p1;
- csync;
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
- r0 = 0x801f (z);
- STI r0;
- raise 15; /* raise evt15 to do signal or reschedule */
- rti;
-.Lreturn_to_kernel:
- rts;
-ENDPROC(_return_from_int)
-
-ENTRY(_lower_to_irq14)
-#if ANOMALY_05000281 || ANOMALY_05000461
- r0.l = lo(SAFE_USER_INSTRUCTION);
- r0.h = hi(SAFE_USER_INSTRUCTION);
- reti = r0;
-#endif
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14;
- rti;
-ENDPROC(_lower_to_irq14)
-
-ENTRY(_evt_evt14)
-#ifdef CONFIG_DEBUG_HWERR
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#else
- cli r0;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = rets;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- rets = [sp++];
-#endif
- [--sp] = RETI;
- SP += 4;
- rts;
-ENDPROC(_evt_evt14)
-
-ENTRY(_schedule_and_signal_from_int)
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
-
- /* Set orig_p0 to -1 to indicate this isn't the end of a syscall. */
- r0 = -1 (x);
- [sp + PT_ORIG_P0] = r0;
-
- p1 = rets;
- [sp + PT_RESERVED] = p1;
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- /* trace_hardirqs_on() checks if all irqs are disabled. But here IRQ 15
- * is turned on, so disable all irqs. */
- cli r0;
- sp += -12;
- call _trace_hardirqs_on;
- sp += 12;
-#endif
-#ifdef CONFIG_SMP
- GET_PDA(p0, r0); /* Fetch current PDA (can't migrate to other CPU here) */
- r0 = [p0 + PDA_IRQFLAGS];
-#else
- p0.l = _bfin_irq_flags;
- p0.h = _bfin_irq_flags;
- r0 = [p0];
-#endif
- sti r0;
-
- /* finish the userspace "atomic" functions for it */
- r1.l = lo(FIXED_CODE_END);
- r1.h = hi(FIXED_CODE_END);
- r2 = [sp + PT_PC];
- cc = r1 <= r2;
- if cc jump .Lresume_userspace (bp);
-
- r0 = sp;
- sp += -12;
-
- pseudo_long_call _finish_atomic_sections, p5;
- sp += 12;
- jump.s .Lresume_userspace;
-ENDPROC(_schedule_and_signal_from_int)
-
-ENTRY(_schedule_and_signal)
- SAVE_CONTEXT_SYSCALL
- /* To end up here, vector 15 was changed - so we have to change it
- * back.
- */
- p0.l = lo(EVT15);
- p0.h = hi(EVT15);
- p1.l = _evt_system_call;
- p1.h = _evt_system_call;
- [p0] = p1;
- csync;
- p0.l = 1f;
- p0.h = 1f;
- [sp + PT_RESERVED] = P0;
- call .Lresume_userspace;
-1:
- RESTORE_CONTEXT
- rti;
-ENDPROC(_schedule_and_signal)
-
-/* We handle this 100% in exception space - to reduce overhead
- * Only potiential problem is if the software buffer gets swapped out of the
- * CPLB table - then double fault. - so we don't let this happen in other places
- */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-ENTRY(_ex_trace_buff_full)
- [--sp] = P3;
- [--sp] = P2;
- [--sp] = LC0;
- [--sp] = LT0;
- [--sp] = LB0;
- P5.L = _trace_buff_offset;
- P5.H = _trace_buff_offset;
- P3 = [P5]; /* trace_buff_offset */
- P5.L = lo(TBUFSTAT);
- P5.H = hi(TBUFSTAT);
- R7 = [P5];
- R7 <<= 1; /* double, since we need to read twice */
- LC0 = R7;
- R7 <<= 2; /* need to shift over again,
- * to get the number of bytes */
- P5.L = lo(TBUF);
- P5.H = hi(TBUF);
- R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1;
-
- P2 = R7;
- P3 = P3 + P2;
- R7 = P3;
- R7 = R7 & R6;
- P3 = R7;
- P2.L = _trace_buff_offset;
- P2.H = _trace_buff_offset;
- [P2] = P3;
-
- P2.L = _software_trace_buff;
- P2.H = _software_trace_buff;
-
- LSETUP (.Lstart, .Lend) LC0;
-.Lstart:
- R7 = [P5]; /* read TBUF */
- P4 = P3 + P2;
- [P4] = R7;
- P3 += -4;
- R7 = P3;
- R7 = R7 & R6;
-.Lend:
- P3 = R7;
-
- LB0 = [sp++];
- LT0 = [sp++];
- LC0 = [sp++];
- P2 = [sp++];
- P3 = [sp++];
- jump _bfin_return_from_exception;
-ENDPROC(_ex_trace_buff_full)
-
-#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4
-.data
-#else
-.section .l1.data.B
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */
-ENTRY(_trace_buff_offset)
- .long 0;
-ALIGN
-ENTRY(_software_trace_buff)
- .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256);
- .long 0
- .endr
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */
-
-#ifdef CONFIG_EARLY_PRINTK
-__INIT
-ENTRY(_early_trap)
- SAVE_ALL_SYS
- trace_buffer_stop(p0,r0);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- /* Turn caches off, to ensure we don't get double exceptions */
-
- P4.L = LO(IMEM_CONTROL);
- P4.H = HI(IMEM_CONTROL);
-
- R5 = [P4]; /* Control Register*/
- BITCLR(R5,ENICPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- P4.L = LO(DMEM_CONTROL);
- P4.H = HI(DMEM_CONTROL);
- R5 = [P4];
- BITCLR(R5,ENDCPLB_P);
- CSYNC; /* Disabling of CPLBs should be proceeded by a CSYNC */
- [P4] = R5;
- SSYNC;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- r1 = RETX;
-
- SP += -12;
- call _early_trap_c;
- SP += 12;
-ENDPROC(_early_trap)
-__FINIT
-#endif /* CONFIG_EARLY_PRINTK */
-
-/*
- * Put these in the kernel data section - that should always be covered by
- * a CPLB. This is needed to ensure we don't get double fault conditions
- */
-
-#ifdef CONFIG_SYSCALL_TAB_L1
-.section .l1.data
-#else
-.data
-#endif
-
-ENTRY(_ex_table)
- /* entry for each EXCAUSE[5:0]
- * This table must be in sync with the table in ./kernel/traps.c
- * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
- */
- .long _ex_syscall /* 0x00 - User Defined - Linux Syscall */
- .long _ex_trap_c /* 0x01 - User Defined - Software breakpoint */
-#ifdef CONFIG_KGDB
- .long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection
- and break signal trap */
-#else
- .long _ex_replaceable /* 0x02 - User Defined */
-#endif
- .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
- .long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */
- .long _ex_replaceable /* 0x05 - User Defined */
- .long _ex_replaceable /* 0x06 - User Defined */
- .long _ex_replaceable /* 0x07 - User Defined */
- .long _ex_replaceable /* 0x08 - User Defined */
- .long _ex_replaceable /* 0x09 - User Defined */
- .long _ex_replaceable /* 0x0A - User Defined */
- .long _ex_replaceable /* 0x0B - User Defined */
- .long _ex_replaceable /* 0x0C - User Defined */
- .long _ex_replaceable /* 0x0D - User Defined */
- .long _ex_replaceable /* 0x0E - User Defined */
- .long _ex_replaceable /* 0x0F - User Defined */
- .long _ex_single_step /* 0x10 - HW Single step */
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
- .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */
-#else
- .long _ex_trap_c /* 0x11 - Trace Buffer Full */
-#endif
- .long _ex_trap_c /* 0x12 - Reserved */
- .long _ex_trap_c /* 0x13 - Reserved */
- .long _ex_trap_c /* 0x14 - Reserved */
- .long _ex_trap_c /* 0x15 - Reserved */
- .long _ex_trap_c /* 0x16 - Reserved */
- .long _ex_trap_c /* 0x17 - Reserved */
- .long _ex_trap_c /* 0x18 - Reserved */
- .long _ex_trap_c /* 0x19 - Reserved */
- .long _ex_trap_c /* 0x1A - Reserved */
- .long _ex_trap_c /* 0x1B - Reserved */
- .long _ex_trap_c /* 0x1C - Reserved */
- .long _ex_trap_c /* 0x1D - Reserved */
- .long _ex_trap_c /* 0x1E - Reserved */
- .long _ex_trap_c /* 0x1F - Reserved */
- .long _ex_trap_c /* 0x20 - Reserved */
- .long _ex_trap_c /* 0x21 - Undefined Instruction */
- .long _ex_trap_c /* 0x22 - Illegal Instruction Combination */
- .long _ex_dviol /* 0x23 - Data CPLB Protection Violation */
- .long _ex_trap_c /* 0x24 - Data access misaligned */
- .long _ex_trap_c /* 0x25 - Unrecoverable Event */
- .long _ex_dmiss /* 0x26 - Data CPLB Miss */
- .long _ex_dmult /* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero */
- .long _ex_trap_c /* 0x28 - Emulation Watchpoint */
- .long _ex_trap_c /* 0x29 - Instruction fetch access error (535 only) */
- .long _ex_trap_c /* 0x2A - Instruction fetch misaligned */
- .long _ex_trap_c /* 0x2B - Instruction CPLB protection Violation */
- .long _ex_icplb_miss /* 0x2C - Instruction CPLB miss */
- .long _ex_trap_c /* 0x2D - Instruction CPLB Multiple Hits */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2E - Illegal use of Supervisor Resource */
- .long _ex_trap_c /* 0x2F - Reserved */
- .long _ex_trap_c /* 0x30 - Reserved */
- .long _ex_trap_c /* 0x31 - Reserved */
- .long _ex_trap_c /* 0x32 - Reserved */
- .long _ex_trap_c /* 0x33 - Reserved */
- .long _ex_trap_c /* 0x34 - Reserved */
- .long _ex_trap_c /* 0x35 - Reserved */
- .long _ex_trap_c /* 0x36 - Reserved */
- .long _ex_trap_c /* 0x37 - Reserved */
- .long _ex_trap_c /* 0x38 - Reserved */
- .long _ex_trap_c /* 0x39 - Reserved */
- .long _ex_trap_c /* 0x3A - Reserved */
- .long _ex_trap_c /* 0x3B - Reserved */
- .long _ex_trap_c /* 0x3C - Reserved */
- .long _ex_trap_c /* 0x3D - Reserved */
- .long _ex_trap_c /* 0x3E - Reserved */
- .long _ex_trap_c /* 0x3F - Reserved */
-END(_ex_table)
-
-ENTRY(_sys_call_table)
- .long _sys_restart_syscall /* 0 */
- .long _sys_exit
- .long _sys_ni_syscall /* fork */
- .long _sys_read
- .long _sys_write
- .long _sys_open /* 5 */
- .long _sys_close
- .long _sys_ni_syscall /* old waitpid */
- .long _sys_creat
- .long _sys_link
- .long _sys_unlink /* 10 */
- .long _sys_execve
- .long _sys_chdir
- .long _sys_time
- .long _sys_mknod
- .long _sys_chmod /* 15 */
- .long _sys_chown /* chown16 */
- .long _sys_ni_syscall /* old break syscall holder */
- .long _sys_ni_syscall /* old stat */
- .long _sys_lseek
- .long _sys_getpid /* 20 */
- .long _sys_mount
- .long _sys_ni_syscall /* old umount */
- .long _sys_setuid
- .long _sys_getuid
- .long _sys_stime /* 25 */
- .long _sys_ptrace
- .long _sys_alarm
- .long _sys_ni_syscall /* old fstat */
- .long _sys_pause
- .long _sys_ni_syscall /* old utime */ /* 30 */
- .long _sys_ni_syscall /* old stty syscall holder */
- .long _sys_ni_syscall /* old gtty syscall holder */
- .long _sys_access
- .long _sys_nice
- .long _sys_ni_syscall /* 35 */ /* old ftime syscall holder */
- .long _sys_sync
- .long _sys_kill
- .long _sys_rename
- .long _sys_mkdir
- .long _sys_rmdir /* 40 */
- .long _sys_dup
- .long _sys_pipe
- .long _sys_times
- .long _sys_ni_syscall /* old prof syscall holder */
- .long _sys_brk /* 45 */
- .long _sys_setgid
- .long _sys_getgid
- .long _sys_ni_syscall /* old sys_signal */
- .long _sys_geteuid /* geteuid16 */
- .long _sys_getegid /* getegid16 */ /* 50 */
- .long _sys_acct
- .long _sys_umount /* recycled never used phys() */
- .long _sys_ni_syscall /* old lock syscall holder */
- .long _sys_ioctl
- .long _sys_fcntl /* 55 */
- .long _sys_ni_syscall /* old mpx syscall holder */
- .long _sys_setpgid
- .long _sys_ni_syscall /* old ulimit syscall holder */
- .long _sys_ni_syscall /* old old uname */
- .long _sys_umask /* 60 */
- .long _sys_chroot
- .long _sys_ustat
- .long _sys_dup2
- .long _sys_getppid
- .long _sys_getpgrp /* 65 */
- .long _sys_setsid
- .long _sys_ni_syscall /* old sys_sigaction */
- .long _sys_sgetmask
- .long _sys_ssetmask
- .long _sys_setreuid /* setreuid16 */ /* 70 */
- .long _sys_setregid /* setregid16 */
- .long _sys_ni_syscall /* old sys_sigsuspend */
- .long _sys_ni_syscall /* old sys_sigpending */
- .long _sys_sethostname
- .long _sys_setrlimit /* 75 */
- .long _sys_ni_syscall /* old getrlimit */
- .long _sys_getrusage
- .long _sys_gettimeofday
- .long _sys_settimeofday
- .long _sys_getgroups /* getgroups16 */ /* 80 */
- .long _sys_setgroups /* setgroups16 */
- .long _sys_ni_syscall /* old_select */
- .long _sys_symlink
- .long _sys_ni_syscall /* old lstat */
- .long _sys_readlink /* 85 */
- .long _sys_uselib
- .long _sys_ni_syscall /* sys_swapon */
- .long _sys_reboot
- .long _sys_ni_syscall /* old_readdir */
- .long _sys_ni_syscall /* sys_mmap */ /* 90 */
- .long _sys_munmap
- .long _sys_truncate
- .long _sys_ftruncate
- .long _sys_fchmod
- .long _sys_fchown /* fchown16 */ /* 95 */
- .long _sys_getpriority
- .long _sys_setpriority
- .long _sys_ni_syscall /* old profil syscall holder */
- .long _sys_statfs
- .long _sys_fstatfs /* 100 */
- .long _sys_ni_syscall
- .long _sys_ni_syscall /* old sys_socketcall */
- .long _sys_syslog
- .long _sys_setitimer
- .long _sys_getitimer /* 105 */
- .long _sys_newstat
- .long _sys_newlstat
- .long _sys_newfstat
- .long _sys_ni_syscall /* old uname */
- .long _sys_ni_syscall /* iopl for i386 */ /* 110 */
- .long _sys_vhangup
- .long _sys_ni_syscall /* obsolete idle() syscall */
- .long _sys_ni_syscall /* vm86old for i386 */
- .long _sys_wait4
- .long _sys_ni_syscall /* 115 */ /* sys_swapoff */
- .long _sys_sysinfo
- .long _sys_ni_syscall /* old sys_ipc */
- .long _sys_fsync
- .long _sys_ni_syscall /* old sys_sigreturn */
- .long _bfin_clone /* 120 */
- .long _sys_setdomainname
- .long _sys_newuname
- .long _sys_ni_syscall /* old sys_modify_ldt */
- .long _sys_adjtimex
- .long _sys_mprotect /* 125 */
- .long _sys_ni_syscall /* old sys_sigprocmask */
- .long _sys_ni_syscall /* old "creat_module" */
- .long _sys_init_module
- .long _sys_delete_module
- .long _sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long _sys_quotactl
- .long _sys_getpgid
- .long _sys_fchdir
- .long _sys_bdflush
- .long _sys_ni_syscall /* 135 */ /* sys_sysfs */
- .long _sys_personality
- .long _sys_ni_syscall /* for afs_syscall */
- .long _sys_setfsuid /* setfsuid16 */
- .long _sys_setfsgid /* setfsgid16 */
- .long _sys_llseek /* 140 */
- .long _sys_getdents
- .long _sys_ni_syscall /* sys_select */
- .long _sys_flock
- .long _sys_msync
- .long _sys_readv /* 145 */
- .long _sys_writev
- .long _sys_getsid
- .long _sys_fdatasync
- .long _sys_sysctl
- .long _sys_mlock /* 150 */
- .long _sys_munlock
- .long _sys_mlockall
- .long _sys_munlockall
- .long _sys_sched_setparam
- .long _sys_sched_getparam /* 155 */
- .long _sys_sched_setscheduler
- .long _sys_sched_getscheduler
- .long _sys_sched_yield
- .long _sys_sched_get_priority_max
- .long _sys_sched_get_priority_min /* 160 */
- .long _sys_sched_rr_get_interval
- .long _sys_nanosleep
- .long _sys_mremap
- .long _sys_setresuid /* setresuid16 */
- .long _sys_getresuid /* getresuid16 */ /* 165 */
- .long _sys_ni_syscall /* for vm86 */
- .long _sys_ni_syscall /* old "query_module" */
- .long _sys_ni_syscall /* sys_poll */
- .long _sys_ni_syscall /* old nfsservctl */
- .long _sys_setresgid /* setresgid16 */ /* 170 */
- .long _sys_getresgid /* getresgid16 */
- .long _sys_prctl
- .long _sys_rt_sigreturn
- .long _sys_rt_sigaction
- .long _sys_rt_sigprocmask /* 175 */
- .long _sys_rt_sigpending
- .long _sys_rt_sigtimedwait
- .long _sys_rt_sigqueueinfo
- .long _sys_rt_sigsuspend
- .long _sys_pread64 /* 180 */
- .long _sys_pwrite64
- .long _sys_lchown /* lchown16 */
- .long _sys_getcwd
- .long _sys_capget
- .long _sys_capset /* 185 */
- .long _sys_sigaltstack
- .long _sys_sendfile
- .long _sys_ni_syscall /* streams1 */
- .long _sys_ni_syscall /* streams2 */
- .long _sys_vfork /* 190 */
- .long _sys_getrlimit
- .long _sys_mmap_pgoff
- .long _sys_truncate64
- .long _sys_ftruncate64
- .long _sys_stat64 /* 195 */
- .long _sys_lstat64
- .long _sys_fstat64
- .long _sys_chown
- .long _sys_getuid
- .long _sys_getgid /* 200 */
- .long _sys_geteuid
- .long _sys_getegid
- .long _sys_setreuid
- .long _sys_setregid
- .long _sys_getgroups /* 205 */
- .long _sys_setgroups
- .long _sys_fchown
- .long _sys_setresuid
- .long _sys_getresuid
- .long _sys_setresgid /* 210 */
- .long _sys_getresgid
- .long _sys_lchown
- .long _sys_setuid
- .long _sys_setgid
- .long _sys_setfsuid /* 215 */
- .long _sys_setfsgid
- .long _sys_pivot_root
- .long _sys_mincore
- .long _sys_madvise
- .long _sys_getdents64 /* 220 */
- .long _sys_fcntl64
- .long _sys_ni_syscall /* reserved for TUX */
- .long _sys_ni_syscall
- .long _sys_gettid
- .long _sys_readahead /* 225 */
- .long _sys_setxattr
- .long _sys_lsetxattr
- .long _sys_fsetxattr
- .long _sys_getxattr
- .long _sys_lgetxattr /* 230 */
- .long _sys_fgetxattr
- .long _sys_listxattr
- .long _sys_llistxattr
- .long _sys_flistxattr
- .long _sys_removexattr /* 235 */
- .long _sys_lremovexattr
- .long _sys_fremovexattr
- .long _sys_tkill
- .long _sys_sendfile64
- .long _sys_futex /* 240 */
- .long _sys_sched_setaffinity
- .long _sys_sched_getaffinity
- .long _sys_ni_syscall /* sys_set_thread_area */
- .long _sys_ni_syscall /* sys_get_thread_area */
- .long _sys_io_setup /* 245 */
- .long _sys_io_destroy
- .long _sys_io_getevents
- .long _sys_io_submit
- .long _sys_io_cancel
- .long _sys_ni_syscall /* 250 */ /* sys_alloc_hugepages */
- .long _sys_ni_syscall /* sys_freec_hugepages */
- .long _sys_exit_group
- .long _sys_lookup_dcookie
- .long _sys_bfin_spinlock
- .long _sys_epoll_create /* 255 */
- .long _sys_epoll_ctl
- .long _sys_epoll_wait
- .long _sys_ni_syscall /* remap_file_pages */
- .long _sys_set_tid_address
- .long _sys_timer_create /* 260 */
- .long _sys_timer_settime
- .long _sys_timer_gettime
- .long _sys_timer_getoverrun
- .long _sys_timer_delete
- .long _sys_clock_settime /* 265 */
- .long _sys_clock_gettime
- .long _sys_clock_getres
- .long _sys_clock_nanosleep
- .long _sys_statfs64
- .long _sys_fstatfs64 /* 270 */
- .long _sys_tgkill
- .long _sys_utimes
- .long _sys_fadvise64_64
- .long _sys_ni_syscall /* vserver */
- .long _sys_mbind /* 275 */
- .long _sys_ni_syscall /* get_mempolicy */
- .long _sys_ni_syscall /* set_mempolicy */
- .long _sys_mq_open
- .long _sys_mq_unlink
- .long _sys_mq_timedsend /* 280 */
- .long _sys_mq_timedreceive
- .long _sys_mq_notify
- .long _sys_mq_getsetattr
- .long _sys_ni_syscall /* kexec_load */
- .long _sys_waitid /* 285 */
- .long _sys_add_key
- .long _sys_request_key
- .long _sys_keyctl
- .long _sys_ioprio_set
- .long _sys_ioprio_get /* 290 */
- .long _sys_inotify_init
- .long _sys_inotify_add_watch
- .long _sys_inotify_rm_watch
- .long _sys_ni_syscall /* migrate_pages */
- .long _sys_openat /* 295 */
- .long _sys_mkdirat
- .long _sys_mknodat
- .long _sys_fchownat
- .long _sys_futimesat
- .long _sys_fstatat64 /* 300 */
- .long _sys_unlinkat
- .long _sys_renameat
- .long _sys_linkat
- .long _sys_symlinkat
- .long _sys_readlinkat /* 305 */
- .long _sys_fchmodat
- .long _sys_faccessat
- .long _sys_pselect6
- .long _sys_ppoll
- .long _sys_unshare /* 310 */
- .long _sys_sram_alloc
- .long _sys_sram_free
- .long _sys_dma_memcpy
- .long _sys_accept
- .long _sys_bind /* 315 */
- .long _sys_connect
- .long _sys_getpeername
- .long _sys_getsockname
- .long _sys_getsockopt
- .long _sys_listen /* 320 */
- .long _sys_recv
- .long _sys_recvfrom
- .long _sys_recvmsg
- .long _sys_send
- .long _sys_sendmsg /* 325 */
- .long _sys_sendto
- .long _sys_setsockopt
- .long _sys_shutdown
- .long _sys_socket
- .long _sys_socketpair /* 330 */
- .long _sys_semctl
- .long _sys_semget
- .long _sys_semop
- .long _sys_msgctl
- .long _sys_msgget /* 335 */
- .long _sys_msgrcv
- .long _sys_msgsnd
- .long _sys_shmat
- .long _sys_shmctl
- .long _sys_shmdt /* 340 */
- .long _sys_shmget
- .long _sys_splice
- .long _sys_sync_file_range
- .long _sys_tee
- .long _sys_vmsplice /* 345 */
- .long _sys_epoll_pwait
- .long _sys_utimensat
- .long _sys_signalfd
- .long _sys_timerfd_create
- .long _sys_eventfd /* 350 */
- .long _sys_pread64
- .long _sys_pwrite64
- .long _sys_fadvise64
- .long _sys_set_robust_list
- .long _sys_get_robust_list /* 355 */
- .long _sys_fallocate
- .long _sys_semtimedop
- .long _sys_timerfd_settime
- .long _sys_timerfd_gettime
- .long _sys_signalfd4 /* 360 */
- .long _sys_eventfd2
- .long _sys_epoll_create1
- .long _sys_dup3
- .long _sys_pipe2
- .long _sys_inotify_init1 /* 365 */
- .long _sys_preadv
- .long _sys_pwritev
- .long _sys_rt_tgsigqueueinfo
- .long _sys_perf_event_open
- .long _sys_recvmmsg /* 370 */
- .long _sys_fanotify_init
- .long _sys_fanotify_mark
- .long _sys_prlimit64
- .long _sys_cacheflush
- .long _sys_name_to_handle_at /* 375 */
- .long _sys_open_by_handle_at
- .long _sys_clock_adjtime
- .long _sys_syncfs
- .long _sys_setns
- .long _sys_sendmmsg /* 380 */
- .long _sys_process_vm_readv
- .long _sys_process_vm_writev
- .long _sys_kcmp
- .long _sys_finit_module
- .long _sys_sched_setattr /* 385 */
- .long _sys_sched_getattr
- .long _sys_renameat2
- .long _sys_seccomp
- .long _sys_getrandom
- .long _sys_memfd_create /* 390 */
- .long _sys_bpf
- .long _sys_execveat
-
- .rept NR_syscalls-(.-_sys_call_table)/4
- .long _sys_ni_syscall
- .endr
-END(_sys_call_table)
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
deleted file mode 100644
index 31515f0146f9..000000000000
--- a/arch/blackfin/mach-common/head.S
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Common Blackfin startup code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/blackfin.h>
-#include <asm/thread_info.h>
-#include <asm/trace.h>
-#include <asm/asm-offsets.h>
-
-__INIT
-
-ENTRY(__init_clear_bss)
- r2 = r2 - r1;
- cc = r2 == 0;
- if cc jump .L_bss_done;
- r2 >>= 2;
- p1 = r1;
- p2 = r2;
- lsetup (1f, 1f) lc0 = p2;
-1: [p1++] = r0;
-.L_bss_done:
- rts;
-ENDPROC(__init_clear_bss)
-
-ENTRY(__start)
- /* R0: argument of command line string, passed from uboot, save it */
- R7 = R0;
-
- /* Enable Cycle Counter and Nesting Of Interrupts */
-#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
- R0 = SYSCFG_SNEN;
-#else
- R0 = SYSCFG_SNEN | SYSCFG_CCEN;
-#endif
- SYSCFG = R0;
-
- /* Optimization register tricks: keep a base value in the
- * reserved P registers so we use the load/store with an
- * offset syntax. R0 = [P5 + <constant>];
- * P5 - core MMR base
- * R6 - 0
- */
- r6 = 0;
- p5.l = 0;
- p5.h = hi(COREMMR_BASE);
-
- /* Zero out registers required by Blackfin ABI */
-
- /* Disable circular buffers */
- L0 = r6;
- L1 = r6;
- L2 = r6;
- L3 = r6;
-
- /* Disable hardware loops in case we were started by 'go' */
- LC0 = r6;
- LC1 = r6;
-
- /*
- * Clear ITEST_COMMAND and DTEST_COMMAND registers,
- * Leaving these as non-zero can confuse the emulator
- */
- [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
- [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
- CSYNC;
-
- trace_buffer_init(p0,r0);
-
- /* Turn off the icache */
- r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENICPLB_P);
- [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* Turn off the dcache */
- r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
- BITCLR (r1, ENDCPLB_P);
- [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
- SSYNC;
-
- /* in case of double faults, save a few things */
- p1.l = _initial_pda;
- p1.h = _initial_pda;
- r4 = RETX;
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- /* Only save these if we are storing them,
- * This happens here, since L1 gets clobbered
- * below
- */
- GET_PDA(p0, r0);
- r0 = [p0 + PDA_DF_RETX];
- r1 = [p0 + PDA_DF_DCPLB];
- r2 = [p0 + PDA_DF_ICPLB];
- r3 = [p0 + PDA_DF_SEQSTAT];
- [p1 + PDA_INIT_DF_RETX] = r0;
- [p1 + PDA_INIT_DF_DCPLB] = r1;
- [p1 + PDA_INIT_DF_ICPLB] = r2;
- [p1 + PDA_INIT_DF_SEQSTAT] = r3;
-#endif
- [p1 + PDA_INIT_RETX] = r4;
-
- /* Initialize stack pointer */
- sp.l = _init_thread_union + THREAD_SIZE;
- sp.h = _init_thread_union + THREAD_SIZE;
- fp = sp;
- usp = sp;
-
-#ifdef CONFIG_EARLY_PRINTK
- call _init_early_exception_vectors;
- r0 = (EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
- sti r0;
-#endif
-
- r0 = r6;
- /* Zero out all of the fun bss regions */
-#if L1_DATA_A_LENGTH > 0
- r1.l = __sbss_l1;
- r1.h = __sbss_l1;
- r2.l = __ebss_l1;
- r2.h = __ebss_l1;
- call __init_clear_bss
-#endif
-#if L1_DATA_B_LENGTH > 0
- r1.l = __sbss_b_l1;
- r1.h = __sbss_b_l1;
- r2.l = __ebss_b_l1;
- r2.h = __ebss_b_l1;
- call __init_clear_bss
-#endif
-#if L2_LENGTH > 0
- r1.l = __sbss_l2;
- r1.h = __sbss_l2;
- r2.l = __ebss_l2;
- r2.h = __ebss_l2;
- call __init_clear_bss
-#endif
- r1.l = ___bss_start;
- r1.h = ___bss_start;
- r2.l = ___bss_stop;
- r2.h = ___bss_stop;
- call __init_clear_bss
-
- /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
- call _bfin_relocate_l1_mem;
-
-#ifdef CONFIG_ROMKERNEL
- call _bfin_relocate_xip_data;
-#endif
-
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
- /* Only use on-chip scratch space for stack when absolutely required
- * to avoid Anomaly 05000227 ... we know the init_clocks() func only
- * uses L1 text and stack space and no other memory region.
- */
-# define KERNEL_CLOCK_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
- sp.l = lo(KERNEL_CLOCK_STACK);
- sp.h = hi(KERNEL_CLOCK_STACK);
- call _init_clocks;
- sp = usp; /* usp hasn't been touched, so restore from there */
-#endif
-
- /* This section keeps the processor in supervisor mode
- * during kernel boot. Switches to user mode at end of boot.
- * See page 3-9 of Hardware Reference manual for documentation.
- */
-
- /* EVT15 = _real_start */
-
- p1.l = _real_start;
- p1.h = _real_start;
- [p5 + (EVT15 - COREMMR_BASE)] = p1;
- csync;
-
-#ifdef CONFIG_EARLY_PRINTK
- r0 = (EVT_IVG15 | EVT_IVHW | EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU) (z);
-#else
- r0 = EVT_IVG15 (z);
-#endif
- sti r0;
-
- raise 15;
-#ifdef CONFIG_EARLY_PRINTK
- p0.l = _early_trap;
- p0.h = _early_trap;
-#else
- p0.l = .LWAIT_HERE;
- p0.h = .LWAIT_HERE;
-#endif
- reti = p0;
-#if ANOMALY_05000281
- nop; nop; nop;
-#endif
- rti;
-
-.LWAIT_HERE:
- jump .LWAIT_HERE;
-ENDPROC(__start)
-
-/* A little BF561 glue ... */
-#ifndef WDOG_CTL
-# define WDOG_CTL WDOGA_CTL
-#endif
-
-ENTRY(_real_start)
- /* Enable nested interrupts */
- [--sp] = reti;
- /* watchdog off for now */
- p0.l = lo(WDOG_CTL);
- p0.h = hi(WDOG_CTL);
- r0 = 0xAD6(z);
- w[p0] = r0;
- ssync;
- /* Pass the u-boot arguments to the global value command line */
- R0 = R7;
- call _cmdline_init;
-
- sp += -12 + 4; /* +4 is for reti loading above */
- call _init_pda
- sp += 12;
- jump.l _start_kernel;
-ENDPROC(_real_start)
-
-__FINIT
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
deleted file mode 100644
index 469ce7282dc8..000000000000
--- a/arch/blackfin/mach-common/interrupt.S
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * Interrupt Entries
- *
- * Copyright 2005-2009 Analog Devices Inc.
- * D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>
- * Kenneth Albanowski <kjahds@kjahds.com>
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/blackfin.h>
-#include <mach/irq.h>
-#include <linux/linkage.h>
-#include <asm/entry.h>
-#include <asm/asm-offsets.h>
-#include <asm/trace.h>
-#include <asm/traps.h>
-#include <asm/thread_info.h>
-
-#include <asm/context.S>
-
-.extern _ret_from_exception
-
-#ifdef CONFIG_I_ENTRY_L1
-.section .l1.text
-#else
-.text
-#endif
-
-.align 4 /* just in case */
-
-/* Common interrupt entry code. First we do CLI, then push
- * RETI, to keep interrupts disabled, but to allow this state to be changed
- * by local_bh_enable.
- * R0 contains the interrupt number, while R1 may contain the value of IPEND,
- * or garbage if IPEND won't be needed by the ISR. */
-__common_int_entry:
- [--sp] = fp;
- [--sp] = usp;
-
- [--sp] = i0;
- [--sp] = i1;
- [--sp] = i2;
- [--sp] = i3;
-
- [--sp] = m0;
- [--sp] = m1;
- [--sp] = m2;
- [--sp] = m3;
-
- [--sp] = l0;
- [--sp] = l1;
- [--sp] = l2;
- [--sp] = l3;
-
- [--sp] = b0;
- [--sp] = b1;
- [--sp] = b2;
- [--sp] = b3;
- [--sp] = a0.x;
- [--sp] = a0.w;
- [--sp] = a1.x;
- [--sp] = a1.w;
-
- [--sp] = LC0;
- [--sp] = LC1;
- [--sp] = LT0;
- [--sp] = LT1;
- [--sp] = LB0;
- [--sp] = LB1;
-
- [--sp] = ASTAT;
-
- [--sp] = r0; /* Skip reserved */
- [--sp] = RETS;
- r2 = RETI;
- [--sp] = r2;
- [--sp] = RETX;
- [--sp] = RETN;
- [--sp] = RETE;
- [--sp] = SEQSTAT;
- [--sp] = r1; /* IPEND - R1 may or may not be set up before jumping here. */
-
- /* Switch to other method of keeping interrupts disabled. */
-#ifdef CONFIG_DEBUG_HWERR
- r1 = 0x3f;
- sti r1;
-#else
- cli r1;
-#endif
-#ifdef CONFIG_TRACE_IRQFLAGS
- [--sp] = r0;
- sp += -12;
- call _trace_hardirqs_off;
- sp += 12;
- r0 = [sp++];
-#endif
- [--sp] = RETI; /* orig_pc */
- /* Clear all L registers. */
- r1 = 0 (x);
- l0 = r1;
- l1 = r1;
- l2 = r1;
- l3 = r1;
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- r1 = sp;
- SP += -12;
-#ifdef CONFIG_IPIPE
- call ___ipipe_grab_irq
- SP += 12;
- cc = r0 == 0;
- if cc jump .Lcommon_restore_context;
-#else /* CONFIG_IPIPE */
-
-#ifdef CONFIG_PREEMPT
- r7 = sp;
- r4.l = lo(ALIGN_PAGE_MASK);
- r4.h = hi(ALIGN_PAGE_MASK);
- r7 = r7 & r4;
- p5 = r7;
- r7 = [p5 + TI_PREEMPT]; /* get preempt count */
- r7 += 1; /* increment it */
- [p5 + TI_PREEMPT] = r7;
-#endif
- pseudo_long_call _do_irq, p2;
-
-#ifdef CONFIG_PREEMPT
- r7 += -1;
- [p5 + TI_PREEMPT] = r7; /* restore preempt count */
-#endif
-
- SP += 12;
-#endif /* CONFIG_IPIPE */
- pseudo_long_call _return_from_int, p2;
-.Lcommon_restore_context:
- RESTORE_CONTEXT
- rti;
-
-/* interrupt routine for ivhw - 5 */
-ENTRY(_evt_ivhw)
- /* In case a single action kicks off multiple memory transactions, (like
- * a cache line fetch, - this can cause multiple hardware errors, let's
- * catch them all. First - make sure all the actions are complete, and
- * the core sees the hardware errors.
- */
- SSYNC;
- SSYNC;
-
- SAVE_ALL_SYS
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
-
- ANOMALY_283_315_WORKAROUND(p5, r7)
-
- /* Handle all stacked hardware errors
- * To make sure we don't hang forever, only do it 10 times
- */
- R0 = 0;
- R2 = 10;
-1:
- P0.L = LO(ILAT);
- P0.H = HI(ILAT);
- R1 = [P0];
- CC = BITTST(R1, EVT_IVHW_P);
- IF ! CC JUMP 2f;
- /* OK a hardware error is pending - clear it */
- R1 = EVT_IVHW_P;
- [P0] = R1;
- R0 += 1;
- CC = R1 == R2;
- if CC JUMP 2f;
- JUMP 1b;
-2:
- # We are going to dump something out, so make sure we print IPEND properly
- p2.l = lo(IPEND);
- p2.h = hi(IPEND);
- r0 = [p2];
- [sp + PT_IPEND] = r0;
-
- /* set the EXCAUSE to HWERR for trap_c */
- r0 = [sp + PT_SEQSTAT];
- R1.L = LO(VEC_HWERR);
- R1.H = HI(VEC_HWERR);
- R0 = R0 | R1;
- [sp + PT_SEQSTAT] = R0;
-
- r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
- SP += -12;
- pseudo_long_call _trap_c, p5;
- SP += 12;
-
-#ifdef EBIU_ERRMST
- /* make sure EBIU_ERRMST is clear */
- p0.l = LO(EBIU_ERRMST);
- p0.h = HI(EBIU_ERRMST);
- r0.l = (CORE_ERROR | CORE_MERROR);
- w[p0] = r0.l;
-#endif
-
- pseudo_long_call _ret_from_exception, p2;
-
-.Lcommon_restore_all_sys:
- RESTORE_ALL_SYS
- rti;
-ENDPROC(_evt_ivhw)
-
-/* Interrupt routine for evt2 (NMI).
- * For inner circle type details, please see:
- * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:nmi
- */
-ENTRY(_evt_nmi)
-#ifndef CONFIG_NMI_WATCHDOG
-.weak _evt_nmi
-#else
- /* Not take account of CPLBs, this handler will not return */
- SAVE_ALL_SYS
- r0 = sp;
- r1 = retn;
- [sp + PT_PC] = r1;
- trace_buffer_save(p4,r5);
-
- ANOMALY_283_315_WORKAROUND(p4, r5)
-
- SP += -12;
- call _do_nmi;
- SP += 12;
-1:
- jump 1b;
-#endif
- rtn;
-ENDPROC(_evt_nmi)
-
-/* interrupt routine for core timer - 6 */
-ENTRY(_evt_timer)
- TIMER_INTERRUPT_ENTRY(EVT_IVTMR_P)
-
-/* interrupt routine for evt7 - 7 */
-ENTRY(_evt_evt7)
- INTERRUPT_ENTRY(EVT_IVG7_P)
-ENTRY(_evt_evt8)
- INTERRUPT_ENTRY(EVT_IVG8_P)
-ENTRY(_evt_evt9)
- INTERRUPT_ENTRY(EVT_IVG9_P)
-ENTRY(_evt_evt10)
- INTERRUPT_ENTRY(EVT_IVG10_P)
-ENTRY(_evt_evt11)
- INTERRUPT_ENTRY(EVT_IVG11_P)
-ENTRY(_evt_evt12)
- INTERRUPT_ENTRY(EVT_IVG12_P)
-ENTRY(_evt_evt13)
- INTERRUPT_ENTRY(EVT_IVG13_P)
-
-
- /* interrupt routine for system_call - 15 */
-ENTRY(_evt_system_call)
- SAVE_CONTEXT_SYSCALL
-#ifdef CONFIG_FRAME_POINTER
- fp = 0;
-#endif
- pseudo_long_call _system_call, p2;
- jump .Lcommon_restore_context;
-ENDPROC(_evt_system_call)
-
-#ifdef CONFIG_IPIPE
-/*
- * __ipipe_call_irqtail: lowers the current priority level to EVT15
- * before running a user-defined routine, then raises the priority
- * level to EVT14 to prepare the caller for a normal interrupt
- * return through RTI.
- *
- * We currently use this feature in two occasions:
- *
- * - before branching to __ipipe_irq_tail_hook as requested by a high
- * priority domain after the pipeline delivered an interrupt,
- * e.g. such as Xenomai, in order to start its rescheduling
- * procedure, since we may not switch tasks when IRQ levels are
- * nested on the Blackfin, so we have to fake an interrupt return
- * so that we may reschedule immediately.
- *
- * - before branching to __ipipe_sync_root(), in order to play any interrupt
- * pending for the root domain (i.e. the Linux kernel). This lowers
- * the core priority level enough so that Linux IRQ handlers may
- * never delay interrupts handled by high priority domains; we defer
- * those handlers until this point instead. This is a substitute
- * to using a threaded interrupt model for the Linux kernel.
- *
- * r0: address of user-defined routine
- * context: caller must have preempted EVT15, hw interrupts must be off.
- */
-ENTRY(___ipipe_call_irqtail)
- p0 = r0;
- r0.l = 1f;
- r0.h = 1f;
- reti = r0;
- rti;
-1:
- [--sp] = rets;
- [--sp] = ( r7:4, p5:3 );
- sp += -12;
- call (p0);
- sp += 12;
- ( r7:4, p5:3 ) = [sp++];
- rets = [sp++];
-
-#ifdef CONFIG_DEBUG_HWERR
- /* enable irq14 & hwerr interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | EVT_IVHW | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#else
- /* Only enable irq14 interrupt, until we transition to _evt_evt14 */
- r0 = (EVT_IVG14 | \
- EVT_IRPTEN | EVT_EVX | EVT_NMI | EVT_RST | EVT_EMU);
-#endif
- sti r0;
- raise 14; /* Branches to _evt_evt14 */
-2:
- jump 2b; /* Likely paranoid. */
-ENDPROC(___ipipe_call_irqtail)
-
-#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
deleted file mode 100644
index e81a5b7dabdc..000000000000
--- a/arch/blackfin/mach-common/ints-priority.c
+++ /dev/null
@@ -1,1366 +0,0 @@
-/*
- * Set up the interrupt priorities
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * 2003 Bas Vermeulen <bas@buyways.nl>
- * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * 1999 D. Jeff Dionne <jeff@uclinux.org>
- * 1996 Roman Zippel
- *
- * Licensed under the GPL-2
- */
-
-#include <linux/module.h>
-#include <linux/kernel_stat.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/syscore_ops.h>
-#include <asm/delay.h>
-#ifdef CONFIG_IPIPE
-#include <linux/ipipe.h>
-#endif
-#include <asm/traps.h>
-#include <asm/blackfin.h>
-#include <asm/irq_handler.h>
-#include <asm/dpmc.h>
-#include <asm/traps.h>
-#include <asm/gpio.h>
-
-/*
- * NOTES:
- * - we have separated the physical Hardware interrupt from the
- * levels that the LINUX kernel sees (see the description in irq.h)
- * -
- */
-
-#ifndef CONFIG_SMP
-/* Initialize this to an actual value to force it into the .data
- * section so that we know it is properly initialized at entry into
- * the kernel but before bss is initialized to zero (which is where
- * it would live otherwise). The 0x1f magic represents the IRQs we
- * cannot actually mask out in hardware.
- */
-unsigned long bfin_irq_flags = 0x1f;
-EXPORT_SYMBOL(bfin_irq_flags);
-#endif
-
-#ifdef CONFIG_PM
-unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
-unsigned vr_wakeup;
-#endif
-
-#ifndef SEC_GCTL
-static struct ivgx {
- /* irq number for request_irq, available in mach-bf5xx/irq.h */
- unsigned int irqno;
- /* corresponding bit in the SIC_ISR register */
- unsigned int isrflag;
-} ivg_table[NR_PERI_INTS];
-
-static struct ivg_slice {
- /* position of first irq in ivg_table for given ivg */
- struct ivgx *ifirst;
- struct ivgx *istop;
-} ivg7_13[IVG13 - IVG7 + 1];
-
-
-/*
- * Search SIC_IAR and fill tables with the irqvalues
- * and their positions in the SIC_ISR register.
- */
-static void __init search_IAR(void)
-{
- unsigned ivg, irq_pos = 0;
- for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
- int irqN;
-
- ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
-
- for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
- int irqn;
- u32 iar =
- bfin_read32((unsigned long *)SIC_IAR0 +
-#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
- defined(CONFIG_BF538) || defined(CONFIG_BF539)
- ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
-#else
- (irqN >> 3)
-#endif
- );
- for (irqn = irqN; irqn < irqN + 4; ++irqn) {
- int iar_shift = (irqn & 7) * 4;
- if (ivg == (0xf & (iar >> iar_shift))) {
- ivg_table[irq_pos].irqno = IVG7 + irqn;
- ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
- ivg7_13[ivg].istop++;
- irq_pos++;
- }
- }
- }
- }
-}
-#endif
-
-/*
- * This is for core internal IRQs
- */
-void bfin_ack_noop(struct irq_data *d)
-{
- /* Dummy function. */
-}
-
-static void bfin_core_mask_irq(struct irq_data *d)
-{
- bfin_irq_flags &= ~(1 << d->irq);
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
-}
-
-static void bfin_core_unmask_irq(struct irq_data *d)
-{
- bfin_irq_flags |= 1 << d->irq;
- /*
- * If interrupts are enabled, IMASK must contain the same value
- * as bfin_irq_flags. Make sure that invariant holds. If interrupts
- * are currently disabled we need not do anything; one of the
- * callers will take care of setting IMASK to the proper value
- * when reenabling interrupts.
- * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
- * what we need.
- */
- if (!hard_irqs_disabled())
- hard_local_irq_enable();
- return;
-}
-
-#ifndef SEC_GCTL
-void bfin_internal_mask_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
- bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
- ~(1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
- ~(1 << BFIN_SYSIRQ(irq)));
-#endif /* end of SIC_IMASK0 */
- hard_local_irq_restore(flags);
-}
-
-static void bfin_internal_mask_irq_chip(struct irq_data *d)
-{
- bfin_internal_mask_irq(d->irq);
-}
-
-#ifdef CONFIG_SMP
-void bfin_internal_unmask_irq_affinity(unsigned int irq,
- const struct cpumask *affinity)
-#else
-void bfin_internal_unmask_irq(unsigned int irq)
-#endif
-{
- unsigned long flags = hard_local_irq_save();
-
-#ifdef SIC_IMASK0
- unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
- unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(0, affinity))
-# endif
- bfin_write_SIC_IMASK(mask_bank,
- bfin_read_SIC_IMASK(mask_bank) |
- (1 << mask_bit));
-# ifdef CONFIG_SMP
- if (cpumask_test_cpu(1, affinity))
- bfin_write_SICB_IMASK(mask_bank,
- bfin_read_SICB_IMASK(mask_bank) |
- (1 << mask_bit));
-# endif
-#else
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
- (1 << BFIN_SYSIRQ(irq)));
-#endif
- hard_local_irq_restore(flags);
-}
-
-#ifdef CONFIG_SMP
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq_affinity(d->irq,
- irq_data_get_affinity_mask(d));
-}
-
-static int bfin_internal_set_affinity(struct irq_data *d,
- const struct cpumask *mask, bool force)
-{
- bfin_internal_mask_irq(d->irq);
- bfin_internal_unmask_irq_affinity(d->irq, mask);
-
- return 0;
-}
-#else
-static void bfin_internal_unmask_irq_chip(struct irq_data *d)
-{
- bfin_internal_unmask_irq(d->irq);
-}
-#endif
-
-#if defined(CONFIG_PM)
-int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- u32 bank, bit, wakeup = 0;
- unsigned long flags;
- bank = BFIN_SYSIRQ(irq) / 32;
- bit = BFIN_SYSIRQ(irq) % 32;
-
- switch (irq) {
-#ifdef IRQ_RTC
- case IRQ_RTC:
- wakeup |= WAKE;
- break;
-#endif
-#ifdef IRQ_CAN0_RX
- case IRQ_CAN0_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_CAN1_RX
- case IRQ_CAN1_RX:
- wakeup |= CANWE;
- break;
-#endif
-#ifdef IRQ_USB_INT0
- case IRQ_USB_INT0:
- wakeup |= USBWE;
- break;
-#endif
-#ifdef CONFIG_BF54x
- case IRQ_CNT:
- wakeup |= ROTWE;
- break;
-#endif
- default:
- break;
- }
-
- flags = hard_local_irq_save();
-
- if (state) {
- bfin_sic_iwr[bank] |= (1 << bit);
- vr_wakeup |= wakeup;
-
- } else {
- bfin_sic_iwr[bank] &= ~(1 << bit);
- vr_wakeup &= ~wakeup;
- }
-
- hard_local_irq_restore(flags);
-
- return 0;
-}
-
-static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
-{
- return bfin_internal_set_wake(d->irq, state);
-}
-#else
-inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
-{
- return 0;
-}
-# define bfin_internal_set_wake_chip NULL
-#endif
-
-#else /* SEC_GCTL */
-static void bfin_sec_preflow_handler(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_mask_ack_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write_SEC_SCI(0, SEC_CSID, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_unmask_irq(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_write32(SEC_END, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl |= SEC_SCTL_SRC_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_ssi(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
- bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
- reg_sctl |= SEC_SCTL_FAULT_EN;
- else
- reg_sctl |= SEC_SCTL_INT_EN;
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable_sci(unsigned int sid)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
-
- reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
- bfin_write_SEC_SCTL(sid, reg_sctl);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_enable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_enable_sci(sid);
- bfin_sec_enable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_disable(struct irq_data *d)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(d->irq);
-
- bfin_sec_disable_sci(sid);
- bfin_sec_disable_ssi(sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
-{
- unsigned long flags = hard_local_irq_save();
- uint32_t reg_sctl;
- int i;
-
- bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
-
- for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
- reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
- reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
- bfin_write_SEC_SCTL(i, reg_sctl);
- }
-
- hard_local_irq_restore(flags);
-}
-
-void bfin_sec_raise_irq(unsigned int irq)
-{
- unsigned long flags = hard_local_irq_save();
- unsigned int sid = BFIN_SYSIRQ(irq);
-
- bfin_write32(SEC_RAISE, sid);
-
- hard_local_irq_restore(flags);
-}
-
-static void init_software_driven_irq(void)
-{
- bfin_sec_set_ssi_coreid(34, 0);
- bfin_sec_set_ssi_coreid(35, 1);
-
- bfin_sec_enable_sci(35);
- bfin_sec_enable_ssi(35);
- bfin_sec_set_ssi_coreid(36, 0);
- bfin_sec_set_ssi_coreid(37, 1);
- bfin_sec_enable_sci(37);
- bfin_sec_enable_ssi(37);
-}
-
-void handle_sec_sfi_fault(uint32_t gstat)
-{
-
-}
-
-void handle_sec_sci_fault(uint32_t gstat)
-{
- uint32_t core_id;
- uint32_t cstat;
-
- core_id = gstat & SEC_GSTAT_SCI;
- cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
- if (cstat & SEC_CSTAT_ERR) {
- switch (cstat & SEC_CSTAT_ERRC) {
- case SEC_CSTAT_ACKERR:
- printk(KERN_DEBUG "sec ack err\n");
- break;
- default:
- printk(KERN_DEBUG "sec sci unknown err\n");
- }
- }
-
-}
-
-void handle_sec_ssi_fault(uint32_t gstat)
-{
- uint32_t sid;
- uint32_t sstat;
-
- sid = gstat & SEC_GSTAT_SID;
- sstat = bfin_read_SEC_SSTAT(sid);
-
-}
-
-void handle_sec_fault(uint32_t sec_gstat)
-{
- if (sec_gstat & SEC_GSTAT_ERR) {
-
- switch (sec_gstat & SEC_GSTAT_ERRC) {
- case 0:
- handle_sec_sfi_fault(sec_gstat);
- break;
- case SEC_GSTAT_SCIERR:
- handle_sec_sci_fault(sec_gstat);
- break;
- case SEC_GSTAT_SSIERR:
- handle_sec_ssi_fault(sec_gstat);
- break;
- }
-
-
- }
-}
-
-static struct irqaction bfin_fault_irq = {
- .name = "Blackfin fault",
-};
-
-static irqreturn_t bfin_fault_routine(int irq, void *data)
-{
- struct pt_regs *fp = get_irq_regs();
-
- switch (irq) {
- case IRQ_C0_DBL_FAULT:
- double_fault_c(fp);
- break;
- case IRQ_C0_HW_ERR:
- dump_bfin_process(fp);
- dump_bfin_mem(fp);
- show_regs(fp);
- printk(KERN_NOTICE "Kernel Stack\n");
- show_stack(current, NULL);
- print_modules();
- panic("Core 0 hardware error");
- break;
- case IRQ_C0_NMI_L1_PARITY_ERR:
- panic("Core 0 NMI L1 parity error");
- break;
- case IRQ_SEC_ERR:
- pr_err("SEC error\n");
- handle_sec_fault(bfin_read32(SEC_GSTAT));
- break;
- default:
- panic("Unknown fault %d", irq);
- }
-
- return IRQ_HANDLED;
-}
-#endif /* SEC_GCTL */
-
-static struct irq_chip bfin_core_irqchip = {
- .name = "CORE",
- .irq_mask = bfin_core_mask_irq,
- .irq_unmask = bfin_core_unmask_irq,
-};
-
-#ifndef SEC_GCTL
-static struct irq_chip bfin_internal_irqchip = {
- .name = "INTN",
- .irq_mask = bfin_internal_mask_irq_chip,
- .irq_unmask = bfin_internal_unmask_irq_chip,
- .irq_disable = bfin_internal_mask_irq_chip,
- .irq_enable = bfin_internal_unmask_irq_chip,
-#ifdef CONFIG_SMP
- .irq_set_affinity = bfin_internal_set_affinity,
-#endif
- .irq_set_wake = bfin_internal_set_wake_chip,
-};
-#else
-static struct irq_chip bfin_sec_irqchip = {
- .name = "SEC",
- .irq_mask_ack = bfin_sec_mask_ack_irq,
- .irq_mask = bfin_sec_mask_ack_irq,
- .irq_unmask = bfin_sec_unmask_irq,
- .irq_eoi = bfin_sec_unmask_irq,
- .irq_disable = bfin_sec_disable,
- .irq_enable = bfin_sec_enable,
-};
-#endif
-
-void bfin_handle_irq(unsigned irq)
-{
-#ifdef CONFIG_IPIPE
- struct pt_regs regs; /* Contents not used. */
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, &regs);
- ipipe_trace_irq_exit(irq);
-#else /* !CONFIG_IPIPE */
- generic_handle_irq(irq);
-#endif /* !CONFIG_IPIPE */
-}
-
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-static int mac_stat_int_mask;
-
-static void bfin_mac_status_ack_irq(unsigned int irq)
-{
- switch (irq) {
- case IRQ_MAC_MMCINT:
- bfin_write_EMAC_MMC_TIRQS(
- bfin_read_EMAC_MMC_TIRQE() &
- bfin_read_EMAC_MMC_TIRQS());
- bfin_write_EMAC_MMC_RIRQS(
- bfin_read_EMAC_MMC_RIRQE() &
- bfin_read_EMAC_MMC_RIRQS());
- break;
- case IRQ_MAC_RXFSINT:
- bfin_write_EMAC_RX_STKY(
- bfin_read_EMAC_RX_IRQE() &
- bfin_read_EMAC_RX_STKY());
- break;
- case IRQ_MAC_TXFSINT:
- bfin_write_EMAC_TX_STKY(
- bfin_read_EMAC_TX_IRQE() &
- bfin_read_EMAC_TX_STKY());
- break;
- case IRQ_MAC_WAKEDET:
- bfin_write_EMAC_WKUP_CTL(
- bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
- break;
- default:
- /* These bits are W1C */
- bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
- break;
- }
-}
-
-static void bfin_mac_status_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
- mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_mask_irq(IRQ_MAC_ERROR);
-#endif
- bfin_mac_status_ack_irq(irq);
-}
-
-static void bfin_mac_status_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-
-#ifdef BF537_FAMILY
- switch (irq) {
- case IRQ_MAC_PHYINT:
- bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
- break;
- default:
- break;
- }
-#else
- if (!mac_stat_int_mask)
- bfin_internal_unmask_irq(IRQ_MAC_ERROR);
-#endif
- mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
-}
-
-#ifdef CONFIG_PM
-int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
-{
-#ifdef BF537_FAMILY
- return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
-#else
- return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
-#endif
-}
-#else
-# define bfin_mac_status_set_wake NULL
-#endif
-
-static struct irq_chip bfin_mac_status_irqchip = {
- .name = "MACST",
- .irq_mask = bfin_mac_status_mask_irq,
- .irq_unmask = bfin_mac_status_unmask_irq,
- .irq_set_wake = bfin_mac_status_set_wake,
-};
-
-void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
-{
- int i, irq = 0;
- u32 status = bfin_read_EMAC_SYSTAT();
-
- for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
- if (status & (1L << i)) {
- irq = IRQ_MAC_PHYINT + i;
- break;
- }
-
- if (irq) {
- if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
- bfin_handle_irq(irq);
- } else {
- bfin_mac_status_ack_irq(irq);
- pr_debug("IRQ %d:"
- " MASKED MAC ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- printk(KERN_ERR
- "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
- " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
- "(EMAC_SYSTAT=0x%X)\n",
- __func__, __FILE__, __LINE__, status);
-}
-#endif
-
-static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
-{
-#ifdef CONFIG_IPIPE
- handle = handle_level_irq;
-#endif
- irq_set_handler_locked(d, handle);
-}
-
-#ifdef CONFIG_GPIO_ADI
-
-static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
-
-static void bfin_gpio_ack_irq(struct irq_data *d)
-{
- /* AFAIK ack_irq in case mask_ack is provided
- * get's only called for edge sense irqs
- */
- set_gpio_data(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_mask_ack_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- u32 gpionr = irq_to_gpio(irq);
-
- if (!irqd_is_level_type(d))
- set_gpio_data(gpionr, 0);
-
- set_gpio_maska(gpionr, 0);
-}
-
-static void bfin_gpio_mask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 0);
-}
-
-static void bfin_gpio_unmask_irq(struct irq_data *d)
-{
- set_gpio_maska(irq_to_gpio(d->irq), 1);
-}
-
-static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- bfin_gpio_unmask_irq(d);
-
- return 0;
-}
-
-static void bfin_gpio_irq_shutdown(struct irq_data *d)
-{
- u32 gpionr = irq_to_gpio(d->irq);
-
- bfin_gpio_mask_irq(d);
- __clear_bit(gpionr, gpio_enabled);
- bfin_gpio_irq_free(gpionr);
-}
-
-static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
-{
- unsigned int irq = d->irq;
- int ret;
- char buf[16];
- u32 gpionr = irq_to_gpio(irq);
-
- if (type == IRQ_TYPE_PROBE) {
- /* only probe unenabled GPIO interrupt lines */
- if (test_bit(gpionr, gpio_enabled))
- return 0;
- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
- IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-
- snprintf(buf, 16, "gpio-irq%d", irq);
- ret = bfin_gpio_irq_request(gpionr, buf);
- if (ret)
- return ret;
-
- if (__test_and_set_bit(gpionr, gpio_enabled))
- bfin_gpio_irq_prepare(gpionr);
-
- } else {
- __clear_bit(gpionr, gpio_enabled);
- return 0;
- }
-
- set_gpio_inen(gpionr, 0);
- set_gpio_dir(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- set_gpio_both(gpionr, 1);
- else
- set_gpio_both(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
- set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
- else
- set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- set_gpio_edge(gpionr, 1);
- set_gpio_inen(gpionr, 1);
- set_gpio_data(gpionr, 0);
-
- } else {
- set_gpio_edge(gpionr, 0);
- set_gpio_inen(gpionr, 1);
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- bfin_set_irq_handler(d, handle_edge_irq);
- else
- bfin_set_irq_handler(d, handle_level_irq);
-
- return 0;
-}
-
-static void bfin_demux_gpio_block(unsigned int irq)
-{
- unsigned int gpio, mask;
-
- gpio = irq_to_gpio(irq);
- mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
-
- while (mask) {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- }
-}
-
-void bfin_demux_gpio_irq(struct irq_desc *desc)
-{
- unsigned int inta_irq = irq_desc_get_irq(desc);
- unsigned int irq;
-
- switch (inta_irq) {
-#if defined(BF537_FAMILY)
- case IRQ_PF_INTA_PG_INTA:
- bfin_demux_gpio_block(IRQ_PF0);
- irq = IRQ_PG0;
- break;
- case IRQ_PH_INTA_MAC_RX:
- irq = IRQ_PH0;
- break;
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PORTG_INTA:
- irq = IRQ_PG0;
- break;
- case IRQ_PORTH_INTA:
- irq = IRQ_PH0;
- break;
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PROG1_INTA:
- irq = IRQ_PF16;
- break;
- case IRQ_PROG2_INTA:
- irq = IRQ_PF32;
- break;
-#endif
- default:
- BUG();
- return;
- }
-
- bfin_demux_gpio_block(irq);
-}
-
-#ifdef CONFIG_PM
-
-static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
-{
- return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
-}
-
-#else
-
-# define bfin_gpio_set_wake NULL
-
-#endif
-
-static struct irq_chip bfin_gpio_irqchip = {
- .name = "GPIO",
- .irq_ack = bfin_gpio_ack_irq,
- .irq_mask = bfin_gpio_mask_irq,
- .irq_mask_ack = bfin_gpio_mask_ack_irq,
- .irq_unmask = bfin_gpio_unmask_irq,
- .irq_disable = bfin_gpio_mask_irq,
- .irq_enable = bfin_gpio_unmask_irq,
- .irq_set_type = bfin_gpio_irq_type,
- .irq_startup = bfin_gpio_irq_startup,
- .irq_shutdown = bfin_gpio_irq_shutdown,
- .irq_set_wake = bfin_gpio_set_wake,
-};
-
-#endif
-
-#ifdef CONFIG_PM
-
-#ifdef SEC_GCTL
-static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
-
-static int sec_suspend(void)
-{
- u32 bank;
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
- return 0;
-}
-
-static void sec_resume(void)
-{
- u32 bank;
-
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
- bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
-}
-
-static struct syscore_ops sec_pm_syscore_ops = {
- .suspend = sec_suspend,
- .resume = sec_resume,
-};
-#endif
-
-#endif
-
-void init_exception_vectors(void)
-{
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- bfin_write_EVT2(evt_nmi);
- bfin_write_EVT3(trap);
- bfin_write_EVT5(evt_ivhw);
- bfin_write_EVT6(evt_timer);
- bfin_write_EVT7(evt_evt7);
- bfin_write_EVT8(evt_evt8);
- bfin_write_EVT9(evt_evt9);
- bfin_write_EVT10(evt_evt10);
- bfin_write_EVT11(evt_evt11);
- bfin_write_EVT12(evt_evt12);
- bfin_write_EVT13(evt_evt13);
- bfin_write_EVT14(evt_evt14);
- bfin_write_EVT15(evt_system_call);
- CSYNC();
-}
-
-#ifndef SEC_GCTL
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
-#ifdef SIC_IMASK0
- bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
-# ifdef SIC_IMASK2
- bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
-# endif
-# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
-# endif
-#else
- bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
-#endif
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR)
- irq_set_chip(irq, &bfin_core_irqchip);
- else
- irq_set_chip(irq, &bfin_internal_irqchip);
-
- switch (irq) {
-#if !BFIN_GPIO_PINT
-#if defined(BF537_FAMILY)
- case IRQ_PH_INTA_MAC_RX:
- case IRQ_PF_INTA_PG_INTA:
-#elif defined(BF533_FAMILY)
- case IRQ_PROG_INTA:
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
- case IRQ_PORTF_INTA:
- case IRQ_PORTG_INTA:
- case IRQ_PORTH_INTA:
-#elif defined(CONFIG_BF561)
- case IRQ_PROG0_INTA:
- case IRQ_PROG1_INTA:
- case IRQ_PROG2_INTA:
-#elif defined(BF538_FAMILY)
- case IRQ_PORTF_INTA:
-#endif
- irq_set_chained_handler(irq, bfin_demux_gpio_irq);
- break;
-#endif
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- case IRQ_MAC_ERROR:
- irq_set_chained_handler(irq,
- bfin_demux_mac_status_irq);
- break;
-#endif
-#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
- case IRQ_SUPPLE_0:
- case IRQ_SUPPLE_1:
- irq_set_handler(irq, handle_percpu_irq);
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_CORETMR
- case IRQ_CORETMR:
-# ifdef CONFIG_SMP
- irq_set_handler(irq, handle_percpu_irq);
-# else
- irq_set_handler(irq, handle_simple_irq);
-# endif
- break;
-#endif
-
-#ifdef CONFIG_TICKSOURCE_GPTMR0
- case IRQ_TIMER0:
- irq_set_handler(irq, handle_simple_irq);
- break;
-#endif
-
- default:
-#ifdef CONFIG_IPIPE
- irq_set_handler(irq, handle_level_irq);
-#else
- irq_set_handler(irq, handle_simple_irq);
-#endif
- break;
- }
- }
-
- init_mach_irq();
-
-#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
- irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
- handle_level_irq);
-#endif
- /* if configured as edge, then will be changed to do_edge_IRQ */
-#ifdef CONFIG_GPIO_ADI
- for (irq = GPIO_IRQ_BASE;
- irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
- irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
- handle_level_irq);
-#endif
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
- /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
- * local_irq_enable()
- */
- program_IAR();
- /* Therefore it's better to setup IARs before interrupts enabled */
- search_IAR();
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- /* This implicitly covers ANOMALY_05000171
- * Boot-ROM code modifies SICA_IWRx wakeup registers
- */
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
- struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
- unsigned long sic_status[3];
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-#ifdef SIC_ISR
- sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-#else
- if (smp_processor_id()) {
-# ifdef SICB_ISR0
- /* This will be optimized out in UP mode. */
- sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
- sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
-# endif
- } else {
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
- }
-#endif
-#ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-#endif
-
- for (;; ivg++) {
- if (ivg >= ivg_stop)
- return -1;
-#ifdef SIC_ISR
- if (sic_status[0] & ivg->isrflag)
-#else
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
-#endif
- return ivg->irqno;
- }
-}
-
-#else /* SEC_GCTL */
-
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
-
- bfin_write_SEC_GCTL(SEC_GCTL_RESET);
-
- local_irq_disable();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR) {
- irq_set_chip_and_handler(irq, &bfin_core_irqchip,
- handle_simple_irq);
-#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
- if (irq == IRQ_CORETMR)
- irq_set_handler(irq, handle_percpu_irq);
-#endif
- } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
- irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
- handle_percpu_irq);
- } else {
- irq_set_chip(irq, &bfin_sec_irqchip);
- irq_set_handler(irq, handle_fasteoi_irq);
- __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
- }
- }
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
-
- bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
-
- /* Enable interrupts IVG7-15 */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
- bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
- bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
- udelay(100);
- bfin_write_SEC_GCTL(SEC_GCTL_EN);
- bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
- bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-
- init_software_driven_irq();
-
-#ifdef CONFIG_PM
- register_syscore_ops(&sec_pm_syscore_ops);
-#endif
-
- bfin_fault_irq.handler = bfin_fault_routine;
-#ifdef CONFIG_L1_PARITY_CHECK
- setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
-#endif
- setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
- setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
-
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-static int vec_to_irq(int vec)
-{
- if (likely(vec == EVT_IVTMR_P))
- return IRQ_CORETMR;
-
- return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
-}
-#endif /* SEC_GCTL */
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-void do_irq(int vec, struct pt_regs *fp)
-{
- int irq = vec_to_irq(vec);
- if (irq == -1)
- return;
- asm_do_IRQ(irq, fp);
-}
-
-#ifdef CONFIG_IPIPE
-
-int __ipipe_get_irq_priority(unsigned irq)
-{
- int ient, prio;
-
- if (irq <= IRQ_CORETMR)
- return irq;
-
-#ifdef SEC_GCTL
- if (irq >= BFIN_IRQ(0))
- return IVG11;
-#else
- for (ient = 0; ient < NR_PERI_INTS; ient++) {
- struct ivgx *ivg = ivg_table + ient;
- if (ivg->irqno == irq) {
- for (prio = 0; prio <= IVG13-IVG7; prio++) {
- if (ivg7_13[prio].ifirst <= ivg &&
- ivg7_13[prio].istop > ivg)
- return IVG7 + prio;
- }
- }
- }
-#endif
-
- return IVG15;
-}
-
-/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
-{
- struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
- struct ipipe_domain *this_domain = __ipipe_current_domain;
- int irq, s = 0;
-
- irq = vec_to_irq(vec);
- if (irq == -1)
- return 0;
-
- if (irq == IRQ_SYSTMR) {
-#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
- bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
-#endif
- /* This is basically what we need from the register frame. */
- __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend);
- __this_cpu_write(__ipipe_tick_regs.pc, regs->pc);
- if (this_domain != ipipe_root_domain)
- __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10);
- else
- __this_cpu_or(__ipipe_tick_regs.ipend, 0x10);
- }
-
- /*
- * We don't want Linux interrupt handlers to run at the
- * current core priority level (i.e. < EVT15), since this
- * might delay other interrupts handled by a high priority
- * domain. Here is what we do instead:
- *
- * - we raise the SYNCDEFER bit to prevent
- * __ipipe_handle_irq() to sync the pipeline for the root
- * stage for the incoming interrupt. Upon return, that IRQ is
- * pending in the interrupt log.
- *
- * - we raise the TIF_IRQ_SYNC bit for the current thread, so
- * that _schedule_and_signal_from_int will eventually sync the
- * pipeline from EVT15.
- */
- if (this_domain == ipipe_root_domain) {
- s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- barrier();
- }
-
- ipipe_trace_irq_entry(irq);
- __ipipe_handle_irq(irq, regs);
- ipipe_trace_irq_exit(irq);
-
- if (user_mode(regs) &&
- !ipipe_test_foreign_stack() &&
- (current->ipipe_flags & PF_EVTRET) != 0) {
- /*
- * Testing for user_regs() does NOT fully eliminate
- * foreign stack contexts, because of the forged
- * interrupt returns we do through
- * __ipipe_call_irqtail. In that case, we might have
- * preempted a foreign stack context in a high
- * priority domain, with a single interrupt level now
- * pending after the irqtail unwinding is done. In
- * which case user_mode() is now true, and the event
- * gets dispatched spuriously.
- */
- current->ipipe_flags &= ~PF_EVTRET;
- __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
- }
-
- if (this_domain == ipipe_root_domain) {
- set_thread_flag(TIF_IRQ_SYNC);
- if (!s) {
- __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
- return !test_bit(IPIPE_STALL_FLAG, &p->status);
- }
- }
-
- return 0;
-}
-
-#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
deleted file mode 100644
index f57b5fe5355e..000000000000
--- a/arch/blackfin/mach-common/pm.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Blackfin power management
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2
- * based on arm/mach-omap/pm.c
- * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
- */
-
-#include <linux/suspend.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-
-#include <asm/cplb.h>
-#include <asm/dma.h>
-#include <asm/dpmc.h>
-#include <asm/pm.h>
-#include <asm/gpio.h>
-
-#ifdef CONFIG_BF60x
-struct bfin_cpu_pm_fns *bfin_cpu_pm;
-#endif
-
-void bfin_pm_suspend_standby_enter(void)
-{
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_setup();
-#endif
-
-#ifdef CONFIG_BF60x
- bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
-#else
-# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
- sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# else
- sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
-# endif
-#endif
-
-#if !BFIN_GPIO_PINT
- bfin_pm_standby_restore();
-#endif
-
-#ifndef CONFIG_BF60x
-#ifdef SIC_IWR0
- bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-# ifdef SIC_IWR1
- /* BF52x system reset does not properly reset SIC_IWR1 which
- * will screw up the bootrom as it relies on MDMA0/1 waking it
- * up from IDLE instructions. See this report for more info:
- * http://blackfin.uclinux.org/gf/tracker/4323
- */
- if (ANOMALY_05000435)
- bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
- else
- bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-# endif
-# ifdef SIC_IWR2
- bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
-# endif
-#else
- bfin_write_SIC_IWR(IWR_DISABLE_ALL);
-#endif
-
-#endif
-}
-
-int bf53x_suspend_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
- L1_CODE_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
- (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
- dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
- (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
- memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
- L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
- L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-int bf53x_resume_l1_mem(unsigned char *memptr)
-{
- dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
- L1_DATA_A_LENGTH);
- dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
- memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
- L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
-
- return 0;
-}
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-# ifdef CONFIG_BF60x
-__attribute__((l1_text))
-# endif
-static void flushinv_all_dcache(void)
-{
- register u32 way, bank, subbank, set;
- register u32 status, addr;
- u32 dmem_ctl = bfin_read_DMEM_CONTROL();
-
- for (bank = 0; bank < 2; ++bank) {
- if (!(dmem_ctl & (1 << (DMC1_P - bank))))
- continue;
-
- for (way = 0; way < 2; ++way)
- for (subbank = 0; subbank < 4; ++subbank)
- for (set = 0; set < 64; ++set) {
-
- bfin_write_DTEST_COMMAND(
- way << 26 |
- bank << 23 |
- subbank << 16 |
- set << 5
- );
- CSYNC();
- status = bfin_read_DTEST_DATA0();
-
- /* only worry about valid/dirty entries */
- if ((status & 0x3) != 0x3)
- continue;
-
-
- /* construct the address using the tag */
- addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
-
- /* flush it */
- __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
- }
- }
-}
-#endif
-
-int bfin_pm_suspend_mem_enter(void)
-{
- int ret;
-#ifndef CONFIG_BF60x
- int wakeup;
-#endif
-
- unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
- + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
- GFP_ATOMIC);
-
- if (memptr == NULL) {
- panic("bf53x_suspend_l1_mem malloc failed");
- return -ENOMEM;
- }
-
-#ifndef CONFIG_BF60x
- wakeup = bfin_read_VR_CTL() & ~FREQ;
- wakeup |= SCKELOW;
-
-#ifdef CONFIG_PM_BFIN_WAKE_PH6
- wakeup |= PHYWE;
-#endif
-#ifdef CONFIG_PM_BFIN_WAKE_GP
- wakeup |= GPWE;
-#endif
-#endif
-
- ret = blackfin_dma_suspend();
-
- if (ret) {
- kfree(memptr);
- return ret;
- }
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_suspend();
-#endif
-
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
- flushinv_all_dcache();
- udelay(1);
-#endif
- _disable_dcplb();
- _disable_icplb();
- bf53x_suspend_l1_mem(memptr);
-
-#ifndef CONFIG_BF60x
- do_hibernate(wakeup | vr_wakeup); /* See you later! */
-#else
- bfin_cpu_pm->enter(PM_SUSPEND_MEM);
-#endif
-
- bf53x_resume_l1_mem(memptr);
-
- _enable_icplb();
- _enable_dcplb();
-
-#ifdef CONFIG_GPIO_ADI
- bfin_gpio_pm_hibernate_restore();
-#endif
- blackfin_dma_resume();
-
- kfree(memptr);
-
- return 0;
-}
-
-/*
- * bfin_pm_valid - Tell the PM core that we only support the standby sleep
- * state
- * @state: suspend state we're checking.
- *
- */
-static int bfin_pm_valid(suspend_state_t state)
-{
- return (state == PM_SUSPEND_STANDBY
-#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
- /*
- * On BF533/2/1:
- * If we enter Hibernate the SCKE Pin is driven Low,
- * so that the SDRAM enters Self Refresh Mode.
- * However when the reset sequence that follows hibernate
- * state is executed, SCKE is driven High, taking the
- * SDRAM out of Self Refresh.
- *
- * If you reconfigure and access the SDRAM "very quickly",
- * you are likely to avoid errors, otherwise the SDRAM
- * start losing its contents.
- * An external HW workaround is possible using logic gates.
- */
- || state == PM_SUSPEND_MEM
-#endif
- );
-}
-
-/*
- * bfin_pm_enter - Actually enter a sleep state.
- * @state: State we're entering.
- *
- */
-static int bfin_pm_enter(suspend_state_t state)
-{
- switch (state) {
- case PM_SUSPEND_STANDBY:
- bfin_pm_suspend_standby_enter();
- break;
- case PM_SUSPEND_MEM:
- bfin_pm_suspend_mem_enter();
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
-void bfin_pm_end(void)
-{
- u32 cycle, cycle2;
- u64 usec64;
- u32 usec;
-
- __asm__ __volatile__ (
- "1: %0 = CYCLES2\n"
- "%1 = CYCLES\n"
- "%2 = CYCLES2\n"
- "CC = %2 == %0\n"
- "if ! CC jump 1b\n"
- : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
- );
-
- usec64 = ((u64)cycle2 << 32) + cycle;
- do_div(usec64, get_cclk() / USEC_PER_SEC);
- usec = usec64;
- if (usec == 0)
- usec = 1;
-
- pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
- usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
-}
-#endif
-
-static const struct platform_suspend_ops bfin_pm_ops = {
- .enter = bfin_pm_enter,
- .valid = bfin_pm_valid,
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
- .end = bfin_pm_end,
-#endif
-};
-
-static int __init bfin_pm_init(void)
-{
- suspend_set_ops(&bfin_pm_ops);
- return 0;
-}
-
-__initcall(bfin_pm_init);
diff --git a/arch/blackfin/mach-common/scb-init.c b/arch/blackfin/mach-common/scb-init.c
deleted file mode 100644
index 8923398db66f..000000000000
--- a/arch/blackfin/mach-common/scb-init.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
- *
- * Copyright 2012 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <asm/scb.h>
-
-__attribute__((l1_text))
-inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i)
- bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
-}
-
-__attribute__((l1_text))
-inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
- unsigned char *scb_mi_prio)
-{
- unsigned int i;
-
- for (i = 0; i < slots; ++i) {
- bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
- scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
- }
-}
-
-__attribute__((l1_text))
-void init_scb(void)
-{
- unsigned int i, j;
- unsigned char scb_tmp_prio[32];
-
- pr_info("Init System Crossbar\n");
- for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
-
- scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
-
- pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
- scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
- for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
- pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
- }
-
-}
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
deleted file mode 100644
index b32ddab7966c..000000000000
--- a/arch/blackfin/mach-common/smp.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
- *
- * Copyright 2007-2009 Analog Devices Inc.
- * Philippe Gerum <rpm@xenomai.org>
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task_stack.h>
-#include <linux/interrupt.h>
-#include <linux/cache.h>
-#include <linux/clockchips.h>
-#include <linux/profile.h>
-#include <linux/errno.h>
-#include <linux/mm.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/cpumask.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-#include <linux/atomic.h>
-#include <asm/cacheflush.h>
-#include <asm/irq_handler.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>
-#include <asm/cpu.h>
-#include <asm/time.h>
-#include <linux/err.h>
-
-/*
- * Anomaly notes:
- * 05000120 - we always define corelock as 32-bit integer in L2
- */
-struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
-
-#ifdef CONFIG_ICACHE_FLUSH_L1
-unsigned long blackfin_iflush_l1_entry[NR_CPUS];
-#endif
-
-struct blackfin_initial_pda initial_pda_coreb;
-
-enum ipi_message_type {
- BFIN_IPI_NONE,
- BFIN_IPI_TIMER,
- BFIN_IPI_RESCHEDULE,
- BFIN_IPI_CALL_FUNC,
- BFIN_IPI_CPU_STOP,
-};
-
-struct blackfin_flush_data {
- unsigned long start;
- unsigned long end;
-};
-
-void *secondary_stack;
-
-static struct blackfin_flush_data smp_flush_data;
-
-static DEFINE_SPINLOCK(stop_lock);
-
-/* A magic number - stress test shows this is safe for common cases */
-#define BFIN_IPI_MSGQ_LEN 5
-
-/* Simple FIFO buffer, overflow leads to panic */
-struct ipi_data {
- atomic_t count;
- atomic_t bits;
-};
-
-static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
-
-static void ipi_cpu_stop(unsigned int cpu)
-{
- spin_lock(&stop_lock);
- printk(KERN_CRIT "CPU%u: stopping\n", cpu);
- dump_stack();
- spin_unlock(&stop_lock);
-
- set_cpu_online(cpu, false);
-
- local_irq_disable();
-
- while (1)
- SSYNC();
-}
-
-static void ipi_flush_icache(void *info)
-{
- struct blackfin_flush_data *fdata = info;
-
- /* Invalidate the memory holding the bounds of the flushed region. */
- blackfin_dcache_invalidate_range((unsigned long)fdata,
- (unsigned long)fdata + sizeof(*fdata));
-
- /* Make sure all write buffers in the data side of the core
- * are flushed before trying to invalidate the icache. This
- * needs to be after the data flush and before the icache
- * flush so that the SSYNC does the right thing in preventing
- * the instruction prefetcher from hitting things in cached
- * memory at the wrong time -- it runs much further ahead than
- * the pipeline.
- */
- SSYNC();
-
- /* ipi_flaush_icache is invoked by generic flush_icache_range,
- * so call blackfin arch icache flush directly here.
- */
- blackfin_icache_flush_range(fdata->start, fdata->end);
-}
-
-/* Use IRQ_SUPPLE_0 to request reschedule.
- * When returning from interrupt to user space,
- * there is chance to reschedule */
-static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
-{
- unsigned int cpu = smp_processor_id();
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_0);
- return IRQ_HANDLED;
-}
-
-DECLARE_PER_CPU(struct clock_event_device, coretmr_events);
-void ipi_timer(void)
-{
- int cpu = smp_processor_id();
- struct clock_event_device *evt = &per_cpu(coretmr_events, cpu);
- evt->event_handler(evt);
-}
-
-static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
-{
- struct ipi_data *bfin_ipi_data;
- unsigned int cpu = smp_processor_id();
- unsigned long pending;
- unsigned long msg;
-
- platform_clear_ipi(cpu, IRQ_SUPPLE_1);
-
- smp_rmb();
- bfin_ipi_data = this_cpu_ptr(&bfin_ipi);
- while ((pending = atomic_xchg(&bfin_ipi_data->bits, 0)) != 0) {
- msg = 0;
- do {
- msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
- switch (msg) {
- case BFIN_IPI_TIMER:
- ipi_timer();
- break;
- case BFIN_IPI_RESCHEDULE:
- scheduler_ipi();
- break;
- case BFIN_IPI_CALL_FUNC:
- generic_smp_call_function_interrupt();
- break;
- case BFIN_IPI_CPU_STOP:
- ipi_cpu_stop(cpu);
- break;
- default:
- goto out;
- }
- atomic_dec(&bfin_ipi_data->count);
- } while (msg < BITS_PER_LONG);
-
- }
-out:
- return IRQ_HANDLED;
-}
-
-static void bfin_ipi_init(void)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- for_each_possible_cpu(cpu) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_set(&bfin_ipi_data->bits, 0);
- atomic_set(&bfin_ipi_data->count, 0);
- }
-}
-
-void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
-{
- unsigned int cpu;
- struct ipi_data *bfin_ipi_data;
- unsigned long flags;
-
- local_irq_save(flags);
- for_each_cpu(cpu, cpumask) {
- bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
- atomic_or((1 << msg), &bfin_ipi_data->bits);
- atomic_inc(&bfin_ipi_data->count);
- }
- local_irq_restore(flags);
- smp_wmb();
- for_each_cpu(cpu, cpumask)
- platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
-}
-
-void arch_send_call_function_single_ipi(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
-}
-
-void arch_send_call_function_ipi_mask(const struct cpumask *mask)
-{
- send_ipi(mask, BFIN_IPI_CALL_FUNC);
-}
-
-void smp_send_reschedule(int cpu)
-{
- send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
-
- return;
-}
-
-void smp_send_msg(const struct cpumask *mask, unsigned long type)
-{
- send_ipi(mask, type);
-}
-
-void smp_timer_broadcast(const struct cpumask *mask)
-{
- smp_send_msg(mask, BFIN_IPI_TIMER);
-}
-
-void smp_send_stop(void)
-{
- cpumask_t callmap;
-
- preempt_disable();
- cpumask_copy(&callmap, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &callmap);
- if (!cpumask_empty(&callmap))
- send_ipi(&callmap, BFIN_IPI_CPU_STOP);
-
- preempt_enable();
-
- return;
-}
-
-int __cpu_up(unsigned int cpu, struct task_struct *idle)
-{
- int ret;
-
- secondary_stack = task_stack_page(idle) + THREAD_SIZE;
-
- ret = platform_boot_secondary(cpu, idle);
-
- secondary_stack = NULL;
-
- return ret;
-}
-
-static void setup_secondary(unsigned int cpu)
-{
- unsigned long ilat;
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- /* Enable interrupt levels IVG7-15. IARs have been already
- * programmed by the boot CPU. */
- bfin_irq_flags |= IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-}
-
-void secondary_start_kernel(void)
-{
- unsigned int cpu = smp_processor_id();
- struct mm_struct *mm = &init_mm;
-
- if (_bfin_swrst & SWRST_DBL_FAULT_B) {
- printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
-#ifdef CONFIG_DEBUG_DOUBLEFAULT
- printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n",
- initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE,
- initial_pda_coreb.retx_doublefault);
- printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.dcplb_doublefault_addr);
- printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n",
- initial_pda_coreb.icplb_doublefault_addr);
-#endif
- printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
- initial_pda_coreb.retx);
- }
-
- /*
- * We want the D-cache to be enabled early, in case the atomic
- * support code emulates cache coherence (see
- * __ARCH_SYNC_CORE_DCACHE).
- */
- init_exception_vectors();
-
- local_irq_disable();
-
- /* Attach the new idle task to the global mm. */
- mmget(mm);
- mmgrab(mm);
- current->active_mm = mm;
-
- preempt_disable();
-
- setup_secondary(cpu);
-
- platform_secondary_init(cpu);
- /* setup local core timer */
- bfin_local_timer_setup();
-
- local_irq_enable();
-
- bfin_setup_caches(cpu);
-
- notify_cpu_starting(cpu);
- /*
- * Calibrate loops per jiffy value.
- * IRQs need to be enabled here - D-cache can be invalidated
- * in timer irq handler, so core B can read correct jiffies.
- */
- calibrate_delay();
-
- /* We are done with local CPU inits, unblock the boot CPU. */
- set_cpu_online(cpu, true);
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
-}
-
-void __init smp_prepare_boot_cpu(void)
-{
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- platform_prepare_cpus(max_cpus);
- bfin_ipi_init();
- platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
- platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
-}
-
-void __init smp_cpus_done(unsigned int max_cpus)
-{
- unsigned long bogosum = 0;
- unsigned int cpu;
-
- for_each_online_cpu(cpu)
- bogosum += loops_per_jiffy;
-
- printk(KERN_INFO "SMP: Total of %d processors activated "
- "(%lu.%02lu BogoMIPS).\n",
- num_online_cpus(),
- bogosum / (500000/HZ),
- (bogosum / (5000/HZ)) % 100);
-}
-
-void smp_icache_flush_range_others(unsigned long start, unsigned long end)
-{
- smp_flush_data.start = start;
- smp_flush_data.end = end;
-
- preempt_disable();
- if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1))
- printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
- preempt_enable();
-}
-EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
-
-#ifdef __ARCH_SYNC_CORE_ICACHE
-unsigned long icache_invld_count[NR_CPUS];
-void resync_core_icache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_icache();
- icache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_icache);
-#endif
-
-#ifdef __ARCH_SYNC_CORE_DCACHE
-unsigned long dcache_invld_count[NR_CPUS];
-unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
-
-void resync_core_dcache(void)
-{
- unsigned int cpu = get_cpu();
- blackfin_invalidate_entire_dcache();
- dcache_invld_count[cpu]++;
- put_cpu();
-}
-EXPORT_SYMBOL(resync_core_dcache);
-#endif
-
-#ifdef CONFIG_HOTPLUG_CPU
-int __cpu_disable(void)
-{
- unsigned int cpu = smp_processor_id();
-
- if (cpu == 0)
- return -EPERM;
-
- set_cpu_online(cpu, false);
- return 0;
-}
-
-int __cpu_die(unsigned int cpu)
-{
- return cpu_wait_death(cpu, 5);
-}
-
-void cpu_die(void)
-{
- (void)cpu_report_death();
-
- atomic_dec(&init_mm.mm_users);
- atomic_dec(&init_mm.mm_count);
-
- local_irq_disable();
- platform_cpu_die();
-}
-#endif
diff --git a/arch/blackfin/mm/Makefile b/arch/blackfin/mm/Makefile
deleted file mode 100644
index 4c011b1f661f..000000000000
--- a/arch/blackfin/mm/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# arch/blackfin/mm/Makefile
-#
-
-obj-y := sram-alloc.o isram-driver.o init.o maccess.o
diff --git a/arch/blackfin/mm/blackfin_sram.h b/arch/blackfin/mm/blackfin_sram.h
deleted file mode 100644
index fb0b1599cfb7..000000000000
--- a/arch/blackfin/mm/blackfin_sram.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Local prototypes meant for internal use only
- *
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BLACKFIN_SRAM_H__
-#define __BLACKFIN_SRAM_H__
-
-extern void *l1sram_alloc(size_t);
-
-#endif
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
deleted file mode 100644
index b59cd7c3261a..000000000000
--- a/arch/blackfin/mm/init.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/gfp.h>
-#include <linux/swap.h>
-#include <linux/bootmem.h>
-#include <linux/uaccess.h>
-#include <linux/export.h>
-#include <asm/bfin-global.h>
-#include <asm/pda.h>
-#include <asm/cplbinit.h>
-#include <asm/early_printk.h>
-#include "blackfin_sram.h"
-
-/*
- * ZERO_PAGE is a special page that is used for zero-initialized data and COW.
- * Let the bss do its zero-init magic so we don't have to do it ourselves.
- */
-char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
-EXPORT_SYMBOL(empty_zero_page);
-
-#ifndef CONFIG_EXCEPTION_L1_SCRATCH
-#if defined CONFIG_SYSCALL_TAB_L1
-__attribute__((l1_data))
-#endif
-static unsigned long exception_stack[NR_CPUS][1024];
-#endif
-
-struct blackfin_pda cpu_pda[NR_CPUS];
-EXPORT_SYMBOL(cpu_pda);
-
-/*
- * paging_init() continues the virtual memory environment setup which
- * was begun by the code in arch/head.S.
- * The parameters are pointers to where to stick the starting and ending
- * addresses of available kernel virtual memory.
- */
-void __init paging_init(void)
-{
- /*
- * make sure start_mem is page aligned, otherwise bootmem and
- * page_alloc get different views of the world
- */
- unsigned long end_mem = memory_end & PAGE_MASK;
-
- unsigned long zones_size[MAX_NR_ZONES] = {
- [0] = 0,
- [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
- [ZONE_NORMAL] = 0,
-#ifdef CONFIG_HIGHMEM
- [ZONE_HIGHMEM] = 0,
-#endif
- };
-
- /* Set up SFC/DFC registers (user data space) */
- set_fs(KERNEL_DS);
-
- pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
- PAGE_ALIGN(memory_start), end_mem);
- free_area_init_node(0, zones_size,
- CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
-}
-
-asmlinkage void __init init_pda(void)
-{
- unsigned int cpu = raw_smp_processor_id();
-
- early_shadow_stamp();
-
- /* Initialize the PDA fields holding references to other parts
- of the memory. The content of such memory is still
- undefined at the time of the call, we are only setting up
- valid pointers to it. */
- memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
-
-#ifdef CONFIG_EXCEPTION_L1_SCRATCH
- cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
- L1_SCRATCH_LENGTH);
-#else
- cpu_pda[cpu].ex_stack = exception_stack[cpu + 1];
-#endif
-
-#ifdef CONFIG_SMP
- cpu_pda[cpu].imask = 0x1f;
-#endif
-}
-
-void __init mem_init(void)
-{
- char buf[64];
-
- high_memory = (void *)(memory_end & PAGE_MASK);
- max_mapnr = MAP_NR(high_memory);
- printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", max_mapnr);
-
- /* This will put all low memory onto the freelists. */
- free_all_bootmem();
-
- snprintf(buf, sizeof(buf) - 1, "%uK DMA", DMA_UNCACHED_REGION >> 10);
- mem_init_print_info(buf);
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void __init free_initrd_mem(unsigned long start, unsigned long end)
-{
-#ifndef CONFIG_MPU
- free_reserved_area((void *)start, (void *)end, -1, "initrd");
-#endif
-}
-#endif
-
-void __ref free_initmem(void)
-{
-#if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
- free_initmem_default(-1);
- if (memory_start == (unsigned long)(&__init_end))
- memory_start = (unsigned long)(&__init_begin);
-#endif
-}
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c
deleted file mode 100644
index aaa1e64b753b..000000000000
--- a/arch/blackfin/mm/isram-driver.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Instruction SRAM accessor functions for the Blackfin
- *
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#define pr_fmt(fmt) "isram: " fmt
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-
-#include <asm/blackfin.h>
-#include <asm/dma.h>
-
-/*
- * IMPORTANT WARNING ABOUT THESE FUNCTIONS
- *
- * The emulator will not function correctly if a write command is left in
- * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
- * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
- * and DTEST_COMMAND are zero when exiting these functions.
- */
-
-
-/*
- * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
- * be accessed by a normal core load, so we need to go through a few hoops to
- * read/write it.
- * To try to make it easier - we export a memcpy interface, where either src or
- * dest can be in this special L1 memory area.
- * The low level read/write functions should not be exposed to the rest of the
- * kernel, since they operate on 64-bit data, and need specific address alignment
- */
-
-static DEFINE_SPINLOCK(dtest_lock);
-
-/* Takes a void pointer */
-#define IADDR2DTEST(x) \
- ({ unsigned long __addr = (unsigned long)(x); \
- ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \
- (1 << 24) | /* instruction access = 1 */ \
- ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \
- ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
- (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \
- (1 << 2); /* data array = 1 */ \
- })
-
-/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
-#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
-
-/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
-#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
-
-static void isram_write(const void *addr, uint64_t data)
-{
- uint32_t cmd;
- unsigned long flags;
-
- if (unlikely(addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return;
-
- cmd = IADDR2DTEST(addr) | 2; /* write */
-
- /*
- * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
-
- bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
- bfin_write_DTEST_DATA1(data >> 32);
-
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
-
- spin_unlock_irqrestore(&dtest_lock, flags);
-}
-
-static uint64_t isram_read(const void *addr)
-{
- uint32_t cmd;
- unsigned long flags;
- uint64_t ret;
-
- if (unlikely(addr > (void *)(L1_CODE_START + L1_CODE_LENGTH)))
- return 0;
-
- cmd = IADDR2DTEST(addr) | 0; /* read */
-
- /*
- * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
- * While in exception context - atomicity is guaranteed or double fault
- */
- spin_lock_irqsave(&dtest_lock, flags);
- /* use the builtin, since interrupts are already turned off */
- __builtin_bfin_csync();
- bfin_write_DTEST_COMMAND(cmd);
- __builtin_bfin_csync();
- ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
-
- bfin_write_DTEST_COMMAND(0);
- __builtin_bfin_csync();
- spin_unlock_irqrestore(&dtest_lock, flags);
-
- return ret;
-}
-
-static bool isram_check_addr(const void *addr, size_t n)
-{
- if ((addr >= (void *)L1_CODE_START) &&
- (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- if (unlikely((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
- show_stack(NULL, NULL);
- pr_err("copy involving %p length (%zu) too long\n", addr, n);
- }
- return true;
- }
- return false;
-}
-
-/*
- * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
- * The isram_memcpy() function returns a pointer to dest.
- * Either dest or src can be in L1 instruction sram.
- */
-void *isram_memcpy(void *dest, const void *src, size_t n)
-{
- uint64_t data_in = 0, data_out = 0;
- size_t count;
- bool dest_in_l1, src_in_l1, need_data, put_data;
- unsigned char byte, *src_byte, *dest_byte;
-
- src_byte = (unsigned char *)src;
- dest_byte = (unsigned char *)dest;
-
- dest_in_l1 = isram_check_addr(dest, n);
- src_in_l1 = isram_check_addr(src, n);
-
- need_data = true;
- put_data = true;
- for (count = 0; count < n; count++) {
- if (src_in_l1) {
- if (need_data) {
- data_in = isram_read(src + count);
- need_data = false;
- }
-
- if (ADDR2LAST(src + count))
- need_data = true;
-
- byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
-
- } else {
- /* src is in L2 or L3 - so just dereference*/
- byte = src_byte[count];
- }
-
- if (dest_in_l1) {
- if (put_data) {
- data_out = isram_read(dest + count);
- put_data = false;
- }
-
- data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
- data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
-
- if (ADDR2LAST(dest + count)) {
- put_data = true;
- isram_write(dest + count, data_out);
- }
- } else {
- /* dest in L2 or L3 - so just dereference */
- dest_byte[count] = byte;
- }
- }
-
- /* make sure we dump the last byte if necessary */
- if (dest_in_l1 && !put_data)
- isram_write(dest + count, data_out);
-
- return dest;
-}
-EXPORT_SYMBOL(isram_memcpy);
-
-#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
-
-static int test_len = 0x20000;
-
-static __init void hex_dump(unsigned char *buf, int len)
-{
- while (len--)
- pr_cont("%02x", *buf++);
-}
-
-static __init int isram_read_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_read tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- /* make sure we can read the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- data1 = isram_read(l1inst + i);
- memcpy(&data2, sdram + i, sizeof(data2));
- if (data1 != data2) {
- pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- return ret;
-}
-
-static __init int isram_write_test(char *sdram, void *l1inst)
-{
- int i, ret = 0;
- uint64_t data1, data2;
-
- pr_info("INFO: running isram_write tests\n");
-
- /* setup some different data to play with */
- memset(sdram, 0, test_len * 2);
- dma_memcpy(l1inst, sdram, test_len);
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
-
- /* make sure we can write the L1 inst */
- for (i = 0; i < test_len; i += sizeof(uint64_t)) {
- memcpy(&data1, sdram + i, sizeof(data1));
- isram_write(l1inst + i, data1);
- data2 = isram_read(l1inst + i);
- if (data1 != data2) {
- pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
- l1inst + i, data1, data2);
- ++ret;
- }
- }
-
- dma_memcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: isram_write() did not work properly\n");
- ++ret;
- }
-
- return ret;
-}
-
-static __init int
-_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
- void *(*fmemcpy)(void *, const void *, size_t))
-{
- memset(sdram, pattern, test_len);
- fmemcpy(l1inst, sdram, test_len);
- fmemcpy(sdram + test_len, l1inst, test_len);
- if (memcmp(sdram, sdram + test_len, test_len)) {
- pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
- smemcpy, l1inst, sdram, test_len, pattern);
- return 1;
- }
- return 0;
-}
-#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
-
-static __init int isram_memcpy_test(char *sdram, void *l1inst)
-{
- int i, j, thisret, ret = 0;
-
- /* check broad isram_memcpy() */
- pr_info("INFO: running broad isram_memcpy tests\n");
- for (i = 0xf; i >= 0; --i)
- ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);
-
- /* check read of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (read) tests\n");
-
- /* setup some different data to play with */
- for (i = 0; i < test_len; ++i)
- sdram[i] = i % 255;
- dma_memcpy(l1inst, sdram, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- memset(cmp, 0, sizeof(cmp));
- isram_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + 1);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- /* check write of small, unaligned, and hardware 64bit limits */
- pr_info("INFO: running isram_memcpy (write) tests\n");
-
- memset(sdram + test_len, 0, test_len);
- dma_memcpy(l1inst, sdram + test_len, test_len);
-
- thisret = 0;
- for (i = 0; i < test_len - 32; ++i) {
- unsigned char cmp[32];
- for (j = 1; j <= 32; ++j) {
- isram_memcpy(l1inst + i, sdram + i, j);
- dma_memcpy(cmp, l1inst + i, j);
- if (memcmp(cmp, sdram + i, j)) {
- pr_err("FAIL: %p:", l1inst + i);
- hex_dump(cmp, j);
- pr_cont(" SDRAM:");
- hex_dump(sdram + i, j);
- pr_cont("\n");
- if (++thisret > 20) {
- pr_err("FAIL: skipping remaining series\n");
- i = test_len;
- break;
- }
- }
- }
- }
- ret += thisret;
-
- return ret;
-}
-
-static __init int isram_test_init(void)
-{
- int ret;
- char *sdram;
- void *l1inst;
-
- /* Try to test as much of L1SRAM as possible */
- while (test_len) {
- test_len >>= 1;
- l1inst = l1_inst_sram_alloc(test_len);
- if (l1inst)
- break;
- }
- if (!l1inst) {
- pr_warning("SKIP: could not allocate L1 inst\n");
- return 0;
- }
- pr_info("INFO: testing %#x bytes (%p - %p)\n",
- test_len, l1inst, l1inst + test_len);
-
- sdram = kmalloc(test_len * 2, GFP_KERNEL);
- if (!sdram) {
- sram_free(l1inst);
- pr_warning("SKIP: could not allocate sdram\n");
- return 0;
- }
-
- /* sanity check initial L1 inst state */
- ret = 1;
- pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
- if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
- goto abort;
- if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
- goto abort;
-
- ret = 0;
- ret += isram_read_test(sdram, l1inst);
- ret += isram_write_test(sdram, l1inst);
- ret += isram_memcpy_test(sdram, l1inst);
-
- abort:
- sram_free(l1inst);
- kfree(sdram);
-
- if (ret)
- return -EIO;
-
- pr_info("PASS: all tests worked !\n");
- return 0;
-}
-late_initcall(isram_test_init);
-
-static __exit void isram_test_exit(void)
-{
- /* stub to allow unloading */
-}
-module_exit(isram_test_exit);
-
-#endif
diff --git a/arch/blackfin/mm/maccess.c b/arch/blackfin/mm/maccess.c
deleted file mode 100644
index e2532114c5fd..000000000000
--- a/arch/blackfin/mm/maccess.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * safe read and write memory routines callable while atomic
- *
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/uaccess.h>
-#include <asm/dma.h>
-
-static int validate_memory_access_address(unsigned long addr, int size)
-{
- if (size < 0 || addr == 0)
- return -EFAULT;
- return bfin_mem_access_type(addr, size);
-}
-
-long probe_kernel_read(void *dst, const void *src, size_t size)
-{
- unsigned long lsrc = (unsigned long)src;
- int mem_type;
-
- mem_type = validate_memory_access_address(lsrc, size);
- if (mem_type < 0)
- return mem_type;
-
- if (lsrc >= SYSMMR_BASE) {
- if (size == 2 && lsrc % 2 == 0) {
- u16 mmr = bfin_read16(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- } else if (size == 4 && lsrc % 4 == 0) {
- u32 mmr = bfin_read32(src);
- memcpy(dst, &mmr, sizeof(mmr));
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_read(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
-
-long probe_kernel_write(void *dst, const void *src, size_t size)
-{
- unsigned long ldst = (unsigned long)dst;
- int mem_type;
-
- mem_type = validate_memory_access_address(ldst, size);
- if (mem_type < 0)
- return mem_type;
-
- if (ldst >= SYSMMR_BASE) {
- if (size == 2 && ldst % 2 == 0) {
- u16 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write16(dst, mmr);
- return 0;
- } else if (size == 4 && ldst % 4 == 0) {
- u32 mmr;
- memcpy(&mmr, src, sizeof(mmr));
- bfin_write32(dst, mmr);
- return 0;
- }
- } else {
- switch (mem_type) {
- case BFIN_MEM_ACCESS_CORE:
- case BFIN_MEM_ACCESS_CORE_ONLY:
- return __probe_kernel_write(dst, src, size);
- /* XXX: should support IDMA here with SMP */
- case BFIN_MEM_ACCESS_DMA:
- if (dma_memcpy(dst, src, size))
- return 0;
- break;
- case BFIN_MEM_ACCESS_ITEST:
- if (isram_memcpy(dst, src, size))
- return 0;
- break;
- }
- }
-
- return -EFAULT;
-}
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
deleted file mode 100644
index d2a96c2c02a3..000000000000
--- a/arch/blackfin/mm/sram-alloc.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * SRAM allocator for Blackfin on-chip memory
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/miscdevice.h>
-#include <linux/ioport.h>
-#include <linux/fcntl.h>
-#include <linux/init.h>
-#include <linux/poll.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/spinlock.h>
-#include <linux/rtc.h>
-#include <linux/slab.h>
-#include <linux/mm_types.h>
-
-#include <asm/blackfin.h>
-#include <asm/mem_map.h>
-#include "blackfin_sram.h"
-
-/* the data structure for L1 scratchpad and DATA SRAM */
-struct sram_piece {
- void *paddr;
- int size;
- pid_t pid;
- struct sram_piece *next;
-};
-
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_ssram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_ssram_head);
-
-#if L1_DATA_A_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_A_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_A_sram_head);
-#endif
-
-#if L1_DATA_B_LENGTH != 0
-static DEFINE_PER_CPU(struct sram_piece, free_l1_data_B_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_data_B_sram_head);
-#endif
-
-#if L1_DATA_A_LENGTH || L1_DATA_B_LENGTH
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_data_sram_lock);
-#endif
-
-#if L1_CODE_LENGTH != 0
-static DEFINE_PER_CPU_SHARED_ALIGNED(spinlock_t, l1_inst_sram_lock);
-static DEFINE_PER_CPU(struct sram_piece, free_l1_inst_sram_head);
-static DEFINE_PER_CPU(struct sram_piece, used_l1_inst_sram_head);
-#endif
-
-#if L2_LENGTH != 0
-static spinlock_t l2_sram_lock ____cacheline_aligned_in_smp;
-static struct sram_piece free_l2_sram_head, used_l2_sram_head;
-#endif
-
-static struct kmem_cache *sram_piece_cache;
-
-/* L1 Scratchpad SRAM initialization function */
-static void __init l1sram_init(void)
-{
- unsigned int cpu;
- unsigned long reserve;
-
-#ifdef CONFIG_SMP
- reserve = 0;
-#else
- reserve = sizeof(struct l1_scratch_task_info);
-#endif
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_ssram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_ssram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize Scratchpad data SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_ssram_head, cpu).next->paddr = (void *)get_l1_scratch_start_cpu(cpu) + reserve;
- per_cpu(free_l1_ssram_head, cpu).next->size = L1_SCRATCH_LENGTH - reserve;
- per_cpu(free_l1_ssram_head, cpu).next->pid = 0;
- per_cpu(free_l1_ssram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_ssram_head, cpu).next = NULL;
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1sram_lock, cpu));
- printk(KERN_INFO "Blackfin Scratchpad data SRAM: %d KB\n",
- L1_SCRATCH_LENGTH >> 10);
- }
-}
-
-static void __init l1_data_sram_init(void)
-{
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- unsigned int cpu;
-#endif
-#if L1_DATA_A_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_A_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_A_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data A SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_A_sram_head, cpu).next->paddr =
- (void *)get_l1_data_a_start_cpu(cpu) + (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->size =
- L1_DATA_A_LENGTH - (_ebss_l1 - _sdata_l1);
- per_cpu(free_l1_data_A_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_A_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_A_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data A SRAM: %d KB (%d KB free)\n",
- L1_DATA_A_LENGTH >> 10,
- per_cpu(free_l1_data_A_sram_head, cpu).next->size >> 10);
- }
-#endif
-#if L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_data_B_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_data_B_sram_head, cpu).next) {
- printk(KERN_INFO "Fail to initialize L1 Data B SRAM.\n");
- return;
- }
-
- per_cpu(free_l1_data_B_sram_head, cpu).next->paddr =
- (void *)get_l1_data_b_start_cpu(cpu) + (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->size =
- L1_DATA_B_LENGTH - (_ebss_b_l1 - _sdata_b_l1);
- per_cpu(free_l1_data_B_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_data_B_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_data_B_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Data B SRAM: %d KB (%d KB free)\n",
- L1_DATA_B_LENGTH >> 10,
- per_cpu(free_l1_data_B_sram_head, cpu).next->size >> 10);
- /* mutex initialize */
- }
-#endif
-
-#if L1_DATA_A_LENGTH != 0 || L1_DATA_B_LENGTH != 0
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
- spin_lock_init(&per_cpu(l1_data_sram_lock, cpu));
-#endif
-}
-
-static void __init l1_inst_sram_init(void)
-{
-#if L1_CODE_LENGTH != 0
- unsigned int cpu;
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- per_cpu(free_l1_inst_sram_head, cpu).next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!per_cpu(free_l1_inst_sram_head, cpu).next) {
- printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
- return;
- }
-
- per_cpu(free_l1_inst_sram_head, cpu).next->paddr =
- (void *)get_l1_code_start_cpu(cpu) + (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->size =
- L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
- per_cpu(free_l1_inst_sram_head, cpu).next->pid = 0;
- per_cpu(free_l1_inst_sram_head, cpu).next->next = NULL;
-
- per_cpu(used_l1_inst_sram_head, cpu).next = NULL;
-
- printk(KERN_INFO "Blackfin L1 Instruction SRAM: %d KB (%d KB free)\n",
- L1_CODE_LENGTH >> 10,
- per_cpu(free_l1_inst_sram_head, cpu).next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&per_cpu(l1_inst_sram_lock, cpu));
- }
-#endif
-}
-
-#ifdef __ADSPBF60x__
-static irqreturn_t l2_ecc_err(int irq, void *dev_id)
-{
- int status;
-
- printk(KERN_ERR "L2 ecc error happened\n");
- status = bfin_read32(L2CTL0_STAT);
- if (status & 0x1)
- printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0));
- if (status & 0x2)
- printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n",
- bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1));
-
- status = status >> 8;
- if (status)
- printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n",
- status, bfin_read32(L2CTL0_ERRADDR0 + status));
-
- panic("L2 Ecc error");
- return IRQ_HANDLED;
-}
-#endif
-
-static void __init l2_sram_init(void)
-{
-#if L2_LENGTH != 0
-
-#ifdef __ADSPBF60x__
- int ret;
-
- ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err",
- NULL);
- if (unlikely(ret < 0)) {
- printk(KERN_INFO "Fail to request l2 ecc error interrupt");
- return;
- }
-#endif
-
- free_l2_sram_head.next =
- kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
- if (!free_l2_sram_head.next) {
- printk(KERN_INFO "Fail to initialize L2 SRAM.\n");
- return;
- }
-
- free_l2_sram_head.next->paddr =
- (void *)L2_START + (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->size =
- L2_LENGTH - (_ebss_l2 - _stext_l2);
- free_l2_sram_head.next->pid = 0;
- free_l2_sram_head.next->next = NULL;
-
- used_l2_sram_head.next = NULL;
-
- printk(KERN_INFO "Blackfin L2 SRAM: %d KB (%d KB free)\n",
- L2_LENGTH >> 10,
- free_l2_sram_head.next->size >> 10);
-
- /* mutex initialize */
- spin_lock_init(&l2_sram_lock);
-#endif
-}
-
-static int __init bfin_sram_init(void)
-{
- sram_piece_cache = kmem_cache_create("sram_piece_cache",
- sizeof(struct sram_piece),
- 0, SLAB_PANIC, NULL);
-
- l1sram_init();
- l1_data_sram_init();
- l1_inst_sram_init();
- l2_sram_init();
-
- return 0;
-}
-pure_initcall(bfin_sram_init);
-
-/* SRAM allocate function */
-static void *_sram_alloc(size_t size, struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (size <= 0 || !pfree_head || !pused_head)
- return NULL;
-
- /* Align the size */
- size = (size + 3) & ~3;
-
- pslot = pfree_head->next;
- plast = pfree_head;
-
- /* search an available piece slot */
- while (pslot != NULL && size > pslot->size) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return NULL;
-
- if (pslot->size == size) {
- plast->next = pslot->next;
- pavail = pslot;
- } else {
- /* use atomic so our L1 allocator can be used atomically */
- pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC);
-
- if (!pavail)
- return NULL;
-
- pavail->paddr = pslot->paddr;
- pavail->size = size;
- pslot->paddr += size;
- pslot->size -= size;
- }
-
- pavail->pid = current->pid;
-
- pslot = pused_head->next;
- plast = pused_head;
-
- /* insert new piece into used piece list !!! */
- while (pslot != NULL && pavail->paddr < pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- pavail->next = pslot;
- plast->next = pavail;
-
- return pavail->paddr;
-}
-
-/* Allocate the largest available block. */
-static void *_sram_alloc_max(struct sram_piece *pfree_head,
- struct sram_piece *pused_head,
- unsigned long *psize)
-{
- struct sram_piece *pslot, *pmax;
-
- if (!pfree_head || !pused_head)
- return NULL;
-
- pmax = pslot = pfree_head->next;
-
- /* search an available piece slot */
- while (pslot != NULL) {
- if (pslot->size > pmax->size)
- pmax = pslot;
- pslot = pslot->next;
- }
-
- if (!pmax)
- return NULL;
-
- *psize = pmax->size;
-
- return _sram_alloc(*psize, pfree_head, pused_head);
-}
-
-/* SRAM free function */
-static int _sram_free(const void *addr,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot, *plast, *pavail;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
- plast = pused_head;
-
- /* search an available piece slot */
- while (pslot != NULL && pslot->paddr != addr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (!pslot)
- return -1;
-
- plast->next = pslot->next;
- pavail = pslot;
- pavail->pid = 0;
-
- /* insert free pieces back to the free list */
- pslot = pfree_head->next;
- plast = pfree_head;
-
- while (pslot != NULL && addr > pslot->paddr) {
- plast = pslot;
- pslot = pslot->next;
- }
-
- if (plast != pfree_head && plast->paddr + plast->size == pavail->paddr) {
- plast->size += pavail->size;
- kmem_cache_free(sram_piece_cache, pavail);
- } else {
- pavail->next = plast->next;
- plast->next = pavail;
- plast = pavail;
- }
-
- if (pslot && plast->paddr + plast->size == pslot->paddr) {
- plast->size += pslot->size;
- plast->next = pslot->next;
- kmem_cache_free(sram_piece_cache, pslot);
- }
-
- return 0;
-}
-
-int sram_free(const void *addr)
-{
-
-#if L1_CODE_LENGTH != 0
- if (addr >= (void *)get_l1_code_start()
- && addr < (void *)(get_l1_code_start() + L1_CODE_LENGTH))
- return l1_inst_sram_free(addr);
- else
-#endif
-#if L1_DATA_A_LENGTH != 0
- if (addr >= (void *)get_l1_data_a_start()
- && addr < (void *)(get_l1_data_a_start() + L1_DATA_A_LENGTH))
- return l1_data_A_sram_free(addr);
- else
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (addr >= (void *)get_l1_data_b_start()
- && addr < (void *)(get_l1_data_b_start() + L1_DATA_B_LENGTH))
- return l1_data_B_sram_free(addr);
- else
-#endif
-#if L2_LENGTH != 0
- if (addr >= (void *)L2_START
- && addr < (void *)(L2_START + L2_LENGTH))
- return l2_sram_free(addr);
- else
-#endif
- return -1;
-}
-EXPORT_SYMBOL(sram_free);
-
-void *l1_data_A_sram_alloc(size_t size)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_A_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_alloc);
-
-int l1_data_A_sram_free(const void *addr)
-{
-#if L1_DATA_A_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_A_sram_free);
-
-void *l1_data_B_sram_alloc(size_t size)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_data_B_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_alloc);
-
-int l1_data_B_sram_free(const void *addr)
-{
-#if L1_DATA_B_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_data_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_data_B_sram_free);
-
-void *l1_data_sram_alloc(size_t size)
-{
- void *addr = l1_data_A_sram_alloc(size);
-
- if (!addr)
- addr = l1_data_B_sram_alloc(size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_alloc);
-
-void *l1_data_sram_zalloc(size_t size)
-{
- void *addr = l1_data_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l1_data_sram_zalloc);
-
-int l1_data_sram_free(const void *addr)
-{
- int ret;
- ret = l1_data_A_sram_free(addr);
- if (ret == -1)
- ret = l1_data_B_sram_free(addr);
- return ret;
-}
-EXPORT_SYMBOL(l1_data_sram_free);
-
-void *l1_inst_sram_alloc(size_t size)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- pr_debug("Allocated address in l1_inst_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_alloc);
-
-int l1_inst_sram_free(const void *addr)
-{
-#if L1_CODE_LENGTH != 0
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1_inst_sram_lock, cpu), flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l1_inst_sram_free);
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc(size_t size)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc(size, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory allocate function */
-void *l1sram_alloc_max(size_t *psize)
-{
- unsigned long flags;
- void *addr;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- addr = _sram_alloc_max(&per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu), psize);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return addr;
-}
-
-/* L1 Scratchpad memory free function */
-int l1sram_free(const void *addr)
-{
- unsigned long flags;
- int ret;
- unsigned int cpu;
-
- cpu = smp_processor_id();
- /* add mutex operation */
- spin_lock_irqsave(&per_cpu(l1sram_lock, cpu), flags);
-
- ret = _sram_free(addr, &per_cpu(free_l1_ssram_head, cpu),
- &per_cpu(used_l1_ssram_head, cpu));
-
- /* add mutex operation */
- spin_unlock_irqrestore(&per_cpu(l1sram_lock, cpu), flags);
-
- return ret;
-}
-
-void *l2_sram_alloc(size_t size)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- void *addr;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- addr = _sram_alloc(size, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- pr_debug("Allocated address in l2_sram_alloc is 0x%lx+0x%lx\n",
- (long unsigned int)addr, size);
-
- return addr;
-#else
- return NULL;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_alloc);
-
-void *l2_sram_zalloc(size_t size)
-{
- void *addr = l2_sram_alloc(size);
-
- if (addr)
- memset(addr, 0x00, size);
-
- return addr;
-}
-EXPORT_SYMBOL(l2_sram_zalloc);
-
-int l2_sram_free(const void *addr)
-{
-#if L2_LENGTH != 0
- unsigned long flags;
- int ret;
-
- /* add mutex operation */
- spin_lock_irqsave(&l2_sram_lock, flags);
-
- ret = _sram_free(addr, &free_l2_sram_head,
- &used_l2_sram_head);
-
- /* add mutex operation */
- spin_unlock_irqrestore(&l2_sram_lock, flags);
-
- return ret;
-#else
- return -1;
-#endif
-}
-EXPORT_SYMBOL(l2_sram_free);
-
-int sram_free_with_lsl(const void *addr)
-{
- struct sram_list_struct *lsl, **tmp;
- struct mm_struct *mm = current->mm;
- int ret = -1;
-
- for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next)
- if ((*tmp)->addr == addr) {
- lsl = *tmp;
- ret = sram_free(addr);
- *tmp = lsl->next;
- kfree(lsl);
- break;
- }
-
- return ret;
-}
-EXPORT_SYMBOL(sram_free_with_lsl);
-
-/* Allocate memory and keep in L1 SRAM List (lsl) so that the resources are
- * tracked. These are designed for userspace so that when a process exits,
- * we can safely reap their resources.
- */
-void *sram_alloc_with_lsl(size_t size, unsigned long flags)
-{
- void *addr = NULL;
- struct sram_list_struct *lsl = NULL;
- struct mm_struct *mm = current->mm;
-
- lsl = kzalloc(sizeof(struct sram_list_struct), GFP_KERNEL);
- if (!lsl)
- return NULL;
-
- if (flags & L1_INST_SRAM)
- addr = l1_inst_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_A_SRAM))
- addr = l1_data_A_sram_alloc(size);
-
- if (addr == NULL && (flags & L1_DATA_B_SRAM))
- addr = l1_data_B_sram_alloc(size);
-
- if (addr == NULL && (flags & L2_SRAM))
- addr = l2_sram_alloc(size);
-
- if (addr == NULL) {
- kfree(lsl);
- return NULL;
- }
- lsl->addr = addr;
- lsl->length = size;
- lsl->next = mm->context.sram_list;
- mm->context.sram_list = lsl;
- return addr;
-}
-EXPORT_SYMBOL(sram_alloc_with_lsl);
-
-#ifdef CONFIG_PROC_FS
-/* Once we get a real allocator, we'll throw all of this away.
- * Until then, we need some sort of visibility into the L1 alloc.
- */
-/* Need to keep line of output the same. Currently, that is 44 bytes
- * (including newline).
- */
-static int _sram_proc_show(struct seq_file *m, const char *desc,
- struct sram_piece *pfree_head,
- struct sram_piece *pused_head)
-{
- struct sram_piece *pslot;
-
- if (!pfree_head || !pused_head)
- return -1;
-
- seq_printf(m, "--- SRAM %-14s Size PID State \n", desc);
-
- /* search the relevant memory slot */
- pslot = pused_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "ALLOCATED");
-
- pslot = pslot->next;
- }
-
- pslot = pfree_head->next;
-
- while (pslot != NULL) {
- seq_printf(m, "%p-%p %10i %5i %-10s\n",
- pslot->paddr, pslot->paddr + pslot->size,
- pslot->size, pslot->pid, "FREE");
-
- pslot = pslot->next;
- }
-
- return 0;
-}
-static int sram_proc_show(struct seq_file *m, void *v)
-{
- unsigned int cpu;
-
- for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- if (_sram_proc_show(m, "Scratchpad",
- &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
- goto not_done;
-#if L1_DATA_A_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data A",
- &per_cpu(free_l1_data_A_sram_head, cpu),
- &per_cpu(used_l1_data_A_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_DATA_B_LENGTH != 0
- if (_sram_proc_show(m, "L1 Data B",
- &per_cpu(free_l1_data_B_sram_head, cpu),
- &per_cpu(used_l1_data_B_sram_head, cpu)))
- goto not_done;
-#endif
-#if L1_CODE_LENGTH != 0
- if (_sram_proc_show(m, "L1 Instruction",
- &per_cpu(free_l1_inst_sram_head, cpu),
- &per_cpu(used_l1_inst_sram_head, cpu)))
- goto not_done;
-#endif
- }
-#if L2_LENGTH != 0
- if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
- goto not_done;
-#endif
- not_done:
- return 0;
-}
-
-static int sram_proc_open(struct inode *inode, struct file *file)
-{
- return single_open(file, sram_proc_show, NULL);
-}
-
-static const struct file_operations sram_proc_ops = {
- .open = sram_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init sram_proc_init(void)
-{
- struct proc_dir_entry *ptr;
-
- ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
- if (!ptr) {
- printk(KERN_WARNING "unable to create /proc/sram\n");
- return -1;
- }
- return 0;
-}
-late_initcall(sram_proc_init);
-#endif
diff --git a/arch/blackfin/oprofile/Makefile b/arch/blackfin/oprofile/Makefile
deleted file mode 100644
index e89e1c9f3496..000000000000
--- a/arch/blackfin/oprofile/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/blackfin/oprofile/Makefile
-#
-
-obj-$(CONFIG_OPROFILE) += oprofile.o
-
-DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
- oprof.o cpu_buffer.o buffer_sync.o \
- event_buffer.o oprofile_files.o \
- oprofilefs.o oprofile_stats.o \
- timer_int.o )
-
-oprofile-y := $(DRIVER_OBJS) bfin_oprofile.o
diff --git a/arch/blackfin/oprofile/bfin_oprofile.c b/arch/blackfin/oprofile/bfin_oprofile.c
deleted file mode 100644
index c3b9713b23f8..000000000000
--- a/arch/blackfin/oprofile/bfin_oprofile.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * bfin_oprofile.c - Blackfin oprofile code
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/oprofile.h>
-#include <linux/init.h>
-
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- return -1;
-}
-
-void oprofile_arch_exit(void)
-{
-}
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
deleted file mode 100644
index cd5a0865c97f..000000000000
--- a/arch/cris/Kconfig
+++ /dev/null
@@ -1,595 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config MMU
- bool
- default y
-
-config ZONE_DMA
- bool
- default y
-
-config RWSEM_GENERIC_SPINLOCK
- bool
- default y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
-
-config ARCH_HAS_ILOG2_U32
- bool
- default n
-
-config ARCH_HAS_ILOG2_U64
- bool
- default n
-
-config GENERIC_HWEIGHT
- bool
- default y
-
-config GENERIC_CALIBRATE_DELAY
- bool
- default y
-
-config NO_IOPORT_MAP
- def_bool y if !PCI
-
-config NO_DMA
- def_bool y if !PCI
-
-config FORCE_MAX_ZONEORDER
- int
- default 6
-
-config TRACE_IRQFLAGS_SUPPORT
- depends on ETRAX_ARCH_V32
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-config LOCKDEP_SUPPORT
- depends on ETRAX_ARCH_V32
- def_bool y
-
-config CRIS
- bool
- default y
- select HAVE_IDE
- select GENERIC_ATOMIC64
- select HAVE_UID16
- select VIRT_TO_BUS
- select ARCH_WANT_IPC_PARSE_VERSION
- select GENERIC_IRQ_SHOW
- select GENERIC_IOMAP
- select MODULES_USE_ELF_RELA
- select CLONE_BACKWARDS2
- select HAVE_EXIT_THREAD if ETRAX_ARCH_V32
- select OLD_SIGSUSPEND
- select OLD_SIGACTION
- select GPIOLIB
- select IRQ_DOMAIN if ETRAX_ARCH_V32
- select OF if ETRAX_ARCH_V32
- select OF_EARLY_FLATTREE if ETRAX_ARCH_V32
- select CLKSRC_MMIO if ETRAX_ARCH_V32
- select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32
- select GENERIC_SCHED_CLOCK if ETRAX_ARCH_V32
- select HAVE_DEBUG_BUGVERBOSE if ETRAX_ARCH_V32
- select HAVE_NMI
- select DMA_DIRECT_OPS if PCI
-
-config HZ
- int
- default 100
-
-config NR_CPUS
- int
- default "1"
-
-config BUILTIN_DTB
- string "DTB to build into the kernel image"
- depends on OF
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-menu "General setup"
-
-source "fs/Kconfig.binfmt"
-
-config ETRAX_CMDLINE
- string "Kernel command line"
- default "root=/dev/mtdblock3"
- help
- Pass additional commands to the kernel.
-
-config ETRAX_WATCHDOG
- bool "Enable ETRAX watchdog"
- help
- Enable the built-in watchdog timer support on ETRAX based embedded
- network computers.
-
-config ETRAX_WATCHDOG_NICE_DOGGY
- bool "Disable watchdog during Oops printouts"
- depends on ETRAX_WATCHDOG
- help
- By enabling this you make sure that the watchdog does not bite while
- printing oopses. Recommended for development systems but not for
- production releases.
-
-config ETRAX_FAST_TIMER
- bool "Enable ETRAX fast timer API"
- help
- This options enables the API to a fast timer implementation using
- timer1 to get sub jiffie resolution timers (primarily one-shot
- timers).
- This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled.
-
-config ETRAX_KMALLOCED_MODULES
- bool "Enable module allocation with kmalloc"
- help
- Enable module allocation with kmalloc instead of vmalloc.
-
-source "kernel/Kconfig.preempt"
-
-source mm/Kconfig
-
-endmenu
-
-menu "Hardware setup"
-
-choice
- prompt "Processor type"
- default ETRAX100LX
-
-config ETRAX100LX
- bool "ETRAX-100LX-v1"
- select ARCH_USES_GETTIMEOFFSET
- help
- Support version 1 of the ETRAX 100LX.
-
-config ETRAX100LX_V2
- bool "ETRAX-100LX-v2"
- select ARCH_USES_GETTIMEOFFSET
- help
- Support version 2 of the ETRAX 100LX.
-
-config ETRAXFS
- bool "ETRAX-FS-V32"
- help
- Support CRIS V32.
-
-config CRIS_MACH_ARTPEC3
- bool "ARTPEC-3"
- help
- Support Axis ARTPEC-3.
-
-endchoice
-
-config ETRAX_ARCH_V10
- bool
- default y if ETRAX100LX || ETRAX100LX_V2
- default n if !(ETRAX100LX || ETRAX100LX_V2)
- select TTY
-
-config ETRAX_ARCH_V32
- bool
- default y if (ETRAXFS || CRIS_MACH_ARTPEC3)
- default n if !(ETRAXFS || CRIS_MACH_ARTPEC3)
-
-config ETRAX_DRAM_SIZE
- int "DRAM size (dec, in MB)"
- default "8"
- help
- Size of DRAM (decimal in MB) typically 2, 8 or 16.
-
-config ETRAX_VMEM_SIZE
- int "Video memory size (dec, in MB)"
- depends on ETRAX_ARCH_V32 && !ETRAXFS
- default 8 if !ETRAXFS
- help
- Size of Video accessible memory (decimal, in MB).
-
-config ETRAX_FLASH_BUSWIDTH
- int "Buswidth of NOR flash in bytes"
- default "2"
- help
- Width in bytes of the NOR Flash bus (1, 2 or 4). Is usually 2.
-
-config ETRAX_FLASH1_SIZE
- int "FLASH1 size (dec, in MB. 0 = Unknown)"
- default "0"
-
-choice
- prompt "Product debug-port"
- default ETRAX_DEBUG_PORT0
-
-config ETRAX_DEBUG_PORT0
- bool "Serial-0"
- help
- Choose a serial port for the ETRAX debug console. Default to
- port 0.
-
-config ETRAX_DEBUG_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for the console.
-
-config ETRAX_DEBUG_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for the console.
-
-config ETRAX_DEBUG_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for the console.
-
-config ETRAX_DEBUG_PORT_NULL
- bool "disabled"
- help
- Disable serial-port debugging.
-
-endchoice
-
-choice
- prompt "Kernel GDB port"
- depends on ETRAX_KGDB
- default ETRAX_KGDB_PORT0
- help
- Choose a serial port for kernel debugging. NOTE: This port should
- not be enabled under Drivers for built-in interfaces (as it has its
- own initialization code) and should not be the same as the debug port.
-
-config ETRAX_KGDB_PORT0
- bool "Serial-0"
- help
- Use serial port 0 for kernel debugging.
-
-config ETRAX_KGDB_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for kernel debugging.
-
-config ETRAX_KGDB_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for kernel debugging.
-
-config ETRAX_KGDB_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for kernel debugging.
-
-endchoice
-
-source arch/cris/arch-v10/Kconfig
-source arch/cris/arch-v32/Kconfig
-
-endmenu
-
-source "net/Kconfig"
-
-# bring in ETRAX built-in drivers
-menu "Drivers for built-in interfaces"
-source arch/cris/arch-v10/drivers/Kconfig
-source arch/cris/arch-v32/drivers/Kconfig
-
-config ETRAX_AXISFLASHMAP
- bool "Axis flash-map support"
- select MTD
- select MTD_CFI
- select MTD_CFI_AMDSTD
- select MTD_JEDECPROBE if ETRAX_ARCH_V32
- select MTD_BLOCK
- select MTD_COMPLEX_MAPPINGS
- help
- This option enables MTD mapping of flash devices. Needed to use
- flash memories. If unsure, say Y.
-
-config ETRAX_SYNCHRONOUS_SERIAL
- bool "Synchronous serial-port support"
- help
- Select this to enable the synchronous serial port driver.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT0
- bool "Synchronous serial port 0 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL
- help
- Enabled synchronous serial port 0.
-
-config ETRAX_SYNCHRONOUS_SERIAL0_DMA
- bool "Enable DMA on synchronous serial port 0."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT1
- bool "Synchronous serial port 1 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL && (ETRAXFS || ETRAX_ARCH_V10)
- help
- Enabled synchronous serial port 1.
-
-config ETRAX_SYNCHRONOUS_SERIAL1_DMA
- bool "Enable DMA on synchronous serial port 1."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-choice
- prompt "Network LED behavior"
- depends on ETRAX_ETHERNET
- default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
-
-config ETRAX_NETWORK_LED_ON_WHEN_LINK
- bool "LED_on_when_link"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
- bool "LED_on_when_activity"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-endchoice
-
-choice
- prompt "Ser0 DMA out channel"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_DMA6_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT0_NO_DMA_OUT if ETRAX_ARCH_V10
-
-config ETRAX_SERIAL_PORT0_NO_DMA_OUT
- bool "Ser0 uses no DMA for output"
- help
- Do not use DMA for ser0 output.
-
-config ETRAX_SERIAL_PORT0_DMA6_OUT
- bool "Ser0 uses DMA6 for output"
- depends on ETRAXFS
- help
- Enables the DMA6 output channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT0_DMA0_OUT
- bool "Ser0 uses DMA0 for output"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA0 output channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser0 DMA in channel "
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT0_DMA7_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser0.
-
-config ETRAX_SERIAL_PORT0_NO_DMA_IN
- bool "Ser0 uses no DMA for input"
- help
- Do not use DMA for ser0 input.
-
-config ETRAX_SERIAL_PORT0_DMA7_IN
- bool "Ser0 uses DMA7 for input"
- depends on ETRAXFS
- help
- Enables the DMA7 input channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT0_DMA1_IN
- bool "Ser0 uses DMA1 for input"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA1 input channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser1 DMA in channel "
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT1_DMA9_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser1.
-
-config ETRAX_SERIAL_PORT1_NO_DMA_IN
- bool "Ser1 uses no DMA for input"
- help
- Do not use DMA for ser1 input.
-
-config ETRAX_SERIAL_PORT1_DMA5_IN
- bool "Ser1 uses DMA5 for input"
- depends on ETRAX_ARCH_V32
- help
- Enables the DMA5 input channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT1_DMA9_IN
- depends on ETRAX_ARCH_V10
- bool "Ser1 uses DMA9 for input"
-
-endchoice
-
-
-choice
- prompt "Ser1 DMA out channel"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT1_DMA8_OUT if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser1.
-
-config ETRAX_SERIAL_PORT1_NO_DMA_OUT
- bool "Ser1 uses no DMA for output"
- help
- Do not use DMA for ser1 output.
-
-config ETRAX_SERIAL_PORT1_DMA8_OUT
- depends on ETRAX_ARCH_V10
- bool "Ser1 uses DMA8 for output"
-
-config ETRAX_SERIAL_PORT1_DMA4_OUT
- depends on ETRAX_ARCH_V32
- bool "Ser1 uses DMA4 for output"
- help
- Enables the DMA4 output channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser2 DMA out channel"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT2_DMA2_OUT if ETRAX_ARCH_V10
-
-config ETRAX_SERIAL_PORT2_NO_DMA_OUT
- bool "Ser2 uses no DMA for output"
- help
- Do not use DMA for ser2 output.
-
-config ETRAX_SERIAL_PORT2_DMA2_OUT
- bool "Ser2 uses DMA2 for output"
- depends on ETRAXFS || ETRAX_ARCH_V10
- help
- Enables the DMA2 output channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT2_DMA6_OUT
- bool "Ser2 uses DMA6 for output"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA6 output channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser2 DMA in channel"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT2_DMA3_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser2.
-
-config ETRAX_SERIAL_PORT2_NO_DMA_IN
- bool "Ser2 uses no DMA for input"
- help
- Do not use DMA for ser2 input.
-
-config ETRAX_SERIAL_PORT2_DMA3_IN
- bool "Ser2 uses DMA3 for input"
- depends on ETRAXFS || ETRAX_ARCH_V10
- help
- Enables the DMA3 input channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-config ETRAX_SERIAL_PORT2_DMA7_IN
- bool "Ser2 uses DMA7 for input"
- depends on CRIS_MACH_ARTPEC3
- help
- Enables the DMA7 input channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser3 DMA in channel"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_IN if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT3_DMA5_IN if ETRAX_ARCH_V10
- help
- What DMA channel to use for ser3.
-
-config ETRAX_SERIAL_PORT3_NO_DMA_IN
- bool "Ser3 uses no DMA for input"
- help
- Do not use DMA for ser3 input.
-
-config ETRAX_SERIAL_PORT3_DMA5_IN
- depends on ETRAX_ARCH_V10
- bool "DMA 5"
-
-endchoice
-
-choice
- prompt "Ser3 DMA out channel"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_OUT if ETRAX_ARCH_V32
- default ETRAX_SERIAL_PORT3_DMA4_OUT if ETRAX_ARCH_V10
-
-config ETRAX_SERIAL_PORT3_NO_DMA_OUT
- bool "Ser3 uses no DMA for output"
- help
- Do not use DMA for ser3 output.
-
-config ETRAX_SERIAL_PORT3_DMA4_OUT
- depends on ETRAX_ARCH_V10
- bool "DMA 4"
-
-endchoice
-
-endmenu
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/cris/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/cris/Kconfig.debug b/arch/cris/Kconfig.debug
deleted file mode 100644
index 6084d5e0c512..000000000000
--- a/arch/cris/Kconfig.debug
+++ /dev/null
@@ -1,41 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-config PROFILING
- bool "Kernel profiling support"
-
-config SYSTEM_PROFILER
- bool "System profiling support"
-
-source "lib/Kconfig.debug"
-
-config ETRAX_KGDB
- bool "Use kernel GDB debugger"
- depends on DEBUG_KERNEL
- ---help---
- The CRIS version of gdb can be used to remotely debug a running
- Linux kernel via the serial debug port. Provided you have gdb-cris
- installed, run gdb-cris vmlinux, then type
-
- (gdb) set remotebaud 115200 <- kgdb uses 115200 as default
- (gdb) target remote /dev/ttyS0 <- maybe you use another port
-
- This should connect you to your booted kernel (or boot it now if you
- didn't before). The kernel halts when it boots, waiting for gdb if
- this option is turned on!
-
-
-config DEBUG_NMI_OOPS
- bool "NMI causes oops printout"
- depends on DEBUG_KERNEL
- help
- If the system locks up without any debug information you can say Y
- here to make it possible to dump an OOPS with an external NMI.
-
-config NO_SEGFAULT_TERMINATION
- bool "Keep segfaulting processes"
- help
- Place segfaulting user mode processes on a wait queue instead of
- delivering a terminating SIGSEGV to allow debugging with gdb.
-
-endmenu
diff --git a/arch/cris/Makefile b/arch/cris/Makefile
deleted file mode 100644
index 4a5404b3d0e4..000000000000
--- a/arch/cris/Makefile
+++ /dev/null
@@ -1,104 +0,0 @@
-#
-# cris/Makefile
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies. Remember to do have actions
-# for "archclean" and "archdep" for cleaning up and making dependencies for
-# this architecture
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-
-KBUILD_DEFCONFIG := etrax-100lx_v2_defconfig
-
-arch-y := v10
-arch-$(CONFIG_ETRAX_ARCH_V10) := v10
-arch-$(CONFIG_ETRAX_ARCH_V32) := v32
-
-# No config available for make clean etc
-mach-y := fs
-mach-$(CONFIG_CRIS_MACH_ARTPEC3) := a3
-mach-$(CONFIG_ETRAXFS) := fs
-
-ifneq ($(arch-y),)
-SARCH := arch-$(arch-y)
-inc := -Iarch/cris/include/uapi/$(SARCH)
-inc += -Iarch/cris/include/$(SARCH)
-inc += -Iarch/cris/include/uapi/$(SARCH)/arch
-inc += -Iarch/cris/include/$(SARCH)/arch
-else
-SARCH :=
-inc :=
-endif
-
-ifneq ($(mach-y),)
-MACH := mach-$(mach-y)
-inc += -Iarch/cris/include/$(SARCH)/$(MACH)/
-inc += -Iarch/cris/include/$(SARCH)/$(MACH)/mach
-else
-MACH :=
-endif
-
-ifneq ($(CONFIG_BUILTIN_DTB),"")
-core-$(CONFIG_OF) += arch/cris/boot/dts/
-endif
-
-LD = $(CROSS_COMPILE)ld -mcrislinux
-
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-
-KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc)
-KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc)
-KBUILD_CPPFLAGS += $(inc)
-
-ifdef CONFIG_FRAME_POINTER
-KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g
-KBUILD_CFLAGS += -fno-omit-frame-pointer
-endif
-
-head-y := arch/cris/$(SARCH)/kernel/head.o
-
-LIBGCC = $(shell $(CC) $(KBUILD_CFLAGS) -print-file-name=libgcc.a)
-
-core-y += arch/cris/kernel/ arch/cris/mm/
-core-y += arch/cris/$(SARCH)/kernel/ arch/cris/$(SARCH)/mm/
-ifdef CONFIG_ETRAX_ARCH_V32
-core-y += arch/cris/$(SARCH)/$(MACH)/
-endif
-drivers-y += arch/cris/$(SARCH)/drivers/
-libs-y += arch/cris/$(SARCH)/lib/ $(LIBGCC)
-
-# cris source path
-SRC_ARCH = $(srctree)/arch/cris
-# cris object files path
-OBJ_ARCH = $(objtree)/arch/cris
-
-boot := arch/cris/boot
-MACHINE := arch/cris/$(SARCH)
-
-all: zImage
-
-zImage Image: vmlinux
- $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
-
-archprepare:
-
-archclean:
- $(Q)if [ -e arch/cris/boot ]; then \
- $(MAKE) $(clean)=arch/cris/boot; \
- fi
-
-CLEAN_FILES += \
- $(boot)/zImage \
- $(boot)/compressed/decompress.bin \
- $(boot)/compressed/piggy.gz \
- $(boot)/rescue/rescue.bin
-
-
-# MRPROPER_FILES +=
-
-define archhelp
- echo '* zImage - Compressed kernel image (arch/cris/boot/zImage)'
- echo '* Image - Uncompressed kernel image (arch/cris/boot/Image)'
-endef
diff --git a/arch/cris/arch-v10/Kconfig b/arch/cris/arch-v10/Kconfig
deleted file mode 100644
index d4015a931374..000000000000
--- a/arch/cris/arch-v10/Kconfig
+++ /dev/null
@@ -1,399 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V10
-
-menu "CRIS v10 options"
-
-# ETRAX 100LX v1 has a MMU "feature" requiring a low mapping
-config CRIS_LOW_MAP
- bool
- depends on ETRAX_ARCH_V10 && ETRAX100LX
- default y
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- depends on ETRAX_ARCH_V10
- default "c0000000" if !ETRAX100LX
- default "60000000" if ETRAX100LX
-
-choice
- prompt "Product LED port"
- depends on ETRAX_ARCH_V10
- default ETRAX_PA_LEDS
-
-config ETRAX_PA_LEDS
- bool "Port-PA-LEDs"
- help
- The ETRAX network driver is responsible for flashing LED's when
- packets arrive and are sent. It uses macros defined in
- <file:arch/cris/include/asm/io.h>, and those macros are defined after
- what YOU choose in this option. The actual bits used are configured
- separately. Select this if the LEDs are on port PA. Some products
- put the leds on PB or a memory-mapped latch (CSP0) instead.
-
-config ETRAX_PB_LEDS
- bool "Port-PB-LEDs"
- help
- The ETRAX network driver is responsible for flashing LED's when
- packets arrive and are sent. It uses macros defined in
- <file:arch/cris/include/asm/io.h>, and those macros are defined after
- what YOU choose in this option. The actual bits used are configured
- separately. Select this if the LEDs are on port PB. Some products
- put the leds on PA or a memory-mapped latch (CSP0) instead.
-
-config ETRAX_CSP0_LEDS
- bool "Port-CSP0-LEDs"
- help
- The ETRAX network driver is responsible for flashing LED's when
- packets arrive and are sent. It uses macros defined in
- <file:arch/cris/include/asm/io.h>, and those macros are defined after
- what YOU choose in this option. The actual bits used are configured
- separately. Select this if the LEDs are on a memory-mapped latch
- using chip select CSP0, this is mapped at 0x90000000.
- Some products put the leds on PA or PB instead.
-
-config ETRAX_NO_LEDS
- bool "None"
- help
- Select this option if you don't have any LED at all.
-
-endchoice
-
-config ETRAX_LED1G
- int "First green LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "2"
- help
- Bit to use for the first green LED.
- Most Axis products use bit 2 here.
-
-config ETRAX_LED1R
- int "First red LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "3"
- help
- Bit to use for the first red LED.
- Most Axis products use bit 3 here.
- For products with only one controllable LED,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED2G
- int "Second green LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "4"
- help
- Bit to use for the second green LED. The "Active" LED.
- Most Axis products use bit 4 here.
- For products with only one controllable LED,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED2R
- int "Second red LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "5"
- help
- Bit to use for the second red LED.
- Most Axis products use bit 5 here.
- For products with only one controllable LED,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED3G
- int "Third green LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "2"
- help
- Bit to use for the third green LED. The "Drive" LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED3R
- int "Third red LED bit"
- depends on ETRAX_ARCH_V10 && !ETRAX_NO_LEDS
- default "2"
- help
- Bit to use for the third red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED4R
- int "Fourth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fourth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED4G
- int "Fourth green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fourth green LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED5R
- int "Fifth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fifth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED5G
- int "Fifth green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the fifth green LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED6R
- int "Sixth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the sixth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED6G
- int "Sixth green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the sixth green LED. The "Drive" LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED7R
- int "Seventh red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the seventh red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED7G
- int "Seventh green LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the seventh green LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED8Y
- int "Eighth yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the eighth yellow LED. The "Drive" LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED9Y
- int "Ninth yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the ninth yellow LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED10Y
- int "Tenth yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the tenth yellow LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED11Y
- int "Eleventh yellow LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the eleventh yellow LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-config ETRAX_LED12R
- int "Twelfth red LED bit"
- depends on ETRAX_CSP0_LEDS
- default "2"
- help
- Bit to use for the twelfth red LED.
- For products with only one or two controllable LEDs,
- set this to same as CONFIG_ETRAX_LED1G (normally 2).
-
-
-choice
- prompt "Product rescue-port"
- depends on ETRAX_ARCH_V10
- default ETRAX_RESCUE_SER0
-
-config ETRAX_RESCUE_SER0
- bool "Serial-0"
- help
- Select one of the four serial ports as a rescue port. The default
- is port 0.
-
-config ETRAX_RESCUE_SER1
- bool "Serial-1"
- help
- Use serial port 1 as the rescue port.
-
-config ETRAX_RESCUE_SER2
- bool "Serial-2"
- help
- Use serial port 2 as the rescue port.
-
-config ETRAX_RESCUE_SER3
- bool "Serial-3"
- help
- Use serial port 3 as the rescue port.
-
-endchoice
-
-config ETRAX_DEF_R_WAITSTATES
- hex "R_WAITSTATES"
- depends on ETRAX_ARCH_V10
- default "95a6"
- help
- Waitstates for SRAM, Flash and peripherals (not DRAM). 95f8 is a
- good choice for most Axis products...
-
-config ETRAX_DEF_R_BUS_CONFIG
- hex "R_BUS_CONFIG"
- depends on ETRAX_ARCH_V10
- default "104"
- help
- Assorted bits controlling write mode, DMA burst length etc. 104 is
- a good choice for most Axis products...
-
-config ETRAX_SDRAM
- bool "SDRAM support"
- depends on ETRAX_ARCH_V10
- help
- Enable this if you use SDRAM chips and configure
- R_SDRAM_CONFIG and R_SDRAM_TIMING as well.
-
-config ETRAX_DEF_R_DRAM_CONFIG
- hex "R_DRAM_CONFIG"
- depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM
- default "1a200040"
- help
- The R_DRAM_CONFIG register specifies everything on how the DRAM
- chips in the system are connected to the ETRAX CPU. This is
- different depending on the manufacturer, chip type and number of
- chips. So this value often needs to be different for each Axis
- product.
-
-config ETRAX_DEF_R_DRAM_TIMING
- hex "R_DRAM_TIMING"
- depends on ETRAX_ARCH_V10 && !ETRAX_SDRAM
- default "5611"
- help
- Different DRAM chips have different speeds. Current Axis products
- use 50ns DRAM chips which can use the timing: 5611.
-
-config ETRAX_DEF_R_SDRAM_CONFIG
- hex "R_SDRAM_CONFIG"
- depends on ETRAX_ARCH_V10 && ETRAX_SDRAM
- default "d2fa7878"
- help
- The R_SDRAM_CONFIG register specifies everything on how the SDRAM
- chips in the system are connected to the ETRAX CPU. This is
- different depending on the manufacturer, chip type and number of
- chips. So this value often needs to be different for each Axis
- product.
-
-config ETRAX_DEF_R_SDRAM_TIMING
- hex "R_SDRAM_TIMING"
- depends on ETRAX_ARCH_V10 && ETRAX_SDRAM
- default "80004801"
- help
- Different SDRAM chips have different timing.
-
-config ETRAX_DEF_R_PORT_PA_DIR
- hex "R_PORT_PA_DIR"
- depends on ETRAX_ARCH_V10
- default "1c"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_R_PORT_PA_DATA
- hex "R_PORT_PA_DATA"
- depends on ETRAX_ARCH_V10
- default "00"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_R_PORT_PB_CONFIG
- hex "R_PORT_PB_CONFIG"
- depends on ETRAX_ARCH_V10
- default "00"
- help
- Configures the type of the general port B bits. 1 is chip select,
- 0 is port. Most products should use 00 here.
-
-config ETRAX_DEF_R_PORT_PB_DIR
- hex "R_PORT_PB_DIR"
- depends on ETRAX_ARCH_V10
- default "00"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used. Bits
- 0 and 1 on port PB are usually used for I2C communication, but the
- kernel I2C driver sets the appropriate directions itself so you
- don't need to take that into consideration when setting this option.
- If you don't know what to use, it is always safe to put all as
- inputs.
-
-config ETRAX_DEF_R_PORT_PB_DATA
- hex "R_PORT_PB_DATA"
- depends on ETRAX_ARCH_V10
- default "ff"
- help
- Configures the initial data for the general port A bits. Most
- products should use FF here.
-
-config ETRAX_SOFT_SHUTDOWN
- bool "Software Shutdown Support"
- depends on ETRAX_ARCH_V10
- help
- Enable this if ETRAX is used with a power-supply that can be turned
- off and on with PS_ON signal. Gives the possibility to detect
- powerbutton and then do a power off after unmounting disks.
-
-config ETRAX_SHUTDOWN_BIT
- int "Shutdown bit on port CSP0"
- depends on ETRAX_SOFT_SHUTDOWN
- default "12"
- help
- Configure what pin on CSPO-port that is used for controlling power
- supply.
-
-config ETRAX_POWERBUTTON_BIT
- int "Power button bit on port G"
- depends on ETRAX_SOFT_SHUTDOWN
- default "25"
- help
- Configure where power button is connected.
-
-endmenu
-
-endif
diff --git a/arch/cris/arch-v10/README.mm b/arch/cris/arch-v10/README.mm
deleted file mode 100644
index 67731d75cb51..000000000000
--- a/arch/cris/arch-v10/README.mm
+++ /dev/null
@@ -1,244 +0,0 @@
-Memory management for CRIS/MMU
-------------------------------
-HISTORY:
-
-$Log: README.mm,v $
-Revision 1.1 2001/12/17 13:59:27 bjornw
-Initial revision
-
-Revision 1.1 2000/07/10 16:25:21 bjornw
-Initial revision
-
-Revision 1.4 2000/01/17 02:31:59 bjornw
-Added discussion of paging and VM.
-
-Revision 1.3 1999/12/03 16:43:23 hp
-Blurb about that the 3.5G-limitation is not a MMU limitation
-
-Revision 1.2 1999/12/03 16:04:21 hp
-Picky comment about not mapping the first page
-
-Revision 1.1 1999/12/03 15:41:30 bjornw
-First version of CRIS/MMU memory layout specification.
-
-
-
-
-
-------------------------------
-
-See the ETRAX-NG HSDD for reference.
-
-We use the page-size of 8 kbytes, as opposed to the i386 page-size of 4 kbytes.
-
-The MMU can, apart from the normal mapping of pages, also do a top-level
-segmentation of the kernel memory space. We use this feature to avoid having
-to use page-tables to map the physical memory into the kernel's address
-space. We also use it to keep the user-mode virtual mapping in the same
-map during kernel-mode, so that the kernel easily can access the corresponding
-user-mode process' data.
-
-As a comparison, the Linux/i386 2.0 puts the kernel and physical RAM at
-address 0, overlapping with the user-mode virtual space, so that descriptor
-registers are needed for each memory access to specify which MMU space to
-map through. That changed in 2.2, putting the kernel/physical RAM at
-0xc0000000, to co-exist with the user-mode mapping. We will do something
-quite similar, but with the additional complexity of having to map the
-internal chip I/O registers and the flash memory area (including SRAM
-and peripherial chip-selets).
-
-The kernel-mode segmentation map:
-
- ------------------------ ------------------------
-FFFFFFFF| | => cached | |
- | kernel seg_f | flash | |
-F0000000|______________________| | |
-EFFFFFFF| | => uncached | |
- | kernel seg_e | flash | |
-E0000000|______________________| | DRAM |
-DFFFFFFF| | paged to any | Un-cached |
- | kernel seg_d | =======> | |
-D0000000|______________________| | |
-CFFFFFFF| | | |
- | kernel seg_c |==\ | |
-C0000000|______________________| \ |______________________|
-BFFFFFFF| | uncached | |
- | kernel seg_b |=====\=========>| Registers |
-B0000000|______________________| \c |______________________|
-AFFFFFFF| | \a | |
- | | \c | FLASH/SRAM/Peripheral|
- | | \h |______________________|
- | | \e | |
- | | \d | |
- | kernel seg_0 - seg_a | \==>| DRAM |
- | | | Cached |
- | | paged to any | |
- | | =======> |______________________|
- | | | |
- | | | Illegal |
- | | |______________________|
- | | | |
- | | | FLASH/SRAM/Peripheral|
-00000000|______________________| |______________________|
-
-In user-mode it looks the same except that only the space 0-AFFFFFFF is
-available. Therefore, in this model, the virtual address space per process
-is limited to 0xb0000000 bytes (minus 8192 bytes, since the first page,
-0..8191, is never mapped, in order to trap NULL references).
-
-It also means that the total physical RAM that can be mapped is 256 MB
-(kseg_c above). More RAM can be mapped by choosing a different segmentation
-and shrinking the user-mode memory space.
-
-The MMU can map all 4 GB in user mode, but doing that would mean that a
-few extra instructions would be needed for each access to user mode
-memory.
-
-The kernel needs access to both cached and uncached flash. Uncached is
-necessary because of the special write/erase sequences. Also, the
-peripherial chip-selects are decoded from that region.
-
-The kernel also needs its own virtual memory space. That is kseg_d. It
-is used by the vmalloc() kernel function to allocate virtual contiguous
-chunks of memory not possible using the normal kmalloc physical RAM
-allocator.
-
-The setting of the actual MMU control registers to use this layout would
-be something like this:
-
-R_MMU_KSEG = ( ( seg_f, seg ) | // Flash cached
- ( seg_e, seg ) | // Flash uncached
- ( seg_d, page ) | // kernel vmalloc area
- ( seg_c, seg ) | // kernel linear segment
- ( seg_b, seg ) | // kernel linear segment
- ( seg_a, page ) |
- ( seg_9, page ) |
- ( seg_8, page ) |
- ( seg_7, page ) |
- ( seg_6, page ) |
- ( seg_5, page ) |
- ( seg_4, page ) |
- ( seg_3, page ) |
- ( seg_2, page ) |
- ( seg_1, page ) |
- ( seg_0, page ) );
-
-R_MMU_KBASE_HI = ( ( base_f, 0x0 ) | // flash/sram/periph cached
- ( base_e, 0x8 ) | // flash/sram/periph uncached
- ( base_d, 0x0 ) | // don't care
- ( base_c, 0x4 ) | // physical RAM cached area
- ( base_b, 0xb ) | // uncached on-chip registers
- ( base_a, 0x0 ) | // don't care
- ( base_9, 0x0 ) | // don't care
- ( base_8, 0x0 ) ); // don't care
-
-R_MMU_KBASE_LO = ( ( base_7, 0x0 ) | // don't care
- ( base_6, 0x0 ) | // don't care
- ( base_5, 0x0 ) | // don't care
- ( base_4, 0x0 ) | // don't care
- ( base_3, 0x0 ) | // don't care
- ( base_2, 0x0 ) | // don't care
- ( base_1, 0x0 ) | // don't care
- ( base_0, 0x0 ) ); // don't care
-
-NOTE: while setting up the MMU, we run in a non-mapped mode in the DRAM (0x40
-segment) and need to setup the seg_4 to a unity mapping, so that we don't get
-a fault before we have had time to jump into the real kernel segment (0xc0). This
-is done in head.S temporarily, but fixed by the kernel later in paging_init.
-
-
-Paging - PTE's, PMD's and PGD's
--------------------------------
-
-[ References: asm/pgtable.h, asm/page.h, asm/mmu.h ]
-
-The paging mechanism uses virtual addresses to split a process memory-space into
-pages, a page being the smallest unit that can be freely remapped in memory. On
-Linux/CRIS, a page is 8192 bytes (for technical reasons not equal to 4096 as in
-most other 32-bit architectures). It would be inefficient to let a virtual memory
-mapping be controlled by a long table of page mappings, so it is broken down into
-a 2-level structure with a Page Directory containing pointers to Page Tables which
-each have maps of up to 2048 pages (8192 / sizeof(void *)). Linux can actually
-handle 3-level structures as well, with a Page Middle Directory in between, but
-in many cases, this is folded into a two-level structure by excluding the Middle
-Directory.
-
-We'll take a look at how an address is translated while we discuss how it's handled
-in the Linux kernel.
-
-The example address is 0xd004000c; in binary this is:
-
-31 23 15 7 0
-11010000 00000100 00000000 00001100
-
-|______| |__________||____________|
- PGD PTE page offset
-
-Given the top-level Page Directory, the offset in that directory is calculated
-using the upper 8 bits:
-
-static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address)
-{
- return mm->pgd + (address >> PGDIR_SHIFT);
-}
-
-PGDIR_SHIFT is the log2 of the amount of memory an entry in the PGD can map; in our
-case it is 24, corresponding to 16 MB. This means that each entry in the PGD
-corresponds to 16 MB of virtual memory.
-
-The pgd_t from our example will therefore be the 208'th (0xd0) entry in mm->pgd.
-
-Since the Middle Directory does not exist, it is a unity mapping:
-
-static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
- return (pmd_t *) dir;
-}
-
-The Page Table provides the final lookup by using bits 13 to 23 as index:
-
-static inline pte_t * pte_offset(pmd_t * dir, unsigned long address)
-{
- return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) &
- (PTRS_PER_PTE - 1));
-}
-
-PAGE_SHIFT is the log2 of the size of a page; 13 in our case. PTRS_PER_PTE is
-the number of pointers that fit in a Page Table and is used to mask off the
-PGD-part of the address.
-
-The so-far unused bits 0 to 12 are used to index inside a page linearily.
-
-The VM system
--------------
-
-The kernels own page-directory is the swapper_pg_dir, cleared in paging_init,
-and contains the kernels virtual mappings (the kernel itself is not paged - it
-is mapped linearily using kseg_c as described above). Architectures without
-kernel segments like the i386, need to setup swapper_pg_dir directly in head.S
-to map the kernel itself. swapper_pg_dir is pointed to by init_mm.pgd as the
-init-task's PGD.
-
-To see what support functions are used to setup a page-table, let's look at the
-kernel's internal paged memory system, vmalloc/vfree.
-
-void * vmalloc(unsigned long size)
-
-The vmalloc-system keeps a paged segment in kernel-space at 0xd0000000. What
-happens first is that a virtual address chunk is allocated to the request using
-get_vm_area(size). After that, physical RAM pages are allocated and put into
-the kernel's page-table using alloc_area_pages(addr, size).
-
-static int alloc_area_pages(unsigned long address, unsigned long size)
-
-First the PGD entry is found using init_mm.pgd. This is passed to
-alloc_area_pmd (remember the 3->2 folding). It uses pte_alloc_kernel to
-check if the PGD entry points anywhere - if not, a page table page is
-allocated and the PGD entry updated. Then the alloc_area_pte function is
-used just like alloc_area_pmd to check which page table entry is desired,
-and a physical page is allocated and the table entry updated. All of this
-is repeated at the top-level until the entire address range specified has
-been mapped.
-
-
-
diff --git a/arch/cris/arch-v10/drivers/Kconfig b/arch/cris/arch-v10/drivers/Kconfig
deleted file mode 100644
index 8792af63c049..000000000000
--- a/arch/cris/arch-v10/drivers/Kconfig
+++ /dev/null
@@ -1,561 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V10
-
-config ETRAX_ETHERNET
- bool "Ethernet support"
- depends on ETRAX_ARCH_V10 && NETDEVICES
- select MII
- help
- This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
- controller.
-
-config ETRAX_SERIAL
- bool "Serial-port support"
- depends on ETRAX_ARCH_V10
- help
- Enables the ETRAX 100 serial driver for ser0 (ttyS0)
- You probably want this enabled.
-
-config ETRAX_SERIAL_FAST_TIMER
- bool "Use fast timers for serial DMA flush (experimental)"
- depends on ETRAX_SERIAL
- help
- Select this to have the serial DMAs flushed at a higher rate than
- normally, possible by using the fast timer API, the timeout is
- approx. 4 character times.
- If unsure, say N.
-
-config ETRAX_SERIAL_FLUSH_DMA_FAST
- bool "Fast serial port DMA flush"
- depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER
- help
- Select this to have the serial DMAs flushed at a higher rate than
- normally possible through a fast timer interrupt (currently at
- 15360 Hz).
- If unsure, say N.
-
-config ETRAX_SERIAL_RX_TIMEOUT_TICKS
- int "Receive flush timeout (ticks) "
- depends on ETRAX_SERIAL && !ETRAX_SERIAL_FAST_TIMER && !ETRAX_SERIAL_FLUSH_DMA_FAST
- default "5"
- help
- Number of timer ticks between flush of receive fifo (1 tick = 10ms).
- Try 0-3 for low latency applications. Approx 5 for high load
- applications (e.g. PPP). Maybe this should be more adaptive some
- day...
-
-config ETRAX_SERIAL_PORT0
- bool "Serial port 0 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser0 (ttyS0)
- Normally you want this on, unless you use external DMA 1 that uses
- the same DMA channels.
-
-choice
- prompt "Ser0 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER0_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
-
-config ETRAX_SER0_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
- help
- Enables the status and control signals DTR, RI, DSR and CD on PB for
- ser0.
-
-config ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER0_DTR_ON_PA_BIT
- int "Ser0 DTR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_RI_ON_PA_BIT
- int "Ser0 RI on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_DSR_ON_PA_BIT
- int "Ser0 DSR on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_CD_ON_PA_BIT
- int "Ser0 CD on PA bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PA || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER0_DTR_ON_PB_BIT
- int "Ser0 DTR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DTR signal for serial
- port 0.
-
-config ETRAX_SER0_RI_ON_PB_BIT
- int "Ser0 RI on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the RI signal for serial
- port 0.
-
-config ETRAX_SER0_DSR_ON_PB_BIT
- int "Ser0 DSR on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DSR signal for serial
- port 0.
-
-config ETRAX_SER0_CD_ON_PB_BIT
- int "Ser0 CD on PB bit (-1 = not used)" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT0
- default "-1" if !ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER0_DTR_RI_DSR_CD_ON_PB || ETRAX_SER0_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the CD signal for serial
- port 0.
-
-config ETRAX_SERIAL_PORT1
- bool "Serial port 1 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser1 (ttyS1).
-
-choice
- prompt "Ser1 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER1_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER1_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
-
-config ETRAX_SER1_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
- help
- Enables the status and control signals DTR, RI, DSR and CD on PB for
- ser1.
-
-config ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER1_DTR_ON_PA_BIT
- int "Ser1 DTR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_RI_ON_PA_BIT
- int "Ser1 RI on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_DSR_ON_PA_BIT
- int "Ser1 DSR on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_CD_ON_PA_BIT
- int "Ser1 CD on PA bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PA || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER1_DTR_ON_PB_BIT
- int "Ser1 DTR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DTR signal for serial
- port 1.
-
-config ETRAX_SER1_RI_ON_PB_BIT
- int "Ser1 RI on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the RI signal for serial
- port 1.
-
-config ETRAX_SER1_DSR_ON_PB_BIT
- int "Ser1 DSR on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the DSR signal for serial
- port 1.
-
-config ETRAX_SER1_CD_ON_PB_BIT
- int "Ser1 CD on PB bit (-1 = not used)" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT1
- default "-1" if !ETRAX_SER1_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER1_DTR_RI_DSR_CD_ON_PB || ETRAX_SER1_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PB port to carry the CD signal for serial
- port 1.
-
-comment "Make sure you do not have the same PB bits more than once!"
- depends on ETRAX_SERIAL && ETRAX_SER0_DTR_RI_DSR_CD_ON_PB && ETRAX_SER1_DTR_RI_DSR_CD_ON_PB
-
-config ETRAX_SERIAL_PORT2
- bool "Serial port 2 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser2 (ttyS2).
-
-choice
- prompt "Ser2 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER2_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
- help
- Enables the status and control signals DTR, RI, DSR and CD on PA for
- ser2.
-
-config ETRAX_SER2_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
-
-config ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER2_DTR_ON_PA_BIT
- int "Ser2 DTR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the DTR signal for serial
- port 2.
-
-config ETRAX_SER2_RI_ON_PA_BIT
- int "Ser2 RI on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the RI signal for serial
- port 2.
-
-config ETRAX_SER2_DSR_ON_PA_BIT
- int "Ser2 DSR on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the DTR signal for serial
- port 2.
-
-config ETRAX_SER2_CD_ON_PA_BIT
- int "Ser2 CD on PA bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PA && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PA || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- help
- Specify the pin of the PA port to carry the CD signal for serial
- port 2.
-
-config ETRAX_SER2_DTR_ON_PB_BIT
- int "Ser2 DTR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "4" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER2_RI_ON_PB_BIT
- int "Ser2 RI on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "5" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER2_DSR_ON_PB_BIT
- int "Ser2 DSR on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "6" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SER2_CD_ON_PB_BIT
- int "Ser2 CD on PB bit (-1 = not used)" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT2
- default "-1" if !ETRAX_SER2_DTR_RI_DSR_CD_ON_PB && !ETRAX_SER2_DTR_RI_DSR_CD_MIXED
- default "7" if ETRAX_SER2_DTR_RI_DSR_CD_ON_PB || ETRAX_SER2_DTR_RI_DSR_CD_MIXED
-
-config ETRAX_SERIAL_PORT3
- bool "Serial port 3 enabled"
- depends on ETRAX_SERIAL
- help
- Enables the ETRAX 100 serial driver for ser3 (ttyS3).
-
-choice
- prompt "Ser3 DTR, RI, DSR and CD assignment"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
-
-config ETRAX_SER3_DTR_RI_DSR_CD_ON_NONE
- bool "No_DTR_RI_DSR_CD"
-
-config ETRAX_SER3_DTR_RI_DSR_CD_ON_PA
- bool "DTR_RI_DSR_CD_on_PA"
-
-config ETRAX_SER3_DTR_RI_DSR_CD_ON_PB
- bool "DTR_RI_DSR_CD_on_PB"
-
-config ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- bool "DTR_RI_DSR_CD_mixed_on_PA_and_PB"
-
-endchoice
-
-config ETRAX_SER3_DTR_ON_PA_BIT
- int "Ser3 DTR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_RI_ON_PA_BIT
- int "Ser3 RI on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_DSR_ON_PA_BIT
- int "Ser3 DSR on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_CD_ON_PA_BIT
- int "Ser3 CD on PA bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PA || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_DTR_ON_PB_BIT
- int "Ser3 DTR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_RI_ON_PB_BIT
- int "Ser3 RI on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_DSR_ON_PB_BIT
- int "Ser3 DSR on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_SER3_CD_ON_PB_BIT
- int "Ser3 CD on PB bit (-1 = not used)" if ETRAX_SER3_DTR_RI_DSR_CD_ON_PB || ETRAX_SER3_DTR_RI_DSR_CD_MIXED
- depends on ETRAX_SERIAL_PORT3
- default "-1"
-
-config ETRAX_RS485
- bool "RS-485 support"
- depends on ETRAX_SERIAL
- help
- Enables support for RS-485 serial communication. For a primer on
- RS-485, see <http://en.wikipedia.org/wiki/Rs485>
-
-config ETRAX_RS485_ON_PA
- bool "RS-485 mode on PA"
- depends on ETRAX_RS485
- help
- Control Driver Output Enable on RS485 transceiver using a pin on PA
- port:
- Axis 2400/2401 uses PA 3.
-
-config ETRAX_RS485_ON_PA_BIT
- int "RS-485 mode on PA bit"
- depends on ETRAX_RS485_ON_PA
- default "3"
- help
- Control Driver Output Enable on RS485 transceiver using a this bit
- on PA port.
-
-config ETRAX_RS485_DISABLE_RECEIVER
- bool "Disable serial receiver"
- depends on ETRAX_RS485
- help
- It's necessary to disable the serial receiver to avoid serial
- loopback. Not all products are able to do this in software only.
- Axis 2400/2401 must disable receiver.
-
-config ETRAX_USB_HOST
- bool "USB host"
- select USB
- help
- This option enables the host functionality of the ETRAX 100LX
- built-in USB controller. In host mode the controller is designed
- for CTRL and BULK traffic only, INTR traffic may work as well
- however (depending on the requirements of timeliness).
-
-config ETRAX_PTABLE_SECTOR
- int "Byte-offset of partition table sector"
- depends on ETRAX_AXISFLASHMAP
- default "65536"
- help
- Byte-offset of the partition table in the first flash chip.
- The default value is 64kB and should not be changed unless
- you know exactly what you are doing. The only valid reason
- for changing this is when the flash block size is bigger
- than 64kB (e.g. when using two parallel 16 bit flashes).
-
-config ETRAX_I2C
- bool "I2C support"
- depends on ETRAX_ARCH_V10
- help
- Enables an I2C driver on ETRAX100.
- EXAMPLE usage:
- i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
- ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
- i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
- val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
-
-# this is true for most products since PB-I2C seems to be somewhat
-# flawed..
-config ETRAX_I2C_USES_PB_NOT_PB_I2C
- bool "I2C uses PB not PB-I2C"
- depends on ETRAX_I2C
- help
- Select whether to use the special I2C mode in the PB I/O register or
- not. This option needs to be selected in order to use some drivers
- that access the I2C I/O pins directly instead of going through the
- I2C driver, like the DS1302 realtime-clock driver. If you are
- uncertain, choose Y here.
-
-config ETRAX_I2C_DATA_PORT
- int "I2C SDA bit number"
- depends on ETRAX_I2C_USES_PB_NOT_PB_I2C
- default "0"
- help
- Selects the pin on Port B where the data pin is connected
-
-config ETRAX_I2C_CLK_PORT
- int "I2C SCL bit number"
- depends on ETRAX_I2C_USES_PB_NOT_PB_I2C
- default "1"
- help
- Select the pin on Port B where the clock pin is connected
-
-config ETRAX_I2C_EEPROM
- bool "I2C EEPROM (non-volatile RAM) support"
- depends on ETRAX_I2C
- help
- Enables I2C EEPROM (non-volatile RAM) on PB0 and PB1 using the I2C
- driver. Select size option: Probed, 2k, 8k, 16k.
- (Probing works for 2k and 8k but not that well for 16k)
-
-choice
- prompt "EEPROM size"
- depends on ETRAX_I2C_EEPROM
- default ETRAX_I2C_EEPROM_PROBE
-
-config ETRAX_I2C_EEPROM_PROBE
- bool "Probed"
- help
- Specifies size or auto probe of the EEPROM size.
- Options: Probed, 2k, 8k, 16k.
- (Probing works for 2k and 8k but not that well for 16k)
-
-config ETRAX_I2C_EEPROM_2KB
- bool "2kB"
- help
- Use a 2kB EEPROM.
-
-config ETRAX_I2C_EEPROM_8KB
- bool "8kB"
- help
- Use a 8kB EEPROM.
-
-config ETRAX_I2C_EEPROM_16KB
- bool "16kB"
- help
- Use a 16kB EEPROM.
-
-endchoice
-
-config ETRAX_GPIO
- bool "GPIO support"
- depends on ETRAX_ARCH_V10
- ---help---
- Enables the ETRAX general port device (major 120, minors 0 and 1).
- You can use this driver to access the general port bits. It supports
- these ioctl's:
- #include <linux/etraxgpio.h>
- fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
- ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
- ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
- val = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READBITS), NULL);
- Remember that you need to setup the port directions appropriately in
- the General configuration.
-
-config ETRAX_PA_CHANGEABLE_DIR
- hex "PA user changeable dir mask"
- depends on ETRAX_GPIO
- default "00"
- help
- This is a bitmask with information of what bits in PA that a user
- can change direction on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-config ETRAX_PA_CHANGEABLE_BITS
- hex "PA user changeable bits mask"
- depends on ETRAX_GPIO
- default "FF"
- help
- This is a bitmask with information of what bits in PA that a user
- can change the value on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-config ETRAX_PB_CHANGEABLE_DIR
- hex "PB user changeable dir mask"
- depends on ETRAX_GPIO
- default "00"
- help
- This is a bitmask with information of what bits in PB that a user
- can change direction on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-config ETRAX_PB_CHANGEABLE_BITS
- hex "PB user changeable bits mask"
- depends on ETRAX_GPIO
- default "FF"
- help
- This is a bitmask with information of what bits in PB that a user
- can change the value on using ioctl's.
- Bit set = changeable.
- You probably want 00 here.
-
-endif
diff --git a/arch/cris/arch-v10/drivers/Makefile b/arch/cris/arch-v10/drivers/Makefile
deleted file mode 100644
index d5549dca81bf..000000000000
--- a/arch/cris/arch-v10/drivers/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
-obj-$(CONFIG_ETRAX_I2C) += i2c.o
-obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o
-obj-$(CONFIG_ETRAX_GPIO) += gpio.o
-obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
-
diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c
deleted file mode 100644
index 28292da49664..000000000000
--- a/arch/cris/arch-v10/drivers/axisflashmap.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * Physical mapping layer for MTD using the Axis partitiontable format
- *
- * Copyright (c) 2001, 2002 Axis Communications AB
- *
- * This file is under the GPL.
- *
- * First partition is always sector 0 regardless of if we find a partitiontable
- * or not. In the start of the next sector, there can be a partitiontable that
- * tells us what other partitions to define. If there isn't, we use a default
- * partition split defined below.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-
-#include <linux/mtd/concat.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/mtdram.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/axisflashmap.h>
-#include <asm/mmu.h>
-#include <arch/sv_addr_ag.h>
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define FLASH_UNCACHED_ADDR KSEG_8
-#define FLASH_CACHED_ADDR KSEG_5
-#else
-#define FLASH_UNCACHED_ADDR KSEG_E
-#define FLASH_CACHED_ADDR KSEG_F
-#endif
-
-#if CONFIG_ETRAX_FLASH_BUSWIDTH==1
-#define flash_data __u8
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
-#define flash_data __u16
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
-#define flash_data __u32
-#endif
-
-/* From head.S */
-extern unsigned long romfs_start, romfs_length, romfs_in_flash;
-
-/* The master mtd for the entire flash. */
-struct mtd_info* axisflash_mtd = NULL;
-
-/* Map driver functions. */
-
-static map_word flash_read(struct map_info *map, unsigned long ofs)
-{
- map_word tmp;
- tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs);
- return tmp;
-}
-
-static void flash_copy_from(struct map_info *map, void *to,
- unsigned long from, ssize_t len)
-{
- memcpy(to, (void *)(map->map_priv_1 + from), len);
-}
-
-static void flash_write(struct map_info *map, map_word d, unsigned long adr)
-{
- *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0];
-}
-
-/*
- * The map for chip select e0.
- *
- * We run into tricky coherence situations if we mix cached with uncached
- * accesses to we only use the uncached version here.
- *
- * The size field is the total size where the flash chips may be mapped on the
- * chip select. MTD probes should find all devices there and it does not matter
- * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD
- * probes will ignore them.
- *
- * The start address in map_priv_1 is in virtual memory so we cannot use
- * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start
- * address of cse0.
- */
-static struct map_info map_cse0 = {
- .name = "cse0",
- .size = MEM_CSE0_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR
-};
-
-/*
- * The map for chip select e1.
- *
- * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong
- * address, but there isn't.
- */
-static struct map_info map_cse1 = {
- .name = "cse1",
- .size = MEM_CSE1_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE
-};
-
-/* If no partition-table was found, we use this default-set. */
-#define MAX_PARTITIONS 7
-#define NUM_DEFAULT_PARTITIONS 3
-
-/*
- * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the
- * size of one flash block and "filesystem"-partition needs 5 blocks to be able
- * to use JFFS.
- */
-static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
- {
- .name = "boot firmware",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "kernel",
- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR),
- .offset = CONFIG_ETRAX_PTABLE_SECTOR
- },
- {
- .name = "filesystem",
- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR)
- }
-};
-
-/* Initialize the ones normally used. */
-static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
- {
- .name = "part0",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "part1",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part2",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part3",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part4",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part5",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part6",
- .size = 0,
- .offset = 0
- },
-};
-
-/*
- * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
- * chips in that order (because the amd_flash-driver is faster).
- */
-static struct mtd_info *probe_cs(struct map_info *map_cs)
-{
- struct mtd_info *mtd_cs = NULL;
-
- printk(KERN_INFO
- "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n",
- map_cs->name, map_cs->size, map_cs->map_priv_1);
-
-#ifdef CONFIG_MTD_CFI
- mtd_cs = do_map_probe("cfi_probe", map_cs);
-#endif
-#ifdef CONFIG_MTD_JEDECPROBE
- if (!mtd_cs)
- mtd_cs = do_map_probe("jedec_probe", map_cs);
-#endif
-
- return mtd_cs;
-}
-
-/*
- * Probe each chip select individually for flash chips. If there are chips on
- * both cse0 and cse1, the mtd_info structs will be concatenated to one struct
- * so that MTD partitions can cross chip boundaries.
- *
- * The only known restriction to how you can mount your chips is that each
- * chip select must hold similar flash chips. But you need external hardware
- * to do that anyway and you can put totally different chips on cse0 and cse1
- * so it isn't really much of a restriction.
- */
-static struct mtd_info *flash_probe(void)
-{
- struct mtd_info *mtd_cse0;
- struct mtd_info *mtd_cse1;
- struct mtd_info *mtd_cse;
-
- mtd_cse0 = probe_cs(&map_cse0);
- mtd_cse1 = probe_cs(&map_cse1);
-
- if (!mtd_cse0 && !mtd_cse1) {
- /* No chip found. */
- return NULL;
- }
-
- if (mtd_cse0 && mtd_cse1) {
- struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 };
-
- /* Since the concatenation layer adds a small overhead we
- * could try to figure out if the chips in cse0 and cse1 are
- * identical and reprobe the whole cse0+cse1 window. But since
- * flash chips are slow, the overhead is relatively small.
- * So we use the MTD concatenation layer instead of further
- * complicating the probing procedure.
- */
- mtd_cse = mtd_concat_create(mtds, ARRAY_SIZE(mtds),
- "cse0+cse1");
- if (!mtd_cse) {
- printk(KERN_ERR "%s and %s: Concatenation failed!\n",
- map_cse0.name, map_cse1.name);
-
- /* The best we can do now is to only use what we found
- * at cse0.
- */
- mtd_cse = mtd_cse0;
- map_destroy(mtd_cse1);
- }
- } else {
- mtd_cse = mtd_cse0? mtd_cse0 : mtd_cse1;
- }
-
- return mtd_cse;
-}
-
-/*
- * Probe the flash chip(s) and, if it succeeds, read the partition-table
- * and register the partitions with MTD.
- */
-static int __init init_axis_flash(void)
-{
- struct mtd_info *mymtd;
- int err = 0;
- int pidx = 0;
- struct partitiontable_head *ptable_head = NULL;
- struct partitiontable_entry *ptable;
- int use_default_ptable = 1; /* Until proven otherwise. */
- const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n";
-
- if (!(mymtd = flash_probe())) {
- /* There's no reason to use this module if no flash chip can
- * be identified. Make sure that's understood.
- */
- printk(KERN_INFO "axisflashmap: Found no flash chip.\n");
- } else {
- printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n",
- mymtd->name, mymtd->size);
- axisflash_mtd = mymtd;
- }
-
- if (mymtd) {
- mymtd->owner = THIS_MODULE;
- ptable_head = (struct partitiontable_head *)(FLASH_CACHED_ADDR +
- CONFIG_ETRAX_PTABLE_SECTOR +
- PARTITION_TABLE_OFFSET);
- }
- pidx++; /* First partition is always set to the default. */
-
- if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC)
- && (ptable_head->size <
- (MAX_PARTITIONS * sizeof(struct partitiontable_entry) +
- PARTITIONTABLE_END_MARKER_SIZE))
- && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) +
- ptable_head->size -
- PARTITIONTABLE_END_MARKER_SIZE)
- == PARTITIONTABLE_END_MARKER)) {
- /* Looks like a start, sane length and end of a
- * partition table, lets check csum etc.
- */
- int ptable_ok = 0;
- struct partitiontable_entry *max_addr =
- (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head) +
- ptable_head->size);
- unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
- unsigned char *p;
- unsigned long csum = 0;
-
- ptable = (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head));
-
- /* Lets be PARANOID, and check the checksum. */
- p = (unsigned char*) ptable;
-
- while (p <= (unsigned char*)max_addr) {
- csum += *p++;
- csum += *p++;
- csum += *p++;
- csum += *p++;
- }
- ptable_ok = (csum == ptable_head->checksum);
-
- /* Read the entries and use/show the info. */
- printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n",
- (ptable_ok ? " valid" : "n invalid"), ptable_head,
- max_addr);
-
- /* We have found a working bootblock. Now read the
- * partition table. Scan the table. It ends when
- * there is 0xffffffff, that is, empty flash.
- */
- while (ptable_ok
- && ptable->offset != 0xffffffff
- && ptable < max_addr
- && pidx < MAX_PARTITIONS) {
-
- axis_partitions[pidx].offset = offset + ptable->offset;
- axis_partitions[pidx].size = ptable->size;
-
- printk(pmsg, pidx, axis_partitions[pidx].offset,
- axis_partitions[pidx].size);
- pidx++;
- ptable++;
- }
- use_default_ptable = !ptable_ok;
- }
-
- if (romfs_in_flash) {
- /* Add an overlapping device for the root partition (romfs). */
-
- axis_partitions[pidx].name = "romfs";
- axis_partitions[pidx].size = romfs_length;
- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE;
-
- printk(KERN_INFO
- " Adding readonly flash partition for romfs image:\n");
- printk(pmsg, pidx, axis_partitions[pidx].offset,
- axis_partitions[pidx].size);
- pidx++;
- }
-
- if (mymtd) {
- if (use_default_ptable) {
- printk(KERN_INFO " Using default partition table.\n");
- err = mtd_device_register(mymtd,
- axis_default_partitions,
- NUM_DEFAULT_PARTITIONS);
- } else {
- err = mtd_device_register(mymtd, axis_partitions,
- pidx);
- }
-
- if (err)
- panic("axisflashmap could not add MTD partitions!\n");
- }
-
- if (!romfs_in_flash) {
- /* Create an RAM device for the root partition (romfs). */
-
-#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0)
- /* No use trying to boot this kernel from RAM. Panic! */
- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
- "device due to kernel (mis)configuration!\n");
- panic("This kernel cannot boot from RAM!\n");
-#else
- struct mtd_info *mtd_ram;
-
- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
- if (!mtd_ram)
- panic("axisflashmap couldn't allocate memory for "
- "mtd_info!\n");
-
- printk(KERN_INFO " Adding RAM partition for romfs image:\n");
- printk(pmsg, pidx, (unsigned)romfs_start,
- (unsigned)romfs_length);
-
- err = mtdram_init_device(mtd_ram,
- (void *)romfs_start,
- romfs_length,
- "romfs");
- if (err)
- panic("axisflashmap could not initialize MTD RAM "
- "device!\n");
-#endif
- }
- return err;
-}
-
-/* This adds the above to the kernels init-call chain. */
-module_init(init_axis_flash);
-
-EXPORT_SYMBOL(axisflash_mtd);
diff --git a/arch/cris/arch-v10/drivers/eeprom.c b/arch/cris/arch-v10/drivers/eeprom.c
deleted file mode 100644
index 2d312c8a4dd5..000000000000
--- a/arch/cris/arch-v10/drivers/eeprom.c
+++ /dev/null
@@ -1,852 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*!*****************************************************************************
-*!
-*! Implements an interface for i2c compatible eeproms to run under Linux.
-*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by
-*! Johan.Adolfsson@axis.com
-*!
-*! Probing results:
-*! 8k or not is detected (the assumes 2k or 16k)
-*! 2k or 16k detected using test reads and writes.
-*!
-*!------------------------------------------------------------------------
-*! HISTORY
-*!
-*! DATE NAME CHANGES
-*! ---- ---- -------
-*! Aug 28 1999 Edgar Iglesias Initial Version
-*! Aug 31 1999 Edgar Iglesias Allow simultaneous users.
-*! Sep 03 1999 Edgar Iglesias Updated probe.
-*! Sep 03 1999 Edgar Iglesias Added bail-out stuff if we get interrupted
-*! in the spin-lock.
-*!
-*! (c) 1999 Axis Communications AB, Lund, Sweden
-*!*****************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/wait.h>
-#include <linux/uaccess.h>
-#include "i2c.h"
-
-#define D(x)
-
-/* If we should use adaptive timing or not: */
-/* #define EEPROM_ADAPTIVE_TIMING */
-
-#define EEPROM_MAJOR_NR 122 /* use a LOCAL/EXPERIMENTAL major for now */
-#define EEPROM_MINOR_NR 0
-
-/* Empirical sane initial value of the delay, the value will be adapted to
- * what the chip needs when using EEPROM_ADAPTIVE_TIMING.
- */
-#define INITIAL_WRITEDELAY_US 4000
-#define MAX_WRITEDELAY_US 10000 /* 10 ms according to spec for 2KB EEPROM */
-
-/* This one defines how many times to try when eeprom fails. */
-#define EEPROM_RETRIES 10
-
-#define EEPROM_2KB (2 * 1024)
-/*#define EEPROM_4KB (4 * 1024)*/ /* Exists but not used in Axis products */
-#define EEPROM_8KB (8 * 1024 - 1 ) /* Last byte has write protection bit */
-#define EEPROM_16KB (16 * 1024)
-
-#define i2c_delay(x) udelay(x)
-
-/*
- * This structure describes the attached eeprom chip.
- * The values are probed for.
- */
-
-struct eeprom_type
-{
- unsigned long size;
- unsigned long sequential_write_pagesize;
- unsigned char select_cmd;
- unsigned long usec_delay_writecycles; /* Min time between write cycles
- (up to 10ms for some models) */
- unsigned long usec_delay_step; /* For adaptive algorithm */
- int adapt_state; /* 1 = To high , 0 = Even, -1 = To low */
-
- /* this one is to keep the read/write operations atomic */
- struct mutex lock;
- int retry_cnt_addr; /* Used to keep track of number of retries for
- adaptive timing adjustments */
- int retry_cnt_read;
-};
-
-static int eeprom_open(struct inode * inode, struct file * file);
-static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig);
-static ssize_t eeprom_read(struct file * file, char * buf, size_t count,
- loff_t *off);
-static ssize_t eeprom_write(struct file * file, const char * buf, size_t count,
- loff_t *off);
-static int eeprom_close(struct inode * inode, struct file * file);
-
-static int eeprom_address(unsigned long addr);
-static int read_from_eeprom(char * buf, int count);
-static int eeprom_write_buf(loff_t addr, const char * buf, int count);
-static int eeprom_read_buf(loff_t addr, char * buf, int count);
-
-static void eeprom_disable_write_protect(void);
-
-
-static const char eeprom_name[] = "eeprom";
-
-/* chip description */
-static struct eeprom_type eeprom;
-
-/* This is the exported file-operations structure for this device. */
-const struct file_operations eeprom_fops =
-{
- .llseek = eeprom_lseek,
- .read = eeprom_read,
- .write = eeprom_write,
- .open = eeprom_open,
- .release = eeprom_close
-};
-
-/* eeprom init call. Probes for different eeprom models. */
-
-int __init eeprom_init(void)
-{
- mutex_init(&eeprom.lock);
-
-#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE
-#define EETEXT "Found"
-#else
-#define EETEXT "Assuming"
-#endif
- if (register_chrdev(EEPROM_MAJOR_NR, eeprom_name, &eeprom_fops))
- {
- printk(KERN_INFO "%s: unable to get major %d for eeprom device\n",
- eeprom_name, EEPROM_MAJOR_NR);
- return -1;
- }
-
- printk("EEPROM char device v0.3, (c) 2000 Axis Communications AB\n");
-
- /*
- * Note: Most of this probing method was taken from the printserver (5470e)
- * codebase. It did not contain a way of finding the 16kB chips
- * (M24128 or variants). The method used here might not work
- * for all models. If you encounter problems the easiest way
- * is probably to define your model within #ifdef's, and hard-
- * code it.
- */
-
- eeprom.size = 0;
- eeprom.usec_delay_writecycles = INITIAL_WRITEDELAY_US;
- eeprom.usec_delay_step = 128;
- eeprom.adapt_state = 0;
-
-#ifdef CONFIG_ETRAX_I2C_EEPROM_PROBE
- i2c_start();
- i2c_outbyte(0x80);
- if(!i2c_getack())
- {
- /* It's not 8k.. */
- int success = 0;
- unsigned char buf_2k_start[16];
-
- /* Im not sure this will work... :) */
- /* assume 2kB, if failure go for 16kB */
- /* Test with 16kB settings.. */
- /* If it's a 2kB EEPROM and we address it outside it's range
- * it will mirror the address space:
- * 1. We read two locations (that are mirrored),
- * if the content differs * it's a 16kB EEPROM.
- * 2. if it doesn't differ - write different value to one of the locations,
- * check the other - if content still is the same it's a 2k EEPROM,
- * restore original data.
- */
-#define LOC1 8
-#define LOC2 (0x1fb) /*1fb, 3ed, 5df, 7d1 */
-
- /* 2k settings */
- i2c_stop();
- eeprom.size = EEPROM_2KB;
- eeprom.select_cmd = 0xA0;
- eeprom.sequential_write_pagesize = 16;
- if( eeprom_read_buf( 0, buf_2k_start, 16 ) == 16 )
- {
- D(printk("2k start: '%16.16s'\n", buf_2k_start));
- }
- else
- {
- printk(KERN_INFO "%s: Failed to read in 2k mode!\n", eeprom_name);
- }
-
- /* 16k settings */
- eeprom.size = EEPROM_16KB;
- eeprom.select_cmd = 0xA0;
- eeprom.sequential_write_pagesize = 64;
-
- {
- unsigned char loc1[4], loc2[4], tmp[4];
- if( eeprom_read_buf(LOC2, loc2, 4) == 4)
- {
- if( eeprom_read_buf(LOC1, loc1, 4) == 4)
- {
- D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n",
- LOC1, loc1, LOC2, loc2));
-#if 0
- if (memcmp(loc1, loc2, 4) != 0 )
- {
- /* It's 16k */
- printk(KERN_INFO "%s: 16k detected in step 1\n", eeprom_name);
- eeprom.size = EEPROM_16KB;
- success = 1;
- }
- else
-#endif
- {
- /* Do step 2 check */
- /* Invert value */
- loc1[0] = ~loc1[0];
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- /* If 2k EEPROM this write will actually write 10 bytes
- * from pos 0
- */
- D(printk("1 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n",
- LOC1, loc1, LOC2, loc2));
- if( eeprom_read_buf(LOC1, tmp, 4) == 4)
- {
- D(printk("2 loc1: (%i) '%4.4s' tmp '%4.4s'\n",
- LOC1, loc1, tmp));
- if (memcmp(loc1, tmp, 4) != 0 )
- {
- printk(KERN_INFO "%s: read and write differs! Not 16kB\n",
- eeprom_name);
- loc1[0] = ~loc1[0];
-
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- success = 1;
- }
- else
- {
- printk(KERN_INFO "%s: Restore 2k failed during probe,"
- " EEPROM might be corrupt!\n", eeprom_name);
-
- }
- i2c_stop();
- /* Go to 2k mode and write original data */
- eeprom.size = EEPROM_2KB;
- eeprom.select_cmd = 0xA0;
- eeprom.sequential_write_pagesize = 16;
- if( eeprom_write_buf(0, buf_2k_start, 16) == 16)
- {
- }
- else
- {
- printk(KERN_INFO "%s: Failed to write back 2k start!\n",
- eeprom_name);
- }
-
- eeprom.size = EEPROM_2KB;
- }
- }
-
- if(!success)
- {
- if( eeprom_read_buf(LOC2, loc2, 1) == 1)
- {
- D(printk("0 loc1: (%i) '%4.4s' loc2 (%i) '%4.4s'\n",
- LOC1, loc1, LOC2, loc2));
- if (memcmp(loc1, loc2, 4) == 0 )
- {
- /* Data the same, must be mirrored -> 2k */
- /* Restore data */
- printk(KERN_INFO "%s: 2k detected in step 2\n", eeprom_name);
- loc1[0] = ~loc1[0];
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- success = 1;
- }
- else
- {
- printk(KERN_INFO "%s: Restore 2k failed during probe,"
- " EEPROM might be corrupt!\n", eeprom_name);
-
- }
-
- eeprom.size = EEPROM_2KB;
- }
- else
- {
- printk(KERN_INFO "%s: 16k detected in step 2\n",
- eeprom_name);
- loc1[0] = ~loc1[0];
- /* Data differs, assume 16k */
- /* Restore data */
- if (eeprom_write_buf(LOC1, loc1, 1) == 1)
- {
- success = 1;
- }
- else
- {
- printk(KERN_INFO "%s: Restore 16k failed during probe,"
- " EEPROM might be corrupt!\n", eeprom_name);
- }
-
- eeprom.size = EEPROM_16KB;
- }
- }
- }
- }
- } /* read LOC1 */
- } /* address LOC1 */
- if (!success)
- {
- printk(KERN_INFO "%s: Probing failed!, using 2KB!\n", eeprom_name);
- eeprom.size = EEPROM_2KB;
- }
- } /* read */
- }
- }
- else
- {
- i2c_outbyte(0x00);
- if(!i2c_getack())
- {
- /* No 8k */
- eeprom.size = EEPROM_2KB;
- }
- else
- {
- i2c_start();
- i2c_outbyte(0x81);
- if (!i2c_getack())
- {
- eeprom.size = EEPROM_2KB;
- }
- else
- {
- /* It's a 8kB */
- i2c_inbyte();
- eeprom.size = EEPROM_8KB;
- }
- }
- }
- i2c_stop();
-#elif defined(CONFIG_ETRAX_I2C_EEPROM_16KB)
- eeprom.size = EEPROM_16KB;
-#elif defined(CONFIG_ETRAX_I2C_EEPROM_8KB)
- eeprom.size = EEPROM_8KB;
-#elif defined(CONFIG_ETRAX_I2C_EEPROM_2KB)
- eeprom.size = EEPROM_2KB;
-#endif
-
- switch(eeprom.size)
- {
- case (EEPROM_2KB):
- printk("%s: " EETEXT " i2c compatible 2kB eeprom.\n", eeprom_name);
- eeprom.sequential_write_pagesize = 16;
- eeprom.select_cmd = 0xA0;
- break;
- case (EEPROM_8KB):
- printk("%s: " EETEXT " i2c compatible 8kB eeprom.\n", eeprom_name);
- eeprom.sequential_write_pagesize = 16;
- eeprom.select_cmd = 0x80;
- break;
- case (EEPROM_16KB):
- printk("%s: " EETEXT " i2c compatible 16kB eeprom.\n", eeprom_name);
- eeprom.sequential_write_pagesize = 64;
- eeprom.select_cmd = 0xA0;
- break;
- default:
- eeprom.size = 0;
- printk("%s: Did not find a supported eeprom\n", eeprom_name);
- break;
- }
-
-
-
- eeprom_disable_write_protect();
-
- return 0;
-}
-
-/* Opens the device. */
-static int eeprom_open(struct inode * inode, struct file * file)
-{
- if(iminor(inode) != EEPROM_MINOR_NR)
- return -ENXIO;
- if(imajor(inode) != EEPROM_MAJOR_NR)
- return -ENXIO;
-
- if( eeprom.size > 0 )
- {
- /* OK */
- return 0;
- }
-
- /* No EEprom found */
- return -EFAULT;
-}
-
-/* Changes the current file position. */
-
-static loff_t eeprom_lseek(struct file * file, loff_t offset, int orig)
-{
-/*
- * orig 0: position from beginning of eeprom
- * orig 1: relative from current position
- * orig 2: position from last eeprom address
- */
-
- switch (orig)
- {
- case 0:
- file->f_pos = offset;
- break;
- case 1:
- file->f_pos += offset;
- break;
- case 2:
- file->f_pos = eeprom.size - offset;
- break;
- default:
- return -EINVAL;
- }
-
- /* truncate position */
- if (file->f_pos < 0)
- {
- file->f_pos = 0;
- return(-EOVERFLOW);
- }
-
- if (file->f_pos >= eeprom.size)
- {
- file->f_pos = eeprom.size - 1;
- return(-EOVERFLOW);
- }
-
- return ( file->f_pos );
-}
-
-/* Reads data from eeprom. */
-
-static int eeprom_read_buf(loff_t addr, char * buf, int count)
-{
- return eeprom_read(NULL, buf, count, &addr);
-}
-
-
-
-/* Reads data from eeprom. */
-
-static ssize_t eeprom_read(struct file * file, char * buf, size_t count, loff_t *off)
-{
- int read=0;
- unsigned long p = *off;
-
- unsigned char page;
-
- if(p >= eeprom.size) /* Address i 0 - (size-1) */
- {
- return -EFAULT;
- }
-
- if (mutex_lock_interruptible(&eeprom.lock))
- return -EINTR;
-
- page = (unsigned char) (p >> 8);
-
- if(!eeprom_address(p))
- {
- printk(KERN_INFO "%s: Read failed to address the eeprom: "
- "0x%08X (%i) page: %i\n", eeprom_name, (int)p, (int)p, page);
- i2c_stop();
-
- /* don't forget to wake them up */
- mutex_unlock(&eeprom.lock);
- return -EFAULT;
- }
-
- if( (p + count) > eeprom.size)
- {
- /* truncate count */
- count = eeprom.size - p;
- }
-
- /* stop dummy write op and initiate the read op */
- i2c_start();
-
- /* special case for small eeproms */
- if(eeprom.size < EEPROM_16KB)
- {
- i2c_outbyte( eeprom.select_cmd | 1 | (page << 1) );
- }
-
- /* go on with the actual read */
- read = read_from_eeprom( buf, count);
-
- if(read > 0)
- {
- *off += read;
- }
-
- mutex_unlock(&eeprom.lock);
- return read;
-}
-
-/* Writes data to eeprom. */
-
-static int eeprom_write_buf(loff_t addr, const char * buf, int count)
-{
- return eeprom_write(NULL, buf, count, &addr);
-}
-
-
-/* Writes data to eeprom. */
-
-static ssize_t eeprom_write(struct file * file, const char * buf, size_t count,
- loff_t *off)
-{
- int i, written, restart=1;
- unsigned long p;
-
- if (!access_ok(VERIFY_READ, buf, count))
- {
- return -EFAULT;
- }
-
- /* bail out if we get interrupted */
- if (mutex_lock_interruptible(&eeprom.lock))
- return -EINTR;
- for(i = 0; (i < EEPROM_RETRIES) && (restart > 0); i++)
- {
- restart = 0;
- written = 0;
- p = *off;
-
-
- while( (written < count) && (p < eeprom.size))
- {
- /* address the eeprom */
- if(!eeprom_address(p))
- {
- printk(KERN_INFO "%s: Write failed to address the eeprom: "
- "0x%08X (%i) \n", eeprom_name, (int)p, (int)p);
- i2c_stop();
-
- /* don't forget to wake them up */
- mutex_unlock(&eeprom.lock);
- return -EFAULT;
- }
-#ifdef EEPROM_ADAPTIVE_TIMING
- /* Adaptive algorithm to adjust timing */
- if (eeprom.retry_cnt_addr > 0)
- {
- /* To Low now */
- D(printk(">D=%i d=%i\n",
- eeprom.usec_delay_writecycles, eeprom.usec_delay_step));
-
- if (eeprom.usec_delay_step < 4)
- {
- eeprom.usec_delay_step++;
- eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
- }
- else
- {
-
- if (eeprom.adapt_state > 0)
- {
- /* To Low before */
- eeprom.usec_delay_step *= 2;
- if (eeprom.usec_delay_step > 2)
- {
- eeprom.usec_delay_step--;
- }
- eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
- }
- else if (eeprom.adapt_state < 0)
- {
- /* To High before (toggle dir) */
- eeprom.usec_delay_writecycles += eeprom.usec_delay_step;
- if (eeprom.usec_delay_step > 1)
- {
- eeprom.usec_delay_step /= 2;
- eeprom.usec_delay_step--;
- }
- }
- }
-
- eeprom.adapt_state = 1;
- }
- else
- {
- /* To High (or good) now */
- D(printk("<D=%i d=%i\n",
- eeprom.usec_delay_writecycles, eeprom.usec_delay_step));
-
- if (eeprom.adapt_state < 0)
- {
- /* To High before */
- if (eeprom.usec_delay_step > 1)
- {
- eeprom.usec_delay_step *= 2;
- eeprom.usec_delay_step--;
-
- if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step)
- {
- eeprom.usec_delay_writecycles -= eeprom.usec_delay_step;
- }
- }
- }
- else if (eeprom.adapt_state > 0)
- {
- /* To Low before (toggle dir) */
- if (eeprom.usec_delay_writecycles > eeprom.usec_delay_step)
- {
- eeprom.usec_delay_writecycles -= eeprom.usec_delay_step;
- }
- if (eeprom.usec_delay_step > 1)
- {
- eeprom.usec_delay_step /= 2;
- eeprom.usec_delay_step--;
- }
-
- eeprom.adapt_state = -1;
- }
-
- if (eeprom.adapt_state > -100)
- {
- eeprom.adapt_state--;
- }
- else
- {
- /* Restart adaption */
- D(printk("#Restart\n"));
- eeprom.usec_delay_step++;
- }
- }
-#endif /* EEPROM_ADAPTIVE_TIMING */
- /* write until we hit a page boundary or count */
- do
- {
- i2c_outbyte(buf[written]);
- if(!i2c_getack())
- {
- restart=1;
- printk(KERN_INFO "%s: write error, retrying. %d\n", eeprom_name, i);
- i2c_stop();
- break;
- }
- written++;
- p++;
- } while( written < count && ( p % eeprom.sequential_write_pagesize ));
-
- /* end write cycle */
- i2c_stop();
- i2c_delay(eeprom.usec_delay_writecycles);
- } /* while */
- } /* for */
-
- mutex_unlock(&eeprom.lock);
- if (written == 0 && p >= eeprom.size){
- return -ENOSPC;
- }
- *off = p;
- return written;
-}
-
-/* Closes the device. */
-
-static int eeprom_close(struct inode * inode, struct file * file)
-{
- /* do nothing for now */
- return 0;
-}
-
-/* Sets the current address of the eeprom. */
-
-static int eeprom_address(unsigned long addr)
-{
- int i;
- unsigned char page, offset;
-
- page = (unsigned char) (addr >> 8);
- offset = (unsigned char) addr;
-
- for(i = 0; i < EEPROM_RETRIES; i++)
- {
- /* start a dummy write for addressing */
- i2c_start();
-
- if(eeprom.size == EEPROM_16KB)
- {
- i2c_outbyte( eeprom.select_cmd );
- i2c_getack();
- i2c_outbyte(page);
- }
- else
- {
- i2c_outbyte( eeprom.select_cmd | (page << 1) );
- }
- if(!i2c_getack())
- {
- /* retry */
- i2c_stop();
- /* Must have a delay here.. 500 works, >50, 100->works 5th time*/
- i2c_delay(MAX_WRITEDELAY_US / EEPROM_RETRIES * i);
- /* The chip needs up to 10 ms from write stop to next start */
-
- }
- else
- {
- i2c_outbyte(offset);
-
- if(!i2c_getack())
- {
- /* retry */
- i2c_stop();
- }
- else
- break;
- }
- }
-
-
- eeprom.retry_cnt_addr = i;
- D(printk("%i\n", eeprom.retry_cnt_addr));
- if(eeprom.retry_cnt_addr == EEPROM_RETRIES)
- {
- /* failed */
- return 0;
- }
- return 1;
-}
-
-/* Reads from current address. */
-
-static int read_from_eeprom(char * buf, int count)
-{
- int i, read=0;
-
- for(i = 0; i < EEPROM_RETRIES; i++)
- {
- if(eeprom.size == EEPROM_16KB)
- {
- i2c_outbyte( eeprom.select_cmd | 1 );
- }
-
- if(i2c_getack())
- {
- break;
- }
- }
-
- if(i == EEPROM_RETRIES)
- {
- printk(KERN_INFO "%s: failed to read from eeprom\n", eeprom_name);
- i2c_stop();
-
- return -EFAULT;
- }
-
- while( (read < count))
- {
- if (put_user(i2c_inbyte(), &buf[read++]))
- {
- i2c_stop();
-
- return -EFAULT;
- }
-
- /*
- * make sure we don't ack last byte or you will get very strange
- * results!
- */
- if(read < count)
- {
- i2c_sendack();
- }
- }
-
- /* stop the operation */
- i2c_stop();
-
- return read;
-}
-
-/* Disables write protection if applicable. */
-
-#define DBP_SAVE(x)
-#define ax_printf printk
-static void eeprom_disable_write_protect(void)
-{
- /* Disable write protect */
- if (eeprom.size == EEPROM_8KB)
- {
- /* Step 1 Set WEL = 1 (write 00000010 to address 1FFFh */
- i2c_start();
- i2c_outbyte(0xbe);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false\n"));
- }
- i2c_outbyte(0xFF);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 2\n"));
- }
- i2c_outbyte(0x02);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 3\n"));
- }
- i2c_stop();
-
- i2c_delay(1000);
-
- /* Step 2 Set RWEL = 1 (write 00000110 to address 1FFFh */
- i2c_start();
- i2c_outbyte(0xbe);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 55\n"));
- }
- i2c_outbyte(0xFF);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 52\n"));
- }
- i2c_outbyte(0x06);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 53\n"));
- }
- i2c_stop();
-
- /* Step 3 Set BP1, BP0, and/or WPEN bits (write 00000110 to address 1FFFh */
- i2c_start();
- i2c_outbyte(0xbe);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 56\n"));
- }
- i2c_outbyte(0xFF);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 57\n"));
- }
- i2c_outbyte(0x06);
- if(!i2c_getack())
- {
- DBP_SAVE(ax_printf("Get ack returns false 58\n"));
- }
- i2c_stop();
-
- /* Write protect disabled */
- }
-}
-device_initcall(eeprom_init);
diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c
deleted file mode 100644
index cd0e05d89d42..000000000000
--- a/arch/cris/arch-v10/drivers/gpio.c
+++ /dev/null
@@ -1,857 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Etrax general port I/O device
- *
- * Copyright (c) 1999-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (initial version)
- * Ola Knutsson (LED handling)
- * Johan Adolfsson (read/set directions, write, port G)
- */
-
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/ioport.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/poll.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-
-#include <asm/etraxgpio.h>
-#include <arch/svinto.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <arch/io_interface_mux.h>
-
-#define GPIO_MAJOR 120 /* experimental MAJOR number */
-
-#define D(x)
-
-#if 0
-static int dp_cnt;
-#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
-#else
-#define DP(x)
-#endif
-
-static char gpio_name[] = "etrax gpio";
-
-#if 0
-static wait_queue_head_t *gpio_wq;
-#endif
-
-static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
-static ssize_t gpio_write(struct file *file, const char __user *buf,
- size_t count, loff_t *off);
-static int gpio_open(struct inode *inode, struct file *filp);
-static int gpio_release(struct inode *inode, struct file *filp);
-static __poll_t gpio_poll(struct file *filp, struct poll_table_struct *wait);
-
-/* private data per open() of this driver */
-
-struct gpio_private {
- struct gpio_private *next;
- /* These fields are for PA and PB only */
- volatile unsigned char *port, *shadow;
- volatile unsigned char *dir, *dir_shadow;
- unsigned char changeable_dir;
- unsigned char changeable_bits;
- unsigned char clk_mask;
- unsigned char data_mask;
- unsigned char write_msb;
- unsigned char pad1, pad2, pad3;
- /* These fields are generic */
- unsigned long highalarm, lowalarm;
- wait_queue_head_t alarm_wq;
- int minor;
-};
-
-/* linked list of alarms to check for */
-
-static struct gpio_private *alarmlist;
-
-static int gpio_some_alarms; /* Set if someone uses alarm */
-static unsigned long gpio_pa_irq_enabled_mask;
-
-static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
-
-/* Port A and B use 8 bit access, but Port G is 32 bit */
-#define NUM_PORTS (GPIO_MINOR_B+1)
-
-static volatile unsigned char *ports[NUM_PORTS] = {
- R_PORT_PA_DATA,
- R_PORT_PB_DATA,
-};
-static volatile unsigned char *shads[NUM_PORTS] = {
- &port_pa_data_shadow,
- &port_pb_data_shadow
-};
-
-/* What direction bits that are user changeable 1=changeable*/
-#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR
-#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00
-#endif
-#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR
-#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00
-#endif
-
-#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS
-#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF
-#endif
-#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS
-#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF
-#endif
-
-
-static unsigned char changeable_dir[NUM_PORTS] = {
- CONFIG_ETRAX_PA_CHANGEABLE_DIR,
- CONFIG_ETRAX_PB_CHANGEABLE_DIR
-};
-static unsigned char changeable_bits[NUM_PORTS] = {
- CONFIG_ETRAX_PA_CHANGEABLE_BITS,
- CONFIG_ETRAX_PB_CHANGEABLE_BITS
-};
-
-static volatile unsigned char *dir[NUM_PORTS] = {
- R_PORT_PA_DIR,
- R_PORT_PB_DIR
-};
-
-static volatile unsigned char *dir_shadow[NUM_PORTS] = {
- &port_pa_dir_shadow,
- &port_pb_dir_shadow
-};
-
-/* All bits in port g that can change dir. */
-static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
-
-/* Port G is 32 bit, handle it special, some bits are both inputs
- and outputs at the same time, only some of the bits can change direction
- and some of them in groups of 8 bit. */
-static unsigned long changeable_dir_g;
-static unsigned long dir_g_in_bits;
-static unsigned long dir_g_out_bits;
-static unsigned long dir_g_shadow; /* 1=output */
-
-#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
-
-
-static __poll_t gpio_poll(struct file *file, poll_table *wait)
-{
- __poll_t mask = 0;
- struct gpio_private *priv = file->private_data;
- unsigned long data;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- poll_wait(file, &priv->alarm_wq, wait);
- if (priv->minor == GPIO_MINOR_A) {
- unsigned long tmp;
- data = *R_PORT_PA_DATA;
- /* PA has support for high level interrupt -
- * lets activate for those low and with highalarm set
- */
- tmp = ~data & priv->highalarm & 0xFF;
- tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
-
- gpio_pa_irq_enabled_mask |= tmp;
- *R_IRQ_MASK1_SET = tmp;
- } else if (priv->minor == GPIO_MINOR_B)
- data = *R_PORT_PB_DATA;
- else if (priv->minor == GPIO_MINOR_G)
- data = *R_PORT_G_DATA;
- else {
- mask = 0;
- goto out;
- }
-
- if ((data & priv->highalarm) ||
- (~data & priv->lowalarm)) {
- mask = EPOLLIN|EPOLLRDNORM;
- }
-
-out:
- spin_unlock_irqrestore(&gpio_lock, flags);
- DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
-
- return mask;
-}
-
-int etrax_gpio_wake_up_check(void)
-{
- struct gpio_private *priv;
- unsigned long data = 0;
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
- priv = alarmlist;
- while (priv) {
- if (USE_PORTS(priv))
- data = *priv->port;
- else if (priv->minor == GPIO_MINOR_G)
- data = *R_PORT_G_DATA;
-
- if ((data & priv->highalarm) ||
- (~data & priv->lowalarm)) {
- DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
- wake_up_interruptible(&priv->alarm_wq);
- ret = 1;
- }
- priv = priv->next;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- return ret;
-}
-
-static irqreturn_t
-gpio_poll_timer_interrupt(int irq, void *dev_id)
-{
- if (gpio_some_alarms) {
- etrax_gpio_wake_up_check();
- return IRQ_HANDLED;
- }
- return IRQ_NONE;
-}
-
-static irqreturn_t
-gpio_interrupt(int irq, void *dev_id)
-{
- unsigned long tmp;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- /* Find what PA interrupts are active */
- tmp = (*R_IRQ_READ1);
-
- /* Find those that we have enabled */
- tmp &= gpio_pa_irq_enabled_mask;
-
- /* Clear them.. */
- *R_IRQ_MASK1_CLR = tmp;
- gpio_pa_irq_enabled_mask &= ~tmp;
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- if (gpio_some_alarms)
- return IRQ_RETVAL(etrax_gpio_wake_up_check());
-
- return IRQ_NONE;
-}
-
-static void gpio_write_bit(struct gpio_private *priv,
- unsigned char data, int bit)
-{
- *priv->port = *priv->shadow &= ~(priv->clk_mask);
- if (data & 1 << bit)
- *priv->port = *priv->shadow |= priv->data_mask;
- else
- *priv->port = *priv->shadow &= ~(priv->data_mask);
-
- /* For FPGA: min 5.0ns (DCC) before CCLK high */
- *priv->port = *priv->shadow |= priv->clk_mask;
-}
-
-static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
-{
- int i;
-
- if (priv->write_msb)
- for (i = 7; i >= 0; i--)
- gpio_write_bit(priv, data, i);
- else
- for (i = 0; i <= 7; i++)
- gpio_write_bit(priv, data, i);
-}
-
-static ssize_t gpio_write(struct file *file, const char __user *buf,
- size_t count, loff_t *off)
-{
- struct gpio_private *priv = file->private_data;
- unsigned long flags;
- ssize_t retval = count;
-
- if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
- return -EFAULT;
-
- if (!access_ok(VERIFY_READ, buf, count))
- return -EFAULT;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- /* It must have been configured using the IO_CFG_WRITE_MODE */
- /* Perhaps a better error code? */
- if (priv->clk_mask == 0 || priv->data_mask == 0) {
- retval = -EPERM;
- goto out;
- }
-
- D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
- "clk 0x%02X msb: %i\n",
- count, priv->data_mask, priv->clk_mask, priv->write_msb));
-
- while (count--)
- gpio_write_byte(priv, *buf++);
-
-out:
- spin_unlock_irqrestore(&gpio_lock, flags);
- return retval;
-}
-
-
-
-static int
-gpio_open(struct inode *inode, struct file *filp)
-{
- struct gpio_private *priv;
- int p = iminor(inode);
- unsigned long flags;
-
- if (p > GPIO_MINOR_LAST)
- return -EINVAL;
-
- priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
-
- if (!priv)
- return -ENOMEM;
-
- priv->minor = p;
-
- /* initialize the io/alarm struct */
-
- if (USE_PORTS(priv)) { /* A and B */
- priv->port = ports[p];
- priv->shadow = shads[p];
- priv->dir = dir[p];
- priv->dir_shadow = dir_shadow[p];
- priv->changeable_dir = changeable_dir[p];
- priv->changeable_bits = changeable_bits[p];
- } else {
- priv->port = NULL;
- priv->shadow = NULL;
- priv->dir = NULL;
- priv->dir_shadow = NULL;
- priv->changeable_dir = 0;
- priv->changeable_bits = 0;
- }
-
- priv->highalarm = 0;
- priv->lowalarm = 0;
- priv->clk_mask = 0;
- priv->data_mask = 0;
- init_waitqueue_head(&priv->alarm_wq);
-
- filp->private_data = priv;
-
- /* link it into our alarmlist */
- spin_lock_irqsave(&gpio_lock, flags);
- priv->next = alarmlist;
- alarmlist = priv;
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- return 0;
-}
-
-static int
-gpio_release(struct inode *inode, struct file *filp)
-{
- struct gpio_private *p;
- struct gpio_private *todel;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- p = alarmlist;
- todel = filp->private_data;
-
- /* unlink from alarmlist and free the private structure */
-
- if (p == todel) {
- alarmlist = todel->next;
- } else {
- while (p->next != todel)
- p = p->next;
- p->next = todel->next;
- }
-
- kfree(todel);
- /* Check if there are still any alarms set */
- p = alarmlist;
- while (p) {
- if (p->highalarm | p->lowalarm) {
- gpio_some_alarms = 1;
- goto out;
- }
- p = p->next;
- }
- gpio_some_alarms = 0;
-out:
- spin_unlock_irqrestore(&gpio_lock, flags);
- return 0;
-}
-
-/* Main device API. ioctl's to read/set/clear bits, as well as to
- * set alarms to wait for using a subsequent select().
- */
-inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
-{
- /* Set direction 0=unchanged 1=input,
- * return mask with 1=input */
- if (USE_PORTS(priv)) {
- *priv->dir = *priv->dir_shadow &=
- ~((unsigned char)arg & priv->changeable_dir);
- return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
- }
-
- if (priv->minor != GPIO_MINOR_G)
- return 0;
-
- /* We must fiddle with R_GEN_CONFIG to change dir */
- if (((arg & dir_g_in_bits) != arg) &&
- (arg & changeable_dir_g)) {
- arg &= changeable_dir_g;
- /* Clear bits in genconfig to set to input */
- if (arg & (1<<0)) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
- dir_g_in_bits |= (1<<0);
- dir_g_out_bits &= ~(1<<0);
- }
- if ((arg & 0x0000FF00) == 0x0000FF00) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
- dir_g_in_bits |= 0x0000FF00;
- dir_g_out_bits &= ~0x0000FF00;
- }
- if ((arg & 0x00FF0000) == 0x00FF0000) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
- dir_g_in_bits |= 0x00FF0000;
- dir_g_out_bits &= ~0x00FF0000;
- }
- if (arg & (1<<24)) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
- dir_g_in_bits |= (1<<24);
- dir_g_out_bits &= ~(1<<24);
- }
- D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
- "genconfig to 0x%08lX "
- "in_bits: 0x%08lX "
- "out_bits: 0x%08lX\n",
- (unsigned long)genconfig_shadow,
- dir_g_in_bits, dir_g_out_bits));
- *R_GEN_CONFIG = genconfig_shadow;
- /* Must be a >120 ns delay before writing this again */
-
- }
- return dir_g_in_bits;
-} /* setget_input */
-
-inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
-{
- if (USE_PORTS(priv)) {
- *priv->dir = *priv->dir_shadow |=
- ((unsigned char)arg & priv->changeable_dir);
- return *priv->dir_shadow;
- }
- if (priv->minor != GPIO_MINOR_G)
- return 0;
-
- /* We must fiddle with R_GEN_CONFIG to change dir */
- if (((arg & dir_g_out_bits) != arg) &&
- (arg & changeable_dir_g)) {
- /* Set bits in genconfig to set to output */
- if (arg & (1<<0)) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
- dir_g_out_bits |= (1<<0);
- dir_g_in_bits &= ~(1<<0);
- }
- if ((arg & 0x0000FF00) == 0x0000FF00) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
- dir_g_out_bits |= 0x0000FF00;
- dir_g_in_bits &= ~0x0000FF00;
- }
- if ((arg & 0x00FF0000) == 0x00FF0000) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
- dir_g_out_bits |= 0x00FF0000;
- dir_g_in_bits &= ~0x00FF0000;
- }
- if (arg & (1<<24)) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
- dir_g_out_bits |= (1<<24);
- dir_g_in_bits &= ~(1<<24);
- }
- D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
- "genconfig to 0x%08lX "
- "in_bits: 0x%08lX "
- "out_bits: 0x%08lX\n",
- (unsigned long)genconfig_shadow,
- dir_g_in_bits, dir_g_out_bits));
- *R_GEN_CONFIG = genconfig_shadow;
- /* Must be a >120 ns delay before writing this again */
- }
- return dir_g_out_bits & 0x7FFFFFFF;
-} /* setget_output */
-
-static int
-gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
-
-static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- unsigned long flags;
- unsigned long val;
- int ret = 0;
-
- struct gpio_private *priv = file->private_data;
- if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
- return -EINVAL;
-
- switch (_IOC_NR(cmd)) {
- case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
- // read the port
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- ret = *priv->port;
- } else if (priv->minor == GPIO_MINOR_G) {
- ret = (*R_PORT_G_DATA) & 0x7FFFFFFF;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- break;
- case IO_SETBITS:
- // set changeable bits with a 1 in arg
- spin_lock_irqsave(&gpio_lock, flags);
-
- if (USE_PORTS(priv)) {
- *priv->port = *priv->shadow |=
- ((unsigned char)arg & priv->changeable_bits);
- } else if (priv->minor == GPIO_MINOR_G) {
- *R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- break;
- case IO_CLRBITS:
- // clear changeable bits with a 1 in arg
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- *priv->port = *priv->shadow &=
- ~((unsigned char)arg & priv->changeable_bits);
- } else if (priv->minor == GPIO_MINOR_G) {
- *R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_HIGHALARM:
- // set alarm when bits with 1 in arg go high
- spin_lock_irqsave(&gpio_lock, flags);
- priv->highalarm |= arg;
- gpio_some_alarms = 1;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_LOWALARM:
- // set alarm when bits with 1 in arg go low
- spin_lock_irqsave(&gpio_lock, flags);
- priv->lowalarm |= arg;
- gpio_some_alarms = 1;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_CLRALARM:
- /* clear alarm for bits with 1 in arg */
- spin_lock_irqsave(&gpio_lock, flags);
- priv->highalarm &= ~arg;
- priv->lowalarm &= ~arg;
- {
- /* Must update gpio_some_alarms */
- struct gpio_private *p = alarmlist;
- int some_alarms;
- p = alarmlist;
- some_alarms = 0;
- while (p) {
- if (p->highalarm | p->lowalarm) {
- some_alarms = 1;
- break;
- }
- p = p->next;
- }
- gpio_some_alarms = some_alarms;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
- /* Read direction 0=input 1=output */
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- ret = *priv->dir_shadow;
- } else if (priv->minor == GPIO_MINOR_G) {
- /* Note: Some bits are both in and out,
- * Those that are dual is set here as well.
- */
- ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
- /* Set direction 0=unchanged 1=input,
- * return mask with 1=input
- */
- spin_lock_irqsave(&gpio_lock, flags);
- ret = setget_input(priv, arg) & 0x7FFFFFFF;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
- /* Set direction 0=unchanged 1=output,
- * return mask with 1=output
- */
- spin_lock_irqsave(&gpio_lock, flags);
- ret = setget_output(priv, arg) & 0x7FFFFFFF;
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_SHUTDOWN:
- spin_lock_irqsave(&gpio_lock, flags);
- SOFT_SHUTDOWN();
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_GET_PWR_BT:
- spin_lock_irqsave(&gpio_lock, flags);
-#if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
- ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
-#else
- ret = 0;
-#endif
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_CFG_WRITE_MODE:
- spin_lock_irqsave(&gpio_lock, flags);
- priv->clk_mask = arg & 0xFF;
- priv->data_mask = (arg >> 8) & 0xFF;
- priv->write_msb = (arg >> 16) & 0x01;
- /* Check if we're allowed to change the bits and
- * the direction is correct
- */
- if (!((priv->clk_mask & priv->changeable_bits) &&
- (priv->data_mask & priv->changeable_bits) &&
- (priv->clk_mask & *priv->dir_shadow) &&
- (priv->data_mask & *priv->dir_shadow)))
- {
- priv->clk_mask = 0;
- priv->data_mask = 0;
- ret = -EPERM;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- break;
- case IO_READ_INBITS:
- /* *arg is result of reading the input pins */
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- val = *priv->port;
- } else if (priv->minor == GPIO_MINOR_G) {
- val = *R_PORT_G_DATA;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- case IO_READ_OUTBITS:
- /* *arg is result of reading the output shadow */
- spin_lock_irqsave(&gpio_lock, flags);
- if (USE_PORTS(priv)) {
- val = *priv->shadow;
- } else if (priv->minor == GPIO_MINOR_G) {
- val = port_g_data_shadow;
- }
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- case IO_SETGET_INPUT:
- /* bits set in *arg is set to input,
- * *arg updated with current input pins.
- */
- if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
- {
- ret = -EFAULT;
- break;
- }
- spin_lock_irqsave(&gpio_lock, flags);
- val = setget_input(priv, val);
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- case IO_SETGET_OUTPUT:
- /* bits set in *arg is set to output,
- * *arg updated with current output pins.
- */
- if (copy_from_user(&val, (void __user *)arg, sizeof(val))) {
- ret = -EFAULT;
- break;
- }
- spin_lock_irqsave(&gpio_lock, flags);
- val = setget_output(priv, val);
- spin_unlock_irqrestore(&gpio_lock, flags);
- if (copy_to_user((void __user *)arg, &val, sizeof(val)))
- ret = -EFAULT;
- break;
- default:
- spin_lock_irqsave(&gpio_lock, flags);
- if (priv->minor == GPIO_MINOR_LEDS)
- ret = gpio_leds_ioctl(cmd, arg);
- else
- ret = -EINVAL;
- spin_unlock_irqrestore(&gpio_lock, flags);
- } /* switch */
-
- return ret;
-}
-
-static int
-gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
-{
- unsigned char green;
- unsigned char red;
-
- switch (_IOC_NR(cmd)) {
- case IO_LEDACTIVE_SET:
- green = ((unsigned char)arg) & 1;
- red = (((unsigned char)arg) >> 1) & 1;
- CRIS_LED_ACTIVE_SET_G(green);
- CRIS_LED_ACTIVE_SET_R(red);
- break;
-
- case IO_LED_SETBIT:
- CRIS_LED_BIT_SET(arg);
- break;
-
- case IO_LED_CLRBIT:
- CRIS_LED_BIT_CLR(arg);
- break;
-
- default:
- return -EINVAL;
- } /* switch */
-
- return 0;
-}
-
-static const struct file_operations gpio_fops = {
- .owner = THIS_MODULE,
- .poll = gpio_poll,
- .unlocked_ioctl = gpio_ioctl,
- .write = gpio_write,
- .open = gpio_open,
- .release = gpio_release,
- .llseek = noop_llseek,
-};
-
-static void ioif_watcher(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available)
-{
- unsigned long int flags;
-
- D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
- D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
- "PA: 0x%02x PB: 0x%02x\n",
- gpio_in_available, gpio_out_available,
- pa_available, pb_available));
-
- spin_lock_irqsave(&gpio_lock, flags);
-
- dir_g_in_bits = gpio_in_available;
- dir_g_out_bits = gpio_out_available;
-
- /* Initialise the dir_g_shadow etc. depending on genconfig */
- /* 0=input 1=output */
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
- dir_g_shadow |= (1 << 0);
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
- dir_g_shadow |= 0x0000FF00;
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out))
- dir_g_shadow |= 0x00FF0000;
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
- dir_g_shadow |= (1 << 24);
-
- changeable_dir_g = changeable_dir_g_mask;
- changeable_dir_g &= dir_g_out_bits;
- changeable_dir_g &= dir_g_in_bits;
-
- /* Correct the bits that can change direction */
- dir_g_out_bits &= ~changeable_dir_g;
- dir_g_out_bits |= dir_g_shadow;
- dir_g_in_bits &= ~changeable_dir_g;
- dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
- "val: %08lX\n",
- dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
- printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
- dir_g_shadow, changeable_dir_g);
-}
-
-/* main driver initialization routine, called from mem.c */
-
-static int __init gpio_init(void)
-{
- int res;
-#if defined (CONFIG_ETRAX_CSP0_LEDS)
- int i;
-#endif
-
- res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
- if (res < 0) {
- printk(KERN_ERR "gpio: couldn't get a major number.\n");
- return res;
- }
-
- /* Clear all leds */
-#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
- CRIS_LED_NETWORK_SET(0);
- CRIS_LED_ACTIVE_SET(0);
- CRIS_LED_DISK_READ(0);
- CRIS_LED_DISK_WRITE(0);
-
-#if defined (CONFIG_ETRAX_CSP0_LEDS)
- for (i = 0; i < 32; i++)
- CRIS_LED_BIT_SET(i);
-#endif
-
-#endif
- /* The I/O interface allocation watcher will be called when
- * registering it. */
- if (cris_io_interface_register_watcher(ioif_watcher)){
- printk(KERN_WARNING "gpio_init: Failed to install IO "
- "if allocator watcher\n");
- }
-
- printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
- "Axis Communications AB\n");
- /* We call etrax_gpio_wake_up_check() from timer interrupt and
- * from default_idle() in kernel/process.c
- * The check in default_idle() reduces latency from ~15 ms to ~6 ms
- * in some tests.
- */
- res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
- IRQF_SHARED, "gpio poll", gpio_name);
- if (res) {
- printk(KERN_CRIT "err: timer0 irq for gpio\n");
- return res;
- }
- res = request_irq(PA_IRQ_NBR, gpio_interrupt,
- IRQF_SHARED, "gpio PA", gpio_name);
- if (res)
- printk(KERN_CRIT "err: PA irq for gpio\n");
-
- return res;
-}
-
-/* this makes sure that gpio_init is called during kernel boot */
-module_init(gpio_init);
-
diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c
deleted file mode 100644
index ec35d62e8e63..000000000000
--- a/arch/cris/arch-v10/drivers/i2c.c
+++ /dev/null
@@ -1,699 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*!***************************************************************************
-*!
-*! FILE NAME : i2c.c
-*!
-*! DESCRIPTION: implements an interface for IIC/I2C, both directly from other
-*! kernel modules (i2c_writereg/readreg) and from userspace using
-*! ioctl()'s
-*!
-*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN
-*!
-*!***************************************************************************/
-
-/****************** INCLUDE FILES SECTION ***********************************/
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/init.h>
-
-#include <asm/etraxi2c.h>
-
-#include <arch/svinto.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <arch/io_interface_mux.h>
-
-#include "i2c.h"
-
-/****************** I2C DEFINITION SECTION *************************/
-
-#define D(x)
-
-#define I2C_MAJOR 123 /* LOCAL/EXPERIMENTAL */
-static const char i2c_name[] = "i2c";
-
-#define CLOCK_LOW_TIME 8
-#define CLOCK_HIGH_TIME 8
-#define START_CONDITION_HOLD_TIME 8
-#define STOP_CONDITION_HOLD_TIME 8
-#define ENABLE_OUTPUT 0x01
-#define ENABLE_INPUT 0x00
-#define I2C_CLOCK_HIGH 1
-#define I2C_CLOCK_LOW 0
-#define I2C_DATA_HIGH 1
-#define I2C_DATA_LOW 0
-
-#ifdef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C
-/* Use PB and not PB_I2C */
-#ifndef CONFIG_ETRAX_I2C_DATA_PORT
-#define CONFIG_ETRAX_I2C_DATA_PORT 0
-#endif
-#ifndef CONFIG_ETRAX_I2C_CLK_PORT
-#define CONFIG_ETRAX_I2C_CLK_PORT 1
-#endif
-
-#define SDABIT CONFIG_ETRAX_I2C_DATA_PORT
-#define SCLBIT CONFIG_ETRAX_I2C_CLK_PORT
-#define i2c_enable()
-#define i2c_disable()
-
-/* enable or disable output-enable, to select output or input on the i2c bus */
-
-#define i2c_dir_out() \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 1)
-#define i2c_dir_in() \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, SDABIT, 0)
-
-/* control the i2c clock and data signals */
-
-#define i2c_clk(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SCLBIT, x)
-#define i2c_data(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, SDABIT, x)
-
-/* read a bit from the i2c interface */
-
-#define i2c_getbit() (((*R_PORT_PB_READ & (1 << SDABIT))) >> SDABIT)
-
-#else
-/* enable or disable the i2c interface */
-
-#define i2c_enable() *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_en))
-#define i2c_disable() *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_en))
-
-/* enable or disable output-enable, to select output or input on the i2c bus */
-
-#define i2c_dir_out() \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow &= ~IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 1);
-#define i2c_dir_in() \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow |= IO_MASK(R_PORT_PB_I2C, i2c_oe_)); \
- REG_SHADOW_SET(R_PORT_PB_DIR, port_pb_dir_shadow, 0, 0);
-
-/* control the i2c clock and data signals */
-
-#define i2c_clk(x) \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \
- ~IO_MASK(R_PORT_PB_I2C, i2c_clk)) | IO_FIELD(R_PORT_PB_I2C, i2c_clk, (x))); \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 1, x);
-
-#define i2c_data(x) \
- *R_PORT_PB_I2C = (port_pb_i2c_shadow = (port_pb_i2c_shadow & \
- ~IO_MASK(R_PORT_PB_I2C, i2c_d)) | IO_FIELD(R_PORT_PB_I2C, i2c_d, (x))); \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 0, x);
-
-/* read a bit from the i2c interface */
-
-#define i2c_getbit() (*R_PORT_PB_READ & 0x1)
-#endif
-
-/* use the kernels delay routine */
-
-#define i2c_delay(usecs) udelay(usecs)
-
-static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */
-
-/****************** FUNCTION DEFINITION SECTION *************************/
-
-
-/* generate i2c start condition */
-
-void
-i2c_start(void)
-{
- /*
- * SCL=1 SDA=1
- */
- i2c_dir_out();
- i2c_delay(CLOCK_HIGH_TIME/6);
- i2c_data(I2C_DATA_HIGH);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- /*
- * SCL=1 SDA=0
- */
- i2c_data(I2C_DATA_LOW);
- i2c_delay(START_CONDITION_HOLD_TIME);
- /*
- * SCL=0 SDA=0
- */
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME);
-}
-
-/* generate i2c stop condition */
-
-void
-i2c_stop(void)
-{
- i2c_dir_out();
-
- /*
- * SCL=0 SDA=0
- */
- i2c_clk(I2C_CLOCK_LOW);
- i2c_data(I2C_DATA_LOW);
- i2c_delay(CLOCK_LOW_TIME*2);
- /*
- * SCL=1 SDA=0
- */
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME*2);
- /*
- * SCL=1 SDA=1
- */
- i2c_data(I2C_DATA_HIGH);
- i2c_delay(STOP_CONDITION_HOLD_TIME);
-
- i2c_dir_in();
-}
-
-/* write a byte to the i2c interface */
-
-void
-i2c_outbyte(unsigned char x)
-{
- int i;
-
- i2c_dir_out();
-
- for (i = 0; i < 8; i++) {
- if (x & 0x80) {
- i2c_data(I2C_DATA_HIGH);
- } else {
- i2c_data(I2C_DATA_LOW);
- }
-
- i2c_delay(CLOCK_LOW_TIME/2);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME/2);
- x <<= 1;
- }
- i2c_data(I2C_DATA_LOW);
- i2c_delay(CLOCK_LOW_TIME/2);
-
- /*
- * enable input
- */
- i2c_dir_in();
-}
-
-/* read a byte from the i2c interface */
-
-unsigned char
-i2c_inbyte(void)
-{
- unsigned char aBitByte = 0;
- int i;
-
- /* Switch off I2C to get bit */
- i2c_disable();
- i2c_dir_in();
- i2c_delay(CLOCK_HIGH_TIME/2);
-
- /* Get bit */
- aBitByte |= i2c_getbit();
-
- /* Enable I2C */
- i2c_enable();
- i2c_delay(CLOCK_LOW_TIME/2);
-
- for (i = 1; i < 8; i++) {
- aBitByte <<= 1;
- /* Clock pulse */
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME);
-
- /* Switch off I2C to get bit */
- i2c_disable();
- i2c_dir_in();
- i2c_delay(CLOCK_HIGH_TIME/2);
-
- /* Get bit */
- aBitByte |= i2c_getbit();
-
- /* Enable I2C */
- i2c_enable();
- i2c_delay(CLOCK_LOW_TIME/2);
- }
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
-
- /*
- * we leave the clock low, getbyte is usually followed
- * by sendack/nack, they assume the clock to be low
- */
- i2c_clk(I2C_CLOCK_LOW);
- return aBitByte;
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_getack
-*#
-*# DESCRIPTION : checks if ack was received from ic2
-*#
-*#--------------------------------------------------------------------------*/
-
-int
-i2c_getack(void)
-{
- int ack = 1;
- /*
- * enable output
- */
- i2c_dir_out();
- /*
- * Release data bus by setting
- * data high
- */
- i2c_data(I2C_DATA_HIGH);
- /*
- * enable input
- */
- i2c_dir_in();
- i2c_delay(CLOCK_HIGH_TIME/4);
- /*
- * generate ACK clock pulse
- */
- i2c_clk(I2C_CLOCK_HIGH);
- /*
- * Use PORT PB instead of I2C
- * for input. (I2C not working)
- */
- i2c_clk(1);
- i2c_data(1);
- /*
- * switch off I2C
- */
- i2c_data(1);
- i2c_disable();
- i2c_dir_in();
- /*
- * now wait for ack
- */
- i2c_delay(CLOCK_HIGH_TIME/2);
- /*
- * check for ack
- */
- if(i2c_getbit())
- ack = 0;
- i2c_delay(CLOCK_HIGH_TIME/2);
- if(!ack){
- if(!i2c_getbit()) /* receiver pulld SDA low */
- ack = 1;
- i2c_delay(CLOCK_HIGH_TIME/2);
- }
-
- /*
- * our clock is high now, make sure data is low
- * before we enable our output. If we keep data high
- * and enable output, we would generate a stop condition.
- */
- i2c_data(I2C_DATA_LOW);
-
- /*
- * end clock pulse
- */
- i2c_enable();
- i2c_dir_out();
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_HIGH_TIME/4);
- /*
- * enable output
- */
- i2c_dir_out();
- /*
- * remove ACK clock pulse
- */
- i2c_data(I2C_DATA_HIGH);
- i2c_delay(CLOCK_LOW_TIME/2);
- return ack;
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: I2C::sendAck
-*#
-*# DESCRIPTION : Send ACK on received data
-*#
-*#--------------------------------------------------------------------------*/
-void
-i2c_sendack(void)
-{
- /*
- * enable output
- */
- i2c_delay(CLOCK_LOW_TIME);
- i2c_dir_out();
- /*
- * set ack pulse high
- */
- i2c_data(I2C_DATA_LOW);
- /*
- * generate clock pulse
- */
- i2c_delay(CLOCK_HIGH_TIME/6);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME/6);
- /*
- * reset data out
- */
- i2c_data(I2C_DATA_HIGH);
- i2c_delay(CLOCK_LOW_TIME);
-
- i2c_dir_in();
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_sendnack
-*#
-*# DESCRIPTION : Sends NACK on received data
-*#
-*#--------------------------------------------------------------------------*/
-void
-i2c_sendnack(void)
-{
- /*
- * enable output
- */
- i2c_delay(CLOCK_LOW_TIME);
- i2c_dir_out();
- /*
- * set data high
- */
- i2c_data(I2C_DATA_HIGH);
- /*
- * generate clock pulse
- */
- i2c_delay(CLOCK_HIGH_TIME/6);
- i2c_clk(I2C_CLOCK_HIGH);
- i2c_delay(CLOCK_HIGH_TIME);
- i2c_clk(I2C_CLOCK_LOW);
- i2c_delay(CLOCK_LOW_TIME);
-
- i2c_dir_in();
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_writereg
-*#
-*# DESCRIPTION : Writes a value to an I2C device
-*#
-*#--------------------------------------------------------------------------*/
-int
-i2c_writereg(unsigned char theSlave, unsigned char theReg,
- unsigned char theValue)
-{
- int error, cntr = 3;
- unsigned long flags;
-
- spin_lock(&i2c_lock);
-
- do {
- error = 0;
- /*
- * we don't like to be interrupted
- */
- local_irq_save(flags);
-
- i2c_start();
- /*
- * send slave address
- */
- i2c_outbyte((theSlave & 0xfe));
- /*
- * wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * now select register
- */
- i2c_dir_out();
- i2c_outbyte(theReg);
- /*
- * now it's time to wait for ack
- */
- if(!i2c_getack())
- error |= 2;
- /*
- * send register register data
- */
- i2c_outbyte(theValue);
- /*
- * now it's time to wait for ack
- */
- if(!i2c_getack())
- error |= 4;
- /*
- * end byte stream
- */
- i2c_stop();
- /*
- * enable interrupt again
- */
- local_irq_restore(flags);
-
- } while(error && cntr--);
-
- i2c_delay(CLOCK_LOW_TIME);
-
- spin_unlock(&i2c_lock);
-
- return -error;
-}
-
-/*#---------------------------------------------------------------------------
-*#
-*# FUNCTION NAME: i2c_readreg
-*#
-*# DESCRIPTION : Reads a value from the decoder registers.
-*#
-*#--------------------------------------------------------------------------*/
-unsigned char
-i2c_readreg(unsigned char theSlave, unsigned char theReg)
-{
- unsigned char b = 0;
- int error, cntr = 3;
- unsigned long flags;
-
- spin_lock(&i2c_lock);
-
- do {
- error = 0;
- /*
- * we don't like to be interrupted
- */
- local_irq_save(flags);
- /*
- * generate start condition
- */
- i2c_start();
-
- /*
- * send slave address
- */
- i2c_outbyte((theSlave & 0xfe));
- /*
- * wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * now select register
- */
- i2c_dir_out();
- i2c_outbyte(theReg);
- /*
- * now it's time to wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * repeat start condition
- */
- i2c_delay(CLOCK_LOW_TIME);
- i2c_start();
- /*
- * send slave address
- */
- i2c_outbyte(theSlave | 0x01);
- /*
- * wait for ack
- */
- if(!i2c_getack())
- error = 1;
- /*
- * fetch register
- */
- b = i2c_inbyte();
- /*
- * last received byte needs to be nacked
- * instead of acked
- */
- i2c_sendnack();
- /*
- * end sequence
- */
- i2c_stop();
- /*
- * enable interrupt again
- */
- local_irq_restore(flags);
-
- } while(error && cntr--);
-
- spin_unlock(&i2c_lock);
-
- return b;
-}
-
-static int
-i2c_open(struct inode *inode, struct file *filp)
-{
- return 0;
-}
-
-static int
-i2c_release(struct inode *inode, struct file *filp)
-{
- return 0;
-}
-
-/* Main device API. ioctl's to write or read to/from i2c registers.
- */
-
-static long i2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
-{
- if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
- return -EINVAL;
- }
-
- switch (_IOC_NR(cmd)) {
- case I2C_WRITEREG:
- /* write to an i2c slave */
- D(printk(KERN_DEBUG "i2cw %d %d %d\n",
- I2C_ARGSLAVE(arg),
- I2C_ARGREG(arg),
- I2C_ARGVALUE(arg)));
-
- return i2c_writereg(I2C_ARGSLAVE(arg),
- I2C_ARGREG(arg),
- I2C_ARGVALUE(arg));
- case I2C_READREG:
- {
- unsigned char val;
- /* read from an i2c slave */
- D(printk(KERN_DEBUG "i2cr %d %d ",
- I2C_ARGSLAVE(arg),
- I2C_ARGREG(arg)));
- val = i2c_readreg(I2C_ARGSLAVE(arg), I2C_ARGREG(arg));
- D(printk(KERN_DEBUG "= %d\n", val));
- return val;
- }
- default:
- return -EINVAL;
-
- }
- return 0;
-}
-
-static const struct file_operations i2c_fops = {
- .owner = THIS_MODULE,
- .unlocked_ioctl = i2c_ioctl,
- .open = i2c_open,
- .release = i2c_release,
- .llseek = noop_llseek,
-};
-
-int __init
-i2c_init(void)
-{
- static int res = 0;
- static int first = 1;
-
- if (!first) {
- return res;
- }
- first = 0;
-
- /* Setup and enable the Port B I2C interface */
-
-#ifndef CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C
- if ((res = cris_request_io_interface(if_i2c, "I2C"))) {
- printk(KERN_CRIT "i2c_init: Failed to get IO interface\n");
- return res;
- }
-
- *R_PORT_PB_I2C = port_pb_i2c_shadow |=
- IO_STATE(R_PORT_PB_I2C, i2c_en, on) |
- IO_FIELD(R_PORT_PB_I2C, i2c_d, 1) |
- IO_FIELD(R_PORT_PB_I2C, i2c_clk, 1) |
- IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable);
-
- port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir0);
- port_pb_dir_shadow &= ~IO_MASK(R_PORT_PB_DIR, dir1);
-
- *R_PORT_PB_DIR = (port_pb_dir_shadow |=
- IO_STATE(R_PORT_PB_DIR, dir0, input) |
- IO_STATE(R_PORT_PB_DIR, dir1, output));
-#else
- if ((res = cris_io_interface_allocate_pins(if_i2c,
- 'b',
- CONFIG_ETRAX_I2C_DATA_PORT,
- CONFIG_ETRAX_I2C_DATA_PORT))) {
- printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C data port\n");
- return res;
- } else if ((res = cris_io_interface_allocate_pins(if_i2c,
- 'b',
- CONFIG_ETRAX_I2C_CLK_PORT,
- CONFIG_ETRAX_I2C_CLK_PORT))) {
- cris_io_interface_free_pins(if_i2c,
- 'b',
- CONFIG_ETRAX_I2C_DATA_PORT,
- CONFIG_ETRAX_I2C_DATA_PORT);
- printk(KERN_WARNING "i2c_init: Failed to get IO pin for I2C clk port\n");
- }
-#endif
-
- return res;
-}
-
-static int __init
-i2c_register(void)
-{
- int res;
-
- res = i2c_init();
- if (res < 0)
- return res;
- res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops);
- if(res < 0) {
- printk(KERN_ERR "i2c: couldn't get a major number.\n");
- return res;
- }
-
- printk(KERN_INFO "I2C driver v2.2, (c) 1999-2004 Axis Communications AB\n");
-
- return 0;
-}
-
-/* this makes sure that i2c_register is called during boot */
-
-module_init(i2c_register);
-
-/****************** END OF FILE i2c.c ********************************/
diff --git a/arch/cris/arch-v10/drivers/i2c.h b/arch/cris/arch-v10/drivers/i2c.h
deleted file mode 100644
index de45c1ffbd7b..000000000000
--- a/arch/cris/arch-v10/drivers/i2c.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* i2c.h */
-int i2c_init(void);
-
-/* High level I2C actions */
-int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
-unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
-
-/* Low level I2C */
-void i2c_start(void);
-void i2c_stop(void);
-void i2c_outbyte(unsigned char x);
-unsigned char i2c_inbyte(void);
-int i2c_getack(void);
-void i2c_sendack(void);
-
-
-
diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c
deleted file mode 100644
index ed1a568a7217..000000000000
--- a/arch/cris/arch-v10/drivers/sync_serial.c
+++ /dev/null
@@ -1,1463 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Simple synchronous serial port driver for ETRAX 100LX.
- *
- * Synchronous serial ports are used for continuous streamed data like audio.
- * The default setting for this driver is compatible with the STA 013 MP3
- * decoder. The driver can easily be tuned to fit other audio encoder/decoders
- * and SPI
- *
- * Copyright (c) 2001-2008 Axis Communications AB
- *
- * Author: Mikael Starvik, Johan Adolfsson
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/major.h>
-#include <linux/sched/signal.h>
-#include <linux/interrupt.h>
-#include <linux/poll.h>
-#include <linux/init.h>
-#include <linux/mutex.h>
-#include <linux/timer.h>
-#include <linux/wait.h>
-#include <asm/irq.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <arch/svinto.h>
-#include <linux/uaccess.h>
-#include <asm/sync_serial.h>
-#include <arch/io_interface_mux.h>
-
-/* The receiver is a bit tricky because of the continuous stream of data.*/
-/* */
-/* Three DMA descriptors are linked together. Each DMA descriptor is */
-/* responsible for port->bufchunk of a common buffer. */
-/* */
-/* +---------------------------------------------+ */
-/* | +----------+ +----------+ +----------+ | */
-/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
-/* +----------+ +----------+ +----------+ */
-/* | | | */
-/* v v v */
-/* +-------------------------------------+ */
-/* | BUFFER | */
-/* +-------------------------------------+ */
-/* |<- data_avail ->| */
-/* readp writep */
-/* */
-/* If the application keeps up the pace readp will be right after writep.*/
-/* If the application can't keep the pace we have to throw away data. */
-/* The idea is that readp should be ready with the data pointed out by */
-/* Descr[i] when the DMA has filled in Descr[i+1]. */
-/* Otherwise we will discard */
-/* the rest of the data pointed out by Descr1 and set readp to the start */
-/* of Descr2 */
-
-#define SYNC_SERIAL_MAJOR 125
-
-/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
-/* words can be handled */
-#define IN_BUFFER_SIZE 12288
-#define IN_DESCR_SIZE 256
-#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
-#define OUT_BUFFER_SIZE 4096
-
-#define DEFAULT_FRAME_RATE 0
-#define DEFAULT_WORD_RATE 7
-
-/* NOTE: Enabling some debug will likely cause overrun or underrun,
- * especially if manual mode is use.
- */
-#define DEBUG(x)
-#define DEBUGREAD(x)
-#define DEBUGWRITE(x)
-#define DEBUGPOLL(x)
-#define DEBUGRXINT(x)
-#define DEBUGTXINT(x)
-
-/* Define some macros to access ETRAX 100 registers */
-#define SETF(var, reg, field, val) \
- do { \
- var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_FIELD_(reg##_, field##_, val); \
- } while (0)
-
-#define SETS(var, reg, field, val) \
- do { \
- var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_STATE_(reg##_, field##_, _##val); \
- } while (0)
-
-struct sync_port {
- /* Etrax registers and bits*/
- const volatile unsigned *const status;
- volatile unsigned *const ctrl_data;
- volatile unsigned *const output_dma_first;
- volatile unsigned char *const output_dma_cmd;
- volatile unsigned char *const output_dma_clr_irq;
- volatile unsigned *const input_dma_first;
- volatile unsigned char *const input_dma_cmd;
- volatile unsigned *const input_dma_descr;
- /* 8*4 */
- volatile unsigned char *const input_dma_clr_irq;
- volatile unsigned *const data_out;
- const volatile unsigned *const data_in;
- char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
- char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
- char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
-
- char output_dma_bit; /* In R_IRQ_MASK2_RD */
- /* End of fields initialised in array */
- char started; /* 1 if port has been started */
- char port_nbr; /* Port 0 or 1 */
- char busy; /* 1 if port is busy */
-
- char enabled; /* 1 if port is enabled */
- char use_dma; /* 1 if port uses dma */
- char tr_running;
-
- char init_irqs;
-
- /* Register shadow */
- unsigned int ctrl_data_shadow;
- /* Remaining bytes for current transfer */
- volatile unsigned int out_count;
- /* Current position in out_buffer */
- unsigned char *outp;
- /* 16*4 */
- /* Next byte to be read by application */
- volatile unsigned char *volatile readp;
- /* Next byte to be written by etrax */
- volatile unsigned char *volatile writep;
-
- unsigned int in_buffer_size;
- unsigned int inbufchunk;
- struct etrax_dma_descr out_descr __attribute__ ((aligned(32)));
- struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32)));
- unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
- unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
- unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
- struct etrax_dma_descr *next_rx_desc;
- struct etrax_dma_descr *prev_rx_desc;
- int full;
-
- wait_queue_head_t out_wait_q;
- wait_queue_head_t in_wait_q;
-};
-
-
-static DEFINE_MUTEX(sync_serial_mutex);
-static int etrax_sync_serial_init(void);
-static void initialize_port(int portnbr);
-static inline int sync_data_avail(struct sync_port *port);
-
-static int sync_serial_open(struct inode *inode, struct file *file);
-static int sync_serial_release(struct inode *inode, struct file *file);
-static __poll_t sync_serial_poll(struct file *filp, poll_table *wait);
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg);
-static ssize_t sync_serial_write(struct file *file, const char *buf,
- size_t count, loff_t *ppos);
-static ssize_t sync_serial_read(struct file *file, char *buf,
- size_t count, loff_t *ppos);
-
-#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
- (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
-#define SYNC_SER_DMA
-#endif
-
-static void send_word(struct sync_port *port);
-static void start_dma(struct sync_port *port, const char *data, int count);
-static void start_dma_in(struct sync_port *port);
-#ifdef SYNC_SER_DMA
-static irqreturn_t tr_interrupt(int irq, void *dev_id);
-static irqreturn_t rx_interrupt(int irq, void *dev_id);
-#endif
-#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
- !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
- (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
- !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
-#define SYNC_SER_MANUAL
-#endif
-#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id);
-#endif
-
-/* The ports */
-static struct sync_port ports[] = {
- {
- .status = R_SYNC_SERIAL1_STATUS,
- .ctrl_data = R_SYNC_SERIAL1_CTRL,
- .output_dma_first = R_DMA_CH8_FIRST,
- .output_dma_cmd = R_DMA_CH8_CMD,
- .output_dma_clr_irq = R_DMA_CH8_CLR_INTR,
- .input_dma_first = R_DMA_CH9_FIRST,
- .input_dma_cmd = R_DMA_CH9_CMD,
- .input_dma_descr = R_DMA_CH9_DESCR,
- .input_dma_clr_irq = R_DMA_CH9_CLR_INTR,
- .data_out = R_SYNC_SERIAL1_TR_DATA,
- .data_in = R_SYNC_SERIAL1_REC_DATA,
- .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data),
- .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),
- .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),
- .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),
- .init_irqs = 1,
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- },
- {
- .status = R_SYNC_SERIAL3_STATUS,
- .ctrl_data = R_SYNC_SERIAL3_CTRL,
- .output_dma_first = R_DMA_CH4_FIRST,
- .output_dma_cmd = R_DMA_CH4_CMD,
- .output_dma_clr_irq = R_DMA_CH4_CLR_INTR,
- .input_dma_first = R_DMA_CH5_FIRST,
- .input_dma_cmd = R_DMA_CH5_CMD,
- .input_dma_descr = R_DMA_CH5_DESCR,
- .input_dma_clr_irq = R_DMA_CH5_CLR_INTR,
- .data_out = R_SYNC_SERIAL3_TR_DATA,
- .data_in = R_SYNC_SERIAL3_REC_DATA,
- .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data),
- .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),
- .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),
- .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),
- .init_irqs = 1,
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
- .use_dma = 1,
-#else
- .use_dma = 0,
-#endif
- }
-};
-
-/* Register shadows */
-static unsigned sync_serial_prescale_shadow;
-
-#define NUMBER_OF_PORTS 2
-
-static const struct file_operations sync_serial_fops = {
- .owner = THIS_MODULE,
- .write = sync_serial_write,
- .read = sync_serial_read,
- .poll = sync_serial_poll,
- .unlocked_ioctl = sync_serial_ioctl,
- .open = sync_serial_open,
- .release = sync_serial_release,
- .llseek = noop_llseek,
-};
-
-static int __init etrax_sync_serial_init(void)
-{
- ports[0].enabled = 0;
- ports[1].enabled = 0;
-
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) {
- printk(KERN_CRIT "ETRAX100LX sync_serial: "
- "Could not allocate IO group for port %d\n", 0);
- return -EBUSY;
- }
-#endif
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) {
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- cris_free_io_interface(if_sync_serial_1);
-#endif
- printk(KERN_CRIT "ETRAX100LX sync_serial: "
- "Could not allocate IO group for port %d\n", 1);
- return -EBUSY;
- }
-#endif
-
- if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
- &sync_serial_fops) < 0) {
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- cris_free_io_interface(if_sync_serial_3);
-#endif
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- cris_free_io_interface(if_sync_serial_1);
-#endif
- printk("unable to get major for synchronous serial port\n");
- return -EBUSY;
- }
-
- /* Deselect synchronous serial ports while configuring. */
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
-
- /* Initialize Ports */
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- ports[0].enabled = 1;
- SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
- ports[0].use_dma = 1;
-#else
- ports[0].use_dma = 0;
-#endif
- initialize_port(0);
-#endif
-
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- ports[1].enabled = 1;
- SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
- ports[1].use_dma = 1;
-#else
- ports[1].use_dma = 0;
-#endif
- initialize_port(1);
-#endif
-
- *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
-
- /* Set up timing */
- *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
- IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
- IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate,
- DEFAULT_FRAME_RATE) |
- IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
- IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
-
- /* Select synchronous ports */
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
-
- printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n");
- return 0;
-}
-
-static void __init initialize_port(int portnbr)
-{
- struct sync_port *port = &ports[portnbr];
-
- DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
-
- port->started = 0;
- port->port_nbr = portnbr;
- port->busy = 0;
- port->tr_running = 0;
-
- port->out_count = 0;
- port->outp = port->out_buffer;
-
- port->readp = port->flip;
- port->writep = port->flip;
- port->in_buffer_size = IN_BUFFER_SIZE;
- port->inbufchunk = IN_DESCR_SIZE;
- port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
- port->prev_rx_desc->ctrl = d_eol;
-
- init_waitqueue_head(&port->out_wait_q);
- init_waitqueue_head(&port->in_wait_q);
-
- port->ctrl_data_shadow =
- IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
- IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
- IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
- IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
- IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
-
- if (port->use_dma)
- port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
- dma_enable, on);
- else
- port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
- dma_enable, off);
-
- *port->ctrl_data = port->ctrl_data_shadow;
-}
-
-static inline int sync_data_avail(struct sync_port *port)
-{
- int avail;
- unsigned char *start;
- unsigned char *end;
-
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- /* 0123456789 0123456789
- * ----- - -----
- * ^rp ^wp ^wp ^rp
- */
- if (end >= start)
- avail = end - start;
- else
- avail = port->in_buffer_size - (start - end);
- return avail;
-}
-
-static inline int sync_data_avail_to_end(struct sync_port *port)
-{
- int avail;
- unsigned char *start;
- unsigned char *end;
-
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- /* 0123456789 0123456789
- * ----- -----
- * ^rp ^wp ^wp ^rp
- */
-
- if (end >= start)
- avail = end - start;
- else
- avail = port->flip + port->in_buffer_size - start;
- return avail;
-}
-
-
-static int sync_serial_open(struct inode *inode, struct file *file)
-{
- int dev = MINOR(inode->i_rdev);
- struct sync_port *port;
- int mode;
- int err = -EBUSY;
-
- mutex_lock(&sync_serial_mutex);
- DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- err = -ENODEV;
- goto out;
- }
- port = &ports[dev];
- /* Allow open this device twice (assuming one reader and one writer) */
- if (port->busy == 2) {
- DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
- goto out;
- }
- if (port->init_irqs) {
- if (port->use_dma) {
- if (port == &ports[0]) {
-#ifdef SYNC_SER_DMA
- if (request_irq(24, tr_interrupt, 0,
- "synchronous serial 1 dma tr",
- &ports[0])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 IRQ");
- goto out;
- } else if (request_irq(25, rx_interrupt, 0,
- "synchronous serial 1 dma rx",
- &ports[0])) {
- free_irq(24, &port[0]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 IRQ");
- goto out;
- } else if (cris_request_dma(8,
- "synchronous serial 1 dma tr",
- DMA_VERBOSE_ON_ERROR,
- dma_ser1)) {
- free_irq(24, &port[0]);
- free_irq(25, &port[0]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 "
- "TX DMA channel");
- goto out;
- } else if (cris_request_dma(9,
- "synchronous serial 1 dma rec",
- DMA_VERBOSE_ON_ERROR,
- dma_ser1)) {
- cris_free_dma(8, NULL);
- free_irq(24, &port[0]);
- free_irq(25, &port[0]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 1 "
- "RX DMA channel");
- goto out;
- }
-#endif
- RESET_DMA(8); WAIT_DMA(8);
- RESET_DMA(9); WAIT_DMA(9);
- *R_DMA_CH8_CLR_INTR =
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr,
- do);
- *R_DMA_CH9_CLR_INTR =
- IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr,
- do);
- *R_IRQ_MASK2_SET =
- IO_STATE(R_IRQ_MASK2_SET, dma8_eop,
- set) |
- IO_STATE(R_IRQ_MASK2_SET, dma9_descr,
- set);
- } else if (port == &ports[1]) {
-#ifdef SYNC_SER_DMA
- if (request_irq(20, tr_interrupt, 0,
- "synchronous serial 3 dma tr",
- &ports[1])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 IRQ");
- goto out;
- } else if (request_irq(21, rx_interrupt, 0,
- "synchronous serial 3 dma rx",
- &ports[1])) {
- free_irq(20, &ports[1]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 IRQ");
- goto out;
- } else if (cris_request_dma(4,
- "synchronous serial 3 dma tr",
- DMA_VERBOSE_ON_ERROR,
- dma_ser3)) {
- free_irq(21, &ports[1]);
- free_irq(20, &ports[1]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 "
- "TX DMA channel");
- goto out;
- } else if (cris_request_dma(5,
- "synchronous serial 3 dma rec",
- DMA_VERBOSE_ON_ERROR,
- dma_ser3)) {
- cris_free_dma(4, NULL);
- free_irq(21, &ports[1]);
- free_irq(20, &ports[1]);
- printk(KERN_CRIT "Can't alloc "
- "sync serial port 3 "
- "RX DMA channel");
- goto out;
- }
-#endif
- RESET_DMA(4); WAIT_DMA(4);
- RESET_DMA(5); WAIT_DMA(5);
- *R_DMA_CH4_CLR_INTR =
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr,
- do);
- *R_DMA_CH5_CLR_INTR =
- IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop,
- do) |
- IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr,
- do);
- *R_IRQ_MASK2_SET =
- IO_STATE(R_IRQ_MASK2_SET, dma4_eop,
- set) |
- IO_STATE(R_IRQ_MASK2_SET, dma5_descr,
- set);
- }
- start_dma_in(port);
- port->init_irqs = 0;
- } else { /* !port->use_dma */
-#ifdef SYNC_SER_MANUAL
- if (port == &ports[0]) {
- if (request_irq(8,
- manual_interrupt,
- IRQF_SHARED,
- "synchronous serial manual irq",
- &ports[0])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial manual irq");
- goto out;
- }
- } else if (port == &ports[1]) {
- if (request_irq(8,
- manual_interrupt,
- IRQF_SHARED,
- "synchronous serial manual irq",
- &ports[1])) {
- printk(KERN_CRIT "Can't alloc "
- "sync serial manual irq");
- goto out;
- }
- }
- port->init_irqs = 0;
-#else
- panic("sync_serial: Manual mode not supported.\n");
-#endif /* SYNC_SER_MANUAL */
- }
- } /* port->init_irqs */
-
- port->busy++;
- /* Start port if we use it as input */
- mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow);
- if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) ||
- mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) ||
- mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) ||
- mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
- running);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
- enable);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
- enable);
- port->started = 1;
- *port->ctrl_data = port->ctrl_data_shadow;
- if (!port->use_dma)
- *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
- DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev));
- }
- err = 0;
-
-out:
- mutex_unlock(&sync_serial_mutex);
- return err;
-}
-
-static int sync_serial_release(struct inode *inode, struct file *file)
-{
- int dev = MINOR(inode->i_rdev);
- struct sync_port *port;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
- if (port->busy)
- port->busy--;
- if (!port->busy)
- *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) |
- (1 << port->transmitter_ready_bit));
-
- return 0;
-}
-
-
-
-static __poll_t sync_serial_poll(struct file *file, poll_table *wait)
-{
- int dev = MINOR(file_inode(file)->i_rdev);
- __poll_t mask = 0;
- struct sync_port *port;
- DEBUGPOLL(static __poll_t prev_mask = 0);
-
- port = &ports[dev];
- poll_wait(file, &port->out_wait_q, wait);
- poll_wait(file, &port->in_wait_q, wait);
- /* Some room to write */
- if (port->out_count < OUT_BUFFER_SIZE)
- mask |= EPOLLOUT | EPOLLWRNORM;
- /* At least an inbufchunk of data */
- if (sync_data_avail(port) >= port->inbufchunk)
- mask |= EPOLLIN | EPOLLRDNORM;
-
- DEBUGPOLL(if (mask != prev_mask)
- printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n",
- mask,
- mask & EPOLLOUT ? "POLLOUT" : "",
- mask & EPOLLIN ? "POLLIN" : "");
- prev_mask = mask;
- );
- return mask;
-}
-
-static int sync_serial_ioctl_unlocked(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int return_val = 0;
- unsigned long flags;
-
- int dev = MINOR(file_inode(file)->i_rdev);
- struct sync_port *port;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -1;
- }
- port = &ports[dev];
-
- local_irq_save(flags);
- /* Disable port while changing config */
- if (dev) {
- if (port->use_dma) {
- RESET_DMA(4); WAIT_DMA(4);
- port->tr_running = 0;
- port->out_count = 0;
- port->outp = port->out_buffer;
- *R_DMA_CH4_CLR_INTR =
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
- IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
- }
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
- } else {
- if (port->use_dma) {
- RESET_DMA(8); WAIT_DMA(8);
- port->tr_running = 0;
- port->out_count = 0;
- port->outp = port->out_buffer;
- *R_DMA_CH8_CLR_INTR =
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
- IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
- }
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
- }
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
- local_irq_restore(flags);
-
- switch (cmd) {
- case SSP_SPEED:
- if (GET_SPEED(arg) == CODEC) {
- if (dev)
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
- codec);
- else
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
- codec);
-
- SETF(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, prescaler,
- GET_FREQ(arg));
- SETF(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, frame_rate,
- GET_FRAME_RATE(arg));
- SETF(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, word_rate,
- GET_WORD_RATE(arg));
- } else {
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- tr_baud, GET_SPEED(arg));
- if (dev)
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
- baudrate);
- else
- SETS(sync_serial_prescale_shadow,
- R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
- baudrate);
- }
- break;
- case SSP_MODE:
- if (arg > 5)
- return -EINVAL;
- if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)
- *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit;
- else if (!port->use_dma)
- *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
- break;
- case SSP_FRAME_SYNC:
- if (arg & NORMAL_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_synctype, normal);
- else if (arg & EARLY_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_synctype, early);
-
- if (arg & BIT_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_syncsize, bit);
- else if (arg & WORD_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_syncsize, word);
- else if (arg & EXTENDED_SYNC)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_syncsize, extended);
-
- if (arg & SYNC_ON)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_sync, on);
- else if (arg & SYNC_OFF)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- f_sync, off);
-
- if (arg & WORD_SIZE_8)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size8bit);
- else if (arg & WORD_SIZE_12)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size12bit);
- else if (arg & WORD_SIZE_16)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size16bit);
- else if (arg & WORD_SIZE_24)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size24bit);
- else if (arg & WORD_SIZE_32)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- wordsize, size32bit);
-
- if (arg & BIT_ORDER_MSB)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- bitorder, msb);
- else if (arg & BIT_ORDER_LSB)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- bitorder, lsb);
-
- if (arg & FLOW_CONTROL_ENABLE)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- flow_ctrl, enabled);
- else if (arg & FLOW_CONTROL_DISABLE)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- flow_ctrl, disabled);
-
- if (arg & CLOCK_NOT_GATED)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_mode, normal);
- else if (arg & CLOCK_GATED)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_mode, gated);
-
- break;
- case SSP_IPOLARITY:
- /* NOTE!! negedge is considered NORMAL */
- if (arg & CLOCK_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_polarity, neg);
- else if (arg & CLOCK_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_polarity, pos);
-
- if (arg & FRAME_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_polarity, normal);
- else if (arg & FRAME_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_polarity, inverted);
-
- if (arg & STATUS_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_polarity, normal);
- else if (arg & STATUS_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_polarity, inverted);
- break;
- case SSP_OPOLARITY:
- if (arg & CLOCK_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_driver, normal);
- else if (arg & CLOCK_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_driver, inverted);
-
- if (arg & FRAME_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_driver, normal);
- else if (arg & FRAME_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_driver, inverted);
-
- if (arg & STATUS_NORMAL)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_driver, normal);
- else if (arg & STATUS_INVERT)
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- status_driver, inverted);
- break;
- case SSP_SPI:
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl,
- disabled);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder,
- msb);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize,
- size8bit);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize,
- word);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype,
- normal);
- if (arg & SPI_SLAVE) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_polarity, inverted);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_polarity, neg);
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- mode, SLAVE_INPUT);
- } else {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- frame_driver, inverted);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- clk_driver, inverted);
- SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
- mode, MASTER_OUTPUT);
- }
- break;
- case SSP_INBUFCHUNK:
-#if 0
- if (arg > port->in_buffer_size/NUM_IN_DESCR)
- return -EINVAL;
- port->inbufchunk = arg;
- /* Make sure in_buffer_size is a multiple of inbufchunk */
- port->in_buffer_size =
- (port->in_buffer_size/port->inbufchunk) *
- port->inbufchunk;
- DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n",
- port->inbufchunk, port->in_buffer_size));
- if (port->use_dma) {
- if (port->port_nbr == 0) {
- RESET_DMA(9);
- WAIT_DMA(9);
- } else {
- RESET_DMA(5);
- WAIT_DMA(5);
- }
- start_dma_in(port);
- }
-#endif
- break;
- default:
- return_val = -1;
- }
- /* Make sure we write the config without interruption */
- local_irq_save(flags);
- /* Set config and enable port */
- *port->ctrl_data = port->ctrl_data_shadow;
- nop(); nop(); nop(); nop();
- *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
- nop(); nop(); nop(); nop();
- if (dev)
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
- else
- SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
-
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
- /* Reset DMA. At readout from serial port the data could be shifted
- * one byte if not resetting DMA.
- */
- if (port->use_dma) {
- if (port->port_nbr == 0) {
- RESET_DMA(9);
- WAIT_DMA(9);
- } else {
- RESET_DMA(5);
- WAIT_DMA(5);
- }
- start_dma_in(port);
- }
- local_irq_restore(flags);
- return return_val;
-}
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- long ret;
-
- mutex_lock(&sync_serial_mutex);
- ret = sync_serial_ioctl_unlocked(file, cmd, arg);
- mutex_unlock(&sync_serial_mutex);
-
- return ret;
-}
-
-
-static ssize_t sync_serial_write(struct file *file, const char *buf,
- size_t count, loff_t *ppos)
-{
- int dev = MINOR(file_inode(file)->i_rdev);
- DECLARE_WAITQUEUE(wait, current);
- struct sync_port *port;
- unsigned long flags;
- unsigned long c, c1;
- unsigned long free_outp;
- unsigned long outp;
- unsigned long out_buffer;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n",
- port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
- /* Space to end of buffer */
- /*
- * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE
- * outp^ +out_count
- * ^free_outp
- * out_buffer 45<- c ->0123OUT_BUFFER_SIZE
- * +out_count outp^
- * free_outp
- *
- */
-
- /* Read variables that may be updated by interrupts */
- local_irq_save(flags);
- if (count > OUT_BUFFER_SIZE - port->out_count)
- count = OUT_BUFFER_SIZE - port->out_count;
-
- outp = (unsigned long)port->outp;
- free_outp = outp + port->out_count;
- local_irq_restore(flags);
- out_buffer = (unsigned long)port->out_buffer;
-
- /* Find out where and how much to write */
- if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
- free_outp -= OUT_BUFFER_SIZE;
- if (free_outp >= outp)
- c = out_buffer + OUT_BUFFER_SIZE - free_outp;
- else
- c = outp - free_outp;
- if (c > count)
- c = count;
-
- DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n",
- outp, free_outp, c));
- if (copy_from_user((void *)free_outp, buf, c))
- return -EFAULT;
-
- if (c != count) {
- buf += c;
- c1 = count - c;
- DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n",
- free_outp-out_buffer, c, c1));
- if (copy_from_user((void *)out_buffer, buf, c1))
- return -EFAULT;
- }
- local_irq_save(flags);
- port->out_count += count;
- local_irq_restore(flags);
-
- /* Make sure transmitter/receiver is running */
- if (!port->started) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
- running);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
- enable);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
- enable);
- port->started = 1;
- }
-
- *port->ctrl_data = port->ctrl_data_shadow;
-
- if (file->f_flags & O_NONBLOCK) {
- local_irq_save(flags);
- if (!port->tr_running) {
- if (!port->use_dma) {
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- *R_IRQ_MASK1_SET = 1 <<
- port->transmitter_ready_bit;
- } else
- start_dma(port,
- (unsigned char *volatile)port->outp, c);
- }
- local_irq_restore(flags);
- DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n",
- port->port_nbr, count));
- return count;
- }
-
- /* Sleep until all sent */
- add_wait_queue(&port->out_wait_q, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
- local_irq_save(flags);
- if (!port->tr_running) {
- if (!port->use_dma) {
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
- } else
- start_dma(port, port->outp, c);
- }
- local_irq_restore(flags);
- schedule();
- remove_wait_queue(&port->out_wait_q, &wait);
- if (signal_pending(current))
- return -EINTR;
-
- DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count));
- return count;
-}
-
-static ssize_t sync_serial_read(struct file *file, char *buf,
- size_t count, loff_t *ppos)
-{
- int dev = MINOR(file_inode(file)->i_rdev);
- int avail;
- struct sync_port *port;
- unsigned char *start;
- unsigned char *end;
- unsigned long flags;
-
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
- DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n",
- dev, count, port->readp - port->flip,
- port->writep - port->flip, port->in_buffer_size));
-
- if (!port->started) {
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
- running);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
- enable);
- SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
- enable);
- port->started = 1;
- }
- *port->ctrl_data = port->ctrl_data_shadow;
-
- /* Calculate number of available bytes */
- /* Save pointers to avoid that they are modified by interrupt */
- local_irq_save(flags);
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- local_irq_restore(flags);
- while (start == end && !port->full) {
- /* No data */
- if (file->f_flags & O_NONBLOCK)
- return -EAGAIN;
-
- wait_event_interruptible(port->in_wait_q,
- !(start == end && !port->full));
- if (signal_pending(current))
- return -EINTR;
-
- local_irq_save(flags);
- start = (unsigned char *)port->readp; /* cast away volatile */
- end = (unsigned char *)port->writep; /* cast away volatile */
- local_irq_restore(flags);
- }
-
- /* Lazy read, never return wrapped data. */
- if (port->full)
- avail = port->in_buffer_size;
- else if (end > start)
- avail = end - start;
- else
- avail = port->flip + port->in_buffer_size - start;
-
- count = count > avail ? avail : count;
- if (copy_to_user(buf, start, count))
- return -EFAULT;
- /* Disable interrupts while updating readp */
- local_irq_save(flags);
- port->readp += count;
- if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
- port->readp = port->flip;
- port->full = 0;
- local_irq_restore(flags);
- DEBUGREAD(printk(KERN_DEBUG "r %d\n", count));
- return count;
-}
-
-static void send_word(struct sync_port *port)
-{
- switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize,
- port->ctrl_data_shadow)) {
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
- port->out_count--;
- *port->data_out = *port->outp++;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
- {
- int data = (*port->outp++) << 8;
- data |= *port->outp++;
- port->out_count -= 2;
- *port->data_out = data;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- }
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
- port->out_count -= 2;
- *port->data_out = *(unsigned short *)port->outp;
- port->outp += 2;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
- port->out_count -= 3;
- *port->data_out = *(unsigned int *)port->outp;
- port->outp += 3;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
- port->out_count -= 4;
- *port->data_out = *(unsigned int *)port->outp;
- port->outp += 4;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- break;
- }
-}
-
-
-static void start_dma(struct sync_port *port, const char *data, int count)
-{
- port->tr_running = 1;
- port->out_descr.hw_len = 0;
- port->out_descr.next = 0;
- port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */
- port->out_descr.sw_len = count;
- port->out_descr.buf = virt_to_phys(data);
- port->out_descr.status = 0;
-
- *port->output_dma_first = virt_to_phys(&port->out_descr);
- *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
- DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n",
- (unsigned long)data, count));
-}
-
-static void start_dma_in(struct sync_port *port)
-{
- int i;
- unsigned long buf;
- port->writep = port->flip;
-
- if (port->writep > port->flip + port->in_buffer_size) {
- panic("Offset too large in sync serial driver\n");
- return;
- }
- buf = virt_to_phys(port->in_buffer);
- for (i = 0; i < NUM_IN_DESCR; i++) {
- port->in_descr[i].sw_len = port->inbufchunk;
- port->in_descr[i].ctrl = d_int;
- port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]);
- port->in_descr[i].buf = buf;
- port->in_descr[i].hw_len = 0;
- port->in_descr[i].status = 0;
- port->in_descr[i].fifo_len = 0;
- buf += port->inbufchunk;
- prepare_rx_descriptor(&port->in_descr[i]);
- }
- /* Link the last descriptor to the first */
- port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]);
- port->in_descr[i-1].ctrl |= d_eol;
- port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
- *port->input_dma_first = virt_to_phys(port->next_rx_desc);
- *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
-}
-
-#ifdef SYNC_SER_DMA
-static irqreturn_t tr_interrupt(int irq, void *dev_id)
-{
- unsigned long ireg = *R_IRQ_MASK2_RD;
- struct etrax_dma_descr *descr;
- unsigned int sentl;
- int handled = 0;
- int i;
-
- for (i = 0; i < NUMBER_OF_PORTS; i++) {
- struct sync_port *port = &ports[i];
- if (!port->enabled || !port->use_dma)
- continue;
-
- /* IRQ active for the port? */
- if (!(ireg & (1 << port->output_dma_bit)))
- continue;
-
- handled = 1;
-
- /* Clear IRQ */
- *port->output_dma_clr_irq =
- IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
- IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
-
- descr = &port->out_descr;
- if (!(descr->status & d_stop))
- sentl = descr->sw_len;
- else
- /* Otherwise find amount of data sent here */
- sentl = descr->hw_len;
-
- port->out_count -= sentl;
- port->outp += sentl;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- if (port->out_count) {
- int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
- if (c > port->out_count)
- c = port->out_count;
- DEBUGTXINT(printk(KERN_DEBUG
- "tx_int DMAWRITE %i %i\n", sentl, c));
- start_dma(port, port->outp, c);
- } else {
- DEBUGTXINT(printk(KERN_DEBUG
- "tx_int DMA stop %i\n", sentl));
- port->tr_running = 0;
- }
- /* wake up the waiting process */
- wake_up_interruptible(&port->out_wait_q);
- }
- return IRQ_RETVAL(handled);
-} /* tr_interrupt */
-
-static irqreturn_t rx_interrupt(int irq, void *dev_id)
-{
- unsigned long ireg = *R_IRQ_MASK2_RD;
- int i;
- int handled = 0;
-
- for (i = 0; i < NUMBER_OF_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || !port->use_dma)
- continue;
-
- if (!(ireg & (1 << port->input_dma_descr_bit)))
- continue;
-
- /* Descriptor interrupt */
- handled = 1;
- while (*port->input_dma_descr !=
- virt_to_phys(port->next_rx_desc)) {
- if (port->writep + port->inbufchunk > port->flip +
- port->in_buffer_size) {
- int first_size = port->flip +
- port->in_buffer_size - port->writep;
- memcpy(port->writep,
- phys_to_virt(port->next_rx_desc->buf),
- first_size);
- memcpy(port->flip,
- phys_to_virt(port->next_rx_desc->buf +
- first_size),
- port->inbufchunk - first_size);
- port->writep = port->flip +
- port->inbufchunk - first_size;
- } else {
- memcpy(port->writep,
- phys_to_virt(port->next_rx_desc->buf),
- port->inbufchunk);
- port->writep += port->inbufchunk;
- if (port->writep >= port->flip
- + port->in_buffer_size)
- port->writep = port->flip;
- }
- if (port->writep == port->readp)
- port->full = 1;
- prepare_rx_descriptor(port->next_rx_desc);
- port->next_rx_desc->ctrl |= d_eol;
- port->prev_rx_desc->ctrl &= ~d_eol;
- port->prev_rx_desc = phys_to_virt((unsigned)
- port->next_rx_desc);
- port->next_rx_desc = phys_to_virt((unsigned)
- port->next_rx_desc->next);
- /* Wake up the waiting process */
- wake_up_interruptible(&port->in_wait_q);
- *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD,
- cmd, restart);
- /* DMA has reached end of descriptor */
- *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR,
- clr_descr, do);
- }
- }
- return IRQ_RETVAL(handled);
-} /* rx_interrupt */
-#endif /* SYNC_SER_DMA */
-
-#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id)
-{
- int i;
- int handled = 0;
-
- for (i = 0; i < NUMBER_OF_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || port->use_dma)
- continue;
-
- /* Data received? */
- if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) {
- handled = 1;
- /* Read data */
- switch (port->ctrl_data_shadow &
- IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) {
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
- *port->writep++ =
- *(volatile char *)port->data_in;
- break;
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
- {
- int data = *(unsigned short *)port->data_in;
- *port->writep = (data & 0x0ff0) >> 4;
- *(port->writep + 1) = data & 0x0f;
- port->writep += 2;
- break;
- }
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
- *(unsigned short *)port->writep =
- *(volatile unsigned short *)port->data_in;
- port->writep += 2;
- break;
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
- *(unsigned int *)port->writep = *port->data_in;
- port->writep += 3;
- break;
- case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
- *(unsigned int *)port->writep = *port->data_in;
- port->writep += 4;
- break;
- }
-
- /* Wrap? */
- if (port->writep >= port->flip + port->in_buffer_size)
- port->writep = port->flip;
- if (port->writep == port->readp) {
- /* Receive buffer overrun, discard oldest */
- port->readp++;
- /* Wrap? */
- if (port->readp >= port->flip +
- port->in_buffer_size)
- port->readp = port->flip;
- }
- if (sync_data_avail(port) >= port->inbufchunk) {
- /* Wake up application */
- wake_up_interruptible(&port->in_wait_q);
- }
- }
-
- /* Transmitter ready? */
- if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) {
- if (port->out_count > 0) {
- /* More data to send */
- send_word(port);
- } else {
- /* Transmission finished */
- /* Turn off IRQ */
- *R_IRQ_MASK1_CLR = 1 <<
- port->transmitter_ready_bit;
- /* Wake up application */
- wake_up_interruptible(&port->out_wait_q);
- }
- }
- }
- return IRQ_RETVAL(handled);
-}
-#endif
-
-module_init(etrax_sync_serial_init);
diff --git a/arch/cris/arch-v10/kernel/Makefile b/arch/cris/arch-v10/kernel/Makefile
deleted file mode 100644
index 7ec04b4a285e..000000000000
--- a/arch/cris/arch-v10/kernel/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-extra-y := head.o
-
-
-obj-y := entry.o traps.o shadows.o debugport.o irq.o \
- process.o setup.o signal.o traps.o time.o ptrace.o \
- dma.o io_interface_mux.o
-
-obj-$(CONFIG_ETRAX_KGDB) += kgdb.o
-obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
-obj-$(CONFIG_MODULES) += crisksyms.o
-
-clean:
-
diff --git a/arch/cris/arch-v10/kernel/crisksyms.c b/arch/cris/arch-v10/kernel/crisksyms.c
deleted file mode 100644
index e1d897ed5b37..000000000000
--- a/arch/cris/arch-v10/kernel/crisksyms.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <asm/io.h>
-#include <arch/svinto.h>
-
-/* Export shadow registers for the CPU I/O pins */
-EXPORT_SYMBOL(genconfig_shadow);
-EXPORT_SYMBOL(port_pa_data_shadow);
-EXPORT_SYMBOL(port_pa_dir_shadow);
-EXPORT_SYMBOL(port_pb_data_shadow);
-EXPORT_SYMBOL(port_pb_dir_shadow);
-EXPORT_SYMBOL(port_pb_config_shadow);
-EXPORT_SYMBOL(port_g_data_shadow);
-
-/* Cache flush functions */
-EXPORT_SYMBOL(flush_etrax_cache);
-EXPORT_SYMBOL(prepare_rx_descriptor);
diff --git a/arch/cris/arch-v10/kernel/debugport.c b/arch/cris/arch-v10/kernel/debugport.c
deleted file mode 100644
index d30834d4dd7e..000000000000
--- a/arch/cris/arch-v10/kernel/debugport.c
+++ /dev/null
@@ -1,560 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Serialport functions for debugging
- *
- * Copyright (c) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- * Exports:
- * console_print_etrax(char *buf)
- * int getDebugChar()
- * putDebugChar(int)
- * enableDebugIRQ()
- * init_etrax_debug()
- *
- */
-
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/delay.h>
-#include <linux/tty.h>
-#include <arch/svinto.h>
-
-extern void reset_watchdog(void);
-
-struct dbg_port
-{
- unsigned int index;
- const volatile unsigned* read;
- volatile char* write;
- volatile unsigned* xoff;
- volatile char* baud;
- volatile char* tr_ctrl;
- volatile char* rec_ctrl;
- unsigned long irq;
- unsigned int started;
- unsigned long baudrate;
- unsigned char parity;
- unsigned int bits;
-};
-
-struct dbg_port ports[]=
-{
- {
- 0,
- R_SERIAL0_READ,
- R_SERIAL0_TR_DATA,
- R_SERIAL0_XOFF,
- R_SERIAL0_BAUD,
- R_SERIAL0_TR_CTRL,
- R_SERIAL0_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser0_data, set),
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 1,
- R_SERIAL1_READ,
- R_SERIAL1_TR_DATA,
- R_SERIAL1_XOFF,
- R_SERIAL1_BAUD,
- R_SERIAL1_TR_CTRL,
- R_SERIAL1_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser1_data, set),
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 2,
- R_SERIAL2_READ,
- R_SERIAL2_TR_DATA,
- R_SERIAL2_XOFF,
- R_SERIAL2_BAUD,
- R_SERIAL2_TR_CTRL,
- R_SERIAL2_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser2_data, set),
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 3,
- R_SERIAL3_READ,
- R_SERIAL3_TR_DATA,
- R_SERIAL3_XOFF,
- R_SERIAL3_BAUD,
- R_SERIAL3_TR_CTRL,
- R_SERIAL3_REC_CTRL,
- IO_STATE(R_IRQ_MASK1_SET, ser3_data, set),
- 0,
- 115200,
- 'N',
- 8
- }
-};
-
-#ifdef CONFIG_ETRAX_SERIAL
-extern struct tty_driver *serial_driver;
-#endif
-
-struct dbg_port* port =
-#if defined(CONFIG_ETRAX_DEBUG_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- &ports[3];
-#else
- NULL;
-#endif
-
-static struct dbg_port* kgdb_port =
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- &ports[3];
-#else
- NULL;
-#endif
-
-static void
-start_port(struct dbg_port* p)
-{
- unsigned long rec_ctrl = 0;
- unsigned long tr_ctrl = 0;
-
- if (!p)
- return;
-
- if (p->started)
- return;
- p->started = 1;
-
- if (p->index == 0)
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
- }
- else if (p->index == 1)
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
- }
- else if (p->index == 2)
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser2, select);
- }
- else
- {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
- genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser3, select);
- }
-
- *R_GEN_CONFIG = genconfig_shadow;
-
- *p->xoff =
- IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) |
- IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) |
- IO_FIELD(R_SERIAL0_XOFF, xoff_char, 0);
-
- switch (p->baudrate)
- {
- case 0:
- case 115200:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz);
- break;
- case 1200:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz);
- break;
- case 2400:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz);
- break;
- case 4800:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz);
- break;
- case 9600:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz);
- break;
- case 19200:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz);
- break;
- case 38400:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz);
- break;
- case 57600:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz);
- break;
- default:
- *p->baud =
- IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) |
- IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz);
- break;
- }
-
- if (p->parity == 'E') {
- rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
- tr_ctrl =
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
- } else if (p->parity == 'O') {
- rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
- tr_ctrl =
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
- } else {
- rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, disable);
- tr_ctrl =
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable);
- }
- if (p->bits == 7)
- {
- rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
- tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
- }
- else
- {
- rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit);
- tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit);
- }
-
- *p->rec_ctrl =
- IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) |
- IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) |
- IO_STATE(R_SERIAL0_REC_CTRL, sampling, middle) |
- IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) |
- rec_ctrl;
-
- *p->tr_ctrl =
- IO_FIELD(R_SERIAL0_TR_CTRL, txd, 0) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) |
- IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) |
- IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, one_bit) |
- IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, normal) |
- tr_ctrl;
-}
-
-static void
-console_write_direct(struct console *co, const char *buf, unsigned int len)
-{
- int i;
- unsigned long flags;
-
- if (!port)
- return;
-
- local_irq_save(flags);
-
- /* Send data */
- for (i = 0; i < len; i++) {
- /* LF -> CRLF */
- if (buf[i] == '\n') {
- while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
- ;
- *port->write = '\r';
- }
- /* Wait until transmitter is ready and send.*/
- while (!(*port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
- ;
- *port->write = buf[i];
- }
-
- /*
- * Feed the watchdog, otherwise it will reset the chip during boot.
- * The time to send an ordinary boot message line (10-90 chars)
- * varies between 1-8ms at 115200. What makes up for the additional
- * 90ms that allows the watchdog to bite?
- */
- reset_watchdog();
-
- local_irq_restore(flags);
-}
-
-static void
-console_write(struct console *co, const char *buf, unsigned int len)
-{
- if (!port)
- return;
-
- console_write_direct(co, buf, len);
-}
-
-/* legacy function */
-
-void
-console_print_etrax(const char *buf)
-{
- console_write(NULL, buf, strlen(buf));
-}
-
-/* Use polling to get a single character FROM the debug port */
-
-int
-getDebugChar(void)
-{
- unsigned long readval;
-
- if (!kgdb_port)
- return 0;
-
- do {
- readval = *kgdb_port->read;
- } while (!(readval & IO_MASK(R_SERIAL0_READ, data_avail)));
-
- return (readval & IO_MASK(R_SERIAL0_READ, data_in));
-}
-
-/* Use polling to put a single character to the debug port */
-
-void
-putDebugChar(int val)
-{
- if (!kgdb_port)
- return;
-
- while (!(*kgdb_port->read & IO_MASK(R_SERIAL0_READ, tr_ready)))
- ;
- *kgdb_port->write = val;
-}
-
-/* Enable irq for receiving chars on the debug port, used by kgdb */
-
-void
-enableDebugIRQ(void)
-{
- if (!kgdb_port)
- return;
-
- *R_IRQ_MASK1_SET = kgdb_port->irq;
- /* use R_VECT_MASK directly, since we really bypass Linux normal
- * IRQ handling in kgdb anyway, we don't need to use enable_irq
- */
- *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
-
- *kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
-}
-
-static int __init
-console_setup(struct console *co, char *options)
-{
- char* s;
-
- if (options) {
- port = &ports[co->index];
- port->baudrate = 115200;
- port->parity = 'N';
- port->bits = 8;
- port->baudrate = simple_strtoul(options, NULL, 10);
- s = options;
- while(*s >= '0' && *s <= '9')
- s++;
- if (*s) port->parity = *s++;
- if (*s) port->bits = *s++ - '0';
- port->started = 0;
- start_port(0);
- }
- return 0;
-}
-
-
-/* This is a dummy serial device that throws away anything written to it.
- * This is used when no debug output is wanted.
- */
-static struct tty_driver dummy_driver;
-
-static int dummy_open(struct tty_struct *tty, struct file * filp)
-{
- return 0;
-}
-
-static void dummy_close(struct tty_struct *tty, struct file * filp)
-{
-}
-
-static int dummy_write(struct tty_struct * tty,
- const unsigned char *buf, int count)
-{
- return count;
-}
-
-static int dummy_write_room(struct tty_struct *tty)
-{
- return 8192;
-}
-
-static const struct tty_operations dummy_ops = {
- .open = dummy_open,
- .close = dummy_close,
- .write = dummy_write,
- .write_room = dummy_write_room,
-};
-
-void __init
-init_dummy_console(void)
-{
- memset(&dummy_driver, 0, sizeof(struct tty_driver));
- dummy_driver.driver_name = "serial";
- dummy_driver.name = "ttyS";
- dummy_driver.major = TTY_MAJOR;
- dummy_driver.minor_start = 68;
- dummy_driver.num = 1; /* etrax100 has 4 serial ports */
- dummy_driver.type = TTY_DRIVER_TYPE_SERIAL;
- dummy_driver.subtype = SERIAL_TYPE_NORMAL;
- dummy_driver.init_termios = tty_std_termios;
- /* Normally B9600 default... */
- dummy_driver.init_termios.c_cflag =
- B115200 | CS8 | CREAD | HUPCL | CLOCAL;
- dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
- dummy_driver.init_termios.c_ispeed = 115200;
- dummy_driver.init_termios.c_ospeed = 115200;
-
- dummy_driver.ops = &dummy_ops;
- if (tty_register_driver(&dummy_driver))
- panic("Couldn't register dummy serial driver\n");
-}
-
-static struct tty_driver*
-etrax_console_device(struct console* co, int *index)
-{
- if (port)
- *index = port->index;
- else
- *index = 0;
-#ifdef CONFIG_ETRAX_SERIAL
- return port ? serial_driver : &dummy_driver;
-#else
- return &dummy_driver;
-#endif
-}
-
-static struct console ser_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : -1,
- cflag : 0,
- next : NULL
-};
-static struct console ser0_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 0,
- cflag : 0,
- next : NULL
-};
-
-static struct console ser1_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 1,
- cflag : 0,
- next : NULL
-};
-static struct console ser2_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 2,
- cflag : 0,
- next : NULL
-};
-static struct console ser3_console = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : etrax_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 3,
- cflag : 0,
- next : NULL
-};
-/*
- * Register console (for printk's etc)
- */
-
-int __init
-init_etrax_debug(void)
-{
- static int first = 1;
-
- if (!first) {
- unregister_console(&ser_console);
- register_console(&ser0_console);
- register_console(&ser1_console);
- register_console(&ser2_console);
- register_console(&ser3_console);
- init_dummy_console();
- return 0;
- }
-
- first = 0;
- register_console(&ser_console);
- start_port(port);
-#ifdef CONFIG_ETRAX_KGDB
- start_port(kgdb_port);
-#endif
- return 0;
-}
-__initcall(init_etrax_debug);
diff --git a/arch/cris/arch-v10/kernel/dma.c b/arch/cris/arch-v10/kernel/dma.c
deleted file mode 100644
index c68e978def05..000000000000
--- a/arch/cris/arch-v10/kernel/dma.c
+++ /dev/null
@@ -1,288 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Wrapper for DMA channel allocator that updates DMA client muxing.
- * Copyright 2004-2007, Axis Communications AB
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-
-#include <asm/dma.h>
-#include <arch/svinto.h>
-#include <arch/system.h>
-
-/* Macro to access ETRAX 100 registers */
-#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_STATE_(reg##_, field##_, _##val)
-
-
-static char used_dma_channels[MAX_DMA_CHANNELS];
-static const char * used_dma_channels_users[MAX_DMA_CHANNELS];
-
-int cris_request_dma(unsigned int dmanr, const char * device_id,
- unsigned options, enum dma_owner owner)
-{
- unsigned long flags;
- unsigned long int gens;
- int fail = -EINVAL;
-
- if (dmanr >= MAX_DMA_CHANNELS) {
- printk(KERN_CRIT "cris_request_dma: invalid DMA channel %u\n", dmanr);
- return -EINVAL;
- }
-
- local_irq_save(flags);
- if (used_dma_channels[dmanr]) {
- local_irq_restore(flags);
- if (options & DMA_VERBOSE_ON_ERROR) {
- printk(KERN_CRIT "Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]);
- }
- if (options & DMA_PANIC_ON_ERROR) {
- panic("request_dma error!");
- }
- return -EBUSY;
- }
-
- gens = genconfig_shadow;
-
- switch(owner)
- {
- case dma_eth:
- if ((dmanr != NETWORK_TX_DMA_NBR) &&
- (dmanr != NETWORK_RX_DMA_NBR)) {
- printk(KERN_CRIT "Invalid DMA channel for eth\n");
- goto bail;
- }
- break;
- case dma_ser0:
- if (dmanr == SER0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma6, serial0);
- } else if (dmanr == SER0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma7, serial0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser0\n");
- goto bail;
- }
- break;
- case dma_ser1:
- if (dmanr == SER1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma8, serial1);
- } else if (dmanr == SER1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma9, serial1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser1\n");
- goto bail;
- }
- break;
- case dma_ser2:
- if (dmanr == SER2_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, serial2);
- } else if (dmanr == SER2_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, serial2);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser2\n");
- goto bail;
- }
- break;
- case dma_ser3:
- if (dmanr == SER3_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, serial3);
- } else if (dmanr == SER3_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, serial3);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ser3\n");
- goto bail;
- }
- break;
- case dma_ata:
- if (dmanr == ATA_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, ata);
- } else if (dmanr == ATA_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, ata);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ata\n");
- goto bail;
- }
- break;
- case dma_ext0:
- if (dmanr == EXTDMA0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, extdma0);
- } else if (dmanr == EXTDMA0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, extdma0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ext0\n");
- goto bail;
- }
- break;
- case dma_ext1:
- if (dmanr == EXTDMA1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma6, extdma1);
- } else if (dmanr == EXTDMA1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma7, extdma1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for ext1\n");
- goto bail;
- }
- break;
- case dma_int6:
- if (dmanr == MEM2MEM_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma7, intdma6);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for int6\n");
- goto bail;
- }
- break;
- case dma_int7:
- if (dmanr == MEM2MEM_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma6, intdma7);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for int7\n");
- goto bail;
- }
- break;
- case dma_usb:
- if (dmanr == USB_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma8, usb);
- } else if (dmanr == USB_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma9, usb);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for usb\n");
- goto bail;
- }
- break;
- case dma_scsi0:
- if (dmanr == SCSI0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, scsi0);
- } else if (dmanr == SCSI0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, scsi0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for scsi0\n");
- goto bail;
- }
- break;
- case dma_scsi1:
- if (dmanr == SCSI1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, scsi1);
- } else if (dmanr == SCSI1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, scsi1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for scsi1\n");
- goto bail;
- }
- break;
- case dma_par0:
- if (dmanr == PAR0_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma2, par0);
- } else if (dmanr == PAR0_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma3, par0);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for par0\n");
- goto bail;
- }
- break;
- case dma_par1:
- if (dmanr == PAR1_TX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma4, par1);
- } else if (dmanr == PAR1_RX_DMA_NBR) {
- SETS(gens, R_GEN_CONFIG, dma5, par1);
- } else {
- printk(KERN_CRIT "Invalid DMA channel for par1\n");
- goto bail;
- }
- break;
- default:
- printk(KERN_CRIT "Invalid DMA owner.\n");
- goto bail;
- }
-
- used_dma_channels[dmanr] = 1;
- used_dma_channels_users[dmanr] = device_id;
-
- {
- volatile int i;
- genconfig_shadow = gens;
- *R_GEN_CONFIG = genconfig_shadow;
- /* Wait 12 cycles before doing any DMA command */
- for(i = 6; i > 0; i--)
- nop();
- }
- fail = 0;
- bail:
- local_irq_restore(flags);
- return fail;
-}
-
-void cris_free_dma(unsigned int dmanr, const char * device_id)
-{
- unsigned long flags;
- if (dmanr >= MAX_DMA_CHANNELS) {
- printk(KERN_CRIT "cris_free_dma: invalid DMA channel %u\n", dmanr);
- return;
- }
-
- local_irq_save(flags);
- if (!used_dma_channels[dmanr]) {
- printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated\n", dmanr);
- } else if (device_id != used_dma_channels_users[dmanr]) {
- printk(KERN_CRIT "cris_free_dma: DMA channel %u not allocated by device\n", dmanr);
- } else {
- switch(dmanr)
- {
- case 0:
- *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH0_CMD, cmd, *R_DMA_CH0_CMD) ==
- IO_STATE_VALUE(R_DMA_CH0_CMD, cmd, reset));
- break;
- case 1:
- *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH1_CMD, cmd, *R_DMA_CH1_CMD) ==
- IO_STATE_VALUE(R_DMA_CH1_CMD, cmd, reset));
- break;
- case 2:
- *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH2_CMD, cmd, *R_DMA_CH2_CMD) ==
- IO_STATE_VALUE(R_DMA_CH2_CMD, cmd, reset));
- break;
- case 3:
- *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH3_CMD, cmd, *R_DMA_CH3_CMD) ==
- IO_STATE_VALUE(R_DMA_CH3_CMD, cmd, reset));
- break;
- case 4:
- *R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH4_CMD, cmd, *R_DMA_CH4_CMD) ==
- IO_STATE_VALUE(R_DMA_CH4_CMD, cmd, reset));
- break;
- case 5:
- *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH5_CMD, cmd, *R_DMA_CH5_CMD) ==
- IO_STATE_VALUE(R_DMA_CH5_CMD, cmd, reset));
- break;
- case 6:
- *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *R_DMA_CH6_CMD) ==
- IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
- break;
- case 7:
- *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH7_CMD, cmd, *R_DMA_CH7_CMD) ==
- IO_STATE_VALUE(R_DMA_CH7_CMD, cmd, reset));
- break;
- case 8:
- *R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH8_CMD, cmd, *R_DMA_CH8_CMD) ==
- IO_STATE_VALUE(R_DMA_CH8_CMD, cmd, reset));
- break;
- case 9:
- *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset);
- while (IO_EXTRACT(R_DMA_CH9_CMD, cmd, *R_DMA_CH9_CMD) ==
- IO_STATE_VALUE(R_DMA_CH9_CMD, cmd, reset));
- break;
- }
- used_dma_channels[dmanr] = 0;
- }
- local_irq_restore(flags);
-}
-
-EXPORT_SYMBOL(cris_request_dma);
-EXPORT_SYMBOL(cris_free_dma);
diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S
deleted file mode 100644
index 1f066eebbd2b..000000000000
--- a/arch/cris/arch-v10/kernel/entry.S
+++ /dev/null
@@ -1,978 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/cris/entry.S
- *
- * Copyright (C) 2000, 2001, 2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- */
-
-/*
- * entry.S contains the system-call and fault low-level handling routines.
- *
- * NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- *
- * Stack layout in 'ret_from_system_call':
- * ptrace needs to have all regs on the stack.
- * if the order here is changed, it needs to be
- * updated in fork.c:copy_process, signal.c:do_signal,
- * ptrace.c and ptrace.h
- *
- */
-
-#include <linux/linkage.h>
-#include <linux/sys.h>
-#include <asm/unistd.h>
-#include <arch/sv_addr_ag.h>
-#include <asm/errno.h>
-#include <asm/thread_info.h>
-#include <asm/asm-offsets.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
- ;; functions exported from this file
-
- .globl system_call
- .globl ret_from_intr
- .globl ret_from_fork
- .globl ret_from_kernel_thread
- .globl resume
- .globl multiple_interrupt
- .globl hwbreakpoint
- .globl IRQ1_interrupt
- .globl spurious_interrupt
- .globl hw_bp_trigs
- .globl mmu_bus_fault
- .globl do_sigtrap
- .globl gdb_handle_breakpoint
- .globl sys_call_table
-
- ;; below are various parts of system_call which are not in the fast-path
-
-#ifdef CONFIG_PREEMPT
- ; Check if preemptive kernel scheduling should be done
-_resume_kernel:
- di
- ; Load current task struct
- movs.w -8192, $r0 ; THREAD_SIZE = 8192
- and.d $sp, $r0
- move.d [$r0+TI_preempt_count], $r10 ; Preemption disabled?
- bne _Rexit
- nop
-_need_resched:
- move.d [$r0+TI_flags], $r10
- btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set
- bpl _Rexit
- nop
- ; Ok, lets's do some preemptive kernel scheduling
- jsr preempt_schedule_irq
- ; Load new task struct
- movs.w -8192, $r0 ; THREAD_SIZE = 8192
- and.d $sp, $r0
- ; One more time (with new task)
- ba _need_resched
- nop
-#else
-#define _resume_kernel _Rexit
-#endif
-
- ; Called at exit from fork. schedule_tail must be called to drop
- ; spinlock if CONFIG_PREEMPT
-ret_from_fork:
- jsr schedule_tail
- ba ret_from_sys_call
- nop
-
-ret_from_kernel_thread:
- jsr schedule_tail
- move.d $r2, $r10 ; argument is here
- jsr $r1 ; call the payload
- moveq 0, $r9 ; no syscall restarts, TYVM...
- ba ret_from_sys_call
-
-ret_from_intr:
- ;; check for resched if preemptive kernel or if we're going back to user-mode
- ;; this test matches the user_regs(regs) macro
- ;; we cannot simply test $dccr, because that does not necessarily
- ;; reflect what mode we'll return into.
-
- move.d [$sp + PT_dccr], $r0; regs->dccr
- btstq 8, $r0 ; U-flag
- bpl _resume_kernel
- ; Note that di below is in delay slot
-
-_resume_userspace:
- di ; so need_resched and sigpending don't change
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- move.d [$r0+TI_flags], $r10 ; current->work
- and.d _TIF_WORK_MASK, $r10 ; is there any work to be done on return
- bne _work_pending
- nop
- ba _Rexit
- nop
-
- ;; The system_call is called by a BREAK instruction, which works like
- ;; an interrupt call but it stores the return PC in BRP instead of IRP.
- ;; Since we dont really want to have two epilogues (one for system calls
- ;; and one for interrupts) we push the contents of BRP instead of IRP in the
- ;; system call prologue, to make it look like an ordinary interrupt on the
- ;; stackframe.
- ;;
- ;; Since we can't have system calls inside interrupts, it should not matter
- ;; that we don't stack IRP.
- ;;
- ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,r13,mof,srp
- ;;
- ;; This function looks on the _surface_ like spaghetti programming, but it's
- ;; really designed so that the fast-path does not force cache-loading of non-used
- ;; instructions. Only the non-common cases cause the outlined code to run..
-
-system_call:
- ;; stack-frame similar to the irq heads, which is reversed in ret_from_sys_call
- move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
- push $srp
- push $dccr
- push $mof
- subq 14*4, $sp ; make room for r0-r13
- movem $r13, [$sp] ; push r0-r13
- push $r10 ; push orig_r10
- clear.d [$sp=$sp-4] ; frametype == 0, normal stackframe
-
- movs.w -ENOSYS, $r0
- move.d $r0, [$sp+PT_r10] ; put the default return value in r10 in the frame
-
- ;; check if this process is syscall-traced
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- move.d [$r0+TI_flags], $r0
- btstq TIF_SYSCALL_TRACE, $r0
- bmi _syscall_trace_entry
- nop
-
-_syscall_traced:
-
- ;; check for sanity in the requested syscall number
-
- cmpu.w NR_syscalls, $r9
- bcc ret_from_sys_call
- lslq 2, $r9 ; multiply by 4, in the delay slot
-
- ;; as a bonus 7th parameter, we give the location on the stack
- ;; of the register structure itself. some syscalls need this.
-
- push $sp
-
- ;; the parameter carrying registers r10, r11, r12 and 13 are intact.
- ;; the fifth and sixth parameters (if any) was in mof and srp
- ;; respectively, and we need to put them on the stack.
-
- push $srp
- push $mof
-
- jsr [$r9+sys_call_table] ; actually do the system call
- addq 3*4, $sp ; pop the mof, srp and regs parameters
- move.d $r10, [$sp+PT_r10] ; save the return value
-
- moveq 1, $r9 ; "parameter" to ret_from_sys_call to show it was a sys call
-
- ;; fall through into ret_from_sys_call to return
-
-ret_from_sys_call:
- ;; r9 is a parameter - if >=1 we came from a syscall, if 0, from an irq
-
- ;; get the current task-struct pointer (see top for defs)
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- di ; make sure need_resched and sigpending don't change
- move.d [$r0+TI_flags],$r1
- and.d _TIF_ALLWORK_MASK, $r1
- bne _syscall_exit_work
- nop
-
-_Rexit:
- ;; this epilogue MUST match the prologues in multiple_interrupt, irq.h and ptregs.h
- pop $r10 ; frametype
- bne _RBFexit ; was not CRIS_FRAME_NORMAL, handle otherwise
- addq 4, $sp ; skip orig_r10, in delayslot
- movem [$sp+], $r13 ; registers r0-r13
- pop $mof ; multiply overflow register
- pop $dccr ; condition codes
- pop $srp ; subroutine return pointer
- ;; now we have a 4-word SBFS frame which we do not want to restore
- ;; using RBF since it was not stacked with SBFS. instead we would like to
- ;; just get the PC value to restart it with, and skip the rest of
- ;; the frame.
- ;; Also notice that it's important to use instructions here that
- ;; keep the interrupts disabled (since we've already popped DCCR)
- move [$sp=$sp+16], $p8; pop the SBFS frame from the sp
- jmpu [$sp-16] ; return through the irp field in the sbfs frame
-
-_RBFexit:
- movem [$sp+], $r13 ; registers r0-r13, in delay slot
- pop $mof ; multiply overflow register
- pop $dccr ; condition codes
- pop $srp ; subroutine return pointer
- rbf [$sp+] ; return by popping the CPU status
-
- ;; We get here after doing a syscall if extra work might need to be done
- ;; perform syscall exit tracing if needed
-
-_syscall_exit_work:
- ;; $r0 contains current at this point and irq's are disabled
-
- move.d [$r0+TI_flags], $r1
- btstq TIF_SYSCALL_TRACE, $r1
- bpl _work_pending
- nop
-
- ei
-
- move.d $r9, $r1 ; preserve r9
- jsr do_syscall_trace
- move.d $r1, $r9
-
- ba _resume_userspace
- nop
-
-_work_pending:
- move.d [$r0+TI_flags], $r1
- btstq TIF_NEED_RESCHED, $r1
- bpl _work_notifysig ; was neither trace nor sched, must be signal/notify
- nop
-
-_work_resched:
- move.d $r9, $r1 ; preserve r9
- jsr schedule
- move.d $r1, $r9
- di
-
- move.d [$r0+TI_flags], $r1
- and.d _TIF_WORK_MASK, $r1; ignore the syscall trace counter
- beq _Rexit
- nop
- btstq TIF_NEED_RESCHED, $r1
- bmi _work_resched ; current->work.need_resched
- nop
-
-_work_notifysig:
- ;; deal with pending signals and notify-resume requests
-
- move.d $r9, $r10 ; do_notify_resume syscall/irq param
- move.d $sp, $r11 ; the regs param
- move.d $r1, $r12 ; the thread_info_flags parameter
- jsr do_notify_resume
-
- ba _Rexit
- nop
-
- ;; We get here as a sidetrack when we've entered a syscall with the
- ;; trace-bit set. We need to call do_syscall_trace and then continue
- ;; with the call.
-
-_syscall_trace_entry:
- ;; PT_r10 in the frame contains -ENOSYS as required, at this point
-
- jsr do_syscall_trace
-
- ;; now re-enter the syscall code to do the syscall itself
- ;; we need to restore $r9 here to contain the wanted syscall, and
- ;; the other parameter-bearing registers
-
- move.d [$sp+PT_r9], $r9
- move.d [$sp+PT_orig_r10], $r10 ; PT_r10 is already filled with -ENOSYS.
- move.d [$sp+PT_r11], $r11
- move.d [$sp+PT_r12], $r12
- move.d [$sp+PT_r13], $r13
- move [$sp+PT_mof], $mof
- move [$sp+PT_srp], $srp
-
- ba _syscall_traced
- nop
-
- ;; resume performs the actual task-switching, by switching stack pointers
- ;; input arguments: r10 = prev, r11 = next, r12 = thread offset in task struct
- ;; returns old current in r10
- ;;
- ;; TODO: see the i386 version. The switch_to which calls resume in our version
- ;; could really be an inline asm of this.
-
-resume:
- push $srp ; we keep the old/new PC on the stack
- add.d $r12, $r10 ; r10 = current tasks tss
- move $dccr, [$r10+THREAD_dccr]; save irq enable state
- di
-
- move $usp, [$r10+ THREAD_usp] ; save user-mode stackpointer
-
- ;; See copy_thread for the reason why register R9 is saved.
- subq 10*4, $sp
- movem $r9, [$sp] ; save non-scratch registers and R9.
-
- move.d $sp, [$r10+THREAD_ksp] ; save the kernel stack pointer for the old task
- move.d $sp, $r10 ; return last running task in r10
- and.d -8192, $r10 ; get thread_info from stackpointer
- move.d [$r10+TI_task], $r10 ; get task
- add.d $r12, $r11 ; find the new tasks tss
- move.d [$r11+THREAD_ksp], $sp ; switch into the new stackframe by restoring kernel sp
-
- movem [$sp+], $r9 ; restore non-scratch registers and R9.
-
- move [$r11+THREAD_usp], $usp ; restore user-mode stackpointer
-
- move [$r11+THREAD_dccr], $dccr ; restore irq enable status
- jump [$sp+] ; restore PC
-
- ;; This is the MMU bus fault handler.
- ;; It needs to stack the CPU status and overall is different
- ;; from the other interrupt handlers.
-
-mmu_bus_fault:
- ;; For refills we try to do a quick page table lookup. If it is
- ;; a real fault we let the mm subsystem handle it.
-
- ;; the first longword in the sbfs frame was the interrupted PC
- ;; which fits nicely with the "IRP" slot in pt_regs normally used to
- ;; contain the return address. used by Oops to print kernel errors.
- sbfs [$sp=$sp-16] ; push the internal CPU status
- push $dccr
- di
- subq 2*4, $sp
- movem $r1, [$sp]
- move.d [R_MMU_CAUSE], $r1
- ;; ETRAX 100LX TR89 bugfix: if the second half of an unaligned
- ;; write causes a MMU-fault, it will not be restarted correctly.
- ;; This could happen if a write crosses a page-boundary and the
- ;; second page is not yet COW'ed or even loaded. The workaround
- ;; is to clear the unaligned bit in the CPU status record, so
- ;; that the CPU will rerun both the first and second halves of
- ;; the instruction. This will not have any sideeffects unless
- ;; the first half goes to any device or memory that can't be
- ;; written twice, and which is mapped through the MMU.
- ;;
- ;; We only need to do this for writes.
- btstq 8, $r1 ; Write access?
- bpl 1f
- nop
- move.d [$sp+16], $r0 ; Clear unaligned bit in csrinstr
- and.d ~(1<<5), $r0
- move.d $r0, [$sp+16]
-1: btstq 12, $r1 ; Refill?
- bpl 2f
- lsrq 24, $r1 ; Get PGD index (bit 24-31)
- move.d [current_pgd], $r0 ; PGD for the current process
- move.d [$r0+$r1.d], $r0 ; Get PMD
- beq 2f
- nop
- and.w PAGE_MASK, $r0 ; Remove PMD flags
- move.d [R_MMU_CAUSE], $r1
- lsrq PAGE_SHIFT, $r1
- and.d 0x7ff, $r1 ; Get PTE index into PGD (bit 13-23)
- move.d [$r0+$r1.d], $r1 ; Get PTE
- beq 2f
- nop
- ;; Store in TLB
- move.d $r1, [R_TLB_LO]
- ;; Return
- movem [$sp+], $r1
- pop $dccr
- rbf [$sp+] ; return by popping the CPU status
-
-2: ; PMD or PTE missing, let the mm subsystem fix it up.
- movem [$sp+], $r1
- pop $dccr
-
- ; Ok, not that easy, pass it on to the mm subsystem
- ; The MMU status record is now on the stack
- push $srp ; make a stackframe similar to pt_regs
- push $dccr
- push $mof
- di
- subq 14*4, $sp
- movem $r13, [$sp]
- push $r10 ; dummy orig_r10
- moveq 1, $r10
- push $r10 ; frametype == 1, BUSFAULT frame type
-
- move.d $sp, $r10 ; pt_regs argument to handle_mmu_bus_fault
-
- jsr handle_mmu_bus_fault ; in arch/cris/arch-v10/mm/fault.c
-
- ;; now we need to return through the normal path, we cannot just
- ;; do the RBFexit since we might have killed off the running
- ;; process due to a SEGV, scheduled due to a page blocking or
- ;; whatever.
-
- moveq 0, $r9 ; busfault is equivalent to an irq
-
- ba ret_from_intr
- nop
-
- ;; special handlers for breakpoint and NMI
-hwbreakpoint:
- push $dccr
- di
- push $r10
- push $r11
- move.d [hw_bp_trig_ptr],$r10
- move $brp,$r11
- move.d $r11,[$r10+]
- move.d $r10,[hw_bp_trig_ptr]
-1: pop $r11
- pop $r10
- pop $dccr
- retb
- nop
-
-IRQ1_interrupt:
- ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!!
- move $brp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
- push $srp
- push $dccr
- push $mof
- di
- subq 14*4, $sp
- movem $r13, [$sp]
- push $r10 ; push orig_r10
- clear.d [$sp=$sp-4] ; frametype == 0, normal frame
-
- ;; If there is a glitch on the NMI pin shorter than ~100ns
- ;; (i.e. non-active by the time we get here) then the nmi_pin bit
- ;; in R_IRQ_MASK0_RD will already be cleared. The watchdog_nmi bit
- ;; is cleared by us however (when feeding the watchdog), which is why
- ;; we use that bit to determine what brought us here.
-
- move.d [R_IRQ_MASK0_RD], $r1 ; External NMI or watchdog?
- and.d (1<<30), $r1
- bne wdog
- move.d $sp, $r10
- jsr handle_nmi
- setf m ; Enable NMI again
- ba _Rexit ; Return the standard way
- nop
-wdog:
-#if defined(CONFIG_ETRAX_WATCHDOG)
-;; Check if we're waiting for reset to happen, as signalled by
-;; hard_reset_now setting cause_of_death to a magic value. If so, just
-;; get stuck until reset happens.
- .comm cause_of_death, 4 ;; Don't declare this anywhere.
- move.d [cause_of_death], $r10
- cmp.d 0xbedead, $r10
-_killed_by_death:
- beq _killed_by_death
- nop
-
-;; We'll see this in ksymoops dumps.
-Watchdog_bite:
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- ;; We just restart the watchdog here to be sure we dont get
- ;; hit while printing the watchdogmsg below
- ;; This restart is compatible with the rest of the C-code, so
- ;; the C-code can keep restarting the watchdog after this point.
- ;; The non-NICE_DOGGY code below though, disables the possibility
- ;; to restart since it changes the watchdog key, to avoid any
- ;; buggy loops etc. keeping the watchdog alive after this.
- jsr reset_watchdog
-#else
-
-;; We need to extend the 3.3ms after the NMI at watchdog bite, so we have
-;; time for an oops-dump over a 115k2 serial wire. Another 100ms should do.
-
-;; Change the watchdog key to an arbitrary 3-bit value and restart the
-;; watchdog.
-#define WD_INIT 2
- moveq IO_FIELD (R_WATCHDOG, key, WD_INIT), $r10
- move.d R_WATCHDOG, $r11
-
- move.d $r10, [$r11]
- moveq IO_FIELD (R_WATCHDOG, key, \
- IO_EXTRACT (R_WATCHDOG, key, \
- IO_MASK (R_WATCHDOG, key)) \
- ^ WD_INIT) \
- | IO_STATE (R_WATCHDOG, enable, start), $r10
- move.d $r10, [$r11]
-
-#endif
-
-;; Note that we don't do "setf m" here (or after two necessary NOPs),
-;; since *not* doing that saves us from re-entrancy checks. We don't want
-;; to get here again due to possible subsequent NMIs; we want the watchdog
-;; to reset us.
-
- move.d _watchdogmsg,$r10
- jsr printk
-
- move.d $sp, $r10
- jsr watchdog_bite_hook
-
-;; This nop is here so we see the "Watchdog_bite" label in ksymoops dumps
-;; rather than "spurious_interrupt".
- nop
-;; At this point we drop down into spurious_interrupt, which will do a
-;; hard reset.
-
- .section .rodata,"a"
-_watchdogmsg:
- .ascii "Oops: bitten by watchdog\n\0"
- .previous
-
-#endif /* CONFIG_ETRAX_WATCHDOG */
-
-spurious_interrupt:
- di
- jump hard_reset_now
-
- ;; this handles the case when multiple interrupts arrive at the same time
- ;; we jump to the first set interrupt bit in a priority fashion
- ;; the hardware will call the unserved interrupts after the handler finishes
-
-multiple_interrupt:
- ;; this prologue MUST match the one in irq.h and the struct in ptregs.h!!!
- move $irp,[$sp=$sp-16]; instruction pointer and room for a fake SBFS frame
- push $srp
- push $dccr
- push $mof
- di
- subq 14*4, $sp
- movem $r13, [$sp]
- push $r10 ; push orig_r10
- clear.d [$sp=$sp-4] ; frametype == 0, normal frame
-
- move.d $sp, $r10
- jsr do_multiple_IRQ
-
- jump ret_from_intr
-
-do_sigtrap:
- ;;
- ;; SIGTRAP the process that executed the break instruction.
- ;; Make a frame that Rexit in entry.S expects.
- ;;
- move $brp, [$sp=$sp-16] ; Push BRP while faking a cpu status record.
- push $srp ; Push subroutine return pointer.
- push $dccr ; Push condition codes.
- push $mof ; Push multiply overflow reg.
- di ; Need to disable irq's at this point.
- subq 14*4, $sp ; Make room for r0-r13.
- movem $r13, [$sp] ; Push the r0-r13 registers.
- push $r10 ; Push orig_r10.
- clear.d [$sp=$sp-4] ; Frametype - this is a normal stackframe.
-
- movs.w -8192,$r9 ; THREAD_SIZE == 8192
- and.d $sp, $r9
- move.d [$r9+TI_task], $r10
- move.d [$r10+TASK_pid], $r10 ; current->pid as arg1.
- moveq 5, $r11 ; SIGTRAP as arg2.
- jsr sys_kill
- jump ret_from_intr ; Use the return routine for interrupts.
-
-gdb_handle_breakpoint:
- push $dccr
- push $r0
-#ifdef CONFIG_ETRAX_KGDB
- move $dccr, $r0 ; U-flag not affected by previous insns.
- btstq 8, $r0 ; Test the U-flag.
- bmi _ugdb_handle_breakpoint ; Go to user mode debugging.
- nop ; Empty delay slot (cannot pop r0 here).
- pop $r0 ; Restore r0.
- ba kgdb_handle_breakpoint ; Go to kernel debugging.
- pop $dccr ; Restore dccr in delay slot.
-#endif
-
-_ugdb_handle_breakpoint:
- move $brp, $r0 ; Use r0 temporarily for calculation.
- subq 2, $r0 ; Set to address of previous instruction.
- move $r0, $brp
- pop $r0 ; Restore r0.
- ba do_sigtrap ; SIGTRAP the offending process.
- pop $dccr ; Restore dccr in delay slot.
-
- .data
-
-hw_bp_trigs:
- .space 64*4
-hw_bp_trig_ptr:
- .dword hw_bp_trigs
-
- .section .rodata,"a"
-sys_call_table:
- .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_lchown16
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_stat
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_setuid16
- .long sys_getuid16
- .long sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_fstat
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_ni_syscall /* old gtty syscall holder */
- .long sys_access
- .long sys_nice
- .long sys_ni_syscall /* 35 old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_setgid16
- .long sys_getgid16
- .long sys_signal
- .long sys_geteuid16
- .long sys_getegid16 /* 50 */
- .long sys_acct
- .long sys_umount /* recycled never used phys( */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 */
- .long sys_ni_syscall /* old mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* old sys_olduname holder */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_sigaction
- .long sys_sgetmask
- .long sys_ssetmask
- .long sys_setreuid16 /* 70 */
- .long sys_setregid16
- .long sys_sigsuspend
- .long sys_sigpending
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_old_getrlimit
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_getgroups16 /* 80 */
- .long sys_setgroups16
- .long sys_select /* was old_select in Linux/E100 */
- .long sys_symlink
- .long sys_lstat
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_old_readdir
- .long sys_old_mmap /* 90 */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_fchown16 /* 95 */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* sys_ioperm in i386 */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* old sys_uname holder */
- .long sys_ni_syscall /* 110 */ /* sys_iopl in i386 */
- .long sys_vhangup
- .long sys_ni_syscall /* old "idle" system call */
- .long sys_ni_syscall /* vm86old in i386 */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_sigreturn
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* sys_modify_ldt */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* for afs_syscall */
- .long sys_setfsuid16
- .long sys_setfsgid16
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_setresuid16
- .long sys_getresuid16 /* 165 */
- .long sys_ni_syscall /* sys_vm86 */
- .long sys_ni_syscall /* Old sys_query_module */
- .long sys_poll
- .long sys_ni_syscall /* old nfsservctl */
- .long sys_setresgid16 /* 170 */
- .long sys_getresgid16
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_chown16
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* streams1 */
- .long sys_ni_syscall /* streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap2 /* mmap_pgoff */
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall /* sys_set_thread_area */
- .long sys_ni_syscall /* sys_get_thread_area */
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* sys_vserver */
- .long sys_ni_syscall /* sys_mbind */
- .long sys_ni_syscall /* 275 sys_get_mempolicy */
- .long sys_ni_syscall /* sys_set_mempolicy */
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_ni_syscall
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_ioprio_set
- .long sys_ioprio_get /* 290 */
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages
- .long sys_openat /* 295 */
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat
- .long sys_fstatat64 /* 300 */
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat
- .long sys_readlinkat /* 305 */
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll
- .long sys_unshare /* 310 */
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range
- .long sys_tee /* 315 */
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait
- .long sys_utimensat /* 320 */
- .long sys_signalfd
- .long sys_timerfd_create
- .long sys_eventfd
- .long sys_fallocate
- .long sys_timerfd_settime /* 325 */
- .long sys_timerfd_gettime
- .long sys_signalfd4
- .long sys_eventfd2
- .long sys_epoll_create1
- .long sys_dup3 /* 330 */
- .long sys_pipe2
- .long sys_inotify_init1
- .long sys_preadv
- .long sys_pwritev
- .long sys_setns /* 335 */
- .long sys_name_to_handle_at
- .long sys_open_by_handle_at
- .long sys_rt_tgsigqueueinfo
- .long sys_perf_event_open
- .long sys_recvmmsg /* 340 */
- .long sys_accept4
- .long sys_fanotify_init
- .long sys_fanotify_mark
- .long sys_prlimit64
- .long sys_clock_adjtime /* 345 */
- .long sys_syncfs
- .long sys_sendmmsg
- .long sys_process_vm_readv
- .long sys_process_vm_writev
- .long sys_kcmp /* 350 */
- .long sys_finit_module
- .long sys_sched_setattr
- .long sys_sched_getattr
- .long sys_renameat2
- .long sys_seccomp /* 355 */
- .long sys_getrandom
- .long sys_memfd_create
- .long sys_bpf
- .long sys_execveat
-
- /*
- * NOTE!! This doesn't have to be exact - we just have
- * to make sure we have _enough_ of the "sys_ni_syscall"
- * entries. Don't panic if you notice that this hasn't
- * been shrunk every time we add a new system call.
- */
-
- .rept NR_syscalls-(.-sys_call_table)/4
- .long sys_ni_syscall
- .endr
-
diff --git a/arch/cris/arch-v10/kernel/fasttimer.c b/arch/cris/arch-v10/kernel/fasttimer.c
deleted file mode 100644
index 94abbff557ff..000000000000
--- a/arch/cris/arch-v10/kernel/fasttimer.c
+++ /dev/null
@@ -1,835 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/fasttimer.c
- *
- * Fast timers for ETRAX100/ETRAX100LX
- *
- * Copyright (C) 2000-2007 Axis Communications AB, Lund, Sweden
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-
-#include <asm/segment.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/delay.h>
-
-#include <arch/svinto.h>
-#include <asm/fasttimer.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-
-#define DEBUG_LOG_INCLUDED
-#define FAST_TIMER_LOG
-/* #define FAST_TIMER_TEST */
-
-#define FAST_TIMER_SANITY_CHECKS
-
-#ifdef FAST_TIMER_SANITY_CHECKS
-static int sanity_failed;
-#endif
-
-#define D1(x)
-#define D2(x)
-#define DP(x)
-
-static unsigned int fast_timer_running;
-static unsigned int fast_timers_added;
-static unsigned int fast_timers_started;
-static unsigned int fast_timers_expired;
-static unsigned int fast_timers_deleted;
-static unsigned int fast_timer_is_init;
-static unsigned int fast_timer_ints;
-
-struct fast_timer *fast_timer_list = NULL;
-
-#ifdef DEBUG_LOG_INCLUDED
-#define DEBUG_LOG_MAX 128
-static const char * debug_log_string[DEBUG_LOG_MAX];
-static unsigned long debug_log_value[DEBUG_LOG_MAX];
-static unsigned int debug_log_cnt;
-static unsigned int debug_log_cnt_wrapped;
-
-#define DEBUG_LOG(string, value) \
-{ \
- unsigned long log_flags; \
- local_irq_save(log_flags); \
- debug_log_string[debug_log_cnt] = (string); \
- debug_log_value[debug_log_cnt] = (unsigned long)(value); \
- if (++debug_log_cnt >= DEBUG_LOG_MAX) \
- { \
- debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \
- debug_log_cnt_wrapped = 1; \
- } \
- local_irq_restore(log_flags); \
-}
-#else
-#define DEBUG_LOG(string, value)
-#endif
-
-
-/* The frequencies for index = clkselx number in R_TIMER_CTRL */
-#define NUM_TIMER_FREQ 15
-#define MAX_USABLE_TIMER_FREQ 7
-#define MAX_DELAY_US 853333L
-const unsigned long timer_freq_100[NUM_TIMER_FREQ] =
-{
- 3, /* 0 3333 - 853333 us */
- 6, /* 1 1666 - 426666 us */
- 12, /* 2 833 - 213333 us */
- 24, /* 3 416 - 106666 us */
- 48, /* 4 208 - 53333 us */
- 96, /* 5 104 - 26666 us */
- 192, /* 6 52 - 13333 us */
- 384, /* 7 26 - 6666 us */
- 576,
- 1152,
- 2304,
- 4608,
- 9216,
- 18432,
- 62500,
- /* 15 = cascade */
-};
-#define NUM_TIMER_STATS 16
-#ifdef FAST_TIMER_LOG
-struct fast_timer timer_added_log[NUM_TIMER_STATS];
-struct fast_timer timer_started_log[NUM_TIMER_STATS];
-struct fast_timer timer_expired_log[NUM_TIMER_STATS];
-#endif
-
-int timer_div_settings[NUM_TIMER_STATS];
-int timer_freq_settings[NUM_TIMER_STATS];
-int timer_delay_settings[NUM_TIMER_STATS];
-
-/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */
-inline void do_gettimeofday_fast(struct fasttime_t *tv)
-{
- tv->tv_jiff = jiffies;
- tv->tv_usec = GET_JIFFIES_USEC();
-}
-
-inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1)
-{
- /* Compare jiffies. Takes care of wrapping */
- if (time_before(t0->tv_jiff, t1->tv_jiff))
- return -1;
- else if (time_after(t0->tv_jiff, t1->tv_jiff))
- return 1;
-
- /* Compare us */
- if (t0->tv_usec < t1->tv_usec)
- return -1;
- else if (t0->tv_usec > t1->tv_usec)
- return 1;
- return 0;
-}
-
-inline void start_timer1(unsigned long delay_us)
-{
- int freq_index = 0; /* This is the lowest resolution */
- unsigned long upper_limit = MAX_DELAY_US;
-
- unsigned long div;
- /* Start/Restart the timer to the new shorter value */
- /* t = 1/freq = 1/19200 = 53us
- * T=div*t, div = T/t = delay_us*freq/1000000
- */
-#if 1 /* Adaptive timer settings */
- while (delay_us < upper_limit && freq_index < MAX_USABLE_TIMER_FREQ)
- {
- freq_index++;
- upper_limit >>= 1; /* Divide by 2 using shift */
- }
- if (freq_index > 0)
- {
- freq_index--;
- }
-#else
- freq_index = 6;
-#endif
- div = delay_us * timer_freq_100[freq_index]/10000;
- if (div < 2)
- {
- /* Maybe increase timer freq? */
- div = 2;
- }
- if (div > 255)
- {
- div = 0; /* This means 256, the max the timer takes */
- /* If a longer timeout than the timer can handle is used,
- * then we must restart it when it goes off.
- */
- }
-
- timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = div;
- timer_freq_settings[fast_timers_started % NUM_TIMER_STATS] = freq_index;
- timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
-
- D1(printk(KERN_DEBUG "start_timer1 : %d us freq: %i div: %i\n",
- delay_us, freq_index, div));
- /* Clear timer1 irq */
- *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr);
-
- /* Set timer values */
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- (r_timer_ctrl_shadow &
- ~IO_MASK(R_TIMER_CTRL, timerdiv1) &
- ~IO_MASK(R_TIMER_CTRL, tm1) &
- ~IO_MASK(R_TIMER_CTRL, clksel1)) |
- IO_FIELD(R_TIMER_CTRL, timerdiv1, div) |
- IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
- IO_FIELD(R_TIMER_CTRL, clksel1, freq_index ); /* 6=c19k2Hz */
-
- /* Ack interrupt */
- *R_TIMER_CTRL = r_timer_ctrl_shadow |
- IO_STATE(R_TIMER_CTRL, i1, clr);
-
- /* Start timer */
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) |
- IO_STATE(R_TIMER_CTRL, tm1, run);
-
- /* Enable timer1 irq */
- *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer1, set);
- fast_timers_started++;
- fast_timer_running = 1;
-}
-
-/* In version 1.4 this function takes 27 - 50 us */
-void start_one_shot_timer(struct fast_timer *t,
- fast_timer_function_type *function,
- unsigned long data,
- unsigned long delay_us,
- const char *name)
-{
- unsigned long flags;
- struct fast_timer *tmp;
-
- D1(printk("sft %s %d us\n", name, delay_us));
-
- local_irq_save(flags);
-
- do_gettimeofday_fast(&t->tv_set);
- tmp = fast_timer_list;
-
-#ifdef FAST_TIMER_SANITY_CHECKS
- /* Check so this is not in the list already... */
- while (tmp != NULL) {
- if (tmp == t) {
- printk(KERN_WARNING "timer name: %s data: "
- "0x%08lX already in list!\n", name, data);
- sanity_failed++;
- goto done;
- } else
- tmp = tmp->next;
- }
- tmp = fast_timer_list;
-#endif
-
- t->delay_us = delay_us;
- t->function = function;
- t->data = data;
- t->name = name;
-
- t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000;
- t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ;
- if (t->tv_expires.tv_usec > 1000000)
- {
- t->tv_expires.tv_usec -= 1000000;
- t->tv_expires.tv_jiff += HZ;
- }
-#ifdef FAST_TIMER_LOG
- timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_added++;
-
- /* Check if this should timeout before anything else */
- if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0)
- {
- /* Put first in list and modify the timer value */
- t->prev = NULL;
- t->next = fast_timer_list;
- if (fast_timer_list)
- {
- fast_timer_list->prev = t;
- }
- fast_timer_list = t;
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer1(delay_us);
- } else {
- /* Put in correct place in list */
- while (tmp->next && fasttime_cmp(&t->tv_expires,
- &tmp->next->tv_expires) > 0)
- {
- tmp = tmp->next;
- }
- /* Insert t after tmp */
- t->prev = tmp;
- t->next = tmp->next;
- if (tmp->next)
- {
- tmp->next->prev = t;
- }
- tmp->next = t;
- }
-
- D2(printk("start_one_shot_timer: %d us done\n", delay_us));
-
-done:
- local_irq_restore(flags);
-} /* start_one_shot_timer */
-
-static inline int fast_timer_pending (const struct fast_timer * t)
-{
- return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list);
-}
-
-static inline int detach_fast_timer (struct fast_timer *t)
-{
- struct fast_timer *next, *prev;
- if (!fast_timer_pending(t))
- return 0;
- next = t->next;
- prev = t->prev;
- if (next)
- next->prev = prev;
- if (prev)
- prev->next = next;
- else
- fast_timer_list = next;
- fast_timers_deleted++;
- return 1;
-}
-
-int del_fast_timer(struct fast_timer * t)
-{
- unsigned long flags;
- int ret;
-
- local_irq_save(flags);
- ret = detach_fast_timer(t);
- t->next = t->prev = NULL;
- local_irq_restore(flags);
- return ret;
-} /* del_fast_timer */
-
-
-/* Interrupt routines or functions called in interrupt context */
-
-/* Timer 1 interrupt handler */
-
-static irqreturn_t
-timer1_handler(int irq, void *dev_id)
-{
- struct fast_timer *t;
- unsigned long flags;
-
- /* We keep interrupts disabled not only when we modify the
- * fast timer list, but any time we hold a reference to a
- * timer in the list, since del_fast_timer may be called
- * from (another) interrupt context. Thus, the only time
- * when interrupts are enabled is when calling the timer
- * callback function.
- */
- local_irq_save(flags);
-
- /* Clear timer1 irq */
- *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr);
-
- /* First stop timer, then ack interrupt */
- /* Stop timer */
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- (r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) |
- IO_STATE(R_TIMER_CTRL, tm1, stop_ld);
-
- /* Ack interrupt */
- *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i1, clr);
-
- fast_timer_running = 0;
- fast_timer_ints++;
-
- t = fast_timer_list;
- while (t)
- {
- struct fasttime_t tv;
- fast_timer_function_type *f;
- unsigned long d;
-
- /* Has it really expired? */
- do_gettimeofday_fast(&tv);
- D1(printk(KERN_DEBUG "t: %is %06ius\n",
- tv.tv_jiff, tv.tv_usec));
-
- if (fasttime_cmp(&t->tv_expires, &tv) <= 0)
- {
- /* Yes it has expired */
-#ifdef FAST_TIMER_LOG
- timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_expired++;
-
- /* Remove this timer before call, since it may reuse the timer */
- if (t->prev)
- {
- t->prev->next = t->next;
- }
- else
- {
- fast_timer_list = t->next;
- }
- if (t->next)
- {
- t->next->prev = t->prev;
- }
- t->prev = NULL;
- t->next = NULL;
-
- /* Save function callback data before enabling
- * interrupts, since the timer may be removed and
- * we don't know how it was allocated
- * (e.g. ->function and ->data may become overwritten
- * after deletion if the timer was stack-allocated).
- */
- f = t->function;
- d = t->data;
-
- if (f != NULL) {
- /* Run callback with interrupts enabled. */
- local_irq_restore(flags);
- f(d);
- local_irq_save(flags);
- } else
- DEBUG_LOG("!timer1 %i function==NULL!\n", fast_timer_ints);
- }
- else
- {
- /* Timer is to early, let's set it again using the normal routines */
- D1(printk(".\n"));
- }
-
- if ((t = fast_timer_list) != NULL)
- {
- /* Start next timer.. */
- long us = 0;
- struct fasttime_t tv;
-
- do_gettimeofday_fast(&tv);
-
- /* time_after_eq takes care of wrapping */
- if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff))
- us = ((t->tv_expires.tv_jiff - tv.tv_jiff) *
- 1000000 / HZ + t->tv_expires.tv_usec -
- tv.tv_usec);
-
- if (us > 0)
- {
- if (!fast_timer_running)
- {
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer1(us);
- }
- break;
- }
- else
- {
- /* Timer already expired, let's handle it better late than never.
- * The normal loop handles it
- */
- D1(printk("e! %d\n", us));
- }
- }
- }
-
- local_irq_restore(flags);
-
- if (!t)
- {
- D1(printk("t1 stop!\n"));
- }
-
- return IRQ_HANDLED;
-}
-
-static void wake_up_func(unsigned long data)
-{
- wait_queue_head_t *sleep_wait_p = (wait_queue_head_t *)data;
- wake_up(sleep_wait_p);
-}
-
-
-/* Useful API */
-
-void schedule_usleep(unsigned long us)
-{
- struct fast_timer t;
- wait_queue_head_t sleep_wait;
- init_waitqueue_head(&sleep_wait);
-
- D1(printk("schedule_usleep(%d)\n", us));
- start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us,
- "usleep");
- /* Uninterruptible sleep on the fast timer. (The condition is somewhat
- * redundant since the timer is what wakes us up.) */
- wait_event(sleep_wait, !fast_timer_pending(&t));
-
- D1(printk("done schedule_usleep(%d)\n", us));
-}
-
-#ifdef CONFIG_PROC_FS
-/* This value is very much based on testing */
-#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300)
-
-static int proc_fasttimer_show(struct seq_file *m, void *v)
-{
- unsigned long flags;
- int i = 0;
- int num_to_show;
- struct fasttime_t tv;
- struct fast_timer *t, *nextt;
-
- do_gettimeofday_fast(&tv);
-
- seq_printf(m, "Fast timers added: %i\n", fast_timers_added);
- seq_printf(m, "Fast timers started: %i\n", fast_timers_started);
- seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints);
- seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired);
- seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted);
- seq_printf(m, "Fast timer running: %s\n",
- fast_timer_running ? "yes" : "no");
- seq_printf(m, "Current time: %lu.%06lu\n",
- (unsigned long)tv.tv_jiff,
- (unsigned long)tv.tv_usec);
-#ifdef FAST_TIMER_SANITY_CHECKS
- seq_printf(m, "Sanity failed: %i\n", sanity_failed);
-#endif
- seq_putc(m, '\n');
-
-#ifdef DEBUG_LOG_INCLUDED
- {
- int end_i = debug_log_cnt;
- i = 0;
-
- if (debug_log_cnt_wrapped)
- i = debug_log_cnt;
-
- while (i != end_i || debug_log_cnt_wrapped) {
- seq_printf(m, debug_log_string[i], debug_log_value[i]);
- if (seq_has_overflowed(m))
- return 0;
- i = (i+1) % DEBUG_LOG_MAX;
- }
- }
- seq_putc(m, '\n');
-#endif
-
- num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers started: %i\n", fast_timers_started);
- for (i = 0; i < num_to_show; i++) {
- int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
-
-#if 1 //ndef FAST_TIMER_LOG
- seq_printf(m, "div: %i freq: %i delay: %i\n",
- timer_div_settings[cur],
- timer_freq_settings[cur],
- timer_delay_settings[cur]);
-#endif
-#ifdef FAST_TIMER_LOG
- t = &timer_started_log[cur];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
-#endif
- }
- seq_putc(m, '\n');
-
-#ifdef FAST_TIMER_LOG
- num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers added: %i\n", fast_timers_added);
- for (i = 0; i < num_to_show; i++) {
- t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-
- num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers expired: %i\n", fast_timers_expired);
- for (i = 0; i < num_to_show; i++) {
- t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-#endif
-
- seq_puts(m, "Active timers:\n");
- local_irq_save(flags);
- t = fast_timer_list;
- while (t) {
- nextt = t->next;
- local_irq_restore(flags);
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- local_irq_save(flags);
- if (t->next != nextt)
- printk(KERN_WARNING "timer removed!\n");
- t = nextt;
- }
- local_irq_restore(flags);
-
- return 0;
-}
-
-static int proc_fasttimer_open(struct inode *inode, struct file *file)
-{
- return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE);
-}
-
-static const struct file_operations proc_fasttimer_fops = {
- .open = proc_fasttimer_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-#endif /* PROC_FS */
-
-#ifdef FAST_TIMER_TEST
-static volatile unsigned long i = 0;
-static volatile int num_test_timeout = 0;
-static struct fast_timer tr[10];
-static int exp_num[10];
-
-static struct fasttime_t tv_exp[100];
-
-static void test_timeout(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
-
- num_test_timeout++;
-}
-
-static void test_timeout1(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
- if (data < 7)
- {
- start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1");
- i++;
- }
- num_test_timeout++;
-}
-
-DP(
-static char buf0[2000];
-static char buf1[2000];
-static char buf2[2000];
-static char buf3[2000];
-static char buf4[2000];
-);
-
-static char buf5[6000];
-static int j_u[1000];
-
-static void fast_timer_test(void)
-{
- int prev_num;
- int j;
-
- struct fasttime_t tv, tv0, tv1, tv2;
-
- printk("fast_timer_test() start\n");
- do_gettimeofday_fast(&tv);
-
- for (j = 0; j < 1000; j++)
- {
- j_u[j] = GET_JIFFIES_USEC();
- }
- for (j = 0; j < 100; j++)
- {
- do_gettimeofday_fast(&tv_exp[j]);
- }
- printk(KERN_DEBUG "fast_timer_test() %is %06i\n",
- tv.tv_jiff, tv.tv_usec);
-
- for (j = 0; j < 1000; j++)
- {
- printk("%i %i %i %i %i\n",j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]);
- j += 4;
- }
- for (j = 0; j < 100; j++)
- {
- printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n",
- tv_exp[j].tv_jiff, tv_exp[j].tv_usec,
- tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec,
- tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec,
- tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec,
- tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec);
- j += 4;
- }
- do_gettimeofday_fast(&tv0);
- start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0");
- DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1");
- DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2");
- DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3");
- DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx");
- DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0));
- i++;
- do_gettimeofday_fast(&tv1);
-
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
-
- prev_num = num_test_timeout;
- while (num_test_timeout < i)
- {
- if (num_test_timeout != prev_num)
- {
- prev_num = num_test_timeout;
- }
- }
- do_gettimeofday_fast(&tv2);
- printk(KERN_DEBUG "Timers started %is %06i\n",
- tv0.tv_jiff, tv0.tv_usec);
- printk(KERN_DEBUG "Timers started at %is %06i\n",
- tv1.tv_jiff, tv1.tv_usec);
- printk(KERN_DEBUG "Timers done %is %06i\n",
- tv2.tv_jiff, tv2.tv_usec);
- DP(printk("buf0:\n");
- printk(buf0);
- printk("buf1:\n");
- printk(buf1);
- printk("buf2:\n");
- printk(buf2);
- printk("buf3:\n");
- printk(buf3);
- printk("buf4:\n");
- printk(buf4);
- );
- printk("buf5:\n");
- printk(buf5);
-
- printk("timers set:\n");
- for(j = 0; j<i; j++)
- {
- struct fast_timer *t = &tr[j];
- printk("%-10s set: %6is %06ius exp: %6is %06ius "
- "data: 0x%08X func: 0x%08X\n",
- t->name,
- t->tv_set.tv_jiff,
- t->tv_set.tv_usec,
- t->tv_expires.tv_jiff,
- t->tv_expires.tv_usec,
- t->data,
- t->function
- );
-
- printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n",
- t->delay_us,
- tv_exp[j].tv_jiff,
- tv_exp[j].tv_usec,
- exp_num[j],
- (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) *
- 1000000 + tv_exp[j].tv_usec -
- t->tv_expires.tv_usec);
- }
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
- printk("buf5 after all done:\n");
- printk(buf5);
- printk("fast_timer_test() done\n");
-}
-#endif
-
-
-int fast_timer_init(void)
-{
- /* For some reason, request_irq() hangs when called froom time_init() */
- if (!fast_timer_is_init)
- {
-#if 0 && defined(FAST_TIMER_TEST)
- int i;
-#endif
-
- printk(KERN_INFO "fast_timer_init()\n");
-
-#if 0 && defined(FAST_TIMER_TEST)
- for (i = 0; i <= TIMER0_DIV; i++)
- {
- /* We must be careful not to get overflow... */
- printk("%3i %6u\n", i, timer0_value_us[i]);
- }
-#endif
-#ifdef CONFIG_PROC_FS
- proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops);
-#endif /* PROC_FS */
- if(request_irq(TIMER1_IRQ_NBR, timer1_handler, 0,
- "fast timer int", NULL))
- {
- printk("err: timer1 irq\n");
- }
- fast_timer_is_init = 1;
-#ifdef FAST_TIMER_TEST
- printk("do test\n");
- fast_timer_test();
-#endif
- }
- return 0;
-}
-__initcall(fast_timer_init);
diff --git a/arch/cris/arch-v10/kernel/head.S b/arch/cris/arch-v10/kernel/head.S
deleted file mode 100644
index b260a8833903..000000000000
--- a/arch/cris/arch-v10/kernel/head.S
+++ /dev/null
@@ -1,620 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Head of the kernel - alter with care
- *
- * Copyright (C) 2000, 2001, 2010 Axis Communications AB
- *
- */
-
-#include <linux/init.h>
-
-#define ASSEMBLER_MACROS_ONLY
-/* The IO_* macros use the ## token concatenation operator, so
- -traditional must not be used when assembling this file. */
-#include <arch/sv_addr_ag.h>
-
-#define CRAMFS_MAGIC 0x28cd3d45
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-
-#define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\
- IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk)
-
- ;; exported symbols
-
- .globl etrax_irv
- .globl romfs_start
- .globl romfs_length
- .globl romfs_in_flash
- .globl swapper_pg_dir
-
- __HEAD
-
- ;; This is the entry point of the kernel. We are in supervisor mode.
- ;; 0x00000000 if Flash, 0x40004000 if DRAM
- ;; since etrax actually starts at address 2 when booting from flash, we
- ;; put a nop (2 bytes) here first so we dont accidentally skip the di
- ;;
- ;; NOTICE! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below until read.
-
- nop
- di
-
- ;; First setup the kseg_c mapping from where the kernel is linked
- ;; to 0x40000000 (where the actual DRAM resides) otherwise
- ;; we cannot do very much! See arch/cris/README.mm
- ;;
- ;; Notice that since we're potentially running at 0x00 or 0x40 right now,
- ;; we will get a fault as soon as we enable the MMU if we dont
- ;; temporarily map those segments linearily.
- ;;
- ;; Due to a bug in Etrax-100 LX version 1 we need to map the memory
- ;; slightly different. The bug is that you can't remap bit 31 of
- ;; an address. Though we can check the version register for
- ;; whether the bug is present, some constants would then have to
- ;; be variables, so we don't. The drawback is that you can "only" map
- ;; 1G per process with CONFIG_CRIS_LOW_MAP.
-
-#ifdef CONFIG_CRIS_LOW_MAP
- ; kseg mappings, temporary map of 0xc0->0x40
- move.d IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \
- | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb) \
- | IO_FIELD (R_MMU_KBASE_HI, base_9, 9) \
- | IO_FIELD (R_MMU_KBASE_HI, base_8, 8), $r0
- move.d $r0, [R_MMU_KBASE_HI]
-
- ; temporary map of 0x40->0x40 and 0x60->0x40
- move.d IO_FIELD (R_MMU_KBASE_LO, base_6, 4) \
- | IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0
- move.d $r0, [R_MMU_KBASE_LO]
-
- ; mmu enable, segs e,c,b,a,6,5,4,0 segment mapped
- move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \
- | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, we_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, seg_f, page) \
- | IO_STATE (R_MMU_CONFIG, seg_e, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_d, page) \
- | IO_STATE (R_MMU_CONFIG, seg_c, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_b, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_a, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_9, page) \
- | IO_STATE (R_MMU_CONFIG, seg_8, page) \
- | IO_STATE (R_MMU_CONFIG, seg_7, page) \
- | IO_STATE (R_MMU_CONFIG, seg_6, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_5, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_4, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_3, page) \
- | IO_STATE (R_MMU_CONFIG, seg_2, page) \
- | IO_STATE (R_MMU_CONFIG, seg_1, page) \
- | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0
- move.d $r0, [R_MMU_CONFIG]
-#else
- ; kseg mappings
- move.d IO_FIELD (R_MMU_KBASE_HI, base_e, 8) \
- | IO_FIELD (R_MMU_KBASE_HI, base_c, 4) \
- | IO_FIELD (R_MMU_KBASE_HI, base_b, 0xb), $r0
- move.d $r0, [R_MMU_KBASE_HI]
-
- ; temporary map of 0x40->0x40 and 0x00->0x00
- move.d IO_FIELD (R_MMU_KBASE_LO, base_4, 4), $r0
- move.d $r0, [R_MMU_KBASE_LO]
-
- ; mmu enable, segs f,e,c,b,4,0 segment mapped
- move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \
- | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, we_excp, enable) \
- | IO_STATE (R_MMU_CONFIG, seg_f, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_e, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_d, page) \
- | IO_STATE (R_MMU_CONFIG, seg_c, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_b, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_a, page) \
- | IO_STATE (R_MMU_CONFIG, seg_9, page) \
- | IO_STATE (R_MMU_CONFIG, seg_8, page) \
- | IO_STATE (R_MMU_CONFIG, seg_7, page) \
- | IO_STATE (R_MMU_CONFIG, seg_6, page) \
- | IO_STATE (R_MMU_CONFIG, seg_5, page) \
- | IO_STATE (R_MMU_CONFIG, seg_4, seg) \
- | IO_STATE (R_MMU_CONFIG, seg_3, page) \
- | IO_STATE (R_MMU_CONFIG, seg_2, page) \
- | IO_STATE (R_MMU_CONFIG, seg_1, page) \
- | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0
- move.d $r0, [R_MMU_CONFIG]
-#endif
-
- ;; Now we need to sort out the segments and their locations in RAM or
- ;; Flash. The image in the Flash (or in DRAM) consists of 3 pieces:
- ;; 1) kernel text, 2) kernel data, 3) ROM filesystem image
- ;; But the linker has linked the kernel to expect this layout in
- ;; DRAM memory:
- ;; 1) kernel text, 2) kernel data, 3) kernel BSS
- ;; (the location of the ROM filesystem is determined by the krom driver)
- ;; If we boot this from Flash, we want to keep the ROM filesystem in
- ;; the flash, we want to copy the text and need to copy the data to DRAM.
- ;; But if we boot from DRAM, we need to move the ROMFS image
- ;; from its position after kernel data, to after kernel BSS, BEFORE the
- ;; kernel starts using the BSS area (since its "overlayed" with the ROMFS)
- ;;
- ;; In both cases, we start in un-cached mode, and need to jump into a
- ;; cached PC after we're done fiddling around with the segments.
- ;;
- ;; arch/etrax100/etrax100.ld sets some symbols that define the start
- ;; and end of each segment.
-
- ;; Check if we start from DRAM or FLASH by testing PC
-
- move.d $pc,$r0
- and.d 0x7fffffff,$r0 ; get rid of the non-cache bit
- cmp.d 0x10000,$r0 ; arbitrary... just something above this code
- blo _inflash0
- nop
-
- jump _inram ; enter cached ram
-
- ;; Jumpgate for branches.
-_inflash0:
- jump _inflash
-
- ;; Put this in a suitable section where we can reclaim storage
- ;; after init.
- __INIT
-_inflash:
-#ifdef CONFIG_ETRAX_ETHERNET
- ;; Start MII clock to make sure it is running when tranceiver is reset
- move.d START_ETHERNET_CLOCK, $r0
- move.d $r0, [R_NETWORK_GEN_CONFIG]
-#endif
-
- ;; Set up waitstates etc according to kernel configuration.
- move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
- move.d $r0, [R_WAITSTATES]
-
- move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
- move.d $r0, [R_BUS_CONFIG]
-
- ;; We need to initialze DRAM registers before we start using the DRAM
-
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq _dram_init_finished
- nop
-
-#include "../lib/dram_init.S"
-
-_dram_init_finished:
- ;; Copy text+data to DRAM
- ;; This is fragile - the calculation of r4 as the image size depends
- ;; on that the labels below actually are the first and last positions
- ;; in the linker-script.
- ;;
- ;; Then the locating of the cramfs image depends on the aforementioned
- ;; image being located in the flash at 0. This is most often not true,
- ;; thus the following does not work (normally there is a rescue-block
- ;; between the physical start of the flash and the flash-image start,
- ;; and when run with compression, the kernel is actually unpacked to
- ;; DRAM and we never get here in the first place :))
-
- moveq 0, $r0 ; source
- move.d text_start, $r1 ; destination
- move.d __vmlinux_end, $r2 ; end destination
- move.d $r2, $r4
- sub.d $r1, $r4 ; r4=__vmlinux_end in flash, used below
-1: move.w [$r0+], $r3
- move.w $r3, [$r1+]
- cmp.d $r2, $r1
- blo 1b
- nop
-
- ;; We keep the cramfs in the flash.
- ;; There might be none, but that does not matter because
- ;; we don't do anything than read some bytes here.
-
- moveq 0, $r0
- move.d $r0, [romfs_length] ; default if there is no cramfs
-
- move.d [$r4], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne 1f
- nop
- move.d [$r4 + 4], $r0 ; cramfs_super.size
- move.d $r0, [romfs_length]
-#ifdef CONFIG_CRIS_LOW_MAP
- add.d 0x50000000, $r4 ; add flash start in virtual memory (cached)
-#else
- add.d 0xf0000000, $r4 ; add flash start in virtual memory (cached)
-#endif
- move.d $r4, [romfs_start]
-1:
- moveq 1, $r0
- move.d $r0, [romfs_in_flash]
-
- jump _start_it ; enter code, cached this time
-
-_inram:
- ;; Move the ROM fs to after BSS end. This assumes that the cramfs
- ;; second longword contains the length of the cramfs
-
- moveq 0, $r0
- move.d $r0, [romfs_length] ; default if there is no cramfs
-
- ;; The kernel could have been unpacked to DRAM by the loader, but
- ;; the cramfs image could still be in the Flash directly after the
- ;; compressed kernel image. The loader passes the address of the
- ;; byte succeeding the last compressed byte in the flash in the
- ;; register r9 when starting the kernel. Check if r9 points to a
- ;; decent cramfs image!
- ;; (Notice that if this is not booted from the loader, r9 will be
- ;; garbage but we do sanity checks on it, the chance that it points
- ;; to a cramfs magic is small.. )
-
- cmp.d 0x0ffffff8, $r9
- bhs _no_romfs_in_flash ; r9 points outside the flash area
- nop
- move.d [$r9], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne _no_romfs_in_flash
- nop
- move.d [$r9+4], $r0 ; cramfs_super.length
- move.d $r0, [romfs_length]
-#ifdef CONFIG_CRIS_LOW_MAP
- add.d 0x50000000, $r9 ; add flash start in virtual memory (cached)
-#else
- add.d 0xf0000000, $r9 ; add flash start in virtual memory (cached)
-#endif
- move.d $r9, [romfs_start]
-
- moveq 1, $r0
- move.d $r0, [romfs_in_flash]
-
- jump _start_it ; enter code, cached this time
-
-_no_romfs_in_flash:
-
- ;; Check if there is a cramfs (magic value).
- ;; Notice that we check for cramfs magic value - which is
- ;; the "rom fs" we'll possibly use in 2.4 if not JFFS (which does
- ;; not need this mechanism anyway)
-
- move.d __init_end, $r0; the image will be after the end of init
- move.d [$r0], $r1 ; cramfs assumes same endian on host/target
- cmp.d CRAMFS_MAGIC, $r1; magic value in cramfs superblock
- bne 2f
- nop
-
- ;; Ok. What is its size ?
-
- move.d [$r0 + 4], $r2 ; cramfs_super.size (again, no need to swapwb)
-
- ;; We want to copy it to the end of the BSS
-
- move.d _end, $r1
-
- ;; Remember values so cramfs and setup can find this info
-
- move.d $r1, [romfs_start] ; new romfs location
- move.d $r2, [romfs_length]
-
- ;; We need to copy it backwards, since they can be overlapping
-
- add.d $r2, $r0
- add.d $r2, $r1
-
- ;; Go ahead. Make my loop.
-
- lsrq 1, $r2 ; size is in bytes, we copy words
-
-1: move.w [$r0=$r0-2],$r3
- move.w $r3,[$r1=$r1-2]
- subq 1, $r2
- bne 1b
- nop
-
-2:
- ;; Dont worry that the BSS is tainted. It will be cleared later.
-
- moveq 0, $r0
- move.d $r0, [romfs_in_flash]
-
- jump _start_it ; better skip the additional cramfs check below
-
-_start_it:
-
- ;; Check if kernel command line is supplied
- cmp.d COMMAND_LINE_MAGIC, $r10
- bne no_command_line
- nop
-
- move.d 256, $r13
- move.d cris_command_line, $r10
- or.d 0x80000000, $r11 ; Make it virtual
-1:
- move.b [$r11+], $r12
- move.b $r12, [$r10+]
- subq 1, $r13
- bne 1b
- nop
-
-no_command_line:
-
- ;; the kernel stack is overlayed with the task structure for each
- ;; task. thus the initial kernel stack is in the same page as the
- ;; init_task (but starts in the top of the page, size 8192)
- move.d init_thread_union + 8192, $sp
- move.d ibr_start,$r0 ; this symbol is set by the linker script
- move $r0,$ibr
- move.d $r0,[etrax_irv] ; set the interrupt base register and pointer
-
- ;; Clear BSS region, from _bss_start to _end
-
- move.d __bss_start, $r0
- move.d _end, $r1
-1: clear.d [$r0+]
- cmp.d $r1, $r0
- blo 1b
- nop
-
- ;; Etrax product HW genconfig setup
-
- moveq 0,$r0
-
- ;; Select or disable serial port 2
-#ifdef CONFIG_ETRAX_SERIAL_PORT2
- or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0
-#else
- or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0
-#endif
-
- ;; Init interfaces (disable them).
- or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \
- | IO_STATE (R_GEN_CONFIG, ata, disable) \
- | IO_STATE (R_GEN_CONFIG, par0, disable) \
- | IO_STATE (R_GEN_CONFIG, mio, disable) \
- | IO_STATE (R_GEN_CONFIG, scsi1, disable) \
- | IO_STATE (R_GEN_CONFIG, scsi0w, disable) \
- | IO_STATE (R_GEN_CONFIG, par1, disable) \
- | IO_STATE (R_GEN_CONFIG, ser3, disable) \
- | IO_STATE (R_GEN_CONFIG, mio_w, disable) \
- | IO_STATE (R_GEN_CONFIG, usb1, disable) \
- | IO_STATE (R_GEN_CONFIG, usb2, disable) \
- | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0
-
- ;; Init DMA channel muxing (set to unused clients).
- or.d IO_STATE (R_GEN_CONFIG, dma2, ata) \
- | IO_STATE (R_GEN_CONFIG, dma3, ata) \
- | IO_STATE (R_GEN_CONFIG, dma4, scsi1) \
- | IO_STATE (R_GEN_CONFIG, dma5, scsi1) \
- | IO_STATE (R_GEN_CONFIG, dma6, unused) \
- | IO_STATE (R_GEN_CONFIG, dma7, unused) \
- | IO_STATE (R_GEN_CONFIG, dma8, usb) \
- | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
-
-
- move.d $r0,[genconfig_shadow] ; init a shadow register of R_GEN_CONFIG
-
- move.d $r0,[R_GEN_CONFIG]
-
-#if 0
- moveq 4,$r0
- move.b $r0,[R_DMA_CH6_CMD] ; reset (ser0 dma out)
- move.b $r0,[R_DMA_CH7_CMD] ; reset (ser0 dma in)
-1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish
- and.b 7,$r0
- cmp.b 4,$r0
- beq 1b
- nop
-1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish
- and.b 7,$r0
- cmp.b 4,$r0
- beq 1b
- nop
-#endif
-
- moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
- move.b $r0,[R_DMA_CH8_CMD] ; reset (ser1 dma out)
- move.b $r0,[R_DMA_CH9_CMD] ; reset (ser1 dma in)
-1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish
- andq IO_MASK (R_DMA_CH8_CMD, cmd),$r0
- cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
- beq 1b
- nop
-1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish
- andq IO_MASK (R_DMA_CH9_CMD, cmd),$r0
- cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0
- beq 1b
- nop
-
- ;; setup port PA and PB default initial directions and data
- ;; including their shadow registers
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR,$r0
- move.b $r0,[port_pa_dir_shadow]
- move.b $r0,[R_PORT_PA_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA,$r0
- move.b $r0,[port_pa_data_shadow]
- move.b $r0,[R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG,$r0
- move.b $r0,[port_pb_config_shadow]
- move.b $r0,[R_PORT_PB_CONFIG]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR,$r0
- move.b $r0,[port_pb_dir_shadow]
- move.b $r0,[R_PORT_PB_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA,$r0
- move.b $r0,[port_pb_data_shadow]
- move.b $r0,[R_PORT_PB_DATA]
-
- moveq 0, $r0
- move.d $r0,[port_pb_i2c_shadow]
- move.d $r0, [R_PORT_PB_I2C]
-
- moveq 0,$r0
- move.d $r0,[port_g_data_shadow]
- move.d $r0,[R_PORT_G_DATA]
-
- ;; setup the serial port 0 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL0_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL0_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL0_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL0_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL0_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL0_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL0_BAUD]
-
- ; Set up and enable the serial0 receiver.
- move.b IO_STATE (R_SERIAL0_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL0_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL0_REC_CTRL]
-
- ; Set up and enable the serial0 transmitter.
- move.b IO_FIELD (R_SERIAL0_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL0_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL0_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL0_TR_CTRL]
-
- ;; setup the serial port 1 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL1_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL1_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL1_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL1_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL1_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL1_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL1_BAUD]
-
- ; Set up and enable the serial1 receiver.
- move.b IO_STATE (R_SERIAL1_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL1_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL1_REC_CTRL]
-
- ; Set up and enable the serial1 transmitter.
- move.b IO_FIELD (R_SERIAL1_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL1_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL1_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL1_TR_CTRL]
-
-#ifdef CONFIG_ETRAX_SERIAL_PORT2
- ;; setup the serial port 2 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL2_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL2_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL2_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL2_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL2_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL2_BAUD]
-
- ; Set up and enable the serial2 receiver.
- move.b IO_STATE (R_SERIAL2_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL2_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL2_REC_CTRL]
-
- ; Set up and enable the serial2 transmitter.
- move.b IO_FIELD (R_SERIAL2_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL2_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL2_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL2_TR_CTRL]
-#endif
-
-#ifdef CONFIG_ETRAX_SERIAL_PORT3
- ;; setup the serial port 3 at 115200 baud for debug purposes
-
- moveq IO_STATE (R_SERIAL3_XOFF, tx_stop, enable) \
- | IO_STATE (R_SERIAL3_XOFF, auto_xoff, disable) \
- | IO_FIELD (R_SERIAL3_XOFF, xoff_char, 0),$r0
- move.d $r0,[R_SERIAL3_XOFF]
-
- ; 115.2kbaud for both transmit and receive
- move.b IO_STATE (R_SERIAL3_BAUD, tr_baud, c115k2Hz) \
- | IO_STATE (R_SERIAL3_BAUD, rec_baud, c115k2Hz),$r0
- move.b $r0,[R_SERIAL3_BAUD]
-
- ; Set up and enable the serial3 receiver.
- move.b IO_STATE (R_SERIAL3_REC_CTRL, dma_err, stop) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_enable, enable) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rts_, active) \
- | IO_STATE (R_SERIAL3_REC_CTRL, sampling, middle) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_stick_par, normal) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_par, even) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_par_en, disable) \
- | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0
- move.b $r0,[R_SERIAL3_REC_CTRL]
-
- ; Set up and enable the serial3 transmitter.
- move.b IO_FIELD (R_SERIAL3_TR_CTRL, txd, 0) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_enable, enable) \
- | IO_STATE (R_SERIAL3_TR_CTRL, auto_cts, disabled) \
- | IO_STATE (R_SERIAL3_TR_CTRL, stop_bits, one_bit) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_stick_par, normal) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_par, even) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_par_en, disable) \
- | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0
- move.b $r0,[R_SERIAL3_TR_CTRL]
-#endif
-
- jump start_kernel ; jump into the C-function start_kernel in init/main.c
-
- .data
-etrax_irv:
- .dword 0
-romfs_start:
- .dword 0
-romfs_length:
- .dword 0
-romfs_in_flash:
- .dword 0
-
- ;; put some special pages at the beginning of the kernel aligned
- ;; to page boundaries - the kernel cannot start until after this
-
-#ifdef CONFIG_CRIS_LOW_MAP
-swapper_pg_dir = 0x60002000
-#else
-swapper_pg_dir = 0xc0002000
-#endif
-
- .section ".init.data", "aw"
-#include "../lib/hw_settings.S"
diff --git a/arch/cris/arch-v10/kernel/io_interface_mux.c b/arch/cris/arch-v10/kernel/io_interface_mux.c
deleted file mode 100644
index 13a887ce115a..000000000000
--- a/arch/cris/arch-v10/kernel/io_interface_mux.c
+++ /dev/null
@@ -1,1183 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* IO interface mux allocator for ETRAX100LX.
- * Copyright 2004-2007, Axis Communications AB
- */
-
-
-/* C.f. ETRAX100LX Designer's Reference chapter 19.9 */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include <arch/svinto.h>
-#include <asm/io.h>
-#include <arch/io_interface_mux.h>
-#include <arch/system.h>
-
-
-#define DBG(s)
-
-/* Macro to access ETRAX 100 registers */
-#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
- IO_STATE_(reg##_, field##_, _##val)
-
-enum io_if_group {
- group_a = (1<<0),
- group_b = (1<<1),
- group_c = (1<<2),
- group_d = (1<<3),
- group_e = (1<<4),
- group_f = (1<<5)
-};
-
-struct watcher
-{
- void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available);
- struct watcher *next;
-};
-
-
-struct if_group
-{
- enum io_if_group group;
- /* name - the name of the group 'A' to 'F' */
- char *name;
- /* used - a bit mask of all pins in the group in the order listed
- * in the tables in 19.9.1 to 19.9.6. Note that no
- * distinction is made between in, out and in/out pins. */
- unsigned int used;
-};
-
-
-struct interface
-{
- enum cris_io_interface ioif;
- /* name - the name of the interface */
- char *name;
- /* groups - OR'ed together io_if_group flags describing what pin groups
- * the interface uses pins in. */
- unsigned char groups;
- /* used - set when the interface is allocated. */
- unsigned char used;
- char *owner;
- /* group_a through group_f - bit masks describing what pins in the
- * pin groups the interface uses. */
- unsigned int group_a;
- unsigned int group_b;
- unsigned int group_c;
- unsigned int group_d;
- unsigned int group_e;
- unsigned int group_f;
-
- /* gpio_g_in, gpio_g_out, gpio_b - bit masks telling what pins in the
- * GPIO ports the interface uses. This could be reconstucted using
- * the group_X masks and a table of what pins the GPIO ports use,
- * but that would be messy. */
- unsigned int gpio_g_in;
- unsigned int gpio_g_out;
- unsigned char gpio_b;
-};
-
-static struct if_group if_groups[6] = {
- {
- .group = group_a,
- .name = "A",
- .used = 0,
- },
- {
- .group = group_b,
- .name = "B",
- .used = 0,
- },
- {
- .group = group_c,
- .name = "C",
- .used = 0,
- },
- {
- .group = group_d,
- .name = "D",
- .used = 0,
- },
- {
- .group = group_e,
- .name = "E",
- .used = 0,
- },
- {
- .group = group_f,
- .name = "F",
- .used = 0,
- }
-};
-
-/* The order in the array must match the order of enum
- * cris_io_interface in io_interface_mux.h */
-static struct interface interfaces[] = {
- /* Begin Non-multiplexed interfaces */
- {
- .ioif = if_eth,
- .name = "ethernet",
- .groups = 0,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0,
- .gpio_g_out = 0,
- .gpio_b = 0
- },
- {
- .ioif = if_serial_0,
- .name = "serial_0",
- .groups = 0,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0,
- .gpio_g_out = 0,
- .gpio_b = 0
- },
- /* End Non-multiplexed interfaces */
- {
- .ioif = if_serial_1,
- .name = "serial_1",
- .groups = group_e,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x0f,
- .group_f = 0,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_serial_2,
- .name = "serial_2",
- .groups = group_b,
-
- .group_a = 0,
- .group_b = 0x0f,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x000000c0,
- .gpio_g_out = 0x000000c0,
- .gpio_b = 0x00
- },
- {
- .ioif = if_serial_3,
- .name = "serial_3",
- .groups = group_c,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0x0f,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0xc0000000,
- .gpio_g_out = 0xc0000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_sync_serial_1,
- .name = "sync_serial_1",
- .groups = group_e | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x0f,
- .group_f = 0x10,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x10
- },
- {
- .ioif = if_sync_serial_3,
- .name = "sync_serial_3",
- .groups = group_c | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0x0f,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0x80,
-
- .gpio_g_in = 0xc0000000,
- .gpio_g_out = 0xc0000000,
- .gpio_b = 0x80
- },
- {
- .ioif = if_shared_ram,
- .name = "shared_ram",
- .groups = group_a,
-
- .group_a = 0x7f8ff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x0000ff3e,
- .gpio_g_out = 0x0000ff38,
- .gpio_b = 0x00
- },
- {
- .ioif = if_shared_ram_w,
- .name = "shared_ram_w",
- .groups = group_a | group_d,
-
- .group_a = 0x7f8ff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0xff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00ffff3e,
- .gpio_g_out = 0x00ffff38,
- .gpio_b = 0x00
- },
- {
- .ioif = if_par_0,
- .name = "par_0",
- .groups = group_a,
-
- .group_a = 0x7fbff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x0000ff3e,
- .gpio_g_out = 0x0000ff3e,
- .gpio_b = 0x00
- },
- {
- .ioif = if_par_1,
- .name = "par_1",
- .groups = group_d,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0x7feff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x3eff0000,
- .gpio_g_out = 0x3eff0000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_par_w,
- .name = "par_w",
- .groups = group_a | group_d,
-
- .group_a = 0x7fbff,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0xff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00ffff3e,
- .gpio_g_out = 0x00ffff3e,
- .gpio_b = 0x00
- },
- {
- .ioif = if_scsi8_0,
- .name = "scsi8_0",
- .groups = group_a | group_b | group_f,
-
- .group_a = 0x7ffff,
- .group_b = 0x0f,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0x10,
-
- .gpio_g_in = 0x0000ffff,
- .gpio_g_out = 0x0000ffff,
- .gpio_b = 0x10
- },
- {
- .ioif = if_scsi8_1,
- .name = "scsi8_1",
- .groups = group_c | group_d | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0x0f,
- .group_d = 0x7ffff,
- .group_e = 0,
- .group_f = 0x80,
-
- .gpio_g_in = 0xffff0000,
- .gpio_g_out = 0xffff0000,
- .gpio_b = 0x80
- },
- {
- .ioif = if_scsi_w,
- .name = "scsi_w",
- .groups = group_a | group_b | group_d | group_f,
-
- .group_a = 0x7ffff,
- .group_b = 0x0f,
- .group_c = 0,
- .group_d = 0x601ff,
- .group_e = 0,
- .group_f = 0x90,
-
- .gpio_g_in = 0x01ffffff,
- .gpio_g_out = 0x07ffffff,
- .gpio_b = 0x80
- },
- {
- .ioif = if_ata,
- .name = "ata",
- .groups = group_a | group_b | group_c | group_d,
-
- .group_a = 0x7ffff,
- .group_b = 0x0f,
- .group_c = 0x0f,
- .group_d = 0x7cfff,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0xf9ffffff,
- .gpio_g_out = 0xffffffff,
- .gpio_b = 0x80
- },
- {
- .ioif = if_csp,
- .name = "csp",
- .groups = group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0xfc,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0xfc
- },
- {
- .ioif = if_i2c,
- .name = "i2c",
- .groups = group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0x03,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x03
- },
- {
- .ioif = if_usb_1,
- .name = "usb_1",
- .groups = group_e | group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x0f,
- .group_f = 0x2c,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x2c
- },
- {
- .ioif = if_usb_2,
- .name = "usb_2",
- .groups = group_d,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0x33e00,
- .group_f = 0,
-
- .gpio_g_in = 0x3e000000,
- .gpio_g_out = 0x0c000000,
- .gpio_b = 0x00
- },
- /* GPIO pins */
- {
- .ioif = if_gpio_grp_a,
- .name = "gpio_a",
- .groups = group_a,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x0000ff3f,
- .gpio_g_out = 0x0000ff3f,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_b,
- .name = "gpio_b",
- .groups = group_b,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x000000c0,
- .gpio_g_out = 0x000000c0,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_c,
- .name = "gpio_c",
- .groups = group_c,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0xc0000000,
- .gpio_g_out = 0xc0000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_d,
- .name = "gpio_d",
- .groups = group_d,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x3fff0000,
- .gpio_g_out = 0x3fff0000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_e,
- .name = "gpio_e",
- .groups = group_e,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0x00
- },
- {
- .ioif = if_gpio_grp_f,
- .name = "gpio_f",
- .groups = group_f,
-
- .group_a = 0,
- .group_b = 0,
- .group_c = 0,
- .group_d = 0,
- .group_e = 0,
- .group_f = 0,
-
- .gpio_g_in = 0x00000000,
- .gpio_g_out = 0x00000000,
- .gpio_b = 0xff
- }
- /* Array end */
-};
-
-static struct watcher *watchers = NULL;
-
-/* The pins that are free to use in the GPIO ports. */
-static unsigned int gpio_in_pins = 0xffffffff;
-static unsigned int gpio_out_pins = 0xffffffff;
-static unsigned char gpio_pb_pins = 0xff;
-static unsigned char gpio_pa_pins = 0xff;
-
-/* Identifiers for the owners of the GPIO pins. */
-static enum cris_io_interface gpio_pa_owners[8];
-static enum cris_io_interface gpio_pb_owners[8];
-static enum cris_io_interface gpio_pg_owners[32];
-
-static int cris_io_interface_init(void);
-
-static unsigned char clear_group_from_set(const unsigned char groups, struct if_group *group)
-{
- return (groups & ~group->group);
-}
-
-
-static struct if_group *get_group(const unsigned char groups)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(if_groups); i++) {
- if (groups & if_groups[i].group) {
- return &if_groups[i];
- }
- }
- return NULL;
-}
-
-
-static void notify_watchers(void)
-{
- struct watcher *w = watchers;
-
- DBG(printk("io_interface_mux: notifying watchers\n"));
-
- while (NULL != w) {
- w->notify((const unsigned int)gpio_in_pins,
- (const unsigned int)gpio_out_pins,
- (const unsigned char)gpio_pa_pins,
- (const unsigned char)gpio_pb_pins);
- w = w->next;
- }
-}
-
-
-int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id)
-{
- int set_gen_config = 0;
- int set_gen_config_ii = 0;
- unsigned long int gens;
- unsigned long int gens_ii;
- struct if_group *grp;
- unsigned char group_set;
- unsigned long flags;
- int res = 0;
-
- (void)cris_io_interface_init();
-
- DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id));
-
- if ((ioif >= if_max_interfaces) || (ioif < 0)) {
- printk(KERN_CRIT "cris_request_io_interface: Bad interface "
- "%u submitted for %s\n",
- ioif,
- device_id);
- return -EINVAL;
- }
-
- local_irq_save(flags);
-
- if (interfaces[ioif].used) {
- printk(KERN_CRIT "cris_io_interface: Cannot allocate interface "
- "%s for %s, in use by %s\n",
- interfaces[ioif].name,
- device_id,
- interfaces[ioif].owner);
- res = -EBUSY;
- goto exit;
- }
-
- /* Check that all required pins in the used groups are free
- * before allocating. */
- group_set = interfaces[ioif].groups;
- while (NULL != (grp = get_group(group_set))) {
- unsigned int if_group_use = 0;
-
- switch (grp->group) {
- case group_a:
- if_group_use = interfaces[ioif].group_a;
- break;
- case group_b:
- if_group_use = interfaces[ioif].group_b;
- break;
- case group_c:
- if_group_use = interfaces[ioif].group_c;
- break;
- case group_d:
- if_group_use = interfaces[ioif].group_d;
- break;
- case group_e:
- if_group_use = interfaces[ioif].group_e;
- break;
- case group_f:
- if_group_use = interfaces[ioif].group_f;
- break;
- default:
- BUG_ON(1);
- }
-
- if (if_group_use & grp->used) {
- printk(KERN_INFO "cris_request_io_interface: group "
- "%s needed by %s not available\n",
- grp->name, interfaces[ioif].name);
- res = -EBUSY;
- goto exit;
- }
-
- group_set = clear_group_from_set(group_set, grp);
- }
-
- /* Are the required GPIO pins available too? */
- if (((interfaces[ioif].gpio_g_in & gpio_in_pins) !=
- interfaces[ioif].gpio_g_in) ||
- ((interfaces[ioif].gpio_g_out & gpio_out_pins) !=
- interfaces[ioif].gpio_g_out) ||
- ((interfaces[ioif].gpio_b & gpio_pb_pins) !=
- interfaces[ioif].gpio_b)) {
- printk(KERN_CRIT "cris_request_io_interface: Could not get "
- "required pins for interface %u\n", ioif);
- res = -EBUSY;
- goto exit;
- }
-
- /* Check which registers need to be reconfigured. */
- gens = genconfig_shadow;
- gens_ii = gen_config_ii_shadow;
-
- set_gen_config = 1;
- switch (ioif)
- {
- /* Begin Non-multiplexed interfaces */
- case if_eth:
- /* fall through */
- case if_serial_0:
- set_gen_config = 0;
- break;
- /* End Non-multiplexed interfaces */
- case if_serial_1:
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode1, async);
- break;
- case if_serial_2:
- SETS(gens, R_GEN_CONFIG, ser2, select);
- break;
- case if_serial_3:
- SETS(gens, R_GEN_CONFIG, ser3, select);
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode3, async);
- break;
- case if_sync_serial_1:
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode1, sync);
- break;
- case if_sync_serial_3:
- SETS(gens, R_GEN_CONFIG, ser3, select);
- set_gen_config_ii = 1;
- SETS(gens_ii, R_GEN_CONFIG_II, sermode3, sync);
- break;
- case if_shared_ram:
- SETS(gens, R_GEN_CONFIG, mio, select);
- break;
- case if_shared_ram_w:
- SETS(gens, R_GEN_CONFIG, mio_w, select);
- break;
- case if_par_0:
- SETS(gens, R_GEN_CONFIG, par0, select);
- break;
- case if_par_1:
- SETS(gens, R_GEN_CONFIG, par1, select);
- break;
- case if_par_w:
- SETS(gens, R_GEN_CONFIG, par0, select);
- SETS(gens, R_GEN_CONFIG, par_w, select);
- break;
- case if_scsi8_0:
- SETS(gens, R_GEN_CONFIG, scsi0, select);
- break;
- case if_scsi8_1:
- SETS(gens, R_GEN_CONFIG, scsi1, select);
- break;
- case if_scsi_w:
- SETS(gens, R_GEN_CONFIG, scsi0, select);
- SETS(gens, R_GEN_CONFIG, scsi0w, select);
- break;
- case if_ata:
- SETS(gens, R_GEN_CONFIG, ata, select);
- break;
- case if_csp:
- /* fall through */
- case if_i2c:
- set_gen_config = 0;
- break;
- case if_usb_1:
- SETS(gens, R_GEN_CONFIG, usb1, select);
- break;
- case if_usb_2:
- SETS(gens, R_GEN_CONFIG, usb2, select);
- break;
- case if_gpio_grp_a:
- /* GPIO groups are only accounted, don't do configuration changes. */
- /* fall through */
- case if_gpio_grp_b:
- /* fall through */
- case if_gpio_grp_c:
- /* fall through */
- case if_gpio_grp_d:
- /* fall through */
- case if_gpio_grp_e:
- /* fall through */
- case if_gpio_grp_f:
- set_gen_config = 0;
- break;
- default:
- printk(KERN_INFO "cris_request_io_interface: Bad interface "
- "%u submitted for %s\n",
- ioif, device_id);
- res = -EBUSY;
- goto exit;
- }
-
- /* All needed I/O pins and pin groups are free, allocate. */
- group_set = interfaces[ioif].groups;
- while (NULL != (grp = get_group(group_set))) {
- unsigned int if_group_use = 0;
-
- switch (grp->group) {
- case group_a:
- if_group_use = interfaces[ioif].group_a;
- break;
- case group_b:
- if_group_use = interfaces[ioif].group_b;
- break;
- case group_c:
- if_group_use = interfaces[ioif].group_c;
- break;
- case group_d:
- if_group_use = interfaces[ioif].group_d;
- break;
- case group_e:
- if_group_use = interfaces[ioif].group_e;
- break;
- case group_f:
- if_group_use = interfaces[ioif].group_f;
- break;
- default:
- BUG_ON(1);
- }
- grp->used |= if_group_use;
-
- group_set = clear_group_from_set(group_set, grp);
- }
-
- interfaces[ioif].used = 1;
- interfaces[ioif].owner = (char*)device_id;
-
- if (set_gen_config) {
- volatile int i;
- genconfig_shadow = gens;
- *R_GEN_CONFIG = genconfig_shadow;
- /* Wait 12 cycles before doing any DMA command */
- for(i = 6; i > 0; i--)
- nop();
- }
- if (set_gen_config_ii) {
- gen_config_ii_shadow = gens_ii;
- *R_GEN_CONFIG_II = gen_config_ii_shadow;
- }
-
- DBG(printk(KERN_DEBUG "GPIO pins: available before: "
- "g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
- DBG(printk(KERN_DEBUG
- "grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- interfaces[ioif].gpio_g_in,
- interfaces[ioif].gpio_g_out,
- interfaces[ioif].gpio_b));
-
- gpio_in_pins &= ~interfaces[ioif].gpio_g_in;
- gpio_out_pins &= ~interfaces[ioif].gpio_g_out;
- gpio_pb_pins &= ~interfaces[ioif].gpio_b;
-
- DBG(printk(KERN_DEBUG "GPIO pins: available after: "
- "g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
-
-exit:
- local_irq_restore(flags);
- if (res == 0)
- notify_watchers();
- return res;
-}
-
-
-void cris_free_io_interface(enum cris_io_interface ioif)
-{
- struct if_group *grp;
- unsigned char group_set;
- unsigned long flags;
-
- (void)cris_io_interface_init();
-
- if ((ioif >= if_max_interfaces) || (ioif < 0)) {
- printk(KERN_CRIT "cris_free_io_interface: Bad interface %u\n",
- ioif);
- return;
- }
- local_irq_save(flags);
- if (!interfaces[ioif].used) {
- printk(KERN_CRIT "cris_free_io_interface: Freeing free interface %u\n",
- ioif);
- local_irq_restore(flags);
- return;
- }
- group_set = interfaces[ioif].groups;
- while (NULL != (grp = get_group(group_set))) {
- unsigned int if_group_use = 0;
-
- switch (grp->group) {
- case group_a:
- if_group_use = interfaces[ioif].group_a;
- break;
- case group_b:
- if_group_use = interfaces[ioif].group_b;
- break;
- case group_c:
- if_group_use = interfaces[ioif].group_c;
- break;
- case group_d:
- if_group_use = interfaces[ioif].group_d;
- break;
- case group_e:
- if_group_use = interfaces[ioif].group_e;
- break;
- case group_f:
- if_group_use = interfaces[ioif].group_f;
- break;
- default:
- BUG_ON(1);
- }
-
- if ((grp->used & if_group_use) != if_group_use)
- BUG_ON(1);
- grp->used = grp->used & ~if_group_use;
-
- group_set = clear_group_from_set(group_set, grp);
- }
- interfaces[ioif].used = 0;
- interfaces[ioif].owner = NULL;
-
- DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
- DBG(printk("freeing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- interfaces[ioif].gpio_g_in,
- interfaces[ioif].gpio_g_out,
- interfaces[ioif].gpio_b));
-
- gpio_in_pins |= interfaces[ioif].gpio_g_in;
- gpio_out_pins |= interfaces[ioif].gpio_g_out;
- gpio_pb_pins |= interfaces[ioif].gpio_b;
-
- DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
-
- local_irq_restore(flags);
-
- notify_watchers();
-}
-
-/* Create a bitmask from bit 0 (inclusive) to bit stop_bit
- (non-inclusive). stop_bit == 0 returns 0x0 */
-static inline unsigned int create_mask(const unsigned stop_bit)
-{
- /* Avoid overflow */
- if (stop_bit >= 32) {
- return 0xffffffff;
- }
- return (1<<stop_bit)-1;
-}
-
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit)
-{
- unsigned int i;
- unsigned int mask = 0;
- unsigned int tmp_mask;
- unsigned long int flags;
- enum cris_io_interface *owners;
-
- (void)cris_io_interface_init();
-
- DBG(printk("cris_io_interface_allocate_pins: if=%d port=%c start=%u stop=%u\n",
- ioif, port, start_bit, stop_bit));
-
- if (!((start_bit <= stop_bit) &&
- ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
- ((port == 'g') && (stop_bit < 32))))) {
- return -EINVAL;
- }
-
- mask = create_mask(stop_bit + 1);
- tmp_mask = create_mask(start_bit);
- mask &= ~tmp_mask;
-
- DBG(printk("cris_io_interface_allocate_pins: port=%c start=%u stop=%u mask=0x%08x\n",
- port, start_bit, stop_bit, mask));
-
- local_irq_save(flags);
-
- switch (port) {
- case 'a':
- if ((gpio_pa_pins & mask) != mask) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- owners = gpio_pa_owners;
- gpio_pa_pins &= ~mask;
- break;
- case 'b':
- if ((gpio_pb_pins & mask) != mask) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- owners = gpio_pb_owners;
- gpio_pb_pins &= ~mask;
- break;
- case 'g':
- if (((gpio_in_pins & mask) != mask) ||
- ((gpio_out_pins & mask) != mask)) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- owners = gpio_pg_owners;
- gpio_in_pins &= ~mask;
- gpio_out_pins &= ~mask;
- break;
- default:
- local_irq_restore(flags);
- return -EINVAL;
- }
-
- for (i = start_bit; i <= stop_bit; i++) {
- owners[i] = ioif;
- }
- local_irq_restore(flags);
-
- notify_watchers();
- return 0;
-}
-
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_free_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit)
-{
- unsigned int i;
- unsigned int mask = 0;
- unsigned int tmp_mask;
- unsigned long int flags;
- enum cris_io_interface *owners;
-
- (void)cris_io_interface_init();
-
- if (!((start_bit <= stop_bit) &&
- ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
- ((port == 'g') && (stop_bit < 32))))) {
- return -EINVAL;
- }
-
- mask = create_mask(stop_bit + 1);
- tmp_mask = create_mask(start_bit);
- mask &= ~tmp_mask;
-
- DBG(printk("cris_io_interface_free_pins: port=%c start=%u stop=%u mask=0x%08x\n",
- port, start_bit, stop_bit, mask));
-
- local_irq_save(flags);
-
- switch (port) {
- case 'a':
- if ((~gpio_pa_pins & mask) != mask) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
- }
- owners = gpio_pa_owners;
- break;
- case 'b':
- if ((~gpio_pb_pins & mask) != mask) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
- }
- owners = gpio_pb_owners;
- break;
- case 'g':
- if (((~gpio_in_pins & mask) != mask) ||
- ((~gpio_out_pins & mask) != mask)) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
- }
- owners = gpio_pg_owners;
- break;
- default:
- owners = NULL; /* Cannot happen. Shut up, gcc! */
- }
-
- for (i = start_bit; i <= stop_bit; i++) {
- if (owners[i] != ioif) {
- printk(KERN_CRIT "cris_io_interface_free_pins: Freeing unowned pins");
- }
- }
-
- /* All was ok, change data. */
- switch (port) {
- case 'a':
- gpio_pa_pins |= mask;
- break;
- case 'b':
- gpio_pb_pins |= mask;
- break;
- case 'g':
- gpio_in_pins |= mask;
- gpio_out_pins |= mask;
- break;
- }
-
- for (i = start_bit; i <= stop_bit; i++) {
- owners[i] = if_unclaimed;
- }
- local_irq_restore(flags);
- notify_watchers();
-
- return 0;
-}
-
-
-int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available))
-{
- struct watcher *w;
-
- (void)cris_io_interface_init();
-
- if (NULL == notify) {
- return -EINVAL;
- }
- w = kmalloc(sizeof(*w), GFP_KERNEL);
- if (!w) {
- return -ENOMEM;
- }
- w->notify = notify;
- w->next = watchers;
- watchers = w;
-
- w->notify((const unsigned int)gpio_in_pins,
- (const unsigned int)gpio_out_pins,
- (const unsigned char)gpio_pa_pins,
- (const unsigned char)gpio_pb_pins);
-
- return 0;
-}
-
-void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available))
-{
- struct watcher *w = watchers, *prev = NULL;
-
- (void)cris_io_interface_init();
-
- while ((NULL != w) && (w->notify != notify)){
- prev = w;
- w = w->next;
- }
- if (NULL != w) {
- if (NULL != prev) {
- prev->next = w->next;
- } else {
- watchers = w->next;
- }
- kfree(w);
- return;
- }
- printk(KERN_WARNING "cris_io_interface_delete_watcher: Deleting unknown watcher 0x%p\n", notify);
-}
-
-
-static int cris_io_interface_init(void)
-{
- static int first = 1;
- int i;
-
- if (!first) {
- return 0;
- }
- first = 0;
-
- for (i = 0; i<8; i++) {
- gpio_pa_owners[i] = if_unclaimed;
- gpio_pb_owners[i] = if_unclaimed;
- gpio_pg_owners[i] = if_unclaimed;
- }
- for (; i<32; i++) {
- gpio_pg_owners[i] = if_unclaimed;
- }
- return 0;
-}
-
-
-module_init(cris_io_interface_init);
-
-
-EXPORT_SYMBOL(cris_request_io_interface);
-EXPORT_SYMBOL(cris_free_io_interface);
-EXPORT_SYMBOL(cris_io_interface_allocate_pins);
-EXPORT_SYMBOL(cris_io_interface_free_pins);
-EXPORT_SYMBOL(cris_io_interface_register_watcher);
-EXPORT_SYMBOL(cris_io_interface_delete_watcher);
diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c
deleted file mode 100644
index df11e383acdd..000000000000
--- a/arch/cris/arch-v10/kernel/irq.c
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/irq.c
- *
- * Copyright (c) 2000-2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- * This file contains the interrupt vectors and some
- * helper functions
- *
- */
-
-#include <asm/irq.h>
-#include <asm/current.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#define crisv10_mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
-#define crisv10_unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
-
-extern void kgdb_init(void);
-extern void breakpoint(void);
-
-/* don't use set_int_vector, it bypasses the linux interrupt handlers. it is
- * global just so that the kernel gdb can use it.
- */
-
-void
-set_int_vector(int n, irqvectptr addr)
-{
- etrax_irv->v[n + 0x20] = (irqvectptr)addr;
-}
-
-/* the breakpoint vector is obviously not made just like the normal irq handlers
- * but needs to contain _code_ to jump to addr.
- *
- * the BREAK n instruction jumps to IBR + n * 8
- */
-
-void
-set_break_vector(int n, irqvectptr addr)
-{
- unsigned short *jinstr = (unsigned short *)&etrax_irv->v[n*2];
- unsigned long *jaddr = (unsigned long *)(jinstr + 1);
-
- /* if you don't know what this does, do not touch it! */
-
- *jinstr = 0x0d3f;
- *jaddr = (unsigned long)addr;
-
- /* 00000026 <clrlop+1a> 3f0d82000000 jump 0x82 */
-}
-
-/*
- * This builds up the IRQ handler stubs using some ugly macros in irq.h
- *
- * These macros create the low-level assembly IRQ routines that do all
- * the operations that are needed. They are also written to be fast - and to
- * disable interrupts as little as humanly possible.
- *
- */
-
-/* IRQ0 and 1 are special traps */
-void hwbreakpoint(void);
-void IRQ1_interrupt(void);
-BUILD_TIMER_IRQ(2, 0x04) /* the timer interrupt is somewhat special */
-BUILD_IRQ(3, 0x08)
-BUILD_IRQ(4, 0x10)
-BUILD_IRQ(5, 0x20)
-BUILD_IRQ(6, 0x40)
-BUILD_IRQ(7, 0x80)
-BUILD_IRQ(8, 0x100)
-BUILD_IRQ(9, 0x200)
-BUILD_IRQ(10, 0x400)
-BUILD_IRQ(11, 0x800)
-BUILD_IRQ(12, 0x1000)
-BUILD_IRQ(13, 0x2000)
-void mmu_bus_fault(void); /* IRQ 14 is the bus fault interrupt */
-void multiple_interrupt(void); /* IRQ 15 is the multiple IRQ interrupt */
-BUILD_IRQ(16, 0x10000 | 0x20000) /* ethernet tx interrupt needs to block rx */
-BUILD_IRQ(17, 0x20000 | 0x10000) /* ...and vice versa */
-BUILD_IRQ(18, 0x40000)
-BUILD_IRQ(19, 0x80000)
-BUILD_IRQ(20, 0x100000)
-BUILD_IRQ(21, 0x200000)
-BUILD_IRQ(22, 0x400000)
-BUILD_IRQ(23, 0x800000)
-BUILD_IRQ(24, 0x1000000)
-BUILD_IRQ(25, 0x2000000)
-/* IRQ 26-30 are reserved */
-BUILD_IRQ(31, 0x80000000)
-
-/*
- * Pointers to the low-level handlers
- */
-
-static void (*interrupt[NR_IRQS])(void) = {
- NULL, NULL, IRQ2_interrupt, IRQ3_interrupt,
- IRQ4_interrupt, IRQ5_interrupt, IRQ6_interrupt, IRQ7_interrupt,
- IRQ8_interrupt, IRQ9_interrupt, IRQ10_interrupt, IRQ11_interrupt,
- IRQ12_interrupt, IRQ13_interrupt, NULL, NULL,
- IRQ16_interrupt, IRQ17_interrupt, IRQ18_interrupt, IRQ19_interrupt,
- IRQ20_interrupt, IRQ21_interrupt, IRQ22_interrupt, IRQ23_interrupt,
- IRQ24_interrupt, IRQ25_interrupt, NULL, NULL, NULL, NULL, NULL,
- IRQ31_interrupt
-};
-
-static void enable_crisv10_irq(struct irq_data *data)
-{
- crisv10_unmask_irq(data->irq);
-}
-
-static void disable_crisv10_irq(struct irq_data *data)
-{
- crisv10_mask_irq(data->irq);
-}
-
-static struct irq_chip crisv10_irq_type = {
- .name = "CRISv10",
- .irq_shutdown = disable_crisv10_irq,
- .irq_enable = enable_crisv10_irq,
- .irq_disable = disable_crisv10_irq,
-};
-
-void weird_irq(void);
-void system_call(void); /* from entry.S */
-void do_sigtrap(void); /* from entry.S */
-void gdb_handle_breakpoint(void); /* from entry.S */
-
-extern void do_IRQ(int irq, struct pt_regs * regs);
-
-/* Handle multiple IRQs */
-void do_multiple_IRQ(struct pt_regs* regs)
-{
- int bit;
- unsigned masked;
- unsigned mask;
- unsigned ethmask = 0;
-
- /* Get interrupts to mask and handle */
- mask = masked = *R_VECT_MASK_RD;
-
- /* Never mask timer IRQ */
- mask &= ~(IO_MASK(R_VECT_MASK_RD, timer0));
-
- /*
- * If either ethernet interrupt (rx or tx) is active then block
- * the other one too. Unblock afterwards also.
- */
- if (mask &
- (IO_STATE(R_VECT_MASK_RD, dma0, active) |
- IO_STATE(R_VECT_MASK_RD, dma1, active))) {
- ethmask = (IO_MASK(R_VECT_MASK_RD, dma0) |
- IO_MASK(R_VECT_MASK_RD, dma1));
- }
-
- /* Block them */
- *R_VECT_MASK_CLR = (mask | ethmask);
-
- /* An extra irq_enter here to prevent softIRQs to run after
- * each do_IRQ. This will decrease the interrupt latency.
- */
- irq_enter();
-
- /* Handle all IRQs */
- for (bit = 2; bit < 32; bit++) {
- if (masked & (1 << bit)) {
- do_IRQ(bit, regs);
- }
- }
-
- /* This irq_exit() will trigger the soft IRQs. */
- irq_exit();
-
- /* Unblock the IRQs again */
- *R_VECT_MASK_SET = (masked | ethmask);
-}
-
-/* init_IRQ() is called by start_kernel and is responsible for fixing IRQ masks and
- setting the irq vector table.
-*/
-
-void __init init_IRQ(void)
-{
- int i;
-
- /* clear all interrupt masks */
- *R_IRQ_MASK0_CLR = 0xffffffff;
- *R_IRQ_MASK1_CLR = 0xffffffff;
- *R_IRQ_MASK2_CLR = 0xffffffff;
- *R_VECT_MASK_CLR = 0xffffffff;
-
- for (i = 0; i < 256; i++)
- etrax_irv->v[i] = weird_irq;
-
- /* Initialize IRQ handler descriptors. */
- for(i = 2; i < NR_IRQS; i++) {
- irq_set_chip_and_handler(i, &crisv10_irq_type,
- handle_simple_irq);
- set_int_vector(i, interrupt[i]);
- }
-
- /* the entries in the break vector contain actual code to be
- executed by the associated break handler, rather than just a jump
- address. therefore we need to setup a default breakpoint handler
- for all breakpoints */
- for (i = 0; i < 16; i++)
- set_break_vector(i, do_sigtrap);
-
- /* except IRQ 15 which is the multiple-IRQ handler on Etrax100 */
- set_int_vector(15, multiple_interrupt);
-
- /* 0 and 1 which are special breakpoint/NMI traps */
- set_int_vector(0, hwbreakpoint);
- set_int_vector(1, IRQ1_interrupt);
-
- /* and irq 14 which is the mmu bus fault handler */
- set_int_vector(14, mmu_bus_fault);
-
- /* setup the system-call trap, which is reached by BREAK 13 */
- set_break_vector(13, system_call);
-
- /* setup a breakpoint handler for debugging used for both user and
- kernel mode debugging (which is why it is not inside an ifdef
- CONFIG_ETRAX_KGDB) */
- set_break_vector(8, gdb_handle_breakpoint);
-
-#ifdef CONFIG_ETRAX_KGDB
- /* setup kgdb if its enabled, and break into the debugger */
- kgdb_init();
- breakpoint();
-#endif
-}
diff --git a/arch/cris/arch-v10/kernel/kgdb.c b/arch/cris/arch-v10/kernel/kgdb.c
deleted file mode 100644
index 79b13564d15c..000000000000
--- a/arch/cris/arch-v10/kernel/kgdb.c
+++ /dev/null
@@ -1,1128 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*!**************************************************************************
-*!
-*! FILE NAME : kgdb.c
-*!
-*! DESCRIPTION: Implementation of the gdb stub with respect to ETRAX 100.
-*! It is a mix of arch/m68k/kernel/kgdb.c and cris_stub.c.
-*!
-*!---------------------------------------------------------------------------
-*! HISTORY
-*!
-*! DATE NAME CHANGES
-*! ---- ---- -------
-*! Apr 26 1999 Hendrik Ruijter Initial version.
-*! May 6 1999 Hendrik Ruijter Removed call to strlen in libc and removed
-*! struct assignment as it generates calls to
-*! memcpy in libc.
-*! Jun 17 1999 Hendrik Ruijter Added gdb 4.18 support. 'X', 'qC' and 'qL'.
-*! Jul 21 1999 Bjorn Wesen eLinux port
-*!
-*!---------------------------------------------------------------------------
-*!
-*! (C) Copyright 1999, Axis Communications AB, LUND, SWEDEN
-*!
-*!**************************************************************************/
-/* @(#) cris_stub.c 1.3 06/17/99 */
-
-/*
- * kgdb usage notes:
- * -----------------
- *
- * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
- * built with different gcc flags: "-g" is added to get debug infos, and
- * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
- * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
- * before compresion. Such a kernel will behave just as usually, except if
- * given a "debug=<device>" command line option. (Only serial devices are
- * allowed for <device>, i.e. no printers or the like; possible values are
- * machine depedend and are the same as for the usual debug device, the one
- * for logging kernel messages.) If that option is given and the device can be
- * initialized, the kernel will connect to the remote gdb in trap_init(). The
- * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
- * implementation.
- *
- * To start a debugging session, start that gdb with the debugging kernel
- * image (the one with the symbols, vmlinux.debug) named on the command line.
- * This file will be used by gdb to get symbol and debugging infos about the
- * kernel. Next, select remote debug mode by
- * target remote <device>
- * where <device> is the name of the serial device over which the debugged
- * machine is connected. Maybe you have to adjust the baud rate by
- * set remotebaud <rate>
- * or also other parameters with stty:
- * shell stty ... </dev/...
- * If the kernel to debug has already booted, it waited for gdb and now
- * connects, and you'll see a breakpoint being reported. If the kernel isn't
- * running yet, start it now. The order of gdb and the kernel doesn't matter.
- * Another thing worth knowing about in the getting-started phase is how to
- * debug the remote protocol itself. This is activated with
- * set remotedebug 1
- * gdb will then print out each packet sent or received. You'll also get some
- * messages about the gdb stub on the console of the debugged machine.
- *
- * If all that works, you can use lots of the usual debugging techniques on
- * the kernel, e.g. inspecting and changing variables/memory, setting
- * breakpoints, single stepping and so on. It's also possible to interrupt the
- * debugged kernel by pressing C-c in gdb. Have fun! :-)
- *
- * The gdb stub is entered (and thus the remote gdb gets control) in the
- * following situations:
- *
- * - If breakpoint() is called. This is just after kgdb initialization, or if
- * a breakpoint() call has been put somewhere into the kernel source.
- * (Breakpoints can of course also be set the usual way in gdb.)
- * In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
- *
- * - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
- * are entered. All the CPU exceptions are mapped to (more or less..., see
- * the hard_trap_info array below) appropriate signal, which are reported
- * to gdb. die_if_kernel() is usually called after some kind of access
- * error and thus is reported as SIGSEGV.
- *
- * - When panic() is called. This is reported as SIGABRT.
- *
- * - If C-c is received over the serial line, which is treated as
- * SIGINT.
- *
- * Of course, all these signals are just faked for gdb, since there is no
- * signal concept as such for the kernel. It also isn't possible --obviously--
- * to set signal handlers from inside gdb, or restart the kernel with a
- * signal.
- *
- * Current limitations:
- *
- * - While the kernel is stopped, interrupts are disabled for safety reasons
- * (i.e., variables not changing magically or the like). But this also
- * means that the clock isn't running anymore, and that interrupts from the
- * hardware may get lost/not be served in time. This can cause some device
- * errors...
- *
- * - When single-stepping, only one instruction of the current thread is
- * executed, but interrupts are allowed for that time and will be serviced
- * if pending. Be prepared for that.
- *
- * - All debugging happens in kernel virtual address space. There's no way to
- * access physical memory not mapped in kernel space, or to access user
- * space. A way to work around this is using get_user_long & Co. in gdb
- * expressions, but only for the current process.
- *
- * - Interrupting the kernel only works if interrupts are currently allowed,
- * and the interrupt of the serial line isn't blocked by some other means
- * (IPL too high, disabled, ...)
- *
- * - The gdb stub is currently not reentrant, i.e. errors that happen therein
- * (e.g. accessing invalid memory) may not be caught correctly. This could
- * be removed in future by introducing a stack of struct registers.
- *
- */
-
-/*
- * To enable debugger support, two things need to happen. One, a
- * call to kgdb_init() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint().
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
- * baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- */
-
-
-#include <linux/string.h>
-#include <linux/signal.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/linkage.h>
-#include <linux/reboot.h>
-
-#include <asm/setup.h>
-#include <asm/ptrace.h>
-
-#include <arch/svinto.h>
-#include <asm/irq.h>
-
-static int kgdb_started = 0;
-
-/********************************* Register image ****************************/
-/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's
- Reference", p. 1-1, with the additional register definitions of the
- ETRAX 100LX in cris-opc.h.
- There are 16 general 32-bit registers, R0-R15, where R14 is the stack
- pointer, SP, and R15 is the program counter, PC.
- There are 16 special registers, P0-P15, where three of the unimplemented
- registers, P0, P4 and P8, are reserved as zero-registers. A read from
- any of these registers returns zero and a write has no effect. */
-
-typedef
-struct register_image
-{
- /* Offset */
- unsigned int r0; /* 0x00 */
- unsigned int r1; /* 0x04 */
- unsigned int r2; /* 0x08 */
- unsigned int r3; /* 0x0C */
- unsigned int r4; /* 0x10 */
- unsigned int r5; /* 0x14 */
- unsigned int r6; /* 0x18 */
- unsigned int r7; /* 0x1C */
- unsigned int r8; /* 0x20 Frame pointer */
- unsigned int r9; /* 0x24 */
- unsigned int r10; /* 0x28 */
- unsigned int r11; /* 0x2C */
- unsigned int r12; /* 0x30 */
- unsigned int r13; /* 0x34 */
- unsigned int sp; /* 0x38 Stack pointer */
- unsigned int pc; /* 0x3C Program counter */
-
- unsigned char p0; /* 0x40 8-bit zero-register */
- unsigned char vr; /* 0x41 Version register */
-
- unsigned short p4; /* 0x42 16-bit zero-register */
- unsigned short ccr; /* 0x44 Condition code register */
-
- unsigned int mof; /* 0x46 Multiply overflow register */
-
- unsigned int p8; /* 0x4A 32-bit zero-register */
- unsigned int ibr; /* 0x4E Interrupt base register */
- unsigned int irp; /* 0x52 Interrupt return pointer */
- unsigned int srp; /* 0x56 Subroutine return pointer */
- unsigned int bar; /* 0x5A Breakpoint address register */
- unsigned int dccr; /* 0x5E Double condition code register */
- unsigned int brp; /* 0x62 Breakpoint return pointer (pc in caller) */
- unsigned int usp; /* 0x66 User mode stack pointer */
-} registers;
-
-/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
-int getDebugChar (void);
-
-/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
-void putDebugChar (int val);
-
-void enableDebugIRQ (void);
-
-/******************** Prototypes for global functions. ***********************/
-
-/* The string str is prepended with the GDB printout token and sent. */
-void putDebugString (const unsigned char *str, int length); /* used by etrax100ser.c */
-
-/* The hook for both static (compiled) and dynamic breakpoints set by GDB.
- ETRAX 100 specific. */
-void handle_breakpoint (void); /* used by irq.c */
-
-/* The hook for an interrupt generated by GDB. ETRAX 100 specific. */
-void handle_interrupt (void); /* used by irq.c */
-
-/* A static breakpoint to be used at startup. */
-void breakpoint (void); /* called by init/main.c */
-
-/* From osys_int.c, executing_task contains the number of the current
- executing task in osys. Does not know of object-oriented threads. */
-extern unsigned char executing_task;
-
-/* The number of characters used for a 64 bit thread identifier. */
-#define HEXCHARS_IN_THREAD_ID 16
-
-/********************************** Packet I/O ******************************/
-/* BUFMAX defines the maximum number of characters in
- inbound/outbound buffers */
-#define BUFMAX 512
-
-/* Run-length encoding maximum length. Send 64 at most. */
-#define RUNLENMAX 64
-
-/* The inbound/outbound buffers used in packet I/O */
-static char remcomInBuffer[BUFMAX];
-static char remcomOutBuffer[BUFMAX];
-
-/* Error and warning messages. */
-enum error_type
-{
- SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
-};
-static char *error_message[] =
-{
- "",
- "E01 Set current or general thread - H[c,g] - internal error.",
- "E02 Change register content - P - cannot change read-only register.",
- "E03 Thread is not alive.", /* T, not used. */
- "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
- "E05 Change register content - P - the register is not implemented..",
- "E06 Change memory content - M - internal error.",
- "E07 Change register content - P - the register is not stored on the stack",
- "E08 Invalid parameter"
-};
-/********************************* Register image ****************************/
-/* Use the order of registers as defined in "AXIS ETRAX CRIS Programmer's
- Reference", p. 1-1, with the additional register definitions of the
- ETRAX 100LX in cris-opc.h.
- There are 16 general 32-bit registers, R0-R15, where R14 is the stack
- pointer, SP, and R15 is the program counter, PC.
- There are 16 special registers, P0-P15, where three of the unimplemented
- registers, P0, P4 and P8, are reserved as zero-registers. A read from
- any of these registers returns zero and a write has no effect. */
-enum register_name
-{
- R0, R1, R2, R3,
- R4, R5, R6, R7,
- R8, R9, R10, R11,
- R12, R13, SP, PC,
- P0, VR, P2, P3,
- P4, CCR, P6, MOF,
- P8, IBR, IRP, SRP,
- BAR, DCCR, BRP, USP
-};
-
-/* The register sizes of the registers in register_name. An unimplemented register
- is designated by size 0 in this array. */
-static int register_size[] =
-{
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 1, 1, 0, 0,
- 2, 2, 0, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4
-};
-
-/* Contains the register image of the executing thread in the assembler
- part of the code in order to avoid horrible addressing modes. */
-registers cris_reg;
-
-/* FIXME: Should this be used? Delete otherwise. */
-/* Contains the assumed consistency state of the register image. Uses the
- enum error_type for state information. */
-static int consistency_status = SUCCESS;
-
-/********************************** Handle exceptions ************************/
-/* The variable cris_reg contains the register image associated with the
- current_thread_c variable. It is a complete register image created at
- entry. The reg_g contains a register image of a task where the general
- registers are taken from the stack and all special registers are taken
- from the executing task. It is associated with current_thread_g and used
- in order to provide access mainly for 'g', 'G' and 'P'.
-*/
-
-/********************************** Breakpoint *******************************/
-/* Use an internal stack in the breakpoint and interrupt response routines */
-#define INTERNAL_STACK_SIZE 1024
-char internal_stack[INTERNAL_STACK_SIZE];
-
-/* Due to the breakpoint return pointer, a state variable is needed to keep
- track of whether it is a static (compiled) or dynamic (gdb-invoked)
- breakpoint to be handled. A static breakpoint uses the content of register
- BRP as it is whereas a dynamic breakpoint requires subtraction with 2
- in order to execute the instruction. The first breakpoint is static. */
-static unsigned char __used is_dyn_brkp;
-
-/********************************* String library ****************************/
-/* Single-step over library functions creates trap loops. */
-
-/* Copy char s2[] to s1[]. */
-static char*
-gdb_cris_strcpy (char *s1, const char *s2)
-{
- char *s = s1;
-
- for (s = s1; (*s++ = *s2++) != '\0'; )
- ;
- return (s1);
-}
-
-/* Find length of s[]. */
-static int
-gdb_cris_strlen (const char *s)
-{
- const char *sc;
-
- for (sc = s; *sc != '\0'; sc++)
- ;
- return (sc - s);
-}
-
-/* Find first occurrence of c in s[n]. */
-static void*
-gdb_cris_memchr (const void *s, int c, int n)
-{
- const unsigned char uc = c;
- const unsigned char *su;
-
- for (su = s; 0 < n; ++su, --n)
- if (*su == uc)
- return ((void *)su);
- return (NULL);
-}
-/******************************* Standard library ****************************/
-/* Single-step over library functions creates trap loops. */
-/* Convert string to long. */
-static int
-gdb_cris_strtol (const char *s, char **endptr, int base)
-{
- char *s1;
- char *sd;
- int x = 0;
-
- for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
- x = x * base + (sd - hex_asc);
-
- if (endptr)
- {
- /* Unconverted suffix is stored in endptr unless endptr is NULL. */
- *endptr = s1;
- }
-
- return x;
-}
-
-/********************************** Packet I/O ******************************/
-
-/* Convert the memory, pointed to by mem into hexadecimal representation.
- Put the result in buf, and return a pointer to the last character
- in buf (null). */
-
-static char *
-mem2hex(char *buf, unsigned char *mem, int count)
-{
- int i;
- int ch;
-
- if (mem == NULL) {
- /* Bogus read from m0. FIXME: What constitutes a valid address? */
- for (i = 0; i < count; i++) {
- *buf++ = '0';
- *buf++ = '0';
- }
- } else {
- /* Valid mem address. */
- for (i = 0; i < count; i++) {
- ch = *mem++;
- buf = hex_byte_pack(buf, ch);
- }
- }
-
- /* Terminate properly. */
- *buf = '\0';
- return (buf);
-}
-
-/* Put the content of the array, in binary representation, pointed to by buf
- into memory pointed to by mem, and return a pointer to the character after
- the last byte written.
- Gdb will escape $, #, and the escape char (0x7d). */
-static unsigned char*
-bin2mem (unsigned char *mem, unsigned char *buf, int count)
-{
- int i;
- unsigned char *next;
- for (i = 0; i < count; i++) {
- /* Check for any escaped characters. Be paranoid and
- only unescape chars that should be escaped. */
- if (*buf == 0x7d) {
- next = buf + 1;
- if (*next == 0x3 || *next == 0x4 || *next == 0x5D) /* #, $, ESC */
- {
- buf++;
- *buf += 0x20;
- }
- }
- *mem++ = *buf++;
- }
- return (mem);
-}
-
-/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
- returned. */
-static void
-getpacket (char *buffer)
-{
- unsigned char checksum;
- unsigned char xmitcsum;
- int i;
- int count;
- char ch;
- do {
- while ((ch = getDebugChar ()) != '$')
- /* Wait for the start character $ and ignore all other characters */;
- checksum = 0;
- xmitcsum = -1;
- count = 0;
- /* Read until a # or the end of the buffer is reached */
- while (count < BUFMAX - 1) {
- ch = getDebugChar ();
- if (ch == '#')
- break;
- checksum = checksum + ch;
- buffer[count] = ch;
- count = count + 1;
- }
- buffer[count] = '\0';
-
- if (ch == '#') {
- xmitcsum = hex_to_bin(getDebugChar()) << 4;
- xmitcsum += hex_to_bin(getDebugChar());
- if (checksum != xmitcsum) {
- /* Wrong checksum */
- putDebugChar ('-');
- }
- else {
- /* Correct checksum */
- putDebugChar ('+');
- /* If sequence characters are received, reply with them */
- if (buffer[2] == ':') {
- putDebugChar (buffer[0]);
- putDebugChar (buffer[1]);
- /* Remove the sequence characters from the buffer */
- count = gdb_cris_strlen (buffer);
- for (i = 3; i <= count; i++)
- buffer[i - 3] = buffer[i];
- }
- }
- }
- } while (checksum != xmitcsum);
-}
-
-/* Send $<data>#<checksum> from the <data> in the array buffer. */
-
-static void
-putpacket(char *buffer)
-{
- int checksum;
- int runlen;
- int encode;
-
- do {
- char *src = buffer;
- putDebugChar ('$');
- checksum = 0;
- while (*src) {
- /* Do run length encoding */
- putDebugChar (*src);
- checksum += *src;
- runlen = 0;
- while (runlen < RUNLENMAX && *src == src[runlen]) {
- runlen++;
- }
- if (runlen > 3) {
- /* Got a useful amount */
- putDebugChar ('*');
- checksum += '*';
- encode = runlen + ' ' - 4;
- putDebugChar (encode);
- checksum += encode;
- src += runlen;
- }
- else {
- src++;
- }
- }
- putDebugChar('#');
- putDebugChar(hex_asc_hi(checksum));
- putDebugChar(hex_asc_lo(checksum));
- } while(kgdb_started && (getDebugChar() != '+'));
-}
-
-/* The string str is prepended with the GDB printout token and sent. Required
- in traditional implementations. */
-void
-putDebugString (const unsigned char *str, int length)
-{
- remcomOutBuffer[0] = 'O';
- mem2hex(&remcomOutBuffer[1], (unsigned char *)str, length);
- putpacket(remcomOutBuffer);
-}
-
-/********************************* Register image ****************************/
-/* Write a value to a specified register in the register image of the current
- thread. Returns status code SUCCESS, E02, E05 or E08. */
-static int
-write_register (int regno, char *val)
-{
- int status = SUCCESS;
- registers *current_reg = &cris_reg;
-
- if (regno >= R0 && regno <= PC) {
- /* 32-bit register with simple offset. */
- if (hex2bin((unsigned char *)current_reg + regno * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
- }
- else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
- /* Do not support read-only registers. */
- status = E02;
- }
- else if (regno == CCR) {
- /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented,
- and P7 (MOF) is 32 bits in ETRAX 100LX. */
- if (hex2bin((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
- val, sizeof(unsigned short)))
- status = E08;
- }
- else if (regno >= MOF && regno <= USP) {
- /* 32 bit register with complex offset. (P8 has been taken care of.) */
- if (hex2bin((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
- }
- else {
- /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
- status = E05;
- }
- return status;
-}
-
-/* Read a value from a specified register in the register image. Returns the
- value in the register or -1 for non-implemented registers.
- Should check consistency_status after a call which may be E05 after changes
- in the implementation. */
-static int
-read_register (char regno, unsigned int *valptr)
-{
- registers *current_reg = &cris_reg;
-
- if (regno >= R0 && regno <= PC) {
- /* 32-bit register with simple offset. */
- *valptr = *(unsigned int *)((char *)current_reg + regno * sizeof(unsigned int));
- return SUCCESS;
- }
- else if (regno == P0 || regno == VR) {
- /* 8 bit register with complex offset. */
- *valptr = (unsigned int)(*(unsigned char *)
- ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char)));
- return SUCCESS;
- }
- else if (regno == P4 || regno == CCR) {
- /* 16 bit register with complex offset. */
- *valptr = (unsigned int)(*(unsigned short *)
- ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short)));
- return SUCCESS;
- }
- else if (regno >= MOF && regno <= USP) {
- /* 32 bit register with complex offset. */
- *valptr = *(unsigned int *)((char *)&(current_reg->p8)
- + (regno-P8) * sizeof(unsigned int));
- return SUCCESS;
- }
- else {
- /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
- consistency_status = E05;
- return E05;
- }
-}
-
-/********************************** Handle exceptions ************************/
-/* Build and send a response packet in order to inform the host the
- stub is stopped. TAAn...:r...;n...:r...;n...:r...;
- AA = signal number
- n... = register number (hex)
- r... = register contents
- n... = `thread'
- r... = thread process ID. This is a hex integer.
- n... = other string not starting with valid hex digit.
- gdb should ignore this n,r pair and go on to the next.
- This way we can extend the protocol. */
-static void
-stub_is_stopped(int sigval)
-{
- char *ptr = remcomOutBuffer;
- int regno;
-
- unsigned int reg_cont;
- int status;
-
- /* Send trap type (converted to signal) */
-
- *ptr++ = 'T';
- ptr = hex_byte_pack(ptr, sigval);
-
- /* Send register contents. We probably only need to send the
- * PC, frame pointer and stack pointer here. Other registers will be
- * explicitly asked for. But for now, send all.
- */
-
- for (regno = R0; regno <= USP; regno++) {
- /* Store n...:r...; for the registers in the buffer. */
-
- status = read_register (regno, &reg_cont);
-
- if (status == SUCCESS) {
- ptr = hex_byte_pack(ptr, regno);
- *ptr++ = ':';
-
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont,
- register_size[regno]);
- *ptr++ = ';';
- }
-
- }
-
- /* null-terminate and send it off */
-
- *ptr = 0;
-
- putpacket (remcomOutBuffer);
-}
-
-/* Performs a complete re-start from scratch. */
-static void
-kill_restart (void)
-{
- machine_restart("");
-}
-
-/* All expected commands are sent from remote.c. Send a response according
- to the description in remote.c. */
-void
-handle_exception (int sigval)
-{
- /* Send response. */
-
- stub_is_stopped (sigval);
-
- for (;;) {
- remcomOutBuffer[0] = '\0';
- getpacket (remcomInBuffer);
- switch (remcomInBuffer[0]) {
- case 'g':
- /* Read registers: g
- Success: Each byte of register data is described by two hex digits.
- Registers are in the internal order for GDB, and the bytes
- in a register are in the same order the machine uses.
- Failure: void. */
-
- mem2hex(remcomOutBuffer, (char *)&cris_reg, sizeof(registers));
- break;
-
- case 'G':
- /* Write registers. GXX..XX
- Each byte of register data is described by two hex digits.
- Success: OK
- Failure: E08. */
- if (hex2bin((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers)))
- gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
- else
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- break;
-
- case 'P':
- /* Write register. Pn...=r...
- Write register n..., hex value without 0x, with value r...,
- which contains a hex value without 0x and two hex digits
- for each byte in the register (target byte order). P1f=11223344 means
- set register 31 to 44332211.
- Success: OK
- Failure: E02, E05, E08 */
- {
- char *suffix;
- int regno = gdb_cris_strtol (&remcomInBuffer[1], &suffix, 16);
- int status;
- status = write_register (regno, suffix+1);
-
- switch (status) {
- case E02:
- /* Do not support read-only registers. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E02]);
- break;
- case E05:
- /* Do not support non-existing registers. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E05]);
- break;
- case E07:
- /* Do not support non-existing registers on the stack. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E07]);
- break;
- case E08:
- /* Invalid parameter. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
- break;
- default:
- /* Valid register number. */
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- break;
- }
- }
- break;
-
- case 'm':
- /* Read from memory. mAA..AA,LLLL
- AA..AA is the address and LLLL is the length.
- Success: XX..XX is the memory content. Can be fewer bytes than
- requested if only part of the data may be read. m6000120a,6c means
- retrieve 108 byte from base address 6000120a.
- Failure: void. */
- {
- char *suffix;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1],
- &suffix, 16); int length = gdb_cris_strtol(suffix+1, 0, 16);
-
- mem2hex(remcomOutBuffer, addr, length);
- }
- break;
-
- case 'X':
- /* Write to memory. XAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the binary data.
- Success: OK
- Failure: void. */
- case 'M':
- /* Write to memory. MAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the hexadecimal data.
- Success: OK
- Failure: E08. */
- {
- char *lenptr;
- char *dataptr;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&remcomInBuffer[1],
- &lenptr, 16);
- int length = gdb_cris_strtol(lenptr+1, &dataptr, 16);
- if (*lenptr == ',' && *dataptr == ':') {
- if (remcomInBuffer[0] == 'M') {
- if (hex2bin(addr, dataptr + 1, length))
- gdb_cris_strcpy (remcomOutBuffer, error_message[E08]);
- else
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- } else /* X */ {
- bin2mem(addr, dataptr + 1, length);
- gdb_cris_strcpy (remcomOutBuffer, "OK");
- }
- } else {
- gdb_cris_strcpy (remcomOutBuffer, error_message[E06]);
- }
- }
- break;
-
- case 'c':
- /* Continue execution. cAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address.
- Success: return to the executing thread.
- Failure: will never know. */
- if (remcomInBuffer[1] != '\0') {
- cris_reg.pc = gdb_cris_strtol (&remcomInBuffer[1], 0, 16);
- }
- enableDebugIRQ();
- return;
-
- case 's':
- /* Step. sAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address. Success: return to the
- executing thread. Failure: will never know.
-
- Should never be invoked. The single-step is implemented on
- the host side. If ever invoked, it is an internal error E04. */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E04]);
- putpacket (remcomOutBuffer);
- return;
-
- case '?':
- /* The last signal which caused a stop. ?
- Success: SAA, where AA is the signal number.
- Failure: void. */
- remcomOutBuffer[0] = 'S';
- remcomOutBuffer[1] = hex_asc_hi(sigval);
- remcomOutBuffer[2] = hex_asc_lo(sigval);
- remcomOutBuffer[3] = 0;
- break;
-
- case 'D':
- /* Detach from host. D
- Success: OK, and return to the executing thread.
- Failure: will never know */
- putpacket ("OK");
- return;
-
- case 'k':
- case 'r':
- /* kill request or reset request.
- Success: restart of target.
- Failure: will never know. */
- kill_restart ();
- break;
-
- case 'C':
- case 'S':
- case '!':
- case 'R':
- case 'd':
- /* Continue with signal sig. Csig;AA..AA
- Step with signal sig. Ssig;AA..AA
- Use the extended remote protocol. !
- Restart the target system. R0
- Toggle debug flag. d
- Search backwards. tAA:PP,MM
- Not supported: E04 */
- gdb_cris_strcpy (remcomOutBuffer, error_message[E04]);
- break;
-
- default:
- /* The stub should ignore other request and send an empty
- response ($#<checksum>). This way we can extend the protocol and GDB
- can tell whether the stub it is talking to uses the old or the new. */
- remcomOutBuffer[0] = 0;
- break;
- }
- putpacket(remcomOutBuffer);
- }
-}
-
-/********************************** Breakpoint *******************************/
-/* The hook for both a static (compiled) and a dynamic breakpoint set by GDB.
- An internal stack is used by the stub. The register image of the caller is
- stored in the structure register_image.
- Interactive communication with the host is handled by handle_exception and
- finally the register image is restored. */
-
-void kgdb_handle_breakpoint(void);
-
-asm ("\n"
-" .global kgdb_handle_breakpoint\n"
-"kgdb_handle_breakpoint:\n"
-";;\n"
-";; Response to the break-instruction\n"
-";;\n"
-";; Create a register image of the caller\n"
-";;\n"
-" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR before disable interrupts\n"
-" di ; Disable interrupts\n"
-" move.d $r0,[cris_reg] ; Save R0\n"
-" move.d $r1,[cris_reg+0x04] ; Save R1\n"
-" move.d $r2,[cris_reg+0x08] ; Save R2\n"
-" move.d $r3,[cris_reg+0x0C] ; Save R3\n"
-" move.d $r4,[cris_reg+0x10] ; Save R4\n"
-" move.d $r5,[cris_reg+0x14] ; Save R5\n"
-" move.d $r6,[cris_reg+0x18] ; Save R6\n"
-" move.d $r7,[cris_reg+0x1C] ; Save R7\n"
-" move.d $r8,[cris_reg+0x20] ; Save R8\n"
-" move.d $r9,[cris_reg+0x24] ; Save R9\n"
-" move.d $r10,[cris_reg+0x28] ; Save R10\n"
-" move.d $r11,[cris_reg+0x2C] ; Save R11\n"
-" move.d $r12,[cris_reg+0x30] ; Save R12\n"
-" move.d $r13,[cris_reg+0x34] ; Save R13\n"
-" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n"
-";; Due to the old assembler-versions BRP might not be recognized\n"
-" .word 0xE670 ; move brp,$r0\n"
-" subq 2,$r0 ; Set to address of previous instruction.\n"
-" move.d $r0,[cris_reg+0x3c] ; Save the address in PC (R15)\n"
-" clear.b [cris_reg+0x40] ; Clear P0\n"
-" move $vr,[cris_reg+0x41] ; Save special register P1\n"
-" clear.w [cris_reg+0x42] ; Clear P4\n"
-" move $ccr,[cris_reg+0x44] ; Save special register CCR\n"
-" move $mof,[cris_reg+0x46] ; P7\n"
-" clear.d [cris_reg+0x4A] ; Clear P8\n"
-" move $ibr,[cris_reg+0x4E] ; P9,\n"
-" move $irp,[cris_reg+0x52] ; P10,\n"
-" move $srp,[cris_reg+0x56] ; P11,\n"
-" move $bar,[cris_reg+0x5A] ; P12,\n"
-" ; P13, register DCCR already saved\n"
-";; Due to the old assembler-versions BRP might not be recognized\n"
-" .word 0xE670 ; move brp,r0\n"
-";; Static (compiled) breakpoints must return to the next instruction in order\n"
-";; to avoid infinite loops. Dynamic (gdb-invoked) must restore the instruction\n"
-";; in order to execute it when execution is continued.\n"
-" test.b [is_dyn_brkp] ; Is this a dynamic breakpoint?\n"
-" beq is_static ; No, a static breakpoint\n"
-" nop\n"
-" subq 2,$r0 ; rerun the instruction the break replaced\n"
-"is_static:\n"
-" moveq 1,$r1\n"
-" move.b $r1,[is_dyn_brkp] ; Set the state variable to dynamic breakpoint\n"
-" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n"
-" move $usp,[cris_reg+0x66] ; USP\n"
-";;\n"
-";; Handle the communication\n"
-";;\n"
-" move.d internal_stack+1020,$sp ; Use the internal stack which grows upward\n"
-" moveq 5,$r10 ; SIGTRAP\n"
-" jsr handle_exception ; Interactive routine\n"
-";;\n"
-";; Return to the caller\n"
-";;\n"
-" move.d [cris_reg],$r0 ; Restore R0\n"
-" move.d [cris_reg+0x04],$r1 ; Restore R1\n"
-" move.d [cris_reg+0x08],$r2 ; Restore R2\n"
-" move.d [cris_reg+0x0C],$r3 ; Restore R3\n"
-" move.d [cris_reg+0x10],$r4 ; Restore R4\n"
-" move.d [cris_reg+0x14],$r5 ; Restore R5\n"
-" move.d [cris_reg+0x18],$r6 ; Restore R6\n"
-" move.d [cris_reg+0x1C],$r7 ; Restore R7\n"
-" move.d [cris_reg+0x20],$r8 ; Restore R8\n"
-" move.d [cris_reg+0x24],$r9 ; Restore R9\n"
-" move.d [cris_reg+0x28],$r10 ; Restore R10\n"
-" move.d [cris_reg+0x2C],$r11 ; Restore R11\n"
-" move.d [cris_reg+0x30],$r12 ; Restore R12\n"
-" move.d [cris_reg+0x34],$r13 ; Restore R13\n"
-";;\n"
-";; FIXME: Which registers should be restored?\n"
-";;\n"
-" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n"
-" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n"
-" move [cris_reg+0x5E],$dccr ; Restore DCCR\n"
-" move [cris_reg+0x66],$usp ; Restore USP\n"
-" jump [cris_reg+0x62] ; A jump to the content in register BRP works.\n"
-" nop ;\n"
-"\n");
-
-/* The hook for an interrupt generated by GDB. An internal stack is used
- by the stub. The register image of the caller is stored in the structure
- register_image. Interactive communication with the host is handled by
- handle_exception and finally the register image is restored. Due to the
- old assembler which does not recognise the break instruction and the
- breakpoint return pointer hex-code is used. */
-
-void kgdb_handle_serial(void);
-
-asm ("\n"
-" .global kgdb_handle_serial\n"
-"kgdb_handle_serial:\n"
-";;\n"
-";; Response to a serial interrupt\n"
-";;\n"
-"\n"
-" move $dccr,[cris_reg+0x5E] ; Save the flags in DCCR\n"
-" di ; Disable interrupts\n"
-" move.d $r0,[cris_reg] ; Save R0\n"
-" move.d $r1,[cris_reg+0x04] ; Save R1\n"
-" move.d $r2,[cris_reg+0x08] ; Save R2\n"
-" move.d $r3,[cris_reg+0x0C] ; Save R3\n"
-" move.d $r4,[cris_reg+0x10] ; Save R4\n"
-" move.d $r5,[cris_reg+0x14] ; Save R5\n"
-" move.d $r6,[cris_reg+0x18] ; Save R6\n"
-" move.d $r7,[cris_reg+0x1C] ; Save R7\n"
-" move.d $r8,[cris_reg+0x20] ; Save R8\n"
-" move.d $r9,[cris_reg+0x24] ; Save R9\n"
-" move.d $r10,[cris_reg+0x28] ; Save R10\n"
-" move.d $r11,[cris_reg+0x2C] ; Save R11\n"
-" move.d $r12,[cris_reg+0x30] ; Save R12\n"
-" move.d $r13,[cris_reg+0x34] ; Save R13\n"
-" move.d $sp,[cris_reg+0x38] ; Save SP (R14)\n"
-" move $irp,[cris_reg+0x3c] ; Save the address in PC (R15)\n"
-" clear.b [cris_reg+0x40] ; Clear P0\n"
-" move $vr,[cris_reg+0x41] ; Save special register P1,\n"
-" clear.w [cris_reg+0x42] ; Clear P4\n"
-" move $ccr,[cris_reg+0x44] ; Save special register CCR\n"
-" move $mof,[cris_reg+0x46] ; P7\n"
-" clear.d [cris_reg+0x4A] ; Clear P8\n"
-" move $ibr,[cris_reg+0x4E] ; P9,\n"
-" move $irp,[cris_reg+0x52] ; P10,\n"
-" move $srp,[cris_reg+0x56] ; P11,\n"
-" move $bar,[cris_reg+0x5A] ; P12,\n"
-" ; P13, register DCCR already saved\n"
-";; Due to the old assembler-versions BRP might not be recognized\n"
-" .word 0xE670 ; move brp,r0\n"
-" move.d $r0,[cris_reg+0x62] ; Save the return address in BRP\n"
-" move $usp,[cris_reg+0x66] ; USP\n"
-"\n"
-";; get the serial character (from debugport.c) and check if it is a ctrl-c\n"
-"\n"
-" jsr getDebugChar\n"
-" cmp.b 3, $r10\n"
-" bne goback\n"
-" nop\n"
-"\n"
-" move.d [cris_reg+0x5E], $r10 ; Get DCCR\n"
-" btstq 8, $r10 ; Test the U-flag.\n"
-" bmi goback\n"
-" nop\n"
-"\n"
-";;\n"
-";; Handle the communication\n"
-";;\n"
-" move.d internal_stack+1020,$sp ; Use the internal stack\n"
-" moveq 2,$r10 ; SIGINT\n"
-" jsr handle_exception ; Interactive routine\n"
-"\n"
-"goback:\n"
-";;\n"
-";; Return to the caller\n"
-";;\n"
-" move.d [cris_reg],$r0 ; Restore R0\n"
-" move.d [cris_reg+0x04],$r1 ; Restore R1\n"
-" move.d [cris_reg+0x08],$r2 ; Restore R2\n"
-" move.d [cris_reg+0x0C],$r3 ; Restore R3\n"
-" move.d [cris_reg+0x10],$r4 ; Restore R4\n"
-" move.d [cris_reg+0x14],$r5 ; Restore R5\n"
-" move.d [cris_reg+0x18],$r6 ; Restore R6\n"
-" move.d [cris_reg+0x1C],$r7 ; Restore R7\n"
-" move.d [cris_reg+0x20],$r8 ; Restore R8\n"
-" move.d [cris_reg+0x24],$r9 ; Restore R9\n"
-" move.d [cris_reg+0x28],$r10 ; Restore R10\n"
-" move.d [cris_reg+0x2C],$r11 ; Restore R11\n"
-" move.d [cris_reg+0x30],$r12 ; Restore R12\n"
-" move.d [cris_reg+0x34],$r13 ; Restore R13\n"
-";;\n"
-";; FIXME: Which registers should be restored?\n"
-";;\n"
-" move.d [cris_reg+0x38],$sp ; Restore SP (R14)\n"
-" move [cris_reg+0x56],$srp ; Restore the subroutine return pointer.\n"
-" move [cris_reg+0x5E],$dccr ; Restore DCCR\n"
-" move [cris_reg+0x66],$usp ; Restore USP\n"
-" reti ; Return from the interrupt routine\n"
-" nop\n"
-"\n");
-
-/* Use this static breakpoint in the start-up only. */
-
-void
-breakpoint(void)
-{
- kgdb_started = 1;
- is_dyn_brkp = 0; /* This is a static, not a dynamic breakpoint. */
- __asm__ volatile ("break 8"); /* Jump to handle_breakpoint. */
-}
-
-/* initialize kgdb. doesn't break into the debugger, but sets up irq and ports */
-
-void
-kgdb_init(void)
-{
- /* could initialize debug port as well but it's done in head.S already... */
-
- /* breakpoint handler is now set in irq.c */
- set_int_vector(8, kgdb_handle_serial);
-
- enableDebugIRQ();
-}
-
-/****************************** End of file **********************************/
diff --git a/arch/cris/arch-v10/kernel/process.c b/arch/cris/arch-v10/kernel/process.c
deleted file mode 100644
index 16848b2c61c8..000000000000
--- a/arch/cris/arch-v10/kernel/process.c
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/process.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 2000-2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Mikael Starvik (starvik@axis.com)
- *
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <arch/svinto.h>
-#include <linux/init.h>
-#include <arch/system.h>
-#include <linux/ptrace.h>
-
-#ifdef CONFIG_ETRAX_GPIO
-void etrax_gpio_wake_up_check(void); /* drivers/gpio.c */
-#endif
-
-/*
- * We use this if we don't have any better
- * idle routine..
- */
-void default_idle(void)
-{
-#ifdef CONFIG_ETRAX_GPIO
- etrax_gpio_wake_up_check();
-#endif
- local_irq_enable();
-}
-
-/* if the watchdog is enabled, we can simply disable interrupts and go
- * into an eternal loop, and the watchdog will reset the CPU after 0.1s
- * if on the other hand the watchdog wasn't enabled, we just enable it and wait
- */
-
-void hard_reset_now (void)
-{
- /*
- * Don't declare this variable elsewhere. We don't want any other
- * code to know about it than the watchdog handler in entry.S and
- * this code, implementing hard reset through the watchdog.
- */
-#if defined(CONFIG_ETRAX_WATCHDOG)
- extern int cause_of_death;
-#endif
-
- printk("*** HARD RESET ***\n");
- local_irq_disable();
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
- cause_of_death = 0xbedead;
-#else
- /* Since we dont plan to keep on resetting the watchdog,
- the key can be arbitrary hence three */
- *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, 3) |
- IO_STATE(R_WATCHDOG, enable, start);
-#endif
-
- while(1) /* waiting for RETRIBUTION! */ ;
-}
-
-/* setup the child's kernel stack with a pt_regs and switch_stack on it.
- * it will be un-nested during _resume and _ret_from_sys_call when the
- * new thread is scheduled.
- *
- * also setup the thread switching structure which is used to keep
- * thread-specific data during _resumes.
- *
- */
-asmlinkage void ret_from_fork(void);
-asmlinkage void ret_from_kernel_thread(void);
-
-int copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long arg, struct task_struct *p)
-{
- struct pt_regs *childregs = task_pt_regs(p);
- struct switch_stack *swstack = ((struct switch_stack *)childregs) - 1;
-
- /* put the pt_regs structure at the end of the new kernel stack page and fix it up
- * remember that the task_struct doubles as the kernel stack for the task
- */
-
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(swstack, 0,
- sizeof(struct switch_stack) + sizeof(struct pt_regs));
- swstack->r1 = usp;
- swstack->r2 = arg;
- childregs->dccr = 1 << I_DCCR_BITNR;
- swstack->return_ip = (unsigned long) ret_from_kernel_thread;
- p->thread.ksp = (unsigned long) swstack;
- p->thread.usp = 0;
- return 0;
- }
- *childregs = *current_pt_regs(); /* struct copy of pt_regs */
-
- childregs->r10 = 0; /* child returns 0 after a fork/clone */
-
- /* put the switch stack right below the pt_regs */
-
- swstack->r9 = 0; /* parameter to ret_from_sys_call, 0 == dont restart the syscall */
-
- /* we want to return into ret_from_sys_call after the _resume */
-
- swstack->return_ip = (unsigned long) ret_from_fork; /* Will call ret_from_sys_call */
-
- /* fix the user-mode stackpointer */
-
- p->thread.usp = usp ?: rdusp();
-
- /* and the kernel-mode one */
-
- p->thread.ksp = (unsigned long) swstack;
-
-#ifdef DEBUG
- printk("copy_thread: new regs at 0x%p, as shown below:\n", childregs);
- show_registers(childregs);
-#endif
-
- return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
-#if 0
- /* YURGH. TODO. */
-
- unsigned long ebp, esp, eip;
- unsigned long stack_page;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
- stack_page = (unsigned long)p;
- esp = p->thread.esp;
- if (!stack_page || esp < stack_page || esp > 8188+stack_page)
- return 0;
- /* include/asm-i386/system.h:switch_to() pushes ebp last. */
- ebp = *(unsigned long *) esp;
- do {
- if (ebp < stack_page || ebp > 8184+stack_page)
- return 0;
- eip = *(unsigned long *) (ebp+4);
- if (!in_sched_functions(eip))
- return eip;
- ebp = *(unsigned long *) ebp;
- } while (count++ < 16);
-#endif
- return 0;
-}
-#undef last_sched
-#undef first_sched
-
-void show_regs(struct pt_regs * regs)
-{
- unsigned long usp = rdusp();
-
- show_regs_print_info(KERN_DEFAULT);
-
- printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
- regs->irp, regs->srp, regs->dccr, usp, regs->mof );
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
- printk("r12: %08lx r13: %08lx oR10: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10);
-}
-
diff --git a/arch/cris/arch-v10/kernel/ptrace.c b/arch/cris/arch-v10/kernel/ptrace.c
deleted file mode 100644
index b89f57ae096e..000000000000
--- a/arch/cris/arch-v10/kernel/ptrace.c
+++ /dev/null
@@ -1,204 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2000-2003, Axis Communications AB.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/signal.h>
-#include <linux/security.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-
-/*
- * Determines which bits in DCCR the user has access to.
- * 1 = access, 0 = no access.
- */
-#define DCCR_MASK 0x0000001f /* XNZVC */
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-inline long get_reg(struct task_struct *task, unsigned int regno)
-{
- /* USP is a special case, it's not in the pt_regs struct but
- * in the tasks thread struct
- */
-
- if (regno == PT_USP)
- return task->thread.usp;
- else if (regno < PT_MAX)
- return ((unsigned long *)task_pt_regs(task))[regno];
- else
- return 0;
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-inline int put_reg(struct task_struct *task, unsigned int regno,
- unsigned long data)
-{
- if (regno == PT_USP)
- task->thread.usp = data;
- else if (regno < PT_MAX)
- ((unsigned long *)task_pt_regs(task))[regno] = data;
- else
- return -1;
- return 0;
-}
-
-/*
- * Called by kernel/ptrace.c when detaching.
- *
- * Make sure the single step bit is not set.
- */
-void
-ptrace_disable(struct task_struct *child)
-{
- /* Todo - pending singlesteps? */
- clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-}
-
-/*
- * Note that this implementation of ptrace behaves differently from vanilla
- * ptrace. Contrary to what the man page says, in the PTRACE_PEEKTEXT,
- * PTRACE_PEEKDATA, and PTRACE_PEEKUSER requests the data variable is not
- * ignored. Instead, the data variable is expected to point at a location
- * (in user space) where the result of the ptrace call is written (instead of
- * being returned).
- */
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned int regno = addr >> 2;
- unsigned long __user *datap = (unsigned long __user *)data;
-
- switch (request) {
- /* Read word at location address. */
- case PTRACE_PEEKTEXT:
- case PTRACE_PEEKDATA:
- ret = generic_ptrace_peekdata(child, addr, data);
- break;
-
- /* Read the word at location address in the USER area. */
- case PTRACE_PEEKUSR: {
- unsigned long tmp;
-
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- tmp = get_reg(child, regno);
- ret = put_user(tmp, datap);
- break;
- }
-
- /* Write the word at location address. */
- case PTRACE_POKETEXT:
- case PTRACE_POKEDATA:
- ret = generic_ptrace_pokedata(child, addr, data);
- break;
-
- /* Write the word at location address in the USER area. */
- case PTRACE_POKEUSR:
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- if (regno == PT_DCCR) {
- /* don't allow the tracing process to change stuff like
- * interrupt enable, kernel/user bit, dma enables etc.
- */
- data &= DCCR_MASK;
- data |= get_reg(child, PT_DCCR) & ~DCCR_MASK;
- }
- if (put_reg(child, regno, data))
- break;
- ret = 0;
- break;
-
- /* Get all GP registers from the child. */
- case PTRACE_GETREGS: {
- int i;
- unsigned long tmp;
-
- ret = 0;
- for (i = 0; i <= PT_MAX; i++) {
- tmp = get_reg(child, i);
-
- if (put_user(tmp, datap)) {
- ret = -EFAULT;
- break;
- }
-
- datap++;
- }
-
- break;
- }
-
- /* Set all GP registers in the child. */
- case PTRACE_SETREGS: {
- int i;
- unsigned long tmp;
-
- ret = 0;
- for (i = 0; i <= PT_MAX; i++) {
- if (get_user(tmp, datap)) {
- ret = -EFAULT;
- break;
- }
-
- if (i == PT_DCCR) {
- tmp &= DCCR_MASK;
- tmp |= get_reg(child, PT_DCCR) & ~DCCR_MASK;
- }
-
- put_reg(child, i, tmp);
- datap++;
- }
-
- break;
- }
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-void do_syscall_trace(void)
-{
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return;
-
- if (!(current->ptrace & PT_PTRACED))
- return;
-
- /* the 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
-
- /*
- * This isn't the same as continuing with a signal, but it will do for
- * normal use.
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
-}
diff --git a/arch/cris/arch-v10/kernel/setup.c b/arch/cris/arch-v10/kernel/setup.c
deleted file mode 100644
index 8e4fc248f96f..000000000000
--- a/arch/cris/arch-v10/kernel/setup.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- *
- * linux/arch/cris/arch-v10/kernel/setup.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (c) 2001-2002 Axis Communications AB
- */
-
-/*
- * This file handles the architecture-dependent parts of initialization
- */
-
-#include <linux/seq_file.h>
-#include <linux/proc_fs.h>
-#include <linux/delay.h>
-#include <linux/param.h>
-#include <arch/system.h>
-
-#ifdef CONFIG_PROC_FS
-#define HAS_FPU 0x0001
-#define HAS_MMU 0x0002
-#define HAS_ETHERNET100 0x0004
-#define HAS_TOKENRING 0x0008
-#define HAS_SCSI 0x0010
-#define HAS_ATA 0x0020
-#define HAS_USB 0x0040
-#define HAS_IRQ_BUG 0x0080
-#define HAS_MMU_BUG 0x0100
-
-static struct cpu_info {
- char *model;
- unsigned short cache;
- unsigned short flags;
-} cpu_info[] = {
- /* The first four models will never ever run this code and are
- only here for display. */
- { "ETRAX 1", 0, 0 },
- { "ETRAX 2", 0, 0 },
- { "ETRAX 3", 0, HAS_TOKENRING },
- { "ETRAX 4", 0, HAS_TOKENRING | HAS_SCSI },
- { "Unknown", 0, 0 },
- { "Unknown", 0, 0 },
- { "Unknown", 0, 0 },
- { "Simulator", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA },
- { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG },
- { "ETRAX 100", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA },
- { "ETRAX 100LX", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU | HAS_MMU_BUG },
- { "ETRAX 100LX v2", 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB | HAS_MMU },
- { "Unknown", 0, 0 } /* This entry MUST be the last */
-};
-
-int show_cpuinfo(struct seq_file *m, void *v)
-{
- unsigned long revision;
- struct cpu_info *info;
-
- /* read the version register in the CPU and print some stuff */
-
- revision = rdvr();
-
- if (revision >= ARRAY_SIZE(cpu_info))
- info = &cpu_info[ARRAY_SIZE(cpu_info) - 1];
- else
- info = &cpu_info[revision];
-
- seq_printf(m,
- "processor\t: 0\n"
- "cpu\t\t: CRIS\n"
- "cpu revision\t: %lu\n"
- "cpu model\t: %s\n"
- "cache size\t: %d kB\n"
- "fpu\t\t: %s\n"
- "mmu\t\t: %s\n"
- "mmu DMA bug\t: %s\n"
- "ethernet\t: %s Mbps\n"
- "token ring\t: %s\n"
- "scsi\t\t: %s\n"
- "ata\t\t: %s\n"
- "usb\t\t: %s\n"
- "bogomips\t: %lu.%02lu\n",
-
- revision,
- info->model,
- info->cache,
- info->flags & HAS_FPU ? "yes" : "no",
- info->flags & HAS_MMU ? "yes" : "no",
- info->flags & HAS_MMU_BUG ? "yes" : "no",
- info->flags & HAS_ETHERNET100 ? "10/100" : "10",
- info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no",
- info->flags & HAS_SCSI ? "yes" : "no",
- info->flags & HAS_ATA ? "yes" : "no",
- info->flags & HAS_USB ? "yes" : "no",
- (loops_per_jiffy * HZ + 500) / 500000,
- ((loops_per_jiffy * HZ + 500) / 5000) % 100);
-
- return 0;
-}
-
-#endif /* CONFIG_PROC_FS */
-
-void
-show_etrax_copyright(void)
-{
- printk(KERN_INFO
- "Linux/CRIS port on ETRAX 100LX (c) 2001 Axis Communications AB\n");
-}
diff --git a/arch/cris/arch-v10/kernel/shadows.c b/arch/cris/arch-v10/kernel/shadows.c
deleted file mode 100644
index 2e9565e868f2..000000000000
--- a/arch/cris/arch-v10/kernel/shadows.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Various shadow registers. Defines for these are in include/asm-etrax100/io.h
- */
-
-/* Shadows for internal Etrax-registers */
-
-unsigned long genconfig_shadow;
-unsigned long gen_config_ii_shadow;
-unsigned long port_g_data_shadow;
-unsigned char port_pa_dir_shadow;
-unsigned char port_pa_data_shadow;
-unsigned char port_pb_i2c_shadow;
-unsigned char port_pb_config_shadow;
-unsigned char port_pb_dir_shadow;
-unsigned char port_pb_data_shadow;
-unsigned long r_timer_ctrl_shadow;
-
-/* Shadows for external I/O port registers.
- * These are only usable if there actually IS a latch connected
- * to the corresponding external chip-select pin.
- *
- * A common usage is that CSP0 controls LEDs and CSP4 video chips.
- */
-
-unsigned long port_cse1_shadow;
-unsigned long port_csp0_shadow;
-unsigned long port_csp4_shadow;
-
-/* Corresponding addresses for the ports.
- * These are initialized in arch/cris/mm/init.c using ioremap.
- */
-
-volatile unsigned long *port_cse1_addr;
-volatile unsigned long *port_csp0_addr;
-volatile unsigned long *port_csp4_addr;
-
diff --git a/arch/cris/arch-v10/kernel/signal.c b/arch/cris/arch-v10/kernel/signal.c
deleted file mode 100644
index 2beffc37faf8..000000000000
--- a/arch/cris/arch-v10/kernel/signal.c
+++ /dev/null
@@ -1,440 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/signal.c
- *
- * Based on arch/i386/kernel/signal.c by
- * Copyright (C) 1991, 1992 Linus Torvalds
- * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson *
- *
- * Ideas also taken from arch/arm.
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-
-#include <asm/processor.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-#include <arch/system.h>
-
-#define DEBUG_SIG 0
-
-/* a syscall in Linux/CRIS is a break 13 instruction which is 2 bytes */
-/* manipulate regs so that upon return, it will be re-executed */
-
-/* We rely on that pc points to the instruction after "break 13", so the
- * library must never do strange things like putting it in a delay slot.
- */
-#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->irp -= 2;
-
-void do_signal(int canrestart, struct pt_regs *regs);
-
-/*
- * Do a signal return; undo the signal stack.
- */
-
-struct sigframe {
- struct sigcontext sc;
- unsigned long extramask[_NSIG_WORDS-1];
- unsigned char retcode[8]; /* trampoline code */
-};
-
-struct rt_sigframe {
- struct siginfo *pinfo;
- void *puc;
- struct siginfo info;
- struct ucontext uc;
- unsigned char retcode[8]; /* trampoline code */
-};
-
-
-static int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
-{
- unsigned int err = 0;
- unsigned long old_usp;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- /* restore the regs from &sc->regs (same as sc, since regs is first)
- * (sc is already checked for VERIFY_READ since the sigframe was
- * checked in sys_sigreturn previously)
- */
-
- if (__copy_from_user(regs, sc, sizeof(struct pt_regs)))
- goto badframe;
-
- /* make sure the U-flag is set so user-mode cannot fool us */
-
- regs->dccr |= 1 << 8;
-
- /* restore the old USP as it was before we stacked the sc etc.
- * (we cannot just pop the sigcontext since we aligned the sp and
- * stuff after pushing it)
- */
-
- err |= __get_user(old_usp, &sc->usp);
-
- wrusp(old_usp);
-
- /* TODO: the other ports use regs->orig_XX to disable syscall checks
- * after this completes, but we don't use that mechanism. maybe we can
- * use it now ?
- */
-
- return err;
-
-badframe:
- return 1;
-}
-
-asmlinkage int sys_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- struct sigframe __user *frame = (struct sigframe *)rdusp();
- sigset_t set;
-
- /*
- * Since we stacked the signal on a dword boundary,
- * then frame should be dword aligned here. If it's
- * not, then the user is trying to mess with us.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__get_user(set.sig[0], &frame->sc.oldmask)
- || (_NSIG_WORDS > 1
- && __copy_from_user(&set.sig[1], frame->extramask,
- sizeof(frame->extramask))))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->sc))
- goto badframe;
-
- /* TODO: SIGTRAP when single-stepping as in arm ? */
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- struct rt_sigframe __user *frame = (struct rt_sigframe *)rdusp();
- sigset_t set;
-
- /*
- * Since we stacked the signal on a dword boundary,
- * then frame should be dword aligned here. If it's
- * not, then the user is trying to mess with us.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/*
- * Set up a signal frame.
- */
-
-static int setup_sigcontext(struct sigcontext __user *sc,
- struct pt_regs *regs, unsigned long mask)
-{
- int err = 0;
- unsigned long usp = rdusp();
-
- /* copy the regs. they are first in sc so we can use sc directly */
-
- err |= __copy_to_user(sc, regs, sizeof(struct pt_regs));
-
- /* Set the frametype to CRIS_FRAME_NORMAL for the execution of
- the signal handler. The frametype will be restored to its previous
- value in restore_sigcontext. */
- regs->frametype = CRIS_FRAME_NORMAL;
-
- /* then some other stuff */
-
- err |= __put_user(mask, &sc->oldmask);
-
- err |= __put_user(usp, &sc->usp);
-
- return err;
-}
-
-/* Figure out where we want to put the new signal frame
- * - usually on the stack. */
-
-static inline void __user *
-get_sigframe(struct ksignal *ksig, size_t frame_size)
-{
- unsigned long sp = sigsp(rdusp(), ksig);
-
- /* make sure the frame is dword-aligned */
-
- sp &= ~3;
-
- return (void __user*)(sp - frame_size);
-}
-
-/* grab and setup a signal frame.
- *
- * basically we stack a lot of state info, and arrange for the
- * user-mode program to return to the kernel using either a
- * trampoline which performs the syscall sigreturn, or a provided
- * user-mode trampoline.
- */
-
-static int setup_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct sigframe __user *frame;
- unsigned long return_ip;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= setup_sigcontext(&frame->sc, regs, set->sig[0]);
- if (err)
- return -EFAULT;
-
- if (_NSIG_WORDS > 1) {
- err |= __copy_to_user(frame->extramask, &set->sig[1],
- sizeof(frame->extramask));
- }
- if (err)
- return -EFAULT;
-
- /* Set up to return from userspace. If provided, use a stub
- already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long)ksig->ka.sa.sa_restorer;
- } else {
- /* trampoline - the desired return ip is the retcode itself */
- return_ip = (unsigned long)&frame->retcode;
- /* This is movu.w __NR_sigreturn, r9; break 13; */
- err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0));
- err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2));
- err |= __put_user(0xe93d, (short __user*)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
-
- regs->irp = (unsigned long) ksig->ka.sa.sa_handler; /* what we enter NOW */
- regs->srp = return_ip; /* what we enter LATER */
- regs->r10 = ksig->sig; /* first argument is signo */
-
- /* actually move the usp to reflect the stacked frame */
-
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct rt_sigframe __user *frame;
- unsigned long return_ip;
- int err = 0;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
- if (err)
- return -EFAULT;
-
- /* Clear all the bits of the ucontext we don't use. */
- err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
-
- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
-
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
-
- if (err)
- return -EFAULT;
-
- /* Set up to return from userspace. If provided, use a stub
- already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long)ksig->ka.sa.sa_restorer;
- } else {
- /* trampoline - the desired return ip is the retcode itself */
- return_ip = (unsigned long)&frame->retcode;
- /* This is movu.w __NR_rt_sigreturn, r9; break 13; */
- err |= __put_user(0x9c5f, (short __user *)(frame->retcode+0));
- err |= __put_user(__NR_rt_sigreturn,
- (short __user *)(frame->retcode+2));
- err |= __put_user(0xe93d, (short __user *)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
-
- /* What we enter NOW */
- regs->irp = (unsigned long) ksig->ka.sa.sa_handler;
- /* What we enter LATER */
- regs->srp = return_ip;
- /* First argument is signo */
- regs->r10 = ksig->sig;
- /* Second argument is (siginfo_t *) */
- regs->r11 = (unsigned long)&frame->info;
- /* Third argument is unused */
- regs->r12 = 0;
-
- /* Actually move the usp to reflect the stacked frame */
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-/*
- * OK, we're invoking a handler
- */
-
-static inline void handle_signal(int canrestart, struct ksignal *ksig,
- struct pt_regs *regs)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Are we from a system call? */
- if (canrestart) {
- /* If so, check system call restarting.. */
- switch (regs->r10) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- /* ERESTARTNOHAND means that the syscall should
- * only be restarted if there was no handler for
- * the signal, and since we only get here if there
- * is a handler, we don't restart */
- regs->r10 = -EINTR;
- break;
- case -ERESTARTSYS:
- /* ERESTARTSYS means to restart the syscall if
- * there is no handler or the handler was
- * registered with SA_RESTART */
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->r10 = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- /* ERESTARTNOINTR means that the syscall should
- * be called again after the signal handler returns. */
- RESTART_CRIS_SYS(regs);
- }
- }
-
- /* Set up the stack frame */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO)
- ret = setup_rt_frame(ksig, oldset, regs);
- else
- ret = setup_frame(ksig, oldset, regs);
-
- signal_setup_done(ret, ksig, 0);
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Also note that the regs structure given here as an argument, is the latest
- * pushed pt_regs. It may or may not be the same as the first pushed registers
- * when the initial usermode->kernelmode transition took place. Therefore
- * we can use user_mode(regs) to see if we came directly from kernel or user
- * mode below.
- */
-
-void do_signal(int canrestart, struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- /*
- * We want the common case to go fast, which
- * is why we may in certain cases get here from
- * kernel mode. Just return without doing anything
- * if so.
- */
- if (!user_mode(regs))
- return;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(canrestart, &ksig, regs);
- return;
- }
-
- /* Did we come from a system call? */
- if (canrestart) {
- /* Restart the system call - no handlers present */
- if (regs->r10 == -ERESTARTNOHAND ||
- regs->r10 == -ERESTARTSYS ||
- regs->r10 == -ERESTARTNOINTR) {
- RESTART_CRIS_SYS(regs);
- }
- if (regs->r10 == -ERESTART_RESTARTBLOCK) {
- regs->r9 = __NR_restart_syscall;
- regs->irp -= 2;
- }
- }
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
diff --git a/arch/cris/arch-v10/kernel/time.c b/arch/cris/arch-v10/kernel/time.c
deleted file mode 100644
index 3d78373db254..000000000000
--- a/arch/cris/arch-v10/kernel/time.c
+++ /dev/null
@@ -1,268 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v10/kernel/time.c
- *
- * Copyright (C) 1991, 1992, 1995 Linus Torvalds
- * Copyright (C) 1999-2002 Axis Communications AB
- *
- */
-
-#include <linux/timex.h>
-#include <linux/time.h>
-#include <linux/jiffies.h>
-#include <linux/interrupt.h>
-#include <linux/swap.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <asm/types.h>
-#include <asm/signal.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq_regs.h>
-
-/* define this if you need to use print_timestamp */
-/* it will make jiffies at 96 hz instead of 100 hz though */
-#undef USE_CASCADE_TIMERS
-
-unsigned long get_ns_in_jiffie(void)
-{
- unsigned char timer_count, t1;
- unsigned short presc_count;
- unsigned long ns;
- unsigned long flags;
-
- local_irq_save(flags);
- timer_count = *R_TIMER0_DATA;
- presc_count = *R_TIM_PRESC_STATUS;
- /* presc_count might be wrapped */
- t1 = *R_TIMER0_DATA;
-
- if (timer_count != t1){
- /* it wrapped, read prescaler again... */
- presc_count = *R_TIM_PRESC_STATUS;
- timer_count = t1;
- }
- local_irq_restore(flags);
- if (presc_count >= PRESCALE_VALUE/2 ){
- presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
- } else {
- presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
- }
-
- ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
- ( (presc_count) * (1000000000/PRESCALE_FREQ));
- return ns;
-}
-
-static u32 cris_v10_gettimeoffset(void)
-{
- u32 count;
-
- /* The timer interrupt comes from Etrax timer 0. In order to get
- * better precision, we check the current value. It might have
- * underflowed already though.
- */
- count = *R_TIMER0_DATA;
-
- /* Convert timer value to nsec */
- return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV;
-}
-
-/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
- *
- * 3.10.4 Watchdog timer
-
- * When the watchdog timer is started, it generates an NMI if the watchdog
- * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
- * stopped after an additional 3.3 ms, the watchdog resets the chip.
- * The watchdog timer is stopped after reset. The watchdog timer is controlled
- * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
- * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
- * described in the table below:
- *
- * Watchdog Value written:
- * state: To enable: To key: Operation:
- * -------- ---------- ------- ----------
- * stopped 0 X No effect.
- * stopped 1 key_val Start watchdog with key = key_val.
- * started 0 ~key Stop watchdog
- * started 1 ~key Restart watchdog with key = ~key.
- * started X new_key_val Change key to new_key_val.
- *
- * Note: '~' is the bitwise NOT operator.
- *
- */
-
-/* right now, starting the watchdog is the same as resetting it */
-#define start_watchdog reset_watchdog
-
-#ifdef CONFIG_ETRAX_WATCHDOG
-static int watchdog_key = 0; /* arbitrary number */
-#endif
-
-/* number of pages to consider "out of memory". it is normal that the memory
- * is used though, so put this really low.
- */
-
-#define WATCHDOG_MIN_FREE_PAGES 8
-
-void reset_watchdog(void)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- /* only keep watchdog happy as long as we have memory left! */
- if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
- /* reset the watchdog with the inverse of the old key */
- watchdog_key ^= 0x7; /* invert key, which is 3 bits */
- *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
- IO_STATE(R_WATCHDOG, enable, start);
- }
-#endif
-}
-
-/* stop the watchdog - we still need the correct key */
-
-void stop_watchdog(void)
-{
-#ifdef CONFIG_ETRAX_WATCHDOG
- watchdog_key ^= 0x7; /* invert key, which is 3 bits */
- *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
- IO_STATE(R_WATCHDOG, enable, stop);
-#endif
-}
-
-
-extern void cris_do_profile(struct pt_regs *regs);
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
- struct pt_regs *regs = get_irq_regs();
- /* acknowledge the timer irq */
-
-#ifdef USE_CASCADE_TIMERS
- *R_TIMER_CTRL =
- IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
- IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
- IO_STATE( R_TIMER_CTRL, i1, clr) |
- IO_STATE( R_TIMER_CTRL, tm1, run) |
- IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
- IO_STATE( R_TIMER_CTRL, i0, clr) |
- IO_STATE( R_TIMER_CTRL, tm0, run) |
- IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
-#else
- *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr);
-#endif
-
- /* reset watchdog otherwise it resets us! */
- reset_watchdog();
-
- /* Update statistics. */
- update_process_times(user_mode(regs));
-
- /* call the real timer interrupt handler */
- xtime_update(1);
-
- cris_do_profile(regs); /* Save profiling information */
- return IRQ_HANDLED;
-}
-
-/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */
-
-static struct irqaction irq2 = {
- .handler = timer_interrupt,
- .flags = IRQF_SHARED,
- .name = "timer",
-};
-
-void __init time_init(void)
-{
- arch_gettimeoffset = cris_v10_gettimeoffset;
-
- /* probe for the RTC and read it if it exists
- * Before the RTC can be probed the loops_per_usec variable needs
- * to be initialized to make usleep work. A better value for
- * loops_per_usec is calculated by the kernel later once the
- * clock has started.
- */
- loops_per_usec = 50;
-
- /* Setup the etrax timers
- * Base frequency is 25000 hz, divider 250 -> 100 HZ
- * In normal mode, we use timer0, so timer1 is free. In cascade
- * mode (which we sometimes use for debugging) both timers are used.
- * Remember that linux/timex.h contains #defines that rely on the
- * timer settings below (hz and divide factor) !!!
- */
-
-#ifdef USE_CASCADE_TIMERS
- *R_TIMER_CTRL =
- IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
- IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
- IO_STATE( R_TIMER_CTRL, i1, nop) |
- IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
- IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
- IO_STATE( R_TIMER_CTRL, i0, nop) |
- IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
- IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
-
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
- IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
- IO_STATE( R_TIMER_CTRL, i1, nop) |
- IO_STATE( R_TIMER_CTRL, tm1, run) |
- IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
- IO_STATE( R_TIMER_CTRL, i0, nop) |
- IO_STATE( R_TIMER_CTRL, tm0, run) |
- IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
-#else
- *R_TIMER_CTRL =
- IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
- IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
- IO_STATE(R_TIMER_CTRL, i1, nop) |
- IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
- IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
- IO_STATE(R_TIMER_CTRL, i0, nop) |
- IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
- IO_STATE(R_TIMER_CTRL, clksel0, flexible);
-
- *R_TIMER_CTRL = r_timer_ctrl_shadow =
- IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
- IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
- IO_STATE(R_TIMER_CTRL, i1, nop) |
- IO_STATE(R_TIMER_CTRL, tm1, run) |
- IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
- IO_STATE(R_TIMER_CTRL, i0, nop) |
- IO_STATE(R_TIMER_CTRL, tm0, run) |
- IO_STATE(R_TIMER_CTRL, clksel0, flexible);
-
- *R_TIMER_PRESCALE = PRESCALE_VALUE;
-#endif
-
- /* unmask the timer irq */
- *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);
-
- /* now actually register the irq handler that calls timer_interrupt() */
- setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
-
- /* enable watchdog if we should use one */
-#if defined(CONFIG_ETRAX_WATCHDOG)
- printk("Enabling watchdog...\n");
- start_watchdog();
-
- /* If we use the hardware watchdog, we want to trap it as an NMI
- and dump registers before it resets us. For this to happen, we
- must set the "m" NMI enable flag (which once set, is unset only
- when an NMI is taken).
-
- The same goes for the external NMI, but that doesn't have any
- driver or infrastructure support yet. */
- asm ("setf m");
-
- *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
- *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
-#endif
-}
diff --git a/arch/cris/arch-v10/kernel/traps.c b/arch/cris/arch-v10/kernel/traps.c
deleted file mode 100644
index 876d45b957f4..000000000000
--- a/arch/cris/arch-v10/kernel/traps.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Helper functions for trap handlers
- *
- * Copyright (C) 2000-2007, Axis Communications AB.
- *
- * Authors: Bjorn Wesen
- * Hans-Peter Nilsson
- *
- */
-
-#include <linux/ptrace.h>
-#include <linux/uaccess.h>
-#include <linux/sched/debug.h>
-
-#include <arch/sv_addr_ag.h>
-#include <arch/system.h>
-
-void
-show_registers(struct pt_regs *regs)
-{
- /*
- * It's possible to use either the USP register or current->thread.usp.
- * USP might not correspond to the current process for all cases this
- * function is called, and current->thread.usp isn't up to date for the
- * current process. Experience shows that using USP is the way to go.
- */
- unsigned long usp = rdusp();
-
- printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
- regs->irp, regs->srp, regs->dccr, usp, regs->mof);
-
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
-
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
-
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
-
- printk("r12: %08lx r13: %08lx oR10: %08lx sp: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10, (long unsigned)regs);
-
- printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE);
-
- printk("Process %s (pid: %d, stackpage=%08lx)\n",
- current->comm, current->pid, (unsigned long)current);
-
- /*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (!user_mode(regs)) {
- int i;
-
- show_stack(NULL, (unsigned long *)usp);
-
- /*
- * If the previous stack-dump wasn't a kernel one, dump the
- * kernel stack now.
- */
- if (usp != 0)
- show_stack(NULL, NULL);
-
- printk("\nCode: ");
-
- if (regs->irp < PAGE_OFFSET)
- goto bad_value;
-
- /*
- * Quite often the value at regs->irp doesn't point to the
- * interesting instruction, which often is the previous
- * instruction. So dump at an offset large enough that the
- * instruction decoding should be in sync at the interesting
- * point, but small enough to fit on a row. The regs->irp
- * location is pointed out in a ksymoops-friendly way by
- * wrapping the byte for that address in parenthesises.
- */
- for (i = -12; i < 12; i++) {
- unsigned char c;
-
- if (__get_user(c, &((unsigned char *)regs->irp)[i])) {
-bad_value:
- printk(" Bad IP value.");
- break;
- }
-
- if (i == 0)
- printk("(%02x) ", c);
- else
- printk("%02x ", c);
- }
- printk("\n");
- }
-}
-
-void
-arch_enable_nmi(void)
-{
- asm volatile ("setf m");
-}
-
-extern void (*nmi_handler)(struct pt_regs *);
-void handle_nmi(struct pt_regs *regs)
-{
- if (nmi_handler)
- nmi_handler(regs);
-
- /* Wait until nmi is no longer active. (We enable NMI immediately after
- returning from this function, and we don't want it happening while
- exiting from the NMI interrupt handler.) */
- while (*R_IRQ_MASK0_RD & IO_STATE(R_IRQ_MASK0_RD, nmi_pin, active))
- ;
-}
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-void
-handle_BUG(struct pt_regs *regs)
-{
- struct bug_frame f;
- unsigned char c;
- unsigned long irp = regs->irp;
-
- if (__copy_from_user(&f, (const void __user *)(irp - 8), sizeof f))
- return;
- if (f.prefix != BUG_PREFIX || f.magic != BUG_MAGIC)
- return;
- if (__get_user(c, f.filename))
- f.filename = "<bad filename>";
-
- printk("kernel BUG at %s:%d!\n", f.filename, f.line);
-}
-#endif
diff --git a/arch/cris/arch-v10/lib/Makefile b/arch/cris/arch-v10/lib/Makefile
deleted file mode 100644
index 725153edb764..000000000000
--- a/arch/cris/arch-v10/lib/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for Etrax-specific library files..
-#
-
-lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o csumcpfruser.o
-
diff --git a/arch/cris/arch-v10/lib/checksum.S b/arch/cris/arch-v10/lib/checksum.S
deleted file mode 100644
index a3b96391706f..000000000000
--- a/arch/cris/arch-v10/lib/checksum.S
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum routine using movem
- * Copyright (c) 1998-2001 Axis Communications AB
- *
- * csum_partial(const unsigned char * buff, int len, unsigned int sum)
- */
-
- .globl csum_partial
-csum_partial:
-
- ;; r10 - src
- ;; r11 - length
- ;; r12 - checksum
-
- ;; check for breakeven length between movem and normal word looping versions
- ;; we also do _NOT_ want to compute a checksum over more than the
- ;; actual length when length < 40
-
- cmpu.w 80,$r11
- blo _word_loop
- nop
-
- ;; need to save the registers we use below in the movem loop
- ;; this overhead is why we have a check above for breakeven length
- ;; only r0 - r8 have to be saved, the other ones are clobber-able
- ;; according to the ABI
-
- subq 9*4,$sp
- movem $r8,[$sp]
-
- ;; do a movem checksum
-
- subq 10*4,$r11 ; update length for the first loop
-
-_mloop: movem [$r10+],$r9 ; read 10 longwords
-
- ;; perform dword checksumming on the 10 longwords
-
- add.d $r0,$r12
- ax
- add.d $r1,$r12
- ax
- add.d $r2,$r12
- ax
- add.d $r3,$r12
- ax
- add.d $r4,$r12
- ax
- add.d $r5,$r12
- ax
- add.d $r6,$r12
- ax
- add.d $r7,$r12
- ax
- add.d $r8,$r12
- ax
- add.d $r9,$r12
-
- ;; fold the carry into the checksum, to avoid having to loop the carry
- ;; back into the top
-
- ax
- addq 0,$r12
-
- subq 10*4,$r11
- bge _mloop
- nop
-
- addq 10*4,$r11 ; compensate for last loop underflowing length
-
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- ;; only fold if there is anything to fold.
-
- cmpq 0,$r12
- beq _no_fold
-
- ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below.
- ;; r9 and r13 can be used as temporaries.
-
- moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9
- lsrq 16,$r9
-
- move.d $r12,$r13
- lsrq 16,$r13 ; r13 = checksum >> 16
- and.d $r9,$r12 ; checksum = checksum & 0xffff
- add.d $r13,$r12 ; checksum += r13
-
-_no_fold:
- cmpq 2,$r11
- blt _no_words
- nop
-
- ;; checksum the rest of the words
-
- subq 2,$r11
-
-_wloop: subq 2,$r11
- bge _wloop
- addu.w [$r10+],$r12
-
- addq 2,$r11
-
-_no_words:
- ;; see if we have one odd byte more
- cmpq 1,$r11
- beq _do_byte
- nop
- ret
- move.d $r12, $r10
-
-_do_byte:
- ;; copy and checksum the last byte
- addu.b [$r10],$r12
- ret
- move.d $r12, $r10
-
diff --git a/arch/cris/arch-v10/lib/checksumcopy.S b/arch/cris/arch-v10/lib/checksumcopy.S
deleted file mode 100644
index b21449cb1ad3..000000000000
--- a/arch/cris/arch-v10/lib/checksumcopy.S
+++ /dev/null
@@ -1,127 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum+copy routine using movem
- * Copyright (c) 1998, 2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- * csum_partial_copy_nocheck(const char *src, char *dst,
- * int len, unsigned int sum)
- */
-
- .globl csum_partial_copy_nocheck
-csum_partial_copy_nocheck:
-
- ;; r10 - src
- ;; r11 - dst
- ;; r12 - length
- ;; r13 - checksum
-
- ;; check for breakeven length between movem and normal word looping versions
- ;; we also do _NOT_ want to compute a checksum over more than the
- ;; actual length when length < 40
-
- cmpu.w 80, $r12
- blo _word_loop
- nop
-
- ;; need to save the registers we use below in the movem loop
- ;; this overhead is why we have a check above for breakeven length
- ;; only r0 - r8 have to be saved, the other ones are clobber-able
- ;; according to the ABI
-
- subq 9*4, $sp
- movem $r8, [$sp]
-
- ;; do a movem copy and checksum
-
- subq 10*4, $r12 ; update length for the first loop
-
-_mloop: movem [$r10+],$r9 ; read 10 longwords
-1: ;; A failing userspace access will have this as PC.
- movem $r9,[$r11+] ; write 10 longwords
-
- ;; perform dword checksumming on the 10 longwords
-
- add.d $r0,$r13
- ax
- add.d $r1,$r13
- ax
- add.d $r2,$r13
- ax
- add.d $r3,$r13
- ax
- add.d $r4,$r13
- ax
- add.d $r5,$r13
- ax
- add.d $r6,$r13
- ax
- add.d $r7,$r13
- ax
- add.d $r8,$r13
- ax
- add.d $r9,$r13
-
- ;; fold the carry into the checksum, to avoid having to loop the carry
- ;; back into the top
-
- ax
- addq 0,$r13
-
- subq 10*4,$r12
- bge _mloop
- nop
-
- addq 10*4,$r12 ; compensate for last loop underflowing length
-
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- ;; only fold if there is anything to fold.
-
- cmpq 0,$r13
- beq _no_fold
-
- ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below
- ;; r9 can be used as temporary.
-
- move.d $r13,$r9
- lsrq 16,$r9 ; r0 = checksum >> 16
- and.d 0xffff,$r13 ; checksum = checksum & 0xffff
- add.d $r9,$r13 ; checksum += r0
-
-_no_fold:
- cmpq 2,$r12
- blt _no_words
- nop
-
- ;; copy and checksum the rest of the words
-
- subq 2,$r12
-
-_wloop: move.w [$r10+],$r9
-2: ;; A failing userspace access will have this as PC.
- addu.w $r9,$r13
- subq 2,$r12
- bge _wloop
- move.w $r9,[$r11+]
-
- addq 2,$r12
-
-_no_words:
- ;; see if we have one odd byte more
- cmpq 1,$r12
- beq _do_byte
- nop
- ret
- move.d $r13, $r10
-
-_do_byte:
- ;; copy and checksum the last byte
- move.b [$r10],$r9
-3: ;; A failing userspace access will have this as PC.
- addu.b $r9,$r13
- move.b $r9,[$r11]
- ret
- move.d $r13, $r10
diff --git a/arch/cris/arch-v10/lib/csumcpfruser.S b/arch/cris/arch-v10/lib/csumcpfruser.S
deleted file mode 100644
index beb8992ed478..000000000000
--- a/arch/cris/arch-v10/lib/csumcpfruser.S
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into
- * csum_partial_copy_from_user by adding exception records.
- *
- * Copyright (C) 2001 Axis Communications AB.
- *
- * Author: Hans-Peter Nilsson.
- */
-
-#include <asm/errno.h>
-
-/* Same function body, but a different name. If we just added exception
- records to _csum_partial_copy_nocheck and made it generic, we wouldn't
- know a user fault from a kernel fault and we would have overhead in
- each kernel caller for the error-pointer argument.
-
- unsigned int csum_partial_copy_from_user
- (const char *src, char *dst, int len, unsigned int sum, int *errptr);
-
- Note that the errptr argument is only set if we encounter an error.
- It is conveniently located on the stack, so the normal function body
- does not have to handle it. */
-
-#define csum_partial_copy_nocheck csum_partial_copy_from_user
-
-/* There are local labels numbered 1, 2 and 3 present to mark the
- different from-user accesses. */
-#include "checksumcopy.S"
-
- .section .fixup,"ax"
-
-;; Here from the movem loop; restore stack.
-4:
- movem [$sp+],$r8
-;; r12 is already decremented. Add back chunk_size-2.
- addq 40-2,$r12
-
-;; Here from the word loop; r12 is off by 2; add it back.
-5:
- addq 2,$r12
-
-;; Here from a failing single byte.
-6:
-
-;; Signal in *errptr that we had a failing access.
- moveq -EFAULT,$r9
- move.d $r9,[[$sp]]
-
-;; Clear the rest of the destination area using memset. Preserve the
-;; checksum for the readable bytes.
- push $srp
- push $r13
- move.d $r11,$r10
- clear.d $r11
- jsr memset
- pop $r10
- jump [$sp+]
-
- .previous
- .section __ex_table,"a"
- .dword 1b,4b
- .dword 2b,5b
- .dword 3b,6b
- .previous
diff --git a/arch/cris/arch-v10/lib/dram_init.S b/arch/cris/arch-v10/lib/dram_init.S
deleted file mode 100644
index fd7437577938..000000000000
--- a/arch/cris/arch-v10/lib/dram_init.S
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DRAM/SDRAM initialization - alter with care
- * This file is intended to be included from other assembler files
- *
- * Note: This file may not modify r9 because r9 is used to carry
- * information from the decompressor to the kernel
- *
- * Copyright (C) 2000-2012 Axis Communications AB
- *
- */
-
-/* Just to be certain the config file is included, we include it here
- * explicitly instead of depending on it being included in the file that
- * uses this code.
- */
-
-
- ;; WARNING! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below.
-
- move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
- move.d $r0, [R_WAITSTATES]
-
- move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
- move.d $r0, [R_BUS_CONFIG]
-
-#ifndef CONFIG_ETRAX_SDRAM
- move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
- move.d $r0, [R_DRAM_CONFIG]
-
- move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
- move.d $r0, [R_DRAM_TIMING]
-#else
- ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
- moveq 2, $r6
-_sdram_init:
-
- ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
-
- ; Bank configuration
- move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
- move.d $r0, [R_SDRAM_CONFIG]
-
- ; Calculate value of mrs_data
- ; CAS latency = 2 && bus_width = 32 => 0x40
- ; CAS latency = 3 && bus_width = 32 => 0x60
- ; CAS latency = 2 && bus_width = 16 => 0x20
- ; CAS latency = 3 && bus_width = 16 => 0x30
-
- ; Check if value is already supplied in kernel config
- move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
- and.d 0x00ff0000, $r2
- bne _set_timing
- lsrq 16, $r2
-
- move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
- move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
- move.d $r1, $r3
- and.d 0x03, $r1 ; Get CAS latency
- and.d 0x1000, $r3 ; 50 or 100 MHz?
- beq _speed_50
- nop
-_speed_100:
- cmp.d 0x00, $r1 ; CAS latency = 2?
- beq _bw_check
- nop
- or.d 0x20, $r2 ; CAS latency = 3
- ba _bw_check
- nop
-_speed_50:
- cmp.d 0x01, $r1 ; CAS latency = 2?
- beq _bw_check
- nop
- or.d 0x20, $r2 ; CAS latency = 3
-_bw_check:
- move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
- and.d 0x800000, $r1 ; DRAM width is bit 23
- bne _set_timing
- nop
- lsrq 1, $r2 ; 16 bits. Shift down value.
-
- ; Set timing parameters. Starts master clock
-_set_timing:
- move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
- and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
- or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
- move.d $r1, $r5
- or.d 0x0000c000, $r1 ; ref = disable
- lslq 16, $r2 ; mrs data starts at bit 16
- or.d $r2, $r1
- move.d $r1, [R_SDRAM_TIMING]
-
- ; Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Issue initialization command sequence
- move.d _sdram_commands_start, $r2
- and.d 0x000fffff, $r2 ; Make sure commands are read from flash
- move.d _sdram_commands_end, $r3
- and.d 0x000fffff, $r3
-1: clear.d $r4
- move.b [$r2+], $r4
- lslq 9, $r4 ; Command starts at bit 9
- or.d $r1, $r4
- move.d $r4, [R_SDRAM_TIMING]
- nop ; Wait five nop cycles between each command
- nop
- nop
- nop
- nop
- cmp.d $r2, $r3
- bne 1b
- nop
- move.d $r5, [R_SDRAM_TIMING]
- subq 1, $r6
- bne _sdram_init
- nop
- ba _sdram_commands_end
- nop
-
-_sdram_commands_start:
- .byte 3 ; Precharge
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 2 ; refresh
- .byte 0 ; nop
- .byte 1 ; mrs
- .byte 0 ; nop
-_sdram_commands_end:
-#endif
diff --git a/arch/cris/arch-v10/lib/hw_settings.S b/arch/cris/arch-v10/lib/hw_settings.S
deleted file mode 100644
index 0d449852517e..000000000000
--- a/arch/cris/arch-v10/lib/hw_settings.S
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This table is used by some tools to extract hardware parameters.
- * The table should be included in the kernel and the decompressor.
- * Don't forget to update the tools if you change this table.
- *
- * Copyright (C) 2001 Axis Communications AB
- *
- * Authors: Mikael Starvik (starvik@axis.com)
- */
-
-#define PA_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PA_DIR << 8) | \
- (CONFIG_ETRAX_DEF_R_PORT_PA_DATA))
-#define PB_SET_VALUE ((CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG << 16) | \
- (CONFIG_ETRAX_DEF_R_PORT_PB_DIR << 8) | \
- (CONFIG_ETRAX_DEF_R_PORT_PB_DATA))
-
- .ascii "HW_PARAM_MAGIC" ; Magic number
- .dword 0xc0004000 ; Kernel start address
-
- ; Debug port
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- .dword 0
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- .dword 1
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- .dword 2
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- .dword 3
-#else
- .dword 4 ; No debug
-#endif
-
- ; SDRAM or EDO DRAM?
-#ifdef CONFIG_ETRAX_SDRAM
- .dword 1
-#else
- .dword 0
-#endif
-
- ; Register values
- .dword R_WAITSTATES
- .dword CONFIG_ETRAX_DEF_R_WAITSTATES
- .dword R_BUS_CONFIG
- .dword CONFIG_ETRAX_DEF_R_BUS_CONFIG
-#ifdef CONFIG_ETRAX_SDRAM
- .dword R_SDRAM_CONFIG
- .dword CONFIG_ETRAX_DEF_R_SDRAM_CONFIG
- .dword R_SDRAM_TIMING
- .dword CONFIG_ETRAX_DEF_R_SDRAM_TIMING
-#else
- .dword R_DRAM_CONFIG
- .dword CONFIG_ETRAX_DEF_R_DRAM_CONFIG
- .dword R_DRAM_TIMING
- .dword CONFIG_ETRAX_DEF_R_DRAM_TIMING
-#endif
- .dword R_PORT_PA_SET
- .dword PA_SET_VALUE
- .dword R_PORT_PB_SET
- .dword PB_SET_VALUE
- .dword 0 ; No more register values
diff --git a/arch/cris/arch-v10/lib/memset.c b/arch/cris/arch-v10/lib/memset.c
deleted file mode 100644
index c94ea9b3ec29..000000000000
--- a/arch/cris/arch-v10/lib/memset.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* A memset for CRIS.
- Copyright (C) 1999-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-/* Note the multiple occurrence of the expression "12*4", including the
- asm. It is hard to get it into the asm in a good way. Thus better to
- expose the problem everywhere: no macro. */
-
-/* Assuming one cycle per dword written or read (ok, not really true; the
- world is not ideal), and one cycle per instruction, then 43+3*(n/48-1)
- <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full
- 48-byte block to set. */
-
-#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *memset(void *pdst, int c, unsigned int plen)
-{
- /* Now we want the parameters in special registers. Make sure the
- compiler does something usable with this. */
-
- register char *return_dst __asm__ ("r10") = pdst;
- register int n __asm__ ("r12") = plen;
- register int lc __asm__ ("r11") = c;
-
- /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get
- penalized here compared to the generic implementation. */
-
- /* This is fragile performancewise at best. Check with newer GCC
- releases, if they compile cascaded "x |= x << 8" to sane code. */
- __asm__("movu.b %0,r13 \n\
- lslq 8,r13 \n\
- move.b %0,r13 \n\
- move.d r13,%0 \n\
- lslq 16,r13 \n\
- or.d r13,%0"
- : "=r" (lc) /* Inputs. */
- : "0" (lc) /* Outputs. */
- : "r13"); /* Trash. */
-
- {
- register char *dst __asm__ ("r13") = pdst;
-
- if (((unsigned long) pdst & 3) != 0
- /* Oops! n = 0 must be a valid call, regardless of alignment. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- *dst = (char) lc;
- n--;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- *(short *) dst = lc;
- n -= 2;
- dst += 2;
- }
- }
-
- /* Decide which setting method to use. */
- if (n >= MEMSET_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-block sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%4,$r13-$r12-$r11 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- move.d r11,r0 \n\
- move.d r11,r1 \n\
- move.d r11,r2 \n\
- move.d r11,r3 \n\
- move.d r11,r4 \n\
- move.d r11,r5 \n\
- move.d r11,r6 \n\
- move.d r11,r7 \n\
- move.d r11,r8 \n\
- move.d r11,r9 \n\
- move.d r11,r10 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" subq 12*4,r12 \n\
- bge 0b \n\
- movem r11,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 12*4,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (n), "r" (lc));
- }
-
- /* An ad-hoc unroll, used for 4*12-1..16 bytes. */
- while (n >= 16)
- {
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = (char) lc;
- break;
-
- case 2:
- *(short *) dst = (short) lc;
- break;
-
- case 3:
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 4:
- *(long *) dst = lc;
- break;
-
- case 5:
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 6:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 7:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 8:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 9:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 10:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 11:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 12:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 13:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 14:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 15:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
- }
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v10/lib/string.c b/arch/cris/arch-v10/lib/string.c
deleted file mode 100644
index c7bd6ebdc93c..000000000000
--- a/arch/cris/arch-v10/lib/string.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* A memcpy for CRIS.
- Copyright (C) 1994-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-#include <stddef.h>
-
-/* Break even between movem and move16 is really at 38.7 * 2, but
- modulo 44, so up to the next multiple of 44, we use ordinary code. */
-#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *
-memcpy(void *pdst, const void *psrc, size_t pn)
-{
- /* Now we want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- If gcc was allright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register void *return_dst __asm__ ("r10") = pdst;
- register unsigned char *dst __asm__ ("r13") = pdst;
- register unsigned const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- n--;
- *dst = *src;
- src++;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- n -= 2;
- *(short *) dst = *(short *) src;
- src += 2;
- dst += 2;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= MEMCPY_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%2,$r13-$r11-$r12 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop. \n\
- subq 44,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" movem [r11+],r10 \n\
- subq 44,r12 \n\
- bge 0b \n\
- movem r10,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 44,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (src), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (src), "2" (n));
- }
-
- while (n >= 16)
- {
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
-
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = *src;
- break;
-
- case 2:
- *(short *) dst = *(short *) src;
- break;
-
- case 3:
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 4:
- *(long *) dst = *(long *) src;
- break;
-
- case 5:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 6:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 7:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 8:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 9:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 10:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 11:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 12:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 13:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 14:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 15:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v10/lib/usercopy.c b/arch/cris/arch-v10/lib/usercopy.c
deleted file mode 100644
index 3f1e2f4680f7..000000000000
--- a/arch/cris/arch-v10/lib/usercopy.c
+++ /dev/null
@@ -1,511 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * User address space access functions.
- * The non-inlined parts of asm-cris/uaccess.h are here.
- *
- * Copyright (C) 2000, Axis Communications AB.
- *
- * Written by Hans-Peter Nilsson.
- * Pieces used from memcpy, originally by Kenny Ranerup long time ago.
- */
-
-#include <linux/uaccess.h>
-
-/* Asm:s have been tweaked (within the domain of correctness) to give
- satisfactory results for "gcc version 2.96 20000427 (experimental)".
-
- Check regularly...
-
- Note that the PC saved at a bus-fault is the address *after* the
- faulting instruction, which means the branch-target for instructions in
- delay-slots for taken branches. Note also that the postincrement in
- the instruction is performed regardless of bus-fault; the register is
- seen updated in fault handlers.
-
- Oh, and on the code formatting issue, to whomever feels like "fixing
- it" to Conformity: I'm too "lazy", but why don't you go ahead and "fix"
- string.c too. I just don't think too many people will hack this file
- for the code format to be an issue. */
-
-
-/* Copy to userspace. This is based on the memcpy used for
- kernel-to-kernel copying; see "string.c". */
-
-unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_copy_to_user_1 (dst, src, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_copy_to_user_2 (dst, src, retn);
- n -= 2;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= 44*2) /* Break even between movem and
- move16 is at 38.7*2, but modulo 44. */
- {
- /* For large copies we use 'movem'. */
-
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- "r13=r13, r11=r11, r12=r12". */
- __asm__ volatile ("\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
- \n\
-; Since the noted PC of a faulting instruction in a delay-slot of a taken \n\
-; branch, is that of the branch target, we actually point at the from-movem \n\
-; for this case. There is no ambiguity here; if there was a fault in that \n\
-; instruction (meaning a kernel oops), the faulted PC would be the address \n\
-; after *that* movem. \n\
- \n\
-0: \n\
- movem [$r11+],$r10 \n\
- subq 44,$r12 \n\
- bge 0b \n\
- movem $r10,[$r13+] \n\
-1: \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
- \n\
-; To provide a correct count in r10 of bytes that failed to be copied, \n\
-; we jump back into the loop if the loop-branch was taken. There is no \n\
-; performance penalty for sany use; the program will segfault soon enough.\n\
- \n\
-3: \n\
- move.d [$sp],$r10 \n\
- addq 44,$r10 \n\
- move.d $r10,[$sp] \n\
- jump 0b \n\
-4: \n\
- movem [$sp+],$r10 \n\
- addq 44,$r10 \n\
- addq 44,$r12 \n\
- jump 2b \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 0b,3b \n\
- .dword 1b,4b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
-
- }
-
- /* Either we directly start copying, using dword copying in a loop, or
- we copy as much as possible with 'movem' and then the last block (<44
- bytes) is copied here. This will work since 'movem' will have
- updated SRC, DST and N. */
-
- while (n >= 16)
- {
- __asm_copy_to_user_16 (dst, src, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_copy_to_user_4 (dst, src, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_copy_to_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_to_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_to_user_3 (dst, src, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__copy_user);
-
-/* Copy from user to kernel. The return-value is the number of bytes that were
- inaccessible. */
-
-unsigned long __copy_user_in(void *pdst, const void __user *psrc,
- unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
- /* The best reason to align src is that we then know that a read-fault
- was for aligned bytes; there's no 1..3 remaining good bytes to
- pickle. */
- if (((unsigned long) src & 3) != 0)
- {
- if (((unsigned long) src & 1) && n != 0)
- {
- __asm_copy_from_user_1 (dst, src, retn);
- n--;
- if (retn)
- goto exception;
- }
-
- if (((unsigned long) src & 2) && n >= 2)
- {
- __asm_copy_from_user_2 (dst, src, retn);
- n -= 2;
- if (retn)
- goto exception;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= 44*2) /* Break even between movem and
- move16 is at 38.7*2, but modulo 44.
- FIXME: We use move4 now. */
- {
- /* For large copies we use 'movem' */
-
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- "r13=r13, r11=r11, r12=r12" */
- __asm__ volatile ("\n\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
-0: \n\
- movem [$r11+],$r10 \n\
-1: \n\
- subq 44,$r12 \n\
- bge 0b \n\
- movem $r10,[$r13+] \n\
- \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-4: \n\
- .section .fixup,\"ax\" \n\
- \n\
-;; Do not jump back into the loop if we fail. For some uses, we get a \n\
-;; page fault somewhere on the line. Without checking for page limits, \n\
-;; we don't know where, but we need to copy accurately and keep an \n\
-;; accurate count; not just clear the whole line. To do that, we fall \n\
-;; down in the code below, proceeding with smaller amounts. It should \n\
-;; be kept in mind that we have to cater to code like what at one time \n\
-;; was in fs/super.c: \n\
-;; i = size - copy_from_user((void *)page, data, size); \n\
-;; which would cause repeated faults while clearing the remainder of \n\
-;; the SIZE bytes at PAGE after the first fault. \n\
-;; A caveat here is that we must not fall through from a failing page \n\
-;; to a valid page. \n\
- \n\
-3: \n\
- movem [$sp+],$r10 \n\
- addq 44,$r12 ;; Get back count before faulting point. \n\
- subq 44,$r11 ;; Get back pointer to faulting movem-line. \n\
- jump 4b ;; Fall through, pretending the fault didn't happen.\n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 1b,3b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
-
- }
-
- /* Either we directly start copying here, using dword copying in a loop,
- or we copy as much as possible with 'movem' and then the last block
- (<44 bytes) is copied here. This will work since 'movem' will have
- updated src, dst and n. (Except with failing src.)
-
- Since we want to keep src accurate, we can't use
- __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and
- retn, but not src (by design; it's value is ignored elsewhere). */
-
- while (n >= 4)
- {
- __asm_copy_from_user_4 (dst, src, retn);
- n -= 4;
-
- if (retn)
- goto exception;
- }
-
- /* If we get here, there were no memory read faults. */
- switch (n)
- {
- /* These copies are at least "naturally aligned" (so we don't have
- to check each byte), due to the src alignment code before the
- movem loop. The *_3 case *will* get the correct count for retn. */
- case 0:
- /* This case deliberately left in (if you have doubts check the
- generated assembly code). */
- break;
- case 1:
- __asm_copy_from_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_from_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_from_user_3 (dst, src, retn);
- break;
- }
-
- /* If we get here, retn correctly reflects the number of failing
- bytes. */
- return retn;
-
-exception:
- return retn + n;
-}
-EXPORT_SYMBOL(__copy_user_in);
-
-/* Zero userspace. */
-unsigned long __do_clear_user(void __user *pto, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pto;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_clear_1 (dst, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_clear_2 (dst, retn);
- n -= 2;
- }
- }
-
- /* Decide which copying method to use.
- FIXME: This number is from the "ordinary" kernel memset. */
- if (n >= (1*48))
- {
- /* For large clears we use 'movem' */
-
- /* It is not optimal to tell the compiler about clobbering any
- call-saved registers; that will move the saving/restoring of
- those registers to the function prologue/epilogue, and make
- non-movem sizes suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- something like "r13=r13, r11=r11, r12=r12". */
- __asm__ volatile ("\n\
- .ifnc %0%1%2,$r13$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- clear.d $r0 \n\
- clear.d $r1 \n\
- clear.d $r2 \n\
- clear.d $r3 \n\
- clear.d $r4 \n\
- clear.d $r5 \n\
- clear.d $r6 \n\
- clear.d $r7 \n\
- clear.d $r8 \n\
- clear.d $r9 \n\
- clear.d $r10 \n\
- clear.d $r11 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,$r12 \n\
-0: \n\
- subq 12*4,$r12 \n\
- bge 0b \n\
- movem $r11,[$r13+] \n\
-1: \n\
- addq 12*4,$r12 ;; compensate for last loop underflowing n\n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
-3: \n\
- move.d [$sp],$r10 \n\
- addq 12*4,$r10 \n\
- move.d $r10,[$sp] \n\
- clear.d $r10 \n\
- jump 0b \n\
- \n\
-4: \n\
- movem [$sp+],$r10 \n\
- addq 12*4,$r10 \n\
- addq 12*4,$r12 \n\
- jump 2b \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 0b,3b \n\
- .dword 1b,4b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (n), "2" (retn)
- /* Clobber */ : "r11");
- }
-
- while (n >= 16)
- {
- __asm_clear_16 (dst, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_clear_4 (dst, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_clear_1 (dst, retn);
- break;
- case 2:
- __asm_clear_2 (dst, retn);
- break;
- case 3:
- __asm_clear_3 (dst, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__do_clear_user);
diff --git a/arch/cris/arch-v10/mm/Makefile b/arch/cris/arch-v10/mm/Makefile
deleted file mode 100644
index 588b4baee85e..000000000000
--- a/arch/cris/arch-v10/mm/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for the linux cris-specific parts of the memory manager.
-#
-
-obj-y := fault.o init.o tlb.o
-
diff --git a/arch/cris/arch-v10/mm/fault.c b/arch/cris/arch-v10/mm/fault.c
deleted file mode 100644
index e6c225169642..000000000000
--- a/arch/cris/arch-v10/mm/fault.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/mm/fault.c
- *
- * Low level bus fault handler
- *
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- */
-
-#include <linux/mm.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <arch/svinto.h>
-#include <asm/mmu_context.h>
-
-/* debug of low-level TLB reload */
-#undef DEBUG
-
-#ifdef DEBUG
-#define D(x) x
-#else
-#define D(x)
-#endif
-
-extern const struct exception_table_entry
- *search_exception_tables(unsigned long addr);
-
-asmlinkage void do_page_fault(unsigned long address, struct pt_regs *regs,
- int protection, int writeaccess);
-
-/* fast TLB-fill fault handler
- * this is called from entry.S with interrupts disabled
- */
-
-void
-handle_mmu_bus_fault(struct pt_regs *regs)
-{
- int cause;
- int select;
-#ifdef DEBUG
- int index;
- int page_id;
- int acc, inv;
-#endif
- pgd_t* pgd = (pgd_t*)per_cpu(current_pgd, smp_processor_id());
- pmd_t *pmd;
- pte_t pte;
- int miss, we, writeac;
- unsigned long address;
- unsigned long flags;
-
- cause = *R_MMU_CAUSE;
-
- address = cause & PAGE_MASK; /* get faulting address */
- select = *R_TLB_SELECT;
-
-#ifdef DEBUG
- page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause);
- acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause);
- inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause);
- index = IO_EXTRACT(R_TLB_SELECT, index, select);
-#endif
- miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause);
- we = IO_EXTRACT(R_MMU_CAUSE, we_excp, cause);
- writeac = IO_EXTRACT(R_MMU_CAUSE, wr_rd, cause);
-
- D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n",
- regs->irp, address, miss, inv, we, acc, index, page_id));
-
- /* leave it to the MM system fault handler */
- if (miss)
- do_page_fault(address, regs, 0, writeac);
- else
- do_page_fault(address, regs, 1, we);
-
- /* Reload TLB with new entry to avoid an extra miss exception.
- * do_page_fault may have flushed the TLB so we have to restore
- * the MMU registers.
- */
- local_irq_save(flags);
- pmd = (pmd_t *)(pgd + pgd_index(address));
- if (pmd_none(*pmd))
- goto exit;
- pte = *pte_offset_kernel(pmd, address);
- if (!pte_present(pte))
- goto exit;
- *R_TLB_SELECT = select;
- *R_TLB_HI = cause;
- *R_TLB_LO = pte_val(pte);
-exit:
- local_irq_restore(flags);
-}
diff --git a/arch/cris/arch-v10/mm/init.c b/arch/cris/arch-v10/mm/init.c
deleted file mode 100644
index 4da99a0e3b57..000000000000
--- a/arch/cris/arch-v10/mm/init.c
+++ /dev/null
@@ -1,256 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v10/mm/init.c
- *
- */
-#include <linux/mmzone.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/mm.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/types.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <arch/svinto.h>
-
-extern void tlb_init(void);
-
-/*
- * The kernel is already mapped with a kernel segment at kseg_c so
- * we don't need to map it with a page table. However head.S also
- * temporarily mapped it at kseg_4 so we should set up the ksegs again,
- * clear the TLB and do some other paging setup stuff.
- */
-
-void __init
-paging_init(void)
-{
- int i;
- unsigned long zones_size[MAX_NR_ZONES];
-
- printk("Setting up paging and the MMU.\n");
-
- /* clear out the init_mm.pgd that will contain the kernel's mappings */
-
- for(i = 0; i < PTRS_PER_PGD; i++)
- swapper_pg_dir[i] = __pgd(0);
-
- /* make sure the current pgd table points to something sane
- * (even if it is most probably not used until the next
- * switch_mm)
- */
-
- per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
-
- /* initialise the TLB (tlb.c) */
-
- tlb_init();
-
- /* see README.mm for details on the KSEG setup */
-
-#ifdef CONFIG_CRIS_LOW_MAP
- /* Etrax-100 LX version 1 has a bug so that we cannot map anything
- * across the 0x80000000 boundary, so we need to shrink the user-virtual
- * area to 0x50000000 instead of 0xb0000000 and map things slightly
- * different. The unused areas are marked as paged so that we can catch
- * freak kernel accesses there.
- *
- * The ARTPEC chip is mapped at 0xa so we pass that segment straight
- * through. We cannot vremap it because the vmalloc area is below 0x8
- * and Juliette needs an uncached area above 0x8.
- *
- * Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards.
- * We map them straight over in LOW_MAP, but use vremap in LX version 2.
- */
-
-#define CACHED_BOOTROM (KSEG_F | 0x08000000UL)
-
- *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
- IO_STATE(R_MMU_KSEG, seg_e, page ) |
- IO_STATE(R_MMU_KSEG, seg_d, page ) |
- IO_STATE(R_MMU_KSEG, seg_c, page ) |
- IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
- IO_STATE(R_MMU_KSEG, seg_a, page ) |
- IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
- IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
- IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
- IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */
- IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */
- IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */
-
- *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
- IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
-
- *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
-#else
- /* This code is for the corrected Etrax-100 LX version 2... */
-
-#define CACHED_BOOTROM (KSEG_A | 0x08000000UL)
-
- *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */
- IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */
- IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */
- IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */
- IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
- IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */
- IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */
- IO_STATE(R_MMU_KSEG, seg_8, page ) |
- IO_STATE(R_MMU_KSEG, seg_7, page ) |
- IO_STATE(R_MMU_KSEG, seg_6, page ) |
- IO_STATE(R_MMU_KSEG, seg_5, page ) |
- IO_STATE(R_MMU_KSEG, seg_4, page ) |
- IO_STATE(R_MMU_KSEG, seg_3, page ) |
- IO_STATE(R_MMU_KSEG, seg_2, page ) |
- IO_STATE(R_MMU_KSEG, seg_1, page ) |
- IO_STATE(R_MMU_KSEG, seg_0, page ) );
-
- *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
- IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) );
-
- *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
- IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
-#endif
-
- *R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) );
-
- /* The MMU has been enabled ever since head.S but just to make
- * it totally obvious we do it here as well.
- */
-
- *R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) |
- IO_STATE(R_MMU_CTRL, acc_excp, enable ) |
- IO_STATE(R_MMU_CTRL, we_excp, enable ) );
-
- *R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable);
-
- /*
- * initialize the bad page table and bad page to point
- * to a couple of allocated pages
- */
-
- empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
- memset((void *)empty_zero_page, 0, PAGE_SIZE);
-
- /* All pages are DMA'able in Etrax, so put all in the DMA'able zone */
-
- zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
-
- for (i = 1; i < MAX_NR_ZONES; i++)
- zones_size[i] = 0;
-
- /* Use free_area_init_node instead of free_area_init, because the former
- * is designed for systems where the DRAM starts at an address substantially
- * higher than 0, like us (we start at PAGE_OFFSET). This saves space in the
- * mem_map page array.
- */
-
- free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
-}
-
-/* Initialize remaps of some I/O-ports. It is important that this
- * is called before any driver is initialized.
- */
-
-static int
-__init init_ioremap(void)
-{
-
- /* Give the external I/O-port addresses their values */
-
-#ifdef CONFIG_CRIS_LOW_MAP
- /* Simply a linear map (see the KSEG map above in paging_init) */
- port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START |
- MEM_NON_CACHEABLE);
- port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START |
- MEM_NON_CACHEABLE);
- port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START |
- MEM_NON_CACHEABLE);
-#else
- /* Note that nothing blows up just because we do this remapping
- * it's ok even if the ports are not used or connected
- * to anything (or connected to a non-I/O thing) */
- port_cse1_addr = (volatile unsigned long *)
- ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16);
- port_csp0_addr = (volatile unsigned long *)
- ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16);
- port_csp4_addr = (volatile unsigned long *)
- ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16);
-#endif
- return 0;
-}
-
-__initcall(init_ioremap);
-
-/* Helper function for the two below */
-
-static inline void
-flush_etrax_cacherange(void *startadr, int length)
-{
- /* CACHED_BOOTROM is mapped to the boot-rom area (cached) which
- * we can use to get fast dummy-reads of cachelines
- */
-
- volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) |
- CACHED_BOOTROM);
-
- length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */
-
- while(length > 0) {
- *flushadr; /* dummy read to flush */
- flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */
- length -= 32;
- }
-}
-
-/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers
- * will occasionally corrupt certain CPU writes if the DMA buffers
- * happen to be hot in the cache.
- *
- * As a workaround, we have to flush the relevant parts of the cache
- * before (re) inserting any receiving descriptor into the DMA HW.
- */
-
-void
-prepare_rx_descriptor(struct etrax_dma_descr *desc)
-{
- flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536);
-}
-
-/* Do the same thing but flush the entire cache */
-
-void
-flush_etrax_cache(void)
-{
- flush_etrax_cacherange(0, 8192);
-}
diff --git a/arch/cris/arch-v10/mm/tlb.c b/arch/cris/arch-v10/mm/tlb.c
deleted file mode 100644
index 7f1f752f2445..000000000000
--- a/arch/cris/arch-v10/mm/tlb.c
+++ /dev/null
@@ -1,179 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v10/mm/tlb.c
- *
- * Low level TLB handling
- *
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/mm_types.h>
-
-#include <asm/tlb.h>
-#include <asm/mmu_context.h>
-#include <arch/svinto.h>
-
-#define D(x)
-
-/* The TLB can host up to 64 different mm contexts at the same time.
- * The running context is R_MMU_CONTEXT, and each TLB entry contains a
- * page_id that has to match to give a hit. In page_id_map, we keep track
- * of which mm's we have assigned which page_id's, so that we know when
- * to invalidate TLB entries.
- *
- * The last page_id is never running - it is used as an invalid page_id
- * so we can make TLB entries that will never match.
- *
- * Notice that we need to make the flushes atomic, otherwise an interrupt
- * handler that uses vmalloced memory might cause a TLB load in the middle
- * of a flush causing.
- */
-
-/* invalidate all TLB entries */
-
-void
-flush_tlb_all(void)
-{
- int i;
- unsigned long flags;
-
- /* the vpn of i & 0xf is so we dont write similar TLB entries
- * in the same 4-way entry group. details...
- */
-
- local_irq_save(flags);
- for(i = 0; i < NUM_TLB_ENTRIES; i++) {
- *R_TLB_SELECT = ( IO_FIELD(R_TLB_SELECT, index, i) );
- *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
- IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
-
- *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
- IO_STATE(R_TLB_LO, valid, no ) |
- IO_STATE(R_TLB_LO, kernel,no ) |
- IO_STATE(R_TLB_LO, we, no ) |
- IO_FIELD(R_TLB_LO, pfn, 0 ) );
- }
- local_irq_restore(flags);
- D(printk("tlb: flushed all\n"));
-}
-
-/* invalidate the selected mm context only */
-
-void
-flush_tlb_mm(struct mm_struct *mm)
-{
- int i;
- int page_id = mm->context.page_id;
- unsigned long flags;
-
- D(printk("tlb: flush mm context %d (%p)\n", page_id, mm));
-
- if(page_id == NO_CONTEXT)
- return;
-
- /* mark the TLB entries that match the page_id as invalid.
- * here we could also check the _PAGE_GLOBAL bit and NOT flush
- * global pages. is it worth the extra I/O ?
- */
-
- local_irq_save(flags);
- for(i = 0; i < NUM_TLB_ENTRIES; i++) {
- *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i);
- if (IO_EXTRACT(R_TLB_HI, page_id, *R_TLB_HI) == page_id) {
- *R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
- IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
-
- *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
- IO_STATE(R_TLB_LO, valid, no ) |
- IO_STATE(R_TLB_LO, kernel,no ) |
- IO_STATE(R_TLB_LO, we, no ) |
- IO_FIELD(R_TLB_LO, pfn, 0 ) );
- }
- }
- local_irq_restore(flags);
-}
-
-/* invalidate a single page */
-
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
- struct mm_struct *mm = vma->vm_mm;
- int page_id = mm->context.page_id;
- int i;
- unsigned long flags;
-
- D(printk("tlb: flush page %p in context %d (%p)\n", addr, page_id, mm));
-
- if(page_id == NO_CONTEXT)
- return;
-
- addr &= PAGE_MASK; /* perhaps not necessary */
-
- /* invalidate those TLB entries that match both the mm context
- * and the virtual address requested
- */
-
- local_irq_save(flags);
- for(i = 0; i < NUM_TLB_ENTRIES; i++) {
- unsigned long tlb_hi;
- *R_TLB_SELECT = IO_FIELD(R_TLB_SELECT, index, i);
- tlb_hi = *R_TLB_HI;
- if (IO_EXTRACT(R_TLB_HI, page_id, tlb_hi) == page_id &&
- (tlb_hi & PAGE_MASK) == addr) {
- *R_TLB_HI = IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
- addr; /* same addr as before works. */
-
- *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
- IO_STATE(R_TLB_LO, valid, no ) |
- IO_STATE(R_TLB_LO, kernel,no ) |
- IO_STATE(R_TLB_LO, we, no ) |
- IO_FIELD(R_TLB_LO, pfn, 0 ) );
- }
- }
- local_irq_restore(flags);
-}
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-
-int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- mm->context.page_id = NO_CONTEXT;
- return 0;
-}
-
-/* called in schedule() just before actually doing the switch_to */
-
-void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- if (prev != next) {
- /* make sure we have a context */
- get_mmu_context(next);
-
- /* remember the pgd for the fault handlers
- * this is similar to the pgd register in some other CPU's.
- * we need our own copy of it because current and active_mm
- * might be invalid at points where we still need to derefer
- * the pgd.
- */
-
- per_cpu(current_pgd, smp_processor_id()) = next->pgd;
-
- /* switch context in the MMU */
-
- D(printk(KERN_DEBUG "switching mmu_context to %d (%p)\n",
- next->context, next));
-
- *R_MMU_CONTEXT = IO_FIELD(R_MMU_CONTEXT,
- page_id, next->context.page_id);
- }
-}
-
diff --git a/arch/cris/arch-v10/output_arch.ld b/arch/cris/arch-v10/output_arch.ld
deleted file mode 100644
index 2f3288006991..000000000000
--- a/arch/cris/arch-v10/output_arch.ld
+++ /dev/null
@@ -1,2 +0,0 @@
-/* At the time of this writing, there's no equivalent ld option. */
-OUTPUT_ARCH (cris)
diff --git a/arch/cris/arch-v32/Kconfig b/arch/cris/arch-v32/Kconfig
deleted file mode 100644
index 958dabfca7eb..000000000000
--- a/arch/cris/arch-v32/Kconfig
+++ /dev/null
@@ -1,211 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V32
-
-source arch/cris/arch-v32/mach-fs/Kconfig
-source arch/cris/arch-v32/mach-a3/Kconfig
-
-source drivers/cpufreq/Kconfig
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- depends on ETRAX_ARCH_V32
- default "c0000000"
-
-choice
- prompt "Kernel GDB port"
- depends on ETRAX_KGDB
- default ETRAX_KGDB_PORT0
- help
- Choose a serial port for kernel debugging. NOTE: This port should
- not be enabled under Drivers for built-in interfaces (as it has its
- own initialization code) and should not be the same as the debug port.
-
-config ETRAX_KGDB_PORT4
- bool "Serial-4"
- depends on ETRAX_SERIAL_PORTS = 5
- help
- Use serial port 4 for kernel debugging.
-
-endchoice
-
-config ETRAX_MEM_GRP1_CONFIG
- hex "MEM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "4044a"
- help
- Waitstates for flash. The default value is suitable for the
- standard flashes used in axis products (120 ns).
-
-config ETRAX_MEM_GRP2_CONFIG
- hex "MEM_GRP2_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for SRAM. 0 is a good choice for most Axis products.
-
-config ETRAX_MEM_GRP3_CONFIG
- hex "MEM_GRP3_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP0-3. 0 is a good choice for most Axis products.
- It may need to be changed if external devices such as extra
- register-mapped LEDs are used.
-
-config ETRAX_MEM_GRP4_CONFIG
- hex "MEM_GRP4_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP4-6. 0 is a good choice for most Axis products.
-
-config ETRAX_SDRAM_GRP0_CONFIG
- hex "SDRAM_GRP0_CONFIG"
- depends on ETRAX_ARCH_V32
- default "336"
- help
- SDRAM configuration for group 0. The value depends on the
- hardware configuration. The default value is suitable
- for 32 MB organized as two 16 bits chips (e.g. Axis
- part number 18550) connected as one 32 bit device (i.e. in
- the same group).
-
-config ETRAX_SDRAM_GRP1_CONFIG
- hex "SDRAM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM configuration for group 1. The default value is 0
- because group 1 is not used in the default configuration,
- described in the help for SDRAM_GRP0_CONFIG.
-
-config ETRAX_SDRAM_TIMING
- hex "SDRAM_TIMING"
- depends on ETRAX_ARCH_V32
- default "104a"
- help
- SDRAM timing parameters. The default value is ok for
- most hardwares but large SDRAMs may require a faster
- refresh (a.k.a 8K refresh). The default value implies
- 100MHz clock and SDR mode.
-
-config ETRAX_SDRAM_COMMAND
- hex "SDRAM_COMMAND"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM command. Should be 0 unless you really know what
- you are doing (may be != 0 for unusual address line
- mappings such as in a MCM)..
-
-config ETRAX_DEF_GIO_PA_OE
- hex "GIO_PA_OE"
- depends on ETRAX_ARCH_V32
- default "1c"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PA_OUT
- hex "GIO_PA_OUT"
- depends on ETRAX_ARCH_V32
- default "00"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_GIO_PB_OE
- hex "GIO_PB_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PB_OUT
- hex "GIO_PB_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port B bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PC_OE
- hex "GIO_PC_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port C bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PC_OUT
- hex "GIO_PC_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port C bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PD_OE
- hex "GIO_PD_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port D bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PD_OUT
- hex "GIO_PD_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port D bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PE_OE
- hex "GIO_PE_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port E bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PE_OUT
- hex "GIO_PE_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port E bits. Most
- products should use 00000 here.
-
-endif
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
deleted file mode 100644
index 4d2d744bced2..000000000000
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ /dev/null
@@ -1,263 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAX_ARCH_V32
-
-config ETRAX_ETHERNET
- bool "Ethernet support"
- depends on ETRAX_ARCH_V32 && NETDEVICES
- select MII
- help
- This option enables the ETRAX FS built-in 10/100Mbit Ethernet
- controller.
-
-config ETRAX_NO_PHY
- bool "PHY not present"
- depends on ETRAX_ETHERNET
- help
- This option disables all MDIO communication with an ethernet
- transceiver connected to the MII interface. This option shall
- typically be enabled if the MII interface is connected to a
- switch. This option should normally be disabled. If enabled,
- speed and duplex will be locked to 100 Mbit and full duplex.
-
-config ETRAXFS_SERIAL
- bool "Serial-port support"
- depends on ETRAX_ARCH_V32
- select SERIAL_CORE
- select SERIAL_CORE_CONSOLE
- help
- Enables the ETRAX FS serial driver for ser0 (ttyS0)
- You probably want this enabled.
-
-config ETRAX_RS485
- bool "RS-485 support"
- depends on ETRAXFS_SERIAL
- help
- Enables support for RS-485 serial communication.
-
-config ETRAX_RS485_DISABLE_RECEIVER
- bool "Disable serial receiver"
- depends on ETRAX_RS485
- help
- It is necessary to disable the serial receiver to avoid serial
- loopback. Not all products are able to do this in software only.
-
-config ETRAX_SERIAL_PORT0
- bool "Serial port 0 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser0 (ttyS0)
- Normally you want this on. You can control what DMA channels to use
- if you do not need DMA to something else.
- ser0 can use dma4 or dma6 for output and dma5 or dma7 for input.
-
-config ETRAX_SERIAL_PORT1
- bool "Serial port 1 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser1 (ttyS1).
-
-config ETRAX_SERIAL_PORT2
- bool "Serial port 2 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser2 (ttyS2).
-
-config ETRAX_SERIAL_PORT3
- bool "Serial port 3 enabled"
- depends on ETRAXFS_SERIAL
- help
- Enables the ETRAX FS serial driver for ser3 (ttyS3).
-
-config ETRAX_SYNCHRONOUS_SERIAL
- bool "Synchronous serial-port support"
- depends on ETRAX_ARCH_V32
- help
- Enables the ETRAX FS synchronous serial driver.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT0
- bool "Synchronous serial port 0 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL
- help
- Enabled synchronous serial port 0.
-
-config ETRAX_SYNCHRONOUS_SERIAL0_DMA
- bool "Enable DMA on synchronous serial port 0."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-config ETRAX_SYNCHRONOUS_SERIAL_PORT1
- bool "Synchronous serial port 1 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL && ETRAXFS
- help
- Enabled synchronous serial port 1.
-
-config ETRAX_SYNCHRONOUS_SERIAL1_DMA
- bool "Enable DMA on synchronous serial port 1."
- depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1
- help
- A synchronous serial port can run in manual or DMA mode.
- Selecting this option will make it run in DMA mode.
-
-config ETRAX_AXISFLASHMAP
- bool "Axis flash-map support"
- depends on ETRAX_ARCH_V32
- select MTD
- select MTD_CFI
- select MTD_CFI_AMDSTD
- select MTD_JEDECPROBE
- select MTD_BLOCK
- select MTD_COMPLEX_MAPPINGS
- select MTD_MTDRAM
- help
- This option enables MTD mapping of flash devices. Needed to use
- flash memories. If unsure, say Y.
-
-config ETRAX_AXISFLASHMAP_MTD0WHOLE
- bool "MTD0 is whole boot flash device"
- depends on ETRAX_AXISFLASHMAP
- help
- When this option is not set, mtd0 refers to the first partition
- on the boot flash device. When set, mtd0 refers to the whole
- device, with mtd1 referring to the first partition etc.
-
-config ETRAX_PTABLE_SECTOR
- int "Byte-offset of partition table sector"
- depends on ETRAX_AXISFLASHMAP
- default "65536"
- help
- Byte-offset of the partition table in the first flash chip.
- The default value is 64kB and should not be changed unless
- you know exactly what you are doing. The only valid reason
- for changing this is when the flash block size is bigger
- than 64kB (e.g. when using two parallel 16 bit flashes).
-
-config ETRAX_NANDFLASH
- bool "NAND flash support"
- depends on ETRAX_ARCH_V32
- select MTD_NAND
- help
- This option enables MTD mapping of NAND flash devices. Needed to use
- NAND flash memories. If unsure, say Y.
-
-config ETRAX_NANDBOOT
- bool "Boot from NAND flash"
- depends on ETRAX_NANDFLASH
- help
- This options enables booting from NAND flash devices.
- Say Y if your boot code, kernel and root file system is in
- NAND flash. Say N if they are in NOR flash.
-
-config ETRAX_CARDBUS
- bool "Cardbus support"
- depends on ETRAX_ARCH_V32
- help
- Enabled the ETRAX Cardbus driver.
-
-config PCI
- bool
- depends on ETRAX_CARDBUS
- default y
- select HAVE_GENERIC_DMA_COHERENT
-
-config ETRAX_IOP_FW_LOAD
- tristate "IO-processor hotplug firmware loading support"
- depends on ETRAX_ARCH_V32
- select FW_LOADER
- help
- Enables IO-processor hotplug firmware loading support.
-
-config ETRAX_STREAMCOPROC
- tristate "Stream co-processor driver enabled"
- depends on ETRAX_ARCH_V32
- help
- This option enables a driver for the stream co-processor
- for cryptographic operations.
-
-config ETRAX_MMC_IOP
- tristate "MMC/SD host driver using IO-processor"
- depends on ETRAX_ARCH_V32 && MMC
- help
- This option enables the SD/MMC host controller interface.
- The host controller is implemented using the built in
- IO-Processor. Only the SPU is used in this implementation.
-
-config ETRAX_SPI_MMC
-# Make this one of several "choices" (possible simultaneously but
-# suggested uniquely) when an IOP driver emerges for "real" MMC/SD
-# protocol support.
- tristate
- depends on !ETRAX_MMC_IOP
- default MMC
- select SPI
- select MMC_SPI
-
-# While the board info is MMC_SPI only, the drivers are written to be
-# independent of MMC_SPI, so we'll keep SPI non-dependent on the
-# MMC_SPI config choices (well, except for a single depends-on-line
-# for the board-info file until a separate non-MMC SPI board file
-# emerges).
-# FIXME: When that happens, we'll need to be able to ask for and
-# configure non-MMC SPI ports together with MMC_SPI ports (if multiple
-# SPI ports are enabled).
-
-config SPI_ETRAX_SSER
- tristate
- depends on SPI_MASTER && ETRAX_ARCH_V32
- select SPI_BITBANG
- help
- This enables using an synchronous serial (sser) port as a
- SPI master controller on Axis ETRAX FS and later. The
- driver can be configured to use any sser port.
-
-config SPI_ETRAX_GPIO
- tristate
- depends on SPI_MASTER && ETRAX_ARCH_V32
- select SPI_BITBANG
- help
- This enables using GPIO pins port as a SPI master controller
- on Axis ETRAX FS and later. The driver can be configured to
- use any GPIO pins.
-
-config ETRAX_SPI_SSER0
- tristate "SPI using synchronous serial port 0 (sser0)"
- depends on ETRAX_SPI_MMC
- default m if MMC_SPI=m
- default y if MMC_SPI=y
- default y if MMC_SPI=n
- select SPI_ETRAX_SSER
- help
- Say Y for an MMC/SD socket connected to synchronous serial port 0,
- or for devices using the SPI protocol on that port. Say m if you
- want to build it as a module, which will be named spi_crisv32_sser.
- (You need to select MMC separately.)
-
-config ETRAX_SPI_SSER1
- tristate "SPI using synchronous serial port 1 (sser1)"
- depends on ETRAX_SPI_MMC
- default m if MMC_SPI=m && ETRAX_SPI_SSER0=n
- default y if MMC_SPI=y && ETRAX_SPI_SSER0=n
- default y if MMC_SPI=n && ETRAX_SPI_SSER0=n
- select SPI_ETRAX_SSER
- help
- Say Y for an MMC/SD socket connected to synchronous serial port 1,
- or for devices using the SPI protocol on that port. Say m if you
- want to build it as a module, which will be named spi_crisv32_sser.
- (You need to select MMC separately.)
-
-config ETRAX_SPI_GPIO
- tristate "Bitbanged SPI using gpio pins"
- depends on ETRAX_SPI_MMC
- select SPI_ETRAX_GPIO
- default m if MMC_SPI=m && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
- default y if MMC_SPI=y && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
- default y if MMC_SPI=n && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
- help
- Say Y for an MMC/SD socket connected to general I/O pins (but not
- a complete synchronous serial ports), or for devices using the SPI
- protocol on general I/O pins. Slow and slows down the system.
- Say m to build it as a module, which will be called spi_crisv32_gpio.
- (You need to select MMC separately.)
-
-endif
diff --git a/arch/cris/arch-v32/drivers/Makefile b/arch/cris/arch-v32/drivers/Makefile
deleted file mode 100644
index 57c9568707b0..000000000000
--- a/arch/cris/arch-v32/drivers/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_STREAMCOPROC) += cryptocop.o
-obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
-obj-$(CONFIG_ETRAXFS) += mach-fs/
-obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/
-obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o
-obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
-obj-$(CONFIG_PCI) += pci/
diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c
deleted file mode 100644
index 87656c41fec7..000000000000
--- a/arch/cris/arch-v32/drivers/axisflashmap.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * Physical mapping layer for MTD using the Axis partitiontable format
- *
- * Copyright (c) 2001-2007 Axis Communications AB
- *
- * This file is under the GPL.
- *
- * First partition is always sector 0 regardless of if we find a partitiontable
- * or not. In the start of the next sector, there can be a partitiontable that
- * tells us what other partitions to define. If there isn't, we use a default
- * partition split defined below.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-
-#include <linux/mtd/concat.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/mtdram.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/axisflashmap.h>
-#include <asm/mmu.h>
-
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-
-#define FLASH_UNCACHED_ADDR KSEG_E
-#define FLASH_CACHED_ADDR KSEG_F
-
-#define PAGESIZE (512)
-
-#if CONFIG_ETRAX_FLASH_BUSWIDTH==1
-#define flash_data __u8
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
-#define flash_data __u16
-#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
-#define flash_data __u32
-#endif
-
-/* From head.S */
-extern unsigned long romfs_in_flash; /* 1 when romfs_start, _length in flash */
-extern unsigned long romfs_start, romfs_length;
-extern unsigned long nand_boot; /* 1 when booted from nand flash */
-
-struct partition_name {
- char name[6];
-};
-
-/* The master mtd for the entire flash. */
-struct mtd_info* axisflash_mtd = NULL;
-
-/* Map driver functions. */
-
-static map_word flash_read(struct map_info *map, unsigned long ofs)
-{
- map_word tmp;
- tmp.x[0] = *(flash_data *)(map->map_priv_1 + ofs);
- return tmp;
-}
-
-static void flash_copy_from(struct map_info *map, void *to,
- unsigned long from, ssize_t len)
-{
- memcpy(to, (void *)(map->map_priv_1 + from), len);
-}
-
-static void flash_write(struct map_info *map, map_word d, unsigned long adr)
-{
- *(flash_data *)(map->map_priv_1 + adr) = (flash_data)d.x[0];
-}
-
-/*
- * The map for chip select e0.
- *
- * We run into tricky coherence situations if we mix cached with uncached
- * accesses to we only use the uncached version here.
- *
- * The size field is the total size where the flash chips may be mapped on the
- * chip select. MTD probes should find all devices there and it does not matter
- * if there are unmapped gaps or aliases (mirrors of flash devices). The MTD
- * probes will ignore them.
- *
- * The start address in map_priv_1 is in virtual memory so we cannot use
- * MEM_CSE0_START but must rely on that FLASH_UNCACHED_ADDR is the start
- * address of cse0.
- */
-static struct map_info map_cse0 = {
- .name = "cse0",
- .size = MEM_CSE0_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR
-};
-
-/*
- * The map for chip select e1.
- *
- * If there was a gap between cse0 and cse1, map_priv_1 would get the wrong
- * address, but there isn't.
- */
-static struct map_info map_cse1 = {
- .name = "cse1",
- .size = MEM_CSE1_SIZE,
- .bankwidth = CONFIG_ETRAX_FLASH_BUSWIDTH,
- .read = flash_read,
- .copy_from = flash_copy_from,
- .write = flash_write,
- .map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE
-};
-
-#define MAX_PARTITIONS 7
-#ifdef CONFIG_ETRAX_NANDBOOT
-#define NUM_DEFAULT_PARTITIONS 4
-#define DEFAULT_ROOTFS_PARTITION_NO 2
-#define DEFAULT_MEDIA_SIZE 0x2000000 /* 32 megs */
-#else
-#define NUM_DEFAULT_PARTITIONS 3
-#define DEFAULT_ROOTFS_PARTITION_NO (-1)
-#define DEFAULT_MEDIA_SIZE 0x800000 /* 8 megs */
-#endif
-
-#if (MAX_PARTITIONS < NUM_DEFAULT_PARTITIONS)
-#error MAX_PARTITIONS must be >= than NUM_DEFAULT_PARTITIONS
-#endif
-
-/* Initialize the ones normally used. */
-static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
- {
- .name = "part0",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "part1",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part2",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part3",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part4",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part5",
- .size = 0,
- .offset = 0
- },
- {
- .name = "part6",
- .size = 0,
- .offset = 0
- },
-};
-
-
-/* If no partition-table was found, we use this default-set.
- * Default flash size is 8MB (NOR). CONFIG_ETRAX_PTABLE_SECTOR is most
- * likely the size of one flash block and "filesystem"-partition needs
- * to be >=5 blocks to be able to use JFFS.
- */
-static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
- {
- .name = "boot firmware",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "kernel",
- .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = CONFIG_ETRAX_PTABLE_SECTOR
- },
-#define FILESYSTEM_SECTOR (11 * CONFIG_ETRAX_PTABLE_SECTOR)
-#ifdef CONFIG_ETRAX_NANDBOOT
- {
- .name = "rootfs",
- .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = FILESYSTEM_SECTOR
- },
-#undef FILESYSTEM_SECTOR
-#define FILESYSTEM_SECTOR (21 * CONFIG_ETRAX_PTABLE_SECTOR)
-#endif
- {
- .name = "rwfs",
- .size = DEFAULT_MEDIA_SIZE - FILESYSTEM_SECTOR,
- .offset = FILESYSTEM_SECTOR
- }
-};
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
-/* Main flash device */
-static struct mtd_partition main_partition = {
- .name = "main",
- .size = 0,
- .offset = 0
-};
-#endif
-
-/* Auxiliary partition if we find another flash */
-static struct mtd_partition aux_partition = {
- .name = "aux",
- .size = 0,
- .offset = 0
-};
-
-/*
- * Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
- * chips in that order (because the amd_flash-driver is faster).
- */
-static struct mtd_info *probe_cs(struct map_info *map_cs)
-{
- struct mtd_info *mtd_cs = NULL;
-
- printk(KERN_INFO
- "%s: Probing a 0x%08lx bytes large window at 0x%08lx.\n",
- map_cs->name, map_cs->size, map_cs->map_priv_1);
-
-#ifdef CONFIG_MTD_CFI
- mtd_cs = do_map_probe("cfi_probe", map_cs);
-#endif
-#ifdef CONFIG_MTD_JEDECPROBE
- if (!mtd_cs)
- mtd_cs = do_map_probe("jedec_probe", map_cs);
-#endif
-
- return mtd_cs;
-}
-
-/*
- * Probe each chip select individually for flash chips. If there are chips on
- * both cse0 and cse1, the mtd_info structs will be concatenated to one struct
- * so that MTD partitions can cross chip boundaries.
- *
- * The only known restriction to how you can mount your chips is that each
- * chip select must hold similar flash chips. But you need external hardware
- * to do that anyway and you can put totally different chips on cse0 and cse1
- * so it isn't really much of a restriction.
- */
-extern struct mtd_info* __init crisv32_nand_flash_probe (void);
-static struct mtd_info *flash_probe(void)
-{
- struct mtd_info *mtd_cse0;
- struct mtd_info *mtd_cse1;
- struct mtd_info *mtd_total;
- struct mtd_info *mtds[2];
- int count = 0;
-
- if ((mtd_cse0 = probe_cs(&map_cse0)) != NULL)
- mtds[count++] = mtd_cse0;
- if ((mtd_cse1 = probe_cs(&map_cse1)) != NULL)
- mtds[count++] = mtd_cse1;
-
- if (!mtd_cse0 && !mtd_cse1) {
- /* No chip found. */
- return NULL;
- }
-
- if (count > 1) {
- /* Since the concatenation layer adds a small overhead we
- * could try to figure out if the chips in cse0 and cse1 are
- * identical and reprobe the whole cse0+cse1 window. But since
- * flash chips are slow, the overhead is relatively small.
- * So we use the MTD concatenation layer instead of further
- * complicating the probing procedure.
- */
- mtd_total = mtd_concat_create(mtds, count, "cse0+cse1");
- if (!mtd_total) {
- printk(KERN_ERR "%s and %s: Concatenation failed!\n",
- map_cse0.name, map_cse1.name);
-
- /* The best we can do now is to only use what we found
- * at cse0. */
- mtd_total = mtd_cse0;
- map_destroy(mtd_cse1);
- }
- } else
- mtd_total = mtd_cse0 ? mtd_cse0 : mtd_cse1;
-
- return mtd_total;
-}
-
-/*
- * Probe the flash chip(s) and, if it succeeds, read the partition-table
- * and register the partitions with MTD.
- */
-static int __init init_axis_flash(void)
-{
- struct mtd_info *main_mtd;
- struct mtd_info *aux_mtd = NULL;
- int err = 0;
- int pidx = 0;
- struct partitiontable_head *ptable_head = NULL;
- struct partitiontable_entry *ptable;
- int ptable_ok = 0;
- static char page[PAGESIZE];
- size_t len;
- int ram_rootfs_partition = -1; /* -1 => no RAM rootfs partition */
- int part;
- struct mtd_partition *partition;
-
- /* We need a root fs. If it resides in RAM, we need to use an
- * MTDRAM device, so it must be enabled in the kernel config,
- * but its size must be configured as 0 so as not to conflict
- * with our usage.
- */
-#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0)
- if (!romfs_in_flash && !nand_boot) {
- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
- "device; configure CONFIG_MTD_MTDRAM with size = 0!\n");
- panic("This kernel cannot boot from RAM!\n");
- }
-#endif
-
- main_mtd = flash_probe();
- if (main_mtd)
- printk(KERN_INFO "%s: 0x%08llx bytes of NOR flash memory.\n",
- main_mtd->name, main_mtd->size);
-
-#ifdef CONFIG_ETRAX_NANDFLASH
- aux_mtd = crisv32_nand_flash_probe();
- if (aux_mtd)
- printk(KERN_INFO "%s: 0x%08x bytes of NAND flash memory.\n",
- aux_mtd->name, aux_mtd->size);
-
-#ifdef CONFIG_ETRAX_NANDBOOT
- {
- struct mtd_info *tmp_mtd;
-
- printk(KERN_INFO "axisflashmap: Set to boot from NAND flash, "
- "making NAND flash primary device.\n");
- tmp_mtd = main_mtd;
- main_mtd = aux_mtd;
- aux_mtd = tmp_mtd;
- }
-#endif /* CONFIG_ETRAX_NANDBOOT */
-#endif /* CONFIG_ETRAX_NANDFLASH */
-
- if (!main_mtd && !aux_mtd) {
- /* There's no reason to use this module if no flash chip can
- * be identified. Make sure that's understood.
- */
- printk(KERN_INFO "axisflashmap: Found no flash chip.\n");
- }
-
-#if 0 /* Dump flash memory so we can see what is going on */
- if (main_mtd) {
- int sectoraddr;
- for (sectoraddr = 0; sectoraddr < 2*65536+4096;
- sectoraddr += PAGESIZE) {
- main_mtd->read(main_mtd, sectoraddr, PAGESIZE, &len,
- page);
- printk(KERN_INFO
- "Sector at %d (length %d):\n",
- sectoraddr, len);
- print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, page, PAGESIZE, false);
- }
- }
-#endif
-
- if (main_mtd) {
- loff_t ptable_sector = CONFIG_ETRAX_PTABLE_SECTOR;
- main_mtd->owner = THIS_MODULE;
- axisflash_mtd = main_mtd;
-
-
- /* First partition (rescue) is always set to the default. */
- pidx++;
-#ifdef CONFIG_ETRAX_NANDBOOT
- /* We know where the partition table should be located,
- * it will be in first good block after that.
- */
- int blockstat;
- do {
- blockstat = mtd_block_isbad(main_mtd, ptable_sector);
- if (blockstat < 0)
- ptable_sector = 0; /* read error */
- else if (blockstat)
- ptable_sector += main_mtd->erasesize;
- } while (blockstat && ptable_sector);
-#endif
- if (ptable_sector) {
- mtd_read(main_mtd, ptable_sector, PAGESIZE, &len,
- page);
- ptable_head = &((struct partitiontable *) page)->head;
- }
-
-#if 0 /* Dump partition table so we can see what is going on */
- printk(KERN_INFO
- "axisflashmap: flash read %d bytes at 0x%08x, data: %8ph\n",
- len, CONFIG_ETRAX_PTABLE_SECTOR, page);
- printk(KERN_INFO
- "axisflashmap: partition table offset %d, data: %8ph\n",
- PARTITION_TABLE_OFFSET, page + PARTITION_TABLE_OFFSET);
-#endif
- }
-
- if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC)
- && (ptable_head->size <
- (MAX_PARTITIONS * sizeof(struct partitiontable_entry) +
- PARTITIONTABLE_END_MARKER_SIZE))
- && (*(unsigned long*)((void*)ptable_head + sizeof(*ptable_head) +
- ptable_head->size -
- PARTITIONTABLE_END_MARKER_SIZE)
- == PARTITIONTABLE_END_MARKER)) {
- /* Looks like a start, sane length and end of a
- * partition table, lets check csum etc.
- */
- struct partitiontable_entry *max_addr =
- (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head) +
- ptable_head->size);
- unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
- unsigned char *p;
- unsigned long csum = 0;
-
- ptable = (struct partitiontable_entry *)
- ((unsigned long)ptable_head + sizeof(*ptable_head));
-
- /* Lets be PARANOID, and check the checksum. */
- p = (unsigned char*) ptable;
-
- while (p <= (unsigned char*)max_addr) {
- csum += *p++;
- csum += *p++;
- csum += *p++;
- csum += *p++;
- }
- ptable_ok = (csum == ptable_head->checksum);
-
- /* Read the entries and use/show the info. */
- printk(KERN_INFO "axisflashmap: "
- "Found a%s partition table at 0x%p-0x%p.\n",
- (ptable_ok ? " valid" : "n invalid"), ptable_head,
- max_addr);
-
- /* We have found a working bootblock. Now read the
- * partition table. Scan the table. It ends with 0xffffffff.
- */
- while (ptable_ok
- && ptable->offset != PARTITIONTABLE_END_MARKER
- && ptable < max_addr
- && pidx < MAX_PARTITIONS - 1) {
-
- axis_partitions[pidx].offset = offset + ptable->offset;
-#ifdef CONFIG_ETRAX_NANDFLASH
- if (main_mtd->type == MTD_NANDFLASH) {
- axis_partitions[pidx].size =
- (((ptable+1)->offset ==
- PARTITIONTABLE_END_MARKER) ?
- main_mtd->size :
- ((ptable+1)->offset + offset)) -
- (ptable->offset + offset);
-
- } else
-#endif /* CONFIG_ETRAX_NANDFLASH */
- axis_partitions[pidx].size = ptable->size;
-#ifdef CONFIG_ETRAX_NANDBOOT
- /* Save partition number of jffs2 ro partition.
- * Needed if RAM booting or root file system in RAM.
- */
- if (!nand_boot &&
- ram_rootfs_partition < 0 && /* not already set */
- ptable->type == PARTITION_TYPE_JFFS2 &&
- (ptable->flags & PARTITION_FLAGS_READONLY_MASK) ==
- PARTITION_FLAGS_READONLY)
- ram_rootfs_partition = pidx;
-#endif /* CONFIG_ETRAX_NANDBOOT */
- pidx++;
- ptable++;
- }
- }
-
- /* Decide whether to use default partition table. */
- /* Only use default table if we actually have a device (main_mtd) */
-
- partition = &axis_partitions[0];
- if (main_mtd && !ptable_ok) {
- memcpy(axis_partitions, axis_default_partitions,
- sizeof(axis_default_partitions));
- pidx = NUM_DEFAULT_PARTITIONS;
- ram_rootfs_partition = DEFAULT_ROOTFS_PARTITION_NO;
- }
-
- /* Add artificial partitions for rootfs if necessary */
- if (romfs_in_flash) {
- /* rootfs is in directly accessible flash memory = NOR flash.
- Add an overlapping device for the rootfs partition. */
- printk(KERN_INFO "axisflashmap: Adding partition for "
- "overlapping root file system image\n");
- axis_partitions[pidx].size = romfs_length;
- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
- axis_partitions[pidx].name = "romfs";
- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE;
- ram_rootfs_partition = -1;
- pidx++;
- } else if (romfs_length && !nand_boot) {
- /* romfs exists in memory, but not in flash, so must be in RAM.
- * Configure an MTDRAM partition. */
- if (ram_rootfs_partition < 0) {
- /* None set yet, put it at the end */
- ram_rootfs_partition = pidx;
- pidx++;
- }
- printk(KERN_INFO "axisflashmap: Adding partition for "
- "root file system image in RAM\n");
- axis_partitions[ram_rootfs_partition].size = romfs_length;
- axis_partitions[ram_rootfs_partition].offset = romfs_start;
- axis_partitions[ram_rootfs_partition].name = "romfs";
- axis_partitions[ram_rootfs_partition].mask_flags |=
- MTD_WRITEABLE;
- }
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
- if (main_mtd) {
- main_partition.size = main_mtd->size;
- err = mtd_device_register(main_mtd, &main_partition, 1);
- if (err)
- panic("axisflashmap: Could not initialize "
- "partition for whole main mtd device!\n");
- }
-#endif
-
- /* Now, register all partitions with mtd.
- * We do this one at a time so we can slip in an MTDRAM device
- * in the proper place if required. */
-
- for (part = 0; part < pidx; part++) {
- if (part == ram_rootfs_partition) {
- /* add MTDRAM partition here */
- struct mtd_info *mtd_ram;
-
- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
- if (!mtd_ram)
- panic("axisflashmap: Couldn't allocate memory "
- "for mtd_info!\n");
- printk(KERN_INFO "axisflashmap: Adding RAM partition "
- "for rootfs image.\n");
- err = mtdram_init_device(mtd_ram,
- (void *)(u_int32_t)partition[part].offset,
- partition[part].size,
- partition[part].name);
- if (err)
- panic("axisflashmap: Could not initialize "
- "MTD RAM device!\n");
- /* JFFS2 likes to have an erasesize. Keep potential
- * JFFS2 rootfs happy by providing one. Since image
- * was most likely created for main mtd, use that
- * erasesize, if available. Otherwise, make a guess. */
- mtd_ram->erasesize = (main_mtd ? main_mtd->erasesize :
- CONFIG_ETRAX_PTABLE_SECTOR);
- } else {
- err = mtd_device_register(main_mtd, &partition[part],
- 1);
- if (err)
- panic("axisflashmap: Could not add mtd "
- "partition %d\n", part);
- }
- }
-
- if (aux_mtd) {
- aux_partition.size = aux_mtd->size;
- err = mtd_device_register(aux_mtd, &aux_partition, 1);
- if (err)
- panic("axisflashmap: Could not initialize "
- "aux mtd device!\n");
-
- }
-
- return err;
-}
-
-/* This adds the above to the kernels init-call chain. */
-module_init(init_axis_flash);
-
-EXPORT_SYMBOL(axisflash_mtd);
diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c
deleted file mode 100644
index a3c353472a8c..000000000000
--- a/arch/cris/arch-v32/drivers/cryptocop.c
+++ /dev/null
@@ -1,3522 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Stream co-processor driver for the ETRAX FS
- *
- * Copyright (C) 2003-2007 Axis Communications AB
- */
-
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/spinlock.h>
-#include <linux/stddef.h>
-
-#include <linux/uaccess.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-
-#include <linux/list.h>
-#include <linux/interrupt.h>
-
-#include <asm/signal.h>
-#include <asm/irq.h>
-
-#include <dma.h>
-#include <hwregs/dma.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect_defs.h>
-
-#include <hwregs/strcop.h>
-#include <hwregs/strcop_defs.h>
-#include <cryptocop.h>
-
-#ifdef CONFIG_ETRAXFS
-#define IN_DMA 9
-#define OUT_DMA 8
-#define IN_DMA_INST regi_dma9
-#define OUT_DMA_INST regi_dma8
-#define DMA_IRQ DMA9_INTR_VECT
-#else
-#define IN_DMA 3
-#define OUT_DMA 2
-#define IN_DMA_INST regi_dma3
-#define OUT_DMA_INST regi_dma2
-#define DMA_IRQ DMA3_INTR_VECT
-#endif
-
-#define DESCR_ALLOC_PAD (31)
-
-struct cryptocop_dma_desc {
- char *free_buf; /* If non-null will be kfreed in free_cdesc() */
- dma_descr_data *dma_descr;
-
- unsigned char dma_descr_buf[sizeof(dma_descr_data) + DESCR_ALLOC_PAD];
-
- unsigned int from_pool:1; /* If 1 'allocated' from the descriptor pool. */
- struct cryptocop_dma_desc *next;
-};
-
-
-struct cryptocop_int_operation{
- void *alloc_ptr;
- cryptocop_session_id sid;
-
- dma_descr_context ctx_out;
- dma_descr_context ctx_in;
-
- /* DMA descriptors allocated by driver. */
- struct cryptocop_dma_desc *cdesc_out;
- struct cryptocop_dma_desc *cdesc_in;
-
- /* Strcop config to use. */
- cryptocop_3des_mode tdes_mode;
- cryptocop_csum_type csum_mode;
-
- /* DMA descrs provided by consumer. */
- dma_descr_data *ddesc_out;
- dma_descr_data *ddesc_in;
-};
-
-
-struct cryptocop_tfrm_ctx {
- cryptocop_tfrm_id tid;
- unsigned int blocklength;
-
- unsigned int start_ix;
-
- struct cryptocop_tfrm_cfg *tcfg;
- struct cryptocop_transform_ctx *tctx;
-
- unsigned char previous_src;
- unsigned char current_src;
-
- /* Values to use in metadata out. */
- unsigned char hash_conf;
- unsigned char hash_mode;
- unsigned char ciph_conf;
- unsigned char cbcmode;
- unsigned char decrypt;
-
- unsigned int requires_padding:1;
- unsigned int strict_block_length:1;
- unsigned int active:1;
- unsigned int done:1;
- size_t consumed;
- size_t produced;
-
- /* Pad (input) descriptors to put in the DMA out list when the transform
- * output is put on the DMA in list. */
- struct cryptocop_dma_desc *pad_descs;
-
- struct cryptocop_tfrm_ctx *prev_src;
- struct cryptocop_tfrm_ctx *curr_src;
-
- /* Mapping to HW. */
- unsigned char unit_no;
-};
-
-
-struct cryptocop_private{
- cryptocop_session_id sid;
- struct cryptocop_private *next;
-};
-
-/* Session list. */
-
-struct cryptocop_transform_ctx{
- struct cryptocop_transform_init init;
- unsigned char dec_key[CRYPTOCOP_MAX_KEY_LENGTH];
- unsigned int dec_key_set:1;
-
- struct cryptocop_transform_ctx *next;
-};
-
-
-struct cryptocop_session{
- cryptocop_session_id sid;
-
- struct cryptocop_transform_ctx *tfrm_ctx;
-
- struct cryptocop_session *next;
-};
-
-/* Priority levels for jobs sent to the cryptocop. Checksum operations from
- kernel have highest priority since TCPIP stack processing must not
- be a bottleneck. */
-typedef enum {
- cryptocop_prio_kernel_csum = 0,
- cryptocop_prio_kernel = 1,
- cryptocop_prio_user = 2,
- cryptocop_prio_no_prios = 3
-} cryptocop_queue_priority;
-
-struct cryptocop_prio_queue{
- struct list_head jobs;
- cryptocop_queue_priority prio;
-};
-
-struct cryptocop_prio_job{
- struct list_head node;
- cryptocop_queue_priority prio;
-
- struct cryptocop_operation *oper;
- struct cryptocop_int_operation *iop;
-};
-
-struct ioctl_job_cb_ctx {
- unsigned int processed:1;
-};
-
-
-static struct cryptocop_session *cryptocop_sessions = NULL;
-spinlock_t cryptocop_sessions_lock;
-
-/* Next Session ID to assign. */
-static cryptocop_session_id next_sid = 1;
-
-/* Pad for checksum. */
-static const char csum_zero_pad[1] = {0x00};
-
-/* Trash buffer for mem2mem operations. */
-#define MEM2MEM_DISCARD_BUF_LENGTH (512)
-static unsigned char mem2mem_discard_buf[MEM2MEM_DISCARD_BUF_LENGTH];
-
-/* Descriptor pool. */
-/* FIXME Tweak this value. */
-#define CRYPTOCOP_DESCRIPTOR_POOL_SIZE (100)
-static struct cryptocop_dma_desc descr_pool[CRYPTOCOP_DESCRIPTOR_POOL_SIZE];
-static struct cryptocop_dma_desc *descr_pool_free_list;
-static int descr_pool_no_free;
-static spinlock_t descr_pool_lock;
-
-/* Lock to stop cryptocop to start processing of a new operation. The holder
- of this lock MUST call cryptocop_start_job() after it is unlocked. */
-spinlock_t cryptocop_process_lock;
-
-static struct cryptocop_prio_queue cryptocop_job_queues[cryptocop_prio_no_prios];
-static spinlock_t cryptocop_job_queue_lock;
-static struct cryptocop_prio_job *cryptocop_running_job = NULL;
-static spinlock_t running_job_lock;
-
-/* The interrupt handler appends completed jobs to this list. The scehduled
- * tasklet removes them upon sending the response to the crypto consumer. */
-static struct list_head cryptocop_completed_jobs;
-static spinlock_t cryptocop_completed_jobs_lock;
-
-DECLARE_WAIT_QUEUE_HEAD(cryptocop_ioc_process_wq);
-
-
-/** Local functions. **/
-
-static int cryptocop_open(struct inode *, struct file *);
-
-static int cryptocop_release(struct inode *, struct file *);
-
-static long cryptocop_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg);
-
-static void cryptocop_start_job(void);
-
-static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation);
-static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation);
-
-static int cryptocop_job_queue_init(void);
-static void cryptocop_job_queue_close(void);
-
-static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length);
-
-static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length);
-
-static int transform_ok(struct cryptocop_transform_init *tinit);
-
-static struct cryptocop_session *get_session(cryptocop_session_id sid);
-
-static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid);
-
-static void delete_internal_operation(struct cryptocop_int_operation *iop);
-
-static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength);
-
-static int init_stream_coprocessor(void);
-
-static void __exit exit_stream_coprocessor(void);
-
-/*#define LDEBUG*/
-#ifdef LDEBUG
-#define DEBUG(s) s
-#define DEBUG_API(s) s
-static void print_cryptocop_operation(struct cryptocop_operation *cop);
-static void print_dma_descriptors(struct cryptocop_int_operation *iop);
-static void print_strcop_crypto_op(struct strcop_crypto_op *cop);
-static void print_lock_status(void);
-static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op);
-#define assert(s) do{if (!(s)) panic(#s);} while(0);
-#else
-#define DEBUG(s)
-#define DEBUG_API(s)
-#define assert(s)
-#endif
-
-
-/* Transform constants. */
-#define DES_BLOCK_LENGTH (8)
-#define AES_BLOCK_LENGTH (16)
-#define MD5_BLOCK_LENGTH (64)
-#define SHA1_BLOCK_LENGTH (64)
-#define CSUM_BLOCK_LENGTH (2)
-#define MD5_STATE_LENGTH (16)
-#define SHA1_STATE_LENGTH (20)
-
-/* The device number. */
-#define CRYPTOCOP_MAJOR (254)
-#define CRYPTOCOP_MINOR (0)
-
-
-
-const struct file_operations cryptocop_fops = {
- .owner = THIS_MODULE,
- .open = cryptocop_open,
- .release = cryptocop_release,
- .unlocked_ioctl = cryptocop_ioctl,
- .llseek = noop_llseek,
-};
-
-
-static void free_cdesc(struct cryptocop_dma_desc *cdesc)
-{
- DEBUG(printk("free_cdesc: cdesc 0x%p, from_pool=%d\n", cdesc, cdesc->from_pool));
- kfree(cdesc->free_buf);
-
- if (cdesc->from_pool) {
- unsigned long int flags;
- spin_lock_irqsave(&descr_pool_lock, flags);
- cdesc->next = descr_pool_free_list;
- descr_pool_free_list = cdesc;
- ++descr_pool_no_free;
- spin_unlock_irqrestore(&descr_pool_lock, flags);
- } else {
- kfree(cdesc);
- }
-}
-
-
-static struct cryptocop_dma_desc *alloc_cdesc(int alloc_flag)
-{
- int use_pool = (alloc_flag & GFP_ATOMIC) ? 1 : 0;
- struct cryptocop_dma_desc *cdesc;
-
- if (use_pool) {
- unsigned long int flags;
- spin_lock_irqsave(&descr_pool_lock, flags);
- if (!descr_pool_free_list) {
- spin_unlock_irqrestore(&descr_pool_lock, flags);
- DEBUG_API(printk("alloc_cdesc: pool is empty\n"));
- return NULL;
- }
- cdesc = descr_pool_free_list;
- descr_pool_free_list = descr_pool_free_list->next;
- --descr_pool_no_free;
- spin_unlock_irqrestore(&descr_pool_lock, flags);
- cdesc->from_pool = 1;
- } else {
- cdesc = kmalloc(sizeof(struct cryptocop_dma_desc), alloc_flag);
- if (!cdesc) {
- DEBUG_API(printk("alloc_cdesc: kmalloc\n"));
- return NULL;
- }
- cdesc->from_pool = 0;
- }
- cdesc->dma_descr = (dma_descr_data*)(((unsigned long int)cdesc + offsetof(struct cryptocop_dma_desc, dma_descr_buf) + DESCR_ALLOC_PAD) & ~0x0000001F);
-
- cdesc->next = NULL;
-
- cdesc->free_buf = NULL;
- cdesc->dma_descr->out_eop = 0;
- cdesc->dma_descr->in_eop = 0;
- cdesc->dma_descr->intr = 0;
- cdesc->dma_descr->eol = 0;
- cdesc->dma_descr->wait = 0;
- cdesc->dma_descr->buf = NULL;
- cdesc->dma_descr->after = NULL;
-
- DEBUG_API(printk("alloc_cdesc: return 0x%p, cdesc->dma_descr=0x%p, from_pool=%d\n", cdesc, cdesc->dma_descr, cdesc->from_pool));
- return cdesc;
-}
-
-
-static void setup_descr_chain(struct cryptocop_dma_desc *cd)
-{
- DEBUG(printk("setup_descr_chain: entering\n"));
- while (cd) {
- if (cd->next) {
- cd->dma_descr->next = (dma_descr_data*)virt_to_phys(cd->next->dma_descr);
- } else {
- cd->dma_descr->next = NULL;
- }
- cd = cd->next;
- }
- DEBUG(printk("setup_descr_chain: exit\n"));
-}
-
-
-/* Create a pad descriptor for the transform.
- * Return -1 for error, 0 if pad created. */
-static int create_pad_descriptor(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **pad_desc, int alloc_flag)
-{
- struct cryptocop_dma_desc *cdesc = NULL;
- int error = 0;
- struct strcop_meta_out mo = {
- .ciphsel = src_none,
- .hashsel = src_none,
- .csumsel = src_none
- };
- char *pad;
- size_t plen;
-
- DEBUG(printk("create_pad_descriptor: start.\n"));
- /* Setup pad descriptor. */
-
- DEBUG(printk("create_pad_descriptor: setting up padding.\n"));
- cdesc = alloc_cdesc(alloc_flag);
- if (!cdesc){
- DEBUG_API(printk("create_pad_descriptor: alloc pad desc\n"));
- goto error_cleanup;
- }
- switch (tc->unit_no) {
- case src_md5:
- error = create_md5_pad(alloc_flag, tc->consumed, &pad, &plen);
- if (error){
- DEBUG_API(printk("create_pad_descriptor: create_md5_pad_failed\n"));
- goto error_cleanup;
- }
- cdesc->free_buf = pad;
- mo.hashsel = src_dma;
- mo.hashconf = tc->hash_conf;
- mo.hashmode = tc->hash_mode;
- break;
- case src_sha1:
- error = create_sha1_pad(alloc_flag, tc->consumed, &pad, &plen);
- if (error){
- DEBUG_API(printk("create_pad_descriptor: create_sha1_pad_failed\n"));
- goto error_cleanup;
- }
- cdesc->free_buf = pad;
- mo.hashsel = src_dma;
- mo.hashconf = tc->hash_conf;
- mo.hashmode = tc->hash_mode;
- break;
- case src_csum:
- if (tc->consumed % tc->blocklength){
- pad = (char*)csum_zero_pad;
- plen = 1;
- } else {
- pad = (char*)cdesc; /* Use any pointer. */
- plen = 0;
- }
- mo.csumsel = src_dma;
- break;
- }
- cdesc->dma_descr->wait = 1;
- cdesc->dma_descr->out_eop = 1; /* Since this is a pad output is pushed. EOP is ok here since the padded unit is the only one active. */
- cdesc->dma_descr->buf = (char*)virt_to_phys((char*)pad);
- cdesc->dma_descr->after = cdesc->dma_descr->buf + plen;
-
- cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
- *pad_desc = cdesc;
-
- return 0;
-
- error_cleanup:
- if (cdesc) free_cdesc(cdesc);
- return -1;
-}
-
-
-static int setup_key_dl_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **kd, int alloc_flag)
-{
- struct cryptocop_dma_desc *key_desc = alloc_cdesc(alloc_flag);
- struct strcop_meta_out mo = {0};
-
- DEBUG(printk("setup_key_dl_desc\n"));
-
- if (!key_desc) {
- DEBUG_API(printk("setup_key_dl_desc: failed descriptor allocation.\n"));
- return -ENOMEM;
- }
-
- /* Download key. */
- if ((tc->tctx->init.alg == cryptocop_alg_aes) && (tc->tcfg->flags & CRYPTOCOP_DECRYPT)) {
- /* Precook the AES decrypt key. */
- if (!tc->tctx->dec_key_set){
- get_aes_decrypt_key(tc->tctx->dec_key, tc->tctx->init.key, tc->tctx->init.keylen);
- tc->tctx->dec_key_set = 1;
- }
- key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->dec_key);
- key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8;
- } else {
- key_desc->dma_descr->buf = (char*)virt_to_phys(tc->tctx->init.key);
- key_desc->dma_descr->after = key_desc->dma_descr->buf + tc->tctx->init.keylen/8;
- }
- /* Setup metadata. */
- mo.dlkey = 1;
- switch (tc->tctx->init.keylen) {
- case 64:
- mo.decrypt = 0;
- mo.hashmode = 0;
- break;
- case 128:
- mo.decrypt = 0;
- mo.hashmode = 1;
- break;
- case 192:
- mo.decrypt = 1;
- mo.hashmode = 0;
- break;
- case 256:
- mo.decrypt = 1;
- mo.hashmode = 1;
- break;
- default:
- break;
- }
- mo.ciphsel = mo.hashsel = mo.csumsel = src_none;
- key_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
-
- key_desc->dma_descr->out_eop = 1;
- key_desc->dma_descr->wait = 1;
- key_desc->dma_descr->intr = 0;
-
- *kd = key_desc;
- return 0;
-}
-
-static int setup_cipher_iv_desc(struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag)
-{
- struct cryptocop_dma_desc *iv_desc = alloc_cdesc(alloc_flag);
- struct strcop_meta_out mo = {0};
-
- DEBUG(printk("setup_cipher_iv_desc\n"));
-
- if (!iv_desc) {
- DEBUG_API(printk("setup_cipher_iv_desc: failed CBC IV descriptor allocation.\n"));
- return -ENOMEM;
- }
- /* Download IV. */
- iv_desc->dma_descr->buf = (char*)virt_to_phys(tc->tcfg->iv);
- iv_desc->dma_descr->after = iv_desc->dma_descr->buf + tc->blocklength;
-
- /* Setup metadata. */
- mo.hashsel = mo.csumsel = src_none;
- mo.ciphsel = src_dma;
- mo.ciphconf = tc->ciph_conf;
- mo.cbcmode = tc->cbcmode;
-
- iv_desc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, mo);
-
- iv_desc->dma_descr->out_eop = 0;
- iv_desc->dma_descr->wait = 1;
- iv_desc->dma_descr->intr = 0;
-
- *id = iv_desc;
- return 0;
-}
-
-/* Map the output length of the transform to operation output starting on the inject index. */
-static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ctx *tc, struct cryptocop_dma_desc **id, int alloc_flag)
-{
- int err = 0;
- struct cryptocop_dma_desc head = {0};
- struct cryptocop_dma_desc *outdesc = &head;
- size_t iov_offset = 0;
- size_t out_ix = 0;
- int outiov_ix = 0;
- struct strcop_meta_in mi = {0};
-
- size_t out_length = tc->produced;
- int rem_length;
- int dlength;
-
- assert(out_length != 0);
- if (((tc->produced + tc->tcfg->inject_ix) > operation->tfrm_op.outlen) || (tc->produced && (operation->tfrm_op.outlen == 0))) {
- DEBUG_API(printk("create_input_descriptors: operation outdata too small\n"));
- return -EINVAL;
- }
- /* Traverse the out iovec until the result inject index is reached. */
- while ((outiov_ix < operation->tfrm_op.outcount) && ((out_ix + operation->tfrm_op.outdata[outiov_ix].iov_len) <= tc->tcfg->inject_ix)){
- out_ix += operation->tfrm_op.outdata[outiov_ix].iov_len;
- outiov_ix++;
- }
- if (outiov_ix >= operation->tfrm_op.outcount){
- DEBUG_API(printk("create_input_descriptors: operation outdata too small\n"));
- return -EINVAL;
- }
- iov_offset = tc->tcfg->inject_ix - out_ix;
- mi.dmasel = tc->unit_no;
-
- /* Setup the output descriptors. */
- while ((out_length > 0) && (outiov_ix < operation->tfrm_op.outcount)) {
- outdesc->next = alloc_cdesc(alloc_flag);
- if (!outdesc->next) {
- DEBUG_API(printk("create_input_descriptors: alloc_cdesc\n"));
- err = -ENOMEM;
- goto error_cleanup;
- }
- outdesc = outdesc->next;
- rem_length = operation->tfrm_op.outdata[outiov_ix].iov_len - iov_offset;
- dlength = (out_length < rem_length) ? out_length : rem_length;
-
- DEBUG(printk("create_input_descriptors:\n"
- "outiov_ix=%d, rem_length=%d, dlength=%d\n"
- "iov_offset=%d, outdata[outiov_ix].iov_len=%d\n"
- "outcount=%d, outiov_ix=%d\n",
- outiov_ix, rem_length, dlength, iov_offset, operation->tfrm_op.outdata[outiov_ix].iov_len, operation->tfrm_op.outcount, outiov_ix));
-
- outdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.outdata[outiov_ix].iov_base + iov_offset);
- outdesc->dma_descr->after = outdesc->dma_descr->buf + dlength;
- outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
-
- out_length -= dlength;
- iov_offset += dlength;
- if (iov_offset >= operation->tfrm_op.outdata[outiov_ix].iov_len) {
- iov_offset = 0;
- ++outiov_ix;
- }
- }
- if (out_length > 0){
- DEBUG_API(printk("create_input_descriptors: not enough room for output, %d remained\n", out_length));
- err = -EINVAL;
- goto error_cleanup;
- }
- /* Set sync in last descriptor. */
- mi.sync = 1;
- outdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
-
- *id = head.next;
- return 0;
-
- error_cleanup:
- while (head.next) {
- outdesc = head.next->next;
- free_cdesc(head.next);
- head.next = outdesc;
- }
- return err;
-}
-
-
-static int create_output_descriptors(struct cryptocop_operation *operation, int *iniov_ix, int *iniov_offset, size_t desc_len, struct cryptocop_dma_desc **current_out_cdesc, struct strcop_meta_out *meta_out, int alloc_flag)
-{
- while (desc_len != 0) {
- struct cryptocop_dma_desc *cdesc;
- int rem_length = operation->tfrm_op.indata[*iniov_ix].iov_len - *iniov_offset;
- int dlength = (desc_len < rem_length) ? desc_len : rem_length;
-
- cdesc = alloc_cdesc(alloc_flag);
- if (!cdesc) {
- DEBUG_API(printk("create_output_descriptors: alloc_cdesc\n"));
- return -ENOMEM;
- }
- (*current_out_cdesc)->next = cdesc;
- (*current_out_cdesc) = cdesc;
-
- cdesc->free_buf = NULL;
-
- cdesc->dma_descr->buf = (char*)virt_to_phys(operation->tfrm_op.indata[*iniov_ix].iov_base + *iniov_offset);
- cdesc->dma_descr->after = cdesc->dma_descr->buf + dlength;
-
- assert(desc_len >= dlength);
- desc_len -= dlength;
- *iniov_offset += dlength;
- if (*iniov_offset >= operation->tfrm_op.indata[*iniov_ix].iov_len) {
- *iniov_offset = 0;
- ++(*iniov_ix);
- if (*iniov_ix > operation->tfrm_op.incount) {
- DEBUG_API(printk("create_output_descriptors: not enough indata in operation."));
- return -EINVAL;
- }
- }
- cdesc->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, (*meta_out));
- } /* while (desc_len != 0) */
- /* Last DMA descriptor gets a 'wait' bit to signal expected change in metadata. */
- (*current_out_cdesc)->dma_descr->wait = 1; /* This will set extraneous WAIT in some situations, e.g. when padding hashes and checksums. */
-
- return 0;
-}
-
-
-static int append_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_dma_desc **current_in_cdesc, struct cryptocop_dma_desc **current_out_cdesc, struct cryptocop_tfrm_ctx *tc, int alloc_flag)
-{
- DEBUG(printk("append_input_descriptors, tc=0x%p, unit_no=%d\n", tc, tc->unit_no));
- if (tc->tcfg) {
- int failed = 0;
- struct cryptocop_dma_desc *idescs = NULL;
- DEBUG(printk("append_input_descriptors: pushing output, consumed %d produced %d bytes.\n", tc->consumed, tc->produced));
- if (tc->pad_descs) {
- DEBUG(printk("append_input_descriptors: append pad descriptors to DMA out list.\n"));
- while (tc->pad_descs) {
- DEBUG(printk("append descriptor 0x%p\n", tc->pad_descs));
- (*current_out_cdesc)->next = tc->pad_descs;
- tc->pad_descs = tc->pad_descs->next;
- (*current_out_cdesc) = (*current_out_cdesc)->next;
- }
- }
-
- /* Setup and append output descriptors to DMA in list. */
- if (tc->unit_no == src_dma){
- /* mem2mem. Setup DMA in descriptors to discard all input prior to the requested mem2mem data. */
- struct strcop_meta_in mi = {.sync = 0, .dmasel = src_dma};
- unsigned int start_ix = tc->start_ix;
- while (start_ix){
- unsigned int desclen = start_ix < MEM2MEM_DISCARD_BUF_LENGTH ? start_ix : MEM2MEM_DISCARD_BUF_LENGTH;
- (*current_in_cdesc)->next = alloc_cdesc(alloc_flag);
- if (!(*current_in_cdesc)->next){
- DEBUG_API(printk("append_input_descriptors: alloc_cdesc mem2mem discard failed\n"));
- return -ENOMEM;
- }
- (*current_in_cdesc) = (*current_in_cdesc)->next;
- (*current_in_cdesc)->dma_descr->buf = (char*)virt_to_phys(mem2mem_discard_buf);
- (*current_in_cdesc)->dma_descr->after = (*current_in_cdesc)->dma_descr->buf + desclen;
- (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
- start_ix -= desclen;
- }
- mi.sync = 1;
- (*current_in_cdesc)->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_in, mi);
- }
-
- failed = create_input_descriptors(operation, tc, &idescs, alloc_flag);
- if (failed){
- DEBUG_API(printk("append_input_descriptors: output descriptor setup failed\n"));
- return failed;
- }
- DEBUG(printk("append_input_descriptors: append output descriptors to DMA in list.\n"));
- while (idescs) {
- DEBUG(printk("append descriptor 0x%p\n", idescs));
- (*current_in_cdesc)->next = idescs;
- idescs = idescs->next;
- (*current_in_cdesc) = (*current_in_cdesc)->next;
- }
- }
- return 0;
-}
-
-
-
-static int cryptocop_setup_dma_list(struct cryptocop_operation *operation, struct cryptocop_int_operation **int_op, int alloc_flag)
-{
- struct cryptocop_session *sess;
- struct cryptocop_transform_ctx *tctx;
-
- struct cryptocop_tfrm_ctx digest_ctx = {
- .previous_src = src_none,
- .current_src = src_none,
- .start_ix = 0,
- .requires_padding = 1,
- .strict_block_length = 0,
- .hash_conf = 0,
- .hash_mode = 0,
- .ciph_conf = 0,
- .cbcmode = 0,
- .decrypt = 0,
- .consumed = 0,
- .produced = 0,
- .pad_descs = NULL,
- .active = 0,
- .done = 0,
- .prev_src = NULL,
- .curr_src = NULL,
- .tcfg = NULL};
- struct cryptocop_tfrm_ctx cipher_ctx = {
- .previous_src = src_none,
- .current_src = src_none,
- .start_ix = 0,
- .requires_padding = 0,
- .strict_block_length = 1,
- .hash_conf = 0,
- .hash_mode = 0,
- .ciph_conf = 0,
- .cbcmode = 0,
- .decrypt = 0,
- .consumed = 0,
- .produced = 0,
- .pad_descs = NULL,
- .active = 0,
- .done = 0,
- .prev_src = NULL,
- .curr_src = NULL,
- .tcfg = NULL};
- struct cryptocop_tfrm_ctx csum_ctx = {
- .previous_src = src_none,
- .current_src = src_none,
- .start_ix = 0,
- .blocklength = 2,
- .requires_padding = 1,
- .strict_block_length = 0,
- .hash_conf = 0,
- .hash_mode = 0,
- .ciph_conf = 0,
- .cbcmode = 0,
- .decrypt = 0,
- .consumed = 0,
- .produced = 0,
- .pad_descs = NULL,
- .active = 0,
- .done = 0,
- .tcfg = NULL,
- .prev_src = NULL,
- .curr_src = NULL,
- .unit_no = src_csum};
- struct cryptocop_tfrm_cfg *tcfg = operation->tfrm_op.tfrm_cfg;
-
- unsigned int indata_ix = 0;
-
- /* iovec accounting. */
- int iniov_ix = 0;
- int iniov_offset = 0;
-
- /* Operation descriptor cfg traversal pointer. */
- struct cryptocop_desc *odsc;
-
- int failed = 0;
- /* List heads for allocated descriptors. */
- struct cryptocop_dma_desc out_cdesc_head = {0};
- struct cryptocop_dma_desc in_cdesc_head = {0};
-
- struct cryptocop_dma_desc *current_out_cdesc = &out_cdesc_head;
- struct cryptocop_dma_desc *current_in_cdesc = &in_cdesc_head;
-
- struct cryptocop_tfrm_ctx *output_tc = NULL;
- void *iop_alloc_ptr;
-
- assert(operation != NULL);
- assert(int_op != NULL);
-
- DEBUG(printk("cryptocop_setup_dma_list: start\n"));
- DEBUG(print_cryptocop_operation(operation));
-
- sess = get_session(operation->sid);
- if (!sess) {
- DEBUG_API(printk("cryptocop_setup_dma_list: no session found for operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag);
- if (!iop_alloc_ptr) {
- DEBUG_API(printk("cryptocop_setup_dma_list: kmalloc cryptocop_int_operation\n"));
- failed = -ENOMEM;
- goto error_cleanup;
- }
- (*int_op) = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out));
- DEBUG(memset((*int_op), 0xff, sizeof(struct cryptocop_int_operation)));
- (*int_op)->alloc_ptr = iop_alloc_ptr;
- DEBUG(printk("cryptocop_setup_dma_list: *int_op=0x%p, alloc_ptr=0x%p\n", *int_op, (*int_op)->alloc_ptr));
-
- (*int_op)->sid = operation->sid;
- (*int_op)->cdesc_out = NULL;
- (*int_op)->cdesc_in = NULL;
- (*int_op)->tdes_mode = cryptocop_3des_ede;
- (*int_op)->csum_mode = cryptocop_csum_le;
- (*int_op)->ddesc_out = NULL;
- (*int_op)->ddesc_in = NULL;
-
- /* Scan operation->tfrm_op.tfrm_cfg for bad configuration and set up the local contexts. */
- if (!tcfg) {
- DEBUG_API(printk("cryptocop_setup_dma_list: no configured transforms in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- while (tcfg) {
- tctx = get_transform_ctx(sess, tcfg->tid);
- if (!tctx) {
- DEBUG_API(printk("cryptocop_setup_dma_list: no transform id %d in session.\n", tcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (tcfg->inject_ix > operation->tfrm_op.outlen){
- DEBUG_API(printk("cryptocop_setup_dma_list: transform id %d inject_ix (%d) > operation->tfrm_op.outlen(%d)", tcfg->tid, tcfg->inject_ix, operation->tfrm_op.outlen));
- failed = -EINVAL;
- goto error_cleanup;
- }
- switch (tctx->init.alg){
- case cryptocop_alg_mem2mem:
- if (cipher_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- /* mem2mem is handled as a NULL cipher. */
- cipher_ctx.cbcmode = 0;
- cipher_ctx.decrypt = 0;
- cipher_ctx.blocklength = 1;
- cipher_ctx.ciph_conf = 0;
- cipher_ctx.unit_no = src_dma;
- cipher_ctx.tcfg = tcfg;
- cipher_ctx.tctx = tctx;
- break;
- case cryptocop_alg_des:
- case cryptocop_alg_3des:
- case cryptocop_alg_aes:
- /* cipher */
- if (cipher_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple ciphers in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- cipher_ctx.tcfg = tcfg;
- cipher_ctx.tctx = tctx;
- if (cipher_ctx.tcfg->flags & CRYPTOCOP_DECRYPT){
- cipher_ctx.decrypt = 1;
- }
- switch (tctx->init.cipher_mode) {
- case cryptocop_cipher_mode_ecb:
- cipher_ctx.cbcmode = 0;
- break;
- case cryptocop_cipher_mode_cbc:
- cipher_ctx.cbcmode = 1;
- break;
- default:
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher_ctx, bad cipher mode==%d\n", tctx->init.cipher_mode));
- failed = -EINVAL;
- goto error_cleanup;
- }
- DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx, set CBC mode==%d\n", cipher_ctx.cbcmode));
- switch (tctx->init.alg){
- case cryptocop_alg_des:
- cipher_ctx.ciph_conf = 0;
- cipher_ctx.unit_no = src_des;
- cipher_ctx.blocklength = DES_BLOCK_LENGTH;
- break;
- case cryptocop_alg_3des:
- cipher_ctx.ciph_conf = 1;
- cipher_ctx.unit_no = src_des;
- cipher_ctx.blocklength = DES_BLOCK_LENGTH;
- break;
- case cryptocop_alg_aes:
- cipher_ctx.ciph_conf = 2;
- cipher_ctx.unit_no = src_aes;
- cipher_ctx.blocklength = AES_BLOCK_LENGTH;
- break;
- default:
- panic("cryptocop_setup_dma_list: impossible algorithm %d\n", tctx->init.alg);
- }
- (*int_op)->tdes_mode = tctx->init.tdes_mode;
- break;
- case cryptocop_alg_md5:
- case cryptocop_alg_sha1:
- /* digest */
- if (digest_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple digests in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- digest_ctx.tcfg = tcfg;
- digest_ctx.tctx = tctx;
- digest_ctx.hash_mode = 0; /* Don't use explicit IV in this API. */
- switch (tctx->init.alg){
- case cryptocop_alg_md5:
- digest_ctx.blocklength = MD5_BLOCK_LENGTH;
- digest_ctx.unit_no = src_md5;
- digest_ctx.hash_conf = 1; /* 1 => MD-5 */
- break;
- case cryptocop_alg_sha1:
- digest_ctx.blocklength = SHA1_BLOCK_LENGTH;
- digest_ctx.unit_no = src_sha1;
- digest_ctx.hash_conf = 0; /* 0 => SHA-1 */
- break;
- default:
- panic("cryptocop_setup_dma_list: impossible digest algorithm\n");
- }
- break;
- case cryptocop_alg_csum:
- /* digest */
- if (csum_ctx.tcfg != NULL){
- DEBUG_API(printk("cryptocop_setup_dma_list: multiple checksums in operation.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- (*int_op)->csum_mode = tctx->init.csum_mode;
- csum_ctx.tcfg = tcfg;
- csum_ctx.tctx = tctx;
- break;
- default:
- /* no algorithm. */
- DEBUG_API(printk("cryptocop_setup_dma_list: invalid algorithm %d specified in tfrm %d.\n", tctx->init.alg, tcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- tcfg = tcfg->next;
- }
- /* Download key if a cipher is used. */
- if (cipher_ctx.tcfg && (cipher_ctx.tctx->init.alg != cryptocop_alg_mem2mem)){
- struct cryptocop_dma_desc *key_desc = NULL;
-
- failed = setup_key_dl_desc(&cipher_ctx, &key_desc, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: setup key dl\n"));
- goto error_cleanup;
- }
- current_out_cdesc->next = key_desc;
- current_out_cdesc = key_desc;
- indata_ix += (unsigned int)(key_desc->dma_descr->after - key_desc->dma_descr->buf);
-
- /* Download explicit IV if a cipher is used and CBC mode and explicit IV selected. */
- if ((cipher_ctx.tctx->init.cipher_mode == cryptocop_cipher_mode_cbc) && (cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV)) {
- struct cryptocop_dma_desc *iv_desc = NULL;
-
- DEBUG(printk("cryptocop_setup_dma_list: setup cipher CBC IV descriptor.\n"));
-
- failed = setup_cipher_iv_desc(&cipher_ctx, &iv_desc, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: CBC IV descriptor.\n"));
- goto error_cleanup;
- }
- current_out_cdesc->next = iv_desc;
- current_out_cdesc = iv_desc;
- indata_ix += (unsigned int)(iv_desc->dma_descr->after - iv_desc->dma_descr->buf);
- }
- }
-
- /* Process descriptors. */
- odsc = operation->tfrm_op.desc;
- while (odsc) {
- struct cryptocop_desc_cfg *dcfg = odsc->cfg;
- struct strcop_meta_out meta_out = {0};
- size_t desc_len = odsc->length;
- int active_count, eop_needed_count;
-
- output_tc = NULL;
-
- DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor\n"));
-
- while (dcfg) {
- struct cryptocop_tfrm_ctx *tc = NULL;
-
- DEBUG(printk("cryptocop_setup_dma_list: parsing an operation descriptor configuration.\n"));
- /* Get the local context for the transform and mark it as the output unit if it produces output. */
- if (digest_ctx.tcfg && (digest_ctx.tcfg->tid == dcfg->tid)){
- tc = &digest_ctx;
- } else if (cipher_ctx.tcfg && (cipher_ctx.tcfg->tid == dcfg->tid)){
- tc = &cipher_ctx;
- } else if (csum_ctx.tcfg && (csum_ctx.tcfg->tid == dcfg->tid)){
- tc = &csum_ctx;
- }
- if (!tc) {
- DEBUG_API(printk("cryptocop_setup_dma_list: invalid transform %d specified in descriptor.\n", dcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (tc->done) {
- DEBUG_API(printk("cryptocop_setup_dma_list: completed transform %d reused.\n", dcfg->tid));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (!tc->active) {
- tc->start_ix = indata_ix;
- tc->active = 1;
- }
-
- tc->previous_src = tc->current_src;
- tc->prev_src = tc->curr_src;
- /* Map source unit id to DMA source config. */
- switch (dcfg->src){
- case cryptocop_source_dma:
- tc->current_src = src_dma;
- break;
- case cryptocop_source_des:
- tc->current_src = src_des;
- break;
- case cryptocop_source_3des:
- tc->current_src = src_des;
- break;
- case cryptocop_source_aes:
- tc->current_src = src_aes;
- break;
- case cryptocop_source_md5:
- case cryptocop_source_sha1:
- case cryptocop_source_csum:
- case cryptocop_source_none:
- default:
- /* We do not allow using accumulating style units (SHA-1, MD5, checksum) as sources to other units.
- */
- DEBUG_API(printk("cryptocop_setup_dma_list: bad unit source configured %d.\n", dcfg->src));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (tc->current_src != src_dma) {
- /* Find the unit we are sourcing from. */
- if (digest_ctx.unit_no == tc->current_src){
- tc->curr_src = &digest_ctx;
- } else if (cipher_ctx.unit_no == tc->current_src){
- tc->curr_src = &cipher_ctx;
- } else if (csum_ctx.unit_no == tc->current_src){
- tc->curr_src = &csum_ctx;
- }
- if ((tc->curr_src == tc) && (tc->unit_no != src_dma)){
- DEBUG_API(printk("cryptocop_setup_dma_list: unit %d configured to source from itself.\n", tc->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
- } else {
- tc->curr_src = NULL;
- }
-
- /* Detect source switch. */
- DEBUG(printk("cryptocop_setup_dma_list: tc->active=%d tc->unit_no=%d tc->current_src=%d tc->previous_src=%d, tc->curr_src=0x%p, tc->prev_srv=0x%p\n", tc->active, tc->unit_no, tc->current_src, tc->previous_src, tc->curr_src, tc->prev_src));
- if (tc->active && (tc->current_src != tc->previous_src)) {
- /* Only allow source switch when both the old source unit and the new one have
- * no pending data to process (i.e. the consumed length must be a multiple of the
- * transform blocklength). */
- /* Note: if the src == NULL we are actually sourcing from DMA out. */
- if (((tc->prev_src != NULL) && (tc->prev_src->consumed % tc->prev_src->blocklength)) ||
- ((tc->curr_src != NULL) && (tc->curr_src->consumed % tc->curr_src->blocklength)))
- {
- DEBUG_API(printk("cryptocop_setup_dma_list: can only disconnect from or connect to a unit on a multiple of the blocklength, old: cons=%d, prod=%d, block=%d, new: cons=%d prod=%d, block=%d.\n", tc->prev_src ? tc->prev_src->consumed : INT_MIN, tc->prev_src ? tc->prev_src->produced : INT_MIN, tc->prev_src ? tc->prev_src->blocklength : INT_MIN, tc->curr_src ? tc->curr_src->consumed : INT_MIN, tc->curr_src ? tc->curr_src->produced : INT_MIN, tc->curr_src ? tc->curr_src->blocklength : INT_MIN));
- failed = -EINVAL;
- goto error_cleanup;
- }
- }
- /* Detect unit deactivation. */
- if (dcfg->last) {
- /* Length check of this is handled below. */
- tc->done = 1;
- }
- dcfg = dcfg->next;
- } /* while (dcfg) */
- DEBUG(printk("cryptocop_setup_dma_list: parsing operation descriptor configuration complete.\n"));
-
- if (cipher_ctx.active && (cipher_ctx.curr_src != NULL) && !cipher_ctx.curr_src->active){
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", cipher_ctx.curr_src->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (digest_ctx.active && (digest_ctx.curr_src != NULL) && !digest_ctx.curr_src->active){
- DEBUG_API(printk("cryptocop_setup_dma_list: digest source from inactive unit %d\n", digest_ctx.curr_src->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (csum_ctx.active && (csum_ctx.curr_src != NULL) && !csum_ctx.curr_src->active){
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher source from inactive unit %d\n", csum_ctx.curr_src->unit_no));
- failed = -EINVAL;
- goto error_cleanup;
- }
-
- /* Update consumed and produced lengths.
-
- The consumed length accounting here is actually cheating. If a unit source from DMA (or any
- other unit that process data in blocks of one octet) it is correct, but if it source from a
- block processing unit, i.e. a cipher, it will be temporarily incorrect at some times. However
- since it is only allowed--by the HW--to change source to or from a block processing unit at times where that
- unit has processed an exact multiple of its block length the end result will be correct.
- Beware that if the source change restriction change this code will need to be (much) reworked.
- */
- DEBUG(printk("cryptocop_setup_dma_list: desc->length=%d, desc_len=%d.\n", odsc->length, desc_len));
-
- if (csum_ctx.active) {
- csum_ctx.consumed += desc_len;
- if (csum_ctx.done) {
- csum_ctx.produced = 2;
- }
- DEBUG(printk("cryptocop_setup_dma_list: csum_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", csum_ctx.consumed, csum_ctx.produced, csum_ctx.blocklength));
- }
- if (digest_ctx.active) {
- digest_ctx.consumed += desc_len;
- if (digest_ctx.done) {
- if (digest_ctx.unit_no == src_md5) {
- digest_ctx.produced = MD5_STATE_LENGTH;
- } else {
- digest_ctx.produced = SHA1_STATE_LENGTH;
- }
- }
- DEBUG(printk("cryptocop_setup_dma_list: digest_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", digest_ctx.consumed, digest_ctx.produced, digest_ctx.blocklength));
- }
- if (cipher_ctx.active) {
- /* Ciphers are allowed only to source from DMA out. That is filtered above. */
- assert(cipher_ctx.current_src == src_dma);
- cipher_ctx.consumed += desc_len;
- cipher_ctx.produced = cipher_ctx.blocklength * (cipher_ctx.consumed / cipher_ctx.blocklength);
- if (cipher_ctx.cbcmode && !(cipher_ctx.tcfg->flags & CRYPTOCOP_EXPLICIT_IV) && cipher_ctx.produced){
- cipher_ctx.produced -= cipher_ctx.blocklength; /* Compensate for CBC iv. */
- }
- DEBUG(printk("cryptocop_setup_dma_list: cipher_ctx producing: consumed=%d, produced=%d, blocklength=%d.\n", cipher_ctx.consumed, cipher_ctx.produced, cipher_ctx.blocklength));
- }
-
- /* Setup the DMA out descriptors. */
- /* Configure the metadata. */
- active_count = 0;
- eop_needed_count = 0;
- if (cipher_ctx.active) {
- ++active_count;
- if (cipher_ctx.unit_no == src_dma){
- /* mem2mem */
- meta_out.ciphsel = src_none;
- } else {
- meta_out.ciphsel = cipher_ctx.current_src;
- }
- meta_out.ciphconf = cipher_ctx.ciph_conf;
- meta_out.cbcmode = cipher_ctx.cbcmode;
- meta_out.decrypt = cipher_ctx.decrypt;
- DEBUG(printk("set ciphsel=%d ciphconf=%d cbcmode=%d decrypt=%d\n", meta_out.ciphsel, meta_out.ciphconf, meta_out.cbcmode, meta_out.decrypt));
- if (cipher_ctx.done) ++eop_needed_count;
- } else {
- meta_out.ciphsel = src_none;
- }
-
- if (digest_ctx.active) {
- ++active_count;
- meta_out.hashsel = digest_ctx.current_src;
- meta_out.hashconf = digest_ctx.hash_conf;
- meta_out.hashmode = 0; /* Explicit mode is not used here. */
- DEBUG(printk("set hashsel=%d hashconf=%d hashmode=%d\n", meta_out.hashsel, meta_out.hashconf, meta_out.hashmode));
- if (digest_ctx.done) {
- assert(digest_ctx.pad_descs == NULL);
- failed = create_pad_descriptor(&digest_ctx, &digest_ctx.pad_descs, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: failed digest pad creation.\n"));
- goto error_cleanup;
- }
- }
- } else {
- meta_out.hashsel = src_none;
- }
-
- if (csum_ctx.active) {
- ++active_count;
- meta_out.csumsel = csum_ctx.current_src;
- if (csum_ctx.done) {
- assert(csum_ctx.pad_descs == NULL);
- failed = create_pad_descriptor(&csum_ctx, &csum_ctx.pad_descs, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: failed csum pad creation.\n"));
- goto error_cleanup;
- }
- }
- } else {
- meta_out.csumsel = src_none;
- }
- DEBUG(printk("cryptocop_setup_dma_list: %d eop needed, %d active units\n", eop_needed_count, active_count));
- /* Setup DMA out descriptors for the indata. */
- failed = create_output_descriptors(operation, &iniov_ix, &iniov_offset, desc_len, &current_out_cdesc, &meta_out, alloc_flag);
- if (failed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: create_output_descriptors %d\n", failed));
- goto error_cleanup;
- }
- /* Setup out EOP. If there are active units that are not done here they cannot get an EOP
- * so we ust setup a zero length descriptor to DMA to signal EOP only to done units.
- * If there is a pad descriptor EOP for the padded unit will be EOPed by it.
- */
- assert(active_count >= eop_needed_count);
- assert((eop_needed_count == 0) || (eop_needed_count == 1));
- if (eop_needed_count) {
- /* This means that the bulk operation (cipher/m2m) is terminated. */
- if (active_count > 1) {
- /* Use zero length EOP descriptor. */
- struct cryptocop_dma_desc *ed = alloc_cdesc(alloc_flag);
- struct strcop_meta_out ed_mo = {0};
- if (!ed) {
- DEBUG_API(printk("cryptocop_setup_dma_list: alloc EOP descriptor for cipher\n"));
- failed = -ENOMEM;
- goto error_cleanup;
- }
-
- assert(cipher_ctx.active && cipher_ctx.done);
-
- if (cipher_ctx.unit_no == src_dma){
- /* mem2mem */
- ed_mo.ciphsel = src_none;
- } else {
- ed_mo.ciphsel = cipher_ctx.current_src;
- }
- ed_mo.ciphconf = cipher_ctx.ciph_conf;
- ed_mo.cbcmode = cipher_ctx.cbcmode;
- ed_mo.decrypt = cipher_ctx.decrypt;
-
- ed->free_buf = NULL;
- ed->dma_descr->wait = 1;
- ed->dma_descr->out_eop = 1;
-
- ed->dma_descr->buf = (char*)virt_to_phys(&ed); /* Use any valid physical address for zero length descriptor. */
- ed->dma_descr->after = ed->dma_descr->buf;
- ed->dma_descr->md = REG_TYPE_CONV(unsigned short int, struct strcop_meta_out, ed_mo);
- current_out_cdesc->next = ed;
- current_out_cdesc = ed;
- } else {
- /* Set EOP in the current out descriptor since the only active module is
- * the one needing the EOP. */
-
- current_out_cdesc->dma_descr->out_eop = 1;
- }
- }
-
- if (cipher_ctx.done && cipher_ctx.active) cipher_ctx.active = 0;
- if (digest_ctx.done && digest_ctx.active) digest_ctx.active = 0;
- if (csum_ctx.done && csum_ctx.active) csum_ctx.active = 0;
- indata_ix += odsc->length;
- odsc = odsc->next;
- } /* while (odsc) */ /* Process descriptors. */
- DEBUG(printk("cryptocop_setup_dma_list: done parsing operation descriptors\n"));
- if (cipher_ctx.tcfg && (cipher_ctx.active || !cipher_ctx.done)){
- DEBUG_API(printk("cryptocop_setup_dma_list: cipher operation not terminated.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (digest_ctx.tcfg && (digest_ctx.active || !digest_ctx.done)){
- DEBUG_API(printk("cryptocop_setup_dma_list: digest operation not terminated.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
- if (csum_ctx.tcfg && (csum_ctx.active || !csum_ctx.done)){
- DEBUG_API(printk("cryptocop_setup_dma_list: csum operation not terminated.\n"));
- failed = -EINVAL;
- goto error_cleanup;
- }
-
- failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &cipher_ctx, alloc_flag);
- if (failed){
- DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
- goto error_cleanup;
- }
- failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &digest_ctx, alloc_flag);
- if (failed){
- DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
- goto error_cleanup;
- }
- failed = append_input_descriptors(operation, &current_in_cdesc, &current_out_cdesc, &csum_ctx, alloc_flag);
- if (failed){
- DEBUG_API(printk("cryptocop_setup_dma_list: append_input_descriptors cipher_ctx %d\n", failed));
- goto error_cleanup;
- }
-
- DEBUG(printk("cryptocop_setup_dma_list: int_op=0x%p, *int_op=0x%p\n", int_op, *int_op));
- (*int_op)->cdesc_out = out_cdesc_head.next;
- (*int_op)->cdesc_in = in_cdesc_head.next;
- DEBUG(printk("cryptocop_setup_dma_list: out_cdesc_head=0x%p in_cdesc_head=0x%p\n", (*int_op)->cdesc_out, (*int_op)->cdesc_in));
-
- setup_descr_chain(out_cdesc_head.next);
- setup_descr_chain(in_cdesc_head.next);
-
- /* Last but not least: mark the last DMA in descriptor for a INTR and EOL and the the
- * last DMA out descriptor for EOL.
- */
- current_in_cdesc->dma_descr->intr = 1;
- current_in_cdesc->dma_descr->eol = 1;
- current_out_cdesc->dma_descr->eol = 1;
-
- /* Setup DMA contexts. */
- (*int_op)->ctx_out.next = NULL;
- (*int_op)->ctx_out.eol = 1;
- (*int_op)->ctx_out.intr = 0;
- (*int_op)->ctx_out.store_mode = 0;
- (*int_op)->ctx_out.en = 0;
- (*int_op)->ctx_out.dis = 0;
- (*int_op)->ctx_out.md0 = 0;
- (*int_op)->ctx_out.md1 = 0;
- (*int_op)->ctx_out.md2 = 0;
- (*int_op)->ctx_out.md3 = 0;
- (*int_op)->ctx_out.md4 = 0;
- (*int_op)->ctx_out.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_out->dma_descr);
- (*int_op)->ctx_out.saved_data_buf = (*int_op)->cdesc_out->dma_descr->buf; /* Already physical address. */
-
- (*int_op)->ctx_in.next = NULL;
- (*int_op)->ctx_in.eol = 1;
- (*int_op)->ctx_in.intr = 0;
- (*int_op)->ctx_in.store_mode = 0;
- (*int_op)->ctx_in.en = 0;
- (*int_op)->ctx_in.dis = 0;
- (*int_op)->ctx_in.md0 = 0;
- (*int_op)->ctx_in.md1 = 0;
- (*int_op)->ctx_in.md2 = 0;
- (*int_op)->ctx_in.md3 = 0;
- (*int_op)->ctx_in.md4 = 0;
-
- (*int_op)->ctx_in.saved_data = (dma_descr_data*)virt_to_phys((*int_op)->cdesc_in->dma_descr);
- (*int_op)->ctx_in.saved_data_buf = (*int_op)->cdesc_in->dma_descr->buf; /* Already physical address. */
-
- DEBUG(printk("cryptocop_setup_dma_list: done\n"));
- return 0;
-
-error_cleanup:
- {
- /* Free all allocated resources. */
- struct cryptocop_dma_desc *tmp_cdesc;
- while (digest_ctx.pad_descs){
- tmp_cdesc = digest_ctx.pad_descs->next;
- free_cdesc(digest_ctx.pad_descs);
- digest_ctx.pad_descs = tmp_cdesc;
- }
- while (csum_ctx.pad_descs){
- tmp_cdesc = csum_ctx.pad_descs->next;
- free_cdesc(csum_ctx.pad_descs);
- csum_ctx.pad_descs = tmp_cdesc;
- }
- assert(cipher_ctx.pad_descs == NULL); /* The ciphers are never padded. */
-
- if (*int_op != NULL) delete_internal_operation(*int_op);
- }
- DEBUG_API(printk("cryptocop_setup_dma_list: done with error %d\n", failed));
- return failed;
-}
-
-
-static void delete_internal_operation(struct cryptocop_int_operation *iop)
-{
- void *ptr = iop->alloc_ptr;
- struct cryptocop_dma_desc *cd = iop->cdesc_out;
- struct cryptocop_dma_desc *next;
-
- DEBUG(printk("delete_internal_operation: iop=0x%p, alloc_ptr=0x%p\n", iop, ptr));
-
- while (cd) {
- next = cd->next;
- free_cdesc(cd);
- cd = next;
- }
- cd = iop->cdesc_in;
- while (cd) {
- next = cd->next;
- free_cdesc(cd);
- cd = next;
- }
- kfree(ptr);
-}
-
-#define MD5_MIN_PAD_LENGTH (9)
-#define MD5_PAD_LENGTH_FIELD_LENGTH (8)
-
-static int create_md5_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length)
-{
- size_t padlen = MD5_BLOCK_LENGTH - (hashed_length % MD5_BLOCK_LENGTH);
- unsigned char *p;
- int i;
- unsigned long long int bit_length = hashed_length << 3;
-
- if (padlen < MD5_MIN_PAD_LENGTH) padlen += MD5_BLOCK_LENGTH;
-
- p = kzalloc(padlen, alloc_flag);
- if (!p) return -ENOMEM;
-
- *p = 0x80;
-
- DEBUG(printk("create_md5_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length));
-
- i = padlen - MD5_PAD_LENGTH_FIELD_LENGTH;
- while (bit_length != 0){
- p[i++] = bit_length % 0x100;
- bit_length >>= 8;
- }
-
- *pad = (char*)p;
- *pad_length = padlen;
-
- return 0;
-}
-
-#define SHA1_MIN_PAD_LENGTH (9)
-#define SHA1_PAD_LENGTH_FIELD_LENGTH (8)
-
-static int create_sha1_pad(int alloc_flag, unsigned long long hashed_length, char **pad, size_t *pad_length)
-{
- size_t padlen = SHA1_BLOCK_LENGTH - (hashed_length % SHA1_BLOCK_LENGTH);
- unsigned char *p;
- int i;
- unsigned long long int bit_length = hashed_length << 3;
-
- if (padlen < SHA1_MIN_PAD_LENGTH) padlen += SHA1_BLOCK_LENGTH;
-
- p = kzalloc(padlen, alloc_flag);
- if (!p) return -ENOMEM;
-
- *p = 0x80;
-
- DEBUG(printk("create_sha1_pad: hashed_length=%lld bits == %lld bytes\n", bit_length, hashed_length));
-
- i = padlen - 1;
- while (bit_length != 0){
- p[i--] = bit_length % 0x100;
- bit_length >>= 8;
- }
-
- *pad = (char*)p;
- *pad_length = padlen;
-
- return 0;
-}
-
-
-static int transform_ok(struct cryptocop_transform_init *tinit)
-{
- switch (tinit->alg){
- case cryptocop_alg_csum:
- switch (tinit->csum_mode){
- case cryptocop_csum_le:
- case cryptocop_csum_be:
- break;
- default:
- DEBUG_API(printk("transform_ok: Bad mode set for csum transform\n"));
- return -EINVAL;
- }
- case cryptocop_alg_mem2mem:
- case cryptocop_alg_md5:
- case cryptocop_alg_sha1:
- if (tinit->keylen != 0) {
- DEBUG_API(printk("transform_ok: non-zero keylength, %d, for a digest/csum algorithm\n", tinit->keylen));
- return -EINVAL; /* This check is a bit strict. */
- }
- break;
- case cryptocop_alg_des:
- if (tinit->keylen != 64) {
- DEBUG_API(printk("transform_ok: keylen %d invalid for DES\n", tinit->keylen));
- return -EINVAL;
- }
- break;
- case cryptocop_alg_3des:
- if (tinit->keylen != 192) {
- DEBUG_API(printk("transform_ok: keylen %d invalid for 3DES\n", tinit->keylen));
- return -EINVAL;
- }
- break;
- case cryptocop_alg_aes:
- if (tinit->keylen != 128 && tinit->keylen != 192 && tinit->keylen != 256) {
- DEBUG_API(printk("transform_ok: keylen %d invalid for AES\n", tinit->keylen));
- return -EINVAL;
- }
- break;
- case cryptocop_no_alg:
- default:
- DEBUG_API(printk("transform_ok: no such algorithm %d\n", tinit->alg));
- return -EINVAL;
- }
-
- switch (tinit->alg){
- case cryptocop_alg_des:
- case cryptocop_alg_3des:
- case cryptocop_alg_aes:
- if (tinit->cipher_mode != cryptocop_cipher_mode_ecb && tinit->cipher_mode != cryptocop_cipher_mode_cbc) return -EINVAL;
- default:
- break;
- }
- return 0;
-}
-
-
-int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag)
-{
- struct cryptocop_session *sess;
- struct cryptocop_transform_init *tfrm_in = tinit;
- struct cryptocop_transform_init *tmp_in;
- int no_tfrms = 0;
- int i;
- unsigned long int flags;
-
- init_stream_coprocessor(); /* For safety if we are called early */
-
- while (tfrm_in){
- int err;
- ++no_tfrms;
- if ((err = transform_ok(tfrm_in))) {
- DEBUG_API(printk("cryptocop_new_session, bad transform\n"));
- return err;
- }
- tfrm_in = tfrm_in->next;
- }
- if (0 == no_tfrms) {
- DEBUG_API(printk("cryptocop_new_session, no transforms specified\n"));
- return -EINVAL;
- }
-
- sess = kmalloc(sizeof(struct cryptocop_session), alloc_flag);
- if (!sess){
- DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_session\n"));
- return -ENOMEM;
- }
-
- sess->tfrm_ctx = kmalloc(no_tfrms * sizeof(struct cryptocop_transform_ctx), alloc_flag);
- if (!sess->tfrm_ctx) {
- DEBUG_API(printk("cryptocop_new_session, kmalloc cryptocop_transform_ctx\n"));
- kfree(sess);
- return -ENOMEM;
- }
-
- tfrm_in = tinit;
- for (i = 0; i < no_tfrms; i++){
- tmp_in = tfrm_in->next;
- while (tmp_in){
- if (tmp_in->tid == tfrm_in->tid) {
- DEBUG_API(printk("cryptocop_new_session, duplicate transform ids\n"));
- kfree(sess->tfrm_ctx);
- kfree(sess);
- return -EINVAL;
- }
- tmp_in = tmp_in->next;
- }
- memcpy(&sess->tfrm_ctx[i].init, tfrm_in, sizeof(struct cryptocop_transform_init));
- sess->tfrm_ctx[i].dec_key_set = 0;
- sess->tfrm_ctx[i].next = &sess->tfrm_ctx[i] + 1;
-
- tfrm_in = tfrm_in->next;
- }
- sess->tfrm_ctx[i-1].next = NULL;
-
- spin_lock_irqsave(&cryptocop_sessions_lock, flags);
- sess->sid = next_sid;
- next_sid++;
- /* TODO If we are really paranoid we should do duplicate check to handle sid wraparound.
- * OTOH 2^64 is a really large number of session. */
- if (next_sid == 0) next_sid = 1;
-
- /* Prepend to session list. */
- sess->next = cryptocop_sessions;
- cryptocop_sessions = sess;
- spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
- *sid = sess->sid;
- return 0;
-}
-
-
-int cryptocop_free_session(cryptocop_session_id sid)
-{
- struct cryptocop_transform_ctx *tc;
- struct cryptocop_session *sess = NULL;
- struct cryptocop_session *psess = NULL;
- unsigned long int flags;
- int i;
- LIST_HEAD(remove_list);
- struct list_head *node, *tmp;
- struct cryptocop_prio_job *pj;
-
- DEBUG(printk("cryptocop_free_session: sid=%lld\n", sid));
-
- spin_lock_irqsave(&cryptocop_sessions_lock, flags);
- sess = cryptocop_sessions;
- while (sess && sess->sid != sid){
- psess = sess;
- sess = sess->next;
- }
- if (sess){
- if (psess){
- psess->next = sess->next;
- } else {
- cryptocop_sessions = sess->next;
- }
- }
- spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
-
- if (!sess) return -EINVAL;
-
- /* Remove queued jobs. */
- spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
-
- for (i = 0; i < cryptocop_prio_no_prios; i++){
- if (!list_empty(&(cryptocop_job_queues[i].jobs))){
- list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) {
- pj = list_entry(node, struct cryptocop_prio_job, node);
- if (pj->oper->sid == sid) {
- list_move_tail(node, &remove_list);
- }
- }
- }
- }
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
-
- list_for_each_safe(node, tmp, &remove_list) {
- list_del(node);
- pj = list_entry(node, struct cryptocop_prio_job, node);
- pj->oper->operation_status = -EAGAIN; /* EAGAIN is not ideal for job/session terminated but it's the best choice I know of. */
- DEBUG(printk("cryptocop_free_session: pj=0x%p, pj->oper=0x%p, pj->iop=0x%p\n", pj, pj->oper, pj->iop));
- pj->oper->cb(pj->oper, pj->oper->cb_data);
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
-
- tc = sess->tfrm_ctx;
- /* Erase keying data. */
- while (tc){
- DEBUG(printk("cryptocop_free_session: memset keys, tfrm id=%d\n", tc->init.tid));
- memset(tc->init.key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH);
- memset(tc->dec_key, 0xff, CRYPTOCOP_MAX_KEY_LENGTH);
- tc = tc->next;
- }
- kfree(sess->tfrm_ctx);
- kfree(sess);
-
- return 0;
-}
-
-static struct cryptocop_session *get_session(cryptocop_session_id sid)
-{
- struct cryptocop_session *sess;
- unsigned long int flags;
-
- spin_lock_irqsave(&cryptocop_sessions_lock, flags);
- sess = cryptocop_sessions;
- while (sess && (sess->sid != sid)){
- sess = sess->next;
- }
- spin_unlock_irqrestore(&cryptocop_sessions_lock, flags);
-
- return sess;
-}
-
-static struct cryptocop_transform_ctx *get_transform_ctx(struct cryptocop_session *sess, cryptocop_tfrm_id tid)
-{
- struct cryptocop_transform_ctx *tc = sess->tfrm_ctx;
-
- DEBUG(printk("get_transform_ctx, sess=0x%p, tid=%d\n", sess, tid));
- assert(sess != NULL);
- while (tc && tc->init.tid != tid){
- DEBUG(printk("tc=0x%p, tc->next=0x%p\n", tc, tc->next));
- tc = tc->next;
- }
- DEBUG(printk("get_transform_ctx, returning tc=0x%p\n", tc));
- return tc;
-}
-
-
-
-/* The AES s-transform matrix (s-box). */
-static const u8 aes_sbox[256] = {
- 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118,
- 202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192,
- 183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21,
- 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117,
- 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132,
- 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207,
- 208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168,
- 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210,
- 205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115,
- 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219,
- 224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121,
- 231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8,
- 186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138,
- 112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158,
- 225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223,
- 140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22
-};
-
-/* AES has a 32 bit word round constants for each round in the
- * key schedule. round_constant[i] is really Rcon[i+1] in FIPS187.
- */
-static u32 round_constant[11] = {
- 0x01000000, 0x02000000, 0x04000000, 0x08000000,
- 0x10000000, 0x20000000, 0x40000000, 0x80000000,
- 0x1B000000, 0x36000000, 0x6C000000
-};
-
-/* Apply the s-box to each of the four occtets in w. */
-static u32 aes_ks_subword(const u32 w)
-{
- u8 bytes[4];
-
- *(u32*)(&bytes[0]) = w;
- bytes[0] = aes_sbox[bytes[0]];
- bytes[1] = aes_sbox[bytes[1]];
- bytes[2] = aes_sbox[bytes[2]];
- bytes[3] = aes_sbox[bytes[3]];
- return *(u32*)(&bytes[0]);
-}
-
-/* The encrypt (forward) Rijndael key schedule algorithm pseudo code:
- * (Note that AES words are 32 bit long)
- *
- * KeyExpansion(byte key[4*Nk], word w[Nb*(Nr+1)], Nk){
- * word temp
- * i = 0
- * while (i < Nk) {
- * w[i] = word(key[4*i, 4*i + 1, 4*i + 2, 4*i + 3])
- * i = i + 1
- * }
- * i = Nk
- *
- * while (i < (Nb * (Nr + 1))) {
- * temp = w[i - 1]
- * if ((i mod Nk) == 0) {
- * temp = SubWord(RotWord(temp)) xor Rcon[i/Nk]
- * }
- * else if ((Nk > 6) && ((i mod Nk) == 4)) {
- * temp = SubWord(temp)
- * }
- * w[i] = w[i - Nk] xor temp
- * }
- * RotWord(t) does a 8 bit cyclic shift left on a 32 bit word.
- * SubWord(t) applies the AES s-box individually to each octet
- * in a 32 bit word.
- *
- * For AES Nk can have the values 4, 6, and 8 (corresponding to
- * values for Nr of 10, 12, and 14). Nb is always 4.
- *
- * To construct w[i], w[i - 1] and w[i - Nk] must be
- * available. Consequently we must keep a state of the last Nk words
- * to be able to create the last round keys.
- */
-static void get_aes_decrypt_key(unsigned char *dec_key, const unsigned char *key, unsigned int keylength)
-{
- u32 temp;
- u32 w_ring[8]; /* nk is max 8, use elements 0..(nk - 1) as a ringbuffer */
- u8 w_last_ix;
- int i;
- u8 nr, nk;
-
- switch (keylength){
- case 128:
- nk = 4;
- nr = 10;
- break;
- case 192:
- nk = 6;
- nr = 12;
- break;
- case 256:
- nk = 8;
- nr = 14;
- break;
- default:
- panic("stream co-processor: bad aes key length in get_aes_decrypt_key\n");
- };
-
- /* Need to do host byte order correction here since key is byte oriented and the
- * kx algorithm is word (u32) oriented. */
- for (i = 0; i < nk; i+=1) {
- w_ring[i] = be32_to_cpu(*(u32*)&key[4*i]);
- }
-
- i = (int)nk;
- w_last_ix = i - 1;
- while (i < (4 * (nr + 2))) {
- temp = w_ring[w_last_ix];
- if (!(i % nk)) {
- /* RotWord(temp) */
- temp = (temp << 8) | (temp >> 24);
- temp = aes_ks_subword(temp);
- temp ^= round_constant[i/nk - 1];
- } else if ((nk > 6) && ((i % nk) == 4)) {
- temp = aes_ks_subword(temp);
- }
- w_last_ix = (w_last_ix + 1) % nk; /* This is the same as (i-Nk) mod Nk */
- temp ^= w_ring[w_last_ix];
- w_ring[w_last_ix] = temp;
-
- /* We need the round keys for round Nr+1 and Nr+2 (round key
- * Nr+2 is the round key beyond the last one used when
- * encrypting). Rounds are numbered starting from 0, Nr=10
- * implies 11 rounds are used in encryption/decryption.
- */
- if (i >= (4 * nr)) {
- /* Need to do host byte order correction here, the key
- * is byte oriented. */
- *(u32*)dec_key = cpu_to_be32(temp);
- dec_key += 4;
- }
- ++i;
- }
-}
-
-
-/**** Job/operation management. ****/
-
-int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation)
-{
- return cryptocop_job_queue_insert(cryptocop_prio_kernel_csum, operation);
-}
-
-int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation)
-{
- return cryptocop_job_queue_insert(cryptocop_prio_kernel, operation);
-}
-
-int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation)
-{
- return cryptocop_job_queue_insert(cryptocop_prio_user, operation);
-}
-
-static int cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation)
-{
- int ret;
- struct cryptocop_prio_job *pj = NULL;
- unsigned long int flags;
-
- DEBUG(printk("cryptocop_job_queue_insert(%d, 0x%p)\n", prio, operation));
-
- if (!operation || !operation->cb){
- DEBUG_API(printk("cryptocop_job_queue_insert oper=0x%p, NULL operation or callback\n", operation));
- return -EINVAL;
- }
-
- if ((ret = cryptocop_job_setup(&pj, operation)) != 0){
- DEBUG_API(printk("cryptocop_job_queue_insert: job setup failed\n"));
- return ret;
- }
- assert(pj != NULL);
-
- spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
- list_add_tail(&pj->node, &cryptocop_job_queues[prio].jobs);
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
-
- /* Make sure a job is running */
- cryptocop_start_job();
- return 0;
-}
-
-static void cryptocop_do_tasklet(unsigned long unused);
-DECLARE_TASKLET (cryptocop_tasklet, cryptocop_do_tasklet, 0);
-
-static void cryptocop_do_tasklet(unsigned long unused)
-{
- struct list_head *node;
- struct cryptocop_prio_job *pj = NULL;
- unsigned long flags;
-
- DEBUG(printk("cryptocop_do_tasklet: entering\n"));
-
- do {
- spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags);
- if (!list_empty(&cryptocop_completed_jobs)){
- node = cryptocop_completed_jobs.next;
- list_del(node);
- pj = list_entry(node, struct cryptocop_prio_job, node);
- } else {
- pj = NULL;
- }
- spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags);
- if (pj) {
- assert(pj->oper != NULL);
-
- /* Notify consumer of operation completeness. */
- DEBUG(printk("cryptocop_do_tasklet: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
-
- pj->oper->operation_status = 0; /* Job is completed. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- } while (pj != NULL);
-
- DEBUG(printk("cryptocop_do_tasklet: exiting\n"));
-}
-
-static irqreturn_t
-dma_done_interrupt(int irq, void *dev_id)
-{
- struct cryptocop_prio_job *done_job;
- reg_dma_rw_ack_intr ack_intr = {
- .data = 1,
- };
-
- REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
-
- DEBUG(printk("cryptocop DMA done\n"));
-
- spin_lock(&running_job_lock);
- if (cryptocop_running_job == NULL){
- printk("stream co-processor got interrupt when not busy\n");
- spin_unlock(&running_job_lock);
- return IRQ_HANDLED;
- }
- done_job = cryptocop_running_job;
- cryptocop_running_job = NULL;
- spin_unlock(&running_job_lock);
-
- /* Start processing a job. */
- if (!spin_trylock(&cryptocop_process_lock)){
- DEBUG(printk("cryptocop irq handler, not starting a job\n"));
- } else {
- cryptocop_start_job();
- spin_unlock(&cryptocop_process_lock);
- }
-
- done_job->oper->operation_status = 0; /* Job is completed. */
- if (done_job->oper->fast_callback){
- /* This operation wants callback from interrupt. */
- done_job->oper->cb(done_job->oper, done_job->oper->cb_data);
- delete_internal_operation(done_job->iop);
- kfree(done_job);
- } else {
- spin_lock(&cryptocop_completed_jobs_lock);
- list_add_tail(&(done_job->node), &cryptocop_completed_jobs);
- spin_unlock(&cryptocop_completed_jobs_lock);
- tasklet_schedule(&cryptocop_tasklet);
- }
-
- DEBUG(printk("cryptocop leave irq handler\n"));
- return IRQ_HANDLED;
-}
-
-
-/* Setup interrupts and DMA channels. */
-static int init_cryptocop(void)
-{
- unsigned long flags;
- reg_dma_rw_cfg dma_cfg = {.en = 1};
- reg_dma_rw_intr_mask intr_mask_in = {.data = regk_dma_yes}; /* Only want descriptor interrupts from the DMA in channel. */
- reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 };
- reg_strcop_rw_cfg strcop_cfg = {
- .ipend = regk_strcop_little,
- .td1 = regk_strcop_e,
- .td2 = regk_strcop_d,
- .td3 = regk_strcop_e,
- .ignore_sync = 0,
- .en = 1
- };
-
- if (request_irq(DMA_IRQ, dma_done_interrupt, 0,
- "stream co-processor DMA", NULL))
- panic("request_irq stream co-processor irq dma9");
-
- (void)crisv32_request_dma(OUT_DMA, "strcop", DMA_PANIC_ON_ERROR,
- 0, dma_strp);
- (void)crisv32_request_dma(IN_DMA, "strcop", DMA_PANIC_ON_ERROR,
- 0, dma_strp);
-
- local_irq_save(flags);
-
- /* Reset and enable the cryptocop. */
- strcop_cfg.en = 0;
- REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg);
- strcop_cfg.en = 1;
- REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg);
-
- /* Enable DMAs. */
- REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */
- REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */
-
- /* Set up wordsize = 4 for DMAs. */
- DMA_WR_CMD(OUT_DMA_INST, regk_dma_set_w_size4);
- DMA_WR_CMD(IN_DMA_INST, regk_dma_set_w_size4);
-
- /* Enable interrupts. */
- REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in);
-
- /* Clear intr ack. */
- REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
-
- local_irq_restore(flags);
-
- return 0;
-}
-
-/* Free used cryptocop hw resources (interrupt and DMA channels). */
-static void release_cryptocop(void)
-{
- unsigned long flags;
- reg_dma_rw_cfg dma_cfg = {.en = 0};
- reg_dma_rw_intr_mask intr_mask_in = {0};
- reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 };
-
- local_irq_save(flags);
-
- /* Clear intr ack. */
- REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
-
- /* Disable DMAs. */
- REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */
- REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */
-
- /* Disable interrupts. */
- REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in);
-
- local_irq_restore(flags);
-
- free_irq(DMA_IRQ, NULL);
-
- (void)crisv32_free_dma(OUT_DMA);
- (void)crisv32_free_dma(IN_DMA);
-}
-
-
-/* Init job queue. */
-static int cryptocop_job_queue_init(void)
-{
- int i;
-
- INIT_LIST_HEAD(&cryptocop_completed_jobs);
-
- for (i = 0; i < cryptocop_prio_no_prios; i++){
- cryptocop_job_queues[i].prio = (cryptocop_queue_priority)i;
- INIT_LIST_HEAD(&cryptocop_job_queues[i].jobs);
- }
- return 0;
-}
-
-
-static void cryptocop_job_queue_close(void)
-{
- struct list_head *node, *tmp;
- struct cryptocop_prio_job *pj = NULL;
- unsigned long int process_flags, flags;
- int i;
-
- /* FIXME: This is as yet untested code. */
-
- /* Stop strcop from getting an operation to process while we are closing the
- module. */
- spin_lock_irqsave(&cryptocop_process_lock, process_flags);
-
- /* Empty the job queue. */
- for (i = 0; i < cryptocop_prio_no_prios; i++){
- if (!list_empty(&(cryptocop_job_queues[i].jobs))){
- list_for_each_safe(node, tmp, &(cryptocop_job_queues[i].jobs)) {
- pj = list_entry(node, struct cryptocop_prio_job, node);
- list_del(node);
-
- /* Call callback to notify consumer of job removal. */
- DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
- pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
-
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- }
- }
- spin_unlock_irqrestore(&cryptocop_process_lock, process_flags);
-
- /* Remove the running job, if any. */
- spin_lock_irqsave(&running_job_lock, flags);
- if (cryptocop_running_job){
- reg_strcop_rw_cfg rw_cfg;
- reg_dma_rw_cfg dma_out_cfg, dma_in_cfg;
-
- /* Stop DMA. */
- dma_out_cfg = REG_RD(dma, OUT_DMA_INST, rw_cfg);
- dma_out_cfg.en = regk_dma_no;
- REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_out_cfg);
-
- dma_in_cfg = REG_RD(dma, IN_DMA_INST, rw_cfg);
- dma_in_cfg.en = regk_dma_no;
- REG_WR(dma, IN_DMA_INST, rw_cfg, dma_in_cfg);
-
- /* Disable the cryptocop. */
- rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg);
- rw_cfg.en = 0;
- REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg);
-
- pj = cryptocop_running_job;
- cryptocop_running_job = NULL;
-
- /* Call callback to notify consumer of job removal. */
- DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
- pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
-
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- spin_unlock_irqrestore(&running_job_lock, flags);
-
- /* Remove completed jobs, if any. */
- spin_lock_irqsave(&cryptocop_completed_jobs_lock, flags);
-
- list_for_each_safe(node, tmp, &cryptocop_completed_jobs) {
- pj = list_entry(node, struct cryptocop_prio_job, node);
- list_del(node);
- /* Call callback to notify consumer of job removal. */
- DEBUG(printk("cryptocop_job_queue_close: callback 0x%p, data 0x%p\n", pj->oper->cb, pj->oper->cb_data));
- pj->oper->operation_status = -EINTR; /* Job is terminated without completion. */
- pj->oper->cb(pj->oper, pj->oper->cb_data);
-
- delete_internal_operation(pj->iop);
- kfree(pj);
- }
- spin_unlock_irqrestore(&cryptocop_completed_jobs_lock, flags);
-}
-
-
-static void cryptocop_start_job(void)
-{
- int i;
- struct cryptocop_prio_job *pj;
- unsigned long int flags;
- unsigned long int running_job_flags;
- reg_strcop_rw_cfg rw_cfg = {.en = 1, .ignore_sync = 0};
-
- DEBUG(printk("cryptocop_start_job: entering\n"));
-
- spin_lock_irqsave(&running_job_lock, running_job_flags);
- if (cryptocop_running_job != NULL){
- /* Already running. */
- DEBUG(printk("cryptocop_start_job: already running, exit\n"));
- spin_unlock_irqrestore(&running_job_lock, running_job_flags);
- return;
- }
- spin_lock_irqsave(&cryptocop_job_queue_lock, flags);
-
- /* Check the queues in priority order. */
- for (i = cryptocop_prio_kernel_csum; (i < cryptocop_prio_no_prios) && list_empty(&cryptocop_job_queues[i].jobs); i++);
- if (i == cryptocop_prio_no_prios) {
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
- spin_unlock_irqrestore(&running_job_lock, running_job_flags);
- DEBUG(printk("cryptocop_start_job: no jobs to run\n"));
- return; /* No jobs to run */
- }
- DEBUG(printk("starting job for prio %d\n", i));
-
- /* TODO: Do not starve lower priority jobs. Let in a lower
- * prio job for every N-th processed higher prio job or some
- * other scheduling policy. This could reasonably be
- * tweakable since the optimal balance would depend on the
- * type of load on the system. */
-
- /* Pull the DMA lists from the job and start the DMA client. */
- pj = list_entry(cryptocop_job_queues[i].jobs.next, struct cryptocop_prio_job, node);
- list_del(&pj->node);
- spin_unlock_irqrestore(&cryptocop_job_queue_lock, flags);
- cryptocop_running_job = pj;
-
- /* Set config register (3DES and CSUM modes). */
- switch (pj->iop->tdes_mode){
- case cryptocop_3des_eee:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_eed:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_d;
- break;
- case cryptocop_3des_ede:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_edd:
- rw_cfg.td1 = regk_strcop_e;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_d;
- break;
- case cryptocop_3des_dee:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_ded:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_e;
- rw_cfg.td3 = regk_strcop_d;
- break;
- case cryptocop_3des_dde:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_e;
- break;
- case cryptocop_3des_ddd:
- rw_cfg.td1 = regk_strcop_d;
- rw_cfg.td2 = regk_strcop_d;
- rw_cfg.td3 = regk_strcop_d;
- break;
- default:
- DEBUG(printk("cryptocop_setup_dma_list: bad 3DES mode\n"));
- }
- switch (pj->iop->csum_mode){
- case cryptocop_csum_le:
- rw_cfg.ipend = regk_strcop_little;
- break;
- case cryptocop_csum_be:
- rw_cfg.ipend = regk_strcop_big;
- break;
- default:
- DEBUG(printk("cryptocop_setup_dma_list: bad checksum mode\n"));
- }
- REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg);
-
- DEBUG(printk("cryptocop_start_job: starting DMA, new cryptocop_running_job=0x%p\n"
- "ctx_in: 0x%p, phys: 0x%p\n"
- "ctx_out: 0x%p, phys: 0x%p\n",
- pj,
- &pj->iop->ctx_in, (char*)virt_to_phys(&pj->iop->ctx_in),
- &pj->iop->ctx_out, (char*)virt_to_phys(&pj->iop->ctx_out)));
-
- /* Start input DMA. */
- flush_dma_context(&pj->iop->ctx_in);
- DMA_START_CONTEXT(IN_DMA_INST, virt_to_phys(&pj->iop->ctx_in));
-
- /* Start output DMA. */
- DMA_START_CONTEXT(OUT_DMA_INST, virt_to_phys(&pj->iop->ctx_out));
-
- spin_unlock_irqrestore(&running_job_lock, running_job_flags);
- DEBUG(printk("cryptocop_start_job: exiting\n"));
-}
-
-
-static int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation)
-{
- int err;
- int alloc_flag = operation->in_interrupt ? GFP_ATOMIC : GFP_KERNEL;
- void *iop_alloc_ptr = NULL;
-
- *pj = kmalloc(sizeof (struct cryptocop_prio_job), alloc_flag);
- if (!*pj) return -ENOMEM;
-
- DEBUG(printk("cryptocop_job_setup: operation=0x%p\n", operation));
-
- (*pj)->oper = operation;
- DEBUG(printk("cryptocop_job_setup, cb=0x%p cb_data=0x%p\n", (*pj)->oper->cb, (*pj)->oper->cb_data));
-
- if (operation->use_dmalists) {
- DEBUG(print_user_dma_lists(&operation->list_op));
- if (!operation->list_op.inlist || !operation->list_op.outlist || !operation->list_op.out_data_buf || !operation->list_op.in_data_buf){
- DEBUG_API(printk("cryptocop_job_setup: bad indata (use_dmalists)\n"));
- kfree(*pj);
- return -EINVAL;
- }
- iop_alloc_ptr = kmalloc(DESCR_ALLOC_PAD + sizeof(struct cryptocop_int_operation), alloc_flag);
- if (!iop_alloc_ptr) {
- DEBUG_API(printk("cryptocop_job_setup: kmalloc cryptocop_int_operation\n"));
- kfree(*pj);
- return -ENOMEM;
- }
- (*pj)->iop = (struct cryptocop_int_operation*)(((unsigned long int)(iop_alloc_ptr + DESCR_ALLOC_PAD + offsetof(struct cryptocop_int_operation, ctx_out)) & ~0x0000001F) - offsetof(struct cryptocop_int_operation, ctx_out));
- DEBUG(memset((*pj)->iop, 0xff, sizeof(struct cryptocop_int_operation)));
- (*pj)->iop->alloc_ptr = iop_alloc_ptr;
- (*pj)->iop->sid = operation->sid;
- (*pj)->iop->cdesc_out = NULL;
- (*pj)->iop->cdesc_in = NULL;
- (*pj)->iop->tdes_mode = operation->list_op.tdes_mode;
- (*pj)->iop->csum_mode = operation->list_op.csum_mode;
- (*pj)->iop->ddesc_out = operation->list_op.outlist;
- (*pj)->iop->ddesc_in = operation->list_op.inlist;
-
- /* Setup DMA contexts. */
- (*pj)->iop->ctx_out.next = NULL;
- (*pj)->iop->ctx_out.eol = 1;
- (*pj)->iop->ctx_out.saved_data = operation->list_op.outlist;
- (*pj)->iop->ctx_out.saved_data_buf = operation->list_op.out_data_buf;
-
- (*pj)->iop->ctx_in.next = NULL;
- (*pj)->iop->ctx_in.eol = 1;
- (*pj)->iop->ctx_in.saved_data = operation->list_op.inlist;
- (*pj)->iop->ctx_in.saved_data_buf = operation->list_op.in_data_buf;
- } else {
- if ((err = cryptocop_setup_dma_list(operation, &(*pj)->iop, alloc_flag))) {
- DEBUG_API(printk("cryptocop_job_setup: cryptocop_setup_dma_list failed %d\n", err));
- kfree(*pj);
- return err;
- }
- }
- DEBUG(print_dma_descriptors((*pj)->iop));
-
- DEBUG(printk("cryptocop_job_setup, DMA list setup successful\n"));
-
- return 0;
-}
-
-static int cryptocop_open(struct inode *inode, struct file *filp)
-{
- int p = iminor(inode);
-
- if (p != CRYPTOCOP_MINOR) return -EINVAL;
-
- filp->private_data = NULL;
- return 0;
-}
-
-
-static int cryptocop_release(struct inode *inode, struct file *filp)
-{
- struct cryptocop_private *dev = filp->private_data;
- struct cryptocop_private *dev_next;
-
- while (dev){
- dev_next = dev->next;
- if (dev->sid != CRYPTOCOP_SESSION_ID_NONE) {
- (void)cryptocop_free_session(dev->sid);
- }
- kfree(dev);
- dev = dev_next;
- }
-
- return 0;
-}
-
-
-static int cryptocop_ioctl_close_session(struct inode *inode, struct file *filp,
- unsigned int cmd, unsigned long arg)
-{
- struct cryptocop_private *dev = filp->private_data;
- struct cryptocop_private *prev_dev = NULL;
- struct strcop_session_op *sess_op = (struct strcop_session_op *)arg;
- struct strcop_session_op sop;
- int err;
-
- DEBUG(printk("cryptocop_ioctl_close_session\n"));
-
- if (!access_ok(VERIFY_READ, sess_op, sizeof(struct strcop_session_op)))
- return -EFAULT;
- err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op));
- if (err) return -EFAULT;
-
- while (dev && (dev->sid != sop.ses_id)) {
- prev_dev = dev;
- dev = dev->next;
- }
- if (dev){
- if (prev_dev){
- prev_dev->next = dev->next;
- } else {
- filp->private_data = dev->next;
- }
- err = cryptocop_free_session(dev->sid);
- if (err) return -EFAULT;
- } else {
- DEBUG_API(printk("cryptocop_ioctl_close_session: session %lld not found\n", sop.ses_id));
- return -EINVAL;
- }
- return 0;
-}
-
-
-static void ioctl_process_job_callback(struct cryptocop_operation *op, void*cb_data)
-{
- struct ioctl_job_cb_ctx *jc = (struct ioctl_job_cb_ctx *)cb_data;
-
- DEBUG(printk("ioctl_process_job_callback: op=0x%p, cb_data=0x%p\n", op, cb_data));
-
- jc->processed = 1;
- wake_up(&cryptocop_ioc_process_wq);
-}
-
-
-#define CRYPTOCOP_IOCTL_CIPHER_TID (1)
-#define CRYPTOCOP_IOCTL_DIGEST_TID (2)
-#define CRYPTOCOP_IOCTL_CSUM_TID (3)
-
-static size_t first_cfg_change_ix(struct strcop_crypto_op *crp_op)
-{
- size_t ch_ix = 0;
-
- if (crp_op->do_cipher) ch_ix = crp_op->cipher_start;
- if (crp_op->do_digest && (crp_op->digest_start < ch_ix)) ch_ix = crp_op->digest_start;
- if (crp_op->do_csum && (crp_op->csum_start < ch_ix)) ch_ix = crp_op->csum_start;
-
- DEBUG(printk("first_cfg_change_ix: ix=%d\n", ch_ix));
- return ch_ix;
-}
-
-
-static size_t next_cfg_change_ix(struct strcop_crypto_op *crp_op, size_t ix)
-{
- size_t ch_ix = INT_MAX;
- size_t tmp_ix = 0;
-
- if (crp_op->do_cipher && ((crp_op->cipher_start + crp_op->cipher_len) > ix)){
- if (crp_op->cipher_start > ix) {
- ch_ix = crp_op->cipher_start;
- } else {
- ch_ix = crp_op->cipher_start + crp_op->cipher_len;
- }
- }
- if (crp_op->do_digest && ((crp_op->digest_start + crp_op->digest_len) > ix)){
- if (crp_op->digest_start > ix) {
- tmp_ix = crp_op->digest_start;
- } else {
- tmp_ix = crp_op->digest_start + crp_op->digest_len;
- }
- if (tmp_ix < ch_ix) ch_ix = tmp_ix;
- }
- if (crp_op->do_csum && ((crp_op->csum_start + crp_op->csum_len) > ix)){
- if (crp_op->csum_start > ix) {
- tmp_ix = crp_op->csum_start;
- } else {
- tmp_ix = crp_op->csum_start + crp_op->csum_len;
- }
- if (tmp_ix < ch_ix) ch_ix = tmp_ix;
- }
- if (ch_ix == INT_MAX) ch_ix = ix;
- DEBUG(printk("next_cfg_change_ix prev ix=%d, next ix=%d\n", ix, ch_ix));
- return ch_ix;
-}
-
-
-/* Map map_length bytes from the pages starting on *pageix and *pageoffset to iovecs starting on *iovix.
- * Return -1 for ok, 0 for fail. */
-static int map_pages_to_iovec(struct iovec *iov, int iovlen, int *iovix, struct page **pages, int nopages, int *pageix, int *pageoffset, int map_length )
-{
- int tmplen;
-
- assert(iov != NULL);
- assert(iovix != NULL);
- assert(pages != NULL);
- assert(pageix != NULL);
- assert(pageoffset != NULL);
-
- DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset));
-
- while (map_length > 0){
- DEBUG(printk("map_pages_to_iovec, map_length=%d, iovlen=%d, *iovix=%d, nopages=%d, *pageix=%d, *pageoffset=%d\n", map_length, iovlen, *iovix, nopages, *pageix, *pageoffset));
- if (*iovix >= iovlen){
- DEBUG_API(printk("map_page_to_iovec: *iovix=%d >= iovlen=%d\n", *iovix, iovlen));
- return 0;
- }
- if (*pageix >= nopages){
- DEBUG_API(printk("map_page_to_iovec: *pageix=%d >= nopages=%d\n", *pageix, nopages));
- return 0;
- }
- iov[*iovix].iov_base = (unsigned char*)page_address(pages[*pageix]) + *pageoffset;
- tmplen = PAGE_SIZE - *pageoffset;
- if (tmplen < map_length){
- (*pageoffset) = 0;
- (*pageix)++;
- } else {
- tmplen = map_length;
- (*pageoffset) += map_length;
- }
- DEBUG(printk("mapping %d bytes from page %d (or %d) to iovec %d\n", tmplen, *pageix, *pageix-1, *iovix));
- iov[*iovix].iov_len = tmplen;
- map_length -= tmplen;
- (*iovix)++;
- }
- DEBUG(printk("map_page_to_iovec, exit, *iovix=%d\n", *iovix));
- return -1;
-}
-
-
-
-static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
-{
- int i;
- struct cryptocop_private *dev = filp->private_data;
- struct strcop_crypto_op *crp_oper = (struct strcop_crypto_op *)arg;
- struct strcop_crypto_op oper = {0};
- int err = 0;
- struct cryptocop_operation *cop = NULL;
-
- struct ioctl_job_cb_ctx *jc = NULL;
-
- struct page **inpages = NULL;
- struct page **outpages = NULL;
- int noinpages = 0;
- int nooutpages = 0;
-
- struct cryptocop_desc descs[5]; /* Max 5 descriptors are needed, there are three transforms that
- * can get connected/disconnected on different places in the indata. */
- struct cryptocop_desc_cfg dcfgs[5*3];
- int desc_ix = 0;
- int dcfg_ix = 0;
- struct cryptocop_tfrm_cfg ciph_tcfg = {0};
- struct cryptocop_tfrm_cfg digest_tcfg = {0};
- struct cryptocop_tfrm_cfg csum_tcfg = {0};
-
- unsigned char *digest_result = NULL;
- int digest_length = 0;
- int cblocklen = 0;
- unsigned char csum_result[CSUM_BLOCK_LENGTH];
- struct cryptocop_session *sess;
-
- int iovlen = 0;
- int iovix = 0;
- int pageix = 0;
- int pageoffset = 0;
-
- size_t prev_ix = 0;
- size_t next_ix;
-
- int cipher_active, digest_active, csum_active;
- int end_digest, end_csum;
- int digest_done = 0;
- int cipher_done = 0;
- int csum_done = 0;
-
- DEBUG(printk("cryptocop_ioctl_process\n"));
-
- if (!access_ok(VERIFY_WRITE, crp_oper, sizeof(struct strcop_crypto_op))){
- DEBUG_API(printk("cryptocop_ioctl_process: !access_ok crp_oper!\n"));
- return -EFAULT;
- }
- if (copy_from_user(&oper, crp_oper, sizeof(struct strcop_crypto_op))) {
- DEBUG_API(printk("cryptocop_ioctl_process: copy_from_user\n"));
- return -EFAULT;
- }
- DEBUG(print_strcop_crypto_op(&oper));
-
- while (dev && dev->sid != oper.ses_id) dev = dev->next;
- if (!dev){
- DEBUG_API(printk("cryptocop_ioctl_process: session %lld not found\n", oper.ses_id));
- return -EINVAL;
- }
-
- /* Check buffers. */
- if (((oper.indata + oper.inlen) < oper.indata) || ((oper.cipher_outdata + oper.cipher_outlen) < oper.cipher_outdata)){
- DEBUG_API(printk("cryptocop_ioctl_process: user buffers wrapped around, bad user!\n"));
- return -EINVAL;
- }
-
- if (!access_ok(VERIFY_WRITE, oper.cipher_outdata, oper.cipher_outlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: !access_ok out data!\n"));
- return -EFAULT;
- }
- if (!access_ok(VERIFY_READ, oper.indata, oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: !access_ok in data!\n"));
- return -EFAULT;
- }
-
- cop = kmalloc(sizeof(struct cryptocop_operation), GFP_KERNEL);
- if (!cop) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n"));
- return -ENOMEM;
- }
- jc = kmalloc(sizeof(struct ioctl_job_cb_ctx), GFP_KERNEL);
- if (!jc) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc\n"));
- err = -ENOMEM;
- goto error_cleanup;
- }
- jc->processed = 0;
-
- cop->cb_data = jc;
- cop->cb = ioctl_process_job_callback;
- cop->operation_status = 0;
- cop->use_dmalists = 0;
- cop->in_interrupt = 0;
- cop->fast_callback = 0;
- cop->tfrm_op.tfrm_cfg = NULL;
- cop->tfrm_op.desc = NULL;
- cop->tfrm_op.indata = NULL;
- cop->tfrm_op.incount = 0;
- cop->tfrm_op.inlen = 0;
- cop->tfrm_op.outdata = NULL;
- cop->tfrm_op.outcount = 0;
- cop->tfrm_op.outlen = 0;
-
- sess = get_session(oper.ses_id);
- if (!sess){
- DEBUG_API(printk("cryptocop_ioctl_process: bad session id.\n"));
- kfree(cop);
- kfree(jc);
- return -EINVAL;
- }
-
- if (oper.do_cipher) {
- unsigned int cipher_outlen = 0;
- struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_CIPHER_TID);
- if (!tc) {
- DEBUG_API(printk("cryptocop_ioctl_process: no cipher transform in session.\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
- ciph_tcfg.tid = CRYPTOCOP_IOCTL_CIPHER_TID;
- ciph_tcfg.inject_ix = 0;
- ciph_tcfg.flags = 0;
- if ((oper.cipher_start < 0) || (oper.cipher_len <= 0) || (oper.cipher_start > oper.inlen) || ((oper.cipher_start + oper.cipher_len) > oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: bad cipher length\n"));
- kfree(cop);
- kfree(jc);
- return -EINVAL;
- }
- cblocklen = tc->init.alg == cryptocop_alg_aes ? AES_BLOCK_LENGTH : DES_BLOCK_LENGTH;
- if (oper.cipher_len % cblocklen) {
- kfree(cop);
- kfree(jc);
- DEBUG_API(printk("cryptocop_ioctl_process: cipher inlength not multiple of block length.\n"));
- return -EINVAL;
- }
- cipher_outlen = oper.cipher_len;
- if (tc->init.cipher_mode == cryptocop_cipher_mode_cbc){
- if (oper.cipher_explicit) {
- ciph_tcfg.flags |= CRYPTOCOP_EXPLICIT_IV;
- memcpy(ciph_tcfg.iv, oper.cipher_iv, cblocklen);
- } else {
- cipher_outlen = oper.cipher_len - cblocklen;
- }
- } else {
- if (oper.cipher_explicit){
- kfree(cop);
- kfree(jc);
- DEBUG_API(printk("cryptocop_ioctl_process: explicit_iv when not CBC mode\n"));
- return -EINVAL;
- }
- }
- if (oper.cipher_outlen != cipher_outlen) {
- kfree(cop);
- kfree(jc);
- DEBUG_API(printk("cryptocop_ioctl_process: cipher_outlen incorrect, should be %d not %d.\n", cipher_outlen, oper.cipher_outlen));
- return -EINVAL;
- }
-
- if (oper.decrypt){
- ciph_tcfg.flags |= CRYPTOCOP_DECRYPT;
- } else {
- ciph_tcfg.flags |= CRYPTOCOP_ENCRYPT;
- }
- ciph_tcfg.next = cop->tfrm_op.tfrm_cfg;
- cop->tfrm_op.tfrm_cfg = &ciph_tcfg;
- }
- if (oper.do_digest){
- struct cryptocop_transform_ctx *tc = get_transform_ctx(sess, CRYPTOCOP_IOCTL_DIGEST_TID);
- if (!tc) {
- DEBUG_API(printk("cryptocop_ioctl_process: no digest transform in session.\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
- digest_length = tc->init.alg == cryptocop_alg_md5 ? 16 : 20;
- digest_result = kmalloc(digest_length, GFP_KERNEL);
- if (!digest_result) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc digest_result\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
- DEBUG(memset(digest_result, 0xff, digest_length));
-
- digest_tcfg.tid = CRYPTOCOP_IOCTL_DIGEST_TID;
- digest_tcfg.inject_ix = 0;
- ciph_tcfg.inject_ix += digest_length;
- if ((oper.digest_start < 0) || (oper.digest_len <= 0) || (oper.digest_start > oper.inlen) || ((oper.digest_start + oper.digest_len) > oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: bad digest length\n"));
- err = -EINVAL;
- goto error_cleanup;
- }
-
- digest_tcfg.next = cop->tfrm_op.tfrm_cfg;
- cop->tfrm_op.tfrm_cfg = &digest_tcfg;
- }
- if (oper.do_csum){
- csum_tcfg.tid = CRYPTOCOP_IOCTL_CSUM_TID;
- csum_tcfg.inject_ix = digest_length;
- ciph_tcfg.inject_ix += 2;
-
- if ((oper.csum_start < 0) || (oper.csum_len <= 0) || (oper.csum_start > oper.inlen) || ((oper.csum_start + oper.csum_len) > oper.inlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: bad csum length\n"));
- kfree(cop);
- kfree(jc);
- return -EINVAL;
- }
-
- csum_tcfg.next = cop->tfrm_op.tfrm_cfg;
- cop->tfrm_op.tfrm_cfg = &csum_tcfg;
- }
-
- prev_ix = first_cfg_change_ix(&oper);
- if (prev_ix > oper.inlen) {
- DEBUG_API(printk("cryptocop_ioctl_process: length mismatch\n"));
- nooutpages = noinpages = 0;
- err = -EINVAL;
- goto error_cleanup;
- }
- DEBUG(printk("cryptocop_ioctl_process: inlen=%d, cipher_outlen=%d\n", oper.inlen, oper.cipher_outlen));
-
- /* Map user pages for in and out data of the operation. */
- noinpages = (((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK) + oper.inlen - 1 - prev_ix + ~PAGE_MASK) >> PAGE_SHIFT;
- DEBUG(printk("cryptocop_ioctl_process: noinpages=%d\n", noinpages));
- inpages = kmalloc(noinpages * sizeof(struct page*), GFP_KERNEL);
- if (!inpages){
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc inpages\n"));
- nooutpages = noinpages = 0;
- err = -ENOMEM;
- goto error_cleanup;
- }
- if (oper.do_cipher){
- nooutpages = (((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) + oper.cipher_outlen - 1 + ~PAGE_MASK) >> PAGE_SHIFT;
- DEBUG(printk("cryptocop_ioctl_process: nooutpages=%d\n", nooutpages));
- outpages = kmalloc(nooutpages * sizeof(struct page*), GFP_KERNEL);
- if (!outpages){
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc outpages\n"));
- nooutpages = noinpages = 0;
- err = -ENOMEM;
- goto error_cleanup;
- }
- }
-
- err = get_user_pages_fast((unsigned long)(oper.indata + prev_ix),
- noinpages,
- false, /* read access only for in data */
- inpages);
-
- if (err < 0) {
- nooutpages = noinpages = 0;
- DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages indata\n"));
- goto error_cleanup;
- }
- noinpages = err;
- if (oper.do_cipher) {
- err = get_user_pages_fast((unsigned long)oper.cipher_outdata,
- nooutpages,
- true, /* write access for out data */
- outpages);
- if (err < 0) {
- nooutpages = 0;
- DEBUG_API(printk("cryptocop_ioctl_process: get_user_pages outdata\n"));
- goto error_cleanup;
- }
- nooutpages = err;
- }
-
- /* Add 6 to nooutpages to make room for possibly inserted buffers for storing digest and
- * csum output and splits when units are (dis-)connected. */
- cop->tfrm_op.indata = kmalloc((noinpages) * sizeof(struct iovec), GFP_KERNEL);
- cop->tfrm_op.outdata = kmalloc((6 + nooutpages) * sizeof(struct iovec), GFP_KERNEL);
- if (!cop->tfrm_op.indata || !cop->tfrm_op.outdata) {
- DEBUG_API(printk("cryptocop_ioctl_process: kmalloc iovecs\n"));
- err = -ENOMEM;
- goto error_cleanup;
- }
-
- cop->tfrm_op.inlen = oper.inlen - prev_ix;
- cop->tfrm_op.outlen = 0;
- if (oper.do_cipher) cop->tfrm_op.outlen += oper.cipher_outlen;
- if (oper.do_digest) cop->tfrm_op.outlen += digest_length;
- if (oper.do_csum) cop->tfrm_op.outlen += 2;
-
- /* Setup the in iovecs. */
- cop->tfrm_op.incount = noinpages;
- if (noinpages > 1){
- size_t tmplen = cop->tfrm_op.inlen;
-
- cop->tfrm_op.indata[0].iov_len = PAGE_SIZE - ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
- cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
- tmplen -= cop->tfrm_op.indata[0].iov_len;
- for (i = 1; i<noinpages; i++){
- cop->tfrm_op.indata[i].iov_len = tmplen < PAGE_SIZE ? tmplen : PAGE_SIZE;
- cop->tfrm_op.indata[i].iov_base = (unsigned char*)page_address(inpages[i]);
- tmplen -= PAGE_SIZE;
- }
- } else {
- cop->tfrm_op.indata[0].iov_len = oper.inlen - prev_ix;
- cop->tfrm_op.indata[0].iov_base = (unsigned char*)page_address(inpages[0]) + ((unsigned long int)(oper.indata + prev_ix) & ~PAGE_MASK);
- }
-
- iovlen = nooutpages + 6;
- pageoffset = oper.do_cipher ? ((unsigned long int)oper.cipher_outdata & ~PAGE_MASK) : 0;
-
- next_ix = next_cfg_change_ix(&oper, prev_ix);
- if (prev_ix == next_ix){
- DEBUG_API(printk("cryptocop_ioctl_process: length configuration broken.\n"));
- err = -EINVAL; /* This should be impossible barring bugs. */
- goto error_cleanup;
- }
- while (prev_ix != next_ix){
- end_digest = end_csum = cipher_active = digest_active = csum_active = 0;
- descs[desc_ix].cfg = NULL;
- descs[desc_ix].length = next_ix - prev_ix;
-
- if (oper.do_cipher && (oper.cipher_start < next_ix) && (prev_ix < (oper.cipher_start + oper.cipher_len))) {
- dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CIPHER_TID;
- dcfgs[dcfg_ix].src = cryptocop_source_dma;
- cipher_active = 1;
-
- if (next_ix == (oper.cipher_start + oper.cipher_len)){
- cipher_done = 1;
- dcfgs[dcfg_ix].last = 1;
- } else {
- dcfgs[dcfg_ix].last = 0;
- }
- dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
- descs[desc_ix].cfg = &dcfgs[dcfg_ix];
- ++dcfg_ix;
- }
- if (oper.do_digest && (oper.digest_start < next_ix) && (prev_ix < (oper.digest_start + oper.digest_len))) {
- digest_active = 1;
- dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_DIGEST_TID;
- dcfgs[dcfg_ix].src = cryptocop_source_dma;
- if (next_ix == (oper.digest_start + oper.digest_len)){
- assert(!digest_done);
- digest_done = 1;
- dcfgs[dcfg_ix].last = 1;
- } else {
- dcfgs[dcfg_ix].last = 0;
- }
- dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
- descs[desc_ix].cfg = &dcfgs[dcfg_ix];
- ++dcfg_ix;
- }
- if (oper.do_csum && (oper.csum_start < next_ix) && (prev_ix < (oper.csum_start + oper.csum_len))){
- csum_active = 1;
- dcfgs[dcfg_ix].tid = CRYPTOCOP_IOCTL_CSUM_TID;
- dcfgs[dcfg_ix].src = cryptocop_source_dma;
- if (next_ix == (oper.csum_start + oper.csum_len)){
- csum_done = 1;
- dcfgs[dcfg_ix].last = 1;
- } else {
- dcfgs[dcfg_ix].last = 0;
- }
- dcfgs[dcfg_ix].next = descs[desc_ix].cfg;
- descs[desc_ix].cfg = &dcfgs[dcfg_ix];
- ++dcfg_ix;
- }
- if (!descs[desc_ix].cfg){
- DEBUG_API(printk("cryptocop_ioctl_process: data segment %d (%d to %d) had no active transforms\n", desc_ix, prev_ix, next_ix));
- err = -EINVAL;
- goto error_cleanup;
- }
- descs[desc_ix].next = &(descs[desc_ix]) + 1;
- ++desc_ix;
- prev_ix = next_ix;
- next_ix = next_cfg_change_ix(&oper, prev_ix);
- }
- if (desc_ix > 0){
- descs[desc_ix-1].next = NULL;
- } else {
- descs[0].next = NULL;
- }
- if (oper.do_digest) {
- DEBUG(printk("cryptocop_ioctl_process: mapping %d byte digest output to iovec %d\n", digest_length, iovix));
- /* Add outdata iovec, length == <length of type of digest> */
- cop->tfrm_op.outdata[iovix].iov_base = digest_result;
- cop->tfrm_op.outdata[iovix].iov_len = digest_length;
- ++iovix;
- }
- if (oper.do_csum) {
- /* Add outdata iovec, length == 2, the length of csum. */
- DEBUG(printk("cryptocop_ioctl_process: mapping 2 byte csum output to iovec %d\n", iovix));
- /* Add outdata iovec, length == <length of type of digest> */
- cop->tfrm_op.outdata[iovix].iov_base = csum_result;
- cop->tfrm_op.outdata[iovix].iov_len = 2;
- ++iovix;
- }
- if (oper.do_cipher) {
- if (!map_pages_to_iovec(cop->tfrm_op.outdata, iovlen, &iovix, outpages, nooutpages, &pageix, &pageoffset, oper.cipher_outlen)){
- DEBUG_API(printk("cryptocop_ioctl_process: failed to map pages to iovec.\n"));
- err = -ENOSYS; /* This should be impossible barring bugs. */
- goto error_cleanup;
- }
- }
- DEBUG(printk("cryptocop_ioctl_process: setting cop->tfrm_op.outcount %d\n", iovix));
- cop->tfrm_op.outcount = iovix;
- assert(iovix <= (nooutpages + 6));
-
- cop->sid = oper.ses_id;
- cop->tfrm_op.desc = &descs[0];
-
- DEBUG(printk("cryptocop_ioctl_process: inserting job, cb_data=0x%p\n", cop->cb_data));
-
- if ((err = cryptocop_job_queue_insert_user_job(cop)) != 0) {
- DEBUG_API(printk("cryptocop_ioctl_process: insert job %d\n", err));
- err = -EINVAL;
- goto error_cleanup;
- }
-
- DEBUG(printk("cryptocop_ioctl_process: begin wait for result\n"));
-
- wait_event(cryptocop_ioc_process_wq, (jc->processed != 0));
- DEBUG(printk("cryptocop_ioctl_process: end wait for result\n"));
- if (!jc->processed){
- printk(KERN_WARNING "cryptocop_ioctl_process: job not processed at completion\n");
- err = -EIO;
- goto error_cleanup;
- }
-
- /* Job process done. Cipher output should already be correct in job so no post processing of outdata. */
- DEBUG(printk("cryptocop_ioctl_process: operation_status = %d\n", cop->operation_status));
- if (cop->operation_status == 0){
- if (oper.do_digest){
- DEBUG(printk("cryptocop_ioctl_process: copy %d bytes digest to user\n", digest_length));
- err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, digest), digest_result, digest_length);
- if (0 != err){
- DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, digest length %d, err %d\n", digest_length, err));
- err = -EFAULT;
- goto error_cleanup;
- }
- }
- if (oper.do_csum){
- DEBUG(printk("cryptocop_ioctl_process: copy 2 bytes checksum to user\n"));
- err = copy_to_user((unsigned char*)crp_oper + offsetof(struct strcop_crypto_op, csum), csum_result, 2);
- if (0 != err){
- DEBUG_API(printk("cryptocop_ioctl_process: copy_to_user, csum, err %d\n", err));
- err = -EFAULT;
- goto error_cleanup;
- }
- }
- err = 0;
- } else {
- DEBUG(printk("cryptocop_ioctl_process: returning err = operation_status = %d\n", cop->operation_status));
- err = cop->operation_status;
- }
-
- error_cleanup:
- /* Release page caches. */
- for (i = 0; i < noinpages; i++){
- put_page(inpages[i]);
- }
- for (i = 0; i < nooutpages; i++){
- int spdl_err;
- /* Mark output pages dirty. */
- spdl_err = set_page_dirty_lock(outpages[i]);
- DEBUG(if (spdl_err < 0)printk("cryptocop_ioctl_process: set_page_dirty_lock returned %d\n", spdl_err));
- }
- for (i = 0; i < nooutpages; i++){
- put_page(outpages[i]);
- }
-
- kfree(digest_result);
- kfree(inpages);
- kfree(outpages);
- if (cop){
- kfree(cop->tfrm_op.indata);
- kfree(cop->tfrm_op.outdata);
- kfree(cop);
- }
- kfree(jc);
-
- DEBUG(print_lock_status());
-
- return err;
-}
-
-
-static int cryptocop_ioctl_create_session(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
-{
- cryptocop_session_id sid;
- int err;
- struct cryptocop_private *dev;
- struct strcop_session_op *sess_op = (struct strcop_session_op *)arg;
- struct strcop_session_op sop;
- struct cryptocop_transform_init *tis = NULL;
- struct cryptocop_transform_init ti_cipher = {0};
- struct cryptocop_transform_init ti_digest = {0};
- struct cryptocop_transform_init ti_csum = {0};
-
- if (!access_ok(VERIFY_WRITE, sess_op, sizeof(struct strcop_session_op)))
- return -EFAULT;
- err = copy_from_user(&sop, sess_op, sizeof(struct strcop_session_op));
- if (err) return -EFAULT;
- if (sop.cipher != cryptocop_cipher_none) {
- if (!access_ok(VERIFY_READ, sop.key, sop.keylen)) return -EFAULT;
- }
- DEBUG(printk("cryptocop_ioctl_create_session, sess_op:\n"));
-
- DEBUG(printk("\tcipher:%d\n"
- "\tcipher_mode:%d\n"
- "\tdigest:%d\n"
- "\tcsum:%d\n",
- (int)sop.cipher,
- (int)sop.cmode,
- (int)sop.digest,
- (int)sop.csum));
-
- if (sop.cipher != cryptocop_cipher_none){
- /* Init the cipher. */
- switch (sop.cipher){
- case cryptocop_cipher_des:
- ti_cipher.alg = cryptocop_alg_des;
- break;
- case cryptocop_cipher_3des:
- ti_cipher.alg = cryptocop_alg_3des;
- break;
- case cryptocop_cipher_aes:
- ti_cipher.alg = cryptocop_alg_aes;
- break;
- default:
- DEBUG_API(printk("create session, bad cipher algorithm %d\n", sop.cipher));
- return -EINVAL;
- };
- DEBUG(printk("setting cipher transform %d\n", ti_cipher.alg));
- copy_from_user(ti_cipher.key, sop.key, sop.keylen/8);
- ti_cipher.keylen = sop.keylen;
- switch (sop.cmode){
- case cryptocop_cipher_mode_cbc:
- case cryptocop_cipher_mode_ecb:
- ti_cipher.cipher_mode = sop.cmode;
- break;
- default:
- DEBUG_API(printk("create session, bad cipher mode %d\n", sop.cmode));
- return -EINVAL;
- }
- DEBUG(printk("cryptocop_ioctl_create_session: setting CBC mode %d\n", ti_cipher.cipher_mode));
- switch (sop.des3_mode){
- case cryptocop_3des_eee:
- case cryptocop_3des_eed:
- case cryptocop_3des_ede:
- case cryptocop_3des_edd:
- case cryptocop_3des_dee:
- case cryptocop_3des_ded:
- case cryptocop_3des_dde:
- case cryptocop_3des_ddd:
- ti_cipher.tdes_mode = sop.des3_mode;
- break;
- default:
- DEBUG_API(printk("create session, bad 3DES mode %d\n", sop.des3_mode));
- return -EINVAL;
- }
- ti_cipher.tid = CRYPTOCOP_IOCTL_CIPHER_TID;
- ti_cipher.next = tis;
- tis = &ti_cipher;
- } /* if (sop.cipher != cryptocop_cipher_none) */
- if (sop.digest != cryptocop_digest_none){
- DEBUG(printk("setting digest transform\n"));
- switch (sop.digest){
- case cryptocop_digest_md5:
- ti_digest.alg = cryptocop_alg_md5;
- break;
- case cryptocop_digest_sha1:
- ti_digest.alg = cryptocop_alg_sha1;
- break;
- default:
- DEBUG_API(printk("create session, bad digest algorithm %d\n", sop.digest));
- return -EINVAL;
- }
- ti_digest.tid = CRYPTOCOP_IOCTL_DIGEST_TID;
- ti_digest.next = tis;
- tis = &ti_digest;
- } /* if (sop.digest != cryptocop_digest_none) */
- if (sop.csum != cryptocop_csum_none){
- DEBUG(printk("setting csum transform\n"));
- switch (sop.csum){
- case cryptocop_csum_le:
- case cryptocop_csum_be:
- ti_csum.csum_mode = sop.csum;
- break;
- default:
- DEBUG_API(printk("create session, bad checksum algorithm %d\n", sop.csum));
- return -EINVAL;
- }
- ti_csum.alg = cryptocop_alg_csum;
- ti_csum.tid = CRYPTOCOP_IOCTL_CSUM_TID;
- ti_csum.next = tis;
- tis = &ti_csum;
- } /* (sop.csum != cryptocop_csum_none) */
- dev = kmalloc(sizeof(struct cryptocop_private), GFP_KERNEL);
- if (!dev){
- DEBUG_API(printk("create session, alloc dev\n"));
- return -ENOMEM;
- }
-
- err = cryptocop_new_session(&sid, tis, GFP_KERNEL);
- DEBUG({ if (err) printk("create session, cryptocop_new_session %d\n", err);});
-
- if (err) {
- kfree(dev);
- return err;
- }
- sess_op->ses_id = sid;
- dev->sid = sid;
- dev->next = filp->private_data;
- filp->private_data = dev;
-
- return 0;
-}
-
-static long cryptocop_ioctl_unlocked(struct inode *inode,
- struct file *filp, unsigned int cmd, unsigned long arg)
-{
- int err = 0;
- if (_IOC_TYPE(cmd) != ETRAXCRYPTOCOP_IOCTYPE) {
- DEBUG_API(printk("cryptocop_ioctl: wrong type\n"));
- return -ENOTTY;
- }
- if (_IOC_NR(cmd) > CRYPTOCOP_IO_MAXNR){
- return -ENOTTY;
- }
- /* Access check of the argument. Some commands, e.g. create session and process op,
- needs additional checks. Those are handled in the command handling functions. */
- if (_IOC_DIR(cmd) & _IOC_READ)
- err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
- else if (_IOC_DIR(cmd) & _IOC_WRITE)
- err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
- if (err) return -EFAULT;
-
- switch (cmd) {
- case CRYPTOCOP_IO_CREATE_SESSION:
- return cryptocop_ioctl_create_session(inode, filp, cmd, arg);
- case CRYPTOCOP_IO_CLOSE_SESSION:
- return cryptocop_ioctl_close_session(inode, filp, cmd, arg);
- case CRYPTOCOP_IO_PROCESS_OP:
- return cryptocop_ioctl_process(inode, filp, cmd, arg);
- default:
- DEBUG_API(printk("cryptocop_ioctl: unknown command\n"));
- return -ENOTTY;
- }
- return 0;
-}
-
-static long
-cryptocop_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
- long ret;
-
- mutex_lock(&cryptocop_mutex);
- ret = cryptocop_ioctl_unlocked(file_inode(filp), filp, cmd, arg);
- mutex_unlock(&cryptocop_mutex);
-
- return ret;
-}
-
-
-#ifdef LDEBUG
-static void print_dma_descriptors(struct cryptocop_int_operation *iop)
-{
- struct cryptocop_dma_desc *cdesc_out = iop->cdesc_out;
- struct cryptocop_dma_desc *cdesc_in = iop->cdesc_in;
- int i;
-
- printk("print_dma_descriptors start\n");
-
- printk("iop:\n");
- printk("\tsid: 0x%llx\n", iop->sid);
-
- printk("\tcdesc_out: 0x%p\n", iop->cdesc_out);
- printk("\tcdesc_in: 0x%p\n", iop->cdesc_in);
- printk("\tddesc_out: 0x%p\n", iop->ddesc_out);
- printk("\tddesc_in: 0x%p\n", iop->ddesc_in);
-
- printk("\niop->ctx_out: 0x%p phys: 0x%p\n", &iop->ctx_out, (char*)virt_to_phys(&iop->ctx_out));
- printk("\tnext: 0x%p\n"
- "\tsaved_data: 0x%p\n"
- "\tsaved_data_buf: 0x%p\n",
- iop->ctx_out.next,
- iop->ctx_out.saved_data,
- iop->ctx_out.saved_data_buf);
-
- printk("\niop->ctx_in: 0x%p phys: 0x%p\n", &iop->ctx_in, (char*)virt_to_phys(&iop->ctx_in));
- printk("\tnext: 0x%p\n"
- "\tsaved_data: 0x%p\n"
- "\tsaved_data_buf: 0x%p\n",
- iop->ctx_in.next,
- iop->ctx_in.saved_data,
- iop->ctx_in.saved_data_buf);
-
- i = 0;
- while (cdesc_out) {
- dma_descr_data *td;
- printk("cdesc_out %d, desc=0x%p\n", i, cdesc_out->dma_descr);
- printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_out->dma_descr));
- td = cdesc_out->dma_descr;
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- td->buf,
- td->after,
- td->md,
- td->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- td->wait,
- td->eol,
- td->out_eop,
- td->in_eop,
- td->intr);
- cdesc_out = cdesc_out->next;
- i++;
- }
- i = 0;
- while (cdesc_in) {
- dma_descr_data *td;
- printk("cdesc_in %d, desc=0x%p\n", i, cdesc_in->dma_descr);
- printk("\n\tvirt_to_phys(desc): 0x%p\n", (char*)virt_to_phys(cdesc_in->dma_descr));
- td = cdesc_in->dma_descr;
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- td->buf,
- td->after,
- td->md,
- td->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- td->wait,
- td->eol,
- td->out_eop,
- td->in_eop,
- td->intr);
- cdesc_in = cdesc_in->next;
- i++;
- }
-
- printk("print_dma_descriptors end\n");
-}
-
-
-static void print_strcop_crypto_op(struct strcop_crypto_op *cop)
-{
- printk("print_strcop_crypto_op, 0x%p\n", cop);
-
- /* Indata. */
- printk("indata=0x%p\n"
- "inlen=%d\n"
- "do_cipher=%d\n"
- "decrypt=%d\n"
- "cipher_explicit=%d\n"
- "cipher_start=%d\n"
- "cipher_len=%d\n"
- "outdata=0x%p\n"
- "outlen=%d\n",
- cop->indata,
- cop->inlen,
- cop->do_cipher,
- cop->decrypt,
- cop->cipher_explicit,
- cop->cipher_start,
- cop->cipher_len,
- cop->cipher_outdata,
- cop->cipher_outlen);
-
- printk("do_digest=%d\n"
- "digest_start=%d\n"
- "digest_len=%d\n",
- cop->do_digest,
- cop->digest_start,
- cop->digest_len);
-
- printk("do_csum=%d\n"
- "csum_start=%d\n"
- "csum_len=%d\n",
- cop->do_csum,
- cop->csum_start,
- cop->csum_len);
-}
-
-static void print_cryptocop_operation(struct cryptocop_operation *cop)
-{
- struct cryptocop_desc *d;
- struct cryptocop_tfrm_cfg *tc;
- struct cryptocop_desc_cfg *dc;
- int i;
-
- printk("print_cryptocop_operation, cop=0x%p\n\n", cop);
- printk("sid: %lld\n", cop->sid);
- printk("operation_status=%d\n"
- "use_dmalists=%d\n"
- "in_interrupt=%d\n"
- "fast_callback=%d\n",
- cop->operation_status,
- cop->use_dmalists,
- cop->in_interrupt,
- cop->fast_callback);
-
- if (cop->use_dmalists){
- print_user_dma_lists(&cop->list_op);
- } else {
- printk("cop->tfrm_op\n"
- "tfrm_cfg=0x%p\n"
- "desc=0x%p\n"
- "indata=0x%p\n"
- "incount=%d\n"
- "inlen=%d\n"
- "outdata=0x%p\n"
- "outcount=%d\n"
- "outlen=%d\n\n",
- cop->tfrm_op.tfrm_cfg,
- cop->tfrm_op.desc,
- cop->tfrm_op.indata,
- cop->tfrm_op.incount,
- cop->tfrm_op.inlen,
- cop->tfrm_op.outdata,
- cop->tfrm_op.outcount,
- cop->tfrm_op.outlen);
-
- tc = cop->tfrm_op.tfrm_cfg;
- while (tc){
- printk("tfrm_cfg, 0x%p\n"
- "tid=%d\n"
- "flags=%d\n"
- "inject_ix=%d\n"
- "next=0x%p\n",
- tc,
- tc->tid,
- tc->flags,
- tc->inject_ix,
- tc->next);
- tc = tc->next;
- }
- d = cop->tfrm_op.desc;
- while (d){
- printk("\n======================desc, 0x%p\n"
- "length=%d\n"
- "cfg=0x%p\n"
- "next=0x%p\n",
- d,
- d->length,
- d->cfg,
- d->next);
- dc = d->cfg;
- while (dc){
- printk("=========desc_cfg, 0x%p\n"
- "tid=%d\n"
- "src=%d\n"
- "last=%d\n"
- "next=0x%p\n",
- dc,
- dc->tid,
- dc->src,
- dc->last,
- dc->next);
- dc = dc->next;
- }
- d = d->next;
- }
- printk("\n====iniov\n");
- for (i = 0; i < cop->tfrm_op.incount; i++){
- printk("indata[%d]\n"
- "base=0x%p\n"
- "len=%d\n",
- i,
- cop->tfrm_op.indata[i].iov_base,
- cop->tfrm_op.indata[i].iov_len);
- }
- printk("\n====outiov\n");
- for (i = 0; i < cop->tfrm_op.outcount; i++){
- printk("outdata[%d]\n"
- "base=0x%p\n"
- "len=%d\n",
- i,
- cop->tfrm_op.outdata[i].iov_base,
- cop->tfrm_op.outdata[i].iov_len);
- }
- }
- printk("------------end print_cryptocop_operation\n");
-}
-
-
-static void print_user_dma_lists(struct cryptocop_dma_list_operation *dma_op)
-{
- dma_descr_data *dd;
- int i;
-
- printk("print_user_dma_lists, dma_op=0x%p\n", dma_op);
-
- printk("out_data_buf = 0x%p, phys_to_virt(out_data_buf) = 0x%p\n", dma_op->out_data_buf, phys_to_virt((unsigned long int)dma_op->out_data_buf));
- printk("in_data_buf = 0x%p, phys_to_virt(in_data_buf) = 0x%p\n", dma_op->in_data_buf, phys_to_virt((unsigned long int)dma_op->in_data_buf));
-
- printk("##############outlist\n");
- dd = phys_to_virt((unsigned long int)dma_op->outlist);
- i = 0;
- while (dd != NULL) {
- printk("#%d phys_to_virt(desc) 0x%p\n", i, dd);
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- dd->buf,
- dd->after,
- dd->md,
- dd->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- dd->wait,
- dd->eol,
- dd->out_eop,
- dd->in_eop,
- dd->intr);
- if (dd->eol)
- dd = NULL;
- else
- dd = phys_to_virt((unsigned long int)dd->next);
- ++i;
- }
-
- printk("##############inlist\n");
- dd = phys_to_virt((unsigned long int)dma_op->inlist);
- i = 0;
- while (dd != NULL) {
- printk("#%d phys_to_virt(desc) 0x%p\n", i, dd);
- printk("\n\tbuf: 0x%p\n"
- "\tafter: 0x%p\n"
- "\tmd: 0x%04x\n"
- "\tnext: 0x%p\n",
- dd->buf,
- dd->after,
- dd->md,
- dd->next);
- printk("flags:\n"
- "\twait:\t%d\n"
- "\teol:\t%d\n"
- "\touteop:\t%d\n"
- "\tineop:\t%d\n"
- "\tintr:\t%d\n",
- dd->wait,
- dd->eol,
- dd->out_eop,
- dd->in_eop,
- dd->intr);
- if (dd->eol)
- dd = NULL;
- else
- dd = phys_to_virt((unsigned long int)dd->next);
- ++i;
- }
-}
-
-
-static void print_lock_status(void)
-{
- printk("**********************print_lock_status\n");
- printk("cryptocop_completed_jobs_lock %d\n", spin_is_locked(&cryptocop_completed_jobs_lock));
- printk("cryptocop_job_queue_lock %d\n", spin_is_locked(&cryptocop_job_queue_lock));
- printk("descr_pool_lock %d\n", spin_is_locked(&descr_pool_lock));
- printk("cryptocop_sessions_lock %d\n", spin_is_locked(cryptocop_sessions_lock));
- printk("running_job_lock %d\n", spin_is_locked(running_job_lock));
- printk("cryptocop_process_lock %d\n", spin_is_locked(cryptocop_process_lock));
-}
-#endif /* LDEBUG */
-
-
-static const char cryptocop_name[] = "ETRAX FS stream co-processor";
-
-static int init_stream_coprocessor(void)
-{
- int err;
- int i;
- static int initialized = 0;
-
- if (initialized)
- return 0;
-
- initialized = 1;
-
- printk("ETRAX FS stream co-processor driver v0.01, (c) 2003 Axis Communications AB\n");
-
- err = register_chrdev(CRYPTOCOP_MAJOR, cryptocop_name, &cryptocop_fops);
- if (err < 0) {
- printk(KERN_ERR "stream co-processor: could not get major number.\n");
- return err;
- }
-
- err = init_cryptocop();
- if (err) {
- (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name);
- return err;
- }
- err = cryptocop_job_queue_init();
- if (err) {
- release_cryptocop();
- (void)unregister_chrdev(CRYPTOCOP_MAJOR, cryptocop_name);
- return err;
- }
- /* Init the descriptor pool. */
- for (i = 0; i < CRYPTOCOP_DESCRIPTOR_POOL_SIZE - 1; i++) {
- descr_pool[i].from_pool = 1;
- descr_pool[i].next = &descr_pool[i + 1];
- }
- descr_pool[i].from_pool = 1;
- descr_pool[i].next = NULL;
- descr_pool_free_list = &descr_pool[0];
- descr_pool_no_free = CRYPTOCOP_DESCRIPTOR_POOL_SIZE;
-
- spin_lock_init(&cryptocop_completed_jobs_lock);
- spin_lock_init(&cryptocop_job_queue_lock);
- spin_lock_init(&descr_pool_lock);
- spin_lock_init(&cryptocop_sessions_lock);
- spin_lock_init(&running_job_lock);
- spin_lock_init(&cryptocop_process_lock);
-
- cryptocop_sessions = NULL;
- next_sid = 1;
-
- cryptocop_running_job = NULL;
-
- printk("stream co-processor: init done.\n");
- return 0;
-}
-
-static void __exit exit_stream_coprocessor(void)
-{
- release_cryptocop();
- cryptocop_job_queue_close();
-}
-
-module_init(init_stream_coprocessor);
-module_exit(exit_stream_coprocessor);
-
diff --git a/arch/cris/arch-v32/drivers/iop_fw_load.c b/arch/cris/arch-v32/drivers/iop_fw_load.c
deleted file mode 100644
index 2f8ea0f7a63c..000000000000
--- a/arch/cris/arch-v32/drivers/iop_fw_load.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * Firmware loader for ETRAX FS IO-Processor
- *
- * Copyright (C) 2004 Axis Communications AB
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/firmware.h>
-
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/iop/iop_reg_space.h>
-#include <hwregs/iop/iop_mpu_macros.h>
-#include <hwregs/iop/iop_mpu_defs.h>
-#include <hwregs/iop/iop_spu_defs.h>
-#include <hwregs/iop/iop_sw_cpu_defs.h>
-
-#define IOP_TIMEOUT 100
-
-#error "This driver is broken with regard to its driver core usage."
-#error "Please contact <greg@kroah.com> for details on how to fix it properly."
-
-static struct device iop_spu_device[2] = {
- { .init_name = "iop-spu0", },
- { .init_name = "iop-spu1", },
-};
-
-static struct device iop_mpu_device = {
- .init_name = "iop-mpu",
-};
-
-static int wait_mpu_idle(void)
-{
- reg_iop_mpu_r_stat mpu_stat;
- unsigned int timeout = IOP_TIMEOUT;
-
- do {
- mpu_stat = REG_RD(iop_mpu, regi_iop_mpu, r_stat);
- } while (mpu_stat.instr_reg_busy == regk_iop_mpu_yes && --timeout > 0);
- if (timeout == 0) {
- printk(KERN_ERR "Timeout waiting for MPU to be idle\n");
- return -EBUSY;
- }
- return 0;
-}
-
-int iop_fw_load_spu(const unsigned char *fw_name, unsigned int spu_inst)
-{
- reg_iop_sw_cpu_rw_mc_ctrl mc_ctrl = {
- .wr_spu0_mem = regk_iop_sw_cpu_no,
- .wr_spu1_mem = regk_iop_sw_cpu_no,
- .size = 4,
- .cmd = regk_iop_sw_cpu_reg_copy,
- .keep_owner = regk_iop_sw_cpu_yes
- };
- reg_iop_spu_rw_ctrl spu_ctrl = {
- .en = regk_iop_spu_no,
- .fsm = regk_iop_spu_no,
- };
- reg_iop_sw_cpu_r_mc_stat mc_stat;
- const struct firmware *fw_entry;
- u32 *data;
- unsigned int timeout;
- int retval, i;
-
- if (spu_inst > 1)
- return -ENODEV;
-
- /* get firmware */
- retval = request_firmware(&fw_entry,
- fw_name,
- &iop_spu_device[spu_inst]);
- if (retval != 0)
- {
- printk(KERN_ERR
- "iop_load_spu: Failed to load firmware \"%s\"\n",
- fw_name);
- return retval;
- }
- data = (u32 *) fw_entry->data;
-
- /* acquire ownership of memory controller */
- switch (spu_inst) {
- case 0:
- mc_ctrl.wr_spu0_mem = regk_iop_sw_cpu_yes;
- REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl);
- break;
- case 1:
- mc_ctrl.wr_spu1_mem = regk_iop_sw_cpu_yes;
- REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl);
- break;
- }
- timeout = IOP_TIMEOUT;
- do {
- REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl);
- mc_stat = REG_RD(iop_sw_cpu, regi_iop_sw_cpu, r_mc_stat);
- } while (mc_stat.owned_by_cpu == regk_iop_sw_cpu_no && --timeout > 0);
- if (timeout == 0) {
- printk(KERN_ERR "Timeout waiting to acquire MC\n");
- retval = -EBUSY;
- goto out;
- }
-
- /* write to SPU memory */
- for (i = 0; i < (fw_entry->size/4); i++) {
- switch (spu_inst) {
- case 0:
- REG_WR_INT(iop_spu, regi_iop_spu0, rw_seq_pc, (i*4));
- break;
- case 1:
- REG_WR_INT(iop_spu, regi_iop_spu1, rw_seq_pc, (i*4));
- break;
- }
- REG_WR_INT(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_data, *data);
- data++;
- }
-
- /* release ownership of memory controller */
- (void) REG_RD(iop_sw_cpu, regi_iop_sw_cpu, rs_mc_data);
-
- out:
- release_firmware(fw_entry);
- return retval;
-}
-
-int iop_fw_load_mpu(unsigned char *fw_name)
-{
- const unsigned int start_addr = 0;
- reg_iop_mpu_rw_ctrl mpu_ctrl;
- const struct firmware *fw_entry;
- u32 *data;
- int retval, i;
-
- /* get firmware */
- retval = request_firmware(&fw_entry, fw_name, &iop_mpu_device);
- if (retval != 0)
- {
- printk(KERN_ERR
- "iop_load_spu: Failed to load firmware \"%s\"\n",
- fw_name);
- return retval;
- }
- data = (u32 *) fw_entry->data;
-
- /* disable MPU */
- mpu_ctrl.en = regk_iop_mpu_no;
- REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);
- /* put start address in R0 */
- REG_WR_VECT(iop_mpu, regi_iop_mpu, rw_r, 0, start_addr);
- /* write to memory by executing 'SWX i, 4, R0' for each word */
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0));
- for (i = 0; i < (fw_entry->size / 4); i++) {
- REG_WR_INT(iop_mpu, regi_iop_mpu, rw_immediate, *data);
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- data++;
- }
-
- out:
- release_firmware(fw_entry);
- return retval;
-}
-
-int iop_start_mpu(unsigned int start_addr)
-{
- reg_iop_mpu_rw_ctrl mpu_ctrl = { .en = regk_iop_mpu_yes };
- int retval;
-
- /* disable MPU */
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT());
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- /* set PC and wait for it to bite */
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- REG_WR_INT(iop_mpu, regi_iop_mpu, rw_instr, MPU_BA_I(start_addr));
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- /* make sure the MPU starts executing with interrupts disabled */
- REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI());
- if ((retval = wait_mpu_idle()) != 0)
- goto out;
- /* enable MPU */
- REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);
- out:
- return retval;
-}
-
-static int __init iop_fw_load_init(void)
-{
-#if 0
- /*
- * static struct devices can not be added directly to sysfs by ignoring
- * the driver model infrastructure. To fix this properly, please use
- * the platform_bus to register these devices to be able to properly
- * use the firmware infrastructure.
- */
- device_initialize(&iop_spu_device[0]);
- kobject_set_name(&iop_spu_device[0].kobj, "iop-spu0");
- kobject_add(&iop_spu_device[0].kobj);
- device_initialize(&iop_spu_device[1]);
- kobject_set_name(&iop_spu_device[1].kobj, "iop-spu1");
- kobject_add(&iop_spu_device[1].kobj);
- device_initialize(&iop_mpu_device);
- kobject_set_name(&iop_mpu_device.kobj, "iop-mpu");
- kobject_add(&iop_mpu_device.kobj);
-#endif
- return 0;
-}
-
-static void __exit iop_fw_load_exit(void)
-{
-}
-
-module_init(iop_fw_load_init);
-module_exit(iop_fw_load_exit);
-
-MODULE_DESCRIPTION("ETRAX FS IO-Processor Firmware Loader");
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(iop_fw_load_spu);
-EXPORT_SYMBOL(iop_fw_load_mpu);
-EXPORT_SYMBOL(iop_start_mpu);
diff --git a/arch/cris/arch-v32/drivers/mach-a3/Makefile b/arch/cris/arch-v32/drivers/mach-a3/Makefile
deleted file mode 100644
index 59028d0b981c..000000000000
--- a/arch/cris/arch-v32/drivers/mach-a3/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
diff --git a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c b/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
deleted file mode 100644
index 925a98eb6d68..000000000000
--- a/arch/cris/arch-v32/drivers/mach-a3/nandflash.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * arch/cris/arch-v32/drivers/nandflash.c
- *
- * Copyright (c) 2007
- *
- * Derived from drivers/mtd/nand/spia.c
- * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <arch/memmap.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/pio_defs.h>
-#include <pinmux.h>
-#include <asm/io.h>
-
-#define MANUAL_ALE_CLE_CONTROL 1
-
-#define regf_ALE a0
-#define regf_CLE a1
-#define regf_NCE ce0_n
-
-#define CLE_BIT 10
-#define ALE_BIT 11
-#define CE_BIT 12
-
-struct mtd_info_wrapper {
- struct nand_chip chip;
-};
-
-/* Bitmask for control pins */
-#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
-
-static struct mtd_info *crisv32_mtd;
-/*
- * hardware specific access to control-lines
- */
-static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- unsigned long flags;
- reg_pio_rw_dout dout;
- struct nand_chip *this = mtd_to_nand(mtd);
-
- local_irq_save(flags);
-
- /* control bits change */
- if (ctrl & NAND_CTRL_CHANGE) {
- dout = REG_RD(pio, regi_pio, rw_dout);
- dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
-
-#if !MANUAL_ALE_CLE_CONTROL
- if (ctrl & NAND_ALE) {
- /* A0 = ALE high */
- this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
- regi_pio, rw_io_access1);
- } else if (ctrl & NAND_CLE) {
- /* A1 = CLE high */
- this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
- regi_pio, rw_io_access2);
- } else {
- /* A1 = CLE and A0 = ALE low */
- this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
- regi_pio, rw_io_access0);
- }
-#else
-
- dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
- dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
-#endif
- REG_WR(pio, regi_pio, rw_dout, dout);
- }
-
- /* command to chip */
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-
- local_irq_restore(flags);
-}
-
-/*
-* read device ready pin
-*/
-static int crisv32_device_ready(struct mtd_info *mtd)
-{
- reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
- return din.rdy;
-}
-
-/*
- * Main initialization routine
- */
-struct mtd_info *__init crisv32_nand_flash_probe(void)
-{
- void __iomem *read_cs;
- void __iomem *write_cs;
-
- struct mtd_info_wrapper *wrapper;
- struct nand_chip *this;
- int err = 0;
-
- reg_pio_rw_man_ctrl man_ctrl = {
- .regf_NCE = regk_pio_yes,
-#if MANUAL_ALE_CLE_CONTROL
- .regf_ALE = regk_pio_yes,
- .regf_CLE = regk_pio_yes
-#endif
- };
- reg_pio_rw_oe oe = {
- .regf_NCE = regk_pio_yes,
-#if MANUAL_ALE_CLE_CONTROL
- .regf_ALE = regk_pio_yes,
- .regf_CLE = regk_pio_yes
-#endif
- };
- reg_pio_rw_dout dout = { .regf_NCE = 1 };
-
- /* Allocate pio pins to pio */
- crisv32_pinmux_alloc_fixed(pinmux_pio);
- /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
- REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
- REG_WR(pio, regi_pio, rw_dout, dout);
- REG_WR(pio, regi_pio, rw_oe, oe);
-
- /* Allocate memory for MTD device structure and private data */
- wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
- if (!wrapper) {
- printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
- "device structure.\n");
- err = -ENOMEM;
- return NULL;
- }
-
- read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
- rw_io_access0);
-
- /* Get pointer to private data */
- this = &wrapper->chip;
- crisv32_mtd = nand_to_mtd(this);
-
- /* Set address of NAND IO lines */
- this->IO_ADDR_R = read_cs;
- this->IO_ADDR_W = write_cs;
- this->cmd_ctrl = crisv32_hwcontrol;
- this->dev_ready = crisv32_device_ready;
- /* 20 us command delay time */
- this->chip_delay = 20;
- this->ecc.mode = NAND_ECC_SOFT;
- this->ecc.algo = NAND_ECC_HAMMING;
-
- /* Enable the following for a flash based bad block table */
- /* this->bbt_options = NAND_BBT_USE_FLASH; */
-
- /* Scan to find existence of the device */
- if (nand_scan(crisv32_mtd, 1)) {
- err = -ENXIO;
- goto out_mtd;
- }
-
- return crisv32_mtd;
-
-out_mtd:
- kfree(wrapper);
- return NULL;
-}
-
diff --git a/arch/cris/arch-v32/drivers/mach-fs/Makefile b/arch/cris/arch-v32/drivers/mach-fs/Makefile
deleted file mode 100644
index 59028d0b981c..000000000000
--- a/arch/cris/arch-v32/drivers/mach-fs/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for Etrax-specific drivers
-#
-
-obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
diff --git a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c b/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
deleted file mode 100644
index 53b56a429dde..000000000000
--- a/arch/cris/arch-v32/drivers/mach-fs/nandflash.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * arch/cris/arch-v32/drivers/nandflash.c
- *
- * Copyright (c) 2004
- *
- * Derived from drivers/mtd/nand/spia.c
- * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <arch/memmap.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/gio_defs.h>
-#include <hwregs/bif_core_defs.h>
-#include <asm/io.h>
-
-#define CE_BIT 4
-#define CLE_BIT 5
-#define ALE_BIT 6
-#define BY_BIT 7
-
-struct mtd_info_wrapper {
- struct nand_chip chip;
-};
-
-/* Bitmask for control pins */
-#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
-
-/* Bitmask for mtd nand control bits */
-#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
-
-
-static struct mtd_info *crisv32_mtd;
-/*
- * hardware specific access to control-lines
- */
-static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
- unsigned int ctrl)
-{
- unsigned long flags;
- reg_gio_rw_pa_dout dout;
- struct nand_chip *this = mtd_to_nand(mtd);
-
- local_irq_save(flags);
-
- /* control bits change */
- if (ctrl & NAND_CTRL_CHANGE) {
- dout = REG_RD(gio, regi_gio, rw_pa_dout);
- dout.data &= ~PIN_BITMASK;
-
-#if (CE_BIT == 4 && NAND_NCE == 1 && \
- CLE_BIT == 5 && NAND_CLE == 2 && \
- ALE_BIT == 6 && NAND_ALE == 4)
- /* Pins in same order as control bits, but shifted.
- * Optimize for this case; works for 2.6.18 */
- dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
-#else
- /* the slow way */
- if (!(ctrl & NAND_NCE))
- dout.data |= (1 << CE_BIT);
- if (ctrl & NAND_CLE)
- dout.data |= (1 << CLE_BIT);
- if (ctrl & NAND_ALE)
- dout.data |= (1 << ALE_BIT);
-#endif
- REG_WR(gio, regi_gio, rw_pa_dout, dout);
- }
-
- /* command to chip */
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-
- local_irq_restore(flags);
-}
-
-/*
-* read device ready pin
-*/
-static int crisv32_device_ready(struct mtd_info *mtd)
-{
- reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
- return ((din.data & (1 << BY_BIT)) >> BY_BIT);
-}
-
-/*
- * Main initialization routine
- */
-struct mtd_info *__init crisv32_nand_flash_probe(void)
-{
- void __iomem *read_cs;
- void __iomem *write_cs;
-
- reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core,
- rw_grp3_cfg);
- reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
- struct mtd_info_wrapper *wrapper;
- struct nand_chip *this;
- int err = 0;
-
- /* Allocate memory for MTD device structure and private data */
- wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
- if (!wrapper) {
- printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
- "device structure.\n");
- err = -ENOMEM;
- return NULL;
- }
-
- read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
- write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
-
- if (!read_cs || !write_cs) {
- printk(KERN_ERR "CRISv32 NAND ioremap failed\n");
- err = -EIO;
- goto out_mtd;
- }
-
- /* Get pointer to private data */
- this = &wrapper->chip;
- crisv32_mtd = nand_to_mtd(this);
-
- pa_oe.oe |= 1 << CE_BIT;
- pa_oe.oe |= 1 << ALE_BIT;
- pa_oe.oe |= 1 << CLE_BIT;
- pa_oe.oe &= ~(1 << BY_BIT);
- REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
-
- bif_cfg.gated_csp0 = regk_bif_core_rd;
- bif_cfg.gated_csp1 = regk_bif_core_wr;
- REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
-
- /* Set address of NAND IO lines */
- this->IO_ADDR_R = read_cs;
- this->IO_ADDR_W = write_cs;
- this->cmd_ctrl = crisv32_hwcontrol;
- this->dev_ready = crisv32_device_ready;
- /* 20 us command delay time */
- this->chip_delay = 20;
- this->ecc.mode = NAND_ECC_SOFT;
- this->ecc.algo = NAND_ECC_HAMMING;
-
- /* Enable the following for a flash based bad block table */
- /* this->bbt_options = NAND_BBT_USE_FLASH; */
-
- /* Scan to find existence of the device */
- if (nand_scan(crisv32_mtd, 1)) {
- err = -ENXIO;
- goto out_ior;
- }
-
- return crisv32_mtd;
-
-out_ior:
- iounmap((void *)read_cs);
- iounmap((void *)write_cs);
-out_mtd:
- kfree(wrapper);
- return NULL;
-}
-
diff --git a/arch/cris/arch-v32/drivers/pci/Makefile b/arch/cris/arch-v32/drivers/pci/Makefile
deleted file mode 100644
index 93c8be6170b1..000000000000
--- a/arch/cris/arch-v32/drivers/pci/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for Etrax cardbus driver
-#
-
-obj-$(CONFIG_ETRAX_CARDBUS) += bios.o
diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c
deleted file mode 100644
index 6b9e6cfaa29e..000000000000
--- a/arch/cris/arch-v32/drivers/pci/bios.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <hwregs/intr_vect.h>
-
-void pcibios_set_master(struct pci_dev *dev)
-{
- u8 lat;
- pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
- printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
-}
-
-resource_size_t
-pcibios_align_resource(void *data, const struct resource *res,
- resource_size_t size, resource_size_t align)
-{
- resource_size_t start = res->start;
-
- if ((res->flags & IORESOURCE_IO) && (start & 0x300))
- start = (start + 0x3ff) & ~0x3ff;
-
- return start;
-}
-
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for(idx=0; idx<6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
-int pcibios_enable_irq(struct pci_dev *dev)
-{
- dev->irq = EXT_INTR_VECT;
- return 0;
-}
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
- int err;
-
- if ((err = pcibios_enable_resources(dev, mask)) < 0)
- return err;
-
- if (!dev->msi_enabled)
- pcibios_enable_irq(dev);
- return 0;
-}
diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c
deleted file mode 100644
index 1b0ce8a8af16..000000000000
--- a/arch/cris/arch-v32/drivers/sync_serial.c
+++ /dev/null
@@ -1,1715 +0,0 @@
-/*
- * Simple synchronous serial port driver for ETRAX FS and ARTPEC-3.
- *
- * Copyright (c) 2005, 2008 Axis Communications AB
- * Author: Mikael Starvik
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/major.h>
-#include <linux/sched/signal.h>
-#include <linux/mutex.h>
-#include <linux/interrupt.h>
-#include <linux/poll.h>
-#include <linux/fs.h>
-#include <linux/cdev.h>
-#include <linux/device.h>
-#include <linux/wait.h>
-
-#include <asm/io.h>
-#include <mach/dma.h>
-#include <pinmux.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/sser_defs.h>
-#include <hwregs/timer_defs.h>
-#include <hwregs/dma_defs.h>
-#include <hwregs/dma.h>
-#include <hwregs/intr_vect_defs.h>
-#include <hwregs/intr_vect.h>
-#include <hwregs/reg_map.h>
-#include <asm/sync_serial.h>
-
-
-/* The receiver is a bit tricky because of the continuous stream of data.*/
-/* */
-/* Three DMA descriptors are linked together. Each DMA descriptor is */
-/* responsible for port->bufchunk of a common buffer. */
-/* */
-/* +---------------------------------------------+ */
-/* | +----------+ +----------+ +----------+ | */
-/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
-/* +----------+ +----------+ +----------+ */
-/* | | | */
-/* v v v */
-/* +-------------------------------------+ */
-/* | BUFFER | */
-/* +-------------------------------------+ */
-/* |<- data_avail ->| */
-/* readp writep */
-/* */
-/* If the application keeps up the pace readp will be right after writep.*/
-/* If the application can't keep the pace we have to throw away data. */
-/* The idea is that readp should be ready with the data pointed out by */
-/* Descr[i] when the DMA has filled in Descr[i+1]. */
-/* Otherwise we will discard */
-/* the rest of the data pointed out by Descr1 and set readp to the start */
-/* of Descr2 */
-
-/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
-/* words can be handled */
-#define IN_DESCR_SIZE SSP_INPUT_CHUNK_SIZE
-#define NBR_IN_DESCR (8*6)
-#define IN_BUFFER_SIZE (IN_DESCR_SIZE * NBR_IN_DESCR)
-
-#define NBR_OUT_DESCR 8
-#define OUT_BUFFER_SIZE (1024 * NBR_OUT_DESCR)
-
-#define DEFAULT_FRAME_RATE 0
-#define DEFAULT_WORD_RATE 7
-
-/* To be removed when we move to pure udev. */
-#define SYNC_SERIAL_MAJOR 125
-
-/* NOTE: Enabling some debug will likely cause overrun or underrun,
- * especially if manual mode is used.
- */
-#define DEBUG(x)
-#define DEBUGREAD(x)
-#define DEBUGWRITE(x)
-#define DEBUGPOLL(x)
-#define DEBUGRXINT(x)
-#define DEBUGTXINT(x)
-#define DEBUGTRDMA(x)
-#define DEBUGOUTBUF(x)
-
-enum syncser_irq_setup {
- no_irq_setup = 0,
- dma_irq_setup = 1,
- manual_irq_setup = 2,
-};
-
-struct sync_port {
- unsigned long regi_sser;
- unsigned long regi_dmain;
- unsigned long regi_dmaout;
-
- /* Interrupt vectors. */
- unsigned long dma_in_intr_vect; /* Used for DMA in. */
- unsigned long dma_out_intr_vect; /* Used for DMA out. */
- unsigned long syncser_intr_vect; /* Used when no DMA. */
-
- /* DMA number for in and out. */
- unsigned int dma_in_nbr;
- unsigned int dma_out_nbr;
-
- /* DMA owner. */
- enum dma_owner req_dma;
-
- char started; /* 1 if port has been started */
- char port_nbr; /* Port 0 or 1 */
- char busy; /* 1 if port is busy */
-
- char enabled; /* 1 if port is enabled */
- char use_dma; /* 1 if port uses dma */
- char tr_running;
-
- enum syncser_irq_setup init_irqs;
- int output;
- int input;
-
- /* Next byte to be read by application */
- unsigned char *readp;
- /* Next byte to be written by etrax */
- unsigned char *writep;
-
- unsigned int in_buffer_size;
- unsigned int in_buffer_len;
- unsigned int inbufchunk;
- /* Data buffers for in and output. */
- unsigned char out_buffer[OUT_BUFFER_SIZE] __aligned(32);
- unsigned char in_buffer[IN_BUFFER_SIZE] __aligned(32);
- unsigned char flip[IN_BUFFER_SIZE] __aligned(32);
- struct timespec timestamp[NBR_IN_DESCR];
- struct dma_descr_data *next_rx_desc;
- struct dma_descr_data *prev_rx_desc;
-
- struct timeval last_timestamp;
- int read_ts_idx;
- int write_ts_idx;
-
- /* Pointer to the first available descriptor in the ring,
- * unless active_tr_descr == catch_tr_descr and a dma
- * transfer is active */
- struct dma_descr_data *active_tr_descr;
-
- /* Pointer to the first allocated descriptor in the ring */
- struct dma_descr_data *catch_tr_descr;
-
- /* Pointer to the descriptor with the current end-of-list */
- struct dma_descr_data *prev_tr_descr;
- int full;
-
- /* Pointer to the first byte being read by DMA
- * or current position in out_buffer if not using DMA. */
- unsigned char *out_rd_ptr;
-
- /* Number of bytes currently locked for being read by DMA */
- int out_buf_count;
-
- dma_descr_context in_context __aligned(32);
- dma_descr_context out_context __aligned(32);
- dma_descr_data in_descr[NBR_IN_DESCR] __aligned(16);
- dma_descr_data out_descr[NBR_OUT_DESCR] __aligned(16);
-
- wait_queue_head_t out_wait_q;
- wait_queue_head_t in_wait_q;
-
- spinlock_t lock;
-};
-
-static DEFINE_MUTEX(sync_serial_mutex);
-static int etrax_sync_serial_init(void);
-static void initialize_port(int portnbr);
-static inline int sync_data_avail(struct sync_port *port);
-
-static int sync_serial_open(struct inode *, struct file *);
-static int sync_serial_release(struct inode *, struct file *);
-static __poll_t sync_serial_poll(struct file *filp, poll_table *wait);
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg);
-static int sync_serial_ioctl_unlocked(struct file *file,
- unsigned int cmd, unsigned long arg);
-static ssize_t sync_serial_write(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos);
-static ssize_t sync_serial_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos);
-
-#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
- (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
- defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
-#define SYNC_SER_DMA
-#else
-#define SYNC_SER_MANUAL
-#endif
-
-#ifdef SYNC_SER_DMA
-static void start_dma_out(struct sync_port *port, const char *data, int count);
-static void start_dma_in(struct sync_port *port);
-static irqreturn_t tr_interrupt(int irq, void *dev_id);
-static irqreturn_t rx_interrupt(int irq, void *dev_id);
-#endif
-#ifdef SYNC_SER_MANUAL
-static void send_word(struct sync_port *port);
-static irqreturn_t manual_interrupt(int irq, void *dev_id);
-#endif
-
-#define artpec_pinmux_alloc_fixed crisv32_pinmux_alloc_fixed
-#define artpec_request_dma crisv32_request_dma
-#define artpec_free_dma crisv32_free_dma
-
-#ifdef CONFIG_ETRAXFS
-/* ETRAX FS */
-#define DMA_OUT_NBR0 SYNC_SER0_TX_DMA_NBR
-#define DMA_IN_NBR0 SYNC_SER0_RX_DMA_NBR
-#define DMA_OUT_NBR1 SYNC_SER1_TX_DMA_NBR
-#define DMA_IN_NBR1 SYNC_SER1_RX_DMA_NBR
-#define PINMUX_SSER0 pinmux_sser0
-#define PINMUX_SSER1 pinmux_sser1
-#define SYNCSER_INST0 regi_sser0
-#define SYNCSER_INST1 regi_sser1
-#define SYNCSER_INTR_VECT0 SSER0_INTR_VECT
-#define SYNCSER_INTR_VECT1 SSER1_INTR_VECT
-#define OUT_DMA_INST0 regi_dma4
-#define IN_DMA_INST0 regi_dma5
-#define DMA_OUT_INTR_VECT0 DMA4_INTR_VECT
-#define DMA_OUT_INTR_VECT1 DMA7_INTR_VECT
-#define DMA_IN_INTR_VECT0 DMA5_INTR_VECT
-#define DMA_IN_INTR_VECT1 DMA6_INTR_VECT
-#define REQ_DMA_SYNCSER0 dma_sser0
-#define REQ_DMA_SYNCSER1 dma_sser1
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
-#define PORT1_DMA 1
-#else
-#define PORT1_DMA 0
-#endif
-#elif defined(CONFIG_CRIS_MACH_ARTPEC3)
-/* ARTPEC-3 */
-#define DMA_OUT_NBR0 SYNC_SER_TX_DMA_NBR
-#define DMA_IN_NBR0 SYNC_SER_RX_DMA_NBR
-#define PINMUX_SSER0 pinmux_sser
-#define SYNCSER_INST0 regi_sser
-#define SYNCSER_INTR_VECT0 SSER_INTR_VECT
-#define OUT_DMA_INST0 regi_dma6
-#define IN_DMA_INST0 regi_dma7
-#define DMA_OUT_INTR_VECT0 DMA6_INTR_VECT
-#define DMA_IN_INTR_VECT0 DMA7_INTR_VECT
-#define REQ_DMA_SYNCSER0 dma_sser
-#define REQ_DMA_SYNCSER1 dma_sser
-#endif
-
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
-#define PORT0_DMA 1
-#else
-#define PORT0_DMA 0
-#endif
-
-/* The ports */
-static struct sync_port ports[] = {
- {
- .regi_sser = SYNCSER_INST0,
- .regi_dmaout = OUT_DMA_INST0,
- .regi_dmain = IN_DMA_INST0,
- .use_dma = PORT0_DMA,
- .dma_in_intr_vect = DMA_IN_INTR_VECT0,
- .dma_out_intr_vect = DMA_OUT_INTR_VECT0,
- .dma_in_nbr = DMA_IN_NBR0,
- .dma_out_nbr = DMA_OUT_NBR0,
- .req_dma = REQ_DMA_SYNCSER0,
- .syncser_intr_vect = SYNCSER_INTR_VECT0,
- },
-#ifdef CONFIG_ETRAXFS
- {
- .regi_sser = SYNCSER_INST1,
- .regi_dmaout = regi_dma6,
- .regi_dmain = regi_dma7,
- .use_dma = PORT1_DMA,
- .dma_in_intr_vect = DMA_IN_INTR_VECT1,
- .dma_out_intr_vect = DMA_OUT_INTR_VECT1,
- .dma_in_nbr = DMA_IN_NBR1,
- .dma_out_nbr = DMA_OUT_NBR1,
- .req_dma = REQ_DMA_SYNCSER1,
- .syncser_intr_vect = SYNCSER_INTR_VECT1,
- },
-#endif
-};
-
-#define NBR_PORTS ARRAY_SIZE(ports)
-
-static const struct file_operations syncser_fops = {
- .owner = THIS_MODULE,
- .write = sync_serial_write,
- .read = sync_serial_read,
- .poll = sync_serial_poll,
- .unlocked_ioctl = sync_serial_ioctl,
- .open = sync_serial_open,
- .release = sync_serial_release,
- .llseek = noop_llseek,
-};
-
-static dev_t syncser_first;
-static int minor_count = NBR_PORTS;
-#define SYNCSER_NAME "syncser"
-static struct cdev *syncser_cdev;
-static struct class *syncser_class;
-
-static void sync_serial_start_port(struct sync_port *port)
-{
- reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
- reg_sser_rw_tr_cfg tr_cfg =
- REG_RD(sser, port->regi_sser, rw_tr_cfg);
- reg_sser_rw_rec_cfg rec_cfg =
- REG_RD(sser, port->regi_sser, rw_rec_cfg);
- cfg.en = regk_sser_yes;
- tr_cfg.tr_en = regk_sser_yes;
- rec_cfg.rec_en = regk_sser_yes;
- REG_WR(sser, port->regi_sser, rw_cfg, cfg);
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
- port->started = 1;
-}
-
-static void __init initialize_port(int portnbr)
-{
- struct sync_port *port = &ports[portnbr];
- reg_sser_rw_cfg cfg = { 0 };
- reg_sser_rw_frm_cfg frm_cfg = { 0 };
- reg_sser_rw_tr_cfg tr_cfg = { 0 };
- reg_sser_rw_rec_cfg rec_cfg = { 0 };
-
- DEBUG(pr_info("Init sync serial port %d\n", portnbr));
-
- port->port_nbr = portnbr;
- port->init_irqs = no_irq_setup;
-
- port->out_rd_ptr = port->out_buffer;
- port->out_buf_count = 0;
-
- port->output = 1;
- port->input = 0;
-
- port->readp = port->flip;
- port->writep = port->flip;
- port->in_buffer_size = IN_BUFFER_SIZE;
- port->in_buffer_len = 0;
- port->inbufchunk = IN_DESCR_SIZE;
-
- port->read_ts_idx = 0;
- port->write_ts_idx = 0;
-
- init_waitqueue_head(&port->out_wait_q);
- init_waitqueue_head(&port->in_wait_q);
-
- spin_lock_init(&port->lock);
-
- cfg.out_clk_src = regk_sser_intern_clk;
- cfg.out_clk_pol = regk_sser_pos;
- cfg.clk_od_mode = regk_sser_no;
- cfg.clk_dir = regk_sser_out;
- cfg.gate_clk = regk_sser_no;
- cfg.base_freq = regk_sser_f29_493;
- cfg.clk_div = 256;
- REG_WR(sser, port->regi_sser, rw_cfg, cfg);
-
- frm_cfg.wordrate = DEFAULT_WORD_RATE;
- frm_cfg.type = regk_sser_edge;
- frm_cfg.frame_pin_dir = regk_sser_out;
- frm_cfg.frame_pin_use = regk_sser_frm;
- frm_cfg.status_pin_dir = regk_sser_in;
- frm_cfg.status_pin_use = regk_sser_hold;
- frm_cfg.out_on = regk_sser_tr;
- frm_cfg.tr_delay = 1;
- REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
-
- tr_cfg.urun_stop = regk_sser_no;
- tr_cfg.sample_size = 7;
- tr_cfg.sh_dir = regk_sser_msbfirst;
- tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
-#if 0
- tr_cfg.rate_ctrl = regk_sser_bulk;
- tr_cfg.data_pin_use = regk_sser_dout;
-#else
- tr_cfg.rate_ctrl = regk_sser_iso;
- tr_cfg.data_pin_use = regk_sser_dout;
-#endif
- tr_cfg.bulk_wspace = 1;
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
-
- rec_cfg.sample_size = 7;
- rec_cfg.sh_dir = regk_sser_msbfirst;
- rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
- rec_cfg.fifo_thr = regk_sser_inf;
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
-
-#ifdef SYNC_SER_DMA
- {
- int i;
- /* Setup the descriptor ring for dma out/transmit. */
- for (i = 0; i < NBR_OUT_DESCR; i++) {
- dma_descr_data *descr = &port->out_descr[i];
- descr->wait = 0;
- descr->intr = 1;
- descr->eol = 0;
- descr->out_eop = 0;
- descr->next =
- (dma_descr_data *)virt_to_phys(&descr[i+1]);
- }
- }
-
- /* Create a ring from the list. */
- port->out_descr[NBR_OUT_DESCR-1].next =
- (dma_descr_data *)virt_to_phys(&port->out_descr[0]);
-
- /* Setup context for traversing the ring. */
- port->active_tr_descr = &port->out_descr[0];
- port->prev_tr_descr = &port->out_descr[NBR_OUT_DESCR-1];
- port->catch_tr_descr = &port->out_descr[0];
-#endif
-}
-
-static inline int sync_data_avail(struct sync_port *port)
-{
- return port->in_buffer_len;
-}
-
-static int sync_serial_open(struct inode *inode, struct file *file)
-{
- int ret = 0;
- int dev = iminor(inode);
- struct sync_port *port;
-#ifdef SYNC_SER_DMA
- reg_dma_rw_cfg cfg = { .en = regk_dma_yes };
- reg_dma_rw_intr_mask intr_mask = { .data = regk_dma_yes };
-#endif
-
- DEBUG(pr_debug("Open sync serial port %d\n", dev));
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
- /* Allow open this device twice (assuming one reader and one writer) */
- if (port->busy == 2) {
- DEBUG(pr_info("syncser%d is busy\n", dev));
- return -EBUSY;
- }
-
- mutex_lock(&sync_serial_mutex);
-
- /* Clear any stale date left in the flip buffer */
- port->readp = port->writep = port->flip;
- port->in_buffer_len = 0;
- port->read_ts_idx = 0;
- port->write_ts_idx = 0;
-
- if (port->init_irqs != no_irq_setup) {
- /* Init only on first call. */
- port->busy++;
- mutex_unlock(&sync_serial_mutex);
- return 0;
- }
- if (port->use_dma) {
-#ifdef SYNC_SER_DMA
- const char *tmp;
- DEBUG(pr_info("Using DMA for syncser%d\n", dev));
-
- tmp = dev == 0 ? "syncser0 tx" : "syncser1 tx";
- if (request_irq(port->dma_out_intr_vect, tr_interrupt, 0,
- tmp, port)) {
- pr_err("Can't alloc syncser%d TX IRQ", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- if (artpec_request_dma(port->dma_out_nbr, tmp,
- DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) {
- free_irq(port->dma_out_intr_vect, port);
- pr_err("Can't alloc syncser%d TX DMA", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- tmp = dev == 0 ? "syncser0 rx" : "syncser1 rx";
- if (request_irq(port->dma_in_intr_vect, rx_interrupt, 0,
- tmp, port)) {
- artpec_free_dma(port->dma_out_nbr);
- free_irq(port->dma_out_intr_vect, port);
- pr_err("Can't alloc syncser%d RX IRQ", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- if (artpec_request_dma(port->dma_in_nbr, tmp,
- DMA_VERBOSE_ON_ERROR, 0, port->req_dma)) {
- artpec_free_dma(port->dma_out_nbr);
- free_irq(port->dma_out_intr_vect, port);
- free_irq(port->dma_in_intr_vect, port);
- pr_err("Can't alloc syncser%d RX DMA", dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- /* Enable DMAs */
- REG_WR(dma, port->regi_dmain, rw_cfg, cfg);
- REG_WR(dma, port->regi_dmaout, rw_cfg, cfg);
- /* Enable DMA IRQs */
- REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask);
- REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask);
- /* Set up wordsize = 1 for DMAs. */
- DMA_WR_CMD(port->regi_dmain, regk_dma_set_w_size1);
- DMA_WR_CMD(port->regi_dmaout, regk_dma_set_w_size1);
-
- start_dma_in(port);
- port->init_irqs = dma_irq_setup;
-#endif
- } else { /* !port->use_dma */
-#ifdef SYNC_SER_MANUAL
- const char *tmp = dev == 0 ? "syncser0 manual irq" :
- "syncser1 manual irq";
- if (request_irq(port->syncser_intr_vect, manual_interrupt,
- 0, tmp, port)) {
- pr_err("Can't alloc syncser%d manual irq",
- dev);
- ret = -EBUSY;
- goto unlock_and_exit;
- }
- port->init_irqs = manual_irq_setup;
-#else
- panic("sync_serial: Manual mode not supported\n");
-#endif /* SYNC_SER_MANUAL */
- }
- port->busy++;
- ret = 0;
-
-unlock_and_exit:
- mutex_unlock(&sync_serial_mutex);
- return ret;
-}
-
-static int sync_serial_release(struct inode *inode, struct file *file)
-{
- int dev = iminor(inode);
- struct sync_port *port;
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
- if (port->busy)
- port->busy--;
- if (!port->busy)
- /* XXX */;
- return 0;
-}
-
-static __poll_t sync_serial_poll(struct file *file, poll_table *wait)
-{
- int dev = iminor(file_inode(file));
- __poll_t mask = 0;
- struct sync_port *port;
- DEBUGPOLL(
- static __poll_t prev_mask;
- );
-
- port = &ports[dev];
-
- if (!port->started)
- sync_serial_start_port(port);
-
- poll_wait(file, &port->out_wait_q, wait);
- poll_wait(file, &port->in_wait_q, wait);
-
- /* No active transfer, descriptors are available */
- if (port->output && !port->tr_running)
- mask |= EPOLLOUT | EPOLLWRNORM;
-
- /* Descriptor and buffer space available. */
- if (port->output &&
- port->active_tr_descr != port->catch_tr_descr &&
- port->out_buf_count < OUT_BUFFER_SIZE)
- mask |= EPOLLOUT | EPOLLWRNORM;
-
- /* At least an inbufchunk of data */
- if (port->input && sync_data_avail(port) >= port->inbufchunk)
- mask |= EPOLLIN | EPOLLRDNORM;
-
- DEBUGPOLL(
- if (mask != prev_mask)
- pr_info("sync_serial_poll: mask 0x%08X %s %s\n",
- mask,
- mask & EPOLLOUT ? "POLLOUT" : "",
- mask & EPOLLIN ? "POLLIN" : "");
- prev_mask = mask;
- );
- return mask;
-}
-
-static ssize_t __sync_serial_read(struct file *file,
- char __user *buf,
- size_t count,
- loff_t *ppos,
- struct timespec *ts)
-{
- unsigned long flags;
- int dev = MINOR(file_inode(file)->i_rdev);
- int avail;
- struct sync_port *port;
- unsigned char *start;
- unsigned char *end;
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- if (!port->started)
- sync_serial_start_port(port);
-
- /* Calculate number of available bytes */
- /* Save pointers to avoid that they are modified by interrupt */
- spin_lock_irqsave(&port->lock, flags);
- start = port->readp;
- end = port->writep;
- spin_unlock_irqrestore(&port->lock, flags);
-
- while ((start == end) && !port->in_buffer_len) {
- if (file->f_flags & O_NONBLOCK)
- return -EAGAIN;
-
- wait_event_interruptible(port->in_wait_q,
- !(start == end && !port->full));
-
- if (signal_pending(current))
- return -EINTR;
-
- spin_lock_irqsave(&port->lock, flags);
- start = port->readp;
- end = port->writep;
- spin_unlock_irqrestore(&port->lock, flags);
- }
-
- DEBUGREAD(pr_info("R%d c %d ri %u wi %u /%u\n",
- dev, count,
- start - port->flip, end - port->flip,
- port->in_buffer_size));
-
- /* Lazy read, never return wrapped data. */
- if (end > start)
- avail = end - start;
- else
- avail = port->flip + port->in_buffer_size - start;
-
- count = count > avail ? avail : count;
- if (copy_to_user(buf, start, count))
- return -EFAULT;
-
- /* If timestamp requested, find timestamp of first returned byte
- * and copy it.
- * N.B: Applications that request timstamps MUST read data in
- * chunks that are multiples of IN_DESCR_SIZE.
- * Otherwise the timestamps will not be aligned to the data read.
- */
- if (ts != NULL) {
- int idx = port->read_ts_idx;
- memcpy(ts, &port->timestamp[idx], sizeof(struct timespec));
- port->read_ts_idx += count / IN_DESCR_SIZE;
- if (port->read_ts_idx >= NBR_IN_DESCR)
- port->read_ts_idx = 0;
- }
-
- spin_lock_irqsave(&port->lock, flags);
- port->readp += count;
- /* Check for wrap */
- if (port->readp >= port->flip + port->in_buffer_size)
- port->readp = port->flip;
- port->in_buffer_len -= count;
- port->full = 0;
- spin_unlock_irqrestore(&port->lock, flags);
-
- DEBUGREAD(pr_info("r %d\n", count));
-
- return count;
-}
-
-static ssize_t sync_serial_input(struct file *file, unsigned long arg)
-{
- struct ssp_request req;
- int count;
- int ret;
-
- /* Copy the request structure from user-mode. */
- ret = copy_from_user(&req, (struct ssp_request __user *)arg,
- sizeof(struct ssp_request));
-
- if (ret) {
- DEBUG(pr_info("sync_serial_input copy from user failed\n"));
- return -EFAULT;
- }
-
- /* To get the timestamps aligned, make sure that 'len'
- * is a multiple of IN_DESCR_SIZE.
- */
- if ((req.len % IN_DESCR_SIZE) != 0) {
- DEBUG(pr_info("sync_serial: req.len %x, IN_DESCR_SIZE %x\n",
- req.len, IN_DESCR_SIZE));
- return -EFAULT;
- }
-
- /* Do the actual read. */
- /* Note that req.buf is actually a pointer to user space. */
- count = __sync_serial_read(file, req.buf, req.len,
- NULL, &req.ts);
-
- if (count < 0) {
- DEBUG(pr_info("sync_serial_input read failed\n"));
- return count;
- }
-
- /* Copy the request back to user-mode. */
- ret = copy_to_user((struct ssp_request __user *)arg, &req,
- sizeof(struct ssp_request));
-
- if (ret) {
- DEBUG(pr_info("syncser input copy2user failed\n"));
- return -EFAULT;
- }
-
- /* Return the number of bytes read. */
- return count;
-}
-
-
-static int sync_serial_ioctl_unlocked(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int return_val = 0;
- int dma_w_size = regk_dma_set_w_size1;
- int dev = iminor(file_inode(file));
- struct sync_port *port;
- reg_sser_rw_tr_cfg tr_cfg;
- reg_sser_rw_rec_cfg rec_cfg;
- reg_sser_rw_frm_cfg frm_cfg;
- reg_sser_rw_cfg gen_cfg;
- reg_sser_rw_intr_mask intr_mask;
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -1;
- }
-
- if (cmd == SSP_INPUT)
- return sync_serial_input(file, arg);
-
- port = &ports[dev];
- spin_lock_irq(&port->lock);
-
- tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
- rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
- frm_cfg = REG_RD(sser, port->regi_sser, rw_frm_cfg);
- gen_cfg = REG_RD(sser, port->regi_sser, rw_cfg);
- intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
-
- switch (cmd) {
- case SSP_SPEED:
- if (GET_SPEED(arg) == CODEC) {
- unsigned int freq;
-
- gen_cfg.base_freq = regk_sser_f32;
-
- /* Clock divider will internally be
- * gen_cfg.clk_div + 1.
- */
-
- freq = GET_FREQ(arg);
- switch (freq) {
- case FREQ_32kHz:
- case FREQ_64kHz:
- case FREQ_128kHz:
- case FREQ_256kHz:
- gen_cfg.clk_div = 125 *
- (1 << (freq - FREQ_256kHz)) - 1;
- break;
- case FREQ_512kHz:
- gen_cfg.clk_div = 62;
- break;
- case FREQ_1MHz:
- case FREQ_2MHz:
- case FREQ_4MHz:
- gen_cfg.clk_div = 8 * (1 << freq) - 1;
- break;
- }
- } else if (GET_SPEED(arg) == CODEC_f32768) {
- gen_cfg.base_freq = regk_sser_f32_768;
- switch (GET_FREQ(arg)) {
- case FREQ_4096kHz:
- gen_cfg.clk_div = 7;
- break;
- default:
- spin_unlock_irq(&port->lock);
- return -EINVAL;
- }
- } else {
- gen_cfg.base_freq = regk_sser_f29_493;
- switch (GET_SPEED(arg)) {
- case SSP150:
- gen_cfg.clk_div = 29493000 / (150 * 8) - 1;
- break;
- case SSP300:
- gen_cfg.clk_div = 29493000 / (300 * 8) - 1;
- break;
- case SSP600:
- gen_cfg.clk_div = 29493000 / (600 * 8) - 1;
- break;
- case SSP1200:
- gen_cfg.clk_div = 29493000 / (1200 * 8) - 1;
- break;
- case SSP2400:
- gen_cfg.clk_div = 29493000 / (2400 * 8) - 1;
- break;
- case SSP4800:
- gen_cfg.clk_div = 29493000 / (4800 * 8) - 1;
- break;
- case SSP9600:
- gen_cfg.clk_div = 29493000 / (9600 * 8) - 1;
- break;
- case SSP19200:
- gen_cfg.clk_div = 29493000 / (19200 * 8) - 1;
- break;
- case SSP28800:
- gen_cfg.clk_div = 29493000 / (28800 * 8) - 1;
- break;
- case SSP57600:
- gen_cfg.clk_div = 29493000 / (57600 * 8) - 1;
- break;
- case SSP115200:
- gen_cfg.clk_div = 29493000 / (115200 * 8) - 1;
- break;
- case SSP230400:
- gen_cfg.clk_div = 29493000 / (230400 * 8) - 1;
- break;
- case SSP460800:
- gen_cfg.clk_div = 29493000 / (460800 * 8) - 1;
- break;
- case SSP921600:
- gen_cfg.clk_div = 29493000 / (921600 * 8) - 1;
- break;
- case SSP3125000:
- gen_cfg.base_freq = regk_sser_f100;
- gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1;
- break;
-
- }
- }
- frm_cfg.wordrate = GET_WORD_RATE(arg);
-
- break;
- case SSP_MODE:
- switch (arg) {
- case MASTER_OUTPUT:
- port->output = 1;
- port->input = 0;
- frm_cfg.out_on = regk_sser_tr;
- frm_cfg.frame_pin_dir = regk_sser_out;
- gen_cfg.clk_dir = regk_sser_out;
- break;
- case SLAVE_OUTPUT:
- port->output = 1;
- port->input = 0;
- frm_cfg.frame_pin_dir = regk_sser_in;
- gen_cfg.clk_dir = regk_sser_in;
- break;
- case MASTER_INPUT:
- port->output = 0;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_out;
- frm_cfg.out_on = regk_sser_intern_tb;
- gen_cfg.clk_dir = regk_sser_out;
- break;
- case SLAVE_INPUT:
- port->output = 0;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_in;
- gen_cfg.clk_dir = regk_sser_in;
- break;
- case MASTER_BIDIR:
- port->output = 1;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_out;
- frm_cfg.out_on = regk_sser_intern_tb;
- gen_cfg.clk_dir = regk_sser_out;
- break;
- case SLAVE_BIDIR:
- port->output = 1;
- port->input = 1;
- frm_cfg.frame_pin_dir = regk_sser_in;
- gen_cfg.clk_dir = regk_sser_in;
- break;
- default:
- spin_unlock_irq(&port->lock);
- return -EINVAL;
- }
- if (!port->use_dma || arg == MASTER_OUTPUT ||
- arg == SLAVE_OUTPUT)
- intr_mask.rdav = regk_sser_yes;
- break;
- case SSP_FRAME_SYNC:
- if (arg & NORMAL_SYNC) {
- frm_cfg.rec_delay = 1;
- frm_cfg.tr_delay = 1;
- } else if (arg & EARLY_SYNC)
- frm_cfg.rec_delay = frm_cfg.tr_delay = 0;
- else if (arg & LATE_SYNC) {
- frm_cfg.tr_delay = 2;
- frm_cfg.rec_delay = 2;
- } else if (arg & SECOND_WORD_SYNC) {
- frm_cfg.rec_delay = 7;
- frm_cfg.tr_delay = 1;
- }
-
- tr_cfg.bulk_wspace = frm_cfg.tr_delay;
- frm_cfg.early_wend = regk_sser_yes;
- if (arg & BIT_SYNC)
- frm_cfg.type = regk_sser_edge;
- else if (arg & WORD_SYNC)
- frm_cfg.type = regk_sser_level;
- else if (arg & EXTENDED_SYNC)
- frm_cfg.early_wend = regk_sser_no;
-
- if (arg & SYNC_ON)
- frm_cfg.frame_pin_use = regk_sser_frm;
- else if (arg & SYNC_OFF)
- frm_cfg.frame_pin_use = regk_sser_gio0;
-
- dma_w_size = regk_dma_set_w_size2;
- if (arg & WORD_SIZE_8) {
- rec_cfg.sample_size = tr_cfg.sample_size = 7;
- dma_w_size = regk_dma_set_w_size1;
- } else if (arg & WORD_SIZE_12)
- rec_cfg.sample_size = tr_cfg.sample_size = 11;
- else if (arg & WORD_SIZE_16)
- rec_cfg.sample_size = tr_cfg.sample_size = 15;
- else if (arg & WORD_SIZE_24)
- rec_cfg.sample_size = tr_cfg.sample_size = 23;
- else if (arg & WORD_SIZE_32)
- rec_cfg.sample_size = tr_cfg.sample_size = 31;
-
- if (arg & BIT_ORDER_MSB)
- rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
- else if (arg & BIT_ORDER_LSB)
- rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst;
-
- if (arg & FLOW_CONTROL_ENABLE) {
- frm_cfg.status_pin_use = regk_sser_frm;
- rec_cfg.fifo_thr = regk_sser_thr16;
- } else if (arg & FLOW_CONTROL_DISABLE) {
- frm_cfg.status_pin_use = regk_sser_gio0;
- rec_cfg.fifo_thr = regk_sser_inf;
- }
-
- if (arg & CLOCK_NOT_GATED)
- gen_cfg.gate_clk = regk_sser_no;
- else if (arg & CLOCK_GATED)
- gen_cfg.gate_clk = regk_sser_yes;
-
- break;
- case SSP_IPOLARITY:
- /* NOTE!! negedge is considered NORMAL */
- if (arg & CLOCK_NORMAL)
- rec_cfg.clk_pol = regk_sser_neg;
- else if (arg & CLOCK_INVERT)
- rec_cfg.clk_pol = regk_sser_pos;
-
- if (arg & FRAME_NORMAL)
- frm_cfg.level = regk_sser_pos_hi;
- else if (arg & FRAME_INVERT)
- frm_cfg.level = regk_sser_neg_lo;
-
- if (arg & STATUS_NORMAL)
- gen_cfg.hold_pol = regk_sser_pos;
- else if (arg & STATUS_INVERT)
- gen_cfg.hold_pol = regk_sser_neg;
- break;
- case SSP_OPOLARITY:
- if (arg & CLOCK_NORMAL)
- gen_cfg.out_clk_pol = regk_sser_pos;
- else if (arg & CLOCK_INVERT)
- gen_cfg.out_clk_pol = regk_sser_neg;
-
- if (arg & FRAME_NORMAL)
- frm_cfg.level = regk_sser_pos_hi;
- else if (arg & FRAME_INVERT)
- frm_cfg.level = regk_sser_neg_lo;
-
- if (arg & STATUS_NORMAL)
- gen_cfg.hold_pol = regk_sser_pos;
- else if (arg & STATUS_INVERT)
- gen_cfg.hold_pol = regk_sser_neg;
- break;
- case SSP_SPI:
- rec_cfg.fifo_thr = regk_sser_inf;
- rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_msbfirst;
- rec_cfg.sample_size = tr_cfg.sample_size = 7;
- frm_cfg.frame_pin_use = regk_sser_frm;
- frm_cfg.type = regk_sser_level;
- frm_cfg.tr_delay = 1;
- frm_cfg.level = regk_sser_neg_lo;
- if (arg & SPI_SLAVE) {
- rec_cfg.clk_pol = regk_sser_neg;
- gen_cfg.clk_dir = regk_sser_in;
- port->input = 1;
- port->output = 0;
- } else {
- gen_cfg.out_clk_pol = regk_sser_pos;
- port->input = 0;
- port->output = 1;
- gen_cfg.clk_dir = regk_sser_out;
- }
- break;
- case SSP_INBUFCHUNK:
- break;
- default:
- return_val = -1;
- }
-
-
- if (port->started) {
- rec_cfg.rec_en = port->input;
- gen_cfg.en = (port->output | port->input);
- }
-
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
- REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg);
- REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
- REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
-
-
- if (cmd == SSP_FRAME_SYNC && (arg & (WORD_SIZE_8 | WORD_SIZE_12 |
- WORD_SIZE_16 | WORD_SIZE_24 | WORD_SIZE_32))) {
- int en = gen_cfg.en;
- gen_cfg.en = 0;
- REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
- /* ##### Should DMA be stoped before we change dma size? */
- DMA_WR_CMD(port->regi_dmain, dma_w_size);
- DMA_WR_CMD(port->regi_dmaout, dma_w_size);
- gen_cfg.en = en;
- REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
- }
-
- spin_unlock_irq(&port->lock);
- return return_val;
-}
-
-static long sync_serial_ioctl(struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- long ret;
-
- mutex_lock(&sync_serial_mutex);
- ret = sync_serial_ioctl_unlocked(file, cmd, arg);
- mutex_unlock(&sync_serial_mutex);
-
- return ret;
-}
-
-/* NOTE: sync_serial_write does not support concurrency */
-static ssize_t sync_serial_write(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos)
-{
- int dev = iminor(file_inode(file));
- DECLARE_WAITQUEUE(wait, current);
- struct sync_port *port;
- int trunc_count;
- unsigned long flags;
- int bytes_free;
- int out_buf_count;
-
- unsigned char *rd_ptr; /* First allocated byte in the buffer */
- unsigned char *wr_ptr; /* First free byte in the buffer */
- unsigned char *buf_stop_ptr; /* Last byte + 1 */
-
- if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
- DEBUG(pr_info("Invalid minor %d\n", dev));
- return -ENODEV;
- }
- port = &ports[dev];
-
- /* |<- OUT_BUFFER_SIZE ->|
- * |<- out_buf_count ->|
- * |<- trunc_count ->| ...->|
- * ______________________________________________________
- * | free | data | free |
- * |_________|___________________|________________________|
- * ^ rd_ptr ^ wr_ptr
- */
- DEBUGWRITE(pr_info("W d%d c %u a: %p c: %p\n",
- port->port_nbr, count, port->active_tr_descr,
- port->catch_tr_descr));
-
- /* Read variables that may be updated by interrupts */
- spin_lock_irqsave(&port->lock, flags);
- rd_ptr = port->out_rd_ptr;
- out_buf_count = port->out_buf_count;
- spin_unlock_irqrestore(&port->lock, flags);
-
- /* Check if resources are available */
- if (port->tr_running &&
- ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) ||
- out_buf_count >= OUT_BUFFER_SIZE)) {
- DEBUGWRITE(pr_info("sser%d full\n", dev));
- return -EAGAIN;
- }
-
- buf_stop_ptr = port->out_buffer + OUT_BUFFER_SIZE;
-
- /* Determine pointer to the first free byte, before copying. */
- wr_ptr = rd_ptr + out_buf_count;
- if (wr_ptr >= buf_stop_ptr)
- wr_ptr -= OUT_BUFFER_SIZE;
-
- /* If we wrap the ring buffer, let the user space program handle it by
- * truncating the data. This could be more elegant, small buffer
- * fragments may occur.
- */
- bytes_free = OUT_BUFFER_SIZE - out_buf_count;
- if (wr_ptr + bytes_free > buf_stop_ptr)
- bytes_free = buf_stop_ptr - wr_ptr;
- trunc_count = (count < bytes_free) ? count : bytes_free;
-
- if (copy_from_user(wr_ptr, buf, trunc_count))
- return -EFAULT;
-
- DEBUGOUTBUF(pr_info("%-4d + %-4d = %-4d %p %p %p\n",
- out_buf_count, trunc_count,
- port->out_buf_count, port->out_buffer,
- wr_ptr, buf_stop_ptr));
-
- /* Make sure transmitter/receiver is running */
- if (!port->started) {
- reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
- reg_sser_rw_rec_cfg rec_cfg =
- REG_RD(sser, port->regi_sser, rw_rec_cfg);
- cfg.en = regk_sser_yes;
- rec_cfg.rec_en = port->input;
- REG_WR(sser, port->regi_sser, rw_cfg, cfg);
- REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
- port->started = 1;
- }
-
- /* Setup wait if blocking */
- if (!(file->f_flags & O_NONBLOCK)) {
- add_wait_queue(&port->out_wait_q, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
- }
-
- spin_lock_irqsave(&port->lock, flags);
- port->out_buf_count += trunc_count;
- if (port->use_dma) {
-#ifdef SYNC_SER_DMA
- start_dma_out(port, wr_ptr, trunc_count);
-#endif
- } else if (!port->tr_running) {
-#ifdef SYNC_SER_MANUAL
- reg_sser_rw_intr_mask intr_mask;
- intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- intr_mask.trdy = 1;
- REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
-#endif
- }
- spin_unlock_irqrestore(&port->lock, flags);
-
- /* Exit if non blocking */
- if (file->f_flags & O_NONBLOCK) {
- DEBUGWRITE(pr_info("w d%d c %u %08x\n",
- port->port_nbr, trunc_count,
- REG_RD_INT(dma, port->regi_dmaout, r_intr)));
- return trunc_count;
- }
-
- schedule();
- remove_wait_queue(&port->out_wait_q, &wait);
-
- if (signal_pending(current))
- return -EINTR;
-
- DEBUGWRITE(pr_info("w d%d c %u\n", port->port_nbr, trunc_count));
- return trunc_count;
-}
-
-static ssize_t sync_serial_read(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- return __sync_serial_read(file, buf, count, ppos, NULL);
-}
-
-#ifdef SYNC_SER_MANUAL
-static void send_word(struct sync_port *port)
-{
- reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
- reg_sser_rw_tr_data tr_data = {0};
-
- switch (tr_cfg.sample_size) {
- case 8:
- port->out_buf_count--;
- tr_data.data = *port->out_rd_ptr++;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- case 12:
- {
- int data = (*port->out_rd_ptr++) << 8;
- data |= *port->out_rd_ptr++;
- port->out_buf_count -= 2;
- tr_data.data = data;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- }
- case 16:
- port->out_buf_count -= 2;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- case 24:
- port->out_buf_count -= 3;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- tr_data.data = *port->out_rd_ptr++;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- case 32:
- port->out_buf_count -= 4;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- tr_data.data = *(unsigned short *)port->out_rd_ptr;
- REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->out_rd_ptr += 2;
- if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
- break;
- }
-}
-#endif
-
-#ifdef SYNC_SER_DMA
-static void start_dma_out(struct sync_port *port, const char *data, int count)
-{
- port->active_tr_descr->buf = (char *)virt_to_phys((char *)data);
- port->active_tr_descr->after = port->active_tr_descr->buf + count;
- port->active_tr_descr->intr = 1;
-
- port->active_tr_descr->eol = 1;
- port->prev_tr_descr->eol = 0;
-
- DEBUGTRDMA(pr_info("Inserting eolr:%p eol@:%p\n",
- port->prev_tr_descr, port->active_tr_descr));
- port->prev_tr_descr = port->active_tr_descr;
- port->active_tr_descr = phys_to_virt((int)port->active_tr_descr->next);
-
- if (!port->tr_running) {
- reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser,
- rw_tr_cfg);
-
- port->out_context.next = NULL;
- port->out_context.saved_data =
- (dma_descr_data *)virt_to_phys(port->prev_tr_descr);
- port->out_context.saved_data_buf = port->prev_tr_descr->buf;
-
- DMA_START_CONTEXT(port->regi_dmaout,
- virt_to_phys((char *)&port->out_context));
-
- tr_cfg.tr_en = regk_sser_yes;
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- DEBUGTRDMA(pr_info("dma s\n"););
- } else {
- DMA_CONTINUE_DATA(port->regi_dmaout);
- DEBUGTRDMA(pr_info("dma c\n"););
- }
-
- port->tr_running = 1;
-}
-
-static void start_dma_in(struct sync_port *port)
-{
- int i;
- char *buf;
- unsigned long flags;
- spin_lock_irqsave(&port->lock, flags);
- port->writep = port->flip;
- spin_unlock_irqrestore(&port->lock, flags);
-
- buf = (char *)virt_to_phys(port->in_buffer);
- for (i = 0; i < NBR_IN_DESCR; i++) {
- port->in_descr[i].buf = buf;
- port->in_descr[i].after = buf + port->inbufchunk;
- port->in_descr[i].intr = 1;
- port->in_descr[i].next =
- (dma_descr_data *)virt_to_phys(&port->in_descr[i+1]);
- port->in_descr[i].buf = buf;
- buf += port->inbufchunk;
- }
- /* Link the last descriptor to the first */
- port->in_descr[i-1].next =
- (dma_descr_data *)virt_to_phys(&port->in_descr[0]);
- port->in_descr[i-1].eol = regk_sser_yes;
- port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1];
- port->in_context.saved_data =
- (dma_descr_data *)virt_to_phys(&port->in_descr[0]);
- port->in_context.saved_data_buf = port->in_descr[0].buf;
- DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context));
-}
-
-static irqreturn_t tr_interrupt(int irq, void *dev_id)
-{
- reg_dma_r_masked_intr masked;
- reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes };
- reg_dma_rw_stat stat;
- int i;
- int found = 0;
- int stop_sser = 0;
-
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
- if (!port->enabled || !port->use_dma)
- continue;
-
- /* IRQ active for the port? */
- masked = REG_RD(dma, port->regi_dmaout, r_masked_intr);
- if (!masked.data)
- continue;
-
- found = 1;
-
- /* Check if we should stop the DMA transfer */
- stat = REG_RD(dma, port->regi_dmaout, rw_stat);
- if (stat.list_state == regk_dma_data_at_eol)
- stop_sser = 1;
-
- /* Clear IRQ */
- REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr);
-
- if (!stop_sser) {
- /* The DMA has completed a descriptor, EOL was not
- * encountered, so step relevant descriptor and
- * datapointers forward. */
- int sent;
- sent = port->catch_tr_descr->after -
- port->catch_tr_descr->buf;
- DEBUGTXINT(pr_info("%-4d - %-4d = %-4d\t"
- "in descr %p (ac: %p)\n",
- port->out_buf_count, sent,
- port->out_buf_count - sent,
- port->catch_tr_descr,
- port->active_tr_descr););
- port->out_buf_count -= sent;
- port->catch_tr_descr =
- phys_to_virt((int) port->catch_tr_descr->next);
- port->out_rd_ptr =
- phys_to_virt((int) port->catch_tr_descr->buf);
- } else {
- reg_sser_rw_tr_cfg tr_cfg;
- int j, sent;
- /* EOL handler.
- * Note that if an EOL was encountered during the irq
- * locked section of sync_ser_write the DMA will be
- * restarted and the eol flag will be cleared.
- * The remaining descriptors will be traversed by
- * the descriptor interrupts as usual.
- */
- j = 0;
- while (!port->catch_tr_descr->eol) {
- sent = port->catch_tr_descr->after -
- port->catch_tr_descr->buf;
- DEBUGOUTBUF(pr_info(
- "traversing descr %p -%d (%d)\n",
- port->catch_tr_descr,
- sent,
- port->out_buf_count));
- port->out_buf_count -= sent;
- port->catch_tr_descr = phys_to_virt(
- (int)port->catch_tr_descr->next);
- j++;
- if (j >= NBR_OUT_DESCR) {
- /* TODO: Reset and recover */
- panic("sync_serial: missing eol");
- }
- }
- sent = port->catch_tr_descr->after -
- port->catch_tr_descr->buf;
- DEBUGOUTBUF(pr_info("eol at descr %p -%d (%d)\n",
- port->catch_tr_descr,
- sent,
- port->out_buf_count));
-
- port->out_buf_count -= sent;
-
- /* Update read pointer to first free byte, we
- * may already be writing data there. */
- port->out_rd_ptr =
- phys_to_virt((int) port->catch_tr_descr->after);
- if (port->out_rd_ptr > port->out_buffer +
- OUT_BUFFER_SIZE)
- port->out_rd_ptr = port->out_buffer;
-
- tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
- DEBUGTXINT(pr_info(
- "tr_int DMA stop %d, set catch @ %p\n",
- port->out_buf_count,
- port->active_tr_descr));
- if (port->out_buf_count != 0)
- pr_err("sync_ser: buf not empty after eol\n");
- port->catch_tr_descr = port->active_tr_descr;
- port->tr_running = 0;
- tr_cfg.tr_en = regk_sser_no;
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
- }
- /* wake up the waiting process */
- wake_up_interruptible(&port->out_wait_q);
- }
- return IRQ_RETVAL(found);
-} /* tr_interrupt */
-
-
-static inline void handle_rx_packet(struct sync_port *port)
-{
- int idx;
- reg_dma_rw_ack_intr ack_intr = { .data = regk_dma_yes };
- unsigned long flags;
-
- DEBUGRXINT(pr_info("!"));
- spin_lock_irqsave(&port->lock, flags);
-
- /* If we overrun the user experience is crap regardless if we
- * drop new or old data. Its much easier to get it right when
- * dropping new data so lets do that.
- */
- if ((port->writep + port->inbufchunk <=
- port->flip + port->in_buffer_size) &&
- (port->in_buffer_len + port->inbufchunk < IN_BUFFER_SIZE)) {
- memcpy(port->writep,
- phys_to_virt((unsigned)port->next_rx_desc->buf),
- port->inbufchunk);
- port->writep += port->inbufchunk;
- if (port->writep >= port->flip + port->in_buffer_size)
- port->writep = port->flip;
-
- /* Timestamp the new data chunk. */
- if (port->write_ts_idx == NBR_IN_DESCR)
- port->write_ts_idx = 0;
- idx = port->write_ts_idx++;
- ktime_get_ts(&port->timestamp[idx]);
- port->in_buffer_len += port->inbufchunk;
- }
- spin_unlock_irqrestore(&port->lock, flags);
-
- port->next_rx_desc->eol = 1;
- port->prev_rx_desc->eol = 0;
- /* Cache bug workaround */
- flush_dma_descr(port->prev_rx_desc, 0);
- port->prev_rx_desc = port->next_rx_desc;
- port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next);
- /* Cache bug workaround */
- flush_dma_descr(port->prev_rx_desc, 1);
- /* wake up the waiting process */
- wake_up_interruptible(&port->in_wait_q);
- DMA_CONTINUE(port->regi_dmain);
- REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr);
-
-}
-
-static irqreturn_t rx_interrupt(int irq, void *dev_id)
-{
- reg_dma_r_masked_intr masked;
-
- int i;
- int found = 0;
-
- DEBUG(pr_info("rx_interrupt\n"));
-
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || !port->use_dma)
- continue;
-
- masked = REG_RD(dma, port->regi_dmain, r_masked_intr);
-
- if (!masked.data)
- continue;
-
- /* Descriptor interrupt */
- found = 1;
- while (REG_RD(dma, port->regi_dmain, rw_data) !=
- virt_to_phys(port->next_rx_desc))
- handle_rx_packet(port);
- }
- return IRQ_RETVAL(found);
-} /* rx_interrupt */
-#endif /* SYNC_SER_DMA */
-
-#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id)
-{
- unsigned long flags;
- int i;
- int found = 0;
- reg_sser_r_masked_intr masked;
-
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
-
- if (!port->enabled || port->use_dma)
- continue;
-
- masked = REG_RD(sser, port->regi_sser, r_masked_intr);
- /* Data received? */
- if (masked.rdav) {
- reg_sser_rw_rec_cfg rec_cfg =
- REG_RD(sser, port->regi_sser, rw_rec_cfg);
- reg_sser_r_rec_data data = REG_RD(sser,
- port->regi_sser, r_rec_data);
- found = 1;
- /* Read data */
- spin_lock_irqsave(&port->lock, flags);
- switch (rec_cfg.sample_size) {
- case 8:
- *port->writep++ = data.data & 0xff;
- break;
- case 12:
- *port->writep = (data.data & 0x0ff0) >> 4;
- *(port->writep + 1) = data.data & 0x0f;
- port->writep += 2;
- break;
- case 16:
- *(unsigned short *)port->writep = data.data;
- port->writep += 2;
- break;
- case 24:
- *(unsigned int *)port->writep = data.data;
- port->writep += 3;
- break;
- case 32:
- *(unsigned int *)port->writep = data.data;
- port->writep += 4;
- break;
- }
-
- /* Wrap? */
- if (port->writep >= port->flip + port->in_buffer_size)
- port->writep = port->flip;
- if (port->writep == port->readp) {
- /* Receive buf overrun, discard oldest data */
- port->readp++;
- /* Wrap? */
- if (port->readp >= port->flip +
- port->in_buffer_size)
- port->readp = port->flip;
- }
- spin_unlock_irqrestore(&port->lock, flags);
- if (sync_data_avail(port) >= port->inbufchunk)
- /* Wake up application */
- wake_up_interruptible(&port->in_wait_q);
- }
-
- /* Transmitter ready? */
- if (masked.trdy) {
- found = 1;
- /* More data to send */
- if (port->out_buf_count > 0)
- send_word(port);
- else {
- /* Transmission finished */
- reg_sser_rw_intr_mask intr_mask;
- intr_mask = REG_RD(sser, port->regi_sser,
- rw_intr_mask);
- intr_mask.trdy = 0;
- REG_WR(sser, port->regi_sser,
- rw_intr_mask, intr_mask);
- /* Wake up application */
- wake_up_interruptible(&port->out_wait_q);
- }
- }
- }
- return IRQ_RETVAL(found);
-}
-#endif
-
-static int __init etrax_sync_serial_init(void)
-{
-#if 1
- /* This code will be removed when we move to udev for all devices. */
- syncser_first = MKDEV(SYNC_SERIAL_MAJOR, 0);
- if (register_chrdev_region(syncser_first, minor_count, SYNCSER_NAME)) {
- pr_err("Failed to register major %d\n", SYNC_SERIAL_MAJOR);
- return -1;
- }
-#else
- /* Allocate dynamic major number. */
- if (alloc_chrdev_region(&syncser_first, 0, minor_count, SYNCSER_NAME)) {
- pr_err("Failed to allocate character device region\n");
- return -1;
- }
-#endif
- syncser_cdev = cdev_alloc();
- if (!syncser_cdev) {
- pr_err("Failed to allocate cdev for syncser\n");
- unregister_chrdev_region(syncser_first, minor_count);
- return -1;
- }
- cdev_init(syncser_cdev, &syncser_fops);
-
- /* Create a sysfs class for syncser */
- syncser_class = class_create(THIS_MODULE, "syncser_class");
- if (IS_ERR(syncser_class)) {
- pr_err("Failed to create a sysfs class for syncser\n");
- unregister_chrdev_region(syncser_first, minor_count);
- cdev_del(syncser_cdev);
- return -1;
- }
-
- /* Initialize Ports */
-#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- if (artpec_pinmux_alloc_fixed(PINMUX_SSER0)) {
- pr_warn("Unable to alloc pins for synchronous serial port 0\n");
- unregister_chrdev_region(syncser_first, minor_count);
- return -EIO;
- }
- initialize_port(0);
- ports[0].enabled = 1;
- /* Register with sysfs so udev can pick it up. */
- device_create(syncser_class, NULL, syncser_first, NULL,
- "%s%d", SYNCSER_NAME, 0);
-#endif
-
-#if defined(CONFIG_ETRAXFS) && defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- if (artpec_pinmux_alloc_fixed(PINMUX_SSER1)) {
- pr_warn("Unable to alloc pins for synchronous serial port 1\n");
- unregister_chrdev_region(syncser_first, minor_count);
- class_destroy(syncser_class);
- return -EIO;
- }
- initialize_port(1);
- ports[1].enabled = 1;
- /* Register with sysfs so udev can pick it up. */
- device_create(syncser_class, NULL, syncser_first, NULL,
- "%s%d", SYNCSER_NAME, 0);
-#endif
-
- /* Add it to system */
- if (cdev_add(syncser_cdev, syncser_first, minor_count) < 0) {
- pr_err("Failed to add syncser as char device\n");
- device_destroy(syncser_class, syncser_first);
- class_destroy(syncser_class);
- cdev_del(syncser_cdev);
- unregister_chrdev_region(syncser_first, minor_count);
- return -1;
- }
-
-
- pr_info("ARTPEC synchronous serial port (%s: %d, %d)\n",
- SYNCSER_NAME, MAJOR(syncser_first), MINOR(syncser_first));
-
- return 0;
-}
-
-static void __exit etrax_sync_serial_exit(void)
-{
- int i;
- device_destroy(syncser_class, syncser_first);
- class_destroy(syncser_class);
-
- if (syncser_cdev) {
- cdev_del(syncser_cdev);
- unregister_chrdev_region(syncser_first, minor_count);
- }
- for (i = 0; i < NBR_PORTS; i++) {
- struct sync_port *port = &ports[i];
- if (port->init_irqs == dma_irq_setup) {
- /* Free dma irqs and dma channels. */
-#ifdef SYNC_SER_DMA
- artpec_free_dma(port->dma_in_nbr);
- artpec_free_dma(port->dma_out_nbr);
- free_irq(port->dma_out_intr_vect, port);
- free_irq(port->dma_in_intr_vect, port);
-#endif
- } else if (port->init_irqs == manual_irq_setup) {
- /* Free manual irq. */
- free_irq(port->syncser_intr_vect, port);
- }
- }
-
- pr_info("ARTPEC synchronous serial port unregistered\n");
-}
-
-module_init(etrax_sync_serial_init);
-module_exit(etrax_sync_serial_exit);
-
-MODULE_LICENSE("GPL");
-
diff --git a/arch/cris/arch-v32/kernel/Makefile b/arch/cris/arch-v32/kernel/Makefile
deleted file mode 100644
index 2db7e4f7c1fa..000000000000
--- a/arch/cris/arch-v32/kernel/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-extra-y := head.o
-
-
-obj-y := entry.o traps.o irq.o debugport.o \
- process.o ptrace.o setup.o signal.o traps.o time.o \
- cache.o cacheflush.o
-
-obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o
-obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
-obj-$(CONFIG_MODULES) += crisksyms.o
-
-clean:
-
diff --git a/arch/cris/arch-v32/kernel/cache.c b/arch/cris/arch-v32/kernel/cache.c
deleted file mode 100644
index a080d2fa4803..000000000000
--- a/arch/cris/arch-v32/kernel/cache.c
+++ /dev/null
@@ -1,34 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <asm/io.h>
-#include <arch/cache.h>
-#include <arch/hwregs/dma.h>
-
-/* This file is used to workaround a cache bug, Guinness TR 106. */
-
-inline void flush_dma_descr(struct dma_descr_data *descr, int flush_buf)
-{
- /* Flush descriptor to make sure we get correct in_eop and after. */
- asm volatile ("ftagd [%0]" :: "r" (descr));
- /* Flush buffer pointed out by descriptor. */
- if (flush_buf)
- cris_flush_cache_range(phys_to_virt((unsigned)descr->buf),
- (unsigned)(descr->after - descr->buf));
-}
-EXPORT_SYMBOL(flush_dma_descr);
-
-void flush_dma_list(struct dma_descr_data *descr)
-{
- while (1) {
- flush_dma_descr(descr, 1);
- if (descr->eol)
- break;
- descr = phys_to_virt((unsigned)descr->next);
- }
-}
-EXPORT_SYMBOL(flush_dma_list);
-
-/* From cacheflush.S */
-EXPORT_SYMBOL(cris_flush_cache);
-/* From cacheflush.S */
-EXPORT_SYMBOL(cris_flush_cache_range);
diff --git a/arch/cris/arch-v32/kernel/cacheflush.S b/arch/cris/arch-v32/kernel/cacheflush.S
deleted file mode 100644
index 2a54d793f96c..000000000000
--- a/arch/cris/arch-v32/kernel/cacheflush.S
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
- .global cris_flush_cache_range
- .type cris_flush_cache_range, @function
-cris_flush_cache_range:
- move.d 1024, $r12
- cmp.d $r11, $r12
- bhi cris_flush_1KB
- nop
- add.d $r10, $r11
- ftagd [$r10]
-cris_flush_last:
- addq 32, $r10
- cmp.d $r11, $r10
- blt cris_flush_last
- ftagd [$r10]
- ret
- nop
-cris_flush_1KB:
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ftagd [$r10]
- addq 32, $r10
- ba cris_flush_cache_range
- sub.d $r12, $r11
- .size cris_flush_cache_range, . - cris_flush_cache_range
-
- .global cris_flush_cache
- .type cris_flush_cache, @function
-cris_flush_cache:
- moveq 0, $r10
-cris_flush_line:
- move.d 16*1024, $r11
- addq 16, $r10
- cmp.d $r10, $r11
- blt cris_flush_line
- fidxd [$r10]
- ret
- nop
- .size cris_flush_cache, . - cris_flush_cache
-
diff --git a/arch/cris/arch-v32/kernel/crisksyms.c b/arch/cris/arch-v32/kernel/crisksyms.c
deleted file mode 100644
index 8cc8ad1cb532..000000000000
--- a/arch/cris/arch-v32/kernel/crisksyms.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/irq.h>
-#include <arch/dma.h>
-#include <arch/intmem.h>
-#include <mach/pinmux.h>
-
-/* Functions for allocating DMA channels */
-EXPORT_SYMBOL(crisv32_request_dma);
-EXPORT_SYMBOL(crisv32_free_dma);
-
-/* Functions for handling internal RAM */
-EXPORT_SYMBOL(crisv32_intmem_alloc);
-EXPORT_SYMBOL(crisv32_intmem_free);
-EXPORT_SYMBOL(crisv32_intmem_phys_to_virt);
-EXPORT_SYMBOL(crisv32_intmem_virt_to_phys);
-
-/* Functions for handling pinmux */
-EXPORT_SYMBOL(crisv32_pinmux_alloc);
-EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
-EXPORT_SYMBOL(crisv32_pinmux_dealloc);
-EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
-
-/* Functions masking/unmasking interrupts */
-EXPORT_SYMBOL(crisv32_mask_irq);
-EXPORT_SYMBOL(crisv32_unmask_irq);
diff --git a/arch/cris/arch-v32/kernel/debugport.c b/arch/cris/arch-v32/kernel/debugport.c
deleted file mode 100644
index 69247fd2090a..000000000000
--- a/arch/cris/arch-v32/kernel/debugport.c
+++ /dev/null
@@ -1,232 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <linux/console.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/ser_defs.h>
-#include <hwregs/dma_defs.h>
-#include <mach/pinmux.h>
-
-struct dbg_port
-{
- unsigned char nbr;
- unsigned long instance;
- unsigned int started;
- unsigned long baudrate;
- unsigned char parity;
- unsigned int bits;
-};
-
-struct dbg_port ports[] =
-{
- {
- 0,
- regi_ser0,
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 1,
- regi_ser1,
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 2,
- regi_ser2,
- 0,
- 115200,
- 'N',
- 8
- },
- {
- 3,
- regi_ser3,
- 0,
- 115200,
- 'N',
- 8
- },
-#if CONFIG_ETRAX_SERIAL_PORTS == 5
- {
- 4,
- regi_ser4,
- 0,
- 115200,
- 'N',
- 8
- },
-#endif
-};
-
-static struct dbg_port *port =
-#if defined(CONFIG_ETRAX_DEBUG_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- &ports[3];
-#else
- NULL;
-#endif
-
-#ifdef CONFIG_ETRAX_KGDB
-static struct dbg_port *kgdb_port =
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- &ports[0];
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- &ports[1];
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- &ports[2];
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- &ports[3];
-#elif defined(CONFIG_ETRAX_KGDB_PORT4)
- &ports[4];
-#else
- NULL;
-#endif
-#endif
-
-static void start_port(struct dbg_port *p)
-{
- /* Set up serial port registers */
- reg_ser_rw_tr_ctrl tr_ctrl = {0};
- reg_ser_rw_tr_dma_en tr_dma_en = {0};
-
- reg_ser_rw_rec_ctrl rec_ctrl = {0};
- reg_ser_rw_tr_baud_div tr_baud_div = {0};
- reg_ser_rw_rec_baud_div rec_baud_div = {0};
-
- if (!p || p->started)
- return;
-
- p->started = 1;
-
- if (p->nbr == 1)
- crisv32_pinmux_alloc_fixed(pinmux_ser1);
- else if (p->nbr == 2)
- crisv32_pinmux_alloc_fixed(pinmux_ser2);
- else if (p->nbr == 3)
- crisv32_pinmux_alloc_fixed(pinmux_ser3);
-#if CONFIG_ETRAX_SERIAL_PORTS == 5
- else if (p->nbr == 4)
- crisv32_pinmux_alloc_fixed(pinmux_ser4);
-#endif
-
- tr_ctrl.base_freq = rec_ctrl.base_freq = regk_ser_f29_493;
- tr_dma_en.en = rec_ctrl.dma_mode = regk_ser_no;
- tr_baud_div.div = rec_baud_div.div = 29493000 / p->baudrate / 8;
- tr_ctrl.en = rec_ctrl.en = 1;
-
- if (p->parity == 'O') {
- tr_ctrl.par_en = regk_ser_yes;
- tr_ctrl.par = regk_ser_odd;
- rec_ctrl.par_en = regk_ser_yes;
- rec_ctrl.par = regk_ser_odd;
- } else if (p->parity == 'E') {
- tr_ctrl.par_en = regk_ser_yes;
- tr_ctrl.par = regk_ser_even;
- rec_ctrl.par_en = regk_ser_yes;
- rec_ctrl.par = regk_ser_odd;
- }
-
- if (p->bits == 7) {
- tr_ctrl.data_bits = regk_ser_bits7;
- rec_ctrl.data_bits = regk_ser_bits7;
- }
-
- REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div);
- REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div);
- REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en);
- REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl);
- REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl);
-}
-
-#ifdef CONFIG_ETRAX_KGDB
-/* Use polling to get a single character from the kernel debug port */
-int getDebugChar(void)
-{
- reg_ser_rs_stat_din stat;
- reg_ser_rw_ack_intr ack_intr = { 0 };
-
- do {
- stat = REG_RD(ser, kgdb_port->instance, rs_stat_din);
- } while (!stat.dav);
-
- /* Ack the data_avail interrupt. */
- ack_intr.dav = 1;
- REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr);
-
- return stat.data;
-}
-
-/* Use polling to put a single character to the kernel debug port */
-void putDebugChar(int val)
-{
- reg_ser_r_stat_din stat;
- do {
- stat = REG_RD(ser, kgdb_port->instance, r_stat_din);
- } while (!stat.tr_rdy);
- REG_WR_INT(ser, kgdb_port->instance, rw_dout, val);
-}
-#endif /* CONFIG_ETRAX_KGDB */
-
-static void __init early_putch(int c)
-{
- reg_ser_r_stat_din stat;
- /* Wait until transmitter is ready and send. */
- do
- stat = REG_RD(ser, port->instance, r_stat_din);
- while (!stat.tr_rdy);
- REG_WR_INT(ser, port->instance, rw_dout, c);
-}
-
-static void __init
-early_console_write(struct console *con, const char *s, unsigned n)
-{
- extern void reset_watchdog(void);
- int i;
-
- /* Send data. */
- for (i = 0; i < n; i++) {
- /* TODO: the '\n' -> '\n\r' translation should be done at the
- receiver. Remove it when the serial driver removes it. */
- if (s[i] == '\n')
- early_putch('\r');
- early_putch(s[i]);
- reset_watchdog();
- }
-}
-
-static struct console early_console_dev __initdata = {
- .name = "early",
- .write = early_console_write,
- .flags = CON_PRINTBUFFER | CON_BOOT,
- .index = -1
-};
-
-/* Register console for printk's, etc. */
-int __init init_etrax_debug(void)
-{
- start_port(port);
-
- /* Register an early console if a debug port was chosen. */
- register_console(&early_console_dev);
-
-#ifdef CONFIG_ETRAX_KGDB
- start_port(kgdb_port);
-#endif /* CONFIG_ETRAX_KGDB */
- return 0;
-}
diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S
deleted file mode 100644
index 0793a52b2c34..000000000000
--- a/arch/cris/arch-v32/kernel/entry.S
+++ /dev/null
@@ -1,909 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2000-2003 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Tobias Anderberg (tobiasa@axis.com), CRISv32 port.
- *
- * Code for the system-call and fault low-level handling routines.
- *
- * NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- *
- * Stack layout in 'ret_from_system_call':
- * ptrace needs to have all regs on the stack.
- * if the order here is changed, it needs to be
- * updated in fork.c:copy_process, signal.c:do_signal,
- * ptrace.c and ptrace.h
- *
- */
-
-#include <linux/linkage.h>
-#include <linux/sys.h>
-#include <asm/unistd.h>
-#include <asm/errno.h>
-#include <asm/thread_info.h>
-#include <asm/asm-offsets.h>
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/intr_vect_defs_asm.h>
-
- ;; Exported functions.
- .globl system_call
- .globl ret_from_intr
- .globl ret_from_fork
- .globl ret_from_kernel_thread
- .globl resume
- .globl multiple_interrupt
- .globl nmi_interrupt
- .globl spurious_interrupt
- .globl do_sigtrap
- .globl gdb_handle_exception
- .globl sys_call_table
-
- ; Check if preemptive kernel scheduling should be done.
-#ifdef CONFIG_PREEMPT
-_resume_kernel:
- di
- ; Load current task struct.
- movs.w -8192, $r0 ; THREAD_SIZE = 8192
- and.d $sp, $r0
-
- addoq +TI_preempt_count, $r0, $acr
- move.d [$acr], $r10 ; Preemption disabled?
- bne _Rexit
- nop
-
-_need_resched:
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r10
- btstq TIF_NEED_RESCHED, $r10 ; Check if need_resched is set.
- bpl _Rexit
- nop
-
- ; Do preemptive kernel scheduling.
- jsr preempt_schedule_irq
- nop
-
- ; Load new task struct.
- movs.w -8192, $r0 ; THREAD_SIZE = 8192.
- and.d $sp, $r0
-
- ; One more time with new task.
- ba _need_resched
- nop
-#else
-#define _resume_kernel _Rexit
-#endif
-
- ; Called at exit from fork. schedule_tail must be called to drop
- ; spinlock if CONFIG_PREEMPT.
- .type ret_from_fork,@function
-ret_from_fork:
- jsr schedule_tail
- nop
- ba ret_from_sys_call
- nop
- .size ret_from_fork, . - ret_from_fork
-
- .type ret_from_kernel_thread,@function
-ret_from_kernel_thread:
- jsr schedule_tail
- nop
- move.d $r2, $r10
- jsr $r1
- nop
- moveq 0, $r9 ; no syscall restarts, TYVM...
- ba ret_from_sys_call
- nop
- .size ret_from_kernel_thread, . - ret_from_kernel_thread
-
- .type ret_from_intr,@function
-ret_from_intr:
- moveq 0, $r9 ; not a syscall
-
- ;; Check for resched if preemptive kernel, or if we're going back to
- ;; user-mode. This test matches the user_regs(regs) macro. Don't simply
- ;; test CCS since that doesn't necessarily reflect what mode we'll
- ;; return into.
- addoq +PT_ccs, $sp, $acr
- move.d [$acr], $r0
- btstq 16, $r0 ; User-mode flag.
- bpl _resume_kernel
- .size ret_from_intr, . - ret_from_intr + 2 ; +2 includes the dslot.
-
- ; Note that di below is in delay slot.
- .type _resume_userspace,@function
-_resume_userspace:
- di ; So need_resched and sigpending don't change.
-
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- addoq +TI_flags, $r0, $acr ; current->work
- move.d [$acr], $r10
- and.d _TIF_WORK_MASK, $r10 ; Work to be done on return?
- bne _work_pending
- nop
- ba _Rexit
- nop
- .size _resume_userspace, . - _resume_userspace
-
- ;; The system_call is called by a BREAK instruction, which looks pretty
- ;; much like any other exception.
- ;;
- ;; System calls can't be made from interrupts but we still stack ERP
- ;; to have a complete stack frame.
- ;;
- ;; In r9 we have the wanted syscall number. Arguments come in r10,r11,r12,
- ;; r13,mof,srp
- ;;
- ;; This function looks on the _surface_ like spaghetti programming, but it's
- ;; really designed so that the fast-path does not force cache-loading of
- ;; non-used instructions. Only the non-common cases cause the outlined code
- ;; to run..
-
- .type system_call,@function
-system_call:
- ;; Stack-frame similar to the irq heads, which is reversed in
- ;; ret_from_sys_call.
-
- sub.d 92, $sp ; Skip EDA.
- movem $r13, [$sp]
- move.d $sp, $r8
- addq 14*4, $r8
- move.d $acr, $r0
- move $srs, $r1
- move $mof, $r2
- move $spc, $r3
- move $ccs, $r4
- move $srp, $r5
- move $erp, $r6
- move.d $r9, $r7 ; Store syscall number in EXS
- subq 4, $sp
- movem $r7, [$r8]
- ei ; Enable interrupts while processing syscalls.
- move.d $r10, [$sp]
-
- ; Set S-bit when kernel debugging to keep hardware breakpoints active.
-#ifdef CONFIG_ETRAX_KGDB
- move $ccs, $r0
- or.d (1<<9), $r0
- move $r0, $ccs
-#endif
-
- movs.w -ENOSYS, $r0
- addoq +PT_r10, $sp, $acr
- move.d $r0, [$acr]
-
- ;; Check if this process is syscall-traced.
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r0
- btstq TIF_SYSCALL_TRACE, $r0
- bmi _syscall_trace_entry
- nop
-
-_syscall_traced:
- ;; Check for sanity in the requested syscall number.
- cmpu.w NR_syscalls, $r9
- bhs ret_from_sys_call
- lslq 2, $r9 ; Multiply by 4, in the delay slot.
-
- ;; The location on the stack for the register structure is passed as a
- ;; seventh argument. Some system calls need this.
- move.d $sp, $r0
- subq 4, $sp
- move.d $r0, [$sp]
-
- ;; The registers carrying parameters (R10-R13) are intact. The optional
- ;; fifth and sixth parameters is in MOF and SRP respectively. Put them
- ;; back on the stack.
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $mof, [$sp]
-
- ;; Actually to the system call.
- addo.d +sys_call_table, $r9, $acr
- move.d [$acr], $acr
- jsr $acr
- nop
-
- addq 3*4, $sp ; Pop the mof, srp and regs parameters.
- addoq +PT_r10, $sp, $acr
- move.d $r10, [$acr] ; Save the return value.
-
- moveq 1, $r9 ; "Parameter" to ret_from_sys_call to
- ; show it was a sys call.
-
- ;; Fall through into ret_from_sys_call to return.
-
-ret_from_sys_call:
- ;; R9 is a parameter:
- ;; >= 1 from syscall
- ;; 0 from irq
-
- ;; Get the current task-struct pointer.
- movs.w -8192, $r0 ; THREAD_SIZE == 8192
- and.d $sp, $r0
-
- di ; Make sure need_resched and sigpending don't change.
-
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r1
- and.d _TIF_ALLWORK_MASK, $r1
- bne _syscall_exit_work
- nop
- .size system_call, . - system_call
-
- .type _Rexit,@function
-_Rexit:
-#if defined(CONFIG_TRACE_IRQFLAGS)
- addoq +PT_ccs, $sp, $acr
- move.d [$acr], $r0
- btstq 15, $r0 ; I1
- bpl 1f
- nop
- jsr trace_hardirqs_on
- nop
-1:
-#endif
-
- ;; This epilogue MUST match the prologues in multiple_interrupt, irq.h
- ;; and ptregs.h.
- addq 4, $sp ; Skip orig_r10.
- movem [$sp+], $r13 ; Registers R0-R13.
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- move [$sp+], $mof
- move [$sp+], $spc
- move [$sp+], $ccs
- move [$sp+], $srp
- move [$sp+], $erp
- addq 8, $sp ; Skip EXS, EDA.
- jump $erp
- rfe ; Restore condition code stack in delay-slot.
- .size _Rexit, . - _Rexit
-
- ;; We get here after doing a syscall if extra work might need to be done
- ;; perform syscall exit tracing if needed.
-
- .type _syscall_exit_work,@function
-_syscall_exit_work:
- ;; R0 contains current at this point and irq's are disabled.
-
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r1
- btstq TIF_SYSCALL_TRACE, $r1
- bpl _work_pending
- nop
- ei
- move.d $r9, $r1 ; Preserve R9.
- jsr do_syscall_trace
- nop
- move.d $r1, $r9
- ba _resume_userspace
- nop
- .size _syscall_exit_work, . - _syscall_exit_work
-
- .type _work_pending,@function
-_work_pending:
- addoq +TI_flags, $r0, $acr
- move.d [$acr], $r12 ; The thread_info_flags parameter.
- move.d $sp, $r11 ; The regs param.
- jsr do_work_pending
- move.d $r9, $r10 ; The syscall/irq param.
-
- ba _Rexit
- nop
- .size _work_pending, . - _work_pending
-
- ;; We get here as a sidetrack when we've entered a syscall with the
- ;; trace-bit set. We need to call do_syscall_trace and then continue
- ;; with the call.
-
-_syscall_trace_entry:
- ;; PT_r10 in the frame contains -ENOSYS as required, at this point.
-
- jsr do_syscall_trace
- nop
-
- ;; Now re-enter the syscall code to do the syscall itself. We need to
- ;; restore R9 here to contain the wanted syscall, and the other
- ;; parameter-bearing registers.
- addoq +PT_r9, $sp, $acr
- move.d [$acr], $r9
- addoq +PT_orig_r10, $sp, $acr
- move.d [$acr], $r10 ; PT_r10 is already -ENOSYS.
- addoq +PT_r11, $sp, $acr
- move.d [$acr], $r11
- addoq +PT_r12, $sp, $acr
- move.d [$acr], $r12
- addoq +PT_r13, $sp, $acr
- move.d [$acr], $r13
- addoq +PT_mof, $sp, $acr
- move [$acr], $mof
- addoq +PT_srp, $sp, $acr
- move [$acr], $srp
-
- ba _syscall_traced
- nop
-
- ;; Resume performs the actual task-switching, by switching stack
- ;; pointers. Input arguments are:
- ;;
- ;; R10 = prev
- ;; R11 = next
- ;; R12 = thread offset in task struct.
- ;;
- ;; Returns old current in R10.
-
- .type resume,@function
-resume:
- subq 4, $sp ; Make space for srp.
-
- add.d $r12, $r10 ; R10 = current tasks tss.
- addoq +THREAD_ccs, $r10, $acr
- move $srp, [$sp] ; Keep old/new PC on the stack.
- move $ccs, [$acr] ; Save IRQ enable state.
- di
-
- addoq +THREAD_usp, $r10, $acr
- subq 10*4, $sp ; Make room for R9.
- move $usp, [$acr] ; Save user-mode stackpointer.
-
- ;; See copy_thread for the reason why register R9 is saved.
- movem $r9, [$sp] ; Save non-scratch registers and R9.
-
- addoq +THREAD_ksp, $r10, $acr
- move.d $sp, $r10 ; Return last running task in R10.
- move.d $sp, [$acr] ; Save kernel SP for old task.
-
- and.d -8192, $r10 ; Get thread_info from stackpointer.
- addoq +TI_task, $r10, $acr
- add.d $r12, $r11 ; Find the new tasks tss.
- move.d [$acr], $r10 ; Get task.
- addoq +THREAD_ksp, $r11, $acr
- move.d [$acr], $sp ; Switch to new stackframe.
- addoq +THREAD_usp, $r11, $acr
- movem [$sp+], $r9 ; Restore non-scratch registers and R9.
-
- move [$acr], $usp ; Restore user-mode stackpointer.
-
- addoq +THREAD_ccs, $r11, $acr
- move.d [$sp+], $r11
- jump $r11 ; Restore PC.
- move [$acr], $ccs ; Restore IRQ enable status.
- .size resume, . - resume
-
-nmi_interrupt:
-
-;; If we receive a watchdog interrupt while it is not expected, then set
-;; up a canonical frame and dump register contents before dying.
-
- ;; This prologue MUST match the one in irq.h and the struct in ptregs.h!
- subq 12, $sp ; Skip EXS, EDA.
- move $nrp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- subq 14*4, $sp ; Make room for R0-R13.
- movem $r13, [$sp] ; Push R0-R13.
- subq 4, $sp
- move.d $r10, [$sp] ; Push orig_r10.
- move.d REG_ADDR(intr_vect, regi_irq, r_nmi), $r0
- move.d [$r0], $r0
- btstq REG_BIT(intr_vect, r_nmi, watchdog), $r0
- bpl 1f
- nop
- jsr handle_watchdog_bite ; In time.c.
- move.d $sp, $r10 ; Pointer to registers
-1: btstq REG_BIT(intr_vect, r_nmi, ext), $r0
- bpl 1f
- nop
- jsr handle_nmi
- move.d $sp, $r10 ; Pointer to registers
-1: addq 4, $sp ; Skip orig_r10
- movem [$sp+], $r13
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- move [$sp+], $mof
- move [$sp+], $spc
- move [$sp+], $ccs
- move [$sp+], $srp
- move [$sp+], $nrp
- addq 8, $sp ; Skip EXS, EDA.
- jump $nrp
- rfn
-
- .comm cause_of_death, 4 ;; Don't declare this anywhere.
-
-spurious_interrupt:
- di
- jump hard_reset_now
- nop
-
- ;; This handles the case when multiple interrupts arrive at the same
- ;; time. Jump to the first set interrupt bit in a priority fashion. The
- ;; hardware will call the unserved interrupts after the handler
- ;; finishes.
- .type multiple_interrupt, @function
-multiple_interrupt:
- ;; This prologue MUST match the one in irq.h and the struct in ptregs.h!
- subq 12, $sp ; Skip EXS, EDA.
- move $erp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- subq 14*4, $sp ; Make room for R0-R13.
- movem $r13, [$sp] ; Push R0-R13.
- subq 4, $sp
- move.d $r10, [$sp] ; Push orig_r10.
-
-; Set S-bit when kernel debugging to keep hardware breakpoints active.
-#ifdef CONFIG_ETRAX_KGDB
- move $ccs, $r0
- or.d (1<<9), $r0
- move $r0, $ccs
-#endif
-
- jsr crisv32_do_multiple
- move.d $sp, $r10
- jump ret_from_intr
- nop
- .size multiple_interrupt, . - multiple_interrupt
-
-do_sigtrap:
- ;; Sigtraps the process that executed the BREAK instruction. Creates a
- ;; frame that Rexit expects.
- subq 4, $sp
- move $eda, [$sp]
- subq 4, $sp
- move $exs, [$sp]
- subq 4, $sp
- move $erp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- di ; Need to disable irq's at this point.
- subq 14*4, $sp ; Make room for r0-r13.
- movem $r13, [$sp] ; Push the r0-r13 registers.
- subq 4, $sp
- move.d $r10, [$sp] ; Push orig_r10.
-
- movs.w -8192, $r9 ; THREAD_SIZE == 8192
- and.d $sp, $r9
-
- ;; thread_info as first parameter
- move.d $r9, $r10
- moveq 5, $r11 ; SIGTRAP as second argument.
- jsr ugdb_trap_user
- nop
- jump ret_from_intr ; Use the return routine for interrupts.
- nop
-
-gdb_handle_exception:
- subq 4, $sp
- move.d $r0, [$sp]
-#ifdef CONFIG_ETRAX_KGDB
- move $ccs, $r0 ; U-flag not affected by previous insns.
- btstq 16, $r0 ; Test the U-flag.
- bmi _ugdb_handle_exception ; Go to user mode debugging.
- nop ; Empty delay-slot (cannot pop R0 here).
- ba kgdb_handle_exception ; Go to kernel debugging.
- move.d [$sp+], $r0 ; Restore R0 in delay slot.
-#endif
-
-_ugdb_handle_exception:
- ba do_sigtrap ; SIGTRAP the offending process.
- move.d [$sp+], $r0 ; Restore R0 in delay slot.
-
- .data
-
- .section .rodata,"a"
-sys_call_table:
- .long sys_restart_syscall ; 0 - old "setup()" system call, used
- ; for restarting.
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_lchown16
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_stat
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_setuid16
- .long sys_getuid16
- .long sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_fstat
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_ni_syscall /* old gtty syscall holder */
- .long sys_access
- .long sys_nice
- .long sys_ni_syscall /* 35 old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_setgid16
- .long sys_getgid16
- .long sys_signal
- .long sys_geteuid16
- .long sys_getegid16 /* 50 */
- .long sys_acct
- .long sys_umount /* recycled never used phys( */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 */
- .long sys_ni_syscall /* old mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* old sys_olduname holder */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_sigaction
- .long sys_sgetmask
- .long sys_ssetmask
- .long sys_setreuid16 /* 70 */
- .long sys_setregid16
- .long sys_sigsuspend
- .long sys_sigpending
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_old_getrlimit
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_getgroups16 /* 80 */
- .long sys_setgroups16
- .long sys_select /* was old_select in Linux/E100 */
- .long sys_symlink
- .long sys_lstat
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_old_readdir
- .long sys_old_mmap /* 90 */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_fchown16 /* 95 */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* sys_ioperm in i386 */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* old sys_uname holder */
- .long sys_ni_syscall /* sys_iopl in i386 */
- .long sys_vhangup
- .long sys_ni_syscall /* old "idle" system call */
- .long sys_ni_syscall /* vm86old in i386 */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_sigreturn
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* sys_modify_ldt */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* for afs_syscall */
- .long sys_setfsuid16
- .long sys_setfsgid16
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_setresuid16
- .long sys_getresuid16 /* 165 */
- .long sys_ni_syscall /* sys_vm86 */
- .long sys_ni_syscall /* Old sys_query_module */
- .long sys_poll
- .long sys_ni_syscall /* Old nfsservctl */
- .long sys_setresgid16 /* 170 */
- .long sys_getresgid16
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_chown16
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* streams1 */
- .long sys_ni_syscall /* streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap2
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall /* sys_set_thread_area */
- .long sys_ni_syscall /* sys_get_thread_area */
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* sys_vserver */
- .long sys_ni_syscall /* sys_mbind */
- .long sys_ni_syscall /* 275 sys_get_mempolicy */
- .long sys_ni_syscall /* sys_set_mempolicy */
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_ni_syscall /* reserved for kexec */
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_ioprio_set
- .long sys_ioprio_get /* 290 */
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages
- .long sys_openat /* 295 */
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat
- .long sys_fstatat64 /* 300 */
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat
- .long sys_readlinkat /* 305 */
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll
- .long sys_unshare /* 310 */
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range
- .long sys_tee /* 315 */
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait
- .long sys_utimensat /* 320 */
- .long sys_signalfd
- .long sys_timerfd_create
- .long sys_eventfd
- .long sys_fallocate
- .long sys_timerfd_settime /* 325 */
- .long sys_timerfd_gettime
- .long sys_signalfd4
- .long sys_eventfd2
- .long sys_epoll_create1
- .long sys_dup3 /* 330 */
- .long sys_pipe2
- .long sys_inotify_init1
- .long sys_preadv
- .long sys_pwritev
- .long sys_setns /* 335 */
- .long sys_name_to_handle_at
- .long sys_open_by_handle_at
- .long sys_rt_tgsigqueueinfo
- .long sys_perf_event_open
- .long sys_recvmmsg /* 340 */
- .long sys_accept4
- .long sys_fanotify_init
- .long sys_fanotify_mark
- .long sys_prlimit64
- .long sys_clock_adjtime /* 345 */
- .long sys_syncfs
- .long sys_sendmmsg
- .long sys_process_vm_readv
- .long sys_process_vm_writev
- .long sys_kcmp /* 350 */
- .long sys_finit_module
- .long sys_sched_setattr
- .long sys_sched_getattr
- .long sys_renameat2
- .long sys_seccomp /* 355 */
- .long sys_getrandom
- .long sys_memfd_create
- .long sys_bpf
- .long sys_execveat
-
- /*
- * NOTE!! This doesn't have to be exact - we just have
- * to make sure we have _enough_ of the "sys_ni_syscall"
- * entries. Don't panic if you notice that this hasn't
- * been shrunk every time we add a new system call.
- */
-
- .rept NR_syscalls - (.-sys_call_table) / 4
- .long sys_ni_syscall
- .endr
-
diff --git a/arch/cris/arch-v32/kernel/fasttimer.c b/arch/cris/arch-v32/kernel/fasttimer.c
deleted file mode 100644
index 7452c70f61ff..000000000000
--- a/arch/cris/arch-v32/kernel/fasttimer.c
+++ /dev/null
@@ -1,793 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/fasttimer.c
- *
- * Fast timers for ETRAX FS
- *
- * Copyright (C) 2000-2006 Axis Communications AB, Lund, Sweden
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-
-#include <asm/irq.h>
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-#include <asm/fasttimer.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-
-/*
- * timer0 is running at 100MHz and generating jiffies timer ticks
- * at 100 or 1000 HZ.
- * fasttimer gives an API that gives timers that expire "between" the jiffies
- * giving microsecond resolution (10 ns).
- * fasttimer uses reg_timer_rw_trig register to get interrupt when
- * r_time reaches a certain value.
- */
-
-
-#define DEBUG_LOG_INCLUDED
-#define FAST_TIMER_LOG
-/* #define FAST_TIMER_TEST */
-
-#define FAST_TIMER_SANITY_CHECKS
-
-#ifdef FAST_TIMER_SANITY_CHECKS
-static int sanity_failed;
-#endif
-
-#define D1(x)
-#define D2(x)
-#define DP(x)
-
-static unsigned int fast_timer_running;
-static unsigned int fast_timers_added;
-static unsigned int fast_timers_started;
-static unsigned int fast_timers_expired;
-static unsigned int fast_timers_deleted;
-static unsigned int fast_timer_is_init;
-static unsigned int fast_timer_ints;
-
-struct fast_timer *fast_timer_list = NULL;
-
-#ifdef DEBUG_LOG_INCLUDED
-#define DEBUG_LOG_MAX 128
-static const char * debug_log_string[DEBUG_LOG_MAX];
-static unsigned long debug_log_value[DEBUG_LOG_MAX];
-static unsigned int debug_log_cnt;
-static unsigned int debug_log_cnt_wrapped;
-
-#define DEBUG_LOG(string, value) \
-{ \
- unsigned long log_flags; \
- local_irq_save(log_flags); \
- debug_log_string[debug_log_cnt] = (string); \
- debug_log_value[debug_log_cnt] = (unsigned long)(value); \
- if (++debug_log_cnt >= DEBUG_LOG_MAX) \
- { \
- debug_log_cnt = debug_log_cnt % DEBUG_LOG_MAX; \
- debug_log_cnt_wrapped = 1; \
- } \
- local_irq_restore(log_flags); \
-}
-#else
-#define DEBUG_LOG(string, value)
-#endif
-
-
-#define NUM_TIMER_STATS 16
-#ifdef FAST_TIMER_LOG
-struct fast_timer timer_added_log[NUM_TIMER_STATS];
-struct fast_timer timer_started_log[NUM_TIMER_STATS];
-struct fast_timer timer_expired_log[NUM_TIMER_STATS];
-#endif
-
-int timer_div_settings[NUM_TIMER_STATS];
-int timer_delay_settings[NUM_TIMER_STATS];
-
-struct work_struct fast_work;
-
-static void
-timer_trig_handler(struct work_struct *work);
-
-
-
-/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */
-inline void do_gettimeofday_fast(struct fasttime_t *tv)
-{
- tv->tv_jiff = jiffies;
- tv->tv_usec = GET_JIFFIES_USEC();
-}
-
-inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1)
-{
- /* Compare jiffies. Takes care of wrapping */
- if (time_before(t0->tv_jiff, t1->tv_jiff))
- return -1;
- else if (time_after(t0->tv_jiff, t1->tv_jiff))
- return 1;
-
- /* Compare us */
- if (t0->tv_usec < t1->tv_usec)
- return -1;
- else if (t0->tv_usec > t1->tv_usec)
- return 1;
- return 0;
-}
-
-/* Called with ints off */
-inline void start_timer_trig(unsigned long delay_us)
-{
- reg_timer_rw_ack_intr ack_intr = { 0 };
- reg_timer_rw_intr_mask intr_mask;
- reg_timer_rw_trig trig;
- reg_timer_rw_trig_cfg trig_cfg = { 0 };
- reg_timer_r_time r_time0;
- reg_timer_r_time r_time1;
- unsigned char trig_wrap;
- unsigned char time_wrap;
-
- r_time0 = REG_RD(timer, regi_timer0, r_time);
-
- D1(printk("start_timer_trig : %d us freq: %i div: %i\n",
- delay_us, freq_index, div));
- /* Clear trig irq */
- intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
- intr_mask.trig = 0;
- REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
-
- /* Set timer values and check if trigger wraps. */
- /* r_time is 100MHz (10 ns resolution) */
- trig_wrap = (trig = r_time0 + delay_us*(1000/10)) < r_time0;
-
- timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig;
- timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
-
- /* Ack interrupt */
- ack_intr.trig = 1;
- REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
-
- /* Start timer */
- REG_WR(timer, regi_timer0, rw_trig, trig);
- trig_cfg.tmr = regk_timer_time;
- REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
-
- /* Check if we have already passed the trig time */
- r_time1 = REG_RD(timer, regi_timer0, r_time);
- time_wrap = r_time1 < r_time0;
-
- if ((trig_wrap && !time_wrap) || (r_time1 < trig)) {
- /* No, Enable trig irq */
- intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
- intr_mask.trig = 1;
- REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
- fast_timers_started++;
- fast_timer_running = 1;
- } else {
- /* We have passed the time, disable trig point, ack intr */
- trig_cfg.tmr = regk_timer_off;
- REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
- REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
- /* call the int routine */
- INIT_WORK(&fast_work, timer_trig_handler);
- schedule_work(&fast_work);
- }
-
-}
-
-/* In version 1.4 this function takes 27 - 50 us */
-void start_one_shot_timer(struct fast_timer *t,
- fast_timer_function_type *function,
- unsigned long data,
- unsigned long delay_us,
- const char *name)
-{
- unsigned long flags;
- struct fast_timer *tmp;
-
- D1(printk("sft %s %d us\n", name, delay_us));
-
- local_irq_save(flags);
-
- do_gettimeofday_fast(&t->tv_set);
- tmp = fast_timer_list;
-
-#ifdef FAST_TIMER_SANITY_CHECKS
- /* Check so this is not in the list already... */
- while (tmp != NULL) {
- if (tmp == t) {
- printk(KERN_DEBUG
- "timer name: %s data: 0x%08lX already "
- "in list!\n", name, data);
- sanity_failed++;
- goto done;
- } else
- tmp = tmp->next;
- }
- tmp = fast_timer_list;
-#endif
-
- t->delay_us = delay_us;
- t->function = function;
- t->data = data;
- t->name = name;
-
- t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000;
- t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ;
- if (t->tv_expires.tv_usec > 1000000) {
- t->tv_expires.tv_usec -= 1000000;
- t->tv_expires.tv_jiff += HZ;
- }
-#ifdef FAST_TIMER_LOG
- timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_added++;
-
- /* Check if this should timeout before anything else */
- if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0) {
- /* Put first in list and modify the timer value */
- t->prev = NULL;
- t->next = fast_timer_list;
- if (fast_timer_list)
- fast_timer_list->prev = t;
- fast_timer_list = t;
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer_trig(delay_us);
- } else {
- /* Put in correct place in list */
- while (tmp->next &&
- fasttime_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0)
- tmp = tmp->next;
- /* Insert t after tmp */
- t->prev = tmp;
- t->next = tmp->next;
- if (tmp->next)
- {
- tmp->next->prev = t;
- }
- tmp->next = t;
- }
-
- D2(printk("start_one_shot_timer: %d us done\n", delay_us));
-
-done:
- local_irq_restore(flags);
-} /* start_one_shot_timer */
-
-static inline int fast_timer_pending (const struct fast_timer * t)
-{
- return (t->next != NULL) || (t->prev != NULL) || (t == fast_timer_list);
-}
-
-static inline int detach_fast_timer (struct fast_timer *t)
-{
- struct fast_timer *next, *prev;
- if (!fast_timer_pending(t))
- return 0;
- next = t->next;
- prev = t->prev;
- if (next)
- next->prev = prev;
- if (prev)
- prev->next = next;
- else
- fast_timer_list = next;
- fast_timers_deleted++;
- return 1;
-}
-
-int del_fast_timer(struct fast_timer * t)
-{
- unsigned long flags;
- int ret;
-
- local_irq_save(flags);
- ret = detach_fast_timer(t);
- t->next = t->prev = NULL;
- local_irq_restore(flags);
- return ret;
-} /* del_fast_timer */
-
-
-/* Interrupt routines or functions called in interrupt context */
-
-/* Timer interrupt handler for trig interrupts */
-
-static irqreturn_t
-timer_trig_interrupt(int irq, void *dev_id)
-{
- reg_timer_r_masked_intr masked_intr;
- /* Check if the timer interrupt is for us (a trig int) */
- masked_intr = REG_RD(timer, regi_timer0, r_masked_intr);
- if (!masked_intr.trig)
- return IRQ_NONE;
- timer_trig_handler(NULL);
- return IRQ_HANDLED;
-}
-
-static void timer_trig_handler(struct work_struct *work)
-{
- reg_timer_rw_ack_intr ack_intr = { 0 };
- reg_timer_rw_intr_mask intr_mask;
- reg_timer_rw_trig_cfg trig_cfg = { 0 };
- struct fast_timer *t;
- fast_timer_function_type *f;
- unsigned long d;
- unsigned long flags;
-
- /* We keep interrupts disabled not only when we modify the
- * fast timer list, but any time we hold a reference to a
- * timer in the list, since del_fast_timer may be called
- * from (another) interrupt context. Thus, the only time
- * when interrupts are enabled is when calling the timer
- * callback function.
- */
- local_irq_save(flags);
-
- /* Clear timer trig interrupt */
- intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
- intr_mask.trig = 0;
- REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
-
- /* First stop timer, then ack interrupt */
- /* Stop timer */
- trig_cfg.tmr = regk_timer_off;
- REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
-
- /* Ack interrupt */
- ack_intr.trig = 1;
- REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
-
- fast_timer_running = 0;
- fast_timer_ints++;
-
- t = fast_timer_list;
- while (t) {
- struct fasttime_t tv;
-
- /* Has it really expired? */
- do_gettimeofday_fast(&tv);
- D1(printk(KERN_DEBUG
- "t: %is %06ius\n", tv.tv_jiff, tv.tv_usec));
-
- if (fasttime_cmp(&t->tv_expires, &tv) <= 0) {
- /* Yes it has expired */
-#ifdef FAST_TIMER_LOG
- timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t;
-#endif
- fast_timers_expired++;
-
- /* Remove this timer before call, since it may reuse the timer */
- if (t->prev)
- t->prev->next = t->next;
- else
- fast_timer_list = t->next;
- if (t->next)
- t->next->prev = t->prev;
- t->prev = NULL;
- t->next = NULL;
-
- /* Save function callback data before enabling
- * interrupts, since the timer may be removed and we
- * don't know how it was allocated (e.g. ->function
- * and ->data may become overwritten after deletion
- * if the timer was stack-allocated).
- */
- f = t->function;
- d = t->data;
-
- if (f != NULL) {
- /* Run the callback function with interrupts
- * enabled. */
- local_irq_restore(flags);
- f(d);
- local_irq_save(flags);
- } else
- DEBUG_LOG("!trimertrig %i function==NULL!\n", fast_timer_ints);
- } else {
- /* Timer is to early, let's set it again using the normal routines */
- D1(printk(".\n"));
- }
-
- t = fast_timer_list;
- if (t != NULL) {
- /* Start next timer.. */
- long us = 0;
- struct fasttime_t tv;
-
- do_gettimeofday_fast(&tv);
-
- /* time_after_eq takes care of wrapping */
- if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff))
- us = ((t->tv_expires.tv_jiff - tv.tv_jiff) *
- 1000000 / HZ + t->tv_expires.tv_usec -
- tv.tv_usec);
-
- if (us > 0) {
- if (!fast_timer_running) {
-#ifdef FAST_TIMER_LOG
- timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
-#endif
- start_timer_trig(us);
- }
- break;
- } else {
- /* Timer already expired, let's handle it better late than never.
- * The normal loop handles it
- */
- D1(printk("e! %d\n", us));
- }
- }
- }
-
- local_irq_restore(flags);
-
- if (!t)
- D1(printk("ttrig stop!\n"));
-}
-
-static void wake_up_func(unsigned long data)
-{
- wait_queue_head_t *sleep_wait_p = (wait_queue_head_t*)data;
- wake_up(sleep_wait_p);
-}
-
-
-/* Useful API */
-
-void schedule_usleep(unsigned long us)
-{
- struct fast_timer t;
- wait_queue_head_t sleep_wait;
- init_waitqueue_head(&sleep_wait);
-
- D1(printk("schedule_usleep(%d)\n", us));
- start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us,
- "usleep");
- /* Uninterruptible sleep on the fast timer. (The condition is
- * somewhat redundant since the timer is what wakes us up.) */
- wait_event(sleep_wait, !fast_timer_pending(&t));
-
- D1(printk("done schedule_usleep(%d)\n", us));
-}
-
-#ifdef CONFIG_PROC_FS
-/* This value is very much based on testing */
-#define BIG_BUF_SIZE (500 + NUM_TIMER_STATS * 300)
-
-static int proc_fasttimer_show(struct seq_file *m, void *v)
-{
- unsigned long flags;
- int i = 0;
- int num_to_show;
- struct fasttime_t tv;
- struct fast_timer *t, *nextt;
-
- do_gettimeofday_fast(&tv);
-
- seq_printf(m, "Fast timers added: %i\n", fast_timers_added);
- seq_printf(m, "Fast timers started: %i\n", fast_timers_started);
- seq_printf(m, "Fast timer interrupts: %i\n", fast_timer_ints);
- seq_printf(m, "Fast timers expired: %i\n", fast_timers_expired);
- seq_printf(m, "Fast timers deleted: %i\n", fast_timers_deleted);
- seq_printf(m, "Fast timer running: %s\n",
- fast_timer_running ? "yes" : "no");
- seq_printf(m, "Current time: %lu.%06lu\n",
- (unsigned long)tv.tv_jiff,
- (unsigned long)tv.tv_usec);
-#ifdef FAST_TIMER_SANITY_CHECKS
- seq_printf(m, "Sanity failed: %i\n", sanity_failed);
-#endif
- seq_putc(m, '\n');
-
-#ifdef DEBUG_LOG_INCLUDED
- {
- int end_i = debug_log_cnt;
- i = 0;
-
- if (debug_log_cnt_wrapped)
- i = debug_log_cnt;
-
- while ((i != end_i || debug_log_cnt_wrapped)) {
- seq_printf(m, debug_log_string[i], debug_log_value[i]);
- if (seq_has_overflowed(m))
- return 0;
- i = (i+1) % DEBUG_LOG_MAX;
- }
- }
- seq_putc(m, '\n');
-#endif
-
- num_to_show = (fast_timers_started < NUM_TIMER_STATS ? fast_timers_started:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers started: %i\n", fast_timers_started);
- for (i = 0; i < num_to_show; i++) {
- int cur = (fast_timers_started - i - 1) % NUM_TIMER_STATS;
-
-#if 1 //ndef FAST_TIMER_LOG
- seq_printf(m, "div: %i delay: %i\n",
- timer_div_settings[cur],
- timer_delay_settings[cur]);
-#endif
-#ifdef FAST_TIMER_LOG
- t = &timer_started_log[cur];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
-#endif
- }
- seq_putc(m, '\n');
-
-#ifdef FAST_TIMER_LOG
- num_to_show = (fast_timers_added < NUM_TIMER_STATS ? fast_timers_added:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers added: %i\n", fast_timers_added);
- for (i = 0; i < num_to_show; i++) {
- t = &timer_added_log[(fast_timers_added - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-
- num_to_show = (fast_timers_expired < NUM_TIMER_STATS ? fast_timers_expired:
- NUM_TIMER_STATS);
- seq_printf(m, "Timers expired: %i\n", fast_timers_expired);
- for (i = 0; i < num_to_show; i++){
- t = &timer_expired_log[(fast_timers_expired - i - 1) % NUM_TIMER_STATS];
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- }
- seq_putc(m, '\n');
-#endif
-
- seq_puts(m, "Active timers:\n");
- local_irq_save(flags);
- t = fast_timer_list;
- while (t != NULL){
- nextt = t->next;
- local_irq_restore(flags);
- seq_printf(m, "%-14s s: %6lu.%06lu e: %6lu.%06lu d: %6li us data: 0x%08lX\n",
- t->name,
- (unsigned long)t->tv_set.tv_jiff,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_jiff,
- (unsigned long)t->tv_expires.tv_usec,
- t->delay_us,
- t->data);
- if (seq_has_overflowed(m))
- return 0;
- local_irq_save(flags);
- if (t->next != nextt)
- printk("timer removed!\n");
- t = nextt;
- }
- local_irq_restore(flags);
- return 0;
-}
-
-static int proc_fasttimer_open(struct inode *inode, struct file *file)
-{
- return single_open_size(file, proc_fasttimer_show, PDE_DATA(inode), BIG_BUF_SIZE);
-}
-
-static const struct file_operations proc_fasttimer_fops = {
- .open = proc_fasttimer_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-#endif /* PROC_FS */
-
-#ifdef FAST_TIMER_TEST
-static volatile unsigned long i = 0;
-static volatile int num_test_timeout = 0;
-static struct fast_timer tr[10];
-static int exp_num[10];
-
-static struct fasttime_t tv_exp[100];
-
-static void test_timeout(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
-
- num_test_timeout++;
-}
-
-static void test_timeout1(unsigned long data)
-{
- do_gettimeofday_fast(&tv_exp[data]);
- exp_num[data] = num_test_timeout;
- if (data < 7)
- {
- start_one_shot_timer(&tr[i], test_timeout1, i, 1000, "timeout1");
- i++;
- }
- num_test_timeout++;
-}
-
-DP(
-static char buf0[2000];
-static char buf1[2000];
-static char buf2[2000];
-static char buf3[2000];
-static char buf4[2000];
-);
-
-static char buf5[6000];
-static int j_u[1000];
-
-static void fast_timer_test(void)
-{
- int prev_num;
- int j;
-
- struct fasttime_t tv, tv0, tv1, tv2;
-
- printk("fast_timer_test() start\n");
- do_gettimeofday_fast(&tv);
-
- for (j = 0; j < 1000; j++)
- {
- j_u[j] = GET_JIFFIES_USEC();
- }
- for (j = 0; j < 100; j++)
- {
- do_gettimeofday_fast(&tv_exp[j]);
- }
- printk(KERN_DEBUG "fast_timer_test() %is %06i\n", tv.tv_jiff, tv.tv_usec);
-
- for (j = 0; j < 1000; j++)
- {
- printk(KERN_DEBUG "%i %i %i %i %i\n",
- j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]);
- j += 4;
- }
- for (j = 0; j < 100; j++)
- {
- printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n",
- tv_exp[j].tv_jiff, tv_exp[j].tv_usec,
- tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec,
- tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec,
- tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec,
- tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec);
- j += 4;
- }
- do_gettimeofday_fast(&tv0);
- start_one_shot_timer(&tr[i], test_timeout, i, 50000, "test0");
- DP(proc_fasttimer_read(buf0, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 70000, "test1");
- DP(proc_fasttimer_read(buf1, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 40000, "test2");
- DP(proc_fasttimer_read(buf2, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout, i, 60000, "test3");
- DP(proc_fasttimer_read(buf3, NULL, 0, 0, 0));
- i++;
- start_one_shot_timer(&tr[i], test_timeout1, i, 55000, "test4xx");
- DP(proc_fasttimer_read(buf4, NULL, 0, 0, 0));
- i++;
- do_gettimeofday_fast(&tv1);
-
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
-
- prev_num = num_test_timeout;
- while (num_test_timeout < i)
- {
- if (num_test_timeout != prev_num)
- prev_num = num_test_timeout;
- }
- do_gettimeofday_fast(&tv2);
- printk(KERN_INFO "Timers started %is %06i\n",
- tv0.tv_jiff, tv0.tv_usec);
- printk(KERN_INFO "Timers started at %is %06i\n",
- tv1.tv_jiff, tv1.tv_usec);
- printk(KERN_INFO "Timers done %is %06i\n",
- tv2.tv_jiff, tv2.tv_usec);
- DP(printk("buf0:\n");
- printk(buf0);
- printk("buf1:\n");
- printk(buf1);
- printk("buf2:\n");
- printk(buf2);
- printk("buf3:\n");
- printk(buf3);
- printk("buf4:\n");
- printk(buf4);
- );
- printk("buf5:\n");
- printk(buf5);
-
- printk("timers set:\n");
- for(j = 0; j<i; j++)
- {
- struct fast_timer *t = &tr[j];
- printk("%-10s set: %6is %06ius exp: %6is %06ius "
- "data: 0x%08X func: 0x%08X\n",
- t->name,
- t->tv_set.tv_jiff,
- t->tv_set.tv_usec,
- t->tv_expires.tv_jiff,
- t->tv_expires.tv_usec,
- t->data,
- t->function
- );
-
- printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n",
- t->delay_us,
- tv_exp[j].tv_jiff,
- tv_exp[j].tv_usec,
- exp_num[j],
- (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) *
- 1000000 + tv_exp[j].tv_usec -
- t->tv_expires.tv_usec);
- }
- proc_fasttimer_read(buf5, NULL, 0, 0, 0);
- printk("buf5 after all done:\n");
- printk(buf5);
- printk("fast_timer_test() done\n");
-}
-#endif
-
-
-int fast_timer_init(void)
-{
- /* For some reason, request_irq() hangs when called froom time_init() */
- if (!fast_timer_is_init)
- {
- printk("fast_timer_init()\n");
-
-#ifdef CONFIG_PROC_FS
- proc_create("fasttimer", 0, NULL, &proc_fasttimer_fops);
-#endif /* PROC_FS */
- if (request_irq(TIMER0_INTR_VECT, timer_trig_interrupt,
- IRQF_SHARED,
- "fast timer int", &fast_timer_list))
- printk(KERN_ERR "err: fasttimer irq\n");
- fast_timer_is_init = 1;
-#ifdef FAST_TIMER_TEST
- printk("do test\n");
- fast_timer_test();
-#endif
- }
- return 0;
-}
-__initcall(fast_timer_init);
diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S
deleted file mode 100644
index 92f9fb1f6845..000000000000
--- a/arch/cris/arch-v32/kernel/head.S
+++ /dev/null
@@ -1,439 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRISv32 kernel startup code.
- *
- * Copyright (C) 2003, Axis Communications AB
- */
-
-#include <linux/init.h>
-
-#define ASSEMBLER_MACROS_ONLY
-
-/*
- * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
- * -traditional must not be used when assembling this file.
- */
-#include <arch/memmap.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect.h>
-#include <hwregs/asm/mmu_defs_asm.h>
-#include <hwregs/asm/reg_map_asm.h>
-#include <mach/startup.inc>
-
-#define CRAMFS_MAGIC 0x28cd3d45
-#define JHEAD_MAGIC 0x1FF528A6
-#define JHEAD_SIZE 8
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-#define NAND_BOOT_MAGIC 0x9a9db001
-
- ;; NOTE: R8 and R9 carry information from the decompressor (if the
- ;; kernel was compressed). They must not be used in the code below
- ;; until they are read!
-
- ;; Exported symbols.
- .global etrax_irv
- .global romfs_start
- .global romfs_length
- .global romfs_in_flash
- .global nand_boot
- .global swapper_pg_dir
-
- __HEAD
-tstart:
- ;; This is the entry point of the kernel. The CPU is currently in
- ;; supervisor mode.
- ;;
- ;; 0x00000000 if flash.
- ;; 0x40004000 if DRAM.
- ;;
- di
-
- START_CLOCKS
-
- SETUP_WAIT_STATES
-
- GIO_INIT
-
- ;; Setup and enable the MMU. Use same configuration for both the data
- ;; and the instruction MMU.
- ;;
- ;; Note; 3 cycles is needed for a bank-select to take effect. Further;
- ;; bank 1 is the instruction MMU, bank 2 is the data MMU.
-
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 5) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
-#else
- move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
-#endif
-
- ;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
- move.d REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4) \
- | REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1
-
- ;; Enable certain page protections and setup linear mapping
- ;; for f,e,c,b,4,0.
-
- ;; ARTPEC-3:
- ;; c,d used for linear kernel mapping, up to 512 MB
- ;; e used for vmalloc
- ;; f unused, but page mapped to get page faults
-
- ;; ETRAX FS:
- ;; c used for linear kernel mapping, up to 256 MB
- ;; d used for vmalloc
- ;; e,f used for memory-mapped NOR flash
-
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
- | REG_STATE(mmu, rw_mm_cfg, acc, on) \
- | REG_STATE(mmu, rw_mm_cfg, ex, on) \
- | REG_STATE(mmu, rw_mm_cfg, inv, on) \
- | REG_STATE(mmu, rw_mm_cfg, seg_f, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_e, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_d, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
-#else
- move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
- | REG_STATE(mmu, rw_mm_cfg, acc, on) \
- | REG_STATE(mmu, rw_mm_cfg, ex, on) \
- | REG_STATE(mmu, rw_mm_cfg, inv, on) \
- | REG_STATE(mmu, rw_mm_cfg, seg_f, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_e, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_d, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_c, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_b, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_a, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_9, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_8, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_7, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_6, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_5, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_4, linear) \
- | REG_STATE(mmu, rw_mm_cfg, seg_3, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_2, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_1, page) \
- | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
-#endif
-
- ;; Update instruction MMU.
- move 1, $srs
- nop
- nop
- nop
- move $r0, $s2 ; kbase_hi.
- move $r1, $s1 ; kbase_lo.
- move $r2, $s0 ; mm_cfg, virtual memory configuration.
-
- ;; Update data MMU.
- move 2, $srs
- nop
- nop
- nop
- move $r0, $s2 ; kbase_hi.
- move $r1, $s1 ; kbase_lo
- move $r2, $s0 ; mm_cfg, virtual memory configuration.
-
- ;; Enable data and instruction MMU.
- move 0, $srs
- moveq 0xf, $r0 ; IMMU, DMMU, DCache, Icache on
- nop
- nop
- nop
- move $r0, $s0
- nop
- nop
- nop
-
- ; Check if starting from DRAM (network->RAM boot or unpacked
- ; compressed kernel), or directly from flash.
- lapcq ., $r0
- and.d 0x7fffffff, $r0 ; Mask off the non-cache bit.
- cmp.d 0x10000, $r0 ; Arbitrary, something above this code.
- blo _inflash0
- nop
-
- jump _inram ; Jump to cached RAM.
- nop
-
- ;; Jumpgate.
-_inflash0:
- jump _inflash
- nop
-
- ;; Put the following in a section so that storage for it can be
- ;; reclaimed after init is finished.
- __INIT
-
-_inflash:
-
- ;; Initialize DRAM.
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq _dram_initialized
- nop
-
-#if defined CONFIG_ETRAXFS
-#include "../mach-fs/dram_init.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../mach-a3/dram_init.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
-
-
-_dram_initialized:
- ;; Copy the text and data section to DRAM. This depends on that the
- ;; variables used below are correctly set up by the linker script.
- ;; The calculated value stored in R4 is used below.
- ;; Leave the cramfs file system (piggybacked after the kernel) in flash.
- moveq 0, $r0 ; Source.
- move.d text_start, $r1 ; Destination.
- move.d __vmlinux_end, $r2
- move.d $r2, $r4
- sub.d $r1, $r4
-1: move.w [$r0+], $r3
- move.w $r3, [$r1+]
- cmp.d $r2, $r1
- blo 1b
- nop
-
- ;; Check for cramfs.
- moveq 0, $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
- move.d [$r4], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne 1f
- nop
-
- ;; Set length and start of cramfs, set romfs_in_flash flag
- addoq +4, $r4, $acr
- move.d [$acr], $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
- add.d 0xf0000000, $r4 ; Add cached flash start in virtual memory.
- move.d romfs_start, $r1
- move.d $r4, [$r1]
-1: moveq 1, $r0
- move.d romfs_in_flash, $r1
- move.d $r0, [$r1]
-
- jump _start_it ; Jump to cached code.
- nop
-
-_inram:
- ;; Check if booting from NAND flash; if so, set appropriate flags
- ;; and move on.
- cmp.d NAND_BOOT_MAGIC, $r12
- bne move_cramfs ; not nand, jump
- moveq 1, $r0
- move.d nand_boot, $r1 ; tell axisflashmap we're booting from NAND
- move.d $r0, [$r1]
- moveq 0, $r0 ; tell axisflashmap romfs is not in
- move.d romfs_in_flash, $r1 ; (directly accessed) flash
- move.d $r0, [$r1]
- jump _start_it ; continue with boot
- nop
-
-move_cramfs:
- ;; kernel is in DRAM.
- ;; Must figure out if there is a piggybacked rootfs image or not.
- ;; Set romfs_length to 0 => no rootfs image available by default.
- moveq 0, $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
-
- ;; The kernel could have been unpacked to DRAM by the loader, but
- ;; the cramfs image could still be in the flash immediately
- ;; following the compressed kernel image. The loader passes the address
- ;; of the byte succeeding the last compressed byte in the flash in
- ;; register R9 when starting the kernel.
- cmp.d 0x0ffffff8, $r9
- bhs _no_romfs_in_flash ; R9 points outside the flash area.
- nop
- ;; cramfs rootfs might to be in flash. Check for it.
- move.d [$r9], $r0 ; cramfs_super.magic
- cmp.d CRAMFS_MAGIC, $r0
- bne _no_romfs_in_flash
- nop
-
- ;; found cramfs in flash. set address and size, and romfs_in_flash flag.
- addoq +4, $r9, $acr
- move.d [$acr], $r0
- move.d romfs_length, $r1
- move.d $r0, [$r1]
- add.d 0xf0000000, $r9 ; Add cached flash start in virtual memory.
- move.d romfs_start, $r1
- move.d $r9, [$r1]
- moveq 1, $r0
- move.d romfs_in_flash, $r1
- move.d $r0, [$r1]
-
- jump _start_it ; Jump to cached code.
- nop
-
-_no_romfs_in_flash:
- ;; No romfs in flash, so look for cramfs, or jffs2 with jhead,
- ;; after kernel in RAM, as is the case with network->RAM boot.
- ;; For cramfs, partition starts with magic and length.
- ;; For jffs2, a jhead is prepended which contains with magic and length.
- ;; The jhead is not part of the jffs2 partition however.
- move.d __bss_start, $r0
- move.d [$r0], $r1
- cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
- beq 2f ; yes, jump
- nop
- cmp.d JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic?
- bne 4f ; no, skip copy
- nop
- addq 4, $r0 ; location of jffs2 size
- move.d [$r0+], $r2 ; fetch jffs2 size -> r2
- ; r0 now points to start of jffs2
- ba 3f
- nop
-2:
- addoq +4, $r0, $acr ; location of cramfs size
- move.d [$acr], $r2 ; fetch cramfs size -> r2
- ; r0 still points to start of cramfs
-3:
- ;; Now, move the root fs to after kernel's BSS
-
- move.d _end, $r1 ; start of cramfs -> r1
- move.d romfs_start, $r3
- move.d $r1, [$r3] ; store at romfs_start (for axisflashmap)
- move.d romfs_length, $r3
- move.d $r2, [$r3] ; store size at romfs_length
-
- add.d $r2, $r0 ; copy from end and downwards
- add.d $r2, $r1
-
- lsrq 1, $r2 ; Size is in bytes, we copy words.
- addq 1, $r2
-1:
- move.w [$r0], $r3
- move.w $r3, [$r1]
- subq 2, $r0
- subq 2, $r1
- subq 1, $r2
- bne 1b
- nop
-
-4:
- ;; BSS move done.
- ;; Clear romfs_in_flash flag, as we now know romfs is in DRAM
- ;; Also clear nand_boot flag; if we got here, we know we've not
- ;; booted from NAND flash.
- moveq 0, $r0
- move.d romfs_in_flash, $r1
- move.d $r0, [$r1]
- moveq 0, $r0
- move.d nand_boot, $r1
- move.d $r0, [$r1]
-
- jump _start_it ; Jump to cached code.
- nop
-
-_start_it:
-
- ;; Check if kernel command line is supplied
- cmp.d COMMAND_LINE_MAGIC, $r10
- bne no_command_line
- nop
-
- move.d 256, $r13
- move.d cris_command_line, $r10
- or.d 0x80000000, $r11 ; Make it virtual
-1:
- move.b [$r11+], $r1
- move.b $r1, [$r10+]
- subq 1, $r13
- bne 1b
- nop
-
-no_command_line:
-
- ;; The kernel stack contains a task structure for each task. This
- ;; the initial kernel stack is in the same page as the init_task,
- ;; but starts at the top of the page, i.e. + 8192 bytes.
- move.d init_thread_union + 8192, $sp
- move.d ebp_start, $r0 ; Defined in linker-script.
- move $r0, $ebp
- move.d etrax_irv, $r1 ; Set the exception base register and pointer.
- move.d $r0, [$r1]
-
- ;; Clear the BSS region from _bss_start to _end.
- move.d __bss_start, $r0
- move.d _end, $r1
-1: clear.d [$r0+]
- cmp.d $r1, $r0
- blo 1b
- nop
-
- ; Initialize registers to increase determinism
- move.d __bss_start, $r0
- movem [$r0], $r13
-
-#ifdef CONFIG_ETRAX_L2CACHE
- jsr l2cache_init
- nop
-#endif
-
- jump start_kernel ; Jump to start_kernel() in init/main.c.
- nop
-
- .data
-etrax_irv:
- .dword 0
-
-; Variables for communication with the Axis flash map driver (axisflashmap),
-; and for setting up memory in arch/cris/kernel/setup.c .
-
-; romfs_start is set to the start of the root file system, if it exists
-; in directly accessible memory (i.e. NOR Flash when booting from Flash,
-; or RAM when booting directly from a network-downloaded RAM image)
-romfs_start:
- .dword 0
-
-; romfs_length is set to the size of the root file system image, if it exists
-; in directly accessible memory (see romfs_start). Otherwise it is set to 0.
-romfs_length:
- .dword 0
-
-; romfs_in_flash is set to 1 if the root file system resides in directly
-; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot
-; or NAND flash boot.
-romfs_in_flash:
- .dword 0
-
-; nand_boot is set to 1 when the kernel has been booted from NAND flash
-nand_boot:
- .dword 0
-
-swapper_pg_dir = 0xc0002000
-
- .section ".init.data", "aw"
-
-#if defined CONFIG_ETRAXFS
-#include "../mach-fs/hw_settings.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../mach-a3/hw_settings.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
deleted file mode 100644
index 414afd543232..000000000000
--- a/arch/cris/arch-v32/kernel/irq.c
+++ /dev/null
@@ -1,520 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <asm/irq.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/threads.h>
-#include <linux/spinlock.h>
-#include <linux/kernel_stat.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect.h>
-#include <hwregs/intr_vect_defs.h>
-
-#define CPU_FIXED -1
-
-/* IRQ masks (refer to comment for crisv32_do_multiple) */
-#if TIMER0_INTR_VECT - FIRST_IRQ < 32
-#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
-#undef TIMER_VECT1
-#else
-#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
-#define TIMER_VECT1
-#endif
-#ifdef CONFIG_ETRAX_KGDB
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
-#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
-#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
-#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
-#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
-#endif
-#endif
-
-DEFINE_SPINLOCK(irq_lock);
-
-struct cris_irq_allocation
-{
- int cpu; /* The CPU to which the IRQ is currently allocated. */
- cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
-};
-
-struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
- { [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
-
-static unsigned long irq_regs[NR_CPUS] =
-{
- regi_irq,
-};
-
-#if NR_REAL_IRQS > 32
-#define NBR_REGS 2
-#else
-#define NBR_REGS 1
-#endif
-
-unsigned long cpu_irq_counters[NR_CPUS];
-unsigned long irq_counters[NR_REAL_IRQS];
-
-/* From irq.c. */
-extern void weird_irq(void);
-
-/* From entry.S. */
-extern void system_call(void);
-extern void nmi_interrupt(void);
-extern void multiple_interrupt(void);
-extern void gdb_handle_exception(void);
-extern void i_mmu_refill(void);
-extern void i_mmu_invalid(void);
-extern void i_mmu_access(void);
-extern void i_mmu_execute(void);
-extern void d_mmu_refill(void);
-extern void d_mmu_invalid(void);
-extern void d_mmu_access(void);
-extern void d_mmu_write(void);
-
-/* From kgdb.c. */
-extern void kgdb_init(void);
-extern void breakpoint(void);
-
-/* From traps.c. */
-extern void breakh_BUG(void);
-
-/*
- * Build the IRQ handler stubs using macros from irq.h.
- */
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-BUILD_TIMER_IRQ(0x31, 0)
-#else
-BUILD_IRQ(0x31)
-#endif
-BUILD_IRQ(0x32)
-BUILD_IRQ(0x33)
-BUILD_IRQ(0x34)
-BUILD_IRQ(0x35)
-BUILD_IRQ(0x36)
-BUILD_IRQ(0x37)
-BUILD_IRQ(0x38)
-BUILD_IRQ(0x39)
-BUILD_IRQ(0x3a)
-BUILD_IRQ(0x3b)
-BUILD_IRQ(0x3c)
-BUILD_IRQ(0x3d)
-BUILD_IRQ(0x3e)
-BUILD_IRQ(0x3f)
-BUILD_IRQ(0x40)
-BUILD_IRQ(0x41)
-BUILD_IRQ(0x42)
-BUILD_IRQ(0x43)
-BUILD_IRQ(0x44)
-BUILD_IRQ(0x45)
-BUILD_IRQ(0x46)
-BUILD_IRQ(0x47)
-BUILD_IRQ(0x48)
-BUILD_IRQ(0x49)
-BUILD_IRQ(0x4a)
-#ifdef CONFIG_ETRAXFS
-BUILD_TIMER_IRQ(0x4b, 0)
-#else
-BUILD_IRQ(0x4b)
-#endif
-BUILD_IRQ(0x4c)
-BUILD_IRQ(0x4d)
-BUILD_IRQ(0x4e)
-BUILD_IRQ(0x4f)
-BUILD_IRQ(0x50)
-#if MACH_IRQS > 32
-BUILD_IRQ(0x51)
-BUILD_IRQ(0x52)
-BUILD_IRQ(0x53)
-BUILD_IRQ(0x54)
-BUILD_IRQ(0x55)
-BUILD_IRQ(0x56)
-BUILD_IRQ(0x57)
-BUILD_IRQ(0x58)
-BUILD_IRQ(0x59)
-BUILD_IRQ(0x5a)
-BUILD_IRQ(0x5b)
-BUILD_IRQ(0x5c)
-BUILD_IRQ(0x5d)
-BUILD_IRQ(0x5e)
-BUILD_IRQ(0x5f)
-BUILD_IRQ(0x60)
-BUILD_IRQ(0x61)
-BUILD_IRQ(0x62)
-BUILD_IRQ(0x63)
-BUILD_IRQ(0x64)
-BUILD_IRQ(0x65)
-BUILD_IRQ(0x66)
-BUILD_IRQ(0x67)
-BUILD_IRQ(0x68)
-BUILD_IRQ(0x69)
-BUILD_IRQ(0x6a)
-BUILD_IRQ(0x6b)
-BUILD_IRQ(0x6c)
-BUILD_IRQ(0x6d)
-BUILD_IRQ(0x6e)
-BUILD_IRQ(0x6f)
-BUILD_IRQ(0x70)
-#endif
-
-/* Pointers to the low-level handlers. */
-static void (*interrupt[MACH_IRQS])(void) = {
- IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
- IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
- IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
- IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
- IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
- IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
- IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
- IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
- IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
- IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
- IRQ0x4f_interrupt, IRQ0x50_interrupt,
-#if MACH_IRQS > 32
- IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
- IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
- IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
- IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
- IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
- IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
- IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
- IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
- IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
- IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
- IRQ0x6f_interrupt, IRQ0x70_interrupt,
-#endif
-};
-
-void
-block_irq(int irq, int cpu)
-{
- int intr_mask;
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- /* Remember, 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32) {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 0);
- intr_mask &= ~(1 << (irq - FIRST_IRQ));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 0, intr_mask);
- } else {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
- intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 1, intr_mask);
- }
- spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-void
-unblock_irq(int irq, int cpu)
-{
- int intr_mask;
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- /* Remember, 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32) {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 0);
- intr_mask |= (1 << (irq - FIRST_IRQ));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 0, intr_mask);
- } else {
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
- intr_mask |= (1 << (irq - FIRST_IRQ - 32));
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
- 1, intr_mask);
- }
- spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-/* Find out which CPU the irq should be allocated to. */
-static int irq_cpu(int irq)
-{
- int cpu;
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- cpu = irq_allocations[irq - FIRST_IRQ].cpu;
-
- /* Fixed interrupts stay on the local CPU. */
- if (cpu == CPU_FIXED)
- {
- spin_unlock_irqrestore(&irq_lock, flags);
- return smp_processor_id();
- }
-
-
- /* Let the interrupt stay if possible */
- if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask))
- goto out;
-
- /* IRQ must be moved to another CPU. */
- cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask);
- irq_allocations[irq - FIRST_IRQ].cpu = cpu;
-out:
- spin_unlock_irqrestore(&irq_lock, flags);
- return cpu;
-}
-
-void crisv32_mask_irq(int irq)
-{
- int cpu;
-
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- block_irq(irq, cpu);
-}
-
-void crisv32_unmask_irq(int irq)
-{
- unblock_irq(irq, irq_cpu(irq));
-}
-
-
-static void enable_crisv32_irq(struct irq_data *data)
-{
- crisv32_unmask_irq(data->irq);
-}
-
-static void disable_crisv32_irq(struct irq_data *data)
-{
- crisv32_mask_irq(data->irq);
-}
-
-static int set_affinity_crisv32_irq(struct irq_data *data,
- const struct cpumask *dest, bool force)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&irq_lock, flags);
- irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
- spin_unlock_irqrestore(&irq_lock, flags);
- return 0;
-}
-
-static struct irq_chip crisv32_irq_type = {
- .name = "CRISv32",
- .irq_shutdown = disable_crisv32_irq,
- .irq_enable = enable_crisv32_irq,
- .irq_disable = disable_crisv32_irq,
- .irq_set_affinity = set_affinity_crisv32_irq,
-};
-
-void
-set_exception_vector(int n, irqvectptr addr)
-{
- etrax_irv->v[n] = (irqvectptr) addr;
-}
-
-extern void do_IRQ(int irq, struct pt_regs * regs);
-
-void
-crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
-{
- /* Interrupts that may not be moved to another CPU may
- * skip blocking. This is currently only valid for the
- * timer IRQ and the IPI and is used for the timer
- * interrupt to avoid watchdog starvation.
- */
- if (!block) {
- do_IRQ(irq, regs);
- return;
- }
-
- block_irq(irq, smp_processor_id());
- do_IRQ(irq, regs);
-
- unblock_irq(irq, irq_cpu(irq));
-}
-
-/* If multiple interrupts occur simultaneously we get a multiple
- * interrupt from the CPU and software has to sort out which
- * interrupts that happened. There are two special cases here:
- *
- * 1. Timer interrupts may never be blocked because of the
- * watchdog (refer to comment in include/asr/arch/irq.h)
- * 2. GDB serial port IRQs are unhandled here and will be handled
- * as a single IRQ when it strikes again because the GDB
- * stubb wants to save the registers in its own fashion.
- */
-void
-crisv32_do_multiple(struct pt_regs* regs)
-{
- int cpu;
- int mask;
- int masked[NBR_REGS];
- int bit;
- int i;
-
- cpu = smp_processor_id();
-
- /* An extra irq_enter here to prevent softIRQs to run after
- * each do_IRQ. This will decrease the interrupt latency.
- */
- irq_enter();
-
- for (i = 0; i < NBR_REGS; i++) {
- /* Get which IRQs that happened. */
- masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- r_masked_vect, i);
-
- /* Calculate new IRQ mask with these IRQs disabled. */
- mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
- mask &= ~masked[i];
-
- /* Timer IRQ is never masked */
-#ifdef TIMER_VECT1
- if ((i == 1) && (masked[0] & TIMER_MASK))
- mask |= TIMER_MASK;
-#else
- if ((i == 0) && (masked[0] & TIMER_MASK))
- mask |= TIMER_MASK;
-#endif
- /* Block all the IRQs */
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
-
- /* Check for timer IRQ and handle it special. */
-#ifdef TIMER_VECT1
- if ((i == 1) && (masked[i] & TIMER_MASK)) {
- masked[i] &= ~TIMER_MASK;
- do_IRQ(TIMER0_INTR_VECT, regs);
- }
-#else
- if ((i == 0) && (masked[i] & TIMER_MASK)) {
- masked[i] &= ~TIMER_MASK;
- do_IRQ(TIMER0_INTR_VECT, regs);
- }
-#endif
- }
-
-#ifdef IGNORE_MASK
- /* Remove IRQs that can't be handled as multiple. */
- masked[0] &= ~IGNORE_MASK;
-#endif
-
- /* Handle the rest of the IRQs. */
- for (i = 0; i < NBR_REGS; i++) {
- for (bit = 0; bit < 32; bit++) {
- if (masked[i] & (1 << bit))
- do_IRQ(bit + FIRST_IRQ + i*32, regs);
- }
- }
-
- /* Unblock all the IRQs. */
- for (i = 0; i < NBR_REGS; i++) {
- mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
- mask |= masked[i];
- REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
- }
-
- /* This irq_exit() will trigger the soft IRQs. */
- irq_exit();
-}
-
-static int crisv32_irq_map(struct irq_domain *h, unsigned int virq,
- irq_hw_number_t hw_irq_num)
-{
- irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq);
-
- return 0;
-}
-
-static struct irq_domain_ops crisv32_irq_ops = {
- .map = crisv32_irq_map,
- .xlate = irq_domain_xlate_onecell,
-};
-
-/*
- * This is called by start_kernel. It fixes the IRQ masks and setup the
- * interrupt vector table to point to bad_interrupt pointers.
- */
-void __init
-init_IRQ(void)
-{
- int i;
- int j;
- reg_intr_vect_rw_mask vect_mask = {0};
- struct device_node *np;
- struct irq_domain *domain;
-
- /* Clear all interrupts masks. */
- for (i = 0; i < NBR_REGS; i++)
- REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
-
- for (i = 0; i < 256; i++)
- etrax_irv->v[i] = weird_irq;
-
- np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
- domain = irq_domain_add_legacy(np, NBR_INTR_VECT - FIRST_IRQ,
- FIRST_IRQ, FIRST_IRQ,
- &crisv32_irq_ops, NULL);
- BUG_ON(!domain);
- irq_set_default_host(domain);
- of_node_put(np);
-
- for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT && j < MACH_IRQS; i++, j++)
- set_exception_vector(i, interrupt[j]);
-
- /* Mark Timer and IPI IRQs as CPU local */
- irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
- irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU);
- irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
- irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU);
-
- set_exception_vector(0x00, nmi_interrupt);
- set_exception_vector(0x30, multiple_interrupt);
-
- /* Set up handler for various MMU bus faults. */
- set_exception_vector(0x04, i_mmu_refill);
- set_exception_vector(0x05, i_mmu_invalid);
- set_exception_vector(0x06, i_mmu_access);
- set_exception_vector(0x07, i_mmu_execute);
- set_exception_vector(0x08, d_mmu_refill);
- set_exception_vector(0x09, d_mmu_invalid);
- set_exception_vector(0x0a, d_mmu_access);
- set_exception_vector(0x0b, d_mmu_write);
-
-#ifdef CONFIG_BUG
- /* Break 14 handler, used to implement cheap BUG(). */
- set_exception_vector(0x1e, breakh_BUG);
-#endif
-
- /* The system-call trap is reached by "break 13". */
- set_exception_vector(0x1d, system_call);
-
- /* Exception handlers for debugging, both user-mode and kernel-mode. */
-
- /* Break 8. */
- set_exception_vector(0x18, gdb_handle_exception);
- /* Hardware single step. */
- set_exception_vector(0x3, gdb_handle_exception);
- /* Hardware breakpoint. */
- set_exception_vector(0xc, gdb_handle_exception);
-
-#ifdef CONFIG_ETRAX_KGDB
- kgdb_init();
- /* Everything is set up; now trap the kernel. */
- breakpoint();
-#endif
-}
-
diff --git a/arch/cris/arch-v32/kernel/kgdb.c b/arch/cris/arch-v32/kernel/kgdb.c
deleted file mode 100644
index 3d6f516763a5..000000000000
--- a/arch/cris/arch-v32/kernel/kgdb.c
+++ /dev/null
@@ -1,1593 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/cris/arch-v32/kernel/kgdb.c
- *
- * CRIS v32 version by Orjan Friberg, Axis Communications AB.
- *
- * S390 version
- * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
- * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
- *
- * Originally written by Glenn Engel, Lake Stevens Instrument Division
- *
- * Contributed by HP Systems
- *
- * Modified for SPARC by Stu Grossman, Cygnus Support.
- *
- * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
- * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
- *
- * Copyright (C) 1995 Andreas Busse
- */
-
-/* FIXME: Check the documentation. */
-
-/*
- * kgdb usage notes:
- * -----------------
- *
- * If you select CONFIG_ETRAX_KGDB in the configuration, the kernel will be
- * built with different gcc flags: "-g" is added to get debug infos, and
- * "-fomit-frame-pointer" is omitted to make debugging easier. Since the
- * resulting kernel will be quite big (approx. > 7 MB), it will be stripped
- * before compresion. Such a kernel will behave just as usually, except if
- * given a "debug=<device>" command line option. (Only serial devices are
- * allowed for <device>, i.e. no printers or the like; possible values are
- * machine depedend and are the same as for the usual debug device, the one
- * for logging kernel messages.) If that option is given and the device can be
- * initialized, the kernel will connect to the remote gdb in trap_init(). The
- * serial parameters are fixed to 8N1 and 115200 bps, for easyness of
- * implementation.
- *
- * To start a debugging session, start that gdb with the debugging kernel
- * image (the one with the symbols, vmlinux.debug) named on the command line.
- * This file will be used by gdb to get symbol and debugging infos about the
- * kernel. Next, select remote debug mode by
- * target remote <device>
- * where <device> is the name of the serial device over which the debugged
- * machine is connected. Maybe you have to adjust the baud rate by
- * set remotebaud <rate>
- * or also other parameters with stty:
- * shell stty ... </dev/...
- * If the kernel to debug has already booted, it waited for gdb and now
- * connects, and you'll see a breakpoint being reported. If the kernel isn't
- * running yet, start it now. The order of gdb and the kernel doesn't matter.
- * Another thing worth knowing about in the getting-started phase is how to
- * debug the remote protocol itself. This is activated with
- * set remotedebug 1
- * gdb will then print out each packet sent or received. You'll also get some
- * messages about the gdb stub on the console of the debugged machine.
- *
- * If all that works, you can use lots of the usual debugging techniques on
- * the kernel, e.g. inspecting and changing variables/memory, setting
- * breakpoints, single stepping and so on. It's also possible to interrupt the
- * debugged kernel by pressing C-c in gdb. Have fun! :-)
- *
- * The gdb stub is entered (and thus the remote gdb gets control) in the
- * following situations:
- *
- * - If breakpoint() is called. This is just after kgdb initialization, or if
- * a breakpoint() call has been put somewhere into the kernel source.
- * (Breakpoints can of course also be set the usual way in gdb.)
- * In eLinux, we call breakpoint() in init/main.c after IRQ initialization.
- *
- * - If there is a kernel exception, i.e. bad_super_trap() or die_if_kernel()
- * are entered. All the CPU exceptions are mapped to (more or less..., see
- * the hard_trap_info array below) appropriate signal, which are reported
- * to gdb. die_if_kernel() is usually called after some kind of access
- * error and thus is reported as SIGSEGV.
- *
- * - When panic() is called. This is reported as SIGABRT.
- *
- * - If C-c is received over the serial line, which is treated as
- * SIGINT.
- *
- * Of course, all these signals are just faked for gdb, since there is no
- * signal concept as such for the kernel. It also isn't possible --obviously--
- * to set signal handlers from inside gdb, or restart the kernel with a
- * signal.
- *
- * Current limitations:
- *
- * - While the kernel is stopped, interrupts are disabled for safety reasons
- * (i.e., variables not changing magically or the like). But this also
- * means that the clock isn't running anymore, and that interrupts from the
- * hardware may get lost/not be served in time. This can cause some device
- * errors...
- *
- * - When single-stepping, only one instruction of the current thread is
- * executed, but interrupts are allowed for that time and will be serviced
- * if pending. Be prepared for that.
- *
- * - All debugging happens in kernel virtual address space. There's no way to
- * access physical memory not mapped in kernel space, or to access user
- * space. A way to work around this is using get_user_long & Co. in gdb
- * expressions, but only for the current process.
- *
- * - Interrupting the kernel only works if interrupts are currently allowed,
- * and the interrupt of the serial line isn't blocked by some other means
- * (IPL too high, disabled, ...)
- *
- * - The gdb stub is currently not reentrant, i.e. errors that happen therein
- * (e.g. accessing invalid memory) may not be caught correctly. This could
- * be removed in future by introducing a stack of struct registers.
- *
- */
-
-/*
- * To enable debugger support, two things need to happen. One, a
- * call to kgdb_init() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint().
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
- * baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- */
-
-
-#include <linux/string.h>
-#include <linux/signal.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/linkage.h>
-#include <linux/reboot.h>
-
-#include <asm/setup.h>
-#include <asm/ptrace.h>
-
-#include <asm/irq.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/intr_vect_defs.h>
-#include <hwregs/ser_defs.h>
-
-/* From entry.S. */
-extern void gdb_handle_exception(void);
-/* From kgdb_asm.S. */
-extern void kgdb_handle_exception(void);
-
-static int kgdb_started = 0;
-
-/********************************* Register image ****************************/
-
-typedef
-struct register_image
-{
- /* Offset */
- unsigned int r0; /* 0x00 */
- unsigned int r1; /* 0x04 */
- unsigned int r2; /* 0x08 */
- unsigned int r3; /* 0x0C */
- unsigned int r4; /* 0x10 */
- unsigned int r5; /* 0x14 */
- unsigned int r6; /* 0x18 */
- unsigned int r7; /* 0x1C */
- unsigned int r8; /* 0x20; Frame pointer (if any) */
- unsigned int r9; /* 0x24 */
- unsigned int r10; /* 0x28 */
- unsigned int r11; /* 0x2C */
- unsigned int r12; /* 0x30 */
- unsigned int r13; /* 0x34 */
- unsigned int sp; /* 0x38; R14, Stack pointer */
- unsigned int acr; /* 0x3C; R15, Address calculation register. */
-
- unsigned char bz; /* 0x40; P0, 8-bit zero register */
- unsigned char vr; /* 0x41; P1, Version register (8-bit) */
- unsigned int pid; /* 0x42; P2, Process ID */
- unsigned char srs; /* 0x46; P3, Support register select (8-bit) */
- unsigned short wz; /* 0x47; P4, 16-bit zero register */
- unsigned int exs; /* 0x49; P5, Exception status */
- unsigned int eda; /* 0x4D; P6, Exception data address */
- unsigned int mof; /* 0x51; P7, Multiply overflow register */
- unsigned int dz; /* 0x55; P8, 32-bit zero register */
- unsigned int ebp; /* 0x59; P9, Exception base pointer */
- unsigned int erp; /* 0x5D; P10, Exception return pointer. Contains the PC we are interested in. */
- unsigned int srp; /* 0x61; P11, Subroutine return pointer */
- unsigned int nrp; /* 0x65; P12, NMI return pointer */
- unsigned int ccs; /* 0x69; P13, Condition code stack */
- unsigned int usp; /* 0x6D; P14, User mode stack pointer */
- unsigned int spc; /* 0x71; P15, Single step PC */
- unsigned int pc; /* 0x75; Pseudo register (for the most part set to ERP). */
-
-} registers;
-
-typedef
-struct bp_register_image
-{
- /* Support register bank 0. */
- unsigned int s0_0;
- unsigned int s1_0;
- unsigned int s2_0;
- unsigned int s3_0;
- unsigned int s4_0;
- unsigned int s5_0;
- unsigned int s6_0;
- unsigned int s7_0;
- unsigned int s8_0;
- unsigned int s9_0;
- unsigned int s10_0;
- unsigned int s11_0;
- unsigned int s12_0;
- unsigned int s13_0;
- unsigned int s14_0;
- unsigned int s15_0;
-
- /* Support register bank 1. */
- unsigned int s0_1;
- unsigned int s1_1;
- unsigned int s2_1;
- unsigned int s3_1;
- unsigned int s4_1;
- unsigned int s5_1;
- unsigned int s6_1;
- unsigned int s7_1;
- unsigned int s8_1;
- unsigned int s9_1;
- unsigned int s10_1;
- unsigned int s11_1;
- unsigned int s12_1;
- unsigned int s13_1;
- unsigned int s14_1;
- unsigned int s15_1;
-
- /* Support register bank 2. */
- unsigned int s0_2;
- unsigned int s1_2;
- unsigned int s2_2;
- unsigned int s3_2;
- unsigned int s4_2;
- unsigned int s5_2;
- unsigned int s6_2;
- unsigned int s7_2;
- unsigned int s8_2;
- unsigned int s9_2;
- unsigned int s10_2;
- unsigned int s11_2;
- unsigned int s12_2;
- unsigned int s13_2;
- unsigned int s14_2;
- unsigned int s15_2;
-
- /* Support register bank 3. */
- unsigned int s0_3; /* BP_CTRL */
- unsigned int s1_3; /* BP_I0_START */
- unsigned int s2_3; /* BP_I0_END */
- unsigned int s3_3; /* BP_D0_START */
- unsigned int s4_3; /* BP_D0_END */
- unsigned int s5_3; /* BP_D1_START */
- unsigned int s6_3; /* BP_D1_END */
- unsigned int s7_3; /* BP_D2_START */
- unsigned int s8_3; /* BP_D2_END */
- unsigned int s9_3; /* BP_D3_START */
- unsigned int s10_3; /* BP_D3_END */
- unsigned int s11_3; /* BP_D4_START */
- unsigned int s12_3; /* BP_D4_END */
- unsigned int s13_3; /* BP_D5_START */
- unsigned int s14_3; /* BP_D5_END */
- unsigned int s15_3; /* BP_RESERVED */
-
-} support_registers;
-
-enum register_name
-{
- R0, R1, R2, R3,
- R4, R5, R6, R7,
- R8, R9, R10, R11,
- R12, R13, SP, ACR,
-
- BZ, VR, PID, SRS,
- WZ, EXS, EDA, MOF,
- DZ, EBP, ERP, SRP,
- NRP, CCS, USP, SPC,
- PC,
-
- S0, S1, S2, S3,
- S4, S5, S6, S7,
- S8, S9, S10, S11,
- S12, S13, S14, S15
-
-};
-
-/* The register sizes of the registers in register_name. An unimplemented register
- is designated by size 0 in this array. */
-static int register_size[] =
-{
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
-
- 1, 1, 4, 1,
- 2, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
-
- 4,
-
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4, 4,
- 4, 4, 4
-
-};
-
-/* Contains the register image of the kernel.
- (Global so that they can be reached from assembler code.) */
-registers reg;
-support_registers sreg;
-
-/************** Prototypes for local library functions ***********************/
-
-/* Copy of strcpy from libc. */
-static char *gdb_cris_strcpy(char *s1, const char *s2);
-
-/* Copy of strlen from libc. */
-static int gdb_cris_strlen(const char *s);
-
-/* Copy of memchr from libc. */
-static void *gdb_cris_memchr(const void *s, int c, int n);
-
-/* Copy of strtol from libc. Does only support base 16. */
-static int gdb_cris_strtol(const char *s, char **endptr, int base);
-
-/********************** Prototypes for local functions. **********************/
-
-/* Write a value to a specified register regno in the register image
- of the current thread. */
-static int write_register(int regno, char *val);
-
-/* Read a value from a specified register in the register image. Returns the
- status of the read operation. The register value is returned in valptr. */
-static int read_register(char regno, unsigned int *valptr);
-
-/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
-int getDebugChar(void);
-
-/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
-void putDebugChar(int val);
-
-/* Convert the memory, pointed to by mem into hexadecimal representation.
- Put the result in buf, and return a pointer to the last character
- in buf (null). */
-static char *mem2hex(char *buf, unsigned char *mem, int count);
-
-/* Put the content of the array, in binary representation, pointed to by buf
- into memory pointed to by mem, and return a pointer to
- the character after the last byte written. */
-static unsigned char *bin2mem(unsigned char *mem, unsigned char *buf, int count);
-
-/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
- returned. */
-static void getpacket(char *buffer);
-
-/* Send $<data>#<checksum> from the <data> in the array buffer. */
-static void putpacket(char *buffer);
-
-/* Build and send a response packet in order to inform the host the
- stub is stopped. */
-static void stub_is_stopped(int sigval);
-
-/* All expected commands are sent from remote.c. Send a response according
- to the description in remote.c. Not static since it needs to be reached
- from assembler code. */
-void handle_exception(int sigval);
-
-/* Performs a complete re-start from scratch. ETRAX specific. */
-static void kill_restart(void);
-
-/******************** Prototypes for global functions. ***********************/
-
-/* The string str is prepended with the GDB printout token and sent. */
-void putDebugString(const unsigned char *str, int len);
-
-/* A static breakpoint to be used at startup. */
-void breakpoint(void);
-
-/* Avoid warning as the internal_stack is not used in the C-code. */
-#define USEDVAR(name) { if (name) { ; } }
-#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
-
-/********************************** Packet I/O ******************************/
-/* BUFMAX defines the maximum number of characters in
- inbound/outbound buffers */
-/* FIXME: How do we know it's enough? */
-#define BUFMAX 512
-
-/* Run-length encoding maximum length. Send 64 at most. */
-#define RUNLENMAX 64
-
-/* The inbound/outbound buffers used in packet I/O */
-static char input_buffer[BUFMAX];
-static char output_buffer[BUFMAX];
-
-/* Error and warning messages. */
-enum error_type
-{
- SUCCESS, E01, E02, E03, E04, E05, E06, E07, E08
-};
-
-static char *error_message[] =
-{
- "",
- "E01 Set current or general thread - H[c,g] - internal error.",
- "E02 Change register content - P - cannot change read-only register.",
- "E03 Thread is not alive.", /* T, not used. */
- "E04 The command is not supported - [s,C,S,!,R,d,r] - internal error.",
- "E05 Change register content - P - the register is not implemented..",
- "E06 Change memory content - M - internal error.",
- "E07 Change register content - P - the register is not stored on the stack",
- "E08 Invalid parameter"
-};
-
-/********************************** Breakpoint *******************************/
-/* Use an internal stack in the breakpoint and interrupt response routines.
- FIXME: How do we know the size of this stack is enough?
- Global so it can be reached from assembler code. */
-#define INTERNAL_STACK_SIZE 1024
-char internal_stack[INTERNAL_STACK_SIZE];
-
-/* Due to the breakpoint return pointer, a state variable is needed to keep
- track of whether it is a static (compiled) or dynamic (gdb-invoked)
- breakpoint to be handled. A static breakpoint uses the content of register
- ERP as it is whereas a dynamic breakpoint requires subtraction with 2
- in order to execute the instruction. The first breakpoint is static; all
- following are assumed to be dynamic. */
-static int dynamic_bp = 0;
-
-/********************************* String library ****************************/
-/* Single-step over library functions creates trap loops. */
-
-/* Copy char s2[] to s1[]. */
-static char*
-gdb_cris_strcpy(char *s1, const char *s2)
-{
- char *s = s1;
-
- for (s = s1; (*s++ = *s2++) != '\0'; )
- ;
- return s1;
-}
-
-/* Find length of s[]. */
-static int
-gdb_cris_strlen(const char *s)
-{
- const char *sc;
-
- for (sc = s; *sc != '\0'; sc++)
- ;
- return (sc - s);
-}
-
-/* Find first occurrence of c in s[n]. */
-static void*
-gdb_cris_memchr(const void *s, int c, int n)
-{
- const unsigned char uc = c;
- const unsigned char *su;
-
- for (su = s; 0 < n; ++su, --n)
- if (*su == uc)
- return (void *)su;
- return NULL;
-}
-/******************************* Standard library ****************************/
-/* Single-step over library functions creates trap loops. */
-/* Convert string to long. */
-static int
-gdb_cris_strtol(const char *s, char **endptr, int base)
-{
- char *s1;
- char *sd;
- int x = 0;
-
- for (s1 = (char*)s; (sd = gdb_cris_memchr(hex_asc, *s1, base)) != NULL; ++s1)
- x = x * base + (sd - hex_asc);
-
- if (endptr) {
- /* Unconverted suffix is stored in endptr unless endptr is NULL. */
- *endptr = s1;
- }
-
- return x;
-}
-
-/********************************* Register image ****************************/
-
-/* Write a value to a specified register in the register image of the current
- thread. Returns status code SUCCESS, E02, E05 or E08. */
-static int
-write_register(int regno, char *val)
-{
- int status = SUCCESS;
-
- if (regno >= R0 && regno <= ACR) {
- /* Consecutive 32-bit registers. */
- if (hex2bin((unsigned char *)&reg.r0 + (regno - R0) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
-
- } else if (regno == BZ || regno == VR || regno == WZ || regno == DZ) {
- /* Read-only registers. */
- status = E02;
-
- } else if (regno == PID) {
- /* 32-bit register. (Even though we already checked SRS and WZ, we cannot
- combine this with the EXS - SPC write since SRS and WZ have different size.) */
- if (hex2bin((unsigned char *)&reg.pid, val, sizeof(unsigned int)))
- status = E08;
-
- } else if (regno == SRS) {
- /* 8-bit register. */
- if (hex2bin((unsigned char *)&reg.srs, val, sizeof(unsigned char)))
- status = E08;
-
- } else if (regno >= EXS && regno <= SPC) {
- /* Consecutive 32-bit registers. */
- if (hex2bin((unsigned char *)&reg.exs + (regno - EXS) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
-
- } else if (regno == PC) {
- /* Pseudo-register. Treat as read-only. */
- status = E02;
-
- } else if (regno >= S0 && regno <= S15) {
- /* 32-bit registers. */
- if (hex2bin((unsigned char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int),
- val, sizeof(unsigned int)))
- status = E08;
- } else {
- /* Non-existing register. */
- status = E05;
- }
- return status;
-}
-
-/* Read a value from a specified register in the register image. Returns the
- value in the register or -1 for non-implemented registers. */
-static int
-read_register(char regno, unsigned int *valptr)
-{
- int status = SUCCESS;
-
- /* We read the zero registers from the register struct (instead of just returning 0)
- to catch errors. */
-
- if (regno >= R0 && regno <= ACR) {
- /* Consecutive 32-bit registers. */
- *valptr = *(unsigned int *)((char *)&reg.r0 + (regno - R0) * sizeof(unsigned int));
-
- } else if (regno == BZ || regno == VR) {
- /* Consecutive 8-bit registers. */
- *valptr = (unsigned int)(*(unsigned char *)
- ((char *)&reg.bz + (regno - BZ) * sizeof(char)));
-
- } else if (regno == PID) {
- /* 32-bit register. */
- *valptr = *(unsigned int *)((char *)&reg.pid);
-
- } else if (regno == SRS) {
- /* 8-bit register. */
- *valptr = (unsigned int)(*(unsigned char *)((char *)&reg.srs));
-
- } else if (regno == WZ) {
- /* 16-bit register. */
- *valptr = (unsigned int)(*(unsigned short *)(char *)&reg.wz);
-
- } else if (regno >= EXS && regno <= PC) {
- /* Consecutive 32-bit registers. */
- *valptr = *(unsigned int *)((char *)&reg.exs + (regno - EXS) * sizeof(unsigned int));
-
- } else if (regno >= S0 && regno <= S15) {
- /* Consecutive 32-bit registers, located elsewhere. */
- *valptr = *(unsigned int *)((char *)&sreg.s0_0 + (reg.srs * 16 * sizeof(unsigned int)) + (regno - S0) * sizeof(unsigned int));
-
- } else {
- /* Non-existing register. */
- status = E05;
- }
- return status;
-
-}
-
-/********************************** Packet I/O ******************************/
-/* Convert the memory, pointed to by mem into hexadecimal representation.
- Put the result in buf, and return a pointer to the last character
- in buf (null). */
-
-static char *
-mem2hex(char *buf, unsigned char *mem, int count)
-{
- int i;
- int ch;
-
- if (mem == NULL) {
- /* Invalid address, caught by 'm' packet handler. */
- for (i = 0; i < count; i++) {
- *buf++ = '0';
- *buf++ = '0';
- }
- } else {
- /* Valid mem address. */
- for (i = 0; i < count; i++) {
- ch = *mem++;
- buf = hex_byte_pack(buf, ch);
- }
- }
- /* Terminate properly. */
- *buf = '\0';
- return buf;
-}
-
-/* Same as mem2hex, but puts it in network byte order. */
-static char *
-mem2hex_nbo(char *buf, unsigned char *mem, int count)
-{
- int i;
- int ch;
-
- mem += count - 1;
- for (i = 0; i < count; i++) {
- ch = *mem--;
- buf = hex_byte_pack(buf, ch);
- }
-
- /* Terminate properly. */
- *buf = '\0';
- return buf;
-}
-
-/* Put the content of the array, in binary representation, pointed to by buf
- into memory pointed to by mem, and return a pointer to the character after
- the last byte written.
- Gdb will escape $, #, and the escape char (0x7d). */
-static unsigned char*
-bin2mem(unsigned char *mem, unsigned char *buf, int count)
-{
- int i;
- unsigned char *next;
- for (i = 0; i < count; i++) {
- /* Check for any escaped characters. Be paranoid and
- only unescape chars that should be escaped. */
- if (*buf == 0x7d) {
- next = buf + 1;
- if (*next == 0x3 || *next == 0x4 || *next == 0x5D) {
- /* #, $, ESC */
- buf++;
- *buf += 0x20;
- }
- }
- *mem++ = *buf++;
- }
- return mem;
-}
-
-/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
- returned. */
-static void
-getpacket(char *buffer)
-{
- unsigned char checksum;
- unsigned char xmitcsum;
- int i;
- int count;
- char ch;
-
- do {
- while((ch = getDebugChar ()) != '$')
- /* Wait for the start character $ and ignore all other characters */;
- checksum = 0;
- xmitcsum = -1;
- count = 0;
- /* Read until a # or the end of the buffer is reached */
- while (count < BUFMAX) {
- ch = getDebugChar();
- if (ch == '#')
- break;
- checksum = checksum + ch;
- buffer[count] = ch;
- count = count + 1;
- }
-
- if (count >= BUFMAX)
- continue;
-
- buffer[count] = 0;
-
- if (ch == '#') {
- xmitcsum = hex_to_bin(getDebugChar()) << 4;
- xmitcsum += hex_to_bin(getDebugChar());
- if (checksum != xmitcsum) {
- /* Wrong checksum */
- putDebugChar('-');
- } else {
- /* Correct checksum */
- putDebugChar('+');
- /* If sequence characters are received, reply with them */
- if (buffer[2] == ':') {
- putDebugChar(buffer[0]);
- putDebugChar(buffer[1]);
- /* Remove the sequence characters from the buffer */
- count = gdb_cris_strlen(buffer);
- for (i = 3; i <= count; i++)
- buffer[i - 3] = buffer[i];
- }
- }
- }
- } while (checksum != xmitcsum);
-}
-
-/* Send $<data>#<checksum> from the <data> in the array buffer. */
-
-static void
-putpacket(char *buffer)
-{
- int checksum;
- int runlen;
- int encode;
-
- do {
- char *src = buffer;
- putDebugChar('$');
- checksum = 0;
- while (*src) {
- /* Do run length encoding */
- putDebugChar(*src);
- checksum += *src;
- runlen = 0;
- while (runlen < RUNLENMAX && *src == src[runlen]) {
- runlen++;
- }
- if (runlen > 3) {
- /* Got a useful amount */
- putDebugChar ('*');
- checksum += '*';
- encode = runlen + ' ' - 4;
- putDebugChar(encode);
- checksum += encode;
- src += runlen;
- } else {
- src++;
- }
- }
- putDebugChar('#');
- putDebugChar(hex_asc_hi(checksum));
- putDebugChar(hex_asc_lo(checksum));
- } while(kgdb_started && (getDebugChar() != '+'));
-}
-
-/* The string str is prepended with the GDB printout token and sent. Required
- in traditional implementations. */
-void
-putDebugString(const unsigned char *str, int len)
-{
- /* Move SPC forward if we are single-stepping. */
- asm("spchere:");
- asm("move $spc, $r10");
- asm("cmp.d spchere, $r10");
- asm("bne nosstep");
- asm("nop");
- asm("move.d spccont, $r10");
- asm("move $r10, $spc");
- asm("nosstep:");
-
- output_buffer[0] = 'O';
- mem2hex(&output_buffer[1], (unsigned char *)str, len);
- putpacket(output_buffer);
-
- asm("spccont:");
-}
-
-/********************************** Handle exceptions ************************/
-/* Build and send a response packet in order to inform the host the
- stub is stopped. TAAn...:r...;n...:r...;n...:r...;
- AA = signal number
- n... = register number (hex)
- r... = register contents
- n... = `thread'
- r... = thread process ID. This is a hex integer.
- n... = other string not starting with valid hex digit.
- gdb should ignore this n,r pair and go on to the next.
- This way we can extend the protocol. */
-static void
-stub_is_stopped(int sigval)
-{
- char *ptr = output_buffer;
- unsigned int reg_cont;
-
- /* Send trap type (converted to signal) */
-
- *ptr++ = 'T';
- ptr = hex_byte_pack(ptr, sigval);
-
- if (((reg.exs & 0xff00) >> 8) == 0xc) {
-
- /* Some kind of hardware watchpoint triggered. Find which one
- and determine its type (read/write/access). */
- int S, bp, trig_bits = 0, rw_bits = 0;
- int trig_mask = 0;
- unsigned int *bp_d_regs = &sreg.s3_3;
- /* In a lot of cases, the stopped data address will simply be EDA.
- In some cases, we adjust it to match the watched data range.
- (We don't want to change the actual EDA though). */
- unsigned int stopped_data_address;
- /* The S field of EXS. */
- S = (reg.exs & 0xffff0000) >> 16;
-
- if (S & 1) {
- /* Instruction watchpoint. */
- /* FIXME: Check against, and possibly adjust reported EDA. */
- } else {
- /* Data watchpoint. Find the one that triggered. */
- for (bp = 0; bp < 6; bp++) {
-
- /* Dx_RD, Dx_WR in the S field of EXS for this BP. */
- int bitpos_trig = 1 + bp * 2;
- /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
- int bitpos_config = 2 + bp * 4;
-
- /* Get read/write trig bits for this BP. */
- trig_bits = (S & (3 << bitpos_trig)) >> bitpos_trig;
-
- /* Read/write config bits for this BP. */
- rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
- if (trig_bits) {
- /* Sanity check: the BP shouldn't trigger for accesses
- that it isn't configured for. */
- if ((rw_bits == 0x1 && trig_bits != 0x1) ||
- (rw_bits == 0x2 && trig_bits != 0x2))
- panic("Invalid r/w trigging for this BP");
-
- /* Mark this BP as trigged for future reference. */
- trig_mask |= (1 << bp);
-
- if (reg.eda >= bp_d_regs[bp * 2] &&
- reg.eda <= bp_d_regs[bp * 2 + 1]) {
- /* EDA within range for this BP; it must be the one
- we're looking for. */
- stopped_data_address = reg.eda;
- break;
- }
- }
- }
- if (bp < 6) {
- /* Found a trigged BP with EDA within its configured data range. */
- } else if (trig_mask) {
- /* Something triggered, but EDA doesn't match any BP's range. */
- for (bp = 0; bp < 6; bp++) {
- /* Dx_BPRD, Dx_BPWR in BP_CTRL for this BP. */
- int bitpos_config = 2 + bp * 4;
-
- /* Read/write config bits for this BP (needed later). */
- rw_bits = (sreg.s0_3 & (3 << bitpos_config)) >> bitpos_config;
-
- if (trig_mask & (1 << bp)) {
- /* EDA within 31 bytes of the configured start address? */
- if (reg.eda + 31 >= bp_d_regs[bp * 2]) {
- /* Changing the reported address to match
- the start address of the first applicable BP. */
- stopped_data_address = bp_d_regs[bp * 2];
- break;
- } else {
- /* We continue since we might find another useful BP. */
- printk("EDA doesn't match trigged BP's range");
- }
- }
- }
- }
-
- /* No match yet? */
- BUG_ON(bp >= 6);
- /* Note that we report the type according to what the BP is configured
- for (otherwise we'd never report an 'awatch'), not according to how
- it trigged. We did check that the trigged bits match what the BP is
- configured for though. */
- if (rw_bits == 0x1) {
- /* read */
- strncpy(ptr, "rwatch", 6);
- ptr += 6;
- } else if (rw_bits == 0x2) {
- /* write */
- strncpy(ptr, "watch", 5);
- ptr += 5;
- } else if (rw_bits == 0x3) {
- /* access */
- strncpy(ptr, "awatch", 6);
- ptr += 6;
- } else {
- panic("Invalid r/w bits for this BP.");
- }
-
- *ptr++ = ':';
- /* Note that we don't read_register(EDA, ...) */
- ptr = mem2hex_nbo(ptr, (unsigned char *)&stopped_data_address, register_size[EDA]);
- *ptr++ = ';';
- }
- }
- /* Only send PC, frame and stack pointer. */
- read_register(PC, &reg_cont);
- ptr = hex_byte_pack(ptr, PC);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[PC]);
- *ptr++ = ';';
-
- read_register(R8, &reg_cont);
- ptr = hex_byte_pack(ptr, R8);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[R8]);
- *ptr++ = ';';
-
- read_register(SP, &reg_cont);
- ptr = hex_byte_pack(ptr, SP);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[SP]);
- *ptr++ = ';';
-
- /* Send ERP as well; this will save us an entire register fetch in some cases. */
- read_register(ERP, &reg_cont);
- ptr = hex_byte_pack(ptr, ERP);
- *ptr++ = ':';
- ptr = mem2hex(ptr, (unsigned char *)&reg_cont, register_size[ERP]);
- *ptr++ = ';';
-
- /* null-terminate and send it off */
- *ptr = 0;
- putpacket(output_buffer);
-}
-
-/* Returns the size of an instruction that has a delay slot. */
-
-int insn_size(unsigned long pc)
-{
- unsigned short opcode = *(unsigned short *)pc;
- int size = 0;
-
- switch ((opcode & 0x0f00) >> 8) {
- case 0x0:
- case 0x9:
- case 0xb:
- size = 2;
- break;
- case 0xe:
- case 0xf:
- size = 6;
- break;
- case 0xd:
- /* Could be 4 or 6; check more bits. */
- if ((opcode & 0xff) == 0xff)
- size = 4;
- else
- size = 6;
- break;
- default:
- panic("Couldn't find size of opcode 0x%x at 0x%lx\n", opcode, pc);
- }
-
- return size;
-}
-
-void register_fixup(int sigval)
-{
- /* Compensate for ACR push at the beginning of exception handler. */
- reg.sp += 4;
-
- /* Standard case. */
- reg.pc = reg.erp;
- if (reg.erp & 0x1) {
- /* Delay slot bit set. Report as stopped on proper instruction. */
- if (reg.spc) {
- /* Rely on SPC if set. */
- reg.pc = reg.spc;
- } else {
- /* Calculate the PC from the size of the instruction
- that the delay slot we're in belongs to. */
- reg.pc += insn_size(reg.erp & ~1) - 1 ;
- }
- }
-
- if ((reg.exs & 0x3) == 0x0) {
- /* Bits 1 - 0 indicate the type of memory operation performed
- by the interrupted instruction. 0 means no memory operation,
- and EDA is undefined in that case. We zero it to avoid confusion. */
- reg.eda = 0;
- }
-
- if (sigval == SIGTRAP) {
- /* Break 8, single step or hardware breakpoint exception. */
-
- /* Check IDX field of EXS. */
- if (((reg.exs & 0xff00) >> 8) == 0x18) {
-
- /* Break 8. */
-
- /* Static (compiled) breakpoints must return to the next instruction
- in order to avoid infinite loops (default value of ERP). Dynamic
- (gdb-invoked) must subtract the size of the break instruction from
- the ERP so that the instruction that was originally in the break
- instruction's place will be run when we return from the exception. */
- if (!dynamic_bp) {
- /* Assuming that all breakpoints are dynamic from now on. */
- dynamic_bp = 1;
- } else {
-
- /* Only if not in a delay slot. */
- if (!(reg.erp & 0x1)) {
- reg.erp -= 2;
- reg.pc -= 2;
- }
- }
-
- } else if (((reg.exs & 0xff00) >> 8) == 0x3) {
- /* Single step. */
- /* Don't fiddle with S1. */
-
- } else if (((reg.exs & 0xff00) >> 8) == 0xc) {
-
- /* Hardware watchpoint exception. */
-
- /* SPC has been updated so that we will get a single step exception
- when we return, but we don't want that. */
- reg.spc = 0;
-
- /* Don't fiddle with S1. */
- }
-
- } else if (sigval == SIGINT) {
- /* Nothing special. */
- }
-}
-
-static void insert_watchpoint(char type, int addr, int len)
-{
- /* Breakpoint/watchpoint types (GDB terminology):
- 0 = memory breakpoint for instructions
- (not supported; done via memory write instead)
- 1 = hardware breakpoint for instructions (supported)
- 2 = write watchpoint (supported)
- 3 = read watchpoint (supported)
- 4 = access watchpoint (supported) */
-
- if (type < '1' || type > '4') {
- output_buffer[0] = 0;
- return;
- }
-
- /* Read watchpoints are set as access watchpoints, because of GDB's
- inability to deal with pure read watchpoints. */
- if (type == '3')
- type = '4';
-
- if (type == '1') {
- /* Hardware (instruction) breakpoint. */
- /* Bit 0 in BP_CTRL holds the configuration for I0. */
- if (sreg.s0_3 & 0x1) {
- /* Already in use. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
- /* Configure. */
- sreg.s1_3 = addr;
- sreg.s2_3 = (addr + len - 1);
- sreg.s0_3 |= 1;
- } else {
- int bp;
- unsigned int *bp_d_regs = &sreg.s3_3;
-
- /* The watchpoint allocation scheme is the simplest possible.
- For example, if a region is watched for read and
- a write watch is requested, a new watchpoint will
- be used. Also, if a watch for a region that is already
- covered by one or more existing watchpoints, a new
- watchpoint will be used. */
-
- /* First, find a free data watchpoint. */
- for (bp = 0; bp < 6; bp++) {
- /* Each data watchpoint's control registers occupy 2 bits
- (hence the 3), starting at bit 2 for D0 (hence the 2)
- with 4 bits between for each watchpoint (yes, the 4). */
- if (!(sreg.s0_3 & (0x3 << (2 + (bp * 4))))) {
- break;
- }
- }
-
- if (bp > 5) {
- /* We're out of watchpoints. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
-
- /* Configure the control register first. */
- if (type == '3' || type == '4') {
- /* Trigger on read. */
- sreg.s0_3 |= (1 << (2 + bp * 4));
- }
- if (type == '2' || type == '4') {
- /* Trigger on write. */
- sreg.s0_3 |= (2 << (2 + bp * 4));
- }
-
- /* Ugly pointer arithmetics to configure the watched range. */
- bp_d_regs[bp * 2] = addr;
- bp_d_regs[bp * 2 + 1] = (addr + len - 1);
- }
-
- /* Set the S1 flag to enable watchpoints. */
- reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- gdb_cris_strcpy(output_buffer, "OK");
-}
-
-static void remove_watchpoint(char type, int addr, int len)
-{
- /* Breakpoint/watchpoint types:
- 0 = memory breakpoint for instructions
- (not supported; done via memory write instead)
- 1 = hardware breakpoint for instructions (supported)
- 2 = write watchpoint (supported)
- 3 = read watchpoint (supported)
- 4 = access watchpoint (supported) */
- if (type < '1' || type > '4') {
- output_buffer[0] = 0;
- return;
- }
-
- /* Read watchpoints are set as access watchpoints, because of GDB's
- inability to deal with pure read watchpoints. */
- if (type == '3')
- type = '4';
-
- if (type == '1') {
- /* Hardware breakpoint. */
- /* Bit 0 in BP_CTRL holds the configuration for I0. */
- if (!(sreg.s0_3 & 0x1)) {
- /* Not in use. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
- /* Deconfigure. */
- sreg.s1_3 = 0;
- sreg.s2_3 = 0;
- sreg.s0_3 &= ~1;
- } else {
- int bp;
- unsigned int *bp_d_regs = &sreg.s3_3;
- /* Try to find a watchpoint that is configured for the
- specified range, then check that read/write also matches. */
-
- /* Ugly pointer arithmetic, since I cannot rely on a
- single switch (addr) as there may be several watchpoints with
- the same start address for example. */
-
- for (bp = 0; bp < 6; bp++) {
- if (bp_d_regs[bp * 2] == addr &&
- bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
- /* Matching range. */
- int bitpos = 2 + bp * 4;
- int rw_bits;
-
- /* Read/write bits for this BP. */
- rw_bits = (sreg.s0_3 & (0x3 << bitpos)) >> bitpos;
-
- if ((type == '3' && rw_bits == 0x1) ||
- (type == '2' && rw_bits == 0x2) ||
- (type == '4' && rw_bits == 0x3)) {
- /* Read/write matched. */
- break;
- }
- }
- }
-
- if (bp > 5) {
- /* No watchpoint matched. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- return;
- }
-
- /* Found a matching watchpoint. Now, deconfigure it by
- both disabling read/write in bp_ctrl and zeroing its
- start/end addresses. */
- sreg.s0_3 &= ~(3 << (2 + (bp * 4)));
- bp_d_regs[bp * 2] = 0;
- bp_d_regs[bp * 2 + 1] = 0;
- }
-
- /* Note that we don't clear the S1 flag here. It's done when continuing. */
- gdb_cris_strcpy(output_buffer, "OK");
-}
-
-
-
-/* All expected commands are sent from remote.c. Send a response according
- to the description in remote.c. */
-void
-handle_exception(int sigval)
-{
- /* Avoid warning of not used. */
-
- USEDFUN(handle_exception);
- USEDVAR(internal_stack[0]);
-
- register_fixup(sigval);
-
- /* Send response. */
- stub_is_stopped(sigval);
-
- for (;;) {
- output_buffer[0] = '\0';
- getpacket(input_buffer);
- switch (input_buffer[0]) {
- case 'g':
- /* Read registers: g
- Success: Each byte of register data is described by two hex digits.
- Registers are in the internal order for GDB, and the bytes
- in a register are in the same order the machine uses.
- Failure: void. */
- {
- char *buf;
- /* General and special registers. */
- buf = mem2hex(output_buffer, (char *)&reg, sizeof(registers));
- /* Support registers. */
- /* -1 because of the null termination that mem2hex adds. */
- mem2hex(buf,
- (char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
- 16 * sizeof(unsigned int));
- break;
- }
- case 'G':
- /* Write registers. GXX..XX
- Each byte of register data is described by two hex digits.
- Success: OK
- Failure: E08. */
- /* General and special registers. */
- if (hex2bin((char *)&reg, &input_buffer[1], sizeof(registers)))
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- /* Support registers. */
- else if (hex2bin((char *)&sreg + (reg.srs * 16 * sizeof(unsigned int)),
- &input_buffer[1] + sizeof(registers),
- 16 * sizeof(unsigned int)))
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- else
- gdb_cris_strcpy(output_buffer, "OK");
- break;
-
- case 'P':
- /* Write register. Pn...=r...
- Write register n..., hex value without 0x, with value r...,
- which contains a hex value without 0x and two hex digits
- for each byte in the register (target byte order). P1f=11223344 means
- set register 31 to 44332211.
- Success: OK
- Failure: E02, E05 */
- {
- char *suffix;
- int regno = gdb_cris_strtol(&input_buffer[1], &suffix, 16);
- int status;
-
- status = write_register(regno, suffix+1);
-
- switch (status) {
- case E02:
- /* Do not support read-only registers. */
- gdb_cris_strcpy(output_buffer, error_message[E02]);
- break;
- case E05:
- /* Do not support non-existing registers. */
- gdb_cris_strcpy(output_buffer, error_message[E05]);
- break;
- case E08:
- /* Invalid parameter. */
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- break;
- default:
- /* Valid register number. */
- gdb_cris_strcpy(output_buffer, "OK");
- break;
- }
- }
- break;
-
- case 'm':
- /* Read from memory. mAA..AA,LLLL
- AA..AA is the address and LLLL is the length.
- Success: XX..XX is the memory content. Can be fewer bytes than
- requested if only part of the data may be read. m6000120a,6c means
- retrieve 108 byte from base address 6000120a.
- Failure: void. */
- {
- char *suffix;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
- &suffix, 16);
- int len = gdb_cris_strtol(suffix+1, 0, 16);
-
- /* Bogus read (i.e. outside the kernel's
- segment)? . */
- if (!((unsigned int)addr >= 0xc0000000 &&
- (unsigned int)addr < 0xd0000000))
- addr = NULL;
-
- mem2hex(output_buffer, addr, len);
- }
- break;
-
- case 'X':
- /* Write to memory. XAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the binary data.
- Success: OK
- Failure: void. */
- case 'M':
- /* Write to memory. MAA..AA,LLLL:XX..XX
- AA..AA is the start address, LLLL is the number of bytes, and
- XX..XX is the hexadecimal data.
- Success: OK
- Failure: E08. */
- {
- char *lenptr;
- char *dataptr;
- unsigned char *addr = (unsigned char *)gdb_cris_strtol(&input_buffer[1],
- &lenptr, 16);
- int len = gdb_cris_strtol(lenptr+1, &dataptr, 16);
- if (*lenptr == ',' && *dataptr == ':') {
- if (input_buffer[0] == 'M') {
- if (hex2bin(addr, dataptr + 1, len))
- gdb_cris_strcpy(output_buffer, error_message[E08]);
- else
- gdb_cris_strcpy(output_buffer, "OK");
- } else /* X */ {
- bin2mem(addr, dataptr + 1, len);
- gdb_cris_strcpy(output_buffer, "OK");
- }
- } else {
- gdb_cris_strcpy(output_buffer, error_message[E06]);
- }
- }
- break;
-
- case 'c':
- /* Continue execution. cAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address.
- Success: return to the executing thread.
- Failure: will never know. */
-
- if (input_buffer[1] != '\0') {
- /* FIXME: Doesn't handle address argument. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- break;
- }
-
- /* Before continuing, make sure everything is set up correctly. */
-
- /* Set the SPC to some unlikely value. */
- reg.spc = 0;
- /* Set the S1 flag to 0 unless some watchpoint is enabled (since setting
- S1 to 0 would also disable watchpoints). (Note that bits 26-31 in BP_CTRL
- are reserved, so don't check against those). */
- if ((sreg.s0_3 & 0x3fff) == 0) {
- reg.ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
- }
-
- return;
-
- case 's':
- /* Step. sAA..AA
- AA..AA is the address where execution is resumed. If AA..AA is
- omitted, resume at the present address. Success: return to the
- executing thread. Failure: will never know. */
-
- if (input_buffer[1] != '\0') {
- /* FIXME: Doesn't handle address argument. */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- break;
- }
-
- /* Set the SPC to PC, which is where we'll return
- (deduced previously). */
- reg.spc = reg.pc;
-
- /* Set the S1 (first stacked, not current) flag, which will
- kick into action when we rfe. */
- reg.ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- return;
-
- case 'Z':
-
- /* Insert breakpoint or watchpoint, Ztype,addr,length.
- Remote protocol says: A remote target shall return an empty string
- for an unrecognized breakpoint or watchpoint packet type. */
- {
- char *lenptr;
- char *dataptr;
- int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
- int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
- char type = input_buffer[1];
-
- insert_watchpoint(type, addr, len);
- break;
- }
-
- case 'z':
- /* Remove breakpoint or watchpoint, Ztype,addr,length.
- Remote protocol says: A remote target shall return an empty string
- for an unrecognized breakpoint or watchpoint packet type. */
- {
- char *lenptr;
- char *dataptr;
- int addr = gdb_cris_strtol(&input_buffer[3], &lenptr, 16);
- int len = gdb_cris_strtol(lenptr + 1, &dataptr, 16);
- char type = input_buffer[1];
-
- remove_watchpoint(type, addr, len);
- break;
- }
-
-
- case '?':
- /* The last signal which caused a stop. ?
- Success: SAA, where AA is the signal number.
- Failure: void. */
- output_buffer[0] = 'S';
- output_buffer[1] = hex_asc_hi(sigval);
- output_buffer[2] = hex_asc_lo(sigval);
- output_buffer[3] = 0;
- break;
-
- case 'D':
- /* Detach from host. D
- Success: OK, and return to the executing thread.
- Failure: will never know */
- putpacket("OK");
- return;
-
- case 'k':
- case 'r':
- /* kill request or reset request.
- Success: restart of target.
- Failure: will never know. */
- kill_restart();
- break;
-
- case 'C':
- case 'S':
- case '!':
- case 'R':
- case 'd':
- /* Continue with signal sig. Csig;AA..AA
- Step with signal sig. Ssig;AA..AA
- Use the extended remote protocol. !
- Restart the target system. R0
- Toggle debug flag. d
- Search backwards. tAA:PP,MM
- Not supported: E04 */
-
- /* FIXME: What's the difference between not supported
- and ignored (below)? */
- gdb_cris_strcpy(output_buffer, error_message[E04]);
- break;
-
- default:
- /* The stub should ignore other request and send an empty
- response ($#<checksum>). This way we can extend the protocol and GDB
- can tell whether the stub it is talking to uses the old or the new. */
- output_buffer[0] = 0;
- break;
- }
- putpacket(output_buffer);
- }
-}
-
-void
-kgdb_init(void)
-{
- reg_intr_vect_rw_mask intr_mask;
- reg_ser_rw_intr_mask ser_intr_mask;
-
- /* Configure the kgdb serial port. */
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER0_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser0 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER1_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser1 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER2_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser2 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- /* Note: no shortcut registered (not handled by multiple_interrupt).
- See entry.S. */
- set_exception_vector(SER3_INTR_VECT, kgdb_handle_exception);
- /* Enable the ser irq in the global config. */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.ser3 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
- ser_intr_mask.dav = regk_ser_yes;
- REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
-#endif
-
-}
-/* Performs a complete re-start from scratch. */
-static void
-kill_restart(void)
-{
- machine_restart("");
-}
-
-/* Use this static breakpoint in the start-up only. */
-
-void
-breakpoint(void)
-{
- kgdb_started = 1;
- dynamic_bp = 0; /* This is a static, not a dynamic breakpoint. */
- __asm__ volatile ("break 8"); /* Jump to kgdb_handle_breakpoint. */
-}
-
-/****************************** End of file **********************************/
diff --git a/arch/cris/arch-v32/kernel/kgdb_asm.S b/arch/cris/arch-v32/kernel/kgdb_asm.S
deleted file mode 100644
index c26ea6b0e334..000000000000
--- a/arch/cris/arch-v32/kernel/kgdb_asm.S
+++ /dev/null
@@ -1,552 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2004 Axis Communications AB
- *
- * Code for handling break 8, hardware breakpoint, single step, and serial
- * port exceptions for kernel debugging purposes.
- */
-
-#include <hwregs/intr_vect.h>
-
- ;; Exported functions.
- .globl kgdb_handle_exception
-
-kgdb_handle_exception:
-
-;; Create a register image of the caller.
-;;
-;; First of all, save the ACR on the stack since we need it for address calculations.
-;; We put it into the register struct later.
-
- subq 4, $sp
- move.d $acr, [$sp]
-
-;; Now we are free to use ACR all we want.
-;; If we were running this handler with interrupts on, we would have to be careful
-;; to save and restore CCS manually, but since we aren't we treat it like every other
-;; register.
-
- move.d reg, $acr
- move.d $r0, [$acr] ; Save R0 (start of register struct)
- addq 4, $acr
- move.d $r1, [$acr] ; Save R1
- addq 4, $acr
- move.d $r2, [$acr] ; Save R2
- addq 4, $acr
- move.d $r3, [$acr] ; Save R3
- addq 4, $acr
- move.d $r4, [$acr] ; Save R4
- addq 4, $acr
- move.d $r5, [$acr] ; Save R5
- addq 4, $acr
- move.d $r6, [$acr] ; Save R6
- addq 4, $acr
- move.d $r7, [$acr] ; Save R7
- addq 4, $acr
- move.d $r8, [$acr] ; Save R8
- addq 4, $acr
- move.d $r9, [$acr] ; Save R9
- addq 4, $acr
- move.d $r10, [$acr] ; Save R10
- addq 4, $acr
- move.d $r11, [$acr] ; Save R11
- addq 4, $acr
- move.d $r12, [$acr] ; Save R12
- addq 4, $acr
- move.d $r13, [$acr] ; Save R13
- addq 4, $acr
- move.d $sp, [$acr] ; Save SP (R14)
- addq 4, $acr
-
- ;; The ACR register is already saved on the stack, so pop it from there.
- move.d [$sp],$r0
- move.d $r0, [$acr]
- addq 4, $acr
-
- move $bz, [$acr]
- addq 1, $acr
- move $vr, [$acr]
- addq 1, $acr
- move $pid, [$acr]
- addq 4, $acr
- move $srs, [$acr]
- addq 1, $acr
- move $wz, [$acr]
- addq 2, $acr
- move $exs, [$acr]
- addq 4, $acr
- move $eda, [$acr]
- addq 4, $acr
- move $mof, [$acr]
- addq 4, $acr
- move $dz, [$acr]
- addq 4, $acr
- move $ebp, [$acr]
- addq 4, $acr
- move $erp, [$acr]
- addq 4, $acr
- move $srp, [$acr]
- addq 4, $acr
- move $nrp, [$acr]
- addq 4, $acr
- move $ccs, [$acr]
- addq 4, $acr
- move $usp, [$acr]
- addq 4, $acr
- move $spc, [$acr]
- addq 4, $acr
-
-;; Skip the pseudo-PC.
- addq 4, $acr
-
-;; Save the support registers in bank 0 - 3.
- clear.d $r1 ; Bank counter
- move.d sreg, $acr
-
-;; Bank 0
- move $r1, $srs
- nop
- nop
- nop
- move $s0, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s1, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s2, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s3, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s4, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s5, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s6, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s7, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s8, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s9, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s10, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s11, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s12, $r0
- move.d $r0, [$acr]
- addq 4, $acr
-
- ;; Nothing in S13 - S15, bank 0
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
-
-;; Bank 1 and bank 2 have the same layout, hence the loop.
- addq 1, $r1
-1:
- move $r1, $srs
- nop
- nop
- nop
- move $s0, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s1, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s2, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s3, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s4, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s5, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s6, $r0
- move.d $r0, [$acr]
- addq 4, $acr
-
- ;; Nothing in S7 - S15, bank 1 and 2
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
- clear.d [$acr]
- addq 4, $acr
-
- addq 1, $r1
- cmpq 3, $r1
- bne 1b
- nop
-
-;; Bank 3
- move $r1, $srs
- nop
- nop
- nop
- move $s0, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s1, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s2, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s3, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s4, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s5, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s6, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s7, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s8, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s9, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s10, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s11, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s12, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s13, $r0
- move.d $r0, [$acr]
- addq 4, $acr
- move $s14, $r0
- move.d $r0, [$acr]
- addq 4, $acr
-;; Nothing in S15, bank 3
- clear.d [$acr]
- addq 4, $acr
-
-;; Check what got us here: get IDX field of EXS.
- move $exs, $r10
- and.d 0xff00, $r10
- lsrq 8, $r10
-#if defined(CONFIG_ETRAX_KGDB_PORT0)
- cmp.d SER0_INTR_VECT, $r10 ; IRQ for serial port 0
- beq sigint
- nop
-#elif defined(CONFIG_ETRAX_KGDB_PORT1)
- cmp.d SER1_INTR_VECT, $r10 ; IRQ for serial port 1
- beq sigint
- nop
-#elif defined(CONFIG_ETRAX_KGDB_PORT2)
- cmp.d SER2_INTR_VECT, $r10 ; IRQ for serial port 2
- beq sigint
- nop
-#elif defined(CONFIG_ETRAX_KGDB_PORT3)
- cmp.d SER3_INTR_VECT, $r10 ; IRQ for serial port 3
- beq sigint
- nop
-#endif
-;; Multiple interrupt must be due to serial break.
- cmp.d 0x30, $r10 ; Multiple interrupt
- beq sigint
- nop
-;; Neither of those? Then it's a sigtrap.
- ba handle_comm
- moveq 5, $r10 ; Set SIGTRAP (delay slot)
-
-sigint:
- ;; Serial interrupt; get character
- jsr getDebugChar
- nop ; Delay slot
- cmp.b 3, $r10 ; \003 (Ctrl-C)?
- bne return ; No, get out of here
- nop
- moveq 2, $r10 ; Set SIGINT
-
-;;
-;; Handle the communication
-;;
-handle_comm:
- move.d internal_stack+1020, $sp ; Use the internal stack which grows upwards
- jsr handle_exception ; Interactive routine
- nop
-
-;;
-;; Return to the caller
-;;
-return:
-
-;; First of all, write the support registers.
- clear.d $r1 ; Bank counter
- move.d sreg, $acr
-
-;; Bank 0
- move $r1, $srs
- nop
- nop
- nop
- move.d [$acr], $r0
- move $r0, $s0
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s1
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s2
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s3
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s4
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s5
- addq 4, $acr
-
-;; Nothing in S6 - S7, bank 0.
- addq 4, $acr
- addq 4, $acr
-
- move.d [$acr], $r0
- move $r0, $s8
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s9
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s10
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s11
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s12
- addq 4, $acr
-
-;; Nothing in S13 - S15, bank 0
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
-
-;; Bank 1 and bank 2 have the same layout, hence the loop.
- addq 1, $r1
-2:
- move $r1, $srs
- nop
- nop
- nop
- move.d [$acr], $r0
- move $r0, $s0
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s1
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s2
- addq 4, $acr
-
-;; S3 (MM_CAUSE) is read-only.
- addq 4, $acr
-
- move.d [$acr], $r0
- move $r0, $s4
- addq 4, $acr
-
-;; FIXME: Actually write S5/S6? (Affects MM_CAUSE.)
- addq 4, $acr
- addq 4, $acr
-
-;; Nothing in S7 - S15, bank 1 and 2
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
- addq 4, $acr
-
- addq 1, $r1
- cmpq 3, $r1
- bne 2b
- nop
-
-;; Bank 3
- move $r1, $srs
- nop
- nop
- nop
- move.d [$acr], $r0
- move $r0, $s0
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s1
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s2
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s3
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s4
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s5
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s6
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s7
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s8
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s9
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s10
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s11
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s12
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s13
- addq 4, $acr
- move.d [$acr], $r0
- move $r0, $s14
- addq 4, $acr
-
-;; Nothing in S15, bank 3
- addq 4, $acr
-
-;; Now, move on to the regular register restoration process.
-
- move.d reg, $acr ; Reset ACR to point at the beginning of the register image
- move.d [$acr], $r0 ; Restore R0
- addq 4, $acr
- move.d [$acr], $r1 ; Restore R1
- addq 4, $acr
- move.d [$acr], $r2 ; Restore R2
- addq 4, $acr
- move.d [$acr], $r3 ; Restore R3
- addq 4, $acr
- move.d [$acr], $r4 ; Restore R4
- addq 4, $acr
- move.d [$acr], $r5 ; Restore R5
- addq 4, $acr
- move.d [$acr], $r6 ; Restore R6
- addq 4, $acr
- move.d [$acr], $r7 ; Restore R7
- addq 4, $acr
- move.d [$acr], $r8 ; Restore R8
- addq 4, $acr
- move.d [$acr], $r9 ; Restore R9
- addq 4, $acr
- move.d [$acr], $r10 ; Restore R10
- addq 4, $acr
- move.d [$acr], $r11 ; Restore R11
- addq 4, $acr
- move.d [$acr], $r12 ; Restore R12
- addq 4, $acr
- move.d [$acr], $r13 ; Restore R13
-
-;;
-;; We restore all registers, even though some of them probably haven't changed.
-;;
-
- addq 4, $acr
- move.d [$acr], $sp ; Restore SP (R14)
-
- ;; ACR cannot be restored just yet.
- addq 8, $acr
-
- ;; Skip BZ, VR.
- addq 2, $acr
-
- move [$acr], $pid ; Restore PID
- addq 4, $acr
- move [$acr], $srs ; Restore SRS
- nop
- nop
- nop
- addq 1, $acr
-
- ;; Skip WZ.
- addq 2, $acr
-
- move [$acr], $exs ; Restore EXS.
- addq 4, $acr
- move [$acr], $eda ; Restore EDA.
- addq 4, $acr
- move [$acr], $mof ; Restore MOF.
-
- ;; Skip DZ.
- addq 8, $acr
-
- move [$acr], $ebp ; Restore EBP.
- addq 4, $acr
- move [$acr], $erp ; Restore ERP.
- addq 4, $acr
- move [$acr], $srp ; Restore SRP.
- addq 4, $acr
- move [$acr], $nrp ; Restore NRP.
- addq 4, $acr
- move [$acr], $ccs ; Restore CCS like an ordinary register.
- addq 4, $acr
- move [$acr], $usp ; Restore USP
- addq 4, $acr
- move [$acr], $spc ; Restore SPC
- ; No restoration of pseudo-PC of course.
-
- move.d reg, $acr ; Reset ACR to point at the beginning of the register image
- add.d 15*4, $acr
- move.d [$acr], $acr ; Finally, restore ACR.
- rete ; Same as jump ERP
- rfe ; Shifts CCS
diff --git a/arch/cris/arch-v32/kernel/process.c b/arch/cris/arch-v32/kernel/process.c
deleted file mode 100644
index a02f276d0ed4..000000000000
--- a/arch/cris/arch-v32/kernel/process.c
+++ /dev/null
@@ -1,180 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2000-2003 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Mikael Starvik (starvik@axis.com)
- * Tobias Anderberg (tobiasa@axis.com), CRISv32 port.
- *
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/timer_defs.h>
-#include <hwregs/intr_vect_defs.h>
-#include <linux/ptrace.h>
-
-extern void stop_watchdog(void);
-
-/* We use this if we don't have any better idle routine. */
-void default_idle(void)
-{
- local_irq_enable();
- /* Halt until exception. */
- __asm__ volatile("halt");
-}
-
-/*
- * Free current thread data structures etc..
- */
-
-extern void deconfigure_bp(long pid);
-void exit_thread(struct task_struct *tsk)
-{
- deconfigure_bp(tsk->pid);
-}
-
-/*
- * If the watchdog is enabled, disable interrupts and enter an infinite loop.
- * The watchdog will reset the CPU after 0.1s. If the watchdog isn't enabled
- * then enable it and wait.
- */
-extern void arch_enable_nmi(void);
-
-void
-hard_reset_now(void)
-{
- /*
- * Don't declare this variable elsewhere. We don't want any other
- * code to know about it than the watchdog handler in entry.S and
- * this code, implementing hard reset through the watchdog.
- */
-#if defined(CONFIG_ETRAX_WATCHDOG)
- extern int cause_of_death;
-#endif
-
- printk("*** HARD RESET ***\n");
- local_irq_disable();
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
- cause_of_death = 0xbedead;
-#else
-{
- reg_timer_rw_wd_ctrl wd_ctrl = {0};
-
- stop_watchdog();
-
- wd_ctrl.key = 16; /* Arbitrary key. */
- wd_ctrl.cnt = 1; /* Minimum time. */
- wd_ctrl.cmd = regk_timer_start;
-
- arch_enable_nmi();
- REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
-}
-#endif
-
- while (1)
- ; /* Wait for reset. */
-}
-
-/*
- * Setup the child's kernel stack with a pt_regs and call switch_stack() on it.
- * It will be unnested during _resume and _ret_from_sys_call when the new thread
- * is scheduled.
- *
- * Also setup the thread switching structure which is used to keep
- * thread-specific data during _resumes.
- */
-
-extern asmlinkage void ret_from_fork(void);
-extern asmlinkage void ret_from_kernel_thread(void);
-
-int
-copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long arg, struct task_struct *p)
-{
- struct pt_regs *childregs = task_pt_regs(p);
- struct switch_stack *swstack = ((struct switch_stack *) childregs) - 1;
-
- /*
- * Put the pt_regs structure at the end of the new kernel stack page and
- * fix it up. Note: the task_struct doubles as the kernel stack for the
- * task.
- */
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(swstack, 0,
- sizeof(struct switch_stack) + sizeof(struct pt_regs));
- swstack->r1 = usp;
- swstack->r2 = arg;
- childregs->ccs = 1 << (I_CCS_BITNR + CCS_SHIFT);
- swstack->return_ip = (unsigned long) ret_from_kernel_thread;
- p->thread.ksp = (unsigned long) swstack;
- p->thread.usp = 0;
- return 0;
- }
- *childregs = *current_pt_regs(); /* Struct copy of pt_regs. */
- childregs->r10 = 0; /* Child returns 0 after a fork/clone. */
-
- /* Set a new TLS ?
- * The TLS is in $mof because it is the 5th argument to sys_clone.
- */
- if (p->mm && (clone_flags & CLONE_SETTLS)) {
- task_thread_info(p)->tls = childregs->mof;
- }
-
- /* Put the switch stack right below the pt_regs. */
-
- /* Parameter to ret_from_sys_call. 0 is don't restart the syscall. */
- swstack->r9 = 0;
-
- /*
- * We want to return into ret_from_sys_call after the _resume.
- * ret_from_fork will call ret_from_sys_call.
- */
- swstack->return_ip = (unsigned long) ret_from_fork;
-
- /* Fix the user-mode and kernel-mode stackpointer. */
- p->thread.usp = usp ?: rdusp();
- p->thread.ksp = (unsigned long) swstack;
-
- return 0;
-}
-
-unsigned long
-get_wchan(struct task_struct *p)
-{
- /* TODO */
- return 0;
-}
-#undef last_sched
-#undef first_sched
-
-void show_regs(struct pt_regs * regs)
-{
- unsigned long usp = rdusp();
-
- show_regs_print_info(KERN_DEFAULT);
-
- printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
- regs->erp, regs->srp, regs->ccs, usp, regs->mof);
-
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
-
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
-
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
-
- printk("r12: %08lx r13: %08lx oR10: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10);
-}
diff --git a/arch/cris/arch-v32/kernel/ptrace.c b/arch/cris/arch-v32/kernel/ptrace.c
deleted file mode 100644
index ccac1aaadc8a..000000000000
--- a/arch/cris/arch-v32/kernel/ptrace.c
+++ /dev/null
@@ -1,492 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2000-2007, Axis Communications AB.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/signal.h>
-#include <linux/security.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <arch/hwregs/supp_reg.h>
-
-/*
- * Determines which bits in CCS the user has access to.
- * 1 = access, 0 = no access.
- */
-#define CCS_MASK 0x00087c00 /* SXNZVC */
-
-#define SBIT_USER (1 << (S_CCS_BITNR + CCS_SHIFT))
-
-static int put_debugreg(long pid, unsigned int regno, long data);
-static long get_debugreg(long pid, unsigned int regno);
-static unsigned long get_pseudo_pc(struct task_struct *child);
-void deconfigure_bp(long pid);
-
-extern unsigned long cris_signal_return_page;
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-long get_reg(struct task_struct *task, unsigned int regno)
-{
- /* USP is a special case, it's not in the pt_regs struct but
- * in the tasks thread struct
- */
- unsigned long ret;
-
- if (regno <= PT_EDA)
- ret = ((unsigned long *)task_pt_regs(task))[regno];
- else if (regno == PT_USP)
- ret = task->thread.usp;
- else if (regno == PT_PPC)
- ret = get_pseudo_pc(task);
- else if (regno <= PT_MAX)
- ret = get_debugreg(task->pid, regno);
- else
- ret = 0;
-
- return ret;
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-int put_reg(struct task_struct *task, unsigned int regno, unsigned long data)
-{
- if (regno <= PT_EDA)
- ((unsigned long *)task_pt_regs(task))[regno] = data;
- else if (regno == PT_USP)
- task->thread.usp = data;
- else if (regno == PT_PPC) {
- /* Write pseudo-PC to ERP only if changed. */
- if (data != get_pseudo_pc(task))
- task_pt_regs(task)->erp = data;
- } else if (regno <= PT_MAX)
- return put_debugreg(task->pid, regno, data);
- else
- return -1;
- return 0;
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- unsigned long tmp;
-
- /*
- * Set up SPC if not set already (in which case we have no other
- * choice but to trust it).
- */
- if (!get_reg(child, PT_SPC)) {
- /* In case we're stopped in a delay slot. */
- tmp = get_reg(child, PT_ERP) & ~1;
- put_reg(child, PT_SPC, tmp);
- }
- tmp = get_reg(child, PT_CCS) | SBIT_USER;
- put_reg(child, PT_CCS, tmp);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- put_reg(child, PT_SPC, 0);
-
- if (!get_debugreg(child->pid, PT_BP_CTRL)) {
- unsigned long tmp;
- /* If no h/w bp configured, disable S bit. */
- tmp = get_reg(child, PT_CCS) & ~SBIT_USER;
- put_reg(child, PT_CCS, tmp);
- }
-}
-
-/*
- * Called by kernel/ptrace.c when detaching.
- *
- * Make sure the single step bit is not set.
- */
-void
-ptrace_disable(struct task_struct *child)
-{
- /* Deconfigure SPC and S-bit. */
- user_disable_single_step(child);
- put_reg(child, PT_SPC, 0);
-
- /* Deconfigure any watchpoints associated with the child. */
- deconfigure_bp(child->pid);
-}
-
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned int regno = addr >> 2;
- unsigned long __user *datap = (unsigned long __user *)data;
-
- switch (request) {
- /* Read word at location address. */
- case PTRACE_PEEKTEXT:
- case PTRACE_PEEKDATA: {
- unsigned long tmp;
- int copied;
-
- ret = -EIO;
-
- /* The signal trampoline page is outside the normal user-addressable
- * space but still accessible. This is hack to make it possible to
- * access the signal handler code in GDB.
- */
- if ((addr & PAGE_MASK) == cris_signal_return_page) {
- /* The trampoline page is globally mapped, no page table to traverse.*/
- tmp = *(unsigned long*)addr;
- } else {
- copied = ptrace_access_vm(child, addr, &tmp, sizeof(tmp), FOLL_FORCE);
-
- if (copied != sizeof(tmp))
- break;
- }
-
- ret = put_user(tmp,datap);
- break;
- }
-
- /* Read the word at location address in the USER area. */
- case PTRACE_PEEKUSR: {
- unsigned long tmp;
-
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- tmp = get_reg(child, regno);
- ret = put_user(tmp, datap);
- break;
- }
-
- /* Write the word at location address. */
- case PTRACE_POKETEXT:
- case PTRACE_POKEDATA:
- ret = generic_ptrace_pokedata(child, addr, data);
- break;
-
- /* Write the word at location address in the USER area. */
- case PTRACE_POKEUSR:
- ret = -EIO;
- if ((addr & 3) || regno > PT_MAX)
- break;
-
- if (regno == PT_CCS) {
- /* don't allow the tracing process to change stuff like
- * interrupt enable, kernel/user bit, dma enables etc.
- */
- data &= CCS_MASK;
- data |= get_reg(child, PT_CCS) & ~CCS_MASK;
- }
- if (put_reg(child, regno, data))
- break;
- ret = 0;
- break;
-
- /* Get all GP registers from the child. */
- case PTRACE_GETREGS: {
- int i;
- unsigned long tmp;
-
- for (i = 0; i <= PT_MAX; i++) {
- tmp = get_reg(child, i);
-
- if (put_user(tmp, datap)) {
- ret = -EFAULT;
- goto out_tsk;
- }
-
- datap++;
- }
-
- ret = 0;
- break;
- }
-
- /* Set all GP registers in the child. */
- case PTRACE_SETREGS: {
- int i;
- unsigned long tmp;
-
- for (i = 0; i <= PT_MAX; i++) {
- if (get_user(tmp, datap)) {
- ret = -EFAULT;
- goto out_tsk;
- }
-
- if (i == PT_CCS) {
- tmp &= CCS_MASK;
- tmp |= get_reg(child, PT_CCS) & ~CCS_MASK;
- }
-
- put_reg(child, i, tmp);
- datap++;
- }
-
- ret = 0;
- break;
- }
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
-out_tsk:
- return ret;
-}
-
-void do_syscall_trace(void)
-{
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return;
-
- if (!(current->ptrace & PT_PTRACED))
- return;
-
- /* the 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
-
- /*
- * This isn't the same as continuing with a signal, but it will do for
- * normal use.
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
-}
-
-/* Returns the size of an instruction that has a delay slot. */
-
-static int insn_size(struct task_struct *child, unsigned long pc)
-{
- unsigned long opcode;
- int copied;
- int opsize = 0;
-
- /* Read the opcode at pc (do what PTRACE_PEEKTEXT would do). */
- copied = access_process_vm(child, pc, &opcode, sizeof(opcode), FOLL_FORCE);
- if (copied != sizeof(opcode))
- return 0;
-
- switch ((opcode & 0x0f00) >> 8) {
- case 0x0:
- case 0x9:
- case 0xb:
- opsize = 2;
- break;
- case 0xe:
- case 0xf:
- opsize = 6;
- break;
- case 0xd:
- /* Could be 4 or 6; check more bits. */
- if ((opcode & 0xff) == 0xff)
- opsize = 4;
- else
- opsize = 6;
- break;
- default:
- panic("ERROR: Couldn't find size of opcode 0x%lx at 0x%lx\n",
- opcode, pc);
- }
-
- return opsize;
-}
-
-static unsigned long get_pseudo_pc(struct task_struct *child)
-{
- /* Default value for PC is ERP. */
- unsigned long pc = get_reg(child, PT_ERP);
-
- if (pc & 0x1) {
- unsigned long spc = get_reg(child, PT_SPC);
- /* Delay slot bit set. Report as stopped on proper
- instruction. */
- if (spc) {
- /* Rely on SPC if set. FIXME: We might want to check
- that EXS indicates we stopped due to a single-step
- exception. */
- pc = spc;
- } else {
- /* Calculate the PC from the size of the instruction
- that the delay slot we're in belongs to. */
- pc += insn_size(child, pc & ~1) - 1;
- }
- }
- return pc;
-}
-
-static long bp_owner = 0;
-
-/* Reachable from exit_thread in signal.c, so not static. */
-void deconfigure_bp(long pid)
-{
- int bp;
-
- /* Only deconfigure if the pid is the owner. */
- if (bp_owner != pid)
- return;
-
- for (bp = 0; bp < 6; bp++) {
- unsigned long tmp;
- /* Deconfigure start and end address (also gets rid of ownership). */
- put_debugreg(pid, PT_BP + 3 + (bp * 2), 0);
- put_debugreg(pid, PT_BP + 4 + (bp * 2), 0);
-
- /* Deconfigure relevant bits in control register. */
- tmp = get_debugreg(pid, PT_BP_CTRL) & ~(3 << (2 + (bp * 4)));
- put_debugreg(pid, PT_BP_CTRL, tmp);
- }
- /* No owner now. */
- bp_owner = 0;
-}
-
-static int put_debugreg(long pid, unsigned int regno, long data)
-{
- int ret = 0;
- register int old_srs;
-
-#ifdef CONFIG_ETRAX_KGDB
- /* Ignore write, but pretend it was ok if value is 0
- (we don't want POKEUSR/SETREGS failing unnessecarily). */
- return (data == 0) ? ret : -1;
-#endif
-
- /* Simple owner management. */
- if (!bp_owner)
- bp_owner = pid;
- else if (bp_owner != pid) {
- /* Ignore write, but pretend it was ok if value is 0
- (we don't want POKEUSR/SETREGS failing unnessecarily). */
- return (data == 0) ? ret : -1;
- }
-
- /* Remember old SRS. */
- SPEC_REG_RD(SPEC_REG_SRS, old_srs);
- /* Switch to BP bank. */
- SUPP_BANK_SEL(BANK_BP);
-
- switch (regno - PT_BP) {
- case 0:
- SUPP_REG_WR(0, data); break;
- case 1:
- case 2:
- if (data)
- ret = -1;
- break;
- case 3:
- SUPP_REG_WR(3, data); break;
- case 4:
- SUPP_REG_WR(4, data); break;
- case 5:
- SUPP_REG_WR(5, data); break;
- case 6:
- SUPP_REG_WR(6, data); break;
- case 7:
- SUPP_REG_WR(7, data); break;
- case 8:
- SUPP_REG_WR(8, data); break;
- case 9:
- SUPP_REG_WR(9, data); break;
- case 10:
- SUPP_REG_WR(10, data); break;
- case 11:
- SUPP_REG_WR(11, data); break;
- case 12:
- SUPP_REG_WR(12, data); break;
- case 13:
- SUPP_REG_WR(13, data); break;
- case 14:
- SUPP_REG_WR(14, data); break;
- default:
- ret = -1;
- break;
- }
-
- /* Restore SRS. */
- SPEC_REG_WR(SPEC_REG_SRS, old_srs);
- /* Just for show. */
- NOP();
- NOP();
- NOP();
-
- return ret;
-}
-
-static long get_debugreg(long pid, unsigned int regno)
-{
- register int old_srs;
- register long data;
-
- if (pid != bp_owner) {
- return 0;
- }
-
- /* Remember old SRS. */
- SPEC_REG_RD(SPEC_REG_SRS, old_srs);
- /* Switch to BP bank. */
- SUPP_BANK_SEL(BANK_BP);
-
- switch (regno - PT_BP) {
- case 0:
- SUPP_REG_RD(0, data); break;
- case 1:
- case 2:
- /* error return value? */
- data = 0;
- break;
- case 3:
- SUPP_REG_RD(3, data); break;
- case 4:
- SUPP_REG_RD(4, data); break;
- case 5:
- SUPP_REG_RD(5, data); break;
- case 6:
- SUPP_REG_RD(6, data); break;
- case 7:
- SUPP_REG_RD(7, data); break;
- case 8:
- SUPP_REG_RD(8, data); break;
- case 9:
- SUPP_REG_RD(9, data); break;
- case 10:
- SUPP_REG_RD(10, data); break;
- case 11:
- SUPP_REG_RD(11, data); break;
- case 12:
- SUPP_REG_RD(12, data); break;
- case 13:
- SUPP_REG_RD(13, data); break;
- case 14:
- SUPP_REG_RD(14, data); break;
- default:
- /* error return value? */
- data = 0;
- }
-
- /* Restore SRS. */
- SPEC_REG_WR(SPEC_REG_SRS, old_srs);
- /* Just for show. */
- NOP();
- NOP();
- NOP();
-
- return data;
-}
diff --git a/arch/cris/arch-v32/kernel/setup.c b/arch/cris/arch-v32/kernel/setup.c
deleted file mode 100644
index a36372e35e96..000000000000
--- a/arch/cris/arch-v32/kernel/setup.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Display CPU info in /proc/cpuinfo.
- *
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <linux/seq_file.h>
-#include <linux/proc_fs.h>
-#include <linux/delay.h>
-#include <linux/param.h>
-
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-
-#ifdef CONFIG_PROC_FS
-
-#define HAS_FPU 0x0001
-#define HAS_MMU 0x0002
-#define HAS_ETHERNET100 0x0004
-#define HAS_TOKENRING 0x0008
-#define HAS_SCSI 0x0010
-#define HAS_ATA 0x0020
-#define HAS_USB 0x0040
-#define HAS_IRQ_BUG 0x0080
-#define HAS_MMU_BUG 0x0100
-
-struct cpu_info {
- char *cpu_model;
- unsigned short rev;
- unsigned short cache_size;
- unsigned short flags;
-};
-
-/* Some of these model are here for historical reasons only. */
-static struct cpu_info cpinfo[] = {
- {"ETRAX 1", 0, 0, 0},
- {"ETRAX 2", 1, 0, 0},
- {"ETRAX 3", 2, 0, 0},
- {"ETRAX 4", 3, 0, 0},
- {"Simulator", 7, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA},
- {"ETRAX 100", 8, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_IRQ_BUG},
- {"ETRAX 100", 9, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA},
-
- {"ETRAX 100LX", 10, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB
- | HAS_MMU | HAS_MMU_BUG},
-
- {"ETRAX 100LX v2", 11, 8, HAS_ETHERNET100 | HAS_SCSI | HAS_ATA | HAS_USB
- | HAS_MMU},
-#ifdef CONFIG_ETRAXFS
- {"ETRAX FS", 32, 32, HAS_ETHERNET100 | HAS_ATA | HAS_MMU},
-#else
- {"ARTPEC-3", 32, 32, HAS_ETHERNET100 | HAS_MMU},
-#endif
- {"Unknown", 0, 0, 0}
-};
-
-int show_cpuinfo(struct seq_file *m, void *v)
-{
- int i;
- int cpu = (int)v - 1;
- unsigned long revision;
- struct cpu_info *info;
-
- info = &cpinfo[ARRAY_SIZE(cpinfo) - 1];
-
- revision = rdvr();
-
- for (i = 0; i < ARRAY_SIZE(cpinfo); i++) {
- if (cpinfo[i].rev == revision) {
- info = &cpinfo[i];
- break;
- }
- }
-
- seq_printf(m,
- "processor\t: %d\n"
- "cpu\t\t: CRIS\n"
- "cpu revision\t: %lu\n"
- "cpu model\t: %s\n"
- "cache size\t: %d KB\n"
- "fpu\t\t: %s\n"
- "mmu\t\t: %s\n"
- "mmu DMA bug\t: %s\n"
- "ethernet\t: %s Mbps\n"
- "token ring\t: %s\n"
- "scsi\t\t: %s\n"
- "ata\t\t: %s\n"
- "usb\t\t: %s\n"
- "bogomips\t: %lu.%02lu\n\n",
-
- cpu,
- revision,
- info->cpu_model,
- info->cache_size,
- info->flags & HAS_FPU ? "yes" : "no",
- info->flags & HAS_MMU ? "yes" : "no",
- info->flags & HAS_MMU_BUG ? "yes" : "no",
- info->flags & HAS_ETHERNET100 ? "10/100" : "10",
- info->flags & HAS_TOKENRING ? "4/16 Mbps" : "no",
- info->flags & HAS_SCSI ? "yes" : "no",
- info->flags & HAS_ATA ? "yes" : "no",
- info->flags & HAS_USB ? "yes" : "no",
- (loops_per_jiffy * HZ + 500) / 500000,
- ((loops_per_jiffy * HZ + 500) / 5000) % 100);
-
- return 0;
-}
-
-#endif /* CONFIG_PROC_FS */
-
-void show_etrax_copyright(void)
-{
-#ifdef CONFIG_ETRAXFS
- printk(KERN_INFO "Linux/CRISv32 port on ETRAX FS "
- "(C) 2003, 2004 Axis Communications AB\n");
-#else
- printk(KERN_INFO "Linux/CRISv32 port on ARTPEC-3 "
- "(C) 2003-2009 Axis Communications AB\n");
-#endif
-}
-
-static struct i2c_board_info __initdata i2c_info[] = {
- {I2C_BOARD_INFO("camblock", 0x43)},
- {I2C_BOARD_INFO("tmp100", 0x48)},
- {I2C_BOARD_INFO("tmp100", 0x4A)},
- {I2C_BOARD_INFO("tmp100", 0x4C)},
- {I2C_BOARD_INFO("tmp100", 0x4D)},
- {I2C_BOARD_INFO("tmp100", 0x4E)},
-#ifdef CONFIG_RTC_DRV_PCF8563
- {I2C_BOARD_INFO("pcf8563", 0x51)},
-#endif
- {I2C_BOARD_INFO("pca9536", 0x41)},
- {I2C_BOARD_INFO("fnp300", 0x40)},
- {I2C_BOARD_INFO("fnp300", 0x42)},
- {I2C_BOARD_INFO("adc101", 0x54)},
-};
-
-static struct i2c_board_info __initdata i2c_info2[] = {
- {I2C_BOARD_INFO("camblock", 0x43)},
- {I2C_BOARD_INFO("tmp100", 0x48)},
- {I2C_BOARD_INFO("tmp100", 0x4A)},
- {I2C_BOARD_INFO("tmp100", 0x4C)},
- {I2C_BOARD_INFO("tmp100", 0x4D)},
- {I2C_BOARD_INFO("tmp100", 0x4E)},
- {I2C_BOARD_INFO("pca9536", 0x41)},
- {I2C_BOARD_INFO("fnp300", 0x40)},
- {I2C_BOARD_INFO("fnp300", 0x42)},
- {I2C_BOARD_INFO("adc101", 0x54)},
-};
-
-static struct i2c_board_info __initdata i2c_info3[] = {
- {I2C_BOARD_INFO("adc101", 0x54)},
-};
-
-static int __init etrax_init(void)
-{
- i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));
- i2c_register_board_info(1, i2c_info2, ARRAY_SIZE(i2c_info2));
- i2c_register_board_info(2, i2c_info3, ARRAY_SIZE(i2c_info3));
- return 0;
-}
-arch_initcall(etrax_init);
diff --git a/arch/cris/arch-v32/kernel/signal.c b/arch/cris/arch-v32/kernel/signal.c
deleted file mode 100644
index 4f2e3ba3bf40..000000000000
--- a/arch/cris/arch-v32/kernel/signal.c
+++ /dev/null
@@ -1,541 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003, Axis Communications AB.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/syscalls.h>
-#include <linux/vmalloc.h>
-
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-#include <arch/hwregs/cpu_vect.h>
-
-extern unsigned long cris_signal_return_page;
-
-/*
- * A syscall in CRIS is really a "break 13" instruction, which is 2
- * bytes. The registers is manipulated so upon return the instruction
- * will be executed again.
- *
- * This relies on that PC points to the instruction after the break call.
- */
-#define RESTART_CRIS_SYS(regs) regs->r10 = regs->orig_r10; regs->erp -= 2;
-
-/* Signal frames. */
-struct signal_frame {
- struct sigcontext sc;
- unsigned long extramask[_NSIG_WORDS - 1];
- unsigned char retcode[8]; /* Trampoline code. */
-};
-
-struct rt_signal_frame {
- struct siginfo *pinfo;
- void *puc;
- struct siginfo info;
- struct ucontext uc;
- unsigned char retcode[8]; /* Trampoline code. */
-};
-
-void do_signal(int restart, struct pt_regs *regs);
-void keep_debug_flags(unsigned long oldccs, unsigned long oldspc,
- struct pt_regs *regs);
-
-static int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
-{
- unsigned int err = 0;
- unsigned long old_usp;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- /*
- * Restore the registers from &sc->regs. sc is already checked
- * for VERIFY_READ since the signal_frame was previously
- * checked in sys_sigreturn().
- */
- if (__copy_from_user(regs, sc, sizeof(struct pt_regs)))
- goto badframe;
-
- /* Make that the user-mode flag is set. */
- regs->ccs |= (1 << (U_CCS_BITNR + CCS_SHIFT));
-
- /* Don't perform syscall restarting */
- regs->exs = -1;
-
- /* Restore the old USP. */
- err |= __get_user(old_usp, &sc->usp);
- wrusp(old_usp);
-
- return err;
-
-badframe:
- return 1;
-}
-
-asmlinkage int sys_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- sigset_t set;
- struct signal_frame __user *frame;
- unsigned long oldspc = regs->spc;
- unsigned long oldccs = regs->ccs;
-
- frame = (struct signal_frame *) rdusp();
-
- /*
- * Since the signal is stacked on a dword boundary, the frame
- * should be dword aligned here as well. It it's not, then the
- * user is trying some funny business.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
-
- if (__get_user(set.sig[0], &frame->sc.oldmask) ||
- (_NSIG_WORDS > 1 && __copy_from_user(&set.sig[1],
- frame->extramask,
- sizeof(frame->extramask))))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->sc))
- goto badframe;
-
- keep_debug_flags(oldccs, oldspc, regs);
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- sigset_t set;
- struct rt_signal_frame __user *frame;
- unsigned long oldspc = regs->spc;
- unsigned long oldccs = regs->ccs;
-
- frame = (struct rt_signal_frame *) rdusp();
-
- /*
- * Since the signal is stacked on a dword boundary, the frame
- * should be dword aligned here as well. It it's not, then the
- * user is trying some funny business.
- */
- if (((long)frame) & 3)
- goto badframe;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
-
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- keep_debug_flags(oldccs, oldspc, regs);
-
- return regs->r10;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/* Setup a signal frame. */
-static int
-setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
- unsigned long mask)
-{
- int err;
- unsigned long usp;
-
- err = 0;
- usp = rdusp();
-
- /*
- * Copy the registers. They are located first in sc, so it's
- * possible to use sc directly.
- */
- err |= __copy_to_user(sc, regs, sizeof(struct pt_regs));
-
- err |= __put_user(mask, &sc->oldmask);
- err |= __put_user(usp, &sc->usp);
-
- return err;
-}
-
-/* Figure out where to put the new signal frame - usually on the stack. */
-static inline void __user *
-get_sigframe(struct ksignal *ksig, size_t frame_size)
-{
- unsigned long sp = sigsp(rdusp(), ksig);
-
- /* Make sure the frame is dword-aligned. */
- sp &= ~3;
-
- return (void __user *)(sp - frame_size);
-}
-
-/* Grab and setup a signal frame.
- *
- * Basically a lot of state-info is stacked, and arranged for the
- * user-mode program to return to the kernel using either a trampiline
- * which performs the syscall sigreturn(), or a provided user-mode
- * trampoline.
- */
-static int
-setup_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- int err;
- unsigned long return_ip;
- struct signal_frame __user *frame;
-
- err = 0;
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= setup_sigcontext(&frame->sc, regs, set->sig[0]);
-
- if (err)
- return -EFAULT;
-
- if (_NSIG_WORDS > 1) {
- err |= __copy_to_user(frame->extramask, &set->sig[1],
- sizeof(frame->extramask));
- }
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up to return from user-space. If provided, use a stub
- * already located in user-space.
- */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long)ksig->ka.sa.sa_restorer;
- } else {
- /* Trampoline - the desired return ip is in the signal return page. */
- return_ip = cris_signal_return_page;
-
- /*
- * This is movu.w __NR_sigreturn, r9; break 13;
- *
- * WE DO NOT USE IT ANY MORE! It's only left here for historical
- * reasons and because gdb uses it as a signature to notice
- * signal handler stack frames.
- */
- err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0));
- err |= __put_user(__NR_sigreturn, (short __user*)(frame->retcode+2));
- err |= __put_user(0xe93d, (short __user*)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up registers for signal handler.
- *
- * Where the code enters now.
- * Where the code enter later.
- * First argument, signo.
- */
- regs->erp = (unsigned long) ksig->ka.sa.sa_handler;
- regs->srp = return_ip;
- regs->r10 = ksig->sig;
-
- /* Actually move the USP to reflect the stacked frame. */
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-static int
-setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs)
-{
- int err;
- unsigned long return_ip;
- struct rt_signal_frame __user *frame;
-
- err = 0;
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
-
- if (err)
- return -EFAULT;
-
- /* Clear all the bits of the ucontext we don't use. */
- err |= __clear_user(&frame->uc, offsetof(struct ucontext, uc_mcontext));
- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
- err |= __save_altstack(&frame->uc.uc_stack, rdusp());
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up to return from user-space. If provided, use a stub
- * already located in user-space.
- */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- return_ip = (unsigned long) ksig->ka.sa.sa_restorer;
- } else {
- /* Trampoline - the desired return ip is in the signal return page. */
- return_ip = cris_signal_return_page + 6;
-
- /*
- * This is movu.w __NR_rt_sigreturn, r9; break 13;
- *
- * WE DO NOT USE IT ANY MORE! It's only left here for historical
- * reasons and because gdb uses it as a signature to notice
- * signal handler stack frames.
- */
- err |= __put_user(0x9c5f, (short __user*)(frame->retcode+0));
-
- err |= __put_user(__NR_rt_sigreturn,
- (short __user*)(frame->retcode+2));
-
- err |= __put_user(0xe93d, (short __user*)(frame->retcode+4));
- }
-
- if (err)
- return -EFAULT;
-
- /*
- * Set up registers for signal handler.
- *
- * Where the code enters now.
- * Where the code enters later.
- * First argument is signo.
- * Second argument is (siginfo_t *).
- * Third argument is unused.
- */
- regs->erp = (unsigned long) ksig->ka.sa.sa_handler;
- regs->srp = return_ip;
- regs->r10 = ksig->sig;
- regs->r11 = (unsigned long) &frame->info;
- regs->r12 = 0;
-
- /* Actually move the usp to reflect the stacked frame. */
- wrusp((unsigned long)frame);
-
- return 0;
-}
-
-/* Invoke a signal handler to, well, handle the signal. */
-static inline void
-handle_signal(int canrestart, struct ksignal *ksig, struct pt_regs *regs)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Check if this got called from a system call. */
- if (canrestart) {
- /* If so, check system call restarting. */
- switch (regs->r10) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- /*
- * This means that the syscall should
- * only be restarted if there was no
- * handler for the signal, and since
- * this point isn't reached unless
- * there is a handler, there's no need
- * to restart.
- */
- regs->r10 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- /*
- * This means restart the syscall if
- * there is no handler, or the handler
- * was registered with SA_RESTART.
- */
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->r10 = -EINTR;
- break;
- }
-
- /* Fall through. */
-
- case -ERESTARTNOINTR:
- /*
- * This means that the syscall should
- * be called again after the signal
- * handler returns.
- */
- RESTART_CRIS_SYS(regs);
- break;
- }
- }
-
- /* Set up the stack frame. */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO)
- ret = setup_rt_frame(ksig, oldset, regs);
- else
- ret = setup_frame(ksig, oldset, regs);
-
- signal_setup_done(ret, ksig, 0);
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- *
- * Also note that the regs structure given here as an argument, is the latest
- * pushed pt_regs. It may or may not be the same as the first pushed registers
- * when the initial usermode->kernelmode transition took place. Therefore
- * we can use user_mode(regs) to see if we came directly from kernel or user
- * mode below.
- */
-void
-do_signal(int canrestart, struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- canrestart = canrestart && ((int)regs->exs >= 0);
-
- /*
- * The common case should go fast, which is why this point is
- * reached from kernel-mode. If that's the case, just return
- * without doing anything.
- */
- if (!user_mode(regs))
- return;
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(canrestart, &ksig, regs);
- return;
- }
-
- /* Got here from a system call? */
- if (canrestart) {
- /* Restart the system call - no handlers present. */
- if (regs->r10 == -ERESTARTNOHAND ||
- regs->r10 == -ERESTARTSYS ||
- regs->r10 == -ERESTARTNOINTR) {
- RESTART_CRIS_SYS(regs);
- }
-
- if (regs->r10 == -ERESTART_RESTARTBLOCK){
- regs->r9 = __NR_restart_syscall;
- regs->erp -= 2;
- }
- }
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
-
-asmlinkage void
-ugdb_trap_user(struct thread_info *ti, int sig)
-{
- if (((user_regs(ti)->exs & 0xff00) >> 8) != SINGLE_STEP_INTR_VECT) {
- /* Zero single-step PC if the reason we stopped wasn't a single
- step exception. This is to avoid relying on it when it isn't
- reliable. */
- user_regs(ti)->spc = 0;
- }
- /* FIXME: Filter out false h/w breakpoint hits (i.e. EDA
- not within any configured h/w breakpoint range). Synchronize with
- what already exists for kernel debugging. */
- if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) {
- /* Break 8: subtract 2 from ERP unless in a delay slot. */
- if (!(user_regs(ti)->erp & 0x1))
- user_regs(ti)->erp -= 2;
- }
- sys_kill(ti->task->pid, sig);
-}
-
-void
-keep_debug_flags(unsigned long oldccs, unsigned long oldspc,
- struct pt_regs *regs)
-{
- if (oldccs & (1 << Q_CCS_BITNR)) {
- /* Pending single step due to single-stepping the break 13
- in the signal trampoline: keep the Q flag. */
- regs->ccs |= (1 << Q_CCS_BITNR);
- /* S flag should be set - complain if it's not. */
- if (!(oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT)))) {
- printk("Q flag but no S flag?");
- }
- regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- /* Assume the SPC is valid and interesting. */
- regs->spc = oldspc;
-
- } else if (oldccs & (1 << (S_CCS_BITNR + CCS_SHIFT))) {
- /* If a h/w bp was set in the signal handler we need
- to keep the S flag. */
- regs->ccs |= (1 << (S_CCS_BITNR + CCS_SHIFT));
- /* Don't keep the old SPC though; if we got here due to
- a single-step, the Q flag should have been set. */
- } else if (regs->spc) {
- /* If we were single-stepping *before* the signal was taken,
- we don't want to restore that state now, because GDB will
- have forgotten all about it. */
- regs->spc = 0;
- regs->ccs &= ~(1 << (S_CCS_BITNR + CCS_SHIFT));
- }
-}
-
-/* Set up the trampolines on the signal return page. */
-int __init
-cris_init_signal(void)
-{
- u16* data = kmalloc(PAGE_SIZE, GFP_KERNEL);
-
- /* This is movu.w __NR_sigreturn, r9; break 13; */
- data[0] = 0x9c5f;
- data[1] = __NR_sigreturn;
- data[2] = 0xe93d;
- /* This is movu.w __NR_rt_sigreturn, r9; break 13; */
- data[3] = 0x9c5f;
- data[4] = __NR_rt_sigreturn;
- data[5] = 0xe93d;
-
- /* Map to userspace with appropriate permissions (no write access...) */
- cris_signal_return_page = (unsigned long)
- __ioremap_prot(virt_to_phys(data), PAGE_SIZE, PAGE_SIGNAL_TRAMPOLINE);
-
- return 0;
-}
-
-__initcall(cris_init_signal);
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
deleted file mode 100644
index d07a3912687e..000000000000
--- a/arch/cris/arch-v32/kernel/time.c
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/arch-v32/kernel/time.c
- *
- * Copyright (C) 2003-2010 Axis Communications AB
- *
- */
-
-#include <linux/timex.h>
-#include <linux/time.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/swap.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/cpufreq.h>
-#include <linux/sched_clock.h>
-#include <linux/mm.h>
-#include <asm/types.h>
-#include <asm/signal.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irq_regs.h>
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-#include <hwregs/intr_vect_defs.h>
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#include <hwregs/clkgen_defs.h>
-#endif
-
-/* Watchdog defines */
-#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
-#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
-/* Number of 763 counts before watchdog bites */
-#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
-
-#define CRISV32_TIMER_FREQ (100000000lu)
-
-unsigned long timer_regs[NR_CPUS] =
-{
- regi_timer0,
-};
-
-extern int set_rtc_mmss(unsigned long nowtime);
-
-#ifdef CONFIG_CPU_FREQ
-static int cris_time_freq_notifier(struct notifier_block *nb,
- unsigned long val, void *data);
-
-static struct notifier_block cris_time_freq_notifier_block = {
- .notifier_call = cris_time_freq_notifier,
-};
-#endif
-
-unsigned long get_ns_in_jiffie(void)
-{
- reg_timer_r_tmr0_data data;
- unsigned long ns;
-
- data = REG_RD(timer, regi_timer0, r_tmr0_data);
- ns = (TIMER0_DIV - data) * 10;
- return ns;
-}
-
-/* From timer MDS describing the hardware watchdog:
- * 4.3.1 Watchdog Operation
- * The watchdog timer is an 8-bit timer with a configurable start value.
- * Once started the watchdog counts downwards with a frequency of 763 Hz
- * (100/131072 MHz). When the watchdog counts down to 1, it generates an
- * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
- * chip.
- */
-/* This gives us 1.3 ms to do something useful when the NMI comes */
-
-/* Right now, starting the watchdog is the same as resetting it */
-#define start_watchdog reset_watchdog
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
-static short int watchdog_key = 42; /* arbitrary 7 bit number */
-#endif
-
-/* Number of pages to consider "out of memory". It is normal that the memory
- * is used though, so set this really low. */
-#define WATCHDOG_MIN_FREE_PAGES 8
-
-#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
-/* for reliable NICE_DOGGY behaviour */
-static int bite_in_progress;
-#endif
-
-void reset_watchdog(void)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
-
-#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
- if (unlikely(bite_in_progress))
- return;
-#endif
- /* Only keep watchdog happy as long as we have memory left! */
- if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
- /* Reset the watchdog with the inverse of the old key */
- /* Invert key, which is 7 bits */
- watchdog_key ^= ETRAX_WD_KEY_MASK;
- wd_ctrl.cnt = ETRAX_WD_CNT;
- wd_ctrl.cmd = regk_timer_start;
- wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
- }
-#endif
-}
-
-/* stop the watchdog - we still need the correct key */
-
-void stop_watchdog(void)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
- watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
- wd_ctrl.cnt = ETRAX_WD_CNT;
- wd_ctrl.cmd = regk_timer_stop;
- wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
-#endif
-}
-
-extern void show_registers(struct pt_regs *regs);
-
-void handle_watchdog_bite(struct pt_regs *regs)
-{
-#if defined(CONFIG_ETRAX_WATCHDOG)
- extern int cause_of_death;
-
- nmi_enter();
- oops_in_progress = 1;
-#if defined(CONFIG_ETRAX_WATCHDOG_NICE_DOGGY)
- bite_in_progress = 1;
-#endif
- printk(KERN_WARNING "Watchdog bite\n");
-
- /* Check if forced restart or unexpected watchdog */
- if (cause_of_death == 0xbedead) {
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- /* There is a bug in Artpec-3 (voodoo TR 78) that requires
- * us to go to lower frequency for the reset to be reliable
- */
- reg_clkgen_rw_clk_ctrl ctrl =
- REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
- ctrl.pll = 0;
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
-#endif
- while(1);
- }
-
- /* Unexpected watchdog, stop the watchdog and dump registers. */
- stop_watchdog();
- printk(KERN_WARNING "Oops: bitten by watchdog\n");
- show_registers(regs);
- oops_in_progress = 0;
- printk("\n"); /* Flush mtdoops. */
-#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- reset_watchdog();
-#endif
- while(1) /* nothing */;
-#endif
-}
-
-extern void cris_profile_sample(struct pt_regs *regs);
-static void __iomem *timer_base;
-
-static int crisv32_clkevt_switch_state(struct clock_event_device *dev)
-{
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_hold,
- .freq = regk_timer_f100,
- };
-
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
- return 0;
-}
-
-static int crisv32_clkevt_next_event(unsigned long evt,
- struct clock_event_device *dev)
-{
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_ld,
- .freq = regk_timer_f100,
- };
-
- REG_WR(timer, timer_base, rw_tmr0_div, evt);
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
-
- ctrl.op = regk_timer_run;
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
-
- return 0;
-}
-
-static irqreturn_t crisv32_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = dev_id;
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_hold,
- .freq = regk_timer_f100,
- };
- reg_timer_rw_ack_intr ack = { .tmr0 = 1 };
- reg_timer_r_masked_intr intr;
-
- intr = REG_RD(timer, timer_base, r_masked_intr);
- if (!intr.tmr0)
- return IRQ_NONE;
-
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
- REG_WR(timer, timer_base, rw_ack_intr, ack);
-
- reset_watchdog();
-#ifdef CONFIG_SYSTEM_PROFILER
- cris_profile_sample(get_irq_regs());
-#endif
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct clock_event_device crisv32_clockevent = {
- .name = "crisv32-timer",
- .rating = 300,
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .set_state_oneshot = crisv32_clkevt_switch_state,
- .set_state_shutdown = crisv32_clkevt_switch_state,
- .tick_resume = crisv32_clkevt_switch_state,
- .set_next_event = crisv32_clkevt_next_event,
-};
-
-/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain. */
-static struct irqaction irq_timer = {
- .handler = crisv32_timer_interrupt,
- .flags = IRQF_TIMER | IRQF_SHARED,
- .name = "crisv32-timer",
- .dev_id = &crisv32_clockevent,
-};
-
-static u64 notrace crisv32_timer_sched_clock(void)
-{
- return REG_RD(timer, timer_base, r_time);
-}
-
-static void __init crisv32_timer_init(void)
-{
- reg_timer_rw_intr_mask timer_intr_mask;
- reg_timer_rw_tmr0_ctrl ctrl = {
- .op = regk_timer_hold,
- .freq = regk_timer_f100,
- };
-
- REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl);
-
- timer_intr_mask = REG_RD(timer, timer_base, rw_intr_mask);
- timer_intr_mask.tmr0 = 1;
- REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask);
-}
-
-void __init time_init(void)
-{
- int irq;
- int ret;
-
- /* Probe for the RTC and read it if it exists.
- * Before the RTC can be probed the loops_per_usec variable needs
- * to be initialized to make usleep work. A better value for
- * loops_per_usec is calculated by the kernel later once the
- * clock has started.
- */
- loops_per_usec = 50;
-
- irq = TIMER0_INTR_VECT;
- timer_base = (void __iomem *) regi_timer0;
-
- crisv32_timer_init();
-
- sched_clock_register(crisv32_timer_sched_clock, 32,
- CRISV32_TIMER_FREQ);
-
- clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time,
- "crisv32-timer", CRISV32_TIMER_FREQ,
- 300, 32, clocksource_mmio_readl_up);
-
- crisv32_clockevent.cpumask = cpu_possible_mask;
- crisv32_clockevent.irq = irq;
-
- ret = setup_irq(irq, &irq_timer);
- if (ret)
- pr_warn("failed to setup irq %d\n", irq);
-
- clockevents_config_and_register(&crisv32_clockevent,
- CRISV32_TIMER_FREQ,
- 2, 0xffffffff);
-
- /* Enable watchdog if we should use one. */
-
-#if defined(CONFIG_ETRAX_WATCHDOG)
- printk(KERN_INFO "Enabling watchdog...\n");
- start_watchdog();
-
- /* If we use the hardware watchdog, we want to trap it as an NMI
- * and dump registers before it resets us. For this to happen, we
- * must set the "m" NMI enable flag (which once set, is unset only
- * when an NMI is taken). */
- {
- unsigned long flags;
- local_save_flags(flags);
- flags |= (1<<30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
- }
-#endif
-
-#ifdef CONFIG_CPU_FREQ
- cpufreq_register_notifier(&cris_time_freq_notifier_block,
- CPUFREQ_TRANSITION_NOTIFIER);
-#endif
-}
-
-#ifdef CONFIG_CPU_FREQ
-static int cris_time_freq_notifier(struct notifier_block *nb,
- unsigned long val, void *data)
-{
- struct cpufreq_freqs *freqs = data;
- if (val == CPUFREQ_POSTCHANGE) {
- reg_timer_r_tmr0_data data;
- reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
- do {
- data = REG_RD(timer, timer_regs[freqs->cpu],
- r_tmr0_data);
- } while (data > 20);
- REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
- }
- return 0;
-}
-#endif
diff --git a/arch/cris/arch-v32/kernel/traps.c b/arch/cris/arch-v32/kernel/traps.c
deleted file mode 100644
index ba54c7eccbaa..000000000000
--- a/arch/cris/arch-v32/kernel/traps.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2003-2006, Axis Communications AB.
- */
-
-#include <linux/ptrace.h>
-#include <linux/extable.h>
-#include <linux/uaccess.h>
-#include <linux/sched/debug.h>
-
-#include <hwregs/supp_reg.h>
-#include <hwregs/intr_vect_defs.h>
-#include <asm/irq.h>
-
-void show_registers(struct pt_regs *regs)
-{
- /*
- * It's possible to use either the USP register or current->thread.usp.
- * USP might not correspond to the current process for all cases this
- * function is called, and current->thread.usp isn't up to date for the
- * current process. Experience shows that using USP is the way to go.
- */
- unsigned long usp = rdusp();
- unsigned long d_mmu_cause;
- unsigned long i_mmu_cause;
-
- printk("CPU: %d\n", smp_processor_id());
-
- printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
- regs->erp, regs->srp, regs->ccs, usp, regs->mof);
-
- printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
-
- printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
-
- printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
-
- printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10, regs->acr);
-
- printk(" sp: %08lx\n", (unsigned long)regs);
-
- SUPP_BANK_SEL(BANK_IM);
- SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause);
-
- SUPP_BANK_SEL(BANK_DM);
- SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause);
-
- printk(" Data MMU Cause: %08lx\n", d_mmu_cause);
- printk("Instruction MMU Cause: %08lx\n", i_mmu_cause);
-
- printk("Process %s (pid: %d, stackpage=%08lx)\n",
- current->comm, current->pid, (unsigned long)current);
-
- /*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (!user_mode(regs)) {
- int i;
-
- show_stack(NULL, (unsigned long *)usp);
-
- /*
- * If the previous stack-dump wasn't a kernel one, dump the
- * kernel stack now.
- */
- if (usp != 0)
- show_stack(NULL, NULL);
-
- printk("\nCode: ");
-
- if (regs->erp < PAGE_OFFSET)
- goto bad_value;
-
- /*
- * Quite often the value at regs->erp doesn't point to the
- * interesting instruction, which often is the previous
- * instruction. So dump at an offset large enough that the
- * instruction decoding should be in sync at the interesting
- * point, but small enough to fit on a row. The regs->erp
- * location is pointed out in a ksymoops-friendly way by
- * wrapping the byte for that address in parenthesises.
- */
- for (i = -12; i < 12; i++) {
- unsigned char c;
-
- if (__get_user(c, &((unsigned char *)regs->erp)[i])) {
-bad_value:
- printk(" Bad IP value.");
- break;
- }
-
- if (i == 0)
- printk("(%02x) ", c);
- else
- printk("%02x ", c);
- }
- printk("\n");
- }
-}
-
-void arch_enable_nmi(void)
-{
- unsigned long flags;
-
- local_save_flags(flags);
- flags |= (1 << 30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
-}
-
-extern void (*nmi_handler)(struct pt_regs *);
-void handle_nmi(struct pt_regs *regs)
-{
-#ifdef CONFIG_ETRAXFS
- reg_intr_vect_r_nmi r;
-#endif
-
- if (nmi_handler)
- nmi_handler(regs);
-
-#ifdef CONFIG_ETRAXFS
- /* Wait until nmi is no longer active. */
- do {
- r = REG_RD(intr_vect, regi_irq, r_nmi);
- } while (r.ext == regk_intr_vect_on);
-#endif
-}
-
-
-#ifdef CONFIG_BUG
-extern void die_if_kernel(const char *str, struct pt_regs *regs, long err);
-
-/* Copy of the regs at BUG() time. */
-struct pt_regs BUG_regs;
-
-void do_BUG(char *file, unsigned int line)
-{
- printk("kernel BUG at %s:%d!\n", file, line);
- die_if_kernel("Oops", &BUG_regs, 0);
-}
-EXPORT_SYMBOL(do_BUG);
-
-void fixup_BUG(struct pt_regs *regs)
-{
- BUG_regs = *regs;
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
- /*
- * Fixup the BUG arguments through exception handlers.
- */
- {
- const struct exception_table_entry *fixup;
-
- /*
- * ERP points at the "break 14" + 2, compensate for the 2
- * bytes.
- */
- fixup = search_exception_tables(instruction_pointer(regs) - 2);
- if (fixup) {
- /* Adjust the instruction pointer in the stackframe. */
- instruction_pointer(regs) = fixup->fixup;
- arch_fixup(regs);
- }
- }
-#else
- /* Dont try to lookup the filename + line, just dump regs. */
- do_BUG("unknown", 0);
-#endif
-}
-
-/*
- * Break 14 handler. Save regs and jump into the fixup_BUG.
- */
-__asm__ ( ".text\n\t"
- ".global breakh_BUG\n\t"
- "breakh_BUG:\n\t"
- SAVE_ALL
- KGDB_FIXUP
- "move.d $sp, $r10\n\t"
- "jsr fixup_BUG\n\t"
- "nop\n\t"
- "jump ret_from_intr\n\t"
- "nop\n\t");
-
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-void
-handle_BUG(struct pt_regs *regs)
-{
-}
-#endif
-#endif
diff --git a/arch/cris/arch-v32/lib/Makefile b/arch/cris/arch-v32/lib/Makefile
deleted file mode 100644
index e91cf02f625d..000000000000
--- a/arch/cris/arch-v32/lib/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for Etrax-specific library files..
-#
-
-lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \
- csumcpfruser.o delay.o strcmp.o
-
diff --git a/arch/cris/arch-v32/lib/checksum.S b/arch/cris/arch-v32/lib/checksum.S
deleted file mode 100644
index f773d4d93609..000000000000
--- a/arch/cris/arch-v32/lib/checksum.S
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum routine using movem
- * Copyright (c) 1998-2007 Axis Communications AB
- *
- * csum_partial(const unsigned char * buff, int len, unsigned int sum)
- */
-
- .globl csum_partial
- .type csum_partial,@function
-csum_partial:
-
- ;; r10 - src
- ;; r11 - length
- ;; r12 - checksum
-
- ;; Optimized for large packets
- subq 10*4, $r11
- blt _word_loop
- move.d $r11, $acr
-
- subq 9*4,$sp
- clearf c
- movem $r8,[$sp]
-
- ;; do a movem checksum
-
-_mloop: movem [$r10+],$r9 ; read 10 longwords
- ;; Loop count without touching the c flag.
- addoq -10*4, $acr, $acr
- ;; perform dword checksumming on the 10 longwords
-
- addc $r0,$r12
- addc $r1,$r12
- addc $r2,$r12
- addc $r3,$r12
- addc $r4,$r12
- addc $r5,$r12
- addc $r6,$r12
- addc $r7,$r12
- addc $r8,$r12
- addc $r9,$r12
-
- ;; test $acr without trashing carry.
- move.d $acr, $acr
- bpl _mloop
- ;; r11 <= acr is not really needed in the mloop, just using the dslot
- ;; to prepare for what is needed after mloop.
- move.d $acr, $r11
-
- ;; fold the last carry into r13
- addc 0, $r12
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- addq 10*4,$r11 ; compensate for last loop underflowing length
-
- moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9
- lsrq 16,$r9
-
- move.d $r12,$r13
- lsrq 16,$r13 ; r13 = checksum >> 16
- and.d $r9,$r12 ; checksum = checksum & 0xffff
-
-_no_fold:
- subq 2,$r11
- blt _no_words
- add.d $r13,$r12 ; checksum += r13
-
- ;; checksum the rest of the words
-_wloop: subq 2,$r11
- bge _wloop
- addu.w [$r10+],$r12
-
-_no_words:
- addq 2,$r11
- ;; see if we have one odd byte more
- bne _do_byte
- nop
- ret
- move.d $r12,$r10
-
-_do_byte:
- ;; copy and checksum the last byte
- addu.b [$r10],$r12
- ret
- move.d $r12,$r10
-
- .size csum_partial, .-csum_partial
diff --git a/arch/cris/arch-v32/lib/checksumcopy.S b/arch/cris/arch-v32/lib/checksumcopy.S
deleted file mode 100644
index a76e586d4114..000000000000
--- a/arch/cris/arch-v32/lib/checksumcopy.S
+++ /dev/null
@@ -1,95 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * A fast checksum+copy routine using movem
- * Copyright (c) 1998-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- * csum_partial_copy_nocheck(const char *src, char *dst,
- * int len, unsigned int sum)
- */
-
- .globl csum_partial_copy_nocheck
- .type csum_partial_copy_nocheck,@function
-csum_partial_copy_nocheck:
-
- ;; r10 - src
- ;; r11 - dst
- ;; r12 - length
- ;; r13 - checksum
-
- ;; Optimized for large packets
- subq 10*4, $r12
- blt _word_loop
- move.d $r12, $acr
-
- subq 9*4,$sp
- clearf c
- movem $r8,[$sp]
-
- ;; do a movem copy and checksum
-1: ;; A failing userspace access (the read) will have this as PC.
-_mloop: movem [$r10+],$r9 ; read 10 longwords
- addoq -10*4, $acr, $acr ; loop counter in latency cycle
- movem $r9,[$r11+] ; write 10 longwords
-
- ;; perform dword checksumming on the 10 longwords
- addc $r0,$r13
- addc $r1,$r13
- addc $r2,$r13
- addc $r3,$r13
- addc $r4,$r13
- addc $r5,$r13
- addc $r6,$r13
- addc $r7,$r13
- addc $r8,$r13
- addc $r9,$r13
-
- ;; test $acr, without trashing carry.
- move.d $acr, $acr
- bpl _mloop
- ;; r12 <= acr is needed after mloop and in the exception handlers.
- move.d $acr, $r12
-
- ;; fold the last carry into r13
- addc 0, $r13
- movem [$sp+],$r8 ; restore regs
-
-_word_loop:
- addq 10*4,$r12 ; compensate for last loop underflowing length
-
- ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below
- ;; r9 can be used as temporary.
- move.d $r13,$r9
- lsrq 16,$r9 ; r0 = checksum >> 16
- and.d 0xffff,$r13 ; checksum = checksum & 0xffff
-
- subq 2, $r12
- blt _no_words
- add.d $r9,$r13 ; checksum += r0
-
- ;; copy and checksum the rest of the words
-2: ;; A failing userspace access for the read below will have this as PC.
-_wloop: move.w [$r10+],$r9
- addu.w $r9,$r13
- subq 2,$r12
- bge _wloop
- move.w $r9,[$r11+]
-
-_no_words:
- addq 2,$r12
- bne _do_byte
- nop
- ret
- move.d $r13,$r10
-
-_do_byte:
- ;; copy and checksum the last byte
-3: ;; A failing userspace access for the read below will have this as PC.
- move.b [$r10],$r9
- addu.b $r9,$r13
- move.b $r9,[$r11]
- ret
- move.d $r13,$r10
-
- .size csum_partial_copy_nocheck, . - csum_partial_copy_nocheck
diff --git a/arch/cris/arch-v32/lib/csumcpfruser.S b/arch/cris/arch-v32/lib/csumcpfruser.S
deleted file mode 100644
index 093cd757fcfa..000000000000
--- a/arch/cris/arch-v32/lib/csumcpfruser.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Add-on to transform csum_partial_copy_nocheck in checksumcopy.S into
- * csum_partial_copy_from_user by adding exception records.
- *
- * Copyright (C) 2001, 2003 Axis Communications AB.
- *
- * Author: Hans-Peter Nilsson.
- */
-
-#include <asm/errno.h>
-
-/* Same function body, but a different name. If we just added exception
- records to _csum_partial_copy_nocheck and made it generic, we wouldn't
- know a user fault from a kernel fault and we would have overhead in
- each kernel caller for the error-pointer argument.
-
- unsigned int csum_partial_copy_from_user
- (const char *src, char *dst, int len, unsigned int sum, int *errptr);
-
- Note that the errptr argument is only set if we encounter an error.
- It is conveniently located on the stack, so the normal function body
- does not have to handle it. */
-
-#define csum_partial_copy_nocheck csum_partial_copy_from_user
-
-/* There are local labels numbered 1, 2 and 3 present to mark the
- different from-user accesses. */
-#include "checksumcopy.S"
-
- .section .fixup,"ax"
-
-;; Here from the movem loop; restore stack.
-4:
- movem [$sp+],$r8
-;; r12 is already decremented. Add back chunk_size-2.
- addq 40-2,$r12
-
-;; Here from the word loop; r12 is off by 2; add it back.
-5:
- addq 2,$r12
-
-;; Here from a failing single byte.
-6:
-
-;; Signal in *errptr that we had a failing access.
- move.d [$sp],$acr
- moveq -EFAULT,$r9
- subq 4,$sp
- move.d $r9,[$acr]
-
-;; Clear the rest of the destination area using memset. Preserve the
-;; checksum for the readable bytes.
- move.d $r13,[$sp]
- subq 4,$sp
- move.d $r11,$r10
- move $srp,[$sp]
- jsr memset
- clear.d $r11
-
- move [$sp+],$srp
- ret
- move.d [$sp+],$r10
-
- .previous
- .section __ex_table,"a"
- .dword 1b,4b
- .dword 2b,5b
- .dword 3b,6b
- .previous
diff --git a/arch/cris/arch-v32/lib/delay.c b/arch/cris/arch-v32/lib/delay.c
deleted file mode 100644
index db06a94ef646..000000000000
--- a/arch/cris/arch-v32/lib/delay.c
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Precise Delay Loops for ETRAX FS
- *
- * Copyright (C) 2006 Axis Communications AB.
- *
- */
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-
-/*
- * On ETRAX FS, we can check the free-running read-only 100MHz timer
- * getting 32-bit 10ns precision, theoretically good for 42.94967295
- * seconds. Unsigned arithmetic and careful expression handles
- * wrapping.
- */
-
-void cris_delay10ns(u32 n10ns)
-{
- u32 t0 = REG_RD(timer, regi_timer0, r_time);
- while (REG_RD(timer, regi_timer0, r_time) - t0 < n10ns)
- ;
-}
-EXPORT_SYMBOL(cris_delay10ns);
diff --git a/arch/cris/arch-v32/lib/memset.c b/arch/cris/arch-v32/lib/memset.c
deleted file mode 100644
index c94ea9b3ec29..000000000000
--- a/arch/cris/arch-v32/lib/memset.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* A memset for CRIS.
- Copyright (C) 1999-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-/* Note the multiple occurrence of the expression "12*4", including the
- asm. It is hard to get it into the asm in a good way. Thus better to
- expose the problem everywhere: no macro. */
-
-/* Assuming one cycle per dword written or read (ok, not really true; the
- world is not ideal), and one cycle per instruction, then 43+3*(n/48-1)
- <= 24+24*(n/48-1) so n >= 45.7; n >= 0.9; we win on the first full
- 48-byte block to set. */
-
-#define MEMSET_BY_BLOCK_THRESHOLD (1 * 48)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *memset(void *pdst, int c, unsigned int plen)
-{
- /* Now we want the parameters in special registers. Make sure the
- compiler does something usable with this. */
-
- register char *return_dst __asm__ ("r10") = pdst;
- register int n __asm__ ("r12") = plen;
- register int lc __asm__ ("r11") = c;
-
- /* Most apps use memset sanely. Memsetting about 3..4 bytes or less get
- penalized here compared to the generic implementation. */
-
- /* This is fragile performancewise at best. Check with newer GCC
- releases, if they compile cascaded "x |= x << 8" to sane code. */
- __asm__("movu.b %0,r13 \n\
- lslq 8,r13 \n\
- move.b %0,r13 \n\
- move.d r13,%0 \n\
- lslq 16,r13 \n\
- or.d r13,%0"
- : "=r" (lc) /* Inputs. */
- : "0" (lc) /* Outputs. */
- : "r13"); /* Trash. */
-
- {
- register char *dst __asm__ ("r13") = pdst;
-
- if (((unsigned long) pdst & 3) != 0
- /* Oops! n = 0 must be a valid call, regardless of alignment. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- *dst = (char) lc;
- n--;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- *(short *) dst = lc;
- n -= 2;
- dst += 2;
- }
- }
-
- /* Decide which setting method to use. */
- if (n >= MEMSET_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-block sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%4,$r13-$r12-$r11 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- move.d r11,r0 \n\
- move.d r11,r1 \n\
- move.d r11,r2 \n\
- move.d r11,r3 \n\
- move.d r11,r4 \n\
- move.d r11,r5 \n\
- move.d r11,r6 \n\
- move.d r11,r7 \n\
- move.d r11,r8 \n\
- move.d r11,r9 \n\
- move.d r11,r10 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" subq 12*4,r12 \n\
- bge 0b \n\
- movem r11,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 12*4,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (n), "r" (lc));
- }
-
- /* An ad-hoc unroll, used for 4*12-1..16 bytes. */
- while (n >= 16)
- {
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = (char) lc;
- break;
-
- case 2:
- *(short *) dst = (short) lc;
- break;
-
- case 3:
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 4:
- *(long *) dst = lc;
- break;
-
- case 5:
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 6:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 7:
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 8:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 9:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 10:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 11:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
-
- case 12:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc;
- break;
-
- case 13:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *dst = (char) lc;
- break;
-
- case 14:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc;
- break;
-
- case 15:
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(long *) dst = lc; dst += 4;
- *(short *) dst = (short) lc; dst += 2;
- *dst = (char) lc;
- break;
- }
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v32/lib/strcmp.S b/arch/cris/arch-v32/lib/strcmp.S
deleted file mode 100644
index 8f7a1ee62591..000000000000
--- a/arch/cris/arch-v32/lib/strcmp.S
+++ /dev/null
@@ -1,21 +0,0 @@
-; strcmp.S -- CRISv32 version.
-; Copyright (C) 2008 AXIS Communications AB
-; Written by Edgar E. Iglesias
-;
-; This source code is licensed under the GNU General Public License,
-; Version 2. See the file COPYING for more details.
-
- .global strcmp
- .type strcmp,@function
-strcmp:
-1:
- move.b [$r10+], $r12
- seq $r13
- sub.b [$r11+], $r12
- or.b $r12, $r13
- beq 1b
- nop
-
- ret
- movs.b $r12, $r10
- .size strcmp, . - strcmp
diff --git a/arch/cris/arch-v32/lib/string.c b/arch/cris/arch-v32/lib/string.c
deleted file mode 100644
index c7bd6ebdc93c..000000000000
--- a/arch/cris/arch-v32/lib/string.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* A memcpy for CRIS.
- Copyright (C) 1994-2005 Axis Communications.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions
- are met:
-
- 1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-
- 2. Neither the name of Axis Communications nor the names of its
- contributors may be used to endorse or promote products derived
- from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS
- ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS
- COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE. */
-
-/* FIXME: This file should really only be used for reference, as the
- result is somewhat depending on gcc generating what we expect rather
- than what we describe. An assembly file should be used instead. */
-
-#include <stddef.h>
-
-/* Break even between movem and move16 is really at 38.7 * 2, but
- modulo 44, so up to the next multiple of 44, we use ordinary code. */
-#define MEMCPY_BY_BLOCK_THRESHOLD (44 * 2)
-
-/* No name ambiguities in this file. */
-__asm__ (".syntax no_register_prefix");
-
-void *
-memcpy(void *pdst, const void *psrc, size_t pn)
-{
- /* Now we want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- If gcc was allright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register void *return_dst __asm__ ("r10") = pdst;
- register unsigned char *dst __asm__ ("r13") = pdst;
- register unsigned const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- n--;
- *dst = *src;
- src++;
- dst++;
- }
-
- if ((unsigned long) dst & 2)
- {
- n -= 2;
- *(short *) dst = *(short *) src;
- src += 2;
- dst += 2;
- }
- }
-
- /* Decide which copying method to use. */
- if (n >= MEMCPY_BY_BLOCK_THRESHOLD)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile
- ("\
- ;; GCC does promise correct register allocations, but let's \n\
- ;; make sure it keeps its promises. \n\
- .ifnc %0-%1-%2,$r13-$r11-$r12 \n\
- .error \"GCC reg alloc bug: %0-%1-%4 != $r13-$r12-$r11\" \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,sp \n\
- movem r10,[sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop. \n\
- subq 44,r12 \n\
-0: \n\
-"
-#ifdef __arch_common_v10_v32
- /* Cater to branch offset difference between v32 and v10. We
- assume the branch below has an 8-bit offset. */
-" setf\n"
-#endif
-" movem [r11+],r10 \n\
- subq 44,r12 \n\
- bge 0b \n\
- movem r10,[r13+] \n\
- \n\
- ;; Compensate for last loop underflowing n. \n\
- addq 44,r12 \n\
- \n\
- ;; Restore registers from stack. \n\
- movem [sp+],r10"
-
- /* Outputs. */
- : "=r" (dst), "=r" (src), "=r" (n)
-
- /* Inputs. */
- : "0" (dst), "1" (src), "2" (n));
- }
-
- while (n >= 16)
- {
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
-
- n -= 16;
- }
-
- switch (n)
- {
- case 0:
- break;
-
- case 1:
- *dst = *src;
- break;
-
- case 2:
- *(short *) dst = *(short *) src;
- break;
-
- case 3:
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 4:
- *(long *) dst = *(long *) src;
- break;
-
- case 5:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 6:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 7:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 8:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 9:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 10:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 11:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
-
- case 12:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src;
- break;
-
- case 13:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *dst = *src;
- break;
-
- case 14:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src;
- break;
-
- case 15:
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(long *) dst = *(long *) src; dst += 4; src += 4;
- *(short *) dst = *(short *) src; dst += 2; src += 2;
- *dst = *src;
- break;
- }
-
- return return_dst;
-}
diff --git a/arch/cris/arch-v32/lib/usercopy.c b/arch/cris/arch-v32/lib/usercopy.c
deleted file mode 100644
index 04e78b6ffa22..000000000000
--- a/arch/cris/arch-v32/lib/usercopy.c
+++ /dev/null
@@ -1,458 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * User address space access functions.
- * The non-inlined parts of asm-cris/uaccess.h are here.
- *
- * Copyright (C) 2000, 2003 Axis Communications AB.
- *
- * Written by Hans-Peter Nilsson.
- * Pieces used from memcpy, originally by Kenny Ranerup long time ago.
- */
-
-#include <linux/uaccess.h>
-
-/* Asm:s have been tweaked (within the domain of correctness) to give
- satisfactory results for "gcc version 3.2.1 Axis release R53/1.53-v32".
-
- Check regularly...
-
- Note that for CRISv32, the PC saved at a bus-fault is the address
- *at* the faulting instruction, with a special case for instructions
- in delay slots: then it's the address of the branch. Note also that
- in contrast to v10, a postincrement in the instruction is *not*
- performed at a bus-fault; the register is seen having the original
- value in fault handlers. */
-
-
-/* Copy to userspace. This is based on the memcpy used for
- kernel-to-kernel copying; see "string.c". */
-
-unsigned long __copy_user(void __user *pdst, const void *psrc, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- /* When src is aligned but not dst, this makes a few extra needless
- cycles. I believe it would take as many to check that the
- re-alignment was unnecessary. */
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes; so we
- don't have to check further for overflows. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_copy_to_user_1 (dst, src, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_copy_to_user_2 (dst, src, retn);
- n -= 2;
- }
- }
-
- /* Movem is dirt cheap. The overheap is low enough to always use the
- minimum possible block size as the threshold. */
- if (n >= 44)
- {
- /* For large copies we use 'movem'. */
-
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile ("\
- ;; Check that the register asm declaration got right. \n\
- ;; The GCC manual explicitly says TRT will happen. \n\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
-0: \n\
- movem [$r11+],$r10 \n\
- subq 44,$r12 \n\
-1: bge 0b \n\
- movem $r10,[$r13+] \n\
-3: \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
-4: \n\
-; When failing on any of the 1..44 bytes in a chunk, we adjust back the \n\
-; source pointer and just drop through to the by-16 and by-4 loops to \n\
-; get the correct number of failing bytes. This necessarily means a \n\
-; few extra exceptions, but invalid user pointers shouldn't happen in \n\
-; time-critical code anyway. \n\
- jump 3b \n\
- subq 44,$r11 \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 1b,4b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
-
- }
-
- while (n >= 16)
- {
- __asm_copy_to_user_16 (dst, src, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_copy_to_user_4 (dst, src, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_copy_to_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_to_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_to_user_3 (dst, src, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__copy_user);
-
-/* Copy from user to kernel. The return-value is the number of bytes that were
- inaccessible. */
-unsigned long __copy_user_in(void *pdst, const void __user *psrc,
- unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pdst;
- register const char *src __asm__ ("r11") = psrc;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
- /* The best reason to align src is that we then know that a read-fault
- was for aligned bytes; there's no 1..3 remaining good bytes to
- pickle. */
- if (((unsigned long) src & 3) != 0)
- {
- if (((unsigned long) src & 1) && n != 0)
- {
- __asm_copy_from_user_1 (dst, src, retn);
- n--;
- if (retn != 0)
- goto exception;
- }
-
- if (((unsigned long) src & 2) && n >= 2)
- {
- __asm_copy_from_user_2 (dst, src, retn);
- n -= 2;
- if (retn != 0)
- goto exception;
- }
-
- }
-
- /* Movem is dirt cheap. The overheap is low enough to always use the
- minimum possible block size as the threshold. */
- if (n >= 44)
- {
- /* It is not optimal to tell the compiler about clobbering any
- registers; that will move the saving/restoring of those registers
- to the function prologue/epilogue, and make non-movem sizes
- suboptimal. */
- __asm__ volatile ("\
- .ifnc %0%1%2%3,$r13$r11$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll use in the movem process \n\
- ;; on the stack. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- ;; Now we've got this: \n\
- ;; r11 - src \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 44,$r12 \n\
-0: \n\
- movem [$r11+],$r10 \n\
- \n\
- subq 44,$r12 \n\
- bge 0b \n\
- movem $r10,[$r13+] \n\
- \n\
-4: \n\
- addq 44,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
- .section .fixup,\"ax\" \n\
- \n\
-;; Do not jump back into the loop if we fail. For some uses, we get a \n\
-;; page fault somewhere on the line. Without checking for page limits, \n\
-;; we don't know where, but we need to copy accurately and keep an \n\
-;; accurate count; not just clear the whole line. To do that, we fall \n\
-;; down in the code below, proceeding with smaller amounts. It should \n\
-;; be kept in mind that we have to cater to code like what at one time \n\
-;; was in fs/super.c: \n\
-;; i = size - copy_from_user((void *)page, data, size); \n\
-;; which would cause repeated faults while clearing the remainder of \n\
-;; the SIZE bytes at PAGE after the first fault. \n\
-;; A caveat here is that we must not fall through from a failing page \n\
-;; to a valid page. \n\
- \n\
-3: \n\
- jump 4b ;; Fall through, pretending the fault didn't happen. \n\
- nop \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 0b,3b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (src), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (src), "2" (n), "3" (retn));
- }
-
- /* Either we directly start copying here, using dword copying in a loop,
- or we copy as much as possible with 'movem' and then the last block
- (<44 bytes) is copied here. This will work since 'movem' will have
- updated src, dst and n. (Except with failing src.)
-
- Since we want to keep src accurate, we can't use
- __asm_copy_from_user_N with N != (1, 2, 4); it updates dst and
- retn, but not src (by design; it's value is ignored elsewhere). */
-
- while (n >= 4)
- {
- __asm_copy_from_user_4 (dst, src, retn);
- n -= 4;
-
- if (retn)
- goto exception;
- }
-
- /* If we get here, there were no memory read faults. */
- switch (n)
- {
- /* These copies are at least "naturally aligned" (so we don't have
- to check each byte), due to the src alignment code before the
- movem loop. The *_3 case *will* get the correct count for retn. */
- case 0:
- /* This case deliberately left in (if you have doubts check the
- generated assembly code). */
- break;
- case 1:
- __asm_copy_from_user_1 (dst, src, retn);
- break;
- case 2:
- __asm_copy_from_user_2 (dst, src, retn);
- break;
- case 3:
- __asm_copy_from_user_3 (dst, src, retn);
- break;
- }
-
- /* If we get here, retn correctly reflects the number of failing
- bytes. */
- return retn;
-
-exception:
- return retn + n;
-}
-EXPORT_SYMBOL(__copy_user_in);
-
-/* Zero userspace. */
-unsigned long __do_clear_user(void __user *pto, unsigned long pn)
-{
- /* We want the parameters put in special registers.
- Make sure the compiler is able to make something useful of this.
- As it is now: r10 -> r13; r11 -> r11 (nop); r12 -> r12 (nop).
-
- FIXME: Comment for old gcc version. Check.
- If gcc was alright, it really would need no temporaries, and no
- stack space to save stuff on. */
-
- register char *dst __asm__ ("r13") = pto;
- register int n __asm__ ("r12") = pn;
- register int retn __asm__ ("r10") = 0;
-
-
- if (((unsigned long) dst & 3) != 0
- /* Don't align if we wouldn't copy more than a few bytes. */
- && n >= 3)
- {
- if ((unsigned long) dst & 1)
- {
- __asm_clear_1 (dst, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2)
- {
- __asm_clear_2 (dst, retn);
- n -= 2;
- }
- }
-
- /* Decide which copying method to use.
- FIXME: This number is from the "ordinary" kernel memset. */
- if (n >= 48)
- {
- /* For large clears we use 'movem' */
-
- /* It is not optimal to tell the compiler about clobbering any
- call-saved registers; that will move the saving/restoring of
- those registers to the function prologue/epilogue, and make
- non-movem sizes suboptimal.
-
- This method is not foolproof; it assumes that the "asm reg"
- declarations at the beginning of the function really are used
- here (beware: they may be moved to temporary registers).
- This way, we do not have to save/move the registers around into
- temporaries; we can safely use them straight away.
-
- If you want to check that the allocation was right; then
- check the equalities in the first comment. It should say
- something like "r13=r13, r11=r11, r12=r12". */
- __asm__ volatile ("\
- .ifnc %0%1%2,$r13$r12$r10 \n\
- .err \n\
- .endif \n\
- \n\
- ;; Save the registers we'll clobber in the movem process \n\
- ;; on the stack. Don't mention them to gcc, it will only be \n\
- ;; upset. \n\
- subq 11*4,$sp \n\
- movem $r10,[$sp] \n\
- \n\
- clear.d $r0 \n\
- clear.d $r1 \n\
- clear.d $r2 \n\
- clear.d $r3 \n\
- clear.d $r4 \n\
- clear.d $r5 \n\
- clear.d $r6 \n\
- clear.d $r7 \n\
- clear.d $r8 \n\
- clear.d $r9 \n\
- clear.d $r10 \n\
- clear.d $r11 \n\
- \n\
- ;; Now we've got this: \n\
- ;; r13 - dst \n\
- ;; r12 - n \n\
- \n\
- ;; Update n for the first loop \n\
- subq 12*4,$r12 \n\
-0: \n\
- subq 12*4,$r12 \n\
-1: \n\
- bge 0b \n\
- movem $r11,[$r13+] \n\
- \n\
- addq 12*4,$r12 ;; compensate for last loop underflowing n \n\
- \n\
- ;; Restore registers from stack \n\
- movem [$sp+],$r10 \n\
-2: \n\
- .section .fixup,\"ax\" \n\
-3: \n\
- movem [$sp],$r10 \n\
- addq 12*4,$r10 \n\
- addq 12*4,$r13 \n\
- movem $r10,[$sp] \n\
- jump 0b \n\
- clear.d $r10 \n\
- \n\
- .previous \n\
- .section __ex_table,\"a\" \n\
- .dword 1b,3b \n\
- .previous"
-
- /* Outputs */ : "=r" (dst), "=r" (n), "=r" (retn)
- /* Inputs */ : "0" (dst), "1" (n), "2" (retn)
- /* Clobber */ : "r11");
- }
-
- while (n >= 16)
- {
- __asm_clear_16 (dst, retn);
- n -= 16;
- }
-
- /* Having a separate by-four loops cuts down on cache footprint.
- FIXME: Test with and without; increasing switch to be 0..15. */
- while (n >= 4)
- {
- __asm_clear_4 (dst, retn);
- n -= 4;
- }
-
- switch (n)
- {
- case 0:
- break;
- case 1:
- __asm_clear_1 (dst, retn);
- break;
- case 2:
- __asm_clear_2 (dst, retn);
- break;
- case 3:
- __asm_clear_3 (dst, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__do_clear_user);
diff --git a/arch/cris/arch-v32/mach-a3/Kconfig b/arch/cris/arch-v32/mach-a3/Kconfig
deleted file mode 100644
index 7b63755544dd..000000000000
--- a/arch/cris/arch-v32/mach-a3/Kconfig
+++ /dev/null
@@ -1,111 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if CRIS_MACH_ARTPEC3
-
-menu "Artpec-3 options"
- depends on CRIS_MACH_ARTPEC3
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- default "c0000000"
-
-config ETRAX_L2CACHE
- bool
- default y
-
-config ETRAX_SERIAL_PORTS
- int
- default 5
-
-config ETRAX_DDR2_MRS
- hex "DDR2 MRS"
- default "0"
-
-config ETRAX_DDR2_TIMING
- hex "DDR2 SDRAM timing"
- default "0"
- help
- SDRAM timing parameters.
-
-config ETRAX_DDR2_CONFIG
- hex "DDR2 config"
- default "0"
-
-config ETRAX_DDR2_LATENCY
- hex "DDR2 latency"
- default "0"
-
-config ETRAX_PIO_CE0_CFG
- hex "PIO CE0 configuration"
- default "0"
-
-config ETRAX_PIO_CE1_CFG
- hex "PIO CE1 configuration"
- default "0"
-
-config ETRAX_PIO_CE2_CFG
- hex "PIO CE2 configuration"
- default "0"
-
-config ETRAX_DEF_GIO_PA_OE
- hex "GIO_PA_OE"
- default "00000000"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PA_OUT
- hex "GIO_PA_OUT"
- default "00000000"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_GIO_PB_OE
- hex "GIO_PB_OE"
- default "000000000"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PB_OUT
- hex "GIO_PB_OUT"
- default "000000000"
- help
- Configures the initial data for the general port B bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PC_OE
- hex "GIO_PC_OE"
- default "00000"
- help
- Configures the direction of general port C bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PC_OUT
- hex "GIO_PC_OUT"
- default "00000"
- help
- Configures the initial data for the general port C bits. Most
- products should use 00000 here.
-
-endmenu
-
-endif
diff --git a/arch/cris/arch-v32/mach-a3/Makefile b/arch/cris/arch-v32/mach-a3/Makefile
deleted file mode 100644
index 0cc6eebacbed..000000000000
--- a/arch/cris/arch-v32/mach-a3/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := dma.o pinmux.o arbiter.o
-
-clean:
-
diff --git a/arch/cris/arch-v32/mach-a3/arbiter.c b/arch/cris/arch-v32/mach-a3/arbiter.c
deleted file mode 100644
index 076182cc65a3..000000000000
--- a/arch/cris/arch-v32/mach-a3/arbiter.c
+++ /dev/null
@@ -1,635 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Memory arbiter functions. Allocates bandwidth through the
- * arbiter and sets up arbiter breakpoints.
- *
- * The algorithm first assigns slots to the clients that has specified
- * bandwidth (e.g. ethernet) and then the remaining slots are divided
- * on all the active clients.
- *
- * Copyright (c) 2004-2007 Axis Communications AB.
- *
- * The artpec-3 has two arbiters. The memory hierarchy looks like this:
- *
- *
- * CPU DMAs
- * | |
- * | |
- * -------------- ------------------
- * | foo arbiter|----| Internal memory|
- * -------------- ------------------
- * |
- * --------------
- * | L2 cache |
- * --------------
- * |
- * h264 etc |
- * | |
- * | |
- * --------------
- * | bar arbiter|
- * --------------
- * |
- * ---------
- * | SDRAM |
- * ---------
- *
- */
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_foo_defs.h>
-#include <hwregs/marb_bar_defs.h>
-#include <arbiter.h>
-#include <hwregs/intr_vect.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <asm/io.h>
-#include <asm/irq_regs.h>
-
-#define D(x)
-
-struct crisv32_watch_entry {
- unsigned long instance;
- watch_callback *cb;
- unsigned long start;
- unsigned long end;
- int used;
-};
-
-#define NUMBER_OF_BP 4
-#define SDRAM_BANDWIDTH 400000000
-#define INTMEM_BANDWIDTH 400000000
-#define NBR_OF_SLOTS 64
-#define NBR_OF_REGIONS 2
-#define NBR_OF_CLIENTS 15
-#define ARBITERS 2
-#define UNASSIGNED 100
-
-struct arbiter {
- unsigned long instance;
- int nbr_regions;
- int nbr_clients;
- int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
- int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-};
-
-static struct crisv32_watch_entry watches[ARBITERS][NUMBER_OF_BP] =
-{
- {
- {regi_marb_foo_bp0},
- {regi_marb_foo_bp1},
- {regi_marb_foo_bp2},
- {regi_marb_foo_bp3}
- },
- {
- {regi_marb_bar_bp0},
- {regi_marb_bar_bp1},
- {regi_marb_bar_bp2},
- {regi_marb_bar_bp3}
- }
-};
-
-struct arbiter arbiters[ARBITERS] =
-{
- { /* L2 cache arbiter */
- .instance = regi_marb_foo,
- .nbr_regions = 2,
- .nbr_clients = 15
- },
- { /* DDR2 arbiter */
- .instance = regi_marb_bar,
- .nbr_regions = 1,
- .nbr_clients = 9
- }
-};
-
-static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
-
-DEFINE_SPINLOCK(arbiter_lock);
-
-static irqreturn_t
-crisv32_foo_arbiter_irq(int irq, void *dev_id);
-static irqreturn_t
-crisv32_bar_arbiter_irq(int irq, void *dev_id);
-
-/*
- * "I'm the arbiter, I know the score.
- * From square one I'll be watching all 64."
- * (memory arbiter slots, that is)
- *
- * Or in other words:
- * Program the memory arbiter slots for "region" according to what's
- * in requested_slots[] and active_clients[], while minimizing
- * latency. A caller may pass a non-zero positive amount for
- * "unused_slots", which must then be the unallocated, remaining
- * number of slots, free to hand out to any client.
- */
-
-static void crisv32_arbiter_config(int arbiter, int region, int unused_slots)
-{
- int slot;
- int client;
- int interval = 0;
-
- /*
- * This vector corresponds to the hardware arbiter slots (see
- * the hardware documentation for semantics). We initialize
- * each slot with a suitable sentinel value outside the valid
- * range {0 .. NBR_OF_CLIENTS - 1} and replace them with
- * client indexes. Then it's fed to the hardware.
- */
- s8 val[NBR_OF_SLOTS];
-
- for (slot = 0; slot < NBR_OF_SLOTS; slot++)
- val[slot] = -1;
-
- for (client = 0; client < arbiters[arbiter].nbr_clients; client++) {
- int pos;
- /* Allocate the requested non-zero number of slots, but
- * also give clients with zero-requests one slot each
- * while stocks last. We do the latter here, in client
- * order. This makes sure zero-request clients are the
- * first to get to any spare slots, else those slots
- * could, when bandwidth is allocated close to the limit,
- * all be allocated to low-index non-zero-request clients
- * in the default-fill loop below. Another positive but
- * secondary effect is a somewhat better spread of the
- * zero-bandwidth clients in the vector, avoiding some of
- * the latency that could otherwise be caused by the
- * partitioning of non-zero-bandwidth clients at low
- * indexes and zero-bandwidth clients at high
- * indexes. (Note that this spreading can only affect the
- * unallocated bandwidth.) All the above only matters for
- * memory-intensive situations, of course.
- */
- if (!arbiters[arbiter].requested_slots[region][client]) {
- /*
- * Skip inactive clients. Also skip zero-slot
- * allocations in this pass when there are no known
- * free slots.
- */
- if (!arbiters[arbiter].active_clients[region][client] ||
- unused_slots <= 0)
- continue;
-
- unused_slots--;
-
- /* Only allocate one slot for this client. */
- interval = NBR_OF_SLOTS;
- } else
- interval = NBR_OF_SLOTS /
- arbiters[arbiter].requested_slots[region][client];
-
- pos = 0;
- while (pos < NBR_OF_SLOTS) {
- if (val[pos] >= 0)
- pos++;
- else {
- val[pos] = client;
- pos += interval;
- }
- }
- }
-
- client = 0;
- for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
- /*
- * Allocate remaining slots in round-robin
- * client-number order for active clients. For this
- * pass, we ignore requested bandwidth and previous
- * allocations.
- */
- if (val[slot] < 0) {
- int first = client;
- while (!arbiters[arbiter].active_clients[region][client]) {
- client = (client + 1) %
- arbiters[arbiter].nbr_clients;
- if (client == first)
- break;
- }
- val[slot] = client;
- client = (client + 1) % arbiters[arbiter].nbr_clients;
- }
- if (arbiter == 0) {
- if (region == EXT_REGION)
- REG_WR_INT_VECT(marb_foo, regi_marb_foo,
- rw_l2_slots, slot, val[slot]);
- else if (region == INT_REGION)
- REG_WR_INT_VECT(marb_foo, regi_marb_foo,
- rw_intm_slots, slot, val[slot]);
- } else {
- REG_WR_INT_VECT(marb_bar, regi_marb_bar,
- rw_ddr2_slots, slot, val[slot]);
- }
- }
-}
-
-extern char _stext[], _etext[];
-
-static void crisv32_arbiter_init(void)
-{
- static int initialized;
-
- if (initialized)
- return;
-
- initialized = 1;
-
- /*
- * CPU caches are always set to active, but with zero
- * bandwidth allocated. It should be ok to allocate zero
- * bandwidth for the caches, because DMA for other channels
- * will supposedly finish, once their programmed amount is
- * done, and then the caches will get access according to the
- * "fixed scheme" for unclaimed slots. Though, if for some
- * use-case somewhere, there's a maximum CPU latency for
- * e.g. some interrupt, we have to start allocating specific
- * bandwidth for the CPU caches too.
- */
- arbiters[0].active_clients[EXT_REGION][11] = 1;
- arbiters[0].active_clients[EXT_REGION][12] = 1;
- crisv32_arbiter_config(0, EXT_REGION, 0);
- crisv32_arbiter_config(0, INT_REGION, 0);
- crisv32_arbiter_config(1, EXT_REGION, 0);
-
- if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq,
- 0, "arbiter", NULL))
- printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
-
- if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq,
- 0, "arbiter", NULL))
- printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
-
-#ifndef CONFIG_ETRAX_KGDB
- /* Global watch for writes to kernel text segment. */
- crisv32_arbiter_watch(virt_to_phys(_stext), _etext - _stext,
- MARB_CLIENTS(arbiter_all_clients, arbiter_bar_all_clients),
- arbiter_all_write, NULL);
-#endif
-
- /* Set up max burst sizes by default */
- REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3);
- REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3);
-}
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth)
-{
- int i;
- int total_assigned = 0;
- int total_clients = 0;
- int req;
- int arbiter = 0;
-
- crisv32_arbiter_init();
-
- if (client & 0xffff0000) {
- arbiter = 1;
- client >>= 16;
- }
-
- for (i = 0; i < arbiters[arbiter].nbr_clients; i++) {
- total_assigned += arbiters[arbiter].requested_slots[region][i];
- total_clients += arbiters[arbiter].active_clients[region][i];
- }
-
- /* Avoid division by 0 for 0-bandwidth requests. */
- req = bandwidth == 0
- ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
-
- /*
- * We make sure that there are enough slots only for non-zero
- * requests. Requesting 0 bandwidth *may* allocate slots,
- * though if all bandwidth is allocated, such a client won't
- * get any and will have to rely on getting memory access
- * according to the fixed scheme that's the default when one
- * of the slot-allocated clients doesn't claim their slot.
- */
- if (total_assigned + req > NBR_OF_SLOTS)
- return -ENOMEM;
-
- arbiters[arbiter].active_clients[region][client] = 1;
- arbiters[arbiter].requested_slots[region][client] = req;
- crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
-
- /* Propagate allocation from foo to bar */
- if (arbiter == 0)
- crisv32_arbiter_allocate_bandwidth(8 << 16,
- EXT_REGION, bandwidth);
- return 0;
-}
-
-/*
- * Main entry for bandwidth deallocation.
- *
- * Strictly speaking, for a somewhat constant set of clients where
- * each client gets a constant bandwidth and is just enabled or
- * disabled (somewhat dynamically), no action is necessary here to
- * avoid starvation for non-zero-allocation clients, as the allocated
- * slots will just be unused. However, handing out those unused slots
- * to active clients avoids needless latency if the "fixed scheme"
- * would give unclaimed slots to an eager low-index client.
- */
-
-void crisv32_arbiter_deallocate_bandwidth(int client, int region)
-{
- int i;
- int total_assigned = 0;
- int arbiter = 0;
-
- if (client & 0xffff0000)
- arbiter = 1;
-
- arbiters[arbiter].requested_slots[region][client] = 0;
- arbiters[arbiter].active_clients[region][client] = 0;
-
- for (i = 0; i < arbiters[arbiter].nbr_clients; i++)
- total_assigned += arbiters[arbiter].requested_slots[region][i];
-
- crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
-}
-
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback *cb)
-{
- int i;
- int arbiter;
- int used[2];
- int ret = 0;
-
- crisv32_arbiter_init();
-
- if (start > 0x80000000) {
- printk(KERN_ERR "Arbiter: %lX doesn't look like a "
- "physical address", start);
- return -EFAULT;
- }
-
- spin_lock(&arbiter_lock);
-
- if (clients & 0xffff)
- used[0] = 1;
- if (clients & 0xffff0000)
- used[1] = 1;
-
- for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
- if (!used[arbiter])
- continue;
-
- for (i = 0; i < NUMBER_OF_BP; i++) {
- if (!watches[arbiter][i].used) {
- unsigned intr_mask;
- if (arbiter)
- intr_mask = REG_RD_INT(marb_bar,
- regi_marb_bar, rw_intr_mask);
- else
- intr_mask = REG_RD_INT(marb_foo,
- regi_marb_foo, rw_intr_mask);
-
- watches[arbiter][i].used = 1;
- watches[arbiter][i].start = start;
- watches[arbiter][i].end = start + size;
- watches[arbiter][i].cb = cb;
-
- ret |= (i + 1) << (arbiter + 8);
- if (arbiter) {
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_first_addr,
- watches[arbiter][i].start);
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_last_addr,
- watches[arbiter][i].end);
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_op, accesses);
- REG_WR_INT(marb_bar_bp,
- watches[arbiter][i].instance,
- rw_clients,
- clients & 0xffff);
- } else {
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_first_addr,
- watches[arbiter][i].start);
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_last_addr,
- watches[arbiter][i].end);
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_op, accesses);
- REG_WR_INT(marb_foo_bp,
- watches[arbiter][i].instance,
- rw_clients, clients >> 16);
- }
-
- if (i == 0)
- intr_mask |= 1;
- else if (i == 1)
- intr_mask |= 2;
- else if (i == 2)
- intr_mask |= 4;
- else if (i == 3)
- intr_mask |= 8;
-
- if (arbiter)
- REG_WR_INT(marb_bar, regi_marb_bar,
- rw_intr_mask, intr_mask);
- else
- REG_WR_INT(marb_foo, regi_marb_foo,
- rw_intr_mask, intr_mask);
-
- spin_unlock(&arbiter_lock);
-
- break;
- }
- }
- }
- spin_unlock(&arbiter_lock);
- if (ret)
- return ret;
- else
- return -ENOMEM;
-}
-
-int crisv32_arbiter_unwatch(int id)
-{
- int arbiter;
- int intr_mask;
-
- crisv32_arbiter_init();
-
- spin_lock(&arbiter_lock);
-
- for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
- int id2;
-
- if (arbiter)
- intr_mask = REG_RD_INT(marb_bar, regi_marb_bar,
- rw_intr_mask);
- else
- intr_mask = REG_RD_INT(marb_foo, regi_marb_foo,
- rw_intr_mask);
-
- id2 = (id & (0xff << (arbiter + 8))) >> (arbiter + 8);
- if (id2 == 0)
- continue;
- id2--;
- if ((id2 >= NUMBER_OF_BP) || (!watches[arbiter][id2].used)) {
- spin_unlock(&arbiter_lock);
- return -EINVAL;
- }
-
- memset(&watches[arbiter][id2], 0,
- sizeof(struct crisv32_watch_entry));
-
- if (id2 == 0)
- intr_mask &= ~1;
- else if (id2 == 1)
- intr_mask &= ~2;
- else if (id2 == 2)
- intr_mask &= ~4;
- else if (id2 == 3)
- intr_mask &= ~8;
-
- if (arbiter)
- REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask,
- intr_mask);
- else
- REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask,
- intr_mask);
- }
-
- spin_unlock(&arbiter_lock);
- return 0;
-}
-
-extern void show_registers(struct pt_regs *regs);
-
-
-static irqreturn_t
-crisv32_foo_arbiter_irq(int irq, void *dev_id)
-{
- reg_marb_foo_r_masked_intr masked_intr =
- REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
- reg_marb_foo_bp_r_brk_clients r_clients;
- reg_marb_foo_bp_r_brk_addr r_addr;
- reg_marb_foo_bp_r_brk_op r_op;
- reg_marb_foo_bp_r_brk_first_client r_first;
- reg_marb_foo_bp_r_brk_size r_size;
- reg_marb_foo_bp_rw_ack ack = {0};
- reg_marb_foo_rw_ack_intr ack_intr = {
- .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
- };
- struct crisv32_watch_entry *watch;
- unsigned arbiter = (unsigned)dev_id;
-
- masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
-
- if (masked_intr.bp0)
- watch = &watches[arbiter][0];
- else if (masked_intr.bp1)
- watch = &watches[arbiter][1];
- else if (masked_intr.bp2)
- watch = &watches[arbiter][2];
- else if (masked_intr.bp3)
- watch = &watches[arbiter][3];
- else
- return IRQ_NONE;
-
- /* Retrieve all useful information and print it. */
- r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients);
- r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr);
- r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op);
- r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client);
- r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size);
-
- printk(KERN_DEBUG "Arbiter IRQ\n");
- printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_clients, r_clients),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_addr, r_addr),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_op, r_op),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_first_client, r_first),
- REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_size, r_size));
-
- REG_WR(marb_foo_bp, watch->instance, rw_ack, ack);
- REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr);
-
- printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs());
-
- if (watch->cb)
- watch->cb();
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t
-crisv32_bar_arbiter_irq(int irq, void *dev_id)
-{
- reg_marb_bar_r_masked_intr masked_intr =
- REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
- reg_marb_bar_bp_r_brk_clients r_clients;
- reg_marb_bar_bp_r_brk_addr r_addr;
- reg_marb_bar_bp_r_brk_op r_op;
- reg_marb_bar_bp_r_brk_first_client r_first;
- reg_marb_bar_bp_r_brk_size r_size;
- reg_marb_bar_bp_rw_ack ack = {0};
- reg_marb_bar_rw_ack_intr ack_intr = {
- .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
- };
- struct crisv32_watch_entry *watch;
- unsigned arbiter = (unsigned)dev_id;
-
- masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
-
- if (masked_intr.bp0)
- watch = &watches[arbiter][0];
- else if (masked_intr.bp1)
- watch = &watches[arbiter][1];
- else if (masked_intr.bp2)
- watch = &watches[arbiter][2];
- else if (masked_intr.bp3)
- watch = &watches[arbiter][3];
- else
- return IRQ_NONE;
-
- /* Retrieve all useful information and print it. */
- r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients);
- r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr);
- r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op);
- r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client);
- r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size);
-
- printk(KERN_DEBUG "Arbiter IRQ\n");
- printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_clients, r_clients),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_addr, r_addr),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_op, r_op),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_first_client, r_first),
- REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_size, r_size));
-
- REG_WR(marb_bar_bp, watch->instance, rw_ack, ack);
- REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr);
-
- printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()->erp);
-
- if (watch->cb)
- watch->cb();
-
- return IRQ_HANDLED;
-}
-
diff --git a/arch/cris/arch-v32/mach-a3/dma.c b/arch/cris/arch-v32/mach-a3/dma.c
deleted file mode 100644
index 3f4e923b2527..000000000000
--- a/arch/cris/arch-v32/mach-a3/dma.c
+++ /dev/null
@@ -1,184 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Wrapper for DMA channel allocator that starts clocks etc */
-
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <mach/dma.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_defs.h>
-#include <hwregs/clkgen_defs.h>
-#include <hwregs/strmux_defs.h>
-#include <linux/errno.h>
-#include <arbiter.h>
-
-static char used_dma_channels[MAX_DMA_CHANNELS];
-static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
-
-static DEFINE_SPINLOCK(dma_lock);
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned int bandwidth, enum dma_owner owner)
-{
- unsigned long flags;
- reg_clkgen_rw_clk_ctrl clk_ctrl;
- reg_strmux_rw_cfg strmux_cfg;
-
- if (crisv32_arbiter_allocate_bandwidth(dmanr,
- options & DMA_INT_MEM ? INT_REGION : EXT_REGION,
- bandwidth))
- return -ENOMEM;
-
- spin_lock_irqsave(&dma_lock, flags);
-
- if (used_dma_channels[dmanr]) {
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR)
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "already allocated by %s\n",
- dmanr,
- device_id,
- used_dma_channels_users[dmanr]);
-
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EBUSY;
- }
- clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
- strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
-
- switch (dmanr) {
- case 0:
- case 1:
- clk_ctrl.dma0_1_eth = 1;
- break;
- case 2:
- case 3:
- clk_ctrl.dma2_3_strcop = 1;
- break;
- case 4:
- case 5:
- clk_ctrl.dma4_5_iop = 1;
- break;
- case 6:
- case 7:
- clk_ctrl.sser_ser_dma6_7 = 1;
- break;
- case 9:
- case 11:
- clk_ctrl.dma9_11 = 1;
- break;
-#if MAX_DMA_CHANNELS-1 != 11
-#error Check dma.c
-#endif
- default:
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR)
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "only 0-%i valid)\n",
- dmanr, device_id, MAX_DMA_CHANNELS-1);
-
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EINVAL;
- }
-
- switch (owner) {
- case dma_eth:
- if (dmanr == 0)
- strmux_cfg.dma0 = regk_strmux_eth;
- else if (dmanr == 1)
- strmux_cfg.dma1 = regk_strmux_eth;
- else
- panic("Invalid DMA channel for eth\n");
- break;
- case dma_ser0:
- if (dmanr == 0)
- strmux_cfg.dma0 = regk_strmux_ser0;
- else if (dmanr == 1)
- strmux_cfg.dma1 = regk_strmux_ser0;
- else
- panic("Invalid DMA channel for ser0\n");
- break;
- case dma_ser3:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ser3;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ser3;
- else
- panic("Invalid DMA channel for ser3\n");
- break;
- case dma_strp:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_strcop;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_strcop;
- else
- panic("Invalid DMA channel for strp\n");
- break;
- case dma_ser1:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_ser1;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_ser1;
- else
- panic("Invalid DMA channel for ser1\n");
- break;
- case dma_iop:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_iop;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_iop;
- else
- panic("Invalid DMA channel for iop\n");
- break;
- case dma_ser2:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_ser2;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_ser2;
- else
- panic("Invalid DMA channel for ser2\n");
- break;
- case dma_sser:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_sser;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_sser;
- else
- panic("Invalid DMA channel for sser\n");
- break;
- case dma_ser4:
- if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_ser4;
- else
- panic("Invalid DMA channel for ser4\n");
- break;
- case dma_jpeg:
- if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_jpeg;
- else
- panic("Invalid DMA channel for JPEG\n");
- break;
- case dma_h264:
- if (dmanr == 11)
- strmux_cfg.dma11 = regk_strmux_h264;
- else
- panic("Invalid DMA channel for H264\n");
- break;
- }
-
- used_dma_channels[dmanr] = 1;
- used_dma_channels_users[dmanr] = device_id;
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
- REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
- spin_unlock_irqrestore(&dma_lock, flags);
- return 0;
-}
-
-void crisv32_free_dma(unsigned int dmanr)
-{
- spin_lock(&dma_lock);
- used_dma_channels[dmanr] = 0;
- spin_unlock(&dma_lock);
-}
diff --git a/arch/cris/arch-v32/mach-a3/dram_init.S b/arch/cris/arch-v32/mach-a3/dram_init.S
deleted file mode 100644
index 733c3564ad79..000000000000
--- a/arch/cris/arch-v32/mach-a3/dram_init.S
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DDR SDRAM initialization - alter with care
- * This file is intended to be included from other assembler files
- *
- * Note: This file may not modify r8 or r9 because they are used to
- * carry information from the decompressor to the kernel
- *
- * Copyright (C) 2005-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-/* Just to be certain the config file is included, we include it here
- * explicitly instead of depending on it being included in the file that
- * uses this code.
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/ddr2_defs_asm.h>
-
- ;; WARNING! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below.
-
- ;; Refer to ddr2 MDS for initialization sequence
-
- ; 2. Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Start clock
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
- move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
- move.d $r1, [$r0]
-
- ; 2. Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Reset phy and start calibration
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
- move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
- REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
- move.d $r1, [$r0]
- move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
- move.d $r1, [$r0]
-
- ; 2. Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Issue commands
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
- move.d sdram_commands_start, $r2
-command_loop:
- movu.b [$r2+], $r1
- movu.w [$r2+], $r3
-do_cmd:
- lslq 16, $r1
- or.d $r3, $r1
- move.d $r1, [$r0]
- ; 2. Wait 200us
- move.d 10000, $r4
-1: bne 1b
- subq 1, $r4
- cmp.d sdram_commands_end, $r2
- blo command_loop
- nop
-
- ; Set timing
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
- move.d CONFIG_ETRAX_DDR2_TIMING, $r1
- move.d $r1, [$r0]
-
- ; Set latency
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
- move.d CONFIG_ETRAX_DDR2_LATENCY, $r1
- move.d $r1, [$r0]
-
- ; Set configuration
- move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
- move.d CONFIG_ETRAX_DDR2_CONFIG, $r1
- move.d $r1, [$r0]
-
- ba after_sdram_commands
- nop
-
-sdram_commands_start:
- .byte regk_ddr2_deselect
- .word 0
- .byte regk_ddr2_pre
- .word regk_ddr2_pre_all
- .byte regk_ddr2_emrs2
- .word 0
- .byte regk_ddr2_emrs3
- .word 0
- .byte regk_ddr2_emrs
- .word regk_ddr2_dll_en
- .byte regk_ddr2_mrs
- .word regk_ddr2_dll_rst
- .byte regk_ddr2_pre
- .word regk_ddr2_pre_all
- .byte regk_ddr2_ref
- .word 0
- .byte regk_ddr2_ref
- .word 0
- .byte regk_ddr2_mrs
- .word CONFIG_ETRAX_DDR2_MRS & 0xffff
- .byte regk_ddr2_emrs
- .word regk_ddr2_ocd_default | regk_ddr2_dll_en
- .byte regk_ddr2_emrs
- .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16)
-sdram_commands_end:
- .align 1
-after_sdram_commands:
diff --git a/arch/cris/arch-v32/mach-a3/hw_settings.S b/arch/cris/arch-v32/mach-a3/hw_settings.S
deleted file mode 100644
index 7c325cc59e1f..000000000000
--- a/arch/cris/arch-v32/mach-a3/hw_settings.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This table is used by some tools to extract hardware parameters.
- * The table should be included in the kernel and the decompressor.
- * Don't forget to update the tools if you change this table.
- *
- * Copyright (C) 2001-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/ddr2_defs_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-
- .ascii "HW_PARAM_MAGIC" ; Magic number
- .dword 0xc0004000 ; Kernel start address
-
- ; Debug port
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- .dword 0
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- .dword 1
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- .dword 2
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- .dword 3
-#else
- .dword 4 ; No debug
-#endif
-
- ; Register values
- .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)
- .dword CONFIG_ETRAX_DDR2_CONFIG
- .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency)
- .dword CONFIG_ETRAX_DDR2_LATENCY
- .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)
- .dword CONFIG_ETRAX_DDR2_TIMING
- .dword CONFIG_ETRAX_DDR2_MRS
-
- .dword REG_ADDR(gio, regi_gio, rw_pa_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pa_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OE
- .dword REG_ADDR(gio, regi_gio, rw_pb_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pb_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OE
- .dword REG_ADDR(gio, regi_gio, rw_pc_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pc_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OE
-
- .dword 0 ; No more register values
diff --git a/arch/cris/arch-v32/mach-a3/pinmux.c b/arch/cris/arch-v32/mach-a3/pinmux.c
deleted file mode 100644
index 4875bf7aa53f..000000000000
--- a/arch/cris/arch-v32/mach-a3/pinmux.c
+++ /dev/null
@@ -1,389 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
- * Unassigned pins and GPIO pins can be allocated to a fixed interface
- * or the I/O processor instead.
- *
- * Copyright (c) 2005-2007 Axis Communications AB.
- */
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <pinmux.h>
-#include <hwregs/pinmux_defs.h>
-#include <hwregs/clkgen_defs.h>
-
-#undef DEBUG
-
-#define PINS 80
-#define PORT_PINS 32
-#define PORTS 3
-
-static char pins[PINS];
-static DEFINE_SPINLOCK(pinmux_lock);
-
-static void crisv32_pinmux_set(int port);
-
-int
-crisv32_pinmux_init(void)
-{
- static int initialized;
-
- if (!initialized) {
- initialized = 1;
- REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
- crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio);
- crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio);
- crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio);
- }
-
- return 0;
-}
-
-int
-crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
-{
- int i;
- unsigned long flags;
-
- crisv32_pinmux_init();
-
- if (port >= PORTS)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- for (i = first_pin; i <= last_pin; i++) {
- if ((pins[port * PORT_PINS + i] != pinmux_none) &&
- (pins[port * PORT_PINS + i] != pinmux_gpio) &&
- (pins[port * PORT_PINS + i] != mode)) {
- spin_unlock_irqrestore(&pinmux_lock, flags);
-#ifdef DEBUG
- panic("Pinmux alloc failed!\n");
-#endif
- return -EPERM;
- }
- }
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port * PORT_PINS + i] = mode;
-
- crisv32_pinmux_set(port);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return 0;
-}
-
-int
-crisv32_pinmux_alloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
- reg_clkgen_rw_clk_ctrl clk_ctrl;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
- clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
-
- switch (function) {
- case pinmux_eth:
- clk_ctrl.eth = regk_clkgen_yes;
- clk_ctrl.dma0_1_eth = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed);
- hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes;
- break;
- case pinmux_geth:
- ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed);
- hwprot.geth = regk_pinmux_yes;
- break;
- case pinmux_tg_cmos:
- clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed);
- hwprot.tg_clk = regk_pinmux_yes;
- break;
- case pinmux_tg_ccd:
- clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed);
- hwprot.tg = hwprot.tg_clk = regk_pinmux_yes;
- break;
- case pinmux_vout:
- clk_ctrl.strdma0_2_video = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed);
- hwprot.vout = hwprot.vout_sync = regk_pinmux_yes;
- break;
- case pinmux_ser1:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed);
- hwprot.ser1 = regk_pinmux_yes;
- break;
- case pinmux_ser2:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed);
- hwprot.ser2 = regk_pinmux_yes;
- break;
- case pinmux_ser3:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed);
- hwprot.ser3 = regk_pinmux_yes;
- break;
- case pinmux_ser4:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed);
- hwprot.ser4 = regk_pinmux_yes;
- break;
- case pinmux_sser:
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed);
- hwprot.sser = regk_pinmux_yes;
- break;
- case pinmux_pio:
- hwprot.pio = regk_pinmux_yes;
- ret = 0;
- break;
- case pinmux_pwm0:
- ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed);
- hwprot.pwm0 = regk_pinmux_yes;
- break;
- case pinmux_pwm1:
- ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed);
- hwprot.pwm1 = regk_pinmux_yes;
- break;
- case pinmux_pwm2:
- ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed);
- hwprot.pwm2 = regk_pinmux_yes;
- break;
- case pinmux_i2c0:
- ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed);
- hwprot.i2c0 = regk_pinmux_yes;
- break;
- case pinmux_i2c1:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- hwprot.i2c1 = regk_pinmux_yes;
- break;
- case pinmux_i2c1_3wire:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes;
- break;
- case pinmux_i2c1_sda1:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes;
- break;
- case pinmux_i2c1_sda2:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes;
- break;
- case pinmux_i2c1_sda3:
- ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
- ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed);
- hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- if (!ret) {
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
- } else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-void
-crisv32_pinmux_set(int port)
-{
- int i;
- int gpio_val = 0;
- int iop_val = 0;
- int pin = port * PORT_PINS;
-
- for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) {
- if (pins[pin] == pinmux_gpio)
- gpio_val |= (1 << i);
- else if (pins[pin] == pinmux_iop)
- iop_val |= (1 << i);
- }
-
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port,
- gpio_val);
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port,
- iop_val);
-
-#ifdef DEBUG
- crisv32_pinmux_dump();
-#endif
-}
-
-int
-crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
-{
- int i;
- unsigned long flags;
-
- crisv32_pinmux_init();
-
- if (port > PORTS || port < 0)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port * PORT_PINS + i] = pinmux_none;
-
- crisv32_pinmux_set(port);
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return 0;
-}
-
-int
-crisv32_pinmux_dealloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-
- switch (function) {
- case pinmux_eth:
- ret = crisv32_pinmux_dealloc(PORT_B, 8, 23);
- ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25);
- ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7);
- hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no;
- break;
- case pinmux_tg_cmos:
- ret = crisv32_pinmux_dealloc(PORT_B, 27, 29);
- hwprot.tg_clk = regk_pinmux_no;
- break;
- case pinmux_tg_ccd:
- ret = crisv32_pinmux_dealloc(PORT_B, 27, 31);
- ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15);
- hwprot.tg = hwprot.tg_clk = regk_pinmux_no;
- break;
- case pinmux_vout:
- ret = crisv32_pinmux_dealloc(PORT_A, 8, 18);
- hwprot.vout = hwprot.vout_sync = regk_pinmux_no;
- break;
- case pinmux_ser1:
- ret = crisv32_pinmux_dealloc(PORT_A, 24, 25);
- hwprot.ser1 = regk_pinmux_no;
- break;
- case pinmux_ser2:
- ret = crisv32_pinmux_dealloc(PORT_A, 26, 27);
- hwprot.ser2 = regk_pinmux_no;
- break;
- case pinmux_ser3:
- ret = crisv32_pinmux_dealloc(PORT_A, 28, 29);
- hwprot.ser3 = regk_pinmux_no;
- break;
- case pinmux_ser4:
- ret = crisv32_pinmux_dealloc(PORT_A, 30, 31);
- hwprot.ser4 = regk_pinmux_no;
- break;
- case pinmux_sser:
- ret = crisv32_pinmux_dealloc(PORT_A, 19, 23);
- hwprot.sser = regk_pinmux_no;
- break;
- case pinmux_pwm0:
- ret = crisv32_pinmux_dealloc(PORT_A, 30, 30);
- hwprot.pwm0 = regk_pinmux_no;
- break;
- case pinmux_pwm1:
- ret = crisv32_pinmux_dealloc(PORT_A, 31, 31);
- hwprot.pwm1 = regk_pinmux_no;
- break;
- case pinmux_pwm2:
- ret = crisv32_pinmux_dealloc(PORT_B, 26, 26);
- hwprot.pwm2 = regk_pinmux_no;
- break;
- case pinmux_i2c0:
- ret = crisv32_pinmux_dealloc(PORT_A, 0, 1);
- hwprot.i2c0 = regk_pinmux_no;
- break;
- case pinmux_i2c1:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- hwprot.i2c1 = regk_pinmux_no;
- break;
- case pinmux_i2c1_3wire:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7);
- hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no;
- break;
- case pinmux_i2c1_sda1:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 4);
- hwprot.i2c1_sda1 = regk_pinmux_no;
- break;
- case pinmux_i2c1_sda2:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5);
- hwprot.i2c1_sda2 = regk_pinmux_no;
- break;
- case pinmux_i2c1_sda3:
- ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
- ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6);
- hwprot.i2c1_sda3 = regk_pinmux_no;
- break;
- default:
- ret = -EINVAL;
- break;
- }
-
- if (!ret)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-void
-crisv32_pinmux_dump(void)
-{
- int i, j;
- int pin = 0;
-
- crisv32_pinmux_init();
-
- for (i = 0; i < PORTS; i++) {
- pin++;
- printk(KERN_DEBUG "Port %c\n", 'A'+i);
- for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++)
- printk(KERN_DEBUG
- " Pin %d = %d\n", j, pins[i * PORT_PINS + j]);
- }
-}
-
-__initcall(crisv32_pinmux_init);
diff --git a/arch/cris/arch-v32/mach-fs/Kconfig b/arch/cris/arch-v32/mach-fs/Kconfig
deleted file mode 100644
index 743ba3bcbaec..000000000000
--- a/arch/cris/arch-v32/mach-fs/Kconfig
+++ /dev/null
@@ -1,198 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-if ETRAXFS
-
-menu "ETRAX FS options"
- depends on ETRAXFS
-
-config ETRAX_DRAM_VIRTUAL_BASE
- hex
- depends on ETRAX_ARCH_V32
- default "c0000000"
-
-config ETRAX_SERIAL_PORTS
- int
- default 4
-
-config ETRAX_MEM_GRP1_CONFIG
- hex "MEM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "4044a"
- help
- Waitstates for flash. The default value is suitable for the
- standard flashes used in axis products (120 ns).
-
-config ETRAX_MEM_GRP2_CONFIG
- hex "MEM_GRP2_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for SRAM. 0 is a good choice for most Axis products.
-
-config ETRAX_MEM_GRP3_CONFIG
- hex "MEM_GRP3_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP0-3. 0 is a good choice for most Axis products.
- It may need to be changed if external devices such as extra
- register-mapped LEDs are used.
-
-config ETRAX_MEM_GRP4_CONFIG
- hex "MEM_GRP4_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- Waitstates for CSP4-6. 0 is a good choice for most Axis products.
-
-config ETRAX_SDRAM_GRP0_CONFIG
- hex "SDRAM_GRP0_CONFIG"
- depends on ETRAX_ARCH_V32
- default "336"
- help
- SDRAM configuration for group 0. The value depends on the
- hardware configuration. The default value is suitable
- for 32 MB organized as two 16 bits chips (e.g. Axis
- part number 18550) connected as one 32 bit device (i.e. in
- the same group).
-
-config ETRAX_SDRAM_GRP1_CONFIG
- hex "SDRAM_GRP1_CONFIG"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM configuration for group 1. The default value is 0
- because group 1 is not used in the default configuration,
- described in the help for SDRAM_GRP0_CONFIG.
-
-config ETRAX_SDRAM_TIMING
- hex "SDRAM_TIMING"
- depends on ETRAX_ARCH_V32
- default "104a"
- help
- SDRAM timing parameters. The default value is ok for
- most hardwares but large SDRAMs may require a faster
- refresh (a.k.a 8K refresh). The default value implies
- 100MHz clock and SDR mode.
-
-config ETRAX_SDRAM_COMMAND
- hex "SDRAM_COMMAND"
- depends on ETRAX_ARCH_V32
- default "0"
- help
- SDRAM command. Should be 0 unless you really know what
- you are doing (may be != 0 for unusual address line
- mappings such as in a MCM)..
-
-config ETRAX_DEF_GIO_PA_OE
- hex "GIO_PA_OE"
- depends on ETRAX_ARCH_V32
- default "1c"
- help
- Configures the direction of general port A bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PA_OUT
- hex "GIO_PA_OUT"
- depends on ETRAX_ARCH_V32
- default "00"
- help
- Configures the initial data for the general port A bits. Most
- products should use 00 here.
-
-config ETRAX_DEF_GIO_PB_OE
- hex "GIO_PB_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port B bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PB_OUT
- hex "GIO_PB_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port B bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PC_OE
- hex "GIO_PC_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port C bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PC_OUT
- hex "GIO_PC_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port C bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PD_OE
- hex "GIO_PD_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port D bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PD_OUT
- hex "GIO_PD_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port D bits. Most
- products should use 00000 here.
-
-config ETRAX_DEF_GIO_PE_OE
- hex "GIO_PE_OE"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the direction of general port E bits. 1 is out, 0 is in.
- This is often totally different depending on the product used.
- There are some guidelines though - if you know that only LED's are
- connected to port PA, then they are usually connected to bits 2-4
- and you can therefore use 1c. On other boards which don't have the
- LED's at the general ports, these bits are used for all kinds of
- stuff. If you don't know what to use, it is always safe to put all
- as inputs, although floating inputs isn't good.
-
-config ETRAX_DEF_GIO_PE_OUT
- hex "GIO_PE_OUT"
- depends on ETRAX_ARCH_V32
- default "00000"
- help
- Configures the initial data for the general port E bits. Most
- products should use 00000 here.
-
-endmenu
-
-endif
diff --git a/arch/cris/arch-v32/mach-fs/Makefile b/arch/cris/arch-v32/mach-fs/Makefile
deleted file mode 100644
index 0cc6eebacbed..000000000000
--- a/arch/cris/arch-v32/mach-fs/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := dma.o pinmux.o arbiter.o
-
-clean:
-
diff --git a/arch/cris/arch-v32/mach-fs/arbiter.c b/arch/cris/arch-v32/mach-fs/arbiter.c
deleted file mode 100644
index c4750d97e46c..000000000000
--- a/arch/cris/arch-v32/mach-fs/arbiter.c
+++ /dev/null
@@ -1,405 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Memory arbiter functions. Allocates bandwidth through the
- * arbiter and sets up arbiter breakpoints.
- *
- * The algorithm first assigns slots to the clients that has specified
- * bandwidth (e.g. ethernet) and then the remaining slots are divided
- * on all the active clients.
- *
- * Copyright (c) 2004-2007 Axis Communications AB.
- */
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_defs.h>
-#include <arbiter.h>
-#include <hwregs/intr_vect.h>
-#include <linux/interrupt.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <asm/io.h>
-#include <asm/irq_regs.h>
-
-struct crisv32_watch_entry {
- unsigned long instance;
- watch_callback *cb;
- unsigned long start;
- unsigned long end;
- int used;
-};
-
-#define NUMBER_OF_BP 4
-#define NBR_OF_CLIENTS 14
-#define NBR_OF_SLOTS 64
-#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */
-#define INTMEM_BANDWIDTH 400000000
-#define NBR_OF_REGIONS 2
-
-static struct crisv32_watch_entry watches[NUMBER_OF_BP] = {
- {regi_marb_bp0},
- {regi_marb_bp1},
- {regi_marb_bp2},
- {regi_marb_bp3}
-};
-
-static u8 requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-static u8 active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-static int max_bandwidth[NBR_OF_REGIONS] =
- { SDRAM_BANDWIDTH, INTMEM_BANDWIDTH };
-
-DEFINE_SPINLOCK(arbiter_lock);
-
-static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id);
-
-/*
- * "I'm the arbiter, I know the score.
- * From square one I'll be watching all 64."
- * (memory arbiter slots, that is)
- *
- * Or in other words:
- * Program the memory arbiter slots for "region" according to what's
- * in requested_slots[] and active_clients[], while minimizing
- * latency. A caller may pass a non-zero positive amount for
- * "unused_slots", which must then be the unallocated, remaining
- * number of slots, free to hand out to any client.
- */
-
-static void crisv32_arbiter_config(int region, int unused_slots)
-{
- int slot;
- int client;
- int interval = 0;
-
- /*
- * This vector corresponds to the hardware arbiter slots (see
- * the hardware documentation for semantics). We initialize
- * each slot with a suitable sentinel value outside the valid
- * range {0 .. NBR_OF_CLIENTS - 1} and replace them with
- * client indexes. Then it's fed to the hardware.
- */
- s8 val[NBR_OF_SLOTS];
-
- for (slot = 0; slot < NBR_OF_SLOTS; slot++)
- val[slot] = -1;
-
- for (client = 0; client < NBR_OF_CLIENTS; client++) {
- int pos;
- /* Allocate the requested non-zero number of slots, but
- * also give clients with zero-requests one slot each
- * while stocks last. We do the latter here, in client
- * order. This makes sure zero-request clients are the
- * first to get to any spare slots, else those slots
- * could, when bandwidth is allocated close to the limit,
- * all be allocated to low-index non-zero-request clients
- * in the default-fill loop below. Another positive but
- * secondary effect is a somewhat better spread of the
- * zero-bandwidth clients in the vector, avoiding some of
- * the latency that could otherwise be caused by the
- * partitioning of non-zero-bandwidth clients at low
- * indexes and zero-bandwidth clients at high
- * indexes. (Note that this spreading can only affect the
- * unallocated bandwidth.) All the above only matters for
- * memory-intensive situations, of course.
- */
- if (!requested_slots[region][client]) {
- /*
- * Skip inactive clients. Also skip zero-slot
- * allocations in this pass when there are no known
- * free slots.
- */
- if (!active_clients[region][client]
- || unused_slots <= 0)
- continue;
-
- unused_slots--;
-
- /* Only allocate one slot for this client. */
- interval = NBR_OF_SLOTS;
- } else
- interval =
- NBR_OF_SLOTS / requested_slots[region][client];
-
- pos = 0;
- while (pos < NBR_OF_SLOTS) {
- if (val[pos] >= 0)
- pos++;
- else {
- val[pos] = client;
- pos += interval;
- }
- }
- }
-
- client = 0;
- for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
- /*
- * Allocate remaining slots in round-robin
- * client-number order for active clients. For this
- * pass, we ignore requested bandwidth and previous
- * allocations.
- */
- if (val[slot] < 0) {
- int first = client;
- while (!active_clients[region][client]) {
- client = (client + 1) % NBR_OF_CLIENTS;
- if (client == first)
- break;
- }
- val[slot] = client;
- client = (client + 1) % NBR_OF_CLIENTS;
- }
- if (region == EXT_REGION)
- REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot,
- val[slot]);
- else if (region == INT_REGION)
- REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot,
- val[slot]);
- }
-}
-
-extern char _stext[], _etext[];
-
-static void crisv32_arbiter_init(void)
-{
- static int initialized;
-
- if (initialized)
- return;
-
- initialized = 1;
-
- /*
- * CPU caches are always set to active, but with zero
- * bandwidth allocated. It should be ok to allocate zero
- * bandwidth for the caches, because DMA for other channels
- * will supposedly finish, once their programmed amount is
- * done, and then the caches will get access according to the
- * "fixed scheme" for unclaimed slots. Though, if for some
- * use-case somewhere, there's a maximum CPU latency for
- * e.g. some interrupt, we have to start allocating specific
- * bandwidth for the CPU caches too.
- */
- active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1;
- crisv32_arbiter_config(EXT_REGION, 0);
- crisv32_arbiter_config(INT_REGION, 0);
-
- if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, 0,
- "arbiter", NULL))
- printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
-
-#ifndef CONFIG_ETRAX_KGDB
- /* Global watch for writes to kernel text segment. */
- crisv32_arbiter_watch(virt_to_phys(_stext), _etext - _stext,
- arbiter_all_clients, arbiter_all_write, NULL);
-#endif
-}
-
-/* Main entry for bandwidth allocation. */
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth)
-{
- int i;
- int total_assigned = 0;
- int total_clients = 0;
- int req;
-
- crisv32_arbiter_init();
-
- for (i = 0; i < NBR_OF_CLIENTS; i++) {
- total_assigned += requested_slots[region][i];
- total_clients += active_clients[region][i];
- }
-
- /* Avoid division by 0 for 0-bandwidth requests. */
- req = bandwidth == 0
- ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
-
- /*
- * We make sure that there are enough slots only for non-zero
- * requests. Requesting 0 bandwidth *may* allocate slots,
- * though if all bandwidth is allocated, such a client won't
- * get any and will have to rely on getting memory access
- * according to the fixed scheme that's the default when one
- * of the slot-allocated clients doesn't claim their slot.
- */
- if (total_assigned + req > NBR_OF_SLOTS)
- return -ENOMEM;
-
- active_clients[region][client] = 1;
- requested_slots[region][client] = req;
- crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned);
-
- return 0;
-}
-
-/*
- * Main entry for bandwidth deallocation.
- *
- * Strictly speaking, for a somewhat constant set of clients where
- * each client gets a constant bandwidth and is just enabled or
- * disabled (somewhat dynamically), no action is necessary here to
- * avoid starvation for non-zero-allocation clients, as the allocated
- * slots will just be unused. However, handing out those unused slots
- * to active clients avoids needless latency if the "fixed scheme"
- * would give unclaimed slots to an eager low-index client.
- */
-
-void crisv32_arbiter_deallocate_bandwidth(int client, int region)
-{
- int i;
- int total_assigned = 0;
-
- requested_slots[region][client] = 0;
- active_clients[region][client] = 0;
-
- for (i = 0; i < NBR_OF_CLIENTS; i++)
- total_assigned += requested_slots[region][i];
-
- crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned);
-}
-
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback *cb)
-{
- int i;
-
- crisv32_arbiter_init();
-
- if (start > 0x80000000) {
- printk(KERN_ERR "Arbiter: %lX doesn't look like a "
- "physical address", start);
- return -EFAULT;
- }
-
- spin_lock(&arbiter_lock);
-
- for (i = 0; i < NUMBER_OF_BP; i++) {
- if (!watches[i].used) {
- reg_marb_rw_intr_mask intr_mask =
- REG_RD(marb, regi_marb, rw_intr_mask);
-
- watches[i].used = 1;
- watches[i].start = start;
- watches[i].end = start + size;
- watches[i].cb = cb;
-
- REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr,
- watches[i].start);
- REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr,
- watches[i].end);
- REG_WR_INT(marb_bp, watches[i].instance, rw_op,
- accesses);
- REG_WR_INT(marb_bp, watches[i].instance, rw_clients,
- clients);
-
- if (i == 0)
- intr_mask.bp0 = regk_marb_yes;
- else if (i == 1)
- intr_mask.bp1 = regk_marb_yes;
- else if (i == 2)
- intr_mask.bp2 = regk_marb_yes;
- else if (i == 3)
- intr_mask.bp3 = regk_marb_yes;
-
- REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
- spin_unlock(&arbiter_lock);
-
- return i;
- }
- }
- spin_unlock(&arbiter_lock);
- return -ENOMEM;
-}
-
-int crisv32_arbiter_unwatch(int id)
-{
- reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
-
- crisv32_arbiter_init();
-
- spin_lock(&arbiter_lock);
-
- if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) {
- spin_unlock(&arbiter_lock);
- return -EINVAL;
- }
-
- memset(&watches[id], 0, sizeof(struct crisv32_watch_entry));
-
- if (id == 0)
- intr_mask.bp0 = regk_marb_no;
- else if (id == 1)
- intr_mask.bp1 = regk_marb_no;
- else if (id == 2)
- intr_mask.bp2 = regk_marb_no;
- else if (id == 3)
- intr_mask.bp3 = regk_marb_no;
-
- REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
-
- spin_unlock(&arbiter_lock);
- return 0;
-}
-
-extern void show_registers(struct pt_regs *regs);
-
-static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id)
-{
- reg_marb_r_masked_intr masked_intr =
- REG_RD(marb, regi_marb, r_masked_intr);
- reg_marb_bp_r_brk_clients r_clients;
- reg_marb_bp_r_brk_addr r_addr;
- reg_marb_bp_r_brk_op r_op;
- reg_marb_bp_r_brk_first_client r_first;
- reg_marb_bp_r_brk_size r_size;
- reg_marb_bp_rw_ack ack = { 0 };
- reg_marb_rw_ack_intr ack_intr = {
- .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
- };
- struct crisv32_watch_entry *watch;
-
- if (masked_intr.bp0) {
- watch = &watches[0];
- ack_intr.bp0 = regk_marb_yes;
- } else if (masked_intr.bp1) {
- watch = &watches[1];
- ack_intr.bp1 = regk_marb_yes;
- } else if (masked_intr.bp2) {
- watch = &watches[2];
- ack_intr.bp2 = regk_marb_yes;
- } else if (masked_intr.bp3) {
- watch = &watches[3];
- ack_intr.bp3 = regk_marb_yes;
- } else {
- return IRQ_NONE;
- }
-
- /* Retrieve all useful information and print it. */
- r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients);
- r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr);
- r_op = REG_RD(marb_bp, watch->instance, r_brk_op);
- r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client);
- r_size = REG_RD(marb_bp, watch->instance, r_brk_size);
-
- printk(KERN_INFO "Arbiter IRQ\n");
- printk(KERN_INFO "Clients %X addr %X op %X first %X size %X\n",
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size));
-
- REG_WR(marb_bp, watch->instance, rw_ack, ack);
- REG_WR(marb, regi_marb, rw_ack_intr, ack_intr);
-
- printk(KERN_INFO "IRQ occurred at %lX\n", get_irq_regs()->erp);
-
- if (watch->cb)
- watch->cb();
-
- return IRQ_HANDLED;
-}
diff --git a/arch/cris/arch-v32/mach-fs/dma.c b/arch/cris/arch-v32/mach-fs/dma.c
deleted file mode 100644
index c0347a4f8c65..000000000000
--- a/arch/cris/arch-v32/mach-fs/dma.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* Wrapper for DMA channel allocator that starts clocks etc */
-
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <asm/dma.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/marb_defs.h>
-#include <hwregs/config_defs.h>
-#include <hwregs/strmux_defs.h>
-#include <linux/errno.h>
-#include <mach/arbiter.h>
-
-static char used_dma_channels[MAX_DMA_CHANNELS];
-static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
-
-static DEFINE_SPINLOCK(dma_lock);
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned int bandwidth,
- enum dma_owner owner)
-{
- unsigned long flags;
- reg_config_rw_clk_ctrl clk_ctrl;
- reg_strmux_rw_cfg strmux_cfg;
-
- if (crisv32_arbiter_allocate_bandwidth(dmanr,
- options & DMA_INT_MEM ?
- INT_REGION : EXT_REGION,
- bandwidth))
- return -ENOMEM;
-
- spin_lock_irqsave(&dma_lock, flags);
-
- if (used_dma_channels[dmanr]) {
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR) {
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "already allocated by %s\n",
- dmanr,
- device_id,
- used_dma_channels_users[dmanr]);
- }
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EBUSY;
- }
- clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
- strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
-
- switch (dmanr) {
- case 0:
- case 1:
- clk_ctrl.dma01_eth0 = 1;
- break;
- case 2:
- case 3:
- clk_ctrl.dma23 = 1;
- break;
- case 4:
- case 5:
- clk_ctrl.dma45 = 1;
- break;
- case 6:
- case 7:
- clk_ctrl.dma67 = 1;
- break;
- case 8:
- case 9:
- clk_ctrl.dma89_strcop = 1;
- break;
-#if MAX_DMA_CHANNELS-1 != 9
-#error Check dma.c
-#endif
- default:
- spin_unlock_irqrestore(&dma_lock, flags);
- if (options & DMA_VERBOSE_ON_ERROR) {
- printk(KERN_ERR "Failed to request DMA %i for %s, "
- "only 0-%i valid)\n",
- dmanr, device_id, MAX_DMA_CHANNELS - 1);
- }
-
- if (options & DMA_PANIC_ON_ERROR)
- panic("request_dma error!");
- return -EINVAL;
- }
-
- switch (owner) {
- case dma_eth0:
- if (dmanr == 0)
- strmux_cfg.dma0 = regk_strmux_eth0;
- else if (dmanr == 1)
- strmux_cfg.dma1 = regk_strmux_eth0;
- else
- panic("Invalid DMA channel for eth0\n");
- break;
- case dma_eth1:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_eth1;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_eth1;
- else
- panic("Invalid DMA channel for eth1\n");
- break;
- case dma_iop0:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_iop0;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_iop0;
- else
- panic("Invalid DMA channel for iop0\n");
- break;
- case dma_iop1:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_iop1;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_iop1;
- else
- panic("Invalid DMA channel for iop1\n");
- break;
- case dma_ser0:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_ser0;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_ser0;
- else
- panic("Invalid DMA channel for ser0\n");
- break;
- case dma_ser1:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_ser1;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_ser1;
- else
- panic("Invalid DMA channel for ser1\n");
- break;
- case dma_ser2:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ser2;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ser2;
- else
- panic("Invalid DMA channel for ser2\n");
- break;
- case dma_ser3:
- if (dmanr == 8)
- strmux_cfg.dma8 = regk_strmux_ser3;
- else if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_ser3;
- else
- panic("Invalid DMA channel for ser3\n");
- break;
- case dma_sser0:
- if (dmanr == 4)
- strmux_cfg.dma4 = regk_strmux_sser0;
- else if (dmanr == 5)
- strmux_cfg.dma5 = regk_strmux_sser0;
- else
- panic("Invalid DMA channel for sser0\n");
- break;
- case dma_sser1:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_sser1;
- else if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_sser1;
- else
- panic("Invalid DMA channel for sser1\n");
- break;
- case dma_ata:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ata;
- else if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ata;
- else
- panic("Invalid DMA channel for ata\n");
- break;
- case dma_strp:
- if (dmanr == 8)
- strmux_cfg.dma8 = regk_strmux_strcop;
- else if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_strcop;
- else
- panic("Invalid DMA channel for strp\n");
- break;
- case dma_ext0:
- if (dmanr == 6)
- strmux_cfg.dma6 = regk_strmux_ext0;
- else
- panic("Invalid DMA channel for ext0\n");
- break;
- case dma_ext1:
- if (dmanr == 7)
- strmux_cfg.dma7 = regk_strmux_ext1;
- else
- panic("Invalid DMA channel for ext1\n");
- break;
- case dma_ext2:
- if (dmanr == 2)
- strmux_cfg.dma2 = regk_strmux_ext2;
- else if (dmanr == 8)
- strmux_cfg.dma8 = regk_strmux_ext2;
- else
- panic("Invalid DMA channel for ext2\n");
- break;
- case dma_ext3:
- if (dmanr == 3)
- strmux_cfg.dma3 = regk_strmux_ext3;
- else if (dmanr == 9)
- strmux_cfg.dma9 = regk_strmux_ext2;
- else
- panic("Invalid DMA channel for ext2\n");
- break;
- }
-
- used_dma_channels[dmanr] = 1;
- used_dma_channels_users[dmanr] = device_id;
- REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
- REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
- spin_unlock_irqrestore(&dma_lock, flags);
- return 0;
-}
-
-void crisv32_free_dma(unsigned int dmanr)
-{
- spin_lock(&dma_lock);
- used_dma_channels[dmanr] = 0;
- spin_unlock(&dma_lock);
-}
diff --git a/arch/cris/arch-v32/mach-fs/dram_init.S b/arch/cris/arch-v32/mach-fs/dram_init.S
deleted file mode 100644
index e1a01fa4c272..000000000000
--- a/arch/cris/arch-v32/mach-fs/dram_init.S
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DRAM/SDRAM initialization - alter with care
- * This file is intended to be included from other assembler files
- *
- * Note: This file may not modify r8 or r9 because they are used to
- * carry information from the decompressor to the kernel
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-/* Just to be certain the config file is included, we include it here
- * explicitly instead of depending on it being included in the file that
- * uses this code.
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/bif_core_defs_asm.h>
-
- ;; WARNING! The registers r8 and r9 are used as parameters carrying
- ;; information from the decompressor (if the kernel was compressed).
- ;; They should not be used in the code below.
-
- ; Refer to BIF MDS for a description of SDRAM initialization
-
- ; Bank configuration
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
- move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
- move.d CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
- move.d $r1, [$r0]
-
- ; Calculate value of mrs_data
- ; CAS latency = 2 && bus_width = 32 => 0x40
- ; CAS latency = 3 && bus_width = 32 => 0x60
- ; CAS latency = 2 && bus_width = 16 => 0x20
- ; CAS latency = 3 && bus_width = 16 => 0x30
-
- ; Check if value is already supplied in kernel config
- move.d CONFIG_ETRAX_SDRAM_COMMAND, $r2
- bne _set_timing
- nop
-
- move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2
- move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
- and.d 0x07, $r1 ; Get CAS latency
- cmpq 2, $r1 ; CL = 2 ?
- beq _bw_check
- nop
- move.d 0x60, $r4
-
-_bw_check:
- ; Assume that group 0 width is equal to group 1. This assumption
- ; is wrong for a group 1 only hardware (such as the grand old
- ; StorPoint+).
- move.d CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
- and.d 0x200, $r1 ; DRAM width is bit 9
- beq _set_timing
- lslq 2, $r4 ; mrs_data starts at bit 2
- lsrq 1, $r4 ; 16 bits. Shift down value.
-
- ; Set timing parameters (refresh off to avoid Guinness TR 83)
-_set_timing:
- move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
- and.d ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
- move.d $r1, [$r0]
-
- ; Issue NOP command
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
- moveq regk_bif_core_nop, $r1
- move.d $r1, [$r5]
-
- ; Wait 200us
- move.d 10000, $r2
-1: bne 1b
- subq 1, $r2
-
- ; Issue initialization command sequence
- lapc _sdram_commands_start, $r2
- lapc _sdram_commands_end, $r3
-1: clear.d $r6
- move.b [$r2+], $r6 ; Load command
- or.d $r4, $r6 ; Add calculated mrs
- move.d $r6, [$r5] ; Write rw_sdram_cmd
- ; Wait 80 ns between each command
- move.d 4000, $r7
-2: bne 2b
- subq 1, $r7
- cmp.d $r2, $r3 ; Last command?
- bne 1b
- nop
-
- ; Start refresh
- move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
- move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
- move.d $r1, [$r0]
-
- ; Initialization finished
- ba _sdram_commands_end
- nop
-
-_sdram_commands_start:
- .byte regk_bif_core_pre ; Precharge
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_ref ; refresh
- .byte regk_bif_core_mrs ; mrs
-_sdram_commands_end:
diff --git a/arch/cris/arch-v32/mach-fs/hw_settings.S b/arch/cris/arch-v32/mach-fs/hw_settings.S
deleted file mode 100644
index 7fbadcc48c0c..000000000000
--- a/arch/cris/arch-v32/mach-fs/hw_settings.S
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This table is used by some tools to extract hardware parameters.
- * The table should be included in the kernel and the decompressor.
- * Don't forget to update the tools if you change this table.
- *
- * Copyright (C) 2001-2007 Axis Communications AB
- *
- * Authors: Mikael Starvik <starvik@axis.com>
- */
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/bif_core_defs_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-
- .ascii "HW_PARAM_MAGIC" ; Magic number
- .dword 0xc0004000 ; Kernel start address
-
- ; Debug port
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- .dword 0
-#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
- .dword 1
-#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
- .dword 2
-#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
- .dword 3
-#else
- .dword 4 ; No debug
-#endif
-
- ; Register values
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg)
- .dword CONFIG_ETRAX_MEM_GRP1_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg)
- .dword CONFIG_ETRAX_MEM_GRP2_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg)
- .dword CONFIG_ETRAX_MEM_GRP3_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg)
- .dword CONFIG_ETRAX_MEM_GRP4_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0)
- .dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1)
- .dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing)
- .dword CONFIG_ETRAX_SDRAM_TIMING
- .dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd)
- .dword CONFIG_ETRAX_SDRAM_COMMAND
-
- .dword REG_ADDR(gio, regi_gio, rw_pa_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pa_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PA_OE
- .dword REG_ADDR(gio, regi_gio, rw_pb_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pb_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PB_OE
- .dword REG_ADDR(gio, regi_gio, rw_pc_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pc_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PC_OE
- .dword REG_ADDR(gio, regi_gio, rw_pd_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PD_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pd_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PD_OE
- .dword REG_ADDR(gio, regi_gio, rw_pe_dout)
- .dword CONFIG_ETRAX_DEF_GIO_PE_OUT
- .dword REG_ADDR(gio, regi_gio, rw_pe_oe)
- .dword CONFIG_ETRAX_DEF_GIO_PE_OE
-
- .dword 0 ; No more register values
diff --git a/arch/cris/arch-v32/mach-fs/pinmux.c b/arch/cris/arch-v32/mach-fs/pinmux.c
deleted file mode 100644
index a0b2f101003a..000000000000
--- a/arch/cris/arch-v32/mach-fs/pinmux.c
+++ /dev/null
@@ -1,328 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
- * Unassigned pins and GPIO pins can be allocated to a fixed interface
- * or the I/O processor instead.
- *
- * Copyright (c) 2004-2007 Axis Communications AB.
- */
-
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/spinlock.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <pinmux.h>
-#include <hwregs/pinmux_defs.h>
-
-#undef DEBUG
-
-#define PORT_PINS 18
-#define PORTS 4
-
-static char pins[PORTS][PORT_PINS];
-static DEFINE_SPINLOCK(pinmux_lock);
-
-static void crisv32_pinmux_set(int port);
-
-static int __crisv32_pinmux_alloc(int port, int first_pin, int last_pin,
- enum pin_mode mode)
-{
- int i;
-
- for (i = first_pin; i <= last_pin; i++) {
- if ((pins[port][i] != pinmux_none)
- && (pins[port][i] != pinmux_gpio)
- && (pins[port][i] != mode)) {
-#ifdef DEBUG
- panic("Pinmux alloc failed!\n");
-#endif
- return -EPERM;
- }
- }
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port][i] = mode;
-
- crisv32_pinmux_set(port);
-
- return 0;
-}
-
-static int crisv32_pinmux_init(void)
-{
- static int initialized;
-
- if (!initialized) {
- reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa);
- initialized = 1;
- REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
- pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 =
- pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes;
- REG_WR(pinmux, regi_pinmux, rw_pa, pa);
- __crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio);
- __crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio);
- __crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio);
- __crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio);
- }
-
- return 0;
-}
-
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin,
- enum pin_mode mode)
-{
- unsigned long flags;
- int ret;
-
- crisv32_pinmux_init();
-
- if (port > PORTS || port < 0)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- ret = __crisv32_pinmux_alloc(port, first_pin, last_pin, mode);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-int crisv32_pinmux_alloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-
- switch (function) {
- case pinmux_ser1:
- ret = __crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed);
- hwprot.ser1 = regk_pinmux_yes;
- break;
- case pinmux_ser2:
- ret = __crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed);
- hwprot.ser2 = regk_pinmux_yes;
- break;
- case pinmux_ser3:
- ret = __crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed);
- hwprot.ser3 = regk_pinmux_yes;
- break;
- case pinmux_sser0:
- ret = __crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
- hwprot.sser0 = regk_pinmux_yes;
- break;
- case pinmux_sser1:
- ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
- hwprot.sser1 = regk_pinmux_yes;
- break;
- case pinmux_ata0:
- ret = __crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed);
- hwprot.ata0 = regk_pinmux_yes;
- break;
- case pinmux_ata1:
- ret = __crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed);
- hwprot.ata1 = regk_pinmux_yes;
- break;
- case pinmux_ata2:
- ret = __crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed);
- hwprot.ata2 = regk_pinmux_yes;
- break;
- case pinmux_ata3:
- ret = __crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed);
- hwprot.ata2 = regk_pinmux_yes;
- break;
- case pinmux_ata:
- ret = __crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed);
- ret |= __crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed);
- hwprot.ata = regk_pinmux_yes;
- break;
- case pinmux_eth1:
- ret = __crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed);
- hwprot.eth1 = regk_pinmux_yes;
- hwprot.eth1_mgm = regk_pinmux_yes;
- break;
- case pinmux_timer:
- ret = __crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
- hwprot.timer = regk_pinmux_yes;
- spin_unlock_irqrestore(&pinmux_lock, flags);
- return ret;
- }
-
- if (!ret)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-void crisv32_pinmux_set(int port)
-{
- int i;
- int gpio_val = 0;
- int iop_val = 0;
-
- for (i = 0; i < PORT_PINS; i++) {
- if (pins[port][i] == pinmux_gpio)
- gpio_val |= (1 << i);
- else if (pins[port][i] == pinmux_iop)
- iop_val |= (1 << i);
- }
-
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port,
- gpio_val);
- REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port,
- iop_val);
-
-#ifdef DEBUG
- crisv32_pinmux_dump();
-#endif
-}
-
-static int __crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
-{
- int i;
-
- for (i = first_pin; i <= last_pin; i++)
- pins[port][i] = pinmux_none;
-
- crisv32_pinmux_set(port);
- return 0;
-}
-
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
-{
- unsigned long flags;
-
- crisv32_pinmux_init();
-
- if (port > PORTS || port < 0)
- return -EINVAL;
-
- spin_lock_irqsave(&pinmux_lock, flags);
- __crisv32_pinmux_dealloc(port, first_pin, last_pin);
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return 0;
-}
-
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function)
-{
- int ret = -EINVAL;
- char saved[sizeof pins];
- unsigned long flags;
- reg_pinmux_rw_hwprot hwprot;
-
- spin_lock_irqsave(&pinmux_lock, flags);
-
- /* Save internal data for recovery */
- memcpy(saved, pins, sizeof pins);
-
- crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
-
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-
- switch (function) {
- case pinmux_ser1:
- ret = __crisv32_pinmux_dealloc(PORT_C, 4, 7);
- hwprot.ser1 = regk_pinmux_no;
- break;
- case pinmux_ser2:
- ret = __crisv32_pinmux_dealloc(PORT_C, 8, 11);
- hwprot.ser2 = regk_pinmux_no;
- break;
- case pinmux_ser3:
- ret = __crisv32_pinmux_dealloc(PORT_C, 12, 15);
- hwprot.ser3 = regk_pinmux_no;
- break;
- case pinmux_sser0:
- ret = __crisv32_pinmux_dealloc(PORT_C, 0, 3);
- ret |= __crisv32_pinmux_dealloc(PORT_C, 16, 16);
- hwprot.sser0 = regk_pinmux_no;
- break;
- case pinmux_sser1:
- ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4);
- hwprot.sser1 = regk_pinmux_no;
- break;
- case pinmux_ata0:
- ret = __crisv32_pinmux_dealloc(PORT_D, 5, 7);
- ret |= __crisv32_pinmux_dealloc(PORT_D, 15, 17);
- hwprot.ata0 = regk_pinmux_no;
- break;
- case pinmux_ata1:
- ret = __crisv32_pinmux_dealloc(PORT_D, 0, 4);
- ret |= __crisv32_pinmux_dealloc(PORT_E, 17, 17);
- hwprot.ata1 = regk_pinmux_no;
- break;
- case pinmux_ata2:
- ret = __crisv32_pinmux_dealloc(PORT_C, 11, 15);
- ret |= __crisv32_pinmux_dealloc(PORT_E, 3, 3);
- hwprot.ata2 = regk_pinmux_no;
- break;
- case pinmux_ata3:
- ret = __crisv32_pinmux_dealloc(PORT_C, 8, 10);
- ret |= __crisv32_pinmux_dealloc(PORT_C, 0, 2);
- hwprot.ata2 = regk_pinmux_no;
- break;
- case pinmux_ata:
- ret = __crisv32_pinmux_dealloc(PORT_B, 0, 15);
- ret |= __crisv32_pinmux_dealloc(PORT_D, 8, 15);
- hwprot.ata = regk_pinmux_no;
- break;
- case pinmux_eth1:
- ret = __crisv32_pinmux_dealloc(PORT_E, 0, 17);
- hwprot.eth1 = regk_pinmux_no;
- hwprot.eth1_mgm = regk_pinmux_no;
- break;
- case pinmux_timer:
- ret = __crisv32_pinmux_dealloc(PORT_C, 16, 16);
- hwprot.timer = regk_pinmux_no;
- spin_unlock_irqrestore(&pinmux_lock, flags);
- return ret;
- }
-
- if (!ret)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
- else
- memcpy(pins, saved, sizeof pins);
-
- spin_unlock_irqrestore(&pinmux_lock, flags);
-
- return ret;
-}
-
-#ifdef DEBUG
-static void crisv32_pinmux_dump(void)
-{
- int i, j;
-
- crisv32_pinmux_init();
-
- for (i = 0; i < PORTS; i++) {
- printk(KERN_DEBUG "Port %c\n", 'B' + i);
- for (j = 0; j < PORT_PINS; j++)
- printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i][j]);
- }
-}
-#endif
-__initcall(crisv32_pinmux_init);
diff --git a/arch/cris/arch-v32/mm/Makefile b/arch/cris/arch-v32/mm/Makefile
deleted file mode 100644
index 0b801f2964ac..000000000000
--- a/arch/cris/arch-v32/mm/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# Makefile for the Linux/cris parts of the memory manager.
-
-obj-y += mmu.o init.o tlb.o intmem.o
-obj-$(CONFIG_ETRAX_L2CACHE) += l2cache.o
diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c
deleted file mode 100644
index 784876afa001..000000000000
--- a/arch/cris/arch-v32/mm/init.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Set up paging and the MMU.
- *
- * Copyright (C) 2000-2003, Axis Communications AB.
- *
- * Authors: Bjorn Wesen <bjornw@axis.com>
- * Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
- */
-#include <linux/mmzone.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/mm.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/types.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <arch/hwregs/asm/mmu_defs_asm.h>
-#include <arch/hwregs/supp_reg.h>
-
-extern void tlb_init(void);
-
-/*
- * The kernel is already mapped with linear mapping at kseg_c so there's no
- * need to map it with a page table. However, head.S also temporarily mapped it
- * at kseg_4 thus the ksegs are set up again. Also clear the TLB and do various
- * other paging stuff.
- */
-void __init cris_mmu_init(void)
-{
- unsigned long mmu_config;
- unsigned long mmu_kbase_hi;
- unsigned long mmu_kbase_lo;
- unsigned short mmu_page_id;
-
- /*
- * Make sure the current pgd table points to something sane, even if it
- * is most probably not used until the next switch_mm.
- */
- per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
-
- /* Initialise the TLB. Function found in tlb.c. */
- tlb_init();
-
- /*
- * Enable exceptions and initialize the kernel segments.
- * See head.S for differences between ARTPEC-3 and ETRAX FS.
- */
- mmu_config = ( REG_STATE(mmu, rw_mm_cfg, we, on) |
- REG_STATE(mmu, rw_mm_cfg, acc, on) |
- REG_STATE(mmu, rw_mm_cfg, ex, on) |
- REG_STATE(mmu, rw_mm_cfg, inv, on) |
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- REG_STATE(mmu, rw_mm_cfg, seg_f, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_e, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_d, linear) |
-#else
- REG_STATE(mmu, rw_mm_cfg, seg_f, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_e, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_d, page) |
-#endif
- REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
- REG_STATE(mmu, rw_mm_cfg, seg_a, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_9, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_8, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_7, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_6, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_5, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_4, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_3, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_2, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_1, page) |
- REG_STATE(mmu, rw_mm_cfg, seg_0, page));
-
- /* See head.S for differences between ARTPEC-3 and ETRAX FS. */
- mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x5) |
-#else
- REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
-#endif
- REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_9, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_hi, base_8, 0x0));
-
- mmu_kbase_lo = ( REG_FIELD(mmu, rw_mm_kbase_lo, base_7, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_6, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_5, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_3, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_2, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_1, 0x0) |
- REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0x0));
-
- mmu_page_id = REG_FIELD(mmu, rw_mm_tlb_hi, pid, 0);
-
- /* Update the instruction MMU. */
- SUPP_BANK_SEL(BANK_IM);
- SUPP_REG_WR(RW_MM_CFG, mmu_config);
- SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
- SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
- SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
-
- /* Update the data MMU. */
- SUPP_BANK_SEL(BANK_DM);
- SUPP_REG_WR(RW_MM_CFG, mmu_config);
- SUPP_REG_WR(RW_MM_KBASE_HI, mmu_kbase_hi);
- SUPP_REG_WR(RW_MM_KBASE_LO, mmu_kbase_lo);
- SUPP_REG_WR(RW_MM_TLB_HI, mmu_page_id);
-
- SPEC_REG_WR(SPEC_REG_PID, 0);
-
- /*
- * The MMU has been enabled ever since head.S but just to make it
- * totally obvious enable it here as well.
- */
- SUPP_BANK_SEL(BANK_GC);
- SUPP_REG_WR(RW_GC_CFG, 0xf); /* IMMU, DMMU, ICache, DCache on */
-}
-
-void __init paging_init(void)
-{
- int i;
- unsigned long zones_size[MAX_NR_ZONES];
-
- printk("Setting up paging and the MMU.\n");
-
- /* Clear out the init_mm.pgd that will contain the kernel's mappings. */
- for(i = 0; i < PTRS_PER_PGD; i++)
- swapper_pg_dir[i] = __pgd(0);
-
- cris_mmu_init();
-
- /*
- * Initialize the bad page table and bad page to point to a couple of
- * allocated pages.
- */
- empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
- memset((void *) empty_zero_page, 0, PAGE_SIZE);
-
- /* All pages are DMA'able in Etrax, so put all in the DMA'able zone. */
- zones_size[0] = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
-
- for (i = 1; i < MAX_NR_ZONES; i++)
- zones_size[i] = 0;
-
- /*
- * Use free_area_init_node instead of free_area_init, because it is
- * designed for systems where the DRAM starts at an address
- * substantially higher than 0, like us (we start at PAGE_OFFSET). This
- * saves space in the mem_map page array.
- */
- free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
-
- mem_map = contig_page_data.node_mem_map;
-}
diff --git a/arch/cris/arch-v32/mm/intmem.c b/arch/cris/arch-v32/mm/intmem.c
deleted file mode 100644
index 928b94d1d320..000000000000
--- a/arch/cris/arch-v32/mm/intmem.c
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Simple allocator for internal RAM in ETRAX FS
- *
- * Copyright (c) 2004 Axis Communications AB.
- */
-
-#include <linux/list.h>
-#include <linux/slab.h>
-#include <asm/io.h>
-#include <memmap.h>
-
-#define STATUS_FREE 0
-#define STATUS_ALLOCATED 1
-
-#ifdef CONFIG_ETRAX_L2CACHE
-#define RESERVED_SIZE 66*1024
-#else
-#define RESERVED_SIZE 0
-#endif
-
-struct intmem_allocation {
- struct list_head entry;
- unsigned int size;
- unsigned offset;
- char status;
-};
-
-
-static struct list_head intmem_allocations;
-static void* intmem_virtual;
-
-static void crisv32_intmem_init(void)
-{
- static int initiated = 0;
- if (!initiated) {
- struct intmem_allocation* alloc;
- alloc = kmalloc(sizeof *alloc, GFP_KERNEL);
- INIT_LIST_HEAD(&intmem_allocations);
- intmem_virtual = ioremap(MEM_INTMEM_START + RESERVED_SIZE,
- MEM_INTMEM_SIZE - RESERVED_SIZE);
- initiated = 1;
- alloc->size = MEM_INTMEM_SIZE - RESERVED_SIZE;
- alloc->offset = 0;
- alloc->status = STATUS_FREE;
- list_add_tail(&alloc->entry, &intmem_allocations);
- }
-}
-
-void* crisv32_intmem_alloc(unsigned size, unsigned align)
-{
- struct intmem_allocation* allocation;
- struct intmem_allocation* tmp;
- void* ret = NULL;
-
- preempt_disable();
- crisv32_intmem_init();
-
- list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) {
- int alignment = allocation->offset % align;
- alignment = alignment ? align - alignment : alignment;
-
- if (allocation->status == STATUS_FREE &&
- allocation->size >= size + alignment) {
- if (allocation->size > size + alignment) {
- struct intmem_allocation* alloc;
- alloc = kmalloc(sizeof *alloc, GFP_ATOMIC);
- alloc->status = STATUS_FREE;
- alloc->size = allocation->size - size -
- alignment;
- alloc->offset = allocation->offset + size +
- alignment;
- list_add(&alloc->entry, &allocation->entry);
-
- if (alignment) {
- struct intmem_allocation *tmp;
- tmp = kmalloc(sizeof *tmp, GFP_ATOMIC);
- tmp->offset = allocation->offset;
- tmp->size = alignment;
- tmp->status = STATUS_FREE;
- allocation->offset += alignment;
- list_add_tail(&tmp->entry,
- &allocation->entry);
- }
- }
- allocation->status = STATUS_ALLOCATED;
- allocation->size = size;
- ret = (void*)((int)intmem_virtual + allocation->offset);
- }
- }
- preempt_enable();
- return ret;
-}
-
-void crisv32_intmem_free(void* addr)
-{
- struct intmem_allocation* allocation;
- struct intmem_allocation* tmp;
-
- if (addr == NULL)
- return;
-
- preempt_disable();
- crisv32_intmem_init();
-
- list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) {
- if (allocation->offset == (int)(addr - intmem_virtual)) {
- struct intmem_allocation *prev =
- list_entry(allocation->entry.prev,
- struct intmem_allocation, entry);
- struct intmem_allocation *next =
- list_entry(allocation->entry.next,
- struct intmem_allocation, entry);
-
- allocation->status = STATUS_FREE;
- /* Join with prev and/or next if also free */
- if ((&prev->entry != &intmem_allocations) &&
- (prev->status == STATUS_FREE)) {
- prev->size += allocation->size;
- list_del(&allocation->entry);
- kfree(allocation);
- allocation = prev;
- }
- if ((&next->entry != &intmem_allocations) &&
- (next->status == STATUS_FREE)) {
- allocation->size += next->size;
- list_del(&next->entry);
- kfree(next);
- }
- preempt_enable();
- return;
- }
- }
- preempt_enable();
-}
-
-void* crisv32_intmem_phys_to_virt(unsigned long addr)
-{
- return (void *)(addr - (MEM_INTMEM_START + RESERVED_SIZE) +
- (unsigned long)intmem_virtual);
-}
-
-unsigned long crisv32_intmem_virt_to_phys(void* addr)
-{
- return (unsigned long)((unsigned long )addr -
- (unsigned long)intmem_virtual + MEM_INTMEM_START +
- RESERVED_SIZE);
-}
-
-static int __init crisv32_intmem_setup(void)
-{
- crisv32_intmem_init();
-
- return 0;
-}
-device_initcall(crisv32_intmem_setup);
-
diff --git a/arch/cris/arch-v32/mm/l2cache.c b/arch/cris/arch-v32/mm/l2cache.c
deleted file mode 100644
index 4fef321d5606..000000000000
--- a/arch/cris/arch-v32/mm/l2cache.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <memmap.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/l2cache_defs.h>
-#include <asm/io.h>
-
-#define L2CACHE_SIZE 64
-
-int __init l2cache_init(void)
-{
- reg_l2cache_rw_ctrl ctrl = {0};
- reg_l2cache_rw_cfg cfg = {.en = regk_l2cache_yes};
-
- ctrl.csize = L2CACHE_SIZE;
- ctrl.cbase = L2CACHE_SIZE / 4 + (L2CACHE_SIZE % 4 ? 1 : 0);
- REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl);
-
- /* Flush the tag memory */
- memset((void *)(MEM_INTMEM_START | MEM_NON_CACHEABLE), 0, 2*1024);
-
- /* Enable the cache */
- REG_WR(l2cache, regi_l2cache, rw_cfg, cfg);
-
- return 0;
-}
-
diff --git a/arch/cris/arch-v32/mm/mmu.S b/arch/cris/arch-v32/mm/mmu.S
deleted file mode 100644
index f24965703f6d..000000000000
--- a/arch/cris/arch-v32/mm/mmu.S
+++ /dev/null
@@ -1,211 +0,0 @@
-; SPDX-License-Identifier: GPL-2.0
-; WARNING : The refill handler has been modified, see below !!!
-
-/*
- * Copyright (C) 2003 Axis Communications AB
- *
- * Authors: Mikael Starvik (starvik@axis.com)
- *
- * Code for the fault low-level handling routines.
- *
- */
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
-; Save all register. Must save in same order as struct pt_regs.
-.macro SAVE_ALL
- subq 12, $sp
- move $erp, [$sp]
- subq 4, $sp
- move $srp, [$sp]
- subq 4, $sp
- move $ccs, [$sp]
- subq 4, $sp
- move $spc, [$sp]
- subq 4, $sp
- move $mof, [$sp]
- subq 4, $sp
- move $srs, [$sp]
- subq 4, $sp
- move.d $acr, [$sp]
- subq 14*4, $sp
- movem $r13, [$sp]
- subq 4, $sp
- move.d $r10, [$sp]
-.endm
-
-; Bus fault handler. Extracts relevant information and calls mm subsystem
-; to handle the fault.
-.macro MMU_BUS_FAULT_HANDLER handler, mmu, we, ex
- .globl \handler
- .type \handler,"function"
-\handler:
- SAVE_ALL
- move \mmu, $srs ; Select MMU support register bank
- move.d $sp, $r11 ; regs
- moveq 1, $r12 ; protection fault
- moveq \we, $r13 ; write exception?
- orq \ex << 1, $r13 ; execute?
- move $s3, $r10 ; rw_mm_cause
- and.d ~8191, $r10 ; Get faulting page start address
-
- jsr do_page_fault
- nop
- ba ret_from_intr
- nop
- .size \handler, . - \handler
-.endm
-
-; Refill handler. Three cases may occur:
-; 1. PMD and PTE exists in mm subsystem but not in TLB
-; 2. PMD exists but not PTE
-; 3. PMD doesn't exist
-; The code below handles case 1 and calls the mm subsystem for case 2 and 3.
-; Do not touch this code without very good reasons and extensive testing.
-; Note that the code is optimized to minimize stalls (makes the code harder
-; to read).
-;
-; WARNING !!!
-; Modified by Mikael Asker 060725: added a workaround for strange TLB
-; behavior. If the same PTE is present in more than one set, the TLB
-; doesn't recognize it and we get stuck in a loop of refill exceptions.
-; The workaround detects such loops and exits them by flushing
-; the TLB contents. The problem and workaround were verified
-; in VCS by Mikael Starvik.
-;
-; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each
-; PMD holds 16 MB of virtual memory.
-; Bits 0-12 : Offset within a page
-; Bits 13-23 : PTE offset within a PMD
-; Bits 24-31 : PMD offset within the PGD
-
-.macro MMU_REFILL_HANDLER handler, mmu
- .data
-1: .dword 0 ; refill_count
- ; == 0 <=> last_refill_cause is invalid
-2: .dword 0 ; last_refill_cause
- .text
- .globl \handler
- .type \handler, "function"
-\handler:
- subq 4, $sp
-; (The pipeline stalls for one cycle; $sp used as address in the next cycle.)
- move $srs, [$sp]
- subq 4, $sp
- move \mmu, $srs ; Select MMU support register bank
- move.d $acr, [$sp]
- subq 12, $sp
- move.d 1b, $acr ; Point to refill_count
- movem $r2, [$sp]
-
- test.d [$acr] ; refill_count == 0 ?
- beq 5f ; yes, last_refill_cause is invalid
- move.d $acr, $r1
-
- ; last_refill_cause is valid, investigate cause
- addq 4, $r1 ; Point to last_refill_cause
- move $s3, $r0 ; Get rw_mm_cause
- move.d [$r1], $r2 ; Get last_refill_cause
- cmp.d $r0, $r2 ; rw_mm_cause == last_refill_cause ?
- beq 6f ; yes, increment count
- moveq 1, $r2
-
- ; rw_mm_cause != last_refill_cause
- move.d $r2, [$acr] ; refill_count = 1
- move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause
-
-3: ; Probably not in a loop, continue normal processing
- move.d current_pgd, $acr ; PGD
- ; Look up PMD in PGD
- lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31)
- move.d [$acr], $acr ; PGD for the current process
- addi $r0.d, $acr, $acr
- move $s3, $r0 ; rw_mm_cause
- move.d [$acr], $acr ; Get PMD
- beq 8f
- ; Look up PTE in PMD
- lsrq PAGE_SHIFT, $r0
- and.w PAGE_MASK, $acr ; Remove PMD flags
- and.d 0x7ff, $r0 ; Get PTE index into PMD (bit 13-23)
- addi $r0.d, $acr, $acr
- move.d [$acr], $acr ; Get PTE
- beq 9f
- movem [$sp], $r2 ; Restore r0-r2 in delay slot
- addq 12, $sp
- ; Store in TLB
- move $acr, $s5
-4: ; Return
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- rete
- rfe
-
-5: ; last_refill_cause is invalid
- moveq 1, $r2
- addq 4, $r1 ; Point to last_refill_cause
- move.d $r2, [$acr] ; refill_count = 1
- move $s3, $r0 ; Get rw_mm_cause
- ba 3b ; Continue normal processing
- move.d $r0,[$r1] ; last_refill_cause = rw_mm_cause
-
-6: ; rw_mm_cause == last_refill_cause
- move.d [$acr], $r2 ; Get refill_count
- cmpq 4, $r2 ; refill_count > 4 ?
- bhi 7f ; yes
- addq 1, $r2 ; refill_count++
- ba 3b ; Continue normal processing
- move.d $r2, [$acr]
-
-7: ; refill_count > 4, error
- move.d $acr, $r0 ; Save pointer to refill_count
- clear.d [$r0] ; refill_count = 0
-
- ;; rewind the short stack
- movem [$sp], $r2 ; Restore r0-r2
- addq 12, $sp
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- ;; Keep it simple (slow), save all the regs.
- SAVE_ALL
- jsr __flush_tlb_all
- nop
- ba ret_from_intr ; Return
- nop
-
-8: ; PMD missing, let the mm subsystem fix it up.
- movem [$sp], $r2 ; Restore r0-r2
-9: ; PTE missing, let the mm subsystem fix it up.
- addq 12, $sp
- move.d [$sp+], $acr
- move [$sp], $srs
- addq 4, $sp
- SAVE_ALL
- move \mmu, $srs
- move.d $sp, $r11 ; regs
- clear.d $r12 ; Not a protection fault
- move.w PAGE_MASK, $acr
- move $s3, $r10 ; rw_mm_cause
- btstq 9, $r10 ; Check if write access
- smi $r13
- and.w PAGE_MASK, $r10 ; Get VPN (virtual address)
- jsr do_page_fault
- and.w $acr, $r10
- ; Return
- ba ret_from_intr
- nop
- .size \handler, . - \handler
-.endm
-
- ; This is the MMU bus fault handlers.
-
-MMU_REFILL_HANDLER i_mmu_refill, 1
-MMU_BUS_FAULT_HANDLER i_mmu_invalid, 1, 0, 0
-MMU_BUS_FAULT_HANDLER i_mmu_access, 1, 0, 0
-MMU_BUS_FAULT_HANDLER i_mmu_execute, 1, 0, 1
-MMU_REFILL_HANDLER d_mmu_refill, 2
-MMU_BUS_FAULT_HANDLER d_mmu_invalid, 2, 0, 0
-MMU_BUS_FAULT_HANDLER d_mmu_access, 2, 0, 0
-MMU_BUS_FAULT_HANDLER d_mmu_write, 2, 1, 0
diff --git a/arch/cris/arch-v32/mm/tlb.c b/arch/cris/arch-v32/mm/tlb.c
deleted file mode 100644
index 9e4b5ab4971d..000000000000
--- a/arch/cris/arch-v32/mm/tlb.c
+++ /dev/null
@@ -1,209 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Low level TLB handling.
- *
- * Copyright (C) 2000-2003, Axis Communications AB.
- *
- * Authors: Bjorn Wesen <bjornw@axis.com>
- * Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
- */
-#include <linux/mm_types.h>
-
-#include <asm/tlb.h>
-#include <asm/mmu_context.h>
-#include <arch/hwregs/asm/mmu_defs_asm.h>
-#include <arch/hwregs/supp_reg.h>
-
-#define UPDATE_TLB_SEL_IDX(val) \
-do { \
- unsigned long tlb_sel; \
- \
- tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \
- SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \
-} while(0)
-
-#define UPDATE_TLB_HILO(tlb_hi, tlb_lo) \
-do { \
- SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi); \
- SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo); \
-} while(0)
-
-/*
- * The TLB can host up to 256 different mm contexts at the same time. The running
- * context is found in the PID register. Each TLB entry contains a page_id that
- * has to match the PID register to give a hit. page_id_map keeps track of which
- * mm's is assigned to which page_id's, making sure it's known when to
- * invalidate TLB entries.
- *
- * The last page_id is never running, it is used as an invalid page_id so that
- * it's possible to make TLB entries that will nerver match.
- *
- * Note; the flushes needs to be atomic otherwise an interrupt hander that uses
- * vmalloc'ed memory might cause a TLB load in the middle of a flush.
- */
-
-/* Flush all TLB entries. */
-void
-__flush_tlb_all(void)
-{
- int i;
- int mmu;
- unsigned long flags;
- unsigned long mmu_tlb_hi;
- unsigned long mmu_tlb_sel;
-
- /*
- * Mask with 0xf so similar TLB entries aren't written in the same 4-way
- * entry group.
- */
- local_irq_save(flags);
-
- for (mmu = 1; mmu <= 2; mmu++) {
- SUPP_BANK_SEL(mmu); /* Select the MMU */
- for (i = 0; i < NUM_TLB_ENTRIES; i++) {
- /* Store invalid entry */
- mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i);
-
- mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID)
- | REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf));
-
- SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel);
- SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi);
- SUPP_REG_WR(RW_MM_TLB_LO, 0);
- }
- }
-
- local_irq_restore(flags);
-}
-
-/* Flush an entire user address space. */
-void
-__flush_tlb_mm(struct mm_struct *mm)
-{
- int i;
- int mmu;
- unsigned long flags;
- unsigned long page_id;
- unsigned long tlb_hi;
- unsigned long mmu_tlb_hi;
-
- page_id = mm->context.page_id;
-
- if (page_id == NO_CONTEXT)
- return;
-
- /* Mark the TLB entries that match the page_id as invalid. */
- local_irq_save(flags);
-
- for (mmu = 1; mmu <= 2; mmu++) {
- SUPP_BANK_SEL(mmu);
- for (i = 0; i < NUM_TLB_ENTRIES; i++) {
- UPDATE_TLB_SEL_IDX(i);
-
- /* Get the page_id */
- SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
-
- /* Check if the page_id match. */
- if ((tlb_hi & 0xff) == page_id) {
- mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid,
- INVALID_PAGEID)
- | REG_FIELD(mmu, rw_mm_tlb_hi, vpn,
- i & 0xf));
-
- UPDATE_TLB_HILO(mmu_tlb_hi, 0);
- }
- }
- }
-
- local_irq_restore(flags);
-}
-
-/* Invalidate a single page. */
-void
-__flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
- int i;
- int mmu;
- unsigned long page_id;
- unsigned long flags;
- unsigned long tlb_hi;
- unsigned long mmu_tlb_hi;
-
- page_id = vma->vm_mm->context.page_id;
-
- if (page_id == NO_CONTEXT)
- return;
-
- addr &= PAGE_MASK;
-
- /*
- * Invalidate those TLB entries that match both the mm context and the
- * requested virtual address.
- */
- local_irq_save(flags);
-
- for (mmu = 1; mmu <= 2; mmu++) {
- SUPP_BANK_SEL(mmu);
- for (i = 0; i < NUM_TLB_ENTRIES; i++) {
- UPDATE_TLB_SEL_IDX(i);
- SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
-
- /* Check if page_id and address matches */
- if (((tlb_hi & 0xff) == page_id) &&
- ((tlb_hi & PAGE_MASK) == addr)) {
- mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid,
- INVALID_PAGEID) | addr;
-
- UPDATE_TLB_HILO(mmu_tlb_hi, 0);
- }
- }
- }
-
- local_irq_restore(flags);
-}
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-
-int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- mm->context.page_id = NO_CONTEXT;
- return 0;
-}
-
-static DEFINE_SPINLOCK(mmu_context_lock);
-
-/* Called in schedule() just before actually doing the switch_to. */
-void
-switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- if (prev != next) {
- int cpu = smp_processor_id();
-
- /* Make sure there is a MMU context. */
- spin_lock(&mmu_context_lock);
- get_mmu_context(next);
- cpumask_set_cpu(cpu, mm_cpumask(next));
- spin_unlock(&mmu_context_lock);
-
- /*
- * Remember the pgd for the fault handlers. Keep a separate
- * copy of it because current and active_mm might be invalid
- * at points where * there's still a need to derefer the pgd.
- */
- per_cpu(current_pgd, cpu) = next->pgd;
-
- /* Switch context in the MMU. */
- if (tsk && task_thread_info(tsk)) {
- SPEC_REG_WR(SPEC_REG_PID, next->context.page_id |
- task_thread_info(tsk)->tls);
- } else {
- SPEC_REG_WR(SPEC_REG_PID, next->context.page_id);
- }
- }
-}
-
diff --git a/arch/cris/arch-v32/output_arch.ld b/arch/cris/arch-v32/output_arch.ld
deleted file mode 100644
index d60a57db0ec2..000000000000
--- a/arch/cris/arch-v32/output_arch.ld
+++ /dev/null
@@ -1,2 +0,0 @@
-/* At the time of this writing, there's no equivalent ld option. */
-OUTPUT_ARCH (crisv32)
diff --git a/arch/cris/boot/.gitignore b/arch/cris/boot/.gitignore
deleted file mode 100644
index 171a0853caf8..000000000000
--- a/arch/cris/boot/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Image
-zImage
diff --git a/arch/cris/boot/Makefile b/arch/cris/boot/Makefile
deleted file mode 100644
index 859d275f862b..000000000000
--- a/arch/cris/boot/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/cris/boot/Makefile
-#
-
-objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment
-objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id
-
-OBJCOPYFLAGS = -O binary $(objcopyflags-y)
-
-
-subdir- := compressed rescue
-targets := Image
-
-$(obj)/Image: vmlinux FORCE
- $(call if_changed,objcopy)
- @echo ' Kernel: $@ is ready'
-
-$(obj)/compressed/vmlinux: $(obj)/Image FORCE
- $(Q)$(MAKE) $(build)=$(obj)/compressed $@
- $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin
-
-$(obj)/zImage: $(obj)/compressed/vmlinux
- @cp $< $@
- @echo ' Kernel: $@ is ready'
diff --git a/arch/cris/boot/compressed/Makefile b/arch/cris/boot/compressed/Makefile
deleted file mode 100644
index e149c3467c93..000000000000
--- a/arch/cris/boot/compressed/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# arch/cris/boot/compressed/Makefile
-#
-
-# asflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/mach \
-# -I$(srctree)/include/asm/arch
-# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -O2 -I$(srctree)/include/asm/mach
-# -I$(srctree)/include/asm/arch
-
-arch-$(CONFIG_ETRAX_ARCH_V10) = v10
-arch-$(CONFIG_ETRAX_ARCH_V32) = v32
-
-ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds
-
-OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o
-OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o
-OBJECTS= $(OBJECTS-y) $(obj)/misc.o
-OBJCOPYFLAGS = -O binary --remove-section=.bss
-
-quiet_cmd_image = BUILD $@
-cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@
-
-targets := vmlinux piggy.gz decompress.o decompress.bin
-
-$(obj)/decompress.o: $(OBJECTS) FORCE
- $(call if_changed,ld)
-
-$(obj)/decompress.bin: $(obj)/decompress.o FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE
- $(call if_changed,image)
-
-$(obj)/piggy.gz: $(obj)/../Image FORCE
- $(call if_changed,gzip)
diff --git a/arch/cris/boot/compressed/README b/arch/cris/boot/compressed/README
deleted file mode 100644
index 182c5d75784b..000000000000
--- a/arch/cris/boot/compressed/README
+++ /dev/null
@@ -1,24 +0,0 @@
-Creation of the self-extracting compressed kernel image (vmlinuz)
------------------------------------------------------------------
-
-This can be slightly confusing because it's a process with many steps.
-
-The kernel object built by the arch/etrax100/Makefile, vmlinux, is split
-by that makefile into text and data binary files, vmlinux.text and
-vmlinux.data.
-
-Those files together with a ROM filesystem can be catted together and
-burned into a flash or executed directly at the DRAM origin.
-
-They can also be catted together and compressed with gzip, which is what
-happens in this makefile. Together they make up piggy.img.
-
-The decompressor is built into the file decompress.o. It is turned into
-the binary file decompress.bin, which is catted together with piggy.img
-into the file vmlinuz. It can be executed in an arbitrary place in flash.
-
-Be careful - it assumes some things about free locations in DRAM. It
-assumes the DRAM starts at 0x40000000 and that it is at least 8 MB,
-so it puts its code at 0x40700000, and initial stack at 0x40800000.
-
--Bjorn
diff --git a/arch/cris/boot/compressed/decompress_v10.lds b/arch/cris/boot/compressed/decompress_v10.lds
deleted file mode 100644
index d8326779dda2..000000000000
--- a/arch/cris/boot/compressed/decompress_v10.lds
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* OUTPUT_FORMAT(elf32-us-cris) */
-OUTPUT_FORMAT(elf32-cris)
-
-MEMORY
- {
- dram : ORIGIN = 0x40700000,
- LENGTH = 0x00100000
- }
-
-SECTIONS
-{
- .text :
- {
- _stext = . ;
- *(.text)
- *(.rodata)
- *(.rodata.*)
- _etext = . ;
- } > dram
- .data :
- {
- *(.data)
- _edata = . ;
- } > dram
- .bss :
- {
- *(.bss)
- _end = ALIGN( 0x10 ) ;
- } > dram
-}
diff --git a/arch/cris/boot/compressed/decompress_v32.lds b/arch/cris/boot/compressed/decompress_v32.lds
deleted file mode 100644
index 91d311c243ed..000000000000
--- a/arch/cris/boot/compressed/decompress_v32.lds
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*#OUTPUT_FORMAT(elf32-us-cris) */
-OUTPUT_ARCH (crisv32)
-
-MEMORY
- {
- dram : ORIGIN = 0x40700000,
- LENGTH = 0x00100000
- }
-
-SECTIONS
-{
- .text :
- {
- _stext = . ;
- *(.text)
- *(.rodata)
- *(.rodata.*)
- _etext = . ;
- } > dram
- .data :
- {
- *(.data)
- _edata = . ;
- } > dram
- .bss :
- {
- *(.bss)
- _end = ALIGN( 0x10 ) ;
- } > dram
-}
diff --git a/arch/cris/boot/compressed/head_v10.S b/arch/cris/boot/compressed/head_v10.S
deleted file mode 100644
index 08198d8cd37f..000000000000
--- a/arch/cris/boot/compressed/head_v10.S
+++ /dev/null
@@ -1,127 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * arch/cris/boot/compressed/head.S
- *
- * Copyright (C) 1999, 2001 Axis Communications AB
- *
- * Code that sets up the DRAM registers, calls the
- * decompressor to unpack the piggybacked kernel, and jumps.
- *
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-
- ;; Exported symbols
-
- .globl input_data
-
-
- .text
-
- nop
- di
-
-;; We need to initialze DRAM registers before we start using the DRAM
-
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq dram_init_finished
- nop
-
-#include "../../arch-v10/lib/dram_init.S"
-
-dram_init_finished:
-
- ;; Initiate the PA and PB ports
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
- move.b $r0, [R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
- move.b $r0, [R_PORT_PA_DIR]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
- move.b $r0, [R_PORT_PB_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
- move.b $r0, [R_PORT_PB_DIR]
-
- ;; Setup the stack to a suitably high address.
- ;; We assume 8 MB is the minimum DRAM in an eLinux
- ;; product and put the sp at the top for now.
-
- move.d 0x40800000, $sp
-
- ;; Figure out where the compressed piggyback image is
- ;; in the flash (since we wont try to copy it to DRAM
- ;; before unpacking). It is at _edata, but in flash.
- ;; Use (_edata - basse) as offset to the current PC.
-
-basse: move.d $pc, $r5
- and.d 0x7fffffff, $r5 ; strip any non-cache bit
- subq 2, $r5 ; compensate for the move.d $pc instr
- move.d $r5, $r0 ; save for later - flash address of 'basse'
- add.d _edata, $r5
- sub.d basse, $r5 ; $r5 = flash address of '_edata'
-
- ;; Copy text+data to DRAM
-
- move.d basse, $r1 ; destination
- move.d _edata, $r2 ; end destination
-1: move.w [$r0+], $r3
- move.w $r3, [$r1+]
- cmp.d $r2, $r1
- bcs 1b
- nop
-
- move.d $r5, [input_data] ; for the decompressor
-
-
- ;; Clear the decompressors BSS (between _edata and _end)
-
- moveq 0, $r0
- move.d _edata, $r1
- move.d _end, $r2
-1: move.w $r0, [$r1+]
- cmp.d $r2, $r1
- bcs 1b
- nop
-
- ;; Save command line magic and address.
- move.d _cmd_line_magic, $r12
- move.d $r10, [$r12]
- move.d _cmd_line_addr, $r12
- move.d $r11, [$r12]
-
- ;; Do the decompression and save compressed size in inptr
-
- jsr decompress_kernel
-
- ;; Put start address of root partition in $r9 so the kernel can use it
- ;; when mounting from flash
-
- move.d [input_data], $r9 ; flash address of compressed kernel
- add.d [inptr], $r9 ; size of compressed kernel
-
- ;; Restore command line magic and address.
- move.d _cmd_line_magic, $r10
- move.d [$r10], $r10
- move.d _cmd_line_addr, $r11
- move.d [$r11], $r11
-
- ;; Enter the decompressed kernel
- move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized
- jump 0x40004000 ; kernel is linked to this address
-
- .data
-
-input_data:
- .dword 0 ; used by the decompressor
-_cmd_line_magic:
- .dword 0
-_cmd_line_addr:
- .dword 0
-#include "../../arch-v10/lib/hw_settings.S"
diff --git a/arch/cris/boot/compressed/head_v32.S b/arch/cris/boot/compressed/head_v32.S
deleted file mode 100644
index a997947d31e3..000000000000
--- a/arch/cris/boot/compressed/head_v32.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Code that sets up the DRAM registers, calls the
- * decompressor to unpack the piggybacked kernel, and jumps.
- *
- * Copyright (C) 1999 - 2006, Axis Communications AB
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <hwregs/asm/reg_map_asm.h>
-#include <mach/startup.inc>
-
-#define RAM_INIT_MAGIC 0x56902387
-#define COMMAND_LINE_MAGIC 0x87109563
-
- ;; Exported symbols
-
- .globl input_data
-
- .text
-start:
- di
-
- ;; Start clocks for used blocks.
- START_CLOCKS
-
- ;; Initialize the DRAM registers.
- cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
- beq dram_init_finished
- nop
-
-#if defined CONFIG_ETRAXFS
-#include "../../arch-v32/mach-fs/dram_init.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../../arch-v32/mach-a3/dram_init.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
-
-dram_init_finished:
-
- GIO_INIT
- ;; Setup the stack to a suitably high address.
- ;; We assume 8 MB is the minimum DRAM and put
- ;; the SP at the top for now.
-
- move.d 0x40800000, $sp
-
- ;; Figure out where the compressed piggyback image is.
- ;; It is either in [NOR] flash (we don't want to copy it
- ;; to DRAM before unpacking), or copied to DRAM
- ;; by the [NAND] flash boot loader.
- ;; The piggyback image is at _edata, but relative to where the
- ;; image is actually located in memory, not where it is linked
- ;; (the decompressor is linked at 0x40700000+ and runs there).
- ;; Use (_edata - herami) as offset to the current PC.
-
-hereami:
- lapcq ., $r5 ; get PC
- and.d 0x7fffffff, $r5 ; strip any non-cache bit
- move.d $r5, $r0 ; source address of 'herami'
- add.d _edata, $r5
- sub.d hereami, $r5 ; r5 = flash address of '_edata'
- move.d hereami, $r1 ; destination
-
- ;; Copy text+data to DRAM
-
- move.d _edata, $r2 ; end destination
-1: move.w [$r0+], $r3 ; from herami+ source
- move.w $r3, [$r1+] ; to hereami+ destination (linked address)
- cmp.d $r2, $r1 ; finish when destination == _edata
- bcs 1b
- nop
- move.d input_data, $r0 ; for the decompressor
- move.d $r5, [$r0] ; for the decompressor
-
- ;; Clear the decompressors BSS (between _edata and _end)
-
- moveq 0, $r0
- move.d _edata, $r1
- move.d _end, $r2
-1: move.w $r0, [$r1+]
- cmp.d $r2, $r1
- bcs 1b
- nop
-
- ;; Save command line magic and address.
- move.d _cmd_line_magic, $r0
- move.d $r10, [$r0]
- move.d _cmd_line_addr, $r0
- move.d $r11, [$r0]
-
- ;; Save boot source indicator
- move.d _boot_source, $r0
- move.d $r12, [$r0]
-
- ;; Do the decompression and save compressed size in _inptr
-
- jsr decompress_kernel
- nop
-
- ;; Restore boot source indicator
- move.d _boot_source, $r12
- move.d [$r12], $r12
-
- ;; Restore command line magic and address.
- move.d _cmd_line_magic, $r10
- move.d [$r10], $r10
- move.d _cmd_line_addr, $r11
- move.d [$r11], $r11
-
- ;; Put start address of root partition in r9 so the kernel can use it
- ;; when mounting from flash
- move.d input_data, $r0
- move.d [$r0], $r9 ; flash address of compressed kernel
- move.d inptr, $r0
- add.d [$r0], $r9 ; size of compressed kernel
- cmp.d 0x40000000, $r9 ; image in DRAM ?
- blo enter_kernel ; no, must be [NOR] flash, jump
- nop ; delay slot
- and.d 0x001fffff, $r9 ; assume compressed kernel was < 2M
-
-enter_kernel:
- ;; Enter the decompressed kernel
- move.d RAM_INIT_MAGIC, $r8 ; Tell kernel that DRAM is initialized
- jump 0x40004000 ; kernel is linked to this address
- nop
-
- .data
-
-input_data:
- .dword 0 ; used by the decompressor
-_cmd_line_magic:
- .dword 0
-_cmd_line_addr:
- .dword 0
-_boot_source:
- .dword 0
-
-#if defined CONFIG_ETRAXFS
-#include "../../arch-v32/mach-fs/hw_settings.S"
-#elif defined CONFIG_CRIS_MACH_ARTPEC3
-#include "../../arch-v32/mach-a3/hw_settings.S"
-#else
-#error Only ETRAXFS and ARTPEC-3 supported!
-#endif
diff --git a/arch/cris/boot/compressed/misc.c b/arch/cris/boot/compressed/misc.c
deleted file mode 100644
index 1ad464a117b8..000000000000
--- a/arch/cris/boot/compressed/misc.c
+++ /dev/null
@@ -1,377 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * misc.c
- *
- * This is a collection of several routines from gzip-1.0.3
- * adapted for Linux.
- *
- * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
- * puts by Nick Holloway 1993, better puts by Martin Mares 1995
- * adaptation for Linux/CRIS Axis Communications AB, 1999
- *
- */
-
-/* where the piggybacked kernel image expects itself to live.
- * it is the same address we use when we network load an uncompressed
- * image into DRAM, and it is the address the kernel is linked to live
- * at by vmlinux.lds.S
- */
-
-#define KERNEL_LOAD_ADR 0x40004000
-
-#include <linux/types.h>
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/reg_map.h>
-#include <hwregs/ser_defs.h>
-#include <hwregs/pinmux_defs.h>
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#include <hwregs/clkgen_defs.h>
-#endif
-#else
-#include <arch/svinto.h>
-#endif
-
-/*
- * gzip declarations
- */
-
-#define OF(args) args
-#define STATIC static
-
-void *memset(void *s, int c, size_t n);
-void *memcpy(void *__dest, __const void *__src, size_t __n);
-
-#define memzero(s, n) memset((s), 0, (n))
-
-typedef unsigned char uch;
-typedef unsigned short ush;
-typedef unsigned long ulg;
-
-#define WSIZE 0x8000 /* Window size must be at least 32k, */
- /* and a power of two */
-
-static uch *inbuf; /* input buffer */
-static uch window[WSIZE]; /* Sliding window buffer */
-
-unsigned inptr = 0; /* index of next byte to be processed in inbuf
- * After decompression it will contain the
- * compressed size, and head.S will read it.
- */
-
-static unsigned outcnt = 0; /* bytes in output buffer */
-
-/* gzip flag byte */
-#define ASCII_FLAG 0x01 /* bit 0 set: file probably ascii text */
-#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
-#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
-#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
-#define COMMENT 0x10 /* bit 4 set: file comment present */
-#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
-#define RESERVED 0xC0 /* bit 6,7: reserved */
-
-#define get_byte() (inbuf[inptr++])
-
-/* Diagnostic functions */
-#ifdef DEBUG
-# define Assert(cond, msg) do { \
- if (!(cond)) \
- error(msg); \
- } while (0)
-# define Trace(x) fprintf x
-# define Tracev(x) do { \
- if (verbose) \
- fprintf x; \
- } while (0)
-# define Tracevv(x) do { \
- if (verbose > 1) \
- fprintf x; \
- } while (0)
-# define Tracec(c, x) do { \
- if (verbose && (c)) \
- fprintf x; \
- } while (0)
-# define Tracecv(c, x) do { \
- if (verbose > 1 && (c)) \
- fprintf x; \
- } while (0)
-#else
-# define Assert(cond, msg)
-# define Trace(x)
-# define Tracev(x)
-# define Tracevv(x)
-# define Tracec(c, x)
-# define Tracecv(c, x)
-#endif
-
-static void flush_window(void);
-static void error(char *m);
-static void aputs(const char *s);
-
-extern char *input_data; /* lives in head.S */
-
-static long bytes_out;
-static uch *output_data;
-static unsigned long output_ptr;
-
-/* the "heap" is put directly after the BSS ends, at end */
-
-extern int _end;
-static long free_mem_ptr = (long)&_end;
-static long free_mem_end_ptr;
-
-#include "../../../../../lib/inflate.c"
-
-/* decompressor info and error messages to serial console */
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-static inline void serout(const char *s, reg_scope_instances regi_ser)
-{
- reg_ser_rs_stat_din rs;
- reg_ser_rw_dout dout = {.data = *s};
-
- do {
- rs = REG_RD(ser, regi_ser, rs_stat_din);
- }
- while (!rs.tr_rdy);/* Wait for transceiver. */
-
- REG_WR(ser, regi_ser, rw_dout, dout);
-}
-#define SEROUT(S, N) \
- do { \
- serout(S, regi_ser ## N); \
- s++; \
- } while (0)
-#else
-#define SEROUT(S, N) do { \
- while (!(*R_SERIAL ## N ## _STATUS & (1 << 5))) \
- ; \
- *R_SERIAL ## N ## _TR_DATA = *s++; \
- } while (0)
-#endif
-
-static void aputs(const char *s)
-{
-#ifndef CONFIG_ETRAX_DEBUG_PORT_NULL
- while (*s) {
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- SEROUT(s, 0);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT1
- SEROUT(s, 1);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT2
- SEROUT(s, 2);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT3
- SEROUT(s, 3);
-#endif
- }
-#endif /* CONFIG_ETRAX_DEBUG_PORT_NULL */
-}
-
-void *memset(void *s, int c, size_t n)
-{
- int i;
- char *ss = (char*)s;
-
- for (i=0;i<n;i++) ss[i] = c;
-
- return s;
-}
-
-void *memcpy(void *__dest, __const void *__src, size_t __n)
-{
- int i;
- char *d = (char *)__dest, *s = (char *)__src;
-
- for (i = 0; i < __n; i++)
- d[i] = s[i];
-
- return __dest;
-}
-
-/* ===========================================================================
- * Write the output window window[0..outcnt-1] and update crc and bytes_out.
- * (Used for the decompressed data only.)
- */
-
-static void flush_window(void)
-{
- ulg c = crc; /* temporary variable */
- unsigned n;
- uch *in, *out, ch;
-
- in = window;
- out = &output_data[output_ptr];
- for (n = 0; n < outcnt; n++) {
- ch = *out = *in;
- out++;
- in++;
- c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
- }
- crc = c;
- bytes_out += (ulg)outcnt;
- output_ptr += (ulg)outcnt;
- outcnt = 0;
-}
-
-static void error(char *x)
-{
- aputs("\n\n");
- aputs(x);
- aputs("\n\n -- System halted\n");
-
- while(1); /* Halt */
-}
-
-void setup_normal_output_buffer(void)
-{
- output_data = (char *)KERNEL_LOAD_ADR;
-}
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-static inline void serial_setup(reg_scope_instances regi_ser)
-{
- reg_ser_rw_xoff xoff;
- reg_ser_rw_tr_ctrl tr_ctrl;
- reg_ser_rw_rec_ctrl rec_ctrl;
- reg_ser_rw_tr_baud_div tr_baud;
- reg_ser_rw_rec_baud_div rec_baud;
-
- /* Turn off XOFF. */
- xoff = REG_RD(ser, regi_ser, rw_xoff);
-
- xoff.chr = 0;
- xoff.automatic = regk_ser_no;
-
- REG_WR(ser, regi_ser, rw_xoff, xoff);
-
- /* Set baudrate and stopbits. */
- tr_ctrl = REG_RD(ser, regi_ser, rw_tr_ctrl);
- rec_ctrl = REG_RD(ser, regi_ser, rw_rec_ctrl);
- tr_baud = REG_RD(ser, regi_ser, rw_tr_baud_div);
- rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div);
-
- tr_ctrl.stop_bits = 1; /* 2 stop bits. */
- tr_ctrl.en = 1; /* enable transmitter */
- rec_ctrl.en = 1; /* enabler receiver */
-
- /*
- * The baudrate setup used to be a bit fishy, but now transmitter and
- * receiver are both set to the intended baud rate, 115200.
- * The magic value is 29.493 MHz.
- */
- tr_ctrl.base_freq = regk_ser_f29_493;
- rec_ctrl.base_freq = regk_ser_f29_493;
- tr_baud.div = (29493000 / 8) / 115200;
- rec_baud.div = (29493000 / 8) / 115200;
-
- REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
- REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud);
- REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl);
- REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud);
-}
-#endif
-
-void decompress_kernel(void)
-{
- char revision;
- char compile_rev;
-
-#ifdef CONFIG_ETRAX_ARCH_V32
- /* Need at least a CRISv32 to run. */
- compile_rev = 32;
-#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \
- defined(CONFIG_ETRAX_DEBUG_PORT2) || \
- defined(CONFIG_ETRAX_DEBUG_PORT3)
- reg_pinmux_rw_hwprot hwprot;
-
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
- reg_clkgen_rw_clk_ctrl clk_ctrl;
-
- /* Enable corresponding clock region when serial 1..3 selected */
-
- clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
- clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
- REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
-#endif
-
- /* pinmux setup for ports 1..3 */
- hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
-#endif
-
-
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- serial_setup(regi_ser0);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT1
- hwprot.ser1 = regk_pinmux_yes;
- serial_setup(regi_ser1);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT2
- hwprot.ser2 = regk_pinmux_yes;
- serial_setup(regi_ser2);
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT3
- hwprot.ser3 = regk_pinmux_yes;
- serial_setup(regi_ser3);
-#endif
-#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \
- defined(CONFIG_ETRAX_DEBUG_PORT2) || \
- defined(CONFIG_ETRAX_DEBUG_PORT3)
- REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
-#endif
-
- /* input_data is set in head.S */
- inbuf = input_data;
-#else /* CRISv10 */
- /* Need at least a crisv10 to run. */
- compile_rev = 10;
-
- /* input_data is set in head.S */
- inbuf = input_data;
-
-#ifdef CONFIG_ETRAX_DEBUG_PORT0
- *R_SERIAL0_XOFF = 0;
- *R_SERIAL0_BAUD = 0x99;
- *R_SERIAL0_TR_CTRL = 0x40;
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT1
- *R_SERIAL1_XOFF = 0;
- *R_SERIAL1_BAUD = 0x99;
- *R_SERIAL1_TR_CTRL = 0x40;
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT2
- *R_GEN_CONFIG = 0x08;
- *R_SERIAL2_XOFF = 0;
- *R_SERIAL2_BAUD = 0x99;
- *R_SERIAL2_TR_CTRL = 0x40;
-#endif
-#ifdef CONFIG_ETRAX_DEBUG_PORT3
- *R_GEN_CONFIG = 0x100;
- *R_SERIAL3_XOFF = 0;
- *R_SERIAL3_BAUD = 0x99;
- *R_SERIAL3_TR_CTRL = 0x40;
-#endif
-#endif
-
- setup_normal_output_buffer();
-
- makecrc();
-
- __asm__ volatile ("move $vr,%0" : "=rm" (revision));
- if (revision < compile_rev) {
-#ifdef CONFIG_ETRAX_ARCH_V32
- aputs("You need at least ETRAX FS to run Linux 2.6/crisv32\n");
-#else
- aputs("You need an ETRAX 100LX to run linux 2.6/crisv10\n");
-#endif
- while(1);
- }
-
- aputs("Uncompressing Linux...\n");
- gunzip();
- aputs("Done. Now booting the kernel\n");
-}
diff --git a/arch/cris/boot/dts/Makefile b/arch/cris/boot/dts/Makefile
deleted file mode 100644
index 118fe990a173..000000000000
--- a/arch/cris/boot/dts/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o
-ifneq ($(CONFIG_BUILTIN_DTB),"")
-obj-$(CONFIG_OF) += $(BUILTIN_DTB)
-endif
diff --git a/arch/cris/boot/dts/artpec3.dtsi b/arch/cris/boot/dts/artpec3.dtsi
deleted file mode 100644
index f857300f4edd..000000000000
--- a/arch/cris/boot/dts/artpec3.dtsi
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "axis,crisv32";
- reg = <0>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- model = "artpec3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- intc: interrupt-controller {
- compatible = "axis,crisv32-intc";
- reg = <0xb002a000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- gio: gpio@b0020000 {
- compatible = "axis,artpec3-gio";
- reg = <0xb0020000 0x1000>;
- interrupts = <61>;
- gpio-controller;
- #gpio-cells = <3>;
- };
-
- serial@b003e000 {
- compatible = "axis,etraxfs-uart";
- reg = <0xb003e000 0x1000>;
- interrupts = <64>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/cris/boot/dts/dev88.dts b/arch/cris/boot/dts/dev88.dts
deleted file mode 100644
index 415270ea5309..000000000000
--- a/arch/cris/boot/dts/dev88.dts
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-
-/include/ "etraxfs.dtsi"
-
-/ {
- model = "Axis 88 Developer Board";
- compatible = "axis,dev88";
-
- aliases {
- serial0 = &uart0;
- };
-
- soc {
- uart0: serial@b00260000 {
- status = "okay";
- };
- };
-
- spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&gio 1 0 0xd>;
- gpio-miso = <&gio 4 0 0xd>;
- gpio-mosi = <&gio 0 0 0xd>;
- cs-gpios = <&gio 3 0 0xd>;
- num-chipselects = <1>;
-
- temp-sensor@0 {
- compatible = "ti,lm70";
- reg = <0>;
-
- spi-max-frequency = <100000>;
- };
- };
-
- i2c {
- compatible = "i2c-gpio";
- gpios = <&gio 5 0 0xd>, <&gio 6 0 0xd>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- network {
- label = "network";
- gpios = <&gio 2 GPIO_ACTIVE_LOW 0xa>;
- };
-
- status {
- label = "status";
- gpios = <&gio 3 GPIO_ACTIVE_LOW 0xa>;
- linux,default-trigger = "heartbeat";
- };
- };
-};
diff --git a/arch/cris/boot/dts/etraxfs.dtsi b/arch/cris/boot/dts/etraxfs.dtsi
deleted file mode 100644
index 4513edf72545..000000000000
--- a/arch/cris/boot/dts/etraxfs.dtsi
+++ /dev/null
@@ -1,47 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "axis,crisv32";
- reg = <0>;
- };
- };
-
- soc {
- compatible = "simple-bus";
- model = "etraxfs";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- intc: interrupt-controller {
- compatible = "axis,crisv32-intc";
- reg = <0xb001c000 0x1000>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- gio: gpio@b001a000 {
- compatible = "axis,etraxfs-gio";
- reg = <0xb001a000 0x1000>;
- interrupts = <50>;
- gpio-controller;
- #gpio-cells = <3>;
- };
-
- serial@b00260000 {
- compatible = "axis,etraxfs-uart";
- reg = <0xb0026000 0x1000>;
- interrupts = <68>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/cris/boot/dts/p1343.dts b/arch/cris/boot/dts/p1343.dts
deleted file mode 100644
index 6030561d4574..000000000000
--- a/arch/cris/boot/dts/p1343.dts
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/include/ "artpec3.dtsi"
-
-/ {
- model = "Axis P1343 Network Camera";
- compatible = "axis,p1343";
-
- aliases {
- serial0 = &uart0;
- };
-
- soc {
- uart0: serial@b003e000 {
- status = "okay";
- };
- };
-
- i2c {
- compatible = "i2c-gpio";
- gpios = <&gio 3 0 0xa>, <&gio 2 0 0xa>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_green {
- label = "status:green";
- gpios = <&gio 0 GPIO_ACTIVE_LOW 0xc>;
- linux,default-trigger = "heartbeat";
- };
-
- status_red {
- label = "status:red";
- gpios = <&gio 1 GPIO_ACTIVE_LOW 0xc>;
- };
-
- network_green {
- label = "network:green";
- gpios = <&gio 2 GPIO_ACTIVE_LOW 0xc>;
- };
-
- network_red {
- label = "network:red";
- gpios = <&gio 3 GPIO_ACTIVE_LOW 0xc>;
- };
-
- power_red {
- label = "power:red";
- gpios = <&gio 4 GPIO_ACTIVE_LOW 0xc>;
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- activity-button@0 {
- label = "Activity Button";
- linux,code = <KEY_FN>;
- gpios = <&gio 13 GPIO_ACTIVE_LOW 0xd>;
- };
- };
-};
diff --git a/arch/cris/boot/rescue/Makefile b/arch/cris/boot/rescue/Makefile
deleted file mode 100644
index f73ac4c83b96..000000000000
--- a/arch/cris/boot/rescue/Makefile
+++ /dev/null
@@ -1,53 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for rescue (bootstrap) code
-#
-
-# CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE)
-# ccflags-$(CONFIG_ETRAX_ARCH_V32) += -I$(srctree)/include/asm/arch/mach/ \
-# -I$(srctree)/include/asm/arch
-# asflags-y += -I $(srctree)/include/asm/arch/mach/ -I $(srctree)/include/asm/arch
-# LD = gcc-cris -mlinux -march=v32 -nostdlib
-
-ifdef CONFIG_ETRAX_AXISFLASHMAP
-
-arch-$(CONFIG_ETRAX_ARCH_V10) = v10
-arch-$(CONFIG_ETRAX_ARCH_V32) = v32
-
-ldflags-y += -T $(srctree)/$(src)/rescue_$(arch-y).lds
-OBJCOPYFLAGS = -O binary --remove-section=.bss
-obj-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o
-obj-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o
-OBJECTS := $(obj-y)
-
-targets := rescue.o rescue.bin
-
-$(obj)/rescue.o: $(OBJECTS) FORCE
- $(call if_changed,ld)
-
-$(obj)/rescue.bin: $(obj)/rescue.o FORCE
- $(call if_changed,objcopy)
- cp -p $(obj)/rescue.bin $(objtree)
-
-else
-$(obj)/rescue.bin:
-
-endif
-
-$(obj)/testrescue.bin: $(obj)/testrescue.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/testrescue.o tr.bin
-# Pad it to 784 bytes
- dd if=/dev/zero of=tmp2423 bs=1 count=784
- cat tr.bin tmp2423 >testrescue_tmp.bin
- dd if=testrescue_tmp.bin of=$(obj)/testrescue.bin bs=1 count=784
- rm tr.bin tmp2423 testrescue_tmp.bin
-
-
-$(obj)/kimagerescue.bin: $(obj)/kimagerescue.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/kimagerescue.o ktr.bin
-# Pad it to 784 bytes, that's what the rescue loader expects
- dd if=/dev/zero of=tmp2423 bs=1 count=784
- cat ktr.bin tmp2423 >kimagerescue_tmp.bin
- dd if=kimagerescue_tmp.bin of=$(obj)/kimagerescue.bin bs=1 count=784
- rm ktr.bin tmp2423 kimagerescue_tmp.bin
-
diff --git a/arch/cris/boot/rescue/head_v10.S b/arch/cris/boot/rescue/head_v10.S
deleted file mode 100644
index 11eedb1bf31a..000000000000
--- a/arch/cris/boot/rescue/head_v10.S
+++ /dev/null
@@ -1,358 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Rescue code, made to reside at the beginning of the
- * flash-memory. when it starts, it checks a partition
- * table at the first sector after the rescue sector.
- * the partition table was generated by the product builder
- * script and contains offsets, lengths, types and checksums
- * for each partition that this code should check.
- *
- * If any of the checksums fail, we assume the flash is so
- * corrupt that we can't use it to boot into the ftp flash
- * loader, and instead we initialize the serial port to
- * receive a flash-loader and new flash image. we dont include
- * any flash code here, but just accept a certain amount of
- * bytes from the serial port and jump into it. the downloaded
- * code is put in the cache.
- *
- * The partitiontable is designed so that it is transparent to
- * code execution - it has a relative branch opcode in the
- * beginning that jumps over it. each entry contains extra
- * data so we can add stuff later.
- *
- * Partition table format:
- *
- * Code transparency:
- *
- * 2 bytes [opcode 'nop']
- * 2 bytes [opcode 'di']
- * 4 bytes [opcode 'ba <offset>', 8-bit or 16-bit version]
- * 2 bytes [opcode 'nop', delay slot]
- *
- * Table validation (at +10):
- *
- * 2 bytes [magic/version word for partitiontable - 0xef, 0xbe]
- * 2 bytes [length of all entries plus the end marker]
- * 4 bytes [checksum for the partitiontable itself]
- *
- * Entries, each with the following format, last has offset -1:
- *
- * 4 bytes [offset in bytes, from start of flash]
- * 4 bytes [length in bytes of partition]
- * 4 bytes [checksum, simple longword sum]
- * 2 bytes [partition type]
- * 2 bytes [flags, only bit 0 used, ro/rw = 1/0]
- * 16 bytes [reserved for future use]
- *
- * End marker
- *
- * 4 bytes [-1]
- *
- * 10 bytes [0, padding]
- *
- * Bit 0 in flags signifies RW or RO. The rescue code only bothers
- * to check the checksum for RO partitions, since the others will
- * change their data without updating the checksums. A 1 in bit 0
- * means RO, 0 means RW. That way, it is possible to set a partition
- * in RO mode initially, and later mark it as RW, since you can always
- * write 0's to the flash.
- *
- * During the wait for serial input, the status LED will flash so the
- * user knows something went wrong.
- *
- * Copyright (C) 1999-2007 Axis Communications AB
- */
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
- ;; The partitiontable is looked for at the first sector after the boot
- ;; sector. Sector size is 65536 bytes in all flashes we use.
-
-#define PTABLE_START CONFIG_ETRAX_PTABLE_SECTOR
-#define PTABLE_MAGIC 0xbeef
-
- ;; The normal Etrax100 on-chip boot ROM does serial boot at 0x380000f0.
- ;; That is not where we put our downloaded serial boot-code.
- ;; The length is enough for downloading code that loads the rest
- ;; of itself (after having setup the DRAM etc).
- ;; It is the same length as the on-chip ROM loads, so the same
- ;; host loader can be used to load a rescued product as well as
- ;; one booted through the Etrax serial boot code.
-
-#define CODE_START 0x40000000
-#define CODE_LENGTH 784
-
-#ifdef CONFIG_ETRAX_RESCUE_SER0
-#define SERXOFF R_SERIAL0_XOFF
-#define SERBAUD R_SERIAL0_BAUD
-#define SERRECC R_SERIAL0_REC_CTRL
-#define SERRDAT R_SERIAL0_REC_DATA
-#define SERSTAT R_SERIAL0_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER1
-#define SERXOFF R_SERIAL1_XOFF
-#define SERBAUD R_SERIAL1_BAUD
-#define SERRECC R_SERIAL1_REC_CTRL
-#define SERRDAT R_SERIAL1_REC_DATA
-#define SERSTAT R_SERIAL1_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER2
-#define SERXOFF R_SERIAL2_XOFF
-#define SERBAUD R_SERIAL2_BAUD
-#define SERRECC R_SERIAL2_REC_CTRL
-#define SERRDAT R_SERIAL2_REC_DATA
-#define SERSTAT R_SERIAL2_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER3
-#define SERXOFF R_SERIAL3_XOFF
-#define SERBAUD R_SERIAL3_BAUD
-#define SERRECC R_SERIAL3_REC_CTRL
-#define SERRDAT R_SERIAL3_REC_DATA
-#define SERSTAT R_SERIAL3_STATUS
-#endif
-
-#define NOP_DI 0xf025050f
-#define RAM_INIT_MAGIC 0x56902387
-
- .text
-
- ;; This is the entry point of the rescue code
- ;; 0x80000000 if loaded in flash (as it should be)
- ;; Since etrax actually starts at address 2 when booting from flash, we
- ;; put a nop (2 bytes) here first so we dont accidentally skip the di
-
- nop
- di
-
- jump in_cache ; enter cached area instead
-in_cache:
-
-
- ;; First put a jump test to give a possibility of upgrading the
- ;; rescue code without erasing/reflashing the sector.
- ;; We put a longword of -1 here and if it is not -1, we jump using
- ;; the value as jump target. Since we can always change 1's to 0's
- ;; without erasing the sector, it is possible to add new
- ;; code after this and altering the jumptarget in an upgrade.
-
-jtcd: move.d [jumptarget], $r0
- cmp.d 0xffffffff, $r0
- beq no_newjump
- nop
-
- jump [$r0]
-
-jumptarget:
- .dword 0xffffffff ; can be overwritten later to insert new code
-
-no_newjump:
-#ifdef CONFIG_ETRAX_ETHERNET
- ;; Start MII clock to make sure it is running when tranceiver is reset
- move.d 0x3, $r0 ; enable = on, phy = mii_clk
- move.d $r0, [R_NETWORK_GEN_CONFIG]
-#endif
-
- ;; We need to setup the bus registers before we start using the DRAM
-#include "../../../arch-v10/lib/dram_init.S"
-
- ;; we now should go through the checksum-table and check the listed
- ;; partitions for errors.
-
- move.d PTABLE_START, $r3
- move.d [$r3], $r0
- cmp.d NOP_DI, $r0 ; make sure the nop/di is there...
- bne do_rescue
- nop
-
- ;; skip the code transparency block (10 bytes).
-
- addq 10, $r3
-
- ;; check for correct magic
-
- move.w [$r3+], $r0
- cmp.w PTABLE_MAGIC, $r0
- bne do_rescue ; didn't recognize - trig rescue
- nop
-
- ;; check for correct ptable checksum
-
- movu.w [$r3+], $r2 ; ptable length
- move.d $r2, $r8 ; save for later, length of total ptable
- addq 28, $r8 ; account for the rest
- move.d [$r3+], $r4 ; ptable checksum
- move.d $r3, $r1
- jsr checksum ; r1 source, r2 length, returns in r0
-
- cmp.d $r0, $r4
- bne do_rescue ; didn't match - trig rescue
- nop
-
- ;; ptable is ok. validate each entry.
-
- moveq -1, $r7
-
-ploop: move.d [$r3+], $r1 ; partition offset (from ptable start)
- bne notfirst ; check if it is the partition containing ptable
- nop ; yes..
- move.d $r8, $r1 ; for its checksum check, skip the ptable
- move.d [$r3+], $r2 ; partition length
- sub.d $r8, $r2 ; minus the ptable length
- ba bosse
- nop
-notfirst:
- cmp.d -1, $r1 ; the end of the ptable ?
- beq flash_ok ; if so, the flash is validated
- move.d [$r3+], $r2 ; partition length
-bosse: move.d [$r3+], $r5 ; checksum
- move.d [$r3+], $r4 ; type and flags
- addq 16, $r3 ; skip the reserved bytes
- btstq 16, $r4 ; check ro flag
- bpl ploop ; rw partition, skip validation
- nop
- btstq 17, $r4 ; check bootable flag
- bpl 1f
- nop
- move.d $r1, $r7 ; remember boot partition offset
-1:
- add.d PTABLE_START, $r1
-
- jsr checksum ; checksum the partition
-
- cmp.d $r0, $r5
- beq ploop ; checksums matched, go to next entry
- nop
-
- ;; otherwise fall through to the rescue code.
-
-do_rescue:
- ;; setup port PA and PB default initial directions and data
- ;; (so we can flash LEDs, and so that DTR and others are set)
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
- move.b $r0, [R_PORT_PA_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
- move.b $r0, [R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
- move.b $r0, [R_PORT_PB_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
- move.b $r0, [R_PORT_PB_DATA]
-
- ;; setup the serial port at 115200 baud
-
- moveq 0, $r0
- move.d $r0, [SERXOFF]
-
- move.b 0x99, $r0
- move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit and receive
-
- move.b 0x40, $r0 ; rec enable
- move.b $r0, [SERRECC]
-
- moveq 0, $r1 ; "timer" to clock out a LED red flash
- move.d CODE_START, $r3 ; destination counter
- movu.w CODE_LENGTH, $r4; length
-
-wait_ser:
- addq 1, $r1
-#ifndef CONFIG_ETRAX_NO_LEDS
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2
-#endif
- move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0
- btstq 16, $r1
- bpl 1f
- nop
- or.d $r0, $r2 ; set bit
- ba 2f
- nop
-1: not $r0 ; clear bit
- and.d $r0, $r2
-2:
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b $r2, [R_PORT_PA_DATA]
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b $r2, [R_PORT_PB_DATA]
-#endif
-#endif
-
- ;; check if we got something on the serial port
-
- move.b [SERSTAT], $r0
- btstq 0, $r0 ; data_avail
- bpl wait_ser
- nop
-
- ;; got something - copy the byte and loop
-
- move.b [SERRDAT], $r0
- move.b $r0, [$r3+]
-
- subq 1, $r4 ; decrease length
- bne wait_ser
- nop
-
- ;; jump into downloaded code
-
- move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is
- ; initialized
- jump CODE_START
-
-flash_ok:
- ;; check r7, which contains either -1 or the partition to boot from
-
- cmp.d -1, $r7
- bne 1f
- nop
- move.d PTABLE_START, $r7; otherwise use the ptable start
-1:
- move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is
- ; initialized
- jump $r7 ; boot!
-
-
- ;; Helper subroutines
-
- ;; Will checksum by simple addition
- ;; r1 - source
- ;; r2 - length in bytes
- ;; result will be in r0
-checksum:
- moveq 0, $r0
- moveq CONFIG_ETRAX_FLASH1_SIZE, $r6
-
- ;; If the first physical flash memory is exceeded wrap to the
- ;; second one
- btstq 26, $r1 ; Are we addressing first flash?
- bpl 1f
- nop
- clear.d $r6
-
-1: test.d $r6 ; 0 = no wrapping
- beq 2f
- nop
- lslq 20, $r6 ; Convert MB to bytes
- sub.d $r1, $r6
-
-2: addu.b [$r1+], $r0
- subq 1, $r6 ; Flash memory left
- beq 3f
- subq 1, $r2 ; Length left
- bne 2b
- nop
- ret
- nop
-
-3: move.d MEM_CSE1_START, $r1 ; wrap to second flash
- ba 2b
- nop
-
-#endif
diff --git a/arch/cris/boot/rescue/head_v32.S b/arch/cris/boot/rescue/head_v32.S
deleted file mode 100644
index 9eb04abaa0c0..000000000000
--- a/arch/cris/boot/rescue/head_v32.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Just get started by jumping to CONFIG_ETRAX_PTABLE_SECTOR to start
- * kernel decompressor.
- *
- * In practice, this only works for NOR flash (or some convoluted RAM boot)
- * and hence is not really useful for Artpec-3, so it's Etrax FS / NOR only.
- *
- */
-
-#include <mach/startup.inc>
-
-#ifdef CONFIG_ETRAX_AXISFLASHMAP
-
-;; Code
-
- .text
-start:
-
- ;; Start clocks for used blocks.
- START_CLOCKS
-
- move.d CONFIG_ETRAX_PTABLE_SECTOR, $r10
- jump $r10 ; Jump to decompressor
- nop
-
-#endif
diff --git a/arch/cris/boot/rescue/kimagerescue.S b/arch/cris/boot/rescue/kimagerescue.S
deleted file mode 100644
index 3306098dee15..000000000000
--- a/arch/cris/boot/rescue/kimagerescue.S
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Rescue code to be prepended on a kimage and copied to the
- * rescue serial port.
- * This is called from the rescue code, it will copy received data to
- * 4004000 and after a timeout jump to it.
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
-#define CODE_START 0x40004000
-#define CODE_LENGTH 784
-#define TIMEOUT_VALUE 1000
-
-
-#ifdef CONFIG_ETRAX_RESCUE_SER0
-#define SERXOFF R_SERIAL0_XOFF
-#define SERBAUD R_SERIAL0_BAUD
-#define SERRECC R_SERIAL0_REC_CTRL
-#define SERRDAT R_SERIAL0_REC_DATA
-#define SERSTAT R_SERIAL0_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER1
-#define SERXOFF R_SERIAL1_XOFF
-#define SERBAUD R_SERIAL1_BAUD
-#define SERRECC R_SERIAL1_REC_CTRL
-#define SERRDAT R_SERIAL1_REC_DATA
-#define SERSTAT R_SERIAL1_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER2
-#define SERXOFF R_SERIAL2_XOFF
-#define SERBAUD R_SERIAL2_BAUD
-#define SERRECC R_SERIAL2_REC_CTRL
-#define SERRDAT R_SERIAL2_REC_DATA
-#define SERSTAT R_SERIAL2_STATUS
-#endif
-#ifdef CONFIG_ETRAX_RESCUE_SER3
-#define SERXOFF R_SERIAL3_XOFF
-#define SERBAUD R_SERIAL3_BAUD
-#define SERRECC R_SERIAL3_REC_CTRL
-#define SERRDAT R_SERIAL3_REC_DATA
-#define SERSTAT R_SERIAL3_STATUS
-#endif
-
- .text
- ;; This is the entry point of the rescue code
- ;; 0x80000000 if loaded in flash (as it should be)
- ;; since etrax actually starts at address 2 when booting from flash, we
- ;; put a nop (2 bytes) here first so we dont accidentally skip the di
-
- nop
- di
- ;; setup port PA and PB default initial directions and data
- ;; (so we can flash LEDs, and so that DTR and others are set)
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
- move.b $r0, [R_PORT_PA_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
- move.b $r0, [R_PORT_PA_DATA]
-
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
- move.b $r0, [R_PORT_PB_DIR]
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
- move.b $r0, [R_PORT_PB_DATA]
-
- ;; We need to setup the bus registers before we start using the DRAM
-#include "../../lib/dram_init.S"
-
- ;; Setup the stack to a suitably high address.
- ;; We assume 8 MB is the minimum DRAM in an eLinux
- ;; product and put the sp at the top for now.
-
- move.d 0x40800000, $sp
-
- ;; setup the serial port at 115200 baud
-
- moveq 0, $r0
- move.d $r0, [SERXOFF]
-
- move.b 0x99, $r0
- move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit
- ; and receive
-
- move.b 0x40, $r0 ; rec enable
- move.b $r0, [SERRECC]
-
-
- moveq 0, $r1 ; "timer" to clock out a LED red flash
- move.d CODE_START, $r3 ; destination counter
- move.d CODE_LENGTH, $r4 ; length
- move.d TIMEOUT_VALUE, $r5 ; "timeout" until jump
-
-wait_ser:
- addq 1, $r1
- subq 1, $r5 ; decrease timeout
- beq jump_start ; timed out
- nop
-#ifndef CONFIG_ETRAX_NO_LEDS
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r2
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r2
-#endif
- move.d (1 << CONFIG_ETRAX_LED1R) | (1 << CONFIG_ETRAX_LED2R), $r0
- btstq 16, $r1
- bpl 1f
- nop
- or.d $r0, $r2 ; set bit
- ba 2f
- nop
-1: not $r0 ; clear bit
- and.d $r0, $r2
-2:
-#ifdef CONFIG_ETRAX_PA_LEDS
- move.b $r2, [R_PORT_PA_DATA]
-#endif
-#ifdef CONFIG_ETRAX_PB_LEDS
- move.b $r2, [R_PORT_PB_DATA]
-#endif
-#endif
-
- ;; check if we got something on the serial port
-
- move.b [SERSTAT], $r0
- btstq 0, $r0 ; data_avail
- bpl wait_ser
- nop
-
- ;; got something - copy the byte and loop
-
- move.b [SERRDAT], $r0
- move.b $r0, [$r3+]
- move.d TIMEOUT_VALUE, $r5 ; reset "timeout"
- subq 1, $r4 ; decrease length
- bne wait_ser
- nop
-jump_start:
- ;; jump into downloaded code
-
- jump CODE_START
diff --git a/arch/cris/boot/rescue/rescue_v10.lds b/arch/cris/boot/rescue/rescue_v10.lds
deleted file mode 100644
index e58a53f91728..000000000000
--- a/arch/cris/boot/rescue/rescue_v10.lds
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-MEMORY
- {
- flash : ORIGIN = 0x00000000,
- LENGTH = 0x00100000
- }
-
-SECTIONS
-{
- .text :
- {
- stext = . ;
- *(.text)
- etext = . ;
- } > flash
- .data :
- {
- *(.data)
- edata = . ;
- } > flash
-}
diff --git a/arch/cris/boot/rescue/rescue_v32.lds b/arch/cris/boot/rescue/rescue_v32.lds
deleted file mode 100644
index f1542183f263..000000000000
--- a/arch/cris/boot/rescue/rescue_v32.lds
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*#OUTPUT_FORMAT(elf32-us-cris) */
-OUTPUT_ARCH (crisv32)
-/* Now that NAND support has been stripped, this file could be simplified,
- * but it doesn't do any harm on the other hand so why bother. */
-
-MEMORY
- {
- bootblk : ORIGIN = 0x38000000,
- LENGTH = 0x00004000
- intmem : ORIGIN = 0x38004000,
- LENGTH = 0x00005000
- }
-
-SECTIONS
-{
- .text :
- {
- _stext = . ;
- *(.text)
- *(.init.text)
- *(.rodata)
- *(.rodata.*)
- _etext = . ;
- } > bootblk
- .data :
- {
- *(.data)
- _edata = . ;
- } > bootblk
- .bss :
- {
- _bss = . ;
- *(.bss)
- _end = ALIGN( 0x10 ) ;
- } > intmem
-
- /* Get rid of stuff from EXPORT_SYMBOL(foo). */
- /DISCARD/ :
- {
- *(__ksymtab_strings)
- *(__ksymtab)
- }
-}
diff --git a/arch/cris/boot/rescue/testrescue.S b/arch/cris/boot/rescue/testrescue.S
deleted file mode 100644
index 06f78a0b0622..000000000000
--- a/arch/cris/boot/rescue/testrescue.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Simple testcode to download by the rescue block.
- * Just lights some LEDs to show it was downloaded correctly.
- *
- * Copyright (C) 1999 Axis Communications AB
- */
-
-#define ASSEMBLER_MACROS_ONLY
-#include <arch/sv_addr_ag.h>
-
- .text
-
- nop
- nop
- moveq -1, $r2
- move.b $r2, [R_PORT_PA_DIR]
- moveq 0, $r2
- move.b $r2, [R_PORT_PA_DATA]
-
-endless:
- nop
- ba endless
- nop
-
diff --git a/arch/cris/boot/tools/build.c b/arch/cris/boot/tools/build.c
deleted file mode 100644
index 3ae485049779..000000000000
--- a/arch/cris/boot/tools/build.c
+++ /dev/null
@@ -1,288 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/tools/build.c
- *
- * Copyright (C) 1991, 1992 Linus Torvalds
- */
-
-/*
- * This file builds a disk-image from three different files:
- *
- * - bootsect: exactly 512 bytes of 8086 machine code, loads the rest
- * - setup: 8086 machine code, sets up system parm
- * - system: 80386 code for actual system
- *
- * It does some checking that all files are of the correct type, and
- * just writes the result to stdout, removing headers and padding to
- * the right amount. It also writes some system data to stderr.
- */
-
-/*
- * Changes by tytso to allow root device specification
- * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
- * Cross compiling fixes by Gertjan van Wingerde, July 1996
- */
-
-#include <stdio.h> /* fprintf */
-#include <string.h>
-#include <stdlib.h> /* contains exit */
-#include <sys/types.h> /* unistd.h needs this */
-#include <sys/stat.h>
-#include <sys/sysmacros.h>
-#include <unistd.h> /* contains read/write */
-#include <fcntl.h>
-#include <errno.h>
-
-#define MINIX_HEADER 32
-
-#define N_MAGIC_OFFSET 1024
-#ifndef __BFD__
-static int GCC_HEADER = sizeof(struct exec);
-#endif
-
-#ifdef __BIG_KERNEL__
-#define SYS_SIZE 0xffff
-#else
-#define SYS_SIZE DEF_SYSSIZE
-#endif
-
-#define DEFAULT_MAJOR_ROOT 0
-#define DEFAULT_MINOR_ROOT 0
-
-/* max nr of sectors of setup: don't change unless you also change
- * bootsect etc */
-#define SETUP_SECTS 4
-
-#define STRINGIFY(x) #x
-
-typedef union {
- int i;
- long l;
- short s[2];
- char b[4];
-} conv;
-
-long intel_long(long l)
-{
- conv t;
-
- t.b[0] = l & 0xff; l >>= 8;
- t.b[1] = l & 0xff; l >>= 8;
- t.b[2] = l & 0xff; l >>= 8;
- t.b[3] = l & 0xff; l >>= 8;
- return t.l;
-}
-
-int intel_int(int i)
-{
- conv t;
-
- t.b[0] = i & 0xff; i >>= 8;
- t.b[1] = i & 0xff; i >>= 8;
- t.b[2] = i & 0xff; i >>= 8;
- t.b[3] = i & 0xff; i >>= 8;
- return t.i;
-}
-
-short intel_short(short l)
-{
- conv t;
-
- t.b[0] = l & 0xff; l >>= 8;
- t.b[1] = l & 0xff; l >>= 8;
- return t.s[0];
-}
-
-void die(const char * str)
-{
- fprintf(stderr,"%s\n",str);
- exit(1);
-}
-
-void usage(void)
-{
- die("Usage: build bootsect setup system [rootdev] [> image]");
-}
-
-int main(int argc, char ** argv)
-{
- int i,c,id,sz,tmp_int;
- unsigned long sys_size, tmp_long;
- char buf[1024];
-#ifndef __BFD__
- struct exec *ex = (struct exec *)buf;
-#endif
- char major_root, minor_root;
- struct stat sb;
- unsigned char setup_sectors;
-
- if ((argc < 4) || (argc > 5))
- usage();
- if (argc > 4) {
- if (!strcmp(argv[4], "CURRENT")) {
- if (stat("/", &sb)) {
- perror("/");
- die("Couldn't stat /");
- }
- major_root = major(sb.st_dev);
- minor_root = minor(sb.st_dev);
- } else if (strcmp(argv[4], "FLOPPY")) {
- if (stat(argv[4], &sb)) {
- perror(argv[4]);
- die("Couldn't stat root device.");
- }
- major_root = major(sb.st_rdev);
- minor_root = minor(sb.st_rdev);
- } else {
- major_root = 0;
- minor_root = 0;
- }
- } else {
- major_root = DEFAULT_MAJOR_ROOT;
- minor_root = DEFAULT_MINOR_ROOT;
- }
- fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
- for (i=0;i<sizeof buf; i++) buf[i]=0;
- if ((id=open(argv[1],O_RDONLY,0))<0)
- die("Unable to open 'boot'");
- if (read(id,buf,MINIX_HEADER) != MINIX_HEADER)
- die("Unable to read header of 'boot'");
- if (((long *) buf)[0]!=intel_long(0x04100301))
- die("Non-Minix header of 'boot'");
- if (((long *) buf)[1]!=intel_long(MINIX_HEADER))
- die("Non-Minix header of 'boot'");
- if (((long *) buf)[3] != 0)
- die("Illegal data segment in 'boot'");
- if (((long *) buf)[4] != 0)
- die("Illegal bss in 'boot'");
- if (((long *) buf)[5] != 0)
- die("Non-Minix header of 'boot'");
- if (((long *) buf)[7] != 0)
- die("Illegal symbol table in 'boot'");
- i=read(id,buf,sizeof buf);
- fprintf(stderr,"Boot sector %d bytes.\n",i);
- if (i != 512)
- die("Boot block must be exactly 512 bytes");
- if ((*(unsigned short *)(buf+510)) != (unsigned short)intel_short(0xAA55))
- die("Boot block hasn't got boot flag (0xAA55)");
- buf[508] = (char) minor_root;
- buf[509] = (char) major_root;
- i=write(1,buf,512);
- if (i!=512)
- die("Write call failed");
- close (id);
-
- if ((id=open(argv[2],O_RDONLY,0))<0)
- die("Unable to open 'setup'");
- if (read(id,buf,MINIX_HEADER) != MINIX_HEADER)
- die("Unable to read header of 'setup'");
- if (((long *) buf)[0]!=intel_long(0x04100301))
- die("Non-Minix header of 'setup'");
- if (((long *) buf)[1]!=intel_long(MINIX_HEADER))
- die("Non-Minix header of 'setup'");
- if (((long *) buf)[3] != 0)
- die("Illegal data segment in 'setup'");
- if (((long *) buf)[4] != 0)
- die("Illegal bss in 'setup'");
- if (((long *) buf)[5] != 0)
- die("Non-Minix header of 'setup'");
- if (((long *) buf)[7] != 0)
- die("Illegal symbol table in 'setup'");
- for (i=0 ; (c=read(id,buf,sizeof buf))>0 ; i+=c )
-#ifdef __BIG_KERNEL__
- {
- if (!i) {
- /* Working with memcpy because of alignment constraints
- on Sparc - Gertjan */
- memcpy(&tmp_long, &buf[2], sizeof(long));
- if (tmp_long != intel_long(0x53726448) )
- die("Wrong magic in loader header of 'setup'");
- memcpy(&tmp_int, &buf[6], sizeof(int));
- if (tmp_int < intel_int(0x200))
- die("Wrong version of loader header of 'setup'");
- buf[0x11] = 1; /* LOADED_HIGH */
- tmp_long = intel_long(0x100000);
- memcpy(&buf[0x14], &tmp_long, sizeof(long)); /* code32_start */
- }
-#endif
- if (write(1,buf,c)!=c)
- die("Write call failed");
-#ifdef __BIG_KERNEL__
- }
-#endif
- if (c != 0)
- die("read-error on 'setup'");
- close (id);
- setup_sectors = (unsigned char)((i + 511) / 512);
- /* for compatibility with LILO */
- if (setup_sectors < SETUP_SECTS)
- setup_sectors = SETUP_SECTS;
- fprintf(stderr,"Setup is %d bytes.\n",i);
- for (c=0 ; c<sizeof(buf) ; c++)
- buf[c] = '\0';
- while (i < setup_sectors * 512) {
- c = setup_sectors * 512 - i;
- if (c > sizeof(buf))
- c = sizeof(buf);
- if (write(1,buf,c) != c)
- die("Write call failed");
- i += c;
- }
-
- if ((id=open(argv[3],O_RDONLY,0))<0)
- die("Unable to open 'system'");
-#ifndef __BFD__
- if (read(id,buf,GCC_HEADER) != GCC_HEADER)
- die("Unable to read header of 'system'");
- if (N_MAGIC(*ex) == ZMAGIC) {
- GCC_HEADER = N_MAGIC_OFFSET;
- lseek(id, GCC_HEADER, SEEK_SET);
- } else if (N_MAGIC(*ex) != QMAGIC)
- die("Non-GCC header of 'system'");
- fprintf(stderr,"System is %d kB (%d kB code, %d kB data and %d kB bss)\n",
- (ex->a_text+ex->a_data+ex->a_bss)/1024,
- ex->a_text /1024,
- ex->a_data /1024,
- ex->a_bss /1024);
- sz = N_SYMOFF(*ex) - GCC_HEADER + 4;
-#else
- if (fstat (id, &sb)) {
- perror ("fstat");
- die ("Unable to stat 'system'");
- }
- sz = sb.st_size;
- fprintf (stderr, "System is %d kB\n", sz/1024);
-#endif
- sys_size = (sz + 15) / 16;
- if (sys_size > SYS_SIZE)
- die("System is too big");
- while (sz > 0) {
- int l, n;
-
- l = sz;
- if (l > sizeof(buf))
- l = sizeof(buf);
- if ((n=read(id, buf, l)) != l) {
- if (n == -1)
- perror(argv[1]);
- else
- fprintf(stderr, "Unexpected EOF\n");
- die("Can't read 'system'");
- }
- if (write(1, buf, l) != l)
- die("Write failed");
- sz -= l;
- }
- close(id);
- if (lseek(1, 497, 0) == 497) {
- if (write(1, &setup_sectors, 1) != 1)
- die("Write of setup sectors failed");
- }
- if (lseek(1,500,0) == 500) {
- buf[0] = (sys_size & 0xff);
- buf[1] = ((sys_size >> 8) & 0xff);
- if (write(1, buf, 2) != 2)
- die("Write failed");
- }
- return(0);
-}
diff --git a/arch/cris/configs/artpec_3_defconfig b/arch/cris/configs/artpec_3_defconfig
deleted file mode 100644
index d31851f29db8..000000000000
--- a/arch/cris/configs/artpec_3_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_CRIS_MACH_ARTPEC3=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_MTDRAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ETRAX_GPIO=y
diff --git a/arch/cris/configs/dev88_defconfig b/arch/cris/configs/dev88_defconfig
deleted file mode 100644
index beff4ee6edb3..000000000000
--- a/arch/cris/configs/dev88_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_BUILTIN_DTB="dev88"
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_ETRAXFS=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_ETRAX_MEM_GRP1_CONFIG=0x40688
-CONFIG_ETRAX_MEM_GRP3_CONFIG=0x3
-CONFIG_ETRAX_MEM_GRP4_CONFIG=0x10040
-CONFIG_ETRAX_SDRAM_GRP0_CONFIG=0x958
-CONFIG_ETRAX_SDRAM_TIMING=0x824a
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_DEVTMPFS=y
-CONFIG_MTD_RAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_ETRAXFS=y
-CONFIG_SERIAL_ETRAXFS_CONSOLE=y
-CONFIG_GPIO_ETRAXFS=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
diff --git a/arch/cris/configs/etrax-100lx_defconfig b/arch/cris/configs/etrax-100lx_defconfig
deleted file mode 100644
index cbbcefeaa8fc..000000000000
--- a/arch/cris/configs/etrax-100lx_defconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_ETRAX_LED1R=2
-CONFIG_ETRAX_LED2G=2
-CONFIG_ETRAX_LED2R=2
-CONFIG_ETRAX_DEF_R_PORT_PA_DIR=1d
-CONFIG_ETRAX_DEF_R_PORT_PA_DATA=f0
-CONFIG_ETRAX_DEF_R_PORT_PB_DIR=1e
-CONFIG_ETRAX_DEF_R_PORT_PB_DATA=f3
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_SERIAL=y
-CONFIG_ETRAX_SERIAL_PORT0=y
-CONFIG_ETRAX_SERIAL_PORT1=y
-CONFIG_ETRAX_I2C=y
-CONFIG_ETRAX_I2C_USES_PB_NOT_PB_I2C=y
-CONFIG_ETRAX_GPIO=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_NETDEVICES=y
-CONFIG_CRAMFS=y
diff --git a/arch/cris/configs/etrax-100lx_v2_defconfig b/arch/cris/configs/etrax-100lx_v2_defconfig
deleted file mode 100644
index d90ac95c1e44..000000000000
--- a/arch/cris/configs/etrax-100lx_v2_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_ETRAX100LX_V2=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_ETRAX_DEBUG_PORT_NULL=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_SERIAL=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_MTDRAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
diff --git a/arch/cris/configs/etraxfs_defconfig b/arch/cris/configs/etraxfs_defconfig
deleted file mode 100644
index f714e9dfef9b..000000000000
--- a/arch/cris/configs/etraxfs_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
-CONFIG_ETRAX_FAST_TIMER=y
-CONFIG_ETRAXFS=y
-CONFIG_ETRAX_DRAM_SIZE=32
-CONFIG_ETRAX_FLASH1_SIZE=4
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_ETRAX_ETHERNET=y
-CONFIG_ETRAX_AXISFLASHMAP=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_MTDRAM=y
-CONFIG_MTDRAM_TOTAL_SIZE=0
-CONFIG_MTDRAM_ERASE_SIZE=64
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ETRAX_GPIO=y
diff --git a/arch/cris/include/arch-v10/arch/bitops.h b/arch/cris/include/arch-v10/arch/bitops.h
deleted file mode 100644
index c18f81858899..000000000000
--- a/arch/cris/include/arch-v10/arch/bitops.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* asm/arch/bitops.h for Linux/CRISv10 */
-
-#ifndef _CRIS_ARCH_BITOPS_H
-#define _CRIS_ARCH_BITOPS_H
-
-/*
- * Helper functions for the core of the ff[sz] functions, wrapping the
- * syntactically awkward asms. The asms compute the number of leading
- * zeroes of a bits-in-byte and byte-in-word and word-in-dword-swapped
- * number. They differ in that the first function also inverts all bits
- * in the input.
- */
-static inline unsigned long cris_swapnwbrlz(unsigned long w)
-{
- /* Let's just say we return the result in the same register as the
- input. Saying we clobber the input but can return the result
- in another register:
- ! __asm__ ("swapnwbr %2\n\tlz %2,%0"
- ! : "=r,r" (res), "=r,X" (dummy) : "1,0" (w));
- confuses gcc (core.c, gcc from cris-dist-1.14). */
-
- unsigned long res;
- __asm__ ("swapnwbr %0 \n\t"
- "lz %0,%0"
- : "=r" (res) : "0" (w));
- return res;
-}
-
-static inline unsigned long cris_swapwbrlz(unsigned long w)
-{
- unsigned res;
- __asm__ ("swapwbr %0 \n\t"
- "lz %0,%0"
- : "=r" (res)
- : "0" (w));
- return res;
-}
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long w)
-{
- return cris_swapnwbrlz(w);
-}
-
-/**
- * __ffs - find first bit in word.
- * @word: The word to search
- *
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
- return cris_swapnwbrlz(~word);
-}
-
-/**
- * ffs - find first bit set
- * @x: the word to search
- *
- * This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-
-static inline unsigned long kernel_ffs(unsigned long w)
-{
- return w ? cris_swapwbrlz (w) + 1 : 0;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/bug.h b/arch/cris/include/arch-v10/arch/bug.h
deleted file mode 100644
index 06da9d49152a..000000000000
--- a/arch/cris/include/arch-v10/arch/bug.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRISv10_ARCH_BUG_H
-#define __ASM_CRISv10_ARCH_BUG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_BUG
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-/* The BUG() macro is used for marking obviously incorrect code paths.
- * It will cause a message with the file name and line number to be printed,
- * and then cause an oops. The message is actually printed by handle_BUG()
- * in arch/cris/kernel/traps.c, and the reason we use this method of storing
- * the file name and line number is that we do not want to affect the registers
- * by calling printk() before causing the oops.
- */
-
-#define BUG_PREFIX 0x0D7F
-#define BUG_MAGIC 0x00001234
-
-struct bug_frame {
- unsigned short prefix;
- unsigned int magic;
- unsigned short clear;
- unsigned short movu;
- unsigned short line;
- unsigned short jump;
- unsigned char *filename;
-};
-
-#if 0
-/* Unfortunately this version of the macro does not work due to a problem
- * with the compiler (aka a bug) when compiling with -O2, which sometimes
- * erroneously causes the second input to be stored in a register...
- */
-#define BUG() \
- __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
- "movu.w %0,$r0\n\t" \
- "jump %1\n\t" \
- : : "i" (__LINE__), "i" (__FILE__))
-#else
-/* This version will have to do for now, until the compiler is fixed.
- * The drawbacks of this version are that the file name will appear multiple
- * times in the .rodata section, and that __LINE__ and __FILE__ can probably
- * not be used like this with newer versions of gcc.
- */
-#define BUG() \
-do { \
- __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
- "movu.w " __stringify(__LINE__) ",$r0\n\t"\
- "jump 0f\n\t" \
- ".section .rodata\n" \
- "0:\t.string \"" __FILE__ "\"\n\t" \
- ".previous"); \
- unreachable(); \
-} while (0)
-#endif
-
-#else
-
-/* This just causes an oops. */
-#define BUG() \
-do { \
- barrier_before_unreachable(); \
- __builtin_trap(); \
-} while (0)
-
-#endif
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/cache.h b/arch/cris/include/arch-v10/arch/cache.h
deleted file mode 100644
index d4049bcab3c5..000000000000
--- a/arch/cris/include/arch-v10/arch/cache.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CACHE_H
-#define _ASM_ARCH_CACHE_H
-
-/* Etrax 100LX have 32-byte cache-lines. */
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-
-#endif /* _ASM_ARCH_CACHE_H */
diff --git a/arch/cris/include/arch-v10/arch/checksum.h b/arch/cris/include/arch-v10/arch/checksum.h
deleted file mode 100644
index eb186be4fb32..000000000000
--- a/arch/cris/include/arch-v10/arch/checksum.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_CHECKSUM_H
-#define _CRIS_ARCH_CHECKSUM_H
-
-/* Checksum some values used in TCP/UDP headers.
- *
- * The gain by doing this in asm is that C will not generate carry-additions
- * for the 32-bit components of the checksum, so otherwise we would have had
- * to split all of those into 16-bit components, then add.
- */
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- __wsum res;
- __asm__ ("add.d %2, %0\n\t"
- "ax\n\t"
- "add.d %3, %0\n\t"
- "ax\n\t"
- "add.d %4, %0\n\t"
- "ax\n\t"
- "addq 0, %0\n"
- : "=r" (res)
- : "0" (sum), "r" (daddr), "r" (saddr), "r" ((len + proto) << 8));
-
- return res;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/delay.h b/arch/cris/include/arch-v10/arch/delay.h
deleted file mode 100644
index a57d2cc0baf7..000000000000
--- a/arch/cris/include/arch-v10/arch/delay.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_DELAY_H
-#define _CRIS_ARCH_DELAY_H
-
-static inline void __delay(int loops)
-{
- __asm__ __volatile__ (
- "move.d %0,$r9\n\t"
- "beq 2f\n\t"
- "subq 1,$r9\n\t"
- "1:\n\t"
- "bne 1b\n\t"
- "subq 1,$r9\n"
- "2:"
- : : "g" (loops) : "r9");
-}
-
-#endif /* defined(_CRIS_ARCH_DELAY_H) */
-
-
-
diff --git a/arch/cris/include/arch-v10/arch/dma.h b/arch/cris/include/arch-v10/arch/dma.h
deleted file mode 100644
index ea794a32cf5e..000000000000
--- a/arch/cris/include/arch-v10/arch/dma.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Defines for using and allocating dma channels. */
-
-#ifndef _ASM_ARCH_DMA_H
-#define _ASM_ARCH_DMA_H
-
-#define MAX_DMA_CHANNELS 10
-
-/* dma0 and dma1 used for network (ethernet) */
-#define NETWORK_TX_DMA_NBR 0
-#define NETWORK_RX_DMA_NBR 1
-
-/* dma2 and dma3 shared by par0, scsi0, ser2 and ata */
-#define PAR0_TX_DMA_NBR 2
-#define PAR0_RX_DMA_NBR 3
-#define SCSI0_TX_DMA_NBR 2
-#define SCSI0_RX_DMA_NBR 3
-#define SER2_TX_DMA_NBR 2
-#define SER2_RX_DMA_NBR 3
-#define ATA_TX_DMA_NBR 2
-#define ATA_RX_DMA_NBR 3
-
-/* dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
-#define PAR1_TX_DMA_NBR 4
-#define PAR1_RX_DMA_NBR 5
-#define SCSI1_TX_DMA_NBR 4
-#define SCSI1_RX_DMA_NBR 5
-#define SER3_TX_DMA_NBR 4
-#define SER3_RX_DMA_NBR 5
-#define EXTDMA0_TX_DMA_NBR 4
-#define EXTDMA0_RX_DMA_NBR 5
-
-/* dma6 and dma7 shared by ser0, extdma1 and mem2mem */
-#define SER0_TX_DMA_NBR 6
-#define SER0_RX_DMA_NBR 7
-#define EXTDMA1_TX_DMA_NBR 6
-#define EXTDMA1_RX_DMA_NBR 7
-#define MEM2MEM_TX_DMA_NBR 6
-#define MEM2MEM_RX_DMA_NBR 7
-
-/* dma8 and dma9 shared by ser1 and usb */
-#define SER1_TX_DMA_NBR 8
-#define SER1_RX_DMA_NBR 9
-#define USB_TX_DMA_NBR 8
-#define USB_RX_DMA_NBR 9
-
-#endif
-
-enum dma_owner
-{
- dma_eth,
- dma_ser0,
- dma_ser1, /* Async and sync */
- dma_ser2,
- dma_ser3, /* Async and sync */
- dma_ata,
- dma_par0,
- dma_par1,
- dma_ext0,
- dma_ext1,
- dma_int6,
- dma_int7,
- dma_usb,
- dma_scsi0,
- dma_scsi1
-};
-
-/* Masks used by cris_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR (1<<0)
-#define DMA_PANIC_ON_ERROR ((1<<1)|DMA_VERBOSE_ON_ERROR)
-
-int cris_request_dma(unsigned int dmanr, const char * device_id,
- unsigned options, enum dma_owner owner);
-
-void cris_free_dma(unsigned int dmanr, const char * device_id);
diff --git a/arch/cris/include/arch-v10/arch/io.h b/arch/cris/include/arch-v10/arch/io.h
deleted file mode 100644
index bae5f77cfabc..000000000000
--- a/arch/cris/include/arch-v10/arch/io.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CRIS_IO_H
-#define _ASM_ARCH_CRIS_IO_H
-
-/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
-
-extern unsigned long gen_config_ii_shadow;
-extern unsigned long port_g_data_shadow;
-extern unsigned char port_pa_dir_shadow;
-extern unsigned char port_pa_data_shadow;
-extern unsigned char port_pb_i2c_shadow;
-extern unsigned char port_pb_config_shadow;
-extern unsigned char port_pb_dir_shadow;
-extern unsigned char port_pb_data_shadow;
-extern unsigned long r_timer_ctrl_shadow;
-
-extern unsigned long port_cse1_shadow;
-extern unsigned long port_csp0_shadow;
-extern unsigned long port_csp4_shadow;
-
-extern volatile unsigned long *port_cse1_addr;
-extern volatile unsigned long *port_csp0_addr;
-extern volatile unsigned long *port_csp4_addr;
-
-/* macro for setting regs through a shadow -
- * r = register name (like R_PORT_PA_DATA)
- * s = shadow name (like port_pa_data_shadow)
- * b = bit number
- * v = value (0 or 1)
- */
-
-#define REG_SHADOW_SET(r,s,b,v) *r = s = (s & ~(1 << (b))) | ((v) << (b))
-
-/* The LED's on various Etrax-based products are set differently. */
-
-#if defined(CONFIG_ETRAX_NO_LEDS)
-#undef CONFIG_ETRAX_PA_LEDS
-#undef CONFIG_ETRAX_PB_LEDS
-#undef CONFIG_ETRAX_CSP0_LEDS
-#define CRIS_LED_NETWORK_SET_G(x)
-#define CRIS_LED_NETWORK_SET_R(x)
-#define CRIS_LED_ACTIVE_SET_G(x)
-#define CRIS_LED_ACTIVE_SET_R(x)
-#define CRIS_LED_DISK_WRITE(x)
-#define CRIS_LED_DISK_READ(x)
-#endif
-
-#if !defined(CONFIG_ETRAX_CSP0_LEDS)
-#define CRIS_LED_BIT_SET(x)
-#define CRIS_LED_BIT_CLR(x)
-#endif
-
-#define CRIS_LED_OFF 0x00
-#define CRIS_LED_GREEN 0x01
-#define CRIS_LED_RED 0x02
-#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
-
-#if defined(CONFIG_ETRAX_NO_LEDS)
-#define CRIS_LED_NETWORK_SET(x)
-#else
-#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R
-#define CRIS_LED_NETWORK_SET(x) \
- do { \
- CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
- } while (0)
-#else
-#define CRIS_LED_NETWORK_SET(x) \
- do { \
- CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
- CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \
- } while (0)
-#endif
-#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R
-#define CRIS_LED_ACTIVE_SET(x) \
- do { \
- CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
- } while (0)
-#else
-#define CRIS_LED_ACTIVE_SET(x) \
- do { \
- CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
- CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
- } while (0)
-#endif
-#endif
-
-#ifdef CONFIG_ETRAX_PA_LEDS
-#define CRIS_LED_NETWORK_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
- do{\
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
- }while(0)
-#define CRIS_LED_DISK_READ(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \
- CONFIG_ETRAX_LED3G, !(x))
-#endif
-
-#ifdef CONFIG_ETRAX_PB_LEDS
-#define CRIS_LED_NETWORK_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
- do{\
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
- }while(0)
-#define CRIS_LED_DISK_READ(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \
- CONFIG_ETRAX_LED3G, !(x))
-#endif
-
-#ifdef CONFIG_ETRAX_CSP0_LEDS
-#define CONFIGURABLE_LEDS\
- ((1 << CONFIG_ETRAX_LED1G ) | (1 << CONFIG_ETRAX_LED1R ) |\
- (1 << CONFIG_ETRAX_LED2G ) | (1 << CONFIG_ETRAX_LED2R ) |\
- (1 << CONFIG_ETRAX_LED3G ) | (1 << CONFIG_ETRAX_LED3R ) |\
- (1 << CONFIG_ETRAX_LED4G ) | (1 << CONFIG_ETRAX_LED4R ) |\
- (1 << CONFIG_ETRAX_LED5G ) | (1 << CONFIG_ETRAX_LED5R ) |\
- (1 << CONFIG_ETRAX_LED6G ) | (1 << CONFIG_ETRAX_LED6R ) |\
- (1 << CONFIG_ETRAX_LED7G ) | (1 << CONFIG_ETRAX_LED7R ) |\
- (1 << CONFIG_ETRAX_LED8Y ) | (1 << CONFIG_ETRAX_LED9Y ) |\
- (1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\
- (1 << CONFIG_ETRAX_LED12R ))
-
-#define CRIS_LED_NETWORK_SET_G(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define CRIS_LED_NETWORK_SET_R(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define CRIS_LED_ACTIVE_SET_G(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define CRIS_LED_ACTIVE_SET_R(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define CRIS_LED_DISK_WRITE(x) \
- do{\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\
- }while(0)
-#define CRIS_LED_DISK_READ(x) \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x))
-#define CRIS_LED_BIT_SET(x)\
- do{\
- if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\
- }while(0)
-#define CRIS_LED_BIT_CLR(x)\
- do{\
- if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\
- }while(0)
-#endif
-
-#
-#ifdef CONFIG_ETRAX_SOFT_SHUTDOWN
-#define SOFT_SHUTDOWN() \
- REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_SHUTDOWN_BIT, 1)
-#else
-#define SOFT_SHUTDOWN()
-#endif
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/io_interface_mux.h b/arch/cris/include/arch-v10/arch/io_interface_mux.h
deleted file mode 100644
index 2d5617e67ab0..000000000000
--- a/arch/cris/include/arch-v10/arch/io_interface_mux.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* IO interface mux allocator for ETRAX100LX.
- * Copyright 2004, Axis Communications AB
- * $Id: io_interface_mux.h,v 1.1 2004/12/13 12:21:53 starvik Exp $
- */
-
-
-#ifndef _IO_INTERFACE_MUX_H
-#define _IO_INTERFACE_MUX_H
-
-
-/* C.f. ETRAX100LX Designer's Reference 20.9 */
-
-/* The order in enum must match the order of interfaces[] in
- * io_interface_mux.c */
-enum cris_io_interface {
- /* Begin Non-multiplexed interfaces */
- if_eth = 0,
- if_serial_0,
- /* End Non-multiplexed interfaces */
- if_serial_1,
- if_serial_2,
- if_serial_3,
- if_sync_serial_1,
- if_sync_serial_3,
- if_shared_ram,
- if_shared_ram_w,
- if_par_0,
- if_par_1,
- if_par_w,
- if_scsi8_0,
- if_scsi8_1,
- if_scsi_w,
- if_ata,
- if_csp,
- if_i2c,
- if_usb_1,
- if_usb_2,
- /* GPIO pins */
- if_gpio_grp_a,
- if_gpio_grp_b,
- if_gpio_grp_c,
- if_gpio_grp_d,
- if_gpio_grp_e,
- if_gpio_grp_f,
- if_max_interfaces,
- if_unclaimed
-};
-
-int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id);
-
-void cris_free_io_interface(enum cris_io_interface ioif);
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit);
-
-/* port can be 'a', 'b' or 'g' */
-int cris_io_interface_free_pins(const enum cris_io_interface ioif,
- const char port,
- const unsigned start_bit,
- const unsigned stop_bit);
-
-int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available));
-
-void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available));
-
-#endif /* _IO_INTERFACE_MUX_H */
diff --git a/arch/cris/include/arch-v10/arch/irq.h b/arch/cris/include/arch-v10/arch/irq.h
deleted file mode 100644
index c4e8a78e33d1..000000000000
--- a/arch/cris/include/arch-v10/arch/irq.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Interrupt handling assembler and defines for Linux/CRISv10
- */
-
-#ifndef _ASM_ARCH_IRQ_H
-#define _ASM_ARCH_IRQ_H
-
-#include <arch/sv_addr_ag.h>
-
-#define NR_IRQS 32
-
-/* The first vector number used for IRQs in v10 is really 0x20 */
-/* but all the code and constants are offseted to make 0 the first */
-#define FIRST_IRQ 0
-
-#define SOME_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, some) /* 0 ? */
-#define NMI_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, nmi) /* 1 */
-#define TIMER0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer0) /* 2 */
-#define TIMER1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, timer1) /* 3 */
-/* mio, ata, par0, scsi0 on 4 */
-/* par1, scsi1 on 5 */
-#define NETWORK_STATUS_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, network) /* 6 */
-
-#define SERIAL_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, serial) /* 8 */
-#define PA_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, pa) /* 11 */
-/* extdma0 and extdma1 is at irq 12 and 13 and/or same as dma5 and dma6 ? */
-#define EXTDMA0_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma0)
-#define EXTDMA1_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, ext_dma1)
-
-/* dma0-9 is irq 16..25 */
-/* 16,17: network */
-#define DMA0_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma0)
-#define DMA1_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma1)
-#define NETWORK_DMA_TX_IRQ_NBR DMA0_TX_IRQ_NBR
-#define NETWORK_DMA_RX_IRQ_NBR DMA1_RX_IRQ_NBR
-
-/* 18,19: dma2 and dma3 shared by par0, scsi0, ser2 and ata */
-#define DMA2_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma2)
-#define DMA3_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma3)
-#define SER2_DMA_TX_IRQ_NBR DMA2_TX_IRQ_NBR
-#define SER2_DMA_RX_IRQ_NBR DMA3_RX_IRQ_NBR
-
-/* 20,21: dma4 and dma5 shared by par1, scsi1, ser3 and extdma0 */
-#define DMA4_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma4)
-#define DMA5_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma5)
-#define SER3_DMA_TX_IRQ_NBR DMA4_TX_IRQ_NBR
-#define SER3_DMA_RX_IRQ_NBR DMA5_RX_IRQ_NBR
-
-/* 22,23: dma6 and dma7 shared by ser0, extdma1 and mem2mem */
-#define DMA6_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma6)
-#define DMA7_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma7)
-#define SER0_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
-#define SER0_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
-#define MEM2MEM_DMA_TX_IRQ_NBR DMA6_TX_IRQ_NBR
-#define MEM2MEM_DMA_RX_IRQ_NBR DMA7_RX_IRQ_NBR
-
-/* 24,25: dma8 and dma9 shared by ser1 and usb */
-#define DMA8_TX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma8)
-#define DMA9_RX_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, dma9)
-#define SER1_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
-#define SER1_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
-#define USB_DMA_TX_IRQ_NBR DMA8_TX_IRQ_NBR
-#define USB_DMA_RX_IRQ_NBR DMA9_RX_IRQ_NBR
-
-/* usb: controller at irq 31 + uses DMA8 and DMA9 */
-#define USB_HC_IRQ_NBR IO_BITNR(R_VECT_MASK_RD, usb)
-
-/* our fine, global, etrax irq vector! the pointer lives in the head.S file. */
-
-typedef void (*irqvectptr)(void);
-
-struct etrax_interrupt_vector {
- irqvectptr v[256];
-};
-
-extern struct etrax_interrupt_vector *etrax_irv;
-void set_int_vector(int n, irqvectptr addr);
-void set_break_vector(int n, irqvectptr addr);
-
-#define __STR(x) #x
-#define STR(x) __STR(x)
-
-/* SAVE_ALL saves registers so they match pt_regs */
-
-#define SAVE_ALL \
- "move $irp,[$sp=$sp-16]\n\t" /* push instruction pointer and fake SBFS struct */ \
- "push $srp\n\t" /* push subroutine return pointer */ \
- "push $dccr\n\t" /* push condition codes */ \
- "push $mof\n\t" /* push multiply overflow reg */ \
- "di\n\t" /* need to disable irq's at this point */\
- "subq 14*4,$sp\n\t" /* make room for r0-r13 */ \
- "movem $r13,[$sp]\n\t" /* push the r0-r13 registers */ \
- "push $r10\n\t" /* push orig_r10 */ \
- "clear.d [$sp=$sp-4]\n\t" /* frametype - this is a normal stackframe */
-
-/* BLOCK_IRQ and UNBLOCK_IRQ do the same as
- * crisv10_mask_irq and crisv10_unmask_irq */
-
-#define BLOCK_IRQ(mask,nr) \
- "move.d " #mask ",$r0\n\t" \
- "move.d $r0,[0xb00000d8]\n\t"
-
-#define UNBLOCK_IRQ(mask) \
- "move.d " #mask ",$r0\n\t" \
- "move.d $r0,[0xb00000dc]\n\t"
-
-#define IRQ_NAME2(nr) nr##_interrupt(void)
-#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
-#define sIRQ_NAME(nr) IRQ_NAME2(sIRQ##nr)
-#define BAD_IRQ_NAME(nr) IRQ_NAME2(bad_IRQ##nr)
-
- /* the asm IRQ handler makes sure the causing IRQ is blocked, then it calls
- * do_IRQ (with irq disabled still). after that it unblocks and jumps to
- * ret_from_intr (entry.S)
- *
- * The reason the IRQ is blocked is to allow an sti() before the handler which
- * will acknowledge the interrupt is run.
- */
-
-#define BUILD_IRQ(nr,mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- BLOCK_IRQ(mask,nr) /* this must be done to prevent irq loops when we ei later */ \
- "moveq "#nr",$r10\n\t" \
- "move.d $sp,$r11\n\t" \
- "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
- UNBLOCK_IRQ(mask) \
- "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
- "jump ret_from_intr\n\t");
-
-/* This is subtle. The timer interrupt is crucial and it should not be disabled for
- * too long. However, if it had been a normal interrupt as per BUILD_IRQ, it would
- * have been BLOCK'ed, and then softirq's are run before we return here to UNBLOCK.
- * If the softirq's take too much time to run, the timer irq won't run and the
- * watchdog will kill us.
- *
- * Furthermore, if a lot of other irq's occur before we return here, the multiple_irq
- * handler is run and it prioritizes the timer interrupt. However if we had BLOCK'ed
- * it here, we would not get the multiple_irq at all.
- *
- * The non-blocking here is based on the knowledge that the timer interrupt runs
- * with interrupts disabled, and therefore there will not be an sti() before the
- * timer irq handler is run to acknowledge the interrupt.
- */
-
-#define BUILD_TIMER_IRQ(nr,mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- "moveq "#nr",$r10\n\t" \
- "move.d $sp,$r11\n\t" \
- "jsr do_IRQ\n\t" /* irq.c, r10 and r11 are arguments */ \
- "moveq 0,$r9\n\t" /* make ret_from_intr realise we came from an irq */ \
- "jump ret_from_intr\n\t");
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/irqflags.h b/arch/cris/include/arch-v10/arch/irqflags.h
deleted file mode 100644
index 9959b0a8a58c..000000000000
--- a/arch/cris/include/arch-v10/arch/irqflags.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H
-#define __ASM_CRIS_ARCH_IRQFLAGS_H
-
-#include <linux/types.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
- asm volatile("move $ccr,%0" : "=rm" (flags) : : "memory");
- return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
- asm volatile("di" : : : "memory");
-}
-
-static inline void arch_local_irq_enable(void)
-{
- asm volatile("ei" : : : "memory");
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags = arch_local_save_flags();
- arch_local_irq_disable();
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile("move %0,$ccr" : : "rm" (flags) : "memory");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return !(flags & (1 << 5));
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */
diff --git a/arch/cris/include/arch-v10/arch/memmap.h b/arch/cris/include/arch-v10/arch/memmap.h
deleted file mode 100644
index b6b171f48b29..000000000000
--- a/arch/cris/include/arch-v10/arch/memmap.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/mmu.h b/arch/cris/include/arch-v10/arch/mmu.h
deleted file mode 100644
index 74c53048be79..000000000000
--- a/arch/cris/include/arch-v10/arch/mmu.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRIS MMU constants and PTE layout
- */
-
-#ifndef _CRIS_ARCH_MMU_H
-#define _CRIS_ARCH_MMU_H
-
-/* type used in struct mm to couple an MMU context to an active mm */
-
-typedef struct
-{
- unsigned int page_id;
-} mm_context_t;
-
-/* kernel memory segments */
-
-#define KSEG_F 0xf0000000UL
-#define KSEG_E 0xe0000000UL
-#define KSEG_D 0xd0000000UL
-#define KSEG_C 0xc0000000UL
-#define KSEG_B 0xb0000000UL
-#define KSEG_A 0xa0000000UL
-#define KSEG_9 0x90000000UL
-#define KSEG_8 0x80000000UL
-#define KSEG_7 0x70000000UL
-#define KSEG_6 0x60000000UL
-#define KSEG_5 0x50000000UL
-#define KSEG_4 0x40000000UL
-#define KSEG_3 0x30000000UL
-#define KSEG_2 0x20000000UL
-#define KSEG_1 0x10000000UL
-#define KSEG_0 0x00000000UL
-
-/* CRIS PTE bits (see R_TLB_LO in the register description)
- *
- * Bit: 31 30-13 12-------4 3 2 1 0
- * _______________________________________________________
- * | cache |pfn | reserved | global | valid | kernel | we |
- * |_______|____|__________|________|_______|________|_____|
- *
- * (pfn = physical frame number)
- */
-
-/* Real HW-based PTE bits. We use some synonym names so that
- * things become less confusing in combination with the SW-based
- * bits further below.
- *
- */
-
-#define _PAGE_WE (1<<0) /* page is write-enabled */
-#define _PAGE_SILENT_WRITE (1<<0) /* synonym */
-#define _PAGE_KERNEL (1<<1) /* page is kernel only */
-#define _PAGE_VALID (1<<2) /* page is valid */
-#define _PAGE_SILENT_READ (1<<2) /* synonym */
-#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */
-#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */
-
-/* Bits the HW doesn't care about but the kernel uses them in SW */
-
-#define _PAGE_PRESENT (1<<4) /* page present in memory */
-#define _PAGE_ACCESSED (1<<5) /* simulated in software using valid bit */
-#define _PAGE_MODIFIED (1<<6) /* simulated in software using we bit */
-#define _PAGE_READ (1<<7) /* read-enabled */
-#define _PAGE_WRITE (1<<8) /* write-enabled */
-
-/* Define some higher level generic page attributes. */
-
-#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-
-#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
-
-#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
- _PAGE_ACCESSED)
-#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW
-#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
- _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
-
-/*
- * CRIS can't do page protection for execute, and considers read the same.
- * Also, write permissions imply read permissions. This is the closest we can
- * get..
- */
-
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY
-#define __P101 PAGE_READONLY
-#define __P110 PAGE_COPY
-#define __P111 PAGE_COPY
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY
-#define __S101 PAGE_READONLY
-#define __S110 PAGE_SHARED
-#define __S111 PAGE_SHARED
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/offset.h b/arch/cris/include/arch-v10/arch/offset.h
deleted file mode 100644
index 6f0f2b4a163f..000000000000
--- a/arch/cris/include/arch-v10/arch/offset.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_OFFSETS_H__
-#define __ASM_OFFSETS_H__
-/*
- * DO NOT MODIFY.
- *
- * This file was generated by arch/cris/Makefile
- *
- */
-
-#define PT_orig_r10 4 /* offsetof(struct pt_regs, orig_r10) */
-#define PT_r13 8 /* offsetof(struct pt_regs, r13) */
-#define PT_r12 12 /* offsetof(struct pt_regs, r12) */
-#define PT_r11 16 /* offsetof(struct pt_regs, r11) */
-#define PT_r10 20 /* offsetof(struct pt_regs, r10) */
-#define PT_r9 24 /* offsetof(struct pt_regs, r9) */
-#define PT_mof 64 /* offsetof(struct pt_regs, mof) */
-#define PT_dccr 68 /* offsetof(struct pt_regs, dccr) */
-#define PT_srp 72 /* offsetof(struct pt_regs, srp) */
-
-#define TI_task 0 /* offsetof(struct thread_info, task) */
-#define TI_flags 8 /* offsetof(struct thread_info, flags) */
-#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
-
-#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
-#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
-#define THREAD_dccr 8 /* offsetof(struct thread_struct, dccr) */
-
-#define TASK_pid 141 /* offsetof(struct task_struct, pid) */
-
-#define LCLONE_VM 256 /* CLONE_VM */
-#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/page.h b/arch/cris/include/arch-v10/arch/page.h
deleted file mode 100644
index a4bbff64868c..000000000000
--- a/arch/cris/include/arch-v10/arch/page.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_PAGE_H
-#define _CRIS_ARCH_PAGE_H
-
-
-#ifdef __KERNEL__
-
-/* This handles the memory map.. */
-#ifdef CONFIG_CRIS_LOW_MAP
-#define PAGE_OFFSET KSEG_6 /* kseg_6 is mapped to physical ram */
-#else
-#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram */
-#endif
-
-/* macros to convert between really physical and virtual addresses
- * by stripping a selected bit, we can convert between KSEG_x and
- * 0x40000000 where the DRAM really resides
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-/* we have DRAM virtually at 0x6 */
-#define __pa(x) ((unsigned long)(x) & 0xdfffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0x20000000))
-#else
-/* we have DRAM virtually at 0xc */
-#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
-#endif
-
-#endif
-#endif
diff --git a/arch/cris/include/arch-v10/arch/pgtable.h b/arch/cris/include/arch-v10/arch/pgtable.h
deleted file mode 100644
index a61532d06acb..000000000000
--- a/arch/cris/include/arch-v10/arch/pgtable.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_PGTABLE_H
-#define _CRIS_ARCH_PGTABLE_H
-
-/*
- * Kernels own virtual memory area.
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define VMALLOC_START KSEG_7
-#define VMALLOC_END KSEG_8
-#else
-#define VMALLOC_START KSEG_D
-#define VMALLOC_END KSEG_E
-#endif
-
-#endif
-
diff --git a/arch/cris/include/arch-v10/arch/processor.h b/arch/cris/include/arch-v10/arch/processor.h
deleted file mode 100644
index b2df646bc1eb..000000000000
--- a/arch/cris/include/arch-v10/arch/processor.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_PROCESSOR_H
-#define __ASM_CRIS_ARCH_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({void *pc; __asm__ ("move.d $pc,%0" : "=rm" (pc)); pc; })
-
-/* CRIS has no problems with write protection */
-#define wp_works_ok 1
-
-/* CRIS thread_struct. this really has nothing to do with the processor itself, since
- * CRIS does not do any hardware task-switching, but it's here for legacy reasons.
- * The thread_struct here is used when task-switching using _resume defined in entry.S.
- * The offsets here are hardcoded into _resume - if you change this struct, you need to
- * change them as well!!!
-*/
-
-struct thread_struct {
- unsigned long ksp; /* kernel stack pointer */
- unsigned long usp; /* user stack pointer */
- unsigned long dccr; /* saved flag register */
-};
-
-/*
- * User space process size. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-
-#ifdef CONFIG_CRIS_LOW_MAP
-#define TASK_SIZE (0x50000000UL) /* 1.25 GB */
-#else
-#define TASK_SIZE (0xA0000000UL) /* 2.56 GB */
-#endif
-
-#define INIT_THREAD { \
- 0, 0, 0x20 } /* ccr = int enable, nothing else */
-
-#define KSTK_EIP(tsk) \
-({ \
- unsigned long eip = 0; \
- unsigned long regs = (unsigned long)task_pt_regs(tsk); \
- if (regs > PAGE_SIZE && \
- virt_addr_valid(regs)) \
- eip = ((struct pt_regs *)regs)->irp; \
- eip; \
-})
-
-/* give the thread a program location
- * set user-mode (The 'U' flag (User mode flag) is CCR/DCCR bit 8)
- * switch user-stackpointer
- */
-
-#define start_thread(regs, ip, usp) do { \
- regs->irp = ip; \
- regs->dccr |= 1 << U_DCCR_BITNR; \
- wrusp(usp); \
-} while(0)
-
-/* Called when handling a kernel bus fault fixup.
- *
- * After a fixup we do not want to return by restoring the CPU-state
- * anymore, so switch frame-types (see ptrace.h)
- */
-#define arch_fixup(regs) \
- regs->frametype = CRIS_FRAME_NORMAL;
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/swab.h b/arch/cris/include/arch-v10/arch/swab.h
deleted file mode 100644
index 8cc27dfb9d3a..000000000000
--- a/arch/cris/include/arch-v10/arch/swab.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_SWAB_H
-#define _CRIS_ARCH_SWAB_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-#define __SWAB_64_THRU_32__
-
-/* we just define these two (as we can do the swap in a single
- * asm instruction in CRIS) and the arch-independent files will put
- * them together into ntohl etc.
- */
-
-static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
-{
- __asm__ ("swapwb %0" : "=r" (x) : "0" (x));
-
- return(x);
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
-{
- __asm__ ("swapb %0" : "=r" (x) : "0" (x));
-
- return(x);
-}
-#define __arch_swab16 __arch_swab16
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/system.h b/arch/cris/include/arch-v10/arch/system.h
deleted file mode 100644
index 4c63f728122b..000000000000
--- a/arch/cris/include/arch-v10/arch/system.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_SYSTEM_H
-#define __ASM_CRIS_ARCH_SYSTEM_H
-
-
-/* read the CPU version register */
-
-static inline unsigned long rdvr(void) {
- unsigned char vr;
- __asm__ volatile ("move $vr,%0" : "=rm" (vr));
- return vr;
-}
-
-#define cris_machine_name "cris"
-
-/* read/write the user-mode stackpointer */
-
-static inline unsigned long rdusp(void) {
- unsigned long usp;
- __asm__ __volatile__("move $usp,%0" : "=rm" (usp));
- return usp;
-}
-
-#define wrusp(usp) \
- __asm__ __volatile__("move %0,$usp" : /* no outputs */ : "rm" (usp))
-
-/* read the current stackpointer */
-
-static inline unsigned long rdsp(void) {
- unsigned long sp;
- __asm__ __volatile__("move.d $sp,%0" : "=rm" (sp));
- return sp;
-}
-
-static inline unsigned long _get_base(char * addr)
-{
- return 0;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/thread_info.h b/arch/cris/include/arch-v10/arch/thread_info.h
deleted file mode 100644
index 0ef1223998c1..000000000000
--- a/arch/cris/include/arch-v10/arch/thread_info.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_THREAD_INFO_H
-#define _ASM_ARCH_THREAD_INFO_H
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
- __asm__("and.d $sp,%0; ":"=r" (ti) : "0" (~8191UL));
- return ti;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/timex.h b/arch/cris/include/arch-v10/arch/timex.h
deleted file mode 100644
index 9c9583e5aed6..000000000000
--- a/arch/cris/include/arch-v10/arch/timex.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Use prescale timer at 25000 Hz instead of the baudrate timer at
- * 19200 to get rid of the 64ppm to fast timer (and we get better
- * resolution within a jiffie as well.
- */
-#ifndef _ASM_CRIS_ARCH_TIMEX_H
-#define _ASM_CRIS_ARCH_TIMEX_H
-
-/* The prescaler clock runs at 25MHz, we divide it by 1000 in the prescaler */
-/* If you change anything here you must check time.c as well... */
-#define PRESCALE_FREQ 25000000
-#define PRESCALE_VALUE 1000
-#define CLOCK_TICK_RATE 25000 /* Underlying frequency of the HZ timer */
-/* The timer0 values gives 40us resolution (1/25000) but interrupts at HZ*/
-#define TIMER0_FREQ (CLOCK_TICK_RATE)
-#define TIMER0_CLKSEL flexible
-#define TIMER0_DIV (TIMER0_FREQ/(HZ))
-
-
-#define GET_JIFFIES_USEC() \
- ( (TIMER0_DIV - *R_TIMER0_DATA) * (1000000/HZ)/TIMER0_DIV )
-
-unsigned long get_ns_in_jiffie(void);
-
-static inline unsigned long get_us_in_jiffie_highres(void)
-{
- return get_ns_in_jiffie()/1000;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/tlb.h b/arch/cris/include/arch-v10/arch/tlb.h
deleted file mode 100644
index 9f039d83f21b..000000000000
--- a/arch/cris/include/arch-v10/arch/tlb.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_TLB_H
-#define _CRIS_ARCH_TLB_H
-
-/* The TLB can host up to 64 different mm contexts at the same time.
- * The last page_id is never running - it is used as an invalid page_id
- * so we can make TLB entries that will never match.
- */
-#define NUM_TLB_ENTRIES 64
-#define NUM_PAGEID 64
-#define INVALID_PAGEID 63
-#define NO_CONTEXT -1
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/uaccess.h b/arch/cris/include/arch-v10/arch/uaccess.h
deleted file mode 100644
index 8d033c534f1f..000000000000
--- a/arch/cris/include/arch-v10/arch/uaccess.h
+++ /dev/null
@@ -1,651 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Hans-Peter Nilsson (hp@axis.com)
- *
- */
-#ifndef _CRIS_ARCH_UACCESS_H
-#define _CRIS_ARCH_UACCESS_H
-
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- *
- * Note that PC at a fault is the address *after* the faulting
- * instruction.
- */
-#define __put_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- " "op" %1,[%2]\n" \
- "2:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 2b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err) \
- : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __put_user_asm_64(x, addr, err) \
- __asm__ __volatile__( \
- " move.d %M1,[%2]\n" \
- "2: move.d %H1,[%2+4]\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 4b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err) \
- : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-/* See comment before __put_user_asm. */
-
-#define __get_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- " "op" [%2],%1\n" \
- "2:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " moveq 0,%1\n" \
- " jump 2b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x) \
- : "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __get_user_asm_64(x, addr, err) \
- __asm__ __volatile__( \
- " move.d [%2],%M1\n" \
- "2: move.d [%2+4],%H1\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " moveq 0,%1\n" \
- " jump 4b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x) \
- : "r" (addr), "g" (-EFAULT), "0" (err))
-
-/*
- * Copy a null terminated string from userspace.
- *
- * Must return:
- * -EFAULT for an exception
- * count if we hit the buffer limit
- * bytes copied if we hit a null byte
- * (without the null byte)
- */
-static inline long
-__do_strncpy_from_user(char *dst, const char *src, long count)
-{
- long res;
-
- if (count == 0)
- return 0;
-
- /*
- * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
- * So do we.
- *
- * This code is deduced from:
- *
- * char tmp2;
- * long tmp1, tmp3
- * tmp1 = count;
- * while ((*dst++ = (tmp2 = *src++)) != 0
- * && --tmp1)
- * ;
- *
- * res = count - tmp1;
- *
- * with tweaks.
- */
-
- __asm__ __volatile__ (
- " move.d %3,%0\n"
- " move.b [%2+],$r9\n"
- "1: beq 2f\n"
- " move.b $r9,[%1+]\n"
-
- " subq 1,%0\n"
- " bne 1b\n"
- " move.b [%2+],$r9\n"
-
- "2: sub.d %3,%0\n"
- " neg.d %0,%0\n"
- "3:\n"
- " .section .fixup,\"ax\"\n"
- "4: move.d %7,%0\n"
- " jump 3b\n"
-
- /* There's one address for a fault at the first move, and
- two possible PC values for a fault at the second move,
- being a delay-slot filler. However, the branch-target
- for the second move is the same as the first address.
- Just so you don't get confused... */
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 1b,4b\n"
- " .dword 2b,4b\n"
- " .previous"
- : "=r" (res), "=r" (dst), "=r" (src), "=r" (count)
- : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
- : "r9");
-
- return res;
-}
-
-/* A few copy asms to build up the more complex ones from.
-
- Note again, a post-increment is performed regardless of whether a bus
- fault occurred in that instruction, and PC for a faulted insn is the
- address *after* the insn. */
-
-#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- COPY \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " jump 1b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous\n" \
- : "=r" (to), "=r" (from), "=r" (ret) \
- : "0" (to), "1" (from), "2" (ret) \
- : "r9", "memory")
-
-#define __asm_copy_from_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "2: move.b $r9,[%0+]\n", \
- "3: addq 1,%2\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "2: move.w $r9,[%0+]\n" COPY, \
- "3: addq 2,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_2(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_3(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "4: move.b $r9,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "2: move.d $r9,[%0+]\n" COPY, \
- "3: addq 4,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_4(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_5(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "4: move.b $r9,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "4: move.w $r9,[%0+]\n" COPY, \
- "5: addq 2,%2\n" \
- FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_from_user_6(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_7(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "6: move.b $r9,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "4: move.d $r9,[%0+]\n" COPY, \
- "5: addq 4,%2\n" \
- FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_from_user_8(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_9(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "6: move.b $r9,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "6: move.w $r9,[%0+]\n" COPY, \
- "7: addq 2,%2\n" \
- FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_from_user_10(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_11(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "8: move.b $r9,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "6: move.d $r9,[%0+]\n" COPY, \
- "7: addq 4,%2\n" \
- FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_from_user_12(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_13(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "8: move.b $r9,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- "8: move.w $r9,[%0+]\n" COPY, \
- "9: addq 2,%2\n" \
- FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_from_user_14(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_15(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- "10: move.b $r9,[%0+]\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "8: move.d $r9,[%0+]\n" COPY, \
- "9: addq 4,%2\n" \
- FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_from_user_16(to, from, ret) \
- __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_16x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "10: move.d $r9,[%0+]\n" COPY, \
- "11: addq 4,%2\n" \
- FIXUP, \
- " .dword 10b,11b\n" TENTRY)
-
-#define __asm_copy_from_user_20(to, from, ret) \
- __asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_20x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- "12: move.d $r9,[%0+]\n" COPY, \
- "13: addq 4,%2\n" \
- FIXUP, \
- " .dword 12b,13b\n" TENTRY)
-
-#define __asm_copy_from_user_24(to, from, ret) \
- __asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
-
-/* And now, the to-user ones. */
-
-#define __asm_copy_to_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n2:\n", \
- "3: addq 1,%2\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n2:\n" COPY, \
- "3: addq 2,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_2(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_3(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n4:\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n2:\n" COPY, \
- "3: addq 4,%2\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_4(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_5(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n4:\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n4:\n" COPY, \
- "5: addq 2,%2\n" FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_6(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_7(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n6:\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n4:\n" COPY, \
- "5: addq 4,%2\n" FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_8(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_9(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n6:\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n6:\n" COPY, \
- "7: addq 2,%2\n" FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_to_user_10(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_11(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n8:\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n6:\n" COPY, \
- "7: addq 4,%2\n" FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_copy_to_user_12(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_13(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n8:\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.w [%1+],$r9\n" \
- " move.w $r9,[%0+]\n8:\n" COPY, \
- "9: addq 2,%2\n" FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_14(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_15(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, \
- " move.b [%1+],$r9\n" \
- " move.b $r9,[%0+]\n10:\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n8:\n" COPY, \
- "9: addq 4,%2\n" FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_16(to, from, ret) \
- __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_16x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n10:\n" COPY, \
- "11: addq 4,%2\n" FIXUP, \
- " .dword 10b,11b\n" TENTRY)
-
-#define __asm_copy_to_user_20(to, from, ret) \
- __asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_20x_cont(to, from, ret, \
- " move.d [%1+],$r9\n" \
- " move.d $r9,[%0+]\n12:\n" COPY, \
- "13: addq 4,%2\n" FIXUP, \
- " .dword 12b,13b\n" TENTRY)
-
-#define __asm_copy_to_user_24(to, from, ret) \
- __asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
-
-/* Define a few clearing asms with exception handlers. */
-
-/* This frame-asm is like the __asm_copy_user_cont one, but has one less
- input. */
-
-#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- CLEAR \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " jump 1b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous" \
- : "=r" (to), "=r" (ret) \
- : "0" (to), "1" (ret) \
- : "memory")
-
-#define __asm_clear_1(to, ret) \
- __asm_clear(to, ret, \
- " clear.b [%0+]\n2:\n", \
- "3: addq 1,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_2(to, ret) \
- __asm_clear(to, ret, \
- " clear.w [%0+]\n2:\n", \
- "3: addq 2,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_3(to, ret) \
- __asm_clear(to, ret, \
- " clear.w [%0+]\n" \
- "2: clear.b [%0+]\n3:\n", \
- "4: addq 2,%1\n" \
- "5: addq 1,%1\n", \
- " .dword 2b,4b\n" \
- " .dword 3b,5b\n")
-
-#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear(to, ret, \
- " clear.d [%0+]\n2:\n" CLEAR, \
- "3: addq 4,%1\n" FIXUP, \
- " .dword 2b,3b\n" TENTRY)
-
-#define __asm_clear_4(to, ret) \
- __asm_clear_4x_cont(to, ret, "", "", "")
-
-#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_4x_cont(to, ret, \
- " clear.d [%0+]\n4:\n" CLEAR, \
- "5: addq 4,%1\n" FIXUP, \
- " .dword 4b,5b\n" TENTRY)
-
-#define __asm_clear_8(to, ret) \
- __asm_clear_8x_cont(to, ret, "", "", "")
-
-#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_8x_cont(to, ret, \
- " clear.d [%0+]\n6:\n" CLEAR, \
- "7: addq 4,%1\n" FIXUP, \
- " .dword 6b,7b\n" TENTRY)
-
-#define __asm_clear_12(to, ret) \
- __asm_clear_12x_cont(to, ret, "", "", "")
-
-#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_12x_cont(to, ret, \
- " clear.d [%0+]\n8:\n" CLEAR, \
- "9: addq 4,%1\n" FIXUP, \
- " .dword 8b,9b\n" TENTRY)
-
-#define __asm_clear_16(to, ret) \
- __asm_clear_16x_cont(to, ret, "", "", "")
-
-#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_16x_cont(to, ret, \
- " clear.d [%0+]\n10:\n" CLEAR, \
- "11: addq 4,%1\n" FIXUP, \
- " .dword 10b,11b\n" TENTRY)
-
-#define __asm_clear_20(to, ret) \
- __asm_clear_20x_cont(to, ret, "", "", "")
-
-#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_20x_cont(to, ret, \
- " clear.d [%0+]\n12:\n" CLEAR, \
- "13: addq 4,%1\n" FIXUP, \
- " .dword 12b,13b\n" TENTRY)
-
-#define __asm_clear_24(to, ret) \
- __asm_clear_24x_cont(to, ret, "", "", "")
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return length of string in userspace including terminating 0
- * or 0 for error. Return a value greater than N if too long.
- */
-
-static inline long
-strnlen_user(const char *s, long n)
-{
- long res, tmp1;
-
- if (!access_ok(VERIFY_READ, s, 0))
- return 0;
-
- /*
- * This code is deduced from:
- *
- * tmp1 = n;
- * while (tmp1-- > 0 && *s++)
- * ;
- *
- * res = n - tmp1;
- *
- * (with tweaks).
- */
-
- __asm__ __volatile__ (
- " move.d %1,$r9\n"
- "0:\n"
- " ble 1f\n"
- " subq 1,$r9\n"
-
- " test.b [%0+]\n"
- " bne 0b\n"
- " test.d $r9\n"
- "1:\n"
- " move.d %1,%0\n"
- " sub.d $r9,%0\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
-
- "3: clear.d %0\n"
- " jump 2b\n"
-
- /* There's one address for a fault at the first move, and
- two possible PC values for a fault at the second move,
- being a delay-slot filler. However, the branch-target
- for the second move is the same as the first address.
- Just so you don't get confused... */
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 0b,3b\n"
- " .dword 1b,3b\n"
- " .previous\n"
- : "=r" (res), "=r" (tmp1)
- : "0" (s), "1" (n)
- : "r9");
-
- return res;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v10/arch/unistd.h b/arch/cris/include/arch-v10/arch/unistd.h
deleted file mode 100644
index 03cd0b8652f4..000000000000
--- a/arch/cris/include/arch-v10/arch/unistd.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_UNISTD_H_
-#define _ASM_CRIS_ARCH_UNISTD_H_
-
-/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
-/*
- * Don't remove the .ifnc tests; they are an insurance against
- * any hard-to-spot gcc register allocation bugs.
- */
-#define _syscall0(type,name) \
-type name(void) \
-{ \
- register long __a __asm__ ("r10"); \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall1(type,name,type1,arg1) \
-type name(type1 arg1) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2) \
-type name(type1 arg1,type2 arg2) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
-type name(type1 arg1,type2 arg2,type3 arg3) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "move %6,$mof\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "g" (arg5)); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5,type6,arg6) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "move %6,$mof\n\tmove %7,$srp\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "g" (arg5), "g" (arg6)\
- : "srp"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/bitops.h b/arch/cris/include/arch-v32/arch/bitops.h
deleted file mode 100644
index 7df94798f063..000000000000
--- a/arch/cris/include/arch-v32/arch/bitops.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_BITOPS_H
-#define _ASM_CRIS_ARCH_BITOPS_H
-
-/*
- * Helper functions for the core of the ff[sz] functions. They compute the
- * number of leading zeroes of a bits-in-byte, byte-in-word and
- * word-in-dword-swapped number. They differ in that the first function also
- * inverts all bits in the input.
- */
-
-static inline unsigned long
-cris_swapnwbrlz(unsigned long w)
-{
- unsigned long res;
-
- __asm__ __volatile__ ("swapnwbr %0\n\t"
- "lz %0,%0"
- : "=r" (res) : "0" (w));
-
- return res;
-}
-
-static inline unsigned long
-cris_swapwbrlz(unsigned long w)
-{
- unsigned long res;
-
- __asm__ __volatile__ ("swapwbr %0\n\t"
- "lz %0,%0"
- : "=r" (res) : "0" (w));
-
- return res;
-}
-
-/*
- * Find First Zero in word. Undefined if no zero exist, so the caller should
- * check against ~0 first.
- */
-static inline unsigned long
-ffz(unsigned long w)
-{
- return cris_swapnwbrlz(w);
-}
-
-/*
- * Find First Set bit in word. Undefined if no 1 exist, so the caller
- * should check against 0 first.
- */
-static inline unsigned long
-__ffs(unsigned long w)
-{
- return cris_swapnwbrlz(~w);
-}
-
-/*
- * Find First Bit that is set.
- */
-static inline unsigned long
-kernel_ffs(unsigned long w)
-{
- return w ? cris_swapwbrlz (w) + 1 : 0;
-}
-
-#endif /* _ASM_CRIS_ARCH_BITOPS_H */
diff --git a/arch/cris/include/arch-v32/arch/bug.h b/arch/cris/include/arch-v32/arch/bug.h
deleted file mode 100644
index 982c6b08fdf1..000000000000
--- a/arch/cris/include/arch-v32/arch/bug.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRISv32_ARCH_BUG_H
-#define __ASM_CRISv32_ARCH_BUG_H
-
-#include <linux/stringify.h>
-
-#ifdef CONFIG_BUG
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-/*
- * The penalty for the in-band code path will be the size of break 14.
- * All other stuff is done out-of-band with exception handlers.
- */
-#define BUG() \
-do { \
- __asm__ __volatile__ ("0: break 14\n\t" \
- ".section .fixup,\"ax\"\n" \
- "1:\n\t" \
- "move.d %0, $r10\n\t" \
- "move.d %1, $r11\n\t" \
- "jump do_BUG\n\t" \
- "nop\n\t" \
- ".previous\n\t" \
- ".section __ex_table,\"a\"\n\t" \
- ".dword 0b, 1b\n\t" \
- ".previous\n\t" \
- : : "ri" (__FILE__), "i" (__LINE__)); \
- unreachable(); \
-} while (0)
-#else
-#define BUG() \
-do { \
- __asm__ __volatile__ ("break 14\n\t"); \
- unreachable(); \
-} while (0)
-#endif
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-#endif
diff --git a/arch/cris/include/arch-v32/arch/cache.h b/arch/cris/include/arch-v32/arch/cache.h
deleted file mode 100644
index f61f3088c45b..000000000000
--- a/arch/cris/include/arch-v32/arch/cache.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_CACHE_H
-#define _ASM_CRIS_ARCH_CACHE_H
-
-#include <arch/hwregs/dma.h>
-
-/* A cache-line is 32 bytes. */
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-
-void flush_dma_list(dma_descr_data *descr);
-void flush_dma_descr(dma_descr_data *descr, int flush_buf);
-
-#define flush_dma_context(c) \
- flush_dma_list(phys_to_virt((c)->saved_data));
-
-void cris_flush_cache_range(void *buf, unsigned long len);
-void cris_flush_cache(void);
-
-#endif /* _ASM_CRIS_ARCH_CACHE_H */
diff --git a/arch/cris/include/arch-v32/arch/checksum.h b/arch/cris/include/arch-v32/arch/checksum.h
deleted file mode 100644
index fea1341ef244..000000000000
--- a/arch/cris/include/arch-v32/arch/checksum.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_CHECKSUM_H
-#define _ASM_CRIS_ARCH_CHECKSUM_H
-
-/*
- * Check values used in TCP/UDP headers.
- *
- * The gain of doing this in assembler instead of C, is that C doesn't
- * generate carry-additions for the 32-bit components of the
- * checksum. Which means it would be necessary to split all those into
- * 16-bit components and then add.
- */
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto, __wsum sum)
-{
- __wsum res;
-
- __asm__ __volatile__ ("add.d %2, %0\n\t"
- "addc %3, %0\n\t"
- "addc %4, %0\n\t"
- "addc 0, %0\n\t"
- : "=r" (res)
- : "0" (sum), "r" (daddr), "r" (saddr), \
- "r" ((len + proto) << 8));
-
- return res;
-}
-
-#endif /* _ASM_CRIS_ARCH_CHECKSUM_H */
diff --git a/arch/cris/include/arch-v32/arch/cryptocop.h b/arch/cris/include/arch-v32/arch/cryptocop.h
deleted file mode 100644
index f2f8eda1ffb1..000000000000
--- a/arch/cris/include/arch-v32/arch/cryptocop.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * The device /dev/cryptocop is accessible using this driver using
- * CRYPTOCOP_MAJOR (254) and minor number 0.
- */
-#ifndef CRYPTOCOP_H
-#define CRYPTOCOP_H
-
-#include <uapi/arch-v32/arch/cryptocop.h>
-
-
-/********** The API to use from inside the kernel. ************/
-
-#include <arch/hwregs/dma.h>
-
-typedef enum {
- cryptocop_alg_csum = 0,
- cryptocop_alg_mem2mem,
- cryptocop_alg_md5,
- cryptocop_alg_sha1,
- cryptocop_alg_des,
- cryptocop_alg_3des,
- cryptocop_alg_aes,
- cryptocop_no_alg,
-} cryptocop_algorithm;
-
-typedef u8 cryptocop_tfrm_id;
-
-
-struct cryptocop_operation;
-
-typedef void (cryptocop_callback)(struct cryptocop_operation*, void*);
-
-struct cryptocop_transform_init {
- cryptocop_algorithm alg;
- /* Keydata for ciphers. */
- unsigned char key[CRYPTOCOP_MAX_KEY_LENGTH];
- unsigned int keylen;
- cryptocop_cipher_mode cipher_mode;
- cryptocop_3des_mode tdes_mode;
- cryptocop_csum_type csum_mode; /* cryptocop_csum_none is not allowed when alg==cryptocop_alg_csum */
-
- cryptocop_tfrm_id tid; /* Locally unique in session; assigned by user, checked by driver. */
- struct cryptocop_transform_init *next;
-};
-
-
-typedef enum {
- cryptocop_source_dma = 0,
- cryptocop_source_des,
- cryptocop_source_3des,
- cryptocop_source_aes,
- cryptocop_source_md5,
- cryptocop_source_sha1,
- cryptocop_source_csum,
- cryptocop_source_none,
-} cryptocop_source;
-
-
-struct cryptocop_desc_cfg {
- cryptocop_tfrm_id tid;
- cryptocop_source src;
- unsigned int last:1; /* Last use of this transform in the operation. Will push outdata when encountered. */
- struct cryptocop_desc_cfg *next;
-};
-
-struct cryptocop_desc {
- size_t length;
- struct cryptocop_desc_cfg *cfg;
- struct cryptocop_desc *next;
-};
-
-
-/* Flags for cryptocop_tfrm_cfg */
-#define CRYPTOCOP_NO_FLAG (0x00)
-#define CRYPTOCOP_ENCRYPT (0x01)
-#define CRYPTOCOP_DECRYPT (0x02)
-#define CRYPTOCOP_EXPLICIT_IV (0x04)
-
-struct cryptocop_tfrm_cfg {
- cryptocop_tfrm_id tid;
-
- unsigned int flags; /* DECRYPT, ENCRYPT, EXPLICIT_IV */
-
- /* CBC initialisation vector for ciphers. */
- u8 iv[CRYPTOCOP_MAX_IV_LENGTH];
-
- /* The position in output where to write the transform output. The order
- in which the driver writes the output is unspecified, hence if several
- transforms write on the same positions in the output the result is
- unspecified. */
- size_t inject_ix;
-
- struct cryptocop_tfrm_cfg *next;
-};
-
-
-
-struct cryptocop_dma_list_operation{
- /* The consumer can provide DMA lists to send to the co-processor. 'use_dmalists' in
- struct cryptocop_operation must be set for the driver to use them. outlist,
- out_data_buf, inlist and in_data_buf must all be physical addresses since they will
- be loaded to DMA . */
- dma_descr_data *outlist; /* Out from memory to the co-processor. */
- char *out_data_buf;
- dma_descr_data *inlist; /* In from the co-processor to memory. */
- char *in_data_buf;
-
- cryptocop_3des_mode tdes_mode;
- cryptocop_csum_type csum_mode;
-};
-
-
-struct cryptocop_tfrm_operation{
- /* Operation configuration, if not 'use_dmalists' is set. */
- struct cryptocop_tfrm_cfg *tfrm_cfg;
- struct cryptocop_desc *desc;
-
- struct iovec *indata;
- size_t incount;
- size_t inlen; /* Total inlength. */
-
- struct iovec *outdata;
- size_t outcount;
- size_t outlen; /* Total outlength. */
-};
-
-
-struct cryptocop_operation {
- cryptocop_callback *cb;
- void *cb_data;
-
- cryptocop_session_id sid;
-
- /* The status of the operation when returned to consumer. */
- int operation_status; /* 0, -EAGAIN */
-
- /* Flags */
- unsigned int use_dmalists:1; /* Use outlist and inlist instead of the desc/tfrm_cfg configuration. */
- unsigned int in_interrupt:1; /* Set if inserting job from interrupt context. */
- unsigned int fast_callback:1; /* Set if fast callback wanted, i.e. from interrupt context. */
-
- union{
- struct cryptocop_dma_list_operation list_op;
- struct cryptocop_tfrm_operation tfrm_op;
- };
-};
-
-
-int cryptocop_new_session(cryptocop_session_id *sid, struct cryptocop_transform_init *tinit, int alloc_flag);
-int cryptocop_free_session(cryptocop_session_id sid);
-
-int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
-
-int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
-
-int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
-
-#endif /* CRYPTOCOP_H */
diff --git a/arch/cris/include/arch-v32/arch/delay.h b/arch/cris/include/arch-v32/arch/delay.h
deleted file mode 100644
index 94307c1fbb1c..000000000000
--- a/arch/cris/include/arch-v32/arch/delay.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_DELAY_H
-#define _ASM_CRIS_ARCH_DELAY_H
-
-extern void cris_delay10ns(u32 n10ns);
-#define udelay(u) cris_delay10ns((u)*100)
-#define ndelay(n) cris_delay10ns(((n)+9)/10)
-
-/*
- * Not used anymore for udelay or ndelay. Referenced by
- * e.g. init/calibrate.c. All other references are likely bugs;
- * should be replaced by mdelay, udelay or ndelay.
- */
-
-static inline void
-__delay(int loops)
-{
- __asm__ __volatile__ (
- "move.d %0, $r9\n\t"
- "beq 2f\n\t"
- "subq 1, $r9\n\t"
- "1:\n\t"
- "bne 1b\n\t"
- "subq 1, $r9\n"
- "2:"
- : : "g" (loops) : "r9");
-}
-
-#endif /* _ASM_CRIS_ARCH_DELAY_H */
diff --git a/arch/cris/include/arch-v32/arch/dma.h b/arch/cris/include/arch-v32/arch/dma.h
deleted file mode 100644
index 6f92f4f23f28..000000000000
--- a/arch/cris/include/arch-v32/arch/dma.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach/dma.h>
diff --git a/arch/cris/include/arch-v32/arch/hwregs/Makefile b/arch/cris/include/arch-v32/arch/hwregs/Makefile
deleted file mode 100644
index bb5ffa7ff9f4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/Makefile
+++ /dev/null
@@ -1,187 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# Makefile to generate or copy the latest register definitions
-# and related datastructures and helpermacros.
-# The official place for these files is at:
-RELEASE ?= r1_alfa5
-OFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
-
-# which is updated on each new release.
-INCL_ASMFILES =
-INCL_FILES = ata_defs.h
-INCL_FILES += bif_core_defs.h
-INCL_ASMFILES += bif_core_defs_asm.h
-INCL_FILES += bif_slave_defs.h
-#INCL_FILES += bif_slave_ext_defs.h
-INCL_FILES += config_defs.h
-INCL_ASMFILES += config_defs_asm.h
-INCL_FILES += cpu_vect.h
-#INCL_FILES += cris_defs.h
-#INCL_FILES += cris_supp_reg.h # In handcrafted supp_reg.h
-INCL_FILES += dma.h
-INCL_FILES += dma_defs.h
-INCL_FILES += eth_defs.h
-INCL_FILES += extmem_defs.h
-INCL_FILES += gio_defs.h
-INCL_ASMFILES += gio_defs_asm.h
-INCL_FILES += intr_vect.h
-INCL_FILES += intr_vect_defs.h
-INCL_ASMFILES += intr_vect_defs_asm.h
-INCL_FILES += marb_bp_defs.h
-INCL_FILES += marb_defs.h
-INCL_ASMFILES += mmu_defs_asm.h
-#INCL_FILES += mmu_supp_reg.h # In handcrafted supp_reg.h
-#INCL_FILES += par_defs.h # No useful content
-INCL_FILES += pinmux_defs.h
-INCL_FILES += reg_map.h
-INCL_ASMFILES += reg_map_asm.h
-INCL_FILES += reg_rdwr.h
-INCL_FILES += ser_defs.h
-#INCL_FILES += spec_reg.h # In handcrafted supp_reg.h
-INCL_FILES += sser_defs.h
-INCL_FILES += strcop_defs.h
-#INCL_FILES += strcop.h # Where is this?
-INCL_FILES += strmux_defs.h
-#INCL_FILES += supp_reg.h # Handcrafted instead
-INCL_FILES += timer_defs.h
-
-REGDESC =
-REGDESC += $(BASEDIR)/io/ata/rtl/ata_regs.r
-REGDESC += $(BASEDIR)/io/bif/rtl/bif_core_regs.r
-REGDESC += $(BASEDIR)/io/bif/rtl/bif_slave_regs.r
-#REGDESC += $(BASEDIR)/io/bif/sw/bif_slave_ext_regs.r
-REGDESC += $(DESIGNDIR)/top/rtl/config_regs.r
-REGDESC += $(BASEDIR)/mod/dma_common/rtl/dma_regdes.r
-REGDESC += $(BASEDIR)/io/eth/rtl/eth_regs.r
-REGDESC += $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
-REGDESC += $(DESIGNDIR)/gio/rtl/gio_regs.r
-REGDESC += $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-REGDESC += $(BASEDIR)/core/memarb/rtl/guinness/marb_top.r
-REGDESC += $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
-#REGDESC += $(BASEDIR)/io/par_port/rtl/par_regs.r
-REGDESC += $(BASEDIR)/io/pinmux/rtl/guinness/pinmux_regs.r
-REGDESC += $(BASEDIR)/io/ser/rtl/ser_regs.r
-REGDESC += $(BASEDIR)/core/strcop/rtl/strcop_regs.r
-REGDESC += $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
-REGDESC += $(BASEDIR)/io/timer/rtl/timer_regs.r
-#REGDESC += $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
-
-
-BASEDIR = /n/asic/design
-DESIGNDIR = /n/asic/projects/guinness/design
-RDES2C = /n/asic/bin/rdes2c
-RDES2C = /n/asic/design/tools/rdesc/rdes2c
-RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
-RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
-
-## all - Just print help - you probably want to do 'make gen'
-all: help
-
-# Disable implicit rule that may generate deleted files from RCS/ directory.
-%.r:
-
-%.h:
-
-## help - This help
-help:
- @grep '^## ' Makefile
-
-## gen - Generate include files
-gen: $(INCL_FILES) $(INCL_ASMFILES)
-
-ata_defs.h: $(BASEDIR)/io/ata/rtl/ata_regs.r
- $(RDES2C) $<
-config_defs.h: $(DESIGNDIR)/top/rtl/config_regs.r
- $(RDES2C) $<
-config_defs_asm.h: $(DESIGNDIR)/top/rtl/config_regs.r
- $(RDES2C) -asm $<
-# Can't generate cpu_vect.h yet
-#cpu_vect.h: $(DESIGNDIR)/top/rtl/cpu_vect.r # ????
-# $(RDES2INTR) $<
-cpu_vect.h: $(OFFICIAL_INCDIR)cpu_vect.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-dma_defs.h: $(BASEDIR)/core/dma/rtl/common/dma_regdes.r
- $(RDES2C) $<
-$(BASEDIR)/core/dma/sw/dma.h:
-dma.h: $(BASEDIR)/core/dma/sw/dma.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-eth_defs.h: $(BASEDIR)/io/eth/rtl/eth_regs.r
- $(RDES2C) $<
-extmem_defs.h: $(BASEDIR)/io/bif/mod/extmem/extmem_regs.r
- $(RDES2C) $<
-gio_defs.h: $(DESIGNDIR)/gio/rtl/gio_regs.r
- $(RDES2C) $<
-intr_vect_defs.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
- $(RDES2C) $<
-intr_vect_defs_asm.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
- $(RDES2C) -asm $<
-# Can't generate intr_vect.h yet
-#intr_vect.h: $(BASEDIR)/core/cpu/intr_vect/rtl/guinness/ivmask.config.r
-# $(RDES2INTR) $<
-intr_vect.h: $(OFFICIAL_INCDIR)intr_vect.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-mmu_defs_asm.h: $(BASEDIR)/core/cpu/mmu/doc/mmu_regs.r
- $(RDES2C) -asm $<
-par_defs.h: $(BASEDIR)/io/par_port/rtl/par_regs.r
- $(RDES2C) $<
-
-# From /n/asic/projects/guinness/design/
-reg_map.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
- $(RDES2C) -base 0xb0000000 $^
-reg_map_asm.h: $(DESIGNDIR)/top/rtl/global.rmap $(DESIGNDIR)/top/mod/modreg.rmap
- $(RDES2C) -base 0xb0000000 -asm -outfile $@ $^
-
-reg_rdwr.h: $(DESIGNDIR)/top/sw/include/reg_rdwr.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-
-ser_defs.h: $(BASEDIR)/io/ser/rtl/ser_regs.r
- $(RDES2C) $<
-strcop_defs.h: $(BASEDIR)/core/strcop/rtl/strcop_regs.r
- $(RDES2C) $<
-strcop.h: $(BASEDIR)/core/strcop/rtl/strcop.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-strmux_defs.h: $(BASEDIR)/io/strmux/rtl/guinness/strmux_regs.r
- $(RDES2C) $<
-timer_defs.h: $(BASEDIR)/io/timer/rtl/timer_regs.r
- $(RDES2C) $<
-usb_defs.h: $(BASEDIR)/io/usb/usb1_1/rtl/usb_regs.r
- $(RDES2C) $<
-
-## copy - Copy files from official location
-copy:
- @for HFILE in $(INCL_FILES); do \
- echo " $$HFILE"; \
- cat $(OFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
- @for HFILE in $(INCL_ASMFILES); do \
- echo " $$HFILE"; \
- cat $(OFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
-## ls_official - List official location
-ls_official:
- (cd $(OFFICIAL_INCDIR); ls -l *.h )
-
-## diff_official - Diff current directory with official location
-diff_official:
- diff . $(OFFICIAL_INCDIR)
-
-## doc - Generate .axw files from register description.
-doc: $(REGDESC)
- for RDES in $^; do \
- $(RDES2TXT) $$RDES; \
- done
-
-.PHONY: axw
-## %.axw - Generate the specified .axw file (doesn't work for all files
-## due to inconsistent naming ir .r files.
-%.axw: axw
- @for RDES in $(REGDESC); do \
- if echo "$$RDES" | grep $* ; then \
- $(RDES2TXT) $$RDES; \
- fi \
- done
-
-.PHONY: clean
-## clean - Remove .h files and .axw files.
-clean:
- rm -rf $(INCL_FILES) *.axw
-
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h
deleted file mode 100644
index 6886ba3c2d53..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/ata_defs_asm.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ata_defs_asm_h
-#define __ata_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ata/rtl/ata_regs.r
- * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
- * last modfied: Mon Apr 11 16:06:25 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
- * id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ctrl0, scope ata, type rw */
-#define reg_ata_rw_ctrl0___pio_hold___lsb 0
-#define reg_ata_rw_ctrl0___pio_hold___width 6
-#define reg_ata_rw_ctrl0___pio_strb___lsb 6
-#define reg_ata_rw_ctrl0___pio_strb___width 6
-#define reg_ata_rw_ctrl0___pio_setup___lsb 12
-#define reg_ata_rw_ctrl0___pio_setup___width 6
-#define reg_ata_rw_ctrl0___dma_hold___lsb 18
-#define reg_ata_rw_ctrl0___dma_hold___width 6
-#define reg_ata_rw_ctrl0___dma_strb___lsb 24
-#define reg_ata_rw_ctrl0___dma_strb___width 6
-#define reg_ata_rw_ctrl0___rst___lsb 30
-#define reg_ata_rw_ctrl0___rst___width 1
-#define reg_ata_rw_ctrl0___rst___bit 30
-#define reg_ata_rw_ctrl0___en___lsb 31
-#define reg_ata_rw_ctrl0___en___width 1
-#define reg_ata_rw_ctrl0___en___bit 31
-#define reg_ata_rw_ctrl0_offset 12
-
-/* Register rw_ctrl1, scope ata, type rw */
-#define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
-#define reg_ata_rw_ctrl1___udma_tcyc___width 4
-#define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
-#define reg_ata_rw_ctrl1___udma_tdvs___width 4
-#define reg_ata_rw_ctrl1_offset 16
-
-/* Register rw_ctrl2, scope ata, type rw */
-#define reg_ata_rw_ctrl2___data___lsb 0
-#define reg_ata_rw_ctrl2___data___width 16
-#define reg_ata_rw_ctrl2___dma_size___lsb 19
-#define reg_ata_rw_ctrl2___dma_size___width 1
-#define reg_ata_rw_ctrl2___dma_size___bit 19
-#define reg_ata_rw_ctrl2___multi___lsb 20
-#define reg_ata_rw_ctrl2___multi___width 1
-#define reg_ata_rw_ctrl2___multi___bit 20
-#define reg_ata_rw_ctrl2___hsh___lsb 21
-#define reg_ata_rw_ctrl2___hsh___width 2
-#define reg_ata_rw_ctrl2___trf_mode___lsb 23
-#define reg_ata_rw_ctrl2___trf_mode___width 1
-#define reg_ata_rw_ctrl2___trf_mode___bit 23
-#define reg_ata_rw_ctrl2___rw___lsb 24
-#define reg_ata_rw_ctrl2___rw___width 1
-#define reg_ata_rw_ctrl2___rw___bit 24
-#define reg_ata_rw_ctrl2___addr___lsb 25
-#define reg_ata_rw_ctrl2___addr___width 3
-#define reg_ata_rw_ctrl2___cs0___lsb 28
-#define reg_ata_rw_ctrl2___cs0___width 1
-#define reg_ata_rw_ctrl2___cs0___bit 28
-#define reg_ata_rw_ctrl2___cs1___lsb 29
-#define reg_ata_rw_ctrl2___cs1___width 1
-#define reg_ata_rw_ctrl2___cs1___bit 29
-#define reg_ata_rw_ctrl2___sel___lsb 30
-#define reg_ata_rw_ctrl2___sel___width 2
-#define reg_ata_rw_ctrl2_offset 0
-
-/* Register rs_stat_data, scope ata, type rs */
-#define reg_ata_rs_stat_data___data___lsb 0
-#define reg_ata_rs_stat_data___data___width 16
-#define reg_ata_rs_stat_data___dav___lsb 16
-#define reg_ata_rs_stat_data___dav___width 1
-#define reg_ata_rs_stat_data___dav___bit 16
-#define reg_ata_rs_stat_data___busy___lsb 17
-#define reg_ata_rs_stat_data___busy___width 1
-#define reg_ata_rs_stat_data___busy___bit 17
-#define reg_ata_rs_stat_data_offset 4
-
-/* Register r_stat_data, scope ata, type r */
-#define reg_ata_r_stat_data___data___lsb 0
-#define reg_ata_r_stat_data___data___width 16
-#define reg_ata_r_stat_data___dav___lsb 16
-#define reg_ata_r_stat_data___dav___width 1
-#define reg_ata_r_stat_data___dav___bit 16
-#define reg_ata_r_stat_data___busy___lsb 17
-#define reg_ata_r_stat_data___busy___width 1
-#define reg_ata_r_stat_data___busy___bit 17
-#define reg_ata_r_stat_data_offset 8
-
-/* Register rw_trf_cnt, scope ata, type rw */
-#define reg_ata_rw_trf_cnt___cnt___lsb 0
-#define reg_ata_rw_trf_cnt___cnt___width 17
-#define reg_ata_rw_trf_cnt_offset 20
-
-/* Register r_stat_misc, scope ata, type r */
-#define reg_ata_r_stat_misc___crc___lsb 0
-#define reg_ata_r_stat_misc___crc___width 16
-#define reg_ata_r_stat_misc_offset 24
-
-/* Register rw_intr_mask, scope ata, type rw */
-#define reg_ata_rw_intr_mask___bus0___lsb 0
-#define reg_ata_rw_intr_mask___bus0___width 1
-#define reg_ata_rw_intr_mask___bus0___bit 0
-#define reg_ata_rw_intr_mask___bus1___lsb 1
-#define reg_ata_rw_intr_mask___bus1___width 1
-#define reg_ata_rw_intr_mask___bus1___bit 1
-#define reg_ata_rw_intr_mask___bus2___lsb 2
-#define reg_ata_rw_intr_mask___bus2___width 1
-#define reg_ata_rw_intr_mask___bus2___bit 2
-#define reg_ata_rw_intr_mask___bus3___lsb 3
-#define reg_ata_rw_intr_mask___bus3___width 1
-#define reg_ata_rw_intr_mask___bus3___bit 3
-#define reg_ata_rw_intr_mask_offset 28
-
-/* Register rw_ack_intr, scope ata, type rw */
-#define reg_ata_rw_ack_intr___bus0___lsb 0
-#define reg_ata_rw_ack_intr___bus0___width 1
-#define reg_ata_rw_ack_intr___bus0___bit 0
-#define reg_ata_rw_ack_intr___bus1___lsb 1
-#define reg_ata_rw_ack_intr___bus1___width 1
-#define reg_ata_rw_ack_intr___bus1___bit 1
-#define reg_ata_rw_ack_intr___bus2___lsb 2
-#define reg_ata_rw_ack_intr___bus2___width 1
-#define reg_ata_rw_ack_intr___bus2___bit 2
-#define reg_ata_rw_ack_intr___bus3___lsb 3
-#define reg_ata_rw_ack_intr___bus3___width 1
-#define reg_ata_rw_ack_intr___bus3___bit 3
-#define reg_ata_rw_ack_intr_offset 32
-
-/* Register r_intr, scope ata, type r */
-#define reg_ata_r_intr___bus0___lsb 0
-#define reg_ata_r_intr___bus0___width 1
-#define reg_ata_r_intr___bus0___bit 0
-#define reg_ata_r_intr___bus1___lsb 1
-#define reg_ata_r_intr___bus1___width 1
-#define reg_ata_r_intr___bus1___bit 1
-#define reg_ata_r_intr___bus2___lsb 2
-#define reg_ata_r_intr___bus2___width 1
-#define reg_ata_r_intr___bus2___bit 2
-#define reg_ata_r_intr___bus3___lsb 3
-#define reg_ata_r_intr___bus3___width 1
-#define reg_ata_r_intr___bus3___bit 3
-#define reg_ata_r_intr_offset 36
-
-/* Register r_masked_intr, scope ata, type r */
-#define reg_ata_r_masked_intr___bus0___lsb 0
-#define reg_ata_r_masked_intr___bus0___width 1
-#define reg_ata_r_masked_intr___bus0___bit 0
-#define reg_ata_r_masked_intr___bus1___lsb 1
-#define reg_ata_r_masked_intr___bus1___width 1
-#define reg_ata_r_masked_intr___bus1___bit 1
-#define reg_ata_r_masked_intr___bus2___lsb 2
-#define reg_ata_r_masked_intr___bus2___width 1
-#define reg_ata_r_masked_intr___bus2___bit 2
-#define reg_ata_r_masked_intr___bus3___lsb 3
-#define reg_ata_r_masked_intr___bus3___width 1
-#define reg_ata_r_masked_intr___bus3___bit 3
-#define reg_ata_r_masked_intr_offset 40
-
-
-/* Constants */
-#define regk_ata_active 0x00000001
-#define regk_ata_byte 0x00000001
-#define regk_ata_data 0x00000001
-#define regk_ata_dma 0x00000001
-#define regk_ata_inactive 0x00000000
-#define regk_ata_no 0x00000000
-#define regk_ata_nodata 0x00000000
-#define regk_ata_pio 0x00000000
-#define regk_ata_rd 0x00000001
-#define regk_ata_reg 0x00000000
-#define regk_ata_rw_ctrl0_default 0x00000000
-#define regk_ata_rw_ctrl2_default 0x00000000
-#define regk_ata_rw_intr_mask_default 0x00000000
-#define regk_ata_udma 0x00000002
-#define regk_ata_word 0x00000000
-#define regk_ata_wr 0x00000000
-#define regk_ata_yes 0x00000001
-#endif /* __ata_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h
deleted file mode 100644
index 1d75d8c31cc0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_core_defs_asm.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_asm_h
-#define __bif_core_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp1_cfg___lw___width 6
-#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp1_cfg___ew___width 3
-#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp1_cfg___zw___width 3
-#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp1_cfg___aw___width 2
-#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp1_cfg___dw___width 2
-#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp1_cfg___ewb___width 2
-#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp1_cfg___bw___width 1
-#define reg_bif_core_rw_grp1_cfg___bw___bit 18
-#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp1_cfg___mode___width 1
-#define reg_bif_core_rw_grp1_cfg___mode___bit 21
-#define reg_bif_core_rw_grp1_cfg_offset 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp2_cfg___lw___width 6
-#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp2_cfg___ew___width 3
-#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp2_cfg___zw___width 3
-#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp2_cfg___aw___width 2
-#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp2_cfg___dw___width 2
-#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp2_cfg___ewb___width 2
-#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp2_cfg___bw___width 1
-#define reg_bif_core_rw_grp2_cfg___bw___bit 18
-#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp2_cfg___mode___width 1
-#define reg_bif_core_rw_grp2_cfg___mode___bit 21
-#define reg_bif_core_rw_grp2_cfg_offset 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp3_cfg___lw___width 6
-#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp3_cfg___ew___width 3
-#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp3_cfg___zw___width 3
-#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp3_cfg___aw___width 2
-#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp3_cfg___dw___width 2
-#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp3_cfg___ewb___width 2
-#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp3_cfg___bw___width 1
-#define reg_bif_core_rw_grp3_cfg___bw___bit 18
-#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp3_cfg___mode___width 1
-#define reg_bif_core_rw_grp3_cfg___mode___bit 21
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
-#define reg_bif_core_rw_grp3_cfg_offset 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp4_cfg___lw___width 6
-#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp4_cfg___ew___width 3
-#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp4_cfg___zw___width 3
-#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp4_cfg___aw___width 2
-#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp4_cfg___dw___width 2
-#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp4_cfg___ewb___width 2
-#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp4_cfg___bw___width 1
-#define reg_bif_core_rw_grp4_cfg___bw___bit 18
-#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp4_cfg___mode___width 1
-#define reg_bif_core_rw_grp4_cfg___mode___bit 21
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
-#define reg_bif_core_rw_grp4_cfg_offset 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_timing___cl___lsb 0
-#define reg_bif_core_rw_sdram_timing___cl___width 3
-#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
-#define reg_bif_core_rw_sdram_timing___rcd___width 3
-#define reg_bif_core_rw_sdram_timing___rp___lsb 6
-#define reg_bif_core_rw_sdram_timing___rp___width 3
-#define reg_bif_core_rw_sdram_timing___rc___lsb 9
-#define reg_bif_core_rw_sdram_timing___rc___width 2
-#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
-#define reg_bif_core_rw_sdram_timing___dpl___width 2
-#define reg_bif_core_rw_sdram_timing___pde___lsb 13
-#define reg_bif_core_rw_sdram_timing___pde___width 1
-#define reg_bif_core_rw_sdram_timing___pde___bit 13
-#define reg_bif_core_rw_sdram_timing___ref___lsb 14
-#define reg_bif_core_rw_sdram_timing___ref___width 2
-#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
-#define reg_bif_core_rw_sdram_timing___cpd___width 1
-#define reg_bif_core_rw_sdram_timing___cpd___bit 16
-#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
-#define reg_bif_core_rw_sdram_timing___sdcke___width 1
-#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
-#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
-#define reg_bif_core_rw_sdram_timing___sdclk___width 1
-#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
-#define reg_bif_core_rw_sdram_timing_offset 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
-#define reg_bif_core_rw_sdram_cmd___cmd___width 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
-#define reg_bif_core_rw_sdram_cmd_offset 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
-#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_rs_sdram_ref_stat_offset 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_r_sdram_ref_stat___ok___width 1
-#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_r_sdram_ref_stat_offset 36
-
-
-/* Constants */
-#define regk_bif_core_bank2 0x00000000
-#define regk_bif_core_bank4 0x00000001
-#define regk_bif_core_bit10 0x0000000a
-#define regk_bif_core_bit11 0x0000000b
-#define regk_bif_core_bit12 0x0000000c
-#define regk_bif_core_bit13 0x0000000d
-#define regk_bif_core_bit14 0x0000000e
-#define regk_bif_core_bit15 0x0000000f
-#define regk_bif_core_bit16 0x00000010
-#define regk_bif_core_bit17 0x00000011
-#define regk_bif_core_bit18 0x00000012
-#define regk_bif_core_bit19 0x00000013
-#define regk_bif_core_bit20 0x00000014
-#define regk_bif_core_bit21 0x00000015
-#define regk_bif_core_bit22 0x00000016
-#define regk_bif_core_bit23 0x00000017
-#define regk_bif_core_bit24 0x00000018
-#define regk_bif_core_bit25 0x00000019
-#define regk_bif_core_bit26 0x0000001a
-#define regk_bif_core_bit27 0x0000001b
-#define regk_bif_core_bit28 0x0000001c
-#define regk_bif_core_bit29 0x0000001d
-#define regk_bif_core_bit9 0x00000009
-#define regk_bif_core_bw16 0x00000001
-#define regk_bif_core_bw32 0x00000000
-#define regk_bif_core_bwe 0x00000000
-#define regk_bif_core_cwe 0x00000001
-#define regk_bif_core_e15us 0x00000001
-#define regk_bif_core_e7800ns 0x00000002
-#define regk_bif_core_grp0 0x00000000
-#define regk_bif_core_grp1 0x00000001
-#define regk_bif_core_mrs 0x00000003
-#define regk_bif_core_no 0x00000000
-#define regk_bif_core_none 0x00000000
-#define regk_bif_core_nop 0x00000000
-#define regk_bif_core_off 0x00000000
-#define regk_bif_core_pre 0x00000002
-#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rd 0x00000002
-#define regk_bif_core_ref 0x00000001
-#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
-#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
-#define regk_bif_core_slf 0x00000004
-#define regk_bif_core_wr 0x00000001
-#define regk_bif_core_yes 0x00000001
-#endif /* __bif_core_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h
deleted file mode 100644
index a07447fa75f8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_dma_defs_asm.h
+++ /dev/null
@@ -1,496 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_dma_defs_asm_h
-#define __bif_dma_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_dma_regs.r
- * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_dma_defs_asm.h ../../inst/bif/rtl/bif_dma_regs.r
- * id: $Id: bif_dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch0_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch0_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch0_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch0_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch0_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___lsb 4
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___width 1
-#define reg_bif_dma_rw_ch0_ctrl___end_pad___bit 4
-#define reg_bif_dma_rw_ch0_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch0_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch0_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch0_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch0_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch0_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch0_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch0_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___lsb 19
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___width 1
-#define reg_bif_dma_rw_ch0_ctrl___wr_all___bit 19
-#define reg_bif_dma_rw_ch0_ctrl_offset 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch0_addr___addr___width 32
-#define reg_bif_dma_rw_ch0_addr_offset 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_start___run___lsb 0
-#define reg_bif_dma_rw_ch0_start___run___width 1
-#define reg_bif_dma_rw_ch0_start___run___bit 0
-#define reg_bif_dma_rw_ch0_start_offset 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch0_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch0_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch0_cnt_offset 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch0_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch0_stat___cnt___width 16
-#define reg_bif_dma_r_ch0_stat___run___lsb 31
-#define reg_bif_dma_r_ch0_stat___run___width 1
-#define reg_bif_dma_r_ch0_stat___run___bit 31
-#define reg_bif_dma_r_ch0_stat_offset 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch1_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch1_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch1_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch1_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch1_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___lsb 4
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___width 1
-#define reg_bif_dma_rw_ch1_ctrl___end_discard___bit 4
-#define reg_bif_dma_rw_ch1_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch1_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch1_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch1_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch1_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch1_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch1_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch1_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch1_ctrl_offset 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch1_addr___addr___width 32
-#define reg_bif_dma_rw_ch1_addr_offset 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_start___run___lsb 0
-#define reg_bif_dma_rw_ch1_start___run___width 1
-#define reg_bif_dma_rw_ch1_start___run___bit 0
-#define reg_bif_dma_rw_ch1_start_offset 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch1_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch1_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch1_cnt_offset 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch1_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch1_stat___cnt___width 16
-#define reg_bif_dma_r_ch1_stat___run___lsb 31
-#define reg_bif_dma_r_ch1_stat___run___width 1
-#define reg_bif_dma_r_ch1_stat___run___bit 31
-#define reg_bif_dma_r_ch1_stat_offset 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch2_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch2_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch2_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch2_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch2_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___lsb 4
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___width 1
-#define reg_bif_dma_rw_ch2_ctrl___end_pad___bit 4
-#define reg_bif_dma_rw_ch2_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch2_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch2_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch2_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch2_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch2_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch2_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch2_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___lsb 19
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___width 1
-#define reg_bif_dma_rw_ch2_ctrl___wr_all___bit 19
-#define reg_bif_dma_rw_ch2_ctrl_offset 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch2_addr___addr___width 32
-#define reg_bif_dma_rw_ch2_addr_offset 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_start___run___lsb 0
-#define reg_bif_dma_rw_ch2_start___run___width 1
-#define reg_bif_dma_rw_ch2_start___run___bit 0
-#define reg_bif_dma_rw_ch2_start_offset 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch2_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch2_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch2_cnt_offset 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch2_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch2_stat___cnt___width 16
-#define reg_bif_dma_r_ch2_stat___run___lsb 31
-#define reg_bif_dma_r_ch2_stat___run___width 1
-#define reg_bif_dma_r_ch2_stat___run___bit 31
-#define reg_bif_dma_r_ch2_stat_offset 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_ctrl___bw___lsb 0
-#define reg_bif_dma_rw_ch3_ctrl___bw___width 2
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___lsb 2
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___width 1
-#define reg_bif_dma_rw_ch3_ctrl___burst_len___bit 2
-#define reg_bif_dma_rw_ch3_ctrl___cont___lsb 3
-#define reg_bif_dma_rw_ch3_ctrl___cont___width 1
-#define reg_bif_dma_rw_ch3_ctrl___cont___bit 3
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___lsb 4
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___width 1
-#define reg_bif_dma_rw_ch3_ctrl___end_discard___bit 4
-#define reg_bif_dma_rw_ch3_ctrl___cnt___lsb 5
-#define reg_bif_dma_rw_ch3_ctrl___cnt___width 1
-#define reg_bif_dma_rw_ch3_ctrl___cnt___bit 5
-#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___lsb 6
-#define reg_bif_dma_rw_ch3_ctrl___dreq_pin___width 3
-#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___lsb 9
-#define reg_bif_dma_rw_ch3_ctrl___dreq_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___lsb 11
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_pin___width 3
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___lsb 14
-#define reg_bif_dma_rw_ch3_ctrl___tc_in_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___bus_mode___lsb 16
-#define reg_bif_dma_rw_ch3_ctrl___bus_mode___width 2
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___lsb 18
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___width 1
-#define reg_bif_dma_rw_ch3_ctrl___rate_en___bit 18
-#define reg_bif_dma_rw_ch3_ctrl_offset 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_addr___addr___lsb 0
-#define reg_bif_dma_rw_ch3_addr___addr___width 32
-#define reg_bif_dma_rw_ch3_addr_offset 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_start___run___lsb 0
-#define reg_bif_dma_rw_ch3_start___run___width 1
-#define reg_bif_dma_rw_ch3_start___run___bit 0
-#define reg_bif_dma_rw_ch3_start_offset 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ch3_cnt___start_cnt___lsb 0
-#define reg_bif_dma_rw_ch3_cnt___start_cnt___width 16
-#define reg_bif_dma_rw_ch3_cnt_offset 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_ch3_stat___cnt___lsb 0
-#define reg_bif_dma_r_ch3_stat___cnt___width 16
-#define reg_bif_dma_r_ch3_stat___run___lsb 31
-#define reg_bif_dma_r_ch3_stat___run___width 1
-#define reg_bif_dma_r_ch3_stat___run___bit 31
-#define reg_bif_dma_r_ch3_stat_offset 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-#define reg_bif_dma_rw_intr_mask___ext_dma0___lsb 0
-#define reg_bif_dma_rw_intr_mask___ext_dma0___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma0___bit 0
-#define reg_bif_dma_rw_intr_mask___ext_dma1___lsb 1
-#define reg_bif_dma_rw_intr_mask___ext_dma1___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma1___bit 1
-#define reg_bif_dma_rw_intr_mask___ext_dma2___lsb 2
-#define reg_bif_dma_rw_intr_mask___ext_dma2___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma2___bit 2
-#define reg_bif_dma_rw_intr_mask___ext_dma3___lsb 3
-#define reg_bif_dma_rw_intr_mask___ext_dma3___width 1
-#define reg_bif_dma_rw_intr_mask___ext_dma3___bit 3
-#define reg_bif_dma_rw_intr_mask_offset 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-#define reg_bif_dma_rw_ack_intr___ext_dma0___lsb 0
-#define reg_bif_dma_rw_ack_intr___ext_dma0___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma0___bit 0
-#define reg_bif_dma_rw_ack_intr___ext_dma1___lsb 1
-#define reg_bif_dma_rw_ack_intr___ext_dma1___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma1___bit 1
-#define reg_bif_dma_rw_ack_intr___ext_dma2___lsb 2
-#define reg_bif_dma_rw_ack_intr___ext_dma2___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma2___bit 2
-#define reg_bif_dma_rw_ack_intr___ext_dma3___lsb 3
-#define reg_bif_dma_rw_ack_intr___ext_dma3___width 1
-#define reg_bif_dma_rw_ack_intr___ext_dma3___bit 3
-#define reg_bif_dma_rw_ack_intr_offset 132
-
-/* Register r_intr, scope bif_dma, type r */
-#define reg_bif_dma_r_intr___ext_dma0___lsb 0
-#define reg_bif_dma_r_intr___ext_dma0___width 1
-#define reg_bif_dma_r_intr___ext_dma0___bit 0
-#define reg_bif_dma_r_intr___ext_dma1___lsb 1
-#define reg_bif_dma_r_intr___ext_dma1___width 1
-#define reg_bif_dma_r_intr___ext_dma1___bit 1
-#define reg_bif_dma_r_intr___ext_dma2___lsb 2
-#define reg_bif_dma_r_intr___ext_dma2___width 1
-#define reg_bif_dma_r_intr___ext_dma2___bit 2
-#define reg_bif_dma_r_intr___ext_dma3___lsb 3
-#define reg_bif_dma_r_intr___ext_dma3___width 1
-#define reg_bif_dma_r_intr___ext_dma3___bit 3
-#define reg_bif_dma_r_intr_offset 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-#define reg_bif_dma_r_masked_intr___ext_dma0___lsb 0
-#define reg_bif_dma_r_masked_intr___ext_dma0___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma0___bit 0
-#define reg_bif_dma_r_masked_intr___ext_dma1___lsb 1
-#define reg_bif_dma_r_masked_intr___ext_dma1___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma1___bit 1
-#define reg_bif_dma_r_masked_intr___ext_dma2___lsb 2
-#define reg_bif_dma_r_masked_intr___ext_dma2___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma2___bit 2
-#define reg_bif_dma_r_masked_intr___ext_dma3___lsb 3
-#define reg_bif_dma_r_masked_intr___ext_dma3___width 1
-#define reg_bif_dma_r_masked_intr___ext_dma3___bit 3
-#define reg_bif_dma_r_masked_intr_offset 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin0_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin0_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin0_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin0_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin0_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin0_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin0_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin0_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin0_cfg_offset 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin1_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin1_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin1_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin1_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin1_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin1_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin1_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin1_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin1_cfg_offset 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin2_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin2_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin2_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin2_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin2_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin2_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin2_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin2_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin2_cfg_offset 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin3_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin3_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin3_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin3_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin3_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin3_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin3_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin3_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin3_cfg_offset 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin4_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin4_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin4_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin4_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin4_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin4_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin4_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin4_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin4_cfg_offset 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin5_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin5_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin5_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin5_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin5_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin5_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin5_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin5_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin5_cfg_offset 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin6_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin6_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin6_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin6_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin6_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin6_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin6_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin6_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin6_cfg_offset 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-#define reg_bif_dma_rw_pin7_cfg___master_ch___lsb 0
-#define reg_bif_dma_rw_pin7_cfg___master_ch___width 2
-#define reg_bif_dma_rw_pin7_cfg___master_mode___lsb 2
-#define reg_bif_dma_rw_pin7_cfg___master_mode___width 3
-#define reg_bif_dma_rw_pin7_cfg___slave_ch___lsb 5
-#define reg_bif_dma_rw_pin7_cfg___slave_ch___width 2
-#define reg_bif_dma_rw_pin7_cfg___slave_mode___lsb 7
-#define reg_bif_dma_rw_pin7_cfg___slave_mode___width 3
-#define reg_bif_dma_rw_pin7_cfg_offset 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-#define reg_bif_dma_r_pin_stat___pin0___lsb 0
-#define reg_bif_dma_r_pin_stat___pin0___width 1
-#define reg_bif_dma_r_pin_stat___pin0___bit 0
-#define reg_bif_dma_r_pin_stat___pin1___lsb 1
-#define reg_bif_dma_r_pin_stat___pin1___width 1
-#define reg_bif_dma_r_pin_stat___pin1___bit 1
-#define reg_bif_dma_r_pin_stat___pin2___lsb 2
-#define reg_bif_dma_r_pin_stat___pin2___width 1
-#define reg_bif_dma_r_pin_stat___pin2___bit 2
-#define reg_bif_dma_r_pin_stat___pin3___lsb 3
-#define reg_bif_dma_r_pin_stat___pin3___width 1
-#define reg_bif_dma_r_pin_stat___pin3___bit 3
-#define reg_bif_dma_r_pin_stat___pin4___lsb 4
-#define reg_bif_dma_r_pin_stat___pin4___width 1
-#define reg_bif_dma_r_pin_stat___pin4___bit 4
-#define reg_bif_dma_r_pin_stat___pin5___lsb 5
-#define reg_bif_dma_r_pin_stat___pin5___width 1
-#define reg_bif_dma_r_pin_stat___pin5___bit 5
-#define reg_bif_dma_r_pin_stat___pin6___lsb 6
-#define reg_bif_dma_r_pin_stat___pin6___width 1
-#define reg_bif_dma_r_pin_stat___pin6___bit 6
-#define reg_bif_dma_r_pin_stat___pin7___lsb 7
-#define reg_bif_dma_r_pin_stat___pin7___width 1
-#define reg_bif_dma_r_pin_stat___pin7___bit 7
-#define reg_bif_dma_r_pin_stat_offset 192
-
-
-/* Constants */
-#define regk_bif_dma_as_master 0x00000001
-#define regk_bif_dma_as_slave 0x00000001
-#define regk_bif_dma_burst1 0x00000000
-#define regk_bif_dma_burst8 0x00000001
-#define regk_bif_dma_bw16 0x00000001
-#define regk_bif_dma_bw32 0x00000002
-#define regk_bif_dma_bw8 0x00000000
-#define regk_bif_dma_dack 0x00000006
-#define regk_bif_dma_dack_inv 0x00000007
-#define regk_bif_dma_force 0x00000001
-#define regk_bif_dma_hi 0x00000003
-#define regk_bif_dma_inv 0x00000003
-#define regk_bif_dma_lo 0x00000002
-#define regk_bif_dma_master 0x00000001
-#define regk_bif_dma_no 0x00000000
-#define regk_bif_dma_norm 0x00000002
-#define regk_bif_dma_off 0x00000000
-#define regk_bif_dma_rw_ch0_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch0_start_default 0x00000000
-#define regk_bif_dma_rw_ch1_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch1_start_default 0x00000000
-#define regk_bif_dma_rw_ch2_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch2_start_default 0x00000000
-#define regk_bif_dma_rw_ch3_ctrl_default 0x00000000
-#define regk_bif_dma_rw_ch3_start_default 0x00000000
-#define regk_bif_dma_rw_intr_mask_default 0x00000000
-#define regk_bif_dma_rw_pin0_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin1_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin2_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin3_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin4_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin5_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin6_cfg_default 0x00000000
-#define regk_bif_dma_rw_pin7_cfg_default 0x00000000
-#define regk_bif_dma_slave 0x00000002
-#define regk_bif_dma_sreq 0x00000006
-#define regk_bif_dma_sreq_inv 0x00000007
-#define regk_bif_dma_tc 0x00000004
-#define regk_bif_dma_tc_inv 0x00000005
-#define regk_bif_dma_yes 0x00000001
-#endif /* __bif_dma_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h
deleted file mode 100644
index 55697fec603e..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/bif_slave_defs_asm.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_slave_defs_asm_h
-#define __bif_slave_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_slave_regs.r
- * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- * last modfied: Mon Apr 11 16:06:34 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_slave_defs_asm.h ../../inst/bif/rtl/bif_slave_regs.r
- * id: $Id: bif_slave_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_slave_cfg___slave_id___lsb 0
-#define reg_bif_slave_rw_slave_cfg___slave_id___width 3
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___lsb 3
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___width 1
-#define reg_bif_slave_rw_slave_cfg___use_slave_id___bit 3
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___lsb 4
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___width 1
-#define reg_bif_slave_rw_slave_cfg___boot_rdy___bit 4
-#define reg_bif_slave_rw_slave_cfg___loopback___lsb 5
-#define reg_bif_slave_rw_slave_cfg___loopback___width 1
-#define reg_bif_slave_rw_slave_cfg___loopback___bit 5
-#define reg_bif_slave_rw_slave_cfg___dis___lsb 6
-#define reg_bif_slave_rw_slave_cfg___dis___width 1
-#define reg_bif_slave_rw_slave_cfg___dis___bit 6
-#define reg_bif_slave_rw_slave_cfg_offset 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-#define reg_bif_slave_r_slave_mode___ch0_mode___lsb 0
-#define reg_bif_slave_r_slave_mode___ch0_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch0_mode___bit 0
-#define reg_bif_slave_r_slave_mode___ch1_mode___lsb 1
-#define reg_bif_slave_r_slave_mode___ch1_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch1_mode___bit 1
-#define reg_bif_slave_r_slave_mode___ch2_mode___lsb 2
-#define reg_bif_slave_r_slave_mode___ch2_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch2_mode___bit 2
-#define reg_bif_slave_r_slave_mode___ch3_mode___lsb 3
-#define reg_bif_slave_r_slave_mode___ch3_mode___width 1
-#define reg_bif_slave_r_slave_mode___ch3_mode___bit 3
-#define reg_bif_slave_r_slave_mode_offset 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch0_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch0_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch0_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch0_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch0_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch0_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch0_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch0_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch0_cfg_offset 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch1_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch1_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch1_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch1_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch1_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch1_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch1_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch1_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch1_cfg_offset 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch2_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch2_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch2_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch2_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch2_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch2_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch2_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch2_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch2_cfg_offset 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ch3_cfg___rd_hold___lsb 0
-#define reg_bif_slave_rw_ch3_cfg___rd_hold___width 2
-#define reg_bif_slave_rw_ch3_cfg___access_mode___lsb 2
-#define reg_bif_slave_rw_ch3_cfg___access_mode___width 1
-#define reg_bif_slave_rw_ch3_cfg___access_mode___bit 2
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___lsb 3
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___width 1
-#define reg_bif_slave_rw_ch3_cfg___access_ctrl___bit 3
-#define reg_bif_slave_rw_ch3_cfg___data_cs___lsb 4
-#define reg_bif_slave_rw_ch3_cfg___data_cs___width 2
-#define reg_bif_slave_rw_ch3_cfg_offset 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-#define reg_bif_slave_rw_arb_cfg___brin_mode___lsb 0
-#define reg_bif_slave_rw_arb_cfg___brin_mode___width 1
-#define reg_bif_slave_rw_arb_cfg___brin_mode___bit 0
-#define reg_bif_slave_rw_arb_cfg___brout_mode___lsb 1
-#define reg_bif_slave_rw_arb_cfg___brout_mode___width 3
-#define reg_bif_slave_rw_arb_cfg___bg_mode___lsb 4
-#define reg_bif_slave_rw_arb_cfg___bg_mode___width 3
-#define reg_bif_slave_rw_arb_cfg___release___lsb 7
-#define reg_bif_slave_rw_arb_cfg___release___width 2
-#define reg_bif_slave_rw_arb_cfg___acquire___lsb 9
-#define reg_bif_slave_rw_arb_cfg___acquire___width 1
-#define reg_bif_slave_rw_arb_cfg___acquire___bit 9
-#define reg_bif_slave_rw_arb_cfg___settle_time___lsb 10
-#define reg_bif_slave_rw_arb_cfg___settle_time___width 2
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___lsb 12
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___width 1
-#define reg_bif_slave_rw_arb_cfg___dram_ctrl___bit 12
-#define reg_bif_slave_rw_arb_cfg_offset 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-#define reg_bif_slave_r_arb_stat___init_mode___lsb 0
-#define reg_bif_slave_r_arb_stat___init_mode___width 1
-#define reg_bif_slave_r_arb_stat___init_mode___bit 0
-#define reg_bif_slave_r_arb_stat___mode___lsb 1
-#define reg_bif_slave_r_arb_stat___mode___width 1
-#define reg_bif_slave_r_arb_stat___mode___bit 1
-#define reg_bif_slave_r_arb_stat___brin___lsb 2
-#define reg_bif_slave_r_arb_stat___brin___width 1
-#define reg_bif_slave_r_arb_stat___brin___bit 2
-#define reg_bif_slave_r_arb_stat___brout___lsb 3
-#define reg_bif_slave_r_arb_stat___brout___width 1
-#define reg_bif_slave_r_arb_stat___brout___bit 3
-#define reg_bif_slave_r_arb_stat___bg___lsb 4
-#define reg_bif_slave_r_arb_stat___bg___width 1
-#define reg_bif_slave_r_arb_stat___bg___bit 4
-#define reg_bif_slave_r_arb_stat_offset 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-#define reg_bif_slave_rw_intr_mask___bus_release___lsb 0
-#define reg_bif_slave_rw_intr_mask___bus_release___width 1
-#define reg_bif_slave_rw_intr_mask___bus_release___bit 0
-#define reg_bif_slave_rw_intr_mask___bus_acquire___lsb 1
-#define reg_bif_slave_rw_intr_mask___bus_acquire___width 1
-#define reg_bif_slave_rw_intr_mask___bus_acquire___bit 1
-#define reg_bif_slave_rw_intr_mask_offset 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-#define reg_bif_slave_rw_ack_intr___bus_release___lsb 0
-#define reg_bif_slave_rw_ack_intr___bus_release___width 1
-#define reg_bif_slave_rw_ack_intr___bus_release___bit 0
-#define reg_bif_slave_rw_ack_intr___bus_acquire___lsb 1
-#define reg_bif_slave_rw_ack_intr___bus_acquire___width 1
-#define reg_bif_slave_rw_ack_intr___bus_acquire___bit 1
-#define reg_bif_slave_rw_ack_intr_offset 68
-
-/* Register r_intr, scope bif_slave, type r */
-#define reg_bif_slave_r_intr___bus_release___lsb 0
-#define reg_bif_slave_r_intr___bus_release___width 1
-#define reg_bif_slave_r_intr___bus_release___bit 0
-#define reg_bif_slave_r_intr___bus_acquire___lsb 1
-#define reg_bif_slave_r_intr___bus_acquire___width 1
-#define reg_bif_slave_r_intr___bus_acquire___bit 1
-#define reg_bif_slave_r_intr_offset 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-#define reg_bif_slave_r_masked_intr___bus_release___lsb 0
-#define reg_bif_slave_r_masked_intr___bus_release___width 1
-#define reg_bif_slave_r_masked_intr___bus_release___bit 0
-#define reg_bif_slave_r_masked_intr___bus_acquire___lsb 1
-#define reg_bif_slave_r_masked_intr___bus_acquire___width 1
-#define reg_bif_slave_r_masked_intr___bus_acquire___bit 1
-#define reg_bif_slave_r_masked_intr_offset 76
-
-
-/* Constants */
-#define regk_bif_slave_active_hi 0x00000003
-#define regk_bif_slave_active_lo 0x00000002
-#define regk_bif_slave_addr 0x00000000
-#define regk_bif_slave_always 0x00000001
-#define regk_bif_slave_at_idle 0x00000002
-#define regk_bif_slave_burst_end 0x00000003
-#define regk_bif_slave_dma 0x00000001
-#define regk_bif_slave_hi 0x00000003
-#define regk_bif_slave_inv 0x00000001
-#define regk_bif_slave_lo 0x00000002
-#define regk_bif_slave_local 0x00000001
-#define regk_bif_slave_master 0x00000000
-#define regk_bif_slave_mode_reg 0x00000001
-#define regk_bif_slave_no 0x00000000
-#define regk_bif_slave_norm 0x00000000
-#define regk_bif_slave_on_access 0x00000000
-#define regk_bif_slave_rw_arb_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch0_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch1_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch2_cfg_default 0x00000000
-#define regk_bif_slave_rw_ch3_cfg_default 0x00000000
-#define regk_bif_slave_rw_intr_mask_default 0x00000000
-#define regk_bif_slave_rw_slave_cfg_default 0x00000000
-#define regk_bif_slave_shared 0x00000000
-#define regk_bif_slave_slave 0x00000001
-#define regk_bif_slave_t0ns 0x00000003
-#define regk_bif_slave_t10ns 0x00000002
-#define regk_bif_slave_t20ns 0x00000003
-#define regk_bif_slave_t30ns 0x00000002
-#define regk_bif_slave_t40ns 0x00000001
-#define regk_bif_slave_t50ns 0x00000000
-#define regk_bif_slave_yes 0x00000001
-#define regk_bif_slave_z 0x00000004
-#endif /* __bif_slave_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h
deleted file mode 100644
index 6455b4897bcc..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/config_defs_asm.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_asm_h
-#define __config_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
- * id: $Id: config_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope config, type r */
-#define reg_config_r_bootsel___boot_mode___lsb 0
-#define reg_config_r_bootsel___boot_mode___width 3
-#define reg_config_r_bootsel___full_duplex___lsb 3
-#define reg_config_r_bootsel___full_duplex___width 1
-#define reg_config_r_bootsel___full_duplex___bit 3
-#define reg_config_r_bootsel___user___lsb 4
-#define reg_config_r_bootsel___user___width 1
-#define reg_config_r_bootsel___user___bit 4
-#define reg_config_r_bootsel___pll___lsb 5
-#define reg_config_r_bootsel___pll___width 1
-#define reg_config_r_bootsel___pll___bit 5
-#define reg_config_r_bootsel___flash_bw___lsb 6
-#define reg_config_r_bootsel___flash_bw___width 1
-#define reg_config_r_bootsel___flash_bw___bit 6
-#define reg_config_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-#define reg_config_rw_clk_ctrl___pll___lsb 0
-#define reg_config_rw_clk_ctrl___pll___width 1
-#define reg_config_rw_clk_ctrl___pll___bit 0
-#define reg_config_rw_clk_ctrl___cpu___lsb 1
-#define reg_config_rw_clk_ctrl___cpu___width 1
-#define reg_config_rw_clk_ctrl___cpu___bit 1
-#define reg_config_rw_clk_ctrl___iop___lsb 2
-#define reg_config_rw_clk_ctrl___iop___width 1
-#define reg_config_rw_clk_ctrl___iop___bit 2
-#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
-#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
-#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
-#define reg_config_rw_clk_ctrl___dma23___lsb 4
-#define reg_config_rw_clk_ctrl___dma23___width 1
-#define reg_config_rw_clk_ctrl___dma23___bit 4
-#define reg_config_rw_clk_ctrl___dma45___lsb 5
-#define reg_config_rw_clk_ctrl___dma45___width 1
-#define reg_config_rw_clk_ctrl___dma45___bit 5
-#define reg_config_rw_clk_ctrl___dma67___lsb 6
-#define reg_config_rw_clk_ctrl___dma67___width 1
-#define reg_config_rw_clk_ctrl___dma67___bit 6
-#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
-#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
-#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
-#define reg_config_rw_clk_ctrl___bif___lsb 8
-#define reg_config_rw_clk_ctrl___bif___width 1
-#define reg_config_rw_clk_ctrl___bif___bit 8
-#define reg_config_rw_clk_ctrl___fix_io___lsb 9
-#define reg_config_rw_clk_ctrl___fix_io___width 1
-#define reg_config_rw_clk_ctrl___fix_io___bit 9
-#define reg_config_rw_clk_ctrl_offset 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
-#define reg_config_rw_pad_ctrl___usb_susp___width 1
-#define reg_config_rw_pad_ctrl___usb_susp___bit 0
-#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
-#define reg_config_rw_pad_ctrl___phyrst_n___width 1
-#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
-#define reg_config_rw_pad_ctrl_offset 8
-
-
-/* Constants */
-#define regk_config_bw16 0x00000000
-#define regk_config_bw32 0x00000001
-#define regk_config_master 0x00000005
-#define regk_config_nand 0x00000003
-#define regk_config_net_rx 0x00000001
-#define regk_config_net_tx_rx 0x00000002
-#define regk_config_no 0x00000000
-#define regk_config_none 0x00000007
-#define regk_config_nor 0x00000000
-#define regk_config_rw_clk_ctrl_default 0x00000002
-#define regk_config_rw_pad_ctrl_default 0x00000000
-#define regk_config_ser 0x00000004
-#define regk_config_slave 0x00000006
-#define regk_config_yes 0x00000001
-#endif /* __config_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h
deleted file mode 100644
index 8370aee8a14a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/cpu_vect.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/crisp/doc/cpu_vect.r
-version . */
-
-#ifndef _______INST_CRISP_DOC_CPU_VECT_R
-#define _______INST_CRISP_DOC_CPU_VECT_R
-#define NMI_INTR_VECT 0x00
-#define RESERVED_1_INTR_VECT 0x01
-#define RESERVED_2_INTR_VECT 0x02
-#define SINGLE_STEP_INTR_VECT 0x03
-#define INSTR_TLB_REFILL_INTR_VECT 0x04
-#define INSTR_TLB_INV_INTR_VECT 0x05
-#define INSTR_TLB_ACC_INTR_VECT 0x06
-#define TLB_EX_INTR_VECT 0x07
-#define DATA_TLB_REFILL_INTR_VECT 0x08
-#define DATA_TLB_INV_INTR_VECT 0x09
-#define DATA_TLB_ACC_INTR_VECT 0x0a
-#define DATA_TLB_WE_INTR_VECT 0x0b
-#define HW_BP_INTR_VECT 0x0c
-#define RESERVED_D_INTR_VECT 0x0d
-#define RESERVED_E_INTR_VECT 0x0e
-#define RESERVED_F_INTR_VECT 0x0f
-#define BREAK_0_INTR_VECT 0x10
-#define BREAK_1_INTR_VECT 0x11
-#define BREAK_2_INTR_VECT 0x12
-#define BREAK_3_INTR_VECT 0x13
-#define BREAK_4_INTR_VECT 0x14
-#define BREAK_5_INTR_VECT 0x15
-#define BREAK_6_INTR_VECT 0x16
-#define BREAK_7_INTR_VECT 0x17
-#define BREAK_8_INTR_VECT 0x18
-#define BREAK_9_INTR_VECT 0x19
-#define BREAK_10_INTR_VECT 0x1a
-#define BREAK_11_INTR_VECT 0x1b
-#define BREAK_12_INTR_VECT 0x1c
-#define BREAK_13_INTR_VECT 0x1d
-#define BREAK_14_INTR_VECT 0x1e
-#define BREAK_15_INTR_VECT 0x1f
-#define MULTIPLE_INTR_VECT 0x30
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h
deleted file mode 100644
index bd048296d2f8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_defs_asm.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __cris_defs_asm_h
-#define __cris_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/crisp/doc/cris.r
- * id: cris.r,v 1.6 2004/05/05 07:41:12 perz Exp
- * last modfied: Mon Apr 11 16:06:39 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/cris_defs_asm.h ../../inst/crisp/doc/cris.r
- * id: $Id: cris_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gc_cfg, scope cris, type rw */
-#define reg_cris_rw_gc_cfg___ic___lsb 0
-#define reg_cris_rw_gc_cfg___ic___width 1
-#define reg_cris_rw_gc_cfg___ic___bit 0
-#define reg_cris_rw_gc_cfg___dc___lsb 1
-#define reg_cris_rw_gc_cfg___dc___width 1
-#define reg_cris_rw_gc_cfg___dc___bit 1
-#define reg_cris_rw_gc_cfg___im___lsb 2
-#define reg_cris_rw_gc_cfg___im___width 1
-#define reg_cris_rw_gc_cfg___im___bit 2
-#define reg_cris_rw_gc_cfg___dm___lsb 3
-#define reg_cris_rw_gc_cfg___dm___width 1
-#define reg_cris_rw_gc_cfg___dm___bit 3
-#define reg_cris_rw_gc_cfg___gb___lsb 4
-#define reg_cris_rw_gc_cfg___gb___width 1
-#define reg_cris_rw_gc_cfg___gb___bit 4
-#define reg_cris_rw_gc_cfg___gk___lsb 5
-#define reg_cris_rw_gc_cfg___gk___width 1
-#define reg_cris_rw_gc_cfg___gk___bit 5
-#define reg_cris_rw_gc_cfg___gp___lsb 6
-#define reg_cris_rw_gc_cfg___gp___width 1
-#define reg_cris_rw_gc_cfg___gp___bit 6
-#define reg_cris_rw_gc_cfg_offset 0
-
-/* Register rw_gc_ccs, scope cris, type rw */
-#define reg_cris_rw_gc_ccs_offset 4
-
-/* Register rw_gc_srs, scope cris, type rw */
-#define reg_cris_rw_gc_srs___srs___lsb 0
-#define reg_cris_rw_gc_srs___srs___width 8
-#define reg_cris_rw_gc_srs_offset 8
-
-/* Register rw_gc_nrp, scope cris, type rw */
-#define reg_cris_rw_gc_nrp_offset 12
-
-/* Register rw_gc_exs, scope cris, type rw */
-#define reg_cris_rw_gc_exs_offset 16
-
-/* Register rw_gc_eda, scope cris, type rw */
-#define reg_cris_rw_gc_eda_offset 20
-
-/* Register rw_gc_r0, scope cris, type rw */
-#define reg_cris_rw_gc_r0_offset 32
-
-/* Register rw_gc_r1, scope cris, type rw */
-#define reg_cris_rw_gc_r1_offset 36
-
-/* Register rw_gc_r2, scope cris, type rw */
-#define reg_cris_rw_gc_r2_offset 40
-
-/* Register rw_gc_r3, scope cris, type rw */
-#define reg_cris_rw_gc_r3_offset 44
-
-
-/* Constants */
-#define regk_cris_no 0x00000000
-#define regk_cris_rw_gc_cfg_default 0x00000000
-#define regk_cris_yes 0x00000001
-#endif /* __cris_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h
deleted file mode 100644
index 429fe0d4ffe4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/cris_supp_reg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#define RW_GC_CFG 0
-#define RW_GC_CCS 1
-#define RW_GC_SRS 2
-#define RW_GC_NRP 3
-#define RW_GC_EXS 4
-#define RW_GC_EDA 5
-#define RW_GC_R0 8
-#define RW_GC_R1 9
-#define RW_GC_R2 10
-#define RW_GC_R3 11
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h
deleted file mode 100644
index fec451d2a3db..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/dma_defs_asm.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __dma_defs_asm_h
-#define __dma_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
- * last modfied: Mon Apr 11 16:06:51 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/dma_defs_asm.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: $Id: dma_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_data, scope dma, type rw */
-#define reg_dma_rw_data_offset 0
-
-/* Register rw_data_next, scope dma, type rw */
-#define reg_dma_rw_data_next_offset 4
-
-/* Register rw_data_buf, scope dma, type rw */
-#define reg_dma_rw_data_buf_offset 8
-
-/* Register rw_data_ctrl, scope dma, type rw */
-#define reg_dma_rw_data_ctrl___eol___lsb 0
-#define reg_dma_rw_data_ctrl___eol___width 1
-#define reg_dma_rw_data_ctrl___eol___bit 0
-#define reg_dma_rw_data_ctrl___out_eop___lsb 3
-#define reg_dma_rw_data_ctrl___out_eop___width 1
-#define reg_dma_rw_data_ctrl___out_eop___bit 3
-#define reg_dma_rw_data_ctrl___intr___lsb 4
-#define reg_dma_rw_data_ctrl___intr___width 1
-#define reg_dma_rw_data_ctrl___intr___bit 4
-#define reg_dma_rw_data_ctrl___wait___lsb 5
-#define reg_dma_rw_data_ctrl___wait___width 1
-#define reg_dma_rw_data_ctrl___wait___bit 5
-#define reg_dma_rw_data_ctrl_offset 12
-
-/* Register rw_data_stat, scope dma, type rw */
-#define reg_dma_rw_data_stat___in_eop___lsb 3
-#define reg_dma_rw_data_stat___in_eop___width 1
-#define reg_dma_rw_data_stat___in_eop___bit 3
-#define reg_dma_rw_data_stat_offset 16
-
-/* Register rw_data_md, scope dma, type rw */
-#define reg_dma_rw_data_md___md___lsb 0
-#define reg_dma_rw_data_md___md___width 16
-#define reg_dma_rw_data_md_offset 20
-
-/* Register rw_data_md_s, scope dma, type rw */
-#define reg_dma_rw_data_md_s___md_s___lsb 0
-#define reg_dma_rw_data_md_s___md_s___width 16
-#define reg_dma_rw_data_md_s_offset 24
-
-/* Register rw_data_after, scope dma, type rw */
-#define reg_dma_rw_data_after_offset 28
-
-/* Register rw_ctxt, scope dma, type rw */
-#define reg_dma_rw_ctxt_offset 32
-
-/* Register rw_ctxt_next, scope dma, type rw */
-#define reg_dma_rw_ctxt_next_offset 36
-
-/* Register rw_ctxt_ctrl, scope dma, type rw */
-#define reg_dma_rw_ctxt_ctrl___eol___lsb 0
-#define reg_dma_rw_ctxt_ctrl___eol___width 1
-#define reg_dma_rw_ctxt_ctrl___eol___bit 0
-#define reg_dma_rw_ctxt_ctrl___intr___lsb 4
-#define reg_dma_rw_ctxt_ctrl___intr___width 1
-#define reg_dma_rw_ctxt_ctrl___intr___bit 4
-#define reg_dma_rw_ctxt_ctrl___store_mode___lsb 6
-#define reg_dma_rw_ctxt_ctrl___store_mode___width 1
-#define reg_dma_rw_ctxt_ctrl___store_mode___bit 6
-#define reg_dma_rw_ctxt_ctrl___en___lsb 7
-#define reg_dma_rw_ctxt_ctrl___en___width 1
-#define reg_dma_rw_ctxt_ctrl___en___bit 7
-#define reg_dma_rw_ctxt_ctrl_offset 40
-
-/* Register rw_ctxt_stat, scope dma, type rw */
-#define reg_dma_rw_ctxt_stat___dis___lsb 7
-#define reg_dma_rw_ctxt_stat___dis___width 1
-#define reg_dma_rw_ctxt_stat___dis___bit 7
-#define reg_dma_rw_ctxt_stat_offset 44
-
-/* Register rw_ctxt_md0, scope dma, type rw */
-#define reg_dma_rw_ctxt_md0___md0___lsb 0
-#define reg_dma_rw_ctxt_md0___md0___width 16
-#define reg_dma_rw_ctxt_md0_offset 48
-
-/* Register rw_ctxt_md0_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md0_s___md0_s___lsb 0
-#define reg_dma_rw_ctxt_md0_s___md0_s___width 16
-#define reg_dma_rw_ctxt_md0_s_offset 52
-
-/* Register rw_ctxt_md1, scope dma, type rw */
-#define reg_dma_rw_ctxt_md1_offset 56
-
-/* Register rw_ctxt_md1_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md1_s_offset 60
-
-/* Register rw_ctxt_md2, scope dma, type rw */
-#define reg_dma_rw_ctxt_md2_offset 64
-
-/* Register rw_ctxt_md2_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md2_s_offset 68
-
-/* Register rw_ctxt_md3, scope dma, type rw */
-#define reg_dma_rw_ctxt_md3_offset 72
-
-/* Register rw_ctxt_md3_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md3_s_offset 76
-
-/* Register rw_ctxt_md4, scope dma, type rw */
-#define reg_dma_rw_ctxt_md4_offset 80
-
-/* Register rw_ctxt_md4_s, scope dma, type rw */
-#define reg_dma_rw_ctxt_md4_s_offset 84
-
-/* Register rw_saved_data, scope dma, type rw */
-#define reg_dma_rw_saved_data_offset 88
-
-/* Register rw_saved_data_buf, scope dma, type rw */
-#define reg_dma_rw_saved_data_buf_offset 92
-
-/* Register rw_group, scope dma, type rw */
-#define reg_dma_rw_group_offset 96
-
-/* Register rw_group_next, scope dma, type rw */
-#define reg_dma_rw_group_next_offset 100
-
-/* Register rw_group_ctrl, scope dma, type rw */
-#define reg_dma_rw_group_ctrl___eol___lsb 0
-#define reg_dma_rw_group_ctrl___eol___width 1
-#define reg_dma_rw_group_ctrl___eol___bit 0
-#define reg_dma_rw_group_ctrl___tol___lsb 1
-#define reg_dma_rw_group_ctrl___tol___width 1
-#define reg_dma_rw_group_ctrl___tol___bit 1
-#define reg_dma_rw_group_ctrl___bol___lsb 2
-#define reg_dma_rw_group_ctrl___bol___width 1
-#define reg_dma_rw_group_ctrl___bol___bit 2
-#define reg_dma_rw_group_ctrl___intr___lsb 4
-#define reg_dma_rw_group_ctrl___intr___width 1
-#define reg_dma_rw_group_ctrl___intr___bit 4
-#define reg_dma_rw_group_ctrl___en___lsb 7
-#define reg_dma_rw_group_ctrl___en___width 1
-#define reg_dma_rw_group_ctrl___en___bit 7
-#define reg_dma_rw_group_ctrl_offset 104
-
-/* Register rw_group_stat, scope dma, type rw */
-#define reg_dma_rw_group_stat___dis___lsb 7
-#define reg_dma_rw_group_stat___dis___width 1
-#define reg_dma_rw_group_stat___dis___bit 7
-#define reg_dma_rw_group_stat_offset 108
-
-/* Register rw_group_md, scope dma, type rw */
-#define reg_dma_rw_group_md___md___lsb 0
-#define reg_dma_rw_group_md___md___width 16
-#define reg_dma_rw_group_md_offset 112
-
-/* Register rw_group_md_s, scope dma, type rw */
-#define reg_dma_rw_group_md_s___md_s___lsb 0
-#define reg_dma_rw_group_md_s___md_s___width 16
-#define reg_dma_rw_group_md_s_offset 116
-
-/* Register rw_group_up, scope dma, type rw */
-#define reg_dma_rw_group_up_offset 120
-
-/* Register rw_group_down, scope dma, type rw */
-#define reg_dma_rw_group_down_offset 124
-
-/* Register rw_cmd, scope dma, type rw */
-#define reg_dma_rw_cmd___cont_data___lsb 0
-#define reg_dma_rw_cmd___cont_data___width 1
-#define reg_dma_rw_cmd___cont_data___bit 0
-#define reg_dma_rw_cmd_offset 128
-
-/* Register rw_cfg, scope dma, type rw */
-#define reg_dma_rw_cfg___en___lsb 0
-#define reg_dma_rw_cfg___en___width 1
-#define reg_dma_rw_cfg___en___bit 0
-#define reg_dma_rw_cfg___stop___lsb 1
-#define reg_dma_rw_cfg___stop___width 1
-#define reg_dma_rw_cfg___stop___bit 1
-#define reg_dma_rw_cfg_offset 132
-
-/* Register rw_stat, scope dma, type rw */
-#define reg_dma_rw_stat___mode___lsb 0
-#define reg_dma_rw_stat___mode___width 5
-#define reg_dma_rw_stat___list_state___lsb 5
-#define reg_dma_rw_stat___list_state___width 3
-#define reg_dma_rw_stat___stream_cmd_src___lsb 8
-#define reg_dma_rw_stat___stream_cmd_src___width 8
-#define reg_dma_rw_stat___buf___lsb 24
-#define reg_dma_rw_stat___buf___width 8
-#define reg_dma_rw_stat_offset 136
-
-/* Register rw_intr_mask, scope dma, type rw */
-#define reg_dma_rw_intr_mask___group___lsb 0
-#define reg_dma_rw_intr_mask___group___width 1
-#define reg_dma_rw_intr_mask___group___bit 0
-#define reg_dma_rw_intr_mask___ctxt___lsb 1
-#define reg_dma_rw_intr_mask___ctxt___width 1
-#define reg_dma_rw_intr_mask___ctxt___bit 1
-#define reg_dma_rw_intr_mask___data___lsb 2
-#define reg_dma_rw_intr_mask___data___width 1
-#define reg_dma_rw_intr_mask___data___bit 2
-#define reg_dma_rw_intr_mask___in_eop___lsb 3
-#define reg_dma_rw_intr_mask___in_eop___width 1
-#define reg_dma_rw_intr_mask___in_eop___bit 3
-#define reg_dma_rw_intr_mask___stream_cmd___lsb 4
-#define reg_dma_rw_intr_mask___stream_cmd___width 1
-#define reg_dma_rw_intr_mask___stream_cmd___bit 4
-#define reg_dma_rw_intr_mask_offset 140
-
-/* Register rw_ack_intr, scope dma, type rw */
-#define reg_dma_rw_ack_intr___group___lsb 0
-#define reg_dma_rw_ack_intr___group___width 1
-#define reg_dma_rw_ack_intr___group___bit 0
-#define reg_dma_rw_ack_intr___ctxt___lsb 1
-#define reg_dma_rw_ack_intr___ctxt___width 1
-#define reg_dma_rw_ack_intr___ctxt___bit 1
-#define reg_dma_rw_ack_intr___data___lsb 2
-#define reg_dma_rw_ack_intr___data___width 1
-#define reg_dma_rw_ack_intr___data___bit 2
-#define reg_dma_rw_ack_intr___in_eop___lsb 3
-#define reg_dma_rw_ack_intr___in_eop___width 1
-#define reg_dma_rw_ack_intr___in_eop___bit 3
-#define reg_dma_rw_ack_intr___stream_cmd___lsb 4
-#define reg_dma_rw_ack_intr___stream_cmd___width 1
-#define reg_dma_rw_ack_intr___stream_cmd___bit 4
-#define reg_dma_rw_ack_intr_offset 144
-
-/* Register r_intr, scope dma, type r */
-#define reg_dma_r_intr___group___lsb 0
-#define reg_dma_r_intr___group___width 1
-#define reg_dma_r_intr___group___bit 0
-#define reg_dma_r_intr___ctxt___lsb 1
-#define reg_dma_r_intr___ctxt___width 1
-#define reg_dma_r_intr___ctxt___bit 1
-#define reg_dma_r_intr___data___lsb 2
-#define reg_dma_r_intr___data___width 1
-#define reg_dma_r_intr___data___bit 2
-#define reg_dma_r_intr___in_eop___lsb 3
-#define reg_dma_r_intr___in_eop___width 1
-#define reg_dma_r_intr___in_eop___bit 3
-#define reg_dma_r_intr___stream_cmd___lsb 4
-#define reg_dma_r_intr___stream_cmd___width 1
-#define reg_dma_r_intr___stream_cmd___bit 4
-#define reg_dma_r_intr_offset 148
-
-/* Register r_masked_intr, scope dma, type r */
-#define reg_dma_r_masked_intr___group___lsb 0
-#define reg_dma_r_masked_intr___group___width 1
-#define reg_dma_r_masked_intr___group___bit 0
-#define reg_dma_r_masked_intr___ctxt___lsb 1
-#define reg_dma_r_masked_intr___ctxt___width 1
-#define reg_dma_r_masked_intr___ctxt___bit 1
-#define reg_dma_r_masked_intr___data___lsb 2
-#define reg_dma_r_masked_intr___data___width 1
-#define reg_dma_r_masked_intr___data___bit 2
-#define reg_dma_r_masked_intr___in_eop___lsb 3
-#define reg_dma_r_masked_intr___in_eop___width 1
-#define reg_dma_r_masked_intr___in_eop___bit 3
-#define reg_dma_r_masked_intr___stream_cmd___lsb 4
-#define reg_dma_r_masked_intr___stream_cmd___width 1
-#define reg_dma_r_masked_intr___stream_cmd___bit 4
-#define reg_dma_r_masked_intr_offset 152
-
-/* Register rw_stream_cmd, scope dma, type rw */
-#define reg_dma_rw_stream_cmd___cmd___lsb 0
-#define reg_dma_rw_stream_cmd___cmd___width 10
-#define reg_dma_rw_stream_cmd___n___lsb 16
-#define reg_dma_rw_stream_cmd___n___width 8
-#define reg_dma_rw_stream_cmd___busy___lsb 31
-#define reg_dma_rw_stream_cmd___busy___width 1
-#define reg_dma_rw_stream_cmd___busy___bit 31
-#define reg_dma_rw_stream_cmd_offset 156
-
-
-/* Constants */
-#define regk_dma_ack_pkt 0x00000100
-#define regk_dma_anytime 0x00000001
-#define regk_dma_array 0x00000008
-#define regk_dma_burst 0x00000020
-#define regk_dma_client 0x00000002
-#define regk_dma_copy_next 0x00000010
-#define regk_dma_copy_up 0x00000020
-#define regk_dma_data_at_eol 0x00000001
-#define regk_dma_dis_c 0x00000010
-#define regk_dma_dis_g 0x00000020
-#define regk_dma_idle 0x00000001
-#define regk_dma_intern 0x00000004
-#define regk_dma_load_c 0x00000200
-#define regk_dma_load_c_n 0x00000280
-#define regk_dma_load_c_next 0x00000240
-#define regk_dma_load_d 0x00000140
-#define regk_dma_load_g 0x00000300
-#define regk_dma_load_g_down 0x000003c0
-#define regk_dma_load_g_next 0x00000340
-#define regk_dma_load_g_up 0x00000380
-#define regk_dma_next_en 0x00000010
-#define regk_dma_next_pkt 0x00000010
-#define regk_dma_no 0x00000000
-#define regk_dma_only_at_wait 0x00000000
-#define regk_dma_restore 0x00000020
-#define regk_dma_rst 0x00000001
-#define regk_dma_running 0x00000004
-#define regk_dma_rw_cfg_default 0x00000000
-#define regk_dma_rw_cmd_default 0x00000000
-#define regk_dma_rw_intr_mask_default 0x00000000
-#define regk_dma_rw_stat_default 0x00000101
-#define regk_dma_rw_stream_cmd_default 0x00000000
-#define regk_dma_save_down 0x00000020
-#define regk_dma_save_up 0x00000020
-#define regk_dma_set_reg 0x00000050
-#define regk_dma_set_w_size1 0x00000190
-#define regk_dma_set_w_size2 0x000001a0
-#define regk_dma_set_w_size4 0x000001c0
-#define regk_dma_stopped 0x00000002
-#define regk_dma_store_c 0x00000002
-#define regk_dma_store_descr 0x00000000
-#define regk_dma_store_g 0x00000004
-#define regk_dma_store_md 0x00000001
-#define regk_dma_sw 0x00000008
-#define regk_dma_update_down 0x00000020
-#define regk_dma_yes 0x00000001
-#endif /* __dma_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h
deleted file mode 100644
index 97fe523d4d72..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/eth_defs_asm.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __eth_defs_asm_h
-#define __eth_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/eth/rtl/eth_regs.r
- * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
- * last modfied: Mon Apr 11 16:07:03 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/eth_defs_asm.h ../../inst/eth/rtl/eth_regs.r
- * id: $Id: eth_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_ma0_lo, scope eth, type rw */
-#define reg_eth_rw_ma0_lo___addr___lsb 0
-#define reg_eth_rw_ma0_lo___addr___width 32
-#define reg_eth_rw_ma0_lo_offset 0
-
-/* Register rw_ma0_hi, scope eth, type rw */
-#define reg_eth_rw_ma0_hi___addr___lsb 0
-#define reg_eth_rw_ma0_hi___addr___width 16
-#define reg_eth_rw_ma0_hi_offset 4
-
-/* Register rw_ma1_lo, scope eth, type rw */
-#define reg_eth_rw_ma1_lo___addr___lsb 0
-#define reg_eth_rw_ma1_lo___addr___width 32
-#define reg_eth_rw_ma1_lo_offset 8
-
-/* Register rw_ma1_hi, scope eth, type rw */
-#define reg_eth_rw_ma1_hi___addr___lsb 0
-#define reg_eth_rw_ma1_hi___addr___width 16
-#define reg_eth_rw_ma1_hi_offset 12
-
-/* Register rw_ga_lo, scope eth, type rw */
-#define reg_eth_rw_ga_lo___table___lsb 0
-#define reg_eth_rw_ga_lo___table___width 32
-#define reg_eth_rw_ga_lo_offset 16
-
-/* Register rw_ga_hi, scope eth, type rw */
-#define reg_eth_rw_ga_hi___table___lsb 0
-#define reg_eth_rw_ga_hi___table___width 32
-#define reg_eth_rw_ga_hi_offset 20
-
-/* Register rw_gen_ctrl, scope eth, type rw */
-#define reg_eth_rw_gen_ctrl___en___lsb 0
-#define reg_eth_rw_gen_ctrl___en___width 1
-#define reg_eth_rw_gen_ctrl___en___bit 0
-#define reg_eth_rw_gen_ctrl___phy___lsb 1
-#define reg_eth_rw_gen_ctrl___phy___width 2
-#define reg_eth_rw_gen_ctrl___protocol___lsb 3
-#define reg_eth_rw_gen_ctrl___protocol___width 1
-#define reg_eth_rw_gen_ctrl___protocol___bit 3
-#define reg_eth_rw_gen_ctrl___loopback___lsb 4
-#define reg_eth_rw_gen_ctrl___loopback___width 1
-#define reg_eth_rw_gen_ctrl___loopback___bit 4
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___lsb 5
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___width 1
-#define reg_eth_rw_gen_ctrl___flow_ctrl_dis___bit 5
-#define reg_eth_rw_gen_ctrl_offset 24
-
-/* Register rw_rec_ctrl, scope eth, type rw */
-#define reg_eth_rw_rec_ctrl___ma0___lsb 0
-#define reg_eth_rw_rec_ctrl___ma0___width 1
-#define reg_eth_rw_rec_ctrl___ma0___bit 0
-#define reg_eth_rw_rec_ctrl___ma1___lsb 1
-#define reg_eth_rw_rec_ctrl___ma1___width 1
-#define reg_eth_rw_rec_ctrl___ma1___bit 1
-#define reg_eth_rw_rec_ctrl___individual___lsb 2
-#define reg_eth_rw_rec_ctrl___individual___width 1
-#define reg_eth_rw_rec_ctrl___individual___bit 2
-#define reg_eth_rw_rec_ctrl___broadcast___lsb 3
-#define reg_eth_rw_rec_ctrl___broadcast___width 1
-#define reg_eth_rw_rec_ctrl___broadcast___bit 3
-#define reg_eth_rw_rec_ctrl___undersize___lsb 4
-#define reg_eth_rw_rec_ctrl___undersize___width 1
-#define reg_eth_rw_rec_ctrl___undersize___bit 4
-#define reg_eth_rw_rec_ctrl___oversize___lsb 5
-#define reg_eth_rw_rec_ctrl___oversize___width 1
-#define reg_eth_rw_rec_ctrl___oversize___bit 5
-#define reg_eth_rw_rec_ctrl___bad_crc___lsb 6
-#define reg_eth_rw_rec_ctrl___bad_crc___width 1
-#define reg_eth_rw_rec_ctrl___bad_crc___bit 6
-#define reg_eth_rw_rec_ctrl___duplex___lsb 7
-#define reg_eth_rw_rec_ctrl___duplex___width 1
-#define reg_eth_rw_rec_ctrl___duplex___bit 7
-#define reg_eth_rw_rec_ctrl___max_size___lsb 8
-#define reg_eth_rw_rec_ctrl___max_size___width 1
-#define reg_eth_rw_rec_ctrl___max_size___bit 8
-#define reg_eth_rw_rec_ctrl_offset 28
-
-/* Register rw_tr_ctrl, scope eth, type rw */
-#define reg_eth_rw_tr_ctrl___crc___lsb 0
-#define reg_eth_rw_tr_ctrl___crc___width 1
-#define reg_eth_rw_tr_ctrl___crc___bit 0
-#define reg_eth_rw_tr_ctrl___pad___lsb 1
-#define reg_eth_rw_tr_ctrl___pad___width 1
-#define reg_eth_rw_tr_ctrl___pad___bit 1
-#define reg_eth_rw_tr_ctrl___retry___lsb 2
-#define reg_eth_rw_tr_ctrl___retry___width 1
-#define reg_eth_rw_tr_ctrl___retry___bit 2
-#define reg_eth_rw_tr_ctrl___ignore_col___lsb 3
-#define reg_eth_rw_tr_ctrl___ignore_col___width 1
-#define reg_eth_rw_tr_ctrl___ignore_col___bit 3
-#define reg_eth_rw_tr_ctrl___cancel___lsb 4
-#define reg_eth_rw_tr_ctrl___cancel___width 1
-#define reg_eth_rw_tr_ctrl___cancel___bit 4
-#define reg_eth_rw_tr_ctrl___hsh_delay___lsb 5
-#define reg_eth_rw_tr_ctrl___hsh_delay___width 1
-#define reg_eth_rw_tr_ctrl___hsh_delay___bit 5
-#define reg_eth_rw_tr_ctrl___ignore_crs___lsb 6
-#define reg_eth_rw_tr_ctrl___ignore_crs___width 1
-#define reg_eth_rw_tr_ctrl___ignore_crs___bit 6
-#define reg_eth_rw_tr_ctrl_offset 32
-
-/* Register rw_clr_err, scope eth, type rw */
-#define reg_eth_rw_clr_err___clr___lsb 0
-#define reg_eth_rw_clr_err___clr___width 1
-#define reg_eth_rw_clr_err___clr___bit 0
-#define reg_eth_rw_clr_err_offset 36
-
-/* Register rw_mgm_ctrl, scope eth, type rw */
-#define reg_eth_rw_mgm_ctrl___mdio___lsb 0
-#define reg_eth_rw_mgm_ctrl___mdio___width 1
-#define reg_eth_rw_mgm_ctrl___mdio___bit 0
-#define reg_eth_rw_mgm_ctrl___mdoe___lsb 1
-#define reg_eth_rw_mgm_ctrl___mdoe___width 1
-#define reg_eth_rw_mgm_ctrl___mdoe___bit 1
-#define reg_eth_rw_mgm_ctrl___mdc___lsb 2
-#define reg_eth_rw_mgm_ctrl___mdc___width 1
-#define reg_eth_rw_mgm_ctrl___mdc___bit 2
-#define reg_eth_rw_mgm_ctrl___phyclk___lsb 3
-#define reg_eth_rw_mgm_ctrl___phyclk___width 1
-#define reg_eth_rw_mgm_ctrl___phyclk___bit 3
-#define reg_eth_rw_mgm_ctrl___txdata___lsb 4
-#define reg_eth_rw_mgm_ctrl___txdata___width 4
-#define reg_eth_rw_mgm_ctrl___txen___lsb 8
-#define reg_eth_rw_mgm_ctrl___txen___width 1
-#define reg_eth_rw_mgm_ctrl___txen___bit 8
-#define reg_eth_rw_mgm_ctrl_offset 40
-
-/* Register r_stat, scope eth, type r */
-#define reg_eth_r_stat___mdio___lsb 0
-#define reg_eth_r_stat___mdio___width 1
-#define reg_eth_r_stat___mdio___bit 0
-#define reg_eth_r_stat___exc_col___lsb 1
-#define reg_eth_r_stat___exc_col___width 1
-#define reg_eth_r_stat___exc_col___bit 1
-#define reg_eth_r_stat___urun___lsb 2
-#define reg_eth_r_stat___urun___width 1
-#define reg_eth_r_stat___urun___bit 2
-#define reg_eth_r_stat___phyclk___lsb 3
-#define reg_eth_r_stat___phyclk___width 1
-#define reg_eth_r_stat___phyclk___bit 3
-#define reg_eth_r_stat___txdata___lsb 4
-#define reg_eth_r_stat___txdata___width 4
-#define reg_eth_r_stat___txen___lsb 8
-#define reg_eth_r_stat___txen___width 1
-#define reg_eth_r_stat___txen___bit 8
-#define reg_eth_r_stat___col___lsb 9
-#define reg_eth_r_stat___col___width 1
-#define reg_eth_r_stat___col___bit 9
-#define reg_eth_r_stat___crs___lsb 10
-#define reg_eth_r_stat___crs___width 1
-#define reg_eth_r_stat___crs___bit 10
-#define reg_eth_r_stat___txclk___lsb 11
-#define reg_eth_r_stat___txclk___width 1
-#define reg_eth_r_stat___txclk___bit 11
-#define reg_eth_r_stat___rxdata___lsb 12
-#define reg_eth_r_stat___rxdata___width 4
-#define reg_eth_r_stat___rxer___lsb 16
-#define reg_eth_r_stat___rxer___width 1
-#define reg_eth_r_stat___rxer___bit 16
-#define reg_eth_r_stat___rxdv___lsb 17
-#define reg_eth_r_stat___rxdv___width 1
-#define reg_eth_r_stat___rxdv___bit 17
-#define reg_eth_r_stat___rxclk___lsb 18
-#define reg_eth_r_stat___rxclk___width 1
-#define reg_eth_r_stat___rxclk___bit 18
-#define reg_eth_r_stat_offset 44
-
-/* Register rs_rec_cnt, scope eth, type rs */
-#define reg_eth_rs_rec_cnt___crc_err___lsb 0
-#define reg_eth_rs_rec_cnt___crc_err___width 8
-#define reg_eth_rs_rec_cnt___align_err___lsb 8
-#define reg_eth_rs_rec_cnt___align_err___width 8
-#define reg_eth_rs_rec_cnt___oversize___lsb 16
-#define reg_eth_rs_rec_cnt___oversize___width 8
-#define reg_eth_rs_rec_cnt___congestion___lsb 24
-#define reg_eth_rs_rec_cnt___congestion___width 8
-#define reg_eth_rs_rec_cnt_offset 48
-
-/* Register r_rec_cnt, scope eth, type r */
-#define reg_eth_r_rec_cnt___crc_err___lsb 0
-#define reg_eth_r_rec_cnt___crc_err___width 8
-#define reg_eth_r_rec_cnt___align_err___lsb 8
-#define reg_eth_r_rec_cnt___align_err___width 8
-#define reg_eth_r_rec_cnt___oversize___lsb 16
-#define reg_eth_r_rec_cnt___oversize___width 8
-#define reg_eth_r_rec_cnt___congestion___lsb 24
-#define reg_eth_r_rec_cnt___congestion___width 8
-#define reg_eth_r_rec_cnt_offset 52
-
-/* Register rs_tr_cnt, scope eth, type rs */
-#define reg_eth_rs_tr_cnt___single_col___lsb 0
-#define reg_eth_rs_tr_cnt___single_col___width 8
-#define reg_eth_rs_tr_cnt___mult_col___lsb 8
-#define reg_eth_rs_tr_cnt___mult_col___width 8
-#define reg_eth_rs_tr_cnt___late_col___lsb 16
-#define reg_eth_rs_tr_cnt___late_col___width 8
-#define reg_eth_rs_tr_cnt___deferred___lsb 24
-#define reg_eth_rs_tr_cnt___deferred___width 8
-#define reg_eth_rs_tr_cnt_offset 56
-
-/* Register r_tr_cnt, scope eth, type r */
-#define reg_eth_r_tr_cnt___single_col___lsb 0
-#define reg_eth_r_tr_cnt___single_col___width 8
-#define reg_eth_r_tr_cnt___mult_col___lsb 8
-#define reg_eth_r_tr_cnt___mult_col___width 8
-#define reg_eth_r_tr_cnt___late_col___lsb 16
-#define reg_eth_r_tr_cnt___late_col___width 8
-#define reg_eth_r_tr_cnt___deferred___lsb 24
-#define reg_eth_r_tr_cnt___deferred___width 8
-#define reg_eth_r_tr_cnt_offset 60
-
-/* Register rs_phy_cnt, scope eth, type rs */
-#define reg_eth_rs_phy_cnt___carrier_loss___lsb 0
-#define reg_eth_rs_phy_cnt___carrier_loss___width 8
-#define reg_eth_rs_phy_cnt___sqe_err___lsb 8
-#define reg_eth_rs_phy_cnt___sqe_err___width 8
-#define reg_eth_rs_phy_cnt_offset 64
-
-/* Register r_phy_cnt, scope eth, type r */
-#define reg_eth_r_phy_cnt___carrier_loss___lsb 0
-#define reg_eth_r_phy_cnt___carrier_loss___width 8
-#define reg_eth_r_phy_cnt___sqe_err___lsb 8
-#define reg_eth_r_phy_cnt___sqe_err___width 8
-#define reg_eth_r_phy_cnt_offset 68
-
-/* Register rw_test_ctrl, scope eth, type rw */
-#define reg_eth_rw_test_ctrl___snmp_inc___lsb 0
-#define reg_eth_rw_test_ctrl___snmp_inc___width 1
-#define reg_eth_rw_test_ctrl___snmp_inc___bit 0
-#define reg_eth_rw_test_ctrl___snmp___lsb 1
-#define reg_eth_rw_test_ctrl___snmp___width 1
-#define reg_eth_rw_test_ctrl___snmp___bit 1
-#define reg_eth_rw_test_ctrl___backoff___lsb 2
-#define reg_eth_rw_test_ctrl___backoff___width 1
-#define reg_eth_rw_test_ctrl___backoff___bit 2
-#define reg_eth_rw_test_ctrl_offset 72
-
-/* Register rw_intr_mask, scope eth, type rw */
-#define reg_eth_rw_intr_mask___crc___lsb 0
-#define reg_eth_rw_intr_mask___crc___width 1
-#define reg_eth_rw_intr_mask___crc___bit 0
-#define reg_eth_rw_intr_mask___align___lsb 1
-#define reg_eth_rw_intr_mask___align___width 1
-#define reg_eth_rw_intr_mask___align___bit 1
-#define reg_eth_rw_intr_mask___oversize___lsb 2
-#define reg_eth_rw_intr_mask___oversize___width 1
-#define reg_eth_rw_intr_mask___oversize___bit 2
-#define reg_eth_rw_intr_mask___congestion___lsb 3
-#define reg_eth_rw_intr_mask___congestion___width 1
-#define reg_eth_rw_intr_mask___congestion___bit 3
-#define reg_eth_rw_intr_mask___single_col___lsb 4
-#define reg_eth_rw_intr_mask___single_col___width 1
-#define reg_eth_rw_intr_mask___single_col___bit 4
-#define reg_eth_rw_intr_mask___mult_col___lsb 5
-#define reg_eth_rw_intr_mask___mult_col___width 1
-#define reg_eth_rw_intr_mask___mult_col___bit 5
-#define reg_eth_rw_intr_mask___late_col___lsb 6
-#define reg_eth_rw_intr_mask___late_col___width 1
-#define reg_eth_rw_intr_mask___late_col___bit 6
-#define reg_eth_rw_intr_mask___deferred___lsb 7
-#define reg_eth_rw_intr_mask___deferred___width 1
-#define reg_eth_rw_intr_mask___deferred___bit 7
-#define reg_eth_rw_intr_mask___carrier_loss___lsb 8
-#define reg_eth_rw_intr_mask___carrier_loss___width 1
-#define reg_eth_rw_intr_mask___carrier_loss___bit 8
-#define reg_eth_rw_intr_mask___sqe_test_err___lsb 9
-#define reg_eth_rw_intr_mask___sqe_test_err___width 1
-#define reg_eth_rw_intr_mask___sqe_test_err___bit 9
-#define reg_eth_rw_intr_mask___orun___lsb 10
-#define reg_eth_rw_intr_mask___orun___width 1
-#define reg_eth_rw_intr_mask___orun___bit 10
-#define reg_eth_rw_intr_mask___urun___lsb 11
-#define reg_eth_rw_intr_mask___urun___width 1
-#define reg_eth_rw_intr_mask___urun___bit 11
-#define reg_eth_rw_intr_mask___excessive_col___lsb 12
-#define reg_eth_rw_intr_mask___excessive_col___width 1
-#define reg_eth_rw_intr_mask___excessive_col___bit 12
-#define reg_eth_rw_intr_mask___mdio___lsb 13
-#define reg_eth_rw_intr_mask___mdio___width 1
-#define reg_eth_rw_intr_mask___mdio___bit 13
-#define reg_eth_rw_intr_mask_offset 76
-
-/* Register rw_ack_intr, scope eth, type rw */
-#define reg_eth_rw_ack_intr___crc___lsb 0
-#define reg_eth_rw_ack_intr___crc___width 1
-#define reg_eth_rw_ack_intr___crc___bit 0
-#define reg_eth_rw_ack_intr___align___lsb 1
-#define reg_eth_rw_ack_intr___align___width 1
-#define reg_eth_rw_ack_intr___align___bit 1
-#define reg_eth_rw_ack_intr___oversize___lsb 2
-#define reg_eth_rw_ack_intr___oversize___width 1
-#define reg_eth_rw_ack_intr___oversize___bit 2
-#define reg_eth_rw_ack_intr___congestion___lsb 3
-#define reg_eth_rw_ack_intr___congestion___width 1
-#define reg_eth_rw_ack_intr___congestion___bit 3
-#define reg_eth_rw_ack_intr___single_col___lsb 4
-#define reg_eth_rw_ack_intr___single_col___width 1
-#define reg_eth_rw_ack_intr___single_col___bit 4
-#define reg_eth_rw_ack_intr___mult_col___lsb 5
-#define reg_eth_rw_ack_intr___mult_col___width 1
-#define reg_eth_rw_ack_intr___mult_col___bit 5
-#define reg_eth_rw_ack_intr___late_col___lsb 6
-#define reg_eth_rw_ack_intr___late_col___width 1
-#define reg_eth_rw_ack_intr___late_col___bit 6
-#define reg_eth_rw_ack_intr___deferred___lsb 7
-#define reg_eth_rw_ack_intr___deferred___width 1
-#define reg_eth_rw_ack_intr___deferred___bit 7
-#define reg_eth_rw_ack_intr___carrier_loss___lsb 8
-#define reg_eth_rw_ack_intr___carrier_loss___width 1
-#define reg_eth_rw_ack_intr___carrier_loss___bit 8
-#define reg_eth_rw_ack_intr___sqe_test_err___lsb 9
-#define reg_eth_rw_ack_intr___sqe_test_err___width 1
-#define reg_eth_rw_ack_intr___sqe_test_err___bit 9
-#define reg_eth_rw_ack_intr___orun___lsb 10
-#define reg_eth_rw_ack_intr___orun___width 1
-#define reg_eth_rw_ack_intr___orun___bit 10
-#define reg_eth_rw_ack_intr___urun___lsb 11
-#define reg_eth_rw_ack_intr___urun___width 1
-#define reg_eth_rw_ack_intr___urun___bit 11
-#define reg_eth_rw_ack_intr___excessive_col___lsb 12
-#define reg_eth_rw_ack_intr___excessive_col___width 1
-#define reg_eth_rw_ack_intr___excessive_col___bit 12
-#define reg_eth_rw_ack_intr___mdio___lsb 13
-#define reg_eth_rw_ack_intr___mdio___width 1
-#define reg_eth_rw_ack_intr___mdio___bit 13
-#define reg_eth_rw_ack_intr_offset 80
-
-/* Register r_intr, scope eth, type r */
-#define reg_eth_r_intr___crc___lsb 0
-#define reg_eth_r_intr___crc___width 1
-#define reg_eth_r_intr___crc___bit 0
-#define reg_eth_r_intr___align___lsb 1
-#define reg_eth_r_intr___align___width 1
-#define reg_eth_r_intr___align___bit 1
-#define reg_eth_r_intr___oversize___lsb 2
-#define reg_eth_r_intr___oversize___width 1
-#define reg_eth_r_intr___oversize___bit 2
-#define reg_eth_r_intr___congestion___lsb 3
-#define reg_eth_r_intr___congestion___width 1
-#define reg_eth_r_intr___congestion___bit 3
-#define reg_eth_r_intr___single_col___lsb 4
-#define reg_eth_r_intr___single_col___width 1
-#define reg_eth_r_intr___single_col___bit 4
-#define reg_eth_r_intr___mult_col___lsb 5
-#define reg_eth_r_intr___mult_col___width 1
-#define reg_eth_r_intr___mult_col___bit 5
-#define reg_eth_r_intr___late_col___lsb 6
-#define reg_eth_r_intr___late_col___width 1
-#define reg_eth_r_intr___late_col___bit 6
-#define reg_eth_r_intr___deferred___lsb 7
-#define reg_eth_r_intr___deferred___width 1
-#define reg_eth_r_intr___deferred___bit 7
-#define reg_eth_r_intr___carrier_loss___lsb 8
-#define reg_eth_r_intr___carrier_loss___width 1
-#define reg_eth_r_intr___carrier_loss___bit 8
-#define reg_eth_r_intr___sqe_test_err___lsb 9
-#define reg_eth_r_intr___sqe_test_err___width 1
-#define reg_eth_r_intr___sqe_test_err___bit 9
-#define reg_eth_r_intr___orun___lsb 10
-#define reg_eth_r_intr___orun___width 1
-#define reg_eth_r_intr___orun___bit 10
-#define reg_eth_r_intr___urun___lsb 11
-#define reg_eth_r_intr___urun___width 1
-#define reg_eth_r_intr___urun___bit 11
-#define reg_eth_r_intr___excessive_col___lsb 12
-#define reg_eth_r_intr___excessive_col___width 1
-#define reg_eth_r_intr___excessive_col___bit 12
-#define reg_eth_r_intr___mdio___lsb 13
-#define reg_eth_r_intr___mdio___width 1
-#define reg_eth_r_intr___mdio___bit 13
-#define reg_eth_r_intr_offset 84
-
-/* Register r_masked_intr, scope eth, type r */
-#define reg_eth_r_masked_intr___crc___lsb 0
-#define reg_eth_r_masked_intr___crc___width 1
-#define reg_eth_r_masked_intr___crc___bit 0
-#define reg_eth_r_masked_intr___align___lsb 1
-#define reg_eth_r_masked_intr___align___width 1
-#define reg_eth_r_masked_intr___align___bit 1
-#define reg_eth_r_masked_intr___oversize___lsb 2
-#define reg_eth_r_masked_intr___oversize___width 1
-#define reg_eth_r_masked_intr___oversize___bit 2
-#define reg_eth_r_masked_intr___congestion___lsb 3
-#define reg_eth_r_masked_intr___congestion___width 1
-#define reg_eth_r_masked_intr___congestion___bit 3
-#define reg_eth_r_masked_intr___single_col___lsb 4
-#define reg_eth_r_masked_intr___single_col___width 1
-#define reg_eth_r_masked_intr___single_col___bit 4
-#define reg_eth_r_masked_intr___mult_col___lsb 5
-#define reg_eth_r_masked_intr___mult_col___width 1
-#define reg_eth_r_masked_intr___mult_col___bit 5
-#define reg_eth_r_masked_intr___late_col___lsb 6
-#define reg_eth_r_masked_intr___late_col___width 1
-#define reg_eth_r_masked_intr___late_col___bit 6
-#define reg_eth_r_masked_intr___deferred___lsb 7
-#define reg_eth_r_masked_intr___deferred___width 1
-#define reg_eth_r_masked_intr___deferred___bit 7
-#define reg_eth_r_masked_intr___carrier_loss___lsb 8
-#define reg_eth_r_masked_intr___carrier_loss___width 1
-#define reg_eth_r_masked_intr___carrier_loss___bit 8
-#define reg_eth_r_masked_intr___sqe_test_err___lsb 9
-#define reg_eth_r_masked_intr___sqe_test_err___width 1
-#define reg_eth_r_masked_intr___sqe_test_err___bit 9
-#define reg_eth_r_masked_intr___orun___lsb 10
-#define reg_eth_r_masked_intr___orun___width 1
-#define reg_eth_r_masked_intr___orun___bit 10
-#define reg_eth_r_masked_intr___urun___lsb 11
-#define reg_eth_r_masked_intr___urun___width 1
-#define reg_eth_r_masked_intr___urun___bit 11
-#define reg_eth_r_masked_intr___excessive_col___lsb 12
-#define reg_eth_r_masked_intr___excessive_col___width 1
-#define reg_eth_r_masked_intr___excessive_col___bit 12
-#define reg_eth_r_masked_intr___mdio___lsb 13
-#define reg_eth_r_masked_intr___mdio___width 1
-#define reg_eth_r_masked_intr___mdio___bit 13
-#define reg_eth_r_masked_intr_offset 88
-
-
-/* Constants */
-#define regk_eth_discard 0x00000000
-#define regk_eth_ether 0x00000000
-#define regk_eth_full 0x00000001
-#define regk_eth_half 0x00000000
-#define regk_eth_hsh 0x00000001
-#define regk_eth_mii 0x00000001
-#define regk_eth_mii_clk 0x00000000
-#define regk_eth_mii_rec 0x00000002
-#define regk_eth_no 0x00000000
-#define regk_eth_rec 0x00000001
-#define regk_eth_rw_ga_hi_default 0x00000000
-#define regk_eth_rw_ga_lo_default 0x00000000
-#define regk_eth_rw_gen_ctrl_default 0x00000000
-#define regk_eth_rw_intr_mask_default 0x00000000
-#define regk_eth_rw_ma0_hi_default 0x00000000
-#define regk_eth_rw_ma0_lo_default 0x00000000
-#define regk_eth_rw_ma1_hi_default 0x00000000
-#define regk_eth_rw_ma1_lo_default 0x00000000
-#define regk_eth_rw_mgm_ctrl_default 0x00000000
-#define regk_eth_rw_test_ctrl_default 0x00000000
-#define regk_eth_size1518 0x00000000
-#define regk_eth_size1522 0x00000001
-#define regk_eth_yes 0x00000001
-#endif /* __eth_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index 41bc2f83795c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/gio/rtl/gio_regs.r
- * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- * last modfied: Mon Apr 11 16:07:47 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
- * id: $Id: gio_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 8
-#define reg_gio_rw_pa_dout_offset 0
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 8
-#define reg_gio_r_pa_din_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 8
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___pa0___lsb 0
-#define reg_gio_rw_intr_cfg___pa0___width 3
-#define reg_gio_rw_intr_cfg___pa1___lsb 3
-#define reg_gio_rw_intr_cfg___pa1___width 3
-#define reg_gio_rw_intr_cfg___pa2___lsb 6
-#define reg_gio_rw_intr_cfg___pa2___width 3
-#define reg_gio_rw_intr_cfg___pa3___lsb 9
-#define reg_gio_rw_intr_cfg___pa3___width 3
-#define reg_gio_rw_intr_cfg___pa4___lsb 12
-#define reg_gio_rw_intr_cfg___pa4___width 3
-#define reg_gio_rw_intr_cfg___pa5___lsb 15
-#define reg_gio_rw_intr_cfg___pa5___width 3
-#define reg_gio_rw_intr_cfg___pa6___lsb 18
-#define reg_gio_rw_intr_cfg___pa6___width 3
-#define reg_gio_rw_intr_cfg___pa7___lsb 21
-#define reg_gio_rw_intr_cfg___pa7___width 3
-#define reg_gio_rw_intr_cfg_offset 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___pa0___lsb 0
-#define reg_gio_rw_intr_mask___pa0___width 1
-#define reg_gio_rw_intr_mask___pa0___bit 0
-#define reg_gio_rw_intr_mask___pa1___lsb 1
-#define reg_gio_rw_intr_mask___pa1___width 1
-#define reg_gio_rw_intr_mask___pa1___bit 1
-#define reg_gio_rw_intr_mask___pa2___lsb 2
-#define reg_gio_rw_intr_mask___pa2___width 1
-#define reg_gio_rw_intr_mask___pa2___bit 2
-#define reg_gio_rw_intr_mask___pa3___lsb 3
-#define reg_gio_rw_intr_mask___pa3___width 1
-#define reg_gio_rw_intr_mask___pa3___bit 3
-#define reg_gio_rw_intr_mask___pa4___lsb 4
-#define reg_gio_rw_intr_mask___pa4___width 1
-#define reg_gio_rw_intr_mask___pa4___bit 4
-#define reg_gio_rw_intr_mask___pa5___lsb 5
-#define reg_gio_rw_intr_mask___pa5___width 1
-#define reg_gio_rw_intr_mask___pa5___bit 5
-#define reg_gio_rw_intr_mask___pa6___lsb 6
-#define reg_gio_rw_intr_mask___pa6___width 1
-#define reg_gio_rw_intr_mask___pa6___bit 6
-#define reg_gio_rw_intr_mask___pa7___lsb 7
-#define reg_gio_rw_intr_mask___pa7___width 1
-#define reg_gio_rw_intr_mask___pa7___bit 7
-#define reg_gio_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___pa0___lsb 0
-#define reg_gio_rw_ack_intr___pa0___width 1
-#define reg_gio_rw_ack_intr___pa0___bit 0
-#define reg_gio_rw_ack_intr___pa1___lsb 1
-#define reg_gio_rw_ack_intr___pa1___width 1
-#define reg_gio_rw_ack_intr___pa1___bit 1
-#define reg_gio_rw_ack_intr___pa2___lsb 2
-#define reg_gio_rw_ack_intr___pa2___width 1
-#define reg_gio_rw_ack_intr___pa2___bit 2
-#define reg_gio_rw_ack_intr___pa3___lsb 3
-#define reg_gio_rw_ack_intr___pa3___width 1
-#define reg_gio_rw_ack_intr___pa3___bit 3
-#define reg_gio_rw_ack_intr___pa4___lsb 4
-#define reg_gio_rw_ack_intr___pa4___width 1
-#define reg_gio_rw_ack_intr___pa4___bit 4
-#define reg_gio_rw_ack_intr___pa5___lsb 5
-#define reg_gio_rw_ack_intr___pa5___width 1
-#define reg_gio_rw_ack_intr___pa5___bit 5
-#define reg_gio_rw_ack_intr___pa6___lsb 6
-#define reg_gio_rw_ack_intr___pa6___width 1
-#define reg_gio_rw_ack_intr___pa6___bit 6
-#define reg_gio_rw_ack_intr___pa7___lsb 7
-#define reg_gio_rw_ack_intr___pa7___width 1
-#define reg_gio_rw_ack_intr___pa7___bit 7
-#define reg_gio_rw_ack_intr_offset 20
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___pa0___lsb 0
-#define reg_gio_r_intr___pa0___width 1
-#define reg_gio_r_intr___pa0___bit 0
-#define reg_gio_r_intr___pa1___lsb 1
-#define reg_gio_r_intr___pa1___width 1
-#define reg_gio_r_intr___pa1___bit 1
-#define reg_gio_r_intr___pa2___lsb 2
-#define reg_gio_r_intr___pa2___width 1
-#define reg_gio_r_intr___pa2___bit 2
-#define reg_gio_r_intr___pa3___lsb 3
-#define reg_gio_r_intr___pa3___width 1
-#define reg_gio_r_intr___pa3___bit 3
-#define reg_gio_r_intr___pa4___lsb 4
-#define reg_gio_r_intr___pa4___width 1
-#define reg_gio_r_intr___pa4___bit 4
-#define reg_gio_r_intr___pa5___lsb 5
-#define reg_gio_r_intr___pa5___width 1
-#define reg_gio_r_intr___pa5___bit 5
-#define reg_gio_r_intr___pa6___lsb 6
-#define reg_gio_r_intr___pa6___width 1
-#define reg_gio_r_intr___pa6___bit 6
-#define reg_gio_r_intr___pa7___lsb 7
-#define reg_gio_r_intr___pa7___width 1
-#define reg_gio_r_intr___pa7___bit 7
-#define reg_gio_r_intr_offset 24
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___pa0___lsb 0
-#define reg_gio_r_masked_intr___pa0___width 1
-#define reg_gio_r_masked_intr___pa0___bit 0
-#define reg_gio_r_masked_intr___pa1___lsb 1
-#define reg_gio_r_masked_intr___pa1___width 1
-#define reg_gio_r_masked_intr___pa1___bit 1
-#define reg_gio_r_masked_intr___pa2___lsb 2
-#define reg_gio_r_masked_intr___pa2___width 1
-#define reg_gio_r_masked_intr___pa2___bit 2
-#define reg_gio_r_masked_intr___pa3___lsb 3
-#define reg_gio_r_masked_intr___pa3___width 1
-#define reg_gio_r_masked_intr___pa3___bit 3
-#define reg_gio_r_masked_intr___pa4___lsb 4
-#define reg_gio_r_masked_intr___pa4___width 1
-#define reg_gio_r_masked_intr___pa4___bit 4
-#define reg_gio_r_masked_intr___pa5___lsb 5
-#define reg_gio_r_masked_intr___pa5___width 1
-#define reg_gio_r_masked_intr___pa5___bit 5
-#define reg_gio_r_masked_intr___pa6___lsb 6
-#define reg_gio_r_masked_intr___pa6___width 1
-#define reg_gio_r_masked_intr___pa6___bit 6
-#define reg_gio_r_masked_intr___pa7___lsb 7
-#define reg_gio_r_masked_intr___pa7___width 1
-#define reg_gio_r_masked_intr___pa7___bit 7
-#define reg_gio_r_masked_intr_offset 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 18
-#define reg_gio_rw_pb_dout_offset 32
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 18
-#define reg_gio_r_pb_din_offset 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 18
-#define reg_gio_rw_pb_oe_offset 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 18
-#define reg_gio_rw_pc_dout_offset 48
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 18
-#define reg_gio_r_pc_din_offset 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 18
-#define reg_gio_rw_pc_oe_offset 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-#define reg_gio_rw_pd_dout___data___lsb 0
-#define reg_gio_rw_pd_dout___data___width 18
-#define reg_gio_rw_pd_dout_offset 64
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 18
-#define reg_gio_r_pd_din_offset 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-#define reg_gio_rw_pd_oe___oe___lsb 0
-#define reg_gio_rw_pd_oe___oe___width 18
-#define reg_gio_rw_pd_oe_offset 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-#define reg_gio_rw_pe_dout___data___lsb 0
-#define reg_gio_rw_pe_dout___data___width 18
-#define reg_gio_rw_pe_dout_offset 80
-
-/* Register r_pe_din, scope gio, type r */
-#define reg_gio_r_pe_din___data___lsb 0
-#define reg_gio_r_pe_din___data___width 18
-#define reg_gio_r_pe_din_offset 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-#define reg_gio_rw_pe_oe___oe___lsb 0
-#define reg_gio_rw_pe_oe___oe___width 18
-#define reg_gio_rw_pe_oe_offset 88
-
-
-/* Constants */
-#define regk_gio_anyedge 0x00000007
-#define regk_gio_hi 0x00000001
-#define regk_gio_lo 0x00000002
-#define regk_gio_negedge 0x00000006
-#define regk_gio_no 0x00000000
-#define regk_gio_off 0x00000000
-#define regk_gio_posedge 0x00000005
-#define regk_gio_rw_intr_cfg_default 0x00000000
-#define regk_gio_rw_intr_mask_default 0x00000000
-#define regk_gio_rw_pa_oe_default 0x00000000
-#define regk_gio_rw_pb_oe_default 0x00000000
-#define regk_gio_rw_pc_oe_default 0x00000000
-#define regk_gio_rw_pd_oe_default 0x00000000
-#define regk_gio_rw_pe_oe_default 0x00000000
-#define regk_gio_set 0x00000003
-#define regk_gio_yes 0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h
deleted file mode 100644
index e371052fa1bc..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
-version . */
-
-#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define MEMARB_INTR_VECT 0x31
-#define GEN_IO_INTR_VECT 0x32
-#define IOP0_INTR_VECT 0x33
-#define IOP1_INTR_VECT 0x34
-#define IOP2_INTR_VECT 0x35
-#define IOP3_INTR_VECT 0x36
-#define DMA0_INTR_VECT 0x37
-#define DMA1_INTR_VECT 0x38
-#define DMA2_INTR_VECT 0x39
-#define DMA3_INTR_VECT 0x3a
-#define DMA4_INTR_VECT 0x3b
-#define DMA5_INTR_VECT 0x3c
-#define DMA6_INTR_VECT 0x3d
-#define DMA7_INTR_VECT 0x3e
-#define DMA8_INTR_VECT 0x3f
-#define DMA9_INTR_VECT 0x40
-#define ATA_INTR_VECT 0x41
-#define SSER0_INTR_VECT 0x42
-#define SSER1_INTR_VECT 0x43
-#define SER0_INTR_VECT 0x44
-#define SER1_INTR_VECT 0x45
-#define SER2_INTR_VECT 0x46
-#define SER3_INTR_VECT 0x47
-#define P21_INTR_VECT 0x48
-#define ETH0_INTR_VECT 0x49
-#define ETH1_INTR_VECT 0x4a
-#define TIMER_INTR_VECT 0x4b
-#define BIF_ARB_INTR_VECT 0x4c
-#define BIF_DMA_INTR_VECT 0x4d
-#define EXT_INTR_VECT 0x4e
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h
deleted file mode 100644
index 8d0c788b286b..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/intr_vect_defs_asm.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __intr_vect_defs_asm_h
-#define __intr_vect_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
- * last modfied: Mon Apr 11 16:08:03 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mask, scope intr_vect, type rw */
-#define reg_intr_vect_rw_mask___memarb___lsb 0
-#define reg_intr_vect_rw_mask___memarb___width 1
-#define reg_intr_vect_rw_mask___memarb___bit 0
-#define reg_intr_vect_rw_mask___gen_io___lsb 1
-#define reg_intr_vect_rw_mask___gen_io___width 1
-#define reg_intr_vect_rw_mask___gen_io___bit 1
-#define reg_intr_vect_rw_mask___iop0___lsb 2
-#define reg_intr_vect_rw_mask___iop0___width 1
-#define reg_intr_vect_rw_mask___iop0___bit 2
-#define reg_intr_vect_rw_mask___iop1___lsb 3
-#define reg_intr_vect_rw_mask___iop1___width 1
-#define reg_intr_vect_rw_mask___iop1___bit 3
-#define reg_intr_vect_rw_mask___iop2___lsb 4
-#define reg_intr_vect_rw_mask___iop2___width 1
-#define reg_intr_vect_rw_mask___iop2___bit 4
-#define reg_intr_vect_rw_mask___iop3___lsb 5
-#define reg_intr_vect_rw_mask___iop3___width 1
-#define reg_intr_vect_rw_mask___iop3___bit 5
-#define reg_intr_vect_rw_mask___dma0___lsb 6
-#define reg_intr_vect_rw_mask___dma0___width 1
-#define reg_intr_vect_rw_mask___dma0___bit 6
-#define reg_intr_vect_rw_mask___dma1___lsb 7
-#define reg_intr_vect_rw_mask___dma1___width 1
-#define reg_intr_vect_rw_mask___dma1___bit 7
-#define reg_intr_vect_rw_mask___dma2___lsb 8
-#define reg_intr_vect_rw_mask___dma2___width 1
-#define reg_intr_vect_rw_mask___dma2___bit 8
-#define reg_intr_vect_rw_mask___dma3___lsb 9
-#define reg_intr_vect_rw_mask___dma3___width 1
-#define reg_intr_vect_rw_mask___dma3___bit 9
-#define reg_intr_vect_rw_mask___dma4___lsb 10
-#define reg_intr_vect_rw_mask___dma4___width 1
-#define reg_intr_vect_rw_mask___dma4___bit 10
-#define reg_intr_vect_rw_mask___dma5___lsb 11
-#define reg_intr_vect_rw_mask___dma5___width 1
-#define reg_intr_vect_rw_mask___dma5___bit 11
-#define reg_intr_vect_rw_mask___dma6___lsb 12
-#define reg_intr_vect_rw_mask___dma6___width 1
-#define reg_intr_vect_rw_mask___dma6___bit 12
-#define reg_intr_vect_rw_mask___dma7___lsb 13
-#define reg_intr_vect_rw_mask___dma7___width 1
-#define reg_intr_vect_rw_mask___dma7___bit 13
-#define reg_intr_vect_rw_mask___dma8___lsb 14
-#define reg_intr_vect_rw_mask___dma8___width 1
-#define reg_intr_vect_rw_mask___dma8___bit 14
-#define reg_intr_vect_rw_mask___dma9___lsb 15
-#define reg_intr_vect_rw_mask___dma9___width 1
-#define reg_intr_vect_rw_mask___dma9___bit 15
-#define reg_intr_vect_rw_mask___ata___lsb 16
-#define reg_intr_vect_rw_mask___ata___width 1
-#define reg_intr_vect_rw_mask___ata___bit 16
-#define reg_intr_vect_rw_mask___sser0___lsb 17
-#define reg_intr_vect_rw_mask___sser0___width 1
-#define reg_intr_vect_rw_mask___sser0___bit 17
-#define reg_intr_vect_rw_mask___sser1___lsb 18
-#define reg_intr_vect_rw_mask___sser1___width 1
-#define reg_intr_vect_rw_mask___sser1___bit 18
-#define reg_intr_vect_rw_mask___ser0___lsb 19
-#define reg_intr_vect_rw_mask___ser0___width 1
-#define reg_intr_vect_rw_mask___ser0___bit 19
-#define reg_intr_vect_rw_mask___ser1___lsb 20
-#define reg_intr_vect_rw_mask___ser1___width 1
-#define reg_intr_vect_rw_mask___ser1___bit 20
-#define reg_intr_vect_rw_mask___ser2___lsb 21
-#define reg_intr_vect_rw_mask___ser2___width 1
-#define reg_intr_vect_rw_mask___ser2___bit 21
-#define reg_intr_vect_rw_mask___ser3___lsb 22
-#define reg_intr_vect_rw_mask___ser3___width 1
-#define reg_intr_vect_rw_mask___ser3___bit 22
-#define reg_intr_vect_rw_mask___p21___lsb 23
-#define reg_intr_vect_rw_mask___p21___width 1
-#define reg_intr_vect_rw_mask___p21___bit 23
-#define reg_intr_vect_rw_mask___eth0___lsb 24
-#define reg_intr_vect_rw_mask___eth0___width 1
-#define reg_intr_vect_rw_mask___eth0___bit 24
-#define reg_intr_vect_rw_mask___eth1___lsb 25
-#define reg_intr_vect_rw_mask___eth1___width 1
-#define reg_intr_vect_rw_mask___eth1___bit 25
-#define reg_intr_vect_rw_mask___timer___lsb 26
-#define reg_intr_vect_rw_mask___timer___width 1
-#define reg_intr_vect_rw_mask___timer___bit 26
-#define reg_intr_vect_rw_mask___bif_arb___lsb 27
-#define reg_intr_vect_rw_mask___bif_arb___width 1
-#define reg_intr_vect_rw_mask___bif_arb___bit 27
-#define reg_intr_vect_rw_mask___bif_dma___lsb 28
-#define reg_intr_vect_rw_mask___bif_dma___width 1
-#define reg_intr_vect_rw_mask___bif_dma___bit 28
-#define reg_intr_vect_rw_mask___ext___lsb 29
-#define reg_intr_vect_rw_mask___ext___width 1
-#define reg_intr_vect_rw_mask___ext___bit 29
-#define reg_intr_vect_rw_mask_offset 0
-
-/* Register r_vect, scope intr_vect, type r */
-#define reg_intr_vect_r_vect___memarb___lsb 0
-#define reg_intr_vect_r_vect___memarb___width 1
-#define reg_intr_vect_r_vect___memarb___bit 0
-#define reg_intr_vect_r_vect___gen_io___lsb 1
-#define reg_intr_vect_r_vect___gen_io___width 1
-#define reg_intr_vect_r_vect___gen_io___bit 1
-#define reg_intr_vect_r_vect___iop0___lsb 2
-#define reg_intr_vect_r_vect___iop0___width 1
-#define reg_intr_vect_r_vect___iop0___bit 2
-#define reg_intr_vect_r_vect___iop1___lsb 3
-#define reg_intr_vect_r_vect___iop1___width 1
-#define reg_intr_vect_r_vect___iop1___bit 3
-#define reg_intr_vect_r_vect___iop2___lsb 4
-#define reg_intr_vect_r_vect___iop2___width 1
-#define reg_intr_vect_r_vect___iop2___bit 4
-#define reg_intr_vect_r_vect___iop3___lsb 5
-#define reg_intr_vect_r_vect___iop3___width 1
-#define reg_intr_vect_r_vect___iop3___bit 5
-#define reg_intr_vect_r_vect___dma0___lsb 6
-#define reg_intr_vect_r_vect___dma0___width 1
-#define reg_intr_vect_r_vect___dma0___bit 6
-#define reg_intr_vect_r_vect___dma1___lsb 7
-#define reg_intr_vect_r_vect___dma1___width 1
-#define reg_intr_vect_r_vect___dma1___bit 7
-#define reg_intr_vect_r_vect___dma2___lsb 8
-#define reg_intr_vect_r_vect___dma2___width 1
-#define reg_intr_vect_r_vect___dma2___bit 8
-#define reg_intr_vect_r_vect___dma3___lsb 9
-#define reg_intr_vect_r_vect___dma3___width 1
-#define reg_intr_vect_r_vect___dma3___bit 9
-#define reg_intr_vect_r_vect___dma4___lsb 10
-#define reg_intr_vect_r_vect___dma4___width 1
-#define reg_intr_vect_r_vect___dma4___bit 10
-#define reg_intr_vect_r_vect___dma5___lsb 11
-#define reg_intr_vect_r_vect___dma5___width 1
-#define reg_intr_vect_r_vect___dma5___bit 11
-#define reg_intr_vect_r_vect___dma6___lsb 12
-#define reg_intr_vect_r_vect___dma6___width 1
-#define reg_intr_vect_r_vect___dma6___bit 12
-#define reg_intr_vect_r_vect___dma7___lsb 13
-#define reg_intr_vect_r_vect___dma7___width 1
-#define reg_intr_vect_r_vect___dma7___bit 13
-#define reg_intr_vect_r_vect___dma8___lsb 14
-#define reg_intr_vect_r_vect___dma8___width 1
-#define reg_intr_vect_r_vect___dma8___bit 14
-#define reg_intr_vect_r_vect___dma9___lsb 15
-#define reg_intr_vect_r_vect___dma9___width 1
-#define reg_intr_vect_r_vect___dma9___bit 15
-#define reg_intr_vect_r_vect___ata___lsb 16
-#define reg_intr_vect_r_vect___ata___width 1
-#define reg_intr_vect_r_vect___ata___bit 16
-#define reg_intr_vect_r_vect___sser0___lsb 17
-#define reg_intr_vect_r_vect___sser0___width 1
-#define reg_intr_vect_r_vect___sser0___bit 17
-#define reg_intr_vect_r_vect___sser1___lsb 18
-#define reg_intr_vect_r_vect___sser1___width 1
-#define reg_intr_vect_r_vect___sser1___bit 18
-#define reg_intr_vect_r_vect___ser0___lsb 19
-#define reg_intr_vect_r_vect___ser0___width 1
-#define reg_intr_vect_r_vect___ser0___bit 19
-#define reg_intr_vect_r_vect___ser1___lsb 20
-#define reg_intr_vect_r_vect___ser1___width 1
-#define reg_intr_vect_r_vect___ser1___bit 20
-#define reg_intr_vect_r_vect___ser2___lsb 21
-#define reg_intr_vect_r_vect___ser2___width 1
-#define reg_intr_vect_r_vect___ser2___bit 21
-#define reg_intr_vect_r_vect___ser3___lsb 22
-#define reg_intr_vect_r_vect___ser3___width 1
-#define reg_intr_vect_r_vect___ser3___bit 22
-#define reg_intr_vect_r_vect___p21___lsb 23
-#define reg_intr_vect_r_vect___p21___width 1
-#define reg_intr_vect_r_vect___p21___bit 23
-#define reg_intr_vect_r_vect___eth0___lsb 24
-#define reg_intr_vect_r_vect___eth0___width 1
-#define reg_intr_vect_r_vect___eth0___bit 24
-#define reg_intr_vect_r_vect___eth1___lsb 25
-#define reg_intr_vect_r_vect___eth1___width 1
-#define reg_intr_vect_r_vect___eth1___bit 25
-#define reg_intr_vect_r_vect___timer___lsb 26
-#define reg_intr_vect_r_vect___timer___width 1
-#define reg_intr_vect_r_vect___timer___bit 26
-#define reg_intr_vect_r_vect___bif_arb___lsb 27
-#define reg_intr_vect_r_vect___bif_arb___width 1
-#define reg_intr_vect_r_vect___bif_arb___bit 27
-#define reg_intr_vect_r_vect___bif_dma___lsb 28
-#define reg_intr_vect_r_vect___bif_dma___width 1
-#define reg_intr_vect_r_vect___bif_dma___bit 28
-#define reg_intr_vect_r_vect___ext___lsb 29
-#define reg_intr_vect_r_vect___ext___width 1
-#define reg_intr_vect_r_vect___ext___bit 29
-#define reg_intr_vect_r_vect_offset 4
-
-/* Register r_masked_vect, scope intr_vect, type r */
-#define reg_intr_vect_r_masked_vect___memarb___lsb 0
-#define reg_intr_vect_r_masked_vect___memarb___width 1
-#define reg_intr_vect_r_masked_vect___memarb___bit 0
-#define reg_intr_vect_r_masked_vect___gen_io___lsb 1
-#define reg_intr_vect_r_masked_vect___gen_io___width 1
-#define reg_intr_vect_r_masked_vect___gen_io___bit 1
-#define reg_intr_vect_r_masked_vect___iop0___lsb 2
-#define reg_intr_vect_r_masked_vect___iop0___width 1
-#define reg_intr_vect_r_masked_vect___iop0___bit 2
-#define reg_intr_vect_r_masked_vect___iop1___lsb 3
-#define reg_intr_vect_r_masked_vect___iop1___width 1
-#define reg_intr_vect_r_masked_vect___iop1___bit 3
-#define reg_intr_vect_r_masked_vect___iop2___lsb 4
-#define reg_intr_vect_r_masked_vect___iop2___width 1
-#define reg_intr_vect_r_masked_vect___iop2___bit 4
-#define reg_intr_vect_r_masked_vect___iop3___lsb 5
-#define reg_intr_vect_r_masked_vect___iop3___width 1
-#define reg_intr_vect_r_masked_vect___iop3___bit 5
-#define reg_intr_vect_r_masked_vect___dma0___lsb 6
-#define reg_intr_vect_r_masked_vect___dma0___width 1
-#define reg_intr_vect_r_masked_vect___dma0___bit 6
-#define reg_intr_vect_r_masked_vect___dma1___lsb 7
-#define reg_intr_vect_r_masked_vect___dma1___width 1
-#define reg_intr_vect_r_masked_vect___dma1___bit 7
-#define reg_intr_vect_r_masked_vect___dma2___lsb 8
-#define reg_intr_vect_r_masked_vect___dma2___width 1
-#define reg_intr_vect_r_masked_vect___dma2___bit 8
-#define reg_intr_vect_r_masked_vect___dma3___lsb 9
-#define reg_intr_vect_r_masked_vect___dma3___width 1
-#define reg_intr_vect_r_masked_vect___dma3___bit 9
-#define reg_intr_vect_r_masked_vect___dma4___lsb 10
-#define reg_intr_vect_r_masked_vect___dma4___width 1
-#define reg_intr_vect_r_masked_vect___dma4___bit 10
-#define reg_intr_vect_r_masked_vect___dma5___lsb 11
-#define reg_intr_vect_r_masked_vect___dma5___width 1
-#define reg_intr_vect_r_masked_vect___dma5___bit 11
-#define reg_intr_vect_r_masked_vect___dma6___lsb 12
-#define reg_intr_vect_r_masked_vect___dma6___width 1
-#define reg_intr_vect_r_masked_vect___dma6___bit 12
-#define reg_intr_vect_r_masked_vect___dma7___lsb 13
-#define reg_intr_vect_r_masked_vect___dma7___width 1
-#define reg_intr_vect_r_masked_vect___dma7___bit 13
-#define reg_intr_vect_r_masked_vect___dma8___lsb 14
-#define reg_intr_vect_r_masked_vect___dma8___width 1
-#define reg_intr_vect_r_masked_vect___dma8___bit 14
-#define reg_intr_vect_r_masked_vect___dma9___lsb 15
-#define reg_intr_vect_r_masked_vect___dma9___width 1
-#define reg_intr_vect_r_masked_vect___dma9___bit 15
-#define reg_intr_vect_r_masked_vect___ata___lsb 16
-#define reg_intr_vect_r_masked_vect___ata___width 1
-#define reg_intr_vect_r_masked_vect___ata___bit 16
-#define reg_intr_vect_r_masked_vect___sser0___lsb 17
-#define reg_intr_vect_r_masked_vect___sser0___width 1
-#define reg_intr_vect_r_masked_vect___sser0___bit 17
-#define reg_intr_vect_r_masked_vect___sser1___lsb 18
-#define reg_intr_vect_r_masked_vect___sser1___width 1
-#define reg_intr_vect_r_masked_vect___sser1___bit 18
-#define reg_intr_vect_r_masked_vect___ser0___lsb 19
-#define reg_intr_vect_r_masked_vect___ser0___width 1
-#define reg_intr_vect_r_masked_vect___ser0___bit 19
-#define reg_intr_vect_r_masked_vect___ser1___lsb 20
-#define reg_intr_vect_r_masked_vect___ser1___width 1
-#define reg_intr_vect_r_masked_vect___ser1___bit 20
-#define reg_intr_vect_r_masked_vect___ser2___lsb 21
-#define reg_intr_vect_r_masked_vect___ser2___width 1
-#define reg_intr_vect_r_masked_vect___ser2___bit 21
-#define reg_intr_vect_r_masked_vect___ser3___lsb 22
-#define reg_intr_vect_r_masked_vect___ser3___width 1
-#define reg_intr_vect_r_masked_vect___ser3___bit 22
-#define reg_intr_vect_r_masked_vect___p21___lsb 23
-#define reg_intr_vect_r_masked_vect___p21___width 1
-#define reg_intr_vect_r_masked_vect___p21___bit 23
-#define reg_intr_vect_r_masked_vect___eth0___lsb 24
-#define reg_intr_vect_r_masked_vect___eth0___width 1
-#define reg_intr_vect_r_masked_vect___eth0___bit 24
-#define reg_intr_vect_r_masked_vect___eth1___lsb 25
-#define reg_intr_vect_r_masked_vect___eth1___width 1
-#define reg_intr_vect_r_masked_vect___eth1___bit 25
-#define reg_intr_vect_r_masked_vect___timer___lsb 26
-#define reg_intr_vect_r_masked_vect___timer___width 1
-#define reg_intr_vect_r_masked_vect___timer___bit 26
-#define reg_intr_vect_r_masked_vect___bif_arb___lsb 27
-#define reg_intr_vect_r_masked_vect___bif_arb___width 1
-#define reg_intr_vect_r_masked_vect___bif_arb___bit 27
-#define reg_intr_vect_r_masked_vect___bif_dma___lsb 28
-#define reg_intr_vect_r_masked_vect___bif_dma___width 1
-#define reg_intr_vect_r_masked_vect___bif_dma___bit 28
-#define reg_intr_vect_r_masked_vect___ext___lsb 29
-#define reg_intr_vect_r_masked_vect___ext___width 1
-#define reg_intr_vect_r_masked_vect___ext___bit 29
-#define reg_intr_vect_r_masked_vect_offset 8
-
-/* Register r_nmi, scope intr_vect, type r */
-#define reg_intr_vect_r_nmi___ext___lsb 0
-#define reg_intr_vect_r_nmi___ext___width 1
-#define reg_intr_vect_r_nmi___ext___bit 0
-#define reg_intr_vect_r_nmi___watchdog___lsb 1
-#define reg_intr_vect_r_nmi___watchdog___width 1
-#define reg_intr_vect_r_nmi___watchdog___bit 1
-#define reg_intr_vect_r_nmi_offset 12
-
-/* Register r_guru, scope intr_vect, type r */
-#define reg_intr_vect_r_guru___jtag___lsb 0
-#define reg_intr_vect_r_guru___jtag___width 1
-#define reg_intr_vect_r_guru___jtag___bit 0
-#define reg_intr_vect_r_guru_offset 16
-
-
-/* Constants */
-#define regk_intr_vect_off 0x00000000
-#define regk_intr_vect_on 0x00000001
-#define regk_intr_vect_rw_mask_default 0x00000000
-#endif /* __intr_vect_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h
deleted file mode 100644
index f624468346af..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/irq_nmi_defs_asm.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __irq_nmi_defs_asm_h
-#define __irq_nmi_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/irq_nmi.r
- * id: <not found>
- * last modfied: Thu Jan 22 09:22:43 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/irq_nmi_defs_asm.h ../../mod/irq_nmi.r
- * id: $Id: irq_nmi_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cmd, scope irq_nmi, type rw */
-#define reg_irq_nmi_rw_cmd___delay___lsb 0
-#define reg_irq_nmi_rw_cmd___delay___width 16
-#define reg_irq_nmi_rw_cmd___op___lsb 16
-#define reg_irq_nmi_rw_cmd___op___width 2
-#define reg_irq_nmi_rw_cmd_offset 0
-
-
-/* Constants */
-#define regk_irq_nmi_ack_irq 0x00000002
-#define regk_irq_nmi_ack_nmi 0x00000003
-#define regk_irq_nmi_irq 0x00000000
-#define regk_irq_nmi_nmi 0x00000001
-#endif /* __irq_nmi_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h
deleted file mode 100644
index 6a5ce2141860..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/marb_defs_asm.h
+++ /dev/null
@@ -1,580 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_defs_asm_h
-#define __marb_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-#define reg_marb_rw_int_slots___owner___lsb 0
-#define reg_marb_rw_int_slots___owner___width 4
-#define reg_marb_rw_int_slots_offset 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-#define reg_marb_rw_ext_slots___owner___lsb 0
-#define reg_marb_rw_ext_slots___owner___width 4
-#define reg_marb_rw_ext_slots_offset 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-#define reg_marb_rw_regs_slots___owner___lsb 0
-#define reg_marb_rw_regs_slots___owner___width 4
-#define reg_marb_rw_regs_slots_offset 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-#define reg_marb_rw_intr_mask___bp0___lsb 0
-#define reg_marb_rw_intr_mask___bp0___width 1
-#define reg_marb_rw_intr_mask___bp0___bit 0
-#define reg_marb_rw_intr_mask___bp1___lsb 1
-#define reg_marb_rw_intr_mask___bp1___width 1
-#define reg_marb_rw_intr_mask___bp1___bit 1
-#define reg_marb_rw_intr_mask___bp2___lsb 2
-#define reg_marb_rw_intr_mask___bp2___width 1
-#define reg_marb_rw_intr_mask___bp2___bit 2
-#define reg_marb_rw_intr_mask___bp3___lsb 3
-#define reg_marb_rw_intr_mask___bp3___width 1
-#define reg_marb_rw_intr_mask___bp3___bit 3
-#define reg_marb_rw_intr_mask_offset 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-#define reg_marb_rw_ack_intr___bp0___lsb 0
-#define reg_marb_rw_ack_intr___bp0___width 1
-#define reg_marb_rw_ack_intr___bp0___bit 0
-#define reg_marb_rw_ack_intr___bp1___lsb 1
-#define reg_marb_rw_ack_intr___bp1___width 1
-#define reg_marb_rw_ack_intr___bp1___bit 1
-#define reg_marb_rw_ack_intr___bp2___lsb 2
-#define reg_marb_rw_ack_intr___bp2___width 1
-#define reg_marb_rw_ack_intr___bp2___bit 2
-#define reg_marb_rw_ack_intr___bp3___lsb 3
-#define reg_marb_rw_ack_intr___bp3___width 1
-#define reg_marb_rw_ack_intr___bp3___bit 3
-#define reg_marb_rw_ack_intr_offset 532
-
-/* Register r_intr, scope marb, type r */
-#define reg_marb_r_intr___bp0___lsb 0
-#define reg_marb_r_intr___bp0___width 1
-#define reg_marb_r_intr___bp0___bit 0
-#define reg_marb_r_intr___bp1___lsb 1
-#define reg_marb_r_intr___bp1___width 1
-#define reg_marb_r_intr___bp1___bit 1
-#define reg_marb_r_intr___bp2___lsb 2
-#define reg_marb_r_intr___bp2___width 1
-#define reg_marb_r_intr___bp2___bit 2
-#define reg_marb_r_intr___bp3___lsb 3
-#define reg_marb_r_intr___bp3___width 1
-#define reg_marb_r_intr___bp3___bit 3
-#define reg_marb_r_intr_offset 536
-
-/* Register r_masked_intr, scope marb, type r */
-#define reg_marb_r_masked_intr___bp0___lsb 0
-#define reg_marb_r_masked_intr___bp0___width 1
-#define reg_marb_r_masked_intr___bp0___bit 0
-#define reg_marb_r_masked_intr___bp1___lsb 1
-#define reg_marb_r_masked_intr___bp1___width 1
-#define reg_marb_r_masked_intr___bp1___bit 1
-#define reg_marb_r_masked_intr___bp2___lsb 2
-#define reg_marb_r_masked_intr___bp2___width 1
-#define reg_marb_r_masked_intr___bp2___bit 2
-#define reg_marb_r_masked_intr___bp3___lsb 3
-#define reg_marb_r_masked_intr___bp3___width 1
-#define reg_marb_r_masked_intr___bp3___bit 3
-#define reg_marb_r_masked_intr_offset 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-#define reg_marb_rw_stop_mask___dma0___lsb 0
-#define reg_marb_rw_stop_mask___dma0___width 1
-#define reg_marb_rw_stop_mask___dma0___bit 0
-#define reg_marb_rw_stop_mask___dma1___lsb 1
-#define reg_marb_rw_stop_mask___dma1___width 1
-#define reg_marb_rw_stop_mask___dma1___bit 1
-#define reg_marb_rw_stop_mask___dma2___lsb 2
-#define reg_marb_rw_stop_mask___dma2___width 1
-#define reg_marb_rw_stop_mask___dma2___bit 2
-#define reg_marb_rw_stop_mask___dma3___lsb 3
-#define reg_marb_rw_stop_mask___dma3___width 1
-#define reg_marb_rw_stop_mask___dma3___bit 3
-#define reg_marb_rw_stop_mask___dma4___lsb 4
-#define reg_marb_rw_stop_mask___dma4___width 1
-#define reg_marb_rw_stop_mask___dma4___bit 4
-#define reg_marb_rw_stop_mask___dma5___lsb 5
-#define reg_marb_rw_stop_mask___dma5___width 1
-#define reg_marb_rw_stop_mask___dma5___bit 5
-#define reg_marb_rw_stop_mask___dma6___lsb 6
-#define reg_marb_rw_stop_mask___dma6___width 1
-#define reg_marb_rw_stop_mask___dma6___bit 6
-#define reg_marb_rw_stop_mask___dma7___lsb 7
-#define reg_marb_rw_stop_mask___dma7___width 1
-#define reg_marb_rw_stop_mask___dma7___bit 7
-#define reg_marb_rw_stop_mask___dma8___lsb 8
-#define reg_marb_rw_stop_mask___dma8___width 1
-#define reg_marb_rw_stop_mask___dma8___bit 8
-#define reg_marb_rw_stop_mask___dma9___lsb 9
-#define reg_marb_rw_stop_mask___dma9___width 1
-#define reg_marb_rw_stop_mask___dma9___bit 9
-#define reg_marb_rw_stop_mask___cpui___lsb 10
-#define reg_marb_rw_stop_mask___cpui___width 1
-#define reg_marb_rw_stop_mask___cpui___bit 10
-#define reg_marb_rw_stop_mask___cpud___lsb 11
-#define reg_marb_rw_stop_mask___cpud___width 1
-#define reg_marb_rw_stop_mask___cpud___bit 11
-#define reg_marb_rw_stop_mask___iop___lsb 12
-#define reg_marb_rw_stop_mask___iop___width 1
-#define reg_marb_rw_stop_mask___iop___bit 12
-#define reg_marb_rw_stop_mask___slave___lsb 13
-#define reg_marb_rw_stop_mask___slave___width 1
-#define reg_marb_rw_stop_mask___slave___bit 13
-#define reg_marb_rw_stop_mask_offset 544
-
-/* Register r_stopped, scope marb, type r */
-#define reg_marb_r_stopped___dma0___lsb 0
-#define reg_marb_r_stopped___dma0___width 1
-#define reg_marb_r_stopped___dma0___bit 0
-#define reg_marb_r_stopped___dma1___lsb 1
-#define reg_marb_r_stopped___dma1___width 1
-#define reg_marb_r_stopped___dma1___bit 1
-#define reg_marb_r_stopped___dma2___lsb 2
-#define reg_marb_r_stopped___dma2___width 1
-#define reg_marb_r_stopped___dma2___bit 2
-#define reg_marb_r_stopped___dma3___lsb 3
-#define reg_marb_r_stopped___dma3___width 1
-#define reg_marb_r_stopped___dma3___bit 3
-#define reg_marb_r_stopped___dma4___lsb 4
-#define reg_marb_r_stopped___dma4___width 1
-#define reg_marb_r_stopped___dma4___bit 4
-#define reg_marb_r_stopped___dma5___lsb 5
-#define reg_marb_r_stopped___dma5___width 1
-#define reg_marb_r_stopped___dma5___bit 5
-#define reg_marb_r_stopped___dma6___lsb 6
-#define reg_marb_r_stopped___dma6___width 1
-#define reg_marb_r_stopped___dma6___bit 6
-#define reg_marb_r_stopped___dma7___lsb 7
-#define reg_marb_r_stopped___dma7___width 1
-#define reg_marb_r_stopped___dma7___bit 7
-#define reg_marb_r_stopped___dma8___lsb 8
-#define reg_marb_r_stopped___dma8___width 1
-#define reg_marb_r_stopped___dma8___bit 8
-#define reg_marb_r_stopped___dma9___lsb 9
-#define reg_marb_r_stopped___dma9___width 1
-#define reg_marb_r_stopped___dma9___bit 9
-#define reg_marb_r_stopped___cpui___lsb 10
-#define reg_marb_r_stopped___cpui___width 1
-#define reg_marb_r_stopped___cpui___bit 10
-#define reg_marb_r_stopped___cpud___lsb 11
-#define reg_marb_r_stopped___cpud___width 1
-#define reg_marb_r_stopped___cpud___bit 11
-#define reg_marb_r_stopped___iop___lsb 12
-#define reg_marb_r_stopped___iop___width 1
-#define reg_marb_r_stopped___iop___bit 12
-#define reg_marb_r_stopped___slave___lsb 13
-#define reg_marb_r_stopped___slave___width 1
-#define reg_marb_r_stopped___slave___bit 13
-#define reg_marb_r_stopped_offset 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-#define reg_marb_rw_no_snoop___dma0___lsb 0
-#define reg_marb_rw_no_snoop___dma0___width 1
-#define reg_marb_rw_no_snoop___dma0___bit 0
-#define reg_marb_rw_no_snoop___dma1___lsb 1
-#define reg_marb_rw_no_snoop___dma1___width 1
-#define reg_marb_rw_no_snoop___dma1___bit 1
-#define reg_marb_rw_no_snoop___dma2___lsb 2
-#define reg_marb_rw_no_snoop___dma2___width 1
-#define reg_marb_rw_no_snoop___dma2___bit 2
-#define reg_marb_rw_no_snoop___dma3___lsb 3
-#define reg_marb_rw_no_snoop___dma3___width 1
-#define reg_marb_rw_no_snoop___dma3___bit 3
-#define reg_marb_rw_no_snoop___dma4___lsb 4
-#define reg_marb_rw_no_snoop___dma4___width 1
-#define reg_marb_rw_no_snoop___dma4___bit 4
-#define reg_marb_rw_no_snoop___dma5___lsb 5
-#define reg_marb_rw_no_snoop___dma5___width 1
-#define reg_marb_rw_no_snoop___dma5___bit 5
-#define reg_marb_rw_no_snoop___dma6___lsb 6
-#define reg_marb_rw_no_snoop___dma6___width 1
-#define reg_marb_rw_no_snoop___dma6___bit 6
-#define reg_marb_rw_no_snoop___dma7___lsb 7
-#define reg_marb_rw_no_snoop___dma7___width 1
-#define reg_marb_rw_no_snoop___dma7___bit 7
-#define reg_marb_rw_no_snoop___dma8___lsb 8
-#define reg_marb_rw_no_snoop___dma8___width 1
-#define reg_marb_rw_no_snoop___dma8___bit 8
-#define reg_marb_rw_no_snoop___dma9___lsb 9
-#define reg_marb_rw_no_snoop___dma9___width 1
-#define reg_marb_rw_no_snoop___dma9___bit 9
-#define reg_marb_rw_no_snoop___cpui___lsb 10
-#define reg_marb_rw_no_snoop___cpui___width 1
-#define reg_marb_rw_no_snoop___cpui___bit 10
-#define reg_marb_rw_no_snoop___cpud___lsb 11
-#define reg_marb_rw_no_snoop___cpud___width 1
-#define reg_marb_rw_no_snoop___cpud___bit 11
-#define reg_marb_rw_no_snoop___iop___lsb 12
-#define reg_marb_rw_no_snoop___iop___width 1
-#define reg_marb_rw_no_snoop___iop___bit 12
-#define reg_marb_rw_no_snoop___slave___lsb 13
-#define reg_marb_rw_no_snoop___slave___width 1
-#define reg_marb_rw_no_snoop___slave___bit 13
-#define reg_marb_rw_no_snoop_offset 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-#define reg_marb_rw_no_snoop_rq___cpui___lsb 10
-#define reg_marb_rw_no_snoop_rq___cpui___width 1
-#define reg_marb_rw_no_snoop_rq___cpui___bit 10
-#define reg_marb_rw_no_snoop_rq___cpud___lsb 11
-#define reg_marb_rw_no_snoop_rq___cpud___width 1
-#define reg_marb_rw_no_snoop_rq___cpud___bit 11
-#define reg_marb_rw_no_snoop_rq_offset 836
-
-
-/* Constants */
-#define regk_marb_cpud 0x0000000b
-#define regk_marb_cpui 0x0000000a
-#define regk_marb_dma0 0x00000000
-#define regk_marb_dma1 0x00000001
-#define regk_marb_dma2 0x00000002
-#define regk_marb_dma3 0x00000003
-#define regk_marb_dma4 0x00000004
-#define regk_marb_dma5 0x00000005
-#define regk_marb_dma6 0x00000006
-#define regk_marb_dma7 0x00000007
-#define regk_marb_dma8 0x00000008
-#define regk_marb_dma9 0x00000009
-#define regk_marb_iop 0x0000000c
-#define regk_marb_no 0x00000000
-#define regk_marb_r_stopped_default 0x00000000
-#define regk_marb_rw_ext_slots_default 0x00000000
-#define regk_marb_rw_ext_slots_size 0x00000040
-#define regk_marb_rw_int_slots_default 0x00000000
-#define regk_marb_rw_int_slots_size 0x00000040
-#define regk_marb_rw_intr_mask_default 0x00000000
-#define regk_marb_rw_no_snoop_default 0x00000000
-#define regk_marb_rw_no_snoop_rq_default 0x00000000
-#define regk_marb_rw_regs_slots_default 0x00000000
-#define regk_marb_rw_regs_slots_size 0x00000004
-#define regk_marb_rw_stop_mask_default 0x00000000
-#define regk_marb_slave 0x0000000d
-#define regk_marb_yes 0x00000001
-#endif /* __marb_defs_asm_h */
-#ifndef __marb_bp_defs_asm_h
-#define __marb_bp_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/marb_defs_asm.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-#define reg_marb_bp_rw_first_addr_offset 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-#define reg_marb_bp_rw_last_addr_offset 4
-
-/* Register rw_op, scope marb_bp, type rw */
-#define reg_marb_bp_rw_op___rd___lsb 0
-#define reg_marb_bp_rw_op___rd___width 1
-#define reg_marb_bp_rw_op___rd___bit 0
-#define reg_marb_bp_rw_op___wr___lsb 1
-#define reg_marb_bp_rw_op___wr___width 1
-#define reg_marb_bp_rw_op___wr___bit 1
-#define reg_marb_bp_rw_op___rd_excl___lsb 2
-#define reg_marb_bp_rw_op___rd_excl___width 1
-#define reg_marb_bp_rw_op___rd_excl___bit 2
-#define reg_marb_bp_rw_op___pri_wr___lsb 3
-#define reg_marb_bp_rw_op___pri_wr___width 1
-#define reg_marb_bp_rw_op___pri_wr___bit 3
-#define reg_marb_bp_rw_op___us_rd___lsb 4
-#define reg_marb_bp_rw_op___us_rd___width 1
-#define reg_marb_bp_rw_op___us_rd___bit 4
-#define reg_marb_bp_rw_op___us_wr___lsb 5
-#define reg_marb_bp_rw_op___us_wr___width 1
-#define reg_marb_bp_rw_op___us_wr___bit 5
-#define reg_marb_bp_rw_op___us_rd_excl___lsb 6
-#define reg_marb_bp_rw_op___us_rd_excl___width 1
-#define reg_marb_bp_rw_op___us_rd_excl___bit 6
-#define reg_marb_bp_rw_op___us_pri_wr___lsb 7
-#define reg_marb_bp_rw_op___us_pri_wr___width 1
-#define reg_marb_bp_rw_op___us_pri_wr___bit 7
-#define reg_marb_bp_rw_op_offset 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-#define reg_marb_bp_rw_clients___dma0___lsb 0
-#define reg_marb_bp_rw_clients___dma0___width 1
-#define reg_marb_bp_rw_clients___dma0___bit 0
-#define reg_marb_bp_rw_clients___dma1___lsb 1
-#define reg_marb_bp_rw_clients___dma1___width 1
-#define reg_marb_bp_rw_clients___dma1___bit 1
-#define reg_marb_bp_rw_clients___dma2___lsb 2
-#define reg_marb_bp_rw_clients___dma2___width 1
-#define reg_marb_bp_rw_clients___dma2___bit 2
-#define reg_marb_bp_rw_clients___dma3___lsb 3
-#define reg_marb_bp_rw_clients___dma3___width 1
-#define reg_marb_bp_rw_clients___dma3___bit 3
-#define reg_marb_bp_rw_clients___dma4___lsb 4
-#define reg_marb_bp_rw_clients___dma4___width 1
-#define reg_marb_bp_rw_clients___dma4___bit 4
-#define reg_marb_bp_rw_clients___dma5___lsb 5
-#define reg_marb_bp_rw_clients___dma5___width 1
-#define reg_marb_bp_rw_clients___dma5___bit 5
-#define reg_marb_bp_rw_clients___dma6___lsb 6
-#define reg_marb_bp_rw_clients___dma6___width 1
-#define reg_marb_bp_rw_clients___dma6___bit 6
-#define reg_marb_bp_rw_clients___dma7___lsb 7
-#define reg_marb_bp_rw_clients___dma7___width 1
-#define reg_marb_bp_rw_clients___dma7___bit 7
-#define reg_marb_bp_rw_clients___dma8___lsb 8
-#define reg_marb_bp_rw_clients___dma8___width 1
-#define reg_marb_bp_rw_clients___dma8___bit 8
-#define reg_marb_bp_rw_clients___dma9___lsb 9
-#define reg_marb_bp_rw_clients___dma9___width 1
-#define reg_marb_bp_rw_clients___dma9___bit 9
-#define reg_marb_bp_rw_clients___cpui___lsb 10
-#define reg_marb_bp_rw_clients___cpui___width 1
-#define reg_marb_bp_rw_clients___cpui___bit 10
-#define reg_marb_bp_rw_clients___cpud___lsb 11
-#define reg_marb_bp_rw_clients___cpud___width 1
-#define reg_marb_bp_rw_clients___cpud___bit 11
-#define reg_marb_bp_rw_clients___iop___lsb 12
-#define reg_marb_bp_rw_clients___iop___width 1
-#define reg_marb_bp_rw_clients___iop___bit 12
-#define reg_marb_bp_rw_clients___slave___lsb 13
-#define reg_marb_bp_rw_clients___slave___width 1
-#define reg_marb_bp_rw_clients___slave___bit 13
-#define reg_marb_bp_rw_clients_offset 12
-
-/* Register rw_options, scope marb_bp, type rw */
-#define reg_marb_bp_rw_options___wrap___lsb 0
-#define reg_marb_bp_rw_options___wrap___width 1
-#define reg_marb_bp_rw_options___wrap___bit 0
-#define reg_marb_bp_rw_options_offset 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_addr_offset 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_op___rd___lsb 0
-#define reg_marb_bp_r_brk_op___rd___width 1
-#define reg_marb_bp_r_brk_op___rd___bit 0
-#define reg_marb_bp_r_brk_op___wr___lsb 1
-#define reg_marb_bp_r_brk_op___wr___width 1
-#define reg_marb_bp_r_brk_op___wr___bit 1
-#define reg_marb_bp_r_brk_op___rd_excl___lsb 2
-#define reg_marb_bp_r_brk_op___rd_excl___width 1
-#define reg_marb_bp_r_brk_op___rd_excl___bit 2
-#define reg_marb_bp_r_brk_op___pri_wr___lsb 3
-#define reg_marb_bp_r_brk_op___pri_wr___width 1
-#define reg_marb_bp_r_brk_op___pri_wr___bit 3
-#define reg_marb_bp_r_brk_op___us_rd___lsb 4
-#define reg_marb_bp_r_brk_op___us_rd___width 1
-#define reg_marb_bp_r_brk_op___us_rd___bit 4
-#define reg_marb_bp_r_brk_op___us_wr___lsb 5
-#define reg_marb_bp_r_brk_op___us_wr___width 1
-#define reg_marb_bp_r_brk_op___us_wr___bit 5
-#define reg_marb_bp_r_brk_op___us_rd_excl___lsb 6
-#define reg_marb_bp_r_brk_op___us_rd_excl___width 1
-#define reg_marb_bp_r_brk_op___us_rd_excl___bit 6
-#define reg_marb_bp_r_brk_op___us_pri_wr___lsb 7
-#define reg_marb_bp_r_brk_op___us_pri_wr___width 1
-#define reg_marb_bp_r_brk_op___us_pri_wr___bit 7
-#define reg_marb_bp_r_brk_op_offset 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_clients___dma0___lsb 0
-#define reg_marb_bp_r_brk_clients___dma0___width 1
-#define reg_marb_bp_r_brk_clients___dma0___bit 0
-#define reg_marb_bp_r_brk_clients___dma1___lsb 1
-#define reg_marb_bp_r_brk_clients___dma1___width 1
-#define reg_marb_bp_r_brk_clients___dma1___bit 1
-#define reg_marb_bp_r_brk_clients___dma2___lsb 2
-#define reg_marb_bp_r_brk_clients___dma2___width 1
-#define reg_marb_bp_r_brk_clients___dma2___bit 2
-#define reg_marb_bp_r_brk_clients___dma3___lsb 3
-#define reg_marb_bp_r_brk_clients___dma3___width 1
-#define reg_marb_bp_r_brk_clients___dma3___bit 3
-#define reg_marb_bp_r_brk_clients___dma4___lsb 4
-#define reg_marb_bp_r_brk_clients___dma4___width 1
-#define reg_marb_bp_r_brk_clients___dma4___bit 4
-#define reg_marb_bp_r_brk_clients___dma5___lsb 5
-#define reg_marb_bp_r_brk_clients___dma5___width 1
-#define reg_marb_bp_r_brk_clients___dma5___bit 5
-#define reg_marb_bp_r_brk_clients___dma6___lsb 6
-#define reg_marb_bp_r_brk_clients___dma6___width 1
-#define reg_marb_bp_r_brk_clients___dma6___bit 6
-#define reg_marb_bp_r_brk_clients___dma7___lsb 7
-#define reg_marb_bp_r_brk_clients___dma7___width 1
-#define reg_marb_bp_r_brk_clients___dma7___bit 7
-#define reg_marb_bp_r_brk_clients___dma8___lsb 8
-#define reg_marb_bp_r_brk_clients___dma8___width 1
-#define reg_marb_bp_r_brk_clients___dma8___bit 8
-#define reg_marb_bp_r_brk_clients___dma9___lsb 9
-#define reg_marb_bp_r_brk_clients___dma9___width 1
-#define reg_marb_bp_r_brk_clients___dma9___bit 9
-#define reg_marb_bp_r_brk_clients___cpui___lsb 10
-#define reg_marb_bp_r_brk_clients___cpui___width 1
-#define reg_marb_bp_r_brk_clients___cpui___bit 10
-#define reg_marb_bp_r_brk_clients___cpud___lsb 11
-#define reg_marb_bp_r_brk_clients___cpud___width 1
-#define reg_marb_bp_r_brk_clients___cpud___bit 11
-#define reg_marb_bp_r_brk_clients___iop___lsb 12
-#define reg_marb_bp_r_brk_clients___iop___width 1
-#define reg_marb_bp_r_brk_clients___iop___bit 12
-#define reg_marb_bp_r_brk_clients___slave___lsb 13
-#define reg_marb_bp_r_brk_clients___slave___width 1
-#define reg_marb_bp_r_brk_clients___slave___bit 13
-#define reg_marb_bp_r_brk_clients_offset 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_first_client___dma0___lsb 0
-#define reg_marb_bp_r_brk_first_client___dma0___width 1
-#define reg_marb_bp_r_brk_first_client___dma0___bit 0
-#define reg_marb_bp_r_brk_first_client___dma1___lsb 1
-#define reg_marb_bp_r_brk_first_client___dma1___width 1
-#define reg_marb_bp_r_brk_first_client___dma1___bit 1
-#define reg_marb_bp_r_brk_first_client___dma2___lsb 2
-#define reg_marb_bp_r_brk_first_client___dma2___width 1
-#define reg_marb_bp_r_brk_first_client___dma2___bit 2
-#define reg_marb_bp_r_brk_first_client___dma3___lsb 3
-#define reg_marb_bp_r_brk_first_client___dma3___width 1
-#define reg_marb_bp_r_brk_first_client___dma3___bit 3
-#define reg_marb_bp_r_brk_first_client___dma4___lsb 4
-#define reg_marb_bp_r_brk_first_client___dma4___width 1
-#define reg_marb_bp_r_brk_first_client___dma4___bit 4
-#define reg_marb_bp_r_brk_first_client___dma5___lsb 5
-#define reg_marb_bp_r_brk_first_client___dma5___width 1
-#define reg_marb_bp_r_brk_first_client___dma5___bit 5
-#define reg_marb_bp_r_brk_first_client___dma6___lsb 6
-#define reg_marb_bp_r_brk_first_client___dma6___width 1
-#define reg_marb_bp_r_brk_first_client___dma6___bit 6
-#define reg_marb_bp_r_brk_first_client___dma7___lsb 7
-#define reg_marb_bp_r_brk_first_client___dma7___width 1
-#define reg_marb_bp_r_brk_first_client___dma7___bit 7
-#define reg_marb_bp_r_brk_first_client___dma8___lsb 8
-#define reg_marb_bp_r_brk_first_client___dma8___width 1
-#define reg_marb_bp_r_brk_first_client___dma8___bit 8
-#define reg_marb_bp_r_brk_first_client___dma9___lsb 9
-#define reg_marb_bp_r_brk_first_client___dma9___width 1
-#define reg_marb_bp_r_brk_first_client___dma9___bit 9
-#define reg_marb_bp_r_brk_first_client___cpui___lsb 10
-#define reg_marb_bp_r_brk_first_client___cpui___width 1
-#define reg_marb_bp_r_brk_first_client___cpui___bit 10
-#define reg_marb_bp_r_brk_first_client___cpud___lsb 11
-#define reg_marb_bp_r_brk_first_client___cpud___width 1
-#define reg_marb_bp_r_brk_first_client___cpud___bit 11
-#define reg_marb_bp_r_brk_first_client___iop___lsb 12
-#define reg_marb_bp_r_brk_first_client___iop___width 1
-#define reg_marb_bp_r_brk_first_client___iop___bit 12
-#define reg_marb_bp_r_brk_first_client___slave___lsb 13
-#define reg_marb_bp_r_brk_first_client___slave___width 1
-#define reg_marb_bp_r_brk_first_client___slave___bit 13
-#define reg_marb_bp_r_brk_first_client_offset 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-#define reg_marb_bp_r_brk_size_offset 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-#define reg_marb_bp_rw_ack_offset 40
-
-
-/* Constants */
-#define regk_marb_bp_no 0x00000000
-#define regk_marb_bp_rw_op_default 0x00000000
-#define regk_marb_bp_rw_options_default 0x00000000
-#define regk_marb_bp_yes 0x00000001
-#endif /* __marb_bp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h
deleted file mode 100644
index 083174678961..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_defs_asm.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __mmu_defs_asm_h
-#define __mmu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/mmu/doc/mmu_regs.r
- * id: mmu_regs.r,v 1.12 2004/05/06 13:48:45 mikaeln Exp
- * last modfied: Mon Apr 11 17:03:20 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/mmu_defs_asm.h ../../inst/mmu/doc/mmu_regs.r
- * id: $Id: mmu_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mm_cfg, scope mmu, type rw */
-#define reg_mmu_rw_mm_cfg___seg_0___lsb 0
-#define reg_mmu_rw_mm_cfg___seg_0___width 1
-#define reg_mmu_rw_mm_cfg___seg_0___bit 0
-#define reg_mmu_rw_mm_cfg___seg_1___lsb 1
-#define reg_mmu_rw_mm_cfg___seg_1___width 1
-#define reg_mmu_rw_mm_cfg___seg_1___bit 1
-#define reg_mmu_rw_mm_cfg___seg_2___lsb 2
-#define reg_mmu_rw_mm_cfg___seg_2___width 1
-#define reg_mmu_rw_mm_cfg___seg_2___bit 2
-#define reg_mmu_rw_mm_cfg___seg_3___lsb 3
-#define reg_mmu_rw_mm_cfg___seg_3___width 1
-#define reg_mmu_rw_mm_cfg___seg_3___bit 3
-#define reg_mmu_rw_mm_cfg___seg_4___lsb 4
-#define reg_mmu_rw_mm_cfg___seg_4___width 1
-#define reg_mmu_rw_mm_cfg___seg_4___bit 4
-#define reg_mmu_rw_mm_cfg___seg_5___lsb 5
-#define reg_mmu_rw_mm_cfg___seg_5___width 1
-#define reg_mmu_rw_mm_cfg___seg_5___bit 5
-#define reg_mmu_rw_mm_cfg___seg_6___lsb 6
-#define reg_mmu_rw_mm_cfg___seg_6___width 1
-#define reg_mmu_rw_mm_cfg___seg_6___bit 6
-#define reg_mmu_rw_mm_cfg___seg_7___lsb 7
-#define reg_mmu_rw_mm_cfg___seg_7___width 1
-#define reg_mmu_rw_mm_cfg___seg_7___bit 7
-#define reg_mmu_rw_mm_cfg___seg_8___lsb 8
-#define reg_mmu_rw_mm_cfg___seg_8___width 1
-#define reg_mmu_rw_mm_cfg___seg_8___bit 8
-#define reg_mmu_rw_mm_cfg___seg_9___lsb 9
-#define reg_mmu_rw_mm_cfg___seg_9___width 1
-#define reg_mmu_rw_mm_cfg___seg_9___bit 9
-#define reg_mmu_rw_mm_cfg___seg_a___lsb 10
-#define reg_mmu_rw_mm_cfg___seg_a___width 1
-#define reg_mmu_rw_mm_cfg___seg_a___bit 10
-#define reg_mmu_rw_mm_cfg___seg_b___lsb 11
-#define reg_mmu_rw_mm_cfg___seg_b___width 1
-#define reg_mmu_rw_mm_cfg___seg_b___bit 11
-#define reg_mmu_rw_mm_cfg___seg_c___lsb 12
-#define reg_mmu_rw_mm_cfg___seg_c___width 1
-#define reg_mmu_rw_mm_cfg___seg_c___bit 12
-#define reg_mmu_rw_mm_cfg___seg_d___lsb 13
-#define reg_mmu_rw_mm_cfg___seg_d___width 1
-#define reg_mmu_rw_mm_cfg___seg_d___bit 13
-#define reg_mmu_rw_mm_cfg___seg_e___lsb 14
-#define reg_mmu_rw_mm_cfg___seg_e___width 1
-#define reg_mmu_rw_mm_cfg___seg_e___bit 14
-#define reg_mmu_rw_mm_cfg___seg_f___lsb 15
-#define reg_mmu_rw_mm_cfg___seg_f___width 1
-#define reg_mmu_rw_mm_cfg___seg_f___bit 15
-#define reg_mmu_rw_mm_cfg___inv___lsb 16
-#define reg_mmu_rw_mm_cfg___inv___width 1
-#define reg_mmu_rw_mm_cfg___inv___bit 16
-#define reg_mmu_rw_mm_cfg___ex___lsb 17
-#define reg_mmu_rw_mm_cfg___ex___width 1
-#define reg_mmu_rw_mm_cfg___ex___bit 17
-#define reg_mmu_rw_mm_cfg___acc___lsb 18
-#define reg_mmu_rw_mm_cfg___acc___width 1
-#define reg_mmu_rw_mm_cfg___acc___bit 18
-#define reg_mmu_rw_mm_cfg___we___lsb 19
-#define reg_mmu_rw_mm_cfg___we___width 1
-#define reg_mmu_rw_mm_cfg___we___bit 19
-#define reg_mmu_rw_mm_cfg_offset 0
-
-/* Register rw_mm_kbase_lo, scope mmu, type rw */
-#define reg_mmu_rw_mm_kbase_lo___base_0___lsb 0
-#define reg_mmu_rw_mm_kbase_lo___base_0___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_1___lsb 4
-#define reg_mmu_rw_mm_kbase_lo___base_1___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_2___lsb 8
-#define reg_mmu_rw_mm_kbase_lo___base_2___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_3___lsb 12
-#define reg_mmu_rw_mm_kbase_lo___base_3___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_4___lsb 16
-#define reg_mmu_rw_mm_kbase_lo___base_4___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_5___lsb 20
-#define reg_mmu_rw_mm_kbase_lo___base_5___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_6___lsb 24
-#define reg_mmu_rw_mm_kbase_lo___base_6___width 4
-#define reg_mmu_rw_mm_kbase_lo___base_7___lsb 28
-#define reg_mmu_rw_mm_kbase_lo___base_7___width 4
-#define reg_mmu_rw_mm_kbase_lo_offset 4
-
-/* Register rw_mm_kbase_hi, scope mmu, type rw */
-#define reg_mmu_rw_mm_kbase_hi___base_8___lsb 0
-#define reg_mmu_rw_mm_kbase_hi___base_8___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_9___lsb 4
-#define reg_mmu_rw_mm_kbase_hi___base_9___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_a___lsb 8
-#define reg_mmu_rw_mm_kbase_hi___base_a___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_b___lsb 12
-#define reg_mmu_rw_mm_kbase_hi___base_b___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_c___lsb 16
-#define reg_mmu_rw_mm_kbase_hi___base_c___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_d___lsb 20
-#define reg_mmu_rw_mm_kbase_hi___base_d___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_e___lsb 24
-#define reg_mmu_rw_mm_kbase_hi___base_e___width 4
-#define reg_mmu_rw_mm_kbase_hi___base_f___lsb 28
-#define reg_mmu_rw_mm_kbase_hi___base_f___width 4
-#define reg_mmu_rw_mm_kbase_hi_offset 8
-
-/* Register r_mm_cause, scope mmu, type r */
-#define reg_mmu_r_mm_cause___pid___lsb 0
-#define reg_mmu_r_mm_cause___pid___width 8
-#define reg_mmu_r_mm_cause___op___lsb 8
-#define reg_mmu_r_mm_cause___op___width 2
-#define reg_mmu_r_mm_cause___vpn___lsb 13
-#define reg_mmu_r_mm_cause___vpn___width 19
-#define reg_mmu_r_mm_cause_offset 12
-
-/* Register rw_mm_tlb_sel, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_sel___idx___lsb 0
-#define reg_mmu_rw_mm_tlb_sel___idx___width 4
-#define reg_mmu_rw_mm_tlb_sel___set___lsb 4
-#define reg_mmu_rw_mm_tlb_sel___set___width 2
-#define reg_mmu_rw_mm_tlb_sel_offset 16
-
-/* Register rw_mm_tlb_lo, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_lo___x___lsb 0
-#define reg_mmu_rw_mm_tlb_lo___x___width 1
-#define reg_mmu_rw_mm_tlb_lo___x___bit 0
-#define reg_mmu_rw_mm_tlb_lo___w___lsb 1
-#define reg_mmu_rw_mm_tlb_lo___w___width 1
-#define reg_mmu_rw_mm_tlb_lo___w___bit 1
-#define reg_mmu_rw_mm_tlb_lo___k___lsb 2
-#define reg_mmu_rw_mm_tlb_lo___k___width 1
-#define reg_mmu_rw_mm_tlb_lo___k___bit 2
-#define reg_mmu_rw_mm_tlb_lo___v___lsb 3
-#define reg_mmu_rw_mm_tlb_lo___v___width 1
-#define reg_mmu_rw_mm_tlb_lo___v___bit 3
-#define reg_mmu_rw_mm_tlb_lo___g___lsb 4
-#define reg_mmu_rw_mm_tlb_lo___g___width 1
-#define reg_mmu_rw_mm_tlb_lo___g___bit 4
-#define reg_mmu_rw_mm_tlb_lo___pfn___lsb 13
-#define reg_mmu_rw_mm_tlb_lo___pfn___width 19
-#define reg_mmu_rw_mm_tlb_lo_offset 20
-
-/* Register rw_mm_tlb_hi, scope mmu, type rw */
-#define reg_mmu_rw_mm_tlb_hi___pid___lsb 0
-#define reg_mmu_rw_mm_tlb_hi___pid___width 8
-#define reg_mmu_rw_mm_tlb_hi___vpn___lsb 13
-#define reg_mmu_rw_mm_tlb_hi___vpn___width 19
-#define reg_mmu_rw_mm_tlb_hi_offset 24
-
-
-/* Constants */
-#define regk_mmu_execute 0x00000000
-#define regk_mmu_flush 0x00000003
-#define regk_mmu_linear 0x00000001
-#define regk_mmu_no 0x00000000
-#define regk_mmu_off 0x00000000
-#define regk_mmu_on 0x00000001
-#define regk_mmu_page 0x00000000
-#define regk_mmu_read 0x00000001
-#define regk_mmu_write 0x00000002
-#define regk_mmu_yes 0x00000001
-#endif /* __mmu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h
deleted file mode 100644
index fd66daa79259..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/mmu_supp_reg.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#define RW_MM_CFG 0
-#define RW_MM_KBASE_LO 1
-#define RW_MM_KBASE_HI 2
-#define R_MM_CAUSE 3
-#define RW_MM_TLB_SEL 4
-#define RW_MM_TLB_LO 5
-#define RW_MM_TLB_HI 6
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h
deleted file mode 100644
index 72b3d231d80f..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/rt_trace_defs_asm.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __rt_trace_defs_asm_h
-#define __rt_trace_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/rt_trace/rtl/rt_regs.r
- * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
- * last modfied: Mon Apr 11 16:09:14 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/rt_trace_defs_asm.h ../../inst/rt_trace/rtl/rt_regs.r
- * id: $Id: rt_trace_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope rt_trace, type rw */
-#define reg_rt_trace_rw_cfg___en___lsb 0
-#define reg_rt_trace_rw_cfg___en___width 1
-#define reg_rt_trace_rw_cfg___en___bit 0
-#define reg_rt_trace_rw_cfg___mode___lsb 1
-#define reg_rt_trace_rw_cfg___mode___width 1
-#define reg_rt_trace_rw_cfg___mode___bit 1
-#define reg_rt_trace_rw_cfg___owner___lsb 2
-#define reg_rt_trace_rw_cfg___owner___width 1
-#define reg_rt_trace_rw_cfg___owner___bit 2
-#define reg_rt_trace_rw_cfg___wp___lsb 3
-#define reg_rt_trace_rw_cfg___wp___width 1
-#define reg_rt_trace_rw_cfg___wp___bit 3
-#define reg_rt_trace_rw_cfg___stall___lsb 4
-#define reg_rt_trace_rw_cfg___stall___width 1
-#define reg_rt_trace_rw_cfg___stall___bit 4
-#define reg_rt_trace_rw_cfg___wp_start___lsb 8
-#define reg_rt_trace_rw_cfg___wp_start___width 7
-#define reg_rt_trace_rw_cfg___wp_stop___lsb 16
-#define reg_rt_trace_rw_cfg___wp_stop___width 7
-#define reg_rt_trace_rw_cfg_offset 0
-
-/* Register rw_tap_ctrl, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_ctrl___ack_data___lsb 0
-#define reg_rt_trace_rw_tap_ctrl___ack_data___width 1
-#define reg_rt_trace_rw_tap_ctrl___ack_data___bit 0
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___lsb 1
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___width 1
-#define reg_rt_trace_rw_tap_ctrl___ack_guru___bit 1
-#define reg_rt_trace_rw_tap_ctrl_offset 4
-
-/* Register r_tap_stat, scope rt_trace, type r */
-#define reg_rt_trace_r_tap_stat___dav___lsb 0
-#define reg_rt_trace_r_tap_stat___dav___width 1
-#define reg_rt_trace_r_tap_stat___dav___bit 0
-#define reg_rt_trace_r_tap_stat___empty___lsb 1
-#define reg_rt_trace_r_tap_stat___empty___width 1
-#define reg_rt_trace_r_tap_stat___empty___bit 1
-#define reg_rt_trace_r_tap_stat_offset 8
-
-/* Register rw_tap_data, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_data_offset 12
-
-/* Register rw_tap_hdata, scope rt_trace, type rw */
-#define reg_rt_trace_rw_tap_hdata___op___lsb 0
-#define reg_rt_trace_rw_tap_hdata___op___width 4
-#define reg_rt_trace_rw_tap_hdata___sub_op___lsb 4
-#define reg_rt_trace_rw_tap_hdata___sub_op___width 4
-#define reg_rt_trace_rw_tap_hdata_offset 16
-
-/* Register r_redir, scope rt_trace, type r */
-#define reg_rt_trace_r_redir_offset 20
-
-
-/* Constants */
-#define regk_rt_trace_brk 0x0000000c
-#define regk_rt_trace_dbg 0x00000003
-#define regk_rt_trace_dbgdi 0x00000004
-#define regk_rt_trace_dbgdo 0x00000005
-#define regk_rt_trace_gmode 0x00000000
-#define regk_rt_trace_no 0x00000000
-#define regk_rt_trace_nop 0x00000000
-#define regk_rt_trace_normal 0x00000000
-#define regk_rt_trace_rdmem 0x00000007
-#define regk_rt_trace_rdmemb 0x00000009
-#define regk_rt_trace_rdpreg 0x00000002
-#define regk_rt_trace_rdreg 0x00000001
-#define regk_rt_trace_rdsreg 0x00000003
-#define regk_rt_trace_redir 0x00000006
-#define regk_rt_trace_ret 0x0000000b
-#define regk_rt_trace_rw_cfg_default 0x00000000
-#define regk_rt_trace_trcfg 0x00000001
-#define regk_rt_trace_wp 0x00000001
-#define regk_rt_trace_wp0 0x00000001
-#define regk_rt_trace_wp1 0x00000002
-#define regk_rt_trace_wp2 0x00000004
-#define regk_rt_trace_wp3 0x00000008
-#define regk_rt_trace_wp4 0x00000010
-#define regk_rt_trace_wp5 0x00000020
-#define regk_rt_trace_wp6 0x00000040
-#define regk_rt_trace_wrmem 0x00000008
-#define regk_rt_trace_wrmemb 0x0000000a
-#define regk_rt_trace_wrpreg 0x00000005
-#define regk_rt_trace_wrreg 0x00000004
-#define regk_rt_trace_wrsreg 0x00000006
-#define regk_rt_trace_yes 0x00000001
-#endif /* __rt_trace_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h
deleted file mode 100644
index 944f4c7666b4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/ser_defs_asm.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ser_defs_asm_h
-#define __ser_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ser/rtl/ser_regs.r
- * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
- * last modfied: Mon Apr 11 16:09:21 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ser_defs_asm.h ../../inst/ser/rtl/ser_regs.r
- * id: $Id: ser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tr_ctrl, scope ser, type rw */
-#define reg_ser_rw_tr_ctrl___base_freq___lsb 0
-#define reg_ser_rw_tr_ctrl___base_freq___width 3
-#define reg_ser_rw_tr_ctrl___en___lsb 3
-#define reg_ser_rw_tr_ctrl___en___width 1
-#define reg_ser_rw_tr_ctrl___en___bit 3
-#define reg_ser_rw_tr_ctrl___par___lsb 4
-#define reg_ser_rw_tr_ctrl___par___width 2
-#define reg_ser_rw_tr_ctrl___par_en___lsb 6
-#define reg_ser_rw_tr_ctrl___par_en___width 1
-#define reg_ser_rw_tr_ctrl___par_en___bit 6
-#define reg_ser_rw_tr_ctrl___data_bits___lsb 7
-#define reg_ser_rw_tr_ctrl___data_bits___width 1
-#define reg_ser_rw_tr_ctrl___data_bits___bit 7
-#define reg_ser_rw_tr_ctrl___stop_bits___lsb 8
-#define reg_ser_rw_tr_ctrl___stop_bits___width 1
-#define reg_ser_rw_tr_ctrl___stop_bits___bit 8
-#define reg_ser_rw_tr_ctrl___stop___lsb 9
-#define reg_ser_rw_tr_ctrl___stop___width 1
-#define reg_ser_rw_tr_ctrl___stop___bit 9
-#define reg_ser_rw_tr_ctrl___rts_delay___lsb 10
-#define reg_ser_rw_tr_ctrl___rts_delay___width 3
-#define reg_ser_rw_tr_ctrl___rts_setup___lsb 13
-#define reg_ser_rw_tr_ctrl___rts_setup___width 1
-#define reg_ser_rw_tr_ctrl___rts_setup___bit 13
-#define reg_ser_rw_tr_ctrl___auto_rts___lsb 14
-#define reg_ser_rw_tr_ctrl___auto_rts___width 1
-#define reg_ser_rw_tr_ctrl___auto_rts___bit 14
-#define reg_ser_rw_tr_ctrl___txd___lsb 15
-#define reg_ser_rw_tr_ctrl___txd___width 1
-#define reg_ser_rw_tr_ctrl___txd___bit 15
-#define reg_ser_rw_tr_ctrl___auto_cts___lsb 16
-#define reg_ser_rw_tr_ctrl___auto_cts___width 1
-#define reg_ser_rw_tr_ctrl___auto_cts___bit 16
-#define reg_ser_rw_tr_ctrl_offset 0
-
-/* Register rw_tr_dma_en, scope ser, type rw */
-#define reg_ser_rw_tr_dma_en___en___lsb 0
-#define reg_ser_rw_tr_dma_en___en___width 1
-#define reg_ser_rw_tr_dma_en___en___bit 0
-#define reg_ser_rw_tr_dma_en_offset 4
-
-/* Register rw_rec_ctrl, scope ser, type rw */
-#define reg_ser_rw_rec_ctrl___base_freq___lsb 0
-#define reg_ser_rw_rec_ctrl___base_freq___width 3
-#define reg_ser_rw_rec_ctrl___en___lsb 3
-#define reg_ser_rw_rec_ctrl___en___width 1
-#define reg_ser_rw_rec_ctrl___en___bit 3
-#define reg_ser_rw_rec_ctrl___par___lsb 4
-#define reg_ser_rw_rec_ctrl___par___width 2
-#define reg_ser_rw_rec_ctrl___par_en___lsb 6
-#define reg_ser_rw_rec_ctrl___par_en___width 1
-#define reg_ser_rw_rec_ctrl___par_en___bit 6
-#define reg_ser_rw_rec_ctrl___data_bits___lsb 7
-#define reg_ser_rw_rec_ctrl___data_bits___width 1
-#define reg_ser_rw_rec_ctrl___data_bits___bit 7
-#define reg_ser_rw_rec_ctrl___dma_mode___lsb 8
-#define reg_ser_rw_rec_ctrl___dma_mode___width 1
-#define reg_ser_rw_rec_ctrl___dma_mode___bit 8
-#define reg_ser_rw_rec_ctrl___dma_err___lsb 9
-#define reg_ser_rw_rec_ctrl___dma_err___width 1
-#define reg_ser_rw_rec_ctrl___dma_err___bit 9
-#define reg_ser_rw_rec_ctrl___sampling___lsb 10
-#define reg_ser_rw_rec_ctrl___sampling___width 1
-#define reg_ser_rw_rec_ctrl___sampling___bit 10
-#define reg_ser_rw_rec_ctrl___timeout___lsb 11
-#define reg_ser_rw_rec_ctrl___timeout___width 3
-#define reg_ser_rw_rec_ctrl___auto_eop___lsb 14
-#define reg_ser_rw_rec_ctrl___auto_eop___width 1
-#define reg_ser_rw_rec_ctrl___auto_eop___bit 14
-#define reg_ser_rw_rec_ctrl___half_duplex___lsb 15
-#define reg_ser_rw_rec_ctrl___half_duplex___width 1
-#define reg_ser_rw_rec_ctrl___half_duplex___bit 15
-#define reg_ser_rw_rec_ctrl___rts_n___lsb 16
-#define reg_ser_rw_rec_ctrl___rts_n___width 1
-#define reg_ser_rw_rec_ctrl___rts_n___bit 16
-#define reg_ser_rw_rec_ctrl___loopback___lsb 17
-#define reg_ser_rw_rec_ctrl___loopback___width 1
-#define reg_ser_rw_rec_ctrl___loopback___bit 17
-#define reg_ser_rw_rec_ctrl_offset 8
-
-/* Register rw_tr_baud_div, scope ser, type rw */
-#define reg_ser_rw_tr_baud_div___div___lsb 0
-#define reg_ser_rw_tr_baud_div___div___width 16
-#define reg_ser_rw_tr_baud_div_offset 12
-
-/* Register rw_rec_baud_div, scope ser, type rw */
-#define reg_ser_rw_rec_baud_div___div___lsb 0
-#define reg_ser_rw_rec_baud_div___div___width 16
-#define reg_ser_rw_rec_baud_div_offset 16
-
-/* Register rw_xoff, scope ser, type rw */
-#define reg_ser_rw_xoff___chr___lsb 0
-#define reg_ser_rw_xoff___chr___width 8
-#define reg_ser_rw_xoff___automatic___lsb 8
-#define reg_ser_rw_xoff___automatic___width 1
-#define reg_ser_rw_xoff___automatic___bit 8
-#define reg_ser_rw_xoff_offset 20
-
-/* Register rw_xoff_clr, scope ser, type rw */
-#define reg_ser_rw_xoff_clr___clr___lsb 0
-#define reg_ser_rw_xoff_clr___clr___width 1
-#define reg_ser_rw_xoff_clr___clr___bit 0
-#define reg_ser_rw_xoff_clr_offset 24
-
-/* Register rw_dout, scope ser, type rw */
-#define reg_ser_rw_dout___data___lsb 0
-#define reg_ser_rw_dout___data___width 8
-#define reg_ser_rw_dout_offset 28
-
-/* Register rs_stat_din, scope ser, type rs */
-#define reg_ser_rs_stat_din___data___lsb 0
-#define reg_ser_rs_stat_din___data___width 8
-#define reg_ser_rs_stat_din___dav___lsb 16
-#define reg_ser_rs_stat_din___dav___width 1
-#define reg_ser_rs_stat_din___dav___bit 16
-#define reg_ser_rs_stat_din___framing_err___lsb 17
-#define reg_ser_rs_stat_din___framing_err___width 1
-#define reg_ser_rs_stat_din___framing_err___bit 17
-#define reg_ser_rs_stat_din___par_err___lsb 18
-#define reg_ser_rs_stat_din___par_err___width 1
-#define reg_ser_rs_stat_din___par_err___bit 18
-#define reg_ser_rs_stat_din___orun___lsb 19
-#define reg_ser_rs_stat_din___orun___width 1
-#define reg_ser_rs_stat_din___orun___bit 19
-#define reg_ser_rs_stat_din___rec_err___lsb 20
-#define reg_ser_rs_stat_din___rec_err___width 1
-#define reg_ser_rs_stat_din___rec_err___bit 20
-#define reg_ser_rs_stat_din___rxd___lsb 21
-#define reg_ser_rs_stat_din___rxd___width 1
-#define reg_ser_rs_stat_din___rxd___bit 21
-#define reg_ser_rs_stat_din___tr_idle___lsb 22
-#define reg_ser_rs_stat_din___tr_idle___width 1
-#define reg_ser_rs_stat_din___tr_idle___bit 22
-#define reg_ser_rs_stat_din___tr_empty___lsb 23
-#define reg_ser_rs_stat_din___tr_empty___width 1
-#define reg_ser_rs_stat_din___tr_empty___bit 23
-#define reg_ser_rs_stat_din___tr_rdy___lsb 24
-#define reg_ser_rs_stat_din___tr_rdy___width 1
-#define reg_ser_rs_stat_din___tr_rdy___bit 24
-#define reg_ser_rs_stat_din___cts_n___lsb 25
-#define reg_ser_rs_stat_din___cts_n___width 1
-#define reg_ser_rs_stat_din___cts_n___bit 25
-#define reg_ser_rs_stat_din___xoff_detect___lsb 26
-#define reg_ser_rs_stat_din___xoff_detect___width 1
-#define reg_ser_rs_stat_din___xoff_detect___bit 26
-#define reg_ser_rs_stat_din___rts_n___lsb 27
-#define reg_ser_rs_stat_din___rts_n___width 1
-#define reg_ser_rs_stat_din___rts_n___bit 27
-#define reg_ser_rs_stat_din___txd___lsb 28
-#define reg_ser_rs_stat_din___txd___width 1
-#define reg_ser_rs_stat_din___txd___bit 28
-#define reg_ser_rs_stat_din_offset 32
-
-/* Register r_stat_din, scope ser, type r */
-#define reg_ser_r_stat_din___data___lsb 0
-#define reg_ser_r_stat_din___data___width 8
-#define reg_ser_r_stat_din___dav___lsb 16
-#define reg_ser_r_stat_din___dav___width 1
-#define reg_ser_r_stat_din___dav___bit 16
-#define reg_ser_r_stat_din___framing_err___lsb 17
-#define reg_ser_r_stat_din___framing_err___width 1
-#define reg_ser_r_stat_din___framing_err___bit 17
-#define reg_ser_r_stat_din___par_err___lsb 18
-#define reg_ser_r_stat_din___par_err___width 1
-#define reg_ser_r_stat_din___par_err___bit 18
-#define reg_ser_r_stat_din___orun___lsb 19
-#define reg_ser_r_stat_din___orun___width 1
-#define reg_ser_r_stat_din___orun___bit 19
-#define reg_ser_r_stat_din___rec_err___lsb 20
-#define reg_ser_r_stat_din___rec_err___width 1
-#define reg_ser_r_stat_din___rec_err___bit 20
-#define reg_ser_r_stat_din___rxd___lsb 21
-#define reg_ser_r_stat_din___rxd___width 1
-#define reg_ser_r_stat_din___rxd___bit 21
-#define reg_ser_r_stat_din___tr_idle___lsb 22
-#define reg_ser_r_stat_din___tr_idle___width 1
-#define reg_ser_r_stat_din___tr_idle___bit 22
-#define reg_ser_r_stat_din___tr_empty___lsb 23
-#define reg_ser_r_stat_din___tr_empty___width 1
-#define reg_ser_r_stat_din___tr_empty___bit 23
-#define reg_ser_r_stat_din___tr_rdy___lsb 24
-#define reg_ser_r_stat_din___tr_rdy___width 1
-#define reg_ser_r_stat_din___tr_rdy___bit 24
-#define reg_ser_r_stat_din___cts_n___lsb 25
-#define reg_ser_r_stat_din___cts_n___width 1
-#define reg_ser_r_stat_din___cts_n___bit 25
-#define reg_ser_r_stat_din___xoff_detect___lsb 26
-#define reg_ser_r_stat_din___xoff_detect___width 1
-#define reg_ser_r_stat_din___xoff_detect___bit 26
-#define reg_ser_r_stat_din___rts_n___lsb 27
-#define reg_ser_r_stat_din___rts_n___width 1
-#define reg_ser_r_stat_din___rts_n___bit 27
-#define reg_ser_r_stat_din___txd___lsb 28
-#define reg_ser_r_stat_din___txd___width 1
-#define reg_ser_r_stat_din___txd___bit 28
-#define reg_ser_r_stat_din_offset 36
-
-/* Register rw_rec_eop, scope ser, type rw */
-#define reg_ser_rw_rec_eop___set___lsb 0
-#define reg_ser_rw_rec_eop___set___width 1
-#define reg_ser_rw_rec_eop___set___bit 0
-#define reg_ser_rw_rec_eop_offset 40
-
-/* Register rw_intr_mask, scope ser, type rw */
-#define reg_ser_rw_intr_mask___tr_rdy___lsb 0
-#define reg_ser_rw_intr_mask___tr_rdy___width 1
-#define reg_ser_rw_intr_mask___tr_rdy___bit 0
-#define reg_ser_rw_intr_mask___tr_empty___lsb 1
-#define reg_ser_rw_intr_mask___tr_empty___width 1
-#define reg_ser_rw_intr_mask___tr_empty___bit 1
-#define reg_ser_rw_intr_mask___tr_idle___lsb 2
-#define reg_ser_rw_intr_mask___tr_idle___width 1
-#define reg_ser_rw_intr_mask___tr_idle___bit 2
-#define reg_ser_rw_intr_mask___dav___lsb 3
-#define reg_ser_rw_intr_mask___dav___width 1
-#define reg_ser_rw_intr_mask___dav___bit 3
-#define reg_ser_rw_intr_mask_offset 44
-
-/* Register rw_ack_intr, scope ser, type rw */
-#define reg_ser_rw_ack_intr___tr_rdy___lsb 0
-#define reg_ser_rw_ack_intr___tr_rdy___width 1
-#define reg_ser_rw_ack_intr___tr_rdy___bit 0
-#define reg_ser_rw_ack_intr___tr_empty___lsb 1
-#define reg_ser_rw_ack_intr___tr_empty___width 1
-#define reg_ser_rw_ack_intr___tr_empty___bit 1
-#define reg_ser_rw_ack_intr___tr_idle___lsb 2
-#define reg_ser_rw_ack_intr___tr_idle___width 1
-#define reg_ser_rw_ack_intr___tr_idle___bit 2
-#define reg_ser_rw_ack_intr___dav___lsb 3
-#define reg_ser_rw_ack_intr___dav___width 1
-#define reg_ser_rw_ack_intr___dav___bit 3
-#define reg_ser_rw_ack_intr_offset 48
-
-/* Register r_intr, scope ser, type r */
-#define reg_ser_r_intr___tr_rdy___lsb 0
-#define reg_ser_r_intr___tr_rdy___width 1
-#define reg_ser_r_intr___tr_rdy___bit 0
-#define reg_ser_r_intr___tr_empty___lsb 1
-#define reg_ser_r_intr___tr_empty___width 1
-#define reg_ser_r_intr___tr_empty___bit 1
-#define reg_ser_r_intr___tr_idle___lsb 2
-#define reg_ser_r_intr___tr_idle___width 1
-#define reg_ser_r_intr___tr_idle___bit 2
-#define reg_ser_r_intr___dav___lsb 3
-#define reg_ser_r_intr___dav___width 1
-#define reg_ser_r_intr___dav___bit 3
-#define reg_ser_r_intr_offset 52
-
-/* Register r_masked_intr, scope ser, type r */
-#define reg_ser_r_masked_intr___tr_rdy___lsb 0
-#define reg_ser_r_masked_intr___tr_rdy___width 1
-#define reg_ser_r_masked_intr___tr_rdy___bit 0
-#define reg_ser_r_masked_intr___tr_empty___lsb 1
-#define reg_ser_r_masked_intr___tr_empty___width 1
-#define reg_ser_r_masked_intr___tr_empty___bit 1
-#define reg_ser_r_masked_intr___tr_idle___lsb 2
-#define reg_ser_r_masked_intr___tr_idle___width 1
-#define reg_ser_r_masked_intr___tr_idle___bit 2
-#define reg_ser_r_masked_intr___dav___lsb 3
-#define reg_ser_r_masked_intr___dav___width 1
-#define reg_ser_r_masked_intr___dav___bit 3
-#define reg_ser_r_masked_intr_offset 56
-
-
-/* Constants */
-#define regk_ser_active 0x00000000
-#define regk_ser_bits1 0x00000000
-#define regk_ser_bits2 0x00000001
-#define regk_ser_bits7 0x00000001
-#define regk_ser_bits8 0x00000000
-#define regk_ser_del0_5 0x00000000
-#define regk_ser_del1 0x00000001
-#define regk_ser_del1_5 0x00000002
-#define regk_ser_del2 0x00000003
-#define regk_ser_del2_5 0x00000004
-#define regk_ser_del3 0x00000005
-#define regk_ser_del3_5 0x00000006
-#define regk_ser_del4 0x00000007
-#define regk_ser_even 0x00000000
-#define regk_ser_ext 0x00000001
-#define regk_ser_f100 0x00000007
-#define regk_ser_f29_493 0x00000004
-#define regk_ser_f32 0x00000005
-#define regk_ser_f32_768 0x00000006
-#define regk_ser_ignore 0x00000001
-#define regk_ser_inactive 0x00000001
-#define regk_ser_majority 0x00000001
-#define regk_ser_mark 0x00000002
-#define regk_ser_middle 0x00000000
-#define regk_ser_no 0x00000000
-#define regk_ser_odd 0x00000001
-#define regk_ser_off 0x00000000
-#define regk_ser_rw_intr_mask_default 0x00000000
-#define regk_ser_rw_rec_baud_div_default 0x00000000
-#define regk_ser_rw_rec_ctrl_default 0x00010000
-#define regk_ser_rw_tr_baud_div_default 0x00000000
-#define regk_ser_rw_tr_ctrl_default 0x00008000
-#define regk_ser_rw_tr_dma_en_default 0x00000000
-#define regk_ser_rw_xoff_default 0x00000000
-#define regk_ser_space 0x00000003
-#define regk_ser_stop 0x00000000
-#define regk_ser_yes 0x00000001
-#endif /* __ser_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h
deleted file mode 100644
index 607b505100fa..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/sser_defs_asm.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __sser_defs_asm_h
-#define __sser_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/syncser/rtl/sser_regs.r
- * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
- * last modfied: Mon Apr 11 16:09:48 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/sser_defs_asm.h ../../inst/syncser/rtl/sser_regs.r
- * id: $Id: sser_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope sser, type rw */
-#define reg_sser_rw_cfg___clk_div___lsb 0
-#define reg_sser_rw_cfg___clk_div___width 16
-#define reg_sser_rw_cfg___base_freq___lsb 16
-#define reg_sser_rw_cfg___base_freq___width 3
-#define reg_sser_rw_cfg___gate_clk___lsb 19
-#define reg_sser_rw_cfg___gate_clk___width 1
-#define reg_sser_rw_cfg___gate_clk___bit 19
-#define reg_sser_rw_cfg___clkgate_ctrl___lsb 20
-#define reg_sser_rw_cfg___clkgate_ctrl___width 1
-#define reg_sser_rw_cfg___clkgate_ctrl___bit 20
-#define reg_sser_rw_cfg___clkgate_in___lsb 21
-#define reg_sser_rw_cfg___clkgate_in___width 1
-#define reg_sser_rw_cfg___clkgate_in___bit 21
-#define reg_sser_rw_cfg___clk_dir___lsb 22
-#define reg_sser_rw_cfg___clk_dir___width 1
-#define reg_sser_rw_cfg___clk_dir___bit 22
-#define reg_sser_rw_cfg___clk_od_mode___lsb 23
-#define reg_sser_rw_cfg___clk_od_mode___width 1
-#define reg_sser_rw_cfg___clk_od_mode___bit 23
-#define reg_sser_rw_cfg___out_clk_pol___lsb 24
-#define reg_sser_rw_cfg___out_clk_pol___width 1
-#define reg_sser_rw_cfg___out_clk_pol___bit 24
-#define reg_sser_rw_cfg___out_clk_src___lsb 25
-#define reg_sser_rw_cfg___out_clk_src___width 2
-#define reg_sser_rw_cfg___clk_in_sel___lsb 27
-#define reg_sser_rw_cfg___clk_in_sel___width 1
-#define reg_sser_rw_cfg___clk_in_sel___bit 27
-#define reg_sser_rw_cfg___hold_pol___lsb 28
-#define reg_sser_rw_cfg___hold_pol___width 1
-#define reg_sser_rw_cfg___hold_pol___bit 28
-#define reg_sser_rw_cfg___prepare___lsb 29
-#define reg_sser_rw_cfg___prepare___width 1
-#define reg_sser_rw_cfg___prepare___bit 29
-#define reg_sser_rw_cfg___en___lsb 30
-#define reg_sser_rw_cfg___en___width 1
-#define reg_sser_rw_cfg___en___bit 30
-#define reg_sser_rw_cfg_offset 0
-
-/* Register rw_frm_cfg, scope sser, type rw */
-#define reg_sser_rw_frm_cfg___wordrate___lsb 0
-#define reg_sser_rw_frm_cfg___wordrate___width 10
-#define reg_sser_rw_frm_cfg___rec_delay___lsb 10
-#define reg_sser_rw_frm_cfg___rec_delay___width 3
-#define reg_sser_rw_frm_cfg___tr_delay___lsb 13
-#define reg_sser_rw_frm_cfg___tr_delay___width 3
-#define reg_sser_rw_frm_cfg___early_wend___lsb 16
-#define reg_sser_rw_frm_cfg___early_wend___width 1
-#define reg_sser_rw_frm_cfg___early_wend___bit 16
-#define reg_sser_rw_frm_cfg___level___lsb 17
-#define reg_sser_rw_frm_cfg___level___width 2
-#define reg_sser_rw_frm_cfg___type___lsb 19
-#define reg_sser_rw_frm_cfg___type___width 1
-#define reg_sser_rw_frm_cfg___type___bit 19
-#define reg_sser_rw_frm_cfg___clk_pol___lsb 20
-#define reg_sser_rw_frm_cfg___clk_pol___width 1
-#define reg_sser_rw_frm_cfg___clk_pol___bit 20
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___lsb 21
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___width 1
-#define reg_sser_rw_frm_cfg___fr_in_rxclk___bit 21
-#define reg_sser_rw_frm_cfg___clk_src___lsb 22
-#define reg_sser_rw_frm_cfg___clk_src___width 1
-#define reg_sser_rw_frm_cfg___clk_src___bit 22
-#define reg_sser_rw_frm_cfg___out_off___lsb 23
-#define reg_sser_rw_frm_cfg___out_off___width 1
-#define reg_sser_rw_frm_cfg___out_off___bit 23
-#define reg_sser_rw_frm_cfg___out_on___lsb 24
-#define reg_sser_rw_frm_cfg___out_on___width 1
-#define reg_sser_rw_frm_cfg___out_on___bit 24
-#define reg_sser_rw_frm_cfg___frame_pin_dir___lsb 25
-#define reg_sser_rw_frm_cfg___frame_pin_dir___width 1
-#define reg_sser_rw_frm_cfg___frame_pin_dir___bit 25
-#define reg_sser_rw_frm_cfg___frame_pin_use___lsb 26
-#define reg_sser_rw_frm_cfg___frame_pin_use___width 2
-#define reg_sser_rw_frm_cfg___status_pin_dir___lsb 28
-#define reg_sser_rw_frm_cfg___status_pin_dir___width 1
-#define reg_sser_rw_frm_cfg___status_pin_dir___bit 28
-#define reg_sser_rw_frm_cfg___status_pin_use___lsb 29
-#define reg_sser_rw_frm_cfg___status_pin_use___width 2
-#define reg_sser_rw_frm_cfg_offset 4
-
-/* Register rw_tr_cfg, scope sser, type rw */
-#define reg_sser_rw_tr_cfg___tr_en___lsb 0
-#define reg_sser_rw_tr_cfg___tr_en___width 1
-#define reg_sser_rw_tr_cfg___tr_en___bit 0
-#define reg_sser_rw_tr_cfg___stop___lsb 1
-#define reg_sser_rw_tr_cfg___stop___width 1
-#define reg_sser_rw_tr_cfg___stop___bit 1
-#define reg_sser_rw_tr_cfg___urun_stop___lsb 2
-#define reg_sser_rw_tr_cfg___urun_stop___width 1
-#define reg_sser_rw_tr_cfg___urun_stop___bit 2
-#define reg_sser_rw_tr_cfg___eop_stop___lsb 3
-#define reg_sser_rw_tr_cfg___eop_stop___width 1
-#define reg_sser_rw_tr_cfg___eop_stop___bit 3
-#define reg_sser_rw_tr_cfg___sample_size___lsb 4
-#define reg_sser_rw_tr_cfg___sample_size___width 6
-#define reg_sser_rw_tr_cfg___sh_dir___lsb 10
-#define reg_sser_rw_tr_cfg___sh_dir___width 1
-#define reg_sser_rw_tr_cfg___sh_dir___bit 10
-#define reg_sser_rw_tr_cfg___clk_pol___lsb 11
-#define reg_sser_rw_tr_cfg___clk_pol___width 1
-#define reg_sser_rw_tr_cfg___clk_pol___bit 11
-#define reg_sser_rw_tr_cfg___clk_src___lsb 12
-#define reg_sser_rw_tr_cfg___clk_src___width 1
-#define reg_sser_rw_tr_cfg___clk_src___bit 12
-#define reg_sser_rw_tr_cfg___use_dma___lsb 13
-#define reg_sser_rw_tr_cfg___use_dma___width 1
-#define reg_sser_rw_tr_cfg___use_dma___bit 13
-#define reg_sser_rw_tr_cfg___mode___lsb 14
-#define reg_sser_rw_tr_cfg___mode___width 2
-#define reg_sser_rw_tr_cfg___frm_src___lsb 16
-#define reg_sser_rw_tr_cfg___frm_src___width 1
-#define reg_sser_rw_tr_cfg___frm_src___bit 16
-#define reg_sser_rw_tr_cfg___use60958___lsb 17
-#define reg_sser_rw_tr_cfg___use60958___width 1
-#define reg_sser_rw_tr_cfg___use60958___bit 17
-#define reg_sser_rw_tr_cfg___iec60958_ckdiv___lsb 18
-#define reg_sser_rw_tr_cfg___iec60958_ckdiv___width 2
-#define reg_sser_rw_tr_cfg___rate_ctrl___lsb 20
-#define reg_sser_rw_tr_cfg___rate_ctrl___width 1
-#define reg_sser_rw_tr_cfg___rate_ctrl___bit 20
-#define reg_sser_rw_tr_cfg___use_md___lsb 21
-#define reg_sser_rw_tr_cfg___use_md___width 1
-#define reg_sser_rw_tr_cfg___use_md___bit 21
-#define reg_sser_rw_tr_cfg___dual_i2s___lsb 22
-#define reg_sser_rw_tr_cfg___dual_i2s___width 1
-#define reg_sser_rw_tr_cfg___dual_i2s___bit 22
-#define reg_sser_rw_tr_cfg___data_pin_use___lsb 23
-#define reg_sser_rw_tr_cfg___data_pin_use___width 2
-#define reg_sser_rw_tr_cfg___od_mode___lsb 25
-#define reg_sser_rw_tr_cfg___od_mode___width 1
-#define reg_sser_rw_tr_cfg___od_mode___bit 25
-#define reg_sser_rw_tr_cfg___bulk_wspace___lsb 26
-#define reg_sser_rw_tr_cfg___bulk_wspace___width 2
-#define reg_sser_rw_tr_cfg_offset 8
-
-/* Register rw_rec_cfg, scope sser, type rw */
-#define reg_sser_rw_rec_cfg___rec_en___lsb 0
-#define reg_sser_rw_rec_cfg___rec_en___width 1
-#define reg_sser_rw_rec_cfg___rec_en___bit 0
-#define reg_sser_rw_rec_cfg___force_eop___lsb 1
-#define reg_sser_rw_rec_cfg___force_eop___width 1
-#define reg_sser_rw_rec_cfg___force_eop___bit 1
-#define reg_sser_rw_rec_cfg___stop___lsb 2
-#define reg_sser_rw_rec_cfg___stop___width 1
-#define reg_sser_rw_rec_cfg___stop___bit 2
-#define reg_sser_rw_rec_cfg___orun_stop___lsb 3
-#define reg_sser_rw_rec_cfg___orun_stop___width 1
-#define reg_sser_rw_rec_cfg___orun_stop___bit 3
-#define reg_sser_rw_rec_cfg___eop_stop___lsb 4
-#define reg_sser_rw_rec_cfg___eop_stop___width 1
-#define reg_sser_rw_rec_cfg___eop_stop___bit 4
-#define reg_sser_rw_rec_cfg___sample_size___lsb 5
-#define reg_sser_rw_rec_cfg___sample_size___width 6
-#define reg_sser_rw_rec_cfg___sh_dir___lsb 11
-#define reg_sser_rw_rec_cfg___sh_dir___width 1
-#define reg_sser_rw_rec_cfg___sh_dir___bit 11
-#define reg_sser_rw_rec_cfg___clk_pol___lsb 12
-#define reg_sser_rw_rec_cfg___clk_pol___width 1
-#define reg_sser_rw_rec_cfg___clk_pol___bit 12
-#define reg_sser_rw_rec_cfg___clk_src___lsb 13
-#define reg_sser_rw_rec_cfg___clk_src___width 1
-#define reg_sser_rw_rec_cfg___clk_src___bit 13
-#define reg_sser_rw_rec_cfg___use_dma___lsb 14
-#define reg_sser_rw_rec_cfg___use_dma___width 1
-#define reg_sser_rw_rec_cfg___use_dma___bit 14
-#define reg_sser_rw_rec_cfg___mode___lsb 15
-#define reg_sser_rw_rec_cfg___mode___width 2
-#define reg_sser_rw_rec_cfg___frm_src___lsb 17
-#define reg_sser_rw_rec_cfg___frm_src___width 2
-#define reg_sser_rw_rec_cfg___use60958___lsb 19
-#define reg_sser_rw_rec_cfg___use60958___width 1
-#define reg_sser_rw_rec_cfg___use60958___bit 19
-#define reg_sser_rw_rec_cfg___iec60958_ui_len___lsb 20
-#define reg_sser_rw_rec_cfg___iec60958_ui_len___width 5
-#define reg_sser_rw_rec_cfg___slave2_en___lsb 25
-#define reg_sser_rw_rec_cfg___slave2_en___width 1
-#define reg_sser_rw_rec_cfg___slave2_en___bit 25
-#define reg_sser_rw_rec_cfg___slave3_en___lsb 26
-#define reg_sser_rw_rec_cfg___slave3_en___width 1
-#define reg_sser_rw_rec_cfg___slave3_en___bit 26
-#define reg_sser_rw_rec_cfg___fifo_thr___lsb 27
-#define reg_sser_rw_rec_cfg___fifo_thr___width 2
-#define reg_sser_rw_rec_cfg_offset 12
-
-/* Register rw_tr_data, scope sser, type rw */
-#define reg_sser_rw_tr_data___data___lsb 0
-#define reg_sser_rw_tr_data___data___width 16
-#define reg_sser_rw_tr_data___md___lsb 16
-#define reg_sser_rw_tr_data___md___width 1
-#define reg_sser_rw_tr_data___md___bit 16
-#define reg_sser_rw_tr_data_offset 16
-
-/* Register r_rec_data, scope sser, type r */
-#define reg_sser_r_rec_data___data___lsb 0
-#define reg_sser_r_rec_data___data___width 16
-#define reg_sser_r_rec_data___md___lsb 16
-#define reg_sser_r_rec_data___md___width 1
-#define reg_sser_r_rec_data___md___bit 16
-#define reg_sser_r_rec_data___ext_clk___lsb 17
-#define reg_sser_r_rec_data___ext_clk___width 1
-#define reg_sser_r_rec_data___ext_clk___bit 17
-#define reg_sser_r_rec_data___status_in___lsb 18
-#define reg_sser_r_rec_data___status_in___width 1
-#define reg_sser_r_rec_data___status_in___bit 18
-#define reg_sser_r_rec_data___frame_in___lsb 19
-#define reg_sser_r_rec_data___frame_in___width 1
-#define reg_sser_r_rec_data___frame_in___bit 19
-#define reg_sser_r_rec_data___din___lsb 20
-#define reg_sser_r_rec_data___din___width 1
-#define reg_sser_r_rec_data___din___bit 20
-#define reg_sser_r_rec_data___data_in___lsb 21
-#define reg_sser_r_rec_data___data_in___width 1
-#define reg_sser_r_rec_data___data_in___bit 21
-#define reg_sser_r_rec_data___clk_in___lsb 22
-#define reg_sser_r_rec_data___clk_in___width 1
-#define reg_sser_r_rec_data___clk_in___bit 22
-#define reg_sser_r_rec_data_offset 20
-
-/* Register rw_extra, scope sser, type rw */
-#define reg_sser_rw_extra___clkoff_cycles___lsb 0
-#define reg_sser_rw_extra___clkoff_cycles___width 20
-#define reg_sser_rw_extra___clkoff_en___lsb 20
-#define reg_sser_rw_extra___clkoff_en___width 1
-#define reg_sser_rw_extra___clkoff_en___bit 20
-#define reg_sser_rw_extra___clkon_en___lsb 21
-#define reg_sser_rw_extra___clkon_en___width 1
-#define reg_sser_rw_extra___clkon_en___bit 21
-#define reg_sser_rw_extra___dout_delay___lsb 22
-#define reg_sser_rw_extra___dout_delay___width 5
-#define reg_sser_rw_extra_offset 24
-
-/* Register rw_intr_mask, scope sser, type rw */
-#define reg_sser_rw_intr_mask___trdy___lsb 0
-#define reg_sser_rw_intr_mask___trdy___width 1
-#define reg_sser_rw_intr_mask___trdy___bit 0
-#define reg_sser_rw_intr_mask___rdav___lsb 1
-#define reg_sser_rw_intr_mask___rdav___width 1
-#define reg_sser_rw_intr_mask___rdav___bit 1
-#define reg_sser_rw_intr_mask___tidle___lsb 2
-#define reg_sser_rw_intr_mask___tidle___width 1
-#define reg_sser_rw_intr_mask___tidle___bit 2
-#define reg_sser_rw_intr_mask___rstop___lsb 3
-#define reg_sser_rw_intr_mask___rstop___width 1
-#define reg_sser_rw_intr_mask___rstop___bit 3
-#define reg_sser_rw_intr_mask___urun___lsb 4
-#define reg_sser_rw_intr_mask___urun___width 1
-#define reg_sser_rw_intr_mask___urun___bit 4
-#define reg_sser_rw_intr_mask___orun___lsb 5
-#define reg_sser_rw_intr_mask___orun___width 1
-#define reg_sser_rw_intr_mask___orun___bit 5
-#define reg_sser_rw_intr_mask___md_rec___lsb 6
-#define reg_sser_rw_intr_mask___md_rec___width 1
-#define reg_sser_rw_intr_mask___md_rec___bit 6
-#define reg_sser_rw_intr_mask___md_sent___lsb 7
-#define reg_sser_rw_intr_mask___md_sent___width 1
-#define reg_sser_rw_intr_mask___md_sent___bit 7
-#define reg_sser_rw_intr_mask___r958err___lsb 8
-#define reg_sser_rw_intr_mask___r958err___width 1
-#define reg_sser_rw_intr_mask___r958err___bit 8
-#define reg_sser_rw_intr_mask_offset 28
-
-/* Register rw_ack_intr, scope sser, type rw */
-#define reg_sser_rw_ack_intr___trdy___lsb 0
-#define reg_sser_rw_ack_intr___trdy___width 1
-#define reg_sser_rw_ack_intr___trdy___bit 0
-#define reg_sser_rw_ack_intr___rdav___lsb 1
-#define reg_sser_rw_ack_intr___rdav___width 1
-#define reg_sser_rw_ack_intr___rdav___bit 1
-#define reg_sser_rw_ack_intr___tidle___lsb 2
-#define reg_sser_rw_ack_intr___tidle___width 1
-#define reg_sser_rw_ack_intr___tidle___bit 2
-#define reg_sser_rw_ack_intr___rstop___lsb 3
-#define reg_sser_rw_ack_intr___rstop___width 1
-#define reg_sser_rw_ack_intr___rstop___bit 3
-#define reg_sser_rw_ack_intr___urun___lsb 4
-#define reg_sser_rw_ack_intr___urun___width 1
-#define reg_sser_rw_ack_intr___urun___bit 4
-#define reg_sser_rw_ack_intr___orun___lsb 5
-#define reg_sser_rw_ack_intr___orun___width 1
-#define reg_sser_rw_ack_intr___orun___bit 5
-#define reg_sser_rw_ack_intr___md_rec___lsb 6
-#define reg_sser_rw_ack_intr___md_rec___width 1
-#define reg_sser_rw_ack_intr___md_rec___bit 6
-#define reg_sser_rw_ack_intr___md_sent___lsb 7
-#define reg_sser_rw_ack_intr___md_sent___width 1
-#define reg_sser_rw_ack_intr___md_sent___bit 7
-#define reg_sser_rw_ack_intr___r958err___lsb 8
-#define reg_sser_rw_ack_intr___r958err___width 1
-#define reg_sser_rw_ack_intr___r958err___bit 8
-#define reg_sser_rw_ack_intr_offset 32
-
-/* Register r_intr, scope sser, type r */
-#define reg_sser_r_intr___trdy___lsb 0
-#define reg_sser_r_intr___trdy___width 1
-#define reg_sser_r_intr___trdy___bit 0
-#define reg_sser_r_intr___rdav___lsb 1
-#define reg_sser_r_intr___rdav___width 1
-#define reg_sser_r_intr___rdav___bit 1
-#define reg_sser_r_intr___tidle___lsb 2
-#define reg_sser_r_intr___tidle___width 1
-#define reg_sser_r_intr___tidle___bit 2
-#define reg_sser_r_intr___rstop___lsb 3
-#define reg_sser_r_intr___rstop___width 1
-#define reg_sser_r_intr___rstop___bit 3
-#define reg_sser_r_intr___urun___lsb 4
-#define reg_sser_r_intr___urun___width 1
-#define reg_sser_r_intr___urun___bit 4
-#define reg_sser_r_intr___orun___lsb 5
-#define reg_sser_r_intr___orun___width 1
-#define reg_sser_r_intr___orun___bit 5
-#define reg_sser_r_intr___md_rec___lsb 6
-#define reg_sser_r_intr___md_rec___width 1
-#define reg_sser_r_intr___md_rec___bit 6
-#define reg_sser_r_intr___md_sent___lsb 7
-#define reg_sser_r_intr___md_sent___width 1
-#define reg_sser_r_intr___md_sent___bit 7
-#define reg_sser_r_intr___r958err___lsb 8
-#define reg_sser_r_intr___r958err___width 1
-#define reg_sser_r_intr___r958err___bit 8
-#define reg_sser_r_intr_offset 36
-
-/* Register r_masked_intr, scope sser, type r */
-#define reg_sser_r_masked_intr___trdy___lsb 0
-#define reg_sser_r_masked_intr___trdy___width 1
-#define reg_sser_r_masked_intr___trdy___bit 0
-#define reg_sser_r_masked_intr___rdav___lsb 1
-#define reg_sser_r_masked_intr___rdav___width 1
-#define reg_sser_r_masked_intr___rdav___bit 1
-#define reg_sser_r_masked_intr___tidle___lsb 2
-#define reg_sser_r_masked_intr___tidle___width 1
-#define reg_sser_r_masked_intr___tidle___bit 2
-#define reg_sser_r_masked_intr___rstop___lsb 3
-#define reg_sser_r_masked_intr___rstop___width 1
-#define reg_sser_r_masked_intr___rstop___bit 3
-#define reg_sser_r_masked_intr___urun___lsb 4
-#define reg_sser_r_masked_intr___urun___width 1
-#define reg_sser_r_masked_intr___urun___bit 4
-#define reg_sser_r_masked_intr___orun___lsb 5
-#define reg_sser_r_masked_intr___orun___width 1
-#define reg_sser_r_masked_intr___orun___bit 5
-#define reg_sser_r_masked_intr___md_rec___lsb 6
-#define reg_sser_r_masked_intr___md_rec___width 1
-#define reg_sser_r_masked_intr___md_rec___bit 6
-#define reg_sser_r_masked_intr___md_sent___lsb 7
-#define reg_sser_r_masked_intr___md_sent___width 1
-#define reg_sser_r_masked_intr___md_sent___bit 7
-#define reg_sser_r_masked_intr___r958err___lsb 8
-#define reg_sser_r_masked_intr___r958err___width 1
-#define reg_sser_r_masked_intr___r958err___bit 8
-#define reg_sser_r_masked_intr_offset 40
-
-
-/* Constants */
-#define regk_sser_both 0x00000002
-#define regk_sser_bulk 0x00000001
-#define regk_sser_clk100 0x00000000
-#define regk_sser_clk_in 0x00000000
-#define regk_sser_const0 0x00000003
-#define regk_sser_dout 0x00000002
-#define regk_sser_edge 0x00000000
-#define regk_sser_ext 0x00000001
-#define regk_sser_ext_clk 0x00000001
-#define regk_sser_f100 0x00000000
-#define regk_sser_f29_493 0x00000004
-#define regk_sser_f32 0x00000005
-#define regk_sser_f32_768 0x00000006
-#define regk_sser_frm 0x00000003
-#define regk_sser_gio0 0x00000000
-#define regk_sser_gio1 0x00000001
-#define regk_sser_hispeed 0x00000001
-#define regk_sser_hold 0x00000002
-#define regk_sser_in 0x00000000
-#define regk_sser_inf 0x00000003
-#define regk_sser_intern 0x00000000
-#define regk_sser_intern_clk 0x00000001
-#define regk_sser_intern_tb 0x00000000
-#define regk_sser_iso 0x00000000
-#define regk_sser_level 0x00000001
-#define regk_sser_lospeed 0x00000000
-#define regk_sser_lsbfirst 0x00000000
-#define regk_sser_msbfirst 0x00000001
-#define regk_sser_neg 0x00000001
-#define regk_sser_neg_lo 0x00000000
-#define regk_sser_no 0x00000000
-#define regk_sser_no_clk 0x00000007
-#define regk_sser_nojitter 0x00000002
-#define regk_sser_out 0x00000001
-#define regk_sser_pos 0x00000000
-#define regk_sser_pos_hi 0x00000001
-#define regk_sser_rec 0x00000000
-#define regk_sser_rw_cfg_default 0x00000000
-#define regk_sser_rw_extra_default 0x00000000
-#define regk_sser_rw_frm_cfg_default 0x00000000
-#define regk_sser_rw_intr_mask_default 0x00000000
-#define regk_sser_rw_rec_cfg_default 0x00000000
-#define regk_sser_rw_tr_cfg_default 0x01800000
-#define regk_sser_rw_tr_data_default 0x00000000
-#define regk_sser_thr16 0x00000001
-#define regk_sser_thr32 0x00000002
-#define regk_sser_thr8 0x00000000
-#define regk_sser_tr 0x00000001
-#define regk_sser_ts_out 0x00000003
-#define regk_sser_tx_bulk 0x00000002
-#define regk_sser_wiresave 0x00000002
-#define regk_sser_yes 0x00000001
-#endif /* __sser_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h
deleted file mode 100644
index fab117b00ab6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/strcop_defs_asm.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strcop_defs_asm_h
-#define __strcop_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strcop/rtl/strcop_regs.r
- * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
- * last modfied: Mon Apr 11 16:09:38 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strcop_defs_asm.h ../../inst/strcop/rtl/strcop_regs.r
- * id: $Id: strcop_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope strcop, type rw */
-#define reg_strcop_rw_cfg___td3___lsb 0
-#define reg_strcop_rw_cfg___td3___width 1
-#define reg_strcop_rw_cfg___td3___bit 0
-#define reg_strcop_rw_cfg___td2___lsb 1
-#define reg_strcop_rw_cfg___td2___width 1
-#define reg_strcop_rw_cfg___td2___bit 1
-#define reg_strcop_rw_cfg___td1___lsb 2
-#define reg_strcop_rw_cfg___td1___width 1
-#define reg_strcop_rw_cfg___td1___bit 2
-#define reg_strcop_rw_cfg___ipend___lsb 3
-#define reg_strcop_rw_cfg___ipend___width 1
-#define reg_strcop_rw_cfg___ipend___bit 3
-#define reg_strcop_rw_cfg___ignore_sync___lsb 4
-#define reg_strcop_rw_cfg___ignore_sync___width 1
-#define reg_strcop_rw_cfg___ignore_sync___bit 4
-#define reg_strcop_rw_cfg___en___lsb 5
-#define reg_strcop_rw_cfg___en___width 1
-#define reg_strcop_rw_cfg___en___bit 5
-#define reg_strcop_rw_cfg_offset 0
-
-
-/* Constants */
-#define regk_strcop_big 0x00000001
-#define regk_strcop_d 0x00000001
-#define regk_strcop_e 0x00000000
-#define regk_strcop_little 0x00000000
-#define regk_strcop_rw_cfg_default 0x00000002
-#endif /* __strcop_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h
deleted file mode 100644
index 73755fa8a526..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/strmux_defs_asm.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strmux_defs_asm_h
-#define __strmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
- * last modfied: Mon Apr 11 16:09:43 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/strmux_defs_asm.h ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: $Id: strmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope strmux, type rw */
-#define reg_strmux_rw_cfg___dma0___lsb 0
-#define reg_strmux_rw_cfg___dma0___width 3
-#define reg_strmux_rw_cfg___dma1___lsb 3
-#define reg_strmux_rw_cfg___dma1___width 3
-#define reg_strmux_rw_cfg___dma2___lsb 6
-#define reg_strmux_rw_cfg___dma2___width 3
-#define reg_strmux_rw_cfg___dma3___lsb 9
-#define reg_strmux_rw_cfg___dma3___width 3
-#define reg_strmux_rw_cfg___dma4___lsb 12
-#define reg_strmux_rw_cfg___dma4___width 3
-#define reg_strmux_rw_cfg___dma5___lsb 15
-#define reg_strmux_rw_cfg___dma5___width 3
-#define reg_strmux_rw_cfg___dma6___lsb 18
-#define reg_strmux_rw_cfg___dma6___width 3
-#define reg_strmux_rw_cfg___dma7___lsb 21
-#define reg_strmux_rw_cfg___dma7___width 3
-#define reg_strmux_rw_cfg___dma8___lsb 24
-#define reg_strmux_rw_cfg___dma8___width 3
-#define reg_strmux_rw_cfg___dma9___lsb 27
-#define reg_strmux_rw_cfg___dma9___width 3
-#define reg_strmux_rw_cfg_offset 0
-
-
-/* Constants */
-#define regk_strmux_ata 0x00000003
-#define regk_strmux_eth0 0x00000001
-#define regk_strmux_eth1 0x00000004
-#define regk_strmux_ext0 0x00000001
-#define regk_strmux_ext1 0x00000001
-#define regk_strmux_ext2 0x00000001
-#define regk_strmux_ext3 0x00000001
-#define regk_strmux_iop0 0x00000002
-#define regk_strmux_iop1 0x00000001
-#define regk_strmux_off 0x00000000
-#define regk_strmux_p21 0x00000004
-#define regk_strmux_rw_cfg_default 0x00000000
-#define regk_strmux_ser0 0x00000002
-#define regk_strmux_ser1 0x00000002
-#define regk_strmux_ser2 0x00000004
-#define regk_strmux_ser3 0x00000003
-#define regk_strmux_sser0 0x00000003
-#define regk_strmux_sser1 0x00000003
-#define regk_strmux_strcop 0x00000002
-#endif /* __strmux_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index cc67986d7437..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/timer/rtl/timer_regs.r
- * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
- * last modfied: Mon Apr 11 16:09:53 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
- * id: $Id: timer_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext 0x00000001
-#define regk_timer_f100 0x00000007
-#define regk_timer_f29_493 0x00000004
-#define regk_timer_f32 0x00000005
-#define regk_timer_f32_768 0x00000006
-#define regk_timer_hold 0x00000001
-#define regk_timer_ld 0x00000000
-#define regk_timer_no 0x00000000
-#define regk_timer_off 0x00000000
-#define regk_timer_run 0x00000002
-#define regk_timer_rw_cnt_cfg_default 0x00000000
-#define regk_timer_rw_intr_mask_default 0x00000000
-#define regk_timer_rw_out_default 0x00000000
-#define regk_timer_rw_test_default 0x00000000
-#define regk_timer_rw_tmr0_ctrl_default 0x00000000
-#define regk_timer_rw_tmr1_ctrl_default 0x00000000
-#define regk_timer_rw_trig_cfg_default 0x00000000
-#define regk_timer_start 0x00000001
-#define regk_timer_stop 0x00000000
-#define regk_timer_time 0x00000001
-#define regk_timer_tmr0 0x00000002
-#define regk_timer_tmr1 0x00000003
-#define regk_timer_yes 0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h
deleted file mode 100644
index 2a8adbcf75d8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/ata_defs.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ata_defs_h
-#define __ata_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ata/rtl/ata_regs.r
- * id: ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
- * last modfied: Mon Apr 11 16:06:25 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ata_defs.h ../../inst/ata/rtl/ata_regs.r
- * id: $Id: ata_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ata */
-
-/* Register rw_ctrl0, scope ata, type rw */
-typedef struct {
- unsigned int pio_hold : 6;
- unsigned int pio_strb : 6;
- unsigned int pio_setup : 6;
- unsigned int dma_hold : 6;
- unsigned int dma_strb : 6;
- unsigned int rst : 1;
- unsigned int en : 1;
-} reg_ata_rw_ctrl0;
-#define REG_RD_ADDR_ata_rw_ctrl0 12
-#define REG_WR_ADDR_ata_rw_ctrl0 12
-
-/* Register rw_ctrl1, scope ata, type rw */
-typedef struct {
- unsigned int udma_tcyc : 4;
- unsigned int udma_tdvs : 4;
- unsigned int dummy1 : 24;
-} reg_ata_rw_ctrl1;
-#define REG_RD_ADDR_ata_rw_ctrl1 16
-#define REG_WR_ADDR_ata_rw_ctrl1 16
-
-/* Register rw_ctrl2, scope ata, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 3;
- unsigned int dma_size : 1;
- unsigned int multi : 1;
- unsigned int hsh : 2;
- unsigned int trf_mode : 1;
- unsigned int rw : 1;
- unsigned int addr : 3;
- unsigned int cs0 : 1;
- unsigned int cs1 : 1;
- unsigned int sel : 2;
-} reg_ata_rw_ctrl2;
-#define REG_RD_ADDR_ata_rw_ctrl2 0
-#define REG_WR_ADDR_ata_rw_ctrl2 0
-
-/* Register rs_stat_data, scope ata, type rs */
-typedef struct {
- unsigned int data : 16;
- unsigned int dav : 1;
- unsigned int busy : 1;
- unsigned int dummy1 : 14;
-} reg_ata_rs_stat_data;
-#define REG_RD_ADDR_ata_rs_stat_data 4
-
-/* Register r_stat_data, scope ata, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int dav : 1;
- unsigned int busy : 1;
- unsigned int dummy1 : 14;
-} reg_ata_r_stat_data;
-#define REG_RD_ADDR_ata_r_stat_data 8
-
-/* Register rw_trf_cnt, scope ata, type rw */
-typedef struct {
- unsigned int cnt : 17;
- unsigned int dummy1 : 15;
-} reg_ata_rw_trf_cnt;
-#define REG_RD_ADDR_ata_rw_trf_cnt 20
-#define REG_WR_ADDR_ata_rw_trf_cnt 20
-
-/* Register r_stat_misc, scope ata, type r */
-typedef struct {
- unsigned int crc : 16;
- unsigned int dummy1 : 16;
-} reg_ata_r_stat_misc;
-#define REG_RD_ADDR_ata_r_stat_misc 24
-
-/* Register rw_intr_mask, scope ata, type rw */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_rw_intr_mask;
-#define REG_RD_ADDR_ata_rw_intr_mask 28
-#define REG_WR_ADDR_ata_rw_intr_mask 28
-
-/* Register rw_ack_intr, scope ata, type rw */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_rw_ack_intr;
-#define REG_RD_ADDR_ata_rw_ack_intr 32
-#define REG_WR_ADDR_ata_rw_ack_intr 32
-
-/* Register r_intr, scope ata, type r */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_r_intr;
-#define REG_RD_ADDR_ata_r_intr 36
-
-/* Register r_masked_intr, scope ata, type r */
-typedef struct {
- unsigned int bus0 : 1;
- unsigned int bus1 : 1;
- unsigned int bus2 : 1;
- unsigned int bus3 : 1;
- unsigned int dummy1 : 28;
-} reg_ata_r_masked_intr;
-#define REG_RD_ADDR_ata_r_masked_intr 40
-
-
-/* Constants */
-enum {
- regk_ata_active = 0x00000001,
- regk_ata_byte = 0x00000001,
- regk_ata_data = 0x00000001,
- regk_ata_dma = 0x00000001,
- regk_ata_inactive = 0x00000000,
- regk_ata_no = 0x00000000,
- regk_ata_nodata = 0x00000000,
- regk_ata_pio = 0x00000000,
- regk_ata_rd = 0x00000001,
- regk_ata_reg = 0x00000000,
- regk_ata_rw_ctrl0_default = 0x00000000,
- regk_ata_rw_ctrl2_default = 0x00000000,
- regk_ata_rw_intr_mask_default = 0x00000000,
- regk_ata_udma = 0x00000002,
- regk_ata_word = 0x00000000,
- regk_ata_wr = 0x00000000,
- regk_ata_yes = 0x00000001
-};
-#endif /* __ata_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h
deleted file mode 100644
index 054841c45466..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/bif_core_defs.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_h
-#define __bif_core_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_core */
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp1_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
-#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp2_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
-#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 2;
- unsigned int gated_csp0 : 2;
- unsigned int gated_csp1 : 2;
- unsigned int gated_csp2 : 2;
- unsigned int gated_csp3 : 2;
-} reg_bif_core_rw_grp3_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
-#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 4;
- unsigned int gated_csp4 : 2;
- unsigned int gated_csp5 : 2;
- unsigned int gated_csp6 : 2;
-} reg_bif_core_rw_grp4_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
-#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int grp_sel : 5;
- unsigned int dummy1 : 12;
-} reg_bif_core_rw_sdram_cfg_grp0;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int dummy1 : 17;
-} reg_bif_core_rw_sdram_cfg_grp1;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-typedef struct {
- unsigned int cl : 3;
- unsigned int rcd : 3;
- unsigned int rp : 3;
- unsigned int rc : 2;
- unsigned int dpl : 2;
- unsigned int pde : 1;
- unsigned int ref : 2;
- unsigned int cpd : 1;
- unsigned int sdcke : 1;
- unsigned int sdclk : 1;
- unsigned int dummy1 : 13;
-} reg_bif_core_rw_sdram_timing;
-#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
-#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-typedef struct {
- unsigned int cmd : 3;
- unsigned int mrs_data : 15;
- unsigned int dummy1 : 14;
-} reg_bif_core_rw_sdram_cmd;
-#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
-#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_rs_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_r_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
-
-
-/* Constants */
-enum {
- regk_bif_core_bank2 = 0x00000000,
- regk_bif_core_bank4 = 0x00000001,
- regk_bif_core_bit10 = 0x0000000a,
- regk_bif_core_bit11 = 0x0000000b,
- regk_bif_core_bit12 = 0x0000000c,
- regk_bif_core_bit13 = 0x0000000d,
- regk_bif_core_bit14 = 0x0000000e,
- regk_bif_core_bit15 = 0x0000000f,
- regk_bif_core_bit16 = 0x00000010,
- regk_bif_core_bit17 = 0x00000011,
- regk_bif_core_bit18 = 0x00000012,
- regk_bif_core_bit19 = 0x00000013,
- regk_bif_core_bit20 = 0x00000014,
- regk_bif_core_bit21 = 0x00000015,
- regk_bif_core_bit22 = 0x00000016,
- regk_bif_core_bit23 = 0x00000017,
- regk_bif_core_bit24 = 0x00000018,
- regk_bif_core_bit25 = 0x00000019,
- regk_bif_core_bit26 = 0x0000001a,
- regk_bif_core_bit27 = 0x0000001b,
- regk_bif_core_bit28 = 0x0000001c,
- regk_bif_core_bit29 = 0x0000001d,
- regk_bif_core_bit9 = 0x00000009,
- regk_bif_core_bw16 = 0x00000001,
- regk_bif_core_bw32 = 0x00000000,
- regk_bif_core_bwe = 0x00000000,
- regk_bif_core_cwe = 0x00000001,
- regk_bif_core_e15us = 0x00000001,
- regk_bif_core_e7800ns = 0x00000002,
- regk_bif_core_grp0 = 0x00000000,
- regk_bif_core_grp1 = 0x00000001,
- regk_bif_core_mrs = 0x00000003,
- regk_bif_core_no = 0x00000000,
- regk_bif_core_none = 0x00000000,
- regk_bif_core_nop = 0x00000000,
- regk_bif_core_off = 0x00000000,
- regk_bif_core_pre = 0x00000002,
- regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rd = 0x00000002,
- regk_bif_core_ref = 0x00000001,
- regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
- regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
- regk_bif_core_slf = 0x00000004,
- regk_bif_core_wr = 0x00000001,
- regk_bif_core_yes = 0x00000001
-};
-#endif /* __bif_core_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h
deleted file mode 100644
index 5c4abf5c0167..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_dma_defs_h
-#define __bif_dma_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_dma_regs.r
- * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
- * id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_dma */
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch0_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
-#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch0_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
-#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch0_start;
-#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
-#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch0_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
-#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch0_stat;
-#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch1_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
-#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch1_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
-#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch1_start;
-#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
-#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch1_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
-#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch1_stat;
-#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch2_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
-#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch2_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
-#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch2_start;
-#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
-#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch2_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
-#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch2_stat;
-#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch3_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
-#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch3_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
-#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch3_start;
-#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
-#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch3_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
-#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch3_stat;
-#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_intr_mask;
-#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
-#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_ack_intr;
-#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
-#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
-
-/* Register r_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_intr;
-#define REG_RD_ADDR_bif_dma_r_intr 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_masked_intr;
-#define REG_RD_ADDR_bif_dma_r_masked_intr 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin0_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
-#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin1_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
-#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin2_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
-#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin3_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
-#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin4_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
-#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin5_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
-#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin6_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
-#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin7_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
-#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int pin0 : 1;
- unsigned int pin1 : 1;
- unsigned int pin2 : 1;
- unsigned int pin3 : 1;
- unsigned int pin4 : 1;
- unsigned int pin5 : 1;
- unsigned int pin6 : 1;
- unsigned int pin7 : 1;
- unsigned int dummy1 : 24;
-} reg_bif_dma_r_pin_stat;
-#define REG_RD_ADDR_bif_dma_r_pin_stat 192
-
-
-/* Constants */
-enum {
- regk_bif_dma_as_master = 0x00000001,
- regk_bif_dma_as_slave = 0x00000001,
- regk_bif_dma_burst1 = 0x00000000,
- regk_bif_dma_burst8 = 0x00000001,
- regk_bif_dma_bw16 = 0x00000001,
- regk_bif_dma_bw32 = 0x00000002,
- regk_bif_dma_bw8 = 0x00000000,
- regk_bif_dma_dack = 0x00000006,
- regk_bif_dma_dack_inv = 0x00000007,
- regk_bif_dma_force = 0x00000001,
- regk_bif_dma_hi = 0x00000003,
- regk_bif_dma_inv = 0x00000003,
- regk_bif_dma_lo = 0x00000002,
- regk_bif_dma_master = 0x00000001,
- regk_bif_dma_no = 0x00000000,
- regk_bif_dma_norm = 0x00000002,
- regk_bif_dma_off = 0x00000000,
- regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch0_start_default = 0x00000000,
- regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch1_start_default = 0x00000000,
- regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch2_start_default = 0x00000000,
- regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch3_start_default = 0x00000000,
- regk_bif_dma_rw_intr_mask_default = 0x00000000,
- regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
- regk_bif_dma_slave = 0x00000002,
- regk_bif_dma_sreq = 0x00000006,
- regk_bif_dma_sreq_inv = 0x00000007,
- regk_bif_dma_tc = 0x00000004,
- regk_bif_dma_tc_inv = 0x00000005,
- regk_bif_dma_yes = 0x00000001
-};
-#endif /* __bif_dma_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h
deleted file mode 100644
index 80c740b3c785..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/bif_slave_defs.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_slave_defs_h
-#define __bif_slave_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_slave_regs.r
- * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- * last modfied: Mon Apr 11 16:06:34 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
- * id: $Id: bif_slave_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_slave */
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int slave_id : 3;
- unsigned int use_slave_id : 1;
- unsigned int boot_rdy : 1;
- unsigned int loopback : 1;
- unsigned int dis : 1;
- unsigned int dummy1 : 25;
-} reg_bif_slave_rw_slave_cfg;
-#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
-#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-typedef struct {
- unsigned int ch0_mode : 1;
- unsigned int ch1_mode : 1;
- unsigned int ch2_mode : 1;
- unsigned int ch3_mode : 1;
- unsigned int dummy1 : 28;
-} reg_bif_slave_r_slave_mode;
-#define REG_RD_ADDR_bif_slave_r_slave_mode 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch0_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
-#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch1_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
-#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch2_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
-#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch3_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
-#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int brin_mode : 1;
- unsigned int brout_mode : 3;
- unsigned int bg_mode : 3;
- unsigned int release : 2;
- unsigned int acquire : 1;
- unsigned int settle_time : 2;
- unsigned int dram_ctrl : 1;
- unsigned int dummy1 : 19;
-} reg_bif_slave_rw_arb_cfg;
-#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
-#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-typedef struct {
- unsigned int init_mode : 1;
- unsigned int mode : 1;
- unsigned int brin : 1;
- unsigned int brout : 1;
- unsigned int bg : 1;
- unsigned int dummy1 : 27;
-} reg_bif_slave_r_arb_stat;
-#define REG_RD_ADDR_bif_slave_r_arb_stat 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_intr_mask;
-#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
-#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_ack_intr;
-#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
-#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
-
-/* Register r_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_intr;
-#define REG_RD_ADDR_bif_slave_r_intr 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_masked_intr;
-#define REG_RD_ADDR_bif_slave_r_masked_intr 76
-
-
-/* Constants */
-enum {
- regk_bif_slave_active_hi = 0x00000003,
- regk_bif_slave_active_lo = 0x00000002,
- regk_bif_slave_addr = 0x00000000,
- regk_bif_slave_always = 0x00000001,
- regk_bif_slave_at_idle = 0x00000002,
- regk_bif_slave_burst_end = 0x00000003,
- regk_bif_slave_dma = 0x00000001,
- regk_bif_slave_hi = 0x00000003,
- regk_bif_slave_inv = 0x00000001,
- regk_bif_slave_lo = 0x00000002,
- regk_bif_slave_local = 0x00000001,
- regk_bif_slave_master = 0x00000000,
- regk_bif_slave_mode_reg = 0x00000001,
- regk_bif_slave_no = 0x00000000,
- regk_bif_slave_norm = 0x00000000,
- regk_bif_slave_on_access = 0x00000000,
- regk_bif_slave_rw_arb_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
- regk_bif_slave_rw_intr_mask_default = 0x00000000,
- regk_bif_slave_rw_slave_cfg_default = 0x00000000,
- regk_bif_slave_shared = 0x00000000,
- regk_bif_slave_slave = 0x00000001,
- regk_bif_slave_t0ns = 0x00000003,
- regk_bif_slave_t10ns = 0x00000002,
- regk_bif_slave_t20ns = 0x00000003,
- regk_bif_slave_t30ns = 0x00000002,
- regk_bif_slave_t40ns = 0x00000001,
- regk_bif_slave_t50ns = 0x00000000,
- regk_bif_slave_yes = 0x00000001,
- regk_bif_slave_z = 0x00000004
-};
-#endif /* __bif_slave_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/config_defs.h b/arch/cris/include/arch-v32/arch/hwregs/config_defs.h
deleted file mode 100644
index 1c5da14f27f3..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/config_defs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_h
-#define __config_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
- * id: $Id: config_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope config */
-
-/* Register r_bootsel, scope config, type r */
-typedef struct {
- unsigned int boot_mode : 3;
- unsigned int full_duplex : 1;
- unsigned int user : 1;
- unsigned int pll : 1;
- unsigned int flash_bw : 1;
- unsigned int dummy1 : 25;
-} reg_config_r_bootsel;
-#define REG_RD_ADDR_config_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-typedef struct {
- unsigned int pll : 1;
- unsigned int cpu : 1;
- unsigned int iop : 1;
- unsigned int dma01_eth0 : 1;
- unsigned int dma23 : 1;
- unsigned int dma45 : 1;
- unsigned int dma67 : 1;
- unsigned int dma89_strcop : 1;
- unsigned int bif : 1;
- unsigned int fix_io : 1;
- unsigned int dummy1 : 22;
-} reg_config_rw_clk_ctrl;
-#define REG_RD_ADDR_config_rw_clk_ctrl 4
-#define REG_WR_ADDR_config_rw_clk_ctrl 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-typedef struct {
- unsigned int usb_susp : 1;
- unsigned int phyrst_n : 1;
- unsigned int dummy1 : 30;
-} reg_config_rw_pad_ctrl;
-#define REG_RD_ADDR_config_rw_pad_ctrl 8
-#define REG_WR_ADDR_config_rw_pad_ctrl 8
-
-
-/* Constants */
-enum {
- regk_config_bw16 = 0x00000000,
- regk_config_bw32 = 0x00000001,
- regk_config_master = 0x00000005,
- regk_config_nand = 0x00000003,
- regk_config_net_rx = 0x00000001,
- regk_config_net_tx_rx = 0x00000002,
- regk_config_no = 0x00000000,
- regk_config_none = 0x00000007,
- regk_config_nor = 0x00000000,
- regk_config_rw_clk_ctrl_default = 0x00000002,
- regk_config_rw_pad_ctrl_default = 0x00000000,
- regk_config_ser = 0x00000004,
- regk_config_slave = 0x00000006,
- regk_config_yes = 0x00000001
-};
-#endif /* __config_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h b/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h
deleted file mode 100644
index 913f918bba14..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/crisp/doc/cpu_vect.r
-version . */
-
-#ifndef _______INST_CRISP_DOC_CPU_VECT_R
-#define _______INST_CRISP_DOC_CPU_VECT_R
-#define NMI_INTR_VECT 0x00
-#define RESERVED_1_INTR_VECT 0x01
-#define RESERVED_2_INTR_VECT 0x02
-#define SINGLE_STEP_INTR_VECT 0x03
-#define INSTR_TLB_REFILL_INTR_VECT 0x04
-#define INSTR_TLB_INV_INTR_VECT 0x05
-#define INSTR_TLB_ACC_INTR_VECT 0x06
-#define TLB_EX_INTR_VECT 0x07
-#define DATA_TLB_REFILL_INTR_VECT 0x08
-#define DATA_TLB_INV_INTR_VECT 0x09
-#define DATA_TLB_ACC_INTR_VECT 0x0a
-#define DATA_TLB_WE_INTR_VECT 0x0b
-#define HW_BP_INTR_VECT 0x0c
-#define RESERVED_D_INTR_VECT 0x0d
-#define RESERVED_E_INTR_VECT 0x0e
-#define RESERVED_F_INTR_VECT 0x0f
-#define BREAK_0_INTR_VECT 0x10
-#define BREAK_1_INTR_VECT 0x11
-#define BREAK_2_INTR_VECT 0x12
-#define BREAK_3_INTR_VECT 0x13
-#define BREAK_4_INTR_VECT 0x14
-#define BREAK_5_INTR_VECT 0x15
-#define BREAK_6_INTR_VECT 0x16
-#define BREAK_7_INTR_VECT 0x17
-#define BREAK_8_INTR_VECT 0x18
-#define BREAK_9_INTR_VECT 0x19
-#define BREAK_10_INTR_VECT 0x1a
-#define BREAK_11_INTR_VECT 0x1b
-#define BREAK_12_INTR_VECT 0x1c
-#define BREAK_13_INTR_VECT 0x1d
-#define BREAK_14_INTR_VECT 0x1e
-#define BREAK_15_INTR_VECT 0x1f
-#define MULTIPLE_INTR_VECT 0x30
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma.h b/arch/cris/include/arch-v32/arch/hwregs/dma.h
deleted file mode 100644
index dd24c6da09e0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/dma.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * DMA C definitions and help macros
- *
- */
-
-#ifndef dma_h
-#define dma_h
-
-/* registers */ /* Really needed, since both are listed in sw.list? */
-#include <arch/hwregs/dma_defs.h>
-
-
-/* descriptors */
-
-// ------------------------------------------------------------ dma_descr_group
-typedef struct dma_descr_group {
- struct dma_descr_group *next;
- unsigned eol : 1;
- unsigned tol : 1;
- unsigned bol : 1;
- unsigned : 1;
- unsigned intr : 1;
- unsigned : 2;
- unsigned en : 1;
- unsigned : 7;
- unsigned dis : 1;
- unsigned md : 16;
- struct dma_descr_group *up;
- union {
- struct dma_descr_context *context;
- struct dma_descr_group *group;
- } down;
-} dma_descr_group;
-
-// ---------------------------------------------------------- dma_descr_context
-typedef struct dma_descr_context {
- struct dma_descr_context *next;
- unsigned eol : 1;
- unsigned : 3;
- unsigned intr : 1;
- unsigned : 1;
- unsigned store_mode : 1;
- unsigned en : 1;
- unsigned : 7;
- unsigned dis : 1;
- unsigned md0 : 16;
- unsigned md1;
- unsigned md2;
- unsigned md3;
- unsigned md4;
- struct dma_descr_data *saved_data;
- char *saved_data_buf;
-} dma_descr_context;
-
-// ------------------------------------------------------------- dma_descr_data
-typedef struct dma_descr_data {
- struct dma_descr_data *next;
- char *buf;
- unsigned eol : 1;
- unsigned : 2;
- unsigned out_eop : 1;
- unsigned intr : 1;
- unsigned wait : 1;
- unsigned : 2;
- unsigned : 3;
- unsigned in_eop : 1;
- unsigned : 4;
- unsigned md : 16;
- char *after;
-} dma_descr_data;
-
-// --------------------------------------------------------------------- macros
-
-// enable DMA channel
-#define DMA_ENABLE( inst ) \
- do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
- e.en = regk_dma_yes; \
- REG_WR( dma, inst, rw_cfg, e); } while( 0 )
-
-// reset DMA channel
-#define DMA_RESET( inst ) \
- do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
- r.en = regk_dma_no; \
- REG_WR( dma, inst, rw_cfg, r); } while( 0 )
-
-// stop DMA channel
-#define DMA_STOP( inst ) \
- do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
- s.stop = regk_dma_yes; \
- REG_WR( dma, inst, rw_cfg, s); } while( 0 )
-
-// continue DMA channel operation
-#define DMA_CONTINUE( inst ) \
- do { reg_dma_rw_cfg c = REG_RD( dma, inst, rw_cfg );\
- c.stop = regk_dma_no; \
- REG_WR( dma, inst, rw_cfg, c); } while( 0 )
-
-// give stream command
-#define DMA_WR_CMD( inst, cmd_par ) \
- do { reg_dma_rw_stream_cmd __x = {0}; \
- do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
- __x.cmd = (cmd_par); \
- REG_WR(dma, inst, rw_stream_cmd, __x); \
- } while (0)
-
-// load: g,c,d:burst
-#define DMA_START_GROUP( inst, group_descr ) \
- do { REG_WR_INT( dma, inst, rw_group, (int) group_descr ); \
- DMA_WR_CMD( inst, regk_dma_load_g ); \
- DMA_WR_CMD( inst, regk_dma_load_c ); \
- DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
- } while( 0 )
-
-// load: c,d:burst
-#define DMA_START_CONTEXT( inst, ctx_descr ) \
- do { REG_WR_INT( dma, inst, rw_group_down, (int) ctx_descr ); \
- DMA_WR_CMD( inst, regk_dma_load_c ); \
- DMA_WR_CMD( inst, regk_dma_load_d | regk_dma_burst ); \
- } while( 0 )
-
-// if the DMA is at the end of the data list, the last data descr is reloaded
-#define DMA_CONTINUE_DATA( inst ) \
-do { reg_dma_rw_cmd c = {0}; \
- c.cont_data = regk_dma_yes;\
- REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h b/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h
deleted file mode 100644
index a67826f5fe21..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/dma_defs.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __dma_defs_h
-#define __dma_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
- * last modfied: Mon Apr 11 16:06:51 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
- * id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope dma */
-
-/* Register rw_data, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data;
-#define REG_RD_ADDR_dma_rw_data 0
-#define REG_WR_ADDR_dma_rw_data 0
-
-/* Register rw_data_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_next;
-#define REG_RD_ADDR_dma_rw_data_next 4
-#define REG_WR_ADDR_dma_rw_data_next 4
-
-/* Register rw_data_buf, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_buf;
-#define REG_RD_ADDR_dma_rw_data_buf 8
-#define REG_WR_ADDR_dma_rw_data_buf 8
-
-/* Register rw_data_ctrl, scope dma, type rw */
-typedef struct {
- unsigned int eol : 1;
- unsigned int dummy1 : 2;
- unsigned int out_eop : 1;
- unsigned int intr : 1;
- unsigned int wait : 1;
- unsigned int dummy2 : 26;
-} reg_dma_rw_data_ctrl;
-#define REG_RD_ADDR_dma_rw_data_ctrl 12
-#define REG_WR_ADDR_dma_rw_data_ctrl 12
-
-/* Register rw_data_stat, scope dma, type rw */
-typedef struct {
- unsigned int dummy1 : 3;
- unsigned int in_eop : 1;
- unsigned int dummy2 : 28;
-} reg_dma_rw_data_stat;
-#define REG_RD_ADDR_dma_rw_data_stat 16
-#define REG_WR_ADDR_dma_rw_data_stat 16
-
-/* Register rw_data_md, scope dma, type rw */
-typedef struct {
- unsigned int md : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_data_md;
-#define REG_RD_ADDR_dma_rw_data_md 20
-#define REG_WR_ADDR_dma_rw_data_md 20
-
-/* Register rw_data_md_s, scope dma, type rw */
-typedef struct {
- unsigned int md_s : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_data_md_s;
-#define REG_RD_ADDR_dma_rw_data_md_s 24
-#define REG_WR_ADDR_dma_rw_data_md_s 24
-
-/* Register rw_data_after, scope dma, type rw */
-typedef unsigned int reg_dma_rw_data_after;
-#define REG_RD_ADDR_dma_rw_data_after 28
-#define REG_WR_ADDR_dma_rw_data_after 28
-
-/* Register rw_ctxt, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt;
-#define REG_RD_ADDR_dma_rw_ctxt 32
-#define REG_WR_ADDR_dma_rw_ctxt 32
-
-/* Register rw_ctxt_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_next;
-#define REG_RD_ADDR_dma_rw_ctxt_next 36
-#define REG_WR_ADDR_dma_rw_ctxt_next 36
-
-/* Register rw_ctxt_ctrl, scope dma, type rw */
-typedef struct {
- unsigned int eol : 1;
- unsigned int dummy1 : 3;
- unsigned int intr : 1;
- unsigned int dummy2 : 1;
- unsigned int store_mode : 1;
- unsigned int en : 1;
- unsigned int dummy3 : 24;
-} reg_dma_rw_ctxt_ctrl;
-#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
-#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
-
-/* Register rw_ctxt_stat, scope dma, type rw */
-typedef struct {
- unsigned int dummy1 : 7;
- unsigned int dis : 1;
- unsigned int dummy2 : 24;
-} reg_dma_rw_ctxt_stat;
-#define REG_RD_ADDR_dma_rw_ctxt_stat 44
-#define REG_WR_ADDR_dma_rw_ctxt_stat 44
-
-/* Register rw_ctxt_md0, scope dma, type rw */
-typedef struct {
- unsigned int md0 : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_ctxt_md0;
-#define REG_RD_ADDR_dma_rw_ctxt_md0 48
-#define REG_WR_ADDR_dma_rw_ctxt_md0 48
-
-/* Register rw_ctxt_md0_s, scope dma, type rw */
-typedef struct {
- unsigned int md0_s : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_ctxt_md0_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
-#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
-
-/* Register rw_ctxt_md1, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md1;
-#define REG_RD_ADDR_dma_rw_ctxt_md1 56
-#define REG_WR_ADDR_dma_rw_ctxt_md1 56
-
-/* Register rw_ctxt_md1_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md1_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
-#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
-
-/* Register rw_ctxt_md2, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md2;
-#define REG_RD_ADDR_dma_rw_ctxt_md2 64
-#define REG_WR_ADDR_dma_rw_ctxt_md2 64
-
-/* Register rw_ctxt_md2_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md2_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
-#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
-
-/* Register rw_ctxt_md3, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md3;
-#define REG_RD_ADDR_dma_rw_ctxt_md3 72
-#define REG_WR_ADDR_dma_rw_ctxt_md3 72
-
-/* Register rw_ctxt_md3_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md3_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
-#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
-
-/* Register rw_ctxt_md4, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md4;
-#define REG_RD_ADDR_dma_rw_ctxt_md4 80
-#define REG_WR_ADDR_dma_rw_ctxt_md4 80
-
-/* Register rw_ctxt_md4_s, scope dma, type rw */
-typedef unsigned int reg_dma_rw_ctxt_md4_s;
-#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
-#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
-
-/* Register rw_saved_data, scope dma, type rw */
-typedef unsigned int reg_dma_rw_saved_data;
-#define REG_RD_ADDR_dma_rw_saved_data 88
-#define REG_WR_ADDR_dma_rw_saved_data 88
-
-/* Register rw_saved_data_buf, scope dma, type rw */
-typedef unsigned int reg_dma_rw_saved_data_buf;
-#define REG_RD_ADDR_dma_rw_saved_data_buf 92
-#define REG_WR_ADDR_dma_rw_saved_data_buf 92
-
-/* Register rw_group, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group;
-#define REG_RD_ADDR_dma_rw_group 96
-#define REG_WR_ADDR_dma_rw_group 96
-
-/* Register rw_group_next, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_next;
-#define REG_RD_ADDR_dma_rw_group_next 100
-#define REG_WR_ADDR_dma_rw_group_next 100
-
-/* Register rw_group_ctrl, scope dma, type rw */
-typedef struct {
- unsigned int eol : 1;
- unsigned int tol : 1;
- unsigned int bol : 1;
- unsigned int dummy1 : 1;
- unsigned int intr : 1;
- unsigned int dummy2 : 2;
- unsigned int en : 1;
- unsigned int dummy3 : 24;
-} reg_dma_rw_group_ctrl;
-#define REG_RD_ADDR_dma_rw_group_ctrl 104
-#define REG_WR_ADDR_dma_rw_group_ctrl 104
-
-/* Register rw_group_stat, scope dma, type rw */
-typedef struct {
- unsigned int dummy1 : 7;
- unsigned int dis : 1;
- unsigned int dummy2 : 24;
-} reg_dma_rw_group_stat;
-#define REG_RD_ADDR_dma_rw_group_stat 108
-#define REG_WR_ADDR_dma_rw_group_stat 108
-
-/* Register rw_group_md, scope dma, type rw */
-typedef struct {
- unsigned int md : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_group_md;
-#define REG_RD_ADDR_dma_rw_group_md 112
-#define REG_WR_ADDR_dma_rw_group_md 112
-
-/* Register rw_group_md_s, scope dma, type rw */
-typedef struct {
- unsigned int md_s : 16;
- unsigned int dummy1 : 16;
-} reg_dma_rw_group_md_s;
-#define REG_RD_ADDR_dma_rw_group_md_s 116
-#define REG_WR_ADDR_dma_rw_group_md_s 116
-
-/* Register rw_group_up, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_up;
-#define REG_RD_ADDR_dma_rw_group_up 120
-#define REG_WR_ADDR_dma_rw_group_up 120
-
-/* Register rw_group_down, scope dma, type rw */
-typedef unsigned int reg_dma_rw_group_down;
-#define REG_RD_ADDR_dma_rw_group_down 124
-#define REG_WR_ADDR_dma_rw_group_down 124
-
-/* Register rw_cmd, scope dma, type rw */
-typedef struct {
- unsigned int cont_data : 1;
- unsigned int dummy1 : 31;
-} reg_dma_rw_cmd;
-#define REG_RD_ADDR_dma_rw_cmd 128
-#define REG_WR_ADDR_dma_rw_cmd 128
-
-/* Register rw_cfg, scope dma, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int stop : 1;
- unsigned int dummy1 : 30;
-} reg_dma_rw_cfg;
-#define REG_RD_ADDR_dma_rw_cfg 132
-#define REG_WR_ADDR_dma_rw_cfg 132
-
-/* Register rw_stat, scope dma, type rw */
-typedef struct {
- unsigned int mode : 5;
- unsigned int list_state : 3;
- unsigned int stream_cmd_src : 8;
- unsigned int dummy1 : 8;
- unsigned int buf : 8;
-} reg_dma_rw_stat;
-#define REG_RD_ADDR_dma_rw_stat 136
-#define REG_WR_ADDR_dma_rw_stat 136
-
-/* Register rw_intr_mask, scope dma, type rw */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_rw_intr_mask;
-#define REG_RD_ADDR_dma_rw_intr_mask 140
-#define REG_WR_ADDR_dma_rw_intr_mask 140
-
-/* Register rw_ack_intr, scope dma, type rw */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_rw_ack_intr;
-#define REG_RD_ADDR_dma_rw_ack_intr 144
-#define REG_WR_ADDR_dma_rw_ack_intr 144
-
-/* Register r_intr, scope dma, type r */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_r_intr;
-#define REG_RD_ADDR_dma_r_intr 148
-
-/* Register r_masked_intr, scope dma, type r */
-typedef struct {
- unsigned int group : 1;
- unsigned int ctxt : 1;
- unsigned int data : 1;
- unsigned int in_eop : 1;
- unsigned int stream_cmd : 1;
- unsigned int dummy1 : 27;
-} reg_dma_r_masked_intr;
-#define REG_RD_ADDR_dma_r_masked_intr 152
-
-/* Register rw_stream_cmd, scope dma, type rw */
-typedef struct {
- unsigned int cmd : 10;
- unsigned int dummy1 : 6;
- unsigned int n : 8;
- unsigned int dummy2 : 7;
- unsigned int busy : 1;
-} reg_dma_rw_stream_cmd;
-#define REG_RD_ADDR_dma_rw_stream_cmd 156
-#define REG_WR_ADDR_dma_rw_stream_cmd 156
-
-
-/* Constants */
-enum {
- regk_dma_ack_pkt = 0x00000100,
- regk_dma_anytime = 0x00000001,
- regk_dma_array = 0x00000008,
- regk_dma_burst = 0x00000020,
- regk_dma_client = 0x00000002,
- regk_dma_copy_next = 0x00000010,
- regk_dma_copy_up = 0x00000020,
- regk_dma_data_at_eol = 0x00000001,
- regk_dma_dis_c = 0x00000010,
- regk_dma_dis_g = 0x00000020,
- regk_dma_idle = 0x00000001,
- regk_dma_intern = 0x00000004,
- regk_dma_load_c = 0x00000200,
- regk_dma_load_c_n = 0x00000280,
- regk_dma_load_c_next = 0x00000240,
- regk_dma_load_d = 0x00000140,
- regk_dma_load_g = 0x00000300,
- regk_dma_load_g_down = 0x000003c0,
- regk_dma_load_g_next = 0x00000340,
- regk_dma_load_g_up = 0x00000380,
- regk_dma_next_en = 0x00000010,
- regk_dma_next_pkt = 0x00000010,
- regk_dma_no = 0x00000000,
- regk_dma_only_at_wait = 0x00000000,
- regk_dma_restore = 0x00000020,
- regk_dma_rst = 0x00000001,
- regk_dma_running = 0x00000004,
- regk_dma_rw_cfg_default = 0x00000000,
- regk_dma_rw_cmd_default = 0x00000000,
- regk_dma_rw_intr_mask_default = 0x00000000,
- regk_dma_rw_stat_default = 0x00000101,
- regk_dma_rw_stream_cmd_default = 0x00000000,
- regk_dma_save_down = 0x00000020,
- regk_dma_save_up = 0x00000020,
- regk_dma_set_reg = 0x00000050,
- regk_dma_set_w_size1 = 0x00000190,
- regk_dma_set_w_size2 = 0x000001a0,
- regk_dma_set_w_size4 = 0x000001c0,
- regk_dma_stopped = 0x00000002,
- regk_dma_store_c = 0x00000002,
- regk_dma_store_descr = 0x00000000,
- regk_dma_store_g = 0x00000004,
- regk_dma_store_md = 0x00000001,
- regk_dma_sw = 0x00000008,
- regk_dma_update_down = 0x00000020,
- regk_dma_yes = 0x00000001
-};
-#endif /* __dma_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h b/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h
deleted file mode 100644
index d8021b44e5e6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/eth_defs.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __eth_defs_h
-#define __eth_defs_h
-
-/*
- * This file is autogenerated from
- * file: eth.r
- * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
- * last modfied: Mon Jan 9 06:06:41 2006
- *
- * by /n/asic/design/tools/rdesc/rdes2c eth.r
- * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope eth */
-
-/* Register rw_ma0_lo, scope eth, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_eth_rw_ma0_lo;
-#define REG_RD_ADDR_eth_rw_ma0_lo 0
-#define REG_WR_ADDR_eth_rw_ma0_lo 0
-
-/* Register rw_ma0_hi, scope eth, type rw */
-typedef struct {
- unsigned int addr : 16;
- unsigned int dummy1 : 16;
-} reg_eth_rw_ma0_hi;
-#define REG_RD_ADDR_eth_rw_ma0_hi 4
-#define REG_WR_ADDR_eth_rw_ma0_hi 4
-
-/* Register rw_ma1_lo, scope eth, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_eth_rw_ma1_lo;
-#define REG_RD_ADDR_eth_rw_ma1_lo 8
-#define REG_WR_ADDR_eth_rw_ma1_lo 8
-
-/* Register rw_ma1_hi, scope eth, type rw */
-typedef struct {
- unsigned int addr : 16;
- unsigned int dummy1 : 16;
-} reg_eth_rw_ma1_hi;
-#define REG_RD_ADDR_eth_rw_ma1_hi 12
-#define REG_WR_ADDR_eth_rw_ma1_hi 12
-
-/* Register rw_ga_lo, scope eth, type rw */
-typedef struct {
- unsigned int tbl : 32;
-} reg_eth_rw_ga_lo;
-#define REG_RD_ADDR_eth_rw_ga_lo 16
-#define REG_WR_ADDR_eth_rw_ga_lo 16
-
-/* Register rw_ga_hi, scope eth, type rw */
-typedef struct {
- unsigned int tbl : 32;
-} reg_eth_rw_ga_hi;
-#define REG_RD_ADDR_eth_rw_ga_hi 20
-#define REG_WR_ADDR_eth_rw_ga_hi 20
-
-/* Register rw_gen_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int phy : 2;
- unsigned int protocol : 1;
- unsigned int loopback : 1;
- unsigned int flow_ctrl : 1;
- unsigned int gtxclk_out : 1;
- unsigned int phyrst_n : 1;
- unsigned int dummy1 : 24;
-} reg_eth_rw_gen_ctrl;
-#define REG_RD_ADDR_eth_rw_gen_ctrl 24
-#define REG_WR_ADDR_eth_rw_gen_ctrl 24
-
-/* Register rw_rec_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int ma0 : 1;
- unsigned int ma1 : 1;
- unsigned int individual : 1;
- unsigned int broadcast : 1;
- unsigned int undersize : 1;
- unsigned int oversize : 1;
- unsigned int bad_crc : 1;
- unsigned int duplex : 1;
- unsigned int max_size : 16;
- unsigned int dummy1 : 8;
-} reg_eth_rw_rec_ctrl;
-#define REG_RD_ADDR_eth_rw_rec_ctrl 28
-#define REG_WR_ADDR_eth_rw_rec_ctrl 28
-
-/* Register rw_tr_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int crc : 1;
- unsigned int pad : 1;
- unsigned int retry : 1;
- unsigned int ignore_col : 1;
- unsigned int cancel : 1;
- unsigned int hsh_delay : 1;
- unsigned int ignore_crs : 1;
- unsigned int carrier_ext : 1;
- unsigned int dummy1 : 24;
-} reg_eth_rw_tr_ctrl;
-#define REG_RD_ADDR_eth_rw_tr_ctrl 32
-#define REG_WR_ADDR_eth_rw_tr_ctrl 32
-
-/* Register rw_clr_err, scope eth, type rw */
-typedef struct {
- unsigned int clr : 1;
- unsigned int dummy1 : 31;
-} reg_eth_rw_clr_err;
-#define REG_RD_ADDR_eth_rw_clr_err 36
-#define REG_WR_ADDR_eth_rw_clr_err 36
-
-/* Register rw_mgm_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int mdio : 1;
- unsigned int mdoe : 1;
- unsigned int mdc : 1;
- unsigned int dummy1 : 29;
-} reg_eth_rw_mgm_ctrl;
-#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
-#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
-
-/* Register r_stat, scope eth, type r */
-typedef struct {
- unsigned int mdio : 1;
- unsigned int exc_col : 1;
- unsigned int urun : 1;
- unsigned int clk_125 : 1;
- unsigned int dummy1 : 28;
-} reg_eth_r_stat;
-#define REG_RD_ADDR_eth_r_stat 44
-
-/* Register rs_rec_cnt, scope eth, type rs */
-typedef struct {
- unsigned int crc_err : 8;
- unsigned int align_err : 8;
- unsigned int oversize : 8;
- unsigned int congestion : 8;
-} reg_eth_rs_rec_cnt;
-#define REG_RD_ADDR_eth_rs_rec_cnt 48
-
-/* Register r_rec_cnt, scope eth, type r */
-typedef struct {
- unsigned int crc_err : 8;
- unsigned int align_err : 8;
- unsigned int oversize : 8;
- unsigned int congestion : 8;
-} reg_eth_r_rec_cnt;
-#define REG_RD_ADDR_eth_r_rec_cnt 52
-
-/* Register rs_tr_cnt, scope eth, type rs */
-typedef struct {
- unsigned int single_col : 8;
- unsigned int mult_col : 8;
- unsigned int late_col : 8;
- unsigned int deferred : 8;
-} reg_eth_rs_tr_cnt;
-#define REG_RD_ADDR_eth_rs_tr_cnt 56
-
-/* Register r_tr_cnt, scope eth, type r */
-typedef struct {
- unsigned int single_col : 8;
- unsigned int mult_col : 8;
- unsigned int late_col : 8;
- unsigned int deferred : 8;
-} reg_eth_r_tr_cnt;
-#define REG_RD_ADDR_eth_r_tr_cnt 60
-
-/* Register rs_phy_cnt, scope eth, type rs */
-typedef struct {
- unsigned int carrier_loss : 8;
- unsigned int sqe_err : 8;
- unsigned int dummy1 : 16;
-} reg_eth_rs_phy_cnt;
-#define REG_RD_ADDR_eth_rs_phy_cnt 64
-
-/* Register r_phy_cnt, scope eth, type r */
-typedef struct {
- unsigned int carrier_loss : 8;
- unsigned int sqe_err : 8;
- unsigned int dummy1 : 16;
-} reg_eth_r_phy_cnt;
-#define REG_RD_ADDR_eth_r_phy_cnt 68
-
-/* Register rw_test_ctrl, scope eth, type rw */
-typedef struct {
- unsigned int snmp_inc : 1;
- unsigned int snmp : 1;
- unsigned int backoff : 1;
- unsigned int dummy1 : 29;
-} reg_eth_rw_test_ctrl;
-#define REG_RD_ADDR_eth_rw_test_ctrl 72
-#define REG_WR_ADDR_eth_rw_test_ctrl 72
-
-/* Register rw_intr_mask, scope eth, type rw */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_rw_intr_mask;
-#define REG_RD_ADDR_eth_rw_intr_mask 76
-#define REG_WR_ADDR_eth_rw_intr_mask 76
-
-/* Register rw_ack_intr, scope eth, type rw */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_rw_ack_intr;
-#define REG_RD_ADDR_eth_rw_ack_intr 80
-#define REG_WR_ADDR_eth_rw_ack_intr 80
-
-/* Register r_intr, scope eth, type r */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_r_intr;
-#define REG_RD_ADDR_eth_r_intr 84
-
-/* Register r_masked_intr, scope eth, type r */
-typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int exc_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
-} reg_eth_r_masked_intr;
-#define REG_RD_ADDR_eth_r_masked_intr 88
-
-
-/* Constants */
-enum {
- regk_eth_discard = 0x00000000,
- regk_eth_ether = 0x00000000,
- regk_eth_full = 0x00000001,
- regk_eth_gmii = 0x00000003,
- regk_eth_gtxclk = 0x00000001,
- regk_eth_half = 0x00000000,
- regk_eth_hsh = 0x00000001,
- regk_eth_mii = 0x00000001,
- regk_eth_mii_arec = 0x00000002,
- regk_eth_mii_clk = 0x00000000,
- regk_eth_no = 0x00000000,
- regk_eth_phyrst = 0x00000000,
- regk_eth_rec = 0x00000001,
- regk_eth_rw_ga_hi_default = 0x00000000,
- regk_eth_rw_ga_lo_default = 0x00000000,
- regk_eth_rw_gen_ctrl_default = 0x00000000,
- regk_eth_rw_intr_mask_default = 0x00000000,
- regk_eth_rw_ma0_hi_default = 0x00000000,
- regk_eth_rw_ma0_lo_default = 0x00000000,
- regk_eth_rw_ma1_hi_default = 0x00000000,
- regk_eth_rw_ma1_lo_default = 0x00000000,
- regk_eth_rw_mgm_ctrl_default = 0x00000000,
- regk_eth_rw_test_ctrl_default = 0x00000000,
- regk_eth_size1518 = 0x000005ee,
- regk_eth_size1522 = 0x000005f2,
- regk_eth_yes = 0x00000001
-};
-#endif /* __eth_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h b/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h
deleted file mode 100644
index 5937ed7a5228..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/extmem_defs.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __extmem_defs_h
-#define __extmem_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ext_mem/mod/extmem_regs.r
- * id: extmem_regs.r,v 1.1 2004/02/16 13:29:30 np Exp
- * last modfied: Tue Mar 30 22:26:21 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile extmem_defs.h ../../inst/ext_mem/mod/extmem_regs.r
- * id: $Id: extmem_defs.h,v 1.5 2004/06/04 07:15:33 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope extmem */
-
-/* Register rw_cse0_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_cse0_cfg;
-#define REG_RD_ADDR_extmem_rw_cse0_cfg 0
-#define REG_WR_ADDR_extmem_rw_cse0_cfg 0
-
-/* Register rw_cse1_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_cse1_cfg;
-#define REG_RD_ADDR_extmem_rw_cse1_cfg 4
-#define REG_WR_ADDR_extmem_rw_cse1_cfg 4
-
-/* Register rw_csr0_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csr0_cfg;
-#define REG_RD_ADDR_extmem_rw_csr0_cfg 8
-#define REG_WR_ADDR_extmem_rw_csr0_cfg 8
-
-/* Register rw_csr1_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csr1_cfg;
-#define REG_RD_ADDR_extmem_rw_csr1_cfg 12
-#define REG_WR_ADDR_extmem_rw_csr1_cfg 12
-
-/* Register rw_csp0_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp0_cfg;
-#define REG_RD_ADDR_extmem_rw_csp0_cfg 16
-#define REG_WR_ADDR_extmem_rw_csp0_cfg 16
-
-/* Register rw_csp1_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp1_cfg;
-#define REG_RD_ADDR_extmem_rw_csp1_cfg 20
-#define REG_WR_ADDR_extmem_rw_csp1_cfg 20
-
-/* Register rw_csp2_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp2_cfg;
-#define REG_RD_ADDR_extmem_rw_csp2_cfg 24
-#define REG_WR_ADDR_extmem_rw_csp2_cfg 24
-
-/* Register rw_csp3_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp3_cfg;
-#define REG_RD_ADDR_extmem_rw_csp3_cfg 28
-#define REG_WR_ADDR_extmem_rw_csp3_cfg 28
-
-/* Register rw_csp4_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp4_cfg;
-#define REG_RD_ADDR_extmem_rw_csp4_cfg 32
-#define REG_WR_ADDR_extmem_rw_csp4_cfg 32
-
-/* Register rw_csp5_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp5_cfg;
-#define REG_RD_ADDR_extmem_rw_csp5_cfg 36
-#define REG_WR_ADDR_extmem_rw_csp5_cfg 36
-
-/* Register rw_csp6_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_csp6_cfg;
-#define REG_RD_ADDR_extmem_rw_csp6_cfg 40
-#define REG_WR_ADDR_extmem_rw_csp6_cfg 40
-
-/* Register rw_css_cfg, scope extmem, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int mode : 1;
- unsigned int erc_en : 1;
- unsigned int dummy1 : 6;
- unsigned int size : 3;
- unsigned int log : 1;
- unsigned int en : 1;
-} reg_extmem_rw_css_cfg;
-#define REG_RD_ADDR_extmem_rw_css_cfg 44
-#define REG_WR_ADDR_extmem_rw_css_cfg 44
-
-/* Register rw_status_handle, scope extmem, type rw */
-typedef struct {
- unsigned int h : 32;
-} reg_extmem_rw_status_handle;
-#define REG_RD_ADDR_extmem_rw_status_handle 48
-#define REG_WR_ADDR_extmem_rw_status_handle 48
-
-/* Register rw_wait_pin, scope extmem, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 15;
- unsigned int start : 1;
-} reg_extmem_rw_wait_pin;
-#define REG_RD_ADDR_extmem_rw_wait_pin 52
-#define REG_WR_ADDR_extmem_rw_wait_pin 52
-
-/* Register rw_gated_csp, scope extmem, type rw */
-typedef struct {
- unsigned int dummy1 : 31;
- unsigned int en : 1;
-} reg_extmem_rw_gated_csp;
-#define REG_RD_ADDR_extmem_rw_gated_csp 56
-#define REG_WR_ADDR_extmem_rw_gated_csp 56
-
-
-/* Constants */
-enum {
- regk_extmem_b16 = 0x00000001,
- regk_extmem_b32 = 0x00000000,
- regk_extmem_bwe = 0x00000000,
- regk_extmem_cwe = 0x00000001,
- regk_extmem_no = 0x00000000,
- regk_extmem_rw_cse0_cfg_default = 0x000006cf,
- regk_extmem_rw_cse1_cfg_default = 0x000006cf,
- regk_extmem_rw_csp0_cfg_default = 0x000006cf,
- regk_extmem_rw_csp1_cfg_default = 0x000006cf,
- regk_extmem_rw_csp2_cfg_default = 0x000006cf,
- regk_extmem_rw_csp3_cfg_default = 0x000006cf,
- regk_extmem_rw_csp4_cfg_default = 0x000006cf,
- regk_extmem_rw_csp5_cfg_default = 0x000006cf,
- regk_extmem_rw_csp6_cfg_default = 0x000006cf,
- regk_extmem_rw_csr0_cfg_default = 0x000006cf,
- regk_extmem_rw_csr1_cfg_default = 0x000006cf,
- regk_extmem_rw_css_cfg_default = 0x000006cf,
- regk_extmem_s128KB = 0x00000000,
- regk_extmem_s16MB = 0x00000005,
- regk_extmem_s1MB = 0x00000001,
- regk_extmem_s2MB = 0x00000002,
- regk_extmem_s32MB = 0x00000006,
- regk_extmem_s4MB = 0x00000003,
- regk_extmem_s64MB = 0x00000007,
- regk_extmem_s8MB = 0x00000004,
- regk_extmem_yes = 0x00000001
-};
-#endif /* __extmem_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile b/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile
deleted file mode 100644
index 1b9467ae65c1..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/Makefile
+++ /dev/null
@@ -1,147 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# $Id: Makefile,v 1.3 2004/01/07 20:34:55 johana Exp $
-# Makefile to generate or copy the latest register definitions
-# and related datastructures and helpermacros.
-# The official place for these files is probably at:
-RELEASE ?= r1_alfa5
-IOPOFFICIAL_INCDIR = /n/asic/projects/guinness/releases/$(RELEASE)/design/top/sw/include/
-
-IOPROCDIR = /n/asic/design/io/io_proc/rtl
-
-IOPROCINCL_FILES =
-IOPROCINCL_FILES2=
-IOPROCINCL_FILES += iop_crc_par_defs.h
-IOPROCINCL_FILES += iop_dmc_in_defs.h
-IOPROCINCL_FILES += iop_dmc_out_defs.h
-IOPROCINCL_FILES += iop_fifo_in_defs.h
-IOPROCINCL_FILES += iop_fifo_in_xtra_defs.h
-IOPROCINCL_FILES += iop_fifo_out_defs.h
-IOPROCINCL_FILES += iop_fifo_out_xtra_defs.h
-IOPROCINCL_FILES += iop_mpu_defs.h
-IOPROCINCL_FILES2+= iop_mpu_macros.h
-IOPROCINCL_FILES2+= iop_reg_space.h
-IOPROCINCL_FILES += iop_sap_in_defs.h
-IOPROCINCL_FILES += iop_sap_out_defs.h
-IOPROCINCL_FILES += iop_scrc_in_defs.h
-IOPROCINCL_FILES += iop_scrc_out_defs.h
-IOPROCINCL_FILES += iop_spu_defs.h
-# in guiness/
-IOPROCINCL_FILES += iop_sw_cfg_defs.h
-IOPROCINCL_FILES += iop_sw_cpu_defs.h
-IOPROCINCL_FILES += iop_sw_mpu_defs.h
-IOPROCINCL_FILES += iop_sw_spu_defs.h
-#
-IOPROCINCL_FILES += iop_timer_grp_defs.h
-IOPROCINCL_FILES += iop_trigger_grp_defs.h
-# in guiness/
-IOPROCINCL_FILES += iop_version_defs.h
-
-IOPROCASMINCL_FILES = $(patsubst %_defs.h,%_defs_asm.h,$(IOPROCINCL_FILES))
-IOPROCASMINCL_FILES+= iop_reg_space_asm.h
-
-
-IOPROCREGDESC =
-IOPROCREGDESC += $(IOPROCDIR)/iop_crc_par.r
-#IOPROCREGDESC += $(IOPROCDIR)/iop_crc_ser.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_dmc_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_in_xtra.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_fifo_out_xtra.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_mpu.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_sap_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_sap_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_in.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_scrc_out.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_spu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cfg.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_cpu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_mpu.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_sw_spu.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_timer_grp.r
-IOPROCREGDESC += $(IOPROCDIR)/iop_trigger_grp.r
-IOPROCREGDESC += $(IOPROCDIR)/guinness/iop_version.r
-
-
-RDES2C = /n/asic/bin/rdes2c
-RDES2C = /n/asic/design/tools/rdesc/rdes2c
-RDES2INTR = /n/asic/design/tools/rdesc/rdes2intr
-RDES2TXT = /n/asic/design/tools/rdesc/rdes2txt
-
-## all - Just print help - you probably want to do 'make gen'
-all: help
-
-## help - This help
-help:
- @grep '^## ' Makefile
-
-## gen - Generate include files
-gen: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
- echo "INCL: $(IOPROCINCL_FILES)"
- echo "INCL2: $(IOPROCINCL_FILES2)"
- echo "ASMINCL: $(IOPROCASMINCL_FILES)"
-
-# From the official location...
-iop_reg_space.h: $(IOPOFFICIAL_INCDIR)/iop_reg_space.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-iop_mpu_macros.h: $(IOPOFFICIAL_INCDIR)/iop_mpu_macros.h
- cat $< | sed -e 's/\$$Id\:/id\:/g' >$@
-
-## copy - Copy files from official location
-copy:
- @echo "## Copying and fixing iop files ##"
- @for HFILE in $(IOPROCINCL_FILES); do \
- echo " $$HFILE"; \
- cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
- @for HFILE in $(IOPROCINCL_FILES2); do \
- echo " $$HFILE"; \
- cat $(IOPOFFICIAL_INCDIR)$$HFILE | sed -e 's/\$$Id\:/id\:/g' > $$HFILE; \
- done
- @echo "## Copying and fixing iop asm files ##"
- @for HFILE in $(IOPROCASMINCL_FILES); do \
- echo " $$HFILE"; \
- cat $(IOPOFFICIAL_INCDIR)asm/$$HFILE | sed -e 's/\$$Id\:/id\:/g' > asm/$$HFILE; \
- done
-
-# I/O processor files:
-## iop - Generate I/O processor include files
-iop: $(IOPROCINCL_FILES) $(IOPROCINCL_FILES2) $(IOPROCASMINCL_FILES)
-iop_sw_%_defs.h: $(IOPROCDIR)/guinness/iop_sw_%.r
- $(RDES2C) $<
-iop_version_defs.h: $(IOPROCDIR)/guinness/iop_version.r
- $(RDES2C) $<
-%_defs.h: $(IOPROCDIR)/%.r
- $(RDES2C) $<
-%_defs_asm.h: $(IOPROCDIR)/%.r
- $(RDES2C) -asm $<
-iop_version_defs_asm.h: $(IOPROCDIR)/guinness/iop_version.r
- $(RDES2C) -asm $<
-
-## doc - Generate .axw files from register description.
-doc: $(IOPROCREGDESC)
- for RDES in $^; do \
- $(RDES2TXT) $$RDES; \
- done
-
-.PHONY: axw
-## %.axw - Generate the specified .axw file (doesn't work for all files
-## due to inconsistent naming of .r files.
-%.axw: axw
- @for RDES in $(IOPROCREGDESC); do \
- if echo "$$RDES" | grep $* ; then \
- $(RDES2TXT) $$RDES; \
- fi \
- done
-
-.PHONY: clean
-## clean - Remove .h files and .axw files.
-clean:
- rm -rf $(IOPROCINCL_FILES) *.axw
-
-.PHONY: cleandoc
-## cleandoc - Remove .axw files.
-cleandoc:
- rm -rf *.axw
-
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h
deleted file mode 100644
index 10443d789a66..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_crc_par_defs_asm_h
-#define __iop_crc_par_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_crc_par.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
- * id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_cfg___mode___lsb 0
-#define reg_iop_crc_par_rw_cfg___mode___width 1
-#define reg_iop_crc_par_rw_cfg___mode___bit 0
-#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
-#define reg_iop_crc_par_rw_cfg___crc_out___width 1
-#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
-#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
-#define reg_iop_crc_par_rw_cfg___rev_out___width 1
-#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
-#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
-#define reg_iop_crc_par_rw_cfg___inv_out___width 1
-#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
-#define reg_iop_crc_par_rw_cfg___trig___lsb 4
-#define reg_iop_crc_par_rw_cfg___trig___width 2
-#define reg_iop_crc_par_rw_cfg___poly___lsb 6
-#define reg_iop_crc_par_rw_cfg___poly___width 3
-#define reg_iop_crc_par_rw_cfg_offset 0
-
-/* Register rw_init_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_init_crc_offset 4
-
-/* Register rw_correct_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_correct_crc_offset 8
-
-/* Register rw_ctrl, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_ctrl___en___lsb 0
-#define reg_iop_crc_par_rw_ctrl___en___width 1
-#define reg_iop_crc_par_rw_ctrl___en___bit 0
-#define reg_iop_crc_par_rw_ctrl_offset 12
-
-/* Register rw_set_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
-#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
-#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
-#define reg_iop_crc_par_rw_set_last_offset 16
-
-/* Register rw_wr1byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_offset 20
-
-/* Register rw_wr2byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_offset 24
-
-/* Register rw_wr3byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_offset 28
-
-/* Register rw_wr4byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_offset 32
-
-/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_last_offset 36
-
-/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_last_offset 40
-
-/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_last_offset 44
-
-/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_last_offset 48
-
-/* Register r_stat, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_stat___err___lsb 0
-#define reg_iop_crc_par_r_stat___err___width 1
-#define reg_iop_crc_par_r_stat___err___bit 0
-#define reg_iop_crc_par_r_stat___busy___lsb 1
-#define reg_iop_crc_par_r_stat___busy___width 1
-#define reg_iop_crc_par_r_stat___busy___bit 1
-#define reg_iop_crc_par_r_stat_offset 52
-
-/* Register r_sh_reg, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_sh_reg_offset 56
-
-/* Register r_crc, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_crc_offset 60
-
-/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
-#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
-
-
-/* Constants */
-#define regk_iop_crc_par_calc 0x00000001
-#define regk_iop_crc_par_ccitt 0x00000002
-#define regk_iop_crc_par_check 0x00000000
-#define regk_iop_crc_par_crc16 0x00000001
-#define regk_iop_crc_par_crc32 0x00000000
-#define regk_iop_crc_par_crc5 0x00000003
-#define regk_iop_crc_par_crc5_11 0x00000004
-#define regk_iop_crc_par_dif_in 0x00000002
-#define regk_iop_crc_par_hi 0x00000000
-#define regk_iop_crc_par_neg 0x00000002
-#define regk_iop_crc_par_no 0x00000000
-#define regk_iop_crc_par_pos 0x00000001
-#define regk_iop_crc_par_pos_neg 0x00000003
-#define regk_iop_crc_par_rw_cfg_default 0x00000000
-#define regk_iop_crc_par_rw_ctrl_default 0x00000000
-#define regk_iop_crc_par_yes 0x00000001
-#endif /* __iop_crc_par_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h
deleted file mode 100644
index fdee9bbe1fd4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_in_defs_asm_h
-#define __iop_dmc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
-#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
-#define reg_iop_dmc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
-#define reg_iop_dmc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_in_r_stat___dif_en___width 1
-#define reg_iop_dmc_in_r_stat___dif_en___bit 0
-#define reg_iop_dmc_in_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_in_rw_stream_cmd_offset 12
-
-/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
-
-/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
-
-/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
-#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
-#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
-#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
-
-/* Register r_stream_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
-#define reg_iop_dmc_in_r_stream_stat___sth___width 7
-#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
-#define reg_iop_dmc_in_r_stream_stat___full___width 1
-#define reg_iop_dmc_in_r_stream_stat___full___bit 16
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
-#define reg_iop_dmc_in_r_stream_stat_offset 28
-
-/* Register r_data_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_data_descr___stat___width 8
-#define reg_iop_dmc_in_r_data_descr___md___lsb 16
-#define reg_iop_dmc_in_r_data_descr___md___width 16
-#define reg_iop_dmc_in_r_data_descr_offset 32
-
-/* Register r_ctxt_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_r_ctxt_descr_offset 36
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
-
-/* Register r_group_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_group_descr___stat___width 8
-#define reg_iop_dmc_in_r_group_descr___md___lsb 16
-#define reg_iop_dmc_in_r_group_descr___md___width 16
-#define reg_iop_dmc_in_r_group_descr_offset 56
-
-/* Register rw_data_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_data_descr___md___width 16
-#define reg_iop_dmc_in_rw_data_descr_offset 60
-
-/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
-
-/* Register rw_group_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_group_descr___md___width 16
-#define reg_iop_dmc_in_rw_group_descr_offset 84
-
-/* Register rw_intr_mask, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
-#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
-#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
-#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
-#define reg_iop_dmc_in_rw_intr_mask___full___width 1
-#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
-#define reg_iop_dmc_in_rw_intr_mask_offset 88
-
-/* Register rw_ack_intr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
-#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
-#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
-#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
-#define reg_iop_dmc_in_rw_ack_intr___full___width 1
-#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
-#define reg_iop_dmc_in_rw_ack_intr_offset 92
-
-/* Register r_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_intr___data_md___width 1
-#define reg_iop_dmc_in_r_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_intr___group_md___width 1
-#define reg_iop_dmc_in_r_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_intr___sth___width 1
-#define reg_iop_dmc_in_r_intr___sth___bit 4
-#define reg_iop_dmc_in_r_intr___full___lsb 5
-#define reg_iop_dmc_in_r_intr___full___width 1
-#define reg_iop_dmc_in_r_intr___full___bit 5
-#define reg_iop_dmc_in_r_intr_offset 96
-
-/* Register r_masked_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_masked_intr___sth___width 1
-#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
-#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
-#define reg_iop_dmc_in_r_masked_intr___full___width 1
-#define reg_iop_dmc_in_r_masked_intr___full___bit 5
-#define reg_iop_dmc_in_r_masked_intr_offset 100
-
-
-/* Constants */
-#define regk_iop_dmc_in_ack_pkt 0x00000100
-#define regk_iop_dmc_in_array 0x00000008
-#define regk_iop_dmc_in_burst 0x00000020
-#define regk_iop_dmc_in_copy_next 0x00000010
-#define regk_iop_dmc_in_copy_up 0x00000020
-#define regk_iop_dmc_in_dis_c 0x00000010
-#define regk_iop_dmc_in_dis_g 0x00000020
-#define regk_iop_dmc_in_lim1 0x00000000
-#define regk_iop_dmc_in_lim16 0x00000004
-#define regk_iop_dmc_in_lim2 0x00000001
-#define regk_iop_dmc_in_lim32 0x00000005
-#define regk_iop_dmc_in_lim4 0x00000002
-#define regk_iop_dmc_in_lim64 0x00000006
-#define regk_iop_dmc_in_lim8 0x00000003
-#define regk_iop_dmc_in_load_c 0x00000200
-#define regk_iop_dmc_in_load_c_n 0x00000280
-#define regk_iop_dmc_in_load_c_next 0x00000240
-#define regk_iop_dmc_in_load_d 0x00000140
-#define regk_iop_dmc_in_load_g 0x00000300
-#define regk_iop_dmc_in_load_g_down 0x000003c0
-#define regk_iop_dmc_in_load_g_next 0x00000340
-#define regk_iop_dmc_in_load_g_up 0x00000380
-#define regk_iop_dmc_in_next_en 0x00000010
-#define regk_iop_dmc_in_next_pkt 0x00000010
-#define regk_iop_dmc_in_no 0x00000000
-#define regk_iop_dmc_in_restore 0x00000020
-#define regk_iop_dmc_in_rw_cfg_default 0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_default 0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md1_default 0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md2_default 0x00000000
-#define regk_iop_dmc_in_rw_data_descr_default 0x00000000
-#define regk_iop_dmc_in_rw_group_descr_default 0x00000000
-#define regk_iop_dmc_in_rw_intr_mask_default 0x00000000
-#define regk_iop_dmc_in_rw_stream_ctrl_default 0x00000000
-#define regk_iop_dmc_in_save_down 0x00000020
-#define regk_iop_dmc_in_save_up 0x00000020
-#define regk_iop_dmc_in_set_reg 0x00000050
-#define regk_iop_dmc_in_set_w_size1 0x00000190
-#define regk_iop_dmc_in_set_w_size2 0x000001a0
-#define regk_iop_dmc_in_set_w_size4 0x000001c0
-#define regk_iop_dmc_in_store_c 0x00000002
-#define regk_iop_dmc_in_store_descr 0x00000000
-#define regk_iop_dmc_in_store_g 0x00000004
-#define regk_iop_dmc_in_store_md 0x00000001
-#define regk_iop_dmc_in_update_down 0x00000020
-#define regk_iop_dmc_in_yes 0x00000001
-#endif /* __iop_dmc_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h
deleted file mode 100644
index a97b741bd36a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_out_defs_asm_h
-#define __iop_dmc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
-#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
-#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
-#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
-#define reg_iop_dmc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_out_r_stat___dif_en___width 1
-#define reg_iop_dmc_out_r_stat___dif_en___bit 0
-#define reg_iop_dmc_out_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_out_rw_stream_cmd_offset 12
-
-/* Register rs_stream_data, scope iop_dmc_out, type rs */
-#define reg_iop_dmc_out_rs_stream_data_offset 16
-
-/* Register r_stream_data, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_data_offset 20
-
-/* Register r_stream_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
-#define reg_iop_dmc_out_r_stream_stat___dth___width 7
-#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
-#define reg_iop_dmc_out_r_stream_stat___dv___width 1
-#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
-#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
-#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
-#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
-#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
-#define reg_iop_dmc_out_r_stream_stat___last___width 1
-#define reg_iop_dmc_out_r_stream_stat___last___bit 18
-#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
-#define reg_iop_dmc_out_r_stream_stat___size___width 3
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
-#define reg_iop_dmc_out_r_stream_stat_offset 24
-
-/* Register r_data_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_data_descr___stat___width 8
-#define reg_iop_dmc_out_r_data_descr___md___lsb 16
-#define reg_iop_dmc_out_r_data_descr___md___width 16
-#define reg_iop_dmc_out_r_data_descr_offset 28
-
-/* Register r_ctxt_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_r_ctxt_descr_offset 32
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
-
-/* Register r_group_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_group_descr___stat___width 8
-#define reg_iop_dmc_out_r_group_descr___md___lsb 16
-#define reg_iop_dmc_out_r_group_descr___md___width 16
-#define reg_iop_dmc_out_r_group_descr_offset 52
-
-/* Register rw_data_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_data_descr___md___width 16
-#define reg_iop_dmc_out_rw_data_descr_offset 56
-
-/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
-
-/* Register rw_group_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_group_descr___md___width 16
-#define reg_iop_dmc_out_rw_group_descr_offset 80
-
-/* Register rw_intr_mask, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
-#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
-#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
-#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
-#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
-#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
-#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_intr_mask_offset 84
-
-/* Register rw_ack_intr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
-#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
-#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
-#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
-#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
-#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
-#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_ack_intr_offset 88
-
-/* Register r_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_intr___data_md___width 1
-#define reg_iop_dmc_out_r_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_intr___group_md___width 1
-#define reg_iop_dmc_out_r_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_intr___dth___width 1
-#define reg_iop_dmc_out_r_intr___dth___bit 4
-#define reg_iop_dmc_out_r_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_intr___dv___width 1
-#define reg_iop_dmc_out_r_intr___dv___bit 5
-#define reg_iop_dmc_out_r_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_intr___last_data___width 1
-#define reg_iop_dmc_out_r_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_intr_offset 92
-
-/* Register r_masked_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_masked_intr___dth___width 1
-#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
-#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_masked_intr___dv___width 1
-#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
-#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
-#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_masked_intr_offset 96
-
-
-/* Constants */
-#define regk_iop_dmc_out_ack_pkt 0x00000100
-#define regk_iop_dmc_out_array 0x00000008
-#define regk_iop_dmc_out_burst 0x00000020
-#define regk_iop_dmc_out_copy_next 0x00000010
-#define regk_iop_dmc_out_copy_up 0x00000020
-#define regk_iop_dmc_out_dis_c 0x00000010
-#define regk_iop_dmc_out_dis_g 0x00000020
-#define regk_iop_dmc_out_lim1 0x00000000
-#define regk_iop_dmc_out_lim16 0x00000004
-#define regk_iop_dmc_out_lim2 0x00000001
-#define regk_iop_dmc_out_lim32 0x00000005
-#define regk_iop_dmc_out_lim4 0x00000002
-#define regk_iop_dmc_out_lim64 0x00000006
-#define regk_iop_dmc_out_lim8 0x00000003
-#define regk_iop_dmc_out_load_c 0x00000200
-#define regk_iop_dmc_out_load_c_n 0x00000280
-#define regk_iop_dmc_out_load_c_next 0x00000240
-#define regk_iop_dmc_out_load_d 0x00000140
-#define regk_iop_dmc_out_load_g 0x00000300
-#define regk_iop_dmc_out_load_g_down 0x000003c0
-#define regk_iop_dmc_out_load_g_next 0x00000340
-#define regk_iop_dmc_out_load_g_up 0x00000380
-#define regk_iop_dmc_out_next_en 0x00000010
-#define regk_iop_dmc_out_next_pkt 0x00000010
-#define regk_iop_dmc_out_no 0x00000000
-#define regk_iop_dmc_out_restore 0x00000020
-#define regk_iop_dmc_out_rw_cfg_default 0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_default 0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md1_default 0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md2_default 0x00000000
-#define regk_iop_dmc_out_rw_data_descr_default 0x00000000
-#define regk_iop_dmc_out_rw_group_descr_default 0x00000000
-#define regk_iop_dmc_out_rw_intr_mask_default 0x00000000
-#define regk_iop_dmc_out_save_down 0x00000020
-#define regk_iop_dmc_out_save_up 0x00000020
-#define regk_iop_dmc_out_set_reg 0x00000050
-#define regk_iop_dmc_out_set_w_size1 0x00000190
-#define regk_iop_dmc_out_set_w_size2 0x000001a0
-#define regk_iop_dmc_out_set_w_size4 0x000001c0
-#define regk_iop_dmc_out_store_c 0x00000002
-#define regk_iop_dmc_out_store_descr 0x00000000
-#define regk_iop_dmc_out_store_g 0x00000004
-#define regk_iop_dmc_out_store_md 0x00000001
-#define regk_iop_dmc_out_update_down 0x00000020
-#define regk_iop_dmc_out_yes 0x00000001
-#endif /* __iop_dmc_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h
deleted file mode 100644
index e2c0990246f2..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_defs_asm_h
-#define __iop_fifo_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:07 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
-#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_in_rw_cfg___trig___width 2
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_in_rw_cfg___mode___width 2
-#define reg_iop_fifo_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_r_stat___last___lsb 4
-#define reg_iop_fifo_in_r_stat___last___width 8
-#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_r_stat_offset 8
-
-/* Register rs_rd1byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd1byte___data___width 8
-#define reg_iop_fifo_in_rs_rd1byte_offset 12
-
-/* Register r_rd1byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd1byte___data___width 8
-#define reg_iop_fifo_in_r_rd1byte_offset 16
-
-/* Register rs_rd2byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd2byte___data___width 16
-#define reg_iop_fifo_in_rs_rd2byte_offset 20
-
-/* Register r_rd2byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd2byte___data___width 16
-#define reg_iop_fifo_in_r_rd2byte_offset 24
-
-/* Register rs_rd3byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd3byte___data___width 24
-#define reg_iop_fifo_in_rs_rd3byte_offset 28
-
-/* Register r_rd3byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd3byte___data___width 24
-#define reg_iop_fifo_in_r_rd3byte_offset 32
-
-/* Register rs_rd4byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd4byte___data___width 32
-#define reg_iop_fifo_in_rs_rd4byte_offset 36
-
-/* Register r_rd4byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd4byte___data___width 32
-#define reg_iop_fifo_in_r_rd4byte_offset 40
-
-/* Register rw_set_last, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_set_last_offset 44
-
-/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
-
-/* Register rw_intr_mask, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_rw_intr_mask_offset 52
-
-/* Register rw_ack_intr, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_rw_ack_intr_offset 56
-
-/* Register r_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_intr___urun___width 1
-#define reg_iop_fifo_in_r_intr___urun___bit 0
-#define reg_iop_fifo_in_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_intr___last_data___width 1
-#define reg_iop_fifo_in_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_intr___dav___width 1
-#define reg_iop_fifo_in_r_intr___dav___bit 2
-#define reg_iop_fifo_in_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_intr___avail___width 1
-#define reg_iop_fifo_in_r_intr___avail___bit 3
-#define reg_iop_fifo_in_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_intr___orun___width 1
-#define reg_iop_fifo_in_r_intr___orun___bit 4
-#define reg_iop_fifo_in_r_intr_offset 60
-
-/* Register r_masked_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_r_masked_intr_offset 64
-
-
-/* Constants */
-#define regk_iop_fifo_in_dif_in 0x00000002
-#define regk_iop_fifo_in_hi 0x00000000
-#define regk_iop_fifo_in_neg 0x00000002
-#define regk_iop_fifo_in_no 0x00000000
-#define regk_iop_fifo_in_order16 0x00000001
-#define regk_iop_fifo_in_order24 0x00000002
-#define regk_iop_fifo_in_order32 0x00000003
-#define regk_iop_fifo_in_order8 0x00000000
-#define regk_iop_fifo_in_pos 0x00000001
-#define regk_iop_fifo_in_pos_neg 0x00000003
-#define regk_iop_fifo_in_rw_cfg_default 0x00000024
-#define regk_iop_fifo_in_rw_ctrl_default 0x00000000
-#define regk_iop_fifo_in_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_in_rw_set_last_default 0x00000000
-#define regk_iop_fifo_in_rw_strb_dif_in_default 0x00000000
-#define regk_iop_fifo_in_size16 0x00000002
-#define regk_iop_fifo_in_size24 0x00000001
-#define regk_iop_fifo_in_size32 0x00000000
-#define regk_iop_fifo_in_size8 0x00000003
-#define regk_iop_fifo_in_yes 0x00000001
-#endif /* __iop_fifo_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
deleted file mode 100644
index 50837b989c90..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_extra_defs_asm_h
-#define __iop_fifo_in_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:08 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
-
-/* Register r_stat, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_in_extra_r_stat___last___width 8
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_extra_r_stat_offset 4
-
-/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
-
-/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
-
-/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
-
-/* Register r_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_intr_offset 20
-
-/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
-
-
-/* Constants */
-#define regk_iop_fifo_in_extra_fifo_in 0x00000002
-#define regk_iop_fifo_in_extra_no 0x00000000
-#define regk_iop_fifo_in_extra_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_in_extra_yes 0x00000001
-#endif /* __iop_fifo_in_extra_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h
deleted file mode 100644
index 9f06dddf33a0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_defs_asm_h
-#define __iop_fifo_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:09 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
-#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_out_rw_cfg___trig___width 2
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_out_rw_cfg___mode___width 2
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
-#define reg_iop_fifo_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_r_stat___last___lsb 4
-#define reg_iop_fifo_out_r_stat___last___width 8
-#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_r_stat_offset 8
-
-/* Register rw_wr1byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_offset 12
-
-/* Register rw_wr2byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_offset 16
-
-/* Register rw_wr3byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_offset 20
-
-/* Register rw_wr4byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_offset 24
-
-/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
-
-/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
-
-/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
-
-/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
-
-/* Register rw_set_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_set_last_offset 44
-
-/* Register rs_rd_data, scope iop_fifo_out, type rs */
-#define reg_iop_fifo_out_rs_rd_data_offset 48
-
-/* Register r_rd_data, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_rd_data_offset 52
-
-/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
-
-/* Register rw_intr_mask, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_rw_intr_mask_offset 60
-
-/* Register rw_ack_intr, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_rw_ack_intr_offset 64
-
-/* Register r_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_intr___urun___width 1
-#define reg_iop_fifo_out_r_intr___urun___bit 0
-#define reg_iop_fifo_out_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_intr___last_data___width 1
-#define reg_iop_fifo_out_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_intr___dav___width 1
-#define reg_iop_fifo_out_r_intr___dav___bit 2
-#define reg_iop_fifo_out_r_intr___free___lsb 3
-#define reg_iop_fifo_out_r_intr___free___width 1
-#define reg_iop_fifo_out_r_intr___free___bit 3
-#define reg_iop_fifo_out_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_intr___orun___width 1
-#define reg_iop_fifo_out_r_intr___orun___bit 4
-#define reg_iop_fifo_out_r_intr_offset 68
-
-/* Register r_masked_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_r_masked_intr_offset 72
-
-
-/* Constants */
-#define regk_iop_fifo_out_hi 0x00000000
-#define regk_iop_fifo_out_neg 0x00000002
-#define regk_iop_fifo_out_no 0x00000000
-#define regk_iop_fifo_out_order16 0x00000001
-#define regk_iop_fifo_out_order24 0x00000002
-#define regk_iop_fifo_out_order32 0x00000003
-#define regk_iop_fifo_out_order8 0x00000000
-#define regk_iop_fifo_out_pos 0x00000001
-#define regk_iop_fifo_out_pos_neg 0x00000003
-#define regk_iop_fifo_out_rw_cfg_default 0x00000024
-#define regk_iop_fifo_out_rw_ctrl_default 0x00000000
-#define regk_iop_fifo_out_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_out_rw_set_last_default 0x00000000
-#define regk_iop_fifo_out_rw_strb_dif_out_default 0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_last_default 0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_last_default 0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_last_default 0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_default 0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_last_default 0x00000000
-#define regk_iop_fifo_out_size16 0x00000002
-#define regk_iop_fifo_out_size24 0x00000001
-#define regk_iop_fifo_out_size32 0x00000000
-#define regk_iop_fifo_out_size8 0x00000003
-#define regk_iop_fifo_out_yes 0x00000001
-#endif /* __iop_fifo_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
deleted file mode 100644
index e8c488c389e4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_extra_defs_asm_h
-#define __iop_fifo_out_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:10 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
-#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
-
-/* Register r_rd_data, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_rd_data_offset 4
-
-/* Register r_stat, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_out_extra_r_stat___last___width 8
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_extra_r_stat_offset 8
-
-/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
-
-/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
-
-/* Register r_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_intr_offset 24
-
-/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
-
-
-/* Constants */
-#define regk_iop_fifo_out_extra_no 0x00000000
-#define regk_iop_fifo_out_extra_rw_intr_mask_default 0x00000000
-#define regk_iop_fifo_out_extra_yes 0x00000001
-#endif /* __iop_fifo_out_extra_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h
deleted file mode 100644
index 48869d445e07..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_mpu_defs_asm_h
-#define __iop_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_mpu.r
- * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
- * id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_mpu_rw_r 4
-/* Register rw_r, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_r_offset 0
-
-/* Register rw_ctrl, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_ctrl___en___lsb 0
-#define reg_iop_mpu_rw_ctrl___en___width 1
-#define reg_iop_mpu_rw_ctrl___en___bit 0
-#define reg_iop_mpu_rw_ctrl_offset 128
-
-/* Register r_pc, scope iop_mpu, type r */
-#define reg_iop_mpu_r_pc___addr___lsb 0
-#define reg_iop_mpu_r_pc___addr___width 12
-#define reg_iop_mpu_r_pc_offset 132
-
-/* Register r_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
-#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
-#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
-#define reg_iop_mpu_r_stat___intr_busy___lsb 1
-#define reg_iop_mpu_r_stat___intr_busy___width 1
-#define reg_iop_mpu_r_stat___intr_busy___bit 1
-#define reg_iop_mpu_r_stat___intr_vect___lsb 2
-#define reg_iop_mpu_r_stat___intr_vect___width 16
-#define reg_iop_mpu_r_stat_offset 136
-
-/* Register rw_instr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_instr_offset 140
-
-/* Register rw_immediate, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_immediate_offset 144
-
-/* Register r_trace, scope iop_mpu, type r */
-#define reg_iop_mpu_r_trace___intr_vect___lsb 0
-#define reg_iop_mpu_r_trace___intr_vect___width 16
-#define reg_iop_mpu_r_trace___pc___lsb 16
-#define reg_iop_mpu_r_trace___pc___width 12
-#define reg_iop_mpu_r_trace___en___lsb 28
-#define reg_iop_mpu_r_trace___en___width 1
-#define reg_iop_mpu_r_trace___en___bit 28
-#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
-#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
-#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
-#define reg_iop_mpu_r_trace___intr_busy___lsb 30
-#define reg_iop_mpu_r_trace___intr_busy___width 1
-#define reg_iop_mpu_r_trace___intr_busy___bit 30
-#define reg_iop_mpu_r_trace_offset 148
-
-/* Register r_wr_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_wr_stat___r0___lsb 0
-#define reg_iop_mpu_r_wr_stat___r0___width 1
-#define reg_iop_mpu_r_wr_stat___r0___bit 0
-#define reg_iop_mpu_r_wr_stat___r1___lsb 1
-#define reg_iop_mpu_r_wr_stat___r1___width 1
-#define reg_iop_mpu_r_wr_stat___r1___bit 1
-#define reg_iop_mpu_r_wr_stat___r2___lsb 2
-#define reg_iop_mpu_r_wr_stat___r2___width 1
-#define reg_iop_mpu_r_wr_stat___r2___bit 2
-#define reg_iop_mpu_r_wr_stat___r3___lsb 3
-#define reg_iop_mpu_r_wr_stat___r3___width 1
-#define reg_iop_mpu_r_wr_stat___r3___bit 3
-#define reg_iop_mpu_r_wr_stat___r4___lsb 4
-#define reg_iop_mpu_r_wr_stat___r4___width 1
-#define reg_iop_mpu_r_wr_stat___r4___bit 4
-#define reg_iop_mpu_r_wr_stat___r5___lsb 5
-#define reg_iop_mpu_r_wr_stat___r5___width 1
-#define reg_iop_mpu_r_wr_stat___r5___bit 5
-#define reg_iop_mpu_r_wr_stat___r6___lsb 6
-#define reg_iop_mpu_r_wr_stat___r6___width 1
-#define reg_iop_mpu_r_wr_stat___r6___bit 6
-#define reg_iop_mpu_r_wr_stat___r7___lsb 7
-#define reg_iop_mpu_r_wr_stat___r7___width 1
-#define reg_iop_mpu_r_wr_stat___r7___bit 7
-#define reg_iop_mpu_r_wr_stat___r8___lsb 8
-#define reg_iop_mpu_r_wr_stat___r8___width 1
-#define reg_iop_mpu_r_wr_stat___r8___bit 8
-#define reg_iop_mpu_r_wr_stat___r9___lsb 9
-#define reg_iop_mpu_r_wr_stat___r9___width 1
-#define reg_iop_mpu_r_wr_stat___r9___bit 9
-#define reg_iop_mpu_r_wr_stat___r10___lsb 10
-#define reg_iop_mpu_r_wr_stat___r10___width 1
-#define reg_iop_mpu_r_wr_stat___r10___bit 10
-#define reg_iop_mpu_r_wr_stat___r11___lsb 11
-#define reg_iop_mpu_r_wr_stat___r11___width 1
-#define reg_iop_mpu_r_wr_stat___r11___bit 11
-#define reg_iop_mpu_r_wr_stat___r12___lsb 12
-#define reg_iop_mpu_r_wr_stat___r12___width 1
-#define reg_iop_mpu_r_wr_stat___r12___bit 12
-#define reg_iop_mpu_r_wr_stat___r13___lsb 13
-#define reg_iop_mpu_r_wr_stat___r13___width 1
-#define reg_iop_mpu_r_wr_stat___r13___bit 13
-#define reg_iop_mpu_r_wr_stat___r14___lsb 14
-#define reg_iop_mpu_r_wr_stat___r14___width 1
-#define reg_iop_mpu_r_wr_stat___r14___bit 14
-#define reg_iop_mpu_r_wr_stat___r15___lsb 15
-#define reg_iop_mpu_r_wr_stat___r15___width 1
-#define reg_iop_mpu_r_wr_stat___r15___bit 15
-#define reg_iop_mpu_r_wr_stat_offset 152
-
-#define STRIDE_iop_mpu_rw_thread 4
-/* Register rw_thread, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_thread___addr___lsb 0
-#define reg_iop_mpu_rw_thread___addr___width 12
-#define reg_iop_mpu_rw_thread_offset 156
-
-#define STRIDE_iop_mpu_rw_intr 4
-/* Register rw_intr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_intr___addr___lsb 0
-#define reg_iop_mpu_rw_intr___addr___width 12
-#define reg_iop_mpu_rw_intr_offset 196
-
-
-/* Constants */
-#define regk_iop_mpu_no 0x00000000
-#define regk_iop_mpu_r_pc_default 0x00000000
-#define regk_iop_mpu_rw_ctrl_default 0x00000000
-#define regk_iop_mpu_rw_intr_size 0x00000010
-#define regk_iop_mpu_rw_r_size 0x00000010
-#define regk_iop_mpu_rw_thread_default 0x00000000
-#define regk_iop_mpu_rw_thread_size 0x00000004
-#define regk_iop_mpu_yes 0x00000001
-#endif /* __iop_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h
deleted file mode 100644
index 615f869a6de9..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
- */
-#define iop_version 0
-#define iop_fifo_in0_extra 64
-#define iop_fifo_in1_extra 128
-#define iop_fifo_out0_extra 192
-#define iop_fifo_out1_extra 256
-#define iop_trigger_grp0 320
-#define iop_trigger_grp1 384
-#define iop_trigger_grp2 448
-#define iop_trigger_grp3 512
-#define iop_trigger_grp4 576
-#define iop_trigger_grp5 640
-#define iop_trigger_grp6 704
-#define iop_trigger_grp7 768
-#define iop_crc_par0 896
-#define iop_crc_par1 1024
-#define iop_dmc_in0 1152
-#define iop_dmc_in1 1280
-#define iop_dmc_out0 1408
-#define iop_dmc_out1 1536
-#define iop_fifo_in0 1664
-#define iop_fifo_in1 1792
-#define iop_fifo_out0 1920
-#define iop_fifo_out1 2048
-#define iop_scrc_in0 2176
-#define iop_scrc_in1 2304
-#define iop_scrc_out0 2432
-#define iop_scrc_out1 2560
-#define iop_timer_grp0 2688
-#define iop_timer_grp1 2816
-#define iop_timer_grp2 2944
-#define iop_timer_grp3 3072
-#define iop_sap_in 3328
-#define iop_sap_out 3584
-#define iop_spu0 3840
-#define iop_spu1 4096
-#define iop_sw_cfg 4352
-#define iop_sw_cpu 4608
-#define iop_sw_mpu 4864
-#define iop_sw_spu0 5120
-#define iop_sw_spu1 5376
-#define iop_mpu 5632
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h
deleted file mode 100644
index fe8c90e015b0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_asm_h
-#define __iop_sap_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
- * id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_bus0_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus0_sync_offset 0
-
-/* Register rw_bus1_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus1_sync_offset 4
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_gio___sync_sel___width 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_gio___sync_edge___width 2
-#define reg_iop_sap_in_rw_gio___delay___lsb 7
-#define reg_iop_sap_in_rw_gio___delay___width 1
-#define reg_iop_sap_in_rw_gio___delay___bit 7
-#define reg_iop_sap_in_rw_gio___logic___lsb 8
-#define reg_iop_sap_in_rw_gio___logic___width 2
-#define reg_iop_sap_in_rw_gio_offset 8
-
-
-/* Constants */
-#define regk_iop_sap_in_and 0x00000002
-#define regk_iop_sap_in_ext_clk200 0x00000003
-#define regk_iop_sap_in_gio1 0x00000000
-#define regk_iop_sap_in_gio13 0x00000005
-#define regk_iop_sap_in_gio18 0x00000003
-#define regk_iop_sap_in_gio19 0x00000004
-#define regk_iop_sap_in_gio21 0x00000006
-#define regk_iop_sap_in_gio23 0x00000005
-#define regk_iop_sap_in_gio29 0x00000007
-#define regk_iop_sap_in_gio5 0x00000004
-#define regk_iop_sap_in_gio6 0x00000001
-#define regk_iop_sap_in_gio7 0x00000002
-#define regk_iop_sap_in_inv 0x00000001
-#define regk_iop_sap_in_neg 0x00000002
-#define regk_iop_sap_in_no 0x00000000
-#define regk_iop_sap_in_no_del_ext_clk200 0x00000001
-#define regk_iop_sap_in_none 0x00000000
-#define regk_iop_sap_in_or 0x00000003
-#define regk_iop_sap_in_pos 0x00000001
-#define regk_iop_sap_in_pos_neg 0x00000003
-#define regk_iop_sap_in_rw_bus0_sync_default 0x02020202
-#define regk_iop_sap_in_rw_bus1_sync_default 0x02020202
-#define regk_iop_sap_in_rw_gio_default 0x00000002
-#define regk_iop_sap_in_rw_gio_size 0x00000020
-#define regk_iop_sap_in_timer_grp0_tmr3 0x00000006
-#define regk_iop_sap_in_timer_grp1_tmr3 0x00000004
-#define regk_iop_sap_in_timer_grp2_tmr3 0x00000005
-#define regk_iop_sap_in_timer_grp3_tmr3 0x00000007
-#define regk_iop_sap_in_tmr_clk200 0x00000000
-#define regk_iop_sap_in_two_clk200 0x00000002
-#define regk_iop_sap_in_yes 0x00000001
-#endif /* __iop_sap_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h
deleted file mode 100644
index a5e46f0bbf6f..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_asm_h
-#define __iop_sap_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
- * id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated_offset 0
-
-/* Register rw_bus0, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus0_offset 4
-
-/* Register rw_bus1, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus1_offset 8
-
-/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
-
-/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
-
-/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
-
-/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
-#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
-#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
-#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
-#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
-#define reg_iop_sap_out_rw_gio___out_logic___width 1
-#define reg_iop_sap_out_rw_gio___out_logic___bit 10
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
-#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
-#define reg_iop_sap_out_rw_gio___oe_logic___width 2
-#define reg_iop_sap_out_rw_gio_offset 28
-
-
-/* Constants */
-#define regk_iop_sap_out_and 0x00000002
-#define regk_iop_sap_out_clk0 0x00000000
-#define regk_iop_sap_out_clk1 0x00000001
-#define regk_iop_sap_out_clk12 0x00000002
-#define regk_iop_sap_out_clk2 0x00000002
-#define regk_iop_sap_out_clk200 0x00000001
-#define regk_iop_sap_out_clk3 0x00000003
-#define regk_iop_sap_out_ext 0x00000003
-#define regk_iop_sap_out_gated 0x00000004
-#define regk_iop_sap_out_gio1 0x00000000
-#define regk_iop_sap_out_gio13 0x00000002
-#define regk_iop_sap_out_gio13_clk 0x0000000c
-#define regk_iop_sap_out_gio15 0x00000001
-#define regk_iop_sap_out_gio18 0x00000003
-#define regk_iop_sap_out_gio18_clk 0x0000000d
-#define regk_iop_sap_out_gio1_clk 0x00000008
-#define regk_iop_sap_out_gio21_clk 0x0000000e
-#define regk_iop_sap_out_gio23 0x00000002
-#define regk_iop_sap_out_gio29_clk 0x0000000f
-#define regk_iop_sap_out_gio31 0x00000003
-#define regk_iop_sap_out_gio5 0x00000001
-#define regk_iop_sap_out_gio5_clk 0x00000009
-#define regk_iop_sap_out_gio6_clk 0x0000000a
-#define regk_iop_sap_out_gio7 0x00000000
-#define regk_iop_sap_out_gio7_clk 0x0000000b
-#define regk_iop_sap_out_gio_in13 0x00000001
-#define regk_iop_sap_out_gio_in21 0x00000002
-#define regk_iop_sap_out_gio_in29 0x00000003
-#define regk_iop_sap_out_gio_in5 0x00000000
-#define regk_iop_sap_out_inv 0x00000001
-#define regk_iop_sap_out_nand 0x00000003
-#define regk_iop_sap_out_no 0x00000000
-#define regk_iop_sap_out_none 0x00000000
-#define regk_iop_sap_out_rw_bus0_default 0x00000000
-#define regk_iop_sap_out_rw_bus0_hi_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus0_lo_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus1_default 0x00000000
-#define regk_iop_sap_out_rw_bus1_hi_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus1_lo_oe_default 0x00000000
-#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
-#define regk_iop_sap_out_rw_gio_default 0x00000000
-#define regk_iop_sap_out_rw_gio_size 0x00000020
-#define regk_iop_sap_out_spu0_gio0 0x00000002
-#define regk_iop_sap_out_spu0_gio1 0x00000003
-#define regk_iop_sap_out_spu0_gio12 0x00000004
-#define regk_iop_sap_out_spu0_gio13 0x00000004
-#define regk_iop_sap_out_spu0_gio14 0x00000004
-#define regk_iop_sap_out_spu0_gio15 0x00000004
-#define regk_iop_sap_out_spu0_gio2 0x00000002
-#define regk_iop_sap_out_spu0_gio3 0x00000003
-#define regk_iop_sap_out_spu0_gio4 0x00000002
-#define regk_iop_sap_out_spu0_gio5 0x00000003
-#define regk_iop_sap_out_spu0_gio6 0x00000002
-#define regk_iop_sap_out_spu0_gio7 0x00000003
-#define regk_iop_sap_out_spu1_gio0 0x00000005
-#define regk_iop_sap_out_spu1_gio1 0x00000006
-#define regk_iop_sap_out_spu1_gio12 0x00000007
-#define regk_iop_sap_out_spu1_gio13 0x00000007
-#define regk_iop_sap_out_spu1_gio14 0x00000007
-#define regk_iop_sap_out_spu1_gio15 0x00000007
-#define regk_iop_sap_out_spu1_gio2 0x00000005
-#define regk_iop_sap_out_spu1_gio3 0x00000006
-#define regk_iop_sap_out_spu1_gio4 0x00000005
-#define regk_iop_sap_out_spu1_gio5 0x00000006
-#define regk_iop_sap_out_spu1_gio6 0x00000005
-#define regk_iop_sap_out_spu1_gio7 0x00000006
-#define regk_iop_sap_out_timer_grp0_tmr2 0x00000004
-#define regk_iop_sap_out_timer_grp1_tmr2 0x00000005
-#define regk_iop_sap_out_timer_grp2_tmr2 0x00000006
-#define regk_iop_sap_out_timer_grp3_tmr2 0x00000007
-#define regk_iop_sap_out_tmr 0x00000005
-#define regk_iop_sap_out_yes 0x00000001
-#endif /* __iop_sap_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h
deleted file mode 100644
index 169aaf8d44b2..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_in_defs_asm_h
-#define __iop_scrc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_in_rw_cfg___trig___width 2
-#define reg_iop_scrc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_scrc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_stat___err___lsb 0
-#define reg_iop_scrc_in_r_stat___err___width 1
-#define reg_iop_scrc_in_r_stat___err___bit 0
-#define reg_iop_scrc_in_r_stat_offset 8
-
-/* Register rw_init_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_init_crc_offset 12
-
-/* Register rs_computed_crc, scope iop_scrc_in, type rs */
-#define reg_iop_scrc_in_rs_computed_crc_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_computed_crc_offset 20
-
-/* Register rw_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_crc_offset 24
-
-/* Register rw_correct_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_correct_crc_offset 28
-
-/* Register rw_wr1bit, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
-#define reg_iop_scrc_in_rw_wr1bit___data___width 2
-#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
-#define reg_iop_scrc_in_rw_wr1bit___last___width 2
-#define reg_iop_scrc_in_rw_wr1bit_offset 32
-
-
-/* Constants */
-#define regk_iop_scrc_in_dif_in 0x00000002
-#define regk_iop_scrc_in_hi 0x00000000
-#define regk_iop_scrc_in_neg 0x00000002
-#define regk_iop_scrc_in_no 0x00000000
-#define regk_iop_scrc_in_pos 0x00000001
-#define regk_iop_scrc_in_pos_neg 0x00000003
-#define regk_iop_scrc_in_r_computed_crc_default 0x00000000
-#define regk_iop_scrc_in_rs_computed_crc_default 0x00000000
-#define regk_iop_scrc_in_rw_cfg_default 0x00000000
-#define regk_iop_scrc_in_rw_ctrl_default 0x00000000
-#define regk_iop_scrc_in_rw_init_crc_default 0x00000000
-#define regk_iop_scrc_in_set0 0x00000000
-#define regk_iop_scrc_in_set1 0x00000001
-#define regk_iop_scrc_in_yes 0x00000001
-#endif /* __iop_scrc_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h
deleted file mode 100644
index 0e9bca149bc6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_out_defs_asm_h
-#define __iop_scrc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_out_rw_cfg___trig___width 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
-#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
-#define reg_iop_scrc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
-#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
-#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
-#define reg_iop_scrc_out_rw_ctrl_offset 4
-
-/* Register rw_init_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_init_crc_offset 8
-
-/* Register rw_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_crc_offset 12
-
-/* Register rw_data, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_data___val___lsb 0
-#define reg_iop_scrc_out_rw_data___val___width 1
-#define reg_iop_scrc_out_rw_data___val___bit 0
-#define reg_iop_scrc_out_rw_data_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_out, type r */
-#define reg_iop_scrc_out_r_computed_crc_offset 20
-
-
-/* Constants */
-#define regk_iop_scrc_out_crc 0x00000001
-#define regk_iop_scrc_out_data 0x00000000
-#define regk_iop_scrc_out_dif 0x00000001
-#define regk_iop_scrc_out_hi 0x00000000
-#define regk_iop_scrc_out_neg 0x00000002
-#define regk_iop_scrc_out_no 0x00000000
-#define regk_iop_scrc_out_pos 0x00000001
-#define regk_iop_scrc_out_pos_neg 0x00000003
-#define regk_iop_scrc_out_reg 0x00000000
-#define regk_iop_scrc_out_rw_cfg_default 0x00000000
-#define regk_iop_scrc_out_rw_crc_default 0x00000000
-#define regk_iop_scrc_out_rw_ctrl_default 0x00000000
-#define regk_iop_scrc_out_rw_data_default 0x00000000
-#define regk_iop_scrc_out_rw_init_crc_default 0x00000000
-#define regk_iop_scrc_out_yes 0x00000001
-#endif /* __iop_scrc_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h
deleted file mode 100644
index cf2b64a9d42c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h
+++ /dev/null
@@ -1,574 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_spu_defs_asm_h
-#define __iop_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
- * id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_spu_rw_r 4
-/* Register rw_r, scope iop_spu, type rw */
-#define reg_iop_spu_rw_r_offset 0
-
-/* Register rw_seq_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_seq_pc___addr___lsb 0
-#define reg_iop_spu_rw_seq_pc___addr___width 12
-#define reg_iop_spu_rw_seq_pc_offset 64
-
-/* Register rw_fsm_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
-#define reg_iop_spu_rw_fsm_pc___addr___width 12
-#define reg_iop_spu_rw_fsm_pc_offset 68
-
-/* Register rw_ctrl, scope iop_spu, type rw */
-#define reg_iop_spu_rw_ctrl___fsm___lsb 0
-#define reg_iop_spu_rw_ctrl___fsm___width 1
-#define reg_iop_spu_rw_ctrl___fsm___bit 0
-#define reg_iop_spu_rw_ctrl___en___lsb 1
-#define reg_iop_spu_rw_ctrl___en___width 1
-#define reg_iop_spu_rw_ctrl___en___bit 1
-#define reg_iop_spu_rw_ctrl_offset 72
-
-/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
-
-/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
-
-/* Register rw_gio_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_offset 84
-
-/* Register rw_bus0_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus0_out_offset 88
-
-/* Register rw_bus1_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus1_out_offset 92
-
-/* Register r_gio_in, scope iop_spu, type r */
-#define reg_iop_spu_r_gio_in_offset 96
-
-/* Register r_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus0_in_offset 100
-
-/* Register r_bus1_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus1_in_offset 104
-
-/* Register rw_gio_out_set, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_set_offset 108
-
-/* Register rw_gio_out_clr, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_clr_offset 112
-
-/* Register rs_wr_stat, scope iop_spu, type rs */
-#define reg_iop_spu_rs_wr_stat___r0___lsb 0
-#define reg_iop_spu_rs_wr_stat___r0___width 1
-#define reg_iop_spu_rs_wr_stat___r0___bit 0
-#define reg_iop_spu_rs_wr_stat___r1___lsb 1
-#define reg_iop_spu_rs_wr_stat___r1___width 1
-#define reg_iop_spu_rs_wr_stat___r1___bit 1
-#define reg_iop_spu_rs_wr_stat___r2___lsb 2
-#define reg_iop_spu_rs_wr_stat___r2___width 1
-#define reg_iop_spu_rs_wr_stat___r2___bit 2
-#define reg_iop_spu_rs_wr_stat___r3___lsb 3
-#define reg_iop_spu_rs_wr_stat___r3___width 1
-#define reg_iop_spu_rs_wr_stat___r3___bit 3
-#define reg_iop_spu_rs_wr_stat___r4___lsb 4
-#define reg_iop_spu_rs_wr_stat___r4___width 1
-#define reg_iop_spu_rs_wr_stat___r4___bit 4
-#define reg_iop_spu_rs_wr_stat___r5___lsb 5
-#define reg_iop_spu_rs_wr_stat___r5___width 1
-#define reg_iop_spu_rs_wr_stat___r5___bit 5
-#define reg_iop_spu_rs_wr_stat___r6___lsb 6
-#define reg_iop_spu_rs_wr_stat___r6___width 1
-#define reg_iop_spu_rs_wr_stat___r6___bit 6
-#define reg_iop_spu_rs_wr_stat___r7___lsb 7
-#define reg_iop_spu_rs_wr_stat___r7___width 1
-#define reg_iop_spu_rs_wr_stat___r7___bit 7
-#define reg_iop_spu_rs_wr_stat___r8___lsb 8
-#define reg_iop_spu_rs_wr_stat___r8___width 1
-#define reg_iop_spu_rs_wr_stat___r8___bit 8
-#define reg_iop_spu_rs_wr_stat___r9___lsb 9
-#define reg_iop_spu_rs_wr_stat___r9___width 1
-#define reg_iop_spu_rs_wr_stat___r9___bit 9
-#define reg_iop_spu_rs_wr_stat___r10___lsb 10
-#define reg_iop_spu_rs_wr_stat___r10___width 1
-#define reg_iop_spu_rs_wr_stat___r10___bit 10
-#define reg_iop_spu_rs_wr_stat___r11___lsb 11
-#define reg_iop_spu_rs_wr_stat___r11___width 1
-#define reg_iop_spu_rs_wr_stat___r11___bit 11
-#define reg_iop_spu_rs_wr_stat___r12___lsb 12
-#define reg_iop_spu_rs_wr_stat___r12___width 1
-#define reg_iop_spu_rs_wr_stat___r12___bit 12
-#define reg_iop_spu_rs_wr_stat___r13___lsb 13
-#define reg_iop_spu_rs_wr_stat___r13___width 1
-#define reg_iop_spu_rs_wr_stat___r13___bit 13
-#define reg_iop_spu_rs_wr_stat___r14___lsb 14
-#define reg_iop_spu_rs_wr_stat___r14___width 1
-#define reg_iop_spu_rs_wr_stat___r14___bit 14
-#define reg_iop_spu_rs_wr_stat___r15___lsb 15
-#define reg_iop_spu_rs_wr_stat___r15___width 1
-#define reg_iop_spu_rs_wr_stat___r15___bit 15
-#define reg_iop_spu_rs_wr_stat_offset 116
-
-/* Register r_wr_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_wr_stat___r0___lsb 0
-#define reg_iop_spu_r_wr_stat___r0___width 1
-#define reg_iop_spu_r_wr_stat___r0___bit 0
-#define reg_iop_spu_r_wr_stat___r1___lsb 1
-#define reg_iop_spu_r_wr_stat___r1___width 1
-#define reg_iop_spu_r_wr_stat___r1___bit 1
-#define reg_iop_spu_r_wr_stat___r2___lsb 2
-#define reg_iop_spu_r_wr_stat___r2___width 1
-#define reg_iop_spu_r_wr_stat___r2___bit 2
-#define reg_iop_spu_r_wr_stat___r3___lsb 3
-#define reg_iop_spu_r_wr_stat___r3___width 1
-#define reg_iop_spu_r_wr_stat___r3___bit 3
-#define reg_iop_spu_r_wr_stat___r4___lsb 4
-#define reg_iop_spu_r_wr_stat___r4___width 1
-#define reg_iop_spu_r_wr_stat___r4___bit 4
-#define reg_iop_spu_r_wr_stat___r5___lsb 5
-#define reg_iop_spu_r_wr_stat___r5___width 1
-#define reg_iop_spu_r_wr_stat___r5___bit 5
-#define reg_iop_spu_r_wr_stat___r6___lsb 6
-#define reg_iop_spu_r_wr_stat___r6___width 1
-#define reg_iop_spu_r_wr_stat___r6___bit 6
-#define reg_iop_spu_r_wr_stat___r7___lsb 7
-#define reg_iop_spu_r_wr_stat___r7___width 1
-#define reg_iop_spu_r_wr_stat___r7___bit 7
-#define reg_iop_spu_r_wr_stat___r8___lsb 8
-#define reg_iop_spu_r_wr_stat___r8___width 1
-#define reg_iop_spu_r_wr_stat___r8___bit 8
-#define reg_iop_spu_r_wr_stat___r9___lsb 9
-#define reg_iop_spu_r_wr_stat___r9___width 1
-#define reg_iop_spu_r_wr_stat___r9___bit 9
-#define reg_iop_spu_r_wr_stat___r10___lsb 10
-#define reg_iop_spu_r_wr_stat___r10___width 1
-#define reg_iop_spu_r_wr_stat___r10___bit 10
-#define reg_iop_spu_r_wr_stat___r11___lsb 11
-#define reg_iop_spu_r_wr_stat___r11___width 1
-#define reg_iop_spu_r_wr_stat___r11___bit 11
-#define reg_iop_spu_r_wr_stat___r12___lsb 12
-#define reg_iop_spu_r_wr_stat___r12___width 1
-#define reg_iop_spu_r_wr_stat___r12___bit 12
-#define reg_iop_spu_r_wr_stat___r13___lsb 13
-#define reg_iop_spu_r_wr_stat___r13___width 1
-#define reg_iop_spu_r_wr_stat___r13___bit 13
-#define reg_iop_spu_r_wr_stat___r14___lsb 14
-#define reg_iop_spu_r_wr_stat___r14___width 1
-#define reg_iop_spu_r_wr_stat___r14___bit 14
-#define reg_iop_spu_r_wr_stat___r15___lsb 15
-#define reg_iop_spu_r_wr_stat___r15___width 1
-#define reg_iop_spu_r_wr_stat___r15___bit 15
-#define reg_iop_spu_r_wr_stat_offset 120
-
-/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
-
-/* Register r_stat_in, scope iop_spu, type r */
-#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
-#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
-#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
-#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
-#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
-#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
-#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
-#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
-#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
-#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
-#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
-#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
-#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
-#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
-#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
-#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
-#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
-#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
-#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
-#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
-#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
-#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
-#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
-#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
-#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
-#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
-#define reg_iop_spu_r_stat_in___sync_clk12___width 1
-#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
-#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
-#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
-#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
-#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
-#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
-#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
-#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
-#define reg_iop_spu_r_stat_in___mc_busy___width 1
-#define reg_iop_spu_r_stat_in___mc_busy___bit 30
-#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
-#define reg_iop_spu_r_stat_in___mc_owned___width 1
-#define reg_iop_spu_r_stat_in___mc_owned___bit 31
-#define reg_iop_spu_r_stat_in_offset 128
-
-/* Register r_trigger_in, scope iop_spu, type r */
-#define reg_iop_spu_r_trigger_in_offset 132
-
-/* Register r_special_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_special_stat___c_flag___lsb 0
-#define reg_iop_spu_r_special_stat___c_flag___width 1
-#define reg_iop_spu_r_special_stat___c_flag___bit 0
-#define reg_iop_spu_r_special_stat___v_flag___lsb 1
-#define reg_iop_spu_r_special_stat___v_flag___width 1
-#define reg_iop_spu_r_special_stat___v_flag___bit 1
-#define reg_iop_spu_r_special_stat___z_flag___lsb 2
-#define reg_iop_spu_r_special_stat___z_flag___width 1
-#define reg_iop_spu_r_special_stat___z_flag___bit 2
-#define reg_iop_spu_r_special_stat___n_flag___lsb 3
-#define reg_iop_spu_r_special_stat___n_flag___width 1
-#define reg_iop_spu_r_special_stat___n_flag___bit 3
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
-#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
-#define reg_iop_spu_r_special_stat___fsm_in0___width 1
-#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
-#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
-#define reg_iop_spu_r_special_stat___fsm_in1___width 1
-#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
-#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
-#define reg_iop_spu_r_special_stat___fsm_in2___width 1
-#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
-#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
-#define reg_iop_spu_r_special_stat___fsm_in3___width 1
-#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
-#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
-#define reg_iop_spu_r_special_stat___fsm_in4___width 1
-#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
-#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
-#define reg_iop_spu_r_special_stat___fsm_in5___width 1
-#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
-#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
-#define reg_iop_spu_r_special_stat___fsm_in6___width 1
-#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
-#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
-#define reg_iop_spu_r_special_stat___fsm_in7___width 1
-#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
-#define reg_iop_spu_r_special_stat___event0___lsb 16
-#define reg_iop_spu_r_special_stat___event0___width 1
-#define reg_iop_spu_r_special_stat___event0___bit 16
-#define reg_iop_spu_r_special_stat___event1___lsb 17
-#define reg_iop_spu_r_special_stat___event1___width 1
-#define reg_iop_spu_r_special_stat___event1___bit 17
-#define reg_iop_spu_r_special_stat___event2___lsb 18
-#define reg_iop_spu_r_special_stat___event2___width 1
-#define reg_iop_spu_r_special_stat___event2___bit 18
-#define reg_iop_spu_r_special_stat___event3___lsb 19
-#define reg_iop_spu_r_special_stat___event3___width 1
-#define reg_iop_spu_r_special_stat___event3___bit 19
-#define reg_iop_spu_r_special_stat_offset 136
-
-/* Register rw_reg_access, scope iop_spu, type rw */
-#define reg_iop_spu_rw_reg_access___addr___lsb 0
-#define reg_iop_spu_rw_reg_access___addr___width 13
-#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
-#define reg_iop_spu_rw_reg_access___imm_hi___width 16
-#define reg_iop_spu_rw_reg_access_offset 140
-
-#define STRIDE_iop_spu_rw_event_cfg 4
-/* Register rw_event_cfg, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_cfg___addr___lsb 0
-#define reg_iop_spu_rw_event_cfg___addr___width 12
-#define reg_iop_spu_rw_event_cfg___src___lsb 12
-#define reg_iop_spu_rw_event_cfg___src___width 2
-#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
-#define reg_iop_spu_rw_event_cfg___eq_en___width 1
-#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
-#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
-#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
-#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
-#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
-#define reg_iop_spu_rw_event_cfg___gt_en___width 1
-#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
-#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
-#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
-#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
-#define reg_iop_spu_rw_event_cfg_offset 144
-
-#define STRIDE_iop_spu_rw_event_mask 4
-/* Register rw_event_mask, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_mask_offset 160
-
-#define STRIDE_iop_spu_rw_event_val 4
-/* Register rw_event_val, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_val_offset 176
-
-/* Register rw_event_ret, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_ret___addr___lsb 0
-#define reg_iop_spu_rw_event_ret___addr___width 12
-#define reg_iop_spu_rw_event_ret_offset 192
-
-/* Register r_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_trace___fsm___lsb 0
-#define reg_iop_spu_r_trace___fsm___width 1
-#define reg_iop_spu_r_trace___fsm___bit 0
-#define reg_iop_spu_r_trace___en___lsb 1
-#define reg_iop_spu_r_trace___en___width 1
-#define reg_iop_spu_r_trace___en___bit 1
-#define reg_iop_spu_r_trace___c_flag___lsb 2
-#define reg_iop_spu_r_trace___c_flag___width 1
-#define reg_iop_spu_r_trace___c_flag___bit 2
-#define reg_iop_spu_r_trace___v_flag___lsb 3
-#define reg_iop_spu_r_trace___v_flag___width 1
-#define reg_iop_spu_r_trace___v_flag___bit 3
-#define reg_iop_spu_r_trace___z_flag___lsb 4
-#define reg_iop_spu_r_trace___z_flag___width 1
-#define reg_iop_spu_r_trace___z_flag___bit 4
-#define reg_iop_spu_r_trace___n_flag___lsb 5
-#define reg_iop_spu_r_trace___n_flag___width 1
-#define reg_iop_spu_r_trace___n_flag___bit 5
-#define reg_iop_spu_r_trace___seq_addr___lsb 6
-#define reg_iop_spu_r_trace___seq_addr___width 12
-#define reg_iop_spu_r_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_trace___fsm_addr___width 12
-#define reg_iop_spu_r_trace_offset 196
-
-/* Register r_fsm_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
-#define reg_iop_spu_r_fsm_trace___fsm___width 1
-#define reg_iop_spu_r_fsm_trace___fsm___bit 0
-#define reg_iop_spu_r_fsm_trace___en___lsb 1
-#define reg_iop_spu_r_fsm_trace___en___width 1
-#define reg_iop_spu_r_fsm_trace___en___bit 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
-#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
-#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
-#define reg_iop_spu_r_fsm_trace___inp0___width 1
-#define reg_iop_spu_r_fsm_trace___inp0___bit 3
-#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
-#define reg_iop_spu_r_fsm_trace___inp1___width 1
-#define reg_iop_spu_r_fsm_trace___inp1___bit 4
-#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
-#define reg_iop_spu_r_fsm_trace___inp2___width 1
-#define reg_iop_spu_r_fsm_trace___inp2___bit 5
-#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
-#define reg_iop_spu_r_fsm_trace___inp3___width 1
-#define reg_iop_spu_r_fsm_trace___inp3___bit 6
-#define reg_iop_spu_r_fsm_trace___event0___lsb 7
-#define reg_iop_spu_r_fsm_trace___event0___width 1
-#define reg_iop_spu_r_fsm_trace___event0___bit 7
-#define reg_iop_spu_r_fsm_trace___event1___lsb 8
-#define reg_iop_spu_r_fsm_trace___event1___width 1
-#define reg_iop_spu_r_fsm_trace___event1___bit 8
-#define reg_iop_spu_r_fsm_trace___event2___lsb 9
-#define reg_iop_spu_r_fsm_trace___event2___width 1
-#define reg_iop_spu_r_fsm_trace___event2___bit 9
-#define reg_iop_spu_r_fsm_trace___event3___lsb 10
-#define reg_iop_spu_r_fsm_trace___event3___width 1
-#define reg_iop_spu_r_fsm_trace___event3___bit 10
-#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
-#define reg_iop_spu_r_fsm_trace___gio_out___width 8
-#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
-#define reg_iop_spu_r_fsm_trace_offset 200
-
-#define STRIDE_iop_spu_rw_brp 4
-/* Register rw_brp, scope iop_spu, type rw */
-#define reg_iop_spu_rw_brp___addr___lsb 0
-#define reg_iop_spu_rw_brp___addr___width 12
-#define reg_iop_spu_rw_brp___fsm___lsb 12
-#define reg_iop_spu_rw_brp___fsm___width 1
-#define reg_iop_spu_rw_brp___fsm___bit 12
-#define reg_iop_spu_rw_brp___en___lsb 13
-#define reg_iop_spu_rw_brp___en___width 1
-#define reg_iop_spu_rw_brp___en___bit 13
-#define reg_iop_spu_rw_brp_offset 204
-
-
-/* Constants */
-#define regk_iop_spu_attn_hi 0x00000005
-#define regk_iop_spu_attn_lo 0x00000005
-#define regk_iop_spu_attn_r0 0x00000000
-#define regk_iop_spu_attn_r1 0x00000001
-#define regk_iop_spu_attn_r10 0x00000002
-#define regk_iop_spu_attn_r11 0x00000003
-#define regk_iop_spu_attn_r12 0x00000004
-#define regk_iop_spu_attn_r13 0x00000005
-#define regk_iop_spu_attn_r14 0x00000006
-#define regk_iop_spu_attn_r15 0x00000007
-#define regk_iop_spu_attn_r2 0x00000002
-#define regk_iop_spu_attn_r3 0x00000003
-#define regk_iop_spu_attn_r4 0x00000004
-#define regk_iop_spu_attn_r5 0x00000005
-#define regk_iop_spu_attn_r6 0x00000006
-#define regk_iop_spu_attn_r7 0x00000007
-#define regk_iop_spu_attn_r8 0x00000000
-#define regk_iop_spu_attn_r9 0x00000001
-#define regk_iop_spu_c 0x00000000
-#define regk_iop_spu_flag 0x00000002
-#define regk_iop_spu_gio_in 0x00000000
-#define regk_iop_spu_gio_out 0x00000005
-#define regk_iop_spu_gio_out0 0x00000008
-#define regk_iop_spu_gio_out1 0x00000009
-#define regk_iop_spu_gio_out2 0x0000000a
-#define regk_iop_spu_gio_out3 0x0000000b
-#define regk_iop_spu_gio_out4 0x0000000c
-#define regk_iop_spu_gio_out5 0x0000000d
-#define regk_iop_spu_gio_out6 0x0000000e
-#define regk_iop_spu_gio_out7 0x0000000f
-#define regk_iop_spu_n 0x00000003
-#define regk_iop_spu_no 0x00000000
-#define regk_iop_spu_r0 0x00000008
-#define regk_iop_spu_r1 0x00000009
-#define regk_iop_spu_r10 0x0000000a
-#define regk_iop_spu_r11 0x0000000b
-#define regk_iop_spu_r12 0x0000000c
-#define regk_iop_spu_r13 0x0000000d
-#define regk_iop_spu_r14 0x0000000e
-#define regk_iop_spu_r15 0x0000000f
-#define regk_iop_spu_r2 0x0000000a
-#define regk_iop_spu_r3 0x0000000b
-#define regk_iop_spu_r4 0x0000000c
-#define regk_iop_spu_r5 0x0000000d
-#define regk_iop_spu_r6 0x0000000e
-#define regk_iop_spu_r7 0x0000000f
-#define regk_iop_spu_r8 0x00000008
-#define regk_iop_spu_r9 0x00000009
-#define regk_iop_spu_reg_hi 0x00000002
-#define regk_iop_spu_reg_lo 0x00000002
-#define regk_iop_spu_rw_brp_default 0x00000000
-#define regk_iop_spu_rw_brp_size 0x00000004
-#define regk_iop_spu_rw_ctrl_default 0x00000000
-#define regk_iop_spu_rw_event_cfg_size 0x00000004
-#define regk_iop_spu_rw_event_mask_size 0x00000004
-#define regk_iop_spu_rw_event_val_size 0x00000004
-#define regk_iop_spu_rw_gio_out_default 0x00000000
-#define regk_iop_spu_rw_r_size 0x00000010
-#define regk_iop_spu_rw_reg_access_default 0x00000000
-#define regk_iop_spu_stat_in 0x00000002
-#define regk_iop_spu_statin_hi 0x00000004
-#define regk_iop_spu_statin_lo 0x00000004
-#define regk_iop_spu_trig 0x00000003
-#define regk_iop_spu_trigger 0x00000006
-#define regk_iop_spu_v 0x00000001
-#define regk_iop_spu_wsts_gioout_spec 0x00000001
-#define regk_iop_spu_xor 0x00000003
-#define regk_iop_spu_xor_bus0_r2_0 0x00000000
-#define regk_iop_spu_xor_bus0m_r2_0 0x00000002
-#define regk_iop_spu_xor_bus1_r3_0 0x00000001
-#define regk_iop_spu_xor_bus1m_r3_0 0x00000003
-#define regk_iop_spu_yes 0x00000001
-#define regk_iop_spu_z 0x00000002
-#endif /* __iop_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
deleted file mode 100644
index 4f4c7340d39a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
+++ /dev/null
@@ -1,1053 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_asm_h
-#define __iop_sw_cfg_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
-
-/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
-
-/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
-
-/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
-
-/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
-
-/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
-
-/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
-
-/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
-
-/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
-
-/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
-
-/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
-
-/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
-
-/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
-
-/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
-
-/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
-
-/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
-
-/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
-
-/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
-
-/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu0_owner_offset 80
-
-/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu1_owner_offset 84
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
-
-/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
-
-/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
-
-/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask_offset 136
-
-/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
-
-/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask_offset 144
-
-/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_mask_offset 152
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
-#define reg_iop_sw_cfg_rw_pinmapping_offset 160
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
-
-/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
-
-/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
-
-/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
-
-/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
-
-/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
-
-/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
-
-
-/* Constants */
-#define regk_iop_sw_cfg_a 0x00000001
-#define regk_iop_sw_cfg_b 0x00000002
-#define regk_iop_sw_cfg_bus0 0x00000000
-#define regk_iop_sw_cfg_bus0_rot16 0x00000004
-#define regk_iop_sw_cfg_bus0_rot24 0x00000006
-#define regk_iop_sw_cfg_bus0_rot8 0x00000002
-#define regk_iop_sw_cfg_bus1 0x00000001
-#define regk_iop_sw_cfg_bus1_rot16 0x00000005
-#define regk_iop_sw_cfg_bus1_rot24 0x00000007
-#define regk_iop_sw_cfg_bus1_rot8 0x00000003
-#define regk_iop_sw_cfg_clk12 0x00000000
-#define regk_iop_sw_cfg_cpu 0x00000000
-#define regk_iop_sw_cfg_dmc0 0x00000000
-#define regk_iop_sw_cfg_dmc1 0x00000001
-#define regk_iop_sw_cfg_gated_clk0 0x00000010
-#define regk_iop_sw_cfg_gated_clk1 0x00000011
-#define regk_iop_sw_cfg_gated_clk2 0x00000012
-#define regk_iop_sw_cfg_gated_clk3 0x00000013
-#define regk_iop_sw_cfg_gio0 0x00000004
-#define regk_iop_sw_cfg_gio1 0x00000001
-#define regk_iop_sw_cfg_gio2 0x00000005
-#define regk_iop_sw_cfg_gio3 0x00000002
-#define regk_iop_sw_cfg_gio4 0x00000006
-#define regk_iop_sw_cfg_gio5 0x00000003
-#define regk_iop_sw_cfg_gio6 0x00000007
-#define regk_iop_sw_cfg_gio7 0x00000004
-#define regk_iop_sw_cfg_gio_in0 0x00000000
-#define regk_iop_sw_cfg_gio_in1 0x00000001
-#define regk_iop_sw_cfg_gio_in10 0x00000002
-#define regk_iop_sw_cfg_gio_in11 0x00000003
-#define regk_iop_sw_cfg_gio_in14 0x00000004
-#define regk_iop_sw_cfg_gio_in15 0x00000005
-#define regk_iop_sw_cfg_gio_in18 0x00000002
-#define regk_iop_sw_cfg_gio_in19 0x00000003
-#define regk_iop_sw_cfg_gio_in20 0x00000004
-#define regk_iop_sw_cfg_gio_in21 0x00000005
-#define regk_iop_sw_cfg_gio_in26 0x00000006
-#define regk_iop_sw_cfg_gio_in27 0x00000007
-#define regk_iop_sw_cfg_gio_in28 0x00000006
-#define regk_iop_sw_cfg_gio_in29 0x00000007
-#define regk_iop_sw_cfg_gio_in4 0x00000000
-#define regk_iop_sw_cfg_gio_in5 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp2_tmr2 0x00000002
-#define regk_iop_sw_cfg_last_timer_grp2_tmr3 0x00000003
-#define regk_iop_sw_cfg_last_timer_grp3_tmr2 0x00000002
-#define regk_iop_sw_cfg_last_timer_grp3_tmr3 0x00000003
-#define regk_iop_sw_cfg_mpu 0x00000001
-#define regk_iop_sw_cfg_none 0x00000000
-#define regk_iop_sw_cfg_par0 0x00000000
-#define regk_iop_sw_cfg_par1 0x00000001
-#define regk_iop_sw_cfg_pdp_out0 0x00000002
-#define regk_iop_sw_cfg_pdp_out0_hi 0x00000001
-#define regk_iop_sw_cfg_pdp_out0_hi_rot8 0x00000005
-#define regk_iop_sw_cfg_pdp_out0_lo 0x00000000
-#define regk_iop_sw_cfg_pdp_out0_lo_rot8 0x00000004
-#define regk_iop_sw_cfg_pdp_out1 0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi 0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi_rot8 0x00000005
-#define regk_iop_sw_cfg_pdp_out1_lo 0x00000002
-#define regk_iop_sw_cfg_pdp_out1_lo_rot8 0x00000004
-#define regk_iop_sw_cfg_rw_bus0_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus0_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus1_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus1_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_crc_par0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_crc_par1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pdp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pdp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pinmapping_default 0x55555555
-#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
-#define regk_iop_sw_cfg_sdp_out0 0x00000008
-#define regk_iop_sw_cfg_sdp_out1 0x00000009
-#define regk_iop_sw_cfg_size16 0x00000002
-#define regk_iop_sw_cfg_size24 0x00000003
-#define regk_iop_sw_cfg_size32 0x00000004
-#define regk_iop_sw_cfg_size8 0x00000001
-#define regk_iop_sw_cfg_spu0 0x00000002
-#define regk_iop_sw_cfg_spu0_bus_out0_hi 0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out0_lo 0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out1_hi 0x00000007
-#define regk_iop_sw_cfg_spu0_bus_out1_lo 0x00000007
-#define regk_iop_sw_cfg_spu0_g0 0x0000000e
-#define regk_iop_sw_cfg_spu0_g1 0x0000000e
-#define regk_iop_sw_cfg_spu0_g2 0x0000000e
-#define regk_iop_sw_cfg_spu0_g3 0x0000000e
-#define regk_iop_sw_cfg_spu0_g4 0x0000000e
-#define regk_iop_sw_cfg_spu0_g5 0x0000000e
-#define regk_iop_sw_cfg_spu0_g6 0x0000000e
-#define regk_iop_sw_cfg_spu0_g7 0x0000000e
-#define regk_iop_sw_cfg_spu0_gio0 0x00000000
-#define regk_iop_sw_cfg_spu0_gio1 0x00000001
-#define regk_iop_sw_cfg_spu0_gio2 0x00000000
-#define regk_iop_sw_cfg_spu0_gio5 0x00000005
-#define regk_iop_sw_cfg_spu0_gio6 0x00000006
-#define regk_iop_sw_cfg_spu0_gio7 0x00000007
-#define regk_iop_sw_cfg_spu0_gio_out0 0x00000008
-#define regk_iop_sw_cfg_spu0_gio_out1 0x00000009
-#define regk_iop_sw_cfg_spu0_gio_out2 0x0000000a
-#define regk_iop_sw_cfg_spu0_gio_out3 0x0000000b
-#define regk_iop_sw_cfg_spu0_gio_out4 0x0000000c
-#define regk_iop_sw_cfg_spu0_gio_out5 0x0000000d
-#define regk_iop_sw_cfg_spu0_gio_out6 0x0000000e
-#define regk_iop_sw_cfg_spu0_gio_out7 0x0000000f
-#define regk_iop_sw_cfg_spu0_gioout0 0x00000000
-#define regk_iop_sw_cfg_spu0_gioout1 0x00000000
-#define regk_iop_sw_cfg_spu0_gioout10 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout11 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout12 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout13 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout14 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout15 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout16 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout17 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout18 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout19 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout2 0x00000002
-#define regk_iop_sw_cfg_spu0_gioout20 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout21 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout22 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout23 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout24 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout25 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout26 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout27 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout28 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout29 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout3 0x00000002
-#define regk_iop_sw_cfg_spu0_gioout30 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout31 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout4 0x00000004
-#define regk_iop_sw_cfg_spu0_gioout5 0x00000004
-#define regk_iop_sw_cfg_spu0_gioout6 0x00000006
-#define regk_iop_sw_cfg_spu0_gioout7 0x00000006
-#define regk_iop_sw_cfg_spu0_gioout8 0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout9 0x0000000e
-#define regk_iop_sw_cfg_spu1 0x00000003
-#define regk_iop_sw_cfg_spu1_bus_out0_hi 0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out0_lo 0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out1_hi 0x00000007
-#define regk_iop_sw_cfg_spu1_bus_out1_lo 0x00000007
-#define regk_iop_sw_cfg_spu1_g0 0x0000000f
-#define regk_iop_sw_cfg_spu1_g1 0x0000000f
-#define regk_iop_sw_cfg_spu1_g2 0x0000000f
-#define regk_iop_sw_cfg_spu1_g3 0x0000000f
-#define regk_iop_sw_cfg_spu1_g4 0x0000000f
-#define regk_iop_sw_cfg_spu1_g5 0x0000000f
-#define regk_iop_sw_cfg_spu1_g6 0x0000000f
-#define regk_iop_sw_cfg_spu1_g7 0x0000000f
-#define regk_iop_sw_cfg_spu1_gio0 0x00000002
-#define regk_iop_sw_cfg_spu1_gio1 0x00000003
-#define regk_iop_sw_cfg_spu1_gio2 0x00000002
-#define regk_iop_sw_cfg_spu1_gio5 0x00000005
-#define regk_iop_sw_cfg_spu1_gio6 0x00000006
-#define regk_iop_sw_cfg_spu1_gio7 0x00000007
-#define regk_iop_sw_cfg_spu1_gio_out0 0x00000008
-#define regk_iop_sw_cfg_spu1_gio_out1 0x00000009
-#define regk_iop_sw_cfg_spu1_gio_out2 0x0000000a
-#define regk_iop_sw_cfg_spu1_gio_out3 0x0000000b
-#define regk_iop_sw_cfg_spu1_gio_out4 0x0000000c
-#define regk_iop_sw_cfg_spu1_gio_out5 0x0000000d
-#define regk_iop_sw_cfg_spu1_gio_out6 0x0000000e
-#define regk_iop_sw_cfg_spu1_gio_out7 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout0 0x00000001
-#define regk_iop_sw_cfg_spu1_gioout1 0x00000001
-#define regk_iop_sw_cfg_spu1_gioout10 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout11 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout12 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout13 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout14 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout15 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout16 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout17 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout18 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout19 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout2 0x00000003
-#define regk_iop_sw_cfg_spu1_gioout20 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout21 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout22 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout23 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout24 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout25 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout26 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout27 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout28 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout29 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout3 0x00000003
-#define regk_iop_sw_cfg_spu1_gioout30 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout31 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout4 0x00000005
-#define regk_iop_sw_cfg_spu1_gioout5 0x00000005
-#define regk_iop_sw_cfg_spu1_gioout6 0x00000007
-#define regk_iop_sw_cfg_spu1_gioout7 0x00000007
-#define regk_iop_sw_cfg_spu1_gioout8 0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout9 0x0000000f
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr0 0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr0 0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr1 0x00000002
-#define regk_iop_sw_cfg_timer_grp0 0x00000000
-#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp0_strb0 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb1 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb2 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb3 0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000004
-#define regk_iop_sw_cfg_timer_grp0_tmr1 0x00000004
-#define regk_iop_sw_cfg_timer_grp1 0x00000000
-#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp1_strb0 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb1 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb2 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb3 0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000005
-#define regk_iop_sw_cfg_timer_grp1_tmr1 0x00000005
-#define regk_iop_sw_cfg_timer_grp2 0x00000000
-#define regk_iop_sw_cfg_timer_grp2_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp2_strb0 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb1 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb2 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb3 0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_tmr0 0x00000006
-#define regk_iop_sw_cfg_timer_grp2_tmr1 0x00000006
-#define regk_iop_sw_cfg_timer_grp3 0x00000000
-#define regk_iop_sw_cfg_timer_grp3_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp3_strb0 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb1 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb2 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb3 0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_tmr0 0x00000007
-#define regk_iop_sw_cfg_timer_grp3_tmr1 0x00000007
-#define regk_iop_sw_cfg_trig0_0 0x00000000
-#define regk_iop_sw_cfg_trig0_1 0x00000000
-#define regk_iop_sw_cfg_trig0_2 0x00000000
-#define regk_iop_sw_cfg_trig0_3 0x00000000
-#define regk_iop_sw_cfg_trig1_0 0x00000000
-#define regk_iop_sw_cfg_trig1_1 0x00000000
-#define regk_iop_sw_cfg_trig1_2 0x00000000
-#define regk_iop_sw_cfg_trig1_3 0x00000000
-#define regk_iop_sw_cfg_trig2_0 0x00000000
-#define regk_iop_sw_cfg_trig2_1 0x00000000
-#define regk_iop_sw_cfg_trig2_2 0x00000000
-#define regk_iop_sw_cfg_trig2_3 0x00000000
-#define regk_iop_sw_cfg_trig3_0 0x00000000
-#define regk_iop_sw_cfg_trig3_1 0x00000000
-#define regk_iop_sw_cfg_trig3_2 0x00000000
-#define regk_iop_sw_cfg_trig3_3 0x00000000
-#define regk_iop_sw_cfg_trig4_0 0x00000001
-#define regk_iop_sw_cfg_trig4_1 0x00000001
-#define regk_iop_sw_cfg_trig4_2 0x00000001
-#define regk_iop_sw_cfg_trig4_3 0x00000001
-#define regk_iop_sw_cfg_trig5_0 0x00000001
-#define regk_iop_sw_cfg_trig5_1 0x00000001
-#define regk_iop_sw_cfg_trig5_2 0x00000001
-#define regk_iop_sw_cfg_trig5_3 0x00000001
-#define regk_iop_sw_cfg_trig6_0 0x00000001
-#define regk_iop_sw_cfg_trig6_1 0x00000001
-#define regk_iop_sw_cfg_trig6_2 0x00000001
-#define regk_iop_sw_cfg_trig6_3 0x00000001
-#define regk_iop_sw_cfg_trig7_0 0x00000001
-#define regk_iop_sw_cfg_trig7_1 0x00000001
-#define regk_iop_sw_cfg_trig7_2 0x00000001
-#define regk_iop_sw_cfg_trig7_3 0x00000001
-#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
deleted file mode 100644
index ef04a57a0680..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
+++ /dev/null
@@ -1,1759 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_asm_h
-#define __iop_sw_cpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_cpu_rw_mc_data___val___width 32
-#define reg_iop_sw_cpu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-#define reg_iop_sw_cpu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_cpu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_gio_in_offset 80
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_intr0_mask_offset 84
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr0_offset 88
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_intr0_offset 92
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_masked_intr0_offset 96
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_intr1_mask_offset 100
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr1_offset 104
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_intr1_offset 108
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_masked_intr1_offset 112
-
-/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
-#define reg_iop_sw_cpu_rw_intr2_mask_offset 116
-
-/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr2_offset 120
-
-/* Register r_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_intr2_offset 124
-
-/* Register r_masked_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_masked_intr2_offset 128
-
-/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31
-#define reg_iop_sw_cpu_rw_intr3_mask_offset 132
-
-/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr3_offset 136
-
-/* Register r_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_intr3_offset 140
-
-/* Register r_masked_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_masked_intr3_offset 144
-
-
-/* Constants */
-#define regk_iop_sw_cpu_copy 0x00000000
-#define regk_iop_sw_cpu_no 0x00000000
-#define regk_iop_sw_cpu_rd 0x00000002
-#define regk_iop_sw_cpu_reg_copy 0x00000001
-#define regk_iop_sw_cpu_rw_bus0_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus0_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus1_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr2_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr3_mask_default 0x00000000
-#define regk_iop_sw_cpu_wr 0x00000003
-#define regk_iop_sw_cpu_yes 0x00000001
-#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
deleted file mode 100644
index 22292069e4fd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
+++ /dev/null
@@ -1,1777 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_asm_h
-#define __iop_sw_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
-#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_mpu_rw_mc_data___val___width 32
-#define reg_iop_sw_mpu_rw_mc_data_offset 8
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_addr_offset 12
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-#define reg_iop_sw_mpu_rs_mc_data_offset 16
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_data_offset 20
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_mpu_r_mc_stat_offset 24
-
-/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28
-
-/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40
-
-/* Register r_bus0_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus0_in_offset 44
-
-/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48
-
-/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60
-
-/* Register r_bus1_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus1_in_offset 64
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_gio_in_offset 84
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_rw_cpu_intr_offset 88
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_r_cpu_intr_offset 92
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp0_offset 104
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp1_offset 120
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp2_offset 136
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp3_offset 152
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156
-
-
-/* Constants */
-#define regk_iop_sw_mpu_copy 0x00000000
-#define regk_iop_sw_mpu_cpu 0x00000000
-#define regk_iop_sw_mpu_mpu 0x00000001
-#define regk_iop_sw_mpu_no 0x00000000
-#define regk_iop_sw_mpu_nop 0x00000000
-#define regk_iop_sw_mpu_rd 0x00000002
-#define regk_iop_sw_mpu_reg_copy 0x00000001
-#define regk_iop_sw_mpu_rw_bus0_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus0_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus1_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000
-#define regk_iop_sw_mpu_set 0x00000001
-#define regk_iop_sw_mpu_spu0 0x00000002
-#define regk_iop_sw_mpu_spu1 0x00000003
-#define regk_iop_sw_mpu_wr 0x00000003
-#define regk_iop_sw_mpu_yes 0x00000001
-#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h
deleted file mode 100644
index 82729218621c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_asm_h
-#define __iop_sw_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_spu_rw_mc_data___val___width 32
-#define reg_iop_sw_spu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-#define reg_iop_sw_spu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_spu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_gio_in_offset 80
-
-/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
-
-/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
-
-/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
-
-/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
-
-/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
-
-/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
-
-/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
-
-/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_cpu_intr_offset 148
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_cpu_intr_offset 152
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
-#define reg_iop_sw_spu_r_hw_intr_offset 156
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_mpu_intr_offset 160
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
-#define reg_iop_sw_spu_r_mpu_intr_offset 164
-
-
-/* Constants */
-#define regk_iop_sw_spu_copy 0x00000000
-#define regk_iop_sw_spu_no 0x00000000
-#define regk_iop_sw_spu_nop 0x00000000
-#define regk_iop_sw_spu_rd 0x00000002
-#define regk_iop_sw_spu_reg_copy 0x00000001
-#define regk_iop_sw_spu_rw_bus0_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus0_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus1_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_spu_set 0x00000001
-#define regk_iop_sw_spu_wr 0x00000003
-#define regk_iop_sw_spu_yes 0x00000001
-#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h
deleted file mode 100644
index 4f1cf73d86cd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_timer_grp_defs_asm_h
-#define __iop_timer_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
-#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
-#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
-#define reg_iop_timer_grp_rw_cfg___trig___width 2
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
-#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
-#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
-#define reg_iop_timer_grp_rw_cfg_offset 0
-
-/* Register rw_half_period, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
-#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
-#define reg_iop_timer_grp_rw_half_period_offset 4
-
-/* Register rw_half_period_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period_len_offset 8
-
-#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
-/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
-#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
-
-#define STRIDE_iop_timer_grp_rw_tmr_len 4
-/* Register rw_tmr_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
-#define reg_iop_timer_grp_rw_tmr_len___val___width 16
-#define reg_iop_timer_grp_rw_tmr_len_offset 44
-
-/* Register rw_cmd, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
-#define reg_iop_timer_grp_rw_cmd___rst___width 4
-#define reg_iop_timer_grp_rw_cmd___en___lsb 4
-#define reg_iop_timer_grp_rw_cmd___en___width 4
-#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
-#define reg_iop_timer_grp_rw_cmd___dis___width 4
-#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
-#define reg_iop_timer_grp_rw_cmd___strb___width 4
-#define reg_iop_timer_grp_rw_cmd_offset 60
-
-/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
-
-#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
-/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
-#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
-
-#define STRIDE_iop_timer_grp_r_tmr_cnt 8
-/* Register r_tmr_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_r_tmr_cnt_offset 72
-
-/* Register rw_intr_mask, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
-#define reg_iop_timer_grp_rw_intr_mask_offset 100
-
-/* Register rw_ack_intr, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
-#define reg_iop_timer_grp_rw_ack_intr_offset 104
-
-/* Register r_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_intr_offset 108
-
-/* Register r_masked_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_masked_intr_offset 112
-
-
-/* Constants */
-#define regk_iop_timer_grp_clk200 0x00000000
-#define regk_iop_timer_grp_clk_gen 0x00000002
-#define regk_iop_timer_grp_complete 0x00000002
-#define regk_iop_timer_grp_div_clk200 0x00000001
-#define regk_iop_timer_grp_div_clk_gen 0x00000003
-#define regk_iop_timer_grp_ext 0x00000001
-#define regk_iop_timer_grp_hi 0x00000000
-#define regk_iop_timer_grp_long_period 0x00000001
-#define regk_iop_timer_grp_neg 0x00000002
-#define regk_iop_timer_grp_no 0x00000000
-#define regk_iop_timer_grp_once 0x00000003
-#define regk_iop_timer_grp_pause 0x00000001
-#define regk_iop_timer_grp_pos 0x00000001
-#define regk_iop_timer_grp_pos_neg 0x00000003
-#define regk_iop_timer_grp_pulse 0x00000000
-#define regk_iop_timer_grp_r_tmr_cnt_size 0x00000004
-#define regk_iop_timer_grp_rs_tmr_cnt_size 0x00000004
-#define regk_iop_timer_grp_rw_cfg_default 0x00000002
-#define regk_iop_timer_grp_rw_intr_mask_default 0x00000000
-#define regk_iop_timer_grp_rw_tmr_cfg_default0 0x00018000
-#define regk_iop_timer_grp_rw_tmr_cfg_default1 0x0001a900
-#define regk_iop_timer_grp_rw_tmr_cfg_default2 0x0001d200
-#define regk_iop_timer_grp_rw_tmr_cfg_default3 0x0001fb00
-#define regk_iop_timer_grp_rw_tmr_cfg_size 0x00000004
-#define regk_iop_timer_grp_rw_tmr_len_default 0x00000000
-#define regk_iop_timer_grp_rw_tmr_len_size 0x00000004
-#define regk_iop_timer_grp_short_period 0x00000000
-#define regk_iop_timer_grp_stop 0x00000000
-#define regk_iop_timer_grp_tmr 0x00000004
-#define regk_iop_timer_grp_toggle 0x00000001
-#define regk_iop_timer_grp_yes 0x00000001
-#endif /* __iop_timer_grp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
deleted file mode 100644
index 7bc882c62952..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_trigger_grp_defs_asm_h
-#define __iop_trigger_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_trigger_grp_rw_cfg 4
-/* Register rw_cfg, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
-#define reg_iop_trigger_grp_rw_cfg___action___width 2
-#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
-#define reg_iop_trigger_grp_rw_cfg___once___width 1
-#define reg_iop_trigger_grp_rw_cfg___once___bit 2
-#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
-#define reg_iop_trigger_grp_rw_cfg___trig___width 3
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
-#define reg_iop_trigger_grp_rw_cfg_offset 0
-
-/* Register rw_cmd, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
-#define reg_iop_trigger_grp_rw_cmd___dis___width 4
-#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
-#define reg_iop_trigger_grp_rw_cmd___en___width 4
-#define reg_iop_trigger_grp_rw_cmd_offset 16
-
-/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
-#define reg_iop_trigger_grp_rw_intr_mask_offset 20
-
-/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
-#define reg_iop_trigger_grp_rw_ack_intr_offset 24
-
-/* Register r_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_intr_offset 28
-
-/* Register r_masked_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_masked_intr_offset 32
-
-
-/* Constants */
-#define regk_iop_trigger_grp_fall 0x00000002
-#define regk_iop_trigger_grp_fall_lo 0x00000006
-#define regk_iop_trigger_grp_no 0x00000000
-#define regk_iop_trigger_grp_off 0x00000000
-#define regk_iop_trigger_grp_pulse 0x00000000
-#define regk_iop_trigger_grp_rise 0x00000001
-#define regk_iop_trigger_grp_rise_fall 0x00000003
-#define regk_iop_trigger_grp_rise_fall_hi 0x00000007
-#define regk_iop_trigger_grp_rise_fall_lo 0x00000004
-#define regk_iop_trigger_grp_rise_hi 0x00000005
-#define regk_iop_trigger_grp_rw_cfg_default 0x000000c0
-#define regk_iop_trigger_grp_rw_cfg_size 0x00000004
-#define regk_iop_trigger_grp_rw_intr_mask_default 0x00000000
-#define regk_iop_trigger_grp_toggle 0x00000003
-#define regk_iop_trigger_grp_yes 0x00000001
-#endif /* __iop_trigger_grp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h
deleted file mode 100644
index 2e239957e34a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_asm_h
-#define __iop_version_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
- * last modfied: Mon Apr 11 16:08:44 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_version, scope iop_version, type r */
-#define reg_iop_version_r_version___nr___lsb 0
-#define reg_iop_version_r_version___nr___width 8
-#define reg_iop_version_r_version_offset 0
-
-
-/* Constants */
-#define regk_iop_version_v1_0 0x00000001
-#endif /* __iop_version_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h
deleted file mode 100644
index 8690034d9bec..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_crc_par_defs.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_crc_par_defs_h
-#define __iop_crc_par_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_crc_par.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_crc_par_defs.h ../../inst/io_proc/rtl/iop_crc_par.r
- * id: $Id: iop_crc_par_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_crc_par */
-
-/* Register rw_cfg, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int mode : 1;
- unsigned int crc_out : 1;
- unsigned int rev_out : 1;
- unsigned int inv_out : 1;
- unsigned int trig : 2;
- unsigned int poly : 3;
- unsigned int dummy1 : 23;
-} reg_iop_crc_par_rw_cfg;
-#define REG_RD_ADDR_iop_crc_par_rw_cfg 0
-#define REG_WR_ADDR_iop_crc_par_rw_cfg 0
-
-/* Register rw_init_crc, scope iop_crc_par, type rw */
-typedef unsigned int reg_iop_crc_par_rw_init_crc;
-#define REG_RD_ADDR_iop_crc_par_rw_init_crc 4
-#define REG_WR_ADDR_iop_crc_par_rw_init_crc 4
-
-/* Register rw_correct_crc, scope iop_crc_par, type rw */
-typedef unsigned int reg_iop_crc_par_rw_correct_crc;
-#define REG_RD_ADDR_iop_crc_par_rw_correct_crc 8
-#define REG_WR_ADDR_iop_crc_par_rw_correct_crc 8
-
-/* Register rw_ctrl, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_crc_par_rw_ctrl;
-#define REG_RD_ADDR_iop_crc_par_rw_ctrl 12
-#define REG_WR_ADDR_iop_crc_par_rw_ctrl 12
-
-/* Register rw_set_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int tr_dif : 1;
- unsigned int dummy1 : 31;
-} reg_iop_crc_par_rw_set_last;
-#define REG_RD_ADDR_iop_crc_par_rw_set_last 16
-#define REG_WR_ADDR_iop_crc_par_rw_set_last 16
-
-/* Register rw_wr1byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_crc_par_rw_wr1byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr1byte 20
-#define REG_WR_ADDR_iop_crc_par_rw_wr1byte 20
-
-/* Register rw_wr2byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_crc_par_rw_wr2byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr2byte 24
-#define REG_WR_ADDR_iop_crc_par_rw_wr2byte 24
-
-/* Register rw_wr3byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_crc_par_rw_wr3byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr3byte 28
-#define REG_WR_ADDR_iop_crc_par_rw_wr3byte 28
-
-/* Register rw_wr4byte, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_crc_par_rw_wr4byte;
-#define REG_RD_ADDR_iop_crc_par_rw_wr4byte 32
-#define REG_WR_ADDR_iop_crc_par_rw_wr4byte 32
-
-/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_crc_par_rw_wr1byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr1byte_last 36
-#define REG_WR_ADDR_iop_crc_par_rw_wr1byte_last 36
-
-/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_crc_par_rw_wr2byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr2byte_last 40
-#define REG_WR_ADDR_iop_crc_par_rw_wr2byte_last 40
-
-/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_crc_par_rw_wr3byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr3byte_last 44
-#define REG_WR_ADDR_iop_crc_par_rw_wr3byte_last 44
-
-/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_crc_par_rw_wr4byte_last;
-#define REG_RD_ADDR_iop_crc_par_rw_wr4byte_last 48
-#define REG_WR_ADDR_iop_crc_par_rw_wr4byte_last 48
-
-/* Register r_stat, scope iop_crc_par, type r */
-typedef struct {
- unsigned int err : 1;
- unsigned int busy : 1;
- unsigned int dummy1 : 30;
-} reg_iop_crc_par_r_stat;
-#define REG_RD_ADDR_iop_crc_par_r_stat 52
-
-/* Register r_sh_reg, scope iop_crc_par, type r */
-typedef unsigned int reg_iop_crc_par_r_sh_reg;
-#define REG_RD_ADDR_iop_crc_par_r_sh_reg 56
-
-/* Register r_crc, scope iop_crc_par, type r */
-typedef unsigned int reg_iop_crc_par_r_crc;
-#define REG_RD_ADDR_iop_crc_par_r_crc 60
-
-/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
-typedef struct {
- unsigned int last : 2;
- unsigned int dummy1 : 30;
-} reg_iop_crc_par_rw_strb_rec_dif_in;
-#define REG_RD_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
-#define REG_WR_ADDR_iop_crc_par_rw_strb_rec_dif_in 64
-
-
-/* Constants */
-enum {
- regk_iop_crc_par_calc = 0x00000001,
- regk_iop_crc_par_ccitt = 0x00000002,
- regk_iop_crc_par_check = 0x00000000,
- regk_iop_crc_par_crc16 = 0x00000001,
- regk_iop_crc_par_crc32 = 0x00000000,
- regk_iop_crc_par_crc5 = 0x00000003,
- regk_iop_crc_par_crc5_11 = 0x00000004,
- regk_iop_crc_par_dif_in = 0x00000002,
- regk_iop_crc_par_hi = 0x00000000,
- regk_iop_crc_par_neg = 0x00000002,
- regk_iop_crc_par_no = 0x00000000,
- regk_iop_crc_par_pos = 0x00000001,
- regk_iop_crc_par_pos_neg = 0x00000003,
- regk_iop_crc_par_rw_cfg_default = 0x00000000,
- regk_iop_crc_par_rw_ctrl_default = 0x00000000,
- regk_iop_crc_par_yes = 0x00000001
-};
-#endif /* __iop_crc_par_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h
deleted file mode 100644
index 3dd4e870a3a5..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_in_defs.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_in_defs_h
-#define __iop_dmc_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_in_defs.h ../../inst/io_proc/rtl/iop_dmc_in.r
- * id: $Id: iop_dmc_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_dmc_in */
-
-/* Register rw_cfg, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int sth_intr : 3;
- unsigned int last_dis_dif : 1;
- unsigned int dummy1 : 28;
-} reg_iop_dmc_in_rw_cfg;
-#define REG_RD_ADDR_iop_dmc_in_rw_cfg 0
-#define REG_WR_ADDR_iop_dmc_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dif_dis : 1;
- unsigned int stream_clr : 1;
- unsigned int dummy1 : 29;
-} reg_iop_dmc_in_rw_ctrl;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_dmc_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_dmc_in_r_stat;
-#define REG_RD_ADDR_iop_dmc_in_r_stat 8
-
-/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int cmd : 10;
- unsigned int dummy1 : 6;
- unsigned int n : 8;
- unsigned int dummy2 : 8;
-} reg_iop_dmc_in_rw_stream_cmd;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_cmd 12
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_cmd 12
-
-/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data 16
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data 16
-
-/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_stream_wr_data_last;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_wr_data_last 20
-
-/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int eop : 1;
- unsigned int wait : 1;
- unsigned int keep_md : 1;
- unsigned int size : 3;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_rw_stream_ctrl;
-#define REG_RD_ADDR_iop_dmc_in_rw_stream_ctrl 24
-#define REG_WR_ADDR_iop_dmc_in_rw_stream_ctrl 24
-
-/* Register r_stream_stat, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int sth : 7;
- unsigned int dummy1 : 9;
- unsigned int full : 1;
- unsigned int last_pkt : 1;
- unsigned int data_md_valid : 1;
- unsigned int ctxt_md_valid : 1;
- unsigned int group_md_valid : 1;
- unsigned int stream_busy : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dummy2 : 9;
-} reg_iop_dmc_in_r_stream_stat;
-#define REG_RD_ADDR_iop_dmc_in_r_stream_stat 28
-
-/* Register r_data_descr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_in_r_data_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_data_descr 32
-
-/* Register r_ctxt_descr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md0 : 16;
-} reg_iop_dmc_in_r_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr 36
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
-typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md1 40
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
-typedef unsigned int reg_iop_dmc_in_r_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_in_r_ctxt_descr_md2 44
-
-/* Register r_group_descr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_in_r_group_descr;
-#define REG_RD_ADDR_iop_dmc_in_r_group_descr 56
-
-/* Register rw_data_descr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_in_rw_data_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_data_descr 60
-#define REG_WR_ADDR_iop_dmc_in_rw_data_descr 60
-
-/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md0 : 16;
-} reg_iop_dmc_in_rw_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr 64
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr 64
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md1 68
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
-typedef unsigned int reg_iop_dmc_in_rw_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
-#define REG_WR_ADDR_iop_dmc_in_rw_ctxt_descr_md2 72
-
-/* Register rw_group_descr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_in_rw_group_descr;
-#define REG_RD_ADDR_iop_dmc_in_rw_group_descr 84
-#define REG_WR_ADDR_iop_dmc_in_rw_group_descr 84
-
-/* Register rw_intr_mask, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_rw_intr_mask;
-#define REG_RD_ADDR_iop_dmc_in_rw_intr_mask 88
-#define REG_WR_ADDR_iop_dmc_in_rw_intr_mask 88
-
-/* Register rw_ack_intr, scope iop_dmc_in, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_rw_ack_intr;
-#define REG_RD_ADDR_iop_dmc_in_rw_ack_intr 92
-#define REG_WR_ADDR_iop_dmc_in_rw_ack_intr 92
-
-/* Register r_intr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_r_intr;
-#define REG_RD_ADDR_iop_dmc_in_r_intr 96
-
-/* Register r_masked_intr, scope iop_dmc_in, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int sth : 1;
- unsigned int full : 1;
- unsigned int dummy1 : 26;
-} reg_iop_dmc_in_r_masked_intr;
-#define REG_RD_ADDR_iop_dmc_in_r_masked_intr 100
-
-
-/* Constants */
-enum {
- regk_iop_dmc_in_ack_pkt = 0x00000100,
- regk_iop_dmc_in_array = 0x00000008,
- regk_iop_dmc_in_burst = 0x00000020,
- regk_iop_dmc_in_copy_next = 0x00000010,
- regk_iop_dmc_in_copy_up = 0x00000020,
- regk_iop_dmc_in_dis_c = 0x00000010,
- regk_iop_dmc_in_dis_g = 0x00000020,
- regk_iop_dmc_in_lim1 = 0x00000000,
- regk_iop_dmc_in_lim16 = 0x00000004,
- regk_iop_dmc_in_lim2 = 0x00000001,
- regk_iop_dmc_in_lim32 = 0x00000005,
- regk_iop_dmc_in_lim4 = 0x00000002,
- regk_iop_dmc_in_lim64 = 0x00000006,
- regk_iop_dmc_in_lim8 = 0x00000003,
- regk_iop_dmc_in_load_c = 0x00000200,
- regk_iop_dmc_in_load_c_n = 0x00000280,
- regk_iop_dmc_in_load_c_next = 0x00000240,
- regk_iop_dmc_in_load_d = 0x00000140,
- regk_iop_dmc_in_load_g = 0x00000300,
- regk_iop_dmc_in_load_g_down = 0x000003c0,
- regk_iop_dmc_in_load_g_next = 0x00000340,
- regk_iop_dmc_in_load_g_up = 0x00000380,
- regk_iop_dmc_in_next_en = 0x00000010,
- regk_iop_dmc_in_next_pkt = 0x00000010,
- regk_iop_dmc_in_no = 0x00000000,
- regk_iop_dmc_in_restore = 0x00000020,
- regk_iop_dmc_in_rw_cfg_default = 0x00000000,
- regk_iop_dmc_in_rw_ctxt_descr_default = 0x00000000,
- regk_iop_dmc_in_rw_ctxt_descr_md1_default = 0x00000000,
- regk_iop_dmc_in_rw_ctxt_descr_md2_default = 0x00000000,
- regk_iop_dmc_in_rw_data_descr_default = 0x00000000,
- regk_iop_dmc_in_rw_group_descr_default = 0x00000000,
- regk_iop_dmc_in_rw_intr_mask_default = 0x00000000,
- regk_iop_dmc_in_rw_stream_ctrl_default = 0x00000000,
- regk_iop_dmc_in_save_down = 0x00000020,
- regk_iop_dmc_in_save_up = 0x00000020,
- regk_iop_dmc_in_set_reg = 0x00000050,
- regk_iop_dmc_in_set_w_size1 = 0x00000190,
- regk_iop_dmc_in_set_w_size2 = 0x000001a0,
- regk_iop_dmc_in_set_w_size4 = 0x000001c0,
- regk_iop_dmc_in_store_c = 0x00000002,
- regk_iop_dmc_in_store_descr = 0x00000000,
- regk_iop_dmc_in_store_g = 0x00000004,
- regk_iop_dmc_in_store_md = 0x00000001,
- regk_iop_dmc_in_update_down = 0x00000020,
- regk_iop_dmc_in_yes = 0x00000001
-};
-#endif /* __iop_dmc_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h
deleted file mode 100644
index 7ed17bc553c3..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_dmc_out_defs.h
+++ /dev/null
@@ -1,327 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_out_defs_h
-#define __iop_dmc_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_dmc_out_defs.h ../../inst/io_proc/rtl/iop_dmc_out.r
- * id: $Id: iop_dmc_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_dmc_out */
-
-/* Register rw_cfg, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int trf_lim : 16;
- unsigned int last_at_trf_lim : 1;
- unsigned int dth_intr : 3;
- unsigned int dummy1 : 12;
-} reg_iop_dmc_out_rw_cfg;
-#define REG_RD_ADDR_iop_dmc_out_rw_cfg 0
-#define REG_WR_ADDR_iop_dmc_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dif_dis : 1;
- unsigned int dummy1 : 30;
-} reg_iop_dmc_out_rw_ctrl;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_dmc_out_rw_ctrl 4
-
-/* Register r_stat, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int dif_en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_dmc_out_r_stat;
-#define REG_RD_ADDR_iop_dmc_out_r_stat 8
-
-/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int cmd : 10;
- unsigned int dummy1 : 6;
- unsigned int n : 8;
- unsigned int dummy2 : 8;
-} reg_iop_dmc_out_rw_stream_cmd;
-#define REG_RD_ADDR_iop_dmc_out_rw_stream_cmd 12
-#define REG_WR_ADDR_iop_dmc_out_rw_stream_cmd 12
-
-/* Register rs_stream_data, scope iop_dmc_out, type rs */
-typedef unsigned int reg_iop_dmc_out_rs_stream_data;
-#define REG_RD_ADDR_iop_dmc_out_rs_stream_data 16
-
-/* Register r_stream_data, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_stream_data;
-#define REG_RD_ADDR_iop_dmc_out_r_stream_data 20
-
-/* Register r_stream_stat, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int dth : 7;
- unsigned int dummy1 : 9;
- unsigned int dv : 1;
- unsigned int all_avail : 1;
- unsigned int last : 1;
- unsigned int size : 3;
- unsigned int data_md_valid : 1;
- unsigned int ctxt_md_valid : 1;
- unsigned int group_md_valid : 1;
- unsigned int stream_busy : 1;
- unsigned int cmd_rdy : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy2 : 4;
-} reg_iop_dmc_out_r_stream_stat;
-#define REG_RD_ADDR_iop_dmc_out_r_stream_stat 24
-
-/* Register r_data_descr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_out_r_data_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_data_descr 28
-
-/* Register r_ctxt_descr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md0 : 16;
-} reg_iop_dmc_out_r_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr 32
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md1 36
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
-typedef unsigned int reg_iop_dmc_out_r_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_out_r_ctxt_descr_md2 40
-
-/* Register r_group_descr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int ctrl : 8;
- unsigned int stat : 8;
- unsigned int md : 16;
-} reg_iop_dmc_out_r_group_descr;
-#define REG_RD_ADDR_iop_dmc_out_r_group_descr 52
-
-/* Register rw_data_descr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_out_rw_data_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_data_descr 56
-#define REG_WR_ADDR_iop_dmc_out_rw_data_descr 56
-
-/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md0 : 16;
-} reg_iop_dmc_out_rw_ctxt_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr 60
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr 60
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
-typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md1;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md1 64
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
-typedef unsigned int reg_iop_dmc_out_rw_ctxt_descr_md2;
-#define REG_RD_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
-#define REG_WR_ADDR_iop_dmc_out_rw_ctxt_descr_md2 68
-
-/* Register rw_group_descr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int dummy1 : 16;
- unsigned int md : 16;
-} reg_iop_dmc_out_rw_group_descr;
-#define REG_RD_ADDR_iop_dmc_out_rw_group_descr 80
-#define REG_WR_ADDR_iop_dmc_out_rw_group_descr 80
-
-/* Register rw_intr_mask, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_rw_intr_mask;
-#define REG_RD_ADDR_iop_dmc_out_rw_intr_mask 84
-#define REG_WR_ADDR_iop_dmc_out_rw_intr_mask 84
-
-/* Register rw_ack_intr, scope iop_dmc_out, type rw */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_rw_ack_intr;
-#define REG_RD_ADDR_iop_dmc_out_rw_ack_intr 88
-#define REG_WR_ADDR_iop_dmc_out_rw_ack_intr 88
-
-/* Register r_intr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_r_intr;
-#define REG_RD_ADDR_iop_dmc_out_r_intr 92
-
-/* Register r_masked_intr, scope iop_dmc_out, type r */
-typedef struct {
- unsigned int data_md : 1;
- unsigned int ctxt_md : 1;
- unsigned int group_md : 1;
- unsigned int cmd_rdy : 1;
- unsigned int dth : 1;
- unsigned int dv : 1;
- unsigned int last_data : 1;
- unsigned int trf_lim : 1;
- unsigned int cmd_rq : 1;
- unsigned int dummy1 : 23;
-} reg_iop_dmc_out_r_masked_intr;
-#define REG_RD_ADDR_iop_dmc_out_r_masked_intr 96
-
-
-/* Constants */
-enum {
- regk_iop_dmc_out_ack_pkt = 0x00000100,
- regk_iop_dmc_out_array = 0x00000008,
- regk_iop_dmc_out_burst = 0x00000020,
- regk_iop_dmc_out_copy_next = 0x00000010,
- regk_iop_dmc_out_copy_up = 0x00000020,
- regk_iop_dmc_out_dis_c = 0x00000010,
- regk_iop_dmc_out_dis_g = 0x00000020,
- regk_iop_dmc_out_lim1 = 0x00000000,
- regk_iop_dmc_out_lim16 = 0x00000004,
- regk_iop_dmc_out_lim2 = 0x00000001,
- regk_iop_dmc_out_lim32 = 0x00000005,
- regk_iop_dmc_out_lim4 = 0x00000002,
- regk_iop_dmc_out_lim64 = 0x00000006,
- regk_iop_dmc_out_lim8 = 0x00000003,
- regk_iop_dmc_out_load_c = 0x00000200,
- regk_iop_dmc_out_load_c_n = 0x00000280,
- regk_iop_dmc_out_load_c_next = 0x00000240,
- regk_iop_dmc_out_load_d = 0x00000140,
- regk_iop_dmc_out_load_g = 0x00000300,
- regk_iop_dmc_out_load_g_down = 0x000003c0,
- regk_iop_dmc_out_load_g_next = 0x00000340,
- regk_iop_dmc_out_load_g_up = 0x00000380,
- regk_iop_dmc_out_next_en = 0x00000010,
- regk_iop_dmc_out_next_pkt = 0x00000010,
- regk_iop_dmc_out_no = 0x00000000,
- regk_iop_dmc_out_restore = 0x00000020,
- regk_iop_dmc_out_rw_cfg_default = 0x00000000,
- regk_iop_dmc_out_rw_ctxt_descr_default = 0x00000000,
- regk_iop_dmc_out_rw_ctxt_descr_md1_default = 0x00000000,
- regk_iop_dmc_out_rw_ctxt_descr_md2_default = 0x00000000,
- regk_iop_dmc_out_rw_data_descr_default = 0x00000000,
- regk_iop_dmc_out_rw_group_descr_default = 0x00000000,
- regk_iop_dmc_out_rw_intr_mask_default = 0x00000000,
- regk_iop_dmc_out_save_down = 0x00000020,
- regk_iop_dmc_out_save_up = 0x00000020,
- regk_iop_dmc_out_set_reg = 0x00000050,
- regk_iop_dmc_out_set_w_size1 = 0x00000190,
- regk_iop_dmc_out_set_w_size2 = 0x000001a0,
- regk_iop_dmc_out_set_w_size4 = 0x000001c0,
- regk_iop_dmc_out_store_c = 0x00000002,
- regk_iop_dmc_out_store_descr = 0x00000000,
- regk_iop_dmc_out_store_g = 0x00000004,
- regk_iop_dmc_out_store_md = 0x00000001,
- regk_iop_dmc_out_update_down = 0x00000020,
- regk_iop_dmc_out_yes = 0x00000001
-};
-#endif /* __iop_dmc_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h
deleted file mode 100644
index dc14868680e6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_defs.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_defs_h
-#define __iop_fifo_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:07 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_defs.h ../../inst/io_proc/rtl/iop_fifo_in.r
- * id: $Id: iop_fifo_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_in */
-
-/* Register rw_cfg, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int avail_lim : 3;
- unsigned int byte_order : 2;
- unsigned int trig : 2;
- unsigned int last_dis_dif_in : 1;
- unsigned int mode : 2;
- unsigned int dummy1 : 22;
-} reg_iop_fifo_in_rw_cfg;
-#define REG_RD_ADDR_iop_fifo_in_rw_cfg 0
-#define REG_WR_ADDR_iop_fifo_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_in_rw_ctrl;
-#define REG_RD_ADDR_iop_fifo_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_fifo_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 18;
-} reg_iop_fifo_in_r_stat;
-#define REG_RD_ADDR_iop_fifo_in_r_stat 8
-
-/* Register rs_rd1byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_in_rs_rd1byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd1byte 12
-
-/* Register r_rd1byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_in_r_rd1byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd1byte 16
-
-/* Register rs_rd2byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_in_rs_rd2byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd2byte 20
-
-/* Register r_rd2byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_in_r_rd2byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd2byte 24
-
-/* Register rs_rd3byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_in_rs_rd3byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd3byte 28
-
-/* Register r_rd3byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_in_r_rd3byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd3byte 32
-
-/* Register rs_rd4byte, scope iop_fifo_in, type rs */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_in_rs_rd4byte;
-#define REG_RD_ADDR_iop_fifo_in_rs_rd4byte 36
-
-/* Register r_rd4byte, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_in_r_rd4byte;
-#define REG_RD_ADDR_iop_fifo_in_r_rd4byte 40
-
-/* Register rw_set_last, scope iop_fifo_in, type rw */
-typedef unsigned int reg_iop_fifo_in_rw_set_last;
-#define REG_RD_ADDR_iop_fifo_in_rw_set_last 44
-#define REG_WR_ADDR_iop_fifo_in_rw_set_last 44
-
-/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int last : 2;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_in_rw_strb_dif_in;
-#define REG_RD_ADDR_iop_fifo_in_rw_strb_dif_in 48
-#define REG_WR_ADDR_iop_fifo_in_rw_strb_dif_in 48
-
-/* Register rw_intr_mask, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_in_rw_intr_mask 52
-#define REG_WR_ADDR_iop_fifo_in_rw_intr_mask 52
-
-/* Register rw_ack_intr, scope iop_fifo_in, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_in_rw_ack_intr 56
-#define REG_WR_ADDR_iop_fifo_in_rw_ack_intr 56
-
-/* Register r_intr, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_r_intr;
-#define REG_RD_ADDR_iop_fifo_in_r_intr 60
-
-/* Register r_masked_intr, scope iop_fifo_in, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_in_r_masked_intr 64
-
-
-/* Constants */
-enum {
- regk_iop_fifo_in_dif_in = 0x00000002,
- regk_iop_fifo_in_hi = 0x00000000,
- regk_iop_fifo_in_neg = 0x00000002,
- regk_iop_fifo_in_no = 0x00000000,
- regk_iop_fifo_in_order16 = 0x00000001,
- regk_iop_fifo_in_order24 = 0x00000002,
- regk_iop_fifo_in_order32 = 0x00000003,
- regk_iop_fifo_in_order8 = 0x00000000,
- regk_iop_fifo_in_pos = 0x00000001,
- regk_iop_fifo_in_pos_neg = 0x00000003,
- regk_iop_fifo_in_rw_cfg_default = 0x00000024,
- regk_iop_fifo_in_rw_ctrl_default = 0x00000000,
- regk_iop_fifo_in_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_in_rw_set_last_default = 0x00000000,
- regk_iop_fifo_in_rw_strb_dif_in_default = 0x00000000,
- regk_iop_fifo_in_size16 = 0x00000002,
- regk_iop_fifo_in_size24 = 0x00000001,
- regk_iop_fifo_in_size32 = 0x00000000,
- regk_iop_fifo_in_size8 = 0x00000003,
- regk_iop_fifo_in_yes = 0x00000001
-};
-#endif /* __iop_fifo_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h
deleted file mode 100644
index ee7dc07a7862..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_in_extra_defs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_extra_defs_h
-#define __iop_fifo_in_extra_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:08 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_in_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- * id: $Id: iop_fifo_in_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_in_extra */
-
-/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
-typedef unsigned int reg_iop_fifo_in_extra_rw_wr_data;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_wr_data 0
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_wr_data 0
-
-/* Register r_stat, scope iop_fifo_in_extra, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 18;
-} reg_iop_fifo_in_extra_r_stat;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_stat 4
-
-/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
-typedef struct {
- unsigned int last : 2;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_in_extra_rw_strb_dif_in;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_strb_dif_in 8
-
-/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_intr_mask 12
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_intr_mask 12
-
-/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_rw_ack_intr 16
-#define REG_WR_ADDR_iop_fifo_in_extra_rw_ack_intr 16
-
-/* Register r_intr, scope iop_fifo_in_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_r_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_intr 20
-
-/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int avail : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_in_extra_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_in_extra_r_masked_intr 24
-
-
-/* Constants */
-enum {
- regk_iop_fifo_in_extra_fifo_in = 0x00000002,
- regk_iop_fifo_in_extra_no = 0x00000000,
- regk_iop_fifo_in_extra_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_in_extra_yes = 0x00000001
-};
-#endif /* __iop_fifo_in_extra_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h
deleted file mode 100644
index ee8194fcfa82..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_defs.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_defs_h
-#define __iop_fifo_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:09 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_defs.h ../../inst/io_proc/rtl/iop_fifo_out.r
- * id: $Id: iop_fifo_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_out */
-
-/* Register rw_cfg, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int free_lim : 3;
- unsigned int byte_order : 2;
- unsigned int trig : 2;
- unsigned int last_dis_dif_in : 1;
- unsigned int mode : 2;
- unsigned int delay_out_last : 1;
- unsigned int last_dis_dif_out : 1;
- unsigned int dummy1 : 20;
-} reg_iop_fifo_out_rw_cfg;
-#define REG_RD_ADDR_iop_fifo_out_rw_cfg 0
-#define REG_WR_ADDR_iop_fifo_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int dummy1 : 30;
-} reg_iop_fifo_out_rw_ctrl;
-#define REG_RD_ADDR_iop_fifo_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_fifo_out_rw_ctrl 4
-
-/* Register r_stat, scope iop_fifo_out, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int zero_data_last : 1;
- unsigned int dummy1 : 17;
-} reg_iop_fifo_out_r_stat;
-#define REG_RD_ADDR_iop_fifo_out_r_stat 8
-
-/* Register rw_wr1byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_out_rw_wr1byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte 12
-#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte 12
-
-/* Register rw_wr2byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_out_rw_wr2byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte 16
-#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte 16
-
-/* Register rw_wr3byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_out_rw_wr3byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte 20
-#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte 20
-
-/* Register rw_wr4byte, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_out_rw_wr4byte;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte 24
-#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte 24
-
-/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_iop_fifo_out_rw_wr1byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr1byte_last 28
-#define REG_WR_ADDR_iop_fifo_out_rw_wr1byte_last 28
-
-/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_iop_fifo_out_rw_wr2byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr2byte_last 32
-#define REG_WR_ADDR_iop_fifo_out_rw_wr2byte_last 32
-
-/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 24;
- unsigned int dummy1 : 8;
-} reg_iop_fifo_out_rw_wr3byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr3byte_last 36
-#define REG_WR_ADDR_iop_fifo_out_rw_wr3byte_last 36
-
-/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_iop_fifo_out_rw_wr4byte_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_wr4byte_last 40
-#define REG_WR_ADDR_iop_fifo_out_rw_wr4byte_last 40
-
-/* Register rw_set_last, scope iop_fifo_out, type rw */
-typedef unsigned int reg_iop_fifo_out_rw_set_last;
-#define REG_RD_ADDR_iop_fifo_out_rw_set_last 44
-#define REG_WR_ADDR_iop_fifo_out_rw_set_last 44
-
-/* Register rs_rd_data, scope iop_fifo_out, type rs */
-typedef unsigned int reg_iop_fifo_out_rs_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_rs_rd_data 48
-
-/* Register r_rd_data, scope iop_fifo_out, type r */
-typedef unsigned int reg_iop_fifo_out_r_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_r_rd_data 52
-
-/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
-typedef unsigned int reg_iop_fifo_out_rw_strb_dif_out;
-#define REG_RD_ADDR_iop_fifo_out_rw_strb_dif_out 56
-#define REG_WR_ADDR_iop_fifo_out_rw_strb_dif_out 56
-
-/* Register rw_intr_mask, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_out_rw_intr_mask 60
-#define REG_WR_ADDR_iop_fifo_out_rw_intr_mask 60
-
-/* Register rw_ack_intr, scope iop_fifo_out, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_out_rw_ack_intr 64
-#define REG_WR_ADDR_iop_fifo_out_rw_ack_intr 64
-
-/* Register r_intr, scope iop_fifo_out, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_r_intr;
-#define REG_RD_ADDR_iop_fifo_out_r_intr 68
-
-/* Register r_masked_intr, scope iop_fifo_out, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_out_r_masked_intr 72
-
-
-/* Constants */
-enum {
- regk_iop_fifo_out_hi = 0x00000000,
- regk_iop_fifo_out_neg = 0x00000002,
- regk_iop_fifo_out_no = 0x00000000,
- regk_iop_fifo_out_order16 = 0x00000001,
- regk_iop_fifo_out_order24 = 0x00000002,
- regk_iop_fifo_out_order32 = 0x00000003,
- regk_iop_fifo_out_order8 = 0x00000000,
- regk_iop_fifo_out_pos = 0x00000001,
- regk_iop_fifo_out_pos_neg = 0x00000003,
- regk_iop_fifo_out_rw_cfg_default = 0x00000024,
- regk_iop_fifo_out_rw_ctrl_default = 0x00000000,
- regk_iop_fifo_out_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_out_rw_set_last_default = 0x00000000,
- regk_iop_fifo_out_rw_strb_dif_out_default = 0x00000000,
- regk_iop_fifo_out_rw_wr1byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr1byte_last_default = 0x00000000,
- regk_iop_fifo_out_rw_wr2byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr2byte_last_default = 0x00000000,
- regk_iop_fifo_out_rw_wr3byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr3byte_last_default = 0x00000000,
- regk_iop_fifo_out_rw_wr4byte_default = 0x00000000,
- regk_iop_fifo_out_rw_wr4byte_last_default = 0x00000000,
- regk_iop_fifo_out_size16 = 0x00000002,
- regk_iop_fifo_out_size24 = 0x00000001,
- regk_iop_fifo_out_size32 = 0x00000000,
- regk_iop_fifo_out_size8 = 0x00000003,
- regk_iop_fifo_out_yes = 0x00000001
-};
-#endif /* __iop_fifo_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h
deleted file mode 100644
index b9721649f6fd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_fifo_out_extra_defs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_extra_defs_h
-#define __iop_fifo_out_extra_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:10 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_fifo_out_extra_defs.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- * id: $Id: iop_fifo_out_extra_defs.h,v 1.1 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_fifo_out_extra */
-
-/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
-typedef unsigned int reg_iop_fifo_out_extra_rs_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_extra_rs_rd_data 0
-
-/* Register r_rd_data, scope iop_fifo_out_extra, type r */
-typedef unsigned int reg_iop_fifo_out_extra_r_rd_data;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_rd_data 4
-
-/* Register r_stat, scope iop_fifo_out_extra, type r */
-typedef struct {
- unsigned int avail_bytes : 4;
- unsigned int last : 8;
- unsigned int dif_in_en : 1;
- unsigned int dif_out_en : 1;
- unsigned int zero_data_last : 1;
- unsigned int dummy1 : 17;
-} reg_iop_fifo_out_extra_r_stat;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_stat 8
-
-/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
-typedef unsigned int reg_iop_fifo_out_extra_rw_strb_dif_out;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_strb_dif_out 12
-
-/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_rw_intr_mask;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_intr_mask 16
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_intr_mask 16
-
-/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_rw_ack_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_rw_ack_intr 20
-#define REG_WR_ADDR_iop_fifo_out_extra_rw_ack_intr 20
-
-/* Register r_intr, scope iop_fifo_out_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_r_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_intr 24
-
-/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
-typedef struct {
- unsigned int urun : 1;
- unsigned int last_data : 1;
- unsigned int dav : 1;
- unsigned int free : 1;
- unsigned int orun : 1;
- unsigned int dummy1 : 27;
-} reg_iop_fifo_out_extra_r_masked_intr;
-#define REG_RD_ADDR_iop_fifo_out_extra_r_masked_intr 28
-
-
-/* Constants */
-enum {
- regk_iop_fifo_out_extra_no = 0x00000000,
- regk_iop_fifo_out_extra_rw_intr_mask_default = 0x00000000,
- regk_iop_fifo_out_extra_yes = 0x00000001
-};
-#endif /* __iop_fifo_out_extra_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h
deleted file mode 100644
index 28e1c5903677..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_defs.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_mpu_defs_h
-#define __iop_mpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_mpu.r
- * id: iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_mpu_defs.h ../../inst/io_proc/rtl/iop_mpu.r
- * id: $Id: iop_mpu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_mpu */
-
-#define STRIDE_iop_mpu_rw_r 4
-/* Register rw_r, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_r;
-#define REG_RD_ADDR_iop_mpu_rw_r 0
-#define REG_WR_ADDR_iop_mpu_rw_r 0
-
-/* Register rw_ctrl, scope iop_mpu, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_mpu_rw_ctrl;
-#define REG_RD_ADDR_iop_mpu_rw_ctrl 128
-#define REG_WR_ADDR_iop_mpu_rw_ctrl 128
-
-/* Register r_pc, scope iop_mpu, type r */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_mpu_r_pc;
-#define REG_RD_ADDR_iop_mpu_r_pc 132
-
-/* Register r_stat, scope iop_mpu, type r */
-typedef struct {
- unsigned int instr_reg_busy : 1;
- unsigned int intr_busy : 1;
- unsigned int intr_vect : 16;
- unsigned int dummy1 : 14;
-} reg_iop_mpu_r_stat;
-#define REG_RD_ADDR_iop_mpu_r_stat 136
-
-/* Register rw_instr, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_instr;
-#define REG_RD_ADDR_iop_mpu_rw_instr 140
-#define REG_WR_ADDR_iop_mpu_rw_instr 140
-
-/* Register rw_immediate, scope iop_mpu, type rw */
-typedef unsigned int reg_iop_mpu_rw_immediate;
-#define REG_RD_ADDR_iop_mpu_rw_immediate 144
-#define REG_WR_ADDR_iop_mpu_rw_immediate 144
-
-/* Register r_trace, scope iop_mpu, type r */
-typedef struct {
- unsigned int intr_vect : 16;
- unsigned int pc : 12;
- unsigned int en : 1;
- unsigned int instr_reg_busy : 1;
- unsigned int intr_busy : 1;
- unsigned int dummy1 : 1;
-} reg_iop_mpu_r_trace;
-#define REG_RD_ADDR_iop_mpu_r_trace 148
-
-/* Register r_wr_stat, scope iop_mpu, type r */
-typedef struct {
- unsigned int r0 : 1;
- unsigned int r1 : 1;
- unsigned int r2 : 1;
- unsigned int r3 : 1;
- unsigned int r4 : 1;
- unsigned int r5 : 1;
- unsigned int r6 : 1;
- unsigned int r7 : 1;
- unsigned int r8 : 1;
- unsigned int r9 : 1;
- unsigned int r10 : 1;
- unsigned int r11 : 1;
- unsigned int r12 : 1;
- unsigned int r13 : 1;
- unsigned int r14 : 1;
- unsigned int r15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_mpu_r_wr_stat;
-#define REG_RD_ADDR_iop_mpu_r_wr_stat 152
-
-#define STRIDE_iop_mpu_rw_thread 4
-/* Register rw_thread, scope iop_mpu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_mpu_rw_thread;
-#define REG_RD_ADDR_iop_mpu_rw_thread 156
-#define REG_WR_ADDR_iop_mpu_rw_thread 156
-
-#define STRIDE_iop_mpu_rw_intr 4
-/* Register rw_intr, scope iop_mpu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_mpu_rw_intr;
-#define REG_RD_ADDR_iop_mpu_rw_intr 196
-#define REG_WR_ADDR_iop_mpu_rw_intr 196
-
-
-/* Constants */
-enum {
- regk_iop_mpu_no = 0x00000000,
- regk_iop_mpu_r_pc_default = 0x00000000,
- regk_iop_mpu_rw_ctrl_default = 0x00000000,
- regk_iop_mpu_rw_intr_size = 0x00000010,
- regk_iop_mpu_rw_r_size = 0x00000010,
- regk_iop_mpu_rw_thread_default = 0x00000000,
- regk_iop_mpu_rw_thread_size = 0x00000004,
- regk_iop_mpu_yes = 0x00000001
-};
-#endif /* __iop_mpu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h
deleted file mode 100644
index 41f5178a65b8..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_mpu_macros.h
+++ /dev/null
@@ -1,765 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ************************************************************************* */
-/* This file is autogenerated by IOPASM Version 1.2 */
-/* DO NOT EDIT THIS FILE - All changes will be lost! */
-/* ************************************************************************* */
-
-
-
-#ifndef __IOP_MPU_MACROS_H__
-#define __IOP_MPU_MACROS_H__
-
-
-/* ************************************************************************* */
-/* REGISTER DEFINITIONS */
-/* ************************************************************************* */
-#define MPU_R0 (0x0)
-#define MPU_R1 (0x1)
-#define MPU_R2 (0x2)
-#define MPU_R3 (0x3)
-#define MPU_R4 (0x4)
-#define MPU_R5 (0x5)
-#define MPU_R6 (0x6)
-#define MPU_R7 (0x7)
-#define MPU_R8 (0x8)
-#define MPU_R9 (0x9)
-#define MPU_R10 (0xa)
-#define MPU_R11 (0xb)
-#define MPU_R12 (0xc)
-#define MPU_R13 (0xd)
-#define MPU_R14 (0xe)
-#define MPU_R15 (0xf)
-#define MPU_PC (0x2)
-#define MPU_WSTS (0x3)
-#define MPU_JADDR (0x4)
-#define MPU_IRP (0x5)
-#define MPU_SRP (0x6)
-#define MPU_T0 (0x8)
-#define MPU_T1 (0x9)
-#define MPU_T2 (0xa)
-#define MPU_T3 (0xb)
-#define MPU_I0 (0x10)
-#define MPU_I1 (0x11)
-#define MPU_I2 (0x12)
-#define MPU_I3 (0x13)
-#define MPU_I4 (0x14)
-#define MPU_I5 (0x15)
-#define MPU_I6 (0x16)
-#define MPU_I7 (0x17)
-#define MPU_I8 (0x18)
-#define MPU_I9 (0x19)
-#define MPU_I10 (0x1a)
-#define MPU_I11 (0x1b)
-#define MPU_I12 (0x1c)
-#define MPU_I13 (0x1d)
-#define MPU_I14 (0x1e)
-#define MPU_I15 (0x1f)
-#define MPU_P2 (0x2)
-#define MPU_P3 (0x3)
-#define MPU_P5 (0x5)
-#define MPU_P6 (0x6)
-#define MPU_P8 (0x8)
-#define MPU_P9 (0x9)
-#define MPU_P10 (0xa)
-#define MPU_P11 (0xb)
-#define MPU_P16 (0x10)
-#define MPU_P17 (0x12)
-#define MPU_P18 (0x12)
-#define MPU_P19 (0x13)
-#define MPU_P20 (0x14)
-#define MPU_P21 (0x15)
-#define MPU_P22 (0x16)
-#define MPU_P23 (0x17)
-#define MPU_P24 (0x18)
-#define MPU_P25 (0x19)
-#define MPU_P26 (0x1a)
-#define MPU_P27 (0x1b)
-#define MPU_P28 (0x1c)
-#define MPU_P29 (0x1d)
-#define MPU_P30 (0x1e)
-#define MPU_P31 (0x1f)
-#define MPU_P1 (0x1)
-#define MPU_REGA (0x1)
-
-
-
-/* ************************************************************************* */
-/* ADDRESS MACROS */
-/* ************************************************************************* */
-#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
-#define MK_BYTE_ADDR(ADDR) (ADDR)
-
-
-
-/* ************************************************************************* */
-/* INSTRUCTION MACROS */
-/* ************************************************************************* */
-#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 21)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 21)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_DI() (0x40000001)
-
-#define MPU_EI() (0x40000003)
-
-#define MPU_HALT() (0x40000002)
-
-#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JNT() (0x61000000)
-
-#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
-
-#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
-
-#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_NOP() (0x40000000)
-
-#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_RET() (0x63003000)
-
-#define MPU_RETI() (0x63602800)
-
-#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
- | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
-
-#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
-
-#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
-
-#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 11))
-
-#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
- | ((N & ((1 << 16) - 1)) << 0)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
- | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
-
-#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
- | ((D & ((1 << 5) - 1)) << 21))
-
-#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
-
-
-#endif /* end of __IOP_MPU_MACROS_H__ */
-/* End of iop_mpu_macros.h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h
deleted file mode 100644
index 95e9ce8c042a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_reg_space.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
- */
-#define regi_iop_version (regi_iop + 0)
-#define regi_iop_fifo_in0_extra (regi_iop + 64)
-#define regi_iop_fifo_in1_extra (regi_iop + 128)
-#define regi_iop_fifo_out0_extra (regi_iop + 192)
-#define regi_iop_fifo_out1_extra (regi_iop + 256)
-#define regi_iop_trigger_grp0 (regi_iop + 320)
-#define regi_iop_trigger_grp1 (regi_iop + 384)
-#define regi_iop_trigger_grp2 (regi_iop + 448)
-#define regi_iop_trigger_grp3 (regi_iop + 512)
-#define regi_iop_trigger_grp4 (regi_iop + 576)
-#define regi_iop_trigger_grp5 (regi_iop + 640)
-#define regi_iop_trigger_grp6 (regi_iop + 704)
-#define regi_iop_trigger_grp7 (regi_iop + 768)
-#define regi_iop_crc_par0 (regi_iop + 896)
-#define regi_iop_crc_par1 (regi_iop + 1024)
-#define regi_iop_dmc_in0 (regi_iop + 1152)
-#define regi_iop_dmc_in1 (regi_iop + 1280)
-#define regi_iop_dmc_out0 (regi_iop + 1408)
-#define regi_iop_dmc_out1 (regi_iop + 1536)
-#define regi_iop_fifo_in0 (regi_iop + 1664)
-#define regi_iop_fifo_in1 (regi_iop + 1792)
-#define regi_iop_fifo_out0 (regi_iop + 1920)
-#define regi_iop_fifo_out1 (regi_iop + 2048)
-#define regi_iop_scrc_in0 (regi_iop + 2176)
-#define regi_iop_scrc_in1 (regi_iop + 2304)
-#define regi_iop_scrc_out0 (regi_iop + 2432)
-#define regi_iop_scrc_out1 (regi_iop + 2560)
-#define regi_iop_timer_grp0 (regi_iop + 2688)
-#define regi_iop_timer_grp1 (regi_iop + 2816)
-#define regi_iop_timer_grp2 (regi_iop + 2944)
-#define regi_iop_timer_grp3 (regi_iop + 3072)
-#define regi_iop_sap_in (regi_iop + 3328)
-#define regi_iop_sap_out (regi_iop + 3584)
-#define regi_iop_spu0 (regi_iop + 3840)
-#define regi_iop_spu1 (regi_iop + 4096)
-#define regi_iop_sw_cfg (regi_iop + 4352)
-#define regi_iop_sw_cpu (regi_iop + 4608)
-#define regi_iop_sw_mpu (regi_iop + 4864)
-#define regi_iop_sw_spu0 (regi_iop + 5120)
-#define regi_iop_sw_spu1 (regi_iop + 5376)
-#define regi_iop_mpu (regi_iop + 5632)
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h
deleted file mode 100644
index 22a74eafb8b0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_h
-#define __iop_sap_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_in.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:45 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
- * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_in */
-
-/* Register rw_bus0_sync, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int byte0_sel : 2;
- unsigned int byte0_ext_src : 3;
- unsigned int byte0_edge : 2;
- unsigned int byte0_delay : 1;
- unsigned int byte1_sel : 2;
- unsigned int byte1_ext_src : 3;
- unsigned int byte1_edge : 2;
- unsigned int byte1_delay : 1;
- unsigned int byte2_sel : 2;
- unsigned int byte2_ext_src : 3;
- unsigned int byte2_edge : 2;
- unsigned int byte2_delay : 1;
- unsigned int byte3_sel : 2;
- unsigned int byte3_ext_src : 3;
- unsigned int byte3_edge : 2;
- unsigned int byte3_delay : 1;
-} reg_iop_sap_in_rw_bus0_sync;
-#define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
-#define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
-
-/* Register rw_bus1_sync, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int byte0_sel : 2;
- unsigned int byte0_ext_src : 3;
- unsigned int byte0_edge : 2;
- unsigned int byte0_delay : 1;
- unsigned int byte1_sel : 2;
- unsigned int byte1_ext_src : 3;
- unsigned int byte1_edge : 2;
- unsigned int byte1_delay : 1;
- unsigned int byte2_sel : 2;
- unsigned int byte2_ext_src : 3;
- unsigned int byte2_edge : 2;
- unsigned int byte2_delay : 1;
- unsigned int byte3_sel : 2;
- unsigned int byte3_ext_src : 3;
- unsigned int byte3_edge : 2;
- unsigned int byte3_delay : 1;
-} reg_iop_sap_in_rw_bus1_sync;
-#define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
-#define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int sync_sel : 2;
- unsigned int sync_ext_src : 3;
- unsigned int sync_edge : 2;
- unsigned int delay : 1;
- unsigned int logic : 2;
- unsigned int dummy1 : 22;
-} reg_iop_sap_in_rw_gio;
-#define REG_RD_ADDR_iop_sap_in_rw_gio 8
-#define REG_WR_ADDR_iop_sap_in_rw_gio 8
-
-
-/* Constants */
-enum {
- regk_iop_sap_in_and = 0x00000002,
- regk_iop_sap_in_ext_clk200 = 0x00000003,
- regk_iop_sap_in_gio1 = 0x00000000,
- regk_iop_sap_in_gio13 = 0x00000005,
- regk_iop_sap_in_gio18 = 0x00000003,
- regk_iop_sap_in_gio19 = 0x00000004,
- regk_iop_sap_in_gio21 = 0x00000006,
- regk_iop_sap_in_gio23 = 0x00000005,
- regk_iop_sap_in_gio29 = 0x00000007,
- regk_iop_sap_in_gio5 = 0x00000004,
- regk_iop_sap_in_gio6 = 0x00000001,
- regk_iop_sap_in_gio7 = 0x00000002,
- regk_iop_sap_in_inv = 0x00000001,
- regk_iop_sap_in_neg = 0x00000002,
- regk_iop_sap_in_no = 0x00000000,
- regk_iop_sap_in_no_del_ext_clk200 = 0x00000001,
- regk_iop_sap_in_none = 0x00000000,
- regk_iop_sap_in_or = 0x00000003,
- regk_iop_sap_in_pos = 0x00000001,
- regk_iop_sap_in_pos_neg = 0x00000003,
- regk_iop_sap_in_rw_bus0_sync_default = 0x02020202,
- regk_iop_sap_in_rw_bus1_sync_default = 0x02020202,
- regk_iop_sap_in_rw_gio_default = 0x00000002,
- regk_iop_sap_in_rw_gio_size = 0x00000020,
- regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006,
- regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004,
- regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005,
- regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007,
- regk_iop_sap_in_tmr_clk200 = 0x00000000,
- regk_iop_sap_in_two_clk200 = 0x00000002,
- regk_iop_sap_in_yes = 0x00000001
-};
-#endif /* __iop_sap_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h
deleted file mode 100644
index 380133910105..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_out_defs.h
+++ /dev/null
@@ -1,307 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_h
-#define __iop_sap_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_sap_out.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_out_defs.h ../../inst/io_proc/rtl/iop_sap_out.r
- * id: $Id: iop_sap_out_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_out */
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int clk0_src : 2;
- unsigned int clk0_gate_src : 2;
- unsigned int clk0_force_src : 3;
- unsigned int clk1_src : 2;
- unsigned int clk1_gate_src : 2;
- unsigned int clk1_force_src : 3;
- unsigned int clk2_src : 2;
- unsigned int clk2_gate_src : 2;
- unsigned int clk2_force_src : 3;
- unsigned int clk3_src : 2;
- unsigned int clk3_gate_src : 2;
- unsigned int clk3_force_src : 3;
- unsigned int dummy1 : 4;
-} reg_iop_sap_out_rw_gen_gated;
-#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
-#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
-
-/* Register rw_bus0, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int dummy1 : 8;
-} reg_iop_sap_out_rw_bus0;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
-#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
-
-/* Register rw_bus1, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int dummy1 : 8;
-} reg_iop_sap_out_rw_bus1;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
-#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
-
-/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_clk_ext : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_logic : 2;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_clk_ext : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus0_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
-#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
-
-/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_clk_ext : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_logic : 2;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_clk_ext : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus0_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
-#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
-
-/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 3;
- unsigned int byte0_clk_ext : 3;
- unsigned int byte0_gated_clk : 2;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_logic : 2;
- unsigned int byte1_clk_sel : 3;
- unsigned int byte1_clk_ext : 3;
- unsigned int byte1_gated_clk : 2;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus1_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
-#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
-
-/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte2_clk_sel : 3;
- unsigned int byte2_clk_ext : 3;
- unsigned int byte2_gated_clk : 2;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_logic : 2;
- unsigned int byte3_clk_sel : 3;
- unsigned int byte3_clk_ext : 3;
- unsigned int byte3_gated_clk : 2;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus1_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
-#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int out_clk_sel : 3;
- unsigned int out_clk_ext : 4;
- unsigned int out_gated_clk : 2;
- unsigned int out_clk_inv : 1;
- unsigned int out_logic : 1;
- unsigned int oe_clk_sel : 3;
- unsigned int oe_clk_ext : 3;
- unsigned int oe_gated_clk : 2;
- unsigned int oe_clk_inv : 1;
- unsigned int oe_logic : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_gio;
-#define REG_RD_ADDR_iop_sap_out_rw_gio 28
-#define REG_WR_ADDR_iop_sap_out_rw_gio 28
-
-
-/* Constants */
-enum {
- regk_iop_sap_out_and = 0x00000002,
- regk_iop_sap_out_clk0 = 0x00000000,
- regk_iop_sap_out_clk1 = 0x00000001,
- regk_iop_sap_out_clk12 = 0x00000002,
- regk_iop_sap_out_clk2 = 0x00000002,
- regk_iop_sap_out_clk200 = 0x00000001,
- regk_iop_sap_out_clk3 = 0x00000003,
- regk_iop_sap_out_ext = 0x00000003,
- regk_iop_sap_out_gated = 0x00000004,
- regk_iop_sap_out_gio1 = 0x00000000,
- regk_iop_sap_out_gio13 = 0x00000002,
- regk_iop_sap_out_gio13_clk = 0x0000000c,
- regk_iop_sap_out_gio15 = 0x00000001,
- regk_iop_sap_out_gio18 = 0x00000003,
- regk_iop_sap_out_gio18_clk = 0x0000000d,
- regk_iop_sap_out_gio1_clk = 0x00000008,
- regk_iop_sap_out_gio21_clk = 0x0000000e,
- regk_iop_sap_out_gio23 = 0x00000002,
- regk_iop_sap_out_gio29_clk = 0x0000000f,
- regk_iop_sap_out_gio31 = 0x00000003,
- regk_iop_sap_out_gio5 = 0x00000001,
- regk_iop_sap_out_gio5_clk = 0x00000009,
- regk_iop_sap_out_gio6_clk = 0x0000000a,
- regk_iop_sap_out_gio7 = 0x00000000,
- regk_iop_sap_out_gio7_clk = 0x0000000b,
- regk_iop_sap_out_gio_in13 = 0x00000001,
- regk_iop_sap_out_gio_in21 = 0x00000002,
- regk_iop_sap_out_gio_in29 = 0x00000003,
- regk_iop_sap_out_gio_in5 = 0x00000000,
- regk_iop_sap_out_inv = 0x00000001,
- regk_iop_sap_out_nand = 0x00000003,
- regk_iop_sap_out_no = 0x00000000,
- regk_iop_sap_out_none = 0x00000000,
- regk_iop_sap_out_rw_bus0_default = 0x00000000,
- regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus1_default = 0x00000000,
- regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000,
- regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
- regk_iop_sap_out_rw_gio_default = 0x00000000,
- regk_iop_sap_out_rw_gio_size = 0x00000020,
- regk_iop_sap_out_spu0_gio0 = 0x00000002,
- regk_iop_sap_out_spu0_gio1 = 0x00000003,
- regk_iop_sap_out_spu0_gio12 = 0x00000004,
- regk_iop_sap_out_spu0_gio13 = 0x00000004,
- regk_iop_sap_out_spu0_gio14 = 0x00000004,
- regk_iop_sap_out_spu0_gio15 = 0x00000004,
- regk_iop_sap_out_spu0_gio2 = 0x00000002,
- regk_iop_sap_out_spu0_gio3 = 0x00000003,
- regk_iop_sap_out_spu0_gio4 = 0x00000002,
- regk_iop_sap_out_spu0_gio5 = 0x00000003,
- regk_iop_sap_out_spu0_gio6 = 0x00000002,
- regk_iop_sap_out_spu0_gio7 = 0x00000003,
- regk_iop_sap_out_spu1_gio0 = 0x00000005,
- regk_iop_sap_out_spu1_gio1 = 0x00000006,
- regk_iop_sap_out_spu1_gio12 = 0x00000007,
- regk_iop_sap_out_spu1_gio13 = 0x00000007,
- regk_iop_sap_out_spu1_gio14 = 0x00000007,
- regk_iop_sap_out_spu1_gio15 = 0x00000007,
- regk_iop_sap_out_spu1_gio2 = 0x00000005,
- regk_iop_sap_out_spu1_gio3 = 0x00000006,
- regk_iop_sap_out_spu1_gio4 = 0x00000005,
- regk_iop_sap_out_spu1_gio5 = 0x00000006,
- regk_iop_sap_out_spu1_gio6 = 0x00000005,
- regk_iop_sap_out_spu1_gio7 = 0x00000006,
- regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004,
- regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005,
- regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006,
- regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007,
- regk_iop_sap_out_tmr = 0x00000005,
- regk_iop_sap_out_yes = 0x00000001
-};
-#endif /* __iop_sap_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h
deleted file mode 100644
index 65d662046ca9..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_in_defs.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_in_defs_h
-#define __iop_scrc_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
- * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_scrc_in */
-
-/* Register rw_cfg, scope iop_scrc_in, type rw */
-typedef struct {
- unsigned int trig : 2;
- unsigned int dummy1 : 30;
-} reg_iop_scrc_in_rw_cfg;
-#define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
-#define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_scrc_in, type rw */
-typedef struct {
- unsigned int dif_in_en : 1;
- unsigned int dummy1 : 31;
-} reg_iop_scrc_in_rw_ctrl;
-#define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
-#define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
-
-/* Register r_stat, scope iop_scrc_in, type r */
-typedef struct {
- unsigned int err : 1;
- unsigned int dummy1 : 31;
-} reg_iop_scrc_in_r_stat;
-#define REG_RD_ADDR_iop_scrc_in_r_stat 8
-
-/* Register rw_init_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_init_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
-#define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
-
-/* Register rs_computed_crc, scope iop_scrc_in, type rs */
-typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
-#define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
-
-/* Register r_computed_crc, scope iop_scrc_in, type r */
-typedef unsigned int reg_iop_scrc_in_r_computed_crc;
-#define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
-
-/* Register rw_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_crc 24
-#define REG_WR_ADDR_iop_scrc_in_rw_crc 24
-
-/* Register rw_correct_crc, scope iop_scrc_in, type rw */
-typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
-#define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
-#define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
-
-/* Register rw_wr1bit, scope iop_scrc_in, type rw */
-typedef struct {
- unsigned int data : 2;
- unsigned int last : 2;
- unsigned int dummy1 : 28;
-} reg_iop_scrc_in_rw_wr1bit;
-#define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
-#define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
-
-
-/* Constants */
-enum {
- regk_iop_scrc_in_dif_in = 0x00000002,
- regk_iop_scrc_in_hi = 0x00000000,
- regk_iop_scrc_in_neg = 0x00000002,
- regk_iop_scrc_in_no = 0x00000000,
- regk_iop_scrc_in_pos = 0x00000001,
- regk_iop_scrc_in_pos_neg = 0x00000003,
- regk_iop_scrc_in_r_computed_crc_default = 0x00000000,
- regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
- regk_iop_scrc_in_rw_cfg_default = 0x00000000,
- regk_iop_scrc_in_rw_ctrl_default = 0x00000000,
- regk_iop_scrc_in_rw_init_crc_default = 0x00000000,
- regk_iop_scrc_in_set0 = 0x00000000,
- regk_iop_scrc_in_set1 = 0x00000001,
- regk_iop_scrc_in_yes = 0x00000001
-};
-#endif /* __iop_scrc_in_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h
deleted file mode 100644
index ba39605b9737..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_scrc_out_defs.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_out_defs_h
-#define __iop_scrc_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r
- * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_scrc_out */
-
-/* Register rw_cfg, scope iop_scrc_out, type rw */
-typedef struct {
- unsigned int trig : 2;
- unsigned int inv_crc : 1;
- unsigned int dummy1 : 29;
-} reg_iop_scrc_out_rw_cfg;
-#define REG_RD_ADDR_iop_scrc_out_rw_cfg 0
-#define REG_WR_ADDR_iop_scrc_out_rw_cfg 0
-
-/* Register rw_ctrl, scope iop_scrc_out, type rw */
-typedef struct {
- unsigned int strb_src : 1;
- unsigned int out_src : 1;
- unsigned int dummy1 : 30;
-} reg_iop_scrc_out_rw_ctrl;
-#define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4
-#define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4
-
-/* Register rw_init_crc, scope iop_scrc_out, type rw */
-typedef unsigned int reg_iop_scrc_out_rw_init_crc;
-#define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8
-#define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8
-
-/* Register rw_crc, scope iop_scrc_out, type rw */
-typedef unsigned int reg_iop_scrc_out_rw_crc;
-#define REG_RD_ADDR_iop_scrc_out_rw_crc 12
-#define REG_WR_ADDR_iop_scrc_out_rw_crc 12
-
-/* Register rw_data, scope iop_scrc_out, type rw */
-typedef struct {
- unsigned int val : 1;
- unsigned int dummy1 : 31;
-} reg_iop_scrc_out_rw_data;
-#define REG_RD_ADDR_iop_scrc_out_rw_data 16
-#define REG_WR_ADDR_iop_scrc_out_rw_data 16
-
-/* Register r_computed_crc, scope iop_scrc_out, type r */
-typedef unsigned int reg_iop_scrc_out_r_computed_crc;
-#define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20
-
-
-/* Constants */
-enum {
- regk_iop_scrc_out_crc = 0x00000001,
- regk_iop_scrc_out_data = 0x00000000,
- regk_iop_scrc_out_dif = 0x00000001,
- regk_iop_scrc_out_hi = 0x00000000,
- regk_iop_scrc_out_neg = 0x00000002,
- regk_iop_scrc_out_no = 0x00000000,
- regk_iop_scrc_out_pos = 0x00000001,
- regk_iop_scrc_out_pos_neg = 0x00000003,
- regk_iop_scrc_out_reg = 0x00000000,
- regk_iop_scrc_out_rw_cfg_default = 0x00000000,
- regk_iop_scrc_out_rw_crc_default = 0x00000000,
- regk_iop_scrc_out_rw_ctrl_default = 0x00000000,
- regk_iop_scrc_out_rw_data_default = 0x00000000,
- regk_iop_scrc_out_rw_init_crc_default = 0x00000000,
- regk_iop_scrc_out_yes = 0x00000001
-};
-#endif /* __iop_scrc_out_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h
deleted file mode 100644
index 7681fdab93fc..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_spu_defs.h
+++ /dev/null
@@ -1,454 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_spu_defs_h
-#define __iop_spu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_spu_defs.h ../../inst/io_proc/rtl/iop_spu.r
- * id: $Id: iop_spu_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_spu */
-
-#define STRIDE_iop_spu_rw_r 4
-/* Register rw_r, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_r;
-#define REG_RD_ADDR_iop_spu_rw_r 0
-#define REG_WR_ADDR_iop_spu_rw_r 0
-
-/* Register rw_seq_pc, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_spu_rw_seq_pc;
-#define REG_RD_ADDR_iop_spu_rw_seq_pc 64
-#define REG_WR_ADDR_iop_spu_rw_seq_pc 64
-
-/* Register rw_fsm_pc, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_spu_rw_fsm_pc;
-#define REG_RD_ADDR_iop_spu_rw_fsm_pc 68
-#define REG_WR_ADDR_iop_spu_rw_fsm_pc 68
-
-/* Register rw_ctrl, scope iop_spu, type rw */
-typedef struct {
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 30;
-} reg_iop_spu_rw_ctrl;
-#define REG_RD_ADDR_iop_spu_rw_ctrl 72
-#define REG_WR_ADDR_iop_spu_rw_ctrl 72
-
-/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
-typedef struct {
- unsigned int val0 : 5;
- unsigned int src0 : 3;
- unsigned int val1 : 5;
- unsigned int src1 : 3;
- unsigned int val2 : 5;
- unsigned int src2 : 3;
- unsigned int val3 : 5;
- unsigned int src3 : 3;
-} reg_iop_spu_rw_fsm_inputs3_0;
-#define REG_RD_ADDR_iop_spu_rw_fsm_inputs3_0 76
-#define REG_WR_ADDR_iop_spu_rw_fsm_inputs3_0 76
-
-/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
-typedef struct {
- unsigned int val4 : 5;
- unsigned int src4 : 3;
- unsigned int val5 : 5;
- unsigned int src5 : 3;
- unsigned int val6 : 5;
- unsigned int src6 : 3;
- unsigned int val7 : 5;
- unsigned int src7 : 3;
-} reg_iop_spu_rw_fsm_inputs7_4;
-#define REG_RD_ADDR_iop_spu_rw_fsm_inputs7_4 80
-#define REG_WR_ADDR_iop_spu_rw_fsm_inputs7_4 80
-
-/* Register rw_gio_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out;
-#define REG_RD_ADDR_iop_spu_rw_gio_out 84
-#define REG_WR_ADDR_iop_spu_rw_gio_out 84
-
-/* Register rw_bus0_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_bus0_out;
-#define REG_RD_ADDR_iop_spu_rw_bus0_out 88
-#define REG_WR_ADDR_iop_spu_rw_bus0_out 88
-
-/* Register rw_bus1_out, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_bus1_out;
-#define REG_RD_ADDR_iop_spu_rw_bus1_out 92
-#define REG_WR_ADDR_iop_spu_rw_bus1_out 92
-
-/* Register r_gio_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_gio_in;
-#define REG_RD_ADDR_iop_spu_r_gio_in 96
-
-/* Register r_bus0_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_bus0_in;
-#define REG_RD_ADDR_iop_spu_r_bus0_in 100
-
-/* Register r_bus1_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_bus1_in;
-#define REG_RD_ADDR_iop_spu_r_bus1_in 104
-
-/* Register rw_gio_out_set, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out_set;
-#define REG_RD_ADDR_iop_spu_rw_gio_out_set 108
-#define REG_WR_ADDR_iop_spu_rw_gio_out_set 108
-
-/* Register rw_gio_out_clr, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_gio_out_clr;
-#define REG_RD_ADDR_iop_spu_rw_gio_out_clr 112
-#define REG_WR_ADDR_iop_spu_rw_gio_out_clr 112
-
-/* Register rs_wr_stat, scope iop_spu, type rs */
-typedef struct {
- unsigned int r0 : 1;
- unsigned int r1 : 1;
- unsigned int r2 : 1;
- unsigned int r3 : 1;
- unsigned int r4 : 1;
- unsigned int r5 : 1;
- unsigned int r6 : 1;
- unsigned int r7 : 1;
- unsigned int r8 : 1;
- unsigned int r9 : 1;
- unsigned int r10 : 1;
- unsigned int r11 : 1;
- unsigned int r12 : 1;
- unsigned int r13 : 1;
- unsigned int r14 : 1;
- unsigned int r15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_spu_rs_wr_stat;
-#define REG_RD_ADDR_iop_spu_rs_wr_stat 116
-
-/* Register r_wr_stat, scope iop_spu, type r */
-typedef struct {
- unsigned int r0 : 1;
- unsigned int r1 : 1;
- unsigned int r2 : 1;
- unsigned int r3 : 1;
- unsigned int r4 : 1;
- unsigned int r5 : 1;
- unsigned int r6 : 1;
- unsigned int r7 : 1;
- unsigned int r8 : 1;
- unsigned int r9 : 1;
- unsigned int r10 : 1;
- unsigned int r11 : 1;
- unsigned int r12 : 1;
- unsigned int r13 : 1;
- unsigned int r14 : 1;
- unsigned int r15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_spu_r_wr_stat;
-#define REG_RD_ADDR_iop_spu_r_wr_stat 120
-
-/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_reg_indexed_by_bus0_in;
-#define REG_RD_ADDR_iop_spu_r_reg_indexed_by_bus0_in 124
-
-/* Register r_stat_in, scope iop_spu, type r */
-typedef struct {
- unsigned int timer_grp_lo : 4;
- unsigned int fifo_out_last : 1;
- unsigned int fifo_out_rdy : 1;
- unsigned int fifo_out_all : 1;
- unsigned int fifo_in_rdy : 1;
- unsigned int dmc_out_all : 1;
- unsigned int dmc_out_dth : 1;
- unsigned int dmc_out_eop : 1;
- unsigned int dmc_out_dv : 1;
- unsigned int dmc_out_last : 1;
- unsigned int dmc_out_cmd_rq : 1;
- unsigned int dmc_out_cmd_rdy : 1;
- unsigned int pcrc_correct : 1;
- unsigned int timer_grp_hi : 4;
- unsigned int dmc_in_sth : 1;
- unsigned int dmc_in_full : 1;
- unsigned int dmc_in_cmd_rdy : 1;
- unsigned int spu_gio_out : 4;
- unsigned int sync_clk12 : 1;
- unsigned int scrc_out_data : 1;
- unsigned int scrc_in_err : 1;
- unsigned int mc_busy : 1;
- unsigned int mc_owned : 1;
-} reg_iop_spu_r_stat_in;
-#define REG_RD_ADDR_iop_spu_r_stat_in 128
-
-/* Register r_trigger_in, scope iop_spu, type r */
-typedef unsigned int reg_iop_spu_r_trigger_in;
-#define REG_RD_ADDR_iop_spu_r_trigger_in 132
-
-/* Register r_special_stat, scope iop_spu, type r */
-typedef struct {
- unsigned int c_flag : 1;
- unsigned int v_flag : 1;
- unsigned int z_flag : 1;
- unsigned int n_flag : 1;
- unsigned int xor_bus0_r2_0 : 1;
- unsigned int xor_bus1_r3_0 : 1;
- unsigned int xor_bus0m_r2_0 : 1;
- unsigned int xor_bus1m_r3_0 : 1;
- unsigned int fsm_in0 : 1;
- unsigned int fsm_in1 : 1;
- unsigned int fsm_in2 : 1;
- unsigned int fsm_in3 : 1;
- unsigned int fsm_in4 : 1;
- unsigned int fsm_in5 : 1;
- unsigned int fsm_in6 : 1;
- unsigned int fsm_in7 : 1;
- unsigned int event0 : 1;
- unsigned int event1 : 1;
- unsigned int event2 : 1;
- unsigned int event3 : 1;
- unsigned int dummy1 : 12;
-} reg_iop_spu_r_special_stat;
-#define REG_RD_ADDR_iop_spu_r_special_stat 136
-
-/* Register rw_reg_access, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 13;
- unsigned int dummy1 : 3;
- unsigned int imm_hi : 16;
-} reg_iop_spu_rw_reg_access;
-#define REG_RD_ADDR_iop_spu_rw_reg_access 140
-#define REG_WR_ADDR_iop_spu_rw_reg_access 140
-
-#define STRIDE_iop_spu_rw_event_cfg 4
-/* Register rw_event_cfg, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int src : 2;
- unsigned int eq_en : 1;
- unsigned int eq_inv : 1;
- unsigned int gt_en : 1;
- unsigned int gt_inv : 1;
- unsigned int dummy1 : 14;
-} reg_iop_spu_rw_event_cfg;
-#define REG_RD_ADDR_iop_spu_rw_event_cfg 144
-#define REG_WR_ADDR_iop_spu_rw_event_cfg 144
-
-#define STRIDE_iop_spu_rw_event_mask 4
-/* Register rw_event_mask, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_event_mask;
-#define REG_RD_ADDR_iop_spu_rw_event_mask 160
-#define REG_WR_ADDR_iop_spu_rw_event_mask 160
-
-#define STRIDE_iop_spu_rw_event_val 4
-/* Register rw_event_val, scope iop_spu, type rw */
-typedef unsigned int reg_iop_spu_rw_event_val;
-#define REG_RD_ADDR_iop_spu_rw_event_val 176
-#define REG_WR_ADDR_iop_spu_rw_event_val 176
-
-/* Register rw_event_ret, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int dummy1 : 20;
-} reg_iop_spu_rw_event_ret;
-#define REG_RD_ADDR_iop_spu_rw_event_ret 192
-#define REG_WR_ADDR_iop_spu_rw_event_ret 192
-
-/* Register r_trace, scope iop_spu, type r */
-typedef struct {
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int c_flag : 1;
- unsigned int v_flag : 1;
- unsigned int z_flag : 1;
- unsigned int n_flag : 1;
- unsigned int seq_addr : 12;
- unsigned int dummy1 : 2;
- unsigned int fsm_addr : 12;
-} reg_iop_spu_r_trace;
-#define REG_RD_ADDR_iop_spu_r_trace 196
-
-/* Register r_fsm_trace, scope iop_spu, type r */
-typedef struct {
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int tmr_done : 1;
- unsigned int inp0 : 1;
- unsigned int inp1 : 1;
- unsigned int inp2 : 1;
- unsigned int inp3 : 1;
- unsigned int event0 : 1;
- unsigned int event1 : 1;
- unsigned int event2 : 1;
- unsigned int event3 : 1;
- unsigned int gio_out : 8;
- unsigned int dummy1 : 1;
- unsigned int fsm_addr : 12;
-} reg_iop_spu_r_fsm_trace;
-#define REG_RD_ADDR_iop_spu_r_fsm_trace 200
-
-#define STRIDE_iop_spu_rw_brp 4
-/* Register rw_brp, scope iop_spu, type rw */
-typedef struct {
- unsigned int addr : 12;
- unsigned int fsm : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 18;
-} reg_iop_spu_rw_brp;
-#define REG_RD_ADDR_iop_spu_rw_brp 204
-#define REG_WR_ADDR_iop_spu_rw_brp 204
-
-
-/* Constants */
-enum {
- regk_iop_spu_attn_hi = 0x00000005,
- regk_iop_spu_attn_lo = 0x00000005,
- regk_iop_spu_attn_r0 = 0x00000000,
- regk_iop_spu_attn_r1 = 0x00000001,
- regk_iop_spu_attn_r10 = 0x00000002,
- regk_iop_spu_attn_r11 = 0x00000003,
- regk_iop_spu_attn_r12 = 0x00000004,
- regk_iop_spu_attn_r13 = 0x00000005,
- regk_iop_spu_attn_r14 = 0x00000006,
- regk_iop_spu_attn_r15 = 0x00000007,
- regk_iop_spu_attn_r2 = 0x00000002,
- regk_iop_spu_attn_r3 = 0x00000003,
- regk_iop_spu_attn_r4 = 0x00000004,
- regk_iop_spu_attn_r5 = 0x00000005,
- regk_iop_spu_attn_r6 = 0x00000006,
- regk_iop_spu_attn_r7 = 0x00000007,
- regk_iop_spu_attn_r8 = 0x00000000,
- regk_iop_spu_attn_r9 = 0x00000001,
- regk_iop_spu_c = 0x00000000,
- regk_iop_spu_flag = 0x00000002,
- regk_iop_spu_gio_in = 0x00000000,
- regk_iop_spu_gio_out = 0x00000005,
- regk_iop_spu_gio_out0 = 0x00000008,
- regk_iop_spu_gio_out1 = 0x00000009,
- regk_iop_spu_gio_out2 = 0x0000000a,
- regk_iop_spu_gio_out3 = 0x0000000b,
- regk_iop_spu_gio_out4 = 0x0000000c,
- regk_iop_spu_gio_out5 = 0x0000000d,
- regk_iop_spu_gio_out6 = 0x0000000e,
- regk_iop_spu_gio_out7 = 0x0000000f,
- regk_iop_spu_n = 0x00000003,
- regk_iop_spu_no = 0x00000000,
- regk_iop_spu_r0 = 0x00000008,
- regk_iop_spu_r1 = 0x00000009,
- regk_iop_spu_r10 = 0x0000000a,
- regk_iop_spu_r11 = 0x0000000b,
- regk_iop_spu_r12 = 0x0000000c,
- regk_iop_spu_r13 = 0x0000000d,
- regk_iop_spu_r14 = 0x0000000e,
- regk_iop_spu_r15 = 0x0000000f,
- regk_iop_spu_r2 = 0x0000000a,
- regk_iop_spu_r3 = 0x0000000b,
- regk_iop_spu_r4 = 0x0000000c,
- regk_iop_spu_r5 = 0x0000000d,
- regk_iop_spu_r6 = 0x0000000e,
- regk_iop_spu_r7 = 0x0000000f,
- regk_iop_spu_r8 = 0x00000008,
- regk_iop_spu_r9 = 0x00000009,
- regk_iop_spu_reg_hi = 0x00000002,
- regk_iop_spu_reg_lo = 0x00000002,
- regk_iop_spu_rw_brp_default = 0x00000000,
- regk_iop_spu_rw_brp_size = 0x00000004,
- regk_iop_spu_rw_ctrl_default = 0x00000000,
- regk_iop_spu_rw_event_cfg_size = 0x00000004,
- regk_iop_spu_rw_event_mask_size = 0x00000004,
- regk_iop_spu_rw_event_val_size = 0x00000004,
- regk_iop_spu_rw_gio_out_default = 0x00000000,
- regk_iop_spu_rw_r_size = 0x00000010,
- regk_iop_spu_rw_reg_access_default = 0x00000000,
- regk_iop_spu_stat_in = 0x00000002,
- regk_iop_spu_statin_hi = 0x00000004,
- regk_iop_spu_statin_lo = 0x00000004,
- regk_iop_spu_trig = 0x00000003,
- regk_iop_spu_trigger = 0x00000006,
- regk_iop_spu_v = 0x00000001,
- regk_iop_spu_wsts_gioout_spec = 0x00000001,
- regk_iop_spu_xor = 0x00000003,
- regk_iop_spu_xor_bus0_r2_0 = 0x00000000,
- regk_iop_spu_xor_bus0m_r2_0 = 0x00000002,
- regk_iop_spu_xor_bus1_r3_0 = 0x00000001,
- regk_iop_spu_xor_bus1m_r3_0 = 0x00000003,
- regk_iop_spu_yes = 0x00000001,
- regk_iop_spu_z = 0x00000002
-};
-#endif /* __iop_spu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h
deleted file mode 100644
index 86e5c9b3e593..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cfg_defs.h
+++ /dev/null
@@ -1,1043 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_h
-#define __iop_sw_cfg_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cfg_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- * id: $Id: iop_sw_cfg_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cfg */
-
-/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0
-
-/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4
-
-/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8
-
-/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12
-
-/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16
-
-/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20
-
-/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24
-
-/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in0_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28
-
-/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32
-
-/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in1_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36
-
-/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40
-
-/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out0_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44
-
-/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48
-
-/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out1_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60
-
-/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64
-
-/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68
-
-/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72
-
-/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76
-
-/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80
-
-/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92
-
-/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96
-
-/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp4_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp5_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp6_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp7_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132
-
-/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus0_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136
-
-/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus0_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140
-
-/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus1_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144
-
-/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus1_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_byte0 : 2;
- unsigned int bus0_byte1 : 2;
- unsigned int bus0_byte2 : 2;
- unsigned int bus0_byte3 : 2;
- unsigned int bus1_byte0 : 2;
- unsigned int bus1_byte1 : 2;
- unsigned int bus1_byte2 : 2;
- unsigned int bus1_byte3 : 2;
- unsigned int gio3_0 : 2;
- unsigned int gio7_4 : 2;
- unsigned int gio11_8 : 2;
- unsigned int gio15_12 : 2;
- unsigned int gio19_16 : 2;
- unsigned int gio23_20 : 2;
- unsigned int gio27_24 : 2;
- unsigned int gio31_28 : 2;
-} reg_iop_sw_cfg_rw_pinmapping;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160
-#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_lo : 3;
- unsigned int bus0_hi : 3;
- unsigned int bus0_lo_oe : 3;
- unsigned int bus0_hi_oe : 3;
- unsigned int bus1_lo : 3;
- unsigned int bus1_hi : 3;
- unsigned int bus1_lo_oe : 3;
- unsigned int bus1_hi_oe : 3;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_bus_out_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio0 : 4;
- unsigned int gio0_oe : 2;
- unsigned int gio1 : 4;
- unsigned int gio1_oe : 2;
- unsigned int gio2 : 4;
- unsigned int gio2_oe : 2;
- unsigned int gio3 : 4;
- unsigned int gio3_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio4 : 4;
- unsigned int gio4_oe : 2;
- unsigned int gio5 : 4;
- unsigned int gio5_oe : 2;
- unsigned int gio6 : 4;
- unsigned int gio6_oe : 2;
- unsigned int gio7 : 4;
- unsigned int gio7_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio8 : 4;
- unsigned int gio8_oe : 2;
- unsigned int gio9 : 4;
- unsigned int gio9_oe : 2;
- unsigned int gio10 : 4;
- unsigned int gio10_oe : 2;
- unsigned int gio11 : 4;
- unsigned int gio11_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio12 : 4;
- unsigned int gio12_oe : 2;
- unsigned int gio13 : 4;
- unsigned int gio13_oe : 2;
- unsigned int gio14 : 4;
- unsigned int gio14_oe : 2;
- unsigned int gio15 : 4;
- unsigned int gio15_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio16 : 4;
- unsigned int gio16_oe : 2;
- unsigned int gio17 : 4;
- unsigned int gio17_oe : 2;
- unsigned int gio18 : 4;
- unsigned int gio18_oe : 2;
- unsigned int gio19 : 4;
- unsigned int gio19_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio20 : 4;
- unsigned int gio20_oe : 2;
- unsigned int gio21 : 4;
- unsigned int gio21_oe : 2;
- unsigned int gio22 : 4;
- unsigned int gio22_oe : 2;
- unsigned int gio23 : 4;
- unsigned int gio23_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio24 : 4;
- unsigned int gio24_oe : 2;
- unsigned int gio25 : 4;
- unsigned int gio25_oe : 2;
- unsigned int gio26 : 4;
- unsigned int gio26_oe : 2;
- unsigned int gio27 : 4;
- unsigned int gio27_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio28 : 4;
- unsigned int gio28_oe : 2;
- unsigned int gio29 : 4;
- unsigned int gio29_oe : 2;
- unsigned int gio30 : 4;
- unsigned int gio30_oe : 2;
- unsigned int gio31 : 4;
- unsigned int gio31_oe : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196
-
-/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_in : 2;
- unsigned int bus1_in : 2;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_spu0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200
-
-/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_in : 2;
- unsigned int bus1_in : 2;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_spu1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212
-
-/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216
-
-/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 1;
- unsigned int tmr1_en : 1;
- unsigned int tmr2_en : 1;
- unsigned int tmr3_en : 1;
- unsigned int tmr0_dis : 1;
- unsigned int tmr1_dis : 1;
- unsigned int tmr2_dis : 1;
- unsigned int tmr3_dis : 1;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_timer_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int grp0_dis : 1;
- unsigned int grp0_en : 1;
- unsigned int grp1_dis : 1;
- unsigned int grp1_en : 1;
- unsigned int grp2_dis : 1;
- unsigned int grp2_en : 1;
- unsigned int grp3_dis : 1;
- unsigned int grp3_en : 1;
- unsigned int grp4_dis : 1;
- unsigned int grp4_en : 1;
- unsigned int grp5_dis : 1;
- unsigned int grp5_en : 1;
- unsigned int grp6_dis : 1;
- unsigned int grp6_en : 1;
- unsigned int grp7_dis : 1;
- unsigned int grp7_en : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_trigger_grps_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224
-
-/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int dmc0_usr : 1;
- unsigned int out_strb : 5;
- unsigned int in_src : 3;
- unsigned int in_size : 3;
- unsigned int in_last : 2;
- unsigned int in_strb : 4;
- unsigned int out_src : 1;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_pdp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228
-
-/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int dmc1_usr : 1;
- unsigned int out_strb : 5;
- unsigned int in_src : 3;
- unsigned int in_size : 3;
- unsigned int in_last : 2;
- unsigned int in_strb : 4;
- unsigned int out_src : 1;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_pdp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int sdp_out0_strb : 3;
- unsigned int sdp_out1_strb : 3;
- unsigned int sdp_in0_data : 3;
- unsigned int sdp_in0_last : 2;
- unsigned int sdp_in0_strb : 3;
- unsigned int sdp_in1_data : 3;
- unsigned int sdp_in1_last : 2;
- unsigned int sdp_in1_strb : 3;
- unsigned int dummy1 : 10;
-} reg_iop_sw_cfg_rw_sdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236
-#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236
-
-
-/* Constants */
-enum {
- regk_iop_sw_cfg_a = 0x00000001,
- regk_iop_sw_cfg_b = 0x00000002,
- regk_iop_sw_cfg_bus0 = 0x00000000,
- regk_iop_sw_cfg_bus0_rot16 = 0x00000004,
- regk_iop_sw_cfg_bus0_rot24 = 0x00000006,
- regk_iop_sw_cfg_bus0_rot8 = 0x00000002,
- regk_iop_sw_cfg_bus1 = 0x00000001,
- regk_iop_sw_cfg_bus1_rot16 = 0x00000005,
- regk_iop_sw_cfg_bus1_rot24 = 0x00000007,
- regk_iop_sw_cfg_bus1_rot8 = 0x00000003,
- regk_iop_sw_cfg_clk12 = 0x00000000,
- regk_iop_sw_cfg_cpu = 0x00000000,
- regk_iop_sw_cfg_dmc0 = 0x00000000,
- regk_iop_sw_cfg_dmc1 = 0x00000001,
- regk_iop_sw_cfg_gated_clk0 = 0x00000010,
- regk_iop_sw_cfg_gated_clk1 = 0x00000011,
- regk_iop_sw_cfg_gated_clk2 = 0x00000012,
- regk_iop_sw_cfg_gated_clk3 = 0x00000013,
- regk_iop_sw_cfg_gio0 = 0x00000004,
- regk_iop_sw_cfg_gio1 = 0x00000001,
- regk_iop_sw_cfg_gio2 = 0x00000005,
- regk_iop_sw_cfg_gio3 = 0x00000002,
- regk_iop_sw_cfg_gio4 = 0x00000006,
- regk_iop_sw_cfg_gio5 = 0x00000003,
- regk_iop_sw_cfg_gio6 = 0x00000007,
- regk_iop_sw_cfg_gio7 = 0x00000004,
- regk_iop_sw_cfg_gio_in0 = 0x00000000,
- regk_iop_sw_cfg_gio_in1 = 0x00000001,
- regk_iop_sw_cfg_gio_in10 = 0x00000002,
- regk_iop_sw_cfg_gio_in11 = 0x00000003,
- regk_iop_sw_cfg_gio_in14 = 0x00000004,
- regk_iop_sw_cfg_gio_in15 = 0x00000005,
- regk_iop_sw_cfg_gio_in18 = 0x00000002,
- regk_iop_sw_cfg_gio_in19 = 0x00000003,
- regk_iop_sw_cfg_gio_in20 = 0x00000004,
- regk_iop_sw_cfg_gio_in21 = 0x00000005,
- regk_iop_sw_cfg_gio_in26 = 0x00000006,
- regk_iop_sw_cfg_gio_in27 = 0x00000007,
- regk_iop_sw_cfg_gio_in28 = 0x00000006,
- regk_iop_sw_cfg_gio_in29 = 0x00000007,
- regk_iop_sw_cfg_gio_in4 = 0x00000000,
- regk_iop_sw_cfg_gio_in5 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002,
- regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003,
- regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002,
- regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003,
- regk_iop_sw_cfg_mpu = 0x00000001,
- regk_iop_sw_cfg_none = 0x00000000,
- regk_iop_sw_cfg_par0 = 0x00000000,
- regk_iop_sw_cfg_par1 = 0x00000001,
- regk_iop_sw_cfg_pdp_out0 = 0x00000002,
- regk_iop_sw_cfg_pdp_out0_hi = 0x00000001,
- regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005,
- regk_iop_sw_cfg_pdp_out0_lo = 0x00000000,
- regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004,
- regk_iop_sw_cfg_pdp_out1 = 0x00000003,
- regk_iop_sw_cfg_pdp_out1_hi = 0x00000003,
- regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005,
- regk_iop_sw_cfg_pdp_out1_lo = 0x00000002,
- regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004,
- regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555,
- regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
- regk_iop_sw_cfg_sdp_out0 = 0x00000008,
- regk_iop_sw_cfg_sdp_out1 = 0x00000009,
- regk_iop_sw_cfg_size16 = 0x00000002,
- regk_iop_sw_cfg_size24 = 0x00000003,
- regk_iop_sw_cfg_size32 = 0x00000004,
- regk_iop_sw_cfg_size8 = 0x00000001,
- regk_iop_sw_cfg_spu0 = 0x00000002,
- regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006,
- regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006,
- regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007,
- regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007,
- regk_iop_sw_cfg_spu0_g0 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g1 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g2 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g3 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g4 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g5 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g6 = 0x0000000e,
- regk_iop_sw_cfg_spu0_g7 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gio0 = 0x00000000,
- regk_iop_sw_cfg_spu0_gio1 = 0x00000001,
- regk_iop_sw_cfg_spu0_gio2 = 0x00000000,
- regk_iop_sw_cfg_spu0_gio5 = 0x00000005,
- regk_iop_sw_cfg_spu0_gio6 = 0x00000006,
- regk_iop_sw_cfg_spu0_gio7 = 0x00000007,
- regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008,
- regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009,
- regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a,
- regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b,
- regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c,
- regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d,
- regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f,
- regk_iop_sw_cfg_spu0_gioout0 = 0x00000000,
- regk_iop_sw_cfg_spu0_gioout1 = 0x00000000,
- regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout2 = 0x00000002,
- regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout3 = 0x00000002,
- regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout4 = 0x00000004,
- regk_iop_sw_cfg_spu0_gioout5 = 0x00000004,
- regk_iop_sw_cfg_spu0_gioout6 = 0x00000006,
- regk_iop_sw_cfg_spu0_gioout7 = 0x00000006,
- regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e,
- regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e,
- regk_iop_sw_cfg_spu1 = 0x00000003,
- regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006,
- regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006,
- regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007,
- regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007,
- regk_iop_sw_cfg_spu1_g0 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g1 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g2 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g3 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g4 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g5 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g6 = 0x0000000f,
- regk_iop_sw_cfg_spu1_g7 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gio0 = 0x00000002,
- regk_iop_sw_cfg_spu1_gio1 = 0x00000003,
- regk_iop_sw_cfg_spu1_gio2 = 0x00000002,
- regk_iop_sw_cfg_spu1_gio5 = 0x00000005,
- regk_iop_sw_cfg_spu1_gio6 = 0x00000006,
- regk_iop_sw_cfg_spu1_gio7 = 0x00000007,
- regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008,
- regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009,
- regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a,
- regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b,
- regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c,
- regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d,
- regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e,
- regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout0 = 0x00000001,
- regk_iop_sw_cfg_spu1_gioout1 = 0x00000001,
- regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout2 = 0x00000003,
- regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout3 = 0x00000003,
- regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout4 = 0x00000005,
- regk_iop_sw_cfg_spu1_gioout5 = 0x00000005,
- regk_iop_sw_cfg_spu1_gioout6 = 0x00000007,
- regk_iop_sw_cfg_spu1_gioout7 = 0x00000007,
- regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f,
- regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f,
- regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
- regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001,
- regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003,
- regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003,
- regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002,
- regk_iop_sw_cfg_timer_grp0 = 0x00000000,
- regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a,
- regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004,
- regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004,
- regk_iop_sw_cfg_timer_grp1 = 0x00000000,
- regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b,
- regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005,
- regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005,
- regk_iop_sw_cfg_timer_grp2 = 0x00000000,
- regk_iop_sw_cfg_timer_grp2_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c,
- regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006,
- regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006,
- regk_iop_sw_cfg_timer_grp3 = 0x00000000,
- regk_iop_sw_cfg_timer_grp3_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d,
- regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007,
- regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007,
- regk_iop_sw_cfg_trig0_0 = 0x00000000,
- regk_iop_sw_cfg_trig0_1 = 0x00000000,
- regk_iop_sw_cfg_trig0_2 = 0x00000000,
- regk_iop_sw_cfg_trig0_3 = 0x00000000,
- regk_iop_sw_cfg_trig1_0 = 0x00000000,
- regk_iop_sw_cfg_trig1_1 = 0x00000000,
- regk_iop_sw_cfg_trig1_2 = 0x00000000,
- regk_iop_sw_cfg_trig1_3 = 0x00000000,
- regk_iop_sw_cfg_trig2_0 = 0x00000000,
- regk_iop_sw_cfg_trig2_1 = 0x00000000,
- regk_iop_sw_cfg_trig2_2 = 0x00000000,
- regk_iop_sw_cfg_trig2_3 = 0x00000000,
- regk_iop_sw_cfg_trig3_0 = 0x00000000,
- regk_iop_sw_cfg_trig3_1 = 0x00000000,
- regk_iop_sw_cfg_trig3_2 = 0x00000000,
- regk_iop_sw_cfg_trig3_3 = 0x00000000,
- regk_iop_sw_cfg_trig4_0 = 0x00000001,
- regk_iop_sw_cfg_trig4_1 = 0x00000001,
- regk_iop_sw_cfg_trig4_2 = 0x00000001,
- regk_iop_sw_cfg_trig4_3 = 0x00000001,
- regk_iop_sw_cfg_trig5_0 = 0x00000001,
- regk_iop_sw_cfg_trig5_1 = 0x00000001,
- regk_iop_sw_cfg_trig5_2 = 0x00000001,
- regk_iop_sw_cfg_trig5_3 = 0x00000001,
- regk_iop_sw_cfg_trig6_0 = 0x00000001,
- regk_iop_sw_cfg_trig6_1 = 0x00000001,
- regk_iop_sw_cfg_trig6_2 = 0x00000001,
- regk_iop_sw_cfg_trig6_3 = 0x00000001,
- regk_iop_sw_cfg_trig7_0 = 0x00000001,
- regk_iop_sw_cfg_trig7_1 = 0x00000001,
- regk_iop_sw_cfg_trig7_2 = 0x00000001,
- regk_iop_sw_cfg_trig7_3 = 0x00000001
-};
-#endif /* __iop_sw_cfg_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h
deleted file mode 100644
index 31055d3fcd76..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_cpu_defs.h
+++ /dev/null
@@ -1,854 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_h
-#define __iop_sw_cpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cpu */
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu0_mem : 1;
- unsigned int wr_spu1_mem : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_cpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu0 : 1;
- unsigned int busy_spu1 : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu0 : 1;
- unsigned int owned_by_spu1 : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_cpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
-
-/* Register r_bus0_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
-
-/* Register r_bus1_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_rw_intr0_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_rw_ack_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_r_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int spu1_8 : 1;
- unsigned int spu1_9 : 1;
- unsigned int spu1_10 : 1;
- unsigned int spu1_11 : 1;
- unsigned int spu1_12 : 1;
- unsigned int spu1_13 : 1;
- unsigned int spu1_14 : 1;
- unsigned int spu1_15 : 1;
-} reg_iop_sw_cpu_r_masked_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_rw_intr1_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_rw_ack_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_r_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int spu0_8 : 1;
- unsigned int spu0_9 : 1;
- unsigned int spu0_10 : 1;
- unsigned int spu0_11 : 1;
- unsigned int spu0_12 : 1;
- unsigned int spu0_13 : 1;
- unsigned int spu0_14 : 1;
- unsigned int spu0_15 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
-} reg_iop_sw_cpu_r_masked_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
-
-/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_rw_intr2_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
-
-/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
-
-/* Register r_intr2, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
-
-/* Register r_masked_intr2, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int spu0_0 : 1;
- unsigned int spu0_1 : 1;
- unsigned int spu0_2 : 1;
- unsigned int spu0_3 : 1;
- unsigned int spu0_4 : 1;
- unsigned int spu0_5 : 1;
- unsigned int spu0_6 : 1;
- unsigned int spu0_7 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_masked_intr2;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
-
-/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
-} reg_iop_sw_cpu_rw_intr3_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
-
-/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
-
-/* Register r_intr3, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
-} reg_iop_sw_cpu_r_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
-
-/* Register r_masked_intr3, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int spu1_0 : 1;
- unsigned int spu1_1 : 1;
- unsigned int spu1_2 : 1;
- unsigned int spu1_3 : 1;
- unsigned int spu1_4 : 1;
- unsigned int spu1_5 : 1;
- unsigned int spu1_6 : 1;
- unsigned int spu1_7 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
-} reg_iop_sw_cpu_r_masked_intr3;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
-
-
-/* Constants */
-enum {
- regk_iop_sw_cpu_copy = 0x00000000,
- regk_iop_sw_cpu_no = 0x00000000,
- regk_iop_sw_cpu_rd = 0x00000002,
- regk_iop_sw_cpu_reg_copy = 0x00000001,
- regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000,
- regk_iop_sw_cpu_wr = 0x00000003,
- regk_iop_sw_cpu_yes = 0x00000001
-};
-#endif /* __iop_sw_cpu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h
deleted file mode 100644
index 5038c08e8a95..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_mpu_defs.h
+++ /dev/null
@@ -1,894 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_h
-#define __iop_sw_mpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_mpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- * id: $Id: iop_sw_mpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_mpu */
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_mpu_rw_sw_cfg_owner;
-#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu0_mem : 1;
- unsigned int wr_spu1_mem : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_mpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 4
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 4
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 8
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 8
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 12
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 12
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 16
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 20
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu0 : 1;
- unsigned int busy_spu1 : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu0 : 1;
- unsigned int owned_by_spu1 : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_mpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 24
-
-/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask 28
-
-/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask 32
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask 36
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask 40
-
-/* Register r_bus0_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in 44
-
-/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask 48
-
-/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask 52
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask 56
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask 60
-
-/* Register r_bus1_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in 64
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 68
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 72
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 72
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 76
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 80
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 84
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 88
-#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 88
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 92
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp0_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 96
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 100
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 104
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr0 : 1;
- unsigned int spu1_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr1 : 1;
- unsigned int spu1_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr2 : 1;
- unsigned int spu1_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr3 : 1;
- unsigned int spu1_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 108
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp1_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 112
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 116
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 120
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr4 : 1;
- unsigned int spu1_intr4 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr5 : 1;
- unsigned int spu1_intr5 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr6 : 1;
- unsigned int spu1_intr6 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr7 : 1;
- unsigned int spu1_intr7 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 124
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp2_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 128
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 132
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 136
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr8 : 1;
- unsigned int spu1_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr9 : 1;
- unsigned int spu1_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr10 : 1;
- unsigned int spu1_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr11 : 1;
- unsigned int spu1_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 140
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_rw_intr_grp3_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 144
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int dummy1 : 6;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int dummy2 : 6;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int dummy3 : 6;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int dummy4 : 6;
-} reg_iop_sw_mpu_rw_ack_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 148
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 152
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu0_intr12 : 1;
- unsigned int spu1_intr12 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int spu0_intr13 : 1;
- unsigned int spu1_intr13 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int dmc_in0 : 1;
- unsigned int spu0_intr14 : 1;
- unsigned int spu1_intr14 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int dmc_out1 : 1;
- unsigned int spu0_intr15 : 1;
- unsigned int spu1_intr15 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int dmc_in1 : 1;
-} reg_iop_sw_mpu_r_masked_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 156
-
-
-/* Constants */
-enum {
- regk_iop_sw_mpu_copy = 0x00000000,
- regk_iop_sw_mpu_cpu = 0x00000000,
- regk_iop_sw_mpu_mpu = 0x00000001,
- regk_iop_sw_mpu_no = 0x00000000,
- regk_iop_sw_mpu_nop = 0x00000000,
- regk_iop_sw_mpu_rd = 0x00000002,
- regk_iop_sw_mpu_reg_copy = 0x00000001,
- regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
- regk_iop_sw_mpu_set = 0x00000001,
- regk_iop_sw_mpu_spu0 = 0x00000002,
- regk_iop_sw_mpu_spu1 = 0x00000003,
- regk_iop_sw_mpu_wr = 0x00000003,
- regk_iop_sw_mpu_yes = 0x00000001
-};
-#endif /* __iop_sw_mpu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h
deleted file mode 100644
index aeebd57af7f7..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_h
-#define __iop_sw_spu_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:10:19 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- * id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_spu */
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu0_mem : 1;
- unsigned int wr_spu1_mem : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_spu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-typedef unsigned int reg_iop_sw_spu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu0 : 1;
- unsigned int busy_spu1 : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu0 : 1;
- unsigned int owned_by_spu1 : 1;
- unsigned int dummy1 : 24;
-} reg_iop_sw_spu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus0_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus0_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus0_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus0_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
-
-/* Register r_bus0_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus0_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus1_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus1_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus1_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus1_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
-
-/* Register r_bus1_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus1_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
-
-/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
-
-/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
-
-/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
-
-/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus0_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
-#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
-
-/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
-
-/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
-
-/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
-
-/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus1_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
-#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
-#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int timer_grp2 : 1;
- unsigned int timer_grp3 : 1;
- unsigned int fifo_out0 : 1;
- unsigned int fifo_out0_extra : 1;
- unsigned int fifo_in0 : 1;
- unsigned int fifo_in0_extra : 1;
- unsigned int fifo_out1 : 1;
- unsigned int fifo_out1_extra : 1;
- unsigned int fifo_in1 : 1;
- unsigned int fifo_in1_extra : 1;
- unsigned int dmc_out0 : 1;
- unsigned int dmc_in0 : 1;
- unsigned int dmc_out1 : 1;
- unsigned int dmc_in1 : 1;
- unsigned int dummy1 : 8;
-} reg_iop_sw_spu_r_hw_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
-#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int other_spu_intr0 : 1;
- unsigned int other_spu_intr1 : 1;
- unsigned int other_spu_intr2 : 1;
- unsigned int other_spu_intr3 : 1;
- unsigned int other_spu_intr4 : 1;
- unsigned int other_spu_intr5 : 1;
- unsigned int other_spu_intr6 : 1;
- unsigned int other_spu_intr7 : 1;
- unsigned int other_spu_intr8 : 1;
- unsigned int other_spu_intr9 : 1;
- unsigned int other_spu_intr10 : 1;
- unsigned int other_spu_intr11 : 1;
- unsigned int other_spu_intr12 : 1;
- unsigned int other_spu_intr13 : 1;
- unsigned int other_spu_intr14 : 1;
- unsigned int other_spu_intr15 : 1;
-} reg_iop_sw_spu_r_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
-
-
-/* Constants */
-enum {
- regk_iop_sw_spu_copy = 0x00000000,
- regk_iop_sw_spu_no = 0x00000000,
- regk_iop_sw_spu_nop = 0x00000000,
- regk_iop_sw_spu_rd = 0x00000002,
- regk_iop_sw_spu_reg_copy = 0x00000001,
- regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_spu_set = 0x00000001,
- regk_iop_sw_spu_wr = 0x00000003,
- regk_iop_sw_spu_yes = 0x00000001
-};
-#endif /* __iop_sw_spu_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h
deleted file mode 100644
index b4095422adf6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_timer_grp_defs.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_timer_grp_defs_h
-#define __iop_timer_grp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_timer_grp_defs.h ../../inst/io_proc/rtl/iop_timer_grp.r
- * id: $Id: iop_timer_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_timer_grp */
-
-/* Register rw_cfg, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int clk_src : 1;
- unsigned int trig : 2;
- unsigned int clk_gen_div : 8;
- unsigned int clk_div : 8;
- unsigned int dummy1 : 13;
-} reg_iop_timer_grp_rw_cfg;
-#define REG_RD_ADDR_iop_timer_grp_rw_cfg 0
-#define REG_WR_ADDR_iop_timer_grp_rw_cfg 0
-
-/* Register rw_half_period, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int quota_lo : 15;
- unsigned int quota_hi : 15;
- unsigned int quota_hi_sel : 1;
- unsigned int dummy1 : 1;
-} reg_iop_timer_grp_rw_half_period;
-#define REG_RD_ADDR_iop_timer_grp_rw_half_period 4
-#define REG_WR_ADDR_iop_timer_grp_rw_half_period 4
-
-/* Register rw_half_period_len, scope iop_timer_grp, type rw */
-typedef unsigned int reg_iop_timer_grp_rw_half_period_len;
-#define REG_RD_ADDR_iop_timer_grp_rw_half_period_len 8
-#define REG_WR_ADDR_iop_timer_grp_rw_half_period_len 8
-
-#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
-/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int clk_src : 3;
- unsigned int strb : 2;
- unsigned int run_mode : 2;
- unsigned int out_mode : 1;
- unsigned int active_on_tmr : 2;
- unsigned int inv : 1;
- unsigned int en_by_tmr : 2;
- unsigned int dis_by_tmr : 2;
- unsigned int en_only_by_reg : 1;
- unsigned int dis_only_by_reg : 1;
- unsigned int rst_at_en_strb : 1;
- unsigned int dummy1 : 14;
-} reg_iop_timer_grp_rw_tmr_cfg;
-#define REG_RD_ADDR_iop_timer_grp_rw_tmr_cfg 12
-#define REG_WR_ADDR_iop_timer_grp_rw_tmr_cfg 12
-
-#define STRIDE_iop_timer_grp_rw_tmr_len 4
-/* Register rw_tmr_len, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rw_tmr_len;
-#define REG_RD_ADDR_iop_timer_grp_rw_tmr_len 44
-#define REG_WR_ADDR_iop_timer_grp_rw_tmr_len 44
-
-/* Register rw_cmd, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int rst : 4;
- unsigned int en : 4;
- unsigned int dis : 4;
- unsigned int strb : 4;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rw_cmd;
-#define REG_RD_ADDR_iop_timer_grp_rw_cmd 60
-#define REG_WR_ADDR_iop_timer_grp_rw_cmd 60
-
-/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
-typedef unsigned int reg_iop_timer_grp_r_clk_gen_cnt;
-#define REG_RD_ADDR_iop_timer_grp_r_clk_gen_cnt 64
-
-#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
-/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_rs_tmr_cnt;
-#define REG_RD_ADDR_iop_timer_grp_rs_tmr_cnt 68
-
-#define STRIDE_iop_timer_grp_r_tmr_cnt 8
-/* Register r_tmr_cnt, scope iop_timer_grp, type r */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_timer_grp_r_tmr_cnt;
-#define REG_RD_ADDR_iop_timer_grp_r_tmr_cnt 72
-
-/* Register rw_intr_mask, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_rw_intr_mask;
-#define REG_RD_ADDR_iop_timer_grp_rw_intr_mask 100
-#define REG_WR_ADDR_iop_timer_grp_rw_intr_mask 100
-
-/* Register rw_ack_intr, scope iop_timer_grp, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_rw_ack_intr;
-#define REG_RD_ADDR_iop_timer_grp_rw_ack_intr 104
-#define REG_WR_ADDR_iop_timer_grp_rw_ack_intr 104
-
-/* Register r_intr, scope iop_timer_grp, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_r_intr;
-#define REG_RD_ADDR_iop_timer_grp_r_intr 108
-
-/* Register r_masked_intr, scope iop_timer_grp, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int tmr2 : 1;
- unsigned int tmr3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_timer_grp_r_masked_intr;
-#define REG_RD_ADDR_iop_timer_grp_r_masked_intr 112
-
-
-/* Constants */
-enum {
- regk_iop_timer_grp_clk200 = 0x00000000,
- regk_iop_timer_grp_clk_gen = 0x00000002,
- regk_iop_timer_grp_complete = 0x00000002,
- regk_iop_timer_grp_div_clk200 = 0x00000001,
- regk_iop_timer_grp_div_clk_gen = 0x00000003,
- regk_iop_timer_grp_ext = 0x00000001,
- regk_iop_timer_grp_hi = 0x00000000,
- regk_iop_timer_grp_long_period = 0x00000001,
- regk_iop_timer_grp_neg = 0x00000002,
- regk_iop_timer_grp_no = 0x00000000,
- regk_iop_timer_grp_once = 0x00000003,
- regk_iop_timer_grp_pause = 0x00000001,
- regk_iop_timer_grp_pos = 0x00000001,
- regk_iop_timer_grp_pos_neg = 0x00000003,
- regk_iop_timer_grp_pulse = 0x00000000,
- regk_iop_timer_grp_r_tmr_cnt_size = 0x00000004,
- regk_iop_timer_grp_rs_tmr_cnt_size = 0x00000004,
- regk_iop_timer_grp_rw_cfg_default = 0x00000002,
- regk_iop_timer_grp_rw_intr_mask_default = 0x00000000,
- regk_iop_timer_grp_rw_tmr_cfg_default0 = 0x00018000,
- regk_iop_timer_grp_rw_tmr_cfg_default1 = 0x0001a900,
- regk_iop_timer_grp_rw_tmr_cfg_default2 = 0x0001d200,
- regk_iop_timer_grp_rw_tmr_cfg_default3 = 0x0001fb00,
- regk_iop_timer_grp_rw_tmr_cfg_size = 0x00000004,
- regk_iop_timer_grp_rw_tmr_len_default = 0x00000000,
- regk_iop_timer_grp_rw_tmr_len_size = 0x00000004,
- regk_iop_timer_grp_short_period = 0x00000000,
- regk_iop_timer_grp_stop = 0x00000000,
- regk_iop_timer_grp_tmr = 0x00000004,
- regk_iop_timer_grp_toggle = 0x00000001,
- regk_iop_timer_grp_yes = 0x00000001
-};
-#endif /* __iop_timer_grp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h
deleted file mode 100644
index aff694506e7f..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_trigger_grp_defs.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_trigger_grp_defs_h
-#define __iop_trigger_grp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
- * last modfied: Mon Apr 11 16:08:46 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_trigger_grp_defs.h ../../inst/io_proc/rtl/iop_trigger_grp.r
- * id: $Id: iop_trigger_grp_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_trigger_grp */
-
-#define STRIDE_iop_trigger_grp_rw_cfg 4
-/* Register rw_cfg, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int action : 2;
- unsigned int once : 1;
- unsigned int trig : 3;
- unsigned int en_only_by_reg : 1;
- unsigned int dis_only_by_reg : 1;
- unsigned int dummy1 : 24;
-} reg_iop_trigger_grp_rw_cfg;
-#define REG_RD_ADDR_iop_trigger_grp_rw_cfg 0
-#define REG_WR_ADDR_iop_trigger_grp_rw_cfg 0
-
-/* Register rw_cmd, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int dis : 4;
- unsigned int en : 4;
- unsigned int dummy1 : 24;
-} reg_iop_trigger_grp_rw_cmd;
-#define REG_RD_ADDR_iop_trigger_grp_rw_cmd 16
-#define REG_WR_ADDR_iop_trigger_grp_rw_cmd 16
-
-/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_rw_intr_mask;
-#define REG_RD_ADDR_iop_trigger_grp_rw_intr_mask 20
-#define REG_WR_ADDR_iop_trigger_grp_rw_intr_mask 20
-
-/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_rw_ack_intr;
-#define REG_RD_ADDR_iop_trigger_grp_rw_ack_intr 24
-#define REG_WR_ADDR_iop_trigger_grp_rw_ack_intr 24
-
-/* Register r_intr, scope iop_trigger_grp, type r */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_r_intr;
-#define REG_RD_ADDR_iop_trigger_grp_r_intr 28
-
-/* Register r_masked_intr, scope iop_trigger_grp, type r */
-typedef struct {
- unsigned int trig0 : 1;
- unsigned int trig1 : 1;
- unsigned int trig2 : 1;
- unsigned int trig3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_trigger_grp_r_masked_intr;
-#define REG_RD_ADDR_iop_trigger_grp_r_masked_intr 32
-
-
-/* Constants */
-enum {
- regk_iop_trigger_grp_fall = 0x00000002,
- regk_iop_trigger_grp_fall_lo = 0x00000006,
- regk_iop_trigger_grp_no = 0x00000000,
- regk_iop_trigger_grp_off = 0x00000000,
- regk_iop_trigger_grp_pulse = 0x00000000,
- regk_iop_trigger_grp_rise = 0x00000001,
- regk_iop_trigger_grp_rise_fall = 0x00000003,
- regk_iop_trigger_grp_rise_fall_hi = 0x00000007,
- regk_iop_trigger_grp_rise_fall_lo = 0x00000004,
- regk_iop_trigger_grp_rise_hi = 0x00000005,
- regk_iop_trigger_grp_rw_cfg_default = 0x000000c0,
- regk_iop_trigger_grp_rw_cfg_size = 0x00000004,
- regk_iop_trigger_grp_rw_intr_mask_default = 0x00000000,
- regk_iop_trigger_grp_toggle = 0x00000003,
- regk_iop_trigger_grp_yes = 0x00000001
-};
-#endif /* __iop_trigger_grp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h
deleted file mode 100644
index 53a4b8cda969..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/iop_version_defs.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_h
-#define __iop_version_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
- * last modfied: Mon Apr 11 16:08:44 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_version_defs.h ../../inst/io_proc/rtl/guinness/iop_version.r
- * id: $Id: iop_version_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_version */
-
-/* Register r_version, scope iop_version, type r */
-typedef struct {
- unsigned int nr : 8;
- unsigned int dummy1 : 24;
-} reg_iop_version_r_version;
-#define REG_RD_ADDR_iop_version_r_version 0
-
-
-/* Constants */
-enum {
- regk_iop_version_v1_0 = 0x00000001
-};
-#endif /* __iop_version_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h b/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h
deleted file mode 100644
index 63b20dee2fd1..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/irq_nmi_defs.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __irq_nmi_defs_h
-#define __irq_nmi_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/irq_nmi.r
- * id: <not found>
- * last modfied: Thu Jan 22 09:22:43 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile irq_nmi_defs.h ../../mod/irq_nmi.r
- * id: $Id: irq_nmi_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope irq_nmi */
-
-/* Register rw_cmd, scope irq_nmi, type rw */
-typedef struct {
- unsigned int delay : 16;
- unsigned int op : 2;
- unsigned int dummy1 : 14;
-} reg_irq_nmi_rw_cmd;
-#define REG_RD_ADDR_irq_nmi_rw_cmd 0
-#define REG_WR_ADDR_irq_nmi_rw_cmd 0
-
-
-/* Constants */
-enum {
- regk_irq_nmi_ack_irq = 0x00000002,
- regk_irq_nmi_ack_nmi = 0x00000003,
- regk_irq_nmi_irq = 0x00000000,
- regk_irq_nmi_nmi = 0x00000001
-};
-#endif /* __irq_nmi_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h
deleted file mode 100644
index da29a8a22250..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/marb_bp_defs.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Fri Nov 7 15:36:04 2003
- *
- * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_bp_defs.h,v 1.2 2004/06/04 07:15:33 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_break_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_addr;
-#define REG_RD_ADDR_marb_bp_r_break_addr 20
-
-/* Register r_break_op, scope marb_bp, type r */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_break_op;
-#define REG_RD_ADDR_marb_bp_r_break_op 24
-
-/* Register r_break_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_clients;
-#define REG_RD_ADDR_marb_bp_r_break_clients 28
-
-/* Register r_break_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_first_client;
-#define REG_RD_ADDR_marb_bp_r_break_first_client 32
-
-/* Register r_break_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_size;
-#define REG_RD_ADDR_marb_bp_r_break_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h b/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h
deleted file mode 100644
index 2858de48a5e0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/marb_defs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_defs_h
-#define __marb_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb */
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_int_slots;
-#define REG_RD_ADDR_marb_rw_int_slots 0
-#define REG_WR_ADDR_marb_rw_int_slots 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ext_slots;
-#define REG_RD_ADDR_marb_rw_ext_slots 256
-#define REG_WR_ADDR_marb_rw_ext_slots 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_regs_slots;
-#define REG_RD_ADDR_marb_rw_regs_slots 512
-#define REG_WR_ADDR_marb_rw_regs_slots 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_intr_mask;
-#define REG_RD_ADDR_marb_rw_intr_mask 528
-#define REG_WR_ADDR_marb_rw_intr_mask 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ack_intr;
-#define REG_RD_ADDR_marb_rw_ack_intr 532
-#define REG_WR_ADDR_marb_rw_ack_intr 532
-
-/* Register r_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_intr;
-#define REG_RD_ADDR_marb_r_intr 536
-
-/* Register r_masked_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_masked_intr;
-#define REG_RD_ADDR_marb_r_masked_intr 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_stop_mask;
-#define REG_RD_ADDR_marb_rw_stop_mask 544
-#define REG_WR_ADDR_marb_rw_stop_mask 544
-
-/* Register r_stopped, scope marb, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_r_stopped;
-#define REG_RD_ADDR_marb_r_stopped 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_no_snoop;
-#define REG_RD_ADDR_marb_rw_no_snoop 832
-#define REG_WR_ADDR_marb_rw_no_snoop 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-typedef struct {
- unsigned int dummy1 : 10;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int dummy2 : 20;
-} reg_marb_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
-#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
-
-
-/* Constants */
-enum {
- regk_marb_cpud = 0x0000000b,
- regk_marb_cpui = 0x0000000a,
- regk_marb_dma0 = 0x00000000,
- regk_marb_dma1 = 0x00000001,
- regk_marb_dma2 = 0x00000002,
- regk_marb_dma3 = 0x00000003,
- regk_marb_dma4 = 0x00000004,
- regk_marb_dma5 = 0x00000005,
- regk_marb_dma6 = 0x00000006,
- regk_marb_dma7 = 0x00000007,
- regk_marb_dma8 = 0x00000008,
- regk_marb_dma9 = 0x00000009,
- regk_marb_iop = 0x0000000c,
- regk_marb_no = 0x00000000,
- regk_marb_r_stopped_default = 0x00000000,
- regk_marb_rw_ext_slots_default = 0x00000000,
- regk_marb_rw_ext_slots_size = 0x00000040,
- regk_marb_rw_int_slots_default = 0x00000000,
- regk_marb_rw_int_slots_size = 0x00000040,
- regk_marb_rw_intr_mask_default = 0x00000000,
- regk_marb_rw_no_snoop_default = 0x00000000,
- regk_marb_rw_no_snoop_rq_default = 0x00000000,
- regk_marb_rw_regs_slots_default = 0x00000000,
- regk_marb_rw_regs_slots_size = 0x00000004,
- regk_marb_rw_stop_mask_default = 0x00000000,
- regk_marb_slave = 0x0000000d,
- regk_marb_yes = 0x00000001
-};
-#endif /* __marb_defs_h */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h b/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h
deleted file mode 100644
index 8fabdd211507..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/reg_rdwr.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Read/write register macros used by *_defs.h
- */
-
-#ifndef reg_rdwr_h
-#define reg_rdwr_h
-
-#ifndef REG_READ
-#define REG_READ(type, addr) (*((volatile type *) (addr)))
-#endif
-
-#ifndef REG_WRITE
-#define REG_WRITE(type, addr, val) \
- do { *((volatile type *) (addr)) = (val); } while(0)
-#endif
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h b/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h
deleted file mode 100644
index ebb6bbc6e778..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/rt_trace_defs.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __rt_trace_defs_h
-#define __rt_trace_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/rt_trace/rtl/rt_regs.r
- * id: rt_regs.r,v 1.18 2005/02/08 15:45:00 stefans Exp
- * last modfied: Mon Apr 11 16:09:14 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile rt_trace_defs.h ../../inst/rt_trace/rtl/rt_regs.r
- * id: $Id: rt_trace_defs.h,v 1.1 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope rt_trace */
-
-/* Register rw_cfg, scope rt_trace, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int mode : 1;
- unsigned int owner : 1;
- unsigned int wp : 1;
- unsigned int stall : 1;
- unsigned int dummy1 : 3;
- unsigned int wp_start : 7;
- unsigned int dummy2 : 1;
- unsigned int wp_stop : 7;
- unsigned int dummy3 : 9;
-} reg_rt_trace_rw_cfg;
-#define REG_RD_ADDR_rt_trace_rw_cfg 0
-#define REG_WR_ADDR_rt_trace_rw_cfg 0
-
-/* Register rw_tap_ctrl, scope rt_trace, type rw */
-typedef struct {
- unsigned int ack_data : 1;
- unsigned int ack_guru : 1;
- unsigned int dummy1 : 30;
-} reg_rt_trace_rw_tap_ctrl;
-#define REG_RD_ADDR_rt_trace_rw_tap_ctrl 4
-#define REG_WR_ADDR_rt_trace_rw_tap_ctrl 4
-
-/* Register r_tap_stat, scope rt_trace, type r */
-typedef struct {
- unsigned int dav : 1;
- unsigned int empty : 1;
- unsigned int dummy1 : 30;
-} reg_rt_trace_r_tap_stat;
-#define REG_RD_ADDR_rt_trace_r_tap_stat 8
-
-/* Register rw_tap_data, scope rt_trace, type rw */
-typedef unsigned int reg_rt_trace_rw_tap_data;
-#define REG_RD_ADDR_rt_trace_rw_tap_data 12
-#define REG_WR_ADDR_rt_trace_rw_tap_data 12
-
-/* Register rw_tap_hdata, scope rt_trace, type rw */
-typedef struct {
- unsigned int op : 4;
- unsigned int sub_op : 4;
- unsigned int dummy1 : 24;
-} reg_rt_trace_rw_tap_hdata;
-#define REG_RD_ADDR_rt_trace_rw_tap_hdata 16
-#define REG_WR_ADDR_rt_trace_rw_tap_hdata 16
-
-/* Register r_redir, scope rt_trace, type r */
-typedef unsigned int reg_rt_trace_r_redir;
-#define REG_RD_ADDR_rt_trace_r_redir 20
-
-
-/* Constants */
-enum {
- regk_rt_trace_brk = 0x0000000c,
- regk_rt_trace_dbg = 0x00000003,
- regk_rt_trace_dbgdi = 0x00000004,
- regk_rt_trace_dbgdo = 0x00000005,
- regk_rt_trace_gmode = 0x00000000,
- regk_rt_trace_no = 0x00000000,
- regk_rt_trace_nop = 0x00000000,
- regk_rt_trace_normal = 0x00000000,
- regk_rt_trace_rdmem = 0x00000007,
- regk_rt_trace_rdmemb = 0x00000009,
- regk_rt_trace_rdpreg = 0x00000002,
- regk_rt_trace_rdreg = 0x00000001,
- regk_rt_trace_rdsreg = 0x00000003,
- regk_rt_trace_redir = 0x00000006,
- regk_rt_trace_ret = 0x0000000b,
- regk_rt_trace_rw_cfg_default = 0x00000000,
- regk_rt_trace_trcfg = 0x00000001,
- regk_rt_trace_wp = 0x00000001,
- regk_rt_trace_wp0 = 0x00000001,
- regk_rt_trace_wp1 = 0x00000002,
- regk_rt_trace_wp2 = 0x00000004,
- regk_rt_trace_wp3 = 0x00000008,
- regk_rt_trace_wp4 = 0x00000010,
- regk_rt_trace_wp5 = 0x00000020,
- regk_rt_trace_wp6 = 0x00000040,
- regk_rt_trace_wrmem = 0x00000008,
- regk_rt_trace_wrmemb = 0x0000000a,
- regk_rt_trace_wrpreg = 0x00000005,
- regk_rt_trace_wrreg = 0x00000004,
- regk_rt_trace_wrsreg = 0x00000006,
- regk_rt_trace_yes = 0x00000001
-};
-#endif /* __rt_trace_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h
deleted file mode 100644
index 3b04cf9012cf..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/ser_defs.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ser_defs_h
-#define __ser_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/ser/rtl/ser_regs.r
- * id: ser_regs.r,v 1.23 2005/02/08 13:58:35 perz Exp
- * last modfied: Mon Apr 11 16:09:21 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile ser_defs.h ../../inst/ser/rtl/ser_regs.r
- * id: $Id: ser_defs.h,v 1.10 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ser */
-
-/* Register rw_tr_ctrl, scope ser, type rw */
-typedef struct {
- unsigned int base_freq : 3;
- unsigned int en : 1;
- unsigned int par : 2;
- unsigned int par_en : 1;
- unsigned int data_bits : 1;
- unsigned int stop_bits : 1;
- unsigned int stop : 1;
- unsigned int rts_delay : 3;
- unsigned int rts_setup : 1;
- unsigned int auto_rts : 1;
- unsigned int txd : 1;
- unsigned int auto_cts : 1;
- unsigned int dummy1 : 15;
-} reg_ser_rw_tr_ctrl;
-#define REG_RD_ADDR_ser_rw_tr_ctrl 0
-#define REG_WR_ADDR_ser_rw_tr_ctrl 0
-
-/* Register rw_tr_dma_en, scope ser, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_ser_rw_tr_dma_en;
-#define REG_RD_ADDR_ser_rw_tr_dma_en 4
-#define REG_WR_ADDR_ser_rw_tr_dma_en 4
-
-/* Register rw_rec_ctrl, scope ser, type rw */
-typedef struct {
- unsigned int base_freq : 3;
- unsigned int en : 1;
- unsigned int par : 2;
- unsigned int par_en : 1;
- unsigned int data_bits : 1;
- unsigned int dma_mode : 1;
- unsigned int dma_err : 1;
- unsigned int sampling : 1;
- unsigned int timeout : 3;
- unsigned int auto_eop : 1;
- unsigned int half_duplex : 1;
- unsigned int rts_n : 1;
- unsigned int loopback : 1;
- unsigned int dummy1 : 14;
-} reg_ser_rw_rec_ctrl;
-#define REG_RD_ADDR_ser_rw_rec_ctrl 8
-#define REG_WR_ADDR_ser_rw_rec_ctrl 8
-
-/* Register rw_tr_baud_div, scope ser, type rw */
-typedef struct {
- unsigned int div : 16;
- unsigned int dummy1 : 16;
-} reg_ser_rw_tr_baud_div;
-#define REG_RD_ADDR_ser_rw_tr_baud_div 12
-#define REG_WR_ADDR_ser_rw_tr_baud_div 12
-
-/* Register rw_rec_baud_div, scope ser, type rw */
-typedef struct {
- unsigned int div : 16;
- unsigned int dummy1 : 16;
-} reg_ser_rw_rec_baud_div;
-#define REG_RD_ADDR_ser_rw_rec_baud_div 16
-#define REG_WR_ADDR_ser_rw_rec_baud_div 16
-
-/* Register rw_xoff, scope ser, type rw */
-typedef struct {
- unsigned int chr : 8;
- unsigned int automatic : 1;
- unsigned int dummy1 : 23;
-} reg_ser_rw_xoff;
-#define REG_RD_ADDR_ser_rw_xoff 20
-#define REG_WR_ADDR_ser_rw_xoff 20
-
-/* Register rw_xoff_clr, scope ser, type rw */
-typedef struct {
- unsigned int clr : 1;
- unsigned int dummy1 : 31;
-} reg_ser_rw_xoff_clr;
-#define REG_RD_ADDR_ser_rw_xoff_clr 24
-#define REG_WR_ADDR_ser_rw_xoff_clr 24
-
-/* Register rw_dout, scope ser, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_ser_rw_dout;
-#define REG_RD_ADDR_ser_rw_dout 28
-#define REG_WR_ADDR_ser_rw_dout 28
-
-/* Register rs_stat_din, scope ser, type rs */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 8;
- unsigned int dav : 1;
- unsigned int framing_err : 1;
- unsigned int par_err : 1;
- unsigned int orun : 1;
- unsigned int rec_err : 1;
- unsigned int rxd : 1;
- unsigned int tr_idle : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_rdy : 1;
- unsigned int cts_n : 1;
- unsigned int xoff_detect : 1;
- unsigned int rts_n : 1;
- unsigned int txd : 1;
- unsigned int dummy2 : 3;
-} reg_ser_rs_stat_din;
-#define REG_RD_ADDR_ser_rs_stat_din 32
-
-/* Register r_stat_din, scope ser, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 8;
- unsigned int dav : 1;
- unsigned int framing_err : 1;
- unsigned int par_err : 1;
- unsigned int orun : 1;
- unsigned int rec_err : 1;
- unsigned int rxd : 1;
- unsigned int tr_idle : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_rdy : 1;
- unsigned int cts_n : 1;
- unsigned int xoff_detect : 1;
- unsigned int rts_n : 1;
- unsigned int txd : 1;
- unsigned int dummy2 : 3;
-} reg_ser_r_stat_din;
-#define REG_RD_ADDR_ser_r_stat_din 36
-
-/* Register rw_rec_eop, scope ser, type rw */
-typedef struct {
- unsigned int set : 1;
- unsigned int dummy1 : 31;
-} reg_ser_rw_rec_eop;
-#define REG_RD_ADDR_ser_rw_rec_eop 40
-#define REG_WR_ADDR_ser_rw_rec_eop 40
-
-/* Register rw_intr_mask, scope ser, type rw */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_rw_intr_mask;
-#define REG_RD_ADDR_ser_rw_intr_mask 44
-#define REG_WR_ADDR_ser_rw_intr_mask 44
-
-/* Register rw_ack_intr, scope ser, type rw */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_rw_ack_intr;
-#define REG_RD_ADDR_ser_rw_ack_intr 48
-#define REG_WR_ADDR_ser_rw_ack_intr 48
-
-/* Register r_intr, scope ser, type r */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_r_intr;
-#define REG_RD_ADDR_ser_r_intr 52
-
-/* Register r_masked_intr, scope ser, type r */
-typedef struct {
- unsigned int tr_rdy : 1;
- unsigned int tr_empty : 1;
- unsigned int tr_idle : 1;
- unsigned int dav : 1;
- unsigned int dummy1 : 28;
-} reg_ser_r_masked_intr;
-#define REG_RD_ADDR_ser_r_masked_intr 56
-
-
-/* Constants */
-enum {
- regk_ser_active = 0x00000000,
- regk_ser_bits1 = 0x00000000,
- regk_ser_bits2 = 0x00000001,
- regk_ser_bits7 = 0x00000001,
- regk_ser_bits8 = 0x00000000,
- regk_ser_del0_5 = 0x00000000,
- regk_ser_del1 = 0x00000001,
- regk_ser_del1_5 = 0x00000002,
- regk_ser_del2 = 0x00000003,
- regk_ser_del2_5 = 0x00000004,
- regk_ser_del3 = 0x00000005,
- regk_ser_del3_5 = 0x00000006,
- regk_ser_del4 = 0x00000007,
- regk_ser_even = 0x00000000,
- regk_ser_ext = 0x00000001,
- regk_ser_f100 = 0x00000007,
- regk_ser_f29_493 = 0x00000004,
- regk_ser_f32 = 0x00000005,
- regk_ser_f32_768 = 0x00000006,
- regk_ser_ignore = 0x00000001,
- regk_ser_inactive = 0x00000001,
- regk_ser_majority = 0x00000001,
- regk_ser_mark = 0x00000002,
- regk_ser_middle = 0x00000000,
- regk_ser_no = 0x00000000,
- regk_ser_odd = 0x00000001,
- regk_ser_off = 0x00000000,
- regk_ser_rw_intr_mask_default = 0x00000000,
- regk_ser_rw_rec_baud_div_default = 0x00000000,
- regk_ser_rw_rec_ctrl_default = 0x00010000,
- regk_ser_rw_tr_baud_div_default = 0x00000000,
- regk_ser_rw_tr_ctrl_default = 0x00008000,
- regk_ser_rw_tr_dma_en_default = 0x00000000,
- regk_ser_rw_xoff_default = 0x00000000,
- regk_ser_space = 0x00000003,
- regk_ser_stop = 0x00000000,
- regk_ser_yes = 0x00000001
-};
-#endif /* __ser_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h b/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h
deleted file mode 100644
index 02971f9b6558..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/sser_defs.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __sser_defs_h
-#define __sser_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/syncser/rtl/sser_regs.r
- * id: sser_regs.r,v 1.24 2005/02/11 14:27:36 gunnard Exp
- * last modfied: Mon Apr 11 16:09:48 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile sser_defs.h ../../inst/syncser/rtl/sser_regs.r
- * id: $Id: sser_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope sser */
-
-/* Register rw_cfg, scope sser, type rw */
-typedef struct {
- unsigned int clk_div : 16;
- unsigned int base_freq : 3;
- unsigned int gate_clk : 1;
- unsigned int clkgate_ctrl : 1;
- unsigned int clkgate_in : 1;
- unsigned int clk_dir : 1;
- unsigned int clk_od_mode : 1;
- unsigned int out_clk_pol : 1;
- unsigned int out_clk_src : 2;
- unsigned int clk_in_sel : 1;
- unsigned int hold_pol : 1;
- unsigned int prepare : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 1;
-} reg_sser_rw_cfg;
-#define REG_RD_ADDR_sser_rw_cfg 0
-#define REG_WR_ADDR_sser_rw_cfg 0
-
-/* Register rw_frm_cfg, scope sser, type rw */
-typedef struct {
- unsigned int wordrate : 10;
- unsigned int rec_delay : 3;
- unsigned int tr_delay : 3;
- unsigned int early_wend : 1;
- unsigned int level : 2;
- unsigned int type : 1;
- unsigned int clk_pol : 1;
- unsigned int fr_in_rxclk : 1;
- unsigned int clk_src : 1;
- unsigned int out_off : 1;
- unsigned int out_on : 1;
- unsigned int frame_pin_dir : 1;
- unsigned int frame_pin_use : 2;
- unsigned int status_pin_dir : 1;
- unsigned int status_pin_use : 2;
- unsigned int dummy1 : 1;
-} reg_sser_rw_frm_cfg;
-#define REG_RD_ADDR_sser_rw_frm_cfg 4
-#define REG_WR_ADDR_sser_rw_frm_cfg 4
-
-/* Register rw_tr_cfg, scope sser, type rw */
-typedef struct {
- unsigned int tr_en : 1;
- unsigned int stop : 1;
- unsigned int urun_stop : 1;
- unsigned int eop_stop : 1;
- unsigned int sample_size : 6;
- unsigned int sh_dir : 1;
- unsigned int clk_pol : 1;
- unsigned int clk_src : 1;
- unsigned int use_dma : 1;
- unsigned int mode : 2;
- unsigned int frm_src : 1;
- unsigned int use60958 : 1;
- unsigned int iec60958_ckdiv : 2;
- unsigned int rate_ctrl : 1;
- unsigned int use_md : 1;
- unsigned int dual_i2s : 1;
- unsigned int data_pin_use : 2;
- unsigned int od_mode : 1;
- unsigned int bulk_wspace : 2;
- unsigned int dummy1 : 4;
-} reg_sser_rw_tr_cfg;
-#define REG_RD_ADDR_sser_rw_tr_cfg 8
-#define REG_WR_ADDR_sser_rw_tr_cfg 8
-
-/* Register rw_rec_cfg, scope sser, type rw */
-typedef struct {
- unsigned int rec_en : 1;
- unsigned int force_eop : 1;
- unsigned int stop : 1;
- unsigned int orun_stop : 1;
- unsigned int eop_stop : 1;
- unsigned int sample_size : 6;
- unsigned int sh_dir : 1;
- unsigned int clk_pol : 1;
- unsigned int clk_src : 1;
- unsigned int use_dma : 1;
- unsigned int mode : 2;
- unsigned int frm_src : 2;
- unsigned int use60958 : 1;
- unsigned int iec60958_ui_len : 5;
- unsigned int slave2_en : 1;
- unsigned int slave3_en : 1;
- unsigned int fifo_thr : 2;
- unsigned int dummy1 : 3;
-} reg_sser_rw_rec_cfg;
-#define REG_RD_ADDR_sser_rw_rec_cfg 12
-#define REG_WR_ADDR_sser_rw_rec_cfg 12
-
-/* Register rw_tr_data, scope sser, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int md : 1;
- unsigned int dummy1 : 15;
-} reg_sser_rw_tr_data;
-#define REG_RD_ADDR_sser_rw_tr_data 16
-#define REG_WR_ADDR_sser_rw_tr_data 16
-
-/* Register r_rec_data, scope sser, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int md : 1;
- unsigned int ext_clk : 1;
- unsigned int status_in : 1;
- unsigned int frame_in : 1;
- unsigned int din : 1;
- unsigned int data_in : 1;
- unsigned int clk_in : 1;
- unsigned int dummy1 : 9;
-} reg_sser_r_rec_data;
-#define REG_RD_ADDR_sser_r_rec_data 20
-
-/* Register rw_extra, scope sser, type rw */
-typedef struct {
- unsigned int clkoff_cycles : 20;
- unsigned int clkoff_en : 1;
- unsigned int clkon_en : 1;
- unsigned int dout_delay : 5;
- unsigned int dummy1 : 5;
-} reg_sser_rw_extra;
-#define REG_RD_ADDR_sser_rw_extra 24
-#define REG_WR_ADDR_sser_rw_extra 24
-
-/* Register rw_intr_mask, scope sser, type rw */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_rw_intr_mask;
-#define REG_RD_ADDR_sser_rw_intr_mask 28
-#define REG_WR_ADDR_sser_rw_intr_mask 28
-
-/* Register rw_ack_intr, scope sser, type rw */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_rw_ack_intr;
-#define REG_RD_ADDR_sser_rw_ack_intr 32
-#define REG_WR_ADDR_sser_rw_ack_intr 32
-
-/* Register r_intr, scope sser, type r */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_r_intr;
-#define REG_RD_ADDR_sser_r_intr 36
-
-/* Register r_masked_intr, scope sser, type r */
-typedef struct {
- unsigned int trdy : 1;
- unsigned int rdav : 1;
- unsigned int tidle : 1;
- unsigned int rstop : 1;
- unsigned int urun : 1;
- unsigned int orun : 1;
- unsigned int md_rec : 1;
- unsigned int md_sent : 1;
- unsigned int r958err : 1;
- unsigned int dummy1 : 23;
-} reg_sser_r_masked_intr;
-#define REG_RD_ADDR_sser_r_masked_intr 40
-
-
-/* Constants */
-enum {
- regk_sser_both = 0x00000002,
- regk_sser_bulk = 0x00000001,
- regk_sser_clk100 = 0x00000000,
- regk_sser_clk_in = 0x00000000,
- regk_sser_const0 = 0x00000003,
- regk_sser_dout = 0x00000002,
- regk_sser_edge = 0x00000000,
- regk_sser_ext = 0x00000001,
- regk_sser_ext_clk = 0x00000001,
- regk_sser_f100 = 0x00000000,
- regk_sser_f29_493 = 0x00000004,
- regk_sser_f32 = 0x00000005,
- regk_sser_f32_768 = 0x00000006,
- regk_sser_frm = 0x00000003,
- regk_sser_gio0 = 0x00000000,
- regk_sser_gio1 = 0x00000001,
- regk_sser_hispeed = 0x00000001,
- regk_sser_hold = 0x00000002,
- regk_sser_in = 0x00000000,
- regk_sser_inf = 0x00000003,
- regk_sser_intern = 0x00000000,
- regk_sser_intern_clk = 0x00000001,
- regk_sser_intern_tb = 0x00000000,
- regk_sser_iso = 0x00000000,
- regk_sser_level = 0x00000001,
- regk_sser_lospeed = 0x00000000,
- regk_sser_lsbfirst = 0x00000000,
- regk_sser_msbfirst = 0x00000001,
- regk_sser_neg = 0x00000001,
- regk_sser_neg_lo = 0x00000000,
- regk_sser_no = 0x00000000,
- regk_sser_no_clk = 0x00000007,
- regk_sser_nojitter = 0x00000002,
- regk_sser_out = 0x00000001,
- regk_sser_pos = 0x00000000,
- regk_sser_pos_hi = 0x00000001,
- regk_sser_rec = 0x00000000,
- regk_sser_rw_cfg_default = 0x00000000,
- regk_sser_rw_extra_default = 0x00000000,
- regk_sser_rw_frm_cfg_default = 0x00000000,
- regk_sser_rw_intr_mask_default = 0x00000000,
- regk_sser_rw_rec_cfg_default = 0x00000000,
- regk_sser_rw_tr_cfg_default = 0x01800000,
- regk_sser_rw_tr_data_default = 0x00000000,
- regk_sser_thr16 = 0x00000001,
- regk_sser_thr32 = 0x00000002,
- regk_sser_thr8 = 0x00000000,
- regk_sser_tr = 0x00000001,
- regk_sser_ts_out = 0x00000003,
- regk_sser_tx_bulk = 0x00000002,
- regk_sser_wiresave = 0x00000002,
- regk_sser_yes = 0x00000001
-};
-#endif /* __sser_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop.h b/arch/cris/include/arch-v32/arch/hwregs/strcop.h
deleted file mode 100644
index 2c522b024ee7..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/strcop.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-// $Id: strcop.h,v 1.3 2003/10/22 13:27:12 henriken Exp $
-
-// Streamcop meta-data configuration structs
-
-struct strcop_meta_out {
- unsigned char csumsel : 3;
- unsigned char ciphsel : 3;
- unsigned char ciphconf : 2;
- unsigned char hashsel : 3;
- unsigned char hashconf : 1;
- unsigned char hashmode : 1;
- unsigned char decrypt : 1;
- unsigned char dlkey : 1;
- unsigned char cbcmode : 1;
-};
-
-struct strcop_meta_in {
- unsigned char dmasel : 3;
- unsigned char sync : 1;
- unsigned char res1 : 5;
- unsigned char res2;
-};
-
-// Source definitions
-
-enum {
- src_none = 0,
- src_dma = 1,
- src_des = 2,
- src_sha1 = 3,
- src_csum = 4,
- src_aes = 5,
- src_md5 = 6,
- src_res = 7
-};
-
-// Cipher definitions
-
-enum {
- ciph_des = 0,
- ciph_3des = 1,
- ciph_aes = 2
-};
-
-// Hash definitions
-
-enum {
- hash_sha1 = 0,
- hash_md5 = 1
-};
-
-enum {
- hash_noiv = 0,
- hash_iv = 1
-};
-
-
diff --git a/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h b/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h
deleted file mode 100644
index 069b2ed9def5..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/strcop_defs.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strcop_defs_h
-#define __strcop_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strcop/rtl/strcop_regs.r
- * id: strcop_regs.r,v 1.5 2003/10/15 12:09:45 kriskn Exp
- * last modfied: Mon Apr 11 16:09:38 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strcop_defs.h ../../inst/strcop/rtl/strcop_regs.r
- * id: $Id: strcop_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strcop */
-
-/* Register rw_cfg, scope strcop, type rw */
-typedef struct {
- unsigned int td3 : 1;
- unsigned int td2 : 1;
- unsigned int td1 : 1;
- unsigned int ipend : 1;
- unsigned int ignore_sync : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 26;
-} reg_strcop_rw_cfg;
-#define REG_RD_ADDR_strcop_rw_cfg 0
-#define REG_WR_ADDR_strcop_rw_cfg 0
-
-
-/* Constants */
-enum {
- regk_strcop_big = 0x00000001,
- regk_strcop_d = 0x00000001,
- regk_strcop_e = 0x00000000,
- regk_strcop_little = 0x00000000,
- regk_strcop_rw_cfg_default = 0x00000002
-};
-#endif /* __strcop_defs_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h b/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h
deleted file mode 100644
index c3fa0c06c558..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/supp_reg.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SUPP_REG_H__
-#define __SUPP_REG_H__
-
-/* Macros for reading and writing support/special registers. */
-
-#ifndef STRINGIFYFY
-#define STRINGIFYFY(i) #i
-#endif
-
-#ifndef STRINGIFY
-#define STRINGIFY(i) STRINGIFYFY(i)
-#endif
-
-#define SPEC_REG_BZ "BZ"
-#define SPEC_REG_VR "VR"
-#define SPEC_REG_PID "PID"
-#define SPEC_REG_SRS "SRS"
-#define SPEC_REG_WZ "WZ"
-#define SPEC_REG_EXS "EXS"
-#define SPEC_REG_EDA "EDA"
-#define SPEC_REG_MOF "MOF"
-#define SPEC_REG_DZ "DZ"
-#define SPEC_REG_EBP "EBP"
-#define SPEC_REG_ERP "ERP"
-#define SPEC_REG_SRP "SRP"
-#define SPEC_REG_NRP "NRP"
-#define SPEC_REG_CCS "CCS"
-#define SPEC_REG_USP "USP"
-#define SPEC_REG_SPC "SPC"
-
-#define RW_MM_CFG 0
-#define RW_MM_KBASE_LO 1
-#define RW_MM_KBASE_HI 2
-#define RW_MM_CAUSE 3
-#define RW_MM_TLB_SEL 4
-#define RW_MM_TLB_LO 5
-#define RW_MM_TLB_HI 6
-#define RW_MM_TLB_PGD 7
-
-#define BANK_GC 0
-#define BANK_IM 1
-#define BANK_DM 2
-#define BANK_BP 3
-
-#define RW_GC_CFG 0
-#define RW_GC_CCS 1
-#define RW_GC_SRS 2
-#define RW_GC_NRP 3
-#define RW_GC_EXS 4
-#define RW_GC_R0 8
-#define RW_GC_R1 9
-
-#define SPEC_REG_WR(r,v) \
-__asm__ __volatile__ ("move %0, $" r : : "r" (v));
-
-#define SPEC_REG_RD(r,v) \
-__asm__ __volatile__ ("move $" r ",%0" : "=r" (v));
-
-#define NOP() \
- __asm__ __volatile__ ("nop");
-
-#define SUPP_BANK_SEL(b) \
- SPEC_REG_WR(SPEC_REG_SRS,b); \
- NOP(); \
- NOP(); \
- NOP();
-
-#define SUPP_REG_WR(r,v) \
-__asm__ __volatile__ ("move %0, $S" STRINGIFYFY(r) "\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- "nop\n\t" \
- : : "r" (v));
-
-#define SUPP_REG_RD(r,v) \
-__asm__ __volatile__ ("move $S" STRINGIFYFY(r) ",%0" : "=r" (v));
-
-#endif /* __SUPP_REG_H__ */
diff --git a/arch/cris/include/arch-v32/arch/intmem.h b/arch/cris/include/arch-v32/arch/intmem.h
deleted file mode 100644
index 2bcb21c9b25f..000000000000
--- a/arch/cris/include/arch-v32/arch/intmem.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_INTMEM_H
-#define _ASM_CRIS_INTMEM_H
-
-void* crisv32_intmem_alloc(unsigned size, unsigned align);
-void crisv32_intmem_free(void* addr);
-void* crisv32_intmem_phys_to_virt(unsigned long addr);
-unsigned long crisv32_intmem_virt_to_phys(void *addr);
-
-#endif /* _ASM_CRIS_ARCH_INTMEM_H */
diff --git a/arch/cris/include/arch-v32/arch/irq.h b/arch/cris/include/arch-v32/arch/irq.h
deleted file mode 100644
index 5259084001d4..000000000000
--- a/arch/cris/include/arch-v32/arch/irq.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_IRQ_H
-#define _ASM_ARCH_IRQ_H
-
-#include <hwregs/intr_vect.h>
-
-/* Number of non-cpu interrupts. */
-#define NR_IRQS (NBR_INTR_VECT + 256) /* Exceptions + IRQs */
-#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
-#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */
-#if NR_REAL_IRQS > 32
-#define MACH_IRQS 64
-#else
-#define MACH_IRQS 32
-#endif
-
-#ifndef __ASSEMBLY__
-/* Global IRQ vector. */
-typedef void (*irqvectptr)(void);
-
-struct etrax_interrupt_vector {
- irqvectptr v[256];
-};
-
-extern struct etrax_interrupt_vector *etrax_irv; /* head.S */
-
-void crisv32_mask_irq(int irq);
-void crisv32_unmask_irq(int irq);
-
-void set_exception_vector(int n, irqvectptr addr);
-
-/* Save registers so that they match pt_regs. */
-#define SAVE_ALL \
- "subq 12,$sp\n\t" \
- "move $erp,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $srp,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $ccs,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $spc,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $mof,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move $srs,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move.d $acr,[$sp]\n\t" \
- "subq 14*4,$sp\n\t" \
- "movem $r13,[$sp]\n\t" \
- "subq 4,$sp\n\t" \
- "move.d $r10,[$sp]\n"
-
-#define STR2(x) #x
-#define STR(x) STR2(x)
-
-#define IRQ_NAME2(nr) nr##_interrupt(void)
-#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
-
-/*
- * The reason for setting the S-bit when debugging the kernel is that we want
- * hardware breakpoints to remain active while we are in an exception handler.
- * Note that we cannot simply copy S1, since we may come here from user-space,
- * or any context where the S-bit wasn't set.
- */
-#ifdef CONFIG_ETRAX_KGDB
-#define KGDB_FIXUP \
- "move $ccs, $r10\n\t" \
- "or.d (1<<9), $r10\n\t" \
- "move $r10, $ccs\n\t"
-#else
-#define KGDB_FIXUP ""
-#endif
-
-/*
- * Make sure the causing IRQ is blocked, then call do_IRQ. After that, unblock
- * and jump to ret_from_intr which is found in entry.S.
- *
- * The reason for blocking the IRQ is to allow an sti() before the handler,
- * which will acknowledge the interrupt, is run. The actual blocking is made
- * by crisv32_do_IRQ.
- */
-#define BUILD_IRQ(nr) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- KGDB_FIXUP \
- "move.d "#nr",$r10\n\t" \
- "move.d $sp, $r12\n\t" \
- "jsr crisv32_do_IRQ\n\t" \
- "moveq 1, $r11\n\t" \
- "jump ret_from_intr\n\t" \
- "nop\n\t");
-/*
- * This is subtle. The timer interrupt is crucial and it should not be disabled
- * for too long. However, if it had been a normal interrupt as per BUILD_IRQ, it
- * would have been BLOCK'ed, and then softirq's are run before we return here to
- * UNBLOCK. If the softirq's take too much time to run, the timer irq won't run
- * and the watchdog will kill us.
- *
- * Furthermore, if a lot of other irq's occur before we return here, the
- * multiple_irq handler is run and it prioritizes the timer interrupt. However
- * if we had BLOCK'edit here, we would not get the multiple_irq at all.
- *
- * The non-blocking here is based on the knowledge that the timer interrupt runs
- * with interrupts disabled, and therefore there will not be an sti() before the
- * timer irq handler is run to acknowledge the interrupt.
- */
-#define BUILD_TIMER_IRQ(nr, mask) \
-void IRQ_NAME(nr); \
-__asm__ ( \
- ".text\n\t" \
- "IRQ" #nr "_interrupt:\n\t" \
- SAVE_ALL \
- KGDB_FIXUP \
- "move.d "#nr",$r10\n\t" \
- "move.d $sp,$r12\n\t" \
- "jsr crisv32_do_IRQ\n\t" \
- "moveq 0,$r11\n\t" \
- "jump ret_from_intr\n\t" \
- "nop\n\t");
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_ARCH_IRQ_H */
diff --git a/arch/cris/include/arch-v32/arch/irqflags.h b/arch/cris/include/arch-v32/arch/irqflags.h
deleted file mode 100644
index d55bf82de77c..000000000000
--- a/arch/cris/include/arch-v32/arch/irqflags.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H
-#define __ASM_CRIS_ARCH_IRQFLAGS_H
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
- asm volatile("move $ccs,%0" : "=rm" (flags) : : "memory");
- return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
- asm volatile("di" : : : "memory");
-}
-
-static inline void arch_local_irq_enable(void)
-{
- asm volatile("ei" : : : "memory");
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags = arch_local_save_flags();
- arch_local_irq_disable();
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile("move %0,$ccs" : : "rm" (flags) : "memory");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return !(flags & (1 << I_CCS_BITNR));
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */
diff --git a/arch/cris/include/arch-v32/arch/memmap.h b/arch/cris/include/arch-v32/arch/memmap.h
deleted file mode 100644
index 81985c0a6789..000000000000
--- a/arch/cris/include/arch-v32/arch/memmap.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <mach/memmap.h>
diff --git a/arch/cris/include/arch-v32/arch/mmu.h b/arch/cris/include/arch-v32/arch/mmu.h
deleted file mode 100644
index a8eec1312de0..000000000000
--- a/arch/cris/include/arch-v32/arch/mmu.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_MMU_H
-#define _ASM_CRIS_ARCH_MMU_H
-
-/* MMU context type. */
-typedef struct
-{
- unsigned int page_id;
-} mm_context_t;
-
-/* Kernel memory segments. */
-#define KSEG_F 0xf0000000UL
-#define KSEG_E 0xe0000000UL
-#define KSEG_D 0xd0000000UL
-#define KSEG_C 0xc0000000UL
-#define KSEG_B 0xb0000000UL
-#define KSEG_A 0xa0000000UL
-#define KSEG_9 0x90000000UL
-#define KSEG_8 0x80000000UL
-#define KSEG_7 0x70000000UL
-#define KSEG_6 0x60000000UL
-#define KSEG_5 0x50000000UL
-#define KSEG_4 0x40000000UL
-#define KSEG_3 0x30000000UL
-#define KSEG_2 0x20000000UL
-#define KSEG_1 0x10000000UL
-#define KSEG_0 0x00000000UL
-
-/*
- * CRISv32 PTE bits:
- *
- * Bit: 31 30-13 12-5 4 3 2 1 0
- * +-------+-----+------+--------+-------+--------+-------+---------+
- * | cache | pfn | zero | global | valid | kernel | write | execute |
- * +-------+-----+------+--------+-------+--------+-------+---------+
- */
-
-/*
- * Defines for accessing the bits. Also define some synonyms for use with
- * the software-based defined bits below.
- */
-#define _PAGE_EXECUTE (1 << 0) /* Execution bit. */
-#define _PAGE_WE (1 << 1) /* Write bit. */
-#define _PAGE_SILENT_WRITE (1 << 1) /* Same as above. */
-#define _PAGE_KERNEL (1 << 2) /* Kernel mode page. */
-#define _PAGE_VALID (1 << 3) /* Page is valid. */
-#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */
-#define _PAGE_GLOBAL (1 << 4) /* Global page. */
-#define _PAGE_NO_CACHE (1 << 31) /* part of the uncached memory map */
-
-
-/*
- * The hardware doesn't care about these bits, but the kernel uses them in
- * software.
- */
-#define _PAGE_PRESENT (1 << 5) /* Page is present in memory. */
-#define _PAGE_ACCESSED (1 << 6) /* Simulated in software using valid bit. */
-#define _PAGE_MODIFIED (1 << 7) /* Simulated in software using we bit. */
-#define _PAGE_READ (1 << 8) /* Read enabled. */
-#define _PAGE_WRITE (1 << 9) /* Write enabled. */
-
-/* Define some higher level generic page attributes. */
-#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-
-#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED)
-
-#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
- _PAGE_ACCESSED)
-#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \
- _PAGE_ACCESSED | _PAGE_EXECUTE)
-
-#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE | _PAGE_ACCESSED)
-
-#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE)
-#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_EXECUTE)
-#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \
- _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define PAGE_KERNEL_EXEC __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | _PAGE_EXECUTE | \
- _PAGE_PRESENT | __READABLE | __WRITEABLE)
-#define PAGE_SIGNAL_TRAMPOLINE __pgprot(_PAGE_GLOBAL | _PAGE_EXECUTE | \
- _PAGE_PRESENT | __READABLE)
-
-#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL)
-
-/* CRISv32 can do page protection for execute.
- * Write permissions imply read permissions.
- * Note that the numbers are in Execute-Write-Read order!
- */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY_EXEC
-#define __P101 PAGE_READONLY_EXEC
-#define __P110 PAGE_COPY_EXEC
-#define __P111 PAGE_COPY_EXEC
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY_EXEC
-#define __S101 PAGE_READONLY_EXEC
-#define __S110 PAGE_SHARED_EXEC
-#define __S111 PAGE_SHARED_EXEC
-
-#endif /* _ASM_CRIS_ARCH_MMU_H */
diff --git a/arch/cris/include/arch-v32/arch/offset.h b/arch/cris/include/arch-v32/arch/offset.h
deleted file mode 100644
index 10a670443386..000000000000
--- a/arch/cris/include/arch-v32/arch/offset.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_OFFSETS_H__
-#define __ASM_OFFSETS_H__
-/*
- * DO NOT MODIFY.
- *
- * This file was generated by arch/cris/Makefile
- *
- */
-
-#define PT_orig_r10 0 /* offsetof(struct pt_regs, orig_r10) */
-#define PT_r13 56 /* offsetof(struct pt_regs, r13) */
-#define PT_r12 52 /* offsetof(struct pt_regs, r12) */
-#define PT_r11 48 /* offsetof(struct pt_regs, r11) */
-#define PT_r10 44 /* offsetof(struct pt_regs, r10) */
-#define PT_r9 40 /* offsetof(struct pt_regs, r9) */
-#define PT_acr 60 /* offsetof(struct pt_regs, acr) */
-#define PT_srs 64 /* offsetof(struct pt_regs, srs) */
-#define PT_mof 68 /* offsetof(struct pt_regs, mof) */
-#define PT_ccs 76 /* offsetof(struct pt_regs, ccs) */
-#define PT_srp 80 /* offsetof(struct pt_regs, srp) */
-
-#define TI_task 0 /* offsetof(struct thread_info, task) */
-#define TI_flags 8 /* offsetof(struct thread_info, flags) */
-#define TI_preempt_count 16 /* offsetof(struct thread_info, preempt_count) */
-
-#define THREAD_ksp 0 /* offsetof(struct thread_struct, ksp) */
-#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
-#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */
-
-#define TASK_pid 151 /* offsetof(struct task_struct, pid) */
-
-#define LCLONE_VM 256 /* CLONE_VM */
-#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/page.h b/arch/cris/include/arch-v32/arch/page.h
deleted file mode 100644
index 7ac04f615193..000000000000
--- a/arch/cris/include/arch-v32/arch/page.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PAGE_H
-#define _ASM_CRIS_ARCH_PAGE_H
-
-
-#ifdef __KERNEL__
-
-#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */
-
-/*
- * Macros to convert between physical and virtual addresses. By stripping a
- * selected bit it's possible to convert between KSEG_x and 0x40000000 where the
- * DRAM really resides. DRAM is virtually at 0xc.
- */
-#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
-#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
-
-#define VM_STACK_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
- VM_MAYREAD | VM_MAYWRITE)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_CRIS_ARCH_PAGE_H */
diff --git a/arch/cris/include/arch-v32/arch/pgtable.h b/arch/cris/include/arch-v32/arch/pgtable.h
deleted file mode 100644
index e787b19b700e..000000000000
--- a/arch/cris/include/arch-v32/arch/pgtable.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PGTABLE_H
-#define _ASM_CRIS_ARCH_PGTABLE_H
-
-/* Define the kernels virtual memory area. */
-
-/* See head.S for differences between ARTPEC-3 and ETRAX FS. */
-#ifdef CONFIG_CRIS_MACH_ARTPEC3
-#define VMALLOC_START KSEG_E
-#define VMALLOC_END KSEG_F
-#else
-#define VMALLOC_START KSEG_D
-#define VMALLOC_END KSEG_E
-#endif
-
-#define VMALLOC_VMADDR(x) ((unsigned long)(x))
-
-#endif /* _ASM_CRIS_ARCH_PGTABLE_H */
diff --git a/arch/cris/include/arch-v32/arch/processor.h b/arch/cris/include/arch-v32/arch/processor.h
deleted file mode 100644
index 554088ab5f01..000000000000
--- a/arch/cris/include/arch-v32/arch/processor.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PROCESSOR_H
-#define _ASM_CRIS_ARCH_PROCESSOR_H
-
-
-/* Return current instruction pointer. */
-#define current_text_addr() \
- ({void *pc; __asm__ __volatile__ ("lapcq .,%0" : "=rm" (pc)); pc;})
-
-/*
- * Since CRIS doesn't do hardware task-switching this hasn't really anything to
- * do with the proccessor itself, it's just here for legacy reasons. This is
- * used when task-switching using _resume defined in entry.S. The offsets here
- * are hardcoded into _resume, so if this struct is changed, entry.S needs to be
- * changed as well.
- */
-struct thread_struct {
- unsigned long ksp; /* Kernel stack pointer. */
- unsigned long usp; /* User stack pointer. */
- unsigned long ccs; /* Saved flags register. */
-};
-
-/*
- * User-space process size. This is hardcoded into a few places, so don't
- * change it unless everything's clear!
- */
-#define TASK_SIZE (0xB0000000UL)
-
-#define INIT_THREAD { }
-
-#define KSTK_EIP(tsk) \
-({ \
- unsigned long eip = 0; \
- unsigned long regs = (unsigned long)task_pt_regs(tsk); \
- if (regs > PAGE_SIZE && virt_addr_valid(regs)) \
- eip = ((struct pt_regs *)regs)->erp; \
- eip; \
-})
-
-/*
- * Give the thread a program location, set user-mode and switch user
- * stackpointer.
- */
-#define start_thread(regs, ip, usp) \
-do { \
- regs->erp = ip; \
- regs->ccs |= 1 << (U_CCS_BITNR + CCS_SHIFT); \
- wrusp(usp); \
-} while(0)
-
-/* Nothing special to do for v32 when handling a kernel bus fault fixup. */
-#define arch_fixup(regs) {};
-
-#endif /* _ASM_CRIS_ARCH_PROCESSOR_H */
diff --git a/arch/cris/include/arch-v32/arch/swab.h b/arch/cris/include/arch-v32/arch/swab.h
deleted file mode 100644
index 280dd7093e4f..000000000000
--- a/arch/cris/include/arch-v32/arch/swab.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_SWAB_H
-#define _ASM_CRIS_ARCH_SWAB_H
-
-#include <asm/types.h>
-
-#define __SWAB_64_THRU_32__
-
-static inline __const__ __u32
-__arch_swab32(__u32 x)
-{
- __asm__ __volatile__ ("swapwb %0" : "=r" (x) : "0" (x));
- return (x);
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __const__ __u16
-__arch_swab16(__u16 x)
-{
- __asm__ __volatile__ ("swapb %0" : "=r" (x) : "0" (x));
- return (x);
-}
-#define __arch_swab16 __arch_swab16
-
-#endif /* _ASM_CRIS_ARCH_SWAB_H */
diff --git a/arch/cris/include/arch-v32/arch/system.h b/arch/cris/include/arch-v32/arch/system.h
deleted file mode 100644
index 84f00e5d4652..000000000000
--- a/arch/cris/include/arch-v32/arch/system.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_SYSTEM_H
-#define _ASM_CRIS_ARCH_SYSTEM_H
-
-
-/* Read the CPU version register. */
-static inline unsigned long rdvr(void)
-{
- unsigned char vr;
-
- __asm__ __volatile__ ("move $vr, %0" : "=rm" (vr));
- return vr;
-}
-
-#define cris_machine_name "crisv32"
-
-/* Read the user-mode stack pointer. */
-static inline unsigned long rdusp(void)
-{
- unsigned long usp;
-
- __asm__ __volatile__ ("move $usp, %0" : "=rm" (usp));
- return usp;
-}
-
-/* Read the current stack pointer. */
-static inline unsigned long rdsp(void)
-{
- unsigned long sp;
-
- __asm__ __volatile__ ("move.d $sp, %0" : "=rm" (sp));
- return sp;
-}
-
-/* Write the user-mode stack pointer. */
-#define wrusp(usp) __asm__ __volatile__ ("move %0, $usp" : : "rm" (usp))
-
-#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
diff --git a/arch/cris/include/arch-v32/arch/thread_info.h b/arch/cris/include/arch-v32/arch/thread_info.h
deleted file mode 100644
index 8514669e5fab..000000000000
--- a/arch/cris/include/arch-v32/arch/thread_info.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_THREAD_INFO_H
-#define _ASM_CRIS_ARCH_THREAD_INFO_H
-
-/* Return a thread_info struct. */
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
-
- __asm__ __volatile__ ("and.d $sp, %0" : "=r" (ti) : "0" (~8191UL));
- return ti;
-}
-
-#endif /* _ASM_CRIS_ARCH_THREAD_INFO_H */
diff --git a/arch/cris/include/arch-v32/arch/timex.h b/arch/cris/include/arch-v32/arch/timex.h
deleted file mode 100644
index 2cd8e704a73b..000000000000
--- a/arch/cris/include/arch-v32/arch/timex.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_TIMEX_H
-#define _ASM_CRIS_ARCH_TIMEX_H
-
-#include <hwregs/reg_map.h>
-#include <hwregs/reg_rdwr.h>
-#include <hwregs/timer_defs.h>
-
-/*
- * The clock runs at 100MHz, we divide it by 1000000. If you change anything
- * here you must check time.c as well.
- */
-
-#define CLOCK_TICK_RATE 100000000 /* Underlying frequency of the HZ timer */
-
-/* The timer0 values gives 10 ns resolution but interrupts at HZ. */
-#define TIMER0_FREQ (CLOCK_TICK_RATE)
-#define TIMER0_DIV (TIMER0_FREQ/(HZ))
-
-/* Convert the value in step of 10 ns to 1us without overflow: */
-#define GET_JIFFIES_USEC() \
- ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100)
-
-extern unsigned long get_ns_in_jiffie(void);
-
-static inline unsigned long get_us_in_jiffie_highres(void)
-{
- return get_ns_in_jiffie() / 1000;
-}
-
-#endif
-
diff --git a/arch/cris/include/arch-v32/arch/tlb.h b/arch/cris/include/arch-v32/arch/tlb.h
deleted file mode 100644
index 50452802738f..000000000000
--- a/arch/cris/include/arch-v32/arch/tlb.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_ARCH_TLB_H
-#define _CRIS_ARCH_TLB_H
-
-/*
- * The TLB is a 64-entry cache. Each entry has a 8-bit page_id that is used
- * to store the "process" it belongs to (=> fast mm context switch). The
- * last page_id is never used so we can make TLB entries that never matches.
- */
-#define NUM_TLB_ENTRIES 64
-#define NUM_PAGEID 256
-#define INVALID_PAGEID 255
-#define NO_CONTEXT -1
-
-#endif /* _CRIS_ARCH_TLB_H */
diff --git a/arch/cris/include/arch-v32/arch/uaccess.h b/arch/cris/include/arch-v32/arch/uaccess.h
deleted file mode 100644
index 214bd26efcd9..000000000000
--- a/arch/cris/include/arch-v32/arch/uaccess.h
+++ /dev/null
@@ -1,730 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Authors: Hans-Peter Nilsson (hp@axis.com)
- *
- */
-#ifndef _CRIS_ARCH_UACCESS_H
-#define _CRIS_ARCH_UACCESS_H
-
-/*
- * We don't tell gcc that we are accessing memory, but this is OK
- * because we do not write to any memory gcc knows about, so there
- * are no aliasing issues.
- *
- * Note that PC at a fault is the address *at* the faulting
- * instruction for CRISv32.
- */
-#define __put_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- "2: "op" %1,[%2]\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 4b\n" \
- " nop\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err) \
- : "r" (x), "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __put_user_asm_64(x, addr, err) do { \
- int dummy_for_put_user_asm_64_; \
- __asm__ __volatile__( \
- "2: move.d %M2,[%1+]\n" \
- "4: move.d %H2,[%1]\n" \
- "5:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %4,%0\n" \
- " jump 5b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=b" (dummy_for_put_user_asm_64_) \
- : "r" (x), "1" (addr), "g" (-EFAULT), \
- "0" (err)); \
- } while (0)
-
-/* See comment before __put_user_asm. */
-
-#define __get_user_asm(x, addr, err, op) \
- __asm__ __volatile__( \
- "2: "op" [%2],%1\n" \
- "4:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %3,%0\n" \
- " jump 4b\n" \
- " moveq 0,%1\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x) \
- : "r" (addr), "g" (-EFAULT), "0" (err))
-
-#define __get_user_asm_64(x, addr, err) do { \
- int dummy_for_get_user_asm_64_; \
- __asm__ __volatile__( \
- "2: move.d [%2+],%M1\n" \
- "4: move.d [%2],%H1\n" \
- "5:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: move.d %4,%0\n" \
- " jump 5b\n" \
- " moveq 0,%1\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .dword 2b,3b\n" \
- " .dword 4b,3b\n" \
- " .previous\n" \
- : "=r" (err), "=r" (x), \
- "=b" (dummy_for_get_user_asm_64_) \
- : "2" (addr), "g" (-EFAULT), "0" (err));\
- } while (0)
-
-/*
- * Copy a null terminated string from userspace.
- *
- * Must return:
- * -EFAULT for an exception
- * count if we hit the buffer limit
- * bytes copied if we hit a null byte
- * (without the null byte)
- */
-static inline long
-__do_strncpy_from_user(char *dst, const char *src, long count)
-{
- long res;
-
- if (count == 0)
- return 0;
-
- /*
- * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
- * So do we.
- *
- * This code is deduced from:
- *
- * char tmp2;
- * long tmp1, tmp3;
- * tmp1 = count;
- * while ((*dst++ = (tmp2 = *src++)) != 0
- * && --tmp1)
- * ;
- *
- * res = count - tmp1;
- *
- * with tweaks.
- */
-
- __asm__ __volatile__ (
- " move.d %3,%0\n"
- "5: move.b [%2+],$acr\n"
- "1: beq 6f\n"
- " move.b $acr,[%1+]\n"
-
- " subq 1,%0\n"
- "2: bne 1b\n"
- " move.b [%2+],$acr\n"
-
- "6: sub.d %3,%0\n"
- " neg.d %0,%0\n"
- "3:\n"
- " .section .fixup,\"ax\"\n"
- "4: move.d %7,%0\n"
- " jump 3b\n"
- " nop\n"
-
- /* The address for a fault at the first move is trivial.
- The address for a fault at the second move is that of
- the preceding branch insn, since the move insn is in
- its delay-slot. Just so you don't get confused... */
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 5b,4b\n"
- " .dword 2b,4b\n"
- " .previous"
- : "=r" (res), "=b" (dst), "=b" (src), "=r" (count)
- : "3" (count), "1" (dst), "2" (src), "g" (-EFAULT)
- : "acr");
-
- return res;
-}
-
-/* A few copy asms to build up the more complex ones from.
-
- Note again, a post-increment is performed regardless of whether a bus
- fault occurred in that instruction, and PC for a faulted insn is the
- address for the insn, or for the preceding branch when in a delay-slot. */
-
-#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- COPY \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous\n" \
- : "=b" (to), "=b" (from), "=r" (ret) \
- : "0" (to), "1" (from), "2" (ret) \
- : "acr", "memory")
-
-#define __asm_copy_from_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- "2: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "3: addq 1,%2\n" \
- " jump 1b\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- "2: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "3: addq 2,%2\n" \
- " jump 1b\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_2(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_3(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, \
- "4: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- "2: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "3: addq 4,%2\n" \
- " jump 1b\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_from_user_4(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_5(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- "4: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- COPY \
- "4: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "5: addq 2,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_6(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_7(to, from, ret) \
- __asm_copy_from_user_6x_cont(to, from, ret, \
- "6: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_4x_cont(to, from, ret, \
- COPY \
- "4: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "5: addq 4,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_from_user_8(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_9(to, from, ret) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- "6: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- COPY \
- "6: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "7: addq 2,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_10(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_11(to, from, ret) \
- __asm_copy_from_user_10x_cont(to, from, ret, \
- "8: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_8x_cont(to, from, ret, \
- COPY \
- "6: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "7: addq 4,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_from_user_12(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_13(to, from, ret) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- "8: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- COPY \
- "8: move.w [%1+],$acr\n" \
- " move.w $acr,[%0+]\n", \
- FIXUP \
- "9: addq 2,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_14(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_15(to, from, ret) \
- __asm_copy_from_user_14x_cont(to, from, ret, \
- "10: move.b [%1+],$acr\n" \
- " move.b $acr,[%0+]\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_from_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_12x_cont(to, from, ret, \
- COPY \
- "8: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "9: addq 4,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_from_user_16(to, from, ret) \
- __asm_copy_from_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_16x_cont(to, from, ret, \
- COPY \
- "10: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "11: addq 4,%2\n", \
- TENTRY \
- " .dword 10b,11b\n")
-
-#define __asm_copy_from_user_20(to, from, ret) \
- __asm_copy_from_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_from_user_20x_cont(to, from, ret, \
- COPY \
- "12: move.d [%1+],$acr\n" \
- " move.d $acr,[%0+]\n", \
- FIXUP \
- "13: addq 4,%2\n", \
- TENTRY \
- " .dword 12b,13b\n")
-
-#define __asm_copy_from_user_24(to, from, ret) \
- __asm_copy_from_user_24x_cont(to, from, ret, "", "", "")
-
-/* And now, the to-user ones. */
-
-#define __asm_copy_to_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "2: move.b $acr,[%0+]\n", \
- "3: jump 1b\n" \
- " addq 1,%2\n", \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "2: move.w $acr,[%0+]\n", \
- FIXUP \
- "3: jump 1b\n" \
- " addq 2,%2\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_2(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_3(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "4: move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "2: move.d $acr,[%0+]\n", \
- FIXUP \
- "3: jump 1b\n" \
- " addq 4,%2\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_copy_to_user_4(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_5(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "4: move.b $acr,[%0+]\n", \
- "5: addq 1,%2\n", \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "4: move.w $acr,[%0+]\n", \
- FIXUP \
- "5: addq 2,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_6(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_7(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "6: move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "4: move.d $acr,[%0+]\n", \
- FIXUP \
- "5: addq 4,%2\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_copy_to_user_8(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_9(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "6: move.b $acr,[%0+]\n", \
- "7: addq 1,%2\n", \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "6: move.w $acr,[%0+]\n", \
- FIXUP \
- "7: addq 2,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_10(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_11(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "8: move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "6: move.d $acr,[%0+]\n", \
- FIXUP \
- "7: addq 4,%2\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_copy_to_user_12(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_13(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "8: move.b $acr,[%0+]\n", \
- "9: addq 1,%2\n", \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- COPY \
- " move.w [%1+],$acr\n" \
- "8: move.w $acr,[%0+]\n", \
- FIXUP \
- "9: addq 2,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_14(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_15(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, \
- " move.b [%1+],$acr\n" \
- "10: move.b $acr,[%0+]\n", \
- "11: addq 1,%2\n", \
- " .dword 10b,11b\n")
-
-#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "8: move.d $acr,[%0+]\n", \
- FIXUP \
- "9: addq 4,%2\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_copy_to_user_16(to, from, ret) \
- __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_20x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_16x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "10: move.d $acr,[%0+]\n", \
- FIXUP \
- "11: addq 4,%2\n", \
- TENTRY \
- " .dword 10b,11b\n")
-
-#define __asm_copy_to_user_20(to, from, ret) \
- __asm_copy_to_user_20x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_24x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_20x_cont(to, from, ret, \
- COPY \
- " move.d [%1+],$acr\n" \
- "12: move.d $acr,[%0+]\n", \
- FIXUP \
- "13: addq 4,%2\n", \
- TENTRY \
- " .dword 12b,13b\n")
-
-#define __asm_copy_to_user_24(to, from, ret) \
- __asm_copy_to_user_24x_cont(to, from, ret, "", "", "")
-
-/* Define a few clearing asms with exception handlers. */
-
-/* This frame-asm is like the __asm_copy_user_cont one, but has one less
- input. */
-
-#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm__ __volatile__ ( \
- CLEAR \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous" \
- : "=b" (to), "=r" (ret) \
- : "0" (to), "1" (ret) \
- : "memory")
-
-#define __asm_clear_1(to, ret) \
- __asm_clear(to, ret, \
- "2: clear.b [%0+]\n", \
- "3: jump 1b\n" \
- " addq 1,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_2(to, ret) \
- __asm_clear(to, ret, \
- "2: clear.w [%0+]\n", \
- "3: jump 1b\n" \
- " addq 2,%1\n", \
- " .dword 2b,3b\n")
-
-#define __asm_clear_3(to, ret) \
- __asm_clear(to, ret, \
- "2: clear.w [%0+]\n" \
- "3: clear.b [%0+]\n", \
- "4: addq 2,%1\n" \
- "5: jump 1b\n" \
- " addq 1,%1\n", \
- " .dword 2b,4b\n" \
- " .dword 3b,5b\n")
-
-#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear(to, ret, \
- CLEAR \
- "2: clear.d [%0+]\n", \
- FIXUP \
- "3: jump 1b\n" \
- " addq 4,%1\n", \
- TENTRY \
- " .dword 2b,3b\n")
-
-#define __asm_clear_4(to, ret) \
- __asm_clear_4x_cont(to, ret, "", "", "")
-
-#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_4x_cont(to, ret, \
- CLEAR \
- "4: clear.d [%0+]\n", \
- FIXUP \
- "5: addq 4,%1\n", \
- TENTRY \
- " .dword 4b,5b\n")
-
-#define __asm_clear_8(to, ret) \
- __asm_clear_8x_cont(to, ret, "", "", "")
-
-#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_8x_cont(to, ret, \
- CLEAR \
- "6: clear.d [%0+]\n", \
- FIXUP \
- "7: addq 4,%1\n", \
- TENTRY \
- " .dword 6b,7b\n")
-
-#define __asm_clear_12(to, ret) \
- __asm_clear_12x_cont(to, ret, "", "", "")
-
-#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_12x_cont(to, ret, \
- CLEAR \
- "8: clear.d [%0+]\n", \
- FIXUP \
- "9: addq 4,%1\n", \
- TENTRY \
- " .dword 8b,9b\n")
-
-#define __asm_clear_16(to, ret) \
- __asm_clear_16x_cont(to, ret, "", "", "")
-
-#define __asm_clear_20x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_16x_cont(to, ret, \
- CLEAR \
- "10: clear.d [%0+]\n", \
- FIXUP \
- "11: addq 4,%1\n", \
- TENTRY \
- " .dword 10b,11b\n")
-
-#define __asm_clear_20(to, ret) \
- __asm_clear_20x_cont(to, ret, "", "", "")
-
-#define __asm_clear_24x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_20x_cont(to, ret, \
- CLEAR \
- "12: clear.d [%0+]\n", \
- FIXUP \
- "13: addq 4,%1\n", \
- TENTRY \
- " .dword 12b,13b\n")
-
-#define __asm_clear_24(to, ret) \
- __asm_clear_24x_cont(to, ret, "", "", "")
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return length of string in userspace including terminating 0
- * or 0 for error. Return a value greater than N if too long.
- */
-
-static inline long
-strnlen_user(const char *s, long n)
-{
- long res, tmp1;
-
- if (!access_ok(VERIFY_READ, s, 0))
- return 0;
-
- /*
- * This code is deduced from:
- *
- * tmp1 = n;
- * while (tmp1-- > 0 && *s++)
- * ;
- *
- * res = n - tmp1;
- *
- * (with tweaks).
- */
-
- __asm__ __volatile__ (
- " move.d %1,$acr\n"
- " cmpq 0,$acr\n"
- "0:\n"
- " ble 1f\n"
- " subq 1,$acr\n"
-
- "4: test.b [%0+]\n"
- " bne 0b\n"
- " cmpq 0,$acr\n"
- "1:\n"
- " move.d %1,%0\n"
- " sub.d $acr,%0\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
-
- "3: jump 2b\n"
- " clear.d %0\n"
-
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .dword 4b,3b\n"
- " .previous\n"
- : "=r" (res), "=r" (tmp1)
- : "0" (s), "1" (n)
- : "acr");
-
- return res;
-}
-
-#endif
diff --git a/arch/cris/include/arch-v32/arch/unistd.h b/arch/cris/include/arch-v32/arch/unistd.h
deleted file mode 100644
index 764435b3b28e..000000000000
--- a/arch/cris/include/arch-v32/arch/unistd.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_UNISTD_H_
-#define _ASM_CRIS_ARCH_UNISTD_H_
-
-/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */
-/*
- * Don't remove the .ifnc tests; they are an insurance against
- * any hard-to-spot gcc register allocation bugs.
- */
-#define _syscall0(type,name) \
-type name(void) \
-{ \
- register long __a __asm__ ("r10"); \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall1(type,name,type1,arg1) \
-type name(type1 arg1) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1,$r10$r9\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall2(type,name,type1,arg1,type2,arg2) \
-type name(type1 arg1,type2 arg2) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3,$r10$r9$r11\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
-type name(type1 arg1,type2 arg2,type3 arg3) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4,$r10$r9$r11$r12\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
-type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5,$r10$r9$r11$r12$r13\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d)\
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __e __asm__ ("mof") = (long) arg5; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5%6,$r10$r9$r11$r12$r13$mof\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "h" (__e) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \
- type5,arg5,type6,arg6) \
-type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,type6 arg6) \
-{ \
- register long __a __asm__ ("r10") = (long) arg1; \
- register long __b __asm__ ("r11") = (long) arg2; \
- register long __c __asm__ ("r12") = (long) arg3; \
- register long __d __asm__ ("r13") = (long) arg4; \
- register long __e __asm__ ("mof") = (long) arg5; \
- register long __f __asm__ ("srp") = (long) arg6; \
- register long __n_ __asm__ ("r9") = (__NR_##name); \
- __asm__ __volatile__ (".ifnc %0%1%3%4%5%6%7,$r10$r9$r11$r12$r13$mof$srp\n\t" \
- ".err\n\t" \
- ".endif\n\t" \
- "break 13" \
- : "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "h" (__e), "x" (__f) \
- : "memory"); \
- if (__a >= 0) \
- return (type) __a; \
- errno = -__a; \
- return (type) -1; \
-}
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h b/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h
deleted file mode 100644
index 7fafc370def2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/arbiter.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_ARBITER_H
-#define _ASM_CRIS_ARCH_ARBITER_H
-
-#define EXT_REGION 0
-#define INT_REGION 1
-
-typedef void (watch_callback)(void);
-
-enum {
- arbiter_all_dmas = 0x7fe,
- arbiter_cpu = 0x1800,
- arbiter_all_clients = 0x7fff
-};
-
-enum {
- arbiter_bar_all_clients = 0x1ff
-};
-
-enum {
- arbiter_all_read = 0x55,
- arbiter_all_write = 0xaa,
- arbiter_all_accesses = 0xff
-};
-
-#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth);
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback * cb);
-int crisv32_arbiter_unwatch(int id);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/dma.h b/arch/cris/include/arch-v32/mach-a3/mach/dma.h
deleted file mode 100644
index 92a74eab4395..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/dma.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
-
-#define NETWORK_ETH_TX_DMA_NBR 0 /* Ethernet 0 out. */
-#define NETWORK_ETH_RX_DMA_NBR 1 /* Ethernet 0 in. */
-
-#define IO_PROC_DMA_TX_DMA_NBR 4 /* IO processor DMA0 out. */
-#define IO_PROC_DMA_RX_DMA_NBR 5 /* IO processor DMA0 in. */
-
-#define ASYNC_SER3_TX_DMA_NBR 2 /* Asynchronous serial port 3 out. */
-#define ASYNC_SER3_RX_DMA_NBR 3 /* Asynchronous serial port 3 in. */
-
-#define ASYNC_SER2_TX_DMA_NBR 6 /* Asynchronous serial port 2 out. */
-#define ASYNC_SER2_RX_DMA_NBR 7 /* Asynchronous serial port 2 in. */
-
-#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
-#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
-
-#define SYNC_SER_TX_DMA_NBR 6 /* Synchronous serial port 0 out. */
-#define SYNC_SER_RX_DMA_NBR 7 /* Synchronous serial port 0 in. */
-
-#define ASYNC_SER0_TX_DMA_NBR 0 /* Asynchronous serial port 0 out. */
-#define ASYNC_SER0_RX_DMA_NBR 1 /* Asynchronous serial port 0 in. */
-
-#define STRCOP_TX_DMA_NBR 2 /* Stream co-processor out. */
-#define STRCOP_RX_DMA_NBR 3 /* Stream co-processor in. */
-
-#define dma_eth0 dma_eth
-#define dma_eth1 dma_eth
-
-enum dma_owner {
- dma_eth,
- dma_ser0,
- dma_ser1,
- dma_ser2,
- dma_ser3,
- dma_ser4,
- dma_iop,
- dma_sser,
- dma_strp,
- dma_h264,
- dma_jpeg
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned bandwidth, enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h
deleted file mode 100644
index 3d7f12ec1c54..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/clkgen_defs_asm.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __clkgen_defs_asm_h
-#define __clkgen_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: clkgen.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope clkgen, type r */
-#define reg_clkgen_r_bootsel___boot_mode___lsb 0
-#define reg_clkgen_r_bootsel___boot_mode___width 5
-#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
-#define reg_clkgen_r_bootsel___intern_main_clk___width 1
-#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
-#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
-#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
-#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
-#define reg_clkgen_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope clkgen, type rw */
-#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
-#define reg_clkgen_rw_clk_ctrl___pll___width 1
-#define reg_clkgen_rw_clk_ctrl___pll___bit 0
-#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
-#define reg_clkgen_rw_clk_ctrl___cpu___width 1
-#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
-#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
-#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
-#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
-#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
-#define reg_clkgen_rw_clk_ctrl___vin___width 1
-#define reg_clkgen_rw_clk_ctrl___vin___bit 3
-#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
-#define reg_clkgen_rw_clk_ctrl___sclr___width 1
-#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
-#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
-#define reg_clkgen_rw_clk_ctrl___h264___width 1
-#define reg_clkgen_rw_clk_ctrl___h264___bit 5
-#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
-#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
-#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
-#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
-#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
-#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
-#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
-#define reg_clkgen_rw_clk_ctrl___eth___width 1
-#define reg_clkgen_rw_clk_ctrl___eth___bit 8
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
-#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
-#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
-#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
-#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
-#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
-#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
-#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
-#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
-#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
-#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
-#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
-#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
-#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
-#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
-#define reg_clkgen_rw_clk_ctrl_offset 4
-
-
-/* Constants */
-#define regk_clkgen_eth1000_rx 0x0000000c
-#define regk_clkgen_eth1000_tx 0x0000000e
-#define regk_clkgen_eth100_rx 0x0000001d
-#define regk_clkgen_eth100_rx_half 0x0000001c
-#define regk_clkgen_eth100_tx 0x0000001f
-#define regk_clkgen_eth100_tx_half 0x0000001e
-#define regk_clkgen_nand_3_2 0x00000000
-#define regk_clkgen_nand_3_2_0x30 0x00000002
-#define regk_clkgen_nand_3_2_0x30_pll 0x00000012
-#define regk_clkgen_nand_3_2_pll 0x00000010
-#define regk_clkgen_nand_3_3 0x00000001
-#define regk_clkgen_nand_3_3_0x30 0x00000003
-#define regk_clkgen_nand_3_3_0x30_pll 0x00000013
-#define regk_clkgen_nand_3_3_pll 0x00000011
-#define regk_clkgen_nand_4_2 0x00000004
-#define regk_clkgen_nand_4_2_0x30 0x00000006
-#define regk_clkgen_nand_4_2_0x30_pll 0x00000016
-#define regk_clkgen_nand_4_2_pll 0x00000014
-#define regk_clkgen_nand_4_3 0x00000005
-#define regk_clkgen_nand_4_3_0x30 0x00000007
-#define regk_clkgen_nand_4_3_0x30_pll 0x00000017
-#define regk_clkgen_nand_4_3_pll 0x00000015
-#define regk_clkgen_nand_5_2 0x00000008
-#define regk_clkgen_nand_5_2_0x30 0x0000000a
-#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a
-#define regk_clkgen_nand_5_2_pll 0x00000018
-#define regk_clkgen_nand_5_3 0x00000009
-#define regk_clkgen_nand_5_3_0x30 0x0000000b
-#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b
-#define regk_clkgen_nand_5_3_pll 0x00000019
-#define regk_clkgen_no 0x00000000
-#define regk_clkgen_rw_clk_ctrl_default 0x00000002
-#define regk_clkgen_ser 0x0000000d
-#define regk_clkgen_ser_pll 0x0000000f
-#define regk_clkgen_yes 0x00000001
-#endif /* __clkgen_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h
deleted file mode 100644
index df79e5a7f02a..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ddr2_defs_asm.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ddr2_defs_asm_h
-#define __ddr2_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ddr2.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope ddr2, type rw */
-#define reg_ddr2_rw_cfg___col_width___lsb 0
-#define reg_ddr2_rw_cfg___col_width___width 4
-#define reg_ddr2_rw_cfg___nr_banks___lsb 4
-#define reg_ddr2_rw_cfg___nr_banks___width 1
-#define reg_ddr2_rw_cfg___nr_banks___bit 4
-#define reg_ddr2_rw_cfg___bw___lsb 5
-#define reg_ddr2_rw_cfg___bw___width 1
-#define reg_ddr2_rw_cfg___bw___bit 5
-#define reg_ddr2_rw_cfg___nr_ref___lsb 6
-#define reg_ddr2_rw_cfg___nr_ref___width 4
-#define reg_ddr2_rw_cfg___ref_interval___lsb 10
-#define reg_ddr2_rw_cfg___ref_interval___width 11
-#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
-#define reg_ddr2_rw_cfg___odt_ctrl___width 2
-#define reg_ddr2_rw_cfg___odt_mem___lsb 23
-#define reg_ddr2_rw_cfg___odt_mem___width 1
-#define reg_ddr2_rw_cfg___odt_mem___bit 23
-#define reg_ddr2_rw_cfg___imp_strength___lsb 24
-#define reg_ddr2_rw_cfg___imp_strength___width 1
-#define reg_ddr2_rw_cfg___imp_strength___bit 24
-#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
-#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
-#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
-#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
-#define reg_ddr2_rw_cfg___imp_cal_override___width 1
-#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
-#define reg_ddr2_rw_cfg___dll_override___lsb 27
-#define reg_ddr2_rw_cfg___dll_override___width 1
-#define reg_ddr2_rw_cfg___dll_override___bit 27
-#define reg_ddr2_rw_cfg_offset 0
-
-/* Register rw_timing, scope ddr2, type rw */
-#define reg_ddr2_rw_timing___wr___lsb 0
-#define reg_ddr2_rw_timing___wr___width 3
-#define reg_ddr2_rw_timing___rcd___lsb 3
-#define reg_ddr2_rw_timing___rcd___width 3
-#define reg_ddr2_rw_timing___rp___lsb 6
-#define reg_ddr2_rw_timing___rp___width 3
-#define reg_ddr2_rw_timing___ras___lsb 9
-#define reg_ddr2_rw_timing___ras___width 4
-#define reg_ddr2_rw_timing___rfc___lsb 13
-#define reg_ddr2_rw_timing___rfc___width 7
-#define reg_ddr2_rw_timing___rc___lsb 20
-#define reg_ddr2_rw_timing___rc___width 5
-#define reg_ddr2_rw_timing___rtp___lsb 25
-#define reg_ddr2_rw_timing___rtp___width 2
-#define reg_ddr2_rw_timing___rtw___lsb 27
-#define reg_ddr2_rw_timing___rtw___width 3
-#define reg_ddr2_rw_timing___wtr___lsb 30
-#define reg_ddr2_rw_timing___wtr___width 2
-#define reg_ddr2_rw_timing_offset 4
-
-/* Register rw_latency, scope ddr2, type rw */
-#define reg_ddr2_rw_latency___cas___lsb 0
-#define reg_ddr2_rw_latency___cas___width 3
-#define reg_ddr2_rw_latency___additive___lsb 3
-#define reg_ddr2_rw_latency___additive___width 3
-#define reg_ddr2_rw_latency_offset 8
-
-/* Register rw_phy_cfg, scope ddr2, type rw */
-#define reg_ddr2_rw_phy_cfg___en___lsb 0
-#define reg_ddr2_rw_phy_cfg___en___width 1
-#define reg_ddr2_rw_phy_cfg___en___bit 0
-#define reg_ddr2_rw_phy_cfg_offset 12
-
-/* Register rw_phy_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
-#define reg_ddr2_rw_phy_ctrl___rst___width 1
-#define reg_ddr2_rw_phy_ctrl___rst___bit 0
-#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
-#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
-#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
-#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
-#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
-#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
-#define reg_ddr2_rw_phy_ctrl_offset 16
-
-/* Register rw_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
-#define reg_ddr2_rw_ctrl___mrs_data___width 16
-#define reg_ddr2_rw_ctrl___cmd___lsb 16
-#define reg_ddr2_rw_ctrl___cmd___width 8
-#define reg_ddr2_rw_ctrl_offset 20
-
-/* Register rw_pwr_down, scope ddr2, type rw */
-#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
-#define reg_ddr2_rw_pwr_down___self_ref___width 2
-#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
-#define reg_ddr2_rw_pwr_down___phy_en___width 1
-#define reg_ddr2_rw_pwr_down___phy_en___bit 2
-#define reg_ddr2_rw_pwr_down_offset 24
-
-/* Register r_stat, scope ddr2, type r */
-#define reg_ddr2_r_stat___dll_lock___lsb 0
-#define reg_ddr2_r_stat___dll_lock___width 1
-#define reg_ddr2_r_stat___dll_lock___bit 0
-#define reg_ddr2_r_stat___dll_delay_code___lsb 1
-#define reg_ddr2_r_stat___dll_delay_code___width 7
-#define reg_ddr2_r_stat___imp_cal_done___lsb 8
-#define reg_ddr2_r_stat___imp_cal_done___width 1
-#define reg_ddr2_r_stat___imp_cal_done___bit 8
-#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
-#define reg_ddr2_r_stat___imp_cal_fault___width 1
-#define reg_ddr2_r_stat___imp_cal_fault___bit 9
-#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
-#define reg_ddr2_r_stat___cal_imp_pu___width 4
-#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
-#define reg_ddr2_r_stat___cal_imp_pd___width 4
-#define reg_ddr2_r_stat_offset 28
-
-/* Register rw_imp_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
-#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
-#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
-#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
-#define reg_ddr2_rw_imp_ctrl_offset 32
-
-#define STRIDE_ddr2_rw_dll_ctrl 4
-/* Register rw_dll_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
-#define reg_ddr2_rw_dll_ctrl___mode___width 1
-#define reg_ddr2_rw_dll_ctrl___mode___bit 0
-#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
-#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
-#define reg_ddr2_rw_dll_ctrl_offset 36
-
-#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
-/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
-#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
-#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
-
-
-/* Constants */
-#define regk_ddr2_al0 0x00000000
-#define regk_ddr2_al1 0x00000008
-#define regk_ddr2_al2 0x00000010
-#define regk_ddr2_al3 0x00000018
-#define regk_ddr2_al4 0x00000020
-#define regk_ddr2_auto 0x00000003
-#define regk_ddr2_bank4 0x00000000
-#define regk_ddr2_bank8 0x00000001
-#define regk_ddr2_bl4 0x00000002
-#define regk_ddr2_bl8 0x00000003
-#define regk_ddr2_bt_il 0x00000008
-#define regk_ddr2_bt_seq 0x00000000
-#define regk_ddr2_bw16 0x00000001
-#define regk_ddr2_bw32 0x00000000
-#define regk_ddr2_cas2 0x00000020
-#define regk_ddr2_cas3 0x00000030
-#define regk_ddr2_cas4 0x00000040
-#define regk_ddr2_cas5 0x00000050
-#define regk_ddr2_deselect 0x000000c0
-#define regk_ddr2_dic_weak 0x00000002
-#define regk_ddr2_direct 0x00000001
-#define regk_ddr2_dis 0x00000000
-#define regk_ddr2_dll_dis 0x00000001
-#define regk_ddr2_dll_en 0x00000000
-#define regk_ddr2_dll_rst 0x00000100
-#define regk_ddr2_emrs 0x00000081
-#define regk_ddr2_emrs2 0x00000082
-#define regk_ddr2_emrs3 0x00000083
-#define regk_ddr2_full 0x00000001
-#define regk_ddr2_hi_ref_rate 0x00000080
-#define regk_ddr2_mrs 0x00000080
-#define regk_ddr2_no 0x00000000
-#define regk_ddr2_nop 0x000000b8
-#define regk_ddr2_ocd_adj 0x00000200
-#define regk_ddr2_ocd_default 0x00000380
-#define regk_ddr2_ocd_drive0 0x00000100
-#define regk_ddr2_ocd_drive1 0x00000080
-#define regk_ddr2_ocd_exit 0x00000000
-#define regk_ddr2_odt_dis 0x00000000
-#define regk_ddr2_offs 0x00000000
-#define regk_ddr2_pre 0x00000090
-#define regk_ddr2_pre_all 0x00000400
-#define regk_ddr2_pwr_down_fast 0x00000000
-#define regk_ddr2_pwr_down_slow 0x00001000
-#define regk_ddr2_ref 0x00000088
-#define regk_ddr2_rtt150 0x00000040
-#define regk_ddr2_rtt50 0x00000044
-#define regk_ddr2_rtt75 0x00000004
-#define regk_ddr2_rw_cfg_default 0x00186000
-#define regk_ddr2_rw_dll_ctrl_default 0x00000000
-#define regk_ddr2_rw_dll_ctrl_size 0x00000004
-#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000
-#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004
-#define regk_ddr2_rw_latency_default 0x00000000
-#define regk_ddr2_rw_phy_cfg_default 0x00000000
-#define regk_ddr2_rw_pwr_down_default 0x00000000
-#define regk_ddr2_rw_timing_default 0x00000000
-#define regk_ddr2_s1Gb 0x0000001a
-#define regk_ddr2_s256Mb 0x0000000f
-#define regk_ddr2_s2Gb 0x00000027
-#define regk_ddr2_s4Gb 0x00000042
-#define regk_ddr2_s512Mb 0x00000015
-#define regk_ddr2_temp0_85 0x00000618
-#define regk_ddr2_temp85_95 0x0000030c
-#define regk_ddr2_term150 0x00000002
-#define regk_ddr2_term50 0x00000003
-#define regk_ddr2_term75 0x00000001
-#define regk_ddr2_test 0x00000080
-#define regk_ddr2_weak 0x00000000
-#define regk_ddr2_wr2 0x00000200
-#define regk_ddr2_wr3 0x00000400
-#define regk_ddr2_yes 0x00000001
-#endif /* __ddr2_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index 04b7ff3f70a2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,850 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: gio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 32
-#define reg_gio_r_pa_din_offset 0
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 32
-#define reg_gio_rw_pa_dout_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 32
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_pa_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte0_dout___data___lsb 0
-#define reg_gio_rw_pa_byte0_dout___data___width 8
-#define reg_gio_rw_pa_byte0_dout_offset 12
-
-/* Register rw_pa_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte0_oe___oe___width 8
-#define reg_gio_rw_pa_byte0_oe_offset 16
-
-/* Register rw_pa_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte1_dout___data___lsb 0
-#define reg_gio_rw_pa_byte1_dout___data___width 8
-#define reg_gio_rw_pa_byte1_dout_offset 20
-
-/* Register rw_pa_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte1_oe___oe___width 8
-#define reg_gio_rw_pa_byte1_oe_offset 24
-
-/* Register rw_pa_byte2_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte2_dout___data___lsb 0
-#define reg_gio_rw_pa_byte2_dout___data___width 8
-#define reg_gio_rw_pa_byte2_dout_offset 28
-
-/* Register rw_pa_byte2_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte2_oe___oe___width 8
-#define reg_gio_rw_pa_byte2_oe_offset 32
-
-/* Register rw_pa_byte3_dout, scope gio, type rw */
-#define reg_gio_rw_pa_byte3_dout___data___lsb 0
-#define reg_gio_rw_pa_byte3_dout___data___width 8
-#define reg_gio_rw_pa_byte3_dout_offset 36
-
-/* Register rw_pa_byte3_oe, scope gio, type rw */
-#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
-#define reg_gio_rw_pa_byte3_oe___oe___width 8
-#define reg_gio_rw_pa_byte3_oe_offset 40
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 32
-#define reg_gio_r_pb_din_offset 44
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 32
-#define reg_gio_rw_pb_dout_offset 48
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 32
-#define reg_gio_rw_pb_oe_offset 52
-
-/* Register rw_pb_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte0_dout___data___lsb 0
-#define reg_gio_rw_pb_byte0_dout___data___width 8
-#define reg_gio_rw_pb_byte0_dout_offset 56
-
-/* Register rw_pb_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte0_oe___oe___width 8
-#define reg_gio_rw_pb_byte0_oe_offset 60
-
-/* Register rw_pb_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte1_dout___data___lsb 0
-#define reg_gio_rw_pb_byte1_dout___data___width 8
-#define reg_gio_rw_pb_byte1_dout_offset 64
-
-/* Register rw_pb_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte1_oe___oe___width 8
-#define reg_gio_rw_pb_byte1_oe_offset 68
-
-/* Register rw_pb_byte2_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte2_dout___data___lsb 0
-#define reg_gio_rw_pb_byte2_dout___data___width 8
-#define reg_gio_rw_pb_byte2_dout_offset 72
-
-/* Register rw_pb_byte2_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte2_oe___oe___width 8
-#define reg_gio_rw_pb_byte2_oe_offset 76
-
-/* Register rw_pb_byte3_dout, scope gio, type rw */
-#define reg_gio_rw_pb_byte3_dout___data___lsb 0
-#define reg_gio_rw_pb_byte3_dout___data___width 8
-#define reg_gio_rw_pb_byte3_dout_offset 80
-
-/* Register rw_pb_byte3_oe, scope gio, type rw */
-#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
-#define reg_gio_rw_pb_byte3_oe___oe___width 8
-#define reg_gio_rw_pb_byte3_oe_offset 84
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 16
-#define reg_gio_r_pc_din_offset 88
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 16
-#define reg_gio_rw_pc_dout_offset 92
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 16
-#define reg_gio_rw_pc_oe_offset 96
-
-/* Register rw_pc_byte0_dout, scope gio, type rw */
-#define reg_gio_rw_pc_byte0_dout___data___lsb 0
-#define reg_gio_rw_pc_byte0_dout___data___width 8
-#define reg_gio_rw_pc_byte0_dout_offset 100
-
-/* Register rw_pc_byte0_oe, scope gio, type rw */
-#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
-#define reg_gio_rw_pc_byte0_oe___oe___width 8
-#define reg_gio_rw_pc_byte0_oe_offset 104
-
-/* Register rw_pc_byte1_dout, scope gio, type rw */
-#define reg_gio_rw_pc_byte1_dout___data___lsb 0
-#define reg_gio_rw_pc_byte1_dout___data___width 8
-#define reg_gio_rw_pc_byte1_dout_offset 108
-
-/* Register rw_pc_byte1_oe, scope gio, type rw */
-#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
-#define reg_gio_rw_pc_byte1_oe___oe___width 8
-#define reg_gio_rw_pc_byte1_oe_offset 112
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 32
-#define reg_gio_r_pd_din_offset 116
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___intr0___lsb 0
-#define reg_gio_rw_intr_cfg___intr0___width 3
-#define reg_gio_rw_intr_cfg___intr1___lsb 3
-#define reg_gio_rw_intr_cfg___intr1___width 3
-#define reg_gio_rw_intr_cfg___intr2___lsb 6
-#define reg_gio_rw_intr_cfg___intr2___width 3
-#define reg_gio_rw_intr_cfg___intr3___lsb 9
-#define reg_gio_rw_intr_cfg___intr3___width 3
-#define reg_gio_rw_intr_cfg___intr4___lsb 12
-#define reg_gio_rw_intr_cfg___intr4___width 3
-#define reg_gio_rw_intr_cfg___intr5___lsb 15
-#define reg_gio_rw_intr_cfg___intr5___width 3
-#define reg_gio_rw_intr_cfg___intr6___lsb 18
-#define reg_gio_rw_intr_cfg___intr6___width 3
-#define reg_gio_rw_intr_cfg___intr7___lsb 21
-#define reg_gio_rw_intr_cfg___intr7___width 3
-#define reg_gio_rw_intr_cfg_offset 120
-
-/* Register rw_intr_pins, scope gio, type rw */
-#define reg_gio_rw_intr_pins___intr0___lsb 0
-#define reg_gio_rw_intr_pins___intr0___width 4
-#define reg_gio_rw_intr_pins___intr1___lsb 4
-#define reg_gio_rw_intr_pins___intr1___width 4
-#define reg_gio_rw_intr_pins___intr2___lsb 8
-#define reg_gio_rw_intr_pins___intr2___width 4
-#define reg_gio_rw_intr_pins___intr3___lsb 12
-#define reg_gio_rw_intr_pins___intr3___width 4
-#define reg_gio_rw_intr_pins___intr4___lsb 16
-#define reg_gio_rw_intr_pins___intr4___width 4
-#define reg_gio_rw_intr_pins___intr5___lsb 20
-#define reg_gio_rw_intr_pins___intr5___width 4
-#define reg_gio_rw_intr_pins___intr6___lsb 24
-#define reg_gio_rw_intr_pins___intr6___width 4
-#define reg_gio_rw_intr_pins___intr7___lsb 28
-#define reg_gio_rw_intr_pins___intr7___width 4
-#define reg_gio_rw_intr_pins_offset 124
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___intr0___lsb 0
-#define reg_gio_rw_intr_mask___intr0___width 1
-#define reg_gio_rw_intr_mask___intr0___bit 0
-#define reg_gio_rw_intr_mask___intr1___lsb 1
-#define reg_gio_rw_intr_mask___intr1___width 1
-#define reg_gio_rw_intr_mask___intr1___bit 1
-#define reg_gio_rw_intr_mask___intr2___lsb 2
-#define reg_gio_rw_intr_mask___intr2___width 1
-#define reg_gio_rw_intr_mask___intr2___bit 2
-#define reg_gio_rw_intr_mask___intr3___lsb 3
-#define reg_gio_rw_intr_mask___intr3___width 1
-#define reg_gio_rw_intr_mask___intr3___bit 3
-#define reg_gio_rw_intr_mask___intr4___lsb 4
-#define reg_gio_rw_intr_mask___intr4___width 1
-#define reg_gio_rw_intr_mask___intr4___bit 4
-#define reg_gio_rw_intr_mask___intr5___lsb 5
-#define reg_gio_rw_intr_mask___intr5___width 1
-#define reg_gio_rw_intr_mask___intr5___bit 5
-#define reg_gio_rw_intr_mask___intr6___lsb 6
-#define reg_gio_rw_intr_mask___intr6___width 1
-#define reg_gio_rw_intr_mask___intr6___bit 6
-#define reg_gio_rw_intr_mask___intr7___lsb 7
-#define reg_gio_rw_intr_mask___intr7___width 1
-#define reg_gio_rw_intr_mask___intr7___bit 7
-#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
-#define reg_gio_rw_intr_mask___i2c0_done___width 1
-#define reg_gio_rw_intr_mask___i2c0_done___bit 8
-#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
-#define reg_gio_rw_intr_mask___i2c1_done___width 1
-#define reg_gio_rw_intr_mask___i2c1_done___bit 9
-#define reg_gio_rw_intr_mask_offset 128
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___intr0___lsb 0
-#define reg_gio_rw_ack_intr___intr0___width 1
-#define reg_gio_rw_ack_intr___intr0___bit 0
-#define reg_gio_rw_ack_intr___intr1___lsb 1
-#define reg_gio_rw_ack_intr___intr1___width 1
-#define reg_gio_rw_ack_intr___intr1___bit 1
-#define reg_gio_rw_ack_intr___intr2___lsb 2
-#define reg_gio_rw_ack_intr___intr2___width 1
-#define reg_gio_rw_ack_intr___intr2___bit 2
-#define reg_gio_rw_ack_intr___intr3___lsb 3
-#define reg_gio_rw_ack_intr___intr3___width 1
-#define reg_gio_rw_ack_intr___intr3___bit 3
-#define reg_gio_rw_ack_intr___intr4___lsb 4
-#define reg_gio_rw_ack_intr___intr4___width 1
-#define reg_gio_rw_ack_intr___intr4___bit 4
-#define reg_gio_rw_ack_intr___intr5___lsb 5
-#define reg_gio_rw_ack_intr___intr5___width 1
-#define reg_gio_rw_ack_intr___intr5___bit 5
-#define reg_gio_rw_ack_intr___intr6___lsb 6
-#define reg_gio_rw_ack_intr___intr6___width 1
-#define reg_gio_rw_ack_intr___intr6___bit 6
-#define reg_gio_rw_ack_intr___intr7___lsb 7
-#define reg_gio_rw_ack_intr___intr7___width 1
-#define reg_gio_rw_ack_intr___intr7___bit 7
-#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
-#define reg_gio_rw_ack_intr___i2c0_done___width 1
-#define reg_gio_rw_ack_intr___i2c0_done___bit 8
-#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
-#define reg_gio_rw_ack_intr___i2c1_done___width 1
-#define reg_gio_rw_ack_intr___i2c1_done___bit 9
-#define reg_gio_rw_ack_intr_offset 132
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___intr0___lsb 0
-#define reg_gio_r_intr___intr0___width 1
-#define reg_gio_r_intr___intr0___bit 0
-#define reg_gio_r_intr___intr1___lsb 1
-#define reg_gio_r_intr___intr1___width 1
-#define reg_gio_r_intr___intr1___bit 1
-#define reg_gio_r_intr___intr2___lsb 2
-#define reg_gio_r_intr___intr2___width 1
-#define reg_gio_r_intr___intr2___bit 2
-#define reg_gio_r_intr___intr3___lsb 3
-#define reg_gio_r_intr___intr3___width 1
-#define reg_gio_r_intr___intr3___bit 3
-#define reg_gio_r_intr___intr4___lsb 4
-#define reg_gio_r_intr___intr4___width 1
-#define reg_gio_r_intr___intr4___bit 4
-#define reg_gio_r_intr___intr5___lsb 5
-#define reg_gio_r_intr___intr5___width 1
-#define reg_gio_r_intr___intr5___bit 5
-#define reg_gio_r_intr___intr6___lsb 6
-#define reg_gio_r_intr___intr6___width 1
-#define reg_gio_r_intr___intr6___bit 6
-#define reg_gio_r_intr___intr7___lsb 7
-#define reg_gio_r_intr___intr7___width 1
-#define reg_gio_r_intr___intr7___bit 7
-#define reg_gio_r_intr___i2c0_done___lsb 8
-#define reg_gio_r_intr___i2c0_done___width 1
-#define reg_gio_r_intr___i2c0_done___bit 8
-#define reg_gio_r_intr___i2c1_done___lsb 9
-#define reg_gio_r_intr___i2c1_done___width 1
-#define reg_gio_r_intr___i2c1_done___bit 9
-#define reg_gio_r_intr_offset 136
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___intr0___lsb 0
-#define reg_gio_r_masked_intr___intr0___width 1
-#define reg_gio_r_masked_intr___intr0___bit 0
-#define reg_gio_r_masked_intr___intr1___lsb 1
-#define reg_gio_r_masked_intr___intr1___width 1
-#define reg_gio_r_masked_intr___intr1___bit 1
-#define reg_gio_r_masked_intr___intr2___lsb 2
-#define reg_gio_r_masked_intr___intr2___width 1
-#define reg_gio_r_masked_intr___intr2___bit 2
-#define reg_gio_r_masked_intr___intr3___lsb 3
-#define reg_gio_r_masked_intr___intr3___width 1
-#define reg_gio_r_masked_intr___intr3___bit 3
-#define reg_gio_r_masked_intr___intr4___lsb 4
-#define reg_gio_r_masked_intr___intr4___width 1
-#define reg_gio_r_masked_intr___intr4___bit 4
-#define reg_gio_r_masked_intr___intr5___lsb 5
-#define reg_gio_r_masked_intr___intr5___width 1
-#define reg_gio_r_masked_intr___intr5___bit 5
-#define reg_gio_r_masked_intr___intr6___lsb 6
-#define reg_gio_r_masked_intr___intr6___width 1
-#define reg_gio_r_masked_intr___intr6___bit 6
-#define reg_gio_r_masked_intr___intr7___lsb 7
-#define reg_gio_r_masked_intr___intr7___width 1
-#define reg_gio_r_masked_intr___intr7___bit 7
-#define reg_gio_r_masked_intr___i2c0_done___lsb 8
-#define reg_gio_r_masked_intr___i2c0_done___width 1
-#define reg_gio_r_masked_intr___i2c0_done___bit 8
-#define reg_gio_r_masked_intr___i2c1_done___lsb 9
-#define reg_gio_r_masked_intr___i2c1_done___width 1
-#define reg_gio_r_masked_intr___i2c1_done___bit 9
-#define reg_gio_r_masked_intr_offset 140
-
-/* Register rw_i2c0_start, scope gio, type rw */
-#define reg_gio_rw_i2c0_start___run___lsb 0
-#define reg_gio_rw_i2c0_start___run___width 1
-#define reg_gio_rw_i2c0_start___run___bit 0
-#define reg_gio_rw_i2c0_start_offset 144
-
-/* Register rw_i2c0_cfg, scope gio, type rw */
-#define reg_gio_rw_i2c0_cfg___en___lsb 0
-#define reg_gio_rw_i2c0_cfg___en___width 1
-#define reg_gio_rw_i2c0_cfg___en___bit 0
-#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
-#define reg_gio_rw_i2c0_cfg___bit_order___width 1
-#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
-#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
-#define reg_gio_rw_i2c0_cfg___scl_io___width 1
-#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
-#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
-#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
-#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
-#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
-#define reg_gio_rw_i2c0_cfg___sda_io___width 1
-#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
-#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
-#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
-#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
-#define reg_gio_rw_i2c0_cfg_offset 148
-
-/* Register rw_i2c0_ctrl, scope gio, type rw */
-#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
-#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
-#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
-#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
-#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
-#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
-#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
-#define reg_gio_rw_i2c0_ctrl___early_end___width 1
-#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
-#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
-#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
-#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
-#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
-#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
-#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
-#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
-#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
-#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
-#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
-#define reg_gio_rw_i2c0_ctrl___freq___width 2
-#define reg_gio_rw_i2c0_ctrl_offset 152
-
-/* Register rw_i2c0_data, scope gio, type rw */
-#define reg_gio_rw_i2c0_data___data0___lsb 0
-#define reg_gio_rw_i2c0_data___data0___width 8
-#define reg_gio_rw_i2c0_data___data1___lsb 8
-#define reg_gio_rw_i2c0_data___data1___width 8
-#define reg_gio_rw_i2c0_data___data2___lsb 16
-#define reg_gio_rw_i2c0_data___data2___width 8
-#define reg_gio_rw_i2c0_data___data3___lsb 24
-#define reg_gio_rw_i2c0_data___data3___width 8
-#define reg_gio_rw_i2c0_data_offset 156
-
-/* Register rw_i2c0_data2, scope gio, type rw */
-#define reg_gio_rw_i2c0_data2___data4___lsb 0
-#define reg_gio_rw_i2c0_data2___data4___width 8
-#define reg_gio_rw_i2c0_data2___data5___lsb 8
-#define reg_gio_rw_i2c0_data2___data5___width 8
-#define reg_gio_rw_i2c0_data2___start_val___lsb 16
-#define reg_gio_rw_i2c0_data2___start_val___width 6
-#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
-#define reg_gio_rw_i2c0_data2___ack_val___width 6
-#define reg_gio_rw_i2c0_data2_offset 160
-
-/* Register rw_i2c1_start, scope gio, type rw */
-#define reg_gio_rw_i2c1_start___run___lsb 0
-#define reg_gio_rw_i2c1_start___run___width 1
-#define reg_gio_rw_i2c1_start___run___bit 0
-#define reg_gio_rw_i2c1_start_offset 164
-
-/* Register rw_i2c1_cfg, scope gio, type rw */
-#define reg_gio_rw_i2c1_cfg___en___lsb 0
-#define reg_gio_rw_i2c1_cfg___en___width 1
-#define reg_gio_rw_i2c1_cfg___en___bit 0
-#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
-#define reg_gio_rw_i2c1_cfg___bit_order___width 1
-#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
-#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
-#define reg_gio_rw_i2c1_cfg___scl_io___width 1
-#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
-#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
-#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
-#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
-#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
-#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
-#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
-#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
-#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
-#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
-#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
-#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
-#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
-#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
-#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
-#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
-#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
-#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
-#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
-#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
-#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
-#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
-#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
-#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
-#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
-#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
-#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
-#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
-#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
-#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
-#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
-#define reg_gio_rw_i2c1_cfg_offset 168
-
-/* Register rw_i2c1_ctrl, scope gio, type rw */
-#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
-#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
-#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
-#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
-#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
-#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
-#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
-#define reg_gio_rw_i2c1_ctrl___early_end___width 1
-#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
-#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
-#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
-#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
-#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
-#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
-#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
-#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
-#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
-#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
-#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
-#define reg_gio_rw_i2c1_ctrl___freq___width 2
-#define reg_gio_rw_i2c1_ctrl_offset 172
-
-/* Register rw_i2c1_data, scope gio, type rw */
-#define reg_gio_rw_i2c1_data___data0___lsb 0
-#define reg_gio_rw_i2c1_data___data0___width 8
-#define reg_gio_rw_i2c1_data___data1___lsb 8
-#define reg_gio_rw_i2c1_data___data1___width 8
-#define reg_gio_rw_i2c1_data___data2___lsb 16
-#define reg_gio_rw_i2c1_data___data2___width 8
-#define reg_gio_rw_i2c1_data___data3___lsb 24
-#define reg_gio_rw_i2c1_data___data3___width 8
-#define reg_gio_rw_i2c1_data_offset 176
-
-/* Register rw_i2c1_data2, scope gio, type rw */
-#define reg_gio_rw_i2c1_data2___data4___lsb 0
-#define reg_gio_rw_i2c1_data2___data4___width 8
-#define reg_gio_rw_i2c1_data2___data5___lsb 8
-#define reg_gio_rw_i2c1_data2___data5___width 8
-#define reg_gio_rw_i2c1_data2___start_val___lsb 16
-#define reg_gio_rw_i2c1_data2___start_val___width 6
-#define reg_gio_rw_i2c1_data2___ack_val___lsb 22
-#define reg_gio_rw_i2c1_data2___ack_val___width 6
-#define reg_gio_rw_i2c1_data2_offset 180
-
-/* Register r_ppwm_stat, scope gio, type r */
-#define reg_gio_r_ppwm_stat___freq___lsb 0
-#define reg_gio_r_ppwm_stat___freq___width 2
-#define reg_gio_r_ppwm_stat_offset 184
-
-/* Register rw_ppwm_data, scope gio, type rw */
-#define reg_gio_rw_ppwm_data___data___lsb 0
-#define reg_gio_rw_ppwm_data___data___width 8
-#define reg_gio_rw_ppwm_data_offset 188
-
-/* Register rw_pwm0_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm0_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm0_ctrl___mode___width 2
-#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm0_ctrl_offset 192
-
-/* Register rw_pwm0_var, scope gio, type rw */
-#define reg_gio_rw_pwm0_var___lo___lsb 0
-#define reg_gio_rw_pwm0_var___lo___width 13
-#define reg_gio_rw_pwm0_var___hi___lsb 13
-#define reg_gio_rw_pwm0_var___hi___width 13
-#define reg_gio_rw_pwm0_var_offset 196
-
-/* Register rw_pwm0_data, scope gio, type rw */
-#define reg_gio_rw_pwm0_data___data___lsb 0
-#define reg_gio_rw_pwm0_data___data___width 8
-#define reg_gio_rw_pwm0_data_offset 200
-
-/* Register rw_pwm1_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm1_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm1_ctrl___mode___width 2
-#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm1_ctrl_offset 204
-
-/* Register rw_pwm1_var, scope gio, type rw */
-#define reg_gio_rw_pwm1_var___lo___lsb 0
-#define reg_gio_rw_pwm1_var___lo___width 13
-#define reg_gio_rw_pwm1_var___hi___lsb 13
-#define reg_gio_rw_pwm1_var___hi___width 13
-#define reg_gio_rw_pwm1_var_offset 208
-
-/* Register rw_pwm1_data, scope gio, type rw */
-#define reg_gio_rw_pwm1_data___data___lsb 0
-#define reg_gio_rw_pwm1_data___data___width 8
-#define reg_gio_rw_pwm1_data_offset 212
-
-/* Register rw_pwm2_ctrl, scope gio, type rw */
-#define reg_gio_rw_pwm2_ctrl___mode___lsb 0
-#define reg_gio_rw_pwm2_ctrl___mode___width 2
-#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2
-#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1
-#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2
-#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3
-#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1
-#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3
-#define reg_gio_rw_pwm2_ctrl_offset 216
-
-/* Register rw_pwm2_var, scope gio, type rw */
-#define reg_gio_rw_pwm2_var___lo___lsb 0
-#define reg_gio_rw_pwm2_var___lo___width 13
-#define reg_gio_rw_pwm2_var___hi___lsb 13
-#define reg_gio_rw_pwm2_var___hi___width 13
-#define reg_gio_rw_pwm2_var_offset 220
-
-/* Register rw_pwm2_data, scope gio, type rw */
-#define reg_gio_rw_pwm2_data___data___lsb 0
-#define reg_gio_rw_pwm2_data___data___width 8
-#define reg_gio_rw_pwm2_data_offset 224
-
-/* Register rw_pwm_in_cfg, scope gio, type rw */
-#define reg_gio_rw_pwm_in_cfg___pin___lsb 0
-#define reg_gio_rw_pwm_in_cfg___pin___width 3
-#define reg_gio_rw_pwm_in_cfg_offset 228
-
-/* Register r_pwm_in_lo, scope gio, type r */
-#define reg_gio_r_pwm_in_lo___data___lsb 0
-#define reg_gio_r_pwm_in_lo___data___width 32
-#define reg_gio_r_pwm_in_lo_offset 232
-
-/* Register r_pwm_in_hi, scope gio, type r */
-#define reg_gio_r_pwm_in_hi___data___lsb 0
-#define reg_gio_r_pwm_in_hi___data___width 32
-#define reg_gio_r_pwm_in_hi_offset 236
-
-/* Register r_pwm_in_cnt, scope gio, type r */
-#define reg_gio_r_pwm_in_cnt___data___lsb 0
-#define reg_gio_r_pwm_in_cnt___data___width 32
-#define reg_gio_r_pwm_in_cnt_offset 240
-
-
-/* Constants */
-#define regk_gio_anyedge 0x00000007
-#define regk_gio_f100k 0x00000000
-#define regk_gio_f1562 0x00000000
-#define regk_gio_f195 0x00000003
-#define regk_gio_f1m 0x00000002
-#define regk_gio_f390 0x00000002
-#define regk_gio_f400k 0x00000001
-#define regk_gio_f5m 0x00000003
-#define regk_gio_f781 0x00000001
-#define regk_gio_hi 0x00000001
-#define regk_gio_in 0x00000000
-#define regk_gio_intr_pa0 0x00000000
-#define regk_gio_intr_pa1 0x00000000
-#define regk_gio_intr_pa10 0x00000001
-#define regk_gio_intr_pa11 0x00000001
-#define regk_gio_intr_pa12 0x00000001
-#define regk_gio_intr_pa13 0x00000001
-#define regk_gio_intr_pa14 0x00000001
-#define regk_gio_intr_pa15 0x00000001
-#define regk_gio_intr_pa16 0x00000002
-#define regk_gio_intr_pa17 0x00000002
-#define regk_gio_intr_pa18 0x00000002
-#define regk_gio_intr_pa19 0x00000002
-#define regk_gio_intr_pa2 0x00000000
-#define regk_gio_intr_pa20 0x00000002
-#define regk_gio_intr_pa21 0x00000002
-#define regk_gio_intr_pa22 0x00000002
-#define regk_gio_intr_pa23 0x00000002
-#define regk_gio_intr_pa24 0x00000003
-#define regk_gio_intr_pa25 0x00000003
-#define regk_gio_intr_pa26 0x00000003
-#define regk_gio_intr_pa27 0x00000003
-#define regk_gio_intr_pa28 0x00000003
-#define regk_gio_intr_pa29 0x00000003
-#define regk_gio_intr_pa3 0x00000000
-#define regk_gio_intr_pa30 0x00000003
-#define regk_gio_intr_pa31 0x00000003
-#define regk_gio_intr_pa4 0x00000000
-#define regk_gio_intr_pa5 0x00000000
-#define regk_gio_intr_pa6 0x00000000
-#define regk_gio_intr_pa7 0x00000000
-#define regk_gio_intr_pa8 0x00000001
-#define regk_gio_intr_pa9 0x00000001
-#define regk_gio_intr_pb0 0x00000004
-#define regk_gio_intr_pb1 0x00000004
-#define regk_gio_intr_pb10 0x00000005
-#define regk_gio_intr_pb11 0x00000005
-#define regk_gio_intr_pb12 0x00000005
-#define regk_gio_intr_pb13 0x00000005
-#define regk_gio_intr_pb14 0x00000005
-#define regk_gio_intr_pb15 0x00000005
-#define regk_gio_intr_pb16 0x00000006
-#define regk_gio_intr_pb17 0x00000006
-#define regk_gio_intr_pb18 0x00000006
-#define regk_gio_intr_pb19 0x00000006
-#define regk_gio_intr_pb2 0x00000004
-#define regk_gio_intr_pb20 0x00000006
-#define regk_gio_intr_pb21 0x00000006
-#define regk_gio_intr_pb22 0x00000006
-#define regk_gio_intr_pb23 0x00000006
-#define regk_gio_intr_pb24 0x00000007
-#define regk_gio_intr_pb25 0x00000007
-#define regk_gio_intr_pb26 0x00000007
-#define regk_gio_intr_pb27 0x00000007
-#define regk_gio_intr_pb28 0x00000007
-#define regk_gio_intr_pb29 0x00000007
-#define regk_gio_intr_pb3 0x00000004
-#define regk_gio_intr_pb30 0x00000007
-#define regk_gio_intr_pb31 0x00000007
-#define regk_gio_intr_pb4 0x00000004
-#define regk_gio_intr_pb5 0x00000004
-#define regk_gio_intr_pb6 0x00000004
-#define regk_gio_intr_pb7 0x00000004
-#define regk_gio_intr_pb8 0x00000005
-#define regk_gio_intr_pb9 0x00000005
-#define regk_gio_intr_pc0 0x00000008
-#define regk_gio_intr_pc1 0x00000008
-#define regk_gio_intr_pc10 0x00000009
-#define regk_gio_intr_pc11 0x00000009
-#define regk_gio_intr_pc12 0x00000009
-#define regk_gio_intr_pc13 0x00000009
-#define regk_gio_intr_pc14 0x00000009
-#define regk_gio_intr_pc15 0x00000009
-#define regk_gio_intr_pc2 0x00000008
-#define regk_gio_intr_pc3 0x00000008
-#define regk_gio_intr_pc4 0x00000008
-#define regk_gio_intr_pc5 0x00000008
-#define regk_gio_intr_pc6 0x00000008
-#define regk_gio_intr_pc7 0x00000008
-#define regk_gio_intr_pc8 0x00000009
-#define regk_gio_intr_pc9 0x00000009
-#define regk_gio_intr_pd0 0x0000000c
-#define regk_gio_intr_pd1 0x0000000c
-#define regk_gio_intr_pd10 0x0000000d
-#define regk_gio_intr_pd11 0x0000000d
-#define regk_gio_intr_pd12 0x0000000d
-#define regk_gio_intr_pd13 0x0000000d
-#define regk_gio_intr_pd14 0x0000000d
-#define regk_gio_intr_pd15 0x0000000d
-#define regk_gio_intr_pd16 0x0000000e
-#define regk_gio_intr_pd17 0x0000000e
-#define regk_gio_intr_pd18 0x0000000e
-#define regk_gio_intr_pd19 0x0000000e
-#define regk_gio_intr_pd2 0x0000000c
-#define regk_gio_intr_pd20 0x0000000e
-#define regk_gio_intr_pd21 0x0000000e
-#define regk_gio_intr_pd22 0x0000000e
-#define regk_gio_intr_pd23 0x0000000e
-#define regk_gio_intr_pd24 0x0000000f
-#define regk_gio_intr_pd25 0x0000000f
-#define regk_gio_intr_pd26 0x0000000f
-#define regk_gio_intr_pd27 0x0000000f
-#define regk_gio_intr_pd28 0x0000000f
-#define regk_gio_intr_pd29 0x0000000f
-#define regk_gio_intr_pd3 0x0000000c
-#define regk_gio_intr_pd30 0x0000000f
-#define regk_gio_intr_pd31 0x0000000f
-#define regk_gio_intr_pd4 0x0000000c
-#define regk_gio_intr_pd5 0x0000000c
-#define regk_gio_intr_pd6 0x0000000c
-#define regk_gio_intr_pd7 0x0000000c
-#define regk_gio_intr_pd8 0x0000000d
-#define regk_gio_intr_pd9 0x0000000d
-#define regk_gio_lo 0x00000002
-#define regk_gio_lsb 0x00000000
-#define regk_gio_msb 0x00000001
-#define regk_gio_negedge 0x00000006
-#define regk_gio_no 0x00000000
-#define regk_gio_no_switch 0x0000003f
-#define regk_gio_none 0x00000007
-#define regk_gio_off 0x00000000
-#define regk_gio_opendrain 0x00000000
-#define regk_gio_out 0x00000001
-#define regk_gio_posedge 0x00000005
-#define regk_gio_pwm_hfp 0x00000002
-#define regk_gio_pwm_pa0 0x00000001
-#define regk_gio_pwm_pa19 0x00000004
-#define regk_gio_pwm_pa6 0x00000002
-#define regk_gio_pwm_pa7 0x00000003
-#define regk_gio_pwm_pb26 0x00000005
-#define regk_gio_pwm_pd23 0x00000006
-#define regk_gio_pwm_pd31 0x00000007
-#define regk_gio_pwm_std 0x00000001
-#define regk_gio_pwm_var 0x00000003
-#define regk_gio_rw_i2c0_cfg_default 0x00000020
-#define regk_gio_rw_i2c0_ctrl_default 0x00010000
-#define regk_gio_rw_i2c0_start_default 0x00000000
-#define regk_gio_rw_i2c1_cfg_default 0x00000aa0
-#define regk_gio_rw_i2c1_ctrl_default 0x00010000
-#define regk_gio_rw_i2c1_start_default 0x00000000
-#define regk_gio_rw_intr_cfg_default 0x00000000
-#define regk_gio_rw_intr_mask_default 0x00000000
-#define regk_gio_rw_pa_oe_default 0x00000000
-#define regk_gio_rw_pb_oe_default 0x00000000
-#define regk_gio_rw_pc_oe_default 0x00000000
-#define regk_gio_rw_ppwm_data_default 0x00000000
-#define regk_gio_rw_pwm0_ctrl_default 0x00000000
-#define regk_gio_rw_pwm1_ctrl_default 0x00000000
-#define regk_gio_rw_pwm2_ctrl_default 0x00000000
-#define regk_gio_rw_pwm_in_cfg_default 0x00000000
-#define regk_gio_sda0 0x00000000
-#define regk_gio_sda1 0x00000001
-#define regk_gio_sda2 0x00000002
-#define regk_gio_sda3 0x00000003
-#define regk_gio_sen 0x00000000
-#define regk_gio_set 0x00000003
-#define regk_gio_yes 0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h
deleted file mode 100644
index a73168a8e93a..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pinmux_defs_asm.h
+++ /dev/null
@@ -1,573 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_asm_h
-#define __pinmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: pinmux.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_hwprot, scope pinmux, type rw */
-#define reg_pinmux_rw_hwprot___eth___lsb 0
-#define reg_pinmux_rw_hwprot___eth___width 1
-#define reg_pinmux_rw_hwprot___eth___bit 0
-#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1
-#define reg_pinmux_rw_hwprot___eth_mdio___width 1
-#define reg_pinmux_rw_hwprot___eth_mdio___bit 1
-#define reg_pinmux_rw_hwprot___geth___lsb 2
-#define reg_pinmux_rw_hwprot___geth___width 1
-#define reg_pinmux_rw_hwprot___geth___bit 2
-#define reg_pinmux_rw_hwprot___tg___lsb 3
-#define reg_pinmux_rw_hwprot___tg___width 1
-#define reg_pinmux_rw_hwprot___tg___bit 3
-#define reg_pinmux_rw_hwprot___tg_clk___lsb 4
-#define reg_pinmux_rw_hwprot___tg_clk___width 1
-#define reg_pinmux_rw_hwprot___tg_clk___bit 4
-#define reg_pinmux_rw_hwprot___vout___lsb 5
-#define reg_pinmux_rw_hwprot___vout___width 1
-#define reg_pinmux_rw_hwprot___vout___bit 5
-#define reg_pinmux_rw_hwprot___vout_sync___lsb 6
-#define reg_pinmux_rw_hwprot___vout_sync___width 1
-#define reg_pinmux_rw_hwprot___vout_sync___bit 6
-#define reg_pinmux_rw_hwprot___ser1___lsb 7
-#define reg_pinmux_rw_hwprot___ser1___width 1
-#define reg_pinmux_rw_hwprot___ser1___bit 7
-#define reg_pinmux_rw_hwprot___ser2___lsb 8
-#define reg_pinmux_rw_hwprot___ser2___width 1
-#define reg_pinmux_rw_hwprot___ser2___bit 8
-#define reg_pinmux_rw_hwprot___ser3___lsb 9
-#define reg_pinmux_rw_hwprot___ser3___width 1
-#define reg_pinmux_rw_hwprot___ser3___bit 9
-#define reg_pinmux_rw_hwprot___ser4___lsb 10
-#define reg_pinmux_rw_hwprot___ser4___width 1
-#define reg_pinmux_rw_hwprot___ser4___bit 10
-#define reg_pinmux_rw_hwprot___sser___lsb 11
-#define reg_pinmux_rw_hwprot___sser___width 1
-#define reg_pinmux_rw_hwprot___sser___bit 11
-#define reg_pinmux_rw_hwprot___pwm0___lsb 12
-#define reg_pinmux_rw_hwprot___pwm0___width 1
-#define reg_pinmux_rw_hwprot___pwm0___bit 12
-#define reg_pinmux_rw_hwprot___pwm1___lsb 13
-#define reg_pinmux_rw_hwprot___pwm1___width 1
-#define reg_pinmux_rw_hwprot___pwm1___bit 13
-#define reg_pinmux_rw_hwprot___pwm2___lsb 14
-#define reg_pinmux_rw_hwprot___pwm2___width 1
-#define reg_pinmux_rw_hwprot___pwm2___bit 14
-#define reg_pinmux_rw_hwprot___timer0___lsb 15
-#define reg_pinmux_rw_hwprot___timer0___width 1
-#define reg_pinmux_rw_hwprot___timer0___bit 15
-#define reg_pinmux_rw_hwprot___timer1___lsb 16
-#define reg_pinmux_rw_hwprot___timer1___width 1
-#define reg_pinmux_rw_hwprot___timer1___bit 16
-#define reg_pinmux_rw_hwprot___pio___lsb 17
-#define reg_pinmux_rw_hwprot___pio___width 1
-#define reg_pinmux_rw_hwprot___pio___bit 17
-#define reg_pinmux_rw_hwprot___i2c0___lsb 18
-#define reg_pinmux_rw_hwprot___i2c0___width 1
-#define reg_pinmux_rw_hwprot___i2c0___bit 18
-#define reg_pinmux_rw_hwprot___i2c1___lsb 19
-#define reg_pinmux_rw_hwprot___i2c1___width 1
-#define reg_pinmux_rw_hwprot___i2c1___bit 19
-#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20
-#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20
-#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21
-#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21
-#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22
-#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22
-#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23
-#define reg_pinmux_rw_hwprot___i2c1_sen___width 1
-#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23
-#define reg_pinmux_rw_hwprot_offset 0
-
-/* Register rw_gio_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pa___pa0___lsb 0
-#define reg_pinmux_rw_gio_pa___pa0___width 1
-#define reg_pinmux_rw_gio_pa___pa0___bit 0
-#define reg_pinmux_rw_gio_pa___pa1___lsb 1
-#define reg_pinmux_rw_gio_pa___pa1___width 1
-#define reg_pinmux_rw_gio_pa___pa1___bit 1
-#define reg_pinmux_rw_gio_pa___pa2___lsb 2
-#define reg_pinmux_rw_gio_pa___pa2___width 1
-#define reg_pinmux_rw_gio_pa___pa2___bit 2
-#define reg_pinmux_rw_gio_pa___pa3___lsb 3
-#define reg_pinmux_rw_gio_pa___pa3___width 1
-#define reg_pinmux_rw_gio_pa___pa3___bit 3
-#define reg_pinmux_rw_gio_pa___pa4___lsb 4
-#define reg_pinmux_rw_gio_pa___pa4___width 1
-#define reg_pinmux_rw_gio_pa___pa4___bit 4
-#define reg_pinmux_rw_gio_pa___pa5___lsb 5
-#define reg_pinmux_rw_gio_pa___pa5___width 1
-#define reg_pinmux_rw_gio_pa___pa5___bit 5
-#define reg_pinmux_rw_gio_pa___pa6___lsb 6
-#define reg_pinmux_rw_gio_pa___pa6___width 1
-#define reg_pinmux_rw_gio_pa___pa6___bit 6
-#define reg_pinmux_rw_gio_pa___pa7___lsb 7
-#define reg_pinmux_rw_gio_pa___pa7___width 1
-#define reg_pinmux_rw_gio_pa___pa7___bit 7
-#define reg_pinmux_rw_gio_pa___pa8___lsb 8
-#define reg_pinmux_rw_gio_pa___pa8___width 1
-#define reg_pinmux_rw_gio_pa___pa8___bit 8
-#define reg_pinmux_rw_gio_pa___pa9___lsb 9
-#define reg_pinmux_rw_gio_pa___pa9___width 1
-#define reg_pinmux_rw_gio_pa___pa9___bit 9
-#define reg_pinmux_rw_gio_pa___pa10___lsb 10
-#define reg_pinmux_rw_gio_pa___pa10___width 1
-#define reg_pinmux_rw_gio_pa___pa10___bit 10
-#define reg_pinmux_rw_gio_pa___pa11___lsb 11
-#define reg_pinmux_rw_gio_pa___pa11___width 1
-#define reg_pinmux_rw_gio_pa___pa11___bit 11
-#define reg_pinmux_rw_gio_pa___pa12___lsb 12
-#define reg_pinmux_rw_gio_pa___pa12___width 1
-#define reg_pinmux_rw_gio_pa___pa12___bit 12
-#define reg_pinmux_rw_gio_pa___pa13___lsb 13
-#define reg_pinmux_rw_gio_pa___pa13___width 1
-#define reg_pinmux_rw_gio_pa___pa13___bit 13
-#define reg_pinmux_rw_gio_pa___pa14___lsb 14
-#define reg_pinmux_rw_gio_pa___pa14___width 1
-#define reg_pinmux_rw_gio_pa___pa14___bit 14
-#define reg_pinmux_rw_gio_pa___pa15___lsb 15
-#define reg_pinmux_rw_gio_pa___pa15___width 1
-#define reg_pinmux_rw_gio_pa___pa15___bit 15
-#define reg_pinmux_rw_gio_pa___pa16___lsb 16
-#define reg_pinmux_rw_gio_pa___pa16___width 1
-#define reg_pinmux_rw_gio_pa___pa16___bit 16
-#define reg_pinmux_rw_gio_pa___pa17___lsb 17
-#define reg_pinmux_rw_gio_pa___pa17___width 1
-#define reg_pinmux_rw_gio_pa___pa17___bit 17
-#define reg_pinmux_rw_gio_pa___pa18___lsb 18
-#define reg_pinmux_rw_gio_pa___pa18___width 1
-#define reg_pinmux_rw_gio_pa___pa18___bit 18
-#define reg_pinmux_rw_gio_pa___pa19___lsb 19
-#define reg_pinmux_rw_gio_pa___pa19___width 1
-#define reg_pinmux_rw_gio_pa___pa19___bit 19
-#define reg_pinmux_rw_gio_pa___pa20___lsb 20
-#define reg_pinmux_rw_gio_pa___pa20___width 1
-#define reg_pinmux_rw_gio_pa___pa20___bit 20
-#define reg_pinmux_rw_gio_pa___pa21___lsb 21
-#define reg_pinmux_rw_gio_pa___pa21___width 1
-#define reg_pinmux_rw_gio_pa___pa21___bit 21
-#define reg_pinmux_rw_gio_pa___pa22___lsb 22
-#define reg_pinmux_rw_gio_pa___pa22___width 1
-#define reg_pinmux_rw_gio_pa___pa22___bit 22
-#define reg_pinmux_rw_gio_pa___pa23___lsb 23
-#define reg_pinmux_rw_gio_pa___pa23___width 1
-#define reg_pinmux_rw_gio_pa___pa23___bit 23
-#define reg_pinmux_rw_gio_pa___pa24___lsb 24
-#define reg_pinmux_rw_gio_pa___pa24___width 1
-#define reg_pinmux_rw_gio_pa___pa24___bit 24
-#define reg_pinmux_rw_gio_pa___pa25___lsb 25
-#define reg_pinmux_rw_gio_pa___pa25___width 1
-#define reg_pinmux_rw_gio_pa___pa25___bit 25
-#define reg_pinmux_rw_gio_pa___pa26___lsb 26
-#define reg_pinmux_rw_gio_pa___pa26___width 1
-#define reg_pinmux_rw_gio_pa___pa26___bit 26
-#define reg_pinmux_rw_gio_pa___pa27___lsb 27
-#define reg_pinmux_rw_gio_pa___pa27___width 1
-#define reg_pinmux_rw_gio_pa___pa27___bit 27
-#define reg_pinmux_rw_gio_pa___pa28___lsb 28
-#define reg_pinmux_rw_gio_pa___pa28___width 1
-#define reg_pinmux_rw_gio_pa___pa28___bit 28
-#define reg_pinmux_rw_gio_pa___pa29___lsb 29
-#define reg_pinmux_rw_gio_pa___pa29___width 1
-#define reg_pinmux_rw_gio_pa___pa29___bit 29
-#define reg_pinmux_rw_gio_pa___pa30___lsb 30
-#define reg_pinmux_rw_gio_pa___pa30___width 1
-#define reg_pinmux_rw_gio_pa___pa30___bit 30
-#define reg_pinmux_rw_gio_pa___pa31___lsb 31
-#define reg_pinmux_rw_gio_pa___pa31___width 1
-#define reg_pinmux_rw_gio_pa___pa31___bit 31
-#define reg_pinmux_rw_gio_pa_offset 4
-
-/* Register rw_gio_pb, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pb___pb0___lsb 0
-#define reg_pinmux_rw_gio_pb___pb0___width 1
-#define reg_pinmux_rw_gio_pb___pb0___bit 0
-#define reg_pinmux_rw_gio_pb___pb1___lsb 1
-#define reg_pinmux_rw_gio_pb___pb1___width 1
-#define reg_pinmux_rw_gio_pb___pb1___bit 1
-#define reg_pinmux_rw_gio_pb___pb2___lsb 2
-#define reg_pinmux_rw_gio_pb___pb2___width 1
-#define reg_pinmux_rw_gio_pb___pb2___bit 2
-#define reg_pinmux_rw_gio_pb___pb3___lsb 3
-#define reg_pinmux_rw_gio_pb___pb3___width 1
-#define reg_pinmux_rw_gio_pb___pb3___bit 3
-#define reg_pinmux_rw_gio_pb___pb4___lsb 4
-#define reg_pinmux_rw_gio_pb___pb4___width 1
-#define reg_pinmux_rw_gio_pb___pb4___bit 4
-#define reg_pinmux_rw_gio_pb___pb5___lsb 5
-#define reg_pinmux_rw_gio_pb___pb5___width 1
-#define reg_pinmux_rw_gio_pb___pb5___bit 5
-#define reg_pinmux_rw_gio_pb___pb6___lsb 6
-#define reg_pinmux_rw_gio_pb___pb6___width 1
-#define reg_pinmux_rw_gio_pb___pb6___bit 6
-#define reg_pinmux_rw_gio_pb___pb7___lsb 7
-#define reg_pinmux_rw_gio_pb___pb7___width 1
-#define reg_pinmux_rw_gio_pb___pb7___bit 7
-#define reg_pinmux_rw_gio_pb___pb8___lsb 8
-#define reg_pinmux_rw_gio_pb___pb8___width 1
-#define reg_pinmux_rw_gio_pb___pb8___bit 8
-#define reg_pinmux_rw_gio_pb___pb9___lsb 9
-#define reg_pinmux_rw_gio_pb___pb9___width 1
-#define reg_pinmux_rw_gio_pb___pb9___bit 9
-#define reg_pinmux_rw_gio_pb___pb10___lsb 10
-#define reg_pinmux_rw_gio_pb___pb10___width 1
-#define reg_pinmux_rw_gio_pb___pb10___bit 10
-#define reg_pinmux_rw_gio_pb___pb11___lsb 11
-#define reg_pinmux_rw_gio_pb___pb11___width 1
-#define reg_pinmux_rw_gio_pb___pb11___bit 11
-#define reg_pinmux_rw_gio_pb___pb12___lsb 12
-#define reg_pinmux_rw_gio_pb___pb12___width 1
-#define reg_pinmux_rw_gio_pb___pb12___bit 12
-#define reg_pinmux_rw_gio_pb___pb13___lsb 13
-#define reg_pinmux_rw_gio_pb___pb13___width 1
-#define reg_pinmux_rw_gio_pb___pb13___bit 13
-#define reg_pinmux_rw_gio_pb___pb14___lsb 14
-#define reg_pinmux_rw_gio_pb___pb14___width 1
-#define reg_pinmux_rw_gio_pb___pb14___bit 14
-#define reg_pinmux_rw_gio_pb___pb15___lsb 15
-#define reg_pinmux_rw_gio_pb___pb15___width 1
-#define reg_pinmux_rw_gio_pb___pb15___bit 15
-#define reg_pinmux_rw_gio_pb___pb16___lsb 16
-#define reg_pinmux_rw_gio_pb___pb16___width 1
-#define reg_pinmux_rw_gio_pb___pb16___bit 16
-#define reg_pinmux_rw_gio_pb___pb17___lsb 17
-#define reg_pinmux_rw_gio_pb___pb17___width 1
-#define reg_pinmux_rw_gio_pb___pb17___bit 17
-#define reg_pinmux_rw_gio_pb___pb18___lsb 18
-#define reg_pinmux_rw_gio_pb___pb18___width 1
-#define reg_pinmux_rw_gio_pb___pb18___bit 18
-#define reg_pinmux_rw_gio_pb___pb19___lsb 19
-#define reg_pinmux_rw_gio_pb___pb19___width 1
-#define reg_pinmux_rw_gio_pb___pb19___bit 19
-#define reg_pinmux_rw_gio_pb___pb20___lsb 20
-#define reg_pinmux_rw_gio_pb___pb20___width 1
-#define reg_pinmux_rw_gio_pb___pb20___bit 20
-#define reg_pinmux_rw_gio_pb___pb21___lsb 21
-#define reg_pinmux_rw_gio_pb___pb21___width 1
-#define reg_pinmux_rw_gio_pb___pb21___bit 21
-#define reg_pinmux_rw_gio_pb___pb22___lsb 22
-#define reg_pinmux_rw_gio_pb___pb22___width 1
-#define reg_pinmux_rw_gio_pb___pb22___bit 22
-#define reg_pinmux_rw_gio_pb___pb23___lsb 23
-#define reg_pinmux_rw_gio_pb___pb23___width 1
-#define reg_pinmux_rw_gio_pb___pb23___bit 23
-#define reg_pinmux_rw_gio_pb___pb24___lsb 24
-#define reg_pinmux_rw_gio_pb___pb24___width 1
-#define reg_pinmux_rw_gio_pb___pb24___bit 24
-#define reg_pinmux_rw_gio_pb___pb25___lsb 25
-#define reg_pinmux_rw_gio_pb___pb25___width 1
-#define reg_pinmux_rw_gio_pb___pb25___bit 25
-#define reg_pinmux_rw_gio_pb___pb26___lsb 26
-#define reg_pinmux_rw_gio_pb___pb26___width 1
-#define reg_pinmux_rw_gio_pb___pb26___bit 26
-#define reg_pinmux_rw_gio_pb___pb27___lsb 27
-#define reg_pinmux_rw_gio_pb___pb27___width 1
-#define reg_pinmux_rw_gio_pb___pb27___bit 27
-#define reg_pinmux_rw_gio_pb___pb28___lsb 28
-#define reg_pinmux_rw_gio_pb___pb28___width 1
-#define reg_pinmux_rw_gio_pb___pb28___bit 28
-#define reg_pinmux_rw_gio_pb___pb29___lsb 29
-#define reg_pinmux_rw_gio_pb___pb29___width 1
-#define reg_pinmux_rw_gio_pb___pb29___bit 29
-#define reg_pinmux_rw_gio_pb___pb30___lsb 30
-#define reg_pinmux_rw_gio_pb___pb30___width 1
-#define reg_pinmux_rw_gio_pb___pb30___bit 30
-#define reg_pinmux_rw_gio_pb___pb31___lsb 31
-#define reg_pinmux_rw_gio_pb___pb31___width 1
-#define reg_pinmux_rw_gio_pb___pb31___bit 31
-#define reg_pinmux_rw_gio_pb_offset 8
-
-/* Register rw_gio_pc, scope pinmux, type rw */
-#define reg_pinmux_rw_gio_pc___pc0___lsb 0
-#define reg_pinmux_rw_gio_pc___pc0___width 1
-#define reg_pinmux_rw_gio_pc___pc0___bit 0
-#define reg_pinmux_rw_gio_pc___pc1___lsb 1
-#define reg_pinmux_rw_gio_pc___pc1___width 1
-#define reg_pinmux_rw_gio_pc___pc1___bit 1
-#define reg_pinmux_rw_gio_pc___pc2___lsb 2
-#define reg_pinmux_rw_gio_pc___pc2___width 1
-#define reg_pinmux_rw_gio_pc___pc2___bit 2
-#define reg_pinmux_rw_gio_pc___pc3___lsb 3
-#define reg_pinmux_rw_gio_pc___pc3___width 1
-#define reg_pinmux_rw_gio_pc___pc3___bit 3
-#define reg_pinmux_rw_gio_pc___pc4___lsb 4
-#define reg_pinmux_rw_gio_pc___pc4___width 1
-#define reg_pinmux_rw_gio_pc___pc4___bit 4
-#define reg_pinmux_rw_gio_pc___pc5___lsb 5
-#define reg_pinmux_rw_gio_pc___pc5___width 1
-#define reg_pinmux_rw_gio_pc___pc5___bit 5
-#define reg_pinmux_rw_gio_pc___pc6___lsb 6
-#define reg_pinmux_rw_gio_pc___pc6___width 1
-#define reg_pinmux_rw_gio_pc___pc6___bit 6
-#define reg_pinmux_rw_gio_pc___pc7___lsb 7
-#define reg_pinmux_rw_gio_pc___pc7___width 1
-#define reg_pinmux_rw_gio_pc___pc7___bit 7
-#define reg_pinmux_rw_gio_pc___pc8___lsb 8
-#define reg_pinmux_rw_gio_pc___pc8___width 1
-#define reg_pinmux_rw_gio_pc___pc8___bit 8
-#define reg_pinmux_rw_gio_pc___pc9___lsb 9
-#define reg_pinmux_rw_gio_pc___pc9___width 1
-#define reg_pinmux_rw_gio_pc___pc9___bit 9
-#define reg_pinmux_rw_gio_pc___pc10___lsb 10
-#define reg_pinmux_rw_gio_pc___pc10___width 1
-#define reg_pinmux_rw_gio_pc___pc10___bit 10
-#define reg_pinmux_rw_gio_pc___pc11___lsb 11
-#define reg_pinmux_rw_gio_pc___pc11___width 1
-#define reg_pinmux_rw_gio_pc___pc11___bit 11
-#define reg_pinmux_rw_gio_pc___pc12___lsb 12
-#define reg_pinmux_rw_gio_pc___pc12___width 1
-#define reg_pinmux_rw_gio_pc___pc12___bit 12
-#define reg_pinmux_rw_gio_pc___pc13___lsb 13
-#define reg_pinmux_rw_gio_pc___pc13___width 1
-#define reg_pinmux_rw_gio_pc___pc13___bit 13
-#define reg_pinmux_rw_gio_pc___pc14___lsb 14
-#define reg_pinmux_rw_gio_pc___pc14___width 1
-#define reg_pinmux_rw_gio_pc___pc14___bit 14
-#define reg_pinmux_rw_gio_pc___pc15___lsb 15
-#define reg_pinmux_rw_gio_pc___pc15___width 1
-#define reg_pinmux_rw_gio_pc___pc15___bit 15
-#define reg_pinmux_rw_gio_pc_offset 12
-
-/* Register rw_iop_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pa___pa0___lsb 0
-#define reg_pinmux_rw_iop_pa___pa0___width 1
-#define reg_pinmux_rw_iop_pa___pa0___bit 0
-#define reg_pinmux_rw_iop_pa___pa1___lsb 1
-#define reg_pinmux_rw_iop_pa___pa1___width 1
-#define reg_pinmux_rw_iop_pa___pa1___bit 1
-#define reg_pinmux_rw_iop_pa___pa2___lsb 2
-#define reg_pinmux_rw_iop_pa___pa2___width 1
-#define reg_pinmux_rw_iop_pa___pa2___bit 2
-#define reg_pinmux_rw_iop_pa___pa3___lsb 3
-#define reg_pinmux_rw_iop_pa___pa3___width 1
-#define reg_pinmux_rw_iop_pa___pa3___bit 3
-#define reg_pinmux_rw_iop_pa___pa4___lsb 4
-#define reg_pinmux_rw_iop_pa___pa4___width 1
-#define reg_pinmux_rw_iop_pa___pa4___bit 4
-#define reg_pinmux_rw_iop_pa___pa5___lsb 5
-#define reg_pinmux_rw_iop_pa___pa5___width 1
-#define reg_pinmux_rw_iop_pa___pa5___bit 5
-#define reg_pinmux_rw_iop_pa___pa6___lsb 6
-#define reg_pinmux_rw_iop_pa___pa6___width 1
-#define reg_pinmux_rw_iop_pa___pa6___bit 6
-#define reg_pinmux_rw_iop_pa___pa7___lsb 7
-#define reg_pinmux_rw_iop_pa___pa7___width 1
-#define reg_pinmux_rw_iop_pa___pa7___bit 7
-#define reg_pinmux_rw_iop_pa___pa8___lsb 8
-#define reg_pinmux_rw_iop_pa___pa8___width 1
-#define reg_pinmux_rw_iop_pa___pa8___bit 8
-#define reg_pinmux_rw_iop_pa___pa9___lsb 9
-#define reg_pinmux_rw_iop_pa___pa9___width 1
-#define reg_pinmux_rw_iop_pa___pa9___bit 9
-#define reg_pinmux_rw_iop_pa___pa10___lsb 10
-#define reg_pinmux_rw_iop_pa___pa10___width 1
-#define reg_pinmux_rw_iop_pa___pa10___bit 10
-#define reg_pinmux_rw_iop_pa___pa11___lsb 11
-#define reg_pinmux_rw_iop_pa___pa11___width 1
-#define reg_pinmux_rw_iop_pa___pa11___bit 11
-#define reg_pinmux_rw_iop_pa___pa12___lsb 12
-#define reg_pinmux_rw_iop_pa___pa12___width 1
-#define reg_pinmux_rw_iop_pa___pa12___bit 12
-#define reg_pinmux_rw_iop_pa___pa13___lsb 13
-#define reg_pinmux_rw_iop_pa___pa13___width 1
-#define reg_pinmux_rw_iop_pa___pa13___bit 13
-#define reg_pinmux_rw_iop_pa___pa14___lsb 14
-#define reg_pinmux_rw_iop_pa___pa14___width 1
-#define reg_pinmux_rw_iop_pa___pa14___bit 14
-#define reg_pinmux_rw_iop_pa___pa15___lsb 15
-#define reg_pinmux_rw_iop_pa___pa15___width 1
-#define reg_pinmux_rw_iop_pa___pa15___bit 15
-#define reg_pinmux_rw_iop_pa___pa16___lsb 16
-#define reg_pinmux_rw_iop_pa___pa16___width 1
-#define reg_pinmux_rw_iop_pa___pa16___bit 16
-#define reg_pinmux_rw_iop_pa___pa17___lsb 17
-#define reg_pinmux_rw_iop_pa___pa17___width 1
-#define reg_pinmux_rw_iop_pa___pa17___bit 17
-#define reg_pinmux_rw_iop_pa___pa18___lsb 18
-#define reg_pinmux_rw_iop_pa___pa18___width 1
-#define reg_pinmux_rw_iop_pa___pa18___bit 18
-#define reg_pinmux_rw_iop_pa___pa19___lsb 19
-#define reg_pinmux_rw_iop_pa___pa19___width 1
-#define reg_pinmux_rw_iop_pa___pa19___bit 19
-#define reg_pinmux_rw_iop_pa___pa20___lsb 20
-#define reg_pinmux_rw_iop_pa___pa20___width 1
-#define reg_pinmux_rw_iop_pa___pa20___bit 20
-#define reg_pinmux_rw_iop_pa___pa21___lsb 21
-#define reg_pinmux_rw_iop_pa___pa21___width 1
-#define reg_pinmux_rw_iop_pa___pa21___bit 21
-#define reg_pinmux_rw_iop_pa___pa22___lsb 22
-#define reg_pinmux_rw_iop_pa___pa22___width 1
-#define reg_pinmux_rw_iop_pa___pa22___bit 22
-#define reg_pinmux_rw_iop_pa___pa23___lsb 23
-#define reg_pinmux_rw_iop_pa___pa23___width 1
-#define reg_pinmux_rw_iop_pa___pa23___bit 23
-#define reg_pinmux_rw_iop_pa___pa24___lsb 24
-#define reg_pinmux_rw_iop_pa___pa24___width 1
-#define reg_pinmux_rw_iop_pa___pa24___bit 24
-#define reg_pinmux_rw_iop_pa___pa25___lsb 25
-#define reg_pinmux_rw_iop_pa___pa25___width 1
-#define reg_pinmux_rw_iop_pa___pa25___bit 25
-#define reg_pinmux_rw_iop_pa___pa26___lsb 26
-#define reg_pinmux_rw_iop_pa___pa26___width 1
-#define reg_pinmux_rw_iop_pa___pa26___bit 26
-#define reg_pinmux_rw_iop_pa___pa27___lsb 27
-#define reg_pinmux_rw_iop_pa___pa27___width 1
-#define reg_pinmux_rw_iop_pa___pa27___bit 27
-#define reg_pinmux_rw_iop_pa___pa28___lsb 28
-#define reg_pinmux_rw_iop_pa___pa28___width 1
-#define reg_pinmux_rw_iop_pa___pa28___bit 28
-#define reg_pinmux_rw_iop_pa___pa29___lsb 29
-#define reg_pinmux_rw_iop_pa___pa29___width 1
-#define reg_pinmux_rw_iop_pa___pa29___bit 29
-#define reg_pinmux_rw_iop_pa___pa30___lsb 30
-#define reg_pinmux_rw_iop_pa___pa30___width 1
-#define reg_pinmux_rw_iop_pa___pa30___bit 30
-#define reg_pinmux_rw_iop_pa___pa31___lsb 31
-#define reg_pinmux_rw_iop_pa___pa31___width 1
-#define reg_pinmux_rw_iop_pa___pa31___bit 31
-#define reg_pinmux_rw_iop_pa_offset 16
-
-/* Register rw_iop_pb, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pb___pb0___lsb 0
-#define reg_pinmux_rw_iop_pb___pb0___width 1
-#define reg_pinmux_rw_iop_pb___pb0___bit 0
-#define reg_pinmux_rw_iop_pb___pb1___lsb 1
-#define reg_pinmux_rw_iop_pb___pb1___width 1
-#define reg_pinmux_rw_iop_pb___pb1___bit 1
-#define reg_pinmux_rw_iop_pb___pb2___lsb 2
-#define reg_pinmux_rw_iop_pb___pb2___width 1
-#define reg_pinmux_rw_iop_pb___pb2___bit 2
-#define reg_pinmux_rw_iop_pb___pb3___lsb 3
-#define reg_pinmux_rw_iop_pb___pb3___width 1
-#define reg_pinmux_rw_iop_pb___pb3___bit 3
-#define reg_pinmux_rw_iop_pb___pb4___lsb 4
-#define reg_pinmux_rw_iop_pb___pb4___width 1
-#define reg_pinmux_rw_iop_pb___pb4___bit 4
-#define reg_pinmux_rw_iop_pb___pb5___lsb 5
-#define reg_pinmux_rw_iop_pb___pb5___width 1
-#define reg_pinmux_rw_iop_pb___pb5___bit 5
-#define reg_pinmux_rw_iop_pb___pb6___lsb 6
-#define reg_pinmux_rw_iop_pb___pb6___width 1
-#define reg_pinmux_rw_iop_pb___pb6___bit 6
-#define reg_pinmux_rw_iop_pb___pb7___lsb 7
-#define reg_pinmux_rw_iop_pb___pb7___width 1
-#define reg_pinmux_rw_iop_pb___pb7___bit 7
-#define reg_pinmux_rw_iop_pb_offset 20
-
-/* Register rw_iop_pio, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_pio___d0___lsb 0
-#define reg_pinmux_rw_iop_pio___d0___width 1
-#define reg_pinmux_rw_iop_pio___d0___bit 0
-#define reg_pinmux_rw_iop_pio___d1___lsb 1
-#define reg_pinmux_rw_iop_pio___d1___width 1
-#define reg_pinmux_rw_iop_pio___d1___bit 1
-#define reg_pinmux_rw_iop_pio___d2___lsb 2
-#define reg_pinmux_rw_iop_pio___d2___width 1
-#define reg_pinmux_rw_iop_pio___d2___bit 2
-#define reg_pinmux_rw_iop_pio___d3___lsb 3
-#define reg_pinmux_rw_iop_pio___d3___width 1
-#define reg_pinmux_rw_iop_pio___d3___bit 3
-#define reg_pinmux_rw_iop_pio___d4___lsb 4
-#define reg_pinmux_rw_iop_pio___d4___width 1
-#define reg_pinmux_rw_iop_pio___d4___bit 4
-#define reg_pinmux_rw_iop_pio___d5___lsb 5
-#define reg_pinmux_rw_iop_pio___d5___width 1
-#define reg_pinmux_rw_iop_pio___d5___bit 5
-#define reg_pinmux_rw_iop_pio___d6___lsb 6
-#define reg_pinmux_rw_iop_pio___d6___width 1
-#define reg_pinmux_rw_iop_pio___d6___bit 6
-#define reg_pinmux_rw_iop_pio___d7___lsb 7
-#define reg_pinmux_rw_iop_pio___d7___width 1
-#define reg_pinmux_rw_iop_pio___d7___bit 7
-#define reg_pinmux_rw_iop_pio___rd_n___lsb 8
-#define reg_pinmux_rw_iop_pio___rd_n___width 1
-#define reg_pinmux_rw_iop_pio___rd_n___bit 8
-#define reg_pinmux_rw_iop_pio___wr_n___lsb 9
-#define reg_pinmux_rw_iop_pio___wr_n___width 1
-#define reg_pinmux_rw_iop_pio___wr_n___bit 9
-#define reg_pinmux_rw_iop_pio___a0___lsb 10
-#define reg_pinmux_rw_iop_pio___a0___width 1
-#define reg_pinmux_rw_iop_pio___a0___bit 10
-#define reg_pinmux_rw_iop_pio___a1___lsb 11
-#define reg_pinmux_rw_iop_pio___a1___width 1
-#define reg_pinmux_rw_iop_pio___a1___bit 11
-#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12
-#define reg_pinmux_rw_iop_pio___ce0_n___width 1
-#define reg_pinmux_rw_iop_pio___ce0_n___bit 12
-#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13
-#define reg_pinmux_rw_iop_pio___ce1_n___width 1
-#define reg_pinmux_rw_iop_pio___ce1_n___bit 13
-#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14
-#define reg_pinmux_rw_iop_pio___ce2_n___width 1
-#define reg_pinmux_rw_iop_pio___ce2_n___bit 14
-#define reg_pinmux_rw_iop_pio___rdy___lsb 15
-#define reg_pinmux_rw_iop_pio___rdy___width 1
-#define reg_pinmux_rw_iop_pio___rdy___bit 15
-#define reg_pinmux_rw_iop_pio_offset 24
-
-/* Register rw_iop_usb, scope pinmux, type rw */
-#define reg_pinmux_rw_iop_usb___usb0___lsb 0
-#define reg_pinmux_rw_iop_usb___usb0___width 1
-#define reg_pinmux_rw_iop_usb___usb0___bit 0
-#define reg_pinmux_rw_iop_usb_offset 28
-
-
-/* Constants */
-#define regk_pinmux_no 0x00000000
-#define regk_pinmux_rw_gio_pa_default 0x00000000
-#define regk_pinmux_rw_gio_pb_default 0x00000000
-#define regk_pinmux_rw_gio_pc_default 0x00000000
-#define regk_pinmux_rw_hwprot_default 0x00000000
-#define regk_pinmux_rw_iop_pa_default 0x00000000
-#define regk_pinmux_rw_iop_pb_default 0x00000000
-#define regk_pinmux_rw_iop_pio_default 0x00000000
-#define regk_pinmux_rw_iop_usb_default 0x00000001
-#define regk_pinmux_yes 0x00000001
-#endif /* __pinmux_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h
deleted file mode 100644
index 463bb9e2c38e..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/pio_defs_asm.h
+++ /dev/null
@@ -1,338 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pio_defs_asm_h
-#define __pio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: pio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_data, scope pio, type rw */
-#define reg_pio_rw_data_offset 64
-
-/* Register rw_io_access0, scope pio, type rw */
-#define reg_pio_rw_io_access0___data___lsb 0
-#define reg_pio_rw_io_access0___data___width 8
-#define reg_pio_rw_io_access0_offset 0
-
-/* Register rw_io_access1, scope pio, type rw */
-#define reg_pio_rw_io_access1___data___lsb 0
-#define reg_pio_rw_io_access1___data___width 8
-#define reg_pio_rw_io_access1_offset 4
-
-/* Register rw_io_access2, scope pio, type rw */
-#define reg_pio_rw_io_access2___data___lsb 0
-#define reg_pio_rw_io_access2___data___width 8
-#define reg_pio_rw_io_access2_offset 8
-
-/* Register rw_io_access3, scope pio, type rw */
-#define reg_pio_rw_io_access3___data___lsb 0
-#define reg_pio_rw_io_access3___data___width 8
-#define reg_pio_rw_io_access3_offset 12
-
-/* Register rw_io_access4, scope pio, type rw */
-#define reg_pio_rw_io_access4___data___lsb 0
-#define reg_pio_rw_io_access4___data___width 8
-#define reg_pio_rw_io_access4_offset 16
-
-/* Register rw_io_access5, scope pio, type rw */
-#define reg_pio_rw_io_access5___data___lsb 0
-#define reg_pio_rw_io_access5___data___width 8
-#define reg_pio_rw_io_access5_offset 20
-
-/* Register rw_io_access6, scope pio, type rw */
-#define reg_pio_rw_io_access6___data___lsb 0
-#define reg_pio_rw_io_access6___data___width 8
-#define reg_pio_rw_io_access6_offset 24
-
-/* Register rw_io_access7, scope pio, type rw */
-#define reg_pio_rw_io_access7___data___lsb 0
-#define reg_pio_rw_io_access7___data___width 8
-#define reg_pio_rw_io_access7_offset 28
-
-/* Register rw_io_access8, scope pio, type rw */
-#define reg_pio_rw_io_access8___data___lsb 0
-#define reg_pio_rw_io_access8___data___width 8
-#define reg_pio_rw_io_access8_offset 32
-
-/* Register rw_io_access9, scope pio, type rw */
-#define reg_pio_rw_io_access9___data___lsb 0
-#define reg_pio_rw_io_access9___data___width 8
-#define reg_pio_rw_io_access9_offset 36
-
-/* Register rw_io_access10, scope pio, type rw */
-#define reg_pio_rw_io_access10___data___lsb 0
-#define reg_pio_rw_io_access10___data___width 8
-#define reg_pio_rw_io_access10_offset 40
-
-/* Register rw_io_access11, scope pio, type rw */
-#define reg_pio_rw_io_access11___data___lsb 0
-#define reg_pio_rw_io_access11___data___width 8
-#define reg_pio_rw_io_access11_offset 44
-
-/* Register rw_io_access12, scope pio, type rw */
-#define reg_pio_rw_io_access12___data___lsb 0
-#define reg_pio_rw_io_access12___data___width 8
-#define reg_pio_rw_io_access12_offset 48
-
-/* Register rw_io_access13, scope pio, type rw */
-#define reg_pio_rw_io_access13___data___lsb 0
-#define reg_pio_rw_io_access13___data___width 8
-#define reg_pio_rw_io_access13_offset 52
-
-/* Register rw_io_access14, scope pio, type rw */
-#define reg_pio_rw_io_access14___data___lsb 0
-#define reg_pio_rw_io_access14___data___width 8
-#define reg_pio_rw_io_access14_offset 56
-
-/* Register rw_io_access15, scope pio, type rw */
-#define reg_pio_rw_io_access15___data___lsb 0
-#define reg_pio_rw_io_access15___data___width 8
-#define reg_pio_rw_io_access15_offset 60
-
-/* Register rw_ce0_cfg, scope pio, type rw */
-#define reg_pio_rw_ce0_cfg___lw___lsb 0
-#define reg_pio_rw_ce0_cfg___lw___width 6
-#define reg_pio_rw_ce0_cfg___ew___lsb 6
-#define reg_pio_rw_ce0_cfg___ew___width 3
-#define reg_pio_rw_ce0_cfg___zw___lsb 9
-#define reg_pio_rw_ce0_cfg___zw___width 3
-#define reg_pio_rw_ce0_cfg___aw___lsb 12
-#define reg_pio_rw_ce0_cfg___aw___width 2
-#define reg_pio_rw_ce0_cfg___mode___lsb 14
-#define reg_pio_rw_ce0_cfg___mode___width 2
-#define reg_pio_rw_ce0_cfg_offset 68
-
-/* Register rw_ce1_cfg, scope pio, type rw */
-#define reg_pio_rw_ce1_cfg___lw___lsb 0
-#define reg_pio_rw_ce1_cfg___lw___width 6
-#define reg_pio_rw_ce1_cfg___ew___lsb 6
-#define reg_pio_rw_ce1_cfg___ew___width 3
-#define reg_pio_rw_ce1_cfg___zw___lsb 9
-#define reg_pio_rw_ce1_cfg___zw___width 3
-#define reg_pio_rw_ce1_cfg___aw___lsb 12
-#define reg_pio_rw_ce1_cfg___aw___width 2
-#define reg_pio_rw_ce1_cfg___mode___lsb 14
-#define reg_pio_rw_ce1_cfg___mode___width 2
-#define reg_pio_rw_ce1_cfg_offset 72
-
-/* Register rw_ce2_cfg, scope pio, type rw */
-#define reg_pio_rw_ce2_cfg___lw___lsb 0
-#define reg_pio_rw_ce2_cfg___lw___width 6
-#define reg_pio_rw_ce2_cfg___ew___lsb 6
-#define reg_pio_rw_ce2_cfg___ew___width 3
-#define reg_pio_rw_ce2_cfg___zw___lsb 9
-#define reg_pio_rw_ce2_cfg___zw___width 3
-#define reg_pio_rw_ce2_cfg___aw___lsb 12
-#define reg_pio_rw_ce2_cfg___aw___width 2
-#define reg_pio_rw_ce2_cfg___mode___lsb 14
-#define reg_pio_rw_ce2_cfg___mode___width 2
-#define reg_pio_rw_ce2_cfg_offset 76
-
-/* Register rw_dout, scope pio, type rw */
-#define reg_pio_rw_dout___data___lsb 0
-#define reg_pio_rw_dout___data___width 8
-#define reg_pio_rw_dout___rd_n___lsb 8
-#define reg_pio_rw_dout___rd_n___width 1
-#define reg_pio_rw_dout___rd_n___bit 8
-#define reg_pio_rw_dout___wr_n___lsb 9
-#define reg_pio_rw_dout___wr_n___width 1
-#define reg_pio_rw_dout___wr_n___bit 9
-#define reg_pio_rw_dout___a0___lsb 10
-#define reg_pio_rw_dout___a0___width 1
-#define reg_pio_rw_dout___a0___bit 10
-#define reg_pio_rw_dout___a1___lsb 11
-#define reg_pio_rw_dout___a1___width 1
-#define reg_pio_rw_dout___a1___bit 11
-#define reg_pio_rw_dout___ce0_n___lsb 12
-#define reg_pio_rw_dout___ce0_n___width 1
-#define reg_pio_rw_dout___ce0_n___bit 12
-#define reg_pio_rw_dout___ce1_n___lsb 13
-#define reg_pio_rw_dout___ce1_n___width 1
-#define reg_pio_rw_dout___ce1_n___bit 13
-#define reg_pio_rw_dout___ce2_n___lsb 14
-#define reg_pio_rw_dout___ce2_n___width 1
-#define reg_pio_rw_dout___ce2_n___bit 14
-#define reg_pio_rw_dout___rdy___lsb 15
-#define reg_pio_rw_dout___rdy___width 1
-#define reg_pio_rw_dout___rdy___bit 15
-#define reg_pio_rw_dout_offset 80
-
-/* Register rw_oe, scope pio, type rw */
-#define reg_pio_rw_oe___data___lsb 0
-#define reg_pio_rw_oe___data___width 8
-#define reg_pio_rw_oe___rd_n___lsb 8
-#define reg_pio_rw_oe___rd_n___width 1
-#define reg_pio_rw_oe___rd_n___bit 8
-#define reg_pio_rw_oe___wr_n___lsb 9
-#define reg_pio_rw_oe___wr_n___width 1
-#define reg_pio_rw_oe___wr_n___bit 9
-#define reg_pio_rw_oe___a0___lsb 10
-#define reg_pio_rw_oe___a0___width 1
-#define reg_pio_rw_oe___a0___bit 10
-#define reg_pio_rw_oe___a1___lsb 11
-#define reg_pio_rw_oe___a1___width 1
-#define reg_pio_rw_oe___a1___bit 11
-#define reg_pio_rw_oe___ce0_n___lsb 12
-#define reg_pio_rw_oe___ce0_n___width 1
-#define reg_pio_rw_oe___ce0_n___bit 12
-#define reg_pio_rw_oe___ce1_n___lsb 13
-#define reg_pio_rw_oe___ce1_n___width 1
-#define reg_pio_rw_oe___ce1_n___bit 13
-#define reg_pio_rw_oe___ce2_n___lsb 14
-#define reg_pio_rw_oe___ce2_n___width 1
-#define reg_pio_rw_oe___ce2_n___bit 14
-#define reg_pio_rw_oe___rdy___lsb 15
-#define reg_pio_rw_oe___rdy___width 1
-#define reg_pio_rw_oe___rdy___bit 15
-#define reg_pio_rw_oe_offset 84
-
-/* Register rw_man_ctrl, scope pio, type rw */
-#define reg_pio_rw_man_ctrl___data___lsb 0
-#define reg_pio_rw_man_ctrl___data___width 8
-#define reg_pio_rw_man_ctrl___rd_n___lsb 8
-#define reg_pio_rw_man_ctrl___rd_n___width 1
-#define reg_pio_rw_man_ctrl___rd_n___bit 8
-#define reg_pio_rw_man_ctrl___wr_n___lsb 9
-#define reg_pio_rw_man_ctrl___wr_n___width 1
-#define reg_pio_rw_man_ctrl___wr_n___bit 9
-#define reg_pio_rw_man_ctrl___a0___lsb 10
-#define reg_pio_rw_man_ctrl___a0___width 1
-#define reg_pio_rw_man_ctrl___a0___bit 10
-#define reg_pio_rw_man_ctrl___a1___lsb 11
-#define reg_pio_rw_man_ctrl___a1___width 1
-#define reg_pio_rw_man_ctrl___a1___bit 11
-#define reg_pio_rw_man_ctrl___ce0_n___lsb 12
-#define reg_pio_rw_man_ctrl___ce0_n___width 1
-#define reg_pio_rw_man_ctrl___ce0_n___bit 12
-#define reg_pio_rw_man_ctrl___ce1_n___lsb 13
-#define reg_pio_rw_man_ctrl___ce1_n___width 1
-#define reg_pio_rw_man_ctrl___ce1_n___bit 13
-#define reg_pio_rw_man_ctrl___ce2_n___lsb 14
-#define reg_pio_rw_man_ctrl___ce2_n___width 1
-#define reg_pio_rw_man_ctrl___ce2_n___bit 14
-#define reg_pio_rw_man_ctrl___rdy___lsb 15
-#define reg_pio_rw_man_ctrl___rdy___width 1
-#define reg_pio_rw_man_ctrl___rdy___bit 15
-#define reg_pio_rw_man_ctrl_offset 88
-
-/* Register r_din, scope pio, type r */
-#define reg_pio_r_din___data___lsb 0
-#define reg_pio_r_din___data___width 8
-#define reg_pio_r_din___rd_n___lsb 8
-#define reg_pio_r_din___rd_n___width 1
-#define reg_pio_r_din___rd_n___bit 8
-#define reg_pio_r_din___wr_n___lsb 9
-#define reg_pio_r_din___wr_n___width 1
-#define reg_pio_r_din___wr_n___bit 9
-#define reg_pio_r_din___a0___lsb 10
-#define reg_pio_r_din___a0___width 1
-#define reg_pio_r_din___a0___bit 10
-#define reg_pio_r_din___a1___lsb 11
-#define reg_pio_r_din___a1___width 1
-#define reg_pio_r_din___a1___bit 11
-#define reg_pio_r_din___ce0_n___lsb 12
-#define reg_pio_r_din___ce0_n___width 1
-#define reg_pio_r_din___ce0_n___bit 12
-#define reg_pio_r_din___ce1_n___lsb 13
-#define reg_pio_r_din___ce1_n___width 1
-#define reg_pio_r_din___ce1_n___bit 13
-#define reg_pio_r_din___ce2_n___lsb 14
-#define reg_pio_r_din___ce2_n___width 1
-#define reg_pio_r_din___ce2_n___bit 14
-#define reg_pio_r_din___rdy___lsb 15
-#define reg_pio_r_din___rdy___width 1
-#define reg_pio_r_din___rdy___bit 15
-#define reg_pio_r_din_offset 92
-
-/* Register r_stat, scope pio, type r */
-#define reg_pio_r_stat___busy___lsb 0
-#define reg_pio_r_stat___busy___width 1
-#define reg_pio_r_stat___busy___bit 0
-#define reg_pio_r_stat_offset 96
-
-/* Register rw_intr_mask, scope pio, type rw */
-#define reg_pio_rw_intr_mask___rdy___lsb 0
-#define reg_pio_rw_intr_mask___rdy___width 1
-#define reg_pio_rw_intr_mask___rdy___bit 0
-#define reg_pio_rw_intr_mask_offset 100
-
-/* Register rw_ack_intr, scope pio, type rw */
-#define reg_pio_rw_ack_intr___rdy___lsb 0
-#define reg_pio_rw_ack_intr___rdy___width 1
-#define reg_pio_rw_ack_intr___rdy___bit 0
-#define reg_pio_rw_ack_intr_offset 104
-
-/* Register r_intr, scope pio, type r */
-#define reg_pio_r_intr___rdy___lsb 0
-#define reg_pio_r_intr___rdy___width 1
-#define reg_pio_r_intr___rdy___bit 0
-#define reg_pio_r_intr_offset 108
-
-/* Register r_masked_intr, scope pio, type r */
-#define reg_pio_r_masked_intr___rdy___lsb 0
-#define reg_pio_r_masked_intr___rdy___width 1
-#define reg_pio_r_masked_intr___rdy___bit 0
-#define reg_pio_r_masked_intr_offset 112
-
-
-/* Constants */
-#define regk_pio_a2 0x00000003
-#define regk_pio_no 0x00000000
-#define regk_pio_normal 0x00000000
-#define regk_pio_rd 0x00000001
-#define regk_pio_rw_ce0_cfg_default 0x00000000
-#define regk_pio_rw_ce1_cfg_default 0x00000000
-#define regk_pio_rw_ce2_cfg_default 0x00000000
-#define regk_pio_rw_intr_mask_default 0x00000000
-#define regk_pio_rw_man_ctrl_default 0x00000000
-#define regk_pio_rw_oe_default 0x00000000
-#define regk_pio_wr 0x00000002
-#define regk_pio_wr_ce2 0x00000003
-#define regk_pio_yes 0x00000001
-#define regk_pio_yes_all 0x000000ff
-#endif /* __pio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h
deleted file mode 100644
index e3bf8e0692a6..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/reg_map_asm.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_asm_h
-#define __reg_map_asm_h
-
-/*
- * This file is autogenerated from
- * file: reg.rmap
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-#define regi_ccd 0xb0000000
-#define regi_ccd_top 0xb0000000
-#define regi_ccd_dp 0xb0000400
-#define regi_ccd_stat 0xb0000800
-#define regi_ccd_tg 0xb0001000
-#define regi_cfg 0xb0002000
-#define regi_clkgen 0xb0004000
-#define regi_ddr2_ctrl 0xb0006000
-#define regi_dma0 0xb0008000
-#define regi_dma1 0xb000a000
-#define regi_dma11 0xb000c000
-#define regi_dma2 0xb000e000
-#define regi_dma3 0xb0010000
-#define regi_dma4 0xb0012000
-#define regi_dma5 0xb0014000
-#define regi_dma6 0xb0016000
-#define regi_dma7 0xb0018000
-#define regi_dma9 0xb001a000
-#define regi_eth 0xb001c000
-#define regi_gio 0xb0020000
-#define regi_h264 0xb0022000
-#define regi_hist 0xb0026000
-#define regi_iop 0xb0028000
-#define regi_iop_version 0xb0028000
-#define regi_iop_fifo_in_extra 0xb0028040
-#define regi_iop_fifo_out_extra 0xb0028080
-#define regi_iop_trigger_grp0 0xb00280c0
-#define regi_iop_trigger_grp1 0xb0028100
-#define regi_iop_trigger_grp2 0xb0028140
-#define regi_iop_trigger_grp3 0xb0028180
-#define regi_iop_trigger_grp4 0xb00281c0
-#define regi_iop_trigger_grp5 0xb0028200
-#define regi_iop_trigger_grp6 0xb0028240
-#define regi_iop_trigger_grp7 0xb0028280
-#define regi_iop_crc_par 0xb0028300
-#define regi_iop_dmc_in 0xb0028380
-#define regi_iop_dmc_out 0xb0028400
-#define regi_iop_fifo_in 0xb0028480
-#define regi_iop_fifo_out 0xb0028500
-#define regi_iop_scrc_in 0xb0028580
-#define regi_iop_scrc_out 0xb0028600
-#define regi_iop_timer_grp0 0xb0028680
-#define regi_iop_timer_grp1 0xb0028700
-#define regi_iop_sap_in 0xb0028800
-#define regi_iop_sap_out 0xb0028900
-#define regi_iop_spu 0xb0028a00
-#define regi_iop_sw_cfg 0xb0028b00
-#define regi_iop_sw_cpu 0xb0028c00
-#define regi_iop_sw_mpu 0xb0028d00
-#define regi_iop_sw_spu 0xb0028e00
-#define regi_iop_mpu 0xb0029000
-#define regi_irq 0xb002a000
-#define regi_jpeg 0xb002c000
-#define regi_l2cache 0xb0030000
-#define regi_marb_bar 0xb0032000
-#define regi_marb_bar_bp0 0xb0032140
-#define regi_marb_bar_bp1 0xb0032180
-#define regi_marb_bar_bp2 0xb00321c0
-#define regi_marb_bar_bp3 0xb0032200
-#define regi_marb_foo 0xb0034000
-#define regi_marb_foo_bp0 0xb0034280
-#define regi_marb_foo_bp1 0xb00342c0
-#define regi_marb_foo_bp2 0xb0034300
-#define regi_marb_foo_bp3 0xb0034340
-#define regi_pinmux 0xb0038000
-#define regi_pio 0xb0036000
-#define regi_sclr 0xb003a000
-#define regi_sclr_fifo 0xb003c000
-#define regi_ser0 0xb003e000
-#define regi_ser1 0xb0040000
-#define regi_ser2 0xb0042000
-#define regi_ser3 0xb0044000
-#define regi_ser4 0xb0046000
-#define regi_sser 0xb0048000
-#define regi_strcop 0xb004a000
-#define regi_strdma0 0xb004e000
-#define regi_strdma1 0xb0050000
-#define regi_strdma2 0xb0052000
-#define regi_strdma3 0xb0054000
-#define regi_strdma5 0xb0056000
-#define regi_strmux 0xb004c000
-#define regi_timer0 0xb0058000
-#define regi_timer1 0xb005a000
-#define regi_trace 0xb005c000
-#define regi_vin 0xb005e000
-#define regi_vout 0xb0060000
-#endif /* __reg_map_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index 82da59c382c2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: timer.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext 0x00000001
-#define regk_timer_f100 0x00000007
-#define regk_timer_f29_493 0x00000004
-#define regk_timer_f32 0x00000005
-#define regk_timer_f32_768 0x00000006
-#define regk_timer_f90 0x00000003
-#define regk_timer_hold 0x00000001
-#define regk_timer_ld 0x00000000
-#define regk_timer_no 0x00000000
-#define regk_timer_off 0x00000000
-#define regk_timer_run 0x00000002
-#define regk_timer_rw_cnt_cfg_default 0x00000000
-#define regk_timer_rw_intr_mask_default 0x00000000
-#define regk_timer_rw_out_default 0x00000000
-#define regk_timer_rw_test_default 0x00000000
-#define regk_timer_rw_tmr0_ctrl_default 0x00000000
-#define regk_timer_rw_tmr1_ctrl_default 0x00000000
-#define regk_timer_rw_trig_cfg_default 0x00000000
-#define regk_timer_start 0x00000001
-#define regk_timer_stop 0x00000000
-#define regk_timer_time 0x00000001
-#define regk_timer_tmr0 0x00000002
-#define regk_timer_tmr1 0x00000003
-#define regk_timer_vclk 0x00000002
-#define regk_timer_yes 0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h
deleted file mode 100644
index 32d58fed3b03..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/clkgen_defs.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __clkgen_defs_h
-#define __clkgen_defs_h
-
-/*
- * This file is autogenerated from
- * file: clkgen.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope clkgen */
-
-/* Register r_bootsel, scope clkgen, type r */
-typedef struct {
- unsigned int boot_mode : 5;
- unsigned int intern_main_clk : 1;
- unsigned int extern_usb2_clk : 1;
- unsigned int dummy1 : 25;
-} reg_clkgen_r_bootsel;
-#define REG_RD_ADDR_clkgen_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope clkgen, type rw */
-typedef struct {
- unsigned int pll : 1;
- unsigned int cpu : 1;
- unsigned int iop_usb : 1;
- unsigned int vin : 1;
- unsigned int sclr : 1;
- unsigned int h264 : 1;
- unsigned int ddr2 : 1;
- unsigned int vout_hist : 1;
- unsigned int eth : 1;
- unsigned int ccd_tg_200 : 1;
- unsigned int dma0_1_eth : 1;
- unsigned int ccd_tg_100 : 1;
- unsigned int jpeg : 1;
- unsigned int sser_ser_dma6_7 : 1;
- unsigned int strdma0_2_video : 1;
- unsigned int dma2_3_strcop : 1;
- unsigned int dma4_5_iop : 1;
- unsigned int dma9_11 : 1;
- unsigned int memarb_bar_ddr : 1;
- unsigned int sclr_h264 : 1;
- unsigned int dummy1 : 12;
-} reg_clkgen_rw_clk_ctrl;
-#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
-#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
-
-
-/* Constants */
-enum {
- regk_clkgen_eth1000_rx = 0x0000000c,
- regk_clkgen_eth1000_tx = 0x0000000e,
- regk_clkgen_eth100_rx = 0x0000001d,
- regk_clkgen_eth100_rx_half = 0x0000001c,
- regk_clkgen_eth100_tx = 0x0000001f,
- regk_clkgen_eth100_tx_half = 0x0000001e,
- regk_clkgen_nand_3_2 = 0x00000000,
- regk_clkgen_nand_3_2_0x30 = 0x00000002,
- regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
- regk_clkgen_nand_3_2_pll = 0x00000010,
- regk_clkgen_nand_3_3 = 0x00000001,
- regk_clkgen_nand_3_3_0x30 = 0x00000003,
- regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
- regk_clkgen_nand_3_3_pll = 0x00000011,
- regk_clkgen_nand_4_2 = 0x00000004,
- regk_clkgen_nand_4_2_0x30 = 0x00000006,
- regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
- regk_clkgen_nand_4_2_pll = 0x00000014,
- regk_clkgen_nand_4_3 = 0x00000005,
- regk_clkgen_nand_4_3_0x30 = 0x00000007,
- regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
- regk_clkgen_nand_4_3_pll = 0x00000015,
- regk_clkgen_nand_5_2 = 0x00000008,
- regk_clkgen_nand_5_2_0x30 = 0x0000000a,
- regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
- regk_clkgen_nand_5_2_pll = 0x00000018,
- regk_clkgen_nand_5_3 = 0x00000009,
- regk_clkgen_nand_5_3_0x30 = 0x0000000b,
- regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
- regk_clkgen_nand_5_3_pll = 0x00000019,
- regk_clkgen_no = 0x00000000,
- regk_clkgen_rw_clk_ctrl_default = 0x00000002,
- regk_clkgen_ser = 0x0000000d,
- regk_clkgen_ser_pll = 0x0000000f,
- regk_clkgen_yes = 0x00000001
-};
-#endif /* __clkgen_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h
deleted file mode 100644
index 84684c335d7d..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ddr2_defs.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ddr2_defs_h
-#define __ddr2_defs_h
-
-/*
- * This file is autogenerated from
- * file: ddr2.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope ddr2 */
-
-/* Register rw_cfg, scope ddr2, type rw */
-typedef struct {
- unsigned int col_width : 4;
- unsigned int nr_banks : 1;
- unsigned int bw : 1;
- unsigned int nr_ref : 4;
- unsigned int ref_interval : 11;
- unsigned int odt_ctrl : 2;
- unsigned int odt_mem : 1;
- unsigned int imp_strength : 1;
- unsigned int auto_imp_cal : 1;
- unsigned int imp_cal_override : 1;
- unsigned int dll_override : 1;
- unsigned int dummy1 : 4;
-} reg_ddr2_rw_cfg;
-#define REG_RD_ADDR_ddr2_rw_cfg 0
-#define REG_WR_ADDR_ddr2_rw_cfg 0
-
-/* Register rw_timing, scope ddr2, type rw */
-typedef struct {
- unsigned int wr : 3;
- unsigned int rcd : 3;
- unsigned int rp : 3;
- unsigned int ras : 4;
- unsigned int rfc : 7;
- unsigned int rc : 5;
- unsigned int rtp : 2;
- unsigned int rtw : 3;
- unsigned int wtr : 2;
-} reg_ddr2_rw_timing;
-#define REG_RD_ADDR_ddr2_rw_timing 4
-#define REG_WR_ADDR_ddr2_rw_timing 4
-
-/* Register rw_latency, scope ddr2, type rw */
-typedef struct {
- unsigned int cas : 3;
- unsigned int additive : 3;
- unsigned int dummy1 : 26;
-} reg_ddr2_rw_latency;
-#define REG_RD_ADDR_ddr2_rw_latency 8
-#define REG_WR_ADDR_ddr2_rw_latency 8
-
-/* Register rw_phy_cfg, scope ddr2, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_ddr2_rw_phy_cfg;
-#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
-#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
-
-/* Register rw_phy_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int rst : 1;
- unsigned int cal_rst : 1;
- unsigned int cal_start : 1;
- unsigned int dummy1 : 29;
-} reg_ddr2_rw_phy_ctrl;
-#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
-#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
-
-/* Register rw_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int mrs_data : 16;
- unsigned int cmd : 8;
- unsigned int dummy1 : 8;
-} reg_ddr2_rw_ctrl;
-#define REG_RD_ADDR_ddr2_rw_ctrl 20
-#define REG_WR_ADDR_ddr2_rw_ctrl 20
-
-/* Register rw_pwr_down, scope ddr2, type rw */
-typedef struct {
- unsigned int self_ref : 2;
- unsigned int phy_en : 1;
- unsigned int dummy1 : 29;
-} reg_ddr2_rw_pwr_down;
-#define REG_RD_ADDR_ddr2_rw_pwr_down 24
-#define REG_WR_ADDR_ddr2_rw_pwr_down 24
-
-/* Register r_stat, scope ddr2, type r */
-typedef struct {
- unsigned int dll_lock : 1;
- unsigned int dll_delay_code : 7;
- unsigned int imp_cal_done : 1;
- unsigned int imp_cal_fault : 1;
- unsigned int cal_imp_pu : 4;
- unsigned int cal_imp_pd : 4;
- unsigned int dummy1 : 14;
-} reg_ddr2_r_stat;
-#define REG_RD_ADDR_ddr2_r_stat 28
-
-/* Register rw_imp_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int imp_pu : 4;
- unsigned int imp_pd : 4;
- unsigned int dummy1 : 24;
-} reg_ddr2_rw_imp_ctrl;
-#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
-#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
-
-#define STRIDE_ddr2_rw_dll_ctrl 4
-/* Register rw_dll_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int mode : 1;
- unsigned int clk_delay : 7;
- unsigned int dummy1 : 24;
-} reg_ddr2_rw_dll_ctrl;
-#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
-#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
-
-#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
-/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
-typedef struct {
- unsigned int dqs90_delay : 7;
- unsigned int dqs180_delay : 7;
- unsigned int dqs270_delay : 7;
- unsigned int dqs360_delay : 7;
- unsigned int dummy1 : 4;
-} reg_ddr2_rw_dqs_dll_ctrl;
-#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
-#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
-
-
-/* Constants */
-enum {
- regk_ddr2_al0 = 0x00000000,
- regk_ddr2_al1 = 0x00000008,
- regk_ddr2_al2 = 0x00000010,
- regk_ddr2_al3 = 0x00000018,
- regk_ddr2_al4 = 0x00000020,
- regk_ddr2_auto = 0x00000003,
- regk_ddr2_bank4 = 0x00000000,
- regk_ddr2_bank8 = 0x00000001,
- regk_ddr2_bl4 = 0x00000002,
- regk_ddr2_bl8 = 0x00000003,
- regk_ddr2_bt_il = 0x00000008,
- regk_ddr2_bt_seq = 0x00000000,
- regk_ddr2_bw16 = 0x00000001,
- regk_ddr2_bw32 = 0x00000000,
- regk_ddr2_cas2 = 0x00000020,
- regk_ddr2_cas3 = 0x00000030,
- regk_ddr2_cas4 = 0x00000040,
- regk_ddr2_cas5 = 0x00000050,
- regk_ddr2_deselect = 0x000000c0,
- regk_ddr2_dic_weak = 0x00000002,
- regk_ddr2_direct = 0x00000001,
- regk_ddr2_dis = 0x00000000,
- regk_ddr2_dll_dis = 0x00000001,
- regk_ddr2_dll_en = 0x00000000,
- regk_ddr2_dll_rst = 0x00000100,
- regk_ddr2_emrs = 0x00000081,
- regk_ddr2_emrs2 = 0x00000082,
- regk_ddr2_emrs3 = 0x00000083,
- regk_ddr2_full = 0x00000001,
- regk_ddr2_hi_ref_rate = 0x00000080,
- regk_ddr2_mrs = 0x00000080,
- regk_ddr2_no = 0x00000000,
- regk_ddr2_nop = 0x000000b8,
- regk_ddr2_ocd_adj = 0x00000200,
- regk_ddr2_ocd_default = 0x00000380,
- regk_ddr2_ocd_drive0 = 0x00000100,
- regk_ddr2_ocd_drive1 = 0x00000080,
- regk_ddr2_ocd_exit = 0x00000000,
- regk_ddr2_odt_dis = 0x00000000,
- regk_ddr2_offs = 0x00000000,
- regk_ddr2_pre = 0x00000090,
- regk_ddr2_pre_all = 0x00000400,
- regk_ddr2_pwr_down_fast = 0x00000000,
- regk_ddr2_pwr_down_slow = 0x00001000,
- regk_ddr2_ref = 0x00000088,
- regk_ddr2_rtt150 = 0x00000040,
- regk_ddr2_rtt50 = 0x00000044,
- regk_ddr2_rtt75 = 0x00000004,
- regk_ddr2_rw_cfg_default = 0x00186000,
- regk_ddr2_rw_dll_ctrl_default = 0x00000000,
- regk_ddr2_rw_dll_ctrl_size = 0x00000004,
- regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
- regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
- regk_ddr2_rw_latency_default = 0x00000000,
- regk_ddr2_rw_phy_cfg_default = 0x00000000,
- regk_ddr2_rw_pwr_down_default = 0x00000000,
- regk_ddr2_rw_timing_default = 0x00000000,
- regk_ddr2_s1Gb = 0x0000001a,
- regk_ddr2_s256Mb = 0x0000000f,
- regk_ddr2_s2Gb = 0x00000027,
- regk_ddr2_s4Gb = 0x00000042,
- regk_ddr2_s512Mb = 0x00000015,
- regk_ddr2_temp0_85 = 0x00000618,
- regk_ddr2_temp85_95 = 0x0000030c,
- regk_ddr2_term150 = 0x00000002,
- regk_ddr2_term50 = 0x00000003,
- regk_ddr2_term75 = 0x00000001,
- regk_ddr2_test = 0x00000080,
- regk_ddr2_weak = 0x00000000,
- regk_ddr2_wr2 = 0x00000200,
- regk_ddr2_wr3 = 0x00000400,
- regk_ddr2_yes = 0x00000001
-};
-#endif /* __ddr2_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h
deleted file mode 100644
index 83ab1f495612..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h
+++ /dev/null
@@ -1,838 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_h
-#define __gio_defs_h
-
-/*
- * This file is autogenerated from
- * file: gio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope gio */
-
-/* Register r_pa_din, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pa_din;
-#define REG_RD_ADDR_gio_r_pa_din 0
-
-/* Register rw_pa_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_rw_pa_dout;
-#define REG_RD_ADDR_gio_rw_pa_dout 4
-#define REG_WR_ADDR_gio_rw_pa_dout 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 32;
-} reg_gio_rw_pa_oe;
-#define REG_RD_ADDR_gio_rw_pa_oe 8
-#define REG_WR_ADDR_gio_rw_pa_oe 8
-
-/* Register rw_pa_byte0_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
-#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12
-
-/* Register rw_pa_byte0_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
-#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16
-
-/* Register rw_pa_byte1_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
-#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20
-
-/* Register rw_pa_byte1_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
-#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24
-
-/* Register rw_pa_byte2_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte2_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
-#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28
-
-/* Register rw_pa_byte2_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte2_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
-#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32
-
-/* Register rw_pa_byte3_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte3_dout;
-#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
-#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36
-
-/* Register rw_pa_byte3_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_byte3_oe;
-#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
-#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40
-
-/* Register r_pb_din, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pb_din;
-#define REG_RD_ADDR_gio_r_pb_din 44
-
-/* Register rw_pb_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_rw_pb_dout;
-#define REG_RD_ADDR_gio_rw_pb_dout 48
-#define REG_WR_ADDR_gio_rw_pb_dout 48
-
-/* Register rw_pb_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 32;
-} reg_gio_rw_pb_oe;
-#define REG_RD_ADDR_gio_rw_pb_oe 52
-#define REG_WR_ADDR_gio_rw_pb_oe 52
-
-/* Register rw_pb_byte0_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
-#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56
-
-/* Register rw_pb_byte0_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
-#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60
-
-/* Register rw_pb_byte1_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
-#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64
-
-/* Register rw_pb_byte1_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
-#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68
-
-/* Register rw_pb_byte2_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte2_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
-#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72
-
-/* Register rw_pb_byte2_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte2_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
-#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76
-
-/* Register rw_pb_byte3_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte3_dout;
-#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
-#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80
-
-/* Register rw_pb_byte3_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pb_byte3_oe;
-#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
-#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84
-
-/* Register r_pc_din, scope gio, type r */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_gio_r_pc_din;
-#define REG_RD_ADDR_gio_r_pc_din 88
-
-/* Register rw_pc_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 16;
- unsigned int dummy1 : 16;
-} reg_gio_rw_pc_dout;
-#define REG_RD_ADDR_gio_rw_pc_dout 92
-#define REG_WR_ADDR_gio_rw_pc_dout 92
-
-/* Register rw_pc_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 16;
- unsigned int dummy1 : 16;
-} reg_gio_rw_pc_oe;
-#define REG_RD_ADDR_gio_rw_pc_oe 96
-#define REG_WR_ADDR_gio_rw_pc_oe 96
-
-/* Register rw_pc_byte0_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte0_dout;
-#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
-#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100
-
-/* Register rw_pc_byte0_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte0_oe;
-#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
-#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104
-
-/* Register rw_pc_byte1_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte1_dout;
-#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
-#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108
-
-/* Register rw_pc_byte1_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pc_byte1_oe;
-#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
-#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112
-
-/* Register r_pd_din, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pd_din;
-#define REG_RD_ADDR_gio_r_pd_din 116
-
-/* Register rw_intr_cfg, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 3;
- unsigned int intr1 : 3;
- unsigned int intr2 : 3;
- unsigned int intr3 : 3;
- unsigned int intr4 : 3;
- unsigned int intr5 : 3;
- unsigned int intr6 : 3;
- unsigned int intr7 : 3;
- unsigned int dummy1 : 8;
-} reg_gio_rw_intr_cfg;
-#define REG_RD_ADDR_gio_rw_intr_cfg 120
-#define REG_WR_ADDR_gio_rw_intr_cfg 120
-
-/* Register rw_intr_pins, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 4;
- unsigned int intr1 : 4;
- unsigned int intr2 : 4;
- unsigned int intr3 : 4;
- unsigned int intr4 : 4;
- unsigned int intr5 : 4;
- unsigned int intr6 : 4;
- unsigned int intr7 : 4;
-} reg_gio_rw_intr_pins;
-#define REG_RD_ADDR_gio_rw_intr_pins 124
-#define REG_WR_ADDR_gio_rw_intr_pins 124
-
-/* Register rw_intr_mask, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_rw_intr_mask;
-#define REG_RD_ADDR_gio_rw_intr_mask 128
-#define REG_WR_ADDR_gio_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope gio, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_rw_ack_intr;
-#define REG_RD_ADDR_gio_rw_ack_intr 132
-#define REG_WR_ADDR_gio_rw_ack_intr 132
-
-/* Register r_intr, scope gio, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_r_intr;
-#define REG_RD_ADDR_gio_r_intr 136
-
-/* Register r_masked_intr, scope gio, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int i2c0_done : 1;
- unsigned int i2c1_done : 1;
- unsigned int dummy1 : 22;
-} reg_gio_r_masked_intr;
-#define REG_RD_ADDR_gio_r_masked_intr 140
-
-/* Register rw_i2c0_start, scope gio, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_gio_rw_i2c0_start;
-#define REG_RD_ADDR_gio_rw_i2c0_start 144
-#define REG_WR_ADDR_gio_rw_i2c0_start 144
-
-/* Register rw_i2c0_cfg, scope gio, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int bit_order : 1;
- unsigned int scl_io : 1;
- unsigned int scl_inv : 1;
- unsigned int sda_io : 1;
- unsigned int sda_idle : 1;
- unsigned int dummy1 : 26;
-} reg_gio_rw_i2c0_cfg;
-#define REG_RD_ADDR_gio_rw_i2c0_cfg 148
-#define REG_WR_ADDR_gio_rw_i2c0_cfg 148
-
-/* Register rw_i2c0_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int trf_bits : 6;
- unsigned int switch_dir : 6;
- unsigned int extra_start : 3;
- unsigned int early_end : 1;
- unsigned int start_stop : 1;
- unsigned int ack_dir0 : 1;
- unsigned int ack_dir1 : 1;
- unsigned int ack_dir2 : 1;
- unsigned int ack_dir3 : 1;
- unsigned int ack_dir4 : 1;
- unsigned int ack_dir5 : 1;
- unsigned int ack_bit : 1;
- unsigned int start_bit : 1;
- unsigned int freq : 2;
- unsigned int dummy1 : 5;
-} reg_gio_rw_i2c0_ctrl;
-#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
-#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152
-
-/* Register rw_i2c0_data, scope gio, type rw */
-typedef struct {
- unsigned int data0 : 8;
- unsigned int data1 : 8;
- unsigned int data2 : 8;
- unsigned int data3 : 8;
-} reg_gio_rw_i2c0_data;
-#define REG_RD_ADDR_gio_rw_i2c0_data 156
-#define REG_WR_ADDR_gio_rw_i2c0_data 156
-
-/* Register rw_i2c0_data2, scope gio, type rw */
-typedef struct {
- unsigned int data4 : 8;
- unsigned int data5 : 8;
- unsigned int start_val : 6;
- unsigned int ack_val : 6;
- unsigned int dummy1 : 4;
-} reg_gio_rw_i2c0_data2;
-#define REG_RD_ADDR_gio_rw_i2c0_data2 160
-#define REG_WR_ADDR_gio_rw_i2c0_data2 160
-
-/* Register rw_i2c1_start, scope gio, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_gio_rw_i2c1_start;
-#define REG_RD_ADDR_gio_rw_i2c1_start 164
-#define REG_WR_ADDR_gio_rw_i2c1_start 164
-
-/* Register rw_i2c1_cfg, scope gio, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int bit_order : 1;
- unsigned int scl_io : 1;
- unsigned int scl_inv : 1;
- unsigned int sda0_io : 1;
- unsigned int sda0_idle : 1;
- unsigned int sda1_io : 1;
- unsigned int sda1_idle : 1;
- unsigned int sda2_io : 1;
- unsigned int sda2_idle : 1;
- unsigned int sda3_io : 1;
- unsigned int sda3_idle : 1;
- unsigned int sda_sel : 2;
- unsigned int sen_idle : 1;
- unsigned int sen_inv : 1;
- unsigned int sen_sel : 2;
- unsigned int dummy1 : 14;
-} reg_gio_rw_i2c1_cfg;
-#define REG_RD_ADDR_gio_rw_i2c1_cfg 168
-#define REG_WR_ADDR_gio_rw_i2c1_cfg 168
-
-/* Register rw_i2c1_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int trf_bits : 6;
- unsigned int switch_dir : 6;
- unsigned int extra_start : 3;
- unsigned int early_end : 1;
- unsigned int start_stop : 1;
- unsigned int ack_dir0 : 1;
- unsigned int ack_dir1 : 1;
- unsigned int ack_dir2 : 1;
- unsigned int ack_dir3 : 1;
- unsigned int ack_dir4 : 1;
- unsigned int ack_dir5 : 1;
- unsigned int ack_bit : 1;
- unsigned int start_bit : 1;
- unsigned int freq : 2;
- unsigned int dummy1 : 5;
-} reg_gio_rw_i2c1_ctrl;
-#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
-#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172
-
-/* Register rw_i2c1_data, scope gio, type rw */
-typedef struct {
- unsigned int data0 : 8;
- unsigned int data1 : 8;
- unsigned int data2 : 8;
- unsigned int data3 : 8;
-} reg_gio_rw_i2c1_data;
-#define REG_RD_ADDR_gio_rw_i2c1_data 176
-#define REG_WR_ADDR_gio_rw_i2c1_data 176
-
-/* Register rw_i2c1_data2, scope gio, type rw */
-typedef struct {
- unsigned int data4 : 8;
- unsigned int data5 : 8;
- unsigned int start_val : 6;
- unsigned int ack_val : 6;
- unsigned int dummy1 : 4;
-} reg_gio_rw_i2c1_data2;
-#define REG_RD_ADDR_gio_rw_i2c1_data2 180
-#define REG_WR_ADDR_gio_rw_i2c1_data2 180
-
-/* Register r_ppwm_stat, scope gio, type r */
-typedef struct {
- unsigned int freq : 2;
- unsigned int dummy1 : 30;
-} reg_gio_r_ppwm_stat;
-#define REG_RD_ADDR_gio_r_ppwm_stat 184
-
-/* Register rw_ppwm_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_ppwm_data;
-#define REG_RD_ADDR_gio_rw_ppwm_data 188
-#define REG_WR_ADDR_gio_rw_ppwm_data 188
-
-/* Register rw_pwm0_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int mode : 2;
- unsigned int ccd_override : 1;
- unsigned int ccd_val : 1;
- unsigned int dummy1 : 28;
-} reg_gio_rw_pwm0_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
-#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192
-
-/* Register rw_pwm0_var, scope gio, type rw */
-typedef struct {
- unsigned int lo : 13;
- unsigned int hi : 13;
- unsigned int dummy1 : 6;
-} reg_gio_rw_pwm0_var;
-#define REG_RD_ADDR_gio_rw_pwm0_var 196
-#define REG_WR_ADDR_gio_rw_pwm0_var 196
-
-/* Register rw_pwm0_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pwm0_data;
-#define REG_RD_ADDR_gio_rw_pwm0_data 200
-#define REG_WR_ADDR_gio_rw_pwm0_data 200
-
-/* Register rw_pwm1_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int mode : 2;
- unsigned int ccd_override : 1;
- unsigned int ccd_val : 1;
- unsigned int dummy1 : 28;
-} reg_gio_rw_pwm1_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
-#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204
-
-/* Register rw_pwm1_var, scope gio, type rw */
-typedef struct {
- unsigned int lo : 13;
- unsigned int hi : 13;
- unsigned int dummy1 : 6;
-} reg_gio_rw_pwm1_var;
-#define REG_RD_ADDR_gio_rw_pwm1_var 208
-#define REG_WR_ADDR_gio_rw_pwm1_var 208
-
-/* Register rw_pwm1_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pwm1_data;
-#define REG_RD_ADDR_gio_rw_pwm1_data 212
-#define REG_WR_ADDR_gio_rw_pwm1_data 212
-
-/* Register rw_pwm2_ctrl, scope gio, type rw */
-typedef struct {
- unsigned int mode : 2;
- unsigned int ccd_override : 1;
- unsigned int ccd_val : 1;
- unsigned int dummy1 : 28;
-} reg_gio_rw_pwm2_ctrl;
-#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
-#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216
-
-/* Register rw_pwm2_var, scope gio, type rw */
-typedef struct {
- unsigned int lo : 13;
- unsigned int hi : 13;
- unsigned int dummy1 : 6;
-} reg_gio_rw_pwm2_var;
-#define REG_RD_ADDR_gio_rw_pwm2_var 220
-#define REG_WR_ADDR_gio_rw_pwm2_var 220
-
-/* Register rw_pwm2_data, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pwm2_data;
-#define REG_RD_ADDR_gio_rw_pwm2_data 224
-#define REG_WR_ADDR_gio_rw_pwm2_data 224
-
-/* Register rw_pwm_in_cfg, scope gio, type rw */
-typedef struct {
- unsigned int pin : 3;
- unsigned int dummy1 : 29;
-} reg_gio_rw_pwm_in_cfg;
-#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
-#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228
-
-/* Register r_pwm_in_lo, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pwm_in_lo;
-#define REG_RD_ADDR_gio_r_pwm_in_lo 232
-
-/* Register r_pwm_in_hi, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pwm_in_hi;
-#define REG_RD_ADDR_gio_r_pwm_in_hi 236
-
-/* Register r_pwm_in_cnt, scope gio, type r */
-typedef struct {
- unsigned int data : 32;
-} reg_gio_r_pwm_in_cnt;
-#define REG_RD_ADDR_gio_r_pwm_in_cnt 240
-
-
-/* Constants */
-enum {
- regk_gio_anyedge = 0x00000007,
- regk_gio_f100k = 0x00000000,
- regk_gio_f1562 = 0x00000000,
- regk_gio_f195 = 0x00000003,
- regk_gio_f1m = 0x00000002,
- regk_gio_f390 = 0x00000002,
- regk_gio_f400k = 0x00000001,
- regk_gio_f5m = 0x00000003,
- regk_gio_f781 = 0x00000001,
- regk_gio_hi = 0x00000001,
- regk_gio_in = 0x00000000,
- regk_gio_intr_pa0 = 0x00000000,
- regk_gio_intr_pa1 = 0x00000000,
- regk_gio_intr_pa10 = 0x00000001,
- regk_gio_intr_pa11 = 0x00000001,
- regk_gio_intr_pa12 = 0x00000001,
- regk_gio_intr_pa13 = 0x00000001,
- regk_gio_intr_pa14 = 0x00000001,
- regk_gio_intr_pa15 = 0x00000001,
- regk_gio_intr_pa16 = 0x00000002,
- regk_gio_intr_pa17 = 0x00000002,
- regk_gio_intr_pa18 = 0x00000002,
- regk_gio_intr_pa19 = 0x00000002,
- regk_gio_intr_pa2 = 0x00000000,
- regk_gio_intr_pa20 = 0x00000002,
- regk_gio_intr_pa21 = 0x00000002,
- regk_gio_intr_pa22 = 0x00000002,
- regk_gio_intr_pa23 = 0x00000002,
- regk_gio_intr_pa24 = 0x00000003,
- regk_gio_intr_pa25 = 0x00000003,
- regk_gio_intr_pa26 = 0x00000003,
- regk_gio_intr_pa27 = 0x00000003,
- regk_gio_intr_pa28 = 0x00000003,
- regk_gio_intr_pa29 = 0x00000003,
- regk_gio_intr_pa3 = 0x00000000,
- regk_gio_intr_pa30 = 0x00000003,
- regk_gio_intr_pa31 = 0x00000003,
- regk_gio_intr_pa4 = 0x00000000,
- regk_gio_intr_pa5 = 0x00000000,
- regk_gio_intr_pa6 = 0x00000000,
- regk_gio_intr_pa7 = 0x00000000,
- regk_gio_intr_pa8 = 0x00000001,
- regk_gio_intr_pa9 = 0x00000001,
- regk_gio_intr_pb0 = 0x00000004,
- regk_gio_intr_pb1 = 0x00000004,
- regk_gio_intr_pb10 = 0x00000005,
- regk_gio_intr_pb11 = 0x00000005,
- regk_gio_intr_pb12 = 0x00000005,
- regk_gio_intr_pb13 = 0x00000005,
- regk_gio_intr_pb14 = 0x00000005,
- regk_gio_intr_pb15 = 0x00000005,
- regk_gio_intr_pb16 = 0x00000006,
- regk_gio_intr_pb17 = 0x00000006,
- regk_gio_intr_pb18 = 0x00000006,
- regk_gio_intr_pb19 = 0x00000006,
- regk_gio_intr_pb2 = 0x00000004,
- regk_gio_intr_pb20 = 0x00000006,
- regk_gio_intr_pb21 = 0x00000006,
- regk_gio_intr_pb22 = 0x00000006,
- regk_gio_intr_pb23 = 0x00000006,
- regk_gio_intr_pb24 = 0x00000007,
- regk_gio_intr_pb25 = 0x00000007,
- regk_gio_intr_pb26 = 0x00000007,
- regk_gio_intr_pb27 = 0x00000007,
- regk_gio_intr_pb28 = 0x00000007,
- regk_gio_intr_pb29 = 0x00000007,
- regk_gio_intr_pb3 = 0x00000004,
- regk_gio_intr_pb30 = 0x00000007,
- regk_gio_intr_pb31 = 0x00000007,
- regk_gio_intr_pb4 = 0x00000004,
- regk_gio_intr_pb5 = 0x00000004,
- regk_gio_intr_pb6 = 0x00000004,
- regk_gio_intr_pb7 = 0x00000004,
- regk_gio_intr_pb8 = 0x00000005,
- regk_gio_intr_pb9 = 0x00000005,
- regk_gio_intr_pc0 = 0x00000008,
- regk_gio_intr_pc1 = 0x00000008,
- regk_gio_intr_pc10 = 0x00000009,
- regk_gio_intr_pc11 = 0x00000009,
- regk_gio_intr_pc12 = 0x00000009,
- regk_gio_intr_pc13 = 0x00000009,
- regk_gio_intr_pc14 = 0x00000009,
- regk_gio_intr_pc15 = 0x00000009,
- regk_gio_intr_pc2 = 0x00000008,
- regk_gio_intr_pc3 = 0x00000008,
- regk_gio_intr_pc4 = 0x00000008,
- regk_gio_intr_pc5 = 0x00000008,
- regk_gio_intr_pc6 = 0x00000008,
- regk_gio_intr_pc7 = 0x00000008,
- regk_gio_intr_pc8 = 0x00000009,
- regk_gio_intr_pc9 = 0x00000009,
- regk_gio_intr_pd0 = 0x0000000c,
- regk_gio_intr_pd1 = 0x0000000c,
- regk_gio_intr_pd10 = 0x0000000d,
- regk_gio_intr_pd11 = 0x0000000d,
- regk_gio_intr_pd12 = 0x0000000d,
- regk_gio_intr_pd13 = 0x0000000d,
- regk_gio_intr_pd14 = 0x0000000d,
- regk_gio_intr_pd15 = 0x0000000d,
- regk_gio_intr_pd16 = 0x0000000e,
- regk_gio_intr_pd17 = 0x0000000e,
- regk_gio_intr_pd18 = 0x0000000e,
- regk_gio_intr_pd19 = 0x0000000e,
- regk_gio_intr_pd2 = 0x0000000c,
- regk_gio_intr_pd20 = 0x0000000e,
- regk_gio_intr_pd21 = 0x0000000e,
- regk_gio_intr_pd22 = 0x0000000e,
- regk_gio_intr_pd23 = 0x0000000e,
- regk_gio_intr_pd24 = 0x0000000f,
- regk_gio_intr_pd25 = 0x0000000f,
- regk_gio_intr_pd26 = 0x0000000f,
- regk_gio_intr_pd27 = 0x0000000f,
- regk_gio_intr_pd28 = 0x0000000f,
- regk_gio_intr_pd29 = 0x0000000f,
- regk_gio_intr_pd3 = 0x0000000c,
- regk_gio_intr_pd30 = 0x0000000f,
- regk_gio_intr_pd31 = 0x0000000f,
- regk_gio_intr_pd4 = 0x0000000c,
- regk_gio_intr_pd5 = 0x0000000c,
- regk_gio_intr_pd6 = 0x0000000c,
- regk_gio_intr_pd7 = 0x0000000c,
- regk_gio_intr_pd8 = 0x0000000d,
- regk_gio_intr_pd9 = 0x0000000d,
- regk_gio_lo = 0x00000002,
- regk_gio_lsb = 0x00000000,
- regk_gio_msb = 0x00000001,
- regk_gio_negedge = 0x00000006,
- regk_gio_no = 0x00000000,
- regk_gio_no_switch = 0x0000003f,
- regk_gio_none = 0x00000007,
- regk_gio_off = 0x00000000,
- regk_gio_opendrain = 0x00000000,
- regk_gio_out = 0x00000001,
- regk_gio_posedge = 0x00000005,
- regk_gio_pwm_hfp = 0x00000002,
- regk_gio_pwm_pa0 = 0x00000001,
- regk_gio_pwm_pa19 = 0x00000004,
- regk_gio_pwm_pa6 = 0x00000002,
- regk_gio_pwm_pa7 = 0x00000003,
- regk_gio_pwm_pb26 = 0x00000005,
- regk_gio_pwm_pd23 = 0x00000006,
- regk_gio_pwm_pd31 = 0x00000007,
- regk_gio_pwm_std = 0x00000001,
- regk_gio_pwm_var = 0x00000003,
- regk_gio_rw_i2c0_cfg_default = 0x00000020,
- regk_gio_rw_i2c0_ctrl_default = 0x00010000,
- regk_gio_rw_i2c0_start_default = 0x00000000,
- regk_gio_rw_i2c1_cfg_default = 0x00000aa0,
- regk_gio_rw_i2c1_ctrl_default = 0x00010000,
- regk_gio_rw_i2c1_start_default = 0x00000000,
- regk_gio_rw_intr_cfg_default = 0x00000000,
- regk_gio_rw_intr_mask_default = 0x00000000,
- regk_gio_rw_pa_oe_default = 0x00000000,
- regk_gio_rw_pb_oe_default = 0x00000000,
- regk_gio_rw_pc_oe_default = 0x00000000,
- regk_gio_rw_ppwm_data_default = 0x00000000,
- regk_gio_rw_pwm0_ctrl_default = 0x00000000,
- regk_gio_rw_pwm1_ctrl_default = 0x00000000,
- regk_gio_rw_pwm2_ctrl_default = 0x00000000,
- regk_gio_rw_pwm_in_cfg_default = 0x00000000,
- regk_gio_sda0 = 0x00000000,
- regk_gio_sda1 = 0x00000001,
- regk_gio_sda2 = 0x00000002,
- regk_gio_sda3 = 0x00000003,
- regk_gio_sen = 0x00000000,
- regk_gio_set = 0x00000003,
- regk_gio_yes = 0x00000001
-};
-#endif /* __gio_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h
deleted file mode 100644
index 55dab5bd7bd3..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr
- from intr_vect.r */
-
-#ifndef _INTR_VECT_R
-#define _INTR_VECT_R
-#define TIMER0_INTR_VECT 0x31
-#define TIMER1_INTR_VECT 0x32
-#define DMA0_INTR_VECT 0x33
-#define DMA1_INTR_VECT 0x34
-#define DMA2_INTR_VECT 0x35
-#define DMA3_INTR_VECT 0x36
-#define DMA4_INTR_VECT 0x37
-#define DMA5_INTR_VECT 0x38
-#define DMA6_INTR_VECT 0x39
-#define DMA7_INTR_VECT 0x3a
-#define DMA9_INTR_VECT 0x3b
-#define DMA11_INTR_VECT 0x3c
-#define GIO_INTR_VECT 0x3d
-#define IOP0_INTR_VECT 0x3e
-#define IOP1_INTR_VECT 0x3f
-#define SER0_INTR_VECT 0x40
-#define SER1_INTR_VECT 0x41
-#define SER2_INTR_VECT 0x42
-#define SER3_INTR_VECT 0x43
-#define SER4_INTR_VECT 0x44
-#define SSER_INTR_VECT 0x45
-#define STRDMA0_INTR_VECT 0x46
-#define STRDMA1_INTR_VECT 0x47
-#define STRDMA2_INTR_VECT 0x48
-#define STRDMA3_INTR_VECT 0x49
-#define STRDMA5_INTR_VECT 0x4a
-#define VIN_INTR_VECT 0x4b
-#define VOUT_INTR_VECT 0x4c
-#define JPEG_INTR_VECT 0x4d
-#define H264_INTR_VECT 0x4e
-#define HISTO_INTR_VECT 0x4f
-#define CCD_INTR_VECT 0x50
-#define ETH_INTR_VECT 0x51
-#define MEMARB_BAR_INTR_VECT 0x52
-#define MEMARB_FOO_INTR_VECT 0x53
-#define PIO_INTR_VECT 0x54
-#define SCLR_INTR_VECT 0x55
-#define SCLR_FIFO_INTR_VECT 0x56
-#define IPI_INTR_VECT 0x57
-#define NBR_INTR_VECT 0x58
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h
deleted file mode 100644
index 71a28d1ed74a..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/intr_vect_defs.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __intr_vect_defs_h
-#define __intr_vect_defs_h
-
-/*
- * This file is autogenerated from
- * file: intr_vect.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope intr_vect */
-
-
-#define STRIDE_intr_vect_rw_mask 4
-/* Register rw_mask0, scope intr_vect, type rw */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_rw_mask0;
-#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
-#define REG_RD_ADDR_intr_vect_rw_mask 0
-#define REG_WR_ADDR_intr_vect_rw_mask 0
-#define REG_RD_ADDR_intr_vect_rw_mask0 0
-#define REG_WR_ADDR_intr_vect_rw_mask0 0
-
-#define STRIDE_intr_vect_r_vect 4
-/* Register r_vect0, scope intr_vect, type r */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_r_vect0;
-#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
-#define REG_RD_ADDR_intr_vect_r_vect 8
-#define REG_RD_ADDR_intr_vect_r_vect0 8
-
-#define STRIDE_intr_vect_r_masked_vect 4
-/* Register r_masked_vect0, scope intr_vect, type r */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_r_masked_vect0;
-#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
-#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
-#define REG_RD_ADDR_intr_vect_r_masked_vect 16
-
-#define STRIDE_intr_vect_rw_xmask 4
-/* Register rw_xmask0, scope intr_vect, type rw */
-typedef struct {
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int gio : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int strdma0 : 1;
- unsigned int strdma1 : 1;
- unsigned int strdma2 : 1;
- unsigned int strdma3 : 1;
- unsigned int strdma5 : 1;
- unsigned int vin : 1;
- unsigned int vout : 1;
- unsigned int jpeg : 1;
- unsigned int h264 : 1;
- unsigned int histo : 1;
- unsigned int ccd : 1;
-} reg_intr_vect_rw_xmask0;
-#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
-#define REG_RD_ADDR_intr_vect_rw_xmask0 24
-#define REG_WR_ADDR_intr_vect_rw_xmask0 24
-#define REG_RD_ADDR_intr_vect_rw_xmask 24
-#define REG_WR_ADDR_intr_vect_rw_xmask 24
-
-/* Register rw_mask1, scope intr_vect, type rw */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_rw_mask1;
-#define REG_RD_ADDR_intr_vect_rw_mask1 4
-#define REG_WR_ADDR_intr_vect_rw_mask1 4
-
-/* Register r_vect1, scope intr_vect, type r */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_r_vect1;
-#define REG_RD_ADDR_intr_vect_r_vect1 12
-
-/* Register r_masked_vect1, scope intr_vect, type r */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_r_masked_vect1;
-#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
-
-/* Register rw_xmask1, scope intr_vect, type rw */
-typedef struct {
- unsigned int eth : 1;
- unsigned int memarb_bar : 1;
- unsigned int memarb_foo : 1;
- unsigned int pio : 1;
- unsigned int sclr : 1;
- unsigned int sclr_fifo : 1;
- unsigned int dummy1 : 26;
-} reg_intr_vect_rw_xmask1;
-#define REG_RD_ADDR_intr_vect_rw_xmask1 28
-#define REG_WR_ADDR_intr_vect_rw_xmask1 28
-
-/* Register rw_xmask_ctrl, scope intr_vect, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_intr_vect_rw_xmask_ctrl;
-#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
-#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
-
-/* Register r_nmi, scope intr_vect, type r */
-typedef struct {
- unsigned int watchdog0 : 1;
- unsigned int watchdog1 : 1;
- unsigned int dummy1 : 30;
-} reg_intr_vect_r_nmi;
-#define REG_RD_ADDR_intr_vect_r_nmi 64
-
-/* Register r_guru, scope intr_vect, type r */
-typedef struct {
- unsigned int jtag : 1;
- unsigned int dummy1 : 31;
-} reg_intr_vect_r_guru;
-#define REG_RD_ADDR_intr_vect_r_guru 68
-
-
-/* Register rw_ipi, scope intr_vect, type rw */
-typedef struct
-{
- unsigned int vector;
-} reg_intr_vect_rw_ipi;
-#define REG_RD_ADDR_intr_vect_rw_ipi 72
-#define REG_WR_ADDR_intr_vect_rw_ipi 72
-
-/* Constants */
-enum {
- regk_intr_vect_no = 0x00000000,
- regk_intr_vect_rw_mask0_default = 0x00000000,
- regk_intr_vect_rw_mask1_default = 0x00000000,
- regk_intr_vect_rw_xmask0_default = 0x00000000,
- regk_intr_vect_rw_xmask1_default = 0x00000000,
- regk_intr_vect_rw_xmask_ctrl_default = 0x00000000,
- regk_intr_vect_yes = 0x00000001
-};
-#endif /* __intr_vect_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h
deleted file mode 100644
index 5e5f4d94aecf..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
- */
-#define iop_version 0
-#define iop_fifo_in_extra 64
-#define iop_fifo_out_extra 128
-#define iop_trigger_grp0 192
-#define iop_trigger_grp1 256
-#define iop_trigger_grp2 320
-#define iop_trigger_grp3 384
-#define iop_trigger_grp4 448
-#define iop_trigger_grp5 512
-#define iop_trigger_grp6 576
-#define iop_trigger_grp7 640
-#define iop_crc_par 768
-#define iop_dmc_in 896
-#define iop_dmc_out 1024
-#define iop_fifo_in 1152
-#define iop_fifo_out 1280
-#define iop_scrc_in 1408
-#define iop_scrc_out 1536
-#define iop_timer_grp0 1664
-#define iop_timer_grp1 1792
-#define iop_sap_in 2048
-#define iop_sap_out 2304
-#define iop_spu 2560
-#define iop_sw_cfg 2816
-#define iop_sw_cpu 3072
-#define iop_sw_mpu 3328
-#define iop_sw_spu 3584
-#define iop_mpu 4096
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h
deleted file mode 100644
index ee0587ec433c..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_asm_h
-#define __iop_sap_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_in.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_sap_in_rw_bus_byte 4
-/* Register rw_bus_byte, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
-#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
-#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
-#define reg_iop_sap_in_rw_bus_byte___delay___width 2
-#define reg_iop_sap_in_rw_bus_byte_offset 0
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_gio___sync_sel___width 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_gio___sync_edge___width 2
-#define reg_iop_sap_in_rw_gio___delay___lsb 7
-#define reg_iop_sap_in_rw_gio___delay___width 2
-#define reg_iop_sap_in_rw_gio___logic___lsb 9
-#define reg_iop_sap_in_rw_gio___logic___width 2
-#define reg_iop_sap_in_rw_gio_offset 16
-
-
-/* Constants */
-#define regk_iop_sap_in_and 0x00000002
-#define regk_iop_sap_in_ext_clk200 0x00000003
-#define regk_iop_sap_in_gio0 0x00000000
-#define regk_iop_sap_in_gio12 0x00000003
-#define regk_iop_sap_in_gio16 0x00000004
-#define regk_iop_sap_in_gio20 0x00000005
-#define regk_iop_sap_in_gio24 0x00000006
-#define regk_iop_sap_in_gio28 0x00000007
-#define regk_iop_sap_in_gio4 0x00000001
-#define regk_iop_sap_in_gio8 0x00000002
-#define regk_iop_sap_in_inv 0x00000001
-#define regk_iop_sap_in_neg 0x00000002
-#define regk_iop_sap_in_no 0x00000000
-#define regk_iop_sap_in_no_del_ext_clk200 0x00000002
-#define regk_iop_sap_in_none 0x00000000
-#define regk_iop_sap_in_one 0x00000001
-#define regk_iop_sap_in_or 0x00000003
-#define regk_iop_sap_in_pos 0x00000001
-#define regk_iop_sap_in_pos_neg 0x00000003
-#define regk_iop_sap_in_rw_bus_byte_default 0x00000000
-#define regk_iop_sap_in_rw_bus_byte_size 0x00000004
-#define regk_iop_sap_in_rw_gio_default 0x00000000
-#define regk_iop_sap_in_rw_gio_size 0x00000020
-#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000
-#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001
-#define regk_iop_sap_in_tmr_clk200 0x00000001
-#define regk_iop_sap_in_two 0x00000002
-#define regk_iop_sap_in_two_clk200 0x00000000
-#endif /* __iop_sap_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h
deleted file mode 100644
index 9bbe0b920c93..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_asm_h
-#define __iop_sap_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_out.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated_offset 0
-
-/* Register rw_bus, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6
-#define reg_iop_sap_out_rw_bus___byte0_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6
-#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7
-#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9
-#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12
-#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13
-#define reg_iop_sap_out_rw_bus___byte1_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13
-#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14
-#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16
-#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20
-#define reg_iop_sap_out_rw_bus___byte2_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20
-#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21
-#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23
-#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26
-#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27
-#define reg_iop_sap_out_rw_bus___byte3_delay___width 1
-#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27
-#define reg_iop_sap_out_rw_bus_offset 4
-
-/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9
-#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20
-#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_lo_oe_offset 8
-
-/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9
-#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20
-#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2
-#define reg_iop_sap_out_rw_bus_hi_oe_offset 12
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2
-#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5
-#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1
-#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5
-#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6
-#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6
-#define reg_iop_sap_out_rw_gio___out_delay___lsb 7
-#define reg_iop_sap_out_rw_gio___out_delay___width 1
-#define reg_iop_sap_out_rw_gio___out_delay___bit 7
-#define reg_iop_sap_out_rw_gio___out_logic___lsb 8
-#define reg_iop_sap_out_rw_gio___out_logic___width 2
-#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10
-#define reg_iop_sap_out_rw_gio___out_logic_src___width 2
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18
-#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19
-#define reg_iop_sap_out_rw_gio___oe_delay___width 1
-#define reg_iop_sap_out_rw_gio___oe_delay___bit 19
-#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
-#define reg_iop_sap_out_rw_gio___oe_logic___width 2
-#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22
-#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2
-#define reg_iop_sap_out_rw_gio_offset 16
-
-
-/* Constants */
-#define regk_iop_sap_out_always 0x00000001
-#define regk_iop_sap_out_and 0x00000002
-#define regk_iop_sap_out_clk0 0x00000000
-#define regk_iop_sap_out_clk1 0x00000001
-#define regk_iop_sap_out_clk12 0x00000004
-#define regk_iop_sap_out_clk200 0x00000000
-#define regk_iop_sap_out_ext 0x00000002
-#define regk_iop_sap_out_gated 0x00000003
-#define regk_iop_sap_out_gio0 0x00000000
-#define regk_iop_sap_out_gio1 0x00000000
-#define regk_iop_sap_out_gio16 0x00000002
-#define regk_iop_sap_out_gio17 0x00000002
-#define regk_iop_sap_out_gio24 0x00000003
-#define regk_iop_sap_out_gio25 0x00000003
-#define regk_iop_sap_out_gio8 0x00000001
-#define regk_iop_sap_out_gio9 0x00000001
-#define regk_iop_sap_out_gio_out10 0x00000005
-#define regk_iop_sap_out_gio_out18 0x00000006
-#define regk_iop_sap_out_gio_out2 0x00000004
-#define regk_iop_sap_out_gio_out26 0x00000007
-#define regk_iop_sap_out_inv 0x00000001
-#define regk_iop_sap_out_nand 0x00000003
-#define regk_iop_sap_out_no 0x00000000
-#define regk_iop_sap_out_none 0x00000000
-#define regk_iop_sap_out_one 0x00000001
-#define regk_iop_sap_out_rw_bus_default 0x00000000
-#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000
-#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000
-#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
-#define regk_iop_sap_out_rw_gio_default 0x00000000
-#define regk_iop_sap_out_rw_gio_size 0x00000020
-#define regk_iop_sap_out_spu_gio6 0x00000002
-#define regk_iop_sap_out_spu_gio7 0x00000003
-#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000
-#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001
-#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002
-#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003
-#define regk_iop_sap_out_tmr200 0x00000001
-#define regk_iop_sap_out_yes 0x00000001
-#endif /* __iop_sap_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
deleted file mode 100644
index c4b8bc386cb6..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
+++ /dev/null
@@ -1,740 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_asm_h
-#define __iop_sw_cfg_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cfg.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0
-
-/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4
-
-/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8
-
-/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12
-
-/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16
-
-/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20
-
-/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32
-
-/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36
-
-/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40
-
-/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1
-#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0
-#define reg_iop_sw_cfg_rw_spu_owner_offset 44
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84
-
-/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus_mask_offset 88
-
-/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_mask_offset 96
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6
-#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
-#define reg_iop_sw_cfg_rw_pinmapping_offset 104
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2
-#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140
-
-/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1
-#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1
-#define reg_iop_sw_cfg_rw_spu_cfg_offset 144
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156
-
-/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0
-#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11
-#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164
-
-
-/* Constants */
-#define regk_iop_sw_cfg_a 0x00000001
-#define regk_iop_sw_cfg_b 0x00000002
-#define regk_iop_sw_cfg_bus 0x00000000
-#define regk_iop_sw_cfg_bus_rot16 0x00000002
-#define regk_iop_sw_cfg_bus_rot24 0x00000003
-#define regk_iop_sw_cfg_bus_rot8 0x00000001
-#define regk_iop_sw_cfg_clk12 0x00000000
-#define regk_iop_sw_cfg_cpu 0x00000000
-#define regk_iop_sw_cfg_gated_clk0 0x0000000e
-#define regk_iop_sw_cfg_gated_clk1 0x0000000f
-#define regk_iop_sw_cfg_gio0 0x00000004
-#define regk_iop_sw_cfg_gio1 0x00000001
-#define regk_iop_sw_cfg_gio2 0x00000005
-#define regk_iop_sw_cfg_gio3 0x00000002
-#define regk_iop_sw_cfg_gio4 0x00000006
-#define regk_iop_sw_cfg_gio5 0x00000003
-#define regk_iop_sw_cfg_gio6 0x00000007
-#define regk_iop_sw_cfg_gio7 0x00000004
-#define regk_iop_sw_cfg_gio_in18 0x00000002
-#define regk_iop_sw_cfg_gio_in19 0x00000003
-#define regk_iop_sw_cfg_gio_in20 0x00000004
-#define regk_iop_sw_cfg_gio_in21 0x00000005
-#define regk_iop_sw_cfg_gio_in26 0x00000006
-#define regk_iop_sw_cfg_gio_in27 0x00000007
-#define regk_iop_sw_cfg_gio_in4 0x00000000
-#define regk_iop_sw_cfg_gio_in5 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
-#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002
-#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003
-#define regk_iop_sw_cfg_mpu 0x00000001
-#define regk_iop_sw_cfg_none 0x00000000
-#define regk_iop_sw_cfg_pdp_out 0x00000001
-#define regk_iop_sw_cfg_pdp_out_hi 0x00000001
-#define regk_iop_sw_cfg_pdp_out_lo 0x00000000
-#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555
-#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
-#define regk_iop_sw_cfg_sdp_out 0x00000004
-#define regk_iop_sw_cfg_size16 0x00000002
-#define regk_iop_sw_cfg_size24 0x00000003
-#define regk_iop_sw_cfg_size32 0x00000004
-#define regk_iop_sw_cfg_size8 0x00000001
-#define regk_iop_sw_cfg_spu 0x00000002
-#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002
-#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002
-#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003
-#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003
-#define regk_iop_sw_cfg_spu_g0 0x00000007
-#define regk_iop_sw_cfg_spu_g1 0x00000007
-#define regk_iop_sw_cfg_spu_g2 0x00000007
-#define regk_iop_sw_cfg_spu_g3 0x00000007
-#define regk_iop_sw_cfg_spu_g4 0x00000007
-#define regk_iop_sw_cfg_spu_g5 0x00000007
-#define regk_iop_sw_cfg_spu_g6 0x00000007
-#define regk_iop_sw_cfg_spu_g7 0x00000007
-#define regk_iop_sw_cfg_spu_gio0 0x00000000
-#define regk_iop_sw_cfg_spu_gio1 0x00000001
-#define regk_iop_sw_cfg_spu_gio5 0x00000005
-#define regk_iop_sw_cfg_spu_gio6 0x00000006
-#define regk_iop_sw_cfg_spu_gio7 0x00000007
-#define regk_iop_sw_cfg_spu_gio_out0 0x00000008
-#define regk_iop_sw_cfg_spu_gio_out1 0x00000009
-#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a
-#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b
-#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c
-#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d
-#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e
-#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f
-#define regk_iop_sw_cfg_spu_gioout0 0x00000000
-#define regk_iop_sw_cfg_spu_gioout1 0x00000000
-#define regk_iop_sw_cfg_spu_gioout10 0x00000007
-#define regk_iop_sw_cfg_spu_gioout11 0x00000007
-#define regk_iop_sw_cfg_spu_gioout12 0x00000007
-#define regk_iop_sw_cfg_spu_gioout13 0x00000007
-#define regk_iop_sw_cfg_spu_gioout14 0x00000007
-#define regk_iop_sw_cfg_spu_gioout15 0x00000007
-#define regk_iop_sw_cfg_spu_gioout16 0x00000007
-#define regk_iop_sw_cfg_spu_gioout17 0x00000007
-#define regk_iop_sw_cfg_spu_gioout18 0x00000007
-#define regk_iop_sw_cfg_spu_gioout19 0x00000007
-#define regk_iop_sw_cfg_spu_gioout2 0x00000001
-#define regk_iop_sw_cfg_spu_gioout20 0x00000007
-#define regk_iop_sw_cfg_spu_gioout21 0x00000007
-#define regk_iop_sw_cfg_spu_gioout22 0x00000007
-#define regk_iop_sw_cfg_spu_gioout23 0x00000007
-#define regk_iop_sw_cfg_spu_gioout24 0x00000007
-#define regk_iop_sw_cfg_spu_gioout25 0x00000007
-#define regk_iop_sw_cfg_spu_gioout26 0x00000007
-#define regk_iop_sw_cfg_spu_gioout27 0x00000007
-#define regk_iop_sw_cfg_spu_gioout28 0x00000007
-#define regk_iop_sw_cfg_spu_gioout29 0x00000007
-#define regk_iop_sw_cfg_spu_gioout3 0x00000001
-#define regk_iop_sw_cfg_spu_gioout30 0x00000007
-#define regk_iop_sw_cfg_spu_gioout31 0x00000007
-#define regk_iop_sw_cfg_spu_gioout4 0x00000002
-#define regk_iop_sw_cfg_spu_gioout5 0x00000002
-#define regk_iop_sw_cfg_spu_gioout6 0x00000003
-#define regk_iop_sw_cfg_spu_gioout7 0x00000003
-#define regk_iop_sw_cfg_spu_gioout8 0x00000007
-#define regk_iop_sw_cfg_spu_gioout9 0x00000007
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
-#define regk_iop_sw_cfg_timer_grp0 0x00000000
-#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005
-#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002
-#define regk_iop_sw_cfg_timer_grp1 0x00000000
-#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
-#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006
-#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003
-#define regk_iop_sw_cfg_trig0_0 0x00000000
-#define regk_iop_sw_cfg_trig0_1 0x00000000
-#define regk_iop_sw_cfg_trig0_2 0x00000000
-#define regk_iop_sw_cfg_trig0_3 0x00000000
-#define regk_iop_sw_cfg_trig1_0 0x00000000
-#define regk_iop_sw_cfg_trig1_1 0x00000000
-#define regk_iop_sw_cfg_trig1_2 0x00000000
-#define regk_iop_sw_cfg_trig1_3 0x00000000
-#define regk_iop_sw_cfg_trig2_0 0x00000001
-#define regk_iop_sw_cfg_trig2_1 0x00000001
-#define regk_iop_sw_cfg_trig2_2 0x00000001
-#define regk_iop_sw_cfg_trig2_3 0x00000001
-#define regk_iop_sw_cfg_trig3_0 0x00000001
-#define regk_iop_sw_cfg_trig3_1 0x00000001
-#define regk_iop_sw_cfg_trig3_2 0x00000001
-#define regk_iop_sw_cfg_trig3_3 0x00000001
-#define regk_iop_sw_cfg_trig4_0 0x00000002
-#define regk_iop_sw_cfg_trig4_1 0x00000002
-#define regk_iop_sw_cfg_trig4_2 0x00000002
-#define regk_iop_sw_cfg_trig4_3 0x00000002
-#define regk_iop_sw_cfg_trig5_0 0x00000002
-#define regk_iop_sw_cfg_trig5_1 0x00000002
-#define regk_iop_sw_cfg_trig5_2 0x00000002
-#define regk_iop_sw_cfg_trig5_3 0x00000002
-#define regk_iop_sw_cfg_trig6_0 0x00000003
-#define regk_iop_sw_cfg_trig6_1 0x00000003
-#define regk_iop_sw_cfg_trig6_2 0x00000003
-#define regk_iop_sw_cfg_trig6_3 0x00000003
-#define regk_iop_sw_cfg_trig7_0 0x00000003
-#define regk_iop_sw_cfg_trig7_1 0x00000003
-#define regk_iop_sw_cfg_trig7_2 0x00000003
-#define regk_iop_sw_cfg_trig7_3 0x00000003
-#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
deleted file mode 100644
index 89f36dc1f96d..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
+++ /dev/null
@@ -1,951 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_asm_h
-#define __iop_sw_cpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_mpu_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mpu_trace_offset 0
-
-/* Register r_spu_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_spu_trace_offset 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_cpu_rw_mc_data___val___width 32
-#define reg_iop_sw_cpu_rw_mc_data_offset 16
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_addr_offset 20
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-#define reg_iop_sw_cpu_rs_mc_data_offset 24
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_data_offset 28
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_cpu_r_mc_stat_offset 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36
-
-/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48
-
-/* Register r_bus_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus_in_offset 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_gio_in_offset 72
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31
-#define reg_iop_sw_cpu_rw_intr0_mask_offset 76
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr0_offset 80
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_r_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_r_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_r_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_r_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_r_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_r_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_r_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_r_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_r_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_r_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_r_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_r_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_r_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_r_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_r_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_r_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_r_intr0_offset 84
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31
-#define reg_iop_sw_cpu_r_masked_intr0_offset 88
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31
-#define reg_iop_sw_cpu_rw_intr1_mask_offset 92
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr1_offset 96
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16
-#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1
-#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16
-#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17
-#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1
-#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17
-#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18
-#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18
-#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19
-#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_intr1_offset 100
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_masked_intr1_offset 104
-
-
-/* Constants */
-#define regk_iop_sw_cpu_copy 0x00000000
-#define regk_iop_sw_cpu_no 0x00000000
-#define regk_iop_sw_cpu_rd 0x00000002
-#define regk_iop_sw_cpu_reg_copy 0x00000001
-#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
-#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
-#define regk_iop_sw_cpu_wr 0x00000003
-#define regk_iop_sw_cpu_yes 0x00000001
-#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
deleted file mode 100644
index 45e19d79dba9..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
+++ /dev/null
@@ -1,1087 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_asm_h
-#define __iop_sw_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_mpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
-#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
-
-/* Register r_spu_trace, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_spu_trace_offset 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_mpu_rw_mc_data___val___width 32
-#define reg_iop_sw_mpu_rw_mc_data_offset 16
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_addr_offset 20
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-#define reg_iop_sw_mpu_rs_mc_data_offset 24
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_data_offset 28
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_mpu_r_mc_stat_offset 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36
-
-/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48
-
-/* Register r_bus_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus_in_offset 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_gio_in_offset 72
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_rw_cpu_intr_offset 76
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_r_cpu_intr_offset 80
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp0_offset 92
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp1_offset 108
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp2_offset 124
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_intr_grp3_offset 140
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144
-
-
-/* Constants */
-#define regk_iop_sw_mpu_copy 0x00000000
-#define regk_iop_sw_mpu_cpu 0x00000000
-#define regk_iop_sw_mpu_mpu 0x00000001
-#define regk_iop_sw_mpu_no 0x00000000
-#define regk_iop_sw_mpu_nop 0x00000000
-#define regk_iop_sw_mpu_rd 0x00000002
-#define regk_iop_sw_mpu_reg_copy 0x00000001
-#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000
-#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000
-#define regk_iop_sw_mpu_set 0x00000001
-#define regk_iop_sw_mpu_spu 0x00000002
-#define regk_iop_sw_mpu_wr 0x00000003
-#define regk_iop_sw_mpu_yes 0x00000001
-#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h
deleted file mode 100644
index 55afb6e320e4..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_asm_h
-#define __iop_sw_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_spu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_mpu_trace, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_trace_offset 0
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6
-#define reg_iop_sw_spu_rw_mc_ctrl_offset 4
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_spu_rw_mc_data___val___width 32
-#define reg_iop_sw_spu_rw_mc_data_offset 8
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_addr_offset 12
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-#define reg_iop_sw_spu_rs_mc_data_offset 16
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_data_offset 20
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5
-#define reg_iop_sw_spu_r_mc_stat_offset 24
-
-/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28
-
-/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_offset 32
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40
-
-/* Register r_bus_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus_in_offset 44
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_set_mask_offset 52
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_gio_in_offset 64
-
-/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68
-
-/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72
-
-/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76
-
-/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_cpu_intr_offset 116
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_cpu_intr_offset 120
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15
-#define reg_iop_sw_spu_r_hw_intr_offset 124
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_mpu_intr_offset 128
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_mpu_intr_offset 132
-
-
-/* Constants */
-#define regk_iop_sw_spu_copy 0x00000000
-#define regk_iop_sw_spu_no 0x00000000
-#define regk_iop_sw_spu_nop 0x00000000
-#define regk_iop_sw_spu_rd 0x00000002
-#define regk_iop_sw_spu_reg_copy 0x00000001
-#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
-#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
-#define regk_iop_sw_spu_set 0x00000001
-#define regk_iop_sw_spu_wr 0x00000003
-#define regk_iop_sw_spu_yes 0x00000001
-#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h
deleted file mode 100644
index 79ff8fafd3bf..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_asm_h
-#define __iop_version_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: iop_version.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_version, scope iop_version, type r */
-#define reg_iop_version_r_version___nr___lsb 0
-#define reg_iop_version_r_version___nr___width 8
-#define reg_iop_version_r_version_offset 0
-
-
-/* Constants */
-#define regk_iop_version_v2_0 0x00000002
-#endif /* __iop_version_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h
deleted file mode 100644
index 23d731f36145..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
- */
-#define regi_iop_version (regi_iop + 0)
-#define regi_iop_fifo_in_extra (regi_iop + 64)
-#define regi_iop_fifo_out_extra (regi_iop + 128)
-#define regi_iop_trigger_grp0 (regi_iop + 192)
-#define regi_iop_trigger_grp1 (regi_iop + 256)
-#define regi_iop_trigger_grp2 (regi_iop + 320)
-#define regi_iop_trigger_grp3 (regi_iop + 384)
-#define regi_iop_trigger_grp4 (regi_iop + 448)
-#define regi_iop_trigger_grp5 (regi_iop + 512)
-#define regi_iop_trigger_grp6 (regi_iop + 576)
-#define regi_iop_trigger_grp7 (regi_iop + 640)
-#define regi_iop_crc_par (regi_iop + 768)
-#define regi_iop_dmc_in (regi_iop + 896)
-#define regi_iop_dmc_out (regi_iop + 1024)
-#define regi_iop_fifo_in (regi_iop + 1152)
-#define regi_iop_fifo_out (regi_iop + 1280)
-#define regi_iop_scrc_in (regi_iop + 1408)
-#define regi_iop_scrc_out (regi_iop + 1536)
-#define regi_iop_timer_grp0 (regi_iop + 1664)
-#define regi_iop_timer_grp1 (regi_iop + 1792)
-#define regi_iop_sap_in (regi_iop + 2048)
-#define regi_iop_sap_out (regi_iop + 2304)
-#define regi_iop_spu (regi_iop + 2560)
-#define regi_iop_sw_cfg (regi_iop + 2816)
-#define regi_iop_sw_cpu (regi_iop + 3072)
-#define regi_iop_sw_mpu (regi_iop + 3328)
-#define regi_iop_sw_spu (regi_iop + 3584)
-#define regi_iop_mpu (regi_iop + 4096)
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h
deleted file mode 100644
index 1d6c09a3230d..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_h
-#define __iop_sap_in_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_in.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_in */
-
-#define STRIDE_iop_sap_in_rw_bus_byte 4
-/* Register rw_bus_byte, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int sync_sel : 2;
- unsigned int sync_ext_src : 3;
- unsigned int sync_edge : 2;
- unsigned int delay : 2;
- unsigned int dummy1 : 23;
-} reg_iop_sap_in_rw_bus_byte;
-#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
-#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-typedef struct {
- unsigned int sync_sel : 2;
- unsigned int sync_ext_src : 3;
- unsigned int sync_edge : 2;
- unsigned int delay : 2;
- unsigned int logic : 2;
- unsigned int dummy1 : 21;
-} reg_iop_sap_in_rw_gio;
-#define REG_RD_ADDR_iop_sap_in_rw_gio 16
-#define REG_WR_ADDR_iop_sap_in_rw_gio 16
-
-
-/* Constants */
-enum {
- regk_iop_sap_in_and = 0x00000002,
- regk_iop_sap_in_ext_clk200 = 0x00000003,
- regk_iop_sap_in_gio0 = 0x00000000,
- regk_iop_sap_in_gio12 = 0x00000003,
- regk_iop_sap_in_gio16 = 0x00000004,
- regk_iop_sap_in_gio20 = 0x00000005,
- regk_iop_sap_in_gio24 = 0x00000006,
- regk_iop_sap_in_gio28 = 0x00000007,
- regk_iop_sap_in_gio4 = 0x00000001,
- regk_iop_sap_in_gio8 = 0x00000002,
- regk_iop_sap_in_inv = 0x00000001,
- regk_iop_sap_in_neg = 0x00000002,
- regk_iop_sap_in_no = 0x00000000,
- regk_iop_sap_in_no_del_ext_clk200 = 0x00000002,
- regk_iop_sap_in_none = 0x00000000,
- regk_iop_sap_in_one = 0x00000001,
- regk_iop_sap_in_or = 0x00000003,
- regk_iop_sap_in_pos = 0x00000001,
- regk_iop_sap_in_pos_neg = 0x00000003,
- regk_iop_sap_in_rw_bus_byte_default = 0x00000000,
- regk_iop_sap_in_rw_bus_byte_size = 0x00000004,
- regk_iop_sap_in_rw_gio_default = 0x00000000,
- regk_iop_sap_in_rw_gio_size = 0x00000020,
- regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000,
- regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001,
- regk_iop_sap_in_tmr_clk200 = 0x00000001,
- regk_iop_sap_in_two = 0x00000002,
- regk_iop_sap_in_two_clk200 = 0x00000000
-};
-#endif /* __iop_sap_in_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h
deleted file mode 100644
index 1cbd30efadb7..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_h
-#define __iop_sap_out_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sap_out.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sap_out */
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int clk0_src : 2;
- unsigned int clk0_gate_src : 2;
- unsigned int clk0_force_src : 3;
- unsigned int clk1_src : 2;
- unsigned int clk1_gate_src : 2;
- unsigned int clk1_force_src : 3;
- unsigned int dummy1 : 18;
-} reg_iop_sap_out_rw_gen_gated;
-#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
-#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
-
-/* Register rw_bus, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 2;
- unsigned int byte0_clk_ext : 2;
- unsigned int byte0_gated_clk : 1;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_delay : 1;
- unsigned int byte1_clk_sel : 2;
- unsigned int byte1_clk_ext : 2;
- unsigned int byte1_gated_clk : 1;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_delay : 1;
- unsigned int byte2_clk_sel : 2;
- unsigned int byte2_clk_ext : 2;
- unsigned int byte2_gated_clk : 1;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_delay : 1;
- unsigned int byte3_clk_sel : 2;
- unsigned int byte3_clk_ext : 2;
- unsigned int byte3_gated_clk : 1;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_delay : 1;
- unsigned int dummy1 : 4;
-} reg_iop_sap_out_rw_bus;
-#define REG_RD_ADDR_iop_sap_out_rw_bus 4
-#define REG_WR_ADDR_iop_sap_out_rw_bus 4
-
-/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte0_clk_sel : 2;
- unsigned int byte0_clk_ext : 2;
- unsigned int byte0_gated_clk : 1;
- unsigned int byte0_clk_inv : 1;
- unsigned int byte0_delay : 1;
- unsigned int byte0_logic : 2;
- unsigned int byte0_logic_src : 2;
- unsigned int byte1_clk_sel : 2;
- unsigned int byte1_clk_ext : 2;
- unsigned int byte1_gated_clk : 1;
- unsigned int byte1_clk_inv : 1;
- unsigned int byte1_delay : 1;
- unsigned int byte1_logic : 2;
- unsigned int byte1_logic_src : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus_lo_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8
-#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8
-
-/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int byte2_clk_sel : 2;
- unsigned int byte2_clk_ext : 2;
- unsigned int byte2_gated_clk : 1;
- unsigned int byte2_clk_inv : 1;
- unsigned int byte2_delay : 1;
- unsigned int byte2_logic : 2;
- unsigned int byte2_logic_src : 2;
- unsigned int byte3_clk_sel : 2;
- unsigned int byte3_clk_ext : 2;
- unsigned int byte3_gated_clk : 1;
- unsigned int byte3_clk_inv : 1;
- unsigned int byte3_delay : 1;
- unsigned int byte3_logic : 2;
- unsigned int byte3_logic_src : 2;
- unsigned int dummy1 : 10;
-} reg_iop_sap_out_rw_bus_hi_oe;
-#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12
-#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-typedef struct {
- unsigned int out_clk_sel : 3;
- unsigned int out_clk_ext : 2;
- unsigned int out_gated_clk : 1;
- unsigned int out_clk_inv : 1;
- unsigned int out_delay : 1;
- unsigned int out_logic : 2;
- unsigned int out_logic_src : 2;
- unsigned int oe_clk_sel : 3;
- unsigned int oe_clk_ext : 2;
- unsigned int oe_gated_clk : 1;
- unsigned int oe_clk_inv : 1;
- unsigned int oe_delay : 1;
- unsigned int oe_logic : 2;
- unsigned int oe_logic_src : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sap_out_rw_gio;
-#define REG_RD_ADDR_iop_sap_out_rw_gio 16
-#define REG_WR_ADDR_iop_sap_out_rw_gio 16
-
-
-/* Constants */
-enum {
- regk_iop_sap_out_always = 0x00000001,
- regk_iop_sap_out_and = 0x00000002,
- regk_iop_sap_out_clk0 = 0x00000000,
- regk_iop_sap_out_clk1 = 0x00000001,
- regk_iop_sap_out_clk12 = 0x00000004,
- regk_iop_sap_out_clk200 = 0x00000000,
- regk_iop_sap_out_ext = 0x00000002,
- regk_iop_sap_out_gated = 0x00000003,
- regk_iop_sap_out_gio0 = 0x00000000,
- regk_iop_sap_out_gio1 = 0x00000000,
- regk_iop_sap_out_gio16 = 0x00000002,
- regk_iop_sap_out_gio17 = 0x00000002,
- regk_iop_sap_out_gio24 = 0x00000003,
- regk_iop_sap_out_gio25 = 0x00000003,
- regk_iop_sap_out_gio8 = 0x00000001,
- regk_iop_sap_out_gio9 = 0x00000001,
- regk_iop_sap_out_gio_out10 = 0x00000005,
- regk_iop_sap_out_gio_out18 = 0x00000006,
- regk_iop_sap_out_gio_out2 = 0x00000004,
- regk_iop_sap_out_gio_out26 = 0x00000007,
- regk_iop_sap_out_inv = 0x00000001,
- regk_iop_sap_out_nand = 0x00000003,
- regk_iop_sap_out_no = 0x00000000,
- regk_iop_sap_out_none = 0x00000000,
- regk_iop_sap_out_one = 0x00000001,
- regk_iop_sap_out_rw_bus_default = 0x00000000,
- regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000,
- regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000,
- regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
- regk_iop_sap_out_rw_gio_default = 0x00000000,
- regk_iop_sap_out_rw_gio_size = 0x00000020,
- regk_iop_sap_out_spu_gio6 = 0x00000002,
- regk_iop_sap_out_spu_gio7 = 0x00000003,
- regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000,
- regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001,
- regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002,
- regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003,
- regk_iop_sap_out_tmr200 = 0x00000001,
- regk_iop_sap_out_yes = 0x00000001
-};
-#endif /* __iop_sap_out_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h
deleted file mode 100644
index 07050b053bb4..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h
+++ /dev/null
@@ -1,726 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_h
-#define __iop_sw_cfg_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cfg.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cfg */
-
-/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_crc_par_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0
-#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0
-
-/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
-
-/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_dmc_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
-#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
-
-/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
-
-/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_in_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
-
-/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
-
-/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_fifo_out_extra_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
-#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_sap_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32
-#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32
-
-/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_in_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
-
-/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_scrc_out_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
-#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
-
-/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 1;
- unsigned int dummy1 : 31;
-} reg_iop_sw_cfg_rw_spu_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_timer_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp0_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp1_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp2_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp3_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp4_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp5_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp6_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_trigger_grp7_owner;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
-
-/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cfg_rw_bus_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88
-
-/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cfg_rw_bus_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cfg_rw_gio_oe_mask;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus_byte0 : 2;
- unsigned int bus_byte1 : 2;
- unsigned int bus_byte2 : 2;
- unsigned int bus_byte3 : 2;
- unsigned int gio3_0 : 2;
- unsigned int gio7_4 : 2;
- unsigned int gio11_8 : 2;
- unsigned int gio15_12 : 2;
- unsigned int gio19_16 : 2;
- unsigned int gio23_20 : 2;
- unsigned int gio27_24 : 2;
- unsigned int gio31_28 : 2;
- unsigned int dummy1 : 8;
-} reg_iop_sw_cfg_rw_pinmapping;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104
-#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus_lo : 2;
- unsigned int bus_hi : 2;
- unsigned int bus_lo_oe : 2;
- unsigned int bus_hi_oe : 2;
- unsigned int dummy1 : 24;
-} reg_iop_sw_cfg_rw_bus_out_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
-#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio0 : 3;
- unsigned int gio0_oe : 1;
- unsigned int gio1 : 3;
- unsigned int gio1_oe : 1;
- unsigned int gio2 : 3;
- unsigned int gio2_oe : 1;
- unsigned int gio3 : 3;
- unsigned int gio3_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio4 : 3;
- unsigned int gio4_oe : 1;
- unsigned int gio5 : 3;
- unsigned int gio5_oe : 1;
- unsigned int gio6 : 3;
- unsigned int gio6_oe : 1;
- unsigned int gio7 : 3;
- unsigned int gio7_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio8 : 3;
- unsigned int gio8_oe : 1;
- unsigned int gio9 : 3;
- unsigned int gio9_oe : 1;
- unsigned int gio10 : 3;
- unsigned int gio10_oe : 1;
- unsigned int gio11 : 3;
- unsigned int gio11_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio12 : 3;
- unsigned int gio12_oe : 1;
- unsigned int gio13 : 3;
- unsigned int gio13_oe : 1;
- unsigned int gio14 : 3;
- unsigned int gio14_oe : 1;
- unsigned int gio15 : 3;
- unsigned int gio15_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio16 : 3;
- unsigned int gio16_oe : 1;
- unsigned int gio17 : 3;
- unsigned int gio17_oe : 1;
- unsigned int gio18 : 3;
- unsigned int gio18_oe : 1;
- unsigned int gio19 : 3;
- unsigned int gio19_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio20 : 3;
- unsigned int gio20_oe : 1;
- unsigned int gio21 : 3;
- unsigned int gio21_oe : 1;
- unsigned int gio22 : 3;
- unsigned int gio22_oe : 1;
- unsigned int gio23 : 3;
- unsigned int gio23_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio24 : 3;
- unsigned int gio24_oe : 1;
- unsigned int gio25 : 3;
- unsigned int gio25_oe : 1;
- unsigned int gio26 : 3;
- unsigned int gio26_oe : 1;
- unsigned int gio27 : 3;
- unsigned int gio27_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int gio28 : 3;
- unsigned int gio28_oe : 1;
- unsigned int gio29 : 3;
- unsigned int gio29_oe : 1;
- unsigned int gio30 : 3;
- unsigned int gio30_oe : 1;
- unsigned int gio31 : 3;
- unsigned int gio31_oe : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
-#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
-
-/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int bus0_in : 1;
- unsigned int bus1_in : 1;
- unsigned int dummy1 : 30;
-} reg_iop_sw_cfg_rw_spu_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144
-#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 2;
- unsigned int tmr1_en : 2;
- unsigned int tmr2_en : 2;
- unsigned int tmr3_en : 2;
- unsigned int tmr0_dis : 2;
- unsigned int tmr1_dis : 2;
- unsigned int tmr2_dis : 2;
- unsigned int tmr3_dis : 2;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_timer_grp0_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int ext_clk : 3;
- unsigned int tmr0_en : 2;
- unsigned int tmr1_en : 2;
- unsigned int tmr2_en : 2;
- unsigned int tmr3_en : 2;
- unsigned int tmr0_dis : 2;
- unsigned int tmr1_dis : 2;
- unsigned int tmr2_dis : 2;
- unsigned int tmr3_dis : 2;
- unsigned int dummy1 : 13;
-} reg_iop_sw_cfg_rw_timer_grp1_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
-#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int grp0_dis : 1;
- unsigned int grp0_en : 1;
- unsigned int grp1_dis : 1;
- unsigned int grp1_en : 1;
- unsigned int grp2_dis : 1;
- unsigned int grp2_en : 1;
- unsigned int grp3_dis : 1;
- unsigned int grp3_en : 1;
- unsigned int grp4_dis : 1;
- unsigned int grp4_en : 1;
- unsigned int grp5_dis : 1;
- unsigned int grp5_en : 1;
- unsigned int grp6_dis : 1;
- unsigned int grp6_en : 1;
- unsigned int grp7_dis : 1;
- unsigned int grp7_en : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cfg_rw_trigger_grps_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
-#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
-
-/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int out_strb : 4;
- unsigned int in_src : 2;
- unsigned int in_size : 3;
- unsigned int in_last : 2;
- unsigned int in_strb : 4;
- unsigned int dummy1 : 17;
-} reg_iop_sw_cfg_rw_pdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160
-#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-typedef struct {
- unsigned int sdp_out_strb : 3;
- unsigned int sdp_in_data : 3;
- unsigned int sdp_in_last : 2;
- unsigned int sdp_in_strb : 3;
- unsigned int dummy1 : 21;
-} reg_iop_sw_cfg_rw_sdp_cfg;
-#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164
-#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164
-
-
-/* Constants */
-enum {
- regk_iop_sw_cfg_a = 0x00000001,
- regk_iop_sw_cfg_b = 0x00000002,
- regk_iop_sw_cfg_bus = 0x00000000,
- regk_iop_sw_cfg_bus_rot16 = 0x00000002,
- regk_iop_sw_cfg_bus_rot24 = 0x00000003,
- regk_iop_sw_cfg_bus_rot8 = 0x00000001,
- regk_iop_sw_cfg_clk12 = 0x00000000,
- regk_iop_sw_cfg_cpu = 0x00000000,
- regk_iop_sw_cfg_gated_clk0 = 0x0000000e,
- regk_iop_sw_cfg_gated_clk1 = 0x0000000f,
- regk_iop_sw_cfg_gio0 = 0x00000004,
- regk_iop_sw_cfg_gio1 = 0x00000001,
- regk_iop_sw_cfg_gio2 = 0x00000005,
- regk_iop_sw_cfg_gio3 = 0x00000002,
- regk_iop_sw_cfg_gio4 = 0x00000006,
- regk_iop_sw_cfg_gio5 = 0x00000003,
- regk_iop_sw_cfg_gio6 = 0x00000007,
- regk_iop_sw_cfg_gio7 = 0x00000004,
- regk_iop_sw_cfg_gio_in18 = 0x00000002,
- regk_iop_sw_cfg_gio_in19 = 0x00000003,
- regk_iop_sw_cfg_gio_in20 = 0x00000004,
- regk_iop_sw_cfg_gio_in21 = 0x00000005,
- regk_iop_sw_cfg_gio_in26 = 0x00000006,
- regk_iop_sw_cfg_gio_in27 = 0x00000007,
- regk_iop_sw_cfg_gio_in4 = 0x00000000,
- regk_iop_sw_cfg_gio_in5 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
- regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002,
- regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003,
- regk_iop_sw_cfg_mpu = 0x00000001,
- regk_iop_sw_cfg_none = 0x00000000,
- regk_iop_sw_cfg_pdp_out = 0x00000001,
- regk_iop_sw_cfg_pdp_out_hi = 0x00000001,
- regk_iop_sw_cfg_pdp_out_lo = 0x00000000,
- regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555,
- regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
- regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
- regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
- regk_iop_sw_cfg_sdp_out = 0x00000004,
- regk_iop_sw_cfg_size16 = 0x00000002,
- regk_iop_sw_cfg_size24 = 0x00000003,
- regk_iop_sw_cfg_size32 = 0x00000004,
- regk_iop_sw_cfg_size8 = 0x00000001,
- regk_iop_sw_cfg_spu = 0x00000002,
- regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002,
- regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002,
- regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003,
- regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003,
- regk_iop_sw_cfg_spu_g0 = 0x00000007,
- regk_iop_sw_cfg_spu_g1 = 0x00000007,
- regk_iop_sw_cfg_spu_g2 = 0x00000007,
- regk_iop_sw_cfg_spu_g3 = 0x00000007,
- regk_iop_sw_cfg_spu_g4 = 0x00000007,
- regk_iop_sw_cfg_spu_g5 = 0x00000007,
- regk_iop_sw_cfg_spu_g6 = 0x00000007,
- regk_iop_sw_cfg_spu_g7 = 0x00000007,
- regk_iop_sw_cfg_spu_gio0 = 0x00000000,
- regk_iop_sw_cfg_spu_gio1 = 0x00000001,
- regk_iop_sw_cfg_spu_gio5 = 0x00000005,
- regk_iop_sw_cfg_spu_gio6 = 0x00000006,
- regk_iop_sw_cfg_spu_gio7 = 0x00000007,
- regk_iop_sw_cfg_spu_gio_out0 = 0x00000008,
- regk_iop_sw_cfg_spu_gio_out1 = 0x00000009,
- regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a,
- regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b,
- regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c,
- regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d,
- regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e,
- regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f,
- regk_iop_sw_cfg_spu_gioout0 = 0x00000000,
- regk_iop_sw_cfg_spu_gioout1 = 0x00000000,
- regk_iop_sw_cfg_spu_gioout10 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout11 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout12 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout13 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout14 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout15 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout16 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout17 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout18 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout19 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout2 = 0x00000001,
- regk_iop_sw_cfg_spu_gioout20 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout21 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout22 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout23 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout24 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout25 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout26 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout27 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout28 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout29 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout3 = 0x00000001,
- regk_iop_sw_cfg_spu_gioout30 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout31 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout4 = 0x00000002,
- regk_iop_sw_cfg_spu_gioout5 = 0x00000002,
- regk_iop_sw_cfg_spu_gioout6 = 0x00000003,
- regk_iop_sw_cfg_spu_gioout7 = 0x00000003,
- regk_iop_sw_cfg_spu_gioout8 = 0x00000007,
- regk_iop_sw_cfg_spu_gioout9 = 0x00000007,
- regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
- regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
- regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003,
- regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
- regk_iop_sw_cfg_timer_grp0 = 0x00000000,
- regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005,
- regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002,
- regk_iop_sw_cfg_timer_grp1 = 0x00000000,
- regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
- regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006,
- regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003,
- regk_iop_sw_cfg_trig0_0 = 0x00000000,
- regk_iop_sw_cfg_trig0_1 = 0x00000000,
- regk_iop_sw_cfg_trig0_2 = 0x00000000,
- regk_iop_sw_cfg_trig0_3 = 0x00000000,
- regk_iop_sw_cfg_trig1_0 = 0x00000000,
- regk_iop_sw_cfg_trig1_1 = 0x00000000,
- regk_iop_sw_cfg_trig1_2 = 0x00000000,
- regk_iop_sw_cfg_trig1_3 = 0x00000000,
- regk_iop_sw_cfg_trig2_0 = 0x00000001,
- regk_iop_sw_cfg_trig2_1 = 0x00000001,
- regk_iop_sw_cfg_trig2_2 = 0x00000001,
- regk_iop_sw_cfg_trig2_3 = 0x00000001,
- regk_iop_sw_cfg_trig3_0 = 0x00000001,
- regk_iop_sw_cfg_trig3_1 = 0x00000001,
- regk_iop_sw_cfg_trig3_2 = 0x00000001,
- regk_iop_sw_cfg_trig3_3 = 0x00000001,
- regk_iop_sw_cfg_trig4_0 = 0x00000002,
- regk_iop_sw_cfg_trig4_1 = 0x00000002,
- regk_iop_sw_cfg_trig4_2 = 0x00000002,
- regk_iop_sw_cfg_trig4_3 = 0x00000002,
- regk_iop_sw_cfg_trig5_0 = 0x00000002,
- regk_iop_sw_cfg_trig5_1 = 0x00000002,
- regk_iop_sw_cfg_trig5_2 = 0x00000002,
- regk_iop_sw_cfg_trig5_3 = 0x00000002,
- regk_iop_sw_cfg_trig6_0 = 0x00000003,
- regk_iop_sw_cfg_trig6_1 = 0x00000003,
- regk_iop_sw_cfg_trig6_2 = 0x00000003,
- regk_iop_sw_cfg_trig6_3 = 0x00000003,
- regk_iop_sw_cfg_trig7_0 = 0x00000003,
- regk_iop_sw_cfg_trig7_1 = 0x00000003,
- regk_iop_sw_cfg_trig7_2 = 0x00000003,
- regk_iop_sw_cfg_trig7_3 = 0x00000003
-};
-#endif /* __iop_sw_cfg_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h
deleted file mode 100644
index b4acdae4f653..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_h
-#define __iop_sw_cpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_cpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_cpu */
-
-/* Register r_mpu_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mpu_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0
-
-/* Register r_spu_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_spu_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace;
-#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu_mem : 1;
- unsigned int dummy1 : 25;
-} reg_iop_sw_cpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20
-#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu : 1;
- unsigned int dummy1 : 26;
-} reg_iop_sw_cpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
-
-/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_cpu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_cpu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
-#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
-
-/* Register r_bus_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_cpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
-#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-typedef unsigned int reg_iop_sw_cpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_rw_intr0_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_rw_ack_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_r_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_0 : 1;
- unsigned int mpu_1 : 1;
- unsigned int mpu_2 : 1;
- unsigned int mpu_3 : 1;
- unsigned int mpu_4 : 1;
- unsigned int mpu_5 : 1;
- unsigned int mpu_6 : 1;
- unsigned int mpu_7 : 1;
- unsigned int mpu_8 : 1;
- unsigned int mpu_9 : 1;
- unsigned int mpu_10 : 1;
- unsigned int mpu_11 : 1;
- unsigned int mpu_12 : 1;
- unsigned int mpu_13 : 1;
- unsigned int mpu_14 : 1;
- unsigned int mpu_15 : 1;
- unsigned int spu_0 : 1;
- unsigned int spu_1 : 1;
- unsigned int spu_2 : 1;
- unsigned int spu_3 : 1;
- unsigned int spu_4 : 1;
- unsigned int spu_5 : 1;
- unsigned int spu_6 : 1;
- unsigned int spu_7 : 1;
- unsigned int spu_8 : 1;
- unsigned int spu_9 : 1;
- unsigned int spu_10 : 1;
- unsigned int spu_11 : 1;
- unsigned int spu_12 : 1;
- unsigned int spu_13 : 1;
- unsigned int spu_14 : 1;
- unsigned int spu_15 : 1;
-} reg_iop_sw_cpu_r_masked_intr0;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dmc_in : 1;
- unsigned int dmc_out : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_rw_intr1_mask;
-#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92
-#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_cpu_rw_ack_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96
-#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dmc_in : 1;
- unsigned int dmc_out : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-typedef struct {
- unsigned int mpu_16 : 1;
- unsigned int mpu_17 : 1;
- unsigned int mpu_18 : 1;
- unsigned int mpu_19 : 1;
- unsigned int mpu_20 : 1;
- unsigned int mpu_21 : 1;
- unsigned int mpu_22 : 1;
- unsigned int mpu_23 : 1;
- unsigned int mpu_24 : 1;
- unsigned int mpu_25 : 1;
- unsigned int mpu_26 : 1;
- unsigned int mpu_27 : 1;
- unsigned int mpu_28 : 1;
- unsigned int mpu_29 : 1;
- unsigned int mpu_30 : 1;
- unsigned int mpu_31 : 1;
- unsigned int dmc_in : 1;
- unsigned int dmc_out : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
-} reg_iop_sw_cpu_r_masked_intr1;
-#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104
-
-
-/* Constants */
-enum {
- regk_iop_sw_cpu_copy = 0x00000000,
- regk_iop_sw_cpu_no = 0x00000000,
- regk_iop_sw_cpu_rd = 0x00000002,
- regk_iop_sw_cpu_reg_copy = 0x00000001,
- regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
- regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
- regk_iop_sw_cpu_wr = 0x00000003,
- regk_iop_sw_cpu_yes = 0x00000001
-};
-#endif /* __iop_sw_cpu_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h
deleted file mode 100644
index bc1abb5fb308..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h
+++ /dev/null
@@ -1,649 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_h
-#define __iop_sw_mpu_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_mpu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_mpu */
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int cfg : 2;
- unsigned int dummy1 : 30;
-} reg_iop_sw_mpu_rw_sw_cfg_owner;
-#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
-
-/* Register r_spu_trace, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
-#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
-
-/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
-#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu_mem : 1;
- unsigned int dummy1 : 25;
-} reg_iop_sw_mpu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
-#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu : 1;
- unsigned int dummy1 : 26;
-} reg_iop_sw_mpu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
-
-/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
-
-/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_mpu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_mpu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
-#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
-
-/* Register r_bus_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_mpu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
-#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-typedef unsigned int reg_iop_sw_mpu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
-#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int intr16 : 1;
- unsigned int intr17 : 1;
- unsigned int intr18 : 1;
- unsigned int intr19 : 1;
- unsigned int intr20 : 1;
- unsigned int intr21 : 1;
- unsigned int intr22 : 1;
- unsigned int intr23 : 1;
- unsigned int intr24 : 1;
- unsigned int intr25 : 1;
- unsigned int intr26 : 1;
- unsigned int intr27 : 1;
- unsigned int intr28 : 1;
- unsigned int intr29 : 1;
- unsigned int intr30 : 1;
- unsigned int intr31 : 1;
-} reg_iop_sw_mpu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp0_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr1 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr2 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr3 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr0 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr1 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr2 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr3 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp0;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr5 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr6 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr7 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp1_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr5 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr6 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr7 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr5 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr6 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr7 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr4 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr5 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr6 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr7 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp1;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp2_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr9 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr10 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr11 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr8 : 1;
- unsigned int trigger_grp0 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr9 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int spu_intr10 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr11 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp2;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr13 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr14 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr15 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_rw_intr_grp3_mask;
-#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
-#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int dummy1 : 3;
- unsigned int spu_intr13 : 1;
- unsigned int dummy2 : 3;
- unsigned int spu_intr14 : 1;
- unsigned int dummy3 : 3;
- unsigned int spu_intr15 : 1;
- unsigned int dummy4 : 19;
-} reg_iop_sw_mpu_rw_ack_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
-#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr13 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr14 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr15 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-typedef struct {
- unsigned int spu_intr12 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int spu_intr13 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_in : 1;
- unsigned int spu_intr14 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int fifo_out : 1;
- unsigned int spu_intr15 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_mpu_r_masked_intr_grp3;
-#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
-
-
-/* Constants */
-enum {
- regk_iop_sw_mpu_copy = 0x00000000,
- regk_iop_sw_mpu_cpu = 0x00000000,
- regk_iop_sw_mpu_mpu = 0x00000001,
- regk_iop_sw_mpu_no = 0x00000000,
- regk_iop_sw_mpu_nop = 0x00000000,
- regk_iop_sw_mpu_rd = 0x00000002,
- regk_iop_sw_mpu_reg_copy = 0x00000001,
- regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
- regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
- regk_iop_sw_mpu_set = 0x00000001,
- regk_iop_sw_mpu_spu = 0x00000002,
- regk_iop_sw_mpu_wr = 0x00000003,
- regk_iop_sw_mpu_yes = 0x00000001
-};
-#endif /* __iop_sw_mpu_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h
deleted file mode 100644
index 82b64360a4d3..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h
+++ /dev/null
@@ -1,442 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_h
-#define __iop_sw_spu_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_sw_spu.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_sw_spu */
-
-/* Register r_mpu_trace, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int keep_owner : 1;
- unsigned int cmd : 2;
- unsigned int size : 3;
- unsigned int wr_spu_mem : 1;
- unsigned int dummy1 : 25;
-} reg_iop_sw_spu_rw_mc_ctrl;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
-#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-typedef unsigned int reg_iop_sw_spu_rs_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_mc_data;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int busy_cpu : 1;
- unsigned int busy_mpu : 1;
- unsigned int busy_spu : 1;
- unsigned int owned_by_cpu : 1;
- unsigned int owned_by_mpu : 1;
- unsigned int owned_by_spu : 1;
- unsigned int dummy1 : 26;
-} reg_iop_sw_spu_r_mc_stat;
-#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24
-
-/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28
-
-/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
-} reg_iop_sw_spu_rw_bus_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32
-
-/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
-
-/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 1;
- unsigned int byte1 : 1;
- unsigned int byte2 : 1;
- unsigned int byte3 : 1;
- unsigned int dummy1 : 28;
-} reg_iop_sw_spu_rw_bus_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
-
-/* Register r_bus_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_bus_in;
-#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 32;
-} reg_iop_sw_spu_rw_gio_oe_set_mask;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-typedef unsigned int reg_iop_sw_spu_r_gio_in;
-#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64
-
-/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
-
-/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
-
-/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte0 : 8;
- unsigned int byte1 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
-
-/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int byte2 : 8;
- unsigned int byte3 : 8;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_bus_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
-#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int val : 16;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
-#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
-#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
-#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_cpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int trigger_grp0 : 1;
- unsigned int trigger_grp1 : 1;
- unsigned int trigger_grp2 : 1;
- unsigned int trigger_grp3 : 1;
- unsigned int trigger_grp4 : 1;
- unsigned int trigger_grp5 : 1;
- unsigned int trigger_grp6 : 1;
- unsigned int trigger_grp7 : 1;
- unsigned int timer_grp0 : 1;
- unsigned int timer_grp1 : 1;
- unsigned int fifo_out : 1;
- unsigned int fifo_out_extra : 1;
- unsigned int fifo_in : 1;
- unsigned int fifo_in_extra : 1;
- unsigned int dmc_out : 1;
- unsigned int dmc_in : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_hw_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_rw_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
-#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-typedef struct {
- unsigned int intr0 : 1;
- unsigned int intr1 : 1;
- unsigned int intr2 : 1;
- unsigned int intr3 : 1;
- unsigned int intr4 : 1;
- unsigned int intr5 : 1;
- unsigned int intr6 : 1;
- unsigned int intr7 : 1;
- unsigned int intr8 : 1;
- unsigned int intr9 : 1;
- unsigned int intr10 : 1;
- unsigned int intr11 : 1;
- unsigned int intr12 : 1;
- unsigned int intr13 : 1;
- unsigned int intr14 : 1;
- unsigned int intr15 : 1;
- unsigned int dummy1 : 16;
-} reg_iop_sw_spu_r_mpu_intr;
-#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132
-
-
-/* Constants */
-enum {
- regk_iop_sw_spu_copy = 0x00000000,
- regk_iop_sw_spu_no = 0x00000000,
- regk_iop_sw_spu_nop = 0x00000000,
- regk_iop_sw_spu_rd = 0x00000002,
- regk_iop_sw_spu_reg_copy = 0x00000001,
- regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
- regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
- regk_iop_sw_spu_set = 0x00000001,
- regk_iop_sw_spu_wr = 0x00000003,
- regk_iop_sw_spu_yes = 0x00000001
-};
-#endif /* __iop_sw_spu_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h
deleted file mode 100644
index d944c6ce5f9b..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_h
-#define __iop_version_defs_h
-
-/*
- * This file is autogenerated from
- * file: iop_version.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope iop_version */
-
-/* Register r_version, scope iop_version, type r */
-typedef struct {
- unsigned int nr : 8;
- unsigned int dummy1 : 24;
-} reg_iop_version_r_version;
-#define REG_RD_ADDR_iop_version_r_version 0
-
-
-/* Constants */
-enum {
- regk_iop_version_v2_0 = 0x00000002
-};
-#endif /* __iop_version_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h
deleted file mode 100644
index 5c72116f1067..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/l2cache_defs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __l2cache_defs_h
-#define __l2cache_defs_h
-
-/*
- * This file is autogenerated from
- * file: l2cache.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope l2cache */
-
-/* Register rw_cfg, scope l2cache, type rw */
-typedef struct {
- unsigned int en : 1;
- unsigned int dummy1 : 31;
-} reg_l2cache_rw_cfg;
-#define REG_RD_ADDR_l2cache_rw_cfg 0
-#define REG_WR_ADDR_l2cache_rw_cfg 0
-
-/* Register rw_ctrl, scope l2cache, type rw */
-typedef struct {
- unsigned int dummy1 : 7;
- unsigned int cbase : 9;
- unsigned int dummy2 : 4;
- unsigned int csize : 10;
- unsigned int dummy3 : 2;
-} reg_l2cache_rw_ctrl;
-#define REG_RD_ADDR_l2cache_rw_ctrl 4
-#define REG_WR_ADDR_l2cache_rw_ctrl 4
-
-/* Register rw_idxop, scope l2cache, type rw */
-typedef struct {
- unsigned int idx : 10;
- unsigned int dummy1 : 14;
- unsigned int way : 3;
- unsigned int dummy2 : 2;
- unsigned int cmd : 3;
-} reg_l2cache_rw_idxop;
-#define REG_RD_ADDR_l2cache_rw_idxop 8
-#define REG_WR_ADDR_l2cache_rw_idxop 8
-
-/* Register rw_addrop_addr, scope l2cache, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_l2cache_rw_addrop_addr;
-#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
-#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
-
-/* Register rw_addrop_ctrl, scope l2cache, type rw */
-typedef struct {
- unsigned int size : 16;
- unsigned int dummy1 : 13;
- unsigned int cmd : 3;
-} reg_l2cache_rw_addrop_ctrl;
-#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
-#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
-
-
-/* Constants */
-enum {
- regk_l2cache_flush = 0x00000001,
- regk_l2cache_no = 0x00000000,
- regk_l2cache_rw_addrop_addr_default = 0x00000000,
- regk_l2cache_rw_addrop_ctrl_default = 0x00000000,
- regk_l2cache_rw_cfg_default = 0x00000000,
- regk_l2cache_rw_ctrl_default = 0x00000000,
- regk_l2cache_rw_idxop_default = 0x00000000,
- regk_l2cache_yes = 0x00000001
-};
-#endif /* __l2cache_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h
deleted file mode 100644
index 84f68755a75c..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_bar_defs.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_bar_defs_h
-#define __marb_bar_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_bar.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bar */
-
-#define STRIDE_marb_bar_rw_ddr2_slots 4
-/* Register rw_ddr2_slots, scope marb_bar, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_bar_rw_ddr2_slots;
-#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0
-#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0
-
-/* Register rw_h264_rd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_h264_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256
-#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256
-
-/* Register rw_h264_wr_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_h264_wr_burst;
-#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260
-#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260
-
-/* Register rw_ccd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_ccd_burst;
-#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264
-#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264
-
-/* Register rw_vin_wr_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_vin_wr_burst;
-#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268
-#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268
-
-/* Register rw_vin_rd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_vin_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272
-#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272
-
-/* Register rw_sclr_rd_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_sclr_rd_burst;
-#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276
-#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276
-
-/* Register rw_vout_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_vout_burst;
-#define REG_RD_ADDR_marb_bar_rw_vout_burst 280
-#define REG_WR_ADDR_marb_bar_rw_vout_burst 280
-
-/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_sclr_fifo_burst;
-#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284
-#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284
-
-/* Register rw_l2cache_burst, scope marb_bar, type rw */
-typedef struct {
- unsigned int ddr2_bsize : 2;
- unsigned int dummy1 : 30;
-} reg_marb_bar_rw_l2cache_burst;
-#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288
-#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288
-
-/* Register rw_intr_mask, scope marb_bar, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_rw_intr_mask;
-#define REG_RD_ADDR_marb_bar_rw_intr_mask 292
-#define REG_WR_ADDR_marb_bar_rw_intr_mask 292
-
-/* Register rw_ack_intr, scope marb_bar, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_rw_ack_intr;
-#define REG_RD_ADDR_marb_bar_rw_ack_intr 296
-#define REG_WR_ADDR_marb_bar_rw_ack_intr 296
-
-/* Register r_intr, scope marb_bar, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_r_intr;
-#define REG_RD_ADDR_marb_bar_r_intr 300
-
-/* Register r_masked_intr, scope marb_bar, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_bar_r_masked_intr;
-#define REG_RD_ADDR_marb_bar_r_masked_intr 304
-
-/* Register rw_stop_mask, scope marb_bar, type rw */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_rw_stop_mask;
-#define REG_RD_ADDR_marb_bar_rw_stop_mask 308
-#define REG_WR_ADDR_marb_bar_rw_stop_mask 308
-
-/* Register r_stopped, scope marb_bar, type r */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_r_stopped;
-#define REG_RD_ADDR_marb_bar_r_stopped 312
-
-/* Register rw_no_snoop, scope marb_bar, type rw */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_rw_no_snoop;
-#define REG_RD_ADDR_marb_bar_rw_no_snoop 576
-#define REG_WR_ADDR_marb_bar_rw_no_snoop 576
-
-
-/* Constants */
-enum {
- regk_marb_bar_ccd = 0x00000002,
- regk_marb_bar_h264_rd = 0x00000000,
- regk_marb_bar_h264_wr = 0x00000001,
- regk_marb_bar_l2cache = 0x00000008,
- regk_marb_bar_no = 0x00000000,
- regk_marb_bar_r_stopped_default = 0x00000000,
- regk_marb_bar_rw_ccd_burst_default = 0x00000000,
- regk_marb_bar_rw_ddr2_slots_default = 0x00000000,
- regk_marb_bar_rw_ddr2_slots_size = 0x00000040,
- regk_marb_bar_rw_h264_rd_burst_default = 0x00000000,
- regk_marb_bar_rw_h264_wr_burst_default = 0x00000000,
- regk_marb_bar_rw_intr_mask_default = 0x00000000,
- regk_marb_bar_rw_l2cache_burst_default = 0x00000000,
- regk_marb_bar_rw_no_snoop_default = 0x00000000,
- regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000,
- regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000,
- regk_marb_bar_rw_stop_mask_default = 0x00000000,
- regk_marb_bar_rw_vin_rd_burst_default = 0x00000000,
- regk_marb_bar_rw_vin_wr_burst_default = 0x00000000,
- regk_marb_bar_rw_vout_burst_default = 0x00000000,
- regk_marb_bar_sclr_fifo = 0x00000007,
- regk_marb_bar_sclr_rd = 0x00000005,
- regk_marb_bar_vin_rd = 0x00000004,
- regk_marb_bar_vin_wr = 0x00000003,
- regk_marb_bar_vout = 0x00000006,
- regk_marb_bar_yes = 0x00000001
-};
-#endif /* __marb_bar_defs_h */
-#ifndef __marb_bar_bp_defs_h
-#define __marb_bar_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_bar.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bar_bp */
-
-/* Register rw_first_addr, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bar_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bar_bp_rw_op;
-#define REG_RD_ADDR_marb_bar_bp_rw_op 8
-#define REG_WR_ADDR_marb_bar_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bar_bp, type rw */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_bp_rw_clients;
-#define REG_RD_ADDR_marb_bar_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bar_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bar_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bar_bp_rw_options;
-#define REG_RD_ADDR_marb_bar_bp_rw_options 16
-#define REG_WR_ADDR_marb_bar_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bar_bp, type r */
-typedef unsigned int reg_marb_bar_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bar_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bar_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bar_bp, type r */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bar_bp, type r */
-typedef struct {
- unsigned int h264_rd : 1;
- unsigned int h264_wr : 1;
- unsigned int ccd : 1;
- unsigned int vin_wr : 1;
- unsigned int vin_rd : 1;
- unsigned int sclr_rd : 1;
- unsigned int vout : 1;
- unsigned int sclr_fifo : 1;
- unsigned int l2cache : 1;
- unsigned int dummy1 : 23;
-} reg_marb_bar_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bar_bp, type r */
-typedef unsigned int reg_marb_bar_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bar_bp, type rw */
-typedef unsigned int reg_marb_bar_bp_rw_ack;
-#define REG_RD_ADDR_marb_bar_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bar_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bar_bp_no = 0x00000000,
- regk_marb_bar_bp_rw_op_default = 0x00000000,
- regk_marb_bar_bp_rw_options_default = 0x00000000,
- regk_marb_bar_bp_yes = 0x00000001
-};
-#endif /* __marb_bar_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h
deleted file mode 100644
index 13539bc5d613..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/marb_foo_defs.h
+++ /dev/null
@@ -1,627 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_foo_defs_h
-#define __marb_foo_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_foo.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_foo */
-
-#define STRIDE_marb_foo_rw_intm_slots 4
-/* Register rw_intm_slots, scope marb_foo, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_intm_slots;
-#define REG_RD_ADDR_marb_foo_rw_intm_slots 0
-#define REG_WR_ADDR_marb_foo_rw_intm_slots 0
-
-#define STRIDE_marb_foo_rw_l2_slots 4
-/* Register rw_l2_slots, scope marb_foo, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_l2_slots;
-#define REG_RD_ADDR_marb_foo_rw_l2_slots 256
-#define REG_WR_ADDR_marb_foo_rw_l2_slots 256
-
-#define STRIDE_marb_foo_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb_foo, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_regs_slots;
-#define REG_RD_ADDR_marb_foo_rw_regs_slots 512
-#define REG_WR_ADDR_marb_foo_rw_regs_slots 512
-
-/* Register rw_sclr_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_sclr_burst;
-#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528
-#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528
-
-/* Register rw_dma0_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma0_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532
-#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532
-
-/* Register rw_dma1_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma1_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536
-#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536
-
-/* Register rw_dma2_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma2_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540
-#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540
-
-/* Register rw_dma3_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma3_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544
-#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544
-
-/* Register rw_dma4_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma4_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548
-#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548
-
-/* Register rw_dma5_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma5_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552
-#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552
-
-/* Register rw_dma6_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma6_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556
-#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556
-
-/* Register rw_dma7_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma7_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560
-#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560
-
-/* Register rw_dma9_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma9_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564
-#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564
-
-/* Register rw_dma11_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_dma11_burst;
-#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568
-#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568
-
-/* Register rw_cpui_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_cpui_burst;
-#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572
-#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572
-
-/* Register rw_cpud_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_cpud_burst;
-#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576
-#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576
-
-/* Register rw_iop_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_iop_burst;
-#define REG_RD_ADDR_marb_foo_rw_iop_burst 580
-#define REG_WR_ADDR_marb_foo_rw_iop_burst 580
-
-/* Register rw_ccdstat_burst, scope marb_foo, type rw */
-typedef struct {
- unsigned int intm_bsize : 2;
- unsigned int l2_bsize : 2;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_ccdstat_burst;
-#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584
-#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584
-
-/* Register rw_intr_mask, scope marb_foo, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_intr_mask;
-#define REG_RD_ADDR_marb_foo_rw_intr_mask 588
-#define REG_WR_ADDR_marb_foo_rw_intr_mask 588
-
-/* Register rw_ack_intr, scope marb_foo, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_rw_ack_intr;
-#define REG_RD_ADDR_marb_foo_rw_ack_intr 592
-#define REG_WR_ADDR_marb_foo_rw_ack_intr 592
-
-/* Register r_intr, scope marb_foo, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_r_intr;
-#define REG_RD_ADDR_marb_foo_r_intr 596
-
-/* Register r_masked_intr, scope marb_foo, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_foo_r_masked_intr;
-#define REG_RD_ADDR_marb_foo_r_masked_intr 600
-
-/* Register rw_stop_mask, scope marb_foo, type rw */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_rw_stop_mask;
-#define REG_RD_ADDR_marb_foo_rw_stop_mask 604
-#define REG_WR_ADDR_marb_foo_rw_stop_mask 604
-
-/* Register r_stopped, scope marb_foo, type r */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_r_stopped;
-#define REG_RD_ADDR_marb_foo_r_stopped 608
-
-/* Register rw_no_snoop, scope marb_foo, type rw */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_rw_no_snoop;
-#define REG_RD_ADDR_marb_foo_rw_no_snoop 896
-#define REG_WR_ADDR_marb_foo_rw_no_snoop 896
-
-/* Register rw_no_snoop_rq, scope marb_foo, type rw */
-typedef struct {
- unsigned int dummy1 : 11;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int dummy2 : 19;
-} reg_marb_foo_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900
-#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900
-
-
-/* Constants */
-enum {
- regk_marb_foo_ccdstat = 0x0000000e,
- regk_marb_foo_cpud = 0x0000000c,
- regk_marb_foo_cpui = 0x0000000b,
- regk_marb_foo_dma0 = 0x00000001,
- regk_marb_foo_dma1 = 0x00000002,
- regk_marb_foo_dma11 = 0x0000000a,
- regk_marb_foo_dma2 = 0x00000003,
- regk_marb_foo_dma3 = 0x00000004,
- regk_marb_foo_dma4 = 0x00000005,
- regk_marb_foo_dma5 = 0x00000006,
- regk_marb_foo_dma6 = 0x00000007,
- regk_marb_foo_dma7 = 0x00000008,
- regk_marb_foo_dma9 = 0x00000009,
- regk_marb_foo_iop = 0x0000000d,
- regk_marb_foo_no = 0x00000000,
- regk_marb_foo_r_stopped_default = 0x00000000,
- regk_marb_foo_rw_ccdstat_burst_default = 0x00000000,
- regk_marb_foo_rw_cpud_burst_default = 0x00000000,
- regk_marb_foo_rw_cpui_burst_default = 0x00000000,
- regk_marb_foo_rw_dma0_burst_default = 0x00000000,
- regk_marb_foo_rw_dma11_burst_default = 0x00000000,
- regk_marb_foo_rw_dma1_burst_default = 0x00000000,
- regk_marb_foo_rw_dma2_burst_default = 0x00000000,
- regk_marb_foo_rw_dma3_burst_default = 0x00000000,
- regk_marb_foo_rw_dma4_burst_default = 0x00000000,
- regk_marb_foo_rw_dma5_burst_default = 0x00000000,
- regk_marb_foo_rw_dma6_burst_default = 0x00000000,
- regk_marb_foo_rw_dma7_burst_default = 0x00000000,
- regk_marb_foo_rw_dma9_burst_default = 0x00000000,
- regk_marb_foo_rw_intm_slots_default = 0x00000000,
- regk_marb_foo_rw_intm_slots_size = 0x00000040,
- regk_marb_foo_rw_intr_mask_default = 0x00000000,
- regk_marb_foo_rw_iop_burst_default = 0x00000000,
- regk_marb_foo_rw_l2_slots_default = 0x00000000,
- regk_marb_foo_rw_l2_slots_size = 0x00000040,
- regk_marb_foo_rw_no_snoop_default = 0x00000000,
- regk_marb_foo_rw_no_snoop_rq_default = 0x00000000,
- regk_marb_foo_rw_regs_slots_default = 0x00000000,
- regk_marb_foo_rw_regs_slots_size = 0x00000004,
- regk_marb_foo_rw_sclr_burst_default = 0x00000000,
- regk_marb_foo_rw_stop_mask_default = 0x00000000,
- regk_marb_foo_sclr = 0x00000000,
- regk_marb_foo_yes = 0x00000001
-};
-#endif /* __marb_foo_defs_h */
-#ifndef __marb_foo_bp_defs_h
-#define __marb_foo_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: marb_foo.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_foo_bp */
-
-/* Register rw_first_addr, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_foo_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_foo_bp_rw_op;
-#define REG_RD_ADDR_marb_foo_bp_rw_op 8
-#define REG_WR_ADDR_marb_foo_bp_rw_op 8
-
-/* Register rw_clients, scope marb_foo_bp, type rw */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_bp_rw_clients;
-#define REG_RD_ADDR_marb_foo_bp_rw_clients 12
-#define REG_WR_ADDR_marb_foo_bp_rw_clients 12
-
-/* Register rw_options, scope marb_foo_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_foo_bp_rw_options;
-#define REG_RD_ADDR_marb_foo_bp_rw_options 16
-#define REG_WR_ADDR_marb_foo_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_foo_bp, type r */
-typedef unsigned int reg_marb_foo_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_foo_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_foo_bp_r_brk_op;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_foo_bp, type r */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_foo_bp, type r */
-typedef struct {
- unsigned int sclr : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma9 : 1;
- unsigned int dma11 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int ccdstat : 1;
- unsigned int dummy1 : 17;
-} reg_marb_foo_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_foo_bp, type r */
-typedef unsigned int reg_marb_foo_bp_r_brk_size;
-#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_foo_bp, type rw */
-typedef unsigned int reg_marb_foo_bp_rw_ack;
-#define REG_RD_ADDR_marb_foo_bp_rw_ack 40
-#define REG_WR_ADDR_marb_foo_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_foo_bp_no = 0x00000000,
- regk_marb_foo_bp_rw_op_default = 0x00000000,
- regk_marb_foo_bp_rw_options_default = 0x00000000,
- regk_marb_foo_bp_yes = 0x00000001
-};
-#endif /* __marb_foo_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h
deleted file mode 100644
index d604042a52bf..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pinmux_defs.h
+++ /dev/null
@@ -1,313 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_h
-#define __pinmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: pinmux.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pinmux */
-
-/* Register rw_hwprot, scope pinmux, type rw */
-typedef struct {
- unsigned int eth : 1;
- unsigned int eth_mdio : 1;
- unsigned int geth : 1;
- unsigned int tg : 1;
- unsigned int tg_clk : 1;
- unsigned int vout : 1;
- unsigned int vout_sync : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int ser4 : 1;
- unsigned int sser : 1;
- unsigned int pwm0 : 1;
- unsigned int pwm1 : 1;
- unsigned int pwm2 : 1;
- unsigned int timer0 : 1;
- unsigned int timer1 : 1;
- unsigned int pio : 1;
- unsigned int i2c0 : 1;
- unsigned int i2c1 : 1;
- unsigned int i2c1_sda1 : 1;
- unsigned int i2c1_sda2 : 1;
- unsigned int i2c1_sda3 : 1;
- unsigned int i2c1_sen : 1;
- unsigned int dummy1 : 8;
-} reg_pinmux_rw_hwprot;
-#define REG_RD_ADDR_pinmux_rw_hwprot 0
-#define REG_WR_ADDR_pinmux_rw_hwprot 0
-
-/* Register rw_gio_pa, scope pinmux, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int pa8 : 1;
- unsigned int pa9 : 1;
- unsigned int pa10 : 1;
- unsigned int pa11 : 1;
- unsigned int pa12 : 1;
- unsigned int pa13 : 1;
- unsigned int pa14 : 1;
- unsigned int pa15 : 1;
- unsigned int pa16 : 1;
- unsigned int pa17 : 1;
- unsigned int pa18 : 1;
- unsigned int pa19 : 1;
- unsigned int pa20 : 1;
- unsigned int pa21 : 1;
- unsigned int pa22 : 1;
- unsigned int pa23 : 1;
- unsigned int pa24 : 1;
- unsigned int pa25 : 1;
- unsigned int pa26 : 1;
- unsigned int pa27 : 1;
- unsigned int pa28 : 1;
- unsigned int pa29 : 1;
- unsigned int pa30 : 1;
- unsigned int pa31 : 1;
-} reg_pinmux_rw_gio_pa;
-#define REG_RD_ADDR_pinmux_rw_gio_pa 4
-#define REG_WR_ADDR_pinmux_rw_gio_pa 4
-
-/* Register rw_gio_pb, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int pb8 : 1;
- unsigned int pb9 : 1;
- unsigned int pb10 : 1;
- unsigned int pb11 : 1;
- unsigned int pb12 : 1;
- unsigned int pb13 : 1;
- unsigned int pb14 : 1;
- unsigned int pb15 : 1;
- unsigned int pb16 : 1;
- unsigned int pb17 : 1;
- unsigned int pb18 : 1;
- unsigned int pb19 : 1;
- unsigned int pb20 : 1;
- unsigned int pb21 : 1;
- unsigned int pb22 : 1;
- unsigned int pb23 : 1;
- unsigned int pb24 : 1;
- unsigned int pb25 : 1;
- unsigned int pb26 : 1;
- unsigned int pb27 : 1;
- unsigned int pb28 : 1;
- unsigned int pb29 : 1;
- unsigned int pb30 : 1;
- unsigned int pb31 : 1;
-} reg_pinmux_rw_gio_pb;
-#define REG_RD_ADDR_pinmux_rw_gio_pb 8
-#define REG_WR_ADDR_pinmux_rw_gio_pb 8
-
-/* Register rw_gio_pc, scope pinmux, type rw */
-typedef struct {
- unsigned int pc0 : 1;
- unsigned int pc1 : 1;
- unsigned int pc2 : 1;
- unsigned int pc3 : 1;
- unsigned int pc4 : 1;
- unsigned int pc5 : 1;
- unsigned int pc6 : 1;
- unsigned int pc7 : 1;
- unsigned int pc8 : 1;
- unsigned int pc9 : 1;
- unsigned int pc10 : 1;
- unsigned int pc11 : 1;
- unsigned int pc12 : 1;
- unsigned int pc13 : 1;
- unsigned int pc14 : 1;
- unsigned int pc15 : 1;
- unsigned int dummy1 : 16;
-} reg_pinmux_rw_gio_pc;
-#define REG_RD_ADDR_pinmux_rw_gio_pc 12
-#define REG_WR_ADDR_pinmux_rw_gio_pc 12
-
-/* Register rw_iop_pa, scope pinmux, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int pa8 : 1;
- unsigned int pa9 : 1;
- unsigned int pa10 : 1;
- unsigned int pa11 : 1;
- unsigned int pa12 : 1;
- unsigned int pa13 : 1;
- unsigned int pa14 : 1;
- unsigned int pa15 : 1;
- unsigned int pa16 : 1;
- unsigned int pa17 : 1;
- unsigned int pa18 : 1;
- unsigned int pa19 : 1;
- unsigned int pa20 : 1;
- unsigned int pa21 : 1;
- unsigned int pa22 : 1;
- unsigned int pa23 : 1;
- unsigned int pa24 : 1;
- unsigned int pa25 : 1;
- unsigned int pa26 : 1;
- unsigned int pa27 : 1;
- unsigned int pa28 : 1;
- unsigned int pa29 : 1;
- unsigned int pa30 : 1;
- unsigned int pa31 : 1;
-} reg_pinmux_rw_iop_pa;
-#define REG_RD_ADDR_pinmux_rw_iop_pa 16
-#define REG_WR_ADDR_pinmux_rw_iop_pa 16
-
-/* Register rw_iop_pb, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int dummy1 : 24;
-} reg_pinmux_rw_iop_pb;
-#define REG_RD_ADDR_pinmux_rw_iop_pb 20
-#define REG_WR_ADDR_pinmux_rw_iop_pb 20
-
-/* Register rw_iop_pio, scope pinmux, type rw */
-typedef struct {
- unsigned int d0 : 1;
- unsigned int d1 : 1;
- unsigned int d2 : 1;
- unsigned int d3 : 1;
- unsigned int d4 : 1;
- unsigned int d5 : 1;
- unsigned int d6 : 1;
- unsigned int d7 : 1;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pinmux_rw_iop_pio;
-#define REG_RD_ADDR_pinmux_rw_iop_pio 24
-#define REG_WR_ADDR_pinmux_rw_iop_pio 24
-
-/* Register rw_iop_usb, scope pinmux, type rw */
-typedef struct {
- unsigned int usb0 : 1;
- unsigned int dummy1 : 31;
-} reg_pinmux_rw_iop_usb;
-#define REG_RD_ADDR_pinmux_rw_iop_usb 28
-#define REG_WR_ADDR_pinmux_rw_iop_usb 28
-
-
-/* Constants */
-enum {
- regk_pinmux_no = 0x00000000,
- regk_pinmux_rw_gio_pa_default = 0x00000000,
- regk_pinmux_rw_gio_pb_default = 0x00000000,
- regk_pinmux_rw_gio_pc_default = 0x00000000,
- regk_pinmux_rw_hwprot_default = 0x00000000,
- regk_pinmux_rw_iop_pa_default = 0x00000000,
- regk_pinmux_rw_iop_pb_default = 0x00000000,
- regk_pinmux_rw_iop_pio_default = 0x00000000,
- regk_pinmux_rw_iop_usb_default = 0x00000001,
- regk_pinmux_yes = 0x00000001
-};
-#endif /* __pinmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h
deleted file mode 100644
index 348e39f419e0..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/pio_defs.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pio_defs_h
-#define __pio_defs_h
-
-/*
- * This file is autogenerated from
- * file: pio.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pio */
-
-/* Register rw_data, scope pio, type rw */
-typedef unsigned int reg_pio_rw_data;
-#define REG_RD_ADDR_pio_rw_data 64
-#define REG_WR_ADDR_pio_rw_data 64
-
-/* Register rw_io_access0, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access0;
-#define REG_RD_ADDR_pio_rw_io_access0 0
-#define REG_WR_ADDR_pio_rw_io_access0 0
-
-/* Register rw_io_access1, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access1;
-#define REG_RD_ADDR_pio_rw_io_access1 4
-#define REG_WR_ADDR_pio_rw_io_access1 4
-
-/* Register rw_io_access2, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access2;
-#define REG_RD_ADDR_pio_rw_io_access2 8
-#define REG_WR_ADDR_pio_rw_io_access2 8
-
-/* Register rw_io_access3, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access3;
-#define REG_RD_ADDR_pio_rw_io_access3 12
-#define REG_WR_ADDR_pio_rw_io_access3 12
-
-/* Register rw_io_access4, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access4;
-#define REG_RD_ADDR_pio_rw_io_access4 16
-#define REG_WR_ADDR_pio_rw_io_access4 16
-
-/* Register rw_io_access5, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access5;
-#define REG_RD_ADDR_pio_rw_io_access5 20
-#define REG_WR_ADDR_pio_rw_io_access5 20
-
-/* Register rw_io_access6, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access6;
-#define REG_RD_ADDR_pio_rw_io_access6 24
-#define REG_WR_ADDR_pio_rw_io_access6 24
-
-/* Register rw_io_access7, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access7;
-#define REG_RD_ADDR_pio_rw_io_access7 28
-#define REG_WR_ADDR_pio_rw_io_access7 28
-
-/* Register rw_io_access8, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access8;
-#define REG_RD_ADDR_pio_rw_io_access8 32
-#define REG_WR_ADDR_pio_rw_io_access8 32
-
-/* Register rw_io_access9, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access9;
-#define REG_RD_ADDR_pio_rw_io_access9 36
-#define REG_WR_ADDR_pio_rw_io_access9 36
-
-/* Register rw_io_access10, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access10;
-#define REG_RD_ADDR_pio_rw_io_access10 40
-#define REG_WR_ADDR_pio_rw_io_access10 40
-
-/* Register rw_io_access11, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access11;
-#define REG_RD_ADDR_pio_rw_io_access11 44
-#define REG_WR_ADDR_pio_rw_io_access11 44
-
-/* Register rw_io_access12, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access12;
-#define REG_RD_ADDR_pio_rw_io_access12 48
-#define REG_WR_ADDR_pio_rw_io_access12 48
-
-/* Register rw_io_access13, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access13;
-#define REG_RD_ADDR_pio_rw_io_access13 52
-#define REG_WR_ADDR_pio_rw_io_access13 52
-
-/* Register rw_io_access14, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access14;
-#define REG_RD_ADDR_pio_rw_io_access14 56
-#define REG_WR_ADDR_pio_rw_io_access14 56
-
-/* Register rw_io_access15, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_pio_rw_io_access15;
-#define REG_RD_ADDR_pio_rw_io_access15 60
-#define REG_WR_ADDR_pio_rw_io_access15 60
-
-/* Register rw_ce0_cfg, scope pio, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int mode : 2;
- unsigned int dummy1 : 16;
-} reg_pio_rw_ce0_cfg;
-#define REG_RD_ADDR_pio_rw_ce0_cfg 68
-#define REG_WR_ADDR_pio_rw_ce0_cfg 68
-
-/* Register rw_ce1_cfg, scope pio, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int mode : 2;
- unsigned int dummy1 : 16;
-} reg_pio_rw_ce1_cfg;
-#define REG_RD_ADDR_pio_rw_ce1_cfg 72
-#define REG_WR_ADDR_pio_rw_ce1_cfg 72
-
-/* Register rw_ce2_cfg, scope pio, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int mode : 2;
- unsigned int dummy1 : 16;
-} reg_pio_rw_ce2_cfg;
-#define REG_RD_ADDR_pio_rw_ce2_cfg 76
-#define REG_WR_ADDR_pio_rw_ce2_cfg 76
-
-/* Register rw_dout, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_rw_dout;
-#define REG_RD_ADDR_pio_rw_dout 80
-#define REG_WR_ADDR_pio_rw_dout 80
-
-/* Register rw_oe, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_rw_oe;
-#define REG_RD_ADDR_pio_rw_oe 84
-#define REG_WR_ADDR_pio_rw_oe 84
-
-/* Register rw_man_ctrl, scope pio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_rw_man_ctrl;
-#define REG_RD_ADDR_pio_rw_man_ctrl 88
-#define REG_WR_ADDR_pio_rw_man_ctrl 88
-
-/* Register r_din, scope pio, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int rd_n : 1;
- unsigned int wr_n : 1;
- unsigned int a0 : 1;
- unsigned int a1 : 1;
- unsigned int ce0_n : 1;
- unsigned int ce1_n : 1;
- unsigned int ce2_n : 1;
- unsigned int rdy : 1;
- unsigned int dummy1 : 16;
-} reg_pio_r_din;
-#define REG_RD_ADDR_pio_r_din 92
-
-/* Register r_stat, scope pio, type r */
-typedef struct {
- unsigned int busy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_r_stat;
-#define REG_RD_ADDR_pio_r_stat 96
-
-/* Register rw_intr_mask, scope pio, type rw */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_rw_intr_mask;
-#define REG_RD_ADDR_pio_rw_intr_mask 100
-#define REG_WR_ADDR_pio_rw_intr_mask 100
-
-/* Register rw_ack_intr, scope pio, type rw */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_rw_ack_intr;
-#define REG_RD_ADDR_pio_rw_ack_intr 104
-#define REG_WR_ADDR_pio_rw_ack_intr 104
-
-/* Register r_intr, scope pio, type r */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_r_intr;
-#define REG_RD_ADDR_pio_r_intr 108
-
-/* Register r_masked_intr, scope pio, type r */
-typedef struct {
- unsigned int rdy : 1;
- unsigned int dummy1 : 31;
-} reg_pio_r_masked_intr;
-#define REG_RD_ADDR_pio_r_masked_intr 112
-
-
-/* Constants */
-enum {
- regk_pio_a2 = 0x00000003,
- regk_pio_no = 0x00000000,
- regk_pio_normal = 0x00000000,
- regk_pio_rd = 0x00000001,
- regk_pio_rw_ce0_cfg_default = 0x00000000,
- regk_pio_rw_ce1_cfg_default = 0x00000000,
- regk_pio_rw_ce2_cfg_default = 0x00000000,
- regk_pio_rw_intr_mask_default = 0x00000000,
- regk_pio_rw_man_ctrl_default = 0x00000000,
- regk_pio_rw_oe_default = 0x00000000,
- regk_pio_wr = 0x00000002,
- regk_pio_wr_ce2 = 0x00000003,
- regk_pio_yes = 0x00000001,
- regk_pio_yes_all = 0x000000ff
-};
-#endif /* __pio_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h
deleted file mode 100644
index 04ef87d42513..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/reg_map.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- * file: reg.rmap
- *
- * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-typedef enum {
- regi_ccd = 0xb0000000,
- regi_ccd_top = 0xb0000000,
- regi_ccd_dp = 0xb0000400,
- regi_ccd_stat = 0xb0000800,
- regi_ccd_tg = 0xb0001000,
- regi_cfg = 0xb0002000,
- regi_clkgen = 0xb0004000,
- regi_ddr2_ctrl = 0xb0006000,
- regi_dma0 = 0xb0008000,
- regi_dma1 = 0xb000a000,
- regi_dma11 = 0xb000c000,
- regi_dma2 = 0xb000e000,
- regi_dma3 = 0xb0010000,
- regi_dma4 = 0xb0012000,
- regi_dma5 = 0xb0014000,
- regi_dma6 = 0xb0016000,
- regi_dma7 = 0xb0018000,
- regi_dma9 = 0xb001a000,
- regi_eth = 0xb001c000,
- regi_gio = 0xb0020000,
- regi_h264 = 0xb0022000,
- regi_hist = 0xb0026000,
- regi_iop = 0xb0028000,
- regi_iop_version = 0xb0028000,
- regi_iop_fifo_in_extra = 0xb0028040,
- regi_iop_fifo_out_extra = 0xb0028080,
- regi_iop_trigger_grp0 = 0xb00280c0,
- regi_iop_trigger_grp1 = 0xb0028100,
- regi_iop_trigger_grp2 = 0xb0028140,
- regi_iop_trigger_grp3 = 0xb0028180,
- regi_iop_trigger_grp4 = 0xb00281c0,
- regi_iop_trigger_grp5 = 0xb0028200,
- regi_iop_trigger_grp6 = 0xb0028240,
- regi_iop_trigger_grp7 = 0xb0028280,
- regi_iop_crc_par = 0xb0028300,
- regi_iop_dmc_in = 0xb0028380,
- regi_iop_dmc_out = 0xb0028400,
- regi_iop_fifo_in = 0xb0028480,
- regi_iop_fifo_out = 0xb0028500,
- regi_iop_scrc_in = 0xb0028580,
- regi_iop_scrc_out = 0xb0028600,
- regi_iop_timer_grp0 = 0xb0028680,
- regi_iop_timer_grp1 = 0xb0028700,
- regi_iop_sap_in = 0xb0028800,
- regi_iop_sap_out = 0xb0028900,
- regi_iop_spu = 0xb0028a00,
- regi_iop_sw_cfg = 0xb0028b00,
- regi_iop_sw_cpu = 0xb0028c00,
- regi_iop_sw_mpu = 0xb0028d00,
- regi_iop_sw_spu = 0xb0028e00,
- regi_iop_mpu = 0xb0029000,
- regi_irq = 0xb002a000,
- regi_irq2 = 0xb006a000,
- regi_jpeg = 0xb002c000,
- regi_l2cache = 0xb0030000,
- regi_marb_bar = 0xb0032000,
- regi_marb_bar_bp0 = 0xb0032140,
- regi_marb_bar_bp1 = 0xb0032180,
- regi_marb_bar_bp2 = 0xb00321c0,
- regi_marb_bar_bp3 = 0xb0032200,
- regi_marb_foo = 0xb0034000,
- regi_marb_foo_bp0 = 0xb0034280,
- regi_marb_foo_bp1 = 0xb00342c0,
- regi_marb_foo_bp2 = 0xb0034300,
- regi_marb_foo_bp3 = 0xb0034340,
- regi_pinmux = 0xb0038000,
- regi_pio = 0xb0036000,
- regi_sclr = 0xb003a000,
- regi_sclr_fifo = 0xb003c000,
- regi_ser0 = 0xb003e000,
- regi_ser1 = 0xb0040000,
- regi_ser2 = 0xb0042000,
- regi_ser3 = 0xb0044000,
- regi_ser4 = 0xb0046000,
- regi_sser = 0xb0048000,
- regi_strcop = 0xb004a000,
- regi_strdma0 = 0xb004e000,
- regi_strdma1 = 0xb0050000,
- regi_strdma2 = 0xb0052000,
- regi_strdma3 = 0xb0054000,
- regi_strdma5 = 0xb0056000,
- regi_strmux = 0xb004c000,
- regi_timer0 = 0xb0058000,
- regi_timer1 = 0xb005a000,
- regi_timer2 = 0xb006e000,
- regi_trace = 0xb005c000,
- regi_vin = 0xb005e000,
- regi_vout = 0xb0060000
-} reg_scope_instances;
-#endif /* __reg_map_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h
deleted file mode 100644
index a19955fa8d94..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/strmux_defs.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strmux_defs_h
-#define __strmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: strmux.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strmux */
-
-/* Register rw_cfg, scope strmux, type rw */
-typedef struct {
- unsigned int dma0 : 2;
- unsigned int dma1 : 2;
- unsigned int dma2 : 2;
- unsigned int dma3 : 2;
- unsigned int dma4 : 2;
- unsigned int dma5 : 2;
- unsigned int dma6 : 2;
- unsigned int dma7 : 2;
- unsigned int dummy1 : 2;
- unsigned int dma9 : 2;
- unsigned int dummy2 : 2;
- unsigned int dma11 : 2;
- unsigned int dummy3 : 8;
-} reg_strmux_rw_cfg;
-#define REG_RD_ADDR_strmux_rw_cfg 0
-#define REG_WR_ADDR_strmux_rw_cfg 0
-
-
-/* Constants */
-enum {
- regk_strmux_eth = 0x00000001,
- regk_strmux_h264 = 0x00000001,
- regk_strmux_iop = 0x00000001,
- regk_strmux_jpeg = 0x00000001,
- regk_strmux_off = 0x00000000,
- regk_strmux_rw_cfg_default = 0x00000000,
- regk_strmux_ser0 = 0x00000002,
- regk_strmux_ser1 = 0x00000002,
- regk_strmux_ser2 = 0x00000002,
- regk_strmux_ser3 = 0x00000002,
- regk_strmux_ser4 = 0x00000002,
- regk_strmux_sser = 0x00000001,
- regk_strmux_strcop = 0x00000001
-};
-#endif /* __strmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h
deleted file mode 100644
index de849a6362f6..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/timer_defs.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_h
-#define __timer_defs_h
-
-/*
- * This file is autogenerated from
- * file: timer.r
- *
- * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope timer */
-
-/* Register rw_tmr0_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr0_div;
-#define REG_RD_ADDR_timer_rw_tmr0_div 0
-#define REG_WR_ADDR_timer_rw_tmr0_div 0
-
-/* Register r_tmr0_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr0_data;
-#define REG_RD_ADDR_timer_r_tmr0_data 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr0_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
-#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr1_div;
-#define REG_RD_ADDR_timer_rw_tmr1_div 16
-#define REG_WR_ADDR_timer_rw_tmr1_div 16
-
-/* Register r_tmr1_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr1_data;
-#define REG_RD_ADDR_timer_r_tmr1_data 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr1_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
-#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_rs_cnt_data;
-#define REG_RD_ADDR_timer_rs_cnt_data 32
-
-/* Register r_cnt_data, scope timer, type r */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_r_cnt_data;
-#define REG_RD_ADDR_timer_r_cnt_data 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-typedef struct {
- unsigned int clk : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_cnt_cfg;
-#define REG_RD_ADDR_timer_rw_cnt_cfg 40
-#define REG_WR_ADDR_timer_rw_cnt_cfg 40
-
-/* Register rw_trig, scope timer, type rw */
-typedef unsigned int reg_timer_rw_trig;
-#define REG_RD_ADDR_timer_rw_trig 48
-#define REG_WR_ADDR_timer_rw_trig 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_trig_cfg;
-#define REG_RD_ADDR_timer_rw_trig_cfg 52
-#define REG_WR_ADDR_timer_rw_trig_cfg 52
-
-/* Register r_time, scope timer, type r */
-typedef unsigned int reg_timer_r_time;
-#define REG_RD_ADDR_timer_r_time 56
-
-/* Register rw_out, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_out;
-#define REG_RD_ADDR_timer_rw_out 60
-#define REG_WR_ADDR_timer_rw_out 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int key : 7;
- unsigned int dummy1 : 16;
-} reg_timer_rw_wd_ctrl;
-#define REG_RD_ADDR_timer_rw_wd_ctrl 64
-#define REG_WR_ADDR_timer_rw_wd_ctrl 64
-
-/* Register r_wd_stat, scope timer, type r */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int dummy1 : 23;
-} reg_timer_r_wd_stat;
-#define REG_RD_ADDR_timer_r_wd_stat 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_intr_mask;
-#define REG_RD_ADDR_timer_rw_intr_mask 72
-#define REG_WR_ADDR_timer_rw_intr_mask 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_ack_intr;
-#define REG_RD_ADDR_timer_rw_ack_intr 76
-#define REG_WR_ADDR_timer_rw_ack_intr 76
-
-/* Register r_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_intr;
-#define REG_RD_ADDR_timer_r_intr 80
-
-/* Register r_masked_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_masked_intr;
-#define REG_RD_ADDR_timer_r_masked_intr 84
-
-/* Register rw_test, scope timer, type rw */
-typedef struct {
- unsigned int dis : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 30;
-} reg_timer_rw_test;
-#define REG_RD_ADDR_timer_rw_test 88
-#define REG_WR_ADDR_timer_rw_test 88
-
-
-/* Constants */
-enum {
- regk_timer_ext = 0x00000001,
- regk_timer_f100 = 0x00000007,
- regk_timer_f29_493 = 0x00000004,
- regk_timer_f32 = 0x00000005,
- regk_timer_f32_768 = 0x00000006,
- regk_timer_f90 = 0x00000003,
- regk_timer_hold = 0x00000001,
- regk_timer_ld = 0x00000000,
- regk_timer_no = 0x00000000,
- regk_timer_off = 0x00000000,
- regk_timer_run = 0x00000002,
- regk_timer_rw_cnt_cfg_default = 0x00000000,
- regk_timer_rw_intr_mask_default = 0x00000000,
- regk_timer_rw_out_default = 0x00000000,
- regk_timer_rw_test_default = 0x00000000,
- regk_timer_rw_tmr0_ctrl_default = 0x00000000,
- regk_timer_rw_tmr1_ctrl_default = 0x00000000,
- regk_timer_rw_trig_cfg_default = 0x00000000,
- regk_timer_start = 0x00000001,
- regk_timer_stop = 0x00000000,
- regk_timer_time = 0x00000001,
- regk_timer_tmr0 = 0x00000002,
- regk_timer_tmr1 = 0x00000003,
- regk_timer_vclk = 0x00000002,
- regk_timer_yes = 0x00000001
-};
-#endif /* __timer_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/memmap.h b/arch/cris/include/arch-v32/mach-a3/mach/memmap.h
deleted file mode 100644
index 7b9a9a5699b2..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/memmap.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00018000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h b/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h
deleted file mode 100644
index 35e3fc97d6a3..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/pinmux.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PINMUX_H
-#define _ASM_CRIS_ARCH_PINMUX_H
-
-#define PORT_A 0
-#define PORT_B 1
-#define PORT_C 2
-
-enum pin_mode {
- pinmux_none = 0,
- pinmux_fixed,
- pinmux_gpio,
- pinmux_iop
-};
-
-enum fixed_function {
- pinmux_eth,
- pinmux_geth,
- pinmux_tg_ccd,
- pinmux_tg_cmos,
- pinmux_vout,
- pinmux_ser1,
- pinmux_ser2,
- pinmux_ser3,
- pinmux_ser4,
- pinmux_sser,
- pinmux_pio,
- pinmux_pwm0,
- pinmux_pwm1,
- pinmux_pwm2,
- pinmux_i2c0,
- pinmux_i2c1,
- pinmux_i2c1_3wire,
- pinmux_i2c1_sda1,
- pinmux_i2c1_sda2,
- pinmux_i2c1_sda3,
-};
-
-int crisv32_pinmux_init(void);
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
-int crisv32_pinmux_alloc_fixed(enum fixed_function function);
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
-void crisv32_pinmux_dump(void);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc b/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
deleted file mode 100644
index 2d52bcc96ed5..000000000000
--- a/arch/cris/include/arch-v32/mach-a3/mach/startup.inc
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef STARTUP_INC_INCLUDED
-#define STARTUP_INC_INCLUDED
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-#include <hwregs/asm/pio_defs_asm.h>
-#include <hwregs/asm/clkgen_defs_asm.h>
-#include <hwregs/asm/pinmux_defs_asm.h>
-
- .macro GIO_SET_P BITS, OUTREG
- bmi 1f ; btstq: bit -> N flag
- nop
- or.d \BITS, \OUTREG
-1:
- .endm
-
- .macro GIO_INIT
- move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
- move.d $r0, [$r1]
-
- move.d 0xFFFFFFFF, $r0
- move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
- move.d $r0, [$r1]
- move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
- move.d $r0, [$r1]
-
- ;; If eth_mdio, eth, geth bits are set in hwprot, don't
- ;; set them to gpio, as this means they have been configured
- ;; earlier and shouldn't be changed.
- move.d 0xFC000000, $r2 ; pins 25..0 are eth_mdio, eth, geth
- move.d REG_ADDR(pinmux, regi_pinmux, rw_hwprot), $r1
- move.d [$r1], $r0
- btstq REG_BIT(pinmux, rw_hwprot, eth), $r0
- GIO_SET_P 0x00FFFF00, $r2 ;; pins 8..23 are eth
- btstq REG_BIT(pinmux, rw_hwprot, eth_mdio), $r0
- GIO_SET_P 0x03000000, $r2 ;; pins 24..25 are eth_mdio
- btstq REG_BIT(pinmux, rw_hwprot, geth), $r0
- GIO_SET_P 0x000000FF, $r2 ;; pins 0..7 are geth
- move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
- move.d $r2, [$r1]
- .endm
-
- .macro START_CLOCKS
- move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1
- move.d [$r1], $r0
- or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \
- REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \
- REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0
- move.d $r0, [$r1]
- .endm
-
- .macro SETUP_WAIT_STATES
- move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0
- move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0
- move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0
- move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
- move.d $r1, [$r0]
- .endm
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h b/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h
deleted file mode 100644
index f9401a3de83c..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_ARBITER_H
-#define _ASM_CRIS_ARCH_ARBITER_H
-
-#define EXT_REGION 0
-#define INT_REGION 1
-
-typedef void (watch_callback)(void);
-
-enum {
- arbiter_all_dmas = 0x3ff,
- arbiter_cpu = 0xc00,
- arbiter_all_clients = 0x3fff
-};
-
-enum {
- arbiter_all_read = 0x55,
- arbiter_all_write = 0xaa,
- arbiter_all_accesses = 0xff
-};
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth);
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback * cb);
-int crisv32_arbiter_unwatch(int id);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/dma.h b/arch/cris/include/arch-v32/mach-fs/mach/dma.h
deleted file mode 100644
index 53a59944a48b..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/dma.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_CRIS_DMA_H
-#define _ASM_ARCH_CRIS_DMA_H
-
-/* Defines for using and allocating dma channels. */
-
-#define MAX_DMA_CHANNELS 10
-
-#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */
-#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */
-
-#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */
-#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */
-
-#define ATA_TX_DMA_NBR 2 /* ATA interface out. */
-#define ATA_RX_DMA_NBR 3 /* ATA interface in. */
-
-#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */
-#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */
-
-#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */
-#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */
-
-#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */
-#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */
-
-#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */
-#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */
-
-#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */
-#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */
-
-#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */
-#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */
-
-#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */
-#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */
-
-#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */
-#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */
-
-#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */
-#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */
-
-#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */
-#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */
-
-#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */
-#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */
-
-enum dma_owner {
- dma_eth0,
- dma_eth1,
- dma_iop0,
- dma_iop1,
- dma_ser0,
- dma_ser1,
- dma_ser2,
- dma_ser3,
- dma_sser0,
- dma_sser1,
- dma_ata,
- dma_strp,
- dma_ext0,
- dma_ext1,
- dma_ext2,
- dma_ext3
-};
-
-int crisv32_request_dma(unsigned int dmanr, const char *device_id,
- unsigned options, unsigned bandwidth,
- enum dma_owner owner);
-void crisv32_free_dma(unsigned int dmanr);
-
-/* Masks used by crisv32_request_dma options: */
-#define DMA_VERBOSE_ON_ERROR 1
-#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
-#define DMA_INT_MEM 4
-
-#endif /* _ASM_ARCH_CRIS_DMA_H */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h
deleted file mode 100644
index 092cad384b86..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_asm_h
-#define __bif_core_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp1_cfg___lw___width 6
-#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp1_cfg___ew___width 3
-#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp1_cfg___zw___width 3
-#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp1_cfg___aw___width 2
-#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp1_cfg___dw___width 2
-#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp1_cfg___ewb___width 2
-#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp1_cfg___bw___width 1
-#define reg_bif_core_rw_grp1_cfg___bw___bit 18
-#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp1_cfg___mode___width 1
-#define reg_bif_core_rw_grp1_cfg___mode___bit 21
-#define reg_bif_core_rw_grp1_cfg_offset 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp2_cfg___lw___width 6
-#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp2_cfg___ew___width 3
-#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp2_cfg___zw___width 3
-#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp2_cfg___aw___width 2
-#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp2_cfg___dw___width 2
-#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp2_cfg___ewb___width 2
-#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp2_cfg___bw___width 1
-#define reg_bif_core_rw_grp2_cfg___bw___bit 18
-#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp2_cfg___mode___width 1
-#define reg_bif_core_rw_grp2_cfg___mode___bit 21
-#define reg_bif_core_rw_grp2_cfg_offset 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp3_cfg___lw___width 6
-#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp3_cfg___ew___width 3
-#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp3_cfg___zw___width 3
-#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp3_cfg___aw___width 2
-#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp3_cfg___dw___width 2
-#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp3_cfg___ewb___width 2
-#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp3_cfg___bw___width 1
-#define reg_bif_core_rw_grp3_cfg___bw___bit 18
-#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp3_cfg___mode___width 1
-#define reg_bif_core_rw_grp3_cfg___mode___bit 21
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
-#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
-#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
-#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
-#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
-#define reg_bif_core_rw_grp3_cfg_offset 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
-#define reg_bif_core_rw_grp4_cfg___lw___width 6
-#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
-#define reg_bif_core_rw_grp4_cfg___ew___width 3
-#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
-#define reg_bif_core_rw_grp4_cfg___zw___width 3
-#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
-#define reg_bif_core_rw_grp4_cfg___aw___width 2
-#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
-#define reg_bif_core_rw_grp4_cfg___dw___width 2
-#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
-#define reg_bif_core_rw_grp4_cfg___ewb___width 2
-#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
-#define reg_bif_core_rw_grp4_cfg___bw___width 1
-#define reg_bif_core_rw_grp4_cfg___bw___bit 18
-#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
-#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
-#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
-#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
-#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
-#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
-#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
-#define reg_bif_core_rw_grp4_cfg___mode___width 1
-#define reg_bif_core_rw_grp4_cfg___mode___bit 21
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
-#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
-#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
-#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
-#define reg_bif_core_rw_grp4_cfg_offset 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
-#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
-#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
-#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
-#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
-#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
-#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
-#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_timing___cl___lsb 0
-#define reg_bif_core_rw_sdram_timing___cl___width 3
-#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
-#define reg_bif_core_rw_sdram_timing___rcd___width 3
-#define reg_bif_core_rw_sdram_timing___rp___lsb 6
-#define reg_bif_core_rw_sdram_timing___rp___width 3
-#define reg_bif_core_rw_sdram_timing___rc___lsb 9
-#define reg_bif_core_rw_sdram_timing___rc___width 2
-#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
-#define reg_bif_core_rw_sdram_timing___dpl___width 2
-#define reg_bif_core_rw_sdram_timing___pde___lsb 13
-#define reg_bif_core_rw_sdram_timing___pde___width 1
-#define reg_bif_core_rw_sdram_timing___pde___bit 13
-#define reg_bif_core_rw_sdram_timing___ref___lsb 14
-#define reg_bif_core_rw_sdram_timing___ref___width 2
-#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
-#define reg_bif_core_rw_sdram_timing___cpd___width 1
-#define reg_bif_core_rw_sdram_timing___cpd___bit 16
-#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
-#define reg_bif_core_rw_sdram_timing___sdcke___width 1
-#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
-#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
-#define reg_bif_core_rw_sdram_timing___sdclk___width 1
-#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
-#define reg_bif_core_rw_sdram_timing_offset 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
-#define reg_bif_core_rw_sdram_cmd___cmd___width 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
-#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
-#define reg_bif_core_rw_sdram_cmd_offset 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
-#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_rs_sdram_ref_stat_offset 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
-#define reg_bif_core_r_sdram_ref_stat___ok___width 1
-#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
-#define reg_bif_core_r_sdram_ref_stat_offset 36
-
-
-/* Constants */
-#define regk_bif_core_bank2 0x00000000
-#define regk_bif_core_bank4 0x00000001
-#define regk_bif_core_bit10 0x0000000a
-#define regk_bif_core_bit11 0x0000000b
-#define regk_bif_core_bit12 0x0000000c
-#define regk_bif_core_bit13 0x0000000d
-#define regk_bif_core_bit14 0x0000000e
-#define regk_bif_core_bit15 0x0000000f
-#define regk_bif_core_bit16 0x00000010
-#define regk_bif_core_bit17 0x00000011
-#define regk_bif_core_bit18 0x00000012
-#define regk_bif_core_bit19 0x00000013
-#define regk_bif_core_bit20 0x00000014
-#define regk_bif_core_bit21 0x00000015
-#define regk_bif_core_bit22 0x00000016
-#define regk_bif_core_bit23 0x00000017
-#define regk_bif_core_bit24 0x00000018
-#define regk_bif_core_bit25 0x00000019
-#define regk_bif_core_bit26 0x0000001a
-#define regk_bif_core_bit27 0x0000001b
-#define regk_bif_core_bit28 0x0000001c
-#define regk_bif_core_bit29 0x0000001d
-#define regk_bif_core_bit9 0x00000009
-#define regk_bif_core_bw16 0x00000001
-#define regk_bif_core_bw32 0x00000000
-#define regk_bif_core_bwe 0x00000000
-#define regk_bif_core_cwe 0x00000001
-#define regk_bif_core_e15us 0x00000001
-#define regk_bif_core_e7800ns 0x00000002
-#define regk_bif_core_grp0 0x00000000
-#define regk_bif_core_grp1 0x00000001
-#define regk_bif_core_mrs 0x00000003
-#define regk_bif_core_no 0x00000000
-#define regk_bif_core_none 0x00000000
-#define regk_bif_core_nop 0x00000000
-#define regk_bif_core_off 0x00000000
-#define regk_bif_core_pre 0x00000002
-#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rd 0x00000002
-#define regk_bif_core_ref 0x00000001
-#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
-#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
-#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
-#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
-#define regk_bif_core_slf 0x00000004
-#define regk_bif_core_wr 0x00000001
-#define regk_bif_core_yes 0x00000001
-#endif /* __bif_core_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h
deleted file mode 100644
index 5b38835b42f7..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_asm_h
-#define __config_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
- * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_bootsel, scope config, type r */
-#define reg_config_r_bootsel___boot_mode___lsb 0
-#define reg_config_r_bootsel___boot_mode___width 3
-#define reg_config_r_bootsel___full_duplex___lsb 3
-#define reg_config_r_bootsel___full_duplex___width 1
-#define reg_config_r_bootsel___full_duplex___bit 3
-#define reg_config_r_bootsel___user___lsb 4
-#define reg_config_r_bootsel___user___width 1
-#define reg_config_r_bootsel___user___bit 4
-#define reg_config_r_bootsel___pll___lsb 5
-#define reg_config_r_bootsel___pll___width 1
-#define reg_config_r_bootsel___pll___bit 5
-#define reg_config_r_bootsel___flash_bw___lsb 6
-#define reg_config_r_bootsel___flash_bw___width 1
-#define reg_config_r_bootsel___flash_bw___bit 6
-#define reg_config_r_bootsel_offset 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-#define reg_config_rw_clk_ctrl___pll___lsb 0
-#define reg_config_rw_clk_ctrl___pll___width 1
-#define reg_config_rw_clk_ctrl___pll___bit 0
-#define reg_config_rw_clk_ctrl___cpu___lsb 1
-#define reg_config_rw_clk_ctrl___cpu___width 1
-#define reg_config_rw_clk_ctrl___cpu___bit 1
-#define reg_config_rw_clk_ctrl___iop___lsb 2
-#define reg_config_rw_clk_ctrl___iop___width 1
-#define reg_config_rw_clk_ctrl___iop___bit 2
-#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
-#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
-#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
-#define reg_config_rw_clk_ctrl___dma23___lsb 4
-#define reg_config_rw_clk_ctrl___dma23___width 1
-#define reg_config_rw_clk_ctrl___dma23___bit 4
-#define reg_config_rw_clk_ctrl___dma45___lsb 5
-#define reg_config_rw_clk_ctrl___dma45___width 1
-#define reg_config_rw_clk_ctrl___dma45___bit 5
-#define reg_config_rw_clk_ctrl___dma67___lsb 6
-#define reg_config_rw_clk_ctrl___dma67___width 1
-#define reg_config_rw_clk_ctrl___dma67___bit 6
-#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
-#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
-#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
-#define reg_config_rw_clk_ctrl___bif___lsb 8
-#define reg_config_rw_clk_ctrl___bif___width 1
-#define reg_config_rw_clk_ctrl___bif___bit 8
-#define reg_config_rw_clk_ctrl___fix_io___lsb 9
-#define reg_config_rw_clk_ctrl___fix_io___width 1
-#define reg_config_rw_clk_ctrl___fix_io___bit 9
-#define reg_config_rw_clk_ctrl_offset 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
-#define reg_config_rw_pad_ctrl___usb_susp___width 1
-#define reg_config_rw_pad_ctrl___usb_susp___bit 0
-#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
-#define reg_config_rw_pad_ctrl___phyrst_n___width 1
-#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
-#define reg_config_rw_pad_ctrl_offset 8
-
-
-/* Constants */
-#define regk_config_bw16 0x00000000
-#define regk_config_bw32 0x00000001
-#define regk_config_master 0x00000005
-#define regk_config_nand 0x00000003
-#define regk_config_net_rx 0x00000001
-#define regk_config_net_tx_rx 0x00000002
-#define regk_config_no 0x00000000
-#define regk_config_none 0x00000007
-#define regk_config_nor 0x00000000
-#define regk_config_rw_clk_ctrl_default 0x00000002
-#define regk_config_rw_pad_ctrl_default 0x00000000
-#define regk_config_ser 0x00000004
-#define regk_config_slave 0x00000006
-#define regk_config_yes 0x00000001
-#endif /* __config_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h
deleted file mode 100644
index 3d2056892832..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_asm_h
-#define __gio_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/gio/rtl/gio_regs.r
- * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- * last modfied: Mon Apr 11 16:07:47 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
- * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa_dout, scope gio, type rw */
-#define reg_gio_rw_pa_dout___data___lsb 0
-#define reg_gio_rw_pa_dout___data___width 8
-#define reg_gio_rw_pa_dout_offset 0
-
-/* Register r_pa_din, scope gio, type r */
-#define reg_gio_r_pa_din___data___lsb 0
-#define reg_gio_r_pa_din___data___width 8
-#define reg_gio_r_pa_din_offset 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-#define reg_gio_rw_pa_oe___oe___lsb 0
-#define reg_gio_rw_pa_oe___oe___width 8
-#define reg_gio_rw_pa_oe_offset 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-#define reg_gio_rw_intr_cfg___pa0___lsb 0
-#define reg_gio_rw_intr_cfg___pa0___width 3
-#define reg_gio_rw_intr_cfg___pa1___lsb 3
-#define reg_gio_rw_intr_cfg___pa1___width 3
-#define reg_gio_rw_intr_cfg___pa2___lsb 6
-#define reg_gio_rw_intr_cfg___pa2___width 3
-#define reg_gio_rw_intr_cfg___pa3___lsb 9
-#define reg_gio_rw_intr_cfg___pa3___width 3
-#define reg_gio_rw_intr_cfg___pa4___lsb 12
-#define reg_gio_rw_intr_cfg___pa4___width 3
-#define reg_gio_rw_intr_cfg___pa5___lsb 15
-#define reg_gio_rw_intr_cfg___pa5___width 3
-#define reg_gio_rw_intr_cfg___pa6___lsb 18
-#define reg_gio_rw_intr_cfg___pa6___width 3
-#define reg_gio_rw_intr_cfg___pa7___lsb 21
-#define reg_gio_rw_intr_cfg___pa7___width 3
-#define reg_gio_rw_intr_cfg_offset 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-#define reg_gio_rw_intr_mask___pa0___lsb 0
-#define reg_gio_rw_intr_mask___pa0___width 1
-#define reg_gio_rw_intr_mask___pa0___bit 0
-#define reg_gio_rw_intr_mask___pa1___lsb 1
-#define reg_gio_rw_intr_mask___pa1___width 1
-#define reg_gio_rw_intr_mask___pa1___bit 1
-#define reg_gio_rw_intr_mask___pa2___lsb 2
-#define reg_gio_rw_intr_mask___pa2___width 1
-#define reg_gio_rw_intr_mask___pa2___bit 2
-#define reg_gio_rw_intr_mask___pa3___lsb 3
-#define reg_gio_rw_intr_mask___pa3___width 1
-#define reg_gio_rw_intr_mask___pa3___bit 3
-#define reg_gio_rw_intr_mask___pa4___lsb 4
-#define reg_gio_rw_intr_mask___pa4___width 1
-#define reg_gio_rw_intr_mask___pa4___bit 4
-#define reg_gio_rw_intr_mask___pa5___lsb 5
-#define reg_gio_rw_intr_mask___pa5___width 1
-#define reg_gio_rw_intr_mask___pa5___bit 5
-#define reg_gio_rw_intr_mask___pa6___lsb 6
-#define reg_gio_rw_intr_mask___pa6___width 1
-#define reg_gio_rw_intr_mask___pa6___bit 6
-#define reg_gio_rw_intr_mask___pa7___lsb 7
-#define reg_gio_rw_intr_mask___pa7___width 1
-#define reg_gio_rw_intr_mask___pa7___bit 7
-#define reg_gio_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-#define reg_gio_rw_ack_intr___pa0___lsb 0
-#define reg_gio_rw_ack_intr___pa0___width 1
-#define reg_gio_rw_ack_intr___pa0___bit 0
-#define reg_gio_rw_ack_intr___pa1___lsb 1
-#define reg_gio_rw_ack_intr___pa1___width 1
-#define reg_gio_rw_ack_intr___pa1___bit 1
-#define reg_gio_rw_ack_intr___pa2___lsb 2
-#define reg_gio_rw_ack_intr___pa2___width 1
-#define reg_gio_rw_ack_intr___pa2___bit 2
-#define reg_gio_rw_ack_intr___pa3___lsb 3
-#define reg_gio_rw_ack_intr___pa3___width 1
-#define reg_gio_rw_ack_intr___pa3___bit 3
-#define reg_gio_rw_ack_intr___pa4___lsb 4
-#define reg_gio_rw_ack_intr___pa4___width 1
-#define reg_gio_rw_ack_intr___pa4___bit 4
-#define reg_gio_rw_ack_intr___pa5___lsb 5
-#define reg_gio_rw_ack_intr___pa5___width 1
-#define reg_gio_rw_ack_intr___pa5___bit 5
-#define reg_gio_rw_ack_intr___pa6___lsb 6
-#define reg_gio_rw_ack_intr___pa6___width 1
-#define reg_gio_rw_ack_intr___pa6___bit 6
-#define reg_gio_rw_ack_intr___pa7___lsb 7
-#define reg_gio_rw_ack_intr___pa7___width 1
-#define reg_gio_rw_ack_intr___pa7___bit 7
-#define reg_gio_rw_ack_intr_offset 20
-
-/* Register r_intr, scope gio, type r */
-#define reg_gio_r_intr___pa0___lsb 0
-#define reg_gio_r_intr___pa0___width 1
-#define reg_gio_r_intr___pa0___bit 0
-#define reg_gio_r_intr___pa1___lsb 1
-#define reg_gio_r_intr___pa1___width 1
-#define reg_gio_r_intr___pa1___bit 1
-#define reg_gio_r_intr___pa2___lsb 2
-#define reg_gio_r_intr___pa2___width 1
-#define reg_gio_r_intr___pa2___bit 2
-#define reg_gio_r_intr___pa3___lsb 3
-#define reg_gio_r_intr___pa3___width 1
-#define reg_gio_r_intr___pa3___bit 3
-#define reg_gio_r_intr___pa4___lsb 4
-#define reg_gio_r_intr___pa4___width 1
-#define reg_gio_r_intr___pa4___bit 4
-#define reg_gio_r_intr___pa5___lsb 5
-#define reg_gio_r_intr___pa5___width 1
-#define reg_gio_r_intr___pa5___bit 5
-#define reg_gio_r_intr___pa6___lsb 6
-#define reg_gio_r_intr___pa6___width 1
-#define reg_gio_r_intr___pa6___bit 6
-#define reg_gio_r_intr___pa7___lsb 7
-#define reg_gio_r_intr___pa7___width 1
-#define reg_gio_r_intr___pa7___bit 7
-#define reg_gio_r_intr_offset 24
-
-/* Register r_masked_intr, scope gio, type r */
-#define reg_gio_r_masked_intr___pa0___lsb 0
-#define reg_gio_r_masked_intr___pa0___width 1
-#define reg_gio_r_masked_intr___pa0___bit 0
-#define reg_gio_r_masked_intr___pa1___lsb 1
-#define reg_gio_r_masked_intr___pa1___width 1
-#define reg_gio_r_masked_intr___pa1___bit 1
-#define reg_gio_r_masked_intr___pa2___lsb 2
-#define reg_gio_r_masked_intr___pa2___width 1
-#define reg_gio_r_masked_intr___pa2___bit 2
-#define reg_gio_r_masked_intr___pa3___lsb 3
-#define reg_gio_r_masked_intr___pa3___width 1
-#define reg_gio_r_masked_intr___pa3___bit 3
-#define reg_gio_r_masked_intr___pa4___lsb 4
-#define reg_gio_r_masked_intr___pa4___width 1
-#define reg_gio_r_masked_intr___pa4___bit 4
-#define reg_gio_r_masked_intr___pa5___lsb 5
-#define reg_gio_r_masked_intr___pa5___width 1
-#define reg_gio_r_masked_intr___pa5___bit 5
-#define reg_gio_r_masked_intr___pa6___lsb 6
-#define reg_gio_r_masked_intr___pa6___width 1
-#define reg_gio_r_masked_intr___pa6___bit 6
-#define reg_gio_r_masked_intr___pa7___lsb 7
-#define reg_gio_r_masked_intr___pa7___width 1
-#define reg_gio_r_masked_intr___pa7___bit 7
-#define reg_gio_r_masked_intr_offset 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-#define reg_gio_rw_pb_dout___data___lsb 0
-#define reg_gio_rw_pb_dout___data___width 18
-#define reg_gio_rw_pb_dout_offset 32
-
-/* Register r_pb_din, scope gio, type r */
-#define reg_gio_r_pb_din___data___lsb 0
-#define reg_gio_r_pb_din___data___width 18
-#define reg_gio_r_pb_din_offset 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-#define reg_gio_rw_pb_oe___oe___lsb 0
-#define reg_gio_rw_pb_oe___oe___width 18
-#define reg_gio_rw_pb_oe_offset 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-#define reg_gio_rw_pc_dout___data___lsb 0
-#define reg_gio_rw_pc_dout___data___width 18
-#define reg_gio_rw_pc_dout_offset 48
-
-/* Register r_pc_din, scope gio, type r */
-#define reg_gio_r_pc_din___data___lsb 0
-#define reg_gio_r_pc_din___data___width 18
-#define reg_gio_r_pc_din_offset 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-#define reg_gio_rw_pc_oe___oe___lsb 0
-#define reg_gio_rw_pc_oe___oe___width 18
-#define reg_gio_rw_pc_oe_offset 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-#define reg_gio_rw_pd_dout___data___lsb 0
-#define reg_gio_rw_pd_dout___data___width 18
-#define reg_gio_rw_pd_dout_offset 64
-
-/* Register r_pd_din, scope gio, type r */
-#define reg_gio_r_pd_din___data___lsb 0
-#define reg_gio_r_pd_din___data___width 18
-#define reg_gio_r_pd_din_offset 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-#define reg_gio_rw_pd_oe___oe___lsb 0
-#define reg_gio_rw_pd_oe___oe___width 18
-#define reg_gio_rw_pd_oe_offset 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-#define reg_gio_rw_pe_dout___data___lsb 0
-#define reg_gio_rw_pe_dout___data___width 18
-#define reg_gio_rw_pe_dout_offset 80
-
-/* Register r_pe_din, scope gio, type r */
-#define reg_gio_r_pe_din___data___lsb 0
-#define reg_gio_r_pe_din___data___width 18
-#define reg_gio_r_pe_din_offset 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-#define reg_gio_rw_pe_oe___oe___lsb 0
-#define reg_gio_rw_pe_oe___oe___width 18
-#define reg_gio_rw_pe_oe_offset 88
-
-
-/* Constants */
-#define regk_gio_anyedge 0x00000007
-#define regk_gio_hi 0x00000001
-#define regk_gio_lo 0x00000002
-#define regk_gio_negedge 0x00000006
-#define regk_gio_no 0x00000000
-#define regk_gio_off 0x00000000
-#define regk_gio_posedge 0x00000005
-#define regk_gio_rw_intr_cfg_default 0x00000000
-#define regk_gio_rw_intr_mask_default 0x00000000
-#define regk_gio_rw_pa_oe_default 0x00000000
-#define regk_gio_rw_pb_oe_default 0x00000000
-#define regk_gio_rw_pc_oe_default 0x00000000
-#define regk_gio_rw_pd_oe_default 0x00000000
-#define regk_gio_rw_pe_oe_default 0x00000000
-#define regk_gio_set 0x00000003
-#define regk_gio_yes 0x00000001
-#endif /* __gio_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h
deleted file mode 100644
index 99968cfa446a..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h
+++ /dev/null
@@ -1,633 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_asm_h
-#define __pinmux_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
- * last modfied: Mon Apr 11 16:09:11 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_pa, scope pinmux, type rw */
-#define reg_pinmux_rw_pa___pa0___lsb 0
-#define reg_pinmux_rw_pa___pa0___width 1
-#define reg_pinmux_rw_pa___pa0___bit 0
-#define reg_pinmux_rw_pa___pa1___lsb 1
-#define reg_pinmux_rw_pa___pa1___width 1
-#define reg_pinmux_rw_pa___pa1___bit 1
-#define reg_pinmux_rw_pa___pa2___lsb 2
-#define reg_pinmux_rw_pa___pa2___width 1
-#define reg_pinmux_rw_pa___pa2___bit 2
-#define reg_pinmux_rw_pa___pa3___lsb 3
-#define reg_pinmux_rw_pa___pa3___width 1
-#define reg_pinmux_rw_pa___pa3___bit 3
-#define reg_pinmux_rw_pa___pa4___lsb 4
-#define reg_pinmux_rw_pa___pa4___width 1
-#define reg_pinmux_rw_pa___pa4___bit 4
-#define reg_pinmux_rw_pa___pa5___lsb 5
-#define reg_pinmux_rw_pa___pa5___width 1
-#define reg_pinmux_rw_pa___pa5___bit 5
-#define reg_pinmux_rw_pa___pa6___lsb 6
-#define reg_pinmux_rw_pa___pa6___width 1
-#define reg_pinmux_rw_pa___pa6___bit 6
-#define reg_pinmux_rw_pa___pa7___lsb 7
-#define reg_pinmux_rw_pa___pa7___width 1
-#define reg_pinmux_rw_pa___pa7___bit 7
-#define reg_pinmux_rw_pa___csp2_n___lsb 8
-#define reg_pinmux_rw_pa___csp2_n___width 1
-#define reg_pinmux_rw_pa___csp2_n___bit 8
-#define reg_pinmux_rw_pa___csp3_n___lsb 9
-#define reg_pinmux_rw_pa___csp3_n___width 1
-#define reg_pinmux_rw_pa___csp3_n___bit 9
-#define reg_pinmux_rw_pa___csp5_n___lsb 10
-#define reg_pinmux_rw_pa___csp5_n___width 1
-#define reg_pinmux_rw_pa___csp5_n___bit 10
-#define reg_pinmux_rw_pa___csp6_n___lsb 11
-#define reg_pinmux_rw_pa___csp6_n___width 1
-#define reg_pinmux_rw_pa___csp6_n___bit 11
-#define reg_pinmux_rw_pa___hsh4___lsb 12
-#define reg_pinmux_rw_pa___hsh4___width 1
-#define reg_pinmux_rw_pa___hsh4___bit 12
-#define reg_pinmux_rw_pa___hsh5___lsb 13
-#define reg_pinmux_rw_pa___hsh5___width 1
-#define reg_pinmux_rw_pa___hsh5___bit 13
-#define reg_pinmux_rw_pa___hsh6___lsb 14
-#define reg_pinmux_rw_pa___hsh6___width 1
-#define reg_pinmux_rw_pa___hsh6___bit 14
-#define reg_pinmux_rw_pa___hsh7___lsb 15
-#define reg_pinmux_rw_pa___hsh7___width 1
-#define reg_pinmux_rw_pa___hsh7___bit 15
-#define reg_pinmux_rw_pa_offset 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-#define reg_pinmux_rw_hwprot___ser1___lsb 0
-#define reg_pinmux_rw_hwprot___ser1___width 1
-#define reg_pinmux_rw_hwprot___ser1___bit 0
-#define reg_pinmux_rw_hwprot___ser2___lsb 1
-#define reg_pinmux_rw_hwprot___ser2___width 1
-#define reg_pinmux_rw_hwprot___ser2___bit 1
-#define reg_pinmux_rw_hwprot___ser3___lsb 2
-#define reg_pinmux_rw_hwprot___ser3___width 1
-#define reg_pinmux_rw_hwprot___ser3___bit 2
-#define reg_pinmux_rw_hwprot___sser0___lsb 3
-#define reg_pinmux_rw_hwprot___sser0___width 1
-#define reg_pinmux_rw_hwprot___sser0___bit 3
-#define reg_pinmux_rw_hwprot___sser1___lsb 4
-#define reg_pinmux_rw_hwprot___sser1___width 1
-#define reg_pinmux_rw_hwprot___sser1___bit 4
-#define reg_pinmux_rw_hwprot___ata0___lsb 5
-#define reg_pinmux_rw_hwprot___ata0___width 1
-#define reg_pinmux_rw_hwprot___ata0___bit 5
-#define reg_pinmux_rw_hwprot___ata1___lsb 6
-#define reg_pinmux_rw_hwprot___ata1___width 1
-#define reg_pinmux_rw_hwprot___ata1___bit 6
-#define reg_pinmux_rw_hwprot___ata2___lsb 7
-#define reg_pinmux_rw_hwprot___ata2___width 1
-#define reg_pinmux_rw_hwprot___ata2___bit 7
-#define reg_pinmux_rw_hwprot___ata3___lsb 8
-#define reg_pinmux_rw_hwprot___ata3___width 1
-#define reg_pinmux_rw_hwprot___ata3___bit 8
-#define reg_pinmux_rw_hwprot___ata___lsb 9
-#define reg_pinmux_rw_hwprot___ata___width 1
-#define reg_pinmux_rw_hwprot___ata___bit 9
-#define reg_pinmux_rw_hwprot___eth1___lsb 10
-#define reg_pinmux_rw_hwprot___eth1___width 1
-#define reg_pinmux_rw_hwprot___eth1___bit 10
-#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
-#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
-#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
-#define reg_pinmux_rw_hwprot___timer___lsb 12
-#define reg_pinmux_rw_hwprot___timer___width 1
-#define reg_pinmux_rw_hwprot___timer___bit 12
-#define reg_pinmux_rw_hwprot___p21___lsb 13
-#define reg_pinmux_rw_hwprot___p21___width 1
-#define reg_pinmux_rw_hwprot___p21___bit 13
-#define reg_pinmux_rw_hwprot_offset 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_gio___pb0___lsb 0
-#define reg_pinmux_rw_pb_gio___pb0___width 1
-#define reg_pinmux_rw_pb_gio___pb0___bit 0
-#define reg_pinmux_rw_pb_gio___pb1___lsb 1
-#define reg_pinmux_rw_pb_gio___pb1___width 1
-#define reg_pinmux_rw_pb_gio___pb1___bit 1
-#define reg_pinmux_rw_pb_gio___pb2___lsb 2
-#define reg_pinmux_rw_pb_gio___pb2___width 1
-#define reg_pinmux_rw_pb_gio___pb2___bit 2
-#define reg_pinmux_rw_pb_gio___pb3___lsb 3
-#define reg_pinmux_rw_pb_gio___pb3___width 1
-#define reg_pinmux_rw_pb_gio___pb3___bit 3
-#define reg_pinmux_rw_pb_gio___pb4___lsb 4
-#define reg_pinmux_rw_pb_gio___pb4___width 1
-#define reg_pinmux_rw_pb_gio___pb4___bit 4
-#define reg_pinmux_rw_pb_gio___pb5___lsb 5
-#define reg_pinmux_rw_pb_gio___pb5___width 1
-#define reg_pinmux_rw_pb_gio___pb5___bit 5
-#define reg_pinmux_rw_pb_gio___pb6___lsb 6
-#define reg_pinmux_rw_pb_gio___pb6___width 1
-#define reg_pinmux_rw_pb_gio___pb6___bit 6
-#define reg_pinmux_rw_pb_gio___pb7___lsb 7
-#define reg_pinmux_rw_pb_gio___pb7___width 1
-#define reg_pinmux_rw_pb_gio___pb7___bit 7
-#define reg_pinmux_rw_pb_gio___pb8___lsb 8
-#define reg_pinmux_rw_pb_gio___pb8___width 1
-#define reg_pinmux_rw_pb_gio___pb8___bit 8
-#define reg_pinmux_rw_pb_gio___pb9___lsb 9
-#define reg_pinmux_rw_pb_gio___pb9___width 1
-#define reg_pinmux_rw_pb_gio___pb9___bit 9
-#define reg_pinmux_rw_pb_gio___pb10___lsb 10
-#define reg_pinmux_rw_pb_gio___pb10___width 1
-#define reg_pinmux_rw_pb_gio___pb10___bit 10
-#define reg_pinmux_rw_pb_gio___pb11___lsb 11
-#define reg_pinmux_rw_pb_gio___pb11___width 1
-#define reg_pinmux_rw_pb_gio___pb11___bit 11
-#define reg_pinmux_rw_pb_gio___pb12___lsb 12
-#define reg_pinmux_rw_pb_gio___pb12___width 1
-#define reg_pinmux_rw_pb_gio___pb12___bit 12
-#define reg_pinmux_rw_pb_gio___pb13___lsb 13
-#define reg_pinmux_rw_pb_gio___pb13___width 1
-#define reg_pinmux_rw_pb_gio___pb13___bit 13
-#define reg_pinmux_rw_pb_gio___pb14___lsb 14
-#define reg_pinmux_rw_pb_gio___pb14___width 1
-#define reg_pinmux_rw_pb_gio___pb14___bit 14
-#define reg_pinmux_rw_pb_gio___pb15___lsb 15
-#define reg_pinmux_rw_pb_gio___pb15___width 1
-#define reg_pinmux_rw_pb_gio___pb15___bit 15
-#define reg_pinmux_rw_pb_gio___pb16___lsb 16
-#define reg_pinmux_rw_pb_gio___pb16___width 1
-#define reg_pinmux_rw_pb_gio___pb16___bit 16
-#define reg_pinmux_rw_pb_gio___pb17___lsb 17
-#define reg_pinmux_rw_pb_gio___pb17___width 1
-#define reg_pinmux_rw_pb_gio___pb17___bit 17
-#define reg_pinmux_rw_pb_gio_offset 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pb_iop___pb0___lsb 0
-#define reg_pinmux_rw_pb_iop___pb0___width 1
-#define reg_pinmux_rw_pb_iop___pb0___bit 0
-#define reg_pinmux_rw_pb_iop___pb1___lsb 1
-#define reg_pinmux_rw_pb_iop___pb1___width 1
-#define reg_pinmux_rw_pb_iop___pb1___bit 1
-#define reg_pinmux_rw_pb_iop___pb2___lsb 2
-#define reg_pinmux_rw_pb_iop___pb2___width 1
-#define reg_pinmux_rw_pb_iop___pb2___bit 2
-#define reg_pinmux_rw_pb_iop___pb3___lsb 3
-#define reg_pinmux_rw_pb_iop___pb3___width 1
-#define reg_pinmux_rw_pb_iop___pb3___bit 3
-#define reg_pinmux_rw_pb_iop___pb4___lsb 4
-#define reg_pinmux_rw_pb_iop___pb4___width 1
-#define reg_pinmux_rw_pb_iop___pb4___bit 4
-#define reg_pinmux_rw_pb_iop___pb5___lsb 5
-#define reg_pinmux_rw_pb_iop___pb5___width 1
-#define reg_pinmux_rw_pb_iop___pb5___bit 5
-#define reg_pinmux_rw_pb_iop___pb6___lsb 6
-#define reg_pinmux_rw_pb_iop___pb6___width 1
-#define reg_pinmux_rw_pb_iop___pb6___bit 6
-#define reg_pinmux_rw_pb_iop___pb7___lsb 7
-#define reg_pinmux_rw_pb_iop___pb7___width 1
-#define reg_pinmux_rw_pb_iop___pb7___bit 7
-#define reg_pinmux_rw_pb_iop___pb8___lsb 8
-#define reg_pinmux_rw_pb_iop___pb8___width 1
-#define reg_pinmux_rw_pb_iop___pb8___bit 8
-#define reg_pinmux_rw_pb_iop___pb9___lsb 9
-#define reg_pinmux_rw_pb_iop___pb9___width 1
-#define reg_pinmux_rw_pb_iop___pb9___bit 9
-#define reg_pinmux_rw_pb_iop___pb10___lsb 10
-#define reg_pinmux_rw_pb_iop___pb10___width 1
-#define reg_pinmux_rw_pb_iop___pb10___bit 10
-#define reg_pinmux_rw_pb_iop___pb11___lsb 11
-#define reg_pinmux_rw_pb_iop___pb11___width 1
-#define reg_pinmux_rw_pb_iop___pb11___bit 11
-#define reg_pinmux_rw_pb_iop___pb12___lsb 12
-#define reg_pinmux_rw_pb_iop___pb12___width 1
-#define reg_pinmux_rw_pb_iop___pb12___bit 12
-#define reg_pinmux_rw_pb_iop___pb13___lsb 13
-#define reg_pinmux_rw_pb_iop___pb13___width 1
-#define reg_pinmux_rw_pb_iop___pb13___bit 13
-#define reg_pinmux_rw_pb_iop___pb14___lsb 14
-#define reg_pinmux_rw_pb_iop___pb14___width 1
-#define reg_pinmux_rw_pb_iop___pb14___bit 14
-#define reg_pinmux_rw_pb_iop___pb15___lsb 15
-#define reg_pinmux_rw_pb_iop___pb15___width 1
-#define reg_pinmux_rw_pb_iop___pb15___bit 15
-#define reg_pinmux_rw_pb_iop___pb16___lsb 16
-#define reg_pinmux_rw_pb_iop___pb16___width 1
-#define reg_pinmux_rw_pb_iop___pb16___bit 16
-#define reg_pinmux_rw_pb_iop___pb17___lsb 17
-#define reg_pinmux_rw_pb_iop___pb17___width 1
-#define reg_pinmux_rw_pb_iop___pb17___bit 17
-#define reg_pinmux_rw_pb_iop_offset 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_gio___pc0___lsb 0
-#define reg_pinmux_rw_pc_gio___pc0___width 1
-#define reg_pinmux_rw_pc_gio___pc0___bit 0
-#define reg_pinmux_rw_pc_gio___pc1___lsb 1
-#define reg_pinmux_rw_pc_gio___pc1___width 1
-#define reg_pinmux_rw_pc_gio___pc1___bit 1
-#define reg_pinmux_rw_pc_gio___pc2___lsb 2
-#define reg_pinmux_rw_pc_gio___pc2___width 1
-#define reg_pinmux_rw_pc_gio___pc2___bit 2
-#define reg_pinmux_rw_pc_gio___pc3___lsb 3
-#define reg_pinmux_rw_pc_gio___pc3___width 1
-#define reg_pinmux_rw_pc_gio___pc3___bit 3
-#define reg_pinmux_rw_pc_gio___pc4___lsb 4
-#define reg_pinmux_rw_pc_gio___pc4___width 1
-#define reg_pinmux_rw_pc_gio___pc4___bit 4
-#define reg_pinmux_rw_pc_gio___pc5___lsb 5
-#define reg_pinmux_rw_pc_gio___pc5___width 1
-#define reg_pinmux_rw_pc_gio___pc5___bit 5
-#define reg_pinmux_rw_pc_gio___pc6___lsb 6
-#define reg_pinmux_rw_pc_gio___pc6___width 1
-#define reg_pinmux_rw_pc_gio___pc6___bit 6
-#define reg_pinmux_rw_pc_gio___pc7___lsb 7
-#define reg_pinmux_rw_pc_gio___pc7___width 1
-#define reg_pinmux_rw_pc_gio___pc7___bit 7
-#define reg_pinmux_rw_pc_gio___pc8___lsb 8
-#define reg_pinmux_rw_pc_gio___pc8___width 1
-#define reg_pinmux_rw_pc_gio___pc8___bit 8
-#define reg_pinmux_rw_pc_gio___pc9___lsb 9
-#define reg_pinmux_rw_pc_gio___pc9___width 1
-#define reg_pinmux_rw_pc_gio___pc9___bit 9
-#define reg_pinmux_rw_pc_gio___pc10___lsb 10
-#define reg_pinmux_rw_pc_gio___pc10___width 1
-#define reg_pinmux_rw_pc_gio___pc10___bit 10
-#define reg_pinmux_rw_pc_gio___pc11___lsb 11
-#define reg_pinmux_rw_pc_gio___pc11___width 1
-#define reg_pinmux_rw_pc_gio___pc11___bit 11
-#define reg_pinmux_rw_pc_gio___pc12___lsb 12
-#define reg_pinmux_rw_pc_gio___pc12___width 1
-#define reg_pinmux_rw_pc_gio___pc12___bit 12
-#define reg_pinmux_rw_pc_gio___pc13___lsb 13
-#define reg_pinmux_rw_pc_gio___pc13___width 1
-#define reg_pinmux_rw_pc_gio___pc13___bit 13
-#define reg_pinmux_rw_pc_gio___pc14___lsb 14
-#define reg_pinmux_rw_pc_gio___pc14___width 1
-#define reg_pinmux_rw_pc_gio___pc14___bit 14
-#define reg_pinmux_rw_pc_gio___pc15___lsb 15
-#define reg_pinmux_rw_pc_gio___pc15___width 1
-#define reg_pinmux_rw_pc_gio___pc15___bit 15
-#define reg_pinmux_rw_pc_gio___pc16___lsb 16
-#define reg_pinmux_rw_pc_gio___pc16___width 1
-#define reg_pinmux_rw_pc_gio___pc16___bit 16
-#define reg_pinmux_rw_pc_gio___pc17___lsb 17
-#define reg_pinmux_rw_pc_gio___pc17___width 1
-#define reg_pinmux_rw_pc_gio___pc17___bit 17
-#define reg_pinmux_rw_pc_gio_offset 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pc_iop___pc0___lsb 0
-#define reg_pinmux_rw_pc_iop___pc0___width 1
-#define reg_pinmux_rw_pc_iop___pc0___bit 0
-#define reg_pinmux_rw_pc_iop___pc1___lsb 1
-#define reg_pinmux_rw_pc_iop___pc1___width 1
-#define reg_pinmux_rw_pc_iop___pc1___bit 1
-#define reg_pinmux_rw_pc_iop___pc2___lsb 2
-#define reg_pinmux_rw_pc_iop___pc2___width 1
-#define reg_pinmux_rw_pc_iop___pc2___bit 2
-#define reg_pinmux_rw_pc_iop___pc3___lsb 3
-#define reg_pinmux_rw_pc_iop___pc3___width 1
-#define reg_pinmux_rw_pc_iop___pc3___bit 3
-#define reg_pinmux_rw_pc_iop___pc4___lsb 4
-#define reg_pinmux_rw_pc_iop___pc4___width 1
-#define reg_pinmux_rw_pc_iop___pc4___bit 4
-#define reg_pinmux_rw_pc_iop___pc5___lsb 5
-#define reg_pinmux_rw_pc_iop___pc5___width 1
-#define reg_pinmux_rw_pc_iop___pc5___bit 5
-#define reg_pinmux_rw_pc_iop___pc6___lsb 6
-#define reg_pinmux_rw_pc_iop___pc6___width 1
-#define reg_pinmux_rw_pc_iop___pc6___bit 6
-#define reg_pinmux_rw_pc_iop___pc7___lsb 7
-#define reg_pinmux_rw_pc_iop___pc7___width 1
-#define reg_pinmux_rw_pc_iop___pc7___bit 7
-#define reg_pinmux_rw_pc_iop___pc8___lsb 8
-#define reg_pinmux_rw_pc_iop___pc8___width 1
-#define reg_pinmux_rw_pc_iop___pc8___bit 8
-#define reg_pinmux_rw_pc_iop___pc9___lsb 9
-#define reg_pinmux_rw_pc_iop___pc9___width 1
-#define reg_pinmux_rw_pc_iop___pc9___bit 9
-#define reg_pinmux_rw_pc_iop___pc10___lsb 10
-#define reg_pinmux_rw_pc_iop___pc10___width 1
-#define reg_pinmux_rw_pc_iop___pc10___bit 10
-#define reg_pinmux_rw_pc_iop___pc11___lsb 11
-#define reg_pinmux_rw_pc_iop___pc11___width 1
-#define reg_pinmux_rw_pc_iop___pc11___bit 11
-#define reg_pinmux_rw_pc_iop___pc12___lsb 12
-#define reg_pinmux_rw_pc_iop___pc12___width 1
-#define reg_pinmux_rw_pc_iop___pc12___bit 12
-#define reg_pinmux_rw_pc_iop___pc13___lsb 13
-#define reg_pinmux_rw_pc_iop___pc13___width 1
-#define reg_pinmux_rw_pc_iop___pc13___bit 13
-#define reg_pinmux_rw_pc_iop___pc14___lsb 14
-#define reg_pinmux_rw_pc_iop___pc14___width 1
-#define reg_pinmux_rw_pc_iop___pc14___bit 14
-#define reg_pinmux_rw_pc_iop___pc15___lsb 15
-#define reg_pinmux_rw_pc_iop___pc15___width 1
-#define reg_pinmux_rw_pc_iop___pc15___bit 15
-#define reg_pinmux_rw_pc_iop___pc16___lsb 16
-#define reg_pinmux_rw_pc_iop___pc16___width 1
-#define reg_pinmux_rw_pc_iop___pc16___bit 16
-#define reg_pinmux_rw_pc_iop___pc17___lsb 17
-#define reg_pinmux_rw_pc_iop___pc17___width 1
-#define reg_pinmux_rw_pc_iop___pc17___bit 17
-#define reg_pinmux_rw_pc_iop_offset 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_gio___pd0___lsb 0
-#define reg_pinmux_rw_pd_gio___pd0___width 1
-#define reg_pinmux_rw_pd_gio___pd0___bit 0
-#define reg_pinmux_rw_pd_gio___pd1___lsb 1
-#define reg_pinmux_rw_pd_gio___pd1___width 1
-#define reg_pinmux_rw_pd_gio___pd1___bit 1
-#define reg_pinmux_rw_pd_gio___pd2___lsb 2
-#define reg_pinmux_rw_pd_gio___pd2___width 1
-#define reg_pinmux_rw_pd_gio___pd2___bit 2
-#define reg_pinmux_rw_pd_gio___pd3___lsb 3
-#define reg_pinmux_rw_pd_gio___pd3___width 1
-#define reg_pinmux_rw_pd_gio___pd3___bit 3
-#define reg_pinmux_rw_pd_gio___pd4___lsb 4
-#define reg_pinmux_rw_pd_gio___pd4___width 1
-#define reg_pinmux_rw_pd_gio___pd4___bit 4
-#define reg_pinmux_rw_pd_gio___pd5___lsb 5
-#define reg_pinmux_rw_pd_gio___pd5___width 1
-#define reg_pinmux_rw_pd_gio___pd5___bit 5
-#define reg_pinmux_rw_pd_gio___pd6___lsb 6
-#define reg_pinmux_rw_pd_gio___pd6___width 1
-#define reg_pinmux_rw_pd_gio___pd6___bit 6
-#define reg_pinmux_rw_pd_gio___pd7___lsb 7
-#define reg_pinmux_rw_pd_gio___pd7___width 1
-#define reg_pinmux_rw_pd_gio___pd7___bit 7
-#define reg_pinmux_rw_pd_gio___pd8___lsb 8
-#define reg_pinmux_rw_pd_gio___pd8___width 1
-#define reg_pinmux_rw_pd_gio___pd8___bit 8
-#define reg_pinmux_rw_pd_gio___pd9___lsb 9
-#define reg_pinmux_rw_pd_gio___pd9___width 1
-#define reg_pinmux_rw_pd_gio___pd9___bit 9
-#define reg_pinmux_rw_pd_gio___pd10___lsb 10
-#define reg_pinmux_rw_pd_gio___pd10___width 1
-#define reg_pinmux_rw_pd_gio___pd10___bit 10
-#define reg_pinmux_rw_pd_gio___pd11___lsb 11
-#define reg_pinmux_rw_pd_gio___pd11___width 1
-#define reg_pinmux_rw_pd_gio___pd11___bit 11
-#define reg_pinmux_rw_pd_gio___pd12___lsb 12
-#define reg_pinmux_rw_pd_gio___pd12___width 1
-#define reg_pinmux_rw_pd_gio___pd12___bit 12
-#define reg_pinmux_rw_pd_gio___pd13___lsb 13
-#define reg_pinmux_rw_pd_gio___pd13___width 1
-#define reg_pinmux_rw_pd_gio___pd13___bit 13
-#define reg_pinmux_rw_pd_gio___pd14___lsb 14
-#define reg_pinmux_rw_pd_gio___pd14___width 1
-#define reg_pinmux_rw_pd_gio___pd14___bit 14
-#define reg_pinmux_rw_pd_gio___pd15___lsb 15
-#define reg_pinmux_rw_pd_gio___pd15___width 1
-#define reg_pinmux_rw_pd_gio___pd15___bit 15
-#define reg_pinmux_rw_pd_gio___pd16___lsb 16
-#define reg_pinmux_rw_pd_gio___pd16___width 1
-#define reg_pinmux_rw_pd_gio___pd16___bit 16
-#define reg_pinmux_rw_pd_gio___pd17___lsb 17
-#define reg_pinmux_rw_pd_gio___pd17___width 1
-#define reg_pinmux_rw_pd_gio___pd17___bit 17
-#define reg_pinmux_rw_pd_gio_offset 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pd_iop___pd0___lsb 0
-#define reg_pinmux_rw_pd_iop___pd0___width 1
-#define reg_pinmux_rw_pd_iop___pd0___bit 0
-#define reg_pinmux_rw_pd_iop___pd1___lsb 1
-#define reg_pinmux_rw_pd_iop___pd1___width 1
-#define reg_pinmux_rw_pd_iop___pd1___bit 1
-#define reg_pinmux_rw_pd_iop___pd2___lsb 2
-#define reg_pinmux_rw_pd_iop___pd2___width 1
-#define reg_pinmux_rw_pd_iop___pd2___bit 2
-#define reg_pinmux_rw_pd_iop___pd3___lsb 3
-#define reg_pinmux_rw_pd_iop___pd3___width 1
-#define reg_pinmux_rw_pd_iop___pd3___bit 3
-#define reg_pinmux_rw_pd_iop___pd4___lsb 4
-#define reg_pinmux_rw_pd_iop___pd4___width 1
-#define reg_pinmux_rw_pd_iop___pd4___bit 4
-#define reg_pinmux_rw_pd_iop___pd5___lsb 5
-#define reg_pinmux_rw_pd_iop___pd5___width 1
-#define reg_pinmux_rw_pd_iop___pd5___bit 5
-#define reg_pinmux_rw_pd_iop___pd6___lsb 6
-#define reg_pinmux_rw_pd_iop___pd6___width 1
-#define reg_pinmux_rw_pd_iop___pd6___bit 6
-#define reg_pinmux_rw_pd_iop___pd7___lsb 7
-#define reg_pinmux_rw_pd_iop___pd7___width 1
-#define reg_pinmux_rw_pd_iop___pd7___bit 7
-#define reg_pinmux_rw_pd_iop___pd8___lsb 8
-#define reg_pinmux_rw_pd_iop___pd8___width 1
-#define reg_pinmux_rw_pd_iop___pd8___bit 8
-#define reg_pinmux_rw_pd_iop___pd9___lsb 9
-#define reg_pinmux_rw_pd_iop___pd9___width 1
-#define reg_pinmux_rw_pd_iop___pd9___bit 9
-#define reg_pinmux_rw_pd_iop___pd10___lsb 10
-#define reg_pinmux_rw_pd_iop___pd10___width 1
-#define reg_pinmux_rw_pd_iop___pd10___bit 10
-#define reg_pinmux_rw_pd_iop___pd11___lsb 11
-#define reg_pinmux_rw_pd_iop___pd11___width 1
-#define reg_pinmux_rw_pd_iop___pd11___bit 11
-#define reg_pinmux_rw_pd_iop___pd12___lsb 12
-#define reg_pinmux_rw_pd_iop___pd12___width 1
-#define reg_pinmux_rw_pd_iop___pd12___bit 12
-#define reg_pinmux_rw_pd_iop___pd13___lsb 13
-#define reg_pinmux_rw_pd_iop___pd13___width 1
-#define reg_pinmux_rw_pd_iop___pd13___bit 13
-#define reg_pinmux_rw_pd_iop___pd14___lsb 14
-#define reg_pinmux_rw_pd_iop___pd14___width 1
-#define reg_pinmux_rw_pd_iop___pd14___bit 14
-#define reg_pinmux_rw_pd_iop___pd15___lsb 15
-#define reg_pinmux_rw_pd_iop___pd15___width 1
-#define reg_pinmux_rw_pd_iop___pd15___bit 15
-#define reg_pinmux_rw_pd_iop___pd16___lsb 16
-#define reg_pinmux_rw_pd_iop___pd16___width 1
-#define reg_pinmux_rw_pd_iop___pd16___bit 16
-#define reg_pinmux_rw_pd_iop___pd17___lsb 17
-#define reg_pinmux_rw_pd_iop___pd17___width 1
-#define reg_pinmux_rw_pd_iop___pd17___bit 17
-#define reg_pinmux_rw_pd_iop_offset 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_gio___pe0___lsb 0
-#define reg_pinmux_rw_pe_gio___pe0___width 1
-#define reg_pinmux_rw_pe_gio___pe0___bit 0
-#define reg_pinmux_rw_pe_gio___pe1___lsb 1
-#define reg_pinmux_rw_pe_gio___pe1___width 1
-#define reg_pinmux_rw_pe_gio___pe1___bit 1
-#define reg_pinmux_rw_pe_gio___pe2___lsb 2
-#define reg_pinmux_rw_pe_gio___pe2___width 1
-#define reg_pinmux_rw_pe_gio___pe2___bit 2
-#define reg_pinmux_rw_pe_gio___pe3___lsb 3
-#define reg_pinmux_rw_pe_gio___pe3___width 1
-#define reg_pinmux_rw_pe_gio___pe3___bit 3
-#define reg_pinmux_rw_pe_gio___pe4___lsb 4
-#define reg_pinmux_rw_pe_gio___pe4___width 1
-#define reg_pinmux_rw_pe_gio___pe4___bit 4
-#define reg_pinmux_rw_pe_gio___pe5___lsb 5
-#define reg_pinmux_rw_pe_gio___pe5___width 1
-#define reg_pinmux_rw_pe_gio___pe5___bit 5
-#define reg_pinmux_rw_pe_gio___pe6___lsb 6
-#define reg_pinmux_rw_pe_gio___pe6___width 1
-#define reg_pinmux_rw_pe_gio___pe6___bit 6
-#define reg_pinmux_rw_pe_gio___pe7___lsb 7
-#define reg_pinmux_rw_pe_gio___pe7___width 1
-#define reg_pinmux_rw_pe_gio___pe7___bit 7
-#define reg_pinmux_rw_pe_gio___pe8___lsb 8
-#define reg_pinmux_rw_pe_gio___pe8___width 1
-#define reg_pinmux_rw_pe_gio___pe8___bit 8
-#define reg_pinmux_rw_pe_gio___pe9___lsb 9
-#define reg_pinmux_rw_pe_gio___pe9___width 1
-#define reg_pinmux_rw_pe_gio___pe9___bit 9
-#define reg_pinmux_rw_pe_gio___pe10___lsb 10
-#define reg_pinmux_rw_pe_gio___pe10___width 1
-#define reg_pinmux_rw_pe_gio___pe10___bit 10
-#define reg_pinmux_rw_pe_gio___pe11___lsb 11
-#define reg_pinmux_rw_pe_gio___pe11___width 1
-#define reg_pinmux_rw_pe_gio___pe11___bit 11
-#define reg_pinmux_rw_pe_gio___pe12___lsb 12
-#define reg_pinmux_rw_pe_gio___pe12___width 1
-#define reg_pinmux_rw_pe_gio___pe12___bit 12
-#define reg_pinmux_rw_pe_gio___pe13___lsb 13
-#define reg_pinmux_rw_pe_gio___pe13___width 1
-#define reg_pinmux_rw_pe_gio___pe13___bit 13
-#define reg_pinmux_rw_pe_gio___pe14___lsb 14
-#define reg_pinmux_rw_pe_gio___pe14___width 1
-#define reg_pinmux_rw_pe_gio___pe14___bit 14
-#define reg_pinmux_rw_pe_gio___pe15___lsb 15
-#define reg_pinmux_rw_pe_gio___pe15___width 1
-#define reg_pinmux_rw_pe_gio___pe15___bit 15
-#define reg_pinmux_rw_pe_gio___pe16___lsb 16
-#define reg_pinmux_rw_pe_gio___pe16___width 1
-#define reg_pinmux_rw_pe_gio___pe16___bit 16
-#define reg_pinmux_rw_pe_gio___pe17___lsb 17
-#define reg_pinmux_rw_pe_gio___pe17___width 1
-#define reg_pinmux_rw_pe_gio___pe17___bit 17
-#define reg_pinmux_rw_pe_gio_offset 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-#define reg_pinmux_rw_pe_iop___pe0___lsb 0
-#define reg_pinmux_rw_pe_iop___pe0___width 1
-#define reg_pinmux_rw_pe_iop___pe0___bit 0
-#define reg_pinmux_rw_pe_iop___pe1___lsb 1
-#define reg_pinmux_rw_pe_iop___pe1___width 1
-#define reg_pinmux_rw_pe_iop___pe1___bit 1
-#define reg_pinmux_rw_pe_iop___pe2___lsb 2
-#define reg_pinmux_rw_pe_iop___pe2___width 1
-#define reg_pinmux_rw_pe_iop___pe2___bit 2
-#define reg_pinmux_rw_pe_iop___pe3___lsb 3
-#define reg_pinmux_rw_pe_iop___pe3___width 1
-#define reg_pinmux_rw_pe_iop___pe3___bit 3
-#define reg_pinmux_rw_pe_iop___pe4___lsb 4
-#define reg_pinmux_rw_pe_iop___pe4___width 1
-#define reg_pinmux_rw_pe_iop___pe4___bit 4
-#define reg_pinmux_rw_pe_iop___pe5___lsb 5
-#define reg_pinmux_rw_pe_iop___pe5___width 1
-#define reg_pinmux_rw_pe_iop___pe5___bit 5
-#define reg_pinmux_rw_pe_iop___pe6___lsb 6
-#define reg_pinmux_rw_pe_iop___pe6___width 1
-#define reg_pinmux_rw_pe_iop___pe6___bit 6
-#define reg_pinmux_rw_pe_iop___pe7___lsb 7
-#define reg_pinmux_rw_pe_iop___pe7___width 1
-#define reg_pinmux_rw_pe_iop___pe7___bit 7
-#define reg_pinmux_rw_pe_iop___pe8___lsb 8
-#define reg_pinmux_rw_pe_iop___pe8___width 1
-#define reg_pinmux_rw_pe_iop___pe8___bit 8
-#define reg_pinmux_rw_pe_iop___pe9___lsb 9
-#define reg_pinmux_rw_pe_iop___pe9___width 1
-#define reg_pinmux_rw_pe_iop___pe9___bit 9
-#define reg_pinmux_rw_pe_iop___pe10___lsb 10
-#define reg_pinmux_rw_pe_iop___pe10___width 1
-#define reg_pinmux_rw_pe_iop___pe10___bit 10
-#define reg_pinmux_rw_pe_iop___pe11___lsb 11
-#define reg_pinmux_rw_pe_iop___pe11___width 1
-#define reg_pinmux_rw_pe_iop___pe11___bit 11
-#define reg_pinmux_rw_pe_iop___pe12___lsb 12
-#define reg_pinmux_rw_pe_iop___pe12___width 1
-#define reg_pinmux_rw_pe_iop___pe12___bit 12
-#define reg_pinmux_rw_pe_iop___pe13___lsb 13
-#define reg_pinmux_rw_pe_iop___pe13___width 1
-#define reg_pinmux_rw_pe_iop___pe13___bit 13
-#define reg_pinmux_rw_pe_iop___pe14___lsb 14
-#define reg_pinmux_rw_pe_iop___pe14___width 1
-#define reg_pinmux_rw_pe_iop___pe14___bit 14
-#define reg_pinmux_rw_pe_iop___pe15___lsb 15
-#define reg_pinmux_rw_pe_iop___pe15___width 1
-#define reg_pinmux_rw_pe_iop___pe15___bit 15
-#define reg_pinmux_rw_pe_iop___pe16___lsb 16
-#define reg_pinmux_rw_pe_iop___pe16___width 1
-#define reg_pinmux_rw_pe_iop___pe16___bit 16
-#define reg_pinmux_rw_pe_iop___pe17___lsb 17
-#define reg_pinmux_rw_pe_iop___pe17___width 1
-#define reg_pinmux_rw_pe_iop___pe17___bit 17
-#define reg_pinmux_rw_pe_iop_offset 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
-#define reg_pinmux_rw_usb_phy___en_usb0___width 1
-#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
-#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
-#define reg_pinmux_rw_usb_phy___en_usb1___width 1
-#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
-#define reg_pinmux_rw_usb_phy_offset 40
-
-
-/* Constants */
-#define regk_pinmux_no 0x00000000
-#define regk_pinmux_rw_hwprot_default 0x00000000
-#define regk_pinmux_rw_pa_default 0x00000000
-#define regk_pinmux_rw_pb_gio_default 0x00000000
-#define regk_pinmux_rw_pb_iop_default 0x00000000
-#define regk_pinmux_rw_pc_gio_default 0x00000000
-#define regk_pinmux_rw_pc_iop_default 0x00000000
-#define regk_pinmux_rw_pd_gio_default 0x00000000
-#define regk_pinmux_rw_pd_iop_default 0x00000000
-#define regk_pinmux_rw_pe_gio_default 0x00000000
-#define regk_pinmux_rw_pe_iop_default 0x00000000
-#define regk_pinmux_rw_usb_phy_default 0x00000000
-#define regk_pinmux_yes 0x00000001
-#endif /* __pinmux_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h
deleted file mode 100644
index 412b8748e952..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/fakereg.rmap
- * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
- * last modified: Wed Feb 11 20:53:25 2004
- * file: ../../rtl/global.rmap
- * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
- * last modified: Mon Aug 18 17:08:23 2003
- * file: ../../mod/modreg.rmap
- * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
- * last modified: Fri Feb 20 16:40:04 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-#define regi_artpec_mod 0xb7044000
-#define regi_ata 0xb0032000
-#define regi_ata_mod 0xb7006000
-#define regi_barber 0xb701a000
-#define regi_bif_core 0xb0014000
-#define regi_bif_dma 0xb0016000
-#define regi_bif_slave 0xb0018000
-#define regi_bif_slave_ext 0xac000000
-#define regi_bus_master 0xb703c000
-#define regi_config 0xb003c000
-#define regi_dma0 0xb0000000
-#define regi_dma1 0xb0002000
-#define regi_dma2 0xb0004000
-#define regi_dma3 0xb0006000
-#define regi_dma4 0xb0008000
-#define regi_dma5 0xb000a000
-#define regi_dma6 0xb000c000
-#define regi_dma7 0xb000e000
-#define regi_dma8 0xb0010000
-#define regi_dma9 0xb0012000
-#define regi_eth0 0xb0034000
-#define regi_eth1 0xb0036000
-#define regi_eth_mod 0xb7004000
-#define regi_eth_mod1 0xb701c000
-#define regi_eth_strmod 0xb7008000
-#define regi_eth_strmod1 0xb7032000
-#define regi_ext_dma 0xb703a000
-#define regi_ext_mem 0xb7046000
-#define regi_gen_io 0xb7016000
-#define regi_gio 0xb001a000
-#define regi_hook 0xb7000000
-#define regi_iop 0xb0020000
-#define regi_irq 0xb001c000
-#define regi_irq_nmi 0xb701e000
-#define regi_marb 0xb003e000
-#define regi_marb_bp0 0xb003e240
-#define regi_marb_bp1 0xb003e280
-#define regi_marb_bp2 0xb003e2c0
-#define regi_marb_bp3 0xb003e300
-#define regi_nand_mod 0xb7014000
-#define regi_p21 0xb002e000
-#define regi_p21_mod 0xb7042000
-#define regi_pci_mod 0xb7010000
-#define regi_pin_test 0xb7018000
-#define regi_pinmux 0xb0038000
-#define regi_sdram_chk 0xb703e000
-#define regi_sdram_mod 0xb7012000
-#define regi_ser0 0xb0026000
-#define regi_ser1 0xb0028000
-#define regi_ser2 0xb002a000
-#define regi_ser3 0xb002c000
-#define regi_ser_mod0 0xb7020000
-#define regi_ser_mod1 0xb7022000
-#define regi_ser_mod2 0xb7024000
-#define regi_ser_mod3 0xb7026000
-#define regi_smif_stat 0xb700e000
-#define regi_sser0 0xb0022000
-#define regi_sser1 0xb0024000
-#define regi_sser_mod0 0xb700a000
-#define regi_sser_mod1 0xb700c000
-#define regi_strcop 0xb0030000
-#define regi_strmux 0xb003a000
-#define regi_strmux_tst 0xb7040000
-#define regi_tap 0xb7002000
-#define regi_timer 0xb001e000
-#define regi_timer_mod 0xb7034000
-#define regi_trace 0xb0040000
-#define regi_usb0 0xb7028000
-#define regi_usb1 0xb702a000
-#define regi_usb2 0xb702c000
-#define regi_usb3 0xb702e000
-#define regi_usb_dev 0xb7030000
-#define regi_utmi_mod0 0xb7036000
-#define regi_utmi_mod1 0xb7038000
-#endif /* __reg_map_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h
deleted file mode 100644
index 3eb17cfbdc75..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_asm_h
-#define __timer_defs_asm_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/timer/rtl/timer_regs.r
- * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
- * last modfied: Mon Apr 11 16:09:53 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
- * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
- REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
- REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
- REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
- STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
- ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_tmr0_div, scope timer, type rw */
-#define reg_timer_rw_tmr0_div_offset 0
-
-/* Register r_tmr0_data, scope timer, type r */
-#define reg_timer_r_tmr0_data_offset 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr0_ctrl___op___lsb 0
-#define reg_timer_rw_tmr0_ctrl___op___width 2
-#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr0_ctrl___freq___width 3
-#define reg_timer_rw_tmr0_ctrl_offset 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-#define reg_timer_rw_tmr1_div_offset 16
-
-/* Register r_tmr1_data, scope timer, type r */
-#define reg_timer_r_tmr1_data_offset 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-#define reg_timer_rw_tmr1_ctrl___op___lsb 0
-#define reg_timer_rw_tmr1_ctrl___op___width 2
-#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
-#define reg_timer_rw_tmr1_ctrl___freq___width 3
-#define reg_timer_rw_tmr1_ctrl_offset 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-#define reg_timer_rs_cnt_data___tmr___lsb 0
-#define reg_timer_rs_cnt_data___tmr___width 24
-#define reg_timer_rs_cnt_data___cnt___lsb 24
-#define reg_timer_rs_cnt_data___cnt___width 8
-#define reg_timer_rs_cnt_data_offset 32
-
-/* Register r_cnt_data, scope timer, type r */
-#define reg_timer_r_cnt_data___tmr___lsb 0
-#define reg_timer_r_cnt_data___tmr___width 24
-#define reg_timer_r_cnt_data___cnt___lsb 24
-#define reg_timer_r_cnt_data___cnt___width 8
-#define reg_timer_r_cnt_data_offset 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-#define reg_timer_rw_cnt_cfg___clk___lsb 0
-#define reg_timer_rw_cnt_cfg___clk___width 2
-#define reg_timer_rw_cnt_cfg_offset 40
-
-/* Register rw_trig, scope timer, type rw */
-#define reg_timer_rw_trig_offset 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-#define reg_timer_rw_trig_cfg___tmr___lsb 0
-#define reg_timer_rw_trig_cfg___tmr___width 2
-#define reg_timer_rw_trig_cfg_offset 52
-
-/* Register r_time, scope timer, type r */
-#define reg_timer_r_time_offset 56
-
-/* Register rw_out, scope timer, type rw */
-#define reg_timer_rw_out___tmr___lsb 0
-#define reg_timer_rw_out___tmr___width 2
-#define reg_timer_rw_out_offset 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-#define reg_timer_rw_wd_ctrl___cnt___lsb 0
-#define reg_timer_rw_wd_ctrl___cnt___width 8
-#define reg_timer_rw_wd_ctrl___cmd___lsb 8
-#define reg_timer_rw_wd_ctrl___cmd___width 1
-#define reg_timer_rw_wd_ctrl___cmd___bit 8
-#define reg_timer_rw_wd_ctrl___key___lsb 9
-#define reg_timer_rw_wd_ctrl___key___width 7
-#define reg_timer_rw_wd_ctrl_offset 64
-
-/* Register r_wd_stat, scope timer, type r */
-#define reg_timer_r_wd_stat___cnt___lsb 0
-#define reg_timer_r_wd_stat___cnt___width 8
-#define reg_timer_r_wd_stat___cmd___lsb 8
-#define reg_timer_r_wd_stat___cmd___width 1
-#define reg_timer_r_wd_stat___cmd___bit 8
-#define reg_timer_r_wd_stat_offset 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-#define reg_timer_rw_intr_mask___tmr0___lsb 0
-#define reg_timer_rw_intr_mask___tmr0___width 1
-#define reg_timer_rw_intr_mask___tmr0___bit 0
-#define reg_timer_rw_intr_mask___tmr1___lsb 1
-#define reg_timer_rw_intr_mask___tmr1___width 1
-#define reg_timer_rw_intr_mask___tmr1___bit 1
-#define reg_timer_rw_intr_mask___cnt___lsb 2
-#define reg_timer_rw_intr_mask___cnt___width 1
-#define reg_timer_rw_intr_mask___cnt___bit 2
-#define reg_timer_rw_intr_mask___trig___lsb 3
-#define reg_timer_rw_intr_mask___trig___width 1
-#define reg_timer_rw_intr_mask___trig___bit 3
-#define reg_timer_rw_intr_mask_offset 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-#define reg_timer_rw_ack_intr___tmr0___lsb 0
-#define reg_timer_rw_ack_intr___tmr0___width 1
-#define reg_timer_rw_ack_intr___tmr0___bit 0
-#define reg_timer_rw_ack_intr___tmr1___lsb 1
-#define reg_timer_rw_ack_intr___tmr1___width 1
-#define reg_timer_rw_ack_intr___tmr1___bit 1
-#define reg_timer_rw_ack_intr___cnt___lsb 2
-#define reg_timer_rw_ack_intr___cnt___width 1
-#define reg_timer_rw_ack_intr___cnt___bit 2
-#define reg_timer_rw_ack_intr___trig___lsb 3
-#define reg_timer_rw_ack_intr___trig___width 1
-#define reg_timer_rw_ack_intr___trig___bit 3
-#define reg_timer_rw_ack_intr_offset 76
-
-/* Register r_intr, scope timer, type r */
-#define reg_timer_r_intr___tmr0___lsb 0
-#define reg_timer_r_intr___tmr0___width 1
-#define reg_timer_r_intr___tmr0___bit 0
-#define reg_timer_r_intr___tmr1___lsb 1
-#define reg_timer_r_intr___tmr1___width 1
-#define reg_timer_r_intr___tmr1___bit 1
-#define reg_timer_r_intr___cnt___lsb 2
-#define reg_timer_r_intr___cnt___width 1
-#define reg_timer_r_intr___cnt___bit 2
-#define reg_timer_r_intr___trig___lsb 3
-#define reg_timer_r_intr___trig___width 1
-#define reg_timer_r_intr___trig___bit 3
-#define reg_timer_r_intr_offset 80
-
-/* Register r_masked_intr, scope timer, type r */
-#define reg_timer_r_masked_intr___tmr0___lsb 0
-#define reg_timer_r_masked_intr___tmr0___width 1
-#define reg_timer_r_masked_intr___tmr0___bit 0
-#define reg_timer_r_masked_intr___tmr1___lsb 1
-#define reg_timer_r_masked_intr___tmr1___width 1
-#define reg_timer_r_masked_intr___tmr1___bit 1
-#define reg_timer_r_masked_intr___cnt___lsb 2
-#define reg_timer_r_masked_intr___cnt___width 1
-#define reg_timer_r_masked_intr___cnt___bit 2
-#define reg_timer_r_masked_intr___trig___lsb 3
-#define reg_timer_r_masked_intr___trig___width 1
-#define reg_timer_r_masked_intr___trig___bit 3
-#define reg_timer_r_masked_intr_offset 84
-
-/* Register rw_test, scope timer, type rw */
-#define reg_timer_rw_test___dis___lsb 0
-#define reg_timer_rw_test___dis___width 1
-#define reg_timer_rw_test___dis___bit 0
-#define reg_timer_rw_test___en___lsb 1
-#define reg_timer_rw_test___en___width 1
-#define reg_timer_rw_test___en___bit 1
-#define reg_timer_rw_test_offset 88
-
-
-/* Constants */
-#define regk_timer_ext 0x00000001
-#define regk_timer_f100 0x00000007
-#define regk_timer_f29_493 0x00000004
-#define regk_timer_f32 0x00000005
-#define regk_timer_f32_768 0x00000006
-#define regk_timer_hold 0x00000001
-#define regk_timer_ld 0x00000000
-#define regk_timer_no 0x00000000
-#define regk_timer_off 0x00000000
-#define regk_timer_run 0x00000002
-#define regk_timer_rw_cnt_cfg_default 0x00000000
-#define regk_timer_rw_intr_mask_default 0x00000000
-#define regk_timer_rw_out_default 0x00000000
-#define regk_timer_rw_test_default 0x00000000
-#define regk_timer_rw_tmr0_ctrl_default 0x00000000
-#define regk_timer_rw_tmr1_ctrl_default 0x00000000
-#define regk_timer_rw_trig_cfg_default 0x00000000
-#define regk_timer_start 0x00000001
-#define regk_timer_stop 0x00000000
-#define regk_timer_time 0x00000001
-#define regk_timer_tmr0 0x00000002
-#define regk_timer_tmr1 0x00000003
-#define regk_timer_yes 0x00000001
-#endif /* __timer_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h
deleted file mode 100644
index a9ffb7edaf91..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_core_defs_h
-#define __bif_core_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_core_regs.r
- * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
- * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_core */
-
-/* Register rw_grp1_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp1_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
-#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
-
-/* Register rw_grp2_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 10;
-} reg_bif_core_rw_grp2_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
-#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
-
-/* Register rw_grp3_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 2;
- unsigned int gated_csp0 : 2;
- unsigned int gated_csp1 : 2;
- unsigned int gated_csp2 : 2;
- unsigned int gated_csp3 : 2;
-} reg_bif_core_rw_grp3_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
-#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
-
-/* Register rw_grp4_cfg, scope bif_core, type rw */
-typedef struct {
- unsigned int lw : 6;
- unsigned int ew : 3;
- unsigned int zw : 3;
- unsigned int aw : 2;
- unsigned int dw : 2;
- unsigned int ewb : 2;
- unsigned int bw : 1;
- unsigned int wr_extend : 1;
- unsigned int erc_en : 1;
- unsigned int mode : 1;
- unsigned int dummy1 : 4;
- unsigned int gated_csp4 : 2;
- unsigned int gated_csp5 : 2;
- unsigned int gated_csp6 : 2;
-} reg_bif_core_rw_grp4_cfg;
-#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
-#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
-
-/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int grp_sel : 5;
- unsigned int dummy1 : 12;
-} reg_bif_core_rw_sdram_cfg_grp0;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
-
-/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
-typedef struct {
- unsigned int bank_sel : 5;
- unsigned int ca : 3;
- unsigned int type : 1;
- unsigned int bw : 1;
- unsigned int sh : 3;
- unsigned int wmm : 1;
- unsigned int sh16 : 1;
- unsigned int dummy1 : 17;
-} reg_bif_core_rw_sdram_cfg_grp1;
-#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
-#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
-
-/* Register rw_sdram_timing, scope bif_core, type rw */
-typedef struct {
- unsigned int cl : 3;
- unsigned int rcd : 3;
- unsigned int rp : 3;
- unsigned int rc : 2;
- unsigned int dpl : 2;
- unsigned int pde : 1;
- unsigned int ref : 2;
- unsigned int cpd : 1;
- unsigned int sdcke : 1;
- unsigned int sdclk : 1;
- unsigned int dummy1 : 13;
-} reg_bif_core_rw_sdram_timing;
-#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
-#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
-
-/* Register rw_sdram_cmd, scope bif_core, type rw */
-typedef struct {
- unsigned int cmd : 3;
- unsigned int mrs_data : 15;
- unsigned int dummy1 : 14;
-} reg_bif_core_rw_sdram_cmd;
-#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
-#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
-
-/* Register rs_sdram_ref_stat, scope bif_core, type rs */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_rs_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
-
-/* Register r_sdram_ref_stat, scope bif_core, type r */
-typedef struct {
- unsigned int ok : 1;
- unsigned int dummy1 : 31;
-} reg_bif_core_r_sdram_ref_stat;
-#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
-
-
-/* Constants */
-enum {
- regk_bif_core_bank2 = 0x00000000,
- regk_bif_core_bank4 = 0x00000001,
- regk_bif_core_bit10 = 0x0000000a,
- regk_bif_core_bit11 = 0x0000000b,
- regk_bif_core_bit12 = 0x0000000c,
- regk_bif_core_bit13 = 0x0000000d,
- regk_bif_core_bit14 = 0x0000000e,
- regk_bif_core_bit15 = 0x0000000f,
- regk_bif_core_bit16 = 0x00000010,
- regk_bif_core_bit17 = 0x00000011,
- regk_bif_core_bit18 = 0x00000012,
- regk_bif_core_bit19 = 0x00000013,
- regk_bif_core_bit20 = 0x00000014,
- regk_bif_core_bit21 = 0x00000015,
- regk_bif_core_bit22 = 0x00000016,
- regk_bif_core_bit23 = 0x00000017,
- regk_bif_core_bit24 = 0x00000018,
- regk_bif_core_bit25 = 0x00000019,
- regk_bif_core_bit26 = 0x0000001a,
- regk_bif_core_bit27 = 0x0000001b,
- regk_bif_core_bit28 = 0x0000001c,
- regk_bif_core_bit29 = 0x0000001d,
- regk_bif_core_bit9 = 0x00000009,
- regk_bif_core_bw16 = 0x00000001,
- regk_bif_core_bw32 = 0x00000000,
- regk_bif_core_bwe = 0x00000000,
- regk_bif_core_cwe = 0x00000001,
- regk_bif_core_e15us = 0x00000001,
- regk_bif_core_e7800ns = 0x00000002,
- regk_bif_core_grp0 = 0x00000000,
- regk_bif_core_grp1 = 0x00000001,
- regk_bif_core_mrs = 0x00000003,
- regk_bif_core_no = 0x00000000,
- regk_bif_core_none = 0x00000000,
- regk_bif_core_nop = 0x00000000,
- regk_bif_core_off = 0x00000000,
- regk_bif_core_pre = 0x00000002,
- regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rd = 0x00000002,
- regk_bif_core_ref = 0x00000001,
- regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
- regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
- regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
- regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
- regk_bif_core_slf = 0x00000004,
- regk_bif_core_wr = 0x00000001,
- regk_bif_core_yes = 0x00000001
-};
-#endif /* __bif_core_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h
deleted file mode 100644
index d1fa172f58f4..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_dma_defs_h
-#define __bif_dma_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_dma_regs.r
- * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
- * last modfied: Mon Apr 11 16:06:33 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
- * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_dma */
-
-/* Register rw_ch0_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch0_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
-#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
-
-/* Register rw_ch0_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch0_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
-#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
-
-/* Register rw_ch0_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch0_start;
-#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
-#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
-
-/* Register rw_ch0_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch0_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
-#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
-
-/* Register r_ch0_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch0_stat;
-#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
-
-/* Register rw_ch1_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch1_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
-#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
-
-/* Register rw_ch1_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch1_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
-#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
-
-/* Register rw_ch1_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch1_start;
-#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
-#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
-
-/* Register rw_ch1_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch1_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
-#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
-
-/* Register r_ch1_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch1_stat;
-#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
-
-/* Register rw_ch2_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_pad : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int wr_all : 1;
- unsigned int dummy1 : 12;
-} reg_bif_dma_rw_ch2_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
-#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
-
-/* Register rw_ch2_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch2_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
-#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
-
-/* Register rw_ch2_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch2_start;
-#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
-#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
-
-/* Register rw_ch2_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch2_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
-#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
-
-/* Register r_ch2_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch2_stat;
-#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
-
-/* Register rw_ch3_ctrl, scope bif_dma, type rw */
-typedef struct {
- unsigned int bw : 2;
- unsigned int burst_len : 1;
- unsigned int cont : 1;
- unsigned int end_discard : 1;
- unsigned int cnt : 1;
- unsigned int dreq_pin : 3;
- unsigned int dreq_mode : 2;
- unsigned int tc_in_pin : 3;
- unsigned int tc_in_mode : 2;
- unsigned int bus_mode : 2;
- unsigned int rate_en : 1;
- unsigned int dummy1 : 13;
-} reg_bif_dma_rw_ch3_ctrl;
-#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
-#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
-
-/* Register rw_ch3_addr, scope bif_dma, type rw */
-typedef struct {
- unsigned int addr : 32;
-} reg_bif_dma_rw_ch3_addr;
-#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
-#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
-
-/* Register rw_ch3_start, scope bif_dma, type rw */
-typedef struct {
- unsigned int run : 1;
- unsigned int dummy1 : 31;
-} reg_bif_dma_rw_ch3_start;
-#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
-#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
-
-/* Register rw_ch3_cnt, scope bif_dma, type rw */
-typedef struct {
- unsigned int start_cnt : 16;
- unsigned int dummy1 : 16;
-} reg_bif_dma_rw_ch3_cnt;
-#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
-#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
-
-/* Register r_ch3_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int cnt : 16;
- unsigned int dummy1 : 15;
- unsigned int run : 1;
-} reg_bif_dma_r_ch3_stat;
-#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
-
-/* Register rw_intr_mask, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_intr_mask;
-#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
-#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
-
-/* Register rw_ack_intr, scope bif_dma, type rw */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_rw_ack_intr;
-#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
-#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
-
-/* Register r_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_intr;
-#define REG_RD_ADDR_bif_dma_r_intr 136
-
-/* Register r_masked_intr, scope bif_dma, type r */
-typedef struct {
- unsigned int ext_dma0 : 1;
- unsigned int ext_dma1 : 1;
- unsigned int ext_dma2 : 1;
- unsigned int ext_dma3 : 1;
- unsigned int dummy1 : 28;
-} reg_bif_dma_r_masked_intr;
-#define REG_RD_ADDR_bif_dma_r_masked_intr 140
-
-/* Register rw_pin0_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin0_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
-#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
-
-/* Register rw_pin1_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin1_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
-#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
-
-/* Register rw_pin2_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin2_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
-#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
-
-/* Register rw_pin3_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin3_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
-#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
-
-/* Register rw_pin4_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin4_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
-#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
-
-/* Register rw_pin5_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin5_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
-#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
-
-/* Register rw_pin6_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin6_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
-#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
-
-/* Register rw_pin7_cfg, scope bif_dma, type rw */
-typedef struct {
- unsigned int master_ch : 2;
- unsigned int master_mode : 3;
- unsigned int slave_ch : 2;
- unsigned int slave_mode : 3;
- unsigned int dummy1 : 22;
-} reg_bif_dma_rw_pin7_cfg;
-#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
-#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
-
-/* Register r_pin_stat, scope bif_dma, type r */
-typedef struct {
- unsigned int pin0 : 1;
- unsigned int pin1 : 1;
- unsigned int pin2 : 1;
- unsigned int pin3 : 1;
- unsigned int pin4 : 1;
- unsigned int pin5 : 1;
- unsigned int pin6 : 1;
- unsigned int pin7 : 1;
- unsigned int dummy1 : 24;
-} reg_bif_dma_r_pin_stat;
-#define REG_RD_ADDR_bif_dma_r_pin_stat 192
-
-
-/* Constants */
-enum {
- regk_bif_dma_as_master = 0x00000001,
- regk_bif_dma_as_slave = 0x00000001,
- regk_bif_dma_burst1 = 0x00000000,
- regk_bif_dma_burst8 = 0x00000001,
- regk_bif_dma_bw16 = 0x00000001,
- regk_bif_dma_bw32 = 0x00000002,
- regk_bif_dma_bw8 = 0x00000000,
- regk_bif_dma_dack = 0x00000006,
- regk_bif_dma_dack_inv = 0x00000007,
- regk_bif_dma_force = 0x00000001,
- regk_bif_dma_hi = 0x00000003,
- regk_bif_dma_inv = 0x00000003,
- regk_bif_dma_lo = 0x00000002,
- regk_bif_dma_master = 0x00000001,
- regk_bif_dma_no = 0x00000000,
- regk_bif_dma_norm = 0x00000002,
- regk_bif_dma_off = 0x00000000,
- regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch0_start_default = 0x00000000,
- regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch1_start_default = 0x00000000,
- regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch2_start_default = 0x00000000,
- regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
- regk_bif_dma_rw_ch3_start_default = 0x00000000,
- regk_bif_dma_rw_intr_mask_default = 0x00000000,
- regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
- regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
- regk_bif_dma_slave = 0x00000002,
- regk_bif_dma_sreq = 0x00000006,
- regk_bif_dma_sreq_inv = 0x00000007,
- regk_bif_dma_tc = 0x00000004,
- regk_bif_dma_tc_inv = 0x00000005,
- regk_bif_dma_yes = 0x00000001
-};
-#endif /* __bif_dma_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h
deleted file mode 100644
index a8d7cc528546..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __bif_slave_defs_h
-#define __bif_slave_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/bif/rtl/bif_slave_regs.r
- * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
- * last modfied: Mon Apr 11 16:06:34 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
- * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope bif_slave */
-
-/* Register rw_slave_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int slave_id : 3;
- unsigned int use_slave_id : 1;
- unsigned int boot_rdy : 1;
- unsigned int loopback : 1;
- unsigned int dis : 1;
- unsigned int dummy1 : 25;
-} reg_bif_slave_rw_slave_cfg;
-#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
-#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
-
-/* Register r_slave_mode, scope bif_slave, type r */
-typedef struct {
- unsigned int ch0_mode : 1;
- unsigned int ch1_mode : 1;
- unsigned int ch2_mode : 1;
- unsigned int ch3_mode : 1;
- unsigned int dummy1 : 28;
-} reg_bif_slave_r_slave_mode;
-#define REG_RD_ADDR_bif_slave_r_slave_mode 4
-
-/* Register rw_ch0_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch0_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
-#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
-
-/* Register rw_ch1_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch1_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
-#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
-
-/* Register rw_ch2_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch2_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
-#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
-
-/* Register rw_ch3_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int rd_hold : 2;
- unsigned int access_mode : 1;
- unsigned int access_ctrl : 1;
- unsigned int data_cs : 2;
- unsigned int dummy1 : 26;
-} reg_bif_slave_rw_ch3_cfg;
-#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
-#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
-
-/* Register rw_arb_cfg, scope bif_slave, type rw */
-typedef struct {
- unsigned int brin_mode : 1;
- unsigned int brout_mode : 3;
- unsigned int bg_mode : 3;
- unsigned int release : 2;
- unsigned int acquire : 1;
- unsigned int settle_time : 2;
- unsigned int dram_ctrl : 1;
- unsigned int dummy1 : 19;
-} reg_bif_slave_rw_arb_cfg;
-#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
-#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
-
-/* Register r_arb_stat, scope bif_slave, type r */
-typedef struct {
- unsigned int init_mode : 1;
- unsigned int mode : 1;
- unsigned int brin : 1;
- unsigned int brout : 1;
- unsigned int bg : 1;
- unsigned int dummy1 : 27;
-} reg_bif_slave_r_arb_stat;
-#define REG_RD_ADDR_bif_slave_r_arb_stat 36
-
-/* Register rw_intr_mask, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_intr_mask;
-#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
-#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
-
-/* Register rw_ack_intr, scope bif_slave, type rw */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_rw_ack_intr;
-#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
-#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
-
-/* Register r_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_intr;
-#define REG_RD_ADDR_bif_slave_r_intr 72
-
-/* Register r_masked_intr, scope bif_slave, type r */
-typedef struct {
- unsigned int bus_release : 1;
- unsigned int bus_acquire : 1;
- unsigned int dummy1 : 30;
-} reg_bif_slave_r_masked_intr;
-#define REG_RD_ADDR_bif_slave_r_masked_intr 76
-
-
-/* Constants */
-enum {
- regk_bif_slave_active_hi = 0x00000003,
- regk_bif_slave_active_lo = 0x00000002,
- regk_bif_slave_addr = 0x00000000,
- regk_bif_slave_always = 0x00000001,
- regk_bif_slave_at_idle = 0x00000002,
- regk_bif_slave_burst_end = 0x00000003,
- regk_bif_slave_dma = 0x00000001,
- regk_bif_slave_hi = 0x00000003,
- regk_bif_slave_inv = 0x00000001,
- regk_bif_slave_lo = 0x00000002,
- regk_bif_slave_local = 0x00000001,
- regk_bif_slave_master = 0x00000000,
- regk_bif_slave_mode_reg = 0x00000001,
- regk_bif_slave_no = 0x00000000,
- regk_bif_slave_norm = 0x00000000,
- regk_bif_slave_on_access = 0x00000000,
- regk_bif_slave_rw_arb_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
- regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
- regk_bif_slave_rw_intr_mask_default = 0x00000000,
- regk_bif_slave_rw_slave_cfg_default = 0x00000000,
- regk_bif_slave_shared = 0x00000000,
- regk_bif_slave_slave = 0x00000001,
- regk_bif_slave_t0ns = 0x00000003,
- regk_bif_slave_t10ns = 0x00000002,
- regk_bif_slave_t20ns = 0x00000003,
- regk_bif_slave_t30ns = 0x00000002,
- regk_bif_slave_t40ns = 0x00000001,
- regk_bif_slave_t50ns = 0x00000000,
- regk_bif_slave_yes = 0x00000001,
- regk_bif_slave_z = 0x00000004
-};
-#endif /* __bif_slave_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h
deleted file mode 100644
index cc8b20d17237..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __config_defs_h
-#define __config_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../rtl/config_regs.r
- * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
- * last modfied: Thu Mar 4 12:34:39 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
- * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope config */
-
-/* Register r_bootsel, scope config, type r */
-typedef struct {
- unsigned int boot_mode : 3;
- unsigned int full_duplex : 1;
- unsigned int user : 1;
- unsigned int pll : 1;
- unsigned int flash_bw : 1;
- unsigned int dummy1 : 25;
-} reg_config_r_bootsel;
-#define REG_RD_ADDR_config_r_bootsel 0
-
-/* Register rw_clk_ctrl, scope config, type rw */
-typedef struct {
- unsigned int pll : 1;
- unsigned int cpu : 1;
- unsigned int iop : 1;
- unsigned int dma01_eth0 : 1;
- unsigned int dma23 : 1;
- unsigned int dma45 : 1;
- unsigned int dma67 : 1;
- unsigned int dma89_strcop : 1;
- unsigned int bif : 1;
- unsigned int fix_io : 1;
- unsigned int dummy1 : 22;
-} reg_config_rw_clk_ctrl;
-#define REG_RD_ADDR_config_rw_clk_ctrl 4
-#define REG_WR_ADDR_config_rw_clk_ctrl 4
-
-/* Register rw_pad_ctrl, scope config, type rw */
-typedef struct {
- unsigned int usb_susp : 1;
- unsigned int phyrst_n : 1;
- unsigned int dummy1 : 30;
-} reg_config_rw_pad_ctrl;
-#define REG_RD_ADDR_config_rw_pad_ctrl 8
-#define REG_WR_ADDR_config_rw_pad_ctrl 8
-
-
-/* Constants */
-enum {
- regk_config_bw16 = 0x00000000,
- regk_config_bw32 = 0x00000001,
- regk_config_master = 0x00000005,
- regk_config_nand = 0x00000003,
- regk_config_net_rx = 0x00000001,
- regk_config_net_tx_rx = 0x00000002,
- regk_config_no = 0x00000000,
- regk_config_none = 0x00000007,
- regk_config_nor = 0x00000000,
- regk_config_rw_clk_ctrl_default = 0x00000002,
- regk_config_rw_pad_ctrl_default = 0x00000000,
- regk_config_ser = 0x00000004,
- regk_config_slave = 0x00000006,
- regk_config_yes = 0x00000001
-};
-#endif /* __config_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h
deleted file mode 100644
index da0b1103b66d..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __gio_defs_h
-#define __gio_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/gio/rtl/gio_regs.r
- * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
- * last modfied: Mon Apr 11 16:07:47 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
- * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope gio */
-
-/* Register rw_pa_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_dout;
-#define REG_RD_ADDR_gio_rw_pa_dout 0
-#define REG_WR_ADDR_gio_rw_pa_dout 0
-
-/* Register r_pa_din, scope gio, type r */
-typedef struct {
- unsigned int data : 8;
- unsigned int dummy1 : 24;
-} reg_gio_r_pa_din;
-#define REG_RD_ADDR_gio_r_pa_din 4
-
-/* Register rw_pa_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 8;
- unsigned int dummy1 : 24;
-} reg_gio_rw_pa_oe;
-#define REG_RD_ADDR_gio_rw_pa_oe 8
-#define REG_WR_ADDR_gio_rw_pa_oe 8
-
-/* Register rw_intr_cfg, scope gio, type rw */
-typedef struct {
- unsigned int pa0 : 3;
- unsigned int pa1 : 3;
- unsigned int pa2 : 3;
- unsigned int pa3 : 3;
- unsigned int pa4 : 3;
- unsigned int pa5 : 3;
- unsigned int pa6 : 3;
- unsigned int pa7 : 3;
- unsigned int dummy1 : 8;
-} reg_gio_rw_intr_cfg;
-#define REG_RD_ADDR_gio_rw_intr_cfg 12
-#define REG_WR_ADDR_gio_rw_intr_cfg 12
-
-/* Register rw_intr_mask, scope gio, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_rw_intr_mask;
-#define REG_RD_ADDR_gio_rw_intr_mask 16
-#define REG_WR_ADDR_gio_rw_intr_mask 16
-
-/* Register rw_ack_intr, scope gio, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_rw_ack_intr;
-#define REG_RD_ADDR_gio_rw_ack_intr 20
-#define REG_WR_ADDR_gio_rw_ack_intr 20
-
-/* Register r_intr, scope gio, type r */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_r_intr;
-#define REG_RD_ADDR_gio_r_intr 24
-
-/* Register r_masked_intr, scope gio, type r */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int dummy1 : 24;
-} reg_gio_r_masked_intr;
-#define REG_RD_ADDR_gio_r_masked_intr 28
-
-/* Register rw_pb_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pb_dout;
-#define REG_RD_ADDR_gio_rw_pb_dout 32
-#define REG_WR_ADDR_gio_rw_pb_dout 32
-
-/* Register r_pb_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pb_din;
-#define REG_RD_ADDR_gio_r_pb_din 36
-
-/* Register rw_pb_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pb_oe;
-#define REG_RD_ADDR_gio_rw_pb_oe 40
-#define REG_WR_ADDR_gio_rw_pb_oe 40
-
-/* Register rw_pc_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pc_dout;
-#define REG_RD_ADDR_gio_rw_pc_dout 48
-#define REG_WR_ADDR_gio_rw_pc_dout 48
-
-/* Register r_pc_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pc_din;
-#define REG_RD_ADDR_gio_r_pc_din 52
-
-/* Register rw_pc_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pc_oe;
-#define REG_RD_ADDR_gio_rw_pc_oe 56
-#define REG_WR_ADDR_gio_rw_pc_oe 56
-
-/* Register rw_pd_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pd_dout;
-#define REG_RD_ADDR_gio_rw_pd_dout 64
-#define REG_WR_ADDR_gio_rw_pd_dout 64
-
-/* Register r_pd_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pd_din;
-#define REG_RD_ADDR_gio_r_pd_din 68
-
-/* Register rw_pd_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pd_oe;
-#define REG_RD_ADDR_gio_rw_pd_oe 72
-#define REG_WR_ADDR_gio_rw_pd_oe 72
-
-/* Register rw_pe_dout, scope gio, type rw */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pe_dout;
-#define REG_RD_ADDR_gio_rw_pe_dout 80
-#define REG_WR_ADDR_gio_rw_pe_dout 80
-
-/* Register r_pe_din, scope gio, type r */
-typedef struct {
- unsigned int data : 18;
- unsigned int dummy1 : 14;
-} reg_gio_r_pe_din;
-#define REG_RD_ADDR_gio_r_pe_din 84
-
-/* Register rw_pe_oe, scope gio, type rw */
-typedef struct {
- unsigned int oe : 18;
- unsigned int dummy1 : 14;
-} reg_gio_rw_pe_oe;
-#define REG_RD_ADDR_gio_rw_pe_oe 88
-#define REG_WR_ADDR_gio_rw_pe_oe 88
-
-
-/* Constants */
-enum {
- regk_gio_anyedge = 0x00000007,
- regk_gio_hi = 0x00000001,
- regk_gio_lo = 0x00000002,
- regk_gio_negedge = 0x00000006,
- regk_gio_no = 0x00000000,
- regk_gio_off = 0x00000000,
- regk_gio_posedge = 0x00000005,
- regk_gio_rw_intr_cfg_default = 0x00000000,
- regk_gio_rw_intr_mask_default = 0x00000000,
- regk_gio_rw_pa_oe_default = 0x00000000,
- regk_gio_rw_pb_oe_default = 0x00000000,
- regk_gio_rw_pc_oe_default = 0x00000000,
- regk_gio_rw_pd_oe_default = 0x00000000,
- regk_gio_rw_pe_oe_default = 0x00000000,
- regk_gio_set = 0x00000003,
- regk_gio_yes = 0x00000001
-};
-#endif /* __gio_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h
deleted file mode 100644
index ea752a2d8ee2..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
- from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
-version . */
-
-#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
-#define MEMARB_INTR_VECT 0x31
-#define GEN_IO_INTR_VECT 0x32
-#define GIO_INTR_VECT GEN_IO_INTR_VECT
-#define IOP0_INTR_VECT 0x33
-#define IOP1_INTR_VECT 0x34
-#define IOP2_INTR_VECT 0x35
-#define IOP3_INTR_VECT 0x36
-#define DMA0_INTR_VECT 0x37
-#define DMA1_INTR_VECT 0x38
-#define DMA2_INTR_VECT 0x39
-#define DMA3_INTR_VECT 0x3a
-#define DMA4_INTR_VECT 0x3b
-#define DMA5_INTR_VECT 0x3c
-#define DMA6_INTR_VECT 0x3d
-#define DMA7_INTR_VECT 0x3e
-#define DMA8_INTR_VECT 0x3f
-#define DMA9_INTR_VECT 0x40
-#define ATA_INTR_VECT 0x41
-#define SSER0_INTR_VECT 0x42
-#define SSER1_INTR_VECT 0x43
-#define SER0_INTR_VECT 0x44
-#define SER1_INTR_VECT 0x45
-#define SER2_INTR_VECT 0x46
-#define SER3_INTR_VECT 0x47
-#define P21_INTR_VECT 0x48
-#define ETH0_INTR_VECT 0x49
-#define ETH1_INTR_VECT 0x4a
-#define TIMER_INTR_VECT 0x4b
-#define TIMER0_INTR_VECT TIMER_INTR_VECT
-#define BIF_ARB_INTR_VECT 0x4c
-#define BIF_DMA_INTR_VECT 0x4d
-#define EXT_INTR_VECT 0x4e
-#define IPI_INTR_VECT 0x4f
-#define NBR_INTR_VECT 0x50
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h
deleted file mode 100644
index 11ebd66585cd..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __intr_vect_defs_h
-#define __intr_vect_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
- * last modfied: Mon Apr 11 16:08:03 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope intr_vect */
-
-#define STRIDE_intr_vect_rw_mask 0
-/* Register rw_mask, scope intr_vect, type rw */
-typedef struct {
- unsigned int memarb : 1;
- unsigned int gen_io : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int iop2 : 1;
- unsigned int iop3 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int ata : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int p21 : 1;
- unsigned int eth0 : 1;
- unsigned int eth1 : 1;
- unsigned int timer0 : 1;
- unsigned int bif_arb : 1;
- unsigned int bif_dma : 1;
- unsigned int ext : 1;
- unsigned int dummy1 : 2;
-} reg_intr_vect_rw_mask;
-#define REG_RD_ADDR_intr_vect_rw_mask 0
-#define REG_WR_ADDR_intr_vect_rw_mask 0
-
-#define STRIDE_intr_vect_r_vect 0
-/* Register r_vect, scope intr_vect, type r */
-typedef struct {
- unsigned int memarb : 1;
- unsigned int gen_io : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int iop2 : 1;
- unsigned int iop3 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int ata : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int p21 : 1;
- unsigned int eth0 : 1;
- unsigned int eth1 : 1;
- unsigned int timer : 1;
- unsigned int bif_arb : 1;
- unsigned int bif_dma : 1;
- unsigned int ext : 1;
- unsigned int dummy1 : 2;
-} reg_intr_vect_r_vect;
-#define REG_RD_ADDR_intr_vect_r_vect 4
-
-#define STRIDE_intr_vect_r_masked_vect 0
-/* Register r_masked_vect, scope intr_vect, type r */
-typedef struct {
- unsigned int memarb : 1;
- unsigned int gen_io : 1;
- unsigned int iop0 : 1;
- unsigned int iop1 : 1;
- unsigned int iop2 : 1;
- unsigned int iop3 : 1;
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int ata : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ser0 : 1;
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int p21 : 1;
- unsigned int eth0 : 1;
- unsigned int eth1 : 1;
- unsigned int timer : 1;
- unsigned int bif_arb : 1;
- unsigned int bif_dma : 1;
- unsigned int ext : 1;
- unsigned int dummy1 : 2;
-} reg_intr_vect_r_masked_vect;
-#define REG_RD_ADDR_intr_vect_r_masked_vect 8
-
-/* Register r_nmi, scope intr_vect, type r */
-typedef struct {
- unsigned int ext : 1;
- unsigned int watchdog : 1;
- unsigned int dummy1 : 30;
-} reg_intr_vect_r_nmi;
-#define REG_RD_ADDR_intr_vect_r_nmi 12
-
-/* Register r_guru, scope intr_vect, type r */
-typedef struct {
- unsigned int jtag : 1;
- unsigned int dummy1 : 31;
-} reg_intr_vect_r_guru;
-#define REG_RD_ADDR_intr_vect_r_guru 16
-
-/* Register rw_ipi, scope intr_vect, type rw */
-typedef struct
-{
- unsigned int vector;
-} reg_intr_vect_rw_ipi;
-#define REG_RD_ADDR_intr_vect_rw_ipi 20
-#define REG_WR_ADDR_intr_vect_rw_ipi 20
-
-/* Constants */
-enum {
- regk_intr_vect_off = 0x00000000,
- regk_intr_vect_on = 0x00000001,
- regk_intr_vect_rw_mask_default = 0x00000000
-};
-#endif /* __intr_vect_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h
deleted file mode 100644
index fb7e20d77591..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Fri Nov 7 15:36:04 2003
- *
- * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_break_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_addr;
-#define REG_RD_ADDR_marb_bp_r_break_addr 20
-
-/* Register r_break_op, scope marb_bp, type r */
-typedef struct {
- unsigned int read : 1;
- unsigned int write : 1;
- unsigned int read_excl : 1;
- unsigned int pri_write : 1;
- unsigned int us_read : 1;
- unsigned int us_write : 1;
- unsigned int us_read_excl : 1;
- unsigned int us_pri_write : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_break_op;
-#define REG_RD_ADDR_marb_bp_r_break_op 24
-
-/* Register r_break_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_clients;
-#define REG_RD_ADDR_marb_bp_r_break_clients 28
-
-/* Register r_break_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_break_first_client;
-#define REG_RD_ADDR_marb_bp_r_break_first_client 32
-
-/* Register r_break_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_break_size;
-#define REG_RD_ADDR_marb_bp_r_break_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h
deleted file mode 100644
index 872a7942916a..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __marb_defs_h
-#define __marb_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb */
-
-#define STRIDE_marb_rw_int_slots 4
-/* Register rw_int_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_int_slots;
-#define REG_RD_ADDR_marb_rw_int_slots 0
-#define REG_WR_ADDR_marb_rw_int_slots 0
-
-#define STRIDE_marb_rw_ext_slots 4
-/* Register rw_ext_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ext_slots;
-#define REG_RD_ADDR_marb_rw_ext_slots 256
-#define REG_WR_ADDR_marb_rw_ext_slots 256
-
-#define STRIDE_marb_rw_regs_slots 4
-/* Register rw_regs_slots, scope marb, type rw */
-typedef struct {
- unsigned int owner : 4;
- unsigned int dummy1 : 28;
-} reg_marb_rw_regs_slots;
-#define REG_RD_ADDR_marb_rw_regs_slots 512
-#define REG_WR_ADDR_marb_rw_regs_slots 512
-
-/* Register rw_intr_mask, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_intr_mask;
-#define REG_RD_ADDR_marb_rw_intr_mask 528
-#define REG_WR_ADDR_marb_rw_intr_mask 528
-
-/* Register rw_ack_intr, scope marb, type rw */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_rw_ack_intr;
-#define REG_RD_ADDR_marb_rw_ack_intr 532
-#define REG_WR_ADDR_marb_rw_ack_intr 532
-
-/* Register r_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_intr;
-#define REG_RD_ADDR_marb_r_intr 536
-
-/* Register r_masked_intr, scope marb, type r */
-typedef struct {
- unsigned int bp0 : 1;
- unsigned int bp1 : 1;
- unsigned int bp2 : 1;
- unsigned int bp3 : 1;
- unsigned int dummy1 : 28;
-} reg_marb_r_masked_intr;
-#define REG_RD_ADDR_marb_r_masked_intr 540
-
-/* Register rw_stop_mask, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_stop_mask;
-#define REG_RD_ADDR_marb_rw_stop_mask 544
-#define REG_WR_ADDR_marb_rw_stop_mask 544
-
-/* Register r_stopped, scope marb, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_r_stopped;
-#define REG_RD_ADDR_marb_r_stopped 548
-
-/* Register rw_no_snoop, scope marb, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_rw_no_snoop;
-#define REG_RD_ADDR_marb_rw_no_snoop 832
-#define REG_WR_ADDR_marb_rw_no_snoop 832
-
-/* Register rw_no_snoop_rq, scope marb, type rw */
-typedef struct {
- unsigned int dummy1 : 10;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int dummy2 : 20;
-} reg_marb_rw_no_snoop_rq;
-#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
-#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
-
-
-/* Constants */
-enum {
- regk_marb_cpud = 0x0000000b,
- regk_marb_cpui = 0x0000000a,
- regk_marb_dma0 = 0x00000000,
- regk_marb_dma1 = 0x00000001,
- regk_marb_dma2 = 0x00000002,
- regk_marb_dma3 = 0x00000003,
- regk_marb_dma4 = 0x00000004,
- regk_marb_dma5 = 0x00000005,
- regk_marb_dma6 = 0x00000006,
- regk_marb_dma7 = 0x00000007,
- regk_marb_dma8 = 0x00000008,
- regk_marb_dma9 = 0x00000009,
- regk_marb_iop = 0x0000000c,
- regk_marb_no = 0x00000000,
- regk_marb_r_stopped_default = 0x00000000,
- regk_marb_rw_ext_slots_default = 0x00000000,
- regk_marb_rw_ext_slots_size = 0x00000040,
- regk_marb_rw_int_slots_default = 0x00000000,
- regk_marb_rw_int_slots_size = 0x00000040,
- regk_marb_rw_intr_mask_default = 0x00000000,
- regk_marb_rw_no_snoop_default = 0x00000000,
- regk_marb_rw_no_snoop_rq_default = 0x00000000,
- regk_marb_rw_regs_slots_default = 0x00000000,
- regk_marb_rw_regs_slots_size = 0x00000004,
- regk_marb_rw_stop_mask_default = 0x00000000,
- regk_marb_slave = 0x0000000d,
- regk_marb_yes = 0x00000001
-};
-#endif /* __marb_defs_h */
-#ifndef __marb_bp_defs_h
-#define __marb_bp_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/memarb/rtl/guinness/marb_top.r
- * id: <not found>
- * last modfied: Mon Apr 11 16:12:16 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
- * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope marb_bp */
-
-/* Register rw_first_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_first_addr;
-#define REG_RD_ADDR_marb_bp_rw_first_addr 0
-#define REG_WR_ADDR_marb_bp_rw_first_addr 0
-
-/* Register rw_last_addr, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_last_addr;
-#define REG_RD_ADDR_marb_bp_rw_last_addr 4
-#define REG_WR_ADDR_marb_bp_rw_last_addr 4
-
-/* Register rw_op, scope marb_bp, type rw */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_rw_op;
-#define REG_RD_ADDR_marb_bp_rw_op 8
-#define REG_WR_ADDR_marb_bp_rw_op 8
-
-/* Register rw_clients, scope marb_bp, type rw */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_rw_clients;
-#define REG_RD_ADDR_marb_bp_rw_clients 12
-#define REG_WR_ADDR_marb_bp_rw_clients 12
-
-/* Register rw_options, scope marb_bp, type rw */
-typedef struct {
- unsigned int wrap : 1;
- unsigned int dummy1 : 31;
-} reg_marb_bp_rw_options;
-#define REG_RD_ADDR_marb_bp_rw_options 16
-#define REG_WR_ADDR_marb_bp_rw_options 16
-
-/* Register r_brk_addr, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_addr;
-#define REG_RD_ADDR_marb_bp_r_brk_addr 20
-
-/* Register r_brk_op, scope marb_bp, type r */
-typedef struct {
- unsigned int rd : 1;
- unsigned int wr : 1;
- unsigned int rd_excl : 1;
- unsigned int pri_wr : 1;
- unsigned int us_rd : 1;
- unsigned int us_wr : 1;
- unsigned int us_rd_excl : 1;
- unsigned int us_pri_wr : 1;
- unsigned int dummy1 : 24;
-} reg_marb_bp_r_brk_op;
-#define REG_RD_ADDR_marb_bp_r_brk_op 24
-
-/* Register r_brk_clients, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_clients;
-#define REG_RD_ADDR_marb_bp_r_brk_clients 28
-
-/* Register r_brk_first_client, scope marb_bp, type r */
-typedef struct {
- unsigned int dma0 : 1;
- unsigned int dma1 : 1;
- unsigned int dma2 : 1;
- unsigned int dma3 : 1;
- unsigned int dma4 : 1;
- unsigned int dma5 : 1;
- unsigned int dma6 : 1;
- unsigned int dma7 : 1;
- unsigned int dma8 : 1;
- unsigned int dma9 : 1;
- unsigned int cpui : 1;
- unsigned int cpud : 1;
- unsigned int iop : 1;
- unsigned int slave : 1;
- unsigned int dummy1 : 18;
-} reg_marb_bp_r_brk_first_client;
-#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
-
-/* Register r_brk_size, scope marb_bp, type r */
-typedef unsigned int reg_marb_bp_r_brk_size;
-#define REG_RD_ADDR_marb_bp_r_brk_size 36
-
-/* Register rw_ack, scope marb_bp, type rw */
-typedef unsigned int reg_marb_bp_rw_ack;
-#define REG_RD_ADDR_marb_bp_rw_ack 40
-#define REG_WR_ADDR_marb_bp_rw_ack 40
-
-
-/* Constants */
-enum {
- regk_marb_bp_no = 0x00000000,
- regk_marb_bp_rw_op_default = 0x00000000,
- regk_marb_bp_rw_options_default = 0x00000000,
- regk_marb_bp_yes = 0x00000001
-};
-#endif /* __marb_bp_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h
deleted file mode 100644
index 0a316dc36a6b..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __pinmux_defs_h
-#define __pinmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
- * last modfied: Mon Apr 11 16:09:11 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
- * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope pinmux */
-
-/* Register rw_pa, scope pinmux, type rw */
-typedef struct {
- unsigned int pa0 : 1;
- unsigned int pa1 : 1;
- unsigned int pa2 : 1;
- unsigned int pa3 : 1;
- unsigned int pa4 : 1;
- unsigned int pa5 : 1;
- unsigned int pa6 : 1;
- unsigned int pa7 : 1;
- unsigned int csp2_n : 1;
- unsigned int csp3_n : 1;
- unsigned int csp5_n : 1;
- unsigned int csp6_n : 1;
- unsigned int hsh4 : 1;
- unsigned int hsh5 : 1;
- unsigned int hsh6 : 1;
- unsigned int hsh7 : 1;
- unsigned int dummy1 : 16;
-} reg_pinmux_rw_pa;
-#define REG_RD_ADDR_pinmux_rw_pa 0
-#define REG_WR_ADDR_pinmux_rw_pa 0
-
-/* Register rw_hwprot, scope pinmux, type rw */
-typedef struct {
- unsigned int ser1 : 1;
- unsigned int ser2 : 1;
- unsigned int ser3 : 1;
- unsigned int sser0 : 1;
- unsigned int sser1 : 1;
- unsigned int ata0 : 1;
- unsigned int ata1 : 1;
- unsigned int ata2 : 1;
- unsigned int ata3 : 1;
- unsigned int ata : 1;
- unsigned int eth1 : 1;
- unsigned int eth1_mgm : 1;
- unsigned int timer : 1;
- unsigned int p21 : 1;
- unsigned int dummy1 : 18;
-} reg_pinmux_rw_hwprot;
-#define REG_RD_ADDR_pinmux_rw_hwprot 4
-#define REG_WR_ADDR_pinmux_rw_hwprot 4
-
-/* Register rw_pb_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int pb8 : 1;
- unsigned int pb9 : 1;
- unsigned int pb10 : 1;
- unsigned int pb11 : 1;
- unsigned int pb12 : 1;
- unsigned int pb13 : 1;
- unsigned int pb14 : 1;
- unsigned int pb15 : 1;
- unsigned int pb16 : 1;
- unsigned int pb17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_gio;
-#define REG_RD_ADDR_pinmux_rw_pb_gio 8
-#define REG_WR_ADDR_pinmux_rw_pb_gio 8
-
-/* Register rw_pb_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pb0 : 1;
- unsigned int pb1 : 1;
- unsigned int pb2 : 1;
- unsigned int pb3 : 1;
- unsigned int pb4 : 1;
- unsigned int pb5 : 1;
- unsigned int pb6 : 1;
- unsigned int pb7 : 1;
- unsigned int pb8 : 1;
- unsigned int pb9 : 1;
- unsigned int pb10 : 1;
- unsigned int pb11 : 1;
- unsigned int pb12 : 1;
- unsigned int pb13 : 1;
- unsigned int pb14 : 1;
- unsigned int pb15 : 1;
- unsigned int pb16 : 1;
- unsigned int pb17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pb_iop;
-#define REG_RD_ADDR_pinmux_rw_pb_iop 12
-#define REG_WR_ADDR_pinmux_rw_pb_iop 12
-
-/* Register rw_pc_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pc0 : 1;
- unsigned int pc1 : 1;
- unsigned int pc2 : 1;
- unsigned int pc3 : 1;
- unsigned int pc4 : 1;
- unsigned int pc5 : 1;
- unsigned int pc6 : 1;
- unsigned int pc7 : 1;
- unsigned int pc8 : 1;
- unsigned int pc9 : 1;
- unsigned int pc10 : 1;
- unsigned int pc11 : 1;
- unsigned int pc12 : 1;
- unsigned int pc13 : 1;
- unsigned int pc14 : 1;
- unsigned int pc15 : 1;
- unsigned int pc16 : 1;
- unsigned int pc17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_gio;
-#define REG_RD_ADDR_pinmux_rw_pc_gio 16
-#define REG_WR_ADDR_pinmux_rw_pc_gio 16
-
-/* Register rw_pc_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pc0 : 1;
- unsigned int pc1 : 1;
- unsigned int pc2 : 1;
- unsigned int pc3 : 1;
- unsigned int pc4 : 1;
- unsigned int pc5 : 1;
- unsigned int pc6 : 1;
- unsigned int pc7 : 1;
- unsigned int pc8 : 1;
- unsigned int pc9 : 1;
- unsigned int pc10 : 1;
- unsigned int pc11 : 1;
- unsigned int pc12 : 1;
- unsigned int pc13 : 1;
- unsigned int pc14 : 1;
- unsigned int pc15 : 1;
- unsigned int pc16 : 1;
- unsigned int pc17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pc_iop;
-#define REG_RD_ADDR_pinmux_rw_pc_iop 20
-#define REG_WR_ADDR_pinmux_rw_pc_iop 20
-
-/* Register rw_pd_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pd0 : 1;
- unsigned int pd1 : 1;
- unsigned int pd2 : 1;
- unsigned int pd3 : 1;
- unsigned int pd4 : 1;
- unsigned int pd5 : 1;
- unsigned int pd6 : 1;
- unsigned int pd7 : 1;
- unsigned int pd8 : 1;
- unsigned int pd9 : 1;
- unsigned int pd10 : 1;
- unsigned int pd11 : 1;
- unsigned int pd12 : 1;
- unsigned int pd13 : 1;
- unsigned int pd14 : 1;
- unsigned int pd15 : 1;
- unsigned int pd16 : 1;
- unsigned int pd17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_gio;
-#define REG_RD_ADDR_pinmux_rw_pd_gio 24
-#define REG_WR_ADDR_pinmux_rw_pd_gio 24
-
-/* Register rw_pd_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pd0 : 1;
- unsigned int pd1 : 1;
- unsigned int pd2 : 1;
- unsigned int pd3 : 1;
- unsigned int pd4 : 1;
- unsigned int pd5 : 1;
- unsigned int pd6 : 1;
- unsigned int pd7 : 1;
- unsigned int pd8 : 1;
- unsigned int pd9 : 1;
- unsigned int pd10 : 1;
- unsigned int pd11 : 1;
- unsigned int pd12 : 1;
- unsigned int pd13 : 1;
- unsigned int pd14 : 1;
- unsigned int pd15 : 1;
- unsigned int pd16 : 1;
- unsigned int pd17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pd_iop;
-#define REG_RD_ADDR_pinmux_rw_pd_iop 28
-#define REG_WR_ADDR_pinmux_rw_pd_iop 28
-
-/* Register rw_pe_gio, scope pinmux, type rw */
-typedef struct {
- unsigned int pe0 : 1;
- unsigned int pe1 : 1;
- unsigned int pe2 : 1;
- unsigned int pe3 : 1;
- unsigned int pe4 : 1;
- unsigned int pe5 : 1;
- unsigned int pe6 : 1;
- unsigned int pe7 : 1;
- unsigned int pe8 : 1;
- unsigned int pe9 : 1;
- unsigned int pe10 : 1;
- unsigned int pe11 : 1;
- unsigned int pe12 : 1;
- unsigned int pe13 : 1;
- unsigned int pe14 : 1;
- unsigned int pe15 : 1;
- unsigned int pe16 : 1;
- unsigned int pe17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_gio;
-#define REG_RD_ADDR_pinmux_rw_pe_gio 32
-#define REG_WR_ADDR_pinmux_rw_pe_gio 32
-
-/* Register rw_pe_iop, scope pinmux, type rw */
-typedef struct {
- unsigned int pe0 : 1;
- unsigned int pe1 : 1;
- unsigned int pe2 : 1;
- unsigned int pe3 : 1;
- unsigned int pe4 : 1;
- unsigned int pe5 : 1;
- unsigned int pe6 : 1;
- unsigned int pe7 : 1;
- unsigned int pe8 : 1;
- unsigned int pe9 : 1;
- unsigned int pe10 : 1;
- unsigned int pe11 : 1;
- unsigned int pe12 : 1;
- unsigned int pe13 : 1;
- unsigned int pe14 : 1;
- unsigned int pe15 : 1;
- unsigned int pe16 : 1;
- unsigned int pe17 : 1;
- unsigned int dummy1 : 14;
-} reg_pinmux_rw_pe_iop;
-#define REG_RD_ADDR_pinmux_rw_pe_iop 36
-#define REG_WR_ADDR_pinmux_rw_pe_iop 36
-
-/* Register rw_usb_phy, scope pinmux, type rw */
-typedef struct {
- unsigned int en_usb0 : 1;
- unsigned int en_usb1 : 1;
- unsigned int dummy1 : 30;
-} reg_pinmux_rw_usb_phy;
-#define REG_RD_ADDR_pinmux_rw_usb_phy 40
-#define REG_WR_ADDR_pinmux_rw_usb_phy 40
-
-
-/* Constants */
-enum {
- regk_pinmux_no = 0x00000000,
- regk_pinmux_rw_hwprot_default = 0x00000000,
- regk_pinmux_rw_pa_default = 0x00000000,
- regk_pinmux_rw_pb_gio_default = 0x00000000,
- regk_pinmux_rw_pb_iop_default = 0x00000000,
- regk_pinmux_rw_pc_gio_default = 0x00000000,
- regk_pinmux_rw_pc_iop_default = 0x00000000,
- regk_pinmux_rw_pd_gio_default = 0x00000000,
- regk_pinmux_rw_pd_iop_default = 0x00000000,
- regk_pinmux_rw_pe_gio_default = 0x00000000,
- regk_pinmux_rw_pe_iop_default = 0x00000000,
- regk_pinmux_rw_usb_phy_default = 0x00000000,
- regk_pinmux_yes = 0x00000001
-};
-#endif /* __pinmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h
deleted file mode 100644
index 1bfca2666158..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __reg_map_h
-#define __reg_map_h
-
-/*
- * This file is autogenerated from
- * file: ../../mod/fakereg.rmap
- * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
- * last modified: Wed Feb 11 20:53:25 2004
- * file: ../../rtl/global.rmap
- * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
- * last modified: Mon Aug 18 17:08:23 2003
- * file: ../../mod/modreg.rmap
- * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
- * last modified: Fri Feb 20 16:40:04 2004
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-typedef enum {
- regi_ata = 0xb0032000,
- regi_bif_core = 0xb0014000,
- regi_bif_dma = 0xb0016000,
- regi_bif_slave = 0xb0018000,
- regi_config = 0xb003c000,
- regi_dma0 = 0xb0000000,
- regi_dma1 = 0xb0002000,
- regi_dma2 = 0xb0004000,
- regi_dma3 = 0xb0006000,
- regi_dma4 = 0xb0008000,
- regi_dma5 = 0xb000a000,
- regi_dma6 = 0xb000c000,
- regi_dma7 = 0xb000e000,
- regi_dma8 = 0xb0010000,
- regi_dma9 = 0xb0012000,
- regi_eth0 = 0xb0034000,
- regi_eth1 = 0xb0036000,
- regi_gio = 0xb001a000,
- regi_iop = 0xb0020000,
- regi_iop_version = 0xb0020000,
- regi_iop_fifo_in0_extra = 0xb0020040,
- regi_iop_fifo_in1_extra = 0xb0020080,
- regi_iop_fifo_out0_extra = 0xb00200c0,
- regi_iop_fifo_out1_extra = 0xb0020100,
- regi_iop_trigger_grp0 = 0xb0020140,
- regi_iop_trigger_grp1 = 0xb0020180,
- regi_iop_trigger_grp2 = 0xb00201c0,
- regi_iop_trigger_grp3 = 0xb0020200,
- regi_iop_trigger_grp4 = 0xb0020240,
- regi_iop_trigger_grp5 = 0xb0020280,
- regi_iop_trigger_grp6 = 0xb00202c0,
- regi_iop_trigger_grp7 = 0xb0020300,
- regi_iop_crc_par0 = 0xb0020380,
- regi_iop_crc_par1 = 0xb0020400,
- regi_iop_dmc_in0 = 0xb0020480,
- regi_iop_dmc_in1 = 0xb0020500,
- regi_iop_dmc_out0 = 0xb0020580,
- regi_iop_dmc_out1 = 0xb0020600,
- regi_iop_fifo_in0 = 0xb0020680,
- regi_iop_fifo_in1 = 0xb0020700,
- regi_iop_fifo_out0 = 0xb0020780,
- regi_iop_fifo_out1 = 0xb0020800,
- regi_iop_scrc_in0 = 0xb0020880,
- regi_iop_scrc_in1 = 0xb0020900,
- regi_iop_scrc_out0 = 0xb0020980,
- regi_iop_scrc_out1 = 0xb0020a00,
- regi_iop_timer_grp0 = 0xb0020a80,
- regi_iop_timer_grp1 = 0xb0020b00,
- regi_iop_timer_grp2 = 0xb0020b80,
- regi_iop_timer_grp3 = 0xb0020c00,
- regi_iop_sap_in = 0xb0020d00,
- regi_iop_sap_out = 0xb0020e00,
- regi_iop_spu0 = 0xb0020f00,
- regi_iop_spu1 = 0xb0021000,
- regi_iop_sw_cfg = 0xb0021100,
- regi_iop_sw_cpu = 0xb0021200,
- regi_iop_sw_mpu = 0xb0021300,
- regi_iop_sw_spu0 = 0xb0021400,
- regi_iop_sw_spu1 = 0xb0021500,
- regi_iop_mpu = 0xb0021600,
- regi_irq = 0xb001c000,
- regi_irq2 = 0xb005c000,
- regi_marb = 0xb003e000,
- regi_marb_bp0 = 0xb003e240,
- regi_marb_bp1 = 0xb003e280,
- regi_marb_bp2 = 0xb003e2c0,
- regi_marb_bp3 = 0xb003e300,
- regi_pinmux = 0xb0038000,
- regi_ser0 = 0xb0026000,
- regi_ser1 = 0xb0028000,
- regi_ser2 = 0xb002a000,
- regi_ser3 = 0xb002c000,
- regi_sser0 = 0xb0022000,
- regi_sser1 = 0xb0024000,
- regi_strcop = 0xb0030000,
- regi_strmux = 0xb003a000,
- regi_timer = 0xb001e000,
- regi_timer0 = 0xb001e000,
- regi_timer2 = 0xb005e000,
- regi_trace = 0xb0040000,
-} reg_scope_instances;
-#endif /* __reg_map_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h
deleted file mode 100644
index 0ab49edb1c81..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __strmux_defs_h
-#define __strmux_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
- * last modfied: Mon Apr 11 16:09:43 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
- * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope strmux */
-
-/* Register rw_cfg, scope strmux, type rw */
-typedef struct {
- unsigned int dma0 : 3;
- unsigned int dma1 : 3;
- unsigned int dma2 : 3;
- unsigned int dma3 : 3;
- unsigned int dma4 : 3;
- unsigned int dma5 : 3;
- unsigned int dma6 : 3;
- unsigned int dma7 : 3;
- unsigned int dma8 : 3;
- unsigned int dma9 : 3;
- unsigned int dummy1 : 2;
-} reg_strmux_rw_cfg;
-#define REG_RD_ADDR_strmux_rw_cfg 0
-#define REG_WR_ADDR_strmux_rw_cfg 0
-
-
-/* Constants */
-enum {
- regk_strmux_ata = 0x00000003,
- regk_strmux_eth0 = 0x00000001,
- regk_strmux_eth1 = 0x00000004,
- regk_strmux_ext0 = 0x00000001,
- regk_strmux_ext1 = 0x00000001,
- regk_strmux_ext2 = 0x00000001,
- regk_strmux_ext3 = 0x00000001,
- regk_strmux_iop0 = 0x00000002,
- regk_strmux_iop1 = 0x00000001,
- regk_strmux_off = 0x00000000,
- regk_strmux_p21 = 0x00000004,
- regk_strmux_rw_cfg_default = 0x00000000,
- regk_strmux_ser0 = 0x00000002,
- regk_strmux_ser1 = 0x00000002,
- regk_strmux_ser2 = 0x00000004,
- regk_strmux_ser3 = 0x00000003,
- regk_strmux_sser0 = 0x00000003,
- regk_strmux_sser1 = 0x00000003,
- regk_strmux_strcop = 0x00000002
-};
-#endif /* __strmux_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h
deleted file mode 100644
index 59c70ba9959b..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __timer_defs_h
-#define __timer_defs_h
-
-/*
- * This file is autogenerated from
- * file: ../../inst/timer/rtl/timer_regs.r
- * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
- * last modfied: Mon Apr 11 16:09:53 2005
- *
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
- * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-/* Main access macros */
-#ifndef REG_RD
-#define REG_RD( scope, inst, reg ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR
-#define REG_WR( scope, inst, reg, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_VECT
-#define REG_RD_VECT( scope, inst, reg, index ) \
- REG_READ( reg_##scope##_##reg, \
- (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_VECT
-#define REG_WR_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( reg_##scope##_##reg, \
- (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT
-#define REG_RD_INT( scope, inst, reg ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT
-#define REG_WR_INT( scope, inst, reg, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_RD_INT_VECT
-#define REG_RD_INT_VECT( scope, inst, reg, index ) \
- REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-#ifndef REG_WR_INT_VECT
-#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
- REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg, (val) )
-#endif
-
-#ifndef REG_TYPE_CONV
-#define REG_TYPE_CONV( type, orgtype, val ) \
- ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
-#endif
-
-#ifndef reg_page_size
-#define reg_page_size 8192
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg )
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
- ( (inst) + REG_RD_ADDR_##scope##_##reg + \
- (index) * STRIDE_##scope##_##reg )
-#endif
-
-/* C-code for register scope timer */
-
-/* Register rw_tmr0_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr0_div;
-#define REG_RD_ADDR_timer_rw_tmr0_div 0
-#define REG_WR_ADDR_timer_rw_tmr0_div 0
-
-/* Register r_tmr0_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr0_data;
-#define REG_RD_ADDR_timer_r_tmr0_data 4
-
-/* Register rw_tmr0_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr0_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
-#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
-
-/* Register rw_tmr1_div, scope timer, type rw */
-typedef unsigned int reg_timer_rw_tmr1_div;
-#define REG_RD_ADDR_timer_rw_tmr1_div 16
-#define REG_WR_ADDR_timer_rw_tmr1_div 16
-
-/* Register r_tmr1_data, scope timer, type r */
-typedef unsigned int reg_timer_r_tmr1_data;
-#define REG_RD_ADDR_timer_r_tmr1_data 20
-
-/* Register rw_tmr1_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int op : 2;
- unsigned int freq : 3;
- unsigned int dummy1 : 27;
-} reg_timer_rw_tmr1_ctrl;
-#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
-#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
-
-/* Register rs_cnt_data, scope timer, type rs */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_rs_cnt_data;
-#define REG_RD_ADDR_timer_rs_cnt_data 32
-
-/* Register r_cnt_data, scope timer, type r */
-typedef struct {
- unsigned int tmr : 24;
- unsigned int cnt : 8;
-} reg_timer_r_cnt_data;
-#define REG_RD_ADDR_timer_r_cnt_data 36
-
-/* Register rw_cnt_cfg, scope timer, type rw */
-typedef struct {
- unsigned int clk : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_cnt_cfg;
-#define REG_RD_ADDR_timer_rw_cnt_cfg 40
-#define REG_WR_ADDR_timer_rw_cnt_cfg 40
-
-/* Register rw_trig, scope timer, type rw */
-typedef unsigned int reg_timer_rw_trig;
-#define REG_RD_ADDR_timer_rw_trig 48
-#define REG_WR_ADDR_timer_rw_trig 48
-
-/* Register rw_trig_cfg, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_trig_cfg;
-#define REG_RD_ADDR_timer_rw_trig_cfg 52
-#define REG_WR_ADDR_timer_rw_trig_cfg 52
-
-/* Register r_time, scope timer, type r */
-typedef unsigned int reg_timer_r_time;
-#define REG_RD_ADDR_timer_r_time 56
-
-/* Register rw_out, scope timer, type rw */
-typedef struct {
- unsigned int tmr : 2;
- unsigned int dummy1 : 30;
-} reg_timer_rw_out;
-#define REG_RD_ADDR_timer_rw_out 60
-#define REG_WR_ADDR_timer_rw_out 60
-
-/* Register rw_wd_ctrl, scope timer, type rw */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int key : 7;
- unsigned int dummy1 : 16;
-} reg_timer_rw_wd_ctrl;
-#define REG_RD_ADDR_timer_rw_wd_ctrl 64
-#define REG_WR_ADDR_timer_rw_wd_ctrl 64
-
-/* Register r_wd_stat, scope timer, type r */
-typedef struct {
- unsigned int cnt : 8;
- unsigned int cmd : 1;
- unsigned int dummy1 : 23;
-} reg_timer_r_wd_stat;
-#define REG_RD_ADDR_timer_r_wd_stat 68
-
-/* Register rw_intr_mask, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_intr_mask;
-#define REG_RD_ADDR_timer_rw_intr_mask 72
-#define REG_WR_ADDR_timer_rw_intr_mask 72
-
-/* Register rw_ack_intr, scope timer, type rw */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_rw_ack_intr;
-#define REG_RD_ADDR_timer_rw_ack_intr 76
-#define REG_WR_ADDR_timer_rw_ack_intr 76
-
-/* Register r_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_intr;
-#define REG_RD_ADDR_timer_r_intr 80
-
-/* Register r_masked_intr, scope timer, type r */
-typedef struct {
- unsigned int tmr0 : 1;
- unsigned int tmr1 : 1;
- unsigned int cnt : 1;
- unsigned int trig : 1;
- unsigned int dummy1 : 28;
-} reg_timer_r_masked_intr;
-#define REG_RD_ADDR_timer_r_masked_intr 84
-
-/* Register rw_test, scope timer, type rw */
-typedef struct {
- unsigned int dis : 1;
- unsigned int en : 1;
- unsigned int dummy1 : 30;
-} reg_timer_rw_test;
-#define REG_RD_ADDR_timer_rw_test 88
-#define REG_WR_ADDR_timer_rw_test 88
-
-
-/* Constants */
-enum {
- regk_timer_ext = 0x00000001,
- regk_timer_f100 = 0x00000007,
- regk_timer_f29_493 = 0x00000004,
- regk_timer_f32 = 0x00000005,
- regk_timer_f32_768 = 0x00000006,
- regk_timer_hold = 0x00000001,
- regk_timer_ld = 0x00000000,
- regk_timer_no = 0x00000000,
- regk_timer_off = 0x00000000,
- regk_timer_run = 0x00000002,
- regk_timer_rw_cnt_cfg_default = 0x00000000,
- regk_timer_rw_intr_mask_default = 0x00000000,
- regk_timer_rw_out_default = 0x00000000,
- regk_timer_rw_test_default = 0x00000000,
- regk_timer_rw_tmr0_ctrl_default = 0x00000000,
- regk_timer_rw_tmr1_ctrl_default = 0x00000000,
- regk_timer_rw_trig_cfg_default = 0x00000000,
- regk_timer_start = 0x00000001,
- regk_timer_stop = 0x00000000,
- regk_timer_time = 0x00000001,
- regk_timer_tmr0 = 0x00000002,
- regk_timer_tmr1 = 0x00000003,
- regk_timer_yes = 0x00000001
-};
-#endif /* __timer_defs_h */
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
deleted file mode 100644
index 94328936cc91..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_ARCH_MEMMAP_H
-#define _ASM_ARCH_MEMMAP_H
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_INTMEM_START (0x38000000)
-#define MEM_INTMEM_SIZE (0x00020000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h b/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h
deleted file mode 100644
index 1d87f1392dc8..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_ARCH_PINMUX_H
-#define _ASM_CRIS_ARCH_PINMUX_H
-
-#define PORT_B 0
-#define PORT_C 1
-#define PORT_D 2
-#define PORT_E 3
-
-enum pin_mode {
- pinmux_none = 0,
- pinmux_fixed,
- pinmux_gpio,
- pinmux_iop
-};
-
-enum fixed_function {
- pinmux_ser1,
- pinmux_ser2,
- pinmux_ser3,
- pinmux_sser0,
- pinmux_sser1,
- pinmux_ata0,
- pinmux_ata1,
- pinmux_ata2,
- pinmux_ata3,
- pinmux_ata,
- pinmux_eth1,
- pinmux_timer
-};
-
-int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
-int crisv32_pinmux_alloc_fixed(enum fixed_function function);
-int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
-int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
-
-#endif
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
deleted file mode 100644
index 96c3b0fb62c1..000000000000
--- a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef STARTUP_INC_INCLUDED
-#define STARTUP_INC_INCLUDED
-
-#include <hwregs/asm/reg_map_asm.h>
-#include <hwregs/asm/bif_core_defs_asm.h>
-#include <hwregs/asm/gio_defs_asm.h>
-#include <hwregs/asm/config_defs_asm.h>
-
- .macro GIO_INIT
- move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1
- move.d $r0, [$r1]
- .endm
-
- .macro START_CLOCKS
- move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
- move.d [$r1], $r0
- or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
- REG_STATE(config, rw_clk_ctrl, bif, yes) | \
- REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
- move.d $r0, [$r1]
- .endm
-
- .macro SETUP_WAIT_STATES
- ;; Set up waitstates etc
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
- move.d $r1, [$r0]
- .endm
-
-#endif
diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild
deleted file mode 100644
index 6a547fe8752b..000000000000
--- a/arch/cris/include/asm/Kbuild
+++ /dev/null
@@ -1,31 +0,0 @@
-generic-y += atomic.h
-generic-y += barrier.h
-generic-y += cmpxchg.h
-generic-y += current.h
-generic-y += device.h
-generic-y += div64.h
-generic-y += dma-mapping.h
-generic-y += emergency-restart.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += futex.h
-generic-y += hardirq.h
-generic-y += irq_regs.h
-generic-y += irq_work.h
-generic-y += kdebug.h
-generic-y += kmap_types.h
-generic-y += kprobes.h
-generic-y += linkage.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += module.h
-generic-y += percpu.h
-generic-y += preempt.h
-generic-y += sections.h
-generic-y += topology.h
-generic-y += trace_clock.h
-generic-y += vga.h
-generic-y += word-at-a-time.h
-generic-y += xor.h
diff --git a/arch/cris/include/asm/asm-offsets.h b/arch/cris/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/cris/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/cris/include/asm/axisflashmap.h b/arch/cris/include/asm/axisflashmap.h
deleted file mode 100644
index 185596c2caab..000000000000
--- a/arch/cris/include/asm/axisflashmap.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_AXISFLASHMAP_H
-#define __ASM_AXISFLASHMAP_H
-
-/* Bootblock parameters are stored at 0xc000 and has the FLASH_BOOT_MAGIC
- * as start, it ends with 0xFFFFFFFF */
-#define FLASH_BOOT_MAGIC 0xbeefcace
-#define BOOTPARAM_OFFSET 0xc000
-/* apps/bootblocktool is used to read and write the parameters,
- * and it has nothing to do with the partition table.
- */
-
-#define PARTITION_TABLE_OFFSET 10
-#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */
-
-/* The partitiontable_head is located at offset +10: */
-struct partitiontable_head {
- __u16 magic; /* PARTITION_TABLE_MAGIC */
- __u16 size; /* Length of ptable block (entries + end marker) */
- __u32 checksum; /* simple longword sum, over entries + end marker */
-};
-
-/* And followed by partition table entries */
-struct partitiontable_entry {
- __u32 offset; /* relative to the sector the ptable is in */
- __u32 size; /* in bytes */
- __u32 checksum; /* simple longword sum */
- __u16 type; /* see type codes below */
- __u16 flags; /* bit 0: ro/rw = 1/0 */
- __u32 future0; /* 16 bytes reserved for future use */
- __u32 future1;
- __u32 future2;
- __u32 future3;
-};
-/* ended by an end marker: */
-#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF
-#define PARTITIONTABLE_END_MARKER_SIZE 4
-
-#define PARTITIONTABLE_END_PAD 10
-
-/* Complete structure for whole partition table */
-/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting
- * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER.
- */
-struct partitiontable {
- __u8 skip[PARTITION_TABLE_OFFSET];
- struct partitiontable_head head;
- struct partitiontable_entry entries[];
-};
-
-#define PARTITION_TYPE_PARAM 0x0001
-#define PARTITION_TYPE_KERNEL 0x0002
-#define PARTITION_TYPE_JFFS 0x0003
-#define PARTITION_TYPE_JFFS2 0x0000
-
-#define PARTITION_FLAGS_READONLY_MASK 0x0001
-#define PARTITION_FLAGS_READONLY 0x0001
-
-/* The master mtd for the entire flash. */
-extern struct mtd_info *axisflash_mtd;
-
-#endif
diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h
deleted file mode 100644
index 78f975ad42d9..000000000000
--- a/arch/cris/include/asm/bitops.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* asm/bitops.h for Linux/CRIS
- *
- * TODO: asm versions if speed is needed
- *
- * All bit operations return 0 if the bit was cleared before the
- * operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-
-#ifndef _CRIS_BITOPS_H
-#define _CRIS_BITOPS_H
-
-/* Currently this is unsuitable for consumption outside the kernel. */
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <arch/bitops.h>
-#include <linux/compiler.h>
-#include <asm/barrier.h>
-
-#include <asm-generic/bitops/atomic.h>
-#include <asm-generic/bitops/non-atomic.h>
-
-/*
- * Since we define it "external", it collides with the built-in
- * definition, which doesn't have the same semantics. We don't want to
- * use -fno-builtin, so just hide the name ffs.
- */
-#define ffs(x) kernel_ffs(x)
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/le.h>
-
-#include <asm-generic/bitops/ext2-atomic-setbit.h>
-
-#include <asm-generic/bitops/sched.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _CRIS_BITOPS_H */
diff --git a/arch/cris/include/asm/bug.h b/arch/cris/include/asm/bug.h
deleted file mode 100644
index f1fa72a426c2..000000000000
--- a/arch/cris/include/asm/bug.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_BUG_H
-#define _CRIS_BUG_H
-#include <arch/bug.h>
-#endif
diff --git a/arch/cris/include/asm/bugs.h b/arch/cris/include/asm/bugs.h
deleted file mode 100644
index c5907aac1007..000000000000
--- a/arch/cris/include/asm/bugs.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* $Id: bugs.h,v 1.2 2001/01/17 17:03:18 bjornw Exp $
- *
- * include/asm-cris/bugs.h
- *
- * Copyright (C) 2001 Axis Communications AB
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- * void check_bugs(void);
- */
-
-static void check_bugs(void)
-{
-}
-
-
-
-
diff --git a/arch/cris/include/asm/cache.h b/arch/cris/include/asm/cache.h
deleted file mode 100644
index 8dac0922721c..000000000000
--- a/arch/cris/include/asm/cache.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-#include <arch/cache.h>
-
-#endif /* _ASM_CACHE_H */
diff --git a/arch/cris/include/asm/cacheflush.h b/arch/cris/include/asm/cacheflush.h
deleted file mode 100644
index 0da1c76a2bbc..000000000000
--- a/arch/cris/include/asm/cacheflush.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_CACHEFLUSH_H
-#define _CRIS_CACHEFLUSH_H
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-
-/* The cache doesn't need to be flushed when TLB entries change because
- * the cache is mapped to physical memory, not virtual memory
- */
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_icache_range(start, end) do { } while (0)
-#define flush_icache_page(vma,pg) do { } while (0)
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-
-int change_page_attr(struct page *page, int numpages, pgprot_t prot);
-
-#endif /* _CRIS_CACHEFLUSH_H */
diff --git a/arch/cris/include/asm/checksum.h b/arch/cris/include/asm/checksum.h
deleted file mode 100644
index 61b6a4f6a002..000000000000
--- a/arch/cris/include/asm/checksum.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* TODO: csum_tcpudp_magic could be speeded up, and csum_fold as well */
-
-#ifndef _CRIS_CHECKSUM_H
-#define _CRIS_CHECKSUM_H
-
-#include <arch/checksum.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum);
-
-/*
- * Fold a partial checksum into a word
- */
-
-static inline __sum16 csum_fold(__wsum csum)
-{
- u32 sum = (__force u32)csum;
- sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */
- sum = (sum & 0xffff) + (sum >> 16); /* add in end-around carry */
- return (__force __sum16)~sum;
-}
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum,
- int *errptr);
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- *
- */
-
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- return csum_fold(csum_partial(iph, ihl * 4, 0));
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
- return csum_fold (csum_partial(buff, len, 0));
-}
-
-#endif
diff --git a/arch/cris/include/asm/delay.h b/arch/cris/include/asm/delay.h
deleted file mode 100644
index 2dfdb13e1a9e..000000000000
--- a/arch/cris/include/asm/delay.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_DELAY_H
-#define _CRIS_DELAY_H
-
-/*
- * Copyright (C) 1998-2002 Axis Communications AB
- *
- * Delay routines, using a pre-computed "loops_per_second" value.
- */
-
-#include <arch/delay.h>
-
-/* Use only for very small delays ( < 1 msec). */
-
-extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */
-
-/* May be defined by arch/delay.h. */
-#ifndef udelay
-static inline void udelay(unsigned long usecs)
-{
- __delay(usecs * loops_per_usec);
-}
-#endif
-
-#endif /* defined(_CRIS_DELAY_H) */
-
-
-
diff --git a/arch/cris/include/asm/dma.h b/arch/cris/include/asm/dma.h
deleted file mode 100644
index e1f7d6d9bfc2..000000000000
--- a/arch/cris/include/asm/dma.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* $Id: dma.h,v 1.2 2001/05/09 12:17:42 johana Exp $ */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <arch/dma.h>
-
-/* it's useless on the Etrax, but unfortunately needed by the new
- bootmem allocator (but this should do it for this) */
-
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/arch/cris/include/asm/eshlibld.h b/arch/cris/include/asm/eshlibld.h
deleted file mode 100644
index 88940556c2db..000000000000
--- a/arch/cris/include/asm/eshlibld.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*!**************************************************************************
-*!
-*! FILE NAME : eshlibld.h
-*!
-*! DESCRIPTION: Prototypes for exported shared library functions
-*!
-*! FUNCTIONS : perform_cris_aout_relocations, shlibmod_fork, shlibmod_exit
-*! (EXPORTED)
-*!
-*!---------------------------------------------------------------------------
-*!
-*! (C) Copyright 1998, 1999 Axis Communications AB, LUND, SWEDEN
-*!
-*!**************************************************************************/
-/* $Id: eshlibld.h,v 1.2 2001/02/23 13:47:33 bjornw Exp $ */
-
-#ifndef _cris_relocate_h
-#define _cris_relocate_h
-
-/* Please note that this file is also compiled into the xsim simulator.
- Try to avoid breaking its double use (only works on a little-endian
- 32-bit machine such as the i386 anyway).
-
- Use __KERNEL__ when you're about to use kernel functions,
- (which you should not do here anyway, since this file is
- used by glibc).
- Use defined(__KERNEL__) || defined(__elinux__) when doing
- things that only makes sense on an elinux system.
- Use __CRIS__ when you're about to do (really) CRIS-specific code.
-*/
-
-/* We have dependencies all over the place for the host system
- for xsim being a linux system, so let's not pretend anything
- else with #ifdef:s here until fixed. */
-#include <linux/limits.h>
-
-/* Maybe do sanity checking if file input. */
-#undef SANITYCHECK_RELOC
-
-/* Maybe output debug messages. */
-#undef RELOC_DEBUG
-
-/* Maybe we want to share core as well as disk space.
- Mainly depends on the config macro CONFIG_SHARE_SHLIB_CORE, but it is
- assumed that we want to share code when debugging (exposes more
- trouble). */
-#ifndef SHARE_LIB_CORE
-# if (defined(__KERNEL__) || !defined(RELOC_DEBUG))
-# define SHARE_LIB_CORE 0
-# else
-# define SHARE_LIB_CORE 1
-# endif /* __KERNEL__ etc */
-#endif /* SHARE_LIB_CORE */
-
-
-/* Main exported function; supposed to be called when the program a.out
- has been read in. */
-extern int
-perform_cris_aout_relocations(unsigned long text, unsigned long tlength,
- unsigned long data, unsigned long dlength,
- unsigned long baddr, unsigned long blength,
-
- /* These may be zero when there's "perfect"
- position-independent code. */
- unsigned char *trel, unsigned long tsrel,
- unsigned long dsrel,
-
- /* These will be zero at a first try, to see
- if code is statically linked. Else a
- second try, with the symbol table and
- string table nonzero should be done. */
- unsigned char *symbols, unsigned long symlength,
- unsigned char *strings, unsigned long stringlength,
-
- /* These will only be used when symbol table
- information is present. */
- char **env, int envc,
- int euid, int is_suid);
-
-
-#ifdef RELOC_DEBUG
-/* Task-specific debug stuff. */
-struct task_reloc_debug {
- struct memdebug *alloclast;
- unsigned long alloc_total;
- unsigned long export_total;
-};
-#endif /* RELOC_DEBUG */
-
-#if SHARE_LIB_CORE
-
-/* When code (and some very specific data) is shared and not just
- dynamically linked, we need to export hooks for exec beginning and
- end. */
-
-struct shlibdep;
-
-extern void
-shlibmod_exit(struct shlibdep **deps);
-
-/* Returns 0 if failure, nonzero for ok. */
-extern int
-shlibmod_fork(struct shlibdep **deps);
-
-#else /* ! SHARE_LIB_CORE */
-# define shlibmod_exit(x)
-# define shlibmod_fork(x) 1
-#endif /* ! SHARE_LIB_CORE */
-
-#endif _cris_relocate_h
-/********************** END OF FILE eshlibld.h *****************************/
-
diff --git a/arch/cris/include/asm/etraxi2c.h b/arch/cris/include/asm/etraxi2c.h
deleted file mode 100644
index 0fa6f03d93e7..000000000000
--- a/arch/cris/include/asm/etraxi2c.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* $Id: etraxi2c.h,v 1.1 2001/01/18 15:49:57 bjornw Exp $ */
-
-#ifndef _LINUX_ETRAXI2C_H
-#define _LINUX_ETRAXI2C_H
-
-/* etraxi2c _IOC_TYPE, bits 8 to 15 in ioctl cmd */
-
-#define ETRAXI2C_IOCTYPE 44
-
-/* supported ioctl _IOC_NR's */
-
-/* in write operations, the argument contains both i2c
- * slave, register and value.
- */
-
-#define I2C_WRITEARG(slave, reg, value) (((slave) << 16) | ((reg) << 8) | (value))
-#define I2C_READARG(slave, reg) (((slave) << 16) | ((reg) << 8))
-
-#define I2C_ARGSLAVE(arg) ((arg) >> 16)
-#define I2C_ARGREG(arg) (((arg) >> 8) & 0xff)
-#define I2C_ARGVALUE(arg) ((arg) & 0xff)
-
-#define I2C_WRITEREG 0x1 /* write to an i2c register */
-#define I2C_READREG 0x2 /* read from an i2c register */
-
-/*
-EXAMPLE usage:
-
- i2c_arg = I2C_WRITEARG(STA013_WRITE_ADDR, reg, val);
- ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_WRITEREG), i2c_arg);
-
- i2c_arg = I2C_READARG(STA013_READ_ADDR, reg);
- val = ioctl(fd, _IO(ETRAXI2C_IOCTYPE, I2C_READREG), i2c_arg);
-
-*/
-#endif
diff --git a/arch/cris/include/asm/fasttimer.h b/arch/cris/include/asm/fasttimer.h
deleted file mode 100644
index bc109f4a8377..000000000000
--- a/arch/cris/include/asm/fasttimer.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/include/asm-cris/fasttimer.h
- *
- * Fast timers for ETRAX100LX
- * Copyright (C) 2000-2007 Axis Communications AB
- */
-#include <linux/time.h> /* struct timeval */
-#include <linux/timex.h>
-
-#ifdef CONFIG_ETRAX_FAST_TIMER
-
-typedef void fast_timer_function_type(unsigned long);
-
-struct fasttime_t {
- unsigned long tv_jiff; /* jiffies */
- unsigned long tv_usec; /* microseconds */
-};
-
-struct fast_timer{ /* Close to timer_list */
- struct fast_timer *next;
- struct fast_timer *prev;
- struct fasttime_t tv_set;
- struct fasttime_t tv_expires;
- unsigned long delay_us;
- fast_timer_function_type *function;
- unsigned long data;
- const char *name;
-};
-
-extern struct fast_timer *fast_timer_list;
-
-void start_one_shot_timer(struct fast_timer *t,
- fast_timer_function_type *function,
- unsigned long data,
- unsigned long delay_us,
- const char *name);
-
-int del_fast_timer(struct fast_timer * t);
-/* return 1 if deleted */
-
-
-void schedule_usleep(unsigned long us);
-
-
-int fast_timer_init(void);
-
-#endif
diff --git a/arch/cris/include/asm/fb.h b/arch/cris/include/asm/fb.h
deleted file mode 100644
index e10150073c30..000000000000
--- a/arch/cris/include/asm/fb.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/fb.h>
-
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
- return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/arch/cris/include/asm/ftrace.h b/arch/cris/include/asm/ftrace.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/cris/include/asm/ftrace.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/cris/include/asm/hw_irq.h b/arch/cris/include/asm/hw_irq.h
deleted file mode 100644
index 298066020af2..000000000000
--- a/arch/cris/include/asm/hw_irq.h
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
-
-#endif
-
diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h
deleted file mode 100644
index c92712d30f54..000000000000
--- a/arch/cris/include/asm/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_IO_H
-#define _ASM_CRIS_IO_H
-
-#include <asm/page.h> /* for __va, __pa */
-#ifdef CONFIG_ETRAX_ARCH_V10
-#include <arch/io.h>
-#endif
-#include <asm-generic/iomap.h>
-#include <linux/kernel.h>
-
-extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
-
-static inline void __iomem * ioremap (unsigned long offset, unsigned long size)
-{
- return __ioremap(offset, size, 0);
-}
-
-extern void iounmap(volatile void * __iomem addr);
-
-extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
-
-#include <asm-generic/io.h>
-
-#endif
diff --git a/arch/cris/include/asm/irq.h b/arch/cris/include/asm/irq.h
deleted file mode 100644
index 6a932f7db58e..000000000000
--- a/arch/cris/include/asm/irq.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
-
-#include <arch/irq.h>
-
-static inline int irq_canonicalize(int irq)
-{
- return irq;
-}
-
-#endif /* _ASM_IRQ_H */
-
-
diff --git a/arch/cris/include/asm/irqflags.h b/arch/cris/include/asm/irqflags.h
deleted file mode 100644
index 943ba5ca6d2c..000000000000
--- a/arch/cris/include/asm/irqflags.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <arch/irqflags.h>
diff --git a/arch/cris/include/asm/mmu.h b/arch/cris/include/asm/mmu.h
deleted file mode 100644
index 54da8f64b37a..000000000000
--- a/arch/cris/include/asm/mmu.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRIS MMU constants and PTE layout
- */
-
-#ifndef _CRIS_MMU_H
-#define _CRIS_MMU_H
-
-#include <arch/mmu.h>
-
-#endif
diff --git a/arch/cris/include/asm/mmu_context.h b/arch/cris/include/asm/mmu_context.h
deleted file mode 100644
index 178f3b72e9e3..000000000000
--- a/arch/cris/include/asm/mmu_context.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CRIS_MMU_CONTEXT_H
-#define __CRIS_MMU_CONTEXT_H
-
-#include <asm-generic/mm_hooks.h>
-
-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void get_mmu_context(struct mm_struct *mm);
-extern void destroy_context(struct mm_struct *mm);
-extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk);
-
-#define deactivate_mm(tsk,mm) do { } while (0)
-
-static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- switch_mm(prev, next, NULL);
- local_irq_restore(flags);
-}
-
-/* current active pgd - this is similar to other processors pgd
- * registers like cr3 on the i386
- */
-
-/* defined in arch/cris/mm/fault.c */
-DECLARE_PER_CPU(pgd_t *, current_pgd);
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-#endif
diff --git a/arch/cris/include/asm/page.h b/arch/cris/include/asm/page.h
deleted file mode 100644
index 5b5b3dad7484..000000000000
--- a/arch/cris/include/asm/page.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_PAGE_H
-#define _CRIS_PAGE_H
-
-#include <arch/page.h>
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT 13
-#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
-#define copy_page(to,from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr, pg) clear_page(page)
-#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
- alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-#ifndef __ASSEMBLY__
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-#endif
-
-#define pte_val(x) ((x).pte)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-
-/* On CRIS the PFN numbers doesn't start at 0 so we have to compensate */
-/* for that before indexing into the page table starting at mem_map */
-#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT)
-#define pfn_valid(pfn) (((pfn) - (PAGE_OFFSET >> PAGE_SHIFT)) < max_mapnr)
-
-/* to index into the page map. our pages all start at physical addr PAGE_OFFSET so
- * we can let the map start there. notice that we subtract PAGE_OFFSET because
- * we start our mem_map there - in other ports they map mem_map physically and
- * use __pa instead. in our system both the physical and virtual address of DRAM
- * is too high to let mem_map start at 0, so we do it this way instead (similar
- * to arm and m68k I think)
- */
-
-#define virt_to_page(kaddr) (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT))
-#define virt_addr_valid(kaddr) pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT)
-
-/* convert a page (based on mem_map and forward) to a physical address
- * do this by figuring out the virtual address and then use __pa
- */
-
-#define page_to_phys(page) __pa((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
-
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* _CRIS_PAGE_H */
-
diff --git a/arch/cris/include/asm/pci.h b/arch/cris/include/asm/pci.h
deleted file mode 100644
index dcfef6407ae6..000000000000
--- a/arch/cris/include/asm/pci.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_PCI_H
-#define __ASM_CRIS_PCI_H
-
-
-#ifdef __KERNEL__
-#include <linux/mm.h> /* for struct page */
-
-/* Can be used to override the logic in pci_scan_bus for skipping
- already-configured bus numbers - to be used for buggy BIOSes
- or architectures with incomplete PCI setup by the loader */
-
-#define pcibios_assign_all_busses(void) 1
-
-#define PCIBIOS_MIN_IO 0x1000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#define PCIBIOS_MIN_CARDBUS_IO 0x4000
-
-/* Dynamic DMA mapping stuff.
- * i386 has everything mapped statically.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/scatterlist.h>
-#include <linux/string.h>
-#include <asm/io.h>
-
-/* The PCI address space does equal the physical memory
- * address space. The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS (1)
-
-#define HAVE_PCI_MMAP
-#define ARCH_GENERIC_PCI_MMAP_RESOURCE
-
-#endif /* __KERNEL__ */
-
-/* generic pci stuff */
-#include <asm-generic/pci.h>
-
-#endif /* __ASM_CRIS_PCI_H */
diff --git a/arch/cris/include/asm/pgalloc.h b/arch/cris/include/asm/pgalloc.h
deleted file mode 100644
index d8dc1b834b7d..000000000000
--- a/arch/cris/include/asm/pgalloc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_PGALLOC_H
-#define _CRIS_PGALLOC_H
-
-#include <linux/threads.h>
-#include <linux/mm.h>
-
-#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte)
-#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte))
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-
-static inline pgd_t *pgd_alloc (struct mm_struct *mm)
-{
- return (pgd_t *)get_zeroed_page(GFP_KERNEL);
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- free_page((unsigned long)pgd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
- return pte;
-}
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *pte;
- pte = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
- if (!pte)
- return NULL;
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-#define __pte_free_tlb(tlb,pte,address) \
-do { \
- pgtable_page_dtor(pte); \
- tlb_remove_page((tlb), pte); \
-} while (0)
-
-#define check_pgt_cache() do { } while (0)
-
-#endif
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h
deleted file mode 100644
index 03fca401e23c..000000000000
--- a/arch/cris/include/asm/pgtable.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * CRIS pgtable.h - macros and functions to manipulate page tables.
- */
-
-#ifndef _CRIS_PGTABLE_H
-#define _CRIS_PGTABLE_H
-
-#include <asm/page.h>
-#define __ARCH_USE_5LEVEL_HACK
-#include <asm-generic/pgtable-nopmd.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/sched/mm.h>
-#include <asm/mmu.h>
-#endif
-#include <arch/pgtable.h>
-
-/*
- * The Linux memory management assumes a three-level page table setup. On
- * CRIS, we use that, but "fold" the mid level into the top-level page
- * table. Since the MMU TLB is software loaded through an interrupt, it
- * supports any page table structure, so we could have used a three-level
- * setup, but for the amounts of memory we normally use, a two-level is
- * probably more efficient.
- *
- * This file contains the functions and defines necessary to modify and use
- * the CRIS page table tree.
- */
-#ifndef __ASSEMBLY__
-extern void paging_init(void);
-#endif
-
-/* Certain architectures need to do special things when pte's
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgu(pudptr, pudval) (*(pudptr) = pudval)
-
-/* PGDIR_SHIFT determines the size of the area a second-level page table can
- * map. It is equal to the page size times the number of PTE's that fit in
- * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number.
- */
-
-#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE-1))
-
-/*
- * entries per page directory level: we use a two-level, so
- * we don't really have any PMD directory physically.
- * pointers are 4 bytes so we can use the page size and
- * divide it by 4 (shift by 2).
- */
-#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
-#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2))
-
-/* calculate how many PGD entries a user-level program can use
- * the first mappable virtual address is 0
- * (TASK_SIZE is the maximum virtual address space)
- */
-
-#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-/* zero page used for uninitialized stuff */
-#ifndef __ASSEMBLY__
-extern unsigned long empty_zero_page;
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-#endif
-
-/* number of bits that fit into a memory pointer */
-#define BITS_PER_PTR (8*sizeof(unsigned long))
-
-/* to align the pointer to a pointer address */
-#define PTR_MASK (~(sizeof(void*)-1))
-
-/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
-/* 64-bit machines, beware! SRB. */
-#define SIZEOF_PTR_LOG2 2
-
-/* to find an entry in a page-table */
-#define PAGE_PTR(address) \
-((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
-
-/* to set the page-dir */
-#define SET_PAGE_DIR(tsk,pgdir)
-
-#define pte_none(x) (!pte_val(x))
-#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-/* by removing the _PAGE_KERNEL bit from the comparison, the same pmd_bad
- * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries.
- */
-#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE)
-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
-
-#ifndef __ASSEMBLY__
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-
-static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
-static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_special(pte_t pte) { return 0; }
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
- return pte;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
- return pte;
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
- return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
- pte_val(pte) |= _PAGE_WRITE;
- if (pte_val(pte) & _PAGE_MODIFIED)
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
- pte_val(pte) |= _PAGE_MODIFIED;
- if (pte_val(pte) & _PAGE_WRITE)
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
- pte_val(pte) |= _PAGE_ACCESSED;
- if (pte_val(pte) & _PAGE_READ)
- {
- pte_val(pte) |= _PAGE_SILENT_READ;
- if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) ==
- (_PAGE_WRITE | _PAGE_MODIFIED))
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- }
- return pte;
-}
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-/* What actually goes as arguments to the various functions is less than
- * obvious, but a rule of thumb is that struct page's goes as struct page *,
- * really physical DRAM addresses are unsigned long's, and DRAM "virtual"
- * addresses (the 0xc0xxxxxx's) goes as void *'s.
- */
-
-static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
-{
- pte_t pte;
- /* the PTE needs a physical address */
- pte_val(pte) = __pa(page) | pgprot_val(pgprot);
- return pte;
-}
-
-#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
-
-#define mk_pte_phys(physpage, pgprot) \
-({ \
- pte_t __pte; \
- \
- pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
- __pte; \
-})
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
-
-#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))
-
-
-/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
- * __pte_page(pte_val) refers to the "virtual" DRAM interval
- * pte_pagenr refers to the page-number counted starting from the virtual DRAM start
- */
-
-static inline unsigned long __pte_page(pte_t pte)
-{
- /* the PTE contains a physical address */
- return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
-}
-
-#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
-
-/* permanent address of a page */
-
-#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
-#define pte_page(pte) (mem_map+pte_pagenr(pte))
-
-/* only the pte's themselves need to point to physical DRAM (see above)
- * the pagetable links are purely handled within the kernel SW and thus
- * don't need the __pa and __va transformations.
- */
-
-static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
-{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; }
-
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-
-/* to find an entry in a page-table-directory */
-static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long address)
-{
- return mm->pgd + pgd_index(address);
-}
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/* Find an entry in the third-level page table.. */
-#define __pte_offset(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_map(dir, address) \
- ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-
-#define pte_unmap(pte) do { } while (0)
-#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
-#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#define pte_ERROR(e) \
- printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
-#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
-
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
-
-/*
- * CRIS doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- *
- * Actually I am not sure on what this could be used for.
- */
-static inline void update_mmu_cache(struct vm_area_struct * vma,
- unsigned long address, pte_t *ptep)
-{
-}
-
-/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
-/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
-
-#define __swp_type(x) (((x).val >> 5) & 0x7f)
-#define __swp_offset(x) ((x).val >> 12)
-#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define kern_addr_valid(addr) (1)
-
-#include <asm-generic/pgtable.h>
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init() do { } while (0)
-
-typedef pte_t *pte_addr_t;
-
-#endif /* __ASSEMBLY__ */
-#endif /* _CRIS_PGTABLE_H */
diff --git a/arch/cris/include/asm/processor.h b/arch/cris/include/asm/processor.h
deleted file mode 100644
index ee4d8b03d048..000000000000
--- a/arch/cris/include/asm/processor.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * include/asm-cris/processor.h
- *
- * Copyright (C) 2000, 2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen Initial version
- *
- */
-
-#ifndef __ASM_CRIS_PROCESSOR_H
-#define __ASM_CRIS_PROCESSOR_H
-
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <arch/processor.h>
-#include <arch/system.h>
-
-struct task_struct;
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
-
-/*
- * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack.
- * This macro allows us to find those regs for a task.
- * Notice that subsequent pt_regs stackings, like recursive interrupts occurring while
- * we're in the kernel, won't affect this - only the first user->kernel transition
- * registers are reached by this.
- */
-
-#define user_regs(thread_info) (((struct pt_regs *)((unsigned long)(thread_info) + THREAD_SIZE)) - 1)
-
-/*
- * Dito but for the currently running task
- */
-
-#define task_pt_regs(task) user_regs(task_thread_info(task))
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
- /* Nothing needs to be done. */
-}
-
-#define cpu_relax() barrier()
-
-void default_idle(void);
-
-#endif /* __ASM_CRIS_PROCESSOR_H */
diff --git a/arch/cris/include/asm/ptrace.h b/arch/cris/include/asm/ptrace.h
deleted file mode 100644
index d69295f1a7c8..000000000000
--- a/arch/cris/include/asm/ptrace.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_PTRACE_H
-#define _CRIS_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-
-#define profile_pc(regs) instruction_pointer(regs)
-#define current_user_stack_pointer() rdusp()
-
-#endif /* _CRIS_PTRACE_H */
diff --git a/arch/cris/include/asm/segment.h b/arch/cris/include/asm/segment.h
deleted file mode 100644
index 6ac914b098bf..000000000000
--- a/arch/cris/include/asm/segment.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SEGMENT_H
-#define _ASM_SEGMENT_H
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#endif
diff --git a/arch/cris/include/asm/serial.h b/arch/cris/include/asm/serial.h
deleted file mode 100644
index f51e0e10faa7..000000000000
--- a/arch/cris/include/asm/serial.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SERIAL_H
-#define _ASM_SERIAL_H
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- */
-#define BASE_BAUD (1843200 / 16)
-
-#endif /* _ASM_SERIAL_H */
diff --git a/arch/cris/include/asm/shmparam.h b/arch/cris/include/asm/shmparam.h
deleted file mode 100644
index 704a7257cb0d..000000000000
--- a/arch/cris/include/asm/shmparam.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_SHMPARAM_H
-#define _ASM_CRIS_SHMPARAM_H
-
-/* same as asm-i386/ version.. */
-
-#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
-
-#endif /* _ASM_CRIS_SHMPARAM_H */
diff --git a/arch/cris/include/asm/signal.h b/arch/cris/include/asm/signal.h
deleted file mode 100644
index 64b0943c0b00..000000000000
--- a/arch/cris/include/asm/signal.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_SIGNAL_H
-#define _ASM_CRIS_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-/* Most things should be clean enough to redefine this at will, if care
- is taken to make libc match. */
-
-#define _NSIG 64
-#define _NSIG_BPW 32
-#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t; /* at least 32 bits */
-
-typedef struct {
- unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#define __ARCH_HAS_SA_RESTORER
-
-#include <asm/sigcontext.h>
-
-#endif
diff --git a/arch/cris/include/asm/stacktrace.h b/arch/cris/include/asm/stacktrace.h
deleted file mode 100644
index 154f0c90d0fa..000000000000
--- a/arch/cris/include/asm/stacktrace.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CRIS_STACKTRACE_H
-#define __CRIS_STACKTRACE_H
-
-void walk_stackframe(unsigned long sp,
- int (*fn)(unsigned long addr, void *data),
- void *data);
-
-#endif
diff --git a/arch/cris/include/asm/string.h b/arch/cris/include/asm/string.h
deleted file mode 100644
index bae5a0867785..000000000000
--- a/arch/cris/include/asm/string.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_STRING_H
-#define _ASM_CRIS_STRING_H
-
-/* the optimized memcpy is in arch/cris/lib/string.c */
-
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *, const void *, size_t);
-
-/* New and improved. In arch/cris/lib/memset.c */
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *, int, size_t);
-
-#ifdef CONFIG_ETRAX_ARCH_V32
-/* For v32 we provide strcmp. */
-#define __HAVE_ARCH_STRCMP
-extern int strcmp(const char *s1, const char *s2);
-#endif
-
-#endif
diff --git a/arch/cris/include/asm/swab.h b/arch/cris/include/asm/swab.h
deleted file mode 100644
index 5e1d8cf277fb..000000000000
--- a/arch/cris/include/asm/swab.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_SWAB_H
-#define _CRIS_SWAB_H
-
-#include <arch/swab.h>
-#include <uapi/asm/swab.h>
-
-#endif /* _CRIS_SWAB_H */
diff --git a/arch/cris/include/asm/switch_to.h b/arch/cris/include/asm/switch_to.h
deleted file mode 100644
index dde4acf6e54d..000000000000
--- a/arch/cris/include/asm/switch_to.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_SWITCH_TO_H
-#define __ASM_CRIS_SWITCH_TO_H
-
-/* the switch_to macro calls resume, an asm function in entry.S which does the actual
- * task switching.
- */
-
-extern struct task_struct *resume(struct task_struct *prev, struct task_struct *next, int);
-#define switch_to(prev,next,last) last = resume(prev,next, \
- (int)&((struct task_struct *)0)->thread)
-
-#endif /* __ASM_CRIS_SWITCH_TO_H */
diff --git a/arch/cris/include/asm/termios.h b/arch/cris/include/asm/termios.h
deleted file mode 100644
index 9832bf3221d0..000000000000
--- a/arch/cris/include/asm/termios.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_TERMIOS_H
-#define _CRIS_TERMIOS_H
-
-#include <uapi/asm/termios.h>
-
-
-/* intr=^C quit=^\ erase=del kill=^U
- eof=^D vtime=\0 vmin=\1 sxtc=\0
- start=^Q stop=^S susp=^Z eol=\0
- reprint=^R discard=^U werase=^W lnext=^V
- eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
- unsigned short __tmp; \
- get_user(__tmp,&(termio)->x); \
- *(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
- SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
- copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
- put_user((termios)->c_iflag, &(termio)->c_iflag); \
- put_user((termios)->c_oflag, &(termio)->c_oflag); \
- put_user((termios)->c_cflag, &(termio)->c_cflag); \
- put_user((termios)->c_lflag, &(termio)->c_lflag); \
- put_user((termios)->c_line, &(termio)->c_line); \
- copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif /* _CRIS_TERMIOS_H */
diff --git a/arch/cris/include/asm/thread_info.h b/arch/cris/include/asm/thread_info.h
deleted file mode 100644
index 996fef3be1d5..000000000000
--- a/arch/cris/include/asm/thread_info.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* thread_info.h: CRIS low-level thread information
- *
- * Copyright (C) 2002 David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- *
- * CRIS port by Axis Communications
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/processor.h>
-#include <arch/thread_info.h>
-#include <asm/segment.h>
-#endif
-
-
-/* THREAD_SIZE is the size of the thread_info/kernel_stack combo.
- * normally, the stack is found by doing something like p + THREAD_SIZE
- * in CRIS, a page is 8192 bytes, which seems like a sane size
- */
-#define THREAD_SIZE PAGE_SIZE
-#define THREAD_SIZE_ORDER (0)
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must also be changed
- */
-#ifndef __ASSEMBLY__
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- __u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
- __u32 tls; /* TLS for this thread */
-
- mm_segment_t addr_limit; /* thread address space:
- 0-0xBFFFFFFF for user-thead
- 0-0xFFFFFFFF for kernel-thread
- */
- __u8 supervisor_stack[0];
-};
-
-#endif
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
-#define TIF_SIGPENDING 2 /* signal pending */
-#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
-#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
-#define TIF_MEMDIE 17 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-
-#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
-#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/cris/include/asm/timex.h b/arch/cris/include/asm/timex.h
deleted file mode 100644
index 3840a556612b..000000000000
--- a/arch/cris/include/asm/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/include/asm-cris/timex.h
- *
- * CRIS architecture timex specifications
- */
-
-#ifndef _ASM_CRIS_TIMEX_H
-#define _ASM_CRIS_TIMEX_H
-
-#include <arch/timex.h>
-
-/*
- * We don't have a cycle-counter.. but we do not support SMP anyway where this is
- * used so it does not matter.
- */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- return 0;
-}
-
-#endif
diff --git a/arch/cris/include/asm/tlb.h b/arch/cris/include/asm/tlb.h
deleted file mode 100644
index 1f6a8a67cfda..000000000000
--- a/arch/cris/include/asm/tlb.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_TLB_H
-#define _CRIS_TLB_H
-
-#include <linux/pagemap.h>
-
-#include <arch/tlb.h>
-
-/*
- * cris doesn't need any special per-pte or
- * per-vma handling..
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-#include <asm-generic/tlb.h>
-
-#endif
diff --git a/arch/cris/include/asm/tlbflush.h b/arch/cris/include/asm/tlbflush.h
deleted file mode 100644
index e7cb964536d0..000000000000
--- a/arch/cris/include/asm/tlbflush.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _CRIS_TLBFLUSH_H
-#define _CRIS_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/processor.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-
-/*
- * TLB flushing (implemented in arch/cris/mm/tlb.c):
- *
- * - flush_tlb() flushes the current mm struct TLBs
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(mm, start, end) flushes a range of pages
- *
- */
-
-extern void __flush_tlb_all(void);
-extern void __flush_tlb_mm(struct mm_struct *mm);
-extern void __flush_tlb_page(struct vm_area_struct *vma,
- unsigned long addr);
-
-#define flush_tlb_all __flush_tlb_all
-#define flush_tlb_mm __flush_tlb_mm
-#define flush_tlb_page __flush_tlb_page
-
-static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
-{
- flush_tlb_mm(vma->vm_mm);
-}
-
-static inline void flush_tlb(void)
-{
- flush_tlb_mm(current->mm);
-}
-
-#define flush_tlb_kernel_range(start, end) flush_tlb_all()
-
-#endif /* _CRIS_TLBFLUSH_H */
diff --git a/arch/cris/include/asm/uaccess.h b/arch/cris/include/asm/uaccess.h
deleted file mode 100644
index 3b42ab0cae93..000000000000
--- a/arch/cris/include/asm/uaccess.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Authors: Bjorn Wesen (bjornw@axis.com)
- * Hans-Peter Nilsson (hp@axis.com)
- */
-
-/* Asm:s have been tweaked (within the domain of correctness) to give
- satisfactory results for "gcc version 2.96 20000427 (experimental)".
-
- Check regularly...
-
- Register $r9 is chosen for temporaries, being a call-clobbered register
- first in line to be used (notably for local blocks), not colliding with
- parameter registers. */
-
-#ifndef _CRIS_UACCESS_H
-#define _CRIS_UACCESS_H
-
-#include <asm/processor.h>
-#include <asm/page.h>
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-/* addr_limit is the maximum accessible address for the task. we misuse
- * the KERNEL_DS and USER_DS values to both assign and compare the
- * addr_limit values through the equally misnamed get/set_fs macros.
- * (see above)
- */
-
-#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS MAKE_MM_SEG(TASK_SIZE)
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-#define __kernel_ok (uaccess_kernel())
-#define __user_ok(addr, size) \
- (((size) <= TASK_SIZE) && ((addr) <= TASK_SIZE-(size)))
-#define __access_ok(addr, size) (__kernel_ok || __user_ok((addr), (size)))
-#define access_ok(type, addr, size) __access_ok((unsigned long)(addr), (size))
-
-#include <arch/uaccess.h>
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the ugliness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- *
- * As we use the same address space for kernel and user data on
- * CRIS, we can just do these as direct assignments. (Of course, the
- * exception handling means that it's no longer "just"...)
- */
-#define get_user(x, ptr) \
- __get_user_check((x), (ptr), sizeof(*(ptr)))
-#define put_user(x, ptr) \
- __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-#define __get_user(x, ptr) \
- __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-#define __put_user(x, ptr) \
- __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-extern long __put_user_bad(void);
-
-#define __put_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- switch (size) { \
- case 1: \
- __put_user_asm(x, ptr, retval, "move.b"); \
- break; \
- case 2: \
- __put_user_asm(x, ptr, retval, "move.w"); \
- break; \
- case 4: \
- __put_user_asm(x, ptr, retval, "move.d"); \
- break; \
- case 8: \
- __put_user_asm_64(x, ptr, retval); \
- break; \
- default: \
- __put_user_bad(); \
- } \
-} while (0)
-
-#define __get_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- switch (size) { \
- case 1: \
- __get_user_asm(x, ptr, retval, "move.b"); \
- break; \
- case 2: \
- __get_user_asm(x, ptr, retval, "move.w"); \
- break; \
- case 4: \
- __get_user_asm(x, ptr, retval, "move.d"); \
- break; \
- case 8: \
- __get_user_asm_64(x, ptr, retval); \
- break; \
- default: \
- (x) = __get_user_bad(); \
- } \
-} while (0)
-
-#define __put_user_nocheck(x, ptr, size) \
-({ \
- long __pu_err; \
- __put_user_size((x), (ptr), (size), __pu_err); \
- __pu_err; \
-})
-
-#define __put_user_check(x, ptr, size) \
-({ \
- long __pu_err = -EFAULT; \
- __typeof__(*(ptr)) *__pu_addr = (ptr); \
- if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
- __put_user_size((x), __pu_addr, (size), __pu_err); \
- __pu_err; \
-})
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
-
-
-
-#define __get_user_nocheck(x, ptr, size) \
-({ \
- long __gu_err, __gu_val; \
- __get_user_size(__gu_val, (ptr), (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-#define __get_user_check(x, ptr, size) \
-({ \
- long __gu_err = -EFAULT, __gu_val = 0; \
- const __typeof__(*(ptr)) *__gu_addr = (ptr); \
- if (access_ok(VERIFY_READ, __gu_addr, size)) \
- __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-extern long __get_user_bad(void);
-
-/* More complex functions. Most are inline, but some call functions that
- live in lib/usercopy.c */
-
-extern unsigned long __copy_user(void __user *to, const void *from, unsigned long n);
-extern unsigned long __copy_user_in(void *to, const void __user *from, unsigned long n);
-extern unsigned long __do_clear_user(void __user *to, unsigned long n);
-
-static inline long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- long res = -EFAULT;
-
- if (access_ok(VERIFY_READ, src, 1))
- res = __do_strncpy_from_user(dst, src, count);
- return res;
-}
-
-
-/* Note that these expand awfully if made into switch constructs, so
- don't do that. */
-
-static inline unsigned long
-__constant_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- unsigned long ret = 0;
-
- if (n == 0)
- ;
- else if (n == 1)
- __asm_copy_from_user_1(to, from, ret);
- else if (n == 2)
- __asm_copy_from_user_2(to, from, ret);
- else if (n == 3)
- __asm_copy_from_user_3(to, from, ret);
- else if (n == 4)
- __asm_copy_from_user_4(to, from, ret);
- else if (n == 5)
- __asm_copy_from_user_5(to, from, ret);
- else if (n == 6)
- __asm_copy_from_user_6(to, from, ret);
- else if (n == 7)
- __asm_copy_from_user_7(to, from, ret);
- else if (n == 8)
- __asm_copy_from_user_8(to, from, ret);
- else if (n == 9)
- __asm_copy_from_user_9(to, from, ret);
- else if (n == 10)
- __asm_copy_from_user_10(to, from, ret);
- else if (n == 11)
- __asm_copy_from_user_11(to, from, ret);
- else if (n == 12)
- __asm_copy_from_user_12(to, from, ret);
- else if (n == 13)
- __asm_copy_from_user_13(to, from, ret);
- else if (n == 14)
- __asm_copy_from_user_14(to, from, ret);
- else if (n == 15)
- __asm_copy_from_user_15(to, from, ret);
- else if (n == 16)
- __asm_copy_from_user_16(to, from, ret);
- else if (n == 20)
- __asm_copy_from_user_20(to, from, ret);
- else if (n == 24)
- __asm_copy_from_user_24(to, from, ret);
- else
- ret = __copy_user_in(to, from, n);
-
- return ret;
-}
-
-/* Ditto, don't make a switch out of this. */
-
-static inline unsigned long
-__constant_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- unsigned long ret = 0;
-
- if (n == 0)
- ;
- else if (n == 1)
- __asm_copy_to_user_1(to, from, ret);
- else if (n == 2)
- __asm_copy_to_user_2(to, from, ret);
- else if (n == 3)
- __asm_copy_to_user_3(to, from, ret);
- else if (n == 4)
- __asm_copy_to_user_4(to, from, ret);
- else if (n == 5)
- __asm_copy_to_user_5(to, from, ret);
- else if (n == 6)
- __asm_copy_to_user_6(to, from, ret);
- else if (n == 7)
- __asm_copy_to_user_7(to, from, ret);
- else if (n == 8)
- __asm_copy_to_user_8(to, from, ret);
- else if (n == 9)
- __asm_copy_to_user_9(to, from, ret);
- else if (n == 10)
- __asm_copy_to_user_10(to, from, ret);
- else if (n == 11)
- __asm_copy_to_user_11(to, from, ret);
- else if (n == 12)
- __asm_copy_to_user_12(to, from, ret);
- else if (n == 13)
- __asm_copy_to_user_13(to, from, ret);
- else if (n == 14)
- __asm_copy_to_user_14(to, from, ret);
- else if (n == 15)
- __asm_copy_to_user_15(to, from, ret);
- else if (n == 16)
- __asm_copy_to_user_16(to, from, ret);
- else if (n == 20)
- __asm_copy_to_user_20(to, from, ret);
- else if (n == 24)
- __asm_copy_to_user_24(to, from, ret);
- else
- ret = __copy_user(to, from, n);
-
- return ret;
-}
-
-/* No switch, please. */
-
-static inline unsigned long
-__constant_clear_user(void __user *to, unsigned long n)
-{
- unsigned long ret = 0;
-
- if (n == 0)
- ;
- else if (n == 1)
- __asm_clear_1(to, ret);
- else if (n == 2)
- __asm_clear_2(to, ret);
- else if (n == 3)
- __asm_clear_3(to, ret);
- else if (n == 4)
- __asm_clear_4(to, ret);
- else if (n == 8)
- __asm_clear_8(to, ret);
- else if (n == 12)
- __asm_clear_12(to, ret);
- else if (n == 16)
- __asm_clear_16(to, ret);
- else if (n == 20)
- __asm_clear_20(to, ret);
- else if (n == 24)
- __asm_clear_24(to, ret);
- else
- ret = __do_clear_user(to, n);
-
- return ret;
-}
-
-
-static inline size_t clear_user(void __user *to, size_t n)
-{
- if (unlikely(!access_ok(VERIFY_WRITE, to, n)))
- return n;
- if (__builtin_constant_p(n))
- return __constant_clear_user(to, n);
- else
- return __do_clear_user(to, n);
-}
-
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- if (__builtin_constant_p(n))
- return __constant_copy_from_user(to, from, n);
- else
- return __copy_user_in(to, from, n);
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- if (__builtin_constant_p(n))
- return __constant_copy_to_user(to, from, n);
- else
- return __copy_user(to, from, n);
-}
-
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-
-static inline unsigned long
-__clear_user(void __user *to, unsigned long n)
-{
- return __do_clear_user(to, n);
-}
-
-#endif /* _CRIS_UACCESS_H */
diff --git a/arch/cris/include/asm/ucontext.h b/arch/cris/include/asm/ucontext.h
deleted file mode 100644
index 22f7e7cf59c8..000000000000
--- a/arch/cris/include/asm/ucontext.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_UCONTEXT_H
-#define _ASM_CRIS_UCONTEXT_H
-
-struct ucontext {
- unsigned long uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-#endif /* !_ASM_CRIS_UCONTEXT_H */
diff --git a/arch/cris/include/asm/unaligned.h b/arch/cris/include/asm/unaligned.h
deleted file mode 100644
index 21772cf600dd..000000000000
--- a/arch/cris/include/asm/unaligned.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_UNALIGNED_H
-#define _ASM_CRIS_UNALIGNED_H
-
-/*
- * CRIS can do unaligned accesses itself.
- */
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-
-#endif /* _ASM_CRIS_UNALIGNED_H */
diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h
deleted file mode 100644
index 6a92c0505156..000000000000
--- a/arch/cris/include/asm/unistd.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_CRIS_UNISTD_H_
-#define _ASM_CRIS_UNISTD_H_
-
-#include <uapi/asm/unistd.h>
-
-
-#define NR_syscalls 365
-
-#include <arch/unistd.h>
-
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLD_MMAP
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-#define __ARCH_WANT_SYS_CLONE
-
-#endif /* _ASM_CRIS_UNISTD_H_ */
diff --git a/arch/cris/include/asm/user.h b/arch/cris/include/asm/user.h
deleted file mode 100644
index a19c39547248..000000000000
--- a/arch/cris/include/asm/user.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_CRIS_USER_H
-#define __ASM_CRIS_USER_H
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <arch/user.h>
-
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd). The file contents are as follows:
- *
- * upage: 1 page consisting of a user struct that tells gdb
- * what is present in the file. Directly after this is a
- * copy of the task_struct, which is currently not used by gdb,
- * but it may come in handy at some point. All of the registers
- * are stored as part of the upage. The upage should always be
- * only one page long.
- * data: The data segment follows next. We use current->end_text to
- * current->brk to pick up all of the user variables, plus any memory
- * that may have been sbrk'ed. No attempt is made to determine if a
- * page is demand-zero or if a page is totally unused, we just cover
- * the entire range. All of the addresses are rounded in such a way
- * that an integral number of pages is written.
- * stack: We need the stack information in order to get a meaningful
- * backtrace. We need to write the data from usp to
- * current->start_stack, so we round each of these in order to be able
- * to write an integer number of pages.
- */
-
-struct user {
- struct user_regs_struct regs; /* entire machine state */
- size_t u_tsize; /* text size (pages) */
- size_t u_dsize; /* data size (pages) */
- size_t u_ssize; /* stack size (pages) */
- unsigned long start_code; /* text starting address */
- unsigned long start_data; /* data starting address */
- unsigned long start_stack; /* stack starting address */
- long int signal; /* signal causing core dump */
- unsigned long u_ar0; /* help gdb find registers */
- unsigned long magic; /* identifies a core file */
- char u_comm[32]; /* user command name */
-};
-
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_DATA_START_ADDR (u.start_data)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* __ASM_CRIS_USER_H */
diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh b/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh
deleted file mode 100644
index 6ac3a7bc9760..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh
+++ /dev/null
@@ -1,7306 +0,0 @@
-/*
-!* This file was automatically generated by /n/asic/bin/reg_macro_gen
-!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'.
-!* Editing within this file is thus not recommended,
-!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead.
-!*/
-
-
-/*
-!* Bus interface configuration registers
-!*/
-
-#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000)
-#define R_WAITSTATES__pcs4_7_zw__BITNR 30
-#define R_WAITSTATES__pcs4_7_zw__WIDTH 2
-#define R_WAITSTATES__pcs4_7_ew__BITNR 28
-#define R_WAITSTATES__pcs4_7_ew__WIDTH 2
-#define R_WAITSTATES__pcs4_7_lw__BITNR 24
-#define R_WAITSTATES__pcs4_7_lw__WIDTH 4
-#define R_WAITSTATES__pcs0_3_zw__BITNR 22
-#define R_WAITSTATES__pcs0_3_zw__WIDTH 2
-#define R_WAITSTATES__pcs0_3_ew__BITNR 20
-#define R_WAITSTATES__pcs0_3_ew__WIDTH 2
-#define R_WAITSTATES__pcs0_3_lw__BITNR 16
-#define R_WAITSTATES__pcs0_3_lw__WIDTH 4
-#define R_WAITSTATES__sram_zw__BITNR 14
-#define R_WAITSTATES__sram_zw__WIDTH 2
-#define R_WAITSTATES__sram_ew__BITNR 12
-#define R_WAITSTATES__sram_ew__WIDTH 2
-#define R_WAITSTATES__sram_lw__BITNR 8
-#define R_WAITSTATES__sram_lw__WIDTH 4
-#define R_WAITSTATES__flash_zw__BITNR 6
-#define R_WAITSTATES__flash_zw__WIDTH 2
-#define R_WAITSTATES__flash_ew__BITNR 4
-#define R_WAITSTATES__flash_ew__WIDTH 2
-#define R_WAITSTATES__flash_lw__BITNR 0
-#define R_WAITSTATES__flash_lw__WIDTH 4
-
-#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004)
-#define R_BUS_CONFIG__sram_type__BITNR 9
-#define R_BUS_CONFIG__sram_type__WIDTH 1
-#define R_BUS_CONFIG__sram_type__cwe 1
-#define R_BUS_CONFIG__sram_type__bwe 0
-#define R_BUS_CONFIG__dma_burst__BITNR 8
-#define R_BUS_CONFIG__dma_burst__WIDTH 1
-#define R_BUS_CONFIG__dma_burst__burst16 1
-#define R_BUS_CONFIG__dma_burst__burst32 0
-#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
-#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1
-#define R_BUS_CONFIG__pcs4_7_wr__ext 1
-#define R_BUS_CONFIG__pcs4_7_wr__norm 0
-#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
-#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1
-#define R_BUS_CONFIG__pcs0_3_wr__ext 1
-#define R_BUS_CONFIG__pcs0_3_wr__norm 0
-#define R_BUS_CONFIG__sram_wr__BITNR 5
-#define R_BUS_CONFIG__sram_wr__WIDTH 1
-#define R_BUS_CONFIG__sram_wr__ext 1
-#define R_BUS_CONFIG__sram_wr__norm 0
-#define R_BUS_CONFIG__flash_wr__BITNR 4
-#define R_BUS_CONFIG__flash_wr__WIDTH 1
-#define R_BUS_CONFIG__flash_wr__ext 1
-#define R_BUS_CONFIG__flash_wr__norm 0
-#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
-#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1
-#define R_BUS_CONFIG__pcs4_7_bw__bw32 1
-#define R_BUS_CONFIG__pcs4_7_bw__bw16 0
-#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
-#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1
-#define R_BUS_CONFIG__pcs0_3_bw__bw32 1
-#define R_BUS_CONFIG__pcs0_3_bw__bw16 0
-#define R_BUS_CONFIG__sram_bw__BITNR 1
-#define R_BUS_CONFIG__sram_bw__WIDTH 1
-#define R_BUS_CONFIG__sram_bw__bw32 1
-#define R_BUS_CONFIG__sram_bw__bw16 0
-#define R_BUS_CONFIG__flash_bw__BITNR 0
-#define R_BUS_CONFIG__flash_bw__WIDTH 1
-#define R_BUS_CONFIG__flash_bw__bw32 1
-#define R_BUS_CONFIG__flash_bw__bw16 0
-
-#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004)
-#define R_BUS_STATUS__pll_lock_tm__BITNR 5
-#define R_BUS_STATUS__pll_lock_tm__WIDTH 1
-#define R_BUS_STATUS__pll_lock_tm__expired 0
-#define R_BUS_STATUS__pll_lock_tm__counting 1
-#define R_BUS_STATUS__both_faults__BITNR 4
-#define R_BUS_STATUS__both_faults__WIDTH 1
-#define R_BUS_STATUS__both_faults__no 0
-#define R_BUS_STATUS__both_faults__yes 1
-#define R_BUS_STATUS__bsen___BITNR 3
-#define R_BUS_STATUS__bsen___WIDTH 1
-#define R_BUS_STATUS__bsen___enable 0
-#define R_BUS_STATUS__bsen___disable 1
-#define R_BUS_STATUS__boot__BITNR 1
-#define R_BUS_STATUS__boot__WIDTH 2
-#define R_BUS_STATUS__boot__uncached 0
-#define R_BUS_STATUS__boot__serial 1
-#define R_BUS_STATUS__boot__network 2
-#define R_BUS_STATUS__boot__parallel 3
-#define R_BUS_STATUS__flashw__BITNR 0
-#define R_BUS_STATUS__flashw__WIDTH 1
-#define R_BUS_STATUS__flashw__bw32 1
-#define R_BUS_STATUS__flashw__bw16 0
-
-#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
-#define R_DRAM_TIMING__sdram__BITNR 31
-#define R_DRAM_TIMING__sdram__WIDTH 1
-#define R_DRAM_TIMING__sdram__enable 1
-#define R_DRAM_TIMING__sdram__disable 0
-#define R_DRAM_TIMING__ref__BITNR 14
-#define R_DRAM_TIMING__ref__WIDTH 2
-#define R_DRAM_TIMING__ref__e52us 0
-#define R_DRAM_TIMING__ref__e13us 1
-#define R_DRAM_TIMING__ref__e8700ns 2
-#define R_DRAM_TIMING__ref__disable 3
-#define R_DRAM_TIMING__rp__BITNR 12
-#define R_DRAM_TIMING__rp__WIDTH 2
-#define R_DRAM_TIMING__rs__BITNR 10
-#define R_DRAM_TIMING__rs__WIDTH 2
-#define R_DRAM_TIMING__rh__BITNR 8
-#define R_DRAM_TIMING__rh__WIDTH 2
-#define R_DRAM_TIMING__w__BITNR 7
-#define R_DRAM_TIMING__w__WIDTH 1
-#define R_DRAM_TIMING__w__norm 0
-#define R_DRAM_TIMING__w__ext 1
-#define R_DRAM_TIMING__c__BITNR 6
-#define R_DRAM_TIMING__c__WIDTH 1
-#define R_DRAM_TIMING__c__norm 0
-#define R_DRAM_TIMING__c__ext 1
-#define R_DRAM_TIMING__cz__BITNR 4
-#define R_DRAM_TIMING__cz__WIDTH 2
-#define R_DRAM_TIMING__cp__BITNR 2
-#define R_DRAM_TIMING__cp__WIDTH 2
-#define R_DRAM_TIMING__cw__BITNR 0
-#define R_DRAM_TIMING__cw__WIDTH 2
-
-#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
-#define R_SDRAM_TIMING__sdram__BITNR 31
-#define R_SDRAM_TIMING__sdram__WIDTH 1
-#define R_SDRAM_TIMING__sdram__enable 1
-#define R_SDRAM_TIMING__sdram__disable 0
-#define R_SDRAM_TIMING__mrs_data__BITNR 16
-#define R_SDRAM_TIMING__mrs_data__WIDTH 15
-#define R_SDRAM_TIMING__ref__BITNR 14
-#define R_SDRAM_TIMING__ref__WIDTH 2
-#define R_SDRAM_TIMING__ref__e52us 0
-#define R_SDRAM_TIMING__ref__e13us 1
-#define R_SDRAM_TIMING__ref__e6500ns 2
-#define R_SDRAM_TIMING__ref__disable 3
-#define R_SDRAM_TIMING__ddr__BITNR 13
-#define R_SDRAM_TIMING__ddr__WIDTH 1
-#define R_SDRAM_TIMING__ddr__on 1
-#define R_SDRAM_TIMING__ddr__off 0
-#define R_SDRAM_TIMING__clk100__BITNR 12
-#define R_SDRAM_TIMING__clk100__WIDTH 1
-#define R_SDRAM_TIMING__clk100__on 1
-#define R_SDRAM_TIMING__clk100__off 0
-#define R_SDRAM_TIMING__ps__BITNR 11
-#define R_SDRAM_TIMING__ps__WIDTH 1
-#define R_SDRAM_TIMING__ps__on 1
-#define R_SDRAM_TIMING__ps__off 0
-#define R_SDRAM_TIMING__cmd__BITNR 9
-#define R_SDRAM_TIMING__cmd__WIDTH 2
-#define R_SDRAM_TIMING__cmd__pre 3
-#define R_SDRAM_TIMING__cmd__ref 2
-#define R_SDRAM_TIMING__cmd__mrs 1
-#define R_SDRAM_TIMING__cmd__nop 0
-#define R_SDRAM_TIMING__pde__BITNR 8
-#define R_SDRAM_TIMING__pde__WIDTH 1
-#define R_SDRAM_TIMING__rc__BITNR 6
-#define R_SDRAM_TIMING__rc__WIDTH 2
-#define R_SDRAM_TIMING__rp__BITNR 4
-#define R_SDRAM_TIMING__rp__WIDTH 2
-#define R_SDRAM_TIMING__rcd__BITNR 2
-#define R_SDRAM_TIMING__rcd__WIDTH 2
-#define R_SDRAM_TIMING__cl__BITNR 0
-#define R_SDRAM_TIMING__cl__WIDTH 2
-
-#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
-#define R_DRAM_CONFIG__wmm1__BITNR 31
-#define R_DRAM_CONFIG__wmm1__WIDTH 1
-#define R_DRAM_CONFIG__wmm1__wmm 1
-#define R_DRAM_CONFIG__wmm1__norm 0
-#define R_DRAM_CONFIG__wmm0__BITNR 30
-#define R_DRAM_CONFIG__wmm0__WIDTH 1
-#define R_DRAM_CONFIG__wmm0__wmm 1
-#define R_DRAM_CONFIG__wmm0__norm 0
-#define R_DRAM_CONFIG__sh1__BITNR 27
-#define R_DRAM_CONFIG__sh1__WIDTH 3
-#define R_DRAM_CONFIG__sh0__BITNR 24
-#define R_DRAM_CONFIG__sh0__WIDTH 3
-#define R_DRAM_CONFIG__w__BITNR 23
-#define R_DRAM_CONFIG__w__WIDTH 1
-#define R_DRAM_CONFIG__w__bw16 0
-#define R_DRAM_CONFIG__w__bw32 1
-#define R_DRAM_CONFIG__c__BITNR 22
-#define R_DRAM_CONFIG__c__WIDTH 1
-#define R_DRAM_CONFIG__c__byte 0
-#define R_DRAM_CONFIG__c__bank 1
-#define R_DRAM_CONFIG__e__BITNR 21
-#define R_DRAM_CONFIG__e__WIDTH 1
-#define R_DRAM_CONFIG__e__fast 0
-#define R_DRAM_CONFIG__e__edo 1
-#define R_DRAM_CONFIG__group_sel__BITNR 16
-#define R_DRAM_CONFIG__group_sel__WIDTH 5
-#define R_DRAM_CONFIG__group_sel__grp0 0
-#define R_DRAM_CONFIG__group_sel__grp1 1
-#define R_DRAM_CONFIG__group_sel__bit9 9
-#define R_DRAM_CONFIG__group_sel__bit10 10
-#define R_DRAM_CONFIG__group_sel__bit11 11
-#define R_DRAM_CONFIG__group_sel__bit12 12
-#define R_DRAM_CONFIG__group_sel__bit13 13
-#define R_DRAM_CONFIG__group_sel__bit14 14
-#define R_DRAM_CONFIG__group_sel__bit15 15
-#define R_DRAM_CONFIG__group_sel__bit16 16
-#define R_DRAM_CONFIG__group_sel__bit17 17
-#define R_DRAM_CONFIG__group_sel__bit18 18
-#define R_DRAM_CONFIG__group_sel__bit19 19
-#define R_DRAM_CONFIG__group_sel__bit20 20
-#define R_DRAM_CONFIG__group_sel__bit21 21
-#define R_DRAM_CONFIG__group_sel__bit22 22
-#define R_DRAM_CONFIG__group_sel__bit23 23
-#define R_DRAM_CONFIG__group_sel__bit24 24
-#define R_DRAM_CONFIG__group_sel__bit25 25
-#define R_DRAM_CONFIG__group_sel__bit26 26
-#define R_DRAM_CONFIG__group_sel__bit27 27
-#define R_DRAM_CONFIG__group_sel__bit28 28
-#define R_DRAM_CONFIG__group_sel__bit29 29
-#define R_DRAM_CONFIG__ca1__BITNR 13
-#define R_DRAM_CONFIG__ca1__WIDTH 3
-#define R_DRAM_CONFIG__bank23sel__BITNR 8
-#define R_DRAM_CONFIG__bank23sel__WIDTH 5
-#define R_DRAM_CONFIG__bank23sel__bank0 0
-#define R_DRAM_CONFIG__bank23sel__bank1 1
-#define R_DRAM_CONFIG__bank23sel__bit9 9
-#define R_DRAM_CONFIG__bank23sel__bit10 10
-#define R_DRAM_CONFIG__bank23sel__bit11 11
-#define R_DRAM_CONFIG__bank23sel__bit12 12
-#define R_DRAM_CONFIG__bank23sel__bit13 13
-#define R_DRAM_CONFIG__bank23sel__bit14 14
-#define R_DRAM_CONFIG__bank23sel__bit15 15
-#define R_DRAM_CONFIG__bank23sel__bit16 16
-#define R_DRAM_CONFIG__bank23sel__bit17 17
-#define R_DRAM_CONFIG__bank23sel__bit18 18
-#define R_DRAM_CONFIG__bank23sel__bit19 19
-#define R_DRAM_CONFIG__bank23sel__bit20 20
-#define R_DRAM_CONFIG__bank23sel__bit21 21
-#define R_DRAM_CONFIG__bank23sel__bit22 22
-#define R_DRAM_CONFIG__bank23sel__bit23 23
-#define R_DRAM_CONFIG__bank23sel__bit24 24
-#define R_DRAM_CONFIG__bank23sel__bit25 25
-#define R_DRAM_CONFIG__bank23sel__bit26 26
-#define R_DRAM_CONFIG__bank23sel__bit27 27
-#define R_DRAM_CONFIG__bank23sel__bit28 28
-#define R_DRAM_CONFIG__bank23sel__bit29 29
-#define R_DRAM_CONFIG__ca0__BITNR 5
-#define R_DRAM_CONFIG__ca0__WIDTH 3
-#define R_DRAM_CONFIG__bank01sel__BITNR 0
-#define R_DRAM_CONFIG__bank01sel__WIDTH 5
-#define R_DRAM_CONFIG__bank01sel__bank0 0
-#define R_DRAM_CONFIG__bank01sel__bank1 1
-#define R_DRAM_CONFIG__bank01sel__bit9 9
-#define R_DRAM_CONFIG__bank01sel__bit10 10
-#define R_DRAM_CONFIG__bank01sel__bit11 11
-#define R_DRAM_CONFIG__bank01sel__bit12 12
-#define R_DRAM_CONFIG__bank01sel__bit13 13
-#define R_DRAM_CONFIG__bank01sel__bit14 14
-#define R_DRAM_CONFIG__bank01sel__bit15 15
-#define R_DRAM_CONFIG__bank01sel__bit16 16
-#define R_DRAM_CONFIG__bank01sel__bit17 17
-#define R_DRAM_CONFIG__bank01sel__bit18 18
-#define R_DRAM_CONFIG__bank01sel__bit19 19
-#define R_DRAM_CONFIG__bank01sel__bit20 20
-#define R_DRAM_CONFIG__bank01sel__bit21 21
-#define R_DRAM_CONFIG__bank01sel__bit22 22
-#define R_DRAM_CONFIG__bank01sel__bit23 23
-#define R_DRAM_CONFIG__bank01sel__bit24 24
-#define R_DRAM_CONFIG__bank01sel__bit25 25
-#define R_DRAM_CONFIG__bank01sel__bit26 26
-#define R_DRAM_CONFIG__bank01sel__bit27 27
-#define R_DRAM_CONFIG__bank01sel__bit28 28
-#define R_DRAM_CONFIG__bank01sel__bit29 29
-
-#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
-#define R_SDRAM_CONFIG__wmm1__BITNR 31
-#define R_SDRAM_CONFIG__wmm1__WIDTH 1
-#define R_SDRAM_CONFIG__wmm1__wmm 1
-#define R_SDRAM_CONFIG__wmm1__norm 0
-#define R_SDRAM_CONFIG__wmm0__BITNR 30
-#define R_SDRAM_CONFIG__wmm0__WIDTH 1
-#define R_SDRAM_CONFIG__wmm0__wmm 1
-#define R_SDRAM_CONFIG__wmm0__norm 0
-#define R_SDRAM_CONFIG__sh1__BITNR 27
-#define R_SDRAM_CONFIG__sh1__WIDTH 3
-#define R_SDRAM_CONFIG__sh0__BITNR 24
-#define R_SDRAM_CONFIG__sh0__WIDTH 3
-#define R_SDRAM_CONFIG__w__BITNR 23
-#define R_SDRAM_CONFIG__w__WIDTH 1
-#define R_SDRAM_CONFIG__w__bw16 0
-#define R_SDRAM_CONFIG__w__bw32 1
-#define R_SDRAM_CONFIG__type1__BITNR 22
-#define R_SDRAM_CONFIG__type1__WIDTH 1
-#define R_SDRAM_CONFIG__type1__bank2 0
-#define R_SDRAM_CONFIG__type1__bank4 1
-#define R_SDRAM_CONFIG__type0__BITNR 21
-#define R_SDRAM_CONFIG__type0__WIDTH 1
-#define R_SDRAM_CONFIG__type0__bank2 0
-#define R_SDRAM_CONFIG__type0__bank4 1
-#define R_SDRAM_CONFIG__group_sel__BITNR 16
-#define R_SDRAM_CONFIG__group_sel__WIDTH 5
-#define R_SDRAM_CONFIG__group_sel__grp0 0
-#define R_SDRAM_CONFIG__group_sel__grp1 1
-#define R_SDRAM_CONFIG__group_sel__bit9 9
-#define R_SDRAM_CONFIG__group_sel__bit10 10
-#define R_SDRAM_CONFIG__group_sel__bit11 11
-#define R_SDRAM_CONFIG__group_sel__bit12 12
-#define R_SDRAM_CONFIG__group_sel__bit13 13
-#define R_SDRAM_CONFIG__group_sel__bit14 14
-#define R_SDRAM_CONFIG__group_sel__bit15 15
-#define R_SDRAM_CONFIG__group_sel__bit16 16
-#define R_SDRAM_CONFIG__group_sel__bit17 17
-#define R_SDRAM_CONFIG__group_sel__bit18 18
-#define R_SDRAM_CONFIG__group_sel__bit19 19
-#define R_SDRAM_CONFIG__group_sel__bit20 20
-#define R_SDRAM_CONFIG__group_sel__bit21 21
-#define R_SDRAM_CONFIG__group_sel__bit22 22
-#define R_SDRAM_CONFIG__group_sel__bit23 23
-#define R_SDRAM_CONFIG__group_sel__bit24 24
-#define R_SDRAM_CONFIG__group_sel__bit25 25
-#define R_SDRAM_CONFIG__group_sel__bit26 26
-#define R_SDRAM_CONFIG__group_sel__bit27 27
-#define R_SDRAM_CONFIG__group_sel__bit28 28
-#define R_SDRAM_CONFIG__group_sel__bit29 29
-#define R_SDRAM_CONFIG__ca1__BITNR 13
-#define R_SDRAM_CONFIG__ca1__WIDTH 3
-#define R_SDRAM_CONFIG__bank_sel1__BITNR 8
-#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5
-#define R_SDRAM_CONFIG__bank_sel1__bit9 9
-#define R_SDRAM_CONFIG__bank_sel1__bit10 10
-#define R_SDRAM_CONFIG__bank_sel1__bit11 11
-#define R_SDRAM_CONFIG__bank_sel1__bit12 12
-#define R_SDRAM_CONFIG__bank_sel1__bit13 13
-#define R_SDRAM_CONFIG__bank_sel1__bit14 14
-#define R_SDRAM_CONFIG__bank_sel1__bit15 15
-#define R_SDRAM_CONFIG__bank_sel1__bit16 16
-#define R_SDRAM_CONFIG__bank_sel1__bit17 17
-#define R_SDRAM_CONFIG__bank_sel1__bit18 18
-#define R_SDRAM_CONFIG__bank_sel1__bit19 19
-#define R_SDRAM_CONFIG__bank_sel1__bit20 20
-#define R_SDRAM_CONFIG__bank_sel1__bit21 21
-#define R_SDRAM_CONFIG__bank_sel1__bit22 22
-#define R_SDRAM_CONFIG__bank_sel1__bit23 23
-#define R_SDRAM_CONFIG__bank_sel1__bit24 24
-#define R_SDRAM_CONFIG__bank_sel1__bit25 25
-#define R_SDRAM_CONFIG__bank_sel1__bit26 26
-#define R_SDRAM_CONFIG__bank_sel1__bit27 27
-#define R_SDRAM_CONFIG__bank_sel1__bit28 28
-#define R_SDRAM_CONFIG__bank_sel1__bit29 29
-#define R_SDRAM_CONFIG__ca0__BITNR 5
-#define R_SDRAM_CONFIG__ca0__WIDTH 3
-#define R_SDRAM_CONFIG__bank_sel0__BITNR 0
-#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5
-#define R_SDRAM_CONFIG__bank_sel0__bit9 9
-#define R_SDRAM_CONFIG__bank_sel0__bit10 10
-#define R_SDRAM_CONFIG__bank_sel0__bit11 11
-#define R_SDRAM_CONFIG__bank_sel0__bit12 12
-#define R_SDRAM_CONFIG__bank_sel0__bit13 13
-#define R_SDRAM_CONFIG__bank_sel0__bit14 14
-#define R_SDRAM_CONFIG__bank_sel0__bit15 15
-#define R_SDRAM_CONFIG__bank_sel0__bit16 16
-#define R_SDRAM_CONFIG__bank_sel0__bit17 17
-#define R_SDRAM_CONFIG__bank_sel0__bit18 18
-#define R_SDRAM_CONFIG__bank_sel0__bit19 19
-#define R_SDRAM_CONFIG__bank_sel0__bit20 20
-#define R_SDRAM_CONFIG__bank_sel0__bit21 21
-#define R_SDRAM_CONFIG__bank_sel0__bit22 22
-#define R_SDRAM_CONFIG__bank_sel0__bit23 23
-#define R_SDRAM_CONFIG__bank_sel0__bit24 24
-#define R_SDRAM_CONFIG__bank_sel0__bit25 25
-#define R_SDRAM_CONFIG__bank_sel0__bit26 26
-#define R_SDRAM_CONFIG__bank_sel0__bit27 27
-#define R_SDRAM_CONFIG__bank_sel0__bit28 28
-#define R_SDRAM_CONFIG__bank_sel0__bit29 29
-
-/*
-!* External DMA registers
-!*/
-
-#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010)
-#define R_EXT_DMA_0_CMD__cnt__BITNR 23
-#define R_EXT_DMA_0_CMD__cnt__WIDTH 1
-#define R_EXT_DMA_0_CMD__cnt__enable 1
-#define R_EXT_DMA_0_CMD__cnt__disable 0
-#define R_EXT_DMA_0_CMD__rqpol__BITNR 22
-#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1
-#define R_EXT_DMA_0_CMD__rqpol__ahigh 0
-#define R_EXT_DMA_0_CMD__rqpol__alow 1
-#define R_EXT_DMA_0_CMD__apol__BITNR 21
-#define R_EXT_DMA_0_CMD__apol__WIDTH 1
-#define R_EXT_DMA_0_CMD__apol__ahigh 0
-#define R_EXT_DMA_0_CMD__apol__alow 1
-#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
-#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1
-#define R_EXT_DMA_0_CMD__rq_ack__burst 0
-#define R_EXT_DMA_0_CMD__rq_ack__handsh 1
-#define R_EXT_DMA_0_CMD__wid__BITNR 18
-#define R_EXT_DMA_0_CMD__wid__WIDTH 2
-#define R_EXT_DMA_0_CMD__wid__byte 0
-#define R_EXT_DMA_0_CMD__wid__word 1
-#define R_EXT_DMA_0_CMD__wid__dword 2
-#define R_EXT_DMA_0_CMD__dir__BITNR 17
-#define R_EXT_DMA_0_CMD__dir__WIDTH 1
-#define R_EXT_DMA_0_CMD__dir__input 0
-#define R_EXT_DMA_0_CMD__dir__output 1
-#define R_EXT_DMA_0_CMD__run__BITNR 16
-#define R_EXT_DMA_0_CMD__run__WIDTH 1
-#define R_EXT_DMA_0_CMD__run__start 1
-#define R_EXT_DMA_0_CMD__run__stop 0
-#define R_EXT_DMA_0_CMD__trf_count__BITNR 0
-#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16
-
-#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010)
-#define R_EXT_DMA_0_STAT__run__BITNR 16
-#define R_EXT_DMA_0_STAT__run__WIDTH 1
-#define R_EXT_DMA_0_STAT__run__start 1
-#define R_EXT_DMA_0_STAT__run__stop 0
-#define R_EXT_DMA_0_STAT__trf_count__BITNR 0
-#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16
-
-#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014)
-#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
-#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28
-
-#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018)
-#define R_EXT_DMA_1_CMD__cnt__BITNR 23
-#define R_EXT_DMA_1_CMD__cnt__WIDTH 1
-#define R_EXT_DMA_1_CMD__cnt__enable 1
-#define R_EXT_DMA_1_CMD__cnt__disable 0
-#define R_EXT_DMA_1_CMD__rqpol__BITNR 22
-#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1
-#define R_EXT_DMA_1_CMD__rqpol__ahigh 0
-#define R_EXT_DMA_1_CMD__rqpol__alow 1
-#define R_EXT_DMA_1_CMD__apol__BITNR 21
-#define R_EXT_DMA_1_CMD__apol__WIDTH 1
-#define R_EXT_DMA_1_CMD__apol__ahigh 0
-#define R_EXT_DMA_1_CMD__apol__alow 1
-#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
-#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1
-#define R_EXT_DMA_1_CMD__rq_ack__burst 0
-#define R_EXT_DMA_1_CMD__rq_ack__handsh 1
-#define R_EXT_DMA_1_CMD__wid__BITNR 18
-#define R_EXT_DMA_1_CMD__wid__WIDTH 2
-#define R_EXT_DMA_1_CMD__wid__byte 0
-#define R_EXT_DMA_1_CMD__wid__word 1
-#define R_EXT_DMA_1_CMD__wid__dword 2
-#define R_EXT_DMA_1_CMD__dir__BITNR 17
-#define R_EXT_DMA_1_CMD__dir__WIDTH 1
-#define R_EXT_DMA_1_CMD__dir__input 0
-#define R_EXT_DMA_1_CMD__dir__output 1
-#define R_EXT_DMA_1_CMD__run__BITNR 16
-#define R_EXT_DMA_1_CMD__run__WIDTH 1
-#define R_EXT_DMA_1_CMD__run__start 1
-#define R_EXT_DMA_1_CMD__run__stop 0
-#define R_EXT_DMA_1_CMD__trf_count__BITNR 0
-#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16
-
-#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018)
-#define R_EXT_DMA_1_STAT__run__BITNR 16
-#define R_EXT_DMA_1_STAT__run__WIDTH 1
-#define R_EXT_DMA_1_STAT__run__start 1
-#define R_EXT_DMA_1_STAT__run__stop 0
-#define R_EXT_DMA_1_STAT__trf_count__BITNR 0
-#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16
-
-#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c)
-#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
-#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28
-
-/*
-!* Timer registers
-!*/
-
-#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020)
-#define R_TIMER_CTRL__timerdiv1__BITNR 24
-#define R_TIMER_CTRL__timerdiv1__WIDTH 8
-#define R_TIMER_CTRL__timerdiv0__BITNR 16
-#define R_TIMER_CTRL__timerdiv0__WIDTH 8
-#define R_TIMER_CTRL__presc_timer1__BITNR 15
-#define R_TIMER_CTRL__presc_timer1__WIDTH 1
-#define R_TIMER_CTRL__presc_timer1__normal 0
-#define R_TIMER_CTRL__presc_timer1__prescale 1
-#define R_TIMER_CTRL__i1__BITNR 14
-#define R_TIMER_CTRL__i1__WIDTH 1
-#define R_TIMER_CTRL__i1__clr 1
-#define R_TIMER_CTRL__i1__nop 0
-#define R_TIMER_CTRL__tm1__BITNR 12
-#define R_TIMER_CTRL__tm1__WIDTH 2
-#define R_TIMER_CTRL__tm1__stop_ld 0
-#define R_TIMER_CTRL__tm1__freeze 1
-#define R_TIMER_CTRL__tm1__run 2
-#define R_TIMER_CTRL__tm1__reserved 3
-#define R_TIMER_CTRL__clksel1__BITNR 8
-#define R_TIMER_CTRL__clksel1__WIDTH 4
-#define R_TIMER_CTRL__clksel1__c300Hz 0
-#define R_TIMER_CTRL__clksel1__c600Hz 1
-#define R_TIMER_CTRL__clksel1__c1200Hz 2
-#define R_TIMER_CTRL__clksel1__c2400Hz 3
-#define R_TIMER_CTRL__clksel1__c4800Hz 4
-#define R_TIMER_CTRL__clksel1__c9600Hz 5
-#define R_TIMER_CTRL__clksel1__c19k2Hz 6
-#define R_TIMER_CTRL__clksel1__c38k4Hz 7
-#define R_TIMER_CTRL__clksel1__c57k6Hz 8
-#define R_TIMER_CTRL__clksel1__c115k2Hz 9
-#define R_TIMER_CTRL__clksel1__c230k4Hz 10
-#define R_TIMER_CTRL__clksel1__c460k8Hz 11
-#define R_TIMER_CTRL__clksel1__c921k6Hz 12
-#define R_TIMER_CTRL__clksel1__c1843k2Hz 13
-#define R_TIMER_CTRL__clksel1__c6250kHz 14
-#define R_TIMER_CTRL__clksel1__cascade0 15
-#define R_TIMER_CTRL__presc_ext__BITNR 7
-#define R_TIMER_CTRL__presc_ext__WIDTH 1
-#define R_TIMER_CTRL__presc_ext__prescale 0
-#define R_TIMER_CTRL__presc_ext__external 1
-#define R_TIMER_CTRL__i0__BITNR 6
-#define R_TIMER_CTRL__i0__WIDTH 1
-#define R_TIMER_CTRL__i0__clr 1
-#define R_TIMER_CTRL__i0__nop 0
-#define R_TIMER_CTRL__tm0__BITNR 4
-#define R_TIMER_CTRL__tm0__WIDTH 2
-#define R_TIMER_CTRL__tm0__stop_ld 0
-#define R_TIMER_CTRL__tm0__freeze 1
-#define R_TIMER_CTRL__tm0__run 2
-#define R_TIMER_CTRL__tm0__reserved 3
-#define R_TIMER_CTRL__clksel0__BITNR 0
-#define R_TIMER_CTRL__clksel0__WIDTH 4
-#define R_TIMER_CTRL__clksel0__c300Hz 0
-#define R_TIMER_CTRL__clksel0__c600Hz 1
-#define R_TIMER_CTRL__clksel0__c1200Hz 2
-#define R_TIMER_CTRL__clksel0__c2400Hz 3
-#define R_TIMER_CTRL__clksel0__c4800Hz 4
-#define R_TIMER_CTRL__clksel0__c9600Hz 5
-#define R_TIMER_CTRL__clksel0__c19k2Hz 6
-#define R_TIMER_CTRL__clksel0__c38k4Hz 7
-#define R_TIMER_CTRL__clksel0__c57k6Hz 8
-#define R_TIMER_CTRL__clksel0__c115k2Hz 9
-#define R_TIMER_CTRL__clksel0__c230k4Hz 10
-#define R_TIMER_CTRL__clksel0__c460k8Hz 11
-#define R_TIMER_CTRL__clksel0__c921k6Hz 12
-#define R_TIMER_CTRL__clksel0__c1843k2Hz 13
-#define R_TIMER_CTRL__clksel0__c6250kHz 14
-#define R_TIMER_CTRL__clksel0__flexible 15
-
-#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020)
-#define R_TIMER_DATA__timer1__BITNR 24
-#define R_TIMER_DATA__timer1__WIDTH 8
-#define R_TIMER_DATA__timer0__BITNR 16
-#define R_TIMER_DATA__timer0__WIDTH 8
-#define R_TIMER_DATA__clkdiv_high__BITNR 8
-#define R_TIMER_DATA__clkdiv_high__WIDTH 8
-#define R_TIMER_DATA__clkdiv_low__BITNR 0
-#define R_TIMER_DATA__clkdiv_low__WIDTH 8
-
-#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022)
-#define R_TIMER01_DATA__count__BITNR 0
-#define R_TIMER01_DATA__count__WIDTH 16
-
-#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022)
-#define R_TIMER0_DATA__count__BITNR 0
-#define R_TIMER0_DATA__count__WIDTH 8
-
-#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023)
-#define R_TIMER1_DATA__count__BITNR 0
-#define R_TIMER1_DATA__count__WIDTH 8
-
-#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024)
-#define R_WATCHDOG__key__BITNR 1
-#define R_WATCHDOG__key__WIDTH 3
-#define R_WATCHDOG__enable__BITNR 0
-#define R_WATCHDOG__enable__WIDTH 1
-#define R_WATCHDOG__enable__stop 0
-#define R_WATCHDOG__enable__start 1
-
-#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0)
-#define R_CLOCK_PRESCALE__ser_presc__BITNR 16
-#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16
-#define R_CLOCK_PRESCALE__tim_presc__BITNR 0
-#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16
-
-#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2)
-#define R_SERIAL_PRESCALE__ser_presc__BITNR 0
-#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16
-
-#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0)
-#define R_TIMER_PRESCALE__tim_presc__BITNR 0
-#define R_TIMER_PRESCALE__tim_presc__WIDTH 16
-
-#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0)
-#define R_PRESCALE_STATUS__ser_status__BITNR 16
-#define R_PRESCALE_STATUS__ser_status__WIDTH 16
-#define R_PRESCALE_STATUS__tim_status__BITNR 0
-#define R_PRESCALE_STATUS__tim_status__WIDTH 16
-
-#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2)
-#define R_SER_PRESC_STATUS__ser_status__BITNR 0
-#define R_SER_PRESC_STATUS__ser_status__WIDTH 16
-
-#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0)
-#define R_TIM_PRESC_STATUS__tim_status__BITNR 0
-#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16
-
-#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4)
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0
-#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0
-#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1
-#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
-#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6
-#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0
-#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1
-#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
-#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4
-#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
-#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10
-
-/*
-!* Shared RAM interface registers
-!*/
-
-#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_SHARED_RAM_CONFIG__width__BITNR 3
-#define R_SHARED_RAM_CONFIG__width__WIDTH 1
-#define R_SHARED_RAM_CONFIG__width__byte 0
-#define R_SHARED_RAM_CONFIG__width__word 1
-#define R_SHARED_RAM_CONFIG__enable__BITNR 2
-#define R_SHARED_RAM_CONFIG__enable__WIDTH 1
-#define R_SHARED_RAM_CONFIG__enable__yes 1
-#define R_SHARED_RAM_CONFIG__enable__no 0
-#define R_SHARED_RAM_CONFIG__pint__BITNR 1
-#define R_SHARED_RAM_CONFIG__pint__WIDTH 1
-#define R_SHARED_RAM_CONFIG__pint__int 1
-#define R_SHARED_RAM_CONFIG__pint__nop 0
-#define R_SHARED_RAM_CONFIG__clri__BITNR 0
-#define R_SHARED_RAM_CONFIG__clri__WIDTH 1
-#define R_SHARED_RAM_CONFIG__clri__clr 1
-#define R_SHARED_RAM_CONFIG__clri__nop 0
-
-#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_SHARED_RAM_ADDR__base_addr__BITNR 8
-#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22
-
-/*
-!* General config registers
-!*/
-
-#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c)
-#define R_GEN_CONFIG__par_w__BITNR 31
-#define R_GEN_CONFIG__par_w__WIDTH 1
-#define R_GEN_CONFIG__par_w__select 1
-#define R_GEN_CONFIG__par_w__disable 0
-#define R_GEN_CONFIG__usb2__BITNR 30
-#define R_GEN_CONFIG__usb2__WIDTH 1
-#define R_GEN_CONFIG__usb2__select 1
-#define R_GEN_CONFIG__usb2__disable 0
-#define R_GEN_CONFIG__usb1__BITNR 29
-#define R_GEN_CONFIG__usb1__WIDTH 1
-#define R_GEN_CONFIG__usb1__select 1
-#define R_GEN_CONFIG__usb1__disable 0
-#define R_GEN_CONFIG__g24dir__BITNR 27
-#define R_GEN_CONFIG__g24dir__WIDTH 1
-#define R_GEN_CONFIG__g24dir__in 0
-#define R_GEN_CONFIG__g24dir__out 1
-#define R_GEN_CONFIG__g16_23dir__BITNR 26
-#define R_GEN_CONFIG__g16_23dir__WIDTH 1
-#define R_GEN_CONFIG__g16_23dir__in 0
-#define R_GEN_CONFIG__g16_23dir__out 1
-#define R_GEN_CONFIG__g8_15dir__BITNR 25
-#define R_GEN_CONFIG__g8_15dir__WIDTH 1
-#define R_GEN_CONFIG__g8_15dir__in 0
-#define R_GEN_CONFIG__g8_15dir__out 1
-#define R_GEN_CONFIG__g0dir__BITNR 24
-#define R_GEN_CONFIG__g0dir__WIDTH 1
-#define R_GEN_CONFIG__g0dir__in 0
-#define R_GEN_CONFIG__g0dir__out 1
-#define R_GEN_CONFIG__dma9__BITNR 23
-#define R_GEN_CONFIG__dma9__WIDTH 1
-#define R_GEN_CONFIG__dma9__usb 0
-#define R_GEN_CONFIG__dma9__serial1 1
-#define R_GEN_CONFIG__dma8__BITNR 22
-#define R_GEN_CONFIG__dma8__WIDTH 1
-#define R_GEN_CONFIG__dma8__usb 0
-#define R_GEN_CONFIG__dma8__serial1 1
-#define R_GEN_CONFIG__dma7__BITNR 20
-#define R_GEN_CONFIG__dma7__WIDTH 2
-#define R_GEN_CONFIG__dma7__unused 0
-#define R_GEN_CONFIG__dma7__serial0 1
-#define R_GEN_CONFIG__dma7__extdma1 2
-#define R_GEN_CONFIG__dma7__intdma6 3
-#define R_GEN_CONFIG__dma6__BITNR 18
-#define R_GEN_CONFIG__dma6__WIDTH 2
-#define R_GEN_CONFIG__dma6__unused 0
-#define R_GEN_CONFIG__dma6__serial0 1
-#define R_GEN_CONFIG__dma6__extdma1 2
-#define R_GEN_CONFIG__dma6__intdma7 3
-#define R_GEN_CONFIG__dma5__BITNR 16
-#define R_GEN_CONFIG__dma5__WIDTH 2
-#define R_GEN_CONFIG__dma5__par1 0
-#define R_GEN_CONFIG__dma5__scsi1 1
-#define R_GEN_CONFIG__dma5__serial3 2
-#define R_GEN_CONFIG__dma5__extdma0 3
-#define R_GEN_CONFIG__dma4__BITNR 14
-#define R_GEN_CONFIG__dma4__WIDTH 2
-#define R_GEN_CONFIG__dma4__par1 0
-#define R_GEN_CONFIG__dma4__scsi1 1
-#define R_GEN_CONFIG__dma4__serial3 2
-#define R_GEN_CONFIG__dma4__extdma0 3
-#define R_GEN_CONFIG__dma3__BITNR 12
-#define R_GEN_CONFIG__dma3__WIDTH 2
-#define R_GEN_CONFIG__dma3__par0 0
-#define R_GEN_CONFIG__dma3__scsi0 1
-#define R_GEN_CONFIG__dma3__serial2 2
-#define R_GEN_CONFIG__dma3__ata 3
-#define R_GEN_CONFIG__dma2__BITNR 10
-#define R_GEN_CONFIG__dma2__WIDTH 2
-#define R_GEN_CONFIG__dma2__par0 0
-#define R_GEN_CONFIG__dma2__scsi0 1
-#define R_GEN_CONFIG__dma2__serial2 2
-#define R_GEN_CONFIG__dma2__ata 3
-#define R_GEN_CONFIG__mio_w__BITNR 9
-#define R_GEN_CONFIG__mio_w__WIDTH 1
-#define R_GEN_CONFIG__mio_w__select 1
-#define R_GEN_CONFIG__mio_w__disable 0
-#define R_GEN_CONFIG__ser3__BITNR 8
-#define R_GEN_CONFIG__ser3__WIDTH 1
-#define R_GEN_CONFIG__ser3__select 1
-#define R_GEN_CONFIG__ser3__disable 0
-#define R_GEN_CONFIG__par1__BITNR 7
-#define R_GEN_CONFIG__par1__WIDTH 1
-#define R_GEN_CONFIG__par1__select 1
-#define R_GEN_CONFIG__par1__disable 0
-#define R_GEN_CONFIG__scsi0w__BITNR 6
-#define R_GEN_CONFIG__scsi0w__WIDTH 1
-#define R_GEN_CONFIG__scsi0w__select 1
-#define R_GEN_CONFIG__scsi0w__disable 0
-#define R_GEN_CONFIG__scsi1__BITNR 5
-#define R_GEN_CONFIG__scsi1__WIDTH 1
-#define R_GEN_CONFIG__scsi1__select 1
-#define R_GEN_CONFIG__scsi1__disable 0
-#define R_GEN_CONFIG__mio__BITNR 4
-#define R_GEN_CONFIG__mio__WIDTH 1
-#define R_GEN_CONFIG__mio__select 1
-#define R_GEN_CONFIG__mio__disable 0
-#define R_GEN_CONFIG__ser2__BITNR 3
-#define R_GEN_CONFIG__ser2__WIDTH 1
-#define R_GEN_CONFIG__ser2__select 1
-#define R_GEN_CONFIG__ser2__disable 0
-#define R_GEN_CONFIG__par0__BITNR 2
-#define R_GEN_CONFIG__par0__WIDTH 1
-#define R_GEN_CONFIG__par0__select 1
-#define R_GEN_CONFIG__par0__disable 0
-#define R_GEN_CONFIG__ata__BITNR 1
-#define R_GEN_CONFIG__ata__WIDTH 1
-#define R_GEN_CONFIG__ata__select 1
-#define R_GEN_CONFIG__ata__disable 0
-#define R_GEN_CONFIG__scsi0__BITNR 0
-#define R_GEN_CONFIG__scsi0__WIDTH 1
-#define R_GEN_CONFIG__scsi0__select 1
-#define R_GEN_CONFIG__scsi0__disable 0
-
-#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034)
-#define R_GEN_CONFIG_II__sermode3__BITNR 6
-#define R_GEN_CONFIG_II__sermode3__WIDTH 1
-#define R_GEN_CONFIG_II__sermode3__async 0
-#define R_GEN_CONFIG_II__sermode3__sync 1
-#define R_GEN_CONFIG_II__sermode1__BITNR 4
-#define R_GEN_CONFIG_II__sermode1__WIDTH 1
-#define R_GEN_CONFIG_II__sermode1__async 0
-#define R_GEN_CONFIG_II__sermode1__sync 1
-#define R_GEN_CONFIG_II__ext_clk__BITNR 2
-#define R_GEN_CONFIG_II__ext_clk__WIDTH 1
-#define R_GEN_CONFIG_II__ext_clk__select 1
-#define R_GEN_CONFIG_II__ext_clk__disable 0
-#define R_GEN_CONFIG_II__ser2__BITNR 1
-#define R_GEN_CONFIG_II__ser2__WIDTH 1
-#define R_GEN_CONFIG_II__ser2__select 1
-#define R_GEN_CONFIG_II__ser2__disable 0
-#define R_GEN_CONFIG_II__ser3__BITNR 0
-#define R_GEN_CONFIG_II__ser3__WIDTH 1
-#define R_GEN_CONFIG_II__ser3__select 1
-#define R_GEN_CONFIG_II__ser3__disable 0
-
-#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028)
-#define R_PORT_G_DATA__data__BITNR 0
-#define R_PORT_G_DATA__data__WIDTH 32
-
-/*
-!* General port configuration registers
-!*/
-
-#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030)
-#define R_PORT_PA_SET__dir7__BITNR 15
-#define R_PORT_PA_SET__dir7__WIDTH 1
-#define R_PORT_PA_SET__dir7__input 0
-#define R_PORT_PA_SET__dir7__output 1
-#define R_PORT_PA_SET__dir6__BITNR 14
-#define R_PORT_PA_SET__dir6__WIDTH 1
-#define R_PORT_PA_SET__dir6__input 0
-#define R_PORT_PA_SET__dir6__output 1
-#define R_PORT_PA_SET__dir5__BITNR 13
-#define R_PORT_PA_SET__dir5__WIDTH 1
-#define R_PORT_PA_SET__dir5__input 0
-#define R_PORT_PA_SET__dir5__output 1
-#define R_PORT_PA_SET__dir4__BITNR 12
-#define R_PORT_PA_SET__dir4__WIDTH 1
-#define R_PORT_PA_SET__dir4__input 0
-#define R_PORT_PA_SET__dir4__output 1
-#define R_PORT_PA_SET__dir3__BITNR 11
-#define R_PORT_PA_SET__dir3__WIDTH 1
-#define R_PORT_PA_SET__dir3__input 0
-#define R_PORT_PA_SET__dir3__output 1
-#define R_PORT_PA_SET__dir2__BITNR 10
-#define R_PORT_PA_SET__dir2__WIDTH 1
-#define R_PORT_PA_SET__dir2__input 0
-#define R_PORT_PA_SET__dir2__output 1
-#define R_PORT_PA_SET__dir1__BITNR 9
-#define R_PORT_PA_SET__dir1__WIDTH 1
-#define R_PORT_PA_SET__dir1__input 0
-#define R_PORT_PA_SET__dir1__output 1
-#define R_PORT_PA_SET__dir0__BITNR 8
-#define R_PORT_PA_SET__dir0__WIDTH 1
-#define R_PORT_PA_SET__dir0__input 0
-#define R_PORT_PA_SET__dir0__output 1
-#define R_PORT_PA_SET__data_out__BITNR 0
-#define R_PORT_PA_SET__data_out__WIDTH 8
-
-#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030)
-#define R_PORT_PA_DATA__data_out__BITNR 0
-#define R_PORT_PA_DATA__data_out__WIDTH 8
-
-#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031)
-#define R_PORT_PA_DIR__dir7__BITNR 7
-#define R_PORT_PA_DIR__dir7__WIDTH 1
-#define R_PORT_PA_DIR__dir7__input 0
-#define R_PORT_PA_DIR__dir7__output 1
-#define R_PORT_PA_DIR__dir6__BITNR 6
-#define R_PORT_PA_DIR__dir6__WIDTH 1
-#define R_PORT_PA_DIR__dir6__input 0
-#define R_PORT_PA_DIR__dir6__output 1
-#define R_PORT_PA_DIR__dir5__BITNR 5
-#define R_PORT_PA_DIR__dir5__WIDTH 1
-#define R_PORT_PA_DIR__dir5__input 0
-#define R_PORT_PA_DIR__dir5__output 1
-#define R_PORT_PA_DIR__dir4__BITNR 4
-#define R_PORT_PA_DIR__dir4__WIDTH 1
-#define R_PORT_PA_DIR__dir4__input 0
-#define R_PORT_PA_DIR__dir4__output 1
-#define R_PORT_PA_DIR__dir3__BITNR 3
-#define R_PORT_PA_DIR__dir3__WIDTH 1
-#define R_PORT_PA_DIR__dir3__input 0
-#define R_PORT_PA_DIR__dir3__output 1
-#define R_PORT_PA_DIR__dir2__BITNR 2
-#define R_PORT_PA_DIR__dir2__WIDTH 1
-#define R_PORT_PA_DIR__dir2__input 0
-#define R_PORT_PA_DIR__dir2__output 1
-#define R_PORT_PA_DIR__dir1__BITNR 1
-#define R_PORT_PA_DIR__dir1__WIDTH 1
-#define R_PORT_PA_DIR__dir1__input 0
-#define R_PORT_PA_DIR__dir1__output 1
-#define R_PORT_PA_DIR__dir0__BITNR 0
-#define R_PORT_PA_DIR__dir0__WIDTH 1
-#define R_PORT_PA_DIR__dir0__input 0
-#define R_PORT_PA_DIR__dir0__output 1
-
-#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030)
-#define R_PORT_PA_READ__data_in__BITNR 0
-#define R_PORT_PA_READ__data_in__WIDTH 8
-
-#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038)
-#define R_PORT_PB_SET__syncser3__BITNR 29
-#define R_PORT_PB_SET__syncser3__WIDTH 1
-#define R_PORT_PB_SET__syncser3__port_cs 0
-#define R_PORT_PB_SET__syncser3__ss3extra 1
-#define R_PORT_PB_SET__syncser1__BITNR 28
-#define R_PORT_PB_SET__syncser1__WIDTH 1
-#define R_PORT_PB_SET__syncser1__port_cs 0
-#define R_PORT_PB_SET__syncser1__ss1extra 1
-#define R_PORT_PB_SET__i2c_en__BITNR 27
-#define R_PORT_PB_SET__i2c_en__WIDTH 1
-#define R_PORT_PB_SET__i2c_en__off 0
-#define R_PORT_PB_SET__i2c_en__on 1
-#define R_PORT_PB_SET__i2c_d__BITNR 26
-#define R_PORT_PB_SET__i2c_d__WIDTH 1
-#define R_PORT_PB_SET__i2c_clk__BITNR 25
-#define R_PORT_PB_SET__i2c_clk__WIDTH 1
-#define R_PORT_PB_SET__i2c_oe___BITNR 24
-#define R_PORT_PB_SET__i2c_oe___WIDTH 1
-#define R_PORT_PB_SET__i2c_oe___enable 0
-#define R_PORT_PB_SET__i2c_oe___disable 1
-#define R_PORT_PB_SET__cs7__BITNR 23
-#define R_PORT_PB_SET__cs7__WIDTH 1
-#define R_PORT_PB_SET__cs7__port 0
-#define R_PORT_PB_SET__cs7__cs 1
-#define R_PORT_PB_SET__cs6__BITNR 22
-#define R_PORT_PB_SET__cs6__WIDTH 1
-#define R_PORT_PB_SET__cs6__port 0
-#define R_PORT_PB_SET__cs6__cs 1
-#define R_PORT_PB_SET__cs5__BITNR 21
-#define R_PORT_PB_SET__cs5__WIDTH 1
-#define R_PORT_PB_SET__cs5__port 0
-#define R_PORT_PB_SET__cs5__cs 1
-#define R_PORT_PB_SET__cs4__BITNR 20
-#define R_PORT_PB_SET__cs4__WIDTH 1
-#define R_PORT_PB_SET__cs4__port 0
-#define R_PORT_PB_SET__cs4__cs 1
-#define R_PORT_PB_SET__cs3__BITNR 19
-#define R_PORT_PB_SET__cs3__WIDTH 1
-#define R_PORT_PB_SET__cs3__port 0
-#define R_PORT_PB_SET__cs3__cs 1
-#define R_PORT_PB_SET__cs2__BITNR 18
-#define R_PORT_PB_SET__cs2__WIDTH 1
-#define R_PORT_PB_SET__cs2__port 0
-#define R_PORT_PB_SET__cs2__cs 1
-#define R_PORT_PB_SET__scsi1__BITNR 17
-#define R_PORT_PB_SET__scsi1__WIDTH 1
-#define R_PORT_PB_SET__scsi1__port_cs 0
-#define R_PORT_PB_SET__scsi1__enph 1
-#define R_PORT_PB_SET__scsi0__BITNR 16
-#define R_PORT_PB_SET__scsi0__WIDTH 1
-#define R_PORT_PB_SET__scsi0__port_cs 0
-#define R_PORT_PB_SET__scsi0__enph 1
-#define R_PORT_PB_SET__dir7__BITNR 15
-#define R_PORT_PB_SET__dir7__WIDTH 1
-#define R_PORT_PB_SET__dir7__input 0
-#define R_PORT_PB_SET__dir7__output 1
-#define R_PORT_PB_SET__dir6__BITNR 14
-#define R_PORT_PB_SET__dir6__WIDTH 1
-#define R_PORT_PB_SET__dir6__input 0
-#define R_PORT_PB_SET__dir6__output 1
-#define R_PORT_PB_SET__dir5__BITNR 13
-#define R_PORT_PB_SET__dir5__WIDTH 1
-#define R_PORT_PB_SET__dir5__input 0
-#define R_PORT_PB_SET__dir5__output 1
-#define R_PORT_PB_SET__dir4__BITNR 12
-#define R_PORT_PB_SET__dir4__WIDTH 1
-#define R_PORT_PB_SET__dir4__input 0
-#define R_PORT_PB_SET__dir4__output 1
-#define R_PORT_PB_SET__dir3__BITNR 11
-#define R_PORT_PB_SET__dir3__WIDTH 1
-#define R_PORT_PB_SET__dir3__input 0
-#define R_PORT_PB_SET__dir3__output 1
-#define R_PORT_PB_SET__dir2__BITNR 10
-#define R_PORT_PB_SET__dir2__WIDTH 1
-#define R_PORT_PB_SET__dir2__input 0
-#define R_PORT_PB_SET__dir2__output 1
-#define R_PORT_PB_SET__dir1__BITNR 9
-#define R_PORT_PB_SET__dir1__WIDTH 1
-#define R_PORT_PB_SET__dir1__input 0
-#define R_PORT_PB_SET__dir1__output 1
-#define R_PORT_PB_SET__dir0__BITNR 8
-#define R_PORT_PB_SET__dir0__WIDTH 1
-#define R_PORT_PB_SET__dir0__input 0
-#define R_PORT_PB_SET__dir0__output 1
-#define R_PORT_PB_SET__data_out__BITNR 0
-#define R_PORT_PB_SET__data_out__WIDTH 8
-
-#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038)
-#define R_PORT_PB_DATA__data_out__BITNR 0
-#define R_PORT_PB_DATA__data_out__WIDTH 8
-
-#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039)
-#define R_PORT_PB_DIR__dir7__BITNR 7
-#define R_PORT_PB_DIR__dir7__WIDTH 1
-#define R_PORT_PB_DIR__dir7__input 0
-#define R_PORT_PB_DIR__dir7__output 1
-#define R_PORT_PB_DIR__dir6__BITNR 6
-#define R_PORT_PB_DIR__dir6__WIDTH 1
-#define R_PORT_PB_DIR__dir6__input 0
-#define R_PORT_PB_DIR__dir6__output 1
-#define R_PORT_PB_DIR__dir5__BITNR 5
-#define R_PORT_PB_DIR__dir5__WIDTH 1
-#define R_PORT_PB_DIR__dir5__input 0
-#define R_PORT_PB_DIR__dir5__output 1
-#define R_PORT_PB_DIR__dir4__BITNR 4
-#define R_PORT_PB_DIR__dir4__WIDTH 1
-#define R_PORT_PB_DIR__dir4__input 0
-#define R_PORT_PB_DIR__dir4__output 1
-#define R_PORT_PB_DIR__dir3__BITNR 3
-#define R_PORT_PB_DIR__dir3__WIDTH 1
-#define R_PORT_PB_DIR__dir3__input 0
-#define R_PORT_PB_DIR__dir3__output 1
-#define R_PORT_PB_DIR__dir2__BITNR 2
-#define R_PORT_PB_DIR__dir2__WIDTH 1
-#define R_PORT_PB_DIR__dir2__input 0
-#define R_PORT_PB_DIR__dir2__output 1
-#define R_PORT_PB_DIR__dir1__BITNR 1
-#define R_PORT_PB_DIR__dir1__WIDTH 1
-#define R_PORT_PB_DIR__dir1__input 0
-#define R_PORT_PB_DIR__dir1__output 1
-#define R_PORT_PB_DIR__dir0__BITNR 0
-#define R_PORT_PB_DIR__dir0__WIDTH 1
-#define R_PORT_PB_DIR__dir0__input 0
-#define R_PORT_PB_DIR__dir0__output 1
-
-#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a)
-#define R_PORT_PB_CONFIG__cs7__BITNR 7
-#define R_PORT_PB_CONFIG__cs7__WIDTH 1
-#define R_PORT_PB_CONFIG__cs7__port 0
-#define R_PORT_PB_CONFIG__cs7__cs 1
-#define R_PORT_PB_CONFIG__cs6__BITNR 6
-#define R_PORT_PB_CONFIG__cs6__WIDTH 1
-#define R_PORT_PB_CONFIG__cs6__port 0
-#define R_PORT_PB_CONFIG__cs6__cs 1
-#define R_PORT_PB_CONFIG__cs5__BITNR 5
-#define R_PORT_PB_CONFIG__cs5__WIDTH 1
-#define R_PORT_PB_CONFIG__cs5__port 0
-#define R_PORT_PB_CONFIG__cs5__cs 1
-#define R_PORT_PB_CONFIG__cs4__BITNR 4
-#define R_PORT_PB_CONFIG__cs4__WIDTH 1
-#define R_PORT_PB_CONFIG__cs4__port 0
-#define R_PORT_PB_CONFIG__cs4__cs 1
-#define R_PORT_PB_CONFIG__cs3__BITNR 3
-#define R_PORT_PB_CONFIG__cs3__WIDTH 1
-#define R_PORT_PB_CONFIG__cs3__port 0
-#define R_PORT_PB_CONFIG__cs3__cs 1
-#define R_PORT_PB_CONFIG__cs2__BITNR 2
-#define R_PORT_PB_CONFIG__cs2__WIDTH 1
-#define R_PORT_PB_CONFIG__cs2__port 0
-#define R_PORT_PB_CONFIG__cs2__cs 1
-#define R_PORT_PB_CONFIG__scsi1__BITNR 1
-#define R_PORT_PB_CONFIG__scsi1__WIDTH 1
-#define R_PORT_PB_CONFIG__scsi1__port_cs 0
-#define R_PORT_PB_CONFIG__scsi1__enph 1
-#define R_PORT_PB_CONFIG__scsi0__BITNR 0
-#define R_PORT_PB_CONFIG__scsi0__WIDTH 1
-#define R_PORT_PB_CONFIG__scsi0__port_cs 0
-#define R_PORT_PB_CONFIG__scsi0__enph 1
-
-#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b)
-#define R_PORT_PB_I2C__syncser3__BITNR 5
-#define R_PORT_PB_I2C__syncser3__WIDTH 1
-#define R_PORT_PB_I2C__syncser3__port_cs 0
-#define R_PORT_PB_I2C__syncser3__ss3extra 1
-#define R_PORT_PB_I2C__syncser1__BITNR 4
-#define R_PORT_PB_I2C__syncser1__WIDTH 1
-#define R_PORT_PB_I2C__syncser1__port_cs 0
-#define R_PORT_PB_I2C__syncser1__ss1extra 1
-#define R_PORT_PB_I2C__i2c_en__BITNR 3
-#define R_PORT_PB_I2C__i2c_en__WIDTH 1
-#define R_PORT_PB_I2C__i2c_en__off 0
-#define R_PORT_PB_I2C__i2c_en__on 1
-#define R_PORT_PB_I2C__i2c_d__BITNR 2
-#define R_PORT_PB_I2C__i2c_d__WIDTH 1
-#define R_PORT_PB_I2C__i2c_clk__BITNR 1
-#define R_PORT_PB_I2C__i2c_clk__WIDTH 1
-#define R_PORT_PB_I2C__i2c_oe___BITNR 0
-#define R_PORT_PB_I2C__i2c_oe___WIDTH 1
-#define R_PORT_PB_I2C__i2c_oe___enable 0
-#define R_PORT_PB_I2C__i2c_oe___disable 1
-
-#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038)
-#define R_PORT_PB_READ__data_in__BITNR 0
-#define R_PORT_PB_READ__data_in__WIDTH 8
-
-/*
-!* Serial port registers
-!*/
-
-#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060)
-#define R_SERIAL0_CTRL__tr_baud__BITNR 28
-#define R_SERIAL0_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL0_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL0_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL0_CTRL__tr_baud__reserved 15
-#define R_SERIAL0_CTRL__rec_baud__BITNR 24
-#define R_SERIAL0_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL0_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL0_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL0_CTRL__rec_baud__reserved 15
-#define R_SERIAL0_CTRL__dma_err__BITNR 23
-#define R_SERIAL0_CTRL__dma_err__WIDTH 1
-#define R_SERIAL0_CTRL__dma_err__stop 0
-#define R_SERIAL0_CTRL__dma_err__ignore 1
-#define R_SERIAL0_CTRL__rec_enable__BITNR 22
-#define R_SERIAL0_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL0_CTRL__rec_enable__disable 0
-#define R_SERIAL0_CTRL__rec_enable__enable 1
-#define R_SERIAL0_CTRL__rts___BITNR 21
-#define R_SERIAL0_CTRL__rts___WIDTH 1
-#define R_SERIAL0_CTRL__rts___active 0
-#define R_SERIAL0_CTRL__rts___inactive 1
-#define R_SERIAL0_CTRL__sampling__BITNR 20
-#define R_SERIAL0_CTRL__sampling__WIDTH 1
-#define R_SERIAL0_CTRL__sampling__middle 0
-#define R_SERIAL0_CTRL__sampling__majority 1
-#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL0_CTRL__rec_stick_par__normal 0
-#define R_SERIAL0_CTRL__rec_stick_par__stick 1
-#define R_SERIAL0_CTRL__rec_par__BITNR 18
-#define R_SERIAL0_CTRL__rec_par__WIDTH 1
-#define R_SERIAL0_CTRL__rec_par__even 0
-#define R_SERIAL0_CTRL__rec_par__odd 1
-#define R_SERIAL0_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL0_CTRL__rec_par_en__disable 0
-#define R_SERIAL0_CTRL__rec_par_en__enable 1
-#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL0_CTRL__txd__BITNR 15
-#define R_SERIAL0_CTRL__txd__WIDTH 1
-#define R_SERIAL0_CTRL__tr_enable__BITNR 14
-#define R_SERIAL0_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL0_CTRL__tr_enable__disable 0
-#define R_SERIAL0_CTRL__tr_enable__enable 1
-#define R_SERIAL0_CTRL__auto_cts__BITNR 13
-#define R_SERIAL0_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL0_CTRL__auto_cts__disabled 0
-#define R_SERIAL0_CTRL__auto_cts__active 1
-#define R_SERIAL0_CTRL__stop_bits__BITNR 12
-#define R_SERIAL0_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL0_CTRL__stop_bits__one_bit 0
-#define R_SERIAL0_CTRL__stop_bits__two_bits 1
-#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL0_CTRL__tr_stick_par__normal 0
-#define R_SERIAL0_CTRL__tr_stick_par__stick 1
-#define R_SERIAL0_CTRL__tr_par__BITNR 10
-#define R_SERIAL0_CTRL__tr_par__WIDTH 1
-#define R_SERIAL0_CTRL__tr_par__even 0
-#define R_SERIAL0_CTRL__tr_par__odd 1
-#define R_SERIAL0_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL0_CTRL__tr_par_en__disable 0
-#define R_SERIAL0_CTRL__tr_par_en__enable 1
-#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL0_CTRL__data_out__BITNR 0
-#define R_SERIAL0_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063)
-#define R_SERIAL0_BAUD__tr_baud__BITNR 4
-#define R_SERIAL0_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL0_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL0_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL0_BAUD__tr_baud__reserved 15
-#define R_SERIAL0_BAUD__rec_baud__BITNR 0
-#define R_SERIAL0_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL0_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL0_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL0_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062)
-#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL0_REC_CTRL__dma_err__stop 0
-#define R_SERIAL0_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL0_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL0_REC_CTRL__rts___BITNR 5
-#define R_SERIAL0_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL0_REC_CTRL__rts___active 0
-#define R_SERIAL0_REC_CTRL__rts___inactive 1
-#define R_SERIAL0_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL0_REC_CTRL__sampling__middle 0
-#define R_SERIAL0_REC_CTRL__sampling__majority 1
-#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_par__even 0
-#define R_SERIAL0_REC_CTRL__rec_par__odd 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061)
-#define R_SERIAL0_TR_CTRL__txd__BITNR 7
-#define R_SERIAL0_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL0_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL0_TR_CTRL__auto_cts__active 1
-#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_par__even 0
-#define R_SERIAL0_TR_CTRL__tr_par__odd 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060)
-#define R_SERIAL0_TR_DATA__data_out__BITNR 0
-#define R_SERIAL0_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060)
-#define R_SERIAL0_READ__xoff_detect__BITNR 15
-#define R_SERIAL0_READ__xoff_detect__WIDTH 1
-#define R_SERIAL0_READ__xoff_detect__no_xoff 0
-#define R_SERIAL0_READ__xoff_detect__xoff 1
-#define R_SERIAL0_READ__cts___BITNR 14
-#define R_SERIAL0_READ__cts___WIDTH 1
-#define R_SERIAL0_READ__cts___active 0
-#define R_SERIAL0_READ__cts___inactive 1
-#define R_SERIAL0_READ__tr_ready__BITNR 13
-#define R_SERIAL0_READ__tr_ready__WIDTH 1
-#define R_SERIAL0_READ__tr_ready__full 0
-#define R_SERIAL0_READ__tr_ready__ready 1
-#define R_SERIAL0_READ__rxd__BITNR 12
-#define R_SERIAL0_READ__rxd__WIDTH 1
-#define R_SERIAL0_READ__overrun__BITNR 11
-#define R_SERIAL0_READ__overrun__WIDTH 1
-#define R_SERIAL0_READ__overrun__no 0
-#define R_SERIAL0_READ__overrun__yes 1
-#define R_SERIAL0_READ__par_err__BITNR 10
-#define R_SERIAL0_READ__par_err__WIDTH 1
-#define R_SERIAL0_READ__par_err__no 0
-#define R_SERIAL0_READ__par_err__yes 1
-#define R_SERIAL0_READ__framing_err__BITNR 9
-#define R_SERIAL0_READ__framing_err__WIDTH 1
-#define R_SERIAL0_READ__framing_err__no 0
-#define R_SERIAL0_READ__framing_err__yes 1
-#define R_SERIAL0_READ__data_avail__BITNR 8
-#define R_SERIAL0_READ__data_avail__WIDTH 1
-#define R_SERIAL0_READ__data_avail__no 0
-#define R_SERIAL0_READ__data_avail__yes 1
-#define R_SERIAL0_READ__data_in__BITNR 0
-#define R_SERIAL0_READ__data_in__WIDTH 8
-
-#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061)
-#define R_SERIAL0_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL0_STATUS__xoff_detect__xoff 1
-#define R_SERIAL0_STATUS__cts___BITNR 6
-#define R_SERIAL0_STATUS__cts___WIDTH 1
-#define R_SERIAL0_STATUS__cts___active 0
-#define R_SERIAL0_STATUS__cts___inactive 1
-#define R_SERIAL0_STATUS__tr_ready__BITNR 5
-#define R_SERIAL0_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL0_STATUS__tr_ready__full 0
-#define R_SERIAL0_STATUS__tr_ready__ready 1
-#define R_SERIAL0_STATUS__rxd__BITNR 4
-#define R_SERIAL0_STATUS__rxd__WIDTH 1
-#define R_SERIAL0_STATUS__overrun__BITNR 3
-#define R_SERIAL0_STATUS__overrun__WIDTH 1
-#define R_SERIAL0_STATUS__overrun__no 0
-#define R_SERIAL0_STATUS__overrun__yes 1
-#define R_SERIAL0_STATUS__par_err__BITNR 2
-#define R_SERIAL0_STATUS__par_err__WIDTH 1
-#define R_SERIAL0_STATUS__par_err__no 0
-#define R_SERIAL0_STATUS__par_err__yes 1
-#define R_SERIAL0_STATUS__framing_err__BITNR 1
-#define R_SERIAL0_STATUS__framing_err__WIDTH 1
-#define R_SERIAL0_STATUS__framing_err__no 0
-#define R_SERIAL0_STATUS__framing_err__yes 1
-#define R_SERIAL0_STATUS__data_avail__BITNR 0
-#define R_SERIAL0_STATUS__data_avail__WIDTH 1
-#define R_SERIAL0_STATUS__data_avail__no 0
-#define R_SERIAL0_STATUS__data_avail__yes 1
-
-#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060)
-#define R_SERIAL0_REC_DATA__data_in__BITNR 0
-#define R_SERIAL0_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064)
-#define R_SERIAL0_XOFF__tx_stop__BITNR 9
-#define R_SERIAL0_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL0_XOFF__tx_stop__enable 0
-#define R_SERIAL0_XOFF__tx_stop__stop 1
-#define R_SERIAL0_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL0_XOFF__auto_xoff__disable 0
-#define R_SERIAL0_XOFF__auto_xoff__enable 1
-#define R_SERIAL0_XOFF__xoff_char__BITNR 0
-#define R_SERIAL0_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
-#define R_SERIAL1_CTRL__tr_baud__BITNR 28
-#define R_SERIAL1_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL1_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL1_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL1_CTRL__tr_baud__reserved 15
-#define R_SERIAL1_CTRL__rec_baud__BITNR 24
-#define R_SERIAL1_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL1_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL1_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL1_CTRL__rec_baud__reserved 15
-#define R_SERIAL1_CTRL__dma_err__BITNR 23
-#define R_SERIAL1_CTRL__dma_err__WIDTH 1
-#define R_SERIAL1_CTRL__dma_err__stop 0
-#define R_SERIAL1_CTRL__dma_err__ignore 1
-#define R_SERIAL1_CTRL__rec_enable__BITNR 22
-#define R_SERIAL1_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL1_CTRL__rec_enable__disable 0
-#define R_SERIAL1_CTRL__rec_enable__enable 1
-#define R_SERIAL1_CTRL__rts___BITNR 21
-#define R_SERIAL1_CTRL__rts___WIDTH 1
-#define R_SERIAL1_CTRL__rts___active 0
-#define R_SERIAL1_CTRL__rts___inactive 1
-#define R_SERIAL1_CTRL__sampling__BITNR 20
-#define R_SERIAL1_CTRL__sampling__WIDTH 1
-#define R_SERIAL1_CTRL__sampling__middle 0
-#define R_SERIAL1_CTRL__sampling__majority 1
-#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL1_CTRL__rec_stick_par__normal 0
-#define R_SERIAL1_CTRL__rec_stick_par__stick 1
-#define R_SERIAL1_CTRL__rec_par__BITNR 18
-#define R_SERIAL1_CTRL__rec_par__WIDTH 1
-#define R_SERIAL1_CTRL__rec_par__even 0
-#define R_SERIAL1_CTRL__rec_par__odd 1
-#define R_SERIAL1_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL1_CTRL__rec_par_en__disable 0
-#define R_SERIAL1_CTRL__rec_par_en__enable 1
-#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL1_CTRL__txd__BITNR 15
-#define R_SERIAL1_CTRL__txd__WIDTH 1
-#define R_SERIAL1_CTRL__tr_enable__BITNR 14
-#define R_SERIAL1_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL1_CTRL__tr_enable__disable 0
-#define R_SERIAL1_CTRL__tr_enable__enable 1
-#define R_SERIAL1_CTRL__auto_cts__BITNR 13
-#define R_SERIAL1_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL1_CTRL__auto_cts__disabled 0
-#define R_SERIAL1_CTRL__auto_cts__active 1
-#define R_SERIAL1_CTRL__stop_bits__BITNR 12
-#define R_SERIAL1_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL1_CTRL__stop_bits__one_bit 0
-#define R_SERIAL1_CTRL__stop_bits__two_bits 1
-#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL1_CTRL__tr_stick_par__normal 0
-#define R_SERIAL1_CTRL__tr_stick_par__stick 1
-#define R_SERIAL1_CTRL__tr_par__BITNR 10
-#define R_SERIAL1_CTRL__tr_par__WIDTH 1
-#define R_SERIAL1_CTRL__tr_par__even 0
-#define R_SERIAL1_CTRL__tr_par__odd 1
-#define R_SERIAL1_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL1_CTRL__tr_par_en__disable 0
-#define R_SERIAL1_CTRL__tr_par_en__enable 1
-#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL1_CTRL__data_out__BITNR 0
-#define R_SERIAL1_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b)
-#define R_SERIAL1_BAUD__tr_baud__BITNR 4
-#define R_SERIAL1_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL1_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL1_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL1_BAUD__tr_baud__reserved 15
-#define R_SERIAL1_BAUD__rec_baud__BITNR 0
-#define R_SERIAL1_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL1_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL1_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL1_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a)
-#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL1_REC_CTRL__dma_err__stop 0
-#define R_SERIAL1_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL1_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL1_REC_CTRL__rts___BITNR 5
-#define R_SERIAL1_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL1_REC_CTRL__rts___active 0
-#define R_SERIAL1_REC_CTRL__rts___inactive 1
-#define R_SERIAL1_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL1_REC_CTRL__sampling__middle 0
-#define R_SERIAL1_REC_CTRL__sampling__majority 1
-#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_par__even 0
-#define R_SERIAL1_REC_CTRL__rec_par__odd 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069)
-#define R_SERIAL1_TR_CTRL__txd__BITNR 7
-#define R_SERIAL1_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL1_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL1_TR_CTRL__auto_cts__active 1
-#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_par__even 0
-#define R_SERIAL1_TR_CTRL__tr_par__odd 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068)
-#define R_SERIAL1_TR_DATA__data_out__BITNR 0
-#define R_SERIAL1_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068)
-#define R_SERIAL1_READ__xoff_detect__BITNR 15
-#define R_SERIAL1_READ__xoff_detect__WIDTH 1
-#define R_SERIAL1_READ__xoff_detect__no_xoff 0
-#define R_SERIAL1_READ__xoff_detect__xoff 1
-#define R_SERIAL1_READ__cts___BITNR 14
-#define R_SERIAL1_READ__cts___WIDTH 1
-#define R_SERIAL1_READ__cts___active 0
-#define R_SERIAL1_READ__cts___inactive 1
-#define R_SERIAL1_READ__tr_ready__BITNR 13
-#define R_SERIAL1_READ__tr_ready__WIDTH 1
-#define R_SERIAL1_READ__tr_ready__full 0
-#define R_SERIAL1_READ__tr_ready__ready 1
-#define R_SERIAL1_READ__rxd__BITNR 12
-#define R_SERIAL1_READ__rxd__WIDTH 1
-#define R_SERIAL1_READ__overrun__BITNR 11
-#define R_SERIAL1_READ__overrun__WIDTH 1
-#define R_SERIAL1_READ__overrun__no 0
-#define R_SERIAL1_READ__overrun__yes 1
-#define R_SERIAL1_READ__par_err__BITNR 10
-#define R_SERIAL1_READ__par_err__WIDTH 1
-#define R_SERIAL1_READ__par_err__no 0
-#define R_SERIAL1_READ__par_err__yes 1
-#define R_SERIAL1_READ__framing_err__BITNR 9
-#define R_SERIAL1_READ__framing_err__WIDTH 1
-#define R_SERIAL1_READ__framing_err__no 0
-#define R_SERIAL1_READ__framing_err__yes 1
-#define R_SERIAL1_READ__data_avail__BITNR 8
-#define R_SERIAL1_READ__data_avail__WIDTH 1
-#define R_SERIAL1_READ__data_avail__no 0
-#define R_SERIAL1_READ__data_avail__yes 1
-#define R_SERIAL1_READ__data_in__BITNR 0
-#define R_SERIAL1_READ__data_in__WIDTH 8
-
-#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069)
-#define R_SERIAL1_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL1_STATUS__xoff_detect__xoff 1
-#define R_SERIAL1_STATUS__cts___BITNR 6
-#define R_SERIAL1_STATUS__cts___WIDTH 1
-#define R_SERIAL1_STATUS__cts___active 0
-#define R_SERIAL1_STATUS__cts___inactive 1
-#define R_SERIAL1_STATUS__tr_ready__BITNR 5
-#define R_SERIAL1_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL1_STATUS__tr_ready__full 0
-#define R_SERIAL1_STATUS__tr_ready__ready 1
-#define R_SERIAL1_STATUS__rxd__BITNR 4
-#define R_SERIAL1_STATUS__rxd__WIDTH 1
-#define R_SERIAL1_STATUS__overrun__BITNR 3
-#define R_SERIAL1_STATUS__overrun__WIDTH 1
-#define R_SERIAL1_STATUS__overrun__no 0
-#define R_SERIAL1_STATUS__overrun__yes 1
-#define R_SERIAL1_STATUS__par_err__BITNR 2
-#define R_SERIAL1_STATUS__par_err__WIDTH 1
-#define R_SERIAL1_STATUS__par_err__no 0
-#define R_SERIAL1_STATUS__par_err__yes 1
-#define R_SERIAL1_STATUS__framing_err__BITNR 1
-#define R_SERIAL1_STATUS__framing_err__WIDTH 1
-#define R_SERIAL1_STATUS__framing_err__no 0
-#define R_SERIAL1_STATUS__framing_err__yes 1
-#define R_SERIAL1_STATUS__data_avail__BITNR 0
-#define R_SERIAL1_STATUS__data_avail__WIDTH 1
-#define R_SERIAL1_STATUS__data_avail__no 0
-#define R_SERIAL1_STATUS__data_avail__yes 1
-
-#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068)
-#define R_SERIAL1_REC_DATA__data_in__BITNR 0
-#define R_SERIAL1_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c)
-#define R_SERIAL1_XOFF__tx_stop__BITNR 9
-#define R_SERIAL1_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL1_XOFF__tx_stop__enable 0
-#define R_SERIAL1_XOFF__tx_stop__stop 1
-#define R_SERIAL1_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL1_XOFF__auto_xoff__disable 0
-#define R_SERIAL1_XOFF__auto_xoff__enable 1
-#define R_SERIAL1_XOFF__xoff_char__BITNR 0
-#define R_SERIAL1_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070)
-#define R_SERIAL2_CTRL__tr_baud__BITNR 28
-#define R_SERIAL2_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL2_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL2_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL2_CTRL__tr_baud__reserved 15
-#define R_SERIAL2_CTRL__rec_baud__BITNR 24
-#define R_SERIAL2_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL2_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL2_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL2_CTRL__rec_baud__reserved 15
-#define R_SERIAL2_CTRL__dma_err__BITNR 23
-#define R_SERIAL2_CTRL__dma_err__WIDTH 1
-#define R_SERIAL2_CTRL__dma_err__stop 0
-#define R_SERIAL2_CTRL__dma_err__ignore 1
-#define R_SERIAL2_CTRL__rec_enable__BITNR 22
-#define R_SERIAL2_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL2_CTRL__rec_enable__disable 0
-#define R_SERIAL2_CTRL__rec_enable__enable 1
-#define R_SERIAL2_CTRL__rts___BITNR 21
-#define R_SERIAL2_CTRL__rts___WIDTH 1
-#define R_SERIAL2_CTRL__rts___active 0
-#define R_SERIAL2_CTRL__rts___inactive 1
-#define R_SERIAL2_CTRL__sampling__BITNR 20
-#define R_SERIAL2_CTRL__sampling__WIDTH 1
-#define R_SERIAL2_CTRL__sampling__middle 0
-#define R_SERIAL2_CTRL__sampling__majority 1
-#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL2_CTRL__rec_stick_par__normal 0
-#define R_SERIAL2_CTRL__rec_stick_par__stick 1
-#define R_SERIAL2_CTRL__rec_par__BITNR 18
-#define R_SERIAL2_CTRL__rec_par__WIDTH 1
-#define R_SERIAL2_CTRL__rec_par__even 0
-#define R_SERIAL2_CTRL__rec_par__odd 1
-#define R_SERIAL2_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL2_CTRL__rec_par_en__disable 0
-#define R_SERIAL2_CTRL__rec_par_en__enable 1
-#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL2_CTRL__txd__BITNR 15
-#define R_SERIAL2_CTRL__txd__WIDTH 1
-#define R_SERIAL2_CTRL__tr_enable__BITNR 14
-#define R_SERIAL2_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL2_CTRL__tr_enable__disable 0
-#define R_SERIAL2_CTRL__tr_enable__enable 1
-#define R_SERIAL2_CTRL__auto_cts__BITNR 13
-#define R_SERIAL2_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL2_CTRL__auto_cts__disabled 0
-#define R_SERIAL2_CTRL__auto_cts__active 1
-#define R_SERIAL2_CTRL__stop_bits__BITNR 12
-#define R_SERIAL2_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL2_CTRL__stop_bits__one_bit 0
-#define R_SERIAL2_CTRL__stop_bits__two_bits 1
-#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL2_CTRL__tr_stick_par__normal 0
-#define R_SERIAL2_CTRL__tr_stick_par__stick 1
-#define R_SERIAL2_CTRL__tr_par__BITNR 10
-#define R_SERIAL2_CTRL__tr_par__WIDTH 1
-#define R_SERIAL2_CTRL__tr_par__even 0
-#define R_SERIAL2_CTRL__tr_par__odd 1
-#define R_SERIAL2_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL2_CTRL__tr_par_en__disable 0
-#define R_SERIAL2_CTRL__tr_par_en__enable 1
-#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL2_CTRL__data_out__BITNR 0
-#define R_SERIAL2_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073)
-#define R_SERIAL2_BAUD__tr_baud__BITNR 4
-#define R_SERIAL2_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL2_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL2_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL2_BAUD__tr_baud__reserved 15
-#define R_SERIAL2_BAUD__rec_baud__BITNR 0
-#define R_SERIAL2_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL2_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL2_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL2_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072)
-#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL2_REC_CTRL__dma_err__stop 0
-#define R_SERIAL2_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL2_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL2_REC_CTRL__rts___BITNR 5
-#define R_SERIAL2_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL2_REC_CTRL__rts___active 0
-#define R_SERIAL2_REC_CTRL__rts___inactive 1
-#define R_SERIAL2_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL2_REC_CTRL__sampling__middle 0
-#define R_SERIAL2_REC_CTRL__sampling__majority 1
-#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_par__even 0
-#define R_SERIAL2_REC_CTRL__rec_par__odd 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071)
-#define R_SERIAL2_TR_CTRL__txd__BITNR 7
-#define R_SERIAL2_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL2_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL2_TR_CTRL__auto_cts__active 1
-#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_par__even 0
-#define R_SERIAL2_TR_CTRL__tr_par__odd 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070)
-#define R_SERIAL2_TR_DATA__data_out__BITNR 0
-#define R_SERIAL2_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070)
-#define R_SERIAL2_READ__xoff_detect__BITNR 15
-#define R_SERIAL2_READ__xoff_detect__WIDTH 1
-#define R_SERIAL2_READ__xoff_detect__no_xoff 0
-#define R_SERIAL2_READ__xoff_detect__xoff 1
-#define R_SERIAL2_READ__cts___BITNR 14
-#define R_SERIAL2_READ__cts___WIDTH 1
-#define R_SERIAL2_READ__cts___active 0
-#define R_SERIAL2_READ__cts___inactive 1
-#define R_SERIAL2_READ__tr_ready__BITNR 13
-#define R_SERIAL2_READ__tr_ready__WIDTH 1
-#define R_SERIAL2_READ__tr_ready__full 0
-#define R_SERIAL2_READ__tr_ready__ready 1
-#define R_SERIAL2_READ__rxd__BITNR 12
-#define R_SERIAL2_READ__rxd__WIDTH 1
-#define R_SERIAL2_READ__overrun__BITNR 11
-#define R_SERIAL2_READ__overrun__WIDTH 1
-#define R_SERIAL2_READ__overrun__no 0
-#define R_SERIAL2_READ__overrun__yes 1
-#define R_SERIAL2_READ__par_err__BITNR 10
-#define R_SERIAL2_READ__par_err__WIDTH 1
-#define R_SERIAL2_READ__par_err__no 0
-#define R_SERIAL2_READ__par_err__yes 1
-#define R_SERIAL2_READ__framing_err__BITNR 9
-#define R_SERIAL2_READ__framing_err__WIDTH 1
-#define R_SERIAL2_READ__framing_err__no 0
-#define R_SERIAL2_READ__framing_err__yes 1
-#define R_SERIAL2_READ__data_avail__BITNR 8
-#define R_SERIAL2_READ__data_avail__WIDTH 1
-#define R_SERIAL2_READ__data_avail__no 0
-#define R_SERIAL2_READ__data_avail__yes 1
-#define R_SERIAL2_READ__data_in__BITNR 0
-#define R_SERIAL2_READ__data_in__WIDTH 8
-
-#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071)
-#define R_SERIAL2_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL2_STATUS__xoff_detect__xoff 1
-#define R_SERIAL2_STATUS__cts___BITNR 6
-#define R_SERIAL2_STATUS__cts___WIDTH 1
-#define R_SERIAL2_STATUS__cts___active 0
-#define R_SERIAL2_STATUS__cts___inactive 1
-#define R_SERIAL2_STATUS__tr_ready__BITNR 5
-#define R_SERIAL2_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL2_STATUS__tr_ready__full 0
-#define R_SERIAL2_STATUS__tr_ready__ready 1
-#define R_SERIAL2_STATUS__rxd__BITNR 4
-#define R_SERIAL2_STATUS__rxd__WIDTH 1
-#define R_SERIAL2_STATUS__overrun__BITNR 3
-#define R_SERIAL2_STATUS__overrun__WIDTH 1
-#define R_SERIAL2_STATUS__overrun__no 0
-#define R_SERIAL2_STATUS__overrun__yes 1
-#define R_SERIAL2_STATUS__par_err__BITNR 2
-#define R_SERIAL2_STATUS__par_err__WIDTH 1
-#define R_SERIAL2_STATUS__par_err__no 0
-#define R_SERIAL2_STATUS__par_err__yes 1
-#define R_SERIAL2_STATUS__framing_err__BITNR 1
-#define R_SERIAL2_STATUS__framing_err__WIDTH 1
-#define R_SERIAL2_STATUS__framing_err__no 0
-#define R_SERIAL2_STATUS__framing_err__yes 1
-#define R_SERIAL2_STATUS__data_avail__BITNR 0
-#define R_SERIAL2_STATUS__data_avail__WIDTH 1
-#define R_SERIAL2_STATUS__data_avail__no 0
-#define R_SERIAL2_STATUS__data_avail__yes 1
-
-#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070)
-#define R_SERIAL2_REC_DATA__data_in__BITNR 0
-#define R_SERIAL2_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074)
-#define R_SERIAL2_XOFF__tx_stop__BITNR 9
-#define R_SERIAL2_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL2_XOFF__tx_stop__enable 0
-#define R_SERIAL2_XOFF__tx_stop__stop 1
-#define R_SERIAL2_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL2_XOFF__auto_xoff__disable 0
-#define R_SERIAL2_XOFF__auto_xoff__enable 1
-#define R_SERIAL2_XOFF__xoff_char__BITNR 0
-#define R_SERIAL2_XOFF__xoff_char__WIDTH 8
-
-#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
-#define R_SERIAL3_CTRL__tr_baud__BITNR 28
-#define R_SERIAL3_CTRL__tr_baud__WIDTH 4
-#define R_SERIAL3_CTRL__tr_baud__c300Hz 0
-#define R_SERIAL3_CTRL__tr_baud__c600Hz 1
-#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2
-#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3
-#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4
-#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5
-#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6
-#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7
-#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8
-#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9
-#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10
-#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11
-#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12
-#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13
-#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14
-#define R_SERIAL3_CTRL__tr_baud__reserved 15
-#define R_SERIAL3_CTRL__rec_baud__BITNR 24
-#define R_SERIAL3_CTRL__rec_baud__WIDTH 4
-#define R_SERIAL3_CTRL__rec_baud__c300Hz 0
-#define R_SERIAL3_CTRL__rec_baud__c600Hz 1
-#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2
-#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3
-#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4
-#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5
-#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6
-#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7
-#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8
-#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9
-#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10
-#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11
-#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12
-#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13
-#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14
-#define R_SERIAL3_CTRL__rec_baud__reserved 15
-#define R_SERIAL3_CTRL__dma_err__BITNR 23
-#define R_SERIAL3_CTRL__dma_err__WIDTH 1
-#define R_SERIAL3_CTRL__dma_err__stop 0
-#define R_SERIAL3_CTRL__dma_err__ignore 1
-#define R_SERIAL3_CTRL__rec_enable__BITNR 22
-#define R_SERIAL3_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL3_CTRL__rec_enable__disable 0
-#define R_SERIAL3_CTRL__rec_enable__enable 1
-#define R_SERIAL3_CTRL__rts___BITNR 21
-#define R_SERIAL3_CTRL__rts___WIDTH 1
-#define R_SERIAL3_CTRL__rts___active 0
-#define R_SERIAL3_CTRL__rts___inactive 1
-#define R_SERIAL3_CTRL__sampling__BITNR 20
-#define R_SERIAL3_CTRL__sampling__WIDTH 1
-#define R_SERIAL3_CTRL__sampling__middle 0
-#define R_SERIAL3_CTRL__sampling__majority 1
-#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19
-#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL3_CTRL__rec_stick_par__normal 0
-#define R_SERIAL3_CTRL__rec_stick_par__stick 1
-#define R_SERIAL3_CTRL__rec_par__BITNR 18
-#define R_SERIAL3_CTRL__rec_par__WIDTH 1
-#define R_SERIAL3_CTRL__rec_par__even 0
-#define R_SERIAL3_CTRL__rec_par__odd 1
-#define R_SERIAL3_CTRL__rec_par_en__BITNR 17
-#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL3_CTRL__rec_par_en__disable 0
-#define R_SERIAL3_CTRL__rec_par_en__enable 1
-#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16
-#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1
-#define R_SERIAL3_CTRL__txd__BITNR 15
-#define R_SERIAL3_CTRL__txd__WIDTH 1
-#define R_SERIAL3_CTRL__tr_enable__BITNR 14
-#define R_SERIAL3_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL3_CTRL__tr_enable__disable 0
-#define R_SERIAL3_CTRL__tr_enable__enable 1
-#define R_SERIAL3_CTRL__auto_cts__BITNR 13
-#define R_SERIAL3_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL3_CTRL__auto_cts__disabled 0
-#define R_SERIAL3_CTRL__auto_cts__active 1
-#define R_SERIAL3_CTRL__stop_bits__BITNR 12
-#define R_SERIAL3_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL3_CTRL__stop_bits__one_bit 0
-#define R_SERIAL3_CTRL__stop_bits__two_bits 1
-#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11
-#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL3_CTRL__tr_stick_par__normal 0
-#define R_SERIAL3_CTRL__tr_stick_par__stick 1
-#define R_SERIAL3_CTRL__tr_par__BITNR 10
-#define R_SERIAL3_CTRL__tr_par__WIDTH 1
-#define R_SERIAL3_CTRL__tr_par__even 0
-#define R_SERIAL3_CTRL__tr_par__odd 1
-#define R_SERIAL3_CTRL__tr_par_en__BITNR 9
-#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL3_CTRL__tr_par_en__disable 0
-#define R_SERIAL3_CTRL__tr_par_en__enable 1
-#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8
-#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1
-#define R_SERIAL3_CTRL__data_out__BITNR 0
-#define R_SERIAL3_CTRL__data_out__WIDTH 8
-
-#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b)
-#define R_SERIAL3_BAUD__tr_baud__BITNR 4
-#define R_SERIAL3_BAUD__tr_baud__WIDTH 4
-#define R_SERIAL3_BAUD__tr_baud__c300Hz 0
-#define R_SERIAL3_BAUD__tr_baud__c600Hz 1
-#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2
-#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3
-#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4
-#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5
-#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6
-#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7
-#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8
-#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9
-#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10
-#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11
-#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12
-#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13
-#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14
-#define R_SERIAL3_BAUD__tr_baud__reserved 15
-#define R_SERIAL3_BAUD__rec_baud__BITNR 0
-#define R_SERIAL3_BAUD__rec_baud__WIDTH 4
-#define R_SERIAL3_BAUD__rec_baud__c300Hz 0
-#define R_SERIAL3_BAUD__rec_baud__c600Hz 1
-#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2
-#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3
-#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4
-#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5
-#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6
-#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7
-#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8
-#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9
-#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10
-#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11
-#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12
-#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13
-#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14
-#define R_SERIAL3_BAUD__rec_baud__reserved 15
-
-#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a)
-#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7
-#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1
-#define R_SERIAL3_REC_CTRL__dma_err__stop 0
-#define R_SERIAL3_REC_CTRL__dma_err__ignore 1
-#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6
-#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_enable__disable 0
-#define R_SERIAL3_REC_CTRL__rec_enable__enable 1
-#define R_SERIAL3_REC_CTRL__rts___BITNR 5
-#define R_SERIAL3_REC_CTRL__rts___WIDTH 1
-#define R_SERIAL3_REC_CTRL__rts___active 0
-#define R_SERIAL3_REC_CTRL__rts___inactive 1
-#define R_SERIAL3_REC_CTRL__sampling__BITNR 4
-#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1
-#define R_SERIAL3_REC_CTRL__sampling__middle 0
-#define R_SERIAL3_REC_CTRL__sampling__majority 1
-#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3
-#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0
-#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1
-#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2
-#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_par__even 0
-#define R_SERIAL3_REC_CTRL__rec_par__odd 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0
-#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1
-#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0
-#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1
-#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0
-#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1
-
-#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079)
-#define R_SERIAL3_TR_CTRL__txd__BITNR 7
-#define R_SERIAL3_TR_CTRL__txd__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6
-#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_enable__disable 0
-#define R_SERIAL3_TR_CTRL__tr_enable__enable 1
-#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5
-#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1
-#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0
-#define R_SERIAL3_TR_CTRL__auto_cts__active 1
-#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4
-#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1
-#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0
-#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1
-#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3
-#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0
-#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1
-#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2
-#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_par__even 0
-#define R_SERIAL3_TR_CTRL__tr_par__odd 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0
-#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1
-#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0
-#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1
-#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0
-#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1
-
-#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078)
-#define R_SERIAL3_TR_DATA__data_out__BITNR 0
-#define R_SERIAL3_TR_DATA__data_out__WIDTH 8
-
-#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078)
-#define R_SERIAL3_READ__xoff_detect__BITNR 15
-#define R_SERIAL3_READ__xoff_detect__WIDTH 1
-#define R_SERIAL3_READ__xoff_detect__no_xoff 0
-#define R_SERIAL3_READ__xoff_detect__xoff 1
-#define R_SERIAL3_READ__cts___BITNR 14
-#define R_SERIAL3_READ__cts___WIDTH 1
-#define R_SERIAL3_READ__cts___active 0
-#define R_SERIAL3_READ__cts___inactive 1
-#define R_SERIAL3_READ__tr_ready__BITNR 13
-#define R_SERIAL3_READ__tr_ready__WIDTH 1
-#define R_SERIAL3_READ__tr_ready__full 0
-#define R_SERIAL3_READ__tr_ready__ready 1
-#define R_SERIAL3_READ__rxd__BITNR 12
-#define R_SERIAL3_READ__rxd__WIDTH 1
-#define R_SERIAL3_READ__overrun__BITNR 11
-#define R_SERIAL3_READ__overrun__WIDTH 1
-#define R_SERIAL3_READ__overrun__no 0
-#define R_SERIAL3_READ__overrun__yes 1
-#define R_SERIAL3_READ__par_err__BITNR 10
-#define R_SERIAL3_READ__par_err__WIDTH 1
-#define R_SERIAL3_READ__par_err__no 0
-#define R_SERIAL3_READ__par_err__yes 1
-#define R_SERIAL3_READ__framing_err__BITNR 9
-#define R_SERIAL3_READ__framing_err__WIDTH 1
-#define R_SERIAL3_READ__framing_err__no 0
-#define R_SERIAL3_READ__framing_err__yes 1
-#define R_SERIAL3_READ__data_avail__BITNR 8
-#define R_SERIAL3_READ__data_avail__WIDTH 1
-#define R_SERIAL3_READ__data_avail__no 0
-#define R_SERIAL3_READ__data_avail__yes 1
-#define R_SERIAL3_READ__data_in__BITNR 0
-#define R_SERIAL3_READ__data_in__WIDTH 8
-
-#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079)
-#define R_SERIAL3_STATUS__xoff_detect__BITNR 7
-#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1
-#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0
-#define R_SERIAL3_STATUS__xoff_detect__xoff 1
-#define R_SERIAL3_STATUS__cts___BITNR 6
-#define R_SERIAL3_STATUS__cts___WIDTH 1
-#define R_SERIAL3_STATUS__cts___active 0
-#define R_SERIAL3_STATUS__cts___inactive 1
-#define R_SERIAL3_STATUS__tr_ready__BITNR 5
-#define R_SERIAL3_STATUS__tr_ready__WIDTH 1
-#define R_SERIAL3_STATUS__tr_ready__full 0
-#define R_SERIAL3_STATUS__tr_ready__ready 1
-#define R_SERIAL3_STATUS__rxd__BITNR 4
-#define R_SERIAL3_STATUS__rxd__WIDTH 1
-#define R_SERIAL3_STATUS__overrun__BITNR 3
-#define R_SERIAL3_STATUS__overrun__WIDTH 1
-#define R_SERIAL3_STATUS__overrun__no 0
-#define R_SERIAL3_STATUS__overrun__yes 1
-#define R_SERIAL3_STATUS__par_err__BITNR 2
-#define R_SERIAL3_STATUS__par_err__WIDTH 1
-#define R_SERIAL3_STATUS__par_err__no 0
-#define R_SERIAL3_STATUS__par_err__yes 1
-#define R_SERIAL3_STATUS__framing_err__BITNR 1
-#define R_SERIAL3_STATUS__framing_err__WIDTH 1
-#define R_SERIAL3_STATUS__framing_err__no 0
-#define R_SERIAL3_STATUS__framing_err__yes 1
-#define R_SERIAL3_STATUS__data_avail__BITNR 0
-#define R_SERIAL3_STATUS__data_avail__WIDTH 1
-#define R_SERIAL3_STATUS__data_avail__no 0
-#define R_SERIAL3_STATUS__data_avail__yes 1
-
-#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078)
-#define R_SERIAL3_REC_DATA__data_in__BITNR 0
-#define R_SERIAL3_REC_DATA__data_in__WIDTH 8
-
-#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c)
-#define R_SERIAL3_XOFF__tx_stop__BITNR 9
-#define R_SERIAL3_XOFF__tx_stop__WIDTH 1
-#define R_SERIAL3_XOFF__tx_stop__enable 0
-#define R_SERIAL3_XOFF__tx_stop__stop 1
-#define R_SERIAL3_XOFF__auto_xoff__BITNR 8
-#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1
-#define R_SERIAL3_XOFF__auto_xoff__disable 0
-#define R_SERIAL3_XOFF__auto_xoff__enable 1
-#define R_SERIAL3_XOFF__xoff_char__BITNR 0
-#define R_SERIAL3_XOFF__xoff_char__WIDTH 8
-
-#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c)
-#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28
-#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24
-#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20
-#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16
-#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12
-#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8
-#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3
-#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4
-#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0
-#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1
-#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2
-#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3
-#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0
-#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2
-#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0
-#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1
-#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2
-#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3
-
-/*
-!* Network interface registers
-!*/
-
-#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080)
-#define R_NETWORK_SA_0__ma0_low__BITNR 0
-#define R_NETWORK_SA_0__ma0_low__WIDTH 32
-
-#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084)
-#define R_NETWORK_SA_1__ma1_low__BITNR 16
-#define R_NETWORK_SA_1__ma1_low__WIDTH 16
-#define R_NETWORK_SA_1__ma0_high__BITNR 0
-#define R_NETWORK_SA_1__ma0_high__WIDTH 16
-
-#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088)
-#define R_NETWORK_SA_2__ma1_high__BITNR 0
-#define R_NETWORK_SA_2__ma1_high__WIDTH 32
-
-#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c)
-#define R_NETWORK_GA_0__ga_low__BITNR 0
-#define R_NETWORK_GA_0__ga_low__WIDTH 32
-
-#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090)
-#define R_NETWORK_GA_1__ga_high__BITNR 0
-#define R_NETWORK_GA_1__ga_high__WIDTH 32
-
-#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094)
-#define R_NETWORK_REC_CONFIG__max_size__BITNR 10
-#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1
-#define R_NETWORK_REC_CONFIG__max_size__size1518 0
-#define R_NETWORK_REC_CONFIG__max_size__size1522 1
-#define R_NETWORK_REC_CONFIG__duplex__BITNR 9
-#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1
-#define R_NETWORK_REC_CONFIG__duplex__full 1
-#define R_NETWORK_REC_CONFIG__duplex__half 0
-#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8
-#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1
-#define R_NETWORK_REC_CONFIG__bad_crc__receive 1
-#define R_NETWORK_REC_CONFIG__bad_crc__discard 0
-#define R_NETWORK_REC_CONFIG__oversize__BITNR 7
-#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1
-#define R_NETWORK_REC_CONFIG__oversize__receive 1
-#define R_NETWORK_REC_CONFIG__oversize__discard 0
-#define R_NETWORK_REC_CONFIG__undersize__BITNR 6
-#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1
-#define R_NETWORK_REC_CONFIG__undersize__receive 1
-#define R_NETWORK_REC_CONFIG__undersize__discard 0
-#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5
-#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1
-#define R_NETWORK_REC_CONFIG__all_roots__receive 1
-#define R_NETWORK_REC_CONFIG__all_roots__discard 0
-#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4
-#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1
-#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1
-#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0
-#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3
-#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1
-#define R_NETWORK_REC_CONFIG__broadcast__receive 1
-#define R_NETWORK_REC_CONFIG__broadcast__discard 0
-#define R_NETWORK_REC_CONFIG__individual__BITNR 2
-#define R_NETWORK_REC_CONFIG__individual__WIDTH 1
-#define R_NETWORK_REC_CONFIG__individual__receive 1
-#define R_NETWORK_REC_CONFIG__individual__discard 0
-#define R_NETWORK_REC_CONFIG__ma1__BITNR 1
-#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1
-#define R_NETWORK_REC_CONFIG__ma1__enable 1
-#define R_NETWORK_REC_CONFIG__ma1__disable 0
-#define R_NETWORK_REC_CONFIG__ma0__BITNR 0
-#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1
-#define R_NETWORK_REC_CONFIG__ma0__enable 1
-#define R_NETWORK_REC_CONFIG__ma0__disable 0
-
-#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098)
-#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5
-#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__loopback__on 1
-#define R_NETWORK_GEN_CONFIG__loopback__off 0
-#define R_NETWORK_GEN_CONFIG__frame__BITNR 4
-#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__frame__tokenr 1
-#define R_NETWORK_GEN_CONFIG__frame__ether 0
-#define R_NETWORK_GEN_CONFIG__vg__BITNR 3
-#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__vg__on 1
-#define R_NETWORK_GEN_CONFIG__vg__off 0
-#define R_NETWORK_GEN_CONFIG__phy__BITNR 1
-#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2
-#define R_NETWORK_GEN_CONFIG__phy__sni 0
-#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1
-#define R_NETWORK_GEN_CONFIG__phy__mii_err 2
-#define R_NETWORK_GEN_CONFIG__phy__mii_req 3
-#define R_NETWORK_GEN_CONFIG__enable__BITNR 0
-#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1
-#define R_NETWORK_GEN_CONFIG__enable__on 1
-#define R_NETWORK_GEN_CONFIG__enable__off 0
-
-#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c)
-#define R_NETWORK_TR_CTRL__clr_error__BITNR 8
-#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1
-#define R_NETWORK_TR_CTRL__clr_error__clr 1
-#define R_NETWORK_TR_CTRL__clr_error__nop 0
-#define R_NETWORK_TR_CTRL__delay__BITNR 5
-#define R_NETWORK_TR_CTRL__delay__WIDTH 1
-#define R_NETWORK_TR_CTRL__delay__d2us 1
-#define R_NETWORK_TR_CTRL__delay__none 0
-#define R_NETWORK_TR_CTRL__cancel__BITNR 4
-#define R_NETWORK_TR_CTRL__cancel__WIDTH 1
-#define R_NETWORK_TR_CTRL__cancel__do 1
-#define R_NETWORK_TR_CTRL__cancel__dont 0
-#define R_NETWORK_TR_CTRL__cd__BITNR 3
-#define R_NETWORK_TR_CTRL__cd__WIDTH 1
-#define R_NETWORK_TR_CTRL__cd__enable 0
-#define R_NETWORK_TR_CTRL__cd__disable 1
-#define R_NETWORK_TR_CTRL__cd__ack_col 0
-#define R_NETWORK_TR_CTRL__cd__ack_crs 1
-#define R_NETWORK_TR_CTRL__retry__BITNR 2
-#define R_NETWORK_TR_CTRL__retry__WIDTH 1
-#define R_NETWORK_TR_CTRL__retry__enable 0
-#define R_NETWORK_TR_CTRL__retry__disable 1
-#define R_NETWORK_TR_CTRL__pad__BITNR 1
-#define R_NETWORK_TR_CTRL__pad__WIDTH 1
-#define R_NETWORK_TR_CTRL__pad__enable 1
-#define R_NETWORK_TR_CTRL__pad__disable 0
-#define R_NETWORK_TR_CTRL__crc__BITNR 0
-#define R_NETWORK_TR_CTRL__crc__WIDTH 1
-#define R_NETWORK_TR_CTRL__crc__enable 0
-#define R_NETWORK_TR_CTRL__crc__disable 1
-
-#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0)
-#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4
-#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4
-#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3
-#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdck__BITNR 2
-#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1
-#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1
-#define R_NETWORK_MGM_CTRL__mdoe__enable 1
-#define R_NETWORK_MGM_CTRL__mdoe__disable 0
-#define R_NETWORK_MGM_CTRL__mdio__BITNR 0
-#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1
-
-#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0)
-#define R_NETWORK_STAT__rxd_pins__BITNR 4
-#define R_NETWORK_STAT__rxd_pins__WIDTH 4
-#define R_NETWORK_STAT__rxer__BITNR 3
-#define R_NETWORK_STAT__rxer__WIDTH 1
-#define R_NETWORK_STAT__underrun__BITNR 2
-#define R_NETWORK_STAT__underrun__WIDTH 1
-#define R_NETWORK_STAT__underrun__yes 1
-#define R_NETWORK_STAT__underrun__no 0
-#define R_NETWORK_STAT__exc_col__BITNR 1
-#define R_NETWORK_STAT__exc_col__WIDTH 1
-#define R_NETWORK_STAT__exc_col__yes 1
-#define R_NETWORK_STAT__exc_col__no 0
-#define R_NETWORK_STAT__mdio__BITNR 0
-#define R_NETWORK_STAT__mdio__WIDTH 1
-
-#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4)
-#define R_REC_COUNTERS__congestion__BITNR 24
-#define R_REC_COUNTERS__congestion__WIDTH 8
-#define R_REC_COUNTERS__oversize__BITNR 16
-#define R_REC_COUNTERS__oversize__WIDTH 8
-#define R_REC_COUNTERS__alignment_error__BITNR 8
-#define R_REC_COUNTERS__alignment_error__WIDTH 8
-#define R_REC_COUNTERS__crc_error__BITNR 0
-#define R_REC_COUNTERS__crc_error__WIDTH 8
-
-#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8)
-#define R_TR_COUNTERS__deferred__BITNR 24
-#define R_TR_COUNTERS__deferred__WIDTH 8
-#define R_TR_COUNTERS__late_col__BITNR 16
-#define R_TR_COUNTERS__late_col__WIDTH 8
-#define R_TR_COUNTERS__multiple_col__BITNR 8
-#define R_TR_COUNTERS__multiple_col__WIDTH 8
-#define R_TR_COUNTERS__single_col__BITNR 0
-#define R_TR_COUNTERS__single_col__WIDTH 8
-
-#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac)
-#define R_PHY_COUNTERS__sqe_test_error__BITNR 8
-#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8
-#define R_PHY_COUNTERS__carrier_loss__BITNR 0
-#define R_PHY_COUNTERS__carrier_loss__WIDTH 8
-
-/*
-!* Parallel printer port registers
-!*/
-
-#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_PAR0_CTRL_DATA__peri_int__BITNR 24
-#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1
-#define R_PAR0_CTRL_DATA__peri_int__ack 1
-#define R_PAR0_CTRL_DATA__peri_int__nop 0
-#define R_PAR0_CTRL_DATA__oe__BITNR 20
-#define R_PAR0_CTRL_DATA__oe__WIDTH 1
-#define R_PAR0_CTRL_DATA__oe__enable 1
-#define R_PAR0_CTRL_DATA__oe__disable 0
-#define R_PAR0_CTRL_DATA__seli__BITNR 19
-#define R_PAR0_CTRL_DATA__seli__WIDTH 1
-#define R_PAR0_CTRL_DATA__seli__active 1
-#define R_PAR0_CTRL_DATA__seli__inactive 0
-#define R_PAR0_CTRL_DATA__autofd__BITNR 18
-#define R_PAR0_CTRL_DATA__autofd__WIDTH 1
-#define R_PAR0_CTRL_DATA__autofd__active 1
-#define R_PAR0_CTRL_DATA__autofd__inactive 0
-#define R_PAR0_CTRL_DATA__strb__BITNR 17
-#define R_PAR0_CTRL_DATA__strb__WIDTH 1
-#define R_PAR0_CTRL_DATA__strb__active 1
-#define R_PAR0_CTRL_DATA__strb__inactive 0
-#define R_PAR0_CTRL_DATA__init__BITNR 16
-#define R_PAR0_CTRL_DATA__init__WIDTH 1
-#define R_PAR0_CTRL_DATA__init__active 1
-#define R_PAR0_CTRL_DATA__init__inactive 0
-#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8
-#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1
-#define R_PAR0_CTRL_DATA__ecp_cmd__command 1
-#define R_PAR0_CTRL_DATA__ecp_cmd__data 0
-#define R_PAR0_CTRL_DATA__data__BITNR 0
-#define R_PAR0_CTRL_DATA__data__WIDTH 8
-
-#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042)
-#define R_PAR0_CTRL__ctrl__BITNR 0
-#define R_PAR0_CTRL__ctrl__WIDTH 5
-
-#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
-#define R_PAR0_STATUS_DATA__mode__BITNR 29
-#define R_PAR0_STATUS_DATA__mode__WIDTH 3
-#define R_PAR0_STATUS_DATA__mode__manual 0
-#define R_PAR0_STATUS_DATA__mode__centronics 1
-#define R_PAR0_STATUS_DATA__mode__fastbyte 2
-#define R_PAR0_STATUS_DATA__mode__nibble 3
-#define R_PAR0_STATUS_DATA__mode__byte 4
-#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5
-#define R_PAR0_STATUS_DATA__mode__ecp_rev 6
-#define R_PAR0_STATUS_DATA__mode__off 7
-#define R_PAR0_STATUS_DATA__mode__epp_wr1 5
-#define R_PAR0_STATUS_DATA__mode__epp_wr2 6
-#define R_PAR0_STATUS_DATA__mode__epp_wr3 7
-#define R_PAR0_STATUS_DATA__mode__epp_rd 0
-#define R_PAR0_STATUS_DATA__perr__BITNR 28
-#define R_PAR0_STATUS_DATA__perr__WIDTH 1
-#define R_PAR0_STATUS_DATA__perr__active 1
-#define R_PAR0_STATUS_DATA__perr__inactive 0
-#define R_PAR0_STATUS_DATA__ack__BITNR 27
-#define R_PAR0_STATUS_DATA__ack__WIDTH 1
-#define R_PAR0_STATUS_DATA__ack__active 0
-#define R_PAR0_STATUS_DATA__ack__inactive 1
-#define R_PAR0_STATUS_DATA__busy__BITNR 26
-#define R_PAR0_STATUS_DATA__busy__WIDTH 1
-#define R_PAR0_STATUS_DATA__busy__active 1
-#define R_PAR0_STATUS_DATA__busy__inactive 0
-#define R_PAR0_STATUS_DATA__fault__BITNR 25
-#define R_PAR0_STATUS_DATA__fault__WIDTH 1
-#define R_PAR0_STATUS_DATA__fault__active 0
-#define R_PAR0_STATUS_DATA__fault__inactive 1
-#define R_PAR0_STATUS_DATA__sel__BITNR 24
-#define R_PAR0_STATUS_DATA__sel__WIDTH 1
-#define R_PAR0_STATUS_DATA__sel__active 1
-#define R_PAR0_STATUS_DATA__sel__inactive 0
-#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
-#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1
-#define R_PAR0_STATUS_DATA__ext_mode__enable 1
-#define R_PAR0_STATUS_DATA__ext_mode__disable 0
-#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
-#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1
-#define R_PAR0_STATUS_DATA__ecp_16__active 1
-#define R_PAR0_STATUS_DATA__ecp_16__inactive 0
-#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
-#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_PAR0_STATUS_DATA__tr_rdy__ready 1
-#define R_PAR0_STATUS_DATA__tr_rdy__busy 0
-#define R_PAR0_STATUS_DATA__dav__BITNR 16
-#define R_PAR0_STATUS_DATA__dav__WIDTH 1
-#define R_PAR0_STATUS_DATA__dav__data 1
-#define R_PAR0_STATUS_DATA__dav__nodata 0
-#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8
-#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1
-#define R_PAR0_STATUS_DATA__ecp_cmd__command 1
-#define R_PAR0_STATUS_DATA__ecp_cmd__data 0
-#define R_PAR0_STATUS_DATA__data__BITNR 0
-#define R_PAR0_STATUS_DATA__data__WIDTH 8
-
-#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042)
-#define R_PAR0_STATUS__mode__BITNR 13
-#define R_PAR0_STATUS__mode__WIDTH 3
-#define R_PAR0_STATUS__mode__manual 0
-#define R_PAR0_STATUS__mode__centronics 1
-#define R_PAR0_STATUS__mode__fastbyte 2
-#define R_PAR0_STATUS__mode__nibble 3
-#define R_PAR0_STATUS__mode__byte 4
-#define R_PAR0_STATUS__mode__ecp_fwd 5
-#define R_PAR0_STATUS__mode__ecp_rev 6
-#define R_PAR0_STATUS__mode__off 7
-#define R_PAR0_STATUS__mode__epp_wr1 5
-#define R_PAR0_STATUS__mode__epp_wr2 6
-#define R_PAR0_STATUS__mode__epp_wr3 7
-#define R_PAR0_STATUS__mode__epp_rd 0
-#define R_PAR0_STATUS__perr__BITNR 12
-#define R_PAR0_STATUS__perr__WIDTH 1
-#define R_PAR0_STATUS__perr__active 1
-#define R_PAR0_STATUS__perr__inactive 0
-#define R_PAR0_STATUS__ack__BITNR 11
-#define R_PAR0_STATUS__ack__WIDTH 1
-#define R_PAR0_STATUS__ack__active 0
-#define R_PAR0_STATUS__ack__inactive 1
-#define R_PAR0_STATUS__busy__BITNR 10
-#define R_PAR0_STATUS__busy__WIDTH 1
-#define R_PAR0_STATUS__busy__active 1
-#define R_PAR0_STATUS__busy__inactive 0
-#define R_PAR0_STATUS__fault__BITNR 9
-#define R_PAR0_STATUS__fault__WIDTH 1
-#define R_PAR0_STATUS__fault__active 0
-#define R_PAR0_STATUS__fault__inactive 1
-#define R_PAR0_STATUS__sel__BITNR 8
-#define R_PAR0_STATUS__sel__WIDTH 1
-#define R_PAR0_STATUS__sel__active 1
-#define R_PAR0_STATUS__sel__inactive 0
-#define R_PAR0_STATUS__ext_mode__BITNR 7
-#define R_PAR0_STATUS__ext_mode__WIDTH 1
-#define R_PAR0_STATUS__ext_mode__enable 1
-#define R_PAR0_STATUS__ext_mode__disable 0
-#define R_PAR0_STATUS__ecp_16__BITNR 6
-#define R_PAR0_STATUS__ecp_16__WIDTH 1
-#define R_PAR0_STATUS__ecp_16__active 1
-#define R_PAR0_STATUS__ecp_16__inactive 0
-#define R_PAR0_STATUS__tr_rdy__BITNR 1
-#define R_PAR0_STATUS__tr_rdy__WIDTH 1
-#define R_PAR0_STATUS__tr_rdy__ready 1
-#define R_PAR0_STATUS__tr_rdy__busy 0
-#define R_PAR0_STATUS__dav__BITNR 0
-#define R_PAR0_STATUS__dav__WIDTH 1
-#define R_PAR0_STATUS__dav__data 1
-#define R_PAR0_STATUS__dav__nodata 0
-
-#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040)
-#define R_PAR_ECP16_DATA__data__BITNR 0
-#define R_PAR_ECP16_DATA__data__WIDTH 16
-
-#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_PAR0_CONFIG__ioe__BITNR 25
-#define R_PAR0_CONFIG__ioe__WIDTH 1
-#define R_PAR0_CONFIG__ioe__inv 1
-#define R_PAR0_CONFIG__ioe__noninv 0
-#define R_PAR0_CONFIG__iseli__BITNR 24
-#define R_PAR0_CONFIG__iseli__WIDTH 1
-#define R_PAR0_CONFIG__iseli__inv 1
-#define R_PAR0_CONFIG__iseli__noninv 0
-#define R_PAR0_CONFIG__iautofd__BITNR 23
-#define R_PAR0_CONFIG__iautofd__WIDTH 1
-#define R_PAR0_CONFIG__iautofd__inv 1
-#define R_PAR0_CONFIG__iautofd__noninv 0
-#define R_PAR0_CONFIG__istrb__BITNR 22
-#define R_PAR0_CONFIG__istrb__WIDTH 1
-#define R_PAR0_CONFIG__istrb__inv 1
-#define R_PAR0_CONFIG__istrb__noninv 0
-#define R_PAR0_CONFIG__iinit__BITNR 21
-#define R_PAR0_CONFIG__iinit__WIDTH 1
-#define R_PAR0_CONFIG__iinit__inv 1
-#define R_PAR0_CONFIG__iinit__noninv 0
-#define R_PAR0_CONFIG__iperr__BITNR 20
-#define R_PAR0_CONFIG__iperr__WIDTH 1
-#define R_PAR0_CONFIG__iperr__inv 1
-#define R_PAR0_CONFIG__iperr__noninv 0
-#define R_PAR0_CONFIG__iack__BITNR 19
-#define R_PAR0_CONFIG__iack__WIDTH 1
-#define R_PAR0_CONFIG__iack__inv 1
-#define R_PAR0_CONFIG__iack__noninv 0
-#define R_PAR0_CONFIG__ibusy__BITNR 18
-#define R_PAR0_CONFIG__ibusy__WIDTH 1
-#define R_PAR0_CONFIG__ibusy__inv 1
-#define R_PAR0_CONFIG__ibusy__noninv 0
-#define R_PAR0_CONFIG__ifault__BITNR 17
-#define R_PAR0_CONFIG__ifault__WIDTH 1
-#define R_PAR0_CONFIG__ifault__inv 1
-#define R_PAR0_CONFIG__ifault__noninv 0
-#define R_PAR0_CONFIG__isel__BITNR 16
-#define R_PAR0_CONFIG__isel__WIDTH 1
-#define R_PAR0_CONFIG__isel__inv 1
-#define R_PAR0_CONFIG__isel__noninv 0
-#define R_PAR0_CONFIG__ext_mode__BITNR 11
-#define R_PAR0_CONFIG__ext_mode__WIDTH 1
-#define R_PAR0_CONFIG__ext_mode__enable 1
-#define R_PAR0_CONFIG__ext_mode__disable 0
-#define R_PAR0_CONFIG__wide__BITNR 10
-#define R_PAR0_CONFIG__wide__WIDTH 1
-#define R_PAR0_CONFIG__wide__enable 1
-#define R_PAR0_CONFIG__wide__disable 0
-#define R_PAR0_CONFIG__dma__BITNR 9
-#define R_PAR0_CONFIG__dma__WIDTH 1
-#define R_PAR0_CONFIG__dma__enable 1
-#define R_PAR0_CONFIG__dma__disable 0
-#define R_PAR0_CONFIG__rle_in__BITNR 8
-#define R_PAR0_CONFIG__rle_in__WIDTH 1
-#define R_PAR0_CONFIG__rle_in__enable 1
-#define R_PAR0_CONFIG__rle_in__disable 0
-#define R_PAR0_CONFIG__rle_out__BITNR 7
-#define R_PAR0_CONFIG__rle_out__WIDTH 1
-#define R_PAR0_CONFIG__rle_out__enable 1
-#define R_PAR0_CONFIG__rle_out__disable 0
-#define R_PAR0_CONFIG__enable__BITNR 6
-#define R_PAR0_CONFIG__enable__WIDTH 1
-#define R_PAR0_CONFIG__enable__on 1
-#define R_PAR0_CONFIG__enable__reset 0
-#define R_PAR0_CONFIG__force__BITNR 5
-#define R_PAR0_CONFIG__force__WIDTH 1
-#define R_PAR0_CONFIG__force__on 1
-#define R_PAR0_CONFIG__force__off 0
-#define R_PAR0_CONFIG__ign_ack__BITNR 4
-#define R_PAR0_CONFIG__ign_ack__WIDTH 1
-#define R_PAR0_CONFIG__ign_ack__ignore 1
-#define R_PAR0_CONFIG__ign_ack__wait 0
-#define R_PAR0_CONFIG__oe_ack__BITNR 3
-#define R_PAR0_CONFIG__oe_ack__WIDTH 1
-#define R_PAR0_CONFIG__oe_ack__wait_oe 1
-#define R_PAR0_CONFIG__oe_ack__dont_wait 0
-#define R_PAR0_CONFIG__oe_ack__epp_addr 1
-#define R_PAR0_CONFIG__oe_ack__epp_data 0
-#define R_PAR0_CONFIG__epp_addr_data__BITNR 3
-#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1
-#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1
-#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0
-#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1
-#define R_PAR0_CONFIG__epp_addr_data__epp_data 0
-#define R_PAR0_CONFIG__mode__BITNR 0
-#define R_PAR0_CONFIG__mode__WIDTH 3
-#define R_PAR0_CONFIG__mode__manual 0
-#define R_PAR0_CONFIG__mode__centronics 1
-#define R_PAR0_CONFIG__mode__fastbyte 2
-#define R_PAR0_CONFIG__mode__nibble 3
-#define R_PAR0_CONFIG__mode__byte 4
-#define R_PAR0_CONFIG__mode__ecp_fwd 5
-#define R_PAR0_CONFIG__mode__ecp_rev 6
-#define R_PAR0_CONFIG__mode__off 7
-#define R_PAR0_CONFIG__mode__epp_wr1 5
-#define R_PAR0_CONFIG__mode__epp_wr2 6
-#define R_PAR0_CONFIG__mode__epp_wr3 7
-#define R_PAR0_CONFIG__mode__epp_rd 0
-
-#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048)
-#define R_PAR0_DELAY__fine_hold__BITNR 21
-#define R_PAR0_DELAY__fine_hold__WIDTH 3
-#define R_PAR0_DELAY__hold__BITNR 16
-#define R_PAR0_DELAY__hold__WIDTH 5
-#define R_PAR0_DELAY__fine_strb__BITNR 13
-#define R_PAR0_DELAY__fine_strb__WIDTH 3
-#define R_PAR0_DELAY__strobe__BITNR 8
-#define R_PAR0_DELAY__strobe__WIDTH 5
-#define R_PAR0_DELAY__fine_setup__BITNR 5
-#define R_PAR0_DELAY__fine_setup__WIDTH 3
-#define R_PAR0_DELAY__setup__BITNR 0
-#define R_PAR0_DELAY__setup__WIDTH 5
-
-#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050)
-#define R_PAR1_CTRL_DATA__peri_int__BITNR 24
-#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1
-#define R_PAR1_CTRL_DATA__peri_int__ack 1
-#define R_PAR1_CTRL_DATA__peri_int__nop 0
-#define R_PAR1_CTRL_DATA__oe__BITNR 20
-#define R_PAR1_CTRL_DATA__oe__WIDTH 1
-#define R_PAR1_CTRL_DATA__oe__enable 1
-#define R_PAR1_CTRL_DATA__oe__disable 0
-#define R_PAR1_CTRL_DATA__seli__BITNR 19
-#define R_PAR1_CTRL_DATA__seli__WIDTH 1
-#define R_PAR1_CTRL_DATA__seli__active 1
-#define R_PAR1_CTRL_DATA__seli__inactive 0
-#define R_PAR1_CTRL_DATA__autofd__BITNR 18
-#define R_PAR1_CTRL_DATA__autofd__WIDTH 1
-#define R_PAR1_CTRL_DATA__autofd__active 1
-#define R_PAR1_CTRL_DATA__autofd__inactive 0
-#define R_PAR1_CTRL_DATA__strb__BITNR 17
-#define R_PAR1_CTRL_DATA__strb__WIDTH 1
-#define R_PAR1_CTRL_DATA__strb__active 1
-#define R_PAR1_CTRL_DATA__strb__inactive 0
-#define R_PAR1_CTRL_DATA__init__BITNR 16
-#define R_PAR1_CTRL_DATA__init__WIDTH 1
-#define R_PAR1_CTRL_DATA__init__active 1
-#define R_PAR1_CTRL_DATA__init__inactive 0
-#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8
-#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1
-#define R_PAR1_CTRL_DATA__ecp_cmd__command 1
-#define R_PAR1_CTRL_DATA__ecp_cmd__data 0
-#define R_PAR1_CTRL_DATA__data__BITNR 0
-#define R_PAR1_CTRL_DATA__data__WIDTH 8
-
-#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052)
-#define R_PAR1_CTRL__ctrl__BITNR 0
-#define R_PAR1_CTRL__ctrl__WIDTH 5
-
-#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050)
-#define R_PAR1_STATUS_DATA__mode__BITNR 29
-#define R_PAR1_STATUS_DATA__mode__WIDTH 3
-#define R_PAR1_STATUS_DATA__mode__manual 0
-#define R_PAR1_STATUS_DATA__mode__centronics 1
-#define R_PAR1_STATUS_DATA__mode__fastbyte 2
-#define R_PAR1_STATUS_DATA__mode__nibble 3
-#define R_PAR1_STATUS_DATA__mode__byte 4
-#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5
-#define R_PAR1_STATUS_DATA__mode__ecp_rev 6
-#define R_PAR1_STATUS_DATA__mode__off 7
-#define R_PAR1_STATUS_DATA__mode__epp_wr1 5
-#define R_PAR1_STATUS_DATA__mode__epp_wr2 6
-#define R_PAR1_STATUS_DATA__mode__epp_wr3 7
-#define R_PAR1_STATUS_DATA__mode__epp_rd 0
-#define R_PAR1_STATUS_DATA__perr__BITNR 28
-#define R_PAR1_STATUS_DATA__perr__WIDTH 1
-#define R_PAR1_STATUS_DATA__perr__active 1
-#define R_PAR1_STATUS_DATA__perr__inactive 0
-#define R_PAR1_STATUS_DATA__ack__BITNR 27
-#define R_PAR1_STATUS_DATA__ack__WIDTH 1
-#define R_PAR1_STATUS_DATA__ack__active 0
-#define R_PAR1_STATUS_DATA__ack__inactive 1
-#define R_PAR1_STATUS_DATA__busy__BITNR 26
-#define R_PAR1_STATUS_DATA__busy__WIDTH 1
-#define R_PAR1_STATUS_DATA__busy__active 1
-#define R_PAR1_STATUS_DATA__busy__inactive 0
-#define R_PAR1_STATUS_DATA__fault__BITNR 25
-#define R_PAR1_STATUS_DATA__fault__WIDTH 1
-#define R_PAR1_STATUS_DATA__fault__active 0
-#define R_PAR1_STATUS_DATA__fault__inactive 1
-#define R_PAR1_STATUS_DATA__sel__BITNR 24
-#define R_PAR1_STATUS_DATA__sel__WIDTH 1
-#define R_PAR1_STATUS_DATA__sel__active 1
-#define R_PAR1_STATUS_DATA__sel__inactive 0
-#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
-#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1
-#define R_PAR1_STATUS_DATA__ext_mode__enable 1
-#define R_PAR1_STATUS_DATA__ext_mode__disable 0
-#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
-#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_PAR1_STATUS_DATA__tr_rdy__ready 1
-#define R_PAR1_STATUS_DATA__tr_rdy__busy 0
-#define R_PAR1_STATUS_DATA__dav__BITNR 16
-#define R_PAR1_STATUS_DATA__dav__WIDTH 1
-#define R_PAR1_STATUS_DATA__dav__data 1
-#define R_PAR1_STATUS_DATA__dav__nodata 0
-#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8
-#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1
-#define R_PAR1_STATUS_DATA__ecp_cmd__command 1
-#define R_PAR1_STATUS_DATA__ecp_cmd__data 0
-#define R_PAR1_STATUS_DATA__data__BITNR 0
-#define R_PAR1_STATUS_DATA__data__WIDTH 8
-
-#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052)
-#define R_PAR1_STATUS__mode__BITNR 13
-#define R_PAR1_STATUS__mode__WIDTH 3
-#define R_PAR1_STATUS__mode__manual 0
-#define R_PAR1_STATUS__mode__centronics 1
-#define R_PAR1_STATUS__mode__fastbyte 2
-#define R_PAR1_STATUS__mode__nibble 3
-#define R_PAR1_STATUS__mode__byte 4
-#define R_PAR1_STATUS__mode__ecp_fwd 5
-#define R_PAR1_STATUS__mode__ecp_rev 6
-#define R_PAR1_STATUS__mode__off 7
-#define R_PAR1_STATUS__mode__epp_wr1 5
-#define R_PAR1_STATUS__mode__epp_wr2 6
-#define R_PAR1_STATUS__mode__epp_wr3 7
-#define R_PAR1_STATUS__mode__epp_rd 0
-#define R_PAR1_STATUS__perr__BITNR 12
-#define R_PAR1_STATUS__perr__WIDTH 1
-#define R_PAR1_STATUS__perr__active 1
-#define R_PAR1_STATUS__perr__inactive 0
-#define R_PAR1_STATUS__ack__BITNR 11
-#define R_PAR1_STATUS__ack__WIDTH 1
-#define R_PAR1_STATUS__ack__active 0
-#define R_PAR1_STATUS__ack__inactive 1
-#define R_PAR1_STATUS__busy__BITNR 10
-#define R_PAR1_STATUS__busy__WIDTH 1
-#define R_PAR1_STATUS__busy__active 1
-#define R_PAR1_STATUS__busy__inactive 0
-#define R_PAR1_STATUS__fault__BITNR 9
-#define R_PAR1_STATUS__fault__WIDTH 1
-#define R_PAR1_STATUS__fault__active 0
-#define R_PAR1_STATUS__fault__inactive 1
-#define R_PAR1_STATUS__sel__BITNR 8
-#define R_PAR1_STATUS__sel__WIDTH 1
-#define R_PAR1_STATUS__sel__active 1
-#define R_PAR1_STATUS__sel__inactive 0
-#define R_PAR1_STATUS__ext_mode__BITNR 7
-#define R_PAR1_STATUS__ext_mode__WIDTH 1
-#define R_PAR1_STATUS__ext_mode__enable 1
-#define R_PAR1_STATUS__ext_mode__disable 0
-#define R_PAR1_STATUS__tr_rdy__BITNR 1
-#define R_PAR1_STATUS__tr_rdy__WIDTH 1
-#define R_PAR1_STATUS__tr_rdy__ready 1
-#define R_PAR1_STATUS__tr_rdy__busy 0
-#define R_PAR1_STATUS__dav__BITNR 0
-#define R_PAR1_STATUS__dav__WIDTH 1
-#define R_PAR1_STATUS__dav__data 1
-#define R_PAR1_STATUS__dav__nodata 0
-
-#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054)
-#define R_PAR1_CONFIG__ioe__BITNR 25
-#define R_PAR1_CONFIG__ioe__WIDTH 1
-#define R_PAR1_CONFIG__ioe__inv 1
-#define R_PAR1_CONFIG__ioe__noninv 0
-#define R_PAR1_CONFIG__iseli__BITNR 24
-#define R_PAR1_CONFIG__iseli__WIDTH 1
-#define R_PAR1_CONFIG__iseli__inv 1
-#define R_PAR1_CONFIG__iseli__noninv 0
-#define R_PAR1_CONFIG__iautofd__BITNR 23
-#define R_PAR1_CONFIG__iautofd__WIDTH 1
-#define R_PAR1_CONFIG__iautofd__inv 1
-#define R_PAR1_CONFIG__iautofd__noninv 0
-#define R_PAR1_CONFIG__istrb__BITNR 22
-#define R_PAR1_CONFIG__istrb__WIDTH 1
-#define R_PAR1_CONFIG__istrb__inv 1
-#define R_PAR1_CONFIG__istrb__noninv 0
-#define R_PAR1_CONFIG__iinit__BITNR 21
-#define R_PAR1_CONFIG__iinit__WIDTH 1
-#define R_PAR1_CONFIG__iinit__inv 1
-#define R_PAR1_CONFIG__iinit__noninv 0
-#define R_PAR1_CONFIG__iperr__BITNR 20
-#define R_PAR1_CONFIG__iperr__WIDTH 1
-#define R_PAR1_CONFIG__iperr__inv 1
-#define R_PAR1_CONFIG__iperr__noninv 0
-#define R_PAR1_CONFIG__iack__BITNR 19
-#define R_PAR1_CONFIG__iack__WIDTH 1
-#define R_PAR1_CONFIG__iack__inv 1
-#define R_PAR1_CONFIG__iack__noninv 0
-#define R_PAR1_CONFIG__ibusy__BITNR 18
-#define R_PAR1_CONFIG__ibusy__WIDTH 1
-#define R_PAR1_CONFIG__ibusy__inv 1
-#define R_PAR1_CONFIG__ibusy__noninv 0
-#define R_PAR1_CONFIG__ifault__BITNR 17
-#define R_PAR1_CONFIG__ifault__WIDTH 1
-#define R_PAR1_CONFIG__ifault__inv 1
-#define R_PAR1_CONFIG__ifault__noninv 0
-#define R_PAR1_CONFIG__isel__BITNR 16
-#define R_PAR1_CONFIG__isel__WIDTH 1
-#define R_PAR1_CONFIG__isel__inv 1
-#define R_PAR1_CONFIG__isel__noninv 0
-#define R_PAR1_CONFIG__ext_mode__BITNR 11
-#define R_PAR1_CONFIG__ext_mode__WIDTH 1
-#define R_PAR1_CONFIG__ext_mode__enable 1
-#define R_PAR1_CONFIG__ext_mode__disable 0
-#define R_PAR1_CONFIG__dma__BITNR 9
-#define R_PAR1_CONFIG__dma__WIDTH 1
-#define R_PAR1_CONFIG__dma__enable 1
-#define R_PAR1_CONFIG__dma__disable 0
-#define R_PAR1_CONFIG__rle_in__BITNR 8
-#define R_PAR1_CONFIG__rle_in__WIDTH 1
-#define R_PAR1_CONFIG__rle_in__enable 1
-#define R_PAR1_CONFIG__rle_in__disable 0
-#define R_PAR1_CONFIG__rle_out__BITNR 7
-#define R_PAR1_CONFIG__rle_out__WIDTH 1
-#define R_PAR1_CONFIG__rle_out__enable 1
-#define R_PAR1_CONFIG__rle_out__disable 0
-#define R_PAR1_CONFIG__enable__BITNR 6
-#define R_PAR1_CONFIG__enable__WIDTH 1
-#define R_PAR1_CONFIG__enable__on 1
-#define R_PAR1_CONFIG__enable__reset 0
-#define R_PAR1_CONFIG__force__BITNR 5
-#define R_PAR1_CONFIG__force__WIDTH 1
-#define R_PAR1_CONFIG__force__on 1
-#define R_PAR1_CONFIG__force__off 0
-#define R_PAR1_CONFIG__ign_ack__BITNR 4
-#define R_PAR1_CONFIG__ign_ack__WIDTH 1
-#define R_PAR1_CONFIG__ign_ack__ignore 1
-#define R_PAR1_CONFIG__ign_ack__wait 0
-#define R_PAR1_CONFIG__oe_ack__BITNR 3
-#define R_PAR1_CONFIG__oe_ack__WIDTH 1
-#define R_PAR1_CONFIG__oe_ack__wait_oe 1
-#define R_PAR1_CONFIG__oe_ack__dont_wait 0
-#define R_PAR1_CONFIG__oe_ack__epp_addr 1
-#define R_PAR1_CONFIG__oe_ack__epp_data 0
-#define R_PAR1_CONFIG__epp_addr_data__BITNR 3
-#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1
-#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1
-#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0
-#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1
-#define R_PAR1_CONFIG__epp_addr_data__epp_data 0
-#define R_PAR1_CONFIG__mode__BITNR 0
-#define R_PAR1_CONFIG__mode__WIDTH 3
-#define R_PAR1_CONFIG__mode__manual 0
-#define R_PAR1_CONFIG__mode__centronics 1
-#define R_PAR1_CONFIG__mode__fastbyte 2
-#define R_PAR1_CONFIG__mode__nibble 3
-#define R_PAR1_CONFIG__mode__byte 4
-#define R_PAR1_CONFIG__mode__ecp_fwd 5
-#define R_PAR1_CONFIG__mode__ecp_rev 6
-#define R_PAR1_CONFIG__mode__off 7
-#define R_PAR1_CONFIG__mode__epp_wr1 5
-#define R_PAR1_CONFIG__mode__epp_wr2 6
-#define R_PAR1_CONFIG__mode__epp_wr3 7
-#define R_PAR1_CONFIG__mode__epp_rd 0
-
-#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058)
-#define R_PAR1_DELAY__fine_hold__BITNR 21
-#define R_PAR1_DELAY__fine_hold__WIDTH 3
-#define R_PAR1_DELAY__hold__BITNR 16
-#define R_PAR1_DELAY__hold__WIDTH 5
-#define R_PAR1_DELAY__fine_strb__BITNR 13
-#define R_PAR1_DELAY__fine_strb__WIDTH 3
-#define R_PAR1_DELAY__strobe__BITNR 8
-#define R_PAR1_DELAY__strobe__WIDTH 5
-#define R_PAR1_DELAY__fine_setup__BITNR 5
-#define R_PAR1_DELAY__fine_setup__WIDTH 3
-#define R_PAR1_DELAY__setup__BITNR 0
-#define R_PAR1_DELAY__setup__WIDTH 5
-
-/*
-!* ATA interface registers
-!*/
-
-#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_ATA_CTRL_DATA__sel__BITNR 30
-#define R_ATA_CTRL_DATA__sel__WIDTH 2
-#define R_ATA_CTRL_DATA__cs1__BITNR 29
-#define R_ATA_CTRL_DATA__cs1__WIDTH 1
-#define R_ATA_CTRL_DATA__cs1__active 1
-#define R_ATA_CTRL_DATA__cs1__inactive 0
-#define R_ATA_CTRL_DATA__cs0__BITNR 28
-#define R_ATA_CTRL_DATA__cs0__WIDTH 1
-#define R_ATA_CTRL_DATA__cs0__active 1
-#define R_ATA_CTRL_DATA__cs0__inactive 0
-#define R_ATA_CTRL_DATA__addr__BITNR 25
-#define R_ATA_CTRL_DATA__addr__WIDTH 3
-#define R_ATA_CTRL_DATA__rw__BITNR 24
-#define R_ATA_CTRL_DATA__rw__WIDTH 1
-#define R_ATA_CTRL_DATA__rw__read 1
-#define R_ATA_CTRL_DATA__rw__write 0
-#define R_ATA_CTRL_DATA__src_dst__BITNR 23
-#define R_ATA_CTRL_DATA__src_dst__WIDTH 1
-#define R_ATA_CTRL_DATA__src_dst__dma 1
-#define R_ATA_CTRL_DATA__src_dst__register 0
-#define R_ATA_CTRL_DATA__handsh__BITNR 22
-#define R_ATA_CTRL_DATA__handsh__WIDTH 1
-#define R_ATA_CTRL_DATA__handsh__dma 1
-#define R_ATA_CTRL_DATA__handsh__pio 0
-#define R_ATA_CTRL_DATA__multi__BITNR 21
-#define R_ATA_CTRL_DATA__multi__WIDTH 1
-#define R_ATA_CTRL_DATA__multi__on 1
-#define R_ATA_CTRL_DATA__multi__off 0
-#define R_ATA_CTRL_DATA__dma_size__BITNR 20
-#define R_ATA_CTRL_DATA__dma_size__WIDTH 1
-#define R_ATA_CTRL_DATA__dma_size__byte 1
-#define R_ATA_CTRL_DATA__dma_size__word 0
-#define R_ATA_CTRL_DATA__data__BITNR 0
-#define R_ATA_CTRL_DATA__data__WIDTH 16
-
-#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
-#define R_ATA_STATUS_DATA__busy__BITNR 18
-#define R_ATA_STATUS_DATA__busy__WIDTH 1
-#define R_ATA_STATUS_DATA__busy__yes 1
-#define R_ATA_STATUS_DATA__busy__no 0
-#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17
-#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1
-#define R_ATA_STATUS_DATA__tr_rdy__ready 1
-#define R_ATA_STATUS_DATA__tr_rdy__busy 0
-#define R_ATA_STATUS_DATA__dav__BITNR 16
-#define R_ATA_STATUS_DATA__dav__WIDTH 1
-#define R_ATA_STATUS_DATA__dav__data 1
-#define R_ATA_STATUS_DATA__dav__nodata 0
-#define R_ATA_STATUS_DATA__data__BITNR 0
-#define R_ATA_STATUS_DATA__data__WIDTH 16
-
-#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_ATA_CONFIG__enable__BITNR 25
-#define R_ATA_CONFIG__enable__WIDTH 1
-#define R_ATA_CONFIG__enable__on 1
-#define R_ATA_CONFIG__enable__off 0
-#define R_ATA_CONFIG__dma_strobe__BITNR 20
-#define R_ATA_CONFIG__dma_strobe__WIDTH 5
-#define R_ATA_CONFIG__dma_hold__BITNR 15
-#define R_ATA_CONFIG__dma_hold__WIDTH 5
-#define R_ATA_CONFIG__pio_setup__BITNR 10
-#define R_ATA_CONFIG__pio_setup__WIDTH 5
-#define R_ATA_CONFIG__pio_strobe__BITNR 5
-#define R_ATA_CONFIG__pio_strobe__WIDTH 5
-#define R_ATA_CONFIG__pio_hold__BITNR 0
-#define R_ATA_CONFIG__pio_hold__WIDTH 5
-
-#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048)
-#define R_ATA_TRANSFER_CNT__count__BITNR 0
-#define R_ATA_TRANSFER_CNT__count__WIDTH 17
-
-/*
-!* SCSI registers
-!*/
-
-#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044)
-#define R_SCSI0_CTRL__id_type__BITNR 31
-#define R_SCSI0_CTRL__id_type__WIDTH 1
-#define R_SCSI0_CTRL__id_type__software 1
-#define R_SCSI0_CTRL__id_type__hardware 0
-#define R_SCSI0_CTRL__sel_timeout__BITNR 24
-#define R_SCSI0_CTRL__sel_timeout__WIDTH 7
-#define R_SCSI0_CTRL__synch_per__BITNR 16
-#define R_SCSI0_CTRL__synch_per__WIDTH 8
-#define R_SCSI0_CTRL__rst__BITNR 15
-#define R_SCSI0_CTRL__rst__WIDTH 1
-#define R_SCSI0_CTRL__rst__yes 1
-#define R_SCSI0_CTRL__rst__no 0
-#define R_SCSI0_CTRL__atn__BITNR 14
-#define R_SCSI0_CTRL__atn__WIDTH 1
-#define R_SCSI0_CTRL__atn__yes 1
-#define R_SCSI0_CTRL__atn__no 0
-#define R_SCSI0_CTRL__my_id__BITNR 9
-#define R_SCSI0_CTRL__my_id__WIDTH 4
-#define R_SCSI0_CTRL__target_id__BITNR 4
-#define R_SCSI0_CTRL__target_id__WIDTH 4
-#define R_SCSI0_CTRL__fast_20__BITNR 3
-#define R_SCSI0_CTRL__fast_20__WIDTH 1
-#define R_SCSI0_CTRL__fast_20__yes 1
-#define R_SCSI0_CTRL__fast_20__no 0
-#define R_SCSI0_CTRL__bus_width__BITNR 2
-#define R_SCSI0_CTRL__bus_width__WIDTH 1
-#define R_SCSI0_CTRL__bus_width__wide 1
-#define R_SCSI0_CTRL__bus_width__narrow 0
-#define R_SCSI0_CTRL__synch__BITNR 1
-#define R_SCSI0_CTRL__synch__WIDTH 1
-#define R_SCSI0_CTRL__synch__synch 1
-#define R_SCSI0_CTRL__synch__asynch 0
-#define R_SCSI0_CTRL__enable__BITNR 0
-#define R_SCSI0_CTRL__enable__WIDTH 1
-#define R_SCSI0_CTRL__enable__on 1
-#define R_SCSI0_CTRL__enable__off 0
-
-#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040)
-#define R_SCSI0_CMD_DATA__parity_in__BITNR 26
-#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1
-#define R_SCSI0_CMD_DATA__parity_in__on 0
-#define R_SCSI0_CMD_DATA__parity_in__off 1
-#define R_SCSI0_CMD_DATA__skip__BITNR 25
-#define R_SCSI0_CMD_DATA__skip__WIDTH 1
-#define R_SCSI0_CMD_DATA__skip__on 1
-#define R_SCSI0_CMD_DATA__skip__off 0
-#define R_SCSI0_CMD_DATA__clr_status__BITNR 24
-#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1
-#define R_SCSI0_CMD_DATA__clr_status__yes 1
-#define R_SCSI0_CMD_DATA__clr_status__nop 0
-#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20
-#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4
-#define R_SCSI0_CMD_DATA__command__BITNR 16
-#define R_SCSI0_CMD_DATA__command__WIDTH 4
-#define R_SCSI0_CMD_DATA__command__full_din_1 0
-#define R_SCSI0_CMD_DATA__command__full_dout_1 1
-#define R_SCSI0_CMD_DATA__command__full_stat_1 2
-#define R_SCSI0_CMD_DATA__command__resel_din 3
-#define R_SCSI0_CMD_DATA__command__resel_dout 4
-#define R_SCSI0_CMD_DATA__command__resel_stat 5
-#define R_SCSI0_CMD_DATA__command__arb_only 6
-#define R_SCSI0_CMD_DATA__command__full_din_3 8
-#define R_SCSI0_CMD_DATA__command__full_dout_3 9
-#define R_SCSI0_CMD_DATA__command__full_stat_3 10
-#define R_SCSI0_CMD_DATA__command__man_data_in 11
-#define R_SCSI0_CMD_DATA__command__man_data_out 12
-#define R_SCSI0_CMD_DATA__command__man_rat 13
-#define R_SCSI0_CMD_DATA__data_out__BITNR 0
-#define R_SCSI0_CMD_DATA__data_out__WIDTH 16
-
-#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040)
-#define R_SCSI0_DATA__data_out__BITNR 0
-#define R_SCSI0_DATA__data_out__WIDTH 16
-
-#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042)
-#define R_SCSI0_CMD__asynch_setup__BITNR 4
-#define R_SCSI0_CMD__asynch_setup__WIDTH 4
-#define R_SCSI0_CMD__command__BITNR 0
-#define R_SCSI0_CMD__command__WIDTH 4
-#define R_SCSI0_CMD__command__full_din_1 0
-#define R_SCSI0_CMD__command__full_dout_1 1
-#define R_SCSI0_CMD__command__full_stat_1 2
-#define R_SCSI0_CMD__command__resel_din 3
-#define R_SCSI0_CMD__command__resel_dout 4
-#define R_SCSI0_CMD__command__resel_stat 5
-#define R_SCSI0_CMD__command__arb_only 6
-#define R_SCSI0_CMD__command__full_din_3 8
-#define R_SCSI0_CMD__command__full_dout_3 9
-#define R_SCSI0_CMD__command__full_stat_3 10
-#define R_SCSI0_CMD__command__man_data_in 11
-#define R_SCSI0_CMD__command__man_data_out 12
-#define R_SCSI0_CMD__command__man_rat 13
-
-#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043)
-#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2
-#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__parity_in__on 0
-#define R_SCSI0_STATUS_CTRL__parity_in__off 1
-#define R_SCSI0_STATUS_CTRL__skip__BITNR 1
-#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__skip__on 1
-#define R_SCSI0_STATUS_CTRL__skip__off 0
-#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0
-#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1
-#define R_SCSI0_STATUS_CTRL__clr_status__yes 1
-#define R_SCSI0_STATUS_CTRL__clr_status__nop 0
-
-#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048)
-#define R_SCSI0_STATUS__tst_arb_won__BITNR 23
-#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1
-#define R_SCSI0_STATUS__tst_resel__BITNR 22
-#define R_SCSI0_STATUS__tst_resel__WIDTH 1
-#define R_SCSI0_STATUS__parity_error__BITNR 21
-#define R_SCSI0_STATUS__parity_error__WIDTH 1
-#define R_SCSI0_STATUS__bus_reset__BITNR 20
-#define R_SCSI0_STATUS__bus_reset__WIDTH 1
-#define R_SCSI0_STATUS__bus_reset__yes 1
-#define R_SCSI0_STATUS__bus_reset__no 0
-#define R_SCSI0_STATUS__resel_target__BITNR 15
-#define R_SCSI0_STATUS__resel_target__WIDTH 4
-#define R_SCSI0_STATUS__resel__BITNR 14
-#define R_SCSI0_STATUS__resel__WIDTH 1
-#define R_SCSI0_STATUS__resel__yes 1
-#define R_SCSI0_STATUS__resel__no 0
-#define R_SCSI0_STATUS__curr_phase__BITNR 11
-#define R_SCSI0_STATUS__curr_phase__WIDTH 3
-#define R_SCSI0_STATUS__curr_phase__ph_undef 0
-#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7
-#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6
-#define R_SCSI0_STATUS__curr_phase__ph_status 3
-#define R_SCSI0_STATUS__curr_phase__ph_command 2
-#define R_SCSI0_STATUS__curr_phase__ph_data_in 5
-#define R_SCSI0_STATUS__curr_phase__ph_data_out 4
-#define R_SCSI0_STATUS__curr_phase__ph_resel 1
-#define R_SCSI0_STATUS__last_seq_step__BITNR 6
-#define R_SCSI0_STATUS__last_seq_step__WIDTH 5
-#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24
-#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8
-#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29
-#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2
-#define R_SCSI0_STATUS__last_seq_step__st_manual 28
-#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30
-#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6
-#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22
-#define R_SCSI0_STATUS__last_seq_step__st_answer 3
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1
-#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15
-#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9
-#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12
-#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5
-#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11
-#define R_SCSI0_STATUS__last_seq_step__st_iwr 27
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21
-#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7
-#define R_SCSI0_STATUS__last_seq_step__st_cc 31
-#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14
-#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20
-#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16
-#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10
-#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18
-#define R_SCSI0_STATUS__valid_status__BITNR 5
-#define R_SCSI0_STATUS__valid_status__WIDTH 1
-#define R_SCSI0_STATUS__valid_status__yes 1
-#define R_SCSI0_STATUS__valid_status__no 0
-#define R_SCSI0_STATUS__seq_status__BITNR 0
-#define R_SCSI0_STATUS__seq_status__WIDTH 5
-#define R_SCSI0_STATUS__seq_status__info_seq_complete 0
-#define R_SCSI0_STATUS__seq_status__info_parity_error 1
-#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2
-#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3
-#define R_SCSI0_STATUS__seq_status__info_arb_lost 4
-#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5
-#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6
-#define R_SCSI0_STATUS__seq_status__info_illegal_op 7
-#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8
-#define R_SCSI0_STATUS__seq_status__info_reselected 9
-#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10
-#define R_SCSI0_STATUS__seq_status__info_bus_reset 11
-#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12
-#define R_SCSI0_STATUS__seq_status__info_bus_free 13
-
-#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040)
-#define R_SCSI0_DATA_IN__data_in__BITNR 0
-#define R_SCSI0_DATA_IN__data_in__WIDTH 16
-
-#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054)
-#define R_SCSI1_CTRL__id_type__BITNR 31
-#define R_SCSI1_CTRL__id_type__WIDTH 1
-#define R_SCSI1_CTRL__id_type__software 1
-#define R_SCSI1_CTRL__id_type__hardware 0
-#define R_SCSI1_CTRL__sel_timeout__BITNR 24
-#define R_SCSI1_CTRL__sel_timeout__WIDTH 7
-#define R_SCSI1_CTRL__synch_per__BITNR 16
-#define R_SCSI1_CTRL__synch_per__WIDTH 8
-#define R_SCSI1_CTRL__rst__BITNR 15
-#define R_SCSI1_CTRL__rst__WIDTH 1
-#define R_SCSI1_CTRL__rst__yes 1
-#define R_SCSI1_CTRL__rst__no 0
-#define R_SCSI1_CTRL__atn__BITNR 14
-#define R_SCSI1_CTRL__atn__WIDTH 1
-#define R_SCSI1_CTRL__atn__yes 1
-#define R_SCSI1_CTRL__atn__no 0
-#define R_SCSI1_CTRL__my_id__BITNR 9
-#define R_SCSI1_CTRL__my_id__WIDTH 4
-#define R_SCSI1_CTRL__target_id__BITNR 4
-#define R_SCSI1_CTRL__target_id__WIDTH 4
-#define R_SCSI1_CTRL__fast_20__BITNR 3
-#define R_SCSI1_CTRL__fast_20__WIDTH 1
-#define R_SCSI1_CTRL__fast_20__yes 1
-#define R_SCSI1_CTRL__fast_20__no 0
-#define R_SCSI1_CTRL__bus_width__BITNR 2
-#define R_SCSI1_CTRL__bus_width__WIDTH 1
-#define R_SCSI1_CTRL__bus_width__wide 1
-#define R_SCSI1_CTRL__bus_width__narrow 0
-#define R_SCSI1_CTRL__synch__BITNR 1
-#define R_SCSI1_CTRL__synch__WIDTH 1
-#define R_SCSI1_CTRL__synch__synch 1
-#define R_SCSI1_CTRL__synch__asynch 0
-#define R_SCSI1_CTRL__enable__BITNR 0
-#define R_SCSI1_CTRL__enable__WIDTH 1
-#define R_SCSI1_CTRL__enable__on 1
-#define R_SCSI1_CTRL__enable__off 0
-
-#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050)
-#define R_SCSI1_CMD_DATA__parity_in__BITNR 26
-#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1
-#define R_SCSI1_CMD_DATA__parity_in__on 0
-#define R_SCSI1_CMD_DATA__parity_in__off 1
-#define R_SCSI1_CMD_DATA__skip__BITNR 25
-#define R_SCSI1_CMD_DATA__skip__WIDTH 1
-#define R_SCSI1_CMD_DATA__skip__on 1
-#define R_SCSI1_CMD_DATA__skip__off 0
-#define R_SCSI1_CMD_DATA__clr_status__BITNR 24
-#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1
-#define R_SCSI1_CMD_DATA__clr_status__yes 1
-#define R_SCSI1_CMD_DATA__clr_status__nop 0
-#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20
-#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4
-#define R_SCSI1_CMD_DATA__command__BITNR 16
-#define R_SCSI1_CMD_DATA__command__WIDTH 4
-#define R_SCSI1_CMD_DATA__command__full_din_1 0
-#define R_SCSI1_CMD_DATA__command__full_dout_1 1
-#define R_SCSI1_CMD_DATA__command__full_stat_1 2
-#define R_SCSI1_CMD_DATA__command__resel_din 3
-#define R_SCSI1_CMD_DATA__command__resel_dout 4
-#define R_SCSI1_CMD_DATA__command__resel_stat 5
-#define R_SCSI1_CMD_DATA__command__arb_only 6
-#define R_SCSI1_CMD_DATA__command__full_din_3 8
-#define R_SCSI1_CMD_DATA__command__full_dout_3 9
-#define R_SCSI1_CMD_DATA__command__full_stat_3 10
-#define R_SCSI1_CMD_DATA__command__man_data_in 11
-#define R_SCSI1_CMD_DATA__command__man_data_out 12
-#define R_SCSI1_CMD_DATA__command__man_rat 13
-#define R_SCSI1_CMD_DATA__data_out__BITNR 0
-#define R_SCSI1_CMD_DATA__data_out__WIDTH 16
-
-#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050)
-#define R_SCSI1_DATA__data_out__BITNR 0
-#define R_SCSI1_DATA__data_out__WIDTH 16
-
-#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052)
-#define R_SCSI1_CMD__asynch_setup__BITNR 4
-#define R_SCSI1_CMD__asynch_setup__WIDTH 4
-#define R_SCSI1_CMD__command__BITNR 0
-#define R_SCSI1_CMD__command__WIDTH 4
-#define R_SCSI1_CMD__command__full_din_1 0
-#define R_SCSI1_CMD__command__full_dout_1 1
-#define R_SCSI1_CMD__command__full_stat_1 2
-#define R_SCSI1_CMD__command__resel_din 3
-#define R_SCSI1_CMD__command__resel_dout 4
-#define R_SCSI1_CMD__command__resel_stat 5
-#define R_SCSI1_CMD__command__arb_only 6
-#define R_SCSI1_CMD__command__full_din_3 8
-#define R_SCSI1_CMD__command__full_dout_3 9
-#define R_SCSI1_CMD__command__full_stat_3 10
-#define R_SCSI1_CMD__command__man_data_in 11
-#define R_SCSI1_CMD__command__man_data_out 12
-#define R_SCSI1_CMD__command__man_rat 13
-
-#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053)
-#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2
-#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__parity_in__on 0
-#define R_SCSI1_STATUS_CTRL__parity_in__off 1
-#define R_SCSI1_STATUS_CTRL__skip__BITNR 1
-#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__skip__on 1
-#define R_SCSI1_STATUS_CTRL__skip__off 0
-#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0
-#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1
-#define R_SCSI1_STATUS_CTRL__clr_status__yes 1
-#define R_SCSI1_STATUS_CTRL__clr_status__nop 0
-
-#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058)
-#define R_SCSI1_STATUS__tst_arb_won__BITNR 23
-#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1
-#define R_SCSI1_STATUS__tst_resel__BITNR 22
-#define R_SCSI1_STATUS__tst_resel__WIDTH 1
-#define R_SCSI1_STATUS__parity_error__BITNR 21
-#define R_SCSI1_STATUS__parity_error__WIDTH 1
-#define R_SCSI1_STATUS__bus_reset__BITNR 20
-#define R_SCSI1_STATUS__bus_reset__WIDTH 1
-#define R_SCSI1_STATUS__bus_reset__yes 1
-#define R_SCSI1_STATUS__bus_reset__no 0
-#define R_SCSI1_STATUS__resel_target__BITNR 15
-#define R_SCSI1_STATUS__resel_target__WIDTH 4
-#define R_SCSI1_STATUS__resel__BITNR 14
-#define R_SCSI1_STATUS__resel__WIDTH 1
-#define R_SCSI1_STATUS__resel__yes 1
-#define R_SCSI1_STATUS__resel__no 0
-#define R_SCSI1_STATUS__curr_phase__BITNR 11
-#define R_SCSI1_STATUS__curr_phase__WIDTH 3
-#define R_SCSI1_STATUS__curr_phase__ph_undef 0
-#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7
-#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6
-#define R_SCSI1_STATUS__curr_phase__ph_status 3
-#define R_SCSI1_STATUS__curr_phase__ph_command 2
-#define R_SCSI1_STATUS__curr_phase__ph_data_in 5
-#define R_SCSI1_STATUS__curr_phase__ph_data_out 4
-#define R_SCSI1_STATUS__curr_phase__ph_resel 1
-#define R_SCSI1_STATUS__last_seq_step__BITNR 6
-#define R_SCSI1_STATUS__last_seq_step__WIDTH 5
-#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24
-#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8
-#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29
-#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2
-#define R_SCSI1_STATUS__last_seq_step__st_manual 28
-#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30
-#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6
-#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22
-#define R_SCSI1_STATUS__last_seq_step__st_answer 3
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1
-#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15
-#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9
-#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12
-#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5
-#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11
-#define R_SCSI1_STATUS__last_seq_step__st_iwr 27
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21
-#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7
-#define R_SCSI1_STATUS__last_seq_step__st_cc 31
-#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14
-#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20
-#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16
-#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10
-#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18
-#define R_SCSI1_STATUS__valid_status__BITNR 5
-#define R_SCSI1_STATUS__valid_status__WIDTH 1
-#define R_SCSI1_STATUS__valid_status__yes 1
-#define R_SCSI1_STATUS__valid_status__no 0
-#define R_SCSI1_STATUS__seq_status__BITNR 0
-#define R_SCSI1_STATUS__seq_status__WIDTH 5
-#define R_SCSI1_STATUS__seq_status__info_seq_complete 0
-#define R_SCSI1_STATUS__seq_status__info_parity_error 1
-#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2
-#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3
-#define R_SCSI1_STATUS__seq_status__info_arb_lost 4
-#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5
-#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6
-#define R_SCSI1_STATUS__seq_status__info_illegal_op 7
-#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8
-#define R_SCSI1_STATUS__seq_status__info_reselected 9
-#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10
-#define R_SCSI1_STATUS__seq_status__info_bus_reset 11
-#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12
-#define R_SCSI1_STATUS__seq_status__info_bus_free 13
-
-#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050)
-#define R_SCSI1_DATA_IN__data_in__BITNR 0
-#define R_SCSI1_DATA_IN__data_in__WIDTH 16
-
-/*
-!* Interrupt mask and status registers
-!*/
-
-#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0)
-#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_RD__nmi_pin__active 1
-#define R_IRQ_MASK0_RD__nmi_pin__inactive 0
-#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_RD__watchdog_nmi__active 1
-#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0
-#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_RD__sqe_test_error__active 1
-#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0
-#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_RD__carrier_loss__active 1
-#define R_IRQ_MASK0_RD__carrier_loss__inactive 0
-#define R_IRQ_MASK0_RD__deferred__BITNR 27
-#define R_IRQ_MASK0_RD__deferred__WIDTH 1
-#define R_IRQ_MASK0_RD__deferred__active 1
-#define R_IRQ_MASK0_RD__deferred__inactive 0
-#define R_IRQ_MASK0_RD__late_col__BITNR 26
-#define R_IRQ_MASK0_RD__late_col__WIDTH 1
-#define R_IRQ_MASK0_RD__late_col__active 1
-#define R_IRQ_MASK0_RD__late_col__inactive 0
-#define R_IRQ_MASK0_RD__multiple_col__BITNR 25
-#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_RD__multiple_col__active 1
-#define R_IRQ_MASK0_RD__multiple_col__inactive 0
-#define R_IRQ_MASK0_RD__single_col__BITNR 24
-#define R_IRQ_MASK0_RD__single_col__WIDTH 1
-#define R_IRQ_MASK0_RD__single_col__active 1
-#define R_IRQ_MASK0_RD__single_col__inactive 0
-#define R_IRQ_MASK0_RD__congestion__BITNR 23
-#define R_IRQ_MASK0_RD__congestion__WIDTH 1
-#define R_IRQ_MASK0_RD__congestion__active 1
-#define R_IRQ_MASK0_RD__congestion__inactive 0
-#define R_IRQ_MASK0_RD__oversize__BITNR 22
-#define R_IRQ_MASK0_RD__oversize__WIDTH 1
-#define R_IRQ_MASK0_RD__oversize__active 1
-#define R_IRQ_MASK0_RD__oversize__inactive 0
-#define R_IRQ_MASK0_RD__alignment_error__BITNR 21
-#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_RD__alignment_error__active 1
-#define R_IRQ_MASK0_RD__alignment_error__inactive 0
-#define R_IRQ_MASK0_RD__crc_error__BITNR 20
-#define R_IRQ_MASK0_RD__crc_error__WIDTH 1
-#define R_IRQ_MASK0_RD__crc_error__active 1
-#define R_IRQ_MASK0_RD__crc_error__inactive 0
-#define R_IRQ_MASK0_RD__overrun__BITNR 19
-#define R_IRQ_MASK0_RD__overrun__WIDTH 1
-#define R_IRQ_MASK0_RD__overrun__active 1
-#define R_IRQ_MASK0_RD__overrun__inactive 0
-#define R_IRQ_MASK0_RD__underrun__BITNR 18
-#define R_IRQ_MASK0_RD__underrun__WIDTH 1
-#define R_IRQ_MASK0_RD__underrun__active 1
-#define R_IRQ_MASK0_RD__underrun__inactive 0
-#define R_IRQ_MASK0_RD__excessive_col__BITNR 17
-#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_RD__excessive_col__active 1
-#define R_IRQ_MASK0_RD__excessive_col__inactive 0
-#define R_IRQ_MASK0_RD__mdio__BITNR 16
-#define R_IRQ_MASK0_RD__mdio__WIDTH 1
-#define R_IRQ_MASK0_RD__mdio__active 1
-#define R_IRQ_MASK0_RD__mdio__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq3__active 1
-#define R_IRQ_MASK0_RD__ata_drq3__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq2__active 1
-#define R_IRQ_MASK0_RD__ata_drq2__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq1__active 1
-#define R_IRQ_MASK0_RD__ata_drq1__inactive 0
-#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_drq0__active 1
-#define R_IRQ_MASK0_RD__ata_drq0__inactive 0
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1
-#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq3__active 1
-#define R_IRQ_MASK0_RD__ata_irq3__inactive 0
-#define R_IRQ_MASK0_RD__par0_peri__BITNR 10
-#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_peri__active 1
-#define R_IRQ_MASK0_RD__par0_peri__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq2__active 1
-#define R_IRQ_MASK0_RD__ata_irq2__inactive 0
-#define R_IRQ_MASK0_RD__par0_data__BITNR 9
-#define R_IRQ_MASK0_RD__par0_data__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_data__active 1
-#define R_IRQ_MASK0_RD__par0_data__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq1__active 1
-#define R_IRQ_MASK0_RD__ata_irq1__inactive 0
-#define R_IRQ_MASK0_RD__par0_ready__BITNR 8
-#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_RD__par0_ready__active 1
-#define R_IRQ_MASK0_RD__par0_ready__inactive 0
-#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_irq0__active 1
-#define R_IRQ_MASK0_RD__ata_irq0__inactive 0
-#define R_IRQ_MASK0_RD__mio__BITNR 8
-#define R_IRQ_MASK0_RD__mio__WIDTH 1
-#define R_IRQ_MASK0_RD__mio__active 1
-#define R_IRQ_MASK0_RD__mio__inactive 0
-#define R_IRQ_MASK0_RD__scsi0__BITNR 8
-#define R_IRQ_MASK0_RD__scsi0__WIDTH 1
-#define R_IRQ_MASK0_RD__scsi0__active 1
-#define R_IRQ_MASK0_RD__scsi0__inactive 0
-#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_RD__ata_dmaend__active 1
-#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1
-#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1
-#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0
-#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_RD__ext_dma1__active 1
-#define R_IRQ_MASK0_RD__ext_dma1__inactive 0
-#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_RD__ext_dma0__active 1
-#define R_IRQ_MASK0_RD__ext_dma0__inactive 0
-#define R_IRQ_MASK0_RD__timer1__BITNR 1
-#define R_IRQ_MASK0_RD__timer1__WIDTH 1
-#define R_IRQ_MASK0_RD__timer1__active 1
-#define R_IRQ_MASK0_RD__timer1__inactive 0
-#define R_IRQ_MASK0_RD__timer0__BITNR 0
-#define R_IRQ_MASK0_RD__timer0__WIDTH 1
-#define R_IRQ_MASK0_RD__timer0__active 1
-#define R_IRQ_MASK0_RD__timer0__inactive 0
-
-#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0)
-#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_CLR__nmi_pin__clr 1
-#define R_IRQ_MASK0_CLR__nmi_pin__nop 0
-#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1
-#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0
-#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1
-#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0
-#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_CLR__carrier_loss__clr 1
-#define R_IRQ_MASK0_CLR__carrier_loss__nop 0
-#define R_IRQ_MASK0_CLR__deferred__BITNR 27
-#define R_IRQ_MASK0_CLR__deferred__WIDTH 1
-#define R_IRQ_MASK0_CLR__deferred__clr 1
-#define R_IRQ_MASK0_CLR__deferred__nop 0
-#define R_IRQ_MASK0_CLR__late_col__BITNR 26
-#define R_IRQ_MASK0_CLR__late_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__late_col__clr 1
-#define R_IRQ_MASK0_CLR__late_col__nop 0
-#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25
-#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__multiple_col__clr 1
-#define R_IRQ_MASK0_CLR__multiple_col__nop 0
-#define R_IRQ_MASK0_CLR__single_col__BITNR 24
-#define R_IRQ_MASK0_CLR__single_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__single_col__clr 1
-#define R_IRQ_MASK0_CLR__single_col__nop 0
-#define R_IRQ_MASK0_CLR__congestion__BITNR 23
-#define R_IRQ_MASK0_CLR__congestion__WIDTH 1
-#define R_IRQ_MASK0_CLR__congestion__clr 1
-#define R_IRQ_MASK0_CLR__congestion__nop 0
-#define R_IRQ_MASK0_CLR__oversize__BITNR 22
-#define R_IRQ_MASK0_CLR__oversize__WIDTH 1
-#define R_IRQ_MASK0_CLR__oversize__clr 1
-#define R_IRQ_MASK0_CLR__oversize__nop 0
-#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21
-#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__alignment_error__clr 1
-#define R_IRQ_MASK0_CLR__alignment_error__nop 0
-#define R_IRQ_MASK0_CLR__crc_error__BITNR 20
-#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1
-#define R_IRQ_MASK0_CLR__crc_error__clr 1
-#define R_IRQ_MASK0_CLR__crc_error__nop 0
-#define R_IRQ_MASK0_CLR__overrun__BITNR 19
-#define R_IRQ_MASK0_CLR__overrun__WIDTH 1
-#define R_IRQ_MASK0_CLR__overrun__clr 1
-#define R_IRQ_MASK0_CLR__overrun__nop 0
-#define R_IRQ_MASK0_CLR__underrun__BITNR 18
-#define R_IRQ_MASK0_CLR__underrun__WIDTH 1
-#define R_IRQ_MASK0_CLR__underrun__clr 1
-#define R_IRQ_MASK0_CLR__underrun__nop 0
-#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17
-#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_CLR__excessive_col__clr 1
-#define R_IRQ_MASK0_CLR__excessive_col__nop 0
-#define R_IRQ_MASK0_CLR__mdio__BITNR 16
-#define R_IRQ_MASK0_CLR__mdio__WIDTH 1
-#define R_IRQ_MASK0_CLR__mdio__clr 1
-#define R_IRQ_MASK0_CLR__mdio__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq3__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq3__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq2__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq2__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq1__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq1__nop 0
-#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_drq0__clr 1
-#define R_IRQ_MASK0_CLR__ata_drq0__nop 0
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1
-#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq3__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq3__nop 0
-#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10
-#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_peri__clr 1
-#define R_IRQ_MASK0_CLR__par0_peri__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq2__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq2__nop 0
-#define R_IRQ_MASK0_CLR__par0_data__BITNR 9
-#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_data__clr 1
-#define R_IRQ_MASK0_CLR__par0_data__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq1__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq1__nop 0
-#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
-#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_CLR__par0_ready__clr 1
-#define R_IRQ_MASK0_CLR__par0_ready__nop 0
-#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_irq0__clr 1
-#define R_IRQ_MASK0_CLR__ata_irq0__nop 0
-#define R_IRQ_MASK0_CLR__mio__BITNR 8
-#define R_IRQ_MASK0_CLR__mio__WIDTH 1
-#define R_IRQ_MASK0_CLR__mio__clr 1
-#define R_IRQ_MASK0_CLR__mio__nop 0
-#define R_IRQ_MASK0_CLR__scsi0__BITNR 8
-#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1
-#define R_IRQ_MASK0_CLR__scsi0__clr 1
-#define R_IRQ_MASK0_CLR__scsi0__nop 0
-#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1
-#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1
-#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1
-#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0
-#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_CLR__ext_dma1__clr 1
-#define R_IRQ_MASK0_CLR__ext_dma1__nop 0
-#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_CLR__ext_dma0__clr 1
-#define R_IRQ_MASK0_CLR__ext_dma0__nop 0
-#define R_IRQ_MASK0_CLR__timer1__BITNR 1
-#define R_IRQ_MASK0_CLR__timer1__WIDTH 1
-#define R_IRQ_MASK0_CLR__timer1__clr 1
-#define R_IRQ_MASK0_CLR__timer1__nop 0
-#define R_IRQ_MASK0_CLR__timer0__BITNR 0
-#define R_IRQ_MASK0_CLR__timer0__WIDTH 1
-#define R_IRQ_MASK0_CLR__timer0__clr 1
-#define R_IRQ_MASK0_CLR__timer0__nop 0
-
-#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4)
-#define R_IRQ_READ0__nmi_pin__BITNR 31
-#define R_IRQ_READ0__nmi_pin__WIDTH 1
-#define R_IRQ_READ0__nmi_pin__active 1
-#define R_IRQ_READ0__nmi_pin__inactive 0
-#define R_IRQ_READ0__watchdog_nmi__BITNR 30
-#define R_IRQ_READ0__watchdog_nmi__WIDTH 1
-#define R_IRQ_READ0__watchdog_nmi__active 1
-#define R_IRQ_READ0__watchdog_nmi__inactive 0
-#define R_IRQ_READ0__sqe_test_error__BITNR 29
-#define R_IRQ_READ0__sqe_test_error__WIDTH 1
-#define R_IRQ_READ0__sqe_test_error__active 1
-#define R_IRQ_READ0__sqe_test_error__inactive 0
-#define R_IRQ_READ0__carrier_loss__BITNR 28
-#define R_IRQ_READ0__carrier_loss__WIDTH 1
-#define R_IRQ_READ0__carrier_loss__active 1
-#define R_IRQ_READ0__carrier_loss__inactive 0
-#define R_IRQ_READ0__deferred__BITNR 27
-#define R_IRQ_READ0__deferred__WIDTH 1
-#define R_IRQ_READ0__deferred__active 1
-#define R_IRQ_READ0__deferred__inactive 0
-#define R_IRQ_READ0__late_col__BITNR 26
-#define R_IRQ_READ0__late_col__WIDTH 1
-#define R_IRQ_READ0__late_col__active 1
-#define R_IRQ_READ0__late_col__inactive 0
-#define R_IRQ_READ0__multiple_col__BITNR 25
-#define R_IRQ_READ0__multiple_col__WIDTH 1
-#define R_IRQ_READ0__multiple_col__active 1
-#define R_IRQ_READ0__multiple_col__inactive 0
-#define R_IRQ_READ0__single_col__BITNR 24
-#define R_IRQ_READ0__single_col__WIDTH 1
-#define R_IRQ_READ0__single_col__active 1
-#define R_IRQ_READ0__single_col__inactive 0
-#define R_IRQ_READ0__congestion__BITNR 23
-#define R_IRQ_READ0__congestion__WIDTH 1
-#define R_IRQ_READ0__congestion__active 1
-#define R_IRQ_READ0__congestion__inactive 0
-#define R_IRQ_READ0__oversize__BITNR 22
-#define R_IRQ_READ0__oversize__WIDTH 1
-#define R_IRQ_READ0__oversize__active 1
-#define R_IRQ_READ0__oversize__inactive 0
-#define R_IRQ_READ0__alignment_error__BITNR 21
-#define R_IRQ_READ0__alignment_error__WIDTH 1
-#define R_IRQ_READ0__alignment_error__active 1
-#define R_IRQ_READ0__alignment_error__inactive 0
-#define R_IRQ_READ0__crc_error__BITNR 20
-#define R_IRQ_READ0__crc_error__WIDTH 1
-#define R_IRQ_READ0__crc_error__active 1
-#define R_IRQ_READ0__crc_error__inactive 0
-#define R_IRQ_READ0__overrun__BITNR 19
-#define R_IRQ_READ0__overrun__WIDTH 1
-#define R_IRQ_READ0__overrun__active 1
-#define R_IRQ_READ0__overrun__inactive 0
-#define R_IRQ_READ0__underrun__BITNR 18
-#define R_IRQ_READ0__underrun__WIDTH 1
-#define R_IRQ_READ0__underrun__active 1
-#define R_IRQ_READ0__underrun__inactive 0
-#define R_IRQ_READ0__excessive_col__BITNR 17
-#define R_IRQ_READ0__excessive_col__WIDTH 1
-#define R_IRQ_READ0__excessive_col__active 1
-#define R_IRQ_READ0__excessive_col__inactive 0
-#define R_IRQ_READ0__mdio__BITNR 16
-#define R_IRQ_READ0__mdio__WIDTH 1
-#define R_IRQ_READ0__mdio__active 1
-#define R_IRQ_READ0__mdio__inactive 0
-#define R_IRQ_READ0__ata_drq3__BITNR 15
-#define R_IRQ_READ0__ata_drq3__WIDTH 1
-#define R_IRQ_READ0__ata_drq3__active 1
-#define R_IRQ_READ0__ata_drq3__inactive 0
-#define R_IRQ_READ0__ata_drq2__BITNR 14
-#define R_IRQ_READ0__ata_drq2__WIDTH 1
-#define R_IRQ_READ0__ata_drq2__active 1
-#define R_IRQ_READ0__ata_drq2__inactive 0
-#define R_IRQ_READ0__ata_drq1__BITNR 13
-#define R_IRQ_READ0__ata_drq1__WIDTH 1
-#define R_IRQ_READ0__ata_drq1__active 1
-#define R_IRQ_READ0__ata_drq1__inactive 0
-#define R_IRQ_READ0__ata_drq0__BITNR 12
-#define R_IRQ_READ0__ata_drq0__WIDTH 1
-#define R_IRQ_READ0__ata_drq0__active 1
-#define R_IRQ_READ0__ata_drq0__inactive 0
-#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11
-#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_READ0__par0_ecp_cmd__active 1
-#define R_IRQ_READ0__par0_ecp_cmd__inactive 0
-#define R_IRQ_READ0__ata_irq3__BITNR 11
-#define R_IRQ_READ0__ata_irq3__WIDTH 1
-#define R_IRQ_READ0__ata_irq3__active 1
-#define R_IRQ_READ0__ata_irq3__inactive 0
-#define R_IRQ_READ0__par0_peri__BITNR 10
-#define R_IRQ_READ0__par0_peri__WIDTH 1
-#define R_IRQ_READ0__par0_peri__active 1
-#define R_IRQ_READ0__par0_peri__inactive 0
-#define R_IRQ_READ0__ata_irq2__BITNR 10
-#define R_IRQ_READ0__ata_irq2__WIDTH 1
-#define R_IRQ_READ0__ata_irq2__active 1
-#define R_IRQ_READ0__ata_irq2__inactive 0
-#define R_IRQ_READ0__par0_data__BITNR 9
-#define R_IRQ_READ0__par0_data__WIDTH 1
-#define R_IRQ_READ0__par0_data__active 1
-#define R_IRQ_READ0__par0_data__inactive 0
-#define R_IRQ_READ0__ata_irq1__BITNR 9
-#define R_IRQ_READ0__ata_irq1__WIDTH 1
-#define R_IRQ_READ0__ata_irq1__active 1
-#define R_IRQ_READ0__ata_irq1__inactive 0
-#define R_IRQ_READ0__par0_ready__BITNR 8
-#define R_IRQ_READ0__par0_ready__WIDTH 1
-#define R_IRQ_READ0__par0_ready__active 1
-#define R_IRQ_READ0__par0_ready__inactive 0
-#define R_IRQ_READ0__ata_irq0__BITNR 8
-#define R_IRQ_READ0__ata_irq0__WIDTH 1
-#define R_IRQ_READ0__ata_irq0__active 1
-#define R_IRQ_READ0__ata_irq0__inactive 0
-#define R_IRQ_READ0__mio__BITNR 8
-#define R_IRQ_READ0__mio__WIDTH 1
-#define R_IRQ_READ0__mio__active 1
-#define R_IRQ_READ0__mio__inactive 0
-#define R_IRQ_READ0__scsi0__BITNR 8
-#define R_IRQ_READ0__scsi0__WIDTH 1
-#define R_IRQ_READ0__scsi0__active 1
-#define R_IRQ_READ0__scsi0__inactive 0
-#define R_IRQ_READ0__ata_dmaend__BITNR 7
-#define R_IRQ_READ0__ata_dmaend__WIDTH 1
-#define R_IRQ_READ0__ata_dmaend__active 1
-#define R_IRQ_READ0__ata_dmaend__inactive 0
-#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_READ0__irq_ext_vector_nr__active 1
-#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0
-#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4
-#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_READ0__irq_int_vector_nr__active 1
-#define R_IRQ_READ0__irq_int_vector_nr__inactive 0
-#define R_IRQ_READ0__ext_dma1__BITNR 3
-#define R_IRQ_READ0__ext_dma1__WIDTH 1
-#define R_IRQ_READ0__ext_dma1__active 1
-#define R_IRQ_READ0__ext_dma1__inactive 0
-#define R_IRQ_READ0__ext_dma0__BITNR 2
-#define R_IRQ_READ0__ext_dma0__WIDTH 1
-#define R_IRQ_READ0__ext_dma0__active 1
-#define R_IRQ_READ0__ext_dma0__inactive 0
-#define R_IRQ_READ0__timer1__BITNR 1
-#define R_IRQ_READ0__timer1__WIDTH 1
-#define R_IRQ_READ0__timer1__active 1
-#define R_IRQ_READ0__timer1__inactive 0
-#define R_IRQ_READ0__timer0__BITNR 0
-#define R_IRQ_READ0__timer0__WIDTH 1
-#define R_IRQ_READ0__timer0__active 1
-#define R_IRQ_READ0__timer0__inactive 0
-
-#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4)
-#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31
-#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1
-#define R_IRQ_MASK0_SET__nmi_pin__set 1
-#define R_IRQ_MASK0_SET__nmi_pin__nop 0
-#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30
-#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1
-#define R_IRQ_MASK0_SET__watchdog_nmi__set 1
-#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0
-#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29
-#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1
-#define R_IRQ_MASK0_SET__sqe_test_error__set 1
-#define R_IRQ_MASK0_SET__sqe_test_error__nop 0
-#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28
-#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1
-#define R_IRQ_MASK0_SET__carrier_loss__set 1
-#define R_IRQ_MASK0_SET__carrier_loss__nop 0
-#define R_IRQ_MASK0_SET__deferred__BITNR 27
-#define R_IRQ_MASK0_SET__deferred__WIDTH 1
-#define R_IRQ_MASK0_SET__deferred__set 1
-#define R_IRQ_MASK0_SET__deferred__nop 0
-#define R_IRQ_MASK0_SET__late_col__BITNR 26
-#define R_IRQ_MASK0_SET__late_col__WIDTH 1
-#define R_IRQ_MASK0_SET__late_col__set 1
-#define R_IRQ_MASK0_SET__late_col__nop 0
-#define R_IRQ_MASK0_SET__multiple_col__BITNR 25
-#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1
-#define R_IRQ_MASK0_SET__multiple_col__set 1
-#define R_IRQ_MASK0_SET__multiple_col__nop 0
-#define R_IRQ_MASK0_SET__single_col__BITNR 24
-#define R_IRQ_MASK0_SET__single_col__WIDTH 1
-#define R_IRQ_MASK0_SET__single_col__set 1
-#define R_IRQ_MASK0_SET__single_col__nop 0
-#define R_IRQ_MASK0_SET__congestion__BITNR 23
-#define R_IRQ_MASK0_SET__congestion__WIDTH 1
-#define R_IRQ_MASK0_SET__congestion__set 1
-#define R_IRQ_MASK0_SET__congestion__nop 0
-#define R_IRQ_MASK0_SET__oversize__BITNR 22
-#define R_IRQ_MASK0_SET__oversize__WIDTH 1
-#define R_IRQ_MASK0_SET__oversize__set 1
-#define R_IRQ_MASK0_SET__oversize__nop 0
-#define R_IRQ_MASK0_SET__alignment_error__BITNR 21
-#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1
-#define R_IRQ_MASK0_SET__alignment_error__set 1
-#define R_IRQ_MASK0_SET__alignment_error__nop 0
-#define R_IRQ_MASK0_SET__crc_error__BITNR 20
-#define R_IRQ_MASK0_SET__crc_error__WIDTH 1
-#define R_IRQ_MASK0_SET__crc_error__set 1
-#define R_IRQ_MASK0_SET__crc_error__nop 0
-#define R_IRQ_MASK0_SET__overrun__BITNR 19
-#define R_IRQ_MASK0_SET__overrun__WIDTH 1
-#define R_IRQ_MASK0_SET__overrun__set 1
-#define R_IRQ_MASK0_SET__overrun__nop 0
-#define R_IRQ_MASK0_SET__underrun__BITNR 18
-#define R_IRQ_MASK0_SET__underrun__WIDTH 1
-#define R_IRQ_MASK0_SET__underrun__set 1
-#define R_IRQ_MASK0_SET__underrun__nop 0
-#define R_IRQ_MASK0_SET__excessive_col__BITNR 17
-#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1
-#define R_IRQ_MASK0_SET__excessive_col__set 1
-#define R_IRQ_MASK0_SET__excessive_col__nop 0
-#define R_IRQ_MASK0_SET__mdio__BITNR 16
-#define R_IRQ_MASK0_SET__mdio__WIDTH 1
-#define R_IRQ_MASK0_SET__mdio__set 1
-#define R_IRQ_MASK0_SET__mdio__nop 0
-#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15
-#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq3__set 1
-#define R_IRQ_MASK0_SET__ata_drq3__nop 0
-#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14
-#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq2__set 1
-#define R_IRQ_MASK0_SET__ata_drq2__nop 0
-#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13
-#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq1__set 1
-#define R_IRQ_MASK0_SET__ata_drq1__nop 0
-#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12
-#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_drq0__set 1
-#define R_IRQ_MASK0_SET__ata_drq0__nop 0
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1
-#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0
-#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11
-#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq3__set 1
-#define R_IRQ_MASK0_SET__ata_irq3__nop 0
-#define R_IRQ_MASK0_SET__par0_peri__BITNR 10
-#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_peri__set 1
-#define R_IRQ_MASK0_SET__par0_peri__nop 0
-#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10
-#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq2__set 1
-#define R_IRQ_MASK0_SET__ata_irq2__nop 0
-#define R_IRQ_MASK0_SET__par0_data__BITNR 9
-#define R_IRQ_MASK0_SET__par0_data__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_data__set 1
-#define R_IRQ_MASK0_SET__par0_data__nop 0
-#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9
-#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq1__set 1
-#define R_IRQ_MASK0_SET__ata_irq1__nop 0
-#define R_IRQ_MASK0_SET__par0_ready__BITNR 8
-#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1
-#define R_IRQ_MASK0_SET__par0_ready__set 1
-#define R_IRQ_MASK0_SET__par0_ready__nop 0
-#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8
-#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_irq0__set 1
-#define R_IRQ_MASK0_SET__ata_irq0__nop 0
-#define R_IRQ_MASK0_SET__mio__BITNR 8
-#define R_IRQ_MASK0_SET__mio__WIDTH 1
-#define R_IRQ_MASK0_SET__mio__set 1
-#define R_IRQ_MASK0_SET__mio__nop 0
-#define R_IRQ_MASK0_SET__scsi0__BITNR 8
-#define R_IRQ_MASK0_SET__scsi0__WIDTH 1
-#define R_IRQ_MASK0_SET__scsi0__set 1
-#define R_IRQ_MASK0_SET__scsi0__nop 0
-#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
-#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1
-#define R_IRQ_MASK0_SET__ata_dmaend__set 1
-#define R_IRQ_MASK0_SET__ata_dmaend__nop 0
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1
-#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1
-#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0
-#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3
-#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1
-#define R_IRQ_MASK0_SET__ext_dma1__set 1
-#define R_IRQ_MASK0_SET__ext_dma1__nop 0
-#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2
-#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1
-#define R_IRQ_MASK0_SET__ext_dma0__set 1
-#define R_IRQ_MASK0_SET__ext_dma0__nop 0
-#define R_IRQ_MASK0_SET__timer1__BITNR 1
-#define R_IRQ_MASK0_SET__timer1__WIDTH 1
-#define R_IRQ_MASK0_SET__timer1__set 1
-#define R_IRQ_MASK0_SET__timer1__nop 0
-#define R_IRQ_MASK0_SET__timer0__BITNR 0
-#define R_IRQ_MASK0_SET__timer0__WIDTH 1
-#define R_IRQ_MASK0_SET__timer0__set 1
-#define R_IRQ_MASK0_SET__timer0__nop 0
-
-#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8)
-#define R_IRQ_MASK1_RD__sw_int7__BITNR 31
-#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int7__active 1
-#define R_IRQ_MASK1_RD__sw_int7__inactive 0
-#define R_IRQ_MASK1_RD__sw_int6__BITNR 30
-#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int6__active 1
-#define R_IRQ_MASK1_RD__sw_int6__inactive 0
-#define R_IRQ_MASK1_RD__sw_int5__BITNR 29
-#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int5__active 1
-#define R_IRQ_MASK1_RD__sw_int5__inactive 0
-#define R_IRQ_MASK1_RD__sw_int4__BITNR 28
-#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int4__active 1
-#define R_IRQ_MASK1_RD__sw_int4__inactive 0
-#define R_IRQ_MASK1_RD__sw_int3__BITNR 27
-#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int3__active 1
-#define R_IRQ_MASK1_RD__sw_int3__inactive 0
-#define R_IRQ_MASK1_RD__sw_int2__BITNR 26
-#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int2__active 1
-#define R_IRQ_MASK1_RD__sw_int2__inactive 0
-#define R_IRQ_MASK1_RD__sw_int1__BITNR 25
-#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int1__active 1
-#define R_IRQ_MASK1_RD__sw_int1__inactive 0
-#define R_IRQ_MASK1_RD__sw_int0__BITNR 24
-#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_RD__sw_int0__active 1
-#define R_IRQ_MASK1_RD__sw_int0__inactive 0
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1
-#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0
-#define R_IRQ_MASK1_RD__par1_peri__BITNR 18
-#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_peri__active 1
-#define R_IRQ_MASK1_RD__par1_peri__inactive 0
-#define R_IRQ_MASK1_RD__par1_data__BITNR 17
-#define R_IRQ_MASK1_RD__par1_data__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_data__active 1
-#define R_IRQ_MASK1_RD__par1_data__inactive 0
-#define R_IRQ_MASK1_RD__par1_ready__BITNR 16
-#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__par1_ready__active 1
-#define R_IRQ_MASK1_RD__par1_ready__inactive 0
-#define R_IRQ_MASK1_RD__scsi1__BITNR 16
-#define R_IRQ_MASK1_RD__scsi1__WIDTH 1
-#define R_IRQ_MASK1_RD__scsi1__active 1
-#define R_IRQ_MASK1_RD__scsi1__inactive 0
-#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser3_ready__active 1
-#define R_IRQ_MASK1_RD__ser3_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser3_data__BITNR 14
-#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser3_data__active 1
-#define R_IRQ_MASK1_RD__ser3_data__inactive 0
-#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser2_ready__active 1
-#define R_IRQ_MASK1_RD__ser2_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser2_data__BITNR 12
-#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser2_data__active 1
-#define R_IRQ_MASK1_RD__ser2_data__inactive 0
-#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser1_ready__active 1
-#define R_IRQ_MASK1_RD__ser1_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser1_data__BITNR 10
-#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser1_data__active 1
-#define R_IRQ_MASK1_RD__ser1_data__inactive 0
-#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_RD__ser0_ready__active 1
-#define R_IRQ_MASK1_RD__ser0_ready__inactive 0
-#define R_IRQ_MASK1_RD__ser0_data__BITNR 8
-#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_RD__ser0_data__active 1
-#define R_IRQ_MASK1_RD__ser0_data__inactive 0
-#define R_IRQ_MASK1_RD__pa7__BITNR 7
-#define R_IRQ_MASK1_RD__pa7__WIDTH 1
-#define R_IRQ_MASK1_RD__pa7__active 1
-#define R_IRQ_MASK1_RD__pa7__inactive 0
-#define R_IRQ_MASK1_RD__pa6__BITNR 6
-#define R_IRQ_MASK1_RD__pa6__WIDTH 1
-#define R_IRQ_MASK1_RD__pa6__active 1
-#define R_IRQ_MASK1_RD__pa6__inactive 0
-#define R_IRQ_MASK1_RD__pa5__BITNR 5
-#define R_IRQ_MASK1_RD__pa5__WIDTH 1
-#define R_IRQ_MASK1_RD__pa5__active 1
-#define R_IRQ_MASK1_RD__pa5__inactive 0
-#define R_IRQ_MASK1_RD__pa4__BITNR 4
-#define R_IRQ_MASK1_RD__pa4__WIDTH 1
-#define R_IRQ_MASK1_RD__pa4__active 1
-#define R_IRQ_MASK1_RD__pa4__inactive 0
-#define R_IRQ_MASK1_RD__pa3__BITNR 3
-#define R_IRQ_MASK1_RD__pa3__WIDTH 1
-#define R_IRQ_MASK1_RD__pa3__active 1
-#define R_IRQ_MASK1_RD__pa3__inactive 0
-#define R_IRQ_MASK1_RD__pa2__BITNR 2
-#define R_IRQ_MASK1_RD__pa2__WIDTH 1
-#define R_IRQ_MASK1_RD__pa2__active 1
-#define R_IRQ_MASK1_RD__pa2__inactive 0
-#define R_IRQ_MASK1_RD__pa1__BITNR 1
-#define R_IRQ_MASK1_RD__pa1__WIDTH 1
-#define R_IRQ_MASK1_RD__pa1__active 1
-#define R_IRQ_MASK1_RD__pa1__inactive 0
-#define R_IRQ_MASK1_RD__pa0__BITNR 0
-#define R_IRQ_MASK1_RD__pa0__WIDTH 1
-#define R_IRQ_MASK1_RD__pa0__active 1
-#define R_IRQ_MASK1_RD__pa0__inactive 0
-
-#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8)
-#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31
-#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int7__clr 1
-#define R_IRQ_MASK1_CLR__sw_int7__nop 0
-#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30
-#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int6__clr 1
-#define R_IRQ_MASK1_CLR__sw_int6__nop 0
-#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29
-#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int5__clr 1
-#define R_IRQ_MASK1_CLR__sw_int5__nop 0
-#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28
-#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int4__clr 1
-#define R_IRQ_MASK1_CLR__sw_int4__nop 0
-#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27
-#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int3__clr 1
-#define R_IRQ_MASK1_CLR__sw_int3__nop 0
-#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26
-#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int2__clr 1
-#define R_IRQ_MASK1_CLR__sw_int2__nop 0
-#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25
-#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int1__clr 1
-#define R_IRQ_MASK1_CLR__sw_int1__nop 0
-#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24
-#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_CLR__sw_int0__clr 1
-#define R_IRQ_MASK1_CLR__sw_int0__nop 0
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1
-#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0
-#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18
-#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_peri__clr 1
-#define R_IRQ_MASK1_CLR__par1_peri__nop 0
-#define R_IRQ_MASK1_CLR__par1_data__BITNR 17
-#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_data__clr 1
-#define R_IRQ_MASK1_CLR__par1_data__nop 0
-#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16
-#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__par1_ready__clr 1
-#define R_IRQ_MASK1_CLR__par1_ready__nop 0
-#define R_IRQ_MASK1_CLR__scsi1__BITNR 16
-#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1
-#define R_IRQ_MASK1_CLR__scsi1__clr 1
-#define R_IRQ_MASK1_CLR__scsi1__nop 0
-#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser3_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser3_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14
-#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser3_data__clr 1
-#define R_IRQ_MASK1_CLR__ser3_data__nop 0
-#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser2_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser2_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12
-#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser2_data__clr 1
-#define R_IRQ_MASK1_CLR__ser2_data__nop 0
-#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser1_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser1_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10
-#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser1_data__clr 1
-#define R_IRQ_MASK1_CLR__ser1_data__nop 0
-#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser0_ready__clr 1
-#define R_IRQ_MASK1_CLR__ser0_ready__nop 0
-#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8
-#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_CLR__ser0_data__clr 1
-#define R_IRQ_MASK1_CLR__ser0_data__nop 0
-#define R_IRQ_MASK1_CLR__pa7__BITNR 7
-#define R_IRQ_MASK1_CLR__pa7__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa7__clr 1
-#define R_IRQ_MASK1_CLR__pa7__nop 0
-#define R_IRQ_MASK1_CLR__pa6__BITNR 6
-#define R_IRQ_MASK1_CLR__pa6__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa6__clr 1
-#define R_IRQ_MASK1_CLR__pa6__nop 0
-#define R_IRQ_MASK1_CLR__pa5__BITNR 5
-#define R_IRQ_MASK1_CLR__pa5__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa5__clr 1
-#define R_IRQ_MASK1_CLR__pa5__nop 0
-#define R_IRQ_MASK1_CLR__pa4__BITNR 4
-#define R_IRQ_MASK1_CLR__pa4__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa4__clr 1
-#define R_IRQ_MASK1_CLR__pa4__nop 0
-#define R_IRQ_MASK1_CLR__pa3__BITNR 3
-#define R_IRQ_MASK1_CLR__pa3__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa3__clr 1
-#define R_IRQ_MASK1_CLR__pa3__nop 0
-#define R_IRQ_MASK1_CLR__pa2__BITNR 2
-#define R_IRQ_MASK1_CLR__pa2__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa2__clr 1
-#define R_IRQ_MASK1_CLR__pa2__nop 0
-#define R_IRQ_MASK1_CLR__pa1__BITNR 1
-#define R_IRQ_MASK1_CLR__pa1__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa1__clr 1
-#define R_IRQ_MASK1_CLR__pa1__nop 0
-#define R_IRQ_MASK1_CLR__pa0__BITNR 0
-#define R_IRQ_MASK1_CLR__pa0__WIDTH 1
-#define R_IRQ_MASK1_CLR__pa0__clr 1
-#define R_IRQ_MASK1_CLR__pa0__nop 0
-
-#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc)
-#define R_IRQ_READ1__sw_int7__BITNR 31
-#define R_IRQ_READ1__sw_int7__WIDTH 1
-#define R_IRQ_READ1__sw_int7__active 1
-#define R_IRQ_READ1__sw_int7__inactive 0
-#define R_IRQ_READ1__sw_int6__BITNR 30
-#define R_IRQ_READ1__sw_int6__WIDTH 1
-#define R_IRQ_READ1__sw_int6__active 1
-#define R_IRQ_READ1__sw_int6__inactive 0
-#define R_IRQ_READ1__sw_int5__BITNR 29
-#define R_IRQ_READ1__sw_int5__WIDTH 1
-#define R_IRQ_READ1__sw_int5__active 1
-#define R_IRQ_READ1__sw_int5__inactive 0
-#define R_IRQ_READ1__sw_int4__BITNR 28
-#define R_IRQ_READ1__sw_int4__WIDTH 1
-#define R_IRQ_READ1__sw_int4__active 1
-#define R_IRQ_READ1__sw_int4__inactive 0
-#define R_IRQ_READ1__sw_int3__BITNR 27
-#define R_IRQ_READ1__sw_int3__WIDTH 1
-#define R_IRQ_READ1__sw_int3__active 1
-#define R_IRQ_READ1__sw_int3__inactive 0
-#define R_IRQ_READ1__sw_int2__BITNR 26
-#define R_IRQ_READ1__sw_int2__WIDTH 1
-#define R_IRQ_READ1__sw_int2__active 1
-#define R_IRQ_READ1__sw_int2__inactive 0
-#define R_IRQ_READ1__sw_int1__BITNR 25
-#define R_IRQ_READ1__sw_int1__WIDTH 1
-#define R_IRQ_READ1__sw_int1__active 1
-#define R_IRQ_READ1__sw_int1__inactive 0
-#define R_IRQ_READ1__sw_int0__BITNR 24
-#define R_IRQ_READ1__sw_int0__WIDTH 1
-#define R_IRQ_READ1__sw_int0__active 1
-#define R_IRQ_READ1__sw_int0__inactive 0
-#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19
-#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_READ1__par1_ecp_cmd__active 1
-#define R_IRQ_READ1__par1_ecp_cmd__inactive 0
-#define R_IRQ_READ1__par1_peri__BITNR 18
-#define R_IRQ_READ1__par1_peri__WIDTH 1
-#define R_IRQ_READ1__par1_peri__active 1
-#define R_IRQ_READ1__par1_peri__inactive 0
-#define R_IRQ_READ1__par1_data__BITNR 17
-#define R_IRQ_READ1__par1_data__WIDTH 1
-#define R_IRQ_READ1__par1_data__active 1
-#define R_IRQ_READ1__par1_data__inactive 0
-#define R_IRQ_READ1__par1_ready__BITNR 16
-#define R_IRQ_READ1__par1_ready__WIDTH 1
-#define R_IRQ_READ1__par1_ready__active 1
-#define R_IRQ_READ1__par1_ready__inactive 0
-#define R_IRQ_READ1__scsi1__BITNR 16
-#define R_IRQ_READ1__scsi1__WIDTH 1
-#define R_IRQ_READ1__scsi1__active 1
-#define R_IRQ_READ1__scsi1__inactive 0
-#define R_IRQ_READ1__ser3_ready__BITNR 15
-#define R_IRQ_READ1__ser3_ready__WIDTH 1
-#define R_IRQ_READ1__ser3_ready__active 1
-#define R_IRQ_READ1__ser3_ready__inactive 0
-#define R_IRQ_READ1__ser3_data__BITNR 14
-#define R_IRQ_READ1__ser3_data__WIDTH 1
-#define R_IRQ_READ1__ser3_data__active 1
-#define R_IRQ_READ1__ser3_data__inactive 0
-#define R_IRQ_READ1__ser2_ready__BITNR 13
-#define R_IRQ_READ1__ser2_ready__WIDTH 1
-#define R_IRQ_READ1__ser2_ready__active 1
-#define R_IRQ_READ1__ser2_ready__inactive 0
-#define R_IRQ_READ1__ser2_data__BITNR 12
-#define R_IRQ_READ1__ser2_data__WIDTH 1
-#define R_IRQ_READ1__ser2_data__active 1
-#define R_IRQ_READ1__ser2_data__inactive 0
-#define R_IRQ_READ1__ser1_ready__BITNR 11
-#define R_IRQ_READ1__ser1_ready__WIDTH 1
-#define R_IRQ_READ1__ser1_ready__active 1
-#define R_IRQ_READ1__ser1_ready__inactive 0
-#define R_IRQ_READ1__ser1_data__BITNR 10
-#define R_IRQ_READ1__ser1_data__WIDTH 1
-#define R_IRQ_READ1__ser1_data__active 1
-#define R_IRQ_READ1__ser1_data__inactive 0
-#define R_IRQ_READ1__ser0_ready__BITNR 9
-#define R_IRQ_READ1__ser0_ready__WIDTH 1
-#define R_IRQ_READ1__ser0_ready__active 1
-#define R_IRQ_READ1__ser0_ready__inactive 0
-#define R_IRQ_READ1__ser0_data__BITNR 8
-#define R_IRQ_READ1__ser0_data__WIDTH 1
-#define R_IRQ_READ1__ser0_data__active 1
-#define R_IRQ_READ1__ser0_data__inactive 0
-#define R_IRQ_READ1__pa7__BITNR 7
-#define R_IRQ_READ1__pa7__WIDTH 1
-#define R_IRQ_READ1__pa7__active 1
-#define R_IRQ_READ1__pa7__inactive 0
-#define R_IRQ_READ1__pa6__BITNR 6
-#define R_IRQ_READ1__pa6__WIDTH 1
-#define R_IRQ_READ1__pa6__active 1
-#define R_IRQ_READ1__pa6__inactive 0
-#define R_IRQ_READ1__pa5__BITNR 5
-#define R_IRQ_READ1__pa5__WIDTH 1
-#define R_IRQ_READ1__pa5__active 1
-#define R_IRQ_READ1__pa5__inactive 0
-#define R_IRQ_READ1__pa4__BITNR 4
-#define R_IRQ_READ1__pa4__WIDTH 1
-#define R_IRQ_READ1__pa4__active 1
-#define R_IRQ_READ1__pa4__inactive 0
-#define R_IRQ_READ1__pa3__BITNR 3
-#define R_IRQ_READ1__pa3__WIDTH 1
-#define R_IRQ_READ1__pa3__active 1
-#define R_IRQ_READ1__pa3__inactive 0
-#define R_IRQ_READ1__pa2__BITNR 2
-#define R_IRQ_READ1__pa2__WIDTH 1
-#define R_IRQ_READ1__pa2__active 1
-#define R_IRQ_READ1__pa2__inactive 0
-#define R_IRQ_READ1__pa1__BITNR 1
-#define R_IRQ_READ1__pa1__WIDTH 1
-#define R_IRQ_READ1__pa1__active 1
-#define R_IRQ_READ1__pa1__inactive 0
-#define R_IRQ_READ1__pa0__BITNR 0
-#define R_IRQ_READ1__pa0__WIDTH 1
-#define R_IRQ_READ1__pa0__active 1
-#define R_IRQ_READ1__pa0__inactive 0
-
-#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc)
-#define R_IRQ_MASK1_SET__sw_int7__BITNR 31
-#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int7__set 1
-#define R_IRQ_MASK1_SET__sw_int7__nop 0
-#define R_IRQ_MASK1_SET__sw_int6__BITNR 30
-#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int6__set 1
-#define R_IRQ_MASK1_SET__sw_int6__nop 0
-#define R_IRQ_MASK1_SET__sw_int5__BITNR 29
-#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int5__set 1
-#define R_IRQ_MASK1_SET__sw_int5__nop 0
-#define R_IRQ_MASK1_SET__sw_int4__BITNR 28
-#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int4__set 1
-#define R_IRQ_MASK1_SET__sw_int4__nop 0
-#define R_IRQ_MASK1_SET__sw_int3__BITNR 27
-#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int3__set 1
-#define R_IRQ_MASK1_SET__sw_int3__nop 0
-#define R_IRQ_MASK1_SET__sw_int2__BITNR 26
-#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int2__set 1
-#define R_IRQ_MASK1_SET__sw_int2__nop 0
-#define R_IRQ_MASK1_SET__sw_int1__BITNR 25
-#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int1__set 1
-#define R_IRQ_MASK1_SET__sw_int1__nop 0
-#define R_IRQ_MASK1_SET__sw_int0__BITNR 24
-#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1
-#define R_IRQ_MASK1_SET__sw_int0__set 1
-#define R_IRQ_MASK1_SET__sw_int0__nop 0
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1
-#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0
-#define R_IRQ_MASK1_SET__par1_peri__BITNR 18
-#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_peri__set 1
-#define R_IRQ_MASK1_SET__par1_peri__nop 0
-#define R_IRQ_MASK1_SET__par1_data__BITNR 17
-#define R_IRQ_MASK1_SET__par1_data__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_data__set 1
-#define R_IRQ_MASK1_SET__par1_data__nop 0
-#define R_IRQ_MASK1_SET__par1_ready__BITNR 16
-#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__par1_ready__set 1
-#define R_IRQ_MASK1_SET__par1_ready__nop 0
-#define R_IRQ_MASK1_SET__scsi1__BITNR 16
-#define R_IRQ_MASK1_SET__scsi1__WIDTH 1
-#define R_IRQ_MASK1_SET__scsi1__set 1
-#define R_IRQ_MASK1_SET__scsi1__nop 0
-#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15
-#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser3_ready__set 1
-#define R_IRQ_MASK1_SET__ser3_ready__nop 0
-#define R_IRQ_MASK1_SET__ser3_data__BITNR 14
-#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser3_data__set 1
-#define R_IRQ_MASK1_SET__ser3_data__nop 0
-#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13
-#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser2_ready__set 1
-#define R_IRQ_MASK1_SET__ser2_ready__nop 0
-#define R_IRQ_MASK1_SET__ser2_data__BITNR 12
-#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser2_data__set 1
-#define R_IRQ_MASK1_SET__ser2_data__nop 0
-#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11
-#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser1_ready__set 1
-#define R_IRQ_MASK1_SET__ser1_ready__nop 0
-#define R_IRQ_MASK1_SET__ser1_data__BITNR 10
-#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser1_data__set 1
-#define R_IRQ_MASK1_SET__ser1_data__nop 0
-#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9
-#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1
-#define R_IRQ_MASK1_SET__ser0_ready__set 1
-#define R_IRQ_MASK1_SET__ser0_ready__nop 0
-#define R_IRQ_MASK1_SET__ser0_data__BITNR 8
-#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1
-#define R_IRQ_MASK1_SET__ser0_data__set 1
-#define R_IRQ_MASK1_SET__ser0_data__nop 0
-#define R_IRQ_MASK1_SET__pa7__BITNR 7
-#define R_IRQ_MASK1_SET__pa7__WIDTH 1
-#define R_IRQ_MASK1_SET__pa7__set 1
-#define R_IRQ_MASK1_SET__pa7__nop 0
-#define R_IRQ_MASK1_SET__pa6__BITNR 6
-#define R_IRQ_MASK1_SET__pa6__WIDTH 1
-#define R_IRQ_MASK1_SET__pa6__set 1
-#define R_IRQ_MASK1_SET__pa6__nop 0
-#define R_IRQ_MASK1_SET__pa5__BITNR 5
-#define R_IRQ_MASK1_SET__pa5__WIDTH 1
-#define R_IRQ_MASK1_SET__pa5__set 1
-#define R_IRQ_MASK1_SET__pa5__nop 0
-#define R_IRQ_MASK1_SET__pa4__BITNR 4
-#define R_IRQ_MASK1_SET__pa4__WIDTH 1
-#define R_IRQ_MASK1_SET__pa4__set 1
-#define R_IRQ_MASK1_SET__pa4__nop 0
-#define R_IRQ_MASK1_SET__pa3__BITNR 3
-#define R_IRQ_MASK1_SET__pa3__WIDTH 1
-#define R_IRQ_MASK1_SET__pa3__set 1
-#define R_IRQ_MASK1_SET__pa3__nop 0
-#define R_IRQ_MASK1_SET__pa2__BITNR 2
-#define R_IRQ_MASK1_SET__pa2__WIDTH 1
-#define R_IRQ_MASK1_SET__pa2__set 1
-#define R_IRQ_MASK1_SET__pa2__nop 0
-#define R_IRQ_MASK1_SET__pa1__BITNR 1
-#define R_IRQ_MASK1_SET__pa1__WIDTH 1
-#define R_IRQ_MASK1_SET__pa1__set 1
-#define R_IRQ_MASK1_SET__pa1__nop 0
-#define R_IRQ_MASK1_SET__pa0__BITNR 0
-#define R_IRQ_MASK1_SET__pa0__WIDTH 1
-#define R_IRQ_MASK1_SET__pa0__set 1
-#define R_IRQ_MASK1_SET__pa0__nop 0
-
-#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0)
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma9_eop__active 1
-#define R_IRQ_MASK2_RD__dma9_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma9_descr__active 1
-#define R_IRQ_MASK2_RD__dma9_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_eop__active 1
-#define R_IRQ_MASK2_RD__dma8_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma8_descr__active 1
-#define R_IRQ_MASK2_RD__dma8_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma7_eop__active 1
-#define R_IRQ_MASK2_RD__dma7_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma7_descr__active 1
-#define R_IRQ_MASK2_RD__dma7_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma6_eop__active 1
-#define R_IRQ_MASK2_RD__dma6_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma6_descr__active 1
-#define R_IRQ_MASK2_RD__dma6_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma5_eop__active 1
-#define R_IRQ_MASK2_RD__dma5_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma5_descr__active 1
-#define R_IRQ_MASK2_RD__dma5_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma4_eop__active 1
-#define R_IRQ_MASK2_RD__dma4_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma4_descr__active 1
-#define R_IRQ_MASK2_RD__dma4_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma3_eop__active 1
-#define R_IRQ_MASK2_RD__dma3_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma3_descr__active 1
-#define R_IRQ_MASK2_RD__dma3_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma2_eop__active 1
-#define R_IRQ_MASK2_RD__dma2_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma2_descr__active 1
-#define R_IRQ_MASK2_RD__dma2_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma1_eop__active 1
-#define R_IRQ_MASK2_RD__dma1_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma1_descr__active 1
-#define R_IRQ_MASK2_RD__dma1_descr__inactive 0
-#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_RD__dma0_eop__active 1
-#define R_IRQ_MASK2_RD__dma0_eop__inactive 0
-#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_RD__dma0_descr__active 1
-#define R_IRQ_MASK2_RD__dma0_descr__inactive 0
-
-#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0)
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma9_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma9_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma9_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma9_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma8_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma8_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma8_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma7_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma7_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma7_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma7_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma6_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma6_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma6_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma6_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma5_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma5_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma5_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma5_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma4_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma4_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma4_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma4_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma3_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma3_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma3_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma3_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma2_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma2_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma2_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma2_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma1_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma1_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma1_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma1_descr__nop 0
-#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma0_eop__clr 1
-#define R_IRQ_MASK2_CLR__dma0_eop__nop 0
-#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_CLR__dma0_descr__clr 1
-#define R_IRQ_MASK2_CLR__dma0_descr__nop 0
-
-#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4)
-#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23
-#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub3_descr__active 1
-#define R_IRQ_READ2__dma8_sub3_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22
-#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub2_descr__active 1
-#define R_IRQ_READ2__dma8_sub2_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21
-#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub1_descr__active 1
-#define R_IRQ_READ2__dma8_sub1_descr__inactive 0
-#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20
-#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_sub0_descr__active 1
-#define R_IRQ_READ2__dma8_sub0_descr__inactive 0
-#define R_IRQ_READ2__dma9_eop__BITNR 19
-#define R_IRQ_READ2__dma9_eop__WIDTH 1
-#define R_IRQ_READ2__dma9_eop__active 1
-#define R_IRQ_READ2__dma9_eop__inactive 0
-#define R_IRQ_READ2__dma9_descr__BITNR 18
-#define R_IRQ_READ2__dma9_descr__WIDTH 1
-#define R_IRQ_READ2__dma9_descr__active 1
-#define R_IRQ_READ2__dma9_descr__inactive 0
-#define R_IRQ_READ2__dma8_eop__BITNR 17
-#define R_IRQ_READ2__dma8_eop__WIDTH 1
-#define R_IRQ_READ2__dma8_eop__active 1
-#define R_IRQ_READ2__dma8_eop__inactive 0
-#define R_IRQ_READ2__dma8_descr__BITNR 16
-#define R_IRQ_READ2__dma8_descr__WIDTH 1
-#define R_IRQ_READ2__dma8_descr__active 1
-#define R_IRQ_READ2__dma8_descr__inactive 0
-#define R_IRQ_READ2__dma7_eop__BITNR 15
-#define R_IRQ_READ2__dma7_eop__WIDTH 1
-#define R_IRQ_READ2__dma7_eop__active 1
-#define R_IRQ_READ2__dma7_eop__inactive 0
-#define R_IRQ_READ2__dma7_descr__BITNR 14
-#define R_IRQ_READ2__dma7_descr__WIDTH 1
-#define R_IRQ_READ2__dma7_descr__active 1
-#define R_IRQ_READ2__dma7_descr__inactive 0
-#define R_IRQ_READ2__dma6_eop__BITNR 13
-#define R_IRQ_READ2__dma6_eop__WIDTH 1
-#define R_IRQ_READ2__dma6_eop__active 1
-#define R_IRQ_READ2__dma6_eop__inactive 0
-#define R_IRQ_READ2__dma6_descr__BITNR 12
-#define R_IRQ_READ2__dma6_descr__WIDTH 1
-#define R_IRQ_READ2__dma6_descr__active 1
-#define R_IRQ_READ2__dma6_descr__inactive 0
-#define R_IRQ_READ2__dma5_eop__BITNR 11
-#define R_IRQ_READ2__dma5_eop__WIDTH 1
-#define R_IRQ_READ2__dma5_eop__active 1
-#define R_IRQ_READ2__dma5_eop__inactive 0
-#define R_IRQ_READ2__dma5_descr__BITNR 10
-#define R_IRQ_READ2__dma5_descr__WIDTH 1
-#define R_IRQ_READ2__dma5_descr__active 1
-#define R_IRQ_READ2__dma5_descr__inactive 0
-#define R_IRQ_READ2__dma4_eop__BITNR 9
-#define R_IRQ_READ2__dma4_eop__WIDTH 1
-#define R_IRQ_READ2__dma4_eop__active 1
-#define R_IRQ_READ2__dma4_eop__inactive 0
-#define R_IRQ_READ2__dma4_descr__BITNR 8
-#define R_IRQ_READ2__dma4_descr__WIDTH 1
-#define R_IRQ_READ2__dma4_descr__active 1
-#define R_IRQ_READ2__dma4_descr__inactive 0
-#define R_IRQ_READ2__dma3_eop__BITNR 7
-#define R_IRQ_READ2__dma3_eop__WIDTH 1
-#define R_IRQ_READ2__dma3_eop__active 1
-#define R_IRQ_READ2__dma3_eop__inactive 0
-#define R_IRQ_READ2__dma3_descr__BITNR 6
-#define R_IRQ_READ2__dma3_descr__WIDTH 1
-#define R_IRQ_READ2__dma3_descr__active 1
-#define R_IRQ_READ2__dma3_descr__inactive 0
-#define R_IRQ_READ2__dma2_eop__BITNR 5
-#define R_IRQ_READ2__dma2_eop__WIDTH 1
-#define R_IRQ_READ2__dma2_eop__active 1
-#define R_IRQ_READ2__dma2_eop__inactive 0
-#define R_IRQ_READ2__dma2_descr__BITNR 4
-#define R_IRQ_READ2__dma2_descr__WIDTH 1
-#define R_IRQ_READ2__dma2_descr__active 1
-#define R_IRQ_READ2__dma2_descr__inactive 0
-#define R_IRQ_READ2__dma1_eop__BITNR 3
-#define R_IRQ_READ2__dma1_eop__WIDTH 1
-#define R_IRQ_READ2__dma1_eop__active 1
-#define R_IRQ_READ2__dma1_eop__inactive 0
-#define R_IRQ_READ2__dma1_descr__BITNR 2
-#define R_IRQ_READ2__dma1_descr__WIDTH 1
-#define R_IRQ_READ2__dma1_descr__active 1
-#define R_IRQ_READ2__dma1_descr__inactive 0
-#define R_IRQ_READ2__dma0_eop__BITNR 1
-#define R_IRQ_READ2__dma0_eop__WIDTH 1
-#define R_IRQ_READ2__dma0_eop__active 1
-#define R_IRQ_READ2__dma0_eop__inactive 0
-#define R_IRQ_READ2__dma0_descr__BITNR 0
-#define R_IRQ_READ2__dma0_descr__WIDTH 1
-#define R_IRQ_READ2__dma0_descr__active 1
-#define R_IRQ_READ2__dma0_descr__inactive 0
-
-#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4)
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0
-#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19
-#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma9_eop__set 1
-#define R_IRQ_MASK2_SET__dma9_eop__nop 0
-#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18
-#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma9_descr__set 1
-#define R_IRQ_MASK2_SET__dma9_descr__nop 0
-#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17
-#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_eop__set 1
-#define R_IRQ_MASK2_SET__dma8_eop__nop 0
-#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16
-#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma8_descr__set 1
-#define R_IRQ_MASK2_SET__dma8_descr__nop 0
-#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15
-#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma7_eop__set 1
-#define R_IRQ_MASK2_SET__dma7_eop__nop 0
-#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14
-#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma7_descr__set 1
-#define R_IRQ_MASK2_SET__dma7_descr__nop 0
-#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13
-#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma6_eop__set 1
-#define R_IRQ_MASK2_SET__dma6_eop__nop 0
-#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12
-#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma6_descr__set 1
-#define R_IRQ_MASK2_SET__dma6_descr__nop 0
-#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11
-#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma5_eop__set 1
-#define R_IRQ_MASK2_SET__dma5_eop__nop 0
-#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10
-#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma5_descr__set 1
-#define R_IRQ_MASK2_SET__dma5_descr__nop 0
-#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9
-#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma4_eop__set 1
-#define R_IRQ_MASK2_SET__dma4_eop__nop 0
-#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8
-#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma4_descr__set 1
-#define R_IRQ_MASK2_SET__dma4_descr__nop 0
-#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7
-#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma3_eop__set 1
-#define R_IRQ_MASK2_SET__dma3_eop__nop 0
-#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6
-#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma3_descr__set 1
-#define R_IRQ_MASK2_SET__dma3_descr__nop 0
-#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5
-#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma2_eop__set 1
-#define R_IRQ_MASK2_SET__dma2_eop__nop 0
-#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4
-#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma2_descr__set 1
-#define R_IRQ_MASK2_SET__dma2_descr__nop 0
-#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3
-#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma1_eop__set 1
-#define R_IRQ_MASK2_SET__dma1_eop__nop 0
-#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2
-#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma1_descr__set 1
-#define R_IRQ_MASK2_SET__dma1_descr__nop 0
-#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1
-#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1
-#define R_IRQ_MASK2_SET__dma0_eop__set 1
-#define R_IRQ_MASK2_SET__dma0_eop__nop 0
-#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0
-#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1
-#define R_IRQ_MASK2_SET__dma0_descr__set 1
-#define R_IRQ_MASK2_SET__dma0_descr__nop 0
-
-#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8)
-#define R_VECT_MASK_RD__usb__BITNR 31
-#define R_VECT_MASK_RD__usb__WIDTH 1
-#define R_VECT_MASK_RD__usb__active 1
-#define R_VECT_MASK_RD__usb__inactive 0
-#define R_VECT_MASK_RD__dma9__BITNR 25
-#define R_VECT_MASK_RD__dma9__WIDTH 1
-#define R_VECT_MASK_RD__dma9__active 1
-#define R_VECT_MASK_RD__dma9__inactive 0
-#define R_VECT_MASK_RD__dma8__BITNR 24
-#define R_VECT_MASK_RD__dma8__WIDTH 1
-#define R_VECT_MASK_RD__dma8__active 1
-#define R_VECT_MASK_RD__dma8__inactive 0
-#define R_VECT_MASK_RD__dma7__BITNR 23
-#define R_VECT_MASK_RD__dma7__WIDTH 1
-#define R_VECT_MASK_RD__dma7__active 1
-#define R_VECT_MASK_RD__dma7__inactive 0
-#define R_VECT_MASK_RD__dma6__BITNR 22
-#define R_VECT_MASK_RD__dma6__WIDTH 1
-#define R_VECT_MASK_RD__dma6__active 1
-#define R_VECT_MASK_RD__dma6__inactive 0
-#define R_VECT_MASK_RD__dma5__BITNR 21
-#define R_VECT_MASK_RD__dma5__WIDTH 1
-#define R_VECT_MASK_RD__dma5__active 1
-#define R_VECT_MASK_RD__dma5__inactive 0
-#define R_VECT_MASK_RD__dma4__BITNR 20
-#define R_VECT_MASK_RD__dma4__WIDTH 1
-#define R_VECT_MASK_RD__dma4__active 1
-#define R_VECT_MASK_RD__dma4__inactive 0
-#define R_VECT_MASK_RD__dma3__BITNR 19
-#define R_VECT_MASK_RD__dma3__WIDTH 1
-#define R_VECT_MASK_RD__dma3__active 1
-#define R_VECT_MASK_RD__dma3__inactive 0
-#define R_VECT_MASK_RD__dma2__BITNR 18
-#define R_VECT_MASK_RD__dma2__WIDTH 1
-#define R_VECT_MASK_RD__dma2__active 1
-#define R_VECT_MASK_RD__dma2__inactive 0
-#define R_VECT_MASK_RD__dma1__BITNR 17
-#define R_VECT_MASK_RD__dma1__WIDTH 1
-#define R_VECT_MASK_RD__dma1__active 1
-#define R_VECT_MASK_RD__dma1__inactive 0
-#define R_VECT_MASK_RD__dma0__BITNR 16
-#define R_VECT_MASK_RD__dma0__WIDTH 1
-#define R_VECT_MASK_RD__dma0__active 1
-#define R_VECT_MASK_RD__dma0__inactive 0
-#define R_VECT_MASK_RD__ext_dma1__BITNR 13
-#define R_VECT_MASK_RD__ext_dma1__WIDTH 1
-#define R_VECT_MASK_RD__ext_dma1__active 1
-#define R_VECT_MASK_RD__ext_dma1__inactive 0
-#define R_VECT_MASK_RD__ext_dma0__BITNR 12
-#define R_VECT_MASK_RD__ext_dma0__WIDTH 1
-#define R_VECT_MASK_RD__ext_dma0__active 1
-#define R_VECT_MASK_RD__ext_dma0__inactive 0
-#define R_VECT_MASK_RD__pa__BITNR 11
-#define R_VECT_MASK_RD__pa__WIDTH 1
-#define R_VECT_MASK_RD__pa__active 1
-#define R_VECT_MASK_RD__pa__inactive 0
-#define R_VECT_MASK_RD__irq_intnr__BITNR 10
-#define R_VECT_MASK_RD__irq_intnr__WIDTH 1
-#define R_VECT_MASK_RD__irq_intnr__active 1
-#define R_VECT_MASK_RD__irq_intnr__inactive 0
-#define R_VECT_MASK_RD__sw__BITNR 9
-#define R_VECT_MASK_RD__sw__WIDTH 1
-#define R_VECT_MASK_RD__sw__active 1
-#define R_VECT_MASK_RD__sw__inactive 0
-#define R_VECT_MASK_RD__serial__BITNR 8
-#define R_VECT_MASK_RD__serial__WIDTH 1
-#define R_VECT_MASK_RD__serial__active 1
-#define R_VECT_MASK_RD__serial__inactive 0
-#define R_VECT_MASK_RD__snmp__BITNR 7
-#define R_VECT_MASK_RD__snmp__WIDTH 1
-#define R_VECT_MASK_RD__snmp__active 1
-#define R_VECT_MASK_RD__snmp__inactive 0
-#define R_VECT_MASK_RD__network__BITNR 6
-#define R_VECT_MASK_RD__network__WIDTH 1
-#define R_VECT_MASK_RD__network__active 1
-#define R_VECT_MASK_RD__network__inactive 0
-#define R_VECT_MASK_RD__scsi1__BITNR 5
-#define R_VECT_MASK_RD__scsi1__WIDTH 1
-#define R_VECT_MASK_RD__scsi1__active 1
-#define R_VECT_MASK_RD__scsi1__inactive 0
-#define R_VECT_MASK_RD__par1__BITNR 5
-#define R_VECT_MASK_RD__par1__WIDTH 1
-#define R_VECT_MASK_RD__par1__active 1
-#define R_VECT_MASK_RD__par1__inactive 0
-#define R_VECT_MASK_RD__scsi0__BITNR 4
-#define R_VECT_MASK_RD__scsi0__WIDTH 1
-#define R_VECT_MASK_RD__scsi0__active 1
-#define R_VECT_MASK_RD__scsi0__inactive 0
-#define R_VECT_MASK_RD__par0__BITNR 4
-#define R_VECT_MASK_RD__par0__WIDTH 1
-#define R_VECT_MASK_RD__par0__active 1
-#define R_VECT_MASK_RD__par0__inactive 0
-#define R_VECT_MASK_RD__ata__BITNR 4
-#define R_VECT_MASK_RD__ata__WIDTH 1
-#define R_VECT_MASK_RD__ata__active 1
-#define R_VECT_MASK_RD__ata__inactive 0
-#define R_VECT_MASK_RD__mio__BITNR 4
-#define R_VECT_MASK_RD__mio__WIDTH 1
-#define R_VECT_MASK_RD__mio__active 1
-#define R_VECT_MASK_RD__mio__inactive 0
-#define R_VECT_MASK_RD__timer1__BITNR 3
-#define R_VECT_MASK_RD__timer1__WIDTH 1
-#define R_VECT_MASK_RD__timer1__active 1
-#define R_VECT_MASK_RD__timer1__inactive 0
-#define R_VECT_MASK_RD__timer0__BITNR 2
-#define R_VECT_MASK_RD__timer0__WIDTH 1
-#define R_VECT_MASK_RD__timer0__active 1
-#define R_VECT_MASK_RD__timer0__inactive 0
-#define R_VECT_MASK_RD__nmi__BITNR 1
-#define R_VECT_MASK_RD__nmi__WIDTH 1
-#define R_VECT_MASK_RD__nmi__active 1
-#define R_VECT_MASK_RD__nmi__inactive 0
-#define R_VECT_MASK_RD__some__BITNR 0
-#define R_VECT_MASK_RD__some__WIDTH 1
-#define R_VECT_MASK_RD__some__active 1
-#define R_VECT_MASK_RD__some__inactive 0
-
-#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8)
-#define R_VECT_MASK_CLR__usb__BITNR 31
-#define R_VECT_MASK_CLR__usb__WIDTH 1
-#define R_VECT_MASK_CLR__usb__clr 1
-#define R_VECT_MASK_CLR__usb__nop 0
-#define R_VECT_MASK_CLR__dma9__BITNR 25
-#define R_VECT_MASK_CLR__dma9__WIDTH 1
-#define R_VECT_MASK_CLR__dma9__clr 1
-#define R_VECT_MASK_CLR__dma9__nop 0
-#define R_VECT_MASK_CLR__dma8__BITNR 24
-#define R_VECT_MASK_CLR__dma8__WIDTH 1
-#define R_VECT_MASK_CLR__dma8__clr 1
-#define R_VECT_MASK_CLR__dma8__nop 0
-#define R_VECT_MASK_CLR__dma7__BITNR 23
-#define R_VECT_MASK_CLR__dma7__WIDTH 1
-#define R_VECT_MASK_CLR__dma7__clr 1
-#define R_VECT_MASK_CLR__dma7__nop 0
-#define R_VECT_MASK_CLR__dma6__BITNR 22
-#define R_VECT_MASK_CLR__dma6__WIDTH 1
-#define R_VECT_MASK_CLR__dma6__clr 1
-#define R_VECT_MASK_CLR__dma6__nop 0
-#define R_VECT_MASK_CLR__dma5__BITNR 21
-#define R_VECT_MASK_CLR__dma5__WIDTH 1
-#define R_VECT_MASK_CLR__dma5__clr 1
-#define R_VECT_MASK_CLR__dma5__nop 0
-#define R_VECT_MASK_CLR__dma4__BITNR 20
-#define R_VECT_MASK_CLR__dma4__WIDTH 1
-#define R_VECT_MASK_CLR__dma4__clr 1
-#define R_VECT_MASK_CLR__dma4__nop 0
-#define R_VECT_MASK_CLR__dma3__BITNR 19
-#define R_VECT_MASK_CLR__dma3__WIDTH 1
-#define R_VECT_MASK_CLR__dma3__clr 1
-#define R_VECT_MASK_CLR__dma3__nop 0
-#define R_VECT_MASK_CLR__dma2__BITNR 18
-#define R_VECT_MASK_CLR__dma2__WIDTH 1
-#define R_VECT_MASK_CLR__dma2__clr 1
-#define R_VECT_MASK_CLR__dma2__nop 0
-#define R_VECT_MASK_CLR__dma1__BITNR 17
-#define R_VECT_MASK_CLR__dma1__WIDTH 1
-#define R_VECT_MASK_CLR__dma1__clr 1
-#define R_VECT_MASK_CLR__dma1__nop 0
-#define R_VECT_MASK_CLR__dma0__BITNR 16
-#define R_VECT_MASK_CLR__dma0__WIDTH 1
-#define R_VECT_MASK_CLR__dma0__clr 1
-#define R_VECT_MASK_CLR__dma0__nop 0
-#define R_VECT_MASK_CLR__ext_dma1__BITNR 13
-#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1
-#define R_VECT_MASK_CLR__ext_dma1__clr 1
-#define R_VECT_MASK_CLR__ext_dma1__nop 0
-#define R_VECT_MASK_CLR__ext_dma0__BITNR 12
-#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1
-#define R_VECT_MASK_CLR__ext_dma0__clr 1
-#define R_VECT_MASK_CLR__ext_dma0__nop 0
-#define R_VECT_MASK_CLR__pa__BITNR 11
-#define R_VECT_MASK_CLR__pa__WIDTH 1
-#define R_VECT_MASK_CLR__pa__clr 1
-#define R_VECT_MASK_CLR__pa__nop 0
-#define R_VECT_MASK_CLR__irq_intnr__BITNR 10
-#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1
-#define R_VECT_MASK_CLR__irq_intnr__clr 1
-#define R_VECT_MASK_CLR__irq_intnr__nop 0
-#define R_VECT_MASK_CLR__sw__BITNR 9
-#define R_VECT_MASK_CLR__sw__WIDTH 1
-#define R_VECT_MASK_CLR__sw__clr 1
-#define R_VECT_MASK_CLR__sw__nop 0
-#define R_VECT_MASK_CLR__serial__BITNR 8
-#define R_VECT_MASK_CLR__serial__WIDTH 1
-#define R_VECT_MASK_CLR__serial__clr 1
-#define R_VECT_MASK_CLR__serial__nop 0
-#define R_VECT_MASK_CLR__snmp__BITNR 7
-#define R_VECT_MASK_CLR__snmp__WIDTH 1
-#define R_VECT_MASK_CLR__snmp__clr 1
-#define R_VECT_MASK_CLR__snmp__nop 0
-#define R_VECT_MASK_CLR__network__BITNR 6
-#define R_VECT_MASK_CLR__network__WIDTH 1
-#define R_VECT_MASK_CLR__network__clr 1
-#define R_VECT_MASK_CLR__network__nop 0
-#define R_VECT_MASK_CLR__scsi1__BITNR 5
-#define R_VECT_MASK_CLR__scsi1__WIDTH 1
-#define R_VECT_MASK_CLR__scsi1__clr 1
-#define R_VECT_MASK_CLR__scsi1__nop 0
-#define R_VECT_MASK_CLR__par1__BITNR 5
-#define R_VECT_MASK_CLR__par1__WIDTH 1
-#define R_VECT_MASK_CLR__par1__clr 1
-#define R_VECT_MASK_CLR__par1__nop 0
-#define R_VECT_MASK_CLR__scsi0__BITNR 4
-#define R_VECT_MASK_CLR__scsi0__WIDTH 1
-#define R_VECT_MASK_CLR__scsi0__clr 1
-#define R_VECT_MASK_CLR__scsi0__nop 0
-#define R_VECT_MASK_CLR__par0__BITNR 4
-#define R_VECT_MASK_CLR__par0__WIDTH 1
-#define R_VECT_MASK_CLR__par0__clr 1
-#define R_VECT_MASK_CLR__par0__nop 0
-#define R_VECT_MASK_CLR__ata__BITNR 4
-#define R_VECT_MASK_CLR__ata__WIDTH 1
-#define R_VECT_MASK_CLR__ata__clr 1
-#define R_VECT_MASK_CLR__ata__nop 0
-#define R_VECT_MASK_CLR__mio__BITNR 4
-#define R_VECT_MASK_CLR__mio__WIDTH 1
-#define R_VECT_MASK_CLR__mio__clr 1
-#define R_VECT_MASK_CLR__mio__nop 0
-#define R_VECT_MASK_CLR__timer1__BITNR 3
-#define R_VECT_MASK_CLR__timer1__WIDTH 1
-#define R_VECT_MASK_CLR__timer1__clr 1
-#define R_VECT_MASK_CLR__timer1__nop 0
-#define R_VECT_MASK_CLR__timer0__BITNR 2
-#define R_VECT_MASK_CLR__timer0__WIDTH 1
-#define R_VECT_MASK_CLR__timer0__clr 1
-#define R_VECT_MASK_CLR__timer0__nop 0
-#define R_VECT_MASK_CLR__nmi__BITNR 1
-#define R_VECT_MASK_CLR__nmi__WIDTH 1
-#define R_VECT_MASK_CLR__nmi__clr 1
-#define R_VECT_MASK_CLR__nmi__nop 0
-#define R_VECT_MASK_CLR__some__BITNR 0
-#define R_VECT_MASK_CLR__some__WIDTH 1
-#define R_VECT_MASK_CLR__some__clr 1
-#define R_VECT_MASK_CLR__some__nop 0
-
-#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc)
-#define R_VECT_READ__usb__BITNR 31
-#define R_VECT_READ__usb__WIDTH 1
-#define R_VECT_READ__usb__active 1
-#define R_VECT_READ__usb__inactive 0
-#define R_VECT_READ__dma9__BITNR 25
-#define R_VECT_READ__dma9__WIDTH 1
-#define R_VECT_READ__dma9__active 1
-#define R_VECT_READ__dma9__inactive 0
-#define R_VECT_READ__dma8__BITNR 24
-#define R_VECT_READ__dma8__WIDTH 1
-#define R_VECT_READ__dma8__active 1
-#define R_VECT_READ__dma8__inactive 0
-#define R_VECT_READ__dma7__BITNR 23
-#define R_VECT_READ__dma7__WIDTH 1
-#define R_VECT_READ__dma7__active 1
-#define R_VECT_READ__dma7__inactive 0
-#define R_VECT_READ__dma6__BITNR 22
-#define R_VECT_READ__dma6__WIDTH 1
-#define R_VECT_READ__dma6__active 1
-#define R_VECT_READ__dma6__inactive 0
-#define R_VECT_READ__dma5__BITNR 21
-#define R_VECT_READ__dma5__WIDTH 1
-#define R_VECT_READ__dma5__active 1
-#define R_VECT_READ__dma5__inactive 0
-#define R_VECT_READ__dma4__BITNR 20
-#define R_VECT_READ__dma4__WIDTH 1
-#define R_VECT_READ__dma4__active 1
-#define R_VECT_READ__dma4__inactive 0
-#define R_VECT_READ__dma3__BITNR 19
-#define R_VECT_READ__dma3__WIDTH 1
-#define R_VECT_READ__dma3__active 1
-#define R_VECT_READ__dma3__inactive 0
-#define R_VECT_READ__dma2__BITNR 18
-#define R_VECT_READ__dma2__WIDTH 1
-#define R_VECT_READ__dma2__active 1
-#define R_VECT_READ__dma2__inactive 0
-#define R_VECT_READ__dma1__BITNR 17
-#define R_VECT_READ__dma1__WIDTH 1
-#define R_VECT_READ__dma1__active 1
-#define R_VECT_READ__dma1__inactive 0
-#define R_VECT_READ__dma0__BITNR 16
-#define R_VECT_READ__dma0__WIDTH 1
-#define R_VECT_READ__dma0__active 1
-#define R_VECT_READ__dma0__inactive 0
-#define R_VECT_READ__ext_dma1__BITNR 13
-#define R_VECT_READ__ext_dma1__WIDTH 1
-#define R_VECT_READ__ext_dma1__active 1
-#define R_VECT_READ__ext_dma1__inactive 0
-#define R_VECT_READ__ext_dma0__BITNR 12
-#define R_VECT_READ__ext_dma0__WIDTH 1
-#define R_VECT_READ__ext_dma0__active 1
-#define R_VECT_READ__ext_dma0__inactive 0
-#define R_VECT_READ__pa__BITNR 11
-#define R_VECT_READ__pa__WIDTH 1
-#define R_VECT_READ__pa__active 1
-#define R_VECT_READ__pa__inactive 0
-#define R_VECT_READ__irq_intnr__BITNR 10
-#define R_VECT_READ__irq_intnr__WIDTH 1
-#define R_VECT_READ__irq_intnr__active 1
-#define R_VECT_READ__irq_intnr__inactive 0
-#define R_VECT_READ__sw__BITNR 9
-#define R_VECT_READ__sw__WIDTH 1
-#define R_VECT_READ__sw__active 1
-#define R_VECT_READ__sw__inactive 0
-#define R_VECT_READ__serial__BITNR 8
-#define R_VECT_READ__serial__WIDTH 1
-#define R_VECT_READ__serial__active 1
-#define R_VECT_READ__serial__inactive 0
-#define R_VECT_READ__snmp__BITNR 7
-#define R_VECT_READ__snmp__WIDTH 1
-#define R_VECT_READ__snmp__active 1
-#define R_VECT_READ__snmp__inactive 0
-#define R_VECT_READ__network__BITNR 6
-#define R_VECT_READ__network__WIDTH 1
-#define R_VECT_READ__network__active 1
-#define R_VECT_READ__network__inactive 0
-#define R_VECT_READ__scsi1__BITNR 5
-#define R_VECT_READ__scsi1__WIDTH 1
-#define R_VECT_READ__scsi1__active 1
-#define R_VECT_READ__scsi1__inactive 0
-#define R_VECT_READ__par1__BITNR 5
-#define R_VECT_READ__par1__WIDTH 1
-#define R_VECT_READ__par1__active 1
-#define R_VECT_READ__par1__inactive 0
-#define R_VECT_READ__scsi0__BITNR 4
-#define R_VECT_READ__scsi0__WIDTH 1
-#define R_VECT_READ__scsi0__active 1
-#define R_VECT_READ__scsi0__inactive 0
-#define R_VECT_READ__par0__BITNR 4
-#define R_VECT_READ__par0__WIDTH 1
-#define R_VECT_READ__par0__active 1
-#define R_VECT_READ__par0__inactive 0
-#define R_VECT_READ__ata__BITNR 4
-#define R_VECT_READ__ata__WIDTH 1
-#define R_VECT_READ__ata__active 1
-#define R_VECT_READ__ata__inactive 0
-#define R_VECT_READ__mio__BITNR 4
-#define R_VECT_READ__mio__WIDTH 1
-#define R_VECT_READ__mio__active 1
-#define R_VECT_READ__mio__inactive 0
-#define R_VECT_READ__timer1__BITNR 3
-#define R_VECT_READ__timer1__WIDTH 1
-#define R_VECT_READ__timer1__active 1
-#define R_VECT_READ__timer1__inactive 0
-#define R_VECT_READ__timer0__BITNR 2
-#define R_VECT_READ__timer0__WIDTH 1
-#define R_VECT_READ__timer0__active 1
-#define R_VECT_READ__timer0__inactive 0
-#define R_VECT_READ__nmi__BITNR 1
-#define R_VECT_READ__nmi__WIDTH 1
-#define R_VECT_READ__nmi__active 1
-#define R_VECT_READ__nmi__inactive 0
-#define R_VECT_READ__some__BITNR 0
-#define R_VECT_READ__some__WIDTH 1
-#define R_VECT_READ__some__active 1
-#define R_VECT_READ__some__inactive 0
-
-#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc)
-#define R_VECT_MASK_SET__usb__BITNR 31
-#define R_VECT_MASK_SET__usb__WIDTH 1
-#define R_VECT_MASK_SET__usb__set 1
-#define R_VECT_MASK_SET__usb__nop 0
-#define R_VECT_MASK_SET__dma9__BITNR 25
-#define R_VECT_MASK_SET__dma9__WIDTH 1
-#define R_VECT_MASK_SET__dma9__set 1
-#define R_VECT_MASK_SET__dma9__nop 0
-#define R_VECT_MASK_SET__dma8__BITNR 24
-#define R_VECT_MASK_SET__dma8__WIDTH 1
-#define R_VECT_MASK_SET__dma8__set 1
-#define R_VECT_MASK_SET__dma8__nop 0
-#define R_VECT_MASK_SET__dma7__BITNR 23
-#define R_VECT_MASK_SET__dma7__WIDTH 1
-#define R_VECT_MASK_SET__dma7__set 1
-#define R_VECT_MASK_SET__dma7__nop 0
-#define R_VECT_MASK_SET__dma6__BITNR 22
-#define R_VECT_MASK_SET__dma6__WIDTH 1
-#define R_VECT_MASK_SET__dma6__set 1
-#define R_VECT_MASK_SET__dma6__nop 0
-#define R_VECT_MASK_SET__dma5__BITNR 21
-#define R_VECT_MASK_SET__dma5__WIDTH 1
-#define R_VECT_MASK_SET__dma5__set 1
-#define R_VECT_MASK_SET__dma5__nop 0
-#define R_VECT_MASK_SET__dma4__BITNR 20
-#define R_VECT_MASK_SET__dma4__WIDTH 1
-#define R_VECT_MASK_SET__dma4__set 1
-#define R_VECT_MASK_SET__dma4__nop 0
-#define R_VECT_MASK_SET__dma3__BITNR 19
-#define R_VECT_MASK_SET__dma3__WIDTH 1
-#define R_VECT_MASK_SET__dma3__set 1
-#define R_VECT_MASK_SET__dma3__nop 0
-#define R_VECT_MASK_SET__dma2__BITNR 18
-#define R_VECT_MASK_SET__dma2__WIDTH 1
-#define R_VECT_MASK_SET__dma2__set 1
-#define R_VECT_MASK_SET__dma2__nop 0
-#define R_VECT_MASK_SET__dma1__BITNR 17
-#define R_VECT_MASK_SET__dma1__WIDTH 1
-#define R_VECT_MASK_SET__dma1__set 1
-#define R_VECT_MASK_SET__dma1__nop 0
-#define R_VECT_MASK_SET__dma0__BITNR 16
-#define R_VECT_MASK_SET__dma0__WIDTH 1
-#define R_VECT_MASK_SET__dma0__set 1
-#define R_VECT_MASK_SET__dma0__nop 0
-#define R_VECT_MASK_SET__ext_dma1__BITNR 13
-#define R_VECT_MASK_SET__ext_dma1__WIDTH 1
-#define R_VECT_MASK_SET__ext_dma1__set 1
-#define R_VECT_MASK_SET__ext_dma1__nop 0
-#define R_VECT_MASK_SET__ext_dma0__BITNR 12
-#define R_VECT_MASK_SET__ext_dma0__WIDTH 1
-#define R_VECT_MASK_SET__ext_dma0__set 1
-#define R_VECT_MASK_SET__ext_dma0__nop 0
-#define R_VECT_MASK_SET__pa__BITNR 11
-#define R_VECT_MASK_SET__pa__WIDTH 1
-#define R_VECT_MASK_SET__pa__set 1
-#define R_VECT_MASK_SET__pa__nop 0
-#define R_VECT_MASK_SET__irq_intnr__BITNR 10
-#define R_VECT_MASK_SET__irq_intnr__WIDTH 1
-#define R_VECT_MASK_SET__irq_intnr__set 1
-#define R_VECT_MASK_SET__irq_intnr__nop 0
-#define R_VECT_MASK_SET__sw__BITNR 9
-#define R_VECT_MASK_SET__sw__WIDTH 1
-#define R_VECT_MASK_SET__sw__set 1
-#define R_VECT_MASK_SET__sw__nop 0
-#define R_VECT_MASK_SET__serial__BITNR 8
-#define R_VECT_MASK_SET__serial__WIDTH 1
-#define R_VECT_MASK_SET__serial__set 1
-#define R_VECT_MASK_SET__serial__nop 0
-#define R_VECT_MASK_SET__snmp__BITNR 7
-#define R_VECT_MASK_SET__snmp__WIDTH 1
-#define R_VECT_MASK_SET__snmp__set 1
-#define R_VECT_MASK_SET__snmp__nop 0
-#define R_VECT_MASK_SET__network__BITNR 6
-#define R_VECT_MASK_SET__network__WIDTH 1
-#define R_VECT_MASK_SET__network__set 1
-#define R_VECT_MASK_SET__network__nop 0
-#define R_VECT_MASK_SET__scsi1__BITNR 5
-#define R_VECT_MASK_SET__scsi1__WIDTH 1
-#define R_VECT_MASK_SET__scsi1__set 1
-#define R_VECT_MASK_SET__scsi1__nop 0
-#define R_VECT_MASK_SET__par1__BITNR 5
-#define R_VECT_MASK_SET__par1__WIDTH 1
-#define R_VECT_MASK_SET__par1__set 1
-#define R_VECT_MASK_SET__par1__nop 0
-#define R_VECT_MASK_SET__scsi0__BITNR 4
-#define R_VECT_MASK_SET__scsi0__WIDTH 1
-#define R_VECT_MASK_SET__scsi0__set 1
-#define R_VECT_MASK_SET__scsi0__nop 0
-#define R_VECT_MASK_SET__par0__BITNR 4
-#define R_VECT_MASK_SET__par0__WIDTH 1
-#define R_VECT_MASK_SET__par0__set 1
-#define R_VECT_MASK_SET__par0__nop 0
-#define R_VECT_MASK_SET__ata__BITNR 4
-#define R_VECT_MASK_SET__ata__WIDTH 1
-#define R_VECT_MASK_SET__ata__set 1
-#define R_VECT_MASK_SET__ata__nop 0
-#define R_VECT_MASK_SET__mio__BITNR 4
-#define R_VECT_MASK_SET__mio__WIDTH 1
-#define R_VECT_MASK_SET__mio__set 1
-#define R_VECT_MASK_SET__mio__nop 0
-#define R_VECT_MASK_SET__timer1__BITNR 3
-#define R_VECT_MASK_SET__timer1__WIDTH 1
-#define R_VECT_MASK_SET__timer1__set 1
-#define R_VECT_MASK_SET__timer1__nop 0
-#define R_VECT_MASK_SET__timer0__BITNR 2
-#define R_VECT_MASK_SET__timer0__WIDTH 1
-#define R_VECT_MASK_SET__timer0__set 1
-#define R_VECT_MASK_SET__timer0__nop 0
-#define R_VECT_MASK_SET__nmi__BITNR 1
-#define R_VECT_MASK_SET__nmi__WIDTH 1
-#define R_VECT_MASK_SET__nmi__set 1
-#define R_VECT_MASK_SET__nmi__nop 0
-#define R_VECT_MASK_SET__some__BITNR 0
-#define R_VECT_MASK_SET__some__WIDTH 1
-#define R_VECT_MASK_SET__some__set 1
-#define R_VECT_MASK_SET__some__nop 0
-
-/*
-!* DMA registers
-!*/
-
-#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c)
-#define R_SET_EOP__ch9_eop__BITNR 3
-#define R_SET_EOP__ch9_eop__WIDTH 1
-#define R_SET_EOP__ch9_eop__set 1
-#define R_SET_EOP__ch9_eop__nop 0
-#define R_SET_EOP__ch7_eop__BITNR 2
-#define R_SET_EOP__ch7_eop__WIDTH 1
-#define R_SET_EOP__ch7_eop__set 1
-#define R_SET_EOP__ch7_eop__nop 0
-#define R_SET_EOP__ch5_eop__BITNR 1
-#define R_SET_EOP__ch5_eop__WIDTH 1
-#define R_SET_EOP__ch5_eop__set 1
-#define R_SET_EOP__ch5_eop__nop 0
-#define R_SET_EOP__ch3_eop__BITNR 0
-#define R_SET_EOP__ch3_eop__WIDTH 1
-#define R_SET_EOP__ch3_eop__set 1
-#define R_SET_EOP__ch3_eop__nop 0
-
-#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100)
-#define R_DMA_CH0_HWSW__hw__BITNR 16
-#define R_DMA_CH0_HWSW__hw__WIDTH 16
-#define R_DMA_CH0_HWSW__sw__BITNR 0
-#define R_DMA_CH0_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c)
-#define R_DMA_CH0_DESCR__descr__BITNR 0
-#define R_DMA_CH0_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104)
-#define R_DMA_CH0_NEXT__next__BITNR 0
-#define R_DMA_CH0_NEXT__next__WIDTH 32
-
-#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108)
-#define R_DMA_CH0_BUF__buf__BITNR 0
-#define R_DMA_CH0_BUF__buf__WIDTH 32
-
-#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0)
-#define R_DMA_CH0_FIRST__first__BITNR 0
-#define R_DMA_CH0_FIRST__first__WIDTH 32
-
-#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0)
-#define R_DMA_CH0_CMD__cmd__BITNR 0
-#define R_DMA_CH0_CMD__cmd__WIDTH 3
-#define R_DMA_CH0_CMD__cmd__hold 0
-#define R_DMA_CH0_CMD__cmd__start 1
-#define R_DMA_CH0_CMD__cmd__restart 3
-#define R_DMA_CH0_CMD__cmd__continue 3
-#define R_DMA_CH0_CMD__cmd__reset 4
-
-#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1)
-#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH0_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2)
-#define R_DMA_CH0_STATUS__avail__BITNR 0
-#define R_DMA_CH0_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110)
-#define R_DMA_CH1_HWSW__hw__BITNR 16
-#define R_DMA_CH1_HWSW__hw__WIDTH 16
-#define R_DMA_CH1_HWSW__sw__BITNR 0
-#define R_DMA_CH1_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c)
-#define R_DMA_CH1_DESCR__descr__BITNR 0
-#define R_DMA_CH1_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114)
-#define R_DMA_CH1_NEXT__next__BITNR 0
-#define R_DMA_CH1_NEXT__next__WIDTH 32
-
-#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118)
-#define R_DMA_CH1_BUF__buf__BITNR 0
-#define R_DMA_CH1_BUF__buf__WIDTH 32
-
-#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4)
-#define R_DMA_CH1_FIRST__first__BITNR 0
-#define R_DMA_CH1_FIRST__first__WIDTH 32
-
-#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4)
-#define R_DMA_CH1_CMD__cmd__BITNR 0
-#define R_DMA_CH1_CMD__cmd__WIDTH 3
-#define R_DMA_CH1_CMD__cmd__hold 0
-#define R_DMA_CH1_CMD__cmd__start 1
-#define R_DMA_CH1_CMD__cmd__restart 3
-#define R_DMA_CH1_CMD__cmd__continue 3
-#define R_DMA_CH1_CMD__cmd__reset 4
-
-#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5)
-#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH1_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6)
-#define R_DMA_CH1_STATUS__avail__BITNR 0
-#define R_DMA_CH1_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120)
-#define R_DMA_CH2_HWSW__hw__BITNR 16
-#define R_DMA_CH2_HWSW__hw__WIDTH 16
-#define R_DMA_CH2_HWSW__sw__BITNR 0
-#define R_DMA_CH2_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c)
-#define R_DMA_CH2_DESCR__descr__BITNR 0
-#define R_DMA_CH2_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124)
-#define R_DMA_CH2_NEXT__next__BITNR 0
-#define R_DMA_CH2_NEXT__next__WIDTH 32
-
-#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128)
-#define R_DMA_CH2_BUF__buf__BITNR 0
-#define R_DMA_CH2_BUF__buf__WIDTH 32
-
-#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8)
-#define R_DMA_CH2_FIRST__first__BITNR 0
-#define R_DMA_CH2_FIRST__first__WIDTH 32
-
-#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8)
-#define R_DMA_CH2_CMD__cmd__BITNR 0
-#define R_DMA_CH2_CMD__cmd__WIDTH 3
-#define R_DMA_CH2_CMD__cmd__hold 0
-#define R_DMA_CH2_CMD__cmd__start 1
-#define R_DMA_CH2_CMD__cmd__restart 3
-#define R_DMA_CH2_CMD__cmd__continue 3
-#define R_DMA_CH2_CMD__cmd__reset 4
-
-#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9)
-#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH2_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da)
-#define R_DMA_CH2_STATUS__avail__BITNR 0
-#define R_DMA_CH2_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130)
-#define R_DMA_CH3_HWSW__hw__BITNR 16
-#define R_DMA_CH3_HWSW__hw__WIDTH 16
-#define R_DMA_CH3_HWSW__sw__BITNR 0
-#define R_DMA_CH3_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c)
-#define R_DMA_CH3_DESCR__descr__BITNR 0
-#define R_DMA_CH3_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134)
-#define R_DMA_CH3_NEXT__next__BITNR 0
-#define R_DMA_CH3_NEXT__next__WIDTH 32
-
-#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138)
-#define R_DMA_CH3_BUF__buf__BITNR 0
-#define R_DMA_CH3_BUF__buf__WIDTH 32
-
-#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac)
-#define R_DMA_CH3_FIRST__first__BITNR 0
-#define R_DMA_CH3_FIRST__first__WIDTH 32
-
-#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc)
-#define R_DMA_CH3_CMD__cmd__BITNR 0
-#define R_DMA_CH3_CMD__cmd__WIDTH 3
-#define R_DMA_CH3_CMD__cmd__hold 0
-#define R_DMA_CH3_CMD__cmd__start 1
-#define R_DMA_CH3_CMD__cmd__restart 3
-#define R_DMA_CH3_CMD__cmd__continue 3
-#define R_DMA_CH3_CMD__cmd__reset 4
-
-#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd)
-#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH3_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de)
-#define R_DMA_CH3_STATUS__avail__BITNR 0
-#define R_DMA_CH3_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140)
-#define R_DMA_CH4_HWSW__hw__BITNR 16
-#define R_DMA_CH4_HWSW__hw__WIDTH 16
-#define R_DMA_CH4_HWSW__sw__BITNR 0
-#define R_DMA_CH4_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c)
-#define R_DMA_CH4_DESCR__descr__BITNR 0
-#define R_DMA_CH4_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144)
-#define R_DMA_CH4_NEXT__next__BITNR 0
-#define R_DMA_CH4_NEXT__next__WIDTH 32
-
-#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148)
-#define R_DMA_CH4_BUF__buf__BITNR 0
-#define R_DMA_CH4_BUF__buf__WIDTH 32
-
-#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0)
-#define R_DMA_CH4_FIRST__first__BITNR 0
-#define R_DMA_CH4_FIRST__first__WIDTH 32
-
-#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0)
-#define R_DMA_CH4_CMD__cmd__BITNR 0
-#define R_DMA_CH4_CMD__cmd__WIDTH 3
-#define R_DMA_CH4_CMD__cmd__hold 0
-#define R_DMA_CH4_CMD__cmd__start 1
-#define R_DMA_CH4_CMD__cmd__restart 3
-#define R_DMA_CH4_CMD__cmd__continue 3
-#define R_DMA_CH4_CMD__cmd__reset 4
-
-#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1)
-#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH4_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2)
-#define R_DMA_CH4_STATUS__avail__BITNR 0
-#define R_DMA_CH4_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150)
-#define R_DMA_CH5_HWSW__hw__BITNR 16
-#define R_DMA_CH5_HWSW__hw__WIDTH 16
-#define R_DMA_CH5_HWSW__sw__BITNR 0
-#define R_DMA_CH5_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c)
-#define R_DMA_CH5_DESCR__descr__BITNR 0
-#define R_DMA_CH5_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154)
-#define R_DMA_CH5_NEXT__next__BITNR 0
-#define R_DMA_CH5_NEXT__next__WIDTH 32
-
-#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158)
-#define R_DMA_CH5_BUF__buf__BITNR 0
-#define R_DMA_CH5_BUF__buf__WIDTH 32
-
-#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4)
-#define R_DMA_CH5_FIRST__first__BITNR 0
-#define R_DMA_CH5_FIRST__first__WIDTH 32
-
-#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4)
-#define R_DMA_CH5_CMD__cmd__BITNR 0
-#define R_DMA_CH5_CMD__cmd__WIDTH 3
-#define R_DMA_CH5_CMD__cmd__hold 0
-#define R_DMA_CH5_CMD__cmd__start 1
-#define R_DMA_CH5_CMD__cmd__restart 3
-#define R_DMA_CH5_CMD__cmd__continue 3
-#define R_DMA_CH5_CMD__cmd__reset 4
-
-#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5)
-#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH5_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6)
-#define R_DMA_CH5_STATUS__avail__BITNR 0
-#define R_DMA_CH5_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160)
-#define R_DMA_CH6_HWSW__hw__BITNR 16
-#define R_DMA_CH6_HWSW__hw__WIDTH 16
-#define R_DMA_CH6_HWSW__sw__BITNR 0
-#define R_DMA_CH6_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c)
-#define R_DMA_CH6_DESCR__descr__BITNR 0
-#define R_DMA_CH6_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164)
-#define R_DMA_CH6_NEXT__next__BITNR 0
-#define R_DMA_CH6_NEXT__next__WIDTH 32
-
-#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168)
-#define R_DMA_CH6_BUF__buf__BITNR 0
-#define R_DMA_CH6_BUF__buf__WIDTH 32
-
-#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8)
-#define R_DMA_CH6_FIRST__first__BITNR 0
-#define R_DMA_CH6_FIRST__first__WIDTH 32
-
-#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8)
-#define R_DMA_CH6_CMD__cmd__BITNR 0
-#define R_DMA_CH6_CMD__cmd__WIDTH 3
-#define R_DMA_CH6_CMD__cmd__hold 0
-#define R_DMA_CH6_CMD__cmd__start 1
-#define R_DMA_CH6_CMD__cmd__restart 3
-#define R_DMA_CH6_CMD__cmd__continue 3
-#define R_DMA_CH6_CMD__cmd__reset 4
-
-#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9)
-#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH6_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea)
-#define R_DMA_CH6_STATUS__avail__BITNR 0
-#define R_DMA_CH6_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170)
-#define R_DMA_CH7_HWSW__hw__BITNR 16
-#define R_DMA_CH7_HWSW__hw__WIDTH 16
-#define R_DMA_CH7_HWSW__sw__BITNR 0
-#define R_DMA_CH7_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c)
-#define R_DMA_CH7_DESCR__descr__BITNR 0
-#define R_DMA_CH7_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174)
-#define R_DMA_CH7_NEXT__next__BITNR 0
-#define R_DMA_CH7_NEXT__next__WIDTH 32
-
-#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178)
-#define R_DMA_CH7_BUF__buf__BITNR 0
-#define R_DMA_CH7_BUF__buf__WIDTH 32
-
-#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc)
-#define R_DMA_CH7_FIRST__first__BITNR 0
-#define R_DMA_CH7_FIRST__first__WIDTH 32
-
-#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec)
-#define R_DMA_CH7_CMD__cmd__BITNR 0
-#define R_DMA_CH7_CMD__cmd__WIDTH 3
-#define R_DMA_CH7_CMD__cmd__hold 0
-#define R_DMA_CH7_CMD__cmd__start 1
-#define R_DMA_CH7_CMD__cmd__restart 3
-#define R_DMA_CH7_CMD__cmd__continue 3
-#define R_DMA_CH7_CMD__cmd__reset 4
-
-#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed)
-#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH7_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee)
-#define R_DMA_CH7_STATUS__avail__BITNR 0
-#define R_DMA_CH7_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180)
-#define R_DMA_CH8_HWSW__hw__BITNR 16
-#define R_DMA_CH8_HWSW__hw__WIDTH 16
-#define R_DMA_CH8_HWSW__sw__BITNR 0
-#define R_DMA_CH8_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c)
-#define R_DMA_CH8_DESCR__descr__BITNR 0
-#define R_DMA_CH8_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184)
-#define R_DMA_CH8_NEXT__next__BITNR 0
-#define R_DMA_CH8_NEXT__next__WIDTH 32
-
-#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188)
-#define R_DMA_CH8_BUF__buf__BITNR 0
-#define R_DMA_CH8_BUF__buf__WIDTH 32
-
-#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0)
-#define R_DMA_CH8_FIRST__first__BITNR 0
-#define R_DMA_CH8_FIRST__first__WIDTH 32
-
-#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0)
-#define R_DMA_CH8_CMD__cmd__BITNR 0
-#define R_DMA_CH8_CMD__cmd__WIDTH 3
-#define R_DMA_CH8_CMD__cmd__hold 0
-#define R_DMA_CH8_CMD__cmd__start 1
-#define R_DMA_CH8_CMD__cmd__restart 3
-#define R_DMA_CH8_CMD__cmd__continue 3
-#define R_DMA_CH8_CMD__cmd__reset 4
-
-#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1)
-#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2)
-#define R_DMA_CH8_STATUS__avail__BITNR 0
-#define R_DMA_CH8_STATUS__avail__WIDTH 7
-
-#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c)
-#define R_DMA_CH8_SUB__sub__BITNR 0
-#define R_DMA_CH8_SUB__sub__WIDTH 32
-
-#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0)
-#define R_DMA_CH8_NEP__nep__BITNR 0
-#define R_DMA_CH8_NEP__nep__WIDTH 32
-
-#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8)
-#define R_DMA_CH8_SUB0_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3)
-#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB0_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB0_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3)
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc)
-#define R_DMA_CH8_SUB1_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7)
-#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB1_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB1_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7)
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8)
-#define R_DMA_CH8_SUB2_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db)
-#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB2_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB2_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb)
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc)
-#define R_DMA_CH8_SUB3_EP__ep__BITNR 0
-#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32
-
-#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df)
-#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0
-#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1
-#define R_DMA_CH8_SUB3_CMD__cmd__stop 0
-#define R_DMA_CH8_SUB3_CMD__cmd__start 1
-
-#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef)
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0
-#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1
-
-#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190)
-#define R_DMA_CH9_HWSW__hw__BITNR 16
-#define R_DMA_CH9_HWSW__hw__WIDTH 16
-#define R_DMA_CH9_HWSW__sw__BITNR 0
-#define R_DMA_CH9_HWSW__sw__WIDTH 16
-
-#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c)
-#define R_DMA_CH9_DESCR__descr__BITNR 0
-#define R_DMA_CH9_DESCR__descr__WIDTH 32
-
-#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194)
-#define R_DMA_CH9_NEXT__next__BITNR 0
-#define R_DMA_CH9_NEXT__next__WIDTH 32
-
-#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198)
-#define R_DMA_CH9_BUF__buf__BITNR 0
-#define R_DMA_CH9_BUF__buf__WIDTH 32
-
-#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4)
-#define R_DMA_CH9_FIRST__first__BITNR 0
-#define R_DMA_CH9_FIRST__first__WIDTH 32
-
-#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4)
-#define R_DMA_CH9_CMD__cmd__BITNR 0
-#define R_DMA_CH9_CMD__cmd__WIDTH 3
-#define R_DMA_CH9_CMD__cmd__hold 0
-#define R_DMA_CH9_CMD__cmd__start 1
-#define R_DMA_CH9_CMD__cmd__restart 3
-#define R_DMA_CH9_CMD__cmd__continue 3
-#define R_DMA_CH9_CMD__cmd__reset 4
-
-#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5)
-#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__do 1
-#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0
-#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0
-#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1
-#define R_DMA_CH9_CLR_INTR__clr_descr__do 1
-#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0
-
-#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6)
-#define R_DMA_CH9_STATUS__avail__BITNR 0
-#define R_DMA_CH9_STATUS__avail__WIDTH 7
-
-/*
-!* Test mode registers
-!*/
-
-#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc)
-#define R_TEST_MODE__single_step__BITNR 19
-#define R_TEST_MODE__single_step__WIDTH 1
-#define R_TEST_MODE__single_step__on 1
-#define R_TEST_MODE__single_step__off 0
-#define R_TEST_MODE__step_wr__BITNR 18
-#define R_TEST_MODE__step_wr__WIDTH 1
-#define R_TEST_MODE__step_wr__on 1
-#define R_TEST_MODE__step_wr__off 0
-#define R_TEST_MODE__step_rd__BITNR 17
-#define R_TEST_MODE__step_rd__WIDTH 1
-#define R_TEST_MODE__step_rd__on 1
-#define R_TEST_MODE__step_rd__off 0
-#define R_TEST_MODE__step_fetch__BITNR 16
-#define R_TEST_MODE__step_fetch__WIDTH 1
-#define R_TEST_MODE__step_fetch__on 1
-#define R_TEST_MODE__step_fetch__off 0
-#define R_TEST_MODE__mmu_test__BITNR 12
-#define R_TEST_MODE__mmu_test__WIDTH 1
-#define R_TEST_MODE__mmu_test__on 1
-#define R_TEST_MODE__mmu_test__off 0
-#define R_TEST_MODE__usb_test__BITNR 11
-#define R_TEST_MODE__usb_test__WIDTH 1
-#define R_TEST_MODE__usb_test__on 1
-#define R_TEST_MODE__usb_test__off 0
-#define R_TEST_MODE__scsi_timer_test__BITNR 10
-#define R_TEST_MODE__scsi_timer_test__WIDTH 1
-#define R_TEST_MODE__scsi_timer_test__on 1
-#define R_TEST_MODE__scsi_timer_test__off 0
-#define R_TEST_MODE__backoff__BITNR 9
-#define R_TEST_MODE__backoff__WIDTH 1
-#define R_TEST_MODE__backoff__on 1
-#define R_TEST_MODE__backoff__off 0
-#define R_TEST_MODE__snmp_test__BITNR 8
-#define R_TEST_MODE__snmp_test__WIDTH 1
-#define R_TEST_MODE__snmp_test__on 1
-#define R_TEST_MODE__snmp_test__off 0
-#define R_TEST_MODE__snmp_inc__BITNR 7
-#define R_TEST_MODE__snmp_inc__WIDTH 1
-#define R_TEST_MODE__snmp_inc__do 1
-#define R_TEST_MODE__snmp_inc__dont 0
-#define R_TEST_MODE__ser_loop__BITNR 6
-#define R_TEST_MODE__ser_loop__WIDTH 1
-#define R_TEST_MODE__ser_loop__on 1
-#define R_TEST_MODE__ser_loop__off 0
-#define R_TEST_MODE__baudrate__BITNR 5
-#define R_TEST_MODE__baudrate__WIDTH 1
-#define R_TEST_MODE__baudrate__on 1
-#define R_TEST_MODE__baudrate__off 0
-#define R_TEST_MODE__timer__BITNR 3
-#define R_TEST_MODE__timer__WIDTH 2
-#define R_TEST_MODE__timer__off 0
-#define R_TEST_MODE__timer__even 1
-#define R_TEST_MODE__timer__odd 2
-#define R_TEST_MODE__timer__all 3
-#define R_TEST_MODE__cache_test__BITNR 2
-#define R_TEST_MODE__cache_test__WIDTH 1
-#define R_TEST_MODE__cache_test__normal 0
-#define R_TEST_MODE__cache_test__test 1
-#define R_TEST_MODE__tag_test__BITNR 1
-#define R_TEST_MODE__tag_test__WIDTH 1
-#define R_TEST_MODE__tag_test__normal 0
-#define R_TEST_MODE__tag_test__test 1
-#define R_TEST_MODE__cache_enable__BITNR 0
-#define R_TEST_MODE__cache_enable__WIDTH 1
-#define R_TEST_MODE__cache_enable__enable 1
-#define R_TEST_MODE__cache_enable__disable 0
-
-#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe)
-#define R_SINGLE_STEP__single_step__BITNR 3
-#define R_SINGLE_STEP__single_step__WIDTH 1
-#define R_SINGLE_STEP__single_step__on 1
-#define R_SINGLE_STEP__single_step__off 0
-#define R_SINGLE_STEP__step_wr__BITNR 2
-#define R_SINGLE_STEP__step_wr__WIDTH 1
-#define R_SINGLE_STEP__step_wr__on 1
-#define R_SINGLE_STEP__step_wr__off 0
-#define R_SINGLE_STEP__step_rd__BITNR 1
-#define R_SINGLE_STEP__step_rd__WIDTH 1
-#define R_SINGLE_STEP__step_rd__on 1
-#define R_SINGLE_STEP__step_rd__off 0
-#define R_SINGLE_STEP__step_fetch__BITNR 0
-#define R_SINGLE_STEP__step_fetch__WIDTH 1
-#define R_SINGLE_STEP__step_fetch__on 1
-#define R_SINGLE_STEP__step_fetch__off 0
-
-/*
-!* USB interface control registers
-!*/
-
-#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200)
-#define R_USB_REVISION__major__BITNR 4
-#define R_USB_REVISION__major__WIDTH 4
-#define R_USB_REVISION__minor__BITNR 0
-#define R_USB_REVISION__minor__WIDTH 4
-
-#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201)
-#define R_USB_COMMAND__port_sel__BITNR 6
-#define R_USB_COMMAND__port_sel__WIDTH 2
-#define R_USB_COMMAND__port_sel__nop 0
-#define R_USB_COMMAND__port_sel__port1 1
-#define R_USB_COMMAND__port_sel__port2 2
-#define R_USB_COMMAND__port_sel__both 3
-#define R_USB_COMMAND__port_cmd__BITNR 4
-#define R_USB_COMMAND__port_cmd__WIDTH 2
-#define R_USB_COMMAND__port_cmd__reset 0
-#define R_USB_COMMAND__port_cmd__disable 1
-#define R_USB_COMMAND__port_cmd__suspend 2
-#define R_USB_COMMAND__port_cmd__resume 3
-#define R_USB_COMMAND__busy__BITNR 3
-#define R_USB_COMMAND__busy__WIDTH 1
-#define R_USB_COMMAND__busy__no 0
-#define R_USB_COMMAND__busy__yes 1
-#define R_USB_COMMAND__ctrl_cmd__BITNR 0
-#define R_USB_COMMAND__ctrl_cmd__WIDTH 3
-#define R_USB_COMMAND__ctrl_cmd__nop 0
-#define R_USB_COMMAND__ctrl_cmd__reset 1
-#define R_USB_COMMAND__ctrl_cmd__deconfig 2
-#define R_USB_COMMAND__ctrl_cmd__host_config 3
-#define R_USB_COMMAND__ctrl_cmd__dev_config 4
-#define R_USB_COMMAND__ctrl_cmd__host_nop 5
-#define R_USB_COMMAND__ctrl_cmd__host_run 6
-#define R_USB_COMMAND__ctrl_cmd__host_stop 7
-
-#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201)
-#define R_USB_COMMAND_DEV__port_sel__BITNR 6
-#define R_USB_COMMAND_DEV__port_sel__WIDTH 2
-#define R_USB_COMMAND_DEV__port_sel__nop 0
-#define R_USB_COMMAND_DEV__port_sel__dummy1 1
-#define R_USB_COMMAND_DEV__port_sel__dummy2 2
-#define R_USB_COMMAND_DEV__port_sel__any 3
-#define R_USB_COMMAND_DEV__port_cmd__BITNR 4
-#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2
-#define R_USB_COMMAND_DEV__port_cmd__active 0
-#define R_USB_COMMAND_DEV__port_cmd__passive 1
-#define R_USB_COMMAND_DEV__port_cmd__nop 2
-#define R_USB_COMMAND_DEV__port_cmd__wakeup 3
-#define R_USB_COMMAND_DEV__busy__BITNR 3
-#define R_USB_COMMAND_DEV__busy__WIDTH 1
-#define R_USB_COMMAND_DEV__busy__no 0
-#define R_USB_COMMAND_DEV__busy__yes 1
-#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
-#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3
-#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0
-#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1
-#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2
-#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6
-#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7
-
-#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202)
-#define R_USB_STATUS__ourun__BITNR 5
-#define R_USB_STATUS__ourun__WIDTH 1
-#define R_USB_STATUS__ourun__no 0
-#define R_USB_STATUS__ourun__yes 1
-#define R_USB_STATUS__perror__BITNR 4
-#define R_USB_STATUS__perror__WIDTH 1
-#define R_USB_STATUS__perror__no 0
-#define R_USB_STATUS__perror__yes 1
-#define R_USB_STATUS__device_mode__BITNR 3
-#define R_USB_STATUS__device_mode__WIDTH 1
-#define R_USB_STATUS__device_mode__no 0
-#define R_USB_STATUS__device_mode__yes 1
-#define R_USB_STATUS__host_mode__BITNR 2
-#define R_USB_STATUS__host_mode__WIDTH 1
-#define R_USB_STATUS__host_mode__no 0
-#define R_USB_STATUS__host_mode__yes 1
-#define R_USB_STATUS__started__BITNR 1
-#define R_USB_STATUS__started__WIDTH 1
-#define R_USB_STATUS__started__no 0
-#define R_USB_STATUS__started__yes 1
-#define R_USB_STATUS__running__BITNR 0
-#define R_USB_STATUS__running__WIDTH 1
-#define R_USB_STATUS__running__no 0
-#define R_USB_STATUS__running__yes 1
-
-#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__iso_eof__nop 0
-#define R_USB_IRQ_MASK_SET__iso_eof__set 1
-#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eof__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eof__set 1
-#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__iso_eot__nop 0
-#define R_USB_IRQ_MASK_SET__iso_eot__set 1
-#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__intr_eot__nop 0
-#define R_USB_IRQ_MASK_SET__intr_eot__set 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_SET__ctl_eot__set 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_SET__bulk_eot__set 1
-#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_SET__epid_attn__nop 0
-#define R_USB_IRQ_MASK_SET__epid_attn__set 1
-#define R_USB_IRQ_MASK_SET__sof__BITNR 2
-#define R_USB_IRQ_MASK_SET__sof__WIDTH 1
-#define R_USB_IRQ_MASK_SET__sof__nop 0
-#define R_USB_IRQ_MASK_SET__sof__set 1
-#define R_USB_IRQ_MASK_SET__port_status__BITNR 1
-#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET__port_status__nop 0
-#define R_USB_IRQ_MASK_SET__port_status__set 1
-#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET__ctl_status__nop 0
-#define R_USB_IRQ_MASK_SET__ctl_status__set 1
-
-#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0
-#define R_USB_IRQ_MASK_READ__iso_eof__pend 1
-#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eof__pend 1
-#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__iso_eot__pend 1
-#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__intr_eot__pend 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1
-#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0
-#define R_USB_IRQ_MASK_READ__epid_attn__pend 1
-#define R_USB_IRQ_MASK_READ__sof__BITNR 2
-#define R_USB_IRQ_MASK_READ__sof__WIDTH 1
-#define R_USB_IRQ_MASK_READ__sof__no_pend 0
-#define R_USB_IRQ_MASK_READ__sof__pend 1
-#define R_USB_IRQ_MASK_READ__port_status__BITNR 1
-#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ__port_status__no_pend 0
-#define R_USB_IRQ_MASK_READ__port_status__pend 1
-#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0
-#define R_USB_IRQ_MASK_READ__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206)
-#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
-#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0
-#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
-#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1
-#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
-#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
-#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
-#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
-#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0
-#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1
-#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0
-#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1
-#define R_USB_IRQ_MASK_CLR__sof__BITNR 2
-#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__sof__nop 0
-#define R_USB_IRQ_MASK_CLR__sof__clr 1
-#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1
-#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__port_status__nop 0
-#define R_USB_IRQ_MASK_CLR__port_status__clr 1
-#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0
-#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1
-
-#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206)
-#define R_USB_IRQ_READ__iso_eof__BITNR 13
-#define R_USB_IRQ_READ__iso_eof__WIDTH 1
-#define R_USB_IRQ_READ__iso_eof__no_pend 0
-#define R_USB_IRQ_READ__iso_eof__pend 1
-#define R_USB_IRQ_READ__intr_eof__BITNR 12
-#define R_USB_IRQ_READ__intr_eof__WIDTH 1
-#define R_USB_IRQ_READ__intr_eof__no_pend 0
-#define R_USB_IRQ_READ__intr_eof__pend 1
-#define R_USB_IRQ_READ__iso_eot__BITNR 11
-#define R_USB_IRQ_READ__iso_eot__WIDTH 1
-#define R_USB_IRQ_READ__iso_eot__no_pend 0
-#define R_USB_IRQ_READ__iso_eot__pend 1
-#define R_USB_IRQ_READ__intr_eot__BITNR 10
-#define R_USB_IRQ_READ__intr_eot__WIDTH 1
-#define R_USB_IRQ_READ__intr_eot__no_pend 0
-#define R_USB_IRQ_READ__intr_eot__pend 1
-#define R_USB_IRQ_READ__ctl_eot__BITNR 9
-#define R_USB_IRQ_READ__ctl_eot__WIDTH 1
-#define R_USB_IRQ_READ__ctl_eot__no_pend 0
-#define R_USB_IRQ_READ__ctl_eot__pend 1
-#define R_USB_IRQ_READ__bulk_eot__BITNR 8
-#define R_USB_IRQ_READ__bulk_eot__WIDTH 1
-#define R_USB_IRQ_READ__bulk_eot__no_pend 0
-#define R_USB_IRQ_READ__bulk_eot__pend 1
-#define R_USB_IRQ_READ__epid_attn__BITNR 3
-#define R_USB_IRQ_READ__epid_attn__WIDTH 1
-#define R_USB_IRQ_READ__epid_attn__no_pend 0
-#define R_USB_IRQ_READ__epid_attn__pend 1
-#define R_USB_IRQ_READ__sof__BITNR 2
-#define R_USB_IRQ_READ__sof__WIDTH 1
-#define R_USB_IRQ_READ__sof__no_pend 0
-#define R_USB_IRQ_READ__sof__pend 1
-#define R_USB_IRQ_READ__port_status__BITNR 1
-#define R_USB_IRQ_READ__port_status__WIDTH 1
-#define R_USB_IRQ_READ__port_status__no_pend 0
-#define R_USB_IRQ_READ__port_status__pend 1
-#define R_USB_IRQ_READ__ctl_status__BITNR 0
-#define R_USB_IRQ_READ__ctl_status__WIDTH 1
-#define R_USB_IRQ_READ__ctl_status__no_pend 0
-#define R_USB_IRQ_READ__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1
-#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__sof__set 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0
-#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1
-
-#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204)
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0
-#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1
-
-#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206)
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
-#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0
-#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1
-
-#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206)
-#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
-#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__out_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0
-#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1
-#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
-#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1
-#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0
-#define R_USB_IRQ_READ_DEV__epid_attn__pend 1
-#define R_USB_IRQ_READ_DEV__sof__BITNR 2
-#define R_USB_IRQ_READ_DEV__sof__WIDTH 1
-#define R_USB_IRQ_READ_DEV__sof__no_pend 0
-#define R_USB_IRQ_READ_DEV__sof__pend 1
-#define R_USB_IRQ_READ_DEV__port_status__BITNR 1
-#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1
-#define R_USB_IRQ_READ_DEV__port_status__no_pend 0
-#define R_USB_IRQ_READ_DEV__port_status__pend 1
-#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
-#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1
-#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0
-#define R_USB_IRQ_READ_DEV__ctl_status__pend 1
-
-#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c)
-#define R_USB_FM_NUMBER__value__BITNR 0
-#define R_USB_FM_NUMBER__value__WIDTH 32
-
-#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210)
-#define R_USB_FM_INTERVAL__fixed__BITNR 6
-#define R_USB_FM_INTERVAL__fixed__WIDTH 8
-#define R_USB_FM_INTERVAL__adj__BITNR 0
-#define R_USB_FM_INTERVAL__adj__WIDTH 6
-
-#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212)
-#define R_USB_FM_REMAINING__value__BITNR 0
-#define R_USB_FM_REMAINING__value__WIDTH 14
-
-#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214)
-#define R_USB_FM_PSTART__value__BITNR 0
-#define R_USB_FM_PSTART__value__WIDTH 14
-
-#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203)
-#define R_USB_RH_STATUS__babble2__BITNR 7
-#define R_USB_RH_STATUS__babble2__WIDTH 1
-#define R_USB_RH_STATUS__babble2__no 0
-#define R_USB_RH_STATUS__babble2__yes 1
-#define R_USB_RH_STATUS__babble1__BITNR 6
-#define R_USB_RH_STATUS__babble1__WIDTH 1
-#define R_USB_RH_STATUS__babble1__no 0
-#define R_USB_RH_STATUS__babble1__yes 1
-#define R_USB_RH_STATUS__bus1__BITNR 4
-#define R_USB_RH_STATUS__bus1__WIDTH 2
-#define R_USB_RH_STATUS__bus1__SE0 0
-#define R_USB_RH_STATUS__bus1__Diff0 1
-#define R_USB_RH_STATUS__bus1__Diff1 2
-#define R_USB_RH_STATUS__bus1__SE1 3
-#define R_USB_RH_STATUS__bus2__BITNR 2
-#define R_USB_RH_STATUS__bus2__WIDTH 2
-#define R_USB_RH_STATUS__bus2__SE0 0
-#define R_USB_RH_STATUS__bus2__Diff0 1
-#define R_USB_RH_STATUS__bus2__Diff1 2
-#define R_USB_RH_STATUS__bus2__SE1 3
-#define R_USB_RH_STATUS__nports__BITNR 0
-#define R_USB_RH_STATUS__nports__WIDTH 2
-
-#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218)
-#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9
-#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__speed__full 0
-#define R_USB_RH_PORT_STATUS_1__speed__low 1
-#define R_USB_RH_PORT_STATUS_1__power__BITNR 8
-#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4
-#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__reset__no 0
-#define R_USB_RH_PORT_STATUS_1__reset__yes 1
-#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
-#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0
-#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1
-#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
-#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__suspended__no 0
-#define R_USB_RH_PORT_STATUS_1__suspended__yes 1
-#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1
-#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__enabled__no 0
-#define R_USB_RH_PORT_STATUS_1__enabled__yes 1
-#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0
-#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1
-#define R_USB_RH_PORT_STATUS_1__connected__no 0
-#define R_USB_RH_PORT_STATUS_1__connected__yes 1
-
-#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a)
-#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9
-#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__speed__full 0
-#define R_USB_RH_PORT_STATUS_2__speed__low 1
-#define R_USB_RH_PORT_STATUS_2__power__BITNR 8
-#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4
-#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__reset__no 0
-#define R_USB_RH_PORT_STATUS_2__reset__yes 1
-#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
-#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0
-#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1
-#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
-#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__suspended__no 0
-#define R_USB_RH_PORT_STATUS_2__suspended__yes 1
-#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1
-#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__enabled__no 0
-#define R_USB_RH_PORT_STATUS_2__enabled__yes 1
-#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0
-#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1
-#define R_USB_RH_PORT_STATUS_2__connected__no 0
-#define R_USB_RH_PORT_STATUS_2__connected__yes 1
-
-#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208)
-#define R_USB_EPT_INDEX__value__BITNR 0
-#define R_USB_EPT_INDEX__value__WIDTH 5
-
-#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA__valid__BITNR 31
-#define R_USB_EPT_DATA__valid__WIDTH 1
-#define R_USB_EPT_DATA__valid__no 0
-#define R_USB_EPT_DATA__valid__yes 1
-#define R_USB_EPT_DATA__hold__BITNR 30
-#define R_USB_EPT_DATA__hold__WIDTH 1
-#define R_USB_EPT_DATA__hold__no 0
-#define R_USB_EPT_DATA__hold__yes 1
-#define R_USB_EPT_DATA__error_count_in__BITNR 28
-#define R_USB_EPT_DATA__error_count_in__WIDTH 2
-#define R_USB_EPT_DATA__t_in__BITNR 27
-#define R_USB_EPT_DATA__t_in__WIDTH 1
-#define R_USB_EPT_DATA__low_speed__BITNR 26
-#define R_USB_EPT_DATA__low_speed__WIDTH 1
-#define R_USB_EPT_DATA__low_speed__no 0
-#define R_USB_EPT_DATA__low_speed__yes 1
-#define R_USB_EPT_DATA__port__BITNR 24
-#define R_USB_EPT_DATA__port__WIDTH 2
-#define R_USB_EPT_DATA__port__any 0
-#define R_USB_EPT_DATA__port__p1 1
-#define R_USB_EPT_DATA__port__p2 2
-#define R_USB_EPT_DATA__port__undef 3
-#define R_USB_EPT_DATA__error_code__BITNR 22
-#define R_USB_EPT_DATA__error_code__WIDTH 2
-#define R_USB_EPT_DATA__error_code__no_error 0
-#define R_USB_EPT_DATA__error_code__stall 1
-#define R_USB_EPT_DATA__error_code__bus_error 2
-#define R_USB_EPT_DATA__error_code__buffer_error 3
-#define R_USB_EPT_DATA__t_out__BITNR 21
-#define R_USB_EPT_DATA__t_out__WIDTH 1
-#define R_USB_EPT_DATA__error_count_out__BITNR 19
-#define R_USB_EPT_DATA__error_count_out__WIDTH 2
-#define R_USB_EPT_DATA__max_len__BITNR 11
-#define R_USB_EPT_DATA__max_len__WIDTH 7
-#define R_USB_EPT_DATA__ep__BITNR 7
-#define R_USB_EPT_DATA__ep__WIDTH 4
-#define R_USB_EPT_DATA__dev__BITNR 0
-#define R_USB_EPT_DATA__dev__WIDTH 7
-
-#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA_ISO__valid__BITNR 31
-#define R_USB_EPT_DATA_ISO__valid__WIDTH 1
-#define R_USB_EPT_DATA_ISO__valid__no 0
-#define R_USB_EPT_DATA_ISO__valid__yes 1
-#define R_USB_EPT_DATA_ISO__port__BITNR 24
-#define R_USB_EPT_DATA_ISO__port__WIDTH 2
-#define R_USB_EPT_DATA_ISO__port__any 0
-#define R_USB_EPT_DATA_ISO__port__p1 1
-#define R_USB_EPT_DATA_ISO__port__p2 2
-#define R_USB_EPT_DATA_ISO__port__undef 3
-#define R_USB_EPT_DATA_ISO__error_code__BITNR 22
-#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2
-#define R_USB_EPT_DATA_ISO__error_code__no_error 0
-#define R_USB_EPT_DATA_ISO__error_code__stall 1
-#define R_USB_EPT_DATA_ISO__error_code__bus_error 2
-#define R_USB_EPT_DATA_ISO__error_code__TBD3 3
-#define R_USB_EPT_DATA_ISO__max_len__BITNR 11
-#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10
-#define R_USB_EPT_DATA_ISO__ep__BITNR 7
-#define R_USB_EPT_DATA_ISO__ep__WIDTH 4
-#define R_USB_EPT_DATA_ISO__dev__BITNR 0
-#define R_USB_EPT_DATA_ISO__dev__WIDTH 7
-
-#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c)
-#define R_USB_EPT_DATA_DEV__valid__BITNR 31
-#define R_USB_EPT_DATA_DEV__valid__WIDTH 1
-#define R_USB_EPT_DATA_DEV__valid__no 0
-#define R_USB_EPT_DATA_DEV__valid__yes 1
-#define R_USB_EPT_DATA_DEV__hold__BITNR 30
-#define R_USB_EPT_DATA_DEV__hold__WIDTH 1
-#define R_USB_EPT_DATA_DEV__hold__no 0
-#define R_USB_EPT_DATA_DEV__hold__yes 1
-#define R_USB_EPT_DATA_DEV__stall__BITNR 29
-#define R_USB_EPT_DATA_DEV__stall__WIDTH 1
-#define R_USB_EPT_DATA_DEV__stall__no 0
-#define R_USB_EPT_DATA_DEV__stall__yes 1
-#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
-#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1
-#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0
-#define R_USB_EPT_DATA_DEV__iso_resp__yes 1
-#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
-#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1
-#define R_USB_EPT_DATA_DEV__ctrl__no 0
-#define R_USB_EPT_DATA_DEV__ctrl__yes 1
-#define R_USB_EPT_DATA_DEV__iso__BITNR 26
-#define R_USB_EPT_DATA_DEV__iso__WIDTH 1
-#define R_USB_EPT_DATA_DEV__iso__no 0
-#define R_USB_EPT_DATA_DEV__iso__yes 1
-#define R_USB_EPT_DATA_DEV__port__BITNR 24
-#define R_USB_EPT_DATA_DEV__port__WIDTH 2
-#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
-#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1
-#define R_USB_EPT_DATA_DEV__t__BITNR 21
-#define R_USB_EPT_DATA_DEV__t__WIDTH 1
-#define R_USB_EPT_DATA_DEV__max_len__BITNR 11
-#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10
-#define R_USB_EPT_DATA_DEV__ep__BITNR 7
-#define R_USB_EPT_DATA_DEV__ep__WIDTH 4
-#define R_USB_EPT_DATA_DEV__dev__BITNR 0
-#define R_USB_EPT_DATA_DEV__dev__WIDTH 7
-
-#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220)
-#define R_USB_SNMP_TERROR__value__BITNR 0
-#define R_USB_SNMP_TERROR__value__WIDTH 32
-
-#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224)
-#define R_USB_EPID_ATTN__value__BITNR 0
-#define R_USB_EPID_ATTN__value__WIDTH 32
-
-#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a)
-#define R_USB_PORT1_DISABLE__disable__BITNR 0
-#define R_USB_PORT1_DISABLE__disable__WIDTH 1
-#define R_USB_PORT1_DISABLE__disable__yes 0
-#define R_USB_PORT1_DISABLE__disable__no 1
-
-#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052)
-#define R_USB_PORT2_DISABLE__disable__BITNR 0
-#define R_USB_PORT2_DISABLE__disable__WIDTH 1
-#define R_USB_PORT2_DISABLE__disable__yes 0
-#define R_USB_PORT2_DISABLE__disable__no 1
-
-/*
-!* MMU registers
-!*/
-
-#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240)
-#define R_MMU_CONFIG__mmu_enable__BITNR 31
-#define R_MMU_CONFIG__mmu_enable__WIDTH 1
-#define R_MMU_CONFIG__mmu_enable__enable 1
-#define R_MMU_CONFIG__mmu_enable__disable 0
-#define R_MMU_CONFIG__inv_excp__BITNR 18
-#define R_MMU_CONFIG__inv_excp__WIDTH 1
-#define R_MMU_CONFIG__inv_excp__enable 1
-#define R_MMU_CONFIG__inv_excp__disable 0
-#define R_MMU_CONFIG__acc_excp__BITNR 17
-#define R_MMU_CONFIG__acc_excp__WIDTH 1
-#define R_MMU_CONFIG__acc_excp__enable 1
-#define R_MMU_CONFIG__acc_excp__disable 0
-#define R_MMU_CONFIG__we_excp__BITNR 16
-#define R_MMU_CONFIG__we_excp__WIDTH 1
-#define R_MMU_CONFIG__we_excp__enable 1
-#define R_MMU_CONFIG__we_excp__disable 0
-#define R_MMU_CONFIG__seg_f__BITNR 15
-#define R_MMU_CONFIG__seg_f__WIDTH 1
-#define R_MMU_CONFIG__seg_f__seg 1
-#define R_MMU_CONFIG__seg_f__page 0
-#define R_MMU_CONFIG__seg_e__BITNR 14
-#define R_MMU_CONFIG__seg_e__WIDTH 1
-#define R_MMU_CONFIG__seg_e__seg 1
-#define R_MMU_CONFIG__seg_e__page 0
-#define R_MMU_CONFIG__seg_d__BITNR 13
-#define R_MMU_CONFIG__seg_d__WIDTH 1
-#define R_MMU_CONFIG__seg_d__seg 1
-#define R_MMU_CONFIG__seg_d__page 0
-#define R_MMU_CONFIG__seg_c__BITNR 12
-#define R_MMU_CONFIG__seg_c__WIDTH 1
-#define R_MMU_CONFIG__seg_c__seg 1
-#define R_MMU_CONFIG__seg_c__page 0
-#define R_MMU_CONFIG__seg_b__BITNR 11
-#define R_MMU_CONFIG__seg_b__WIDTH 1
-#define R_MMU_CONFIG__seg_b__seg 1
-#define R_MMU_CONFIG__seg_b__page 0
-#define R_MMU_CONFIG__seg_a__BITNR 10
-#define R_MMU_CONFIG__seg_a__WIDTH 1
-#define R_MMU_CONFIG__seg_a__seg 1
-#define R_MMU_CONFIG__seg_a__page 0
-#define R_MMU_CONFIG__seg_9__BITNR 9
-#define R_MMU_CONFIG__seg_9__WIDTH 1
-#define R_MMU_CONFIG__seg_9__seg 1
-#define R_MMU_CONFIG__seg_9__page 0
-#define R_MMU_CONFIG__seg_8__BITNR 8
-#define R_MMU_CONFIG__seg_8__WIDTH 1
-#define R_MMU_CONFIG__seg_8__seg 1
-#define R_MMU_CONFIG__seg_8__page 0
-#define R_MMU_CONFIG__seg_7__BITNR 7
-#define R_MMU_CONFIG__seg_7__WIDTH 1
-#define R_MMU_CONFIG__seg_7__seg 1
-#define R_MMU_CONFIG__seg_7__page 0
-#define R_MMU_CONFIG__seg_6__BITNR 6
-#define R_MMU_CONFIG__seg_6__WIDTH 1
-#define R_MMU_CONFIG__seg_6__seg 1
-#define R_MMU_CONFIG__seg_6__page 0
-#define R_MMU_CONFIG__seg_5__BITNR 5
-#define R_MMU_CONFIG__seg_5__WIDTH 1
-#define R_MMU_CONFIG__seg_5__seg 1
-#define R_MMU_CONFIG__seg_5__page 0
-#define R_MMU_CONFIG__seg_4__BITNR 4
-#define R_MMU_CONFIG__seg_4__WIDTH 1
-#define R_MMU_CONFIG__seg_4__seg 1
-#define R_MMU_CONFIG__seg_4__page 0
-#define R_MMU_CONFIG__seg_3__BITNR 3
-#define R_MMU_CONFIG__seg_3__WIDTH 1
-#define R_MMU_CONFIG__seg_3__seg 1
-#define R_MMU_CONFIG__seg_3__page 0
-#define R_MMU_CONFIG__seg_2__BITNR 2
-#define R_MMU_CONFIG__seg_2__WIDTH 1
-#define R_MMU_CONFIG__seg_2__seg 1
-#define R_MMU_CONFIG__seg_2__page 0
-#define R_MMU_CONFIG__seg_1__BITNR 1
-#define R_MMU_CONFIG__seg_1__WIDTH 1
-#define R_MMU_CONFIG__seg_1__seg 1
-#define R_MMU_CONFIG__seg_1__page 0
-#define R_MMU_CONFIG__seg_0__BITNR 0
-#define R_MMU_CONFIG__seg_0__WIDTH 1
-#define R_MMU_CONFIG__seg_0__seg 1
-#define R_MMU_CONFIG__seg_0__page 0
-
-#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240)
-#define R_MMU_KSEG__seg_f__BITNR 15
-#define R_MMU_KSEG__seg_f__WIDTH 1
-#define R_MMU_KSEG__seg_f__seg 1
-#define R_MMU_KSEG__seg_f__page 0
-#define R_MMU_KSEG__seg_e__BITNR 14
-#define R_MMU_KSEG__seg_e__WIDTH 1
-#define R_MMU_KSEG__seg_e__seg 1
-#define R_MMU_KSEG__seg_e__page 0
-#define R_MMU_KSEG__seg_d__BITNR 13
-#define R_MMU_KSEG__seg_d__WIDTH 1
-#define R_MMU_KSEG__seg_d__seg 1
-#define R_MMU_KSEG__seg_d__page 0
-#define R_MMU_KSEG__seg_c__BITNR 12
-#define R_MMU_KSEG__seg_c__WIDTH 1
-#define R_MMU_KSEG__seg_c__seg 1
-#define R_MMU_KSEG__seg_c__page 0
-#define R_MMU_KSEG__seg_b__BITNR 11
-#define R_MMU_KSEG__seg_b__WIDTH 1
-#define R_MMU_KSEG__seg_b__seg 1
-#define R_MMU_KSEG__seg_b__page 0
-#define R_MMU_KSEG__seg_a__BITNR 10
-#define R_MMU_KSEG__seg_a__WIDTH 1
-#define R_MMU_KSEG__seg_a__seg 1
-#define R_MMU_KSEG__seg_a__page 0
-#define R_MMU_KSEG__seg_9__BITNR 9
-#define R_MMU_KSEG__seg_9__WIDTH 1
-#define R_MMU_KSEG__seg_9__seg 1
-#define R_MMU_KSEG__seg_9__page 0
-#define R_MMU_KSEG__seg_8__BITNR 8
-#define R_MMU_KSEG__seg_8__WIDTH 1
-#define R_MMU_KSEG__seg_8__seg 1
-#define R_MMU_KSEG__seg_8__page 0
-#define R_MMU_KSEG__seg_7__BITNR 7
-#define R_MMU_KSEG__seg_7__WIDTH 1
-#define R_MMU_KSEG__seg_7__seg 1
-#define R_MMU_KSEG__seg_7__page 0
-#define R_MMU_KSEG__seg_6__BITNR 6
-#define R_MMU_KSEG__seg_6__WIDTH 1
-#define R_MMU_KSEG__seg_6__seg 1
-#define R_MMU_KSEG__seg_6__page 0
-#define R_MMU_KSEG__seg_5__BITNR 5
-#define R_MMU_KSEG__seg_5__WIDTH 1
-#define R_MMU_KSEG__seg_5__seg 1
-#define R_MMU_KSEG__seg_5__page 0
-#define R_MMU_KSEG__seg_4__BITNR 4
-#define R_MMU_KSEG__seg_4__WIDTH 1
-#define R_MMU_KSEG__seg_4__seg 1
-#define R_MMU_KSEG__seg_4__page 0
-#define R_MMU_KSEG__seg_3__BITNR 3
-#define R_MMU_KSEG__seg_3__WIDTH 1
-#define R_MMU_KSEG__seg_3__seg 1
-#define R_MMU_KSEG__seg_3__page 0
-#define R_MMU_KSEG__seg_2__BITNR 2
-#define R_MMU_KSEG__seg_2__WIDTH 1
-#define R_MMU_KSEG__seg_2__seg 1
-#define R_MMU_KSEG__seg_2__page 0
-#define R_MMU_KSEG__seg_1__BITNR 1
-#define R_MMU_KSEG__seg_1__WIDTH 1
-#define R_MMU_KSEG__seg_1__seg 1
-#define R_MMU_KSEG__seg_1__page 0
-#define R_MMU_KSEG__seg_0__BITNR 0
-#define R_MMU_KSEG__seg_0__WIDTH 1
-#define R_MMU_KSEG__seg_0__seg 1
-#define R_MMU_KSEG__seg_0__page 0
-
-#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242)
-#define R_MMU_CTRL__inv_excp__BITNR 2
-#define R_MMU_CTRL__inv_excp__WIDTH 1
-#define R_MMU_CTRL__inv_excp__enable 1
-#define R_MMU_CTRL__inv_excp__disable 0
-#define R_MMU_CTRL__acc_excp__BITNR 1
-#define R_MMU_CTRL__acc_excp__WIDTH 1
-#define R_MMU_CTRL__acc_excp__enable 1
-#define R_MMU_CTRL__acc_excp__disable 0
-#define R_MMU_CTRL__we_excp__BITNR 0
-#define R_MMU_CTRL__we_excp__WIDTH 1
-#define R_MMU_CTRL__we_excp__enable 1
-#define R_MMU_CTRL__we_excp__disable 0
-
-#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243)
-#define R_MMU_ENABLE__mmu_enable__BITNR 7
-#define R_MMU_ENABLE__mmu_enable__WIDTH 1
-#define R_MMU_ENABLE__mmu_enable__enable 1
-#define R_MMU_ENABLE__mmu_enable__disable 0
-
-#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244)
-#define R_MMU_KBASE_LO__base_7__BITNR 28
-#define R_MMU_KBASE_LO__base_7__WIDTH 4
-#define R_MMU_KBASE_LO__base_6__BITNR 24
-#define R_MMU_KBASE_LO__base_6__WIDTH 4
-#define R_MMU_KBASE_LO__base_5__BITNR 20
-#define R_MMU_KBASE_LO__base_5__WIDTH 4
-#define R_MMU_KBASE_LO__base_4__BITNR 16
-#define R_MMU_KBASE_LO__base_4__WIDTH 4
-#define R_MMU_KBASE_LO__base_3__BITNR 12
-#define R_MMU_KBASE_LO__base_3__WIDTH 4
-#define R_MMU_KBASE_LO__base_2__BITNR 8
-#define R_MMU_KBASE_LO__base_2__WIDTH 4
-#define R_MMU_KBASE_LO__base_1__BITNR 4
-#define R_MMU_KBASE_LO__base_1__WIDTH 4
-#define R_MMU_KBASE_LO__base_0__BITNR 0
-#define R_MMU_KBASE_LO__base_0__WIDTH 4
-
-#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248)
-#define R_MMU_KBASE_HI__base_f__BITNR 28
-#define R_MMU_KBASE_HI__base_f__WIDTH 4
-#define R_MMU_KBASE_HI__base_e__BITNR 24
-#define R_MMU_KBASE_HI__base_e__WIDTH 4
-#define R_MMU_KBASE_HI__base_d__BITNR 20
-#define R_MMU_KBASE_HI__base_d__WIDTH 4
-#define R_MMU_KBASE_HI__base_c__BITNR 16
-#define R_MMU_KBASE_HI__base_c__WIDTH 4
-#define R_MMU_KBASE_HI__base_b__BITNR 12
-#define R_MMU_KBASE_HI__base_b__WIDTH 4
-#define R_MMU_KBASE_HI__base_a__BITNR 8
-#define R_MMU_KBASE_HI__base_a__WIDTH 4
-#define R_MMU_KBASE_HI__base_9__BITNR 4
-#define R_MMU_KBASE_HI__base_9__WIDTH 4
-#define R_MMU_KBASE_HI__base_8__BITNR 0
-#define R_MMU_KBASE_HI__base_8__WIDTH 4
-
-#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c)
-#define R_MMU_CONTEXT__page_id__BITNR 0
-#define R_MMU_CONTEXT__page_id__WIDTH 6
-
-#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250)
-#define R_MMU_CAUSE__vpn__BITNR 13
-#define R_MMU_CAUSE__vpn__WIDTH 19
-#define R_MMU_CAUSE__miss_excp__BITNR 12
-#define R_MMU_CAUSE__miss_excp__WIDTH 1
-#define R_MMU_CAUSE__miss_excp__yes 1
-#define R_MMU_CAUSE__miss_excp__no 0
-#define R_MMU_CAUSE__inv_excp__BITNR 11
-#define R_MMU_CAUSE__inv_excp__WIDTH 1
-#define R_MMU_CAUSE__inv_excp__yes 1
-#define R_MMU_CAUSE__inv_excp__no 0
-#define R_MMU_CAUSE__acc_excp__BITNR 10
-#define R_MMU_CAUSE__acc_excp__WIDTH 1
-#define R_MMU_CAUSE__acc_excp__yes 1
-#define R_MMU_CAUSE__acc_excp__no 0
-#define R_MMU_CAUSE__we_excp__BITNR 9
-#define R_MMU_CAUSE__we_excp__WIDTH 1
-#define R_MMU_CAUSE__we_excp__yes 1
-#define R_MMU_CAUSE__we_excp__no 0
-#define R_MMU_CAUSE__wr_rd__BITNR 8
-#define R_MMU_CAUSE__wr_rd__WIDTH 1
-#define R_MMU_CAUSE__wr_rd__write 1
-#define R_MMU_CAUSE__wr_rd__read 0
-#define R_MMU_CAUSE__page_id__BITNR 0
-#define R_MMU_CAUSE__page_id__WIDTH 6
-
-#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254)
-#define R_TLB_SELECT__index__BITNR 0
-#define R_TLB_SELECT__index__WIDTH 6
-
-#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258)
-#define R_TLB_LO__pfn__BITNR 13
-#define R_TLB_LO__pfn__WIDTH 19
-#define R_TLB_LO__global__BITNR 3
-#define R_TLB_LO__global__WIDTH 1
-#define R_TLB_LO__global__yes 1
-#define R_TLB_LO__global__no 0
-#define R_TLB_LO__valid__BITNR 2
-#define R_TLB_LO__valid__WIDTH 1
-#define R_TLB_LO__valid__yes 1
-#define R_TLB_LO__valid__no 0
-#define R_TLB_LO__kernel__BITNR 1
-#define R_TLB_LO__kernel__WIDTH 1
-#define R_TLB_LO__kernel__yes 1
-#define R_TLB_LO__kernel__no 0
-#define R_TLB_LO__we__BITNR 0
-#define R_TLB_LO__we__WIDTH 1
-#define R_TLB_LO__we__yes 1
-#define R_TLB_LO__we__no 0
-
-#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c)
-#define R_TLB_HI__vpn__BITNR 13
-#define R_TLB_HI__vpn__WIDTH 19
-#define R_TLB_HI__page_id__BITNR 0
-#define R_TLB_HI__page_id__WIDTH 6
-
-/*
-!* Syncrounous serial port registers
-!*/
-
-#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c)
-#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32
-
-#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c)
-#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16
-
-#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c)
-#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0
-#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8
-
-#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068)
-#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15
-#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__rec_status__running 0
-#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14
-#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1
-#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0
-#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13
-#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0
-#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1
-#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12
-#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__pin_1__low 0
-#define R_SYNC_SERIAL1_STATUS__pin_1__high 1
-#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11
-#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__pin_0__low 0
-#define R_SYNC_SERIAL1_STATUS__pin_0__high 1
-#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10
-#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__underflow__no 0
-#define R_SYNC_SERIAL1_STATUS__underflow__yes 1
-#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9
-#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__overrun__no 0
-#define R_SYNC_SERIAL1_STATUS__overrun__yes 1
-#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8
-#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1
-#define R_SYNC_SERIAL1_STATUS__data_avail__no 0
-#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1
-#define R_SYNC_SERIAL1_STATUS__data__BITNR 0
-#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8
-
-#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c)
-#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32
-
-#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c)
-#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16
-
-#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c)
-#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0
-#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8
-
-#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
-#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28
-#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13
-#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14
-#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15
-#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27
-#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1
-#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0
-#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24
-#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3
-#define R_SYNC_SERIAL1_CTRL__mode__master_output 0
-#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1
-#define R_SYNC_SERIAL1_CTRL__mode__master_input 2
-#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3
-#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4
-#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5
-#define R_SYNC_SERIAL1_CTRL__error__BITNR 23
-#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__error__normal 0
-#define R_SYNC_SERIAL1_CTRL__error__ignore 1
-#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22
-#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0
-#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1
-#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21
-#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0
-#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2
-#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3
-#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18
-#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__f_sync__on 0
-#define R_SYNC_SERIAL1_CTRL__f_sync__off 1
-#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17
-#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0
-#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1
-#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16
-#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0
-#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1
-#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15
-#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0
-#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1
-#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14
-#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0
-#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1
-#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11
-#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3
-#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0
-#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1
-#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2
-#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3
-#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4
-#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10
-#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0
-#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1
-#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9
-#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0
-#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0
-#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0
-#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0
-#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1
-#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4
-#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0
-#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1
-#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3
-#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2
-#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0
-#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0
-#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__high 1
-#define R_SYNC_SERIAL1_CTRL__def_out0__low 0
-
-#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c)
-#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32
-
-#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c)
-#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16
-
-#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c)
-#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0
-#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8
-
-#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078)
-#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15
-#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__rec_status__running 0
-#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14
-#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1
-#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0
-#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13
-#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0
-#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1
-#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12
-#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__pin_1__low 0
-#define R_SYNC_SERIAL3_STATUS__pin_1__high 1
-#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11
-#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__pin_0__low 0
-#define R_SYNC_SERIAL3_STATUS__pin_0__high 1
-#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10
-#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__underflow__no 0
-#define R_SYNC_SERIAL3_STATUS__underflow__yes 1
-#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9
-#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__overrun__no 0
-#define R_SYNC_SERIAL3_STATUS__overrun__yes 1
-#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8
-#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1
-#define R_SYNC_SERIAL3_STATUS__data_avail__no 0
-#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1
-#define R_SYNC_SERIAL3_STATUS__data__BITNR 0
-#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8
-
-#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c)
-#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32
-
-#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c)
-#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16
-
-#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c)
-#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0
-#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8
-
-#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
-#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28
-#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13
-#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14
-#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15
-#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27
-#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1
-#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0
-#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24
-#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3
-#define R_SYNC_SERIAL3_CTRL__mode__master_output 0
-#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1
-#define R_SYNC_SERIAL3_CTRL__mode__master_input 2
-#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3
-#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4
-#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5
-#define R_SYNC_SERIAL3_CTRL__error__BITNR 23
-#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__error__normal 0
-#define R_SYNC_SERIAL3_CTRL__error__ignore 1
-#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22
-#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0
-#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1
-#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21
-#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0
-#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2
-#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3
-#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18
-#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__f_sync__on 0
-#define R_SYNC_SERIAL3_CTRL__f_sync__off 1
-#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17
-#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0
-#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1
-#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16
-#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0
-#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1
-#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15
-#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0
-#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1
-#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14
-#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0
-#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1
-#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11
-#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3
-#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0
-#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1
-#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2
-#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3
-#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4
-#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10
-#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0
-#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1
-#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9
-#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0
-#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0
-#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0
-#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0
-#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1
-#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4
-#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0
-#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1
-#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3
-#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2
-#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0
-#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0
-#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__high 1
-#define R_SYNC_SERIAL3_CTRL__def_out0__low 0
-
diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h
deleted file mode 100644
index 2644bcbe4490..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*!**************************************************************************
-*!
-*! MACROS:
-*! IO_MASK(reg,field)
-*! IO_STATE(reg,field,state)
-*! IO_EXTRACT(reg,field,val)
-*! IO_STATE_VALUE(reg,field,state)
-*! IO_BITNR(reg,field)
-*! IO_WIDTH(reg,field)
-*! IO_FIELD(reg,field,val)
-*! IO_RD(reg)
-*! All moderegister addresses and fields of these.
-*!
-*!**************************************************************************/
-
-#ifndef __sv_addr_ag_h__
-#define __sv_addr_ag_h__
-
-
-#define __test_sv_addr__ 0
-
-/*------------------------------------------------------------
-!* General macros to manipulate moderegisters.
-!*-----------------------------------------------------------*/
-
-/* IO_MASK returns a mask for a specified bitfield in a register.
- Note that this macro doesn't work when field width is 32 bits. */
-#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_)
-#define IO_MASK_(reg_, field_) \
- ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR )
-
-/* IO_STATE returns a constant corresponding to a one of the symbolic
- states that the bitfield can have. (Shifted to correct position) */
-#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state)
-#define IO_STATE_(reg_, field_, _state) \
- ( reg_##_##field_##_state << reg_##_##field_##_BITNR )
-
-/* IO_EXTRACT returns the masked and shifted value corresponding to the
- bitfield can have. */
-#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val)
-#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \
- - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR )
-
-/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic
- states that the bitfield can have. (Not shifted) */
-#define IO_STATE_VALUE(reg, field, state) \
- IO_STATE_VALUE_ (reg##_, field##_, _##state)
-#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state )
-
-/* IO_FIELD shifts the val parameter to be aligned with the bitfield
- specified. */
-#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val)
-#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR)
-
-/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is
- LSB and the returned bitnumber is LSB of the field. */
-#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_)
-#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR)
-
-/* IO_WIDTH returns the width, in bits, of a bitfield. */
-#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_)
-#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH)
-
-/*--- Obsolete. Kept for backward compatibility. ---*/
-/* Reads (or writes) a byte/uword/udword from the specified mode
- register. */
-#define IO_RD(reg) (*(volatile u32*)(reg))
-#define IO_RD_B(reg) (*(volatile u8*)(reg))
-#define IO_RD_W(reg) (*(volatile u16*)(reg))
-#define IO_RD_D(reg) (*(volatile u32*)(reg))
-
-/*------------------------------------------------------------
-!* Start addresses of the different memory areas.
-!*-----------------------------------------------------------*/
-
-#define MEM_CSE0_START (0x00000000)
-#define MEM_CSE0_SIZE (0x04000000)
-#define MEM_CSE1_START (0x04000000)
-#define MEM_CSE1_SIZE (0x04000000)
-#define MEM_CSR0_START (0x08000000)
-#define MEM_CSR1_START (0x0c000000)
-#define MEM_CSP0_START (0x10000000)
-#define MEM_CSP1_START (0x14000000)
-#define MEM_CSP2_START (0x18000000)
-#define MEM_CSP3_START (0x1c000000)
-#define MEM_CSP4_START (0x20000000)
-#define MEM_CSP5_START (0x24000000)
-#define MEM_CSP6_START (0x28000000)
-#define MEM_CSP7_START (0x2c000000)
-#define MEM_DRAM_START (0x40000000)
-
-#define MEM_NON_CACHEABLE (0x80000000)
-
-/*------------------------------------------------------------
-!* Type casts used in mode register macros, making pointer
-!* dereferencing possible. Empty in assembler.
-!*-----------------------------------------------------------*/
-
-#ifndef __ASSEMBLER__
-# define IO_TYPECAST_UDWORD (volatile u32*)
-# define IO_TYPECAST_RO_UDWORD (const volatile u32*)
-# define IO_TYPECAST_UWORD (volatile u16*)
-# define IO_TYPECAST_RO_UWORD (const volatile u16*)
-# define IO_TYPECAST_BYTE (volatile u8*)
-# define IO_TYPECAST_RO_BYTE (const volatile u8*)
-#else
-# define IO_TYPECAST_UDWORD
-# define IO_TYPECAST_RO_UDWORD
-# define IO_TYPECAST_UWORD
-# define IO_TYPECAST_RO_UWORD
-# define IO_TYPECAST_BYTE
-# define IO_TYPECAST_RO_BYTE
-#endif
-
-/*------------------------------------------------------------*/
-
-#include <arch/sv_addr.agh>
-
-#if __test_sv_addr__
-/* IO_MASK( R_BUS_CONFIG , CE ) */
-IO_MASK( R_WAITSTATES , SRAM_WS )
-IO_MASK( R_TEST , W32 )
-
-IO_STATE( R_BUS_CONFIG, CE, DISABLE )
-IO_STATE( R_BUS_CONFIG, CE, ENABLE )
-
-IO_STATE( R_DRAM_TIMING, REF, IVAL2 )
-
-IO_MASK( R_DRAM_TIMING, REF )
-
-IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT )
-
-IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S )
- == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED )
-#endif
-
-
-#endif /* ifndef __sv_addr_ag_h__ */
-
diff --git a/arch/cris/include/uapi/arch-v10/arch/svinto.h b/arch/cris/include/uapi/arch-v10/arch/svinto.h
deleted file mode 100644
index 793a4275d26a..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/svinto.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_CRIS_SVINTO_H
-#define _ASM_CRIS_SVINTO_H
-
-#include <arch/sv_addr_ag.h>
-
-extern unsigned int genconfig_shadow; /* defined and set in head.S */
-
-/* dma stuff */
-
-enum { /* Available in: */
- d_eol = (1 << 0), /* flags */
- d_eop = (1 << 1), /* flags & status */
- d_wait = (1 << 2), /* flags */
- d_int = (1 << 3), /* flags */
- d_txerr = (1 << 4), /* flags */
- d_stop = (1 << 4), /* status */
- d_ecp = (1 << 4), /* flags & status */
- d_pri = (1 << 5), /* flags & status */
- d_alignerr = (1 << 6), /* status */
- d_crcerr = (1 << 7) /* status */
-};
-
-/* Do remember that DMA does not go through the MMU and needs
- * a real physical address, not an address virtually mapped or
- * paged. Therefore the buf/next ptrs below are unsigned long instead
- * of void * to give a warning if you try to put a pointer directly
- * to them instead of going through virt_to_phys/phys_to_virt.
- */
-
-typedef struct etrax_dma_descr {
- unsigned short sw_len; /* 0-1 */
- unsigned short ctrl; /* 2-3 */
- unsigned long next; /* 4-7 */
- unsigned long buf; /* 8-11 */
- unsigned short hw_len; /* 12-13 */
- unsigned char status; /* 14 */
- unsigned char fifo_len; /* 15 */
-} etrax_dma_descr;
-
-
-/* Use this for constant numbers only */
-#define RESET_DMA_NUM( n ) \
- *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset )
-
-/* Use this for constant numbers or symbols,
- * having two macros makes it possible to use constant expressions.
- */
-#define RESET_DMA( n ) RESET_DMA_NUM( n )
-
-
-/* Use this for constant numbers only */
-#define WAIT_DMA_NUM( n ) \
- while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \
- IO_STATE( R_DMA_CH0_CMD, cmd, hold ) )
-
-/* Use this for constant numbers or symbols
- * having two macros makes it possible to use constant expressions.
- */
-#define WAIT_DMA( n ) WAIT_DMA_NUM( n )
-
-extern void prepare_rx_descriptor(struct etrax_dma_descr *desc);
-extern void flush_etrax_cache(void);
-
-#endif
diff --git a/arch/cris/include/uapi/arch-v10/arch/user.h b/arch/cris/include/uapi/arch-v10/arch/user.h
deleted file mode 100644
index 5b9288527b98..000000000000
--- a/arch/cris/include/uapi/arch-v10/arch/user.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASM_CRIS_ARCH_USER_H
-#define __ASM_CRIS_ARCH_USER_H
-
-/* User mode registers, used for core dumps. In order to keep ELF_NGREG
- sensible we let all registers be 32 bits. The csr registers are included
- for future use. */
-struct user_regs_struct {
- unsigned long r0; /* General registers. */
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- unsigned long r13;
- unsigned long sp; /* Stack pointer. */
- unsigned long pc; /* Program counter. */
- unsigned long p0; /* Constant zero (only 8 bits). */
- unsigned long vr; /* Version register (only 8 bits). */
- unsigned long p2; /* Reserved. */
- unsigned long p3; /* Reserved. */
- unsigned long p4; /* Constant zero (only 16 bits). */
- unsigned long ccr; /* Condition code register (only 16 bits). */
- unsigned long p6; /* Reserved. */
- unsigned long mof; /* Multiply overflow register. */
- unsigned long p8; /* Constant zero. */
- unsigned long ibr; /* Not accessible. */
- unsigned long irp; /* Not accessible. */
- unsigned long srp; /* Subroutine return pointer. */
- unsigned long bar; /* Not accessible. */
- unsigned long dccr; /* Dword condition code register. */
- unsigned long brp; /* Not accessible. */
- unsigned long usp; /* User-mode stack pointer. Same as sp when
- in user mode. */
- unsigned long csrinstr; /* Internal status registers. */
- unsigned long csraddr;
- unsigned long csrdata;
-};
-
-#endif
diff --git a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h b/arch/cris/include/uapi/arch-v32/arch/cryptocop.h
deleted file mode 100644
index 1072d5bf7d4f..000000000000
--- a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * The device /dev/cryptocop is accessible using this driver using
- * CRYPTOCOP_MAJOR (254) and minor number 0.
- */
-
-#ifndef _UAPICRYPTOCOP_H
-#define _UAPICRYPTOCOP_H
-
-#include <linux/uio.h>
-
-
-#define CRYPTOCOP_SESSION_ID_NONE (0)
-
-typedef unsigned long long int cryptocop_session_id;
-
-/* cryptocop ioctls */
-#define ETRAXCRYPTOCOP_IOCTYPE (250)
-
-#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op)
-#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op)
-#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op)
-#define CRYPTOCOP_IO_MAXNR (3)
-
-typedef enum {
- cryptocop_cipher_des = 0,
- cryptocop_cipher_3des = 1,
- cryptocop_cipher_aes = 2,
- cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */
- cryptocop_cipher_none
-} cryptocop_cipher_type;
-
-typedef enum {
- cryptocop_digest_sha1 = 0,
- cryptocop_digest_md5 = 1,
- cryptocop_digest_none
-} cryptocop_digest_type;
-
-typedef enum {
- cryptocop_csum_le = 0,
- cryptocop_csum_be = 1,
- cryptocop_csum_none
-} cryptocop_csum_type;
-
-typedef enum {
- cryptocop_cipher_mode_ecb = 0,
- cryptocop_cipher_mode_cbc,
- cryptocop_cipher_mode_none
-} cryptocop_cipher_mode;
-
-typedef enum {
- cryptocop_3des_eee = 0,
- cryptocop_3des_eed = 1,
- cryptocop_3des_ede = 2,
- cryptocop_3des_edd = 3,
- cryptocop_3des_dee = 4,
- cryptocop_3des_ded = 5,
- cryptocop_3des_dde = 6,
- cryptocop_3des_ddd = 7
-} cryptocop_3des_mode;
-
-/* Usermode accessible (ioctl) operations. */
-struct strcop_session_op{
- cryptocop_session_id ses_id;
-
- cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */
-
- cryptocop_cipher_mode cmode; /* ECB, CBC, none */
- cryptocop_3des_mode des3_mode;
-
- cryptocop_digest_type digest; /* MD5, SHA1, none */
-
- cryptocop_csum_type csum; /* BE, LE, none */
-
- unsigned char *key;
- size_t keylen;
-};
-
-#define CRYPTOCOP_CSUM_LENGTH (2)
-#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */
-#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */
-#define CRYPTOCOP_MAX_KEY_LENGTH (32)
-
-struct strcop_crypto_op{
- cryptocop_session_id ses_id;
-
- /* Indata. */
- unsigned char *indata;
- size_t inlen; /* Total indata length. */
-
- /* Cipher configuration. */
- unsigned char do_cipher:1;
- unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */
- unsigned char cipher_explicit:1;
- size_t cipher_start;
- size_t cipher_len;
- /* cipher_iv is used if do_cipher and cipher_explicit and the cipher
- mode is CBC. The length is controlled by the type of cipher,
- e.g. DES/3DES 8 octets and AES 16 octets. */
- unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH];
- /* Outdata. */
- unsigned char *cipher_outdata;
- size_t cipher_outlen;
-
- /* digest configuration. */
- unsigned char do_digest:1;
- size_t digest_start;
- size_t digest_len;
- /* Outdata. The actual length is determined by the type of the digest. */
- unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH];
-
- /* Checksum configuration. */
- unsigned char do_csum:1;
- size_t csum_start;
- size_t csum_len;
- /* Outdata. */
- unsigned char csum[CRYPTOCOP_CSUM_LENGTH];
-};
-
-
-
-
-#endif /* _UAPICRYPTOCOP_H */
diff --git a/arch/cris/include/uapi/arch-v32/arch/user.h b/arch/cris/include/uapi/arch-v32/arch/user.h
deleted file mode 100644
index 3576b540ba78..000000000000
--- a/arch/cris/include/uapi/arch-v32/arch/user.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_CRIS_ARCH_USER_H
-#define _ASM_CRIS_ARCH_USER_H
-
-/* User-mode register used for core dumps. */
-
-struct user_regs_struct {
- unsigned long r0; /* General registers. */
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- unsigned long r13;
- unsigned long sp; /* R14, Stack pointer. */
- unsigned long acr; /* R15, Address calculation register. */
- unsigned long bz; /* P0, Constant zero (8-bits). */
- unsigned long vr; /* P1, Version register (8-bits). */
- unsigned long pid; /* P2, Process ID (8-bits). */
- unsigned long srs; /* P3, Support register select (8-bits). */
- unsigned long wz; /* P4, Constant zero (16-bits). */
- unsigned long exs; /* P5, Exception status. */
- unsigned long eda; /* P6, Exception data address. */
- unsigned long mof; /* P7, Multiply overflow regiter. */
- unsigned long dz; /* P8, Constant zero (32-bits). */
- unsigned long ebp; /* P9, Exception base pointer. */
- unsigned long erp; /* P10, Exception return pointer. */
- unsigned long srp; /* P11, Subroutine return pointer. */
- unsigned long nrp; /* P12, NMI return pointer. */
- unsigned long ccs; /* P13, Condition code stack. */
- unsigned long usp; /* P14, User mode stack pointer. */
- unsigned long spc; /* P15, Single step PC. */
-};
-
-#endif /* _ASM_CRIS_ARCH_USER_H */
diff --git a/arch/cris/include/uapi/asm/Kbuild b/arch/cris/include/uapi/asm/Kbuild
deleted file mode 100644
index 3470c6e9c7b9..000000000000
--- a/arch/cris/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,22 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += auxvec.h
-generic-y += bitsperlong.h
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += fcntl.h
-generic-y += ioctl.h
-generic-y += ipcbuf.h
-generic-y += kvm_para.h
-generic-y += mman.h
-generic-y += msgbuf.h
-generic-y += poll.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += shmbuf.h
-generic-y += siginfo.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += types.h
diff --git a/arch/cris/include/uapi/asm/byteorder.h b/arch/cris/include/uapi/asm/byteorder.h
deleted file mode 100644
index 6e19891e06ee..000000000000
--- a/arch/cris/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_BYTEORDER_H
-#define _CRIS_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif
-
-
diff --git a/arch/cris/include/uapi/asm/elf.h b/arch/cris/include/uapi/asm/elf.h
deleted file mode 100644
index ea4cbdafe885..000000000000
--- a/arch/cris/include/uapi/asm/elf.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASMCRIS_ELF_H
-#define __ASMCRIS_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#ifdef __arch_v32
-#include <asm/elf_v32.h>
-#else
-#include <asm/elf_v10.h>
-#endif
-
-#define R_CRIS_NONE 0
-#define R_CRIS_8 1
-#define R_CRIS_16 2
-#define R_CRIS_32 3
-#define R_CRIS_8_PCREL 4
-#define R_CRIS_16_PCREL 5
-#define R_CRIS_32_PCREL 6
-#define R_CRIS_GNU_VTINHERIT 7
-#define R_CRIS_GNU_VTENTRY 8
-#define R_CRIS_COPY 9
-#define R_CRIS_GLOB_DAT 10
-#define R_CRIS_JUMP_SLOT 11
-#define R_CRIS_RELATIVE 12
-#define R_CRIS_16_GOT 13
-#define R_CRIS_32_GOT 14
-#define R_CRIS_16_GOTPLT 15
-#define R_CRIS_32_GOTPLT 16
-#define R_CRIS_32_GOTREL 17
-#define R_CRIS_32_PLT_GOTREL 18
-#define R_CRIS_32_PLT_PCREL 19
-
-typedef unsigned long elf_greg_t;
-
-/* Note that NGREG is defined to ELF_NGREG in include/linux/elfcore.h, and is
- thus exposed to user-space. */
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* A placeholder; CRIS does not have any fp regs. */
-typedef unsigned long elf_fpregset_t;
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_CRIS
-
-/* The master for these definitions is {binutils}/include/elf/cris.h: */
-/* User symbols in this file have a leading underscore. */
-#define EF_CRIS_UNDERSCORE 0x00000001
-
-/* This is a mask for different incompatible machine variants. */
-#define EF_CRIS_VARIANT_MASK 0x0000000e
-
-/* Variant 0; may contain v0..10 object. */
-#define EF_CRIS_VARIANT_ANY_V0_V10 0x00000000
-
-/* Variant 1; contains v32 object. */
-#define EF_CRIS_VARIANT_V32 0x00000002
-
-/* Variant 2; contains object compatible with v32 and v10. */
-#define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004
-/* End of excerpt from {binutils}/include/elf/cris.h. */
-
-#define ELF_EXEC_PAGESIZE 8192
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this CPU supports. This could be done in user space,
- but it's not easy, and we've already done it here. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo.
-*/
-
-#define ELF_PLATFORM (NULL)
-
-#endif
diff --git a/arch/cris/include/uapi/asm/elf_v10.h b/arch/cris/include/uapi/asm/elf_v10.h
deleted file mode 100644
index b1515f2684da..000000000000
--- a/arch/cris/include/uapi/asm/elf_v10.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASMCRIS_ARCH_ELF_H
-#define __ASMCRIS_ARCH_ELF_H
-
-#define ELF_MACH EF_CRIS_VARIANT_ANY_V0_V10
-
-/* Matches struct user_regs_struct */
-#define ELF_NGREG 35
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
- ((x)->e_machine == EM_CRIS \
- && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_ANY_V0_V10 \
- || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-
-/* SVR4/i386 ABI (pages 3-31, 3-32) says that when the program
- starts (a register; assume first param register for CRIS)
- contains a pointer to a function which might be
- registered using `atexit'. This provides a mean for the
- dynamic linker to call DT_FINI functions for shared libraries
- that have been loaded before the code runs.
-
- A value of 0 tells we have no such handler. */
-
-/* Explicitly set registers to 0 to increase determinism. */
-#define ELF_PLAT_INIT(_r, load_addr) do { \
- (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
- (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
- (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
- (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
-} while (0)
-
-/* The additional layer below is because the stack pointer is missing in
- the pt_regs struct, but needed in a core dump. pr_reg is a elf_gregset_t,
- and should be filled in according to the layout of the user_regs_struct
- struct; regs is a pt_regs struct. We dump all registers, though several are
- obviously unnecessary. That way there's less need for intelligence at
- the receiving end (i.e. gdb). */
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- pr_reg[0] = regs->r0; \
- pr_reg[1] = regs->r1; \
- pr_reg[2] = regs->r2; \
- pr_reg[3] = regs->r3; \
- pr_reg[4] = regs->r4; \
- pr_reg[5] = regs->r5; \
- pr_reg[6] = regs->r6; \
- pr_reg[7] = regs->r7; \
- pr_reg[8] = regs->r8; \
- pr_reg[9] = regs->r9; \
- pr_reg[10] = regs->r10; \
- pr_reg[11] = regs->r11; \
- pr_reg[12] = regs->r12; \
- pr_reg[13] = regs->r13; \
- pr_reg[14] = rdusp(); /* sp */ \
- pr_reg[15] = regs->irp; /* pc */ \
- pr_reg[16] = 0; /* p0 */ \
- pr_reg[17] = rdvr(); /* vr */ \
- pr_reg[18] = 0; /* p2 */ \
- pr_reg[19] = 0; /* p3 */ \
- pr_reg[20] = 0; /* p4 */ \
- pr_reg[21] = (regs->dccr & 0xffff); /* ccr */ \
- pr_reg[22] = 0; /* p6 */ \
- pr_reg[23] = regs->mof; /* mof */ \
- pr_reg[24] = 0; /* p8 */ \
- pr_reg[25] = 0; /* ibr */ \
- pr_reg[26] = 0; /* irp */ \
- pr_reg[27] = regs->srp; /* srp */ \
- pr_reg[28] = 0; /* bar */ \
- pr_reg[29] = regs->dccr; /* dccr */ \
- pr_reg[30] = 0; /* brp */ \
- pr_reg[31] = rdusp(); /* usp */ \
- pr_reg[32] = 0; /* csrinstr */ \
- pr_reg[33] = 0; /* csraddr */ \
- pr_reg[34] = 0; /* csrdata */
-
-
-#endif
diff --git a/arch/cris/include/uapi/asm/elf_v32.h b/arch/cris/include/uapi/asm/elf_v32.h
deleted file mode 100644
index cc00ffdb7f9c..000000000000
--- a/arch/cris/include/uapi/asm/elf_v32.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_CRIS_ELF_H
-#define _ASM_CRIS_ELF_H
-
-#define ELF_CORE_EFLAGS EF_CRIS_VARIANT_V32
-
-/* Matches struct user_regs_struct */
-#define ELF_NGREG 32
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
- ((x)->e_machine == EM_CRIS \
- && ((((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_V32 \
- || (((x)->e_flags & EF_CRIS_VARIANT_MASK) == EF_CRIS_VARIANT_COMMON_V10_V32))))
-
-/* CRISv32 ELF register definitions. */
-
-#include <asm/ptrace.h>
-
-/* Explicitly zero out registers to increase determinism. */
-#define ELF_PLAT_INIT(_r, load_addr) do { \
- (_r)->r13 = 0; (_r)->r12 = 0; (_r)->r11 = 0; (_r)->r10 = 0; \
- (_r)->r9 = 0; (_r)->r8 = 0; (_r)->r7 = 0; (_r)->r6 = 0; \
- (_r)->r5 = 0; (_r)->r4 = 0; (_r)->r3 = 0; (_r)->r2 = 0; \
- (_r)->r1 = 0; (_r)->r0 = 0; (_r)->mof = 0; (_r)->srp = 0; \
- (_r)->acr = 0; \
-} while (0)
-
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically.
- */
-#define elf_read_implies_exec_binary(ex, have_pt_gnu_stack) (!(have_pt_gnu_stack))
-
-/*
- * This is basically a pt_regs with the additional definition
- * of the stack pointer since it's needed in a core dump.
- * pr_regs is a elf_gregset_t and should be filled according
- * to the layout of user_regs_struct.
- */
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- pr_reg[0] = regs->r0; \
- pr_reg[1] = regs->r1; \
- pr_reg[2] = regs->r2; \
- pr_reg[3] = regs->r3; \
- pr_reg[4] = regs->r4; \
- pr_reg[5] = regs->r5; \
- pr_reg[6] = regs->r6; \
- pr_reg[7] = regs->r7; \
- pr_reg[8] = regs->r8; \
- pr_reg[9] = regs->r9; \
- pr_reg[10] = regs->r10; \
- pr_reg[11] = regs->r11; \
- pr_reg[12] = regs->r12; \
- pr_reg[13] = regs->r13; \
- pr_reg[14] = rdusp(); /* SP */ \
- pr_reg[15] = regs->acr; /* ACR */ \
- pr_reg[16] = 0; /* BZ */ \
- pr_reg[17] = rdvr(); /* VR */ \
- pr_reg[18] = 0; /* PID */ \
- pr_reg[19] = regs->srs; /* SRS */ \
- pr_reg[20] = 0; /* WZ */ \
- pr_reg[21] = regs->exs; /* EXS */ \
- pr_reg[22] = regs->eda; /* EDA */ \
- pr_reg[23] = regs->mof; /* MOF */ \
- pr_reg[24] = 0; /* DZ */ \
- pr_reg[25] = 0; /* EBP */ \
- pr_reg[26] = regs->erp; /* ERP */ \
- pr_reg[27] = regs->srp; /* SRP */ \
- pr_reg[28] = 0; /* NRP */ \
- pr_reg[29] = regs->ccs; /* CCS */ \
- pr_reg[30] = rdusp(); /* USP */ \
- pr_reg[31] = regs->spc; /* SPC */ \
-
-#endif /* _ASM_CRIS_ELF_H */
diff --git a/arch/cris/include/uapi/asm/ethernet.h b/arch/cris/include/uapi/asm/ethernet.h
deleted file mode 100644
index e0c1a6322824..000000000000
--- a/arch/cris/include/uapi/asm/ethernet.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * ioctl defines for ethernet driver
- *
- * Copyright (c) 2001 Axis Communications AB
- *
- * Author: Mikael Starvik
- *
- */
-
-#ifndef _CRIS_ETHERNET_H
-#define _CRIS_ETHERNET_H
-#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */
-#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */
-#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */
-#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */
-#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */
-#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */
-#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */
-#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */
-#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8
-#endif /* _CRIS_ETHERNET_H */
diff --git a/arch/cris/include/uapi/asm/etraxgpio.h b/arch/cris/include/uapi/asm/etraxgpio.h
deleted file mode 100644
index 10ab0dd45bfe..000000000000
--- a/arch/cris/include/uapi/asm/etraxgpio.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * The following devices are accessible using this driver using
- * GPIO_MAJOR (120) and a couple of minor numbers.
- *
- * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
- * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
- * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction
- * /dev/leds minor 2, Access to leds depending on kernelconfig
- * /dev/gpiog minor 3
- * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
- * g1-g7 and g25-g31 is both input and outputs but on different pins
- * Also note that some bits change pins depending on what interfaces
- * are enabled.
- */
-#ifndef _ASM_ETRAXGPIO_H
-#define _ASM_ETRAXGPIO_H
-
-#define GPIO_MINOR_FIRST 0
-
-#define ETRAXGPIO_IOCTYPE 43
-
-/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
-#define GPIO_MINOR_A 0
-#define GPIO_MINOR_B 1
-#define GPIO_MINOR_LEDS 2
-#define GPIO_MINOR_G 3
-#define GPIO_MINOR_LAST 3
-#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
-
-
-/* supported ioctl _IOC_NR's */
-
-#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
-#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */
-#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */
-
-/* the alarm is waited for by select() */
-
-#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */
-#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */
-#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */
-
-/* LED ioctl */
-#define IO_LEDACTIVE_SET 0x7 /* set active led
- * 0=off, 1=green, 2=red, 3=yellow */
-
-/* GPIO direction ioctl's */
-#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */
-#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input,
- returns mask with current inputs (obsolete) */
-#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output,
- returns mask with current outputs (obsolete)*/
-
-/* LED ioctl extended */
-#define IO_LED_SETBIT 0xB
-#define IO_LED_CLRBIT 0xC
-
-/* SHUTDOWN ioctl */
-#define IO_SHUTDOWN 0xD
-#define IO_GET_PWR_BT 0xE
-
-/* Bit toggling in driver settings */
-/* bit set in low byte0 is CLK mask (0x00FF),
- bit set in byte1 is DATA mask (0xFF00)
- msb, data_mask[7:0] , clk_mask[7:0]
- */
-#define IO_CFG_WRITE_MODE 0xF
-#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
- ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
-
-/* The following 4 ioctl's take a pointer as argument and handles
- * 32 bit ports (port G) properly.
- * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
- */
-#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */
-#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */
-#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */
- /* *arg updated with current input pins. */
-#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
- /* *arg updated with current output pins. */
-
-#endif
diff --git a/arch/cris/include/uapi/asm/ioctls.h b/arch/cris/include/uapi/asm/ioctls.h
deleted file mode 100644
index 92d654ce3d84..000000000000
--- a/arch/cris/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ARCH_CRIS_IOCTLS_H__
-#define __ARCH_CRIS_IOCTLS_H__
-
-#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
-#define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */
-#define TIOCSERWRRS485 0x5462 /* write rs-485 */
-#define TIOCSRS485 0x5463 /* enable rs-485 */
-
-#include <asm-generic/ioctls.h>
-
-#endif
diff --git a/arch/cris/include/uapi/asm/param.h b/arch/cris/include/uapi/asm/param.h
deleted file mode 100644
index ae296115c7c9..000000000000
--- a/arch/cris/include/uapi/asm/param.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASMCRIS_PARAM_H
-#define _ASMCRIS_PARAM_H
-
-/* Currently we assume that HZ=100 is good for CRIS. */
-
-#define EXEC_PAGESIZE 8192
-
-#include <asm-generic/param.h>
-
-#endif /* _ASMCRIS_PARAM_H */
diff --git a/arch/cris/include/uapi/asm/posix_types.h b/arch/cris/include/uapi/asm/posix_types.h
deleted file mode 100644
index c75d8b0acc99..000000000000
--- a/arch/cris/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */
-/* I guess we should write these in assembler because they are used often. */
-
-#ifndef __ARCH_CRIS_POSIX_TYPES_H
-#define __ARCH_CRIS_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* __ARCH_CRIS_POSIX_TYPES_H */
diff --git a/arch/cris/include/uapi/asm/ptrace.h b/arch/cris/include/uapi/asm/ptrace.h
deleted file mode 100644
index 99de59e54613..000000000000
--- a/arch/cris/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifdef __arch_v32
-#include <asm/ptrace_v32.h>
-#else
-#include <asm/ptrace_v10.h>
-#endif
diff --git a/arch/cris/include/uapi/asm/ptrace_v10.h b/arch/cris/include/uapi/asm/ptrace_v10.h
deleted file mode 100644
index 4ffffb7ab102..000000000000
--- a/arch/cris/include/uapi/asm/ptrace_v10.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_ARCH_PTRACE_H
-#define _CRIS_ARCH_PTRACE_H
-
-/* Frame types */
-
-#define CRIS_FRAME_NORMAL 0 /* normal frame without SBFS stacking */
-#define CRIS_FRAME_BUSFAULT 1 /* frame stacked using SBFS, need RBF return
- path */
-
-/* Register numbers in the ptrace system call interface */
-
-#define PT_FRAMETYPE 0
-#define PT_ORIG_R10 1
-#define PT_R13 2
-#define PT_R12 3
-#define PT_R11 4
-#define PT_R10 5
-#define PT_R9 6
-#define PT_R8 7
-#define PT_R7 8
-#define PT_R6 9
-#define PT_R5 10
-#define PT_R4 11
-#define PT_R3 12
-#define PT_R2 13
-#define PT_R1 14
-#define PT_R0 15
-#define PT_MOF 16
-#define PT_DCCR 17
-#define PT_SRP 18
-#define PT_IRP 19 /* This is actually the debugged process' PC */
-#define PT_CSRINSTR 20 /* CPU Status record remnants -
- valid if frametype == busfault */
-#define PT_CSRADDR 21
-#define PT_CSRDATA 22
-#define PT_USP 23 /* special case - USP is not in the pt_regs */
-#define PT_MAX 23
-
-/* Condition code bit numbers. The same numbers apply to CCR of course,
- but we use DCCR everywhere else, so let's try and be consistent. */
-#define C_DCCR_BITNR 0
-#define V_DCCR_BITNR 1
-#define Z_DCCR_BITNR 2
-#define N_DCCR_BITNR 3
-#define X_DCCR_BITNR 4
-#define I_DCCR_BITNR 5
-#define B_DCCR_BITNR 6
-#define M_DCCR_BITNR 7
-#define U_DCCR_BITNR 8
-#define P_DCCR_BITNR 9
-#define F_DCCR_BITNR 10
-
-/* pt_regs not only specifices the format in the user-struct during
- * ptrace but is also the frame format used in the kernel prologue/epilogues
- * themselves
- */
-
-struct pt_regs {
- unsigned long frametype; /* type of stackframe */
- unsigned long orig_r10;
- /* pushed by movem r13, [sp] in SAVE_ALL, movem pushes backwards */
- unsigned long r13;
- unsigned long r12;
- unsigned long r11;
- unsigned long r10;
- unsigned long r9;
- unsigned long r8;
- unsigned long r7;
- unsigned long r6;
- unsigned long r5;
- unsigned long r4;
- unsigned long r3;
- unsigned long r2;
- unsigned long r1;
- unsigned long r0;
- unsigned long mof;
- unsigned long dccr;
- unsigned long srp;
- unsigned long irp; /* This is actually the debugged process' PC */
- unsigned long csrinstr;
- unsigned long csraddr;
- unsigned long csrdata;
-};
-
-/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
- * when doing a context-switch. it is used (apart from in resume) when a new
- * thread is made and we need to make _resume (which is starting it for the
- * first time) realise what is going on.
- *
- * Actually, the use is very close to the thread struct (TSS) in that both the
- * switch_stack and the TSS are used to keep thread stuff when switching in
- * _resume.
- */
-
-struct switch_stack {
- unsigned long r9;
- unsigned long r8;
- unsigned long r7;
- unsigned long r6;
- unsigned long r5;
- unsigned long r4;
- unsigned long r3;
- unsigned long r2;
- unsigned long r1;
- unsigned long r0;
- unsigned long return_ip; /* ip that _resume will return to */
-};
-
-#ifdef __KERNEL__
-
-/* bit 8 is user-mode flag */
-#define user_mode(regs) (((regs)->dccr & 0x100) != 0)
-#define instruction_pointer(regs) ((regs)->irp)
-#define profile_pc(regs) instruction_pointer(regs)
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/cris/include/uapi/asm/ptrace_v32.h b/arch/cris/include/uapi/asm/ptrace_v32.h
deleted file mode 100644
index a91c4aacb14f..000000000000
--- a/arch/cris/include/uapi/asm/ptrace_v32.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_ARCH_PTRACE_H
-#define _CRIS_ARCH_PTRACE_H
-
-/* Register numbers in the ptrace system call interface */
-
-#define PT_ORIG_R10 0
-#define PT_R0 1
-#define PT_R1 2
-#define PT_R2 3
-#define PT_R3 4
-#define PT_R4 5
-#define PT_R5 6
-#define PT_R6 7
-#define PT_R7 8
-#define PT_R8 9
-#define PT_R9 10
-#define PT_R10 11
-#define PT_R11 12
-#define PT_R12 13
-#define PT_R13 14
-#define PT_ACR 15
-#define PT_SRS 16
-#define PT_MOF 17
-#define PT_SPC 18
-#define PT_CCS 19
-#define PT_SRP 20
-#define PT_ERP 21 /* This is actually the debugged process' PC */
-#define PT_EXS 22
-#define PT_EDA 23
-#define PT_USP 24 /* special case - USP is not in the pt_regs */
-#define PT_PPC 25 /* special case - pseudo PC */
-#define PT_BP 26 /* Base number for BP registers. */
-#define PT_BP_CTRL 26 /* BP control register. */
-#define PT_MAX 40
-
-/* Condition code bit numbers. */
-#define C_CCS_BITNR 0
-#define V_CCS_BITNR 1
-#define Z_CCS_BITNR 2
-#define N_CCS_BITNR 3
-#define X_CCS_BITNR 4
-#define I_CCS_BITNR 5
-#define U_CCS_BITNR 6
-#define P_CCS_BITNR 7
-#define R_CCS_BITNR 8
-#define S_CCS_BITNR 9
-#define M_CCS_BITNR 30
-#define Q_CCS_BITNR 31
-#define CCS_SHIFT 10 /* Shift count for each level in CCS */
-
-/* pt_regs not only specifices the format in the user-struct during
- * ptrace but is also the frame format used in the kernel prologue/epilogues
- * themselves
- */
-
-struct pt_regs {
- unsigned long orig_r10;
- /* pushed by movem r13, [sp] in SAVE_ALL. */
- unsigned long r0;
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- unsigned long r13;
- unsigned long acr;
- unsigned long srs;
- unsigned long mof;
- unsigned long spc;
- unsigned long ccs;
- unsigned long srp;
- unsigned long erp; /* This is actually the debugged process' PC */
- /* For debugging purposes; saved only when needed. */
- unsigned long exs;
- unsigned long eda;
-};
-
-/* switch_stack is the extra stuff pushed onto the stack in _resume (entry.S)
- * when doing a context-switch. it is used (apart from in resume) when a new
- * thread is made and we need to make _resume (which is starting it for the
- * first time) realise what is going on.
- *
- * Actually, the use is very close to the thread struct (TSS) in that both the
- * switch_stack and the TSS are used to keep thread stuff when switching in
- * _resume.
- */
-
-struct switch_stack {
- unsigned long r0;
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long return_ip; /* ip that _resume will return to */
-};
-
-#ifdef __KERNEL__
-
-#define arch_has_single_step() (1)
-#define user_mode(regs) (((regs)->ccs & (1 << (U_CCS_BITNR + CCS_SHIFT))) != 0)
-#define instruction_pointer(regs) ((regs)->erp)
-#define profile_pc(regs) instruction_pointer(regs)
-
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/cris/include/uapi/asm/rs485.h b/arch/cris/include/uapi/asm/rs485.h
deleted file mode 100644
index 041d31fa33d5..000000000000
--- a/arch/cris/include/uapi/asm/rs485.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* RS-485 structures */
-
-/* Used with ioctl() TIOCSERSETRS485 for backward compatibility!
- * XXX: Do not use it for new code!
- */
-struct rs485_control {
- unsigned short rts_on_send;
- unsigned short rts_after_sent;
- unsigned long delay_rts_before_send;
- unsigned short enabled;
-};
-
-/* Used with ioctl() TIOCSERWRRS485 */
-struct rs485_write {
- unsigned short outc_size;
- unsigned char *outc;
-};
-
diff --git a/arch/cris/include/uapi/asm/setup.h b/arch/cris/include/uapi/asm/setup.h
deleted file mode 100644
index 4854ace9db76..000000000000
--- a/arch/cris/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_SETUP_H
-#define _CRIS_SETUP_H
-
-#define COMMAND_LINE_SIZE 256
-
-#endif
diff --git a/arch/cris/include/uapi/asm/sigcontext.h b/arch/cris/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 97565ce3f0b9..000000000000
--- a/arch/cris/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-#ifndef _ASM_CRIS_SIGCONTEXT_H
-#define _ASM_CRIS_SIGCONTEXT_H
-
-#include <asm/ptrace.h>
-
-/* This struct is saved by setup_frame in signal.c, to keep the current context while
- a signal handler is executed. It's restored by sys_sigreturn.
-
- To keep things simple, we use pt_regs here even though normally you just specify
- the list of regs to save. Then we can use copy_from_user on the entire regs instead
- of a bunch of get_user's as well...
-
-*/
-
-struct sigcontext {
- struct pt_regs regs; /* needs to be first */
- unsigned long oldmask;
- unsigned long usp; /* usp before stacking this gunk on it */
-};
-
-#endif
-
diff --git a/arch/cris/include/uapi/asm/signal.h b/arch/cris/include/uapi/asm/signal.h
deleted file mode 100644
index e4ab00f00111..000000000000
--- a/arch/cris/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_CRIS_SIGNAL_H
-#define _UAPI_ASM_CRIS_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems. */
-struct siginfo;
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-#define NSIG 32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP 1
-#define SIGINT 2
-#define SIGQUIT 3
-#define SIGILL 4
-#define SIGTRAP 5
-#define SIGABRT 6
-#define SIGIOT 6
-#define SIGBUS 7
-#define SIGFPE 8
-#define SIGKILL 9
-#define SIGUSR1 10
-#define SIGSEGV 11
-#define SIGUSR2 12
-#define SIGPIPE 13
-#define SIGALRM 14
-#define SIGTERM 15
-#define SIGSTKFLT 16
-#define SIGCHLD 17
-#define SIGCONT 18
-#define SIGSTOP 19
-#define SIGTSTP 20
-#define SIGTTIN 21
-#define SIGTTOU 22
-#define SIGURG 23
-#define SIGXCPU 24
-#define SIGXFSZ 25
-#define SIGVTALRM 26
-#define SIGPROF 27
-#define SIGWINCH 28
-#define SIGIO 29
-#define SIGPOLL SIGIO
-/*
-#define SIGLOST 29
-*/
-#define SIGPWR 30
-#define SIGSYS 31
-#define SIGUNUSED 31
-
-/* These should not be considered constants from userland. */
-#define SIGRTMIN 32
-#define SIGRTMAX _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-
-#define SA_NOCLDSTOP 0x00000001u
-#define SA_NOCLDWAIT 0x00000002u
-#define SA_SIGINFO 0x00000004u
-#define SA_ONSTACK 0x08000000u
-#define SA_RESTART 0x10000000u
-#define SA_NODEFER 0x40000000u
-#define SA_RESETHAND 0x80000000u
-
-#define SA_NOMASK SA_NODEFER
-#define SA_ONESHOT SA_RESETHAND
-
-#define SA_RESTORER 0x04000000
-
-#define MINSIGSTKSZ 2048
-#define SIGSTKSZ 8192
-
-#include <asm-generic/signal-defs.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-struct sigaction {
- union {
- __sighandler_t _sa_handler;
- void (*_sa_sigaction)(int, struct siginfo *, void *);
- } _u;
- sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void);
-};
-
-#define sa_handler _u._sa_handler
-#define sa_sigaction _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
- void *ss_sp;
- int ss_flags;
- size_t ss_size;
-} stack_t;
-
-
-#endif /* _UAPI_ASM_CRIS_SIGNAL_H */
diff --git a/arch/cris/include/uapi/asm/stat.h b/arch/cris/include/uapi/asm/stat.h
deleted file mode 100644
index cdb74d5862e4..000000000000
--- a/arch/cris/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _CRIS_STAT_H
-#define _CRIS_STAT_H
-
-/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in
- the kernel if necessary. */
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-#define STAT_HAVE_NSEC 1
-
-struct stat {
- unsigned long st_dev;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned long st_rdev;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long st_atime_nsec;
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad0[4];
-
-#define STAT64_HAS_BROKEN_ST_INO 1
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad3[4];
-
- long long st_size;
- unsigned long st_blksize;
-
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
- unsigned long __pad4; /* future possible st_blocks high bits */
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */
-
- unsigned long long st_ino;
-};
-
-#endif
diff --git a/arch/cris/include/uapi/asm/swab.h b/arch/cris/include/uapi/asm/swab.h
deleted file mode 100644
index 4adf1e9f0b09..000000000000
--- a/arch/cris/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * CRIS byte swapping.
- */
diff --git a/arch/cris/include/uapi/asm/sync_serial.h b/arch/cris/include/uapi/asm/sync_serial.h
deleted file mode 100644
index f2d468889ba9..000000000000
--- a/arch/cris/include/uapi/asm/sync_serial.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * ioctl defines for synchronous serial port driver
- *
- * Copyright (c) 2001-2003 Axis Communications AB
- *
- * Author: Mikael Starvik
- *
- */
-
-#ifndef SYNC_SERIAL_H
-#define SYNC_SERIAL_H
-
-#include <linux/ioctl.h>
-
-#define SSP_SPEED _IOR('S', 0, unsigned int)
-#define SSP_MODE _IOR('S', 1, unsigned int)
-#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int)
-#define SSP_IPOLARITY _IOR('S', 3, unsigned int)
-#define SSP_OPOLARITY _IOR('S', 4, unsigned int)
-#define SSP_SPI _IOR('S', 5, unsigned int)
-#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int)
-#define SSP_INPUT _IOR('S', 7, unsigned int)
-
-/* Values for SSP_SPEED */
-#define SSP150 0
-#define SSP300 1
-#define SSP600 2
-#define SSP1200 3
-#define SSP2400 4
-#define SSP4800 5
-#define SSP9600 6
-#define SSP19200 7
-#define SSP28800 8
-#define SSP57600 9
-#define SSP115200 10
-#define SSP230400 11
-#define SSP460800 12
-#define SSP921600 13
-#define SSP3125000 14
-#define CODEC 15
-#define CODEC_f32768 16
-
-#define FREQ_4MHz 0
-#define FREQ_2MHz 1
-#define FREQ_1MHz 2
-#define FREQ_512kHz 3
-#define FREQ_256kHz 4
-#define FREQ_128kHz 5
-#define FREQ_64kHz 6
-#define FREQ_32kHz 7
-/* FREQ_* with values where bit (value & 0x10) is set are */
-/* used for CODEC_f32768 */
-#define FREQ_4096kHz 16 /* CODEC_f32768 */
-
-/* Used by application to set CODEC divider, word rate and frame rate */
-#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \
- ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \
- (clk_per_sync << 16) | (sync_per_frame << 28))
-
-/* Used by driver to extract speed */
-#define GET_SPEED(x) (x & 0xff)
-#define GET_FREQ(x) ((x & 0xff00) >> 8)
-#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1)
-#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1)
-
-/* Values for SSP_MODE */
-#define MASTER_OUTPUT 0
-#define SLAVE_OUTPUT 1
-#define MASTER_INPUT 2
-#define SLAVE_INPUT 3
-#define MASTER_BIDIR 4
-#define SLAVE_BIDIR 5
-
-/* Values for SSP_FRAME_SYNC */
-#define NORMAL_SYNC 1
-#define EARLY_SYNC 2
-#define SECOND_WORD_SYNC 0x40000
-#define LATE_SYNC 0x80000
-
-#define BIT_SYNC 4
-#define WORD_SYNC 8
-#define EXTENDED_SYNC 0x10
-
-#define SYNC_OFF 0x20
-#define SYNC_ON 0x40
-#define WORD_SIZE_8 0x80
-#define WORD_SIZE_12 0x100
-#define WORD_SIZE_16 0x200
-#define WORD_SIZE_24 0x400
-#define WORD_SIZE_32 0x800
-#define BIT_ORDER_LSB 0x1000
-#define BIT_ORDER_MSB 0x2000
-#define FLOW_CONTROL_ENABLE 0x4000
-#define FLOW_CONTROL_DISABLE 0x8000
-#define CLOCK_GATED 0x10000
-#define CLOCK_NOT_GATED 0x20000
-
-/* Values for SSP_IPOLARITY and SSP_OPOLARITY */
-#define CLOCK_NORMAL 1
-#define CLOCK_INVERT 2
-#define CLOCK_INEGEDGE CLOCK_NORMAL
-#define CLOCK_IPOSEDGE CLOCK_INVERT
-#define FRAME_NORMAL 4
-#define FRAME_INVERT 8
-#define STATUS_NORMAL 0x10
-#define STATUS_INVERT 0x20
-
-/* Values for SSP_SPI */
-#define SPI_MASTER 0
-#define SPI_SLAVE 1
-
-/* Values for SSP_INBUFCHUNK */
-/* plain integer with the size of DMA chunks */
-
-/* To ensure that the timestamps are aligned with the data being read
- * the read length MUST be a multiple of the length of the DMA buffers.
- *
- * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below.
- */
-#define SSP_INPUT_CHUNK_SIZE 256
-
-/* Request struct to pass through the ioctl interface to read
- * data with timestamps.
- */
-struct ssp_request {
- char __user *buf; /* Where to put the data. */
- size_t len; /* Size of buf. MUST be a multiple of */
- /* SSP_INPUT_CHUNK_SIZE! */
- struct timespec ts; /* The time the data was sampled. */
-};
-
-#endif
diff --git a/arch/cris/include/uapi/asm/termbits.h b/arch/cris/include/uapi/asm/termbits.h
deleted file mode 100644
index 86925dc1fcae..000000000000
--- a/arch/cris/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */
-
-#ifndef __ARCH_ETRAX100_TERMBITS_H__
-#define __ARCH_ETRAX100_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IUCLC 0001000
-#define IXON 0002000
-#define IXANY 0004000
-#define IXOFF 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
-
-/* c_oflag bits */
-#define OPOST 0000001
-#define OLCUC 0000002
-#define ONLCR 0000004
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-#define OFILL 0000100
-#define OFDEL 0000200
-#define NLDLY 0000400
-#define NL0 0000000
-#define NL1 0000400
-#define CRDLY 0003000
-#define CR0 0000000
-#define CR1 0001000
-#define CR2 0002000
-#define CR3 0003000
-#define TABDLY 0014000
-#define TAB0 0000000
-#define TAB1 0004000
-#define TAB2 0010000
-#define TAB3 0014000
-#define XTABS 0014000
-#define BSDLY 0020000
-#define BS0 0000000
-#define BS1 0020000
-#define VTDLY 0040000
-#define VT0 0000000
-#define VT1 0040000
-#define FFDLY 0100000
-#define FF0 0000000
-#define FF1 0100000
-
-/* c_cflag bit meaning */
-/*
- * 3 2 1
- * 10 987 654 321 098 765 432 109 876 543 210
- * | | ||| CBAUD
- * obaud
- *
- * ||CSIZE
- *
- * |CSTOP
- * |CREAD
- * |CPARENB
- *
- * |CPARODD
- * |HUPCL
- * |CLOCAL
- * |CBAUDEX
- * 10 987 654 321 098 765 432 109 876 543 210
- * | || || CIBAUD, IBSHIFT=16
- * ibaud
- * |CMSPAR
- * | CRTSCTS
- * x x xxx xxx x x xx Free bits
- */
-
-#define CBAUD 0010017
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0000060
-#define CS5 0000000
-#define CS6 0000020
-#define CS7 0000040
-#define CS8 0000060
-#define CSTOPB 0000100
-#define CREAD 0000200
-#define PARENB 0000400
-#define PARODD 0001000
-#define HUPCL 0002000
-#define CLOCAL 0004000
-#define CBAUDEX 0010000
-#define BOTHER 0010000
-#define B57600 0010001
-#define B115200 0010002
-#define B230400 0010003
-#define B460800 0010004
-
-/* Unsupported rates, but needed to avoid compile error. */
-#define B500000 0010005
-#define B576000 0010006
-#define B1000000 0010010
-#define B1152000 0010011
-#define B1500000 0010012
-#define B2000000 0010013
-#define B2500000 0010014
-#define B3000000 0010015
-#define B3500000 0010016
-#define B4000000 0010017
-
-/* etrax supports these additional three baud rates */
-#define B921600 0010005
-#define B1843200 0010006
-#define B6250000 0010007
-/* ETRAX FS supports this as well */
-#define B12500000 0010010
-#define CIBAUD 002003600000 /* input baud rate (used in v32) */
-/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX
- * shifted left IBSHIFT bits.
- */
-#define IBSHIFT 16
-#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/
-#define CRTSCTS 020000000000 /* flow control */
-
-/* c_lflag bits */
-#define ISIG 0000001
-#define ICANON 0000002
-#define XCASE 0000004
-#define ECHO 0000010
-#define ECHOE 0000020
-#define ECHOK 0000040
-#define ECHONL 0000100
-#define NOFLSH 0000200
-#define TOSTOP 0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE 0004000
-#define FLUSHO 0010000
-#define PENDIN 0040000
-#define IEXTEN 0100000
-#define EXTPROC 0200000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif
diff --git a/arch/cris/include/uapi/asm/termios.h b/arch/cris/include/uapi/asm/termios.h
deleted file mode 100644
index d87800a6d854..000000000000
--- a/arch/cris/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_CRIS_TERMIOS_H
-#define _UAPI_CRIS_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-#include <asm/rs485.h>
-#include <linux/serial.h>
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-
-#endif /* _UAPI_CRIS_TERMIOS_H */
diff --git a/arch/cris/include/uapi/asm/unistd.h b/arch/cris/include/uapi/asm/unistd.h
deleted file mode 100644
index 7aba513b082d..000000000000
--- a/arch/cris/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_CRIS_UNISTD_H_
-#define _UAPI_ASM_CRIS_UNISTD_H_
-
-/*
- * This file contains the system call numbers, and stub macros for libc.
- */
-
-#define __NR_restart_syscall 0
-#define __NR_exit 1
-#define __NR_fork 2
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
-#define __NR_waitpid 7
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_lchown 16
-#define __NR_break 17
-#define __NR_oldstat 18
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
-#define __NR_umount 22
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
-#define __NR_oldfstat 28
-#define __NR_pause 29
-#define __NR_utime 30
-#define __NR_stty 31
-#define __NR_gtty 32
-#define __NR_access 33
-#define __NR_nice 34
-#define __NR_ftime 35
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
-#define __NR_prof 44
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
-#define __NR_signal 48
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
-#define __NR_lock 53
-#define __NR_ioctl 54
-#define __NR_fcntl 55
-#define __NR_mpx 56
-#define __NR_setpgid 57
-#define __NR_ulimit 58
-#define __NR_oldolduname 59
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
-#define __NR_sigaction 67
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
-#define __NR_sigsuspend 72
-#define __NR_sigpending 73
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
-#define __NR_getrlimit 76
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
-#define __NR_select 82
-#define __NR_symlink 83
-#define __NR_oldlstat 84
-#define __NR_readlink 85
-#define __NR_uselib 86
-#define __NR_swapon 87
-#define __NR_reboot 88
-#define __NR_readdir 89
-#define __NR_mmap 90
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
-#define __NR_profil 98
-#define __NR_statfs 99
-#define __NR_fstatfs 100
-#define __NR_ioperm 101
-#define __NR_socketcall 102
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
-#define __NR_olduname 109
-#define __NR_iopl 110
-#define __NR_vhangup 111
-#define __NR_idle 112
-#define __NR_vm86 113
-#define __NR_wait4 114
-#define __NR_swapoff 115
-#define __NR_sysinfo 116
-#define __NR_ipc 117
-#define __NR_fsync 118
-#define __NR_sigreturn 119
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
-#define __NR_modify_ldt 123
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
-#define __NR_sigprocmask 126
-#define __NR_create_module 127
-#define __NR_init_module 128
-#define __NR_delete_module 129
-#define __NR_get_kernel_syms 130
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
-#define __NR_sysfs 135
-#define __NR_personality 136
-#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
-#define __NR__newselect 142
-#define __NR_flock 143
-#define __NR_msync 144
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
-#define __NR_mlock 150
-#define __NR_munlock 151
-#define __NR_mlockall 152
-#define __NR_munlockall 153
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
-
-#define __NR_query_module 167
-#define __NR_poll 168
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread64 180
-#define __NR_pwrite64 181
-#define __NR_chown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
-#define __NR_getpmsg 188 /* some people actually want streams */
-#define __NR_putpmsg 189 /* some people actually want streams */
-#define __NR_vfork 190
-#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_lchown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_chown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
-#define __NR_mincore 218
-#define __NR_madvise 219
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
-/* 223 is unused */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
-#define __NR_set_thread_area 243
-#define __NR_get_thread_area 244
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
-#define __NR_fadvise64 250
-/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_epoll_create 254
-#define __NR_epoll_ctl 255
-#define __NR_epoll_wait 256
-#define __NR_remap_file_pages 257
-#define __NR_set_tid_address 258
-#define __NR_timer_create 259
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
-#define __NR_statfs64 268
-#define __NR_fstatfs64 269
-#define __NR_tgkill 270
-#define __NR_utimes 271
-#define __NR_fadvise64_64 272
-#define __NR_vserver 273
-#define __NR_mbind 274
-#define __NR_get_mempolicy 275
-#define __NR_set_mempolicy 276
-#define __NR_mq_open 277
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
-#define __NR_kexec_load 283
-#define __NR_waitid 284
-/* #define __NR_sys_setaltroot 285 */
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
-#define __NR_migrate_pages 294
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-#define __NR_set_robust_list 311
-#define __NR_get_robust_list 312
-#define __NR_splice 313
-#define __NR_sync_file_range 314
-#define __NR_tee 315
-#define __NR_vmsplice 316
-#define __NR_move_pages 317
-#define __NR_getcpu 318
-#define __NR_epoll_pwait 319
-#define __NR_utimensat 320
-#define __NR_signalfd 321
-#define __NR_timerfd_create 322
-#define __NR_eventfd 323
-#define __NR_fallocate 324
-#define __NR_timerfd_settime 325
-#define __NR_timerfd_gettime 326
-#define __NR_signalfd4 327
-#define __NR_eventfd2 328
-#define __NR_epoll_create1 329
-#define __NR_dup3 330
-#define __NR_pipe2 331
-#define __NR_inotify_init1 332
-#define __NR_preadv 333
-#define __NR_pwritev 334
-#define __NR_setns 335
-#define __NR_name_to_handle_at 336
-#define __NR_open_by_handle_at 337
-#define __NR_rt_tgsigqueueinfo 338
-#define __NR_perf_event_open 339
-#define __NR_recvmmsg 340
-#define __NR_accept4 341
-#define __NR_fanotify_init 342
-#define __NR_fanotify_mark 343
-#define __NR_prlimit64 344
-#define __NR_clock_adjtime 345
-#define __NR_syncfs 346
-#define __NR_sendmmsg 347
-#define __NR_process_vm_readv 348
-#define __NR_process_vm_writev 349
-#define __NR_kcmp 350
-#define __NR_finit_module 351
-#define __NR_sched_setattr 352
-#define __NR_sched_getattr 353
-#define __NR_renameat2 354
-#define __NR_seccomp 355
-#define __NR_getrandom 356
-#define __NR_memfd_create 357
-#define __NR_bpf 358
-#define __NR_execveat 359
-
-#endif /* _UAPI_ASM_CRIS_UNISTD_H_ */
diff --git a/arch/cris/kernel/Makefile b/arch/cris/kernel/Makefile
deleted file mode 100644
index f6bfee6c8c1b..000000000000
--- a/arch/cris/kernel/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the CRIS port.
-#
-
-CPPFLAGS_vmlinux.lds := -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE)
-extra-y := vmlinux.lds
-
-obj-y := process.o traps.o irq.o ptrace.o setup.o time.o sys_cris.o
-obj-y += stacktrace.o
-
-obj-$(CONFIG_MODULES) += crisksyms.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_SYSTEM_PROFILER) += profile.o
-
-clean:
-
diff --git a/arch/cris/kernel/asm-offsets.c b/arch/cris/kernel/asm-offsets.c
deleted file mode 100644
index 0a5129941485..000000000000
--- a/arch/cris/kernel/asm-offsets.c
+++ /dev/null
@@ -1,60 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/kbuild.h>
-#include <linux/sched.h>
-#include <asm/thread_info.h>
-
-/*
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed to extract
- * and format the required data.
- */
-
-#if !defined(CONFIG_ETRAX_ARCH_V10) && !defined(CONFIG_ETRAX_ARCH_V32)
-#error One of ARCH v10 and ARCH v32 must be true!
-#endif
-
-int main(void)
-{
-#define ENTRY(entry) DEFINE(PT_ ## entry, offsetof(struct pt_regs, entry))
- ENTRY(orig_r10);
- ENTRY(r13);
- ENTRY(r12);
- ENTRY(r11);
- ENTRY(r10);
- ENTRY(r9);
-#ifdef CONFIG_ETRAX_ARCH_V32
- ENTRY(acr);
- ENTRY(srs);
-#endif
- ENTRY(mof);
-#ifdef CONFIG_ETRAX_ARCH_V10
- ENTRY(dccr);
-#else
- ENTRY(ccs);
-#endif
- ENTRY(srp);
- BLANK();
-#undef ENTRY
-#define ENTRY(entry) DEFINE(TI_ ## entry, offsetof(struct thread_info, entry))
- ENTRY(task);
- ENTRY(flags);
- ENTRY(preempt_count);
- BLANK();
-#undef ENTRY
-#define ENTRY(entry) DEFINE(THREAD_ ## entry, offsetof(struct thread_struct, entry))
- ENTRY(ksp);
- ENTRY(usp);
-#ifdef CONFIG_ETRAX_ARCH_V10
- ENTRY(dccr);
-#else
- ENTRY(ccs);
-#endif
- BLANK();
-#undef ENTRY
-#define ENTRY(entry) DEFINE(TASK_ ## entry, offsetof(struct task_struct, entry))
- ENTRY(pid);
- BLANK();
- DEFINE(LCLONE_VM, CLONE_VM);
- DEFINE(LCLONE_UNTRACED, CLONE_UNTRACED);
- return 0;
-}
diff --git a/arch/cris/kernel/crisksyms.c b/arch/cris/kernel/crisksyms.c
deleted file mode 100644
index 7024f7278c89..000000000000
--- a/arch/cris/kernel/crisksyms.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/sched.h>
-#include <linux/in6.h>
-#include <linux/interrupt.h>
-#include <linux/pm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/tty.h>
-
-#include <asm/processor.h>
-#include <linux/uaccess.h>
-#include <asm/checksum.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/fasttimer.h>
-
-extern void __Udiv(void);
-extern void __Umod(void);
-extern void __Div(void);
-extern void __Mod(void);
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __lshrdi3(void);
-extern void __negdi2(void);
-extern void iounmap(volatile void * __iomem);
-
-/* Platform dependent support */
-EXPORT_SYMBOL(loops_per_usec);
-
-/* Math functions */
-EXPORT_SYMBOL(__Udiv);
-EXPORT_SYMBOL(__Umod);
-EXPORT_SYMBOL(__Div);
-EXPORT_SYMBOL(__Mod);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__negdi2);
-
-/* Memory functions */
-EXPORT_SYMBOL(__ioremap);
-EXPORT_SYMBOL(iounmap);
-
-#undef memcpy
-#undef memset
-extern void * memset(void *, int, __kernel_size_t);
-extern void * memcpy(void *, const void *, __kernel_size_t);
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-#ifdef CONFIG_ETRAX_ARCH_V32
-#undef strcmp
-EXPORT_SYMBOL(strcmp);
-#endif
-
-#ifdef CONFIG_ETRAX_FAST_TIMER
-/* Fast timer functions */
-EXPORT_SYMBOL(fast_timer_list);
-EXPORT_SYMBOL(start_one_shot_timer);
-EXPORT_SYMBOL(del_fast_timer);
-EXPORT_SYMBOL(schedule_usleep);
-#endif
-EXPORT_SYMBOL(csum_partial);
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c
deleted file mode 100644
index 726cdf4bf2d8..000000000000
--- a/arch/cris/kernel/irq.c
+++ /dev/null
@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- *
- * linux/arch/cris/kernel/irq.c
- *
- * Copyright (c) 2000,2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- * This file contains the code used by various IRQ handling routines:
- * asking for different IRQs should be done through these routines
- * instead of just grabbing them. Thus setups with different IRQ numbers
- * shouldn't result in any weird surprises, and installing new handlers
- * should be easier.
- *
- */
-
-/*
- * IRQs are in fact implemented a bit like signal handlers for the kernel.
- * Naturally it's not a 1:1 relation, but there are similarities.
- */
-
-#include <linux/module.h>
-#include <linux/ptrace.h>
-#include <linux/irq.h>
-#include <linux/sched/debug.h>
-
-#include <linux/kernel_stat.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/random.h>
-#include <linux/init.h>
-#include <linux/seq_file.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-
-#include <asm/io.h>
-#include <arch/system.h>
-
-/* called by the assembler IRQ entry functions defined in irq.h
- * to dispatch the interrupts to registered handlers
- */
-
-asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
-{
- unsigned long sp;
- struct pt_regs *old_regs;
-
- trace_hardirqs_off();
-
- old_regs = set_irq_regs(regs);
- irq_enter();
- sp = rdsp();
- if (unlikely((sp & (PAGE_SIZE - 1)) < (PAGE_SIZE/8))) {
- printk("do_IRQ: stack overflow: %lX\n", sp);
- show_stack(NULL, (unsigned long *)sp);
- }
- generic_handle_irq(irq);
- irq_exit();
- set_irq_regs(old_regs);
-}
-
-void weird_irq(void)
-{
- local_irq_disable();
- printk("weird irq\n");
- while(1);
-}
-
diff --git a/arch/cris/kernel/module.c b/arch/cris/kernel/module.c
deleted file mode 100644
index af04cb6b6dc9..000000000000
--- a/arch/cris/kernel/module.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Kernel module help for i386.
- Copyright (C) 2001 Rusty Russell.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-
-#if 0
-#define DEBUGP printk
-#else
-#define DEBUGP(fmt , ...)
-#endif
-
-#ifdef CONFIG_ETRAX_KMALLOCED_MODULES
-void *module_alloc(unsigned long size)
-{
- return kmalloc(size, GFP_KERNEL);
-}
-
-/* Free memory returned from module_alloc */
-void module_memfree(void *module_region)
-{
- kfree(module_region);
-}
-#endif
-
-int apply_relocate_add(Elf32_Shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct module *me)
-{
- unsigned int i;
- Elf32_Rela *rela = (void *)sechdrs[relsec].sh_addr;
-
- DEBUGP ("Applying add relocate section %u to %u\n", relsec,
- sechdrs[relsec].sh_info);
-
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof (*rela); i++) {
- /* This is where to make the change */
- uint32_t *loc
- = ((void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
- + rela[i].r_offset);
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- Elf32_Sym *sym
- = ((Elf32_Sym *)sechdrs[symindex].sh_addr
- + ELF32_R_SYM (rela[i].r_info));
- switch (ELF32_R_TYPE(rela[i].r_info)) {
- case R_CRIS_32:
- *loc = sym->st_value + rela[i].r_addend;
- break;
- case R_CRIS_32_PCREL:
- *loc = sym->st_value - (unsigned)loc + rela[i].r_addend - 4;
- break;
- default:
- printk(KERN_ERR "module %s: Unknown relocation: %u\n",
- me->name, ELF32_R_TYPE(rela[i].r_info));
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c
deleted file mode 100644
index 50e5cf09841d..000000000000
--- a/arch/cris/kernel/process.c
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/process.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 2000-2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-/*
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/atomic.h>
-#include <asm/pgtable.h>
-#include <linux/uaccess.h>
-#include <asm/irq.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/init_task.h>
-#include <linux/sched.h>
-#include <linux/sched/task.h>
-#include <linux/fs.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/mqueue.h>
-#include <linux/reboot.h>
-#include <linux/rcupdate.h>
-
-//#define DEBUG
-
-extern void default_idle(void);
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-void arch_cpu_idle(void)
-{
- default_idle();
-}
-
-void hard_reset_now (void);
-
-void machine_restart(char *cmd)
-{
- hard_reset_now();
-}
-
-/*
- * Similar to machine_power_off, but don't shut off power. Add code
- * here to freeze the system for e.g. post-mortem debug purpose when
- * possible. This halt has nothing to do with the idle halt.
- */
-
-void machine_halt(void)
-{
-}
-
-/* If or when software power-off is implemented, add code here. */
-
-void machine_power_off(void)
-{
-}
-
-/*
- * When a process does an "exec", machine state like FPU and debug
- * registers need to be reset. This is a hook function for that.
- * Currently we don't have any such state to reset, so this is empty.
- */
-
-void flush_thread(void)
-{
-}
-
-/* Fill in the fpu structure for a core dump. */
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
-{
- return 0;
-}
diff --git a/arch/cris/kernel/profile.c b/arch/cris/kernel/profile.c
deleted file mode 100644
index d2f978ad129a..000000000000
--- a/arch/cris/kernel/profile.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <linux/uaccess.h>
-
-#define SAMPLE_BUFFER_SIZE 8192
-
-static char *sample_buffer;
-static char *sample_buffer_pos;
-static int prof_running = 0;
-
-void cris_profile_sample(struct pt_regs *regs)
-{
- if (!prof_running)
- return;
-
- if (user_mode(regs))
- *(unsigned int*)sample_buffer_pos = current->pid;
- else
- *(unsigned int*)sample_buffer_pos = 0;
-
- *(unsigned int *)(sample_buffer_pos + 4) = instruction_pointer(regs);
- sample_buffer_pos += 8;
-
- if (sample_buffer_pos == sample_buffer + SAMPLE_BUFFER_SIZE)
- sample_buffer_pos = sample_buffer;
-}
-
-static ssize_t
-read_cris_profile(struct file *file, char __user *buf,
- size_t count, loff_t *ppos)
-{
- unsigned long p = *ppos;
- ssize_t ret;
-
- ret = simple_read_from_buffer(buf, count, ppos, sample_buffer,
- SAMPLE_BUFFER_SIZE);
- if (ret < 0)
- return ret;
-
- memset(sample_buffer + p, 0, ret);
-
- return ret;
-}
-
-static ssize_t
-write_cris_profile(struct file *file, const char __user *buf,
- size_t count, loff_t *ppos)
-{
- sample_buffer_pos = sample_buffer;
- memset(sample_buffer, 0, SAMPLE_BUFFER_SIZE);
- return count < SAMPLE_BUFFER_SIZE ? count : SAMPLE_BUFFER_SIZE;
-}
-
-static const struct file_operations cris_proc_profile_operations = {
- .read = read_cris_profile,
- .write = write_cris_profile,
- .llseek = default_llseek,
-};
-
-static int __init init_cris_profile(void)
-{
- struct proc_dir_entry *entry;
-
- sample_buffer = kmalloc(SAMPLE_BUFFER_SIZE, GFP_KERNEL);
- if (!sample_buffer) {
- return -ENOMEM;
- }
-
- sample_buffer_pos = sample_buffer;
-
- entry = proc_create("system_profile", S_IWUSR | S_IRUGO, NULL,
- &cris_proc_profile_operations);
- if (entry) {
- proc_set_size(entry, SAMPLE_BUFFER_SIZE);
- }
- prof_running = 1;
-
- return 0;
-}
-__initcall(init_cris_profile);
-
diff --git a/arch/cris/kernel/ptrace.c b/arch/cris/kernel/ptrace.c
deleted file mode 100644
index af42789a1544..000000000000
--- a/arch/cris/kernel/ptrace.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/ptrace.c
- *
- * Parts taken from the m68k port.
- *
- * Copyright (c) 2000, 2001, 2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/tracehook.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-
-
-/* notification of userspace execution resumption
- * - triggered by current->work.notify_resume
- */
-extern int do_signal(int canrestart, struct pt_regs *regs);
-
-
-void do_notify_resume(int canrestart, struct pt_regs *regs,
- __u32 thread_info_flags)
-{
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal(canrestart,regs);
-
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
-
-void do_work_pending(int syscall, struct pt_regs *regs,
- unsigned int thread_flags)
-{
- do {
- if (likely(thread_flags & _TIF_NEED_RESCHED)) {
- schedule();
- } else {
- if (unlikely(!user_mode(regs)))
- return;
- local_irq_enable();
- if (thread_flags & _TIF_SIGPENDING) {
- do_signal(syscall, regs);
- syscall = 0;
- } else {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
- }
- local_irq_disable();
- thread_flags = current_thread_info()->flags;
- } while (thread_flags & _TIF_WORK_MASK);
-}
diff --git a/arch/cris/kernel/setup.c b/arch/cris/kernel/setup.c
deleted file mode 100644
index 1b61a7207afb..000000000000
--- a/arch/cris/kernel/setup.c
+++ /dev/null
@@ -1,214 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- *
- * linux/arch/cris/kernel/setup.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (c) 2001 Axis Communications AB
- */
-
-/*
- * This file handles the architecture-dependent parts of initialization
- */
-
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/pgtable.h>
-#include <linux/seq_file.h>
-#include <linux/screen_info.h>
-#include <linux/utsname.h>
-#include <linux/pfn.h>
-#include <linux/cpu.h>
-#include <linux/of.h>
-#include <linux/of_fdt.h>
-#include <asm/setup.h>
-#include <arch/system.h>
-#include <asm/sections.h>
-
-/*
- * Setup options
- */
-struct screen_info screen_info;
-
-extern int root_mountflags;
-
-char __initdata cris_command_line[COMMAND_LINE_SIZE] = { 0, };
-
-extern const unsigned long text_start, edata; /* set by the linker script */
-extern unsigned long dram_start, dram_end;
-
-extern unsigned long romfs_start, romfs_length, romfs_in_flash; /* from head.S */
-
-static struct cpu cpu_devices[NR_CPUS];
-
-extern void show_etrax_copyright(void); /* arch-vX/kernel/setup.c */
-
-/* This mainly sets up the memory area, and can be really confusing.
- *
- * The physical DRAM is virtually mapped into dram_start to dram_end
- * (usually c0000000 to c0000000 + DRAM size). The physical address is
- * given by the macro __pa().
- *
- * In this DRAM, the kernel code and data is loaded, in the beginning.
- * It really starts at c0004000 to make room for some special pages -
- * the start address is text_start. The kernel data ends at _end. After
- * this the ROM filesystem is appended (if there is any).
- *
- * Between this address and dram_end, we have RAM pages usable to the
- * boot code and the system.
- *
- */
-
-void __init setup_arch(char **cmdline_p)
-{
- extern void init_etrax_debug(void);
- unsigned long bootmap_size;
- unsigned long start_pfn, max_pfn;
- unsigned long memory_start;
-
-#ifdef CONFIG_OF
- early_init_dt_scan(__dtb_start);
-#endif
-
- /* register an initial console printing routine for printk's */
-
- init_etrax_debug();
-
- /* we should really poll for DRAM size! */
-
- high_memory = &dram_end;
-
- if(romfs_in_flash || !romfs_length) {
- /* if we have the romfs in flash, or if there is no rom filesystem,
- * our free area starts directly after the BSS
- */
- memory_start = (unsigned long) &_end;
- } else {
- /* otherwise the free area starts after the ROM filesystem */
- printk("ROM fs in RAM, size %lu bytes\n", romfs_length);
- memory_start = romfs_start + romfs_length;
- }
-
- /* process 1's initial memory region is the kernel code/data */
-
- init_mm.start_code = (unsigned long) &text_start;
- init_mm.end_code = (unsigned long) &_etext;
- init_mm.end_data = (unsigned long) &_edata;
- init_mm.brk = (unsigned long) &_end;
-
- /* min_low_pfn points to the start of DRAM, start_pfn points
- * to the first DRAM pages after the kernel, and max_low_pfn
- * to the end of DRAM.
- */
-
- /*
- * partially used pages are not usable - thus
- * we are rounding upwards:
- */
-
- start_pfn = PFN_UP(memory_start); /* usually c0000000 + kernel + romfs */
- max_pfn = PFN_DOWN((unsigned long)high_memory); /* usually c0000000 + dram size */
-
- /*
- * Initialize the boot-time allocator (start, end)
- *
- * We give it access to all our DRAM, but we could as well just have
- * given it a small slice. No point in doing that though, unless we
- * have non-contiguous memory and want the boot-stuff to be in, say,
- * the smallest area.
- *
- * It will put a bitmap of the allocated pages in the beginning
- * of the range we give it, but it won't mark the bitmaps pages
- * as reserved. We have to do that ourselves below.
- *
- * We need to use init_bootmem_node instead of init_bootmem
- * because our map starts at a quite high address (min_low_pfn).
- */
-
- max_low_pfn = max_pfn;
- min_low_pfn = PAGE_OFFSET >> PAGE_SHIFT;
-
- bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
- min_low_pfn,
- max_low_pfn);
-
- /* And free all memory not belonging to the kernel (addr, size) */
-
- free_bootmem(PFN_PHYS(start_pfn), PFN_PHYS(max_pfn - start_pfn));
-
- /*
- * Reserve the bootmem bitmap itself as well. We do this in two
- * steps (first step was init_bootmem()) because this catches
- * the (very unlikely) case of us accidentally initializing the
- * bootmem allocator with an invalid RAM area.
- *
- * Arguments are start, size
- */
-
- reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size, BOOTMEM_DEFAULT);
-
- unflatten_and_copy_device_tree();
-
- /* paging_init() sets up the MMU and marks all pages as reserved */
-
- paging_init();
-
- *cmdline_p = cris_command_line;
-
-#ifdef CONFIG_ETRAX_CMDLINE
- if (!strcmp(cris_command_line, "")) {
- strlcpy(cris_command_line, CONFIG_ETRAX_CMDLINE, COMMAND_LINE_SIZE);
- cris_command_line[COMMAND_LINE_SIZE - 1] = '\0';
- }
-#endif
-
- /* Save command line for future references. */
- memcpy(boot_command_line, cris_command_line, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-
- /* give credit for the CRIS port */
- show_etrax_copyright();
-
- /* Setup utsname */
- strcpy(init_utsname()->machine, cris_machine_name);
-}
-
-#ifdef CONFIG_PROC_FS
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return *pos < nr_cpu_ids ? (void *)(int)(*pos + 1) : NULL;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-extern int show_cpuinfo(struct seq_file *m, void *v);
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-#endif /* CONFIG_PROC_FS */
-
-static int __init topology_init(void)
-{
- int i;
-
- for_each_possible_cpu(i) {
- return register_cpu(&cpu_devices[i], i);
- }
-
- return 0;
-}
-
-subsys_initcall(topology_init);
diff --git a/arch/cris/kernel/stacktrace.c b/arch/cris/kernel/stacktrace.c
deleted file mode 100644
index f1cc3aaacd8d..000000000000
--- a/arch/cris/kernel/stacktrace.c
+++ /dev/null
@@ -1,76 +0,0 @@
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/stacktrace.h>
-#include <asm/stacktrace.h>
-
-void walk_stackframe(unsigned long sp,
- int (*fn)(unsigned long addr, void *data),
- void *data)
-{
- unsigned long high = ALIGN(sp, THREAD_SIZE);
-
- for (; sp <= high - 4; sp += 4) {
- unsigned long addr = *(unsigned long *) sp;
-
- if (!kernel_text_address(addr))
- continue;
-
- if (fn(addr, data))
- break;
- }
-}
-
-struct stack_trace_data {
- struct stack_trace *trace;
- unsigned int no_sched_functions;
- unsigned int skip;
-};
-
-#ifdef CONFIG_STACKTRACE
-
-static int save_trace(unsigned long addr, void *d)
-{
- struct stack_trace_data *data = d;
- struct stack_trace *trace = data->trace;
-
- if (data->no_sched_functions && in_sched_functions(addr))
- return 0;
-
- if (data->skip) {
- data->skip--;
- return 0;
- }
-
- trace->entries[trace->nr_entries++] = addr;
-
- return trace->nr_entries >= trace->max_entries;
-}
-
-void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
-{
- struct stack_trace_data data;
- unsigned long sp;
-
- data.trace = trace;
- data.skip = trace->skip;
-
- if (tsk != current) {
- data.no_sched_functions = 1;
- sp = tsk->thread.ksp;
- } else {
- data.no_sched_functions = 0;
- sp = rdsp();
- }
-
- walk_stackframe(sp, save_trace, &data);
- if (trace->nr_entries < trace->max_entries)
- trace->entries[trace->nr_entries++] = ULONG_MAX;
-}
-
-void save_stack_trace(struct stack_trace *trace)
-{
- save_stack_trace_tsk(current, trace);
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
-
-#endif /* CONFIG_STACKTRACE */
diff --git a/arch/cris/kernel/sys_cris.c b/arch/cris/kernel/sys_cris.c
deleted file mode 100644
index ecea13f1d760..000000000000
--- a/arch/cris/kernel/sys_cris.c
+++ /dev/null
@@ -1,36 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* $Id: sys_cris.c,v 1.6 2004/03/11 11:38:40 starvik Exp $
- *
- * linux/arch/cris/kernel/sys_cris.c
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on some platforms.
- * Since we don't have to do any backwards compatibility, our
- * versions are done in the most "normal" way possible.
- *
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/syscalls.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/ipc.h>
-
-#include <linux/uaccess.h>
-#include <asm/segment.h>
-
-asmlinkage long
-sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
- unsigned long flags, unsigned long fd, unsigned long pgoff)
-{
- /* bug(?): 8Kb pages here */
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
-}
diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c
deleted file mode 100644
index 593239274f98..000000000000
--- a/arch/cris/kernel/time.c
+++ /dev/null
@@ -1,73 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/kernel/time.c
- *
- * Copyright (C) 1991, 1992, 1995 Linus Torvalds
- * Copyright (C) 1999, 2000, 2001 Axis Communications AB
- *
- * 1994-07-02 Alan Modra
- * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
- * 1995-03-26 Markus Kuhn
- * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
- * precision CMOS clock update
- * 1996-05-03 Ingo Molnar
- * fixed time warps in do_[slow|fast]_gettimeoffset()
- * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
- * "A Kernel Model for Precision Timekeeping" by Dave Mills
- *
- * Linux/CRIS specific code:
- *
- * Authors: Bjorn Wesen
- * Johan Adolfsson
- *
- */
-
-#include <linux/errno.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/jiffies.h>
-#include <linux/bcd.h>
-#include <linux/timex.h>
-#include <linux/init.h>
-#include <linux/profile.h>
-#include <linux/sched/clock.h>
-
-
-#define D(x)
-
-#define TICK_SIZE tick
-
-extern unsigned long loops_per_jiffy; /* init/main.c */
-unsigned long loops_per_usec;
-
-extern void cris_profile_sample(struct pt_regs* regs);
-
-void
-cris_do_profile(struct pt_regs* regs)
-{
-
-#ifdef CONFIG_SYSTEM_PROFILER
- cris_profile_sample(regs);
-#endif
-
-#ifdef CONFIG_PROFILING
- profile_tick(CPU_PROFILING);
-#endif
-}
-
-#ifndef CONFIG_GENERIC_SCHED_CLOCK
-unsigned long long sched_clock(void)
-{
- return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ) +
- get_ns_in_jiffie();
-}
-#endif
-
-static int
-__init init_udelay(void)
-{
- loops_per_usec = (loops_per_jiffy * HZ) / 1000000;
- return 0;
-}
-
-__initcall(init_udelay);
diff --git a/arch/cris/kernel/traps.c b/arch/cris/kernel/traps.c
deleted file mode 100644
index d4bc80469218..000000000000
--- a/arch/cris/kernel/traps.c
+++ /dev/null
@@ -1,241 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/traps.c
- *
- * Here we handle the break vectors not used by the system call
- * mechanism, as well as some general stack/register dumping
- * things.
- *
- * Copyright (C) 2000-2007 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- * Hans-Peter Nilsson
- *
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/utsname.h>
-#include <linux/sched/debug.h>
-#ifdef CONFIG_KALLSYMS
-#include <linux/kallsyms.h>
-#endif
-
-#include <asm/pgtable.h>
-#include <linux/uaccess.h>
-#include <arch/system.h>
-
-extern void arch_enable_nmi(void);
-extern void stop_watchdog(void);
-extern void reset_watchdog(void);
-extern void show_registers(struct pt_regs *regs);
-
-#ifdef CONFIG_DEBUG_BUGVERBOSE
-extern void handle_BUG(struct pt_regs *regs);
-#else
-#define handle_BUG(regs)
-#endif
-
-static int kstack_depth_to_print = 24;
-
-void (*nmi_handler)(struct pt_regs *);
-
-void show_trace(unsigned long *stack)
-{
- unsigned long addr, module_start, module_end;
- extern char _stext[], _etext[];
- int i;
-
- pr_err("\nCall Trace: ");
-
- i = 1;
- module_start = VMALLOC_START;
- module_end = VMALLOC_END;
-
- while (((long)stack & (THREAD_SIZE - 1)) != 0) {
- if (__get_user(addr, stack)) {
- /* This message matches "failing address" marked
- s390 in ksymoops, so lines containing it will
- not be filtered out by ksymoops. */
- pr_err("Failing address 0x%lx\n", (unsigned long)stack);
- break;
- }
- stack++;
-
- /*
- * If the address is either in the text segment of the
- * kernel, or in the region which contains vmalloc'ed
- * memory, it *may* be the address of a calling
- * routine; if so, print it so that someone tracing
- * down the cause of the crash will be able to figure
- * out the call path that was taken.
- */
- if (((addr >= (unsigned long)_stext) &&
- (addr <= (unsigned long)_etext)) ||
- ((addr >= module_start) && (addr <= module_end))) {
-#ifdef CONFIG_KALLSYMS
- print_ip_sym(addr);
-#else
- if (i && ((i % 8) == 0))
- pr_err("\n ");
- pr_err("[<%08lx>] ", addr);
- i++;
-#endif
- }
- }
-}
-
-/*
- * These constants are for searching for possible module text
- * segments. MODULE_RANGE is a guess of how much space is likely
- * to be vmalloced.
- */
-
-#define MODULE_RANGE (8*1024*1024)
-
-/*
- * The output (format, strings and order) is adjusted to be usable with
- * ksymoops-2.4.1 with some necessary CRIS-specific patches. Please don't
- * change it unless you're serious about adjusting ksymoops and syncing
- * with the ksymoops maintainer.
- */
-
-void
-show_stack(struct task_struct *task, unsigned long *sp)
-{
- unsigned long *stack, addr;
- int i;
-
- /*
- * debugging aid: "show_stack(NULL);" prints a
- * back trace.
- */
-
- if (sp == NULL) {
- if (task)
- sp = (unsigned long*)task->thread.ksp;
- else
- sp = (unsigned long*)rdsp();
- }
-
- stack = sp;
-
- pr_err("\nStack from %08lx:\n ", (unsigned long)stack);
- for (i = 0; i < kstack_depth_to_print; i++) {
- if (((long)stack & (THREAD_SIZE-1)) == 0)
- break;
- if (i && ((i % 8) == 0))
- pr_err("\n ");
- if (__get_user(addr, stack)) {
- /* This message matches "failing address" marked
- s390 in ksymoops, so lines containing it will
- not be filtered out by ksymoops. */
- pr_err("Failing address 0x%lx\n", (unsigned long)stack);
- break;
- }
- stack++;
- pr_err("%08lx ", addr);
- }
- show_trace(sp);
-}
-
-#if 0
-/* displays a short stack trace */
-
-int
-show_stack(void)
-{
- unsigned long *sp = (unsigned long *)rdusp();
- int i;
-
- pr_err("Stack dump [0x%08lx]:\n", (unsigned long)sp);
- for (i = 0; i < 16; i++)
- pr_err("sp + %d: 0x%08lx\n", i*4, sp[i]);
- return 0;
-}
-#endif
-
-void set_nmi_handler(void (*handler)(struct pt_regs *))
-{
- nmi_handler = handler;
- arch_enable_nmi();
-}
-
-#ifdef CONFIG_DEBUG_NMI_OOPS
-void oops_nmi_handler(struct pt_regs *regs)
-{
- stop_watchdog();
- oops_in_progress = 1;
- pr_err("NMI!\n");
- show_registers(regs);
- oops_in_progress = 0;
- oops_exit();
- pr_err("\n"); /* Flush mtdoops. */
-}
-
-static int __init oops_nmi_register(void)
-{
- set_nmi_handler(oops_nmi_handler);
- return 0;
-}
-
-__initcall(oops_nmi_register);
-
-#endif
-
-/*
- * This gets called from entry.S when the watchdog has bitten. Show something
- * similar to an Oops dump, and if the kernel is configured to be a nice
- * doggy, then halt instead of reboot.
- */
-void watchdog_bite_hook(struct pt_regs *regs)
-{
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- local_irq_disable();
- stop_watchdog();
- show_registers(regs);
-
- while (1)
- ; /* Do nothing. */
-#else
- show_registers(regs);
-#endif
-}
-
-/* This is normally the Oops function. */
-void die_if_kernel(const char *str, struct pt_regs *regs, long err)
-{
- if (user_mode(regs))
- return;
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- /*
- * This printout might take too long and could trigger
- * the watchdog normally. If NICE_DOGGY is set, simply
- * stop the watchdog during the printout.
- */
- stop_watchdog();
-#endif
-
- oops_enter();
- handle_BUG(regs);
-
- pr_err("Linux %s %s\n", utsname()->release, utsname()->version);
- pr_err("%s: %04lx\n", str, err & 0xffff);
-
- show_registers(regs);
-
- oops_exit();
- oops_in_progress = 0;
- pr_err("\n"); /* Flush mtdoops. */
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- reset_watchdog();
-#endif
- do_exit(SIGSEGV);
-}
-
-void __init trap_init(void)
-{
- /* Nothing needs to be done */
-}
diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S
deleted file mode 100644
index 9b232e0f673e..000000000000
--- a/arch/cris/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ld script to make the Linux/CRIS kernel
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- * It is VERY DANGEROUS to fiddle around with the symbols in this
- * script. It is for example quite vital that all generated sections
- * that are used are actually named here, otherwise the linker will
- * put them at the end, where the init stuff is which is FREED after
- * the kernel has booted.
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
-#ifdef CONFIG_ETRAX_VMEM_SIZE
-#define __CONFIG_ETRAX_VMEM_SIZE CONFIG_ETRAX_VMEM_SIZE
-#else
-#define __CONFIG_ETRAX_VMEM_SIZE 0
-#endif
-
-
-jiffies = jiffies_64;
-SECTIONS
-{
- . = DRAM_VIRTUAL_BASE;
- dram_start = .;
-#ifdef CONFIG_ETRAX_ARCH_V10
- ibr_start = .;
-#else
- ebp_start = .;
- /* The boot section is only necessary until the VCS top */
- /* level testbench includes both flash and DRAM. */
- .boot : { *(.boot) }
-#endif
-
- /* see head.S and pages reserved at the start */
- . = DRAM_VIRTUAL_BASE + 0x4000;
-
- _text = .; /* Text and read-only data. */
- text_start = .; /* Lots of aliases. */
- _stext = .;
- __stext = .;
- .text : {
- HEAD_TEXT
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- *(.fixup)
- *(.text.__*)
- }
-
- _etext = . ; /* End of text section. */
- __etext = .;
-
- EXCEPTION_TABLE(4)
-
- _sdata = .;
- RODATA
-
- . = ALIGN (4);
- ___data_start = . ;
- __Sdata = . ;
- .data : { /* Data */
- CACHELINE_ALIGNED_DATA(32)
- READ_MOSTLY_DATA(32)
- DATA_DATA
- }
- __edata = . ; /* End of data section. */
- _edata = . ;
-
- BUG_TABLE
-
- INIT_TASK_DATA_SECTION(PAGE_SIZE)
-
- . = ALIGN(PAGE_SIZE); /* Init code and data. */
- __init_begin = .;
- INIT_TEXT_SECTION(PAGE_SIZE)
- .init.data : { INIT_DATA }
- .init.setup : { INIT_SETUP(16) }
- .initcall.init : {
- INIT_CALLS
- }
-
- .con_initcall.init : {
- CON_INITCALL
- }
- SECURITY_INIT
-
- /* .exit.text is discarded at runtime, not link time,
- * to deal with references from __bug_table
- */
- .exit.text : {
- EXIT_TEXT
- }
- .exit.data : {
- EXIT_DATA
- }
-
-#ifdef CONFIG_ETRAX_ARCH_V10
-#ifdef CONFIG_BLK_DEV_INITRD
- .init.ramfs : {
- __initramfs_start = .;
- *(.init.ramfs)
- __initramfs_end = .;
- }
-#endif
-#endif
- __vmlinux_end = .; /* Last address of the physical file. */
-#ifdef CONFIG_ETRAX_ARCH_V32
- PERCPU_SECTION(32)
-
- .init.ramfs : {
- INIT_RAM_FS
- }
-#endif
-
- /*
- * We fill to the next page, so we can discard all init
- * pages without needing to consider what payload might be
- * appended to the kernel image.
- */
- . = ALIGN(PAGE_SIZE);
-
- __init_end = .;
-
- __data_end = . ; /* Move to _edata ? */
- BSS_SECTION(1, 1, 1)
-
- . = ALIGN (0x20);
- _end = .;
- __end = .;
-
- dram_end = dram_start + (CONFIG_ETRAX_DRAM_SIZE - __CONFIG_ETRAX_VMEM_SIZE)*1024*1024;
-
- DISCARDS
-}
diff --git a/arch/cris/mm/Makefile b/arch/cris/mm/Makefile
deleted file mode 100644
index d3ae08c90b4e..000000000000
--- a/arch/cris/mm/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for the linux cris-specific parts of the memory manager.
-#
-
-obj-y := init.o fault.o tlb.o ioremap.o
-
diff --git a/arch/cris/mm/fault.c b/arch/cris/mm/fault.c
deleted file mode 100644
index 29cc58038b98..000000000000
--- a/arch/cris/mm/fault.c
+++ /dev/null
@@ -1,390 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/cris/mm/fault.c
- *
- * Copyright (C) 2000-2010 Axis Communications AB
- */
-
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/extable.h>
-#include <linux/wait.h>
-#include <linux/sched/signal.h>
-#include <linux/uaccess.h>
-#include <arch/system.h>
-
-extern int find_fixup_code(struct pt_regs *);
-extern void die_if_kernel(const char *, struct pt_regs *, long);
-extern void show_registers(struct pt_regs *regs);
-
-/* debug of low-level TLB reload */
-#undef DEBUG
-
-#ifdef DEBUG
-#define D(x) x
-#else
-#define D(x)
-#endif
-
-/* debug of higher-level faults */
-#define DPG(x)
-
-/* current active page directory */
-
-DEFINE_PER_CPU(pgd_t *, current_pgd);
-unsigned long cris_signal_return_page;
-
-/*
- * This routine handles page faults. It determines the address,
- * and the problem, and then passes it off to one of the appropriate
- * routines.
- *
- * Notice that the address we're given is aligned to the page the fault
- * occurred in, since we only get the PFN in R_MMU_CAUSE not the complete
- * address.
- *
- * error_code:
- * bit 0 == 0 means no page found, 1 means protection fault
- * bit 1 == 0 means read, 1 means write
- *
- * If this routine detects a bad access, it returns 1, otherwise it
- * returns 0.
- */
-
-asmlinkage void
-do_page_fault(unsigned long address, struct pt_regs *regs,
- int protection, int writeaccess)
-{
- struct task_struct *tsk;
- struct mm_struct *mm;
- struct vm_area_struct * vma;
- siginfo_t info;
- int fault;
- unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
-
- D(printk(KERN_DEBUG
- "Page fault for %lX on %X at %lX, prot %d write %d\n",
- address, smp_processor_id(), instruction_pointer(regs),
- protection, writeaccess));
-
- tsk = current;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- *
- * NOTE2: This is done so that, when updating the vmalloc
- * mappings we don't have to walk all processes pgdirs and
- * add the high mappings all at once. Instead we do it as they
- * are used. However vmalloc'ed page entries have the PAGE_GLOBAL
- * bit set so sometimes the TLB can use a lingering entry.
- *
- * This verifies that the fault happens in kernel space
- * and that the fault was not a protection error (error_code & 1).
- */
-
- if (address >= VMALLOC_START &&
- !protection &&
- !user_mode(regs))
- goto vmalloc_fault;
-
- /* When stack execution is not allowed we store the signal
- * trampolines in the reserved cris_signal_return_page.
- * Handle this in the exact same way as vmalloc (we know
- * that the mapping is there and is valid so no need to
- * call handle_mm_fault).
- */
- if (cris_signal_return_page &&
- address == cris_signal_return_page &&
- !protection && user_mode(regs))
- goto vmalloc_fault;
-
- /* we can and should enable interrupts at this point */
- local_irq_enable();
-
- mm = tsk->mm;
- info.si_code = SEGV_MAPERR;
-
- /*
- * If we're in an interrupt, have pagefaults disabled or have no
- * user context, we must not take the fault.
- */
-
- if (faulthandler_disabled() || !mm)
- goto no_context;
-
- if (user_mode(regs))
- flags |= FAULT_FLAG_USER;
-retry:
- down_read(&mm->mmap_sem);
- vma = find_vma(mm, address);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= address)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
- if (user_mode(regs)) {
- /*
- * accessing the stack below usp is always a bug.
- * we get page-aligned addresses so we can only check
- * if we're within a page from usp, but that might be
- * enough to catch brutal errors at least.
- */
- if (address + PAGE_SIZE < rdusp())
- goto bad_area;
- }
- if (expand_stack(vma, address))
- goto bad_area;
-
- /*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
-
- good_area:
- info.si_code = SEGV_ACCERR;
-
- /* first do some preliminary protection checks */
-
- if (writeaccess == 2){
- if (!(vma->vm_flags & VM_EXEC))
- goto bad_area;
- } else if (writeaccess == 1) {
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- } else {
- if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
- goto bad_area;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
-
- fault = handle_mm_fault(vma, address, flags);
-
- if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
- return;
-
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
-
- if (flags & FAULT_FLAG_ALLOW_RETRY) {
- if (fault & VM_FAULT_MAJOR)
- tsk->maj_flt++;
- else
- tsk->min_flt++;
- if (fault & VM_FAULT_RETRY) {
- flags &= ~FAULT_FLAG_ALLOW_RETRY;
- flags |= FAULT_FLAG_TRIED;
-
- /*
- * No need to up_read(&mm->mmap_sem) as we would
- * have already released it in __lock_page_or_retry
- * in mm/filemap.c.
- */
-
- goto retry;
- }
- }
-
- up_read(&mm->mmap_sem);
- return;
-
- /*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
-
- bad_area:
- up_read(&mm->mmap_sem);
-
- bad_area_nosemaphore:
- DPG(show_registers(regs));
-
- /* User mode accesses just cause a SIGSEGV */
-
- if (user_mode(regs)) {
-#ifdef CONFIG_NO_SEGFAULT_TERMINATION
- DECLARE_WAIT_QUEUE_HEAD(wq);
-#endif
- printk(KERN_NOTICE "%s (pid %d) segfaults for page "
- "address %08lx at pc %08lx\n",
- tsk->comm, tsk->pid,
- address, instruction_pointer(regs));
-
- /* With DPG on, we've already dumped registers above. */
- DPG(if (0))
- show_registers(regs);
-
-#ifdef CONFIG_NO_SEGFAULT_TERMINATION
- wait_event_interruptible(wq, 0 == 1);
-#else
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
- info.si_addr = (void *)address;
- force_sig_info(SIGSEGV, &info, tsk);
-#endif
- return;
- }
-
- no_context:
-
- /* Are we prepared to handle this kernel fault?
- *
- * (The kernel has valid exception-points in the source
- * when it accesses user-memory. When it fails in one
- * of those points, we find it in a table and do a jump
- * to some fixup code that loads an appropriate error
- * code)
- */
-
- if (find_fixup_code(regs))
- return;
-
- /*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- if (!oops_in_progress) {
- oops_in_progress = 1;
- if ((unsigned long) (address) < PAGE_SIZE)
- printk(KERN_ALERT "Unable to handle kernel NULL "
- "pointer dereference");
- else
- printk(KERN_ALERT "Unable to handle kernel access"
- " at virtual address %08lx\n", address);
-
- die_if_kernel("Oops", regs, (writeaccess << 1) | protection);
- oops_in_progress = 0;
- }
-
- do_exit(SIGKILL);
-
- /*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-
- out_of_memory:
- up_read(&mm->mmap_sem);
- if (!user_mode(regs))
- goto no_context;
- pagefault_out_of_memory();
- return;
-
- do_sigbus:
- up_read(&mm->mmap_sem);
-
- /*
- * Send a sigbus, regardless of whether we were in kernel
- * or user mode.
- */
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (void *)address;
- force_sig_info(SIGBUS, &info, tsk);
-
- /* Kernel mode? Handle exceptions or die */
- if (!user_mode(regs))
- goto no_context;
- return;
-
-vmalloc_fault:
- {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Use current_pgd instead of tsk->active_mm->pgd
- * since the latter might be unavailable if this
- * code is executed in a misfortunately run irq
- * (like inside schedule() between switch_mm and
- * switch_to...).
- */
-
- int offset = pgd_index(address);
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd = (pgd_t *)per_cpu(current_pgd, smp_processor_id()) + offset;
- pgd_k = init_mm.pgd + offset;
-
- /* Since we're two-level, we don't need to do both
- * set_pgd and set_pmd (they do the same thing). If
- * we go three-level at some point, do the right thing
- * with pgd_present and set_pgd here.
- *
- * Also, since the vmalloc area is global, we don't
- * need to copy individual PTE's, it is enough to
- * copy the pgd pointer into the pte page of the
- * root task. If that is there, we'll find our pte if
- * it exists.
- */
-
- pud = pud_offset(pgd, address);
- pud_k = pud_offset(pgd_k, address);
- if (!pud_present(*pud_k))
- goto no_context;
-
- pmd = pmd_offset(pud, address);
- pmd_k = pmd_offset(pud_k, address);
-
- if (!pmd_present(*pmd_k))
- goto bad_area_nosemaphore;
-
- set_pmd(pmd, *pmd_k);
-
- /* Make sure the actual PTE exists as well to
- * catch kernel vmalloc-area accesses to non-mapped
- * addresses. If we don't do this, this will just
- * silently loop forever.
- */
-
- pte_k = pte_offset_kernel(pmd_k, address);
- if (!pte_present(*pte_k))
- goto no_context;
-
- return;
- }
-}
-
-/* Find fixup code. */
-int
-find_fixup_code(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
- /* in case of delay slot fault (v32) */
- unsigned long ip = (instruction_pointer(regs) & ~0x1);
-
- fixup = search_exception_tables(ip);
- if (fixup != 0) {
- /* Adjust the instruction pointer in the stackframe. */
- instruction_pointer(regs) = fixup->fixup;
- arch_fixup(regs);
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/cris/mm/init.c b/arch/cris/mm/init.c
deleted file mode 100644
index e41d9c833e1c..000000000000
--- a/arch/cris/mm/init.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/mm/init.c
- *
- * Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 2000,2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/gfp.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/proc_fs.h>
-#include <linux/kcore.h>
-#include <asm/tlb.h>
-#include <asm/sections.h>
-
-unsigned long empty_zero_page;
-EXPORT_SYMBOL(empty_zero_page);
-
-void __init mem_init(void)
-{
- BUG_ON(!mem_map);
-
- /* max/min_low_pfn was set by setup.c
- * now we just copy it to some other necessary places...
- *
- * high_memory was also set in setup.c
- */
- max_mapnr = max_low_pfn - min_low_pfn;
- free_all_bootmem();
- mem_init_print_info(NULL);
-}
-
-/* Free a range of init pages. Virtual addresses. */
-
-void free_init_pages(const char *what, unsigned long begin, unsigned long end)
-{
- unsigned long addr;
-
- for (addr = begin; addr < end; addr += PAGE_SIZE) {
- ClearPageReserved(virt_to_page(addr));
- init_page_count(virt_to_page(addr));
- free_page(addr);
- totalram_pages++;
- }
-
- printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
-}
-
-/* Free the pages occupied by initialization code. */
-
-void free_initmem(void)
-{
- free_initmem_default(-1);
-}
-
-/* Free the pages occupied by initrd code. */
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_init_pages("initrd memory",
- start,
- end);
-}
-#endif
diff --git a/arch/cris/mm/ioremap.c b/arch/cris/mm/ioremap.c
deleted file mode 100644
index 350bd2a86ade..000000000000
--- a/arch/cris/mm/ioremap.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/cris/mm/ioremap.c
- *
- * Re-map IO memory to kernel address space so that we can access it.
- * Needed for memory-mapped I/O devices mapped outside our normal DRAM
- * window (that is, all memory-mapped I/O devices).
- *
- * (C) Copyright 1995 1996 Linus Torvalds
- * CRIS-port by Axis Communications AB
- */
-
-#include <linux/vmalloc.h>
-#include <linux/io.h>
-#include <asm/pgalloc.h>
-#include <arch/memmap.h>
-
-/*
- * Generic mapping function (not visible outside):
- */
-
-/*
- * Remap an arbitrary physical address space into the kernel virtual
- * address space. Needed when the kernel wants to access high addresses
- * directly.
- *
- * NOTE! We need to allow non-page-aligned mappings too: we will obviously
- * have to convert them into an offset in a page-aligned mapping, but the
- * caller shouldn't need to know that small detail.
- */
-void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot)
-{
- void __iomem * addr;
- struct vm_struct * area;
- unsigned long offset, last_addr;
-
- /* Don't allow wraparound or zero size */
- last_addr = phys_addr + size - 1;
- if (!size || last_addr < phys_addr)
- return NULL;
-
- /*
- * Mappings have to be page-aligned
- */
- offset = phys_addr & ~PAGE_MASK;
- phys_addr &= PAGE_MASK;
- size = PAGE_ALIGN(last_addr+1) - phys_addr;
-
- /*
- * Ok, go for it..
- */
- area = get_vm_area(size, VM_IOREMAP);
- if (!area)
- return NULL;
- addr = (void __iomem *)area->addr;
- if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size,
- phys_addr, prot)) {
- vfree((void __force *)addr);
- return NULL;
- }
- return (void __iomem *) (offset + (char __iomem *)addr);
-}
-
-void __iomem * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
-{
- return __ioremap_prot(phys_addr, size,
- __pgprot(_PAGE_PRESENT | __READABLE |
- __WRITEABLE | _PAGE_GLOBAL |
- _PAGE_KERNEL | flags));
-}
-
-/**
- * ioremap_nocache - map bus memory into CPU space
- * @offset: bus address of the memory
- * @size: size of the resource to map
- *
- * Must be freed with iounmap.
- */
-
-void __iomem *ioremap_nocache(unsigned long phys_addr, unsigned long size)
-{
- return __ioremap(phys_addr | MEM_NON_CACHEABLE, size, 0);
-}
-EXPORT_SYMBOL(ioremap_nocache);
-
-void iounmap(volatile void __iomem *addr)
-{
- if (addr > high_memory)
- return vfree((void *) (PAGE_MASK & (unsigned long) addr));
-}
diff --git a/arch/cris/mm/tlb.c b/arch/cris/mm/tlb.c
deleted file mode 100644
index e0dbea62cb81..000000000000
--- a/arch/cris/mm/tlb.c
+++ /dev/null
@@ -1,117 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/cris/mm/tlb.c
- *
- * Copyright (C) 2000, 2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen (bjornw@axis.com)
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/mm_types.h>
-
-#include <asm/tlb.h>
-
-#define D(x)
-
-/* The TLB can host up to 64 different mm contexts at the same time.
- * The running context is R_MMU_CONTEXT, and each TLB entry contains a
- * page_id that has to match to give a hit. In page_id_map, we keep track
- * of which mm we have assigned to which page_id, so that we know when
- * to invalidate TLB entries.
- *
- * The last page_id is never running - it is used as an invalid page_id
- * so we can make TLB entries that will never match.
- *
- * Notice that we need to make the flushes atomic, otherwise an interrupt
- * handler that uses vmalloced memory might cause a TLB load in the middle
- * of a flush causing.
- */
-
-struct mm_struct *page_id_map[NUM_PAGEID];
-static int map_replace_ptr = 1; /* which page_id_map entry to replace next */
-
-/* the following functions are similar to those used in the PPC port */
-
-static inline void
-alloc_context(struct mm_struct *mm)
-{
- struct mm_struct *old_mm;
-
- D(printk("tlb: alloc context %d (%p)\n", map_replace_ptr, mm));
-
- /* did we replace an mm ? */
-
- old_mm = page_id_map[map_replace_ptr];
-
- if(old_mm) {
- /* throw out any TLB entries belonging to the mm we replace
- * in the map
- */
- flush_tlb_mm(old_mm);
-
- old_mm->context.page_id = NO_CONTEXT;
- }
-
- /* insert it into the page_id_map */
-
- mm->context.page_id = map_replace_ptr;
- page_id_map[map_replace_ptr] = mm;
-
- map_replace_ptr++;
-
- if(map_replace_ptr == INVALID_PAGEID)
- map_replace_ptr = 0; /* wrap around */
-}
-
-/*
- * if needed, get a new MMU context for the mm. otherwise nothing is done.
- */
-
-void
-get_mmu_context(struct mm_struct *mm)
-{
- if(mm->context.page_id == NO_CONTEXT)
- alloc_context(mm);
-}
-
-/* called by __exit_mm to destroy the used MMU context if any before
- * destroying the mm itself. this is only called when the last user of the mm
- * drops it.
- *
- * the only thing we really need to do here is mark the used PID slot
- * as empty.
- */
-
-void
-destroy_context(struct mm_struct *mm)
-{
- if(mm->context.page_id != NO_CONTEXT) {
- D(printk("destroy_context %d (%p)\n", mm->context.page_id, mm));
- flush_tlb_mm(mm); /* TODO this might be redundant ? */
- page_id_map[mm->context.page_id] = NULL;
- }
-}
-
-/* called once during VM initialization, from init.c */
-
-void __init
-tlb_init(void)
-{
- int i;
-
- /* clear the page_id map */
-
- for (i = 1; i < ARRAY_SIZE(page_id_map); i++)
- page_id_map[i] = NULL;
-
- /* invalidate the entire TLB */
-
- flush_tlb_all();
-
- /* the init_mm has context 0 from the boot */
-
- page_id_map[0] = &init_mm;
-}
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
deleted file mode 100644
index af369b05fed5..000000000000
--- a/arch/frv/Kconfig
+++ /dev/null
@@ -1,386 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config FRV
- bool
- default y
- select HAVE_IDE
- select HAVE_ARCH_TRACEHOOK
- select HAVE_PERF_EVENTS
- select HAVE_UID16
- select VIRT_TO_BUS
- select GENERIC_IRQ_SHOW
- select HAVE_DEBUG_BUGVERBOSE
- select ARCH_HAVE_NMI_SAFE_CMPXCHG
- select GENERIC_CPU_DEVICES
- select ARCH_HAS_DEVMEM_IS_ALLOWED
- select ARCH_WANT_IPC_PARSE_VERSION
- select OLD_SIGSUSPEND3
- select OLD_SIGACTION
- select HAVE_DEBUG_STACKOVERFLOW
- select ARCH_NO_COHERENT_DMA_MMAP
-
-config CPU_BIG_ENDIAN
- def_bool y
-
-config ZONE_DMA
- bool
- default y
-
-config RWSEM_GENERIC_SPINLOCK
- bool
- default y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
-
-config GENERIC_HWEIGHT
- bool
- default y
-
-config GENERIC_CALIBRATE_DELAY
- bool
- default n
-
-config TIME_LOW_RES
- bool
- default y
-
-config QUICKLIST
- bool
- default y
-
-config ARCH_HAS_ILOG2_U32
- bool
- default y
-
-config ARCH_HAS_ILOG2_U64
- bool
- default y
-
-config HZ
- int
- default 1000
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-
-menu "Fujitsu FR-V system setup"
-
-config MMU
- bool "MMU support"
- help
- This options switches on and off support for the FR-V MMU
- (effectively switching between vmlinux and uClinux). Not all FR-V
- CPUs support this. Currently only the FR451 has a sufficiently
- featured MMU.
-
-config FRV_OUTOFLINE_ATOMIC_OPS
- bool "Out-of-line the FRV atomic operations"
- default n
- help
- Setting this option causes the FR-V atomic operations to be mostly
- implemented out-of-line.
-
- See Documentation/frv/atomic-ops.txt for more information.
-
-config HIGHMEM
- bool "High memory support"
- depends on MMU
- default y
- help
- If you wish to use more than 256MB of memory with your MMU based
- system, you will need to select this option. The kernel can only see
- the memory between 0xC0000000 and 0xD0000000 directly... everything
- else must be kmapped.
-
- The arch is, however, capable of supporting up to 3GB of SDRAM.
-
-config HIGHPTE
- bool "Allocate page tables in highmem"
- depends on HIGHMEM
- default y
- help
- The VM uses one page of memory for each page table. For systems
- with a lot of RAM, this can be wasteful of precious low memory.
- Setting this option will put user-space page tables in high memory.
-
-source "mm/Kconfig"
-
-choice
- prompt "uClinux kernel load address"
- depends on !MMU
- default UCPAGE_OFFSET_C0000000
- help
- This option sets the base address for the uClinux kernel. The kernel
- will rearrange the SDRAM layout to start at this address, and move
- itself to start there. It must be greater than 0, and it must be
- sufficiently less than 0xE0000000 that the SDRAM does not intersect
- the I/O region.
-
- The base address must also be aligned such that the SDRAM controller
- can decode it. For instance, a 512MB SDRAM bank must be 512MB aligned.
-
-config UCPAGE_OFFSET_20000000
- bool "0x20000000"
-
-config UCPAGE_OFFSET_40000000
- bool "0x40000000"
-
-config UCPAGE_OFFSET_60000000
- bool "0x60000000"
-
-config UCPAGE_OFFSET_80000000
- bool "0x80000000"
-
-config UCPAGE_OFFSET_A0000000
- bool "0xA0000000"
-
-config UCPAGE_OFFSET_C0000000
- bool "0xC0000000 (Recommended)"
-
-endchoice
-
-config PAGE_OFFSET
- hex
- default 0x20000000 if UCPAGE_OFFSET_20000000
- default 0x40000000 if UCPAGE_OFFSET_40000000
- default 0x60000000 if UCPAGE_OFFSET_60000000
- default 0x80000000 if UCPAGE_OFFSET_80000000
- default 0xA0000000 if UCPAGE_OFFSET_A0000000
- default 0xC0000000
-
-config PROTECT_KERNEL
- bool "Protect core kernel against userspace"
- depends on !MMU
- default y
- help
- Selecting this option causes the uClinux kernel to change the
- permittivity of DAMPR register covering the core kernel image to
- prevent userspace accessing the underlying memory directly.
-
-choice
- prompt "CPU Caching mode"
- default FRV_DEFL_CACHE_WBACK
- help
- This option determines the default caching mode for the kernel.
-
- Write-Back caching mode involves the all reads and writes causing
- the affected cacheline to be read into the cache first before being
- operated upon. Memory is not then updated by a write until the cache
- is filled and a cacheline needs to be displaced from the cache to
- make room. Only at that point is it written back.
-
- Write-Behind caching is similar to Write-Back caching, except that a
- write won't fetch a cacheline into the cache if there isn't already
- one there; it will write directly to memory instead.
-
- Write-Through caching only fetches cachelines from memory on a
- read. Writes always get written directly to memory. If the affected
- cacheline is also in cache, it will be updated too.
-
- The final option is to turn of caching entirely.
-
- Note that not all CPUs support Write-Behind caching. If the CPU on
- which the kernel is running doesn't, it'll fall back to Write-Back
- caching.
-
-config FRV_DEFL_CACHE_WBACK
- bool "Write-Back"
-
-config FRV_DEFL_CACHE_WBEHIND
- bool "Write-Behind"
-
-config FRV_DEFL_CACHE_WTHRU
- bool "Write-Through"
-
-config FRV_DEFL_CACHE_DISABLED
- bool "Disabled"
-
-endchoice
-
-menu "CPU core support"
-
-config CPU_FR401
- bool "Include FR401 core support"
- depends on !MMU
- default y
- help
- This enables support for the FR401, FR401A and FR403 CPUs
-
-config CPU_FR405
- bool "Include FR405 core support"
- depends on !MMU
- default y
- help
- This enables support for the FR405 CPU
-
-config CPU_FR451
- bool "Include FR451 core support"
- default y
- help
- This enables support for the FR451 CPU
-
-config CPU_FR451_COMPILE
- bool "Specifically compile for FR451 core"
- depends on CPU_FR451 && !CPU_FR401 && !CPU_FR405 && !CPU_FR551
- default y
- help
- This causes appropriate flags to be passed to the compiler to
- optimise for the FR451 CPU
-
-config CPU_FR551
- bool "Include FR551 core support"
- depends on !MMU
- default y
- help
- This enables support for the FR555 CPU
-
-config CPU_FR551_COMPILE
- bool "Specifically compile for FR551 core"
- depends on CPU_FR551 && !CPU_FR401 && !CPU_FR405 && !CPU_FR451
- default y
- help
- This causes appropriate flags to be passed to the compiler to
- optimise for the FR555 CPU
-
-config FRV_L1_CACHE_SHIFT
- int
- default "5" if CPU_FR401 || CPU_FR405 || CPU_FR451
- default "6" if CPU_FR551
-
-endmenu
-
-choice
- prompt "System support"
- default MB93091_VDK
-
-config MB93091_VDK
- bool "MB93091 CPU board with or without motherboard"
-
-config MB93093_PDK
- bool "MB93093 PDK unit"
-
-endchoice
-
-if MB93091_VDK
-choice
- prompt "Motherboard support"
- default MB93090_MB00
-
-config MB93090_MB00
- bool "Use the MB93090-MB00 motherboard"
- help
- Select this option if the MB93091 CPU board is going to be used with
- a MB93090-MB00 VDK motherboard
-
-config MB93091_NO_MB
- bool "Use standalone"
- help
- Select this option if the MB93091 CPU board is going to be used
- without a motherboard
-
-endchoice
-endif
-
-config FUJITSU_MB93493
- bool "MB93493 Multimedia chip"
- help
- Select this option if the MB93493 multimedia chip is going to be
- used.
-
-choice
- prompt "GP-Relative data support"
- default GPREL_DATA_8
- help
- This option controls what data, if any, should be placed in the GP
- relative data sections. Using this means that the compiler can
- generate accesses to the data using GR16-relative addressing which
- is faster than absolute instructions and saves space (2 instructions
- per access).
-
- However, the GPREL region is limited in size because the immediate
- value used in the load and store instructions is limited to a 12-bit
- signed number.
-
- So if the linker starts complaining that accesses to GPREL data are
- out of range, try changing this option from the default.
-
- Note that modules will always be compiled with this feature disabled
- as the module data will not be in range of the GP base address.
-
-config GPREL_DATA_8
- bool "Put data objects of up to 8 bytes into GP-REL"
-
-config GPREL_DATA_4
- bool "Put data objects of up to 4 bytes into GP-REL"
-
-config GPREL_DATA_NONE
- bool "Don't use GP-REL"
-
-endchoice
-
-config FRV_ONCPU_SERIAL
- bool "Use on-CPU serial ports"
- select SERIAL_8250
- default y
-
-config PCI
- bool "Use PCI"
- depends on MB93090_MB00
- default y
- select GENERIC_PCI_IOMAP
- help
- Some FR-V systems (such as the MB93090-MB00 VDK) have PCI
- onboard. If you have one of these boards and you wish to use the PCI
- facilities, say Y here.
-
-config RESERVE_DMA_COHERENT
- bool "Reserve DMA coherent memory"
- depends on PCI && !MMU
- default y
- help
- Many PCI drivers require access to uncached memory for DMA device
- communications (such as is done with some Ethernet buffer rings). If
- a fully featured MMU is available, this can be done through page
- table settings, but if not, a region has to be set aside and marked
- with a special DAMPR register.
-
- Setting this option causes uClinux to set aside a portion of the
- available memory for use in this manner. The memory will then be
- unavailable for normal kernel use.
-
-source "drivers/pci/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-menu "Power management options"
-
-config ARCH_SUSPEND_POSSIBLE
- def_bool y
-
-source kernel/power/Kconfig
-endmenu
-
-endmenu
-
-
-menu "Executable formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/frv/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/frv/Kconfig.debug b/arch/frv/Kconfig.debug
deleted file mode 100644
index ecab6d8a79ed..000000000000
--- a/arch/frv/Kconfig.debug
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config GDBSTUB
- bool "Remote GDB kernel debugging"
- depends on DEBUG_KERNEL
- select DEBUG_INFO
- select FRAME_POINTER
- help
- If you say Y here, it will be possible to remotely debug the kernel
- using gdb. This enlarges your kernel ELF image disk size by several
- megabytes and requires a machine with more than 16 MB, better 32 MB
- RAM to avoid excessive linking time. This is only useful for kernel
- hackers. If unsure, say N.
-
-choice
- prompt "GDB stub port"
- default GDBSTUB_UART1
- depends on GDBSTUB
- help
- Select the on-CPU port used for GDB-stub
-
-config GDBSTUB_UART0
- bool "/dev/ttyS0"
-
-config GDBSTUB_UART1
- bool "/dev/ttyS1"
-
-endchoice
-
-config GDBSTUB_IMMEDIATE
- bool "Break into GDB stub immediately"
- depends on GDBSTUB
- help
- If you say Y here, GDB stub will break into the program as soon as
- possible, leaving the program counter at the beginning of
- start_kernel() in init/main.c.
-
-config GDB_CONSOLE
- bool "Console output to GDB"
- depends on GDBSTUB
- help
- If you are using GDB for remote debugging over a serial port and
- would like kernel messages to be formatted into GDB $O packets so
- that GDB prints them as program output, say 'Y'.
-
-endmenu
diff --git a/arch/frv/Makefile b/arch/frv/Makefile
deleted file mode 100644
index 2a8fb730d1ca..000000000000
--- a/arch/frv/Makefile
+++ /dev/null
@@ -1,90 +0,0 @@
-#
-# frv/Makefile
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies. Remember to do have actions
-# for "archclean" and "archdep" for cleaning up and making dependencies for
-# this architecture
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (c) 2003, 2004 Red Hat Inc.
-# - Written by David Howells <dhowells@redhat.com>
-# - Derived from arch/m68knommu/Makefile,
-# Copyright (c) 1999,2001 D. Jeff Dionne <jeff@lineo.ca>,
-# Rt-Control Inc. / Lineo, Inc.
-#
-# Copyright (C) 1998,1999 D. Jeff Dionne <jeff@uclinux.org>,
-# Kenneth Albanowski <kjahds@kjahds.com>,
-#
-# Based on arch/m68k/Makefile:
-# Copyright (C) 1994 by Hamish Macdonald
-#
-
-ifdef CONFIG_MMU
-UTS_SYSNAME = -DUTS_SYSNAME=\"Linux\"
-else
-UTS_SYSNAME = -DUTS_SYSNAME=\"uClinux\"
-endif
-
-KBUILD_AFLAGS_MODULE += -G0 -mlong-calls
-KBUILD_CFLAGS_MODULE += -G0 -mlong-calls
-
-ifdef CONFIG_GPREL_DATA_8
-KBUILD_CFLAGS += -G8
-else
-ifdef CONFIG_GPREL_DATA_4
-KBUILD_CFLAGS += -G4
-else
-ifdef CONFIG_GPREL_DATA_NONE
-KBUILD_CFLAGS += -G0
-endif
-endif
-endif
-
-#LDFLAGS_vmlinux := -Map linkmap.txt
-
-ifdef CONFIG_GC_SECTIONS
-KBUILD_CFLAGS += -ffunction-sections -fdata-sections
-endif
-
-ifndef CONFIG_FRAME_POINTER
-KBUILD_CFLAGS += -mno-linked-fp
-endif
-
-ifdef CONFIG_CPU_FR451_COMPILE
-KBUILD_CFLAGS += -mcpu=fr450
-KBUILD_AFLAGS += -mcpu=fr450
-else
-ifdef CONFIG_CPU_FR551_COMPILE
-KBUILD_CFLAGS += -mcpu=fr550
-KBUILD_AFLAGS += -mcpu=fr550
-else
-KBUILD_CFLAGS += -mcpu=fr400
-KBUILD_AFLAGS += -mcpu=fr400
-endif
-endif
-
-# pretend the kernel is going to run on an FR400 with no media-fp unit
-# - reserve CC3 for use with atomic ops
-# - all the extra registers are dealt with only at context switch time
-KBUILD_CFLAGS += -mno-fdpic -mgpr-32 -msoft-float -mno-media
-KBUILD_CFLAGS += -ffixed-fcc3 -ffixed-cc3 -ffixed-gr15 -ffixed-icc2
-KBUILD_AFLAGS += -mno-fdpic
-
-head-y := arch/frv/kernel/head.o
-
-core-y += arch/frv/kernel/ arch/frv/mm/
-libs-y += arch/frv/lib/
-
-core-$(CONFIG_MB93090_MB00) += arch/frv/mb93090-mb00/
-
-all: Image
-
-Image: vmlinux
- $(Q)$(MAKE) $(build)=arch/frv/boot $@
-
-archclean:
- $(Q)$(MAKE) $(clean)=arch/frv/boot
diff --git a/arch/frv/boot/Makefile b/arch/frv/boot/Makefile
deleted file mode 100644
index 636d5bbcd53f..000000000000
--- a/arch/frv/boot/Makefile
+++ /dev/null
@@ -1,76 +0,0 @@
-#
-# arch/arm/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995-2000 Russell King
-#
-
-targets := Image zImage bootpImage
-
-SYSTEM =$(LINUX)
-
-ZTEXTADDR = 0x02080000
-PARAMS_PHYS = 0x0207c000
-INITRD_PHYS = 0x02180000
-INITRD_VIRT = 0x02180000
-
-OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment
-
-#
-# If you don't define ZRELADDR above,
-# then it defaults to ZTEXTADDR
-#
-ifeq ($(ZRELADDR),)
-ZRELADDR = $(ZTEXTADDR)
-endif
-
-export SYSTEM ZTEXTADDR ZBSSADDR ZRELADDR INITRD_PHYS INITRD_VIRT PARAMS_PHYS
-
-Image: $(obj)/Image
-
-targets: $(obj)/Image
-
-$(obj)/Image: vmlinux FORCE
- $(OBJCOPY) $(OBJCOPYFLAGS) -S vmlinux $@
-
-#$(obj)/Image: $(CONFIGURE) $(SYSTEM)
-# $(OBJCOPY) $(OBJCOPYFLAGS) -g -S $(SYSTEM) $@
-
-bzImage: zImage
-
-zImage: $(CONFIGURE) compressed/$(LINUX)
- $(OBJCOPY) $(OBJCOPYFLAGS) -S compressed/$(LINUX) $@
-
-bootpImage: bootp/bootp
- $(OBJCOPY) $(OBJCOPYFLAGS) -S bootp/bootp $@
-
-compressed/$(LINUX): $(LINUX) dep
- @$(MAKE) -C compressed $(LINUX)
-
-bootp/bootp: zImage initrd
- @$(MAKE) -C bootp bootp
-
-initrd:
- @test "$(INITRD_VIRT)" != "" || (echo This architecture does not support INITRD; exit -1)
- @test "$(INITRD)" != "" || (echo You must specify INITRD; exit -1)
-
-#
-# installation
-#
-install: $(CONFIGURE) Image
- sh ./install.sh $(KERNELRELEASE) Image System.map "$(INSTALL_PATH)"
-
-zinstall: $(CONFIGURE) zImage
- sh ./install.sh $(KERNELRELEASE) zImage System.map "$(INSTALL_PATH)"
-
-#
-# miscellany
-#
-mrproper clean:
-# @$(MAKE) -C compressed clean
-# @$(MAKE) -C bootp clean
-
-dep:
diff --git a/arch/frv/defconfig b/arch/frv/defconfig
deleted file mode 100644
index b1b792610fdf..000000000000
--- a/arch/frv/defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_MMU=y
-CONFIG_FRV_OUTOFLINE_ATOMIC_OPS=y
-CONFIG_FRV_DEFL_CACHE_WTHRU=y
-CONFIG_GPREL_DATA_4=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_NET_PCI=y
-CONFIG_NE2K_PCI=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=1
-CONFIG_SERIAL_8250_RUNTIME_UARTS=1
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_STACKOVERFLOW=y
diff --git a/arch/frv/include/asm/Kbuild b/arch/frv/include/asm/Kbuild
deleted file mode 100644
index b16b9c48ea09..000000000000
--- a/arch/frv/include/asm/Kbuild
+++ /dev/null
@@ -1,12 +0,0 @@
-
-generic-y += device.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += irq_work.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += preempt.h
-generic-y += trace_clock.h
-generic-y += word-at-a-time.h
-generic-y += kprobes.h
diff --git a/arch/frv/include/asm/asm-offsets.h b/arch/frv/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/frv/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h
deleted file mode 100644
index e93c9494503a..000000000000
--- a/arch/frv/include/asm/atomic.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/* atomic.h: atomic operation emulation for FR-V
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_ATOMIC_H
-#define _ASM_ATOMIC_H
-
-#include <linux/types.h>
-#include <asm/cmpxchg.h>
-#include <asm/barrier.h>
-
-#ifdef CONFIG_SMP
-#error not SMP safe
-#endif
-
-#include <asm/atomic_defs.h>
-
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- *
- * We do not have SMP systems, so we don't have to deal with that.
- */
-
-#define ATOMIC_INIT(i) { (i) }
-#define atomic_read(v) READ_ONCE((v)->counter)
-#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
-
-static inline int atomic_inc_return(atomic_t *v)
-{
- return __atomic_add_return(1, &v->counter);
-}
-
-static inline int atomic_dec_return(atomic_t *v)
-{
- return __atomic_sub_return(1, &v->counter);
-}
-
-static inline int atomic_add_return(int i, atomic_t *v)
-{
- return __atomic_add_return(i, &v->counter);
-}
-
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
- return __atomic_sub_return(i, &v->counter);
-}
-
-static inline int atomic_add_negative(int i, atomic_t *v)
-{
- return atomic_add_return(i, v) < 0;
-}
-
-static inline void atomic_inc(atomic_t *v)
-{
- atomic_inc_return(v);
-}
-
-static inline void atomic_dec(atomic_t *v)
-{
- atomic_dec_return(v);
-}
-
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
-
-/*
- * 64-bit atomic ops
- */
-typedef struct {
- long long counter;
-} atomic64_t;
-
-#define ATOMIC64_INIT(i) { (i) }
-
-static inline long long atomic64_read(const atomic64_t *v)
-{
- long long counter;
-
- asm("ldd%I1 %M1,%0"
- : "=e"(counter)
- : "m"(v->counter));
-
- return counter;
-}
-
-static inline void atomic64_set(atomic64_t *v, long long i)
-{
- asm volatile("std%I0 %1,%M0"
- : "=m"(v->counter)
- : "e"(i));
-}
-
-static inline long long atomic64_inc_return(atomic64_t *v)
-{
- return __atomic64_add_return(1, &v->counter);
-}
-
-static inline long long atomic64_dec_return(atomic64_t *v)
-{
- return __atomic64_sub_return(1, &v->counter);
-}
-
-static inline long long atomic64_add_return(long long i, atomic64_t *v)
-{
- return __atomic64_add_return(i, &v->counter);
-}
-
-static inline long long atomic64_sub_return(long long i, atomic64_t *v)
-{
- return __atomic64_sub_return(i, &v->counter);
-}
-
-static inline long long atomic64_add_negative(long long i, atomic64_t *v)
-{
- return atomic64_add_return(i, v) < 0;
-}
-
-static inline void atomic64_inc(atomic64_t *v)
-{
- atomic64_inc_return(v);
-}
-
-static inline void atomic64_dec(atomic64_t *v)
-{
- atomic64_dec_return(v);
-}
-
-#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
-#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
-#define atomic64_inc_and_test(v) (atomic64_inc_return((v)) == 0)
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-#define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new))
-#define atomic_xchg(v, new) (xchg(&(v)->counter, new))
-#define atomic64_cmpxchg(v, old, new) (__cmpxchg_64(old, new, &(v)->counter))
-#define atomic64_xchg(v, new) (__xchg_64(new, &(v)->counter))
-
-static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- int c, old;
- c = atomic_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c;
-}
-
-static inline int atomic64_add_unless(atomic64_t *v, long long i, long long u)
-{
- long long c, old;
-
- c = atomic64_read(v);
- for (;;) {
- if (unlikely(c == u))
- break;
- old = atomic64_cmpxchg(v, c, c + i);
- if (likely(old == c))
- break;
- c = old;
- }
- return c != u;
-}
-
-static inline long long atomic64_dec_if_positive(atomic64_t *v)
-{
- long long c, old, dec;
-
- c = atomic64_read(v);
- for (;;) {
- dec = c - 1;
- if (unlikely(dec < 0))
- break;
- old = atomic64_cmpxchg((v), c, dec);
- if (likely(old == c))
- break;
- c = old;
- }
- return dec;
-}
-
-#define ATOMIC_OP(op) \
-static inline int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- return __atomic32_fetch_##op(i, &v->counter); \
-} \
-static inline void atomic_##op(int i, atomic_t *v) \
-{ \
- (void)__atomic32_fetch_##op(i, &v->counter); \
-} \
- \
-static inline long long atomic64_fetch_##op(long long i, atomic64_t *v) \
-{ \
- return __atomic64_fetch_##op(i, &v->counter); \
-} \
-static inline void atomic64_##op(long long i, atomic64_t *v) \
-{ \
- (void)__atomic64_fetch_##op(i, &v->counter); \
-}
-
-ATOMIC_OP(or)
-ATOMIC_OP(and)
-ATOMIC_OP(xor)
-ATOMIC_OP(add)
-ATOMIC_OP(sub)
-
-#undef ATOMIC_OP
-
-#endif /* _ASM_ATOMIC_H */
diff --git a/arch/frv/include/asm/atomic_defs.h b/arch/frv/include/asm/atomic_defs.h
deleted file mode 100644
index ce3b8a4efc12..000000000000
--- a/arch/frv/include/asm/atomic_defs.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#include <asm/spr-regs.h>
-
-#ifdef __ATOMIC_LIB__
-
-#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define ATOMIC_QUALS
-#define ATOMIC_EXPORT(x) EXPORT_SYMBOL(x)
-
-#else /* !OUTOFLINE && LIB */
-
-#define ATOMIC_OP_RETURN(op)
-#define ATOMIC_FETCH_OP(op)
-
-#endif /* OUTOFLINE */
-
-#else /* !__ATOMIC_LIB__ */
-
-#define ATOMIC_EXPORT(x)
-
-#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define ATOMIC_OP_RETURN(op) \
-extern int __atomic_##op##_return(int i, int *v); \
-extern long long __atomic64_##op##_return(long long i, long long *v);
-
-#define ATOMIC_FETCH_OP(op) \
-extern int __atomic32_fetch_##op(int i, int *v); \
-extern long long __atomic64_fetch_##op(long long i, long long *v);
-
-#else /* !OUTOFLINE && !LIB */
-
-#define ATOMIC_QUALS static inline
-
-#endif /* OUTOFLINE */
-#endif /* __ATOMIC_LIB__ */
-
-
-/*
- * Note on the 64 bit inline asm variants...
- *
- * CSTD is a conditional instruction and needs a constrained memory reference.
- * Normally 'U' provides the correct constraints for conditional instructions
- * and this is used for the 32 bit version, however 'U' does not appear to work
- * for 64 bit values (gcc-4.9)
- *
- * The exact constraint is that conditional instructions cannot deal with an
- * immediate displacement in the memory reference, so what we do is we read the
- * address through a volatile cast into a local variable in order to insure we
- * _have_ to compute the correct address without displacement. This allows us
- * to use the regular 'm' for the memory address.
- *
- * Furthermore, the %Ln operand, which prints the low word register (r+1),
- * really only works for registers, this means we cannot allow immediate values
- * for the 64 bit versions -- like we do for the 32 bit ones.
- *
- */
-
-#ifndef ATOMIC_OP_RETURN
-#define ATOMIC_OP_RETURN(op) \
-ATOMIC_QUALS int __atomic_##op##_return(int i, int *v) \
-{ \
- int val; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ld.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op"%I2 %1,%2,%1 \n" \
- " cst.p %1,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+U"(*v), "=&r"(val) \
- : "NPr"(i) \
- : "memory", "cc7", "cc3", "icc3" \
- ); \
- \
- return val; \
-} \
-ATOMIC_EXPORT(__atomic_##op##_return); \
- \
-ATOMIC_QUALS long long __atomic64_##op##_return(long long i, long long *v) \
-{ \
- long long *__v = READ_ONCE(v); \
- long long val; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ldd.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op"cc %L1,%L2,%L1,icc0 \n" \
- " "#op"x %1,%2,%1,icc0 \n" \
- " cstd.p %1,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+m"(*__v), "=&e"(val) \
- : "e"(i) \
- : "memory", "cc7", "cc3", "icc0", "icc3" \
- ); \
- \
- return val; \
-} \
-ATOMIC_EXPORT(__atomic64_##op##_return);
-#endif
-
-#ifndef ATOMIC_FETCH_OP
-#define ATOMIC_FETCH_OP(op) \
-ATOMIC_QUALS int __atomic32_fetch_##op(int i, int *v) \
-{ \
- int old, tmp; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ld.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op"%I3 %1,%3,%2 \n" \
- " cst.p %2,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+U"(*v), "=&r"(old), "=r"(tmp) \
- : "NPr"(i) \
- : "memory", "cc7", "cc3", "icc3" \
- ); \
- \
- return old; \
-} \
-ATOMIC_EXPORT(__atomic32_fetch_##op); \
- \
-ATOMIC_QUALS long long __atomic64_fetch_##op(long long i, long long *v) \
-{ \
- long long *__v = READ_ONCE(v); \
- long long old, tmp; \
- \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ldd.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " "#op" %L1,%L3,%L2 \n" \
- " "#op" %1,%3,%2 \n" \
- " cstd.p %2,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- : "+m"(*__v), "=&e"(old), "=e"(tmp) \
- : "e"(i) \
- : "memory", "cc7", "cc3", "icc3" \
- ); \
- \
- return old; \
-} \
-ATOMIC_EXPORT(__atomic64_fetch_##op);
-#endif
-
-ATOMIC_FETCH_OP(or)
-ATOMIC_FETCH_OP(and)
-ATOMIC_FETCH_OP(xor)
-ATOMIC_FETCH_OP(add)
-ATOMIC_FETCH_OP(sub)
-
-ATOMIC_OP_RETURN(add)
-ATOMIC_OP_RETURN(sub)
-
-#undef ATOMIC_FETCH_OP
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_QUALS
-#undef ATOMIC_EXPORT
diff --git a/arch/frv/include/asm/ax88796.h b/arch/frv/include/asm/ax88796.h
deleted file mode 100644
index 637e980393c5..000000000000
--- a/arch/frv/include/asm/ax88796.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* ax88796.h: access points to the driver for the AX88796 NE2000 clone
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_AX88796_H
-#define _ASM_AX88796_H
-
-#include <asm/mb-regs.h>
-
-#define AX88796_IOADDR (__region_CS1 + 0x200)
-#define AX88796_IRQ IRQ_CPU_EXTERNAL7
-#define AX88796_FULL_DUPLEX 0 /* force full duplex */
-#define AX88796_BUS_INFO "CS1#+0x200" /* bus info for ethtool */
-
-#endif /* _ASM_AX88796_H */
diff --git a/arch/frv/include/asm/barrier.h b/arch/frv/include/asm/barrier.h
deleted file mode 100644
index abbef470154c..000000000000
--- a/arch/frv/include/asm/barrier.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* FR-V CPU memory barrier definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_BARRIER_H
-#define _ASM_BARRIER_H
-
-#define nop() asm volatile ("nop"::)
-
-#define mb() asm volatile ("membar" : : :"memory")
-#define rmb() asm volatile ("membar" : : :"memory")
-#define wmb() asm volatile ("membar" : : :"memory")
-
-#include <asm-generic/barrier.h>
-
-#endif /* _ASM_BARRIER_H */
diff --git a/arch/frv/include/asm/bitops.h b/arch/frv/include/asm/bitops.h
deleted file mode 100644
index 0df8e95e3715..000000000000
--- a/arch/frv/include/asm/bitops.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/* bitops.h: bit operations for the Fujitsu FR-V CPUs
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_BITOPS_H
-#define _ASM_BITOPS_H
-
-#include <linux/compiler.h>
-#include <asm/byteorder.h>
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/ffz.h>
-
-#include <asm/atomic.h>
-
-static inline int test_and_clear_bit(unsigned long nr, volatile void *addr)
-{
- unsigned int *ptr = (void *)addr;
- unsigned int mask = 1UL << (nr & 31);
- ptr += nr >> 5;
- return (__atomic32_fetch_and(~mask, ptr) & mask) != 0;
-}
-
-static inline int test_and_set_bit(unsigned long nr, volatile void *addr)
-{
- unsigned int *ptr = (void *)addr;
- unsigned int mask = 1UL << (nr & 31);
- ptr += nr >> 5;
- return (__atomic32_fetch_or(mask, ptr) & mask) != 0;
-}
-
-static inline int test_and_change_bit(unsigned long nr, volatile void *addr)
-{
- unsigned int *ptr = (void *)addr;
- unsigned int mask = 1UL << (nr & 31);
- ptr += nr >> 5;
- return (__atomic32_fetch_xor(mask, ptr) & mask) != 0;
-}
-
-static inline void clear_bit(unsigned long nr, volatile void *addr)
-{
- test_and_clear_bit(nr, addr);
-}
-
-static inline void set_bit(unsigned long nr, volatile void *addr)
-{
- test_and_set_bit(nr, addr);
-}
-
-static inline void change_bit(unsigned long nr, volatile void *addr)
-{
- test_and_change_bit(nr, addr);
-}
-
-static inline void __clear_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- *a &= ~mask;
-}
-
-static inline void __set_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- *a |= mask;
-}
-
-static inline void __change_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- *a ^= mask;
-}
-
-static inline int __test_and_clear_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask, retval;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- retval = (mask & *a) != 0;
- *a &= ~mask;
- return retval;
-}
-
-static inline int __test_and_set_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask, retval;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- retval = (mask & *a) != 0;
- *a |= mask;
- return retval;
-}
-
-static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
-{
- volatile unsigned long *a = addr;
- int mask, retval;
-
- a += nr >> 5;
- mask = 1 << (nr & 31);
- retval = (mask & *a) != 0;
- *a ^= mask;
- return retval;
-}
-
-/*
- * This routine doesn't need to be atomic.
- */
-static inline int
-__constant_test_bit(unsigned long nr, const volatile void *addr)
-{
- return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
-}
-
-static inline int __test_bit(unsigned long nr, const volatile void *addr)
-{
- int * a = (int *) addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- return ((mask & *a) != 0);
-}
-
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#include <asm-generic/bitops/find.h>
-
-/**
- * fls - find last bit set
- * @x: the word to search
- *
- * This is defined the same way as ffs:
- * - return 32..1 to indicate bit 31..0 most significant bit set
- * - return 0 to indicate no bits set
- */
-#define fls(x) \
-({ \
- int bit; \
- \
- asm(" subcc %1,gr0,gr0,icc0 \n" \
- " ckne icc0,cc4 \n" \
- " cscan.p %1,gr0,%0 ,cc4,#1 \n" \
- " csub %0,%0,%0 ,cc4,#0 \n" \
- " csub %2,%0,%0 ,cc4,#1 \n" \
- : "=&r"(bit) \
- : "r"(x), "r"(32) \
- : "icc0", "cc4" \
- ); \
- \
- bit; \
-})
-
-/**
- * fls64 - find last bit set in a 64-bit value
- * @n: the value to search
- *
- * This is defined the same way as ffs:
- * - return 64..1 to indicate bit 63..0 most significant bit set
- * - return 0 to indicate no bits set
- */
-static inline __attribute__((const))
-int fls64(u64 n)
-{
- union {
- u64 ll;
- struct { u32 h, l; };
- } _;
- int bit, x, y;
-
- _.ll = n;
-
- asm(" subcc.p %3,gr0,gr0,icc0 \n"
- " subcc %4,gr0,gr0,icc1 \n"
- " ckne icc0,cc4 \n"
- " ckne icc1,cc5 \n"
- " norcr cc4,cc5,cc6 \n"
- " csub.p %0,%0,%0 ,cc6,1 \n"
- " orcr cc5,cc4,cc4 \n"
- " andcr cc4,cc5,cc4 \n"
- " cscan.p %3,gr0,%0 ,cc4,0 \n"
- " setlos #64,%1 \n"
- " cscan.p %4,gr0,%0 ,cc4,1 \n"
- " setlos #32,%2 \n"
- " csub.p %1,%0,%0 ,cc4,0 \n"
- " csub %2,%0,%0 ,cc4,1 \n"
- : "=&r"(bit), "=r"(x), "=r"(y)
- : "0r"(_.h), "r"(_.l)
- : "icc0", "icc1", "cc4", "cc5", "cc6"
- );
- return bit;
-
-}
-
-/**
- * ffs - find first bit set
- * @x: the word to search
- *
- * - return 32..1 to indicate bit 31..0 most least significant bit set
- * - return 0 to indicate no bits set
- */
-static inline __attribute__((const))
-int ffs(int x)
-{
- /* Note: (x & -x) gives us a mask that is the least significant
- * (rightmost) 1-bit of the value in x.
- */
- return fls(x & -x);
-}
-
-/**
- * __ffs - find first bit set
- * @x: the word to search
- *
- * - return 31..0 to indicate bit 31..0 most least significant bit set
- * - if no bits are set in x, the result is undefined
- */
-static inline __attribute__((const))
-int __ffs(unsigned long x)
-{
- int bit;
- asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
- return 31 - bit;
-}
-
-/**
- * __fls - find last (most-significant) set bit in a long word
- * @word: the word to search
- *
- * Undefined if no set bit exists, so code should check against 0 first.
- */
-static inline unsigned long __fls(unsigned long word)
-{
- unsigned long bit;
- asm("scan %1,gr0,%0" : "=r"(bit) : "r"(word));
- return bit;
-}
-
-/*
- * special slimline version of fls() for calculating ilog2_u32()
- * - note: no protection against n == 0
- */
-#define ARCH_HAS_ILOG2_U32
-static inline __attribute__((const))
-int __ilog2_u32(u32 n)
-{
- int bit;
- asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
- return 31 - bit;
-}
-
-/*
- * special slimline version of fls64() for calculating ilog2_u64()
- * - note: no protection against n == 0
- */
-#define ARCH_HAS_ILOG2_U64
-static inline __attribute__((const))
-int __ilog2_u64(u64 n)
-{
- union {
- u64 ll;
- struct { u32 h, l; };
- } _;
- int bit, x, y;
-
- _.ll = n;
-
- asm(" subcc %3,gr0,gr0,icc0 \n"
- " ckeq icc0,cc4 \n"
- " cscan.p %3,gr0,%0 ,cc4,0 \n"
- " setlos #63,%1 \n"
- " cscan.p %4,gr0,%0 ,cc4,1 \n"
- " setlos #31,%2 \n"
- " csub.p %1,%0,%0 ,cc4,0 \n"
- " csub %2,%0,%0 ,cc4,1 \n"
- : "=&r"(bit), "=r"(x), "=r"(y)
- : "0r"(_.h), "r"(_.l)
- : "icc0", "cc4"
- );
- return bit;
-}
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/le.h>
-
-#include <asm-generic/bitops/ext2-atomic-setbit.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_BITOPS_H */
diff --git a/arch/frv/include/asm/bug.h b/arch/frv/include/asm/bug.h
deleted file mode 100644
index dd01bcf42ee6..000000000000
--- a/arch/frv/include/asm/bug.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* bug.h: FRV bug trapping
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_BUG_H
-#define _ASM_BUG_H
-
-#include <linux/linkage.h>
-
-#ifdef CONFIG_BUG
-/*
- * Tell the user there is some problem.
- */
-extern asmlinkage void __debug_bug_trap(int signr);
-
-#ifdef CONFIG_NO_KERNEL_MSG
-#define _debug_bug_printk()
-#else
-extern void __debug_bug_printk(const char *file, unsigned line);
-#define _debug_bug_printk() __debug_bug_printk(__FILE__, __LINE__)
-#endif
-
-#define _debug_bug_trap(signr) \
-do { \
- __debug_bug_trap(signr); \
- asm volatile("nop"); \
-} while(1)
-
-#define HAVE_ARCH_BUG
-#define BUG() \
-do { \
- _debug_bug_printk(); \
- _debug_bug_trap(6 /*SIGABRT*/); \
-} while (0)
-
-#ifdef CONFIG_GDBSTUB
-#define HAVE_ARCH_KGDB_RAISE
-#define kgdb_raise(signr) do { _debug_bug_trap(signr); } while(0)
-
-#define HAVE_ARCH_KGDB_BAD_PAGE
-#define kgdb_bad_page(page) do { kgdb_raise(SIGABRT); } while(0)
-#endif
-
-#endif /* CONFIG_BUG */
-
-#include <asm-generic/bug.h>
-
-extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
-
-#endif
diff --git a/arch/frv/include/asm/bugs.h b/arch/frv/include/asm/bugs.h
deleted file mode 100644
index f2382be2b46c..000000000000
--- a/arch/frv/include/asm/bugs.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* bugs.h: arch bug checking entry
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-static inline void check_bugs(void)
-{
-}
diff --git a/arch/frv/include/asm/busctl-regs.h b/arch/frv/include/asm/busctl-regs.h
deleted file mode 100644
index bb0ff4816e27..000000000000
--- a/arch/frv/include/asm/busctl-regs.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* busctl-regs.h: FR400-series CPU bus controller registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_BUSCTL_REGS_H
-#define _ASM_BUSCTL_REGS_H
-
-/* bus controller registers */
-#define __get_LGCR() ({ *(volatile unsigned long *)(0xfe000010); })
-#define __get_LMAICR() ({ *(volatile unsigned long *)(0xfe000030); })
-#define __get_LEMBR() ({ *(volatile unsigned long *)(0xfe000040); })
-#define __get_LEMAM() ({ *(volatile unsigned long *)(0xfe000048); })
-#define __get_LCR(R) ({ *(volatile unsigned long *)(0xfe000100 + 8*(R)); })
-#define __get_LSBR(R) ({ *(volatile unsigned long *)(0xfe000c00 + 8*(R)); })
-#define __get_LSAM(R) ({ *(volatile unsigned long *)(0xfe000d00 + 8*(R)); })
-
-#define __set_LGCR(V) do { *(volatile unsigned long *)(0xfe000010) = (V); } while(0)
-#define __set_LMAICR(V) do { *(volatile unsigned long *)(0xfe000030) = (V); } while(0)
-#define __set_LEMBR(V) do { *(volatile unsigned long *)(0xfe000040) = (V); } while(0)
-#define __set_LEMAM(V) do { *(volatile unsigned long *)(0xfe000048) = (V); } while(0)
-#define __set_LCR(R,V) do { *(volatile unsigned long *)(0xfe000100 + 8*(R)) = (V); } while(0)
-#define __set_LSBR(R,V) do { *(volatile unsigned long *)(0xfe000c00 + 8*(R)) = (V); } while(0)
-#define __set_LSAM(R,V) do { *(volatile unsigned long *)(0xfe000d00 + 8*(R)) = (V); } while(0)
-
-/* FR401 SDRAM controller registers */
-#define __get_DBR(R) ({ *(volatile unsigned long *)(0xfe000e00 + 8*(R)); })
-#define __get_DAM(R) ({ *(volatile unsigned long *)(0xfe000f00 + 8*(R)); })
-
-/* FR551 SDRAM controller registers */
-#define __get_DARS(R) ({ *(volatile unsigned long *)(0xfeff0100 + 8*(R)); })
-#define __get_DAMK(R) ({ *(volatile unsigned long *)(0xfeff0110 + 8*(R)); })
-
-
-#endif /* _ASM_BUSCTL_REGS_H */
diff --git a/arch/frv/include/asm/cache.h b/arch/frv/include/asm/cache.h
deleted file mode 100644
index 2797163b8f4f..000000000000
--- a/arch/frv/include/asm/cache.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* cache.h: FRV cache definitions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_CACHE_H
-#define __ASM_CACHE_H
-
-
-/* bytes per L1 cache line */
-#define L1_CACHE_SHIFT (CONFIG_FRV_L1_CACHE_SHIFT)
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#define __cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
-#define ____cacheline_aligned __attribute__((aligned(L1_CACHE_BYTES)))
-
-#endif
diff --git a/arch/frv/include/asm/cacheflush.h b/arch/frv/include/asm/cacheflush.h
deleted file mode 100644
index edbac54ae015..000000000000
--- a/arch/frv/include/asm/cacheflush.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* cacheflush.h: FRV cache flushing routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CACHEFLUSH_H
-#define _ASM_CACHEFLUSH_H
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-
-/*
- * virtually-indexed cache management (our cache is physically indexed)
- */
-#define flush_cache_all() do {} while(0)
-#define flush_cache_mm(mm) do {} while(0)
-#define flush_cache_dup_mm(mm) do {} while(0)
-#define flush_cache_range(mm, start, end) do {} while(0)
-#define flush_cache_page(vma, vmaddr, pfn) do {} while(0)
-#define flush_cache_vmap(start, end) do {} while(0)
-#define flush_cache_vunmap(start, end) do {} while(0)
-#define flush_dcache_mmap_lock(mapping) do {} while(0)
-#define flush_dcache_mmap_unlock(mapping) do {} while(0)
-
-/*
- * physically-indexed cache management
- * - see arch/frv/lib/cache.S
- */
-extern void frv_dcache_writeback(unsigned long start, unsigned long size);
-extern void frv_cache_invalidate(unsigned long start, unsigned long size);
-extern void frv_icache_invalidate(unsigned long start, unsigned long size);
-extern void frv_cache_wback_inv(unsigned long start, unsigned long size);
-
-static inline void __flush_cache_all(void)
-{
- asm volatile(" dcef @(gr0,gr0),#1 \n"
- " icei @(gr0,gr0),#1 \n"
- " membar \n"
- : : : "memory"
- );
-}
-
-/* dcache/icache coherency... */
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-#ifdef CONFIG_MMU
-extern void flush_dcache_page(struct page *page);
-#else
-static inline void flush_dcache_page(struct page *page)
-{
- unsigned long addr = page_to_phys(page);
- frv_dcache_writeback(addr, addr + PAGE_SIZE);
-}
-#endif
-
-static inline void flush_page_to_ram(struct page *page)
-{
- flush_dcache_page(page);
-}
-
-static inline void flush_icache(void)
-{
- __flush_cache_all();
-}
-
-static inline void flush_icache_range(unsigned long start, unsigned long end)
-{
- frv_cache_wback_inv(start, end);
-}
-
-#ifdef CONFIG_MMU
-extern void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
- unsigned long start, unsigned long len);
-#else
-static inline void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
- unsigned long start, unsigned long len)
-{
- frv_cache_wback_inv(start, start + len);
-}
-#endif
-
-static inline void flush_icache_page(struct vm_area_struct *vma, struct page *page)
-{
- flush_icache_user_range(vma, page, page_to_phys(page), PAGE_SIZE);
-}
-
-/*
- * permit ptrace to access another process's address space through the icache
- * and the dcache
- */
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { \
- memcpy((dst), (src), (len)); \
- flush_icache_user_range((vma), (page), (vaddr), (len)); \
-} while(0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy((dst), (src), (len))
-
-#endif /* _ASM_CACHEFLUSH_H */
diff --git a/arch/frv/include/asm/checksum.h b/arch/frv/include/asm/checksum.h
deleted file mode 100644
index b77388c5901d..000000000000
--- a/arch/frv/include/asm/checksum.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* checksum.h: FRV checksumming
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CHECKSUM_H
-#define _ASM_CHECKSUM_H
-
-#include <linux/in6.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum);
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum, int *csum_err);
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- *
- */
-static inline
-__sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- unsigned int tmp, inc, sum = 0;
-
- asm(" addcc gr0,gr0,gr0,icc0\n" /* clear icc0.C */
- " subi %1,#4,%1 \n"
- "0: \n"
- " ldu.p @(%1,%3),%4 \n"
- " subicc %2,#1,%2,icc1 \n"
- " addxcc.p %4,%0,%0,icc0 \n"
- " bhi icc1,#2,0b \n"
-
- /* fold the 33-bit result into 16-bits */
- " addxcc gr0,%0,%0,icc0 \n"
- " srli %0,#16,%1 \n"
- " sethi #0,%0 \n"
- " add %1,%0,%0 \n"
- " srli %0,#16,%1 \n"
- " add %1,%0,%0 \n"
-
- : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (inc), "=&r"(tmp)
- : "0" (sum), "1" (iph), "2" (ihl), "3" (4),
- "m"(*(volatile struct { int _[100]; } *)iph)
- : "icc0", "icc1", "memory"
- );
-
- return (__force __sum16)~sum;
-}
-
-/*
- * Fold a partial checksum
- */
-static inline __sum16 csum_fold(__wsum sum)
-{
- unsigned int tmp;
-
- asm(" srli %0,#16,%1 \n"
- " sethi #0,%0 \n"
- " add %1,%0,%0 \n"
- " srli %0,#16,%1 \n"
- " add %1,%0,%0 \n"
- : "=r"(sum), "=&r"(tmp)
- : "0"(sum)
- );
-
- return (__force __sum16)~sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- asm(" addcc %1,%0,%0,icc0 \n"
- " addxcc %2,%0,%0,icc0 \n"
- " addxcc %3,%0,%0,icc0 \n"
- " addxcc gr0,%0,%0,icc0 \n"
- : "=r" (sum)
- : "r" (daddr), "r" (saddr), "r" (len + proto), "0"(sum)
- : "icc0"
- );
- return sum;
-}
-
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#define _HAVE_ARCH_IPV6_CSUM
-static inline __sum16
-csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
- __u32 len, __u8 proto, __wsum sum)
-{
- unsigned long tmp, tmp2;
-
- asm(" addcc %2,%0,%0,icc0 \n"
-
- /* add up the source addr */
- " ldi @(%3,0),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%3,4),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
- " ldi @(%3,8),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%3,12),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
-
- /* add up the dest addr */
- " ldi @(%4,0),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%4,4),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
- " ldi @(%4,8),%1 \n"
- " addxcc %1,%0,%0,icc0 \n"
- " ldi @(%4,12),%2 \n"
- " addxcc %2,%0,%0,icc0 \n"
-
- /* fold the 33-bit result into 16-bits */
- " addxcc gr0,%0,%0,icc0 \n"
- " srli %0,#16,%1 \n"
- " sethi #0,%0 \n"
- " add %1,%0,%0 \n"
- " srli %0,#16,%1 \n"
- " add %1,%0,%0 \n"
-
- : "=r" (sum), "=&r" (tmp), "=r" (tmp2)
- : "r" (saddr), "r" (daddr), "0" (sum), "2" (len + proto)
- : "icc0"
- );
-
- return (__force __sum16)~sum;
-}
-
-#endif /* _ASM_CHECKSUM_H */
diff --git a/arch/frv/include/asm/cmpxchg.h b/arch/frv/include/asm/cmpxchg.h
deleted file mode 100644
index ad1f11cfa92a..000000000000
--- a/arch/frv/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* xchg and cmpxchg operation emulation for FR-V
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_CMPXCHG_H
-#define _ASM_CMPXCHG_H
-
-#include <linux/types.h>
-
-/*****************************************************************************/
-/*
- * exchange value with memory
- */
-extern uint64_t __xchg_64(uint64_t i, volatile void *v);
-
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define xchg(ptr, x) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig; \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: \
- asm volatile( \
- "swap%I0 %M0,%1" \
- : "+m"(*__xg_ptr), "=r"(__xg_orig) \
- : "1"(x) \
- : "memory" \
- ); \
- break; \
- \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- \
- __xg_orig; \
-})
-
-#else
-
-extern uint32_t __xchg_32(uint32_t i, volatile void *v);
-
-#define xchg(ptr, x) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig; \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- __xg_orig; \
-})
-
-#endif
-
-/*****************************************************************************/
-/*
- * compare and conditionally exchange value with memory
- * - if (*ptr == test) then orig = *ptr; *ptr = test;
- * - if (*ptr != test) then orig = *ptr;
- */
-extern uint64_t __cmpxchg_64(uint64_t test, uint64_t new, volatile uint64_t *v);
-#define cmpxchg64(p, o, n) __cmpxchg_64((o), (n), (p))
-
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define cmpxchg(ptr, test, new) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig, __xg_tmp; \
- __typeof__(*(ptr)) __xg_test = (test); \
- __typeof__(*(ptr)) __xg_new = (new); \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: \
- asm volatile( \
- "0: \n" \
- " orcc gr0,gr0,gr0,icc3 \n" \
- " ckeq icc3,cc7 \n" \
- " ld.p %M0,%1 \n" \
- " orcr cc7,cc7,cc3 \n" \
- " sub%I4cc %1,%4,%2,icc0 \n" \
- " bne icc0,#0,1f \n" \
- " cst.p %3,%M0 ,cc3,#1 \n" \
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
- " beq icc3,#0,0b \n" \
- "1: \n" \
- : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
- : "r"(__xg_new), "NPr"(__xg_test) \
- : "memory", "cc7", "cc3", "icc3", "icc0" \
- ); \
- break; \
- \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- \
- __xg_orig; \
-})
-
-#else
-
-extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
-
-#define cmpxchg(ptr, test, new) \
-({ \
- __typeof__(ptr) __xg_ptr = (ptr); \
- __typeof__(*(ptr)) __xg_orig; \
- __typeof__(*(ptr)) __xg_test = (test); \
- __typeof__(*(ptr)) __xg_new = (new); \
- \
- switch (sizeof(__xg_orig)) { \
- case 4: __xg_orig = (__force __typeof__(*ptr)) \
- __cmpxchg_32((__force uint32_t *)__xg_ptr, \
- (__force uint32_t)__xg_test, \
- (__force uint32_t)__xg_new); break; \
- default: \
- __xg_orig = (__typeof__(__xg_orig))0; \
- asm volatile("break"); \
- break; \
- } \
- \
- __xg_orig; \
-})
-
-#endif
-
-#include <asm-generic/cmpxchg-local.h>
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
- unsigned long old,
- unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return cmpxchg((unsigned long *)ptr, old, new);
- default:
- return __cmpxchg_local_generic(ptr, old, new, size);
- }
-
- return old;
-}
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif /* _ASM_CMPXCHG_H */
diff --git a/arch/frv/include/asm/cpu-irqs.h b/arch/frv/include/asm/cpu-irqs.h
deleted file mode 100644
index 478f3498fcfe..000000000000
--- a/arch/frv/include/asm/cpu-irqs.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* cpu-irqs.h: on-CPU peripheral irqs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CPU_IRQS_H
-#define _ASM_CPU_IRQS_H
-
-#ifndef __ASSEMBLY__
-
-/* IRQ to level mappings */
-#define IRQ_GDBSTUB_LEVEL 15
-#define IRQ_UART_LEVEL 13
-
-#ifdef CONFIG_GDBSTUB_UART0
-#define IRQ_UART0_LEVEL IRQ_GDBSTUB_LEVEL
-#else
-#define IRQ_UART0_LEVEL IRQ_UART_LEVEL
-#endif
-
-#ifdef CONFIG_GDBSTUB_UART1
-#define IRQ_UART1_LEVEL IRQ_GDBSTUB_LEVEL
-#else
-#define IRQ_UART1_LEVEL IRQ_UART_LEVEL
-#endif
-
-#define IRQ_DMA0_LEVEL 14
-#define IRQ_DMA1_LEVEL 14
-#define IRQ_DMA2_LEVEL 14
-#define IRQ_DMA3_LEVEL 14
-#define IRQ_DMA4_LEVEL 14
-#define IRQ_DMA5_LEVEL 14
-#define IRQ_DMA6_LEVEL 14
-#define IRQ_DMA7_LEVEL 14
-
-#define IRQ_TIMER0_LEVEL 12
-#define IRQ_TIMER1_LEVEL 11
-#define IRQ_TIMER2_LEVEL 10
-
-#define IRQ_XIRQ0_LEVEL 1
-#define IRQ_XIRQ1_LEVEL 2
-#define IRQ_XIRQ2_LEVEL 3
-#define IRQ_XIRQ3_LEVEL 4
-#define IRQ_XIRQ4_LEVEL 5
-#define IRQ_XIRQ5_LEVEL 6
-#define IRQ_XIRQ6_LEVEL 7
-#define IRQ_XIRQ7_LEVEL 8
-
-/* IRQ IDs presented to drivers */
-#define IRQ_CPU__UNUSED IRQ_BASE_CPU
-#define IRQ_CPU_UART0 (IRQ_BASE_CPU + IRQ_UART0_LEVEL)
-#define IRQ_CPU_UART1 (IRQ_BASE_CPU + IRQ_UART1_LEVEL)
-#define IRQ_CPU_TIMER0 (IRQ_BASE_CPU + IRQ_TIMER0_LEVEL)
-#define IRQ_CPU_TIMER1 (IRQ_BASE_CPU + IRQ_TIMER1_LEVEL)
-#define IRQ_CPU_TIMER2 (IRQ_BASE_CPU + IRQ_TIMER2_LEVEL)
-#define IRQ_CPU_DMA0 (IRQ_BASE_CPU + IRQ_DMA0_LEVEL)
-#define IRQ_CPU_DMA1 (IRQ_BASE_CPU + IRQ_DMA1_LEVEL)
-#define IRQ_CPU_DMA2 (IRQ_BASE_CPU + IRQ_DMA2_LEVEL)
-#define IRQ_CPU_DMA3 (IRQ_BASE_CPU + IRQ_DMA3_LEVEL)
-#define IRQ_CPU_DMA4 (IRQ_BASE_CPU + IRQ_DMA4_LEVEL)
-#define IRQ_CPU_DMA5 (IRQ_BASE_CPU + IRQ_DMA5_LEVEL)
-#define IRQ_CPU_DMA6 (IRQ_BASE_CPU + IRQ_DMA6_LEVEL)
-#define IRQ_CPU_DMA7 (IRQ_BASE_CPU + IRQ_DMA7_LEVEL)
-#define IRQ_CPU_EXTERNAL0 (IRQ_BASE_CPU + IRQ_XIRQ0_LEVEL)
-#define IRQ_CPU_EXTERNAL1 (IRQ_BASE_CPU + IRQ_XIRQ1_LEVEL)
-#define IRQ_CPU_EXTERNAL2 (IRQ_BASE_CPU + IRQ_XIRQ2_LEVEL)
-#define IRQ_CPU_EXTERNAL3 (IRQ_BASE_CPU + IRQ_XIRQ3_LEVEL)
-#define IRQ_CPU_EXTERNAL4 (IRQ_BASE_CPU + IRQ_XIRQ4_LEVEL)
-#define IRQ_CPU_EXTERNAL5 (IRQ_BASE_CPU + IRQ_XIRQ5_LEVEL)
-#define IRQ_CPU_EXTERNAL6 (IRQ_BASE_CPU + IRQ_XIRQ6_LEVEL)
-#define IRQ_CPU_EXTERNAL7 (IRQ_BASE_CPU + IRQ_XIRQ7_LEVEL)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_CPU_IRQS_H */
diff --git a/arch/frv/include/asm/current.h b/arch/frv/include/asm/current.h
deleted file mode 100644
index 86b027491b08..000000000000
--- a/arch/frv/include/asm/current.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* current.h: FRV current task pointer
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_CURRENT_H
-#define _ASM_CURRENT_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * dedicate GR29 to keeping the current task pointer
- */
-register struct task_struct *current asm("gr29");
-
-#define get_current() current
-
-#else
-
-#define CURRENT gr29
-
-#endif
-
-#endif /* _ASM_CURRENT_H */
diff --git a/arch/frv/include/asm/delay.h b/arch/frv/include/asm/delay.h
deleted file mode 100644
index 597b4ebf03b4..000000000000
--- a/arch/frv/include/asm/delay.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* delay.h: FRV delay code
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_DELAY_H
-#define _ASM_DELAY_H
-
-#include <asm/param.h>
-#include <asm/timer-regs.h>
-
-/*
- * delay loop - runs at __core_clock_speed_HZ / 2 [there are 2 insns in the loop]
- */
-extern unsigned long __delay_loops_MHz;
-
-static inline void __delay(unsigned long loops)
-{
- asm volatile("1: subicc %0,#1,%0,icc0 \n"
- " bnc icc0,#2,1b \n"
- : "=r" (loops)
- : "0" (loops)
- : "icc0"
- );
-}
-
-/*
- * Use only for very small delays ( < 1 msec). Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays. This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-
-extern unsigned long loops_per_jiffy;
-
-static inline void udelay(unsigned long usecs)
-{
- __delay(usecs * __delay_loops_MHz);
-}
-
-#define ndelay(n) udelay((n) * 5)
-
-#endif /* _ASM_DELAY_H */
diff --git a/arch/frv/include/asm/div64.h b/arch/frv/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/frv/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/frv/include/asm/dm9000.h b/arch/frv/include/asm/dm9000.h
deleted file mode 100644
index f6f48fd9ec6e..000000000000
--- a/arch/frv/include/asm/dm9000.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* dm9000.h: Davicom DM9000 adapter configuration
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_DM9000_H
-#define _ASM_DM9000_H
-
-#include <asm/mb-regs.h>
-
-#define DM9000_ARCH_IOBASE (__region_CS6 + 0x300)
-#define DM9000_ARCH_IRQ IRQ_CPU_EXTERNAL3 /* XIRQ #3 (shared with FPGA) */
-#undef DM9000_ARCH_IRQ_ACTLOW /* IRQ pin active high */
-#define DM9000_ARCH_BUS_INFO "CS6#+0x300" /* bus info for ethtool */
-
-#undef __is_PCI_IO
-#define __is_PCI_IO(addr) 0 /* not PCI */
-
-#undef inl
-#define inl(addr) \
-({ \
- unsigned long __ioaddr = (unsigned long) addr; \
- uint32_t x = readl(__ioaddr); \
- ((x & 0xff) << 24) | ((x & 0xff00) << 8) | ((x >> 8) & 0xff00) | ((x >> 24) & 0xff); \
-})
-
-#undef insl
-#define insl(a,b,l) __insl(a,b,l,0) /* don't byte-swap */
-
-
-#endif /* _ASM_DM9000_H */
diff --git a/arch/frv/include/asm/dma-mapping.h b/arch/frv/include/asm/dma-mapping.h
deleted file mode 100644
index fd80e840a1e6..000000000000
--- a/arch/frv/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_DMA_MAPPING_H
-#define _ASM_DMA_MAPPING_H
-
-#include <asm/cache.h>
-#include <asm/cacheflush.h>
-
-extern unsigned long __nongprelbss dma_coherent_mem_start;
-extern unsigned long __nongprelbss dma_coherent_mem_end;
-
-extern const struct dma_map_ops frv_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &frv_dma_ops;
-}
-
-#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/frv/include/asm/dma.h b/arch/frv/include/asm/dma.h
deleted file mode 100644
index 683c47d48a5b..000000000000
--- a/arch/frv/include/asm/dma.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* dma.h: FRV DMA controller management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-//#define DMA_DEBUG 1
-
-#include <linux/interrupt.h>
-
-#undef MAX_DMA_CHANNELS /* don't use kernel/dma.c */
-
-/* under 2.4 this is actually needed by the new bootmem allocator */
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/*
- * FRV DMA controller management
- */
-typedef irqreturn_t (*dma_irq_handler_t)(int dmachan, unsigned long cstr, void *data);
-
-extern void frv_dma_init(void);
-
-extern int frv_dma_open(const char *devname,
- unsigned long dmamask,
- int dmacap,
- dma_irq_handler_t handler,
- unsigned long irq_flags,
- void *data);
-
-/* channels required */
-#define FRV_DMA_MASK_ANY ULONG_MAX /* any channel */
-
-/* capabilities required */
-#define FRV_DMA_CAP_DREQ 0x01 /* DMA request pin */
-#define FRV_DMA_CAP_DACK 0x02 /* DMA ACK pin */
-#define FRV_DMA_CAP_DONE 0x04 /* DMA done pin */
-
-extern void frv_dma_close(int dma);
-
-extern void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr);
-
-extern void frv_dma_start(int dma,
- unsigned long sba, unsigned long dba,
- unsigned long pix, unsigned long six, unsigned long bcl);
-
-extern void frv_dma_restart_circular(int dma, unsigned long six);
-
-extern void frv_dma_stop(int dma);
-
-extern int is_frv_dma_interrupting(int dma);
-
-extern void frv_dma_dump(int dma);
-
-extern void frv_dma_status_clear(int dma);
-
-#define FRV_DMA_NCHANS 8
-#define FRV_DMA_4CHANS 4
-#define FRV_DMA_8CHANS 8
-
-#define DMAC_CCFRx 0x00 /* channel configuration reg */
-#define DMAC_CCFRx_CM_SHIFT 16
-#define DMAC_CCFRx_CM_DA 0x00000000
-#define DMAC_CCFRx_CM_SCA 0x00010000
-#define DMAC_CCFRx_CM_DCA 0x00020000
-#define DMAC_CCFRx_CM_2D 0x00030000
-#define DMAC_CCFRx_ATS_SHIFT 8
-#define DMAC_CCFRx_RS_INTERN 0x00000000
-#define DMAC_CCFRx_RS_EXTERN 0x00000001
-#define DMAC_CCFRx_RS_SHIFT 0
-
-#define DMAC_CSTRx 0x08 /* channel status reg */
-#define DMAC_CSTRx_FS 0x0000003f
-#define DMAC_CSTRx_NE 0x00000100
-#define DMAC_CSTRx_FED 0x00000200
-#define DMAC_CSTRx_WER 0x00000800
-#define DMAC_CSTRx_RER 0x00001000
-#define DMAC_CSTRx_CE 0x00002000
-#define DMAC_CSTRx_INT 0x00800000
-#define DMAC_CSTRx_BUSY 0x80000000
-
-#define DMAC_CCTRx 0x10 /* channel control reg */
-#define DMAC_CCTRx_DSIZ_1 0x00000000
-#define DMAC_CCTRx_DSIZ_2 0x00000001
-#define DMAC_CCTRx_DSIZ_4 0x00000002
-#define DMAC_CCTRx_DSIZ_32 0x00000005
-#define DMAC_CCTRx_DAU_HOLD 0x00000000
-#define DMAC_CCTRx_DAU_INC 0x00000010
-#define DMAC_CCTRx_DAU_DEC 0x00000020
-#define DMAC_CCTRx_SSIZ_1 0x00000000
-#define DMAC_CCTRx_SSIZ_2 0x00000100
-#define DMAC_CCTRx_SSIZ_4 0x00000200
-#define DMAC_CCTRx_SSIZ_32 0x00000500
-#define DMAC_CCTRx_SAU_HOLD 0x00000000
-#define DMAC_CCTRx_SAU_INC 0x00001000
-#define DMAC_CCTRx_SAU_DEC 0x00002000
-#define DMAC_CCTRx_FC 0x08000000
-#define DMAC_CCTRx_ICE 0x10000000
-#define DMAC_CCTRx_IE 0x40000000
-#define DMAC_CCTRx_ACT 0x80000000
-
-#define DMAC_SBAx 0x18 /* source base address reg */
-#define DMAC_DBAx 0x20 /* data base address reg */
-#define DMAC_PIXx 0x28 /* primary index reg */
-#define DMAC_SIXx 0x30 /* secondary index reg */
-#define DMAC_BCLx 0x38 /* byte count limit reg */
-#define DMAC_APRx 0x40 /* alternate pointer reg */
-
-/*
- * required for PCI + MODULES
- */
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/arch/frv/include/asm/elf.h b/arch/frv/include/asm/elf.h
deleted file mode 100644
index 2bac6446db41..000000000000
--- a/arch/frv/include/asm/elf.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* elf.h: FR-V ELF definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-m68knommu/elf.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_ELF_H
-#define __ASM_ELF_H
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-struct elf32_hdr;
-
-/*
- * ELF header e_flags defines.
- */
-#define EF_FRV_GPR_MASK 0x00000003 /* mask for # of gprs */
-#define EF_FRV_GPR32 0x00000001 /* Only uses GR on 32-register */
-#define EF_FRV_GPR64 0x00000002 /* Only uses GR on 64-register */
-#define EF_FRV_FPR_MASK 0x0000000c /* mask for # of fprs */
-#define EF_FRV_FPR32 0x00000004 /* Only uses FR on 32-register */
-#define EF_FRV_FPR64 0x00000008 /* Only uses FR on 64-register */
-#define EF_FRV_FPR_NONE 0x0000000C /* Uses software floating-point */
-#define EF_FRV_DWORD_MASK 0x00000030 /* mask for dword support */
-#define EF_FRV_DWORD_YES 0x00000010 /* Assumes stack aligned to 8-byte boundaries. */
-#define EF_FRV_DWORD_NO 0x00000020 /* Assumes stack aligned to 4-byte boundaries. */
-#define EF_FRV_DOUBLE 0x00000040 /* Uses double instructions. */
-#define EF_FRV_MEDIA 0x00000080 /* Uses media instructions. */
-#define EF_FRV_PIC 0x00000100 /* Uses position independent code. */
-#define EF_FRV_NON_PIC_RELOCS 0x00000200 /* Does not use position Independent code. */
-#define EF_FRV_MULADD 0x00000400 /* -mmuladd */
-#define EF_FRV_BIGPIC 0x00000800 /* -fPIC */
-#define EF_FRV_LIBPIC 0x00001000 /* -mlibrary-pic */
-#define EF_FRV_G0 0x00002000 /* -G 0, no small data ptr */
-#define EF_FRV_NOPACK 0x00004000 /* -mnopack */
-#define EF_FRV_FDPIC 0x00008000 /* -mfdpic */
-#define EF_FRV_CPU_MASK 0xff000000 /* specific cpu bits */
-#define EF_FRV_CPU_GENERIC 0x00000000 /* Set CPU type is FR-V */
-#define EF_FRV_CPU_FR500 0x01000000 /* Set CPU type is FR500 */
-#define EF_FRV_CPU_FR300 0x02000000 /* Set CPU type is FR300 */
-#define EF_FRV_CPU_SIMPLE 0x03000000 /* SIMPLE */
-#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */
-#define EF_FRV_CPU_FR400 0x05000000 /* Set CPU type is FR400 */
-#define EF_FRV_CPU_FR550 0x06000000 /* Set CPU type is FR550 */
-#define EF_FRV_CPU_FR405 0x07000000 /* Set CPU type is FR405 */
-#define EF_FRV_CPU_FR450 0x08000000 /* Set CPU type is FR450 */
-
-/*
- * FR-V ELF relocation types
- */
-
-
-/*
- * ELF register definitions..
- */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_fpmedia_regs elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-extern int elf_check_arch(const struct elf32_hdr *hdr);
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_FRV_FDPIC && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS))
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_FRV_PIC)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2MSB
-#define ELF_ARCH EM_FRV
-
-#define ELF_PLAT_INIT(_r) \
-do { \
- __kernel_frame0_ptr->gr16 = 0; \
- __kernel_frame0_ptr->gr17 = 0; \
- __kernel_frame0_ptr->gr18 = 0; \
- __kernel_frame0_ptr->gr19 = 0; \
- __kernel_frame0_ptr->gr20 = 0; \
- __kernel_frame0_ptr->gr21 = 0; \
- __kernel_frame0_ptr->gr22 = 0; \
- __kernel_frame0_ptr->gr23 = 0; \
- __kernel_frame0_ptr->gr24 = 0; \
- __kernel_frame0_ptr->gr25 = 0; \
- __kernel_frame0_ptr->gr26 = 0; \
- __kernel_frame0_ptr->gr27 = 0; \
- __kernel_frame0_ptr->gr29 = 0; \
-} while(0)
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr) \
-do { \
- __kernel_frame0_ptr->gr16 = _exec_map_addr; \
- __kernel_frame0_ptr->gr17 = _interp_map_addr; \
- __kernel_frame0_ptr->gr18 = _dynamic_addr; \
- __kernel_frame0_ptr->gr19 = 0; \
- __kernel_frame0_ptr->gr20 = 0; \
- __kernel_frame0_ptr->gr21 = 0; \
- __kernel_frame0_ptr->gr22 = 0; \
- __kernel_frame0_ptr->gr23 = 0; \
- __kernel_frame0_ptr->gr24 = 0; \
- __kernel_frame0_ptr->gr25 = 0; \
- __kernel_frame0_ptr->gr26 = 0; \
- __kernel_frame0_ptr->gr27 = 0; \
- __kernel_frame0_ptr->gr29 = 0; \
-} while(0)
-
-#define CORE_DUMP_USE_REGSET
-#define ELF_FDPIC_CORE_EFLAGS EF_FRV_FDPIC
-#define ELF_EXEC_PAGESIZE 16384
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0x08000000UL
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#endif
diff --git a/arch/frv/include/asm/emergency-restart.h b/arch/frv/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/arch/frv/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/frv/include/asm/fpu.h b/arch/frv/include/asm/fpu.h
deleted file mode 100644
index 2f0929333f91..000000000000
--- a/arch/frv/include/asm/fpu.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_FPU_H
-#define __ASM_FPU_H
-
-
-/*
- * MAX floating point unit state size (FSAVE/FRESTORE)
- */
-
-#define kernel_fpu_end() do { asm volatile("bar":::"memory"); preempt_enable(); } while(0)
-
-#endif /* __ASM_FPU_H */
diff --git a/arch/frv/include/asm/ftrace.h b/arch/frv/include/asm/ftrace.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/frv/include/asm/ftrace.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/frv/include/asm/futex.h b/arch/frv/include/asm/futex.h
deleted file mode 100644
index dfcc3484231d..000000000000
--- a/arch/frv/include/asm/futex.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#ifdef __KERNEL__
-
-#include <linux/futex.h>
-#include <asm/errno.h>
-#include <linux/uaccess.h>
-
-extern int arch_futex_atomic_op_inuser(int op, int oparg, int *oval,
- u32 __user *uaddr);
-
-static inline int
-futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
- u32 oldval, u32 newval)
-{
- return -ENOSYS;
-}
-
-#endif
-#endif
diff --git a/arch/frv/include/asm/gdb-stub.h b/arch/frv/include/asm/gdb-stub.h
deleted file mode 100644
index e6bedd0cd9a5..000000000000
--- a/arch/frv/include/asm/gdb-stub.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* gdb-stub.h: FRV GDB stub
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_GDB_STUB_H
-#define __ASM_GDB_STUB_H
-
-#undef GDBSTUB_DEBUG_IO
-#undef GDBSTUB_DEBUG_PROTOCOL
-
-#include <asm/ptrace.h>
-
-/*
- * important register numbers in GDB protocol
- * - GR0, GR1, GR2, GR3, GR4, GR5, GR6, GR7,
- * - GR8, GR9, GR10, GR11, GR12, GR13, GR14, GR15,
- * - GR16, GR17, GR18, GR19, GR20, GR21, GR22, GR23,
- * - GR24, GR25, GR26, GR27, GR28, GR29, GR30, GR31,
- * - GR32, GR33, GR34, GR35, GR36, GR37, GR38, GR39,
- * - GR40, GR41, GR42, GR43, GR44, GR45, GR46, GR47,
- * - GR48, GR49, GR50, GR51, GR52, GR53, GR54, GR55,
- * - GR56, GR57, GR58, GR59, GR60, GR61, GR62, GR63,
- * - FR0, FR1, FR2, FR3, FR4, FR5, FR6, FR7,
- * - FR8, FR9, FR10, FR11, FR12, FR13, FR14, FR15,
- * - FR16, FR17, FR18, FR19, FR20, FR21, FR22, FR23,
- * - FR24, FR25, FR26, FR27, FR28, FR29, FR30, FR31,
- * - FR32, FR33, FR34, FR35, FR36, FR37, FR38, FR39,
- * - FR40, FR41, FR42, FR43, FR44, FR45, FR46, FR47,
- * - FR48, FR49, FR50, FR51, FR52, FR53, FR54, FR55,
- * - FR56, FR57, FR58, FR59, FR60, FR61, FR62, FR63,
- * - PC, PSR, CCR, CCCR,
- * - _X132, _X133, _X134
- * - TBR, BRR, DBAR0, DBAR1, DBAR2, DBAR3,
- * - SCR0, SCR1, SCR2, SCR3,
- * - LR, LCR,
- * - IACC0H, IACC0L,
- * - FSR0,
- * - ACC0, ACC1, ACC2, ACC3, ACC4, ACC5, ACC6, ACC7,
- * - ACCG0123, ACCG4567,
- * - MSR0, MSR1,
- * - GNER0, GNER1,
- * - FNER0, FNER1,
- */
-#define GDB_REG_GR(N) (N)
-#define GDB_REG_FR(N) (64+(N))
-#define GDB_REG_PC 128
-#define GDB_REG_PSR 129
-#define GDB_REG_CCR 130
-#define GDB_REG_CCCR 131
-#define GDB_REG_TBR 135
-#define GDB_REG_BRR 136
-#define GDB_REG_DBAR(N) (137+(N))
-#define GDB_REG_SCR(N) (141+(N))
-#define GDB_REG_LR 145
-#define GDB_REG_LCR 146
-#define GDB_REG_FSR0 149
-#define GDB_REG_ACC(N) (150+(N))
-#define GDB_REG_ACCG(N) (158+(N)/4)
-#define GDB_REG_MSR(N) (160+(N))
-#define GDB_REG_GNER(N) (162+(N))
-#define GDB_REG_FNER(N) (164+(N))
-
-#define GDB_REG_SP GDB_REG_GR(1)
-#define GDB_REG_FP GDB_REG_GR(2)
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-/*
- * Prototypes
- */
-extern void show_registers_only(struct pt_regs *regs);
-
-extern void gdbstub_init(void);
-extern void gdbstub(int type);
-extern void gdbstub_exit(int status);
-
-extern void gdbstub_io_init(void);
-extern void gdbstub_set_baud(unsigned baud);
-extern int gdbstub_rx_char(unsigned char *_ch, int nonblock);
-extern void gdbstub_tx_char(unsigned char ch);
-extern void gdbstub_tx_flush(void);
-extern void gdbstub_do_rx(void);
-
-extern asmlinkage void __debug_stub_init_break(void);
-extern asmlinkage void __break_hijack_kernel_event(void);
-extern asmlinkage void __break_hijack_kernel_event_breaks_here(void);
-
-extern asmlinkage void gdbstub_rx_handler(void);
-extern asmlinkage void gdbstub_rx_irq(void);
-extern asmlinkage void gdbstub_intercept(void);
-
-extern uint32_t __entry_usertrap_table[];
-extern uint32_t __entry_kerneltrap_table[];
-
-extern volatile u8 gdbstub_rx_buffer[PAGE_SIZE];
-extern volatile u32 gdbstub_rx_inp;
-extern volatile u32 gdbstub_rx_outp;
-extern volatile u8 gdbstub_rx_overflow;
-extern u8 gdbstub_rx_unget;
-
-extern void gdbstub_printk(const char *fmt, ...);
-extern void debug_to_serial(const char *p, int n);
-extern void console_set_baud(unsigned baud);
-
-#ifdef GDBSTUB_DEBUG_IO
-#define gdbstub_io(FMT,...) gdbstub_printk(FMT, ##__VA_ARGS__)
-#else
-#define gdbstub_io(FMT,...) ({ 0; })
-#endif
-
-#ifdef GDBSTUB_DEBUG_PROTOCOL
-#define gdbstub_proto(FMT,...) gdbstub_printk(FMT,##__VA_ARGS__)
-#else
-#define gdbstub_proto(FMT,...) ({ 0; })
-#endif
-
-/*
- * we dedicate GR31 to keeping a pointer to the gdbstub exception frame
- * - gr31 is destroyed on entry to the gdbstub if !MMU
- * - gr31 is saved in scr3 on entry to the gdbstub if in !MMU
- */
-register struct frv_frame0 *__debug_frame0 asm("gr31");
-
-#define __debug_frame (&__debug_frame0->regs)
-#define __debug_user_context (&__debug_frame0->uc)
-#define __debug_regs (&__debug_frame0->debug)
-#define __debug_reg(X) ((unsigned long *) ((unsigned long) &__debug_frame0 + (X)))
-
-struct frv_debug_status {
- unsigned long bpsr;
- unsigned long dcr;
- unsigned long brr;
- unsigned long nmar;
-};
-
-extern struct frv_debug_status __debug_status;
-
-#endif /* _LANGUAGE_ASSEMBLY */
-#endif /* __ASM_GDB_STUB_H */
diff --git a/arch/frv/include/asm/gpio-regs.h b/arch/frv/include/asm/gpio-regs.h
deleted file mode 100644
index 9edf5d5d4d3f..000000000000
--- a/arch/frv/include/asm/gpio-regs.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* gpio-regs.h: on-chip general purpose I/O registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_GPIO_REGS
-#define _ASM_GPIO_REGS
-
-#define __reg(ADDR) (*(volatile unsigned long *)(ADDR))
-
-#define __get_PDR() ({ __reg(0xfeff0400); })
-#define __set_PDR(V) do { __reg(0xfeff0400) = (V); mb(); } while(0)
-
-#define __get_GPDR() ({ __reg(0xfeff0408); })
-#define __set_GPDR(V) do { __reg(0xfeff0408) = (V); mb(); } while(0)
-
-#define __get_SIR() ({ __reg(0xfeff0410); })
-#define __set_SIR(V) do { __reg(0xfeff0410) = (V); mb(); } while(0)
-
-#define __get_SOR() ({ __reg(0xfeff0418); })
-#define __set_SOR(V) do { __reg(0xfeff0418) = (V); mb(); } while(0)
-
-#define __set_PDSR(V) do { __reg(0xfeff0420) = (V); mb(); } while(0)
-
-#define __set_PDCR(V) do { __reg(0xfeff0428) = (V); mb(); } while(0)
-
-#define __get_RSTR() ({ __reg(0xfeff0500); })
-#define __set_RSTR(V) do { __reg(0xfeff0500) = (V); mb(); } while(0)
-
-
-
-/* PDR definitions */
-#define PDR_GPIO_DATA(X) (1 << (X))
-
-/* GPDR definitions */
-#define GPDR_INPUT 0
-#define GPDR_OUTPUT 1
-#define GPDR_DREQ0_BIT 0x00001000
-#define GPDR_DREQ1_BIT 0x00008000
-#define GPDR_DREQ2_BIT 0x00040000
-#define GPDR_DREQ3_BIT 0x00080000
-#define GPDR_DREQ4_BIT 0x00004000
-#define GPDR_DREQ5_BIT 0x00020000
-#define GPDR_DREQ6_BIT 0x00100000
-#define GPDR_DREQ7_BIT 0x00200000
-#define GPDR_DACK0_BIT 0x00002000
-#define GPDR_DACK1_BIT 0x00010000
-#define GPDR_DACK2_BIT 0x00100000
-#define GPDR_DACK3_BIT 0x00200000
-#define GPDR_DONE0_BIT 0x00004000
-#define GPDR_DONE1_BIT 0x00020000
-#define GPDR_GPIO_DIR(X,D) ((D) << (X))
-
-/* SIR definitions */
-#define SIR_GPIO_INPUT 0
-#define SIR_DREQ7_INPUT 0x00200000
-#define SIR_DREQ6_INPUT 0x00100000
-#define SIR_DREQ3_INPUT 0x00080000
-#define SIR_DREQ2_INPUT 0x00040000
-#define SIR_DREQ5_INPUT 0x00020000
-#define SIR_DREQ1_INPUT 0x00008000
-#define SIR_DREQ4_INPUT 0x00004000
-#define SIR_DREQ0_INPUT 0x00001000
-#define SIR_RXD1_INPUT 0x00000400
-#define SIR_CTS0_INPUT 0x00000100
-#define SIR_RXD0_INPUT 0x00000040
-#define SIR_GATE1_INPUT 0x00000020
-#define SIR_GATE0_INPUT 0x00000010
-#define SIR_IRQ3_INPUT 0x00000008
-#define SIR_IRQ2_INPUT 0x00000004
-#define SIR_IRQ1_INPUT 0x00000002
-#define SIR_IRQ0_INPUT 0x00000001
-#define SIR_DREQ_BITS (SIR_DREQ0_INPUT | SIR_DREQ1_INPUT | \
- SIR_DREQ2_INPUT | SIR_DREQ3_INPUT | \
- SIR_DREQ4_INPUT | SIR_DREQ5_INPUT | \
- SIR_DREQ6_INPUT | SIR_DREQ7_INPUT)
-
-/* SOR definitions */
-#define SOR_GPIO_OUTPUT 0
-#define SOR_DACK3_OUTPUT 0x00200000
-#define SOR_DACK2_OUTPUT 0x00100000
-#define SOR_DONE1_OUTPUT 0x00020000
-#define SOR_DACK1_OUTPUT 0x00010000
-#define SOR_DONE0_OUTPUT 0x00004000
-#define SOR_DACK0_OUTPUT 0x00002000
-#define SOR_TXD1_OUTPUT 0x00000800
-#define SOR_RTS0_OUTPUT 0x00000200
-#define SOR_TXD0_OUTPUT 0x00000080
-#define SOR_TOUT1_OUTPUT 0x00000020
-#define SOR_TOUT0_OUTPUT 0x00000010
-#define SOR_DONE_BITS (SOR_DONE0_OUTPUT | SOR_DONE1_OUTPUT)
-#define SOR_DACK_BITS (SOR_DACK0_OUTPUT | SOR_DACK1_OUTPUT | \
- SOR_DACK2_OUTPUT | SOR_DACK3_OUTPUT)
-
-/* PDSR definitions */
-#define PDSR_UNCHANGED 0
-#define PDSR_SET_BIT(X) (1 << (X))
-
-/* PDCR definitions */
-#define PDCR_UNCHANGED 0
-#define PDCR_CLEAR_BIT(X) (1 << (X))
-
-/* RSTR definitions */
-/* Read Only */
-#define RSTR_POWERON 0x00000400
-#define RSTR_SOFTRESET_STATUS 0x00000100
-/* Write Only */
-#define RSTR_SOFTRESET 0x00000001
-
-#endif /* _ASM_GPIO_REGS */
diff --git a/arch/frv/include/asm/hardirq.h b/arch/frv/include/asm/hardirq.h
deleted file mode 100644
index c62833d6ebbb..000000000000
--- a/arch/frv/include/asm/hardirq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* hardirq.h: FRV hardware IRQ management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-
-#include <linux/atomic.h>
-
-extern atomic_t irq_err_count;
-static inline void ack_bad_irq(int irq)
-{
- atomic_inc(&irq_err_count);
-}
-#define ack_bad_irq ack_bad_irq
-
-#include <asm-generic/hardirq.h>
-
-#endif
diff --git a/arch/frv/include/asm/highmem.h b/arch/frv/include/asm/highmem.h
deleted file mode 100644
index 1f58938703ab..000000000000
--- a/arch/frv/include/asm/highmem.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* highmem.h: virtual kernel memory mappings for high memory
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-i386/highmem.h
- *
- * See Documentation/frv/mmu-layout.txt for more information.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/highmem.h>
-#include <asm/mem-layout.h>
-#include <asm/spr-regs.h>
-#include <asm/mb-regs.h>
-
-#define NR_TLB_LINES 64 /* number of lines in the TLB */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-#include <asm/kmap_types.h>
-#include <asm/pgtable.h>
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define HIGHMEM_DEBUG 1
-#else
-#define HIGHMEM_DEBUG 0
-#endif
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-#define kmap_prot PAGE_KERNEL
-#define kmap_pte ______kmap_pte_in_TLB
-extern pte_t *pkmap_page_table;
-
-#define flush_cache_kmaps() do { } while (0)
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-#define LAST_PKMAP PTRS_PER_PTE
-#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
-#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-extern void *kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-extern void *kmap(struct page *page);
-extern void kunmap(struct page *page);
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
- * gives a more generic (and caching) interface. But kmap_atomic can
- * be used in IRQ contexts, so in some (very limited) cases we need
- * it.
- */
-#define KMAP_ATOMIC_CACHE_DAMR 8
-
-#ifndef __ASSEMBLY__
-
-#define __kmap_atomic_primary(cached, paddr, ampr) \
-({ \
- unsigned long damlr, dampr; \
- \
- dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb | xAMPRx_V; \
- \
- if (!cached) \
- asm volatile("movgs %0,dampr"#ampr :: "r"(dampr) : "memory"); \
- else \
- /* cache flush page attachment point */ \
- asm volatile("movgs %0,iampr"#ampr"\n" \
- "movgs %0,dampr"#ampr"\n" \
- :: "r"(dampr) : "memory" \
- ); \
- \
- asm("movsg damlr"#ampr",%0" : "=r"(damlr)); \
- \
- /*printk("DAMR"#ampr": PRIM sl=%d L=%08lx P=%08lx\n", type, damlr, dampr);*/ \
- \
- (void *) damlr; \
-})
-
-#define __kmap_atomic_secondary(slot, paddr) \
-({ \
- unsigned long damlr = KMAP_ATOMIC_SECONDARY_FRAME + (slot) * PAGE_SIZE; \
- unsigned long dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb | xAMPRx_V; \
- \
- asm volatile("movgs %0,tplr \n" \
- "movgs %1,tppr \n" \
- "tlbpr %0,gr0,#2,#1" \
- : : "r"(damlr), "r"(dampr) : "memory"); \
- \
- /*printk("TLB: SECN sl=%d L=%08lx P=%08lx\n", slot, damlr, dampr);*/ \
- \
- (void *) damlr; \
-})
-
-static inline void *kmap_atomic_primary(struct page *page)
-{
- unsigned long paddr;
-
- pagefault_disable();
- paddr = page_to_phys(page);
-
- return __kmap_atomic_primary(1, paddr, 2);
-}
-
-#define __kunmap_atomic_primary(cached, ampr) \
-do { \
- asm volatile("movgs gr0,dampr"#ampr"\n" ::: "memory"); \
- if (cached) \
- asm volatile("movgs gr0,iampr"#ampr"\n" ::: "memory"); \
-} while(0)
-
-#define __kunmap_atomic_secondary(slot, vaddr) \
-do { \
- asm volatile("tlbpr %0,gr0,#4,#1" : : "r"(vaddr) : "memory"); \
-} while(0)
-
-static inline void kunmap_atomic_primary(void *kvaddr)
-{
- __kunmap_atomic_primary(1, 2);
- pagefault_enable();
-}
-
-void *kmap_atomic(struct page *page);
-void __kunmap_atomic(void *kvaddr);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/frv/include/asm/hw_irq.h b/arch/frv/include/asm/hw_irq.h
deleted file mode 100644
index 522ad37923d8..000000000000
--- a/arch/frv/include/asm/hw_irq.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* hw_irq.h: FR-V specific h/w IRQ stuff
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
-
-
-#endif /* _ASM_HW_IRQ_H */
diff --git a/arch/frv/include/asm/io.h b/arch/frv/include/asm/io.h
deleted file mode 100644
index 8062fc73fad0..000000000000
--- a/arch/frv/include/asm/io.h
+++ /dev/null
@@ -1,414 +0,0 @@
-/* io.h: FRV I/O operations
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * This gets interesting when talking to the PCI bus - the CPU is in big endian
- * mode, the PCI bus is little endian and the hardware in the middle can do
- * byte swapping
- */
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#ifdef __KERNEL__
-
-#define ARCH_HAS_IOREMAP_WT
-
-#include <linux/types.h>
-#include <asm/virtconvert.h>
-#include <asm/string.h>
-#include <asm/mb-regs.h>
-#include <asm-generic/pci_iomap.h>
-#include <linux/delay.h>
-
-/*
- * swap functions are sometimes needed to interface little-endian hardware
- */
-
-static inline unsigned short _swapw(unsigned short v)
-{
- return ((v << 8) | (v >> 8));
-}
-
-static inline unsigned long _swapl(unsigned long v)
-{
- return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24));
-}
-
-//#define __iormb() asm volatile("membar")
-//#define __iowmb() asm volatile("membar")
-
-static inline u8 __raw_readb(const volatile void __iomem *addr)
-{
- return __builtin_read8((volatile void __iomem *)addr);
-}
-
-static inline u16 __raw_readw(const volatile void __iomem *addr)
-{
- return __builtin_read16((volatile void __iomem *)addr);
-}
-
-static inline u32 __raw_readl(const volatile void __iomem *addr)
-{
- return __builtin_read32((volatile void __iomem *)addr);
-}
-
-#define __raw_writeb(datum, addr) __builtin_write8(addr, datum)
-#define __raw_writew(datum, addr) __builtin_write16(addr, datum)
-#define __raw_writel(datum, addr) __builtin_write32(addr, datum)
-
-static inline void io_outsb(unsigned int addr, const void *buf, int len)
-{
- unsigned long __ioaddr = (unsigned long) addr;
- const uint8_t *bp = buf;
-
- while (len--)
- __builtin_write8((volatile void __iomem *) __ioaddr, *bp++);
-}
-
-static inline void io_outsw(unsigned int addr, const void *buf, int len)
-{
- unsigned long __ioaddr = (unsigned long) addr;
- const uint16_t *bp = buf;
-
- while (len--)
- __builtin_write16((volatile void __iomem *) __ioaddr, (*bp++));
-}
-
-extern void __outsl_ns(unsigned int addr, const void *buf, int len);
-extern void __outsl_sw(unsigned int addr, const void *buf, int len);
-static inline void __outsl(unsigned int addr, const void *buf, int len, int swap)
-{
- unsigned long __ioaddr = (unsigned long) addr;
-
- if (!swap)
- __outsl_ns(__ioaddr, buf, len);
- else
- __outsl_sw(__ioaddr, buf, len);
-}
-
-static inline void io_insb(unsigned long addr, void *buf, int len)
-{
- uint8_t *bp = buf;
-
- while (len--)
- *bp++ = __builtin_read8((volatile void __iomem *) addr);
-}
-
-static inline void io_insw(unsigned long addr, void *buf, int len)
-{
- uint16_t *bp = buf;
-
- while (len--)
- *bp++ = __builtin_read16((volatile void __iomem *) addr);
-}
-
-extern void __insl_ns(unsigned long addr, void *buf, int len);
-extern void __insl_sw(unsigned long addr, void *buf, int len);
-static inline void __insl(unsigned long addr, void *buf, int len, int swap)
-{
- if (!swap)
- __insl_ns(addr, buf, len);
- else
- __insl_sw(addr, buf, len);
-}
-
-#define mmiowb() mb()
-
-/*
- * make the short names macros so specific devices
- * can override them as required
- */
-
-static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
- memset((void __force *) addr, val, count);
-}
-
-static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
-{
- memcpy(dst, (void __force *) src, count);
-}
-
-static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
- memcpy((void __force *) dst, src, count);
-}
-
-static inline uint8_t inb(unsigned long addr)
-{
- return __builtin_read8((void __iomem *)addr);
-}
-
-static inline uint16_t inw(unsigned long addr)
-{
- uint16_t ret = __builtin_read16((void __iomem *)addr);
-
- if (__is_PCI_IO(addr))
- ret = _swapw(ret);
-
- return ret;
-}
-
-static inline uint32_t inl(unsigned long addr)
-{
- uint32_t ret = __builtin_read32((void __iomem *)addr);
-
- if (__is_PCI_IO(addr))
- ret = _swapl(ret);
-
- return ret;
-}
-
-static inline void outb(uint8_t datum, unsigned long addr)
-{
- __builtin_write8((void __iomem *)addr, datum);
-}
-
-static inline void outw(uint16_t datum, unsigned long addr)
-{
- if (__is_PCI_IO(addr))
- datum = _swapw(datum);
- __builtin_write16((void __iomem *)addr, datum);
-}
-
-static inline void outl(uint32_t datum, unsigned long addr)
-{
- if (__is_PCI_IO(addr))
- datum = _swapl(datum);
- __builtin_write32((void __iomem *)addr, datum);
-}
-
-#define inb_p(addr) inb(addr)
-#define inw_p(addr) inw(addr)
-#define inl_p(addr) inl(addr)
-#define outb_p(x,addr) outb(x,addr)
-#define outw_p(x,addr) outw(x,addr)
-#define outl_p(x,addr) outl(x,addr)
-
-#define outsb(a,b,l) io_outsb(a,b,l)
-#define outsw(a,b,l) io_outsw(a,b,l)
-#define outsl(a,b,l) __outsl(a,b,l,0)
-
-#define insb(a,b,l) io_insb(a,b,l)
-#define insw(a,b,l) io_insw(a,b,l)
-#define insl(a,b,l) __insl(a,b,l,0)
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-static inline uint8_t readb(const volatile void __iomem *addr)
-{
- return __builtin_read8((__force void volatile __iomem *) addr);
-}
-
-static inline uint16_t readw(const volatile void __iomem *addr)
-{
- uint16_t ret = __builtin_read16((__force void volatile __iomem *)addr);
-
- if (__is_PCI_MEM(addr))
- ret = _swapw(ret);
- return ret;
-}
-
-static inline uint32_t readl(const volatile void __iomem *addr)
-{
- uint32_t ret = __builtin_read32((__force void volatile __iomem *)addr);
-
- if (__is_PCI_MEM(addr))
- ret = _swapl(ret);
-
- return ret;
-}
-
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
-
-static inline void writeb(uint8_t datum, volatile void __iomem *addr)
-{
- __builtin_write8(addr, datum);
- if (__is_PCI_MEM(addr))
- __flush_PCI_writes();
-}
-
-static inline void writew(uint16_t datum, volatile void __iomem *addr)
-{
- if (__is_PCI_MEM(addr))
- datum = _swapw(datum);
-
- __builtin_write16(addr, datum);
- if (__is_PCI_MEM(addr))
- __flush_PCI_writes();
-}
-
-static inline void writel(uint32_t datum, volatile void __iomem *addr)
-{
- if (__is_PCI_MEM(addr))
- datum = _swapl(datum);
-
- __builtin_write32(addr, datum);
- if (__is_PCI_MEM(addr))
- __flush_PCI_writes();
-}
-
-#define writeb_relaxed writeb
-#define writew_relaxed writew
-#define writel_relaxed writel
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_FULL_CACHING 0
-#define IOMAP_NOCACHE_SER 1
-#define IOMAP_NOCACHE_NONSER 2
-#define IOMAP_WRITETHROUGH 3
-
-extern void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
-
-static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-
-static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-
-static inline void __iomem *ioremap_wt(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
-}
-
-static inline void __iomem *ioremap_fullcache(unsigned long physaddr, unsigned long size)
-{
- return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
-}
-
-#define ioremap_wc ioremap_nocache
-#define ioremap_uc ioremap_nocache
-
-extern void iounmap(void volatile __iomem *addr);
-
-static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
-{
- return (void __iomem *) port;
-}
-
-static inline void ioport_unmap(void __iomem *p)
-{
-}
-
-static inline void flush_write_buffers(void)
-{
- __asm__ __volatile__ ("membar" : : :"memory");
-}
-
-/*
- * do appropriate I/O accesses for token type
- */
-static inline unsigned int ioread8(void __iomem *p)
-{
- return __builtin_read8(p);
-}
-
-static inline unsigned int ioread16(void __iomem *p)
-{
- uint16_t ret = __builtin_read16(p);
- if (__is_PCI_addr(p))
- ret = _swapw(ret);
- return ret;
-}
-
-static inline unsigned int ioread32(void __iomem *p)
-{
- uint32_t ret = __builtin_read32(p);
- if (__is_PCI_addr(p))
- ret = _swapl(ret);
- return ret;
-}
-
-static inline void iowrite8(u8 val, void __iomem *p)
-{
- __builtin_write8(p, val);
- if (__is_PCI_MEM(p))
- __flush_PCI_writes();
-}
-
-static inline void iowrite16(u16 val, void __iomem *p)
-{
- if (__is_PCI_addr(p))
- val = _swapw(val);
- __builtin_write16(p, val);
- if (__is_PCI_MEM(p))
- __flush_PCI_writes();
-}
-
-static inline void iowrite32(u32 val, void __iomem *p)
-{
- if (__is_PCI_addr(p))
- val = _swapl(val);
- __builtin_write32(p, val);
- if (__is_PCI_MEM(p))
- __flush_PCI_writes();
-}
-
-#define ioread16be(addr) be16_to_cpu(ioread16(addr))
-#define ioread32be(addr) be32_to_cpu(ioread32(addr))
-#define iowrite16be(v, addr) iowrite16(cpu_to_be16(v), (addr))
-#define iowrite32be(v, addr) iowrite32(cpu_to_be32(v), (addr))
-
-static inline void ioread8_rep(void __iomem *p, void *dst, unsigned long count)
-{
- io_insb((unsigned long) p, dst, count);
-}
-
-static inline void ioread16_rep(void __iomem *p, void *dst, unsigned long count)
-{
- io_insw((unsigned long) p, dst, count);
-}
-
-static inline void ioread32_rep(void __iomem *p, void *dst, unsigned long count)
-{
- __insl_ns((unsigned long) p, dst, count);
-}
-
-static inline void iowrite8_rep(void __iomem *p, const void *src, unsigned long count)
-{
- io_outsb((unsigned long) p, src, count);
-}
-
-static inline void iowrite16_rep(void __iomem *p, const void *src, unsigned long count)
-{
- io_outsw((unsigned long) p, src, count);
-}
-
-static inline void iowrite32_rep(void __iomem *p, const void *src, unsigned long count)
-{
- __outsl_ns((unsigned long) p, src, count);
-}
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
-{
-}
-
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IO_H */
diff --git a/arch/frv/include/asm/irc-regs.h b/arch/frv/include/asm/irc-regs.h
deleted file mode 100644
index afa30aeacc82..000000000000
--- a/arch/frv/include/asm/irc-regs.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* irc-regs.h: on-chip interrupt controller registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRC_REGS
-#define _ASM_IRC_REGS
-
-#define __reg(ADDR) (*(volatile unsigned long *)(ADDR))
-
-#define __get_TM0() ({ __reg(0xfeff9800); })
-#define __get_TM1() ({ __reg(0xfeff9808); })
-#define __set_TM1(V) do { __reg(0xfeff9808) = (V); mb(); } while(0)
-
-#define __set_TM1x(XI,V) \
-do { \
- int shift = (XI) * 2 + 16; \
- unsigned long tm1 = __reg(0xfeff9808); \
- tm1 &= ~(0x3 << shift); \
- tm1 |= (V) << shift; \
- __reg(0xfeff9808) = tm1; \
- mb(); \
-} while(0)
-
-#define __get_RS(C) ({ (__reg(0xfeff9810) >> ((C)+16)) & 1; })
-
-#define __clr_RC(C) do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0)
-
-#define __get_MASK(C) ({ (__reg(0xfeff9820) >> ((C)+16)) & 1; })
-#define __set_MASK(C) do { __reg(0xfeff9820) |= 1 << ((C)+16); mb(); } while(0)
-#define __clr_MASK(C) do { __reg(0xfeff9820) &= ~(1 << ((C)+16)); mb(); } while(0)
-
-#define __get_MASK_all() __get_MASK(0)
-#define __set_MASK_all() __set_MASK(0)
-#define __clr_MASK_all() __clr_MASK(0)
-
-#define __get_IRL() ({ (__reg(0xfeff9828) >> 16) & 0xf; })
-#define __clr_IRL() do { __reg(0xfeff9828) = 0x100000; mb(); } while(0)
-
-#define __get_IRR(N) ({ __reg(0xfeff9840 + (N) * 8); })
-#define __set_IRR(N,V) do { __reg(0xfeff9840 + (N) * 8) = (V); } while(0)
-
-#define __get_IITMR(N) ({ __reg(0xfeff9880 + (N) * 8); })
-#define __set_IITMR(N,V) do { __reg(0xfeff9880 + (N) * 8) = (V); } while(0)
-
-
-#endif /* _ASM_IRC_REGS */
diff --git a/arch/frv/include/asm/irq.h b/arch/frv/include/asm/irq.h
deleted file mode 100644
index 3a66ebd754bd..000000000000
--- a/arch/frv/include/asm/irq.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* irq.h: FRV IRQ definitions
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRQ_H_
-#define _ASM_IRQ_H_
-
-#define NR_IRQS 48
-#define IRQ_BASE_CPU (0 * 16)
-#define IRQ_BASE_FPGA (1 * 16)
-#define IRQ_BASE_MB93493 (2 * 16)
-
-/* probe returns a 32-bit IRQ mask:-/ */
-#define MIN_PROBE_IRQ (NR_IRQS - 32)
-
-#ifndef __ASSEMBLY__
-static inline int irq_canonicalize(int irq)
-{
- return irq;
-}
-#endif
-
-#endif /* _ASM_IRQ_H_ */
diff --git a/arch/frv/include/asm/irq_regs.h b/arch/frv/include/asm/irq_regs.h
deleted file mode 100644
index d22e83289ad1..000000000000
--- a/arch/frv/include/asm/irq_regs.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* FRV per-CPU frame pointer holder
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRQ_REGS_H
-#define _ASM_IRQ_REGS_H
-
-/*
- * Per-cpu current frame pointer - the location of the last exception frame on
- * the stack
- * - on FRV, GR28 is dedicated to keeping a pointer to the current exception
- * frame
- */
-#define ARCH_HAS_OWN_IRQ_REGS
-
-#ifndef __ASSEMBLY__
-#define get_irq_regs() (__frame)
-#endif
-
-#endif /* _ASM_IRQ_REGS_H */
diff --git a/arch/frv/include/asm/irqflags.h b/arch/frv/include/asm/irqflags.h
deleted file mode 100644
index 82f0b5363f42..000000000000
--- a/arch/frv/include/asm/irqflags.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* FR-V interrupt handling
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-/*
- * interrupt flag manipulation
- * - use virtual interrupt management since touching the PSR is slow
- * - ICC2.Z: T if interrupts virtually disabled
- * - ICC2.C: F if interrupts really disabled
- * - if Z==1 upon interrupt:
- * - C is set to 0
- * - interrupts are really disabled
- * - entry.S returns immediately
- * - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts
- * - if taken, the trap:
- * - sets ICC2.C
- * - enables interrupts
- */
-static inline void arch_local_irq_disable(void)
-{
- /* set Z flag, but don't change the C flag */
- asm volatile(" andcc gr0,gr0,gr0,icc2 \n"
- :
- :
- : "memory", "icc2"
- );
-}
-
-static inline void arch_local_irq_enable(void)
-{
- /* clear Z flag and then test the C flag */
- asm volatile(" oricc gr0,#1,gr0,icc2 \n"
- " tihi icc2,gr0,#2 \n"
- :
- :
- : "memory", "icc2"
- );
-}
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
-
- asm volatile("movsg ccr,%0"
- : "=r"(flags)
- :
- : "memory");
-
- /* shift ICC2.Z to bit 0 */
- flags >>= 26;
-
- /* make flags 1 if interrupts disabled, 0 otherwise */
- return flags & 1UL;
-
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags = arch_local_save_flags();
- arch_local_irq_disable();
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- /* load the Z flag by turning 1 if disabled into 0 if disabled
- * and thus setting the Z flag but not the C flag */
- asm volatile(" xoricc %0,#1,gr0,icc2 \n"
- /* then trap if Z=0 and C=0 */
- " tihi icc2,gr0,#2 \n"
- :
- : "r"(flags)
- : "memory", "icc2"
- );
-
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return flags;
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-/*
- * real interrupt flag manipulation
- */
-#define __arch_local_irq_disable() \
-do { \
- unsigned long psr; \
- asm volatile(" movsg psr,%0 \n" \
- " andi %0,%2,%0 \n" \
- " ori %0,%1,%0 \n" \
- " movgs %0,psr \n" \
- : "=r"(psr) \
- : "i" (PSR_PIL_14), "i" (~PSR_PIL) \
- : "memory"); \
-} while (0)
-
-#define __arch_local_irq_enable() \
-do { \
- unsigned long psr; \
- asm volatile(" movsg psr,%0 \n" \
- " andi %0,%1,%0 \n" \
- " movgs %0,psr \n" \
- : "=r"(psr) \
- : "i" (~PSR_PIL) \
- : "memory"); \
-} while (0)
-
-#define __arch_local_save_flags(flags) \
-do { \
- typecheck(unsigned long, flags); \
- asm("movsg psr,%0" \
- : "=r"(flags) \
- : \
- : "memory"); \
-} while (0)
-
-#define __arch_local_irq_save(flags) \
-do { \
- unsigned long npsr; \
- typecheck(unsigned long, flags); \
- asm volatile(" movsg psr,%0 \n" \
- " andi %0,%3,%1 \n" \
- " ori %1,%2,%1 \n" \
- " movgs %1,psr \n" \
- : "=r"(flags), "=r"(npsr) \
- : "i" (PSR_PIL_14), "i" (~PSR_PIL) \
- : "memory"); \
-} while (0)
-
-#define __arch_local_irq_restore(flags) \
-do { \
- typecheck(unsigned long, flags); \
- asm volatile(" movgs %0,psr \n" \
- : \
- : "r" (flags) \
- : "memory"); \
-} while (0)
-
-#define __arch_irqs_disabled() \
- ((__get_PSR() & PSR_PIL) >= PSR_PIL_14)
-
-#endif /* _ASM_IRQFLAGS_H */
diff --git a/arch/frv/include/asm/kdebug.h b/arch/frv/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/frv/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/frv/include/asm/kmap_types.h b/arch/frv/include/asm/kmap_types.h
deleted file mode 100644
index 0849db1362d6..000000000000
--- a/arch/frv/include/asm/kmap_types.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-#define KM_TYPE_NR 17
-
-#endif
diff --git a/arch/frv/include/asm/linkage.h b/arch/frv/include/asm/linkage.h
deleted file mode 100644
index 636c1bced7d4..000000000000
--- a/arch/frv/include/asm/linkage.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/arch/frv/include/asm/local.h b/arch/frv/include/asm/local.h
deleted file mode 100644
index 259ae7b041a7..000000000000
--- a/arch/frv/include/asm/local.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_LOCAL_H
-#define _ASM_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif /* _ASM_LOCAL_H */
diff --git a/arch/frv/include/asm/local64.h b/arch/frv/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/frv/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/frv/include/asm/math-emu.h b/arch/frv/include/asm/math-emu.h
deleted file mode 100644
index 8af762dd6109..000000000000
--- a/arch/frv/include/asm/math-emu.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_MATH_EMU_H
-#define _ASM_MATH_EMU_H
-
-#include <asm/setup.h>
-#include <linux/linkage.h>
-
-/* Status Register bits */
-
-/* accrued exception bits */
-#define FPSR_AEXC_INEX 3
-#define FPSR_AEXC_DZ 4
-#define FPSR_AEXC_UNFL 5
-#define FPSR_AEXC_OVFL 6
-#define FPSR_AEXC_IOP 7
-
-/* exception status bits */
-#define FPSR_EXC_INEX1 8
-#define FPSR_EXC_INEX2 9
-#define FPSR_EXC_DZ 10
-#define FPSR_EXC_UNFL 11
-#define FPSR_EXC_OVFL 12
-#define FPSR_EXC_OPERR 13
-#define FPSR_EXC_SNAN 14
-#define FPSR_EXC_BSUN 15
-
-/* quotient byte, assumes big-endian, of course */
-#define FPSR_QUOTIENT(fpsr) (*((signed char *) &(fpsr) + 1))
-
-/* condition code bits */
-#define FPSR_CC_NAN 24
-#define FPSR_CC_INF 25
-#define FPSR_CC_Z 26
-#define FPSR_CC_NEG 27
-
-
-/* Control register bits */
-
-/* rounding mode */
-#define FPCR_ROUND_RN 0 /* round to nearest/even */
-#define FPCR_ROUND_RZ 1 /* round to zero */
-#define FPCR_ROUND_RM 2 /* minus infinity */
-#define FPCR_ROUND_RP 3 /* plus infinity */
-
-/* rounding precision */
-#define FPCR_PRECISION_X 0 /* long double */
-#define FPCR_PRECISION_S 1 /* double */
-#define FPCR_PRECISION_D 2 /* float */
-
-
-/* Flags to select the debugging output */
-#define PDECODE 0
-#define PEXECUTE 1
-#define PCONV 2
-#define PNORM 3
-#define PREGISTER 4
-#define PINSTR 5
-#define PUNIMPL 6
-#define PMOVEM 7
-
-#define PMDECODE (1<<PDECODE)
-#define PMEXECUTE (1<<PEXECUTE)
-#define PMCONV (1<<PCONV)
-#define PMNORM (1<<PNORM)
-#define PMREGISTER (1<<PREGISTER)
-#define PMINSTR (1<<PINSTR)
-#define PMUNIMPL (1<<PUNIMPL)
-#define PMMOVEM (1<<PMOVEM)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-union fp_mant64 {
- unsigned long long m64;
- unsigned long m32[2];
-};
-
-union fp_mant128 {
- unsigned long long m64[2];
- unsigned long m32[4];
-};
-
-/* internal representation of extended fp numbers */
-struct fp_ext {
- unsigned char lowmant;
- unsigned char sign;
- unsigned short exp;
- union fp_mant64 mant;
-};
-
-/* C representation of FPU registers */
-/* NOTE: if you change this, you have to change the assembler offsets
- below and the size in <asm/fpu.h>, too */
-struct fp_data {
- struct fp_ext fpreg[8];
- unsigned int fpcr;
- unsigned int fpsr;
- unsigned int fpiar;
- unsigned short prec;
- unsigned short rnd;
- struct fp_ext temp[2];
-};
-
-#if FPU_EMU_DEBUG
-extern unsigned int fp_debugprint;
-
-#define dprint(bit, fmt, args...) ({ \
- if (fp_debugprint & (1 << (bit))) \
- printk(fmt, ## args); \
-})
-#else
-#define dprint(bit, fmt, args...)
-#endif
-
-#define uprint(str) ({ \
- static int __count = 3; \
- \
- if (__count > 0) { \
- printk("You just hit an unimplemented " \
- "fpu instruction (%s)\n", str); \
- printk("Please report this to ....\n"); \
- __count--; \
- } \
-})
-
-#define FPDATA ((struct fp_data *)current->thread.fp)
-
-#else /* __ASSEMBLY__ */
-
-#define FPDATA %a2
-
-/* offsets from the base register to the floating point data in the task struct */
-#define FPD_FPREG (TASK_THREAD+THREAD_FPREG+0)
-#define FPD_FPCR (TASK_THREAD+THREAD_FPREG+96)
-#define FPD_FPSR (TASK_THREAD+THREAD_FPREG+100)
-#define FPD_FPIAR (TASK_THREAD+THREAD_FPREG+104)
-#define FPD_PREC (TASK_THREAD+THREAD_FPREG+108)
-#define FPD_RND (TASK_THREAD+THREAD_FPREG+110)
-#define FPD_TEMPFP1 (TASK_THREAD+THREAD_FPREG+112)
-#define FPD_TEMPFP2 (TASK_THREAD+THREAD_FPREG+124)
-#define FPD_SIZEOF (TASK_THREAD+THREAD_FPREG+136)
-
-/* offsets on the stack to access saved registers,
- * these are only used during instruction decoding
- * where we always know how deep we're on the stack.
- */
-#define FPS_DO (PT_D0)
-#define FPS_D1 (PT_D1)
-#define FPS_D2 (PT_D2)
-#define FPS_A0 (PT_A0)
-#define FPS_A1 (PT_A1)
-#define FPS_A2 (PT_A2)
-#define FPS_SR (PT_SR)
-#define FPS_PC (PT_PC)
-#define FPS_EA (PT_PC+6)
-#define FPS_PC2 (PT_PC+10)
-
-.macro fp_get_fp_reg
- lea (FPD_FPREG,FPDATA,%d0.w*4),%a0
- lea (%a0,%d0.w*8),%a0
-.endm
-
-/* Macros used to get/put the current program counter.
- * 020/030 use a different stack frame then 040/060, for the
- * 040/060 the return pc points already to the next location,
- * so this only needs to be modified for jump instructions.
- */
-.macro fp_get_pc dest
- move.l (FPS_PC+4,%sp),\dest
-.endm
-
-.macro fp_put_pc src,jump=0
- move.l \src,(FPS_PC+4,%sp)
-.endm
-
-.macro fp_get_instr_data f,s,dest,label
- getuser \f,%sp@(FPS_PC+4)@(0),\dest,\label,%sp@(FPS_PC+4)
- addq.l #\s,%sp@(FPS_PC+4)
-.endm
-
-.macro fp_get_instr_word dest,label,addr
- fp_get_instr_data w,2,\dest,\label,\addr
-.endm
-
-.macro fp_get_instr_long dest,label,addr
- fp_get_instr_data l,4,\dest,\label,\addr
-.endm
-
-/* These macros are used to read from/write to user space
- * on error we jump to the fixup section, load the fault
- * address into %a0 and jump to the exit.
- * (derived from <asm/uaccess.h>)
- */
-.macro getuser size,src,dest,label,addr
-| printf ,"[\size<%08x]",1,\addr
-.Lu1\@: moves\size \src,\dest
-
- .section .fixup,"ax"
- .even
-.Lu2\@: move.l \addr,%a0
- jra \label
- .previous
-
- .section __ex_table,"a"
- .align 4
- .long .Lu1\@,.Lu2\@
- .previous
-.endm
-
-.macro putuser size,src,dest,label,addr
-| printf ,"[\size>%08x]",1,\addr
-.Lu1\@: moves\size \src,\dest
-.Lu2\@:
-
- .section .fixup,"ax"
- .even
-.Lu3\@: move.l \addr,%a0
- jra \label
- .previous
-
- .section __ex_table,"a"
- .align 4
- .long .Lu1\@,.Lu3\@
- .long .Lu2\@,.Lu3\@
- .previous
-.endm
-
-
-.macro movestack nr,arg1,arg2,arg3,arg4,arg5
- .if \nr
- movestack (\nr-1),\arg2,\arg3,\arg4,\arg5
- move.l \arg1,-(%sp)
- .endif
-.endm
-
-.macro printf bit=-1,string,nr=0,arg1,arg2,arg3,arg4,arg5
-#ifdef FPU_EMU_DEBUG
- .data
-.Lpdata\@:
- .string "\string"
- .previous
-
- movem.l %d0/%d1/%a0/%a1,-(%sp)
- .if \bit+1
-#if 0
- moveq #\bit,%d0
- andw #7,%d0
- btst %d0,fp_debugprint+((31-\bit)/8)
-#else
- btst #\bit,fp_debugprint+((31-\bit)/8)
-#endif
- jeq .Lpskip\@
- .endif
- movestack \nr,\arg1,\arg2,\arg3,\arg4,\arg5
- pea .Lpdata\@
- jsr printk
- lea ((\nr+1)*4,%sp),%sp
-.Lpskip\@:
- movem.l (%sp)+,%d0/%d1/%a0/%a1
-#endif
-.endm
-
-.macro printx bit,fp
-#ifdef FPU_EMU_DEBUG
- movem.l %d0/%a0,-(%sp)
- lea \fp,%a0
-#if 0
- moveq #'+',%d0
- tst.w (%a0)
- jeq .Lx1\@
- moveq #'-',%d0
-.Lx1\@: printf \bit," %c",1,%d0
- move.l (4,%a0),%d0
- bclr #31,%d0
- jne .Lx2\@
- printf \bit,"0."
- jra .Lx3\@
-.Lx2\@: printf \bit,"1."
-.Lx3\@: printf \bit,"%08x%08x",2,%d0,%a0@(8)
- move.w (2,%a0),%d0
- ext.l %d0
- printf \bit,"E%04x",1,%d0
-#else
- printf \bit," %08x%08x%08x",3,%a0@,%a0@(4),%a0@(8)
-#endif
- movem.l (%sp)+,%d0/%a0
-#endif
-.endm
-
-.macro debug instr,args
-#ifdef FPU_EMU_DEBUG
- \instr \args
-#endif
-.endm
-
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_FRV_MATH_EMU_H */
-
diff --git a/arch/frv/include/asm/mb-regs.h b/arch/frv/include/asm/mb-regs.h
deleted file mode 100644
index 219e5f926f18..000000000000
--- a/arch/frv/include/asm/mb-regs.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* mb-regs.h: motherboard registers
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB_REGS_H
-#define _ASM_MB_REGS_H
-
-#include <asm/cpu-irqs.h>
-#include <asm/sections.h>
-#include <asm/mem-layout.h>
-
-#ifndef __ASSEMBLY__
-/* gcc builtins, annotated */
-
-unsigned long __builtin_read8(volatile void __iomem *);
-unsigned long __builtin_read16(volatile void __iomem *);
-unsigned long __builtin_read32(volatile void __iomem *);
-void __builtin_write8(volatile void __iomem *, unsigned char);
-void __builtin_write16(volatile void __iomem *, unsigned short);
-void __builtin_write32(volatile void __iomem *, unsigned long);
-#endif
-
-#define __region_IO KERNEL_IO_START /* the region from 0xe0000000 to 0xffffffff has suitable
- * protection laid over the top for use in memory-mapped
- * I/O
- */
-
-#define __region_CS0 0xff000000 /* Boot ROMs area */
-
-#ifdef CONFIG_MB93091_VDK
-/*
- * VDK motherboard and CPU card specific stuff
- */
-
-#include <asm/mb93091-fpga-irqs.h>
-
-#define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0
-#define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1
-
-#define __region_CS2 0xe0000000 /* SLBUS/PCI I/O space */
-#define __region_CS2_M 0x0fffffff /* mask */
-#define __region_CS2_C 0x00000000 /* control */
-#define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */
-#define __region_CS5_M 0x00ffffff
-#define __region_CS5_C 0x00010000
-#define __region_CS7 0xf1000000 /* CB70 CPU-card PCMCIA port I/O space */
-#define __region_CS7_M 0x00ffffff
-#define __region_CS7_C 0x00410701
-#define __region_CS1 0xfc000000 /* SLBUS/PCI bridge control registers */
-#define __region_CS1_M 0x000fffff
-#define __region_CS1_C 0x00000000
-#define __region_CS6 0xfc100000 /* CB70 CPU-card DM9000 LAN I/O space */
-#define __region_CS6_M 0x000fffff
-#define __region_CS6_C 0x00400707
-#define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
-#define __region_CS3_M 0x000fffff
-#define __region_CS3_C 0xc8100000
-#define __region_CS4 0xfd000000 /* CB70 CPU-card extra flash space */
-#define __region_CS4_M 0x00ffffff
-#define __region_CS4_C 0x00000f07
-
-#define __region_PCI_IO (__region_CS2 + 0x04000000UL)
-#define __region_PCI_MEM (__region_CS2 + 0x08000000UL)
-#define __flush_PCI_writes() \
-do { \
- __builtin_write8((volatile void __iomem *) __region_PCI_MEM, 0); \
-} while(0)
-
-#define __is_PCI_IO(addr) \
- (((unsigned long)(addr) >> 24) - (__region_PCI_IO >> 24) < (0x04000000UL >> 24))
-
-#define __is_PCI_MEM(addr) \
- ((unsigned long)(addr) - __region_PCI_MEM < 0x08000000UL)
-
-#define __is_PCI_addr(addr) \
- ((unsigned long)(addr) - __region_PCI_IO < 0x0c000000UL)
-
-#define __get_CLKSW() ({ *(volatile unsigned long *)(__region_CS2 + 0x0130000cUL) & 0xffUL; })
-#define __get_CLKIN() (__get_CLKSW() * 125U * 100000U / 24U)
-
-#ifndef __ASSEMBLY__
-extern int __nongprelbss mb93090_mb00_detected;
-#endif
-
-#define __addr_LEDS() (__region_CS2 + 0x01200004UL)
-#ifdef CONFIG_MB93090_MB00
-#define __set_LEDS(X) \
-do { \
- if (mb93090_mb00_detected) \
- __builtin_write32((void __iomem *) __addr_LEDS(), ~(X)); \
-} while (0)
-#else
-#define __set_LEDS(X)
-#endif
-
-#define __addr_LCD() (__region_CS2 + 0x01200008UL)
-#define __get_LCD(B) __builtin_read32((volatile void __iomem *) (B))
-#define __set_LCD(B,X) __builtin_write32((volatile void __iomem *) (B), (X))
-
-#define LCD_D 0x000000ff /* LCD data bus */
-#define LCD_RW 0x00000100 /* LCD R/W signal */
-#define LCD_RS 0x00000200 /* LCD Register Select */
-#define LCD_E 0x00000400 /* LCD Start Enable Signal */
-
-#define LCD_CMD_CLEAR (LCD_E|0x001)
-#define LCD_CMD_HOME (LCD_E|0x002)
-#define LCD_CMD_CURSOR_INC (LCD_E|0x004)
-#define LCD_CMD_SCROLL_INC (LCD_E|0x005)
-#define LCD_CMD_CURSOR_DEC (LCD_E|0x006)
-#define LCD_CMD_SCROLL_DEC (LCD_E|0x007)
-#define LCD_CMD_OFF (LCD_E|0x008)
-#define LCD_CMD_ON(CRSR,BLINK) (LCD_E|0x00c|(CRSR<<1)|BLINK)
-#define LCD_CMD_CURSOR_MOVE_L (LCD_E|0x010)
-#define LCD_CMD_CURSOR_MOVE_R (LCD_E|0x014)
-#define LCD_CMD_DISPLAY_SHIFT_L (LCD_E|0x018)
-#define LCD_CMD_DISPLAY_SHIFT_R (LCD_E|0x01c)
-#define LCD_CMD_FUNCSET(DL,N,F) (LCD_E|0x020|(DL<<4)|(N<<3)|(F<<2))
-#define LCD_CMD_SET_CG_ADDR(X) (LCD_E|0x040|X)
-#define LCD_CMD_SET_DD_ADDR(X) (LCD_E|0x080|X)
-#define LCD_CMD_READ_BUSY (LCD_E|LCD_RW)
-#define LCD_DATA_WRITE(X) (LCD_E|LCD_RS|(X))
-#define LCD_DATA_READ (LCD_E|LCD_RS|LCD_RW)
-
-#else
-/*
- * PDK unit specific stuff
- */
-
-#include <asm/mb93093-fpga-irqs.h>
-
-#define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0
-#define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1
-
-#define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */
-#define __region_CS5_M 0x00ffffff /* mask */
-#define __region_CS5_C 0x00010000 /* control */
-#define __region_CS2 0x20000000 /* FPGA registers */
-#define __region_CS2_M 0x000fffff
-#define __region_CS2_C 0x00000000
-#define __region_CS1 0xfc100000 /* LAN registers */
-#define __region_CS1_M 0x000fffff
-#define __region_CS1_C 0x00010404
-#define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
-#define __region_CS3_M 0x000fffff
-#define __region_CS3_C 0xc8000000
-#define __region_CS4 0xfd000000 /* extra ROMs area */
-#define __region_CS4_M 0x00ffffff
-#define __region_CS4_C 0x00000f07
-
-#define __region_CS6 0xfe000000 /* not used - hide behind CPU resource I/O regs */
-#define __region_CS6_M 0x000fffff
-#define __region_CS6_C 0x00000f07
-#define __region_CS7 0xfe000000 /* not used - hide behind CPU resource I/O regs */
-#define __region_CS7_M 0x000fffff
-#define __region_CS7_C 0x00000f07
-
-#define __is_PCI_IO(addr) 0 /* no PCI */
-#define __is_PCI_MEM(addr) 0
-#define __is_PCI_addr(addr) 0
-#define __region_PCI_IO 0
-#define __region_PCI_MEM 0
-#define __flush_PCI_writes() do { } while(0)
-
-#define __get_CLKSW() 0UL
-#define __get_CLKIN() 66000000UL
-
-#define __addr_LEDS() (__region_CS2 + 0x00000023UL)
-#define __set_LEDS(X) __builtin_write8((volatile void __iomem *) __addr_LEDS(), (X))
-
-#define __addr_FPGATR() (__region_CS2 + 0x00000030UL)
-#define __set_FPGATR(X) __builtin_write32((volatile void __iomem *) __addr_FPGATR(), (X))
-#define __get_FPGATR() __builtin_read32((volatile void __iomem *) __addr_FPGATR())
-
-#define MB93093_FPGA_FPGATR_AUDIO_CLK 0x00000003
-
-#define __set_FPGATR_AUDIO_CLK(V) \
- __set_FPGATR((__get_FPGATR() & ~MB93093_FPGA_FPGATR_AUDIO_CLK) | (V))
-
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_OFF 0x0
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_11MHz 0x1
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_12MHz 0x2
-#define MB93093_FPGA_FPGATR_AUDIO_CLK_02MHz 0x3
-
-#define MB93093_FPGA_SWR_PUSHSWMASK (0x1F<<26)
-#define MB93093_FPGA_SWR_PUSHSW4 (1<<29)
-
-#define __addr_FPGA_SWR ((volatile void __iomem *)(__region_CS2 + 0x28UL))
-#define __get_FPGA_PUSHSW1_5() (__builtin_read32(__addr_FPGA_SWR) & MB93093_FPGA_SWR_PUSHSWMASK)
-
-
-#endif
-
-#endif /* _ASM_MB_REGS_H */
diff --git a/arch/frv/include/asm/mb86943a.h b/arch/frv/include/asm/mb86943a.h
deleted file mode 100644
index e87ef924bfb4..000000000000
--- a/arch/frv/include/asm/mb86943a.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mb86943a.h: MB86943 SPARClite <-> PCI bridge registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB86943A_H
-#define _ASM_MB86943A_H
-
-#include <asm/mb-regs.h>
-
-#define __reg_MB86943_sl_ctl *(volatile uint32_t *) (__region_CS1 + 0x00)
-
-#define MB86943_SL_CTL_BUS_WIDTH_64 0x00000001
-#define MB86943_SL_CTL_AS_HOST 0x00000002
-#define MB86943_SL_CTL_DRCT_MASTER_SWAP 0x00000004
-#define MB86943_SL_CTL_DRCT_SLAVE_SWAP 0x00000008
-#define MB86943_SL_CTL_PCI_CONFIG_SWAP 0x00000010
-#define MB86943_SL_CTL_ECS0_ENABLE 0x00000020
-#define MB86943_SL_CTL_ECS1_ENABLE 0x00000040
-#define MB86943_SL_CTL_ECS2_ENABLE 0x00000080
-
-#define __reg_MB86943_ecs_ctl(N) *(volatile uint32_t *) (__region_CS1 + 0x08 + (0x08*(N)))
-#define __reg_MB86943_ecs_range(N) *(volatile uint32_t *) (__region_CS1 + 0x20 + (0x10*(N)))
-#define __reg_MB86943_ecs_base(N) *(volatile uint32_t *) (__region_CS1 + 0x28 + (0x10*(N)))
-
-#define __reg_MB86943_sl_pci_io_range *(volatile uint32_t *) (__region_CS1 + 0x50)
-#define __reg_MB86943_sl_pci_io_base *(volatile uint32_t *) (__region_CS1 + 0x58)
-#define __reg_MB86943_sl_pci_mem_range *(volatile uint32_t *) (__region_CS1 + 0x60)
-#define __reg_MB86943_sl_pci_mem_base *(volatile uint32_t *) (__region_CS1 + 0x68)
-#define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70)
-#define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78)
-
-#define __reg_MB86943_pci_arbiter *(volatile uint32_t *) (__region_CS2 + 0x01300014)
-#define MB86943_PCIARB_EN 0x00000001
-
-#endif /* _ASM_MB86943A_H */
diff --git a/arch/frv/include/asm/mb93091-fpga-irqs.h b/arch/frv/include/asm/mb93091-fpga-irqs.h
deleted file mode 100644
index 19778c5ba9d6..000000000000
--- a/arch/frv/include/asm/mb93091-fpga-irqs.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* mb93091-fpga-irqs.h: MB93091 CPU board FPGA IRQs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93091_FPGA_IRQS_H
-#define _ASM_MB93091_FPGA_IRQS_H
-
-#include <asm/irq.h>
-
-#ifndef __ASSEMBLY__
-
-/* IRQ IDs presented to drivers */
-enum {
- IRQ_FPGA__UNUSED = IRQ_BASE_FPGA,
- IRQ_FPGA_SYSINT_BUS_EXPANSION_1,
- IRQ_FPGA_SL_BUS_EXPANSION_2,
- IRQ_FPGA_PCI_INTD,
- IRQ_FPGA_PCI_INTC,
- IRQ_FPGA_PCI_INTB,
- IRQ_FPGA_PCI_INTA,
- IRQ_FPGA_SL_BUS_EXPANSION_7,
- IRQ_FPGA_SYSINT_BUS_EXPANSION_8,
- IRQ_FPGA_SL_BUS_EXPANSION_9,
- IRQ_FPGA_MB86943_PCI_INTA,
- IRQ_FPGA_MB86943_SLBUS_SIDE,
- IRQ_FPGA_RTL8029_INTA,
- IRQ_FPGA_SYSINT_BUS_EXPANSION_13,
- IRQ_FPGA_SL_BUS_EXPANSION_14,
- IRQ_FPGA_NMI,
-};
-
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MB93091_FPGA_IRQS_H */
diff --git a/arch/frv/include/asm/mb93093-fpga-irqs.h b/arch/frv/include/asm/mb93093-fpga-irqs.h
deleted file mode 100644
index 590266b1a6d3..000000000000
--- a/arch/frv/include/asm/mb93093-fpga-irqs.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* mb93093-fpga-irqs.h: MB93093 CPU board FPGA IRQs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93093_FPGA_IRQS_H
-#define _ASM_MB93093_FPGA_IRQS_H
-
-#include <asm/irq.h>
-
-#ifndef __ASSEMBLY__
-
-/* IRQ IDs presented to drivers */
-enum {
- IRQ_FPGA_PUSH_BUTTON_SW1_5 = IRQ_BASE_FPGA + 8,
- IRQ_FPGA_ROCKER_C_SW8 = IRQ_BASE_FPGA + 9,
- IRQ_FPGA_ROCKER_C_SW9 = IRQ_BASE_FPGA + 10,
-};
-
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MB93093_FPGA_IRQS_H */
diff --git a/arch/frv/include/asm/mb93493-irqs.h b/arch/frv/include/asm/mb93493-irqs.h
deleted file mode 100644
index 82c7aeddd333..000000000000
--- a/arch/frv/include/asm/mb93493-irqs.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* mb93493-irqs.h: MB93493 companion chip IRQs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93493_IRQS_H
-#define _ASM_MB93493_IRQS_H
-
-#include <asm/irq.h>
-
-#ifndef __ASSEMBLY__
-
-/* IRQ IDs presented to drivers */
-enum {
- IRQ_MB93493_VDC = IRQ_BASE_MB93493 + 0,
- IRQ_MB93493_VCC = IRQ_BASE_MB93493 + 1,
- IRQ_MB93493_AUDIO_OUT = IRQ_BASE_MB93493 + 2,
- IRQ_MB93493_I2C_0 = IRQ_BASE_MB93493 + 3,
- IRQ_MB93493_I2C_1 = IRQ_BASE_MB93493 + 4,
- IRQ_MB93493_USB = IRQ_BASE_MB93493 + 5,
- IRQ_MB93493_LOCAL_BUS = IRQ_BASE_MB93493 + 7,
- IRQ_MB93493_PCMCIA = IRQ_BASE_MB93493 + 8,
- IRQ_MB93493_GPIO = IRQ_BASE_MB93493 + 9,
- IRQ_MB93493_AUDIO_IN = IRQ_BASE_MB93493 + 10,
-};
-
-/* IRQ multiplexor mappings */
-#define ROUTE_VIA_IRQ0 0 /* route IRQ by way of CPU external IRQ 0 */
-#define ROUTE_VIA_IRQ1 1 /* route IRQ by way of CPU external IRQ 1 */
-
-#define IRQ_MB93493_VDC_ROUTE ROUTE_VIA_IRQ0
-#define IRQ_MB93493_VCC_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_AUDIO_OUT_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_I2C_0_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_I2C_1_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_USB_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_LOCAL_BUS_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_PCMCIA_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_GPIO_ROUTE ROUTE_VIA_IRQ1
-#define IRQ_MB93493_AUDIO_IN_ROUTE ROUTE_VIA_IRQ1
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MB93493_IRQS_H */
diff --git a/arch/frv/include/asm/mb93493-regs.h b/arch/frv/include/asm/mb93493-regs.h
deleted file mode 100644
index 8a1f6aac8cf1..000000000000
--- a/arch/frv/include/asm/mb93493-regs.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/* mb93493-regs.h: MB93493 companion chip registers
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MB93493_REGS_H
-#define _ASM_MB93493_REGS_H
-
-#include <asm/mb-regs.h>
-#include <asm/mb93493-irqs.h>
-
-#define __addr_MB93493(X) ((volatile unsigned long *)(__region_CS3 + (X)))
-#define __get_MB93493(X) ({ *(volatile unsigned long *)(__region_CS3 + (X)); })
-
-#define __set_MB93493(X,V) \
-do { \
- *(volatile unsigned long *)(__region_CS3 + (X)) = (V); mb(); \
-} while(0)
-
-#define __get_MB93493_STSR(X) __get_MB93493(0x3c0 + (X) * 4)
-#define __set_MB93493_STSR(X,V) __set_MB93493(0x3c0 + (X) * 4, (V))
-#define MB93493_STSR_EN
-
-#define __addr_MB93493_IQSR(X) __addr_MB93493(0x3d0 + (X) * 4)
-#define __get_MB93493_IQSR(X) __get_MB93493(0x3d0 + (X) * 4)
-#define __set_MB93493_IQSR(X,V) __set_MB93493(0x3d0 + (X) * 4, (V))
-
-#define __get_MB93493_DQSR(X) __get_MB93493(0x3e0 + (X) * 4)
-#define __set_MB93493_DQSR(X,V) __set_MB93493(0x3e0 + (X) * 4, (V))
-
-#define __get_MB93493_LBSER() __get_MB93493(0x3f0)
-#define __set_MB93493_LBSER(V) __set_MB93493(0x3f0, (V))
-
-#define MB93493_LBSER_VDC 0x00010000
-#define MB93493_LBSER_VCC 0x00020000
-#define MB93493_LBSER_AUDIO 0x00040000
-#define MB93493_LBSER_I2C_0 0x00080000
-#define MB93493_LBSER_I2C_1 0x00100000
-#define MB93493_LBSER_USB 0x00200000
-#define MB93493_LBSER_GPIO 0x00800000
-#define MB93493_LBSER_PCMCIA 0x01000000
-
-#define __get_MB93493_LBSR() __get_MB93493(0x3fc)
-#define __set_MB93493_LBSR(V) __set_MB93493(0x3fc, (V))
-
-/*
- * video display controller
- */
-#define __get_MB93493_VDC(X) __get_MB93493(MB93493_VDC_##X)
-#define __set_MB93493_VDC(X,V) __set_MB93493(MB93493_VDC_##X, (V))
-
-#define MB93493_VDC_RCURSOR 0x140 /* cursor position */
-#define MB93493_VDC_RCT1 0x144 /* cursor colour 1 */
-#define MB93493_VDC_RCT2 0x148 /* cursor colour 2 */
-#define MB93493_VDC_RHDC 0x150 /* horizontal display period */
-#define MB93493_VDC_RH_MARGINS 0x154 /* horizontal margin sizes */
-#define MB93493_VDC_RVDC 0x158 /* vertical display period */
-#define MB93493_VDC_RV_MARGINS 0x15c /* vertical margin sizes */
-#define MB93493_VDC_RC 0x170 /* VDC control */
-#define MB93493_VDC_RCLOCK 0x174 /* clock divider, DMA req delay */
-#define MB93493_VDC_RBLACK 0x178 /* black insert sizes */
-#define MB93493_VDC_RS 0x17c /* VDC status */
-
-#define __addr_MB93493_VDC_BCI(X) ({ (volatile unsigned long *)(__region_CS3 + 0x000 + (X)); })
-#define __addr_MB93493_VDC_TPO(X) (__region_CS3 + 0x1c0 + (X))
-
-#define VDC_TPO_WIDTH 32
-
-#define VDC_RC_DSR 0x00000080 /* VDC master reset */
-
-#define VDC_RS_IT 0x00060000 /* interrupt indicators */
-#define VDC_RS_IT_UNDERFLOW 0x00040000 /* - underflow event */
-#define VDC_RS_IT_VSYNC 0x00020000 /* - VSYNC event */
-#define VDC_RS_DFI 0x00010000 /* current interlace field number */
-#define VDC_RS_DFI_TOP 0x00000000 /* - top field */
-#define VDC_RS_DFI_BOTTOM 0x00010000 /* - bottom field */
-#define VDC_RS_DCSR 0x00000010 /* cursor state */
-#define VDC_RS_DCM 0x00000003 /* display mode */
-#define VDC_RS_DCM_DISABLED 0x00000000 /* - display disabled */
-#define VDC_RS_DCM_STOPPED 0x00000001 /* - VDC stopped */
-#define VDC_RS_DCM_FREERUNNING 0x00000002 /* - VDC free-running */
-#define VDC_RS_DCM_TRANSFERRING 0x00000003 /* - data being transferred to VDC */
-
-/*
- * video capture controller
- */
-#define __get_MB93493_VCC(X) __get_MB93493(MB93493_VCC_##X)
-#define __set_MB93493_VCC(X,V) __set_MB93493(MB93493_VCC_##X, (V))
-
-#define MB93493_VCC_RREDUCT 0x104 /* reduction rate */
-#define MB93493_VCC_RHY 0x108 /* horizontal brightness filter coefficients */
-#define MB93493_VCC_RHC 0x10c /* horizontal colour-difference filter coefficients */
-#define MB93493_VCC_RHSIZE 0x110 /* horizontal cycle sizes */
-#define MB93493_VCC_RHBC 0x114 /* horizontal back porch size */
-#define MB93493_VCC_RVCC 0x118 /* vertical capture period */
-#define MB93493_VCC_RVBC 0x11c /* vertical back porch period */
-#define MB93493_VCC_RV 0x120 /* vertical filter coefficients */
-#define MB93493_VCC_RDTS 0x128 /* DMA transfer size */
-#define MB93493_VCC_RDTS_4B 0x01000000 /* 4-byte transfer */
-#define MB93493_VCC_RDTS_32B 0x03000000 /* 32-byte transfer */
-#define MB93493_VCC_RDTS_SHIFT 24
-#define MB93493_VCC_RCC 0x130 /* VCC control */
-#define MB93493_VCC_RIS 0x134 /* VCC interrupt status */
-
-#define __addr_MB93493_VCC_TPI(X) (__region_CS3 + 0x180 + (X))
-
-#define VCC_RHSIZE_RHCC 0x000007ff
-#define VCC_RHSIZE_RHCC_SHIFT 0
-#define VCC_RHSIZE_RHTCC 0x0fff0000
-#define VCC_RHSIZE_RHTCC_SHIFT 16
-
-#define VCC_RVBC_RVBC 0x00003f00
-#define VCC_RVBC_RVBC_SHIFT 8
-
-#define VCC_RREDUCT_RHR 0x07ff0000
-#define VCC_RREDUCT_RHR_SHIFT 16
-#define VCC_RREDUCT_RVR 0x000007ff
-#define VCC_RREDUCT_RVR_SHIFT 0
-
-#define VCC_RCC_CE 0x00000001 /* VCC enable */
-#define VCC_RCC_CS 0x00000002 /* request video capture start */
-#define VCC_RCC_CPF 0x0000000c /* pixel format */
-#define VCC_RCC_CPF_YCBCR_16 0x00000000 /* - YCbCr 4:2:2 16-bit format */
-#define VCC_RCC_CPF_RGB 0x00000004 /* - RGB 4:4:4 format */
-#define VCC_RCC_CPF_YCBCR_24 0x00000008 /* - YCbCr 4:2:2 24-bit format */
-#define VCC_RCC_CPF_BT656 0x0000000c /* - ITU R-BT.656 format */
-#define VCC_RCC_CPF_SHIFT 2
-#define VCC_RCC_CSR 0x00000080 /* request reset */
-#define VCC_RCC_HSIP 0x00000100 /* HSYNC polarity */
-#define VCC_RCC_HSIP_LOACT 0x00000000 /* - low active */
-#define VCC_RCC_HSIP_HIACT 0x00000100 /* - high active */
-#define VCC_RCC_VSIP 0x00000200 /* VSYNC polarity */
-#define VCC_RCC_VSIP_LOACT 0x00000000 /* - low active */
-#define VCC_RCC_VSIP_HIACT 0x00000200 /* - high active */
-#define VCC_RCC_CIE 0x00000800 /* interrupt enable */
-#define VCC_RCC_CFP 0x00001000 /* RGB pixel packing */
-#define VCC_RCC_CFP_4TO3 0x00000000 /* - pack 4 pixels into 3 words */
-#define VCC_RCC_CFP_1TO1 0x00001000 /* - pack 1 pixel into 1 words */
-#define VCC_RCC_CSM 0x00006000 /* interlace specification */
-#define VCC_RCC_CSM_ONEPASS 0x00002000 /* - non-interlaced */
-#define VCC_RCC_CSM_INTERLACE 0x00004000 /* - interlaced */
-#define VCC_RCC_CSM_SHIFT 13
-#define VCC_RCC_ES 0x00008000 /* capture start polarity */
-#define VCC_RCC_ES_NEG 0x00000000 /* - negative edge */
-#define VCC_RCC_ES_POS 0x00008000 /* - positive edge */
-#define VCC_RCC_IFI 0x00080000 /* inferlace field evaluation reverse */
-#define VCC_RCC_FDTS 0x00300000 /* interlace field start */
-#define VCC_RCC_FDTS_3_8 0x00000000 /* - 3/8 of horizontal entire cycle */
-#define VCC_RCC_FDTS_1_4 0x00100000 /* - 1/4 of horizontal entire cycle */
-#define VCC_RCC_FDTS_7_16 0x00200000 /* - 7/16 of horizontal entire cycle */
-#define VCC_RCC_FDTS_SHIFT 20
-#define VCC_RCC_MOV 0x00400000 /* test bit - always set to 1 */
-#define VCC_RCC_STP 0x00800000 /* request video capture stop */
-#define VCC_RCC_TO 0x01000000 /* input during top-field only */
-
-#define VCC_RIS_VSYNC 0x01000000 /* VSYNC interrupt */
-#define VCC_RIS_OV 0x02000000 /* overflow interrupt */
-#define VCC_RIS_BOTTOM 0x08000000 /* interlace bottom field */
-#define VCC_RIS_STARTED 0x10000000 /* capture started */
-
-/*
- * I2C
- */
-#define MB93493_I2C_BSR 0x340 /* bus status */
-#define MB93493_I2C_BCR 0x344 /* bus control */
-#define MB93493_I2C_CCR 0x348 /* clock control */
-#define MB93493_I2C_ADR 0x34c /* address */
-#define MB93493_I2C_DTR 0x350 /* data */
-#define MB93493_I2C_BC2R 0x35c /* bus control 2 */
-
-#define __addr_MB93493_I2C(port,X) (__region_CS3 + MB93493_I2C_##X + ((port)*0x20))
-#define __get_MB93493_I2C(port,X) __get_MB93493(MB93493_I2C_##X + ((port)*0x20))
-#define __set_MB93493_I2C(port,X,V) __set_MB93493(MB93493_I2C_##X + ((port)*0x20), (V))
-
-#define I2C_BSR_BB (1 << 7)
-
-/*
- * audio controller (I2S) registers
- */
-#define __get_MB93493_I2S(X) __get_MB93493(MB93493_I2S_##X)
-#define __set_MB93493_I2S(X,V) __set_MB93493(MB93493_I2S_##X, (V))
-
-#define MB93493_I2S_ALDR 0x300 /* L-channel data */
-#define MB93493_I2S_ARDR 0x304 /* R-channel data */
-#define MB93493_I2S_APDR 0x308 /* 16-bit packed data */
-#define MB93493_I2S_AISTR 0x310 /* status */
-#define MB93493_I2S_AICR 0x314 /* control */
-
-#define __addr_MB93493_I2S_ALDR(X) (__region_CS3 + MB93493_I2S_ALDR + (X))
-#define __addr_MB93493_I2S_ARDR(X) (__region_CS3 + MB93493_I2S_ARDR + (X))
-#define __addr_MB93493_I2S_APDR(X) (__region_CS3 + MB93493_I2S_APDR + (X))
-#define __addr_MB93493_I2S_ADR(X) (__region_CS3 + 0x320 + (X))
-
-#define I2S_AISTR_OTST 0x00000003 /* status of output data transfer */
-#define I2S_AISTR_OTR 0x00000010 /* output transfer request pending */
-#define I2S_AISTR_OUR 0x00000020 /* output FIFO underrun detected */
-#define I2S_AISTR_OOR 0x00000040 /* output FIFO overrun detected */
-#define I2S_AISTR_ODS 0x00000100 /* output DMA transfer size */
-#define I2S_AISTR_ODE 0x00000400 /* output DMA transfer request enable */
-#define I2S_AISTR_OTRIE 0x00001000 /* output transfer request interrupt enable */
-#define I2S_AISTR_OURIE 0x00002000 /* output FIFO underrun interrupt enable */
-#define I2S_AISTR_OORIE 0x00004000 /* output FIFO overrun interrupt enable */
-#define I2S_AISTR__OUT_MASK 0x00007570
-#define I2S_AISTR_ITST 0x00030000 /* status of input data transfer */
-#define I2S_AISTR_ITST_SHIFT 16
-#define I2S_AISTR_ITR 0x00100000 /* input transfer request pending */
-#define I2S_AISTR_IUR 0x00200000 /* input FIFO underrun detected */
-#define I2S_AISTR_IOR 0x00400000 /* input FIFO overrun detected */
-#define I2S_AISTR_IDS 0x01000000 /* input DMA transfer size */
-#define I2S_AISTR_IDE 0x04000000 /* input DMA transfer request enable */
-#define I2S_AISTR_ITRIE 0x10000000 /* input transfer request interrupt enable */
-#define I2S_AISTR_IURIE 0x20000000 /* input FIFO underrun interrupt enable */
-#define I2S_AISTR_IORIE 0x40000000 /* input FIFO overrun interrupt enable */
-#define I2S_AISTR__IN_MASK 0x75700000
-
-#define I2S_AICR_MI 0x00000001 /* mono input requested */
-#define I2S_AICR_AMI 0x00000002 /* relation between LRCKI/FS1 and SDI */
-#define I2S_AICR_LRI 0x00000004 /* function of LRCKI pin */
-#define I2S_AICR_SDMI 0x00000070 /* format of input audio data */
-#define I2S_AICR_SDMI_SHIFT 4
-#define I2S_AICR_CLI 0x00000080 /* input FIFO clearing control */
-#define I2S_AICR_IM 0x00000300 /* input state control */
-#define I2S_AICR_IM_SHIFT 8
-#define I2S_AICR__IN_MASK 0x000003f7
-#define I2S_AICR_MO 0x00001000 /* mono output requested */
-#define I2S_AICR_AMO 0x00002000 /* relation between LRCKO/FS0 and SDO */
-#define I2S_AICR_AMO_SHIFT 13
-#define I2S_AICR_LRO 0x00004000 /* function of LRCKO pin */
-#define I2S_AICR_SDMO 0x00070000 /* format of output audio data */
-#define I2S_AICR_SDMO_SHIFT 16
-#define I2S_AICR_CLO 0x00080000 /* output FIFO clearing control */
-#define I2S_AICR_OM 0x00100000 /* output state control */
-#define I2S_AICR__OUT_MASK 0x001f7000
-#define I2S_AICR_DIV 0x03000000 /* frequency division rate */
-#define I2S_AICR_DIV_SHIFT 24
-#define I2S_AICR_FL 0x20000000 /* frame length */
-#define I2S_AICR_FS 0x40000000 /* frame sync method */
-#define I2S_AICR_ME 0x80000000 /* master enable */
-
-/*
- * PCMCIA
- */
-#define __addr_MB93493_PCMCIA(X) ((volatile unsigned long *)(__region_CS5 + (X)))
-
-/*
- * GPIO
- */
-#define __get_MB93493_GPIO_PDR(X) __get_MB93493(0x380 + (X) * 0xc0)
-#define __set_MB93493_GPIO_PDR(X,V) __set_MB93493(0x380 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_GPDR(X) __get_MB93493(0x384 + (X) * 0xc0)
-#define __set_MB93493_GPIO_GPDR(X,V) __set_MB93493(0x384 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_SIR(X) __get_MB93493(0x388 + (X) * 0xc0)
-#define __set_MB93493_GPIO_SIR(X,V) __set_MB93493(0x388 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_SOR(X) __get_MB93493(0x38c + (X) * 0xc0)
-#define __set_MB93493_GPIO_SOR(X,V) __set_MB93493(0x38c + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_PDSR(X) __get_MB93493(0x390 + (X) * 0xc0)
-#define __set_MB93493_GPIO_PDSR(X,V) __set_MB93493(0x390 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_PDCR(X) __get_MB93493(0x394 + (X) * 0xc0)
-#define __set_MB93493_GPIO_PDCR(X,V) __set_MB93493(0x394 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_INTST(X) __get_MB93493(0x398 + (X) * 0xc0)
-#define __set_MB93493_GPIO_INTST(X,V) __set_MB93493(0x398 + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_IEHL(X) __get_MB93493(0x39c + (X) * 0xc0)
-#define __set_MB93493_GPIO_IEHL(X,V) __set_MB93493(0x39c + (X) * 0xc0, (V))
-
-#define __get_MB93493_GPIO_IELH(X) __get_MB93493(0x3a0 + (X) * 0xc0)
-#define __set_MB93493_GPIO_IELH(X,V) __set_MB93493(0x3a0 + (X) * 0xc0, (V))
-
-#endif /* _ASM_MB93493_REGS_H */
diff --git a/arch/frv/include/asm/mem-layout.h b/arch/frv/include/asm/mem-layout.h
deleted file mode 100644
index e9a0ec85a402..000000000000
--- a/arch/frv/include/asm/mem-layout.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* mem-layout.h: memory layout
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MEM_LAYOUT_H
-#define _ASM_MEM_LAYOUT_H
-
-#ifndef __ASSEMBLY__
-#define __UL(X) ((unsigned long) (X))
-#else
-#define __UL(X) (X)
-#endif
-
-/*
- * PAGE_SHIFT determines the page size
- */
-#define PAGE_SHIFT 14
-
-#ifndef __ASSEMBLY__
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#else
-#define PAGE_SIZE (1 << PAGE_SHIFT)
-#endif
-
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-/*
- * the slab must be aligned such that load- and store-double instructions don't
- * fault if used
- */
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-#define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
-
-/*****************************************************************************/
-/*
- * virtual memory layout from kernel's point of view
- */
-#define PAGE_OFFSET ((unsigned long) &__page_offset)
-
-#ifdef CONFIG_MMU
-
-/* see Documentation/frv/mmu-layout.txt */
-#define KERNEL_LOWMEM_START __UL(0xc0000000)
-#define KERNEL_LOWMEM_END __UL(0xd0000000)
-#define VMALLOC_START __UL(0xd0000000)
-#define VMALLOC_END __UL(0xd8000000)
-#define PKMAP_BASE __UL(0xd8000000)
-#define PKMAP_END __UL(0xdc000000)
-#define KMAP_ATOMIC_SECONDARY_FRAME __UL(0xdc000000)
-#define KMAP_ATOMIC_PRIMARY_FRAME __UL(0xdd000000)
-
-#endif
-
-#define KERNEL_IO_START __UL(0xe0000000)
-
-
-/*****************************************************************************/
-/*
- * memory layout from userspace's point of view
- */
-#define BRK_BASE __UL(2 * 1024 * 1024 + PAGE_SIZE)
-#define STACK_TOP __UL(2 * 1024 * 1024)
-#define STACK_TOP_MAX __UL(0xc0000000)
-
-/* userspace process size */
-#ifdef CONFIG_MMU
-#define TASK_SIZE (PAGE_OFFSET)
-#else
-#define TASK_SIZE __UL(0xFFFFFFFFUL)
-#endif
-
-/* base of area at which unspecified mmaps will start */
-#ifdef CONFIG_BINFMT_ELF_FDPIC
-#define TASK_UNMAPPED_BASE __UL(16 * 1024 * 1024)
-#else
-#define TASK_UNMAPPED_BASE __UL(TASK_SIZE / 3)
-#endif
-
-#endif /* _ASM_MEM_LAYOUT_H */
diff --git a/arch/frv/include/asm/mmu.h b/arch/frv/include/asm/mmu.h
deleted file mode 100644
index 86ca0e86e7d2..000000000000
--- a/arch/frv/include/asm/mmu.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* mmu.h: memory management context for FR-V with or without MMU support
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_MMU_H
-#define _ASM_MMU_H
-
-typedef struct {
-#ifdef CONFIG_MMU
- struct list_head id_link; /* link in list of context ID owners */
- unsigned short id; /* MMU context ID */
- unsigned short id_busy; /* true if ID is in CXNR */
- unsigned long itlb_cached_pge; /* [SCR0] PGE cached for insn TLB handler */
- unsigned long itlb_ptd_mapping; /* [DAMR4] PTD mapping for itlb cached PGE */
- unsigned long dtlb_cached_pge; /* [SCR1] PGE cached for data TLB handler */
- unsigned long dtlb_ptd_mapping; /* [DAMR5] PTD mapping for dtlb cached PGE */
-
-#else
- unsigned long end_brk;
-
-#endif
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
- unsigned long exec_fdpic_loadmap;
- unsigned long interp_fdpic_loadmap;
-#endif
-
-} mm_context_t;
-
-#ifdef CONFIG_MMU
-extern int __nongpreldata cxn_pinned;
-extern int cxn_pin_by_pid(pid_t pid);
-#endif
-
-#endif /* _ASM_MMU_H */
diff --git a/arch/frv/include/asm/mmu_context.h b/arch/frv/include/asm/mmu_context.h
deleted file mode 100644
index c7daa395156a..000000000000
--- a/arch/frv/include/asm/mmu_context.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* mmu_context.h: MMU context management routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_MMU_CONTEXT_H
-#define _ASM_MMU_CONTEXT_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm-generic/mm_hooks.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-#ifdef CONFIG_MMU
-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void change_mm_context(mm_context_t *old, mm_context_t *ctx, pgd_t *_pgd);
-extern void destroy_context(struct mm_struct *mm);
-
-#else
-#define init_new_context(tsk, mm) ({ 0; })
-#define change_mm_context(old, ctx, _pml4) do {} while(0)
-#define destroy_context(mm) do {} while(0)
-#endif
-
-#define switch_mm(prev, next, tsk) \
-do { \
- if (prev != next) \
- change_mm_context(&prev->context, &next->context, next->pgd); \
-} while(0)
-
-#define activate_mm(prev, next) \
-do { \
- change_mm_context(&prev->context, &next->context, next->pgd); \
-} while(0)
-
-#define deactivate_mm(tsk, mm) \
-do { \
-} while(0)
-
-#endif
diff --git a/arch/frv/include/asm/module.h b/arch/frv/include/asm/module.h
deleted file mode 100644
index a8848f09a217..000000000000
--- a/arch/frv/include/asm/module.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* module.h: FRV module stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_MODULE_H
-#define _ASM_MODULE_H
-
-#include <asm-generic/module.h>
-
-/*
- * Include the architecture version.
- */
-#define MODULE_ARCH_VERMAGIC __stringify(PROCESSOR_MODEL_NAME) " "
-
-#endif /* _ASM_MODULE_H */
-
diff --git a/arch/frv/include/asm/page.h b/arch/frv/include/asm/page.h
deleted file mode 100644
index 0f76a0d586f6..000000000000
--- a/arch/frv/include/asm/page.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_PAGE_H
-#define _ASM_PAGE_H
-
-#include <asm/virtconvert.h>
-#include <asm/mem-layout.h>
-#include <asm/sections.h>
-#include <asm/setup.h>
-
-#ifndef __ASSEMBLY__
-
-#define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE)
-#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE)
-#define copy_user_page(vto, vfrom, vaddr, topg) memcpy((vto), (vfrom), PAGE_SIZE)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long ste[64];} pmd_t;
-typedef struct { pmd_t pue[1]; } pud_t;
-typedef struct { pud_t pge[1]; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x) ((x).pte)
-#define pmd_val(x) ((x).ste[0])
-#define pud_val(x) ((x).pue[0])
-#define pgd_val(x) ((x).pge[0])
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pmd(x) ((pmd_t) { { (x) } } )
-#define __pud(x) ((pud_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-#define PTE_MASK PAGE_MASK
-
-#define devmem_is_allowed(pfn) 1
-
-#define __pa(vaddr) virt_to_phys((void *) (unsigned long) (vaddr))
-#define __va(paddr) phys_to_virt((unsigned long) (paddr))
-
-#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
-
-extern unsigned long max_low_pfn;
-extern unsigned long min_low_pfn;
-extern unsigned long max_pfn;
-
-#ifdef CONFIG_MMU
-#define pfn_valid(pfn) ((pfn) < max_mapnr)
-#else
-#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT)
-#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
-
-#endif
-
-#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | \
- ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* _ASM_PAGE_H */
diff --git a/arch/frv/include/asm/pci.h b/arch/frv/include/asm/pci.h
deleted file mode 100644
index 895af9d558ba..000000000000
--- a/arch/frv/include/asm/pci.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* pci.h: FR-V specific PCI declarations
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-m68k/pci.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_FRV_PCI_H
-#define _ASM_FRV_PCI_H
-
-#include <linux/mm.h>
-#include <linux/scatterlist.h>
-#include <asm-generic/pci.h>
-
-#define pcibios_assign_all_busses() 0
-
-#ifdef CONFIG_MMU
-extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
-extern void consistent_free(void *vaddr);
-extern void consistent_sync(void *vaddr, size_t size, int direction);
-extern void consistent_sync_page(struct page *page, unsigned long offset,
- size_t size, int direction);
-#endif
-
-/* Return the index of the PCI controller for device PDEV. */
-#define pci_controller_num(PDEV) (0)
-
-/*
- * These are pretty much arbitrary with the CoMEM implementation.
- * We have the whole address space to ourselves.
- */
-#define PCIBIOS_MIN_IO 0x100
-#define PCIBIOS_MIN_MEM 0x00010000
-
-#endif /* _ASM_FRV_PCI_H */
diff --git a/arch/frv/include/asm/percpu.h b/arch/frv/include/asm/percpu.h
deleted file mode 100644
index 4209fe5fe0a2..000000000000
--- a/arch/frv/include/asm/percpu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_PERCPU_H
-#define __ASM_PERCPU_H
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ASM_PERCPU_H */
diff --git a/arch/frv/include/asm/perf_event.h b/arch/frv/include/asm/perf_event.h
deleted file mode 100644
index c52ea5546b5b..000000000000
--- a/arch/frv/include/asm/perf_event.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* FRV performance event support
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_PERF_EVENT_H
-#define _ASM_PERF_EVENT_H
-
-#endif /* _ASM_PERF_EVENT_H */
diff --git a/arch/frv/include/asm/pgalloc.h b/arch/frv/include/asm/pgalloc.h
deleted file mode 100644
index 416d19a632f2..000000000000
--- a/arch/frv/include/asm/pgalloc.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* pgalloc.h: Page allocation routines for FRV
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Derived from:
- * include/asm-m68knommu/pgalloc.h
- * include/asm-i386/pgalloc.h
- */
-#ifndef _ASM_PGALLOC_H
-#define _ASM_PGALLOC_H
-
-#include <asm/setup.h>
-#include <asm/virtconvert.h>
-
-#ifdef CONFIG_MMU
-
-#define pmd_populate_kernel(mm, pmd, pte) __set_pmd(pmd, __pa(pte) | _PAGE_TABLE)
-#define pmd_populate(MM, PMD, PAGE) \
-do { \
- __set_pmd((PMD), page_to_pfn(PAGE) << PAGE_SHIFT | _PAGE_TABLE); \
-} while(0)
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-
-extern pgd_t *pgd_alloc(struct mm_struct *);
-extern void pgd_free(struct mm_struct *mm, pgd_t *);
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-
-extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long);
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-#define __pte_free_tlb(tlb,pte,address) \
-do { \
- pgtable_page_dtor(pte); \
- tlb_remove_page((tlb),(pte)); \
-} while (0)
-
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- * (In the PAE case we free the pmds as part of the pgd.)
- */
-#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *) 2); })
-#define pmd_free(mm, x) do { } while (0)
-#define __pmd_free_tlb(tlb,x,a) do { } while (0)
-
-#endif /* CONFIG_MMU */
-
-#endif /* _ASM_PGALLOC_H */
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h
deleted file mode 100644
index ab6e7e961b54..000000000000
--- a/arch/frv/include/asm/pgtable.h
+++ /dev/null
@@ -1,528 +0,0 @@
-/* pgtable.h: FR-V page table mangling
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Derived from:
- * include/asm-m68knommu/pgtable.h
- * include/asm-i386/pgtable.h
- */
-
-#ifndef _ASM_PGTABLE_H
-#define _ASM_PGTABLE_H
-
-#include <asm-generic/5level-fixup.h>
-#include <asm/mem-layout.h>
-#include <asm/setup.h>
-#include <asm/processor.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/threads.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-struct vm_area_struct;
-#endif
-
-#ifndef __ASSEMBLY__
-#if defined(CONFIG_HIGHPTE)
-typedef unsigned long pte_addr_t;
-#else
-typedef pte_t *pte_addr_t;
-#endif
-#endif
-
-/*****************************************************************************/
-/*
- * MMU-less operation case first
- */
-#ifndef CONFIG_MMU
-
-#define pgd_present(pgd) (1) /* pages are always present on NO_MM */
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr) (1)
-#define pmd_offset(a, b) ((void *) 0)
-
-#define PAGE_NONE __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_SHARED __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_COPY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_READONLY __pgprot(0) /* these mean nothing to NO_MM */
-#define PAGE_KERNEL __pgprot(0) /* these mean nothing to NO_MM */
-
-#define __swp_type(x) (0)
-#define __swp_offset(x) (0)
-#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define ZERO_PAGE(vaddr) ({ BUG(); NULL; })
-
-#define swapper_pg_dir ((pgd_t *) NULL)
-
-#define pgtable_cache_init() do {} while (0)
-
-#include <asm-generic/pgtable.h>
-
-#else /* !CONFIG_MMU */
-/*****************************************************************************/
-/*
- * then MMU operation
- */
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#ifndef __ASSEMBLY__
-extern unsigned long empty_zero_page;
-#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
-#endif
-
-/*
- * we use 2-level page tables, folding the PMD (mid-level table) into the PGE (top-level entry)
- * [see Documentation/frv/mmu-layout.txt]
- *
- * Page Directory:
- * - Size: 16KB
- * - 64 PGEs per PGD
- * - Each PGE holds 1 PUD and covers 64MB
- *
- * Page Upper Directory:
- * - Size: 256B
- * - 1 PUE per PUD
- * - Each PUE holds 1 PMD and covers 64MB
- *
- * Page Mid-Level Directory
- * - Size: 256B
- * - 1 PME per PMD
- * - Each PME holds 64 STEs, all of which point to separate chunks of the same Page Table
- * - All STEs are instantiated at the same time
- *
- * Page Table
- * - Size: 16KB
- * - 4096 PTEs per PT
- * - Each Linux PT is subdivided into 64 FR451 PT's, each of which holds 64 entries
- *
- * Pages
- * - Size: 4KB
- *
- * total PTEs
- * = 1 PML4E * 64 PGEs * 1 PUEs * 1 PMEs * 4096 PTEs
- * = 1 PML4E * 64 PGEs * 64 STEs * 64 PTEs/FR451-PT
- * = 262144 (or 256 * 1024)
- */
-#define PGDIR_SHIFT 26
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-#define PTRS_PER_PGD 64
-
-#define __PAGETABLE_PUD_FOLDED
-#define PUD_SHIFT 26
-#define PTRS_PER_PUD 1
-#define PUD_SIZE (1UL << PUD_SHIFT)
-#define PUD_MASK (~(PUD_SIZE - 1))
-#define PUE_SIZE 256
-
-#define __PAGETABLE_PMD_FOLDED
-#define PMD_SHIFT 26
-#define PMD_SIZE (1UL << PMD_SHIFT)
-#define PMD_MASK (~(PMD_SIZE - 1))
-#define PTRS_PER_PMD 1
-#define PME_SIZE 256
-
-#define __frv_PT_SIZE 256
-
-#define PTRS_PER_PTE 4096
-
-#define USER_PGDS_IN_LAST_PML4 (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD - USER_PGD_PTRS)
-
-#define TWOLEVEL_PGDIR_SHIFT 26
-#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
-#define BOOT_KERNEL_PGD_PTRS (PTRS_PER_PGD - BOOT_USER_PGD_PTRS)
-
-#ifndef __ASSEMBLY__
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
-#define pte_ERROR(e) \
- printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte)
-#define pmd_ERROR(e) \
- printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pud_ERROR(e) \
- printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pmd_val(pud_val(e)))
-#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pmd_val(pud_val(pgd_val(e))))
-
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) \
-do { \
- *(pteptr) = (pteval); \
- asm volatile("dcf %M0" :: "U"(*pteptr)); \
-} while(0)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * pgd_offset() returns a (pgd_t *)
- * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
- */
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/*
- * a shortcut which implies the use of the kernel's pgd, instead
- * of a process's
- */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pud is never bad, and a pud always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd) { return 0; }
-static inline int pgd_bad(pgd_t pgd) { return 0; }
-static inline int pgd_present(pgd_t pgd) { return 1; }
-static inline void pgd_clear(pgd_t *pgd) { }
-
-#define pgd_populate(mm, pgd, pud) do { } while (0)
-/*
- * (puds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pgd(pgdptr, pgdval) \
-do { \
- memcpy((pgdptr), &(pgdval), sizeof(pgd_t)); \
- asm volatile("dcf %M0" :: "U"(*(pgdptr))); \
-} while(0)
-
-static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
-{
- return (pud_t *) pgd;
-}
-
-#define pgd_page(pgd) (pud_page((pud_t){ pgd }))
-#define pgd_page_vaddr(pgd) (pud_page_vaddr((pud_t){ pgd }))
-
-/*
- * allocating and freeing a pud is trivial: the 1-entry pud is
- * inside the pgd, so has no extra memory associated with it.
- */
-#define pud_alloc_one(mm, address) NULL
-#define pud_free(mm, x) do { } while (0)
-#define __pud_free_tlb(tlb, x, address) do { } while (0)
-
-/*
- * The "pud_xxx()" functions here are trivial for a folded two-level
- * setup: the pmd is never bad, and a pmd always exists (as it's folded
- * into the pud entry)
- */
-static inline int pud_none(pud_t pud) { return 0; }
-static inline int pud_bad(pud_t pud) { return 0; }
-static inline int pud_present(pud_t pud) { return 1; }
-static inline void pud_clear(pud_t *pud) { }
-
-#define pud_populate(mm, pmd, pte) do { } while (0)
-
-/*
- * (pmds are folded into puds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pud(pudptr, pudval) set_pmd((pmd_t *)(pudptr), (pmd_t) { pudval })
-
-#define pud_page(pud) (pmd_page((pmd_t){ pud }))
-#define pud_page_vaddr(pud) (pmd_page_vaddr((pmd_t){ pud }))
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-extern void __set_pmd(pmd_t *pmdptr, unsigned long __pmd);
-
-#define set_pmd(pmdptr, pmdval) \
-do { \
- __set_pmd((pmdptr), (pmdval).ste[0]); \
-} while(0)
-
-#define __pmd_index(address) 0
-
-static inline pmd_t *pmd_offset(pud_t *dir, unsigned long address)
-{
- return (pmd_t *) dir + __pmd_index(address);
-}
-
-#define pte_same(a, b) ((a).pte == (b).pte)
-#define pte_page(x) (mem_map + ((unsigned long)(((x).pte >> PAGE_SHIFT))))
-#define pte_none(x) (!(x).pte)
-#define pte_pfn(x) ((unsigned long)(((x).pte >> PAGE_SHIFT)))
-#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#define VMALLOC_VMADDR(x) ((unsigned long) (x))
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * control flags in AMPR registers and TLB entries
- */
-#define _PAGE_BIT_PRESENT xAMPRx_V_BIT
-#define _PAGE_BIT_WP DAMPRx_WP_BIT
-#define _PAGE_BIT_NOCACHE xAMPRx_C_BIT
-#define _PAGE_BIT_SUPER xAMPRx_S_BIT
-#define _PAGE_BIT_ACCESSED xAMPRx_RESERVED8_BIT
-#define _PAGE_BIT_DIRTY xAMPRx_M_BIT
-#define _PAGE_BIT_NOTGLOBAL xAMPRx_NG_BIT
-
-#define _PAGE_PRESENT xAMPRx_V
-#define _PAGE_WP DAMPRx_WP
-#define _PAGE_NOCACHE xAMPRx_C
-#define _PAGE_SUPER xAMPRx_S
-#define _PAGE_ACCESSED xAMPRx_RESERVED8 /* accessed if set */
-#define _PAGE_DIRTY xAMPRx_M
-#define _PAGE_NOTGLOBAL xAMPRx_NG
-
-#define _PAGE_RESERVED_MASK (xAMPRx_RESERVED8 | xAMPRx_RESERVED13)
-
-#define _PAGE_PROTNONE 0x000 /* If not present */
-
-#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-#define __PGPROT_BASE \
- (_PAGE_PRESENT | xAMPRx_SS_16Kb | xAMPRx_D | _PAGE_NOTGLOBAL | _PAGE_ACCESSED)
-
-#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
-#define PAGE_SHARED __pgprot(__PGPROT_BASE)
-#define PAGE_COPY __pgprot(__PGPROT_BASE | _PAGE_WP)
-#define PAGE_READONLY __pgprot(__PGPROT_BASE | _PAGE_WP)
-
-#define __PAGE_KERNEL (__PGPROT_BASE | _PAGE_SUPER | _PAGE_DIRTY)
-#define __PAGE_KERNEL_NOCACHE (__PGPROT_BASE | _PAGE_SUPER | _PAGE_DIRTY | _PAGE_NOCACHE)
-#define __PAGE_KERNEL_RO (__PGPROT_BASE | _PAGE_SUPER | _PAGE_DIRTY | _PAGE_WP)
-
-#define MAKE_GLOBAL(x) __pgprot((x) & ~_PAGE_NOTGLOBAL)
-
-#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
-#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
-#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
-
-#define _PAGE_TABLE (_PAGE_PRESENT | xAMPRx_SS_16Kb)
-
-#ifndef __ASSEMBLY__
-
-/*
- * The FR451 can do execute protection by virtue of having separate TLB miss handlers for
- * instruction access and for data access. However, we don't have enough reserved bits to say
- * "execute only", so we don't bother. If you can read it, you can execute it and vice versa.
- */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY
-#define __P101 PAGE_READONLY
-#define __P110 PAGE_COPY
-#define __P111 PAGE_COPY
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY
-#define __S101 PAGE_READONLY
-#define __S110 PAGE_SHARED
-#define __S111 PAGE_SHARED
-
-/*
- * Define this to warn about kernel memory accesses that are
- * done without a 'access_ok(VERIFY_WRITE,..)'
- */
-#undef TEST_ACCESS_OK
-
-#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
-#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_bad(x) (pmd_val(x) & xAMPRx_SS)
-#define pmd_clear(xp) do { __set_pmd(xp, 0); } while(0)
-
-#define pmd_page_vaddr(pmd) \
- ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#endif
-
-#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_dirty(pte_t pte) { return (pte).pte & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte) { return (pte).pte & _PAGE_ACCESSED; }
-static inline int pte_write(pte_t pte) { return !((pte).pte & _PAGE_WP); }
-static inline int pte_special(pte_t pte) { return 0; }
-
-static inline pte_t pte_mkclean(pte_t pte) { (pte).pte &= ~_PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkold(pte_t pte) { (pte).pte &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte |= _PAGE_WP; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte &= ~_PAGE_WP; return pte; }
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-
-static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
-{
- int i = test_and_clear_bit(_PAGE_BIT_ACCESSED, ptep);
- asm volatile("dcf %M0" :: "U"(*ptep));
- return i;
-}
-
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
- unsigned long x = xchg(&ptep->pte, 0);
- asm volatile("dcf %M0" :: "U"(*ptep));
- return __pte(x);
-}
-
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
- set_bit(_PAGE_BIT_WP, ptep);
- asm volatile("dcf %M0" :: "U"(*ptep));
-}
-
-/*
- * Macro to mark a page protection value as "uncacheable"
- */
-#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE))
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-#define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
-
-/* This takes a physical page address that is used by the remapping functions */
-#define mk_pte_phys(physpage, pgprot) pfn_pte((physpage) >> PAGE_SHIFT, pgprot)
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- pte.pte &= _PAGE_CHG_MASK;
- pte.pte |= pgprot_val(newprot);
- return pte;
-}
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-#define pgd_index_k(addr) pgd_index(addr)
-
-/* Find an entry in the bottom-level page table.. */
-#define __pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-
-/*
- * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
- *
- * this macro returns the index of the entry in the pte page which would
- * control the given virtual address
- */
-#define pte_index(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
-
-#if defined(CONFIG_HIGHPTE)
-#define pte_offset_map(dir, address) \
- ((pte_t *)kmap_atomic(pmd_page(*(dir))) + pte_index(address))
-#define pte_unmap(pte) kunmap_atomic(pte)
-#else
-#define pte_offset_map(dir, address) \
- ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
-#define pte_unmap(pte) do { } while (0)
-#endif
-
-/*
- * Handle swap and file entries
- * - the PTE is encoded in the following format:
- * bit 0: Must be 0 (!_PAGE_PRESENT)
- * bits 1-6: Swap type
- * bits 7-31: Swap offset
- */
-#define __swp_type(x) (((x).val >> 1) & 0x1f)
-#define __swp_offset(x) ((x).val >> 7)
-#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 7) })
-#define __pte_to_swp_entry(_pte) ((swp_entry_t) { (_pte).pte })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define PageSkip(page) (0)
-#define kern_addr_valid(addr) (1)
-
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define __HAVE_ARCH_PTE_SAME
-#include <asm-generic/pgtable.h>
-
-/*
- * preload information about a newly instantiated PTE into the SCR0/SCR1 PGE cache
- */
-static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
-{
- struct mm_struct *mm;
- unsigned long ampr;
-
- mm = current->mm;
- if (mm) {
- pgd_t *pge = pgd_offset(mm, address);
- pud_t *pue = pud_offset(pge, address);
- pmd_t *pme = pmd_offset(pue, address);
-
- ampr = pme->ste[0] & 0xffffff00;
- ampr |= xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C |
- xAMPRx_V;
- } else {
- address = ULONG_MAX;
- ampr = 0;
- }
-
- asm volatile("movgs %0,scr0\n"
- "movgs %0,scr1\n"
- "movgs %1,dampr4\n"
- "movgs %1,dampr5\n"
- :
- : "r"(address), "r"(ampr)
- );
-}
-
-#ifdef CONFIG_PROC_FS
-extern char *proc_pid_status_frv_cxnr(struct mm_struct *mm, char *buffer);
-#endif
-
-extern void __init pgtable_cache_init(void);
-
-#endif /* !__ASSEMBLY__ */
-#endif /* !CONFIG_MMU */
-
-#ifndef __ASSEMBLY__
-extern void __init paging_init(void);
-#endif /* !__ASSEMBLY__ */
-#define HAVE_ARCH_UNMAPPED_AREA
-
-#endif /* _ASM_PGTABLE_H */
diff --git a/arch/frv/include/asm/processor.h b/arch/frv/include/asm/processor.h
deleted file mode 100644
index 021cce78b401..000000000000
--- a/arch/frv/include/asm/processor.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* processor.h: FRV processor definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROCESSOR_H
-#define _ASM_PROCESSOR_H
-
-#include <asm/mem-layout.h>
-
-#ifndef __ASSEMBLY__
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <asm/sections.h>
-#include <asm/segment.h>
-#include <asm/fpu.h>
-#include <asm/registers.h>
-#include <asm/ptrace.h>
-#include <asm/current.h>
-#include <asm/cache.h>
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/*
- * Bus types
- */
-#define EISA_bus 0
-
-struct thread_struct {
- struct pt_regs *frame; /* [GR28] exception frame ptr for this thread */
- struct task_struct *curr; /* [GR29] current pointer for this thread */
- unsigned long sp; /* [GR1 ] kernel stack pointer */
- unsigned long fp; /* [GR2 ] kernel frame pointer */
- unsigned long lr; /* link register */
- unsigned long pc; /* program counter */
- unsigned long gr[12]; /* [GR16-GR27] */
- unsigned long sched_lr; /* LR from schedule() */
-
- union {
- struct pt_regs *frame0; /* top (user) stack frame */
- struct user_context *user; /* userspace context */
- };
-} __attribute__((aligned(8)));
-
-extern struct pt_regs *__kernel_frame0_ptr;
-extern struct task_struct *__kernel_current_task;
-
-#endif
-
-#ifndef __ASSEMBLY__
-#define INIT_THREAD_FRAME0 \
- ((struct pt_regs *) \
- (sizeof(init_stack) + (unsigned long) init_stack - sizeof(struct user_context)))
-
-#define INIT_THREAD { \
- NULL, \
- (struct task_struct *) init_stack, \
- 0, 0, 0, 0, \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
- 0, \
- { INIT_THREAD_FRAME0 }, \
-}
-
-/*
- * do necessary setup to start up a newly executed thread.
- */
-#define start_thread(_regs, _pc, _usp) \
-do { \
- _regs->pc = (_pc); \
- _regs->psr &= ~PSR_S; \
- _regs->sp = (_usp); \
-} while(0)
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-extern asmlinkage void save_user_regs(struct user_context *target);
-extern asmlinkage void *restore_user_regs(const struct user_context *target, ...);
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) ((tsk)->thread.frame0->pc)
-#define KSTK_ESP(tsk) ((tsk)->thread.frame0->sp)
-
-#define cpu_relax() barrier()
-
-/* data cache prefetch */
-#define ARCH_HAS_PREFETCH
-static inline void prefetch(const void *x)
-{
- asm volatile("dcpl %0,gr0,#0" : : "r"(x));
-}
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_PROCESSOR_H */
diff --git a/arch/frv/include/asm/ptrace.h b/arch/frv/include/asm/ptrace.h
deleted file mode 100644
index 034f17934192..000000000000
--- a/arch/frv/include/asm/ptrace.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* ptrace.h: ptrace() relevant definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_PTRACE_H
-#define _ASM_PTRACE_H
-
-#include <asm/irq_regs.h>
-#include <uapi/asm/ptrace.h>
-
-#define in_syscall(regs) (((regs)->tbr & TBR_TT) == TBR_TT_TRAP0)
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/*
- * we dedicate GR28 to keeping a pointer to the current exception frame
- * - gr28 is destroyed on entry to the kernel from userspace
- */
-register struct pt_regs *__frame asm("gr28");
-
-#define user_mode(regs) (!((regs)->psr & PSR_S))
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_stack_pointer(regs) ((regs)->sp)
-#define current_pt_regs() (__frame)
-
-extern unsigned long user_stack(const struct pt_regs *);
-#define profile_pc(regs) ((regs)->pc)
-
-#define task_pt_regs(task) ((task)->thread.frame0)
-
-#define arch_has_single_step() (1)
-
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_PTRACE_H */
diff --git a/arch/frv/include/asm/sections.h b/arch/frv/include/asm/sections.h
deleted file mode 100644
index d03fb64e93e9..000000000000
--- a/arch/frv/include/asm/sections.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* sections.h: linkage layout variables
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SECTIONS_H
-#define _ASM_SECTIONS_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <asm-generic/sections.h>
-
-#ifdef __KERNEL__
-
-/*
- * we don't want to put variables in the GP-REL section if they're not used very much - that would
- * be waste since GP-REL addressing is limited to GP16+/-2048
- */
-#define __nongpreldata __attribute__((section(".data")))
-#define __nongprelbss __attribute__((section(".bss")))
-
-/*
- * linker symbols
- */
-extern const void __kernel_image_start, __kernel_image_end, __page_offset;
-
-extern unsigned long __nongprelbss memory_start;
-extern unsigned long __nongprelbss memory_end;
-extern unsigned long __nongprelbss rom_length;
-
-#endif
-#endif
-#endif /* _ASM_SECTIONS_H */
diff --git a/arch/frv/include/asm/segment.h b/arch/frv/include/asm/segment.h
deleted file mode 100644
index 2305142d4cf8..000000000000
--- a/arch/frv/include/asm/segment.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* segment.h: MMU segment settings
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SEGMENT_H
-#define _ASM_SEGMENT_H
-
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-#ifdef CONFIG_MMU
-#define USER_DS MAKE_MM_SEG(TASK_SIZE - 1)
-#define KERNEL_DS MAKE_MM_SEG(0xdfffffffUL)
-#else
-#define USER_DS MAKE_MM_SEG(memory_end)
-#define KERNEL_DS MAKE_MM_SEG(0xe0000000UL)
-#endif
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (__current_thread_info->addr_limit)
-#define segment_eq(a, b) ((a).seg == (b).seg)
-#define get_addr_limit() (get_fs().seg)
-
-#define set_fs(_x) \
-do { \
- __current_thread_info->addr_limit = (_x); \
-} while(0)
-
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_SEGMENT_H */
diff --git a/arch/frv/include/asm/serial-regs.h b/arch/frv/include/asm/serial-regs.h
deleted file mode 100644
index e1286bda00eb..000000000000
--- a/arch/frv/include/asm/serial-regs.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* serial-regs.h: serial port registers
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SERIAL_REGS_H
-#define _ASM_SERIAL_REGS_H
-
-#include <linux/serial_reg.h>
-#include <asm/irc-regs.h>
-
-#define SERIAL_ICLK 33333333 /* the target serial input clock */
-#define UART0_BASE 0xfeff9c00
-#define UART1_BASE 0xfeff9c40
-
-#define __get_UART0(R) ({ __reg(UART0_BASE + (R) * 8) >> 24; })
-#define __get_UART1(R) ({ __reg(UART1_BASE + (R) * 8) >> 24; })
-#define __set_UART0(R,V) do { __reg(UART0_BASE + (R) * 8) = (V) << 24; } while(0)
-#define __set_UART1(R,V) do { __reg(UART1_BASE + (R) * 8) = (V) << 24; } while(0)
-
-#define __get_UART0_LSR() ({ __get_UART0(UART_LSR); })
-#define __get_UART1_LSR() ({ __get_UART1(UART_LSR); })
-
-#define __set_UART0_IER(V) __set_UART0(UART_IER,(V))
-#define __set_UART1_IER(V) __set_UART1(UART_IER,(V))
-
-/* serial prescaler select register */
-#define __get_UCPSR() ({ *(volatile unsigned long *)(0xfeff9c90); })
-#define __set_UCPSR(V) do { *(volatile unsigned long *)(0xfeff9c90) = (V); } while(0)
-#define UCPSR_SELECT0 0x07000000
-#define UCPSR_SELECT1 0x38000000
-
-/* serial prescaler base value register */
-#define __get_UCPVR() ({ *(volatile unsigned long *)(0xfeff9c98); mb(); })
-#define __set_UCPVR(V) do { *(volatile unsigned long *)(0xfeff9c98) = (V) << 24; mb(); } while(0)
-
-
-#endif /* _ASM_SERIAL_REGS_H */
diff --git a/arch/frv/include/asm/serial.h b/arch/frv/include/asm/serial.h
deleted file mode 100644
index 614c6d76789a..000000000000
--- a/arch/frv/include/asm/serial.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * serial.h
- *
- * Copyright (C) 2003 Develer S.r.l. (http://www.develer.com/)
- * Author: Bernardo Innocenti <bernie@codewiz.org>
- *
- * Based on linux/include/asm-i386/serial.h
- */
-#include <asm/serial-regs.h>
-
-/*
- * the base baud is derived from the clock speed and so is variable
- */
-#define BASE_BAUD 0
diff --git a/arch/frv/include/asm/setup.h b/arch/frv/include/asm/setup.h
deleted file mode 100644
index aa76f2eac09a..000000000000
--- a/arch/frv/include/asm/setup.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* setup.h: setup stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_SETUP_H
-#define _ASM_SETUP_H
-
-
-#include <linux/init.h>
-#include <uapi/asm/setup.h>
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_MMU
-extern unsigned long __initdata num_mappedpages;
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_SETUP_H */
diff --git a/arch/frv/include/asm/shmparam.h b/arch/frv/include/asm/shmparam.h
deleted file mode 100644
index 50ea51f26c46..000000000000
--- a/arch/frv/include/asm/shmparam.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SHMPARAM_H
-#define _ASM_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
-
-#endif /* _ASM_SHMPARAM_H */
-
diff --git a/arch/frv/include/asm/signal.h b/arch/frv/include/asm/signal.h
deleted file mode 100644
index 796394113904..000000000000
--- a/arch/frv/include/asm/signal.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SIGNAL_H
-#define _ASM_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-#endif /* _ASM_SIGNAL_H */
diff --git a/arch/frv/include/asm/smp.h b/arch/frv/include/asm/smp.h
deleted file mode 100644
index 0d7fa409312d..000000000000
--- a/arch/frv/include/asm/smp.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_SMP_H
-#define __ASM_SMP_H
-
-
-#ifdef CONFIG_SMP
-#error SMP not supported
-#endif
-
-#endif
diff --git a/arch/frv/include/asm/spinlock.h b/arch/frv/include/asm/spinlock.h
deleted file mode 100644
index fe385f45d1fd..000000000000
--- a/arch/frv/include/asm/spinlock.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* spinlock.h: spinlocks for FR-V
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SPINLOCK_H
-#define _ASM_SPINLOCK_H
-
-#error no spinlocks for FR-V yet
-
-#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/frv/include/asm/spr-regs.h b/arch/frv/include/asm/spr-regs.h
deleted file mode 100644
index d3883021f236..000000000000
--- a/arch/frv/include/asm/spr-regs.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/* spr-regs.h: special-purpose registers on the FRV
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SPR_REGS_H
-#define _ASM_SPR_REGS_H
-
-/*
- * PSR - Processor Status Register
- */
-#define PSR_ET 0x00000001 /* enable interrupts/exceptions flag */
-#define PSR_PS 0x00000002 /* previous supervisor mode flag */
-#define PSR_S 0x00000004 /* supervisor mode flag */
-#define PSR_PIL 0x00000078 /* processor external interrupt level */
-#define PSR_PIL_0 0x00000000 /* - no interrupt in progress */
-#define PSR_PIL_13 0x00000068 /* - debugging only */
-#define PSR_PIL_14 0x00000070 /* - debugging in progress */
-#define PSR_PIL_15 0x00000078 /* - NMI in progress */
-#define PSR_EM 0x00000080 /* enable media operation */
-#define PSR_EF 0x00000100 /* enable FPU operation */
-#define PSR_BE 0x00001000 /* endianness mode */
-#define PSR_BE_LE 0x00000000 /* - little endian mode */
-#define PSR_BE_BE 0x00001000 /* - big endian mode */
-#define PSR_CM 0x00002000 /* conditional mode */
-#define PSR_NEM 0x00004000 /* non-excepting mode */
-#define PSR_ICE 0x00010000 /* in-circuit emulation mode */
-#define PSR_VERSION_SHIFT 24 /* CPU silicon ID */
-#define PSR_IMPLE_SHIFT 28 /* CPU core ID */
-
-#define PSR_VERSION(psr) (((psr) >> PSR_VERSION_SHIFT) & 0xf)
-#define PSR_IMPLE(psr) (((psr) >> PSR_IMPLE_SHIFT) & 0xf)
-
-#define PSR_IMPLE_FR401 0x2
-#define PSR_VERSION_FR401_MB93401 0x0
-#define PSR_VERSION_FR401_MB93401A 0x1
-#define PSR_VERSION_FR401_MB93403 0x2
-
-#define PSR_IMPLE_FR405 0x4
-#define PSR_VERSION_FR405_MB93405 0x0
-
-#define PSR_IMPLE_FR451 0x5
-#define PSR_VERSION_FR451_MB93451 0x0
-
-#define PSR_IMPLE_FR501 0x1
-#define PSR_VERSION_FR501_MB93501 0x1
-#define PSR_VERSION_FR501_MB93501A 0x2
-
-#define PSR_IMPLE_FR551 0x3
-#define PSR_VERSION_FR551_MB93555 0x1
-
-#define __get_PSR() ({ unsigned long x; asm volatile("movsg psr,%0" : "=r"(x)); x; })
-#define __set_PSR(V) do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0)
-
-/*
- * TBR - Trap Base Register
- */
-#define TBR_TT 0x00000ff0
-#define TBR_TT_INSTR_MMU_MISS (0x01 << 4)
-#define TBR_TT_INSTR_ACC_ERROR (0x02 << 4)
-#define TBR_TT_INSTR_ACC_EXCEP (0x03 << 4)
-#define TBR_TT_PRIV_INSTR (0x06 << 4)
-#define TBR_TT_ILLEGAL_INSTR (0x07 << 4)
-#define TBR_TT_FP_EXCEPTION (0x0d << 4)
-#define TBR_TT_MP_EXCEPTION (0x0e << 4)
-#define TBR_TT_DATA_ACC_ERROR (0x11 << 4)
-#define TBR_TT_DATA_MMU_MISS (0x12 << 4)
-#define TBR_TT_DATA_ACC_EXCEP (0x13 << 4)
-#define TBR_TT_DATA_STR_ERROR (0x14 << 4)
-#define TBR_TT_DIVISION_EXCEP (0x17 << 4)
-#define TBR_TT_COMMIT_EXCEP (0x19 << 4)
-#define TBR_TT_INSTR_TLB_MISS (0x1a << 4)
-#define TBR_TT_DATA_TLB_MISS (0x1b << 4)
-#define TBR_TT_DATA_DAT_EXCEP (0x1d << 4)
-#define TBR_TT_DECREMENT_TIMER (0x1f << 4)
-#define TBR_TT_COMPOUND_EXCEP (0x20 << 4)
-#define TBR_TT_INTERRUPT_1 (0x21 << 4)
-#define TBR_TT_INTERRUPT_2 (0x22 << 4)
-#define TBR_TT_INTERRUPT_3 (0x23 << 4)
-#define TBR_TT_INTERRUPT_4 (0x24 << 4)
-#define TBR_TT_INTERRUPT_5 (0x25 << 4)
-#define TBR_TT_INTERRUPT_6 (0x26 << 4)
-#define TBR_TT_INTERRUPT_7 (0x27 << 4)
-#define TBR_TT_INTERRUPT_8 (0x28 << 4)
-#define TBR_TT_INTERRUPT_9 (0x29 << 4)
-#define TBR_TT_INTERRUPT_10 (0x2a << 4)
-#define TBR_TT_INTERRUPT_11 (0x2b << 4)
-#define TBR_TT_INTERRUPT_12 (0x2c << 4)
-#define TBR_TT_INTERRUPT_13 (0x2d << 4)
-#define TBR_TT_INTERRUPT_14 (0x2e << 4)
-#define TBR_TT_INTERRUPT_15 (0x2f << 4)
-#define TBR_TT_TRAP0 (0x80 << 4)
-#define TBR_TT_TRAP1 (0x81 << 4)
-#define TBR_TT_TRAP2 (0x82 << 4)
-#define TBR_TT_TRAP3 (0x83 << 4)
-#define TBR_TT_TRAP120 (0xf8 << 4)
-#define TBR_TT_TRAP121 (0xf9 << 4)
-#define TBR_TT_TRAP122 (0xfa << 4)
-#define TBR_TT_TRAP123 (0xfb << 4)
-#define TBR_TT_TRAP124 (0xfc << 4)
-#define TBR_TT_TRAP125 (0xfd << 4)
-#define TBR_TT_TRAP126 (0xfe << 4)
-#define TBR_TT_BREAK (0xff << 4)
-
-#define TBR_TT_ATOMIC_CMPXCHG32 TBR_TT_TRAP120
-#define TBR_TT_ATOMIC_XCHG32 TBR_TT_TRAP121
-#define TBR_TT_ATOMIC_XOR TBR_TT_TRAP122
-#define TBR_TT_ATOMIC_OR TBR_TT_TRAP123
-#define TBR_TT_ATOMIC_AND TBR_TT_TRAP124
-#define TBR_TT_ATOMIC_SUB TBR_TT_TRAP125
-#define TBR_TT_ATOMIC_ADD TBR_TT_TRAP126
-
-#define __get_TBR() ({ unsigned long x; asm volatile("movsg tbr,%0" : "=r"(x)); x; })
-
-/*
- * HSR0 - Hardware Status Register 0
- */
-#define HSR0_PDM 0x00000007 /* power down mode */
-#define HSR0_PDM_NORMAL 0x00000000 /* - normal mode */
-#define HSR0_PDM_CORE_SLEEP 0x00000001 /* - CPU core sleep mode */
-#define HSR0_PDM_BUS_SLEEP 0x00000003 /* - bus sleep mode */
-#define HSR0_PDM_PLL_RUN 0x00000005 /* - PLL run */
-#define HSR0_PDM_PLL_STOP 0x00000007 /* - PLL stop */
-#define HSR0_GRLE 0x00000040 /* GR lower register set enable */
-#define HSR0_GRHE 0x00000080 /* GR higher register set enable */
-#define HSR0_FRLE 0x00000100 /* FR lower register set enable */
-#define HSR0_FRHE 0x00000200 /* FR higher register set enable */
-#define HSR0_GRN 0x00000400 /* GR quantity */
-#define HSR0_GRN_64 0x00000000 /* - 64 GR registers */
-#define HSR0_GRN_32 0x00000400 /* - 32 GR registers */
-#define HSR0_FRN 0x00000800 /* FR quantity */
-#define HSR0_FRN_64 0x00000000 /* - 64 FR registers */
-#define HSR0_FRN_32 0x00000800 /* - 32 FR registers */
-#define HSR0_SA 0x00001000 /* start address (RAMBOOT#) */
-#define HSR0_ETMI 0x00008000 /* enable TIMERI (64-bit up timer) */
-#define HSR0_ETMD 0x00004000 /* enable TIMERD (32-bit down timer) */
-#define HSR0_PEDAT 0x00010000 /* previous DAT mode */
-#define HSR0_XEDAT 0x00020000 /* exception DAT mode */
-#define HSR0_EDAT 0x00080000 /* enable DAT mode */
-#define HSR0_RME 0x00400000 /* enable RAM mode */
-#define HSR0_EMEM 0x00800000 /* enable MMU_Miss mask */
-#define HSR0_EXMMU 0x01000000 /* enable extended MMU mode */
-#define HSR0_EDMMU 0x02000000 /* enable data MMU */
-#define HSR0_EIMMU 0x04000000 /* enable instruction MMU */
-#define HSR0_CBM 0x08000000 /* copy back mode */
-#define HSR0_CBM_WRITE_THRU 0x00000000 /* - write through */
-#define HSR0_CBM_COPY_BACK 0x08000000 /* - copy back */
-#define HSR0_NWA 0x10000000 /* no write allocate */
-#define HSR0_DCE 0x40000000 /* data cache enable */
-#define HSR0_ICE 0x80000000 /* instruction cache enable */
-
-#define __get_HSR(R) ({ unsigned long x; asm volatile("movsg hsr"#R",%0" : "=r"(x)); x; })
-#define __set_HSR(R,V) do { asm volatile("movgs %0,hsr"#R : : "r"(V)); } while(0)
-
-/*
- * CCR - Condition Codes Register
- */
-#define CCR_FCC0 0x0000000f /* FP/Media condition 0 (fcc0 reg) */
-#define CCR_FCC1 0x000000f0 /* FP/Media condition 1 (fcc1 reg) */
-#define CCR_FCC2 0x00000f00 /* FP/Media condition 2 (fcc2 reg) */
-#define CCR_FCC3 0x0000f000 /* FP/Media condition 3 (fcc3 reg) */
-#define CCR_ICC0 0x000f0000 /* Integer condition 0 (icc0 reg) */
-#define CCR_ICC0_C 0x00010000 /* - Carry flag */
-#define CCR_ICC0_V 0x00020000 /* - Overflow flag */
-#define CCR_ICC0_Z 0x00040000 /* - Zero flag */
-#define CCR_ICC0_N 0x00080000 /* - Negative flag */
-#define CCR_ICC1 0x00f00000 /* Integer condition 1 (icc1 reg) */
-#define CCR_ICC2 0x0f000000 /* Integer condition 2 (icc2 reg) */
-#define CCR_ICC3 0xf0000000 /* Integer condition 3 (icc3 reg) */
-
-/*
- * CCCR - Condition Codes for Conditional Instructions Register
- */
-#define CCCR_CC0 0x00000003 /* condition 0 (cc0 reg) */
-#define CCCR_CC0_FALSE 0x00000002 /* - condition is false */
-#define CCCR_CC0_TRUE 0x00000003 /* - condition is true */
-#define CCCR_CC1 0x0000000c /* condition 1 (cc1 reg) */
-#define CCCR_CC2 0x00000030 /* condition 2 (cc2 reg) */
-#define CCCR_CC3 0x000000c0 /* condition 3 (cc3 reg) */
-#define CCCR_CC4 0x00000300 /* condition 4 (cc4 reg) */
-#define CCCR_CC5 0x00000c00 /* condition 5 (cc5 reg) */
-#define CCCR_CC6 0x00003000 /* condition 6 (cc6 reg) */
-#define CCCR_CC7 0x0000c000 /* condition 7 (cc7 reg) */
-
-/*
- * ISR - Integer Status Register
- */
-#define ISR_EMAM 0x00000001 /* memory misaligned access handling */
-#define ISR_EMAM_EXCEPTION 0x00000000 /* - generate exception */
-#define ISR_EMAM_FUDGE 0x00000001 /* - mask out invalid address bits */
-#define ISR_AEXC 0x00000004 /* accrued [overflow] exception */
-#define ISR_DTT 0x00000018 /* division type trap */
-#define ISR_DTT_IGNORE 0x00000000 /* - ignore division error */
-#define ISR_DTT_DIVBYZERO 0x00000008 /* - generate exception */
-#define ISR_DTT_OVERFLOW 0x00000010 /* - record overflow */
-#define ISR_EDE 0x00000020 /* enable division exception */
-#define ISR_PLI 0x20000000 /* pre-load instruction information */
-#define ISR_QI 0x80000000 /* quad data implementation information */
-
-/*
- * EPCR0 - Exception PC Register
- */
-#define EPCR0_V 0x00000001 /* register content validity indicator */
-#define EPCR0_PC 0xfffffffc /* faulting instruction address */
-
-/*
- * ESR0/14/15 - Exception Status Register
- */
-#define ESRx_VALID 0x00000001 /* register content validity indicator */
-#define ESRx_EC 0x0000003e /* exception type */
-#define ESRx_EC_DATA_STORE 0x00000000 /* - data_store_error */
-#define ESRx_EC_INSN_ACCESS 0x00000006 /* - instruction_access_error */
-#define ESRx_EC_PRIV_INSN 0x00000008 /* - privileged_instruction */
-#define ESRx_EC_ILL_INSN 0x0000000a /* - illegal_instruction */
-#define ESRx_EC_MP_EXCEP 0x0000001c /* - mp_exception */
-#define ESRx_EC_DATA_ACCESS 0x00000020 /* - data_access_error */
-#define ESRx_EC_DIVISION 0x00000026 /* - division_exception */
-#define ESRx_EC_ITLB_MISS 0x00000034 /* - instruction_access_TLB_miss */
-#define ESRx_EC_DTLB_MISS 0x00000036 /* - data_access_TLB_miss */
-#define ESRx_EC_DATA_ACCESS_DAT 0x0000003a /* - data_access_DAT_exception */
-
-#define ESR0_IAEC 0x00000100 /* info for instruction-access-exception */
-#define ESR0_IAEC_RESV 0x00000000 /* - reserved */
-#define ESR0_IAEC_PROT_VIOL 0x00000100 /* - protection violation */
-
-#define ESR0_ATXC 0x00f00000 /* address translation exception code */
-#define ESR0_ATXC_MMU_MISS 0x00000000 /* - MMU miss exception and more (?) */
-#define ESR0_ATXC_MULTI_DAT 0x00800000 /* - multiple DAT entry hit */
-#define ESR0_ATXC_MULTI_SAT 0x00900000 /* - multiple SAT entry hit */
-#define ESR0_ATXC_AMRTLB_MISS 0x00a00000 /* - MMU/TLB miss exception */
-#define ESR0_ATXC_PRIV_EXCEP 0x00c00000 /* - privilege protection fault */
-#define ESR0_ATXC_WP_EXCEP 0x00d00000 /* - write protection fault */
-
-#define ESR0_EAV 0x00000800 /* true if EAR0 register valid */
-#define ESR15_EAV 0x00000800 /* true if EAR15 register valid */
-
-/*
- * ESFR1 - Exception Status Valid Flag Register
- */
-#define ESFR1_ESR0 0x00000001 /* true if ESR0 is valid */
-#define ESFR1_ESR14 0x00004000 /* true if ESR14 is valid */
-#define ESFR1_ESR15 0x00008000 /* true if ESR15 is valid */
-
-/*
- * MSR - Media Status Register
- */
-#define MSR0_AOVF 0x00000001 /* overflow exception accrued */
-#define MSRx_OVF 0x00000002 /* overflow exception detected */
-#define MSRx_SIE 0x0000003c /* last SIMD instruction exception detected */
-#define MSRx_SIE_NONE 0x00000000 /* - none detected */
-#define MSRx_SIE_FRkHI_ACCk 0x00000020 /* - exception at FRkHI or ACCk */
-#define MSRx_SIE_FRkLO_ACCk1 0x00000010 /* - exception at FRkLO or ACCk+1 */
-#define MSRx_SIE_FRk1HI_ACCk2 0x00000008 /* - exception at FRk+1HI or ACCk+2 */
-#define MSRx_SIE_FRk1LO_ACCk3 0x00000004 /* - exception at FRk+1LO or ACCk+3 */
-#define MSR0_MTT 0x00007000 /* type of last media trap detected */
-#define MSR0_MTT_NONE 0x00000000 /* - none detected */
-#define MSR0_MTT_OVERFLOW 0x00001000 /* - overflow detected */
-#define MSR0_HI 0x00c00000 /* hardware implementation */
-#define MSR0_HI_ROUNDING 0x00000000 /* - rounding mode */
-#define MSR0_HI_NONROUNDING 0x00c00000 /* - non-rounding mode */
-#define MSR0_EMCI 0x01000000 /* enable media custom instructions */
-#define MSR0_SRDAV 0x10000000 /* select rounding mode of MAVEH */
-#define MSR0_SRDAV_RDAV 0x00000000 /* - controlled by MSR.RDAV */
-#define MSR0_SRDAV_RD 0x10000000 /* - controlled by MSR.RD */
-#define MSR0_RDAV 0x20000000 /* rounding mode of MAVEH */
-#define MSR0_RDAV_NEAREST_MI 0x00000000 /* - round to nearest minus */
-#define MSR0_RDAV_NEAREST_PL 0x20000000 /* - round to nearest plus */
-#define MSR0_RD 0xc0000000 /* rounding mode */
-#define MSR0_RD_NEAREST 0x00000000 /* - nearest */
-#define MSR0_RD_ZERO 0x40000000 /* - zero */
-#define MSR0_RD_POS_INF 0x80000000 /* - positive infinity */
-#define MSR0_RD_NEG_INF 0xc0000000 /* - negative infinity */
-
-/*
- * IAMPR0-7 - Instruction Address Mapping Register
- * DAMPR0-7 - Data Address Mapping Register
- */
-#define xAMPRx_V 0x00000001 /* register content validity indicator */
-#define DAMPRx_WP 0x00000002 /* write protect */
-#define DAMPRx_WP_RW 0x00000000 /* - read/write */
-#define DAMPRx_WP_RO 0x00000002 /* - read-only */
-#define xAMPRx_C 0x00000004 /* cached/uncached */
-#define xAMPRx_C_CACHED 0x00000000 /* - cached */
-#define xAMPRx_C_UNCACHED 0x00000004 /* - uncached */
-#define xAMPRx_S 0x00000008 /* supervisor only */
-#define xAMPRx_S_USER 0x00000000 /* - userspace can access */
-#define xAMPRx_S_KERNEL 0x00000008 /* - kernel only */
-#define xAMPRx_SS 0x000000f0 /* segment size */
-#define xAMPRx_SS_16Kb 0x00000000 /* - 16 kilobytes */
-#define xAMPRx_SS_64Kb 0x00000010 /* - 64 kilobytes */
-#define xAMPRx_SS_256Kb 0x00000020 /* - 256 kilobytes */
-#define xAMPRx_SS_1Mb 0x00000030 /* - 1 megabyte */
-#define xAMPRx_SS_2Mb 0x00000040 /* - 2 megabytes */
-#define xAMPRx_SS_4Mb 0x00000050 /* - 4 megabytes */
-#define xAMPRx_SS_8Mb 0x00000060 /* - 8 megabytes */
-#define xAMPRx_SS_16Mb 0x00000070 /* - 16 megabytes */
-#define xAMPRx_SS_32Mb 0x00000080 /* - 32 megabytes */
-#define xAMPRx_SS_64Mb 0x00000090 /* - 64 megabytes */
-#define xAMPRx_SS_128Mb 0x000000a0 /* - 128 megabytes */
-#define xAMPRx_SS_256Mb 0x000000b0 /* - 256 megabytes */
-#define xAMPRx_SS_512Mb 0x000000c0 /* - 512 megabytes */
-#define xAMPRx_RESERVED8 0x00000100 /* reserved bit */
-#define xAMPRx_NG 0x00000200 /* non-global */
-#define xAMPRx_L 0x00000400 /* locked */
-#define xAMPRx_M 0x00000800 /* modified */
-#define xAMPRx_D 0x00001000 /* DAT entry */
-#define xAMPRx_RESERVED13 0x00002000 /* reserved bit */
-#define xAMPRx_PPFN 0xfff00000 /* physical page frame number */
-
-#define xAMPRx_V_BIT 0
-#define DAMPRx_WP_BIT 1
-#define xAMPRx_C_BIT 2
-#define xAMPRx_S_BIT 3
-#define xAMPRx_RESERVED8_BIT 8
-#define xAMPRx_NG_BIT 9
-#define xAMPRx_L_BIT 10
-#define xAMPRx_M_BIT 11
-#define xAMPRx_D_BIT 12
-#define xAMPRx_RESERVED13_BIT 13
-
-#define __get_IAMPR(R) ({ unsigned long x; asm volatile("movsg iampr"#R",%0" : "=r"(x)); x; })
-#define __get_DAMPR(R) ({ unsigned long x; asm volatile("movsg dampr"#R",%0" : "=r"(x)); x; })
-
-#define __get_IAMLR(R) ({ unsigned long x; asm volatile("movsg iamlr"#R",%0" : "=r"(x)); x; })
-#define __get_DAMLR(R) ({ unsigned long x; asm volatile("movsg damlr"#R",%0" : "=r"(x)); x; })
-
-#define __set_IAMPR(R,V) do { asm volatile("movgs %0,iampr"#R : : "r"(V)); } while(0)
-#define __set_DAMPR(R,V) do { asm volatile("movgs %0,dampr"#R : : "r"(V)); } while(0)
-
-#define __set_IAMLR(R,V) do { asm volatile("movgs %0,iamlr"#R : : "r"(V)); } while(0)
-#define __set_DAMLR(R,V) do { asm volatile("movgs %0,damlr"#R : : "r"(V)); } while(0)
-
-#define save_dampr(R, _dampr) \
-do { \
- asm volatile("movsg dampr"R",%0" : "=r"(_dampr)); \
-} while(0)
-
-#define restore_dampr(R, _dampr) \
-do { \
- asm volatile("movgs %0,dampr"R :: "r"(_dampr)); \
-} while(0)
-
-/*
- * AMCR - Address Mapping Control Register
- */
-#define AMCR_IAMRN 0x000000ff /* quantity of IAMPR registers */
-#define AMCR_DAMRN 0x0000ff00 /* quantity of DAMPR registers */
-
-/*
- * TTBR - Address Translation Table Base Register
- */
-#define __get_TTBR() ({ unsigned long x; asm volatile("movsg ttbr,%0" : "=r"(x)); x; })
-
-/*
- * TPXR - TLB Probe Extend Register
- */
-#define TPXR_E 0x00000001
-#define TPXR_LMAX_SHIFT 20
-#define TPXR_LMAX_SMASK 0xf
-#define TPXR_WMAX_SHIFT 24
-#define TPXR_WMAX_SMASK 0xf
-#define TPXR_WAY_SHIFT 28
-#define TPXR_WAY_SMASK 0xf
-
-/*
- * DCR - Debug Control Register
- */
-#define DCR_IBCE3 0x00000001 /* break on conditional insn pointed to by IBAR3 */
-#define DCR_IBE3 0x00000002 /* break on insn pointed to by IBAR3 */
-#define DCR_IBCE1 0x00000004 /* break on conditional insn pointed to by IBAR2 */
-#define DCR_IBE1 0x00000008 /* break on insn pointed to by IBAR2 */
-#define DCR_IBCE2 0x00000010 /* break on conditional insn pointed to by IBAR1 */
-#define DCR_IBE2 0x00000020 /* break on insn pointed to by IBAR1 */
-#define DCR_IBCE0 0x00000040 /* break on conditional insn pointed to by IBAR0 */
-#define DCR_IBE0 0x00000080 /* break on insn pointed to by IBAR0 */
-
-#define DCR_DDBE1 0x00004000 /* use DBDR1x when checking DBAR1 */
-#define DCR_DWBE1 0x00008000 /* break on store to address in DBAR1/DBMR1x */
-#define DCR_DRBE1 0x00010000 /* break on load from address in DBAR1/DBMR1x */
-#define DCR_DDBE0 0x00020000 /* use DBDR0x when checking DBAR0 */
-#define DCR_DWBE0 0x00040000 /* break on store to address in DBAR0/DBMR0x */
-#define DCR_DRBE0 0x00080000 /* break on load from address in DBAR0/DBMR0x */
-
-#define DCR_EIM 0x0c000000 /* external interrupt disable */
-#define DCR_IBM 0x10000000 /* instruction break disable */
-#define DCR_SE 0x20000000 /* single step enable */
-#define DCR_EBE 0x40000000 /* exception break enable */
-
-/*
- * BRR - Break Interrupt Request Register
- */
-#define BRR_ST 0x00000001 /* single-step detected */
-#define BRR_SB 0x00000002 /* break instruction detected */
-#define BRR_BB 0x00000004 /* branch with hint detected */
-#define BRR_CBB 0x00000008 /* branch to LR detected */
-#define BRR_IBx 0x000000f0 /* hardware breakpoint detected */
-#define BRR_DBx 0x00000f00 /* hardware watchpoint detected */
-#define BRR_DBNEx 0x0000f000 /* ? */
-#define BRR_EBTT 0x00ff0000 /* trap type of exception break */
-#define BRR_TB 0x10000000 /* external break request detected */
-#define BRR_CB 0x20000000 /* ICE break command detected */
-#define BRR_EB 0x40000000 /* exception break detected */
-
-/*
- * BPSR - Break PSR Save Register
- */
-#define BPSR_BET 0x00000001 /* former PSR.ET */
-#define BPSR_BS 0x00001000 /* former PSR.S */
-
-#endif /* _ASM_SPR_REGS_H */
diff --git a/arch/frv/include/asm/string.h b/arch/frv/include/asm/string.h
deleted file mode 100644
index 1f6c35990439..000000000000
--- a/arch/frv/include/asm/string.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* string.h: FRV string handling
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_STRING_H_
-#define _ASM_STRING_H_
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#define __HAVE_ARCH_MEMSET 1
-#define __HAVE_ARCH_MEMCPY 1
-
-extern void *memset(void *, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-
-#else /* KERNEL */
-
-/*
- * let user libraries deal with these,
- * IMHO the kernel has no place defining these functions for user apps
- */
-
-#define __HAVE_ARCH_STRCPY 1
-#define __HAVE_ARCH_STRNCPY 1
-#define __HAVE_ARCH_STRCAT 1
-#define __HAVE_ARCH_STRNCAT 1
-#define __HAVE_ARCH_STRCMP 1
-#define __HAVE_ARCH_STRNCMP 1
-#define __HAVE_ARCH_STRCHR 1
-#define __HAVE_ARCH_STRRCHR 1
-#define __HAVE_ARCH_STRSTR 1
-#define __HAVE_ARCH_STRLEN 1
-#define __HAVE_ARCH_STRNLEN 1
-#define __HAVE_ARCH_MEMSET 1
-#define __HAVE_ARCH_MEMCPY 1
-#define __HAVE_ARCH_MEMMOVE 1
-#define __HAVE_ARCH_MEMSCAN 1
-#define __HAVE_ARCH_MEMCMP 1
-#define __HAVE_ARCH_MEMCHR 1
-#define __HAVE_ARCH_STRTOK 1
-
-#endif /* KERNEL */
-#endif /* _ASM_STRING_H_ */
diff --git a/arch/frv/include/asm/switch_to.h b/arch/frv/include/asm/switch_to.h
deleted file mode 100644
index 2cf0f6a7fbb1..000000000000
--- a/arch/frv/include/asm/switch_to.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* FR-V CPU basic task switching
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SWITCH_TO_H
-#define _ASM_SWITCH_TO_H
-
-#include <linux/thread_info.h>
-
-/*
- * switch_to(prev, next) should switch from task `prev' to `next'
- * `prev' will never be the same as `next'.
- * The `mb' is to tell GCC not to cache `current' across this call.
- */
-extern asmlinkage
-struct task_struct *__switch_to(struct thread_struct *prev_thread,
- struct thread_struct *next_thread,
- struct task_struct *prev);
-
-#define switch_to(prev, next, last) \
-do { \
- (prev)->thread.sched_lr = \
- (unsigned long) __builtin_return_address(0); \
- (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
- mb(); \
-} while(0)
-
-#endif /* _ASM_SWITCH_TO_H */
diff --git a/arch/frv/include/asm/syscall.h b/arch/frv/include/asm/syscall.h
deleted file mode 100644
index 70689eb29b98..000000000000
--- a/arch/frv/include/asm/syscall.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* syscall parameter access functions
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_SYSCALL_H
-#define _ASM_SYSCALL_H
-
-#include <linux/err.h>
-#include <asm/ptrace.h>
-
-/*
- * Get the system call number or -1
- */
-static inline long syscall_get_nr(struct task_struct *task,
- struct pt_regs *regs)
-{
- return regs->syscallno;
-}
-
-/*
- * Restore the clobbered GR8 register
- * (1st syscall arg was overwritten with syscall return or error)
- */
-static inline void syscall_rollback(struct task_struct *task,
- struct pt_regs *regs)
-{
- regs->gr8 = regs->orig_gr8;
-}
-
-/*
- * See if the syscall return value is an error, returning it if it is and 0 if
- * not
- */
-static inline long syscall_get_error(struct task_struct *task,
- struct pt_regs *regs)
-{
- return IS_ERR_VALUE(regs->gr8) ? regs->gr8 : 0;
-}
-
-/*
- * Get the syscall return value
- */
-static inline long syscall_get_return_value(struct task_struct *task,
- struct pt_regs *regs)
-{
- return regs->gr8;
-}
-
-/*
- * Set the syscall return value
- */
-static inline void syscall_set_return_value(struct task_struct *task,
- struct pt_regs *regs,
- int error, long val)
-{
- if (error)
- regs->gr8 = -error;
- else
- regs->gr8 = val;
-}
-
-/*
- * Retrieve the system call arguments
- */
-static inline void syscall_get_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- unsigned long *args)
-{
- /*
- * Do this simply for now. If we need to start supporting
- * fetching arguments from arbitrary indices, this will need some
- * extra logic. Presently there are no in-tree users that depend
- * on this behaviour.
- */
- BUG_ON(i);
-
- /* Argument pattern is: GR8, GR9, GR10, GR11, GR12, GR13 */
- switch (n) {
- case 6: args[5] = regs->gr13;
- case 5: args[4] = regs->gr12;
- case 4: args[3] = regs->gr11;
- case 3: args[2] = regs->gr10;
- case 2: args[1] = regs->gr9;
- case 1: args[0] = regs->gr8;
- break;
- default:
- BUG();
- }
-}
-
-/*
- * Alter the system call arguments
- */
-static inline void syscall_set_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- const unsigned long *args)
-{
- /* Same note as above applies */
- BUG_ON(i);
-
- switch (n) {
- case 6: regs->gr13 = args[5];
- case 5: regs->gr12 = args[4];
- case 4: regs->gr11 = args[3];
- case 3: regs->gr10 = args[2];
- case 2: regs->gr9 = args[1];
- case 1: regs->gr8 = args[0];
- break;
- default:
- BUG();
- }
-}
-
-#endif /* _ASM_SYSCALL_H */
diff --git a/arch/frv/include/asm/termios.h b/arch/frv/include/asm/termios.h
deleted file mode 100644
index 5a8c63554617..000000000000
--- a/arch/frv/include/asm/termios.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TERMIOS_H
-#define _ASM_TERMIOS_H
-
-#include <uapi/asm/termios.h>
-
-/* intr=^C quit=^| erase=del kill=^U
- eof=^D vtime=\0 vmin=\1 sxtc=\0
- start=^Q stop=^S susp=^Z eol=\0
- reprint=^R discard=^U werase=^W lnext=^V
- eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#include <asm-generic/termios-base.h>
-#endif /* _ASM_TERMIOS_H */
diff --git a/arch/frv/include/asm/thread_info.h b/arch/frv/include/asm/thread_info.h
deleted file mode 100644
index 0f950845fad9..000000000000
--- a/arch/frv/include/asm/thread_info.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* thread_info.h: description
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * Derived from include/asm-i386/thread_info.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#endif
-
-#define THREAD_SIZE 8192
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must also be changed
- */
-#ifndef __ASSEMBLY__
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- unsigned long status; /* thread-synchronous flags */
- __u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
-
- mm_segment_t addr_limit; /* thread address space:
- * 0-0xBFFFFFFF for user-thead
- * 0-0xFFFFFFFF for kernel-thread
- */
-
- __u8 supervisor_stack[0];
-};
-
-#else /* !__ASSEMBLY__ */
-
-#include <asm/asm-offsets.h>
-
-#endif
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-/* how to get the thread information struct from C */
-register struct thread_info *__current_thread_info asm("gr15");
-
-#define current_thread_info() ({ __current_thread_info; })
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_NOTIFY_RESUME 1 /* callback before returning to user */
-#define TIF_SIGPENDING 2 /* signal pending */
-#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
-#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
-#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_MEMDIE 7 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
-#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
-
-/* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK \
- (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_SINGLESTEP)
-
-/* work to do on any return to u-space */
-#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_SYSCALL_TRACE)
-
-#if _TIF_ALLWORK_MASK >= 0x2000
-#error "_TIF_ALLWORK_MASK won't fit in an ANDI now (see entry.S)"
-#endif
-
-/*
- * Thread-synchronous status.
- *
- * This is different from the flags in that nobody else
- * ever touches our thread-synchronous status, so we don't
- * have to worry about atomic accesses.
- */
-#define TS_USEDFPM 0x0001 /* FPU/Media was used by this task this quantum (SMP) */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/frv/include/asm/timer-regs.h b/arch/frv/include/asm/timer-regs.h
deleted file mode 100644
index 6c5a871ce5e9..000000000000
--- a/arch/frv/include/asm/timer-regs.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* timer-regs.h: hardware timer register definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_TIMER_REGS_H
-#define _ASM_TIMER_REGS_H
-
-#include <asm/sections.h>
-
-extern unsigned long __nongprelbss __clkin_clock_speed_HZ;
-extern unsigned long __nongprelbss __ext_bus_clock_speed_HZ;
-extern unsigned long __nongprelbss __res_bus_clock_speed_HZ;
-extern unsigned long __nongprelbss __sdram_clock_speed_HZ;
-extern unsigned long __nongprelbss __core_bus_clock_speed_HZ;
-extern unsigned long __nongprelbss __core_clock_speed_HZ;
-extern unsigned long __nongprelbss __dsu_clock_speed_HZ;
-extern unsigned long __nongprelbss __serial_clock_speed_HZ;
-
-#define __get_CLKC() ({ *(volatile unsigned long *)(0xfeff9a00); })
-
-static inline void __set_CLKC(unsigned long v)
-{
- int tmp;
-
- asm volatile(" st%I0.p %2,%M0 \n"
- " setlos %3,%1 \n"
- " membar \n"
- "0: \n"
- " subicc %1,#1,%1,icc0 \n"
- " bnc icc0,#1,0b \n"
- : "=m"(*(volatile unsigned long *) 0xfeff9a00), "=r"(tmp)
- : "r"(v), "i"(256)
- : "icc0");
-}
-
-#define __get_TCTR() ({ *(volatile unsigned long *)(0xfeff9418); })
-#define __get_TPRV() ({ *(volatile unsigned long *)(0xfeff9420); })
-#define __get_TPRCKSL() ({ *(volatile unsigned long *)(0xfeff9428); })
-#define __get_TCSR(T) ({ *(volatile unsigned long *)(0xfeff9400 + 8 * (T)); })
-#define __get_TxCKSL(T) ({ *(volatile unsigned long *)(0xfeff9430 + 8 * (T)); })
-
-#define __get_TCSR_DATA(T) ({ __get_TCSR(T) >> 24; })
-
-#define __set_TCTR(V) do { *(volatile unsigned long *)(0xfeff9418) = (V); mb(); } while(0)
-#define __set_TPRV(V) do { *(volatile unsigned long *)(0xfeff9420) = (V) << 24; mb(); } while(0)
-#define __set_TPRCKSL(V) do { *(volatile unsigned long *)(0xfeff9428) = (V); mb(); } while(0)
-#define __set_TCSR(T,V) \
-do { *(volatile unsigned long *)(0xfeff9400 + 8 * (T)) = (V); mb(); } while(0)
-
-#define __set_TxCKSL(T,V) \
-do { *(volatile unsigned long *)(0xfeff9430 + 8 * (T)) = (V); mb(); } while(0)
-
-#define __set_TCSR_DATA(T,V) __set_TCSR(T, (V) << 24)
-#define __set_TxCKSL_DATA(T,V) __set_TxCKSL(T, TxCKSL_EIGHT | __TxCKSL_SELECT((V)))
-
-/* clock control register */
-#define CLKC_CMODE 0x0f000000
-#define CLKC_SLPL 0x000f0000
-#define CLKC_P0 0x00000100
-#define CLKC_CM 0x00000003
-
-#define CLKC_CMODE_s 24
-
-/* timer control register - non-readback mode */
-#define TCTR_MODE_0 0x00000000
-#define TCTR_MODE_2 0x04000000
-#define TCTR_MODE_4 0x08000000
-#define TCTR_MODE_5 0x0a000000
-#define TCTR_RL_LATCH 0x00000000
-#define TCTR_RL_RW_LOW8 0x10000000
-#define TCTR_RL_RW_HIGH8 0x20000000
-#define TCTR_RL_RW_LH8 0x30000000
-#define TCTR_SC_CTR0 0x00000000
-#define TCTR_SC_CTR1 0x40000000
-#define TCTR_SC_CTR2 0x80000000
-
-/* timer control register - readback mode */
-#define TCTR_CNT0 0x02000000
-#define TCTR_CNT1 0x04000000
-#define TCTR_CNT2 0x08000000
-#define TCTR_NSTATUS 0x10000000
-#define TCTR_NCOUNT 0x20000000
-#define TCTR_SC_READBACK 0xc0000000
-
-/* timer control status registers - non-readback mode */
-#define TCSRx_DATA 0xff000000
-
-/* timer control status registers - readback mode */
-#define TCSRx_OUTPUT 0x80000000
-#define TCSRx_NULLCOUNT 0x40000000
-#define TCSRx_RL 0x30000000
-#define TCSRx_MODE 0x07000000
-
-/* timer clock select registers */
-#define TxCKSL_SELECT 0x0f000000
-#define __TxCKSL_SELECT(X) ((X) << 24)
-#define TxCKSL_EIGHT 0xf0000000
-
-#endif /* _ASM_TIMER_REGS_H */
diff --git a/arch/frv/include/asm/timex.h b/arch/frv/include/asm/timex.h
deleted file mode 100644
index bf53166f2793..000000000000
--- a/arch/frv/include/asm/timex.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* timex.h: FR-V architecture timex specifications
- */
-#ifndef _ASM_TIMEX_H
-#define _ASM_TIMEX_H
-
-#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
-#define CLOCK_TICK_FACTOR 20 /* Factor of both 1000000 and CLOCK_TICK_RATE */
-
-typedef unsigned long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
- return 0;
-}
-
-#define vxtime_lock() do {} while (0)
-#define vxtime_unlock() do {} while (0)
-
-/* This attribute is used in include/linux/jiffies.h alongside with
- * __cacheline_aligned_in_smp. It is assumed that __cacheline_aligned_in_smp
- * for frv does not contain another section specification.
- */
-#define __jiffy_arch_data __attribute__((__section__(".data")))
-
-#endif
-
diff --git a/arch/frv/include/asm/tlb.h b/arch/frv/include/asm/tlb.h
deleted file mode 100644
index d3e361ad725a..000000000000
--- a/arch/frv/include/asm/tlb.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TLB_H
-#define _ASM_TLB_H
-
-#include <asm/tlbflush.h>
-
-#ifdef CONFIG_MMU
-extern void check_pgt_cache(void);
-#else
-#define check_pgt_cache() do {} while(0)
-#endif
-
-/*
- * we don't need any special per-pte or per-vma handling...
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it fills up
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _ASM_TLB_H */
-
diff --git a/arch/frv/include/asm/tlbflush.h b/arch/frv/include/asm/tlbflush.h
deleted file mode 100644
index 75879420f578..000000000000
--- a/arch/frv/include/asm/tlbflush.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* tlbflush.h: TLB flushing functions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_TLBFLUSH_H
-#define _ASM_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_MMU
-
-#ifndef __ASSEMBLY__
-extern asmlinkage void __flush_tlb_all(void);
-extern asmlinkage void __flush_tlb_mm(unsigned long contextid);
-extern asmlinkage void __flush_tlb_page(unsigned long contextid, unsigned long start);
-extern asmlinkage void __flush_tlb_range(unsigned long contextid,
- unsigned long start, unsigned long end);
-#endif /* !__ASSEMBLY__ */
-
-#define flush_tlb_all() \
-do { \
- preempt_disable(); \
- __flush_tlb_all(); \
- preempt_enable(); \
-} while(0)
-
-#define flush_tlb_mm(mm) \
-do { \
- preempt_disable(); \
- __flush_tlb_mm((mm)->context.id); \
- preempt_enable(); \
-} while(0)
-
-#define flush_tlb_range(vma,start,end) \
-do { \
- preempt_disable(); \
- __flush_tlb_range((vma)->vm_mm->context.id, start, end); \
- preempt_enable(); \
-} while(0)
-
-#define flush_tlb_page(vma,addr) \
-do { \
- preempt_disable(); \
- __flush_tlb_page((vma)->vm_mm->context.id, addr); \
- preempt_enable(); \
-} while(0)
-
-
-#define __flush_tlb_global() flush_tlb_all()
-#define flush_tlb() flush_tlb_all()
-#define flush_tlb_kernel_range(start, end) flush_tlb_all()
-
-#else
-
-#define flush_tlb() BUG()
-#define flush_tlb_all() BUG()
-#define flush_tlb_mm(mm) BUG()
-#define flush_tlb_page(vma,addr) BUG()
-#define flush_tlb_range(mm,start,end) BUG()
-#define flush_tlb_kernel_range(start, end) BUG()
-
-#endif
-
-
-#endif /* _ASM_TLBFLUSH_H */
diff --git a/arch/frv/include/asm/topology.h b/arch/frv/include/asm/topology.h
deleted file mode 100644
index 207603071f78..000000000000
--- a/arch/frv/include/asm/topology.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TOPOLOGY_H
-#define _ASM_TOPOLOGY_H
-
-#ifdef CONFIG_NUMA
-
-#error NUMA not supported yet
-
-#endif /* CONFIG_NUMA */
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_TOPOLOGY_H */
diff --git a/arch/frv/include/asm/types.h b/arch/frv/include/asm/types.h
deleted file mode 100644
index 6bc63650d832..000000000000
--- a/arch/frv/include/asm/types.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* types.h: FRV types
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-#include <uapi/asm/types.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-
-#define BITS_PER_LONG 32
-
-#endif /* _ASM_TYPES_H */
diff --git a/arch/frv/include/asm/uaccess.h b/arch/frv/include/asm/uaccess.h
deleted file mode 100644
index ff9562dc6825..000000000000
--- a/arch/frv/include/asm/uaccess.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* uaccess.h: userspace accessor functions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_UACCESS_H
-#define _ASM_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/mm.h>
-#include <asm/segment.h>
-#include <asm/sections.h>
-#include <asm/extable.h>
-
-#define __ptr(x) ((unsigned long __force *)(x))
-
-/*
- * check that a range of addresses falls within the current address limit
- */
-static inline int ___range_ok(unsigned long addr, unsigned long size)
-{
-#ifdef CONFIG_MMU
- int flag = -EFAULT, tmp;
-
- asm volatile (
- " addcc %3,%2,%1,icc0 \n" /* set C-flag if addr+size>4GB */
- " subcc.p %1,%4,gr0,icc1 \n" /* jump if addr+size>limit */
- " bc icc0,#0,0f \n"
- " bhi icc1,#0,0f \n"
- " setlos #0,%0 \n" /* mark okay */
- "0: \n"
- : "=r"(flag), "=&r"(tmp)
- : "r"(addr), "r"(size), "r"(get_addr_limit()), "0"(flag)
- );
-
- return flag;
-
-#else
-
- if (addr < memory_start ||
- addr > memory_end ||
- size > memory_end - memory_start ||
- addr + size > memory_end)
- return -EFAULT;
-
- return 0;
-#endif
-}
-
-#define __range_ok(addr,size) ___range_ok((unsigned long) (addr), (unsigned long) (size))
-
-#define access_ok(type,addr,size) (__range_ok((void __user *)(addr), (size)) == 0)
-#define __access_ok(addr,size) (__range_ok((addr), (size)) == 0)
-
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- */
-#define __put_user(x, ptr) \
-({ \
- int __pu_err = 0; \
- \
- typeof(*(ptr)) __pu_val = (x); \
- __chk_user_ptr(ptr); \
- \
- switch (sizeof (*(ptr))) { \
- case 1: \
- __put_user_asm(__pu_err, __pu_val, ptr, "b", "r"); \
- break; \
- case 2: \
- __put_user_asm(__pu_err, __pu_val, ptr, "h", "r"); \
- break; \
- case 4: \
- __put_user_asm(__pu_err, __pu_val, ptr, "", "r"); \
- break; \
- case 8: \
- __put_user_asm(__pu_err, __pu_val, ptr, "d", "e"); \
- break; \
- default: \
- __pu_err = __put_user_bad(); \
- break; \
- } \
- __pu_err; \
-})
-
-#define put_user(x, ptr) \
-({ \
- typeof(*(ptr)) __user *_p = (ptr); \
- int _e; \
- \
- _e = __range_ok(_p, sizeof(*_p)); \
- if (_e == 0) \
- _e = __put_user((x), _p); \
- _e; \
-})
-
-extern int __put_user_bad(void);
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#ifdef CONFIG_MMU
-
-#define __put_user_asm(err,x,ptr,dsize,constraint) \
-do { \
- asm volatile("1: st"dsize"%I1 %2,%M1 \n" \
- "2: \n" \
- ".subsection 2 \n" \
- "3: setlos %3,%0 \n" \
- " bra 2b \n" \
- ".previous \n" \
- ".section __ex_table,\"a\" \n" \
- " .balign 8 \n" \
- " .long 1b,3b \n" \
- ".previous" \
- : "=r" (err) \
- : "m" (*__ptr(ptr)), constraint (x), "i"(-EFAULT), "0"(err) \
- : "memory"); \
-} while (0)
-
-#else
-
-#define __put_user_asm(err,x,ptr,bwl,con) \
-do { \
- asm(" st"bwl"%I0 %1,%M0 \n" \
- " membar \n" \
- : \
- : "m" (*__ptr(ptr)), con (x) \
- : "memory"); \
-} while (0)
-
-#endif
-
-/*****************************************************************************/
-/*
- *
- */
-#define __get_user(x, ptr) \
-({ \
- int __gu_err = 0; \
- __chk_user_ptr(ptr); \
- \
- switch (sizeof(*(ptr))) { \
- case 1: { \
- unsigned char __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "ub", "=r"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- case 2: { \
- unsigned short __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "uh", "=r"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- case 4: { \
- unsigned int __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "", "=r"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- case 8: { \
- unsigned long long __gu_val; \
- __get_user_asm(__gu_err, __gu_val, ptr, "d", "=e"); \
- (x) = *(__force __typeof__(*(ptr)) *) &__gu_val; \
- break; \
- } \
- default: \
- __gu_err = __get_user_bad(); \
- break; \
- } \
- __gu_err; \
-})
-
-#define get_user(x, ptr) \
-({ \
- const typeof(*(ptr)) __user *_p = (ptr);\
- int _e; \
- \
- _e = __range_ok(_p, sizeof(*_p)); \
- if (likely(_e == 0)) \
- _e = __get_user((x), _p); \
- else \
- (x) = (typeof(x)) 0; \
- _e; \
-})
-
-extern int __get_user_bad(void);
-
-#ifdef CONFIG_MMU
-
-#define __get_user_asm(err,x,ptr,dtype,constraint) \
-do { \
- asm("1: ld"dtype"%I2 %M2,%1 \n" \
- "2: \n" \
- ".subsection 2 \n" \
- "3: setlos %3,%0 \n" \
- " setlos #0,%1 \n" \
- " bra 2b \n" \
- ".previous \n" \
- ".section __ex_table,\"a\" \n" \
- " .balign 8 \n" \
- " .long 1b,3b \n" \
- ".previous" \
- : "=r" (err), constraint (x) \
- : "m" (*__ptr(ptr)), "i"(-EFAULT), "0"(err) \
- ); \
-} while(0)
-
-#else
-
-#define __get_user_asm(err,x,ptr,bwl,con) \
- asm(" ld"bwl"%I1 %M1,%0 \n" \
- " membar \n" \
- : con(x) \
- : "m" (*__ptr(ptr)))
-
-#endif
-
-/*****************************************************************************/
-/*
- *
- */
-
-#define ____force(x) (__force void *)(void __user *)(x)
-#ifdef CONFIG_MMU
-extern long __memset_user(void *dst, unsigned long count);
-extern long __memcpy_user(void *dst, const void *src, unsigned long count);
-
-#define __clear_user(dst,count) __memset_user(____force(dst), (count))
-
-#else
-
-#define __clear_user(dst,count) (memset(____force(dst), 0, (count)), 0)
-
-#endif
-
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
-#ifdef CONFIG_MMU
- return __memcpy_user(to, (__force const void *)from, n);
-#else
- memcpy(to, (__force const void *)from, n);
- return 0;
-#endif
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
-#ifdef CONFIG_MMU
- return __memcpy_user((__force void *)to, from, n);
-#else
- memcpy((__force void *)to, from, n);
- return 0;
-#endif
-}
-#define INLINE_COPY_TO_USER
-#define INLINE_COPY_FROM_USER
-
-static inline unsigned long __must_check
-clear_user(void __user *to, unsigned long n)
-{
- if (likely(__access_ok(to, n)))
- n = __clear_user(to, n);
- return n;
-}
-
-extern long strncpy_from_user(char *dst, const char __user *src, long count);
-extern long strnlen_user(const char __user *src, long count);
-
-#endif /* _ASM_UACCESS_H */
diff --git a/arch/frv/include/asm/ucontext.h b/arch/frv/include/asm/ucontext.h
deleted file mode 100644
index 0cc2d95dd209..000000000000
--- a/arch/frv/include/asm/ucontext.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_UCONTEXT_H
-#define _ASM_UCONTEXT_H
-
-struct ucontext {
- unsigned long uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-#endif
diff --git a/arch/frv/include/asm/unaligned.h b/arch/frv/include/asm/unaligned.h
deleted file mode 100644
index 6c61c05b2e0c..000000000000
--- a/arch/frv/include/asm/unaligned.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* unaligned.h: unaligned access handler
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNALIGNED_H
-#define _ASM_UNALIGNED_H
-
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_struct.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_be
-#define put_unaligned __put_unaligned_be
-
-#endif /* _ASM_UNALIGNED_H */
diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h
deleted file mode 100644
index b4b3f9b26b81..000000000000
--- a/arch/frv/include/asm/unistd.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_UNISTD_H_
-#define _ASM_UNISTD_H_
-
-#include <uapi/asm/unistd.h>
-
-
-#define NR_syscalls 338
-
-/* #define __ARCH_WANT_OLD_READDIR */
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-/* #define __ARCH_WANT_SYS_GETHOSTNAME */
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-/* #define __ARCH_WANT_SYS_SIGNAL */
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-/* #define __ARCH_WANT_SYS_OLD_GETRLIMIT */
-#define __ARCH_WANT_SYS_OLDUMOUNT
-/* #define __ARCH_WANT_SYS_SIGPENDING */
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-#define __ARCH_WANT_SYS_CLONE
-
-#endif /* _ASM_UNISTD_H_ */
diff --git a/arch/frv/include/asm/user.h b/arch/frv/include/asm/user.h
deleted file mode 100644
index 82fa8fab64ae..000000000000
--- a/arch/frv/include/asm/user.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* user.h: FR-V core file format stuff
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_USER_H
-#define _ASM_USER_H
-
-#include <asm/page.h>
-#include <asm/registers.h>
-
-/* Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the 'trad-core' bfd). There are quite a number of
- * obstacles to being able to view the contents of the floating point
- * registers, and until these are solved you will not be able to view
- * the contents of them. Actually, you can read in the core file and
- * look at the contents of the user struct to find out what the
- * floating point registers contain.
- *
- * The actual file contents are as follows:
- * UPAGE:
- * 1 page consisting of a user struct that tells gdb what is present
- * in the file. Directly after this is a copy of the task_struct,
- * which is currently not used by gdb, but it may come in useful at
- * some point. All of the registers are stored as part of the
- * upage. The upage should always be only one page.
- *
- * DATA:
- * The data area is stored. We use current->end_text to
- * current->brk to pick up all of the user variables, plus any
- * memory that may have been malloced. No attempt is made to
- * determine if a page is demand-zero or if a page is totally
- * unused, we just cover the entire range. All of the addresses are
- * rounded in such a way that an integral number of pages is
- * written.
- *
- * STACK:
- * We need the stack information in order to get a meaningful
- * backtrace. We need to write the data from (esp) to
- * current->start_stack, so we round each of these off in order to
- * be able to write an integer number of pages. The minimum core
- * file size is 3 pages, or 12288 bytes.
- */
-
-/* When the kernel dumps core, it starts by dumping the user struct -
- * this will be used by gdb to figure out where the data and stack segments
- * are within the file, and what virtual addresses to use.
- */
-struct user {
- /* We start with the registers, to mimic the way that "memory" is returned
- * from the ptrace(3,...) function. */
- struct user_context regs;
-
- /* The rest of this junk is to help gdb figure out what goes where */
- unsigned long u_tsize; /* Text segment size (pages). */
- unsigned long u_dsize; /* Data segment size (pages). */
- unsigned long u_ssize; /* Stack segment size (pages). */
- unsigned long start_code; /* Starting virtual address of text. */
- unsigned long start_stack; /* Starting virtual address of stack area.
- * This is actually the bottom of the stack,
- * the top of the stack is always found in the
- * esp register. */
- long int signal; /* Signal that caused the core dump. */
-
- unsigned long magic; /* To uniquely identify a core file */
- char u_comm[32]; /* User command that was responsible */
-};
-
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif
diff --git a/arch/frv/include/asm/vga.h b/arch/frv/include/asm/vga.h
deleted file mode 100644
index a702c800a229..000000000000
--- a/arch/frv/include/asm/vga.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* vga.h: VGA register stuff
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_VGA_H
-#define _ASM_VGA_H
-
-
-
-#endif /* _ASM_VGA_H */
diff --git a/arch/frv/include/asm/virtconvert.h b/arch/frv/include/asm/virtconvert.h
deleted file mode 100644
index b26d70ab9111..000000000000
--- a/arch/frv/include/asm/virtconvert.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* virtconvert.h: virtual/physical/page address conversion
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_VIRTCONVERT_H
-#define _ASM_VIRTCONVERT_H
-
-/*
- * Macros used for converting between virtual and physical mappings.
- */
-
-#ifdef __KERNEL__
-
-#include <asm/setup.h>
-
-#ifdef CONFIG_MMU
-
-#define phys_to_virt(vaddr) ((void *) ((unsigned long)(vaddr) + PAGE_OFFSET))
-#define virt_to_phys(vaddr) ((unsigned long) (vaddr) - PAGE_OFFSET)
-
-#else
-
-#define phys_to_virt(vaddr) ((void *) (vaddr))
-#define virt_to_phys(vaddr) ((unsigned long) (vaddr))
-
-#endif
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
-#define page_to_phys(page) virt_to_phys((void *)__page_address(page))
-
-#endif
-#endif
diff --git a/arch/frv/include/asm/xor.h b/arch/frv/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/frv/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/arch/frv/include/uapi/asm/Kbuild b/arch/frv/include/uapi/asm/Kbuild
deleted file mode 100644
index 5354b0f84d41..000000000000
--- a/arch/frv/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,5 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += siginfo.h
-generic-y += bpf_perf_event.h
diff --git a/arch/frv/include/uapi/asm/auxvec.h b/arch/frv/include/uapi/asm/auxvec.h
deleted file mode 100644
index 07710778fa10..000000000000
--- a/arch/frv/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __FRV_AUXVEC_H
-#define __FRV_AUXVEC_H
-
-#endif
diff --git a/arch/frv/include/uapi/asm/bitsperlong.h b/arch/frv/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index 76da34b10f59..000000000000
--- a/arch/frv/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/frv/include/uapi/asm/byteorder.h b/arch/frv/include/uapi/asm/byteorder.h
deleted file mode 100644
index a46f6472acdc..000000000000
--- a/arch/frv/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_BYTEORDER_H
-#define _ASM_BYTEORDER_H
-
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/frv/include/uapi/asm/errno.h b/arch/frv/include/uapi/asm/errno.h
deleted file mode 100644
index c5b82f2f2970..000000000000
--- a/arch/frv/include/uapi/asm/errno.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_ERRNO_H
-#define _ASM_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif /* _ASM_ERRNO_H */
-
diff --git a/arch/frv/include/uapi/asm/fcntl.h b/arch/frv/include/uapi/asm/fcntl.h
deleted file mode 100644
index a77648c505d1..000000000000
--- a/arch/frv/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/fcntl.h>
diff --git a/arch/frv/include/uapi/asm/ioctl.h b/arch/frv/include/uapi/asm/ioctl.h
deleted file mode 100644
index b809c4566e5f..000000000000
--- a/arch/frv/include/uapi/asm/ioctl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ioctl.h>
diff --git a/arch/frv/include/uapi/asm/ioctls.h b/arch/frv/include/uapi/asm/ioctls.h
deleted file mode 100644
index dd9f5eb9feda..000000000000
--- a/arch/frv/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASM_IOCTLS_H__
-#define __ASM_IOCTLS_H__
-
-#define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
-#define FIOQSIZE 0x545E
-
-#include <asm-generic/ioctls.h>
-
-#endif /* __ASM_IOCTLS_H__ */
-
diff --git a/arch/frv/include/uapi/asm/ipcbuf.h b/arch/frv/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 90d6445a14df..000000000000
--- a/arch/frv/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/frv/include/uapi/asm/kvm_para.h b/arch/frv/include/uapi/asm/kvm_para.h
deleted file mode 100644
index baacc4996d18..000000000000
--- a/arch/frv/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/kvm_para.h>
diff --git a/arch/frv/include/uapi/asm/mman.h b/arch/frv/include/uapi/asm/mman.h
deleted file mode 100644
index 306fc0460b80..000000000000
--- a/arch/frv/include/uapi/asm/mman.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/mman.h>
diff --git a/arch/frv/include/uapi/asm/msgbuf.h b/arch/frv/include/uapi/asm/msgbuf.h
deleted file mode 100644
index 156c81bb46d7..000000000000
--- a/arch/frv/include/uapi/asm/msgbuf.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_MSGBUF_H
-#define _ASM_MSGBUF_H
-
-/*
- * The msqid64_ds structure for FR-V architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
- struct ipc64_perm msg_perm;
- __kernel_time_t msg_stime; /* last msgsnd time */
- unsigned long __unused1;
- __kernel_time_t msg_rtime; /* last msgrcv time */
- unsigned long __unused2;
- __kernel_time_t msg_ctime; /* last change time */
- unsigned long __unused3;
- unsigned long msg_cbytes; /* current number of bytes on queue */
- unsigned long msg_qnum; /* number of messages in queue */
- unsigned long msg_qbytes; /* max number of bytes on queue */
- __kernel_pid_t msg_lspid; /* pid of last msgsnd */
- __kernel_pid_t msg_lrpid; /* last receive pid */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-#endif /* _ASM_MSGBUF_H */
-
diff --git a/arch/frv/include/uapi/asm/param.h b/arch/frv/include/uapi/asm/param.h
deleted file mode 100644
index d3e0168d8937..000000000000
--- a/arch/frv/include/uapi/asm/param.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_PARAM_H
-#define _ASM_PARAM_H
-
-#define EXEC_PAGESIZE 16384
-
-#include <asm-generic/param.h>
-
-#endif /* _ASM_PARAM_H */
diff --git a/arch/frv/include/uapi/asm/poll.h b/arch/frv/include/uapi/asm/poll.h
deleted file mode 100644
index f55b45f475ec..000000000000
--- a/arch/frv/include/uapi/asm/poll.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_POLL_H
-#define _ASM_POLL_H
-
-#define POLLWRNORM POLLOUT
-#define POLLWRBAND 256
-
-#include <asm-generic/poll.h>
-#undef POLLREMOVE
-
-#endif
diff --git a/arch/frv/include/uapi/asm/posix_types.h b/arch/frv/include/uapi/asm/posix_types.h
deleted file mode 100644
index 2995777227b3..000000000000
--- a/arch/frv/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_POSIX_TYPES_H
-#define _ASM_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif
-
diff --git a/arch/frv/include/uapi/asm/ptrace.h b/arch/frv/include/uapi/asm/ptrace.h
deleted file mode 100644
index f1d2f652d083..000000000000
--- a/arch/frv/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* ptrace.h: ptrace() relevant definitions
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _UAPI_ASM_PTRACE_H
-#define _UAPI_ASM_PTRACE_H
-
-#include <asm/registers.h>
-
-
-#define PT_PSR 0
-#define PT_ISR 1
-#define PT_CCR 2
-#define PT_CCCR 3
-#define PT_LR 4
-#define PT_LCR 5
-#define PT_PC 6
-
-#define PT__STATUS 7 /* exception status */
-#define PT_SYSCALLNO 8 /* syscall number or -1 */
-#define PT_ORIG_GR8 9 /* saved GR8 for signal handling */
-#define PT_GNER0 10
-#define PT_GNER1 11
-#define PT_IACC0H 12
-#define PT_IACC0L 13
-
-#define PT_GR(j) ( 14 + (j)) /* GRj for 0<=j<=63 */
-#define PT_FR(j) ( 78 + (j)) /* FRj for 0<=j<=63 */
-#define PT_FNER(j) (142 + (j)) /* FNERj for 0<=j<=1 */
-#define PT_MSR(j) (144 + (j)) /* MSRj for 0<=j<=2 */
-#define PT_ACC(j) (146 + (j)) /* ACCj for 0<=j<=7 */
-#define PT_ACCG(jklm) (154 + (jklm)) /* ACCGjklm for 0<=jklm<=1 (reads four regs per slot) */
-#define PT_FSR(j) (156 + (j)) /* FSRj for 0<=j<=0 */
-#define PT__GPEND 78
-#define PT__END 157
-
-#define PT_TBR PT_GR(0)
-#define PT_SP PT_GR(1)
-#define PT_FP PT_GR(2)
-#define PT_PREV_FRAME PT_GR(28) /* previous exception frame pointer (old gr28 value) */
-#define PT_CURR_TASK PT_GR(29) /* current task */
-
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */
-
-#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */
-#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */
-
-#endif /* _UAPI_ASM_PTRACE_H */
diff --git a/arch/frv/include/uapi/asm/registers.h b/arch/frv/include/uapi/asm/registers.h
deleted file mode 100644
index 4caf09b6c193..000000000000
--- a/arch/frv/include/uapi/asm/registers.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* registers.h: register frame declarations
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * notes:
- *
- * (1) that the members of all these structures are carefully aligned to permit
- * usage of STD/STDF instructions
- *
- * (2) if you change these structures, you must change the code in
- * arch/frvnommu/kernel/{break.S,entry.S,switch_to.S,gdb-stub.c}
- *
- *
- * the kernel stack space block looks like this:
- *
- * +0x2000 +----------------------
- * | union {
- * | struct frv_frame0 {
- * | struct user_context {
- * | struct user_int_regs
- * | struct user_fpmedia_regs
- * | }
- * | struct frv_debug_regs
- * | }
- * | struct pt_regs [user exception]
- * | }
- * +---------------------- <-- __kernel_frame0_ptr (maybe GR28)
- * |
- * | kernel stack
- * |
- * |......................
- * | struct pt_regs [kernel exception]
- * |...................... <-- __kernel_frame0_ptr (maybe GR28)
- * |
- * | kernel stack
- * |
- * |...................... <-- stack pointer (GR1)
- * |
- * | unused stack space
- * |
- * +----------------------
- * | struct thread_info
- * +0x0000 +---------------------- <-- __current_thread_info (GR15);
- *
- * note that GR28 points to the current exception frame
- */
-
-#ifndef _ASM_REGISTERS_H
-#define _ASM_REGISTERS_H
-
-#ifndef __ASSEMBLY__
-#define __OFFSET(X,N) ((X)+(N)*4)
-#define __OFFSETC(X,N) xxxxxxxxxxxxxxxxxxxxxxxx
-#else
-#define __OFFSET(X,N) ((X)+(N)*4)
-#define __OFFSETC(X,N) ((X)+(N))
-#endif
-
-/*****************************************************************************/
-/*
- * Exception/Interrupt frame
- * - held on kernel stack
- * - 8-byte aligned on stack (old SP is saved in frame)
- * - GR0 is fixed 0, so we don't save it
- */
-#ifndef __ASSEMBLY__
-
-struct pt_regs {
- unsigned long psr; /* Processor Status Register */
- unsigned long isr; /* Integer Status Register */
- unsigned long ccr; /* Condition Code Register */
- unsigned long cccr; /* Condition Code for Conditional Insns Register */
- unsigned long lr; /* Link Register */
- unsigned long lcr; /* Loop Count Register */
- unsigned long pc; /* Program Counter Register */
- unsigned long __status; /* exception status */
- unsigned long syscallno; /* syscall number or -1 */
- unsigned long orig_gr8; /* original syscall arg #1 */
- unsigned long gner0;
- unsigned long gner1;
- unsigned long long iacc0;
- unsigned long tbr; /* GR0 is fixed zero, so we use this for TBR */
- unsigned long sp; /* GR1: USP/KSP */
- unsigned long fp; /* GR2: FP */
- unsigned long gr3;
- unsigned long gr4;
- unsigned long gr5;
- unsigned long gr6;
- unsigned long gr7; /* syscall number */
- unsigned long gr8; /* 1st syscall param; syscall return */
- unsigned long gr9; /* 2nd syscall param */
- unsigned long gr10; /* 3rd syscall param */
- unsigned long gr11; /* 4th syscall param */
- unsigned long gr12; /* 5th syscall param */
- unsigned long gr13; /* 6th syscall param */
- unsigned long gr14;
- unsigned long gr15;
- unsigned long gr16; /* GP pointer */
- unsigned long gr17; /* small data */
- unsigned long gr18; /* PIC/PID */
- unsigned long gr19;
- unsigned long gr20;
- unsigned long gr21;
- unsigned long gr22;
- unsigned long gr23;
- unsigned long gr24;
- unsigned long gr25;
- unsigned long gr26;
- unsigned long gr27;
- struct pt_regs *next_frame; /* GR28 - next exception frame */
- unsigned long gr29; /* GR29 - OS reserved */
- unsigned long gr30; /* GR30 - OS reserved */
- unsigned long gr31; /* GR31 - OS reserved */
-} __attribute__((aligned(8)));
-
-#endif
-
-#define REG__STATUS_STEP 0x00000001 /* - reenable single stepping on return */
-#define REG__STATUS_STEPPED 0x00000002 /* - single step caused exception */
-#define REG__STATUS_BROKE 0x00000004 /* - BREAK insn caused exception */
-#define REG__STATUS_SYSC_ENTRY 0x40000000 /* - T on syscall entry (ptrace.c only) */
-#define REG__STATUS_SYSC_EXIT 0x80000000 /* - T on syscall exit (ptrace.c only) */
-
-#define REG_GR(R) __OFFSET(REG_GR0, (R))
-
-#define REG_SP REG_GR(1)
-#define REG_FP REG_GR(2)
-#define REG_PREV_FRAME REG_GR(28) /* previous exception frame pointer (old gr28 value) */
-#define REG_CURR_TASK REG_GR(29) /* current task */
-
-/*****************************************************************************/
-/*
- * debugging registers
- */
-#ifndef __ASSEMBLY__
-
-struct frv_debug_regs
-{
- unsigned long dcr;
- unsigned long ibar[4] __attribute__((aligned(8)));
- unsigned long dbar[4] __attribute__((aligned(8)));
- unsigned long dbdr[4][4] __attribute__((aligned(8)));
- unsigned long dbmr[4][4] __attribute__((aligned(8)));
-} __attribute__((aligned(8)));
-
-#endif
-
-/*****************************************************************************/
-/*
- * userspace registers
- */
-#ifndef __ASSEMBLY__
-
-struct user_int_regs
-{
- /* integer registers
- * - up to gr[31] mirror pt_regs
- * - total size must be multiple of 8 bytes
- */
- unsigned long psr; /* Processor Status Register */
- unsigned long isr; /* Integer Status Register */
- unsigned long ccr; /* Condition Code Register */
- unsigned long cccr; /* Condition Code for Conditional Insns Register */
- unsigned long lr; /* Link Register */
- unsigned long lcr; /* Loop Count Register */
- unsigned long pc; /* Program Counter Register */
- unsigned long __status; /* exception status */
- unsigned long syscallno; /* syscall number or -1 */
- unsigned long orig_gr8; /* original syscall arg #1 */
- unsigned long gner[2];
- unsigned long long iacc[1];
-
- union {
- unsigned long tbr;
- unsigned long gr[64];
- };
-};
-
-struct user_fpmedia_regs
-{
- /* FP/Media registers */
- unsigned long fr[64];
- unsigned long fner[2];
- unsigned long msr[2];
- unsigned long acc[8];
- unsigned char accg[8];
- unsigned long fsr[1];
-};
-
-struct user_context
-{
- struct user_int_regs i;
- struct user_fpmedia_regs f;
-
- /* we provide a context extension so that we can save the regs for CPUs that
- * implement many more of Fujitsu's lavish register spec
- */
- void *extension;
-} __attribute__((aligned(8)));
-
-struct frv_frame0 {
- union {
- struct pt_regs regs;
- struct user_context uc;
- };
-
- struct frv_debug_regs debug;
-
-} __attribute__((aligned(32)));
-
-#endif
-
-#define __INT_GR(R) __OFFSET(__INT_GR0, (R))
-
-#define __FPMEDIA_FR(R) __OFFSET(__FPMEDIA_FR0, (R))
-#define __FPMEDIA_FNER(R) __OFFSET(__FPMEDIA_FNER0, (R))
-#define __FPMEDIA_MSR(R) __OFFSET(__FPMEDIA_MSR0, (R))
-#define __FPMEDIA_ACC(R) __OFFSET(__FPMEDIA_ACC0, (R))
-#define __FPMEDIA_ACCG(R) __OFFSETC(__FPMEDIA_ACCG0, (R))
-#define __FPMEDIA_FSR(R) __OFFSET(__FPMEDIA_FSR0, (R))
-
-#define __THREAD_GR(R) __OFFSET(__THREAD_GR16, (R) - 16)
-
-#endif /* _ASM_REGISTERS_H */
diff --git a/arch/frv/include/uapi/asm/resource.h b/arch/frv/include/uapi/asm/resource.h
deleted file mode 100644
index 2100305f9b3e..000000000000
--- a/arch/frv/include/uapi/asm/resource.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_RESOURCE_H
-#define _ASM_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _ASM_RESOURCE_H */
-
diff --git a/arch/frv/include/uapi/asm/sembuf.h b/arch/frv/include/uapi/asm/sembuf.h
deleted file mode 100644
index d5477f95832b..000000000000
--- a/arch/frv/include/uapi/asm/sembuf.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SEMBUF_H
-#define _ASM_SEMBUF_H
-
-/*
- * The semid64_ds structure for FR-V architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
- struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
- __kernel_time_t sem_otime; /* last semop time */
- unsigned long __unused1;
- __kernel_time_t sem_ctime; /* last change time */
- unsigned long __unused2;
- unsigned long sem_nsems; /* no. of semaphores in array */
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_SEMBUF_H */
-
diff --git a/arch/frv/include/uapi/asm/setup.h b/arch/frv/include/uapi/asm/setup.h
deleted file mode 100644
index f54957047900..000000000000
--- a/arch/frv/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* setup.h: setup stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _UAPI_ASM_SETUP_H
-#define _UAPI_ASM_SETUP_H
-
-#define COMMAND_LINE_SIZE 512
-
-
-#endif /* _UAPI_ASM_SETUP_H */
diff --git a/arch/frv/include/uapi/asm/shmbuf.h b/arch/frv/include/uapi/asm/shmbuf.h
deleted file mode 100644
index 1de8f892e412..000000000000
--- a/arch/frv/include/uapi/asm/shmbuf.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SHMBUF_H
-#define _ASM_SHMBUF_H
-
-/*
- * The shmid64_ds structure for FR-V architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
- struct ipc64_perm shm_perm; /* operation perms */
- size_t shm_segsz; /* size of segment (bytes) */
- __kernel_time_t shm_atime; /* last attach time */
- unsigned long __unused1;
- __kernel_time_t shm_dtime; /* last detach time */
- unsigned long __unused2;
- __kernel_time_t shm_ctime; /* last change time */
- unsigned long __unused3;
- __kernel_pid_t shm_cpid; /* pid of creator */
- __kernel_pid_t shm_lpid; /* pid of last operator */
- unsigned long shm_nattch; /* no. of current attaches */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-struct shminfo64 {
- unsigned long shmmax;
- unsigned long shmmin;
- unsigned long shmmni;
- unsigned long shmseg;
- unsigned long shmall;
- unsigned long __unused1;
- unsigned long __unused2;
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_SHMBUF_H */
-
diff --git a/arch/frv/include/uapi/asm/sigcontext.h b/arch/frv/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 8fbb0b00afdd..000000000000
--- a/arch/frv/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* sigcontext.h: FRV signal context
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_SIGCONTEXT_H
-#define _ASM_SIGCONTEXT_H
-
-#include <asm/registers.h>
-
-/*
- * Signal context structure - contains all info to do with the state
- * before the signal handler was invoked. Note: only add new entries
- * to the end of the structure.
- */
-struct sigcontext {
- struct user_context sc_context;
- unsigned long sc_oldmask; /* old sigmask */
-} __attribute__((aligned(8)));
-
-#endif
diff --git a/arch/frv/include/uapi/asm/signal.h b/arch/frv/include/uapi/asm/signal.h
deleted file mode 100644
index 603bb796cf46..000000000000
--- a/arch/frv/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_SIGNAL_H
-#define _UAPI_ASM_SIGNAL_H
-
-#include <linux/types.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-#define NSIG 32
-typedef unsigned long sigset_t;
-
-#endif /* !__KERNEL__ */
-
-#define SA_RESTORER 0x04000000 /* to get struct sigaction correct */
-
-#include <asm-generic/signal.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-struct sigaction {
- union {
- __sighandler_t _sa_handler;
- void (*_sa_sigaction)(int, struct siginfo *, void *);
- } _u;
- sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void);
-};
-
-#define sa_handler _u._sa_handler
-#define sa_sigaction _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-#endif /* _UAPI_ASM_SIGNAL_H */
diff --git a/arch/frv/include/uapi/asm/socket.h b/arch/frv/include/uapi/asm/socket.h
deleted file mode 100644
index 9168e78fa32a..000000000000
--- a/arch/frv/include/uapi/asm/socket.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET 1
-
-#define SO_DEBUG 1
-#define SO_REUSEADDR 2
-#define SO_TYPE 3
-#define SO_ERROR 4
-#define SO_DONTROUTE 5
-#define SO_BROADCAST 6
-#define SO_SNDBUF 7
-#define SO_RCVBUF 8
-#define SO_SNDBUFFORCE 32
-#define SO_RCVBUFFORCE 33
-#define SO_KEEPALIVE 9
-#define SO_OOBINLINE 10
-#define SO_NO_CHECK 11
-#define SO_PRIORITY 12
-#define SO_LINGER 13
-#define SO_BSDCOMPAT 14
-#define SO_REUSEPORT 15
-#define SO_PASSCRED 16
-#define SO_PEERCRED 17
-#define SO_RCVLOWAT 18
-#define SO_SNDLOWAT 19
-#define SO_RCVTIMEO 20
-#define SO_SNDTIMEO 21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION 22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
-#define SO_SECURITY_ENCRYPTION_NETWORK 24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER 26
-#define SO_DETACH_FILTER 27
-#define SO_GET_FILTER SO_ATTACH_FILTER
-
-#define SO_PEERNAME 28
-#define SO_TIMESTAMP 29
-#define SCM_TIMESTAMP SO_TIMESTAMP
-
-#define SO_ACCEPTCONN 30
-
-#define SO_PEERSEC 31
-#define SO_PASSSEC 34
-#define SO_TIMESTAMPNS 35
-#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
-
-#define SO_MARK 36
-
-#define SO_TIMESTAMPING 37
-#define SCM_TIMESTAMPING SO_TIMESTAMPING
-
-#define SO_PROTOCOL 38
-#define SO_DOMAIN 39
-
-#define SO_RXQ_OVFL 40
-
-#define SO_WIFI_STATUS 41
-#define SCM_WIFI_STATUS SO_WIFI_STATUS
-#define SO_PEEK_OFF 42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS 43
-
-#define SO_LOCK_FILTER 44
-
-#define SO_SELECT_ERR_QUEUE 45
-
-#define SO_BUSY_POLL 46
-
-#define SO_MAX_PACING_RATE 47
-
-#define SO_BPF_EXTENSIONS 48
-
-#define SO_INCOMING_CPU 49
-
-#define SO_ATTACH_BPF 50
-#define SO_DETACH_BPF SO_DETACH_FILTER
-
-#define SO_ATTACH_REUSEPORT_CBPF 51
-#define SO_ATTACH_REUSEPORT_EBPF 52
-
-#define SO_CNX_ADVICE 53
-
-#define SCM_TIMESTAMPING_OPT_STATS 54
-
-#define SO_MEMINFO 55
-
-#define SO_INCOMING_NAPI_ID 56
-
-#define SO_COOKIE 57
-
-#define SCM_TIMESTAMPING_PKTINFO 58
-
-#define SO_PEERGROUPS 59
-
-#define SO_ZEROCOPY 60
-
-#endif /* _ASM_SOCKET_H */
-
diff --git a/arch/frv/include/uapi/asm/sockios.h b/arch/frv/include/uapi/asm/sockios.h
deleted file mode 100644
index 2f62caf1ce84..000000000000
--- a/arch/frv/include/uapi/asm/sockios.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SOCKIOS__
-#define _ASM_SOCKIOS__
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 0x8901
-#define SIOCSPGRP 0x8902
-#define FIOGETOWN 0x8903
-#define SIOCGPGRP 0x8904
-#define SIOCATMARK 0x8905
-#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
-#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
-
-#endif /* _ASM_SOCKIOS__ */
-
diff --git a/arch/frv/include/uapi/asm/stat.h b/arch/frv/include/uapi/asm/stat.h
deleted file mode 100644
index 0ff9fab915a4..000000000000
--- a/arch/frv/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_STAT_H
-#define _ASM_STAT_H
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-/* This matches struct stat in uClibc/glibc. */
-struct stat {
- unsigned char __pad1[6];
- unsigned short st_dev;
-
- unsigned long __pad2;
- unsigned long st_ino;
-
- unsigned short __pad3;
- unsigned short st_mode;
- unsigned short __pad4;
- unsigned short st_nlink;
-
- unsigned short __pad5;
- unsigned short st_uid;
- unsigned short __pad6;
- unsigned short st_gid;
-
- unsigned char __pad7[6];
- unsigned short st_rdev;
-
- unsigned long __pad8;
- unsigned long st_size;
-
- unsigned long __pad9; /* align 64-bit st_blocks to 2-word */
- unsigned long st_blksize;
-
- unsigned long __pad10; /* future possible st_blocks high bits */
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long __unused1;
- unsigned long st_atime;
-
- unsigned long __unused2;
- unsigned long st_mtime;
-
- unsigned long __unused3;
- unsigned long st_ctime;
-
- unsigned long long __unused4;
-};
-
-/* This matches struct stat64 in uClibc/glibc. The layout is exactly
- the same as that of struct stat above, with 64-bit types taking up
- space that was formerly used by padding. stat syscalls are still
- different from stat64, though, in that the former tests for
- overflow. */
-struct stat64 {
- unsigned char __pad1[6];
- unsigned short st_dev;
-
- unsigned long long st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned char __pad2[6];
- unsigned short st_rdev;
-
- long long st_size;
-
- unsigned long __pad3; /* align 64-bit st_blocks to 2-word */
- unsigned long st_blksize;
-
- unsigned long __pad4; /* future possible st_blocks high bits */
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
-
- unsigned long st_atime_nsec;
- unsigned long st_atime;
-
- unsigned int st_mtime_nsec;
- unsigned long st_mtime;
-
- unsigned long st_ctime_nsec;
- unsigned long st_ctime;
-
- unsigned long long __unused4;
-};
-
-#endif /* _ASM_STAT_H */
diff --git a/arch/frv/include/uapi/asm/statfs.h b/arch/frv/include/uapi/asm/statfs.h
deleted file mode 100644
index 2a378cbff07f..000000000000
--- a/arch/frv/include/uapi/asm/statfs.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_STATFS_H
-#define _ASM_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif /* _ASM_STATFS_H */
-
diff --git a/arch/frv/include/uapi/asm/swab.h b/arch/frv/include/uapi/asm/swab.h
deleted file mode 100644
index c78257d172e5..000000000000
--- a/arch/frv/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SWAB_H
-#define _ASM_SWAB_H
-
-#include <linux/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __SWAB_64_THRU_32__
-#endif
-
-#endif /* _ASM_SWAB_H */
diff --git a/arch/frv/include/uapi/asm/termbits.h b/arch/frv/include/uapi/asm/termbits.h
deleted file mode 100644
index b1dcd8d0ff78..000000000000
--- a/arch/frv/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_TERMBITS_H__
-#define _ASM_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-
-/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IUCLC 0001000
-#define IXON 0002000
-#define IXANY 0004000
-#define IXOFF 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
-
-/* c_oflag bits */
-#define OPOST 0000001
-#define OLCUC 0000002
-#define ONLCR 0000004
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-#define OFILL 0000100
-#define OFDEL 0000200
-#define NLDLY 0000400
-#define NL0 0000000
-#define NL1 0000400
-#define CRDLY 0003000
-#define CR0 0000000
-#define CR1 0001000
-#define CR2 0002000
-#define CR3 0003000
-#define TABDLY 0014000
-#define TAB0 0000000
-#define TAB1 0004000
-#define TAB2 0010000
-#define TAB3 0014000
-#define XTABS 0014000
-#define BSDLY 0020000
-#define BS0 0000000
-#define BS1 0020000
-#define VTDLY 0040000
-#define VT0 0000000
-#define VT1 0040000
-#define FFDLY 0100000
-#define FF0 0000000
-#define FF1 0100000
-
-/* c_cflag bit meaning */
-#define CBAUD 0010017
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0000060
-#define CS5 0000000
-#define CS6 0000020
-#define CS7 0000040
-#define CS8 0000060
-#define CSTOPB 0000100
-#define CREAD 0000200
-#define PARENB 0000400
-#define PARODD 0001000
-#define HUPCL 0002000
-#define CLOCAL 0004000
-#define CBAUDEX 0010000
-#define BOTHER 0010000
-#define B57600 0010001
-#define B115200 0010002
-#define B230400 0010003
-#define B460800 0010004
-#define B500000 0010005
-#define B576000 0010006
-#define B921600 0010007
-#define B1000000 0010010
-#define B1152000 0010011
-#define B1500000 0010012
-#define B2000000 0010013
-#define B2500000 0010014
-#define B3000000 0010015
-#define B3500000 0010016
-#define B4000000 0010017
-#define CIBAUD 002003600000 /* Input baud rate */
-#define CTVB 004000000000 /* VisioBraille Terminal flow control */
-#define CMSPAR 010000000000 /* mark or space (stick) parity */
-#define CRTSCTS 020000000000 /* flow control */
-
-#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG 0000001
-#define ICANON 0000002
-#define XCASE 0000004
-#define ECHO 0000010
-#define ECHOE 0000020
-#define ECHOK 0000040
-#define ECHONL 0000100
-#define NOFLSH 0000200
-#define TOSTOP 0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE 0004000
-#define FLUSHO 0010000
-#define PENDIN 0040000
-#define IEXTEN 0100000
-#define EXTPROC 0200000
-
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif /* _ASM_TERMBITS_H__ */
-
diff --git a/arch/frv/include/uapi/asm/termios.h b/arch/frv/include/uapi/asm/termios.h
deleted file mode 100644
index ae35bedae6a2..000000000000
--- a/arch/frv/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_TERMIOS_H
-#define _UAPI_ASM_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-#define TIOCM_MODEM_BITS TIOCM_OUT2 /* IRDA support */
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-
-#endif /* _UAPI_ASM_TERMIOS_H */
diff --git a/arch/frv/include/uapi/asm/types.h b/arch/frv/include/uapi/asm/types.h
deleted file mode 100644
index db74ad9ba6c0..000000000000
--- a/arch/frv/include/uapi/asm/types.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* types.h: FRV types
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <asm-generic/int-ll64.h>
diff --git a/arch/frv/include/uapi/asm/unistd.h b/arch/frv/include/uapi/asm/unistd.h
deleted file mode 100644
index 4b46acaf832b..000000000000
--- a/arch/frv/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,349 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_UNISTD_H_
-#define _UAPI_ASM_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_restart_syscall 0
-#define __NR_exit 1
-#define __NR_fork 2
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
-#define __NR_waitpid 7
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_lchown 16
-#define __NR_break 17
-#define __NR_oldstat 18
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
-#define __NR_umount 22
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
-#define __NR_oldfstat 28
-#define __NR_pause 29
-#define __NR_utime 30
-#define __NR_stty 31
-#define __NR_gtty 32
-#define __NR_access 33
-#define __NR_nice 34
-#define __NR_ftime 35
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
-#define __NR_prof 44
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
-#define __NR_signal 48
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
-#define __NR_lock 53
-#define __NR_ioctl 54
-#define __NR_fcntl 55
-#define __NR_mpx 56
-#define __NR_setpgid 57
-#define __NR_ulimit 58
-// #define __NR_oldolduname /* 59 */ obsolete
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
-#define __NR_sigaction 67
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
-#define __NR_sigsuspend 72
-#define __NR_sigpending 73
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
-#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
-#define __NR_select 82
-#define __NR_symlink 83
-#define __NR_oldlstat 84
-#define __NR_readlink 85
-#define __NR_uselib 86
-#define __NR_swapon 87
-#define __NR_reboot 88
-#define __NR_readdir 89
-// #define __NR_mmap 90 /* obsolete - not implemented */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
-// #define __NR_profil /* 98 */ obsolete
-#define __NR_statfs 99
-#define __NR_fstatfs 100
-// #define __NR_ioperm /* 101 */ not supported
-#define __NR_socketcall 102
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
-// #define __NR_olduname /* 109 */ obsolete
-// #define __NR_iopl /* 110 */ not supported
-#define __NR_vhangup 111
-// #define __NR_idle /* 112 */ Obsolete
-// #define __NR_vm86old /* 113 */ not supported
-#define __NR_wait4 114
-#define __NR_swapoff 115
-#define __NR_sysinfo 116
-#define __NR_ipc 117
-#define __NR_fsync 118
-#define __NR_sigreturn 119
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
-// #define __NR_modify_ldt /* 123 */ not supported
-#define __NR_cacheflush 123
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
-#define __NR_sigprocmask 126
-#define __NR_create_module 127
-#define __NR_init_module 128
-#define __NR_delete_module 129
-#define __NR_get_kernel_syms 130
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
-#define __NR_sysfs 135
-#define __NR_personality 136
-#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
-#define __NR__newselect 142
-#define __NR_flock 143
-#define __NR_msync 144
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
-#define __NR_mlock 150
-#define __NR_munlock 151
-#define __NR_mlockall 152
-#define __NR_munlockall 153
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
-// #define __NR_vm86 /* 166 */ not supported
-#define __NR_query_module 167
-#define __NR_poll 168
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread64 180
-#define __NR_pwrite64 181
-#define __NR_chown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
-#define __NR_getpmsg 188 /* some people actually want streams */
-#define __NR_putpmsg 189 /* some people actually want streams */
-#define __NR_vfork 190
-#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_lchown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_chown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
-#define __NR_mincore 218
-#define __NR_madvise 219
-
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
-#define __NR_security 223 /* syscall for security modules */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
-#define __NR_set_thread_area 243
-#define __NR_get_thread_area 244
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
-#define __NR_fadvise64 250
-
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_epoll_create 254
-#define __NR_epoll_ctl 255
-#define __NR_epoll_wait 256
-#define __NR_remap_file_pages 257
-#define __NR_set_tid_address 258
-#define __NR_timer_create 259
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
-#define __NR_statfs64 268
-#define __NR_fstatfs64 269
-#define __NR_tgkill 270
-#define __NR_utimes 271
-#define __NR_fadvise64_64 272
-#define __NR_vserver 273
-#define __NR_mbind 274
-#define __NR_get_mempolicy 275
-#define __NR_set_mempolicy 276
-#define __NR_mq_open 277
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
-#define __NR_kexec_load 283
-#define __NR_waitid 284
-/* #define __NR_sys_setaltroot 285 */
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
-#define __NR_migrate_pages 294
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-#define __NR_set_robust_list 311
-#define __NR_get_robust_list 312
-#define __NR_splice 313
-#define __NR_sync_file_range 314
-#define __NR_tee 315
-#define __NR_vmsplice 316
-#define __NR_move_pages 317
-#define __NR_getcpu 318
-#define __NR_epoll_pwait 319
-#define __NR_utimensat 320
-#define __NR_signalfd 321
-#define __NR_timerfd_create 322
-#define __NR_eventfd 323
-#define __NR_fallocate 324
-#define __NR_timerfd_settime 325
-#define __NR_timerfd_gettime 326
-#define __NR_signalfd4 327
-#define __NR_eventfd2 328
-#define __NR_epoll_create1 329
-#define __NR_dup3 330
-#define __NR_pipe2 331
-#define __NR_inotify_init1 332
-#define __NR_preadv 333
-#define __NR_pwritev 334
-#define __NR_rt_tgsigqueueinfo 335
-#define __NR_perf_event_open 336
-#define __NR_setns 337
-
-#endif /* _UAPI_ASM_UNISTD_H_ */
diff --git a/arch/frv/kernel/.gitignore b/arch/frv/kernel/.gitignore
deleted file mode 100644
index c5f676c3c224..000000000000
--- a/arch/frv/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/frv/kernel/Makefile b/arch/frv/kernel/Makefile
deleted file mode 100644
index 216ddf30c3c1..000000000000
--- a/arch/frv/kernel/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux kernel.
-#
-
-heads-y := head-uc-fr401.o head-uc-fr451.o head-uc-fr555.o
-heads-$(CONFIG_MMU) := head-mmu-fr451.o
-
-extra-y:= head.o vmlinux.lds
-
-obj-y := $(heads-y) entry.o entry-table.o break.o switch_to.o \
- process.o traps.o ptrace.o signal.o dma.o \
- sys_frv.o time.o setup.o frv_ksyms.o \
- debug-stub.o irq.o sleep.o uaccess.o
-
-obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-io.o
-
-obj-$(CONFIG_MB93091_VDK) += irq-mb93091.o
-obj-$(CONFIG_PM) += pm.o cmode.o
-obj-$(CONFIG_MB93093_PDK) += pm-mb93093.o
-obj-$(CONFIG_FUJITSU_MB93493) += irq-mb93493.o
-obj-$(CONFIG_SYSCTL) += sysctl.o
-obj-$(CONFIG_FUTEX) += futex.o
-obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/frv/kernel/asm-offsets.c b/arch/frv/kernel/asm-offsets.c
deleted file mode 100644
index 0a468e9b51ad..000000000000
--- a/arch/frv/kernel/asm-offsets.c
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed
- * to extract and format the required data.
- */
-
-#include <linux/sched.h>
-#include <linux/signal.h>
-#include <linux/personality.h>
-#include <linux/kbuild.h>
-#include <asm/registers.h>
-#include <asm/ucontext.h>
-#include <asm/processor.h>
-#include <asm/thread_info.h>
-#include <asm/gdb-stub.h>
-
-#define DEF_PTREG(sym, reg) OFFSET(sym, pt_regs, reg)
-#define DEF_IREG(sym, reg) OFFSET(sym, user_context, reg)
-#define DEF_FREG(sym, reg) OFFSET(sym, user_context, reg)
-#define DEF_0REG(sym, reg) OFFSET(sym, frv_frame0, reg)
-
-void foo(void)
-{
- /* offsets into the thread_info structure */
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_STATUS, thread_info, status);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PREEMPT_COUNT, thread_info, preempt_count);
- OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
- BLANK();
-
- /* offsets into register file storage */
- DEF_PTREG(REG_PSR, psr);
- DEF_PTREG(REG_ISR, isr);
- DEF_PTREG(REG_CCR, ccr);
- DEF_PTREG(REG_CCCR, cccr);
- DEF_PTREG(REG_LR, lr);
- DEF_PTREG(REG_LCR, lcr);
- DEF_PTREG(REG_PC, pc);
- DEF_PTREG(REG__STATUS, __status);
- DEF_PTREG(REG_SYSCALLNO, syscallno);
- DEF_PTREG(REG_ORIG_GR8, orig_gr8);
- DEF_PTREG(REG_GNER0, gner0);
- DEF_PTREG(REG_GNER1, gner1);
- DEF_PTREG(REG_IACC0, iacc0);
- DEF_PTREG(REG_TBR, tbr);
- DEF_PTREG(REG_GR0, tbr);
- DEFINE(REG__END, sizeof(struct pt_regs));
- BLANK();
-
- DEF_0REG(REG_DCR, debug.dcr);
- DEF_0REG(REG_IBAR0, debug.ibar[0]);
- DEF_0REG(REG_DBAR0, debug.dbar[0]);
- DEF_0REG(REG_DBDR00, debug.dbdr[0][0]);
- DEF_0REG(REG_DBMR00, debug.dbmr[0][0]);
- BLANK();
-
- DEF_IREG(__INT_GR0, i.gr[0]);
- DEF_FREG(__USER_FPMEDIA, f);
- DEF_FREG(__FPMEDIA_FR0, f.fr[0]);
- DEF_FREG(__FPMEDIA_FNER0, f.fner[0]);
- DEF_FREG(__FPMEDIA_MSR0, f.msr[0]);
- DEF_FREG(__FPMEDIA_ACC0, f.acc[0]);
- DEF_FREG(__FPMEDIA_ACCG0, f.accg[0]);
- DEF_FREG(__FPMEDIA_FSR0, f.fsr[0]);
- BLANK();
-
- DEFINE(NR_PT_REGS, sizeof(struct pt_regs) / 4);
- DEFINE(NR_USER_INT_REGS, sizeof(struct user_int_regs) / 4);
- DEFINE(NR_USER_FPMEDIA_REGS, sizeof(struct user_fpmedia_regs) / 4);
- DEFINE(NR_USER_CONTEXT, sizeof(struct user_context) / 4);
- DEFINE(FRV_FRAME0_SIZE, sizeof(struct frv_frame0));
- BLANK();
-
- /* offsets into thread_struct */
- OFFSET(__THREAD_FRAME, thread_struct, frame);
- OFFSET(__THREAD_CURR, thread_struct, curr);
- OFFSET(__THREAD_SP, thread_struct, sp);
- OFFSET(__THREAD_FP, thread_struct, fp);
- OFFSET(__THREAD_LR, thread_struct, lr);
- OFFSET(__THREAD_PC, thread_struct, pc);
- OFFSET(__THREAD_GR16, thread_struct, gr[0]);
- OFFSET(__THREAD_SCHED_LR, thread_struct, sched_lr);
- OFFSET(__THREAD_FRAME0, thread_struct, frame0);
- OFFSET(__THREAD_USER, thread_struct, user);
- BLANK();
-
- /* offsets into frv_debug_status */
- OFFSET(DEBUG_BPSR, frv_debug_status, bpsr);
- OFFSET(DEBUG_DCR, frv_debug_status, dcr);
- OFFSET(DEBUG_BRR, frv_debug_status, brr);
- OFFSET(DEBUG_NMAR, frv_debug_status, nmar);
- BLANK();
-}
diff --git a/arch/frv/kernel/break.S b/arch/frv/kernel/break.S
deleted file mode 100644
index cbb6958a3147..000000000000
--- a/arch/frv/kernel/break.S
+++ /dev/null
@@ -1,792 +0,0 @@
-/* break.S: Break interrupt handling (kept separate from entry.S)
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/linkage.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/ptrace.h>
-#include <asm/thread_info.h>
-#include <asm/spr-regs.h>
-
-#include <asm/errno.h>
-
-#
-# the break handler has its own stack
-#
- .section .bss..stack
- .globl __break_user_context
- .balign THREAD_SIZE
-__break_stack:
- .space THREAD_SIZE - FRV_FRAME0_SIZE
-__break_frame_0:
- .space FRV_FRAME0_SIZE
-
-#
-# miscellaneous variables
-#
- .section .bss
-#ifdef CONFIG_MMU
- .globl __break_tlb_miss_real_return_info
-__break_tlb_miss_real_return_info:
- .balign 8
- .space 2*4 /* saved PCSR, PSR for TLB-miss handler fixup */
-#endif
-
-__break_trace_through_exceptions:
- .space 4
-
-#define CS2_ECS1 0xe1200000
-#define CS2_USERLED 0x4
-
-.macro LEDS val,reg
-# sethi.p %hi(CS2_ECS1+CS2_USERLED),gr30
-# setlo %lo(CS2_ECS1+CS2_USERLED),gr30
-# setlos #~\val,\reg
-# st \reg,@(gr30,gr0)
-# setlos #0x5555,\reg
-# sethi.p %hi(0xffc00100),gr30
-# setlo %lo(0xffc00100),gr30
-# sth \reg,@(gr30,gr0)
-# membar
-.endm
-
-###############################################################################
-#
-# entry point for Break Exceptions/Interrupts
-#
-###############################################################################
- .section .text..break
- .balign 4
- .globl __entry_break
-__entry_break:
-#ifdef CONFIG_MMU
- movgs gr31,scr3
-#endif
- LEDS 0x1001,gr31
-
- sethi.p %hi(__break_frame_0),gr31
- setlo %lo(__break_frame_0),gr31
-
- stdi gr2,@(gr31,#REG_GR(2))
- movsg ccr,gr3
- sti gr3,@(gr31,#REG_CCR)
-
- # catch the return from a TLB-miss handler that had single-step disabled
- # traps will be enabled, so we have to do this now
-#ifdef CONFIG_MMU
- movsg bpcsr,gr3
- sethi.p %hi(__break_tlb_miss_return_breaks_here),gr2
- setlo %lo(__break_tlb_miss_return_breaks_here),gr2
- subcc gr2,gr3,gr0,icc0
- beq icc0,#2,__break_return_singlestep_tlbmiss
-#endif
-
- # determine whether we have stepped through into an exception
- # - we need to take special action to suspend h/w single stepping if we've done
- # that, so that the gdbstub doesn't get bogged down endlessly stepping through
- # external interrupt handling
- movsg bpsr,gr3
- andicc gr3,#BPSR_BET,gr0,icc0
- bne icc0,#2,__break_maybe_userspace /* jump if PSR.ET was 1 */
-
- LEDS 0x1003,gr2
-
- movsg brr,gr3
- andicc gr3,#BRR_ST,gr0,icc0
- andicc.p gr3,#BRR_SB,gr0,icc1
- bne icc0,#2,__break_step /* jump if single-step caused break */
- beq icc1,#2,__break_continue /* jump if BREAK didn't cause break */
-
- LEDS 0x1007,gr2
-
- # handle special breaks
- movsg bpcsr,gr3
-
- sethi.p %hi(__entry_return_singlestep_breaks_here),gr2
- setlo %lo(__entry_return_singlestep_breaks_here),gr2
- subcc gr2,gr3,gr0,icc0
- beq icc0,#2,__break_return_singlestep
-
- bra __break_continue
-
-
-###############################################################################
-#
-# handle BREAK instruction in kernel-mode exception epilogue
-#
-###############################################################################
-__break_return_singlestep:
- LEDS 0x100f,gr2
-
- # special break insn requests single-stepping to be turned back on
- # HERE RETT
- # PSR.ET 0 0
- # PSR.PS old PSR.S ?
- # PSR.S 1 1
- # BPSR.ET 0 1 (can't have caused orig excep otherwise)
- # BPSR.BS 1 old PSR.S
- movsg dcr,gr2
- sethi.p %hi(DCR_SE),gr3
- setlo %lo(DCR_SE),gr3
- or gr2,gr3,gr2
- movgs gr2,dcr
-
- movsg psr,gr2
- andi gr2,#PSR_PS,gr2
- slli gr2,#11,gr2 /* PSR.PS -> BPSR.BS */
- ori gr2,#BPSR_BET,gr2 /* 1 -> BPSR.BET */
- movgs gr2,bpsr
-
- # return to the invoker of the original kernel exception
- movsg pcsr,gr2
- movgs gr2,bpcsr
-
- LEDS 0x101f,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-###############################################################################
-#
-# handle BREAK instruction in TLB-miss handler return path
-#
-###############################################################################
-#ifdef CONFIG_MMU
-__break_return_singlestep_tlbmiss:
- LEDS 0x1100,gr2
-
- sethi.p %hi(__break_tlb_miss_real_return_info),gr3
- setlo %lo(__break_tlb_miss_real_return_info),gr3
- lddi @(gr3,#0),gr2
- movgs gr2,pcsr
- movgs gr3,psr
-
- bra __break_return_singlestep
-#endif
-
-
-###############################################################################
-#
-# handle single stepping into an exception prologue from kernel mode
-# - we try and catch it whilst it is still in the main vector table
-# - if we catch it there, we have to jump to the fixup handler
-# - there is a fixup table that has a pointer for every 16b slot in the trap
-# table
-#
-###############################################################################
-__break_step:
- LEDS 0x2003,gr2
-
- # external interrupts seem to escape from the trap table before single
- # step catches up with them
- movsg bpcsr,gr2
- sethi.p %hi(__entry_kernel_external_interrupt),gr3
- setlo %lo(__entry_kernel_external_interrupt),gr3
- subcc.p gr2,gr3,gr0,icc0
- sethi %hi(__entry_uspace_external_interrupt),gr3
- setlo.p %lo(__entry_uspace_external_interrupt),gr3
- beq icc0,#2,__break_step_kernel_external_interrupt
- subcc.p gr2,gr3,gr0,icc0
- sethi %hi(__entry_kernel_external_interrupt_virtually_disabled),gr3
- setlo.p %lo(__entry_kernel_external_interrupt_virtually_disabled),gr3
- beq icc0,#2,__break_step_uspace_external_interrupt
- subcc.p gr2,gr3,gr0,icc0
- sethi %hi(__entry_kernel_external_interrupt_virtual_reenable),gr3
- setlo.p %lo(__entry_kernel_external_interrupt_virtual_reenable),gr3
- beq icc0,#2,__break_step_kernel_external_interrupt_virtually_disabled
- subcc gr2,gr3,gr0,icc0
- beq icc0,#2,__break_step_kernel_external_interrupt_virtual_reenable
-
- LEDS 0x2007,gr2
-
- # the two main vector tables are adjacent on one 8Kb slab
- movsg bpcsr,gr2
- setlos #0xffffe000,gr3
- and gr2,gr3,gr2
- sethi.p %hi(__trap_tables),gr3
- setlo %lo(__trap_tables),gr3
- subcc gr2,gr3,gr0,icc0
- bne icc0,#2,__break_continue
-
- LEDS 0x200f,gr2
-
- # skip workaround if so requested by GDB
- sethi.p %hi(__break_trace_through_exceptions),gr3
- setlo %lo(__break_trace_through_exceptions),gr3
- ld @(gr3,gr0),gr3
- subcc gr3,gr0,gr0,icc0
- bne icc0,#0,__break_continue
-
- LEDS 0x201f,gr2
-
- # access the fixup table - there's a 1:1 mapping between the slots in the trap tables and
- # the slots in the trap fixup tables allowing us to simply divide the offset into the
- # former by 4 to access the latter
- sethi.p %hi(__trap_tables),gr3
- setlo %lo(__trap_tables),gr3
- movsg bpcsr,gr2
- sub gr2,gr3,gr2
- srli.p gr2,#2,gr2
-
- sethi %hi(__trap_fixup_tables),gr3
- setlo.p %lo(__trap_fixup_tables),gr3
- andi gr2,#~3,gr2
- ld @(gr2,gr3),gr2
- jmpil @(gr2,#0)
-
-# step through an internal exception from kernel mode
- .globl __break_step_kernel_softprog_interrupt
-__break_step_kernel_softprog_interrupt:
- sethi.p %hi(__entry_kernel_softprog_interrupt_reentry),gr3
- setlo %lo(__entry_kernel_softprog_interrupt_reentry),gr3
- bra __break_return_as_kernel_prologue
-
-# step through an external interrupt from kernel mode
- .globl __break_step_kernel_external_interrupt
-__break_step_kernel_external_interrupt:
- # deal with virtual interrupt disablement
- beq icc2,#0,__break_step_kernel_external_interrupt_virtually_disabled
-
- sethi.p %hi(__entry_kernel_external_interrupt_reentry),gr3
- setlo %lo(__entry_kernel_external_interrupt_reentry),gr3
-
-__break_return_as_kernel_prologue:
- LEDS 0x203f,gr2
-
- movgs gr3,bpcsr
-
- # do the bit we had to skip
-#ifdef CONFIG_MMU
- movsg ear0,gr2 /* EAR0 can get clobbered by gdb-stub (ICI/ICEI) */
- movgs gr2,scr2
-#endif
-
- or.p sp,gr0,gr2 /* set up the stack pointer */
- subi sp,#REG__END,sp
- sti.p gr2,@(sp,#REG_SP)
-
- setlos #REG__STATUS_STEP,gr2
- sti gr2,@(sp,#REG__STATUS) /* record single step status */
-
- # cancel single-stepping mode
- movsg dcr,gr2
- sethi.p %hi(~DCR_SE),gr3
- setlo %lo(~DCR_SE),gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
-
- LEDS 0x207f,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-# we single-stepped into an interrupt handler whilst interrupts were merely virtually disabled
-# need to really disable interrupts, set flag, fix up and return
-__break_step_kernel_external_interrupt_virtually_disabled:
- movsg psr,gr2
- andi gr2,#~PSR_PIL,gr2
- ori gr2,#PSR_PIL_14,gr2 /* debugging interrupts only */
- movgs gr2,psr
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- subcc.p gr0,gr0,gr0,icc2 /* leave Z set, clear C */
-
- # exceptions must've been enabled and we must've been in supervisor mode
- setlos BPSR_BET|BPSR_BS,gr3
- movgs gr3,bpsr
-
- # return to where the interrupt happened
- movsg pcsr,gr2
- movgs gr2,bpcsr
-
- lddi.p @(gr31,#REG_GR(2)),gr2
-
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-# we stepped through into the virtual interrupt reenablement trap
-#
-# we also want to single step anyway, but after fixing up so that we get an event on the
-# instruction after the broken-into exception returns
- .globl __break_step_kernel_external_interrupt_virtual_reenable
-__break_step_kernel_external_interrupt_virtual_reenable:
- movsg psr,gr2
- andi gr2,#~PSR_PIL,gr2
- movgs gr2,psr
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- subicc gr0,#1,gr0,icc2 /* clear Z, set C */
-
- # save the adjusted ICC2
- movsg ccr,gr3
- sti gr3,@(gr31,#REG_CCR)
-
- # exceptions must've been enabled and we must've been in supervisor mode
- setlos BPSR_BET|BPSR_BS,gr3
- movgs gr3,bpsr
-
- # return to where the trap happened
- movsg pcsr,gr2
- movgs gr2,bpcsr
-
- # and then process the single step
- bra __break_continue
-
-# step through an internal exception from uspace mode
- .globl __break_step_uspace_softprog_interrupt
-__break_step_uspace_softprog_interrupt:
- sethi.p %hi(__entry_uspace_softprog_interrupt_reentry),gr3
- setlo %lo(__entry_uspace_softprog_interrupt_reentry),gr3
- bra __break_return_as_uspace_prologue
-
-# step through an external interrupt from kernel mode
- .globl __break_step_uspace_external_interrupt
-__break_step_uspace_external_interrupt:
- sethi.p %hi(__entry_uspace_external_interrupt_reentry),gr3
- setlo %lo(__entry_uspace_external_interrupt_reentry),gr3
-
-__break_return_as_uspace_prologue:
- LEDS 0x20ff,gr2
-
- movgs gr3,bpcsr
-
- # do the bit we had to skip
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi.p @(gr28,#0),gr28
-
- setlos #REG__STATUS_STEP,gr2
- sti gr2,@(gr28,#REG__STATUS) /* record single step status */
-
- # cancel single-stepping mode
- movsg dcr,gr2
- sethi.p %hi(~DCR_SE),gr3
- setlo %lo(~DCR_SE),gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
-
- LEDS 0x20fe,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-#ifdef CONFIG_MMU
-# step through an ITLB-miss handler from user mode
- .globl __break_user_insn_tlb_miss
-__break_user_insn_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_user_insn_tlb_miss),gr2
- setlo %lo(__trap_user_insn_tlb_miss),gr2
- movgs gr2,bpcsr
-
-__break_tlb_miss_common:
- LEDS 0x2101,gr2
-
- # cancel single-stepping mode
- movsg dcr,gr2
- sethi.p %hi(~DCR_SE),gr3
- setlo %lo(~DCR_SE),gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
-
- # we'll swap the real return address for one with a BREAK insn so that we can re-enable
- # single stepping on return
- movsg pcsr,gr2
- sethi.p %hi(__break_tlb_miss_real_return_info),gr3
- setlo %lo(__break_tlb_miss_real_return_info),gr3
- sti gr2,@(gr3,#0)
-
- sethi.p %hi(__break_tlb_miss_return_break),gr2
- setlo %lo(__break_tlb_miss_return_break),gr2
- movgs gr2,pcsr
-
- # we also have to fudge PSR because the return BREAK is in kernel space and we want
- # to get a BREAK fault not an access violation should the return be to userspace
- movsg psr,gr2
- sti.p gr2,@(gr3,#4)
- ori gr2,#PSR_PS,gr2
- movgs gr2,psr
-
- LEDS 0x2102,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi @(gr31,#REG_GR(2)),gr2
- movsg scr3,gr31
- movgs gr0,brr
- rett #1
-
-# step through a DTLB-miss handler from user mode
- .globl __break_user_data_tlb_miss
-__break_user_data_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_user_data_tlb_miss),gr2
- setlo %lo(__trap_user_data_tlb_miss),gr2
- movgs gr2,bpcsr
- bra __break_tlb_miss_common
-
-# step through an ITLB-miss handler from kernel mode
- .globl __break_kernel_insn_tlb_miss
-__break_kernel_insn_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_kernel_insn_tlb_miss),gr2
- setlo %lo(__trap_kernel_insn_tlb_miss),gr2
- movgs gr2,bpcsr
- bra __break_tlb_miss_common
-
-# step through a DTLB-miss handler from kernel mode
- .globl __break_kernel_data_tlb_miss
-__break_kernel_data_tlb_miss:
- # we'll want to try the trap stub again
- sethi.p %hi(__trap_kernel_data_tlb_miss),gr2
- setlo %lo(__trap_kernel_data_tlb_miss),gr2
- movgs gr2,bpcsr
- bra __break_tlb_miss_common
-#endif
-
-###############################################################################
-#
-# handle debug events originating with userspace
-#
-###############################################################################
-__break_maybe_userspace:
- LEDS 0x3003,gr2
-
- setlos #BPSR_BS,gr2
- andcc gr3,gr2,gr0,icc0
- bne icc0,#0,__break_continue /* skip if PSR.S was 1 */
-
- movsg brr,gr2
- andicc gr2,#BRR_ST|BRR_SB,gr0,icc0
- beq icc0,#0,__break_continue /* jump if not BREAK or single-step */
-
- LEDS 0x3007,gr2
-
- # do the first part of the exception prologue here
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
- andi gr28,#~7,gr28
-
- # set up the kernel stack pointer
- sti sp ,@(gr28,#REG_SP)
- ori gr28,0,sp
- sti gr0 ,@(gr28,#REG_GR(28))
-
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
-
- movsg tbr,gr20
- movsg bpcsr,gr21
- movsg psr,gr22
-
- # determine the exception type and cancel single-stepping mode
- or gr0,gr0,gr23
-
- movsg dcr,gr2
- sethi.p %hi(DCR_SE),gr3
- setlo %lo(DCR_SE),gr3
- andcc gr2,gr3,gr0,icc0
- beq icc0,#0,__break_no_user_sstep /* must have been a BREAK insn */
-
- not gr3,gr3
- and gr2,gr3,gr2
- movgs gr2,dcr
- ori gr23,#REG__STATUS_STEP,gr23
-
-__break_no_user_sstep:
- LEDS 0x300f,gr2
-
- movsg brr,gr2
- andi gr2,#BRR_ST|BRR_SB,gr2
- slli gr2,#1,gr2
- or gr23,gr2,gr23
- sti.p gr23,@(gr28,#REG__STATUS) /* record single step status */
-
- # adjust the value acquired from TBR - this indicates the exception
- setlos #~TBR_TT,gr2
- and.p gr20,gr2,gr20
- setlos #TBR_TT_BREAK,gr2
- or.p gr20,gr2,gr20
-
- # fudge PSR.PS and BPSR.BS to return to kernel mode through the trap
- # table as trap 126
- andi gr22,#~PSR_PS,gr22 /* PSR.PS should be 0 */
- movgs gr22,psr
-
- setlos #BPSR_BS,gr2 /* BPSR.BS should be 1 and BPSR.BET 0 */
- movgs gr2,bpsr
-
- # return through remainder of the exception prologue
- # - need to load gr23 with return handler address
- sethi.p %hi(__entry_return_from_user_exception),gr23
- setlo %lo(__entry_return_from_user_exception),gr23
- sethi.p %hi(__entry_common),gr3
- setlo %lo(__entry_common),gr3
- movgs gr3,bpcsr
-
- LEDS 0x301f,gr2
-
- ldi @(gr31,#REG_CCR),gr3
- movgs gr3,ccr
- lddi.p @(gr31,#REG_GR(2)),gr2
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-###############################################################################
-#
-# resume normal debug-mode entry
-#
-###############################################################################
-__break_continue:
- LEDS 0x4003,gr2
-
- # set up the kernel stack pointer
- sti sp,@(gr31,#REG_SP)
-
- sethi.p %hi(__break_frame_0),sp
- setlo %lo(__break_frame_0),sp
-
- # finish building the exception frame
- stdi gr4 ,@(gr31,#REG_GR(4))
- stdi gr6 ,@(gr31,#REG_GR(6))
- stdi gr8 ,@(gr31,#REG_GR(8))
- stdi gr10,@(gr31,#REG_GR(10))
- stdi gr12,@(gr31,#REG_GR(12))
- stdi gr14,@(gr31,#REG_GR(14))
- stdi gr16,@(gr31,#REG_GR(16))
- stdi gr18,@(gr31,#REG_GR(18))
- stdi gr20,@(gr31,#REG_GR(20))
- stdi gr22,@(gr31,#REG_GR(22))
- stdi gr24,@(gr31,#REG_GR(24))
- stdi gr26,@(gr31,#REG_GR(26))
- sti gr0 ,@(gr31,#REG_GR(28)) /* NULL frame pointer */
- sti gr29,@(gr31,#REG_GR(29))
- sti gr30,@(gr31,#REG_GR(30))
- sti gr8 ,@(gr31,#REG_ORIG_GR8)
-
-#ifdef CONFIG_MMU
- movsg scr3,gr19
- sti gr19,@(gr31,#REG_GR(31))
-#endif
-
- movsg bpsr ,gr19
- movsg tbr ,gr20
- movsg bpcsr,gr21
- movsg psr ,gr22
- movsg isr ,gr23
- movsg cccr ,gr25
- movsg lr ,gr26
- movsg lcr ,gr27
-
- andi.p gr22,#~(PSR_S|PSR_ET),gr5 /* rebuild PSR */
- andi gr19,#PSR_ET,gr4
- or.p gr4,gr5,gr5
- srli gr19,#10,gr4
- andi gr4,#PSR_S,gr4
- or.p gr4,gr5,gr5
-
- setlos #-1,gr6
- sti gr20,@(gr31,#REG_TBR)
- sti gr21,@(gr31,#REG_PC)
- sti gr5 ,@(gr31,#REG_PSR)
- sti gr23,@(gr31,#REG_ISR)
- sti gr25,@(gr31,#REG_CCCR)
- stdi gr26,@(gr31,#REG_LR)
- sti gr6 ,@(gr31,#REG_SYSCALLNO)
-
- # store CPU-specific regs
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr31,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi gr4,@(gr31,#REG_GNER0)
-
- # build the debug register frame
- movsg brr,gr4
- movgs gr0,brr
- movsg nmar,gr5
- movsg dcr,gr6
-
- sethi.p %hi(__debug_status),gr7
- setlo %lo(__debug_status),gr7
-
- stdi gr4 ,@(gr7,#DEBUG_BRR)
- sti gr19,@(gr7,#DEBUG_BPSR)
- sti.p gr6 ,@(gr7,#DEBUG_DCR)
-
- # trap exceptions during break handling and disable h/w breakpoints/watchpoints
- sethi %hi(DCR_EBE),gr5
- setlo.p %lo(DCR_EBE),gr5
- sethi %hi(__entry_breaktrap_table),gr4
- setlo %lo(__entry_breaktrap_table),gr4
- movgs gr5,dcr
- movgs gr4,tbr
-
- # set up kernel global registers
- sethi.p %hi(__kernel_current_task),gr5
- setlo %lo(__kernel_current_task),gr5
- ld @(gr5,gr0),gr29
- ldi.p @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
-
- sethi %hi(_gp),gr16
- setlo.p %lo(_gp),gr16
-
- # make sure we (the kernel) get div-zero and misalignment exceptions
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # enter the GDB stub
- LEDS 0x4007,gr2
-
- or.p gr0,gr0,fp
- call debug_stub
-
- LEDS 0x403f,gr2
-
- # return from break
- lddi @(gr31,#REG_IACC0),gr4
- movgs gr4,iacc0h
- movgs gr5,iacc0l
-
- lddi @(gr31,#REG_GNER0),gr4
- movgs gr4,gner0
- movgs gr5,gner1
-
- lddi @(gr31,#REG_LR) ,gr26
- lddi @(gr31,#REG_CCR) ,gr24
- lddi @(gr31,#REG_PSR) ,gr22
- ldi @(gr31,#REG_PC) ,gr21
- ldi @(gr31,#REG_TBR) ,gr20
-
- sethi.p %hi(__debug_status),gr6
- setlo %lo(__debug_status),gr6
- ldi.p @(gr6,#DEBUG_DCR) ,gr6
-
- andi gr22,#PSR_S,gr19 /* rebuild BPSR */
- andi.p gr22,#PSR_ET,gr5
- slli gr19,#10,gr19
- or gr5,gr19,gr19
-
- movgs gr6 ,dcr
- movgs gr19,bpsr
- movgs gr20,tbr
- movgs gr21,bpcsr
- movgs gr23,isr
- movgs gr24,ccr
- movgs gr25,cccr
- movgs gr26,lr
- movgs gr27,lcr
-
- LEDS 0x407f,gr2
-
-#ifdef CONFIG_MMU
- ldi @(gr31,#REG_GR(31)),gr2
- movgs gr2,scr3
-#endif
-
- ldi @(gr31,#REG_GR(30)),gr30
- ldi @(gr31,#REG_GR(29)),gr29
- lddi @(gr31,#REG_GR(26)),gr26
- lddi @(gr31,#REG_GR(24)),gr24
- lddi @(gr31,#REG_GR(22)),gr22
- lddi @(gr31,#REG_GR(20)),gr20
- lddi @(gr31,#REG_GR(18)),gr18
- lddi @(gr31,#REG_GR(16)),gr16
- lddi @(gr31,#REG_GR(14)),gr14
- lddi @(gr31,#REG_GR(12)),gr12
- lddi @(gr31,#REG_GR(10)),gr10
- lddi @(gr31,#REG_GR(8)) ,gr8
- lddi @(gr31,#REG_GR(6)) ,gr6
- lddi @(gr31,#REG_GR(4)) ,gr4
- lddi @(gr31,#REG_GR(2)) ,gr2
- ldi.p @(gr31,#REG_SP) ,sp
-
- xor gr31,gr31,gr31
- movgs gr0,brr
-#ifdef CONFIG_MMU
- movsg scr3,gr31
-#endif
- rett #1
-
-###################################################################################################
-#
-# GDB stub "system calls"
-#
-###################################################################################################
-
-#ifdef CONFIG_GDBSTUB
- # void gdbstub_console_write(struct console *con, const char *p, unsigned n)
- .globl gdbstub_console_write
-gdbstub_console_write:
- break
- bralr
-#endif
-
- # GDB stub BUG() trap
- # GR8 is the proposed signal number
- .globl __debug_bug_trap
-__debug_bug_trap:
- break
- bralr
-
- # transfer kernel exeception to GDB for handling
- .globl __break_hijack_kernel_event
-__break_hijack_kernel_event:
- break
- .globl __break_hijack_kernel_event_breaks_here
-__break_hijack_kernel_event_breaks_here:
- nop
-
-#ifdef CONFIG_MMU
- # handle a return from TLB-miss that requires single-step reactivation
- .globl __break_tlb_miss_return_break
-__break_tlb_miss_return_break:
- break
-__break_tlb_miss_return_breaks_here:
- nop
-#endif
-
- # guard the first .text label in the next file from confusion
- nop
diff --git a/arch/frv/kernel/cmode.S b/arch/frv/kernel/cmode.S
deleted file mode 100644
index 53deeb5d7e87..000000000000
--- a/arch/frv/kernel/cmode.S
+++ /dev/null
@@ -1,189 +0,0 @@
-/* cmode.S: clock mode management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Woodhouse (dwmw2@infradead.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/ptrace.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <asm/spr-regs.h>
-
-#define __addr_MASK 0xfeff9820 /* interrupt controller mask */
-
-#define __addr_SDRAMC 0xfe000400 /* SDRAM controller regs */
-#define SDRAMC_DSTS 0x28 /* SDRAM status */
-#define SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
-#define SDRAMC_DRCN 0x30 /* SDRAM refresh control */
-#define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
-#define __addr_CLKC 0xfeff9a00
-#define CLKC_SWCMODE 0x00000008
-#define __addr_LEDS 0xe1200004
-
-.macro li v r
- sethi.p %hi(\v),\r
- setlo %lo(\v),\r
-.endm
-
- .text
- .balign 4
-
-
-###############################################################################
-#
-# Change CMODE
-# - void frv_change_cmode(int cmode)
-#
-###############################################################################
- .globl frv_change_cmode
- .type frv_change_cmode,@function
-
-.macro LEDS v
-#ifdef DEBUG_CMODE
- setlos #~\v,gr10
- sti gr10,@(gr11,#0)
- membar
-#endif
-.endm
-
-frv_change_cmode:
- movsg lr,gr9
-#ifdef DEBUG_CMODE
- li __addr_LEDS,gr11
-#endif
- dcef @(gr0,gr0),#1
-
- # Shift argument left by 24 bits to fit in SWCMODE register later.
- slli gr8,#24,gr8
-
- # (1) Set '0' in the PSR.ET bit, and prohibit interrupts.
- movsg psr,gr14
- andi gr14,#~PSR_ET,gr3
- movgs gr3,psr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (2) Set '0' to all bits of the MASK register of the interrupt
- # controller, and mask interrupts.
- li __addr_MASK,gr12
- ldi @(gr12,#0),gr13
- li 0xffff0000,gr4
- sti gr4,@(gr12,#0)
-#endif
-
- # (3) Stop the transfer function of DMAC. Stop all the bus masters
- # to access SDRAM and the internal resources.
-
- # (already done by caller)
-
- # (4) Preload a series of following instructions to the instruction
- # cache.
- li #__cmode_icache_lock_start,gr3
- li #__cmode_icache_lock_end,gr4
-
-1: icpl gr3,gr0,#1
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- # Set up addresses in regs for later steps.
- setlos SDRAMC_DRCN_SR,gr3
- li __addr_SDRAMC,gr4
- li __addr_CLKC,gr5
- ldi @(gr5,#0),gr6
- li #0x80000000,gr7
- or gr6,gr7,gr6
-
- bra __cmode_icache_lock_start
-
- .balign L1_CACHE_BYTES
-__cmode_icache_lock_start:
-
- # (5) Flush the content of all caches by the DCEF instruction.
- dcef @(gr0,gr0),#1
-
- # (6) Execute loading the dummy for SDRAM.
- ldi @(gr9,#0),gr0
-
- # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
- # self-refresh mode. Execute the dummy load to all memory
- # devices set to cacheable on the external bus side in parallel
- # with this.
- sti gr3,@(gr4,#SDRAMC_DRCN)
-
- # (8) Execute memory barrier instruction (MEMBAR).
- membar
-
- # (9) Read the DSTS register repeatedly until '1' stands in the
- # DSTS.SSI field.
-1: ldi @(gr4,#SDRAMC_DSTS),gr3
- andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
- beq icc0,#0,1b
-
- # (10) Execute memory barrier instruction (MEMBAR).
- membar
-
-#if 1
- # (11) Set the value of CMODE that you want to change to
- # SWCMODE.SWCM[3:0].
- sti gr8,@(gr5,#CLKC_SWCMODE)
-
- # (12) Set '1' to the CLKC.SWEN bit. In that case, do not change
- # fields other than SWEN of the CLKC register.
- sti gr6,@(gr5,#0)
-#endif
- # (13) Execute the instruction just after the memory barrier
- # instruction that executes the self-loop 256 times. (Meanwhile,
- # the CMODE switch is done.)
- membar
- setlos #256,gr7
-2: subicc gr7,#1,gr7,icc0
- bne icc0,#2,2b
-
- LEDS 0x36
-
- # (14) Release the self-refresh of SDRAM.
- sti gr0,@(gr4,#SDRAMC_DRCN)
-
- # Wait for it...
-3: ldi @(gr4,#SDRAMC_DSTS),gr3
- andicc gr3,#SDRAMC_DSTS_SSI,gr3,icc0
- bne icc0,#2,3b
-
-#if 0
- li 0x0100000,gr10
-4: subicc gr10,#1,gr10,icc0
-
- bne icc0,#0,4b
-#endif
-
-__cmode_icache_lock_end:
-
- li #__cmode_icache_lock_start,gr3
- li #__cmode_icache_lock_end,gr4
-
-4: icul gr3
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,4b
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (15) Release the interrupt mask setting of the MASK register of
- # the interrupt controller if necessary.
- sti gr13,@(gr12,#0)
-#endif
- # (16) Set 1' in the PSR.ET bit, and permit interrupt.
- movgs gr14,psr
-
- bralr
-
- .size frv_change_cmode, .-frv_change_cmode
diff --git a/arch/frv/kernel/debug-stub.c b/arch/frv/kernel/debug-stub.c
deleted file mode 100644
index a0228f717ef2..000000000000
--- a/arch/frv/kernel/debug-stub.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* debug-stub.c: debug-mode stub
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/serial_reg.h>
-#include <linux/start_kernel.h>
-
-#include <asm/serial-regs.h>
-#include <asm/timer-regs.h>
-#include <asm/irc-regs.h>
-#include <asm/gdb-stub.h>
-#include "gdb-io.h"
-
-/* CPU board CON5 */
-#define __UART0(X) (*(volatile uint8_t *)(UART0_BASE + (UART_##X)))
-
-#define LSR_WAIT_FOR0(STATE) \
-do { \
-} while (!(__UART0(LSR) & UART_LSR_##STATE))
-
-#define FLOWCTL_QUERY0(LINE) ({ __UART0(MSR) & UART_MSR_##LINE; })
-#define FLOWCTL_CLEAR0(LINE) do { __UART0(MCR) &= ~UART_MCR_##LINE; } while (0)
-#define FLOWCTL_SET0(LINE) do { __UART0(MCR) |= UART_MCR_##LINE; } while (0)
-
-#define FLOWCTL_WAIT_FOR0(LINE) \
-do { \
- gdbstub_do_rx(); \
-} while(!FLOWCTL_QUERY(LINE))
-
-struct frv_debug_status __debug_status;
-
-static void __init debug_stub_init(void);
-
-/*****************************************************************************/
-/*
- * debug mode handler stub
- * - we come here with the CPU in debug mode and with exceptions disabled
- * - handle debugging services for userspace
- */
-asmlinkage void debug_stub(void)
-{
- unsigned long hsr0;
- int type = 0;
-
- static u8 inited = 0;
- if (!inited) {
- debug_stub_init();
- type = -1;
- inited = 1;
- }
-
- hsr0 = __get_HSR(0);
- if (hsr0 & HSR0_ETMD)
- __set_HSR(0, hsr0 & ~HSR0_ETMD);
-
- /* disable single stepping */
- __debug_status.dcr &= ~DCR_SE;
-
- /* kernel mode can propose an exception be handled in debug mode by jumping to a special
- * location */
- if (__debug_frame->pc == (unsigned long) __break_hijack_kernel_event_breaks_here) {
- /* replace the debug frame with the kernel frame and discard
- * the top kernel context */
- *__debug_frame = *__frame;
- __frame = __debug_frame->next_frame;
- __debug_status.brr = (__debug_frame->tbr & TBR_TT) << 12;
- __debug_status.brr |= BRR_EB;
- }
-
- if (__debug_frame->pc == (unsigned long) __debug_bug_trap + 4) {
- __debug_frame->pc = __debug_frame->lr;
- type = __debug_frame->gr8;
- }
-
-#ifdef CONFIG_GDBSTUB
- gdbstub(type);
-#endif
-
- if (hsr0 & HSR0_ETMD)
- __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
-
-} /* end debug_stub() */
-
-/*****************************************************************************/
-/*
- * debug stub initialisation
- */
-static void __init debug_stub_init(void)
-{
- __set_IRR(6, 0xff000000); /* map ERRs to NMI */
- __set_IITMR(1, 0x20000000); /* ERR0/1, UART0/1 IRQ detect levels */
-
- asm volatile(" movgs gr0,ibar0 \n"
- " movgs gr0,ibar1 \n"
- " movgs gr0,ibar2 \n"
- " movgs gr0,ibar3 \n"
- " movgs gr0,dbar0 \n"
- " movgs gr0,dbmr00 \n"
- " movgs gr0,dbmr01 \n"
- " movgs gr0,dbdr00 \n"
- " movgs gr0,dbdr01 \n"
- " movgs gr0,dbar1 \n"
- " movgs gr0,dbmr10 \n"
- " movgs gr0,dbmr11 \n"
- " movgs gr0,dbdr10 \n"
- " movgs gr0,dbdr11 \n"
- );
-
- /* deal with debugging stub initialisation and initial pause */
- if (__debug_frame->pc == (unsigned long) __debug_stub_init_break)
- __debug_frame->pc = (unsigned long) start_kernel;
-
- /* enable the debug events we want to trap */
- __debug_status.dcr = DCR_EBE;
-
-#ifdef CONFIG_GDBSTUB
- gdbstub_init();
-#endif
-
- __clr_MASK_all();
- __clr_MASK(15);
- __clr_RC(15);
-
-} /* end debug_stub_init() */
-
-/*****************************************************************************/
-/*
- * kernel "exit" trap for gdb stub
- */
-void debug_stub_exit(int status)
-{
-
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(status);
-#endif
-
-} /* end debug_stub_exit() */
-
-/*****************************************************************************/
-/*
- * send string to serial port
- */
-void debug_to_serial(const char *p, int n)
-{
- char ch;
-
- for (; n > 0; n--) {
- ch = *p++;
- FLOWCTL_SET0(DTR);
- LSR_WAIT_FOR0(THRE);
- // FLOWCTL_WAIT_FOR(CTS);
-
- if (ch == 0x0a) {
- __UART0(TX) = 0x0d;
- mb();
- LSR_WAIT_FOR0(THRE);
- // FLOWCTL_WAIT_FOR(CTS);
- }
- __UART0(TX) = ch;
- mb();
-
- FLOWCTL_CLEAR0(DTR);
- }
-
-} /* end debug_to_serial() */
-
-/*****************************************************************************/
-/*
- * send string to serial port
- */
-void debug_to_serial2(const char *fmt, ...)
-{
- va_list va;
- char buf[64];
- int n;
-
- va_start(va, fmt);
- n = vsprintf(buf, fmt, va);
- va_end(va);
-
- debug_to_serial(buf, n);
-
-} /* end debug_to_serial2() */
-
-/*****************************************************************************/
-/*
- * set up the ttyS0 serial port baud rate timers
- */
-void __init console_set_baud(unsigned baud)
-{
- unsigned value, high, low;
- u8 lcr;
-
- /* work out the divisor to give us the nearest higher baud rate */
- value = __serial_clock_speed_HZ / 16 / baud;
-
- /* determine the baud rate range */
- high = __serial_clock_speed_HZ / 16 / value;
- low = __serial_clock_speed_HZ / 16 / (value + 1);
-
- /* pick the nearest bound */
- if (low + (high - low) / 2 > baud)
- value++;
-
- lcr = __UART0(LCR);
- __UART0(LCR) |= UART_LCR_DLAB;
- mb();
- __UART0(DLL) = value & 0xff;
- __UART0(DLM) = (value >> 8) & 0xff;
- mb();
- __UART0(LCR) = lcr;
- mb();
-
-} /* end console_set_baud() */
-
-/*****************************************************************************/
-/*
- *
- */
-int __init console_get_baud(void)
-{
- unsigned value;
- u8 lcr;
-
- lcr = __UART0(LCR);
- __UART0(LCR) |= UART_LCR_DLAB;
- mb();
- value = __UART0(DLM) << 8;
- value |= __UART0(DLL);
- __UART0(LCR) = lcr;
- mb();
-
- return value;
-} /* end console_get_baud() */
-
-/*****************************************************************************/
-/*
- * display BUG() info
- */
-#ifndef CONFIG_NO_KERNEL_MSG
-void __debug_bug_printk(const char *file, unsigned line)
-{
- printk("kernel BUG at %s:%d!\n", file, line);
-
-} /* end __debug_bug_printk() */
-#endif
diff --git a/arch/frv/kernel/dma.c b/arch/frv/kernel/dma.c
deleted file mode 100644
index 370dc9fa0b11..000000000000
--- a/arch/frv/kernel/dma.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/* dma.c: DMA controller management on FR401 and the like
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <asm/dma.h>
-#include <asm/gpio-regs.h>
-#include <asm/irc-regs.h>
-#include <asm/cpu-irqs.h>
-
-struct frv_dma_channel {
- uint8_t flags;
-#define FRV_DMA_FLAGS_RESERVED 0x01
-#define FRV_DMA_FLAGS_INUSE 0x02
-#define FRV_DMA_FLAGS_PAUSED 0x04
- uint8_t cap; /* capabilities available */
- int irq; /* completion IRQ */
- uint32_t dreqbit;
- uint32_t dackbit;
- uint32_t donebit;
- const unsigned long ioaddr; /* DMA controller regs addr */
- const char *devname;
- dma_irq_handler_t handler;
- void *data;
-};
-
-
-#define __get_DMAC(IO,X) ({ *(volatile unsigned long *)((IO) + DMAC_##X##x); })
-
-#define __set_DMAC(IO,X,V) \
-do { \
- *(volatile unsigned long *)((IO) + DMAC_##X##x) = (V); \
- mb(); \
-} while(0)
-
-#define ___set_DMAC(IO,X,V) \
-do { \
- *(volatile unsigned long *)((IO) + DMAC_##X##x) = (V); \
-} while(0)
-
-
-static struct frv_dma_channel frv_dma_channels[FRV_DMA_NCHANS] = {
- [0] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK | FRV_DMA_CAP_DONE,
- .irq = IRQ_CPU_DMA0,
- .dreqbit = SIR_DREQ0_INPUT,
- .dackbit = SOR_DACK0_OUTPUT,
- .donebit = SOR_DONE0_OUTPUT,
- .ioaddr = 0xfe000900,
- },
- [1] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK | FRV_DMA_CAP_DONE,
- .irq = IRQ_CPU_DMA1,
- .dreqbit = SIR_DREQ1_INPUT,
- .dackbit = SOR_DACK1_OUTPUT,
- .donebit = SOR_DONE1_OUTPUT,
- .ioaddr = 0xfe000980,
- },
- [2] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK,
- .irq = IRQ_CPU_DMA2,
- .dreqbit = SIR_DREQ2_INPUT,
- .dackbit = SOR_DACK2_OUTPUT,
- .ioaddr = 0xfe000a00,
- },
- [3] = {
- .cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK,
- .irq = IRQ_CPU_DMA3,
- .dreqbit = SIR_DREQ3_INPUT,
- .dackbit = SOR_DACK3_OUTPUT,
- .ioaddr = 0xfe000a80,
- },
- [4] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA4,
- .dreqbit = SIR_DREQ4_INPUT,
- .ioaddr = 0xfe001000,
- },
- [5] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA5,
- .dreqbit = SIR_DREQ5_INPUT,
- .ioaddr = 0xfe001080,
- },
- [6] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA6,
- .dreqbit = SIR_DREQ6_INPUT,
- .ioaddr = 0xfe001100,
- },
- [7] = {
- .cap = FRV_DMA_CAP_DREQ,
- .irq = IRQ_CPU_DMA7,
- .dreqbit = SIR_DREQ7_INPUT,
- .ioaddr = 0xfe001180,
- },
-};
-
-static DEFINE_RWLOCK(frv_dma_channels_lock);
-
-unsigned int frv_dma_inprogress;
-
-#define frv_clear_dma_inprogress(channel) \
- (void)__atomic32_fetch_and(~(1 << (channel)), &frv_dma_inprogress);
-
-#define frv_set_dma_inprogress(channel) \
- (void)__atomic32_fetch_or(1 << (channel), &frv_dma_inprogress);
-
-/*****************************************************************************/
-/*
- * DMA irq handler - determine channel involved, grab status and call real handler
- */
-static irqreturn_t dma_irq_handler(int irq, void *_channel)
-{
- struct frv_dma_channel *channel = _channel;
-
- frv_clear_dma_inprogress(channel - frv_dma_channels);
- return channel->handler(channel - frv_dma_channels,
- __get_DMAC(channel->ioaddr, CSTR),
- channel->data);
-
-} /* end dma_irq_handler() */
-
-/*****************************************************************************/
-/*
- * Determine which DMA controllers are present on this CPU
- */
-void __init frv_dma_init(void)
-{
- unsigned long psr = __get_PSR();
- int num_dma, i;
-
- /* First, determine how many DMA channels are available */
- switch (PSR_IMPLE(psr)) {
- case PSR_IMPLE_FR405:
- case PSR_IMPLE_FR451:
- case PSR_IMPLE_FR501:
- case PSR_IMPLE_FR551:
- num_dma = FRV_DMA_8CHANS;
- break;
-
- case PSR_IMPLE_FR401:
- default:
- num_dma = FRV_DMA_4CHANS;
- break;
- }
-
- /* Now mark all of the non-existent channels as reserved */
- for(i = num_dma; i < FRV_DMA_NCHANS; i++)
- frv_dma_channels[i].flags = FRV_DMA_FLAGS_RESERVED;
-
-} /* end frv_dma_init() */
-
-/*****************************************************************************/
-/*
- * allocate a DMA controller channel and the IRQ associated with it
- */
-int frv_dma_open(const char *devname,
- unsigned long dmamask,
- int dmacap,
- dma_irq_handler_t handler,
- unsigned long irq_flags,
- void *data)
-{
- struct frv_dma_channel *channel;
- int dma, ret;
- uint32_t val;
-
- write_lock(&frv_dma_channels_lock);
-
- ret = -ENOSPC;
-
- for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
- channel = &frv_dma_channels[dma];
-
- if (!test_bit(dma, &dmamask))
- continue;
-
- if ((channel->cap & dmacap) != dmacap)
- continue;
-
- if (!frv_dma_channels[dma].flags)
- goto found;
- }
-
- goto out;
-
- found:
- ret = request_irq(channel->irq, dma_irq_handler, irq_flags, devname, channel);
- if (ret < 0)
- goto out;
-
- /* okay, we've allocated all the resources */
- channel = &frv_dma_channels[dma];
-
- channel->flags |= FRV_DMA_FLAGS_INUSE;
- channel->devname = devname;
- channel->handler = handler;
- channel->data = data;
-
- /* Now make sure we are set up for DMA and not GPIO */
- /* SIR bit must be set for DMA to work */
- __set_SIR(channel->dreqbit | __get_SIR());
- /* SOR bits depend on what the caller requests */
- val = __get_SOR();
- if(dmacap & FRV_DMA_CAP_DACK)
- val |= channel->dackbit;
- else
- val &= ~channel->dackbit;
- if(dmacap & FRV_DMA_CAP_DONE)
- val |= channel->donebit;
- else
- val &= ~channel->donebit;
- __set_SOR(val);
-
- ret = dma;
- out:
- write_unlock(&frv_dma_channels_lock);
- return ret;
-} /* end frv_dma_open() */
-
-EXPORT_SYMBOL(frv_dma_open);
-
-/*****************************************************************************/
-/*
- * close a DMA channel and its associated interrupt
- */
-void frv_dma_close(int dma)
-{
- struct frv_dma_channel *channel = &frv_dma_channels[dma];
- unsigned long flags;
-
- write_lock_irqsave(&frv_dma_channels_lock, flags);
-
- free_irq(channel->irq, channel);
- frv_dma_stop(dma);
-
- channel->flags &= ~FRV_DMA_FLAGS_INUSE;
-
- write_unlock_irqrestore(&frv_dma_channels_lock, flags);
-} /* end frv_dma_close() */
-
-EXPORT_SYMBOL(frv_dma_close);
-
-/*****************************************************************************/
-/*
- * set static configuration on a DMA channel
- */
-void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- ___set_DMAC(ioaddr, CCFR, ccfr);
- ___set_DMAC(ioaddr, CCTR, cctr);
- ___set_DMAC(ioaddr, APR, apr);
- mb();
-
-} /* end frv_dma_config() */
-
-EXPORT_SYMBOL(frv_dma_config);
-
-/*****************************************************************************/
-/*
- * start a DMA channel
- */
-void frv_dma_start(int dma,
- unsigned long sba, unsigned long dba,
- unsigned long pix, unsigned long six, unsigned long bcl)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- ___set_DMAC(ioaddr, SBA, sba);
- ___set_DMAC(ioaddr, DBA, dba);
- ___set_DMAC(ioaddr, PIX, pix);
- ___set_DMAC(ioaddr, SIX, six);
- ___set_DMAC(ioaddr, BCL, bcl);
- ___set_DMAC(ioaddr, CSTR, 0);
- mb();
-
- __set_DMAC(ioaddr, CCTR, __get_DMAC(ioaddr, CCTR) | DMAC_CCTRx_ACT);
- frv_set_dma_inprogress(dma);
-
-} /* end frv_dma_start() */
-
-EXPORT_SYMBOL(frv_dma_start);
-
-/*****************************************************************************/
-/*
- * restart a DMA channel that's been stopped in circular addressing mode by comparison-end
- */
-void frv_dma_restart_circular(int dma, unsigned long six)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- ___set_DMAC(ioaddr, SIX, six);
- ___set_DMAC(ioaddr, CSTR, __get_DMAC(ioaddr, CSTR) & ~DMAC_CSTRx_CE);
- mb();
-
- __set_DMAC(ioaddr, CCTR, __get_DMAC(ioaddr, CCTR) | DMAC_CCTRx_ACT);
- frv_set_dma_inprogress(dma);
-
-} /* end frv_dma_restart_circular() */
-
-EXPORT_SYMBOL(frv_dma_restart_circular);
-
-/*****************************************************************************/
-/*
- * stop a DMA channel
- */
-void frv_dma_stop(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
- uint32_t cctr;
-
- ___set_DMAC(ioaddr, CSTR, 0);
- cctr = __get_DMAC(ioaddr, CCTR);
- cctr &= ~(DMAC_CCTRx_IE | DMAC_CCTRx_ACT);
- cctr |= DMAC_CCTRx_FC; /* fifo clear */
- __set_DMAC(ioaddr, CCTR, cctr);
- __set_DMAC(ioaddr, BCL, 0);
- frv_clear_dma_inprogress(dma);
-} /* end frv_dma_stop() */
-
-EXPORT_SYMBOL(frv_dma_stop);
-
-/*****************************************************************************/
-/*
- * test interrupt status of DMA channel
- */
-int is_frv_dma_interrupting(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
-
- return __get_DMAC(ioaddr, CSTR) & (1 << 23);
-
-} /* end is_frv_dma_interrupting() */
-
-EXPORT_SYMBOL(is_frv_dma_interrupting);
-
-/*****************************************************************************/
-/*
- * dump data about a DMA channel
- */
-void frv_dma_dump(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
- unsigned long cstr, pix, six, bcl;
-
- cstr = __get_DMAC(ioaddr, CSTR);
- pix = __get_DMAC(ioaddr, PIX);
- six = __get_DMAC(ioaddr, SIX);
- bcl = __get_DMAC(ioaddr, BCL);
-
- printk("DMA[%d] cstr=%lx pix=%lx six=%lx bcl=%lx\n", dma, cstr, pix, six, bcl);
-
-} /* end frv_dma_dump() */
-
-EXPORT_SYMBOL(frv_dma_dump);
-
-/*****************************************************************************/
-/*
- * pause all DMA controllers
- * - called by clock mangling routines
- * - caller must be holding interrupts disabled
- */
-void frv_dma_pause_all(void)
-{
- struct frv_dma_channel *channel;
- unsigned long ioaddr;
- unsigned long cstr, cctr;
- int dma;
-
- write_lock(&frv_dma_channels_lock);
-
- for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
- channel = &frv_dma_channels[dma];
-
- if (!(channel->flags & FRV_DMA_FLAGS_INUSE))
- continue;
-
- ioaddr = channel->ioaddr;
- cctr = __get_DMAC(ioaddr, CCTR);
- if (cctr & DMAC_CCTRx_ACT) {
- cctr &= ~DMAC_CCTRx_ACT;
- __set_DMAC(ioaddr, CCTR, cctr);
-
- do {
- cstr = __get_DMAC(ioaddr, CSTR);
- } while (cstr & DMAC_CSTRx_BUSY);
-
- if (cstr & DMAC_CSTRx_FED)
- channel->flags |= FRV_DMA_FLAGS_PAUSED;
- frv_clear_dma_inprogress(dma);
- }
- }
-
-} /* end frv_dma_pause_all() */
-
-EXPORT_SYMBOL(frv_dma_pause_all);
-
-/*****************************************************************************/
-/*
- * resume paused DMA controllers
- * - called by clock mangling routines
- * - caller must be holding interrupts disabled
- */
-void frv_dma_resume_all(void)
-{
- struct frv_dma_channel *channel;
- unsigned long ioaddr;
- unsigned long cstr, cctr;
- int dma;
-
- for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
- channel = &frv_dma_channels[dma];
-
- if (!(channel->flags & FRV_DMA_FLAGS_PAUSED))
- continue;
-
- ioaddr = channel->ioaddr;
- cstr = __get_DMAC(ioaddr, CSTR);
- cstr &= ~(DMAC_CSTRx_FED | DMAC_CSTRx_INT);
- __set_DMAC(ioaddr, CSTR, cstr);
-
- cctr = __get_DMAC(ioaddr, CCTR);
- cctr |= DMAC_CCTRx_ACT;
- __set_DMAC(ioaddr, CCTR, cctr);
-
- channel->flags &= ~FRV_DMA_FLAGS_PAUSED;
- frv_set_dma_inprogress(dma);
- }
-
- write_unlock(&frv_dma_channels_lock);
-
-} /* end frv_dma_resume_all() */
-
-EXPORT_SYMBOL(frv_dma_resume_all);
-
-/*****************************************************************************/
-/*
- * dma status clear
- */
-void frv_dma_status_clear(int dma)
-{
- unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
- uint32_t cctr;
- ___set_DMAC(ioaddr, CSTR, 0);
-
- cctr = __get_DMAC(ioaddr, CCTR);
-} /* end frv_dma_status_clear() */
-
-EXPORT_SYMBOL(frv_dma_status_clear);
diff --git a/arch/frv/kernel/entry-table.S b/arch/frv/kernel/entry-table.S
deleted file mode 100644
index 06c5ae191e59..000000000000
--- a/arch/frv/kernel/entry-table.S
+++ /dev/null
@@ -1,329 +0,0 @@
-/* entry-table.S: main trap vector tables and exception jump table
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/spr-regs.h>
-
-###############################################################################
-#
-# Declare the main trap and vector tables
-#
-# There are six tables:
-#
-# (1) The trap table for debug mode
-# (2) The trap table for kernel mode
-# (3) The trap table for user mode
-#
-# The CPU jumps to an appropriate slot in the appropriate table to perform
-# exception processing. We have three different tables for the three
-# different CPU modes because there is no hardware differentiation between
-# stack pointers for these three modes, and so we have to invent one when
-# crossing mode boundaries.
-#
-# (4) The exception handler vector table
-#
-# The user and kernel trap tables use the same prologue for normal
-# exception processing. The prologue then jumps to the handler in this
-# table, as indexed by the exception ID from the TBR.
-#
-# (5) The fixup table for kernel-trap single-step
-# (6) The fixup table for user-trap single-step
-#
-# Due to the way single-stepping works on this CPU (single-step is not
-# disabled when crossing exception boundaries, only when in debug mode),
-# we have to catch the single-step event in break.S and jump to the fixup
-# routine pointed to by this table.
-#
-# The linker script places the user mode and kernel mode trap tables on to
-# the same 8Kb page, so that break.S can be more efficient when performing
-# single-step bypass management
-#
-###############################################################################
-
- # trap table for entry from debug mode
- .section .trap.break,"ax"
- .balign 256*16
- .globl __entry_breaktrap_table
-__entry_breaktrap_table:
-
- # trap table for entry from user mode
- .section .trap.user,"ax"
- .balign 256*16
- .globl __entry_usertrap_table
-__entry_usertrap_table:
-
- # trap table for entry from kernel mode
- .section .trap.kernel,"ax"
- .balign 256*16
- .globl __entry_kerneltrap_table
-__entry_kerneltrap_table:
-
- # exception handler jump table
- .section .trap.vector,"ax"
- .balign 256*4
- .globl __entry_vector_table
-__entry_vector_table:
-
- # trap fixup table for single-stepping in user mode
- .section .trap.fixup.user,"a"
- .balign 256*4
- .globl __break_usertrap_fixup_table
-__break_usertrap_fixup_table:
-
- # trap fixup table for single-stepping in user mode
- .section .trap.fixup.kernel,"a"
- .balign 256*4
- .globl __break_kerneltrap_fixup_table
-__break_kerneltrap_fixup_table:
-
- # handler declaration for a software or program interrupt
-.macro VECTOR_SOFTPROG tbr_tt, vec
- .section .trap.user
- .org \tbr_tt
- bra __entry_uspace_softprog_interrupt
- .section .trap.fixup.user
- .org \tbr_tt >> 2
- .long __break_step_uspace_softprog_interrupt
- .section .trap.kernel
- .org \tbr_tt
- bra __entry_kernel_softprog_interrupt
- .section .trap.fixup.kernel
- .org \tbr_tt >> 2
- .long __break_step_kernel_softprog_interrupt
- .section .trap.vector
- .org \tbr_tt >> 2
- .long \vec
-.endm
-
- # handler declaration for a maskable external interrupt
-.macro VECTOR_IRQ tbr_tt, vec
- .section .trap.user
- .org \tbr_tt
- bra __entry_uspace_external_interrupt
- .section .trap.fixup.user
- .org \tbr_tt >> 2
- .long __break_step_uspace_external_interrupt
- .section .trap.kernel
- .org \tbr_tt
- # deal with virtual interrupt disablement
- beq icc2,#0,__entry_kernel_external_interrupt_virtually_disabled
- bra __entry_kernel_external_interrupt
- .section .trap.fixup.kernel
- .org \tbr_tt >> 2
- .long __break_step_kernel_external_interrupt
- .section .trap.vector
- .org \tbr_tt >> 2
- .long \vec
-.endm
-
- # handler declaration for an NMI external interrupt
-.macro VECTOR_NMI tbr_tt, vec
- .section .trap.user
- .org \tbr_tt
- break
- break
- break
- break
- .section .trap.kernel
- .org \tbr_tt
- break
- break
- break
- break
- .section .trap.vector
- .org \tbr_tt >> 2
- .long \vec
-.endm
-
- # handler declaration for an MMU only software or program interrupt
-.macro VECTOR_SP_MMU tbr_tt, vec
-#ifdef CONFIG_MMU
- VECTOR_SOFTPROG \tbr_tt, \vec
-#else
- VECTOR_NMI \tbr_tt, 0
-#endif
-.endm
-
-
-###############################################################################
-#
-# specification of the vectors
-# - note: each macro inserts code into multiple sections
-#
-###############################################################################
- VECTOR_SP_MMU TBR_TT_INSTR_MMU_MISS, __entry_insn_mmu_miss
- VECTOR_SOFTPROG TBR_TT_INSTR_ACC_ERROR, __entry_insn_access_error
- VECTOR_SOFTPROG TBR_TT_INSTR_ACC_EXCEP, __entry_insn_access_exception
- VECTOR_SOFTPROG TBR_TT_PRIV_INSTR, __entry_privileged_instruction
- VECTOR_SOFTPROG TBR_TT_ILLEGAL_INSTR, __entry_illegal_instruction
- VECTOR_SOFTPROG TBR_TT_FP_EXCEPTION, __entry_media_exception
- VECTOR_SOFTPROG TBR_TT_MP_EXCEPTION, __entry_media_exception
- VECTOR_SOFTPROG TBR_TT_DATA_ACC_ERROR, __entry_data_access_error
- VECTOR_SP_MMU TBR_TT_DATA_MMU_MISS, __entry_data_mmu_miss
- VECTOR_SOFTPROG TBR_TT_DATA_ACC_EXCEP, __entry_data_access_exception
- VECTOR_SOFTPROG TBR_TT_DATA_STR_ERROR, __entry_data_store_error
- VECTOR_SOFTPROG TBR_TT_DIVISION_EXCEP, __entry_division_exception
-
-#ifdef CONFIG_MMU
- .section .trap.user
- .org TBR_TT_INSTR_TLB_MISS
- .globl __trap_user_insn_tlb_miss
-__trap_user_insn_tlb_miss:
- movsg ear0,gr28 /* faulting address */
- movsg scr0,gr31 /* get mapped PTD coverage start address */
- xor.p gr28,gr31,gr31 /* compare addresses */
- bra __entry_user_insn_tlb_miss
-
- .org TBR_TT_DATA_TLB_MISS
- .globl __trap_user_data_tlb_miss
-__trap_user_data_tlb_miss:
- movsg ear0,gr28 /* faulting address */
- movsg scr1,gr31 /* get mapped PTD coverage start address */
- xor.p gr28,gr31,gr31 /* compare addresses */
- bra __entry_user_data_tlb_miss
-
- .section .trap.kernel
- .org TBR_TT_INSTR_TLB_MISS
- .globl __trap_kernel_insn_tlb_miss
-__trap_kernel_insn_tlb_miss:
- movsg ear0,gr29 /* faulting address */
- movsg scr0,gr31 /* get mapped PTD coverage start address */
- xor.p gr29,gr31,gr31 /* compare addresses */
- bra __entry_kernel_insn_tlb_miss
-
- .org TBR_TT_DATA_TLB_MISS
- .globl __trap_kernel_data_tlb_miss
-__trap_kernel_data_tlb_miss:
- movsg ear0,gr29 /* faulting address */
- movsg scr1,gr31 /* get mapped PTD coverage start address */
- xor.p gr29,gr31,gr31 /* compare addresses */
- bra __entry_kernel_data_tlb_miss
-
- .section .trap.fixup.user
- .org TBR_TT_INSTR_TLB_MISS >> 2
- .globl __trap_fixup_user_insn_tlb_miss
-__trap_fixup_user_insn_tlb_miss:
- .long __break_user_insn_tlb_miss
- .org TBR_TT_DATA_TLB_MISS >> 2
- .globl __trap_fixup_user_data_tlb_miss
-__trap_fixup_user_data_tlb_miss:
- .long __break_user_data_tlb_miss
-
- .section .trap.fixup.kernel
- .org TBR_TT_INSTR_TLB_MISS >> 2
- .globl __trap_fixup_kernel_insn_tlb_miss
-__trap_fixup_kernel_insn_tlb_miss:
- .long __break_kernel_insn_tlb_miss
- .org TBR_TT_DATA_TLB_MISS >> 2
- .globl __trap_fixup_kernel_data_tlb_miss
-__trap_fixup_kernel_data_tlb_miss:
- .long __break_kernel_data_tlb_miss
-
- .section .trap.vector
- .org TBR_TT_INSTR_TLB_MISS >> 2
- .long __entry_insn_mmu_fault
- .org TBR_TT_DATA_TLB_MISS >> 2
- .long __entry_data_mmu_fault
-#endif
-
- VECTOR_SP_MMU TBR_TT_DATA_DAT_EXCEP, __entry_data_dat_fault
- VECTOR_NMI TBR_TT_DECREMENT_TIMER, __entry_do_NMI
- VECTOR_SOFTPROG TBR_TT_COMPOUND_EXCEP, __entry_compound_exception
- VECTOR_IRQ TBR_TT_INTERRUPT_1, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_2, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_3, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_4, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_5, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_6, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_7, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_8, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_9, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_10, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_11, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_12, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_13, __entry_do_IRQ
- VECTOR_IRQ TBR_TT_INTERRUPT_14, __entry_do_IRQ
- VECTOR_NMI TBR_TT_INTERRUPT_15, __entry_do_NMI
-
- # miscellaneous user mode entry points
- .section .trap.user
- .org TBR_TT_TRAP0
- .rept 127
- bra __entry_uspace_softprog_interrupt
- .long 0,0,0
- .endr
- .org TBR_TT_BREAK
- bra __entry_break
- .long 0,0,0
-
- .section .trap.fixup.user
- .org TBR_TT_TRAP0 >> 2
- .rept 127
- .long __break_step_uspace_softprog_interrupt
- .endr
- .org TBR_TT_BREAK >> 2
- .long 0
-
- # miscellaneous kernel mode entry points
- .section .trap.kernel
- .org TBR_TT_TRAP0
- bra __entry_kernel_softprog_interrupt
- .org TBR_TT_TRAP1
- bra __entry_kernel_softprog_interrupt
-
- # trap #2 in kernel - reenable interrupts
- .org TBR_TT_TRAP2
- bra __entry_kernel_external_interrupt_virtual_reenable
-
- # miscellaneous kernel traps
- .org TBR_TT_TRAP3
- .rept 124
- bra __entry_kernel_softprog_interrupt
- .long 0,0,0
- .endr
- .org TBR_TT_BREAK
- bra __entry_break
- .long 0,0,0
-
- .section .trap.fixup.kernel
- .org TBR_TT_TRAP0 >> 2
- .long __break_step_kernel_softprog_interrupt
- .long __break_step_kernel_softprog_interrupt
- .long __break_step_kernel_external_interrupt_virtual_reenable
- .rept 124
- .long __break_step_kernel_softprog_interrupt
- .endr
- .org TBR_TT_BREAK >> 2
- .long 0
-
- # miscellaneous debug mode entry points
- .section .trap.break
- .org TBR_TT_BREAK
- movsg bpcsr,gr30
- jmpl @(gr30,gr0)
-
- # miscellaneous vectors
- .section .trap.vector
- .org TBR_TT_TRAP0 >> 2
- .long system_call
- .rept 119
- .long __entry_unsupported_trap
- .endr
-
- # userspace atomic op emulation, traps 120-126
- .rept 7
- .long __entry_atomic_op
- .endr
-
- .org TBR_TT_BREAK >> 2
- .long __entry_debug_exception
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
deleted file mode 100644
index dfcd263c0517..000000000000
--- a/arch/frv/kernel/entry.S
+++ /dev/null
@@ -1,1519 +0,0 @@
-/* entry.S: FR-V entry
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- *
- * Entry to the kernel is "interesting":
- * (1) There are no stack pointers, not even for the kernel
- * (2) General Registers should not be clobbered
- * (3) There are no kernel-only data registers
- * (4) Since all addressing modes are wrt to a General Register, no global
- * variables can be reached
- *
- * We deal with this by declaring that we shall kill GR28 on entering the
- * kernel from userspace
- *
- * However, since break interrupts can interrupt the CPU even when PSR.ET==0,
- * they can't rely on GR28 to be anything useful, and so need to clobber a
- * separate register (GR31). Break interrupts are managed in break.S
- *
- * GR29 _is_ saved, and holds the current task pointer globally
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/ptrace.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <asm/spr-regs.h>
-
-#define nr_syscalls ((syscall_table_size)/4)
-
- .section .text..entry
- .balign 4
-
-.macro LEDS val
-# sethi.p %hi(0xe1200004),gr30
-# setlo %lo(0xe1200004),gr30
-# setlos #~\val,gr31
-# st gr31,@(gr30,gr0)
-# sethi.p %hi(0xffc00100),gr30
-# setlo %lo(0xffc00100),gr30
-# sth gr0,@(gr30,gr0)
-# membar
-.endm
-
-.macro LEDS32
-# not gr31,gr31
-# sethi.p %hi(0xe1200004),gr30
-# setlo %lo(0xe1200004),gr30
-# st.p gr31,@(gr30,gr0)
-# srli gr31,#16,gr31
-# sethi.p %hi(0xffc00100),gr30
-# setlo %lo(0xffc00100),gr30
-# sth gr31,@(gr30,gr0)
-# membar
-.endm
-
-###############################################################################
-#
-# entry point for External interrupts received whilst executing userspace code
-#
-###############################################################################
- .globl __entry_uspace_external_interrupt
- .type __entry_uspace_external_interrupt,@function
-__entry_uspace_external_interrupt:
- LEDS 0x6200
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
-
- # handle h/w single-step through exceptions
- sti gr0,@(gr28,#REG__STATUS)
-
- .globl __entry_uspace_external_interrupt_reentry
-__entry_uspace_external_interrupt_reentry:
- LEDS 0x6201
-
- setlos #REG__END,gr30
- dcpl gr28,gr30,#0
-
- # finish building the exception frame
- sti sp, @(gr28,#REG_SP)
- stdi gr2, @(gr28,#REG_GR(2))
- stdi gr4, @(gr28,#REG_GR(4))
- stdi gr6, @(gr28,#REG_GR(6))
- stdi gr8, @(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr0, @(gr28,#REG_GR(28))
- sti gr29,@(gr28,#REG_GR(29))
- stdi.p gr30,@(gr28,#REG_GR(30))
-
- # set up the kernel stack pointer
- ori gr28,0,sp
-
- movsg tbr ,gr20
- movsg psr ,gr22
- movsg pcsr,gr21
- movsg isr ,gr23
- movsg ccr ,gr24
- movsg cccr,gr25
- movsg lr ,gr26
- movsg lcr ,gr27
-
- setlos.p #-1,gr4
- andi gr22,#PSR_PS,gr5 /* try to rebuild original PSR value */
- andi.p gr22,#~(PSR_PS|PSR_S),gr6
- slli gr5,#1,gr5
- or gr6,gr5,gr5
- andi gr5,#~PSR_ET,gr5
-
- sti gr20,@(gr28,#REG_TBR)
- sti gr21,@(gr28,#REG_PC)
- sti gr5 ,@(gr28,#REG_PSR)
- sti gr23,@(gr28,#REG_ISR)
- stdi gr24,@(gr28,#REG_CCR)
- stdi gr26,@(gr28,#REG_LR)
- sti gr4 ,@(gr28,#REG_SYSCALLNO)
-
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr28,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi.p gr4,@(gr28,#REG_GNER0)
-
- # interrupts start off fully disabled in the interrupt handler
- subcc gr0,gr0,gr0,icc2 /* set Z and clear C */
-
- # set up kernel global registers
- sethi.p %hi(__kernel_current_task),gr5
- setlo %lo(__kernel_current_task),gr5
- sethi.p %hi(_gp),gr16
- setlo %lo(_gp),gr16
- ldi @(gr5,#0),gr29
- ldi.p @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
-
- # make sure we (the kernel) get div-zero and misalignment exceptions
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # switch to the kernel trap table
- sethi.p %hi(__entry_kerneltrap_table),gr6
- setlo %lo(__entry_kerneltrap_table),gr6
- movgs gr6,tbr
-
- # set the return address
- sethi.p %hi(__entry_return_from_user_interrupt),gr4
- setlo %lo(__entry_return_from_user_interrupt),gr4
- movgs gr4,lr
-
- # raise the minimum interrupt priority to 15 (NMI only) and enable exceptions
- movsg psr,gr4
-
- ori gr4,#PSR_PIL_14,gr4
- movgs gr4,psr
- ori gr4,#PSR_PIL_14|PSR_ET,gr4
- movgs gr4,psr
-
- LEDS 0x6202
- bra do_IRQ
-
- .size __entry_uspace_external_interrupt,.-__entry_uspace_external_interrupt
-
-###############################################################################
-#
-# entry point for External interrupts received whilst executing kernel code
-# - on arriving here, the following registers should already be set up:
-# GR15 - current thread_info struct pointer
-# GR16 - kernel GP-REL pointer
-# GR29 - current task struct pointer
-# TBR - kernel trap vector table
-# ISR - kernel's preferred integer controls
-#
-###############################################################################
- .globl __entry_kernel_external_interrupt
- .type __entry_kernel_external_interrupt,@function
-__entry_kernel_external_interrupt:
- LEDS 0x6210
-// sub sp,gr15,gr31
-// LEDS32
-
- # set up the stack pointer
- or.p sp,gr0,gr30
- subi sp,#REG__END,sp
- sti gr30,@(sp,#REG_SP)
-
- # handle h/w single-step through exceptions
- sti gr0,@(sp,#REG__STATUS)
-
- .globl __entry_kernel_external_interrupt_reentry
-__entry_kernel_external_interrupt_reentry:
- LEDS 0x6211
-
- # set up the exception frame
- setlos #REG__END,gr30
- dcpl sp,gr30,#0
-
- sti.p gr28,@(sp,#REG_GR(28))
- ori sp,0,gr28
-
- # finish building the exception frame
- stdi gr2,@(gr28,#REG_GR(2))
- stdi gr4,@(gr28,#REG_GR(4))
- stdi gr6,@(gr28,#REG_GR(6))
- stdi gr8,@(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr29,@(gr28,#REG_GR(29))
- stdi.p gr30,@(gr28,#REG_GR(30))
-
- # note virtual interrupts will be fully enabled upon return
- subicc gr0,#1,gr0,icc2 /* clear Z, set C */
-
- movsg tbr ,gr20
- movsg psr ,gr22
- movsg pcsr,gr21
- movsg isr ,gr23
- movsg ccr ,gr24
- movsg cccr,gr25
- movsg lr ,gr26
- movsg lcr ,gr27
-
- setlos.p #-1,gr4
- andi gr22,#PSR_PS,gr5 /* try to rebuild original PSR value */
- andi.p gr22,#~(PSR_PS|PSR_S),gr6
- slli gr5,#1,gr5
- or gr6,gr5,gr5
- andi.p gr5,#~PSR_ET,gr5
-
- # set CCCR.CC3 to Undefined to abort atomic-modify completion inside the kernel
- # - for an explanation of how it works, see: Documentation/frv/atomic-ops.txt
- andi gr25,#~0xc0,gr25
-
- sti gr20,@(gr28,#REG_TBR)
- sti gr21,@(gr28,#REG_PC)
- sti gr5 ,@(gr28,#REG_PSR)
- sti gr23,@(gr28,#REG_ISR)
- stdi gr24,@(gr28,#REG_CCR)
- stdi gr26,@(gr28,#REG_LR)
- sti gr4 ,@(gr28,#REG_SYSCALLNO)
-
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr28,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi.p gr4,@(gr28,#REG_GNER0)
-
- # interrupts start off fully disabled in the interrupt handler
- subcc gr0,gr0,gr0,icc2 /* set Z and clear C */
-
- # set the return address
- sethi.p %hi(__entry_return_from_kernel_interrupt),gr4
- setlo %lo(__entry_return_from_kernel_interrupt),gr4
- movgs gr4,lr
-
- # clear power-saving mode flags
- movsg hsr0,gr4
- andi gr4,#~HSR0_PDM,gr4
- movgs gr4,hsr0
-
- # raise the minimum interrupt priority to 15 (NMI only) and enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_PIL_14,gr4
- movgs gr4,psr
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- LEDS 0x6212
- bra do_IRQ
-
- .size __entry_kernel_external_interrupt,.-__entry_kernel_external_interrupt
-
-###############################################################################
-#
-# deal with interrupts that were actually virtually disabled
-# - we need to really disable them, flag the fact and return immediately
-# - if you change this, you must alter break.S also
-#
-###############################################################################
- .balign L1_CACHE_BYTES
- .globl __entry_kernel_external_interrupt_virtually_disabled
- .type __entry_kernel_external_interrupt_virtually_disabled,@function
-__entry_kernel_external_interrupt_virtually_disabled:
- movsg psr,gr30
- andi gr30,#~PSR_PIL,gr30
- ori gr30,#PSR_PIL_14,gr30 ; debugging interrupts only
- movgs gr30,psr
- subcc gr0,gr0,gr0,icc2 ; leave Z set, clear C
- rett #0
-
- .size __entry_kernel_external_interrupt_virtually_disabled,.-__entry_kernel_external_interrupt_virtually_disabled
-
-###############################################################################
-#
-# deal with re-enablement of interrupts that were pending when virtually re-enabled
-# - set ICC2.C, re-enable the real interrupts and return
-# - we can clear ICC2.Z because we shouldn't be here if it's not 0 [due to TIHI]
-# - if you change this, you must alter break.S also
-#
-###############################################################################
- .balign L1_CACHE_BYTES
- .globl __entry_kernel_external_interrupt_virtual_reenable
- .type __entry_kernel_external_interrupt_virtual_reenable,@function
-__entry_kernel_external_interrupt_virtual_reenable:
- movsg psr,gr30
- andi gr30,#~PSR_PIL,gr30 ; re-enable interrupts
- movgs gr30,psr
- subicc gr0,#1,gr0,icc2 ; clear Z, set C
- rett #0
-
- .size __entry_kernel_external_interrupt_virtual_reenable,.-__entry_kernel_external_interrupt_virtual_reenable
-
-###############################################################################
-#
-# entry point for Software and Progam interrupts generated whilst executing userspace code
-#
-###############################################################################
- .globl __entry_uspace_softprog_interrupt
- .type __entry_uspace_softprog_interrupt,@function
- .globl __entry_uspace_handle_mmu_fault
-__entry_uspace_softprog_interrupt:
- LEDS 0x6000
-#ifdef CONFIG_MMU
- movsg ear0,gr28
-__entry_uspace_handle_mmu_fault:
- movgs gr28,scr2
-#endif
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
-
- # handle h/w single-step through exceptions
- sti gr0,@(gr28,#REG__STATUS)
-
- .globl __entry_uspace_softprog_interrupt_reentry
-__entry_uspace_softprog_interrupt_reentry:
- LEDS 0x6001
-
- setlos #REG__END,gr30
- dcpl gr28,gr30,#0
-
- # set up the kernel stack pointer
- sti.p sp,@(gr28,#REG_SP)
- ori gr28,0,sp
- sti gr0,@(gr28,#REG_GR(28))
-
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
-
- movsg tbr,gr20
- movsg pcsr,gr21
- movsg psr,gr22
-
- sethi.p %hi(__entry_return_from_user_exception),gr23
- setlo %lo(__entry_return_from_user_exception),gr23
-
- bra __entry_common
-
- .size __entry_uspace_softprog_interrupt,.-__entry_uspace_softprog_interrupt
-
- # single-stepping was disabled on entry to a TLB handler that then faulted
-#ifdef CONFIG_MMU
- .globl __entry_uspace_handle_mmu_fault_sstep
-__entry_uspace_handle_mmu_fault_sstep:
- movgs gr28,scr2
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- ldi @(gr28,#0),gr28
-
- # flag single-step re-enablement
- sti gr0,@(gr28,#REG__STATUS)
- bra __entry_uspace_softprog_interrupt_reentry
-#endif
-
-
-###############################################################################
-#
-# entry point for Software and Progam interrupts generated whilst executing kernel code
-#
-###############################################################################
- .globl __entry_kernel_softprog_interrupt
- .type __entry_kernel_softprog_interrupt,@function
-__entry_kernel_softprog_interrupt:
- LEDS 0x6004
-
-#ifdef CONFIG_MMU
- movsg ear0,gr30
- movgs gr30,scr2
-#endif
-
- .globl __entry_kernel_handle_mmu_fault
-__entry_kernel_handle_mmu_fault:
- # set up the stack pointer
- subi sp,#REG__END,sp
- sti sp,@(sp,#REG_SP)
- sti sp,@(sp,#REG_SP-4)
- andi sp,#~7,sp
-
- # handle h/w single-step through exceptions
- sti gr0,@(sp,#REG__STATUS)
-
- .globl __entry_kernel_softprog_interrupt_reentry
-__entry_kernel_softprog_interrupt_reentry:
- LEDS 0x6005
-
- setlos #REG__END,gr30
- dcpl sp,gr30,#0
-
- # set up the exception frame
- sti.p gr28,@(sp,#REG_GR(28))
- ori sp,0,gr28
-
- stdi gr20,@(gr28,#REG_GR(20))
- stdi gr22,@(gr28,#REG_GR(22))
-
- ldi @(sp,#REG_SP),gr22 /* reconstruct the old SP */
- addi gr22,#REG__END,gr22
- sti gr22,@(sp,#REG_SP)
-
- # set CCCR.CC3 to Undefined to abort atomic-modify completion inside the kernel
- # - for an explanation of how it works, see: Documentation/frv/atomic-ops.txt
- movsg cccr,gr20
- andi gr20,#~0xc0,gr20
- movgs gr20,cccr
-
- movsg tbr,gr20
- movsg pcsr,gr21
- movsg psr,gr22
-
- sethi.p %hi(__entry_return_from_kernel_exception),gr23
- setlo %lo(__entry_return_from_kernel_exception),gr23
- bra __entry_common
-
- .size __entry_kernel_softprog_interrupt,.-__entry_kernel_softprog_interrupt
-
- # single-stepping was disabled on entry to a TLB handler that then faulted
-#ifdef CONFIG_MMU
- .globl __entry_kernel_handle_mmu_fault_sstep
-__entry_kernel_handle_mmu_fault_sstep:
- # set up the stack pointer
- subi sp,#REG__END,sp
- sti sp,@(sp,#REG_SP)
- sti sp,@(sp,#REG_SP-4)
- andi sp,#~7,sp
-
- # flag single-step re-enablement
- sethi #REG__STATUS_STEP,gr30
- sti gr30,@(sp,#REG__STATUS)
- bra __entry_kernel_softprog_interrupt_reentry
-#endif
-
-
-###############################################################################
-#
-# the rest of the kernel entry point code
-# - on arriving here, the following registers should be set up:
-# GR1 - kernel stack pointer
-# GR7 - syscall number (trap 0 only)
-# GR8-13 - syscall args (trap 0 only)
-# GR20 - saved TBR
-# GR21 - saved PC
-# GR22 - saved PSR
-# GR23 - return handler address
-# GR28 - exception frame on stack
-# SCR2 - saved EAR0 where applicable (clobbered by ICI & ICEF insns on FR451)
-# PSR - PSR.S 1, PSR.ET 0
-#
-###############################################################################
- .globl __entry_common
- .type __entry_common,@function
-__entry_common:
- LEDS 0x6008
-
- # finish building the exception frame
- stdi gr2,@(gr28,#REG_GR(2))
- stdi gr4,@(gr28,#REG_GR(4))
- stdi gr6,@(gr28,#REG_GR(6))
- stdi gr8,@(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr29,@(gr28,#REG_GR(29))
- stdi gr30,@(gr28,#REG_GR(30))
-
- movsg lcr ,gr27
- movsg lr ,gr26
- movgs gr23,lr
- movsg cccr,gr25
- movsg ccr ,gr24
- movsg isr ,gr23
-
- setlos.p #-1,gr4
- andi gr22,#PSR_PS,gr5 /* try to rebuild original PSR value */
- andi.p gr22,#~(PSR_PS|PSR_S),gr6
- slli gr5,#1,gr5
- or gr6,gr5,gr5
- andi gr5,#~PSR_ET,gr5
-
- sti gr20,@(gr28,#REG_TBR)
- sti gr21,@(gr28,#REG_PC)
- sti gr5 ,@(gr28,#REG_PSR)
- sti gr23,@(gr28,#REG_ISR)
- stdi gr24,@(gr28,#REG_CCR)
- stdi gr26,@(gr28,#REG_LR)
- sti gr4 ,@(gr28,#REG_SYSCALLNO)
-
- movsg iacc0h,gr4
- movsg iacc0l,gr5
- stdi gr4,@(gr28,#REG_IACC0)
-
- movsg gner0,gr4
- movsg gner1,gr5
- stdi.p gr4,@(gr28,#REG_GNER0)
-
- # set up virtual interrupt disablement
- subicc gr0,#1,gr0,icc2 /* clear Z flag, set C flag */
-
- # set up kernel global registers
- sethi.p %hi(__kernel_current_task),gr5
- setlo %lo(__kernel_current_task),gr5
- sethi.p %hi(_gp),gr16
- setlo %lo(_gp),gr16
- ldi @(gr5,#0),gr29
- ldi @(gr29,#4),gr15 ; __current_thread_info = current->thread_info
-
- # switch to the kernel trap table
- sethi.p %hi(__entry_kerneltrap_table),gr6
- setlo %lo(__entry_kerneltrap_table),gr6
- movgs gr6,tbr
-
- # make sure we (the kernel) get div-zero and misalignment exceptions
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # clear power-saving mode flags
- movsg hsr0,gr4
- andi gr4,#~HSR0_PDM,gr4
- movgs gr4,hsr0
-
- # multiplex again using old TBR as a guide
- setlos.p #TBR_TT,gr3
- sethi %hi(__entry_vector_table),gr6
- and.p gr20,gr3,gr5
- setlo %lo(__entry_vector_table),gr6
- srli gr5,#2,gr5
- ld @(gr5,gr6),gr5
-
- LEDS 0x6009
- jmpl @(gr5,gr0)
-
-
- .size __entry_common,.-__entry_common
-
-###############################################################################
-#
-# handle instruction MMU fault
-#
-###############################################################################
-#ifdef CONFIG_MMU
- .globl __entry_insn_mmu_fault
-__entry_insn_mmu_fault:
- LEDS 0x6010
- setlos #0,gr8
- movsg esr0,gr9
- movsg scr2,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- sethi.p %hi(do_page_fault),gr5
- setlo %lo(do_page_fault),gr5
- jmpl @(gr5,gr0) ; call do_page_fault(0,esr0,ear0)
-#endif
-
-
-###############################################################################
-#
-# handle instruction access error
-#
-###############################################################################
- .globl __entry_insn_access_error
-__entry_insn_access_error:
- LEDS 0x6011
- sethi.p %hi(insn_access_error),gr5
- setlo %lo(insn_access_error),gr5
- movsg esfr1,gr8
- movsg epcr0,gr9
- movsg esr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call insn_access_error(esfr1,epcr0,esr0)
-
-###############################################################################
-#
-# handle various instructions of dubious legality
-#
-###############################################################################
- .globl __entry_unsupported_trap
- .globl __entry_illegal_instruction
- .globl __entry_privileged_instruction
- .globl __entry_debug_exception
-__entry_unsupported_trap:
- subi gr21,#4,gr21
- sti gr21,@(gr28,#REG_PC)
-__entry_illegal_instruction:
-__entry_privileged_instruction:
-__entry_debug_exception:
- LEDS 0x6012
- sethi.p %hi(illegal_instruction),gr5
- setlo %lo(illegal_instruction),gr5
- movsg esfr1,gr8
- movsg epcr0,gr9
- movsg esr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call ill_insn(esfr1,epcr0,esr0)
-
-###############################################################################
-#
-# handle atomic operation emulation for userspace
-#
-###############################################################################
- .globl __entry_atomic_op
-__entry_atomic_op:
- LEDS 0x6012
- sethi.p %hi(atomic_operation),gr5
- setlo %lo(atomic_operation),gr5
- movsg esfr1,gr8
- movsg epcr0,gr9
- movsg esr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call atomic_operation(esfr1,epcr0,esr0)
-
-###############################################################################
-#
-# handle media exception
-#
-###############################################################################
- .globl __entry_media_exception
-__entry_media_exception:
- LEDS 0x6013
- sethi.p %hi(media_exception),gr5
- setlo %lo(media_exception),gr5
- movsg msr0,gr8
- movsg msr1,gr9
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call media_excep(msr0,msr1)
-
-###############################################################################
-#
-# handle data MMU fault
-# handle data DAT fault (write-protect exception)
-#
-###############################################################################
-#ifdef CONFIG_MMU
- .globl __entry_data_mmu_fault
-__entry_data_mmu_fault:
- .globl __entry_data_dat_fault
-__entry_data_dat_fault:
- LEDS 0x6014
- setlos #1,gr8
- movsg esr0,gr9
- movsg scr2,gr10 ; saved EAR0
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- sethi.p %hi(do_page_fault),gr5
- setlo %lo(do_page_fault),gr5
- jmpl @(gr5,gr0) ; call do_page_fault(1,esr0,ear0)
-#endif
-
-###############################################################################
-#
-# handle data and instruction access exceptions
-#
-###############################################################################
- .globl __entry_insn_access_exception
- .globl __entry_data_access_exception
-__entry_insn_access_exception:
-__entry_data_access_exception:
- LEDS 0x6016
- sethi.p %hi(memory_access_exception),gr5
- setlo %lo(memory_access_exception),gr5
- movsg esr0,gr8
- movsg scr2,gr9 ; saved EAR0
- movsg epcr0,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call memory_access_error(esr0,ear0,epcr0)
-
-###############################################################################
-#
-# handle data access error
-#
-###############################################################################
- .globl __entry_data_access_error
-__entry_data_access_error:
- LEDS 0x6016
- sethi.p %hi(data_access_error),gr5
- setlo %lo(data_access_error),gr5
- movsg esfr1,gr8
- movsg esr15,gr9
- movsg ear15,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call data_access_error(esfr1,esr15,ear15)
-
-###############################################################################
-#
-# handle data store error
-#
-###############################################################################
- .globl __entry_data_store_error
-__entry_data_store_error:
- LEDS 0x6017
- sethi.p %hi(data_store_error),gr5
- setlo %lo(data_store_error),gr5
- movsg esfr1,gr8
- movsg esr14,gr9
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call data_store_error(esfr1,esr14)
-
-###############################################################################
-#
-# handle division exception
-#
-###############################################################################
- .globl __entry_division_exception
-__entry_division_exception:
- LEDS 0x6018
- sethi.p %hi(division_exception),gr5
- setlo %lo(division_exception),gr5
- movsg esfr1,gr8
- movsg esr0,gr9
- movsg isr,gr10
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call div_excep(esfr1,esr0,isr)
-
-###############################################################################
-#
-# handle compound exception
-#
-###############################################################################
- .globl __entry_compound_exception
-__entry_compound_exception:
- LEDS 0x6019
- sethi.p %hi(compound_exception),gr5
- setlo %lo(compound_exception),gr5
- movsg esfr1,gr8
- movsg esr0,gr9
- movsg esr14,gr10
- movsg esr15,gr11
- movsg msr0,gr12
- movsg msr1,gr13
-
- # now that we've accessed the exception regs, we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- jmpl @(gr5,gr0) ; call comp_excep(esfr1,esr0,esr14,esr15,msr0,msr1)
-
-###############################################################################
-#
-# handle interrupts and NMIs
-#
-###############################################################################
- .globl __entry_do_IRQ
-__entry_do_IRQ:
- LEDS 0x6020
-
- # we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- bra do_IRQ
-
- .globl __entry_do_NMI
-__entry_do_NMI:
- LEDS 0x6021
-
- # we can enable exceptions
- movsg psr,gr4
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
- bra do_NMI
-
-###############################################################################
-#
-# the return path for a newly forked child process
-# - __switch_to() saved the old current pointer in GR8 for us
-#
-###############################################################################
- .globl ret_from_fork
-ret_from_fork:
- LEDS 0x6100
- call schedule_tail
-
- # fork & co. return 0 to child
- setlos.p #0,gr8
- bra __syscall_exit
-
- .globl ret_from_kernel_thread
-ret_from_kernel_thread:
- lddi.p @(gr28,#REG_GR(8)),gr20
- call schedule_tail
- calll.p @(gr21,gr0)
- or gr20,gr20,gr8
- bra __syscall_exit
-
-###################################################################################################
-#
-# Return to user mode is not as complex as all this looks,
-# but we want the default path for a system call return to
-# go as quickly as possible which is why some of this is
-# less clear than it otherwise should be.
-#
-###################################################################################################
- .balign L1_CACHE_BYTES
- .globl system_call
-system_call:
- LEDS 0x6101
- movsg psr,gr4 ; enable exceptions
- ori gr4,#PSR_ET,gr4
- movgs gr4,psr
-
- sti gr7,@(gr28,#REG_SYSCALLNO)
- sti.p gr8,@(gr28,#REG_ORIG_GR8)
-
- subicc gr7,#nr_syscalls,gr0,icc0
- bnc icc0,#0,__syscall_badsys
-
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_SYSCALL_TRACE,gr0,icc0
- bne icc0,#0,__syscall_trace_entry
-
-__syscall_call:
- slli.p gr7,#2,gr7
- sethi %hi(sys_call_table),gr5
- setlo %lo(sys_call_table),gr5
- ld @(gr5,gr7),gr4
- calll @(gr4,gr0)
-
-
-###############################################################################
-#
-# return to interrupted process
-#
-###############################################################################
-__syscall_exit:
- LEDS 0x6300
-
- # keep current PSR in GR23
- movsg psr,gr23
-
- ldi @(gr28,#REG_PSR),gr22
-
- sti.p gr8,@(gr28,#REG_GR(8)) ; save return value
-
- # rebuild saved psr - execve will change it for init/main.c
- srli gr22,#1,gr5
- andi.p gr22,#~PSR_PS,gr22
- andi gr5,#PSR_PS,gr5
- or gr5,gr22,gr22
- ori.p gr22,#PSR_S,gr22
-
- # make sure we don't miss an interrupt setting need_resched or sigpending between
- # sampling and the RETT
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_ALLWORK_MASK,gr0,icc0
- bne icc0,#0,__syscall_exit_work
-
- # restore all registers and return
-__entry_return_direct:
- LEDS 0x6301
-
- andi gr22,#~PSR_ET,gr22
- movgs gr22,psr
-
- ldi @(gr28,#REG_ISR),gr23
- lddi @(gr28,#REG_CCR),gr24
- lddi @(gr28,#REG_LR) ,gr26
- ldi @(gr28,#REG_PC) ,gr21
- ldi @(gr28,#REG_TBR),gr20
-
- movgs gr20,tbr
- movgs gr21,pcsr
- movgs gr23,isr
- movgs gr24,ccr
- movgs gr25,cccr
- movgs gr26,lr
- movgs gr27,lcr
-
- lddi @(gr28,#REG_GNER0),gr4
- movgs gr4,gner0
- movgs gr5,gner1
-
- lddi @(gr28,#REG_IACC0),gr4
- movgs gr4,iacc0h
- movgs gr5,iacc0l
-
- lddi @(gr28,#REG_GR(4)) ,gr4
- lddi @(gr28,#REG_GR(6)) ,gr6
- lddi @(gr28,#REG_GR(8)) ,gr8
- lddi @(gr28,#REG_GR(10)),gr10
- lddi @(gr28,#REG_GR(12)),gr12
- lddi @(gr28,#REG_GR(14)),gr14
- lddi @(gr28,#REG_GR(16)),gr16
- lddi @(gr28,#REG_GR(18)),gr18
- lddi @(gr28,#REG_GR(20)),gr20
- lddi @(gr28,#REG_GR(22)),gr22
- lddi @(gr28,#REG_GR(24)),gr24
- lddi @(gr28,#REG_GR(26)),gr26
- ldi @(gr28,#REG_GR(29)),gr29
- lddi @(gr28,#REG_GR(30)),gr30
-
- # check to see if a debugging return is required
- LEDS 0x67f0
- movsg ccr,gr2
- ldi @(gr28,#REG__STATUS),gr3
- andicc gr3,#REG__STATUS_STEP,gr0,icc0
- bne icc0,#0,__entry_return_singlestep
- movgs gr2,ccr
-
- ldi @(gr28,#REG_SP) ,sp
- lddi @(gr28,#REG_GR(2)) ,gr2
- ldi @(gr28,#REG_GR(28)),gr28
-
- LEDS 0x67fe
-// movsg pcsr,gr31
-// LEDS32
-
-#if 0
- # store the current frame in the workram on the FR451
- movgs gr28,scr2
- sethi.p %hi(0xfe800000),gr28
- setlo %lo(0xfe800000),gr28
-
- stdi gr2,@(gr28,#REG_GR(2))
- stdi gr4,@(gr28,#REG_GR(4))
- stdi gr6,@(gr28,#REG_GR(6))
- stdi gr8,@(gr28,#REG_GR(8))
- stdi gr10,@(gr28,#REG_GR(10))
- stdi gr12,@(gr28,#REG_GR(12))
- stdi gr14,@(gr28,#REG_GR(14))
- stdi gr16,@(gr28,#REG_GR(16))
- stdi gr18,@(gr28,#REG_GR(18))
- stdi gr24,@(gr28,#REG_GR(24))
- stdi gr26,@(gr28,#REG_GR(26))
- sti gr29,@(gr28,#REG_GR(29))
- stdi gr30,@(gr28,#REG_GR(30))
-
- movsg tbr ,gr30
- sti gr30,@(gr28,#REG_TBR)
- movsg pcsr,gr30
- sti gr30,@(gr28,#REG_PC)
- movsg psr ,gr30
- sti gr30,@(gr28,#REG_PSR)
- movsg isr ,gr30
- sti gr30,@(gr28,#REG_ISR)
- movsg ccr ,gr30
- movsg cccr,gr31
- stdi gr30,@(gr28,#REG_CCR)
- movsg lr ,gr30
- movsg lcr ,gr31
- stdi gr30,@(gr28,#REG_LR)
- sti gr0 ,@(gr28,#REG_SYSCALLNO)
- movsg scr2,gr28
-#endif
-
- rett #0
-
- # return via break.S
-__entry_return_singlestep:
- movgs gr2,ccr
- lddi @(gr28,#REG_GR(2)) ,gr2
- ldi @(gr28,#REG_SP) ,sp
- ldi @(gr28,#REG_GR(28)),gr28
- LEDS 0x67ff
- break
- .globl __entry_return_singlestep_breaks_here
-__entry_return_singlestep_breaks_here:
- nop
-
-
-###############################################################################
-#
-# return to a process interrupted in kernel space
-# - we need to consider preemption if that is enabled
-#
-###############################################################################
- .balign L1_CACHE_BYTES
-__entry_return_from_kernel_exception:
- LEDS 0x6302
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
- bra __entry_return_direct
-
- .balign L1_CACHE_BYTES
-__entry_return_from_kernel_interrupt:
- LEDS 0x6303
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
-#ifdef CONFIG_PREEMPT
- ldi @(gr15,#TI_PRE_COUNT),gr5
- subicc gr5,#0,gr0,icc0
- beq icc0,#0,__entry_return_direct
-
- subcc gr0,gr0,gr0,icc2 /* set Z and clear C */
- call preempt_schedule_irq
-#endif
- bra __entry_return_direct
-
-
-###############################################################################
-#
-# perform work that needs to be done immediately before resumption
-#
-###############################################################################
- .globl __entry_return_from_user_exception
- .balign L1_CACHE_BYTES
-__entry_return_from_user_exception:
- LEDS 0x6501
-
-__entry_resume_userspace:
- # make sure we don't miss an interrupt setting need_resched or sigpending between
- # sampling and the RETT
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
-__entry_return_from_user_interrupt:
- LEDS 0x6402
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_WORK_MASK,gr0,icc0
- beq icc0,#1,__entry_return_direct
-
-__entry_work_pending:
- LEDS 0x6404
- andicc gr4,#_TIF_NEED_RESCHED,gr0,icc0
- beq icc0,#1,__entry_work_notifysig
-
-__entry_work_resched:
- LEDS 0x6408
- movsg psr,gr23
- andi gr23,#~PSR_PIL,gr23
- movgs gr23,psr
- call schedule
- movsg psr,gr23
- ori gr23,#PSR_PIL_14,gr23
- movgs gr23,psr
-
- LEDS 0x6401
- ldi @(gr15,#TI_FLAGS),gr4
- andicc gr4,#_TIF_WORK_MASK,gr0,icc0
- beq icc0,#1,__entry_return_direct
- andicc gr4,#_TIF_NEED_RESCHED,gr0,icc0
- bne icc0,#1,__entry_work_resched
-
-__entry_work_notifysig:
- LEDS 0x6410
- ori.p gr4,#0,gr8
- call do_notify_resume
- bra __entry_resume_userspace
-
- # perform syscall entry tracing
-__syscall_trace_entry:
- LEDS 0x6320
- call syscall_trace_entry
-
- lddi.p @(gr28,#REG_GR(8)) ,gr8
- ori gr8,#0,gr7 ; syscall_trace_entry() returned new syscallno
- lddi @(gr28,#REG_GR(10)),gr10
- lddi.p @(gr28,#REG_GR(12)),gr12
-
- subicc gr7,#nr_syscalls,gr0,icc0
- bnc icc0,#0,__syscall_badsys
- bra __syscall_call
-
- # perform syscall exit tracing
-__syscall_exit_work:
- LEDS 0x6340
- andicc gr22,#PSR_PS,gr0,icc1 ; don't handle on return to kernel mode
- andicc.p gr4,#_TIF_SYSCALL_TRACE,gr0,icc0
- bne icc1,#0,__entry_return_direct
- beq icc0,#1,__entry_work_pending
-
- movsg psr,gr23
- andi gr23,#~PSR_PIL,gr23 ; could let syscall_trace_exit() call schedule()
- movgs gr23,psr
-
- call syscall_trace_exit
- bra __entry_resume_userspace
-
-__syscall_badsys:
- LEDS 0x6380
- setlos #-ENOSYS,gr8
- sti gr8,@(gr28,#REG_GR(8)) ; save return value
- bra __entry_resume_userspace
-
-
-###############################################################################
-#
-# syscall vector table
-#
-###############################################################################
- .section .rodata
-ALIGN
- .globl sys_call_table
-sys_call_table:
- .long sys_restart_syscall /* 0 - old "setup()" system call, used for restarting */
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_lchown16
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_stat
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_setuid16
- .long sys_getuid16
- .long sys_ni_syscall // sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_fstat
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_ni_syscall /* old gtty syscall holder */
- .long sys_access
- .long sys_nice
- .long sys_ni_syscall /* 35 */ /* old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_setgid16
- .long sys_getgid16
- .long sys_ni_syscall // sys_signal
- .long sys_geteuid16
- .long sys_getegid16 /* 50 */
- .long sys_acct
- .long sys_umount /* recycled never used phys( */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 */
- .long sys_ni_syscall /* old mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* old old uname syscall */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_sigaction
- .long sys_ni_syscall // sys_sgetmask
- .long sys_ni_syscall // sys_ssetmask
- .long sys_setreuid16 /* 70 */
- .long sys_setregid16
- .long sys_sigsuspend
- .long sys_ni_syscall // sys_sigpending
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_ni_syscall // sys_old_getrlimit
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_getgroups16 /* 80 */
- .long sys_setgroups16
- .long sys_ni_syscall /* old_select slot */
- .long sys_symlink
- .long sys_lstat
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_ni_syscall // old_readdir
- .long sys_ni_syscall /* 90 */ /* old_mmap slot */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_fchown16 /* 95 */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* ioperm for i386 */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* obsolete olduname( syscall */
- .long sys_ni_syscall /* iopl for i386 */ /* 110 */
- .long sys_vhangup
- .long sys_ni_syscall /* obsolete idle( syscall */
- .long sys_ni_syscall /* vm86old for i386 */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_sigreturn
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* old "cacheflush" */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* old "get_kernel_syms" */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* for afs_syscall */
- .long sys_setfsuid16
- .long sys_setfsgid16
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_setresuid16
- .long sys_getresuid16 /* 165 */
- .long sys_ni_syscall /* for vm86 */
- .long sys_ni_syscall /* Old sys_query_module */
- .long sys_poll
- .long sys_ni_syscall /* Old nfsservctl */
- .long sys_setresgid16 /* 170 */
- .long sys_getresgid16
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_chown16
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* streams1 */
- .long sys_ni_syscall /* streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap2
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall /* Reserved for Security */
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall //sys_set_thread_area
- .long sys_ni_syscall //sys_get_thread_area
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* sys_vserver */
- .long sys_mbind
- .long sys_get_mempolicy
- .long sys_set_mempolicy
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_ni_syscall /* reserved for kexec */
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_ioprio_set
- .long sys_ioprio_get /* 290 */
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages
- .long sys_openat /* 295 */
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat
- .long sys_fstatat64 /* 300 */
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat
- .long sys_readlinkat /* 305 */
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll
- .long sys_unshare /* 310 */
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range
- .long sys_tee /* 315 */
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait
- .long sys_utimensat /* 320 */
- .long sys_signalfd
- .long sys_timerfd_create
- .long sys_eventfd
- .long sys_fallocate
- .long sys_timerfd_settime /* 325 */
- .long sys_timerfd_gettime
- .long sys_signalfd4
- .long sys_eventfd2
- .long sys_epoll_create1
- .long sys_dup3 /* 330 */
- .long sys_pipe2
- .long sys_inotify_init1
- .long sys_preadv
- .long sys_pwritev
- .long sys_rt_tgsigqueueinfo /* 335 */
- .long sys_perf_event_open
- .long sys_setns
-
-syscall_table_size = (. - sys_call_table)
diff --git a/arch/frv/kernel/frv_ksyms.c b/arch/frv/kernel/frv_ksyms.c
deleted file mode 100644
index 6ea430d58149..000000000000
--- a/arch/frv/kernel/frv_ksyms.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/linkage.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/in6.h>
-#include <linux/interrupt.h>
-
-#include <asm/setup.h>
-#include <asm/pgalloc.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/checksum.h>
-#include <asm/hardirq.h>
-#include <asm/cacheflush.h>
-
-extern long __memcpy_user(void *dst, const void *src, size_t count);
-extern long __memset_user(void *dst, const void *src, size_t count);
-
-/* platform dependent support */
-
-EXPORT_SYMBOL(__ioremap);
-EXPORT_SYMBOL(iounmap);
-
-EXPORT_SYMBOL(ip_fast_csum);
-
-#if 0
-EXPORT_SYMBOL(local_irq_count);
-EXPORT_SYMBOL(local_bh_count);
-#endif
-
-EXPORT_SYMBOL(__res_bus_clock_speed_HZ);
-EXPORT_SYMBOL(__page_offset);
-EXPORT_SYMBOL(__memcpy_user);
-EXPORT_SYMBOL(__memset_user);
-EXPORT_SYMBOL(frv_dcache_writeback);
-EXPORT_SYMBOL(frv_cache_invalidate);
-EXPORT_SYMBOL(frv_icache_invalidate);
-EXPORT_SYMBOL(frv_cache_wback_inv);
-
-#ifndef CONFIG_MMU
-EXPORT_SYMBOL(memory_start);
-EXPORT_SYMBOL(memory_end);
-#endif
-
-EXPORT_SYMBOL(__debug_bug_trap);
-
-/* The following are special because they're not called
- explicitly (the C compiler generates them). Fortunately,
- their interface isn't gonna change any time soon now, so
- it's OK to leave it out of version control. */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-
-EXPORT_SYMBOL(__outsl_ns);
-EXPORT_SYMBOL(__insl_ns);
-
-#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-EXPORT_SYMBOL(__xchg_32);
-EXPORT_SYMBOL(__cmpxchg_32);
-#endif
-EXPORT_SYMBOL(atomic64_add_return);
-EXPORT_SYMBOL(atomic64_sub_return);
-EXPORT_SYMBOL(__xchg_64);
-EXPORT_SYMBOL(__cmpxchg_64);
-
-EXPORT_SYMBOL(__debug_bug_printk);
-EXPORT_SYMBOL(__delay_loops_MHz);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler... (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __gcc_bcmp(void);
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __cmpdi2(void);
-extern void __divdi3(void);
-extern void __lshrdi3(void);
-extern void __moddi3(void);
-extern void __muldi3(void);
-extern void __mulll(void);
-extern void __umulll(void);
-extern void __negdi2(void);
-extern void __ucmpdi2(void);
-extern void __udivdi3(void);
-extern void __udivmoddi4(void);
-extern void __umoddi3(void);
-
- /* gcc lib functions */
-//EXPORT_SYMBOL(__gcc_bcmp);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-//EXPORT_SYMBOL(__cmpdi2);
-//EXPORT_SYMBOL(__divdi3);
-EXPORT_SYMBOL(__lshrdi3);
-//EXPORT_SYMBOL(__moddi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__mulll);
-EXPORT_SYMBOL(__umulll);
-EXPORT_SYMBOL(__negdi2);
-EXPORT_SYMBOL(__ucmpdi2);
-//EXPORT_SYMBOL(__udivdi3);
-//EXPORT_SYMBOL(__udivmoddi4);
-//EXPORT_SYMBOL(__umoddi3);
diff --git a/arch/frv/kernel/futex.c b/arch/frv/kernel/futex.c
deleted file mode 100644
index 37f7b2bf7f73..000000000000
--- a/arch/frv/kernel/futex.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/* futex.c: futex operations
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-#include <asm/futex.h>
-#include <asm/errno.h>
-
-/*
- * the various futex operations; MMU fault checking is ignored under no-MMU
- * conditions
- */
-static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_add(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " add %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_or(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " or %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_and(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " and %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-static inline int atomic_futex_op_xchg_xor(int oparg, u32 __user *uaddr, int *_oldval)
-{
- int oldval, ret;
-
- asm("0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- "1: ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " xor %1,%3,%3 \n"
- "2: cst.p %3,%M0 ,cc3,#1 \n"
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
- " beq icc3,#0,0b \n"
- " setlos 0,%2 \n"
- "3: \n"
- ".subsection 2 \n"
- "4: setlos %5,%2 \n"
- " bra 3b \n"
- ".previous \n"
- ".section __ex_table,\"a\" \n"
- " .balign 8 \n"
- " .long 1b,4b \n"
- " .long 2b,4b \n"
- ".previous"
- : "+U"(*uaddr), "=&r"(oldval), "=&r"(ret), "=r"(oparg)
- : "3"(oparg), "i"(-EFAULT)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- *_oldval = oldval;
- return ret;
-}
-
-/*****************************************************************************/
-/*
- * do the futex operations
- */
-int arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
-{
- int oldval = 0, ret;
-
- pagefault_disable();
-
- switch (op) {
- case FUTEX_OP_SET:
- ret = atomic_futex_op_xchg_set(oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_ADD:
- ret = atomic_futex_op_xchg_add(oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_OR:
- ret = atomic_futex_op_xchg_or(oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_ANDN:
- ret = atomic_futex_op_xchg_and(~oparg, uaddr, &oldval);
- break;
- case FUTEX_OP_XOR:
- ret = atomic_futex_op_xchg_xor(oparg, uaddr, &oldval);
- break;
- default:
- ret = -ENOSYS;
- break;
- }
-
- pagefault_enable();
-
- if (!ret)
- *oval = oldval;
-
- return ret;
-
-} /* end arch_futex_atomic_op_inuser() */
diff --git a/arch/frv/kernel/gdb-io.c b/arch/frv/kernel/gdb-io.c
deleted file mode 100644
index 0707d35079ba..000000000000
--- a/arch/frv/kernel/gdb-io.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* gdb-io.c: FR403 GDB stub I/O
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/serial_reg.h>
-
-#include <asm/pgtable.h>
-#include <asm/irc-regs.h>
-#include <asm/timer-regs.h>
-#include <asm/gdb-stub.h>
-#include "gdb-io.h"
-
-#ifdef CONFIG_GDBSTUB_UART0
-#define __UART(X) (*(volatile uint8_t *)(UART0_BASE + (UART_##X)))
-#define __UART_IRR_NMI 0xff0f0000
-#else /* CONFIG_GDBSTUB_UART1 */
-#define __UART(X) (*(volatile uint8_t *)(UART1_BASE + (UART_##X)))
-#define __UART_IRR_NMI 0xfff00000
-#endif
-
-#define LSR_WAIT_FOR(STATE) \
-do { \
- gdbstub_do_rx(); \
-} while (!(__UART(LSR) & UART_LSR_##STATE))
-
-#define FLOWCTL_QUERY(LINE) ({ __UART(MSR) & UART_MSR_##LINE; })
-#define FLOWCTL_CLEAR(LINE) do { __UART(MCR) &= ~UART_MCR_##LINE; mb(); } while (0)
-#define FLOWCTL_SET(LINE) do { __UART(MCR) |= UART_MCR_##LINE; mb(); } while (0)
-
-#define FLOWCTL_WAIT_FOR(LINE) \
-do { \
- gdbstub_do_rx(); \
-} while(!FLOWCTL_QUERY(LINE))
-
-/*****************************************************************************/
-/*
- * initialise the GDB stub
- * - called with PSR.ET==0, so can't incur external interrupts
- */
-void gdbstub_io_init(void)
-{
- /* set up the serial port */
- __UART(LCR) = UART_LCR_WLEN8; /* 1N8 */
- __UART(FCR) =
- UART_FCR_ENABLE_FIFO |
- UART_FCR_CLEAR_RCVR |
- UART_FCR_CLEAR_XMIT |
- UART_FCR_TRIGGER_1;
-
- FLOWCTL_CLEAR(DTR);
- FLOWCTL_SET(RTS);
-
-// gdbstub_set_baud(115200);
-
- /* we want to get serial receive interrupts */
- __UART(IER) = UART_IER_RDI | UART_IER_RLSI;
- mb();
-
- __set_IRR(6, __UART_IRR_NMI); /* map ERRs and UARTx to NMI */
-
-} /* end gdbstub_io_init() */
-
-/*****************************************************************************/
-/*
- * set up the GDB stub serial port baud rate timers
- */
-void gdbstub_set_baud(unsigned baud)
-{
- unsigned value, high, low;
- u8 lcr;
-
- /* work out the divisor to give us the nearest higher baud rate */
- value = __serial_clock_speed_HZ / 16 / baud;
-
- /* determine the baud rate range */
- high = __serial_clock_speed_HZ / 16 / value;
- low = __serial_clock_speed_HZ / 16 / (value + 1);
-
- /* pick the nearest bound */
- if (low + (high - low) / 2 > baud)
- value++;
-
- lcr = __UART(LCR);
- __UART(LCR) |= UART_LCR_DLAB;
- mb();
- __UART(DLL) = value & 0xff;
- __UART(DLM) = (value >> 8) & 0xff;
- mb();
- __UART(LCR) = lcr;
- mb();
-
-} /* end gdbstub_set_baud() */
-
-/*****************************************************************************/
-/*
- * receive characters into the receive FIFO
- */
-void gdbstub_do_rx(void)
-{
- unsigned ix, nix;
-
- ix = gdbstub_rx_inp;
-
- while (__UART(LSR) & UART_LSR_DR) {
- nix = (ix + 2) & 0xfff;
- if (nix == gdbstub_rx_outp)
- break;
-
- gdbstub_rx_buffer[ix++] = __UART(LSR);
- gdbstub_rx_buffer[ix++] = __UART(RX);
- ix = nix;
- }
-
- gdbstub_rx_inp = ix;
-
- __clr_RC(15);
- __clr_IRL();
-
-} /* end gdbstub_do_rx() */
-
-/*****************************************************************************/
-/*
- * wait for a character to come from the debugger
- */
-int gdbstub_rx_char(unsigned char *_ch, int nonblock)
-{
- unsigned ix;
- u8 ch, st;
-
- *_ch = 0xff;
-
- if (gdbstub_rx_unget) {
- *_ch = gdbstub_rx_unget;
- gdbstub_rx_unget = 0;
- return 0;
- }
-
- try_again:
- gdbstub_do_rx();
-
- /* pull chars out of the buffer */
- ix = gdbstub_rx_outp;
- if (ix == gdbstub_rx_inp) {
- if (nonblock)
- return -EAGAIN;
- //watchdog_alert_counter = 0;
- goto try_again;
- }
-
- st = gdbstub_rx_buffer[ix++];
- ch = gdbstub_rx_buffer[ix++];
- gdbstub_rx_outp = ix & 0x00000fff;
-
- if (st & UART_LSR_BI) {
- gdbstub_proto("### GDB Rx Break Detected ###\n");
- return -EINTR;
- }
- else if (st & (UART_LSR_FE|UART_LSR_OE|UART_LSR_PE)) {
- gdbstub_io("### GDB Rx Error (st=%02x) ###\n",st);
- return -EIO;
- }
- else {
- gdbstub_io("### GDB Rx %02x (st=%02x) ###\n",ch,st);
- *_ch = ch & 0x7f;
- return 0;
- }
-
-} /* end gdbstub_rx_char() */
-
-/*****************************************************************************/
-/*
- * send a character to the debugger
- */
-void gdbstub_tx_char(unsigned char ch)
-{
- FLOWCTL_SET(DTR);
- LSR_WAIT_FOR(THRE);
-// FLOWCTL_WAIT_FOR(CTS);
-
- if (ch == 0x0a) {
- __UART(TX) = 0x0d;
- mb();
- LSR_WAIT_FOR(THRE);
-// FLOWCTL_WAIT_FOR(CTS);
- }
- __UART(TX) = ch;
- mb();
-
- FLOWCTL_CLEAR(DTR);
-} /* end gdbstub_tx_char() */
-
-/*****************************************************************************/
-/*
- * send a character to the debugger
- */
-void gdbstub_tx_flush(void)
-{
- LSR_WAIT_FOR(TEMT);
- LSR_WAIT_FOR(THRE);
- FLOWCTL_CLEAR(DTR);
-} /* end gdbstub_tx_flush() */
diff --git a/arch/frv/kernel/gdb-io.h b/arch/frv/kernel/gdb-io.h
deleted file mode 100644
index 138714bacc40..000000000000
--- a/arch/frv/kernel/gdb-io.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* gdb-io.h: FR403 GDB I/O port defs
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _GDB_IO_H
-#define _GDB_IO_H
-
-#include <asm/serial-regs.h>
-
-#undef UART_RX
-#undef UART_TX
-#undef UART_DLL
-#undef UART_DLM
-#undef UART_IER
-#undef UART_IIR
-#undef UART_FCR
-#undef UART_LCR
-#undef UART_MCR
-#undef UART_LSR
-#undef UART_MSR
-#undef UART_SCR
-
-#define UART_RX 0*8 /* In: Receive buffer (DLAB=0) */
-#define UART_TX 0*8 /* Out: Transmit buffer (DLAB=0) */
-#define UART_DLL 0*8 /* Out: Divisor Latch Low (DLAB=1) */
-#define UART_DLM 1*8 /* Out: Divisor Latch High (DLAB=1) */
-#define UART_IER 1*8 /* Out: Interrupt Enable Register */
-#define UART_IIR 2*8 /* In: Interrupt ID Register */
-#define UART_FCR 2*8 /* Out: FIFO Control Register */
-#define UART_LCR 3*8 /* Out: Line Control Register */
-#define UART_MCR 4*8 /* Out: Modem Control Register */
-#define UART_LSR 5*8 /* In: Line Status Register */
-#define UART_MSR 6*8 /* In: Modem Status Register */
-#define UART_SCR 7*8 /* I/O: Scratch Register */
-
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-#define UART_LCR_SBC 0x40 /* Set break control */
-#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
-#define UART_LCR_EPAR 0x10 /* Even parity select */
-#define UART_LCR_PARITY 0x08 /* Parity Enable */
-#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-
-#endif /* _GDB_IO_H */
diff --git a/arch/frv/kernel/gdb-stub.c b/arch/frv/kernel/gdb-stub.c
deleted file mode 100644
index bbe78b0bffec..000000000000
--- a/arch/frv/kernel/gdb-stub.c
+++ /dev/null
@@ -1,2149 +0,0 @@
-/* gdb-stub.c: FRV GDB stub
- *
- * Copyright (C) 2003,4 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from Linux/MIPS version, Copyright (C) 1995 Andreas Busse
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/*
- * To enable debugger support, two things need to happen. One, a
- * call to set_debug_traps() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint(). Breakpoint()
- * simulates a breakpoint by executing a BREAK instruction.
- *
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
- * baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- *
- * ==============
- * MORE EXAMPLES:
- * ==============
- *
- * For reference -- the following are the steps that one
- * company took (RidgeRun Inc) to get remote gdb debugging
- * going. In this scenario the host machine was a PC and the
- * target platform was a Galileo EVB64120A MIPS evaluation
- * board.
- *
- * Step 1:
- * First download gdb-5.0.tar.gz from the internet.
- * and then build/install the package.
- *
- * Example:
- * $ tar zxf gdb-5.0.tar.gz
- * $ cd gdb-5.0
- * $ ./configure --target=frv-elf-gdb
- * $ make
- * $ frv-elf-gdb
- *
- * Step 2:
- * Configure linux for remote debugging and build it.
- *
- * Example:
- * $ cd ~/linux
- * $ make menuconfig <go to "Kernel Hacking" and turn on remote debugging>
- * $ make vmlinux
- *
- * Step 3:
- * Download the kernel to the remote target and start
- * the kernel running. It will promptly halt and wait
- * for the host gdb session to connect. It does this
- * since the "Kernel Hacking" option has defined
- * CONFIG_REMOTE_DEBUG which in turn enables your calls
- * to:
- * set_debug_traps();
- * breakpoint();
- *
- * Step 4:
- * Start the gdb session on the host.
- *
- * Example:
- * $ frv-elf-gdb vmlinux
- * (gdb) set remotebaud 115200
- * (gdb) target remote /dev/ttyS1
- * ...at this point you are connected to
- * the remote target and can use gdb
- * in the normal fasion. Setting
- * breakpoints, single stepping,
- * printing variables, etc.
- *
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/nmi.h>
-
-#include <asm/asm-offsets.h>
-#include <asm/pgtable.h>
-#include <asm/gdb-stub.h>
-
-#define LEDS(x) do { /* *(u32*)0xe1200004 = ~(x); mb(); */ } while(0)
-
-#undef GDBSTUB_DEBUG_PROTOCOL
-
-extern void debug_to_serial(const char *p, int n);
-extern void gdbstub_console_write(struct console *co, const char *p, unsigned n);
-
-extern volatile uint32_t __break_error_detect[3]; /* ESFR1, ESR15, EAR15 */
-
-struct __debug_amr {
- unsigned long L, P;
-} __attribute__((aligned(8)));
-
-struct __debug_mmu {
- struct {
- unsigned long hsr0, pcsr, esr0, ear0, epcr0;
-#ifdef CONFIG_MMU
- unsigned long tplr, tppr, tpxr, cxnr;
-#endif
- } regs;
-
- struct __debug_amr iamr[16];
- struct __debug_amr damr[16];
-
-#ifdef CONFIG_MMU
- struct __debug_amr tlb[64*2];
-#endif
-};
-
-static struct __debug_mmu __debug_mmu;
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers
- * at least NUMREGBYTES*2 are needed for register packets
- */
-#define BUFMAX 2048
-
-#define BREAK_INSN 0x801000c0 /* use "break" as bkpt */
-
-static const char gdbstub_banner[] = "Linux/FR-V GDB Stub (c) RedHat 2003\n";
-
-volatile u8 gdbstub_rx_buffer[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
-volatile u32 gdbstub_rx_inp = 0;
-volatile u32 gdbstub_rx_outp = 0;
-volatile u8 gdbstub_rx_overflow = 0;
-u8 gdbstub_rx_unget = 0;
-
-/* set with GDB whilst running to permit step through exceptions */
-extern volatile u32 __attribute__((section(".bss"))) gdbstub_trace_through_exceptions;
-
-static char input_buffer[BUFMAX];
-static char output_buffer[BUFMAX];
-
-static const char *regnames[] = {
- "PSR ", "ISR ", "CCR ", "CCCR",
- "LR ", "LCR ", "PC ", "_stt",
- "sys ", "GR8*", "GNE0", "GNE1",
- "IACH", "IACL",
- "TBR ", "SP ", "FP ", "GR3 ",
- "GR4 ", "GR5 ", "GR6 ", "GR7 ",
- "GR8 ", "GR9 ", "GR10", "GR11",
- "GR12", "GR13", "GR14", "GR15",
- "GR16", "GR17", "GR18", "GR19",
- "GR20", "GR21", "GR22", "GR23",
- "GR24", "GR25", "GR26", "GR27",
- "EFRM", "CURR", "GR30", "BFRM"
-};
-
-struct gdbstub_bkpt {
- unsigned long addr; /* address of breakpoint */
- unsigned len; /* size of breakpoint */
- uint32_t originsns[7]; /* original instructions */
-};
-
-static struct gdbstub_bkpt gdbstub_bkpts[256];
-
-/*
- * local prototypes
- */
-
-static void gdbstub_recv_packet(char *buffer);
-static int gdbstub_send_packet(char *buffer);
-static int gdbstub_compute_signal(unsigned long tbr);
-static int hex(unsigned char ch);
-static int hexToInt(char **ptr, unsigned long *intValue);
-static unsigned char *mem2hex(const void *mem, char *buf, int count, int may_fault);
-static char *hex2mem(const char *buf, void *_mem, int count);
-
-/*
- * Convert ch from a hex digit to an int
- */
-static int hex(unsigned char ch)
-{
- if (ch >= 'a' && ch <= 'f')
- return ch-'a'+10;
- if (ch >= '0' && ch <= '9')
- return ch-'0';
- if (ch >= 'A' && ch <= 'F')
- return ch-'A'+10;
- return -1;
-}
-
-void gdbstub_printk(const char *fmt, ...)
-{
- static char buf[1024];
- va_list args;
- int len;
-
- /* Emit the output into the temporary buffer */
- va_start(args, fmt);
- len = vsnprintf(buf, sizeof(buf), fmt, args);
- va_end(args);
- debug_to_serial(buf, len);
-}
-
-static inline char *gdbstub_strcpy(char *dst, const char *src)
-{
- int loop = 0;
- while ((dst[loop] = src[loop]))
- loop++;
- return dst;
-}
-
-static void gdbstub_purge_cache(void)
-{
- asm volatile(" dcef @(gr0,gr0),#1 \n"
- " icei @(gr0,gr0),#1 \n"
- " membar \n"
- " bar \n"
- );
-}
-
-/*****************************************************************************/
-/*
- * scan for the sequence $<data>#<checksum>
- */
-static void gdbstub_recv_packet(char *buffer)
-{
- unsigned char checksum;
- unsigned char xmitcsum;
- unsigned char ch;
- int count, i, ret, error;
-
- for (;;) {
- /* wait around for the start character, ignore all other characters */
- do {
- gdbstub_rx_char(&ch, 0);
- } while (ch != '$');
-
- checksum = 0;
- xmitcsum = -1;
- count = 0;
- error = 0;
-
- /* now, read until a # or end of buffer is found */
- while (count < BUFMAX) {
- ret = gdbstub_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
-
- if (ch == '#')
- break;
- checksum += ch;
- buffer[count] = ch;
- count++;
- }
-
- if (error == -EIO) {
- gdbstub_proto("### GDB Rx Error - Skipping packet ###\n");
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-');
- continue;
- }
-
- if (count >= BUFMAX || error)
- continue;
-
- buffer[count] = 0;
-
- /* read the checksum */
- ret = gdbstub_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
- xmitcsum = hex(ch) << 4;
-
- ret = gdbstub_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
- xmitcsum |= hex(ch);
-
- if (error) {
- if (error == -EIO)
- gdbstub_proto("### GDB Rx Error - Skipping packet\n");
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-');
- continue;
- }
-
- /* check the checksum */
- if (checksum != xmitcsum) {
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-'); /* failed checksum */
- continue;
- }
-
- gdbstub_proto("### GDB Rx '$%s#%02x' ###\n", buffer, checksum);
- gdbstub_proto("### GDB Tx ACK\n");
- gdbstub_tx_char('+'); /* successful transfer */
-
- /* if a sequence char is present, reply the sequence ID */
- if (buffer[2] == ':') {
- gdbstub_tx_char(buffer[0]);
- gdbstub_tx_char(buffer[1]);
-
- /* remove sequence chars from buffer */
- count = 0;
- while (buffer[count]) count++;
- for (i=3; i <= count; i++)
- buffer[i - 3] = buffer[i];
- }
-
- break;
- }
-} /* end gdbstub_recv_packet() */
-
-/*****************************************************************************/
-/*
- * send the packet in buffer.
- * - return 0 if successfully ACK'd
- * - return 1 if abandoned due to new incoming packet
- */
-static int gdbstub_send_packet(char *buffer)
-{
- unsigned char checksum;
- int count;
- unsigned char ch;
-
- /* $<packet info>#<checksum> */
- gdbstub_proto("### GDB Tx '%s' ###\n", buffer);
-
- do {
- gdbstub_tx_char('$');
- checksum = 0;
- count = 0;
-
- while ((ch = buffer[count]) != 0) {
- gdbstub_tx_char(ch);
- checksum += ch;
- count += 1;
- }
-
- gdbstub_tx_char('#');
- gdbstub_tx_char(hex_asc_hi(checksum));
- gdbstub_tx_char(hex_asc_lo(checksum));
-
- } while (gdbstub_rx_char(&ch,0),
-#ifdef GDBSTUB_DEBUG_PROTOCOL
- ch=='-' && (gdbstub_proto("### GDB Rx NAK\n"),0),
- ch!='-' && ch!='+' && (gdbstub_proto("### GDB Rx ??? %02x\n",ch),0),
-#endif
- ch!='+' && ch!='$');
-
- if (ch=='+') {
- gdbstub_proto("### GDB Rx ACK\n");
- return 0;
- }
-
- gdbstub_proto("### GDB Tx Abandoned\n");
- gdbstub_rx_unget = ch;
- return 1;
-} /* end gdbstub_send_packet() */
-
-/*
- * While we find nice hex chars, build an int.
- * Return number of chars processed.
- */
-static int hexToInt(char **ptr, unsigned long *_value)
-{
- int count = 0, ch;
-
- *_value = 0;
- while (**ptr) {
- ch = hex(**ptr);
- if (ch < 0)
- break;
-
- *_value = (*_value << 4) | ((uint8_t) ch & 0xf);
- count++;
-
- (*ptr)++;
- }
-
- return count;
-}
-
-/*****************************************************************************/
-/*
- * probe an address to see whether it maps to anything
- */
-static inline int gdbstub_addr_probe(const void *vaddr)
-{
-#ifdef CONFIG_MMU
- unsigned long paddr;
-
- asm("lrad %1,%0,#1,#0,#0" : "=r"(paddr) : "r"(vaddr));
- if (!(paddr & xAMPRx_V))
- return 0;
-#endif
-
- return 1;
-} /* end gdbstub_addr_probe() */
-
-#ifdef CONFIG_MMU
-static unsigned long __saved_dampr, __saved_damlr;
-
-static inline unsigned long gdbstub_virt_to_pte(unsigned long vaddr)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- unsigned long val, dampr5;
-
- pgd = (pgd_t *) __get_DAMLR(3) + pgd_index(vaddr);
- pud = pud_offset(pgd, vaddr);
- pmd = pmd_offset(pud, vaddr);
-
- if (pmd_bad(*pmd) || !pmd_present(*pmd))
- return 0;
-
- /* make sure dampr5 maps to the correct pmd */
- dampr5 = __get_DAMPR(5);
- val = pmd_val(*pmd);
- __set_DAMPR(5, val | xAMPRx_L | xAMPRx_SS_16Kb | xAMPRx_S | xAMPRx_C | xAMPRx_V);
-
- /* now its safe to access pmd */
- pte = (pte_t *)__get_DAMLR(5) + __pte_index(vaddr);
- if (pte_present(*pte))
- val = pte_val(*pte);
- else
- val = 0;
-
- /* restore original dampr5 */
- __set_DAMPR(5, dampr5);
-
- return val;
-}
-#endif
-
-static inline int gdbstub_addr_map(const void *vaddr)
-{
-#ifdef CONFIG_MMU
- unsigned long pte;
-
- __saved_dampr = __get_DAMPR(2);
- __saved_damlr = __get_DAMLR(2);
-#endif
- if (gdbstub_addr_probe(vaddr))
- return 1;
-#ifdef CONFIG_MMU
- pte = gdbstub_virt_to_pte((unsigned long) vaddr);
- if (pte) {
- __set_DAMPR(2, pte);
- __set_DAMLR(2, (unsigned long) vaddr & PAGE_MASK);
- return 1;
- }
-#endif
- return 0;
-}
-
-static inline void gdbstub_addr_unmap(void)
-{
-#ifdef CONFIG_MMU
- __set_DAMPR(2, __saved_dampr);
- __set_DAMLR(2, __saved_damlr);
-#endif
-}
-
-/*
- * access potentially dodgy memory through a potentially dodgy pointer
- */
-static inline int gdbstub_read_dword(const void *addr, uint32_t *_res)
-{
- unsigned long brr;
- uint32_t res;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " ld%I2 %M2,%0 \n"
- " movsg brr,%1 \n"
- : "=r"(res), "=r"(brr)
- : "m"(*(uint32_t *) addr));
- *_res = res;
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_write_dword(void *addr, uint32_t val)
-{
- unsigned long brr;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " st%I2 %1,%M2 \n"
- " movsg brr,%0 \n"
- : "=r"(brr)
- : "r"(val), "m"(*(uint32_t *) addr));
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_read_word(const void *addr, uint16_t *_res)
-{
- unsigned long brr;
- uint16_t res;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " lduh%I2 %M2,%0 \n"
- " movsg brr,%1 \n"
- : "=r"(res), "=r"(brr)
- : "m"(*(uint16_t *) addr));
- *_res = res;
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_write_word(void *addr, uint16_t val)
-{
- unsigned long brr;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " sth%I2 %1,%M2 \n"
- " movsg brr,%0 \n"
- : "=r"(brr)
- : "r"(val), "m"(*(uint16_t *) addr));
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_read_byte(const void *addr, uint8_t *_res)
-{
- unsigned long brr;
- uint8_t res;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " ldub%I2 %M2,%0 \n"
- " movsg brr,%1 \n"
- : "=r"(res), "=r"(brr)
- : "m"(*(uint8_t *) addr));
- *_res = res;
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static inline int gdbstub_write_byte(void *addr, uint8_t val)
-{
- unsigned long brr;
-
- if (!gdbstub_addr_map(addr))
- return 0;
-
- asm volatile(" movgs gr0,brr \n"
- " stb%I2 %1,%M2 \n"
- " movsg brr,%0 \n"
- : "=r"(brr)
- : "r"(val), "m"(*(uint8_t *) addr));
- gdbstub_addr_unmap();
- return likely(!brr);
-}
-
-static void __gdbstub_console_write(struct console *co, const char *p, unsigned n)
-{
- char outbuf[26];
- int qty;
-
- outbuf[0] = 'O';
-
- while (n > 0) {
- qty = 1;
-
- while (n > 0 && qty < 20) {
- mem2hex(p, outbuf + qty, 2, 0);
- qty += 2;
- if (*p == 0x0a) {
- outbuf[qty++] = '0';
- outbuf[qty++] = 'd';
- }
- p++;
- n--;
- }
-
- outbuf[qty] = 0;
- gdbstub_send_packet(outbuf);
- }
-}
-
-#if 0
-void debug_to_serial(const char *p, int n)
-{
- gdbstub_console_write(NULL,p,n);
-}
-#endif
-
-#ifdef CONFIG_GDB_CONSOLE
-
-static struct console gdbstub_console = {
- .name = "gdb",
- .write = gdbstub_console_write, /* in break.S */
- .flags = CON_PRINTBUFFER,
- .index = -1,
-};
-
-#endif
-
-/*****************************************************************************/
-/*
- * Convert the memory pointed to by mem into hex, placing result in buf.
- * - if successful, return a pointer to the last char put in buf (NUL)
- * - in case of mem fault, return NULL
- * may_fault is non-zero if we are reading from arbitrary memory, but is currently
- * not used.
- */
-static unsigned char *mem2hex(const void *_mem, char *buf, int count, int may_fault)
-{
- const uint8_t *mem = _mem;
- uint8_t ch[4] __attribute__((aligned(4)));
-
- if ((uint32_t)mem&1 && count>=1) {
- if (!gdbstub_read_byte(mem,ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- mem++;
- count--;
- }
-
- if ((uint32_t)mem&3 && count>=2) {
- if (!gdbstub_read_word(mem,(uint16_t *)ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- mem += 2;
- count -= 2;
- }
-
- while (count>=4) {
- if (!gdbstub_read_dword(mem,(uint32_t *)ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- buf = hex_byte_pack(buf, ch[2]);
- buf = hex_byte_pack(buf, ch[3]);
- mem += 4;
- count -= 4;
- }
-
- if (count>=2) {
- if (!gdbstub_read_word(mem,(uint16_t *)ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- mem += 2;
- count -= 2;
- }
-
- if (count>=1) {
- if (!gdbstub_read_byte(mem,ch))
- return NULL;
- buf = hex_byte_pack(buf, ch[0]);
- }
-
- *buf = 0;
-
- return buf;
-} /* end mem2hex() */
-
-/*****************************************************************************/
-/*
- * convert the hex array pointed to by buf into binary to be placed in mem
- * return a pointer to the character AFTER the last byte of buffer consumed
- */
-static char *hex2mem(const char *buf, void *_mem, int count)
-{
- uint8_t *mem = _mem;
- union {
- uint32_t l;
- uint16_t w;
- uint8_t b[4];
- } ch;
-
- if ((u32)mem&1 && count>=1) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- if (!gdbstub_write_byte(mem,ch.b[0]))
- return NULL;
- mem++;
- count--;
- }
-
- if ((u32)mem&3 && count>=2) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- if (!gdbstub_write_word(mem,ch.w))
- return NULL;
- mem += 2;
- count -= 2;
- }
-
- while (count>=4) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- ch.b[2] = hex(*buf++) << 4;
- ch.b[2] |= hex(*buf++);
- ch.b[3] = hex(*buf++) << 4;
- ch.b[3] |= hex(*buf++);
- if (!gdbstub_write_dword(mem,ch.l))
- return NULL;
- mem += 4;
- count -= 4;
- }
-
- if (count>=2) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- if (!gdbstub_write_word(mem,ch.w))
- return NULL;
- mem += 2;
- count -= 2;
- }
-
- if (count>=1) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- if (!gdbstub_write_byte(mem,ch.b[0]))
- return NULL;
- }
-
- return (char *) buf;
-} /* end hex2mem() */
-
-/*****************************************************************************/
-/*
- * This table contains the mapping between FRV TBR.TT exception codes,
- * and signals, which are primarily what GDB understands. It also
- * indicates which hardware traps we need to commandeer when
- * initializing the stub.
- */
-static const struct brr_to_sig_map {
- unsigned long brr_mask; /* BRR bitmask */
- unsigned long tbr_tt; /* TBR.TT code (in BRR.EBTT) */
- unsigned int signo; /* Signal that we map this into */
-} brr_to_sig_map[] = {
- { BRR_EB, TBR_TT_INSTR_ACC_ERROR, SIGSEGV },
- { BRR_EB, TBR_TT_ILLEGAL_INSTR, SIGILL },
- { BRR_EB, TBR_TT_PRIV_INSTR, SIGILL },
- { BRR_EB, TBR_TT_MP_EXCEPTION, SIGFPE },
- { BRR_EB, TBR_TT_DATA_ACC_ERROR, SIGSEGV },
- { BRR_EB, TBR_TT_DATA_STR_ERROR, SIGSEGV },
- { BRR_EB, TBR_TT_DIVISION_EXCEP, SIGFPE },
- { BRR_EB, TBR_TT_COMPOUND_EXCEP, SIGSEGV },
- { BRR_EB, TBR_TT_INTERRUPT_13, SIGALRM }, /* watchdog */
- { BRR_EB, TBR_TT_INTERRUPT_14, SIGINT }, /* GDB serial */
- { BRR_EB, TBR_TT_INTERRUPT_15, SIGQUIT }, /* NMI */
- { BRR_CB, 0, SIGUSR1 },
- { BRR_TB, 0, SIGUSR2 },
- { BRR_DBNEx, 0, SIGTRAP },
- { BRR_DBx, 0, SIGTRAP }, /* h/w watchpoint */
- { BRR_IBx, 0, SIGTRAP }, /* h/w breakpoint */
- { BRR_CBB, 0, SIGTRAP },
- { BRR_SB, 0, SIGTRAP },
- { BRR_ST, 0, SIGTRAP }, /* single step */
- { 0, 0, SIGHUP } /* default */
-};
-
-/*****************************************************************************/
-/*
- * convert the FRV BRR register contents into a UNIX signal number
- */
-static inline int gdbstub_compute_signal(unsigned long brr)
-{
- const struct brr_to_sig_map *map;
- unsigned long tbr = (brr & BRR_EBTT) >> 12;
-
- for (map = brr_to_sig_map; map->brr_mask; map++)
- if (map->brr_mask & brr)
- if (!map->tbr_tt || map->tbr_tt == tbr)
- break;
-
- return map->signo;
-} /* end gdbstub_compute_signal() */
-
-/*****************************************************************************/
-/*
- * set a software breakpoint or a hardware breakpoint or watchpoint
- */
-static int gdbstub_set_breakpoint(unsigned long type, unsigned long addr, unsigned long len)
-{
- unsigned long tmp;
- int bkpt, loop, xloop;
-
- union {
- struct {
- unsigned long mask0, mask1;
- };
- uint8_t bytes[8];
- } dbmr;
-
- //gdbstub_printk("setbkpt(%ld,%08lx,%ld)\n", type, addr, len);
-
- switch (type) {
- /* set software breakpoint */
- case 0:
- if (addr & 3 || len > 7*4)
- return -EINVAL;
-
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (!gdbstub_bkpts[bkpt].addr)
- break;
- if (bkpt < 0)
- return -ENOSPC;
-
- for (loop = 0; loop < len/4; loop++)
- if (!gdbstub_read_dword(&((uint32_t *) addr)[loop],
- &gdbstub_bkpts[bkpt].originsns[loop]))
- return -EFAULT;
-
- for (loop = 0; loop < len/4; loop++)
- if (!gdbstub_write_dword(&((uint32_t *) addr)[loop],
- BREAK_INSN)
- ) {
- /* need to undo the changes if possible */
- for (xloop = 0; xloop < loop; xloop++)
- gdbstub_write_dword(&((uint32_t *) addr)[xloop],
- gdbstub_bkpts[bkpt].originsns[xloop]);
- return -EFAULT;
- }
-
- gdbstub_bkpts[bkpt].addr = addr;
- gdbstub_bkpts[bkpt].len = len;
-
-#if 0
- gdbstub_printk("Set BKPT[%02x]: %08lx #%d {%04x, %04x} -> { %04x, %04x }\n",
- bkpt,
- gdbstub_bkpts[bkpt].addr,
- gdbstub_bkpts[bkpt].len,
- gdbstub_bkpts[bkpt].originsns[0],
- gdbstub_bkpts[bkpt].originsns[1],
- ((uint32_t *) addr)[0],
- ((uint32_t *) addr)[1]
- );
-#endif
- return 0;
-
- /* set hardware breakpoint */
- case 1:
- if (addr & 3 || len != 4)
- return -EINVAL;
-
- if (!(__debug_regs->dcr & DCR_IBE0)) {
- //gdbstub_printk("set h/w break 0: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE0;
- __debug_regs->ibar[0] = addr;
- asm volatile("movgs %0,ibar0" : : "r"(addr));
- return 0;
- }
-
- if (!(__debug_regs->dcr & DCR_IBE1)) {
- //gdbstub_printk("set h/w break 1: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE1;
- __debug_regs->ibar[1] = addr;
- asm volatile("movgs %0,ibar1" : : "r"(addr));
- return 0;
- }
-
- if (!(__debug_regs->dcr & DCR_IBE2)) {
- //gdbstub_printk("set h/w break 2: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE2;
- __debug_regs->ibar[2] = addr;
- asm volatile("movgs %0,ibar2" : : "r"(addr));
- return 0;
- }
-
- if (!(__debug_regs->dcr & DCR_IBE3)) {
- //gdbstub_printk("set h/w break 3: %08lx\n", addr);
- __debug_regs->dcr |= DCR_IBE3;
- __debug_regs->ibar[3] = addr;
- asm volatile("movgs %0,ibar3" : : "r"(addr));
- return 0;
- }
-
- return -ENOSPC;
-
- /* set data read/write/access watchpoint */
- case 2:
- case 3:
- case 4:
- if ((addr & ~7) != ((addr + len - 1) & ~7))
- return -EINVAL;
-
- tmp = addr & 7;
-
- memset(dbmr.bytes, 0xff, sizeof(dbmr.bytes));
- for (loop = 0; loop < len; loop++)
- dbmr.bytes[tmp + loop] = 0;
-
- addr &= ~7;
-
- if (!(__debug_regs->dcr & (DCR_DRBE0|DCR_DWBE0))) {
- //gdbstub_printk("set h/w watchpoint 0 type %ld: %08lx\n", type, addr);
- tmp = type==2 ? DCR_DWBE0 : type==3 ? DCR_DRBE0 : DCR_DRBE0|DCR_DWBE0;
-
- __debug_regs->dcr |= tmp;
- __debug_regs->dbar[0] = addr;
- __debug_regs->dbmr[0][0] = dbmr.mask0;
- __debug_regs->dbmr[0][1] = dbmr.mask1;
- __debug_regs->dbdr[0][0] = 0;
- __debug_regs->dbdr[0][1] = 0;
-
- asm volatile(" movgs %0,dbar0 \n"
- " movgs %1,dbmr00 \n"
- " movgs %2,dbmr01 \n"
- " movgs gr0,dbdr00 \n"
- " movgs gr0,dbdr01 \n"
- : : "r"(addr), "r"(dbmr.mask0), "r"(dbmr.mask1));
- return 0;
- }
-
- if (!(__debug_regs->dcr & (DCR_DRBE1|DCR_DWBE1))) {
- //gdbstub_printk("set h/w watchpoint 1 type %ld: %08lx\n", type, addr);
- tmp = type==2 ? DCR_DWBE1 : type==3 ? DCR_DRBE1 : DCR_DRBE1|DCR_DWBE1;
-
- __debug_regs->dcr |= tmp;
- __debug_regs->dbar[1] = addr;
- __debug_regs->dbmr[1][0] = dbmr.mask0;
- __debug_regs->dbmr[1][1] = dbmr.mask1;
- __debug_regs->dbdr[1][0] = 0;
- __debug_regs->dbdr[1][1] = 0;
-
- asm volatile(" movgs %0,dbar1 \n"
- " movgs %1,dbmr10 \n"
- " movgs %2,dbmr11 \n"
- " movgs gr0,dbdr10 \n"
- " movgs gr0,dbdr11 \n"
- : : "r"(addr), "r"(dbmr.mask0), "r"(dbmr.mask1));
- return 0;
- }
-
- return -ENOSPC;
-
- default:
- return -EINVAL;
- }
-
-} /* end gdbstub_set_breakpoint() */
-
-/*****************************************************************************/
-/*
- * clear a breakpoint or watchpoint
- */
-int gdbstub_clear_breakpoint(unsigned long type, unsigned long addr, unsigned long len)
-{
- unsigned long tmp;
- int bkpt, loop;
-
- union {
- struct {
- unsigned long mask0, mask1;
- };
- uint8_t bytes[8];
- } dbmr;
-
- //gdbstub_printk("clearbkpt(%ld,%08lx,%ld)\n", type, addr, len);
-
- switch (type) {
- /* clear software breakpoint */
- case 0:
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (gdbstub_bkpts[bkpt].addr == addr && gdbstub_bkpts[bkpt].len == len)
- break;
- if (bkpt < 0)
- return -ENOENT;
-
- gdbstub_bkpts[bkpt].addr = 0;
-
- for (loop = 0; loop < len/4; loop++)
- if (!gdbstub_write_dword(&((uint32_t *) addr)[loop],
- gdbstub_bkpts[bkpt].originsns[loop]))
- return -EFAULT;
- return 0;
-
- /* clear hardware breakpoint */
- case 1:
- if (addr & 3 || len != 4)
- return -EINVAL;
-
-#define __get_ibar(X) ({ unsigned long x; asm volatile("movsg ibar"#X",%0" : "=r"(x)); x; })
-
- if (__debug_regs->dcr & DCR_IBE0 && __get_ibar(0) == addr) {
- //gdbstub_printk("clear h/w break 0: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE0;
- __debug_regs->ibar[0] = 0;
- asm volatile("movgs gr0,ibar0");
- return 0;
- }
-
- if (__debug_regs->dcr & DCR_IBE1 && __get_ibar(1) == addr) {
- //gdbstub_printk("clear h/w break 1: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE1;
- __debug_regs->ibar[1] = 0;
- asm volatile("movgs gr0,ibar1");
- return 0;
- }
-
- if (__debug_regs->dcr & DCR_IBE2 && __get_ibar(2) == addr) {
- //gdbstub_printk("clear h/w break 2: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE2;
- __debug_regs->ibar[2] = 0;
- asm volatile("movgs gr0,ibar2");
- return 0;
- }
-
- if (__debug_regs->dcr & DCR_IBE3 && __get_ibar(3) == addr) {
- //gdbstub_printk("clear h/w break 3: %08lx\n", addr);
- __debug_regs->dcr &= ~DCR_IBE3;
- __debug_regs->ibar[3] = 0;
- asm volatile("movgs gr0,ibar3");
- return 0;
- }
-
- return -EINVAL;
-
- /* clear data read/write/access watchpoint */
- case 2:
- case 3:
- case 4:
- if ((addr & ~7) != ((addr + len - 1) & ~7))
- return -EINVAL;
-
- tmp = addr & 7;
-
- memset(dbmr.bytes, 0xff, sizeof(dbmr.bytes));
- for (loop = 0; loop < len; loop++)
- dbmr.bytes[tmp + loop] = 0;
-
- addr &= ~7;
-
-#define __get_dbar(X) ({ unsigned long x; asm volatile("movsg dbar"#X",%0" : "=r"(x)); x; })
-#define __get_dbmr0(X) ({ unsigned long x; asm volatile("movsg dbmr"#X"0,%0" : "=r"(x)); x; })
-#define __get_dbmr1(X) ({ unsigned long x; asm volatile("movsg dbmr"#X"1,%0" : "=r"(x)); x; })
-
- /* consider DBAR 0 */
- tmp = type==2 ? DCR_DWBE0 : type==3 ? DCR_DRBE0 : DCR_DRBE0|DCR_DWBE0;
-
- if ((__debug_regs->dcr & (DCR_DRBE0|DCR_DWBE0)) != tmp ||
- __get_dbar(0) != addr ||
- __get_dbmr0(0) != dbmr.mask0 ||
- __get_dbmr1(0) != dbmr.mask1)
- goto skip_dbar0;
-
- //gdbstub_printk("clear h/w watchpoint 0 type %ld: %08lx\n", type, addr);
- __debug_regs->dcr &= ~(DCR_DRBE0|DCR_DWBE0);
- __debug_regs->dbar[0] = 0;
- __debug_regs->dbmr[0][0] = 0;
- __debug_regs->dbmr[0][1] = 0;
- __debug_regs->dbdr[0][0] = 0;
- __debug_regs->dbdr[0][1] = 0;
-
- asm volatile(" movgs gr0,dbar0 \n"
- " movgs gr0,dbmr00 \n"
- " movgs gr0,dbmr01 \n"
- " movgs gr0,dbdr00 \n"
- " movgs gr0,dbdr01 \n");
- return 0;
-
- skip_dbar0:
- /* consider DBAR 0 */
- tmp = type==2 ? DCR_DWBE1 : type==3 ? DCR_DRBE1 : DCR_DRBE1|DCR_DWBE1;
-
- if ((__debug_regs->dcr & (DCR_DRBE1|DCR_DWBE1)) != tmp ||
- __get_dbar(1) != addr ||
- __get_dbmr0(1) != dbmr.mask0 ||
- __get_dbmr1(1) != dbmr.mask1)
- goto skip_dbar1;
-
- //gdbstub_printk("clear h/w watchpoint 1 type %ld: %08lx\n", type, addr);
- __debug_regs->dcr &= ~(DCR_DRBE1|DCR_DWBE1);
- __debug_regs->dbar[1] = 0;
- __debug_regs->dbmr[1][0] = 0;
- __debug_regs->dbmr[1][1] = 0;
- __debug_regs->dbdr[1][0] = 0;
- __debug_regs->dbdr[1][1] = 0;
-
- asm volatile(" movgs gr0,dbar1 \n"
- " movgs gr0,dbmr10 \n"
- " movgs gr0,dbmr11 \n"
- " movgs gr0,dbdr10 \n"
- " movgs gr0,dbdr11 \n");
- return 0;
-
- skip_dbar1:
- return -ENOSPC;
-
- default:
- return -EINVAL;
- }
-} /* end gdbstub_clear_breakpoint() */
-
-/*****************************************************************************/
-/*
- * check a for an internal software breakpoint, and wind the PC back if necessary
- */
-static void gdbstub_check_breakpoint(void)
-{
- unsigned long addr = __debug_frame->pc - 4;
- int bkpt;
-
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (gdbstub_bkpts[bkpt].addr == addr)
- break;
- if (bkpt >= 0)
- __debug_frame->pc = addr;
-
- //gdbstub_printk("alter pc [%d] %08lx\n", bkpt, __debug_frame->pc);
-
-} /* end gdbstub_check_breakpoint() */
-
-/*****************************************************************************/
-/*
- *
- */
-static void __maybe_unused gdbstub_show_regs(void)
-{
- unsigned long *reg;
- int loop;
-
- gdbstub_printk("\n");
-
- gdbstub_printk("Frame: @%p [%s]\n",
- __debug_frame,
- __debug_frame->psr & PSR_S ? "kernel" : "user");
-
- reg = (unsigned long *) __debug_frame;
- for (loop = 0; loop < NR_PT_REGS; loop++) {
- printk("%s %08lx", regnames[loop + 0], reg[loop + 0]);
-
- if (loop == NR_PT_REGS - 1 || loop % 5 == 4)
- printk("\n");
- else
- printk(" | ");
- }
-
- gdbstub_printk("Process %s (pid: %d)\n", current->comm, current->pid);
-} /* end gdbstub_show_regs() */
-
-/*****************************************************************************/
-/*
- * dump debugging regs
- */
-static void __maybe_unused gdbstub_dump_debugregs(void)
-{
- gdbstub_printk("DCR %08lx ", __debug_status.dcr);
- gdbstub_printk("BRR %08lx\n", __debug_status.brr);
-
- gdbstub_printk("IBAR0 %08lx ", __get_ibar(0));
- gdbstub_printk("IBAR1 %08lx ", __get_ibar(1));
- gdbstub_printk("IBAR2 %08lx ", __get_ibar(2));
- gdbstub_printk("IBAR3 %08lx\n", __get_ibar(3));
-
- gdbstub_printk("DBAR0 %08lx ", __get_dbar(0));
- gdbstub_printk("DBMR00 %08lx ", __get_dbmr0(0));
- gdbstub_printk("DBMR01 %08lx\n", __get_dbmr1(0));
-
- gdbstub_printk("DBAR1 %08lx ", __get_dbar(1));
- gdbstub_printk("DBMR10 %08lx ", __get_dbmr0(1));
- gdbstub_printk("DBMR11 %08lx\n", __get_dbmr1(1));
-
- gdbstub_printk("\n");
-} /* end gdbstub_dump_debugregs() */
-
-/*****************************************************************************/
-/*
- * dump the MMU state into a structure so that it can be accessed with GDB
- */
-void gdbstub_get_mmu_state(void)
-{
- asm volatile("movsg hsr0,%0" : "=r"(__debug_mmu.regs.hsr0));
- asm volatile("movsg pcsr,%0" : "=r"(__debug_mmu.regs.pcsr));
- asm volatile("movsg esr0,%0" : "=r"(__debug_mmu.regs.esr0));
- asm volatile("movsg ear0,%0" : "=r"(__debug_mmu.regs.ear0));
- asm volatile("movsg epcr0,%0" : "=r"(__debug_mmu.regs.epcr0));
-
- /* read the protection / SAT registers */
- __debug_mmu.iamr[0].L = __get_IAMLR(0);
- __debug_mmu.iamr[0].P = __get_IAMPR(0);
- __debug_mmu.iamr[1].L = __get_IAMLR(1);
- __debug_mmu.iamr[1].P = __get_IAMPR(1);
- __debug_mmu.iamr[2].L = __get_IAMLR(2);
- __debug_mmu.iamr[2].P = __get_IAMPR(2);
- __debug_mmu.iamr[3].L = __get_IAMLR(3);
- __debug_mmu.iamr[3].P = __get_IAMPR(3);
- __debug_mmu.iamr[4].L = __get_IAMLR(4);
- __debug_mmu.iamr[4].P = __get_IAMPR(4);
- __debug_mmu.iamr[5].L = __get_IAMLR(5);
- __debug_mmu.iamr[5].P = __get_IAMPR(5);
- __debug_mmu.iamr[6].L = __get_IAMLR(6);
- __debug_mmu.iamr[6].P = __get_IAMPR(6);
- __debug_mmu.iamr[7].L = __get_IAMLR(7);
- __debug_mmu.iamr[7].P = __get_IAMPR(7);
- __debug_mmu.iamr[8].L = __get_IAMLR(8);
- __debug_mmu.iamr[8].P = __get_IAMPR(8);
- __debug_mmu.iamr[9].L = __get_IAMLR(9);
- __debug_mmu.iamr[9].P = __get_IAMPR(9);
- __debug_mmu.iamr[10].L = __get_IAMLR(10);
- __debug_mmu.iamr[10].P = __get_IAMPR(10);
- __debug_mmu.iamr[11].L = __get_IAMLR(11);
- __debug_mmu.iamr[11].P = __get_IAMPR(11);
- __debug_mmu.iamr[12].L = __get_IAMLR(12);
- __debug_mmu.iamr[12].P = __get_IAMPR(12);
- __debug_mmu.iamr[13].L = __get_IAMLR(13);
- __debug_mmu.iamr[13].P = __get_IAMPR(13);
- __debug_mmu.iamr[14].L = __get_IAMLR(14);
- __debug_mmu.iamr[14].P = __get_IAMPR(14);
- __debug_mmu.iamr[15].L = __get_IAMLR(15);
- __debug_mmu.iamr[15].P = __get_IAMPR(15);
-
- __debug_mmu.damr[0].L = __get_DAMLR(0);
- __debug_mmu.damr[0].P = __get_DAMPR(0);
- __debug_mmu.damr[1].L = __get_DAMLR(1);
- __debug_mmu.damr[1].P = __get_DAMPR(1);
- __debug_mmu.damr[2].L = __get_DAMLR(2);
- __debug_mmu.damr[2].P = __get_DAMPR(2);
- __debug_mmu.damr[3].L = __get_DAMLR(3);
- __debug_mmu.damr[3].P = __get_DAMPR(3);
- __debug_mmu.damr[4].L = __get_DAMLR(4);
- __debug_mmu.damr[4].P = __get_DAMPR(4);
- __debug_mmu.damr[5].L = __get_DAMLR(5);
- __debug_mmu.damr[5].P = __get_DAMPR(5);
- __debug_mmu.damr[6].L = __get_DAMLR(6);
- __debug_mmu.damr[6].P = __get_DAMPR(6);
- __debug_mmu.damr[7].L = __get_DAMLR(7);
- __debug_mmu.damr[7].P = __get_DAMPR(7);
- __debug_mmu.damr[8].L = __get_DAMLR(8);
- __debug_mmu.damr[8].P = __get_DAMPR(8);
- __debug_mmu.damr[9].L = __get_DAMLR(9);
- __debug_mmu.damr[9].P = __get_DAMPR(9);
- __debug_mmu.damr[10].L = __get_DAMLR(10);
- __debug_mmu.damr[10].P = __get_DAMPR(10);
- __debug_mmu.damr[11].L = __get_DAMLR(11);
- __debug_mmu.damr[11].P = __get_DAMPR(11);
- __debug_mmu.damr[12].L = __get_DAMLR(12);
- __debug_mmu.damr[12].P = __get_DAMPR(12);
- __debug_mmu.damr[13].L = __get_DAMLR(13);
- __debug_mmu.damr[13].P = __get_DAMPR(13);
- __debug_mmu.damr[14].L = __get_DAMLR(14);
- __debug_mmu.damr[14].P = __get_DAMPR(14);
- __debug_mmu.damr[15].L = __get_DAMLR(15);
- __debug_mmu.damr[15].P = __get_DAMPR(15);
-
-#ifdef CONFIG_MMU
- do {
- /* read the DAT entries from the TLB */
- struct __debug_amr *p;
- int loop;
-
- asm volatile("movsg tplr,%0" : "=r"(__debug_mmu.regs.tplr));
- asm volatile("movsg tppr,%0" : "=r"(__debug_mmu.regs.tppr));
- asm volatile("movsg tpxr,%0" : "=r"(__debug_mmu.regs.tpxr));
- asm volatile("movsg cxnr,%0" : "=r"(__debug_mmu.regs.cxnr));
-
- p = __debug_mmu.tlb;
-
- /* way 0 */
- asm volatile("movgs %0,tpxr" :: "r"(0 << TPXR_WAY_SHIFT));
- for (loop = 0; loop < 64; loop++) {
- asm volatile("tlbpr %0,gr0,#1,#0" :: "r"(loop << PAGE_SHIFT));
- asm volatile("movsg tplr,%0" : "=r"(p->L));
- asm volatile("movsg tppr,%0" : "=r"(p->P));
- p++;
- }
-
- /* way 1 */
- asm volatile("movgs %0,tpxr" :: "r"(1 << TPXR_WAY_SHIFT));
- for (loop = 0; loop < 64; loop++) {
- asm volatile("tlbpr %0,gr0,#1,#0" :: "r"(loop << PAGE_SHIFT));
- asm volatile("movsg tplr,%0" : "=r"(p->L));
- asm volatile("movsg tppr,%0" : "=r"(p->P));
- p++;
- }
-
- asm volatile("movgs %0,tplr" :: "r"(__debug_mmu.regs.tplr));
- asm volatile("movgs %0,tppr" :: "r"(__debug_mmu.regs.tppr));
- asm volatile("movgs %0,tpxr" :: "r"(__debug_mmu.regs.tpxr));
- } while(0);
-#endif
-
-} /* end gdbstub_get_mmu_state() */
-
-/*
- * handle general query commands of the form 'qXXXXX'
- */
-static void gdbstub_handle_query(void)
-{
- if (strcmp(input_buffer, "qAttached") == 0) {
- /* return current thread ID */
- sprintf(output_buffer, "1");
- return;
- }
-
- if (strcmp(input_buffer, "qC") == 0) {
- /* return current thread ID */
- sprintf(output_buffer, "QC 0");
- return;
- }
-
- if (strcmp(input_buffer, "qOffsets") == 0) {
- /* return relocation offset of text and data segments */
- sprintf(output_buffer, "Text=0;Data=0;Bss=0");
- return;
- }
-
- if (strcmp(input_buffer, "qSymbol::") == 0) {
- sprintf(output_buffer, "OK");
- return;
- }
-
- if (strcmp(input_buffer, "qSupported") == 0) {
- /* query of supported features */
- sprintf(output_buffer, "PacketSize=%u;ReverseContinue-;ReverseStep-",
- sizeof(input_buffer));
- return;
- }
-
- gdbstub_strcpy(output_buffer,"E01");
-}
-
-/*****************************************************************************/
-/*
- * handle event interception and GDB remote protocol processing
- * - on entry:
- * PSR.ET==0, PSR.S==1 and the CPU is in debug mode
- * __debug_frame points to the saved registers
- * __frame points to the kernel mode exception frame, if it was in kernel
- * mode when the break happened
- */
-void gdbstub(int sigval)
-{
- unsigned long addr, length, loop, dbar, temp, temp2, temp3;
- uint32_t zero;
- char *ptr;
- int flush_cache = 0;
-
- LEDS(0x5000);
-
- if (sigval < 0) {
-#ifndef CONFIG_GDBSTUB_IMMEDIATE
- /* return immediately if GDB immediate activation option not set */
- return;
-#else
- sigval = SIGINT;
-#endif
- }
-
- save_user_regs(&__debug_frame0->uc);
-
-#if 0
- gdbstub_printk("--> gdbstub() %08x %p %08x %08x\n",
- __debug_frame->pc,
- __debug_frame,
- __debug_regs->brr,
- __debug_regs->bpsr);
-// gdbstub_show_regs();
-#endif
-
- LEDS(0x5001);
-
- /* if we were interrupted by input on the serial gdbstub serial port,
- * restore the context prior to the interrupt so that we return to that
- * directly
- */
- temp = (unsigned long) __entry_kerneltrap_table;
- temp2 = (unsigned long) __entry_usertrap_table;
- temp3 = __debug_frame->pc & ~15;
-
- if (temp3 == temp + TBR_TT_INTERRUPT_15 ||
- temp3 == temp2 + TBR_TT_INTERRUPT_15
- ) {
- asm volatile("movsg pcsr,%0" : "=r"(__debug_frame->pc));
- __debug_frame->psr |= PSR_ET;
- __debug_frame->psr &= ~PSR_S;
- if (__debug_frame->psr & PSR_PS)
- __debug_frame->psr |= PSR_S;
- __debug_status.brr = (__debug_frame->tbr & TBR_TT) << 12;
- __debug_status.brr |= BRR_EB;
- sigval = SIGINT;
- }
-
- /* handle the decrement timer going off (FR451 only) */
- if (temp3 == temp + TBR_TT_DECREMENT_TIMER ||
- temp3 == temp2 + TBR_TT_DECREMENT_TIMER
- ) {
- asm volatile("movgs %0,timerd" :: "r"(10000000));
- asm volatile("movsg pcsr,%0" : "=r"(__debug_frame->pc));
- __debug_frame->psr |= PSR_ET;
- __debug_frame->psr &= ~PSR_S;
- if (__debug_frame->psr & PSR_PS)
- __debug_frame->psr |= PSR_S;
- __debug_status.brr = (__debug_frame->tbr & TBR_TT) << 12;
- __debug_status.brr |= BRR_EB;
- sigval = SIGXCPU;
- }
-
- LEDS(0x5002);
-
- /* after a BREAK insn, the PC lands on the far side of it */
- if (__debug_status.brr & BRR_SB)
- gdbstub_check_breakpoint();
-
- LEDS(0x5003);
-
- /* handle attempts to write console data via GDB "O" commands */
- if (__debug_frame->pc == (unsigned long) gdbstub_console_write + 4) {
- __gdbstub_console_write((struct console *) __debug_frame->gr8,
- (const char *) __debug_frame->gr9,
- (unsigned) __debug_frame->gr10);
- goto done;
- }
-
- if (gdbstub_rx_unget) {
- sigval = SIGINT;
- goto packet_waiting;
- }
-
- if (!sigval)
- sigval = gdbstub_compute_signal(__debug_status.brr);
-
- LEDS(0x5004);
-
- /* send a message to the debugger's user saying what happened if it may
- * not be clear cut (we can't map exceptions onto signals properly)
- */
- if (sigval != SIGINT && sigval != SIGTRAP && sigval != SIGILL) {
- static const char title[] = "Break ";
- static const char crlf[] = "\r\n";
- unsigned long brr = __debug_status.brr;
- char hx;
-
- ptr = output_buffer;
- *ptr++ = 'O';
- ptr = mem2hex(title, ptr, sizeof(title) - 1,0);
-
- hx = hex_asc_hi(brr >> 24);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr >> 24);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(brr >> 16);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr >> 16);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(brr >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(brr);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(brr);
- ptr = hex_byte_pack(ptr, hx);
-
- ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0);
- *ptr = 0;
- gdbstub_send_packet(output_buffer); /* send it off... */
- }
-
- LEDS(0x5005);
-
- /* tell the debugger that an exception has occurred */
- ptr = output_buffer;
-
- /* Send trap type (converted to signal) */
- *ptr++ = 'T';
- ptr = hex_byte_pack(ptr, sigval);
-
- /* Send Error PC */
- ptr = hex_byte_pack(ptr, GDB_REG_PC);
- *ptr++ = ':';
- ptr = mem2hex(&__debug_frame->pc, ptr, 4, 0);
- *ptr++ = ';';
-
- /*
- * Send frame pointer
- */
- ptr = hex_byte_pack(ptr, GDB_REG_FP);
- *ptr++ = ':';
- ptr = mem2hex(&__debug_frame->fp, ptr, 4, 0);
- *ptr++ = ';';
-
- /*
- * Send stack pointer
- */
- ptr = hex_byte_pack(ptr, GDB_REG_SP);
- *ptr++ = ':';
- ptr = mem2hex(&__debug_frame->sp, ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = 0;
- gdbstub_send_packet(output_buffer); /* send it off... */
-
- LEDS(0x5006);
-
- packet_waiting:
- gdbstub_get_mmu_state();
-
- /* wait for input from remote GDB */
- while (1) {
- output_buffer[0] = 0;
-
- LEDS(0x5007);
- gdbstub_recv_packet(input_buffer);
- LEDS(0x5600 | input_buffer[0]);
-
- switch (input_buffer[0]) {
- /* request repeat of last signal number */
- case '?':
- output_buffer[0] = 'S';
- output_buffer[1] = hex_asc_hi(sigval);
- output_buffer[2] = hex_asc_lo(sigval);
- output_buffer[3] = 0;
- break;
-
- case 'd':
- /* toggle debug flag */
- break;
-
- /* return the value of the CPU registers
- * - GR0, GR1, GR2, GR3, GR4, GR5, GR6, GR7,
- * - GR8, GR9, GR10, GR11, GR12, GR13, GR14, GR15,
- * - GR16, GR17, GR18, GR19, GR20, GR21, GR22, GR23,
- * - GR24, GR25, GR26, GR27, GR28, GR29, GR30, GR31,
- * - GR32, GR33, GR34, GR35, GR36, GR37, GR38, GR39,
- * - GR40, GR41, GR42, GR43, GR44, GR45, GR46, GR47,
- * - GR48, GR49, GR50, GR51, GR52, GR53, GR54, GR55,
- * - GR56, GR57, GR58, GR59, GR60, GR61, GR62, GR63,
- * - FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
- * - FP8, FP9, FP10, FP11, FP12, FP13, FP14, FP15,
- * - FP16, FP17, FP18, FP19, FP20, FP21, FP22, FP23,
- * - FP24, FP25, FP26, FP27, FP28, FP29, FP30, FP31,
- * - FP32, FP33, FP34, FP35, FP36, FP37, FP38, FP39,
- * - FP40, FP41, FP42, FP43, FP44, FP45, FP46, FP47,
- * - FP48, FP49, FP50, FP51, FP52, FP53, FP54, FP55,
- * - FP56, FP57, FP58, FP59, FP60, FP61, FP62, FP63,
- * - PC, PSR, CCR, CCCR,
- * - _X132, _X133, _X134
- * - TBR, BRR, DBAR0, DBAR1, DBAR2, DBAR3,
- * - _X141, _X142, _X143, _X144,
- * - LR, LCR
- */
- case 'g':
- zero = 0;
- ptr = output_buffer;
-
- /* deal with GR0, GR1-GR27, GR28-GR31, GR32-GR63 */
- ptr = mem2hex(&zero, ptr, 4, 0);
-
- for (loop = 1; loop <= 27; loop++)
- ptr = mem2hex(&__debug_user_context->i.gr[loop], ptr, 4, 0);
- temp = (unsigned long) __frame;
- ptr = mem2hex(&temp, ptr, 4, 0);
- ptr = mem2hex(&__debug_user_context->i.gr[29], ptr, 4, 0);
- ptr = mem2hex(&__debug_user_context->i.gr[30], ptr, 4, 0);
-#ifdef CONFIG_MMU
- ptr = mem2hex(&__debug_user_context->i.gr[31], ptr, 4, 0);
-#else
- temp = (unsigned long) __debug_frame;
- ptr = mem2hex(&temp, ptr, 4, 0);
-#endif
-
- for (loop = 32; loop <= 63; loop++)
- ptr = mem2hex(&__debug_user_context->i.gr[loop], ptr, 4, 0);
-
- /* deal with FR0-FR63 */
- for (loop = 0; loop <= 63; loop++)
- ptr = mem2hex(&__debug_user_context->f.fr[loop], ptr, 4, 0);
-
- /* deal with special registers */
- ptr = mem2hex(&__debug_frame->pc, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->psr, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->ccr, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->cccr, ptr, 4, 0);
- ptr = mem2hex(&zero, ptr, 4, 0);
- ptr = mem2hex(&zero, ptr, 4, 0);
- ptr = mem2hex(&zero, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->tbr, ptr, 4, 0);
- ptr = mem2hex(&__debug_status.brr , ptr, 4, 0);
-
- asm volatile("movsg dbar0,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg dbar1,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg dbar2,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg dbar3,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
-
- asm volatile("movsg scr0,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg scr1,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg scr2,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
- asm volatile("movsg scr3,%0" : "=r"(dbar));
- ptr = mem2hex(&dbar, ptr, 4, 0);
-
- ptr = mem2hex(&__debug_frame->lr, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->lcr, ptr, 4, 0);
-
- ptr = mem2hex(&__debug_frame->iacc0, ptr, 8, 0);
-
- ptr = mem2hex(&__debug_user_context->f.fsr[0], ptr, 4, 0);
-
- for (loop = 0; loop <= 7; loop++)
- ptr = mem2hex(&__debug_user_context->f.acc[loop], ptr, 4, 0);
-
- ptr = mem2hex(&__debug_user_context->f.accg, ptr, 8, 0);
-
- for (loop = 0; loop <= 1; loop++)
- ptr = mem2hex(&__debug_user_context->f.msr[loop], ptr, 4, 0);
-
- ptr = mem2hex(&__debug_frame->gner0, ptr, 4, 0);
- ptr = mem2hex(&__debug_frame->gner1, ptr, 4, 0);
-
- ptr = mem2hex(&__debug_user_context->f.fner[0], ptr, 4, 0);
- ptr = mem2hex(&__debug_user_context->f.fner[1], ptr, 4, 0);
-
- break;
-
- /* set the values of the CPU registers */
- case 'G':
- ptr = &input_buffer[1];
-
- /* deal with GR0, GR1-GR27, GR28-GR31, GR32-GR63 */
- ptr = hex2mem(ptr, &temp, 4);
-
- for (loop = 1; loop <= 27; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->i.gr[loop], 4);
-
- ptr = hex2mem(ptr, &temp, 4);
- __frame = (struct pt_regs *) temp;
- ptr = hex2mem(ptr, &__debug_frame->gr29, 4);
- ptr = hex2mem(ptr, &__debug_frame->gr30, 4);
-#ifdef CONFIG_MMU
- ptr = hex2mem(ptr, &__debug_frame->gr31, 4);
-#else
- ptr = hex2mem(ptr, &temp, 4);
-#endif
-
- for (loop = 32; loop <= 63; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->i.gr[loop], 4);
-
- /* deal with FR0-FR63 */
- for (loop = 0; loop <= 63; loop++)
- ptr = mem2hex(&__debug_user_context->f.fr[loop], ptr, 4, 0);
-
- /* deal with special registers */
- ptr = hex2mem(ptr, &__debug_frame->pc, 4);
- ptr = hex2mem(ptr, &__debug_frame->psr, 4);
- ptr = hex2mem(ptr, &__debug_frame->ccr, 4);
- ptr = hex2mem(ptr, &__debug_frame->cccr,4);
-
- for (loop = 132; loop <= 140; loop++)
- ptr = hex2mem(ptr, &temp, 4);
-
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr0" :: "r"(temp));
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr1" :: "r"(temp));
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr2" :: "r"(temp));
- ptr = hex2mem(ptr, &temp, 4);
- asm volatile("movgs %0,scr3" :: "r"(temp));
-
- ptr = hex2mem(ptr, &__debug_frame->lr, 4);
- ptr = hex2mem(ptr, &__debug_frame->lcr, 4);
-
- ptr = hex2mem(ptr, &__debug_frame->iacc0, 8);
-
- ptr = hex2mem(ptr, &__debug_user_context->f.fsr[0], 4);
-
- for (loop = 0; loop <= 7; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->f.acc[loop], 4);
-
- ptr = hex2mem(ptr, &__debug_user_context->f.accg, 8);
-
- for (loop = 0; loop <= 1; loop++)
- ptr = hex2mem(ptr, &__debug_user_context->f.msr[loop], 4);
-
- ptr = hex2mem(ptr, &__debug_frame->gner0, 4);
- ptr = hex2mem(ptr, &__debug_frame->gner1, 4);
-
- ptr = hex2mem(ptr, &__debug_user_context->f.fner[0], 4);
- ptr = hex2mem(ptr, &__debug_user_context->f.fner[1], 4);
-
- gdbstub_strcpy(output_buffer,"OK");
- break;
-
- /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */
- case 'm':
- ptr = &input_buffer[1];
-
- if (hexToInt(&ptr, &addr) &&
- *ptr++ == ',' &&
- hexToInt(&ptr, &length)
- ) {
- if (mem2hex((char *)addr, output_buffer, length, 1))
- break;
- gdbstub_strcpy (output_buffer, "E03");
- }
- else {
- gdbstub_strcpy(output_buffer,"E01");
- }
- break;
-
- /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
- case 'M':
- ptr = &input_buffer[1];
-
- if (hexToInt(&ptr, &addr) &&
- *ptr++ == ',' &&
- hexToInt(&ptr, &length) &&
- *ptr++ == ':'
- ) {
- if (hex2mem(ptr, (char *)addr, length)) {
- gdbstub_strcpy(output_buffer, "OK");
- }
- else {
- gdbstub_strcpy(output_buffer, "E03");
- }
- }
- else
- gdbstub_strcpy(output_buffer, "E02");
-
- flush_cache = 1;
- break;
-
- /* pNN: Read value of reg N and return it */
- case 'p':
- /* return no value, indicating that we don't support
- * this command and that gdb should use 'g' instead */
- break;
-
- /* PNN,=RRRRRRRR: Write value R to reg N return OK */
- case 'P':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr, &addr) ||
- *ptr++ != '=' ||
- !hexToInt(&ptr, &temp)
- ) {
- gdbstub_strcpy(output_buffer, "E01");
- break;
- }
-
- temp2 = 1;
- switch (addr) {
- case GDB_REG_GR(0):
- break;
- case GDB_REG_GR(1) ... GDB_REG_GR(63):
- __debug_user_context->i.gr[addr - GDB_REG_GR(0)] = temp;
- break;
- case GDB_REG_FR(0) ... GDB_REG_FR(63):
- __debug_user_context->f.fr[addr - GDB_REG_FR(0)] = temp;
- break;
- case GDB_REG_PC:
- __debug_user_context->i.pc = temp;
- break;
- case GDB_REG_PSR:
- __debug_user_context->i.psr = temp;
- break;
- case GDB_REG_CCR:
- __debug_user_context->i.ccr = temp;
- break;
- case GDB_REG_CCCR:
- __debug_user_context->i.cccr = temp;
- break;
- case GDB_REG_BRR:
- __debug_status.brr = temp;
- break;
- case GDB_REG_LR:
- __debug_user_context->i.lr = temp;
- break;
- case GDB_REG_LCR:
- __debug_user_context->i.lcr = temp;
- break;
- case GDB_REG_FSR0:
- __debug_user_context->f.fsr[0] = temp;
- break;
- case GDB_REG_ACC(0) ... GDB_REG_ACC(7):
- __debug_user_context->f.acc[addr - GDB_REG_ACC(0)] = temp;
- break;
- case GDB_REG_ACCG(0):
- *(uint32_t *) &__debug_user_context->f.accg[0] = temp;
- break;
- case GDB_REG_ACCG(4):
- *(uint32_t *) &__debug_user_context->f.accg[4] = temp;
- break;
- case GDB_REG_MSR(0) ... GDB_REG_MSR(1):
- __debug_user_context->f.msr[addr - GDB_REG_MSR(0)] = temp;
- break;
- case GDB_REG_GNER(0) ... GDB_REG_GNER(1):
- __debug_user_context->i.gner[addr - GDB_REG_GNER(0)] = temp;
- break;
- case GDB_REG_FNER(0) ... GDB_REG_FNER(1):
- __debug_user_context->f.fner[addr - GDB_REG_FNER(0)] = temp;
- break;
- default:
- temp2 = 0;
- break;
- }
-
- if (temp2) {
- gdbstub_strcpy(output_buffer, "OK");
- }
- else {
- gdbstub_strcpy(output_buffer, "E02");
- }
- break;
-
- /* cAA..AA Continue at address AA..AA(optional) */
- case 'c':
- /* try to read optional parameter, pc unchanged if no parm */
- ptr = &input_buffer[1];
- if (hexToInt(&ptr, &addr))
- __debug_frame->pc = addr;
- goto done;
-
- /* kill the program */
- case 'k' :
- goto done; /* just continue */
-
- /* detach */
- case 'D':
- gdbstub_strcpy(output_buffer, "OK");
- break;
-
- /* reset the whole machine (FIXME: system dependent) */
- case 'r':
- break;
-
-
- /* step to next instruction */
- case 's':
- __debug_regs->dcr |= DCR_SE;
- __debug_status.dcr |= DCR_SE;
- goto done;
-
- /* extended command */
- case 'v':
- if (strcmp(input_buffer, "vCont?") == 0) {
- output_buffer[0] = 0;
- break;
- }
- goto unsupported_cmd;
-
- /* set baud rate (bBB) */
- case 'b':
- ptr = &input_buffer[1];
- if (!hexToInt(&ptr, &temp)) {
- gdbstub_strcpy(output_buffer,"B01");
- break;
- }
-
- if (temp) {
- /* ack before changing speed */
- gdbstub_send_packet("OK");
- gdbstub_set_baud(temp);
- }
- break;
-
- /* set breakpoint */
- case 'Z':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr,&temp) || *ptr++ != ',' ||
- !hexToInt(&ptr,&addr) || *ptr++ != ',' ||
- !hexToInt(&ptr,&length)
- ) {
- gdbstub_strcpy(output_buffer,"E01");
- break;
- }
-
- if (temp >= 5) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (gdbstub_set_breakpoint(temp, addr, length) < 0) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (temp == 0)
- flush_cache = 1; /* soft bkpt by modified memory */
-
- gdbstub_strcpy(output_buffer,"OK");
- break;
-
- /* clear breakpoint */
- case 'z':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr,&temp) || *ptr++ != ',' ||
- !hexToInt(&ptr,&addr) || *ptr++ != ',' ||
- !hexToInt(&ptr,&length)
- ) {
- gdbstub_strcpy(output_buffer,"E01");
- break;
- }
-
- if (temp >= 5) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (gdbstub_clear_breakpoint(temp, addr, length) < 0) {
- gdbstub_strcpy(output_buffer,"E03");
- break;
- }
-
- if (temp == 0)
- flush_cache = 1; /* soft bkpt by modified memory */
-
- gdbstub_strcpy(output_buffer,"OK");
- break;
-
- /* Thread-setting packet */
- case 'H':
- gdbstub_strcpy(output_buffer, "OK");
- break;
-
- case 'q':
- gdbstub_handle_query();
- break;
-
- default:
- unsupported_cmd:
- gdbstub_proto("### GDB Unsupported Cmd '%s'\n",input_buffer);
- gdbstub_strcpy(output_buffer,"E01");
- break;
- }
-
- /* reply to the request */
- LEDS(0x5009);
- gdbstub_send_packet(output_buffer);
- }
-
- done:
- restore_user_regs(&__debug_frame0->uc);
-
- //gdbstub_dump_debugregs();
- //gdbstub_printk("<-- gdbstub() %08x\n", __debug_frame->pc);
-
- /* need to flush the instruction cache before resuming, as we may have
- * deposited a breakpoint, and the icache probably has no way of
- * knowing that a data ref to some location may have changed something
- * that is in the instruction cache. NB: We flush both caches, just to
- * be sure...
- */
-
- /* note: flushing the icache will clobber EAR0 on the FR451 */
- if (flush_cache)
- gdbstub_purge_cache();
-
- LEDS(0x5666);
-
-} /* end gdbstub() */
-
-/*****************************************************************************/
-/*
- * initialise the GDB stub
- */
-void __init gdbstub_init(void)
-{
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- unsigned char ch;
- int ret;
-#endif
-
- gdbstub_printk("%s", gdbstub_banner);
-
- gdbstub_io_init();
-
- /* try to talk to GDB (or anyone insane enough to want to type GDB protocol by hand) */
- gdbstub_proto("### GDB Tx ACK\n");
- gdbstub_tx_char('+'); /* 'hello world' */
-
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- gdbstub_printk("GDB Stub waiting for packet\n");
-
- /*
- * In case GDB is started before us, ack any packets
- * (presumably "$?#xx") sitting there.
- */
- do { gdbstub_rx_char(&ch, 0); } while (ch != '$');
- do { gdbstub_rx_char(&ch, 0); } while (ch != '#');
- do { ret = gdbstub_rx_char(&ch, 0); } while (ret != 0); /* eat first csum byte */
- do { ret = gdbstub_rx_char(&ch, 0); } while (ret != 0); /* eat second csum byte */
-
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_tx_char('-'); /* nak it */
-
-#else
- gdbstub_printk("GDB Stub set\n");
-#endif
-
-#if 0
- /* send banner */
- ptr = output_buffer;
- *ptr++ = 'O';
- ptr = mem2hex(gdbstub_banner, ptr, sizeof(gdbstub_banner) - 1, 0);
- gdbstub_send_packet(output_buffer);
-#endif
-#if defined(CONFIG_GDB_CONSOLE) && defined(CONFIG_GDBSTUB_IMMEDIATE)
- register_console(&gdbstub_console);
-#endif
-
-} /* end gdbstub_init() */
-
-/*****************************************************************************/
-/*
- * register the console at a more appropriate time
- */
-#if defined (CONFIG_GDB_CONSOLE) && !defined(CONFIG_GDBSTUB_IMMEDIATE)
-static int __init gdbstub_postinit(void)
-{
- printk("registering console\n");
- register_console(&gdbstub_console);
- return 0;
-} /* end gdbstub_postinit() */
-
-__initcall(gdbstub_postinit);
-#endif
-
-/*****************************************************************************/
-/*
- * send an exit message to GDB
- */
-void gdbstub_exit(int status)
-{
- unsigned char checksum;
- int count;
- unsigned char ch;
-
- sprintf(output_buffer,"W%02x",status&0xff);
-
- gdbstub_tx_char('$');
- checksum = 0;
- count = 0;
-
- while ((ch = output_buffer[count]) != 0) {
- gdbstub_tx_char(ch);
- checksum += ch;
- count += 1;
- }
-
- gdbstub_tx_char('#');
- gdbstub_tx_char(hex_asc_hi(checksum));
- gdbstub_tx_char(hex_asc_lo(checksum));
-
- /* make sure the output is flushed, or else RedBoot might clobber it */
- gdbstub_tx_char('-');
- gdbstub_tx_flush();
-
-} /* end gdbstub_exit() */
-
-/*****************************************************************************/
-/*
- * GDB wants to call malloc() and free() to allocate memory for calling kernel
- * functions directly from its command line
- */
-static void *malloc(size_t size) __maybe_unused;
-static void *malloc(size_t size)
-{
- return kmalloc(size, GFP_ATOMIC);
-}
-
-static void free(void *p) __maybe_unused;
-static void free(void *p)
-{
- kfree(p);
-}
-
-static uint32_t ___get_HSR0(void) __maybe_unused;
-static uint32_t ___get_HSR0(void)
-{
- return __get_HSR(0);
-}
-
-static uint32_t ___set_HSR0(uint32_t x) __maybe_unused;
-static uint32_t ___set_HSR0(uint32_t x)
-{
- __set_HSR(0, x);
- return __get_HSR(0);
-}
diff --git a/arch/frv/kernel/head-mmu-fr451.S b/arch/frv/kernel/head-mmu-fr451.S
deleted file mode 100644
index 98f87d586e59..000000000000
--- a/arch/frv/kernel/head-mmu-fr451.S
+++ /dev/null
@@ -1,374 +0,0 @@
-/* head-mmu-fr451.S: FR451 mmu-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/mem-layout.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __400_DBR0 0xfe000e00
-#define __400_DBR1 0xfe000e08
-#define __400_DBR2 0xfe000e10
-#define __400_DBR3 0xfe000e18
-#define __400_DAM0 0xfe000f00
-#define __400_DAM1 0xfe000f08
-#define __400_DAM2 0xfe000f10
-#define __400_DAM3 0xfe000f18
-#define __400_LGCR 0xfe000010
-#define __400_LCR 0xfe000100
-#define __400_LSBR 0xfe000c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# describe the position and layout of the SDRAM controller registers
-#
-# ENTRY: EXIT:
-# GR5 - cacheline size
-# GR11 - displacement of 2nd SDRAM addr reg from GR14
-# GR12 - displacement of 3rd SDRAM addr reg from GR14
-# GR13 - displacement of 4th SDRAM addr reg from GR14
-# GR14 - address of 1st SDRAM addr reg
-# GR15 - amount to shift address by to match SDRAM addr reg
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-# CC0 - T if DBR0 is present
-# CC1 - T if DBR1 is present
-# CC2 - T if DBR2 is present
-# CC3 - T if DBR3 is present
-#
-###############################################################################
- .globl __head_fr451_describe_sdram
-__head_fr451_describe_sdram:
- sethi.p %hi(__400_DBR0),gr14
- setlo %lo(__400_DBR0),gr14
- setlos.p #__400_DBR1-__400_DBR0,gr11
- setlos #__400_DBR2-__400_DBR0,gr12
- setlos.p #__400_DBR3-__400_DBR0,gr13
- setlos #32,gr5 ; cacheline size
- setlos.p #0,gr15 ; amount to shift addr reg by
- setlos #0x00ff,gr4
- movgs gr4,cccr ; extant DARS/DAMK regs
- bralr
-
-###############################################################################
-#
-# rearrange the bus controller registers
-#
-# ENTRY: EXIT:
-# GR26 &__head_reference [saved]
-# GR30 LED address revised LED address
-#
-###############################################################################
- .globl __head_fr451_set_busctl
-__head_fr451_set_busctl:
- sethi.p %hi(__400_LGCR),gr4
- setlo %lo(__400_LGCR),gr4
- sethi.p %hi(__400_LSBR),gr10
- setlo %lo(__400_LSBR),gr10
- sethi.p %hi(__400_LCR),gr11
- setlo %lo(__400_LCR),gr11
-
- # set the bus controller
- ldi @(gr4,#0),gr5
- ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled
- sti gr5,@(gr4,#0)
-
- sethi.p %hi(__region_CS1),gr4
- setlo %lo(__region_CS1),gr4
- sethi.p %hi(__region_CS1_M),gr5
- setlo %lo(__region_CS1_M),gr5
- sethi.p %hi(__region_CS1_C),gr6
- setlo %lo(__region_CS1_C),gr6
- sti gr4,@(gr10,#1*0x08)
- sti gr5,@(gr10,#1*0x08+0x100)
- sti gr6,@(gr11,#1*0x08)
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- sethi.p %hi(__region_CS2_M),gr5
- setlo %lo(__region_CS2_M),gr5
- sethi.p %hi(__region_CS2_C),gr6
- setlo %lo(__region_CS2_C),gr6
- sti gr4,@(gr10,#2*0x08)
- sti gr5,@(gr10,#2*0x08+0x100)
- sti gr6,@(gr11,#2*0x08)
- sethi.p %hi(__region_CS3),gr4
- setlo %lo(__region_CS3),gr4
- sethi.p %hi(__region_CS3_M),gr5
- setlo %lo(__region_CS3_M),gr5
- sethi.p %hi(__region_CS3_C),gr6
- setlo %lo(__region_CS3_C),gr6
- sti gr4,@(gr10,#3*0x08)
- sti gr5,@(gr10,#3*0x08+0x100)
- sti gr6,@(gr11,#3*0x08)
- sethi.p %hi(__region_CS4),gr4
- setlo %lo(__region_CS4),gr4
- sethi.p %hi(__region_CS4_M),gr5
- setlo %lo(__region_CS4_M),gr5
- sethi.p %hi(__region_CS4_C),gr6
- setlo %lo(__region_CS4_C),gr6
- sti gr4,@(gr10,#4*0x08)
- sti gr5,@(gr10,#4*0x08+0x100)
- sti gr6,@(gr11,#4*0x08)
- sethi.p %hi(__region_CS5),gr4
- setlo %lo(__region_CS5),gr4
- sethi.p %hi(__region_CS5_M),gr5
- setlo %lo(__region_CS5_M),gr5
- sethi.p %hi(__region_CS5_C),gr6
- setlo %lo(__region_CS5_C),gr6
- sti gr4,@(gr10,#5*0x08)
- sti gr5,@(gr10,#5*0x08+0x100)
- sti gr6,@(gr11,#5*0x08)
- sethi.p %hi(__region_CS6),gr4
- setlo %lo(__region_CS6),gr4
- sethi.p %hi(__region_CS6_M),gr5
- setlo %lo(__region_CS6_M),gr5
- sethi.p %hi(__region_CS6_C),gr6
- setlo %lo(__region_CS6_C),gr6
- sti gr4,@(gr10,#6*0x08)
- sti gr5,@(gr10,#6*0x08+0x100)
- sti gr6,@(gr11,#6*0x08)
- sethi.p %hi(__region_CS7),gr4
- setlo %lo(__region_CS7),gr4
- sethi.p %hi(__region_CS7_M),gr5
- setlo %lo(__region_CS7_M),gr5
- sethi.p %hi(__region_CS7_C),gr6
- setlo %lo(__region_CS7_C),gr6
- sti gr4,@(gr10,#7*0x08)
- sti gr5,@(gr10,#7*0x08+0x100)
- sti gr6,@(gr11,#7*0x08)
- membar
- bar
-
- # adjust LED bank address
-#ifdef CONFIG_MB93091_VDK
- sethi.p %hi(__region_CS2 + 0x01200004),gr30
- setlo %lo(__region_CS2 + 0x01200004),gr30
-#endif
- bralr
-
-###############################################################################
-#
-# determine the total SDRAM size
-#
-# ENTRY: EXIT:
-# GR25 - SDRAM size
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr451_survey_sdram
-__head_fr451_survey_sdram:
- sethi.p %hi(__400_DAM0),gr11
- setlo %lo(__400_DAM0),gr11
- sethi.p %hi(__400_DBR0),gr12
- setlo %lo(__400_DBR0),gr12
-
- sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
- setlo %lo(0xfe000000),gr17
- setlos #0,gr25
-
- ldi @(gr12,#0x00),gr4 ; DAR0
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS0
- ldi @(gr11,#0x00),gr6 ; DAM0: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS0:
-
- ldi @(gr12,#0x08),gr4 ; DAR1
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS1
- ldi @(gr11,#0x08),gr6 ; DAM1: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS1:
-
- ldi @(gr12,#0x10),gr4 ; DAR2
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS2
- ldi @(gr11,#0x10),gr6 ; DAM2: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS2:
-
- ldi @(gr12,#0x18),gr4 ; DAR3
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS3
- ldi @(gr11,#0x18),gr6 ; DAM3: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS3:
- bralr
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size [saved]
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-#
-# Using this map:
-# REGISTERS ADDRESS RANGE VIEW
-# =============== ====================== ===============================
-# IAMPR0/DAMPR0 0xC0000000-0xCFFFFFFF Cached kernel RAM Window
-# DAMPR11 0xE0000000-0xFFFFFFFF Uncached I/O
-#
-###############################################################################
- .globl __head_fr451_set_protection
-__head_fr451_set_protection:
- movsg lr,gr27
-
- # set the I/O region protection registers for FR451 in MMU mode
-#define PGPROT_IO xAMPRx_L|xAMPRx_M|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V
-
- sethi.p %hi(__region_IO),gr5
- setlo %lo(__region_IO),gr5
- setlos #PGPROT_IO|xAMPRx_SS_512Mb,gr4
- or gr4,gr5,gr4
- movgs gr5,damlr11 ; General I/O tile
- movgs gr4,dampr11
-
- # need to open a window onto at least part of the RAM for the kernel's use
- sethi.p %hi(__sdram_base),gr8
- setlo %lo(__sdram_base),gr8 ; physical address
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9 ; virtual address
-
- setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr11
- or gr8,gr11,gr8
-
- movgs gr9,iamlr0 ; mapped from real address 0
- movgs gr8,iampr0 ; cached kernel memory at 0xC0000000
- movgs gr9,damlr0
- movgs gr8,dampr0
-
- # set a temporary mapping for the kernel running at address 0 until we've turned on the MMU
- sethi.p %hi(__sdram_base),gr9
- setlo %lo(__sdram_base),gr9 ; virtual address
-
- and.p gr4,gr11,gr4
- and gr5,gr11,gr5
- or.p gr4,gr11,gr4
- or gr5,gr11,gr5
-
- movgs gr9,iamlr1 ; mapped from real address 0
- movgs gr8,iampr1 ; cached kernel memory at 0x00000000
- movgs gr9,damlr1
- movgs gr8,dampr1
-
- # we use DAMR2-10 for kmap_atomic(), cache flush and TLB management
- # since the DAMLR regs are not going to change, we can set them now
- # also set up IAMLR2 to the same as DAMLR5
- sethi.p %hi(KMAP_ATOMIC_PRIMARY_FRAME),gr4
- setlo %lo(KMAP_ATOMIC_PRIMARY_FRAME),gr4
- sethi.p %hi(PAGE_SIZE),gr5
- setlo %lo(PAGE_SIZE),gr5
-
- movgs gr4,damlr2
- movgs gr4,iamlr2
- add gr4,gr5,gr4
- movgs gr4,damlr3
- add gr4,gr5,gr4
- movgs gr4,damlr4
- add gr4,gr5,gr4
- movgs gr4,damlr5
- add gr4,gr5,gr4
- movgs gr4,damlr6
- add gr4,gr5,gr4
- movgs gr4,damlr7
- add gr4,gr5,gr4
- movgs gr4,damlr8
- add gr4,gr5,gr4
- movgs gr4,damlr9
- add gr4,gr5,gr4
- movgs gr4,damlr10
-
- movgs gr0,dampr2
- movgs gr0,dampr4
- movgs gr0,dampr5
- movgs gr0,dampr6
- movgs gr0,dampr7
- movgs gr0,dampr8
- movgs gr0,dampr9
- movgs gr0,dampr10
-
- movgs gr0,iamlr3
- movgs gr0,iamlr4
- movgs gr0,iamlr5
- movgs gr0,iamlr6
- movgs gr0,iamlr7
-
- movgs gr0,iampr2
- movgs gr0,iampr3
- movgs gr0,iampr4
- movgs gr0,iampr5
- movgs gr0,iampr6
- movgs gr0,iampr7
-
- # start in TLB context 0 with the swapper's page tables
- movgs gr0,cxnr
-
- sethi.p %hi(swapper_pg_dir),gr4
- setlo %lo(swapper_pg_dir),gr4
- sethi.p %hi(__page_offset),gr5
- setlo %lo(__page_offset),gr5
- sub gr4,gr5,gr4
- movgs gr4,ttbr
- setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr5
- or gr4,gr5,gr4
- movgs gr4,dampr3
-
- # the FR451 also has an extra trap base register
- movsg tbr,gr4
- movgs gr4,btbr
-
- LEDS 0x3300
- jmpl @(gr27,gr0)
-
-###############################################################################
-#
-# finish setting up the protection registers
-#
-###############################################################################
- .globl __head_fr451_finalise_protection
-__head_fr451_finalise_protection:
- # turn on the timers as appropriate
- movgs gr0,timerh
- movgs gr0,timerl
- movgs gr0,timerd
- movsg hsr0,gr4
- sethi.p %hi(HSR0_ETMI),gr5
- setlo %lo(HSR0_ETMI),gr5
- or gr4,gr5,gr4
- movgs gr4,hsr0
-
- # clear the TLB entry cache
- movgs gr0,iamlr1
- movgs gr0,iampr1
- movgs gr0,damlr1
- movgs gr0,dampr1
-
- # clear the PGE cache
- sethi.p %hi(__flush_tlb_all),gr4
- setlo %lo(__flush_tlb_all),gr4
- jmpl @(gr4,gr0)
diff --git a/arch/frv/kernel/head-uc-fr401.S b/arch/frv/kernel/head-uc-fr401.S
deleted file mode 100644
index 438643cfa38e..000000000000
--- a/arch/frv/kernel/head-uc-fr401.S
+++ /dev/null
@@ -1,311 +0,0 @@
-/* head-uc-fr401.S: FR401/3/5 uc-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __400_DBR0 0xfe000e00
-#define __400_DBR1 0xfe000e08
-#define __400_DBR2 0xfe000e10 /* not on FR401 */
-#define __400_DBR3 0xfe000e18 /* not on FR401 */
-#define __400_DAM0 0xfe000f00
-#define __400_DAM1 0xfe000f08
-#define __400_DAM2 0xfe000f10 /* not on FR401 */
-#define __400_DAM3 0xfe000f18 /* not on FR401 */
-#define __400_LGCR 0xfe000010
-#define __400_LCR 0xfe000100
-#define __400_LSBR 0xfe000c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# describe the position and layout of the SDRAM controller registers
-#
-# ENTRY: EXIT:
-# GR5 - cacheline size
-# GR11 - displacement of 2nd SDRAM addr reg from GR14
-# GR12 - displacement of 3rd SDRAM addr reg from GR14
-# GR13 - displacement of 4th SDRAM addr reg from GR14
-# GR14 - address of 1st SDRAM addr reg
-# GR15 - amount to shift address by to match SDRAM addr reg
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-# CC0 - T if DBR0 is present
-# CC1 - T if DBR1 is present
-# CC2 - T if DBR2 is present (not FR401/FR401A)
-# CC3 - T if DBR3 is present (not FR401/FR401A)
-#
-###############################################################################
- .globl __head_fr401_describe_sdram
-__head_fr401_describe_sdram:
- sethi.p %hi(__400_DBR0),gr14
- setlo %lo(__400_DBR0),gr14
- setlos.p #__400_DBR1-__400_DBR0,gr11
- setlos #__400_DBR2-__400_DBR0,gr12
- setlos.p #__400_DBR3-__400_DBR0,gr13
- setlos #32,gr5 ; cacheline size
- setlos.p #0,gr15 ; amount to shift addr reg by
-
- # specify which DBR regs are present
- setlos #0x00ff,gr4
- movgs gr4,cccr
- movsg psr,gr3 ; check for FR401/FR401A
- srli gr3,#25,gr3
- subicc gr3,#0x20>>1,gr0,icc0
- bnelr icc0,#1
- setlos #0x000f,gr4
- movgs gr4,cccr
- bralr
-
-###############################################################################
-#
-# rearrange the bus controller registers
-#
-# ENTRY: EXIT:
-# GR26 &__head_reference [saved]
-# GR30 LED address revised LED address
-#
-###############################################################################
- .globl __head_fr401_set_busctl
-__head_fr401_set_busctl:
- sethi.p %hi(__400_LGCR),gr4
- setlo %lo(__400_LGCR),gr4
- sethi.p %hi(__400_LSBR),gr10
- setlo %lo(__400_LSBR),gr10
- sethi.p %hi(__400_LCR),gr11
- setlo %lo(__400_LCR),gr11
-
- # set the bus controller
- ldi @(gr4,#0),gr5
- ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled
- sti gr5,@(gr4,#0)
-
- sethi.p %hi(__region_CS1),gr4
- setlo %lo(__region_CS1),gr4
- sethi.p %hi(__region_CS1_M),gr5
- setlo %lo(__region_CS1_M),gr5
- sethi.p %hi(__region_CS1_C),gr6
- setlo %lo(__region_CS1_C),gr6
- sti gr4,@(gr10,#1*0x08)
- sti gr5,@(gr10,#1*0x08+0x100)
- sti gr6,@(gr11,#1*0x08)
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- sethi.p %hi(__region_CS2_M),gr5
- setlo %lo(__region_CS2_M),gr5
- sethi.p %hi(__region_CS2_C),gr6
- setlo %lo(__region_CS2_C),gr6
- sti gr4,@(gr10,#2*0x08)
- sti gr5,@(gr10,#2*0x08+0x100)
- sti gr6,@(gr11,#2*0x08)
- sethi.p %hi(__region_CS3),gr4
- setlo %lo(__region_CS3),gr4
- sethi.p %hi(__region_CS3_M),gr5
- setlo %lo(__region_CS3_M),gr5
- sethi.p %hi(__region_CS3_C),gr6
- setlo %lo(__region_CS3_C),gr6
- sti gr4,@(gr10,#3*0x08)
- sti gr5,@(gr10,#3*0x08+0x100)
- sti gr6,@(gr11,#3*0x08)
- sethi.p %hi(__region_CS4),gr4
- setlo %lo(__region_CS4),gr4
- sethi.p %hi(__region_CS4_M),gr5
- setlo %lo(__region_CS4_M),gr5
- sethi.p %hi(__region_CS4_C),gr6
- setlo %lo(__region_CS4_C),gr6
- sti gr4,@(gr10,#4*0x08)
- sti gr5,@(gr10,#4*0x08+0x100)
- sti gr6,@(gr11,#4*0x08)
- sethi.p %hi(__region_CS5),gr4
- setlo %lo(__region_CS5),gr4
- sethi.p %hi(__region_CS5_M),gr5
- setlo %lo(__region_CS5_M),gr5
- sethi.p %hi(__region_CS5_C),gr6
- setlo %lo(__region_CS5_C),gr6
- sti gr4,@(gr10,#5*0x08)
- sti gr5,@(gr10,#5*0x08+0x100)
- sti gr6,@(gr11,#5*0x08)
- sethi.p %hi(__region_CS6),gr4
- setlo %lo(__region_CS6),gr4
- sethi.p %hi(__region_CS6_M),gr5
- setlo %lo(__region_CS6_M),gr5
- sethi.p %hi(__region_CS6_C),gr6
- setlo %lo(__region_CS6_C),gr6
- sti gr4,@(gr10,#6*0x08)
- sti gr5,@(gr10,#6*0x08+0x100)
- sti gr6,@(gr11,#6*0x08)
- sethi.p %hi(__region_CS7),gr4
- setlo %lo(__region_CS7),gr4
- sethi.p %hi(__region_CS7_M),gr5
- setlo %lo(__region_CS7_M),gr5
- sethi.p %hi(__region_CS7_C),gr6
- setlo %lo(__region_CS7_C),gr6
- sti gr4,@(gr10,#7*0x08)
- sti gr5,@(gr10,#7*0x08+0x100)
- sti gr6,@(gr11,#7*0x08)
- membar
- bar
-
- # adjust LED bank address
- sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
- setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
- bralr
-
-###############################################################################
-#
-# determine the total SDRAM size
-#
-# ENTRY: EXIT:
-# GR25 - SDRAM size
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr401_survey_sdram
-__head_fr401_survey_sdram:
- sethi.p %hi(__400_DAM0),gr11
- setlo %lo(__400_DAM0),gr11
- sethi.p %hi(__400_DBR0),gr12
- setlo %lo(__400_DBR0),gr12
-
- sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
- setlo %lo(0xfe000000),gr17
- setlos #0,gr25
-
- ldi @(gr12,#0x00),gr4 ; DAR0
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS0
- ldi @(gr11,#0x00),gr6 ; DAM0: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS0:
-
- ldi @(gr12,#0x08),gr4 ; DAR1
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS1
- ldi @(gr11,#0x08),gr6 ; DAM1: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS1:
-
- # FR401/FR401A does not have DCS2/3
- movsg psr,gr3
- srli gr3,#25,gr3
- subicc gr3,#0x20>>1,gr0,icc0
- beq icc0,#0,__head_no_DCS3
-
- ldi @(gr12,#0x10),gr4 ; DAR2
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS2
- ldi @(gr11,#0x10),gr6 ; DAM2: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS2:
-
- ldi @(gr12,#0x18),gr4 ; DAR3
- subcc gr4,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS3
- ldi @(gr11,#0x18),gr6 ; DAM3: bits 31:20 match addr 31:20
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS3:
- bralr
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size [saved]
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr401_set_protection
-__head_fr401_set_protection:
- movsg lr,gr27
-
- # set the I/O region protection registers for FR401/3/5
- sethi.p %hi(__region_IO),gr5
- setlo %lo(__region_IO),gr5
- ori gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
- movgs gr0,iampr7
- movgs gr5,dampr7 ; General I/O tile
-
- # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
- # - start with the highest numbered registers
- sethi.p %hi(__kernel_image_end),gr8
- setlo %lo(__kernel_image_end),gr8
- sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap
- setlo %lo(32768),gr4
- add gr8,gr4,gr8
- sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB
- setlo %lo(1024*2048-1),gr4
- add.p gr8,gr4,gr8
- not gr4,gr4
- and gr8,gr4,gr8
-
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9
- add gr9,gr25,gr9
-
- # GR8 = base of uncovered RAM
- # GR9 = top of uncovered RAM
-
-#ifdef CONFIG_MB93093_PDK
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- ori gr4,#xAMPRx_SS_1Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr4
- movgs gr4,dampr6
- movgs gr0,iampr6
-#else
- call __head_split_region
- movgs gr4,iampr6
- movgs gr5,dampr6
-#endif
- call __head_split_region
- movgs gr4,iampr5
- movgs gr5,dampr5
- call __head_split_region
- movgs gr4,iampr4
- movgs gr5,dampr4
- call __head_split_region
- movgs gr4,iampr3
- movgs gr5,dampr3
- call __head_split_region
- movgs gr4,iampr2
- movgs gr5,dampr2
- call __head_split_region
- movgs gr4,iampr1
- movgs gr5,dampr1
-
- # cover kernel core image with kernel-only segment
- sethi.p %hi(__page_offset),gr8
- setlo %lo(__page_offset),gr8
- call __head_split_region
-
-#ifdef CONFIG_PROTECT_KERNEL
- ori.p gr4,#xAMPRx_S_KERNEL,gr4
- ori gr5,#xAMPRx_S_KERNEL,gr5
-#endif
-
- movgs gr4,iampr0
- movgs gr5,dampr0
- jmpl @(gr27,gr0)
diff --git a/arch/frv/kernel/head-uc-fr451.S b/arch/frv/kernel/head-uc-fr451.S
deleted file mode 100644
index b2a76c4a1786..000000000000
--- a/arch/frv/kernel/head-uc-fr451.S
+++ /dev/null
@@ -1,174 +0,0 @@
-/* head-uc-fr451.S: FR451 uc-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __400_DBR0 0xfe000e00
-#define __400_DBR1 0xfe000e08
-#define __400_DBR2 0xfe000e10
-#define __400_DBR3 0xfe000e18
-#define __400_DAM0 0xfe000f00
-#define __400_DAM1 0xfe000f08
-#define __400_DAM2 0xfe000f10
-#define __400_DAM3 0xfe000f18
-#define __400_LGCR 0xfe000010
-#define __400_LCR 0xfe000100
-#define __400_LSBR 0xfe000c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size [saved]
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr451_set_protection
-__head_fr451_set_protection:
- movsg lr,gr27
-
- movgs gr0,dampr10
- movgs gr0,damlr10
- movgs gr0,dampr9
- movgs gr0,damlr9
- movgs gr0,dampr8
- movgs gr0,damlr8
-
- # set the I/O region protection registers for FR401/3/5
- sethi.p %hi(__region_IO),gr5
- setlo %lo(__region_IO),gr5
- sethi.p %hi(0x1fffffff),gr7
- setlo %lo(0x1fffffff),gr7
- ori gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
- movgs gr5,dampr11 ; General I/O tile
- movgs gr7,damlr11
-
- # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
- # - start with the highest numbered registers
- sethi.p %hi(__kernel_image_end),gr8
- setlo %lo(__kernel_image_end),gr8
- sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap
- setlo %lo(32768),gr4
- add gr8,gr4,gr8
- sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB
- setlo %lo(1024*2048-1),gr4
- add.p gr8,gr4,gr8
- not gr4,gr4
- and gr8,gr4,gr8
-
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9
- add gr9,gr25,gr9
-
- sethi.p %hi(0xffffc000),gr11
- setlo %lo(0xffffc000),gr11
-
- # GR8 = base of uncovered RAM
- # GR9 = top of uncovered RAM
- # GR11 = xAMLR mask
- LEDS 0x3317
- call __head_split_region
- movgs gr4,iampr7
- movgs gr6,iamlr7
- movgs gr5,dampr7
- movgs gr7,damlr7
-
- LEDS 0x3316
- call __head_split_region
- movgs gr4,iampr6
- movgs gr6,iamlr6
- movgs gr5,dampr6
- movgs gr7,damlr6
-
- LEDS 0x3315
- call __head_split_region
- movgs gr4,iampr5
- movgs gr6,iamlr5
- movgs gr5,dampr5
- movgs gr7,damlr5
-
- LEDS 0x3314
- call __head_split_region
- movgs gr4,iampr4
- movgs gr6,iamlr4
- movgs gr5,dampr4
- movgs gr7,damlr4
-
- LEDS 0x3313
- call __head_split_region
- movgs gr4,iampr3
- movgs gr6,iamlr3
- movgs gr5,dampr3
- movgs gr7,damlr3
-
- LEDS 0x3312
- call __head_split_region
- movgs gr4,iampr2
- movgs gr6,iamlr2
- movgs gr5,dampr2
- movgs gr7,damlr2
-
- LEDS 0x3311
- call __head_split_region
- movgs gr4,iampr1
- movgs gr6,iamlr1
- movgs gr5,dampr1
- movgs gr7,damlr1
-
- # cover kernel core image with kernel-only segment
- LEDS 0x3310
- sethi.p %hi(__page_offset),gr8
- setlo %lo(__page_offset),gr8
- call __head_split_region
-
-#ifdef CONFIG_PROTECT_KERNEL
- ori.p gr4,#xAMPRx_S_KERNEL,gr4
- ori gr5,#xAMPRx_S_KERNEL,gr5
-#endif
-
- movgs gr4,iampr0
- movgs gr6,iamlr0
- movgs gr5,dampr0
- movgs gr7,damlr0
-
- # start in TLB context 0 with no page tables
- movgs gr0,cxnr
- movgs gr0,ttbr
-
- # the FR451 also has an extra trap base register
- movsg tbr,gr4
- movgs gr4,btbr
-
- # turn on the timers as appropriate
- movgs gr0,timerh
- movgs gr0,timerl
- movgs gr0,timerd
- movsg hsr0,gr4
- sethi.p %hi(HSR0_ETMI),gr5
- setlo %lo(HSR0_ETMI),gr5
- or gr4,gr5,gr4
- movgs gr4,hsr0
-
- LEDS 0x3300
- jmpl @(gr27,gr0)
diff --git a/arch/frv/kernel/head-uc-fr555.S b/arch/frv/kernel/head-uc-fr555.S
deleted file mode 100644
index 5497aaf34f77..000000000000
--- a/arch/frv/kernel/head-uc-fr555.S
+++ /dev/null
@@ -1,347 +0,0 @@
-/* head-uc-fr555.S: FR555 uc-linux specific bits of initialisation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include "head.inc"
-
-
-#define __551_DARS0 0xfeff0100
-#define __551_DARS1 0xfeff0104
-#define __551_DARS2 0xfeff0108
-#define __551_DARS3 0xfeff010c
-#define __551_DAMK0 0xfeff0110
-#define __551_DAMK1 0xfeff0114
-#define __551_DAMK2 0xfeff0118
-#define __551_DAMK3 0xfeff011c
-#define __551_LCR 0xfeff1100
-#define __551_LSBR 0xfeff1c00
-
- __INIT
- .balign 4
-
-###############################################################################
-#
-# describe the position and layout of the SDRAM controller registers
-#
-# ENTRY: EXIT:
-# GR5 - cacheline size
-# GR11 - displacement of 2nd SDRAM addr reg from GR14
-# GR12 - displacement of 3rd SDRAM addr reg from GR14
-# GR13 - displacement of 4th SDRAM addr reg from GR14
-# GR14 - address of 1st SDRAM addr reg
-# GR15 - amount to shift address by to match SDRAM addr reg
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-# CC0 - T if DARS0 is present
-# CC1 - T if DARS1 is present
-# CC2 - T if DARS2 is present
-# CC3 - T if DARS3 is present
-#
-###############################################################################
- .globl __head_fr555_describe_sdram
-__head_fr555_describe_sdram:
- sethi.p %hi(__551_DARS0),gr14
- setlo %lo(__551_DARS0),gr14
- setlos.p #__551_DARS1-__551_DARS0,gr11
- setlos #__551_DARS2-__551_DARS0,gr12
- setlos.p #__551_DARS3-__551_DARS0,gr13
- setlos #64,gr5 ; cacheline size
- setlos #20,gr15 ; amount to shift addr by
- setlos #0x00ff,gr4
- movgs gr4,cccr ; extant DARS/DAMK regs
- bralr
-
-###############################################################################
-#
-# rearrange the bus controller registers
-#
-# ENTRY: EXIT:
-# GR26 &__head_reference [saved]
-# GR30 LED address revised LED address
-#
-###############################################################################
- .globl __head_fr555_set_busctl
-__head_fr555_set_busctl:
- LEDS 0x100f
- sethi.p %hi(__551_LSBR),gr10
- setlo %lo(__551_LSBR),gr10
- sethi.p %hi(__551_LCR),gr11
- setlo %lo(__551_LCR),gr11
-
- # set the bus controller
- sethi.p %hi(__region_CS1),gr4
- setlo %lo(__region_CS1),gr4
- sethi.p %hi(__region_CS1_M),gr5
- setlo %lo(__region_CS1_M),gr5
- sethi.p %hi(__region_CS1_C),gr6
- setlo %lo(__region_CS1_C),gr6
- sti gr4,@(gr10,#1*0x08)
- sti gr5,@(gr10,#1*0x08+0x100)
- sti gr6,@(gr11,#1*0x08)
- sethi.p %hi(__region_CS2),gr4
- setlo %lo(__region_CS2),gr4
- sethi.p %hi(__region_CS2_M),gr5
- setlo %lo(__region_CS2_M),gr5
- sethi.p %hi(__region_CS2_C),gr6
- setlo %lo(__region_CS2_C),gr6
- sti gr4,@(gr10,#2*0x08)
- sti gr5,@(gr10,#2*0x08+0x100)
- sti gr6,@(gr11,#2*0x08)
- sethi.p %hi(__region_CS3),gr4
- setlo %lo(__region_CS3),gr4
- sethi.p %hi(__region_CS3_M),gr5
- setlo %lo(__region_CS3_M),gr5
- sethi.p %hi(__region_CS3_C),gr6
- setlo %lo(__region_CS3_C),gr6
- sti gr4,@(gr10,#3*0x08)
- sti gr5,@(gr10,#3*0x08+0x100)
- sti gr6,@(gr11,#3*0x08)
- sethi.p %hi(__region_CS4),gr4
- setlo %lo(__region_CS4),gr4
- sethi.p %hi(__region_CS4_M),gr5
- setlo %lo(__region_CS4_M),gr5
- sethi.p %hi(__region_CS4_C),gr6
- setlo %lo(__region_CS4_C),gr6
- sti gr4,@(gr10,#4*0x08)
- sti gr5,@(gr10,#4*0x08+0x100)
- sti gr6,@(gr11,#4*0x08)
- sethi.p %hi(__region_CS5),gr4
- setlo %lo(__region_CS5),gr4
- sethi.p %hi(__region_CS5_M),gr5
- setlo %lo(__region_CS5_M),gr5
- sethi.p %hi(__region_CS5_C),gr6
- setlo %lo(__region_CS5_C),gr6
- sti gr4,@(gr10,#5*0x08)
- sti gr5,@(gr10,#5*0x08+0x100)
- sti gr6,@(gr11,#5*0x08)
- sethi.p %hi(__region_CS6),gr4
- setlo %lo(__region_CS6),gr4
- sethi.p %hi(__region_CS6_M),gr5
- setlo %lo(__region_CS6_M),gr5
- sethi.p %hi(__region_CS6_C),gr6
- setlo %lo(__region_CS6_C),gr6
- sti gr4,@(gr10,#6*0x08)
- sti gr5,@(gr10,#6*0x08+0x100)
- sti gr6,@(gr11,#6*0x08)
- sethi.p %hi(__region_CS7),gr4
- setlo %lo(__region_CS7),gr4
- sethi.p %hi(__region_CS7_M),gr5
- setlo %lo(__region_CS7_M),gr5
- sethi.p %hi(__region_CS7_C),gr6
- setlo %lo(__region_CS7_C),gr6
- sti gr4,@(gr10,#7*0x08)
- sti gr5,@(gr10,#7*0x08+0x100)
- sti gr6,@(gr11,#7*0x08)
- membar
- bar
-
- # adjust LED bank address
-#ifdef CONFIG_MB93091_VDK
- sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
- setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
-#endif
- bralr
-
-###############################################################################
-#
-# determine the total SDRAM size
-#
-# ENTRY: EXIT:
-# GR25 - SDRAM size
-# GR26 &__head_reference [saved]
-# GR30 LED address [saved]
-#
-###############################################################################
- .globl __head_fr555_survey_sdram
-__head_fr555_survey_sdram:
- sethi.p %hi(__551_DAMK0),gr11
- setlo %lo(__551_DAMK0),gr11
- sethi.p %hi(__551_DARS0),gr12
- setlo %lo(__551_DARS0),gr12
-
- sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
- setlo %lo(0xfff),gr17
- setlos #0,gr25
-
- ldi @(gr11,#0x00),gr6 ; DAMK0: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS0
- ldi @(gr12,#0x00),gr4 ; DARS0
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS0:
-
- ldi @(gr11,#0x04),gr6 ; DAMK1: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS1
- ldi @(gr12,#0x04),gr4 ; DARS1
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS1:
-
- ldi @(gr11,#0x8),gr6 ; DAMK2: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS2
- ldi @(gr12,#0x8),gr4 ; DARS2
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS2:
-
- ldi @(gr11,#0xc),gr6 ; DAMK3: bits 11:0 match addr 11:0
- subcc gr6,gr17,gr0,icc0
- beq icc0,#0,__head_no_DCS3
- ldi @(gr12,#0xc),gr4 ; DARS3
- add gr25,gr6,gr25
- addi gr25,#1,gr25
-__head_no_DCS3:
-
- slli gr25,#20,gr25 ; shift [11:0] -> [31:20]
- bralr
-
-###############################################################################
-#
-# set the protection map with the I/DAMPR registers
-#
-# ENTRY: EXIT:
-# GR25 SDRAM size saved
-# GR30 LED address saved
-#
-###############################################################################
- .globl __head_fr555_set_protection
-__head_fr555_set_protection:
- movsg lr,gr27
-
- sethi.p %hi(0xfff00000),gr11
- setlo %lo(0xfff00000),gr11
-
- # set the I/O region protection registers for FR555
- sethi.p %hi(__region_IO),gr7
- setlo %lo(__region_IO),gr7
- ori gr7,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
- movgs gr0,iampr15
- movgs gr0,iamlr15
- movgs gr5,dampr15
- movgs gr7,damlr15
-
- # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
- # - start with the highest numbered registers
- sethi.p %hi(__kernel_image_end),gr8
- setlo %lo(__kernel_image_end),gr8
- sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap
- setlo %lo(32768),gr4
- add gr8,gr4,gr8
- sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB
- setlo %lo(1024*2048-1),gr4
- add.p gr8,gr4,gr8
- not gr4,gr4
- and gr8,gr4,gr8
-
- sethi.p %hi(__page_offset),gr9
- setlo %lo(__page_offset),gr9
- add gr9,gr25,gr9
-
- # GR8 = base of uncovered RAM
- # GR9 = top of uncovered RAM
- # GR11 - mask for DAMLR/IAMLR regs
- #
- call __head_split_region
- movgs gr4,iampr14
- movgs gr6,iamlr14
- movgs gr5,dampr14
- movgs gr7,damlr14
- call __head_split_region
- movgs gr4,iampr13
- movgs gr6,iamlr13
- movgs gr5,dampr13
- movgs gr7,damlr13
- call __head_split_region
- movgs gr4,iampr12
- movgs gr6,iamlr12
- movgs gr5,dampr12
- movgs gr7,damlr12
- call __head_split_region
- movgs gr4,iampr11
- movgs gr6,iamlr11
- movgs gr5,dampr11
- movgs gr7,damlr11
- call __head_split_region
- movgs gr4,iampr10
- movgs gr6,iamlr10
- movgs gr5,dampr10
- movgs gr7,damlr10
- call __head_split_region
- movgs gr4,iampr9
- movgs gr6,iamlr9
- movgs gr5,dampr9
- movgs gr7,damlr9
- call __head_split_region
- movgs gr4,iampr8
- movgs gr6,iamlr8
- movgs gr5,dampr8
- movgs gr7,damlr8
-
- call __head_split_region
- movgs gr4,iampr7
- movgs gr6,iamlr7
- movgs gr5,dampr7
- movgs gr7,damlr7
- call __head_split_region
- movgs gr4,iampr6
- movgs gr6,iamlr6
- movgs gr5,dampr6
- movgs gr7,damlr6
- call __head_split_region
- movgs gr4,iampr5
- movgs gr6,iamlr5
- movgs gr5,dampr5
- movgs gr7,damlr5
- call __head_split_region
- movgs gr4,iampr4
- movgs gr6,iamlr4
- movgs gr5,dampr4
- movgs gr7,damlr4
- call __head_split_region
- movgs gr4,iampr3
- movgs gr6,iamlr3
- movgs gr5,dampr3
- movgs gr7,damlr3
- call __head_split_region
- movgs gr4,iampr2
- movgs gr6,iamlr2
- movgs gr5,dampr2
- movgs gr7,damlr2
- call __head_split_region
- movgs gr4,iampr1
- movgs gr6,iamlr1
- movgs gr5,dampr1
- movgs gr7,damlr1
-
- # cover kernel core image with kernel-only segment
- sethi.p %hi(__page_offset),gr8
- setlo %lo(__page_offset),gr8
- call __head_split_region
-
-#ifdef CONFIG_PROTECT_KERNEL
- ori.p gr4,#xAMPRx_S_KERNEL,gr4
- ori gr5,#xAMPRx_S_KERNEL,gr5
-#endif
-
- movgs gr4,iampr0
- movgs gr6,iamlr0
- movgs gr5,dampr0
- movgs gr7,damlr0
- jmpl @(gr27,gr0)
diff --git a/arch/frv/kernel/head.S b/arch/frv/kernel/head.S
deleted file mode 100644
index a7d0bea9c036..000000000000
--- a/arch/frv/kernel/head.S
+++ /dev/null
@@ -1,638 +0,0 @@
-/* head.S: kernel entry point for FR-V kernel
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-#include <asm/spr-regs.h>
-#include <asm/mb86943a.h>
-#include <asm/cache.h>
-#include "head.inc"
-
-###############################################################################
-#
-# void _boot(unsigned long magic, char *command_line) __attribute__((noreturn))
-#
-# - if magic is 0xdead1eaf, then command_line is assumed to point to the kernel
-# command line string
-#
-###############################################################################
- __HEAD
- .balign 4
-
- .globl _boot, __head_reference
- .type _boot,@function
-_boot:
-__head_reference:
- sethi.p %hi(LED_ADDR),gr30
- setlo %lo(LED_ADDR),gr30
-
- LEDS 0x0000
-
- # calculate reference address for PC-relative stuff
- call 0f
-0: movsg lr,gr26
- addi gr26,#__head_reference-0b,gr26
-
- # invalidate and disable both of the caches and turn off the memory access checking
- dcef @(gr0,gr0),1
- bar
-
- sethi.p %hi(~(HSR0_ICE|HSR0_DCE|HSR0_CBM|HSR0_EIMMU|HSR0_EDMMU)),gr4
- setlo %lo(~(HSR0_ICE|HSR0_DCE|HSR0_CBM|HSR0_EIMMU|HSR0_EDMMU)),gr4
- movsg hsr0,gr5
- and gr4,gr5,gr5
- movgs gr5,hsr0
- movsg hsr0,gr5
-
- LEDS 0x0001
-
- icei @(gr0,gr0),1
- dcei @(gr0,gr0),1
- bar
-
- # turn the instruction cache back on
- sethi.p %hi(HSR0_ICE),gr4
- setlo %lo(HSR0_ICE),gr4
- movsg hsr0,gr5
- or gr4,gr5,gr5
- movgs gr5,hsr0
- movsg hsr0,gr5
-
- bar
-
- LEDS 0x0002
-
- # retrieve the parameters (including command line) before we overwrite them
- sethi.p %hi(0xdead1eaf),gr7
- setlo %lo(0xdead1eaf),gr7
- subcc gr7,gr8,gr0,icc0
- bne icc0,#0,__head_no_parameters
-
- sethi.p %hi(redboot_command_line-1),gr6
- setlo %lo(redboot_command_line-1),gr6
- sethi.p %hi(__head_reference),gr4
- setlo %lo(__head_reference),gr4
- sub gr6,gr4,gr6
- add.p gr6,gr26,gr6
- subi gr9,#1,gr9
- setlos.p #511,gr4
- setlos #1,gr5
-
-__head_copy_cmdline:
- ldubu.p @(gr9,gr5),gr16
- subicc gr4,#1,gr4,icc0
- stbu.p gr16,@(gr6,gr5)
- subicc gr16,#0,gr0,icc1
- bls icc0,#0,__head_end_cmdline
- bne icc1,#1,__head_copy_cmdline
-__head_end_cmdline:
- stbu gr0,@(gr6,gr5)
-__head_no_parameters:
-
-###############################################################################
-#
-# we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
-# - note that we're going to have to run entirely out of the icache whilst
-# fiddling with the SDRAM controller registers
-#
-###############################################################################
-#ifdef CONFIG_MMU
- call __head_fr451_describe_sdram
-
-#else
- movsg psr,gr5
- srli gr5,#28,gr5
- subicc gr5,#3,gr0,icc0
- beq icc0,#0,__head_fr551_sdram
-
- call __head_fr401_describe_sdram
- bra __head_do_sdram
-
-__head_fr551_sdram:
- call __head_fr555_describe_sdram
- LEDS 0x000d
-
-__head_do_sdram:
-#endif
-
- # preload the registers with invalid values in case any DBR/DARS are marked not present
- sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
- setlo %lo(0xfe000000),gr17
- or.p gr17,gr0,gr20
- or gr17,gr0,gr21
- or.p gr17,gr0,gr22
- or gr17,gr0,gr23
-
- # consult the SDRAM controller CS address registers
- cld @(gr14,gr0 ),gr20, cc0,#1 ; DBR0 / DARS0
- cld @(gr14,gr11),gr21, cc1,#1 ; DBR1 / DARS1
- cld @(gr14,gr12),gr22, cc2,#1 ; DBR2 / DARS2
- cld.p @(gr14,gr13),gr23, cc3,#1 ; DBR3 / DARS3
-
- sll gr20,gr15,gr20 ; shift values up for FR551
- sll gr21,gr15,gr21
- sll gr22,gr15,gr22
- sll gr23,gr15,gr23
-
- LEDS 0x0003
-
- # assume the lowest valid CS line to be the SDRAM base and get its address
- subcc gr20,gr17,gr0,icc0
- subcc.p gr21,gr17,gr0,icc1
- subcc gr22,gr17,gr0,icc2
- subcc.p gr23,gr17,gr0,icc3
- ckne icc0,cc4 ; T if DBR0 != 0xfe000000
- ckne icc1,cc5
- ckne icc2,cc6
- ckne icc3,cc7
- cor gr23,gr0,gr24, cc7,#1 ; GR24 = SDRAM base
- cor gr22,gr0,gr24, cc6,#1
- cor gr21,gr0,gr24, cc5,#1
- cor gr20,gr0,gr24, cc4,#1
-
- # calculate the displacement required to get the SDRAM into the right place in memory
- sethi.p %hi(__sdram_base),gr16
- setlo %lo(__sdram_base),gr16
- sub gr16,gr24,gr16 ; delta = __sdram_base - DBRx
-
- # calculate the new values to go in the controller regs
- cadd.p gr20,gr16,gr20, cc4,#1 ; DCS#0 (new) = DCS#0 (old) + delta
- cadd gr21,gr16,gr21, cc5,#1
- cadd.p gr22,gr16,gr22, cc6,#1
- cadd gr23,gr16,gr23, cc7,#1
-
- srl gr20,gr15,gr20 ; shift values down for FR551
- srl gr21,gr15,gr21
- srl gr22,gr15,gr22
- srl gr23,gr15,gr23
-
- # work out the address at which the reg updater resides and lock it into icache
- # also work out the address the updater will jump to when finished
- sethi.p %hi(__head_move_sdram-__head_reference),gr18
- setlo %lo(__head_move_sdram-__head_reference),gr18
- sethi.p %hi(__head_sdram_moved-__head_reference),gr19
- setlo %lo(__head_sdram_moved-__head_reference),gr19
- add.p gr18,gr26,gr18
- add gr19,gr26,gr19
- add.p gr19,gr16,gr19 ; moved = addr + (__sdram_base - DBRx)
- add gr18,gr5,gr4 ; two cachelines probably required
-
- icpl gr18,gr0,#1 ; load and lock the cachelines
- icpl gr4,gr0,#1
- LEDS 0x0004
- membar
- bar
- jmpl @(gr18,gr0)
-
- .balign L1_CACHE_BYTES
-__head_move_sdram:
- cst gr20,@(gr14,gr0 ), cc4,#1
- cst gr21,@(gr14,gr11), cc5,#1
- cst gr22,@(gr14,gr12), cc6,#1
- cst gr23,@(gr14,gr13), cc7,#1
- cld @(gr14,gr0 ),gr20, cc4,#1
- cld @(gr14,gr11),gr21, cc5,#1
- cld @(gr14,gr12),gr22, cc4,#1
- cld @(gr14,gr13),gr23, cc7,#1
- bar
- membar
- jmpl @(gr19,gr0)
-
- .balign L1_CACHE_BYTES
-__head_sdram_moved:
- icul gr18
- add gr18,gr5,gr4
- icul gr4
- icei @(gr0,gr0),1
- dcei @(gr0,gr0),1
-
- LEDS 0x0005
-
- # recalculate reference address
- call 0f
-0: movsg lr,gr26
- addi gr26,#__head_reference-0b,gr26
-
-
-###############################################################################
-#
-# move the kernel image down to the bottom of the SDRAM
-#
-###############################################################################
- sethi.p %hi(__kernel_image_size_no_bss+15),gr4
- setlo %lo(__kernel_image_size_no_bss+15),gr4
- srli.p gr4,#4,gr4 ; count
- or gr26,gr26,gr16 ; source
-
- sethi.p %hi(__sdram_base),gr17 ; destination
- setlo %lo(__sdram_base),gr17
-
- setlos #8,gr5
- sub.p gr16,gr5,gr16 ; adjust src for LDDU
- sub gr17,gr5,gr17 ; adjust dst for LDDU
-
- sethi.p %hi(__head_move_kernel-__head_reference),gr18
- setlo %lo(__head_move_kernel-__head_reference),gr18
- sethi.p %hi(__head_kernel_moved-__head_reference+__sdram_base),gr19
- setlo %lo(__head_kernel_moved-__head_reference+__sdram_base),gr19
- add gr18,gr26,gr18
- icpl gr18,gr0,#1
- jmpl @(gr18,gr0)
-
- .balign 32
-__head_move_kernel:
- lddu @(gr16,gr5),gr10
- lddu @(gr16,gr5),gr12
- stdu.p gr10,@(gr17,gr5)
- subicc gr4,#1,gr4,icc0
- stdu.p gr12,@(gr17,gr5)
- bhi icc0,#0,__head_move_kernel
- jmpl @(gr19,gr0)
-
- .balign 32
-__head_kernel_moved:
- icul gr18
- icei @(gr0,gr0),1
- dcei @(gr0,gr0),1
-
- LEDS 0x0006
-
- # recalculate reference address
- call 0f
-0: movsg lr,gr26
- addi gr26,#__head_reference-0b,gr26
-
-
-###############################################################################
-#
-# rearrange the iomem map and set the protection registers
-#
-###############################################################################
-
-#ifdef CONFIG_MMU
- LEDS 0x3301
- call __head_fr451_set_busctl
- LEDS 0x3303
- call __head_fr451_survey_sdram
- LEDS 0x3305
- call __head_fr451_set_protection
-
-#else
- movsg psr,gr5
- srli gr5,#PSR_IMPLE_SHIFT,gr5
- subicc gr5,#PSR_IMPLE_FR551,gr0,icc0
- beq icc0,#0,__head_fr555_memmap
- subicc gr5,#PSR_IMPLE_FR451,gr0,icc0
- beq icc0,#0,__head_fr451_memmap
-
- LEDS 0x3101
- call __head_fr401_set_busctl
- LEDS 0x3103
- call __head_fr401_survey_sdram
- LEDS 0x3105
- call __head_fr401_set_protection
- bra __head_done_memmap
-
-__head_fr451_memmap:
- LEDS 0x3301
- call __head_fr401_set_busctl
- LEDS 0x3303
- call __head_fr401_survey_sdram
- LEDS 0x3305
- call __head_fr451_set_protection
- bra __head_done_memmap
-
-__head_fr555_memmap:
- LEDS 0x3501
- call __head_fr555_set_busctl
- LEDS 0x3503
- call __head_fr555_survey_sdram
- LEDS 0x3505
- call __head_fr555_set_protection
-
-__head_done_memmap:
-#endif
- LEDS 0x0007
-
-###############################################################################
-#
-# turn the data cache and MMU on
-# - for the FR451 this'll mean that the window through which the kernel is
-# viewed will change
-#
-###############################################################################
-
-#ifdef CONFIG_MMU
-#define MMUMODE HSR0_EIMMU|HSR0_EDMMU|HSR0_EXMMU|HSR0_EDAT|HSR0_XEDAT
-#else
-#define MMUMODE HSR0_EIMMU|HSR0_EDMMU
-#endif
-
- movsg hsr0,gr5
-
- sethi.p %hi(MMUMODE),gr4
- setlo %lo(MMUMODE),gr4
- or gr4,gr5,gr5
-
-#if defined(CONFIG_FRV_DEFL_CACHE_WTHRU)
- sethi.p %hi(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
- setlo %lo(HSR0_DCE|HSR0_CBM_WRITE_THRU),gr4
-#elif defined(CONFIG_FRV_DEFL_CACHE_WBACK)
- sethi.p %hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
- setlo %lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
-#elif defined(CONFIG_FRV_DEFL_CACHE_WBEHIND)
- sethi.p %hi(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
- setlo %lo(HSR0_DCE|HSR0_CBM_COPY_BACK),gr4
-
- movsg psr,gr6
- srli gr6,#24,gr6
- cmpi gr6,#0x50,icc0 // FR451
- beq icc0,#0,0f
- cmpi gr6,#0x40,icc0 // FR405
- bne icc0,#0,1f
-0:
- # turn off write-allocate
- sethi.p %hi(HSR0_NWA),gr6
- setlo %lo(HSR0_NWA),gr6
- or gr4,gr6,gr4
-1:
-
-#else
-#error No default cache configuration set
-#endif
-
- or gr4,gr5,gr5
- movgs gr5,hsr0
- bar
-
- LEDS 0x0008
-
- sethi.p %hi(__head_mmu_enabled),gr19
- setlo %lo(__head_mmu_enabled),gr19
- jmpl @(gr19,gr0)
-
-__head_mmu_enabled:
- icei @(gr0,gr0),#1
- dcei @(gr0,gr0),#1
-
- LEDS 0x0009
-
-#ifdef CONFIG_MMU
- call __head_fr451_finalise_protection
-#endif
-
- LEDS 0x000a
-
-###############################################################################
-#
-# set up the runtime environment
-#
-###############################################################################
-
- # clear the BSS area
- sethi.p %hi(__bss_start),gr4
- setlo %lo(__bss_start),gr4
- sethi.p %hi(_end),gr5
- setlo %lo(_end),gr5
- or.p gr0,gr0,gr18
- or gr0,gr0,gr19
-
-0:
- stdi gr18,@(gr4,#0)
- stdi gr18,@(gr4,#8)
- stdi gr18,@(gr4,#16)
- stdi.p gr18,@(gr4,#24)
- addi gr4,#24,gr4
- subcc gr5,gr4,gr0,icc0
- bhi icc0,#2,0b
-
- LEDS 0x000b
-
- # save the SDRAM details
- sethi.p %hi(__sdram_old_base),gr4
- setlo %lo(__sdram_old_base),gr4
- st gr24,@(gr4,gr0)
-
- sethi.p %hi(__sdram_base),gr5
- setlo %lo(__sdram_base),gr5
- sethi.p %hi(memory_start),gr4
- setlo %lo(memory_start),gr4
- st gr5,@(gr4,gr0)
-
- add gr25,gr5,gr25
- sethi.p %hi(memory_end),gr4
- setlo %lo(memory_end),gr4
- st gr25,@(gr4,gr0)
-
- # point the TBR at the kernel trap table
- sethi.p %hi(__entry_kerneltrap_table),gr4
- setlo %lo(__entry_kerneltrap_table),gr4
- movgs gr4,tbr
-
- # set up the exception frame for init
- sethi.p %hi(__kernel_frame0_ptr),gr28
- setlo %lo(__kernel_frame0_ptr),gr28
- sethi.p %hi(_gp),gr16
- setlo %lo(_gp),gr16
- sethi.p %hi(__entry_usertrap_table),gr4
- setlo %lo(__entry_usertrap_table),gr4
-
- lddi @(gr28,#0),gr28 ; load __frame & current
- ldi.p @(gr29,#4),gr15 ; set current_thread
-
- or gr0,gr0,fp
- or gr28,gr0,sp
-
- sti.p gr4,@(gr28,REG_TBR)
- setlos #ISR_EDE|ISR_DTT_DIVBYZERO|ISR_EMAM_EXCEPTION,gr5
- movgs gr5,isr
-
- # turn on and off various CPU services
- movsg psr,gr22
- sethi.p %hi(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
- setlo %lo(#PSR_EM|PSR_EF|PSR_CM|PSR_NEM),gr4
- or gr22,gr4,gr22
- movgs gr22,psr
-
- andi gr22,#~(PSR_PIL|PSR_PS|PSR_S),gr22
- ori gr22,#PSR_ET,gr22
- sti gr22,@(gr28,REG_PSR)
-
-
-###############################################################################
-#
-# set up the registers and jump into the kernel
-#
-###############################################################################
-
- LEDS 0x000c
-
- sethi.p #0xe5e5,gr3
- setlo #0xe5e5,gr3
- or.p gr3,gr0,gr4
- or gr3,gr0,gr5
- or.p gr3,gr0,gr6
- or gr3,gr0,gr7
- or.p gr3,gr0,gr8
- or gr3,gr0,gr9
- or.p gr3,gr0,gr10
- or gr3,gr0,gr11
- or.p gr3,gr0,gr12
- or gr3,gr0,gr13
- or.p gr3,gr0,gr14
- or gr3,gr0,gr17
- or.p gr3,gr0,gr18
- or gr3,gr0,gr19
- or.p gr3,gr0,gr20
- or gr3,gr0,gr21
- or.p gr3,gr0,gr23
- or gr3,gr0,gr24
- or.p gr3,gr0,gr25
- or gr3,gr0,gr26
- or.p gr3,gr0,gr27
-# or gr3,gr0,gr30
- or gr3,gr0,gr31
- movgs gr0,lr
- movgs gr0,lcr
- movgs gr0,ccr
- movgs gr0,cccr
-
- # initialise the virtual interrupt handling
- subcc gr0,gr0,gr0,icc2 /* set Z, clear C */
-
-#ifdef CONFIG_MMU
- movgs gr3,scr2
- movgs gr3,scr3
-#endif
-
- LEDS 0x0fff
-
- # invoke the debugging stub if present
- # - arch/frv/kernel/debug-stub.c will shift control directly to init/main.c
- # (it will not return here)
- break
- .globl __debug_stub_init_break
-__debug_stub_init_break:
-
- # however, if you need to use an ICE, and don't care about using any userspace
- # debugging tools (such as the ptrace syscall), you can just step over the break
- # above and get to the kernel this way
- # look at arch/frv/kernel/debug-stub.c: debug_stub_init() to see what you've missed
- call start_kernel
-
- .globl __head_end
-__head_end:
- .size _boot, .-_boot
-
- # provide a point for GDB to place a break
- .section .text..start,"ax"
- .globl _start
- .balign 4
-_start:
- call _boot
-
- .previous
-###############################################################################
-#
-# split a tile off of the region defined by GR8-GR9
-#
-# ENTRY: EXIT:
-# GR4 - IAMPR value representing tile
-# GR5 - DAMPR value representing tile
-# GR6 - IAMLR value representing tile
-# GR7 - DAMLR value representing tile
-# GR8 region base pointer [saved]
-# GR9 region top pointer updated to exclude new tile
-# GR11 xAMLR mask [saved]
-# GR25 SDRAM size [saved]
-# GR30 LED address [saved]
-#
-# - GR8 and GR9 should be rounded up/down to the nearest megabyte before calling
-#
-###############################################################################
- .globl __head_split_region
- .type __head_split_region,@function
-__head_split_region:
- subcc.p gr9,gr8,gr4,icc0
- setlos #31,gr5
- scan.p gr4,gr0,gr6
- beq icc0,#0,__head_region_empty
- sub.p gr5,gr6,gr6 ; bit number of highest set bit (1MB=>20)
- setlos #1,gr4
- sll.p gr4,gr6,gr4 ; size of region (1 << bitno)
- subi gr6,#17,gr6 ; 1MB => 0x03
- slli.p gr6,#4,gr6 ; 1MB => 0x30
- sub gr9,gr4,gr9 ; move uncovered top down
-
- or gr9,gr6,gr4
- ori gr4,#xAMPRx_S_USER|xAMPRx_C_CACHED|xAMPRx_V,gr4
- or.p gr4,gr0,gr5
-
- and gr4,gr11,gr6
- and.p gr5,gr11,gr7
- bralr
-
-__head_region_empty:
- or.p gr0,gr0,gr4
- or gr0,gr0,gr5
- or.p gr0,gr0,gr6
- or gr0,gr0,gr7
- bralr
- .size __head_split_region, .-__head_split_region
-
-###############################################################################
-#
-# write the 32-bit hex number in GR8 to ttyS0
-#
-###############################################################################
-#if 0
- .globl __head_write_to_ttyS0
- .type __head_write_to_ttyS0,@function
-__head_write_to_ttyS0:
- sethi.p %hi(0xfeff9c00),gr31
- setlo %lo(0xfeff9c00),gr31
- setlos #8,gr20
-
-0: ldubi @(gr31,#5*8),gr21
- andi gr21,#0x60,gr21
- subicc gr21,#0x60,gr21,icc0
- bne icc0,#0,0b
-
-1: srli gr8,#28,gr21
- slli gr8,#4,gr8
-
- addi gr21,#'0',gr21
- subicc gr21,#'9',gr0,icc0
- bls icc0,#2,2f
- addi gr21,#'A'-'0'-10,gr21
-2:
- stbi gr21,@(gr31,#0*8)
- subicc gr20,#1,gr20,icc0
- bhi icc0,#2,1b
-
- setlos #'\r',gr21
- stbi gr21,@(gr31,#0*8)
-
- setlos #'\n',gr21
- stbi gr21,@(gr31,#0*8)
-
-3: ldubi @(gr31,#5*8),gr21
- andi gr21,#0x60,gr21
- subicc gr21,#0x60,gr21,icc0
- bne icc0,#0,3b
- bralr
-
- .size __head_write_to_ttyS0, .-__head_write_to_ttyS0
-#endif
diff --git a/arch/frv/kernel/head.inc b/arch/frv/kernel/head.inc
deleted file mode 100644
index bff66628b99a..000000000000
--- a/arch/frv/kernel/head.inc
+++ /dev/null
@@ -1,50 +0,0 @@
-/* head.inc: head common definitions -*- asm -*-
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
-#if defined(CONFIG_MB93090_MB00)
-#define LED_ADDR (0x21200000+4)
-
-.macro LEDS val
- sethi.p %hi(0xFFC00030),gr3
- setlo %lo(0xFFC00030),gr3
- lduh @(gr3,gr0),gr3
- andicc gr3,#0x100,gr0,icc0
- bne icc0,0,999f
-
- setlos #~\val,gr3
- st gr3,@(gr30,gr0)
- membar
- dcf @(gr30,gr0)
- 999:
-.endm
-
-#elif defined(CONFIG_MB93093_PDK)
-#define LED_ADDR (0x20000023)
-
-.macro LEDS val
- setlos #\val,gr3
- stb gr3,@(gr30,gr0)
- membar
-.endm
-
-#else
-#define LED_ADDR 0
-
-.macro LEDS val
-.endm
-#endif
-
-#ifdef CONFIG_MMU
-__sdram_base = 0x00000000 /* base address to which SDRAM relocated */
-#else
-__sdram_base = __page_offset /* base address to which SDRAM relocated */
-#endif
diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c
deleted file mode 100644
index 091b2839be90..000000000000
--- a/arch/frv/kernel/irq-mb93091.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* irq-mb93091.c: MB93091 FPGA interrupt handling
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-
-#define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
-
-#define __get_IMR() ({ __reg16(0xffc00004); })
-#define __set_IMR(M) do { __reg16(0xffc00004) = (M); wmb(); } while(0)
-#define __get_IFR() ({ __reg16(0xffc0000c); })
-#define __clr_IFR(M) do { __reg16(0xffc0000c) = ~(M); wmb(); } while(0)
-
-
-/*
- * on-motherboard FPGA PIC operations
- */
-static void frv_fpga_mask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
-
- __set_IMR(imr);
-}
-
-static void frv_fpga_ack(struct irq_data *d)
-{
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_mask_ack(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
- __set_IMR(imr);
-
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_unmask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
-
- __set_IMR(imr);
-}
-
-static struct irq_chip frv_fpga_pic = {
- .name = "mb93091",
- .irq_ack = frv_fpga_ack,
- .irq_mask = frv_fpga_mask,
- .irq_mask_ack = frv_fpga_mask_ack,
- .irq_unmask = frv_fpga_unmask,
-};
-
-/*
- * FPGA PIC interrupt handler
- */
-static irqreturn_t fpga_interrupt(int irq, void *_mask)
-{
- uint16_t imr, mask = (unsigned long) _mask;
-
- imr = __get_IMR();
- mask = mask & ~imr & __get_IFR();
-
- /* poll all the triggered IRQs */
- while (mask) {
- int irq;
-
- asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
- irq = 31 - irq;
- mask &= ~(1 << irq);
-
- generic_handle_irq(IRQ_BASE_FPGA + irq);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * define an interrupt action for each FPGA PIC output
- * - use dev_id to indicate the FPGA PIC input to output mappings
- */
-static struct irqaction fpga_irq[4] = {
- [0] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.0",
- .dev_id = (void *) 0x0028UL,
- },
- [1] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.1",
- .dev_id = (void *) 0x0050UL,
- },
- [2] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.2",
- .dev_id = (void *) 0x1c00UL,
- },
- [3] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga.3",
- .dev_id = (void *) 0x6386UL,
- }
-};
-
-/*
- * initialise the motherboard FPGA's PIC
- */
-void __init fpga_init(void)
-{
- int irq;
-
- /* all PIC inputs are all set to be low-level driven, apart from the
- * NMI button (15) which is fixed at falling-edge
- */
- __set_IMR(0x7ffe);
- __clr_IFR(0x0000);
-
- for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
- irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
-
- irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
-
- /* the FPGA drives the first four external IRQ inputs on the CPU PIC */
- setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
- setup_irq(IRQ_CPU_EXTERNAL1, &fpga_irq[1]);
- setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[2]);
- setup_irq(IRQ_CPU_EXTERNAL3, &fpga_irq[3]);
-}
diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c
deleted file mode 100644
index 1f3015cf80f5..000000000000
--- a/arch/frv/kernel/irq-mb93093.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* irq-mb93093.c: MB93093 FPGA interrupt handling
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-
-#define __reg16(ADDR) (*(volatile unsigned short *)(__region_CS2 + (ADDR)))
-
-#define __get_IMR() ({ __reg16(0x0a); })
-#define __set_IMR(M) do { __reg16(0x0a) = (M); wmb(); } while(0)
-#define __get_IFR() ({ __reg16(0x02); })
-#define __clr_IFR(M) do { __reg16(0x02) = ~(M); wmb(); } while(0)
-
-/*
- * off-CPU FPGA PIC operations
- */
-static void frv_fpga_mask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
- __set_IMR(imr);
-}
-
-static void frv_fpga_ack(struct irq_data *d)
-{
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_mask_ack(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr |= 1 << (d->irq - IRQ_BASE_FPGA);
- __set_IMR(imr);
-
- __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
-}
-
-static void frv_fpga_unmask(struct irq_data *d)
-{
- uint16_t imr = __get_IMR();
-
- imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
-
- __set_IMR(imr);
-}
-
-static struct irq_chip frv_fpga_pic = {
- .name = "mb93093",
- .irq_ack = frv_fpga_ack,
- .irq_mask = frv_fpga_mask,
- .irq_mask_ack = frv_fpga_mask_ack,
- .irq_unmask = frv_fpga_unmask,
-};
-
-/*
- * FPGA PIC interrupt handler
- */
-static irqreturn_t fpga_interrupt(int irq, void *_mask)
-{
- uint16_t imr, mask = (unsigned long) _mask;
-
- imr = __get_IMR();
- mask = mask & ~imr & __get_IFR();
-
- /* poll all the triggered IRQs */
- while (mask) {
- int irq;
-
- asm("scan %1,gr0,%0" : "=r"(irq) : "r"(mask));
- irq = 31 - irq;
- mask &= ~(1 << irq);
-
- generic_handle_irq(IRQ_BASE_FPGA + irq);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * define an interrupt action for each FPGA PIC output
- * - use dev_id to indicate the FPGA PIC input to output mappings
- */
-static struct irqaction fpga_irq[1] = {
- [0] = {
- .handler = fpga_interrupt,
- .name = "fpga.0",
- .dev_id = (void *) 0x0700UL,
- }
-};
-
-/*
- * initialise the motherboard FPGA's PIC
- */
-void __init fpga_init(void)
-{
- int irq;
-
- /* all PIC inputs are all set to be edge triggered */
- __set_IMR(0x0700);
- __clr_IFR(0x0000);
-
- for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
- irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
-
- /* the FPGA drives external IRQ input #2 on the CPU PIC */
- setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
-}
diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c
deleted file mode 100644
index 8ca5aa4ff595..000000000000
--- a/arch/frv/kernel/irq-mb93493.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* irq-mb93493.c: MB93493 companion chip interrupt handler
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/bitops.h>
-
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-#include <asm/mb93493-irqs.h>
-#include <asm/mb93493-regs.h>
-
-#define IRQ_ROUTE_ONE(X) (X##_ROUTE << (X - IRQ_BASE_MB93493))
-
-#define IRQ_ROUTING \
- (IRQ_ROUTE_ONE(IRQ_MB93493_VDC) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_VCC) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_OUT) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_I2C_0) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_I2C_1) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_USB) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_LOCAL_BUS) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_PCMCIA) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_GPIO) | \
- IRQ_ROUTE_ONE(IRQ_MB93493_AUDIO_IN))
-
-/*
- * daughter board PIC operations
- * - there is no way to ACK interrupts in the MB93493 chip
- */
-static void frv_mb93493_mask(struct irq_data *d)
-{
- uint32_t iqsr;
- volatile void *piqsr;
-
- if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
- piqsr = __addr_MB93493_IQSR(1);
- else
- piqsr = __addr_MB93493_IQSR(0);
-
- iqsr = readl(piqsr);
- iqsr &= ~(1 << (d->irq - IRQ_BASE_MB93493 + 16));
- writel(iqsr, piqsr);
-}
-
-static void frv_mb93493_ack(struct irq_data *d)
-{
-}
-
-static void frv_mb93493_unmask(struct irq_data *d)
-{
- uint32_t iqsr;
- volatile void *piqsr;
-
- if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
- piqsr = __addr_MB93493_IQSR(1);
- else
- piqsr = __addr_MB93493_IQSR(0);
-
- iqsr = readl(piqsr);
- iqsr |= 1 << (d->irq - IRQ_BASE_MB93493 + 16);
- writel(iqsr, piqsr);
-}
-
-static struct irq_chip frv_mb93493_pic = {
- .name = "mb93093",
- .irq_ack = frv_mb93493_ack,
- .irq_mask = frv_mb93493_mask,
- .irq_mask_ack = frv_mb93493_mask,
- .irq_unmask = frv_mb93493_unmask,
-};
-
-/*
- * MB93493 PIC interrupt handler
- */
-static irqreturn_t mb93493_interrupt(int irq, void *_piqsr)
-{
- volatile void *piqsr = _piqsr;
- uint32_t iqsr;
-
- iqsr = readl(piqsr);
- iqsr = iqsr & (iqsr >> 16) & 0xffff;
-
- /* poll all the triggered IRQs */
- while (iqsr) {
- int irq;
-
- asm("scan %1,gr0,%0" : "=r"(irq) : "r"(iqsr));
- irq = 31 - irq;
- iqsr &= ~(1 << irq);
-
- generic_handle_irq(IRQ_BASE_MB93493 + irq);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * define an interrupt action for each MB93493 PIC output
- * - use dev_id to indicate the MB93493 PIC input to output mappings
- */
-static struct irqaction mb93493_irq[2] = {
- [0] = {
- .handler = mb93493_interrupt,
- .flags = IRQF_SHARED,
- .name = "mb93493.0",
- .dev_id = (void *) __addr_MB93493_IQSR(0),
- },
- [1] = {
- .handler = mb93493_interrupt,
- .flags = IRQF_SHARED,
- .name = "mb93493.1",
- .dev_id = (void *) __addr_MB93493_IQSR(1),
- }
-};
-
-/*
- * initialise the motherboard MB93493's PIC
- */
-void __init mb93493_init(void)
-{
- int irq;
-
- for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
- irq_set_chip_and_handler(irq, &frv_mb93493_pic,
- handle_edge_irq);
-
- /* the MB93493 drives external IRQ inputs on the CPU PIC */
- setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
- setup_irq(IRQ_CPU_MB93493_1, &mb93493_irq[1]);
-}
diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c
deleted file mode 100644
index 93513e4ccd2b..000000000000
--- a/arch/frv/kernel/irq.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* irq.c: FRV IRQ handling
- *
- * Copyright (C) 2003, 2004, 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/ptrace.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/timex.h>
-#include <linux/random.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/irq.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/module.h>
-#include <linux/bitops.h>
-
-#include <linux/atomic.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <linux/uaccess.h>
-#include <asm/pgalloc.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/irc-regs.h>
-#include <asm/gdb-stub.h>
-
-#define set_IRR(N,A,B,C,D) __set_IRR(N, (A << 28) | (B << 24) | (C << 20) | (D << 16))
-
-extern void __init fpga_init(void);
-#ifdef CONFIG_FUJITSU_MB93493
-extern void __init mb93493_init(void);
-#endif
-
-#define __reg16(ADDR) (*(volatile unsigned short *)(ADDR))
-
-atomic_t irq_err_count;
-
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
- seq_printf(p, "%*s: ", prec, "ERR");
- seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
- return 0;
-}
-
-/*
- * on-CPU PIC operations
- */
-static void frv_cpupic_ack(struct irq_data *d)
-{
- __clr_RC(d->irq);
- __clr_IRL();
-}
-
-static void frv_cpupic_mask(struct irq_data *d)
-{
- __set_MASK(d->irq);
-}
-
-static void frv_cpupic_mask_ack(struct irq_data *d)
-{
- __set_MASK(d->irq);
- __clr_RC(d->irq);
- __clr_IRL();
-}
-
-static void frv_cpupic_unmask(struct irq_data *d)
-{
- __clr_MASK(d->irq);
-}
-
-static struct irq_chip frv_cpu_pic = {
- .name = "cpu",
- .irq_ack = frv_cpupic_ack,
- .irq_mask = frv_cpupic_mask,
- .irq_mask_ack = frv_cpupic_mask_ack,
- .irq_unmask = frv_cpupic_unmask,
-};
-
-/*
- * handles all normal device IRQs
- * - registers are referred to by the __frame variable (GR28)
- * - IRQ distribution is complicated in this arch because of the many PICs, the
- * way they work and the way they cascade
- */
-asmlinkage void do_IRQ(void)
-{
- irq_enter();
- generic_handle_irq(__get_IRL());
- irq_exit();
-}
-
-/*
- * handles all NMIs when not co-opted by the debugger
- * - registers are referred to by the __frame variable (GR28)
- */
-asmlinkage void do_NMI(void)
-{
-}
-
-/*
- * initialise the interrupt system
- */
-void __init init_IRQ(void)
-{
- int level;
-
- for (level = 1; level <= 14; level++)
- irq_set_chip_and_handler(level, &frv_cpu_pic,
- handle_level_irq);
-
- irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
-
- /* set the trigger levels for internal interrupt sources
- * - timers all falling-edge
- * - ERR0 is rising-edge
- * - all others are high-level
- */
- __set_IITMR(0, 0x003f0000); /* DMA0-3, TIMER0-2 */
- __set_IITMR(1, 0x20000000); /* ERR0-1, UART0-1, DMA4-7 */
-
- /* route internal interrupts */
- set_IRR(4, IRQ_DMA3_LEVEL, IRQ_DMA2_LEVEL, IRQ_DMA1_LEVEL,
- IRQ_DMA0_LEVEL);
- set_IRR(5, 0, IRQ_TIMER2_LEVEL, IRQ_TIMER1_LEVEL, IRQ_TIMER0_LEVEL);
- set_IRR(6, IRQ_GDBSTUB_LEVEL, IRQ_GDBSTUB_LEVEL,
- IRQ_UART1_LEVEL, IRQ_UART0_LEVEL);
- set_IRR(7, IRQ_DMA7_LEVEL, IRQ_DMA6_LEVEL, IRQ_DMA5_LEVEL,
- IRQ_DMA4_LEVEL);
-
- /* route external interrupts */
- set_IRR(2, IRQ_XIRQ7_LEVEL, IRQ_XIRQ6_LEVEL, IRQ_XIRQ5_LEVEL,
- IRQ_XIRQ4_LEVEL);
- set_IRR(3, IRQ_XIRQ3_LEVEL, IRQ_XIRQ2_LEVEL, IRQ_XIRQ1_LEVEL,
- IRQ_XIRQ0_LEVEL);
-
-#if defined(CONFIG_MB93091_VDK)
- __set_TM1(0x55550000); /* XIRQ7-0 all active low */
-#elif defined(CONFIG_MB93093_PDK)
- __set_TM1(0x15550000); /* XIRQ7 active high, 6-0 all active low */
-#else
-#error dont know external IRQ trigger levels for this setup
-#endif
-
- fpga_init();
-#ifdef CONFIG_FUJITSU_MB93493
- mb93493_init();
-#endif
-}
diff --git a/arch/frv/kernel/local.h b/arch/frv/kernel/local.h
deleted file mode 100644
index 76606d13b1aa..000000000000
--- a/arch/frv/kernel/local.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* local.h: local definitions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _FRV_LOCAL_H
-#define _FRV_LOCAL_H
-
-#include <asm/sections.h>
-
-#ifndef __ASSEMBLY__
-
-/* dma.c */
-extern unsigned long frv_dma_inprogress;
-
-extern void frv_dma_pause_all(void);
-extern void frv_dma_resume_all(void);
-
-/* sleep.S */
-extern asmlinkage void frv_cpu_suspend(unsigned long);
-extern asmlinkage void frv_cpu_core_sleep(void);
-
-/* setup.c */
-extern unsigned long __nongprelbss pdm_suspend_mode;
-extern void determine_clocks(int verbose);
-extern int __nongprelbss clock_p0_current;
-extern int __nongprelbss clock_cm_current;
-extern int __nongprelbss clock_cmode_current;
-
-#ifdef CONFIG_PM
-extern int __nongprelbss clock_cmodes_permitted;
-extern unsigned long __nongprelbss clock_bits_settable;
-#define CLOCK_BIT_CM 0x0000000f
-#define CLOCK_BIT_CM_H 0x00000001 /* CLKC.CM can be set to 0 */
-#define CLOCK_BIT_CM_M 0x00000002 /* CLKC.CM can be set to 1 */
-#define CLOCK_BIT_CM_L 0x00000004 /* CLKC.CM can be set to 2 */
-#define CLOCK_BIT_P0 0x00000010 /* CLKC.P0 can be changed */
-#define CLOCK_BIT_CMODE 0x00000020 /* CLKC.CMODE can be changed */
-
-extern void (*__power_switch_wake_setup)(void);
-extern int (*__power_switch_wake_check)(void);
-extern void (*__power_switch_wake_cleanup)(void);
-#endif
-
-/* time.c */
-extern void time_divisor_init(void);
-
-/* cmode.S */
-extern asmlinkage void frv_change_cmode(int);
-
-
-#endif /* __ASSEMBLY__ */
-#endif /* _FRV_LOCAL_H */
diff --git a/arch/frv/kernel/local64.h b/arch/frv/kernel/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/frv/kernel/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/frv/kernel/module.c b/arch/frv/kernel/module.c
deleted file mode 100644
index 9d9835f1fe2b..000000000000
--- a/arch/frv/kernel/module.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* module.c: FRV specific module loading bits
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/i386/kernel/module.c, Copyright (C) 2001 Rusty Russell.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-
-#if 0
-#define DEBUGP printk
-#else
-#define DEBUGP(fmt...)
-#endif
-
-/* TODO: At least one of apply_relocate or apply_relocate_add must be
- * implemented in order to get working module support.
- */
diff --git a/arch/frv/kernel/pm-mb93093.c b/arch/frv/kernel/pm-mb93093.c
deleted file mode 100644
index 8358e34a3fad..000000000000
--- a/arch/frv/kernel/pm-mb93093.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * FR-V MB93093 Power Management Routines
- *
- * Copyright (c) 2004 Red Hat, Inc.
- *
- * Written by: msalter@redhat.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License.
- *
- */
-
-#include <linux/init.h>
-#include <linux/pm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/sysctl.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-
-#include <asm/mb86943a.h>
-
-#include "local.h"
-
-static unsigned long imask;
-/*
- * Setup interrupt masks, etc to enable wakeup by power switch
- */
-static void mb93093_power_switch_setup(void)
-{
- /* mask all but FPGA interrupt sources. */
- imask = *(volatile unsigned long *)0xfeff9820;
- *(volatile unsigned long *)0xfeff9820 = ~(1 << (IRQ_XIRQ2_LEVEL + 16)) & 0xfffe0000;
-}
-
-/*
- * Cleanup interrupt masks, etc after wakeup by power switch
- */
-static void mb93093_power_switch_cleanup(void)
-{
- *(volatile unsigned long *)0xfeff9820 = imask;
-}
-
-/*
- * Return non-zero if wakeup irq was caused by power switch
- */
-static int mb93093_power_switch_check(void)
-{
- return 1;
-}
-
-/*
- * Initialize power interface
- */
-static int __init mb93093_pm_init(void)
-{
- __power_switch_wake_setup = mb93093_power_switch_setup;
- __power_switch_wake_check = mb93093_power_switch_check;
- __power_switch_wake_cleanup = mb93093_power_switch_cleanup;
- return 0;
-}
-
-__initcall(mb93093_pm_init);
-
diff --git a/arch/frv/kernel/pm.c b/arch/frv/kernel/pm.c
deleted file mode 100644
index 051ccecbf7f1..000000000000
--- a/arch/frv/kernel/pm.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * FR-V Power Management Routines
- *
- * Copyright (c) 2004 Red Hat, Inc.
- *
- * Based on SA1100 version:
- * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License.
- *
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/pm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/sysctl.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-
-#include <asm/mb86943a.h>
-
-#include "local.h"
-
-/*
- * Debug macros
- */
-#define DEBUG
-
-int pm_do_suspend(void)
-{
- local_irq_disable();
-
- __set_LEDS(0xb1);
-
- /* go zzz */
- frv_cpu_suspend(pdm_suspend_mode);
-
- __set_LEDS(0xb2);
-
- local_irq_enable();
-
- return 0;
-}
-
-static unsigned long __irq_mask;
-
-/*
- * Setup interrupt masks, etc to enable wakeup by power switch
- */
-static void __default_power_switch_setup(void)
-{
- /* default is to mask all interrupt sources. */
- __irq_mask = *(unsigned long *)0xfeff9820;
- *(unsigned long *)0xfeff9820 = 0xfffe0000;
-}
-
-/*
- * Cleanup interrupt masks, etc after wakeup by power switch
- */
-static void __default_power_switch_cleanup(void)
-{
- *(unsigned long *)0xfeff9820 = __irq_mask;
-}
-
-/*
- * Return non-zero if wakeup irq was caused by power switch
- */
-static int __default_power_switch_check(void)
-{
- return 1;
-}
-
-void (*__power_switch_wake_setup)(void) = __default_power_switch_setup;
-int (*__power_switch_wake_check)(void) = __default_power_switch_check;
-void (*__power_switch_wake_cleanup)(void) = __default_power_switch_cleanup;
-
-int pm_do_bus_sleep(void)
-{
- local_irq_disable();
-
- /*
- * Here is where we need some platform-dependent setup
- * of the interrupt state so that appropriate wakeup
- * sources are allowed and all others are masked.
- */
- __power_switch_wake_setup();
-
- __set_LEDS(0xa1);
-
- /* go zzz
- *
- * This is in a loop in case power switch shares an irq with other
- * devices. The wake_check() tells us if we need to finish waking
- * or go back to sleep.
- */
- do {
- frv_cpu_suspend(HSR0_PDM_BUS_SLEEP);
- } while (__power_switch_wake_check && !__power_switch_wake_check());
-
- __set_LEDS(0xa2);
-
- /*
- * Here is where we need some platform-dependent restore
- * of the interrupt state prior to being called.
- */
- __power_switch_wake_cleanup();
-
- local_irq_enable();
-
- return 0;
-}
-
-unsigned long sleep_phys_sp(void *sp)
-{
- return virt_to_phys(sp);
-}
-
-#ifdef CONFIG_SYSCTL
-/*
- * Use a temporary sysctl number. Horrid, but will be cleaned up in 2.6
- * when all the PM interfaces exist nicely.
- */
-#define CTL_PM_SUSPEND 1
-#define CTL_PM_CMODE 2
-#define CTL_PM_P0 4
-#define CTL_PM_CM 5
-
-static int user_atoi(char __user *ubuf, size_t len)
-{
- char buf[16];
- unsigned long ret;
-
- if (len > 15)
- return -EINVAL;
-
- if (copy_from_user(buf, ubuf, len))
- return -EFAULT;
-
- buf[len] = 0;
- ret = simple_strtoul(buf, NULL, 0);
- if (ret > INT_MAX)
- return -ERANGE;
- return ret;
-}
-
-/*
- * Send us to sleep.
- */
-static int sysctl_pm_do_suspend(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int mode;
-
- if (*lenp <= 0)
- return -EIO;
-
- mode = user_atoi(buffer, *lenp);
- switch (mode) {
- case 1:
- return pm_do_suspend();
-
- case 5:
- return pm_do_bus_sleep();
-
- default:
- return -EINVAL;
- }
-}
-
-static int try_set_cmode(int new_cmode)
-{
- if (new_cmode > 15)
- return -EINVAL;
- if (!(clock_cmodes_permitted & (1<<new_cmode)))
- return -EINVAL;
-
- /* now change cmode */
- local_irq_disable();
- frv_dma_pause_all();
-
- frv_change_cmode(new_cmode);
-
- determine_clocks(0);
- time_divisor_init();
-
-#ifdef DEBUG
- determine_clocks(1);
-#endif
- frv_dma_resume_all();
- local_irq_enable();
-
- return 0;
-}
-
-
-static int cmode_procctl(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int new_cmode;
-
- if (!write)
- return proc_dointvec(ctl, write, buffer, lenp, fpos);
-
- new_cmode = user_atoi(buffer, *lenp);
-
- return try_set_cmode(new_cmode)?:*lenp;
-}
-
-static int try_set_p0(int new_p0)
-{
- unsigned long flags, clkc;
-
- if (new_p0 < 0 || new_p0 > 1)
- return -EINVAL;
-
- local_irq_save(flags);
- __set_PSR(flags & ~PSR_ET);
-
- frv_dma_pause_all();
-
- clkc = __get_CLKC();
- if (new_p0)
- clkc |= CLKC_P0;
- else
- clkc &= ~CLKC_P0;
- __set_CLKC(clkc);
-
- determine_clocks(0);
- time_divisor_init();
-
-#ifdef DEBUG
- determine_clocks(1);
-#endif
- frv_dma_resume_all();
- local_irq_restore(flags);
- return 0;
-}
-
-static int try_set_cm(int new_cm)
-{
- unsigned long flags, clkc;
-
- if (new_cm < 0 || new_cm > 1)
- return -EINVAL;
-
- local_irq_save(flags);
- __set_PSR(flags & ~PSR_ET);
-
- frv_dma_pause_all();
-
- clkc = __get_CLKC();
- clkc &= ~CLKC_CM;
- clkc |= new_cm;
- __set_CLKC(clkc);
-
- determine_clocks(0);
- time_divisor_init();
-
-#if 1 //def DEBUG
- determine_clocks(1);
-#endif
-
- frv_dma_resume_all();
- local_irq_restore(flags);
- return 0;
-}
-
-static int p0_procctl(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int new_p0;
-
- if (!write)
- return proc_dointvec(ctl, write, buffer, lenp, fpos);
-
- new_p0 = user_atoi(buffer, *lenp);
-
- return try_set_p0(new_p0)?:*lenp;
-}
-
-static int cm_procctl(struct ctl_table *ctl, int write,
- void __user *buffer, size_t *lenp, loff_t *fpos)
-{
- int new_cm;
-
- if (!write)
- return proc_dointvec(ctl, write, buffer, lenp, fpos);
-
- new_cm = user_atoi(buffer, *lenp);
-
- return try_set_cm(new_cm)?:*lenp;
-}
-
-static struct ctl_table pm_table[] =
-{
- {
- .procname = "suspend",
- .data = NULL,
- .maxlen = 0,
- .mode = 0200,
- .proc_handler = sysctl_pm_do_suspend,
- },
- {
- .procname = "cmode",
- .data = &clock_cmode_current,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = cmode_procctl,
- },
- {
- .procname = "p0",
- .data = &clock_p0_current,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = p0_procctl,
- },
- {
- .procname = "cm",
- .data = &clock_cm_current,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = cm_procctl,
- },
- { }
-};
-
-static struct ctl_table pm_dir_table[] =
-{
- {
- .procname = "pm",
- .mode = 0555,
- .child = pm_table,
- },
- { }
-};
-
-/*
- * Initialize power interface
- */
-static int __init pm_init(void)
-{
- register_sysctl_table(pm_dir_table);
- return 0;
-}
-
-__initcall(pm_init);
-
-#endif
diff --git a/arch/frv/kernel/process.c b/arch/frv/kernel/process.c
deleted file mode 100644
index a957b374e3a6..000000000000
--- a/arch/frv/kernel/process.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/* process.c: FRV specific parts of process handling
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/process.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/user.h>
-#include <linux/elf.h>
-#include <linux/reboot.h>
-#include <linux/interrupt.h>
-#include <linux/pagemap.h>
-#include <linux/rcupdate.h>
-
-#include <asm/asm-offsets.h>
-#include <linux/uaccess.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/tlb.h>
-#include <asm/gdb-stub.h>
-#include <asm/mb-regs.h>
-
-#include "local.h"
-
-asmlinkage void ret_from_fork(void);
-asmlinkage void ret_from_kernel_thread(void);
-
-#include <asm/pgalloc.h>
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-static void core_sleep_idle(void)
-{
-#ifdef LED_DEBUG_SLEEP
- /* Show that we're sleeping... */
- __set_LEDS(0x55aa);
-#endif
- frv_cpu_core_sleep();
-#ifdef LED_DEBUG_SLEEP
- /* ... and that we woke up */
- __set_LEDS(0);
-#endif
- mb();
-}
-
-void arch_cpu_idle(void)
-{
- if (!frv_dma_inprogress)
- core_sleep_idle();
- else
- local_irq_enable();
-}
-
-void machine_restart(char * __unused)
-{
- unsigned long reset_addr;
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(0);
-#endif
-
- if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551)
- reset_addr = 0xfefff500;
- else
- reset_addr = 0xfeff0500;
-
- /* Software reset. */
- asm volatile(" dcef @(gr0,gr0),1 ! membar !"
- " sti %1,@(%0,0) !"
- " nop ! nop ! nop ! nop ! nop ! "
- " nop ! nop ! nop ! nop ! nop ! "
- " nop ! nop ! nop ! nop ! nop ! "
- " nop ! nop ! nop ! nop ! nop ! "
- : : "r" (reset_addr), "r" (1) );
-
- for (;;)
- ;
-}
-
-void machine_halt(void)
-{
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(0);
-#endif
-
- for (;;);
-}
-
-void machine_power_off(void)
-{
-#ifdef CONFIG_GDBSTUB
- gdbstub_exit(0);
-#endif
-
- for (;;);
-}
-
-void flush_thread(void)
-{
- /* nothing */
-}
-
-inline unsigned long user_stack(const struct pt_regs *regs)
-{
- while (regs->next_frame)
- regs = regs->next_frame;
- return user_mode(regs) ? regs->sp : 0;
-}
-
-/*
- * set up the kernel stack and exception frames for a new process
- */
-int copy_thread(unsigned long clone_flags,
- unsigned long usp, unsigned long arg,
- struct task_struct *p)
-{
- struct pt_regs *childregs;
-
- childregs = (struct pt_regs *)
- (task_stack_page(p) + THREAD_SIZE - FRV_FRAME0_SIZE);
-
- /* set up the userspace frame (the only place that the USP is stored) */
- *childregs = *current_pt_regs();
-
- p->thread.frame = childregs;
- p->thread.curr = p;
- p->thread.sp = (unsigned long) childregs;
- p->thread.fp = 0;
- p->thread.lr = 0;
- p->thread.frame0 = childregs;
-
- if (unlikely(p->flags & PF_KTHREAD)) {
- childregs->gr9 = usp; /* function */
- childregs->gr8 = arg;
- p->thread.pc = (unsigned long) ret_from_kernel_thread;
- save_user_regs(p->thread.user);
- return 0;
- }
- if (usp)
- childregs->sp = usp;
- childregs->next_frame = NULL;
-
- p->thread.pc = (unsigned long) ret_from_fork;
-
- /* the new TLS pointer is passed in as arg #5 to sys_clone() */
- if (clone_flags & CLONE_SETTLS)
- childregs->gr29 = childregs->gr12;
-
- save_user_regs(p->thread.user);
-
- return 0;
-} /* end copy_thread() */
-
-unsigned long get_wchan(struct task_struct *p)
-{
- struct pt_regs *regs0;
- unsigned long fp, pc;
- unsigned long stack_limit;
- int count = 0;
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
-
- stack_limit = (unsigned long) (p + 1);
- fp = p->thread.fp;
- regs0 = p->thread.frame0;
-
- do {
- if (fp < stack_limit || fp >= (unsigned long) regs0 || fp & 3)
- return 0;
-
- pc = ((unsigned long *) fp)[2];
-
- /* FIXME: This depends on the order of these functions. */
- if (!in_sched_functions(pc))
- return pc;
-
- fp = *(unsigned long *) fp;
- } while (count++ < 16);
-
- return 0;
-}
-
-int elf_check_arch(const struct elf32_hdr *hdr)
-{
- unsigned long hsr0 = __get_HSR(0);
- unsigned long psr = __get_PSR();
-
- if (hdr->e_machine != EM_FRV)
- return 0;
-
- switch (hdr->e_flags & EF_FRV_GPR_MASK) {
- case EF_FRV_GPR64:
- if ((hsr0 & HSR0_GRN) == HSR0_GRN_32)
- return 0;
- case EF_FRV_GPR32:
- case 0:
- break;
- default:
- return 0;
- }
-
- switch (hdr->e_flags & EF_FRV_FPR_MASK) {
- case EF_FRV_FPR64:
- if ((hsr0 & HSR0_FRN) == HSR0_FRN_32)
- return 0;
- case EF_FRV_FPR32:
- case EF_FRV_FPR_NONE:
- case 0:
- break;
- default:
- return 0;
- }
-
- if ((hdr->e_flags & EF_FRV_MULADD) == EF_FRV_MULADD)
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR405 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR451)
- return 0;
-
- switch (hdr->e_flags & EF_FRV_CPU_MASK) {
- case EF_FRV_CPU_GENERIC:
- break;
- case EF_FRV_CPU_FR300:
- case EF_FRV_CPU_SIMPLE:
- case EF_FRV_CPU_TOMCAT:
- default:
- return 0;
- case EF_FRV_CPU_FR400:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR401 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR405 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR451 &&
- PSR_IMPLE(psr) != PSR_IMPLE_FR551)
- return 0;
- break;
- case EF_FRV_CPU_FR450:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR451)
- return 0;
- break;
- case EF_FRV_CPU_FR500:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR501)
- return 0;
- break;
- case EF_FRV_CPU_FR550:
- if (PSR_IMPLE(psr) != PSR_IMPLE_FR551)
- return 0;
- break;
- }
-
- return 1;
-}
-
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpregs)
-{
- memcpy(fpregs,
- &current->thread.user->f,
- sizeof(current->thread.user->f));
- return 1;
-}
diff --git a/arch/frv/kernel/ptrace.c b/arch/frv/kernel/ptrace.c
deleted file mode 100644
index 49768401ce0f..000000000000
--- a/arch/frv/kernel/ptrace.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/* ptrace.c: FRV specific parts of process tracing
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/ptrace.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/security.h>
-#include <linux/signal.h>
-#include <linux/regset.h>
-#include <linux/elf.h>
-#include <linux/tracehook.h>
-
-#include <linux/uaccess.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/unistd.h>
-
-/*
- * does not yet catch signals sent when the child dies.
- * in exit.c or in signal.c.
- */
-
-/*
- * retrieve the contents of FRV userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct user_int_regs *iregs = &target->thread.user->i;
- int ret;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- iregs, 0, sizeof(*iregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*iregs), -1);
-}
-
-/*
- * update the contents of the FRV userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct user_int_regs *iregs = &target->thread.user->i;
- unsigned int offs_gr0, offs_gr1;
- int ret;
-
- /* not allowed to set PSR or __status */
- if (pos < offsetof(struct user_int_regs, psr) + sizeof(long) &&
- pos + count > offsetof(struct user_int_regs, psr))
- return -EIO;
-
- if (pos < offsetof(struct user_int_regs, __status) + sizeof(long) &&
- pos + count > offsetof(struct user_int_regs, __status))
- return -EIO;
-
- /* set the control regs */
- offs_gr0 = offsetof(struct user_int_regs, gr[0]);
- offs_gr1 = offsetof(struct user_int_regs, gr[1]);
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- iregs, 0, offs_gr0);
- if (ret < 0)
- return ret;
-
- /* skip GR0/TBR */
- ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- offs_gr0, offs_gr1);
- if (ret < 0)
- return ret;
-
- /* set the general regs */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &iregs->gr[1], offs_gr1, sizeof(*iregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- sizeof(*iregs), -1);
-}
-
-/*
- * retrieve the contents of FRV userspace FP/Media registers
- */
-static int fpmregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct user_fpmedia_regs *fpregs = &target->thread.user->f;
- int ret;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- fpregs, 0, sizeof(*fpregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*fpregs), -1);
-}
-
-/*
- * update the contents of the FRV userspace FP/Media registers
- */
-static int fpmregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct user_fpmedia_regs *fpregs = &target->thread.user->f;
- int ret;
-
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- fpregs, 0, sizeof(*fpregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- sizeof(*fpregs), -1);
-}
-
-/*
- * determine if the FP/Media registers have actually been used
- */
-static int fpmregs_active(struct task_struct *target,
- const struct user_regset *regset)
-{
- return tsk_used_math(target) ? regset->n : 0;
-}
-
-/*
- * Define the register sets available on the FRV under Linux
- */
-enum frv_regset {
- REGSET_GENERAL,
- REGSET_FPMEDIA,
-};
-
-static const struct user_regset frv_regsets[] = {
- /*
- * General register format is:
- * PSR, ISR, CCR, CCCR, LR, LCR, PC, (STATUS), SYSCALLNO, ORIG_G8
- * GNER0-1, IACC0, TBR, GR1-63
- */
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = ELF_NGREG,
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
- /*
- * FPU/Media register format is:
- * FR0-63, FNER0-1, MSR0-1, ACC0-7, ACCG0-8, FSR
- */
- [REGSET_FPMEDIA] = {
- .core_note_type = NT_PRFPREG,
- .n = sizeof(struct user_fpmedia_regs) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long),
- .get = fpmregs_get,
- .set = fpmregs_set,
- .active = fpmregs_active,
- },
-};
-
-static const struct user_regset_view user_frv_native_view = {
- .name = "frv",
- .e_machine = EM_FRV,
- .regsets = frv_regsets,
- .n = ARRAY_SIZE(frv_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_frv_native_view;
-}
-
-/*
- * Get contents of register REGNO in task TASK.
- */
-static inline long get_reg(struct task_struct *task, int regno)
-{
- struct user_context *user = task->thread.user;
-
- if (regno < 0 || regno >= PT__END)
- return 0;
-
- return ((unsigned long *) user)[regno];
-}
-
-/*
- * Write contents of register REGNO in task TASK.
- */
-static inline int put_reg(struct task_struct *task, int regno,
- unsigned long data)
-{
- struct user_context *user = task->thread.user;
-
- if (regno < 0 || regno >= PT__END)
- return -EIO;
-
- switch (regno) {
- case PT_GR(0):
- return 0;
- case PT_PSR:
- case PT__STATUS:
- return -EIO;
- default:
- ((unsigned long *) user)[regno] = data;
- return 0;
- }
-}
-
-/*
- * Called by kernel/ptrace.c when detaching..
- *
- * Control h/w single stepping
- */
-void user_enable_single_step(struct task_struct *child)
-{
- child->thread.frame0->__status |= REG__STATUS_STEP;
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- child->thread.frame0->__status &= ~REG__STATUS_STEP;
-}
-
-void ptrace_disable(struct task_struct *child)
-{
- user_disable_single_step(child);
-}
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- unsigned long tmp;
- int ret;
- int regno = addr >> 2;
- unsigned long __user *datap = (unsigned long __user *) data;
-
- switch (request) {
- /* read the word at location addr in the USER area. */
- case PTRACE_PEEKUSR: {
- tmp = 0;
- ret = -EIO;
- if (addr & 3)
- break;
-
- ret = 0;
- switch (regno) {
- case 0 ... PT__END - 1:
- tmp = get_reg(child, regno);
- break;
-
- case PT__END + 0:
- tmp = child->mm->end_code - child->mm->start_code;
- break;
-
- case PT__END + 1:
- tmp = child->mm->end_data - child->mm->start_data;
- break;
-
- case PT__END + 2:
- tmp = child->mm->start_stack - child->mm->start_brk;
- break;
-
- case PT__END + 3:
- tmp = child->mm->start_code;
- break;
-
- case PT__END + 4:
- tmp = child->mm->start_stack;
- break;
-
- default:
- ret = -EIO;
- break;
- }
-
- if (ret == 0)
- ret = put_user(tmp, datap);
- break;
- }
-
- case PTRACE_POKEUSR: /* write the word at location addr in the USER area */
- ret = -EIO;
- if (addr & 3)
- break;
-
- switch (regno) {
- case 0 ... PT__END - 1:
- ret = put_reg(child, regno, data);
- break;
- }
- break;
-
- case PTRACE_GETREGS: /* Get all integer regs from the child. */
- return copy_regset_to_user(child, &user_frv_native_view,
- REGSET_GENERAL,
- 0, sizeof(child->thread.user->i),
- datap);
-
- case PTRACE_SETREGS: /* Set all integer regs in the child. */
- return copy_regset_from_user(child, &user_frv_native_view,
- REGSET_GENERAL,
- 0, sizeof(child->thread.user->i),
- datap);
-
- case PTRACE_GETFPREGS: /* Get the child FP/Media state. */
- return copy_regset_to_user(child, &user_frv_native_view,
- REGSET_FPMEDIA,
- 0, sizeof(child->thread.user->f),
- datap);
-
- case PTRACE_SETFPREGS: /* Set the child FP/Media state. */
- return copy_regset_from_user(child, &user_frv_native_view,
- REGSET_FPMEDIA,
- 0, sizeof(child->thread.user->f),
- datap);
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
- return ret;
-}
-
-/*
- * handle tracing of system call entry
- * - return the revised system call number or ULONG_MAX to cause ENOSYS
- */
-asmlinkage unsigned long syscall_trace_entry(void)
-{
- __frame->__status |= REG__STATUS_SYSC_ENTRY;
- if (tracehook_report_syscall_entry(__frame)) {
- /* tracing decided this syscall should not happen, so
- * We'll return a bogus call number to get an ENOSYS
- * error, but leave the original number in
- * __frame->syscallno
- */
- return ULONG_MAX;
- }
-
- return __frame->syscallno;
-}
-
-/*
- * handle tracing of system call exit
- */
-asmlinkage void syscall_trace_exit(void)
-{
- __frame->__status |= REG__STATUS_SYSC_EXIT;
- tracehook_report_syscall_exit(__frame, 0);
-}
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
deleted file mode 100644
index 9f4a9a607dbe..000000000000
--- a/arch/frv/kernel/setup.c
+++ /dev/null
@@ -1,1178 +0,0 @@
-/* setup.c: FRV specific setup
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/setup.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <generated/utsrelease.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/fb.h>
-#include <linux/console.h>
-#include <linux/genhd.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/major.h>
-#include <linux/bootmem.h>
-#include <linux/highmem.h>
-#include <linux/seq_file.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-#include <linux/serial_8250.h>
-
-#include <asm/setup.h>
-#include <asm/irq.h>
-#include <asm/sections.h>
-#include <asm/pgalloc.h>
-#include <asm/busctl-regs.h>
-#include <asm/serial-regs.h>
-#include <asm/timer-regs.h>
-#include <asm/irc-regs.h>
-#include <asm/spr-regs.h>
-#include <asm/mb-regs.h>
-#include <asm/mb93493-regs.h>
-#include <asm/gdb-stub.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_BLK_DEV_INITRD
-#include <asm/pgtable.h>
-#endif
-
-#include "local.h"
-
-#ifdef CONFIG_MB93090_MB00
-static void __init mb93090_display(void);
-#endif
-#ifdef CONFIG_MMU
-static void __init setup_linux_memory(void);
-#else
-static void __init setup_uclinux_memory(void);
-#endif
-
-#ifdef CONFIG_MB93090_MB00
-static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
-static char __initdata mb93090_version[] = UTS_RELEASE;
-
-int __nongprelbss mb93090_mb00_detected;
-#endif
-
-const char __frv_unknown_system[] = "unknown";
-const char __frv_mb93091_cb10[] = "mb93091-cb10";
-const char __frv_mb93091_cb11[] = "mb93091-cb11";
-const char __frv_mb93091_cb30[] = "mb93091-cb30";
-const char __frv_mb93091_cb41[] = "mb93091-cb41";
-const char __frv_mb93091_cb60[] = "mb93091-cb60";
-const char __frv_mb93091_cb70[] = "mb93091-cb70";
-const char __frv_mb93091_cb451[] = "mb93091-cb451";
-const char __frv_mb93090_mb00[] = "mb93090-mb00";
-
-const char __frv_mb93493[] = "mb93493";
-
-const char __frv_mb93093[] = "mb93093";
-
-static const char *__nongprelbss cpu_series;
-static const char *__nongprelbss cpu_core;
-static const char *__nongprelbss cpu_silicon;
-static const char *__nongprelbss cpu_mmu;
-static const char *__nongprelbss cpu_system;
-static const char *__nongprelbss cpu_board1;
-static const char *__nongprelbss cpu_board2;
-
-static unsigned long __nongprelbss cpu_psr_all;
-static unsigned long __nongprelbss cpu_hsr0_all;
-
-unsigned long __nongprelbss pdm_suspend_mode;
-
-unsigned long __nongprelbss rom_length;
-unsigned long __nongprelbss memory_start;
-unsigned long __nongprelbss memory_end;
-
-unsigned long __nongprelbss dma_coherent_mem_start;
-unsigned long __nongprelbss dma_coherent_mem_end;
-
-unsigned long __initdata __sdram_old_base;
-unsigned long __initdata num_mappedpages;
-
-char __initdata command_line[COMMAND_LINE_SIZE];
-char __initdata redboot_command_line[COMMAND_LINE_SIZE];
-
-#ifdef CONFIG_PM
-#define __pminit
-#define __pminitdata
-#define __pminitconst
-#else
-#define __pminit __init
-#define __pminitdata __initdata
-#define __pminitconst __initconst
-#endif
-
-struct clock_cmode {
- uint8_t xbus, sdram, corebus, core, dsu;
-};
-
-#define _frac(N,D) ((N)<<4 | (D))
-#define _x0_16 _frac(1,6)
-#define _x0_25 _frac(1,4)
-#define _x0_33 _frac(1,3)
-#define _x0_375 _frac(3,8)
-#define _x0_5 _frac(1,2)
-#define _x0_66 _frac(2,3)
-#define _x0_75 _frac(3,4)
-#define _x1 _frac(1,1)
-#define _x1_5 _frac(3,2)
-#define _x2 _frac(2,1)
-#define _x3 _frac(3,1)
-#define _x4 _frac(4,1)
-#define _x4_5 _frac(9,2)
-#define _x6 _frac(6,1)
-#define _x8 _frac(8,1)
-#define _x9 _frac(9,1)
-
-int __nongprelbss clock_p0_current;
-int __nongprelbss clock_cm_current;
-int __nongprelbss clock_cmode_current;
-#ifdef CONFIG_PM
-int __nongprelbss clock_cmodes_permitted;
-unsigned long __nongprelbss clock_bits_settable;
-#endif
-
-static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
-
-static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
- [4] = { _x1, _x1, _x2, _x2, _x0_25 },
- [5] = { _x1, _x2, _x4, _x4, _x0_5 },
- [8] = { _x1, _x1, _x1, _x2, _x0_25 },
- [9] = { _x1, _x2, _x2, _x4, _x0_5 },
- [11] = { _x1, _x4, _x4, _x8, _x1 },
- [12] = { _x1, _x1, _x2, _x4, _x0_5 },
- [13] = { _x1, _x2, _x4, _x8, _x1 },
-};
-
-static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
- [0] = { _x1, _x1, _x1, _x1, _x0_5 },
- [1] = { _x1, _x1, _x1, _x3, _x0_25 },
- [2] = { _x1, _x1, _x2, _x6, _x0_5 },
- [3] = { _x1, _x2, _x2, _x6, _x0_5 },
- [4] = { _x1, _x1, _x2, _x2, _x0_16 },
- [8] = { _x1, _x1, _x1, _x2, _x0_16 },
- [9] = { _x1, _x2, _x2, _x4, _x0_33 },
- [12] = { _x1, _x1, _x2, _x4, _x0_33 },
- [14] = { _x1, _x3, _x3, _x9, _x0_75 },
- [15] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
-
-#define CLOCK_CMODES_PERMITTED_FR405 0xd31f
-};
-
-static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
- [0] = { _x1, _x2, _x2, _x4, _x0_33 },
- [1] = { _x1, _x3, _x3, _x6, _x0_5 },
- [2] = { _x1, _x2, _x4, _x8, _x0_66 },
- [3] = { _x1, _x1_5, _x3, _x6, _x0_5 },
- [4] = { _x1, _x3, _x3, _x9, _x0_75 },
- [5] = { _x1, _x2, _x2, _x6, _x0_5 },
- [6] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
-};
-
-static const struct clock_cmode __pminitconst *clock_cmodes;
-static int __pminitdata clock_doubled;
-
-static struct uart_port __pminitdata __frv_uart0 = {
- .uartclk = 0,
- .membase = (char *) UART0_BASE,
- .irq = IRQ_CPU_UART0,
- .regshift = 3,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-};
-
-static struct uart_port __pminitdata __frv_uart1 = {
- .uartclk = 0,
- .membase = (char *) UART1_BASE,
- .irq = IRQ_CPU_UART1,
- .regshift = 3,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-};
-
-#if 0
-static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
-{
- unsigned long phys, virt, cxn, size;
-
-#ifdef CONFIG_MMU
- virt = amlr & 0xffffc000;
- cxn = amlr & 0x3fff;
-#else
- virt = ampr & 0xffffc000;
- cxn = 0;
-#endif
- phys = ampr & xAMPRx_PPFN;
- size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
-
- printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
- i_d, n,
- virt, virt + size - 1,
- phys,
- ampr & xAMPRx_S ? 'S' : '-',
- ampr & xAMPRx_C ? 'C' : '-',
- ampr & DAMPRx_WP ? 'W' : '-',
- ampr & xAMPRx_V ? 'V' : '-',
- cxn
- );
-}
-#endif
-
-/*****************************************************************************/
-/*
- * dump the memory map
- */
-static void __init dump_memory_map(void)
-{
-
-#if 0
- /* dump the protection map */
- printk_xampr(__get_IAMPR(0), __get_IAMLR(0), 'I', 0);
- printk_xampr(__get_IAMPR(1), __get_IAMLR(1), 'I', 1);
- printk_xampr(__get_IAMPR(2), __get_IAMLR(2), 'I', 2);
- printk_xampr(__get_IAMPR(3), __get_IAMLR(3), 'I', 3);
- printk_xampr(__get_IAMPR(4), __get_IAMLR(4), 'I', 4);
- printk_xampr(__get_IAMPR(5), __get_IAMLR(5), 'I', 5);
- printk_xampr(__get_IAMPR(6), __get_IAMLR(6), 'I', 6);
- printk_xampr(__get_IAMPR(7), __get_IAMLR(7), 'I', 7);
- printk_xampr(__get_IAMPR(8), __get_IAMLR(8), 'I', 8);
- printk_xampr(__get_IAMPR(9), __get_IAMLR(9), 'i', 9);
- printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
- printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
- printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
- printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
- printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
- printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
-
- printk_xampr(__get_DAMPR(0), __get_DAMLR(0), 'D', 0);
- printk_xampr(__get_DAMPR(1), __get_DAMLR(1), 'D', 1);
- printk_xampr(__get_DAMPR(2), __get_DAMLR(2), 'D', 2);
- printk_xampr(__get_DAMPR(3), __get_DAMLR(3), 'D', 3);
- printk_xampr(__get_DAMPR(4), __get_DAMLR(4), 'D', 4);
- printk_xampr(__get_DAMPR(5), __get_DAMLR(5), 'D', 5);
- printk_xampr(__get_DAMPR(6), __get_DAMLR(6), 'D', 6);
- printk_xampr(__get_DAMPR(7), __get_DAMLR(7), 'D', 7);
- printk_xampr(__get_DAMPR(8), __get_DAMLR(8), 'D', 8);
- printk_xampr(__get_DAMPR(9), __get_DAMLR(9), 'D', 9);
- printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
- printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
- printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
- printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
- printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
- printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
-#endif
-
-#if 0
- /* dump the bus controller registers */
- printk("LGCR: %08lx\n", __get_LGCR());
- printk("Master: %08lx-%08lx CR=%08lx\n",
- __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
- __get_LMAICR());
-
- int loop;
- for (loop = 1; loop <= 7; loop++) {
- unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
- printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
- loop,
- lsbr, lsbr + __get_LSAM(loop),
- lcr & 0x80000000 ? 'r' : '-',
- lcr & 0x40000000 ? 'w' : '-',
- lcr & 0x08000000 ? 'b' : '-',
- lcr & 0x04000000 ? 'B' : '-',
- lcr & 0x02000000 ? 'C' : '-',
- lcr & 0x01000000 ? 'D' : '-',
- lcr & 0x00800000 ? 'W' : '-',
- lcr & 0x00400000 ? 'R' : '-',
- (lcr & 0x00030000) == 0x00000000 ? '4' :
- (lcr & 0x00030000) == 0x00010000 ? '2' :
- (lcr & 0x00030000) == 0x00020000 ? '1' :
- '-'
- );
- }
-#endif
-
-#if 0
- printk("\n");
-#endif
-} /* end dump_memory_map() */
-
-/*****************************************************************************/
-/*
- * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
- */
-#ifdef CONFIG_MB93091_VDK
-static void __init detect_mb93091(void)
-{
-#ifdef CONFIG_MB93090_MB00
- /* Detect CB70 without motherboard */
- if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
- cpu_board1 = __frv_mb93090_mb00;
- mb93090_mb00_detected = 1;
- }
-#endif
-
-#ifdef CONFIG_FUJITSU_MB93493
- cpu_board2 = __frv_mb93493;
-#endif
-
-} /* end detect_mb93091() */
-#endif
-
-/*****************************************************************************/
-/*
- * determine the CPU type and set appropriate parameters
- *
- * Family Series CPU Core Silicon Imple Vers
- * ----------------------------------------------------------
- * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1]
- * | | |
- * | | +-> MB93401/A 02 01
- * | | |
- * | | +-> MB93403 02 02
- * | |
- * | +-> FR405 ----> MB93405 04 00
- * |
- * +-> FR450 ----> FR451 ----> MB93451 05 00
- * |
- * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2]
- * | |
- * | +-> MB93501/A 01 02
- * |
- * +-> FR550 --+-> FR551 ----> MB93555 03 01
- *
- * [1] The MB93401 is an obsolete CPU replaced by the MB93401A
- * [2] The MB93501 is an obsolete CPU replaced by the MB93501A
- *
- * Imple is PSR(Processor Status Register)[31:28].
- * Vers is PSR(Processor Status Register)[27:24].
- *
- * A "Silicon" consists of CPU core and some on-chip peripherals.
- */
-static void __init determine_cpu(void)
-{
- unsigned long hsr0 = __get_HSR(0);
- unsigned long psr = __get_PSR();
-
- /* work out what selectable services the CPU supports */
- __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
- cpu_psr_all = __get_PSR();
- __set_PSR(psr);
-
- __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
- cpu_hsr0_all = __get_HSR(0);
- __set_HSR(0, hsr0);
-
- /* derive other service specs from the CPU type */
- cpu_series = "unknown";
- cpu_core = "unknown";
- cpu_silicon = "unknown";
- cpu_mmu = "Prot";
- cpu_system = __frv_unknown_system;
- clock_cmodes = NULL;
- clock_doubled = 0;
-#ifdef CONFIG_PM
- clock_bits_settable = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
-#endif
-
- switch (PSR_IMPLE(psr)) {
- case PSR_IMPLE_FR401:
- cpu_series = "fr400";
- cpu_core = "fr401";
- pdm_suspend_mode = HSR0_PDM_PLL_RUN;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR401_MB93401:
- cpu_silicon = "mb93401";
- cpu_system = __frv_mb93091_cb10;
- clock_cmodes = clock_cmodes_fr401_fr403;
- clock_doubled = 1;
- break;
- case PSR_VERSION_FR401_MB93401A:
- cpu_silicon = "mb93401/A";
- cpu_system = __frv_mb93091_cb11;
- clock_cmodes = clock_cmodes_fr401_fr403;
- break;
- case PSR_VERSION_FR401_MB93403:
- cpu_silicon = "mb93403";
-#ifndef CONFIG_MB93093_PDK
- cpu_system = __frv_mb93091_cb30;
-#else
- cpu_system = __frv_mb93093;
-#endif
- clock_cmodes = clock_cmodes_fr401_fr403;
- break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR405:
- cpu_series = "fr400";
- cpu_core = "fr405";
- pdm_suspend_mode = HSR0_PDM_PLL_STOP;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR405_MB93405:
- cpu_silicon = "mb93405";
- cpu_system = __frv_mb93091_cb60;
- clock_cmodes = clock_cmodes_fr405;
-#ifdef CONFIG_PM
- clock_bits_settable |= CLOCK_BIT_CMODE;
- clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
-#endif
-
- /* the FPGA on the CB70 has extra registers
- * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
- * how we tell the difference between it and a CB60
- */
- if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
- cpu_system = __frv_mb93091_cb70;
- break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR451:
- cpu_series = "fr450";
- cpu_core = "fr451";
- pdm_suspend_mode = HSR0_PDM_PLL_STOP;
-#ifdef CONFIG_PM
- clock_bits_settable |= CLOCK_BIT_CMODE;
- clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
-#endif
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR451_MB93451:
- cpu_silicon = "mb93451";
- cpu_mmu = "Prot, SAT, xSAT, DAT";
- cpu_system = __frv_mb93091_cb451;
- clock_cmodes = clock_cmodes_fr405;
- break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR501:
- cpu_series = "fr500";
- cpu_core = "fr501";
- pdm_suspend_mode = HSR0_PDM_PLL_STOP;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR501_MB93501: cpu_silicon = "mb93501"; break;
- case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
- default:
- break;
- }
- break;
-
- case PSR_IMPLE_FR551:
- cpu_series = "fr550";
- cpu_core = "fr551";
- pdm_suspend_mode = HSR0_PDM_PLL_RUN;
-
- switch (PSR_VERSION(psr)) {
- case PSR_VERSION_FR551_MB93555:
- cpu_silicon = "mb93555";
- cpu_mmu = "Prot, SAT";
- cpu_system = __frv_mb93091_cb41;
- clock_cmodes = clock_cmodes_fr555;
- clock_doubled = 1;
- break;
- default:
- break;
- }
- break;
-
- default:
- break;
- }
-
- printk("- Series:%s CPU:%s Silicon:%s\n",
- cpu_series, cpu_core, cpu_silicon);
-
-#ifdef CONFIG_MB93091_VDK
- detect_mb93091();
-#endif
-
-#if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
- cpu_board2 = __frv_mb93493;
-#endif
-
-} /* end determine_cpu() */
-
-/*****************************************************************************/
-/*
- * calculate the bus clock speed
- */
-void __pminit determine_clocks(int verbose)
-{
- const struct clock_cmode *mode, *tmode;
- unsigned long clkc, psr, quot;
-
- clkc = __get_CLKC();
- psr = __get_PSR();
-
- clock_p0_current = !!(clkc & CLKC_P0);
- clock_cm_current = clkc & CLKC_CM;
- clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
-
- if (verbose)
- printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
-
- /* the CB70 has some alternative ways of setting the clock speed through switches accessed
- * through the FPGA. */
- if (cpu_system == __frv_mb93091_cb70) {
- unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
-
- if (clkswr & 0x1000)
- __clkin_clock_speed_HZ = 60000000UL;
- else
- __clkin_clock_speed_HZ =
- ((clkswr >> 8) & 0xf) * 10000000 +
- ((clkswr >> 4) & 0xf) * 1000000 +
- ((clkswr ) & 0xf) * 100000;
- }
- /* the FR451 is currently fixed at 24MHz */
- else if (cpu_system == __frv_mb93091_cb451) {
- //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
- unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
-
- if (clkswr & 0x1000)
- __clkin_clock_speed_HZ = 60000000UL;
- else
- __clkin_clock_speed_HZ =
- ((clkswr >> 8) & 0xf) * 10000000 +
- ((clkswr >> 4) & 0xf) * 1000000 +
- ((clkswr ) & 0xf) * 100000;
- }
- /* otherwise determine the clockspeed from VDK or other registers */
- else {
- __clkin_clock_speed_HZ = __get_CLKIN();
- }
-
- /* look up the appropriate clock relationships table entry */
- mode = &undef_clock_cmode;
- if (clock_cmodes) {
- tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
- if (tmode->xbus)
- mode = tmode;
- }
-
-#define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
-
- if (clock_doubled)
- __clkin_clock_speed_HZ <<= 1;
-
- __ext_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
- __sdram_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
- __dsu_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
-
- switch (clkc & CLKC_CM) {
- case 0: /* High */
- __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
- __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->core);
- break;
- case 1: /* Medium */
- __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
- __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
- break;
- case 2: /* Low; not supported */
- case 3: /* UNDEF */
- printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
- panic("Bye");
- }
-
- __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
- if (clkc & CLKC_P0)
- __res_bus_clock_speed_HZ >>= 1;
-
- if (verbose) {
- printk("CLKIN: %lu.%3.3luMHz\n",
- __clkin_clock_speed_HZ / 1000000,
- (__clkin_clock_speed_HZ / 1000) % 1000);
-
- printk("CLKS:"
- " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
- __ext_bus_clock_speed_HZ / 1000000,
- __res_bus_clock_speed_HZ / 1000000,
- __sdram_clock_speed_HZ / 1000000,
- __core_bus_clock_speed_HZ / 1000000,
- __core_clock_speed_HZ / 1000000,
- __dsu_clock_speed_HZ / 1000000
- );
- }
-
- /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
- __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
-
- /* set the serial prescaler */
- __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
- quot = 1;
- while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
- quot += 1;
-
- /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
- * - we have to be careful - dividing too much can mean we can't get 115200 baud
- */
- if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
- quot <<= 1;
-
- __serial_clock_speed_HZ /= quot;
- __frv_uart0.uartclk = __serial_clock_speed_HZ;
- __frv_uart1.uartclk = __serial_clock_speed_HZ;
-
- if (verbose)
- printk(" uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
-
- while (!(__get_UART0_LSR() & UART_LSR_TEMT))
- continue;
-
- while (!(__get_UART1_LSR() & UART_LSR_TEMT))
- continue;
-
- __set_UCPVR(quot);
- __set_UCPSR(0);
-} /* end determine_clocks() */
-
-/*****************************************************************************/
-/*
- * reserve some DMA consistent memory
- */
-#ifdef CONFIG_RESERVE_DMA_COHERENT
-static void __init reserve_dma_coherent(void)
-{
- unsigned long ampr;
-
- /* find the first non-kernel memory tile and steal it */
-#define __steal_AMPR(r) \
- if (__get_DAMPR(r) & xAMPRx_V) { \
- ampr = __get_DAMPR(r); \
- __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \
- __set_IAMPR(r, 0); \
- goto found; \
- }
-
- __steal_AMPR(1);
- __steal_AMPR(2);
- __steal_AMPR(3);
- __steal_AMPR(4);
- __steal_AMPR(5);
- __steal_AMPR(6);
-
- if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
- __steal_AMPR(7);
- __steal_AMPR(8);
- __steal_AMPR(9);
- __steal_AMPR(10);
- __steal_AMPR(11);
- __steal_AMPR(12);
- __steal_AMPR(13);
- __steal_AMPR(14);
- }
-
- /* unable to grant any DMA consistent memory */
- printk("No DMA consistent memory reserved\n");
- return;
-
- found:
- dma_coherent_mem_start = ampr & xAMPRx_PPFN;
- ampr &= xAMPRx_SS;
- ampr >>= 4;
- ampr = 1 << (ampr - 3 + 20);
- dma_coherent_mem_end = dma_coherent_mem_start + ampr;
-
- printk("DMA consistent memory reserved %lx-%lx\n",
- dma_coherent_mem_start, dma_coherent_mem_end);
-
-} /* end reserve_dma_coherent() */
-#endif
-
-/*****************************************************************************/
-/*
- * calibrate the delay loop
- */
-void calibrate_delay(void)
-{
- loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
-
- printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
- loops_per_jiffy / (500000 / HZ),
- (loops_per_jiffy / (5000 / HZ)) % 100);
-
-} /* end calibrate_delay() */
-
-/*****************************************************************************/
-/*
- * look through the command line for some things we need to know immediately
- */
-static void __init parse_cmdline_early(char *cmdline)
-{
- if (!cmdline)
- return;
-
- while (*cmdline) {
- if (*cmdline == ' ')
- cmdline++;
-
- /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
- * out from the SDRAM controller mask register
- */
- if (!strncmp(cmdline, "mem=", 4)) {
- unsigned long long mem_size;
-
- mem_size = memparse(cmdline + 4, &cmdline);
- memory_end = memory_start + mem_size;
- }
-
- while (*cmdline && *cmdline != ' ')
- cmdline++;
- }
-
-} /* end parse_cmdline_early() */
-
-/*****************************************************************************/
-/*
- *
- */
-void __init setup_arch(char **cmdline_p)
-{
-#ifdef CONFIG_MMU
- printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
-#else
- printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
-#endif
-
- memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
-
- determine_cpu();
- determine_clocks(1);
-
- /* For printk-directly-beats-on-serial-hardware hack */
- console_set_baud(115200);
-#ifdef CONFIG_GDBSTUB
- gdbstub_set_baud(115200);
-#endif
-
-#ifdef CONFIG_RESERVE_DMA_COHERENT
- reserve_dma_coherent();
-#endif
- dump_memory_map();
-
-#ifdef CONFIG_MB93090_MB00
- if (mb93090_mb00_detected)
- mb93090_display();
-#endif
-
- /* register those serial ports that are available */
-#ifdef CONFIG_FRV_ONCPU_SERIAL
-#ifndef CONFIG_GDBSTUB_UART0
- __reg(UART0_BASE + UART_IER * 8) = 0;
- early_serial_setup(&__frv_uart0);
-#endif
-#ifndef CONFIG_GDBSTUB_UART1
- __reg(UART1_BASE + UART_IER * 8) = 0;
- early_serial_setup(&__frv_uart1);
-#endif
-#endif
-
- /* deal with the command line - RedBoot may have passed one to the kernel */
- memcpy(command_line, boot_command_line, sizeof(command_line));
- *cmdline_p = &command_line[0];
- parse_cmdline_early(command_line);
-
- /* set up the memory description
- * - by now the stack is part of the init task */
- printk("Memory %08lx-%08lx\n", memory_start, memory_end);
-
- BUG_ON(memory_start == memory_end);
-
- init_mm.start_code = (unsigned long) _stext;
- init_mm.end_code = (unsigned long) _etext;
- init_mm.end_data = (unsigned long) _edata;
-#if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
- init_mm.brk = (unsigned long) &_end;
-#else
- init_mm.brk = (unsigned long) 0;
-#endif
-
-#ifdef DEBUG
- printk("KERNEL -> TEXT=0x%p-0x%p DATA=0x%p-0x%p BSS=0x%p-0x%p\n",
- _stext, _etext, _sdata, _edata, __bss_start, __bss_stop);
-#endif
-
-#ifdef CONFIG_VT
-#if defined(CONFIG_VGA_CONSOLE)
- conswitchp = &vga_con;
-#elif defined(CONFIG_DUMMY_CONSOLE)
- conswitchp = &dummy_con;
-#endif
-#endif
-
-#ifdef CONFIG_MMU
- setup_linux_memory();
-#else
- setup_uclinux_memory();
-#endif
-
- /* get kmalloc into gear */
- paging_init();
-
- /* init DMA */
- frv_dma_init();
-#ifdef DEBUG
- printk("Done setup_arch\n");
-#endif
-
- /* start the decrement timer running */
-// asm volatile("movgs %0,timerd" :: "r"(10000000));
-// __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
-
-} /* end setup_arch() */
-
-#if 0
-/*****************************************************************************/
-/*
- *
- */
-static int setup_arch_serial(void)
-{
- /* register those serial ports that are available */
-#ifndef CONFIG_GDBSTUB_UART0
- early_serial_setup(&__frv_uart0);
-#endif
-#ifndef CONFIG_GDBSTUB_UART1
- early_serial_setup(&__frv_uart1);
-#endif
-
- return 0;
-} /* end setup_arch_serial() */
-
-late_initcall(setup_arch_serial);
-#endif
-
-/*****************************************************************************/
-/*
- * set up the memory map for normal MMU linux
- */
-#ifdef CONFIG_MMU
-static void __init setup_linux_memory(void)
-{
- unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
- unsigned long physpages;
-
- kstart = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
- kend = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
-
- kstart = kstart & PAGE_MASK;
- kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
-
- /* give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map immediately following the kernel image
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- kend >> PAGE_SHIFT, /* map addr */
- memory_start >> PAGE_SHIFT, /* start of RAM */
- memory_end >> PAGE_SHIFT /* end of RAM */
- );
-
- /* pass the memory that the kernel can immediately use over to the bootmem allocator */
- max_mapnr = physpages = (memory_end - memory_start) >> PAGE_SHIFT;
- low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
- high_mem = 0;
-
- if (physpages > low_top_pfn) {
-#ifdef CONFIG_HIGHMEM
- high_mem = physpages - low_top_pfn;
-#else
- max_mapnr = physpages = low_top_pfn;
-#endif
- }
- else {
- low_top_pfn = physpages;
- }
-
- min_low_pfn = memory_start >> PAGE_SHIFT;
- max_low_pfn = low_top_pfn;
- max_pfn = memory_end >> PAGE_SHIFT;
-
- num_mappedpages = low_top_pfn;
-
- printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
-
- free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
-
-#ifdef CONFIG_HIGHMEM
- if (high_mem)
- printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
-#endif
-
- /* take back the memory occupied by the kernel image and the bootmem alloc map */
- reserve_bootmem(kstart, kend - kstart + bootmap_size,
- BOOTMEM_DEFAULT);
-
- /* reserve the memory occupied by the initial ramdisk */
-#ifdef CONFIG_BLK_DEV_INITRD
- if (LOADER_TYPE && INITRD_START) {
- if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
- reserve_bootmem(INITRD_START, INITRD_SIZE,
- BOOTMEM_DEFAULT);
- initrd_start = INITRD_START + PAGE_OFFSET;
- initrd_end = initrd_start + INITRD_SIZE;
- }
- else {
- printk(KERN_ERR
- "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
- "disabling initrd\n",
- INITRD_START + INITRD_SIZE,
- low_top_pfn << PAGE_SHIFT);
- initrd_start = 0;
- }
- }
-#endif
-
-} /* end setup_linux_memory() */
-#endif
-
-/*****************************************************************************/
-/*
- * set up the memory map for uClinux
- */
-#ifndef CONFIG_MMU
-static void __init setup_uclinux_memory(void)
-{
-#ifdef CONFIG_PROTECT_KERNEL
- unsigned long dampr;
-#endif
- unsigned long kend;
- int bootmap_size;
-
- kend = (unsigned long) &__kernel_image_end;
- kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
-
- /* give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map immediately following the kernel image
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0),
- kend >> PAGE_SHIFT, /* map addr */
- memory_start >> PAGE_SHIFT, /* start of RAM */
- memory_end >> PAGE_SHIFT /* end of RAM */
- );
-
- /* free all the usable memory */
- free_bootmem(memory_start, memory_end - memory_start);
-
- high_memory = (void *) (memory_end & PAGE_MASK);
- max_mapnr = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
-
- min_low_pfn = memory_start >> PAGE_SHIFT;
- max_low_pfn = memory_end >> PAGE_SHIFT;
- max_pfn = max_low_pfn;
-
- /* now take back the bits the core kernel is occupying */
-#ifndef CONFIG_PROTECT_KERNEL
- reserve_bootmem(kend, bootmap_size, BOOTMEM_DEFAULT);
- reserve_bootmem((unsigned long) &__kernel_image_start,
- kend - (unsigned long) &__kernel_image_start,
- BOOTMEM_DEFAULT);
-
-#else
- dampr = __get_DAMPR(0);
- dampr &= xAMPRx_SS;
- dampr = (dampr >> 4) + 17;
- dampr = 1 << dampr;
-
- reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr, BOOTMEM_DEFAULT);
-#endif
-
- /* reserve some memory to do uncached DMA through if requested */
-#ifdef CONFIG_RESERVE_DMA_COHERENT
- if (dma_coherent_mem_start)
- reserve_bootmem(dma_coherent_mem_start,
- dma_coherent_mem_end - dma_coherent_mem_start,
- BOOTMEM_DEFAULT);
-#endif
-
-} /* end setup_uclinux_memory() */
-#endif
-
-/*****************************************************************************/
-/*
- * get CPU information for use by procfs
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
-#ifdef CONFIG_PM
- const char *sep;
-#endif
-
- gr = cpu_hsr0_all & HSR0_GRHE ? "gr0-63" : "gr0-31";
- fr = cpu_hsr0_all & HSR0_FRHE ? "fr0-63" : "fr0-31";
- fm = cpu_psr_all & PSR_EM ? ", Media" : "";
- fp = cpu_psr_all & PSR_EF ? ", FPU" : "";
- cm = cpu_psr_all & PSR_CM ? ", CCCR" : "";
- nem = cpu_psr_all & PSR_NEM ? ", NE" : "";
- ble = cpu_psr_all & PSR_BE ? "BE" : "LE";
-
- seq_printf(m,
- "CPU-Series:\t%s\n"
- "CPU-Core:\t%s, %s, %s%s%s\n"
- "CPU:\t\t%s\n"
- "MMU:\t\t%s\n"
- "FP-Media:\t%s%s%s\n"
- "System:\t\t%s",
- cpu_series,
- cpu_core, gr, ble, cm, nem,
- cpu_silicon,
- cpu_mmu,
- fr, fm, fp,
- cpu_system);
-
- if (cpu_board1)
- seq_printf(m, ", %s", cpu_board1);
-
- if (cpu_board2)
- seq_printf(m, ", %s", cpu_board2);
-
- seq_printf(m, "\n");
-
-#ifdef CONFIG_PM
- seq_printf(m, "PM-Controls:");
- sep = "\t";
-
- if (clock_bits_settable & CLOCK_BIT_CMODE) {
- seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
- sep = ", ";
- }
-
- if (clock_bits_settable & CLOCK_BIT_CM) {
- seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
- sep = ", ";
- }
-
- if (clock_bits_settable & CLOCK_BIT_P0) {
- seq_printf(m, "%sp0=0x3", sep);
- sep = ", ";
- }
-
- seq_printf(m, "%ssuspend=0x22\n", sep);
-#endif
-
- seq_printf(m,
- "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
- clock_cmode_current, clock_cm_current, clock_p0_current);
-
-#define print_clk(TAG, VAR) \
- seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
-
- print_clk("In", __clkin_clock_speed_HZ);
- print_clk("Core", __core_clock_speed_HZ);
- print_clk("SDRAM", __sdram_clock_speed_HZ);
- print_clk("CBus", __core_bus_clock_speed_HZ);
- print_clk("Res", __res_bus_clock_speed_HZ);
- print_clk("Ext", __ext_bus_clock_speed_HZ);
- print_clk("DSU", __dsu_clock_speed_HZ);
-
- seq_printf(m,
- "BogoMips:\t%lu.%02lu\n",
- (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
-
- return 0;
-} /* end show_cpuinfo() */
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-void arch_gettod(int *year, int *mon, int *day, int *hour,
- int *min, int *sec)
-{
- *year = *mon = *day = *hour = *min = *sec = 0;
-}
-
-/*****************************************************************************/
-/*
- *
- */
-#ifdef CONFIG_MB93090_MB00
-static void __init mb93090_sendlcdcmd(uint32_t cmd)
-{
- unsigned long base = __addr_LCD();
- int loop;
-
- /* request reading of the busy flag */
- __set_LCD(base, LCD_CMD_READ_BUSY);
- __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
-
- /* wait for the busy flag to become clear */
- for (loop = 10000; loop > 0; loop--)
- if (!(__get_LCD(base) & 0x80))
- break;
-
- /* send the command */
- __set_LCD(base, cmd);
- __set_LCD(base, cmd & ~LCD_E);
-
-} /* end mb93090_sendlcdcmd() */
-
-/*****************************************************************************/
-/*
- * write to the MB93090 LEDs and LCD
- */
-static void __init mb93090_display(void)
-{
- const char *p;
-
- __set_LEDS(0);
-
- /* set up the LCD */
- mb93090_sendlcdcmd(LCD_CMD_CLEAR);
- mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
- mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
- mb93090_sendlcdcmd(LCD_CMD_HOME);
-
- mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
- for (p = mb93090_banner; *p; p++)
- mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
-
- mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
- for (p = mb93090_version; *p; p++)
- mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
-
-} /* end mb93090_display() */
-
-#endif // CONFIG_MB93090_MB00
diff --git a/arch/frv/kernel/signal.c b/arch/frv/kernel/signal.c
deleted file mode 100644
index bf6e07a7a1b1..000000000000
--- a/arch/frv/kernel/signal.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/* signal.c: FRV specific bits of signal handling
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/signal.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/personality.h>
-#include <linux/tracehook.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-#include <asm/cacheflush.h>
-
-#define DEBUG_SIG 0
-
-struct fdpic_func_descriptor {
- unsigned long text;
- unsigned long GOT;
-};
-
-/*
- * Do a signal return; undo the signal stack.
- */
-
-struct sigframe
-{
- __sigrestore_t pretcode;
- int sig;
- struct sigcontext sc;
- unsigned long extramask[_NSIG_WORDS-1];
- uint32_t retcode[2];
-};
-
-struct rt_sigframe
-{
- __sigrestore_t pretcode;
- int sig;
- struct siginfo __user *pinfo;
- void __user *puc;
- struct siginfo info;
- struct ucontext uc;
- uint32_t retcode[2];
-};
-
-static int restore_sigcontext(struct sigcontext __user *sc, int *_gr8)
-{
- struct user_context *user = current->thread.user;
- unsigned long tbr, psr;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- tbr = user->i.tbr;
- psr = user->i.psr;
- if (copy_from_user(user, &sc->sc_context, sizeof(sc->sc_context)))
- goto badframe;
- user->i.tbr = tbr;
- user->i.psr = psr;
-
- restore_user_regs(user);
-
- user->i.syscallno = -1; /* disable syscall checks */
-
- *_gr8 = user->i.gr[8];
- return 0;
-
- badframe:
- return 1;
-}
-
-asmlinkage int sys_sigreturn(void)
-{
- struct sigframe __user *frame = (struct sigframe __user *) __frame->sp;
- sigset_t set;
- int gr8;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__get_user(set.sig[0], &frame->sc.sc_oldmask))
- goto badframe;
-
- if (_NSIG_WORDS > 1 &&
- __copy_from_user(&set.sig[1], &frame->extramask, sizeof(frame->extramask)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(&frame->sc, &gr8))
- goto badframe;
- return gr8;
-
- badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-asmlinkage int sys_rt_sigreturn(void)
-{
- struct rt_sigframe __user *frame = (struct rt_sigframe __user *) __frame->sp;
- sigset_t set;
- int gr8;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(&frame->uc.uc_mcontext, &gr8))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return gr8;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/*
- * Set up a signal frame
- */
-static int setup_sigcontext(struct sigcontext __user *sc, unsigned long mask)
-{
- save_user_regs(current->thread.user);
-
- if (copy_to_user(&sc->sc_context, current->thread.user, sizeof(sc->sc_context)) != 0)
- goto badframe;
-
- /* non-iBCS2 extensions.. */
- if (__put_user(mask, &sc->sc_oldmask) < 0)
- goto badframe;
-
- return 0;
-
- badframe:
- return 1;
-}
-
-/*****************************************************************************/
-/*
- * Determine which stack to use..
- */
-static inline void __user *get_sigframe(struct ksignal *ksig,
- size_t frame_size)
-{
- unsigned long sp = sigsp(__frame->sp, ksig);
-
- return (void __user *) ((sp - frame_size) & ~7UL);
-
-} /* end get_sigframe() */
-
-/*****************************************************************************/
-/*
- *
- */
-static int setup_frame(struct ksignal *ksig, sigset_t *set)
-{
- struct sigframe __user *frame;
- int sig = ksig->sig;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- if (__put_user(sig, &frame->sig) < 0)
- return -EFAULT;
-
- if (setup_sigcontext(&frame->sc, set->sig[0]))
- return -EFAULT;
-
- if (_NSIG_WORDS > 1) {
- if (__copy_to_user(frame->extramask, &set->sig[1],
- sizeof(frame->extramask)))
- return -EFAULT;
- }
-
- /* Set up to return from userspace. If provided, use a stub
- * already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode) < 0)
- return -EFAULT;
- }
- else {
- /* Set up the following code on the stack:
- * setlos #__NR_sigreturn,gr7
- * tira gr0,0
- */
- if (__put_user((__sigrestore_t)frame->retcode, &frame->pretcode) ||
- __put_user(0x8efc0000|__NR_sigreturn, &frame->retcode[0]) ||
- __put_user(0xc0700000, &frame->retcode[1]))
- return -EFAULT;
-
- flush_icache_range((unsigned long) frame->retcode,
- (unsigned long) (frame->retcode + 2));
- }
-
- /* Set up registers for the signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor __user *) ksig->ka.sa.sa_handler;
- struct fdpic_func_descriptor desc;
- if (copy_from_user(&desc, funcptr, sizeof(desc)))
- return -EFAULT;
- __frame->pc = desc.text;
- __frame->gr15 = desc.GOT;
- } else {
- __frame->pc = (unsigned long) ksig->ka.sa.sa_handler;
- __frame->gr15 = 0;
- }
-
- __frame->sp = (unsigned long) frame;
- __frame->lr = (unsigned long) &frame->retcode;
- __frame->gr8 = sig;
-
-#if DEBUG_SIG
- printk("SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
- sig, current->comm, current->pid, frame, __frame->pc,
- frame->pretcode);
-#endif
-
- return 0;
-} /* end setup_frame() */
-
-/*****************************************************************************/
-/*
- *
- */
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set)
-{
- struct rt_sigframe __user *frame;
- int sig = ksig->sig;
-
- frame = get_sigframe(ksig, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- if (__put_user(sig, &frame->sig) ||
- __put_user(&frame->info, &frame->pinfo) ||
- __put_user(&frame->uc, &frame->puc))
- return -EFAULT;
-
- if (copy_siginfo_to_user(&frame->info, &ksig->info))
- return -EFAULT;
-
- /* Create the ucontext. */
- if (__put_user(0, &frame->uc.uc_flags) ||
- __put_user(NULL, &frame->uc.uc_link) ||
- __save_altstack(&frame->uc.uc_stack, __frame->sp))
- return -EFAULT;
-
- if (setup_sigcontext(&frame->uc.uc_mcontext, set->sig[0]))
- return -EFAULT;
-
- if (__copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)))
- return -EFAULT;
-
- /* Set up to return from userspace. If provided, use a stub
- * already in userspace. */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode))
- return -EFAULT;
- }
- else {
- /* Set up the following code on the stack:
- * setlos #__NR_sigreturn,gr7
- * tira gr0,0
- */
- if (__put_user((__sigrestore_t)frame->retcode, &frame->pretcode) ||
- __put_user(0x8efc0000|__NR_rt_sigreturn, &frame->retcode[0]) ||
- __put_user(0xc0700000, &frame->retcode[1]))
- return -EFAULT;
-
- flush_icache_range((unsigned long) frame->retcode,
- (unsigned long) (frame->retcode + 2));
- }
-
- /* Set up registers for signal handler */
- if (current->personality & FDPIC_FUNCPTRS) {
- struct fdpic_func_descriptor __user *funcptr =
- (struct fdpic_func_descriptor __user *) ksig->ka.sa.sa_handler;
- struct fdpic_func_descriptor desc;
- if (copy_from_user(&desc, funcptr, sizeof(desc)))
- return -EFAULT;
- __frame->pc = desc.text;
- __frame->gr15 = desc.GOT;
- } else {
- __frame->pc = (unsigned long) ksig->ka.sa.sa_handler;
- __frame->gr15 = 0;
- }
-
- __frame->sp = (unsigned long) frame;
- __frame->lr = (unsigned long) &frame->retcode;
- __frame->gr8 = sig;
- __frame->gr9 = (unsigned long) &frame->info;
-
-#if DEBUG_SIG
- printk("SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
- sig, current->comm, current->pid, frame, __frame->pc,
- frame->pretcode);
-#endif
- return 0;
-
-} /* end setup_rt_frame() */
-
-/*****************************************************************************/
-/*
- * OK, we're invoking a handler
- */
-static void handle_signal(struct ksignal *ksig)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Are we from a system call? */
- if (__frame->syscallno != -1) {
- /* If so, check system call restarting.. */
- switch (__frame->gr8) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- __frame->gr8 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- __frame->gr8 = -EINTR;
- break;
- }
-
- /* fallthrough */
- case -ERESTARTNOINTR:
- __frame->gr8 = __frame->orig_gr8;
- __frame->pc -= 4;
- }
- __frame->syscallno = -1;
- }
-
- /* Set up the stack frame */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO)
- ret = setup_rt_frame(ksig, oldset);
- else
- ret = setup_frame(ksig, oldset);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-} /* end handle_signal() */
-
-/*****************************************************************************/
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- */
-static void do_signal(void)
-{
- struct ksignal ksig;
-
- if (get_signal(&ksig)) {
- handle_signal(&ksig);
- return;
- }
-
- /* Did we come from a system call? */
- if (__frame->syscallno != -1) {
- /* Restart the system call - no handlers present */
- switch (__frame->gr8) {
- case -ERESTARTNOHAND:
- case -ERESTARTSYS:
- case -ERESTARTNOINTR:
- __frame->gr8 = __frame->orig_gr8;
- __frame->pc -= 4;
- break;
-
- case -ERESTART_RESTARTBLOCK:
- __frame->gr7 = __NR_restart_syscall;
- __frame->pc -= 4;
- break;
- }
- __frame->syscallno = -1;
- }
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-} /* end do_signal() */
-
-/*****************************************************************************/
-/*
- * notification of userspace execution resumption
- * - triggered by the TIF_WORK_MASK flags
- */
-asmlinkage void do_notify_resume(__u32 thread_info_flags)
-{
- /* pending single-step? */
- if (thread_info_flags & _TIF_SINGLESTEP)
- clear_thread_flag(TIF_SINGLESTEP);
-
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal();
-
- /* deal with notification on about to resume userspace execution */
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(__frame);
- }
-
-} /* end do_notify_resume() */
diff --git a/arch/frv/kernel/sleep.S b/arch/frv/kernel/sleep.S
deleted file mode 100644
index f67bf73cd2cc..000000000000
--- a/arch/frv/kernel/sleep.S
+++ /dev/null
@@ -1,373 +0,0 @@
-/* sleep.S: power saving mode entry
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Woodhouse (dwmw2@infradead.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <asm/spr-regs.h>
-
-#define __addr_MASK 0xfeff9820 /* interrupt controller mask */
-
-#define __addr_FR55X_DRCN 0xfeff0218 /* Address of DRCN register */
-#define FR55X_DSTS_OFFSET -4 /* Offset from DRCN to DSTS */
-#define FR55X_SDRAMC_DSTS_SSI 0x00000002 /* indicates that the SDRAM is in self-refresh mode */
-
-#define __addr_FR4XX_DRCN 0xfe000430 /* Address of DRCN register */
-#define FR4XX_DSTS_OFFSET -8 /* Offset from DRCN to DSTS */
-#define FR4XX_SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
-
-#define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
-
- .section .bss
- .balign 8
- .globl __sleep_save_area
-__sleep_save_area:
- .space 16
-
-
- .text
- .balign 4
-
-.macro li v r
- sethi.p %hi(\v),\r
- setlo %lo(\v),\r
-.endm
-
-#ifdef CONFIG_PM
-###############################################################################
-#
-# CPU suspension routine
-# - void frv_cpu_suspend(unsigned long pdm_mode)
-#
-###############################################################################
- .globl frv_cpu_suspend
- .type frv_cpu_suspend,@function
-frv_cpu_suspend:
-
- #----------------------------------------------------
- # save hsr0, psr, isr, and lr for resume code
- #----------------------------------------------------
- li __sleep_save_area,gr11
-
- movsg hsr0,gr4
- movsg psr,gr5
- movsg isr,gr6
- movsg lr,gr7
- stdi gr4,@(gr11,#0)
- stdi gr6,@(gr11,#8)
-
- # store the return address from sleep in GR14, and its complement in GR13 as a check
- li __ramboot_resume,gr14
-#ifdef CONFIG_MMU
- # Resume via RAMBOOT# will turn MMU off, so bootloader needs a physical address.
- sethi.p %hi(__page_offset),gr13
- setlo %lo(__page_offset),gr13
- sub gr14,gr13,gr14
-#endif
- not gr14,gr13
-
- #----------------------------------------------------
- # preload and lock into icache that code which may have to run
- # when dram is in self-refresh state.
- #----------------------------------------------------
- movsg hsr0, gr3
- li HSR0_ICE,gr4
- or gr3,gr4,gr3
- movgs gr3,hsr0
- or gr3,gr8,gr7 // add the sleep bits for later
-
- li #__icache_lock_start,gr3
- li #__icache_lock_end,gr4
-1: icpl gr3,gr0,#1
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- # disable exceptions
- movsg psr,gr8
- andi.p gr8,#~PSR_PIL,gr8
- andi gr8,~PSR_ET,gr8
- movgs gr8,psr
- ori gr8,#PSR_ET,gr8
-
- srli gr8,#28,gr4
- subicc gr4,#3,gr0,icc0
- beq icc0,#0,1f
- # FR4xx
- li __addr_FR4XX_DRCN,gr4
- li FR4XX_SDRAMC_DSTS_SSI,gr5
- li FR4XX_DSTS_OFFSET,gr6
- bra __icache_lock_start
-1:
- # FR5xx
- li __addr_FR55X_DRCN,gr4
- li FR55X_SDRAMC_DSTS_SSI,gr5
- li FR55X_DSTS_OFFSET,gr6
- bra __icache_lock_start
-
- .size frv_cpu_suspend, .-frv_cpu_suspend
-
-#
-# the final part of the sleep sequence...
-# - we want it to be be cacheline aligned so we can lock it into the icache easily
-# On entry: gr7 holds desired hsr0 sleep value
-# gr8 holds desired psr sleep value
-#
- .balign L1_CACHE_BYTES
- .type __icache_lock_start,@function
-__icache_lock_start:
-
- #----------------------------------------------------
- # put SDRAM in self-refresh mode
- #----------------------------------------------------
-
- # Flush all data in the cache using the DCEF instruction.
- dcef @(gr0,gr0),#1
-
- # Stop DMAC transfer
-
- # Execute dummy load from SDRAM
- ldi @(gr11,#0),gr11
-
- # put the SDRAM into self-refresh mode
- ld @(gr4,gr0),gr11
- ori gr11,#SDRAMC_DRCN_SR,gr11
- st gr11,@(gr4,gr0)
- membar
-
- # wait for SDRAM to reach self-refresh mode
-1: ld @(gr4,gr6),gr11
- andcc gr11,gr5,gr11,icc0
- beq icc0,#0,1b
-
- # Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
- # Set the clock mode (CLKC register) as required.
- # - At this time, also set the CLKC register P0 bit.
-
- # Set the HSR0 register PDM field.
- movgs gr7,hsr0
-
- # Execute NOP 32 times.
- .rept 32
- nop
- .endr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # Release the interrupt mask setting of the MASK register of the
- # interrupt controller if necessary.
- sti gr10,@(gr9,#0)
- membar
-#endif
-
- # Set the PSR register ET bit to 1 to enable interrupts.
- movgs gr8,psr
-
- ###################################################
- # this is only reached if waking up via interrupt
- ###################################################
-
- # Execute NOP 32 times.
- .rept 32
- nop
- .endr
-
- #----------------------------------------------------
- # wake SDRAM from self-refresh mode
- #----------------------------------------------------
- ld @(gr4,gr0),gr11
- andi gr11,#~SDRAMC_DRCN_SR,gr11
- st gr11,@(gr4,gr0)
- membar
-2:
- ld @(gr4,gr6),gr11 // Wait for it to come back...
- andcc gr11,gr5,gr0,icc0
- bne icc0,0,2b
-
- # wait for the SDRAM to stabilise
- li 0x0100000,gr3
-3: subicc gr3,#1,gr3,icc0
- bne icc0,#0,3b
-
- # now that DRAM is back, this is the end of the code which gets
- # locked in icache.
-__icache_lock_end:
- .size __icache_lock_start, .-__icache_lock_start
-
- # Fall-through to the RAMBOOT# wakeup path
-
-###############################################################################
-#
-# resume from suspend re-entry point reached via RAMBOOT# and bootloader
-#
-###############################################################################
-__ramboot_resume:
-
- #----------------------------------------------------
- # restore hsr0, psr, isr, and leave saved lr in gr7
- #----------------------------------------------------
- li __sleep_save_area,gr11
-#ifdef CONFIG_MMU
- movsg hsr0,gr4
- sethi.p %hi(HSR0_EXMMU),gr3
- setlo %lo(HSR0_EXMMU),gr3
- andcc gr3,gr4,gr0,icc0
- bne icc0,#0,2f
-
- # need to use physical address
- sethi.p %hi(__page_offset),gr3
- setlo %lo(__page_offset),gr3
- sub gr11,gr3,gr11
-
- # flush all tlb entries
- setlos #64,gr4
- setlos.p #PAGE_SIZE,gr5
- setlos #0,gr6
-1:
- tlbpr gr6,gr0,#6,#0
- subicc.p gr4,#1,gr4,icc0
- add gr6,gr5,gr6
- bne icc0,#2,1b
-
- # need a temporary mapping for the current physical address we are
- # using between time MMU is enabled and jump to virtual address is
- # made.
- sethi.p %hi(0x00000000),gr4
- setlo %lo(0x00000000),gr4 ; physical address
- setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_256Mb|xAMPRx_S_KERNEL|xAMPRx_V,gr5
- or gr4,gr5,gr5
-
- movsg cxnr,gr13
- or gr4,gr13,gr4
-
- movgs gr4,iamlr1 ; mapped from real address 0
- movgs gr5,iampr1 ; cached kernel memory at 0x00000000
-2:
-#endif
-
- lddi @(gr11,#0),gr4 ; hsr0, psr
- lddi @(gr11,#8),gr6 ; isr, lr
- movgs gr4,hsr0
- bar
-
-#ifdef CONFIG_MMU
- sethi.p %hi(1f),gr11
- setlo %lo(1f),gr11
- jmpl @(gr11,gr0)
-1:
- movgs gr0,iampr1 ; get rid of temporary mapping
-#endif
- movgs gr5,psr
- movgs gr6,isr
-
- #----------------------------------------------------
- # unlock the icache which was locked before going to sleep
- #----------------------------------------------------
- li __icache_lock_start,gr3
- li __icache_lock_end,gr4
-1: icul gr3
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- #----------------------------------------------------
- # back to business as usual
- #----------------------------------------------------
- jmpl @(gr7,gr0) ;
-
-#endif /* CONFIG_PM */
-
-###############################################################################
-#
-# CPU core sleep mode routine
-#
-###############################################################################
- .globl frv_cpu_core_sleep
- .type frv_cpu_core_sleep,@function
-frv_cpu_core_sleep:
-
- # Preload into icache.
- li #__core_sleep_icache_lock_start,gr3
- li #__core_sleep_icache_lock_end,gr4
-
-1: icpl gr3,gr0,#1
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- bra __core_sleep_icache_lock_start
-
- .balign L1_CACHE_BYTES
-__core_sleep_icache_lock_start:
-
- # (1) Set the PSR register ET bit to 0 to disable interrupts.
- movsg psr,gr8
- andi.p gr8,#~(PSR_PIL),gr8
- andi gr8,#~(PSR_ET),gr4
- movgs gr4,psr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (2) Set '1' to all bits in the MASK register of the interrupt
- # controller and mask interrupts.
- sethi.p %hi(__addr_MASK),gr9
- setlo %lo(__addr_MASK),gr9
- sethi.p %hi(0xffff0000),gr4
- setlo %lo(0xffff0000),gr4
- ldi @(gr9,#0),gr10
- sti gr4,@(gr9,#0)
-#endif
- # (3) Flush all data in the cache using the DCEF instruction.
- dcef @(gr0,gr0),#1
-
- # (4) Execute the memory barrier instruction
- membar
-
- # (5) Set the GPIO register so that the IRQ[3:0] pins become valid, as required.
- # (6) Set the clock mode (CLKC register) as required.
- # - At this time, also set the CLKC register P0 bit.
- # (7) Set the HSR0 register PDM field to 001 .
- movsg hsr0,gr4
- ori gr4,HSR0_PDM_CORE_SLEEP,gr4
- movgs gr4,hsr0
-
- # (8) Execute NOP 32 times.
- .rept 32
- nop
- .endr
-
-#if 0 // Fujitsu recommend to skip this and will update docs.
- # (9) Release the interrupt mask setting of the MASK register of the
- # interrupt controller if necessary.
- sti gr10,@(gr9,#0)
- membar
-#endif
-
- # (10) Set the PSR register ET bit to 1 to enable interrupts.
- movgs gr8,psr
-
-__core_sleep_icache_lock_end:
-
- # Unlock from icache
- li __core_sleep_icache_lock_start,gr3
- li __core_sleep_icache_lock_end,gr4
-1: icul gr3
- addi gr3,#L1_CACHE_BYTES,gr3
- cmp gr4,gr3,icc0
- bhi icc0,#0,1b
-
- bralr
-
- .size frv_cpu_core_sleep, .-frv_cpu_core_sleep
diff --git a/arch/frv/kernel/switch_to.S b/arch/frv/kernel/switch_to.S
deleted file mode 100644
index b06668670fcc..000000000000
--- a/arch/frv/kernel/switch_to.S
+++ /dev/null
@@ -1,489 +0,0 @@
-###############################################################################
-#
-# switch_to.S: context switch operation
-#
-# Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; either version
-# 2 of the License, or (at your option) any later version.
-#
-###############################################################################
-
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/processor.h>
-#include <asm/registers.h>
-#include <asm/spr-regs.h>
-
-.macro LEDS val
- setlos #~\val,gr27
- st gr27,@(gr30,gr0)
- membar
- dcf @(gr30,gr0)
-.endm
-
- .section .sdata
- .balign 8
-
- # address of frame 0 (userspace) on current kernel stack
- .globl __kernel_frame0_ptr
-__kernel_frame0_ptr:
- .long init_thread_union + THREAD_SIZE - FRV_FRAME0_SIZE
-
- # address of current task
- .globl __kernel_current_task
-__kernel_current_task:
- .long init_task
-
- .section .text
- .balign 4
-
-###############################################################################
-#
-# struct task_struct *__switch_to(struct thread_struct *prev_thread,
-# struct thread_struct *next_thread,
-# struct task_struct *prev)
-#
-###############################################################################
- .globl __switch_to
-__switch_to:
- # save outgoing process's context
- sethi.p %hi(__switch_back),gr13
- setlo %lo(__switch_back),gr13
- movsg lr,gr12
-
- stdi gr28,@(gr8,#__THREAD_FRAME)
- sti sp ,@(gr8,#__THREAD_SP)
- sti fp ,@(gr8,#__THREAD_FP)
- stdi gr12,@(gr8,#__THREAD_LR)
- stdi gr16,@(gr8,#__THREAD_GR(16))
- stdi gr18,@(gr8,#__THREAD_GR(18))
- stdi gr20,@(gr8,#__THREAD_GR(20))
- stdi gr22,@(gr8,#__THREAD_GR(22))
- stdi gr24,@(gr8,#__THREAD_GR(24))
- stdi.p gr26,@(gr8,#__THREAD_GR(26))
-
- or gr8,gr8,gr22
- ldi.p @(gr8,#__THREAD_USER),gr8
- call save_user_regs
- or gr22,gr22,gr8
-
- # retrieve the new context
- sethi.p %hi(__kernel_frame0_ptr),gr6
- setlo %lo(__kernel_frame0_ptr),gr6
- movsg psr,gr4
-
- lddi.p @(gr9,#__THREAD_FRAME),gr10
- or gr10,gr10,gr27 ; save prev for the return value
-
- ldi @(gr11,#4),gr19 ; get new_current->thread_info
-
- lddi @(gr9,#__THREAD_SP),gr12
- ldi @(gr9,#__THREAD_LR),gr14
- ldi @(gr9,#__THREAD_PC),gr18
- ldi.p @(gr9,#__THREAD_FRAME0),gr7
-
- # actually switch kernel contexts with ordinary exceptions disabled
- andi gr4,#~PSR_ET,gr5
- movgs gr5,psr
-
- or.p gr10,gr0,gr28 ; set __frame
- or gr11,gr0,gr29 ; set __current
- or.p gr12,gr0,sp
- or gr13,gr0,fp
- or gr19,gr0,gr15 ; set __current_thread_info
-
- sti gr7,@(gr6,#0) ; set __kernel_frame0_ptr
- sti gr29,@(gr6,#4) ; set __kernel_current_task
-
- movgs gr14,lr
- bar
-
- # jump to __switch_back or ret_from_fork as appropriate
- # - move prev to GR8
- movgs gr4,psr
- jmpl.p @(gr18,gr0)
- or gr27,gr27,gr8
-
-###############################################################################
-#
-# restore incoming process's context
-# - on entry:
-# - SP, FP, LR, GR15, GR28 and GR29 will have been set up appropriately
-# - GR8 will point to the outgoing task_struct
-# - GR9 will point to the incoming thread_struct
-#
-###############################################################################
-__switch_back:
- lddi @(gr9,#__THREAD_GR(16)),gr16
- lddi @(gr9,#__THREAD_GR(18)),gr18
- lddi @(gr9,#__THREAD_GR(20)),gr20
- lddi @(gr9,#__THREAD_GR(22)),gr22
- lddi @(gr9,#__THREAD_GR(24)),gr24
- lddi @(gr9,#__THREAD_GR(26)),gr26
-
- # fall through into restore_user_regs()
- ldi.p @(gr9,#__THREAD_USER),gr8
- or gr8,gr8,gr9
-
-###############################################################################
-#
-# restore extra general regs and FP/Media regs
-# - void *restore_user_regs(const struct user_context *target, void *retval)
-# - on entry:
-# - GR8 will point to the user context to swap in
-# - GR9 will contain the value to be returned in GR8 (prev task on context switch)
-#
-###############################################################################
- .globl restore_user_regs
-restore_user_regs:
- movsg hsr0,gr6
- ori gr6,#HSR0_GRHE|HSR0_FRLE|HSR0_FRHE,gr6
- movgs gr6,hsr0
- movsg hsr0,gr6
-
- movsg psr,gr7
- ori gr7,#PSR_EF|PSR_EM,gr7
- movgs gr7,psr
- movsg psr,gr7
- srli gr7,#24,gr7
- bar
-
- lddi @(gr8,#__FPMEDIA_MSR(0)),gr4
-
- movgs gr4,msr0
- movgs gr5,msr1
-
- lddfi @(gr8,#__FPMEDIA_ACC(0)),fr16
- lddfi @(gr8,#__FPMEDIA_ACC(2)),fr18
- ldbfi @(gr8,#__FPMEDIA_ACCG(0)),fr20
- ldbfi @(gr8,#__FPMEDIA_ACCG(1)),fr21
- ldbfi @(gr8,#__FPMEDIA_ACCG(2)),fr22
- ldbfi @(gr8,#__FPMEDIA_ACCG(3)),fr23
-
- mwtacc fr16,acc0
- mwtacc fr17,acc1
- mwtacc fr18,acc2
- mwtacc fr19,acc3
- mwtaccg fr20,accg0
- mwtaccg fr21,accg1
- mwtaccg fr22,accg2
- mwtaccg fr23,accg3
-
- # some CPUs have extra ACCx and ACCGx regs and maybe FSRx regs
- subicc.p gr7,#0x50,gr0,icc0
- subicc gr7,#0x31,gr0,icc1
- beq icc0,#0,__restore_acc_fr451
- beq icc1,#0,__restore_acc_fr555
-__restore_acc_cont:
-
- # some CPU's have GR32-GR63
- setlos #HSR0_FRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__restore_skip_gr32_gr63
-
- lddi @(gr8,#__INT_GR(32)),gr32
- lddi @(gr8,#__INT_GR(34)),gr34
- lddi @(gr8,#__INT_GR(36)),gr36
- lddi @(gr8,#__INT_GR(38)),gr38
- lddi @(gr8,#__INT_GR(40)),gr40
- lddi @(gr8,#__INT_GR(42)),gr42
- lddi @(gr8,#__INT_GR(44)),gr44
- lddi @(gr8,#__INT_GR(46)),gr46
- lddi @(gr8,#__INT_GR(48)),gr48
- lddi @(gr8,#__INT_GR(50)),gr50
- lddi @(gr8,#__INT_GR(52)),gr52
- lddi @(gr8,#__INT_GR(54)),gr54
- lddi @(gr8,#__INT_GR(56)),gr56
- lddi @(gr8,#__INT_GR(58)),gr58
- lddi @(gr8,#__INT_GR(60)),gr60
- lddi @(gr8,#__INT_GR(62)),gr62
-__restore_skip_gr32_gr63:
-
- # all CPU's have FR0-FR31
- lddfi @(gr8,#__FPMEDIA_FR( 0)),fr0
- lddfi @(gr8,#__FPMEDIA_FR( 2)),fr2
- lddfi @(gr8,#__FPMEDIA_FR( 4)),fr4
- lddfi @(gr8,#__FPMEDIA_FR( 6)),fr6
- lddfi @(gr8,#__FPMEDIA_FR( 8)),fr8
- lddfi @(gr8,#__FPMEDIA_FR(10)),fr10
- lddfi @(gr8,#__FPMEDIA_FR(12)),fr12
- lddfi @(gr8,#__FPMEDIA_FR(14)),fr14
- lddfi @(gr8,#__FPMEDIA_FR(16)),fr16
- lddfi @(gr8,#__FPMEDIA_FR(18)),fr18
- lddfi @(gr8,#__FPMEDIA_FR(20)),fr20
- lddfi @(gr8,#__FPMEDIA_FR(22)),fr22
- lddfi @(gr8,#__FPMEDIA_FR(24)),fr24
- lddfi @(gr8,#__FPMEDIA_FR(26)),fr26
- lddfi @(gr8,#__FPMEDIA_FR(28)),fr28
- lddfi.p @(gr8,#__FPMEDIA_FR(30)),fr30
-
- # some CPU's have FR32-FR63
- setlos #HSR0_FRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__restore_skip_fr32_fr63
-
- lddfi @(gr8,#__FPMEDIA_FR(32)),fr32
- lddfi @(gr8,#__FPMEDIA_FR(34)),fr34
- lddfi @(gr8,#__FPMEDIA_FR(36)),fr36
- lddfi @(gr8,#__FPMEDIA_FR(38)),fr38
- lddfi @(gr8,#__FPMEDIA_FR(40)),fr40
- lddfi @(gr8,#__FPMEDIA_FR(42)),fr42
- lddfi @(gr8,#__FPMEDIA_FR(44)),fr44
- lddfi @(gr8,#__FPMEDIA_FR(46)),fr46
- lddfi @(gr8,#__FPMEDIA_FR(48)),fr48
- lddfi @(gr8,#__FPMEDIA_FR(50)),fr50
- lddfi @(gr8,#__FPMEDIA_FR(52)),fr52
- lddfi @(gr8,#__FPMEDIA_FR(54)),fr54
- lddfi @(gr8,#__FPMEDIA_FR(56)),fr56
- lddfi @(gr8,#__FPMEDIA_FR(58)),fr58
- lddfi @(gr8,#__FPMEDIA_FR(60)),fr60
- lddfi @(gr8,#__FPMEDIA_FR(62)),fr62
-__restore_skip_fr32_fr63:
-
- lddi @(gr8,#__FPMEDIA_FNER(0)),gr4
- movsg fner0,gr4
- movsg fner1,gr5
- or.p gr9,gr9,gr8
- bralr
-
- # the FR451 also has ACC8-11/ACCG8-11 regs (but not 4-7...)
-__restore_acc_fr451:
- lddfi @(gr8,#__FPMEDIA_ACC(4)),fr16
- lddfi @(gr8,#__FPMEDIA_ACC(6)),fr18
- ldbfi @(gr8,#__FPMEDIA_ACCG(4)),fr20
- ldbfi @(gr8,#__FPMEDIA_ACCG(5)),fr21
- ldbfi @(gr8,#__FPMEDIA_ACCG(6)),fr22
- ldbfi @(gr8,#__FPMEDIA_ACCG(7)),fr23
-
- mwtacc fr16,acc8
- mwtacc fr17,acc9
- mwtacc fr18,acc10
- mwtacc fr19,acc11
- mwtaccg fr20,accg8
- mwtaccg fr21,accg9
- mwtaccg fr22,accg10
- mwtaccg fr23,accg11
- bra __restore_acc_cont
-
- # the FR555 also has ACC4-7/ACCG4-7 regs and an FSR0 reg
-__restore_acc_fr555:
- lddfi @(gr8,#__FPMEDIA_ACC(4)),fr16
- lddfi @(gr8,#__FPMEDIA_ACC(6)),fr18
- ldbfi @(gr8,#__FPMEDIA_ACCG(4)),fr20
- ldbfi @(gr8,#__FPMEDIA_ACCG(5)),fr21
- ldbfi @(gr8,#__FPMEDIA_ACCG(6)),fr22
- ldbfi @(gr8,#__FPMEDIA_ACCG(7)),fr23
-
- mnop.p
- mwtacc fr16,acc4
- mnop.p
- mwtacc fr17,acc5
- mnop.p
- mwtacc fr18,acc6
- mnop.p
- mwtacc fr19,acc7
- mnop.p
- mwtaccg fr20,accg4
- mnop.p
- mwtaccg fr21,accg5
- mnop.p
- mwtaccg fr22,accg6
- mnop.p
- mwtaccg fr23,accg7
-
- ldi @(gr8,#__FPMEDIA_FSR(0)),gr4
- movgs gr4,fsr0
-
- bra __restore_acc_cont
-
-
-###############################################################################
-#
-# save extra general regs and FP/Media regs
-# - void save_user_regs(struct user_context *target)
-#
-###############################################################################
- .globl save_user_regs
-save_user_regs:
- movsg hsr0,gr6
- ori gr6,#HSR0_GRHE|HSR0_FRLE|HSR0_FRHE,gr6
- movgs gr6,hsr0
- movsg hsr0,gr6
-
- movsg psr,gr7
- ori gr7,#PSR_EF|PSR_EM,gr7
- movgs gr7,psr
- movsg psr,gr7
- srli gr7,#24,gr7
- bar
-
- movsg fner0,gr4
- movsg fner1,gr5
- stdi.p gr4,@(gr8,#__FPMEDIA_FNER(0))
-
- # some CPU's have GR32-GR63
- setlos #HSR0_GRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__save_skip_gr32_gr63
-
- stdi gr32,@(gr8,#__INT_GR(32))
- stdi gr34,@(gr8,#__INT_GR(34))
- stdi gr36,@(gr8,#__INT_GR(36))
- stdi gr38,@(gr8,#__INT_GR(38))
- stdi gr40,@(gr8,#__INT_GR(40))
- stdi gr42,@(gr8,#__INT_GR(42))
- stdi gr44,@(gr8,#__INT_GR(44))
- stdi gr46,@(gr8,#__INT_GR(46))
- stdi gr48,@(gr8,#__INT_GR(48))
- stdi gr50,@(gr8,#__INT_GR(50))
- stdi gr52,@(gr8,#__INT_GR(52))
- stdi gr54,@(gr8,#__INT_GR(54))
- stdi gr56,@(gr8,#__INT_GR(56))
- stdi gr58,@(gr8,#__INT_GR(58))
- stdi gr60,@(gr8,#__INT_GR(60))
- stdi gr62,@(gr8,#__INT_GR(62))
-__save_skip_gr32_gr63:
-
- # all CPU's have FR0-FR31
- stdfi fr0 ,@(gr8,#__FPMEDIA_FR( 0))
- stdfi fr2 ,@(gr8,#__FPMEDIA_FR( 2))
- stdfi fr4 ,@(gr8,#__FPMEDIA_FR( 4))
- stdfi fr6 ,@(gr8,#__FPMEDIA_FR( 6))
- stdfi fr8 ,@(gr8,#__FPMEDIA_FR( 8))
- stdfi fr10,@(gr8,#__FPMEDIA_FR(10))
- stdfi fr12,@(gr8,#__FPMEDIA_FR(12))
- stdfi fr14,@(gr8,#__FPMEDIA_FR(14))
- stdfi fr16,@(gr8,#__FPMEDIA_FR(16))
- stdfi fr18,@(gr8,#__FPMEDIA_FR(18))
- stdfi fr20,@(gr8,#__FPMEDIA_FR(20))
- stdfi fr22,@(gr8,#__FPMEDIA_FR(22))
- stdfi fr24,@(gr8,#__FPMEDIA_FR(24))
- stdfi fr26,@(gr8,#__FPMEDIA_FR(26))
- stdfi fr28,@(gr8,#__FPMEDIA_FR(28))
- stdfi.p fr30,@(gr8,#__FPMEDIA_FR(30))
-
- # some CPU's have FR32-FR63
- setlos #HSR0_FRHE,gr4
- andcc gr6,gr4,gr0,icc0
- beq icc0,#1,__save_skip_fr32_fr63
-
- stdfi fr32,@(gr8,#__FPMEDIA_FR(32))
- stdfi fr34,@(gr8,#__FPMEDIA_FR(34))
- stdfi fr36,@(gr8,#__FPMEDIA_FR(36))
- stdfi fr38,@(gr8,#__FPMEDIA_FR(38))
- stdfi fr40,@(gr8,#__FPMEDIA_FR(40))
- stdfi fr42,@(gr8,#__FPMEDIA_FR(42))
- stdfi fr44,@(gr8,#__FPMEDIA_FR(44))
- stdfi fr46,@(gr8,#__FPMEDIA_FR(46))
- stdfi fr48,@(gr8,#__FPMEDIA_FR(48))
- stdfi fr50,@(gr8,#__FPMEDIA_FR(50))
- stdfi fr52,@(gr8,#__FPMEDIA_FR(52))
- stdfi fr54,@(gr8,#__FPMEDIA_FR(54))
- stdfi fr56,@(gr8,#__FPMEDIA_FR(56))
- stdfi fr58,@(gr8,#__FPMEDIA_FR(58))
- stdfi fr60,@(gr8,#__FPMEDIA_FR(60))
- stdfi fr62,@(gr8,#__FPMEDIA_FR(62))
-__save_skip_fr32_fr63:
-
- mrdacc acc0 ,fr4
- mrdacc acc1 ,fr5
-
- stdfi.p fr4 ,@(gr8,#__FPMEDIA_ACC(0))
-
- mrdacc acc2 ,fr6
- mrdacc acc3 ,fr7
-
- stdfi.p fr6 ,@(gr8,#__FPMEDIA_ACC(2))
-
- mrdaccg accg0,fr4
- stbfi.p fr4 ,@(gr8,#__FPMEDIA_ACCG(0))
-
- mrdaccg accg1,fr5
- stbfi.p fr5 ,@(gr8,#__FPMEDIA_ACCG(1))
-
- mrdaccg accg2,fr6
- stbfi.p fr6 ,@(gr8,#__FPMEDIA_ACCG(2))
-
- mrdaccg accg3,fr7
- stbfi fr7 ,@(gr8,#__FPMEDIA_ACCG(3))
-
- movsg msr0 ,gr4
- movsg msr1 ,gr5
-
- stdi gr4 ,@(gr8,#__FPMEDIA_MSR(0))
-
- # some CPUs have extra ACCx and ACCGx regs and maybe FSRx regs
- subicc.p gr7,#0x50,gr0,icc0
- subicc gr7,#0x31,gr0,icc1
- beq icc0,#0,__save_acc_fr451
- beq icc1,#0,__save_acc_fr555
-__save_acc_cont:
-
- lddfi @(gr8,#__FPMEDIA_FR(4)),fr4
- lddfi.p @(gr8,#__FPMEDIA_FR(6)),fr6
- bralr
-
- # the FR451 also has ACC8-11/ACCG8-11 regs (but not 4-7...)
-__save_acc_fr451:
- mrdacc acc8 ,fr4
- mrdacc acc9 ,fr5
-
- stdfi.p fr4 ,@(gr8,#__FPMEDIA_ACC(4))
-
- mrdacc acc10,fr6
- mrdacc acc11,fr7
-
- stdfi.p fr6 ,@(gr8,#__FPMEDIA_ACC(6))
-
- mrdaccg accg8,fr4
- stbfi.p fr4 ,@(gr8,#__FPMEDIA_ACCG(4))
-
- mrdaccg accg9,fr5
- stbfi.p fr5 ,@(gr8,#__FPMEDIA_ACCG(5))
-
- mrdaccg accg10,fr6
- stbfi.p fr6 ,@(gr8,#__FPMEDIA_ACCG(6))
-
- mrdaccg accg11,fr7
- stbfi fr7 ,@(gr8,#__FPMEDIA_ACCG(7))
- bra __save_acc_cont
-
- # the FR555 also has ACC4-7/ACCG4-7 regs and an FSR0 reg
-__save_acc_fr555:
- mnop.p
- mrdacc acc4 ,fr4
- mnop.p
- mrdacc acc5 ,fr5
-
- stdfi fr4 ,@(gr8,#__FPMEDIA_ACC(4))
-
- mnop.p
- mrdacc acc6 ,fr6
- mnop.p
- mrdacc acc7 ,fr7
-
- stdfi fr6 ,@(gr8,#__FPMEDIA_ACC(6))
-
- mnop.p
- mrdaccg accg4,fr4
- stbfi fr4 ,@(gr8,#__FPMEDIA_ACCG(4))
-
- mnop.p
- mrdaccg accg5,fr5
- stbfi fr5 ,@(gr8,#__FPMEDIA_ACCG(5))
-
- mnop.p
- mrdaccg accg6,fr6
- stbfi fr6 ,@(gr8,#__FPMEDIA_ACCG(6))
-
- mnop.p
- mrdaccg accg7,fr7
- stbfi fr7 ,@(gr8,#__FPMEDIA_ACCG(7))
-
- movsg fsr0 ,gr4
- sti gr4 ,@(gr8,#__FPMEDIA_FSR(0))
- bra __save_acc_cont
diff --git a/arch/frv/kernel/sys_frv.c b/arch/frv/kernel/sys_frv.c
deleted file mode 100644
index f80cc8b9bd45..000000000000
--- a/arch/frv/kernel/sys_frv.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* sys_frv.c: FRV arch-specific syscall wrappers
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/sys_m68k.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/syscalls.h>
-#include <linux/ipc.h>
-
-#include <asm/setup.h>
-#include <linux/uaccess.h>
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
- unsigned long prot, unsigned long flags,
- unsigned long fd, unsigned long pgoff)
-{
- /* As with sparc32, make sure the shift for mmap2 is constant
- (12), no matter what PAGE_SIZE we have.... */
-
- /* But unlike sparc32, don't just silently break if we're
- trying to map something we can't */
- if (pgoff & ((1 << (PAGE_SHIFT - 12)) - 1))
- return -EINVAL;
-
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- pgoff >> (PAGE_SHIFT - 12));
-}
diff --git a/arch/frv/kernel/sysctl.c b/arch/frv/kernel/sysctl.c
deleted file mode 100644
index b54a64971cf1..000000000000
--- a/arch/frv/kernel/sysctl.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* sysctl.c: implementation of /proc/sys files relating to FRV specifically
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sysctl.h>
-#include <linux/proc_fs.h>
-#include <linux/init.h>
-#include <linux/uaccess.h>
-
-static const char frv_cache_wback[] = "wback";
-static const char frv_cache_wthru[] = "wthru";
-
-static void frv_change_dcache_mode(unsigned long newmode)
-{
- unsigned long flags, hsr0;
-
- local_irq_save(flags);
-
- hsr0 = __get_HSR(0);
- hsr0 &= ~HSR0_DCE;
- __set_HSR(0, hsr0);
-
- asm volatile(" dcef @(gr0,gr0),#1 \n"
- " membar \n"
- : : : "memory"
- );
-
- hsr0 = (hsr0 & ~HSR0_CBM) | newmode;
- __set_HSR(0, hsr0);
- hsr0 |= HSR0_DCE;
- __set_HSR(0, hsr0);
-
- local_irq_restore(flags);
-
- //printk("HSR0 now %08lx\n", hsr0);
-}
-
-/*****************************************************************************/
-/*
- * handle requests to dynamically switch the write caching mode delivered by /proc
- */
-static int procctl_frv_cachemode(struct ctl_table *table, int write,
- void __user *buffer, size_t *lenp,
- loff_t *ppos)
-{
- unsigned long hsr0;
- char buff[8];
- int len;
-
- len = *lenp;
-
- if (write) {
- /* potential state change */
- if (len <= 1 || len > sizeof(buff) - 1)
- return -EINVAL;
-
- if (copy_from_user(buff, buffer, len) != 0)
- return -EFAULT;
-
- if (buff[len - 1] == '\n')
- buff[len - 1] = '\0';
- else
- buff[len] = '\0';
-
- if (strcmp(buff, frv_cache_wback) == 0) {
- /* switch dcache into write-back mode */
- frv_change_dcache_mode(HSR0_CBM_COPY_BACK);
- return 0;
- }
-
- if (strcmp(buff, frv_cache_wthru) == 0) {
- /* switch dcache into write-through mode */
- frv_change_dcache_mode(HSR0_CBM_WRITE_THRU);
- return 0;
- }
-
- return -EINVAL;
- }
-
- /* read the state */
- if (*ppos > 0) {
- *lenp = 0;
- return 0;
- }
-
- hsr0 = __get_HSR(0);
- switch (hsr0 & HSR0_CBM) {
- case HSR0_CBM_WRITE_THRU:
- memcpy(buff, frv_cache_wthru, sizeof(frv_cache_wthru) - 1);
- buff[sizeof(frv_cache_wthru) - 1] = '\n';
- len = sizeof(frv_cache_wthru);
- break;
- default:
- memcpy(buff, frv_cache_wback, sizeof(frv_cache_wback) - 1);
- buff[sizeof(frv_cache_wback) - 1] = '\n';
- len = sizeof(frv_cache_wback);
- break;
- }
-
- if (len > *lenp)
- len = *lenp;
-
- if (copy_to_user(buffer, buff, len) != 0)
- return -EFAULT;
-
- *lenp = len;
- *ppos = len;
- return 0;
-
-} /* end procctl_frv_cachemode() */
-
-/*****************************************************************************/
-/*
- * permit the mm_struct the nominated process is using have its MMU context ID pinned
- */
-#ifdef CONFIG_MMU
-static int procctl_frv_pin_cxnr(struct ctl_table *table, int write,
- void __user *buffer, size_t *lenp,
- loff_t *ppos)
-{
- pid_t pid;
- char buff[16], *p;
- int len;
-
- len = *lenp;
-
- if (write) {
- /* potential state change */
- if (len <= 1 || len > sizeof(buff) - 1)
- return -EINVAL;
-
- if (copy_from_user(buff, buffer, len) != 0)
- return -EFAULT;
-
- if (buff[len - 1] == '\n')
- buff[len - 1] = '\0';
- else
- buff[len] = '\0';
-
- pid = simple_strtoul(buff, &p, 10);
- if (*p)
- return -EINVAL;
-
- return cxn_pin_by_pid(pid);
- }
-
- /* read the currently pinned CXN */
- if (*ppos > 0) {
- *lenp = 0;
- return 0;
- }
-
- len = snprintf(buff, sizeof(buff), "%d\n", cxn_pinned);
- if (len > *lenp)
- len = *lenp;
-
- if (copy_to_user(buffer, buff, len) != 0)
- return -EFAULT;
-
- *lenp = len;
- *ppos = len;
- return 0;
-
-} /* end procctl_frv_pin_cxnr() */
-#endif
-
-/*
- * FR-V specific sysctls
- */
-static struct ctl_table frv_table[] =
-{
- {
- .procname = "cache-mode",
- .data = NULL,
- .maxlen = 0,
- .mode = 0644,
- .proc_handler = procctl_frv_cachemode,
- },
-#ifdef CONFIG_MMU
- {
- .procname = "pin-cxnr",
- .data = NULL,
- .maxlen = 0,
- .mode = 0644,
- .proc_handler = procctl_frv_pin_cxnr
- },
-#endif
- {}
-};
-
-/*
- * Use a temporary sysctl number. Horrid, but will be cleaned up in 2.6
- * when all the PM interfaces exist nicely.
- */
-static struct ctl_table frv_dir_table[] =
-{
- {
- .procname = "frv",
- .mode = 0555,
- .child = frv_table
- },
- {}
-};
-
-/*
- * Initialize power interface
- */
-static int __init frv_sysctl_init(void)
-{
- register_sysctl_table(frv_dir_table);
- return 0;
-}
-
-__initcall(frv_sysctl_init);
diff --git a/arch/frv/kernel/time.c b/arch/frv/kernel/time.c
deleted file mode 100644
index 332e00bf9d06..000000000000
--- a/arch/frv/kernel/time.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* time.c: FRV arch-specific time handling
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/kernel/time.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/interrupt.h>
-#include <linux/profile.h>
-#include <linux/irq.h>
-#include <linux/mm.h>
-
-#include <asm/io.h>
-#include <asm/timer-regs.h>
-#include <asm/mb-regs.h>
-#include <asm/mb86943a.h>
-
-#include <linux/timex.h>
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-unsigned long __nongprelbss __clkin_clock_speed_HZ;
-unsigned long __nongprelbss __ext_bus_clock_speed_HZ;
-unsigned long __nongprelbss __res_bus_clock_speed_HZ;
-unsigned long __nongprelbss __sdram_clock_speed_HZ;
-unsigned long __nongprelbss __core_bus_clock_speed_HZ;
-unsigned long __nongprelbss __core_clock_speed_HZ;
-unsigned long __nongprelbss __dsu_clock_speed_HZ;
-unsigned long __nongprelbss __serial_clock_speed_HZ;
-unsigned long __delay_loops_MHz;
-
-static irqreturn_t timer_interrupt(int irq, void *dummy);
-
-static struct irqaction timer_irq = {
- .handler = timer_interrupt,
- .name = "timer",
-};
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-static irqreturn_t timer_interrupt(int irq, void *dummy)
-{
- profile_tick(CPU_PROFILING);
-
- xtime_update(1);
-
-#ifdef CONFIG_HEARTBEAT
- static unsigned short n;
- n++;
- __set_LEDS(n);
-#endif /* CONFIG_HEARTBEAT */
-
- update_process_times(user_mode(get_irq_regs()));
-
- return IRQ_HANDLED;
-}
-
-void time_divisor_init(void)
-{
- unsigned short base, pre, prediv;
-
- /* set the scheduling timer going */
- pre = 1;
- prediv = 4;
- base = __res_bus_clock_speed_HZ / pre / HZ / (1 << prediv);
-
- __set_TPRV(pre);
- __set_TxCKSL_DATA(0, prediv);
- __set_TCTR(TCTR_SC_CTR0 | TCTR_RL_RW_LH8 | TCTR_MODE_2);
- __set_TCSR_DATA(0, base & 0xff);
- __set_TCSR_DATA(0, base >> 8);
-}
-
-
-void read_persistent_clock(struct timespec *ts)
-{
- unsigned int year, mon, day, hour, min, sec;
-
- extern void arch_gettod(int *year, int *mon, int *day, int *hour, int *min, int *sec);
-
- /* FIX by dqg : Set to zero for platforms that don't have tod */
- /* without this time is undefined and can overflow time_t, causing */
- /* very strange errors */
- year = 1980;
- mon = day = 1;
- hour = min = sec = 0;
- arch_gettod (&year, &mon, &day, &hour, &min, &sec);
-
- if ((year += 1900) < 1970)
- year += 100;
- ts->tv_sec = mktime(year, mon, day, hour, min, sec);
- ts->tv_nsec = 0;
-}
-
-void time_init(void)
-{
- /* install scheduling interrupt handler */
- setup_irq(IRQ_CPU_TIMER0, &timer_irq);
-
- time_divisor_init();
-}
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
- return jiffies_64 * (1000000000 / HZ);
-}
diff --git a/arch/frv/kernel/traps.c b/arch/frv/kernel/traps.c
deleted file mode 100644
index fb08ebe0dab4..000000000000
--- a/arch/frv/kernel/traps.c
+++ /dev/null
@@ -1,642 +0,0 @@
-/* traps.c: high-level exception handler for FR-V
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <linux/signal.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/types.h>
-#include <linux/user.h>
-#include <linux/string.h>
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <asm/asm-offsets.h>
-#include <asm/setup.h>
-#include <asm/fpu.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/siginfo.h>
-#include <asm/unaligned.h>
-
-void show_backtrace(struct pt_regs *, unsigned long);
-
-extern asmlinkage void __break_hijack_kernel_event(void);
-
-/*****************************************************************************/
-/*
- * instruction access error
- */
-asmlinkage void insn_access_error(unsigned long esfr1, unsigned long epcr0, unsigned long esr0)
-{
- siginfo_t info;
-
- die_if_kernel("-- Insn Access Error --\n"
- "EPCR0 : %08lx\n"
- "ESR0 : %08lx\n",
- epcr0, esr0);
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = (void __user *) ((epcr0 & EPCR0_V) ? (epcr0 & EPCR0_PC) : __frame->pc);
-
- force_sig_info(info.si_signo, &info, current);
-} /* end insn_access_error() */
-
-/*****************************************************************************/
-/*
- * handler for:
- * - illegal instruction
- * - privileged instruction
- * - unsupported trap
- * - debug exceptions
- */
-asmlinkage void illegal_instruction(unsigned long esfr1, unsigned long epcr0, unsigned long esr0)
-{
- siginfo_t info;
-
- die_if_kernel("-- Illegal Instruction --\n"
- "EPCR0 : %08lx\n"
- "ESR0 : %08lx\n"
- "ESFR1 : %08lx\n",
- epcr0, esr0, esfr1);
-
- info.si_errno = 0;
- info.si_addr = (void __user *) ((epcr0 & EPCR0_V) ? (epcr0 & EPCR0_PC) : __frame->pc);
-
- switch (__frame->tbr & TBR_TT) {
- case TBR_TT_ILLEGAL_INSTR:
- info.si_signo = SIGILL;
- info.si_code = ILL_ILLOPC;
- break;
- case TBR_TT_PRIV_INSTR:
- info.si_signo = SIGILL;
- info.si_code = ILL_PRVOPC;
- break;
- case TBR_TT_TRAP2 ... TBR_TT_TRAP126:
- info.si_signo = SIGILL;
- info.si_code = ILL_ILLTRP;
- break;
- /* GDB uses "tira gr0, #1" as a breakpoint instruction. */
- case TBR_TT_TRAP1:
- case TBR_TT_BREAK:
- info.si_signo = SIGTRAP;
- info.si_code =
- (__frame->__status & REG__STATUS_STEPPED) ? TRAP_TRACE : TRAP_BRKPT;
- break;
- }
-
- force_sig_info(info.si_signo, &info, current);
-} /* end illegal_instruction() */
-
-/*****************************************************************************/
-/*
- * handle atomic operations with errors
- * - arguments in gr8, gr9, gr10
- * - original memory value placed in gr5
- * - replacement memory value placed in gr9
- */
-asmlinkage void atomic_operation(unsigned long esfr1, unsigned long epcr0,
- unsigned long esr0)
-{
- static DEFINE_SPINLOCK(atomic_op_lock);
- unsigned long x, y, z;
- unsigned long __user *p;
- mm_segment_t oldfs;
- siginfo_t info;
- int ret;
-
- y = 0;
- z = 0;
-
- oldfs = get_fs();
- if (!user_mode(__frame))
- set_fs(KERNEL_DS);
-
- switch (__frame->tbr & TBR_TT) {
- /* TIRA gr0,#120
- * u32 __atomic_user_cmpxchg32(u32 *ptr, u32 test, u32 new)
- */
- case TBR_TT_ATOMIC_CMPXCHG32:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
- y = __frame->gr10;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- if (z != x)
- goto done;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- if (z != x)
- goto done2;
-
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#121
- * u32 __atomic_kernel_xchg32(void *v, u32 new)
- */
- case TBR_TT_ATOMIC_XCHG32:
- p = (unsigned long __user *) __frame->gr8;
- y = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#122
- * ulong __atomic_kernel_XOR_return(ulong i, ulong *v)
- */
- case TBR_TT_ATOMIC_XOR:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = x ^ z;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#123
- * ulong __atomic_kernel_OR_return(ulong i, ulong *v)
- */
- case TBR_TT_ATOMIC_OR:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = x ^ z;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#124
- * ulong __atomic_kernel_AND_return(ulong i, ulong *v)
- */
- case TBR_TT_ATOMIC_AND:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = x & z;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#125
- * int __atomic_user_sub_return(atomic_t *v, int i)
- */
- case TBR_TT_ATOMIC_SUB:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = z - x;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- /* TIRA gr0,#126
- * int __atomic_user_add_return(atomic_t *v, int i)
- */
- case TBR_TT_ATOMIC_ADD:
- p = (unsigned long __user *) __frame->gr8;
- x = __frame->gr9;
-
- for (;;) {
- ret = get_user(z, p);
- if (ret < 0)
- goto error;
-
- spin_lock_irq(&atomic_op_lock);
-
- if (__get_user(z, p) == 0) {
- y = z + x;
- if (__put_user(y, p) == 0)
- goto done2;
- goto error2;
- }
-
- spin_unlock_irq(&atomic_op_lock);
- }
-
- default:
- BUG();
- }
-
-done2:
- spin_unlock_irq(&atomic_op_lock);
-done:
- if (!user_mode(__frame))
- set_fs(oldfs);
- __frame->gr5 = z;
- __frame->gr9 = y;
- return;
-
-error2:
- spin_unlock_irq(&atomic_op_lock);
-error:
- if (!user_mode(__frame))
- set_fs(oldfs);
- __frame->pc -= 4;
-
- die_if_kernel("-- Atomic Op Error --\n");
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = (void __user *) __frame->pc;
-
- force_sig_info(info.si_signo, &info, current);
-}
-
-/*****************************************************************************/
-/*
- *
- */
-asmlinkage void media_exception(unsigned long msr0, unsigned long msr1)
-{
- siginfo_t info;
-
- die_if_kernel("-- Media Exception --\n"
- "MSR0 : %08lx\n"
- "MSR1 : %08lx\n",
- msr0, msr1);
-
- info.si_signo = SIGFPE;
- info.si_code = FPE_MDAOVF;
- info.si_errno = 0;
- info.si_addr = (void __user *) __frame->pc;
-
- force_sig_info(info.si_signo, &info, current);
-} /* end media_exception() */
-
-/*****************************************************************************/
-/*
- * instruction or data access exception
- */
-asmlinkage void memory_access_exception(unsigned long esr0,
- unsigned long ear0,
- unsigned long epcr0)
-{
- siginfo_t info;
-
-#ifdef CONFIG_MMU
- if (fixup_exception(__frame))
- return;
-#endif
-
- die_if_kernel("-- Memory Access Exception --\n"
- "ESR0 : %08lx\n"
- "EAR0 : %08lx\n"
- "EPCR0 : %08lx\n",
- esr0, ear0, epcr0);
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = NULL;
-
- if ((esr0 & (ESRx_VALID | ESR0_EAV)) == (ESRx_VALID | ESR0_EAV))
- info.si_addr = (void __user *) ear0;
-
- force_sig_info(info.si_signo, &info, current);
-
-} /* end memory_access_exception() */
-
-/*****************************************************************************/
-/*
- * data access error
- * - double-word data load from CPU control area (0xFExxxxxx)
- * - read performed on inactive or self-refreshing SDRAM
- * - error notification from slave device
- * - misaligned address
- * - access to out of bounds memory region
- * - user mode accessing privileged memory region
- * - write to R/O memory region
- */
-asmlinkage void data_access_error(unsigned long esfr1, unsigned long esr15, unsigned long ear15)
-{
- siginfo_t info;
-
- die_if_kernel("-- Data Access Error --\n"
- "ESR15 : %08lx\n"
- "EAR15 : %08lx\n",
- esr15, ear15);
-
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- info.si_errno = 0;
- info.si_addr = (void __user *)
- (((esr15 & (ESRx_VALID|ESR15_EAV)) == (ESRx_VALID|ESR15_EAV)) ? ear15 : 0);
-
- force_sig_info(info.si_signo, &info, current);
-} /* end data_access_error() */
-
-/*****************************************************************************/
-/*
- * data store error - should only happen if accessing inactive or self-refreshing SDRAM
- */
-asmlinkage void data_store_error(unsigned long esfr1, unsigned long esr15)
-{
- die_if_kernel("-- Data Store Error --\n"
- "ESR15 : %08lx\n",
- esr15);
- BUG();
-} /* end data_store_error() */
-
-/*****************************************************************************/
-/*
- *
- */
-asmlinkage void division_exception(unsigned long esfr1, unsigned long esr0, unsigned long isr)
-{
- siginfo_t info;
-
- die_if_kernel("-- Division Exception --\n"
- "ESR0 : %08lx\n"
- "ISR : %08lx\n",
- esr0, isr);
-
- info.si_signo = SIGFPE;
- info.si_code = FPE_INTDIV;
- info.si_errno = 0;
- info.si_addr = (void __user *) __frame->pc;
-
- force_sig_info(info.si_signo, &info, current);
-} /* end division_exception() */
-
-/*****************************************************************************/
-/*
- *
- */
-asmlinkage void compound_exception(unsigned long esfr1,
- unsigned long esr0, unsigned long esr14, unsigned long esr15,
- unsigned long msr0, unsigned long msr1)
-{
- die_if_kernel("-- Compound Exception --\n"
- "ESR0 : %08lx\n"
- "ESR15 : %08lx\n"
- "ESR15 : %08lx\n"
- "MSR0 : %08lx\n"
- "MSR1 : %08lx\n",
- esr0, esr14, esr15, msr0, msr1);
- BUG();
-} /* end compound_exception() */
-
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
-}
-
-void show_trace_task(struct task_struct *tsk)
-{
- printk("CONTEXT: stack=0x%lx frame=0x%p LR=0x%lx RET=0x%lx\n",
- tsk->thread.sp, tsk->thread.frame, tsk->thread.lr, tsk->thread.sched_lr);
-}
-
-static const char *regnames[] = {
- "PSR ", "ISR ", "CCR ", "CCCR",
- "LR ", "LCR ", "PC ", "_stt",
- "sys ", "GR8*", "GNE0", "GNE1",
- "IACH", "IACL",
- "TBR ", "SP ", "FP ", "GR3 ",
- "GR4 ", "GR5 ", "GR6 ", "GR7 ",
- "GR8 ", "GR9 ", "GR10", "GR11",
- "GR12", "GR13", "GR14", "GR15",
- "GR16", "GR17", "GR18", "GR19",
- "GR20", "GR21", "GR22", "GR23",
- "GR24", "GR25", "GR26", "GR27",
- "EFRM", "CURR", "GR30", "BFRM"
-};
-
-void show_regs(struct pt_regs *regs)
-{
- unsigned long *reg;
- int loop;
-
- printk("\n");
- show_regs_print_info(KERN_DEFAULT);
-
- printk("Frame: @%08lx [%s]\n",
- (unsigned long) regs,
- regs->psr & PSR_S ? "kernel" : "user");
-
- reg = (unsigned long *) regs;
- for (loop = 0; loop < NR_PT_REGS; loop++) {
- printk("%s %08lx", regnames[loop + 0], reg[loop + 0]);
-
- if (loop == NR_PT_REGS - 1 || loop % 5 == 4)
- printk("\n");
- else
- printk(" | ");
- }
-}
-
-void die_if_kernel(const char *str, ...)
-{
- char buffer[256];
- va_list va;
-
- if (user_mode(__frame))
- return;
-
- va_start(va, str);
- vsnprintf(buffer, sizeof(buffer), str, va);
- va_end(va);
-
- console_verbose();
- printk("\n===================================\n");
- printk("%s\n", buffer);
- show_backtrace(__frame, 0);
-
- __break_hijack_kernel_event();
- do_exit(SIGSEGV);
-}
-
-/*****************************************************************************/
-/*
- * dump the contents of an exception frame
- */
-static void show_backtrace_regs(struct pt_regs *frame)
-{
- unsigned long *reg;
- int loop;
-
- /* print the registers for this frame */
- printk("<-- %s Frame: @%p -->\n",
- frame->psr & PSR_S ? "Kernel Mode" : "User Mode",
- frame);
-
- reg = (unsigned long *) frame;
- for (loop = 0; loop < NR_PT_REGS; loop++) {
- printk("%s %08lx", regnames[loop + 0], reg[loop + 0]);
-
- if (loop == NR_PT_REGS - 1 || loop % 5 == 4)
- printk("\n");
- else
- printk(" | ");
- }
-
- printk("--------\n");
-} /* end show_backtrace_regs() */
-
-/*****************************************************************************/
-/*
- * generate a backtrace of the kernel stack
- */
-void show_backtrace(struct pt_regs *frame, unsigned long sp)
-{
- struct pt_regs *frame0;
- unsigned long tos = 0, stop = 0, base;
- int format;
-
- base = ((((unsigned long) frame) + 8191) & ~8191) - sizeof(struct user_context);
- frame0 = (struct pt_regs *) base;
-
- if (sp) {
- tos = sp;
- stop = (unsigned long) frame;
- }
-
- printk("\nProcess %s (pid: %d)\n\n", current->comm, current->pid);
-
- for (;;) {
- /* dump stack segment between frames */
- //printk("%08lx -> %08lx\n", tos, stop);
- format = 0;
- while (tos < stop) {
- if (format == 0)
- printk(" %04lx :", tos & 0xffff);
-
- printk(" %08lx", *(unsigned long *) tos);
-
- tos += 4;
- format++;
- if (format == 8) {
- printk("\n");
- format = 0;
- }
- }
-
- if (format > 0)
- printk("\n");
-
- /* dump frame 0 outside of the loop */
- if (frame == frame0)
- break;
-
- tos = frame->sp;
- if (((unsigned long) frame) + sizeof(*frame) != tos) {
- printk("-- TOS %08lx does not follow frame %p --\n",
- tos, frame);
- break;
- }
-
- show_backtrace_regs(frame);
-
- /* dump the stack between this frame and the next */
- stop = (unsigned long) frame->next_frame;
- if (stop != base &&
- (stop < tos ||
- stop > base ||
- (stop < base && stop + sizeof(*frame) > base) ||
- stop & 3)) {
- printk("-- next_frame %08lx is invalid (range %08lx-%08lx) --\n",
- stop, tos, base);
- break;
- }
-
- /* move to next frame */
- frame = frame->next_frame;
- }
-
- /* we can always dump frame 0, even if the rest of the stack is corrupt */
- show_backtrace_regs(frame0);
-
-} /* end show_backtrace() */
-
-/*****************************************************************************/
-/*
- * initialise traps
- */
-void __init trap_init (void)
-{
-} /* end trap_init() */
diff --git a/arch/frv/kernel/uaccess.c b/arch/frv/kernel/uaccess.c
deleted file mode 100644
index 8b360b4222a5..000000000000
--- a/arch/frv/kernel/uaccess.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* uaccess.c: userspace access functions
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-/*****************************************************************************/
-/*
- * copy a null terminated string from userspace
- */
-long strncpy_from_user(char *dst, const char __user *src, long count)
-{
- unsigned long max;
- char *p, ch;
- long err = -EFAULT;
-
- BUG_ON(count < 0);
-
- p = dst;
-
-#ifndef CONFIG_MMU
- if ((unsigned long) src < memory_start)
- goto error;
-#endif
-
- if ((unsigned long) src >= get_addr_limit())
- goto error;
-
- max = get_addr_limit() - (unsigned long) src;
- if ((unsigned long) count > max) {
- memset(dst + max, 0, count - max);
- count = max;
- }
-
- err = 0;
- for (; count > 0; count--, p++, src++) {
- __get_user_asm(err, ch, src, "ub", "=r");
- if (err < 0)
- goto error;
- if (!ch)
- break;
- *p = ch;
- }
-
- err = p - dst; /* return length excluding NUL */
-
- error:
- if (count > 0)
- memset(p, 0, count); /* clear remainder of buffer [security] */
-
- return err;
-
-} /* end strncpy_from_user() */
-
-EXPORT_SYMBOL(strncpy_from_user);
-
-/*****************************************************************************/
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-long strnlen_user(const char __user *src, long count)
-{
- const char __user *p;
- long err = 0;
- char ch;
-
- BUG_ON(count < 0);
-
-#ifndef CONFIG_MMU
- if ((unsigned long) src < memory_start)
- return 0;
-#endif
-
- if ((unsigned long) src >= get_addr_limit())
- return 0;
-
- for (p = src; count > 0; count--, p++) {
- __get_user_asm(err, ch, p, "ub", "=r");
- if (err < 0)
- return 0;
- if (!ch)
- break;
- }
-
- return p - src + 1; /* return length including NUL */
-
-} /* end strnlen_user() */
-
-EXPORT_SYMBOL(strnlen_user);
diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
deleted file mode 100644
index 42806c512758..000000000000
--- a/arch/frv/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,136 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ld script to make FRV Linux kernel
- * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz>;
- */
-OUTPUT_FORMAT("elf32-frv", "elf32-frv", "elf32-frv")
-OUTPUT_ARCH(frv)
-ENTRY(_start)
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/thread_info.h>
-
-jiffies = jiffies_64 + 4;
-
-__page_offset = CONFIG_PAGE_OFFSET; /* start of area covered by struct pages */
-__kernel_image_start = __page_offset; /* address at which kernel image resides */
-
-SECTIONS
-{
- . = __kernel_image_start;
-
- /* discardable initialisation code and data */
- . = ALIGN(PAGE_SIZE); /* Init code and data */
- __init_begin = .;
-
- _sinittext = .;
- .init.text : {
- HEAD_TEXT
-#ifndef CONFIG_DEBUG_INFO
- INIT_TEXT
- EXIT_TEXT
- EXIT_DATA
- *(.exitcall.exit)
-#endif
- }
- _einittext = .;
-
- INIT_DATA_SECTION(8)
- PERCPU_SECTION(L1_CACHE_BYTES)
-
- . = ALIGN(PAGE_SIZE);
- __init_end = .;
-
- .trap : {
- /* trap table management - read entry-table.S before modifying */
- . = ALIGN(8192);
- __trap_tables = .;
- *(.trap.user)
- *(.trap.kernel)
- . = ALIGN(4096);
- *(.trap.break)
- }
-
- /* Text and read-only data */
- . = ALIGN(4);
- _text = .;
- _stext = .;
- .text : {
- *(.text..start)
- *(.text..entry)
- *(.text..break)
- *(.text..tlbmiss)
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
-#ifdef CONFIG_DEBUG_INFO
- INIT_TEXT
- EXIT_TEXT
- *(.exitcall.exit)
-#endif
- *(.fixup)
- *(.gnu.warning)
- *(.exitcall.exit)
- } = 0x9090
-
- _etext = .; /* End of text section */
-
- RODATA
-
- .rodata : {
- *(.trap.vector)
-
- /* this clause must not be modified - the ordering and adjacency are imperative */
- __trap_fixup_tables = .;
- *(.trap.fixup.user .trap.fixup.kernel)
-
- }
-
- EXCEPTION_TABLE(8)
-
- _sdata = .;
- .data : { /* Data */
- INIT_TASK_DATA(THREAD_SIZE)
- CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
- DATA_DATA
- *(.data.*)
- EXIT_DATA
- CONSTRUCTORS
- }
-
- _edata = .; /* End of data section */
-
- BUG_TABLE
-
- /* GP section */
- . = ALIGN(L1_CACHE_BYTES);
- _gp = . + 2048;
- PROVIDE (gp = _gp);
-
- .sdata : { *(.sdata .sdata.*) }
-
- /* BSS */
- . = ALIGN(L1_CACHE_BYTES);
- __bss_start = .;
-
- .sbss : { *(.sbss .sbss.*) }
- .bss : { *(.bss .bss.*) }
- .bss..stack : { *(.bss) }
-
- __bss_stop = .;
- _end = . ;
- . = ALIGN(PAGE_SIZE);
- __kernel_image_end = .;
-
- STABS_DEBUG
- DWARF_DEBUG
-
- .comment 0 : { *(.comment) }
-
- DISCARDS
-}
-
-__kernel_image_size_no_bss = __bss_start - __kernel_image_start;
diff --git a/arch/frv/lib/Makefile b/arch/frv/lib/Makefile
deleted file mode 100644
index 970e8b4f1a02..000000000000
--- a/arch/frv/lib/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for FRV-specific library files..
-#
-
-lib-y := \
- __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \
- checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \
- outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o atomic-lib.o
diff --git a/arch/frv/lib/__ashldi3.S b/arch/frv/lib/__ashldi3.S
deleted file mode 100644
index db5b6dc37a11..000000000000
--- a/arch/frv/lib/__ashldi3.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* __ashldi3.S: 64-bit arithmetic shift left
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __ashldi3(unsigned long long value [GR8:GR9], unsigned by [GR10])
-#
-###############################################################################
- .globl __ashldi3
- .type __ashldi3,@function
-__ashldi3:
- andicc.p gr10,#63,gr10,icc0
- setlos #32,gr5
- andicc.p gr10,#32,gr0,icc1
- beqlr icc0,#0
- ckeq icc1,cc4 ; cc4 is true if 0<N<32
-
- # deal with a shift in the range 1<=N<=31
- csll.p gr8,gr10,gr8 ,cc4,#1 ; MSW <<= N
- csub gr5,gr10,gr5 ,cc4,#1 ; M = 32 - N
- csrl.p gr9,gr5,gr4 ,cc4,#1
- csll gr9,gr10,gr9 ,cc4,#1 ; LSW <<= N
- cor.p gr4,gr8,gr8 ,cc4,#1 ; MSW |= LSW >> M
-
- # deal with a shift in the range 32<=N<=63
- csll gr9,gr10,gr8 ,cc4,#0 ; MSW = LSW << (N & 31 [implicit AND])
- cor.p gr0,gr0,gr9 ,cc4,#0 ; LSW = 0
- bralr
- .size __ashldi3, .-__ashldi3
diff --git a/arch/frv/lib/__ashrdi3.S b/arch/frv/lib/__ashrdi3.S
deleted file mode 100644
index 5742665bfd29..000000000000
--- a/arch/frv/lib/__ashrdi3.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/* __ashrdi3.S: 64-bit arithmetic shift right
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# signed long long __ashrdi3(signed long long value [GR8:GR9], unsigned by [GR10])
-#
-###############################################################################
- .globl __ashrdi3
- .type __ashrdi3,@function
-__ashrdi3:
- andicc.p gr10,#63,gr10,icc0
- setlos #32,gr5
- andicc.p gr10,#32,gr0,icc1
- beqlr icc0,#0
- setlos.p #31,gr6
- ckeq icc1,cc4 ; cc4 is true if 0<N<32
-
- # deal with a shift in the range 1<=N<=31
- csrl.p gr9,gr10,gr9 ,cc4,#1 ; LSW >>= N
- csub gr5,gr10,gr5 ,cc4,#1 ; M = 32 - N
- csll.p gr8,gr5,gr4 ,cc4,#1
- csra gr8,gr10,gr8 ,cc4,#1 ; MSW >>= N
- cor.p gr4,gr9,gr9 ,cc4,#1 ; LSW |= MSW << M
-
- # deal with a shift in the range 32<=N<=63
- csra gr8,gr10,gr9 ,cc4,#0 ; LSW = MSW >> (N & 31 [implicit AND])
- csra.p gr8,gr6,gr8 ,cc4,#0 ; MSW >>= 31
- bralr
- .size __ashrdi3, .-__ashrdi3
diff --git a/arch/frv/lib/__lshrdi3.S b/arch/frv/lib/__lshrdi3.S
deleted file mode 100644
index 7b41f6304f04..000000000000
--- a/arch/frv/lib/__lshrdi3.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* __lshrdi3.S: 64-bit logical shift right
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __lshrdi3(unsigned long long value [GR8:GR9], unsigned by [GR10])
-#
-###############################################################################
- .globl __lshrdi3
- .type __lshrdi3,@function
-__lshrdi3:
- andicc.p gr10,#63,gr10,icc0
- setlos #32,gr5
- andicc.p gr10,#32,gr0,icc1
- beqlr icc0,#0
- ckeq icc1,cc4 ; cc4 is true if 0<N<32
-
- # deal with a shift in the range 1<=N<=31
- csrl.p gr9,gr10,gr9 ,cc4,#1 ; LSW >>= N
- csub gr5,gr10,gr5 ,cc4,#1 ; M = 32 - N
- csll.p gr8,gr5,gr4 ,cc4,#1
- csrl gr8,gr10,gr8 ,cc4,#1 ; MSW >>= N
- cor.p gr4,gr9,gr9 ,cc4,#1 ; LSW |= MSW << M
-
- # deal with a shift in the range 32<=N<=63
- csrl gr8,gr10,gr9 ,cc4,#0 ; LSW = MSW >> (N & 31 [implicit AND])
- cor.p gr0,gr0,gr8 ,cc4,#0 ; MSW = 0
- bralr
- .size __lshrdi3, .-__lshrdi3
diff --git a/arch/frv/lib/__muldi3.S b/arch/frv/lib/__muldi3.S
deleted file mode 100644
index 2703d9b79361..000000000000
--- a/arch/frv/lib/__muldi3.S
+++ /dev/null
@@ -1,32 +0,0 @@
-/* __muldi3.S: 64-bit multiply
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __muldi3(unsigned long long x [GR8:GR9],
-# unsigned long long y [GR10:GR11])
-#
-###############################################################################
- .globl __muldi3, __mulll, __umulll
- .type __muldi3,@function
-__muldi3:
-__mulll:
-__umulll:
- umul gr8,gr11,gr4 ; GR4:GR5 = x.MSW * y.LSW
- umul gr9,gr10,gr6 ; GR6:GR7 = x.LSW * y.MSW
- umul.p gr9,gr11,gr8 ; GR8:GR9 = x.LSW * y.LSW
- add gr5,gr7,gr5
- add.p gr8,gr5,gr8 ; GR8 += GR5 + GR7
- bralr
- .size __muldi3, .-__muldi3
diff --git a/arch/frv/lib/__negdi2.S b/arch/frv/lib/__negdi2.S
deleted file mode 100644
index d1747bf24997..000000000000
--- a/arch/frv/lib/__negdi2.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/* __negdi2.S: 64-bit negate
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# unsigned long long __negdi2(unsigned long long value [GR8:GR9])
-#
-###############################################################################
- .globl __negdi2
- .type __negdi2,@function
-__negdi2:
- subcc gr0,gr9,gr9,icc0
- subx gr0,gr8,gr8,icc0
- bralr
- .size __negdi2, .-__negdi2
-
diff --git a/arch/frv/lib/__ucmpdi2.S b/arch/frv/lib/__ucmpdi2.S
deleted file mode 100644
index d892f16ffaa9..000000000000
--- a/arch/frv/lib/__ucmpdi2.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/* __ucmpdi2.S: 64-bit unsigned compare
- *
- * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# int __ucmpdi2(unsigned long long a [GR8:GR9],
-# unsigned long long b [GR10:GR11])
-#
-# - returns 0, 1, or 2 as a <, =, > b respectively.
-#
-###############################################################################
- .globl __ucmpdi2
- .type __ucmpdi2,@function
-__ucmpdi2:
- or.p gr8,gr0,gr4
- subcc gr8,gr10,gr0,icc0
- setlos.p #0,gr8
- bclr icc0,#2 ; a.msw < b.msw
-
- setlos.p #2,gr8
- bhilr icc0,#0 ; a.msw > b.msw
-
- subcc.p gr9,gr11,gr0,icc1
- setlos #0,gr8
- setlos.p #2,gr9
- setlos #1,gr7
- cknc icc1,cc6
- cor.p gr9,gr0,gr8, cc6,#1
- cckls icc1,cc4, cc6,#1
- andcr cc6,cc4,cc4
- cor gr7,gr0,gr8, cc4,#1
- bralr
- .size __ucmpdi2, .-__ucmpdi2
diff --git a/arch/frv/lib/atomic-lib.c b/arch/frv/lib/atomic-lib.c
deleted file mode 100644
index 3027576f7782..000000000000
--- a/arch/frv/lib/atomic-lib.c
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <linux/export.h>
-#include <asm/atomic.h>
-
-#define __ATOMIC_LIB__
-
-#include <asm/atomic_defs.h>
diff --git a/arch/frv/lib/atomic-ops.S b/arch/frv/lib/atomic-ops.S
deleted file mode 100644
index b7439a960b5b..000000000000
--- a/arch/frv/lib/atomic-ops.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/* atomic-ops.S: kernel atomic operations
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/spr-regs.h>
-
- .text
- .balign 4
-
-###############################################################################
-#
-# uint32_t __xchg_32(uint32_t i, uint32_t *v)
-#
-###############################################################################
- .globl __xchg_32
- .type __xchg_32,@function
-__xchg_32:
- or.p gr8,gr8,gr10
-0:
- orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
- ckeq icc3,cc7
- ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
- orcr cc7,cc7,cc3 /* set CC3 to true */
- cst.p gr10,@(gr9,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
- beq icc3,#0,0b
- bralr
-
- .size __xchg_32, .-__xchg_32
-
-###############################################################################
-#
-# uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new)
-#
-###############################################################################
- .globl __cmpxchg_32
- .type __cmpxchg_32,@function
-__cmpxchg_32:
- or.p gr8,gr8,gr11
-0:
- orcc gr0,gr0,gr0,icc3
- ckeq icc3,cc7
- ld.p @(gr11,gr0),gr8
- orcr cc7,cc7,cc3
- subcc gr8,gr9,gr7,icc0
- bnelr icc0,#0
- cst.p gr10,@(gr11,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1
- beq icc3,#0,0b
- bralr
-
- .size __cmpxchg_32, .-__cmpxchg_32
diff --git a/arch/frv/lib/atomic64-ops.S b/arch/frv/lib/atomic64-ops.S
deleted file mode 100644
index c4c472308a33..000000000000
--- a/arch/frv/lib/atomic64-ops.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/* kernel atomic64 operations
- *
- * For an explanation of how atomic ops work in this arch, see:
- * Documentation/frv/atomic-ops.txt
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/spr-regs.h>
-
- .text
- .balign 4
-
-
-###############################################################################
-#
-# uint64_t __xchg_64(uint64_t i, uint64_t *v)
-#
-###############################################################################
- .globl __xchg_64
- .type __xchg_64,@function
-__xchg_64:
- or.p gr8,gr8,gr4
- or gr9,gr9,gr5
-0:
- orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
- ckeq icc3,cc7
- ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
- orcr cc7,cc7,cc3 /* set CC3 to true */
- cstd.p gr4,@(gr10,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
- beq icc3,#0,0b
- bralr
-
- .size __xchg_64, .-__xchg_64
-
-###############################################################################
-#
-# uint64_t __cmpxchg_64(uint64_t test, uint64_t new, uint64_t *v)
-#
-###############################################################################
- .globl __cmpxchg_64
- .type __cmpxchg_64,@function
-__cmpxchg_64:
- or.p gr8,gr8,gr4
- or gr9,gr9,gr5
-0:
- orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
- ckeq icc3,cc7
- ldd.p @(gr12,gr0),gr8 /* LDD.P/ORCR must be atomic */
- orcr cc7,cc7,cc3
- subcc gr8,gr4,gr0,icc0
- subcc.p gr9,gr5,gr0,icc1
- bnelr icc0,#0
- bnelr icc1,#0
- cstd.p gr10,@(gr12,gr0) ,cc3,#1
- corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
- beq icc3,#0,0b
- bralr
-
- .size __cmpxchg_64, .-__cmpxchg_64
-
diff --git a/arch/frv/lib/cache.S b/arch/frv/lib/cache.S
deleted file mode 100644
index 0c4fb204911b..000000000000
--- a/arch/frv/lib/cache.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/* cache.S: cache management routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <asm/spr-regs.h>
-#include <asm/cache.h>
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# Write back a range of dcache
-# - void frv_dcache_writeback(unsigned long start [GR8], unsigned long size [GR9])
-#
-###############################################################################
- .globl frv_dcache_writeback
- .type frv_dcache_writeback,@function
-frv_dcache_writeback:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: dcf @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_dcache_writeback, .-frv_dcache_writeback
-
-##############################################################################
-#
-# Invalidate a range of dcache and icache
-# - void frv_cache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
-#
-###############################################################################
- .globl frv_cache_invalidate
- .type frv_cache_invalidate,@function
-frv_cache_invalidate:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: dci @(gr8,gr0)
- ici @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_cache_invalidate, .-frv_cache_invalidate
-
-##############################################################################
-#
-# Invalidate a range of icache
-# - void frv_icache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
-#
-###############################################################################
- .globl frv_icache_invalidate
- .type frv_icache_invalidate,@function
-frv_icache_invalidate:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: ici @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_icache_invalidate, .-frv_icache_invalidate
-
-###############################################################################
-#
-# Write back and invalidate a range of dcache and icache
-# - void frv_cache_wback_inv(unsigned long start [GR8], unsigned long end [GR9])
-#
-###############################################################################
- .globl frv_cache_wback_inv
- .type frv_cache_wback_inv,@function
-frv_cache_wback_inv:
- andi gr8,~(L1_CACHE_BYTES-1),gr8
-
-2: dcf @(gr8,gr0)
- ici @(gr8,gr0)
- addi gr8,#L1_CACHE_BYTES,gr8
- cmp gr9,gr8,icc0
- bhi icc0,#2,2b
-
- membar
- bralr
- .size frv_cache_wback_inv, .-frv_cache_wback_inv
diff --git a/arch/frv/lib/checksum.c b/arch/frv/lib/checksum.c
deleted file mode 100644
index 44e16d59bc10..000000000000
--- a/arch/frv/lib/checksum.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * INET An implementation of the TCP/IP protocol suite for the LINUX
- * operating system. INET is implemented using the BSD Socket
- * interface as the means of communication with the user level.
- *
- * IP/TCP/UDP checksumming routines
- *
- * Authors: Jorge Cwik, <jorge@laser.satlink.net>
- * Arnt Gulbrandsen, <agulbra@nvg.unit.no>
- * Tom May, <ftom@netcom.com>
- * Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de>
- * Lots of code moved from tcp.c and ip.c; see those files
- * for more names.
- *
- * 03/02/96 Jes Sorensen, Andreas Schwab, Roman Hodek:
- * Fixed some nasty bugs, causing some horrible crashes.
- * A: At some points, the sum (%0) was used as
- * length-counter instead of the length counter
- * (%1). Thanks to Roman Hodek for pointing this out.
- * B: GCC seems to mess up if one uses too many
- * data-registers to hold input values and one tries to
- * specify d0 and d1 as scratch registers. Letting gcc choose these
- * registers itself solves the problem.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/* Revised by Kenneth Albanowski for m68knommu. Basic problem: unaligned access kills, so most
- of the assembly has to go. */
-
-#include <net/checksum.h>
-#include <linux/module.h>
-
-static inline unsigned short from32to16(unsigned long x)
-{
- /* add up 16-bit and 16-bit for 16+c bit */
- x = (x & 0xffff) + (x >> 16);
- /* add up carry.. */
- x = (x & 0xffff) + (x >> 16);
- return x;
-}
-
-static unsigned long do_csum(const unsigned char * buff, int len)
-{
- int odd, count;
- unsigned long result = 0;
-
- if (len <= 0)
- goto out;
- odd = 1 & (unsigned long) buff;
- if (odd) {
- result = *buff;
- len--;
- buff++;
- }
- count = len >> 1; /* nr of 16-bit words.. */
- if (count) {
- if (2 & (unsigned long) buff) {
- result += *(unsigned short *) buff;
- count--;
- len -= 2;
- buff += 2;
- }
- count >>= 1; /* nr of 32-bit words.. */
- if (count) {
- unsigned long carry = 0;
- do {
- unsigned long w = *(unsigned long *) buff;
- count--;
- buff += 4;
- result += carry;
- result += w;
- carry = (w > result);
- } while (count);
- result += carry;
- result = (result & 0xffff) + (result >> 16);
- }
- if (len & 2) {
- result += *(unsigned short *) buff;
- buff += 2;
- }
- }
- if (len & 1)
- result += (*buff << 8);
- result = from32to16(result);
- if (odd)
- result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
-out:
- return result;
-}
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum)
-{
- unsigned int result = do_csum(buff, len);
-
- /* add in old sum, and carry.. */
- result += (__force u32)sum;
- if ((__force u32)sum > result)
- result += 1;
- return (__force __wsum)result;
-}
-
-EXPORT_SYMBOL(csum_partial);
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-__sum16 ip_compute_csum(const void *buff, int len)
-{
- return (__force __sum16)~do_csum(buff, len);
-}
-
-EXPORT_SYMBOL(ip_compute_csum);
-
-/*
- * copy from fs while checksumming, otherwise like csum_partial
- */
-__wsum
-csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum, int *csum_err)
-{
- int rem;
-
- if (csum_err)
- *csum_err = 0;
-
- rem = copy_from_user(dst, src, len);
- if (rem != 0) {
- if (csum_err)
- *csum_err = -EFAULT;
- memset(dst + len - rem, 0, rem);
- len = rem;
- }
-
- return csum_partial(dst, len, sum);
-}
-
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-
-/*
- * copy from ds while checksumming, otherwise like csum_partial
- */
-__wsum
-csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
-{
- memcpy(dst, src, len);
- return csum_partial(dst, len, sum);
-}
-
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/frv/lib/insl_ns.S b/arch/frv/lib/insl_ns.S
deleted file mode 100644
index d1658425a9f7..000000000000
--- a/arch/frv/lib/insl_ns.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/* insl_ns.S: input array of 4b words from device port without byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __insl_ns(unsigned int port, void *buf, int n)
-#
-###############################################################################
- .globl __insl_ns
- .type __insl_ns,@function
-__insl_ns:
- andicc.p gr9,#3,gr0,icc0
- setlos #4,gr4
- bne icc0,#0,__insl_ns_misaligned
- subi gr9,#4,gr9
-0:
- ldi.p @(gr8,#0),gr5
- subicc gr10,#1,gr10,icc0
- stu.p gr5,@(gr9,gr4)
- bhi icc0,#2,0b
- bralr
-
-__insl_ns_misaligned:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldi @(gr8,#0),gr5
-
- srli gr5,#24,gr6
- stbu.p gr6,@(gr9,gr4)
- srli gr5,#16,gr6
- stbu.p gr6,@(gr9,gr4)
- srli gr5,#8,gr6
- stbu.p gr6,@(gr9,gr4)
- subicc gr10,#1,gr10,icc0
- stbu.p gr5,@(gr9,gr4)
- bhi icc0,#2,0b
- bralr
-
- .size __insl_ns, .-__insl_ns
diff --git a/arch/frv/lib/insl_sw.S b/arch/frv/lib/insl_sw.S
deleted file mode 100644
index 9b5aa95d069b..000000000000
--- a/arch/frv/lib/insl_sw.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* insl_sw.S: input array of 4b words from device port with byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __insl_sw(unsigned int port, void *buf, int n)
-#
-###############################################################################
- .globl __insl_sw
- .type __insl_sw,@function
-__insl_sw:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldi.p @(gr8,#0),gr5 ; get 0xAABBCCDD
- subicc gr10,#1,gr10,icc0
-
- stbu.p gr5,@(gr9,gr4) ; write 0xDD
- srli gr5,#8,gr5
- stbu.p gr5,@(gr9,gr4) ; write 0xCC
- srli gr5,#8,gr5
- stbu.p gr5,@(gr9,gr4) ; write 0xBB
- srli gr5,#8,gr5
- stbu.p gr5,@(gr9,gr4) ; write 0xAA
- bhi icc0,#2,0b
- bralr
-
- .size __insl_sw, .-__insl_sw
diff --git a/arch/frv/lib/memcpy.S b/arch/frv/lib/memcpy.S
deleted file mode 100644
index 9c5965273428..000000000000
--- a/arch/frv/lib/memcpy.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/* memcpy.S: optimised assembly memcpy
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void *memcpy(void *to, const char *from, size_t count)
-#
-# - NOTE: must not use any stack. exception detection performs function return
-# to caller's fixup routine, aborting the remainder of the copy
-#
-###############################################################################
- .globl memcpy,__memcpy_end
- .type memcpy,@function
-memcpy:
- or.p gr8,gr9,gr4
- orcc gr10,gr0,gr0,icc3
- or.p gr10,gr4,gr4
- beqlr icc3,#0
-
- # optimise based on best common alignment for to, from & count
- andicc.p gr4,#0x0f,gr0,icc0
- setlos #8,gr11
- andicc.p gr4,#0x07,gr0,icc1
- beq icc0,#0,memcpy_16
- andicc.p gr4,#0x03,gr0,icc0
- beq icc1,#0,memcpy_8
- andicc.p gr4,#0x01,gr0,icc1
- beq icc0,#0,memcpy_4
- setlos.p #1,gr11
- beq icc1,#0,memcpy_2
-
- # do byte by byte copy
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: ldubu.p @(gr9,gr11),gr4
- subicc gr10,#1,gr10,icc0
- stbu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do halfword by halfword copy
-memcpy_2:
- setlos #2,gr11
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: lduhu.p @(gr9,gr11),gr4
- subicc gr10,#2,gr10,icc0
- sthu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do word by word copy
-memcpy_4:
- setlos #4,gr11
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: ldu.p @(gr9,gr11),gr4
- subicc gr10,#4,gr10,icc0
- stu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do double-word by double-word copy
-memcpy_8:
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: lddu.p @(gr9,gr11),gr4
- subicc gr10,#8,gr10,icc0
- stdu.p gr4,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-
- # do quad-word by quad-word copy
-memcpy_16:
- sub.p gr8,gr11,gr3
- sub gr9,gr11,gr9
-0: lddu @(gr9,gr11),gr4
- lddu.p @(gr9,gr11),gr6
- subicc gr10,#16,gr10,icc0
- stdu gr4,@(gr3,gr11)
- stdu.p gr6,@(gr3,gr11)
- bne icc0,#2,0b
- bralr
-__memcpy_end:
-
- .size memcpy, __memcpy_end-memcpy
-
-###############################################################################
-#
-# copy to/from userspace
-# - return the number of bytes that could not be copied (0 on complete success)
-#
-# long __memcpy_user(void *dst, const void *src, size_t count)
-#
-###############################################################################
- .globl __memcpy_user, __memcpy_user_error_lr, __memcpy_user_error_handler
- .type __memcpy_user,@function
-__memcpy_user:
- movsg lr,gr7
- subi.p sp,#8,sp
- add gr8,gr10,gr6 ; calculate expected end address
- stdi gr6,@(sp,#0)
-
- # abuse memcpy to do the dirty work
- call memcpy
-__memcpy_user_error_lr:
- ldi.p @(sp,#4),gr7
- setlos #0,gr8
- jmpl.p @(gr7,gr0)
- addi sp,#8,sp
-
- # deal any exception generated by memcpy
- # GR8 - memcpy's current dest address
- # GR11 - memset's step value (index register for store insns)
-__memcpy_user_error_handler:
- lddi.p @(sp,#0),gr4 ; load GR4 with dst+count, GR5 with ret addr
- add gr11,gr3,gr7
- sub.p gr4,gr7,gr8
-
- addi sp,#8,sp
- jmpl @(gr5,gr0)
-
- .size __memcpy_user, .-__memcpy_user
diff --git a/arch/frv/lib/memset.S b/arch/frv/lib/memset.S
deleted file mode 100644
index 55a35263cbe3..000000000000
--- a/arch/frv/lib/memset.S
+++ /dev/null
@@ -1,182 +0,0 @@
-/* memset.S: optimised assembly memset
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void *memset(void *p, char ch, size_t count)
-#
-# - NOTE: must not use any stack. exception detection performs function return
-# to caller's fixup routine, aborting the remainder of the set
-# GR4, GR7, GR8, and GR11 must be managed
-#
-###############################################################################
- .globl memset,__memset_end
- .type memset,@function
-memset:
- orcc.p gr10,gr0,gr5,icc3 ; GR5 = count
- andi gr9,#0xff,gr9
- or.p gr8,gr0,gr4 ; GR4 = address
- beqlr icc3,#0
-
- # conditionally write a byte to 2b-align the address
- setlos.p #1,gr6
- andicc gr4,#1,gr0,icc0
- ckne icc0,cc7
- cstb.p gr9,@(gr4,gr0) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cadd.p gr4,gr6,gr4 ,cc7,#1
- beqlr icc3,#0
-
- # conditionally write a word to 4b-align the address
- andicc.p gr4,#2,gr0,icc0
- subicc gr5,#2,gr0,icc1
- setlos.p #2,gr6
- ckne icc0,cc7
- slli.p gr9,#8,gr12 ; need to double up the pattern
- cknc icc1,cc5
- or.p gr9,gr12,gr12
- andcr cc7,cc5,cc7
-
- csth.p gr12,@(gr4,gr0) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cadd.p gr4,gr6,gr4 ,cc7,#1
- beqlr icc3,#0
-
- # conditionally write a dword to 8b-align the address
- andicc.p gr4,#4,gr0,icc0
- subicc gr5,#4,gr0,icc1
- setlos.p #4,gr6
- ckne icc0,cc7
- slli.p gr12,#16,gr13 ; need to quadruple-up the pattern
- cknc icc1,cc5
- or.p gr13,gr12,gr12
- andcr cc7,cc5,cc7
-
- cst.p gr12,@(gr4,gr0) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cadd.p gr4,gr6,gr4 ,cc7,#1
- beqlr icc3,#0
-
- or.p gr12,gr12,gr13 ; need to octuple-up the pattern
-
- # the address is now 8b-aligned - loop around writing 64b chunks
- setlos #8,gr7
- subi.p gr4,#8,gr4 ; store with update index does weird stuff
- setlos #64,gr6
-
- subicc gr5,#64,gr0,icc0
-0: cknc icc0,cc7
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu gr12,@(gr4,gr7) ,cc7,#1
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- subicc gr5,#64,gr0,icc0
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- beqlr icc3,#0
- bnc icc0,#2,0b
-
- # now do 32-byte remnant
- subicc.p gr5,#32,gr0,icc0
- setlos #32,gr6
- cknc icc0,cc7
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- setlos #16,gr6
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- subicc gr5,#16,gr0,icc0
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- beqlr icc3,#0
-
- # now do 16-byte remnant
- cknc icc0,cc7
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr6,gr5 ,cc7,#1 ; also set ICC3
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- beqlr icc3,#0
-
- # now do 8-byte remnant
- subicc gr5,#8,gr0,icc1
- cknc icc1,cc7
- cstdu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr7,gr5 ,cc7,#1 ; also set ICC3
- setlos.p #4,gr7
- beqlr icc3,#0
-
- # now do 4-byte remnant
- subicc gr5,#4,gr0,icc0
- addi.p gr4,#4,gr4
- cknc icc0,cc7
- cstu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr7,gr5 ,cc7,#1 ; also set ICC3
- subicc.p gr5,#2,gr0,icc1
- beqlr icc3,#0
-
- # now do 2-byte remnant
- setlos #2,gr7
- addi.p gr4,#2,gr4
- cknc icc1,cc7
- csthu.p gr12,@(gr4,gr7) ,cc7,#1
- csubcc gr5,gr7,gr5 ,cc7,#1 ; also set ICC3
- subicc.p gr5,#1,gr0,icc0
- beqlr icc3,#0
-
- # now do 1-byte remnant
- setlos #0,gr7
- addi.p gr4,#2,gr4
- cknc icc0,cc7
- cstb.p gr12,@(gr4,gr0) ,cc7,#1
- bralr
-__memset_end:
-
- .size memset, __memset_end-memset
-
-###############################################################################
-#
-# clear memory in userspace
-# - return the number of bytes that could not be cleared (0 on complete success)
-#
-# long __memset_user(void *p, size_t count)
-#
-###############################################################################
- .globl __memset_user, __memset_user_error_lr, __memset_user_error_handler
- .type __memset_user,@function
-__memset_user:
- movsg lr,gr11
-
- # abuse memset to do the dirty work
- or.p gr9,gr9,gr10
- setlos #0,gr9
- call memset
-__memset_user_error_lr:
- jmpl.p @(gr11,gr0)
- setlos #0,gr8
-
- # deal any exception generated by memset
- # GR4 - memset's address tracking pointer
- # GR7 - memset's step value (index register for store insns)
- # GR8 - memset's original start address
- # GR10 - memset's original count
-__memset_user_error_handler:
- add.p gr4,gr7,gr4
- add gr8,gr10,gr8
- jmpl.p @(gr11,gr0)
- sub gr8,gr4,gr8 ; we return the amount left uncleared
-
- .size __memset_user, .-__memset_user
diff --git a/arch/frv/lib/outsl_ns.S b/arch/frv/lib/outsl_ns.S
deleted file mode 100644
index 4cd4c46a6966..000000000000
--- a/arch/frv/lib/outsl_ns.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/* outsl_ns.S: output array of 4b words to device without byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __outsl_ns(unsigned int port, const void *buf, int n)
-#
-###############################################################################
- .globl __outsl_ns
- .type __outsl_ns,@function
-__outsl_ns:
- andicc.p gr9,#3,gr0,icc0
- setlos #4,gr4
- bne icc0,#0,__outsl_ns_misaligned
- subi gr9,#4,gr9
-0:
- ldu.p @(gr9,gr4),gr5
- subicc gr10,#1,gr10,icc0
- sti.p gr5,@(gr8,#0)
- bhi icc0,#2,0b
-
- membar
- bralr
-
-__outsl_ns_misaligned:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldubu @(gr9,gr4),gr5
- ldubu.p @(gr9,gr4),gr6
- slli gr5,#8,gr5
- ldubu.p @(gr9,gr4),gr7
- or gr5,gr6,gr5
- ldubu.p @(gr9,gr4),gr6
- slli gr5,#16,gr5
- slli.p gr7,#8,gr7
- or gr5,gr6,gr5
- subicc.p gr10,#1,gr10,icc0
- or gr5,gr7,gr5
-
- sti.p gr5,@(gr8,#0)
- bhi icc0,#2,0b
-
- membar
- bralr
-
- .size __outsl_ns, .-__outsl_ns
diff --git a/arch/frv/lib/outsl_sw.S b/arch/frv/lib/outsl_sw.S
deleted file mode 100644
index 7eb56d35a956..000000000000
--- a/arch/frv/lib/outsl_sw.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/* outsl_ns.S: output array of 4b words to device with byte swapping
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# void __outsl_sw(unsigned int port, const void *buf, int n)
-#
-###############################################################################
- .globl __outsl_sw
- .type __outsl_sw,@function
-__outsl_sw:
- subi.p gr9,#1,gr9
- setlos #1,gr4
-0:
- ldubu @(gr9,gr4),gr5
- ldubu @(gr9,gr4),gr6
- slli gr6,#8,gr6
- ldubu.p @(gr9,gr4),gr7
- or gr5,gr6,gr5
- ldubu.p @(gr9,gr4),gr6
- slli gr7,#16,gr7
- slli.p gr6,#24,gr6
- or gr5,gr7,gr5
- subicc.p gr10,#1,gr10,icc0
- or gr5,gr6,gr5
-
- sti.p gr5,@(gr8,#0)
- bhi icc0,#2,0b
-
- membar
- bralr
-
- .size __outsl_sw, .-__outsl_sw
diff --git a/arch/frv/mb93090-mb00/Makefile b/arch/frv/mb93090-mb00/Makefile
deleted file mode 100644
index bcb03ebb3583..000000000000
--- a/arch/frv/mb93090-mb00/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the MB93090-MB00 motherboard stuff
-#
-
-ifeq "$(CONFIG_PCI)" "y"
-obj-y := pci-frv.o pci-irq.o pci-vdk.o
-
-ifeq "$(CONFIG_MMU)" "y"
-obj-y += pci-dma.o
-else
-obj-y += pci-dma-nommu.o
-endif
-endif
-
-obj-$(CONFIG_MTD) += flash.o
diff --git a/arch/frv/mb93090-mb00/flash.c b/arch/frv/mb93090-mb00/flash.c
deleted file mode 100644
index e1cf802d1639..000000000000
--- a/arch/frv/mb93090-mb00/flash.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Flash mappings for the MB93090-MB00 motherboard
- *
- * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#define MB93090_BOOTROM_ADDR 0xFF000000 /* Boot ROM */
-#define MB93090_BOOTROM_SIZE (2 * 1024 * 1024)
-#define MB93090_USERROM_ADDR 0xFF200000 /* User ROM */
-#define MB93090_USERROM_SIZE (2 * 1024 * 1024)
-
-/*
- * default MTD partition table for both main flash devices, expected to be
- * overridden by RedBoot
- */
-static struct mtd_partition mb93090_partitions[] = {
- {
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0,
- }
-};
-
-/*
- * Definition of the MB93090 Boot ROM (on the CPU card)
- */
-static struct physmap_flash_data mb93090_bootrom_data = {
- .width = 2,
- .nr_parts = 2,
- .parts = mb93090_partitions,
-};
-
-static struct resource mb93090_bootrom_resource = {
- .start = MB93090_BOOTROM_ADDR,
- .end = MB93090_BOOTROM_ADDR + MB93090_BOOTROM_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mb93090_bootrom = {
- .name = "physmap-flash",
- .id = 0,
- .dev.platform_data = &mb93090_bootrom_data,
- .num_resources = 1,
- .resource = &mb93090_bootrom_resource,
-};
-
-/*
- * Definition of the MB93090 User ROM definition (on the motherboard)
- */
-static struct physmap_flash_data mb93090_userrom_data = {
- .width = 2,
- .nr_parts = 2,
- .parts = mb93090_partitions,
-};
-
-static struct resource mb93090_userrom_resource = {
- .start = MB93090_USERROM_ADDR,
- .end = MB93090_USERROM_ADDR + MB93090_USERROM_SIZE - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mb93090_userrom = {
- .name = "physmap-flash",
- .id = 1,
- .dev.platform_data = &mb93090_userrom_data,
- .num_resources = 1,
- .resource = &mb93090_userrom_resource,
-};
-
-/*
- * register the MB93090 flashes
- */
-static int __init mb93090_mtd_init(void)
-{
- platform_device_register(&mb93090_bootrom);
- platform_device_register(&mb93090_userrom);
- return 0;
-}
-
-module_init(mb93090_mtd_init);
diff --git a/arch/frv/mb93090-mb00/pci-dma-nommu.c b/arch/frv/mb93090-mb00/pci-dma-nommu.c
deleted file mode 100644
index 4a96de7f0af4..000000000000
--- a/arch/frv/mb93090-mb00/pci-dma-nommu.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* pci-dma-nommu.c: Dynamic DMA mapping support for the FRV
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Woodhouse (dwmw2@infradead.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/export.h>
-#include <linux/dma-mapping.h>
-#include <linux/list.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-
-#if 1
-#define DMA_SRAM_START dma_coherent_mem_start
-#define DMA_SRAM_END dma_coherent_mem_end
-#else // Use video RAM on Matrox
-#define DMA_SRAM_START 0xe8900000
-#define DMA_SRAM_END 0xe8a00000
-#endif
-
-struct dma_alloc_record {
- struct list_head list;
- unsigned long ofs;
- unsigned long len;
-};
-
-static DEFINE_SPINLOCK(dma_alloc_lock);
-static LIST_HEAD(dma_alloc_list);
-
-static void *frv_dma_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
- gfp_t gfp, unsigned long attrs)
-{
- struct dma_alloc_record *new;
- struct list_head *this = &dma_alloc_list;
- unsigned long flags;
- unsigned long start = DMA_SRAM_START;
- unsigned long end;
-
- if (!DMA_SRAM_START) {
- printk("%s called without any DMA area reserved!\n", __func__);
- return NULL;
- }
-
- new = kmalloc(sizeof (*new), GFP_ATOMIC);
- if (!new)
- return NULL;
-
- /* Round up to a reasonable alignment */
- new->len = (size + 31) & ~31;
-
- spin_lock_irqsave(&dma_alloc_lock, flags);
-
- list_for_each (this, &dma_alloc_list) {
- struct dma_alloc_record *this_r = list_entry(this, struct dma_alloc_record, list);
- end = this_r->ofs;
-
- if (end - start >= size)
- goto gotone;
-
- start = this_r->ofs + this_r->len;
- }
- /* Reached end of list. */
- end = DMA_SRAM_END;
- this = &dma_alloc_list;
-
- if (end - start >= size) {
- gotone:
- new->ofs = start;
- list_add_tail(&new->list, this);
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
-
- *dma_handle = start;
- return (void *)start;
- }
-
- kfree(new);
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
- return NULL;
-}
-
-static void frv_dma_free(struct device *hwdev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- struct dma_alloc_record *rec;
- unsigned long flags;
-
- spin_lock_irqsave(&dma_alloc_lock, flags);
-
- list_for_each_entry(rec, &dma_alloc_list, list) {
- if (rec->ofs == dma_handle) {
- list_del(&rec->list);
- kfree(rec);
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
- return;
- }
- }
- spin_unlock_irqrestore(&dma_alloc_lock, flags);
- BUG();
-}
-
-static int frv_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(direction == DMA_NONE);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- return nents;
-
- for_each_sg(sglist, sg, nents, i) {
- frv_cache_wback_inv(sg_dma_address(sg),
- sg_dma_address(sg) + sg_dma_len(sg));
- }
-
- return nents;
-}
-
-static dma_addr_t frv_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction, unsigned long attrs)
-{
- BUG_ON(direction == DMA_NONE);
-
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- flush_dcache_page(page);
-
- return (dma_addr_t) page_to_phys(page) + offset;
-}
-
-static void frv_dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-static void frv_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-
-static int frv_dma_supported(struct device *dev, u64 mask)
-{
- /*
- * we fall back to GFP_DMA when the mask isn't all 1s,
- * so we can't guarantee allocations that must be
- * within a tighter range than GFP_DMA..
- */
- if (mask < 0x00ffffff)
- return 0;
- return 1;
-}
-
-const struct dma_map_ops frv_dma_ops = {
- .alloc = frv_dma_alloc,
- .free = frv_dma_free,
- .map_page = frv_dma_map_page,
- .map_sg = frv_dma_map_sg,
- .sync_single_for_device = frv_dma_sync_single_for_device,
- .sync_sg_for_device = frv_dma_sync_sg_for_device,
- .dma_supported = frv_dma_supported,
-};
-EXPORT_SYMBOL(frv_dma_ops);
diff --git a/arch/frv/mb93090-mb00/pci-dma.c b/arch/frv/mb93090-mb00/pci-dma.c
deleted file mode 100644
index e7130abc0dae..000000000000
--- a/arch/frv/mb93090-mb00/pci-dma.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* pci-dma.c: Dynamic DMA mapping support for the FRV CPUs that have MMUs
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/dma-mapping.h>
-#include <linux/list.h>
-#include <linux/pci.h>
-#include <linux/export.h>
-#include <linux/highmem.h>
-#include <linux/scatterlist.h>
-#include <asm/io.h>
-
-static void *frv_dma_alloc(struct device *hwdev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- void *ret;
-
- ret = consistent_alloc(gfp, size, dma_handle);
- if (ret)
- memset(ret, 0, size);
-
- return ret;
-}
-
-static void frv_dma_free(struct device *hwdev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- consistent_free(vaddr);
-}
-
-static int frv_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- unsigned long dampr2;
- void *vaddr;
- int i;
-
- BUG_ON(direction == DMA_NONE);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- return nents;
-
- dampr2 = __get_DAMPR(2);
-
- for_each_sg(sglist, sg, nents, i) {
- vaddr = kmap_atomic_primary(sg_page(sg));
-
- frv_dcache_writeback((unsigned long) vaddr,
- (unsigned long) vaddr + PAGE_SIZE);
-
- }
-
- kunmap_atomic_primary(vaddr);
- if (dampr2) {
- __set_DAMPR(2, dampr2);
- __set_IAMPR(2, dampr2);
- }
-
- return nents;
-}
-
-static dma_addr_t frv_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction, unsigned long attrs)
-{
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- flush_dcache_page(page);
-
- return (dma_addr_t) page_to_phys(page) + offset;
-}
-
-static void frv_dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-static void frv_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg, int nelems,
- enum dma_data_direction direction)
-{
- flush_write_buffers();
-}
-
-
-static int frv_dma_supported(struct device *dev, u64 mask)
-{
- /*
- * we fall back to GFP_DMA when the mask isn't all 1s,
- * so we can't guarantee allocations that must be
- * within a tighter range than GFP_DMA..
- */
- if (mask < 0x00ffffff)
- return 0;
- return 1;
-}
-
-const struct dma_map_ops frv_dma_ops = {
- .alloc = frv_dma_alloc,
- .free = frv_dma_free,
- .map_page = frv_dma_map_page,
- .map_sg = frv_dma_map_sg,
- .sync_single_for_device = frv_dma_sync_single_for_device,
- .sync_sg_for_device = frv_dma_sync_sg_for_device,
- .dma_supported = frv_dma_supported,
-};
-EXPORT_SYMBOL(frv_dma_ops);
diff --git a/arch/frv/mb93090-mb00/pci-frv.c b/arch/frv/mb93090-mb00/pci-frv.c
deleted file mode 100644
index c452ddb5620f..000000000000
--- a/arch/frv/mb93090-mb00/pci-frv.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* pci-frv.c: low-level PCI access routines
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from the i386 equivalent stuff
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/errno.h>
-
-#include "pci-frv.h"
-
-/*
- * We need to avoid collisions with `mirrored' VGA ports
- * and other strange ISA hardware, so we always want the
- * addresses to be allocated in the 0x000-0x0ff region
- * modulo 0x400.
- *
- * Why? Because some silly external IO cards only decode
- * the low 10 bits of the IO address. The 0x00-0xff region
- * is reserved for motherboard devices that decode all 16
- * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
- * but we want to try to avoid allocating at 0x2900-0x2bff
- * which might have be mirrored at 0x0100-0x03ff..
- */
-resource_size_t
-pcibios_align_resource(void *data, const struct resource *res,
- resource_size_t size, resource_size_t align)
-{
- resource_size_t start = res->start;
-
- if ((res->flags & IORESOURCE_IO) && (start & 0x300))
- start = (start + 0x3ff) & ~0x3ff;
-
- return start;
-}
-
-
-/*
- * Handle resources of PCI devices. If the world were perfect, we could
- * just allocate all the resource regions and do nothing more. It isn't.
- * On the other hand, we cannot just re-allocate all devices, as it would
- * require us to know lots of host bridge internals. So we attempt to
- * keep as much of the original configuration as possible, but tweak it
- * when it's found to be wrong.
- *
- * Known BIOS problems we have to work around:
- * - I/O or memory regions not configured
- * - regions configured, but not enabled in the command register
- * - bogus I/O addresses above 64K used
- * - expansion ROMs left enabled (this may sound harmless, but given
- * the fact the PCI specs explicitly allow address decoders to be
- * shared between expansion ROMs and other resource regions, it's
- * at least dangerous)
- *
- * Our solution:
- * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
- * This gives us fixed barriers on where we can allocate.
- * (2) Allocate resources for all enabled devices. If there is
- * a collision, just mark the resource as unallocated. Also
- * disable expansion ROMs during this step.
- * (3) Try to allocate resources for disabled devices. If the
- * resources were assigned correctly, everything goes well,
- * if they weren't, they won't disturb allocation of other
- * resources.
- * (4) Assign new addresses to resources which were either
- * not configured at all or misconfigured. If explicitly
- * requested by the user, configure expansion ROM address
- * as well.
- */
-
-static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
-{
- struct list_head *ln;
- struct pci_bus *bus;
- struct pci_dev *dev;
- int idx;
- struct resource *r;
-
- /* Depth-First Search on bus tree */
- for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
- bus = list_entry(ln, struct pci_bus, node);
- if ((dev = bus->self)) {
- for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
- r = &dev->resource[idx];
- if (!r->start)
- continue;
- pci_claim_bridge_resource(dev, idx);
- }
- }
- pcibios_allocate_bus_resources(&bus->children);
- }
-}
-
-static void __init pcibios_allocate_resources(int pass)
-{
- struct pci_dev *dev = NULL;
- int idx, disabled;
- u16 command;
- struct resource *r;
-
- for_each_pci_dev(dev) {
- pci_read_config_word(dev, PCI_COMMAND, &command);
- for(idx = 0; idx < 6; idx++) {
- r = &dev->resource[idx];
- if (r->parent) /* Already allocated */
- continue;
- if (!r->start) /* Address not assigned at all */
- continue;
- if (r->flags & IORESOURCE_IO)
- disabled = !(command & PCI_COMMAND_IO);
- else
- disabled = !(command & PCI_COMMAND_MEMORY);
- if (pass == disabled) {
- DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
- r->start, r->end, r->flags, disabled, pass);
- if (pci_claim_resource(dev, idx) < 0) {
- /* We'll assign a new address later */
- r->end -= r->start;
- r->start = 0;
- }
- }
- }
- if (!pass) {
- r = &dev->resource[PCI_ROM_RESOURCE];
- if (r->flags & IORESOURCE_ROM_ENABLE) {
- /* Turn the ROM off, leave the resource region, but keep it unregistered. */
- u32 reg;
- DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
- r->flags &= ~IORESOURCE_ROM_ENABLE;
- pci_read_config_dword(dev, dev->rom_base_reg, &reg);
- pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
- }
- }
- }
-}
-
-static void __init pcibios_assign_resources(void)
-{
- struct pci_dev *dev = NULL;
- int idx, err;
- struct resource *r;
-
- for_each_pci_dev(dev) {
- int class = dev->class >> 8;
-
- /* Don't touch classless devices and host bridges */
- if (!class || class == PCI_CLASS_BRIDGE_HOST)
- continue;
-
- for(idx=0; idx<6; idx++) {
- r = &dev->resource[idx];
-
- /*
- * Don't touch IDE controllers and I/O ports of video cards!
- */
- if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
- (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
- continue;
-
- /*
- * We shall assign a new address to this resource, either because
- * the BIOS forgot to do so or because we have decided the old
- * address was unusable for some reason.
- */
- if (!r->start && r->end) {
- err = pci_assign_resource(dev, idx);
- if (err)
- dev_err(&dev->dev,
- "Failed to assign new address to %d\n",
- idx);
- }
- }
- }
-}
-
-void __init pcibios_resource_survey(void)
-{
- DBG("PCI: Allocating resources\n");
- pcibios_allocate_bus_resources(&pci_root_buses);
- pcibios_allocate_resources(0);
- pcibios_allocate_resources(1);
- pcibios_assign_resources();
-}
diff --git a/arch/frv/mb93090-mb00/pci-frv.h b/arch/frv/mb93090-mb00/pci-frv.h
deleted file mode 100644
index 41fbb6bae558..000000000000
--- a/arch/frv/mb93090-mb00/pci-frv.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Low-Level PCI Access for FRV machines.
- *
- * (c) 1999 Martin Mares <mj@ucw.cz>
- */
-
-#include <asm/sections.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-extern unsigned int __nongpreldata pci_probe;
-
-/* pci-frv.c */
-
-void pcibios_resource_survey(void);
-
-/* pci-vdk.c */
-
-extern struct pci_ops *__nongpreldata pci_root_ops;
-
-/* pci-irq.c */
-extern unsigned int pcibios_irq_mask;
-
-void pcibios_irq_init(void);
-void pcibios_fixup_irqs(void);
-void pcibios_enable_irq(struct pci_dev *dev);
diff --git a/arch/frv/mb93090-mb00/pci-irq.c b/arch/frv/mb93090-mb00/pci-irq.c
deleted file mode 100644
index a40aa8663056..000000000000
--- a/arch/frv/mb93090-mb00/pci-irq.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* pci-irq.c: PCI IRQ routing on the FRV motherboard
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * derived from: arch/i386/kernel/pci-irq.c: (c) 1999--2000 Martin Mares <mj@suse.cz>
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-
-#include <asm/io.h>
-#include <asm/smp.h>
-
-#include "pci-frv.h"
-
-/*
- * DEVICE DEVNO INT#A INT#B INT#C INT#D
- * ======= ======= ======= ======= ======= =======
- * MB86943 0 fpga.10 - - -
- * RTL8029 16 fpga.12 - - -
- * SLOT 1 19 fpga.6 fpga.5 fpga.4 fpga.3
- * SLOT 2 18 fpga.5 fpga.4 fpga.3 fpga.6
- * SLOT 3 17 fpga.4 fpga.3 fpga.6 fpga.5
- *
- */
-
-static const uint8_t __initconst pci_bus0_irq_routing[32][4] = {
- [0 ] = { IRQ_FPGA_MB86943_PCI_INTA },
- [16] = { IRQ_FPGA_RTL8029_INTA },
- [17] = { IRQ_FPGA_PCI_INTC, IRQ_FPGA_PCI_INTD, IRQ_FPGA_PCI_INTA, IRQ_FPGA_PCI_INTB },
- [18] = { IRQ_FPGA_PCI_INTB, IRQ_FPGA_PCI_INTC, IRQ_FPGA_PCI_INTD, IRQ_FPGA_PCI_INTA },
- [19] = { IRQ_FPGA_PCI_INTA, IRQ_FPGA_PCI_INTB, IRQ_FPGA_PCI_INTC, IRQ_FPGA_PCI_INTD },
-};
-
-void __init pcibios_irq_init(void)
-{
-}
-
-void __init pcibios_fixup_irqs(void)
-{
- struct pci_dev *dev = NULL;
- uint8_t line, pin;
-
- for_each_pci_dev(dev) {
- pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
- if (pin) {
- dev->irq = pci_bus0_irq_routing[PCI_SLOT(dev->devfn)][pin - 1];
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
- }
- pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line);
- }
-}
-
-void pcibios_enable_irq(struct pci_dev *dev)
-{
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-}
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
deleted file mode 100644
index f211839e2cae..000000000000
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/* pci-vdk.c: MB93090-MB00 (VDK) PCI support
- *
- * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-
-#include <asm/segment.h>
-#include <asm/io.h>
-#include <asm/mb-regs.h>
-#include <asm/mb86943a.h>
-#include "pci-frv.h"
-
-unsigned int __nongpreldata pci_probe = 1;
-
-struct pci_ops *__nongpreldata pci_root_ops;
-
-/*
- * The accessible PCI window does not cover the entire CPU address space, but
- * there are devices we want to access outside of that window, so we need to
- * insert specific PCI bus resources instead of using the platform-level bus
- * resources directly for the PCI root bus.
- *
- * These are configured and inserted by pcibios_init() and are attached to the
- * root bus by pcibios_fixup_bus().
- */
-static struct resource pci_ioport_resource = {
- .name = "PCI IO",
- .start = 0,
- .end = IO_SPACE_LIMIT,
- .flags = IORESOURCE_IO,
-};
-
-static struct resource pci_iomem_resource = {
- .name = "PCI mem",
- .start = 0,
- .end = -1,
- .flags = IORESOURCE_MEM,
-};
-
-/*
- * Functions for accessing PCI configuration space
- */
-
-#define CONFIG_CMD(bus, dev, where) \
- (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
-
-#define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
-
-#define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
-#define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
-#define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
-
-#define __set_PciCfgDataB(A,V) \
- writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
-
-#define __set_PciCfgDataW(A,V) \
- writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
-
-#define __set_PciCfgDataL(A,V) \
- writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
-
-#define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
-
-#define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
-#define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
-
-static inline int __query(const struct pci_dev *dev)
-{
-// return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
-// return dev->bus->number==1;
-// return dev->bus->number==0 &&
-// (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
- return 0;
-}
-
-/*****************************************************************************/
-/*
- *
- */
-static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
- u32 *val)
-{
- u32 _value;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- _value = __get_PciBridgeDataL(where & ~3);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- _value = __get_PciCfgDataL(where & ~3);
- }
-
- switch (size) {
- case 1:
- _value = _value >> ((where & 3) * 8);
- break;
-
- case 2:
- _value = _value >> ((where & 2) * 8);
- break;
-
- case 4:
- break;
-
- default:
- BUG();
- }
-
- *val = _value;
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
- u32 value)
-{
- switch (size) {
- case 1:
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __set_PciBridgeDataB(where, value);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- __set_PciCfgDataB(where, value);
- }
- break;
-
- case 2:
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __set_PciBridgeDataW(where, value);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- __set_PciCfgDataW(where, value);
- }
- break;
-
- case 4:
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __set_PciBridgeDataL(where, value);
- }
- else {
- __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
- __set_PciCfgDataL(where, value);
- }
- break;
-
- default:
- BUG();
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops pci_direct_frv = {
- .read = pci_frv_read_config,
- .write = pci_frv_write_config,
-};
-
-/*
- * Before we decide to use direct hardware access mechanisms, we try to do some
- * trivial checks to ensure it at least _seems_ to be working -- we just test
- * whether bus 00 contains a host bridge (this is similar to checking
- * techniques used in XFree86, but ours should be more reliable since we
- * attempt to make use of direct access hints provided by the PCI BIOS).
- *
- * This should be close to trivial, but it isn't, because there are buggy
- * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
- */
-static int __init pci_sanity_check(struct pci_ops *o)
-{
- struct pci_bus bus; /* Fake bus and device */
- u32 id;
-
- bus.number = 0;
-
- if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
- printk("PCI: VDK Bridge device:vendor: %08x\n", id);
- if (id == 0x200e10cf)
- return 1;
- }
-
- printk("PCI: VDK Bridge: Sanity check failed\n");
- return 0;
-}
-
-static struct pci_ops * __init pci_check_direct(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- /* check if access works */
- if (pci_sanity_check(&pci_direct_frv)) {
- local_irq_restore(flags);
- printk("PCI: Using configuration frv\n");
-// request_mem_region(0xBE040000, 256, "FRV bridge");
-// request_mem_region(0xBFFFFFF4, 12, "PCI frv");
- return &pci_direct_frv;
- }
-
- local_irq_restore(flags);
- return NULL;
-}
-
-/*
- * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
- */
-
-static void __init pci_fixup_umc_ide(struct pci_dev *d)
-{
- /*
- * UM8886BF IDE controller sets region type bits incorrectly,
- * therefore they look like memory despite of them being I/O.
- */
- int i;
-
- printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
- for(i=0; i<4; i++)
- d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
-}
-
-static void pci_fixup_ide_bases(struct pci_dev *d)
-{
- int i;
-
- /*
- * PCI IDE controllers use non-standard I/O port decoding, respect it.
- */
- if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
- return;
- printk("PCI: IDE base address fixup for %s\n", pci_name(d));
- for(i=0; i<4; i++) {
- struct resource *r = &d->resource[i];
- if ((r->start & ~0x80) == 0x374) {
- r->start |= 2;
- r->end = r->start;
- }
- }
-}
-
-static void pci_fixup_ide_trash(struct pci_dev *d)
-{
- int i;
-
- /*
- * There exist PCI IDE controllers which have utter garbage
- * in first four base registers. Ignore that.
- */
- printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
- for(i=0; i<4; i++)
- d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
-}
-
-static void pci_fixup_latency(struct pci_dev *d)
-{
- /*
- * SiS 5597 and 5598 chipsets require latency timer set to
- * at most 32 to avoid lockups.
- */
- DBG("PCI: Setting max latency to 32\n");
- pcibios_max_latency = 32;
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
-
-/*
- * Called after each bus is probed, but before its children
- * are examined.
- */
-
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
-#if 0
- printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
-#endif
-
- pci_read_bridge_bases(bus);
-
- if (bus->number == 0) {
- struct pci_dev *dev;
- list_for_each_entry(dev, &bus->devices, bus_list) {
- if (dev->devfn == 0) {
- dev->resource[0].start = 0;
- dev->resource[0].end = 0;
- }
- }
- }
-}
-
-/*
- * Initialization. Try all known PCI access methods. Note that we support
- * using both PCI BIOS and direct access: in such cases, we use I/O ports
- * to access config space, but we still keep BIOS order of cards to be
- * compatible with 2.0.X. This should go away some day.
- */
-
-int __init pcibios_init(void)
-{
- struct pci_bus *bus;
- struct pci_ops *dir = NULL;
- LIST_HEAD(resources);
-
- if (!mb93090_mb00_detected)
- return -ENXIO;
-
- __reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP;
-
- __reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000;
- __reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000;
-
- *(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000;
- *(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000;
-
- __reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9;
- __reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9;
- __reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000;
- __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000;
- mb();
-
- /* enable PCI arbitration */
- __reg_MB86943_pci_arbiter = MB86943_PCIARB_EN;
-
- pci_ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
- pci_ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
- pci_ioport_resource.end += pci_ioport_resource.start;
-
- printk("PCI IO window: %08llx-%08llx\n",
- (unsigned long long) pci_ioport_resource.start,
- (unsigned long long) pci_ioport_resource.end);
-
- pci_iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
- pci_iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
- pci_iomem_resource.end += pci_iomem_resource.start;
-
- /* Reserve somewhere to write to flush posted writes. This is used by
- * __flush_PCI_writes() from asm/io.h to force the write FIFO in the
- * CPU-PCI bridge to flush as this doesn't happen automatically when a
- * read is performed on the MB93090 development kit motherboard.
- */
- pci_iomem_resource.start += 0x400;
-
- printk("PCI MEM window: %08llx-%08llx\n",
- (unsigned long long) pci_iomem_resource.start,
- (unsigned long long) pci_iomem_resource.end);
- printk("PCI DMA memory: %08lx-%08lx\n",
- dma_coherent_mem_start, dma_coherent_mem_end);
-
- if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
- panic("Unable to insert PCI IOMEM resource\n");
- if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
- panic("Unable to insert PCI IOPORT resource\n");
-
- if (!pci_probe)
- return -ENXIO;
-
- dir = pci_check_direct();
- if (dir)
- pci_root_ops = dir;
- else {
- printk("PCI: No PCI bus detected\n");
- return -ENXIO;
- }
-
- printk("PCI: Probing PCI hardware\n");
- pci_add_resource(&resources, &pci_ioport_resource);
- pci_add_resource(&resources, &pci_iomem_resource);
- bus = pci_scan_root_bus(NULL, 0, pci_root_ops, NULL, &resources);
-
- pcibios_irq_init();
- pcibios_fixup_irqs();
- pcibios_resource_survey();
- if (!bus)
- return 0;
-
- pci_bus_add_devices(bus);
- return 0;
-}
-
-arch_initcall(pcibios_init);
-
-char * __init pcibios_setup(char *str)
-{
- if (!strcmp(str, "off")) {
- pci_probe = 0;
- return NULL;
- }
- return str;
-}
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
- int err;
-
- if ((err = pci_enable_resources(dev, mask)) < 0)
- return err;
- if (!dev->msi_enabled)
- pcibios_enable_irq(dev);
- return 0;
-}
diff --git a/arch/frv/mm/Makefile b/arch/frv/mm/Makefile
deleted file mode 100644
index 1bca5ab8a6ab..000000000000
--- a/arch/frv/mm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Makefile for the arch-specific parts of the memory manager.
-#
-
-obj-y := init.o kmap.o
-
-obj-$(CONFIG_MMU) += \
- pgalloc.o highmem.o fault.o extable.o cache-page.o tlb-flush.o tlb-miss.o \
- mmu-context.o dma-alloc.o elf-fdpic.o
diff --git a/arch/frv/mm/cache-page.c b/arch/frv/mm/cache-page.c
deleted file mode 100644
index 8e09dae0ec3f..000000000000
--- a/arch/frv/mm/cache-page.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* cache-page.c: whole-page cache wrangling functions for MMU linux
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/highmem.h>
-#include <linux/module.h>
-#include <asm/pgalloc.h>
-
-/*****************************************************************************/
-/*
- * DCF takes a virtual address and the page may not currently have one
- * - temporarily hijack a kmap_atomic() slot and attach the page to it
- */
-void flush_dcache_page(struct page *page)
-{
- unsigned long dampr2;
- void *vaddr;
-
- dampr2 = __get_DAMPR(2);
-
- vaddr = kmap_atomic_primary(page);
-
- frv_dcache_writeback((unsigned long) vaddr, (unsigned long) vaddr + PAGE_SIZE);
-
- kunmap_atomic_primary(vaddr);
-
- if (dampr2) {
- __set_DAMPR(2, dampr2);
- __set_IAMPR(2, dampr2);
- }
-
-} /* end flush_dcache_page() */
-
-EXPORT_SYMBOL(flush_dcache_page);
-
-/*****************************************************************************/
-/*
- * ICI takes a virtual address and the page may not currently have one
- * - so we temporarily attach the page to a bit of virtual space so that is can be flushed
- */
-void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
- unsigned long start, unsigned long len)
-{
- unsigned long dampr2;
- void *vaddr;
-
- dampr2 = __get_DAMPR(2);
-
- vaddr = kmap_atomic_primary(page);
-
- start = (start & ~PAGE_MASK) | (unsigned long) vaddr;
- frv_cache_wback_inv(start, start + len);
-
- kunmap_atomic_primary(vaddr);
-
- if (dampr2) {
- __set_DAMPR(2, dampr2);
- __set_IAMPR(2, dampr2);
- }
-
-} /* end flush_icache_user_range() */
-
-EXPORT_SYMBOL(flush_icache_user_range);
diff --git a/arch/frv/mm/dma-alloc.c b/arch/frv/mm/dma-alloc.c
deleted file mode 100644
index e701aa9e6a14..000000000000
--- a/arch/frv/mm/dma-alloc.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* dma-alloc.c: consistent DMA memory allocation
- *
- * Derived from arch/ppc/mm/cachemap.c
- *
- * PowerPC version derived from arch/arm/mm/consistent.c
- * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
- *
- * linux/arch/arm/mm/consistent.c
- *
- * Copyright (C) 2000 Russell King
- *
- * Consistent memory allocators. Used for DMA devices that want to
- * share uncached memory with the processor core. The function return
- * is the virtual address and 'dma_handle' is the physical address.
- * Mostly stolen from the ARM port, with some changes for PowerPC.
- * -- Dan
- * Modified for 36-bit support. -Matt
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/stddef.h>
-#include <linux/vmalloc.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/hardirq.h>
-#include <linux/gfp.h>
-
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/mmu.h>
-#include <linux/uaccess.h>
-#include <asm/smp.h>
-
-static int map_page(unsigned long va, unsigned long pa, pgprot_t prot)
-{
- pgd_t *pge;
- pud_t *pue;
- pmd_t *pme;
- pte_t *pte;
- int err = -ENOMEM;
-
- /* Use upper 10 bits of VA to index the first level map */
- pge = pgd_offset_k(va);
- pue = pud_offset(pge, va);
- pme = pmd_offset(pue, va);
-
- /* Use middle 10 bits of VA to index the second-level map */
- pte = pte_alloc_kernel(pme, va);
- if (pte != 0) {
- err = 0;
- set_pte(pte, mk_pte_phys(pa & PAGE_MASK, prot));
- }
-
- return err;
-}
-
-/*
- * This function will allocate the requested contiguous pages and
- * map them into the kernel's vmalloc() space. This is done so we
- * get unique mapping for these pages, outside of the kernel's 1:1
- * virtual:physical mapping. This is necessary so we can cover large
- * portions of the kernel with single large page TLB entries, and
- * still get unique uncached pages for consistent DMA.
- */
-void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
-{
- struct vm_struct *area;
- unsigned long page, va, pa;
- void *ret;
- int order, err, i;
-
- if (in_interrupt())
- BUG();
-
- /* only allocate page size areas */
- size = PAGE_ALIGN(size);
- order = get_order(size);
-
- page = __get_free_pages(gfp, order);
- if (!page) {
- BUG();
- return NULL;
- }
-
- /* allocate some common virtual space to map the new pages */
- area = get_vm_area(size, VM_ALLOC);
- if (area == 0) {
- free_pages(page, order);
- return NULL;
- }
- va = VMALLOC_VMADDR(area->addr);
- ret = (void *) va;
-
- /* this gives us the real physical address of the first page */
- *dma_handle = pa = virt_to_bus((void *) page);
-
- /* set refcount=1 on all pages in an order>0 allocation so that vfree() will actually free
- * all pages that were allocated.
- */
- if (order > 0) {
- struct page *rpage = virt_to_page(page);
- split_page(rpage, order);
- }
-
- err = 0;
- for (i = 0; i < size && err == 0; i += PAGE_SIZE)
- err = map_page(va + i, pa + i, PAGE_KERNEL_NOCACHE);
-
- if (err) {
- vfree((void *) va);
- return NULL;
- }
-
- /* we need to ensure that there are no cachelines in use, or worse dirty in this area
- * - can't do until after virtual address mappings are created
- */
- frv_cache_invalidate(va, va + size);
-
- return ret;
-}
-
-/*
- * free page(s) as defined by the above mapping.
- */
-void consistent_free(void *vaddr)
-{
- if (in_interrupt())
- BUG();
- vfree(vaddr);
-}
-
-/*
- * make an area consistent.
- */
-void consistent_sync(void *vaddr, size_t size, int direction)
-{
- unsigned long start = (unsigned long) vaddr;
- unsigned long end = start + size;
-
- switch (direction) {
- case PCI_DMA_NONE:
- BUG();
- case PCI_DMA_FROMDEVICE: /* invalidate only */
- frv_cache_invalidate(start, end);
- break;
- case PCI_DMA_TODEVICE: /* writeback only */
- frv_dcache_writeback(start, end);
- break;
- case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */
- frv_dcache_writeback(start, end);
- break;
- }
-}
-
-/*
- * consistent_sync_page make a page are consistent. identical
- * to consistent_sync, but takes a struct page instead of a virtual address
- */
-
-void consistent_sync_page(struct page *page, unsigned long offset,
- size_t size, int direction)
-{
- void *start;
-
- start = page_address(page) + offset;
- consistent_sync(start, size, direction);
-}
diff --git a/arch/frv/mm/elf-fdpic.c b/arch/frv/mm/elf-fdpic.c
deleted file mode 100644
index 46aa289c5102..000000000000
--- a/arch/frv/mm/elf-fdpic.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* elf-fdpic.c: ELF FDPIC memory layout management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/mm.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/elf-fdpic.h>
-#include <asm/mman.h>
-
-/*****************************************************************************/
-/*
- * lay out the userspace VM according to our grand design
- */
-#ifdef CONFIG_MMU
-void elf_fdpic_arch_lay_out_mm(struct elf_fdpic_params *exec_params,
- struct elf_fdpic_params *interp_params,
- unsigned long *start_stack,
- unsigned long *start_brk)
-{
- *start_stack = 0x02200000UL;
-
- /* if the only executable is a shared object, assume that it is an interpreter rather than
- * a true executable, and map it such that "ld.so --list" comes out right
- */
- if (!(interp_params->flags & ELF_FDPIC_FLAG_PRESENT) &&
- exec_params->hdr.e_type != ET_EXEC
- ) {
- exec_params->load_addr = PAGE_SIZE;
-
- *start_brk = 0x80000000UL;
- }
- else {
- exec_params->load_addr = 0x02200000UL;
-
- if ((exec_params->flags & ELF_FDPIC_FLAG_ARRANGEMENT) ==
- ELF_FDPIC_FLAG_INDEPENDENT
- ) {
- exec_params->flags &= ~ELF_FDPIC_FLAG_ARRANGEMENT;
- exec_params->flags |= ELF_FDPIC_FLAG_CONSTDISP;
- }
- }
-
-} /* end elf_fdpic_arch_lay_out_mm() */
-#endif
-
-/*****************************************************************************/
-/*
- * place non-fixed mmaps firstly in the bottom part of memory, working up, and then in the top part
- * of memory, working down
- */
-unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsigned long len,
- unsigned long pgoff, unsigned long flags)
-{
- struct vm_area_struct *vma;
- struct vm_unmapped_area_info info;
-
- if (len > TASK_SIZE)
- return -ENOMEM;
-
- /* handle MAP_FIXED */
- if (flags & MAP_FIXED)
- return addr;
-
- /* only honour a hint if we're not going to clobber something doing so */
- if (addr) {
- addr = PAGE_ALIGN(addr);
- vma = find_vma(current->mm, addr);
- if (TASK_SIZE - len >= addr &&
- (!vma || addr + len <= vm_start_gap(vma)))
- goto success;
- }
-
- /* search between the bottom of user VM and the stack grow area */
- info.flags = 0;
- info.length = len;
- info.low_limit = PAGE_SIZE;
- info.high_limit = (current->mm->start_stack - 0x00200000);
- info.align_mask = 0;
- info.align_offset = 0;
- addr = vm_unmapped_area(&info);
- if (!(addr & ~PAGE_MASK))
- goto success;
- VM_BUG_ON(addr != -ENOMEM);
-
- /* search from just above the WorkRAM area to the top of memory */
- info.low_limit = PAGE_ALIGN(0x80000000);
- info.high_limit = TASK_SIZE;
- addr = vm_unmapped_area(&info);
- if (!(addr & ~PAGE_MASK))
- goto success;
- VM_BUG_ON(addr != -ENOMEM);
-
-#if 0
- printk("[area] l=%lx (ENOMEM) f='%s'\n",
- len, filp ? filp->f_path.dentry->d_name.name : "");
-#endif
- return -ENOMEM;
-
- success:
-#if 0
- printk("[area] l=%lx ad=%lx f='%s'\n",
- len, addr, filp ? filp->f_path.dentry->d_name.name : "");
-#endif
- return addr;
-} /* end arch_get_unmapped_area() */
diff --git a/arch/frv/mm/extable.c b/arch/frv/mm/extable.c
deleted file mode 100644
index 77c0c5ba88bc..000000000000
--- a/arch/frv/mm/extable.c
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/frv/mm/extable.c
- */
-
-#include <linux/extable.h>
-#include <linux/spinlock.h>
-#include <linux/uaccess.h>
-
-extern const void __memset_end, __memset_user_error_lr, __memset_user_error_handler;
-extern const void __memcpy_end, __memcpy_user_error_lr, __memcpy_user_error_handler;
-extern spinlock_t modlist_lock;
-
-int fixup_exception(struct pt_regs *regs)
-{
- const struct exception_table_entry *extab;
- unsigned long pc = regs->pc;
-
- /* determine if the fault lay during a memcpy_user or a memset_user */
- if (regs->lr == (unsigned long) &__memset_user_error_lr &&
- (unsigned long) &memset <= pc && pc < (unsigned long) &__memset_end
- ) {
- /* the fault occurred in a protected memset
- * - we search for the return address (in LR) instead of the program counter
- * - it was probably during a clear_user()
- */
- regs->pc = (unsigned long) &__memset_user_error_handler;
- return 1;
- }
-
- if (regs->lr == (unsigned long) &__memcpy_user_error_lr &&
- (unsigned long) &memcpy <= pc && pc < (unsigned long) &__memcpy_end
- ) {
- /* the fault occurred in a protected memset
- * - we search for the return address (in LR) instead of the program counter
- * - it was probably during a copy_to/from_user()
- */
- regs->pc = (unsigned long) &__memcpy_user_error_handler;
- return 1;
- }
-
- extab = search_exception_tables(pc);
- if (extab) {
- regs->pc = extab->fixup;
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/frv/mm/fault.c b/arch/frv/mm/fault.c
deleted file mode 100644
index cbe7aec863e3..000000000000
--- a/arch/frv/mm/fault.c
+++ /dev/null
@@ -1,328 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/frv/mm/fault.c
- *
- * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
- * - Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68knommu/mm/fault.c
- * - Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>,
- * - Copyright (C) 2000 Lineo, Inc. (www.lineo.com)
- *
- * Based on:
- *
- * linux/arch/m68k/mm/fault.c
- *
- * Copyright (C) 1995 Hamish Macdonald
- */
-
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/uaccess.h>
-
-#include <asm/pgtable.h>
-#include <asm/gdb-stub.h>
-
-/*****************************************************************************/
-/*
- * This routine handles page faults. It determines the problem, and
- * then passes it off to one of the appropriate routines.
- */
-asmlinkage void do_page_fault(int datammu, unsigned long esr0, unsigned long ear0)
-{
- struct vm_area_struct *vma;
- struct mm_struct *mm;
- unsigned long _pme, lrai, lrad;
- unsigned long flags = 0;
- siginfo_t info;
- pgd_t *pge;
- pud_t *pue;
- pte_t *pte;
- int fault;
-
-#if 0
- const char *atxc[16] = {
- [0x0] = "mmu-miss", [0x8] = "multi-dat", [0x9] = "multi-sat",
- [0xa] = "tlb-miss", [0xc] = "privilege", [0xd] = "write-prot",
- };
-
- printk("do_page_fault(%d,%lx [%s],%lx)\n",
- datammu, esr0, atxc[esr0 >> 20 & 0xf], ear0);
-#endif
-
- mm = current->mm;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- *
- * This verifies that the fault happens in kernel space
- * and that the fault was a page not present (invalid) error
- */
- if (!user_mode(__frame) && (esr0 & ESR0_ATXC) == ESR0_ATXC_AMRTLB_MISS) {
- if (ear0 >= VMALLOC_START && ear0 < VMALLOC_END)
- goto kernel_pte_fault;
- if (ear0 >= PKMAP_BASE && ear0 < PKMAP_END)
- goto kernel_pte_fault;
- }
-
- info.si_code = SEGV_MAPERR;
-
- /*
- * If we're in an interrupt or have no user
- * context, we must not take the fault..
- */
- if (faulthandler_disabled() || !mm)
- goto no_context;
-
- if (user_mode(__frame))
- flags |= FAULT_FLAG_USER;
-
- down_read(&mm->mmap_sem);
-
- vma = find_vma(mm, ear0);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= ear0)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
-
- if (user_mode(__frame)) {
- /*
- * accessing the stack below %esp is always a bug.
- * The "+ 32" is there due to some instructions (like
- * pusha) doing post-decrement on the stack and that
- * doesn't show up until later..
- */
- if ((ear0 & PAGE_MASK) + 2 * PAGE_SIZE < __frame->sp) {
-#if 0
- printk("[%d] ### Access below stack @%lx (sp=%lx)\n",
- current->pid, ear0, __frame->sp);
- show_registers(__frame);
- printk("[%d] ### Code: [%08lx] %02x %02x %02x %02x %02x %02x %02x %02x\n",
- current->pid,
- __frame->pc,
- ((u8*)__frame->pc)[0],
- ((u8*)__frame->pc)[1],
- ((u8*)__frame->pc)[2],
- ((u8*)__frame->pc)[3],
- ((u8*)__frame->pc)[4],
- ((u8*)__frame->pc)[5],
- ((u8*)__frame->pc)[6],
- ((u8*)__frame->pc)[7]
- );
-#endif
- goto bad_area;
- }
- }
-
- if (expand_stack(vma, ear0))
- goto bad_area;
-
-/*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
- good_area:
- info.si_code = SEGV_ACCERR;
- switch (esr0 & ESR0_ATXC) {
- default:
- /* handle write to write protected page */
- case ESR0_ATXC_WP_EXCEP:
-#ifdef TEST_VERIFY_AREA
- if (!(user_mode(__frame)))
- printk("WP fault at %08lx\n", __frame->pc);
-#endif
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- break;
-
- /* handle read from protected page */
- case ESR0_ATXC_PRIV_EXCEP:
- goto bad_area;
-
- /* handle read, write or exec on absent page
- * - can't support write without permitting read
- * - don't support execute without permitting read and vice-versa
- */
- case ESR0_ATXC_AMRTLB_MISS:
- if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
- goto bad_area;
- break;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
- fault = handle_mm_fault(vma, ear0, flags);
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
- if (fault & VM_FAULT_MAJOR)
- current->maj_flt++;
- else
- current->min_flt++;
-
- up_read(&mm->mmap_sem);
- return;
-
-/*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
- bad_area:
- up_read(&mm->mmap_sem);
-
- /* User mode accesses just cause a SIGSEGV */
- if (user_mode(__frame)) {
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
- info.si_addr = (void *) ear0;
- force_sig_info(SIGSEGV, &info, current);
- return;
- }
-
- no_context:
- /* are we prepared to handle this kernel fault? */
- if (fixup_exception(__frame))
- return;
-
-/*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- bust_spinlocks(1);
-
- if (ear0 < PAGE_SIZE)
- printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
- else
- printk(KERN_ALERT "Unable to handle kernel paging request");
- printk(" at virtual addr %08lx\n", ear0);
- printk(" PC : %08lx\n", __frame->pc);
- printk(" EXC : esr0=%08lx ear0=%08lx\n", esr0, ear0);
-
- asm("lrai %1,%0,#1,#0,#0" : "=&r"(lrai) : "r"(ear0));
- asm("lrad %1,%0,#1,#0,#0" : "=&r"(lrad) : "r"(ear0));
-
- printk(KERN_ALERT " LRAI: %08lx\n", lrai);
- printk(KERN_ALERT " LRAD: %08lx\n", lrad);
-
- __break_hijack_kernel_event();
-
- pge = pgd_offset(current->mm, ear0);
- pue = pud_offset(pge, ear0);
- _pme = pue->pue[0].ste[0];
-
- printk(KERN_ALERT " PGE : %8p { PME %08lx }\n", pge, _pme);
-
- if (_pme & xAMPRx_V) {
- unsigned long dampr, damlr, val;
-
- asm volatile("movsg dampr2,%0 ! movgs %2,dampr2 ! movsg damlr2,%1"
- : "=&r"(dampr), "=r"(damlr)
- : "r" (_pme | xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V)
- );
-
- pte = (pte_t *) damlr + __pte_index(ear0);
- val = pte_val(*pte);
-
- asm volatile("movgs %0,dampr2" :: "r" (dampr));
-
- printk(KERN_ALERT " PTE : %8p { %08lx }\n", pte, val);
- }
-
- die_if_kernel("Oops\n");
- do_exit(SIGKILL);
-
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
- out_of_memory:
- up_read(&mm->mmap_sem);
- if (!user_mode(__frame))
- goto no_context;
- pagefault_out_of_memory();
- return;
-
- do_sigbus:
- up_read(&mm->mmap_sem);
-
- /*
- * Send a sigbus, regardless of whether we were in kernel
- * or user mode.
- */
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (void *) ear0;
- force_sig_info(SIGBUS, &info, current);
-
- /* Kernel mode? Handle exceptions or die */
- if (!user_mode(__frame))
- goto no_context;
- return;
-
-/*
- * The fault was caused by a kernel PTE (such as installed by vmalloc or kmap)
- */
- kernel_pte_fault:
- {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Do _not_ use "tsk" here. We might be inside
- * an interrupt in the middle of a task switch..
- */
- int index = pgd_index(ear0);
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd = (pgd_t *) __get_TTBR();
- pgd = (pgd_t *)__va(pgd) + index;
- pgd_k = ((pgd_t *)(init_mm.pgd)) + index;
-
- if (!pgd_present(*pgd_k))
- goto no_context;
- //set_pgd(pgd, *pgd_k); /////// gcc ICE's on this line
-
- pud_k = pud_offset(pgd_k, ear0);
- if (!pud_present(*pud_k))
- goto no_context;
-
- pmd_k = pmd_offset(pud_k, ear0);
- if (!pmd_present(*pmd_k))
- goto no_context;
-
- pud = pud_offset(pgd, ear0);
- pmd = pmd_offset(pud, ear0);
- set_pmd(pmd, *pmd_k);
-
- pte_k = pte_offset_kernel(pmd_k, ear0);
- if (!pte_present(*pte_k))
- goto no_context;
- return;
- }
-} /* end do_page_fault() */
diff --git a/arch/frv/mm/highmem.c b/arch/frv/mm/highmem.c
deleted file mode 100644
index 45750fb65c49..000000000000
--- a/arch/frv/mm/highmem.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* highmem.c: arch-specific highmem stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/highmem.h>
-#include <linux/module.h>
-
-void *kmap(struct page *page)
-{
- might_sleep();
- if (!PageHighMem(page))
- return page_address(page);
- return kmap_high(page);
-}
-
-EXPORT_SYMBOL(kmap);
-
-void kunmap(struct page *page)
-{
- if (in_interrupt())
- BUG();
- if (!PageHighMem(page))
- return;
- kunmap_high(page);
-}
-
-EXPORT_SYMBOL(kunmap);
-
-void *kmap_atomic(struct page *page)
-{
- unsigned long paddr;
- int type;
-
- preempt_disable();
- pagefault_disable();
- type = kmap_atomic_idx_push();
- paddr = page_to_phys(page);
-
- switch (type) {
- /*
- * The first 4 primary maps are reserved for architecture code
- */
- case 0: return __kmap_atomic_primary(0, paddr, 6);
- case 1: return __kmap_atomic_primary(0, paddr, 7);
- case 2: return __kmap_atomic_primary(0, paddr, 8);
- case 3: return __kmap_atomic_primary(0, paddr, 9);
- case 4: return __kmap_atomic_primary(0, paddr, 10);
-
- case 5 ... 5 + NR_TLB_LINES - 1:
- return __kmap_atomic_secondary(type - 5, paddr);
-
- default:
- BUG();
- return NULL;
- }
-}
-EXPORT_SYMBOL(kmap_atomic);
-
-void __kunmap_atomic(void *kvaddr)
-{
- int type = kmap_atomic_idx();
- switch (type) {
- case 0: __kunmap_atomic_primary(0, 6); break;
- case 1: __kunmap_atomic_primary(0, 7); break;
- case 2: __kunmap_atomic_primary(0, 8); break;
- case 3: __kunmap_atomic_primary(0, 9); break;
- case 4: __kunmap_atomic_primary(0, 10); break;
-
- case 5 ... 5 + NR_TLB_LINES - 1:
- __kunmap_atomic_secondary(type - 5, kvaddr);
- break;
-
- default:
- BUG();
- }
- kmap_atomic_idx_pop();
- pagefault_enable();
- preempt_enable();
-}
-EXPORT_SYMBOL(__kunmap_atomic);
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
deleted file mode 100644
index cf464100e838..000000000000
--- a/arch/frv/mm/init.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* init.c: memory initialisation for FRV
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Derived from:
- * - linux/arch/m68knommu/mm/init.c
- * - Copyright (C) 1998 D. Jeff Dionne <jeff@lineo.ca>, Kenneth Albanowski <kjahds@kjahds.com>,
- * - Copyright (C) 2000 Lineo, Inc. (www.lineo.com)
- * - linux/arch/m68k/mm/init.c
- * - Copyright (C) 1995 Hamish Macdonald
- */
-
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/sched/task.h>
-#include <linux/pagemap.h>
-#include <linux/gfp.h>
-#include <linux/swap.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/bootmem.h>
-#include <linux/highmem.h>
-#include <linux/module.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/mmu_context.h>
-#include <asm/virtconvert.h>
-#include <asm/sections.h>
-#include <asm/tlb.h>
-
-#undef DEBUG
-
-/*
- * ZERO_PAGE is a special page that is used for zero-initialized
- * data and COW.
- */
-unsigned long empty_zero_page;
-EXPORT_SYMBOL(empty_zero_page);
-
-/*****************************************************************************/
-/*
- * paging_init() continues the virtual memory environment setup which
- * was begun by the code in arch/head.S.
- * The parameters are pointers to where to stick the starting and ending
- * addresses of available kernel virtual memory.
- */
-void __init paging_init(void)
-{
- unsigned long zones_size[MAX_NR_ZONES] = {0, };
-
- /* allocate some pages for kernel housekeeping tasks */
- empty_zero_page = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
-
- memset((void *) empty_zero_page, 0, PAGE_SIZE);
-
-#ifdef CONFIG_HIGHMEM
- if (get_num_physpages() - num_mappedpages) {
- pgd_t *pge;
- pud_t *pue;
- pmd_t *pme;
-
- pkmap_page_table = alloc_bootmem_pages(PAGE_SIZE);
-
- pge = swapper_pg_dir + pgd_index_k(PKMAP_BASE);
- pue = pud_offset(pge, PKMAP_BASE);
- pme = pmd_offset(pue, PKMAP_BASE);
- __set_pmd(pme, virt_to_phys(pkmap_page_table) | _PAGE_TABLE);
- }
-#endif
-
- /* distribute the allocatable pages across the various zones and pass them to the allocator
- */
- zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
-#ifdef CONFIG_HIGHMEM
- zones_size[ZONE_HIGHMEM] = get_num_physpages() - num_mappedpages;
-#endif
-
- free_area_init(zones_size);
-
-#ifdef CONFIG_MMU
- /* initialise init's MMU context */
- init_new_context(&init_task, &init_mm);
-#endif
-
-} /* end paging_init() */
-
-/*****************************************************************************/
-/*
- *
- */
-void __init mem_init(void)
-{
- unsigned long code_size = _etext - _stext;
-
- /* this will put all low memory onto the freelists */
- free_all_bootmem();
-#if defined(CONFIG_MMU) && defined(CONFIG_HIGHMEM)
- {
- unsigned long pfn;
-
- for (pfn = get_num_physpages() - 1;
- pfn >= num_mappedpages; pfn--)
- free_highmem_page(&mem_map[pfn]);
- }
-#endif
-
- mem_init_print_info(NULL);
- if (rom_length > 0 && rom_length >= code_size)
- printk("Memory available: %luKiB/%luKiB ROM\n",
- (rom_length - code_size) >> 10, rom_length >> 10);
-} /* end mem_init() */
-
-/*****************************************************************************/
-/*
- * free the memory that was only required for initialisation
- */
-void free_initmem(void)
-{
-#if defined(CONFIG_RAMKERNEL) && !defined(CONFIG_PROTECT_KERNEL)
- free_initmem_default(-1);
-#endif
-} /* end free_initmem() */
-
-/*****************************************************************************/
-/*
- * free the initial ramdisk memory
- */
-#ifdef CONFIG_BLK_DEV_INITRD
-void __init free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_reserved_area((void *)start, (void *)end, -1, "initrd");
-} /* end free_initrd_mem() */
-#endif
diff --git a/arch/frv/mm/kmap.c b/arch/frv/mm/kmap.c
deleted file mode 100644
index e9217e605aa8..000000000000
--- a/arch/frv/mm/kmap.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* kmap.c: ioremapping handlers
- *
- * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/m68k/mm/kmap.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/vmalloc.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-
-#undef DEBUG
-
-/*****************************************************************************/
-/*
- * Map some physical address range into the kernel address space.
- */
-
-void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
-{
- return (void __iomem *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again
- */
-void iounmap(void volatile __iomem *addr)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
-{
-}
diff --git a/arch/frv/mm/mmu-context.c b/arch/frv/mm/mmu-context.c
deleted file mode 100644
index 16946a58f64d..000000000000
--- a/arch/frv/mm/mmu-context.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* mmu-context.c: MMU context allocation and management
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task.h>
-#include <linux/mm.h>
-#include <asm/tlbflush.h>
-
-#define NR_CXN 4096
-
-static unsigned long cxn_bitmap[NR_CXN / (sizeof(unsigned long) * 8)];
-static LIST_HEAD(cxn_owners_lru);
-static DEFINE_SPINLOCK(cxn_owners_lock);
-
-int __nongpreldata cxn_pinned = -1;
-
-
-/*****************************************************************************/
-/*
- * initialise a new context
- */
-int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- memset(&mm->context, 0, sizeof(mm->context));
- INIT_LIST_HEAD(&mm->context.id_link);
- mm->context.itlb_cached_pge = 0xffffffffUL;
- mm->context.dtlb_cached_pge = 0xffffffffUL;
-
- return 0;
-} /* end init_new_context() */
-
-/*****************************************************************************/
-/*
- * make sure a kernel MMU context has a CPU context number
- * - call with cxn_owners_lock held
- */
-static unsigned get_cxn(mm_context_t *ctx)
-{
- struct list_head *_p;
- mm_context_t *p;
- unsigned cxn;
-
- if (!list_empty(&ctx->id_link)) {
- list_move_tail(&ctx->id_link, &cxn_owners_lru);
- }
- else {
- /* find the first unallocated context number
- * - 0 is reserved for the kernel
- */
- cxn = find_next_zero_bit(cxn_bitmap, NR_CXN, 1);
- if (cxn < NR_CXN) {
- set_bit(cxn, cxn_bitmap);
- }
- else {
- /* none remaining - need to steal someone else's cxn */
- p = NULL;
- list_for_each(_p, &cxn_owners_lru) {
- p = list_entry(_p, mm_context_t, id_link);
- if (!p->id_busy && p->id != cxn_pinned)
- break;
- }
-
- BUG_ON(_p == &cxn_owners_lru);
-
- cxn = p->id;
- p->id = 0;
- list_del_init(&p->id_link);
- __flush_tlb_mm(cxn);
- }
-
- ctx->id = cxn;
- list_add_tail(&ctx->id_link, &cxn_owners_lru);
- }
-
- return ctx->id;
-} /* end get_cxn() */
-
-/*****************************************************************************/
-/*
- * restore the current TLB miss handler mapped page tables into the MMU context and set up a
- * mapping for the page directory
- */
-void change_mm_context(mm_context_t *old, mm_context_t *ctx, pgd_t *pgd)
-{
- unsigned long _pgd;
-
- _pgd = virt_to_phys(pgd);
-
- /* save the state of the outgoing MMU context */
- old->id_busy = 0;
-
- asm volatile("movsg scr0,%0" : "=r"(old->itlb_cached_pge));
- asm volatile("movsg dampr4,%0" : "=r"(old->itlb_ptd_mapping));
- asm volatile("movsg scr1,%0" : "=r"(old->dtlb_cached_pge));
- asm volatile("movsg dampr5,%0" : "=r"(old->dtlb_ptd_mapping));
-
- /* select an MMU context number */
- spin_lock(&cxn_owners_lock);
- get_cxn(ctx);
- ctx->id_busy = 1;
- spin_unlock(&cxn_owners_lock);
-
- asm volatile("movgs %0,cxnr" : : "r"(ctx->id));
-
- /* restore the state of the incoming MMU context */
- asm volatile("movgs %0,scr0" : : "r"(ctx->itlb_cached_pge));
- asm volatile("movgs %0,dampr4" : : "r"(ctx->itlb_ptd_mapping));
- asm volatile("movgs %0,scr1" : : "r"(ctx->dtlb_cached_pge));
- asm volatile("movgs %0,dampr5" : : "r"(ctx->dtlb_ptd_mapping));
-
- /* map the PGD into uncached virtual memory */
- asm volatile("movgs %0,ttbr" : : "r"(_pgd));
- asm volatile("movgs %0,dampr3"
- :: "r"(_pgd | xAMPRx_L | xAMPRx_M | xAMPRx_SS_16Kb |
- xAMPRx_S | xAMPRx_C | xAMPRx_V));
-
-} /* end change_mm_context() */
-
-/*****************************************************************************/
-/*
- * finished with an MMU context number
- */
-void destroy_context(struct mm_struct *mm)
-{
- mm_context_t *ctx = &mm->context;
-
- spin_lock(&cxn_owners_lock);
-
- if (!list_empty(&ctx->id_link)) {
- if (ctx->id == cxn_pinned)
- cxn_pinned = -1;
-
- list_del_init(&ctx->id_link);
- clear_bit(ctx->id, cxn_bitmap);
- __flush_tlb_mm(ctx->id);
- ctx->id = 0;
- }
-
- spin_unlock(&cxn_owners_lock);
-} /* end destroy_context() */
-
-/*****************************************************************************/
-/*
- * display the MMU context currently a process is currently using
- */
-#ifdef CONFIG_PROC_FS
-char *proc_pid_status_frv_cxnr(struct mm_struct *mm, char *buffer)
-{
- spin_lock(&cxn_owners_lock);
- buffer += sprintf(buffer, "CXNR: %u\n", mm->context.id);
- spin_unlock(&cxn_owners_lock);
-
- return buffer;
-} /* end proc_pid_status_frv_cxnr() */
-#endif
-
-/*****************************************************************************/
-/*
- * (un)pin a process's mm_struct's MMU context ID
- */
-int cxn_pin_by_pid(pid_t pid)
-{
- struct task_struct *tsk;
- struct mm_struct *mm = NULL;
- int ret;
-
- /* unpin if pid is zero */
- if (pid == 0) {
- cxn_pinned = -1;
- return 0;
- }
-
- ret = -ESRCH;
-
- /* get a handle on the mm_struct */
- read_lock(&tasklist_lock);
- tsk = find_task_by_vpid(pid);
- if (tsk) {
- ret = -EINVAL;
-
- task_lock(tsk);
- if (tsk->mm) {
- mm = tsk->mm;
- mmget(mm);
- ret = 0;
- }
- task_unlock(tsk);
- }
- read_unlock(&tasklist_lock);
-
- if (ret < 0)
- return ret;
-
- /* make sure it has a CXN and pin it */
- spin_lock(&cxn_owners_lock);
- cxn_pinned = get_cxn(&mm->context);
- spin_unlock(&cxn_owners_lock);
-
- mmput(mm);
- return 0;
-} /* end cxn_pin_by_pid() */
diff --git a/arch/frv/mm/pgalloc.c b/arch/frv/mm/pgalloc.c
deleted file mode 100644
index c9ed14f6c67d..000000000000
--- a/arch/frv/mm/pgalloc.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* pgalloc.c: page directory & page table allocation
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/gfp.h>
-#include <linux/mm.h>
-#include <linux/highmem.h>
-#include <linux/quicklist.h>
-#include <asm/pgalloc.h>
-#include <asm/page.h>
-#include <asm/cacheflush.h>
-
-pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__((aligned(PAGE_SIZE)));
-
-pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL);
- if (pte)
- clear_page(pte);
- return pte;
-}
-
-pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *page;
-
-#ifdef CONFIG_HIGHPTE
- page = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM, 0);
-#else
- page = alloc_pages(GFP_KERNEL, 0);
-#endif
- if (!page)
- return NULL;
-
- clear_highpage(page);
- if (!pgtable_page_ctor(page)) {
- __free_page(page);
- return NULL;
- }
- flush_dcache_page(page);
- return page;
-}
-
-void __set_pmd(pmd_t *pmdptr, unsigned long pmd)
-{
- unsigned long *__ste_p = pmdptr->ste;
- int loop;
-
- if (!pmd) {
- memset(__ste_p, 0, PME_SIZE);
- }
- else {
- BUG_ON(pmd & (0x3f00 | xAMPRx_SS | 0xe));
-
- for (loop = PME_SIZE; loop > 0; loop -= 4) {
- *__ste_p++ = pmd;
- pmd += __frv_PT_SIZE;
- }
- }
-
- frv_dcache_writeback((unsigned long) pmdptr, (unsigned long) (pmdptr + 1));
-}
-
-/*
- * List of all pgd's needed for non-PAE so it can invalidate entries
- * in both cached and uncached pgd's; not needed for PAE since the
- * kernel pmd is shared. If PAE were not to share the pmd a similar
- * tactic would be needed. This is essentially codepath-based locking
- * against pageattr.c; it is the unique case in which a valid change
- * of kernel pagetables can't be lazily synchronized by vmalloc faults.
- * vmalloc faults work because attached pagetables are never freed.
- * If the locking proves to be non-performant, a ticketing scheme with
- * checks at dup_mmap(), exec(), and other mmlist addition points
- * could be used. The locking scheme was chosen on the basis of
- * manfred's recommendations and having no core impact whatsoever.
- * -- nyc
- */
-DEFINE_SPINLOCK(pgd_lock);
-struct page *pgd_list;
-
-static inline void pgd_list_add(pgd_t *pgd)
-{
- struct page *page = virt_to_page(pgd);
- page->index = (unsigned long) pgd_list;
- if (pgd_list)
- set_page_private(pgd_list, (unsigned long) &page->index);
- pgd_list = page;
- set_page_private(page, (unsigned long)&pgd_list);
-}
-
-static inline void pgd_list_del(pgd_t *pgd)
-{
- struct page *next, **pprev, *page = virt_to_page(pgd);
- next = (struct page *) page->index;
- pprev = (struct page **) page_private(page);
- *pprev = next;
- if (next)
- set_page_private(next, (unsigned long) pprev);
-}
-
-void pgd_ctor(void *pgd)
-{
- unsigned long flags;
-
- if (PTRS_PER_PMD == 1)
- spin_lock_irqsave(&pgd_lock, flags);
-
- memcpy((pgd_t *) pgd + USER_PGDS_IN_LAST_PML4,
- swapper_pg_dir + USER_PGDS_IN_LAST_PML4,
- (PTRS_PER_PGD - USER_PGDS_IN_LAST_PML4) * sizeof(pgd_t));
-
- if (PTRS_PER_PMD > 1)
- return;
-
- pgd_list_add(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
- memset(pgd, 0, USER_PGDS_IN_LAST_PML4 * sizeof(pgd_t));
-}
-
-/* never called when PTRS_PER_PMD > 1 */
-void pgd_dtor(void *pgd)
-{
- unsigned long flags; /* can be called from interrupt context */
-
- spin_lock_irqsave(&pgd_lock, flags);
- pgd_list_del(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
-}
-
-pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- return quicklist_alloc(0, GFP_KERNEL, pgd_ctor);
-}
-
-void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- /* in the non-PAE case, clear_page_tables() clears user pgd entries */
- quicklist_free(0, pgd_dtor, pgd);
-}
-
-void __init pgtable_cache_init(void)
-{
-}
-
-void check_pgt_cache(void)
-{
- quicklist_trim(0, pgd_dtor, 25, 16);
-}
-
diff --git a/arch/frv/mm/tlb-flush.S b/arch/frv/mm/tlb-flush.S
deleted file mode 100644
index 79b3c70910ac..000000000000
--- a/arch/frv/mm/tlb-flush.S
+++ /dev/null
@@ -1,184 +0,0 @@
-/* tlb-flush.S: TLB flushing routines
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <asm/spr-regs.h>
-
-.macro DEBUG ch
-# sethi.p %hi(0xfeff9c00),gr4
-# setlo %lo(0xfeff9c00),gr4
-# setlos #\ch,gr5
-# stbi gr5,@(gr4,#0)
-# membar
-.endm
-
- .section .rodata
-
- # sizes corresponding to TPXR.LMAX
- .balign 1
-__tlb_lmax_sizes:
- .byte 0, 64, 0, 0
- .byte 0, 0, 0, 0
- .byte 0, 0, 0, 0
- .byte 0, 0, 0, 0
-
- .section .text
- .balign 4
-
-###############################################################################
-#
-# flush everything
-# - void __flush_tlb_all(void)
-#
-###############################################################################
- .globl __flush_tlb_all
- .type __flush_tlb_all,@function
-__flush_tlb_all:
- DEBUG 'A'
-
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # kill AMPR-cached TLB values
- movgs gr0,iamlr1
- movgs gr0,iampr1
- movgs gr0,damlr1
- movgs gr0,dampr1
-
- # find out how many lines there are
- movsg tpxr,gr5
- sethi.p %hi(__tlb_lmax_sizes),gr4
- srli gr5,#TPXR_LMAX_SHIFT,gr5
- setlo.p %lo(__tlb_lmax_sizes),gr4
- andi gr5,#TPXR_LMAX_SMASK,gr5
- ldub @(gr4,gr5),gr4
-
- # now, we assume that the TLB line step is page size in size
- setlos.p #PAGE_SIZE,gr5
- setlos #0,gr6
-1:
- tlbpr gr6,gr0,#6,#0
- subicc.p gr4,#1,gr4,icc0
- add gr6,gr5,gr6
- bne icc0,#2,1b
-
- DEBUG 'B'
- bralr
-
- .size __flush_tlb_all, .-__flush_tlb_all
-
-###############################################################################
-#
-# flush everything to do with one context
-# - void __flush_tlb_mm(unsigned long contextid [GR8])
-#
-###############################################################################
- .globl __flush_tlb_mm
- .type __flush_tlb_mm,@function
-__flush_tlb_mm:
- DEBUG 'M'
-
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # specify the context we want to flush
- movgs gr8,tplr
-
- # find out how many lines there are
- movsg tpxr,gr5
- sethi.p %hi(__tlb_lmax_sizes),gr4
- srli gr5,#TPXR_LMAX_SHIFT,gr5
- setlo.p %lo(__tlb_lmax_sizes),gr4
- andi gr5,#TPXR_LMAX_SMASK,gr5
- ldub @(gr4,gr5),gr4
-
- # now, we assume that the TLB line step is page size in size
- setlos.p #PAGE_SIZE,gr5
- setlos #0,gr6
-0:
- tlbpr gr6,gr0,#5,#0
- subicc.p gr4,#1,gr4,icc0
- add gr6,gr5,gr6
- bne icc0,#2,0b
-
- DEBUG 'N'
- bralr
-
- .size __flush_tlb_mm, .-__flush_tlb_mm
-
-###############################################################################
-#
-# flush a range of addresses from the TLB
-# - void __flush_tlb_page(unsigned long contextid [GR8],
-# unsigned long start [GR9])
-#
-###############################################################################
- .globl __flush_tlb_page
- .type __flush_tlb_page,@function
-__flush_tlb_page:
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # specify the context we want to flush
- movgs gr8,tplr
-
- # zap the matching TLB line and AMR values
- setlos #~(PAGE_SIZE-1),gr5
- and gr9,gr5,gr9
- tlbpr gr9,gr0,#5,#0
-
- bralr
-
- .size __flush_tlb_page, .-__flush_tlb_page
-
-###############################################################################
-#
-# flush a range of addresses from the TLB
-# - void __flush_tlb_range(unsigned long contextid [GR8],
-# unsigned long start [GR9],
-# unsigned long end [GR10])
-#
-###############################################################################
- .globl __flush_tlb_range
- .type __flush_tlb_range,@function
-__flush_tlb_range:
- # kill cached PGE value
- setlos #0xffffffff,gr4
- movgs gr4,scr0
- movgs gr4,scr1
-
- # specify the context we want to flush
- movgs gr8,tplr
-
- # round the start down to beginning of TLB line and end up to beginning of next TLB line
- setlos.p #~(PAGE_SIZE-1),gr5
- setlos #PAGE_SIZE,gr6
- subi.p gr10,#1,gr10
- and gr9,gr5,gr9
- and gr10,gr5,gr10
-2:
- tlbpr gr9,gr0,#5,#0
- subcc.p gr9,gr10,gr0,icc0
- add gr9,gr6,gr9
- bne icc0,#0,2b ; most likely a 1-page flush
-
- bralr
-
- .size __flush_tlb_range, .-__flush_tlb_range
diff --git a/arch/frv/mm/tlb-miss.S b/arch/frv/mm/tlb-miss.S
deleted file mode 100644
index f3ac019bb18b..000000000000
--- a/arch/frv/mm/tlb-miss.S
+++ /dev/null
@@ -1,629 +0,0 @@
-/* tlb-miss.S: TLB miss handlers
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/spr-regs.h>
-
- .section .text..tlbmiss
- .balign 4
-
- .globl __entry_insn_mmu_miss
-__entry_insn_mmu_miss:
- break
- nop
-
- .globl __entry_insn_mmu_exception
-__entry_insn_mmu_exception:
- break
- nop
-
- .globl __entry_data_mmu_miss
-__entry_data_mmu_miss:
- break
- nop
-
- .globl __entry_data_mmu_exception
-__entry_data_mmu_exception:
- break
- nop
-
-###############################################################################
-#
-# handle a lookup failure of one sort or another in a kernel TLB handler
-# On entry:
-# GR29 - faulting address
-# SCR2 - saved CCR
-#
-###############################################################################
- .type __tlb_kernel_fault,@function
-__tlb_kernel_fault:
- # see if we're supposed to re-enable single-step mode upon return
- sethi.p %hi(__break_tlb_miss_return_break),gr30
- setlo %lo(__break_tlb_miss_return_break),gr30
- movsg pcsr,gr31
-
- subcc gr31,gr30,gr0,icc0
- beq icc0,#0,__tlb_kernel_fault_sstep
-
- movsg scr2,gr30
- movgs gr30,ccr
- movgs gr29,scr2 /* save EAR0 value */
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi.p @(gr29,#0),gr29 /* restore GR29 */
-
- bra __entry_kernel_handle_mmu_fault
-
- # we've got to re-enable single-stepping
-__tlb_kernel_fault_sstep:
- sethi.p %hi(__break_tlb_miss_real_return_info),gr30
- setlo %lo(__break_tlb_miss_real_return_info),gr30
- lddi @(gr30,0),gr30
- movgs gr30,pcsr
- movgs gr31,psr
-
- movsg scr2,gr30
- movgs gr30,ccr
- movgs gr29,scr2 /* save EAR0 value */
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi.p @(gr29,#0),gr29 /* restore GR29 */
- bra __entry_kernel_handle_mmu_fault_sstep
-
- .size __tlb_kernel_fault, .-__tlb_kernel_fault
-
-###############################################################################
-#
-# handle a lookup failure of one sort or another in a user TLB handler
-# On entry:
-# GR28 - faulting address
-# SCR2 - saved CCR
-#
-###############################################################################
- .type __tlb_user_fault,@function
-__tlb_user_fault:
- # see if we're supposed to re-enable single-step mode upon return
- sethi.p %hi(__break_tlb_miss_return_break),gr30
- setlo %lo(__break_tlb_miss_return_break),gr30
- movsg pcsr,gr31
- subcc gr31,gr30,gr0,icc0
- beq icc0,#0,__tlb_user_fault_sstep
-
- movsg scr2,gr30
- movgs gr30,ccr
- bra __entry_uspace_handle_mmu_fault
-
- # we've got to re-enable single-stepping
-__tlb_user_fault_sstep:
- sethi.p %hi(__break_tlb_miss_real_return_info),gr30
- setlo %lo(__break_tlb_miss_real_return_info),gr30
- lddi @(gr30,0),gr30
- movgs gr30,pcsr
- movgs gr31,psr
- movsg scr2,gr30
- movgs gr30,ccr
- bra __entry_uspace_handle_mmu_fault_sstep
-
- .size __tlb_user_fault, .-__tlb_user_fault
-
-###############################################################################
-#
-# Kernel instruction TLB miss handler
-# On entry:
-# GR1 - kernel stack pointer
-# GR28 - saved exception frame pointer
-# GR29 - faulting address
-# GR31 - EAR0 ^ SCR0
-# SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR4 - mapped page table as matched by SCR0
-#
-###############################################################################
- .globl __entry_kernel_insn_tlb_miss
- .type __entry_kernel_insn_tlb_miss,@function
-__entry_kernel_insn_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__itlb_k_PTD_miss
-
-__itlb_k_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR4 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr4,gr30
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using IAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- # - need to check DAMR1 lest we cause an multiple-DAT-hit exception
- # - IAMPR1 has no WP bit, and we mustn't lose WP information
- movsg iampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__itlb_k_nopunt /* punt not required */
-
- movsg iamlr1,gr31
- movgs gr31,tplr /* set TPLR.CXN */
- tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
-
- movsg dampr1,gr31
- ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
- movgs gr31,tppr
- movsg iamlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_kernel_fault
-
-__itlb_k_nopunt:
-
- # assemble the new TLB entry
- and gr29,gr31,gr29
- movsg cxnr,gr31
- or gr29,gr31,gr29
- movgs gr29,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr29,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi @(gr29,#0),gr29
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__itlb_k_PTD_miss:
- srli gr29,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__itlb_k_bigpage
- movgs gr30,dampr4
- movgs gr31,scr0
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __itlb_k_PTD_mapped
-
-__itlb_k_bigpage:
- break
- nop
-
- .size __entry_kernel_insn_tlb_miss, .-__entry_kernel_insn_tlb_miss
-
-###############################################################################
-#
-# Kernel data TLB miss handler
-# On entry:
-# GR1 - kernel stack pointer
-# GR28 - saved exception frame pointer
-# GR29 - faulting address
-# GR31 - EAR0 ^ SCR1
-# SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR5 - mapped page table as matched by SCR1
-#
-###############################################################################
- .globl __entry_kernel_data_tlb_miss
- .type __entry_kernel_data_tlb_miss,@function
-__entry_kernel_data_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__dtlb_k_PTD_miss
-
-__dtlb_k_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR5 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr5,gr30
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using DAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- # - need to check IAMR1 lest we cause an multiple-DAT-hit exception
- movsg dampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__dtlb_k_nopunt /* punt not required */
-
- movsg damlr1,gr31
- movgs gr31,tplr /* set TPLR.CXN */
- tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
-
- movsg dampr1,gr31
- ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
- movgs gr31,tppr
- movsg damlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_kernel_fault
-
-__dtlb_k_nopunt:
-
- # assemble the new TLB entry
- and gr29,gr31,gr29
- movsg cxnr,gr31
- or gr29,gr31,gr29
- movgs gr29,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr29,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- sethi.p %hi(__kernel_current_task),gr29
- setlo %lo(__kernel_current_task),gr29
- ldi @(gr29,#0),gr29
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__dtlb_k_PTD_miss:
- srli gr29,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__dtlb_k_bigpage
- movgs gr30,dampr5
- movgs gr31,scr1
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __dtlb_k_PTD_mapped
-
-__dtlb_k_bigpage:
- break
- nop
-
- .size __entry_kernel_data_tlb_miss, .-__entry_kernel_data_tlb_miss
-
-###############################################################################
-#
-# Userspace instruction TLB miss handler (with PGE prediction)
-# On entry:
-# GR28 - faulting address
-# GR31 - EAR0 ^ SCR0
-# SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR4 - mapped page table as matched by SCR0
-#
-###############################################################################
- .globl __entry_user_insn_tlb_miss
- .type __entry_user_insn_tlb_miss,@function
-__entry_user_insn_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__itlb_u_PTD_miss
-
-__itlb_u_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR4 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr4,gr30
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using IAMR1/DAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- movsg dampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__itlb_u_nopunt /* punt not required */
-
- movsg dampr1,gr31
- movgs gr31,tppr
- movsg damlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_user_fault
-
-__itlb_u_nopunt:
-
- # assemble the new TLB entry
- and gr28,gr31,gr28
- movsg cxnr,gr31
- or gr28,gr31,gr28
- movgs gr28,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr28,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__itlb_u_PTD_miss:
- srli gr28,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__itlb_u_bigpage
- movgs gr30,dampr4
- movgs gr31,scr0
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __itlb_u_PTD_mapped
-
-__itlb_u_bigpage:
- break
- nop
-
- .size __entry_user_insn_tlb_miss, .-__entry_user_insn_tlb_miss
-
-###############################################################################
-#
-# Userspace data TLB miss handler
-# On entry:
-# GR28 - faulting address
-# GR31 - EAR0 ^ SCR1
-# SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
-# DAMR3 - mapped page directory
-# DAMR5 - mapped page table as matched by SCR1
-#
-###############################################################################
- .globl __entry_user_data_tlb_miss
- .type __entry_user_data_tlb_miss,@function
-__entry_user_data_tlb_miss:
-#if 0
- sethi.p %hi(0xe1200004),gr30
- setlo %lo(0xe1200004),gr30
- st gr0,@(gr30,gr0)
- sethi.p %hi(0xffc00100),gr30
- setlo %lo(0xffc00100),gr30
- sth gr30,@(gr30,gr0)
- membar
-#endif
-
- movsg ccr,gr30 /* save CCR */
- movgs gr30,scr2
-
- # see if the cached page table mapping is appropriate
- srlicc.p gr31,#26,gr0,icc0
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__dtlb_u_PTD_miss
-
-__dtlb_u_PTD_mapped:
- # access the PTD with EAR0[25:14]
- # - DAMLR5 points to the virtual address of the appropriate page table
- # - the PTD holds 4096 PTEs
- # - the PTD must be accessed uncached
- # - the PTE must be marked accessed if it was valid
- #
- and gr31,gr30,gr31
- movsg damlr5,gr30
-
-__dtlb_u_using_iPTD:
- add gr30,gr31,gr31
- ldi @(gr31,#0),gr30 /* fetch the PTE */
- andicc gr30,#_PAGE_PRESENT,gr0,icc0
- ori.p gr30,#_PAGE_ACCESSED,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
- sti.p gr30,@(gr31,#0) /* update the PTE */
- andi gr30,#~_PAGE_ACCESSED,gr30
-
- # we're using DAMR1 as an extra TLB entry
- # - punt the entry here (if valid) to the real TLB and then replace with the new PTE
- movsg dampr1,gr31
- andicc gr31,#xAMPRx_V,gr0,icc0
- setlos.p 0xfffff000,gr31
- beq icc0,#0,__dtlb_u_nopunt /* punt not required */
-
- movsg dampr1,gr31
- movgs gr31,tppr
- movsg damlr1,gr31 /* set TPLR.CXN */
- movgs gr31,tplr
- tlbpr gr31,gr0,#2,#0 /* save to the TLB */
- movsg tpxr,gr31 /* check the TLB write error flag */
- andicc.p gr31,#TPXR_E,gr0,icc0
- setlos #0xfffff000,gr31
- bne icc0,#0,__tlb_user_fault
-
-__dtlb_u_nopunt:
-
- # assemble the new TLB entry
- and gr28,gr31,gr28
- movsg cxnr,gr31
- or gr28,gr31,gr28
- movgs gr28,iamlr1 /* xAMLR = address | context number */
- movgs gr30,iampr1
- movgs gr28,damlr1
- movgs gr30,dampr1
-
- # return, restoring registers
- movsg scr2,gr30
- movgs gr30,ccr
- rett #0
- beq icc0,#3,0 /* prevent icache prefetch */
-
- # the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
- # appropriate page table and map that instead
- # - first of all, check the insn PGE cache - we may well get a hit there
- # - access the PGD with EAR0[31:26]
- # - DAMLR3 points to the virtual address of the page directory
- # - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
-__dtlb_u_PTD_miss:
- movsg scr0,gr31 /* consult the insn-PGE-cache key */
- xor gr28,gr31,gr31
- srlicc gr31,#26,gr0,icc0
- srli gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bne icc0,#0,__dtlb_u_iPGE_miss
-
- # what we're looking for is covered by the insn-PGE-cache
- setlos 0x3ffc,gr30
- and gr31,gr30,gr31
- movsg damlr4,gr30
- bra __dtlb_u_using_iPTD
-
-__dtlb_u_iPGE_miss:
- srli gr28,#26,gr31 /* calculate PGE offset */
- slli gr31,#8,gr31 /* and clear bottom bits */
-
- movsg damlr3,gr30
- ld @(gr31,gr30),gr30 /* access the PGE */
-
- andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
- andicc gr30,#xAMPRx_SS,gr0,icc1
-
- # map this PTD instead and record coverage address
- ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
- beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
- slli.p gr31,#18,gr31
- bne icc1,#0,__dtlb_u_bigpage
- movgs gr30,dampr5
- movgs gr31,scr1
-
- # we can now resume normal service
- setlos 0x3ffc,gr30
- srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
- bra __dtlb_u_PTD_mapped
-
-__dtlb_u_bigpage:
- break
- nop
-
- .size __entry_user_data_tlb_miss, .-__entry_user_data_tlb_miss
diff --git a/arch/h8300/include/asm/byteorder.h b/arch/h8300/include/asm/byteorder.h
index ecff2d1ca5a3..6eaa7ad5fc2c 100644
--- a/arch/h8300/include/asm/byteorder.h
+++ b/arch/h8300/include/asm/byteorder.h
@@ -2,7 +2,6 @@
#ifndef __H8300_BYTEORDER_H__
#define __H8300_BYTEORDER_H__
-#define __BIG_ENDIAN __ORDER_BIG_ENDIAN__
#include <linux/byteorder/big_endian.h>
#endif
diff --git a/arch/ia64/kernel/sys_ia64.c b/arch/ia64/kernel/sys_ia64.c
index 085adfcc74a4..9ebe1d633abc 100644
--- a/arch/ia64/kernel/sys_ia64.c
+++ b/arch/ia64/kernel/sys_ia64.c
@@ -139,7 +139,7 @@ int ia64_mmap_check(unsigned long addr, unsigned long len,
asmlinkage unsigned long
sys_mmap2 (unsigned long addr, unsigned long len, int prot, int flags, int fd, long pgoff)
{
- addr = sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
+ addr = ksys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
if (!IS_ERR((void *) addr))
force_successful_syscall_return();
return addr;
@@ -151,7 +151,7 @@ sys_mmap (unsigned long addr, unsigned long len, int prot, int flags, int fd, lo
if (offset_in_page(off) != 0)
return -EINVAL;
- addr = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ addr = ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
if (!IS_ERR((void *) addr))
force_successful_syscall_return();
return addr;
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
deleted file mode 100644
index dd84ee194579..000000000000
--- a/arch/m32r/Kconfig
+++ /dev/null
@@ -1,419 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config M32R
- bool
- default y
- select HAVE_IDE
- select HAVE_OPROFILE
- select INIT_ALL_POSSIBLE
- select HAVE_KERNEL_GZIP
- select HAVE_KERNEL_BZIP2
- select HAVE_KERNEL_LZMA
- select ARCH_WANT_IPC_PARSE_VERSION
- select HAVE_DEBUG_BUGVERBOSE
- select VIRT_TO_BUS
- select GENERIC_IRQ_PROBE
- select GENERIC_IRQ_SHOW
- select GENERIC_ATOMIC64
- select ARCH_HAS_DEVMEM_IS_ALLOWED
- select ARCH_USES_GETTIMEOFFSET
- select MODULES_USE_ELF_RELA
- select HAVE_DEBUG_STACKOVERFLOW
- select CPU_NO_EFFICIENT_FFS
- select DMA_DIRECT_OPS
- select ARCH_NO_COHERENT_DMA_MMAP if !MMU
-
-config SBUS
- bool
-
-config GENERIC_ISA_DMA
- bool
- default y
-
-config ZONE_DMA
- bool
- default y
-
-config NO_IOPORT_MAP
- def_bool y
-
-config NO_DMA
- def_bool n
-
-config HZ
- int
- default 100
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-
-menu "Processor type and features"
-
-choice
- prompt "Platform Type"
- default PLAT_MAPPI
-
-config PLAT_MAPPI
- bool "Mappi-I"
- help
- The Mappi-I is an FPGA board for SOC (System-On-a-Chip) prototyping.
- You can operate a Linux system on this board by using an M32R
- softmacro core, which is a fully-synthesizable functional model
- described in Verilog-HDL.
-
- The Mappi-I board was the first platform, which had been used
- to port and develop a Linux system for the M32R processor.
- Currently, the Mappi-II, an heir to the Mappi-I, is available.
-
-config PLAT_USRV
- bool "uServer"
- select PLAT_HAS_INT1ICU
-
-config PLAT_M32700UT
- bool "M32700UT"
- select PLAT_HAS_INT0ICU
- select PLAT_HAS_INT1ICU
- select PLAT_HAS_INT2ICU
- help
- The M3T-M32700UT is an evaluation board based on uT-Engine
- specification. This board has an M32700 (Chaos) evaluation chip.
- You can say Y for SMP, because the M32700 is a single chip
- multiprocessor.
-
-config PLAT_OPSPUT
- bool "OPSPUT"
- select PLAT_HAS_INT0ICU
- select PLAT_HAS_INT1ICU
- select PLAT_HAS_INT2ICU
- help
- The OPSPUT is an evaluation board based on uT-Engine
- specification. This board has a OPSP-REP chip.
-
-config PLAT_OAKS32R
- bool "OAKS32R"
- help
- The OAKS32R is a tiny, inexpensive evaluation board.
- Please note that if you say Y here and choose chip "M32102",
- say N for MMU and select a no-MMU version kernel, otherwise
- a kernel with MMU support will not work, because the M32102
- is a microcontroller for embedded systems and it has no MMU.
-
-config PLAT_MAPPI2
- bool "Mappi-II(M3A-ZA36/M3A-ZA52)"
-
-config PLAT_MAPPI3
- bool "Mappi-III(M3A-2170)"
-
-config PLAT_M32104UT
- bool "M32104UT"
- select PLAT_HAS_INT1ICU
- help
- The M3T-M32104UT is an reference board based on uT-Engine
- specification. This board has a M32104 chip.
-
-endchoice
-
-choice
- prompt "Processor family"
- default CHIP_M32700
-
-config CHIP_M32700
- bool "M32700 (Chaos)"
-
-config CHIP_M32102
- bool "M32102"
-
-config CHIP_M32104
- bool "M32104"
- depends on PLAT_M32104UT
-
-config CHIP_VDEC2
- bool "VDEC2"
-
-config CHIP_OPSP
- bool "OPSP"
-
-endchoice
-
-config MMU
- bool "Support for memory management hardware"
- depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
- default y
-
-config TLB_ENTRIES
- int "TLB Entries"
- depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
- default 32 if CHIP_M32700 || CHIP_OPSP
- default 16 if CHIP_VDEC2
-
-
-config ISA_M32R
- bool
- depends on CHIP_M32102 || CHIP_M32104
- default y
-
-config ISA_M32R2
- bool
- depends on CHIP_M32700 || CHIP_VDEC2 || CHIP_OPSP
- default y
-
-config ISA_DSP_LEVEL2
- bool
- depends on CHIP_M32700 || CHIP_OPSP
- default y
-
-config ISA_DUAL_ISSUE
- bool
- depends on CHIP_M32700 || CHIP_OPSP
- default y
-
-config PLAT_HAS_INT0ICU
- bool
- default n
-
-config PLAT_HAS_INT1ICU
- bool
- default n
-
-config PLAT_HAS_INT2ICU
- bool
- default n
-
-config BUS_CLOCK
- int "Bus Clock [Hz] (integer)"
- default "70000000" if PLAT_MAPPI
- default "25000000" if PLAT_USRV
- default "50000000" if PLAT_MAPPI3
- default "50000000" if PLAT_M32700UT
- default "50000000" if PLAT_OPSPUT
- default "54000000" if PLAT_M32104UT
- default "33333333" if PLAT_OAKS32R
- default "20000000" if PLAT_MAPPI2
-
-config TIMER_DIVIDE
- int "Timer divider (integer)"
- default "128"
-
-config CPU_BIG_ENDIAN
- bool
- default !CPU_LITTLE_ENDIAN
-
-config CPU_LITTLE_ENDIAN
- bool "Generate little endian code"
- default n
-
-config MEMORY_START
- hex "Physical memory start address (hex)"
- default "08000000" if PLAT_MAPPI || PLAT_MAPPI2 || PLAT_MAPPI3
- default "08000000" if PLAT_USRV
- default "08000000" if PLAT_M32700UT
- default "08000000" if PLAT_OPSPUT
- default "04000000" if PLAT_M32104UT
- default "01000000" if PLAT_OAKS32R
-
-config MEMORY_SIZE
- hex "Physical memory size (hex)"
- default "08000000" if PLAT_MAPPI3
- default "04000000" if PLAT_MAPPI || PLAT_MAPPI2
- default "02000000" if PLAT_USRV
- default "01000000" if PLAT_M32700UT
- default "01000000" if PLAT_OPSPUT
- default "01000000" if PLAT_M32104UT
- default "00800000" if PLAT_OAKS32R
-
-config ARCH_DISCONTIGMEM_ENABLE
- bool "Internal RAM Support"
- depends on CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104
- default y
-
-source "mm/Kconfig"
-
-config IRAM_START
- hex "Internal memory start address (hex)"
- default "00f00000" if !CHIP_M32104
- default "00700000" if CHIP_M32104
- depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104) && DISCONTIGMEM
-
-config IRAM_SIZE
- hex "Internal memory size (hex)"
- depends on (CHIP_M32700 || CHIP_M32102 || CHIP_VDEC2 || CHIP_OPSP || CHIP_M32104) && DISCONTIGMEM
- default "00080000" if CHIP_M32700
- default "00010000" if CHIP_M32102 || CHIP_OPSP || CHIP_M32104
- default "00008000" if CHIP_VDEC2
-
-#
-# Define implied options from the CPU selection here
-#
-
-config GENERIC_LOCKBREAK
- bool
- default y
- depends on SMP && PREEMPT
-
-config RWSEM_GENERIC_SPINLOCK
- bool
- depends on M32R
- default y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
- default n
-
-config ARCH_HAS_ILOG2_U32
- bool
- default n
-
-config ARCH_HAS_ILOG2_U64
- bool
- default n
-
-config GENERIC_HWEIGHT
- bool
- default y
-
-config GENERIC_CALIBRATE_DELAY
- bool
- default y
-
-config SCHED_OMIT_FRAME_POINTER
- bool
- default y
-
-source "kernel/Kconfig.preempt"
-
-config SMP
- bool "Symmetric multi-processing support"
- depends on MMU
- ---help---
- This enables support for systems with more than one CPU. If you have
- a system with only one CPU, say N. If you have a system with more
- than one CPU, say Y.
-
- If you say N here, the kernel will run on uni- and multiprocessor
- machines, but will use only one CPU of a multiprocessor machine. If
- you say Y here, the kernel will run on many, but not all,
- uniprocessor machines. On a uniprocessor machine, the kernel
- will run faster if you say N here.
-
- People using multiprocessor machines who say Y here should also say
- Y to "Enhanced Real Time Clock Support", below. The "Advanced Power
- Management" code will be disabled if you say Y here.
-
- See also the SMP-HOWTO available at
- <http://tldp.org/HOWTO/SMP-HOWTO.html>.
-
- If you don't know what to do here, say N.
-
-config CHIP_M32700_TS1
- bool "Workaround code for the M32700 TS1 chip's bug"
- depends on (CHIP_M32700 && SMP)
- default n
-
-config NR_CPUS
- int "Maximum number of CPUs (2-32)"
- range 2 32
- depends on SMP
- default "2"
- help
- This allows you to specify the maximum number of CPUs which this
- kernel will support. The maximum supported value is 32 and the
- minimum value which makes sense is 2.
-
- This is purely to save memory - each supported CPU adds
- approximately eight kilobytes to the kernel image.
-
-# Common NUMA Features
-config NUMA
- bool "Numa Memory Allocation Support"
- depends on SMP && BROKEN
- default n
-
-config NODES_SHIFT
- int
- default "1"
- depends on NEED_MULTIPLE_NODES
-
-endmenu
-
-
-menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
-
-config PCI
- bool "PCI support"
- depends on BROKEN
- default n
- help
- Find out whether you have a PCI motherboard. PCI is the name of a
- bus system, i.e. the way the CPU talks to the other stuff inside
- your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
- VESA. If you have PCI, say Y, otherwise N.
-
-choice
- prompt "PCI access mode"
- depends on PCI
- default PCI_GOANY
-
-config PCI_GOBIOS
- bool "BIOS"
- ---help---
- On PCI systems, the BIOS can be used to detect the PCI devices and
- determine their configuration. However, some old PCI motherboards
- have BIOS bugs and may crash if this is done. Also, some embedded
- PCI-based systems don't have any BIOS at all. Linux can also try to
- detect the PCI hardware directly without using the BIOS.
-
- With this option, you can specify how Linux should detect the PCI
- devices. If you choose "BIOS", the BIOS will be used, if you choose
- "Direct", the BIOS won't be used, and if you choose "Any", the
- kernel will try the direct access method and falls back to the BIOS
- if that doesn't work. If unsure, go with the default, which is
- "Any".
-
-config PCI_GODIRECT
- bool "Direct"
-
-config PCI_GOANY
- bool "Any"
-
-endchoice
-
-config PCI_BIOS
- bool
- depends on PCI && (PCI_GOBIOS || PCI_GOANY)
- default y
-
-config PCI_DIRECT
- bool
- depends on PCI && (PCI_GODIRECT || PCI_GOANY)
- default y
-
-source "drivers/pci/Kconfig"
-
-config ISA
- bool
-
-source "drivers/pcmcia/Kconfig"
-
-endmenu
-
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/m32r/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug
deleted file mode 100644
index ffca1e194f91..000000000000
--- a/arch/m32r/Kconfig.debug
+++ /dev/null
@@ -1,22 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config DEBUG_PAGEALLOC
- bool "Debug page memory allocations"
- depends on DEBUG_KERNEL && BROKEN
- help
- Unmap pages from the kernel linear mapping after free_pages().
- This results in a large slowdown, but helps to find certain types
- of memory corruptions.
-
-config FRAME_POINTER
- bool "Compile the kernel with frame pointers"
- help
- If you say Y here the resulting kernel image will be slightly larger
- and slower, but it will give very useful debugging information.
- If you don't debug the kernel, you can say N, but we may not be able
- to solve problems without frame pointers.
-
-endmenu
diff --git a/arch/m32r/Makefile b/arch/m32r/Makefile
deleted file mode 100644
index d73b58c847a6..000000000000
--- a/arch/m32r/Makefile
+++ /dev/null
@@ -1,63 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# m32r/Makefile
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies.
-#
-
-KBUILD_DEFCONFIG := m32700ut.smp_defconfig
-
-LDFLAGS :=
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-LDFLAGS_vmlinux :=
-
-KBUILD_CFLAGS += -pipe -fno-schedule-insns
-KBUILD_CFLAGS_KERNEL += -mmodel=medium
-KBUILD_CFLAGS_MODULE += -mmodel=large
-
-ifdef CONFIG_CHIP_VDEC2
-cflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -Wa,-bitinst
-aflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -O2 -Wa,-bitinst -Wa,-no-parallel
-else
-cflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -m32r2
-aflags-$(CONFIG_ISA_M32R2) += -DNO_FPU -m32r2 -O2
-endif
-
-cflags-$(CONFIG_ISA_M32R) += -DNO_FPU
-aflags-$(CONFIG_ISA_M32R) += -DNO_FPU -O2 -Wa,-no-bitinst
-
-KBUILD_CFLAGS += $(cflags-y)
-KBUILD_AFLAGS += $(aflags-y)
-
-CHECKFLAGS += -D__m32r__ -D__BIG_ENDIAN__=1
-
-head-y := arch/m32r/kernel/head.o
-
-LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
-
-libs-y += arch/m32r/lib/ $(LIBGCC)
-core-y += arch/m32r/kernel/ \
- arch/m32r/mm/ \
- arch/m32r/boot/ \
- arch/m32r/platforms/
-
-drivers-$(CONFIG_OPROFILE) += arch/m32r/oprofile/
-
-boot := arch/m32r/boot
-
-PHONY += zImage
-
-all: zImage
-
-zImage: vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-compressed: zImage
-
-archclean:
- $(Q)$(MAKE) $(clean)=$(boot)
-
-define archhelp
- echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
-endef
diff --git a/arch/m32r/boot/Makefile b/arch/m32r/boot/Makefile
deleted file mode 100644
index af2cef475d98..000000000000
--- a/arch/m32r/boot/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# arch/m32r/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-
-targets := zImage
-subdir- := compressed
-
-obj-y := setup.o
-
-$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
- $(call if_changed,objcopy)
- @echo 'Kernel: $@ is ready'
-
-$(obj)/compressed/vmlinux: FORCE
- $(Q)$(MAKE) $(build)=$(obj)/compressed $@
-
diff --git a/arch/m32r/boot/compressed/Makefile b/arch/m32r/boot/compressed/Makefile
deleted file mode 100644
index abd3c75ebd32..000000000000
--- a/arch/m32r/boot/compressed/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# linux/arch/m32r/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux
-#
-
-targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 \
- vmlinux.bin.lzma head.o misc.o piggy.o vmlinux.lds
-
-OBJECTS = $(obj)/head.o $(obj)/misc.o
-
-#
-# IMAGE_OFFSET is the load offset of the compression loader
-#
-#IMAGE_OFFSET := $(shell printf "0x%08x" $$[$(CONFIG_MEMORY_START)+0x2000])
-#IMAGE_OFFSET := $(shell printf "0x%08x" $$[$(CONFIG_MEMORY_START)+0x00400000])
-
-LDFLAGS_vmlinux := -T
-
-$(obj)/vmlinux: $(obj)/vmlinux.lds $(OBJECTS) $(obj)/piggy.o FORCE
- $(call if_changed,ld)
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
- $(call if_changed,bzip2)
-
-$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzma)
-
-CFLAGS_misc.o += -fpic
-
-ifdef CONFIG_MMU
-LDFLAGS_piggy.o := -r --format binary --oformat elf32-m32r-linux -T
-else
-LDFLAGS_piggy.o := -r --format binary --oformat elf32-m32r -T
-endif
-
-OBJCOPYFLAGS += -R .empty_zero_page
-
-suffix-$(CONFIG_KERNEL_GZIP) = gz
-suffix-$(CONFIG_KERNEL_BZIP2) = bz2
-suffix-$(CONFIG_KERNEL_LZMA) = lzma
-
-$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE
- $(call if_changed,ld)
diff --git a/arch/m32r/boot/compressed/boot.h b/arch/m32r/boot/compressed/boot.h
deleted file mode 100644
index 7fce713e8aac..000000000000
--- a/arch/m32r/boot/compressed/boot.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * 1. load vmlinuz
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinuz |
- * +-----------------------+
- * 2. decompressed
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinuz |
- * +-----------------------+
- * | |
- * BOOT_RELOC_ADDR +-----------------------+
- * | |
- * KERNEL_DECOMPRESS_ADDR +-----------------------+
- * | vmlinux |
- * +-----------------------+
- *
- * 3. relocate copy & jump code
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinuz |
- * +-----------------------+
- * | |
- * BOOT_RELOC_ADDR +-----------------------+
- * | boot(copy&jump) |
- * KERNEL_DECOMPRESS_ADDR +-----------------------+
- * | vmlinux |
- * +-----------------------+
- *
- * 4. relocate decompressed kernel
- *
- * CONFIG_MEMORY_START +-----------------------+
- * | vmlinux |
- * +-----------------------+
- * | |
- * BOOT_RELOC_ADDR +-----------------------+
- * | boot(copy&jump) |
- * KERNEL_DECOMPRESS_ADDR +-----------------------+
- * | |
- * +-----------------------+
- *
- */
-#ifdef __ASSEMBLY__
-#define __val(x) x
-#else
-#define __val(x) (x)
-#endif
-
-#define DECOMPRESS_OFFSET_BASE __val(0x00900000)
-#define BOOT_RELOC_SIZE __val(0x00001000)
-
-#define KERNEL_EXEC_ADDR __val(CONFIG_MEMORY_START)
-#define KERNEL_DECOMPRESS_ADDR __val(CONFIG_MEMORY_START + \
- DECOMPRESS_OFFSET_BASE + BOOT_RELOC_SIZE)
-#define KERNEL_ENTRY __val(CONFIG_MEMORY_START + 0x1000)
-
-#define BOOT_EXEC_ADDR __val(CONFIG_MEMORY_START)
-#define BOOT_RELOC_ADDR __val(CONFIG_MEMORY_START + DECOMPRESS_OFFSET_BASE)
diff --git a/arch/m32r/boot/compressed/head.S b/arch/m32r/boot/compressed/head.S
deleted file mode 100644
index 39b693640375..000000000000
--- a/arch/m32r/boot/compressed/head.S
+++ /dev/null
@@ -1,177 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/boot/compressed/head.S
- *
- * Copyright (c) 2001-2003 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Takeo Takahashi
- * Copyright (c) 2004 Hirokazu Takata
- */
-
- .text
-#include <linux/linkage.h>
-#include <asm/addrspace.h>
-#include <asm/page.h>
-#include <asm/assembler.h>
-
- /*
- * This code can be loaded anywhere, as long as output will not
- * overlap it.
- *
- * NOTE: This head.S should *NOT* be compiled with -fpic.
- *
- */
-
- .global startup
- .global __bss_start, _ebss, end, zimage_data, zimage_len
- __ALIGN
-startup:
- ldi r0, #0x0000 /* SPI, disable EI */
- mvtc r0, psw
-
- ldi r12, #-8
- bl 1f
- .fillinsn
-1:
- seth r1, #high(CONFIG_MEMORY_START + 0x00400000) /* Start address */
- add r12, r14 /* Real address */
- sub r12, r1 /* difference */
-
- .global got_len
- seth r3, #high(_GLOBAL_OFFSET_TABLE_+8)
- or3 r3, r3, #low(_GLOBAL_OFFSET_TABLE_+12)
- add r3, r14
-
- /* Update the contents of global offset table */
- ldi r1, #low(got_len)
- srli r1, #2
- beqz r1, 2f
- .fillinsn
-1:
- ld r2, @r3
- add r2, r12
- st r2, @r3
- addi r3, #4
- addi r1, #-1
- bnez r1, 1b
- .fillinsn
-2:
- /* XXX: resolve plt */
-
-/*
- * Clear BSS first so that there are no surprises...
- */
-#ifdef CONFIG_ISA_DUAL_ISSUE
- seth r2, #high(__bss_start)
- or3 r2, r2, #low(__bss_start)
- add r2, r12
- seth r3, #high(_ebss)
- or3 r3, r3, #low(_ebss)
- add r3, r12
- sub r3, r2
-
- ; R4 = BSS size in longwords (rounded down)
- mv r4, r3 || ldi r1, #0
- srli r4, #4 || addi r2, #-4
- beqz r4, .Lendloop1
-.Lloop1:
-#ifndef CONFIG_CHIP_M32310
- ; Touch memory for the no-write-allocating cache.
- ld r0, @(4,r2)
-#endif
- st r1, @+r2 || addi r4, #-1
- st r1, @+r2
- st r1, @+r2
- st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
- bnc .Lloop1
-.Lendloop1:
- and3 r4, r3, #15
- addi r2, #4
- beqz r4, .Lendloop2
-.Lloop2:
- stb r1, @r2 || addi r4, #-1
- addi r2, #1
- bnez r4, .Lloop2
-.Lendloop2:
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
- seth r2, #high(__bss_start)
- or3 r2, r2, #low(__bss_start)
- add r2, r12
- seth r3, #high(_ebss)
- or3 r3, r3, #low(_ebss)
- add r3, r12
- sub r3, r2
- mv r4, r3
- srli r4, #2 ; R4 = BSS size in longwords (rounded down)
- ldi r1, #0 ; clear R1 for longwords store
- addi r2, #-4 ; account for pre-inc store
- beqz r4, .Lendloop1 ; any more to go?
-.Lloop1:
- st r1, @+r2 ; yep, zero out another longword
- addi r4, #-1 ; decrement count
- bnez r4, .Lloop1 ; go do some more
-.Lendloop1:
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
- seth r1, #high(end)
- or3 r1, r1, #low(end)
- add r1, r12
- mv sp, r1
-
-/*
- * decompress the kernel
- */
- mv r0, sp
- srli r0, 31 /* MMU is ON or OFF */
- seth r1, #high(zimage_data)
- or3 r1, r1, #low(zimage_data)
- add r1, r12
- seth r2, #high(zimage_len)
- or3 r2, r2, #low(zimage_len)
- mv r3, sp
-
- bl decompress_kernel
-
-#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_VDEC2)
- /* Cache flush */
- ldi r0, -1
- ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache
- stb r1, @r0
-#elif defined(CONFIG_CHIP_M32102)
- /* Cache flush */
- ldi r0, -2
- ldi r1, 0x0100 ; invalidate
- stb r1, @r0
-#elif defined(CONFIG_CHIP_M32104)
- /* Cache flush */
- ldi r0, -2
- ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
- sth r1, @r0
-#else
-#error "put your cache flush function, please"
-#endif
-
- mv r0, sp
- srli r0, 31 /* MMU is ON or OFF */
- slli r0, 31
- or3 r0, r0, #0x2000
- seth r1, #high(CONFIG_MEMORY_START)
- or r0, r1
- jmp r0
-
- .balign 512
-fake_headers_as_bzImage:
- .short 0
- .ascii "HdrS"
- .short 0x0202
- .short 0
- .short 0
- .byte 0x00, 0x10
- .short 0
- .byte 0
- .byte 1
- .byte 0x00, 0x80
- .long 0
- .long 0
-
diff --git a/arch/m32r/boot/compressed/install.sh b/arch/m32r/boot/compressed/install.sh
deleted file mode 100644
index 16e5a0a13437..000000000000
--- a/arch/m32r/boot/compressed/install.sh
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/bin/sh
-#
-# arch/sh/boot/install.sh
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995 by Linus Torvalds
-#
-# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
-# Adapted from code in arch/i386/boot/install.sh by Russell King
-# Adapted from code in arch/arm/boot/install.sh by Stuart Menefy
-# Adapted from code in arch/sh/boot/install.sh by Takeo Takahashi
-#
-# "make install" script for sh architecture
-#
-# Arguments:
-# $1 - kernel version
-# $2 - kernel image file
-# $3 - kernel map file
-# $4 - default install path (blank if root directory)
-#
-
-# User may have a custom install script
-
-if [ -x /sbin/${INSTALLKERNEL} ]; then
- exec /sbin/${INSTALLKERNEL} "$@"
-fi
-
-if [ "$2" = "zImage" ]; then
-# Compressed install
- echo "Installing compressed kernel"
- if [ -f $4/vmlinuz-$1 ]; then
- mv $4/vmlinuz-$1 $4/vmlinuz.old
- fi
-
- if [ -f $4/System.map-$1 ]; then
- mv $4/System.map-$1 $4/System.old
- fi
-
- cat $2 > $4/vmlinuz-$1
- cp $3 $4/System.map-$1
-else
-# Normal install
- echo "Installing normal kernel"
- if [ -f $4/vmlinux-$1 ]; then
- mv $4/vmlinux-$1 $4/vmlinux.old
- fi
-
- if [ -f $4/System.map ]; then
- mv $4/System.map $4/System.old
- fi
-
- cat $2 > $4/vmlinux-$1
- cp $3 $4/System.map
-fi
diff --git a/arch/m32r/boot/compressed/m32r_sio.c b/arch/m32r/boot/compressed/m32r_sio.c
deleted file mode 100644
index 9d34bd063c31..000000000000
--- a/arch/m32r/boot/compressed/m32r_sio.c
+++ /dev/null
@@ -1,77 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/m32r/boot/compressed/m32r_sio.c
- *
- * 2003-02-12: Takeo Takahashi
- * 2006-11-30: OPSPUT support by Kazuhiro Inaoka
- *
- */
-
-#include <asm/processor.h>
-
-static void m32r_putc(char c);
-
-static int puts(const char *s)
-{
- char c;
- while ((c = *s++))
- m32r_putc(c);
- return 0;
-}
-
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT)
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define USE_FPGA_MAP 0
-
-#if USE_FPGA_MAP
-/*
- * fpga configuration program uses MMU, and define map as same as
- * M32104 uT-Engine board.
- */
-#define BOOT_SIO0STS (volatile unsigned short *)(0x02c00000 + 0x20006)
-#define BOOT_SIO0TXB (volatile unsigned short *)(0x02c00000 + 0x2000c)
-#else
-#undef PLD_BASE
-#if defined(CONFIG_PLAT_OPSPUT)
-#define PLD_BASE 0x1cc00000
-#else
-#define PLD_BASE 0xa4c00000
-#endif
-#define BOOT_SIO0STS PLD_ESIO0STS
-#define BOOT_SIO0TXB PLD_ESIO0TXB
-#endif
-
-static void m32r_putc(char c)
-{
- while ((*BOOT_SIO0STS & 0x3) != 0x3)
- cpu_relax();
- if (c == '\n') {
- *BOOT_SIO0TXB = '\r';
- while ((*BOOT_SIO0STS & 0x3) != 0x3)
- cpu_relax();
- }
- *BOOT_SIO0TXB = c;
-}
-#else /* !(CONFIG_PLAT_M32700UT) */
-#if defined(CONFIG_PLAT_MAPPI2)
-#define SIO0STS (volatile unsigned short *)(0xa0efd000 + 14)
-#define SIO0TXB (volatile unsigned short *)(0xa0efd000 + 30)
-#else
-#define SIO0STS (volatile unsigned short *)(0x00efd000 + 14)
-#define SIO0TXB (volatile unsigned short *)(0x00efd000 + 30)
-#endif
-
-static void m32r_putc(char c)
-{
- while ((*SIO0STS & 0x1) == 0)
- cpu_relax();
- if (c == '\n') {
- *SIO0TXB = '\r';
- while ((*SIO0STS & 0x1) == 0)
- cpu_relax();
- }
- *SIO0TXB = c;
-}
-#endif
diff --git a/arch/m32r/boot/compressed/misc.c b/arch/m32r/boot/compressed/misc.c
deleted file mode 100644
index 43e367055669..000000000000
--- a/arch/m32r/boot/compressed/misc.c
+++ /dev/null
@@ -1,93 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/m32r/boot/compressed/misc.c
- *
- * This is a collection of several routines from gzip-1.0.3
- * adapted for Linux.
- *
- * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
- *
- * Adapted for SH by Stuart Menefy, Aug 1999
- *
- * 2003-02-12: Support M32R by Takeo Takahashi
- */
-
-/*
- * gzip declarations
- */
-#define STATIC static
-
-#undef memset
-#undef memcpy
-#define memzero(s, n) memset ((s), 0, (n))
-
-static void error(char *m);
-
-#include "m32r_sio.c"
-
-static unsigned long free_mem_ptr;
-static unsigned long free_mem_end_ptr;
-
-#ifdef CONFIG_KERNEL_BZIP2
-void *memset(void *s, int c, size_t n)
-{
- char *ss = s;
-
- while (n--)
- *ss++ = c;
- return s;
-}
-#endif
-
-#ifdef CONFIG_KERNEL_GZIP
-void *memcpy(void *dest, const void *src, size_t n)
-{
- char *d = dest;
- const char *s = src;
- while (n--)
- *d++ = *s++;
-
- return dest;
-}
-
-#define BOOT_HEAP_SIZE 0x10000
-#include "../../../../lib/decompress_inflate.c"
-#endif
-
-#ifdef CONFIG_KERNEL_BZIP2
-#define BOOT_HEAP_SIZE 0x400000
-#include "../../../../lib/decompress_bunzip2.c"
-#endif
-
-#ifdef CONFIG_KERNEL_LZMA
-#define BOOT_HEAP_SIZE 0x10000
-#include "../../../../lib/decompress_unlzma.c"
-#endif
-
-static void error(char *x)
-{
- puts("\n\n");
- puts(x);
- puts("\n\n -- System halted");
-
- while(1); /* Halt */
-}
-
-void
-decompress_kernel(int mmu_on, unsigned char *zimage_data,
- unsigned int zimage_len, unsigned long heap)
-{
- unsigned char *input_data = zimage_data;
- int input_len = zimage_len;
- unsigned char *output_data;
-
- output_data = (unsigned char *)CONFIG_MEMORY_START + 0x2000
- + (mmu_on ? 0x80000000 : 0);
- free_mem_ptr = heap;
- free_mem_end_ptr = free_mem_ptr + BOOT_HEAP_SIZE;
-
- puts("\nDecompressing Linux... ");
- __decompress(input_data, input_len, NULL, NULL, output_data, 0,
- NULL, error);
- puts("done.\nBooting the kernel.\n");
-}
diff --git a/arch/m32r/boot/compressed/vmlinux.lds.S b/arch/m32r/boot/compressed/vmlinux.lds.S
deleted file mode 100644
index c393eb559c4c..000000000000
--- a/arch/m32r/boot/compressed/vmlinux.lds.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-OUTPUT_ARCH(m32r)
-ENTRY(startup)
-SECTIONS
-{
- . = CONFIG_MEMORY_START + 0x00400000;
-
- _text = .;
- .text : { *(.text) } = 0
- .rodata : { *(.rodata) *(.rodata.*) }
- _etext = .;
-
- . = ALIGN(32 / 8);
- .data : { *(.data) }
- . = ALIGN(32 / 8);
- _got = .;
- .got : { *(.got) _egot = .; *(.got.*) }
- _edata = .;
-
- . = ALIGN(32 / 8);
- __bss_start = .;
- .bss : { *(.bss) *(.sbss) }
- . = ALIGN(32 / 8);
- _ebss = .;
- . = ALIGN(4096);
- . += 4096;
- end = . ;
-
- got_len = (_egot - _got);
-}
diff --git a/arch/m32r/boot/compressed/vmlinux.scr b/arch/m32r/boot/compressed/vmlinux.scr
deleted file mode 100644
index 924c7992c55b..000000000000
--- a/arch/m32r/boot/compressed/vmlinux.scr
+++ /dev/null
@@ -1,9 +0,0 @@
-SECTIONS
-{
- .data : {
- zimage_data = .;
- *(.data)
- zimage_data_end = .;
- }
- zimage_len = zimage_data_end - zimage_data;
-}
diff --git a/arch/m32r/boot/setup.S b/arch/m32r/boot/setup.S
deleted file mode 100644
index 5909a825e2ed..000000000000
--- a/arch/m32r/boot/setup.S
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/boot/setup.S -- A setup code.
- *
- * Copyright (C) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Hayato Fujiwara
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
-#include <asm/assembler.h>
-#include <asm/mmu_context.h>
-#include <asm/m32r.h>
-
-/*
- * References to members of the boot_cpu_data structure.
- */
-
-#define CPU_PARAMS boot_cpu_data
-#define M32R_MCICAR 0xfffffff0
-#define M32R_MCDCAR 0xfffffff4
-#define M32R_MCCR 0xfffffffc
-#define M32R_BSCR0 0xffffffd2
-
-;BSEL
-#define BSEL0CR0 0x00ef5000
-#define BSEL0CR1 0x00ef5004
-#define BSEL1CR0 0x00ef5100
-#define BSEL1CR1 0x00ef5104
-#define BSEL0CR0_VAL 0x00000000
-#define BSEL0CR1_VAL 0x01200100
-#define BSEL1CR0_VAL 0x01018000
-#define BSEL1CR1_VAL 0x00200001
-
-;SDRAMC
-#define SDRAMC_SDRF0 0x00ef6000
-#define SDRAMC_SDRF1 0x00ef6004
-#define SDRAMC_SDIR0 0x00ef6008
-#define SDRAMC_SDIR1 0x00ef600c
-#define SDRAMC_SD0ADR 0x00ef6020
-#define SDRAMC_SD0ER 0x00ef6024
-#define SDRAMC_SD0TR 0x00ef6028
-#define SDRAMC_SD0MOD 0x00ef602c
-#define SDRAMC_SD1ADR 0x00ef6040
-#define SDRAMC_SD1ER 0x00ef6044
-#define SDRAMC_SD1TR 0x00ef6048
-#define SDRAMC_SD1MOD 0x00ef604c
-#define SDRAM0 0x18000000
-#define SDRAM1 0x1c000000
-
-/*------------------------------------------------------------------------
- * start up
- */
-
-/*------------------------------------------------------------------------
- * Kernel entry
- */
- .section .boot, "ax"
-ENTRY(boot)
-
-/* Set cache mode */
-#if defined(CONFIG_CHIP_XNUX2)
- ldi r0, #-2 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x0101 ; cache on (with invalidation)
-; ldi r1, #0x00 ; cache off
- sth r1, @r0
-#elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \
- || defined(CONFIG_CHIP_OPSP)
- ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x73 ; cache on (with invalidation)
-; ldi r1, #0x00 ; cache off
- st r1, @r0
-#elif defined(CONFIG_CHIP_M32102)
- ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x101 ; cache on (with invalidation)
-; ldi r1, #0x00 ; cache off
- st r1, @r0
-#elif defined(CONFIG_CHIP_M32104)
- ldi r0, #-96 ; DNCR0
- seth r1, #0x0060 ; from 0x00600000
- or3 r1, r1, #0x0005 ; size 2MB
- st r1, @r0
- seth r1, #0x0100 ; from 0x01000000
- or3 r1, r1, #0x0003 ; size 16MB
- st r1, @+r0
- seth r1, #0x0200 ; from 0x02000000
- or3 r1, r1, #0x0002 ; size 32MB
- st r1, @+r0
- ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
- ldi r1, #0x703 ; cache on (with invalidation)
- st r1, @r0
-#else
-#error unknown chip configuration
-#endif
-
-#ifdef CONFIG_SMP
- ;; if not BSP (CPU#0) goto AP_loop
- seth r5, #shigh(M32R_CPUID_PORTL)
- ld r5, @(low(M32R_CPUID_PORTL), r5)
- bnez r5, AP_loop
-#if !defined(CONFIG_PLAT_USRV)
- ;; boot AP
- ld24 r5, #0xeff2f8 ; IPICR7
- ldi r6, #0x2 ; IPI to CPU1
- st r6, @r5
-#endif
-#endif
-
-/*
- * Now, Jump to stext
- * if with MMU, TLB on.
- * if with no MMU, only jump.
- */
- .global eit_vector
-mmu_on:
- LDIMM (r13, stext)
-#ifdef CONFIG_MMU
- bl init_tlb
- LDIMM (r2, eit_vector) ; set EVB(cr5)
- mvtc r2, cr5
- seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
- or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
- ldi r1, #0x01
- st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
- ld r0, @(MATM_offset,r0) ; Check
-#else
-#if defined(CONFIG_CHIP_M32700)
- seth r0,#high(M32R_MCDCAR)
- or3 r0,r0,#low(M32R_MCDCAR)
- ld24 r1,#0x8080
- st r1,@r0
-#elif defined(CONFIG_CHIP_M32104)
- LDIMM (r2, eit_vector) ; set EVB(cr5)
- mvtc r2, cr5
-#endif
-#endif /* CONFIG_MMU */
- jmp r13
- nop
- nop
-
-#ifdef CONFIG_SMP
-/*
- * AP wait loop
- */
-ENTRY(AP_loop)
- ;; disable interrupt
- clrpsw #0x40
- ;; reset EVB
- LDIMM (r4, _AP_RE)
- seth r5, #high(__PAGE_OFFSET)
- or3 r5, r5, #low(__PAGE_OFFSET)
- not r5, r5
- and r4, r5
- mvtc r4, cr5
- ;; disable maskable interrupt
- seth r4, #high(M32R_ICU_IMASK_PORTL)
- or3 r4, r4, #low(M32R_ICU_IMASK_PORTL)
- ldi r5, #0
- st r5, @r4
- ld r5, @r4
- ;; enable only IPI
- setpsw #0x40
- ;; LOOOOOOOOOOOOOOP!!!
- .fillinsn
-2:
- nop
- nop
- bra 2b
- nop
- nop
-
-#ifdef CONFIG_CHIP_M32700_TS1
- .global dcache_dummy
- .balign 16, 0
-dcache_dummy:
- .byte 16
-#endif /* CONFIG_CHIP_M32700_TS1 */
-#endif /* CONFIG_SMP */
-
- .end
-
diff --git a/arch/m32r/configs/m32104ut_defconfig b/arch/m32r/configs/m32104ut_defconfig
deleted file mode 100644
index 4aa42acbd512..000000000000
--- a/arch/m32r/configs/m32104ut_defconfig
+++ /dev/null
@@ -1,144 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_M32104UT=y
-CONFIG_CHIP_M32104=y
-CONFIG_MEMORY_START=0x04000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00700000
-CONFIG_IRAM_SIZE=0x00010000
-CONFIG_PREEMPT=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_PARPORT=m
-CONFIG_PARPORT_1284=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_WCACHE=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_RAID1=y
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_NE2000=m
-CONFIG_SERIAL_8250=m
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_SMSC47M1=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83L785TS=m
-CONFIG_SENSORS_W83627HF=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_CONFIGFS_FS=m
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_932=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_LIBCRC32C=m
diff --git a/arch/m32r/configs/m32700ut.smp_defconfig b/arch/m32r/configs/m32700ut.smp_defconfig
deleted file mode 100644
index 41a0495b65df..000000000000
--- a/arch/m32r/configs/m32700ut.smp_defconfig
+++ /dev/null
@@ -1,85 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_M32700UT=y
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_SMP=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_BE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_SERIAL_M32R_PLDSIO=y
-CONFIG_HW_RANDOM=y
-CONFIG_DS1302=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_S1D13XXX=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_REISERFS_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/m32700ut.up_defconfig b/arch/m32r/configs/m32700ut.up_defconfig
deleted file mode 100644
index 20078a866f45..000000000000
--- a/arch/m32r/configs/m32700ut.up_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_M32700UT=y
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_BE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_ATA_OVER_ETH=m
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_SERIAL_M32R_PLDSIO=y
-CONFIG_HW_RANDOM=y
-CONFIG_DS1302=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_S1D13XXX=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_REISERFS_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi.nommu_defconfig b/arch/m32r/configs/mappi.nommu_defconfig
deleted file mode 100644
index 4bf3820e054a..000000000000
--- a/arch/m32r/configs/mappi.nommu_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_MMU is not set
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x00000000
-CONFIG_MEMORY_SIZE=0x00E00000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_M32R_PCC=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi.smp_defconfig b/arch/m32r/configs/mappi.smp_defconfig
deleted file mode 100644
index f9ed7bdbf4de..000000000000
--- a/arch/m32r/configs/mappi.smp_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_BUS_CLOCK=10000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x04000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_SMP=y
-CONFIG_CHIP_M32700_TS1=y
-CONFIG_PCCARD=y
-CONFIG_M32R_PCC=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=m
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi.up_defconfig b/arch/m32r/configs/mappi.up_defconfig
deleted file mode 100644
index 289ae7421e12..000000000000
--- a/arch/m32r/configs/mappi.up_defconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_BUS_CLOCK=10000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x04000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_M32R_PCC=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=m
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi2.opsp_defconfig b/arch/m32r/configs/mappi2.opsp_defconfig
deleted file mode 100644
index 2852f6e7e246..000000000000
--- a/arch/m32r/configs/mappi2.opsp_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_MAPPI2=y
-CONFIG_CHIP_OPSP=y
-CONFIG_TLB_ENTRIES=16
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00008000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi2.vdec2_defconfig b/arch/m32r/configs/mappi2.vdec2_defconfig
deleted file mode 100644
index 8da4dbad8510..000000000000
--- a/arch/m32r/configs/mappi2.vdec2_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_MAPPI2=y
-CONFIG_CHIP_VDEC2=y
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00008000
-CONFIG_PREEMPT=y
-CONFIG_PCCARD=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/mappi3.smp_defconfig b/arch/m32r/configs/mappi3.smp_defconfig
deleted file mode 100644
index 5605b23e2faf..000000000000
--- a/arch/m32r/configs/mappi3.smp_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_MAPPI3=y
-CONFIG_BUS_CLOCK=10000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x08000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00080000
-CONFIG_PREEMPT=y
-CONFIG_SMP=y
-CONFIG_PCCARD=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/oaks32r_defconfig b/arch/m32r/configs/oaks32r_defconfig
deleted file mode 100644
index 5ccab127f6ad..000000000000
--- a/arch/m32r/configs/oaks32r_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_OAKS32R=y
-CONFIG_CHIP_M32102=y
-CONFIG_MEMORY_START=0x01000000
-CONFIG_MEMORY_SIZE=0x00800000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00010000
-CONFIG_PREEMPT=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_NETDEVICES=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_EXT2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
diff --git a/arch/m32r/configs/opsput_defconfig b/arch/m32r/configs/opsput_defconfig
deleted file mode 100644
index 3ce1d08355e5..000000000000
--- a/arch/m32r/configs/opsput_defconfig
+++ /dev/null
@@ -1,63 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PLAT_OPSPUT=y
-CONFIG_CHIP_OPSP=y
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x01000000
-CONFIG_IRAM_START=0x00f00000
-CONFIG_IRAM_SIZE=0x00010000
-CONFIG_PCCARD=y
-CONFIG_M32R_CFC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_M32R_SIO_CONSOLE=y
-CONFIG_SERIAL_M32R_PLDSIO=y
-CONFIG_HW_RANDOM=y
-CONFIG_DS1302=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
diff --git a/arch/m32r/configs/usrv_defconfig b/arch/m32r/configs/usrv_defconfig
deleted file mode 100644
index cb8c051c3d46..000000000000
--- a/arch/m32r/configs/usrv_defconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_PLAT_USRV=y
-CONFIG_BUS_CLOCK=50000000
-CONFIG_MEMORY_START=0x08000000
-CONFIG_MEMORY_SIZE=0x02000000
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SMP=y
-CONFIG_PCCARD=y
-CONFIG_M32R_CFC=y
-CONFIG_M32R_CFC_NUM=2
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_INET_AH=y
-CONFIG_INET_ESP=y
-CONFIG_INET_IPCOMP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_BE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_RAM=y
-CONFIG_MTD_ROM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECS=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_PCNET=y
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_M32R_SIO is not set
-# CONFIG_HWMON is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_FRAME_POINTER=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_MICHAEL_MIC=y
-CONFIG_CRYPTO_AES=y
-CONFIG_CRYPTO_ARC4=y
diff --git a/arch/m32r/include/asm/Kbuild b/arch/m32r/include/asm/Kbuild
deleted file mode 100644
index 985ef1d9f556..000000000000
--- a/arch/m32r/include/asm/Kbuild
+++ /dev/null
@@ -1,13 +0,0 @@
-generic-y += current.h
-generic-y += dma-mapping.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += irq_work.h
-generic-y += kprobes.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += module.h
-generic-y += preempt.h
-generic-y += sections.h
-generic-y += trace_clock.h
-generic-y += word-at-a-time.h
diff --git a/arch/m32r/include/asm/addrspace.h b/arch/m32r/include/asm/addrspace.h
deleted file mode 100644
index 81782c122da4..000000000000
--- a/arch/m32r/include/asm/addrspace.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 by Hiroyuki Kondo
- *
- * Defitions for the address spaces of the M32R CPUs.
- */
-#ifndef __ASM_M32R_ADDRSPACE_H
-#define __ASM_M32R_ADDRSPACE_H
-
-/*
- * Memory segments (32bit kernel mode addresses)
- */
-#define KUSEG 0x00000000
-#define KSEG0 0x80000000
-#define KSEG1 0xa0000000
-#define KSEG2 0xc0000000
-#define KSEG3 0xe0000000
-
-#define K0BASE KSEG0
-
-/*
- * Returns the kernel segment base of a given address
- */
-#ifndef __ASSEMBLY__
-#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000)
-#else
-#define KSEGX(a) ((a) & 0xe0000000)
-#endif
-
-/*
- * Returns the physical address of a KSEG0/KSEG1 address
- */
-#ifndef __ASSEMBLY__
-#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
-#else
-#define PHYSADDR(a) ((a) & 0x1fffffff)
-#endif
-
-/*
- * Map an address to a certain kernel segment
- */
-#ifndef __ASSEMBLY__
-#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0))
-#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1))
-#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2))
-#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3))
-#else
-#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0)
-#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1)
-#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2)
-#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3)
-#endif
-
-#endif /* __ASM_M32R_ADDRSPACE_H */
diff --git a/arch/m32r/include/asm/asm-offsets.h b/arch/m32r/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/m32r/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/m32r/include/asm/assembler.h b/arch/m32r/include/asm/assembler.h
deleted file mode 100644
index ed90d894f285..000000000000
--- a/arch/m32r/include/asm/assembler.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_ASSEMBLER_H
-#define _ASM_M32R_ASSEMBLER_H
-
-/*
- * linux/asm-m32r/assembler.h
- *
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- *
- * This file contains M32R architecture specific macro definitions.
- */
-
-#include <linux/stringify.h>
-
-#undef __STR
-
-#ifdef __ASSEMBLY__
-#define __STR(x) x
-#else
-#define __STR(x) __stringify(x)
-#endif
-
-#ifdef CONFIG_SMP
-#define M32R_LOCK __STR(lock)
-#define M32R_UNLOCK __STR(unlock)
-#else
-#define M32R_LOCK __STR(ld)
-#define M32R_UNLOCK __STR(st)
-#endif
-
-#ifdef __ASSEMBLY__
-#undef ENTRY
-#define ENTRY(name) ENTRY_M name
- .macro ENTRY_M name
- .global \name
- ALIGN
-\name:
- .endm
-#endif
-
-
-/**
- * LDIMM - load immediate value
- * STI - enable interruption
- * CLI - disable interruption
- */
-
-#ifdef __ASSEMBLY__
-
-#define LDIMM(reg,x) LDIMM reg x
- .macro LDIMM reg x
- seth \reg, #high(\x)
- or3 \reg, \reg, #low(\x)
- .endm
-
-#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
-#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
- .macro ENABLE_INTERRUPTS reg
- setpsw #0x40 -> nop
- ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
- .endm
-
-#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
- .macro DISABLE_INTERRUPTS reg
- clrpsw #0x40 -> nop
- ; WORKAROUND: "-> nop" is a workaround for the M32700(TS1).
- .endm
-#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
-#define ENABLE_INTERRUPTS(reg) ENABLE_INTERRUPTS reg
- .macro ENABLE_INTERRUPTS reg
- mvfc \reg, psw
- or3 \reg, \reg, #0x0040
- mvtc \reg, psw
- .endm
-
-#define DISABLE_INTERRUPTS(reg) DISABLE_INTERRUPTS reg
- .macro DISABLE_INTERRUPTS reg
- mvfc \reg, psw
- and3 \reg, \reg, #0xffbf
- mvtc \reg, psw
- .endm
-#endif /* CONFIG_CHIP_M32102 */
-
- .macro SAVE_ALL
- push r0 ; orig_r0
- push sp ; spi (r15)
- push lr ; r14
- push r13
- mvfc r13, cr3 ; spu
- push r13
- mvfc r13, bbpc
- push r13
- mvfc r13, bbpsw
- push r13
- mvfc r13, bpc
- push r13
- mvfc r13, psw
- push r13
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
- mvfaclo r13, a1
- push r13
- mvfachi r13, a1
- push r13
- mvfaclo r13, a0
- push r13
- mvfachi r13, a0
- push r13
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
- mvfaclo r13
- push r13
- mvfachi r13
- push r13
- ldi r13, #0
- push r13 ; dummy push acc1h
- push r13 ; dummy push acc1l
-#else
-#error unknown isa configuration
-#endif
- ldi r13, #-1
- push r13 ; syscall_nr (default: -1)
- push r12
- push r11
- push r10
- push r9
- push r8
- push r7
- push r3
- push r2
- push r1
- push r0
- addi sp, #-4 ; room for implicit pt_regs parameter
- push r6
- push r5
- push r4
- .endm
-
- .macro RESTORE_ALL
- pop r4
- pop r5
- pop r6
- addi sp, #4
- pop r0
- pop r1
- pop r2
- pop r3
- pop r7
- pop r8
- pop r9
- pop r10
- pop r11
- pop r12
- addi r15, #4 ; Skip syscall number
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
- pop r13
- mvtachi r13, a0
- pop r13
- mvtaclo r13, a0
- pop r13
- mvtachi r13, a1
- pop r13
- mvtaclo r13, a1
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
- pop r13 ; dummy pop acc1h
- pop r13 ; dummy pop acc1l
- pop r13
- mvtachi r13
- pop r13
- mvtaclo r13
-#else
-#error unknown isa configuration
-#endif
- pop r14
- mvtc r14, psw
- pop r14
- mvtc r14, bpc
- addi sp, #8 ; Skip bbpsw, bbpc
- pop r14
- mvtc r14, cr3 ; spu
- pop r13
- pop lr ; r14
- pop sp ; spi (r15)
- addi sp, #4 ; Skip orig_r0
- .fillinsn
-1: rte
- .section .fixup,"ax"
-2: bl do_exit
- .previous
- .section __ex_table,"a"
- ALIGN
- .long 1b, 2b
- .previous
- .endm
-
-#define GET_CURRENT(reg) get_current reg
- .macro get_current reg
- ldi \reg, #-8192
- and \reg, sp
- .endm
-
-#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
- .macro SWITCH_TO_KERNEL_STACK
- ; switch to kernel stack (spi)
- clrpsw #0x80 -> nop
- .endm
-#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
- .macro SWITCH_TO_KERNEL_STACK
- push r0 ; save r0 for working
- mvfc r0, psw
- and3 r0, r0, #0x00ff7f
- mvtc r0, psw
- slli r0, #16
- bltz r0, 1f ; check BSM-bit
-;
- ;; called from kernel context: previous stack = spi
- pop r0 ; retrieve r0
- bra 2f
- .fillinsn
-1:
- ;; called from user context: previous stack = spu
- mvfc r0, cr3 ; spu
- addi r0, #4
- mvtc r0, cr3 ; spu
- ld r0, @(-4,r0) ; retrieve r0
- .fillinsn
-2:
- .endm
-#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_M32R_ASSEMBLER_H */
diff --git a/arch/m32r/include/asm/atomic.h b/arch/m32r/include/asm/atomic.h
deleted file mode 100644
index 8bf67e55ff54..000000000000
--- a/arch/m32r/include/asm/atomic.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_ATOMIC_H
-#define _ASM_M32R_ATOMIC_H
-
-/*
- * linux/include/asm-m32r/atomic.h
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/types.h>
-#include <asm/assembler.h>
-#include <asm/cmpxchg.h>
-#include <asm/dcache_clear.h>
-#include <asm/barrier.h>
-
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- */
-
-#define ATOMIC_INIT(i) { (i) }
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-#define atomic_read(v) READ_ONCE((v)->counter)
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-#define atomic_set(v,i) WRITE_ONCE(((v)->counter), (i))
-
-#ifdef CONFIG_CHIP_M32700_TS1
-#define __ATOMIC_CLOBBER , "r4"
-#else
-#define __ATOMIC_CLOBBER
-#endif
-
-#define ATOMIC_OP(op) \
-static __inline__ void atomic_##op(int i, atomic_t *v) \
-{ \
- unsigned long flags; \
- int result; \
- \
- local_irq_save(flags); \
- __asm__ __volatile__ ( \
- "# atomic_" #op " \n\t" \
- DCACHE_CLEAR("%0", "r4", "%1") \
- M32R_LOCK" %0, @%1; \n\t" \
- #op " %0, %2; \n\t" \
- M32R_UNLOCK" %0, @%1; \n\t" \
- : "=&r" (result) \
- : "r" (&v->counter), "r" (i) \
- : "memory" \
- __ATOMIC_CLOBBER \
- ); \
- local_irq_restore(flags); \
-} \
-
-#define ATOMIC_OP_RETURN(op) \
-static __inline__ int atomic_##op##_return(int i, atomic_t *v) \
-{ \
- unsigned long flags; \
- int result; \
- \
- local_irq_save(flags); \
- __asm__ __volatile__ ( \
- "# atomic_" #op "_return \n\t" \
- DCACHE_CLEAR("%0", "r4", "%1") \
- M32R_LOCK" %0, @%1; \n\t" \
- #op " %0, %2; \n\t" \
- M32R_UNLOCK" %0, @%1; \n\t" \
- : "=&r" (result) \
- : "r" (&v->counter), "r" (i) \
- : "memory" \
- __ATOMIC_CLOBBER \
- ); \
- local_irq_restore(flags); \
- \
- return result; \
-}
-
-#define ATOMIC_FETCH_OP(op) \
-static __inline__ int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- unsigned long flags; \
- int result, val; \
- \
- local_irq_save(flags); \
- __asm__ __volatile__ ( \
- "# atomic_fetch_" #op " \n\t" \
- DCACHE_CLEAR("%0", "r4", "%2") \
- M32R_LOCK" %1, @%2; \n\t" \
- "mv %0, %1 \n\t" \
- #op " %1, %3; \n\t" \
- M32R_UNLOCK" %1, @%2; \n\t" \
- : "=&r" (result), "=&r" (val) \
- : "r" (&v->counter), "r" (i) \
- : "memory" \
- __ATOMIC_CLOBBER \
- ); \
- local_irq_restore(flags); \
- \
- return result; \
-}
-
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(add)
-ATOMIC_OPS(sub)
-
-#undef ATOMIC_OPS
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(and)
-ATOMIC_OPS(or)
-ATOMIC_OPS(xor)
-
-#undef ATOMIC_OPS
-#undef ATOMIC_FETCH_OP
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
-
-/**
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-
-/**
- * atomic_inc_return - increment atomic variable and return it
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1 and returns the result.
- */
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
- unsigned long flags;
- int result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# atomic_inc_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "addi %0, #1; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&v->counter)
- : "memory"
- __ATOMIC_CLOBBER
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * atomic_dec_return - decrement atomic variable and return it
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and returns the result.
- */
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
- unsigned long flags;
- int result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# atomic_dec_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "addi %0, #-1; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&v->counter)
- : "memory"
- __ATOMIC_CLOBBER
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-#define atomic_inc(v) ((void)atomic_inc_return(v))
-
-/**
- * atomic_dec - decrement atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-#define atomic_dec(v) ((void)atomic_dec_return(v))
-
-/**
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-/**
- * atomic_dec_and_test - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all
- * other cases.
- */
-#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
-
-/**
- * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define atomic_add_negative(i,v) (atomic_add_return((i), (v)) < 0)
-
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-/**
- * __atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns the old value of @v.
- */
-static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- int c, old;
- c = atomic_read(v);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = atomic_cmpxchg((v), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c;
-}
-
-#endif /* _ASM_M32R_ATOMIC_H */
diff --git a/arch/m32r/include/asm/barrier.h b/arch/m32r/include/asm/barrier.h
deleted file mode 100644
index 1a40265e8d88..000000000000
--- a/arch/m32r/include/asm/barrier.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_BARRIER_H
-#define _ASM_M32R_BARRIER_H
-
-#define nop() __asm__ __volatile__ ("nop" : : )
-
-#include <asm-generic/barrier.h>
-
-#endif /* _ASM_M32R_BARRIER_H */
diff --git a/arch/m32r/include/asm/bitops.h b/arch/m32r/include/asm/bitops.h
deleted file mode 100644
index 64e70e57c154..000000000000
--- a/arch/m32r/include/asm/bitops.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_BITOPS_H
-#define _ASM_M32R_BITOPS_H
-
-/*
- * linux/include/asm-m32r/bitops.h
- *
- * Copyright 1992, Linus Torvalds.
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <linux/irqflags.h>
-#include <asm/assembler.h>
-#include <asm/byteorder.h>
-#include <asm/dcache_clear.h>
-#include <asm/types.h>
-#include <asm/barrier.h>
-
-/*
- * These have to be done with inline assembly: that way the bit-setting
- * is guaranteed to be atomic. All bit operations return 0 if the bit
- * was cleared before the operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-
-/**
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered. See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void set_bit(int nr, volatile void * addr)
-{
- __u32 mask;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r6", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "or %0, %2; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/**
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered. However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
- * in order to ensure changes are visible on other processors.
- */
-static __inline__ void clear_bit(int nr, volatile void * addr)
-{
- __u32 mask;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
-
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r6", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "and %0, %2; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (a), "r" (~mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/**
- * change_bit - Toggle a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static __inline__ void change_bit(int nr, volatile void * addr)
-{
- __u32 mask;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r6", "%1")
- M32R_LOCK" %0, @%1; \n\t"
- "xor %0, %2; \n\t"
- M32R_UNLOCK" %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/**
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_set_bit(int nr, volatile void * addr)
-{
- __u32 mask, oldbit;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "%1", "%2")
- M32R_LOCK" %0, @%2; \n\t"
- "mv %1, %0; \n\t"
- "and %0, %3; \n\t"
- "or %1, %3; \n\t"
- M32R_UNLOCK" %1, @%2; \n\t"
- : "=&r" (oldbit), "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
- );
- local_irq_restore(flags);
-
- return (oldbit != 0);
-}
-
-/**
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
-{
- __u32 mask, oldbit;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
-
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "%1", "%3")
- M32R_LOCK" %0, @%3; \n\t"
- "mv %1, %0; \n\t"
- "and %0, %2; \n\t"
- "not %2, %2; \n\t"
- "and %1, %2; \n\t"
- M32R_UNLOCK" %1, @%3; \n\t"
- : "=&r" (oldbit), "=&r" (tmp), "+r" (mask)
- : "r" (a)
- : "memory"
- );
- local_irq_restore(flags);
-
- return (oldbit != 0);
-}
-
-/**
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static __inline__ int test_and_change_bit(int nr, volatile void * addr)
-{
- __u32 mask, oldbit;
- volatile __u32 *a = addr;
- unsigned long flags;
- unsigned long tmp;
-
- a += (nr >> 5);
- mask = (1 << (nr & 0x1F));
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "%1", "%2")
- M32R_LOCK" %0, @%2; \n\t"
- "mv %1, %0; \n\t"
- "and %0, %3; \n\t"
- "xor %1, %3; \n\t"
- M32R_UNLOCK" %1, @%2; \n\t"
- : "=&r" (oldbit), "=&r" (tmp)
- : "r" (a), "r" (mask)
- : "memory"
- );
- local_irq_restore(flags);
-
- return (oldbit != 0);
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#endif /* __KERNEL__ */
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/le.h>
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_BITOPS_H */
diff --git a/arch/m32r/include/asm/bug.h b/arch/m32r/include/asm/bug.h
deleted file mode 100644
index 7197688254da..000000000000
--- a/arch/m32r/include/asm/bug.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32R_BUG_H
-#define _M32R_BUG_H
-#include <asm-generic/bug.h>
-#endif
diff --git a/arch/m32r/include/asm/bugs.h b/arch/m32r/include/asm/bugs.h
deleted file mode 100644
index 74a6d428aebe..000000000000
--- a/arch/m32r/include/asm/bugs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_BUGS_H
-#define _ASM_M32R_BUGS_H
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- * void check_bugs(void);
- */
-#include <asm/processor.h>
-
-static void __init check_bugs(void)
-{
- extern unsigned long loops_per_jiffy;
-
- current_cpu_data.loops_per_jiffy = loops_per_jiffy;
-}
-
-#endif /* _ASM_M32R_BUGS_H */
diff --git a/arch/m32r/include/asm/cache.h b/arch/m32r/include/asm/cache.h
deleted file mode 100644
index 47a766a258f8..000000000000
--- a/arch/m32r/include/asm/cache.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_CACHE_H
-#define _ASM_M32R_CACHE_H
-
-/* L1 cache line size */
-#define L1_CACHE_SHIFT 4
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#endif /* _ASM_M32R_CACHE_H */
diff --git a/arch/m32r/include/asm/cachectl.h b/arch/m32r/include/asm/cachectl.h
deleted file mode 100644
index 12f73f6c1759..000000000000
--- a/arch/m32r/include/asm/cachectl.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * cachectl.h -- defines for M32R cache control system calls
- *
- * Copyright (C) 2003 by Kazuhiro Inaoka
- */
-#ifndef __ASM_M32R_CACHECTL
-#define __ASM_M32R_CACHECTL
-
-/*
- * Options for cacheflush system call
- *
- * cacheflush() is currently fluch_cache_all().
- */
-#define ICACHE (1<<0) /* flush instruction cache */
-#define DCACHE (1<<1) /* writeback and flush data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-/*
- * Caching modes for the cachectl(2) call
- *
- * cachectl(2) is currently not supported and returns ENOSYS.
- */
-#define CACHEABLE 0 /* make pages cacheable */
-#define UNCACHEABLE 1 /* make pages uncacheable */
-
-#endif /* __ASM_M32R_CACHECTL */
diff --git a/arch/m32r/include/asm/cacheflush.h b/arch/m32r/include/asm/cacheflush.h
deleted file mode 100644
index 5ad2a3045483..000000000000
--- a/arch/m32r/include/asm/cacheflush.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_CACHEFLUSH_H
-#define _ASM_M32R_CACHEFLUSH_H
-
-#include <linux/mm.h>
-
-extern void _flush_cache_all(void);
-extern void _flush_cache_copyback_all(void);
-
-#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#ifndef CONFIG_SMP
-#define flush_icache_range(start, end) _flush_cache_copyback_all()
-#define flush_icache_page(vma,pg) _flush_cache_copyback_all()
-#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_copyback_all()
-#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
-#else /* CONFIG_SMP */
-extern void smp_flush_cache_all(void);
-#define flush_icache_range(start, end) smp_flush_cache_all()
-#define flush_icache_page(vma,pg) smp_flush_cache_all()
-#define flush_icache_user_range(vma,pg,adr,len) smp_flush_cache_all()
-#define flush_cache_sigtramp(addr) _flush_cache_copyback_all()
-#endif /* CONFIG_SMP */
-#elif defined(CONFIG_CHIP_M32102)
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_icache_range(start, end) _flush_cache_all()
-#define flush_icache_page(vma,pg) _flush_cache_all()
-#define flush_icache_user_range(vma,pg,adr,len) _flush_cache_all()
-#define flush_cache_sigtramp(addr) _flush_cache_all()
-#else
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_icache_range(start, end) do { } while (0)
-#define flush_icache_page(vma,pg) do { } while (0)
-#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
-#define flush_cache_sigtramp(addr) do { } while (0)
-#endif /* CONFIG_CHIP_* */
-
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { \
- memcpy(dst, src, len); \
- flush_icache_user_range(vma, page, vaddr, len); \
-} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-
-#endif /* _ASM_M32R_CACHEFLUSH_H */
diff --git a/arch/m32r/include/asm/checksum.h b/arch/m32r/include/asm/checksum.h
deleted file mode 100644
index d68e93c9bd62..000000000000
--- a/arch/m32r/include/asm/checksum.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifdef __KERNEL__
-#ifndef _ASM_M32R_CHECKSUM_H
-#define _ASM_M32R_CHECKSUM_H
-
-/*
- * include/asm-m32r/checksum.h
- *
- * IP/TCP/UDP checksum routines
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Some code taken from mips and parisc architecture.
- *
- * Copyright (C) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/in6.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * The same as csum_partial, but copies from src while it checksums.
- *
- * Here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum);
-
-/*
- * This is a new version of the above that records errors it finds in *errp,
- * but continues and zeros thre rest of the buffer.
- */
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum,
- int *err_ptr);
-
-/*
- * Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
- unsigned long tmpreg;
- __asm__(
- " sll3 %1, %0, #16 \n"
- " cmp %0, %0 \n"
- " addx %0, %1 \n"
- " ldi %1, #0 \n"
- " srli %0, #16 \n"
- " addx %0, %1 \n"
- " xor3 %0, %0, #0x0000ffff \n"
- : "=r" (sum), "=&r" (tmpreg)
- : "0" (sum)
- : "cbit"
- );
- return (__force __sum16)sum;
-}
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- unsigned long tmpreg0, tmpreg1;
- __wsum sum;
-
- __asm__ __volatile__(
- " ld %0, @%1+ \n"
- " addi %2, #-4 \n"
- "# bgez %2, 2f \n"
- " cmp %0, %0 \n"
- " ld %3, @%1+ \n"
- " ld %4, @%1+ \n"
- " addx %0, %3 \n"
- " ld %3, @%1+ \n"
- " addx %0, %4 \n"
- " addx %0, %3 \n"
- " .fillinsn\n"
- "1: \n"
- " ld %4, @%1+ \n"
- " addi %2, #-1 \n"
- " addx %0, %4 \n"
- " bgtz %2, 1b \n"
- "\n"
- " ldi %3, #0 \n"
- " addx %0, %3 \n"
- " .fillinsn\n"
- "2: \n"
- /* Since the input registers which are loaded with iph and ihl
- are modified, we must also specify them as outputs, or gcc
- will assume they contain their original values. */
- : "=&r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmpreg0), "=&r" (tmpreg1)
- : "1" (iph), "2" (ihl)
- : "cbit", "memory");
-
- return csum_fold(sum);
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
-#if defined(__LITTLE_ENDIAN)
- unsigned long len_proto = (proto + len) << 8;
-#else
- unsigned long len_proto = proto + len;
-#endif
- unsigned long tmpreg;
-
- __asm__(
- " cmp %0, %0 \n"
- " addx %0, %2 \n"
- " addx %0, %3 \n"
- " addx %0, %4 \n"
- " ldi %1, #0 \n"
- " addx %0, %1 \n"
- : "=r" (sum), "=&r" (tmpreg)
- : "r" (daddr), "r" (saddr), "r" (len_proto), "0" (sum)
- : "cbit"
- );
-
- return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
- return csum_fold (csum_partial(buff, len, 0));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
- const struct in6_addr *daddr,
- __u32 len, unsigned short proto,
- __wsum sum)
-{
- unsigned long tmpreg0, tmpreg1, tmpreg2, tmpreg3;
- __asm__(
- " ld %1, @(%5) \n"
- " ld %2, @(4,%5) \n"
- " ld %3, @(8,%5) \n"
- " ld %4, @(12,%5) \n"
- " add %0, %1 \n"
- " addx %0, %2 \n"
- " addx %0, %3 \n"
- " addx %0, %4 \n"
- " ld %1, @(%6) \n"
- " ld %2, @(4,%6) \n"
- " ld %3, @(8,%6) \n"
- " ld %4, @(12,%6) \n"
- " addx %0, %1 \n"
- " addx %0, %2 \n"
- " addx %0, %3 \n"
- " addx %0, %4 \n"
- " addx %0, %7 \n"
- " addx %0, %8 \n"
- " ldi %1, #0 \n"
- " addx %0, %1 \n"
- : "=&r" (sum), "=&r" (tmpreg0), "=&r" (tmpreg1),
- "=&r" (tmpreg2), "=&r" (tmpreg3)
- : "r" (saddr), "r" (daddr),
- "r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
- : "cbit"
- );
-
- return csum_fold(sum);
-}
-
-#endif /* _ASM_M32R_CHECKSUM_H */
-#endif /* __KERNEL__ */
diff --git a/arch/m32r/include/asm/cmpxchg.h b/arch/m32r/include/asm/cmpxchg.h
deleted file mode 100644
index 1ccdce5ff0ac..000000000000
--- a/arch/m32r/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_CMPXCHG_H
-#define _ASM_M32R_CMPXCHG_H
-
-/*
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/irqflags.h>
-#include <asm/assembler.h>
-#include <asm/dcache_clear.h>
-
-extern void __xchg_called_with_bad_pointer(void);
-
-static __always_inline unsigned long
-__xchg(unsigned long x, volatile void *ptr, int size)
-{
- unsigned long flags;
- unsigned long tmp = 0;
-
- local_irq_save(flags);
-
- switch (size) {
-#ifndef CONFIG_SMP
- case 1:
- __asm__ __volatile__ (
- "ldb %0, @%2 \n\t"
- "stb %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 2:
- __asm__ __volatile__ (
- "ldh %0, @%2 \n\t"
- "sth %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 4:
- __asm__ __volatile__ (
- "ld %0, @%2 \n\t"
- "st %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
-#else /* CONFIG_SMP */
- case 4:
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r4", "%2")
- "lock %0, @%2; \n\t"
- "unlock %1, @%2; \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- break;
-#endif /* CONFIG_SMP */
- default:
- __xchg_called_with_bad_pointer();
- }
-
- local_irq_restore(flags);
-
- return (tmp);
-}
-
-#define xchg(ptr, x) ({ \
- ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), \
- sizeof(*(ptr)))); \
-})
-
-static __always_inline unsigned long
-__xchg_local(unsigned long x, volatile void *ptr, int size)
-{
- unsigned long flags;
- unsigned long tmp = 0;
-
- local_irq_save(flags);
-
- switch (size) {
- case 1:
- __asm__ __volatile__ (
- "ldb %0, @%2 \n\t"
- "stb %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 2:
- __asm__ __volatile__ (
- "ldh %0, @%2 \n\t"
- "sth %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- case 4:
- __asm__ __volatile__ (
- "ld %0, @%2 \n\t"
- "st %1, @%2 \n\t"
- : "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
- break;
- default:
- __xchg_called_with_bad_pointer();
- }
-
- local_irq_restore(flags);
-
- return (tmp);
-}
-
-#define xchg_local(ptr, x) \
- ((__typeof__(*(ptr)))__xchg_local((unsigned long)(x), (ptr), \
- sizeof(*(ptr))))
-
-static inline unsigned long
-__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
-{
- unsigned long flags;
- unsigned int retval;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r4", "%1")
- M32R_LOCK" %0, @%1; \n"
- " bne %0, %2, 1f; \n"
- M32R_UNLOCK" %3, @%1; \n"
- " bra 2f; \n"
- " .fillinsn \n"
- "1:"
- M32R_UNLOCK" %0, @%1; \n"
- " .fillinsn \n"
- "2:"
- : "=&r" (retval)
- : "r" (p), "r" (old), "r" (new)
- : "cbit", "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return retval;
-}
-
-static inline unsigned long
-__cmpxchg_local_u32(volatile unsigned int *p, unsigned int old,
- unsigned int new)
-{
- unsigned long flags;
- unsigned int retval;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n"
- " bne %0, %2, 1f; \n"
- "st %3, @%1; \n"
- " bra 2f; \n"
- " .fillinsn \n"
- "1:"
- "st %0, @%1; \n"
- " .fillinsn \n"
- "2:"
- : "=&r" (retval)
- : "r" (p), "r" (old), "r" (new)
- : "cbit", "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return retval;
-}
-
-/* This function doesn't exist, so you'll get a linker error
- if something tries to do an invalid cmpxchg(). */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return __cmpxchg_u32(ptr, old, new);
-#if 0 /* we don't have __cmpxchg_u64 */
- case 8:
- return __cmpxchg_u64(ptr, old, new);
-#endif /* 0 */
- }
- __cmpxchg_called_with_bad_pointer();
- return old;
-}
-
-#define cmpxchg(ptr, o, n) ({ \
- ((__typeof__(*(ptr))) \
- __cmpxchg((ptr), (unsigned long)(o), \
- (unsigned long)(n), \
- sizeof(*(ptr)))); \
-})
-
-#include <asm-generic/cmpxchg-local.h>
-
-static inline unsigned long __cmpxchg_local(volatile void *ptr,
- unsigned long old,
- unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return __cmpxchg_local_u32(ptr, old, new);
- default:
- return __cmpxchg_local_generic(ptr, old, new, size);
- }
-
- return old;
-}
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n) \
- ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
- (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif /* _ASM_M32R_CMPXCHG_H */
diff --git a/arch/m32r/include/asm/dcache_clear.h b/arch/m32r/include/asm/dcache_clear.h
deleted file mode 100644
index a0ae06c2e9e7..000000000000
--- a/arch/m32r/include/asm/dcache_clear.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_DCACHE_CLEAR_H
-#define _ASM_M32R_DCACHE_CLEAR_H
-
-#ifdef CONFIG_CHIP_M32700_TS1
-#define DCACHE_CLEAR(reg0, reg1, addr) \
- "seth "reg1", #high(dcache_dummy); \n\t" \
- "or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
- "lock "reg0", @"reg1"; \n\t" \
- "add3 "reg0", "addr", #0x1000; \n\t" \
- "ld "reg0", @"reg0"; \n\t" \
- "add3 "reg0", "addr", #0x2000; \n\t" \
- "ld "reg0", @"reg0"; \n\t" \
- "unlock "reg0", @"reg1"; \n\t"
- /* FIXME: This workaround code cannot handle kernel modules
- * correctly under SMP environment.
- */
-#else /* CONFIG_CHIP_M32700_TS1 */
-#define DCACHE_CLEAR(reg0, reg1, addr)
-#endif /* CONFIG_CHIP_M32700_TS1 */
-
-#endif /* _ASM_M32R_DCACHE_CLEAR_H */
diff --git a/arch/m32r/include/asm/delay.h b/arch/m32r/include/asm/delay.h
deleted file mode 100644
index 9670e127b7b2..000000000000
--- a/arch/m32r/include/asm/delay.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/delay.h>
diff --git a/arch/m32r/include/asm/device.h b/arch/m32r/include/asm/device.h
deleted file mode 100644
index 5203fc87f080..000000000000
--- a/arch/m32r/include/asm/device.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-struct dev_archdata {
-};
-
-struct pdev_archdata {
-};
diff --git a/arch/m32r/include/asm/div64.h b/arch/m32r/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/m32r/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/arch/m32r/include/asm/dma.h b/arch/m32r/include/asm/dma.h
deleted file mode 100644
index 661bc3b343ed..000000000000
--- a/arch/m32r/include/asm/dma.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_DMA_H
-#define _ASM_M32R_DMA_H
-
-#include <asm/io.h>
-
-/*
- * The maximum address that we can perform a DMA transfer
- * to on this platform
- */
-#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x20000000)
-
-#endif /* _ASM_M32R_DMA_H */
diff --git a/arch/m32r/include/asm/elf.h b/arch/m32r/include/asm/elf.h
deleted file mode 100644
index 576b2ff57957..000000000000
--- a/arch/m32r/include/asm/elf.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R__ELF_H
-#define _ASM_M32R__ELF_H
-
-/*
- * ELF-specific definitions.
- *
- * Copyright (C) 1999-2004, Renesas Technology Corp.
- * Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-#include <asm/page.h>
-
-/* M32R relocation types */
-#define R_M32R_NONE 0
-#define R_M32R_16 1
-#define R_M32R_32 2
-#define R_M32R_24 3
-#define R_M32R_10_PCREL 4
-#define R_M32R_18_PCREL 5
-#define R_M32R_26_PCREL 6
-#define R_M32R_HI16_ULO 7
-#define R_M32R_HI16_SLO 8
-#define R_M32R_LO16 9
-#define R_M32R_SDA16 10
-#define R_M32R_GNU_VTINHERIT 11
-#define R_M32R_GNU_VTENTRY 12
-
-#define R_M32R_16_RELA 33
-#define R_M32R_32_RELA 34
-#define R_M32R_24_RELA 35
-#define R_M32R_10_PCREL_RELA 36
-#define R_M32R_18_PCREL_RELA 37
-#define R_M32R_26_PCREL_RELA 38
-#define R_M32R_HI16_ULO_RELA 39
-#define R_M32R_HI16_SLO_RELA 40
-#define R_M32R_LO16_RELA 41
-#define R_M32R_SDA16_RELA 42
-#define R_M32R_RELA_GNU_VTINHERIT 43
-#define R_M32R_RELA_GNU_VTENTRY 44
-
-#define R_M32R_GOT24 48
-#define R_M32R_26_PLTREL 49
-#define R_M32R_COPY 50
-#define R_M32R_GLOB_DAT 51
-#define R_M32R_JMP_SLOT 52
-#define R_M32R_RELATIVE 53
-#define R_M32R_GOTOFF 54
-#define R_M32R_GOTPC24 55
-#define R_M32R_GOT16_HI_ULO 56
-#define R_M32R_GOT16_HI_SLO 57
-#define R_M32R_GOT16_LO 58
-#define R_M32R_GOTPC_HI_ULO 59
-#define R_M32R_GOTPC_HI_SLO 60
-#define R_M32R_GOTPC_LO 61
-#define R_M32R_GOTOFF_HI_ULO 62
-#define R_M32R_GOTOFF_HI_SLO 63
-#define R_M32R_GOTOFF_LO 64
-
-#define R_M32R_NUM 256
-
-/*
- * ELF register definitions..
- */
-#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
-
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* We have no FP mumumu. */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
- (((x)->e_machine == EM_M32R) || ((x)->e_machine == EM_CYGNUS_M32R))
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#if defined(__LITTLE_ENDIAN__)
-#define ELF_DATA ELFDATA2LSB
-#elif defined(__BIG_ENDIAN__)
-#define ELF_DATA ELFDATA2MSB
-#else
-#error no endian defined
-#endif
-#define ELF_ARCH EM_M32R
-
-/* r0 is set by ld.so to a pointer to a function which might be
- * registered using 'atexit'. This provides a mean for the dynamic
- * linker to call DT_FINI functions for shared libraries that have
- * been loaded before the code runs.
- *
- * So that we can use the same startup file with static executables,
- * we start programs with a value of 0 to indicate that there is no
- * such function.
- */
-#define ELF_PLAT_INIT(_r, load_addr) (_r)->r0 = 0
-
-#define ELF_EXEC_PAGESIZE PAGE_SIZE
-
-/*
- * This is the location that an ET_DYN program is loaded if exec'ed.
- * Typical use of this is to invoke "./ld.so someprog" to test out a
- * new version of the loader. We need to make sure that it is out of
- * the way of the program that it will "exec", and that there is
- * sufficient room for the brk.
- */
-#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
-
-/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
- now struct_user_regs, they are different) */
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
- memcpy((char *)pr_reg, (char *)regs, sizeof (struct pt_regs));
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this CPU supports. */
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-#define ELF_PLATFORM (NULL)
-
-#endif /* _ASM_M32R__ELF_H */
diff --git a/arch/m32r/include/asm/emergency-restart.h b/arch/m32r/include/asm/emergency-restart.h
deleted file mode 100644
index cca44d5ae264..000000000000
--- a/arch/m32r/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/m32r/include/asm/fb.h b/arch/m32r/include/asm/fb.h
deleted file mode 100644
index 9a0bca2686fd..000000000000
--- a/arch/m32r/include/asm/fb.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
- unsigned long off)
-{
- vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
-}
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
- return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/arch/m32r/include/asm/flat.h b/arch/m32r/include/asm/flat.h
deleted file mode 100644
index dfcb0e4eb256..000000000000
--- a/arch/m32r/include/asm/flat.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * include/asm-m32r/flat.h
- *
- * uClinux flat-format executables
- *
- * Copyright (C) 2004 Kazuhiro Inaoka
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive for
- * more details.
- */
-#ifndef __ASM_M32R_FLAT_H
-#define __ASM_M32R_FLAT_H
-
-#define flat_argvp_envp_on_stack() 0
-#define flat_old_ram_flag(flags) (flags)
-#define flat_set_persistent(relval, p) 0
-#define flat_reloc_valid(reloc, size) \
- (((reloc) - textlen_for_m32r_lo16_data) <= (size))
-
-/* Convert a relocation entry into an address. */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
- return relval & 0x00ffffff; /* Mask out top 8-bits */
-}
-
-#define flat_m32r_get_reloc_type(relval) ((relval) >> 24)
-
-#define M32R_SETH_OPCODE 0xd0c00000 /* SETH instruction code */
-
-#define FLAT_M32R_32 0x00 /* 32bits reloc */
-#define FLAT_M32R_24 0x01 /* unsigned 24bits reloc */
-#define FLAT_M32R_16 0x02 /* 16bits reloc */
-#define FLAT_M32R_LO16 0x03 /* signed low 16bits reloc (low()) */
-#define FLAT_M32R_LO16_DATA 0x04 /* signed low 16bits reloc (low())
- for a symbol in .data section */
- /* High 16bits of an address used
- when the lower 16bbits are treated
- as unsigned.
- To create SETH instruction only.
- 0x1X: X means a number of register.
- 0x10 - 0x3F are reserved. */
-#define FLAT_M32R_HI16_ULO 0x10 /* reloc for SETH Rn,#high(imm16) */
- /* High 16bits of an address used
- when the lower 16bbits are treated
- as signed.
- To create SETH instruction only.
- 0x2X: X means a number of register.
- 0x20 - 0x4F are reserved. */
-#define FLAT_M32R_HI16_SLO 0x20 /* reloc for SETH Rn,#shigh(imm16) */
-
-static unsigned long textlen_for_m32r_lo16_data = 0;
-
-static inline unsigned long m32r_flat_get_addr_from_rp (u32 *rp,
- u32 relval,
- u32 textlen)
-{
- unsigned int reloc = flat_m32r_get_reloc_type (relval);
- textlen_for_m32r_lo16_data = 0;
- if (reloc & 0xf0) {
- unsigned long addr = htonl(*rp);
- switch (reloc & 0xf0)
- {
- case FLAT_M32R_HI16_ULO:
- case FLAT_M32R_HI16_SLO:
- if (addr == 0) {
- /* put "seth Rn,#0x0" instead of 0 (addr). */
- *rp = (M32R_SETH_OPCODE | ((reloc & 0x0f)<<24));
- }
- return addr;
- default:
- break;
- }
- } else {
- switch (reloc)
- {
- case FLAT_M32R_LO16:
- return htonl(*rp) & 0xFFFF;
- case FLAT_M32R_LO16_DATA:
- /* FIXME: The return value will decrease by textlen
- at m32r_flat_put_addr_at_rp () */
- textlen_for_m32r_lo16_data = textlen;
- return (htonl(*rp) & 0xFFFF) + textlen;
- case FLAT_M32R_16:
- return htons(*(unsigned short *)rp) & 0xFFFF;
- case FLAT_M32R_24:
- return htonl(*rp) & 0xFFFFFF;
- case FLAT_M32R_32:
- return htonl(*rp);
- default:
- break;
- }
- }
- return ~0; /* bogus value */
-}
-
-static inline int flat_put_addr_at_rp(u32 *rp, u32 addr, u32 relval)
-{
- unsigned int reloc = flat_m32r_get_reloc_type (relval);
- if (reloc & 0xf0) {
- unsigned long Rn = reloc & 0x0f; /* get a number of register */
- Rn <<= 24; /* 0x0R000000 */
- reloc &= 0xf0;
- switch (reloc)
- {
- case FLAT_M32R_HI16_ULO: /* To create SETH Rn,#high(imm16) */
- *rp = (M32R_SETH_OPCODE | Rn
- | ((addr >> 16) & 0xFFFF));
- break;
- case FLAT_M32R_HI16_SLO: /* To create SETH Rn,#shigh(imm16) */
- *rp = (M32R_SETH_OPCODE | Rn
- | (((addr >> 16) + ((addr & 0x8000) ? 1 : 0))
- & 0xFFFF));
- break;
- }
- } else {
- switch (reloc) {
- case FLAT_M32R_LO16_DATA:
- addr -= textlen_for_m32r_lo16_data;
- textlen_for_m32r_lo16_data = 0;
- case FLAT_M32R_LO16:
- *rp = (htonl(*rp) & 0xFFFF0000) | (addr & 0xFFFF);
- break;
- case FLAT_M32R_16:
- *(unsigned short *)rp = addr & 0xFFFF;
- break;
- case FLAT_M32R_24:
- *rp = (htonl(*rp) & 0xFF000000) | (addr & 0xFFFFFF);
- break;
- case FLAT_M32R_32:
- *rp = addr;
- break;
- }
- }
- return 0;
-}
-
-// kludge - text_len is a local variable in the only user.
-#define flat_get_addr_from_rp(rp, relval, flags, addr, persistent) \
- (m32r_flat_get_addr_from_rp(rp, relval, text_len), 0)
-
-#endif /* __ASM_M32R_FLAT_H */
diff --git a/arch/m32r/include/asm/ftrace.h b/arch/m32r/include/asm/ftrace.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/m32r/include/asm/ftrace.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/m32r/include/asm/futex.h b/arch/m32r/include/asm/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/arch/m32r/include/asm/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/arch/m32r/include/asm/hardirq.h b/arch/m32r/include/asm/hardirq.h
deleted file mode 100644
index 10c23de02b3a..000000000000
--- a/arch/m32r/include/asm/hardirq.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifdef __KERNEL__
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
-
-#include <asm/irq.h>
-#include <asm-generic/hardirq.h>
-
-#endif /* __ASM_HARDIRQ_H */
-#endif /* __KERNEL__ */
diff --git a/arch/m32r/include/asm/hw_irq.h b/arch/m32r/include/asm/hw_irq.h
deleted file mode 100644
index 7138537cda03..000000000000
--- a/arch/m32r/include/asm/hw_irq.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_M32R_HW_IRQ_H
-#define _ASM_M32R_HW_IRQ_H
-
-#endif /* _ASM_M32R_HW_IRQ_H */
diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h
deleted file mode 100644
index a4272d8f0d9c..000000000000
--- a/arch/m32r/include/asm/io.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_IO_H
-#define _ASM_M32R_IO_H
-
-#include <linux/string.h>
-#include <linux/compiler.h>
-#include <asm/page.h> /* __va */
-
-#ifdef __KERNEL__
-
-#define IO_SPACE_LIMIT 0xFFFFFFFF
-
-/**
- * virt_to_phys - map virtual addresses to physical
- * @address: address to remap
- *
- * The returned physical address is the physical (CPU) mapping for
- * the memory address given. It is only valid to use this function on
- * addresses directly mapped or allocated via kmalloc.
- *
- * This function does not give bus mappings for DMA transfers. In
- * almost all conceivable cases a device driver should not be using
- * this function
- */
-
-static inline unsigned long virt_to_phys(volatile void * address)
-{
- return __pa(address);
-}
-
-/**
- * phys_to_virt - map physical address to virtual
- * @address: address to remap
- *
- * The returned virtual address is a current CPU mapping for
- * the memory address given. It is only valid to use this function on
- * addresses that have a kernel mapping
- *
- * This function does not handle bus mappings for DMA transfers. In
- * almost all conceivable cases a device driver should not be using
- * this function
- */
-
-static inline void *phys_to_virt(unsigned long address)
-{
- return __va(address);
-}
-
-extern void __iomem *
-__ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-
-/**
- * ioremap - map bus memory into CPU space
- * @offset: bus address of the memory
- * @size: size of the resource to map
- *
- * ioremap performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- */
-
-static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
-{
- return __ioremap(offset, size, 0);
-}
-
-extern void iounmap(volatile void __iomem *addr);
-#define ioremap_nocache(off,size) ioremap(off,size)
-#define ioremap_wc ioremap_nocache
-#define ioremap_wt ioremap_nocache
-#define ioremap_uc ioremap_nocache
-
-/*
- * IO bus memory addresses are also 1:1 with the physical address
- */
-#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
-#define page_to_bus page_to_phys
-#define virt_to_bus virt_to_phys
-
-extern unsigned char _inb(unsigned long);
-extern unsigned short _inw(unsigned long);
-extern unsigned long _inl(unsigned long);
-extern unsigned char _inb_p(unsigned long);
-extern unsigned short _inw_p(unsigned long);
-extern unsigned long _inl_p(unsigned long);
-extern void _outb(unsigned char, unsigned long);
-extern void _outw(unsigned short, unsigned long);
-extern void _outl(unsigned long, unsigned long);
-extern void _outb_p(unsigned char, unsigned long);
-extern void _outw_p(unsigned short, unsigned long);
-extern void _outl_p(unsigned long, unsigned long);
-extern void _insb(unsigned int, void *, unsigned long);
-extern void _insw(unsigned int, void *, unsigned long);
-extern void _insl(unsigned int, void *, unsigned long);
-extern void _outsb(unsigned int, const void *, unsigned long);
-extern void _outsw(unsigned int, const void *, unsigned long);
-extern void _outsl(unsigned int, const void *, unsigned long);
-
-static inline unsigned char _readb(unsigned long addr)
-{
- return *(volatile unsigned char __force *)addr;
-}
-
-static inline unsigned short _readw(unsigned long addr)
-{
- return *(volatile unsigned short __force *)addr;
-}
-
-static inline unsigned long _readl(unsigned long addr)
-{
- return *(volatile unsigned long __force *)addr;
-}
-
-static inline void _writeb(unsigned char b, unsigned long addr)
-{
- *(volatile unsigned char __force *)addr = b;
-}
-
-static inline void _writew(unsigned short w, unsigned long addr)
-{
- *(volatile unsigned short __force *)addr = w;
-}
-
-static inline void _writel(unsigned long l, unsigned long addr)
-{
- *(volatile unsigned long __force *)addr = l;
-}
-
-#define inb _inb
-#define inw _inw
-#define inl _inl
-#define outb _outb
-#define outw _outw
-#define outl _outl
-
-#define inb_p _inb_p
-#define inw_p _inw_p
-#define inl_p _inl_p
-#define outb_p _outb_p
-#define outw_p _outw_p
-#define outl_p _outl_p
-
-#define insb _insb
-#define insw _insw
-#define insl _insl
-#define outsb _outsb
-#define outsw _outsw
-#define outsl _outsl
-
-#define readb(addr) _readb((unsigned long)(addr))
-#define readw(addr) _readw((unsigned long)(addr))
-#define readl(addr) _readl((unsigned long)(addr))
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
-
-#define writeb(val, addr) _writeb((val), (unsigned long)(addr))
-#define writew(val, addr) _writew((val), (unsigned long)(addr))
-#define writel(val, addr) _writel((val), (unsigned long)(addr))
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define writeb_relaxed writeb
-#define writew_relaxed writew
-#define writel_relaxed writel
-
-#define ioread8 readb
-#define ioread16 readw
-#define ioread32 readl
-#define iowrite8 writeb
-#define iowrite16 writew
-#define iowrite32 writel
-
-#define ioread8_rep(p, dst, count) insb((unsigned long)(p), (dst), (count))
-#define ioread16_rep(p, dst, count) insw((unsigned long)(p), (dst), (count))
-#define ioread32_rep(p, dst, count) insl((unsigned long)(p), (dst), (count))
-
-#define iowrite8_rep(p, src, count) outsb((unsigned long)(p), (src), (count))
-#define iowrite16_rep(p, src, count) outsw((unsigned long)(p), (src), (count))
-#define iowrite32_rep(p, src, count) outsl((unsigned long)(p), (src), (count))
-
-#define ioread16be(addr) be16_to_cpu(readw(addr))
-#define ioread32be(addr) be32_to_cpu(readl(addr))
-#define iowrite16be(v, addr) writew(cpu_to_be16(v), (addr))
-#define iowrite32be(v, addr) writel(cpu_to_be32(v), (addr))
-
-#define mmiowb()
-
-static inline void
-memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
- memset((void __force *) addr, val, count);
-}
-
-static inline void
-memcpy_fromio(void *dst, volatile void __iomem *src, int count)
-{
- memcpy(dst, (void __force *) src, count);
-}
-
-static inline void
-memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
- memcpy((void __force *) dst, src, count);
-}
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p) p
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_IO_H */
diff --git a/arch/m32r/include/asm/irq.h b/arch/m32r/include/asm/irq.h
deleted file mode 100644
index 85b475fff90e..000000000000
--- a/arch/m32r/include/asm/irq.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifdef __KERNEL__
-#ifndef _ASM_M32R_IRQ_H
-#define _ASM_M32R_IRQ_H
-
-
-#if defined(CONFIG_PLAT_USRV)
-/*
- * IRQ definitions for M32700UT
- * M32700 Chip: 64 interrupts
- * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- */
-#define M32700UT_NUM_CPU_IRQ (64)
-#define M32700UT_NUM_PLD_IRQ (32)
-#define M32700UT_IRQ_BASE 0
-#define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE
-#define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
-
-#define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
-#elif defined(CONFIG_PLAT_M32700UT)
-/*
- * IRQ definitions for M32700UT(Rev.C) + M32R-LAN
- * M32700 Chip: 64 interrupts
- * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
- * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
- */
-#define M32700UT_NUM_CPU_IRQ (64)
-#define M32700UT_NUM_PLD_IRQ (32)
-#define M32700UT_NUM_LCD_PLD_IRQ (32)
-#define M32700UT_NUM_LAN_PLD_IRQ (32)
-#define M32700UT_IRQ_BASE 0
-#define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE)
-#define M32700UT_PLD_IRQ_BASE \
- (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
-#define M32700UT_LCD_PLD_IRQ_BASE \
- (M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ)
-#define M32700UT_LAN_PLD_IRQ_BASE \
- (M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ)
-
-#define NR_IRQS \
- (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \
- + M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ)
-#elif defined(CONFIG_PLAT_OPSPUT)
-/*
- * IRQ definitions for OPSPUT + M32R-LAN
- * OPSP Chip: 64 interrupts
- * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin
- * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin
- */
-#define OPSPUT_NUM_CPU_IRQ (64)
-#define OPSPUT_NUM_PLD_IRQ (32)
-#define OPSPUT_NUM_LCD_PLD_IRQ (32)
-#define OPSPUT_NUM_LAN_PLD_IRQ (32)
-#define OPSPUT_IRQ_BASE 0
-#define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE)
-#define OPSPUT_PLD_IRQ_BASE \
- (OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ)
-#define OPSPUT_LCD_PLD_IRQ_BASE \
- (OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ)
-#define OPSPUT_LAN_PLD_IRQ_BASE \
- (OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ)
-
-#define NR_IRQS \
- (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \
- + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ)
-
-#elif defined(CONFIG_PLAT_M32104UT)
-/*
- * IRQ definitions for M32104UT
- * M32104 Chip: 64 interrupts
- * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin
- */
-#define M32104UT_NUM_CPU_IRQ (64)
-#define M32104UT_NUM_PLD_IRQ (32)
-#define M32104UT_IRQ_BASE 0
-#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE
-#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
-
-#define NR_IRQS \
- (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ)
-
-#else
-#define NR_IRQS 64
-#endif
-
-#define irq_canonicalize(irq) (irq)
-
-#endif /* _ASM_M32R_IRQ_H */
-#endif /* __KERNEL__ */
diff --git a/arch/m32r/include/asm/irq_regs.h b/arch/m32r/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/arch/m32r/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/m32r/include/asm/irqflags.h b/arch/m32r/include/asm/irqflags.h
deleted file mode 100644
index 1f92d29982ae..000000000000
--- a/arch/m32r/include/asm/irqflags.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#ifndef _ASM_M32R_IRQFLAGS_H
-#define _ASM_M32R_IRQFLAGS_H
-
-#include <linux/types.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
- asm volatile("mvfc %0,psw" : "=r"(flags));
- return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
-#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
- asm volatile (
- "clrpsw #0x40 -> nop"
- : : : "memory");
-#else
- unsigned long tmpreg0, tmpreg1;
- asm volatile (
- "ld24 %0, #0 ; Use 32-bit insn. \n\t"
- "mvfc %1, psw ; No interrupt can be accepted here. \n\t"
- "mvtc %0, psw \n\t"
- "and3 %0, %1, #0xffbf \n\t"
- "mvtc %0, psw \n\t"
- : "=&r" (tmpreg0), "=&r" (tmpreg1)
- :
- : "cbit", "memory");
-#endif
-}
-
-static inline void arch_local_irq_enable(void)
-{
-#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104)
- asm volatile (
- "setpsw #0x40 -> nop"
- : : : "memory");
-#else
- unsigned long tmpreg;
- asm volatile (
- "mvfc %0, psw; \n\t"
- "or3 %0, %0, #0x0040; \n\t"
- "mvtc %0, psw; \n\t"
- : "=&r" (tmpreg)
- :
- : "cbit", "memory");
-#endif
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
-#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104))
- asm volatile (
- "mvfc %0, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- : "=r" (flags)
- :
- : "memory");
-#else
- unsigned long tmpreg;
- asm volatile (
- "ld24 %1, #0 \n\t"
- "mvfc %0, psw \n\t"
- "mvtc %1, psw \n\t"
- "and3 %1, %0, #0xffbf \n\t"
- "mvtc %1, psw \n\t"
- : "=r" (flags), "=&r" (tmpreg)
- :
- : "cbit", "memory");
-#endif
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile("mvtc %0,psw"
- :
- : "r" (flags)
- : "cbit", "memory");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return !(flags & 0x40);
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#endif /* _ASM_M32R_IRQFLAGS_H */
diff --git a/arch/m32r/include/asm/kdebug.h b/arch/m32r/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/arch/m32r/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/m32r/include/asm/kmap_types.h b/arch/m32r/include/asm/kmap_types.h
deleted file mode 100644
index 3dcba0d17d40..000000000000
--- a/arch/m32r/include/asm/kmap_types.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __M32R_KMAP_TYPES_H
-#define __M32R_KMAP_TYPES_H
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define __WITH_KM_FENCE
-#endif
-
-#include <asm-generic/kmap_types.h>
-
-#undef __WITH_KM_FENCE
-
-#endif /* __M32R_KMAP_TYPES_H */
diff --git a/arch/m32r/include/asm/linkage.h b/arch/m32r/include/asm/linkage.h
deleted file mode 100644
index f1aee6ec5bc3..000000000000
--- a/arch/m32r/include/asm/linkage.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .balign 4
-#define __ALIGN_STR ".balign 4"
-
-#endif /* __ASM_LINKAGE_H */
diff --git a/arch/m32r/include/asm/local.h b/arch/m32r/include/asm/local.h
deleted file mode 100644
index 6780680c185d..000000000000
--- a/arch/m32r/include/asm/local.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __M32R_LOCAL_H
-#define __M32R_LOCAL_H
-
-/*
- * linux/include/asm-m32r/local.h
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- * Copyright (C) 2007 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
- */
-
-#include <linux/percpu.h>
-#include <asm/assembler.h>
-#include <asm/local.h>
-
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- */
-
-/*
- * Make sure gcc doesn't try to be clever and move things around
- * on us. We need to use _exactly_ the address the user gave us,
- * not some alias that contains the same information.
- */
-typedef struct { volatile int counter; } local_t;
-
-#define LOCAL_INIT(i) { (i) }
-
-/**
- * local_read - read local variable
- * @l: pointer of type local_t
- *
- * Atomically reads the value of @l.
- */
-#define local_read(l) ((l)->counter)
-
-/**
- * local_set - set local variable
- * @l: pointer of type local_t
- * @i: required value
- *
- * Atomically sets the value of @l to @i.
- */
-#define local_set(l, i) (((l)->counter) = (i))
-
-/**
- * local_add_return - add long to local variable and return it
- * @i: long value to add
- * @l: pointer of type local_t
- *
- * Atomically adds @i to @l and return (@i + @l).
- */
-static inline long local_add_return(long i, local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_add_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "add %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter), "r" (i)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_sub_return - subtract long from local variable and return it
- * @i: long value to subtract
- * @l: pointer of type local_t
- *
- * Atomically subtracts @i from @l and return (@l - @i).
- */
-static inline long local_sub_return(long i, local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_sub_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "sub %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter), "r" (i)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_add - add long to local variable
- * @i: long value to add
- * @l: pointer of type local_t
- *
- * Atomically adds @i to @l.
- */
-#define local_add(i, l) ((void) local_add_return((i), (l)))
-
-/**
- * local_sub - subtract the local variable
- * @i: long value to subtract
- * @l: pointer of type local_t
- *
- * Atomically subtracts @i from @l.
- */
-#define local_sub(i, l) ((void) local_sub_return((i), (l)))
-
-/**
- * local_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @l: pointer of type local_t
- *
- * Atomically subtracts @i from @l and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
-
-/**
- * local_inc_return - increment local variable and return it
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1 and returns the result.
- */
-static inline long local_inc_return(local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_inc_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "addi %0, #1; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_dec_return - decrement local variable and return it
- * @l: pointer of type local_t
- *
- * Atomically decrements @l by 1 and returns the result.
- */
-static inline long local_dec_return(local_t *l)
-{
- unsigned long flags;
- long result;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_dec_return \n\t"
- DCACHE_CLEAR("%0", "r4", "%1")
- "ld %0, @%1; \n\t"
- "addi %0, #-1; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (result)
- : "r" (&l->counter)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-
- return result;
-}
-
-/**
- * local_inc - increment local variable
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1.
- */
-#define local_inc(l) ((void)local_inc_return(l))
-
-/**
- * local_dec - decrement local variable
- * @l: pointer of type local_t
- *
- * Atomically decrements @l by 1.
- */
-#define local_dec(l) ((void)local_dec_return(l))
-
-/**
- * local_inc_and_test - increment and test
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define local_inc_and_test(l) (local_inc_return(l) == 0)
-
-/**
- * local_dec_and_test - decrement and test
- * @l: pointer of type local_t
- *
- * Atomically decrements @l by 1 and
- * returns true if the result is 0, or false for all
- * other cases.
- */
-#define local_dec_and_test(l) (local_dec_return(l) == 0)
-
-/**
- * local_add_negative - add and test if negative
- * @l: pointer of type local_t
- * @i: integer value to add
- *
- * Atomically adds @i to @l and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define local_add_negative(i, l) (local_add_return((i), (l)) < 0)
-
-#define local_cmpxchg(l, o, n) (cmpxchg_local(&((l)->counter), (o), (n)))
-#define local_xchg(v, new) (xchg_local(&((l)->counter), new))
-
-/**
- * local_add_unless - add unless the number is a given value
- * @l: pointer of type local_t
- * @a: the amount to add to l...
- * @u: ...unless l is equal to u.
- *
- * Atomically adds @a to @l, so long as it was not @u.
- * Returns non-zero if @l was not @u, and zero otherwise.
- */
-static inline int local_add_unless(local_t *l, long a, long u)
-{
- long c, old;
- c = local_read(l);
- for (;;) {
- if (unlikely(c == (u)))
- break;
- old = local_cmpxchg((l), c, c + (a));
- if (likely(old == c))
- break;
- c = old;
- }
- return c != (u);
-}
-
-#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
-
-static inline void local_clear_mask(unsigned long mask, local_t *addr)
-{
- unsigned long flags;
- unsigned long tmp;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_clear_mask \n\t"
- DCACHE_CLEAR("%0", "r5", "%1")
- "ld %0, @%1; \n\t"
- "and %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (addr), "r" (~mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r5"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-static inline void local_set_mask(unsigned long mask, local_t *addr)
-{
- unsigned long flags;
- unsigned long tmp;
-
- local_irq_save(flags);
- __asm__ __volatile__ (
- "# local_set_mask \n\t"
- DCACHE_CLEAR("%0", "r5", "%1")
- "ld %0, @%1; \n\t"
- "or %0, %2; \n\t"
- "st %0, @%1; \n\t"
- : "=&r" (tmp)
- : "r" (addr), "r" (mask)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r5"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
- local_irq_restore(flags);
-}
-
-/* Atomic operations are already serializing on m32r */
-#define smp_mb__before_local_dec() barrier()
-#define smp_mb__after_local_dec() barrier()
-#define smp_mb__before_local_inc() barrier()
-#define smp_mb__after_local_inc() barrier()
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations. Note they take
- * a variable, not an address.
- */
-
-#define __local_inc(l) ((l)->a.counter++)
-#define __local_dec(l) ((l)->a.counter++)
-#define __local_add(i, l) ((l)->a.counter += (i))
-#define __local_sub(i, l) ((l)->a.counter -= (i))
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations. Note they take
- * a variable, not an address.
- */
-
-#endif /* __M32R_LOCAL_H */
diff --git a/arch/m32r/include/asm/local64.h b/arch/m32r/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/m32r/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/m32r/include/asm/m32102.h b/arch/m32r/include/asm/m32102.h
deleted file mode 100644
index f0a986fece65..000000000000
--- a/arch/m32r/include/asm/m32102.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32102_H_
-#define _M32102_H_
-
-/*
- * Renesas M32R 32102 group
- *
- * Copyright (c) 2001 Hitoshi Yamamoto
- * Copyright (c) 2003, 2004 Renesas Technology Corp.
- */
-
-/*======================================================================*
- * Special Function Register
- *======================================================================*/
-#if !defined(CONFIG_CHIP_M32104)
-#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
-#else
-#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */
-#endif
-
-/*
- * Clock and Power Management registers.
- */
-#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
-
-#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
-#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
-#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
-
-/*
- * DMA Controller registers.
- */
-#define M32R_DMA_OFFSET (0x000F8000+M32R_SFR_OFFSET)
-
-#define M32R_DMAEN_PORTL (0x000+M32R_DMA_OFFSET)
-#define M32R_DMAISTS_PORTL (0x004+M32R_DMA_OFFSET)
-#define M32R_DMAEDET_PORTL (0x008+M32R_DMA_OFFSET)
-#define M32R_DMAASTS_PORTL (0x00c+M32R_DMA_OFFSET)
-
-#define M32R_DMA0CR0_PORTL (0x100+M32R_DMA_OFFSET)
-#define M32R_DMA0CR1_PORTL (0x104+M32R_DMA_OFFSET)
-#define M32R_DMA0CSA_PORTL (0x108+M32R_DMA_OFFSET)
-#define M32R_DMA0RSA_PORTL (0x10c+M32R_DMA_OFFSET)
-#define M32R_DMA0CDA_PORTL (0x110+M32R_DMA_OFFSET)
-#define M32R_DMA0RDA_PORTL (0x114+M32R_DMA_OFFSET)
-#define M32R_DMA0CBCUT_PORTL (0x118+M32R_DMA_OFFSET)
-#define M32R_DMA0RBCUT_PORTL (0x11c+M32R_DMA_OFFSET)
-
-#define M32R_DMA1CR0_PORTL (0x200+M32R_DMA_OFFSET)
-#define M32R_DMA1CR1_PORTL (0x204+M32R_DMA_OFFSET)
-#define M32R_DMA1CSA_PORTL (0x208+M32R_DMA_OFFSET)
-#define M32R_DMA1RSA_PORTL (0x20c+M32R_DMA_OFFSET)
-#define M32R_DMA1CDA_PORTL (0x210+M32R_DMA_OFFSET)
-#define M32R_DMA1RDA_PORTL (0x214+M32R_DMA_OFFSET)
-#define M32R_DMA1CBCUT_PORTL (0x218+M32R_DMA_OFFSET)
-#define M32R_DMA1RBCUT_PORTL (0x21c+M32R_DMA_OFFSET)
-
-/*
- * Multi Function Timer registers.
- */
-#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
-
-#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
-#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
-
-#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
-#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
-#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
-#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
-#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
-#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
-
-#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
-#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
-#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
-#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
-#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
-#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
-
-#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
-#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
-#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
-#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
-#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
-#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
-
-#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
-#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
-#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
-#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
-#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
-#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
-
-#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
-#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
-#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
-#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
-#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
-
-#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
-#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
-#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
-#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
-#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
-
-#if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
- || defined(CONFIG_CHIP_M32104)
-#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
-#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
-#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
-#define M32R_MFTCR_MFT3MSK (1UL<<28) /* b3 */
-#define M32R_MFTCR_MFT4MSK (1UL<<27) /* b4 */
-#define M32R_MFTCR_MFT5MSK (1UL<<26) /* b5 */
-#define M32R_MFTCR_MFT0EN (1UL<<23) /* b8 */
-#define M32R_MFTCR_MFT1EN (1UL<<22) /* b9 */
-#define M32R_MFTCR_MFT2EN (1UL<<21) /* b10 */
-#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
-#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
-#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
-#else
-#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
-#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
-#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
-#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
-#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
-#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
-#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
-#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
-#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
-#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
-#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
-#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
-#endif
-
-#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
-#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
-#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
-#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
-#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
-#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
-#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
-#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
-#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
-#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
-#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
-#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
-#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
-#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
-#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
-
-/*
- * Serial I/O registers.
- */
-#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
-
-#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
-#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
-#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
-#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
-#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
-#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
-#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
-
-/*
- * Interrupt Control Unit registers.
- */
-#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
-#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
-#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
-#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
-#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
-#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
-#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
-#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
-#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
-#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
-#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
-#define M32R_ICU_CR8_PORTL (0x219+M32R_ICU_OFFSET) /* INT7 */
-#define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */
-#define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */
-#define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */
-#define M32R_ICU_CR19_PORTL (0x248+M32R_ICU_OFFSET) /* MFT3 */
-#define M32R_ICU_CR20_PORTL (0x24C+M32R_ICU_OFFSET) /* MFT4 */
-#define M32R_ICU_CR21_PORTL (0x250+M32R_ICU_OFFSET) /* MFT5 */
-#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* DMA0 */
-#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* DMA1 */
-#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* SIO0 */
-#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* SIO0 */
-#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* SIO1 */
-#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* SIO1 */
-#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* SIO2 */
-#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* SIO2 */
-#define M32R_ICU_CR54_PORTL (0x2D4+M32R_ICU_OFFSET) /* SIO3 */
-#define M32R_ICU_CR55_PORTL (0x2D8+M32R_ICU_OFFSET) /* SIO3 */
-#define M32R_ICU_CR56_PORTL (0x2DC+M32R_ICU_OFFSET) /* SIO4 */
-#define M32R_ICU_CR57_PORTL (0x2E0+M32R_ICU_OFFSET) /* SIO4 */
-
-#ifdef CONFIG_SMP
-#define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET) /* IPI0 */
-#define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET) /* IPI1 */
-#define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET) /* IPI2 */
-#define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET) /* IPI3 */
-#define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET) /* IPI4 */
-#define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET) /* IPI5 */
-#define M32R_ICU_IPICR6_PORTL (0x2f4+M32R_ICU_OFFSET) /* IPI6 */
-#define M32R_ICU_IPICR7_PORTL (0x2f8+M32R_ICU_OFFSET) /* IPI7 */
-#endif /* CONFIG_SMP */
-
-#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
-#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
-#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
-#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
-#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
-#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
-#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
-#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
-
-#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
-#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
-#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
-#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
-#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
-#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
-#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
-#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
-#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
-#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
-#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
-#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
-#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
-#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
-
-#define M32R_IRQ_INT0 (1) /* INT0 */
-#define M32R_IRQ_INT1 (2) /* INT1 */
-#define M32R_IRQ_INT2 (3) /* INT2 */
-#define M32R_IRQ_INT3 (4) /* INT3 */
-#define M32R_IRQ_INT4 (5) /* INT4 */
-#define M32R_IRQ_INT5 (6) /* INT5 */
-#define M32R_IRQ_INT6 (7) /* INT6 */
-#define M32R_IRQ_MFT0 (16) /* MFT0 */
-#define M32R_IRQ_MFT1 (17) /* MFT1 */
-#define M32R_IRQ_MFT2 (18) /* MFT2 */
-#define M32R_IRQ_MFT3 (19) /* MFT3 */
-#ifdef CONFIG_CHIP_M32104
-#define M32R_IRQ_MFTX0 (24) /* MFTX0 */
-#define M32R_IRQ_MFTX1 (25) /* MFTX1 */
-#define M32R_IRQ_DMA0 (32) /* DMA0 */
-#define M32R_IRQ_DMA1 (33) /* DMA1 */
-#define M32R_IRQ_DMA2 (34) /* DMA2 */
-#define M32R_IRQ_DMA3 (35) /* DMA3 */
-#define M32R_IRQ_SIO0_R (40) /* SIO0 send */
-#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */
-#define M32R_IRQ_SIO1_R (42) /* SIO1 send */
-#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */
-#define M32R_IRQ_SIO2_R (44) /* SIO2 send */
-#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */
-#define M32R_IRQ_SIO3_R (46) /* SIO3 send */
-#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */
-#define M32R_IRQ_ADC (56) /* ADC */
-#define M32R_IRQ_PC (57) /* PC */
-#else /* ! M32104 */
-#define M32R_IRQ_DMA0 (32) /* DMA0 */
-#define M32R_IRQ_DMA1 (33) /* DMA1 */
-#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
-#define M32R_IRQ_SIO0_S (49) /* SIO0 receive */
-#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
-#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
-#define M32R_IRQ_SIO2_R (52) /* SIO2 send */
-#define M32R_IRQ_SIO2_S (53) /* SIO2 receive */
-#define M32R_IRQ_SIO3_R (54) /* SIO3 send */
-#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
-#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
-#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
-#endif /* ! M32104 */
-
-#ifdef CONFIG_SMP
-#define M32R_IRQ_IPI0 (56)
-#define M32R_IRQ_IPI1 (57)
-#define M32R_IRQ_IPI2 (58)
-#define M32R_IRQ_IPI3 (59)
-#define M32R_IRQ_IPI4 (60)
-#define M32R_IRQ_IPI5 (61)
-#define M32R_IRQ_IPI6 (62)
-#define M32R_IRQ_IPI7 (63)
-#define M32R_CPUID_PORTL (0xffffffe0)
-
-#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
-
-#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME3_PORTL (0x1c+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID3_PORTL (0x2c+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
-
-#endif /* CONFIG_SMP */
-
-#ifndef __ASSEMBLY__
-typedef struct {
- unsigned long icucr; /* ICU Control Register */
-} icu_data_t;
-#endif
-
-#endif /* _M32102_H_ */
diff --git a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h b/arch/m32r/include/asm/m32104ut/m32104ut_pld.h
deleted file mode 100644
index 1feae9709f24..000000000000
--- a/arch/m32r/include/asm/m32104ut/m32104ut_pld.h
+++ /dev/null
@@ -1,161 +0,0 @@
-#ifndef _M32104UT_M32104UT_PLD_H
-#define _M32104UT_M32104UT_PLD_H
-
-/*
- * include/asm-m32r/m32104ut/m32104ut_pld.h
- *
- * Definitions for Programmable Logic Device(PLD) on M32104UT board.
- * Based on m32700ut_pld.h
- *
- * Copyright (c) 2002 Takeo Takahashi
- * Copyright (c) 2005 Naoto Sugai
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#if defined(CONFIG_PLAT_M32104UT)
-#define PLD_PLAT_BASE 0x02c00000
-#else
-#error "no platform configuration"
-#endif
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- */
-
-#define PLD_IRQ_INT0 (M32104UT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_CFIREQ (M32104UT_PLD_IRQ_BASE + 3) /* CF IREQ */
-#define PLD_IRQ_CFC_INSERT (M32104UT_PLD_IRQ_BASE + 4) /* CF Insert */
-#define PLD_IRQ_CFC_EJECT (M32104UT_PLD_IRQ_BASE + 5) /* CF Eject */
-#define PLD_IRQ_EXINT (M32104UT_PLD_IRQ_BASE + 6) /* EXINT */
-#define PLD_IRQ_MMCCARD (M32104UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
-#define PLD_IRQ_SC_ERROR (M32104UT_PLD_IRQ_BASE + 13) /* SC error */
-#define PLD_IRQ_SC_RCV (M32104UT_PLD_IRQ_BASE + 14) /* SC receive */
-#define PLD_IRQ_SC_SND (M32104UT_PLD_IRQ_BASE + 15) /* SC send */
-
-#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
-#define PLD_ICUISTS_VECB_MASK (0xf000)
-#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
-#define PLD_ICUISTS_ISN_MASK (0x07c0)
-#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
-#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
-#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
-#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
-#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
-#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
-#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
-#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
-#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
-#define PLD_ICUCR_IEN (0x1000)
-#define PLD_ICUCR_IREQ (0x0100)
-#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
-#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
-#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
-#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
-#define PLD_ICUCR_ILEVEL0 (0x0000)
-#define PLD_ICUCR_ILEVEL1 (0x0001)
-#define PLD_ICUCR_ILEVEL2 (0x0002)
-#define PLD_ICUCR_ILEVEL3 (0x0003)
-#define PLD_ICUCR_ILEVEL4 (0x0004)
-#define PLD_ICUCR_ILEVEL5 (0x0005)
-#define PLD_ICUCR_ILEVEL6 (0x0006)
-#define PLD_ICUCR_ILEVEL7 (0x0007)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-#define PLD_CPCR_CDP 0x0001
-
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif /* _M32104UT_M32104UT_PLD_H */
diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_lan.h b/arch/m32r/include/asm/m32700ut/m32700ut_lan.h
deleted file mode 100644
index aae810a4fb2c..000000000000
--- a/arch/m32r/include/asm/m32700ut/m32700ut_lan.h
+++ /dev/null
@@ -1,103 +0,0 @@
-#ifndef _M32700UT_M32700UT_LAN_H
-#define _M32700UT_M32700UT_LAN_H
-
-/*
- * include/asm-m32r/m32700ut/m32700ut_lan.h
- *
- * M32700UT-LAN board
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define M32700UT_LAN_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define M32700UT_LAN_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#define M32700UT_LAN_IRQ_LAN (M32700UT_LAN_PLD_IRQ_BASE + 1) /* LAN */
-#define M32700UT_LAN_IRQ_I2C (M32700UT_LAN_PLD_IRQ_BASE + 3) /* I2C */
-
-#define M32700UT_LAN_ICUISTS __reg16(M32700UT_LAN_BASE + 0xc0002)
-#define M32700UT_LAN_ICUISTS_VECB_MASK (0xf000)
-#define M32700UT_LAN_VECB(x) ((x) & M32700UT_LAN_ICUISTS_VECB_MASK)
-#define M32700UT_LAN_ICUISTS_ISN_MASK (0x07c0)
-#define M32700UT_LAN_ICUISTS_ISN(x) ((x) & M32700UT_LAN_ICUISTS_ISN_MASK)
-#define M32700UT_LAN_ICUIREQ0 __reg16(M32700UT_LAN_BASE + 0xc0004)
-#define M32700UT_LAN_ICUCR1 __reg16(M32700UT_LAN_BASE + 0xc0010)
-#define M32700UT_LAN_ICUCR3 __reg16(M32700UT_LAN_BASE + 0xc0014)
-
-/*
- * AR register on PLD
- */
-#define ARVCR0 __reg32(M32700UT_LAN_BASE + 0x40000)
-#define ARVCR0_VDS 0x00080000
-#define ARVCR0_RST 0x00010000
-#define ARVCR1 __reg32(M32700UT_LAN_BASE + 0x40004)
-#define ARVCR1_QVGA 0x02000000
-#define ARVCR1_NORMAL 0x01000000
-#define ARVCR1_HIEN 0x00010000
-#define ARVHCOUNT __reg32(M32700UT_LAN_BASE + 0x40008)
-#define ARDATA __reg32(M32700UT_LAN_BASE + 0x40010)
-#define ARINTSEL __reg32(M32700UT_LAN_BASE + 0x40014)
-#define ARINTSEL_INT3 0x10000000 /* CPU INT3 */
-#define ARDATA32 __reg32(M32700UT_LAN_BASE + 0x04040010) // Block 5
-/*
-#define ARINTSEL_SEL2 0x00002000
-#define ARINTSEL_SEL3 0x00001000
-#define ARINTSEL_SEL6 0x00000200
-#define ARINTSEL_SEL7 0x00000100
-#define ARINTSEL_SEL9 0x00000040
-#define ARINTSEL_SEL10 0x00000020
-#define ARINTSEL_SEL11 0x00000010
-#define ARINTSEL_SEL12 0x00000008
-*/
-
-/*
- * I2C register on PLD
- */
-#define PLDI2CCR __reg32(M32700UT_LAN_BASE + 0x40040)
-#define PLDI2CCR_ES0 0x00000001 /* enable I2C interface */
-#define PLDI2CMOD __reg32(M32700UT_LAN_BASE + 0x40044)
-#define PLDI2CMOD_ACKCLK 0x00000200
-#define PLDI2CMOD_DTWD 0x00000100
-#define PLDI2CMOD_10BT 0x00000004
-#define PLDI2CMOD_ATM_NORMAL 0x00000000
-#define PLDI2CMOD_ATM_AUTO 0x00000003
-#define PLDI2CACK __reg32(M32700UT_LAN_BASE + 0x40048)
-#define PLDI2CACK_ACK 0x00000001
-#define PLDI2CFREQ __reg32(M32700UT_LAN_BASE + 0x4004c)
-#define PLDI2CCND __reg32(M32700UT_LAN_BASE + 0x40050)
-#define PLDI2CCND_START 0x00000001
-#define PLDI2CCND_STOP 0x00000002
-#define PLDI2CSTEN __reg32(M32700UT_LAN_BASE + 0x40054)
-#define PLDI2CSTEN_STEN 0x00000001
-#define PLDI2CDATA __reg32(M32700UT_LAN_BASE + 0x40060)
-#define PLDI2CSTS __reg32(M32700UT_LAN_BASE + 0x40064)
-#define PLDI2CSTS_TRX 0x00000020
-#define PLDI2CSTS_BB 0x00000010
-#define PLDI2CSTS_NOACK 0x00000001 /* 0:ack, 1:noack */
-
-#endif /* _M32700UT_M32700UT_LAN_H */
diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_lcd.h b/arch/m32r/include/asm/m32700ut/m32700ut_lcd.h
deleted file mode 100644
index 4c2489079788..000000000000
--- a/arch/m32r/include/asm/m32700ut/m32700ut_lcd.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _M32700UT_M32700UT_LCD_H
-#define _M32700UT_M32700UT_LCD_H
-
-/*
- * include/asm-m32r/m32700ut/m32700ut_lcd.h
- *
- * M32700UT-LCD board
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define M32700UT_LCD_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define M32700UT_LCD_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/*
- * ICU
- */
-#define M32700UT_LCD_IRQ_BAT_INT (M32700UT_LCD_PLD_IRQ_BASE + 1)
-#define M32700UT_LCD_IRQ_USB_INT1 (M32700UT_LCD_PLD_IRQ_BASE + 2)
-#define M32700UT_LCD_IRQ_AUDT0 (M32700UT_LCD_PLD_IRQ_BASE + 3)
-#define M32700UT_LCD_IRQ_AUDT2 (M32700UT_LCD_PLD_IRQ_BASE + 4)
-#define M32700UT_LCD_IRQ_BATSIO_RCV (M32700UT_LCD_PLD_IRQ_BASE + 16)
-#define M32700UT_LCD_IRQ_BATSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 17)
-#define M32700UT_LCD_IRQ_ASNDSIO_RCV (M32700UT_LCD_PLD_IRQ_BASE + 18)
-#define M32700UT_LCD_IRQ_ASNDSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 19)
-#define M32700UT_LCD_IRQ_ACNLSIO_SND (M32700UT_LCD_PLD_IRQ_BASE + 21)
-
-#define M32700UT_LCD_ICUISTS __reg16(M32700UT_LCD_BASE + 0x300002)
-#define M32700UT_LCD_ICUISTS_VECB_MASK (0xf000)
-#define M32700UT_LCD_VECB(x) ((x) & M32700UT_LCD_ICUISTS_VECB_MASK)
-#define M32700UT_LCD_ICUISTS_ISN_MASK (0x07c0)
-#define M32700UT_LCD_ICUISTS_ISN(x) ((x) & M32700UT_LCD_ICUISTS_ISN_MASK)
-#define M32700UT_LCD_ICUIREQ0 __reg16(M32700UT_LCD_BASE + 0x300004)
-#define M32700UT_LCD_ICUIREQ1 __reg16(M32700UT_LCD_BASE + 0x300006)
-#define M32700UT_LCD_ICUCR1 __reg16(M32700UT_LCD_BASE + 0x300020)
-#define M32700UT_LCD_ICUCR2 __reg16(M32700UT_LCD_BASE + 0x300022)
-#define M32700UT_LCD_ICUCR3 __reg16(M32700UT_LCD_BASE + 0x300024)
-#define M32700UT_LCD_ICUCR4 __reg16(M32700UT_LCD_BASE + 0x300026)
-#define M32700UT_LCD_ICUCR16 __reg16(M32700UT_LCD_BASE + 0x300030)
-#define M32700UT_LCD_ICUCR17 __reg16(M32700UT_LCD_BASE + 0x300032)
-#define M32700UT_LCD_ICUCR18 __reg16(M32700UT_LCD_BASE + 0x300034)
-#define M32700UT_LCD_ICUCR19 __reg16(M32700UT_LCD_BASE + 0x300036)
-#define M32700UT_LCD_ICUCR21 __reg16(M32700UT_LCD_BASE + 0x30003a)
-
-#endif /* _M32700UT_M32700UT_LCD_H */
diff --git a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h b/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
deleted file mode 100644
index 35294670b187..000000000000
--- a/arch/m32r/include/asm/m32700ut/m32700ut_pld.h
+++ /dev/null
@@ -1,259 +0,0 @@
-#ifndef _M32700UT_M32700UT_PLD_H
-#define _M32700UT_M32700UT_PLD_H
-
-/*
- * include/asm-m32r/m32700ut/m32700ut_pld.h
- *
- * Definitions for Programmable Logic Device(PLD) on M32700UT board.
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV)
-#define PLD_PLAT_BASE 0x04c00000
-#else
-#error "no platform configuration"
-#endif
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-#define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#if !defined(CONFIG_PLAT_USRV)
-#define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CFIREQ (M32700UT_PLD_IRQ_BASE + 3) /* CF IREQ */
-#define PLD_IRQ_CFC_INSERT (M32700UT_PLD_IRQ_BASE + 4) /* CF Insert */
-#define PLD_IRQ_CFC_EJECT (M32700UT_PLD_IRQ_BASE + 5) /* CF Eject */
-#define PLD_IRQ_EXINT (M32700UT_PLD_IRQ_BASE + 6) /* EXINT */
-#define PLD_IRQ_INT7 (M32700UT_PLD_IRQ_BASE + 7) /* reserved */
-#define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_MMCCARD (M32700UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
-#define PLD_IRQ_INT12 (M32700UT_PLD_IRQ_BASE + 12) /* reserved */
-#define PLD_IRQ_SC_ERROR (M32700UT_PLD_IRQ_BASE + 13) /* SC error */
-#define PLD_IRQ_SC_RCV (M32700UT_PLD_IRQ_BASE + 14) /* SC receive */
-#define PLD_IRQ_SC_SND (M32700UT_PLD_IRQ_BASE + 15) /* SC send */
-#define PLD_IRQ_SIO0_RCV (M32700UT_PLD_IRQ_BASE + 16) /* SIO receive */
-#define PLD_IRQ_SIO0_SND (M32700UT_PLD_IRQ_BASE + 17) /* SIO send */
-#define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
-#define PLD_IRQ_INT31 (M32700UT_PLD_IRQ_BASE + 31) /* reserved */
-
-#else /* CONFIG_PLAT_USRV */
-
-#define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CF0 (M32700UT_PLD_IRQ_BASE + 3) /* CF0# */
-#define PLD_IRQ_CF1 (M32700UT_PLD_IRQ_BASE + 4) /* CF1# */
-#define PLD_IRQ_CF2 (M32700UT_PLD_IRQ_BASE + 5) /* CF2# */
-#define PLD_IRQ_CF3 (M32700UT_PLD_IRQ_BASE + 6) /* CF3# */
-#define PLD_IRQ_CF4 (M32700UT_PLD_IRQ_BASE + 7) /* CF4# */
-#define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_INT11 (M32700UT_PLD_IRQ_BASE + 11) /* reserved */
-#define PLD_IRQ_UART0 (M32700UT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */
-#define PLD_IRQ_UART1 (M32700UT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */
-#define PLD_IRQ_INT14 (M32700UT_PLD_IRQ_BASE + 14) /* reserved */
-#define PLD_IRQ_INT15 (M32700UT_PLD_IRQ_BASE + 15) /* reserved */
-#define PLD_IRQ_SNDINT (M32700UT_PLD_IRQ_BASE + 16) /* SNDINT# */
-#define PLD_IRQ_INT17 (M32700UT_PLD_IRQ_BASE + 17) /* reserved */
-#define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
-
-#endif /* CONFIG_PLAT_USRV */
-
-#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
-#define PLD_ICUISTS_VECB_MASK (0xf000)
-#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
-#define PLD_ICUISTS_ISN_MASK (0x07c0)
-#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
-#define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
-#define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
-#define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
-#define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
-#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
-#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
-#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
-#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
-#define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
-#define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
-#define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
-#define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
-#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
-#define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
-#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
-#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
-#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
-#define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
-#define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
-#define PLD_ICUCR_IEN (0x1000)
-#define PLD_ICUCR_IREQ (0x0100)
-#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
-#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
-#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
-#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
-#define PLD_ICUCR_ILEVEL0 (0x0000)
-#define PLD_ICUCR_ILEVEL1 (0x0001)
-#define PLD_ICUCR_ILEVEL2 (0x0002)
-#define PLD_ICUCR_ILEVEL3 (0x0003)
-#define PLD_ICUCR_ILEVEL4 (0x0004)
-#define PLD_ICUCR_ILEVEL5 (0x0005)
-#define PLD_ICUCR_ILEVEL6 (0x0006)
-#define PLD_ICUCR_ILEVEL7 (0x0007)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-#define PLD_CPCR_CF 0x0001
-#define PLD_CPCR_MMC 0x0002
-
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif /* _M32700UT_M32700UT_PLD.H */
diff --git a/arch/m32r/include/asm/m32r.h b/arch/m32r/include/asm/m32r.h
deleted file mode 100644
index d27f056d92f3..000000000000
--- a/arch/m32r/include/asm/m32r.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_M32R_H_
-#define _ASM_M32R_M32R_H_
-
-/*
- * Renesas M32R processor
- *
- * Copyright (C) 2003, 2004 Renesas Technology Corp.
- */
-
-
-/* Chip type */
-#if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP)
-#include <asm/m32r_mp_fpga.h>
-#elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
- || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
- || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-#include <asm/m32102.h>
-#endif
-
-/* Platform type */
-#if defined(CONFIG_PLAT_M32700UT)
-#include <asm/m32700ut/m32700ut_pld.h>
-#include <asm/m32700ut/m32700ut_lan.h>
-#include <asm/m32700ut/m32700ut_lcd.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
-#define M32R_INT0ICU_ISTS M32700UT_LAN_ICUISTS
-#define M32R_INT0ICU_IRQ_BASE M32700UT_LAN_PLD_IRQ_BASE
-#define M32R_INT2ICU_ISTS M32700UT_LCD_ICUISTS
-#define M32R_INT2ICU_IRQ_BASE M32700UT_LCD_PLD_IRQ_BASE
-#endif /* CONFIG_PLAT_M32700UT */
-
-#if defined(CONFIG_PLAT_OPSPUT)
-#include <asm/opsput/opsput_pld.h>
-#include <asm/opsput/opsput_lan.h>
-#include <asm/opsput/opsput_lcd.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE OPSPUT_PLD_IRQ_BASE
-#define M32R_INT0ICU_ISTS OPSPUT_LAN_ICUISTS
-#define M32R_INT0ICU_IRQ_BASE OPSPUT_LAN_PLD_IRQ_BASE
-#define M32R_INT2ICU_ISTS OPSPUT_LCD_ICUISTS
-#define M32R_INT2ICU_IRQ_BASE OPSPUT_LCD_PLD_IRQ_BASE
-#endif /* CONFIG_PLAT_OPSPUT */
-
-#if defined(CONFIG_PLAT_MAPPI2)
-#include <asm/mappi2/mappi2_pld.h>
-#endif /* CONFIG_PLAT_MAPPI2 */
-
-#if defined(CONFIG_PLAT_MAPPI3)
-#include <asm/mappi3/mappi3_pld.h>
-#endif /* CONFIG_PLAT_MAPPI3 */
-
-#if defined(CONFIG_PLAT_USRV)
-#include <asm/m32700ut/m32700ut_pld.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE
-#endif
-
-#if defined(CONFIG_PLAT_M32104UT)
-#include <asm/m32104ut/m32104ut_pld.h>
-/* for ei_handler:linux/arch/m32r/kernel/entry.S */
-#define M32R_INT1ICU_ISTS PLD_ICUISTS
-#define M32R_INT1ICU_IRQ_BASE M32104UT_PLD_IRQ_BASE
-#endif /* CONFIG_PLAT_M32104 */
-
-/*
- * M32R Register
- */
-
-/*
- * MMU Register
- */
-
-#define MMU_REG_BASE (0xffff0000)
-#define ITLB_BASE (0xfe000000)
-#define DTLB_BASE (0xfe000800)
-
-#define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES
-
-#define MATM MMU_REG_BASE /* MMU Address Translation Mode
- Register */
-#define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
-#define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
-#define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
-#define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
- Address Register */
-#define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
- Number Register */
-#define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
-#define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
- Register */
-#define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
-#define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
- Instruciton */
-#define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
-
-#define MATM_offset (MATM - MMU_REG_BASE)
-#define MPSZ_offset (MPSZ - MMU_REG_BASE)
-#define MASID_offset (MASID - MMU_REG_BASE)
-#define MESTS_offset (MESTS - MMU_REG_BASE)
-#define MDEVA_offset (MDEVA - MMU_REG_BASE)
-#define MDEVP_offset (MDEVP - MMU_REG_BASE)
-#define MPTB_offset (MPTB - MMU_REG_BASE)
-#define MSVA_offset (MSVA - MMU_REG_BASE)
-#define MTOP_offset (MTOP - MMU_REG_BASE)
-#define MIDXI_offset (MIDXI - MMU_REG_BASE)
-#define MIDXD_offset (MIDXD - MMU_REG_BASE)
-
-#define MESTS_IT (1 << 0) /* Instruction TLB miss */
-#define MESTS_IA (1 << 1) /* Instruction Access Exception */
-#define MESTS_DT (1 << 4) /* Operand TLB miss */
-#define MESTS_DA (1 << 5) /* Operand Access Exception */
-#define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */
-
-/*
- * PSW (Processor Status Word)
- */
-
-/* PSW bit */
-#define M32R_PSW_BIT_SM (7) /* Stack Mode */
-#define M32R_PSW_BIT_IE (6) /* Interrupt Enable */
-#define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */
-#define M32R_PSW_BIT_C (0) /* Condition */
-#define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */
-#define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */
-#define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */
-#define M32R_PSW_BIT_BC (0+8) /* Backup Condition */
-
-/* PSW bit map */
-#define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */
-#define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */
-#define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */
-#define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */
-#define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */
-#define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */
-#define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */
-#define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */
-
-/*
- * Direct address to SFR
- */
-
-#include <asm/page.h>
-#ifdef CONFIG_MMU
-#define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000)
-#else
-#define NONCACHE_OFFSET __PAGE_OFFSET
-#endif /* CONFIG_MMU */
-
-#define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET
-#define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET
-#define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET
-#define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET
-
-#endif /* _ASM_M32R_M32R_H_ */
diff --git a/arch/m32r/include/asm/m32r_mp_fpga.h b/arch/m32r/include/asm/m32r_mp_fpga.h
deleted file mode 100644
index 8eeaa9a420c5..000000000000
--- a/arch/m32r/include/asm/m32r_mp_fpga.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_M32R_MP_FPGA_
-#define _ASM_M32R_M32R_MP_FPGA_
-
-/*
- * Renesas M32R-MP-FPGA
- *
- * Copyright (c) 2002 Hitoshi Yamamoto
- * Copyright (c) 2003, 2004 Renesas Technology Corp.
- */
-
-/*
- * ========================================================
- * M32R-MP-FPGA Memory Map
- * ========================================================
- * 0x00000000 : Block#0 : 64[MB]
- * 0x03E00000 : SFR
- * 0x03E00000 : reserved
- * 0x03EF0000 : FPGA
- * 0x03EF1000 : reserved
- * 0x03EF4000 : CKM
- * 0x03EF4000 : BSELC
- * 0x03EF5000 : reserved
- * 0x03EFC000 : MFT
- * 0x03EFD000 : SIO
- * 0x03EFE000 : reserved
- * 0x03EFF000 : ICU
- * 0x03F00000 : Internal SRAM 64[KB]
- * 0x03F10000 : reserved
- * --------------------------------------------------------
- * 0x04000000 : Block#1 : 64[MB]
- * 0x04000000 : Debug board SRAM 4[MB]
- * 0x04400000 : reserved
- * --------------------------------------------------------
- * 0x08000000 : Block#2 : 64[MB]
- * --------------------------------------------------------
- * 0x0C000000 : Block#3 : 64[MB]
- * --------------------------------------------------------
- * 0x10000000 : Block#4 : 64[MB]
- * --------------------------------------------------------
- * 0x14000000 : Block#5 : 64[MB]
- * --------------------------------------------------------
- * 0x18000000 : Block#6 : 64[MB]
- * --------------------------------------------------------
- * 0x1C000000 : Block#7 : 64[MB]
- * --------------------------------------------------------
- * 0xFE000000 : TLB
- * 0xFE000000 : ITLB
- * 0xFE000080 : reserved
- * 0xFE000800 : DTLB
- * 0xFE000880 : reserved
- * --------------------------------------------------------
- * 0xFF000000 : System area
- * 0xFFFF0000 : MMU
- * 0xFFFF0030 : reserved
- * 0xFFFF8000 : Debug function
- * 0xFFFFA000 : reserved
- * 0xFFFFC000 : CPU control
- * 0xFFFFFFFF
- * ========================================================
- */
-
-/*======================================================================*
- * Special Function Register
- *======================================================================*/
-#define M32R_SFR_OFFSET (0x00E00000) /* 0x03E00000-0x03EFFFFF 1[MB] */
-
-/*
- * FPGA registers.
- */
-#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
-
-#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
-#define M32R_FPGA_CPU_NAME3_PORTL (0x1C+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
-#define M32R_FPGA_MODEL_ID3_PORTL (0x2C+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
-#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
-
-/*
- * Clock and Power Manager registers.
- */
-#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
-
-#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
-#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
-#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
-
-/*
- * Block SELect Controller registers.
- */
-#define M32R_BSELC_OFFSET (0x000F5000+M32R_SFR_OFFSET)
-
-#define M32R_BSEL0_CR0_PORTL (0x000+M32R_BSELC_OFFSET)
-#define M32R_BSEL0_CR1_PORTL (0x004+M32R_BSELC_OFFSET)
-#define M32R_BSEL1_CR0_PORTL (0x100+M32R_BSELC_OFFSET)
-#define M32R_BSEL1_CR1_PORTL (0x104+M32R_BSELC_OFFSET)
-#define M32R_BSEL2_CR0_PORTL (0x200+M32R_BSELC_OFFSET)
-#define M32R_BSEL2_CR1_PORTL (0x204+M32R_BSELC_OFFSET)
-#define M32R_BSEL3_CR0_PORTL (0x300+M32R_BSELC_OFFSET)
-#define M32R_BSEL3_CR1_PORTL (0x304+M32R_BSELC_OFFSET)
-#define M32R_BSEL4_CR0_PORTL (0x400+M32R_BSELC_OFFSET)
-#define M32R_BSEL4_CR1_PORTL (0x404+M32R_BSELC_OFFSET)
-#define M32R_BSEL5_CR0_PORTL (0x500+M32R_BSELC_OFFSET)
-#define M32R_BSEL5_CR1_PORTL (0x504+M32R_BSELC_OFFSET)
-#define M32R_BSEL6_CR0_PORTL (0x600+M32R_BSELC_OFFSET)
-#define M32R_BSEL6_CR1_PORTL (0x604+M32R_BSELC_OFFSET)
-#define M32R_BSEL7_CR0_PORTL (0x700+M32R_BSELC_OFFSET)
-#define M32R_BSEL7_CR1_PORTL (0x704+M32R_BSELC_OFFSET)
-
-/*
- * Multi Function Timer registers.
- */
-#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
-
-#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
-#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
-
-#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
-#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
-#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
-#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
-#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
-#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
-
-#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
-#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
-#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
-#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
-#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
-#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
-
-#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
-#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
-#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
-#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
-#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
-#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
-
-#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
-#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
-#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
-#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
-#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
-#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
-
-#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
-#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
-#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
-#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
-#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
-
-#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
-#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
-#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
-#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
-#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
-#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
-
-#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
-#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
-#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
-#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
-#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
-#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
-#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
-#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
-#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
-#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
-#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
-#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
-
-#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
-#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
-#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
-#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
-#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
-#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
-#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
-#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
-#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
-#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
-#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
-#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
-#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
-#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
-#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
-
-/*
- * Serial I/O registers.
- */
-#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
-
-#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
-#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
-#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
-#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
-#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
-#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
-#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
-#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
-
-/*
- * Interrupt Control Unit registers.
- */
-#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
-
-#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
-#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
-#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
-#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
-#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
-#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
-#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
-#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
-#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
-#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
-#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
-#define M32R_ICU_CR8_PORTL (0x218+M32R_ICU_OFFSET) /* INT7 */
-#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* SIO0 RX */
-#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* SIO0 TX */
-#define M32R_ICU_CR40_PORTL (0x29C+M32R_ICU_OFFSET) /* DMAC0 */
-#define M32R_ICU_CR41_PORTL (0x2A0+M32R_ICU_OFFSET) /* DMAC1 */
-#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* MFT0 */
-#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* MFT1 */
-#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* MFT2 */
-#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* MFT3 */
-#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* MFT4 */
-#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* MFT5 */
-#define M32R_ICU_IPICR0_PORTL (0x2DC+M32R_ICU_OFFSET) /* IPI0 */
-#define M32R_ICU_IPICR1_PORTL (0x2E0+M32R_ICU_OFFSET) /* IPI1 */
-#define M32R_ICU_IPICR2_PORTL (0x2E4+M32R_ICU_OFFSET) /* IPI2 */
-#define M32R_ICU_IPICR3_PORTL (0x2E8+M32R_ICU_OFFSET) /* IPI3 */
-#define M32R_ICU_IPICR4_PORTL (0x2EC+M32R_ICU_OFFSET) /* IPI4 */
-#define M32R_ICU_IPICR5_PORTL (0x2F0+M32R_ICU_OFFSET) /* IPI5 */
-#define M32R_ICU_IPICR6_PORTL (0x2F4+M32R_ICU_OFFSET) /* IPI6 */
-#define M32R_ICU_IPICR7_PORTL (0x2FC+M32R_ICU_OFFSET) /* IPI7 */
-
-#define M32R_ICUISTS_VECB(val) ((val>>28) & 0xF)
-#define M32R_ICUISTS_ISN(val) ((val>>22) & 0x3F)
-#define M32R_ICUISTS_PIML(val) ((val>>16) & 0x7)
-
-#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
-#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
-#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
-#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
-#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
-#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
-#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
-#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
-
-#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
-#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
-#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
-#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
-#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
-#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
-#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
-#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
-#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
-#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
-#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
-#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
-#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
-#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
-#define M32R_ICUCR_ILEVEL_MASK (7UL)
-
-#define M32R_IRQ_INT0 (1) /* INT0 */
-#define M32R_IRQ_INT1 (2) /* INT1 */
-#define M32R_IRQ_INT2 (3) /* INT2 */
-#define M32R_IRQ_INT3 (4) /* INT3 */
-#define M32R_IRQ_INT4 (5) /* INT4 */
-#define M32R_IRQ_INT5 (6) /* INT5 */
-#define M32R_IRQ_INT6 (7) /* INT6 */
-#define M32R_IRQ_INT7 (8) /* INT7 */
-#define M32R_IRQ_MFT0 (16) /* MFT0 */
-#define M32R_IRQ_MFT1 (17) /* MFT1 */
-#define M32R_IRQ_MFT2 (18) /* MFT2 */
-#define M32R_IRQ_MFT3 (19) /* MFT3 */
-#define M32R_IRQ_MFT4 (20) /* MFT4 */
-#define M32R_IRQ_MFT5 (21) /* MFT5 */
-#define M32R_IRQ_DMAC0 (32) /* DMAC0 */
-#define M32R_IRQ_DMAC1 (33) /* DMAC1 */
-#define M32R_IRQ_SIO0_R (48) /* SIO0 receive */
-#define M32R_IRQ_SIO0_S (49) /* SIO0 send */
-#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
-#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
-#define M32R_IRQ_IPI0 (56) /* IPI0 */
-#define M32R_IRQ_IPI1 (57) /* IPI1 */
-#define M32R_IRQ_IPI2 (58) /* IPI2 */
-#define M32R_IRQ_IPI3 (59) /* IPI3 */
-#define M32R_IRQ_IPI4 (60) /* IPI4 */
-#define M32R_IRQ_IPI5 (61) /* IPI5 */
-#define M32R_IRQ_IPI6 (62) /* IPI6 */
-#define M32R_IRQ_IPI7 (63) /* IPI7 */
-
-/*======================================================================*
- * CPU
- *======================================================================*/
-
-#define M32R_CPUID_PORTL (0xFFFFFFE0)
-#define M32R_MCICAR_PORTL (0xFFFFFFF0)
-#define M32R_MCDCAR_PORTL (0xFFFFFFF4)
-#define M32R_MCCR_PORTL (0xFFFFFFFC)
-
-#endif /* _ASM_M32R_M32R_MP_FPGA_ */
diff --git a/arch/m32r/include/asm/mappi2/mappi2_pld.h b/arch/m32r/include/asm/mappi2/mappi2_pld.h
deleted file mode 100644
index 2624c9db7255..000000000000
--- a/arch/m32r/include/asm/mappi2/mappi2_pld.h
+++ /dev/null
@@ -1,150 +0,0 @@
-#ifndef _MAPPI2_PLD_H
-#define _MAPPI2_PLD_H
-
-/*
- * include/asm-m32r/mappi2/mappi2_pld.h
- *
- * Definitions for Extended IO Logic on MAPPI2 board.
- * based on m32700ut_pld.h
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/* FIXME:
- * Some C functions use non-cache address, so can't define non-cache address.
- */
-#define PLD_BASE (0x10c00000 /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (0x10c00000 + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-
-
-/*==== ICU ====*/
-#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
-#define M32R_IRQ_I2C (28) /* I2C-BUS */
-#if 1
-#define PLD_IRQ_CFIREQ (40) /* CFC Card Interrupt */
-#define PLD_IRQ_CFC_INSERT (41) /* CFC Card Insert */
-#define PLD_IRQ_CFC_EJECT (42) /* CFC Card Eject */
-#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
-#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
-#else
-#define PLD_IRQ_CFIREQ (34) /* CFC Card Interrupt */
-#define PLD_IRQ_CFC_INSERT (35) /* CFC Card Insert */
-#define PLD_IRQ_CFC_EJECT (36) /* CFC Card Eject */
-#define PLD_IRQ_MMCCARD (37) /* MMC Card Insert */
-#define PLD_IRQ_MMCIRQ (38) /* MMC Transfer Done */
-#endif
-
-
-#if 0
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-#endif
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-
-#if 0
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif
-
-#endif /* _MAPPI2_PLD.H */
diff --git a/arch/m32r/include/asm/mappi3/mappi3_pld.h b/arch/m32r/include/asm/mappi3/mappi3_pld.h
deleted file mode 100644
index 451c40ee70af..000000000000
--- a/arch/m32r/include/asm/mappi3/mappi3_pld.h
+++ /dev/null
@@ -1,142 +0,0 @@
-#ifndef _MAPPI3_PLD_H
-#define _MAPPI3_PLD_H
-
-/*
- * include/asm-m32r/mappi3/mappi3_pld.h
- *
- * Definitions for Extended IO Logic on MAPPI3 board.
- * based on m32700ut_pld.h
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/* FIXME:
- * Some C functions use non-cache address, so can't define non-cache address.
- */
-#define PLD_BASE (0x1c000000 /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (0x1c000000 + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-
-/* ICU */
-#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
-#define M32R_IRQ_I2C (28) /* I2C-BUS */
-#define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */
-#define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert & Eject */
-#define PLD_IRQ_IDEIREQ (8) /* INT7 IDE Interrupt */
-#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
-#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
-
-#if 0
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-#endif
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-#if 0
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif
-
-/* Reset Control */
-#define PLD_REBOOT __reg16(PLD_BASE + 0x38000)
-
-#endif /* _MAPPI3_PLD.H */
diff --git a/arch/m32r/include/asm/mc146818rtc.h b/arch/m32r/include/asm/mc146818rtc.h
deleted file mode 100644
index 4effa4704347..000000000000
--- a/arch/m32r/include/asm/mc146818rtc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef _ASM_MC146818RTC_H
-#define _ASM_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x) ((x))
-#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#define RTC_IRQ 8
-
-#endif /* _ASM_MC146818RTC_H */
diff --git a/arch/m32r/include/asm/mmu.h b/arch/m32r/include/asm/mmu.h
deleted file mode 100644
index 34bcccd8007d..000000000000
--- a/arch/m32r/include/asm/mmu.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_MMU_H
-#define _ASM_M32R_MMU_H
-
-#if !defined(CONFIG_MMU)
-
-typedef struct {
- unsigned long end_brk;
-} mm_context_t;
-
-#else /* CONFIG_MMU */
-
-/* Default "unsigned long" context */
-#ifndef CONFIG_SMP
-typedef unsigned long mm_context_t;
-#else
-typedef unsigned long mm_context_t[NR_CPUS];
-#endif
-
-#endif /* CONFIG_MMU */
-
-#endif /* _ASM_M32R_MMU_H */
diff --git a/arch/m32r/include/asm/mmu_context.h b/arch/m32r/include/asm/mmu_context.h
deleted file mode 100644
index 8a499d0fb3a2..000000000000
--- a/arch/m32r/include/asm/mmu_context.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_MMU_CONTEXT_H
-#define _ASM_M32R_MMU_CONTEXT_H
-#ifdef __KERNEL__
-
-#include <asm/m32r.h>
-
-#define MMU_CONTEXT_ASID_MASK (0x000000FF)
-#define MMU_CONTEXT_VERSION_MASK (0xFFFFFF00)
-#define MMU_CONTEXT_FIRST_VERSION (0x00000100)
-#define NO_CONTEXT (0x00000000)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/atomic.h>
-#include <linux/mm_types.h>
-
-#include <asm/pgalloc.h>
-#include <asm/mmu.h>
-#include <asm/tlbflush.h>
-#include <asm-generic/mm_hooks.h>
-
-/*
- * Cache of MMU context last used.
- */
-#ifndef CONFIG_SMP
-extern unsigned long mmu_context_cache_dat;
-#define mmu_context_cache mmu_context_cache_dat
-#define mm_context(mm) mm->context
-#else /* not CONFIG_SMP */
-extern unsigned long mmu_context_cache_dat[];
-#define mmu_context_cache mmu_context_cache_dat[smp_processor_id()]
-#define mm_context(mm) mm->context[smp_processor_id()]
-#endif /* not CONFIG_SMP */
-
-#define set_tlb_tag(entry, tag) (*entry = (tag & PAGE_MASK)|get_asid())
-#define set_tlb_data(entry, data) (*entry = (data | _PAGE_PRESENT))
-
-#ifdef CONFIG_MMU
-#define enter_lazy_tlb(mm, tsk) do { } while (0)
-
-static inline void get_new_mmu_context(struct mm_struct *mm)
-{
- unsigned long mc = ++mmu_context_cache;
-
- if (!(mc & MMU_CONTEXT_ASID_MASK)) {
- /* We exhaust ASID of this version.
- Flush all TLB and start new cycle. */
- local_flush_tlb_all();
- /* Fix version if needed.
- Note that we avoid version #0 to distinguish NO_CONTEXT. */
- if (!mc)
- mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
- }
- mm_context(mm) = mc;
-}
-
-/*
- * Get MMU context if needed.
- */
-static inline void get_mmu_context(struct mm_struct *mm)
-{
- if (mm) {
- unsigned long mc = mmu_context_cache;
-
- /* Check if we have old version of context.
- If it's old, we need to get new context with new version. */
- if ((mm_context(mm) ^ mc) & MMU_CONTEXT_VERSION_MASK)
- get_new_mmu_context(mm);
- }
-}
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-static inline int init_new_context(struct task_struct *tsk,
- struct mm_struct *mm)
-{
-#ifndef CONFIG_SMP
- mm->context = NO_CONTEXT;
-#else /* CONFIG_SMP */
- int num_cpus = num_online_cpus();
- int i;
-
- for (i = 0 ; i < num_cpus ; i++)
- mm->context[i] = NO_CONTEXT;
-#endif /* CONFIG_SMP */
-
- return 0;
-}
-
-/*
- * Destroy context related info for an mm_struct that is about
- * to be put to rest.
- */
-#define destroy_context(mm) do { } while (0)
-
-static inline void set_asid(unsigned long asid)
-{
- *(volatile unsigned long *)MASID = (asid & MMU_CONTEXT_ASID_MASK);
-}
-
-static inline unsigned long get_asid(void)
-{
- unsigned long asid;
-
- asid = *(volatile long *)MASID;
- asid &= MMU_CONTEXT_ASID_MASK;
-
- return asid;
-}
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-static inline void activate_context(struct mm_struct *mm)
-{
- get_mmu_context(mm);
- set_asid(mm_context(mm) & MMU_CONTEXT_ASID_MASK);
-}
-
-static inline void switch_mm(struct mm_struct *prev,
- struct mm_struct *next, struct task_struct *tsk)
-{
-#ifdef CONFIG_SMP
- int cpu = smp_processor_id();
-#endif /* CONFIG_SMP */
-
- if (prev != next) {
-#ifdef CONFIG_SMP
- cpumask_set_cpu(cpu, mm_cpumask(next));
-#endif /* CONFIG_SMP */
- /* Set MPTB = next->pgd */
- *(volatile unsigned long *)MPTB = (unsigned long)next->pgd;
- activate_context(next);
- }
-#ifdef CONFIG_SMP
- else
- if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)))
- activate_context(next);
-#endif /* CONFIG_SMP */
-}
-
-#define deactivate_mm(tsk, mm) do { } while (0)
-
-#define activate_mm(prev, next) \
- switch_mm((prev), (next), NULL)
-
-#else /* not CONFIG_MMU */
-#define get_mmu_context(mm) do { } while (0)
-#define init_new_context(tsk,mm) (0)
-#define destroy_context(mm) do { } while (0)
-#define set_asid(asid) do { } while (0)
-#define get_asid() (0)
-#define activate_context(mm) do { } while (0)
-#define switch_mm(prev,next,tsk) do { } while (0)
-#define deactivate_mm(mm,tsk) do { } while (0)
-#define activate_mm(prev,next) do { } while (0)
-#define enter_lazy_tlb(mm,tsk) do { } while (0)
-#endif /* not CONFIG_MMU */
-
-#endif /* not __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_M32R_MMU_CONTEXT_H */
diff --git a/arch/m32r/include/asm/mmzone.h b/arch/m32r/include/asm/mmzone.h
deleted file mode 100644
index 568946c13ba6..000000000000
--- a/arch/m32r/include/asm/mmzone.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Written by Pat Gaughen (gone@us.ibm.com) Mar 2002
- *
- */
-
-#ifndef _ASM_MMZONE_H_
-#define _ASM_MMZONE_H_
-
-#include <asm/smp.h>
-
-#ifdef CONFIG_DISCONTIGMEM
-
-extern struct pglist_data *node_data[];
-#define NODE_DATA(nid) (node_data[nid])
-
-#define node_localnr(pfn, nid) ((pfn) - NODE_DATA(nid)->node_start_pfn)
-
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-/*
- * pfn_valid should be made as fast as possible, and the current definition
- * is valid for machines that are NUMA, but still contiguous, which is what
- * is currently supported. A more generalised, but slower definition would
- * be something like this - mbligh:
- * ( pfn_to_pgdat(pfn) && ((pfn) < node_end_pfn(pfn_to_nid(pfn))) )
- */
-#if 1 /* M32R_FIXME */
-#define pfn_valid(pfn) (1)
-#else
-#define pfn_valid(pfn) ((pfn) < num_physpages)
-#endif
-
-/*
- * generic node memory support, the following assumptions apply:
- */
-
-static __inline__ int pfn_to_nid(unsigned long pfn)
-{
- int node;
-
- for (node = 0 ; node < MAX_NUMNODES ; node++)
- if (pfn >= node_start_pfn(node) && pfn < node_end_pfn(node))
- break;
-
- return node;
-}
-
-static __inline__ struct pglist_data *pfn_to_pgdat(unsigned long pfn)
-{
- return(NODE_DATA(pfn_to_nid(pfn)));
-}
-
-#endif /* CONFIG_DISCONTIGMEM */
-#endif /* _ASM_MMZONE_H_ */
diff --git a/arch/m32r/include/asm/opsput/opsput_lan.h b/arch/m32r/include/asm/opsput/opsput_lan.h
deleted file mode 100644
index a5f18dd1ab20..000000000000
--- a/arch/m32r/include/asm/opsput/opsput_lan.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef _OPSPUT_OPSPUT_LAN_H
-#define _OPSPUT_OPSPUT_LAN_H
-
-/*
- * include/asm-m32r/opsput/opsput_lan.h
- *
- * OPSPUT-LAN board
- *
- * Copyright (c) 2002-2004 Takeo Takahashi, Mamoru Sakugawa
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define OPSPUT_LAN_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define OPSPUT_LAN_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#define OPSPUT_LAN_IRQ_LAN (OPSPUT_LAN_PLD_IRQ_BASE + 1) /* LAN */
-#define OPSPUT_LAN_IRQ_I2C (OPSPUT_LAN_PLD_IRQ_BASE + 3) /* I2C */
-
-#define OPSPUT_LAN_ICUISTS __reg16(OPSPUT_LAN_BASE + 0xc0002)
-#define OPSPUT_LAN_ICUISTS_VECB_MASK (0xf000)
-#define OPSPUT_LAN_VECB(x) ((x) & OPSPUT_LAN_ICUISTS_VECB_MASK)
-#define OPSPUT_LAN_ICUISTS_ISN_MASK (0x07c0)
-#define OPSPUT_LAN_ICUISTS_ISN(x) ((x) & OPSPUT_LAN_ICUISTS_ISN_MASK)
-#define OPSPUT_LAN_ICUIREQ0 __reg16(OPSPUT_LAN_BASE + 0xc0004)
-#define OPSPUT_LAN_ICUCR1 __reg16(OPSPUT_LAN_BASE + 0xc0010)
-#define OPSPUT_LAN_ICUCR3 __reg16(OPSPUT_LAN_BASE + 0xc0014)
-
-#endif /* _OPSPUT_OPSPUT_LAN_H */
diff --git a/arch/m32r/include/asm/opsput/opsput_lcd.h b/arch/m32r/include/asm/opsput/opsput_lcd.h
deleted file mode 100644
index 369c9f0832a6..000000000000
--- a/arch/m32r/include/asm/opsput/opsput_lcd.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _OPSPUT_OPSPUT_LCD_H
-#define _OPSPUT_OPSPUT_LCD_H
-
-/*
- * include/asm-m32r/opsput/opsput_lcd.h
- *
- * OPSPUT-LCD board
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define OPSPUT_LCD_BASE (0x10000000 /* + NONCACHE_OFFSET */)
-#else
-#define OPSPUT_LCD_BASE (0x10000000 + NONCACHE_OFFSET)
-#endif /* __ASSEMBLY__ */
-
-/*
- * ICU
- */
-#define OPSPUT_LCD_IRQ_BAT_INT (OPSPUT_LCD_PLD_IRQ_BASE + 1)
-#define OPSPUT_LCD_IRQ_USB_INT1 (OPSPUT_LCD_PLD_IRQ_BASE + 2)
-#define OPSPUT_LCD_IRQ_AUDT0 (OPSPUT_LCD_PLD_IRQ_BASE + 3)
-#define OPSPUT_LCD_IRQ_AUDT2 (OPSPUT_LCD_PLD_IRQ_BASE + 4)
-#define OPSPUT_LCD_IRQ_BATSIO_RCV (OPSPUT_LCD_PLD_IRQ_BASE + 16)
-#define OPSPUT_LCD_IRQ_BATSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 17)
-#define OPSPUT_LCD_IRQ_ASNDSIO_RCV (OPSPUT_LCD_PLD_IRQ_BASE + 18)
-#define OPSPUT_LCD_IRQ_ASNDSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 19)
-#define OPSPUT_LCD_IRQ_ACNLSIO_SND (OPSPUT_LCD_PLD_IRQ_BASE + 21)
-
-#define OPSPUT_LCD_ICUISTS __reg16(OPSPUT_LCD_BASE + 0x300002)
-#define OPSPUT_LCD_ICUISTS_VECB_MASK (0xf000)
-#define OPSPUT_LCD_VECB(x) ((x) & OPSPUT_LCD_ICUISTS_VECB_MASK)
-#define OPSPUT_LCD_ICUISTS_ISN_MASK (0x07c0)
-#define OPSPUT_LCD_ICUISTS_ISN(x) ((x) & OPSPUT_LCD_ICUISTS_ISN_MASK)
-#define OPSPUT_LCD_ICUIREQ0 __reg16(OPSPUT_LCD_BASE + 0x300004)
-#define OPSPUT_LCD_ICUIREQ1 __reg16(OPSPUT_LCD_BASE + 0x300006)
-#define OPSPUT_LCD_ICUCR1 __reg16(OPSPUT_LCD_BASE + 0x300020)
-#define OPSPUT_LCD_ICUCR2 __reg16(OPSPUT_LCD_BASE + 0x300022)
-#define OPSPUT_LCD_ICUCR3 __reg16(OPSPUT_LCD_BASE + 0x300024)
-#define OPSPUT_LCD_ICUCR4 __reg16(OPSPUT_LCD_BASE + 0x300026)
-#define OPSPUT_LCD_ICUCR16 __reg16(OPSPUT_LCD_BASE + 0x300030)
-#define OPSPUT_LCD_ICUCR17 __reg16(OPSPUT_LCD_BASE + 0x300032)
-#define OPSPUT_LCD_ICUCR18 __reg16(OPSPUT_LCD_BASE + 0x300034)
-#define OPSPUT_LCD_ICUCR19 __reg16(OPSPUT_LCD_BASE + 0x300036)
-#define OPSPUT_LCD_ICUCR21 __reg16(OPSPUT_LCD_BASE + 0x30003a)
-
-#endif /* _OPSPUT_OPSPUT_LCD_H */
diff --git a/arch/m32r/include/asm/opsput/opsput_pld.h b/arch/m32r/include/asm/opsput/opsput_pld.h
deleted file mode 100644
index 6901401fe9eb..000000000000
--- a/arch/m32r/include/asm/opsput/opsput_pld.h
+++ /dev/null
@@ -1,255 +0,0 @@
-#ifndef _OPSPUT_OPSPUT_PLD_H
-#define _OPSPUT_OPSPUT_PLD_H
-
-/*
- * include/asm-m32r/opsput/opsput_pld.h
- *
- * Definitions for Programmable Logic Device(PLD) on OPSPUT board.
- *
- * Copyright (c) 2002 Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of
- * this archive for more details.
- */
-
-#define PLD_PLAT_BASE 0x1cc00000
-
-#ifndef __ASSEMBLY__
-/*
- * C functions use non-cache address.
- */
-#define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
-#define __reg8 (volatile unsigned char *)
-#define __reg16 (volatile unsigned short *)
-#define __reg32 (volatile unsigned int *)
-#else
-#define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
-#define __reg8
-#define __reg16
-#define __reg32
-#endif /* __ASSEMBLY__ */
-
-/* CFC */
-#define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
-#define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
-#define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
-#define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
-#define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
-#define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
-#define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
-#define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
-
-/* MMC */
-#define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
-#define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
-#define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
-#define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
-#define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
-#define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
-#define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
-#define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
-#define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
-#define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
-#define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
-#define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
-
-/* ICU
- * ICUISTS: status register
- * ICUIREQ0: request register
- * ICUIREQ1: request register
- * ICUCR3: control register for CFIREQ# interrupt
- * ICUCR4: control register for CFC Card insert interrupt
- * ICUCR5: control register for CFC Card eject interrupt
- * ICUCR6: control register for external interrupt
- * ICUCR11: control register for MMC Card insert/eject interrupt
- * ICUCR13: control register for SC error interrupt
- * ICUCR14: control register for SC receive interrupt
- * ICUCR15: control register for SC send interrupt
- * ICUCR16: control register for SIO0 receive interrupt
- * ICUCR17: control register for SIO0 send interrupt
- */
-#if !defined(CONFIG_PLAT_USRV)
-#define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CFIREQ (OPSPUT_PLD_IRQ_BASE + 3) /* CF IREQ */
-#define PLD_IRQ_CFC_INSERT (OPSPUT_PLD_IRQ_BASE + 4) /* CF Insert */
-#define PLD_IRQ_CFC_EJECT (OPSPUT_PLD_IRQ_BASE + 5) /* CF Eject */
-#define PLD_IRQ_EXINT (OPSPUT_PLD_IRQ_BASE + 6) /* EXINT */
-#define PLD_IRQ_INT7 (OPSPUT_PLD_IRQ_BASE + 7) /* reserved */
-#define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_MMCCARD (OPSPUT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
-#define PLD_IRQ_INT12 (OPSPUT_PLD_IRQ_BASE + 12) /* reserved */
-#define PLD_IRQ_SC_ERROR (OPSPUT_PLD_IRQ_BASE + 13) /* SC error */
-#define PLD_IRQ_SC_RCV (OPSPUT_PLD_IRQ_BASE + 14) /* SC receive */
-#define PLD_IRQ_SC_SND (OPSPUT_PLD_IRQ_BASE + 15) /* SC send */
-#define PLD_IRQ_SIO0_RCV (OPSPUT_PLD_IRQ_BASE + 16) /* SIO receive */
-#define PLD_IRQ_SIO0_SND (OPSPUT_PLD_IRQ_BASE + 17) /* SIO send */
-#define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */
-#define PLD_IRQ_INT31 (OPSPUT_PLD_IRQ_BASE + 31) /* reserved */
-
-#else /* CONFIG_PLAT_USRV */
-
-#define PLD_IRQ_INT0 (OPSPUT_PLD_IRQ_BASE + 0) /* None */
-#define PLD_IRQ_INT1 (OPSPUT_PLD_IRQ_BASE + 1) /* reserved */
-#define PLD_IRQ_INT2 (OPSPUT_PLD_IRQ_BASE + 2) /* reserved */
-#define PLD_IRQ_CF0 (OPSPUT_PLD_IRQ_BASE + 3) /* CF0# */
-#define PLD_IRQ_CF1 (OPSPUT_PLD_IRQ_BASE + 4) /* CF1# */
-#define PLD_IRQ_CF2 (OPSPUT_PLD_IRQ_BASE + 5) /* CF2# */
-#define PLD_IRQ_CF3 (OPSPUT_PLD_IRQ_BASE + 6) /* CF3# */
-#define PLD_IRQ_CF4 (OPSPUT_PLD_IRQ_BASE + 7) /* CF4# */
-#define PLD_IRQ_INT8 (OPSPUT_PLD_IRQ_BASE + 8) /* reserved */
-#define PLD_IRQ_INT9 (OPSPUT_PLD_IRQ_BASE + 9) /* reserved */
-#define PLD_IRQ_INT10 (OPSPUT_PLD_IRQ_BASE + 10) /* reserved */
-#define PLD_IRQ_INT11 (OPSPUT_PLD_IRQ_BASE + 11) /* reserved */
-#define PLD_IRQ_UART0 (OPSPUT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */
-#define PLD_IRQ_UART1 (OPSPUT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */
-#define PLD_IRQ_INT14 (OPSPUT_PLD_IRQ_BASE + 14) /* reserved */
-#define PLD_IRQ_INT15 (OPSPUT_PLD_IRQ_BASE + 15) /* reserved */
-#define PLD_IRQ_SNDINT (OPSPUT_PLD_IRQ_BASE + 16) /* SNDINT# */
-#define PLD_IRQ_INT17 (OPSPUT_PLD_IRQ_BASE + 17) /* reserved */
-#define PLD_IRQ_INT18 (OPSPUT_PLD_IRQ_BASE + 18) /* reserved */
-#define PLD_IRQ_INT19 (OPSPUT_PLD_IRQ_BASE + 19) /* reserved */
-#define PLD_IRQ_INT20 (OPSPUT_PLD_IRQ_BASE + 20) /* reserved */
-#define PLD_IRQ_INT21 (OPSPUT_PLD_IRQ_BASE + 21) /* reserved */
-#define PLD_IRQ_INT22 (OPSPUT_PLD_IRQ_BASE + 22) /* reserved */
-#define PLD_IRQ_INT23 (OPSPUT_PLD_IRQ_BASE + 23) /* reserved */
-#define PLD_IRQ_INT24 (OPSPUT_PLD_IRQ_BASE + 24) /* reserved */
-#define PLD_IRQ_INT25 (OPSPUT_PLD_IRQ_BASE + 25) /* reserved */
-#define PLD_IRQ_INT26 (OPSPUT_PLD_IRQ_BASE + 26) /* reserved */
-#define PLD_IRQ_INT27 (OPSPUT_PLD_IRQ_BASE + 27) /* reserved */
-#define PLD_IRQ_INT28 (OPSPUT_PLD_IRQ_BASE + 28) /* reserved */
-#define PLD_IRQ_INT29 (OPSPUT_PLD_IRQ_BASE + 29) /* reserved */
-#define PLD_IRQ_INT30 (OPSPUT_PLD_IRQ_BASE + 30) /* reserved */
-
-#endif /* CONFIG_PLAT_USRV */
-
-#define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
-#define PLD_ICUISTS_VECB_MASK (0xf000)
-#define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
-#define PLD_ICUISTS_ISN_MASK (0x07c0)
-#define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
-#define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
-#define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
-#define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
-#define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
-#define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
-#define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
-#define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
-#define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
-#define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
-#define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
-#define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
-#define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
-#define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
-#define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
-#define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
-#define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
-#define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
-#define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
-#define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
-#define PLD_ICUCR_IEN (0x1000)
-#define PLD_ICUCR_IREQ (0x0100)
-#define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
-#define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
-#define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
-#define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
-#define PLD_ICUCR_ILEVEL0 (0x0000)
-#define PLD_ICUCR_ILEVEL1 (0x0001)
-#define PLD_ICUCR_ILEVEL2 (0x0002)
-#define PLD_ICUCR_ILEVEL3 (0x0003)
-#define PLD_ICUCR_ILEVEL4 (0x0004)
-#define PLD_ICUCR_ILEVEL5 (0x0005)
-#define PLD_ICUCR_ILEVEL6 (0x0006)
-#define PLD_ICUCR_ILEVEL7 (0x0007)
-
-/* Power Control of MMC and CF */
-#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
-#define PLD_CPCR_CF 0x0001
-#define PLD_CPCR_MMC 0x0002
-
-/* LED Control
- *
- * 1: DIP swich side
- * 2: Reset switch side
- */
-#define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
-#define PLD_IOLED_1_ON 0x001
-#define PLD_IOLED_1_OFF 0x000
-#define PLD_IOLED_2_ON 0x002
-#define PLD_IOLED_2_OFF 0x000
-
-/* DIP Switch
- * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
- * 1: -
- * 2: -
- * 3: -
- */
-#define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
-#define PLD_IOSWSTS_IOSW2 0x0200
-#define PLD_IOSWSTS_IOSW1 0x0100
-#define PLD_IOSWSTS_IOWP0 0x0001
-
-/* CRC */
-#define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
-#define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
-#define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
-#define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
-#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
-#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
-
-/* RTC */
-#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
-#define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
-#define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
-#define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
-#define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
-
-/* SIO0 */
-#define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
-#define PLD_ESIO0CR_TXEN 0x0001
-#define PLD_ESIO0CR_RXEN 0x0002
-#define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
-#define PLD_ESIO0MOD0_CTSS 0x0040
-#define PLD_ESIO0MOD0_RTSS 0x0080
-#define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
-#define PLD_ESIO0MOD1_LMFS 0x0010
-#define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
-#define PLD_ESIO0STS_TEMP 0x0001
-#define PLD_ESIO0STS_TXCP 0x0002
-#define PLD_ESIO0STS_RXCP 0x0004
-#define PLD_ESIO0STS_TXSC 0x0100
-#define PLD_ESIO0STS_RXSC 0x0200
-#define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
-#define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
-#define PLD_ESIO0INTCR_TXIEN 0x0002
-#define PLD_ESIO0INTCR_RXCEN 0x0004
-#define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
-#define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
-#define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
-
-/* SIM Card */
-#define PLD_SCCR __reg16(PLD_BASE + 0x38000)
-#define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
-#define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
-#define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
-#define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
-#define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
-#define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
-
-#endif /* _OPSPUT_OPSPUT_PLD.H */
diff --git a/arch/m32r/include/asm/page.h b/arch/m32r/include/asm/page.h
deleted file mode 100644
index fe4e38b394d3..000000000000
--- a/arch/m32r/include/asm/page.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PAGE_H
-#define _ASM_M32R_PAGE_H
-
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT 12
-#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#ifndef __ASSEMBLY__
-
-extern void clear_page(void *to);
-extern void copy_page(void *to, void *from);
-
-#define clear_user_page(page, vaddr, pg) clear_page(page)
-#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
- alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-#define pte_val(x) ((x).pte)
-#define PTE_MASK PAGE_MASK
-
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pmd_val(x) ((x).pmd)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) } )
-#define __pmd(x) ((pmd_t) { (x) } )
-#define __pgd(x) ((pgd_t) { (x) } )
-#define __pgprot(x) ((pgprot_t) { (x) } )
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * This handles the memory map.. We could make this a config
- * option, but too many people screw it up, and too few need
- * it.
- *
- * A __PAGE_OFFSET of 0xC0000000 means that the kernel has
- * a virtual address space of one gigabyte, which limits the
- * amount of physical memory you can use to about 950MB.
- *
- * If you want more physical memory than this then see the CONFIG_HIGHMEM4G
- * and CONFIG_HIGHMEM64G options in the kernel configuration.
- */
-
-#define __MEMORY_START CONFIG_MEMORY_START
-#define __MEMORY_SIZE CONFIG_MEMORY_SIZE
-
-#ifdef CONFIG_MMU
-#define __PAGE_OFFSET (0x80000000)
-#else
-#define __PAGE_OFFSET (0x00000000)
-#endif
-
-#define PAGE_OFFSET ((unsigned long)__PAGE_OFFSET)
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
-#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define PFN_BASE (CONFIG_MEMORY_START >> PAGE_SHIFT)
-#define ARCH_PFN_OFFSET PFN_BASE
-#define pfn_valid(pfn) (((pfn) - PFN_BASE) < max_mapnr)
-#endif /* !CONFIG_DISCONTIGMEM */
-
-#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC )
-
-#define devmem_is_allowed(x) 1
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* _ASM_M32R_PAGE_H */
diff --git a/arch/m32r/include/asm/pci.h b/arch/m32r/include/asm/pci.h
deleted file mode 100644
index cbcb28b5f6ff..000000000000
--- a/arch/m32r/include/asm/pci.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PCI_H
-#define _ASM_M32R_PCI_H
-
-#include <asm-generic/pci.h>
-
-#endif /* _ASM_M32R_PCI_H */
diff --git a/arch/m32r/include/asm/percpu.h b/arch/m32r/include/asm/percpu.h
deleted file mode 100644
index 41e1680d1117..000000000000
--- a/arch/m32r/include/asm/percpu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ARCH_M32R_PERCPU__
-#define __ARCH_M32R_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_M32R_PERCPU__ */
diff --git a/arch/m32r/include/asm/pgalloc.h b/arch/m32r/include/asm/pgalloc.h
deleted file mode 100644
index eed2cad57d68..000000000000
--- a/arch/m32r/include/asm/pgalloc.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PGALLOC_H
-#define _ASM_M32R_PGALLOC_H
-
-#include <linux/mm.h>
-
-#include <asm/io.h>
-
-#define pmd_populate_kernel(mm, pmd, pte) \
- set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
-
-static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- pgtable_t pte)
-{
- set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
-}
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
-
- return pgd;
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- free_page((unsigned long)pgd);
-}
-
-static __inline__ pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
- unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
-
- return pte;
-}
-
-static __inline__ pgtable_t pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- struct page *pte = alloc_page(GFP_KERNEL|__GFP_ZERO);
-
- if (!pte)
- return NULL;
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-#define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, (pte))
-
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- * (In the PAE case we free the pmds as part of the pgd.)
- */
-
-#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
-#define pmd_free(mm, x) do { } while (0)
-#define __pmd_free_tlb(tlb, x, addr) do { } while (0)
-#define pgd_populate(mm, pmd, pte) BUG()
-
-#define check_pgt_cache() do { } while (0)
-
-#endif /* _ASM_M32R_PGALLOC_H */
diff --git a/arch/m32r/include/asm/pgtable-2level.h b/arch/m32r/include/asm/pgtable-2level.h
deleted file mode 100644
index d7ab1e94e3cb..000000000000
--- a/arch/m32r/include/asm/pgtable-2level.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PGTABLE_2LEVEL_H
-#define _ASM_M32R_PGTABLE_2LEVEL_H
-#ifdef __KERNEL__
-
-/*
- * traditional M32R two-level paging structure:
- */
-
-#define PGDIR_SHIFT 22
-#define PTRS_PER_PGD 1024
-
-/*
- * the M32R is two-level, so we don't really have any
- * PMD directory physically.
- */
-#define __PAGETABLE_PMD_FOLDED
-#define PMD_SHIFT 22
-#define PTRS_PER_PMD 1
-
-#define PTRS_PER_PTE 1024
-
-#define pte_ERROR(e) \
- printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
- printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-static inline int pgd_none(pgd_t pgd) { return 0; }
-static inline int pgd_bad(pgd_t pgd) { return 0; }
-static inline int pgd_present(pgd_t pgd) { return 1; }
-#define pgd_clear(xp) do { } while (0)
-
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
-
-#define pgd_page_vaddr(pgd) \
-((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pgd_page(pgd) (mem_map + ((pgd_val(pgd) >> PAGE_SHIFT) - PFN_BASE))
-#endif /* !CONFIG_DISCONTIGMEM */
-
-static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
-{
- return (pmd_t *) dir;
-}
-
-#define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte, 0))
-#define pte_same(a, b) (pte_val(a) == pte_val(b))
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-#define pte_none(x) (!pte_val(x))
-#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
-#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_M32R_PGTABLE_2LEVEL_H */
diff --git a/arch/m32r/include/asm/pgtable.h b/arch/m32r/include/asm/pgtable.h
deleted file mode 100644
index eb7f9050c8d6..000000000000
--- a/arch/m32r/include/asm/pgtable.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_PGTABLE_H
-#define _ASM_M32R_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#ifdef __KERNEL__
-/*
- * The Linux memory management assumes a three-level page table setup. On
- * the M32R, we use that, but "fold" the mid level into the top-level page
- * table, so that we physically have the same two-level page table as the
- * M32R mmu expects.
- *
- * This file contains the functions and defines necessary to modify and use
- * the M32R page table tree.
- */
-
-/* CAUTION!: If you change macro definitions in this file, you might have to
- * change arch/m32r/mmu.S manually.
- */
-
-#ifndef __ASSEMBLY__
-
-#include <linux/threads.h>
-#include <linux/bitops.h>
-#include <asm/processor.h>
-#include <asm/addrspace.h>
-#include <asm/page.h>
-
-struct mm_struct;
-struct vm_area_struct;
-
-extern pgd_t swapper_pg_dir[1024];
-extern void paging_init(void);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[1024];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-#endif /* !__ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-#include <asm/pgtable-2level.h>
-#endif
-
-#define pgtable_cache_init() do { } while (0)
-
-#define PMD_SIZE (1UL << PMD_SHIFT)
-#define PMD_MASK (~(PMD_SIZE - 1))
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-
-#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-#ifndef __ASSEMBLY__
-/* Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts. That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_START KSEG2
-#define VMALLOC_END KSEG3
-
-/*
- * M32R TLB format
- *
- * [0] [1:19] [20:23] [24:31]
- * +-----------------------+----+-------------+
- * | VPN |0000| ASID |
- * +-----------------------+----+-------------+
- * +-+---------------------+----+-+---+-+-+-+-+
- * |0 PPN |0000|N|AC |L|G|V| |
- * +-+---------------------+----+-+---+-+-+-+-+
- * RWX
- */
-
-#define _PAGE_BIT_DIRTY 0 /* software: page changed */
-#define _PAGE_BIT_PRESENT 1 /* Valid: page is valid */
-#define _PAGE_BIT_GLOBAL 2 /* Global */
-#define _PAGE_BIT_LARGE 3 /* Large */
-#define _PAGE_BIT_EXEC 4 /* Execute */
-#define _PAGE_BIT_WRITE 5 /* Write */
-#define _PAGE_BIT_READ 6 /* Read */
-#define _PAGE_BIT_NONCACHABLE 7 /* Non cachable */
-#define _PAGE_BIT_ACCESSED 8 /* software: page referenced */
-#define _PAGE_BIT_PROTNONE 9 /* software: if not present */
-
-#define _PAGE_DIRTY (1UL << _PAGE_BIT_DIRTY)
-#define _PAGE_PRESENT (1UL << _PAGE_BIT_PRESENT)
-#define _PAGE_GLOBAL (1UL << _PAGE_BIT_GLOBAL)
-#define _PAGE_LARGE (1UL << _PAGE_BIT_LARGE)
-#define _PAGE_EXEC (1UL << _PAGE_BIT_EXEC)
-#define _PAGE_WRITE (1UL << _PAGE_BIT_WRITE)
-#define _PAGE_READ (1UL << _PAGE_BIT_READ)
-#define _PAGE_NONCACHABLE (1UL << _PAGE_BIT_NONCACHABLE)
-#define _PAGE_ACCESSED (1UL << _PAGE_BIT_ACCESSED)
-#define _PAGE_PROTNONE (1UL << _PAGE_BIT_PROTNONE)
-
-#define _PAGE_TABLE \
- ( _PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_ACCESSED \
- | _PAGE_DIRTY )
-#define _KERNPG_TABLE \
- ( _PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_ACCESSED \
- | _PAGE_DIRTY )
-#define _PAGE_CHG_MASK \
- ( PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY )
-
-#ifdef CONFIG_MMU
-#define PAGE_NONE \
- __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
-#define PAGE_SHARED \
- __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_SHARED_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_WRITE | _PAGE_READ \
- | _PAGE_ACCESSED)
-#define PAGE_COPY \
- __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_COPY_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_READONLY \
- __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_ACCESSED)
-#define PAGE_READONLY_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_ACCESSED)
-
-#define __PAGE_KERNEL \
- ( _PAGE_PRESENT | _PAGE_EXEC | _PAGE_WRITE | _PAGE_READ | _PAGE_DIRTY \
- | _PAGE_ACCESSED )
-#define __PAGE_KERNEL_RO ( __PAGE_KERNEL & ~_PAGE_WRITE )
-#define __PAGE_KERNEL_NOCACHE ( __PAGE_KERNEL | _PAGE_NONCACHABLE)
-
-#define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
-
-#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
-#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
-#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
-
-#else
-#define PAGE_NONE __pgprot(0)
-#define PAGE_SHARED __pgprot(0)
-#define PAGE_SHARED_EXEC __pgprot(0)
-#define PAGE_COPY __pgprot(0)
-#define PAGE_COPY_EXEC __pgprot(0)
-#define PAGE_READONLY __pgprot(0)
-#define PAGE_READONLY_EXEC __pgprot(0)
-
-#define PAGE_KERNEL __pgprot(0)
-#define PAGE_KERNEL_RO __pgprot(0)
-#define PAGE_KERNEL_NOCACHE __pgprot(0)
-#endif /* CONFIG_MMU */
-
- /* xwr */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY_EXEC
-#define __P101 PAGE_READONLY_EXEC
-#define __P110 PAGE_COPY_EXEC
-#define __P111 PAGE_COPY_EXEC
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY_EXEC
-#define __S101 PAGE_READONLY_EXEC
-#define __S110 PAGE_SHARED_EXEC
-#define __S111 PAGE_SHARED_EXEC
-
-/* page table for 0-4MB for everybody */
-
-#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
-#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK) != _KERNPG_TABLE)
-
-#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_dirty(pte_t pte)
-{
- return pte_val(pte) & _PAGE_DIRTY;
-}
-
-static inline int pte_young(pte_t pte)
-{
- return pte_val(pte) & _PAGE_ACCESSED;
-}
-
-static inline int pte_write(pte_t pte)
-{
- return pte_val(pte) & _PAGE_WRITE;
-}
-
-static inline int pte_special(pte_t pte)
-{
- return 0;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
- pte_val(pte) &= ~_PAGE_DIRTY;
- return pte;
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
- pte_val(pte) &= ~_PAGE_ACCESSED;
- return pte;
-}
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- pte_val(pte) &= ~_PAGE_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
- pte_val(pte) |= _PAGE_DIRTY;
- return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
- pte_val(pte) |= _PAGE_ACCESSED;
- return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
- pte_val(pte) |= _PAGE_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkspecial(pte_t pte)
-{
- return pte;
-}
-
-static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
-{
- return test_and_clear_bit(_PAGE_BIT_ACCESSED, ptep);
-}
-
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
- clear_bit(_PAGE_BIT_WRITE, ptep);
-}
-
-/*
- * Macro and implementation to make a page protection as uncachable.
- */
-static inline pgprot_t pgprot_noncached(pgprot_t _prot)
-{
- unsigned long prot = pgprot_val(_prot);
-
- prot |= _PAGE_NONCACHABLE;
- return __pgprot(prot);
-}
-
-#define pgprot_writecombine(prot) pgprot_noncached(prot)
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), pgprot)
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) \
- | pgprot_val(newprot)));
-
- return pte;
-}
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
-{
- pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
-}
-
-#define pmd_page_vaddr(pmd) \
- ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pmd_page(pmd) (mem_map + ((pmd_val(pmd) >> PAGE_SHIFT) - PFN_BASE))
-#endif /* !CONFIG_DISCONTIGMEM */
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address) \
- (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-#define pmd_index(address) \
- (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
-
-#define pte_index(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *)pmd_page_vaddr(*(dir)) + pte_index(address))
-#define pte_offset_map(dir, address) \
- ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
-#define pte_unmap(pte) do { } while (0)
-
-/* Encode and de-code a swap entry */
-#define __swp_type(x) (((x).val >> 2) & 0x1f)
-#define __swp_offset(x) ((x).val >> 10)
-#define __swp_entry(type, offset) \
- ((swp_entry_t) { ((type) << 2) | ((offset) << 10) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#endif /* !__ASSEMBLY__ */
-
-/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
-#define kern_addr_valid(addr) (1)
-
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define __HAVE_ARCH_PTE_SAME
-#include <asm-generic/pgtable.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_PGTABLE_H */
diff --git a/arch/m32r/include/asm/processor.h b/arch/m32r/include/asm/processor.h
deleted file mode 100644
index c70fa9ac7169..000000000000
--- a/arch/m32r/include/asm/processor.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _ASM_M32R_PROCESSOR_H
-#define _ASM_M32R_PROCESSOR_H
-
-/*
- * include/asm-m32r/processor.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 Linus Torvalds
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/kernel.h>
-#include <asm/cache.h>
-#include <asm/ptrace.h> /* pt_regs */
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l; })
-
-/*
- * CPU type and hardware bug flags. Kept separately for each CPU.
- * Members of this structure are referenced in head.S, so think twice
- * before touching them. [mj]
- */
-
-struct cpuinfo_m32r {
- unsigned long pgtable_cache_sz;
- unsigned long cpu_clock;
- unsigned long bus_clock;
- unsigned long timer_divide;
- unsigned long loops_per_jiffy;
-};
-
-/*
- * capabilities of CPUs
- */
-
-extern struct cpuinfo_m32r boot_cpu_data;
-
-#ifdef CONFIG_SMP
-extern struct cpuinfo_m32r cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#else
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
-#endif
-
-/*
- * User space process size: 2GB (default).
- */
-#ifdef CONFIG_MMU
-#define TASK_SIZE (0x80000000UL)
-#else
-#define TASK_SIZE (0x00400000UL)
-#endif
-
-#ifdef __KERNEL__
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-#endif
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#define MAX_TRAPS 10
-
-struct debug_trap {
- int nr_trap;
- unsigned long addr[MAX_TRAPS];
- unsigned long insn[MAX_TRAPS];
-};
-
-struct thread_struct {
- unsigned long address;
- unsigned long trap_no; /* Trap number */
- unsigned long error_code; /* Error code of trap */
- unsigned long lr; /* saved pc */
- unsigned long sp; /* user stack pointer */
- struct debug_trap debug_trap;
-};
-
-#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
-
-#define INIT_THREAD { \
- .sp = INIT_SP, \
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- */
-
-/* User process Backup PSW */
-#define USERPS_BPSW (M32R_PSW_BSM|M32R_PSW_BIE|M32R_PSW_BPM)
-
-#define start_thread(regs, new_pc, new_spu) \
- do { \
- regs->psw = (regs->psw | USERPS_BPSW) & 0x0000FFFFUL; \
- regs->bpc = new_pc; \
- regs->spu = new_spu; \
- } while (0)
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-struct mm_struct;
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
-unsigned long get_wchan(struct task_struct *p);
-#define KSTK_EIP(tsk) ((tsk)->thread.lr)
-#define KSTK_ESP(tsk) ((tsk)->thread.sp)
-
-#define cpu_relax() barrier()
-
-#endif /* _ASM_M32R_PROCESSOR_H */
diff --git a/arch/m32r/include/asm/ptrace.h b/arch/m32r/include/asm/ptrace.h
deleted file mode 100644
index fa58ccfff865..000000000000
--- a/arch/m32r/include/asm/ptrace.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * linux/include/asm-m32r/ptrace.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * M32R version:
- * Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_PTRACE_H
-#define _ASM_M32R_PTRACE_H
-
-
-#include <asm/m32r.h> /* M32R_PSW_BSM, M32R_PSW_BPM */
-#include <uapi/asm/ptrace.h>
-
-#define arch_has_single_step() (1)
-
-struct task_struct;
-extern void init_debug_traps(struct task_struct *);
-#define arch_ptrace_attach(child) \
- init_debug_traps(child)
-
-#if defined(CONFIG_ISA_M32R2) || defined(CONFIG_CHIP_VDEC2)
-#define user_mode(regs) ((M32R_PSW_BPM & (regs)->psw) != 0)
-#elif defined(CONFIG_ISA_M32R)
-#define user_mode(regs) ((M32R_PSW_BSM & (regs)->psw) != 0)
-#else
-#error unknown isa configuration
-#endif
-
-#define instruction_pointer(regs) ((regs)->bpc)
-#define profile_pc(regs) instruction_pointer(regs)
-#define user_stack_pointer(regs) ((regs)->spu)
-
-extern void withdraw_debug_trap(struct pt_regs *regs);
-
-#define task_pt_regs(task) \
- ((struct pt_regs *)(task_stack_page(task) + THREAD_SIZE) - 1)
-#define current_pt_regs() ((struct pt_regs *) \
- ((unsigned long)current_thread_info() + THREAD_SIZE) - 1)
-
-#endif /* _ASM_M32R_PTRACE_H */
diff --git a/arch/m32r/include/asm/rtc.h b/arch/m32r/include/asm/rtc.h
deleted file mode 100644
index a94cf1edc60f..000000000000
--- a/arch/m32r/include/asm/rtc.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __RTC_H__
-#define __RTC_H__
-
- /* Dallas DS1302 clock/calendar register numbers. */
-# define RTC_SECONDS 0
-# define RTC_MINUTES 1
-# define RTC_HOURS 2
-# define RTC_DAY_OF_MONTH 3
-# define RTC_MONTH 4
-# define RTC_WEEKDAY 5
-# define RTC_YEAR 6
-# define RTC_CONTROL 7
-
- /* Bits in CONTROL register. */
-# define RTC_CONTROL_WRITEPROTECT 0x80
-# define RTC_TRICKLECHARGER 8
-
- /* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */
-# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */
-# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */
-# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */
-# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */
-# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */
-# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */
-# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */
-
-#ifdef CONFIG_DS1302
-extern unsigned char ds1302_readreg(int reg);
-extern void ds1302_writereg(int reg, unsigned char val);
-extern int ds1302_init(void);
-# define CMOS_READ(x) ds1302_readreg(x)
-# define CMOS_WRITE(val,reg) ds1302_writereg(reg,val)
-# define RTC_INIT() ds1302_init()
-#else
- /* No RTC configured so we shouldn't try to access any. */
-# define CMOS_READ(x) 42
-# define CMOS_WRITE(x,y)
-# define RTC_INIT() (-1)
-#endif
-
-/*
- * The struct used to pass data via the following ioctl. Similar to the
- * struct tm in <time.h>, but it needs to be here so that the kernel
- * source is self contained, allowing cross-compiles, etc. etc.
- */
-struct rtc_time {
- int tm_sec;
- int tm_min;
- int tm_hour;
- int tm_mday;
- int tm_mon;
- int tm_year;
- int tm_wday;
- int tm_yday;
- int tm_isdst;
-};
-
-/* ioctl() calls that are permitted to the /dev/rtc interface. */
-#define RTC_MAGIC 'p'
-#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) /* Read RTC time. */
-#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) /* Set RTC time. */
-#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int)
-#define RTC_MAX_IOCTL 0x0b
-
-#endif /* __RTC_H__ */
diff --git a/arch/m32r/include/asm/s1d13806.h b/arch/m32r/include/asm/s1d13806.h
deleted file mode 100644
index 79e98a259ebe..000000000000
--- a/arch/m32r/include/asm/s1d13806.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-//----------------------------------------------------------------------------
-//
-// File generated by S1D13806CFG.EXE
-//
-// Copyright (c) 2000,2001 Epson Research and Development, Inc.
-// All rights reserved.
-//
-//----------------------------------------------------------------------------
-
-// Panel: (active) 640x480 77Hz STN Single 8-bit (PCLK=CLKI=25.175MHz)
-// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=33.333MHz)
-
-#define SWIVEL_VIEW 0 /* 0:none, 1:90 not completed */
-
-static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
-
- {0x0001,0x00}, // Miscellaneous Register
- {0x01FC,0x00}, // Display Mode Register
-#if defined(CONFIG_PLAT_MAPPI)
- {0x0004,0x00}, // General IO Pins Configuration Register 0
- {0x0005,0x00}, // General IO Pins Configuration Register 1
- {0x0008,0x00}, // General IO Pins Control Register 0
- {0x0009,0x00}, // General IO Pins Control Register 1
- {0x0010,0x00}, // Memory Clock Configuration Register
- {0x0014,0x00}, // LCD Pixel Clock Configuration Register
- {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
- {0x001C,0x00}, // MediaPlug Clock Configuration Register
-/*
- * .. 10MHz: 0x00
- * .. 30MHz: 0x01
- * 30MHz ..: 0x02
- */
- {0x001E,0x02}, // CPU To Memory Wait State Select Register
- {0x0021,0x02}, // DRAM Refresh Rate Register
- {0x002A,0x11}, // DRAM Timings Control Register 0
- {0x002B,0x13}, // DRAM Timings Control Register 1
- {0x0020,0x80}, // Memory Configuration Register
- {0x0030,0x25}, // Panel Type Register
- {0x0031,0x00}, // MOD Rate Register
- {0x0032,0x4F}, // LCD Horizontal Display Width Register
- {0x0034,0x12}, // LCD Horizontal Non-Display Period Register
- {0x0035,0x01}, // TFT FPLINE Start Position Register
- {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
- {0x0038,0xDF}, // LCD Vertical Display Height Register 0
- {0x0039,0x01}, // LCD Vertical Display Height Register 1
- {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
- {0x003B,0x0A}, // TFT FPFRAME Start Position Register
- {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
-
- {0x0041,0x00}, // LCD Miscellaneous Register
- {0x0042,0x00}, // LCD Display Start Address Register 0
- {0x0043,0x00}, // LCD Display Start Address Register 1
- {0x0044,0x00}, // LCD Display Start Address Register 2
-
-#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
- {0x0004,0x07}, // GPIO[0:7] direction
- {0x0005,0x00}, // GPIO[8:12] direction
- {0x0008,0x00}, // GPIO[0:7] data
- {0x0009,0x00}, // GPIO[8:12] data
- {0x0008,0x04}, // LCD panel Vcc on
- {0x0008,0x05}, // LCD panel reset
- {0x0010,0x01}, // Memory Clock Configuration Register
- {0x0014,0x30}, // LCD Pixel Clock Configuration Register (CLKI 22MHz/4)
- {0x0018,0x00}, // CRT/TV Pixel Clock Configuration Register
- {0x001C,0x00}, // MediaPlug Clock Configuration Register(10MHz)
- {0x001E,0x00}, // CPU To Memory Wait State Select Register
- {0x0020,0x80}, // Memory Configuration Register
- {0x0021,0x03}, // DRAM Refresh Rate Register
- {0x002A,0x00}, // DRAM Timings Control Register 0
- {0x002B,0x01}, // DRAM Timings Control Register 1
- {0x0030,0x25}, // Panel Type Register
- {0x0031,0x00}, // MOD Rate Register
- {0x0032,0x1d}, // LCD Horizontal Display Width Register
- {0x0034,0x05}, // LCD Horizontal Non-Display Period Register
- {0x0035,0x01}, // TFT FPLINE Start Position Register
- {0x0036,0x01}, // TFT FPLINE Pulse Width Register
- {0x0038,0x3F}, // LCD Vertical Display Height Register 0
- {0x0039,0x01}, // LCD Vertical Display Height Register 1
- {0x003A,0x0b}, // LCD Vertical Non-Display Period Register
- {0x003B,0x07}, // TFT FPFRAME Start Position Register
- {0x003C,0x02}, // TFT FPFRAME Pulse Width Register
-
- {0x0041,0x00}, // LCD Miscellaneous Register
-#if (SWIVEL_VIEW == 0)
- {0x0042,0x00}, // LCD Display Start Address Register 0
- {0x0043,0x00}, // LCD Display Start Address Register 1
- {0x0044,0x00}, // LCD Display Start Address Register 2
-
-#elif (SWIVEL_VIEW == 1)
- // 1024 - W(320) = 0x2C0
- {0x0042,0xC0}, // LCD Display Start Address Register 0
- {0x0043,0x02}, // LCD Display Start Address Register 1
- {0x0044,0x00}, // LCD Display Start Address Register 2
- // 1024
- {0x0046,0x00}, // LCD Memory Address Offset Register 0
- {0x0047,0x02}, // LCD Memory Address Offset Register 1
-#else
-#error unsupported SWIVEL_VIEW mode
-#endif
-#else
-#error no platform configuration
-#endif /* CONFIG_PLAT_XXX */
-
- {0x0048,0x00}, // LCD Pixel Panning Register
- {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
- {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
- {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
- {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
- {0x0053,0x01}, // CRT/TV HRTC Start Position Register
- {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
- {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
- {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
- {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
- {0x0059,0x09}, // CRT/TV VRTC Start Position Register
- {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
- {0x005B,0x10}, // TV Output Control Register
-
- {0x0062,0x00}, // CRT/TV Display Start Address Register 0
- {0x0063,0x00}, // CRT/TV Display Start Address Register 1
- {0x0064,0x00}, // CRT/TV Display Start Address Register 2
-
- {0x0068,0x00}, // CRT/TV Pixel Panning Register
- {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
- {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
- {0x0070,0x00}, // LCD Ink/Cursor Control Register
- {0x0071,0x01}, // LCD Ink/Cursor Start Address Register
- {0x0072,0x00}, // LCD Cursor X Position Register 0
- {0x0073,0x00}, // LCD Cursor X Position Register 1
- {0x0074,0x00}, // LCD Cursor Y Position Register 0
- {0x0075,0x00}, // LCD Cursor Y Position Register 1
- {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
- {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
- {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
- {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
- {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
- {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
- {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
- {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
- {0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register
- {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
- {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
- {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
- {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
- {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
- {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
- {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
- {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
- {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
- {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
- {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
- {0x0100,0x00}, // BitBlt Control Register 0
- {0x0101,0x00}, // BitBlt Control Register 1
- {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
- {0x0103,0x00}, // BitBlt Operation Register
- {0x0104,0x00}, // BitBlt Source Start Address Register 0
- {0x0105,0x00}, // BitBlt Source Start Address Register 1
- {0x0106,0x00}, // BitBlt Source Start Address Register 2
- {0x0108,0x00}, // BitBlt Destination Start Address Register 0
- {0x0109,0x00}, // BitBlt Destination Start Address Register 1
- {0x010A,0x00}, // BitBlt Destination Start Address Register 2
- {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
- {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
- {0x0110,0x00}, // BitBlt Width Register 0
- {0x0111,0x00}, // BitBlt Width Register 1
- {0x0112,0x00}, // BitBlt Height Register 0
- {0x0113,0x00}, // BitBlt Height Register 1
- {0x0114,0x00}, // BitBlt Background Color Register 0
- {0x0115,0x00}, // BitBlt Background Color Register 1
- {0x0118,0x00}, // BitBlt Foreground Color Register 0
- {0x0119,0x00}, // BitBlt Foreground Color Register 1
- {0x01E0,0x00}, // Look-Up Table Mode Register
- {0x01E2,0x00}, // Look-Up Table Address Register
- {0x01F0,0x10}, // Power Save Configuration Register
- {0x01F1,0x00}, // Power Save Status Register
- {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
-#if (SWIVEL_VIEW == 0)
- {0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
-#elif (SWIVEL_VIEW == 1)
- {0x01FC,0x41}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
-#else
-#error unsupported SWIVEL_VIEW mode
-#endif /* SWIVEL_VIEW */
-
-#if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
- {0x0008,0x07}, // LCD panel Vdd & Vg on
-#endif
-
- {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
-#if defined(CONFIG_PLAT_MAPPI)
- {0x0046,0x80}, // LCD Memory Address Offset Register 0
- {0x0047,0x02}, // LCD Memory Address Offset Register 1
-#elif defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
- {0x0046,0xf0}, // LCD Memory Address Offset Register 0
- {0x0047,0x00}, // LCD Memory Address Offset Register 1
-#endif
- {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
- {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0 // takeo
- {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
-};
diff --git a/arch/m32r/include/asm/segment.h b/arch/m32r/include/asm/segment.h
deleted file mode 100644
index 4095f14728e5..000000000000
--- a/arch/m32r/include/asm/segment.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SEGMENT_H
-#define _ASM_M32R_SEGMENT_H
-
-#define __KERNEL_CS 0x10
-#define __KERNEL_DS 0x18
-
-#define __USER_CS 0x23
-#define __USER_DS 0x2B
-
-#endif /* _ASM_M32R_SEGMENT_H */
diff --git a/arch/m32r/include/asm/serial.h b/arch/m32r/include/asm/serial.h
deleted file mode 100644
index b1375c841b4d..000000000000
--- a/arch/m32r/include/asm/serial.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SERIAL_H
-#define _ASM_M32R_SERIAL_H
-
-/* include/asm-m32r/serial.h */
-
-
-#define BASE_BAUD 115200
-
-#endif /* _ASM_M32R_SERIAL_H */
diff --git a/arch/m32r/include/asm/setup.h b/arch/m32r/include/asm/setup.h
deleted file mode 100644
index 71b4d6514078..000000000000
--- a/arch/m32r/include/asm/setup.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SETUP_H
-#define _ASM_M32R_SETUP_H
-
-#include <uapi/asm/setup.h>
-
-
-#define PARAM ((unsigned char *)empty_zero_page)
-
-#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
-#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
-#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
-#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
-#define INITRD_START (*(unsigned long *) (PARAM+0x010))
-#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
-
-#define M32R_CPUCLK (*(unsigned long *) (PARAM+0x018))
-#define M32R_BUSCLK (*(unsigned long *) (PARAM+0x01c))
-#define M32R_TIMER_DIVIDE (*(unsigned long *) (PARAM+0x020))
-
-#define COMMAND_LINE ((char *) (PARAM+0x100))
-
-#define SCREEN_INFO (*(struct screen_info *) (PARAM+0x200))
-
-#define RAMDISK_IMAGE_START_MASK (0x07FF)
-#define RAMDISK_PROMPT_FLAG (0x8000)
-#define RAMDISK_LOAD_FLAG (0x4000)
-
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
-#endif /* _ASM_M32R_SETUP_H */
diff --git a/arch/m32r/include/asm/shmparam.h b/arch/m32r/include/asm/shmparam.h
deleted file mode 100644
index 1af73d92c96d..000000000000
--- a/arch/m32r/include/asm/shmparam.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SHMPARAM_H
-#define _ASM_M32R_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
-
-#endif /* _ASM_M32R_SHMPARAM_H */
diff --git a/arch/m32r/include/asm/signal.h b/arch/m32r/include/asm/signal.h
deleted file mode 100644
index 8bf57950d21e..000000000000
--- a/arch/m32r/include/asm/signal.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SIGNAL_H
-#define _ASM_M32R_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-/* Most things should be clean enough to redefine this at will, if care
- is taken to make libc match. */
-
-#define _NSIG 64
-#define _NSIG_BPW 32
-#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t; /* at least 32 bits */
-
-typedef struct {
- unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#define __ARCH_HAS_SA_RESTORER
-#include <asm/sigcontext.h>
-
-#undef __HAVE_ARCH_SIG_BITOPS
-
-#endif /* _ASM_M32R_SIGNAL_H */
diff --git a/arch/m32r/include/asm/smp.h b/arch/m32r/include/asm/smp.h
deleted file mode 100644
index 763f22700ce6..000000000000
--- a/arch/m32r/include/asm/smp.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SMP_H
-#define _ASM_M32R_SMP_H
-
-#ifdef CONFIG_SMP
-#ifndef __ASSEMBLY__
-
-#include <linux/cpumask.h>
-#include <linux/spinlock.h>
-#include <linux/threads.h>
-#include <asm/m32r.h>
-
-#define PHYSID_ARRAY_SIZE 1
-
-struct physid_mask
-{
- unsigned long mask[PHYSID_ARRAY_SIZE];
-};
-
-typedef struct physid_mask physid_mask_t;
-
-#define physid_set(physid, map) set_bit(physid, (map).mask)
-#define physid_clear(physid, map) clear_bit(physid, (map).mask)
-#define physid_isset(physid, map) test_bit(physid, (map).mask)
-#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
-
-#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
-#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
-#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
-#define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS)
-#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
-#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
-#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
-#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
-#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
-#define physids_coerce(map) ((map).mask[0])
-
-#define physids_promote(physids) \
- ({ \
- physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
- __physid_mask.mask[0] = physids; \
- __physid_mask; \
- })
-
-#define physid_mask_of_physid(physid) \
- ({ \
- physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
- physid_set(physid, __physid_mask); \
- __physid_mask; \
- })
-
-#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
-#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
-
-extern physid_mask_t phys_cpu_present_map;
-
-/*
- * Some lowlevel functions might want to know about
- * the real CPU ID <-> CPU # mapping.
- */
-extern volatile int cpu_2_physid[NR_CPUS];
-#define cpu_to_physid(cpu_id) cpu_2_physid[cpu_id]
-
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-
-extern cpumask_t cpu_callout_map;
-
-static __inline__ int hard_smp_processor_id(void)
-{
- return (int)*(volatile long *)M32R_CPUID_PORTL;
-}
-
-static __inline__ int cpu_logical_map(int cpu)
-{
- return cpu;
-}
-
-static __inline__ int cpu_number_map(int cpu)
-{
- return cpu;
-}
-
-extern void smp_send_timer(void);
-extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int);
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-#endif /* not __ASSEMBLY__ */
-
-#define NO_PROC_ID (0xff) /* No processor magic marker */
-
-/*
- * M32R-mp IPI
- */
-#define RESCHEDULE_IPI (M32R_IRQ_IPI0-M32R_IRQ_IPI0)
-#define INVALIDATE_TLB_IPI (M32R_IRQ_IPI1-M32R_IRQ_IPI0)
-#define CALL_FUNCTION_IPI (M32R_IRQ_IPI2-M32R_IRQ_IPI0)
-#define LOCAL_TIMER_IPI (M32R_IRQ_IPI3-M32R_IRQ_IPI0)
-#define INVALIDATE_CACHE_IPI (M32R_IRQ_IPI4-M32R_IRQ_IPI0)
-#define CPU_BOOT_IPI (M32R_IRQ_IPI5-M32R_IRQ_IPI0)
-#define CALL_FUNC_SINGLE_IPI (M32R_IRQ_IPI6-M32R_IRQ_IPI0)
-
-#define IPI_SHIFT (0)
-#define NR_IPIS (8)
-
-#else /* CONFIG_SMP */
-
-#define hard_smp_processor_id() 0
-
-#endif /* CONFIG_SMP */
-
-#endif /* _ASM_M32R_SMP_H */
diff --git a/arch/m32r/include/asm/spinlock.h b/arch/m32r/include/asm/spinlock.h
deleted file mode 100644
index 0189f410f8f5..000000000000
--- a/arch/m32r/include/asm/spinlock.h
+++ /dev/null
@@ -1,308 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SPINLOCK_H
-#define _ASM_M32R_SPINLOCK_H
-
-/*
- * linux/include/asm-m32r/spinlock.h
- *
- * M32R version:
- * Copyright (C) 2001, 2002 Hitoshi Yamamoto
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#include <linux/compiler.h>
-#include <linux/atomic.h>
-#include <asm/dcache_clear.h>
-#include <asm/page.h>
-#include <asm/barrier.h>
-#include <asm/processor.h>
-
-/*
- * Your basic SMP spinlocks, allowing only a single CPU anywhere
- *
- * (the type definitions are in asm/spinlock_types.h)
- *
- * Simple spin lock operations. There are two variants, one clears IRQ's
- * on the local processor, one does not.
- *
- * We make no fairness assumptions. They have a cost.
- */
-
-#define arch_spin_is_locked(x) (*(volatile int *)(&(x)->slock) <= 0)
-
-/**
- * arch_spin_trylock - Try spin lock and return a result
- * @lock: Pointer to the lock variable
- *
- * arch_spin_trylock() tries to get the lock and returns a result.
- * On the m32r, the result value is 1 (= Success) or 0 (= Failure).
- */
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int oldval;
- unsigned long tmp1, tmp2;
-
- /*
- * lock->slock : =1 : unlock
- * : <=0 : lock
- * {
- * oldval = lock->slock; <--+ need atomic operation
- * lock->slock = 0; <--+
- * }
- */
- __asm__ __volatile__ (
- "# arch_spin_trylock \n\t"
- "ldi %1, #0; \n\t"
- "mvfc %2, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%3")
- "lock %0, @%3; \n\t"
- "unlock %1, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- : "=&r" (oldval), "=&r" (tmp1), "=&r" (tmp2)
- : "r" (&lock->slock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-
- return (oldval > 0);
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- unsigned long tmp0, tmp1;
-
- /*
- * lock->slock : =1 : unlock
- * : <=0 : lock
- *
- * for ( ; ; ) {
- * lock->slock -= 1; <-- need atomic operation
- * if (lock->slock == 0) break;
- * for ( ; lock->slock <= 0 ; );
- * }
- */
- __asm__ __volatile__ (
- "# arch_spin_lock \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "mvfc %1, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #-1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- "bltz %0, 2f; \n\t"
- LOCK_SECTION_START(".balign 4 \n\t")
- ".fillinsn \n"
- "2: \n\t"
- "ld %0, @%2; \n\t"
- "bgtz %0, 1b; \n\t"
- "bra 2b; \n\t"
- LOCK_SECTION_END
- : "=&r" (tmp0), "=&r" (tmp1)
- : "r" (&lock->slock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- mb();
- lock->slock = 1;
-}
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- *
- * On x86, we implement read-write locks as a 32-bit counter
- * with the high bit (sign) being the "contended" bit.
- *
- * The inline assembly is non-obvious. Think about it.
- *
- * Changed to use the same technique as rw semaphores. See
- * semaphore.h for details. -ben
- */
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1;
-
- /*
- * rw->lock : >0 : unlock
- * : <=0 : lock
- *
- * for ( ; ; ) {
- * rw->lock -= 1; <-- need atomic operation
- * if (rw->lock >= 0) break;
- * rw->lock += 1; <-- need atomic operation
- * for ( ; rw->lock <= 0 ; );
- * }
- */
- __asm__ __volatile__ (
- "# read_lock \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "mvfc %1, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #-1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- "bltz %0, 2f; \n\t"
- LOCK_SECTION_START(".balign 4 \n\t")
- ".fillinsn \n"
- "2: \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- ".fillinsn \n"
- "3: \n\t"
- "ld %0, @%2; \n\t"
- "bgtz %0, 1b; \n\t"
- "bra 3b; \n\t"
- LOCK_SECTION_END
- : "=&r" (tmp0), "=&r" (tmp1)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1, tmp2;
-
- /*
- * rw->lock : =RW_LOCK_BIAS_STR : unlock
- * : !=RW_LOCK_BIAS_STR : lock
- *
- * for ( ; ; ) {
- * rw->lock -= RW_LOCK_BIAS_STR; <-- need atomic operation
- * if (rw->lock == 0) break;
- * rw->lock += RW_LOCK_BIAS_STR; <-- need atomic operation
- * for ( ; rw->lock != RW_LOCK_BIAS_STR ; ) ;
- * }
- */
- __asm__ __volatile__ (
- "# write_lock \n\t"
- "seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
- "or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "mvfc %2, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r7", "%3")
- "lock %0, @%3; \n\t"
- "sub %0, %1; \n\t"
- "unlock %0, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- "bnez %0, 2f; \n\t"
- LOCK_SECTION_START(".balign 4 \n\t")
- ".fillinsn \n"
- "2: \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r7", "%3")
- "lock %0, @%3; \n\t"
- "add %0, %1; \n\t"
- "unlock %0, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- ".fillinsn \n"
- "3: \n\t"
- "ld %0, @%3; \n\t"
- "beq %0, %1, 1b; \n\t"
- "bra 3b; \n\t"
- LOCK_SECTION_END
- : "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r7"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1;
-
- __asm__ __volatile__ (
- "# read_unlock \n\t"
- "mvfc %1, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r6", "%2")
- "lock %0, @%2; \n\t"
- "addi %0, #1; \n\t"
- "unlock %0, @%2; \n\t"
- "mvtc %1, psw; \n\t"
- : "=&r" (tmp0), "=&r" (tmp1)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r6"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- unsigned long tmp0, tmp1, tmp2;
-
- __asm__ __volatile__ (
- "# write_unlock \n\t"
- "seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
- "or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
- "mvfc %2, psw; \n\t"
- "clrpsw #0x40 -> nop; \n\t"
- DCACHE_CLEAR("%0", "r7", "%3")
- "lock %0, @%3; \n\t"
- "add %0, %1; \n\t"
- "unlock %0, @%3; \n\t"
- "mvtc %2, psw; \n\t"
- : "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
- : "r" (&rw->lock)
- : "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r7"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
- atomic_t *count = (atomic_t*)lock;
- if (atomic_dec_return(count) >= 0)
- return 1;
- atomic_inc(count);
- return 0;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
- atomic_t *count = (atomic_t *)lock;
- if (atomic_sub_and_test(RW_LOCK_BIAS, count))
- return 1;
- atomic_add(RW_LOCK_BIAS, count);
- return 0;
-}
-
-#endif /* _ASM_M32R_SPINLOCK_H */
diff --git a/arch/m32r/include/asm/spinlock_types.h b/arch/m32r/include/asm/spinlock_types.h
deleted file mode 100644
index bb0d17b64198..000000000000
--- a/arch/m32r/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SPINLOCK_TYPES_H
-#define _ASM_M32R_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
- volatile int slock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 1 }
-
-typedef struct {
- volatile int lock;
-} arch_rwlock_t;
-
-#define RW_LOCK_BIAS 0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
-
-#endif /* _ASM_M32R_SPINLOCK_TYPES_H */
diff --git a/arch/m32r/include/asm/string.h b/arch/m32r/include/asm/string.h
deleted file mode 100644
index a9ea3b6c3e5a..000000000000
--- a/arch/m32r/include/asm/string.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_STRING_H
-#define _ASM_M32R_STRING_H
-
-#define __HAVE_ARCH_STRLEN
-extern size_t strlen(const char * s);
-
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *__s, int __c, size_t __count);
-
-#endif /* _ASM_M32R_STRING_H */
diff --git a/arch/m32r/include/asm/switch_to.h b/arch/m32r/include/asm/switch_to.h
deleted file mode 100644
index 4b262f7a8fe9..000000000000
--- a/arch/m32r/include/asm/switch_to.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _ASM_M32R_SWITCH_TO_H
-#define _ASM_M32R_SWITCH_TO_H
-
-/*
- * switch_to(prev, next) should switch from task `prev' to `next'
- * `prev' will never be the same as `next'.
- *
- * `next' and `prev' should be struct task_struct, but it isn't always defined
- */
-
-#if defined(CONFIG_FRAME_POINTER) || \
- !defined(CONFIG_SCHED_OMIT_FRAME_POINTER)
-#define M32R_PUSH_FP " push fp\n"
-#define M32R_POP_FP " pop fp\n"
-#else
-#define M32R_PUSH_FP ""
-#define M32R_POP_FP ""
-#endif
-
-#define switch_to(prev, next, last) do { \
- __asm__ __volatile__ ( \
- " seth lr, #high(1f) \n" \
- " or3 lr, lr, #low(1f) \n" \
- " st lr, @%4 ; store old LR \n" \
- " ld lr, @%5 ; load new LR \n" \
- M32R_PUSH_FP \
- " st sp, @%2 ; store old SP \n" \
- " ld sp, @%3 ; load new SP \n" \
- " push %1 ; store `prev' on new stack \n" \
- " jmp lr \n" \
- " .fillinsn \n" \
- "1: \n" \
- " pop %0 ; restore `__last' from new stack \n" \
- M32R_POP_FP \
- : "=r" (last) \
- : "0" (prev), \
- "r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \
- "r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \
- : "memory", "lr" \
- ); \
-} while(0)
-
-#endif /* _ASM_M32R_SWITCH_TO_H */
diff --git a/arch/m32r/include/asm/syscall.h b/arch/m32r/include/asm/syscall.h
deleted file mode 100644
index 22c8516d3c18..000000000000
--- a/arch/m32r/include/asm/syscall.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_SYSCALL_H
-#define _ASM_M32R_SYSCALL_H
-
-/* Definitions for the system call vector. */
-#define SYSCALL_VECTOR "2"
-#define SYSCALL_VECTOR_ADDRESS "0xa0"
-
-#endif /* _ASM_M32R_SYSCALL_H */
diff --git a/arch/m32r/include/asm/termios.h b/arch/m32r/include/asm/termios.h
deleted file mode 100644
index 40274b89cea5..000000000000
--- a/arch/m32r/include/asm/termios.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32R_TERMIOS_H
-#define _M32R_TERMIOS_H
-
-#include <linux/module.h>
-#include <uapi/asm/termios.h>
-
-/* intr=^C quit=^\ erase=del kill=^U
- eof=^D vtime=\0 vmin=\1 sxtc=\0
- start=^Q stop=^S susp=^Z eol=\0
- reprint=^R discard=^U werase=^W lnext=^V
- eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
- unsigned short __tmp; \
- get_user(__tmp,&(termio)->x); \
- *(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
- SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
- copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
- put_user((termios)->c_iflag, &(termio)->c_iflag); \
- put_user((termios)->c_oflag, &(termio)->c_oflag); \
- put_user((termios)->c_cflag, &(termio)->c_cflag); \
- put_user((termios)->c_lflag, &(termio)->c_lflag); \
- put_user((termios)->c_line, &(termio)->c_line); \
- copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif /* _M32R_TERMIOS_H */
diff --git a/arch/m32r/include/asm/thread_info.h b/arch/m32r/include/asm/thread_info.h
deleted file mode 100644
index ba00f1032587..000000000000
--- a/arch/m32r/include/asm/thread_info.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_THREAD_INFO_H
-#define _ASM_M32R_THREAD_INFO_H
-
-/* thread_info.h: m32r low-level thread information
- *
- * Copyright (C) 2002 David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#endif
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must also be changed
- */
-#ifndef __ASSEMBLY__
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- unsigned long status; /* thread-synchronous flags */
- __u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
-
- mm_segment_t addr_limit; /* thread address space:
- 0-0xBFFFFFFF for user-thread
- 0-0xFFFFFFFF for kernel-thread
- */
-
- __u8 supervisor_stack[0];
-};
-
-#endif /* !__ASSEMBLY__ */
-
-#define THREAD_SIZE (PAGE_SIZE << 1)
-#define THREAD_SIZE_ORDER 1
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
-
- __asm__ __volatile__ (
- "ldi %0, #%1 \n\t"
- "and %0, sp \n\t"
- : "=r" (ti) : "i" (~(THREAD_SIZE - 1))
- );
-
- return ti;
-}
-
-#define TI_FLAG_FAULT_CODE_SHIFT 28
-
-static inline void set_thread_fault_code(unsigned int val)
-{
- struct thread_info *ti = current_thread_info();
- ti->flags = (ti->flags & (~0 >> (32 - TI_FLAG_FAULT_CODE_SHIFT)))
- | (val << TI_FLAG_FAULT_CODE_SHIFT);
-}
-
-static inline unsigned int get_thread_fault_code(void)
-{
- struct thread_info *ti = current_thread_info();
- return ti->flags >> TI_FLAG_FAULT_CODE_SHIFT;
-}
-
-#endif
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */
-#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
-#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal() */
-#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
-#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_USEDFPU (1<<TIF_USEDFPU)
-
-#define _TIF_WORK_MASK (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME)
-#define _TIF_ALLWORK_MASK (_TIF_WORK_MASK | _TIF_SYSCALL_TRACE)
-
-/*
- * Thread-synchronous status.
- *
- * This is different from the flags in that nobody else
- * ever touches our thread-synchronous status, so we don't
- * have to worry about atomic accesses.
- */
-#define TS_USEDFPU 0x0001 /* FPU was used by this task this quantum (SMP) */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_THREAD_INFO_H */
diff --git a/arch/m32r/include/asm/timex.h b/arch/m32r/include/asm/timex.h
deleted file mode 100644
index a4f9f852d9e6..000000000000
--- a/arch/m32r/include/asm/timex.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TIMEX_H
-#define _ASM_M32R_TIMEX_H
-
-/*
- * linux/include/asm-m32r/timex.h
- *
- * m32r architecture timex specifications
- */
-
-#define CLOCK_TICK_RATE (CONFIG_BUS_CLOCK / CONFIG_TIMER_DIVIDE)
-#define CLOCK_TICK_FACTOR 20 /* Factor of both 1000000 and CLOCK_TICK_RATE */
-
-#ifdef __KERNEL__
-/*
- * Standard way to access the cycle counter.
- * Currently only used on SMP.
- */
-
-typedef unsigned long long cycles_t;
-
-static __inline__ cycles_t get_cycles (void)
-{
- return 0;
-}
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_M32R_TIMEX_H */
diff --git a/arch/m32r/include/asm/tlb.h b/arch/m32r/include/asm/tlb.h
deleted file mode 100644
index 3576f88b6ea4..000000000000
--- a/arch/m32r/include/asm/tlb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _M32R_TLB_H
-#define _M32R_TLB_H
-
-/*
- * x86 doesn't need any special per-pte or
- * per-vma handling..
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _M32R_TLB_H */
diff --git a/arch/m32r/include/asm/tlbflush.h b/arch/m32r/include/asm/tlbflush.h
deleted file mode 100644
index f6c7237316d0..000000000000
--- a/arch/m32r/include/asm/tlbflush.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TLBFLUSH_H
-#define _ASM_M32R_TLBFLUSH_H
-
-#include <asm/m32r.h>
-
-/*
- * TLB flushing:
- *
- * - flush_tlb() flushes the current mm struct TLBs
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(vma, start, end) flushes a range of pages
- * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- */
-
-extern void local_flush_tlb_all(void);
-extern void local_flush_tlb_mm(struct mm_struct *);
-extern void local_flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void local_flush_tlb_range(struct vm_area_struct *, unsigned long,
- unsigned long);
-
-#ifndef CONFIG_SMP
-#ifdef CONFIG_MMU
-#define flush_tlb_all() local_flush_tlb_all()
-#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
-#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
-#define flush_tlb_range(vma, start, end) \
- local_flush_tlb_range(vma, start, end)
-#define flush_tlb_kernel_range(start, end) local_flush_tlb_all()
-#else /* CONFIG_MMU */
-#define flush_tlb_all() do { } while (0)
-#define flush_tlb_mm(mm) do { } while (0)
-#define flush_tlb_page(vma, vmaddr) do { } while (0)
-#define flush_tlb_range(vma, start, end) do { } while (0)
-#endif /* CONFIG_MMU */
-#else /* CONFIG_SMP */
-extern void smp_flush_tlb_all(void);
-extern void smp_flush_tlb_mm(struct mm_struct *);
-extern void smp_flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void smp_flush_tlb_range(struct vm_area_struct *, unsigned long,
- unsigned long);
-
-#define flush_tlb_all() smp_flush_tlb_all()
-#define flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
-#define flush_tlb_page(vma, page) smp_flush_tlb_page(vma, page)
-#define flush_tlb_range(vma, start, end) \
- smp_flush_tlb_range(vma, start, end)
-#define flush_tlb_kernel_range(start, end) smp_flush_tlb_all()
-#endif /* CONFIG_SMP */
-
-static __inline__ void __flush_tlb_page(unsigned long page)
-{
- unsigned int tmpreg0, tmpreg1, tmpreg2;
-
- __asm__ __volatile__ (
- "seth %0, #high(%4) \n\t"
- "st %3, @(%5, %0) \n\t"
- "ldi %1, #1 \n\t"
- "st %1, @(%6, %0) \n\t"
- "add3 %1, %0, %7 \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "ld %2, @(%6, %0) \n\t"
- "bnez %2, 1b \n\t"
- "ld %0, @%1+ \n\t"
- "ld %1, @%1 \n\t"
- "st %2, @+%0 \n\t"
- "st %2, @+%1 \n\t"
- : "=&r" (tmpreg0), "=&r" (tmpreg1), "=&r" (tmpreg2)
- : "r" (page), "i" (MMU_REG_BASE), "i" (MSVA_offset),
- "i" (MTOP_offset), "i" (MIDXI_offset)
- : "memory"
- );
-}
-
-static __inline__ void __flush_tlb_all(void)
-{
- unsigned int tmpreg0, tmpreg1;
-
- __asm__ __volatile__ (
- "seth %0, #high(%2) \n\t"
- "or3 %0, %0, #low(%2) \n\t"
- "ldi %1, #0xc \n\t"
- "st %1, @%0 \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "ld %1, @%0 \n\t"
- "bnez %1, 1b \n\t"
- : "=&r" (tmpreg0), "=&r" (tmpreg1)
- : "i" (MTOP) : "memory"
- );
-}
-
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
-
-#endif /* _ASM_M32R_TLBFLUSH_H */
diff --git a/arch/m32r/include/asm/topology.h b/arch/m32r/include/asm/topology.h
deleted file mode 100644
index ee79404e8878..000000000000
--- a/arch/m32r/include/asm/topology.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TOPOLOGY_H
-#define _ASM_M32R_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_M32R_TOPOLOGY_H */
diff --git a/arch/m32r/include/asm/types.h b/arch/m32r/include/asm/types.h
deleted file mode 100644
index fce0bf60536c..000000000000
--- a/arch/m32r/include/asm/types.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_TYPES_H
-#define _ASM_M32R_TYPES_H
-
-#include <uapi/asm/types.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-
-#define BITS_PER_LONG 32
-
-#endif /* _ASM_M32R_TYPES_H */
diff --git a/arch/m32r/include/asm/uaccess.h b/arch/m32r/include/asm/uaccess.h
deleted file mode 100644
index 9d89bc3d8181..000000000000
--- a/arch/m32r/include/asm/uaccess.h
+++ /dev/null
@@ -1,515 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UACCESS_H
-#define _ASM_M32R_UACCESS_H
-
-/*
- * linux/include/asm-m32r/uaccess.h
- *
- * M32R version.
- * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-/*
- * User space memory access functions
- */
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <linux/prefetch.h>
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-#ifdef CONFIG_MMU
-
-#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#else /* not CONFIG_MMU */
-
-#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define get_ds() (KERNEL_DS)
-
-static inline mm_segment_t get_fs(void)
-{
- return USER_DS;
-}
-
-static inline void set_fs(mm_segment_t s)
-{
-}
-
-#endif /* not CONFIG_MMU */
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-#define __addr_ok(addr) \
- ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg))
-
-/*
- * Test whether a block of memory is a valid user space address.
- * Returns 0 if the range is valid, nonzero otherwise.
- *
- * This is equivalent to the following test:
- * (u33)addr + (u33)size >= (u33)current->addr_limit.seg
- *
- * This needs 33-bit arithmetic. We have a carry...
- */
-#define __range_ok(addr, size) ({ \
- unsigned long flag, roksum; \
- __chk_user_ptr(addr); \
- asm ( \
- " cmpu %1, %1 ; clear cbit\n" \
- " addx %1, %3 ; set cbit if overflow\n" \
- " subx %0, %0\n" \
- " cmpu %4, %1\n" \
- " subx %0, %5\n" \
- : "=&r" (flag), "=r" (roksum) \
- : "1" (addr), "r" ((int)(size)), \
- "r" (current_thread_info()->addr_limit.seg), "r" (0) \
- : "cbit" ); \
- flag; })
-
-/**
- * access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
- * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- * to write to a block, it is always safe to read from it.
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns true (nonzero) if the memory block may be valid, false (zero)
- * if it is definitely invalid.
- *
- * Note that, depending on architecture, this function probably just
- * checks that the pointer is in the user space range - after calling
- * this function, memory access functions may still return -EFAULT.
- */
-#ifdef CONFIG_MMU
-#define access_ok(type, addr, size) (likely(__range_ok(addr, size) == 0))
-#else
-static inline int access_ok(int type, const void *addr, unsigned long size)
-{
- unsigned long val = (unsigned long)addr;
-
- return ((val >= memory_start) && ((val + size) < memory_end));
-}
-#endif /* CONFIG_MMU */
-
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- *
- * This gets kind of ugly. We want to return _two_ values in "get_user()"
- * and yet we don't want to do any pointers, because that is too much
- * of a performance impact. Thus we have a few rather ugly macros here,
- * and hide all the uglyness from the user.
- *
- * The "__xxx" versions of the user access functions are versions that
- * do not verify the address space, that must have been done previously
- * with a separate "access_ok()" call (this is used when we do multiple
- * accesses to the same area of user memory).
- */
-
-/* Careful: we have to cast the result to the type of the pointer for sign
- reasons */
-/**
- * get_user: - Get a simple variable from user space.
- * @x: Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple variable from user space to kernel
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define get_user(x, ptr) \
- __get_user_check((x), (ptr), sizeof(*(ptr)))
-
-/**
- * put_user: - Write a simple value into user space.
- * @x: Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple value from kernel space to user
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define put_user(x, ptr) \
- __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-/**
- * __get_user: - Get a simple variable from user space, with less checking.
- * @x: Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple variable from user space to kernel
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define __get_user(x, ptr) \
- __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-#define __get_user_nocheck(x, ptr, size) \
-({ \
- long __gu_err = 0; \
- unsigned long __gu_val = 0; \
- might_fault(); \
- __get_user_size(__gu_val, (ptr), (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-#define __get_user_check(x, ptr, size) \
-({ \
- long __gu_err = -EFAULT; \
- unsigned long __gu_val = 0; \
- const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
- might_fault(); \
- if (access_ok(VERIFY_READ, __gu_addr, size)) \
- __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-extern long __get_user_bad(void);
-
-#define __get_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- __chk_user_ptr(ptr); \
- switch (size) { \
- case 1: __get_user_asm(x, ptr, retval, "ub"); break; \
- case 2: __get_user_asm(x, ptr, retval, "uh"); break; \
- case 4: __get_user_asm(x, ptr, retval, ""); break; \
- default: (x) = __get_user_bad(); \
- } \
-} while (0)
-
-#define __get_user_asm(x, addr, err, itype) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: ld"itype" %1,@%2\n" \
- " .fillinsn\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "3: ldi %0,%3\n" \
- " seth r14,#high(2b)\n" \
- " or3 r14,r14,#low(2b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,3b\n" \
- ".previous" \
- : "=&r" (err), "=&r" (x) \
- : "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-
-/**
- * __put_user: - Write a simple value into user space, with less checking.
- * @x: Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple value from kernel space to user
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define __put_user(x, ptr) \
- __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-
-#define __put_user_nocheck(x, ptr, size) \
-({ \
- long __pu_err; \
- might_fault(); \
- __put_user_size((x), (ptr), (size), __pu_err); \
- __pu_err; \
-})
-
-
-#define __put_user_check(x, ptr, size) \
-({ \
- long __pu_err = -EFAULT; \
- __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
- might_fault(); \
- if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
- __put_user_size((x), __pu_addr, (size), __pu_err); \
- __pu_err; \
-})
-
-#if defined(__LITTLE_ENDIAN__)
-#define __put_user_u64(x, addr, err) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: st %L1,@%2\n" \
- " .fillinsn\n" \
- "2: st %H1,@(4,%2)\n" \
- " .fillinsn\n" \
- "3:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "4: ldi %0,%3\n" \
- " seth r14,#high(3b)\n" \
- " or3 r14,r14,#low(3b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,4b\n" \
- " .long 2b,4b\n" \
- ".previous" \
- : "=&r" (err) \
- : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-
-#elif defined(__BIG_ENDIAN__)
-#define __put_user_u64(x, addr, err) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: st %H1,@%2\n" \
- " .fillinsn\n" \
- "2: st %L1,@(4,%2)\n" \
- " .fillinsn\n" \
- "3:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "4: ldi %0,%3\n" \
- " seth r14,#high(3b)\n" \
- " or3 r14,r14,#low(3b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,4b\n" \
- " .long 2b,4b\n" \
- ".previous" \
- : "=&r" (err) \
- : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-#else
-#error no endian defined
-#endif
-
-extern void __put_user_bad(void);
-
-#define __put_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- __chk_user_ptr(ptr); \
- switch (size) { \
- case 1: __put_user_asm(x, ptr, retval, "b"); break; \
- case 2: __put_user_asm(x, ptr, retval, "h"); break; \
- case 4: __put_user_asm(x, ptr, retval, ""); break; \
- case 8: __put_user_u64((__typeof__(*ptr))(x), ptr, retval); break;\
- default: __put_user_bad(); \
- } \
-} while (0)
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-#define __put_user_asm(x, addr, err, itype) \
- __asm__ __volatile__( \
- " .fillinsn\n" \
- "1: st"itype" %1,@%2\n" \
- " .fillinsn\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "3: ldi %0,%3\n" \
- " seth r14,#high(2b)\n" \
- " or3 r14,r14,#low(2b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b,3b\n" \
- ".previous" \
- : "=&r" (err) \
- : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err) \
- : "r14", "memory")
-
-/*
- * Here we special-case 1, 2 and 4-byte copy_*_user invocations. On a fault
- * we return the initial request size (1, 2 or 4), as copy_*_user should do.
- * If a store crosses a page boundary and gets a fault, the m32r will not write
- * anything, so this is accurate.
- */
-
-/*
- * Copy To/From Userspace
- */
-
-/* Generic arbitrary sized copy. */
-/* Return the number of bytes NOT copied. */
-#define __copy_user(to, from, size) \
-do { \
- unsigned long __dst, __src, __c; \
- __asm__ __volatile__ ( \
- " mv r14, %0\n" \
- " or r14, %1\n" \
- " beq %0, %1, 9f\n" \
- " beqz %2, 9f\n" \
- " and3 r14, r14, #3\n" \
- " bnez r14, 2f\n" \
- " and3 %2, %2, #3\n" \
- " beqz %3, 2f\n" \
- " addi %0, #-4 ; word_copy \n" \
- " .fillinsn\n" \
- "0: ld r14, @%1+\n" \
- " addi %3, #-1\n" \
- " .fillinsn\n" \
- "1: st r14, @+%0\n" \
- " bnez %3, 0b\n" \
- " beqz %2, 9f\n" \
- " addi %0, #4\n" \
- " .fillinsn\n" \
- "2: ldb r14, @%1 ; byte_copy \n" \
- " .fillinsn\n" \
- "3: stb r14, @%0\n" \
- " addi %1, #1\n" \
- " addi %2, #-1\n" \
- " addi %0, #1\n" \
- " bnez %2, 2b\n" \
- " .fillinsn\n" \
- "9:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "5: addi %3, #1\n" \
- " addi %1, #-4\n" \
- " .fillinsn\n" \
- "6: slli %3, #2\n" \
- " add %2, %3\n" \
- " addi %0, #4\n" \
- " .fillinsn\n" \
- "7: seth r14, #high(9b)\n" \
- " or3 r14, r14, #low(9b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,6b\n" \
- " .long 1b,5b\n" \
- " .long 2b,9b\n" \
- " .long 3b,9b\n" \
- ".previous\n" \
- : "=&r" (__dst), "=&r" (__src), "=&r" (size), \
- "=&r" (__c) \
- : "0" (to), "1" (from), "2" (size), "3" (size / 4) \
- : "r14", "memory"); \
-} while (0)
-
-/* We let the __ versions of copy_from/to_user inline, because they're often
- * used in fast paths and have only a small space overhead.
- */
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- prefetchw(to);
- __copy_user(to, from, n);
- return n;
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- prefetch(from);
- __copy_user(to, from, n);
- return n;
-}
-
-long __must_check strncpy_from_user(char *dst, const char __user *src,
- long count);
-
-/**
- * __clear_user: - Zero a block of memory in user space, with less checking.
- * @to: Destination address, in user space.
- * @n: Number of bytes to zero.
- *
- * Zero a block of memory in user space. Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-unsigned long __clear_user(void __user *mem, unsigned long len);
-
-/**
- * clear_user: - Zero a block of memory in user space.
- * @to: Destination address, in user space.
- * @n: Number of bytes to zero.
- *
- * Zero a block of memory in user space. Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-unsigned long clear_user(void __user *mem, unsigned long len);
-
-long strnlen_user(const char __user *str, long n);
-
-#endif /* _ASM_M32R_UACCESS_H */
diff --git a/arch/m32r/include/asm/ucontext.h b/arch/m32r/include/asm/ucontext.h
deleted file mode 100644
index 5f9de3736624..000000000000
--- a/arch/m32r/include/asm/ucontext.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UCONTEXT_H
-#define _ASM_M32R_UCONTEXT_H
-
-struct ucontext {
- unsigned long uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-#endif /* _ASM_M32R_UCONTEXT_H */
diff --git a/arch/m32r/include/asm/unaligned.h b/arch/m32r/include/asm/unaligned.h
deleted file mode 100644
index 5981361672f9..000000000000
--- a/arch/m32r/include/asm/unaligned.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UNALIGNED_H
-#define _ASM_M32R_UNALIGNED_H
-
-#if defined(__LITTLE_ENDIAN__)
-# include <linux/unaligned/le_memmove.h>
-# include <linux/unaligned/be_byteshift.h>
-# include <linux/unaligned/generic.h>
-# define get_unaligned __get_unaligned_le
-# define put_unaligned __put_unaligned_le
-#else
-# include <linux/unaligned/be_memmove.h>
-# include <linux/unaligned/le_byteshift.h>
-# include <linux/unaligned/generic.h>
-# define get_unaligned __get_unaligned_be
-# define put_unaligned __put_unaligned_be
-#endif
-
-#endif /* _ASM_M32R_UNALIGNED_H */
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
deleted file mode 100644
index dee4c196972e..000000000000
--- a/arch/m32r/include/asm/unistd.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_UNISTD_H
-#define _ASM_M32R_UNISTD_H
-
-#include <uapi/asm/unistd.h>
-
-
-#define NR_syscalls 326
-
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_CLONE
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-
-#define __IGNORE_lchown
-#define __IGNORE_setuid
-#define __IGNORE_getuid
-#define __IGNORE_setgid
-#define __IGNORE_getgid
-#define __IGNORE_geteuid
-#define __IGNORE_getegid
-#define __IGNORE_fcntl
-#define __IGNORE_setreuid
-#define __IGNORE_setregid
-#define __IGNORE_getrlimit
-#define __IGNORE_getgroups
-#define __IGNORE_setgroups
-#define __IGNORE_select
-#define __IGNORE_mmap
-#define __IGNORE_fchown
-#define __IGNORE_setfsuid
-#define __IGNORE_setfsgid
-#define __IGNORE_setresuid
-#define __IGNORE_getresuid
-#define __IGNORE_setresgid
-#define __IGNORE_getresgid
-#define __IGNORE_chown
-
-#endif /* _ASM_M32R_UNISTD_H */
diff --git a/arch/m32r/include/asm/user.h b/arch/m32r/include/asm/user.h
deleted file mode 100644
index 489b60d4aec2..000000000000
--- a/arch/m32r/include/asm/user.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_USER_H
-#define _ASM_M32R_USER_H
-
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <asm/page.h>
-
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd).
- *
- * The actual file contents are as follows:
- * UPAGE: 1 page consisting of a user struct that tells gdb
- * what is present in the file. Directly after this is a
- * copy of the task_struct, which is currently not used by gdb,
- * but it may come in handy at some point. All of the registers
- * are stored as part of the upage. The upage should always be
- * only one page.
- * DATA: The data area is stored. We use current->end_text to
- * current->brk to pick up all of the user variables, plus any memory
- * that may have been sbrk'ed. No attempt is made to determine if a
- * page is demand-zero or if a page is totally unused, we just cover
- * the entire range. All of the addresses are rounded in such a way
- * that an integral number of pages is written.
- * STACK: We need the stack information in order to get a meaningful
- * backtrace. We need to write the data from usp to
- * current->start_stack, so we round each of these off in order to be
- * able to write an integer number of pages.
- */
-
-struct user {
- struct pt_regs regs; /* entire machine state */
- size_t u_tsize; /* text size (pages) */
- size_t u_dsize; /* data size (pages) */
- size_t u_ssize; /* stack size (pages) */
- unsigned long start_code; /* text starting address */
- unsigned long start_data; /* data starting address */
- unsigned long start_stack; /* stack starting address */
- long int signal; /* signal causing core dump */
- unsigned long u_ar0; /* help gdb find registers */
- unsigned long magic; /* identifies a core file */
- char u_comm[32]; /* user command name */
-};
-
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_DATA_START_ADDR (u.start_data)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* _ASM_M32R_USER_H */
diff --git a/arch/m32r/include/asm/vga.h b/arch/m32r/include/asm/vga.h
deleted file mode 100644
index 783d5bf779c2..000000000000
--- a/arch/m32r/include/asm/vga.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_VGA_H
-#define _ASM_M32R_VGA_H
-
-/*
- * Access to VGA videoram
- *
- * (c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-/*
- * On the PC, we can just recalculate addresses and then
- * access the videoram directly without any black magic.
- */
-
-#define VGA_MAP_MEM(x,s) (unsigned long)phys_to_virt(x)
-
-#define vga_readb(x) (*(x))
-#define vga_writeb(x,y) (*(y) = (x))
-
-#endif /* _ASM_M32R_VGA_H */
diff --git a/arch/m32r/include/asm/xor.h b/arch/m32r/include/asm/xor.h
deleted file mode 100644
index a4d546752c77..000000000000
--- a/arch/m32r/include/asm/xor.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_M32R_XOR_H
-#define _ASM_M32R_XOR_H
-
-#include <asm-generic/xor.h>
-
-#endif /* _ASM_M32R_XOR_H */
diff --git a/arch/m32r/include/uapi/asm/Kbuild b/arch/m32r/include/uapi/asm/Kbuild
deleted file mode 100644
index c3df55aeefe7..000000000000
--- a/arch/m32r/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,7 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += bpf_perf_event.h
-generic-y += kvm_para.h
-generic-y += poll.h
-generic-y += siginfo.h
diff --git a/arch/m32r/include/uapi/asm/auxvec.h b/arch/m32r/include/uapi/asm/auxvec.h
deleted file mode 100644
index f76dcc860fae..000000000000
--- a/arch/m32r/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_M32R__AUXVEC_H
-#define _ASM_M32R__AUXVEC_H
-
-#endif /* _ASM_M32R__AUXVEC_H */
diff --git a/arch/m32r/include/uapi/asm/bitsperlong.h b/arch/m32r/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index 76da34b10f59..000000000000
--- a/arch/m32r/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/m32r/include/uapi/asm/byteorder.h b/arch/m32r/include/uapi/asm/byteorder.h
deleted file mode 100644
index 9b4a8ba483cd..000000000000
--- a/arch/m32r/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_BYTEORDER_H
-#define _ASM_M32R_BYTEORDER_H
-
-#if defined(__LITTLE_ENDIAN__)
-# include <linux/byteorder/little_endian.h>
-#else
-# include <linux/byteorder/big_endian.h>
-#endif
-
-#endif /* _ASM_M32R_BYTEORDER_H */
diff --git a/arch/m32r/include/uapi/asm/errno.h b/arch/m32r/include/uapi/asm/errno.h
deleted file mode 100644
index ab38ef607882..000000000000
--- a/arch/m32r/include/uapi/asm/errno.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_ERRNO_H
-#define _ASM_M32R_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif /* _ASM_M32R_ERRNO_H */
diff --git a/arch/m32r/include/uapi/asm/fcntl.h b/arch/m32r/include/uapi/asm/fcntl.h
deleted file mode 100644
index a77648c505d1..000000000000
--- a/arch/m32r/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/fcntl.h>
diff --git a/arch/m32r/include/uapi/asm/ioctl.h b/arch/m32r/include/uapi/asm/ioctl.h
deleted file mode 100644
index b809c4566e5f..000000000000
--- a/arch/m32r/include/uapi/asm/ioctl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ioctl.h>
diff --git a/arch/m32r/include/uapi/asm/ioctls.h b/arch/m32r/include/uapi/asm/ioctls.h
deleted file mode 100644
index 31da4c3bab94..000000000000
--- a/arch/m32r/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ARCH_M32R_IOCTLS_H__
-#define __ARCH_M32R_IOCTLS_H__
-
-#include <asm-generic/ioctls.h>
-
-#endif /* __ARCH_M32R_IOCTLS_H__ */
diff --git a/arch/m32r/include/uapi/asm/ipcbuf.h b/arch/m32r/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 90d6445a14df..000000000000
--- a/arch/m32r/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/m32r/include/uapi/asm/mman.h b/arch/m32r/include/uapi/asm/mman.h
deleted file mode 100644
index 8eebf89f5ab1..000000000000
--- a/arch/m32r/include/uapi/asm/mman.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/mman.h>
diff --git a/arch/m32r/include/uapi/asm/msgbuf.h b/arch/m32r/include/uapi/asm/msgbuf.h
deleted file mode 100644
index 4386ff2735ba..000000000000
--- a/arch/m32r/include/uapi/asm/msgbuf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_MSGBUF_H
-#define _ASM_M32R_MSGBUF_H
-
-/*
- * The msqid64_ds structure for m32r architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
- struct ipc64_perm msg_perm;
- __kernel_time_t msg_stime; /* last msgsnd time */
- unsigned long __unused1;
- __kernel_time_t msg_rtime; /* last msgrcv time */
- unsigned long __unused2;
- __kernel_time_t msg_ctime; /* last change time */
- unsigned long __unused3;
- unsigned long msg_cbytes; /* current number of bytes on queue */
- unsigned long msg_qnum; /* number of messages in queue */
- unsigned long msg_qbytes; /* max number of bytes on queue */
- __kernel_pid_t msg_lspid; /* pid of last msgsnd */
- __kernel_pid_t msg_lrpid; /* last receive pid */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-#endif /* _ASM_M32R_MSGBUF_H */
diff --git a/arch/m32r/include/uapi/asm/param.h b/arch/m32r/include/uapi/asm/param.h
deleted file mode 100644
index 0bff6d6133f5..000000000000
--- a/arch/m32r/include/uapi/asm/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_PARAM_H
-#define _ASM_M32R_PARAM_H
-
-#include <asm-generic/param.h>
-
-#endif /* _ASM_M32R_PARAM_H */
-
diff --git a/arch/m32r/include/uapi/asm/posix_types.h b/arch/m32r/include/uapi/asm/posix_types.h
deleted file mode 100644
index 63316fcb1b57..000000000000
--- a/arch/m32r/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_POSIX_TYPES_H
-#define _ASM_M32R_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _ASM_M32R_POSIX_TYPES_H */
diff --git a/arch/m32r/include/uapi/asm/ptrace.h b/arch/m32r/include/uapi/asm/ptrace.h
deleted file mode 100644
index 99aec86cf5c0..000000000000
--- a/arch/m32r/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * linux/include/asm-m32r/ptrace.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * M32R version:
- * Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-#ifndef _UAPI_ASM_M32R_PTRACE_H
-#define _UAPI_ASM_M32R_PTRACE_H
-
-
-/* 0 - 13 are integer registers (general purpose registers). */
-#define PT_R4 0
-#define PT_R5 1
-#define PT_R6 2
-#define PT_REGS 3
-#define PT_R0 4
-#define PT_R1 5
-#define PT_R2 6
-#define PT_R3 7
-#define PT_R7 8
-#define PT_R8 9
-#define PT_R9 10
-#define PT_R10 11
-#define PT_R11 12
-#define PT_R12 13
-#define PT_SYSCNR 14
-#define PT_R13 PT_FP
-#define PT_R14 PT_LR
-#define PT_R15 PT_SP
-
-/* processor status and miscellaneous context registers. */
-#define PT_ACC0H 15
-#define PT_ACC0L 16
-#define PT_ACC1H 17 /* ISA_DSP_LEVEL2 only */
-#define PT_ACC1L 18 /* ISA_DSP_LEVEL2 only */
-#define PT_PSW 19
-#define PT_BPC 20
-#define PT_BBPSW 21
-#define PT_BBPC 22
-#define PT_SPU 23
-#define PT_FP 24
-#define PT_LR 25
-#define PT_SPI 26
-#define PT_ORIGR0 27
-
-/* virtual pt_reg entry for gdb */
-#define PT_PC 30
-#define PT_CBR 31
-#define PT_EVB 32
-
-
-/* Control registers. */
-#define SPR_CR0 PT_PSW
-#define SPR_CR1 PT_CBR /* read only */
-#define SPR_CR2 PT_SPI
-#define SPR_CR3 PT_SPU
-#define SPR_CR4
-#define SPR_CR5 PT_EVB /* part of M32R/E, M32R/I core only */
-#define SPR_CR6 PT_BPC
-#define SPR_CR7
-#define SPR_CR8 PT_BBPSW
-#define SPR_CR9
-#define SPR_CR10
-#define SPR_CR11
-#define SPR_CR12
-#define SPR_CR13 PT_WR
-#define SPR_CR14 PT_BBPC
-#define SPR_CR15
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-struct pt_regs {
- /* Saved main processor registers. */
- unsigned long r4;
- unsigned long r5;
- unsigned long r6;
- struct pt_regs *pt_regs;
- unsigned long r0;
- unsigned long r1;
- unsigned long r2;
- unsigned long r3;
- unsigned long r7;
- unsigned long r8;
- unsigned long r9;
- unsigned long r10;
- unsigned long r11;
- unsigned long r12;
- long syscall_nr;
-
- /* Saved main processor status and miscellaneous context registers. */
- unsigned long acc0h;
- unsigned long acc0l;
- unsigned long acc1h; /* ISA_DSP_LEVEL2 only */
- unsigned long acc1l; /* ISA_DSP_LEVEL2 only */
- unsigned long psw;
- unsigned long bpc; /* saved PC for TRAP syscalls */
- unsigned long bbpsw;
- unsigned long bbpc;
- unsigned long spu; /* saved user stack */
- unsigned long fp;
- unsigned long lr; /* saved PC for JL syscalls */
- unsigned long spi; /* saved kernel stack */
- unsigned long orig_r0;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-
-#define PTRACE_OLDSETOPTIONS 21
-
-
-#endif /* _UAPI_ASM_M32R_PTRACE_H */
diff --git a/arch/m32r/include/uapi/asm/resource.h b/arch/m32r/include/uapi/asm/resource.h
deleted file mode 100644
index 3282f3c4a5ca..000000000000
--- a/arch/m32r/include/uapi/asm/resource.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_RESOURCE_H
-#define _ASM_M32R_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _ASM_M32R_RESOURCE_H */
diff --git a/arch/m32r/include/uapi/asm/sembuf.h b/arch/m32r/include/uapi/asm/sembuf.h
deleted file mode 100644
index de34664d8cd7..000000000000
--- a/arch/m32r/include/uapi/asm/sembuf.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SEMBUF_H
-#define _ASM_M32R_SEMBUF_H
-
-/*
- * The semid64_ds structure for m32r architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
- struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
- __kernel_time_t sem_otime; /* last semop time */
- unsigned long __unused1;
- __kernel_time_t sem_ctime; /* last change time */
- unsigned long __unused2;
- unsigned long sem_nsems; /* no. of semaphores in array */
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_M32R_SEMBUF_H */
diff --git a/arch/m32r/include/uapi/asm/setup.h b/arch/m32r/include/uapi/asm/setup.h
deleted file mode 100644
index d936a64bbafd..000000000000
--- a/arch/m32r/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_M32R_SETUP_H
-#define _UAPI_ASM_M32R_SETUP_H
-
-/*
- * This is set up by the setup-routine at boot-time
- */
-
-#define COMMAND_LINE_SIZE 512
-
-
-#endif /* _UAPI_ASM_M32R_SETUP_H */
diff --git a/arch/m32r/include/uapi/asm/shmbuf.h b/arch/m32r/include/uapi/asm/shmbuf.h
deleted file mode 100644
index 44c2ea924829..000000000000
--- a/arch/m32r/include/uapi/asm/shmbuf.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SHMBUF_H
-#define _ASM_M32R_SHMBUF_H
-
-/*
- * The shmid64_ds structure for M32R architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
- struct ipc64_perm shm_perm; /* operation perms */
- size_t shm_segsz; /* size of segment (bytes) */
- __kernel_time_t shm_atime; /* last attach time */
- unsigned long __unused1;
- __kernel_time_t shm_dtime; /* last detach time */
- unsigned long __unused2;
- __kernel_time_t shm_ctime; /* last change time */
- unsigned long __unused3;
- __kernel_pid_t shm_cpid; /* pid of creator */
- __kernel_pid_t shm_lpid; /* pid of last operator */
- unsigned long shm_nattch; /* no. of current attaches */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-struct shminfo64 {
- unsigned long shmmax;
- unsigned long shmmin;
- unsigned long shmmni;
- unsigned long shmseg;
- unsigned long shmall;
- unsigned long __unused1;
- unsigned long __unused2;
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_M32R_SHMBUF_H */
diff --git a/arch/m32r/include/uapi/asm/sigcontext.h b/arch/m32r/include/uapi/asm/sigcontext.h
deleted file mode 100644
index cc9ee73525ff..000000000000
--- a/arch/m32r/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SIGCONTEXT_H
-#define _ASM_M32R_SIGCONTEXT_H
-
-struct sigcontext {
- /* CPU registers */
- /* Saved main processor registers. */
- unsigned long sc_r4;
- unsigned long sc_r5;
- unsigned long sc_r6;
- struct pt_regs *sc_pt_regs;
- unsigned long sc_r0;
- unsigned long sc_r1;
- unsigned long sc_r2;
- unsigned long sc_r3;
- unsigned long sc_r7;
- unsigned long sc_r8;
- unsigned long sc_r9;
- unsigned long sc_r10;
- unsigned long sc_r11;
- unsigned long sc_r12;
-
- /* Saved main processor status and miscellaneous context registers. */
- unsigned long sc_acc0h;
- unsigned long sc_acc0l;
- unsigned long sc_acc1h; /* ISA_DSP_LEVEL2 only */
- unsigned long sc_acc1l; /* ISA_DSP_LEVEL2 only */
- unsigned long sc_psw;
- unsigned long sc_bpc; /* saved PC for TRAP syscalls */
- unsigned long sc_bbpsw;
- unsigned long sc_bbpc;
- unsigned long sc_spu; /* saved user stack */
- unsigned long sc_fp;
- unsigned long sc_lr; /* saved PC for JL syscalls */
- unsigned long sc_spi; /* saved kernel stack */
-
- unsigned long oldmask;
-};
-
-#endif /* _ASM_M32R_SIGCONTEXT_H */
diff --git a/arch/m32r/include/uapi/asm/signal.h b/arch/m32r/include/uapi/asm/signal.h
deleted file mode 100644
index c2ac3417fb98..000000000000
--- a/arch/m32r/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_M32R_SIGNAL_H
-#define _UAPI_ASM_M32R_SIGNAL_H
-
-#include <linux/types.h>
-#include <linux/time.h>
-#include <linux/compiler.h>
-
-/* Avoid too many header ordering problems. */
-struct siginfo;
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-#define NSIG 32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP 1
-#define SIGINT 2
-#define SIGQUIT 3
-#define SIGILL 4
-#define SIGTRAP 5
-#define SIGABRT 6
-#define SIGIOT 6
-#define SIGBUS 7
-#define SIGFPE 8
-#define SIGKILL 9
-#define SIGUSR1 10
-#define SIGSEGV 11
-#define SIGUSR2 12
-#define SIGPIPE 13
-#define SIGALRM 14
-#define SIGTERM 15
-#define SIGSTKFLT 16
-#define SIGCHLD 17
-#define SIGCONT 18
-#define SIGSTOP 19
-#define SIGTSTP 20
-#define SIGTTIN 21
-#define SIGTTOU 22
-#define SIGURG 23
-#define SIGXCPU 24
-#define SIGXFSZ 25
-#define SIGVTALRM 26
-#define SIGPROF 27
-#define SIGWINCH 28
-#define SIGIO 29
-#define SIGPOLL SIGIO
-/*
-#define SIGLOST 29
-*/
-#define SIGPWR 30
-#define SIGSYS 31
-#define SIGUNUSED 31
-
-/* These should not be considered constants from userland. */
-#define SIGRTMIN 32
-#define SIGRTMAX _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP 0x00000001u
-#define SA_NOCLDWAIT 0x00000002u
-#define SA_SIGINFO 0x00000004u
-#define SA_ONSTACK 0x08000000u
-#define SA_RESTART 0x10000000u
-#define SA_NODEFER 0x40000000u
-#define SA_RESETHAND 0x80000000u
-
-#define SA_NOMASK SA_NODEFER
-#define SA_ONESHOT SA_RESETHAND
-
-#define SA_RESTORER 0x04000000
-
-#define MINSIGSTKSZ 2048
-#define SIGSTKSZ 8192
-
-#include <asm-generic/signal-defs.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-struct sigaction {
- union {
- __sighandler_t _sa_handler;
- void (*_sa_sigaction)(int, struct siginfo *, void *);
- } _u;
- sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void);
-};
-
-#define sa_handler _u._sa_handler
-#define sa_sigaction _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
- void __user *ss_sp;
- int ss_flags;
- size_t ss_size;
-} stack_t;
-
-
-#endif /* _UAPI_ASM_M32R_SIGNAL_H */
diff --git a/arch/m32r/include/uapi/asm/socket.h b/arch/m32r/include/uapi/asm/socket.h
deleted file mode 100644
index cf5018e82c3d..000000000000
--- a/arch/m32r/include/uapi/asm/socket.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SOCKET_H
-#define _ASM_M32R_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockoptions(2) */
-#define SOL_SOCKET 1
-
-#define SO_DEBUG 1
-#define SO_REUSEADDR 2
-#define SO_TYPE 3
-#define SO_ERROR 4
-#define SO_DONTROUTE 5
-#define SO_BROADCAST 6
-#define SO_SNDBUF 7
-#define SO_RCVBUF 8
-#define SO_SNDBUFFORCE 32
-#define SO_RCVBUFFORCE 33
-#define SO_KEEPALIVE 9
-#define SO_OOBINLINE 10
-#define SO_NO_CHECK 11
-#define SO_PRIORITY 12
-#define SO_LINGER 13
-#define SO_BSDCOMPAT 14
-#define SO_REUSEPORT 15
-#define SO_PASSCRED 16
-#define SO_PEERCRED 17
-#define SO_RCVLOWAT 18
-#define SO_SNDLOWAT 19
-#define SO_RCVTIMEO 20
-#define SO_SNDTIMEO 21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION 22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
-#define SO_SECURITY_ENCRYPTION_NETWORK 24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER 26
-#define SO_DETACH_FILTER 27
-#define SO_GET_FILTER SO_ATTACH_FILTER
-
-#define SO_PEERNAME 28
-#define SO_TIMESTAMP 29
-#define SCM_TIMESTAMP SO_TIMESTAMP
-
-#define SO_ACCEPTCONN 30
-
-#define SO_PEERSEC 31
-#define SO_PASSSEC 34
-#define SO_TIMESTAMPNS 35
-#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
-
-#define SO_MARK 36
-
-#define SO_TIMESTAMPING 37
-#define SCM_TIMESTAMPING SO_TIMESTAMPING
-
-#define SO_PROTOCOL 38
-#define SO_DOMAIN 39
-
-#define SO_RXQ_OVFL 40
-
-#define SO_WIFI_STATUS 41
-#define SCM_WIFI_STATUS SO_WIFI_STATUS
-#define SO_PEEK_OFF 42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS 43
-
-#define SO_LOCK_FILTER 44
-
-#define SO_SELECT_ERR_QUEUE 45
-
-#define SO_BUSY_POLL 46
-
-#define SO_MAX_PACING_RATE 47
-
-#define SO_BPF_EXTENSIONS 48
-
-#define SO_INCOMING_CPU 49
-
-#define SO_ATTACH_BPF 50
-#define SO_DETACH_BPF SO_DETACH_FILTER
-
-#define SO_ATTACH_REUSEPORT_CBPF 51
-#define SO_ATTACH_REUSEPORT_EBPF 52
-
-#define SO_CNX_ADVICE 53
-
-#define SCM_TIMESTAMPING_OPT_STATS 54
-
-#define SO_MEMINFO 55
-
-#define SO_INCOMING_NAPI_ID 56
-
-#define SO_COOKIE 57
-
-#define SCM_TIMESTAMPING_PKTINFO 58
-
-#define SO_PEERGROUPS 59
-
-#define SO_ZEROCOPY 60
-
-#endif /* _ASM_M32R_SOCKET_H */
diff --git a/arch/m32r/include/uapi/asm/sockios.h b/arch/m32r/include/uapi/asm/sockios.h
deleted file mode 100644
index 948229e474c5..000000000000
--- a/arch/m32r/include/uapi/asm/sockios.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SOCKIOS_H
-#define _ASM_M32R_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 0x8901
-#define SIOCSPGRP 0x8902
-#define FIOGETOWN 0x8903
-#define SIOCGPGRP 0x8904
-#define SIOCATMARK 0x8905
-#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
-#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
-
-#endif /* _ASM_M32R_SOCKIOS_H */
diff --git a/arch/m32r/include/uapi/asm/stat.h b/arch/m32r/include/uapi/asm/stat.h
deleted file mode 100644
index 0fe9f96ce8f0..000000000000
--- a/arch/m32r/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_STAT_H
-#define _ASM_M32R_STAT_H
-
-#include <asm/byteorder.h>
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-#define STAT_HAVE_NSEC 1
-
-struct stat {
- unsigned short st_dev;
- unsigned short __pad1;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned short __pad2;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long st_atime_nsec;
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad0[4];
-#define STAT64_HAS_BROKEN_ST_INO
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad3[4];
-
- long long st_size;
- unsigned long st_blksize;
-
-#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __BIG_ENDIAN : defined(__BIG_ENDIAN)
- unsigned long __pad4; /* future possible st_blocks high bits */
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
-#elif defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : defined(__LITTLE_ENDIAN)
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
- unsigned long __pad4; /* future possible st_blocks high bits */
-#else
-#error no endian defined
-#endif
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
-
- unsigned long long st_ino;
-};
-
-#endif /* _ASM_M32R_STAT_H */
diff --git a/arch/m32r/include/uapi/asm/statfs.h b/arch/m32r/include/uapi/asm/statfs.h
deleted file mode 100644
index d42ae20dbb2b..000000000000
--- a/arch/m32r/include/uapi/asm/statfs.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_STATFS_H
-#define _ASM_M32R_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif /* _ASM_M32R_STATFS_H */
diff --git a/arch/m32r/include/uapi/asm/swab.h b/arch/m32r/include/uapi/asm/swab.h
deleted file mode 100644
index 18dce47d2841..000000000000
--- a/arch/m32r/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_SWAB_H
-#define _ASM_M32R_SWAB_H
-
-#include <linux/types.h>
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __SWAB_64_THRU_32__
-#endif
-
-#endif /* _ASM_M32R_SWAB_H */
diff --git a/arch/m32r/include/uapi/asm/termbits.h b/arch/m32r/include/uapi/asm/termbits.h
deleted file mode 100644
index 6cbbae9695b4..000000000000
--- a/arch/m32r/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_M32R_TERMBITS_H
-#define _ASM_M32R_TERMBITS_H
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IUCLC 0001000
-#define IXON 0002000
-#define IXANY 0004000
-#define IXOFF 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
-
-/* c_oflag bits */
-#define OPOST 0000001
-#define OLCUC 0000002
-#define ONLCR 0000004
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-#define OFILL 0000100
-#define OFDEL 0000200
-#define NLDLY 0000400
-#define NL0 0000000
-#define NL1 0000400
-#define CRDLY 0003000
-#define CR0 0000000
-#define CR1 0001000
-#define CR2 0002000
-#define CR3 0003000
-#define TABDLY 0014000
-#define TAB0 0000000
-#define TAB1 0004000
-#define TAB2 0010000
-#define TAB3 0014000
-#define XTABS 0014000
-#define BSDLY 0020000
-#define BS0 0000000
-#define BS1 0020000
-#define VTDLY 0040000
-#define VT0 0000000
-#define VT1 0040000
-#define FFDLY 0100000
-#define FF0 0000000
-#define FF1 0100000
-
-/* c_cflag bit meaning */
-#define CBAUD 0010017
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0000060
-#define CS5 0000000
-#define CS6 0000020
-#define CS7 0000040
-#define CS8 0000060
-#define CSTOPB 0000100
-#define CREAD 0000200
-#define PARENB 0000400
-#define PARODD 0001000
-#define HUPCL 0002000
-#define CLOCAL 0004000
-#define CBAUDEX 0010000
-#define BOTHER 0010000
-#define B57600 0010001
-#define B115200 0010002
-#define B230400 0010003
-#define B460800 0010004
-#define B500000 0010005
-#define B576000 0010006
-#define B921600 0010007
-#define B1000000 0010010
-#define B1152000 0010011
-#define B1500000 0010012
-#define B2000000 0010013
-#define B2500000 0010014
-#define B3000000 0010015
-#define B3500000 0010016
-#define B4000000 0010017
-#define CIBAUD 002003600000 /** input baud rate */
-#define CTVB 004000000000 /* VisioBraille Terminal flow control */
-#define CMSPAR 010000000000 /* mark or space (stick) parity */
-#define CRTSCTS 020000000000 /* flow control */
-
-#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG 0000001
-#define ICANON 0000002
-#define XCASE 0000004
-#define ECHO 0000010
-#define ECHOE 0000020
-#define ECHOK 0000040
-#define ECHONL 0000100
-#define NOFLSH 0000200
-#define TOSTOP 0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE 0004000
-#define FLUSHO 0010000
-#define PENDIN 0040000
-#define IEXTEN 0100000
-#define EXTPROC 0200000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif /* _ASM_M32R_TERMBITS_H */
diff --git a/arch/m32r/include/uapi/asm/termios.h b/arch/m32r/include/uapi/asm/termios.h
deleted file mode 100644
index 9b80a85e83ac..000000000000
--- a/arch/m32r/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_M32R_TERMIOS_H
-#define _UAPI_M32R_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-
-#endif /* _UAPI_M32R_TERMIOS_H */
diff --git a/arch/m32r/include/uapi/asm/types.h b/arch/m32r/include/uapi/asm/types.h
deleted file mode 100644
index 9ec9d4c5ac4d..000000000000
--- a/arch/m32r/include/uapi/asm/types.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/int-ll64.h>
diff --git a/arch/m32r/include/uapi/asm/unistd.h b/arch/m32r/include/uapi/asm/unistd.h
deleted file mode 100644
index adf8666a68ef..000000000000
--- a/arch/m32r/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_M32R_UNISTD_H
-#define _UAPI_ASM_M32R_UNISTD_H
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_restart_syscall 0
-#define __NR_exit 1
-#define __NR_fork 2
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
-#define __NR_waitpid 7
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-/* 16 is unused */
-/* 17 is unused */
-/* 18 is unused */
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
-#define __NR_umount 22
-/* 23 is unused */
-/* 24 is unused */
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
-/* 28 is unused */
-#define __NR_pause 29
-#define __NR_utime 30
-/* 31 is unused */
-#define __NR_cachectl 32 /* old #define __NR_gtty 32*/
-#define __NR_access 33
-/* 34 is unused */
-/* 35 is unused */
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
-/* 44 is unused */
-#define __NR_brk 45
-/* 46 is unused */
-/* 47 is unused (getgid16) */
-/* 48 is unused */
-/* 49 is unused */
-/* 50 is unused */
-#define __NR_acct 51
-#define __NR_umount2 52
-/* 53 is unused */
-#define __NR_ioctl 54
-/* 55 is unused (fcntl) */
-/* 56 is unused */
-#define __NR_setpgid 57
-/* 58 is unused */
-/* 59 is unused */
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
-/* 67 is unused */
-/* 68 is unused*/
-/* 69 is unused*/
-/* 70 is unused */
-/* 71 is unused */
-/* 72 is unused */
-/* 73 is unused */
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
-/* 76 is unused (old getrlimit) */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-/* 80 is unused */
-/* 81 is unused */
-/* 82 is unused */
-#define __NR_symlink 83
-/* 84 is unused */
-#define __NR_readlink 85
-#define __NR_uselib 86
-#define __NR_swapon 87
-#define __NR_reboot 88
-/* 89 is unused */
-/* 90 is unused */
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-/* 95 is unused */
-#define __NR_getpriority 96
-#define __NR_setpriority 97
-/* 98 is unused */
-#define __NR_statfs 99
-#define __NR_fstatfs 100
-/* 101 is unused */
-#define __NR_socketcall 102
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
-/* 109 is unused */
-/* 110 is unused */
-#define __NR_vhangup 111
-/* 112 is unused */
-/* 113 is unused */
-#define __NR_wait4 114
-#define __NR_swapoff 115
-#define __NR_sysinfo 116
-#define __NR_ipc 117
-#define __NR_fsync 118
-/* 119 is unused */
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
-/* 123 is unused */
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
-/* 126 is unused */
-/* 127 is unused */
-#define __NR_init_module 128
-#define __NR_delete_module 129
-/* 130 is unused */
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
-#define __NR_sysfs 135
-#define __NR_personality 136
-/* 137 is unused */
-/* 138 is unused */
-/* 139 is unused */
-#define __NR__llseek 140
-#define __NR_getdents 141
-#define __NR__newselect 142
-#define __NR_flock 143
-#define __NR_msync 144
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
-#define __NR_mlock 150
-#define __NR_munlock 151
-#define __NR_mlockall 152
-#define __NR_munlockall 153
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-/* 164 is unused */
-/* 165 is unused */
-#define __NR_tas 166
-/* 167 is unused */
-#define __NR_poll 168
-#define __NR_nfsservctl 169
-/* 170 is unused */
-/* 171 is unused */
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread64 180
-#define __NR_pwrite64 181
-/* 182 is unused */
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
-/* 188 is unused */
-/* 189 is unused */
-#define __NR_vfork 190
-#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_lchown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_chown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
-#define __NR_mincore 218
-#define __NR_madvise 219
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
-/* 222 is unused */
-/* 223 is unused */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
-#define __NR_set_thread_area 243
-#define __NR_get_thread_area 244
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
-#define __NR_fadvise64 250
-/* 251 is unused */
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_epoll_create 254
-#define __NR_epoll_ctl 255
-#define __NR_epoll_wait 256
-#define __NR_remap_file_pages 257
-#define __NR_set_tid_address 258
-#define __NR_timer_create 259
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
-#define __NR_statfs64 268
-#define __NR_fstatfs64 269
-#define __NR_tgkill 270
-#define __NR_utimes 271
-#define __NR_fadvise64_64 272
-#define __NR_vserver 273
-#define __NR_mbind 274
-#define __NR_get_mempolicy 275
-#define __NR_set_mempolicy 276
-#define __NR_mq_open 277
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
-#define __NR_kexec_load 283
-#define __NR_waitid 284
-/* 285 is unused */
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_ioprio_set 289
-#define __NR_ioprio_get 290
-#define __NR_inotify_init 291
-#define __NR_inotify_add_watch 292
-#define __NR_inotify_rm_watch 293
-#define __NR_migrate_pages 294
-#define __NR_openat 295
-#define __NR_mkdirat 296
-#define __NR_mknodat 297
-#define __NR_fchownat 298
-#define __NR_futimesat 299
-#define __NR_fstatat64 300
-#define __NR_unlinkat 301
-#define __NR_renameat 302
-#define __NR_linkat 303
-#define __NR_symlinkat 304
-#define __NR_readlinkat 305
-#define __NR_fchmodat 306
-#define __NR_faccessat 307
-#define __NR_pselect6 308
-#define __NR_ppoll 309
-#define __NR_unshare 310
-#define __NR_set_robust_list 311
-#define __NR_get_robust_list 312
-#define __NR_splice 313
-#define __NR_sync_file_range 314
-#define __NR_tee 315
-#define __NR_vmsplice 316
-#define __NR_move_pages 317
-#define __NR_getcpu 318
-#define __NR_epoll_pwait 319
-#define __NR_utimensat 320
-#define __NR_signalfd 321
-/* #define __NR_timerfd 322 removed */
-#define __NR_eventfd 323
-#define __NR_fallocate 324
-#define __NR_setns 325
-
-#endif /* _UAPI_ASM_M32R_UNISTD_H */
diff --git a/arch/m32r/kernel/.gitignore b/arch/m32r/kernel/.gitignore
deleted file mode 100644
index c5f676c3c224..000000000000
--- a/arch/m32r/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/m32r/kernel/Makefile b/arch/m32r/kernel/Makefile
deleted file mode 100644
index bd94dca51596..000000000000
--- a/arch/m32r/kernel/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Linux/M32R kernel.
-#
-
-extra-y := head.o vmlinux.lds
-
-obj-y := process.o entry.o traps.o align.o irq.o setup.o time.o \
- m32r_ksyms.o sys_m32r.o signal.o ptrace.o
-
-obj-$(CONFIG_SMP) += smp.o smpboot.o
-obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/m32r/kernel/align.c b/arch/m32r/kernel/align.c
deleted file mode 100644
index 2919a6647aff..000000000000
--- a/arch/m32r/kernel/align.c
+++ /dev/null
@@ -1,585 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * align.c - address exception handler for M32R
- *
- * Copyright (c) 2003 Hitoshi Yamamoto
- */
-
-#include <asm/ptrace.h>
-#include <linux/uaccess.h>
-
-static int get_reg(struct pt_regs *regs, int nr)
-{
- int val;
-
- if (nr < 4)
- val = *(unsigned long *)(&regs->r0 + nr);
- else if (nr < 7)
- val = *(unsigned long *)(&regs->r4 + (nr - 4));
- else if (nr < 13)
- val = *(unsigned long *)(&regs->r7 + (nr - 7));
- else
- val = *(unsigned long *)(&regs->fp + (nr - 13));
-
- return val;
-}
-
-static void set_reg(struct pt_regs *regs, int nr, int val)
-{
- if (nr < 4)
- *(unsigned long *)(&regs->r0 + nr) = val;
- else if (nr < 7)
- *(unsigned long *)(&regs->r4 + (nr - 4)) = val;
- else if (nr < 13)
- *(unsigned long *)(&regs->r7 + (nr - 7)) = val;
- else
- *(unsigned long *)(&regs->fp + (nr - 13)) = val;
-}
-
-#define REG1(insn) (((insn) & 0x0f00) >> 8)
-#define REG2(insn) ((insn) & 0x000f)
-#define PSW_BC 0x100
-
-/* O- instruction */
-#define ISA_LD1 0x20c0 /* ld Rdest, @Rsrc */
-#define ISA_LD2 0x20e0 /* ld Rdest, @Rsrc+ */
-#define ISA_LDH 0x20a0 /* ldh Rdest, @Rsrc */
-#define ISA_LDUH 0x20b0 /* lduh Rdest, @Rsrc */
-#define ISA_ST1 0x2040 /* st Rsrc1, @Rsrc2 */
-#define ISA_ST2 0x2060 /* st Rsrc1, @+Rsrc2 */
-#define ISA_ST3 0x2070 /* st Rsrc1, @-Rsrc2 */
-#define ISA_STH1 0x2020 /* sth Rsrc1, @Rsrc2 */
-#define ISA_STH2 0x2030 /* sth Rsrc1, @Rsrc2+ */
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
-/* OS instruction */
-#define ISA_ADD 0x00a0 /* add Rdest, Rsrc */
-#define ISA_ADDI 0x4000 /* addi Rdest, #imm8 */
-#define ISA_ADDX 0x0090 /* addx Rdest, Rsrc */
-#define ISA_AND 0x00c0 /* and Rdest, Rsrc */
-#define ISA_CMP 0x0040 /* cmp Rsrc1, Rsrc2 */
-#define ISA_CMPEQ 0x0060 /* cmpeq Rsrc1, Rsrc2 */
-#define ISA_CMPU 0x0050 /* cmpu Rsrc1, Rsrc2 */
-#define ISA_CMPZ 0x0070 /* cmpz Rsrc */
-#define ISA_LDI 0x6000 /* ldi Rdest, #imm8 */
-#define ISA_MV 0x1080 /* mv Rdest, Rsrc */
-#define ISA_NEG 0x0030 /* neg Rdest, Rsrc */
-#define ISA_NOP 0x7000 /* nop */
-#define ISA_NOT 0x00b0 /* not Rdest, Rsrc */
-#define ISA_OR 0x00e0 /* or Rdest, Rsrc */
-#define ISA_SUB 0x0020 /* sub Rdest, Rsrc */
-#define ISA_SUBX 0x0010 /* subx Rdest, Rsrc */
-#define ISA_XOR 0x00d0 /* xor Rdest, Rsrc */
-
-/* -S instruction */
-#define ISA_MUL 0x1060 /* mul Rdest, Rsrc */
-#define ISA_MULLO_A0 0x3010 /* mullo Rsrc1, Rsrc2, A0 */
-#define ISA_MULLO_A1 0x3090 /* mullo Rsrc1, Rsrc2, A1 */
-#define ISA_MVFACMI_A0 0x50f2 /* mvfacmi Rdest, A0 */
-#define ISA_MVFACMI_A1 0x50f6 /* mvfacmi Rdest, A1 */
-
-static int emu_addi(unsigned short insn, struct pt_regs *regs)
-{
- char imm = (char)(insn & 0xff);
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val += imm;
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_ldi(unsigned short insn, struct pt_regs *regs)
-{
- char imm = (char)(insn & 0xff);
-
- set_reg(regs, REG1(insn), (int)imm);
-
- return 0;
-}
-
-static int emu_add(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int src = REG2(insn);
- int val;
-
- val = get_reg(regs, dest);
- val += get_reg(regs, src);
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_addx(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- unsigned int val, tmp;
-
- val = regs->psw & PSW_BC ? 1 : 0;
- tmp = get_reg(regs, dest);
- val += tmp;
- val += (unsigned int)get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- /* C bit set */
- if (val < tmp)
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_and(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val &= get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_cmp(unsigned short insn, struct pt_regs *regs)
-{
- if (get_reg(regs, REG1(insn)) < get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_cmpeq(unsigned short insn, struct pt_regs *regs)
-{
- if (get_reg(regs, REG1(insn)) == get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_cmpu(unsigned short insn, struct pt_regs *regs)
-{
- if ((unsigned int)get_reg(regs, REG1(insn))
- < (unsigned int)get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_cmpz(unsigned short insn, struct pt_regs *regs)
-{
- if (!get_reg(regs, REG2(insn)))
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_mv(unsigned short insn, struct pt_regs *regs)
-{
- int val;
-
- val = get_reg(regs, REG2(insn));
- set_reg(regs, REG1(insn), val);
-
- return 0;
-}
-
-static int emu_neg(unsigned short insn, struct pt_regs *regs)
-{
- int val;
-
- val = get_reg(regs, REG2(insn));
- set_reg(regs, REG1(insn), 0 - val);
-
- return 0;
-}
-
-static int emu_not(unsigned short insn, struct pt_regs *regs)
-{
- int val;
-
- val = get_reg(regs, REG2(insn));
- set_reg(regs, REG1(insn), ~val);
-
- return 0;
-}
-
-static int emu_or(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val |= get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_sub(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int val;
-
- val = get_reg(regs, dest);
- val -= get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_subx(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- unsigned int val, tmp;
-
- val = tmp = get_reg(regs, dest);
- val -= (unsigned int)get_reg(regs, REG2(insn));
- val -= regs->psw & PSW_BC ? 1 : 0;
- set_reg(regs, dest, val);
-
- /* C bit set */
- if (val > tmp)
- regs->psw |= PSW_BC;
- else
- regs->psw &= ~(PSW_BC);
-
- return 0;
-}
-
-static int emu_xor(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- unsigned int val;
-
- val = (unsigned int)get_reg(regs, dest);
- val ^= (unsigned int)get_reg(regs, REG2(insn));
- set_reg(regs, dest, val);
-
- return 0;
-}
-
-static int emu_mul(unsigned short insn, struct pt_regs *regs)
-{
- int dest = REG1(insn);
- int reg1, reg2;
-
- reg1 = get_reg(regs, dest);
- reg2 = get_reg(regs, REG2(insn));
-
- __asm__ __volatile__ (
- "mul %0, %1; \n\t"
- : "+r" (reg1) : "r" (reg2)
- );
-
- set_reg(regs, dest, reg1);
-
- return 0;
-}
-
-static int emu_mullo_a0(unsigned short insn, struct pt_regs *regs)
-{
- int reg1, reg2;
-
- reg1 = get_reg(regs, REG1(insn));
- reg2 = get_reg(regs, REG2(insn));
-
- __asm__ __volatile__ (
- "mullo %0, %1, a0; \n\t"
- "mvfachi %0, a0; \n\t"
- "mvfaclo %1, a0; \n\t"
- : "+r" (reg1), "+r" (reg2)
- );
-
- regs->acc0h = reg1;
- regs->acc0l = reg2;
-
- return 0;
-}
-
-static int emu_mullo_a1(unsigned short insn, struct pt_regs *regs)
-{
- int reg1, reg2;
-
- reg1 = get_reg(regs, REG1(insn));
- reg2 = get_reg(regs, REG2(insn));
-
- __asm__ __volatile__ (
- "mullo %0, %1, a0; \n\t"
- "mvfachi %0, a0; \n\t"
- "mvfaclo %1, a0; \n\t"
- : "+r" (reg1), "+r" (reg2)
- );
-
- regs->acc1h = reg1;
- regs->acc1l = reg2;
-
- return 0;
-}
-
-static int emu_mvfacmi_a0(unsigned short insn, struct pt_regs *regs)
-{
- unsigned long val;
-
- val = (regs->acc0h << 16) | (regs->acc0l >> 16);
- set_reg(regs, REG1(insn), (int)val);
-
- return 0;
-}
-
-static int emu_mvfacmi_a1(unsigned short insn, struct pt_regs *regs)
-{
- unsigned long val;
-
- val = (regs->acc1h << 16) | (regs->acc1l >> 16);
- set_reg(regs, REG1(insn), (int)val);
-
- return 0;
-}
-
-static int emu_m32r2(unsigned short insn, struct pt_regs *regs)
-{
- int res = -1;
-
- if ((insn & 0x7fff) == ISA_NOP) /* nop */
- return 0;
-
- switch(insn & 0x7000) {
- case ISA_ADDI: /* addi Rdest, #imm8 */
- res = emu_addi(insn, regs);
- break;
- case ISA_LDI: /* ldi Rdest, #imm8 */
- res = emu_ldi(insn, regs);
- break;
- default:
- break;
- }
-
- if (!res)
- return 0;
-
- switch(insn & 0x70f0) {
- case ISA_ADD: /* add Rdest, Rsrc */
- res = emu_add(insn, regs);
- break;
- case ISA_ADDX: /* addx Rdest, Rsrc */
- res = emu_addx(insn, regs);
- break;
- case ISA_AND: /* and Rdest, Rsrc */
- res = emu_and(insn, regs);
- break;
- case ISA_CMP: /* cmp Rsrc1, Rsrc2 */
- res = emu_cmp(insn, regs);
- break;
- case ISA_CMPEQ: /* cmpeq Rsrc1, Rsrc2 */
- res = emu_cmpeq(insn, regs);
- break;
- case ISA_CMPU: /* cmpu Rsrc1, Rsrc2 */
- res = emu_cmpu(insn, regs);
- break;
- case ISA_CMPZ: /* cmpz Rsrc */
- res = emu_cmpz(insn, regs);
- break;
- case ISA_MV: /* mv Rdest, Rsrc */
- res = emu_mv(insn, regs);
- break;
- case ISA_NEG: /* neg Rdest, Rsrc */
- res = emu_neg(insn, regs);
- break;
- case ISA_NOT: /* not Rdest, Rsrc */
- res = emu_not(insn, regs);
- break;
- case ISA_OR: /* or Rdest, Rsrc */
- res = emu_or(insn, regs);
- break;
- case ISA_SUB: /* sub Rdest, Rsrc */
- res = emu_sub(insn, regs);
- break;
- case ISA_SUBX: /* subx Rdest, Rsrc */
- res = emu_subx(insn, regs);
- break;
- case ISA_XOR: /* xor Rdest, Rsrc */
- res = emu_xor(insn, regs);
- break;
- case ISA_MUL: /* mul Rdest, Rsrc */
- res = emu_mul(insn, regs);
- break;
- case ISA_MULLO_A0: /* mullo Rsrc1, Rsrc2 */
- res = emu_mullo_a0(insn, regs);
- break;
- case ISA_MULLO_A1: /* mullo Rsrc1, Rsrc2 */
- res = emu_mullo_a1(insn, regs);
- break;
- default:
- break;
- }
-
- if (!res)
- return 0;
-
- switch(insn & 0x70ff) {
- case ISA_MVFACMI_A0: /* mvfacmi Rdest */
- res = emu_mvfacmi_a0(insn, regs);
- break;
- case ISA_MVFACMI_A1: /* mvfacmi Rdest */
- res = emu_mvfacmi_a1(insn, regs);
- break;
- default:
- break;
- }
-
- return res;
-}
-
-#endif /* CONFIG_ISA_DUAL_ISSUE */
-
-/*
- * ld : ?010 dest 1100 src
- * 0010 dest 1110 src : ld Rdest, @Rsrc+
- * ldh : ?010 dest 1010 src
- * lduh : ?010 dest 1011 src
- * st : ?010 src1 0100 src2
- * 0010 src1 0110 src2 : st Rsrc1, @+Rsrc2
- * 0010 src1 0111 src2 : st Rsrc1, @-Rsrc2
- * sth : ?010 src1 0010 src2
- */
-
-static int insn_check(unsigned long insn, struct pt_regs *regs,
- unsigned char **ucp)
-{
- int res = 0;
-
- /*
- * 32bit insn
- * ld Rdest, @(disp16, Rsrc)
- * st Rdest, @(disp16, Rsrc)
- */
- if (insn & 0x80000000) { /* 32bit insn */
- *ucp += (short)(insn & 0x0000ffff);
- regs->bpc += 4;
- } else { /* 16bit insn */
-#ifdef CONFIG_ISA_DUAL_ISSUE
- /* parallel exec check */
- if (!(regs->bpc & 0x2) && insn & 0x8000) {
- res = emu_m32r2((unsigned short)insn, regs);
- regs->bpc += 4;
- } else
-#endif /* CONFIG_ISA_DUAL_ISSUE */
- regs->bpc += 2;
- }
-
- return res;
-}
-
-static int emu_ld(unsigned long insn32, struct pt_regs *regs)
-{
- unsigned char *ucp;
- unsigned long val;
- unsigned short insn16;
- int size, src;
-
- insn16 = insn32 >> 16;
- src = REG2(insn16);
- ucp = (unsigned char *)get_reg(regs, src);
-
- if (insn_check(insn32, regs, &ucp))
- return -1;
-
- size = insn16 & 0x0040 ? 4 : 2;
- if (copy_from_user(&val, ucp, size))
- return -1;
-
- if (size == 2)
- val >>= 16;
-
- /* ldh sign check */
- if ((insn16 & 0x00f0) == 0x00a0 && (val & 0x8000))
- val |= 0xffff0000;
-
- set_reg(regs, REG1(insn16), val);
-
- /* ld increment check */
- if ((insn16 & 0xf0f0) == ISA_LD2) /* ld Rdest, @Rsrc+ */
- set_reg(regs, src, (unsigned long)(ucp + 4));
-
- return 0;
-}
-
-static int emu_st(unsigned long insn32, struct pt_regs *regs)
-{
- unsigned char *ucp;
- unsigned long val;
- unsigned short insn16;
- int size, src2;
-
- insn16 = insn32 >> 16;
- src2 = REG2(insn16);
-
- ucp = (unsigned char *)get_reg(regs, src2);
-
- if (insn_check(insn32, regs, &ucp))
- return -1;
-
- size = insn16 & 0x0040 ? 4 : 2;
- val = get_reg(regs, REG1(insn16));
- if (size == 2)
- val <<= 16;
-
- /* st inc/dec check */
- if ((insn16 & 0xf0e0) == 0x2060) {
- if (insn16 & 0x0010)
- ucp -= 4;
- else
- ucp += 4;
-
- set_reg(regs, src2, (unsigned long)ucp);
- }
-
- if (copy_to_user(ucp, &val, size))
- return -1;
-
- /* sth inc check */
- if ((insn16 & 0xf0f0) == ISA_STH2) {
- ucp += 2;
- set_reg(regs, src2, (unsigned long)ucp);
- }
-
- return 0;
-}
-
-int handle_unaligned_access(unsigned long insn32, struct pt_regs *regs)
-{
- unsigned short insn16;
- int res;
-
- insn16 = insn32 >> 16;
-
- /* ld or st check */
- if ((insn16 & 0x7000) != 0x2000)
- return -1;
-
- /* insn alignment check */
- if ((insn16 & 0x8000) && (regs->bpc & 3))
- return -1;
-
- if (insn16 & 0x0080) /* ld */
- res = emu_ld(insn32, regs);
- else /* st */
- res = emu_st(insn32, regs);
-
- return res;
-}
-
diff --git a/arch/m32r/kernel/asm-offsets.c b/arch/m32r/kernel/asm-offsets.c
deleted file mode 100644
index 7cb90b459e07..000000000000
--- a/arch/m32r/kernel/asm-offsets.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/thread_info.h>
-#include <linux/kbuild.h>
-
-int foo(void)
-{
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_STATUS, thread_info, status);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
- OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
-
- return 0;
-}
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
deleted file mode 100644
index bbf48f2aa2a7..000000000000
--- a/arch/m32r/kernel/entry.S
+++ /dev/null
@@ -1,553 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/kernel/entry.S
- *
- * Copyright (c) 2001, 2002 Hirokazu Takata, Hitoshi Yamamoto, H. Kondo
- * Copyright (c) 2003 Hitoshi Yamamoto
- * Copyright (c) 2004 Hirokazu Takata <takata at linux-m32r.org>
- *
- * Taken from i386 version.
- * Copyright (C) 1991, 1992 Linus Torvalds
- */
-
-/*
- * entry.S contains the system-call and fault low-level handling routines.
- * This also contains the timer-interrupt handler, as well as all interrupts
- * and faults that can result in a task-switch.
- *
- * NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- *
- * Stack layout in 'ret_from_system_call':
- * ptrace needs to have all regs on the stack.
- * if the order here is changed, it needs to be
- * updated in fork.c:copy_thread, signal.c:do_signal,
- * ptrace.c and ptrace.h
- *
- * M32R/M32Rx/M32R2
- * @(sp) - r4
- * @(0x04,sp) - r5
- * @(0x08,sp) - r6
- * @(0x0c,sp) - *pt_regs
- * @(0x10,sp) - r0
- * @(0x14,sp) - r1
- * @(0x18,sp) - r2
- * @(0x1c,sp) - r3
- * @(0x20,sp) - r7
- * @(0x24,sp) - r8
- * @(0x28,sp) - r9
- * @(0x2c,sp) - r10
- * @(0x30,sp) - r11
- * @(0x34,sp) - r12
- * @(0x38,sp) - syscall_nr
- * @(0x3c,sp) - acc0h
- * @(0x40,sp) - acc0l
- * @(0x44,sp) - acc1h ; ISA_DSP_LEVEL2 only
- * @(0x48,sp) - acc1l ; ISA_DSP_LEVEL2 only
- * @(0x4c,sp) - psw
- * @(0x50,sp) - bpc
- * @(0x54,sp) - bbpsw
- * @(0x58,sp) - bbpc
- * @(0x5c,sp) - spu (cr3)
- * @(0x60,sp) - fp (r13)
- * @(0x64,sp) - lr (r14)
- * @(0x68,sp) - spi (cr2)
- * @(0x6c,sp) - orig_r0
- */
-
-#include <linux/linkage.h>
-#include <asm/irq.h>
-#include <asm/unistd.h>
-#include <asm/assembler.h>
-#include <asm/thread_info.h>
-#include <asm/errno.h>
-#include <asm/segment.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/m32r.h>
-#include <asm/mmu_context.h>
-#include <asm/asm-offsets.h>
-
-#if !defined(CONFIG_MMU)
-#define sys_madvise sys_ni_syscall
-#define sys_readahead sys_ni_syscall
-#define sys_mprotect sys_ni_syscall
-#define sys_msync sys_ni_syscall
-#define sys_mlock sys_ni_syscall
-#define sys_munlock sys_ni_syscall
-#define sys_mlockall sys_ni_syscall
-#define sys_munlockall sys_ni_syscall
-#define sys_mremap sys_ni_syscall
-#define sys_mincore sys_ni_syscall
-#define sys_remap_file_pages sys_ni_syscall
-#endif /* CONFIG_MMU */
-
-#define R4(reg) @reg
-#define R5(reg) @(0x04,reg)
-#define R6(reg) @(0x08,reg)
-#define PTREGS(reg) @(0x0C,reg)
-#define R0(reg) @(0x10,reg)
-#define R1(reg) @(0x14,reg)
-#define R2(reg) @(0x18,reg)
-#define R3(reg) @(0x1C,reg)
-#define R7(reg) @(0x20,reg)
-#define R8(reg) @(0x24,reg)
-#define R9(reg) @(0x28,reg)
-#define R10(reg) @(0x2C,reg)
-#define R11(reg) @(0x30,reg)
-#define R12(reg) @(0x34,reg)
-#define SYSCALL_NR(reg) @(0x38,reg)
-#define ACC0H(reg) @(0x3C,reg)
-#define ACC0L(reg) @(0x40,reg)
-#define ACC1H(reg) @(0x44,reg)
-#define ACC1L(reg) @(0x48,reg)
-#define PSW(reg) @(0x4C,reg)
-#define BPC(reg) @(0x50,reg)
-#define BBPSW(reg) @(0x54,reg)
-#define BBPC(reg) @(0x58,reg)
-#define SPU(reg) @(0x5C,reg)
-#define FP(reg) @(0x60,reg) /* FP = R13 */
-#define LR(reg) @(0x64,reg)
-#define SP(reg) @(0x68,reg)
-#define ORIG_R0(reg) @(0x6C,reg)
-
-#define nr_syscalls ((syscall_table_size)/4)
-
-#ifdef CONFIG_PREEMPT
-#define preempt_stop(x) DISABLE_INTERRUPTS(x)
-#else
-#define preempt_stop(x)
-#define resume_kernel restore_all
-#endif
-
-/* how to get the thread information struct from ASM */
-#define GET_THREAD_INFO(reg) GET_THREAD_INFO reg
- .macro GET_THREAD_INFO reg
- ldi \reg, #-THREAD_SIZE
- and \reg, sp
- .endm
-
-ENTRY(ret_from_kernel_thread)
- pop r0
- bl schedule_tail
- GET_THREAD_INFO(r8)
- ld r0, R0(r8)
- ld r1, R1(r8)
- jl r1
- bra syscall_exit
-
-ENTRY(ret_from_fork)
- pop r0
- bl schedule_tail
- GET_THREAD_INFO(r8)
- bra syscall_exit
-
-/*
- * Return to user mode is not as complex as all this looks,
- * but we want the default path for a system call return to
- * go as quickly as possible which is why some of this is
- * less clear than it otherwise should be.
- */
-
- ; userspace resumption stub bypassing syscall exit tracing
- ALIGN
-ret_from_exception:
- preempt_stop(r4)
-ret_from_intr:
- ld r4, PSW(sp)
-#ifdef CONFIG_ISA_M32R2
- and3 r4, r4, #0x8800 ; check BSM and BPM bits
-#else
- and3 r4, r4, #0x8000 ; check BSM bit
-#endif
- beqz r4, resume_kernel
-resume_userspace:
- DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
- ; setting need_resched or sigpending
- ; between sampling and the iret
- GET_THREAD_INFO(r8)
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done on
- ; int/exception return?
- bnez r4, work_pending
- bra restore_all
-
-#ifdef CONFIG_PREEMPT
-ENTRY(resume_kernel)
- GET_THREAD_INFO(r8)
- ld r9, @(TI_PRE_COUNT, r8) ; non-zero preempt_count ?
- bnez r9, restore_all
-need_resched:
- ld r9, @(TI_FLAGS, r8) ; need_resched set ?
- and3 r4, r9, #_TIF_NEED_RESCHED
- beqz r4, restore_all
- ld r4, PSW(sp) ; interrupts off (exception path) ?
- and3 r4, r4, #0x4000
- beqz r4, restore_all
- bl preempt_schedule_irq
- bra need_resched
-#endif
-
- ; system call handler stub
-ENTRY(system_call)
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
- ENABLE_INTERRUPTS(r4) ; Enable interrupt
- st sp, PTREGS(sp) ; implicit pt_regs parameter
- cmpui r7, #NR_syscalls
- bnc syscall_badsys
- st r7, SYSCALL_NR(sp) ; syscall_nr
- ; system call tracing in operation
- GET_THREAD_INFO(r8)
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_SYSCALL_TRACE
- bnez r4, syscall_trace_entry
-syscall_call:
- slli r7, #2 ; table jump for the system call
- LDIMM (r4, sys_call_table)
- add r7, r4
- ld r7, @r7
- jl r7 ; execute system call
- st r0, R0(sp) ; save the return value
-syscall_exit:
- DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
- ; setting need_resched or sigpending
- ; between sampling and the iret
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_ALLWORK_MASK ; current->work
- bnez r4, syscall_exit_work
-restore_all:
- RESTORE_ALL
-
- # perform work that needs to be done immediately before resumption
- # r9 : flags
- ALIGN
-work_pending:
- and3 r4, r9, #_TIF_NEED_RESCHED
- beqz r4, work_notifysig
-work_resched:
- bl schedule
- DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
- ; setting need_resched or sigpending
- ; between sampling and the iret
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_WORK_MASK ; is there any work to be done other
- ; than syscall tracing?
- beqz r4, restore_all
- and3 r4, r4, #_TIF_NEED_RESCHED
- bnez r4, work_resched
-
-work_notifysig: ; deal with pending signals and
- ; notify-resume requests
- mv r0, sp ; arg1 : struct pt_regs *regs
- mv r1, r9 ; arg2 : __u32 thread_info_flags
- bl do_notify_resume
- bra resume_userspace
-
- ; perform syscall exit tracing
- ALIGN
-syscall_trace_entry:
- ldi r4, #-ENOSYS
- st r4, R0(sp)
- bl do_syscall_trace
- ld r0, ORIG_R0(sp)
- ld r1, R1(sp)
- ld r2, R2(sp)
- ld r3, R3(sp)
- ld r4, R4(sp)
- ld r5, R5(sp)
- ld r6, R6(sp)
- ld r7, SYSCALL_NR(sp)
- cmpui r7, #NR_syscalls
- bc syscall_call
- bra syscall_exit
-
- ; perform syscall exit tracing
- ALIGN
-syscall_exit_work:
- ld r9, @(TI_FLAGS, r8)
- and3 r4, r9, #_TIF_SYSCALL_TRACE
- beqz r4, work_pending
- ENABLE_INTERRUPTS(r4) ; could let do_syscall_trace() call
- ; schedule() instead
- bl do_syscall_trace
- bra resume_userspace
-
- ALIGN
-syscall_fault:
- SAVE_ALL
- GET_THREAD_INFO(r8)
- ldi r4, #-EFAULT
- st r4, R0(sp)
- bra resume_userspace
-
- ALIGN
-syscall_badsys:
- ldi r4, #-ENOSYS
- st r4, R0(sp)
- bra resume_userspace
-
- .global eit_vector
-
- .equ ei_vec_table, eit_vector + 0x0200
-
-/*
- * EI handler routine
- */
-ENTRY(ei_handler)
-#if defined(CONFIG_CHIP_M32700)
- ; WORKAROUND: force to clear SM bit and use the kernel stack (SPI).
- SWITCH_TO_KERNEL_STACK
-#endif
- SAVE_ALL
- mv r1, sp ; arg1(regs)
- ; get ICU status
- seth r0, #shigh(M32R_ICU_ISTS_ADDR)
- ld r0, @(low(M32R_ICU_ISTS_ADDR),r0)
- push r0
-#if defined(CONFIG_SMP)
- /*
- * If IRQ == 0 --> Nothing to do, Not write IMASK
- * If IRQ == IPI --> Do IPI handler, Not write IMASK
- * If IRQ != 0, IPI --> Do do_IRQ(), Write IMASK
- */
- slli r0, #4
- srli r0, #24 ; r0(irq_num<<2)
- ;; IRQ exist check
-#if defined(CONFIG_CHIP_M32700)
- /* WORKAROUND: IMASK bug M32700-TS1, TS2 chip. */
- bnez r0, 0f
- ld24 r14, #0x00070000
- seth r0, #shigh(M32R_ICU_IMASK_ADDR)
- st r14, @(low(M32R_ICU_IMASK_ADDR),r0)
- bra 1f
- .fillinsn
-0:
-#endif /* CONFIG_CHIP_M32700 */
- beqz r0, 1f ; if (!irq_num) goto exit
- ;; IPI check
- cmpi r0, #(M32R_IRQ_IPI0<<2) ; ISN < IPI0 check
- bc 2f
- cmpi r0, #((M32R_IRQ_IPI7+1)<<2) ; ISN > IPI7 check
- bnc 2f
- LDIMM (r2, ei_vec_table)
- add r2, r0
- ld r2, @r2
- beqz r2, 1f ; if (no IPI handler) goto exit
- mv r0, r1 ; arg0(regs)
- jl r2
- .fillinsn
-1:
- addi sp, #4
- bra restore_all
- .fillinsn
-2:
- srli r0, #2
-#else /* not CONFIG_SMP */
- srli r0, #22 ; r0(irq)
-#endif /* not CONFIG_SMP */
-
-#if defined(CONFIG_PLAT_HAS_INT1ICU)
- add3 r2, r0, #-(M32R_IRQ_INT1) ; INT1# interrupt
- bnez r2, 3f
- seth r0, #shigh(M32R_INT1ICU_ISTS)
- lduh r0, @(low(M32R_INT1ICU_ISTS),r0) ; bit10-6 : ISN
- slli r0, #21
- srli r0, #27 ; ISN
- addi r0, #(M32R_INT1ICU_IRQ_BASE)
- bra check_end
- .fillinsn
-3:
-#endif /* CONFIG_PLAT_HAS_INT1ICU */
-#if defined(CONFIG_PLAT_HAS_INT0ICU)
- add3 r2, r0, #-(M32R_IRQ_INT0) ; INT0# interrupt
- bnez r2, 4f
- seth r0, #shigh(M32R_INT0ICU_ISTS)
- lduh r0, @(low(M32R_INT0ICU_ISTS),r0) ; bit10-6 : ISN
- slli r0, #21
- srli r0, #27 ; ISN
- add3 r0, r0, #(M32R_INT0ICU_IRQ_BASE)
- bra check_end
- .fillinsn
-4:
-#endif /* CONFIG_PLAT_HAS_INT0ICU */
-#if defined(CONFIG_PLAT_HAS_INT2ICU)
- add3 r2, r0, #-(M32R_IRQ_INT2) ; INT2# interrupt
- bnez r2, 5f
- seth r0, #shigh(M32R_INT2ICU_ISTS)
- lduh r0, @(low(M32R_INT2ICU_ISTS),r0) ; bit10-6 : ISN
- slli r0, #21
- srli r0, #27 ; ISN
- add3 r0, r0, #(M32R_INT2ICU_IRQ_BASE)
- ; bra check_end
- .fillinsn
-5:
-#endif /* CONFIG_PLAT_HAS_INT2ICU */
-
-check_end:
- bl do_IRQ
- pop r14
- seth r0, #shigh(M32R_ICU_IMASK_ADDR)
- st r14, @(low(M32R_ICU_IMASK_ADDR),r0)
- bra ret_from_intr
-
-/*
- * Default EIT handler
- */
- ALIGN
-int_msg:
- .asciz "Unknown interrupt\n"
- .byte 0
-
-ENTRY(default_eit_handler)
- push r0
- mvfc r0, psw
- push r1
- push r2
- push r3
- push r0
- LDIMM (r0, __KERNEL_DS)
- mv r0, r1
- mv r0, r2
- LDIMM (r0, int_msg)
- bl printk
- pop r0
- pop r3
- pop r2
- pop r1
- mvtc r0, psw
- pop r0
-infinit:
- bra infinit
-
-#ifdef CONFIG_MMU
-/*
- * Access Exception handler
- */
-ENTRY(ace_handler)
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
-
- seth r2, #shigh(MMU_REG_BASE) /* Check status register */
- ld r4, @(low(MESTS_offset),r2)
- st r4, @(low(MESTS_offset),r2)
- srl3 r1, r4, #4
-#ifdef CONFIG_CHIP_M32700
- and3 r1, r1, #0x0000ffff
- ; WORKAROUND: ignore TME bit for the M32700(TS1).
-#endif /* CONFIG_CHIP_M32700 */
- beqz r1, inst
-oprand:
- ld r2, @(low(MDEVA_offset),r2) ; set address
- srli r1, #1
- bra 1f
-inst:
- and3 r1, r4, #2
- srli r1, #1
- or3 r1, r1, #8
- mvfc r2, bpc ; set address
- .fillinsn
-1:
- mvfc r3, psw
- mv r0, sp
- and3 r3, r3, 0x800
- srli r3, #9
- or r1, r3
- /*
- * do_page_fault():
- * r0 : struct pt_regs *regs
- * r1 : unsigned long error-code
- * r2 : unsigned long address
- * error-code:
- * +------+------+------+------+
- * | bit3 | bit2 | bit1 | bit0 |
- * +------+------+------+------+
- * bit 3 == 0:means data, 1:means instruction
- * bit 2 == 0:means kernel, 1:means user-mode
- * bit 1 == 0:means read, 1:means write
- * bit 0 == 0:means no page found 1:means protection fault
- *
- */
- bl do_page_fault
- bra ret_from_intr
-#endif /* CONFIG_MMU */
-
-
-ENTRY(alignment_check)
- /* void alignment_check(int error_code) */
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
- ldi r1, #0x30 ; error_code
- mv r0, sp ; pt_regs
- bl do_alignment_check
-error_code:
- bra ret_from_exception
-
-ENTRY(rie_handler)
- /* void rie_handler(int error_code) */
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
- ldi r1, #0x20 ; error_code
- mv r0, sp ; pt_regs
- bl do_rie_handler
- bra error_code
-
-ENTRY(pie_handler)
- /* void pie_handler(int error_code) */
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
- ldi r1, #0 ; error_code ; FIXME
- mv r0, sp ; pt_regs
- bl do_pie_handler
- bra error_code
-
-ENTRY(debug_trap)
- /* void debug_trap(void) */
- .global withdraw_debug_trap
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
- mv r0, sp ; pt_regs
- bl withdraw_debug_trap
- ldi r1, #0 ; error_code
- mv r0, sp ; pt_regs
- bl do_debug_trap
- bra error_code
-
-ENTRY(ill_trap)
- /* void ill_trap(void) */
- SWITCH_TO_KERNEL_STACK
- SAVE_ALL
- ldi r1, #0 ; error_code ; FIXME
- mv r0, sp ; pt_regs
- bl do_ill_trap
- bra error_code
-
-ENTRY(cache_flushing_handler)
- /* void _flush_cache_all(void); */
- .global _flush_cache_all
- SWITCH_TO_KERNEL_STACK
- push r0
- push r1
- push r2
- push r3
- push r4
- push r5
- push r6
- push r7
- push lr
- bl _flush_cache_all
- pop lr
- pop r7
- pop r6
- pop r5
- pop r4
- pop r3
- pop r2
- pop r1
- pop r0
- rte
-
- .section .rodata,"a"
-#include "syscall_table.S"
-
-syscall_table_size=(.-sys_call_table)
diff --git a/arch/m32r/kernel/head.S b/arch/m32r/kernel/head.S
deleted file mode 100644
index 1f040973df1c..000000000000
--- a/arch/m32r/kernel/head.S
+++ /dev/null
@@ -1,284 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/kernel/head.S
- *
- * M32R startup code.
- *
- * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto
- */
-
-#include <linux/init.h>
-__INIT
-__INITDATA
-
- .text
-#include <linux/linkage.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/assembler.h>
-#include <asm/m32r.h>
-#include <asm/mmu_context.h>
-
-/*
- * References to members of the boot_cpu_data structure.
- */
-__HEAD
- .global start_kernel
- .global __bss_start
- .global _end
-ENTRY(stext)
-ENTRY(_stext)
- /* Setup up the stack pointer */
- LDIMM (r0, spi_stack_top)
- LDIMM (r1, spu_stack_top)
- mvtc r0, spi
- mvtc r1, spu
-
- /* Initilalize PSW */
- ldi r0, #0x0000 /* use SPI, disable EI */
- mvtc r0, psw
-
- /* Set up the stack pointer */
- LDIMM (r0, stack_start)
- ld r0, @r0
- mvtc r0, spi
-
-/*
- * Clear BSS first so that there are no surprises...
- */
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
- LDIMM (r2, __bss_start)
- LDIMM (r3, _end)
- sub r3, r2 ; BSS size in bytes
- ; R4 = BSS size in longwords (rounded down)
- mv r4, r3 || ldi r1, #0
- srli r4, #4 || addi r2, #-4
- beqz r4, .Lendloop1
-.Lloop1:
-#ifndef CONFIG_CHIP_M32310
- ; Touch memory for the no-write-allocating cache.
- ld r0, @(4,r2)
-#endif
- st r1, @+r2 || addi r4, #-1
- st r1, @+r2
- st r1, @+r2
- st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
- bnc .Lloop1
-.Lendloop1:
- and3 r4, r3, #15
- addi r2, #4
- beqz r4, .Lendloop2
-.Lloop2:
- stb r1, @r2 || addi r4, #-1
- addi r2, #1
- bnez r4, .Lloop2
-.Lendloop2:
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
- LDIMM (r2, __bss_start)
- LDIMM (r3, _end)
- sub r3, r2 ; BSS size in bytes
- mv r4, r3
- srli r4, #2 ; R4 = BSS size in longwords (rounded down)
- ldi r1, #0 ; clear R1 for longwords store
- addi r2, #-4 ; account for pre-inc store
- beqz r4, .Lendloop1 ; any more to go?
-.Lloop1:
- st r1, @+r2 ; yep, zero out another longword
- addi r4, #-1 ; decrement count
- bnez r4, .Lloop1 ; go do some more
-.Lendloop1:
- and3 r4, r3, #3 ; get no. of remaining BSS bytes to clear
- addi r2, #4 ; account for pre-inc store
- beqz r4, .Lendloop2 ; any more to go?
-.Lloop2:
- stb r1, @r2 ; yep, zero out another byte
- addi r2, #1 ; bump address
- addi r4, #-1 ; decrement count
- bnez r4, .Lloop2 ; go do some more
-.Lendloop2:
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
-#if 0 /* M32R_FIXME */
-/*
- * Copy data segment from ROM to RAM.
- */
- .global ROM_D, TOP_DATA, END_DATA
-
- LDIMM (r1, ROM_D)
- LDIMM (r2, TOP_DATA)
- LDIMM (r3, END_DATA)
- addi r2, #-4
- addi r3, #-4
-loop1:
- ld r0, @r1+
- st r0, @+r2
- cmp r2, r3
- bc loop1
-#endif /* 0 */
-
-/* Jump to kernel */
- LDIMM (r2, start_kernel)
- jl r2
- .fillinsn
-1:
- bra 1b ; main should never return here, but
- ; just in case, we know what happens.
-
-#ifdef CONFIG_SMP
-/*
- * AP startup routine
- */
- .global eit_vector
-ENTRY(startup_AP)
-;; setup EVB
- LDIMM (r4, eit_vector)
- mvtc r4, cr5
-
-;; enable MMU
- LDIMM (r2, init_tlb)
- jl r2
- seth r4, #high(MATM)
- or3 r4, r4, #low(MATM)
- ldi r5, #0x01
- st r5, @r4 ; Set MATM Reg(T bit ON)
- ld r6, @r4 ; MATM Check
- LDIMM (r5, 1f)
- jmp r5 ; enable MMU
- nop
- .fillinsn
-1:
-;; ISN check
- ld r6, @r4 ; MATM Check
- seth r4, #high(M32R_ICU_ISTS_ADDR)
- or3 r4, r4, #low(M32R_ICU_ISTS_ADDR)
- ld r5, @r4 ; Read ISTSi reg.
- mv r6, r5
- slli r5, #13 ; PIML check
- srli r5, #13 ;
- seth r4, #high(M32R_ICU_IMASK_ADDR)
- or3 r4, r4, #low(M32R_ICU_IMASK_ADDR)
- st r5, @r4 ; Write IMASKi reg.
- slli r6, #4 ; ISN check
- srli r6, #26 ;
- seth r4, #high(M32R_IRQ_IPI5)
- or3 r4, r4, #low(M32R_IRQ_IPI5)
- bne r4, r6, 2f ; if (ISN != CPU_BOOT_IPI) goto sleep;
-
-;; check cpu_bootout_map and set cpu_bootin_map
- LDIMM (r4, cpu_bootout_map)
- ld r4, @r4
- seth r5, #high(M32R_CPUID_PORTL)
- or3 r5, r5, #low(M32R_CPUID_PORTL)
- ld r5, @r5
- ldi r6, #1
- sll r6, r5
- and r4, r6
- beqz r4, 2f
- LDIMM (r4, cpu_bootin_map)
- ld r5, @r4
- or r5, r6
- st r6, @r4
-
-;; clear PSW
- ldi r4, #0
- mvtc r4, psw
-
-;; setup SPI
- LDIMM (r4, stack_start)
- ld r4, @r4
- mvtc r4, spi
-
-;; setup BPC (start_secondary)
- LDIMM (r4, start_secondary)
- mvtc r4, bpc
-
- rte ; goto startup_secondary
- nop
- nop
-
- .fillinsn
-2:
- ;; disable MMU
- seth r4, #high(MATM)
- or3 r4, r4, #low(MATM)
- ldi r5, #0
- st r5, @r4 ; Set MATM Reg(T bit OFF)
- ld r6, @r4 ; MATM Check
- LDIMM (r4, 3f)
- seth r5, #high(__PAGE_OFFSET)
- or3 r5, r5, #low(__PAGE_OFFSET)
- not r5, r5
- and r4, r5
- jmp r4 ; disable MMU
- nop
- .fillinsn
-3:
- ;; SLEEP and wait IPI
- LDIMM (r4, AP_loop)
- seth r5, #high(__PAGE_OFFSET)
- or3 r5, r5, #low(__PAGE_OFFSET)
- not r5, r5
- and r4, r5
- jmp r4
- nop
- nop
-#endif /* CONFIG_SMP */
-
- .text
-ENTRY(stack_start)
- .long init_thread_union+8192
- .long __KERNEL_DS
-
-/*
- * This is initialized to create a identity-mapping at 0-4M (for bootup
- * purposes) and another mapping of the 0-4M area at virtual address
- * PAGE_OFFSET.
- */
- .text
-
-#define MOUNT_ROOT_RDONLY 1
-#define RAMDISK_FLAGS 0 ; 1024KB
-#define ORIG_ROOT_DEV 0x0100 ; /dev/ram0 (major:01, minor:00)
-#define LOADER_TYPE 1 ; (??? - non-zero value seems
- ; to be needed to boot from initrd)
-
-#define COMMAND_LINE ""
-
- .section .empty_zero_page, "aw"
-ENTRY(empty_zero_page)
- .long MOUNT_ROOT_RDONLY /* offset: +0x00 */
- .long RAMDISK_FLAGS
- .long ORIG_ROOT_DEV
- .long LOADER_TYPE
- .long 0 /* INITRD_START */ /* +0x10 */
- .long 0 /* INITRD_SIZE */
- .long 0 /* CPU_CLOCK */
- .long 0 /* BUS_CLOCK */
- .long 0 /* TIMER_DIVIDE */ /* +0x20 */
- .balign 256,0
- .asciz COMMAND_LINE
- .byte 0
- .balign 4096,0,4096
-
-/*------------------------------------------------------------------------
- * Stack area
- */
- .section .init.data, "aw"
- ALIGN
- .global spi_stack_top
- .zero 1024
-spi_stack_top:
-
- .section .init.data, "aw"
- ALIGN
- .global spu_stack_top
- .zero 1024
-spu_stack_top:
-
- .end
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c
deleted file mode 100644
index 83b5032f176c..000000000000
--- a/arch/m32r/kernel/irq.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/irq.c
- *
- * Copyright (c) 2003, 2004 Hitoshi Yamamoto
- * Copyright (c) 2004 Hirokazu Takata <takata at linux-m32r.org>
- */
-
-/*
- * linux/arch/i386/kernel/irq.c
- *
- * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
- *
- * This file contains the lowest level m32r-specific interrupt
- * entry and irq statistics code. All the remaining irq logic is
- * done by the generic kernel/irq/ code and in the
- * m32r-specific irq controller code.
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/uaccess.h>
-
-/*
- * do_IRQ handles all normal device IRQs (the special
- * SMP cross-CPU interrupts have their own specific
- * handlers).
- */
-asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
- old_regs = set_irq_regs(regs);
- irq_enter();
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
- /* FIXME M32R */
-#endif
- generic_handle_irq(irq);
- irq_exit();
- set_irq_regs(old_regs);
-
- return 1;
-}
diff --git a/arch/m32r/kernel/m32r_ksyms.c b/arch/m32r/kernel/m32r_ksyms.c
deleted file mode 100644
index 46ebe071e4d6..000000000000
--- a/arch/m32r/kernel/m32r_ksyms.c
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/module.h>
-#include <linux/smp.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/sched.h>
-#include <linux/in6.h>
-#include <linux/interrupt.h>
-#include <linux/string.h>
-
-#include <asm/processor.h>
-#include <linux/uaccess.h>
-#include <asm/checksum.h>
-#include <asm/io.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
-
-/* platform dependent support */
-EXPORT_SYMBOL(boot_cpu_data);
-EXPORT_SYMBOL(dump_fpu);
-EXPORT_SYMBOL(__ioremap);
-EXPORT_SYMBOL(iounmap);
-
-EXPORT_SYMBOL(strncpy_from_user);
-EXPORT_SYMBOL(clear_user);
-EXPORT_SYMBOL(__clear_user);
-EXPORT_SYMBOL(strnlen_user);
-
-#ifdef CONFIG_SMP
-#ifdef CONFIG_CHIP_M32700_TS1
-extern void *dcache_dummy;
-EXPORT_SYMBOL(dcache_dummy);
-#endif
-EXPORT_SYMBOL(cpu_data);
-
-/* TLB flushing */
-EXPORT_SYMBOL(smp_flush_tlb_page);
-#endif
-
-extern int __ucmpdi2(unsigned long long a, unsigned long long b);
-EXPORT_SYMBOL(__ucmpdi2);
-
-/* compiler generated symbol */
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __lshldi3(void);
-extern void __lshrdi3(void);
-extern void __muldi3(void);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__lshldi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__muldi3);
-
-/* memory and string operations */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-EXPORT_SYMBOL(copy_page);
-EXPORT_SYMBOL(clear_page);
-EXPORT_SYMBOL(strlen);
-EXPORT_SYMBOL(empty_zero_page);
-
-EXPORT_SYMBOL(_inb);
-EXPORT_SYMBOL(_inw);
-EXPORT_SYMBOL(_inl);
-EXPORT_SYMBOL(_outb);
-EXPORT_SYMBOL(_outw);
-EXPORT_SYMBOL(_outl);
-EXPORT_SYMBOL(_inb_p);
-EXPORT_SYMBOL(_inw_p);
-EXPORT_SYMBOL(_inl_p);
-EXPORT_SYMBOL(_outb_p);
-EXPORT_SYMBOL(_outw_p);
-EXPORT_SYMBOL(_outl_p);
-EXPORT_SYMBOL(_insb);
-EXPORT_SYMBOL(_insw);
-EXPORT_SYMBOL(_insl);
-EXPORT_SYMBOL(_outsb);
-EXPORT_SYMBOL(_outsw);
-EXPORT_SYMBOL(_outsl);
-EXPORT_SYMBOL(_readb);
-EXPORT_SYMBOL(_readw);
-EXPORT_SYMBOL(_readl);
-EXPORT_SYMBOL(_writeb);
-EXPORT_SYMBOL(_writew);
-EXPORT_SYMBOL(_writel);
-
diff --git a/arch/m32r/kernel/module.c b/arch/m32r/kernel/module.c
deleted file mode 100644
index 38233b6596b6..000000000000
--- a/arch/m32r/kernel/module.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Kernel module help for M32R.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-
-#if 0
-#define DEBUGP printk
-#else
-#define DEBUGP(fmt...)
-#endif
-
-#define COPY_UNALIGNED_WORD(sw, tw, align) \
-{ \
- void *__s = &(sw), *__t = &(tw); \
- unsigned short *__s2 = __s, *__t2 =__t; \
- unsigned char *__s1 = __s, *__t1 =__t; \
- switch ((align)) \
- { \
- case 0: \
- *(unsigned long *) __t = *(unsigned long *) __s; \
- break; \
- case 2: \
- *__t2++ = *__s2++; \
- *__t2 = *__s2; \
- break; \
- default: \
- *__t1++ = *__s1++; \
- *__t1++ = *__s1++; \
- *__t1++ = *__s1++; \
- *__t1 = *__s1; \
- break; \
- } \
-}
-
-#define COPY_UNALIGNED_HWORD(sw, tw, align) \
- { \
- void *__s = &(sw), *__t = &(tw); \
- unsigned short *__s2 = __s, *__t2 =__t; \
- unsigned char *__s1 = __s, *__t1 =__t; \
- switch ((align)) \
- { \
- case 0: \
- *__t2 = *__s2; \
- break; \
- default: \
- *__t1++ = *__s1++; \
- *__t1 = *__s1; \
- break; \
- } \
- }
-
-int apply_relocate_add(Elf32_Shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct module *me)
-{
- unsigned int i;
- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf32_Sym *sym;
- Elf32_Addr relocation;
- uint32_t *location;
- uint32_t value;
- unsigned short *hlocation;
- unsigned short hvalue;
- int svalue;
- int align;
-
- DEBUGP("Applying relocate section %u to %u\n", relsec,
- sechdrs[relsec].sh_info);
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* This is where to make the change */
- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
- + rel[i].r_offset;
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
- + ELF32_R_SYM(rel[i].r_info);
- relocation = sym->st_value + rel[i].r_addend;
- align = (int)location & 3;
-
- switch (ELF32_R_TYPE(rel[i].r_info)) {
- case R_M32R_32_RELA:
- COPY_UNALIGNED_WORD (*location, value, align);
- value += relocation;
- COPY_UNALIGNED_WORD (value, *location, align);
- break;
- case R_M32R_HI16_ULO_RELA:
- COPY_UNALIGNED_WORD (*location, value, align);
- relocation = (relocation >>16) & 0xffff;
- /* RELA must has 0 at relocation field. */
- value += relocation;
- COPY_UNALIGNED_WORD (value, *location, align);
- break;
- case R_M32R_HI16_SLO_RELA:
- COPY_UNALIGNED_WORD (*location, value, align);
- if (relocation & 0x8000) relocation += 0x10000;
- relocation = (relocation >>16) & 0xffff;
- /* RELA must has 0 at relocation field. */
- value += relocation;
- COPY_UNALIGNED_WORD (value, *location, align);
- break;
- case R_M32R_16_RELA:
- hlocation = (unsigned short *)location;
- relocation = relocation & 0xffff;
- /* RELA must has 0 at relocation field. */
- hvalue = relocation;
- COPY_UNALIGNED_WORD (hvalue, *hlocation, align);
- break;
- case R_M32R_SDA16_RELA:
- case R_M32R_LO16_RELA:
- COPY_UNALIGNED_WORD (*location, value, align);
- relocation = relocation & 0xffff;
- /* RELA must has 0 at relocation field. */
- value += relocation;
- COPY_UNALIGNED_WORD (value, *location, align);
- break;
- case R_M32R_24_RELA:
- COPY_UNALIGNED_WORD (*location, value, align);
- relocation = relocation & 0xffffff;
- /* RELA must has 0 at relocation field. */
- value += relocation;
- COPY_UNALIGNED_WORD (value, *location, align);
- break;
- case R_M32R_18_PCREL_RELA:
- relocation = (relocation - (Elf32_Addr) location);
- if (relocation < -0x20000 || 0x1fffc < relocation)
- {
- printk(KERN_ERR "module %s: relocation overflow: %u\n",
- me->name, relocation);
- return -ENOEXEC;
- }
- COPY_UNALIGNED_WORD (*location, value, align);
- if (value & 0xffff)
- {
- /* RELA must has 0 at relocation field. */
- printk(KERN_ERR "module %s: illegal relocation field: %u\n",
- me->name, value);
- return -ENOEXEC;
- }
- relocation = (relocation >> 2) & 0xffff;
- value += relocation;
- COPY_UNALIGNED_WORD (value, *location, align);
- break;
- case R_M32R_10_PCREL_RELA:
- hlocation = (unsigned short *)location;
- relocation = (relocation - (Elf32_Addr) location);
- COPY_UNALIGNED_HWORD (*hlocation, hvalue, align);
- svalue = (int)hvalue;
- svalue = (signed char)svalue << 2;
- relocation += svalue;
- relocation = (relocation >> 2) & 0xff;
- hvalue = hvalue & 0xff00;
- hvalue += relocation;
- COPY_UNALIGNED_HWORD (hvalue, *hlocation, align);
- break;
- case R_M32R_26_PCREL_RELA:
- relocation = (relocation - (Elf32_Addr) location);
- if (relocation < -0x2000000 || 0x1fffffc < relocation)
- {
- printk(KERN_ERR "module %s: relocation overflow: %u\n",
- me->name, relocation);
- return -ENOEXEC;
- }
- COPY_UNALIGNED_WORD (*location, value, align);
- if (value & 0xffffff)
- {
- /* RELA must has 0 at relocation field. */
- printk(KERN_ERR "module %s: illegal relocation field: %u\n",
- me->name, value);
- return -ENOEXEC;
- }
- relocation = (relocation >> 2) & 0xffffff;
- value += relocation;
- COPY_UNALIGNED_WORD (value, *location, align);
- break;
- default:
- printk(KERN_ERR "module %s: Unknown relocation: %u\n",
- me->name, ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
- }
- return 0;
-}
diff --git a/arch/m32r/kernel/process.c b/arch/m32r/kernel/process.c
deleted file mode 100644
index a1a4cb136e99..000000000000
--- a/arch/m32r/kernel/process.c
+++ /dev/null
@@ -1,154 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/process.c
- *
- * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto
- * Taken from sh version.
- * Copyright (C) 1995 Linus Torvalds
- * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
- */
-
-#undef DEBUG_PROCESS
-#ifdef DEBUG_PROCESS
-#define DPRINTK(fmt, args...) printk("%s:%d:%s: " fmt, __FILE__, __LINE__, \
- __func__, ##args)
-#else
-#define DPRINTK(fmt, args...)
-#endif
-
-/*
- * This file handles the architecture-dependent parts of process handling..
- */
-
-#include <linux/fs.h>
-#include <linux/slab.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/module.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/hardirq.h>
-#include <linux/rcupdate.h>
-
-#include <asm/io.h>
-#include <linux/uaccess.h>
-#include <asm/mmu_context.h>
-#include <asm/elf.h>
-#include <asm/m32r.h>
-
-#include <linux/err.h>
-
-void (*pm_power_off)(void) = NULL;
-EXPORT_SYMBOL(pm_power_off);
-
-void machine_restart(char *__unused)
-{
-#if defined(CONFIG_PLAT_MAPPI3)
- outw(1, (unsigned long)PLD_REBOOT);
-#endif
-
- printk("Please push reset button!\n");
- while (1)
- cpu_relax();
-}
-
-void machine_halt(void)
-{
- printk("Please push reset button!\n");
- while (1)
- cpu_relax();
-}
-
-void machine_power_off(void)
-{
- /* M32R_FIXME */
-}
-
-void show_regs(struct pt_regs * regs)
-{
- printk("\n");
- show_regs_print_info(KERN_DEFAULT);
-
- printk("BPC[%08lx]:PSW[%08lx]:LR [%08lx]:FP [%08lx]\n", \
- regs->bpc, regs->psw, regs->lr, regs->fp);
- printk("BBPC[%08lx]:BBPSW[%08lx]:SPU[%08lx]:SPI[%08lx]\n", \
- regs->bbpc, regs->bbpsw, regs->spu, regs->spi);
- printk("R0 [%08lx]:R1 [%08lx]:R2 [%08lx]:R3 [%08lx]\n", \
- regs->r0, regs->r1, regs->r2, regs->r3);
- printk("R4 [%08lx]:R5 [%08lx]:R6 [%08lx]:R7 [%08lx]\n", \
- regs->r4, regs->r5, regs->r6, regs->r7);
- printk("R8 [%08lx]:R9 [%08lx]:R10[%08lx]:R11[%08lx]\n", \
- regs->r8, regs->r9, regs->r10, regs->r11);
- printk("R12[%08lx]\n", \
- regs->r12);
-
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
- printk("ACC0H[%08lx]:ACC0L[%08lx]\n", \
- regs->acc0h, regs->acc0l);
- printk("ACC1H[%08lx]:ACC1L[%08lx]\n", \
- regs->acc1h, regs->acc1l);
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
- printk("ACCH[%08lx]:ACCL[%08lx]\n", \
- regs->acc0h, regs->acc0l);
-#else
-#error unknown isa configuration
-#endif
-}
-
-void flush_thread(void)
-{
- DPRINTK("pid = %d\n", current->pid);
- memset(&current->thread.debug_trap, 0, sizeof(struct debug_trap));
-}
-
-void release_thread(struct task_struct *dead_task)
-{
- /* do nothing */
- DPRINTK("pid = %d\n", dead_task->pid);
-}
-
-/* Fill in the fpu structure for a core dump.. */
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
-{
- return 0; /* Task didn't use the fpu at all. */
-}
-
-int copy_thread(unsigned long clone_flags, unsigned long spu,
- unsigned long arg, struct task_struct *tsk)
-{
- struct pt_regs *childregs = task_pt_regs(tsk);
- extern void ret_from_fork(void);
- extern void ret_from_kernel_thread(void);
-
- if (unlikely(tsk->flags & PF_KTHREAD)) {
- memset(childregs, 0, sizeof(struct pt_regs));
- childregs->psw = M32R_PSW_BIE;
- childregs->r1 = spu; /* fn */
- childregs->r0 = arg;
- tsk->thread.lr = (unsigned long)ret_from_kernel_thread;
- } else {
- /* Copy registers */
- *childregs = *current_pt_regs();
- if (spu)
- childregs->spu = spu;
- childregs->r0 = 0; /* Child gets zero as return value */
- tsk->thread.lr = (unsigned long)ret_from_fork;
- }
- tsk->thread.sp = (unsigned long)childregs;
-
- return 0;
-}
-
-/*
- * These bracket the sleeping functions..
- */
-#define first_sched ((unsigned long) scheduling_functions_start_here)
-#define last_sched ((unsigned long) scheduling_functions_end_here)
-
-unsigned long get_wchan(struct task_struct *p)
-{
- /* M32R_FIXME */
- return (0);
-}
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c
deleted file mode 100644
index d702a5ca0f92..000000000000
--- a/arch/m32r/kernel/ptrace.c
+++ /dev/null
@@ -1,708 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/ptrace.c
- *
- * Copyright (C) 2002 Hirokazu Takata, Takeo Takahashi
- * Copyright (C) 2004 Hirokazu Takata, Kei Sakamoto
- *
- * Original x86 implementation:
- * By Ross Biro 1/23/92
- * edited by Linus Torvalds
- *
- * Some code taken from sh version:
- * Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
- * Some code taken from arm version:
- * Copyright (C) 2000 Russell King
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/err.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/string.h>
-#include <linux/signal.h>
-
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/mmu_context.h>
-
-/*
- * This routine will get a word off of the process kernel stack.
- */
-static inline unsigned long int
-get_stack_long(struct task_struct *task, int offset)
-{
- unsigned long *stack;
-
- stack = (unsigned long *)task_pt_regs(task);
-
- return stack[offset];
-}
-
-/*
- * This routine will put a word on the process kernel stack.
- */
-static inline int
-put_stack_long(struct task_struct *task, int offset, unsigned long data)
-{
- unsigned long *stack;
-
- stack = (unsigned long *)task_pt_regs(task);
- stack[offset] = data;
-
- return 0;
-}
-
-static int reg_offset[] = {
- PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
- PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_FP, PT_LR, PT_SPU,
-};
-
-/*
- * Read the word at offset "off" into the "struct user". We
- * actually access the pt_regs stored on the kernel stack.
- */
-static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
- unsigned long __user *data)
-{
- unsigned long tmp;
-#ifndef NO_FPU
- struct user * dummy = NULL;
-#endif
-
- if ((off & 3) || off > sizeof(struct user) - 3)
- return -EIO;
-
- off >>= 2;
- switch (off) {
- case PT_EVB:
- __asm__ __volatile__ (
- "mvfc %0, cr5 \n\t"
- : "=r" (tmp)
- );
- break;
- case PT_CBR: {
- unsigned long psw;
- psw = get_stack_long(tsk, PT_PSW);
- tmp = ((psw >> 8) & 1);
- }
- break;
- case PT_PSW: {
- unsigned long psw, bbpsw;
- psw = get_stack_long(tsk, PT_PSW);
- bbpsw = get_stack_long(tsk, PT_BBPSW);
- tmp = ((psw >> 8) & 0xff) | ((bbpsw & 0xff) << 8);
- }
- break;
- case PT_PC:
- tmp = get_stack_long(tsk, PT_BPC);
- break;
- case PT_BPC:
- off = PT_BBPC;
- /* fall through */
- default:
- if (off < (sizeof(struct pt_regs) >> 2))
- tmp = get_stack_long(tsk, off);
-#ifndef NO_FPU
- else if (off >= (long)(&dummy->fpu >> 2) &&
- off < (long)(&dummy->u_fpvalid >> 2)) {
- if (!tsk_used_math(tsk)) {
- if (off == (long)(&dummy->fpu.fpscr >> 2))
- tmp = FPSCR_INIT;
- else
- tmp = 0;
- } else
- tmp = ((long *)(&tsk->thread.fpu >> 2))
- [off - (long)&dummy->fpu];
- } else if (off == (long)(&dummy->u_fpvalid >> 2))
- tmp = !!tsk_used_math(tsk);
-#endif /* not NO_FPU */
- else
- tmp = 0;
- }
-
- return put_user(tmp, data);
-}
-
-static int ptrace_write_user(struct task_struct *tsk, unsigned long off,
- unsigned long data)
-{
- int ret = -EIO;
-#ifndef NO_FPU
- struct user * dummy = NULL;
-#endif
-
- if ((off & 3) || off > sizeof(struct user) - 3)
- return -EIO;
-
- off >>= 2;
- switch (off) {
- case PT_EVB:
- case PT_BPC:
- case PT_SPI:
- /* We don't allow to modify evb. */
- ret = 0;
- break;
- case PT_PSW:
- case PT_CBR: {
- /* We allow to modify only cbr in psw */
- unsigned long psw;
- psw = get_stack_long(tsk, PT_PSW);
- psw = (psw & ~0x100) | ((data & 1) << 8);
- ret = put_stack_long(tsk, PT_PSW, psw);
- }
- break;
- case PT_PC:
- off = PT_BPC;
- data &= ~1;
- /* fall through */
- default:
- if (off < (sizeof(struct pt_regs) >> 2))
- ret = put_stack_long(tsk, off, data);
-#ifndef NO_FPU
- else if (off >= (long)(&dummy->fpu >> 2) &&
- off < (long)(&dummy->u_fpvalid >> 2)) {
- set_stopped_child_used_math(tsk);
- ((long *)&tsk->thread.fpu)
- [off - (long)&dummy->fpu] = data;
- ret = 0;
- } else if (off == (long)(&dummy->u_fpvalid >> 2)) {
- conditional_stopped_child_used_math(data, tsk);
- ret = 0;
- }
-#endif /* not NO_FPU */
- break;
- }
-
- return ret;
-}
-
-/*
- * Get all user integer registers.
- */
-static int ptrace_getregs(struct task_struct *tsk, void __user *uregs)
-{
- struct pt_regs *regs = task_pt_regs(tsk);
-
- return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
-}
-
-/*
- * Set all user integer registers.
- */
-static int ptrace_setregs(struct task_struct *tsk, void __user *uregs)
-{
- struct pt_regs newregs;
- int ret;
-
- ret = -EFAULT;
- if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) {
- struct pt_regs *regs = task_pt_regs(tsk);
- *regs = newregs;
- ret = 0;
- }
-
- return ret;
-}
-
-
-static inline int
-check_condition_bit(struct task_struct *child)
-{
- return (int)((get_stack_long(child, PT_PSW) >> 8) & 1);
-}
-
-static int
-check_condition_src(unsigned long op, unsigned long regno1,
- unsigned long regno2, struct task_struct *child)
-{
- unsigned long reg1, reg2;
-
- reg2 = get_stack_long(child, reg_offset[regno2]);
-
- switch (op) {
- case 0x0: /* BEQ */
- reg1 = get_stack_long(child, reg_offset[regno1]);
- return reg1 == reg2;
- case 0x1: /* BNE */
- reg1 = get_stack_long(child, reg_offset[regno1]);
- return reg1 != reg2;
- case 0x8: /* BEQZ */
- return reg2 == 0;
- case 0x9: /* BNEZ */
- return reg2 != 0;
- case 0xa: /* BLTZ */
- return (int)reg2 < 0;
- case 0xb: /* BGEZ */
- return (int)reg2 >= 0;
- case 0xc: /* BLEZ */
- return (int)reg2 <= 0;
- case 0xd: /* BGTZ */
- return (int)reg2 > 0;
- default:
- /* never reached */
- return 0;
- }
-}
-
-static void
-compute_next_pc_for_16bit_insn(unsigned long insn, unsigned long pc,
- unsigned long *next_pc,
- struct task_struct *child)
-{
- unsigned long op, op2, op3;
- unsigned long disp;
- unsigned long regno;
- int parallel = 0;
-
- if (insn & 0x00008000)
- parallel = 1;
- if (pc & 3)
- insn &= 0x7fff; /* right slot */
- else
- insn >>= 16; /* left slot */
-
- op = (insn >> 12) & 0xf;
- op2 = (insn >> 8) & 0xf;
- op3 = (insn >> 4) & 0xf;
-
- if (op == 0x7) {
- switch (op2) {
- case 0xd: /* BNC */
- case 0x9: /* BNCL */
- if (!check_condition_bit(child)) {
- disp = (long)(insn << 24) >> 22;
- *next_pc = (pc & ~0x3) + disp;
- return;
- }
- break;
- case 0x8: /* BCL */
- case 0xc: /* BC */
- if (check_condition_bit(child)) {
- disp = (long)(insn << 24) >> 22;
- *next_pc = (pc & ~0x3) + disp;
- return;
- }
- break;
- case 0xe: /* BL */
- case 0xf: /* BRA */
- disp = (long)(insn << 24) >> 22;
- *next_pc = (pc & ~0x3) + disp;
- return;
- break;
- }
- } else if (op == 0x1) {
- switch (op2) {
- case 0x0:
- if (op3 == 0xf) { /* TRAP */
-#if 1
- /* pass through */
-#else
- /* kernel space is not allowed as next_pc */
- unsigned long evb;
- unsigned long trapno;
- trapno = insn & 0xf;
- __asm__ __volatile__ (
- "mvfc %0, cr5\n"
- :"=r"(evb)
- :
- );
- *next_pc = evb + (trapno << 2);
- return;
-#endif
- } else if (op3 == 0xd) { /* RTE */
- *next_pc = get_stack_long(child, PT_BPC);
- return;
- }
- break;
- case 0xc: /* JC */
- if (op3 == 0xc && check_condition_bit(child)) {
- regno = insn & 0xf;
- *next_pc = get_stack_long(child,
- reg_offset[regno]);
- return;
- }
- break;
- case 0xd: /* JNC */
- if (op3 == 0xc && !check_condition_bit(child)) {
- regno = insn & 0xf;
- *next_pc = get_stack_long(child,
- reg_offset[regno]);
- return;
- }
- break;
- case 0xe: /* JL */
- case 0xf: /* JMP */
- if (op3 == 0xc) { /* JMP */
- regno = insn & 0xf;
- *next_pc = get_stack_long(child,
- reg_offset[regno]);
- return;
- }
- break;
- }
- }
- if (parallel)
- *next_pc = pc + 4;
- else
- *next_pc = pc + 2;
-}
-
-static void
-compute_next_pc_for_32bit_insn(unsigned long insn, unsigned long pc,
- unsigned long *next_pc,
- struct task_struct *child)
-{
- unsigned long op;
- unsigned long op2;
- unsigned long disp;
- unsigned long regno1, regno2;
-
- op = (insn >> 28) & 0xf;
- if (op == 0xf) { /* branch 24-bit relative */
- op2 = (insn >> 24) & 0xf;
- switch (op2) {
- case 0xd: /* BNC */
- case 0x9: /* BNCL */
- if (!check_condition_bit(child)) {
- disp = (long)(insn << 8) >> 6;
- *next_pc = (pc & ~0x3) + disp;
- return;
- }
- break;
- case 0x8: /* BCL */
- case 0xc: /* BC */
- if (check_condition_bit(child)) {
- disp = (long)(insn << 8) >> 6;
- *next_pc = (pc & ~0x3) + disp;
- return;
- }
- break;
- case 0xe: /* BL */
- case 0xf: /* BRA */
- disp = (long)(insn << 8) >> 6;
- *next_pc = (pc & ~0x3) + disp;
- return;
- }
- } else if (op == 0xb) { /* branch 16-bit relative */
- op2 = (insn >> 20) & 0xf;
- switch (op2) {
- case 0x0: /* BEQ */
- case 0x1: /* BNE */
- case 0x8: /* BEQZ */
- case 0x9: /* BNEZ */
- case 0xa: /* BLTZ */
- case 0xb: /* BGEZ */
- case 0xc: /* BLEZ */
- case 0xd: /* BGTZ */
- regno1 = ((insn >> 24) & 0xf);
- regno2 = ((insn >> 16) & 0xf);
- if (check_condition_src(op2, regno1, regno2, child)) {
- disp = (long)(insn << 16) >> 14;
- *next_pc = (pc & ~0x3) + disp;
- return;
- }
- break;
- }
- }
- *next_pc = pc + 4;
-}
-
-static inline void
-compute_next_pc(unsigned long insn, unsigned long pc,
- unsigned long *next_pc, struct task_struct *child)
-{
- if (insn & 0x80000000)
- compute_next_pc_for_32bit_insn(insn, pc, next_pc, child);
- else
- compute_next_pc_for_16bit_insn(insn, pc, next_pc, child);
-}
-
-static int
-register_debug_trap(struct task_struct *child, unsigned long next_pc,
- unsigned long next_insn, unsigned long *code)
-{
- struct debug_trap *p = &child->thread.debug_trap;
- unsigned long addr = next_pc & ~3;
-
- if (p->nr_trap == MAX_TRAPS) {
- printk("kernel BUG at %s %d: p->nr_trap = %d\n",
- __FILE__, __LINE__, p->nr_trap);
- return -1;
- }
- p->addr[p->nr_trap] = addr;
- p->insn[p->nr_trap] = next_insn;
- p->nr_trap++;
- if (next_pc & 3) {
- *code = (next_insn & 0xffff0000) | 0x10f1;
- /* xxx --> TRAP1 */
- } else {
- if ((next_insn & 0x80000000) || (next_insn & 0x8000)) {
- *code = 0x10f17000;
- /* TRAP1 --> NOP */
- } else {
- *code = (next_insn & 0xffff) | 0x10f10000;
- /* TRAP1 --> xxx */
- }
- }
- return 0;
-}
-
-static int
-unregister_debug_trap(struct task_struct *child, unsigned long addr,
- unsigned long *code)
-{
- struct debug_trap *p = &child->thread.debug_trap;
- int i;
-
- /* Search debug trap entry. */
- for (i = 0; i < p->nr_trap; i++) {
- if (p->addr[i] == addr)
- break;
- }
- if (i >= p->nr_trap) {
- /* The trap may be requested from debugger.
- * ptrace should do nothing in this case.
- */
- return 0;
- }
-
- /* Recover original instruction code. */
- *code = p->insn[i];
-
- /* Shift debug trap entries. */
- while (i < p->nr_trap - 1) {
- p->insn[i] = p->insn[i + 1];
- p->addr[i] = p->addr[i + 1];
- i++;
- }
- p->nr_trap--;
- return 1;
-}
-
-static void
-unregister_all_debug_traps(struct task_struct *child)
-{
- struct debug_trap *p = &child->thread.debug_trap;
- int i;
-
- for (i = 0; i < p->nr_trap; i++)
- access_process_vm(child, p->addr[i], &p->insn[i], sizeof(p->insn[i]),
- FOLL_FORCE | FOLL_WRITE);
- p->nr_trap = 0;
-}
-
-static inline void
-invalidate_cache(void)
-{
-#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP)
-
- _flush_cache_copyback_all();
-
-#else /* ! CONFIG_CHIP_M32700 */
-
- /* Invalidate cache */
- __asm__ __volatile__ (
- "ldi r0, #-1 \n\t"
- "ldi r1, #0 \n\t"
- "stb r1, @r0 ; cache off \n\t"
- "; \n\t"
- "ldi r0, #-2 \n\t"
- "ldi r1, #1 \n\t"
- "stb r1, @r0 ; cache invalidate \n\t"
- ".fillinsn \n"
- "0: \n\t"
- "ldb r1, @r0 ; invalidate check \n\t"
- "bnez r1, 0b \n\t"
- "; \n\t"
- "ldi r0, #-1 \n\t"
- "ldi r1, #1 \n\t"
- "stb r1, @r0 ; cache on \n\t"
- : : : "r0", "r1", "memory"
- );
- /* FIXME: copying-back d-cache and invalidating i-cache are needed.
- */
-#endif /* CONFIG_CHIP_M32700 */
-}
-
-/* Embed a debug trap (TRAP1) code */
-static int
-embed_debug_trap(struct task_struct *child, unsigned long next_pc)
-{
- unsigned long next_insn, code;
- unsigned long addr = next_pc & ~3;
-
- if (access_process_vm(child, addr, &next_insn, sizeof(next_insn),
- FOLL_FORCE)
- != sizeof(next_insn)) {
- return -1; /* error */
- }
-
- /* Set a trap code. */
- if (register_debug_trap(child, next_pc, next_insn, &code)) {
- return -1; /* error */
- }
- if (access_process_vm(child, addr, &code, sizeof(code),
- FOLL_FORCE | FOLL_WRITE)
- != sizeof(code)) {
- return -1; /* error */
- }
- return 0; /* success */
-}
-
-void
-withdraw_debug_trap(struct pt_regs *regs)
-{
- unsigned long addr;
- unsigned long code;
-
- addr = (regs->bpc - 2) & ~3;
- regs->bpc -= 2;
- if (unregister_debug_trap(current, addr, &code)) {
- access_process_vm(current, addr, &code, sizeof(code),
- FOLL_FORCE | FOLL_WRITE);
- invalidate_cache();
- }
-}
-
-void
-init_debug_traps(struct task_struct *child)
-{
- struct debug_trap *p = &child->thread.debug_trap;
- int i;
- p->nr_trap = 0;
- for (i = 0; i < MAX_TRAPS; i++) {
- p->addr[i] = 0;
- p->insn[i] = 0;
- }
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- unsigned long next_pc;
- unsigned long pc, insn;
-
- clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-
- /* Compute next pc. */
- pc = get_stack_long(child, PT_BPC);
-
- if (access_process_vm(child, pc&~3, &insn, sizeof(insn),
- FOLL_FORCE)
- != sizeof(insn))
- return;
-
- compute_next_pc(insn, pc, &next_pc, child);
- if (next_pc & 0x80000000)
- return;
-
- if (embed_debug_trap(child, next_pc))
- return;
-
- invalidate_cache();
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- unregister_all_debug_traps(child);
- invalidate_cache();
-}
-
-/*
- * Called by kernel/ptrace.c when detaching..
- *
- * Make sure single step bits etc are not set.
- */
-void ptrace_disable(struct task_struct *child)
-{
- /* nothing to do.. */
-}
-
-long
-arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned long __user *datap = (unsigned long __user *) data;
-
- switch (request) {
- /*
- * read word at location "addr" in the child process.
- */
- case PTRACE_PEEKTEXT:
- case PTRACE_PEEKDATA:
- ret = generic_ptrace_peekdata(child, addr, data);
- break;
-
- /*
- * read the word at location addr in the USER area.
- */
- case PTRACE_PEEKUSR:
- ret = ptrace_read_user(child, addr, datap);
- break;
-
- /*
- * write the word at location addr.
- */
- case PTRACE_POKETEXT:
- case PTRACE_POKEDATA:
- ret = generic_ptrace_pokedata(child, addr, data);
- if (ret == 0 && request == PTRACE_POKETEXT)
- invalidate_cache();
- break;
-
- /*
- * write the word at location addr in the USER area.
- */
- case PTRACE_POKEUSR:
- ret = ptrace_write_user(child, addr, data);
- break;
-
- case PTRACE_GETREGS:
- ret = ptrace_getregs(child, datap);
- break;
-
- case PTRACE_SETREGS:
- ret = ptrace_setregs(child, datap);
- break;
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-/* notification of system call entry/exit
- * - triggered by current->work.syscall_trace
- */
-void do_syscall_trace(void)
-{
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return;
- if (!(current->ptrace & PT_PTRACED))
- return;
- /* the 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
-
- /*
- * this isn't the same as continuing with a signal, but it will do
- * for normal use. strace only continues with a signal if the
- * stopping signal is not SIGTRAP. -brl
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
-}
diff --git a/arch/m32r/kernel/setup.c b/arch/m32r/kernel/setup.c
deleted file mode 100644
index b72d5db39f00..000000000000
--- a/arch/m32r/kernel/setup.c
+++ /dev/null
@@ -1,424 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/setup.c
- *
- * Setup routines for Renesas M32R
- *
- * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/stddef.h>
-#include <linux/fs.h>
-#include <linux/sched/mm.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <linux/console.h>
-#include <linux/initrd.h>
-#include <linux/major.h>
-#include <linux/root_dev.h>
-#include <linux/seq_file.h>
-#include <linux/timex.h>
-#include <linux/screen_info.h>
-#include <linux/cpu.h>
-#include <linux/nodemask.h>
-#include <linux/pfn.h>
-
-#include <asm/processor.h>
-#include <asm/pgtable.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <asm/m32r.h>
-#include <asm/setup.h>
-#include <asm/sections.h>
-
-#ifdef CONFIG_MMU
-extern void init_mmu(void);
-#endif
-
-extern char _end[];
-
-/*
- * Machine setup..
- */
-struct cpuinfo_m32r boot_cpu_data;
-
-#ifdef CONFIG_BLK_DEV_RAM
-extern int rd_doload; /* 1 = load ramdisk, 0 = don't load */
-extern int rd_prompt; /* 1 = prompt for ramdisk, 0 = don't prompt */
-extern int rd_image_start; /* starting block # of image */
-#endif
-
-#if defined(CONFIG_VGA_CONSOLE)
-struct screen_info screen_info = {
- .orig_video_lines = 25,
- .orig_video_cols = 80,
- .orig_video_mode = 0,
- .orig_video_ega_bx = 0,
- .orig_video_isVGA = 1,
- .orig_video_points = 8
-};
-#endif
-
-extern int root_mountflags;
-
-static char __initdata command_line[COMMAND_LINE_SIZE];
-
-static struct resource data_resource = {
- .name = "Kernel data",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
-};
-
-static struct resource code_resource = {
- .name = "Kernel code",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
-};
-
-unsigned long memory_start;
-EXPORT_SYMBOL(memory_start);
-
-unsigned long memory_end;
-EXPORT_SYMBOL(memory_end);
-
-void __init setup_arch(char **);
-int get_cpuinfo(char *);
-
-static __inline__ void parse_mem_cmdline(char ** cmdline_p)
-{
- char c = ' ';
- char *to = command_line;
- char *from = COMMAND_LINE;
- int len = 0;
- int usermem = 0;
-
- /* Save unparsed command line copy for /proc/cmdline */
- memcpy(boot_command_line, COMMAND_LINE, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
-
- memory_start = (unsigned long)CONFIG_MEMORY_START+PAGE_OFFSET;
- memory_end = memory_start+(unsigned long)CONFIG_MEMORY_SIZE;
-
- for ( ; ; ) {
- if (c == ' ' && !memcmp(from, "mem=", 4)) {
- if (to != command_line)
- to--;
-
- {
- unsigned long mem_size;
-
- usermem = 1;
- mem_size = memparse(from+4, &from);
- memory_end = memory_start + mem_size;
- }
- }
- c = *(from++);
- if (!c)
- break;
-
- if (COMMAND_LINE_SIZE <= ++len)
- break;
-
- *(to++) = c;
- }
- *to = '\0';
- *cmdline_p = command_line;
- if (usermem)
- printk(KERN_INFO "user-defined physical RAM map:\n");
-}
-
-#ifndef CONFIG_DISCONTIGMEM
-static unsigned long __init setup_memory(void)
-{
- unsigned long start_pfn, max_low_pfn, bootmap_size;
-
- start_pfn = PFN_UP( __pa(_end) );
- max_low_pfn = PFN_DOWN( __pa(memory_end) );
-
- /*
- * Initialize the boot-time allocator (with low memory only):
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
- CONFIG_MEMORY_START>>PAGE_SHIFT, max_low_pfn);
-
- /*
- * Register fully available low RAM pages with the bootmem allocator.
- */
- {
- unsigned long curr_pfn;
- unsigned long last_pfn;
- unsigned long pages;
-
- /*
- * We are rounding up the start address of usable memory:
- */
- curr_pfn = PFN_UP(__pa(memory_start));
-
- /*
- * ... and at the end of the usable range downwards:
- */
- last_pfn = PFN_DOWN(__pa(memory_end));
-
- if (last_pfn > max_low_pfn)
- last_pfn = max_low_pfn;
-
- pages = last_pfn - curr_pfn;
- free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(pages));
- }
-
- /*
- * Reserve the kernel text and
- * Reserve the bootmem bitmap. We do this in two steps (first step
- * was init_bootmem()), because this catches the (definitely buggy)
- * case of us accidentally initializing the bootmem allocator with
- * an invalid RAM area.
- */
- reserve_bootmem(CONFIG_MEMORY_START + PAGE_SIZE,
- (PFN_PHYS(start_pfn) + bootmap_size + PAGE_SIZE - 1)
- - CONFIG_MEMORY_START,
- BOOTMEM_DEFAULT);
-
- /*
- * reserve physical page 0 - it's a special BIOS page on many boxes,
- * enabling clean reboots, SMP operation, laptop functions.
- */
- reserve_bootmem(CONFIG_MEMORY_START, PAGE_SIZE, BOOTMEM_DEFAULT);
-
- /*
- * reserve memory hole
- */
-#ifdef CONFIG_MEMHOLE
- reserve_bootmem(CONFIG_MEMHOLE_START, CONFIG_MEMHOLE_SIZE,
- BOOTMEM_DEFAULT);
-#endif
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (LOADER_TYPE && INITRD_START) {
- if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
- reserve_bootmem(INITRD_START, INITRD_SIZE,
- BOOTMEM_DEFAULT);
- initrd_start = INITRD_START + PAGE_OFFSET;
- initrd_end = initrd_start + INITRD_SIZE;
- printk("initrd:start[%08lx],size[%08lx]\n",
- initrd_start, INITRD_SIZE);
- } else {
- printk("initrd extends beyond end of memory "
- "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
- INITRD_START + INITRD_SIZE,
- max_low_pfn << PAGE_SHIFT);
-
- initrd_start = 0;
- }
- }
-#endif
-
- return max_low_pfn;
-}
-#else /* CONFIG_DISCONTIGMEM */
-extern unsigned long setup_memory(void);
-#endif /* CONFIG_DISCONTIGMEM */
-
-void __init setup_arch(char **cmdline_p)
-{
- ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
-
- boot_cpu_data.cpu_clock = M32R_CPUCLK;
- boot_cpu_data.bus_clock = M32R_BUSCLK;
- boot_cpu_data.timer_divide = M32R_TIMER_DIVIDE;
-
-#ifdef CONFIG_BLK_DEV_RAM
- rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
- rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
- rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
-#endif
-
- if (!MOUNT_ROOT_RDONLY)
- root_mountflags &= ~MS_RDONLY;
-
-#ifdef CONFIG_VT
-#if defined(CONFIG_VGA_CONSOLE)
- conswitchp = &vga_con;
-#elif defined(CONFIG_DUMMY_CONSOLE)
- conswitchp = &dummy_con;
-#endif
-#endif
-
-#ifdef CONFIG_DISCONTIGMEM
- nodes_clear(node_online_map);
- node_set_online(0);
- node_set_online(1);
-#endif /* CONFIG_DISCONTIGMEM */
-
- init_mm.start_code = (unsigned long) _text;
- init_mm.end_code = (unsigned long) _etext;
- init_mm.end_data = (unsigned long) _edata;
- init_mm.brk = (unsigned long) _end;
-
- code_resource.start = virt_to_phys(_text);
- code_resource.end = virt_to_phys(_etext)-1;
- data_resource.start = virt_to_phys(_etext);
- data_resource.end = virt_to_phys(_edata)-1;
-
- parse_mem_cmdline(cmdline_p);
-
- setup_memory();
-
- paging_init();
-}
-
-static struct cpu cpu_devices[NR_CPUS];
-
-static int __init topology_init(void)
-{
- int i;
-
- for_each_present_cpu(i)
- register_cpu(&cpu_devices[i], i);
-
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-#ifdef CONFIG_PROC_FS
-/*
- * Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- struct cpuinfo_m32r *c = v;
- unsigned long cpu = c - cpu_data;
-
-#ifdef CONFIG_SMP
- if (!cpu_online(cpu))
- return 0;
-#endif /* CONFIG_SMP */
-
- seq_printf(m, "processor\t: %ld\n", cpu);
-
-#if defined(CONFIG_CHIP_VDEC2)
- seq_printf(m, "cpu family\t: VDEC2\n"
- "cache size\t: Unknown\n");
-#elif defined(CONFIG_CHIP_M32700)
- seq_printf(m,"cpu family\t: M32700\n"
- "cache size\t: I-8KB/D-8KB\n");
-#elif defined(CONFIG_CHIP_M32102)
- seq_printf(m,"cpu family\t: M32102\n"
- "cache size\t: I-8KB\n");
-#elif defined(CONFIG_CHIP_OPSP)
- seq_printf(m,"cpu family\t: OPSP\n"
- "cache size\t: I-8KB/D-8KB\n");
-#elif defined(CONFIG_CHIP_MP)
- seq_printf(m, "cpu family\t: M32R-MP\n"
- "cache size\t: I-xxKB/D-xxKB\n");
-#elif defined(CONFIG_CHIP_M32104)
- seq_printf(m,"cpu family\t: M32104\n"
- "cache size\t: I-8KB/D-8KB\n");
-#else
- seq_printf(m, "cpu family\t: Unknown\n");
-#endif
- seq_printf(m, "bogomips\t: %lu.%02lu\n",
- c->loops_per_jiffy/(500000/HZ),
- (c->loops_per_jiffy/(5000/HZ)) % 100);
-#if defined(CONFIG_PLAT_MAPPI)
- seq_printf(m, "Machine\t\t: Mappi Evaluation board\n");
-#elif defined(CONFIG_PLAT_MAPPI2)
- seq_printf(m, "Machine\t\t: Mappi-II Evaluation board\n");
-#elif defined(CONFIG_PLAT_MAPPI3)
- seq_printf(m, "Machine\t\t: Mappi-III Evaluation board\n");
-#elif defined(CONFIG_PLAT_M32700UT)
- seq_printf(m, "Machine\t\t: M32700UT Evaluation board\n");
-#elif defined(CONFIG_PLAT_OPSPUT)
- seq_printf(m, "Machine\t\t: OPSPUT Evaluation board\n");
-#elif defined(CONFIG_PLAT_USRV)
- seq_printf(m, "Machine\t\t: uServer\n");
-#elif defined(CONFIG_PLAT_OAKS32R)
- seq_printf(m, "Machine\t\t: OAKS32R\n");
-#elif defined(CONFIG_PLAT_M32104UT)
- seq_printf(m, "Machine\t\t: M3T-M32104UT uT Engine board\n");
-#else
- seq_printf(m, "Machine\t\t: Unknown\n");
-#endif
-
-#define PRINT_CLOCK(name, value) \
- seq_printf(m, name " clock\t: %d.%02dMHz\n", \
- ((value) / 1000000), ((value) % 1000000)/10000)
-
- PRINT_CLOCK("CPU", (int)c->cpu_clock);
- PRINT_CLOCK("Bus", (int)c->bus_clock);
-
- seq_printf(m, "\n");
-
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return *pos < NR_CPUS ? cpu_data + *pos : NULL;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-#endif /* CONFIG_PROC_FS */
-
-unsigned long cpu_initialized __initdata = 0;
-
-/*
- * cpu_init() initializes state that is per-CPU. Some data is already
- * initialized (naturally) in the bootstrap process.
- * We reload them nevertheless, this function acts as a
- * 'CPU state barrier', nothing should get across.
- */
-#if defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \
- || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \
- || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-void __init cpu_init (void)
-{
- int cpu_id = smp_processor_id();
-
- if (test_and_set_bit(cpu_id, &cpu_initialized)) {
- printk(KERN_WARNING "CPU#%d already initialized!\n", cpu_id);
- for ( ; ; )
- local_irq_enable();
- }
- printk(KERN_INFO "Initializing CPU#%d\n", cpu_id);
-
- /* Set up and load the per-CPU TSS and LDT */
- mmgrab(&init_mm);
- current->active_mm = &init_mm;
- if (current->mm)
- BUG();
-
- /* Force FPU initialization */
- current_thread_info()->status = 0;
- clear_used_math();
-
-#ifdef CONFIG_MMU
- /* Set up MMU */
- init_mmu();
-#endif
-
- /* Set up ICUIMASK */
- outl(0x00070000, M32R_ICU_IMASK_PORTL); /* imask=111 */
-}
-#endif /* defined(CONFIG_CHIP_VDEC2) ... */
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c
deleted file mode 100644
index ba4d8d6330f1..000000000000
--- a/arch/m32r/kernel/signal.c
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/signal.c
- *
- * Copyright (c) 2003 Hitoshi Yamamoto
- *
- * Taken from i386 version.
- * Copyright (C) 1991, 1992 Linus Torvalds
- *
- * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson
- * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes
- */
-
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/personality.h>
-#include <linux/tracehook.h>
-#include <asm/cacheflush.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-
-#define DEBUG_SIG 0
-
-/*
- * Do a signal return; undo the signal stack.
- */
-
-struct rt_sigframe
-{
- int sig;
- struct siginfo __user *pinfo;
- void __user *puc;
- struct siginfo info;
- struct ucontext uc;
-// struct _fpstate fpstate;
-};
-
-static int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc,
- int *r0_p)
-{
- unsigned int err = 0;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
-#define COPY(x) err |= __get_user(regs->x, &sc->sc_##x)
- COPY(r4);
- COPY(r5);
- COPY(r6);
- COPY(pt_regs);
- /* COPY(r0); Skip r0 */
- COPY(r1);
- COPY(r2);
- COPY(r3);
- COPY(r7);
- COPY(r8);
- COPY(r9);
- COPY(r10);
- COPY(r11);
- COPY(r12);
- COPY(acc0h);
- COPY(acc0l);
- COPY(acc1h); /* ISA_DSP_LEVEL2 only */
- COPY(acc1l); /* ISA_DSP_LEVEL2 only */
- COPY(psw);
- COPY(bpc);
- COPY(bbpsw);
- COPY(bbpc);
- COPY(spu);
- COPY(fp);
- COPY(lr);
- COPY(spi);
-#undef COPY
-
- regs->syscall_nr = -1; /* disable syscall checks */
- err |= __get_user(*r0_p, &sc->sc_r0);
-
- return err;
-}
-
-asmlinkage int
-sys_rt_sigreturn(unsigned long r0, unsigned long r1,
- unsigned long r2, unsigned long r3, unsigned long r4,
- unsigned long r5, unsigned long r6, struct pt_regs *regs)
-{
- struct rt_sigframe __user *frame = (struct rt_sigframe __user *)regs->spu;
- sigset_t set;
- int result;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &result))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return result;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/*
- * Set up a signal frame.
- */
-
-static int
-setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
- unsigned long mask)
-{
- int err = 0;
-
-#define COPY(x) err |= __put_user(regs->x, &sc->sc_##x)
- COPY(r4);
- COPY(r5);
- COPY(r6);
- COPY(pt_regs);
- COPY(r0);
- COPY(r1);
- COPY(r2);
- COPY(r3);
- COPY(r7);
- COPY(r8);
- COPY(r9);
- COPY(r10);
- COPY(r11);
- COPY(r12);
- COPY(acc0h);
- COPY(acc0l);
- COPY(acc1h); /* ISA_DSP_LEVEL2 only */
- COPY(acc1l); /* ISA_DSP_LEVEL2 only */
- COPY(psw);
- COPY(bpc);
- COPY(bbpsw);
- COPY(bbpc);
- COPY(spu);
- COPY(fp);
- COPY(lr);
- COPY(spi);
-#undef COPY
-
- err |= __put_user(mask, &sc->oldmask);
-
- return err;
-}
-
-/*
- * Determine which stack to use..
- */
-static inline void __user *
-get_sigframe(struct ksignal *ksig, unsigned long sp, size_t frame_size)
-{
- return (void __user *)((sigsp(sp, ksig) - frame_size) & -8ul);
-}
-
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct rt_sigframe __user *frame;
- int err = 0;
- int sig = ksig->sig;
-
- frame = get_sigframe(ksig, regs->spu, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err |= __put_user(sig, &frame->sig);
- if (err)
- return -EFAULT;
-
- err |= __put_user(&frame->info, &frame->pinfo);
- err |= __put_user(&frame->uc, &frame->puc);
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
- if (err)
- return -EFAULT;
-
- /* Create the ucontext. */
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(0, &frame->uc.uc_link);
- err |= __save_altstack(&frame->uc.uc_stack, regs->spu);
- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs, set->sig[0]);
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
- if (err)
- return -EFAULT;
-
- /* Set up to return from userspace. */
- regs->lr = (unsigned long)ksig->ka.sa.sa_restorer;
-
- /* Set up registers for signal handler */
- regs->spu = (unsigned long)frame;
- regs->r0 = sig; /* Arg for signal handler */
- regs->r1 = (unsigned long)&frame->info;
- regs->r2 = (unsigned long)&frame->uc;
- regs->bpc = (unsigned long)ksig->ka.sa.sa_handler;
-
-#if DEBUG_SIG
- printk("SIG deliver (%s:%d): sp=%p pc=%p\n",
- current->comm, current->pid, frame, regs->pc);
-#endif
-
- return 0;
-}
-
-static int prev_insn(struct pt_regs *regs)
-{
- u16 inst;
- if (get_user(inst, (u16 __user *)(regs->bpc - 2)))
- return -EFAULT;
- if ((inst & 0xfff0) == 0x10f0) /* trap ? */
- regs->bpc -= 2;
- else
- regs->bpc -= 4;
- regs->syscall_nr = -1;
- return 0;
-}
-
-/*
- * OK, we're invoking a handler
- */
-
-static void
-handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- int ret;
-
- /* Are we from a system call? */
- if (regs->syscall_nr >= 0) {
- /* If so, check system call restarting.. */
- switch (regs->r0) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- regs->r0 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->r0 = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- regs->r0 = regs->orig_r0;
- if (prev_insn(regs) < 0)
- return;
- }
- }
-
- /* Set up the stack frame */
- ret = setup_rt_frame(ksig, sigmask_to_save(), regs);
-
- signal_setup_done(ret, ksig, 0);
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- */
-static void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- /*
- * We want the common case to go fast, which
- * is why we may in certain cases get here from
- * kernel mode. Just return without doing anything
- * if so.
- */
- if (!user_mode(regs))
- return;
-
- if (get_signal(&ksig)) {
- /* Re-enable any watchpoints before delivering the
- * signal to user space. The processor register will
- * have been cleared if the watchpoint triggered
- * inside the kernel.
- */
-
- /* Whee! Actually deliver the signal. */
- handle_signal(&ksig, regs);
-
- return;
- }
-
- /* Did we come from a system call? */
- if (regs->syscall_nr >= 0) {
- /* Restart the system call - no handlers present */
- if (regs->r0 == -ERESTARTNOHAND ||
- regs->r0 == -ERESTARTSYS ||
- regs->r0 == -ERESTARTNOINTR) {
- regs->r0 = regs->orig_r0;
- prev_insn(regs);
- } else if (regs->r0 == -ERESTART_RESTARTBLOCK){
- regs->r0 = regs->orig_r0;
- regs->r7 = __NR_restart_syscall;
- prev_insn(regs);
- }
- }
- restore_saved_sigmask();
-}
-
-/*
- * notification of userspace execution resumption
- * - triggered by current->work.notify_resume
- */
-void do_notify_resume(struct pt_regs *regs, __u32 thread_info_flags)
-{
- /* Pending single-step? */
- if (thread_info_flags & _TIF_SINGLESTEP)
- clear_thread_flag(TIF_SINGLESTEP);
-
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal(regs);
-
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c
deleted file mode 100644
index 564052e3d3a0..000000000000
--- a/arch/m32r/kernel/smp.c
+++ /dev/null
@@ -1,836 +0,0 @@
-/*
- * linux/arch/m32r/kernel/smp.c
- *
- * M32R SMP support routines.
- *
- * Copyright (c) 2001, 2002 Hitoshi Yamamoto
- *
- * Taken from i386 version.
- * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
- * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
- *
- * This code is released under the GNU General Public License version 2 or
- * later.
- */
-
-#undef DEBUG_SMP
-
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/profile.h>
-#include <linux/cpu.h>
-
-#include <asm/cacheflush.h>
-#include <asm/pgalloc.h>
-#include <linux/atomic.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <asm/m32r.h>
-#include <asm/tlbflush.h>
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Data structures and variables */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/*
- * For flush_cache_all()
- */
-static DEFINE_SPINLOCK(flushcache_lock);
-static volatile unsigned long flushcache_cpumask = 0;
-
-/*
- * For flush_tlb_others()
- */
-static cpumask_t flush_cpumask;
-static struct mm_struct *flush_mm;
-static struct vm_area_struct *flush_vma;
-static volatile unsigned long flush_va;
-static DEFINE_SPINLOCK(tlbstate_lock);
-#define FLUSH_ALL 0xffffffff
-
-DECLARE_PER_CPU(int, prof_multiplier);
-DECLARE_PER_CPU(int, prof_old_multiplier);
-DECLARE_PER_CPU(int, prof_counter);
-
-extern spinlock_t ipi_lock[];
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Function Prototypes */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-void smp_reschedule_interrupt(void);
-void smp_flush_cache_all_interrupt(void);
-
-static void flush_tlb_all_ipi(void *);
-static void flush_tlb_others(cpumask_t, struct mm_struct *,
- struct vm_area_struct *, unsigned long);
-
-void smp_invalidate_interrupt(void);
-
-static void stop_this_cpu(void *);
-
-void smp_ipi_timer_interrupt(struct pt_regs *);
-void smp_local_timer_interrupt(void);
-
-static void send_IPI_allbutself(int, int);
-static void send_IPI_mask(const struct cpumask *, int, int);
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Rescheduling request Routines */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/*==========================================================================*
- * Name: smp_send_reschedule
- *
- * Description: This routine requests other CPU to execute rescheduling.
- * 1.Send 'RESCHEDULE_IPI' to other CPU.
- * Request other CPU to execute 'smp_reschedule_interrupt()'.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: cpu_id - Target CPU ID
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_send_reschedule(int cpu_id)
-{
- WARN_ON(cpu_is_offline(cpu_id));
- send_IPI_mask(cpumask_of(cpu_id), RESCHEDULE_IPI, 1);
-}
-
-/*==========================================================================*
- * Name: smp_reschedule_interrupt
- *
- * Description: This routine executes on CPU which received
- * 'RESCHEDULE_IPI'.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_reschedule_interrupt(void)
-{
- scheduler_ipi();
-}
-
-/*==========================================================================*
- * Name: smp_flush_cache_all
- *
- * Description: This routine sends a 'INVALIDATE_CACHE_IPI' to all other
- * CPUs in the system.
- *
- * Born on Date: 2003-05-28
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_flush_cache_all(void)
-{
- cpumask_t cpumask;
- unsigned long *mask;
-
- preempt_disable();
- cpumask_copy(&cpumask, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &cpumask);
- spin_lock(&flushcache_lock);
- mask=cpumask_bits(&cpumask);
- atomic_or(*mask, (atomic_t *)&flushcache_cpumask);
- send_IPI_mask(&cpumask, INVALIDATE_CACHE_IPI, 0);
- _flush_cache_copyback_all();
- while (flushcache_cpumask)
- mb();
- spin_unlock(&flushcache_lock);
- preempt_enable();
-}
-EXPORT_SYMBOL(smp_flush_cache_all);
-
-void smp_flush_cache_all_interrupt(void)
-{
- _flush_cache_copyback_all();
- clear_bit(smp_processor_id(), &flushcache_cpumask);
-}
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* TLB flush request Routines */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/*==========================================================================*
- * Name: smp_flush_tlb_all
- *
- * Description: This routine flushes all processes TLBs.
- * 1.Request other CPU to execute 'flush_tlb_all_ipi()'.
- * 2.Execute 'do_flush_tlb_all_local()'.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_flush_tlb_all(void)
-{
- unsigned long flags;
-
- preempt_disable();
- local_irq_save(flags);
- __flush_tlb_all();
- local_irq_restore(flags);
- smp_call_function(flush_tlb_all_ipi, NULL, 1);
- preempt_enable();
-}
-
-/*==========================================================================*
- * Name: flush_tlb_all_ipi
- *
- * Description: This routine flushes all local TLBs.
- * 1.Execute 'do_flush_tlb_all_local()'.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: *info - not used
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-static void flush_tlb_all_ipi(void *info)
-{
- __flush_tlb_all();
-}
-
-/*==========================================================================*
- * Name: smp_flush_tlb_mm
- *
- * Description: This routine flushes the specified mm context TLB's.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: *mm - a pointer to the mm struct for flush TLB
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_flush_tlb_mm(struct mm_struct *mm)
-{
- int cpu_id;
- cpumask_t cpu_mask;
- unsigned long *mmc;
- unsigned long flags;
-
- preempt_disable();
- cpu_id = smp_processor_id();
- mmc = &mm->context[cpu_id];
- cpumask_copy(&cpu_mask, mm_cpumask(mm));
- cpumask_clear_cpu(cpu_id, &cpu_mask);
-
- if (*mmc != NO_CONTEXT) {
- local_irq_save(flags);
- *mmc = NO_CONTEXT;
- if (mm == current->mm)
- activate_context(mm);
- else
- cpumask_clear_cpu(cpu_id, mm_cpumask(mm));
- local_irq_restore(flags);
- }
- if (!cpumask_empty(&cpu_mask))
- flush_tlb_others(cpu_mask, mm, NULL, FLUSH_ALL);
-
- preempt_enable();
-}
-
-/*==========================================================================*
- * Name: smp_flush_tlb_range
- *
- * Description: This routine flushes a range of pages.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: *mm - a pointer to the mm struct for flush TLB
- * start - not used
- * end - not used
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end)
-{
- smp_flush_tlb_mm(vma->vm_mm);
-}
-
-/*==========================================================================*
- * Name: smp_flush_tlb_page
- *
- * Description: This routine flushes one page.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: *vma - a pointer to the vma struct include va
- * va - virtual address for flush TLB
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
-{
- struct mm_struct *mm = vma->vm_mm;
- int cpu_id;
- cpumask_t cpu_mask;
- unsigned long *mmc;
- unsigned long flags;
-
- preempt_disable();
- cpu_id = smp_processor_id();
- mmc = &mm->context[cpu_id];
- cpumask_copy(&cpu_mask, mm_cpumask(mm));
- cpumask_clear_cpu(cpu_id, &cpu_mask);
-
-#ifdef DEBUG_SMP
- if (!mm)
- BUG();
-#endif
-
- if (*mmc != NO_CONTEXT) {
- local_irq_save(flags);
- va &= PAGE_MASK;
- va |= (*mmc & MMU_CONTEXT_ASID_MASK);
- __flush_tlb_page(va);
- local_irq_restore(flags);
- }
- if (!cpumask_empty(&cpu_mask))
- flush_tlb_others(cpu_mask, mm, vma, va);
-
- preempt_enable();
-}
-
-/*==========================================================================*
- * Name: flush_tlb_others
- *
- * Description: This routine requests other CPU to execute flush TLB.
- * 1.Setup parameters.
- * 2.Send 'INVALIDATE_TLB_IPI' to other CPU.
- * Request other CPU to execute 'smp_invalidate_interrupt()'.
- * 3.Wait for other CPUs operation finished.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: cpumask - bitmap of target CPUs
- * *mm - a pointer to the mm struct for flush TLB
- * *vma - a pointer to the vma struct include va
- * va - virtual address for flush TLB
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
- struct vm_area_struct *vma, unsigned long va)
-{
- unsigned long *mask;
-#ifdef DEBUG_SMP
- unsigned long flags;
- __save_flags(flags);
- if (!(flags & 0x0040)) /* Interrupt Disable NONONO */
- BUG();
-#endif /* DEBUG_SMP */
-
- /*
- * A couple of (to be removed) sanity checks:
- *
- * - we do not send IPIs to not-yet booted CPUs.
- * - current CPU must not be in mask
- * - mask must exist :)
- */
- BUG_ON(cpumask_empty(&cpumask));
-
- BUG_ON(cpumask_test_cpu(smp_processor_id(), &cpumask));
- BUG_ON(!mm);
-
- /* If a CPU which we ran on has gone down, OK. */
- cpumask_and(&cpumask, &cpumask, cpu_online_mask);
- if (cpumask_empty(&cpumask))
- return;
-
- /*
- * i'm not happy about this global shared spinlock in the
- * MM hot path, but we'll see how contended it is.
- * Temporarily this turns IRQs off, so that lockups are
- * detected by the NMI watchdog.
- */
- spin_lock(&tlbstate_lock);
-
- flush_mm = mm;
- flush_vma = vma;
- flush_va = va;
- mask=cpumask_bits(&cpumask);
- atomic_or(*mask, (atomic_t *)&flush_cpumask);
-
- /*
- * We have to send the IPI only to
- * CPUs affected.
- */
- send_IPI_mask(&cpumask, INVALIDATE_TLB_IPI, 0);
-
- while (!cpumask_empty(&flush_cpumask)) {
- /* nothing. lockup detection does not belong here */
- mb();
- }
-
- flush_mm = NULL;
- flush_vma = NULL;
- flush_va = 0;
- spin_unlock(&tlbstate_lock);
-}
-
-/*==========================================================================*
- * Name: smp_invalidate_interrupt
- *
- * Description: This routine executes on CPU which received
- * 'INVALIDATE_TLB_IPI'.
- * 1.Flush local TLB.
- * 2.Report flush TLB process was finished.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_invalidate_interrupt(void)
-{
- int cpu_id = smp_processor_id();
- unsigned long *mmc = &flush_mm->context[cpu_id];
-
- if (!cpumask_test_cpu(cpu_id, &flush_cpumask))
- return;
-
- if (flush_va == FLUSH_ALL) {
- *mmc = NO_CONTEXT;
- if (flush_mm == current->active_mm)
- activate_context(flush_mm);
- else
- cpumask_clear_cpu(cpu_id, mm_cpumask(flush_mm));
- } else {
- unsigned long va = flush_va;
-
- if (*mmc != NO_CONTEXT) {
- va &= PAGE_MASK;
- va |= (*mmc & MMU_CONTEXT_ASID_MASK);
- __flush_tlb_page(va);
- }
- }
- cpumask_clear_cpu(cpu_id, &flush_cpumask);
-}
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Stop CPU request Routines */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/*==========================================================================*
- * Name: smp_send_stop
- *
- * Description: This routine requests stop all CPUs.
- * 1.Request other CPU to execute 'stop_this_cpu()'.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_send_stop(void)
-{
- smp_call_function(stop_this_cpu, NULL, 0);
-}
-
-/*==========================================================================*
- * Name: stop_this_cpu
- *
- * Description: This routine halt CPU.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-static void stop_this_cpu(void *dummy)
-{
- int cpu_id = smp_processor_id();
-
- /*
- * Remove this CPU:
- */
- set_cpu_online(cpu_id, false);
-
- /*
- * PSW IE = 1;
- * IMASK = 0;
- * goto SLEEP
- */
- local_irq_disable();
- outl(0, M32R_ICU_IMASK_PORTL);
- inl(M32R_ICU_IMASK_PORTL); /* dummy read */
- local_irq_enable();
-
- for ( ; ; );
-}
-
-void arch_send_call_function_ipi_mask(const struct cpumask *mask)
-{
- send_IPI_mask(mask, CALL_FUNCTION_IPI, 0);
-}
-
-void arch_send_call_function_single_ipi(int cpu)
-{
- send_IPI_mask(cpumask_of(cpu), CALL_FUNC_SINGLE_IPI, 0);
-}
-
-/*==========================================================================*
- * Name: smp_call_function_interrupt
- *
- * Description: This routine executes on CPU which received
- * 'CALL_FUNCTION_IPI'.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_call_function_interrupt(void)
-{
- irq_enter();
- generic_smp_call_function_interrupt();
- irq_exit();
-}
-
-void smp_call_function_single_interrupt(void)
-{
- irq_enter();
- generic_smp_call_function_single_interrupt();
- irq_exit();
-}
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Timer Routines */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/*==========================================================================*
- * Name: smp_send_timer
- *
- * Description: This routine sends a 'LOCAL_TIMER_IPI' to all other CPUs
- * in the system.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_send_timer(void)
-{
- send_IPI_allbutself(LOCAL_TIMER_IPI, 1);
-}
-
-/*==========================================================================*
- * Name: smp_send_timer
- *
- * Description: This routine executes on CPU which received
- * 'LOCAL_TIMER_IPI'.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: *regs - a pointer to the saved regster info
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-void smp_ipi_timer_interrupt(struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
- old_regs = set_irq_regs(regs);
- irq_enter();
- smp_local_timer_interrupt();
- irq_exit();
- set_irq_regs(old_regs);
-}
-
-/*==========================================================================*
- * Name: smp_local_timer_interrupt
- *
- * Description: Local timer interrupt handler. It does both profiling and
- * process statistics/rescheduling.
- * We do profiling in every local tick, statistics/rescheduling
- * happen only every 'profiling multiplier' ticks. The default
- * multiplier is 1 and it can be changed by writing the new
- * multiplier value into /proc/profile.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: *regs - a pointer to the saved regster info
- *
- * Returns: void (cannot fail)
- *
- * Original: arch/i386/kernel/apic.c
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- * 2003-06-24 hy use per_cpu structure.
- *==========================================================================*/
-void smp_local_timer_interrupt(void)
-{
- int user = user_mode(get_irq_regs());
- int cpu_id = smp_processor_id();
-
- /*
- * The profiling function is SMP safe. (nothing can mess
- * around with "current", and the profiling counters are
- * updated with atomic operations). This is especially
- * useful with a profiling multiplier != 1
- */
-
- profile_tick(CPU_PROFILING);
-
- if (--per_cpu(prof_counter, cpu_id) <= 0) {
- /*
- * The multiplier may have changed since the last time we got
- * to this point as a result of the user writing to
- * /proc/profile. In this case we need to adjust the APIC
- * timer accordingly.
- *
- * Interrupts are already masked off at this point.
- */
- per_cpu(prof_counter, cpu_id)
- = per_cpu(prof_multiplier, cpu_id);
- if (per_cpu(prof_counter, cpu_id)
- != per_cpu(prof_old_multiplier, cpu_id))
- {
- per_cpu(prof_old_multiplier, cpu_id)
- = per_cpu(prof_counter, cpu_id);
- }
-
- update_process_times(user);
- }
-}
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Send IPI Routines */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/*==========================================================================*
- * Name: send_IPI_allbutself
- *
- * Description: This routine sends a IPI to all other CPUs in the system.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: ipi_num - Number of IPI
- * try - 0 : Send IPI certainly.
- * !0 : The following IPI is not sent when Target CPU
- * has not received the before IPI.
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-static void send_IPI_allbutself(int ipi_num, int try)
-{
- cpumask_t cpumask;
-
- cpumask_copy(&cpumask, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &cpumask);
-
- send_IPI_mask(&cpumask, ipi_num, try);
-}
-
-/*==========================================================================*
- * Name: send_IPI_mask
- *
- * Description: This routine sends a IPI to CPUs in the system.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: cpu_mask - Bitmap of target CPUs logical ID
- * ipi_num - Number of IPI
- * try - 0 : Send IPI certainly.
- * !0 : The following IPI is not sent when Target CPU
- * has not received the before IPI.
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-static void send_IPI_mask(const struct cpumask *cpumask, int ipi_num, int try)
-{
- cpumask_t physid_mask, tmp;
- int cpu_id, phys_id;
- int num_cpus = num_online_cpus();
-
- if (num_cpus <= 1) /* NO MP */
- return;
-
- cpumask_and(&tmp, cpumask, cpu_online_mask);
- BUG_ON(!cpumask_equal(cpumask, &tmp));
-
- cpumask_clear(&physid_mask);
- for_each_cpu(cpu_id, cpumask) {
- if ((phys_id = cpu_to_physid(cpu_id)) != -1)
- cpumask_set_cpu(phys_id, &physid_mask);
- }
-
- send_IPI_mask_phys(&physid_mask, ipi_num, try);
-}
-
-/*==========================================================================*
- * Name: send_IPI_mask_phys
- *
- * Description: This routine sends a IPI to other CPUs in the system.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: cpu_mask - Bitmap of target CPUs physical ID
- * ipi_num - Number of IPI
- * try - 0 : Send IPI certainly.
- * !0 : The following IPI is not sent when Target CPU
- * has not received the before IPI.
- *
- * Returns: IPICRi regster value.
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- *
- *==========================================================================*/
-unsigned long send_IPI_mask_phys(const cpumask_t *physid_mask, int ipi_num,
- int try)
-{
- spinlock_t *ipilock;
- volatile unsigned long *ipicr_addr;
- unsigned long ipicr_val;
- unsigned long my_physid_mask;
- unsigned long mask = cpumask_bits(physid_mask)[0];
-
-
- if (mask & ~physids_coerce(phys_cpu_present_map))
- BUG();
- if (ipi_num >= NR_IPIS || ipi_num < 0)
- BUG();
-
- mask <<= IPI_SHIFT;
- ipilock = &ipi_lock[ipi_num];
- ipicr_addr = (volatile unsigned long *)(M32R_ICU_IPICR_ADDR
- + (ipi_num << 2));
- my_physid_mask = ~(1 << smp_processor_id());
-
- /*
- * lock ipi_lock[i]
- * check IPICRi == 0
- * write IPICRi (send IPIi)
- * unlock ipi_lock[i]
- */
- spin_lock(ipilock);
- __asm__ __volatile__ (
- ";; CHECK IPICRi == 0 \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "ld %0, @%1 \n\t"
- "and %0, %4 \n\t"
- "beqz %0, 2f \n\t"
- "bnez %3, 3f \n\t"
- "bra 1b \n\t"
- ";; WRITE IPICRi (send IPIi) \n\t"
- ".fillinsn \n"
- "2: \n\t"
- "st %2, @%1 \n\t"
- ".fillinsn \n"
- "3: \n\t"
- : "=&r"(ipicr_val)
- : "r"(ipicr_addr), "r"(mask), "r"(try), "r"(my_physid_mask)
- : "memory"
- );
- spin_unlock(ipilock);
-
- return ipicr_val;
-}
diff --git a/arch/m32r/kernel/smpboot.c b/arch/m32r/kernel/smpboot.c
deleted file mode 100644
index a7d04684d2c7..000000000000
--- a/arch/m32r/kernel/smpboot.c
+++ /dev/null
@@ -1,627 +0,0 @@
-/*
- * linux/arch/m32r/kernel/smpboot.c
- * orig : i386 2.4.10
- *
- * M32R SMP booting functions
- *
- * Copyright (c) 2001, 2002, 2003 Hitoshi Yamamoto
- *
- * Taken from i386 version.
- * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
- * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
- *
- * Much of the core SMP work is based on previous work by Thomas Radke, to
- * whom a great many thanks are extended.
- *
- * Thanks to Intel for making available several different Pentium,
- * Pentium Pro and Pentium-II/Xeon MP machines.
- * Original development of Linux SMP code supported by Caldera.
- *
- * This code is released under the GNU General Public License version 2 or
- * later.
- *
- * Fixes
- * Felix Koop : NR_CPUS used properly
- * Jose Renau : Handle single CPU case.
- * Alan Cox : By repeated request
- * 8) - Total BogoMIP report.
- * Greg Wright : Fix for kernel stacks panic.
- * Erich Boleyn : MP v1.4 and additional changes.
- * Matthias Sattler : Changes for 2.1 kernel map.
- * Michel Lespinasse : Changes for 2.1 kernel map.
- * Michael Chastain : Change trampoline.S to gnu as.
- * Alan Cox : Dumb bug: 'B' step PPro's are fine
- * Ingo Molnar : Added APIC timers, based on code
- * from Jose Renau
- * Ingo Molnar : various cleanups and rewrites
- * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
- * Maciej W. Rozycki : Bits for genuine 82489DX APICs
- * Martin J. Bligh : Added support for multi-quad systems
- */
-
-#include <linux/module.h>
-#include <linux/cpu.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/sched/task.h>
-#include <linux/err.h>
-#include <linux/irq.h>
-#include <linux/bootmem.h>
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include <asm/pgalloc.h>
-#include <asm/tlbflush.h>
-
-#define DEBUG_SMP
-#ifdef DEBUG_SMP
-#define Dprintk(x...) printk(x)
-#else
-#define Dprintk(x...)
-#endif
-
-extern cpumask_t cpu_initialized;
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Data structures and variables */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/* Processor that is doing the boot up */
-static unsigned int bsp_phys_id = -1;
-
-/* Bitmask of physically existing CPUs */
-physid_mask_t phys_cpu_present_map;
-
-cpumask_t cpu_bootout_map;
-cpumask_t cpu_bootin_map;
-static cpumask_t cpu_callin_map;
-cpumask_t cpu_callout_map;
-EXPORT_SYMBOL(cpu_callout_map);
-
-/* Per CPU bogomips and other parameters */
-struct cpuinfo_m32r cpu_data[NR_CPUS] __cacheline_aligned;
-
-static int cpucount;
-static cpumask_t smp_commenced_mask;
-
-extern struct {
- void * spi;
- unsigned short ss;
-} stack_start;
-
-/* which physical physical ID maps to which logical CPU number */
-static volatile int physid_2_cpu[NR_CPUS];
-#define physid_to_cpu(physid) physid_2_cpu[physid]
-
-/* which logical CPU number maps to which physical ID */
-volatile int cpu_2_physid[NR_CPUS];
-
-DEFINE_PER_CPU(int, prof_multiplier) = 1;
-DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
-DEFINE_PER_CPU(int, prof_counter) = 1;
-
-spinlock_t ipi_lock[NR_IPIS];
-
-static unsigned int calibration_result;
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Function Prototypes */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-static void init_ipi_lock(void);
-static void do_boot_cpu(int);
-
-int start_secondary(void *);
-static void smp_callin(void);
-static void smp_online(void);
-
-static void show_mp_info(int);
-static void smp_store_cpu_info(int);
-static void show_cpu_info(int);
-int setup_profiling_timer(unsigned int);
-static void init_cpu_to_physid(void);
-static void map_cpu_to_physid(int, int);
-static void unmap_cpu_to_physid(int, int);
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Boot up APs Routines : BSP */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-void smp_prepare_boot_cpu(void)
-{
- bsp_phys_id = hard_smp_processor_id();
- physid_set(bsp_phys_id, phys_cpu_present_map);
- set_cpu_online(0, true); /* BSP's cpu_id == 0 */
- cpumask_set_cpu(0, &cpu_callout_map);
- cpumask_set_cpu(0, &cpu_callin_map);
-
- /*
- * Initialize the logical to physical CPU number mapping
- */
- init_cpu_to_physid();
- map_cpu_to_physid(0, bsp_phys_id);
- current_thread_info()->cpu = 0;
-}
-
-/*==========================================================================*
- * Name: smp_prepare_cpus (old smp_boot_cpus)
- *
- * Description: This routine boot up APs.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- * 2003-06-24 hy modify for linux-2.5.69
- *
- *==========================================================================*/
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- int phys_id;
- unsigned long nr_cpu;
-
- nr_cpu = inl(M32R_FPGA_NUM_OF_CPUS_PORTL);
- if (nr_cpu > NR_CPUS) {
- printk(KERN_INFO "NUM_OF_CPUS reg. value [%ld] > NR_CPU [%d]",
- nr_cpu, NR_CPUS);
- goto smp_done;
- }
- for (phys_id = 0 ; phys_id < nr_cpu ; phys_id++)
- physid_set(phys_id, phys_cpu_present_map);
-#ifndef CONFIG_HOTPLUG_CPU
- init_cpu_present(cpu_possible_mask);
-#endif
-
- show_mp_info(nr_cpu);
-
- init_ipi_lock();
-
- /*
- * Setup boot CPU information
- */
- smp_store_cpu_info(0); /* Final full version of the data */
-
- /*
- * If SMP should be disabled, then really disable it!
- */
- if (!max_cpus) {
- printk(KERN_INFO "SMP mode deactivated by commandline.\n");
- goto smp_done;
- }
-
- /*
- * Now scan the CPU present map and fire up the other CPUs.
- */
- Dprintk("CPU present map : %lx\n", physids_coerce(phys_cpu_present_map));
-
- for (phys_id = 0 ; phys_id < NR_CPUS ; phys_id++) {
- /*
- * Don't even attempt to start the boot CPU!
- */
- if (phys_id == bsp_phys_id)
- continue;
-
- if (!physid_isset(phys_id, phys_cpu_present_map))
- continue;
-
- if (max_cpus <= cpucount + 1)
- continue;
-
- do_boot_cpu(phys_id);
-
- /*
- * Make sure we unmap all failed CPUs
- */
- if (physid_to_cpu(phys_id) == -1) {
- physid_clear(phys_id, phys_cpu_present_map);
- printk("phys CPU#%d not responding - " \
- "cannot use it.\n", phys_id);
- }
- }
-
-smp_done:
- Dprintk("Boot done.\n");
-}
-
-/*
- * init_ipi_lock : Initialize IPI locks.
- */
-static void __init init_ipi_lock(void)
-{
- int ipi;
-
- for (ipi = 0 ; ipi < NR_IPIS ; ipi++)
- spin_lock_init(&ipi_lock[ipi]);
-}
-
-/*==========================================================================*
- * Name: do_boot_cpu
- *
- * Description: This routine boot up one AP.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: phys_id - Target CPU physical ID
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- * 2003-06-24 hy modify for linux-2.5.69
- *
- *==========================================================================*/
-static void __init do_boot_cpu(int phys_id)
-{
- struct task_struct *idle;
- unsigned long send_status, boot_status;
- int timeout, cpu_id;
-
- cpu_id = ++cpucount;
-
- /*
- * We can't use kernel_thread since we must avoid to
- * reschedule the child.
- */
- idle = fork_idle(cpu_id);
- if (IS_ERR(idle))
- panic("failed fork for CPU#%d.", cpu_id);
-
- idle->thread.lr = (unsigned long)start_secondary;
-
- map_cpu_to_physid(cpu_id, phys_id);
-
- /* So we see what's up */
- printk("Booting processor %d/%d\n", phys_id, cpu_id);
- stack_start.spi = (void *)idle->thread.sp;
- task_thread_info(idle)->cpu = cpu_id;
-
- /*
- * Send Startup IPI
- * 1.IPI received by CPU#(phys_id).
- * 2.CPU#(phys_id) enter startup_AP (arch/m32r/kernel/head.S)
- * 3.CPU#(phys_id) enter start_secondary()
- */
- send_status = 0;
- boot_status = 0;
-
- cpumask_set_cpu(phys_id, &cpu_bootout_map);
-
- /* Send Startup IPI */
- send_IPI_mask_phys(cpumask_of(phys_id), CPU_BOOT_IPI, 0);
-
- Dprintk("Waiting for send to finish...\n");
- timeout = 0;
-
- /* Wait 100[ms] */
- do {
- Dprintk("+");
- udelay(1000);
- send_status = !cpumask_test_cpu(phys_id, &cpu_bootin_map);
- } while (send_status && (timeout++ < 100));
-
- Dprintk("After Startup.\n");
-
- if (!send_status) {
- /*
- * allow APs to start initializing.
- */
- Dprintk("Before Callout %d.\n", cpu_id);
- cpumask_set_cpu(cpu_id, &cpu_callout_map);
- Dprintk("After Callout %d.\n", cpu_id);
-
- /*
- * Wait 5s total for a response
- */
- for (timeout = 0; timeout < 5000; timeout++) {
- if (cpumask_test_cpu(cpu_id, &cpu_callin_map))
- break; /* It has booted */
- udelay(1000);
- }
-
- if (cpumask_test_cpu(cpu_id, &cpu_callin_map)) {
- /* number CPUs logically, starting from 1 (BSP is 0) */
- Dprintk("OK.\n");
- } else {
- boot_status = 1;
- printk("Not responding.\n");
- }
- } else
- printk("IPI never delivered???\n");
-
- if (send_status || boot_status) {
- unmap_cpu_to_physid(cpu_id, phys_id);
- cpumask_clear_cpu(cpu_id, &cpu_callout_map);
- cpumask_clear_cpu(cpu_id, &cpu_callin_map);
- cpumask_clear_cpu(cpu_id, &cpu_initialized);
- cpucount--;
- }
-}
-
-int __cpu_up(unsigned int cpu_id, struct task_struct *tidle)
-{
- int timeout;
-
- cpumask_set_cpu(cpu_id, &smp_commenced_mask);
-
- /*
- * Wait 5s total for a response
- */
- for (timeout = 0; timeout < 5000; timeout++) {
- if (cpu_online(cpu_id))
- break;
- udelay(1000);
- }
- if (!cpu_online(cpu_id))
- BUG();
-
- return 0;
-}
-
-void __init smp_cpus_done(unsigned int max_cpus)
-{
- int cpu_id, timeout;
- unsigned long bogosum = 0;
-
- for (timeout = 0; timeout < 5000; timeout++) {
- if (cpumask_equal(&cpu_callin_map, cpu_online_mask))
- break;
- udelay(1000);
- }
- if (!cpumask_equal(&cpu_callin_map, cpu_online_mask))
- BUG();
-
- for_each_online_cpu(cpu_id)
- show_cpu_info(cpu_id);
-
- /*
- * Allow the user to impress friends.
- */
- Dprintk("Before bogomips.\n");
- if (cpucount) {
- for_each_cpu(cpu_id,cpu_online_mask)
- bogosum += cpu_data[cpu_id].loops_per_jiffy;
-
- printk(KERN_INFO "Total of %d processors activated " \
- "(%lu.%02lu BogoMIPS).\n", cpucount + 1,
- bogosum / (500000 / HZ),
- (bogosum / (5000 / HZ)) % 100);
- Dprintk("Before bogocount - setting activated=1.\n");
- }
-}
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Activate a secondary processor Routines */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-
-/*==========================================================================*
- * Name: start_secondary
- *
- * Description: This routine activate a secondary processor.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: *unused - currently unused.
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- * 2003-06-24 hy modify for linux-2.5.69
- *
- *==========================================================================*/
-int __init start_secondary(void *unused)
-{
- cpu_init();
- preempt_disable();
- smp_callin();
- while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask))
- cpu_relax();
-
- smp_online();
-
- /*
- * low-memory mappings have been cleared, flush them from
- * the local TLBs too.
- */
- local_flush_tlb_all();
-
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
- return 0;
-}
-
-/*==========================================================================*
- * Name: smp_callin
- *
- * Description: This routine activate a secondary processor.
- *
- * Born on Date: 2002.02.05
- *
- * Arguments: NONE
- *
- * Returns: void (cannot fail)
- *
- * Modification log:
- * Date Who Description
- * ---------- --- --------------------------------------------------------
- * 2003-06-24 hy modify for linux-2.5.69
- *
- *==========================================================================*/
-static void __init smp_callin(void)
-{
- int phys_id = hard_smp_processor_id();
- int cpu_id = smp_processor_id();
- unsigned long timeout;
-
- if (cpumask_test_cpu(cpu_id, &cpu_callin_map)) {
- printk("huh, phys CPU#%d, CPU#%d already present??\n",
- phys_id, cpu_id);
- BUG();
- }
- Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpu_id, phys_id);
-
- /* Waiting 2s total for startup (udelay is not yet working) */
- timeout = jiffies + (2 * HZ);
- while (time_before(jiffies, timeout)) {
- /* Has the boot CPU finished it's STARTUP sequence ? */
- if (cpumask_test_cpu(cpu_id, &cpu_callout_map))
- break;
- cpu_relax();
- }
-
- if (!time_before(jiffies, timeout)) {
- printk("BUG: CPU#%d started up but did not get a callout!\n",
- cpu_id);
- BUG();
- }
-
- /* Allow the master to continue. */
- cpumask_set_cpu(cpu_id, &cpu_callin_map);
-}
-
-static void __init smp_online(void)
-{
- int cpu_id = smp_processor_id();
-
- notify_cpu_starting(cpu_id);
-
- local_irq_enable();
-
- /* Get our bogomips. */
- calibrate_delay();
-
- /* Save our processor parameters */
- smp_store_cpu_info(cpu_id);
-
- set_cpu_online(cpu_id, true);
-}
-
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-/* Boot up CPUs common Routines */
-/*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-static void __init show_mp_info(int nr_cpu)
-{
- int i;
- char cpu_model0[17], cpu_model1[17], cpu_ver[9];
-
- strncpy(cpu_model0, (char *)M32R_FPGA_CPU_NAME_ADDR, 16);
- strncpy(cpu_model1, (char *)M32R_FPGA_MODEL_ID_ADDR, 16);
- strncpy(cpu_ver, (char *)M32R_FPGA_VERSION_ADDR, 8);
-
- cpu_model0[16] = '\0';
- for (i = 15 ; i >= 0 ; i--) {
- if (cpu_model0[i] != ' ')
- break;
- cpu_model0[i] = '\0';
- }
- cpu_model1[16] = '\0';
- for (i = 15 ; i >= 0 ; i--) {
- if (cpu_model1[i] != ' ')
- break;
- cpu_model1[i] = '\0';
- }
- cpu_ver[8] = '\0';
- for (i = 7 ; i >= 0 ; i--) {
- if (cpu_ver[i] != ' ')
- break;
- cpu_ver[i] = '\0';
- }
-
- printk(KERN_INFO "M32R-mp information\n");
- printk(KERN_INFO " On-chip CPUs : %d\n", nr_cpu);
- printk(KERN_INFO " CPU model : %s/%s(%s)\n", cpu_model0,
- cpu_model1, cpu_ver);
-}
-
-/*
- * The bootstrap kernel entry code has set these up. Save them for
- * a given CPU
- */
-static void __init smp_store_cpu_info(int cpu_id)
-{
- struct cpuinfo_m32r *ci = cpu_data + cpu_id;
-
- *ci = boot_cpu_data;
- ci->loops_per_jiffy = loops_per_jiffy;
-}
-
-static void __init show_cpu_info(int cpu_id)
-{
- struct cpuinfo_m32r *ci = &cpu_data[cpu_id];
-
- printk("CPU#%d : ", cpu_id);
-
-#define PRINT_CLOCK(name, value) \
- printk(name " clock %d.%02dMHz", \
- ((value) / 1000000), ((value) % 1000000) / 10000)
-
- PRINT_CLOCK("CPU", (int)ci->cpu_clock);
- PRINT_CLOCK(", Bus", (int)ci->bus_clock);
- printk(", loops_per_jiffy[%ld]\n", ci->loops_per_jiffy);
-}
-
-/*
- * the frequency of the profiling timer can be changed
- * by writing a multiplier value into /proc/profile.
- */
-int setup_profiling_timer(unsigned int multiplier)
-{
- int i;
-
- /*
- * Sanity check. [at least 500 APIC cycles should be
- * between APIC interrupts as a rule of thumb, to avoid
- * irqs flooding us]
- */
- if ( (!multiplier) || (calibration_result / multiplier < 500))
- return -EINVAL;
-
- /*
- * Set the new multiplier for each CPU. CPUs don't start using the
- * new values until the next timer interrupt in which they do process
- * accounting. At that time they also adjust their APIC timers
- * accordingly.
- */
- for_each_possible_cpu(i)
- per_cpu(prof_multiplier, i) = multiplier;
-
- return 0;
-}
-
-/* Initialize all maps between cpu number and apicids */
-static void __init init_cpu_to_physid(void)
-{
- int i;
-
- for (i = 0 ; i < NR_CPUS ; i++) {
- cpu_2_physid[i] = -1;
- physid_2_cpu[i] = -1;
- }
-}
-
-/*
- * set up a mapping between cpu and apicid. Uses logical apicids for multiquad,
- * else physical apic ids
- */
-static void __init map_cpu_to_physid(int cpu_id, int phys_id)
-{
- physid_2_cpu[phys_id] = cpu_id;
- cpu_2_physid[cpu_id] = phys_id;
-}
-
-/*
- * undo a mapping between cpu and apicid. Uses logical apicids for multiquad,
- * else physical apic ids
- */
-static void __init unmap_cpu_to_physid(int cpu_id, int phys_id)
-{
- physid_2_cpu[phys_id] = -1;
- cpu_2_physid[cpu_id] = -1;
-}
diff --git a/arch/m32r/kernel/sys_m32r.c b/arch/m32r/kernel/sys_m32r.c
deleted file mode 100644
index 22a50fc49ab7..000000000000
--- a/arch/m32r/kernel/sys_m32r.c
+++ /dev/null
@@ -1,91 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/sys_m32r.c
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on the Linux/M32R platform.
- *
- * Taken from i386 version.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/utsname.h>
-#include <linux/ipc.h>
-
-#include <linux/uaccess.h>
-#include <asm/cachectl.h>
-#include <asm/cacheflush.h>
-#include <asm/syscall.h>
-#include <asm/unistd.h>
-
-/*
- * sys_tas() - test-and-set
- */
-asmlinkage int sys_tas(int __user *addr)
-{
- int oldval;
-
- if (!access_ok(VERIFY_WRITE, addr, sizeof (int)))
- return -EFAULT;
-
- /* atomic operation:
- * oldval = *addr; *addr = 1;
- */
- __asm__ __volatile__ (
- DCACHE_CLEAR("%0", "r4", "%1")
- " .fillinsn\n"
- "1:\n"
- " lock %0, @%1 -> unlock %2, @%1\n"
- "2:\n"
- /* NOTE:
- * The m32r processor can accept interrupts only
- * at the 32-bit instruction boundary.
- * So, in the above code, the "unlock" instruction
- * can be executed continuously after the "lock"
- * instruction execution without any interruptions.
- */
- ".section .fixup,\"ax\"\n"
- " .balign 4\n"
- "3: ldi %0, #%3\n"
- " seth r14, #high(2b)\n"
- " or3 r14, r14, #low(2b)\n"
- " jmp r14\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .balign 4\n"
- " .long 1b,3b\n"
- ".previous\n"
- : "=&r" (oldval)
- : "r" (addr), "r" (1), "i"(-EFAULT)
- : "r14", "memory"
-#ifdef CONFIG_CHIP_M32700_TS1
- , "r4"
-#endif /* CONFIG_CHIP_M32700_TS1 */
- );
-
- return oldval;
-}
-
-asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
-{
- /* This should flush more selectively ... */
- _flush_cache_all();
- return 0;
-}
-
-asmlinkage int sys_cachectl(char *addr, int nbytes, int op)
-{
- /* Not implemented yet. */
- return -ENOSYS;
-}
diff --git a/arch/m32r/kernel/syscall_table.S b/arch/m32r/kernel/syscall_table.S
deleted file mode 100644
index cf0bcf014b98..000000000000
--- a/arch/m32r/kernel/syscall_table.S
+++ /dev/null
@@ -1,328 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-ENTRY(sys_call_table)
- .long sys_restart_syscall /* 0 - old "setup()" system call*/
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_ni_syscall /* lchown16 syscall holder */
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_ni_syscall /* old stat syscall holder */
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_ni_syscall /* setuid16 syscall holder */
- .long sys_ni_syscall /* getuid16 syscall holder */
- .long sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_ni_syscall /* old fstat syscall holder */
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_cachectl /* for M32R */ /* old gtty syscall holder */
- .long sys_access
- .long sys_ni_syscall /* nice syscall holder */
- .long sys_ni_syscall /* 35 - old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_ni_syscall /* setgid16 syscall holder */
- .long sys_getgid /* will be unused */
- .long sys_ni_syscall /* signal syscall holder */
- .long sys_ni_syscall /* geteuid16 syscall holder */
- .long sys_ni_syscall /* 50 - getegid16 syscall holder */
- .long sys_acct
- .long sys_umount /* recycled never used phys() */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 - will be unused */
- .long sys_ni_syscall /* mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* sys_olduname */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_ni_syscall /* sigaction syscall holder */
- .long sys_ni_syscall /* sgetmask syscall holder */
- .long sys_ni_syscall /* ssetmask syscall holder */
- .long sys_ni_syscall /* 70 - setreuid16 syscall holder */
- .long sys_ni_syscall /* setregid16 syscall holder */
- .long sys_ni_syscall /* sigsuspend syscall holder */
- .long sys_ni_syscall /* sigpending syscall holder */
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_getrlimit/*will be unused*/
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_ni_syscall /* 80 - getgroups16 syscall holder */
- .long sys_ni_syscall /* setgroups16 syscall holder */
- .long sys_ni_syscall /* sys_oldselect */
- .long sys_symlink
- .long sys_ni_syscall /* old lstat syscall holder */
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_ni_syscall /* readdir syscall holder */
- .long sys_ni_syscall /* 90 - old_mmap syscall holder */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_ni_syscall /* 95 - fchwon16 syscall holder */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* ioperm syscall holder */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* old uname syscall holder */
- .long sys_ni_syscall /* 110 - iopl syscall holder */
- .long sys_vhangup
- .long sys_ni_syscall /* idle syscall holder */
- .long sys_ni_syscall /* vm86old syscall holder */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_ni_syscall /* sigreturn syscall holder */
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* modify_ldt syscall holder */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_ni_syscall /* sigprocmask syscall holder */
- .long sys_ni_syscall /* create_module syscall holder */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* 130 - get_kernel_syms */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* afs_syscall syscall holder */
- .long sys_ni_syscall /* setfsuid16 syscall holder */
- .long sys_ni_syscall /* setfsgid16 syscall holder */
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_ni_syscall /* setresuid16 syscall holder */
- .long sys_ni_syscall /* 165 - getresuid16 syscall holder */
- .long sys_tas /* vm86 syscall holder */
- .long sys_ni_syscall /* query_module syscall holder */
- .long sys_poll
- .long sys_ni_syscall /* was nfsservctl */
- .long sys_setresgid /* 170 */
- .long sys_getresgid
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_ni_syscall /* chown16 syscall holder */
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* streams1 */
- .long sys_ni_syscall /* streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap_pgoff
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall /* Reserved for Security */
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall /* reserved for "set_thread_area" system call */
- .long sys_ni_syscall /* reserved for "get_thread_area" system call */
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* Reserved for sys_vserver */
- .long sys_ni_syscall /* Reserved for sys_mbind */
- .long sys_ni_syscall /* Reserved for sys_get_mempolicy */
- .long sys_ni_syscall /* Reserved for sys_set_mempolicy */
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_ni_syscall /* reserved for kexec */
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_ioprio_set
- .long sys_ioprio_get /* 290 */
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages
- .long sys_openat /* 295 */
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat
- .long sys_fstatat64 /* 300 */
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat
- .long sys_readlinkat /* 305 */
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll
- .long sys_unshare /* 310 */
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range
- .long sys_tee /* 315 */
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait
- .long sys_utimensat /* 320 */
- .long sys_signalfd
- .long sys_ni_syscall
- .long sys_eventfd
- .long sys_fallocate
- .long sys_setns /* 325 */
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
deleted file mode 100644
index 521749fbbb56..000000000000
--- a/arch/m32r/kernel/time.c
+++ /dev/null
@@ -1,199 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/time.c
- *
- * Copyright (c) 2001, 2002 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto
- * Taken from i386 version.
- * Copyright (C) 1991, 1992, 1995 Linus Torvalds
- * Copyright (C) 1996, 1997, 1998 Ralf Baechle
- *
- * This file contains the time handling details for PC-style clocks as
- * found in some MIPS systems.
- *
- * Some code taken from sh version.
- * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
- * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
- */
-
-#undef DEBUG_TIMER
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/profile.h>
-
-#include <asm/io.h>
-#include <asm/m32r.h>
-
-#include <asm/hw_irq.h>
-
-#if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE)
-/* this needs a better home */
-DEFINE_SPINLOCK(rtc_lock);
-
-#ifdef CONFIG_RTC_DRV_CMOS_MODULE
-EXPORT_SYMBOL(rtc_lock);
-#endif
-#endif /* pc-style 'CMOS' RTC support */
-
-#ifdef CONFIG_SMP
-extern void smp_local_timer_interrupt(void);
-#endif
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-/*
- * Change this if you have some constant time drift
- */
-
-/* This is for machines which generate the exact clock. */
-#define USECS_PER_JIFFY (1000000/HZ)
-
-static unsigned long latch;
-
-static u32 m32r_gettimeoffset(void)
-{
- unsigned long elapsed_time = 0; /* [us] */
-
-#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
- || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
- || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-#ifndef CONFIG_SMP
-
- unsigned long count;
-
- /* timer count may underflow right here */
- count = inl(M32R_MFT2CUT_PORTL);
-
- if (inl(M32R_ICU_CR18_PORTL) & 0x00000100) /* underflow check */
- count = 0;
-
- count = (latch - count) * TICK_SIZE;
- elapsed_time = DIV_ROUND_CLOSEST(count, latch);
- /* NOTE: LATCH is equal to the "interval" value (= reload count). */
-
-#else /* CONFIG_SMP */
- unsigned long count;
- static unsigned long p_jiffies = -1;
- static unsigned long p_count = 0;
-
- /* timer count may underflow right here */
- count = inl(M32R_MFT2CUT_PORTL);
-
- if (jiffies == p_jiffies && count > p_count)
- count = 0;
-
- p_jiffies = jiffies;
- p_count = count;
-
- count = (latch - count) * TICK_SIZE;
- elapsed_time = DIV_ROUND_CLOSEST(count, latch);
- /* NOTE: LATCH is equal to the "interval" value (= reload count). */
-#endif /* CONFIG_SMP */
-#elif defined(CONFIG_CHIP_M32310)
-#warning do_gettimeoffse not implemented
-#else
-#error no chip configuration
-#endif
-
- return elapsed_time * 1000;
-}
-
-/*
- * timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "xtime_update()" routine every clocktick
- */
-static irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
-#ifndef CONFIG_SMP
- profile_tick(CPU_PROFILING);
-#endif
- xtime_update(1);
-
-#ifndef CONFIG_SMP
- update_process_times(user_mode(get_irq_regs()));
-#endif
- /* As we return to user mode fire off the other CPU schedulers..
- this is basically because we don't yet share IRQ's around.
- This message is rigged to be safe on the 386 - basically it's
- a hack, so don't look closely for now.. */
-
-#ifdef CONFIG_SMP
- smp_local_timer_interrupt();
- smp_send_timer();
-#endif
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction irq0 = {
- .handler = timer_interrupt,
- .name = "MFT2",
-};
-
-void read_persistent_clock(struct timespec *ts)
-{
- unsigned int epoch, year, mon, day, hour, min, sec;
-
- sec = min = hour = day = mon = year = 0;
- epoch = 0;
-
- year = 23;
- mon = 4;
- day = 17;
-
- /* Attempt to guess the epoch. This is the same heuristic as in rtc.c
- so no stupid things will happen to timekeeping. Who knows, maybe
- Ultrix also uses 1952 as epoch ... */
- if (year > 10 && year < 44)
- epoch = 1980;
- else if (year < 96)
- epoch = 1952;
- year += epoch;
-
- ts->tv_sec = mktime(year, mon, day, hour, min, sec);
- ts->tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
-}
-
-
-void __init time_init(void)
-{
- arch_gettimeoffset = m32r_gettimeoffset;
-
-#if defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_XNUX2) \
- || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_M32700) \
- || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104)
-
- /* M32102 MFT setup */
- setup_irq(M32R_IRQ_MFT2, &irq0);
- {
- unsigned long bus_clock;
- unsigned short divide;
-
- bus_clock = boot_cpu_data.bus_clock;
- divide = boot_cpu_data.timer_divide;
- latch = DIV_ROUND_CLOSEST(bus_clock/divide, HZ);
-
- printk("Timer start : latch = %ld\n", latch);
-
- outl((M32R_MFTMOD_CC_MASK | M32R_MFTMOD_TCCR \
- |M32R_MFTMOD_CSSEL011), M32R_MFT2MOD_PORTL);
- outl(latch, M32R_MFT2RLD_PORTL);
- outl(latch, M32R_MFT2CUT_PORTL);
- outl(0, M32R_MFT2CMPRLD_PORTL);
- outl((M32R_MFTCR_MFT2MSK|M32R_MFTCR_MFT2EN), M32R_MFTCR_PORTL);
- }
-
-#elif defined(CONFIG_CHIP_M32310)
-#warning time_init not implemented
-#else
-#error no chip configuration
-#endif
-}
diff --git a/arch/m32r/kernel/traps.c b/arch/m32r/kernel/traps.c
deleted file mode 100644
index a6f300a208bd..000000000000
--- a/arch/m32r/kernel/traps.c
+++ /dev/null
@@ -1,324 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/kernel/traps.c
- *
- * Copyright (C) 2001, 2002 Hirokazu Takata, Hiroyuki Kondo,
- * Hitoshi Yamamoto
- */
-
-/*
- * 'traps.c' handles hardware traps and faults after we have saved some
- * state in 'entry.S'.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/kallsyms.h>
-#include <linux/stddef.h>
-#include <linux/ptrace.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/cpu.h>
-
-#include <asm/page.h>
-#include <asm/processor.h>
-
-#include <linux/uaccess.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-
-#include <asm/smp.h>
-
-#include <linux/module.h>
-
-asmlinkage void alignment_check(void);
-asmlinkage void ei_handler(void);
-asmlinkage void rie_handler(void);
-asmlinkage void debug_trap(void);
-asmlinkage void cache_flushing_handler(void);
-asmlinkage void ill_trap(void);
-
-#ifdef CONFIG_SMP
-extern void smp_reschedule_interrupt(void);
-extern void smp_invalidate_interrupt(void);
-extern void smp_call_function_interrupt(void);
-extern void smp_ipi_timer_interrupt(void);
-extern void smp_flush_cache_all_interrupt(void);
-extern void smp_call_function_single_interrupt(void);
-
-/*
- * for Boot AP function
- */
-asm (
- " .section .eit_vector4,\"ax\" \n"
- " .global _AP_RE \n"
- " .global startup_AP \n"
- "_AP_RE: \n"
- " .fill 32, 4, 0 \n"
- "_AP_EI: bra startup_AP \n"
- " .previous \n"
-);
-#endif /* CONFIG_SMP */
-
-extern unsigned long eit_vector[];
-#define BRA_INSN(func, entry) \
- ((unsigned long)func - (unsigned long)eit_vector - entry*4)/4 \
- + 0xff000000UL
-
-static void set_eit_vector_entries(void)
-{
- extern void default_eit_handler(void);
- extern void system_call(void);
- extern void pie_handler(void);
- extern void ace_handler(void);
- extern void tme_handler(void);
- extern void _flush_cache_copyback_all(void);
-
- eit_vector[0] = 0xd0c00001; /* seth r0, 0x01 */
- eit_vector[1] = BRA_INSN(default_eit_handler, 1);
- eit_vector[4] = 0xd0c00010; /* seth r0, 0x10 */
- eit_vector[5] = BRA_INSN(default_eit_handler, 5);
- eit_vector[8] = BRA_INSN(rie_handler, 8);
- eit_vector[12] = BRA_INSN(alignment_check, 12);
- eit_vector[16] = BRA_INSN(ill_trap, 16);
- eit_vector[17] = BRA_INSN(debug_trap, 17);
- eit_vector[18] = BRA_INSN(system_call, 18);
- eit_vector[19] = BRA_INSN(ill_trap, 19);
- eit_vector[20] = BRA_INSN(ill_trap, 20);
- eit_vector[21] = BRA_INSN(ill_trap, 21);
- eit_vector[22] = BRA_INSN(ill_trap, 22);
- eit_vector[23] = BRA_INSN(ill_trap, 23);
- eit_vector[24] = BRA_INSN(ill_trap, 24);
- eit_vector[25] = BRA_INSN(ill_trap, 25);
- eit_vector[26] = BRA_INSN(ill_trap, 26);
- eit_vector[27] = BRA_INSN(ill_trap, 27);
- eit_vector[28] = BRA_INSN(cache_flushing_handler, 28);
- eit_vector[29] = BRA_INSN(ill_trap, 29);
- eit_vector[30] = BRA_INSN(ill_trap, 30);
- eit_vector[31] = BRA_INSN(ill_trap, 31);
- eit_vector[32] = BRA_INSN(ei_handler, 32);
- eit_vector[64] = BRA_INSN(pie_handler, 64);
-#ifdef CONFIG_MMU
- eit_vector[68] = BRA_INSN(ace_handler, 68);
- eit_vector[72] = BRA_INSN(tme_handler, 72);
-#endif /* CONFIG_MMU */
-#ifdef CONFIG_SMP
- eit_vector[184] = (unsigned long)smp_reschedule_interrupt;
- eit_vector[185] = (unsigned long)smp_invalidate_interrupt;
- eit_vector[186] = (unsigned long)smp_call_function_interrupt;
- eit_vector[187] = (unsigned long)smp_ipi_timer_interrupt;
- eit_vector[188] = (unsigned long)smp_flush_cache_all_interrupt;
- eit_vector[189] = 0; /* CPU_BOOT_IPI */
- eit_vector[190] = (unsigned long)smp_call_function_single_interrupt;
- eit_vector[191] = 0;
-#endif
- _flush_cache_copyback_all();
-}
-
-void __init trap_init(void)
-{
- set_eit_vector_entries();
-
- /*
- * Should be a barrier for any external CPU state.
- */
- cpu_init();
-}
-
-static int kstack_depth_to_print = 24;
-
-static void show_trace(struct task_struct *task, unsigned long *stack)
-{
- unsigned long addr;
-
- if (!stack)
- stack = (unsigned long*)&stack;
-
- printk("Call Trace: ");
- while (!kstack_end(stack)) {
- addr = *stack++;
- if (__kernel_text_address(addr))
- printk("[<%08lx>] %pSR\n", addr, (void *)addr);
- }
- printk("\n");
-}
-
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
- unsigned long *stack;
- int i;
-
- /*
- * debugging aid: "show_stack(NULL);" prints the
- * back trace for this cpu.
- */
-
- if(sp==NULL) {
- if (task)
- sp = (unsigned long *)task->thread.sp;
- else
- sp=(unsigned long*)&sp;
- }
-
- stack = sp;
- for(i=0; i < kstack_depth_to_print; i++) {
- if (kstack_end(stack))
- break;
- if (i && ((i % 4) == 0))
- printk("\n ");
- printk("%08lx ", *stack++);
- }
- printk("\n");
- show_trace(task, sp);
-}
-
-static void show_registers(struct pt_regs *regs)
-{
- int i = 0;
- int in_kernel = 1;
- unsigned long sp;
-
- printk("CPU: %d\n", smp_processor_id());
- show_regs(regs);
-
- sp = (unsigned long) (1+regs);
- if (user_mode(regs)) {
- in_kernel = 0;
- sp = regs->spu;
- printk("SPU: %08lx\n", sp);
- } else {
- printk("SPI: %08lx\n", sp);
- }
- printk("Process %s (pid: %d, process nr: %d, stackpage=%08lx)",
- current->comm, task_pid_nr(current), 0xffff & i, 4096+(unsigned long)current);
-
- /*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (in_kernel) {
- printk("\nStack: ");
- show_stack(current, (unsigned long*) sp);
-
- printk("\nCode: ");
- if (regs->bpc < PAGE_OFFSET)
- goto bad;
-
- for(i=0;i<20;i++) {
- unsigned char c;
- if (__get_user(c, &((unsigned char*)regs->bpc)[i])) {
-bad:
- printk(" Bad PC value.");
- break;
- }
- printk("%02x ", c);
- }
- }
- printk("\n");
-}
-
-static DEFINE_SPINLOCK(die_lock);
-
-void die(const char * str, struct pt_regs * regs, long err)
-{
- console_verbose();
- spin_lock_irq(&die_lock);
- bust_spinlocks(1);
- printk("%s: %04lx\n", str, err & 0xffff);
- show_registers(regs);
- bust_spinlocks(0);
- spin_unlock_irq(&die_lock);
- do_exit(SIGSEGV);
-}
-
-static __inline__ void die_if_kernel(const char * str,
- struct pt_regs * regs, long err)
-{
- if (!user_mode(regs))
- die(str, regs, err);
-}
-
-static __inline__ void do_trap(int trapnr, int signr, const char * str,
- struct pt_regs * regs, long error_code, siginfo_t *info)
-{
- if (user_mode(regs)) {
- /* trap_signal */
- struct task_struct *tsk = current;
- tsk->thread.error_code = error_code;
- tsk->thread.trap_no = trapnr;
- if (info)
- force_sig_info(signr, info, tsk);
- else
- force_sig(signr, tsk);
- return;
- } else {
- /* kernel_trap */
- if (!fixup_exception(regs))
- die(str, regs, error_code);
- return;
- }
-}
-
-#define DO_ERROR(trapnr, signr, str, name) \
-asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
-{ \
- do_trap(trapnr, signr, NULL, regs, error_code, NULL); \
-}
-
-#define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \
-asmlinkage void do_##name(struct pt_regs * regs, long error_code) \
-{ \
- siginfo_t info; \
- info.si_signo = signr; \
- info.si_errno = 0; \
- info.si_code = sicode; \
- info.si_addr = (void __user *)siaddr; \
- do_trap(trapnr, signr, str, regs, error_code, &info); \
-}
-
-DO_ERROR( 1, SIGTRAP, "debug trap", debug_trap)
-DO_ERROR_INFO(0x20, SIGILL, "reserved instruction ", rie_handler, ILL_ILLOPC, regs->bpc)
-DO_ERROR_INFO(0x100, SIGILL, "privileged instruction", pie_handler, ILL_PRVOPC, regs->bpc)
-DO_ERROR_INFO(-1, SIGILL, "illegal trap", ill_trap, ILL_ILLTRP, regs->bpc)
-
-extern int handle_unaligned_access(unsigned long, struct pt_regs *);
-
-/* This code taken from arch/sh/kernel/traps.c */
-asmlinkage void do_alignment_check(struct pt_regs *regs, long error_code)
-{
- mm_segment_t oldfs;
- unsigned long insn;
- int tmp;
-
- oldfs = get_fs();
-
- if (user_mode(regs)) {
- local_irq_enable();
- current->thread.error_code = error_code;
- current->thread.trap_no = 0x17;
-
- set_fs(USER_DS);
- if (copy_from_user(&insn, (void *)regs->bpc, 4)) {
- set_fs(oldfs);
- goto uspace_segv;
- }
- tmp = handle_unaligned_access(insn, regs);
- set_fs(oldfs);
-
- if (!tmp)
- return;
-
- uspace_segv:
- printk(KERN_NOTICE "Killing process \"%s\" due to unaligned "
- "access\n", current->comm);
- force_sig(SIGSEGV, current);
- } else {
- set_fs(KERNEL_DS);
- if (copy_from_user(&insn, (void *)regs->bpc, 4)) {
- set_fs(oldfs);
- die("insn faulting in do_address_error", regs, 0);
- }
- handle_unaligned_access(insn, regs);
- set_fs(oldfs);
- }
-}
diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S
deleted file mode 100644
index 7e4d957f7f7f..000000000000
--- a/arch/m32r/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ld script to make M32R Linux kernel
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/addrspace.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-
-OUTPUT_ARCH(m32r)
-#if defined(__LITTLE_ENDIAN__)
- jiffies = jiffies_64;
-#else
- jiffies = jiffies_64 + 4;
-#endif
-
-kernel_entry = boot - 0x80000000;
-ENTRY(kernel_entry)
-
-SECTIONS
-{
- . = CONFIG_MEMORY_START + __PAGE_OFFSET;
- eit_vector = .;
-
- . = . + 0x1000;
- .empty_zero_page : { *(.empty_zero_page) } = 0
-
- /* read-only */
- _text = .; /* Text and read-only data */
- .boot : { *(.boot) } = 0
- .text : {
- HEAD_TEXT
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- *(.fixup)
- *(.gnu.warning)
- } = 0x9090
-#ifdef CONFIG_SMP
- . = ALIGN(65536);
- .eit_vector4 : { *(.eit_vector4) }
-#endif
- _etext = .; /* End of text section */
-
- EXCEPTION_TABLE(16)
- NOTES
-
- _sdata = .; /* Start of data section */
- RODATA
- RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE)
- _edata = .; /* End of data section */
-
- /* will be freed after init */
- . = ALIGN(PAGE_SIZE); /* Init code and data */
- __init_begin = .;
- INIT_TEXT_SECTION(PAGE_SIZE)
- INIT_DATA_SECTION(16)
- PERCPU_SECTION(32)
- . = ALIGN(PAGE_SIZE);
- __init_end = .;
- /* freed after init ends here */
-
- BSS_SECTION(0, 0, 4)
-
- _end = . ;
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
-
- /* Sections to be discarded */
- DISCARDS
-}
diff --git a/arch/m32r/lib/Makefile b/arch/m32r/lib/Makefile
deleted file mode 100644
index 5889eb9610b5..000000000000
--- a/arch/m32r/lib/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for M32R-specific library files..
-#
-
-lib-y := checksum.o ashxdi3.o memset.o memcpy.o \
- delay.o strlen.o usercopy.o csum_partial_copy.o \
- ucmpdi2.o
diff --git a/arch/m32r/lib/ashxdi3.S b/arch/m32r/lib/ashxdi3.S
deleted file mode 100644
index cd1acca53911..000000000000
--- a/arch/m32r/lib/ashxdi3.S
+++ /dev/null
@@ -1,294 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/lib/ashxdi3.S
- *
- * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
- *
- */
-
-;
-; input (r0,r1) src
-; input r2 shift val
-; r3 scratch
-; output (r0,r1)
-;
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
-#ifndef __LITTLE_ENDIAN__
-
- .text
- .align 4
- .globl __ashrdi3
-__ashrdi3:
- cmpz r2 || ldi r3, #32
- jc r14 || cmpu r2, r3
- bc 1f
- ; case 32 =< shift
- mv r1, r0 || srai r0, #31
- addi r2, #-32
- sra r1, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r0 || srl r1, r2
- sra r0, r2 || neg r2, r2
- sll r3, r2
- or r1, r3 || jmp r14
-
- .align 4
- .globl __ashldi3
- .globl __lshldi3
-__ashldi3:
-__lshldi3:
- cmpz r2 || ldi r3, #32
- jc r14 || cmpu r2, r3
- bc 1f
- ; case 32 =< shift
- mv r0, r1 || addi r2, #-32
- sll r0, r2 || ldi r1, #0
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r1 || sll r0, r2
- sll r1, r2 || neg r2, r2
- srl r3, r2
- or r0, r3 || jmp r14
-
- .align 4
- .globl __lshrdi3
-__lshrdi3:
- cmpz r2 || ldi r3, #32
- jc r14 || cmpu r2, r3
- bc 1f
- ; case 32 =< shift
- mv r1, r0 || addi r2, #-32
- ldi r0, #0 || srl r1, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r0 || srl r1, r2
- srl r0, r2 || neg r2, r2
- sll r3, r2
- or r1, r3 || jmp r14
-
-#else /* LITTLE_ENDIAN */
-
- .text
- .align 4
- .globl __ashrdi3
-__ashrdi3:
- cmpz r2 || ldi r3, #32
- jc r14 || cmpu r2, r3
- bc 1f
- ; case 32 =< shift
- mv r0, r1 || srai r1, #31
- addi r2, #-32
- sra r0, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r1 || srl r0, r2
- sra r1, r2 || neg r2, r2
- sll r3, r2
- or r0, r3 || jmp r14
-
- .align 4
- .globl __ashldi3
- .globl __lshldi3
-__ashldi3:
-__lshldi3:
- cmpz r2 || ldi r3, #32
- jc r14 || cmpu r2, r3
- bc 1f
- ; case 32 =< shift
- mv r1, r0 || addi r2, #-32
- sll r1, r2 || ldi r0, #0
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r0 || sll r1, r2
- sll r0, r2 || neg r2, r2
- srl r3, r2
- or r1, r3 || jmp r14
-
- .align 4
- .globl __lshrdi3
-__lshrdi3:
- cmpz r2 || ldi r3, #32
- jc r14 || cmpu r2, r3
- bc 1f
- ; case 32 =< shift
- mv r0, r1 || addi r2, #-32
- ldi r1, #0 || srl r0, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r1 || srl r0, r2
- srl r1, r2 || neg r2, r2
- sll r3, r2
- or r0, r3 || jmp r14
-
-#endif
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
-#ifndef __LITTLE_ENDIAN__
-
- .text
- .align 4
- .globl __ashrdi3
-__ashrdi3:
- beqz r2, 2f
- cmpui r2, #32
- bc 1f
- ; case 32 =< shift
- mv r1, r0
- srai r0, #31
- addi r2, #-32
- sra r1, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r0
- srl r1, r2
- sra r0, r2
- neg r2, r2
- sll r3, r2
- or r1, r3
- .fillinsn
-2:
- jmp r14
-
- .align 4
- .globl __ashldi3
- .globl __lshldi3
-__ashldi3:
-__lshldi3:
- beqz r2, 2f
- cmpui r2, #32
- bc 1f
- ; case 32 =< shift
- mv r0, r1
- addi r2, #-32
- sll r0, r2
- ldi r1, #0
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r1
- sll r0, r2
- sll r1, r2
- neg r2, r2
- srl r3, r2
- or r0, r3
- .fillinsn
-2:
- jmp r14
-
- .align 4
- .globl __lshrdi3
-__lshrdi3:
- beqz r2, 2f
- cmpui r2, #32
- bc 1f
- ; case 32 =< shift
- mv r1, r0
- ldi r0, #0
- addi r2, #-32
- srl r1, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r0
- srl r1, r2
- srl r0, r2
- neg r2, r2
- sll r3, r2
- or r1, r3
- .fillinsn
-2:
- jmp r14
-
-#else
-
- .text
- .align 4
- .globl __ashrdi3
-__ashrdi3:
- beqz r2, 2f
- cmpui r2, #32
- bc 1f
- ; case 32 =< shift
- mv r0, r1
- srai r1, #31
- addi r2, #-32
- sra r0, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r1
- srl r0, r2
- sra r1, r2
- neg r2, r2
- sll r3, r2
- or r0, r3
- .fillinsn
-2:
- jmp r14
-
- .align 4
- .globl __ashldi3
- .globl __lshldi3
-__ashldi3:
-__lshldi3:
- beqz r2, 2f
- cmpui r2, #32
- bc 1f
- ; case 32 =< shift
- mv r1, r0
- addi r2, #-32
- sll r1, r2
- ldi r0, #0
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r0
- sll r1, r2
- sll r0, r2
- neg r2, r2
- srl r3, r2
- or r1, r3
- .fillinsn
-2:
- jmp r14
-
- .align 4
- .globl __lshrdi3
-__lshrdi3:
- beqz r2, 2f
- cmpui r2, #32
- bc 1f
- ; case 32 =< shift
- mv r0, r1
- ldi r1, #0
- addi r2, #-32
- srl r0, r2
- jmp r14
- .fillinsn
-1: ; case shift <32
- mv r3, r1
- srl r0, r2
- srl r1, r2
- neg r2, r2
- sll r3, r2
- or r0, r3
- .fillinsn
-2:
- jmp r14
-
-#endif
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
- .end
diff --git a/arch/m32r/lib/checksum.S b/arch/m32r/lib/checksum.S
deleted file mode 100644
index 0af0360c76d9..000000000000
--- a/arch/m32r/lib/checksum.S
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * INET An implementation of the TCP/IP protocol suite for the LINUX
- * operating system. INET is implemented using the BSD Socket
- * interface as the means of communication with the user level.
- *
- * IP/TCP/UDP checksumming routines
- *
- * Authors: Jorge Cwik, <jorge@laser.satlink.net>
- * Arnt Gulbrandsen, <agulbra@nvg.unit.no>
- * Tom May, <ftom@netcom.com>
- * Pentium Pro/II routines:
- * Alexander Kjeldaas <astor@guardian.no>
- * Finn Arne Gangstad <finnag@guardian.no>
- * Lots of code moved from tcp.c and ip.c; see those files
- * for more names.
- *
- * Changes: Ingo Molnar, converted csum_partial_copy() to 2.1 exception
- * handling.
- * Andi Kleen, add zeroing on error
- * converted to pure assembler
- * Hirokazu Takata,Hiroyuki Kondo rewrite for the m32r architecture.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-
-/*
- * computes a partial checksum, e.g. for TCP/UDP fragments
- */
-
-/*
-unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum)
- */
-
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
- /*
- * Experiments with Ethernet and SLIP connections show that buff
- * is aligned on either a 2-byte or 4-byte boundary. We get at
- * least a twofold speedup on 486 and Pentium if it is 4-byte aligned.
- * Fortunately, it is easy to convert 2-byte alignment to 4-byte
- * alignment for the unrolled loop.
- */
-
- .text
-ENTRY(csum_partial)
- ; Function args
- ; r0: unsigned char *buff
- ; r1: int len
- ; r2: unsigned int sum
-
- push r2 || ldi r2, #0
- and3 r7, r0, #1 ; Check alignment.
- beqz r7, 1f ; Jump if alignment is ok.
- ; 1-byte mis aligned
- ldub r4, @r0 || addi r0, #1
- ; clear c-bit || Alignment uses up bytes.
- cmp r0, r0 || addi r1, #-1
- ldi r3, #0 || addx r2, r4
- addx r2, r3
- .fillinsn
-1:
- and3 r4, r0, #2 ; Check alignment.
- beqz r4, 2f ; Jump if alignment is ok.
- ; clear c-bit || Alignment uses up two bytes.
- cmp r0, r0 || addi r1, #-2
- bgtz r1, 1f ; Jump if we had at least two bytes.
- bra 4f || addi r1, #2
- .fillinsn ; len(r1) was < 2. Deal with it.
-1:
- ; 2-byte aligned
- lduh r4, @r0 || ldi r3, #0
- addx r2, r4 || addi r0, #2
- addx r2, r3
- .fillinsn
-2:
- ; 4-byte aligned
- cmp r0, r0 ; clear c-bit
- srl3 r6, r1, #5
- beqz r6, 2f
- .fillinsn
-
-1: ld r3, @r0+
- ld r4, @r0+ ; +4
- ld r5, @r0+ ; +8
- ld r3, @r0+ || addx r2, r3 ; +12
- ld r4, @r0+ || addx r2, r4 ; +16
- ld r5, @r0+ || addx r2, r5 ; +20
- ld r3, @r0+ || addx r2, r3 ; +24
- ld r4, @r0+ || addx r2, r4 ; +28
- addx r2, r5 || addi r6, #-1
- addx r2, r3
- addx r2, r4
- bnez r6, 1b
-
- addx r2, r6 ; r6=0
- cmp r0, r0 ; This clears c-bit
- .fillinsn
-2: and3 r6, r1, #0x1c ; withdraw len
- beqz r6, 4f
- srli r6, #2
- .fillinsn
-
-3: ld r4, @r0+ || addi r6, #-1
- addx r2, r4
- bnez r6, 3b
-
- addx r2, r6 ; r6=0
- cmp r0, r0 ; This clears c-bit
- .fillinsn
-4: and3 r1, r1, #3
- beqz r1, 7f ; if len == 0 goto end
- and3 r6, r1, #2
- beqz r6, 5f ; if len < 2 goto 5f(1byte)
- lduh r4, @r0 || addi r0, #2
- addi r1, #-2 || slli r4, #16
- addx r2, r4
- beqz r1, 6f
- .fillinsn
-5: ldub r4, @r0 || ldi r1, #0
-#ifndef __LITTLE_ENDIAN__
- slli r4, #8
-#endif
- addx r2, r4
- .fillinsn
-6: addx r2, r1
- .fillinsn
-7:
- and3 r0, r2, #0xffff
- srli r2, #16
- add r0, r2
- srl3 r2, r0, #16
- beqz r2, 1f
- addi r0, #1
- and3 r0, r0, #0xffff
- .fillinsn
-1:
- beqz r7, 1f ; swap the upper byte for the lower
- and3 r2, r0, #0xff
- srl3 r0, r0, #8
- slli r2, #8
- or r0, r2
- .fillinsn
-1:
- pop r2 || cmp r0, r0
- addx r0, r2 || ldi r2, #0
- addx r0, r2
- jmp r14
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
- /*
- * Experiments with Ethernet and SLIP connections show that buff
- * is aligned on either a 2-byte or 4-byte boundary. We get at
- * least a twofold speedup on 486 and Pentium if it is 4-byte aligned.
- * Fortunately, it is easy to convert 2-byte alignment to 4-byte
- * alignment for the unrolled loop.
- */
-
- .text
-ENTRY(csum_partial)
- ; Function args
- ; r0: unsigned char *buff
- ; r1: int len
- ; r2: unsigned int sum
-
- push r2
- ldi r2, #0
- and3 r7, r0, #1 ; Check alignment.
- beqz r7, 1f ; Jump if alignment is ok.
- ; 1-byte mis aligned
- ldub r4, @r0
- addi r0, #1
- addi r1, #-1 ; Alignment uses up bytes.
- cmp r0, r0 ; clear c-bit
- ldi r3, #0
- addx r2, r4
- addx r2, r3
- .fillinsn
-1:
- and3 r4, r0, #2 ; Check alignment.
- beqz r4, 2f ; Jump if alignment is ok.
- addi r1, #-2 ; Alignment uses up two bytes.
- cmp r0, r0 ; clear c-bit
- bgtz r1, 1f ; Jump if we had at least two bytes.
- addi r1, #2 ; len(r1) was < 2. Deal with it.
- bra 4f
- .fillinsn
-1:
- ; 2-byte aligned
- lduh r4, @r0
- addi r0, #2
- ldi r3, #0
- addx r2, r4
- addx r2, r3
- .fillinsn
-2:
- ; 4-byte aligned
- cmp r0, r0 ; clear c-bit
- srl3 r6, r1, #5
- beqz r6, 2f
- .fillinsn
-
-1: ld r3, @r0+
- ld r4, @r0+ ; +4
- ld r5, @r0+ ; +8
- addx r2, r3
- addx r2, r4
- addx r2, r5
- ld r3, @r0+ ; +12
- ld r4, @r0+ ; +16
- ld r5, @r0+ ; +20
- addx r2, r3
- addx r2, r4
- addx r2, r5
- ld r3, @r0+ ; +24
- ld r4, @r0+ ; +28
- addi r6, #-1
- addx r2, r3
- addx r2, r4
- bnez r6, 1b
- addx r2, r6 ; r6=0
- cmp r0, r0 ; This clears c-bit
- .fillinsn
-
-2: and3 r6, r1, #0x1c ; withdraw len
- beqz r6, 4f
- srli r6, #2
- .fillinsn
-
-3: ld r4, @r0+
- addi r6, #-1
- addx r2, r4
- bnez r6, 3b
- addx r2, r6 ; r6=0
- cmp r0, r0 ; This clears c-bit
- .fillinsn
-
-4: and3 r1, r1, #3
- beqz r1, 7f ; if len == 0 goto end
- and3 r6, r1, #2
- beqz r6, 5f ; if len < 2 goto 5f(1byte)
-
- lduh r4, @r0
- addi r0, #2
- addi r1, #-2
- slli r4, #16
- addx r2, r4
- beqz r1, 6f
- .fillinsn
-5: ldub r4, @r0
-#ifndef __LITTLE_ENDIAN__
- slli r4, #8
-#endif
- addx r2, r4
- .fillinsn
-6: ldi r5, #0
- addx r2, r5
- .fillinsn
-7:
- and3 r0, r2, #0xffff
- srli r2, #16
- add r0, r2
- srl3 r2, r0, #16
- beqz r2, 1f
- addi r0, #1
- and3 r0, r0, #0xffff
- .fillinsn
-1:
- beqz r7, 1f
- mv r2, r0
- srl3 r0, r2, #8
- and3 r2, r2, #0xff
- slli r2, #8
- or r0, r2
- .fillinsn
-1:
- pop r2
- cmp r0, r0
- addx r0, r2
- ldi r2, #0
- addx r0, r2
- jmp r14
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
-/*
-unsigned int csum_partial_copy_generic (const char *src, char *dst,
- int len, int sum, int *src_err_ptr, int *dst_err_ptr)
- */
-
-/*
- * Copy from ds while checksumming, otherwise like csum_partial
- *
- * The macros SRC and DST specify the type of access for the instruction.
- * thus we can call a custom exception handler for all access types.
- *
- * FIXME: could someone double-check whether I haven't mixed up some SRC and
- * DST definitions? It's damn hard to trigger all cases. I hope I got
- * them all but there's no guarantee.
- */
-
-ENTRY(csum_partial_copy_generic)
- nop
- nop
- nop
- nop
- jmp r14
- nop
- nop
- nop
-
- .end
diff --git a/arch/m32r/lib/csum_partial_copy.c b/arch/m32r/lib/csum_partial_copy.c
deleted file mode 100644
index b3cd59c12b8e..000000000000
--- a/arch/m32r/lib/csum_partial_copy.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * INET An implementation of the TCP/IP protocol suite for the LINUX
- * operating system. INET is implemented using the BSD Socket
- * interface as the means of communication with the user level.
- *
- * M32R specific IP/TCP/UDP checksumming routines
- * (Some code taken from MIPS architecture)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995 Waldorf Electronics GmbH
- * Copyright (C) 1998, 1999 Ralf Baechle
- * Copyright (C) 2001-2005 Hiroyuki Kondo, Hirokazu Takata
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/string.h>
-
-#include <net/checksum.h>
-#include <asm/byteorder.h>
-#include <linux/uaccess.h>
-
-/*
- * Copy while checksumming, otherwise like csum_partial
- */
-__wsum
-csum_partial_copy_nocheck (const void *src, void *dst, int len, __wsum sum)
-{
- sum = csum_partial(src, len, sum);
- memcpy(dst, src, len);
-
- return sum;
-}
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
-
-/*
- * Copy from userspace and compute checksum. If we catch an exception
- * then zero the rest of the buffer.
- */
-__wsum
-csum_partial_copy_from_user (const void __user *src, void *dst,
- int len, __wsum sum, int *err_ptr)
-{
- int missing;
-
- missing = copy_from_user(dst, src, len);
- if (missing) {
- memset(dst + len - missing, 0, missing);
- *err_ptr = -EFAULT;
- }
-
- return csum_partial(dst, len-missing, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-EXPORT_SYMBOL(csum_partial);
diff --git a/arch/m32r/lib/delay.c b/arch/m32r/lib/delay.c
deleted file mode 100644
index ae1fe90892f9..000000000000
--- a/arch/m32r/lib/delay.c
+++ /dev/null
@@ -1,130 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/lib/delay.c
- *
- * Copyright (c) 2002 Hitoshi Yamamoto, Hirokazu Takata
- * Copyright (c) 2004 Hirokazu Takata
- */
-
-#include <linux/param.h>
-#include <linux/module.h>
-#ifdef CONFIG_SMP
-#include <linux/sched.h>
-#include <asm/current.h>
-#include <asm/smp.h>
-#endif /* CONFIG_SMP */
-#include <asm/processor.h>
-
-void __delay(unsigned long loops)
-{
-#ifdef CONFIG_ISA_DUAL_ISSUE
- __asm__ __volatile__ (
- "beqz %0, 2f \n\t"
- "addi %0, #-1 \n\t"
-
- " .fillinsn \n\t"
- "1: \n\t"
- "cmpz %0 || addi %0, #-1 \n\t"
- "bc 2f || cmpz %0 \n\t"
- "bc 2f || addi %0, #-1 \n\t"
- "cmpz %0 || addi %0, #-1 \n\t"
- "bc 2f || cmpz %0 \n\t"
- "bnc 1b || addi %0, #-1 \n\t"
- " .fillinsn \n\t"
- "2: \n\t"
- : "+r" (loops)
- : "r" (0)
- : "cbit"
- );
-#else
- __asm__ __volatile__ (
- "beqz %0, 2f \n\t"
- " .fillinsn \n\t"
- "1: \n\t"
- "addi %0, #-1 \n\t"
- "blez %0, 2f \n\t"
- "addi %0, #-1 \n\t"
- "blez %0, 2f \n\t"
- "addi %0, #-1 \n\t"
- "blez %0, 2f \n\t"
- "addi %0, #-1 \n\t"
- "bgtz %0, 1b \n\t"
- " .fillinsn \n\t"
- "2: \n\t"
- : "+r" (loops)
- : "r" (0)
- );
-#endif
-}
-
-void __const_udelay(unsigned long xloops)
-{
-#if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
- /*
- * loops [1] = (xloops >> 32) [sec] * loops_per_jiffy [1/jiffy]
- * * HZ [jiffy/sec]
- * = (xloops >> 32) [sec] * (loops_per_jiffy * HZ) [1/sec]
- * = (((xloops * loops_per_jiffy) >> 32) * HZ) [1]
- *
- * NOTE:
- * - '[]' depicts variable's dimension in the above equation.
- * - "rac" instruction rounds the accumulator in word size.
- */
- __asm__ __volatile__ (
- "srli %0, #1 \n\t"
- "mulwhi %0, %1 ; a0 \n\t"
- "mulwu1 %0, %1 ; a1 \n\t"
- "sadd ; a0 += (a1 >> 16) \n\t"
- "rac a0, a0, #1 \n\t"
- "mvfacmi %0, a0 \n\t"
- : "+r" (xloops)
- : "r" (current_cpu_data.loops_per_jiffy)
- : "a0", "a1"
- );
-#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
- /*
- * u64 ull;
- * ull = (u64)xloops * (u64)current_cpu_data.loops_per_jiffy;
- * xloops = (ull >> 32);
- */
- __asm__ __volatile__ (
- "and3 r4, %0, #0xffff \n\t"
- "and3 r5, %1, #0xffff \n\t"
- "mul r4, r5 \n\t"
- "srl3 r6, %0, #16 \n\t"
- "srli r4, #16 \n\t"
- "mul r5, r6 \n\t"
- "add r4, r5 \n\t"
- "and3 r5, %0, #0xffff \n\t"
- "srl3 r6, %1, #16 \n\t"
- "mul r5, r6 \n\t"
- "add r4, r5 \n\t"
- "srl3 r5, %0, #16 \n\t"
- "srli r4, #16 \n\t"
- "mul r5, r6 \n\t"
- "add r4, r5 \n\t"
- "mv %0, r4 \n\t"
- : "+r" (xloops)
- : "r" (current_cpu_data.loops_per_jiffy)
- : "r4", "r5", "r6"
- );
-#else
-#error unknown isa configuration
-#endif
- __delay(xloops * HZ);
-}
-
-void __udelay(unsigned long usecs)
-{
- __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
-}
-
-void __ndelay(unsigned long nsecs)
-{
- __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
-}
-
-EXPORT_SYMBOL(__delay);
-EXPORT_SYMBOL(__const_udelay);
-EXPORT_SYMBOL(__udelay);
-EXPORT_SYMBOL(__ndelay);
diff --git a/arch/m32r/lib/libgcc.h b/arch/m32r/lib/libgcc.h
deleted file mode 100644
index 4854690d944a..000000000000
--- a/arch/m32r/lib/libgcc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_LIBGCC_H
-#define __ASM_LIBGCC_H
-
-#include <asm/byteorder.h>
-
-#ifdef __BIG_ENDIAN
-struct DWstruct {
- int high, low;
-};
-#elif defined(__LITTLE_ENDIAN)
-struct DWstruct {
- int low, high;
-};
-#else
-#error I feel sick.
-#endif
-
-typedef union {
- struct DWstruct s;
- long long ll;
-} DWunion;
-
-#endif /* __ASM_LIBGCC_H */
diff --git a/arch/m32r/lib/memcpy.S b/arch/m32r/lib/memcpy.S
deleted file mode 100644
index 249da3e3358d..000000000000
--- a/arch/m32r/lib/memcpy.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/lib/memcpy.S
- *
- * Copyright (C) 2001 Hiroyuki Kondo, and Hirokazu Takata
- * Copyright (C) 2004 Hirokazu Takata
- *
- * void *memcopy(void *dst, const void *src, int n);
- *
- * dst: r0
- * src: r1
- * n : r2
- */
-
- .text
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
- .text
-ENTRY(memcpy)
-memcopy:
- mv r4, r0 || mv r7, r0
- or r7, r1 || cmpz r2
- jc r14 || cmpeq r0, r1 ; return if r2=0
- jc r14 ; return if r0=r1
-
- and3 r7, r7, #3
- bnez r7, byte_copy
- srl3 r3, r2, #2
- and3 r2, r2, #3
- beqz r3, byte_copy
- addi r4, #-4
-word_copy:
- ld r7, @r1+ || addi r3, #-1
- st r7, @+r4 || cmpz r2
- bnez r3, word_copy
- addi r4, #4 || jc r14 ; return if r2=0
-#if defined(CONFIG_ISA_M32R2)
-byte_copy:
- ldb r7, @r1 || addi r1, #1
- addi r2, #-1 || stb r7, @r4+
- bnez r2, byte_copy
-#elif defined(CONFIG_ISA_M32R)
-byte_copy:
- ldb r7, @r1 || addi r1, #1
- addi r2, #-1 || stb r7, @r4
- addi r4, #1
- bnez r2, byte_copy
-#else
-#error unknown isa configuration
-#endif
-end_memcopy:
- jmp r14
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
- .text
-ENTRY(memcpy)
-memcopy:
- mv r4, r0
- mv r7, r0
- or r7, r1
- beq r0, r1, end_memcopy
- beqz r2, end_memcopy
-
- and3 r7, r7, #3
- bnez r7, byte_copy
- srl3 r3, r2, #2
- and3 r2, r2, #3
- beqz r3, byte_copy
- addi r4, #-4
-word_copy:
- ld r7, @r1+
- addi r3, #-1
- st r7, @+r4
- bnez r3, word_copy
- beqz r2, end_memcopy
- addi r4, #4
-byte_copy:
- ldb r7, @r1
- addi r1, #1
- addi r2, #-1
- stb r7, @r4
- addi r4, #1
- bnez r2, byte_copy
-end_memcopy:
- jmp r14
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
- .end
diff --git a/arch/m32r/lib/memset.S b/arch/m32r/lib/memset.S
deleted file mode 100644
index e7f45e6c73f5..000000000000
--- a/arch/m32r/lib/memset.S
+++ /dev/null
@@ -1,179 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/lib/memset.S
- *
- * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
- * Copyright (C) 2004 Hirokazu Takata
- *
- * void *memset(void *dst, int val, int len);
- *
- * dst: r0
- * val: r1
- * len: r2
- * ret: r0
- *
- */
-
- .text
- .global memset
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
- .align 4
-memset:
- mv r4, r0 || cmpz r2
- jc r14
- cmpui r2, #16
- bnc qword_align_check
- cmpui r2, #4
- bc byte_set
-word_align_check: /* len >= 4 */
- and3 r3, r4, #3
- beqz r3, word_set
- addi r3, #-4
- neg r3, r3 /* r3 = -(r3 - 4) */
-align_word:
- stb r1, @r4 || addi r4, #1
- addi r2, #-1 || addi r3, #-1
- bnez r3, align_word
- cmpui r2, #4
- bc byte_set
-word_set:
- and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
- sll3 r3, r1, #8
- or r1, r3 || addi r4, #-4
- sll3 r3, r1, #16
- or r1, r3 || addi r2, #-4
-word_set_loop:
- st r1, @+r4 || addi r2, #-4
- bgtz r2, word_set_loop
- bnez r2, byte_set_wrap
- st r1, @+r4
- jmp r14
-
-qword_align_check: /* len >= 16 */
- and3 r3, r4, #15
- bnez r3, word_align_check
-qword_set:
- and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
- sll3 r3, r1, #8
- or r1, r3 || addi r4, #-4
- sll3 r3, r1, #16
- or r1, r3 || ldi r5, #16
-qword_set_loop:
- ld r3, @(4,r4) /* cache line allocate */
- st r1, @+r4 || addi r2, #-16
- st r1, @+r4 || cmpu r2, r5
- st r1, @+r4
- st r1, @+r4
- bnc qword_set_loop || cmpz r2
- jc r14
-set_remainder:
- cmpui r2, #4
- bc byte_set_wrap1
- addi r2, #-4
- bra word_set_loop
-
-byte_set_wrap:
- addi r2, #4
- cmpz r2
- jc r14
-byte_set_wrap1:
- addi r4, #4
-#if defined(CONFIG_ISA_M32R2)
-byte_set:
- addi r2, #-1 || stb r1, @r4+
- bnez r2, byte_set
-#elif defined(CONFIG_ISA_M32R)
-byte_set:
- addi r2, #-1 || stb r1, @r4
- addi r4, #1
- bnez r2, byte_set
-#else
-#error unknown isa configuration
-#endif
-end_memset:
- jmp r14
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
- .align 4
-memset:
- mv r4, r0
- beqz r2, end_memset
- cmpui r2, #16
- bnc qword_align_check
- cmpui r2, #4
- bc byte_set
-word_align_check: /* len >= 4 */
- and3 r3, r4, #3
- beqz r3, word_set
- addi r3, #-4
- neg r3, r3 /* r3 = -(r3 - 4) */
-align_word:
- stb r1, @r4
- addi r4, #1
- addi r2, #-1
- addi r3, #-1
- bnez r3, align_word
- cmpui r2, #4
- bc byte_set
-word_set:
- and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
- sll3 r3, r1, #8
- or r1, r3
- sll3 r3, r1, #16
- or r1, r3
- addi r2, #-4
- addi r4, #-4
-word_set_loop:
- st r1, @+r4
- addi r2, #-4
- bgtz r2, word_set_loop
- bnez r2, byte_set_wrap
- st r1, @+r4
- jmp r14
-
-qword_align_check: /* len >= 16 */
- and3 r3, r4, #15
- bnez r3, word_align_check
-qword_set:
- and3 r1, r1, #0x00ff /* r1: abababab <-- ??????ab */
- sll3 r3, r1, #8
- or r1, r3
- sll3 r3, r1, #16
- or r1, r3
- addi r4, #-4
-qword_set_loop:
- ld r3, @(4,r4) /* cache line allocate */
- addi r2, #-16
- st r1, @+r4
- st r1, @+r4
- cmpui r2, #16
- st r1, @+r4
- st r1, @+r4
- bnc qword_set_loop
- bnez r2, set_remainder
- jmp r14
-set_remainder:
- cmpui r2, #4
- bc byte_set_wrap1
- addi r2, #-4
- bra word_set_loop
-
-byte_set_wrap:
- addi r2, #4
- beqz r2, end_memset
-byte_set_wrap1:
- addi r4, #4
-byte_set:
- addi r2, #-1
- stb r1, @r4
- addi r4, #1
- bnez r2, byte_set
-end_memset:
- jmp r14
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
- .end
diff --git a/arch/m32r/lib/strlen.S b/arch/m32r/lib/strlen.S
deleted file mode 100644
index 41c77e387593..000000000000
--- a/arch/m32r/lib/strlen.S
+++ /dev/null
@@ -1,118 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/strlen.S -- strlen code.
- *
- * Copyright (C) 2001 Hirokazu Takata
- *
- * size_t strlen(const char *s);
- *
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
- .text
-ENTRY(strlen)
- mv r6, r0 || ldi r2, #0
- and3 r0, r0, #3
- bnez r0, strlen_byte
-;
-strlen_word:
- ld r0, @r6+
-;
- seth r5, #high(0x01010101)
- or3 r5, r5, #low(0x01010101)
- sll3 r7, r5, #7
-strlen_word_loop:
- ld r1, @r6+ || not r4, r0
- sub r0, r5 || and r4, r7
- and r4, r0
- bnez r4, strlen_last_bytes
- ld r0, @r6+ || not r4, r1
- sub r1, r5 || and r4, r7
- and r4, r1 || addi r2, #4
- bnez r4, strlen_last_bytes
- addi r2, #4 || bra.s strlen_word_loop
-
- ; NOTE: If a null char. exists, return 0.
- ; if ((x - 0x01010101) & ~x & 0x80808080)
- ; return 0;
-;
-strlen_byte:
- ldb r1, @r6 || addi r6, #1
- beqz r1, strlen_exit
- addi r2, #1 || bra.s strlen_byte
-;
-strlen_last_bytes:
- ldi r0, #4 || addi r6, #-8
-;
-strlen_byte_loop:
- ldb r1, @r6 || addi r6, #1
- addi r0, #-1 || cmpz r1
- bc.s strlen_exit || cmpz r0
- addi r2, #1 || bnc.s strlen_byte_loop
-;
-strlen_exit:
- mv r0, r2 || jmp r14
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
- .text
-ENTRY(strlen)
- mv r6, r0
- ldi r2, #0
- and3 r0, r0, #3
- bnez r0, strlen_byte
-;
-strlen_word:
- ld r0, @r6+
-;
- seth r5, #high(0x01010101)
- or3 r5, r5, #low(0x01010101)
- sll3 r7, r5, #7
-strlen_word_loop:
- ld r1, @r6+
- not r4, r0 ; NOTE: If a null char. exists, return 0.
- sub r0, r5 ; if ((x - 0x01010101) & ~x & 0x80808080)
- and r4, r7 ; return 0;
- and r4, r0
- bnez r4, strlen_last_bytes
- addi r2, #4
-;
- ld r0, @r6+
- not r4, r1 ; NOTE: If a null char. exists, return 0.
- sub r1, r5 ; if ((x - 0x01010101) & ~x & 0x80808080)
- and r4, r7 ; return 0;
- and r4, r1
- bnez r4, strlen_last_bytes
- addi r2, #4
- bra strlen_word_loop
-;
-strlen_byte:
- ldb r1, @r6
- addi r6, #1
- beqz r1, strlen_exit
- addi r2, #1
- bra strlen_byte
-;
-strlen_last_bytes:
- ldi r0, #4
- addi r6, #-8
-;
-strlen_byte_loop:
- ldb r1, @r6
- addi r6, #1
- addi r0, #-1
- beqz r1, strlen_exit
- addi r2, #1
- bnez r0, strlen_byte_loop
-;
-strlen_exit:
- mv r0, r2
- jmp r14
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
- .end
diff --git a/arch/m32r/lib/ucmpdi2.c b/arch/m32r/lib/ucmpdi2.c
deleted file mode 100644
index e20fa3484fd8..000000000000
--- a/arch/m32r/lib/ucmpdi2.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "libgcc.h"
-
-int __ucmpdi2(unsigned long long a, unsigned long long b)
-{
- const DWunion au = {.ll = a};
- const DWunion bu = {.ll = b};
-
- if ((unsigned int)au.s.high < (unsigned int)bu.s.high)
- return 0;
- else if ((unsigned int)au.s.high > (unsigned int)bu.s.high)
- return 2;
- if ((unsigned int)au.s.low < (unsigned int)bu.s.low)
- return 0;
- else if ((unsigned int)au.s.low > (unsigned int)bu.s.low)
- return 2;
- return 1;
-}
diff --git a/arch/m32r/lib/usercopy.c b/arch/m32r/lib/usercopy.c
deleted file mode 100644
index 0892a4341b3a..000000000000
--- a/arch/m32r/lib/usercopy.c
+++ /dev/null
@@ -1,362 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * User address space access functions.
- * The non inlined parts of asm-m32r/uaccess.h are here.
- *
- * Copyright 1997 Andi Kleen <ak@muc.de>
- * Copyright 1997 Linus Torvalds
- * Copyright 2001, 2002, 2004 Hirokazu Takata
- */
-#include <linux/prefetch.h>
-#include <linux/string.h>
-#include <linux/thread_info.h>
-#include <linux/uaccess.h>
-
-/*
- * Copy a null terminated string from userspace.
- */
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
-#define __do_strncpy_from_user(dst,src,count,res) \
-do { \
- int __d0, __d1, __d2; \
- __asm__ __volatile__( \
- " beqz %1, 2f\n" \
- " .fillinsn\n" \
- "0: ldb r14, @%3 || addi %3, #1\n" \
- " stb r14, @%4 || addi %4, #1\n" \
- " beqz r14, 1f\n" \
- " addi %1, #-1\n" \
- " bnez %1, 0b\n" \
- " .fillinsn\n" \
- "1: sub %0, %1\n" \
- " .fillinsn\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "3: seth r14, #high(2b)\n" \
- " or3 r14, r14, #low(2b)\n" \
- " jmp r14 || ldi %0, #%5\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,3b\n" \
- ".previous" \
- : "=&r"(res), "=&r"(count), "=&r" (__d0), "=&r" (__d1), \
- "=&r" (__d2) \
- : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), \
- "4"(dst) \
- : "r14", "cbit", "memory"); \
-} while (0)
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
-#define __do_strncpy_from_user(dst,src,count,res) \
-do { \
- int __d0, __d1, __d2; \
- __asm__ __volatile__( \
- " beqz %1, 2f\n" \
- " .fillinsn\n" \
- "0: ldb r14, @%3\n" \
- " stb r14, @%4\n" \
- " addi %3, #1\n" \
- " addi %4, #1\n" \
- " beqz r14, 1f\n" \
- " addi %1, #-1\n" \
- " bnez %1, 0b\n" \
- " .fillinsn\n" \
- "1: sub %0, %1\n" \
- " .fillinsn\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "3: ldi %0, #%5\n" \
- " seth r14, #high(2b)\n" \
- " or3 r14, r14, #low(2b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,3b\n" \
- ".previous" \
- : "=&r"(res), "=&r"(count), "=&r" (__d0), "=&r" (__d1), \
- "=&r" (__d2) \
- : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), \
- "4"(dst) \
- : "r14", "cbit", "memory"); \
-} while (0)
-
-#endif /* CONFIG_ISA_DUAL_ISSUE */
-
-long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- long res = -EFAULT;
- if (access_ok(VERIFY_READ, src, 1))
- __do_strncpy_from_user(dst, src, count, res);
- return res;
-}
-
-
-/*
- * Zero Userspace
- */
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
-#define __do_clear_user(addr,size) \
-do { \
- int __dst, __c; \
- __asm__ __volatile__( \
- " beqz %1, 9f\n" \
- " and3 r14, %0, #3\n" \
- " bnez r14, 2f\n" \
- " and3 r14, %1, #3\n" \
- " bnez r14, 2f\n" \
- " and3 %1, %1, #3\n" \
- " beqz %2, 2f\n" \
- " addi %0, #-4\n" \
- " .fillinsn\n" \
- "0: ; word clear \n" \
- " st %6, @+%0 || addi %2, #-1\n" \
- " bnez %2, 0b\n" \
- " beqz %1, 9f\n" \
- " .fillinsn\n" \
- "2: ; byte clear \n" \
- " stb %6, @%0 || addi %1, #-1\n" \
- " addi %0, #1\n" \
- " bnez %1, 2b\n" \
- " .fillinsn\n" \
- "9:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "4: slli %2, #2\n" \
- " seth r14, #high(9b)\n" \
- " or3 r14, r14, #low(9b)\n" \
- " jmp r14 || add %1, %2\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,4b\n" \
- " .long 2b,9b\n" \
- ".previous\n" \
- : "=&r"(__dst), "=&r"(size), "=&r"(__c) \
- : "0"(addr), "1"(size), "2"(size / 4), "r"(0) \
- : "r14", "cbit", "memory"); \
-} while (0)
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
-#define __do_clear_user(addr,size) \
-do { \
- int __dst, __c; \
- __asm__ __volatile__( \
- " beqz %1, 9f\n" \
- " and3 r14, %0, #3\n" \
- " bnez r14, 2f\n" \
- " and3 r14, %1, #3\n" \
- " bnez r14, 2f\n" \
- " and3 %1, %1, #3\n" \
- " beqz %2, 2f\n" \
- " addi %0, #-4\n" \
- " .fillinsn\n" \
- "0: st %6, @+%0 ; word clear \n" \
- " addi %2, #-1\n" \
- " bnez %2, 0b\n" \
- " beqz %1, 9f\n" \
- " .fillinsn\n" \
- "2: stb %6, @%0 ; byte clear \n" \
- " addi %1, #-1\n" \
- " addi %0, #1\n" \
- " bnez %1, 2b\n" \
- " .fillinsn\n" \
- "9:\n" \
- ".section .fixup,\"ax\"\n" \
- " .balign 4\n" \
- "4: slli %2, #2\n" \
- " add %1, %2\n" \
- " seth r14, #high(9b)\n" \
- " or3 r14, r14, #low(9b)\n" \
- " jmp r14\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,4b\n" \
- " .long 2b,9b\n" \
- ".previous\n" \
- : "=&r"(__dst), "=&r"(size), "=&r"(__c) \
- : "0"(addr), "1"(size), "2"(size / 4), "r"(0) \
- : "r14", "cbit", "memory"); \
-} while (0)
-
-#endif /* not CONFIG_ISA_DUAL_ISSUE */
-
-unsigned long
-clear_user(void __user *to, unsigned long n)
-{
- if (access_ok(VERIFY_WRITE, to, n))
- __do_clear_user(to, n);
- return n;
-}
-
-unsigned long
-__clear_user(void __user *to, unsigned long n)
-{
- __do_clear_user(to, n);
- return n;
-}
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-
-#ifdef CONFIG_ISA_DUAL_ISSUE
-
-long strnlen_user(const char __user *s, long n)
-{
- unsigned long mask = -__addr_ok(s);
- unsigned long res;
-
- __asm__ __volatile__(
- " and %0, %5 || mv r1, %1\n"
- " beqz %0, strnlen_exit\n"
- " and3 r0, %1, #3\n"
- " bnez r0, strnlen_byte_loop\n"
- " cmpui %0, #4\n"
- " bc strnlen_byte_loop\n"
- "strnlen_word_loop:\n"
- "0: ld r0, @%1+\n"
- " pcmpbz r0\n"
- " bc strnlen_last_bytes_fixup\n"
- " addi %0, #-4\n"
- " beqz %0, strnlen_exit\n"
- " bgtz %0, strnlen_word_loop\n"
- "strnlen_last_bytes:\n"
- " mv %0, %4\n"
- "strnlen_last_bytes_fixup:\n"
- " addi %1, #-4\n"
- "strnlen_byte_loop:\n"
- "1: ldb r0, @%1 || addi %0, #-1\n"
- " beqz r0, strnlen_exit\n"
- " addi %1, #1\n"
- " bnez %0, strnlen_byte_loop\n"
- "strnlen_exit:\n"
- " sub %1, r1\n"
- " add3 %0, %1, #1\n"
- " .fillinsn\n"
- "9:\n"
- ".section .fixup,\"ax\"\n"
- " .balign 4\n"
- "4: addi %1, #-4\n"
- " .fillinsn\n"
- "5: seth r1, #high(9b)\n"
- " or3 r1, r1, #low(9b)\n"
- " jmp r1 || ldi %0, #0\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .balign 4\n"
- " .long 0b,4b\n"
- " .long 1b,5b\n"
- ".previous"
- : "=&r" (res), "=r" (s)
- : "0" (n), "1" (s), "r" (n & 3), "r" (mask), "r"(0x01010101)
- : "r0", "r1", "cbit");
-
- /* NOTE: strnlen_user() algorithm:
- * {
- * char *p;
- * for (p = s; n-- && *p != '\0'; ++p)
- * ;
- * return p - s + 1;
- * }
- */
-
- /* NOTE: If a null char. exists, return 0.
- * if ((x - 0x01010101) & ~x & 0x80808080)\n"
- * return 0;\n"
- */
-
- return res & mask;
-}
-
-#else /* not CONFIG_ISA_DUAL_ISSUE */
-
-long strnlen_user(const char __user *s, long n)
-{
- unsigned long mask = -__addr_ok(s);
- unsigned long res;
-
- __asm__ __volatile__(
- " and %0, %5\n"
- " mv r1, %1\n"
- " beqz %0, strnlen_exit\n"
- " and3 r0, %1, #3\n"
- " bnez r0, strnlen_byte_loop\n"
- " cmpui %0, #4\n"
- " bc strnlen_byte_loop\n"
- " sll3 r3, %6, #7\n"
- "strnlen_word_loop:\n"
- "0: ld r0, @%1+\n"
- " not r2, r0\n"
- " sub r0, %6\n"
- " and r2, r3\n"
- " and r2, r0\n"
- " bnez r2, strnlen_last_bytes_fixup\n"
- " addi %0, #-4\n"
- " beqz %0, strnlen_exit\n"
- " bgtz %0, strnlen_word_loop\n"
- "strnlen_last_bytes:\n"
- " mv %0, %4\n"
- "strnlen_last_bytes_fixup:\n"
- " addi %1, #-4\n"
- "strnlen_byte_loop:\n"
- "1: ldb r0, @%1\n"
- " addi %0, #-1\n"
- " beqz r0, strnlen_exit\n"
- " addi %1, #1\n"
- " bnez %0, strnlen_byte_loop\n"
- "strnlen_exit:\n"
- " sub %1, r1\n"
- " add3 %0, %1, #1\n"
- " .fillinsn\n"
- "9:\n"
- ".section .fixup,\"ax\"\n"
- " .balign 4\n"
- "4: addi %1, #-4\n"
- " .fillinsn\n"
- "5: ldi %0, #0\n"
- " seth r1, #high(9b)\n"
- " or3 r1, r1, #low(9b)\n"
- " jmp r1\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .balign 4\n"
- " .long 0b,4b\n"
- " .long 1b,5b\n"
- ".previous"
- : "=&r" (res), "=r" (s)
- : "0" (n), "1" (s), "r" (n & 3), "r" (mask), "r"(0x01010101)
- : "r0", "r1", "r2", "r3", "cbit");
-
- /* NOTE: strnlen_user() algorithm:
- * {
- * char *p;
- * for (p = s; n-- && *p != '\0'; ++p)
- * ;
- * return p - s + 1;
- * }
- */
-
- /* NOTE: If a null char. exists, return 0.
- * if ((x - 0x01010101) & ~x & 0x80808080)\n"
- * return 0;\n"
- */
-
- return res & mask;
-}
-
-#endif /* CONFIG_ISA_DUAL_ISSUE */
-
diff --git a/arch/m32r/mm/Makefile b/arch/m32r/mm/Makefile
deleted file mode 100644
index cb20d90c51d1..000000000000
--- a/arch/m32r/mm/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Linux M32R-specific parts of the memory manager.
-#
-
-ifdef CONFIG_MMU
-obj-y := init.o fault.o mmu.o extable.o ioremap.o cache.o page.o
-else
-obj-y := init.o fault-nommu.o mmu.o extable.o ioremap-nommu.o cache.o page.o
-endif
-
-obj-$(CONFIG_DISCONTIGMEM) += discontig.o
-
diff --git a/arch/m32r/mm/cache.c b/arch/m32r/mm/cache.c
deleted file mode 100644
index 0d1ae744e56f..000000000000
--- a/arch/m32r/mm/cache.c
+++ /dev/null
@@ -1,89 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/mm/cache.c
- *
- * Copyright (C) 2002-2005 Hirokazu Takata, Hayato Fujiwara
- */
-
-#include <asm/pgtable.h>
-
-#undef MCCR
-
-#if defined(CONFIG_CHIP_XNUX2) || defined(CONFIG_CHIP_M32700) \
- || defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_OPSP)
-/* Cache Control Register */
-#define MCCR ((volatile unsigned long*)0xfffffffc)
-#define MCCR_CC (1UL << 7) /* Cache mode modify bit */
-#define MCCR_IIV (1UL << 6) /* I-cache invalidate */
-#define MCCR_DIV (1UL << 5) /* D-cache invalidate */
-#define MCCR_DCB (1UL << 4) /* D-cache copy back */
-#define MCCR_ICM (1UL << 1) /* I-cache mode [0:off,1:on] */
-#define MCCR_DCM (1UL << 0) /* D-cache mode [0:off,1:on] */
-#define MCCR_ICACHE_INV (MCCR_CC|MCCR_IIV)
-#define MCCR_DCACHE_CB (MCCR_CC|MCCR_DCB)
-#define MCCR_DCACHE_CBINV (MCCR_CC|MCCR_DIV|MCCR_DCB)
-#define CHECK_MCCR(mccr) (mccr = *MCCR)
-#elif defined(CONFIG_CHIP_M32102)
-#define MCCR ((volatile unsigned char*)0xfffffffe)
-#define MCCR_IIV (1UL << 0) /* I-cache invalidate */
-#define MCCR_ICACHE_INV MCCR_IIV
-#elif defined(CONFIG_CHIP_M32104)
-#define MCCR ((volatile unsigned short*)0xfffffffe)
-#define MCCR_IIV (1UL << 8) /* I-cache invalidate */
-#define MCCR_DIV (1UL << 9) /* D-cache invalidate */
-#define MCCR_DCB (1UL << 10) /* D-cache copy back */
-#define MCCR_ICM (1UL << 0) /* I-cache mode [0:off,1:on] */
-#define MCCR_DCM (1UL << 1) /* D-cache mode [0:off,1:on] */
-#define MCCR_ICACHE_INV MCCR_IIV
-#define MCCR_DCACHE_CB MCCR_DCB
-#define MCCR_DCACHE_CBINV (MCCR_DIV|MCCR_DCB)
-#endif
-
-#ifndef MCCR
-#error Unknown cache type.
-#endif
-
-
-/* Copy back and invalidate D-cache and invalidate I-cache all */
-void _flush_cache_all(void)
-{
-#if defined(CONFIG_CHIP_M32102)
- unsigned char mccr;
- *MCCR = MCCR_ICACHE_INV;
-#elif defined(CONFIG_CHIP_M32104)
- unsigned short mccr;
-
- /* Copyback and invalidate D-cache */
- /* Invalidate I-cache */
- *MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CBINV);
-#else
- unsigned long mccr;
-
- /* Copyback and invalidate D-cache */
- /* Invalidate I-cache */
- *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CBINV;
-#endif
- while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
-}
-
-/* Copy back D-cache and invalidate I-cache all */
-void _flush_cache_copyback_all(void)
-{
-#if defined(CONFIG_CHIP_M32102)
- unsigned char mccr;
- *MCCR = MCCR_ICACHE_INV;
-#elif defined(CONFIG_CHIP_M32104)
- unsigned short mccr;
-
- /* Copyback and invalidate D-cache */
- /* Invalidate I-cache */
- *MCCR |= (MCCR_ICACHE_INV | MCCR_DCACHE_CB);
-#else
- unsigned long mccr;
-
- /* Copyback D-cache */
- /* Invalidate I-cache */
- *MCCR = MCCR_ICACHE_INV | MCCR_DCACHE_CB;
-#endif
- while ((mccr = *MCCR) & MCCR_IIV); /* loop while invalidating... */
-}
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
deleted file mode 100644
index eb8e7966dcaf..000000000000
--- a/arch/m32r/mm/discontig.c
+++ /dev/null
@@ -1,163 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/mm/discontig.c
- *
- * Discontig memory support
- *
- * Copyright (c) 2003 Hitoshi Yamamoto
- */
-
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <linux/mmzone.h>
-#include <linux/initrd.h>
-#include <linux/nodemask.h>
-#include <linux/module.h>
-#include <linux/pfn.h>
-
-#include <asm/setup.h>
-
-extern char _end[];
-
-struct pglist_data *node_data[MAX_NUMNODES];
-EXPORT_SYMBOL(node_data);
-
-pg_data_t m32r_node_data[MAX_NUMNODES];
-
-/* Memory profile */
-typedef struct {
- unsigned long start_pfn;
- unsigned long pages;
- unsigned long holes;
- unsigned long free_pfn;
-} mem_prof_t;
-static mem_prof_t mem_prof[MAX_NUMNODES];
-
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
-static void __init mem_prof_init(void)
-{
- unsigned long start_pfn, holes, free_pfn;
- const unsigned long zone_alignment = 1UL << (MAX_ORDER - 1);
- unsigned long ul;
- mem_prof_t *mp;
-
- /* Node#0 SDRAM */
- mp = &mem_prof[0];
- mp->start_pfn = PFN_UP(CONFIG_MEMORY_START);
- mp->pages = PFN_DOWN(memory_end - memory_start);
- mp->holes = 0;
- mp->free_pfn = PFN_UP(__pa(_end));
-
- /* Node#1 internal SRAM */
- mp = &mem_prof[1];
- start_pfn = free_pfn = PFN_UP(CONFIG_IRAM_START);
- holes = 0;
- if (start_pfn & (zone_alignment - 1)) {
- ul = zone_alignment;
- while (start_pfn >= ul)
- ul += zone_alignment;
-
- start_pfn = ul - zone_alignment;
- holes = free_pfn - start_pfn;
- }
-
- mp->start_pfn = start_pfn;
- mp->pages = PFN_DOWN(CONFIG_IRAM_SIZE) + holes;
- mp->holes = holes;
- mp->free_pfn = PFN_UP(CONFIG_IRAM_START);
-}
-
-unsigned long __init setup_memory(void)
-{
- unsigned long bootmap_size;
- unsigned long min_pfn;
- int nid;
- mem_prof_t *mp;
-
- max_low_pfn = 0;
- min_low_pfn = -1;
-
- mem_prof_init();
-
- for_each_online_node(nid) {
- mp = &mem_prof[nid];
- NODE_DATA(nid)=(pg_data_t *)&m32r_node_data[nid];
- NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
- min_pfn = mp->start_pfn;
- max_pfn = mp->start_pfn + mp->pages;
- bootmap_size = init_bootmem_node(NODE_DATA(nid), mp->free_pfn,
- mp->start_pfn, max_pfn);
-
- free_bootmem_node(NODE_DATA(nid), PFN_PHYS(mp->start_pfn),
- PFN_PHYS(mp->pages));
-
- reserve_bootmem_node(NODE_DATA(nid), PFN_PHYS(mp->start_pfn),
- PFN_PHYS(mp->free_pfn - mp->start_pfn) + bootmap_size,
- BOOTMEM_DEFAULT);
-
- if (max_low_pfn < max_pfn)
- max_low_pfn = max_pfn;
-
- if (min_low_pfn > min_pfn)
- min_low_pfn = min_pfn;
- }
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (LOADER_TYPE && INITRD_START) {
- if (INITRD_START + INITRD_SIZE <= PFN_PHYS(max_low_pfn)) {
- reserve_bootmem_node(NODE_DATA(0), INITRD_START,
- INITRD_SIZE, BOOTMEM_DEFAULT);
- initrd_start = INITRD_START + PAGE_OFFSET;
- initrd_end = initrd_start + INITRD_SIZE;
- printk("initrd:start[%08lx],size[%08lx]\n",
- initrd_start, INITRD_SIZE);
- } else {
- printk("initrd extends beyond end of memory "
- "(0x%08lx > 0x%08llx)\ndisabling initrd\n",
- INITRD_START + INITRD_SIZE,
- (unsigned long long)PFN_PHYS(max_low_pfn));
-
- initrd_start = 0;
- }
- }
-#endif /* CONFIG_BLK_DEV_INITRD */
-
- return max_low_pfn;
-}
-
-#define START_PFN(nid) (NODE_DATA(nid)->bdata->node_min_pfn)
-#define MAX_LOW_PFN(nid) (NODE_DATA(nid)->bdata->node_low_pfn)
-
-void __init zone_sizes_init(void)
-{
- unsigned long zones_size[MAX_NR_ZONES], zholes_size[MAX_NR_ZONES];
- unsigned long low, start_pfn;
- int nid, i;
- mem_prof_t *mp;
-
- for_each_online_node(nid) {
- mp = &mem_prof[nid];
- for (i = 0 ; i < MAX_NR_ZONES ; i++) {
- zones_size[i] = 0;
- zholes_size[i] = 0;
- }
- start_pfn = START_PFN(nid);
- low = MAX_LOW_PFN(nid);
- zones_size[ZONE_DMA] = low - start_pfn;
- zholes_size[ZONE_DMA] = mp->holes;
-
- node_set_state(nid, N_NORMAL_MEMORY);
- free_area_init_node(nid, zones_size, start_pfn, zholes_size);
- }
-
- /*
- * For test
- * Use all area of internal RAM.
- * see __alloc_pages()
- */
- NODE_DATA(1)->node_zones->watermark[WMARK_MIN] = 0;
- NODE_DATA(1)->node_zones->watermark[WMARK_LOW] = 0;
- NODE_DATA(1)->node_zones->watermark[WMARK_HIGH] = 0;
-}
diff --git a/arch/m32r/mm/extable.c b/arch/m32r/mm/extable.c
deleted file mode 100644
index 066982756a4e..000000000000
--- a/arch/m32r/mm/extable.c
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/mm/extable.c
- */
-
-#include <linux/extable.h>
-#include <linux/uaccess.h>
-
-int fixup_exception(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
-
- fixup = search_exception_tables(regs->bpc);
- if (fixup) {
- regs->bpc = fixup->fixup;
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/m32r/mm/fault-nommu.c b/arch/m32r/mm/fault-nommu.c
deleted file mode 100644
index 240e00067d5e..000000000000
--- a/arch/m32r/mm/fault-nommu.c
+++ /dev/null
@@ -1,134 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/mm/fault.c
- *
- * Copyright (c) 2001, 2002 Hitoshi Yamamoto, and H. Kondo
- *
- * Some code taken from i386 version.
- * Copyright (C) 1995 Linus Torvalds
- */
-
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/vt_kern.h> /* For unblank_screen() */
-
-#include <asm/m32r.h>
-#include <linux/uaccess.h>
-#include <asm/pgalloc.h>
-#include <asm/pgtable.h>
-#include <asm/hardirq.h>
-#include <asm/mmu_context.h>
-
-extern void die(const char *, struct pt_regs *, long);
-
-#ifndef CONFIG_SMP
-asmlinkage unsigned int tlb_entry_i_dat;
-asmlinkage unsigned int tlb_entry_d_dat;
-#define tlb_entry_i tlb_entry_i_dat
-#define tlb_entry_d tlb_entry_d_dat
-#else
-unsigned int tlb_entry_i_dat[NR_CPUS];
-unsigned int tlb_entry_d_dat[NR_CPUS];
-#define tlb_entry_i tlb_entry_i_dat[smp_processor_id()]
-#define tlb_entry_d tlb_entry_d_dat[smp_processor_id()]
-#endif
-
-void do_BUG(const char *file, int line)
-{
- bust_spinlocks(1);
- printk("kernel BUG at %s:%d!\n", file, line);
-}
-
-/*======================================================================*
- * do_page_fault()
- *======================================================================*
- * This routine handles page faults. It determines the address,
- * and the problem, and then passes it off to one of the appropriate
- * routines.
- *
- * ARGUMENT:
- * regs : M32R SP reg.
- * error_code : See below
- * address : M32R MMU MDEVA reg. (Operand ACE)
- * : M32R BPC reg. (Instruction ACE)
- *
- * error_code :
- * bit 0 == 0 means no page found, 1 means protection fault
- * bit 1 == 0 means read, 1 means write
- * bit 2 == 0 means kernel, 1 means user-mode
- *======================================================================*/
-asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
- unsigned long address)
-{
-
-/*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- bust_spinlocks(1);
-
- if (address < PAGE_SIZE)
- printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
- else
- printk(KERN_ALERT "Unable to handle kernel paging request");
- printk(" at virtual address %08lx\n",address);
- printk(" printing bpc:\n");
- printk(KERN_ALERT "bpc = %08lx\n", regs->bpc);
-
- die("Oops", regs, error_code);
- bust_spinlocks(0);
- do_exit(SIGKILL);
-}
-
-/*======================================================================*
- * update_mmu_cache()
- *======================================================================*/
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
- pte_t *ptep)
-{
- BUG();
-}
-
-/*======================================================================*
- * flush_tlb_page() : flushes one page
- *======================================================================*/
-void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
- BUG();
-}
-
-/*======================================================================*
- * flush_tlb_range() : flushes a range of pages
- *======================================================================*/
-void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end)
-{
- BUG();
-}
-
-/*======================================================================*
- * flush_tlb_mm() : flushes the specified mm context TLB's
- *======================================================================*/
-void local_flush_tlb_mm(struct mm_struct *mm)
-{
- BUG();
-}
-
-/*======================================================================*
- * flush_tlb_all() : flushes all processes TLBs
- *======================================================================*/
-void local_flush_tlb_all(void)
-{
- BUG();
-}
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c
deleted file mode 100644
index 46d9a5ca0e3a..000000000000
--- a/arch/m32r/mm/fault.c
+++ /dev/null
@@ -1,550 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/mm/fault.c
- *
- * Copyright (c) 2001, 2002 Hitoshi Yamamoto, and H. Kondo
- * Copyright (c) 2004 Naoto Sugai, NIIBE Yutaka
- *
- * Some code taken from i386 version.
- * Copyright (C) 1995 Linus Torvalds
- */
-
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/tty.h>
-#include <linux/vt_kern.h> /* For unblank_screen() */
-#include <linux/highmem.h>
-#include <linux/extable.h>
-#include <linux/uaccess.h>
-
-#include <asm/m32r.h>
-#include <asm/hardirq.h>
-#include <asm/mmu_context.h>
-#include <asm/tlbflush.h>
-
-extern void die(const char *, struct pt_regs *, long);
-
-#ifndef CONFIG_SMP
-asmlinkage unsigned int tlb_entry_i_dat;
-asmlinkage unsigned int tlb_entry_d_dat;
-#define tlb_entry_i tlb_entry_i_dat
-#define tlb_entry_d tlb_entry_d_dat
-#else
-unsigned int tlb_entry_i_dat[NR_CPUS];
-unsigned int tlb_entry_d_dat[NR_CPUS];
-#define tlb_entry_i tlb_entry_i_dat[smp_processor_id()]
-#define tlb_entry_d tlb_entry_d_dat[smp_processor_id()]
-#endif
-
-extern void init_tlb(void);
-
-/*======================================================================*
- * do_page_fault()
- *======================================================================*
- * This routine handles page faults. It determines the address,
- * and the problem, and then passes it off to one of the appropriate
- * routines.
- *
- * ARGUMENT:
- * regs : M32R SP reg.
- * error_code : See below
- * address : M32R MMU MDEVA reg. (Operand ACE)
- * : M32R BPC reg. (Instruction ACE)
- *
- * error_code :
- * bit 0 == 0 means no page found, 1 means protection fault
- * bit 1 == 0 means read, 1 means write
- * bit 2 == 0 means kernel, 1 means user-mode
- * bit 3 == 0 means data, 1 means instruction
- *======================================================================*/
-#define ACE_PROTECTION 1
-#define ACE_WRITE 2
-#define ACE_USERMODE 4
-#define ACE_INSTRUCTION 8
-
-asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
- unsigned long address)
-{
- struct task_struct *tsk;
- struct mm_struct *mm;
- struct vm_area_struct * vma;
- unsigned long page, addr;
- unsigned long flags = 0;
- int fault;
- siginfo_t info;
-
- /*
- * If BPSW IE bit enable --> set PSW IE bit
- */
- if (regs->psw & M32R_PSW_BIE)
- local_irq_enable();
-
- tsk = current;
-
- info.si_code = SEGV_MAPERR;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- *
- * This verifies that the fault happens in kernel space
- * (error_code & ACE_USERMODE) == 0, and that the fault was not a
- * protection error (error_code & ACE_PROTECTION) == 0.
- */
- if (address >= TASK_SIZE && !(error_code & ACE_USERMODE))
- goto vmalloc_fault;
-
- mm = tsk->mm;
-
- /*
- * If we're in an interrupt or have no user context or have pagefaults
- * disabled then we must not take the fault.
- */
- if (faulthandler_disabled() || !mm)
- goto bad_area_nosemaphore;
-
- if (error_code & ACE_USERMODE)
- flags |= FAULT_FLAG_USER;
-
- /* When running in the kernel we expect faults to occur only to
- * addresses in user space. All other faults represent errors in the
- * kernel and should generate an OOPS. Unfortunately, in the case of an
- * erroneous fault occurring in a code path which already holds mmap_sem
- * we will deadlock attempting to validate the fault against the
- * address space. Luckily the kernel only validly references user
- * space from well defined areas of code, which are listed in the
- * exceptions table.
- *
- * As the vast majority of faults will be valid we will only perform
- * the source reference check when there is a possibility of a deadlock.
- * Attempt to lock the address space, if we cannot we then validate the
- * source. If this is invalid we can skip the address space check,
- * thus avoiding the deadlock.
- */
- if (!down_read_trylock(&mm->mmap_sem)) {
- if ((error_code & ACE_USERMODE) == 0 &&
- !search_exception_tables(regs->psw))
- goto bad_area_nosemaphore;
- down_read(&mm->mmap_sem);
- }
-
- vma = find_vma(mm, address);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= address)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
-
- if (error_code & ACE_USERMODE) {
- /*
- * accessing the stack below "spu" is always a bug.
- * The "+ 4" is there due to the push instruction
- * doing pre-decrement on the stack and that
- * doesn't show up until later..
- */
- if (address + 4 < regs->spu)
- goto bad_area;
- }
-
- if (expand_stack(vma, address))
- goto bad_area;
-/*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
-good_area:
- info.si_code = SEGV_ACCERR;
- switch (error_code & (ACE_WRITE|ACE_PROTECTION)) {
- default: /* 3: write, present */
- /* fall through */
- case ACE_WRITE: /* write, not present */
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- break;
- case ACE_PROTECTION: /* read, present */
- case 0: /* read, not present */
- if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
- goto bad_area;
- }
-
- /*
- * For instruction access exception, check if the area is executable
- */
- if ((error_code & ACE_INSTRUCTION) && !(vma->vm_flags & VM_EXEC))
- goto bad_area;
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
- addr = (address & PAGE_MASK);
- set_thread_fault_code(error_code);
- fault = handle_mm_fault(vma, addr, flags);
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
- if (fault & VM_FAULT_MAJOR)
- tsk->maj_flt++;
- else
- tsk->min_flt++;
- set_thread_fault_code(0);
- up_read(&mm->mmap_sem);
- return;
-
-/*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
-bad_area:
- up_read(&mm->mmap_sem);
-
-bad_area_nosemaphore:
- /* User mode accesses just cause a SIGSEGV */
- if (error_code & ACE_USERMODE) {
- tsk->thread.address = address;
- tsk->thread.error_code = error_code | (address >= TASK_SIZE);
- tsk->thread.trap_no = 14;
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
- info.si_addr = (void __user *)address;
- force_sig_info(SIGSEGV, &info, tsk);
- return;
- }
-
-no_context:
- /* Are we prepared to handle this kernel fault? */
- if (fixup_exception(regs))
- return;
-
-/*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- bust_spinlocks(1);
-
- if (address < PAGE_SIZE)
- printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
- else
- printk(KERN_ALERT "Unable to handle kernel paging request");
- printk(" at virtual address %08lx\n",address);
- printk(KERN_ALERT " printing bpc:\n");
- printk("%08lx\n", regs->bpc);
- page = *(unsigned long *)MPTB;
- page = ((unsigned long *) page)[address >> PGDIR_SHIFT];
- printk(KERN_ALERT "*pde = %08lx\n", page);
- if (page & _PAGE_PRESENT) {
- page &= PAGE_MASK;
- address &= 0x003ff000;
- page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
- printk(KERN_ALERT "*pte = %08lx\n", page);
- }
- die("Oops", regs, error_code);
- bust_spinlocks(0);
- do_exit(SIGKILL);
-
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-out_of_memory:
- up_read(&mm->mmap_sem);
- if (!(error_code & ACE_USERMODE))
- goto no_context;
- pagefault_out_of_memory();
- return;
-
-do_sigbus:
- up_read(&mm->mmap_sem);
-
- /* Kernel mode? Handle exception or die */
- if (!(error_code & ACE_USERMODE))
- goto no_context;
-
- tsk->thread.address = address;
- tsk->thread.error_code = error_code;
- tsk->thread.trap_no = 14;
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (void __user *)address;
- force_sig_info(SIGBUS, &info, tsk);
- return;
-
-vmalloc_fault:
- {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Do _not_ use "tsk" here. We might be inside
- * an interrupt in the middle of a task switch..
- */
- int offset = pgd_index(address);
- pgd_t *pgd, *pgd_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd = (pgd_t *)*(unsigned long *)MPTB;
- pgd = offset + (pgd_t *)pgd;
- pgd_k = init_mm.pgd + offset;
-
- if (!pgd_present(*pgd_k))
- goto no_context;
-
- /*
- * set_pgd(pgd, *pgd_k); here would be useless on PAE
- * and redundant with the set_pmd() on non-PAE.
- */
-
- pmd = pmd_offset(pgd, address);
- pmd_k = pmd_offset(pgd_k, address);
- if (!pmd_present(*pmd_k))
- goto no_context;
- set_pmd(pmd, *pmd_k);
-
- pte_k = pte_offset_kernel(pmd_k, address);
- if (!pte_present(*pte_k))
- goto no_context;
-
- addr = (address & PAGE_MASK);
- set_thread_fault_code(error_code);
- update_mmu_cache(NULL, addr, pte_k);
- set_thread_fault_code(0);
- return;
- }
-}
-
-/*======================================================================*
- * update_mmu_cache()
- *======================================================================*/
-#define TLB_MASK (NR_TLB_ENTRIES - 1)
-#define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
-#define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
- pte_t *ptep)
-{
- volatile unsigned long *entry1, *entry2;
- unsigned long pte_data, flags;
- unsigned int *entry_dat;
- int inst = get_thread_fault_code() & ACE_INSTRUCTION;
- int i;
-
- /* Ptrace may call this routine. */
- if (vma && current->active_mm != vma->vm_mm)
- return;
-
- local_irq_save(flags);
-
- vaddr = (vaddr & PAGE_MASK) | get_asid();
-
- pte_data = pte_val(*ptep);
-
-#ifdef CONFIG_CHIP_OPSP
- entry1 = (unsigned long *)ITLB_BASE;
- for (i = 0; i < NR_TLB_ENTRIES; i++) {
- if (*entry1++ == vaddr) {
- set_tlb_data(entry1, pte_data);
- break;
- }
- entry1++;
- }
- entry2 = (unsigned long *)DTLB_BASE;
- for (i = 0; i < NR_TLB_ENTRIES; i++) {
- if (*entry2++ == vaddr) {
- set_tlb_data(entry2, pte_data);
- break;
- }
- entry2++;
- }
-#else
- /*
- * Update TLB entries
- * entry1: ITLB entry address
- * entry2: DTLB entry address
- */
- __asm__ __volatile__ (
- "seth %0, #high(%4) \n\t"
- "st %2, @(%5, %0) \n\t"
- "ldi %1, #1 \n\t"
- "st %1, @(%6, %0) \n\t"
- "add3 r4, %0, %7 \n\t"
- ".fillinsn \n"
- "1: \n\t"
- "ld %1, @(%6, %0) \n\t"
- "bnez %1, 1b \n\t"
- "ld %0, @r4+ \n\t"
- "ld %1, @r4 \n\t"
- "st %3, @+%0 \n\t"
- "st %3, @+%1 \n\t"
- : "=&r" (entry1), "=&r" (entry2)
- : "r" (vaddr), "r" (pte_data), "i" (MMU_REG_BASE),
- "i" (MSVA_offset), "i" (MTOP_offset), "i" (MIDXI_offset)
- : "r4", "memory"
- );
-#endif
-
- if ((!inst && entry2 >= DTLB_END) || (inst && entry1 >= ITLB_END))
- goto notfound;
-
-found:
- local_irq_restore(flags);
-
- return;
-
- /* Valid entry not found */
-notfound:
- /*
- * Update ITLB or DTLB entry
- * entry1: TLB entry address
- * entry2: TLB base address
- */
- if (!inst) {
- entry2 = (unsigned long *)DTLB_BASE;
- entry_dat = &tlb_entry_d;
- } else {
- entry2 = (unsigned long *)ITLB_BASE;
- entry_dat = &tlb_entry_i;
- }
- entry1 = entry2 + (((*entry_dat - 1) & TLB_MASK) << 1);
-
- for (i = 0 ; i < NR_TLB_ENTRIES ; i++) {
- if (!(entry1[1] & 2)) /* Valid bit check */
- break;
-
- if (entry1 != entry2)
- entry1 -= 2;
- else
- entry1 += TLB_MASK << 1;
- }
-
- if (i >= NR_TLB_ENTRIES) { /* Empty entry not found */
- entry1 = entry2 + (*entry_dat << 1);
- *entry_dat = (*entry_dat + 1) & TLB_MASK;
- }
- *entry1++ = vaddr; /* Set TLB tag */
- set_tlb_data(entry1, pte_data);
-
- goto found;
-}
-
-/*======================================================================*
- * flush_tlb_page() : flushes one page
- *======================================================================*/
-void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
- if (vma->vm_mm && mm_context(vma->vm_mm) != NO_CONTEXT) {
- unsigned long flags;
-
- local_irq_save(flags);
- page &= PAGE_MASK;
- page |= (mm_context(vma->vm_mm) & MMU_CONTEXT_ASID_MASK);
- __flush_tlb_page(page);
- local_irq_restore(flags);
- }
-}
-
-/*======================================================================*
- * flush_tlb_range() : flushes a range of pages
- *======================================================================*/
-void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end)
-{
- struct mm_struct *mm;
-
- mm = vma->vm_mm;
- if (mm_context(mm) != NO_CONTEXT) {
- unsigned long flags;
- int size;
-
- local_irq_save(flags);
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- if (size > (NR_TLB_ENTRIES / 4)) { /* Too many TLB to flush */
- mm_context(mm) = NO_CONTEXT;
- if (mm == current->mm)
- activate_context(mm);
- } else {
- unsigned long asid;
-
- asid = mm_context(mm) & MMU_CONTEXT_ASID_MASK;
- start &= PAGE_MASK;
- end += (PAGE_SIZE - 1);
- end &= PAGE_MASK;
-
- start |= asid;
- end |= asid;
- while (start < end) {
- __flush_tlb_page(start);
- start += PAGE_SIZE;
- }
- }
- local_irq_restore(flags);
- }
-}
-
-/*======================================================================*
- * flush_tlb_mm() : flushes the specified mm context TLB's
- *======================================================================*/
-void local_flush_tlb_mm(struct mm_struct *mm)
-{
- /* Invalidate all TLB of this process. */
- /* Instead of invalidating each TLB, we get new MMU context. */
- if (mm_context(mm) != NO_CONTEXT) {
- unsigned long flags;
-
- local_irq_save(flags);
- mm_context(mm) = NO_CONTEXT;
- if (mm == current->mm)
- activate_context(mm);
- local_irq_restore(flags);
- }
-}
-
-/*======================================================================*
- * flush_tlb_all() : flushes all processes TLBs
- *======================================================================*/
-void local_flush_tlb_all(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- __flush_tlb_all();
- local_irq_restore(flags);
-}
-
-/*======================================================================*
- * init_mmu()
- *======================================================================*/
-void __init init_mmu(void)
-{
- tlb_entry_i = 0;
- tlb_entry_d = 0;
- mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
- set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
- *(volatile unsigned long *)MPTB = (unsigned long)swapper_pg_dir;
-}
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
deleted file mode 100644
index 93abc8c3a46e..000000000000
--- a/arch/m32r/mm/init.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/mm/init.c
- *
- * Copyright (c) 2001, 2002 Hitoshi Yamamoto
- *
- * Some code taken from sh version.
- * Copyright (C) 1999 Niibe Yutaka
- * Based on linux/arch/i386/mm/init.c:
- * Copyright (C) 1995 Linus Torvalds
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/pagemap.h>
-#include <linux/bootmem.h>
-#include <linux/swap.h>
-#include <linux/highmem.h>
-#include <linux/bitops.h>
-#include <linux/nodemask.h>
-#include <linux/pfn.h>
-#include <linux/gfp.h>
-#include <asm/types.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/mmu_context.h>
-#include <asm/setup.h>
-#include <asm/tlb.h>
-#include <asm/sections.h>
-
-pgd_t swapper_pg_dir[1024];
-
-/*
- * Cache of MMU context last used.
- */
-#ifndef CONFIG_SMP
-unsigned long mmu_context_cache_dat;
-#else
-unsigned long mmu_context_cache_dat[NR_CPUS];
-#endif
-
-/*
- * function prototype
- */
-void __init paging_init(void);
-void __init mem_init(void);
-void free_initmem(void);
-#ifdef CONFIG_BLK_DEV_INITRD
-void free_initrd_mem(unsigned long, unsigned long);
-#endif
-
-/* It'd be good if these lines were in the standard header file. */
-#define START_PFN(nid) (NODE_DATA(nid)->bdata->node_min_pfn)
-#define MAX_LOW_PFN(nid) (NODE_DATA(nid)->bdata->node_low_pfn)
-
-#ifndef CONFIG_DISCONTIGMEM
-void __init zone_sizes_init(void)
-{
- unsigned long zones_size[MAX_NR_ZONES] = {0, };
- unsigned long start_pfn;
-
-#ifdef CONFIG_MMU
- {
- unsigned long low;
- unsigned long max_dma;
-
- start_pfn = START_PFN(0);
- max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
- low = MAX_LOW_PFN(0);
-
- if (low < max_dma) {
- zones_size[ZONE_DMA] = low - start_pfn;
- zones_size[ZONE_NORMAL] = 0;
- } else {
- zones_size[ZONE_DMA] = low - start_pfn;
- zones_size[ZONE_NORMAL] = low - max_dma;
- }
- }
-#else
- zones_size[ZONE_DMA] = 0 >> PAGE_SHIFT;
- zones_size[ZONE_NORMAL] = __MEMORY_SIZE >> PAGE_SHIFT;
- start_pfn = __MEMORY_START >> PAGE_SHIFT;
-#endif /* CONFIG_MMU */
-
- free_area_init_node(0, zones_size, start_pfn, 0);
-}
-#else /* CONFIG_DISCONTIGMEM */
-extern void zone_sizes_init(void);
-#endif /* CONFIG_DISCONTIGMEM */
-
-/*======================================================================*
- * paging_init() : sets up the page tables
- *======================================================================*/
-void __init paging_init(void)
-{
-#ifdef CONFIG_MMU
- int i;
- pgd_t *pg_dir;
-
- /* We don't need kernel mapping as hardware support that. */
- pg_dir = swapper_pg_dir;
-
- for (i = 0 ; i < USER_PTRS_PER_PGD * 2 ; i++)
- pgd_val(pg_dir[i]) = 0;
-#endif /* CONFIG_MMU */
- zone_sizes_init();
-}
-
-/*======================================================================*
- * mem_init() :
- * orig : arch/sh/mm/init.c
- *======================================================================*/
-void __init mem_init(void)
-{
-#ifndef CONFIG_MMU
- extern unsigned long memory_end;
-
- high_memory = (void *)(memory_end & PAGE_MASK);
-#else
- high_memory = (void *)__va(PFN_PHYS(MAX_LOW_PFN(0)));
-#endif /* CONFIG_MMU */
-
- /* clear the zero-page */
- memset(empty_zero_page, 0, PAGE_SIZE);
-
- set_max_mapnr(get_num_physpages());
- free_all_bootmem();
- mem_init_print_info(NULL);
-}
-
-/*======================================================================*
- * free_initmem() :
- * orig : arch/sh/mm/init.c
- *======================================================================*/
-void free_initmem(void)
-{
- free_initmem_default(-1);
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-/*======================================================================*
- * free_initrd_mem() :
- * orig : arch/sh/mm/init.c
- *======================================================================*/
-void free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_reserved_area((void *)start, (void *)end, -1, "initrd");
-}
-#endif
diff --git a/arch/m32r/mm/ioremap-nommu.c b/arch/m32r/mm/ioremap-nommu.c
deleted file mode 100644
index 2759f2d48384..000000000000
--- a/arch/m32r/mm/ioremap-nommu.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * linux/arch/m32r/mm/ioremap-nommu.c
- *
- * Copyright (c) 2001, 2002 Hiroyuki Kondo
- *
- * Taken from mips version.
- * (C) Copyright 1995 1996 Linus Torvalds
- * (C) Copyright 2001 Ralf Baechle
- */
-
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-
-#include <linux/module.h>
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <linux/vmalloc.h>
-#include <asm/io.h>
-#include <asm/pgalloc.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-
-
-/*
- * Remap an arbitrary physical address space into the kernel virtual
- * address space. Needed when the kernel wants to access high addresses
- * directly.
- *
- * NOTE! We need to allow non-page-aligned mappings too: we will obviously
- * have to convert them into an offset in a page-aligned mapping, but the
- * caller shouldn't need to know that small detail.
- */
-
-#define IS_LOW512(addr) (!((unsigned long)(addr) & ~0x1fffffffUL))
-
-void __iomem *
-__ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
-{
- return (void *)phys_addr;
-}
-
-#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1)
-
-void iounmap(volatile void __iomem *addr)
-{
-}
-
diff --git a/arch/m32r/mm/ioremap.c b/arch/m32r/mm/ioremap.c
deleted file mode 100644
index 5152c4e6ac80..000000000000
--- a/arch/m32r/mm/ioremap.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * linux/arch/m32r/mm/ioremap.c
- *
- * Copyright (c) 2001, 2002 Hiroyuki Kondo
- *
- * Taken from mips version.
- * (C) Copyright 1995 1996 Linus Torvalds
- * (C) Copyright 2001 Ralf Baechle
- */
-
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
-
-#include <linux/module.h>
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#include <linux/vmalloc.h>
-#include <linux/io.h>
-#include <asm/pgalloc.h>
-
-/*
- * Generic mapping function (not visible outside):
- */
-
-/*
- * Remap an arbitrary physical address space into the kernel virtual
- * address space. Needed when the kernel wants to access high addresses
- * directly.
- *
- * NOTE! We need to allow non-page-aligned mappings too: we will obviously
- * have to convert them into an offset in a page-aligned mapping, but the
- * caller shouldn't need to know that small detail.
- */
-
-#define IS_LOW512(addr) (!((unsigned long)(addr) & ~0x1fffffffUL))
-
-void __iomem *
-__ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags)
-{
- void __iomem * addr;
- struct vm_struct * area;
- unsigned long offset, last_addr;
- pgprot_t pgprot;
-
- /* Don't allow wraparound or zero size */
- last_addr = phys_addr + size - 1;
- if (!size || last_addr < phys_addr)
- return NULL;
-
- /*
- * Map objects in the low 512mb of address space using KSEG1, otherwise
- * map using page tables.
- */
- if (IS_LOW512(phys_addr) && IS_LOW512(phys_addr + size - 1))
- return (void *) KSEG1ADDR(phys_addr);
-
- /*
- * Don't allow anybody to remap normal RAM that we're using..
- */
- if (phys_addr < virt_to_phys(high_memory)) {
- char *t_addr, *t_end;
- struct page *page;
-
- t_addr = __va(phys_addr);
- t_end = t_addr + (size - 1);
-
- for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++)
- if(!PageReserved(page))
- return NULL;
- }
-
- pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_READ
- | _PAGE_WRITE | flags);
-
- /*
- * Mappings have to be page-aligned
- */
- offset = phys_addr & ~PAGE_MASK;
- phys_addr &= PAGE_MASK;
- size = PAGE_ALIGN(last_addr + 1) - phys_addr;
-
- /*
- * Ok, go for it..
- */
- area = get_vm_area(size, VM_IOREMAP);
- if (!area)
- return NULL;
- area->phys_addr = phys_addr;
- addr = (void __iomem *) area->addr;
- if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size,
- phys_addr, pgprot)) {
- vunmap((void __force *) addr);
- return NULL;
- }
-
- return (void __iomem *) (offset + (char __iomem *)addr);
-}
-
-#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == KSEG1)
-
-void iounmap(volatile void __iomem *addr)
-{
- if (!IS_KSEG1(addr))
- vfree((void *) (PAGE_MASK & (unsigned long) addr));
-}
-
diff --git a/arch/m32r/mm/mmu.S b/arch/m32r/mm/mmu.S
deleted file mode 100644
index fd8f9c9b7b07..000000000000
--- a/arch/m32r/mm/mmu.S
+++ /dev/null
@@ -1,355 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/m32r/mm/mmu.S
- *
- * Copyright (C) 2001 by Hiroyuki Kondo
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/smp.h>
-
- .text
-#ifdef CONFIG_MMU
-
-#include <asm/mmu_context.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/m32r.h>
-
-/*
- * TLB Miss Exception handler
- */
- .balign 16
-ENTRY(tme_handler)
- .global tlb_entry_i_dat
- .global tlb_entry_d_dat
-
- SWITCH_TO_KERNEL_STACK
-
-#if defined(CONFIG_ISA_M32R2)
- st r0, @-sp
- st r1, @-sp
- st r2, @-sp
- st r3, @-sp
-
- seth r3, #high(MMU_REG_BASE)
- ld r1, @(MESTS_offset, r3) ; r1: status (MESTS reg.)
- ld r0, @(MDEVP_offset, r3) ; r0: PFN + ASID (MDEVP reg.)
- st r1, @(MESTS_offset, r3) ; clear status (MESTS reg.)
- and3 r1, r1, #(MESTS_IT)
- bnez r1, 1f ; instruction TLB miss?
-
-;; data TLB miss
-;; input
-;; r0: PFN + ASID (MDEVP reg.)
-;; r1 - r3: free
-;; output
-;; r0: PFN + ASID
-;; r1: TLB entry base address
-;; r2: &tlb_entry_{i|d}_dat
-;; r3: free
-
-#ifndef CONFIG_SMP
- seth r2, #high(tlb_entry_d_dat)
- or3 r2, r2, #low(tlb_entry_d_dat)
-#else /* CONFIG_SMP */
- ldi r1, #-8192
- seth r2, #high(tlb_entry_d_dat)
- or3 r2, r2, #low(tlb_entry_d_dat)
- and r1, sp
- ld r1, @(16, r1) ; current_thread_info->cpu
- slli r1, #2
- add r2, r1
-#endif /* !CONFIG_SMP */
- seth r1, #high(DTLB_BASE)
- or3 r1, r1, #low(DTLB_BASE)
- bra 2f
-
- .balign 16
- .fillinsn
-1:
-;; instrucntion TLB miss
-;; input
-;; r0: MDEVP reg. (included ASID)
-;; r1 - r3: free
-;; output
-;; r0: PFN + ASID
-;; r1: TLB entry base address
-;; r2: &tlb_entry_{i|d}_dat
-;; r3: free
- ldi r3, #-4096
- and3 r0, r0, #(MMU_CONTEXT_ASID_MASK)
- mvfc r1, bpc
- and r1, r3
- or r0, r1 ; r0: PFN + ASID
-#ifndef CONFIG_SMP
- seth r2, #high(tlb_entry_i_dat)
- or3 r2, r2, #low(tlb_entry_i_dat)
-#else /* CONFIG_SMP */
- ldi r1, #-8192
- seth r2, #high(tlb_entry_i_dat)
- or3 r2, r2, #low(tlb_entry_i_dat)
- and r1, sp
- ld r1, @(16, r1) ; current_thread_info->cpu
- slli r1, #2
- add r2, r1
-#endif /* !CONFIG_SMP */
- seth r1, #high(ITLB_BASE)
- or3 r1, r1, #low(ITLB_BASE)
-
- .fillinsn
-2:
-;; select TLB entry
-;; input
-;; r0: PFN + ASID
-;; r1: TLB entry base address
-;; r2: &tlb_entry_{i|d}_dat
-;; r3: free
-;; output
-;; r0: PFN + ASID
-;; r1: TLB entry address
-;; r2, r3: free
-#ifdef CONFIG_ISA_DUAL_ISSUE
- ld r3, @r2 || srli r1, #3
-#else
- ld r3, @r2
- srli r1, #3
-#endif
- add r1, r3
- ; tlb_entry_{d|i}_dat++;
- addi r3, #1
- and3 r3, r3, #(NR_TLB_ENTRIES - 1)
-#ifdef CONFIG_ISA_DUAL_ISSUE
- st r3, @r2 || slli r1, #3
-#else
- st r3, @r2
- slli r1, #3
-#endif
-
-;; load pte
-;; input
-;; r0: PFN + ASID
-;; r1: TLB entry address
-;; r2, r3: free
-;; output
-;; r0: PFN + ASID
-;; r1: TLB entry address
-;; r2: pte_data
-;; r3: free
- ; pgd = *(unsigned long *)MPTB;
- ld24 r2, #(-MPTB - 1)
- srl3 r3, r0, #22
-#ifdef CONFIG_ISA_DUAL_ISSUE
- not r2, r2 || slli r3, #2 ; r3: pgd offset
-#else
- not r2, r2
- slli r3, #2
-#endif
- ld r2, @r2 ; r2: pgd base addr (MPTB reg.)
- or r3, r2 ; r3: pmd addr
-
- ; pmd = pmd_offset(pgd, address);
- ld r3, @r3 ; r3: pmd data
- beqz r3, 3f ; pmd_none(*pmd) ?
-
- and3 r2, r3, #0xfff
- add3 r2, r2, #-355 ; _KERNPG_TABLE(=0x163)
- bnez r2, 3f ; pmd_bad(*pmd) ?
- ldi r2, #-4096
-
- ; pte = pte_offset(pmd, address);
- and r2, r3 ; r2: pte base addr
- srl3 r3, r0, #10
- and3 r3, r3, #0xffc ; r3: pte offset
- or r3, r2
- seth r2, #0x8000
- or r3, r2 ; r3: pte addr
-
- ; pte_data = (unsigned long)pte_val(*pte);
- ld r2, @r3 ; r2: pte data
- and3 r3, r2, #2 ; _PAGE_PRESENT(=2) check
- beqz r3, 3f
-
- .fillinsn
-5:
-;; set tlb
-;; input
-;; r0: PFN + ASID
-;; r1: TLB entry address
-;; r2: pte_data
-;; r3: free
- st r0, @r1 ; set_tlb_tag(entry++, address);
- st r2, @+r1 ; set_tlb_data(entry, pte_data);
-
- .fillinsn
-6:
- ld r3, @sp+
- ld r2, @sp+
- ld r1, @sp+
- ld r0, @sp+
- rte
-
- .fillinsn
-3:
-;; error
-;; input
-;; r0: PFN + ASID
-;; r1: TLB entry address
-;; r2, r3: free
-;; output
-;; r0: PFN + ASID
-;; r1: TLB entry address
-;; r2: pte_data
-;; r3: free
-#ifdef CONFIG_ISA_DUAL_ISSUE
- bra 5b || ldi r2, #2
-#else
- ldi r2, #2 ; r2: pte_data = 0 | _PAGE_PRESENT(=2)
- bra 5b
-#endif
-
-#elif defined (CONFIG_ISA_M32R)
-
- st sp, @-sp
- st r0, @-sp
- st r1, @-sp
- st r2, @-sp
- st r3, @-sp
- st r4, @-sp
-
- seth r3, #high(MMU_REG_BASE)
- ld r0, @(MDEVA_offset,r3) ; r0: address (MDEVA reg.)
- mvfc r2, bpc ; r2: bpc
- ld r1, @(MESTS_offset,r3) ; r1: status (MESTS reg.)
- st r1, @(MESTS_offset,r3) ; clear status (MESTS reg.)
- and3 r1, r1, #(MESTS_IT)
- beqz r1, 1f ; data TLB miss?
-
-;; instrucntion TLB miss
- mv r0, r2 ; address = bpc;
- ; entry = (unsigned long *)ITLB_BASE+tlb_entry_i*2;
- seth r3, #shigh(tlb_entry_i_dat)
- ld r4, @(low(tlb_entry_i_dat),r3)
- sll3 r2, r4, #3
- seth r1, #high(ITLB_BASE)
- or3 r1, r1, #low(ITLB_BASE)
- add r2, r1 ; r2: entry
- addi r4, #1 ; tlb_entry_i++;
- and3 r4, r4, #(NR_TLB_ENTRIES-1)
- st r4, @(low(tlb_entry_i_dat),r3)
- bra 2f
- .fillinsn
-1:
-;; data TLB miss
- ; entry = (unsigned long *)DTLB_BASE+tlb_entry_d*2;
- seth r3, #shigh(tlb_entry_d_dat)
- ld r4, @(low(tlb_entry_d_dat),r3)
- sll3 r2, r4, #3
- seth r1, #high(DTLB_BASE)
- or3 r1, r1, #low(DTLB_BASE)
- add r2, r1 ; r2: entry
- addi r4, #1 ; tlb_entry_d++;
- and3 r4, r4, #(NR_TLB_ENTRIES-1)
- st r4, @(low(tlb_entry_d_dat),r3)
- .fillinsn
-2:
-;; load pte
-; r0: address, r2: entry
-; r1,r3,r4: (free)
- ; pgd = *(unsigned long *)MPTB;
- ld24 r1, #(-MPTB-1)
- not r1, r1
- ld r1, @r1
- srl3 r4, r0, #22
- sll3 r3, r4, #2
- add r3, r1 ; r3: pgd
- ; pmd = pmd_offset(pgd, address);
- ld r1, @r3 ; r1: pmd
- beqz r1, 3f ; pmd_none(*pmd) ?
-;
- and3 r1, r1, #0x3ff
- ldi r4, #0x163 ; _KERNPG_TABLE(=0x163)
- bne r1, r4, 3f ; pmd_bad(*pmd) ?
-
- .fillinsn
-4:
- ; pte = pte_offset(pmd, address);
- ld r4, @r3 ; r4: pte
- ldi r3, #-4096
- and r4, r3
- srl3 r3, r0, #10
- and3 r3, r3, #0xffc
- add r4, r3
- seth r3, #0x8000
- add r4, r3 ; r4: pte
- ; pte_data = (unsigned long)pte_val(*pte);
- ld r1, @r4 ; r1: pte_data
- and3 r3, r1, #2 ; _PAGE_PRESENT(=2) check
- beqz r3, 3f
-
- .fillinsn
-;; set tlb
-; r0: address, r1: pte_data, r2: entry
-; r3,r4: (free)
-5:
- ldi r3, #-4096 ; set_tlb_tag(entry++, address);
- and r3, r0
- seth r4, #shigh(MASID)
- ld r4, @(low(MASID),r4) ; r4: MASID
- and3 r4, r4, #(MMU_CONTEXT_ASID_MASK)
- or r3, r4
- st r3, @r2
- st r1, @(4,r2) ; set_tlb_data(entry, pte_data);
-
- ld r4, @sp+
- ld r3, @sp+
- ld r2, @sp+
- ld r1, @sp+
- ld r0, @sp+
- ld sp, @sp+
- rte
-
- .fillinsn
-3:
- ldi r1, #2 ; r1: pte_data = 0 | _PAGE_PRESENT(=2)
- bra 5b
-
-#else
-#error unknown isa configuration
-#endif
-
-ENTRY(init_tlb)
-;; Set MMU Register
- seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
- or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
- ldi r1, #0
- st r1, @(MPSZ_offset,r0) ; Set MPSZ Reg(Page size 4KB:0 16KB:1 64KB:2)
- ldi r1, #0
- st r1, @(MASID_offset,r0) ; Set ASID Zero
-
-;; Set TLB
- seth r0, #high(ITLB_BASE) ; Set ITLB_BASE higher
- or3 r0, r0, #low(ITLB_BASE) ; Set ITLB_BASE lower
- seth r1, #high(DTLB_BASE) ; Set DTLB_BASE higher
- or3 r1, r1, #low(DTLB_BASE) ; Set DTLB_BASE lower
- ldi r2, #0
- ldi r3, #NR_TLB_ENTRIES
- addi r0, #-4
- addi r1, #-4
-clear_tlb:
- st r2, @+r0 ; VPA <- 0
- st r2, @+r0 ; PPA <- 0
- st r2, @+r1 ; VPA <- 0
- st r2, @+r1 ; PPA <- 0
- addi r3, #-1
- bnez r3, clear_tlb
-;;
- jmp r14
-
-ENTRY(m32r_itlb_entrys)
-ENTRY(m32r_otlb_entrys)
-
-#endif /* CONFIG_MMU */
-
- .end
diff --git a/arch/m32r/mm/page.S b/arch/m32r/mm/page.S
deleted file mode 100644
index a2e9367dbf79..000000000000
--- a/arch/m32r/mm/page.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * linux/arch/m32r/mm/page.S
- *
- * Clear/Copy page with CPU
- *
- * Copyright (C) 2004 The Free Software Initiative of Japan
- *
- * Written by Niibe Yutaka
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- */
- .text
- .global copy_page
- /*
- * copy_page (to, from)
- *
- * PAGE_SIZE = 4096-byte
- * Cache line = 16-byte
- * 16 * 256
- */
- .align 4
-copy_page:
- ldi r2, #255
- ld r3, @r0 /* cache line allocate */
- ld r4, @r1+
- ld r5, @r1+
- ld r6, @r1+
- ld r7, @r1+
- .fillinsn
-0:
- st r4, @r0
- st r5, @+r0
- st r6, @+r0
- st r7, @+r0
- ld r4, @r1+
- addi r0, #4
- ld r5, @r1+
- ld r6, @r1+
- ld r7, @r1+
- ld r3, @r0 /* cache line allocate */
- addi r2, #-1
- bnez r2, 0b
-
- st r4, @r0
- st r5, @+r0
- st r6, @+r0
- st r7, @+r0
- jmp r14
-
- .text
- .global clear_page
- /*
- * clear_page (to)
- *
- * PAGE_SIZE = 4096-byte
- * Cache line = 16-byte
- * 16 * 256
- */
- .align 4
-clear_page:
- ldi r2, #255
- ldi r4, #0
- ld r3, @r0 /* cache line allocate */
- .fillinsn
-0:
- st r4, @r0
- st r4, @+r0
- st r4, @+r0
- st r4, @+r0
- addi r0, #4
- ld r3, @r0 /* cache line allocate */
- addi r2, #-1
- bnez r2, 0b
-
- st r4, @r0
- st r4, @+r0
- st r4, @+r0
- st r4, @+r0
- jmp r14
diff --git a/arch/m32r/oprofile/Makefile b/arch/m32r/oprofile/Makefile
deleted file mode 100644
index 8e63a3a5a64c..000000000000
--- a/arch/m32r/oprofile/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_OPROFILE) += oprofile.o
-
-DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
- oprof.o cpu_buffer.o buffer_sync.o \
- event_buffer.o oprofile_files.o \
- oprofilefs.o oprofile_stats.o \
- timer_int.o )
-
-oprofile-y := $(DRIVER_OBJS) init.o
diff --git a/arch/m32r/oprofile/init.c b/arch/m32r/oprofile/init.c
deleted file mode 100644
index fa56860f4258..000000000000
--- a/arch/m32r/oprofile/init.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/**
- * @file init.c
- *
- * @remark Copyright 2002 OProfile authors
- * @remark Read the file COPYING
- *
- * @author John Levon <levon@movementarian.org>
- */
-
-#include <linux/kernel.h>
-#include <linux/oprofile.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- return -ENODEV;
-}
-
-void oprofile_arch_exit(void)
-{
-}
diff --git a/arch/m32r/platforms/Makefile b/arch/m32r/platforms/Makefile
deleted file mode 100644
index 9e1a82529ad9..000000000000
--- a/arch/m32r/platforms/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# arch/m32r/platforms/Makefile
-obj-$(CONFIG_PLAT_M32104UT) += m32104ut/
-obj-$(CONFIG_PLAT_M32700UT) += m32700ut/
-obj-$(CONFIG_PLAT_MAPPI) += mappi/
-obj-$(CONFIG_PLAT_MAPPI2) += mappi2/
-obj-$(CONFIG_PLAT_MAPPI3) += mappi3/
-obj-$(CONFIG_PLAT_OAKS32R) += oaks32r/
-obj-$(CONFIG_PLAT_OPSPUT) += opsput/
-obj-$(CONFIG_PLAT_USRV) += usrv/
diff --git a/arch/m32r/platforms/m32104ut/Makefile b/arch/m32r/platforms/m32104ut/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/m32104ut/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/m32104ut/io.c b/arch/m32r/platforms/m32104ut/io.c
deleted file mode 100644
index ff2bb3b58bb5..000000000000
--- a/arch/m32r/platforms/m32104ut/io.c
+++ /dev/null
@@ -1,298 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/m32104ut/io.c
- *
- * Typical I/O routines for M32104UT board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa,
- * Naoto Sugai, Hayato Fujiwara
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
-#include <linux/types.h>
-
-#define M32R_PCC_IOMAP_SIZE 0x1000
-
-#define M32R_PCC_IOSTART0 0x1000
-#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
-
-extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
-#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
-
-#define PORT2ADDR(port) _port2addr(port)
-
-static inline void *_port2addr(unsigned long port)
-{
- return (void *)(port | NONCACHE_OFFSET);
-}
-
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
-static inline void *__port2addr_ata(unsigned long port)
-{
- static int dummy_reg;
-
- switch (port) {
- case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
- case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
- case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
- case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
- case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
- case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
- case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
- case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
- case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
- default: return (void *)&dummy_reg;
- }
-}
-#endif
-
-/*
- * M32104T-LAN is located in the extended bus space
- * from 0x01000000 to 0x01ffffff on physical address.
- * The base address of LAN controller(LAN91C111) is 0x300.
- */
-#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
-#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)(port + NONCACHE_OFFSET + 0x01000000);
-}
-
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-/*
- * NIC I/O function
- */
-
-#define PORT2ADDR_NE(port) _port2addr_ne(port)
-
-static inline unsigned char _ne_inb(void *portp)
-{
- return *(volatile unsigned char *)portp;
-}
-
-static inline unsigned short _ne_inw(void *portp)
-{
- return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
-}
-
-static inline void _ne_insb(void *portp, void *addr, unsigned long count)
-{
- unsigned char *buf = (unsigned char *)addr;
-
- while (count--)
- *buf++ = _ne_inb(portp);
-}
-
-static inline void _ne_outb(unsigned char b, void *portp)
-{
- *(volatile unsigned char *)portp = b;
-}
-
-static inline void _ne_outw(unsigned short w, void *portp)
-{
- *(volatile unsigned short *)portp = cpu_to_le16(w);
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inb(PORT2ADDR_NE(port));
-
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inw(PORT2ADDR_NE(port));
-
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return (v);
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return (v);
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return (v);
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outb(b, PORT2ADDR_NE(port));
- else
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outw(w, PORT2ADDR_NE(port));
- else
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void *addr, unsigned long count)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_insb(PORT2ADDR_NE(port), addr, count);
- else {
- unsigned char *buf = addr;
- unsigned char *portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void *addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- /*
- * This portion is only used by smc91111.c to read data
- * from the DATA_REG. Do not swap the data.
- */
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void *addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outb(*buf++, portp);
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- /*
- * This portion is only used by smc91111.c to write data
- * into the DATA_REG. Do not swap the data.
- */
- portp = PORT2ADDR_NE(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
deleted file mode 100644
index 297936003b1f..000000000000
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ /dev/null
@@ -1,139 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/m32104ut/setup.c
- *
- * Setup routines for M32104UT Board
- *
- * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa,
- * Naoto Sugai, Hayato Fujiwara
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[NR_IRQS];
-
-static void disable_m32104ut_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_m32104ut_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_m32104ut_irq(struct irq_data *data)
-{
- disable_m32104ut_irq(data->irq);
-}
-
-static void unmask_m32104ut_irq(struct irq_data *data)
-{
- enable_m32104ut_irq(data->irq);
-}
-
-static void shutdown_m32104ut_irq(struct irq_data *data)
-{
- unsigned int irq = data->irq;
- unsigned long port = irq2port(irq);
-
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip m32104ut_irq_type =
-{
- .name = "M32104UT-IRQ",
- .irq_shutdown = shutdown_m32104ut_irq,
- .irq_unmask = unmask_m32104ut_irq,
- .irq_mask = mask_m32104ut_irq,
-};
-
-void __init init_IRQ(void)
-{
- static int once = 0;
-
- if (once)
- return;
- else
- once++;
-
-#if defined(CONFIG_SMC91X)
- /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
- irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
- handle_level_irq);
- /* "H" level sense */
- cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
- disable_m32104ut_irq(M32R_IRQ_INT0);
-#endif /* CONFIG_SMC91X */
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_m32104ut_irq(M32R_IRQ_MFT2);
-
-#ifdef CONFIG_SERIAL_M32R_SIO
- /* SIO0_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
- disable_m32104ut_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
- disable_m32104ut_irq(M32R_IRQ_SIO0_S);
-#endif /* CONFIG_SERIAL_M32R_SIO */
-}
-
-#if defined(CONFIG_SMC91X)
-
-#define LAN_IOSTART 0x300
-#define LAN_IOEND 0x320
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (LAN_IOSTART),
- .end = (LAN_IOEND),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = M32R_IRQ_INT0,
- .end = M32R_IRQ_INT0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-#endif
-
-static int __init platform_init(void)
-{
-#if defined(CONFIG_SMC91X)
- platform_device_register(&smc91x_device);
-#endif
- return 0;
-}
-arch_initcall(platform_init);
diff --git a/arch/m32r/platforms/m32700ut/Makefile b/arch/m32r/platforms/m32700ut/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/m32700ut/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/m32700ut/dot.gdbinit_200MHz_16MB b/arch/m32r/platforms/m32700ut/dot.gdbinit_200MHz_16MB
deleted file mode 100644
index 525dab46982b..000000000000
--- a/arch/m32r/platforms/m32700ut/dot.gdbinit_200MHz_16MB
+++ /dev/null
@@ -1,249 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit_200MHz_16MB,v 1.2 2004/10/20 03:02:27 fujiwara Exp $
-#-----
-# NOTE: this file is generated by a script, "gen_gdbinit.pl".
-# (Please type "gen_gdbinit.pl --help" and check the help message).
-# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
-#-----
-# target platform: m32700ut
-
-# setting
-set width 0d70
-set radix 0d16
-
-debug_chaos
-
-# clk xin:cpu:bif:bus=25:200:50:50
-define clock_init
- set *(unsigned long *)0x00ef4008 = 0x00000000
- set *(unsigned long *)0x00ef4004 = 0
- shell sleep 0.1
- # NOTE: Please change the master clock source from PLL-clock to Xin-clock
- # and switch off PLL, before resetting the clock gear ratio.
-
- set *(unsigned long *)0x00ef4024 = 2
- set *(unsigned long *)0x00ef4020 = 2
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 3
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x00000200
-end
-
-# Initialize SDRAM controller
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008 = 0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c = 0x00000001
- # Initialize wait
- shell sleep 0.1
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c = 0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028 = 0x00041302
- # Ch0-ADR (size:16MB)
- set *(unsigned long *)0x00ef6020 = 0x08000002
- # AutoRef On
- set *(unsigned long *)0x00ef6004 = 0x00010517
- # Access enable
- set *(unsigned long *)0x00ef6024 = 0x00000001
-end
-document sdram_init
- SDRAM controller initialization
- 0x08000000 - 0x08ffffff (16MB)
-end
-
-# Initialize BSEL3 for UT-CFC
-define cfc_init
- set $sfrbase = 0xa0ef0000
-# too fast
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
-end
-document cfc_init
- CF controller initialization
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb 0d32
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb 0d32
-end
-
-# Initialize TLB entries
-define init_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set *(unsigned long *)($addr + 0x4) = 0
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define tlb_init
- set $itlb=0xfe000000
- init_tlb_entries $itlb 0d32
- set $dtlb=0xfe000800
- init_tlb_entries $dtlb 0d32
-end
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-end
-
-# Setup all
-define setup
- use_mon_code
- set *(unsigned int)0xfffffffc=0x60
- shell sleep 0.1
- clock_init
- shell sleep 0.1
- # SDRAM: 16MB
- set *(unsigned long *)0x00ef6020 = 0x08000002
- cfc_init
- # USB
- set *(unsigned short *)0xb0301000 = 0x100
-
- set $evb=0x08000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x08001000
- # INITRD_START
-# set *(unsigned long *)($param + 0x0010) = 0x08300000
- # INITRD_SIZE
-# set *(unsigned long *)($param + 0x0014) = 0x00000000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d200000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d50000000
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=16M \0"
-end
-
-# Boot
-define boot
- set_kernel_parameters
- set $fp = 0
- set $pc = 0x08002000
-# set *(unsigned char *)0xffffffff = 0x03
- si
- c
-end
-
-# Set breakpoints
-define set_breakpoints
- b *0x08000030
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- set $pc = 0
- b *0x04001000
- b *0x08001000
- b *0x08002000
- si
- c
- tlb_init
- del
- setup
- load_modules
- boot
-end
-
-define si
- stepi
- x/i $pc
- show_reg
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-set $pc = 0
-b *0x04001000
-b *0x08001000
-b *0x08002000
-c
-tlb_init
-del
-setup
-load_modules
-boot
-
diff --git a/arch/m32r/platforms/m32700ut/dot.gdbinit_300MHz_32MB b/arch/m32r/platforms/m32700ut/dot.gdbinit_300MHz_32MB
deleted file mode 100644
index aa503657a49b..000000000000
--- a/arch/m32r/platforms/m32700ut/dot.gdbinit_300MHz_32MB
+++ /dev/null
@@ -1,249 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit_300MHz_32MB,v 1.2 2004/10/20 03:02:27 fujiwara Exp $
-#-----
-# NOTE: this file is generated by a script, "gen_gdbinit.pl".
-# (Please type "gen_gdbinit.pl --help" and check the help message).
-# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
-#-----
-# target platform: m32700ut
-
-# setting
-set width 0d70
-set radix 0d16
-
-debug_chaos
-
-# clk xin:cpu:bif:bus=25:300:75:75
-define clock_init
- set *(unsigned long *)0x00ef4008 = 0x00000000
- set *(unsigned long *)0x00ef4004 = 0
- shell sleep 0.1
- # NOTE: Please change the master clock source from PLL-clock to Xin-clock
- # and switch off PLL, before resetting the clock gear ratio.
-
- set *(unsigned long *)0x00ef4024 = 2
- set *(unsigned long *)0x00ef4020 = 2
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 5
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x00000200
-end
-
-# Initialize SDRAM controller
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008 = 0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c = 0x00000001
- # Initialize wait
- shell sleep 0.1
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c = 0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028 = 0x00051502
- # Ch0-ADR (size:32MB)
- set *(unsigned long *)0x00ef6020 = 0x08000003
- # AutoRef On
- set *(unsigned long *)0x00ef6004 = 0x00010e24
- # Access enable
- set *(unsigned long *)0x00ef6024 = 0x00000001
-end
-document sdram_init
- SDRAM controller initialization
- 0x08000000 - 0x09ffffff (32MB)
-end
-
-# Initialize BSEL3 for UT-CFC
-define cfc_init
- set $sfrbase = 0xa0ef0000
-# too fast
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
-end
-document cfc_init
- CF controller initialization
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb 0d32
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb 0d32
-end
-
-# Initialize TLB entries
-define init_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set *(unsigned long *)($addr + 0x4) = 0
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define tlb_init
- set $itlb=0xfe000000
- init_tlb_entries $itlb 0d32
- set $dtlb=0xfe000800
- init_tlb_entries $dtlb 0d32
-end
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-end
-
-# Setup all
-define setup
- use_mon_code
- set *(unsigned int)0xfffffffc=0x60
- shell sleep 0.1
- clock_init
- shell sleep 0.1
- # SDRAM: 32MB
- set *(unsigned long *)0x00ef6020 = 0x08000003
- cfc_init
- # USB
- set *(unsigned short *)0xb0301000 = 0x100
-
- set $evb=0x08000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x08001000
- # INITRD_START
-# set *(unsigned long *)($param + 0x0010) = 0x08300000
- # INITRD_SIZE
-# set *(unsigned long *)($param + 0x0014) = 0x00000000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d300000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d75000000
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=32M \0"
-end
-
-# Boot
-define boot
- set_kernel_parameters
- set $fp = 0
- set $pc = 0x08002000
-# set *(unsigned char *)0xffffffff = 0x03
- si
- c
-end
-
-# Set breakpoints
-define set_breakpoints
- b *0x08000030
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- set $pc = 0
- b *0x04001000
- b *0x08001000
- b *0x08002000
- si
- c
- tlb_init
- del
- setup
- load_modules
- boot
-end
-
-define si
- stepi
- x/i $pc
- show_reg
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-set $pc = 0
-b *0x04001000
-b *0x08001000
-b *0x08002000
-c
-tlb_init
-del
-setup
-load_modules
-boot
-
diff --git a/arch/m32r/platforms/m32700ut/dot.gdbinit_400MHz_32MB b/arch/m32r/platforms/m32700ut/dot.gdbinit_400MHz_32MB
deleted file mode 100644
index adc608aab2fe..000000000000
--- a/arch/m32r/platforms/m32700ut/dot.gdbinit_400MHz_32MB
+++ /dev/null
@@ -1,249 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit_400MHz_32MB,v 1.1 2004/10/21 01:41:27 fujiwara Exp $
-#-----
-# NOTE: this file is generated by a script, "gen_gdbinit.pl".
-# (Please type "gen_gdbinit.pl --help" and check the help message).
-# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
-#-----
-# target platform: m32700ut
-
-# setting
-set width 0d70
-set radix 0d16
-
-debug_chaos
-
-# clk xin:cpu:bif:bus=25:400:100:50
-define clock_init
- set *(unsigned long *)0x00ef4008 = 0x00000000
- set *(unsigned long *)0x00ef4004 = 0
- shell sleep 0.1
- # NOTE: Please change the master clock source from PLL-clock to Xin-clock
- # and switch off PLL, before resetting the clock gear ratio.
-
- set *(unsigned long *)0x00ef4024 = 3
- set *(unsigned long *)0x00ef4020 = 2
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 7
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x00000200
-end
-
-# Initialize SDRAM controller
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008 = 0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c = 0x00000001
- # Initialize wait
- shell sleep 0.1
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c = 0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028 = 0x00041302
- # Ch0-ADR (size:32MB)
- set *(unsigned long *)0x00ef6020 = 0x08000003
- # AutoRef On
- set *(unsigned long *)0x00ef6004 = 0x00010517
- # Access enable
- set *(unsigned long *)0x00ef6024 = 0x00000001
-end
-document sdram_init
- SDRAM controller initialization
- 0x08000000 - 0x09ffffff (32MB)
-end
-
-# Initialize BSEL3 for UT-CFC
-define cfc_init
- set $sfrbase = 0xa0ef0000
-# too fast
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x0b0b8000
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x00102204
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f8000
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x1f1f1fdf
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013220f
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x0013330f
-end
-document cfc_init
- CF controller initialization
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb 0d32
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb 0d32
-end
-
-# Initialize TLB entries
-define init_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set *(unsigned long *)($addr + 0x4) = 0
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define tlb_init
- set $itlb=0xfe000000
- init_tlb_entries $itlb 0d32
- set $dtlb=0xfe000800
- init_tlb_entries $dtlb 0d32
-end
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-end
-
-# Setup all
-define setup
- use_mon_code
- set *(unsigned int)0xfffffffc=0x60
- shell sleep 0.1
- clock_init
- shell sleep 0.1
- # SDRAM: 32MB
- set *(unsigned long *)0x00ef6020 = 0x08000003
- cfc_init
- # USB
- set *(unsigned short *)0xb0301000 = 0x100
-
- set $evb=0x08000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x08001000
- # INITRD_START
-# set *(unsigned long *)($param + 0x0010) = 0x08300000
- # INITRD_SIZE
-# set *(unsigned long *)($param + 0x0014) = 0x00000000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d400000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d50000000
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs,rsize=1024,wsize=1024 nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 mem=32M \0"
-end
-
-# Boot
-define boot
- set_kernel_parameters
- set $fp = 0
- set $pc = 0x08002000
-# set *(unsigned char *)0xffffffff = 0x03
- si
- c
-end
-
-# Set breakpoints
-define set_breakpoints
- b *0x08000030
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- set $pc = 0
- b *0x04001000
- b *0x08001000
- b *0x08002000
- si
- c
- tlb_init
- del
- setup
- load_modules
- boot
-end
-
-define si
- stepi
- x/i $pc
- show_reg
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-set $pc = 0
-b *0x04001000
-b *0x08001000
-b *0x08002000
-c
-tlb_init
-del
-setup
-load_modules
-boot
-
diff --git a/arch/m32r/platforms/m32700ut/io.c b/arch/m32r/platforms/m32700ut/io.c
deleted file mode 100644
index 6862586e58db..000000000000
--- a/arch/m32r/platforms/m32700ut/io.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * linux/arch/m32r/platforms/m32700ut/io.c
- *
- * Typical I/O routines for M32700UT board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of this
- * archive for more details.
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
-#include <linux/types.h>
-
-#define M32R_PCC_IOMAP_SIZE 0x1000
-
-#define M32R_PCC_IOSTART0 0x1000
-#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
-
-extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
-#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
-
-#define PORT2ADDR(port) _port2addr(port)
-#define PORT2ADDR_USB(port) _port2addr_usb(port)
-
-static inline void *_port2addr(unsigned long port)
-{
- return (void *)(port | NONCACHE_OFFSET);
-}
-
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
-static inline void *__port2addr_ata(unsigned long port)
-{
- static int dummy_reg;
-
- switch (port) {
- case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
- case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
- case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
- case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
- case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
- case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
- case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
- case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
- case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
- default: return (void *)&dummy_reg;
- }
-}
-#endif
-
-/*
- * M32700UT-LAN is located in the extended bus space
- * from 0x10000000 to 0x13ffffff on physical address.
- * The base address of LAN controller(LAN91C111) is 0x300.
- */
-#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
-#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)(port + 0x10000000);
-}
-static inline void *_port2addr_usb(unsigned long port)
-{
- return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
-}
-
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-/*
- * NIC I/O function
- */
-
-#define PORT2ADDR_NE(port) _port2addr_ne(port)
-
-static inline unsigned char _ne_inb(void *portp)
-{
- return *(volatile unsigned char *)portp;
-}
-
-static inline unsigned short _ne_inw(void *portp)
-{
- return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
-}
-
-static inline void _ne_insb(void *portp, void *addr, unsigned long count)
-{
- unsigned char *buf = (unsigned char *)addr;
-
- while (count--)
- *buf++ = _ne_inb(portp);
-}
-
-static inline void _ne_outb(unsigned char b, void *portp)
-{
- *(volatile unsigned char *)portp = b;
-}
-
-static inline void _ne_outw(unsigned short w, void *portp)
-{
- *(volatile unsigned short *)portp = cpu_to_le16(w);
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inb(PORT2ADDR_NE(port));
-
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- return *(volatile unsigned char *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned char b;
- pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
- return b;
- } else
-#endif
-
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inw(PORT2ADDR_NE(port));
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- return *(volatile unsigned short *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_USB)
- else if(port >= 0x340 && port < 0x3a0)
- return *(volatile unsigned short *)PORT2ADDR_USB(port);
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned short w;
- pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
- return w;
- } else
-#endif
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned long l;
- pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
- return l;
- } else
-#endif
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return (v);
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return (v);
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return (v);
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outb(b, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- *(volatile unsigned char *)__port2addr_ata(port) = b;
- } else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
- } else
-#endif
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outw(w, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- *(volatile unsigned short *)__port2addr_ata(port) = w;
- } else
-#endif
-#if defined(CONFIG_USB)
- if(port >= 0x340 && port < 0x3a0)
- *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
- else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
- } else
-#endif
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
- } else
-#endif
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void *addr, unsigned long count)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_insb(PORT2ADDR_NE(port), addr, count);
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- unsigned char *buf = addr;
- unsigned char *portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
- }
-#endif
- else {
- unsigned char *buf = addr;
- unsigned char *portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void *addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- /*
- * This portion is only used by smc91111.c to read data
- * from the DATA_REG. Do not swap the data.
- */
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void *addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outb(*buf++, portp);
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- /*
- * This portion is only used by smc91111.c to write data
- * into the DATA_REG. Do not swap the data.
- */
- portp = PORT2ADDR_NE(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
deleted file mode 100644
index 349eb341752c..000000000000
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * linux/arch/m32r/platforms/m32700ut/setup.c
- *
- * Setup routines for Renesas M32700UT Board
- *
- * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of this
- * archive for more details.
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-/*
- * M32700 Interrupt Control Unit (Level 1)
- */
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
-
-static void disable_m32700ut_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_m32700ut_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_m32700ut(struct irq_data *data)
-{
- disable_m32700ut_irq(data->irq);
-}
-
-static void unmask_m32700ut(struct irq_data *data)
-{
- enable_m32700ut_irq(data->irq);
-}
-
-static void shutdown_m32700ut(struct irq_data *data)
-{
- unsigned long port;
-
- port = irq2port(data->irq);
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip m32700ut_irq_type =
-{
- .name = "M32700UT-IRQ",
- .irq_shutdown = shutdown_m32700ut,
- .irq_mask = mask_m32700ut,
- .irq_unmask = unmask_m32700ut
-};
-
-/*
- * Interrupt Control Unit of PLD on M32700UT (Level 2)
- */
-#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
-#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
- (((x) - 1) * sizeof(unsigned short)))
-
-typedef struct {
- unsigned short icucr; /* ICU Control Register */
-} pld_icu_data_t;
-
-static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
-
-static void disable_m32700ut_pld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(irq);
- port = pldirq2port(pldirq);
- data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
- outw(data, port);
-}
-
-static void enable_m32700ut_pld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(irq);
- port = pldirq2port(pldirq);
- data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
- outw(data, port);
-}
-
-static void mask_m32700ut_pld(struct irq_data *data)
-{
- disable_m32700ut_pld_irq(data->irq);
-}
-
-static void unmask_m32700ut_pld(struct irq_data *data)
-{
- enable_m32700ut_pld_irq(data->irq);
- enable_m32700ut_irq(M32R_IRQ_INT1);
-}
-
-static void shutdown_m32700ut_pld_irq(struct irq_data *data)
-{
- unsigned long port;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(data->irq);
- port = pldirq2port(pldirq);
- outw(PLD_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip m32700ut_pld_irq_type =
-{
- .name = "M32700UT-PLD-IRQ",
- .irq_shutdown = shutdown_m32700ut_pld_irq,
- .irq_mask = mask_m32700ut_pld,
- .irq_unmask = unmask_m32700ut_pld,
-};
-
-/*
- * Interrupt Control Unit of PLD on M32700UT-LAN (Level 2)
- */
-#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
-#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
- (((x) - 1) * sizeof(unsigned short)))
-
-static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
-
-static void disable_m32700ut_lanpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lanpldirq(irq);
- port = lanpldirq2port(pldirq);
- data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
- outw(data, port);
-}
-
-static void enable_m32700ut_lanpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lanpldirq(irq);
- port = lanpldirq2port(pldirq);
- data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
- outw(data, port);
-}
-
-static void mask_m32700ut_lanpld(struct irq_data *data)
-{
- disable_m32700ut_lanpld_irq(data->irq);
-}
-
-static void unmask_m32700ut_lanpld(struct irq_data *data)
-{
- enable_m32700ut_lanpld_irq(data->irq);
- enable_m32700ut_irq(M32R_IRQ_INT0);
-}
-
-static void shutdown_m32700ut_lanpld(struct irq_data *data)
-{
- unsigned long port;
- unsigned int pldirq;
-
- pldirq = irq2lanpldirq(data->irq);
- port = lanpldirq2port(pldirq);
- outw(PLD_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip m32700ut_lanpld_irq_type =
-{
- .name = "M32700UT-PLD-LAN-IRQ",
- .irq_shutdown = shutdown_m32700ut_lanpld,
- .irq_mask = mask_m32700ut_lanpld,
- .irq_unmask = unmask_m32700ut_lanpld,
-};
-
-/*
- * Interrupt Control Unit of PLD on M32700UT-LCD (Level 2)
- */
-#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
-#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
- (((x) - 1) * sizeof(unsigned short)))
-
-#ifdef CONFIG_USB
-static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
-
-static void disable_m32700ut_lcdpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lcdpldirq(irq);
- port = lcdpldirq2port(pldirq);
- data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
- outw(data, port);
-}
-
-static void enable_m32700ut_lcdpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lcdpldirq(irq);
- port = lcdpldirq2port(pldirq);
- data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
- outw(data, port);
-}
-
-static void mask_m32700ut_lcdpld(struct irq_data *data)
-{
- disable_m32700ut_lcdpld_irq(data->irq);
-}
-
-static void unmask_m32700ut_lcdpld(struct irq_data *data)
-{
- enable_m32700ut_lcdpld_irq(data->irq);
- enable_m32700ut_irq(M32R_IRQ_INT2);
-}
-
-static void shutdown_m32700ut_lcdpld(struct irq_data *data)
-{
- unsigned long port;
- unsigned int pldirq;
-
- pldirq = irq2lcdpldirq(data->irq);
- port = lcdpldirq2port(pldirq);
- outw(PLD_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip m32700ut_lcdpld_irq_type =
-{
- .name = "M32700UT-PLD-LCD-IRQ",
- .irq_shutdown = shutdown_m32700ut_lcdpld,
- .irq_mask = mask_m32700ut_lcdpld,
- .irq_unmask = unmask_m32700ut_lcdpld,
-};
-#endif
-
-void __init init_IRQ(void)
-{
-#if defined(CONFIG_SMC91X)
- /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
- irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
- &m32700ut_lanpld_irq_type, handle_level_irq);
- lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
- disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
-#endif /* CONFIG_SMC91X */
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_m32700ut_irq(M32R_IRQ_MFT2);
-
- /* SIO0 : receive */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = 0;
- disable_m32700ut_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0 : send */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = 0;
- disable_m32700ut_irq(M32R_IRQ_SIO0_S);
-
- /* SIO1 : receive */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_R].icucr = 0;
- disable_m32700ut_irq(M32R_IRQ_SIO1_R);
-
- /* SIO1 : send */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_S].icucr = 0;
- disable_m32700ut_irq(M32R_IRQ_SIO1_S);
-
- /* DMA1 : */
- irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_DMA1].icucr = 0;
- disable_m32700ut_irq(M32R_IRQ_DMA1);
-
-#ifdef CONFIG_SERIAL_M32R_PLDSIO
- /* INT#1: SIO0 Receive on PLD */
- irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
- disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
-
- /* INT#1: SIO0 Send on PLD */
- irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
- disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
-#endif /* CONFIG_SERIAL_M32R_PLDSIO */
-
- /* INT#1: CFC IREQ on PLD */
- irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
- disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
-
- /* INT#1: CFC Insert on PLD */
- irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
- disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
-
- /* INT#1: CFC Eject on PLD */
- irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
- disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
-
- /*
- * INT0# is used for LAN, DIO
- * We enable it here.
- */
- icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
- enable_m32700ut_irq(M32R_IRQ_INT0);
-
- /*
- * INT1# is used for UART, MMC, CF Controller in FPGA.
- * We enable it here.
- */
- icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
- enable_m32700ut_irq(M32R_IRQ_INT1);
-
-#if defined(CONFIG_USB)
- outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
- irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
- &m32700ut_lcdpld_irq_type, handle_level_irq);
-
- lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
- disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
-#endif
- /*
- * INT2# is used for BAT, USB, AUDIO
- * We enable it here.
- */
- icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
- enable_m32700ut_irq(M32R_IRQ_INT2);
-
-#if defined(CONFIG_VIDEO_M32R_AR)
- /*
- * INT3# is used for AR
- */
- irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
- disable_m32700ut_irq(M32R_IRQ_INT3);
-#endif /* CONFIG_VIDEO_M32R_AR */
-}
-
-#if defined(CONFIG_SMC91X)
-
-#define LAN_IOSTART 0x300
-#define LAN_IOEND 0x320
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (LAN_IOSTART),
- .end = (LAN_IOEND),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = M32700UT_LAN_IRQ_LAN,
- .end = M32700UT_LAN_IRQ_LAN,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-#endif
-
-#if defined(CONFIG_FB_S1D13XXX)
-
-#include <video/s1d13xxxfb.h>
-#include <asm/s1d13806.h>
-
-static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
- .initregs = s1d13xxxfb_initregs,
- .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
- .platform_init_video = NULL,
-#ifdef CONFIG_PM
- .platform_suspend_video = NULL,
- .platform_resume_video = NULL,
-#endif
-};
-
-static struct resource s1d13xxxfb_resources[] = {
- [0] = {
- .start = 0x10600000UL,
- .end = 0x1073FFFFUL,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x10400000UL,
- .end = 0x104001FFUL,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device s1d13xxxfb_device = {
- .name = S1D_DEVICENAME,
- .id = 0,
- .dev = {
- .platform_data = &s1d13xxxfb_data,
- },
- .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
- .resource = s1d13xxxfb_resources,
-};
-#endif
-
-static int __init platform_init(void)
-{
-#if defined(CONFIG_SMC91X)
- platform_device_register(&smc91x_device);
-#endif
-#if defined(CONFIG_FB_S1D13XXX)
- platform_device_register(&s1d13xxxfb_device);
-#endif
- return 0;
-}
-arch_initcall(platform_init);
diff --git a/arch/m32r/platforms/mappi/Makefile b/arch/m32r/platforms/mappi/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/mappi/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/mappi/dot.gdbinit b/arch/m32r/platforms/mappi/dot.gdbinit
deleted file mode 100644
index 7a1d293863eb..000000000000
--- a/arch/m32r/platforms/mappi/dot.gdbinit
+++ /dev/null
@@ -1,242 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit.mappi,v 1.4 2004/10/20 02:24:37 takata Exp $
-#-----
-# NOTE: this file is generated by a script, "gen_gdbinit.pl".
-# (Please type "gen_gdbinit.pl --help" and check the help message).
-# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
-#-----
-# target platform: mappi
-
-# setting
-set width 0d70
-set radix 0d16
-debug_chaos
-
-# clk xin:cpu:bif:bus=30:360:180:90
-define clock_init
- set *(unsigned long *)0x00ef4024 = 2
- set *(unsigned long *)0x00ef4020 = 1
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 5
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x00000200
-end
-
-# Initialize programmable ports
-define port_init
- set $sfrbase = 0x00ef0000
- set *(unsigned short *)0x00ef1060 = 0x5555
- set *(unsigned short *)0x00ef1062 = 0x5555
- set *(unsigned short *)0x00ef1064 = 0x5555
- set *(unsigned short *)0x00ef1066 = 0x5555
- set *(unsigned short *)0x00ef1068 = 0x5555
- set *(unsigned short *)0x00ef106a = 0x0000
- set *(unsigned short *)0x00ef106e = 0x5555
- set *(unsigned short *)0x00ef1070 = 0x5555
- # LED ON
- set *(unsigned char *)($sfrbase + 0x1015) = 0xff
- set *(unsigned char *)($sfrbase + 0x1085) = 0xff
- shell sleep 0.1
- # LED OFF
- set *(unsigned char *)($sfrbase + 0x1085) = 0x00
-end
-document port_init
- P5=LED(output), P6.b4=LAN_RESET(output)
-end
-
-# Initialize SDRAM controller
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008 = 0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c = 0x00000001
- # Initialize wait
- shell sleep 0.1
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c = 0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028 = 0x00051502
- # Ch0-ADR (size:64MB)
- set *(unsigned long *)0x00ef6020 = 0x08000004
- # AutoRef On
- set *(unsigned long *)0x00ef6004 = 0x00010e2b
- # Access enable
- set *(unsigned long *)0x00ef6024 = 0x00000001
-end
-document sdram_init
- SDRAM controller initialization
- 0x08000000 - 0x0bffffff (64MB)
-end
-
-# Initialize LAN controller
-define lanc_init
- set $sfrbase = 0x00ef0000
- # Set BSEL3 (BSEL3 for the Chaos's bselc)
- set *(unsigned long *)($sfrbase + 0x5300) = 0x0a0a8040
- set *(unsigned long *)($sfrbase + 0x5304) = 0x01120203
- set *(unsigned long *)($sfrbase + 0x5308) = 0x00000001
- # Reset (P5=LED,P6.b4=LAN_RESET)
- set *(unsigned short *)($sfrbase + 0x106c) = 0x0000
- set *(unsigned char *)($sfrbase + 0x1016) = 0xff
- set *(unsigned char *)($sfrbase + 0x1086) = 0xff
- shell sleep 0.1
- # swivel: 0=normal, 4=reverse
-# set *(unsigned char *)($sfrbase + 0x1086) = 0x00
- set *(unsigned char *)($sfrbase + 0x1086) = 0x04
- set *(unsigned long *)(0x0c000330) = 0xffffffff
- # Set mac address
- set $lanc = (void*)0x0c000300
- set *(unsigned long *)($lanc + 0x0000) = 0x00610010
- set *(unsigned long *)($lanc + 0x0004) = 0x00200030
- set *(unsigned long *)($lanc + 0x0008) = 0x00400050
- set *(unsigned long *)($lanc + 0x000c) = 0x00600007
-end
-document lanc_init
- LAN controller initialization
- ex.) MAC address: 10 20 30 40 50 60
-end
-
-# LCD & CRT dual-head setting (8bpp)
-define dispc_init
- set $sfrbase = 0x00ef0000
- # BSEL4 Dispc
- set *(unsigned long *)($sfrbase + 0x5400) = 0x0e0e8000
- set *(unsigned long *)($sfrbase + 0x5404) = 0x0012220a
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb 0d32
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb 0d32
-end
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-end
-
-# Setup all
-define setup
- use_mon_code
- set *(unsigned int)0xfffffffc=0x60
- shell sleep 0.1
- clock_init
- shell sleep 0.1
- port_init
- sdram_init
- lanc_init
- dispc_init
- set $evb=0x08000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x08001000
- # INITRD_START
-# set *(unsigned long *)($param + 0x0010) = 0x08300000
- # INITRD_SIZE
-# set *(unsigned long *)($param + 0x0014) = 0x00000000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d360000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d90000000
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
-end
-
-# Boot
-define boot
- set_kernel_parameters
- set $fp = 0
- set $pc = 0x08002000
- si
- c
-end
-
-# Set breakpoints
-define set_breakpoints
- b *0x08000030
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- setup
- load_modules
- boot
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-setup
-#load_modules
-#set_breakpoints
-#boot
-
diff --git a/arch/m32r/platforms/mappi/dot.gdbinit.nommu b/arch/m32r/platforms/mappi/dot.gdbinit.nommu
deleted file mode 100644
index 297536cf67cf..000000000000
--- a/arch/m32r/platforms/mappi/dot.gdbinit.nommu
+++ /dev/null
@@ -1,245 +0,0 @@
-# .gdbinit file
-# $Id$
-#-----
-# NOTE: this file is generated by a script, "gen_gdbinit.pl".
-# (Please type "gen_gdbinit.pl --help" and check the help message).
-# $ Id: gen_gdbinit.pl,v 1.5 2004/01/23 08:23:25 takata Exp $
-#-----
-# target platform: mappi
-
-# setting
-set width 0d70
-set radix 0d16
-debug_chaos
-
-# clk xin:cpu:bif:bus=25:200:50:50
-define clock_init
- set *(unsigned long *)0x00ef4024 = 2
- set *(unsigned long *)0x00ef4020 = 2
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 3
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x00000200
-end
-
-# Initialize programmable ports
-define port_init
- set $sfrbase = 0x00ef0000
- set *(unsigned short *)0x00ef1060 = 0x5555
- set *(unsigned short *)0x00ef1062 = 0x5555
- set *(unsigned short *)0x00ef1064 = 0x5555
- set *(unsigned short *)0x00ef1066 = 0x5555
- set *(unsigned short *)0x00ef1068 = 0x5555
- set *(unsigned short *)0x00ef106a = 0x0000
- set *(unsigned short *)0x00ef106e = 0x5555
- set *(unsigned short *)0x00ef1070 = 0x5555
- # LED ON
- set *(unsigned char *)($sfrbase + 0x1015) = 0xff
- set *(unsigned char *)($sfrbase + 0x1085) = 0xff
- shell sleep 0.1
- # LED OFF
- set *(unsigned char *)($sfrbase + 0x1085) = 0x00
-end
-document port_init
- P5=LED(output), P6.b4=LAN_RESET(output)
-end
-
-# Initialize SDRAM controller
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008 = 0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c = 0x00000001
- # Initialize wait
- shell sleep 0.1
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c = 0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028 = 0x00051502
- # Ch0-ADR (size:64MB)
- set *(unsigned long *)0x00ef6020 = 0x00000004
- # AutoRef On
- set *(unsigned long *)0x00ef6004 = 0x00010f05
- # Access enable
- set *(unsigned long *)0x00ef6024 = 0x00000001
-end
-document sdram_init
- SDRAM controller initialization
- 0x08000000 - 0x0bffffff (64MB)
-end
-
-# Initialize LAN controller
-define lanc_init
- set $sfrbase = 0x00ef0000
- # Set BSEL3 (BSEL3 for the Chaos's bselc)
- set *(unsigned long *)($sfrbase + 0x5300) = 0x07078040
- set *(unsigned long *)($sfrbase + 0x5304) = 0x01110102
- set *(unsigned long *)($sfrbase + 0x5308) = 0x00000001
- # Reset (P5=LED,P6.b4=LAN_RESET)
- set *(unsigned short *)($sfrbase + 0x106c) = 0x0000
- set *(unsigned char *)($sfrbase + 0x1016) = 0xff
- set *(unsigned char *)($sfrbase + 0x1086) = 0xff
- shell sleep 0.1
- # swivel: 0=normal, 4=reverse
-# set *(unsigned char *)($sfrbase + 0x1086) = 0x00
- set *(unsigned char *)($sfrbase + 0x1086) = 0x04
- set *(unsigned long *)(0x0c000330) = 0xffffffff
- # Set mac address
- set $lanc = (void*)0x0c000300
- set *(unsigned long *)($lanc + 0x0000) = 0x00610010
- set *(unsigned long *)($lanc + 0x0004) = 0x00200030
- set *(unsigned long *)($lanc + 0x0008) = 0x00400050
- set *(unsigned long *)($lanc + 0x000c) = 0x00600007
-end
-document lanc_init
- LAN controller initialization
- ex.) MAC address: 10 20 30 40 50 60
-end
-
-# LCD & CRT dual-head setting (8bpp)
-define dispc_init
- set $sfrbase = 0x00ef0000
- # BSEL4 Dispc
- set *(unsigned long *)($sfrbase + 0x5400) = 0x06078000
- set *(unsigned long *)($sfrbase + 0x5404) = 0x00101101
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- set $nr_entries = $arg1
- use_mon_code
- while ($i < $nr_entries)
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb 0d32
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb 0d32
-end
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-end
-
-# Setup all
-define setup
- use_mon_code
- set *(unsigned int)0xfffffffc=0x60
- shell sleep 0.1
- clock_init
- shell sleep 0.1
- port_init
- sdram_init
- lanc_init
- dispc_init
- set $evb=0x00000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x00001000
- # INITRD_START
- #set *(unsigned long *)($param + 0x0010) = 0x082a0000
- # INITRD_SIZE
- #set *(unsigned long *)($param + 0x0014) = 0x00000000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d200000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d50000000
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.bbox-httpd nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
-end
-
-# Boot
-define boot
- set_kernel_parameters
- set $fp = 0
- set $pc=0x00002000
- set *(long *)0xfffffff4=0x8080
-# b load_flat_binary
-# set *(unsigned char *)0x08001003=0x63
-# set *(unsigned char *)0x08001003=0x02
- si
-# c
-end
-
-# Set breakpoints
-define set_breakpoints
- b *0x08000030
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- setup
- load_modules
- boot
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-setup
-load_modules
-boot
-
diff --git a/arch/m32r/platforms/mappi/dot.gdbinit.smp b/arch/m32r/platforms/mappi/dot.gdbinit.smp
deleted file mode 100644
index 171489a440d9..000000000000
--- a/arch/m32r/platforms/mappi/dot.gdbinit.smp
+++ /dev/null
@@ -1,344 +0,0 @@
-# .gdbinit file
-# $Id$
-
-# setting
-set width 0d70
-set radix 0d16
-debug_chaos
-
-# clk xin:cpu:bif:bus=1:4:2:1
-define clock_init_on
- set *(unsigned long *)0x00ef4024 = 2
- set *(unsigned long *)0x00ef4020 = 1
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 0x1
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x0200
-# set *(unsigned long *)0x00ef4008 = 0x0201
-end
-
-# clk xin:cpu:bif:bus=1:4:1:1
-define clock_init_on_1411
- set *(unsigned long *)0x00ef4024 = 2
- set *(unsigned long *)0x00ef4020 = 2
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 0x1
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x0200
-end
-
-# clk xin:cpu:bif:bus=1:4:2:1
-define clock_init_on_1421
- set *(unsigned long *)0x00ef4024 = 2
- set *(unsigned long *)0x00ef4020 = 1
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 0x1
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x0200
-end
-
-# clk xin:cpu:bif:bus=1:8:2:1
-define clock_init_on_1821
- set *(unsigned long *)0x00ef4024 = 3
- set *(unsigned long *)0x00ef4020 = 2
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 0x3
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x0200
-end
-
-# clk xin:cpu:bif:bus=1:8:4:1
-define clock_init_on_1841
- set *(unsigned long *)0x00ef4024 = 3
- set *(unsigned long *)0x00ef4020 = 1
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 0x3
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x0200
-end
-
-# clk xin:cpu:bif:bus=1:16:8:1
-define clock_init_on_11681
- set *(unsigned long *)0x00ef4024 = 4
- set *(unsigned long *)0x00ef4020 = 2
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- set *(unsigned long *)0x00ef4004 = 0x7
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x0200
-end
-
-# clk xin:cpu:bif:bus=1:1:1:1
-define clock_init_off
- # CPU
- set *(unsigned long *)0x00ef4010 = 0
- set *(unsigned long *)0x00ef4014 = 0
- # BIF
- set *(unsigned long *)0x00ef4020 = 0
- # BUS
- set *(unsigned long *)0x00ef4024 = 0
- # PLL
- set *(unsigned long *)0x00ef4008 = 0x0000
-end
-
-# Initialize programmable ports
-define port_init
- set $sfrbase = 0x00ef0000
- set *(unsigned short *)0x00ef1060 = 0x5555
- set *(unsigned short *)0x00ef1062 = 0x5555
- set *(unsigned short *)0x00ef1064 = 0x5555
- set *(unsigned short *)0x00ef1066 = 0x5555
- set *(unsigned short *)0x00ef1068 = 0x5555
- set *(unsigned short *)0x00ef106a = 0x0000
- set *(unsigned short *)0x00ef106e = 0x5555
- set *(unsigned short *)0x00ef1070 = 0x5555
- # LED ON
- set *(unsigned char *)($sfrbase + 0x1015) = 0xff
- set *(unsigned char *)($sfrbase + 0x1085) = 0xff
- shell sleep 0.1
- # LED OFF
- set *(unsigned char *)($sfrbase + 0x1085) = 0x00
-end
-document port_init
- P5=LED(output), P6.b4=LAN_RESET(output)
-end
-
-# Initialize SDRAM controller for Mappi
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008 = 0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c = 0x00000001
- # Initialize wait
- shell sleep 0.1
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c = 0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028 = 0x00010002
- # Ch0-ADR
- set *(unsigned long *)0x00ef6020 = 0x08000004
- # AutoRef On
- set *(unsigned long *)0x00ef6004 = 0x00010107
- # Access enable
- set *(unsigned long *)0x00ef6024 = 0x00000001
-end
-document sdram_init
- Mappi SDRAM controller initialization
- 0x08000000 - 0x0bffffff (64MB)
-end
-
-# Initialize LAN controller for Mappi
-define lanc_init
- set $sfrbase = 0x00ef0000
- # Set BSEL3 (BSEL3 for the Chaos's bselc)
-# set *(unsigned long *)($sfrbase + 0x5300) = 0x01018040
-# set *(unsigned long *)($sfrbase + 0x5304) = 0x01011101
- set *(unsigned long *)($sfrbase + 0x5300) = 0x04048000
- set *(unsigned long *)($sfrbase + 0x5304) = 0x01011103
- set *(unsigned long *)($sfrbase + 0x5308) = 0x00000001
- # Reset (P5=LED,P6.b4=LAN_RESET)
- set *(unsigned short *)($sfrbase + 0x106c) = 0x0000
- set *(unsigned char *)($sfrbase + 0x1016) = 0xff
- set *(unsigned char *)($sfrbase + 0x1086) = 0xff
- shell sleep 0.1
-# set *(unsigned char *)($sfrbase + 0x1086) = 0x00
- set *(unsigned char *)($sfrbase + 0x1086) = 0x04
- set *(unsigned long *)(0x0c000330) = 0xffffffff
- # Set mac address
- set $lanc = (void*)0x0c000300
- set *(unsigned long *)($lanc + 0x0000) = 0x00610010
- set *(unsigned long *)($lanc + 0x0004) = 0x00200030
- set *(unsigned long *)($lanc + 0x0008) = 0x00400050
- set *(unsigned long *)($lanc + 0x000c) = 0x00600007
-end
-document lanc_init
- Mappi LAN controller initialization
- ex.) MAC address: 10 20 30 40 50 60
-end
-
-# LCD & CRT dual-head setting (8bpp)
-define dispc_init
- set $sfrbase = 0x00ef0000
- # BSEL4 Dispc
- # 20MHz
-# set *(unsigned long *)($sfrbase + 0x5400) = 0x02028282
-# set *(unsigned long *)($sfrbase + 0x5404) = 0x00122202
- # 40MHz
- set *(unsigned long *)($sfrbase + 0x5400) = 0x04048000
- set *(unsigned long *)($sfrbase + 0x5404) = 0x00101103
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- use_mon_code
- while ($i < 0d32 )
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
- use_debug_dma
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb
-end
-
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set $task = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$fp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-end
-
-
-# Setup all
-define setup
- use_mon_code
- set *(unsigned int)0xfffffffc=0x60
- shell sleep 0.1
-# clock_init_on_1411
- clock_init_on_1421
-# clock_init_on_1821
-# clock_init_on_1841
-# clock_init_on_11681
-# clock_init_off
- shell sleep 0.1
- port_init
- sdram_init
- lanc_init
- dispc_init
- set $evb=0x08000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-# load ramdisk_082a0000.mot
-# load romfs_082a0000.mot
-# use_mon_code
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x08001000
- # INITRD_START
-# set *(unsigned long *)($param + 0x0010) = 0x082a0000
- # INITRD_SIZE
-# set *(unsigned long *)($param + 0x0014) = 0x00000000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d160000000
-# set *(unsigned long *)($param + 0x0018) = 0d80000000
-# set *(unsigned long *)($param + 0x0018) = 0d40000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d40000000
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=tty1 console=ttyS0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.x nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
-# set {char[0x200]}($param + 0x100) = "console=tty1 root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.x nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
-end
-
-# Boot
-define boot
- set_kernel_parameters
- set $pc=0x08002000
- set *(unsigned char *)0x08001003=0x03
- si
- c
-end
-
-# Set breakpoints
-define set_breakpoints
- b *0x08000030
-end
-
-## Boot MP
-define boot_mp
- set_kernel_parameters
- set *(unsigned long *)0x00f00000 = boot - 0x80000000
- set *(unsigned long *)0x00eff2f8 = 0x2
- x 0x00eff2f8
-
- set $pc=0x08002000
- si
- c
-end
-document boot_mp
- Boot BSP
-end
-
-## Boot UP
-define boot_up
- set_kernel_parameters
- set $pc=0x08002000
- si
- c
-end
-document boot_up
- Boot BSP
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- setup
- load_modules
- boot_mp
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-setup
diff --git a/arch/m32r/platforms/mappi/io.c b/arch/m32r/platforms/mappi/io.c
deleted file mode 100644
index 06ea6d9bc576..000000000000
--- a/arch/m32r/platforms/mappi/io.c
+++ /dev/null
@@ -1,326 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/mappi/io.c
- *
- * Typical I/O routines for Mappi board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
-#include <linux/types.h>
-
-#define M32R_PCC_IOMAP_SIZE 0x1000
-
-#define M32R_PCC_IOSTART0 0x1000
-#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
-#define M32R_PCC_IOSTART1 0x2000
-#define M32R_PCC_IOEND1 (M32R_PCC_IOSTART1 + M32R_PCC_IOMAP_SIZE - 1)
-
-extern void pcc_ioread(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite(int, unsigned long, void *, size_t, size_t, int);
-#endif /* CONFIG_PCMCIA && CONFIG_M32R_PCC */
-
-#define PORT2ADDR(port) _port2addr(port)
-
-static inline void *_port2addr(unsigned long port)
-{
- return (void *)(port | NONCACHE_OFFSET);
-}
-
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)((port<<1) + NONCACHE_OFFSET + 0x0C000000);
-}
-
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-/*
- * NIC I/O function
- */
-
-#define PORT2ADDR_NE(port) _port2addr_ne(port)
-
-static inline unsigned char _ne_inb(void *portp)
-{
- return (unsigned char) *(volatile unsigned short *)portp;
-}
-
-static inline unsigned short _ne_inw(void *portp)
-{
- unsigned short tmp;
-
- tmp = *(volatile unsigned short *)portp;
- return le16_to_cpu(tmp);
-}
-
-static inline void _ne_outb(unsigned char b, void *portp)
-{
- *(volatile unsigned short *)portp = (unsigned short)b;
-}
-
-static inline void _ne_outw(unsigned short w, void *portp)
-{
- *(volatile unsigned short *)portp = cpu_to_le16(w);
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- return _ne_inb(PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned char b;
- pcc_ioread(0, port, &b, sizeof(b), 1, 0);
- return b;
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- unsigned char b;
- pcc_ioread(1, port, &b, sizeof(b), 1, 0);
- return b;
- } else
-#endif
-
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- return _ne_inw(PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned short w;
- pcc_ioread(0, port, &w, sizeof(w), 1, 0);
- return w;
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- unsigned short w;
- pcc_ioread(1, port, &w, sizeof(w), 1, 0);
- return w;
- } else
-#endif
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned long l;
- pcc_ioread(0, port, &l, sizeof(l), 1, 0);
- return l;
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- unsigned short l;
- pcc_ioread(1, port, &l, sizeof(l), 1, 0);
- return l;
- } else
-#endif
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return (v);
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return (v);
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return (v);
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- _ne_outb(b, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite(0, port, &b, sizeof(b), 1, 0);
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- pcc_iowrite(1, port, &b, sizeof(b), 1, 0);
- } else
-#endif
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- _ne_outw(w, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite(0, port, &w, sizeof(w), 1, 0);
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- pcc_iowrite(1, port, &w, sizeof(w), 1, 0);
- } else
-#endif
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite(0, port, &l, sizeof(l), 1, 0);
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- pcc_iowrite(1, port, &l, sizeof(l), 1, 0);
- } else
-#endif
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void *addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= 0x300 && port < 0x320){
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- pcc_ioread(1, port, (void *)addr, sizeof(unsigned char),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void *addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= 0x300 && port < 0x320) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = _ne_inw(portp);
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread(0, port, (void *)addr, sizeof(unsigned short),
- count, 1);
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- pcc_ioread(1, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void *addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= 0x300 && port < 0x320) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outb(*buf++, portp);
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- pcc_iowrite(1, port, (void *)addr, sizeof(unsigned char),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= 0x300 && port < 0x320) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outw(*buf++, portp);
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_PCC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite(0, port, (void *)addr, sizeof(unsigned short),
- count, 1);
- } else if (port >= M32R_PCC_IOSTART1 && port <= M32R_PCC_IOEND1) {
- pcc_iowrite(1, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
deleted file mode 100644
index c8d642ec4bfb..000000000000
--- a/arch/m32r/platforms/mappi/setup.c
+++ /dev/null
@@ -1,175 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/mappi/setup.c
- *
- * Setup routines for Renesas MAPPI Board
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[NR_IRQS];
-
-static void disable_mappi_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_mappi_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_mappi(struct irq_data *data)
-{
- disable_mappi_irq(data->irq);
-}
-
-static void unmask_mappi(struct irq_data *data)
-{
- enable_mappi_irq(data->irq);
-}
-
-static void shutdown_mappi(struct irq_data *data)
-{
- unsigned long port;
-
- port = irq2port(data->irq);
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip mappi_irq_type =
-{
- .name = "MAPPI-IRQ",
- .irq_shutdown = shutdown_mappi,
- .irq_mask = mask_mappi,
- .irq_unmask = unmask_mappi,
-};
-
-void __init init_IRQ(void)
-{
- static int once = 0;
-
- if (once)
- return;
- else
- once++;
-
-#ifdef CONFIG_NE2000
- /* INT0 : LAN controller (RTL8019AS) */
- irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
- disable_mappi_irq(M32R_IRQ_INT0);
-#endif /* CONFIG_M32R_NE2000 */
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_mappi_irq(M32R_IRQ_MFT2);
-
-#ifdef CONFIG_SERIAL_M32R_SIO
- /* SIO0_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO0_S);
-
- /* SIO1_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_R].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO1_R);
-
- /* SIO1_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_S].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO1_S);
-#endif /* CONFIG_SERIAL_M32R_SIO */
-
-#if defined(CONFIG_M32R_PCC)
- /* INT1 : pccard0 interrupt */
- irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
- disable_mappi_irq(M32R_IRQ_INT1);
-
- /* INT2 : pccard1 interrupt */
- irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
- disable_mappi_irq(M32R_IRQ_INT2);
-#endif /* CONFIG_M32RPCC */
-}
-
-#if defined(CONFIG_FB_S1D13XXX)
-
-#include <video/s1d13xxxfb.h>
-#include <asm/s1d13806.h>
-
-static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
- .initregs = s1d13xxxfb_initregs,
- .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
- .platform_init_video = NULL,
-#ifdef CONFIG_PM
- .platform_suspend_video = NULL,
- .platform_resume_video = NULL,
-#endif
-};
-
-static struct resource s1d13xxxfb_resources[] = {
- [0] = {
- .start = 0x10200000UL,
- .end = 0x1033FFFFUL,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x10000000UL,
- .end = 0x100001FFUL,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device s1d13xxxfb_device = {
- .name = S1D_DEVICENAME,
- .id = 0,
- .dev = {
- .platform_data = &s1d13xxxfb_data,
- },
- .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
- .resource = s1d13xxxfb_resources,
-};
-
-static int __init platform_init(void)
-{
- platform_device_register(&s1d13xxxfb_device);
- return 0;
-}
-arch_initcall(platform_init);
-#endif
diff --git a/arch/m32r/platforms/mappi2/Makefile b/arch/m32r/platforms/mappi2/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/mappi2/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/mappi2/dot.gdbinit.vdec2 b/arch/m32r/platforms/mappi2/dot.gdbinit.vdec2
deleted file mode 100644
index 797a830bd4b7..000000000000
--- a/arch/m32r/platforms/mappi2/dot.gdbinit.vdec2
+++ /dev/null
@@ -1,233 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit.vdec2,v 1.2 2004/11/11 02:03:15 takata Exp $
-
-# setting
-set width 0d70
-set radix 0d16
-use_debug_dma
-
-# Initialize SDRAM controller for Mappi
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008=0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c=0x00000001
- # Initialize wait
- shell sleep 1
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c=0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028=0x00041302
- # Ch0-ADR
- set *(unsigned long *)0x00ef6020=0x08000004
- # AutoRef On
- set *(unsigned long *)0x00ef6004=0x00010705
- # Access enable
- set *(unsigned long *)0x00ef6024=0x00000001
-end
-document sdram_init
- Mappi SDRAM controller initialization
- 0x08000000 - 0x0bffffff (64MB)
-end
-
-# Initialize SDRAM controller for Mappi
-define sdram_init2
- # SDIR0
- set *(unsigned long *)0x00ef6008=0x00000182
- # Ch0-MOD
- set *(unsigned long *)0x00ef602c=0x00000020
- # Ch0-TR
- set *(unsigned long *)0x00ef6028=0x00010002
- # Ch0-ADR
- set *(unsigned long *)0x00ef6020=0x08000004
- # AutoRef On
- set *(unsigned long *)0x00ef6004=0x00010107
- # SDIR1
- set *(unsigned long *)0x00ef600c=0x00000001
- # Initialize wait
- shell sleep 1
- # Access enable
- set *(unsigned long *)0x00ef6024=0x00000001
- shell sleep 1
-end
-document sdram_init
- Mappi SDRAM controller initialization
- 0x08000000 - 0x0bffffff (64MB)
-end
-
-# Initialize LAN controller for Mappi
-define lanc_init
- # Set BSEL1 (BSEL3 for the Chaos's bselc)
- #set *(unsigned long *)0x00ef5004 = 0x0fff330f
- #set *(unsigned long *)0x00ef5004 = 0x01113301
-
-# set *(unsigned long *)0x00ef5004 = 0x02011101
-# set *(unsigned long *)0x00ef5004 = 0x04441104
-
- # BSEL5
-# set *(unsigned long *)0x00ef5014 = 0x0ccc310c
-# set *(unsigned long *)0x00ef5014 = 0x0303310f
-# set *(unsigned long *)0x00ef5014 = 0x01011102 -> NG
-# set *(unsigned long *)0x00ef5014 = 0x03033103
-
- set *(unsigned long *)0x00ef500c = 0x0b0b1304
- set *(unsigned long *)0x00ef5010 = 0x03033302
-# set *(unsigned long *)0x00ef5018 = 0x02223302
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- while ($i < 0d16 )
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb
-end
-
-# Cache ON
-define set_cache_type
- set $mctype = (void*)0xfffffff8
-# chaos
-# set *(unsigned long *)($mctype) = 0x0000c000
-# m32102 i-cache only
- set *(unsigned long *)($mctype) = 0x00008000
-# m32102 d-cache only
-# set *(unsigned long *)($mctype) = 0x00004000
-end
-define cache_on
- set $param = (void*)0x08001000
- set *(unsigned long *)($param) = 0x60ff6102
-end
-
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set $task = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-
- set $mests = *(unsigned long *)0xffff000c
- set $mdeva = *(unsigned long *)0xffff0010
- printf "MESTS[0x%08lX] MDEVA[0x%08lX]\n",$mests,$mdeva
-end
-
-
-# Setup all
-define setup
- sdram_init
-# lanc_init
-# dispc_init
-# set $evb=0x08000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-# load busybox.mot
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x08001000
-
- ## MOUNT_ROOT_RDONLY
- set {long}($param+0x00)=0
- ## RAMDISK_FLAGS
- #set {long}($param+0x04)=0
- ## ORIG_ROOT_DEV
- #set {long}($param+0x08)=0x00000100
- ## LOADER_TYPE
- #set {long}($param+0x0C)=0
- ## INITRD_START
- set {long}($param+0x10)=0x082a0000
- ## INITRD_SIZE
- set {long}($param+0x14)=0d6200000
-
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d25000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d25000000
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.2.6 nfsaddrs=192.168.0.102:192.168.0.1:192.168.0.1:255.255.255.0:mappi: \0"
-
-
-end
-
-# Boot
-define boot
- set_kernel_parameters
- debug_chaos
- set $pc=0x08002000
- set $fp=0
- del b
- si
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- setup
- load_modules
- boot
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-
-restart
-boot
-
-
diff --git a/arch/m32r/platforms/mappi2/io.c b/arch/m32r/platforms/mappi2/io.c
deleted file mode 100644
index 18a408ff3fd1..000000000000
--- a/arch/m32r/platforms/mappi2/io.c
+++ /dev/null
@@ -1,384 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/mappi2/io.c
- *
- * Typical I/O routines for Mappi2 board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
-#include <linux/types.h>
-
-#define M32R_PCC_IOMAP_SIZE 0x1000
-
-#define M32R_PCC_IOSTART0 0x1000
-#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
-
-extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
-#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
-
-#define PORT2ADDR(port) _port2addr(port)
-#define PORT2ADDR_NE(port) _port2addr_ne(port)
-#define PORT2ADDR_USB(port) _port2addr_usb(port)
-
-static inline void *_port2addr(unsigned long port)
-{
- return (void *)(port | NONCACHE_OFFSET);
-}
-
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
-static inline void *__port2addr_ata(unsigned long port)
-{
- static int dummy_reg;
-
- switch (port) {
- case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
- case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
- case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
- case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
- case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
- case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
- case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
- case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
- case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
- default: return (void *)&dummy_reg;
- }
-}
-#endif
-
-#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
-#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
-#ifdef CONFIG_CHIP_OPSP
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)(port + 0x10000000);
-}
-#else
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)(port + 0x04000000);
-}
-#endif
-static inline void *_port2addr_usb(unsigned long port)
-{
- return (void *)(port + NONCACHE_OFFSET + 0x14000000);
-}
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-/*
- * NIC I/O function
- */
-
-static inline unsigned char _ne_inb(void *portp)
-{
- return (unsigned char) *(volatile unsigned char *)portp;
-}
-
-static inline unsigned short _ne_inw(void *portp)
-{
- return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
-}
-
-static inline void _ne_insb(void *portp, void * addr, unsigned long count)
-{
- unsigned char *buf = addr;
-
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
-}
-
-static inline void _ne_outb(unsigned char b, void *portp)
-{
- *(volatile unsigned char *)portp = (unsigned char)b;
-}
-
-static inline void _ne_outw(unsigned short w, void *portp)
-{
- *(volatile unsigned short *)portp = cpu_to_le16(w);
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inb(PORT2ADDR_NE(port));
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- return *(volatile unsigned char *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned char b;
- pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
- return b;
- } else
-#endif
-
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inw(PORT2ADDR_NE(port));
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- return *(volatile unsigned short *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_USB)
- else if (port >= 0x340 && port < 0x3a0)
- return *(volatile unsigned short *)PORT2ADDR_USB(port);
-#endif
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned short w;
- pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
- return w;
- } else
-#endif
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned long l;
- pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
- return l;
- } else
-#endif
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return (v);
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return (v);
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return (v);
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outb(b, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- *(volatile unsigned char *)__port2addr_ata(port) = b;
- } else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
- } else
-#endif
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outw(w, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- *(volatile unsigned short *)__port2addr_ata(port) = w;
- } else
-#endif
-#if defined(CONFIG_USB)
- if (port >= 0x340 && port < 0x3a0)
- *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
- else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
- } else
-#endif
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
- } else
-#endif
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void * addr, unsigned long count)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_insb(PORT2ADDR_NE(port), addr, count);
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- unsigned char *buf = addr;
- unsigned char *portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
- }
-#endif
- else {
- unsigned char *buf = addr;
- unsigned char *portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void * addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void * addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outb(*buf++, portp);
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
deleted file mode 100644
index 7253258a7880..000000000000
--- a/arch/m32r/platforms/mappi2/setup.c
+++ /dev/null
@@ -1,172 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/mappi2/setup.c
- *
- * Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[NR_IRQS];
-
-static void disable_mappi2_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- if ((irq == 0) ||(irq >= NR_IRQS)) {
- printk("bad irq 0x%08x\n", irq);
- return;
- }
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_mappi2_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- if ((irq == 0) ||(irq >= NR_IRQS)) {
- printk("bad irq 0x%08x\n", irq);
- return;
- }
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_mappi2(struct irq_data *data)
-{
- disable_mappi2_irq(data->irq);
-}
-
-static void unmask_mappi2(struct irq_data *data)
-{
- enable_mappi2_irq(data->irq);
-}
-
-static void shutdown_mappi2(struct irq_data *data)
-{
- unsigned long port;
-
- port = irq2port(data->irq);
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip mappi2_irq_type =
-{
- .name = "MAPPI2-IRQ",
- .irq_shutdown = shutdown_mappi2,
- .irq_mask = mask_mappi2,
- .irq_unmask = unmask_mappi2,
-};
-
-void __init init_IRQ(void)
-{
-#if defined(CONFIG_SMC91X)
- /* INT0 : LAN controller (SMC91111) */
- irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
- disable_mappi2_irq(M32R_IRQ_INT0);
-#endif /* CONFIG_SMC91X */
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_mappi2_irq(M32R_IRQ_MFT2);
-
-#ifdef CONFIG_SERIAL_M32R_SIO
- /* SIO0_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = 0;
- disable_mappi2_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = 0;
- disable_mappi2_irq(M32R_IRQ_SIO0_S);
- /* SIO1_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_R].icucr = 0;
- disable_mappi2_irq(M32R_IRQ_SIO1_R);
-
- /* SIO1_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_S].icucr = 0;
- disable_mappi2_irq(M32R_IRQ_SIO1_S);
-#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
-
-#if defined(CONFIG_USB)
- /* INT1 : USB Host controller interrupt */
- irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
- disable_mappi2_irq(M32R_IRQ_INT1);
-#endif /* CONFIG_USB */
-
- /* ICUCR40: CFC IREQ */
- irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
- handle_level_irq);
- icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
- disable_mappi2_irq(PLD_IRQ_CFIREQ);
-
-#if defined(CONFIG_M32R_CFC)
- /* ICUCR41: CFC Insert */
- irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
- handle_level_irq);
- icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
- disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
-
- /* ICUCR42: CFC Eject */
- irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
- handle_level_irq);
- icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
- disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
-#endif /* CONFIG_MAPPI2_CFC */
-}
-
-#define LAN_IOSTART 0x300
-#define LAN_IOEND 0x320
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (LAN_IOSTART),
- .end = (LAN_IOEND),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = M32R_IRQ_INT0,
- .end = M32R_IRQ_INT0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static int __init platform_init(void)
-{
- platform_device_register(&smc91x_device);
- return 0;
-}
-arch_initcall(platform_init);
diff --git a/arch/m32r/platforms/mappi3/Makefile b/arch/m32r/platforms/mappi3/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/mappi3/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/mappi3/dot.gdbinit b/arch/m32r/platforms/mappi3/dot.gdbinit
deleted file mode 100644
index 89c22184e139..000000000000
--- a/arch/m32r/platforms/mappi3/dot.gdbinit
+++ /dev/null
@@ -1,224 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit,v 1.1 2005/04/11 02:21:08 sakugawa Exp $
-
-# setting
-set width 0d70
-set radix 0d16
-use_debug_dma
-
-# Initialize SDRAM controller for Mappi
-define sdram_init
- # SDIR0
- set *(unsigned long *)0x00ef6008 = 0x00000182
- # SDIR1
- set *(unsigned long *)0x00ef600c = 0x00000001
- # Initialize wait
- shell sleep 0.1
- # MOD
- set *(unsigned long *)0x00ef602c = 0x00000020
- set *(unsigned long *)0x00ef604c = 0x00000020
- # TR
- set *(unsigned long *)0x00ef6028 = 0x00051502
- set *(unsigned long *)0x00ef6048 = 0x00051502
- # ADR
- set *(unsigned long *)0x00ef6020 = 0x08000004
- set *(unsigned long *)0x00ef6040 = 0x0c000004
- # AutoRef On
- set *(unsigned long *)0x00ef6004 = 0x00010517
- # Access enable
- set *(unsigned long *)0x00ef6024 = 0x00000001
- set *(unsigned long *)0x00ef6044 = 0x00000001
-end
-
-# Initialize LAN controller for Mappi
-define lanc_init
- # Set BSEL4
- #set *(unsigned long *)0x00ef5004 = 0x0fff330f
- #set *(unsigned long *)0x00ef5004 = 0x01113301
-
-# set *(unsigned long *)0x00ef5004 = 0x02011101
-# set *(unsigned long *)0x00ef5004 = 0x04441104
-end
-
-define clock_init
- set *(unsigned long *)0x00ef4010 = 2
- set *(unsigned long *)0x00ef4014 = 2
- set *(unsigned long *)0x00ef4020 = 3
- set *(unsigned long *)0x00ef4024 = 3
- set *(unsigned long *)0x00ef4004 = 0x7
-# shell sleep 0.1
-# set *(unsigned long *)0x00ef4004 = 0x5
- shell sleep 0.1
- set *(unsigned long *)0x00ef4008 = 0x0200
-end
-
-define port_init
- set $sfrbase = 0x00ef0000
- set *(unsigned short *)0x00ef1060 = 0x5555
- set *(unsigned short *)0x00ef1062 = 0x5555
- set *(unsigned short *)0x00ef1064 = 0x5555
- set *(unsigned short *)0x00ef1066 = 0x5555
- set *(unsigned short *)0x00ef1068 = 0x5555
- set *(unsigned short *)0x00ef106a = 0x0000
- set *(unsigned short *)0x00ef106e = 0x5555
- set *(unsigned short *)0x00ef1070 = 0x5555
-end
-
-# MMU enable
-define mmu_enable
- set $evb=0x88000000
- set *(unsigned long *)0xffff0024=1
-end
-
-# MMU disable
-define mmu_disable
- set $evb=0
- set *(unsigned long *)0xffff0024=0
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- while ($i < 0d16 )
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb
-end
-
-# Cache ON
-define set_cache_type
- set $mctype = (void*)0xfffffff8
-# chaos
-# set *(unsigned long *)($mctype) = 0x0000c000
-# m32102 i-cache only
- set *(unsigned long *)($mctype) = 0x00008000
-# m32102 d-cache only
-# set *(unsigned long *)($mctype) = 0x00004000
-end
-define cache_on
- set $param = (void*)0x08001000
- set *(unsigned long *)($param) = 0x60ff6102
-end
-
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set $task = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
- printf "EVB[0x%08lX]\n",$evb
-
- set $mests = *(unsigned long *)0xffff000c
- set $mdeva = *(unsigned long *)0xffff0010
- printf "MESTS[0x%08lX] MDEVA[0x%08lX]\n",$mests,$mdeva
-end
-
-
-# Setup all
-define setup
- clock_init
- shell sleep 0.1
- port_init
- sdram_init
-# lanc_init
-# dispc_init
-# set $evb=0x08000000
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-# load busybox.mot
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x08001000
-
- ## MOUNT_ROOT_RDONLY
- set {long}($param+0x00)=0
- ## RAMDISK_FLAGS
- #set {long}($param+0x04)=0
- ## ORIG_ROOT_DEV
- #set {long}($param+0x08)=0x00000100
- ## LOADER_TYPE
- #set {long}($param+0x0C)=0
- ## INITRD_START
- set {long}($param+0x10)=0x082a0000
- ## INITRD_SIZE
- set {long}($param+0x14)=0d6200000
-
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d100000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d50000000
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/root.2.6_04 nfsaddrs=192.168.0.102:192.168.0.1:192.168.0.1:255.255.255.0:mappi: \0"
-
-
-end
-
-# Boot
-define boot
- set_kernel_parameters
- debug_chaos
- set *(unsigned long *)0x00f00000=0x08002000
- set $pc=0x08002000
- set $fp=0
- del b
- si
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- setup
- load_modules
- boot
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-
-restart
-boot
diff --git a/arch/m32r/platforms/mappi3/io.c b/arch/m32r/platforms/mappi3/io.c
deleted file mode 100644
index e7edcab72a6b..000000000000
--- a/arch/m32r/platforms/mappi3/io.c
+++ /dev/null
@@ -1,406 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/mappi3/io.c
- *
- * Typical I/O routines for Mappi3 board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
-#include <linux/types.h>
-
-#define M32R_PCC_IOMAP_SIZE 0x1000
-
-#define M32R_PCC_IOSTART0 0x1000
-#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
-
-extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
-#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
-
-#define PORT2ADDR(port) _port2addr(port)
-#define PORT2ADDR_NE(port) _port2addr_ne(port)
-#define PORT2ADDR_USB(port) _port2addr_usb(port)
-
-static inline void *_port2addr(unsigned long port)
-{
- return (void *)(port | NONCACHE_OFFSET);
-}
-
-#if defined(CONFIG_IDE)
-static inline void *__port2addr_ata(unsigned long port)
-{
- static int dummy_reg;
-
- switch (port) {
- /* IDE0 CF */
- case 0x1f0: return (void *)(0x14002000 | NONCACHE_OFFSET);
- case 0x1f1: return (void *)(0x14012800 | NONCACHE_OFFSET);
- case 0x1f2: return (void *)(0x14012002 | NONCACHE_OFFSET);
- case 0x1f3: return (void *)(0x14012802 | NONCACHE_OFFSET);
- case 0x1f4: return (void *)(0x14012004 | NONCACHE_OFFSET);
- case 0x1f5: return (void *)(0x14012804 | NONCACHE_OFFSET);
- case 0x1f6: return (void *)(0x14012006 | NONCACHE_OFFSET);
- case 0x1f7: return (void *)(0x14012806 | NONCACHE_OFFSET);
- case 0x3f6: return (void *)(0x1401200e | NONCACHE_OFFSET);
- /* IDE1 IDE */
- case 0x170: /* Data 16bit */
- return (void *)(0x14810000 | NONCACHE_OFFSET);
- case 0x171: /* Features / Error */
- return (void *)(0x14810002 | NONCACHE_OFFSET);
- case 0x172: /* Sector count */
- return (void *)(0x14810004 | NONCACHE_OFFSET);
- case 0x173: /* Sector number */
- return (void *)(0x14810006 | NONCACHE_OFFSET);
- case 0x174: /* Cylinder low */
- return (void *)(0x14810008 | NONCACHE_OFFSET);
- case 0x175: /* Cylinder high */
- return (void *)(0x1481000a | NONCACHE_OFFSET);
- case 0x176: /* Device head */
- return (void *)(0x1481000c | NONCACHE_OFFSET);
- case 0x177: /* Command */
- return (void *)(0x1481000e | NONCACHE_OFFSET);
- case 0x376: /* Device control / Alt status */
- return (void *)(0x1480800c | NONCACHE_OFFSET);
-
- default: return (void *)&dummy_reg;
- }
-}
-#endif
-
-#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
-#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)(port + 0x10000000);
-}
-
-static inline void *_port2addr_usb(unsigned long port)
-{
- return (void *)(port + NONCACHE_OFFSET + 0x12000000);
-}
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-/*
- * NIC I/O function
- */
-
-static inline unsigned char _ne_inb(void *portp)
-{
- return (unsigned char) *(volatile unsigned char *)portp;
-}
-
-static inline unsigned short _ne_inw(void *portp)
-{
- return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
-}
-
-static inline void _ne_insb(void *portp, void * addr, unsigned long count)
-{
- unsigned char *buf = addr;
-
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
-}
-
-static inline void _ne_outb(unsigned char b, void *portp)
-{
- *(volatile unsigned char *)portp = (unsigned char)b;
-}
-
-static inline void _ne_outw(unsigned short w, void *portp)
-{
- *(volatile unsigned short *)portp = cpu_to_le16(w);
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inb(PORT2ADDR_NE(port));
-#if defined(CONFIG_IDE)
- else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- return *(volatile unsigned char *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned char b;
- pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
- return b;
- } else
-#endif
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inw(PORT2ADDR_NE(port));
-#if defined(CONFIG_IDE)
- else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- return *(volatile unsigned short *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_USB)
- else if (port >= 0x340 && port < 0x3a0)
- return *(volatile unsigned short *)PORT2ADDR_USB(port);
-#endif
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned short w;
- pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
- return w;
- } else
-#endif
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned long l;
- pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
- return l;
- } else
-#endif
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return (v);
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return (v);
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return (v);
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outb(b, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE)
- if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- *(volatile unsigned char *)__port2addr_ata(port) = b;
- } else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
- } else
-#endif
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outw(w, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE)
- if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- *(volatile unsigned short *)__port2addr_ata(port) = w;
- } else
-#endif
-#if defined(CONFIG_USB)
- if (port >= 0x340 && port < 0x3a0)
- *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
- else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
- } else
-#endif
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
- } else
-#endif
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void * addr, unsigned long count)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_insb(PORT2ADDR_NE(port), addr, count);
-#if defined(CONFIG_IDE)
- else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- unsigned char *buf = addr;
- unsigned char *portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
- }
-#endif
- else {
- unsigned char *buf = addr;
- unsigned char *portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void * addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
-#if defined(CONFIG_IDE)
- } else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void * addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outb(*buf++, portp);
-#if defined(CONFIG_IDE)
- } else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#if defined(CONFIG_IDE)
- } else if ( ((port >= 0x170 && port <=0x177) || port == 0x376) ||
- ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) ){
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
deleted file mode 100644
index 87d2000081f7..000000000000
--- a/arch/m32r/platforms/mappi3/setup.c
+++ /dev/null
@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/mappi3/setup.c
- *
- * Setup routines for Renesas MAPPI-III(M3A-2170) Board
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[NR_IRQS];
-
-static void disable_mappi3_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- if ((irq == 0) ||(irq >= NR_IRQS)) {
- printk("bad irq 0x%08x\n", irq);
- return;
- }
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_mappi3_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- if ((irq == 0) ||(irq >= NR_IRQS)) {
- printk("bad irq 0x%08x\n", irq);
- return;
- }
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_mappi3(struct irq_data *data)
-{
- disable_mappi3_irq(data->irq);
-}
-
-static void unmask_mappi3(struct irq_data *data)
-{
- enable_mappi3_irq(data->irq);
-}
-
-static void shutdown_mappi3(struct irq_data *data)
-{
- unsigned long port;
-
- port = irq2port(data->irq);
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip mappi3_irq_type = {
- .name = "MAPPI3-IRQ",
- .irq_shutdown = shutdown_mappi3,
- .irq_mask = mask_mappi3,
- .irq_unmask = unmask_mappi3,
-};
-
-void __init init_IRQ(void)
-{
-#if defined(CONFIG_SMC91X)
- /* INT0 : LAN controller (SMC91111) */
- irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
- disable_mappi3_irq(M32R_IRQ_INT0);
-#endif /* CONFIG_SMC91X */
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_mappi3_irq(M32R_IRQ_MFT2);
-
-#ifdef CONFIG_SERIAL_M32R_SIO
- /* SIO0_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = 0;
- disable_mappi3_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = 0;
- disable_mappi3_irq(M32R_IRQ_SIO0_S);
- /* SIO1_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_R].icucr = 0;
- disable_mappi3_irq(M32R_IRQ_SIO1_R);
-
- /* SIO1_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_S].icucr = 0;
- disable_mappi3_irq(M32R_IRQ_SIO1_S);
-#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
-
-#if defined(CONFIG_USB)
- /* INT1 : USB Host controller interrupt */
- irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
- disable_mappi3_irq(M32R_IRQ_INT1);
-#endif /* CONFIG_USB */
-
- /* CFC IREQ */
- irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
- handle_level_irq);
- icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
- disable_mappi3_irq(PLD_IRQ_CFIREQ);
-
-#if defined(CONFIG_M32R_CFC)
- /* ICUCR41: CFC Insert & eject */
- irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
- handle_level_irq);
- icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
- disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
-
-#endif /* CONFIG_M32R_CFC */
-
- /* IDE IREQ */
- irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
- handle_level_irq);
- icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
- disable_mappi3_irq(PLD_IRQ_IDEIREQ);
-
-}
-
-#if defined(CONFIG_SMC91X)
-
-#define LAN_IOSTART 0x300
-#define LAN_IOEND 0x320
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (LAN_IOSTART),
- .end = (LAN_IOEND),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = M32R_IRQ_INT0,
- .end = M32R_IRQ_INT0,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-#endif
-
-#if defined(CONFIG_FB_S1D13XXX)
-
-#include <video/s1d13xxxfb.h>
-#include <asm/s1d13806.h>
-
-static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
- .initregs = s1d13xxxfb_initregs,
- .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
- .platform_init_video = NULL,
-#ifdef CONFIG_PM
- .platform_suspend_video = NULL,
- .platform_resume_video = NULL,
-#endif
-};
-
-static struct resource s1d13xxxfb_resources[] = {
- [0] = {
- .start = 0x1d600000UL,
- .end = 0x1d73FFFFUL,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x1d400000UL,
- .end = 0x1d4001FFUL,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device s1d13xxxfb_device = {
- .name = S1D_DEVICENAME,
- .id = 0,
- .dev = {
- .platform_data = &s1d13xxxfb_data,
- },
- .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
- .resource = s1d13xxxfb_resources,
-};
-#endif
-
-static int __init platform_init(void)
-{
-#if defined(CONFIG_SMC91X)
- platform_device_register(&smc91x_device);
-#endif
-#if defined(CONFIG_FB_S1D13XXX)
- platform_device_register(&s1d13xxxfb_device);
-#endif
- return 0;
-}
-arch_initcall(platform_init);
diff --git a/arch/m32r/platforms/oaks32r/Makefile b/arch/m32r/platforms/oaks32r/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/oaks32r/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/oaks32r/dot.gdbinit.nommu b/arch/m32r/platforms/oaks32r/dot.gdbinit.nommu
deleted file mode 100644
index d481d972b802..000000000000
--- a/arch/m32r/platforms/oaks32r/dot.gdbinit.nommu
+++ /dev/null
@@ -1,154 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit.oaks32r,v 1.4 2004/10/20 02:24:37 takata Exp $
-#-----
-# NOTE: this file is generated by a script, "gen_gdbinit.pl".
-# (Please type "gen_gdbinit.pl --help" and check the help message).
-# $ Id: gen_gdbinit.pl,v 1.12 2004/07/26 09:56:10 takata Exp $
-#-----
-# target platform: oaks32r
-
-# setting
-set width 0d70
-set radix 0d16
-
-# clk xin:cpu:bus=16:66:33
-define clock_init
- set *(unsigned long *)0x00ef4008 = 1
- shell sleep 0.1
- set *(unsigned long *)0x00ef4000 = 0x00020100
-end
-
-# Initialize programmable ports
-define port_init
- set *(unsigned long *)0x00ef1000 = 0x1
- set *(unsigned long *)0x00ef1060 = 0x01400001
- set *(unsigned long *)0x00ef1064 = 0x00015555
- set *(unsigned long *)0x00ef1068 = 0x55555050
- set *(unsigned long *)0x00ef106c = 0x05150040
-end
-
-# Initialize SDRAM controller
-define sdram_init
- set *(unsigned long *)0x00ef6008 = 0x00000182
- set *(unsigned long *)0x00ef600c = 0x00000001
- shell sleep 0.1
- set *(unsigned long *)0x00ef602c = 0x00000010
- set *(unsigned long *)0x00ef6028 = 0x00000300
- set *(unsigned long *)0x00ef6048 = 0x00000001
- set *(unsigned long *)0x00ef6020 = 0x01000041
- set *(unsigned long *)0x00ef6004 = 0x00010117
- set *(unsigned long *)0x00ef6010 = 0x00000001
- set *(unsigned long *)0x00ef6024 = 0x00000001
-end
-document sdram_init
- SDRAM controller initialization
- 0x01000000 - 0x017fffff (8MB)
-end
-
-# Initialize LAN controller
-define lanc_init
- set *(unsigned long *)0x00ef5008 = 0x03031303
- #RST DRV (P64)
- set *(unsigned char *)0x00ef1046 = 0x08
- set *(unsigned char *)0x00ef1026 = 0xff
- set *(unsigned char *)0x00ef1026 = 0x00
- set *(unsigned short *)0x02000630 = 0xffff
-end
-
-# Show current task structure
-define show_current
- set $current = $spi & 0xffffe000
- printf "$current=0x%08lX\n",$current
- print *(struct task_struct *)$current
-end
-
-# Show user assigned task structure
-define show_task
- set = $arg0 & 0xffffe000
- printf "$task=0x%08lX\n",$task
- print *(struct task_struct *)$task
-end
-document show_task
- Show user assigned task structure
- arg0 : task structure address
-end
-
-# Show M32R registers
-define show_regs
- printf " R0[0x%08lX] R1[0x%08lX] R2[0x%08lX] R3[0x%08lX]\n",$r0,$r1,$r2,$r3
- printf " R4[0x%08lX] R5[0x%08lX] R6[0x%08lX] R7[0x%08lX]\n",$r4,$r5,$r6,$r7
- printf " R8[0x%08lX] R9[0x%08lX] R10[0x%08lX] R11[0x%08lX]\n",$r8,$r9,$r10,$r11
- printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
- printf "PSW[0x%08lX] CBR[0x%08lX] SPI[0x%08lX] SPU[0x%08lX]\n",$psw,$cbr,$spi,$spu
- printf "BPC[0x%08lX] PC[0x%08lX] ACCL[0x%08lX] ACCH[0x%08lX]\n",$bpc,$pc,$accl,$acch
-end
-
-# Setup all
-define setup
- use_mon_code
- set *(unsigned int)0xfffffffc=0x60
- shell sleep 0.1
- clock_init
- shell sleep 0.1
- port_init
- sdram_init
- lanc_init
-end
-
-# Load modules
-define load_modules
- use_debug_dma
- load
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x01001000
- # INITRD_START
-# set *(unsigned long *)($param + 0x0010) = 0x00000000
- # INITRD_SIZE
-# set *(unsigned long *)($param + 0x0014) = 0x00000000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d66666667
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d33333333
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x root=/dev/nfsroot nfsroot=192.168.0.1:/project/m32r-linux/export/rootfs nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \0"
-end
-
-# Boot
-define boot
- set_kernel_parameters
- set $fp = 0
- set $pc = 0x01002000
- si
- c
-end
-
-# Set breakpoints
-define set_breakpoints
- b *0x00000020
- b *0x00000030
-end
-
-# Restart
-define restart
- sdireset
- sdireset
- setup
- load_modules
- boot
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-setup
-#load_modules
-#set_breakpoints
-#boot
-
diff --git a/arch/m32r/platforms/oaks32r/io.c b/arch/m32r/platforms/oaks32r/io.c
deleted file mode 100644
index 3ce1f3ac0d16..000000000000
--- a/arch/m32r/platforms/oaks32r/io.c
+++ /dev/null
@@ -1,229 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/oaks32r/io.c
- *
- * Typical I/O routines for OAKS32R board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-
-#define PORT2ADDR(port) _port2addr(port)
-
-static inline void *_port2addr(unsigned long port)
-{
- return (void *)(port | NONCACHE_OFFSET);
-}
-
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)((port<<1) + NONCACHE_OFFSET + 0x02000000);
-}
-
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-/*
- * NIC I/O function
- */
-
-#define PORT2ADDR_NE(port) _port2addr_ne(port)
-
-static inline unsigned char _ne_inb(void *portp)
-{
- return *(volatile unsigned char *)(portp+1);
-}
-
-static inline unsigned short _ne_inw(void *portp)
-{
- unsigned short tmp;
-
- tmp = *(unsigned short *)(portp) & 0xff;
- tmp |= *(unsigned short *)(portp+2) << 8;
- return tmp;
-}
-
-static inline void _ne_insb(void *portp, void *addr, unsigned long count)
-{
- unsigned char *buf = addr;
- while (count--)
- *buf++ = *(volatile unsigned char *)(portp+1);
-}
-
-static inline void _ne_outb(unsigned char b, void *portp)
-{
- *(volatile unsigned char *)(portp+1) = b;
-}
-
-static inline void _ne_outw(unsigned short w, void *portp)
-{
- *(volatile unsigned short *)portp = (w >> 8);
- *(volatile unsigned short *)(portp+2) = (w & 0xff);
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- return _ne_inb(PORT2ADDR_NE(port));
-
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- return _ne_inw(PORT2ADDR_NE(port));
-
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return (v);
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return (v);
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return (v);
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- _ne_outb(b, PORT2ADDR_NE(port));
- else
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= 0x300 && port < 0x320)
- _ne_outw(w, PORT2ADDR_NE(port));
- else
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void *addr, unsigned long count)
-{
- if (port >= 0x300 && port < 0x320)
- _ne_insb(PORT2ADDR_NE(port), addr, count);
- else {
- unsigned char *buf = addr;
- unsigned char *portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void *addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= 0x300 && port < 0x320) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = _ne_inw(portp);
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void *addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= 0x300 && port < 0x320) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outb(*buf++, portp);
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= 0x300 && port < 0x320) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outw(*buf++, portp);
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
deleted file mode 100644
index 8188c0baa064..000000000000
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/oaks32r/setup.c
- *
- * Setup routines for OAKS32R Board
- *
- * Copyright (c) 2002-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Mamoru Sakugawa
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[NR_IRQS];
-
-static void disable_oaks32r_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_oaks32r_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_oaks32r(struct irq_data *data)
-{
- disable_oaks32r_irq(data->irq);
-}
-
-static void unmask_oaks32r(struct irq_data *data)
-{
- enable_oaks32r_irq(data->irq);
-}
-
-static void shutdown_oaks32r(struct irq_data *data)
-{
- unsigned long port;
-
- port = irq2port(data->irq);
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip oaks32r_irq_type =
-{
- .name = "OAKS32R-IRQ",
- .irq_shutdown = shutdown_oaks32r,
- .irq_mask = mask_oaks32r,
- .irq_unmask = unmask_oaks32r,
-};
-
-void __init init_IRQ(void)
-{
- static int once = 0;
-
- if (once)
- return;
- else
- once++;
-
-#ifdef CONFIG_NE2000
- /* INT3 : LAN controller (RTL8019AS) */
- irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
- disable_oaks32r_irq(M32R_IRQ_INT3);
-#endif /* CONFIG_M32R_NE2000 */
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_oaks32r_irq(M32R_IRQ_MFT2);
-
-#ifdef CONFIG_SERIAL_M32R_SIO
- /* SIO0_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = 0;
- disable_oaks32r_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = 0;
- disable_oaks32r_irq(M32R_IRQ_SIO0_S);
-
- /* SIO1_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_R].icucr = 0;
- disable_oaks32r_irq(M32R_IRQ_SIO1_R);
-
- /* SIO1_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_S].icucr = 0;
- disable_oaks32r_irq(M32R_IRQ_SIO1_S);
-#endif /* CONFIG_SERIAL_M32R_SIO */
-}
diff --git a/arch/m32r/platforms/opsput/Makefile b/arch/m32r/platforms/opsput/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/opsput/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/opsput/dot.gdbinit b/arch/m32r/platforms/opsput/dot.gdbinit
deleted file mode 100644
index b7e6c6640857..000000000000
--- a/arch/m32r/platforms/opsput/dot.gdbinit
+++ /dev/null
@@ -1,218 +0,0 @@
-# .gdbinit file
-# $Id: dot.gdbinit,v 1.1 2004/07/27 06:54:20 sakugawa Exp $
-
-# setting
-set width 0d70
-set radix 0d16
-set height 0
-debug_chaos
-
-# clk xin:cpu:bus=1:8:1
-define clock_init_on_181
- set *(unsigned long *)0x00ef400c = 0x2
- set *(unsigned long *)0x00ef4004 = 0x1
- shell sleep 0.1
- set *(unsigned long *)0x00ef4000 = 0x101
-end
-# clk xin:cpu:bus=1:8:2
-define clock_init_on_182
- set *(unsigned long *)0x00ef400c = 0x1
- set *(unsigned long *)0x00ef4004 = 0x1
- shell sleep 0.1
- set *(unsigned long *)0x00ef4000 = 0x101
-end
-
-# clk xin:cpu:bus=1:8:4
-define clock_init_on_184
- set *(unsigned long *)0x00ef400c = 0x0
- set *(unsigned long *)0x00ef4004 = 0x1
- shell sleep 0.1
- set *(unsigned long *)0x00ef4000 = 0x101
-end
-
-# clk xin:cpu:bus=1:1:1
-define clock_init_off
- shell sleep 0.1
- set *(unsigned long *)0x00ef4000 = 0x0
- shell sleep 0.1
- set *(unsigned long *)0x00ef4004 = 0x0
- shell sleep 0.1
- set *(unsigned long *)0x00ef400c = 0x0
-end
-
-define tlb_init
- set $tlbbase = 0xfe000000
- set *(unsigned long *)($tlbbase + 0x04) = 0x0
- set *(unsigned long *)($tlbbase + 0x0c) = 0x0
- set *(unsigned long *)($tlbbase + 0x14) = 0x0
- set *(unsigned long *)($tlbbase + 0x1c) = 0x0
- set *(unsigned long *)($tlbbase + 0x24) = 0x0
- set *(unsigned long *)($tlbbase + 0x2c) = 0x0
- set *(unsigned long *)($tlbbase + 0x34) = 0x0
- set *(unsigned long *)($tlbbase + 0x3c) = 0x0
- set *(unsigned long *)($tlbbase + 0x44) = 0x0
- set *(unsigned long *)($tlbbase + 0x4c) = 0x0
- set *(unsigned long *)($tlbbase + 0x54) = 0x0
- set *(unsigned long *)($tlbbase + 0x5c) = 0x0
- set *(unsigned long *)($tlbbase + 0x64) = 0x0
- set *(unsigned long *)($tlbbase + 0x6c) = 0x0
- set *(unsigned long *)($tlbbase + 0x74) = 0x0
- set *(unsigned long *)($tlbbase + 0x7c) = 0x0
- set *(unsigned long *)($tlbbase + 0x84) = 0x0
- set *(unsigned long *)($tlbbase + 0x8c) = 0x0
- set *(unsigned long *)($tlbbase + 0x94) = 0x0
- set *(unsigned long *)($tlbbase + 0x9c) = 0x0
- set *(unsigned long *)($tlbbase + 0xa4) = 0x0
- set *(unsigned long *)($tlbbase + 0xac) = 0x0
- set *(unsigned long *)($tlbbase + 0xb4) = 0x0
- set *(unsigned long *)($tlbbase + 0xbc) = 0x0
- set *(unsigned long *)($tlbbase + 0xc4) = 0x0
- set *(unsigned long *)($tlbbase + 0xcc) = 0x0
- set *(unsigned long *)($tlbbase + 0xd4) = 0x0
- set *(unsigned long *)($tlbbase + 0xdc) = 0x0
- set *(unsigned long *)($tlbbase + 0xe4) = 0x0
- set *(unsigned long *)($tlbbase + 0xec) = 0x0
- set *(unsigned long *)($tlbbase + 0xf4) = 0x0
- set *(unsigned long *)($tlbbase + 0xfc) = 0x0
- set $tlbbase = 0xfe000800
- set *(unsigned long *)($tlbbase + 0x04) = 0x0
- set *(unsigned long *)($tlbbase + 0x0c) = 0x0
- set *(unsigned long *)($tlbbase + 0x14) = 0x0
- set *(unsigned long *)($tlbbase + 0x1c) = 0x0
- set *(unsigned long *)($tlbbase + 0x24) = 0x0
- set *(unsigned long *)($tlbbase + 0x2c) = 0x0
- set *(unsigned long *)($tlbbase + 0x34) = 0x0
- set *(unsigned long *)($tlbbase + 0x3c) = 0x0
- set *(unsigned long *)($tlbbase + 0x44) = 0x0
- set *(unsigned long *)($tlbbase + 0x4c) = 0x0
- set *(unsigned long *)($tlbbase + 0x54) = 0x0
- set *(unsigned long *)($tlbbase + 0x5c) = 0x0
- set *(unsigned long *)($tlbbase + 0x64) = 0x0
- set *(unsigned long *)($tlbbase + 0x6c) = 0x0
- set *(unsigned long *)($tlbbase + 0x74) = 0x0
- set *(unsigned long *)($tlbbase + 0x7c) = 0x0
- set *(unsigned long *)($tlbbase + 0x84) = 0x0
- set *(unsigned long *)($tlbbase + 0x8c) = 0x0
- set *(unsigned long *)($tlbbase + 0x94) = 0x0
- set *(unsigned long *)($tlbbase + 0x9c) = 0x0
- set *(unsigned long *)($tlbbase + 0xa4) = 0x0
- set *(unsigned long *)($tlbbase + 0xac) = 0x0
- set *(unsigned long *)($tlbbase + 0xb4) = 0x0
- set *(unsigned long *)($tlbbase + 0xbc) = 0x0
- set *(unsigned long *)($tlbbase + 0xc4) = 0x0
- set *(unsigned long *)($tlbbase + 0xcc) = 0x0
- set *(unsigned long *)($tlbbase + 0xd4) = 0x0
- set *(unsigned long *)($tlbbase + 0xdc) = 0x0
- set *(unsigned long *)($tlbbase + 0xe4) = 0x0
- set *(unsigned long *)($tlbbase + 0xec) = 0x0
- set *(unsigned long *)($tlbbase + 0xf4) = 0x0
- set *(unsigned long *)($tlbbase + 0xfc) = 0x0
-end
-
-define load_modules
- use_debug_dma
- load
-end
-
-# Set kernel parameters
-define set_kernel_parameters
- set $param = (void*)0x88001000
- # INITRD_START
-# set *(unsigned long *)($param + 0x0010) = 0x08300000
- # INITRD_SIZE
-# set *(unsigned long *)($param + 0x0014) = 0x00400000
- # M32R_CPUCLK
- set *(unsigned long *)($param + 0x0018) = 0d200000000
- # M32R_BUSCLK
- set *(unsigned long *)($param + 0x001c) = 0d50000000
-# set *(unsigned long *)($param + 0x001c) = 0d25000000
-
- # M32R_TIMER_DIVIDE
- set *(unsigned long *)($param + 0x0020) = 0d128
-
- set {char[0x200]}($param + 0x100) = "console=ttyS0,115200n8x console=tty1 \
- root=/dev/nfsroot \
- nfsroot=192.168.0.1:/project/m32r-linux/export/root.2.6 \
- nfsaddrs=192.168.0.101:192.168.0.1:192.168.0.1:255.255.255.0:mappi001 \
- mem=16m \0"
-end
-
-define boot
- set_kernel_parameters
- set $pc=0x88002000
- set $fp=0
- set $evb=0x88000000
- si
- c
-end
-
-# Show TLB entries
-define show_tlb_entries
- set $i = 0
- set $addr = $arg0
- use_mon_code
- while ($i < 0d32 )
- set $tlb_tag = *(unsigned long*)$addr
- set $tlb_data = *(unsigned long*)($addr + 4)
- printf " [%2d] 0x%08lx : 0x%08lx - 0x%08lx\n", $i, $addr, $tlb_tag, $tlb_data
- set $i = $i + 1
- set $addr = $addr + 8
- end
-# use_debug_dma
-end
-define itlb
- set $itlb=0xfe000000
- show_tlb_entries $itlb
-end
-define dtlb
- set $dtlb=0xfe000800
- show_tlb_entries $dtlb
-end
-
-define show_regs
- printf " R0[%08lx] R1[%08lx] R2[%08lx] R3[%08lx]\n",$r0,$r1,$r2,$r3
- printf " R4[%08lx] R5[%08lx] R6[%08lx] R7[%08lx]\n",$r4,$r5,$r6,$r7
- printf " R8[%08lx] R9[%08lx] R10[%08lx] R11[%08lx]\n",$r8,$r9,$r10,$r11
- printf "R12[%08lx] FP[%08lx] LR[%08lx] SP[%08lx]\n",$r12,$fp,$lr,$sp
- printf "PSW[%08lx] CBR[%08lx] SPI[%08lx] SPU[%08lx]\n",$psw,$cbr,$spi,$spu
- printf "BPC[%08lx] PC[%08lx] ACCL[%08lx] ACCH[%08lx]\n",$bpc,$pc,$accl,$acch
- printf "EVB[%08lx]\n",$evb
-end
-
-define restart
- sdireset
- sdireset
- en 1
- set $pc=0x0
- c
- tlb_init
- setup
- load_modules
- boot
-end
-
-define setup
- debug_chaos
-# Clock
-# shell sleep 0.1
-# clock_init_off
-# shell sleep 1
-# clock_init_on_182
-# shell sleep 0.1
-# SDRAM
- set *(unsigned long *)0xa0ef6004 = 0x0001053f
- set *(unsigned long *)0xa0ef6028 = 0x00031102
-end
-
-sdireset
-sdireset
-file vmlinux
-target m32rsdi
-set $pc=0x0
-b *0x30000
-c
-dis 1
-setup
-tlb_init
-load_modules
-boot
diff --git a/arch/m32r/platforms/opsput/io.c b/arch/m32r/platforms/opsput/io.c
deleted file mode 100644
index 379efb77123d..000000000000
--- a/arch/m32r/platforms/opsput/io.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * linux/arch/m32r/platforms/opsput/io.c
- *
- * Typical I/O routines for OPSPUT board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of this
- * archive for more details.
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
-#include <linux/types.h>
-
-#define M32R_PCC_IOMAP_SIZE 0x1000
-
-#define M32R_PCC_IOSTART0 0x1000
-#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
-
-extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
-#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
-
-#define PORT2ADDR(port) _port2addr(port)
-#define PORT2ADDR_USB(port) _port2addr_usb(port)
-
-static inline void *_port2addr(unsigned long port)
-{
- return (void *)(port | NONCACHE_OFFSET);
-}
-
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
-static inline void *__port2addr_ata(unsigned long port)
-{
- static int dummy_reg;
-
- switch (port) {
- case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
- case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
- case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
- case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
- case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
- case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
- case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
- case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
- case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
- default: return (void *)&dummy_reg;
- }
-}
-#endif
-
-/*
- * OPSPUT-LAN is located in the extended bus space
- * from 0x10000000 to 0x13ffffff on physical address.
- * The base address of LAN controller(LAN91C111) is 0x300.
- */
-#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
-#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
-static inline void *_port2addr_ne(unsigned long port)
-{
- return (void *)(port + 0x10000000);
-}
-static inline void *_port2addr_usb(unsigned long port)
-{
- return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
-}
-
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-/*
- * NIC I/O function
- */
-
-#define PORT2ADDR_NE(port) _port2addr_ne(port)
-
-static inline unsigned char _ne_inb(void *portp)
-{
- return *(volatile unsigned char *)portp;
-}
-
-static inline unsigned short _ne_inw(void *portp)
-{
- return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
-}
-
-static inline void _ne_insb(void *portp, void *addr, unsigned long count)
-{
- unsigned char *buf = (unsigned char *)addr;
-
- while (count--)
- *buf++ = _ne_inb(portp);
-}
-
-static inline void _ne_outb(unsigned char b, void *portp)
-{
- *(volatile unsigned char *)portp = b;
-}
-
-static inline void _ne_outw(unsigned short w, void *portp)
-{
- *(volatile unsigned short *)portp = cpu_to_le16(w);
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inb(PORT2ADDR_NE(port));
-
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- return *(volatile unsigned char *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned char b;
- pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
- return b;
- } else
-#endif
-
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- return _ne_inw(PORT2ADDR_NE(port));
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- return *(volatile unsigned short *)__port2addr_ata(port);
- }
-#endif
-#if defined(CONFIG_USB)
- else if(port >= 0x340 && port < 0x3a0)
- return *(volatile unsigned short *)PORT2ADDR_USB(port);
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned short w;
- pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
- return w;
- } else
-#endif
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- unsigned long l;
- pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
- return l;
- } else
-#endif
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return (v);
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return (v);
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return (v);
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outb(b, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- *(volatile unsigned char *)__port2addr_ata(port) = b;
- } else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
- } else
-#endif
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_outw(w, PORT2ADDR_NE(port));
- else
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- *(volatile unsigned short *)__port2addr_ata(port) = w;
- } else
-#endif
-#if defined(CONFIG_USB)
- if(port >= 0x340 && port < 0x3a0)
- *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
- else
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
- } else
-#endif
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
- } else
-#endif
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void *addr, unsigned long count)
-{
- if (port >= LAN_IOSTART && port < LAN_IOEND)
- _ne_insb(PORT2ADDR_NE(port), addr, count);
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- unsigned char *buf = addr;
- unsigned char *portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
- }
-#endif
- else {
- unsigned char *buf = addr;
- unsigned char *portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void *addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- /*
- * This portion is only used by smc91111.c to read data
- * from the DATA_REG. Do not swap the data.
- */
- portp = PORT2ADDR_NE(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void *addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- portp = PORT2ADDR_NE(port);
- while (count--)
- _ne_outb(*buf++, portp);
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= LAN_IOSTART && port < LAN_IOEND) {
- /*
- * This portion is only used by smc91111.c to write data
- * into the DATA_REG. Do not swap the data.
- */
- portp = PORT2ADDR_NE(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
- } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
- portp = __port2addr_ata(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
-#endif
-#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
- } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
- pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
- count, 1);
-#endif
- } else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void *addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
deleted file mode 100644
index cd0170483e83..000000000000
--- a/arch/m32r/platforms/opsput/setup.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/*
- * linux/arch/m32r/platforms/opsput/setup.c
- *
- * Setup routines for Renesas OPSPUT Board
- *
- * Copyright (c) 2002-2005
- * Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of this
- * archive for more details.
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-/*
- * OPSP Interrupt Control Unit (Level 1)
- */
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
-
-static void disable_opsput_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_opsput_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_opsput(struct irq_data *data)
-{
- disable_opsput_irq(data->irq);
-}
-
-static void unmask_opsput(struct irq_data *data)
-{
- enable_opsput_irq(data->irq);
-}
-
-static void shutdown_opsput(struct irq_data *data)
-{
- unsigned long port;
-
- port = irq2port(data->irq);
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip opsput_irq_type =
-{
- .name = "OPSPUT-IRQ",
- .irq_shutdown = shutdown_opsput,
- .irq_mask = mask_opsput,
- .irq_unmask = unmask_opsput,
-};
-
-/*
- * Interrupt Control Unit of PLD on OPSPUT (Level 2)
- */
-#define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
-#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
- (((x) - 1) * sizeof(unsigned short)))
-
-typedef struct {
- unsigned short icucr; /* ICU Control Register */
-} pld_icu_data_t;
-
-static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
-
-static void disable_opsput_pld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(irq);
- port = pldirq2port(pldirq);
- data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
- outw(data, port);
-}
-
-static void enable_opsput_pld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(irq);
- port = pldirq2port(pldirq);
- data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
- outw(data, port);
-}
-
-static void mask_opsput_pld(struct irq_data *data)
-{
- disable_opsput_pld_irq(data->irq);
-}
-
-static void unmask_opsput_pld(struct irq_data *data)
-{
- enable_opsput_pld_irq(data->irq);
- enable_opsput_irq(M32R_IRQ_INT1);
-}
-
-static void shutdown_opsput_pld(struct irq_data *data)
-{
- unsigned long port;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(data->irq);
- port = pldirq2port(pldirq);
- outw(PLD_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip opsput_pld_irq_type =
-{
- .name = "OPSPUT-PLD-IRQ",
- .irq_shutdown = shutdown_opsput_pld,
- .irq_mask = mask_opsput_pld,
- .irq_unmask = unmask_opsput_pld,
-};
-
-/*
- * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
- */
-#define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
-#define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
- (((x) - 1) * sizeof(unsigned short)))
-
-static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
-
-static void disable_opsput_lanpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lanpldirq(irq);
- port = lanpldirq2port(pldirq);
- data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
- outw(data, port);
-}
-
-static void enable_opsput_lanpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lanpldirq(irq);
- port = lanpldirq2port(pldirq);
- data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
- outw(data, port);
-}
-
-static void mask_opsput_lanpld(struct irq_data *data)
-{
- disable_opsput_lanpld_irq(data->irq);
-}
-
-static void unmask_opsput_lanpld(struct irq_data *data)
-{
- enable_opsput_lanpld_irq(data->irq);
- enable_opsput_irq(M32R_IRQ_INT0);
-}
-
-static void shutdown_opsput_lanpld(struct irq_data *data)
-{
- unsigned long port;
- unsigned int pldirq;
-
- pldirq = irq2lanpldirq(data->irq);
- port = lanpldirq2port(pldirq);
- outw(PLD_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip opsput_lanpld_irq_type =
-{
- .name = "OPSPUT-PLD-LAN-IRQ",
- .irq_shutdown = shutdown_opsput_lanpld,
- .irq_mask = mask_opsput_lanpld,
- .irq_unmask = unmask_opsput_lanpld,
-};
-
-/*
- * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
- */
-#define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
-#define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
- (((x) - 1) * sizeof(unsigned short)))
-
-static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
-
-static void disable_opsput_lcdpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lcdpldirq(irq);
- port = lcdpldirq2port(pldirq);
- data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
- outw(data, port);
-}
-
-static void enable_opsput_lcdpld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2lcdpldirq(irq);
- port = lcdpldirq2port(pldirq);
- data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
- outw(data, port);
-}
-
-static void mask_opsput_lcdpld(struct irq_data *data)
-{
- disable_opsput_lcdpld_irq(data->irq);
-}
-
-static void unmask_opsput_lcdpld(struct irq_data *data)
-{
- enable_opsput_lcdpld_irq(data->irq);
- enable_opsput_irq(M32R_IRQ_INT2);
-}
-
-static void shutdown_opsput_lcdpld(struct irq_data *data)
-{
- unsigned long port;
- unsigned int pldirq;
-
- pldirq = irq2lcdpldirq(data->irq);
- port = lcdpldirq2port(pldirq);
- outw(PLD_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip opsput_lcdpld_irq_type = {
- .name = "OPSPUT-PLD-LCD-IRQ",
- .irq_shutdown = shutdown_opsput_lcdpld,
- .irq_mask = mask_opsput_lcdpld,
- .irq_unmask = unmask_opsput_lcdpld,
-};
-
-void __init init_IRQ(void)
-{
-#if defined(CONFIG_SMC91X)
- /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
- irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type,
- handle_level_irq);
- lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
- disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
-#endif /* CONFIG_SMC91X */
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_opsput_irq(M32R_IRQ_MFT2);
-
- /* SIO0 : receive */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = 0;
- disable_opsput_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0 : send */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = 0;
- disable_opsput_irq(M32R_IRQ_SIO0_S);
-
- /* SIO1 : receive */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_R].icucr = 0;
- disable_opsput_irq(M32R_IRQ_SIO1_R);
-
- /* SIO1 : send */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_S].icucr = 0;
- disable_opsput_irq(M32R_IRQ_SIO1_S);
-
- /* DMA1 : */
- irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_DMA1].icucr = 0;
- disable_opsput_irq(M32R_IRQ_DMA1);
-
-#ifdef CONFIG_SERIAL_M32R_PLDSIO
- /* INT#1: SIO0 Receive on PLD */
- irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
- disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
-
- /* INT#1: SIO0 Send on PLD */
- irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
- disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
-#endif /* CONFIG_SERIAL_M32R_PLDSIO */
-
- /* INT#1: CFC IREQ on PLD */
- irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
- disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
-
- /* INT#1: CFC Insert on PLD */
- irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
- disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
-
- /* INT#1: CFC Eject on PLD */
- irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
- disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
-
- /*
- * INT0# is used for LAN, DIO
- * We enable it here.
- */
- icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
- enable_opsput_irq(M32R_IRQ_INT0);
-
- /*
- * INT1# is used for UART, MMC, CF Controller in FPGA.
- * We enable it here.
- */
- icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
- enable_opsput_irq(M32R_IRQ_INT1);
-
-#if defined(CONFIG_USB)
- outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
- irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1,
- &opsput_lcdpld_irq_type, handle_level_irq);
- lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
- disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
-#endif
- /*
- * INT2# is used for BAT, USB, AUDIO
- * We enable it here.
- */
- icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
- enable_opsput_irq(M32R_IRQ_INT2);
-
-#if defined(CONFIG_VIDEO_M32R_AR)
- /*
- * INT3# is used for AR
- */
- irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
- disable_opsput_irq(M32R_IRQ_INT3);
-#endif /* CONFIG_VIDEO_M32R_AR */
-}
-
-#if defined(CONFIG_SMC91X)
-
-#define LAN_IOSTART 0x300
-#define LAN_IOEND 0x320
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = (LAN_IOSTART),
- .end = (LAN_IOEND),
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = OPSPUT_LAN_IRQ_LAN,
- .end = OPSPUT_LAN_IRQ_LAN,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-#endif
-
-#if defined(CONFIG_FB_S1D13XXX)
-
-#include <video/s1d13xxxfb.h>
-#include <asm/s1d13806.h>
-
-static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
- .initregs = s1d13xxxfb_initregs,
- .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
- .platform_init_video = NULL,
-#ifdef CONFIG_PM
- .platform_suspend_video = NULL,
- .platform_resume_video = NULL,
-#endif
-};
-
-static struct resource s1d13xxxfb_resources[] = {
- [0] = {
- .start = 0x10600000UL,
- .end = 0x1073FFFFUL,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = 0x10400000UL,
- .end = 0x104001FFUL,
- .flags = IORESOURCE_MEM,
- }
-};
-
-static struct platform_device s1d13xxxfb_device = {
- .name = S1D_DEVICENAME,
- .id = 0,
- .dev = {
- .platform_data = &s1d13xxxfb_data,
- },
- .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
- .resource = s1d13xxxfb_resources,
-};
-#endif
-
-static int __init platform_init(void)
-{
-#if defined(CONFIG_SMC91X)
- platform_device_register(&smc91x_device);
-#endif
-#if defined(CONFIG_FB_S1D13XXX)
- platform_device_register(&s1d13xxxfb_device);
-#endif
- return 0;
-}
-arch_initcall(platform_init);
diff --git a/arch/m32r/platforms/usrv/Makefile b/arch/m32r/platforms/usrv/Makefile
deleted file mode 100644
index 0de59084f21c..000000000000
--- a/arch/m32r/platforms/usrv/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/usrv/io.c b/arch/m32r/platforms/usrv/io.c
deleted file mode 100644
index f5e50d37badb..000000000000
--- a/arch/m32r/platforms/usrv/io.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * linux/arch/m32r/platforms/usrv/io.c
- *
- * Typical I/O routines for uServer board.
- *
- * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto, Takeo Takahashi
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file "COPYING" in the main directory of this
- * archive for more details.
- *
- */
-
-#include <asm/m32r.h>
-#include <asm/page.h>
-#include <asm/io.h>
-
-#include <linux/types.h>
-#include "../../../../drivers/pcmcia/m32r_cfc.h"
-
-extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
-extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
-#define CFC_IOSTART CFC_IOPORT_BASE
-#define CFC_IOEND (CFC_IOSTART + (M32R_PCC_MAPSIZE * M32R_MAX_PCC) - 1)
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-#define UART0_REGSTART 0x04c20000
-#define UART1_REGSTART 0x04c20100
-#define UART_IOMAP_SIZE 8
-#define UART0_IOSTART 0x3f8
-#define UART0_IOEND (UART0_IOSTART + UART_IOMAP_SIZE - 1)
-#define UART1_IOSTART 0x2f8
-#define UART1_IOEND (UART1_IOSTART + UART_IOMAP_SIZE - 1)
-#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
-
-#define PORT2ADDR(port) _port2addr(port)
-
-static inline void *_port2addr(unsigned long port)
-{
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
- if (port >= UART0_IOSTART && port <= UART0_IOEND)
- port = ((port - UART0_IOSTART) << 1) + UART0_REGSTART;
- else if (port >= UART1_IOSTART && port <= UART1_IOEND)
- port = ((port - UART1_IOSTART) << 1) + UART1_REGSTART;
-#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
- return (void *)(port | (NONCACHE_OFFSET));
-}
-
-static inline void delay(void)
-{
- __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
-}
-
-unsigned char _inb(unsigned long port)
-{
- if (port >= CFC_IOSTART && port <= CFC_IOEND) {
- unsigned char b;
- pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
- return b;
- } else
- return *(volatile unsigned char *)PORT2ADDR(port);
-}
-
-unsigned short _inw(unsigned long port)
-{
- if (port >= CFC_IOSTART && port <= CFC_IOEND) {
- unsigned short w;
- pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
- return w;
- } else
- return *(volatile unsigned short *)PORT2ADDR(port);
-}
-
-unsigned long _inl(unsigned long port)
-{
- if (port >= CFC_IOSTART && port <= CFC_IOEND) {
- unsigned long l;
- pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
- return l;
- } else
- return *(volatile unsigned long *)PORT2ADDR(port);
-}
-
-unsigned char _inb_p(unsigned long port)
-{
- unsigned char v = _inb(port);
- delay();
- return v;
-}
-
-unsigned short _inw_p(unsigned long port)
-{
- unsigned short v = _inw(port);
- delay();
- return v;
-}
-
-unsigned long _inl_p(unsigned long port)
-{
- unsigned long v = _inl(port);
- delay();
- return v;
-}
-
-void _outb(unsigned char b, unsigned long port)
-{
- if (port >= CFC_IOSTART && port <= CFC_IOEND)
- pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
- else
- *(volatile unsigned char *)PORT2ADDR(port) = b;
-}
-
-void _outw(unsigned short w, unsigned long port)
-{
- if (port >= CFC_IOSTART && port <= CFC_IOEND)
- pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
- else
- *(volatile unsigned short *)PORT2ADDR(port) = w;
-}
-
-void _outl(unsigned long l, unsigned long port)
-{
- if (port >= CFC_IOSTART && port <= CFC_IOEND)
- pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
- else
- *(volatile unsigned long *)PORT2ADDR(port) = l;
-}
-
-void _outb_p(unsigned char b, unsigned long port)
-{
- _outb(b, port);
- delay();
-}
-
-void _outw_p(unsigned short w, unsigned long port)
-{
- _outw(w, port);
- delay();
-}
-
-void _outl_p(unsigned long l, unsigned long port)
-{
- _outl(l, port);
- delay();
-}
-
-void _insb(unsigned int port, void * addr, unsigned long count)
-{
- if (port >= CFC_IOSTART && port <= CFC_IOEND)
- pcc_ioread_byte(0, port, addr, sizeof(unsigned char), count, 1);
- else {
- unsigned char *buf = addr;
- unsigned char *portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned char *)portp;
- }
-}
-
-void _insw(unsigned int port, void * addr, unsigned long count)
-{
- unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= CFC_IOSTART && port <= CFC_IOEND)
- pcc_ioread_word(0, port, addr, sizeof(unsigned short), count,
- 1);
- else {
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned short *)portp;
- }
-}
-
-void _insl(unsigned int port, void * addr, unsigned long count)
-{
- unsigned long *buf = addr;
- unsigned long *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *buf++ = *(volatile unsigned long *)portp;
-}
-
-void _outsb(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned char *buf = addr;
- unsigned char *portp;
-
- if (port >= CFC_IOSTART && port <= CFC_IOEND)
- pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
- count, 1);
- else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned char *)portp = *buf++;
- }
-}
-
-void _outsw(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned short *buf = addr;
- unsigned short *portp;
-
- if (port >= CFC_IOSTART && port <= CFC_IOEND)
- pcc_iowrite_word(0, port, (void *)addr, sizeof(unsigned short),
- count, 1);
- else {
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned short *)portp = *buf++;
- }
-}
-
-void _outsl(unsigned int port, const void * addr, unsigned long count)
-{
- const unsigned long *buf = addr;
- unsigned char *portp;
-
- portp = PORT2ADDR(port);
- while (count--)
- *(volatile unsigned long *)portp = *buf++;
-}
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
deleted file mode 100644
index ba828b16c6e3..000000000000
--- a/arch/m32r/platforms/usrv/setup.c
+++ /dev/null
@@ -1,213 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * linux/arch/m32r/platforms/usrv/setup.c
- *
- * Setup routines for MITSUBISHI uServer
- *
- * Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
- * Hitoshi Yamamoto
- */
-
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/m32r.h>
-#include <asm/io.h>
-
-#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
-
-icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
-
-static void disable_mappi_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
- outl(data, port);
-}
-
-static void enable_mappi_irq(unsigned int irq)
-{
- unsigned long port, data;
-
- port = irq2port(irq);
- data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
- outl(data, port);
-}
-
-static void mask_mappi(struct irq_data *data)
-{
- disable_mappi_irq(data->irq);
-}
-
-static void unmask_mappi(struct irq_data *data)
-{
- enable_mappi_irq(data->irq);
-}
-
-static void shutdown_mappi(struct irq_data *data)
-{
- unsigned long port;
-
- port = irq2port(data->irq);
- outl(M32R_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip mappi_irq_type =
-{
- .name = "M32700-IRQ",
- .irq_shutdown = shutdown_mappi,
- .irq_mask = mask_mappi,
- .irq_unmask = unmask_mappi,
-};
-
-/*
- * Interrupt Control Unit of PLD on M32700UT (Level 2)
- */
-#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
-#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
- (((x) - 1) * sizeof(unsigned short)))
-
-typedef struct {
- unsigned short icucr; /* ICU Control Register */
-} pld_icu_data_t;
-
-static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
-
-static void disable_m32700ut_pld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(irq);
- port = pldirq2port(pldirq);
- data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
- outw(data, port);
-}
-
-static void enable_m32700ut_pld_irq(unsigned int irq)
-{
- unsigned long port, data;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(irq);
- port = pldirq2port(pldirq);
- data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
- outw(data, port);
-}
-
-static void mask_m32700ut_pld(struct irq_data *data)
-{
- disable_m32700ut_pld_irq(data->irq);
-}
-
-static void unmask_m32700ut_pld(struct irq_data *data)
-{
- enable_m32700ut_pld_irq(data->irq);
- enable_mappi_irq(M32R_IRQ_INT1);
-}
-
-static void shutdown_m32700ut_pld(struct irq_data *data)
-{
- unsigned long port;
- unsigned int pldirq;
-
- pldirq = irq2pldirq(data->irq);
- port = pldirq2port(pldirq);
- outw(PLD_ICUCR_ILEVEL7, port);
-}
-
-static struct irq_chip m32700ut_pld_irq_type =
-{
- .name = "USRV-PLD-IRQ",
- .irq_shutdown = shutdown_m32700ut_pld,
- .irq_mask = mask_m32700ut_pld,
- .irq_unmask = unmask_m32700ut_pld,
-};
-
-void __init init_IRQ(void)
-{
- static int once = 0;
- int i;
-
- if (once)
- return;
- else
- once++;
-
- /* MFT2 : system timer */
- irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
- disable_mappi_irq(M32R_IRQ_MFT2);
-
-#if defined(CONFIG_SERIAL_M32R_SIO)
- /* SIO0_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_R].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO0_R);
-
- /* SIO0_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO0_S].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO0_S);
-
- /* SIO1_R : uart receive data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_R].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO1_R);
-
- /* SIO1_S : uart send data */
- irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
- handle_level_irq);
- icu_data[M32R_IRQ_SIO1_S].icucr = 0;
- disable_mappi_irq(M32R_IRQ_SIO1_S);
-#endif /* CONFIG_SERIAL_M32R_SIO */
-
- /* INT#67-#71: CFC#0 IREQ on PLD */
- for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
- irq_set_chip_and_handler(PLD_IRQ_CF0 + i,
- &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
- = PLD_ICUCR_ISMOD01; /* 'L' level sense */
- disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
- }
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
- /* INT#76: 16552D#0 IREQ on PLD */
- irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
- = PLD_ICUCR_ISMOD03; /* 'H' level sense */
- disable_m32700ut_pld_irq(PLD_IRQ_UART0);
-
- /* INT#77: 16552D#1 IREQ on PLD */
- irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
- = PLD_ICUCR_ISMOD03; /* 'H' level sense */
- disable_m32700ut_pld_irq(PLD_IRQ_UART1);
-#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
-
-#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
- /* INT#80: AK4524 IREQ on PLD */
- irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
- handle_level_irq);
- pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
- = PLD_ICUCR_ISMOD01; /* 'L' level sense */
- disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
-#endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
-
- /*
- * INT1# is used for UART, MMC, CF Controller in FPGA.
- * We enable it here.
- */
- icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
- enable_mappi_irq(M32R_IRQ_INT1);
-}
diff --git a/arch/m68k/configs/amiga_defconfig b/arch/m68k/configs/amiga_defconfig
index 52fa7fbdefa2..37a8e5ab8728 100644
--- a/arch/m68k/configs/amiga_defconfig
+++ b/arch/m68k/configs/amiga_defconfig
@@ -105,6 +105,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -124,6 +125,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -202,6 +205,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -231,6 +235,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -244,6 +249,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -354,6 +360,7 @@ CONFIG_SCSI_ZORRO7XX=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -399,6 +406,7 @@ CONFIG_ARIADNE=y
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
@@ -416,6 +424,7 @@ CONFIG_ZORRO8390=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -474,6 +483,7 @@ CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_RP5C01=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
@@ -593,7 +603,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/apollo_defconfig b/arch/m68k/configs/apollo_defconfig
index b00fe19e1c04..6a466266b852 100644
--- a/arch/m68k/configs/apollo_defconfig
+++ b/arch/m68k/configs/apollo_defconfig
@@ -103,6 +103,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -122,6 +123,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -200,6 +203,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -229,6 +233,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -242,6 +247,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -336,6 +342,7 @@ CONFIG_ISCSI_BOOT_SYSFS=m
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -377,6 +384,7 @@ CONFIG_VETH=m
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
@@ -390,6 +398,7 @@ CONFIG_VETH=m
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -435,6 +444,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
@@ -552,7 +562,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/atari_defconfig b/arch/m68k/configs/atari_defconfig
index 2871d75b912f..b0691a7a3345 100644
--- a/arch/m68k/configs/atari_defconfig
+++ b/arch/m68k/configs/atari_defconfig
@@ -103,6 +103,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -122,6 +123,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -200,6 +203,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -229,6 +233,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -242,6 +247,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -345,6 +351,7 @@ CONFIG_ATARI_SCSI=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -387,6 +394,7 @@ CONFIG_ATARILANCE=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
@@ -401,6 +409,7 @@ CONFIG_NE2000=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
CONFIG_SMC91X=y
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -450,6 +459,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
@@ -574,7 +584,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/bvme6000_defconfig b/arch/m68k/configs/bvme6000_defconfig
index 2c90328433bf..6f6470fa9a50 100644
--- a/arch/m68k/configs/bvme6000_defconfig
+++ b/arch/m68k/configs/bvme6000_defconfig
@@ -101,6 +101,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -120,6 +121,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -198,6 +201,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -227,6 +231,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -240,6 +245,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -335,6 +341,7 @@ CONFIG_BVME6000_SCSI=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -376,6 +383,7 @@ CONFIG_VETH=m
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_BVME6000_NET=y
@@ -389,6 +397,7 @@ CONFIG_BVME6000_NET=y
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -428,6 +437,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PROC_HARDWARE=y
CONFIG_EXT4_FS=y
@@ -544,7 +554,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/hp300_defconfig b/arch/m68k/configs/hp300_defconfig
index 177c91d63826..31a1a2b5e860 100644
--- a/arch/m68k/configs/hp300_defconfig
+++ b/arch/m68k/configs/hp300_defconfig
@@ -103,6 +103,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -122,6 +123,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -200,6 +203,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -229,6 +233,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -242,6 +247,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -336,6 +342,7 @@ CONFIG_ISCSI_BOOT_SYSFS=m
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -378,6 +385,7 @@ CONFIG_HPLANCE=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
@@ -391,6 +399,7 @@ CONFIG_HPLANCE=y
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -438,6 +447,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PROC_HARDWARE=y
CONFIG_EXT4_FS=y
@@ -554,7 +564,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index efbcaffa30ed..390d4a87441c 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -102,6 +102,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -121,6 +122,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -199,6 +202,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -228,6 +232,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -241,6 +246,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -345,6 +351,7 @@ CONFIG_SCSI_MAC_ESP=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -395,6 +402,7 @@ CONFIG_MACMACE=y
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_MAC89x0=y
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
@@ -410,6 +418,7 @@ CONFIG_MAC8390=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -460,6 +469,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PROC_HARDWARE=y
CONFIG_EXT4_FS=y
@@ -576,7 +586,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig
index e78a205d266a..77be97d82dc3 100644
--- a/arch/m68k/configs/multi_defconfig
+++ b/arch/m68k/configs/multi_defconfig
@@ -112,6 +112,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -131,6 +132,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -209,6 +212,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -238,6 +242,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -251,6 +256,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -378,6 +384,7 @@ CONFIG_SUN3X_ESP=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -435,6 +442,7 @@ CONFIG_MACMACE=y
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_MAC89x0=y
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
@@ -456,6 +464,7 @@ CONFIG_ZORRO8390=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
CONFIG_SMC91X=y
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -530,6 +539,7 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MSM6242=m
CONFIG_RTC_DRV_RP5C01=m
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
@@ -656,7 +666,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/mvme147_defconfig b/arch/m68k/configs/mvme147_defconfig
index 0d42ecacfd7a..2ca140757b0f 100644
--- a/arch/m68k/configs/mvme147_defconfig
+++ b/arch/m68k/configs/mvme147_defconfig
@@ -100,6 +100,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -119,6 +120,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -197,6 +200,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -226,6 +230,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -239,6 +244,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -334,6 +340,7 @@ CONFIG_MVME147_SCSI=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -376,6 +383,7 @@ CONFIG_MVME147_NET=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
@@ -389,6 +397,7 @@ CONFIG_MVME147_NET=y
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -428,6 +437,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PROC_HARDWARE=y
CONFIG_EXT4_FS=y
@@ -544,7 +554,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/mvme16x_defconfig b/arch/m68k/configs/mvme16x_defconfig
index 8dc609c5b8aa..6a3b4dcc5aab 100644
--- a/arch/m68k/configs/mvme16x_defconfig
+++ b/arch/m68k/configs/mvme16x_defconfig
@@ -101,6 +101,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -120,6 +121,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -198,6 +201,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -227,6 +231,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -240,6 +245,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -335,6 +341,7 @@ CONFIG_MVME16x_SCSI=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -376,6 +383,7 @@ CONFIG_VETH=m
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_MVME16x_NET=y
@@ -389,6 +397,7 @@ CONFIG_MVME16x_NET=y
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -428,6 +437,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PROC_HARDWARE=y
CONFIG_EXT4_FS=y
@@ -544,7 +554,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig
index 11c96087fc5d..2a3e29c97652 100644
--- a/arch/m68k/configs/q40_defconfig
+++ b/arch/m68k/configs/q40_defconfig
@@ -101,6 +101,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -120,6 +121,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -198,6 +201,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -227,6 +231,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -240,6 +245,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -341,6 +347,7 @@ CONFIG_ISCSI_BOOT_SYSFS=m
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -385,6 +392,7 @@ CONFIG_VETH=m
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
@@ -400,6 +408,7 @@ CONFIG_NE2000=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -450,6 +459,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
@@ -567,7 +577,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/sun3_defconfig b/arch/m68k/configs/sun3_defconfig
index ddba205ee1aa..cba2494c99b2 100644
--- a/arch/m68k/configs/sun3_defconfig
+++ b/arch/m68k/configs/sun3_defconfig
@@ -98,6 +98,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -117,6 +118,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -195,6 +198,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -224,6 +228,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -237,6 +242,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -332,6 +338,7 @@ CONFIG_SUN3_SCSI=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -373,6 +380,7 @@ CONFIG_SUN3LANCE=y
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_SUN3_82586=y
@@ -386,6 +394,7 @@ CONFIG_SUN3_82586=y
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_VIA is not set
@@ -430,6 +439,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PROC_HARDWARE=y
CONFIG_EXT4_FS=y
@@ -546,7 +556,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/configs/sun3x_defconfig b/arch/m68k/configs/sun3x_defconfig
index 88d09a14c684..d911561137fd 100644
--- a/arch/m68k/configs/sun3x_defconfig
+++ b/arch/m68k/configs/sun3x_defconfig
@@ -98,6 +98,7 @@ CONFIG_NFT_META=m
CONFIG_NFT_RT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
+CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_SET_RBTREE=m
CONFIG_NFT_SET_HASH=m
CONFIG_NFT_SET_BITMAP=m
@@ -117,6 +118,8 @@ CONFIG_NFT_FIB_INET=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_FIB_NETDEV=m
+CONFIG_NF_FLOW_TABLE_INET=m
+CONFIG_NF_FLOW_TABLE=m
CONFIG_NETFILTER_XT_SET=m
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
@@ -195,6 +198,7 @@ CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=m
+CONFIG_NF_FLOW_TABLE_IPV4=m
CONFIG_NF_LOG_ARP=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_MASQ_IPV4=m
@@ -224,6 +228,7 @@ CONFIG_NF_SOCKET_IPV6=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
+CONFIG_NF_FLOW_TABLE_IPV6=m
CONFIG_NFT_CHAIN_NAT_IPV6=m
CONFIG_NFT_MASQ_IPV6=m
CONFIG_NFT_REDIR_IPV6=m
@@ -237,6 +242,7 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RPFILTER=m
CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_MATCH_SRH=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
@@ -332,6 +338,7 @@ CONFIG_SUN3X_ESP=y
CONFIG_MD=y
CONFIG_MD_LINEAR=m
CONFIG_BLK_DEV_DM=m
+CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
@@ -374,6 +381,7 @@ CONFIG_SUN3LANCE=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
@@ -387,6 +395,7 @@ CONFIG_SUN3LANCE=y
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
@@ -430,6 +439,7 @@ CONFIG_UHID=m
CONFIG_RTC_CLASS=y
# CONFIG_RTC_NVMEM is not set
CONFIG_RTC_DRV_GENERIC=m
+# CONFIG_VIRTIO_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PROC_HARDWARE=y
CONFIG_EXT4_FS=y
@@ -546,7 +556,7 @@ CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_HASH=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
-CONFIG_TEST_FIND_BIT=m
+CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_TEST_UDELAY=m
diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c
index 27e10af5153a..6363ec83a290 100644
--- a/arch/m68k/kernel/sys_m68k.c
+++ b/arch/m68k/kernel/sys_m68k.c
@@ -46,7 +46,7 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
* so we need to shift the argument down by 1; m68k mmap64(3)
* (in libc) expects the last argument of mmap2 in 4Kb units.
*/
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
}
/* Convert virtual (user) address VADDR to physical address PADDR */
diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c
index 87160b4415fb..97dd4e26f234 100644
--- a/arch/m68k/kernel/time.c
+++ b/arch/m68k/kernel/time.c
@@ -91,7 +91,7 @@ void read_persistent_clock(struct timespec *ts)
static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
{
mach_hwclk(0, tm);
- return rtc_valid_tm(tm);
+ return 0;
}
static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
diff --git a/arch/m68k/mac/baboon.c b/arch/m68k/mac/baboon.c
index c7ea6475ef9b..a7d280220662 100644
--- a/arch/m68k/mac/baboon.c
+++ b/arch/m68k/mac/baboon.c
@@ -18,10 +18,6 @@
int baboon_present;
static volatile struct baboon *baboon;
-#if 0
-extern int macide_ack_intr(struct ata_channel *);
-#endif
-
/*
* Baboon initialization.
*/
@@ -41,33 +37,26 @@ void __init baboon_init(void)
}
/*
- * Baboon interrupt handler. This works a lot like a VIA.
+ * Baboon interrupt handler.
+ * XXX how do you clear a pending IRQ? is it even necessary?
*/
static void baboon_irq(struct irq_desc *desc)
{
- int irq_bit, irq_num;
- unsigned char events;
+ short events, irq_bit;
+ int irq_num;
events = baboon->mb_ifr & 0x07;
- if (!events)
- return;
-
irq_num = IRQ_BABOON_0;
irq_bit = 1;
do {
- if (events & irq_bit) {
- baboon->mb_ifr &= ~irq_bit;
+ if (events & irq_bit) {
+ events &= ~irq_bit;
generic_handle_irq(irq_num);
}
+ ++irq_num;
irq_bit <<= 1;
- irq_num++;
- } while(events >= irq_bit);
-#if 0
- if (baboon->mb_ifr & 0x02) macide_ack_intr(NULL);
- /* for now we need to smash all interrupts */
- baboon->mb_ifr &= ~events;
-#endif
+ } while (events);
}
/*
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
index d3d435248a24..36086cceb537 100644
--- a/arch/m68k/mac/config.c
+++ b/arch/m68k/mac/config.c
@@ -26,6 +26,7 @@
#include <linux/platform_device.h>
#include <linux/adb.h>
#include <linux/cuda.h>
+#include <linux/pmu.h>
#include <linux/rtc.h>
#include <asm/setup.h>
@@ -699,7 +700,7 @@ static struct mac_model mac_data_table[] = {
.name = "PowerBook 190",
.adb_type = MAC_ADB_PB2,
.via_type = MAC_VIA_QUADRA,
- .scsi_type = MAC_SCSI_LATE,
+ .scsi_type = MAC_SCSI_OLD,
.ide_type = MAC_IDE_BABOON,
.scc_type = MAC_SCC_QUADRA,
.floppy_type = MAC_FLOPPY_SWIM_ADDR2,
@@ -890,6 +891,9 @@ static void __init mac_identify(void)
#ifdef CONFIG_ADB_CUDA
find_via_cuda();
#endif
+#ifdef CONFIG_ADB_PMU68K
+ find_via_pmu();
+#endif
}
static void __init mac_report_hardware(void)
@@ -1061,9 +1065,7 @@ int __init mac_platform_init(void)
mac_scsi_old_rsrc, ARRAY_SIZE(mac_scsi_old_rsrc));
break;
case MAC_SCSI_LATE:
- /* PDMA logic in 68040 PowerBooks is somehow different to
- * '030 models. It's probably more like Quadras (see mac_esp).
- */
+ /* XXX PDMA support for PowerBook 500 series needs testing */
platform_device_register_simple("mac_scsi", 0,
mac_scsi_late_rsrc, ARRAY_SIZE(mac_scsi_late_rsrc));
break;
diff --git a/arch/m68k/mac/misc.c b/arch/m68k/mac/misc.c
index 4956edaac926..c68054361615 100644
--- a/arch/m68k/mac/misc.c
+++ b/arch/m68k/mac/misc.c
@@ -43,18 +43,19 @@ static long cuda_read_time(void)
while (!req.complete)
cuda_poll();
- time = (req.reply[3] << 24) | (req.reply[4] << 16)
- | (req.reply[5] << 8) | req.reply[6];
+ time = (req.reply[3] << 24) | (req.reply[4] << 16) |
+ (req.reply[5] << 8) | req.reply[6];
return time - RTC_OFFSET;
}
static void cuda_write_time(long data)
{
struct adb_request req;
+
data += RTC_OFFSET;
if (cuda_request(&req, NULL, 6, CUDA_PACKET, CUDA_SET_TIME,
- (data >> 24) & 0xFF, (data >> 16) & 0xFF,
- (data >> 8) & 0xFF, data & 0xFF) < 0)
+ (data >> 24) & 0xFF, (data >> 16) & 0xFF,
+ (data >> 8) & 0xFF, data & 0xFF) < 0)
return;
while (!req.complete)
cuda_poll();
@@ -63,8 +64,9 @@ static void cuda_write_time(long data)
static __u8 cuda_read_pram(int offset)
{
struct adb_request req;
+
if (cuda_request(&req, NULL, 4, CUDA_PACKET, CUDA_GET_PRAM,
- (offset >> 8) & 0xFF, offset & 0xFF) < 0)
+ (offset >> 8) & 0xFF, offset & 0xFF) < 0)
return 0;
while (!req.complete)
cuda_poll();
@@ -74,18 +76,14 @@ static __u8 cuda_read_pram(int offset)
static void cuda_write_pram(int offset, __u8 data)
{
struct adb_request req;
+
if (cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_SET_PRAM,
- (offset >> 8) & 0xFF, offset & 0xFF, data) < 0)
+ (offset >> 8) & 0xFF, offset & 0xFF, data) < 0)
return;
while (!req.complete)
cuda_poll();
}
-#else
-#define cuda_read_time() 0
-#define cuda_write_time(n)
-#define cuda_read_pram NULL
-#define cuda_write_pram NULL
-#endif
+#endif /* CONFIG_ADB_CUDA */
#ifdef CONFIG_ADB_PMU68K
static long pmu_read_time(void)
@@ -98,14 +96,15 @@ static long pmu_read_time(void)
while (!req.complete)
pmu_poll();
- time = (req.reply[1] << 24) | (req.reply[2] << 16)
- | (req.reply[3] << 8) | req.reply[4];
+ time = (req.reply[1] << 24) | (req.reply[2] << 16) |
+ (req.reply[3] << 8) | req.reply[4];
return time - RTC_OFFSET;
}
static void pmu_write_time(long data)
{
struct adb_request req;
+
data += RTC_OFFSET;
if (pmu_request(&req, NULL, 5, PMU_SET_RTC,
(data >> 24) & 0xFF, (data >> 16) & 0xFF,
@@ -118,6 +117,7 @@ static void pmu_write_time(long data)
static __u8 pmu_read_pram(int offset)
{
struct adb_request req;
+
if (pmu_request(&req, NULL, 3, PMU_READ_NVRAM,
(offset >> 8) & 0xFF, offset & 0xFF) < 0)
return 0;
@@ -129,18 +129,14 @@ static __u8 pmu_read_pram(int offset)
static void pmu_write_pram(int offset, __u8 data)
{
struct adb_request req;
+
if (pmu_request(&req, NULL, 4, PMU_WRITE_NVRAM,
(offset >> 8) & 0xFF, offset & 0xFF, data) < 0)
return;
while (!req.complete)
pmu_poll();
}
-#else
-#define pmu_read_time() 0
-#define pmu_write_time(n)
-#define pmu_read_pram NULL
-#define pmu_write_pram NULL
-#endif
+#endif /* CONFIG_ADB_PMU68K */
/*
* VIA PRAM/RTC access routines
@@ -151,8 +147,8 @@ static void pmu_write_pram(int offset, __u8 data)
static __u8 via_pram_readbyte(void)
{
- int i,reg;
- __u8 data;
+ int i, reg;
+ __u8 data;
reg = via1[vBufB] & ~VIA1B_vRTCClk;
@@ -178,7 +174,7 @@ static __u8 via_pram_readbyte(void)
static void via_pram_writebyte(__u8 data)
{
- int i,reg,bit;
+ int i, reg, bit;
reg = via1[vBufB] & ~(VIA1B_vRTCClk | VIA1B_vRTCData);
@@ -204,7 +200,7 @@ static void via_pram_writebyte(__u8 data)
static void via_pram_command(int command, __u8 *data)
{
unsigned long flags;
- int is_read;
+ int is_read;
local_irq_save(flags);
@@ -298,10 +294,10 @@ static long via_read_time(void)
static void via_write_time(long time)
{
union {
- __u8 cdata[4];
- long idata;
+ __u8 cdata[4];
+ long idata;
} data;
- __u8 temp;
+ __u8 temp;
/* Clear the write protect bit */
@@ -333,20 +329,16 @@ static void via_shutdown(void)
}
}
-/*
- * FIXME: not sure how this is supposed to work exactly...
- */
-
static void oss_shutdown(void)
{
oss->rom_ctrl = OSS_POWEROFF;
}
#ifdef CONFIG_ADB_CUDA
-
static void cuda_restart(void)
{
struct adb_request req;
+
if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_RESET_SYSTEM) < 0)
return;
while (!req.complete)
@@ -356,6 +348,7 @@ static void cuda_restart(void)
static void cuda_shutdown(void)
{
struct adb_request req;
+
if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_POWERDOWN) < 0)
return;
@@ -372,7 +365,6 @@ static void cuda_shutdown(void)
while (!req.complete)
cuda_poll();
}
-
#endif /* CONFIG_ADB_CUDA */
#ifdef CONFIG_ADB_PMU68K
@@ -419,18 +411,26 @@ void mac_pram_read(int offset, __u8 *buffer, int len)
__u8 (*func)(int);
int i;
- switch(macintosh_config->adb_type) {
+ switch (macintosh_config->adb_type) {
+ case MAC_ADB_IOP:
+ case MAC_ADB_II:
case MAC_ADB_PB1:
- case MAC_ADB_PB2:
- func = pmu_read_pram; break;
+ func = via_read_pram;
+ break;
+#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
- func = cuda_read_pram; break;
+ func = cuda_read_pram;
+ break;
+#endif
+#ifdef CONFIG_ADB_PMU68K
+ case MAC_ADB_PB2:
+ func = pmu_read_pram;
+ break;
+#endif
default:
- func = via_read_pram;
- }
- if (!func)
return;
+ }
for (i = 0 ; i < len ; i++) {
buffer[i] = (*func)(offset++);
}
@@ -441,18 +441,26 @@ void mac_pram_write(int offset, __u8 *buffer, int len)
void (*func)(int, __u8);
int i;
- switch(macintosh_config->adb_type) {
+ switch (macintosh_config->adb_type) {
+ case MAC_ADB_IOP:
+ case MAC_ADB_II:
case MAC_ADB_PB1:
- case MAC_ADB_PB2:
- func = pmu_write_pram; break;
+ func = via_write_pram;
+ break;
+#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
- func = cuda_write_pram; break;
+ func = cuda_write_pram;
+ break;
+#endif
+#ifdef CONFIG_ADB_PMU68K
+ case MAC_ADB_PB2:
+ func = pmu_write_pram;
+ break;
+#endif
default:
- func = via_write_pram;
- }
- if (!func)
return;
+ }
for (i = 0 ; i < len ; i++) {
(*func)(offset++, buffer[i]);
}
@@ -531,6 +539,7 @@ void mac_reset(void)
unsigned long phys = virt_to_phys(mac_reset);
unsigned long addr = (phys&0xFF000000)|0x8777;
unsigned long offset = phys-virt;
+
local_irq_disable(); /* lets not screw this up, ok? */
__asm__ __volatile__(".chip 68030\n\t"
"pmove %0,%/tt0\n\t"
@@ -538,7 +547,7 @@ void mac_reset(void)
: : "m" (addr));
/* Now jump to physical address so we can disable MMU */
__asm__ __volatile__(
- ".chip 68030\n\t"
+ ".chip 68030\n\t"
"lea %/pc@(1f),%/a0\n\t"
"addl %0,%/a0\n\t"/* fixup target address and stack ptr */
"addl %0,%/sp\n\t"
@@ -627,9 +636,8 @@ static void unmktime(unsigned long time, long offset,
long int yg = y + days / 365 - (days % 365 < 0);
/* Adjust DAYS and Y to match the guessed year. */
- days -= ((yg - y) * 365
- + LEAPS_THRU_END_OF (yg - 1)
- - LEAPS_THRU_END_OF (y - 1));
+ days -= (yg - y) * 365 +
+ LEAPS_THRU_END_OF(yg - 1) - LEAPS_THRU_END_OF(y - 1);
y = yg;
}
*yearp = y - 1900;
@@ -653,18 +661,22 @@ int mac_hwclk(int op, struct rtc_time *t)
if (!op) { /* read */
switch (macintosh_config->adb_type) {
- case MAC_ADB_II:
case MAC_ADB_IOP:
- now = via_read_time();
- break;
+ case MAC_ADB_II:
case MAC_ADB_PB1:
- case MAC_ADB_PB2:
- now = pmu_read_time();
+ now = via_read_time();
break;
+#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
now = cuda_read_time();
break;
+#endif
+#ifdef CONFIG_ADB_PMU68K
+ case MAC_ADB_PB2:
+ now = pmu_read_time();
+ break;
+#endif
default:
now = 0;
}
@@ -685,18 +697,24 @@ int mac_hwclk(int op, struct rtc_time *t)
t->tm_hour, t->tm_min, t->tm_sec);
switch (macintosh_config->adb_type) {
- case MAC_ADB_II:
case MAC_ADB_IOP:
+ case MAC_ADB_II:
+ case MAC_ADB_PB1:
via_write_time(now);
break;
+#ifdef CONFIG_ADB_CUDA
case MAC_ADB_EGRET:
case MAC_ADB_CUDA:
cuda_write_time(now);
break;
- case MAC_ADB_PB1:
+#endif
+#ifdef CONFIG_ADB_PMU68K
case MAC_ADB_PB2:
pmu_write_time(now);
break;
+#endif
+ default:
+ return -ENODEV;
}
}
return 0;
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index e85acd131fa8..8827b7f91402 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -120,32 +120,6 @@ void free_initmem(void)
#define VECTORS _ramvec
#endif
-void __init print_memmap(void)
-{
-#define UL(x) ((unsigned long) (x))
-#define MLK(b, t) UL(b), UL(t), (UL(t) - UL(b)) >> 10
-#define MLM(b, t) UL(b), UL(t), (UL(t) - UL(b)) >> 20
-#define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), 1024)
-
- pr_notice("Virtual kernel memory layout:\n"
- " vector : 0x%08lx - 0x%08lx (%4ld KiB)\n"
- " kmap : 0x%08lx - 0x%08lx (%4ld MiB)\n"
- " vmalloc : 0x%08lx - 0x%08lx (%4ld MiB)\n"
- " lowmem : 0x%08lx - 0x%08lx (%4ld MiB)\n"
- " .init : 0x%p" " - 0x%p" " (%4d KiB)\n"
- " .text : 0x%p" " - 0x%p" " (%4d KiB)\n"
- " .data : 0x%p" " - 0x%p" " (%4d KiB)\n"
- " .bss : 0x%p" " - 0x%p" " (%4d KiB)\n",
- MLK(VECTORS, VECTORS + 256),
- MLM(KMAP_START, KMAP_END),
- MLM(VMALLOC_START, VMALLOC_END),
- MLM(PAGE_OFFSET, (unsigned long)high_memory),
- MLK_ROUNDUP(__init_begin, __init_end),
- MLK_ROUNDUP(_stext, _etext),
- MLK_ROUNDUP(_sdata, _edata),
- MLK_ROUNDUP(__bss_start, __bss_stop));
-}
-
static inline void init_pointer_tables(void)
{
#if defined(CONFIG_MMU) && !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
@@ -170,7 +144,6 @@ void __init mem_init(void)
free_all_bootmem();
init_pointer_tables();
mem_init_print_info(NULL);
- print_memmap();
}
#ifdef CONFIG_BLK_DEV_INITRD
diff --git a/arch/metag/Kconfig b/arch/metag/Kconfig
deleted file mode 100644
index c7b62a339539..000000000000
--- a/arch/metag/Kconfig
+++ /dev/null
@@ -1,287 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config METAG
- def_bool y
- select EMBEDDED
- select GENERIC_ATOMIC64
- select GENERIC_CLOCKEVENTS
- select GENERIC_IRQ_SHOW
- select GENERIC_SMP_IDLE_THREAD
- select HAVE_64BIT_ALIGNED_ACCESS
- select HAVE_ARCH_TRACEHOOK
- select HAVE_C_RECORDMCOUNT
- select HAVE_DEBUG_KMEMLEAK
- select HAVE_DEBUG_STACKOVERFLOW
- select HAVE_DYNAMIC_FTRACE
- select HAVE_EXIT_THREAD
- select HAVE_FTRACE_MCOUNT_RECORD
- select HAVE_FUNCTION_TRACER
- select HAVE_KERNEL_BZIP2
- select HAVE_KERNEL_GZIP
- select HAVE_KERNEL_LZO
- select HAVE_KERNEL_XZ
- select HAVE_MEMBLOCK
- select HAVE_MEMBLOCK_NODE_MAP
- select HAVE_MOD_ARCH_SPECIFIC
- select HAVE_OPROFILE
- select HAVE_PERF_EVENTS
- select HAVE_SYSCALL_TRACEPOINTS
- select HAVE_UNDERSCORE_SYMBOL_PREFIX
- select IRQ_DOMAIN
- select GENERIC_IRQ_EFFECTIVE_AFF_MASK
- select MODULES_USE_ELF_RELA
- select OF
- select OF_EARLY_FLATTREE
- select SPARSE_IRQ
- select CPU_NO_EFFICIENT_FFS
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-config LOCKDEP_SUPPORT
- def_bool y
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
-
-config GENERIC_HWEIGHT
- def_bool y
-
-config GENERIC_CALIBRATE_DELAY
- def_bool y
-
-config NO_IOPORT_MAP
- def_bool y
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-menu "Processor type and features"
-
-config MMU
- def_bool y
-
-config STACK_GROWSUP
- def_bool y
-
-config HOTPLUG_CPU
- bool "Enable CPU hotplug support"
- depends on SMP
- help
- Say Y here to allow turning CPUs off and on. CPUs can be
- controlled through /sys/devices/system/cpu.
-
- Say N if you want to disable CPU hotplug.
-
-config HIGHMEM
- bool "High Memory Support"
- help
- The address space of Meta processors is only 4 Gigabytes large
- and it has to accommodate user address space, kernel address
- space as well as some memory mapped IO. That means that, if you
- have a large amount of physical memory and/or IO, not all of the
- memory can be "permanently mapped" by the kernel. The physical
- memory that is not permanently mapped is called "high memory".
-
- Depending on the selected kernel/user memory split, minimum
- vmalloc space and actual amount of RAM, you may not need this
- option which should result in a slightly faster kernel.
-
- If unsure, say n.
-
-source "arch/metag/mm/Kconfig"
-
-source "arch/metag/Kconfig.soc"
-
-config METAG_META12
- bool
- help
- Select this from the SoC config symbol to indicate that it contains a
- Meta 1.2 core.
-
-config METAG_META21
- bool
- help
- Select this from the SoC config symbol to indicate that it contains a
- Meta 2.1 core.
-
-config SMP
- bool "Symmetric multi-processing support"
- depends on METAG_META21 && METAG_META21_MMU
- help
- This enables support for systems with more than one thread running
- Linux. If you have a system with only one thread running Linux,
- say N. Otherwise, say Y.
-
-config NR_CPUS
- int "Maximum number of CPUs (2-4)" if SMP
- range 2 4 if SMP
- default "1" if !SMP
- default "4" if SMP
-
-config METAG_SMP_WRITE_REORDERING
- bool
- help
- This attempts to prevent cache-memory incoherence due to external
- reordering of writes from different hardware threads when SMP is
- enabled. It adds fences (system event 0) to smp_mb and smp_rmb in an
- attempt to catch some of the cases, and also before writes to shared
- memory in LOCK1 protected atomics and spinlocks.
- This will not completely prevent cache incoherency on affected cores.
-
-config METAG_LNKGET_AROUND_CACHE
- bool
- depends on METAG_META21
- help
- This indicates that the LNKGET/LNKSET instructions go around the
- cache, which requires some extra cache flushes when the memory needs
- to be accessed by normal GET/SET instructions too.
-
-choice
- prompt "Atomicity primitive"
- default METAG_ATOMICITY_LNKGET
- help
- This option selects the mechanism for performing atomic operations.
-
-config METAG_ATOMICITY_IRQSOFF
- depends on !SMP
- bool "irqsoff"
- help
- This option disables interrupts to achieve atomicity. This mechanism
- is not SMP-safe.
-
-config METAG_ATOMICITY_LNKGET
- depends on METAG_META21
- bool "lnkget/lnkset"
- help
- This option uses the LNKGET and LNKSET instructions to achieve
- atomicity. LNKGET/LNKSET are load-link/store-conditional instructions.
- Choose this option if your system requires low latency.
-
-config METAG_ATOMICITY_LOCK1
- depends on SMP
- bool "lock1"
- help
- This option uses the LOCK1 instruction for atomicity. This is mainly
- provided as a debugging aid if the lnkget/lnkset atomicity primitive
- isn't working properly.
-
-endchoice
-
-config METAG_FPU
- bool "FPU Support"
- depends on METAG_META21
- default y
- help
- This option allows processes to use FPU hardware available with this
- CPU. If this option is not enabled FPU registers will not be saved
- and restored on context-switch.
-
- If you plan on running programs which are compiled to use hard floats
- say Y here.
-
-config METAG_DSP
- bool "DSP Support"
- help
- This option allows processes to use DSP hardware available
- with this CPU. If this option is not enabled DSP registers
- will not be saved and restored on context-switch.
-
- If you plan on running DSP programs say Y here.
-
-config METAG_PERFCOUNTER_IRQS
- bool "PerfCounters interrupt support"
- depends on METAG_META21
- help
- This option enables using interrupts to collect information from
- Performance Counters. This option is supported in new META21
- (starting from HTP265).
-
- When disabled, Performance Counters information will be collected
- based on Timer Interrupt.
-
-config HW_PERF_EVENTS
- def_bool METAG_PERFCOUNTER_IRQS && PERF_EVENTS
-
-config METAG_DA
- bool "DA support"
- help
- Say Y if you plan to use a DA debug adapter with Linux. The presence
- of the DA will be detected automatically at boot, so it is safe to say
- Y to this option even when booting without a DA.
-
- This enables support for services provided by DA JTAG debug adapters,
- such as:
- - communication over DA channels (such as the console driver).
- - use of the DA filesystem.
-
-menu "Boot options"
-
-config METAG_BUILTIN_DTB
- bool "Embed DTB in kernel image"
- default y
- help
- Embeds a device tree binary in the kernel image.
-
-config METAG_BUILTIN_DTB_NAME
- string "Built in DTB"
- depends on METAG_BUILTIN_DTB
- help
- Set the name of the DTB to embed (leave blank to pick one
- automatically based on kernel configuration).
-
-config CMDLINE_BOOL
- bool "Default bootloader kernel arguments"
-
-config CMDLINE
- string "Kernel command line"
- depends on CMDLINE_BOOL
- help
- On some architectures there is currently no way for the boot loader
- to pass arguments to the kernel. For these architectures, you should
- supply some command-line options at build time by entering them
- here.
-
-config CMDLINE_FORCE
- bool "Force default kernel command string"
- depends on CMDLINE_BOOL
- help
- Set this to have arguments from the default kernel command string
- override those passed by the boot loader.
-
-endmenu
-
-source "kernel/Kconfig.preempt"
-
-source kernel/Kconfig.hz
-
-endmenu
-
-menu "Power management options"
-
-source kernel/power/Kconfig
-
-endmenu
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/metag/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/metag/Kconfig.debug b/arch/metag/Kconfig.debug
deleted file mode 100644
index ac4516c605db..000000000000
--- a/arch/metag/Kconfig.debug
+++ /dev/null
@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-config TRACE_IRQFLAGS_SUPPORT
- bool
- default y
-
-source "lib/Kconfig.debug"
-
-config 4KSTACKS
- bool "Use 4Kb for kernel stacks instead of 8Kb"
- depends on DEBUG_KERNEL
- help
- If you say Y here the kernel will use a 4Kb stacksize for the
- kernel stack attached to each process/thread. This facilitates
- running more threads on a system and also reduces the pressure
- on the VM subsystem for higher order allocations. This option
- will also use IRQ stacks to compensate for the reduced stackspace.
-
-config METAG_FUNCTION_TRACE
- bool "Output Meta real-time trace data for function entry/exit"
- help
- If you say Y here the kernel will use the Meta hardware trace
- unit to output information about function entry and exit that
- can be used by a debugger for profiling and call-graphs.
-
-config METAG_POISON_CATCH_BUFFERS
- bool "Poison catch buffer contents on kernel entry"
- help
- If you say Y here the kernel will write poison data to the
- catch buffer registers on kernel entry. This will make any
- problem with catch buffer handling much more apparent.
-
-endmenu
diff --git a/arch/metag/Kconfig.soc b/arch/metag/Kconfig.soc
deleted file mode 100644
index c521f0e00d8e..000000000000
--- a/arch/metag/Kconfig.soc
+++ /dev/null
@@ -1,69 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-choice
- prompt "SoC Type"
- default META21_FPGA
-
-config META12_FPGA
- bool "Meta 1.2 FPGA"
- select METAG_META12
- help
- This is a Meta 1.2 FPGA bitstream, just a bare CPU.
-
-config META21_FPGA
- bool "Meta 2.1 FPGA"
- select METAG_META21
- help
- This is a Meta 2.1 FPGA bitstream, just a bare CPU.
-
-config SOC_TZ1090
- bool "Toumaz Xenif TZ1090 SoC (Comet)"
- select IMGPDC_IRQ
- select METAG_LNKGET_AROUND_CACHE
- select METAG_META21
- select METAG_SMP_WRITE_REORDERING
- select PINCTRL
- select PINCTRL_TZ1090
- select PINCTRL_TZ1090_PDC
- help
- This is a Toumaz Technology Xenif TZ1090 (A.K.A. Comet) SoC containing
- a 2-threaded HTP.
-
-endchoice
-
-menu "SoC configuration"
-
-if METAG_META21
-
-# Meta 2.x specific options
-
-config METAG_META21_MMU
- bool "Meta 2.x MMU mode"
- default y
- help
- Use the Meta 2.x MMU in extended mode.
-
-config METAG_UNALIGNED
- bool "Meta 2.x unaligned access checking"
- default y
- help
- All memory accesses will be checked for alignment and an exception
- raised on unaligned accesses. This feature does cost performance
- but without it there will be no notification of this type of error.
-
-config METAG_USER_TCM
- bool "Meta on-chip memory support for userland"
- select GENERIC_ALLOCATOR
- default y
- help
- Allow the on-chip memories of Meta SoCs to be used by user
- applications.
-
-endif
-
-config METAG_HALT_ON_PANIC
- bool "Halt the core on panic"
- help
- Halt the core when a panic occurs. This is useful when running
- pre-production silicon or in an FPGA environment.
-
-endmenu
diff --git a/arch/metag/Makefile b/arch/metag/Makefile
deleted file mode 100644
index 033a58214119..000000000000
--- a/arch/metag/Makefile
+++ /dev/null
@@ -1,89 +0,0 @@
-#
-# metag/Makefile
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies. Remember to do have actions
-# for "archclean" cleaning up for this architecture.
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1994 by Linus Torvalds
-# 2007,2008,2012 by Imagination Technologies Ltd.
-#
-
-LDFLAGS :=
-OBJCOPYFLAGS := -O binary -R .note -R .comment -S
-
-checkflags-$(CONFIG_METAG_META12) += -DMETAC_1_2
-checkflags-$(CONFIG_METAG_META21) += -DMETAC_2_1
-CHECKFLAGS += -D__metag__ $(checkflags-y)
-
-KBUILD_DEFCONFIG := tz1090_defconfig
-
-sflags-$(CONFIG_METAG_META12) += -mmetac=1.2
-ifeq ($(CONFIG_METAG_META12),y)
-# Only use TBI API 1.4 if DSP is enabled for META12 cores
-sflags-$(CONFIG_METAG_DSP) += -DTBI_1_4
-endif
-sflags-$(CONFIG_METAG_META21) += -mmetac=2.1 -DTBI_1_4
-
-cflags-$(CONFIG_METAG_FUNCTION_TRACE) += -mhwtrace-leaf -mhwtrace-retpc
-cflags-$(CONFIG_METAG_META21) += -mextensions=bex
-
-KBUILD_CFLAGS += -pipe
-KBUILD_CFLAGS += -ffunction-sections
-
-KBUILD_CFLAGS += $(sflags-y) $(cflags-y)
-KBUILD_AFLAGS += $(sflags-y)
-
-LDFLAGS_vmlinux := $(ldflags-y)
-
-head-y := arch/metag/kernel/head.o
-
-core-y += arch/metag/boot/dts/
-core-y += arch/metag/kernel/
-core-y += arch/metag/mm/
-
-libs-y += arch/metag/lib/
-libs-y += arch/metag/tbx/
-
-drivers-$(CONFIG_OPROFILE) += arch/metag/oprofile/
-
-boot := arch/metag/boot
-
-boot_targets += uImage
-boot_targets += uImage.gz
-boot_targets += uImage.bz2
-boot_targets += uImage.xz
-boot_targets += uImage.lzo
-boot_targets += uImage.bin
-boot_targets += vmlinux.bin
-
-PHONY += $(boot_targets)
-
-all: vmlinux.bin
-
-$(boot_targets): vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-%.dtb %.dtb.S %.dtb.o: scripts
- $(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@
-
-dtbs: scripts
- $(Q)$(MAKE) $(build)=$(boot)/dts
-
-archclean:
- $(Q)$(MAKE) $(clean)=$(boot)
-
-define archhelp
- echo '* vmlinux.bin - Binary kernel image (arch/$(ARCH)/boot/vmlinux.bin)'
- @echo ' uImage - Alias to bootable U-Boot image'
- @echo ' uImage.bin - Kernel-only image for U-Boot (bin)'
- @echo ' uImage.gz - Kernel-only image for U-Boot (gzip)'
- @echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)'
- @echo ' uImage.xz - Kernel-only image for U-Boot (xz)'
- @echo ' uImage.lzo - Kernel-only image for U-Boot (lzo)'
- @echo ' dtbs - Build device tree blobs for enabled boards'
-endef
diff --git a/arch/metag/boot/.gitignore b/arch/metag/boot/.gitignore
deleted file mode 100644
index 6c662ddb909a..000000000000
--- a/arch/metag/boot/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-vmlinux*
-uImage*
-ramdisk.*
diff --git a/arch/metag/boot/Makefile b/arch/metag/boot/Makefile
deleted file mode 100644
index 5a1f88cf91e3..000000000000
--- a/arch/metag/boot/Makefile
+++ /dev/null
@@ -1,68 +0,0 @@
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2007,2012 Imagination Technologies Ltd.
-#
-
-suffix-y := bin
-suffix-$(CONFIG_KERNEL_GZIP) := gz
-suffix-$(CONFIG_KERNEL_BZIP2) := bz2
-suffix-$(CONFIG_KERNEL_XZ) := xz
-suffix-$(CONFIG_KERNEL_LZO) := lzo
-
-targets += vmlinux.bin
-targets += uImage
-targets += uImage.gz
-targets += uImage.bz2
-targets += uImage.xz
-targets += uImage.lzo
-targets += uImage.bin
-
-extra-y += vmlinux.bin
-extra-y += vmlinux.bin.gz
-extra-y += vmlinux.bin.bz2
-extra-y += vmlinux.bin.xz
-extra-y += vmlinux.bin.lzo
-
-UIMAGE_LOADADDR = $(CONFIG_PAGE_OFFSET)
-
-ifeq ($(CONFIG_FUNCTION_TRACER),y)
-orig_cflags := $(KBUILD_CFLAGS)
-KBUILD_CFLAGS = $(subst -pg, , $(orig_cflags))
-endif
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
- $(call if_changed,bzip2)
-
-$(obj)/vmlinux.bin.xz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,xzkern)
-
-$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
- $(call if_changed,lzo)
-
-$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
- $(call if_changed,uimage,gzip)
-
-$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 FORCE
- $(call if_changed,uimage,bzip2)
-
-$(obj)/uImage.xz: $(obj)/vmlinux.bin.xz FORCE
- $(call if_changed,uimage,xz)
-
-$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE
- $(call if_changed,uimage,lzo)
-
-$(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE
- $(call if_changed,uimage,none)
-
-$(obj)/uImage: $(obj)/uImage.$(suffix-y)
- @ln -sf $(notdir $<) $@
- @echo ' Image $@ is ready'
diff --git a/arch/metag/boot/dts/Makefile b/arch/metag/boot/dts/Makefile
deleted file mode 100644
index f0a180f62766..000000000000
--- a/arch/metag/boot/dts/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-dtb-y += skeleton.dtb
-dtb-y += tz1090_generic.dtb
-
-# Built-in dtb
-builtindtb-y := skeleton
-builtindtb-$(CONFIG_SOC_TZ1090) := tz1090_generic
-
-ifneq ($(CONFIG_METAG_BUILTIN_DTB_NAME),"")
- builtindtb-y := $(patsubst "%",%,$(CONFIG_METAG_BUILTIN_DTB_NAME))
-endif
-
-dtb-$(CONFIG_METAG_BUILTIN_DTB) += $(builtindtb-y).dtb
-obj-$(CONFIG_METAG_BUILTIN_DTB) += $(builtindtb-y).dtb.o
-
-.SECONDARY: $(obj)/$(builtindtb-y).dtb.S
diff --git a/arch/metag/boot/dts/skeleton.dts b/arch/metag/boot/dts/skeleton.dts
deleted file mode 100644
index 7a49aeb365d0..000000000000
--- a/arch/metag/boot/dts/skeleton.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include "skeleton.dtsi"
diff --git a/arch/metag/boot/dts/skeleton.dtsi b/arch/metag/boot/dts/skeleton.dtsi
deleted file mode 100644
index 43e2ffe73c27..000000000000
--- a/arch/metag/boot/dts/skeleton.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Skeleton device tree; the bare minimum needed to boot; just include and
- * add a compatible value. The bootloader will typically populate the memory
- * node.
- */
-
-/ {
- compatible = "img,meta";
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
- aliases { };
- memory { device_type = "memory"; reg = <0 0>; };
-};
diff --git a/arch/metag/boot/dts/tz1090.dtsi b/arch/metag/boot/dts/tz1090.dtsi
deleted file mode 100644
index 24ea7d2e9138..000000000000
--- a/arch/metag/boot/dts/tz1090.dtsi
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include "skeleton.dtsi"
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- compatible = "toumaz,tz1090", "img,meta";
-
- interrupt-parent = <&intc>;
-
- intc: interrupt-controller {
- compatible = "img,meta-intc";
- interrupt-controller;
- #interrupt-cells = <2>;
- num-banks = <2>;
- };
-
- soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdc: pdc@0x02006000 {
- interrupt-controller;
- #interrupt-cells = <2>;
-
- reg = <0x02006000 0x1000>;
- compatible = "img,pdc-intc";
-
- num-perips = <3>;
- num-syswakes = <3>;
-
- interrupts = <18 IRQ_TYPE_LEVEL_HIGH>, /* Syswakes */
- <30 IRQ_TYPE_LEVEL_HIGH>, /* Perip 0 (RTC) */
- <29 IRQ_TYPE_LEVEL_HIGH>, /* Perip 1 (IR) */
- <31 IRQ_TYPE_LEVEL_HIGH>; /* Perip 2 (WDT) */
- };
-
- pinctrl: pinctrl@02005800 {
- #gpio-range-cells = <3>;
- compatible = "img,tz1090-pinctrl";
- reg = <0x02005800 0xe4>;
- };
-
- pdc_pinctrl: pinctrl@02006500 {
- #gpio-range-cells = <3>;
- compatible = "img,tz1090-pdc-pinctrl";
- reg = <0x02006500 0x100>;
- };
-
- gpios: gpios@02005800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "img,tz1090-gpio";
- reg = <0x02005800 0x90>;
-
- gpios0: bank@0 {
- gpio-controller;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- reg = <0>;
- interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
- gpio-ranges = <&pinctrl 0 0 30>;
- };
- gpios1: bank@1 {
- gpio-controller;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- reg = <1>;
- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
- gpio-ranges = <&pinctrl 0 30 30>;
- };
- gpios2: bank@2 {
- gpio-controller;
- interrupt-controller;
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- reg = <2>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
- gpio-ranges = <&pinctrl 0 60 30>;
- };
- };
-
- pdc_gpios: gpios@02006500 {
- gpio-controller;
- #gpio-cells = <2>;
-
- compatible = "img,tz1090-pdc-gpio";
- reg = <0x02006500 0x100>;
-
- interrupt-parent = <&pdc>;
- interrupts = <8 IRQ_TYPE_NONE>,
- <9 IRQ_TYPE_NONE>,
- <10 IRQ_TYPE_NONE>;
- gpio-ranges = <&pdc_pinctrl 0 0 7>;
- };
- };
-};
diff --git a/arch/metag/boot/dts/tz1090_generic.dts b/arch/metag/boot/dts/tz1090_generic.dts
deleted file mode 100644
index f96090955964..000000000000
--- a/arch/metag/boot/dts/tz1090_generic.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-#include "tz1090.dtsi"
diff --git a/arch/metag/configs/meta1_defconfig b/arch/metag/configs/meta1_defconfig
deleted file mode 100644
index 01cd67e4403d..000000000000
--- a/arch/metag/configs/meta1_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_META12_FPGA=y
-CONFIG_METAG_DA=y
-CONFIG_HZ_100=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_DA_TTY=y
-CONFIG_DA_CONSOLE=y
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_INFO=y
diff --git a/arch/metag/configs/meta2_defconfig b/arch/metag/configs/meta2_defconfig
deleted file mode 100644
index 643392ba7ed5..000000000000
--- a/arch/metag/configs/meta2_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_METAG_L2C=y
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_METAG_HALT_ON_PANIC=y
-CONFIG_METAG_DA=y
-CONFIG_HZ_100=y
-CONFIG_DEVTMPFS=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_DA_TTY=y
-CONFIG_DA_CONSOLE=y
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_INFO=y
diff --git a/arch/metag/configs/meta2_smp_defconfig b/arch/metag/configs/meta2_smp_defconfig
deleted file mode 100644
index f3306737da20..000000000000
--- a/arch/metag/configs/meta2_smp_defconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_METAG_L2C=y
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_METAG_HALT_ON_PANIC=y
-CONFIG_SMP=y
-CONFIG_METAG_DA=y
-CONFIG_HZ_100=y
-CONFIG_DEVTMPFS=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_DA_TTY=y
-CONFIG_DA_CONSOLE=y
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_INFO=y
diff --git a/arch/metag/configs/tz1090_defconfig b/arch/metag/configs/tz1090_defconfig
deleted file mode 100644
index 9f9316a6df27..000000000000
--- a/arch/metag/configs/tz1090_defconfig
+++ /dev/null
@@ -1,42 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_ELF_CORE is not set
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_SOC_TZ1090=y
-CONFIG_METAG_HALT_ON_PANIC=y
-# CONFIG_METAG_FPU is not set
-CONFIG_METAG_DA=y
-CONFIG_HZ_100=y
-CONFIG_DEVTMPFS=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_DA_TTY=y
-CONFIG_DA_CONSOLE=y
-# CONFIG_DEVKMEM is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_GPIOLIB=y
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_INFO=y
diff --git a/arch/metag/include/asm/Kbuild b/arch/metag/include/asm/Kbuild
deleted file mode 100644
index 913c779979df..000000000000
--- a/arch/metag/include/asm/Kbuild
+++ /dev/null
@@ -1,33 +0,0 @@
-generic-y += bugs.h
-generic-y += current.h
-generic-y += device.h
-generic-y += dma.h
-generic-y += emergency-restart.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += futex.h
-generic-y += hardirq.h
-generic-y += hw_irq.h
-generic-y += irq_regs.h
-generic-y += irq_work.h
-generic-y += kdebug.h
-generic-y += kmap_types.h
-generic-y += kprobes.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += pci.h
-generic-y += percpu.h
-generic-y += preempt.h
-generic-y += sections.h
-generic-y += serial.h
-generic-y += switch_to.h
-generic-y += timex.h
-generic-y += trace_clock.h
-generic-y += unaligned.h
-generic-y += user.h
-generic-y += vga.h
-generic-y += word-at-a-time.h
-generic-y += xor.h
diff --git a/arch/metag/include/asm/atomic.h b/arch/metag/include/asm/atomic.h
deleted file mode 100644
index 97ae189c2dd8..000000000000
--- a/arch/metag/include/asm/atomic.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_ATOMIC_H
-#define __ASM_METAG_ATOMIC_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <asm/cmpxchg.h>
-#include <asm/barrier.h>
-
-#if defined(CONFIG_METAG_ATOMICITY_IRQSOFF)
-/* The simple UP case. */
-#include <asm-generic/atomic.h>
-#else
-
-#if defined(CONFIG_METAG_ATOMICITY_LOCK1)
-#include <asm/atomic_lock1.h>
-#else
-#include <asm/atomic_lnkget.h>
-#endif
-
-#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
-
-#define atomic_dec_return(v) atomic_sub_return(1, (v))
-#define atomic_inc_return(v) atomic_add_return(1, (v))
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-
-#define atomic_inc(v) atomic_add(1, (v))
-#define atomic_dec(v) atomic_sub(1, (v))
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
-
-#endif
-
-#include <asm-generic/atomic64.h>
-
-#endif /* __ASM_METAG_ATOMIC_H */
diff --git a/arch/metag/include/asm/atomic_lnkget.h b/arch/metag/include/asm/atomic_lnkget.h
deleted file mode 100644
index 17e8c61c946d..000000000000
--- a/arch/metag/include/asm/atomic_lnkget.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_ATOMIC_LNKGET_H
-#define __ASM_METAG_ATOMIC_LNKGET_H
-
-#define ATOMIC_INIT(i) { (i) }
-
-#define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
-
-#include <linux/compiler.h>
-
-#include <asm/barrier.h>
-
-/*
- * None of these asm statements clobber memory as LNKSET writes around
- * the cache so the memory it modifies cannot safely be read by any means
- * other than these accessors.
- */
-
-static inline int atomic_read(const atomic_t *v)
-{
- int temp;
-
- asm volatile (
- "LNKGETD %0, [%1]\n"
- : "=da" (temp)
- : "da" (&v->counter));
-
- return temp;
-}
-
-#define ATOMIC_OP(op) \
-static inline void atomic_##op(int i, atomic_t *v) \
-{ \
- int temp; \
- \
- asm volatile ( \
- "1: LNKGETD %0, [%1]\n" \
- " " #op " %0, %0, %2\n" \
- " LNKSETD [%1], %0\n" \
- " DEFR %0, TXSTAT\n" \
- " ANDT %0, %0, #HI(0x3f000000)\n" \
- " CMPT %0, #HI(0x02000000)\n" \
- " BNZ 1b\n" \
- : "=&d" (temp) \
- : "da" (&v->counter), "bd" (i) \
- : "cc"); \
-} \
-
-#define ATOMIC_OP_RETURN(op) \
-static inline int atomic_##op##_return(int i, atomic_t *v) \
-{ \
- int result, temp; \
- \
- smp_mb(); \
- \
- asm volatile ( \
- "1: LNKGETD %1, [%2]\n" \
- " " #op " %1, %1, %3\n" \
- " LNKSETD [%2], %1\n" \
- " DEFR %0, TXSTAT\n" \
- " ANDT %0, %0, #HI(0x3f000000)\n" \
- " CMPT %0, #HI(0x02000000)\n" \
- " BNZ 1b\n" \
- : "=&d" (temp), "=&da" (result) \
- : "da" (&v->counter), "br" (i) \
- : "cc"); \
- \
- smp_mb(); \
- \
- return result; \
-}
-
-#define ATOMIC_FETCH_OP(op) \
-static inline int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- int result, temp; \
- \
- smp_mb(); \
- \
- asm volatile ( \
- "1: LNKGETD %1, [%2]\n" \
- " " #op " %0, %1, %3\n" \
- " LNKSETD [%2], %0\n" \
- " DEFR %0, TXSTAT\n" \
- " ANDT %0, %0, #HI(0x3f000000)\n" \
- " CMPT %0, #HI(0x02000000)\n" \
- " BNZ 1b\n" \
- : "=&d" (temp), "=&d" (result) \
- : "da" (&v->counter), "bd" (i) \
- : "cc"); \
- \
- smp_mb(); \
- \
- return result; \
-}
-
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(add)
-ATOMIC_OPS(sub)
-
-#undef ATOMIC_OPS
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(and)
-ATOMIC_OPS(or)
-ATOMIC_OPS(xor)
-
-#undef ATOMIC_OPS
-#undef ATOMIC_FETCH_OP
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
-
-static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
-{
- int result, temp;
-
- smp_mb();
-
- asm volatile (
- "1: LNKGETD %1, [%2]\n"
- " CMP %1, %3\n"
- " LNKSETDEQ [%2], %4\n"
- " BNE 2f\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- "2:\n"
- : "=&d" (temp), "=&d" (result)
- : "da" (&v->counter), "bd" (old), "da" (new)
- : "cc");
-
- smp_mb();
-
- return result;
-}
-
-static inline int atomic_xchg(atomic_t *v, int new)
-{
- int temp, old;
-
- asm volatile (
- "1: LNKGETD %1, [%2]\n"
- " LNKSETD [%2], %3\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- : "=&d" (temp), "=&d" (old)
- : "da" (&v->counter), "da" (new)
- : "cc");
-
- return old;
-}
-
-static inline int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- int result, temp;
-
- smp_mb();
-
- asm volatile (
- "1: LNKGETD %1, [%2]\n"
- " CMP %1, %3\n"
- " ADD %0, %1, %4\n"
- " LNKSETDNE [%2], %0\n"
- " BEQ 2f\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- "2:\n"
- : "=&d" (temp), "=&d" (result)
- : "da" (&v->counter), "bd" (u), "bd" (a)
- : "cc");
-
- smp_mb();
-
- return result;
-}
-
-static inline int atomic_sub_if_positive(int i, atomic_t *v)
-{
- int result, temp;
-
- asm volatile (
- "1: LNKGETD %1, [%2]\n"
- " SUBS %1, %1, %3\n"
- " LNKSETDGE [%2], %1\n"
- " BLT 2f\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- "2:\n"
- : "=&d" (temp), "=&da" (result)
- : "da" (&v->counter), "bd" (i)
- : "cc");
-
- return result;
-}
-
-#endif /* __ASM_METAG_ATOMIC_LNKGET_H */
diff --git a/arch/metag/include/asm/atomic_lock1.h b/arch/metag/include/asm/atomic_lock1.h
deleted file mode 100644
index 2ce8fa3a79c2..000000000000
--- a/arch/metag/include/asm/atomic_lock1.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_ATOMIC_LOCK1_H
-#define __ASM_METAG_ATOMIC_LOCK1_H
-
-#define ATOMIC_INIT(i) { (i) }
-
-#include <linux/compiler.h>
-
-#include <asm/barrier.h>
-#include <asm/global_lock.h>
-
-static inline int atomic_read(const atomic_t *v)
-{
- return READ_ONCE((v)->counter);
-}
-
-/*
- * atomic_set needs to be take the lock to protect atomic_add_unless from a
- * possible race, as it reads the counter twice:
- *
- * CPU0 CPU1
- * atomic_add_unless(1, 0)
- * ret = v->counter (non-zero)
- * if (ret != u) v->counter = 0
- * v->counter += 1 (counter set to 1)
- *
- * Making atomic_set take the lock ensures that ordering and logical
- * consistency is preserved.
- */
-static inline int atomic_set(atomic_t *v, int i)
-{
- unsigned long flags;
-
- __global_lock1(flags);
- fence();
- v->counter = i;
- __global_unlock1(flags);
- return i;
-}
-
-#define atomic_set_release(v, i) atomic_set((v), (i))
-
-#define ATOMIC_OP(op, c_op) \
-static inline void atomic_##op(int i, atomic_t *v) \
-{ \
- unsigned long flags; \
- \
- __global_lock1(flags); \
- fence(); \
- v->counter c_op i; \
- __global_unlock1(flags); \
-} \
-
-#define ATOMIC_OP_RETURN(op, c_op) \
-static inline int atomic_##op##_return(int i, atomic_t *v) \
-{ \
- unsigned long result; \
- unsigned long flags; \
- \
- __global_lock1(flags); \
- result = v->counter; \
- result c_op i; \
- fence(); \
- v->counter = result; \
- __global_unlock1(flags); \
- \
- return result; \
-}
-
-#define ATOMIC_FETCH_OP(op, c_op) \
-static inline int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- unsigned long result; \
- unsigned long flags; \
- \
- __global_lock1(flags); \
- result = v->counter; \
- fence(); \
- v->counter c_op i; \
- __global_unlock1(flags); \
- \
- return result; \
-}
-
-#define ATOMIC_OPS(op, c_op) \
- ATOMIC_OP(op, c_op) \
- ATOMIC_OP_RETURN(op, c_op) \
- ATOMIC_FETCH_OP(op, c_op)
-
-ATOMIC_OPS(add, +=)
-ATOMIC_OPS(sub, -=)
-
-#undef ATOMIC_OPS
-#define ATOMIC_OPS(op, c_op) \
- ATOMIC_OP(op, c_op) \
- ATOMIC_FETCH_OP(op, c_op)
-
-ATOMIC_OPS(and, &=)
-ATOMIC_OPS(or, |=)
-ATOMIC_OPS(xor, ^=)
-
-#undef ATOMIC_OPS
-#undef ATOMIC_FETCH_OP
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
-
-static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
-{
- int ret;
- unsigned long flags;
-
- __global_lock1(flags);
- ret = v->counter;
- if (ret == old) {
- fence();
- v->counter = new;
- }
- __global_unlock1(flags);
-
- return ret;
-}
-
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-static inline int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- int ret;
- unsigned long flags;
-
- __global_lock1(flags);
- ret = v->counter;
- if (ret != u) {
- fence();
- v->counter += a;
- }
- __global_unlock1(flags);
-
- return ret;
-}
-
-static inline int atomic_sub_if_positive(int i, atomic_t *v)
-{
- int ret;
- unsigned long flags;
-
- __global_lock1(flags);
- ret = v->counter - 1;
- if (ret >= 0) {
- fence();
- v->counter = ret;
- }
- __global_unlock1(flags);
-
- return ret;
-}
-
-#endif /* __ASM_METAG_ATOMIC_LOCK1_H */
diff --git a/arch/metag/include/asm/barrier.h b/arch/metag/include/asm/barrier.h
deleted file mode 100644
index 2661fec5696a..000000000000
--- a/arch/metag/include/asm/barrier.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_BARRIER_H
-#define _ASM_METAG_BARRIER_H
-
-#include <asm/metag_mem.h>
-
-#define nop() asm volatile ("NOP")
-
-#ifdef CONFIG_METAG_META21
-
-/* HTP and above have a system event to fence writes */
-static inline void wr_fence(void)
-{
- volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_FENCE;
- barrier();
- *flushptr = 0;
- barrier();
-}
-
-#else /* CONFIG_METAG_META21 */
-
-/*
- * ATP doesn't have system event to fence writes, so it is necessary to flush
- * the processor write queues as well as possibly the write combiner (depending
- * on the page being written).
- * To ensure the write queues are flushed we do 4 writes to a system event
- * register (in this case write combiner flush) which will also flush the write
- * combiner.
- */
-static inline void wr_fence(void)
-{
- volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_COMBINE_FLUSH;
- barrier();
- *flushptr = 0;
- *flushptr = 0;
- *flushptr = 0;
- *flushptr = 0;
- barrier();
-}
-
-#endif /* !CONFIG_METAG_META21 */
-
-/* flush writes through the write combiner */
-#define mb() wr_fence()
-#define rmb() barrier()
-#define wmb() mb()
-
-#ifdef CONFIG_METAG_SMP_WRITE_REORDERING
-/*
- * Write to the atomic memory unlock system event register (command 0). This is
- * needed before a write to shared memory in a critical section, to prevent
- * external reordering of writes before the fence on other threads with writes
- * after the fence on this thread (and to prevent the ensuing cache-memory
- * incoherence). It is therefore ineffective if used after and on the same
- * thread as a write.
- */
-static inline void metag_fence(void)
-{
- volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_ATOMIC_UNLOCK;
- barrier();
- *flushptr = 0;
- barrier();
-}
-#define __smp_mb() metag_fence()
-#define __smp_rmb() metag_fence()
-#define __smp_wmb() barrier()
-#else
-#define metag_fence() do { } while (0)
-#define __smp_mb() barrier()
-#define __smp_rmb() barrier()
-#define __smp_wmb() barrier()
-#endif
-
-#ifdef CONFIG_SMP
-#define fence() metag_fence()
-#else
-#define fence() do { } while (0)
-#endif
-
-#define __smp_mb__before_atomic() barrier()
-#define __smp_mb__after_atomic() barrier()
-
-#include <asm-generic/barrier.h>
-
-#endif /* _ASM_METAG_BARRIER_H */
diff --git a/arch/metag/include/asm/bitops.h b/arch/metag/include/asm/bitops.h
deleted file mode 100644
index 766ad43010ad..000000000000
--- a/arch/metag/include/asm/bitops.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_BITOPS_H
-#define __ASM_METAG_BITOPS_H
-
-#include <linux/compiler.h>
-#include <asm/barrier.h>
-#include <asm/global_lock.h>
-
-#ifdef CONFIG_SMP
-/*
- * These functions are the basis of our bit ops.
- */
-static inline void set_bit(unsigned int bit, volatile unsigned long *p)
-{
- unsigned long flags;
- unsigned long mask = 1UL << (bit & 31);
-
- p += bit >> 5;
-
- __global_lock1(flags);
- fence();
- *p |= mask;
- __global_unlock1(flags);
-}
-
-static inline void clear_bit(unsigned int bit, volatile unsigned long *p)
-{
- unsigned long flags;
- unsigned long mask = 1UL << (bit & 31);
-
- p += bit >> 5;
-
- __global_lock1(flags);
- fence();
- *p &= ~mask;
- __global_unlock1(flags);
-}
-
-static inline void change_bit(unsigned int bit, volatile unsigned long *p)
-{
- unsigned long flags;
- unsigned long mask = 1UL << (bit & 31);
-
- p += bit >> 5;
-
- __global_lock1(flags);
- fence();
- *p ^= mask;
- __global_unlock1(flags);
-}
-
-static inline int test_and_set_bit(unsigned int bit, volatile unsigned long *p)
-{
- unsigned long flags;
- unsigned long old;
- unsigned long mask = 1UL << (bit & 31);
-
- p += bit >> 5;
-
- __global_lock1(flags);
- old = *p;
- if (!(old & mask)) {
- fence();
- *p = old | mask;
- }
- __global_unlock1(flags);
-
- return (old & mask) != 0;
-}
-
-static inline int test_and_clear_bit(unsigned int bit,
- volatile unsigned long *p)
-{
- unsigned long flags;
- unsigned long old;
- unsigned long mask = 1UL << (bit & 31);
-
- p += bit >> 5;
-
- __global_lock1(flags);
- old = *p;
- if (old & mask) {
- fence();
- *p = old & ~mask;
- }
- __global_unlock1(flags);
-
- return (old & mask) != 0;
-}
-
-static inline int test_and_change_bit(unsigned int bit,
- volatile unsigned long *p)
-{
- unsigned long flags;
- unsigned long old;
- unsigned long mask = 1UL << (bit & 31);
-
- p += bit >> 5;
-
- __global_lock1(flags);
- fence();
- old = *p;
- *p = old ^ mask;
- __global_unlock1(flags);
-
- return (old & mask) != 0;
-}
-
-#else
-#include <asm-generic/bitops/atomic.h>
-#endif /* CONFIG_SMP */
-
-#include <asm-generic/bitops/non-atomic.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/le.h>
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#endif /* __ASM_METAG_BITOPS_H */
diff --git a/arch/metag/include/asm/bug.h b/arch/metag/include/asm/bug.h
deleted file mode 100644
index ee07a943f931..000000000000
--- a/arch/metag/include/asm/bug.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_BUG_H
-#define _ASM_METAG_BUG_H
-
-#include <asm-generic/bug.h>
-
-struct pt_regs;
-
-extern const char *trap_name(int trapno);
-extern void __noreturn die(const char *str, struct pt_regs *regs, long err,
- unsigned long addr);
-
-#endif
diff --git a/arch/metag/include/asm/cache.h b/arch/metag/include/asm/cache.h
deleted file mode 100644
index b5df02239c8d..000000000000
--- a/arch/metag/include/asm/cache.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_CACHE_H
-#define __ASM_METAG_CACHE_H
-
-/* L1 cache line size (64 bytes) */
-#define L1_CACHE_SHIFT 6
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-/* Meta requires large data items to be 8 byte aligned. */
-#define ARCH_SLAB_MINALIGN 8
-
-/*
- * With an L2 cache, we may invalidate dirty lines, so we need to ensure DMA
- * buffers have cache line alignment.
- */
-#ifdef CONFIG_METAG_L2C
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-#else
-#define ARCH_DMA_MINALIGN 8
-#endif
-
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-
-#endif
diff --git a/arch/metag/include/asm/cacheflush.h b/arch/metag/include/asm/cacheflush.h
deleted file mode 100644
index 2584a51eca1a..000000000000
--- a/arch/metag/include/asm/cacheflush.h
+++ /dev/null
@@ -1,251 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_CACHEFLUSH_H
-#define _METAG_CACHEFLUSH_H
-
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-
-#include <asm/l2cache.h>
-#include <asm/metag_isa.h>
-#include <asm/metag_mem.h>
-
-void metag_cache_probe(void);
-
-void metag_data_cache_flush_all(const void *start);
-void metag_code_cache_flush_all(const void *start);
-
-/*
- * Routines to flush physical cache lines that may be used to cache data or code
- * normally accessed via the linear address range supplied. The region flushed
- * must either lie in local or global address space determined by the top bit of
- * the pStart address. If Bytes is >= 4K then the whole of the related cache
- * state will be flushed rather than a limited range.
- */
-void metag_data_cache_flush(const void *start, int bytes);
-void metag_code_cache_flush(const void *start, int bytes);
-
-#ifdef CONFIG_METAG_META12
-
-/* Write through, virtually tagged, split I/D cache. */
-
-static inline void __flush_cache_all(void)
-{
- metag_code_cache_flush_all((void *) PAGE_OFFSET);
- metag_data_cache_flush_all((void *) PAGE_OFFSET);
-}
-
-#define flush_cache_all() __flush_cache_all()
-
-/* flush the entire user address space referenced in this mm structure */
-static inline void flush_cache_mm(struct mm_struct *mm)
-{
- if (mm == current->mm)
- __flush_cache_all();
-}
-
-#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
-
-/* flush a range of addresses from this mm */
-static inline void flush_cache_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
-{
- flush_cache_mm(vma->vm_mm);
-}
-
-static inline void flush_cache_page(struct vm_area_struct *vma,
- unsigned long vmaddr, unsigned long pfn)
-{
- flush_cache_mm(vma->vm_mm);
-}
-
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-static inline void flush_dcache_page(struct page *page)
-{
- metag_data_cache_flush_all((void *) PAGE_OFFSET);
-}
-
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-
-static inline void flush_icache_page(struct vm_area_struct *vma,
- struct page *page)
-{
- metag_code_cache_flush(page_to_virt(page), PAGE_SIZE);
-}
-
-static inline void flush_cache_vmap(unsigned long start, unsigned long end)
-{
- metag_data_cache_flush_all((void *) PAGE_OFFSET);
-}
-
-static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
-{
- metag_data_cache_flush_all((void *) PAGE_OFFSET);
-}
-
-#else
-
-/* Write through, physically tagged, split I/D cache. */
-
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_icache_page(vma, pg) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
-static inline void flush_dcache_page(struct page *page)
-{
- /* FIXME: We can do better than this. All we are trying to do is
- * make the i-cache coherent, we should use the PG_arch_1 bit like
- * e.g. powerpc.
- */
-#ifdef CONFIG_SMP
- metag_out32(1, SYSC_ICACHE_FLUSH);
-#else
- metag_code_cache_flush_all((void *) PAGE_OFFSET);
-#endif
-}
-
-#endif
-
-/* Push n pages at kernel virtual address and clear the icache */
-static inline void flush_icache_range(unsigned long address,
- unsigned long endaddr)
-{
-#ifdef CONFIG_SMP
- metag_out32(1, SYSC_ICACHE_FLUSH);
-#else
- metag_code_cache_flush((void *) address, endaddr - address);
-#endif
-}
-
-static inline void flush_cache_sigtramp(unsigned long addr, int size)
-{
- /*
- * Flush the icache in case there was previously some code
- * fetched from this address, perhaps a previous sigtramp.
- *
- * We don't need to flush the dcache, it's write through and
- * we just wrote the sigtramp code through it.
- */
-#ifdef CONFIG_SMP
- metag_out32(1, SYSC_ICACHE_FLUSH);
-#else
- metag_code_cache_flush((void *) addr, size);
-#endif
-}
-
-#ifdef CONFIG_METAG_L2C
-
-/*
- * Perform a single specific CACHEWD operation on an address, masking lower bits
- * of address first.
- */
-static inline void cachewd_line(void *addr, unsigned int data)
-{
- unsigned long masked = (unsigned long)addr & -0x40;
- __builtin_meta2_cachewd((void *)masked, data);
-}
-
-/* Perform a certain CACHEW op on each cache line in a range */
-static inline void cachew_region_op(void *start, unsigned long size,
- unsigned int op)
-{
- unsigned long offset = (unsigned long)start & 0x3f;
- int i;
- if (offset) {
- size += offset;
- start -= offset;
- }
- i = (size - 1) >> 6;
- do {
- __builtin_meta2_cachewd(start, op);
- start += 0x40;
- } while (i--);
-}
-
-/* prevent write fence and flushbacks being reordered in L2 */
-static inline void l2c_fence_flush(void *addr)
-{
- /*
- * Synchronise by reading back and re-flushing.
- * It is assumed this access will miss, as the caller should have just
- * flushed the cache line.
- */
- (void)(volatile u8 *)addr;
- cachewd_line(addr, CACHEW_FLUSH_L1D_L2);
-}
-
-/* prevent write fence and writebacks being reordered in L2 */
-static inline void l2c_fence(void *addr)
-{
- /*
- * A write back has occurred, but not necessarily an invalidate, so the
- * readback in l2c_fence_flush() would hit in the cache and have no
- * effect. Therefore fully flush the line first.
- */
- cachewd_line(addr, CACHEW_FLUSH_L1D_L2);
- l2c_fence_flush(addr);
-}
-
-/* Used to keep memory consistent when doing DMA. */
-static inline void flush_dcache_region(void *start, unsigned long size)
-{
- /* metag_data_cache_flush won't flush L2 cache lines if size >= 4096 */
- if (meta_l2c_is_enabled()) {
- cachew_region_op(start, size, CACHEW_FLUSH_L1D_L2);
- if (meta_l2c_is_writeback())
- l2c_fence_flush(start + size - 1);
- } else {
- metag_data_cache_flush(start, size);
- }
-}
-
-/* Write back dirty lines to memory (or do nothing if no writeback caches) */
-static inline void writeback_dcache_region(void *start, unsigned long size)
-{
- if (meta_l2c_is_enabled() && meta_l2c_is_writeback()) {
- cachew_region_op(start, size, CACHEW_WRITEBACK_L1D_L2);
- l2c_fence(start + size - 1);
- }
-}
-
-/* Invalidate (may also write back if necessary) */
-static inline void invalidate_dcache_region(void *start, unsigned long size)
-{
- if (meta_l2c_is_enabled())
- cachew_region_op(start, size, CACHEW_INVALIDATE_L1D_L2);
- else
- metag_data_cache_flush(start, size);
-}
-#else
-#define flush_dcache_region(s, l) metag_data_cache_flush((s), (l))
-#define writeback_dcache_region(s, l) do {} while (0)
-#define invalidate_dcache_region(s, l) flush_dcache_region((s), (l))
-#endif
-
-static inline void copy_to_user_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vaddr,
- void *dst, const void *src,
- unsigned long len)
-{
- memcpy(dst, src, len);
- flush_icache_range((unsigned long)dst, (unsigned long)dst + len);
-}
-
-static inline void copy_from_user_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vaddr,
- void *dst, const void *src,
- unsigned long len)
-{
- memcpy(dst, src, len);
-}
-
-#endif /* _METAG_CACHEFLUSH_H */
diff --git a/arch/metag/include/asm/cachepart.h b/arch/metag/include/asm/cachepart.h
deleted file mode 100644
index 79411e977586..000000000000
--- a/arch/metag/include/asm/cachepart.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Meta cache partition manipulation.
- *
- * Copyright 2010 Imagination Technologies Ltd.
- */
-
-#ifndef _METAG_CACHEPART_H_
-#define _METAG_CACHEPART_H_
-
-/**
- * get_dcache_size() - Get size of data cache.
- */
-unsigned int get_dcache_size(void);
-
-/**
- * get_icache_size() - Get size of code cache.
- */
-unsigned int get_icache_size(void);
-
-/**
- * get_global_dcache_size() - Get the thread's global dcache.
- *
- * Returns the size of the current thread's global dcache partition.
- */
-unsigned int get_global_dcache_size(void);
-
-/**
- * get_global_icache_size() - Get the thread's global icache.
- *
- * Returns the size of the current thread's global icache partition.
- */
-unsigned int get_global_icache_size(void);
-
-/**
- * check_for_dache_aliasing() - Ensure that the bootloader has configured the
- * dache and icache properly to avoid aliasing
- * @thread_id: Hardware thread ID
- *
- */
-void check_for_cache_aliasing(int thread_id);
-
-#endif
diff --git a/arch/metag/include/asm/checksum.h b/arch/metag/include/asm/checksum.h
deleted file mode 100644
index 6533d14e9789..000000000000
--- a/arch/metag/include/asm/checksum.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_CHECKSUM_H
-#define _METAG_CHECKSUM_H
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy(const void *src, void *dst, int len,
- __wsum sum);
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
- int len, __wsum sum, int *csum_err);
-
-#define csum_partial_copy_nocheck(src, dst, len, sum) \
- csum_partial_copy((src), (dst), (len), (sum))
-
-/*
- * Fold a partial checksum
- */
-static inline __sum16 csum_fold(__wsum csum)
-{
- u32 sum = (__force u32)csum;
- sum = (sum & 0xffff) + (sum >> 16);
- sum = (sum & 0xffff) + (sum >> 16);
- return (__force __sum16)~sum;
-}
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- */
-extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- unsigned long len_proto = (proto + len) << 8;
- asm ("ADDS %0, %0, %1\n"
- "ADDCS %0, %0, #1\n"
- "ADDS %0, %0, %2\n"
- "ADDCS %0, %0, #1\n"
- "ADDS %0, %0, %3\n"
- "ADDCS %0, %0, #1\n"
- : "=d" (sum)
- : "d" (daddr), "d" (saddr), "d" (len_proto),
- "0" (sum)
- : "cc");
- return sum;
-}
-
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#endif /* _METAG_CHECKSUM_H */
diff --git a/arch/metag/include/asm/clock.h b/arch/metag/include/asm/clock.h
deleted file mode 100644
index ded4ab2e1fd0..000000000000
--- a/arch/metag/include/asm/clock.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * arch/metag/include/asm/clock.h
- *
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _METAG_CLOCK_H_
-#define _METAG_CLOCK_H_
-
-#include <asm/mach/arch.h>
-
-/**
- * struct meta_clock_desc - Meta Core clock callbacks.
- * @get_core_freq: Get the frequency of the Meta core. If this is NULL, the
- * core frequency will be determined like this:
- * Meta 1: based on loops_per_jiffy.
- * Meta 2: (EXPAND_TIMER_DIV + 1) MHz.
- * If a "core" clock is provided by the device tree, it
- * will override this function.
- */
-struct meta_clock_desc {
- unsigned long (*get_core_freq)(void);
-};
-
-extern struct meta_clock_desc _meta_clock;
-
-/*
- * Perform platform clock initialisation, reading clocks from device tree etc.
- * Only accessible during boot.
- */
-void init_metag_clocks(void);
-
-/*
- * Set up the default clock, ensuring all callbacks are valid - only accessible
- * during boot.
- */
-void setup_meta_clocks(struct meta_clock_desc *desc);
-
-/**
- * get_coreclock() - Get the frequency of the Meta core clock.
- *
- * Returns: The Meta core clock frequency in Hz.
- */
-static inline unsigned long get_coreclock(void)
-{
- /*
- * Use the current clock callback. If set correctly this will provide
- * the most accurate frequency as it can be calculated directly from the
- * PLL configuration. otherwise a default callback will have been set
- * instead.
- */
- return _meta_clock.get_core_freq();
-}
-
-#endif /* _METAG_CLOCK_H_ */
diff --git a/arch/metag/include/asm/cmpxchg.h b/arch/metag/include/asm/cmpxchg.h
deleted file mode 100644
index 68c4ab1466fd..000000000000
--- a/arch/metag/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_CMPXCHG_H
-#define __ASM_METAG_CMPXCHG_H
-
-#include <asm/barrier.h>
-
-#if defined(CONFIG_METAG_ATOMICITY_IRQSOFF)
-#include <asm/cmpxchg_irq.h>
-#elif defined(CONFIG_METAG_ATOMICITY_LOCK1)
-#include <asm/cmpxchg_lock1.h>
-#elif defined(CONFIG_METAG_ATOMICITY_LNKGET)
-#include <asm/cmpxchg_lnkget.h>
-#endif
-
-extern void __xchg_called_with_bad_pointer(void);
-
-#define __xchg(ptr, x, size) \
-({ \
- unsigned long __xchg__res; \
- volatile void *__xchg_ptr = (ptr); \
- switch (size) { \
- case 4: \
- __xchg__res = xchg_u32(__xchg_ptr, x); \
- break; \
- case 1: \
- __xchg__res = xchg_u8(__xchg_ptr, x); \
- break; \
- default: \
- __xchg_called_with_bad_pointer(); \
- __xchg__res = x; \
- break; \
- } \
- \
- __xchg__res; \
-})
-
-#define xchg(ptr, x) \
- ((__typeof__(*(ptr)))__xchg((ptr), (unsigned long)(x), sizeof(*(ptr))))
-
-/* This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg(). */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
- unsigned long new, int size)
-{
- switch (size) {
- case 4:
- return __cmpxchg_u32(ptr, old, new);
- }
- __cmpxchg_called_with_bad_pointer();
- return old;
-}
-
-#define cmpxchg(ptr, o, n) \
- ({ \
- __typeof__(*(ptr)) _o_ = (o); \
- __typeof__(*(ptr)) _n_ = (n); \
- (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
- (unsigned long)_n_, \
- sizeof(*(ptr))); \
- })
-
-#endif /* __ASM_METAG_CMPXCHG_H */
diff --git a/arch/metag/include/asm/cmpxchg_irq.h b/arch/metag/include/asm/cmpxchg_irq.h
deleted file mode 100644
index 5255e37f8496..000000000000
--- a/arch/metag/include/asm/cmpxchg_irq.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_CMPXCHG_IRQ_H
-#define __ASM_METAG_CMPXCHG_IRQ_H
-
-#include <linux/irqflags.h>
-
-static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
-{
- unsigned long flags, retval;
-
- local_irq_save(flags);
- retval = *m;
- *m = val;
- local_irq_restore(flags);
- return retval;
-}
-
-static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
-{
- unsigned long flags, retval;
-
- local_irq_save(flags);
- retval = *m;
- *m = val & 0xff;
- local_irq_restore(flags);
- return retval;
-}
-
-static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
- unsigned long new)
-{
- __u32 retval;
- unsigned long flags;
-
- local_irq_save(flags);
- retval = *m;
- if (retval == old)
- *m = new;
- local_irq_restore(flags); /* implies memory barrier */
- return retval;
-}
-
-#endif /* __ASM_METAG_CMPXCHG_IRQ_H */
diff --git a/arch/metag/include/asm/cmpxchg_lnkget.h b/arch/metag/include/asm/cmpxchg_lnkget.h
deleted file mode 100644
index c69be00a4739..000000000000
--- a/arch/metag/include/asm/cmpxchg_lnkget.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_CMPXCHG_LNKGET_H
-#define __ASM_METAG_CMPXCHG_LNKGET_H
-
-static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
-{
- int temp, old;
-
- smp_mb();
-
- asm volatile (
- "1: LNKGETD %1, [%2]\n"
- " LNKSETD [%2], %3\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
-#ifdef CONFIG_METAG_LNKGET_AROUND_CACHE
- " DCACHE [%2], %0\n"
-#endif
- : "=&d" (temp), "=&d" (old)
- : "da" (m), "da" (val)
- : "cc"
- );
-
- smp_mb();
-
- return old;
-}
-
-static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
-{
- int temp, old;
-
- smp_mb();
-
- asm volatile (
- "1: LNKGETD %1, [%2]\n"
- " LNKSETD [%2], %3\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
-#ifdef CONFIG_METAG_LNKGET_AROUND_CACHE
- " DCACHE [%2], %0\n"
-#endif
- : "=&d" (temp), "=&d" (old)
- : "da" (m), "da" (val & 0xff)
- : "cc"
- );
-
- smp_mb();
-
- return old;
-}
-
-static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
- unsigned long new)
-{
- __u32 retval, temp;
-
- smp_mb();
-
- asm volatile (
- "1: LNKGETD %1, [%2]\n"
- " CMP %1, %3\n"
- " LNKSETDEQ [%2], %4\n"
- " BNE 2f\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
-#ifdef CONFIG_METAG_LNKGET_AROUND_CACHE
- " DCACHE [%2], %0\n"
-#endif
- "2:\n"
- : "=&d" (temp), "=&d" (retval)
- : "da" (m), "bd" (old), "da" (new)
- : "cc"
- );
-
- smp_mb();
-
- return retval;
-}
-
-#endif /* __ASM_METAG_CMPXCHG_LNKGET_H */
diff --git a/arch/metag/include/asm/cmpxchg_lock1.h b/arch/metag/include/asm/cmpxchg_lock1.h
deleted file mode 100644
index 5976e39db2b4..000000000000
--- a/arch/metag/include/asm/cmpxchg_lock1.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_CMPXCHG_LOCK1_H
-#define __ASM_METAG_CMPXCHG_LOCK1_H
-
-#include <asm/global_lock.h>
-
-/* Use LOCK2 as these have to be atomic w.r.t. ordinary accesses. */
-
-static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
-{
- unsigned long flags, retval;
-
- __global_lock2(flags);
- fence();
- retval = *m;
- *m = val;
- __global_unlock2(flags);
- return retval;
-}
-
-static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
-{
- unsigned long flags, retval;
-
- __global_lock2(flags);
- fence();
- retval = *m;
- *m = val & 0xff;
- __global_unlock2(flags);
- return retval;
-}
-
-static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
- unsigned long new)
-{
- __u32 retval;
- unsigned long flags;
-
- __global_lock2(flags);
- retval = *m;
- if (retval == old) {
- fence();
- *m = new;
- }
- __global_unlock2(flags);
- return retval;
-}
-
-#endif /* __ASM_METAG_CMPXCHG_LOCK1_H */
diff --git a/arch/metag/include/asm/core_reg.h b/arch/metag/include/asm/core_reg.h
deleted file mode 100644
index ca70a0a29b61..000000000000
--- a/arch/metag/include/asm/core_reg.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_CORE_REG_H_
-#define __ASM_METAG_CORE_REG_H_
-
-#include <asm/metag_regs.h>
-
-extern void core_reg_write(int unit, int reg, int thread, unsigned int val);
-extern unsigned int core_reg_read(int unit, int reg, int thread);
-
-/*
- * These macros allow direct access from C to any register known to the
- * assembler. Example candidates are TXTACTCYC, TXIDLECYC, and TXPRIVEXT.
- */
-
-#define __core_reg_get(reg) ({ \
- unsigned int __grvalue; \
- asm volatile("MOV %0," #reg \
- : "=r" (__grvalue)); \
- __grvalue; \
-})
-
-#define __core_reg_set(reg, value) do { \
- unsigned int __srvalue = (value); \
- asm volatile("MOV " #reg ",%0" \
- : \
- : "r" (__srvalue)); \
-} while (0)
-
-#define __core_reg_swap(reg, value) do { \
- unsigned int __srvalue = (value); \
- asm volatile("SWAP " #reg ",%0" \
- : "+r" (__srvalue)); \
- (value) = __srvalue; \
-} while (0)
-
-#endif
diff --git a/arch/metag/include/asm/cpu.h b/arch/metag/include/asm/cpu.h
deleted file mode 100644
index 9dac67de4748..000000000000
--- a/arch/metag/include/asm/cpu.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_CPU_H
-#define _ASM_METAG_CPU_H
-
-#include <linux/percpu.h>
-
-struct cpuinfo_metag {
- struct cpu cpu;
-#ifdef CONFIG_SMP
- unsigned long loops_per_jiffy;
-#endif
-};
-
-DECLARE_PER_CPU(struct cpuinfo_metag, cpu_data);
-#endif /* _ASM_METAG_CPU_H */
diff --git a/arch/metag/include/asm/da.h b/arch/metag/include/asm/da.h
deleted file mode 100644
index 901daa540e6e..000000000000
--- a/arch/metag/include/asm/da.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Meta DA JTAG debugger control.
- *
- * Copyright 2012 Imagination Technologies Ltd.
- */
-
-#ifndef _METAG_DA_H_
-#define _METAG_DA_H_
-
-#ifdef CONFIG_METAG_DA
-
-#include <linux/init.h>
-#include <linux/types.h>
-
-extern bool _metag_da_present;
-
-/**
- * metag_da_enabled() - Find whether a DA is currently enabled.
- *
- * Returns: true if a DA was detected, false if not.
- */
-static inline bool metag_da_enabled(void)
-{
- return _metag_da_present;
-}
-
-/**
- * metag_da_probe() - Try and detect a connected DA.
- *
- * This is used at start up to detect whether a DA is active.
- *
- * Returns: 0 on detection, -err otherwise.
- */
-int __init metag_da_probe(void);
-
-#else /* !CONFIG_METAG_DA */
-
-#define metag_da_enabled() false
-#define metag_da_probe() do {} while (0)
-
-#endif
-
-#endif /* _METAG_DA_H_ */
diff --git a/arch/metag/include/asm/delay.h b/arch/metag/include/asm/delay.h
deleted file mode 100644
index fd73d3d5d294..000000000000
--- a/arch/metag/include/asm/delay.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_DELAY_H
-#define _METAG_DELAY_H
-
-/*
- * Copyright (C) 1993 Linus Torvalds
- *
- * Delay routines calling functions in arch/metag/lib/delay.c
- */
-
-/* Undefined functions to get compile-time errors */
-extern void __bad_udelay(void);
-extern void __bad_ndelay(void);
-
-extern void __udelay(unsigned long usecs);
-extern void __ndelay(unsigned long nsecs);
-extern void __const_udelay(unsigned long xloops);
-extern void __delay(unsigned long loops);
-
-/* 0x10c7 is 2**32 / 1000000 (rounded up) */
-#define udelay(n) (__builtin_constant_p(n) ? \
- ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c7ul)) : \
- __udelay(n))
-
-/* 0x5 is 2**32 / 1000000000 (rounded up) */
-#define ndelay(n) (__builtin_constant_p(n) ? \
- ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
- __ndelay(n))
-
-#endif /* _METAG_DELAY_H */
diff --git a/arch/metag/include/asm/div64.h b/arch/metag/include/asm/div64.h
deleted file mode 100644
index e3686d2ae20e..000000000000
--- a/arch/metag/include/asm/div64.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_DIV64_H__
-#define __ASM_DIV64_H__
-
-#include <asm-generic/div64.h>
-
-extern u64 div_u64(u64 dividend, u64 divisor);
-extern s64 div_s64(s64 dividend, s64 divisor);
-
-#define div_u64 div_u64
-#define div_s64 div_s64
-
-#endif
diff --git a/arch/metag/include/asm/dma-mapping.h b/arch/metag/include/asm/dma-mapping.h
deleted file mode 100644
index cfd6a0505b56..000000000000
--- a/arch/metag/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_DMA_MAPPING_H
-#define _ASM_METAG_DMA_MAPPING_H
-
-extern const struct dma_map_ops metag_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &metag_dma_ops;
-}
-
-#endif
diff --git a/arch/metag/include/asm/elf.h b/arch/metag/include/asm/elf.h
deleted file mode 100644
index a6c33800ba66..000000000000
--- a/arch/metag/include/asm/elf.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_ELF_H
-#define __ASM_METAG_ELF_H
-
-#define EM_METAG 174
-
-/* Meta relocations */
-#define R_METAG_HIADDR16 0
-#define R_METAG_LOADDR16 1
-#define R_METAG_ADDR32 2
-#define R_METAG_NONE 3
-#define R_METAG_RELBRANCH 4
-#define R_METAG_GETSETOFF 5
-
-/* Backward compatibility */
-#define R_METAG_REG32OP1 6
-#define R_METAG_REG32OP2 7
-#define R_METAG_REG32OP3 8
-#define R_METAG_REG16OP1 9
-#define R_METAG_REG16OP2 10
-#define R_METAG_REG16OP3 11
-#define R_METAG_REG32OP4 12
-
-#define R_METAG_HIOG 13
-#define R_METAG_LOOG 14
-
-/* GNU */
-#define R_METAG_GNU_VTINHERIT 30
-#define R_METAG_GNU_VTENTRY 31
-
-/* PIC relocations */
-#define R_METAG_HI16_GOTOFF 32
-#define R_METAG_LO16_GOTOFF 33
-#define R_METAG_GETSET_GOTOFF 34
-#define R_METAG_GETSET_GOT 35
-#define R_METAG_HI16_GOTPC 36
-#define R_METAG_LO16_GOTPC 37
-#define R_METAG_HI16_PLT 38
-#define R_METAG_LO16_PLT 39
-#define R_METAG_RELBRANCH_PLT 40
-#define R_METAG_GOTOFF 41
-#define R_METAG_PLT 42
-#define R_METAG_COPY 43
-#define R_METAG_JMP_SLOT 44
-#define R_METAG_RELATIVE 45
-#define R_METAG_GLOB_DAT 46
-
-/*
- * ELF register definitions.
- */
-
-#include <asm/page.h>
-#include <asm/processor.h>
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct user_gp_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef unsigned long elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_METAG)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_METAG
-
-#define ELF_PLAT_INIT(_r, load_addr) \
- do { _r->ctx.AX[0].U0 = 0; } while (0)
-
-#define USE_ELF_CORE_DUMP
-#define CORE_DUMP_USE_REGSET
-#define ELF_EXEC_PAGESIZE PAGE_SIZE
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#define ELF_ET_DYN_BASE 0x08000000UL
-
-#define ELF_CORE_COPY_REGS(_dest, _regs) \
- memcpy((char *)&_dest, (char *)_regs, sizeof(struct pt_regs));
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo. */
-
-#define ELF_PLATFORM (NULL)
-
-#define STACK_RND_MASK (0)
-
-#ifdef CONFIG_METAG_USER_TCM
-
-struct elf32_phdr;
-struct file;
-
-unsigned long __metag_elf_map(struct file *filep, unsigned long addr,
- struct elf32_phdr *eppnt, int prot, int type,
- unsigned long total_size);
-
-static inline unsigned long metag_elf_map(struct file *filep,
- unsigned long addr,
- struct elf32_phdr *eppnt, int prot,
- int type, unsigned long total_size)
-{
- return __metag_elf_map(filep, addr, eppnt, prot, type, total_size);
-}
-#define elf_map metag_elf_map
-
-#endif
-
-#endif
diff --git a/arch/metag/include/asm/fixmap.h b/arch/metag/include/asm/fixmap.h
deleted file mode 100644
index af621b041739..000000000000
--- a/arch/metag/include/asm/fixmap.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * fixmap.h: compile-time virtual memory allocation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Ingo Molnar
- *
- * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
- */
-
-#ifndef _ASM_FIXMAP_H
-#define _ASM_FIXMAP_H
-
-#include <asm/pgtable.h>
-#ifdef CONFIG_HIGHMEM
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#endif
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special addresses
- * from the end of the consistent memory region backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * higher than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-enum fixed_addresses {
-#define FIX_N_COLOURS 8
-#ifdef CONFIG_HIGHMEM
- /* reserved pte's for temporary kernel mappings */
- FIX_KMAP_BEGIN,
- FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
- __end_of_fixed_addresses
-};
-
-#define FIXADDR_TOP (CONSISTENT_START - PAGE_SIZE)
-#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START ((FIXADDR_TOP - FIXADDR_SIZE) & PMD_MASK)
-
-#include <asm-generic/fixmap.h>
-
-#define kmap_get_fixmap_pte(vaddr) \
- pte_offset_kernel( \
- pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), \
- (vaddr) \
- )
-
-/*
- * Called from pgtable_init()
- */
-extern void fixrange_init(unsigned long start, unsigned long end,
- pgd_t *pgd_base);
-
-
-#endif
diff --git a/arch/metag/include/asm/ftrace.h b/arch/metag/include/asm/ftrace.h
deleted file mode 100644
index b1c8c76fb772..000000000000
--- a/arch/metag/include/asm/ftrace.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_FTRACE
-#define _ASM_METAG_FTRACE
-
-#ifdef CONFIG_FUNCTION_TRACER
-#define MCOUNT_INSN_SIZE 8 /* sizeof mcount call */
-
-#ifndef __ASSEMBLY__
-extern void mcount_wrapper(void);
-#define MCOUNT_ADDR ((unsigned long)(mcount_wrapper))
-
-static inline unsigned long ftrace_call_adjust(unsigned long addr)
-{
- return addr;
-}
-
-struct dyn_arch_ftrace {
- /* No extra data needed on metag */
-};
-#endif /* __ASSEMBLY__ */
-
-#endif /* CONFIG_FUNCTION_TRACER */
-
-#endif /* _ASM_METAG_FTRACE */
diff --git a/arch/metag/include/asm/global_lock.h b/arch/metag/include/asm/global_lock.h
deleted file mode 100644
index 4d3da9682233..000000000000
--- a/arch/metag/include/asm/global_lock.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_GLOBAL_LOCK_H
-#define __ASM_METAG_GLOBAL_LOCK_H
-
-#include <asm/metag_mem.h>
-
-/**
- * __global_lock1() - Acquire global voluntary lock (LOCK1).
- * @flags: Variable to store flags into.
- *
- * Acquires the Meta global voluntary lock (LOCK1), also taking care to disable
- * all triggers so we cannot be interrupted, and to enforce a compiler barrier
- * so that the compiler cannot reorder memory accesses across the lock.
- *
- * No other hardware thread will be able to acquire the voluntary or exclusive
- * locks until the voluntary lock is released with @__global_unlock1, but they
- * may continue to execute as long as they aren't trying to acquire either of
- * the locks.
- */
-#define __global_lock1(flags) do { \
- unsigned int __trval; \
- asm volatile("MOV %0,#0\n\t" \
- "SWAP %0,TXMASKI\n\t" \
- "LOCK1" \
- : "=r" (__trval) \
- : \
- : "memory"); \
- (flags) = __trval; \
-} while (0)
-
-/**
- * __global_unlock1() - Release global voluntary lock (LOCK1).
- * @flags: Variable to restore flags from.
- *
- * Releases the Meta global voluntary lock (LOCK1) acquired with
- * @__global_lock1, also taking care to re-enable triggers, and to enforce a
- * compiler barrier so that the compiler cannot reorder memory accesses across
- * the unlock.
- *
- * This immediately allows another hardware thread to acquire the voluntary or
- * exclusive locks.
- */
-#define __global_unlock1(flags) do { \
- unsigned int __trval = (flags); \
- asm volatile("LOCK0\n\t" \
- "MOV TXMASKI,%0" \
- : \
- : "r" (__trval) \
- : "memory"); \
-} while (0)
-
-/**
- * __global_lock2() - Acquire global exclusive lock (LOCK2).
- * @flags: Variable to store flags into.
- *
- * Acquires the Meta global voluntary lock and global exclusive lock (LOCK2),
- * also taking care to disable all triggers so we cannot be interrupted, to take
- * the atomic lock (system event) and to enforce a compiler barrier so that the
- * compiler cannot reorder memory accesses across the lock.
- *
- * No other hardware thread will be able to execute code until the locks are
- * released with @__global_unlock2.
- */
-#define __global_lock2(flags) do { \
- unsigned int __trval; \
- unsigned int __aloc_hi = LINSYSEVENT_WR_ATOMIC_LOCK & 0xFFFF0000; \
- asm volatile("MOV %0,#0\n\t" \
- "SWAP %0,TXMASKI\n\t" \
- "LOCK2\n\t" \
- "SETD [%1+#0x40],D1RtP" \
- : "=r&" (__trval) \
- : "u" (__aloc_hi) \
- : "memory"); \
- (flags) = __trval; \
-} while (0)
-
-/**
- * __global_unlock2() - Release global exclusive lock (LOCK2).
- * @flags: Variable to restore flags from.
- *
- * Releases the Meta global exclusive lock (LOCK2) and global voluntary lock
- * acquired with @__global_lock2, also taking care to release the atomic lock
- * (system event), re-enable triggers, and to enforce a compiler barrier so that
- * the compiler cannot reorder memory accesses across the unlock.
- *
- * This immediately allows other hardware threads to continue executing and one
- * of them to acquire locks.
- */
-#define __global_unlock2(flags) do { \
- unsigned int __trval = (flags); \
- unsigned int __alock_hi = LINSYSEVENT_WR_ATOMIC_LOCK & 0xFFFF0000; \
- asm volatile("SETD [%1+#0x00],D1RtP\n\t" \
- "LOCK0\n\t" \
- "MOV TXMASKI,%0" \
- : \
- : "r" (__trval), \
- "u" (__alock_hi) \
- : "memory"); \
-} while (0)
-
-#endif /* __ASM_METAG_GLOBAL_LOCK_H */
diff --git a/arch/metag/include/asm/hugetlb.h b/arch/metag/include/asm/hugetlb.h
deleted file mode 100644
index 1607363d2639..000000000000
--- a/arch/metag/include/asm/hugetlb.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_HUGETLB_H
-#define _ASM_METAG_HUGETLB_H
-
-#include <asm/page.h>
-#include <asm-generic/hugetlb.h>
-
-
-static inline int is_hugepage_only_range(struct mm_struct *mm,
- unsigned long addr,
- unsigned long len) {
- return 0;
-}
-
-int prepare_hugepage_range(struct file *file, unsigned long addr,
- unsigned long len);
-
-static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
- unsigned long addr, unsigned long end,
- unsigned long floor,
- unsigned long ceiling)
-{
- free_pgd_range(tlb, addr, end, floor, ceiling);
-}
-
-static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, pte_t pte)
-{
- set_pte_at(mm, addr, ptep, pte);
-}
-
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- return ptep_get_and_clear(mm, addr, ptep);
-}
-
-static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep)
-{
-}
-
-static inline int huge_pte_none(pte_t pte)
-{
- return pte_none(pte);
-}
-
-static inline pte_t huge_pte_wrprotect(pte_t pte)
-{
- return pte_wrprotect(pte);
-}
-
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- ptep_set_wrprotect(mm, addr, ptep);
-}
-
-static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep,
- pte_t pte, int dirty)
-{
- return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
-}
-
-static inline pte_t huge_ptep_get(pte_t *ptep)
-{
- return *ptep;
-}
-
-static inline void arch_clear_hugepage_flags(struct page *page)
-{
-}
-
-#endif /* _ASM_METAG_HUGETLB_H */
diff --git a/arch/metag/include/asm/hwthread.h b/arch/metag/include/asm/hwthread.h
deleted file mode 100644
index 8d2171da5414..000000000000
--- a/arch/metag/include/asm/hwthread.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2008 Imagination Technologies
- */
-#ifndef __METAG_HWTHREAD_H
-#define __METAG_HWTHREAD_H
-
-#include <linux/bug.h>
-#include <linux/io.h>
-
-#include <asm/metag_mem.h>
-
-#define BAD_HWTHREAD_ID (0xFFU)
-#define BAD_CPU_ID (0xFFU)
-
-extern u8 cpu_2_hwthread_id[];
-extern u8 hwthread_id_2_cpu[];
-
-/*
- * Each hardware thread's Control Unit registers are memory-mapped
- * and can therefore be accessed by any other hardware thread.
- *
- * This helper function returns the memory address where "thread"'s
- * register "regnum" is mapped.
- */
-static inline
-void __iomem *__CU_addr(unsigned int thread, unsigned int regnum)
-{
- unsigned int base, thread_offset, thread_regnum;
-
- WARN_ON(thread == BAD_HWTHREAD_ID);
-
- base = T0UCTREG0; /* Control unit base */
-
- thread_offset = TnUCTRX_STRIDE * thread;
- thread_regnum = TXUCTREGn_STRIDE * regnum;
-
- return (void __iomem *)(base + thread_offset + thread_regnum);
-}
-
-#endif /* __METAG_HWTHREAD_H */
diff --git a/arch/metag/include/asm/io.h b/arch/metag/include/asm/io.h
deleted file mode 100644
index 71cd2bc54718..000000000000
--- a/arch/metag/include/asm/io.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_IO_H
-#define _ASM_METAG_IO_H
-
-#include <linux/types.h>
-#include <asm/pgtable-bits.h>
-
-#define IO_SPACE_LIMIT 0
-
-#define page_to_bus page_to_phys
-#define bus_to_page phys_to_page
-
-/*
- * Generic I/O
- */
-
-#define __raw_readb __raw_readb
-static inline u8 __raw_readb(const volatile void __iomem *addr)
-{
- u8 ret;
- asm volatile("GETB %0,[%1]"
- : "=da" (ret)
- : "da" (addr)
- : "memory");
- return ret;
-}
-
-#define __raw_readw __raw_readw
-static inline u16 __raw_readw(const volatile void __iomem *addr)
-{
- u16 ret;
- asm volatile("GETW %0,[%1]"
- : "=da" (ret)
- : "da" (addr)
- : "memory");
- return ret;
-}
-
-#define __raw_readl __raw_readl
-static inline u32 __raw_readl(const volatile void __iomem *addr)
-{
- u32 ret;
- asm volatile("GETD %0,[%1]"
- : "=da" (ret)
- : "da" (addr)
- : "memory");
- return ret;
-}
-
-#define __raw_readq __raw_readq
-static inline u64 __raw_readq(const volatile void __iomem *addr)
-{
- u64 ret;
- asm volatile("GETL %0,%t0,[%1]"
- : "=da" (ret)
- : "da" (addr)
- : "memory");
- return ret;
-}
-
-#define __raw_writeb __raw_writeb
-static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
-{
- asm volatile("SETB [%0],%1"
- :
- : "da" (addr),
- "da" (b)
- : "memory");
-}
-
-#define __raw_writew __raw_writew
-static inline void __raw_writew(u16 b, volatile void __iomem *addr)
-{
- asm volatile("SETW [%0],%1"
- :
- : "da" (addr),
- "da" (b)
- : "memory");
-}
-
-#define __raw_writel __raw_writel
-static inline void __raw_writel(u32 b, volatile void __iomem *addr)
-{
- asm volatile("SETD [%0],%1"
- :
- : "da" (addr),
- "da" (b)
- : "memory");
-}
-
-#define __raw_writeq __raw_writeq
-static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
-{
- asm volatile("SETL [%0],%1,%t1"
- :
- : "da" (addr),
- "da" (b)
- : "memory");
-}
-
-/*
- * The generic io.h can define all the other generic accessors
- */
-
-#include <asm-generic/io.h>
-
-/*
- * Despite being a 32bit architecture, Meta can do 64bit memory accesses
- * (assuming the bus supports it).
- */
-
-#define readq __raw_readq
-#define writeq __raw_writeq
-
-/*
- * Meta specific I/O for accessing non-MMU areas.
- *
- * These can be provided with a physical address rather than an __iomem pointer
- * and should only be used by core architecture code for accessing fixed core
- * registers. Generic drivers should use ioremap and the generic I/O accessors.
- */
-
-#define metag_in8(addr) __raw_readb((volatile void __iomem *)(addr))
-#define metag_in16(addr) __raw_readw((volatile void __iomem *)(addr))
-#define metag_in32(addr) __raw_readl((volatile void __iomem *)(addr))
-#define metag_in64(addr) __raw_readq((volatile void __iomem *)(addr))
-
-#define metag_out8(b, addr) __raw_writeb(b, (volatile void __iomem *)(addr))
-#define metag_out16(b, addr) __raw_writew(b, (volatile void __iomem *)(addr))
-#define metag_out32(b, addr) __raw_writel(b, (volatile void __iomem *)(addr))
-#define metag_out64(b, addr) __raw_writeq(b, (volatile void __iomem *)(addr))
-
-/*
- * io remapping functions
- */
-
-extern void __iomem *__ioremap(unsigned long offset,
- size_t size, unsigned long flags);
-extern void __iounmap(void __iomem *addr);
-
-/**
- * ioremap - map bus memory into CPU space
- * @offset: bus address of the memory
- * @size: size of the resource to map
- *
- * ioremap performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- */
-#define ioremap(offset, size) \
- __ioremap((offset), (size), 0)
-
-#define ioremap_nocache(offset, size) \
- __ioremap((offset), (size), 0)
-
-#define ioremap_cached(offset, size) \
- __ioremap((offset), (size), _PAGE_CACHEABLE)
-
-#define ioremap_wc(offset, size) \
- __ioremap((offset), (size), _PAGE_WR_COMBINE)
-
-#define ioremap_wt(offset, size) \
- __ioremap((offset), (size), 0)
-
-#define iounmap(addr) \
- __iounmap(addr)
-
-#endif /* _ASM_METAG_IO_H */
diff --git a/arch/metag/include/asm/irq.h b/arch/metag/include/asm/irq.h
deleted file mode 100644
index cb02c29935a4..000000000000
--- a/arch/metag/include/asm/irq.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_IRQ_H
-#define __ASM_METAG_IRQ_H
-
-#ifdef CONFIG_4KSTACKS
-extern void irq_ctx_init(int cpu);
-extern void irq_ctx_exit(int cpu);
-# define __ARCH_HAS_DO_SOFTIRQ
-#else
-static inline void irq_ctx_init(int cpu)
-{
-}
-static inline void irq_ctx_exit(int cpu)
-{
-}
-#endif
-
-void tbi_startup_interrupt(int);
-void tbi_shutdown_interrupt(int);
-
-struct pt_regs;
-
-int tbisig_map(unsigned int hw);
-extern void do_IRQ(int irq, struct pt_regs *regs);
-extern void init_IRQ(void);
-
-#ifdef CONFIG_METAG_SUSPEND_MEM
-int traps_save_context(void);
-int traps_restore_context(void);
-#endif
-
-#include <asm-generic/irq.h>
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern void migrate_irqs(void);
-#endif
-
-#endif /* __ASM_METAG_IRQ_H */
diff --git a/arch/metag/include/asm/irqflags.h b/arch/metag/include/asm/irqflags.h
deleted file mode 100644
index e2fe34acb93b..000000000000
--- a/arch/metag/include/asm/irqflags.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * IRQ flags handling
- *
- * This file gets included from lowlevel asm headers too, to provide
- * wrapped versions of the local_irq_*() APIs, based on the
- * raw_local_irq_*() functions from the lowlevel headers.
- */
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/core_reg.h>
-#include <asm/metag_regs.h>
-
-#define INTS_OFF_MASK TXSTATI_BGNDHALT_BIT
-
-#ifdef CONFIG_SMP
-extern unsigned int get_trigger_mask(void);
-#else
-
-extern unsigned int global_trigger_mask;
-
-static inline unsigned int get_trigger_mask(void)
-{
- return global_trigger_mask;
-}
-#endif
-
-static inline unsigned long arch_local_save_flags(void)
-{
- return __core_reg_get(TXMASKI);
-}
-
-static inline int arch_irqs_disabled_flags(unsigned long flags)
-{
- return (flags & ~INTS_OFF_MASK) == 0;
-}
-
-static inline int arch_irqs_disabled(void)
-{
- unsigned long flags = arch_local_save_flags();
-
- return arch_irqs_disabled_flags(flags);
-}
-
-static inline unsigned long __irqs_disabled(void)
-{
- /*
- * We shouldn't enable exceptions if they are not already
- * enabled. This is required for chancalls to work correctly.
- */
- return arch_local_save_flags() & INTS_OFF_MASK;
-}
-
-/*
- * For spinlocks, etc:
- */
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags = __irqs_disabled();
-
- asm volatile("SWAP %0,TXMASKI\n" : "=r" (flags) : "0" (flags)
- : "memory");
-
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile("MOV TXMASKI,%0\n" : : "r" (flags) : "memory");
-}
-
-static inline void arch_local_irq_disable(void)
-{
- unsigned long flags = __irqs_disabled();
-
- asm volatile("MOV TXMASKI,%0\n" : : "r" (flags) : "memory");
-}
-
-#ifdef CONFIG_SMP
-/* Avoid circular include dependencies through <linux/preempt.h> */
-void arch_local_irq_enable(void);
-#else
-static inline void arch_local_irq_enable(void)
-{
- arch_local_irq_restore(get_trigger_mask());
-}
-#endif
-
-#endif /* (__ASSEMBLY__) */
-
-#endif /* !(_ASM_IRQFLAGS_H) */
diff --git a/arch/metag/include/asm/l2cache.h b/arch/metag/include/asm/l2cache.h
deleted file mode 100644
index f260b158b8fe..000000000000
--- a/arch/metag/include/asm/l2cache.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_L2CACHE_H
-#define _METAG_L2CACHE_H
-
-#ifdef CONFIG_METAG_L2C
-
-#include <asm/global_lock.h>
-#include <asm/io.h>
-
-/*
- * Store the last known value of pfenable (we don't want prefetch enabled while
- * L2 is off).
- */
-extern int l2c_pfenable;
-
-/* defined in arch/metag/drivers/core-sysfs.c */
-extern struct sysdev_class cache_sysclass;
-
-static inline void wr_fence(void);
-
-/*
- * Functions for reading of L2 cache configuration.
- */
-
-/* Get raw L2 config register (CORE_CONFIG3) */
-static inline unsigned int meta_l2c_config(void)
-{
- const unsigned int *corecfg3 = (const unsigned int *)METAC_CORE_CONFIG3;
- return *corecfg3;
-}
-
-/* Get whether the L2 is present */
-static inline int meta_l2c_is_present(void)
-{
- return meta_l2c_config() & METAC_CORECFG3_L2C_HAVE_L2C_BIT;
-}
-
-/* Get whether the L2 is configured for write-back instead of write-through */
-static inline int meta_l2c_is_writeback(void)
-{
- return meta_l2c_config() & METAC_CORECFG3_L2C_MODE_BIT;
-}
-
-/* Get whether the L2 is unified instead of separated code/data */
-static inline int meta_l2c_is_unified(void)
-{
- return meta_l2c_config() & METAC_CORECFG3_L2C_UNIFIED_BIT;
-}
-
-/* Get the L2 cache size in bytes */
-static inline unsigned int meta_l2c_size(void)
-{
- unsigned int size_s;
- if (!meta_l2c_is_present())
- return 0;
- size_s = (meta_l2c_config() & METAC_CORECFG3_L2C_SIZE_BITS)
- >> METAC_CORECFG3_L2C_SIZE_S;
- /* L2CSIZE is in KiB */
- return 1024 << size_s;
-}
-
-/* Get the number of ways in the L2 cache */
-static inline unsigned int meta_l2c_ways(void)
-{
- unsigned int ways_s;
- if (!meta_l2c_is_present())
- return 0;
- ways_s = (meta_l2c_config() & METAC_CORECFG3_L2C_NUM_WAYS_BITS)
- >> METAC_CORECFG3_L2C_NUM_WAYS_S;
- return 0x1 << ways_s;
-}
-
-/* Get the line size of the L2 cache */
-static inline unsigned int meta_l2c_linesize(void)
-{
- unsigned int line_size;
- if (!meta_l2c_is_present())
- return 0;
- line_size = (meta_l2c_config() & METAC_CORECFG3_L2C_LINE_SIZE_BITS)
- >> METAC_CORECFG3_L2C_LINE_SIZE_S;
- switch (line_size) {
- case METAC_CORECFG3_L2C_LINE_SIZE_64B:
- return 64;
- default:
- return 0;
- }
-}
-
-/* Get the revision ID of the L2 cache */
-static inline unsigned int meta_l2c_revision(void)
-{
- return (meta_l2c_config() & METAC_CORECFG3_L2C_REV_ID_BITS)
- >> METAC_CORECFG3_L2C_REV_ID_S;
-}
-
-
-/*
- * Start an initialisation of the L2 cachelines and wait for completion.
- * This should only be done in a LOCK1 or LOCK2 critical section while the L2
- * is disabled.
- */
-static inline void _meta_l2c_init(void)
-{
- metag_out32(SYSC_L2C_INIT_INIT, SYSC_L2C_INIT);
- while (metag_in32(SYSC_L2C_INIT) == SYSC_L2C_INIT_IN_PROGRESS)
- /* do nothing */;
-}
-
-/*
- * Start a writeback of dirty L2 cachelines and wait for completion.
- * This should only be done in a LOCK1 or LOCK2 critical section.
- */
-static inline void _meta_l2c_purge(void)
-{
- metag_out32(SYSC_L2C_PURGE_PURGE, SYSC_L2C_PURGE);
- while (metag_in32(SYSC_L2C_PURGE) == SYSC_L2C_PURGE_IN_PROGRESS)
- /* do nothing */;
-}
-
-/* Set whether the L2 cache is enabled. */
-static inline void _meta_l2c_enable(int enabled)
-{
- unsigned int enable;
-
- enable = metag_in32(SYSC_L2C_ENABLE);
- if (enabled)
- enable |= SYSC_L2C_ENABLE_ENABLE_BIT;
- else
- enable &= ~SYSC_L2C_ENABLE_ENABLE_BIT;
- metag_out32(enable, SYSC_L2C_ENABLE);
-}
-
-/* Set whether the L2 cache prefetch is enabled. */
-static inline void _meta_l2c_pf_enable(int pfenabled)
-{
- unsigned int enable;
-
- enable = metag_in32(SYSC_L2C_ENABLE);
- if (pfenabled)
- enable |= SYSC_L2C_ENABLE_PFENABLE_BIT;
- else
- enable &= ~SYSC_L2C_ENABLE_PFENABLE_BIT;
- metag_out32(enable, SYSC_L2C_ENABLE);
-}
-
-/* Return whether the L2 cache is enabled */
-static inline int _meta_l2c_is_enabled(void)
-{
- return metag_in32(SYSC_L2C_ENABLE) & SYSC_L2C_ENABLE_ENABLE_BIT;
-}
-
-/* Return whether the L2 cache prefetch is enabled */
-static inline int _meta_l2c_pf_is_enabled(void)
-{
- return metag_in32(SYSC_L2C_ENABLE) & SYSC_L2C_ENABLE_PFENABLE_BIT;
-}
-
-
-/* Return whether the L2 cache is enabled */
-static inline int meta_l2c_is_enabled(void)
-{
- int en;
-
- /*
- * There is no need to lock at the moment, as the enable bit is never
- * intermediately changed, so we will never see an intermediate result.
- */
- en = _meta_l2c_is_enabled();
-
- return en;
-}
-
-/*
- * Ensure the L2 cache is disabled.
- * Return whether the L2 was previously disabled.
- */
-int meta_l2c_disable(void);
-
-/*
- * Ensure the L2 cache is enabled.
- * Return whether the L2 was previously enabled.
- */
-int meta_l2c_enable(void);
-
-/* Return whether the L2 cache prefetch is enabled */
-static inline int meta_l2c_pf_is_enabled(void)
-{
- return l2c_pfenable;
-}
-
-/*
- * Set whether the L2 cache prefetch is enabled.
- * Return whether the L2 prefetch was previously enabled.
- */
-int meta_l2c_pf_enable(int pfenable);
-
-/*
- * Flush the L2 cache.
- * Return 1 if the L2 is disabled.
- */
-int meta_l2c_flush(void);
-
-/*
- * Write back all dirty cache lines in the L2 cache.
- * Return 1 if the L2 is disabled or there isn't any writeback.
- */
-static inline int meta_l2c_writeback(void)
-{
- unsigned long flags;
- int en;
-
- /* no need to purge if it's not a writeback cache */
- if (!meta_l2c_is_writeback())
- return 1;
-
- /*
- * Purge only works if the L2 is enabled, and involves reading back to
- * detect completion, so keep this operation atomic with other threads.
- */
- __global_lock1(flags);
- en = meta_l2c_is_enabled();
- if (likely(en)) {
- wr_fence();
- _meta_l2c_purge();
- }
- __global_unlock1(flags);
-
- return !en;
-}
-
-#else /* CONFIG_METAG_L2C */
-
-#define meta_l2c_config() 0
-#define meta_l2c_is_present() 0
-#define meta_l2c_is_writeback() 0
-#define meta_l2c_is_unified() 0
-#define meta_l2c_size() 0
-#define meta_l2c_ways() 0
-#define meta_l2c_linesize() 0
-#define meta_l2c_revision() 0
-
-#define meta_l2c_is_enabled() 0
-#define _meta_l2c_pf_is_enabled() 0
-#define meta_l2c_pf_is_enabled() 0
-#define meta_l2c_disable() 1
-#define meta_l2c_enable() 0
-#define meta_l2c_pf_enable(X) 0
-static inline int meta_l2c_flush(void)
-{
- return 1;
-}
-static inline int meta_l2c_writeback(void)
-{
- return 1;
-}
-
-#endif /* CONFIG_METAG_L2C */
-
-#endif /* _METAG_L2CACHE_H */
diff --git a/arch/metag/include/asm/linkage.h b/arch/metag/include/asm/linkage.h
deleted file mode 100644
index 3a9024ecb827..000000000000
--- a/arch/metag/include/asm/linkage.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .p2align 2
-#define __ALIGN_STR ".p2align 2"
-
-#endif
diff --git a/arch/metag/include/asm/mach/arch.h b/arch/metag/include/asm/mach/arch.h
deleted file mode 100644
index 433f94624fa2..000000000000
--- a/arch/metag/include/asm/mach/arch.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * arch/metag/include/asm/mach/arch.h
- *
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * based on the ARM version:
- * Copyright (C) 2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _METAG_MACH_ARCH_H_
-#define _METAG_MACH_ARCH_H_
-
-#include <linux/stddef.h>
-
-#include <asm/clock.h>
-
-/**
- * struct machine_desc - Describes a board controlled by a Meta.
- * @name: Board/SoC name.
- * @dt_compat: Array of device tree 'compatible' strings.
- * @clocks: Clock callbacks.
- *
- * @nr_irqs: Maximum number of IRQs.
- * If 0, defaults to NR_IRQS in asm-generic/irq.h.
- *
- * @init_early: Early init callback.
- * @init_irq: IRQ init callback for setting up IRQ controllers.
- * @init_machine: Arch init callback for setting up devices.
- * @init_late: Late init callback.
- *
- * This structure is provided by each board which can be controlled by a Meta.
- * It is chosen by matching the compatible strings in the device tree provided
- * by the bootloader with the strings in @dt_compat, and sets up any aspects of
- * the machine that aren't configured with device tree (yet).
- */
-struct machine_desc {
- const char *name;
- const char **dt_compat;
- struct meta_clock_desc *clocks;
-
- unsigned int nr_irqs;
-
- void (*init_early)(void);
- void (*init_irq)(void);
- void (*init_machine)(void);
- void (*init_late)(void);
-};
-
-/*
- * Current machine - only accessible during boot.
- */
-extern const struct machine_desc *machine_desc;
-
-/*
- * Machine type table - also only accessible during boot
- */
-extern struct machine_desc __arch_info_begin[], __arch_info_end[];
-#define for_each_machine_desc(p) \
- for (p = __arch_info_begin; p < __arch_info_end; p++)
-
-static inline struct machine_desc *default_machine_desc(void)
-{
- /* the default machine is the last one linked in */
- if (__arch_info_end - 1 < __arch_info_begin)
- return NULL;
- return __arch_info_end - 1;
-}
-
-/*
- * Set of macros to define architecture features. This is built into
- * a table by the linker.
- */
-#define MACHINE_START(_type, _name) \
-static const struct machine_desc __mach_desc_##_type \
-__used \
-__attribute__((__section__(".arch.info.init"))) = { \
- .name = _name,
-
-#define MACHINE_END \
-};
-
-#endif /* _METAG_MACH_ARCH_H_ */
diff --git a/arch/metag/include/asm/metag_isa.h b/arch/metag/include/asm/metag_isa.h
deleted file mode 100644
index c8aa2ae3899f..000000000000
--- a/arch/metag/include/asm/metag_isa.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * asm/metag_isa.h
- *
- * Copyright (C) 2000-2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Various defines for Meta instruction set.
- */
-
-#ifndef _ASM_METAG_ISA_H_
-#define _ASM_METAG_ISA_H_
-
-
-/* L1 cache layout */
-
-/* Data cache line size as bytes and shift */
-#define DCACHE_LINE_BYTES 64
-#define DCACHE_LINE_S 6
-
-/* Number of ways in the data cache */
-#define DCACHE_WAYS 4
-
-/* Instruction cache line size as bytes and shift */
-#define ICACHE_LINE_BYTES 64
-#define ICACHE_LINE_S 6
-
-/* Number of ways in the instruction cache */
-#define ICACHE_WAYS 4
-
-
-/*
- * CACHEWD/CACHEWL instructions use the bottom 8 bits of the data presented to
- * control the operation actually achieved.
- */
-/* Use of these two bits should be discouraged since the bits dont have
- * consistent meanings
- */
-#define CACHEW_ICACHE_BIT 0x01
-#define CACHEW_TLBFLUSH_BIT 0x02
-
-#define CACHEW_FLUSH_L1D_L2 0x0
-#define CACHEW_INVALIDATE_L1I 0x1
-#define CACHEW_INVALIDATE_L1DTLB 0x2
-#define CACHEW_INVALIDATE_L1ITLB 0x3
-#define CACHEW_WRITEBACK_L1D_L2 0x4
-#define CACHEW_INVALIDATE_L1D 0x8
-#define CACHEW_INVALIDATE_L1D_L2 0xC
-
-/*
- * CACHERD/CACHERL instructions use bits 3:5 of the address presented to
- * control the operation achieved and hence the specific result.
- */
-#define CACHER_ADDR_BITS 0xFFFFFFC0
-#define CACHER_OPER_BITS 0x00000030
-#define CACHER_OPER_S 4
-#define CACHER_OPER_LINPHY 0
-#define CACHER_ICACHE_BIT 0x00000008
-#define CACHER_ICACHE_S 3
-
-/*
- * CACHERD/CACHERL LINPHY Oper result is one/two 32-bit words
- *
- * If CRLINPHY0_VAL_BIT (Bit 0) set then,
- * Lower 32-bits corresponds to MMCU_ENTRY_* above.
- * Upper 32-bits corresponds to CRLINPHY1_* values below (if requested).
- * else
- * Lower 32-bits corresponds to CRLINPHY0_* values below.
- * Upper 32-bits undefined.
- */
-#define CRLINPHY0_VAL_BIT 0x00000001
-#define CRLINPHY0_FIRST_BIT 0x00000004 /* Set if VAL=0 due to first level */
-
-#define CRLINPHY1_READ_BIT 0x00000001 /* Set if reads permitted */
-#define CRLINPHY1_SINGLE_BIT 0x00000004 /* Set if TLB does not cache entry */
-#define CRLINPHY1_PAGEMSK_BITS 0x0000FFF0 /* Set to ((2^n-1)>>12) value */
-#define CRLINPHY1_PAGEMSK_S 4
-
-#endif /* _ASM_METAG_ISA_H_ */
diff --git a/arch/metag/include/asm/metag_mem.h b/arch/metag/include/asm/metag_mem.h
deleted file mode 100644
index 7848bc6d3b61..000000000000
--- a/arch/metag/include/asm/metag_mem.h
+++ /dev/null
@@ -1,1109 +0,0 @@
-/*
- * asm/metag_mem.h
- *
- * Copyright (C) 2000-2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Various defines for Meta (memory-mapped) registers.
- */
-
-#ifndef _ASM_METAG_MEM_H_
-#define _ASM_METAG_MEM_H_
-
-/*****************************************************************************
- * META MEMORY MAP LINEAR ADDRESS VALUES
- ****************************************************************************/
-/*
- * COMMON MEMORY MAP
- * -----------------
- */
-
-#define LINSYSTEM_BASE 0x00200000
-#define LINSYSTEM_LIMIT 0x07FFFFFF
-
-/* Linear cache flush now implemented via DCACHE instruction. These defines
- related to a special region that used to exist for achieving cache flushes.
- */
-#define LINSYSLFLUSH_S 0
-
-#define LINSYSRES0_BASE 0x00200000
-#define LINSYSRES0_LIMIT 0x01FFFFFF
-
-#define LINSYSCUSTOM_BASE 0x02000000
-#define LINSYSCUSTOM_LIMIT 0x02FFFFFF
-
-#define LINSYSEXPAND_BASE 0x03000000
-#define LINSYSEXPAND_LIMIT 0x03FFFFFF
-
-#define LINSYSEVENT_BASE 0x04000000
-#define LINSYSEVENT_WR_ATOMIC_UNLOCK 0x04000000
-#define LINSYSEVENT_WR_ATOMIC_LOCK 0x04000040
-#define LINSYSEVENT_WR_CACHE_DISABLE 0x04000080
-#define LINSYSEVENT_WR_CACHE_ENABLE 0x040000C0
-#define LINSYSEVENT_WR_COMBINE_FLUSH 0x04000100
-#define LINSYSEVENT_WR_FENCE 0x04000140
-#define LINSYSEVENT_LIMIT 0x04000FFF
-
-#define LINSYSCFLUSH_BASE 0x04400000
-#define LINSYSCFLUSH_DCACHE_LINE 0x04400000
-#define LINSYSCFLUSH_ICACHE_LINE 0x04500000
-#define LINSYSCFLUSH_MMCU 0x04700000
-#ifndef METAC_1_2
-#define LINSYSCFLUSH_TxMMCU_BASE 0x04700020
-#define LINSYSCFLUSH_TxMMCU_STRIDE 0x00000008
-#endif
-#define LINSYSCFLUSH_ADDR_BITS 0x000FFFFF
-#define LINSYSCFLUSH_ADDR_S 0
-#define LINSYSCFLUSH_LIMIT 0x047FFFFF
-
-#define LINSYSCTRL_BASE 0x04800000
-#define LINSYSCTRL_LIMIT 0x04FFFFFF
-
-#define LINSYSMTABLE_BASE 0x05000000
-#define LINSYSMTABLE_LIMIT 0x05FFFFFF
-
-#define LINSYSDIRECT_BASE 0x06000000
-#define LINSYSDIRECT_LIMIT 0x07FFFFFF
-
-#define LINLOCAL_BASE 0x08000000
-#define LINLOCAL_LIMIT 0x7FFFFFFF
-
-#define LINCORE_BASE 0x80000000
-#define LINCORE_LIMIT 0x87FFFFFF
-
-#define LINCORE_CODE_BASE 0x80000000
-#define LINCORE_CODE_LIMIT 0x81FFFFFF
-
-#define LINCORE_DATA_BASE 0x82000000
-#define LINCORE_DATA_LIMIT 0x83FFFFFF
-
-
-/* The core can support locked icache lines in this region */
-#define LINCORE_ICACHE_BASE 0x84000000
-#define LINCORE_ICACHE_LIMIT 0x85FFFFFF
-
-/* The core can support locked dcache lines in this region */
-#define LINCORE_DCACHE_BASE 0x86000000
-#define LINCORE_DCACHE_LIMIT 0x87FFFFFF
-
-#define LINGLOBAL_BASE 0x88000000
-#define LINGLOBAL_LIMIT 0xFFFDFFFF
-
-/*
- * CHIP Core Register Map
- * ----------------------
- */
-#define CORE_HWBASE 0x04800000
-#define PRIV_HWBASE 0x04810000
-#define TRIG_HWBASE 0x04820000
-#define SYSC_HWBASE 0x04830000
-
-/*****************************************************************************
- * INTER-THREAD KICK REGISTERS FOR SOFTWARE EVENT GENERATION
- ****************************************************************************/
-/*
- * These values define memory mapped registers that can be used to supply
- * kicks to threads that service arbitrary software events.
- */
-
-#define T0KICK 0x04800800 /* Background kick 0 */
-#define TXXKICK_MAX 0xFFFF /* Maximum kicks */
-#define TnXKICK_STRIDE 0x00001000 /* Thread scale value */
-#define TnXKICK_STRIDE_S 12
-#define T0KICKI 0x04800808 /* Interrupt kick 0 */
-#define TXIKICK_OFFSET 0x00000008 /* Int level offset value */
-#define T1KICK 0x04801800 /* Background kick 1 */
-#define T1KICKI 0x04801808 /* Interrupt kick 1 */
-#define T2KICK 0x04802800 /* Background kick 2 */
-#define T2KICKI 0x04802808 /* Interrupt kick 2 */
-#define T3KICK 0x04803800 /* Background kick 3 */
-#define T3KICKI 0x04803808 /* Interrupt kick 3 */
-
-/*****************************************************************************
- * GLOBAL REGISTER ACCESS RESOURCES
- ****************************************************************************/
-/*
- * These values define memory mapped registers that allow access to the
- * internal state of all threads in order to allow global set-up of thread
- * state and external handling of thread events, errors, or debugging.
- *
- * The actual unit and register index values needed to access individul
- * registers are chip specific see - METAC_TXUXX_VALUES in metac_x_y.h.
- * However two C array initialisers TXUXX_MASKS and TGUXX_MASKS will always be
- * defined to allow arbitrary loading, display, and saving of all valid
- * register states without detailed knowledge of their purpose - TXUXX sets
- * bits for all valid registers and TGUXX sets bits for the sub-set which are
- * global.
- */
-
-#define T0UCTREG0 0x04800000 /* Access to all CT regs */
-#define TnUCTRX_STRIDE 0x00001000 /* Thread scale value */
-#define TXUCTREGn_STRIDE 0x00000008 /* Register scale value */
-
-#define TXUXXRXDT 0x0480FFF0 /* Data to/from any threads reg */
-#define TXUXXRXRQ 0x0480FFF8
-#define TXUXXRXRQ_DREADY_BIT 0x80000000 /* Poll for done */
-#define TXUXXRXRQ_DSPEXT_BIT 0x00020000 /* Addr DSP Regs */
-#define TXUXXRXRQ_RDnWR_BIT 0x00010000 /* Set for read */
-#define TXUXXRXRQ_TX_BITS 0x00003000 /* Thread number */
-#define TXUXXRXRQ_TX_S 12
-#define TXUXXRXRQ_RX_BITS 0x000001F0 /* Register num */
-#define TXUXXRXRQ_RX_S 4
-#define TXUXXRXRQ_DSPRARD0 0 /* DSP RAM A Read Pointer 0 */
-#define TXUXXRXRQ_DSPRARD1 1 /* DSP RAM A Read Pointer 1 */
-#define TXUXXRXRQ_DSPRAWR0 2 /* DSP RAM A Write Pointer 0 */
-#define TXUXXRXRQ_DSPRAWR2 3 /* DSP RAM A Write Pointer 1 */
-#define TXUXXRXRQ_DSPRBRD0 4 /* DSP RAM B Read Pointer 0 */
-#define TXUXXRXRQ_DSPRBRD1 5 /* DSP RAM B Read Pointer 1 */
-#define TXUXXRXRQ_DSPRBWR0 6 /* DSP RAM B Write Pointer 0 */
-#define TXUXXRXRQ_DSPRBWR1 7 /* DSP RAM B Write Pointer 1 */
-#define TXUXXRXRQ_DSPRARINC0 8 /* DSP RAM A Read Increment 0 */
-#define TXUXXRXRQ_DSPRARINC1 9 /* DSP RAM A Read Increment 1 */
-#define TXUXXRXRQ_DSPRAWINC0 10 /* DSP RAM A Write Increment 0 */
-#define TXUXXRXRQ_DSPRAWINC1 11 /* DSP RAM A Write Increment 1 */
-#define TXUXXRXRQ_DSPRBRINC0 12 /* DSP RAM B Read Increment 0 */
-#define TXUXXRXRQ_DSPRBRINC1 13 /* DSP RAM B Read Increment 1 */
-#define TXUXXRXRQ_DSPRBWINC0 14 /* DSP RAM B Write Increment 0 */
-#define TXUXXRXRQ_DSPRBWINC1 15 /* DSP RAM B Write Increment 1 */
-
-#define TXUXXRXRQ_ACC0L0 16 /* Accumulator 0 bottom 32-bits */
-#define TXUXXRXRQ_ACC1L0 17 /* Accumulator 1 bottom 32-bits */
-#define TXUXXRXRQ_ACC2L0 18 /* Accumulator 2 bottom 32-bits */
-#define TXUXXRXRQ_ACC3L0 19 /* Accumulator 3 bottom 32-bits */
-#define TXUXXRXRQ_ACC0HI 20 /* Accumulator 0 top 8-bits */
-#define TXUXXRXRQ_ACC1HI 21 /* Accumulator 1 top 8-bits */
-#define TXUXXRXRQ_ACC2HI 22 /* Accumulator 2 top 8-bits */
-#define TXUXXRXRQ_ACC3HI 23 /* Accumulator 3 top 8-bits */
-#define TXUXXRXRQ_UXX_BITS 0x0000000F /* Unit number */
-#define TXUXXRXRQ_UXX_S 0
-
-/*****************************************************************************
- * PRIVILEGE CONTROL VALUES FOR MEMORY MAPPED RESOURCES
- ****************************************************************************/
-/*
- * These values define memory mapped registers that give control over and
- * the privilege required to access other memory mapped resources. These
- * registers themselves always require privilege to update them.
- */
-
-#define TXPRIVREG_STRIDE 0x8 /* Delta between per-thread regs */
-#define TXPRIVREG_STRIDE_S 3
-
-/*
- * Each bit 0 to 15 defines privilege required to access internal register
- * regions 0x04800000 to 0x048FFFFF in 64k chunks
- */
-#define T0PIOREG 0x04810100
-#define T1PIOREG 0x04810108
-#define T2PIOREG 0x04810110
-#define T3PIOREG 0x04810118
-
-/*
- * Each bit 0 to 31 defines privilege required to use the pair of
- * system events implemented as writee in the regions 0x04000000 to
- * 0x04000FFF in 2*64 byte chunks.
- */
-#define T0PSYREG 0x04810180
-#define T1PSYREG 0x04810188
-#define T2PSYREG 0x04810190
-#define T3PSYREG 0x04810198
-
-/*
- * CHIP PRIV CONTROLS
- * ------------------
- */
-
-/* The TXPIOREG register holds a bit mask directly mappable to
- corresponding addresses in the range 0x04800000 to 049FFFFF */
-#define TXPIOREG_ADDR_BITS 0x1F0000 /* Up to 32x64K bytes */
-#define TXPIOREG_ADDR_S 16
-
-/* Hence based on the _HWBASE values ... */
-#define TXPIOREG_CORE_BIT (1<<((0x04800000>>16)&0x1F))
-#define TXPIOREG_PRIV_BIT (1<<((0x04810000>>16)&0x1F))
-#define TXPIOREG_TRIG_BIT (1<<((0x04820000>>16)&0x1F))
-#define TXPIOREG_SYSC_BIT (1<<((0x04830000>>16)&0x1F))
-
-#define TXPIOREG_WRC_BIT 0x00080000 /* Wr combiner reg priv */
-#define TXPIOREG_LOCALBUS_RW_BIT 0x00040000 /* Local bus rd/wr priv */
-#define TXPIOREG_SYSREGBUS_RD_BIT 0x00020000 /* Sys reg bus write priv */
-#define TXPIOREG_SYSREGBUS_WR_BIT 0x00010000 /* Sys reg bus read priv */
-
-/* CORE region privilege controls */
-#define T0PRIVCORE 0x04800828
-#define TXPRIVCORE_TXBKICK_BIT 0x001 /* Background kick priv */
-#define TXPRIVCORE_TXIKICK_BIT 0x002 /* Interrupt kick priv */
-#define TXPRIVCORE_TXAMAREGX_BIT 0x004 /* TXAMAREG4|5|6 priv */
-#define TnPRIVCORE_STRIDE 0x00001000
-
-#define T0PRIVSYSR 0x04810000
-#define TnPRIVSYSR_STRIDE 0x00000008
-#define TnPRIVSYSR_STRIDE_S 3
-#define TXPRIVSYSR_CFLUSH_BIT 0x01
-#define TXPRIVSYSR_MTABLE_BIT 0x02
-#define TXPRIVSYSR_DIRECT_BIT 0x04
-#ifdef METAC_1_2
-#define TXPRIVSYSR_ALL_BITS 0x07
-#else
-#define TXPRIVSYSR_CORE_BIT 0x08
-#define TXPRIVSYSR_CORECODE_BIT 0x10
-#define TXPRIVSYSR_ALL_BITS 0x1F
-#endif
-#define T1PRIVSYSR 0x04810008
-#define T2PRIVSYSR 0x04810010
-#define T3PRIVSYSR 0x04810018
-
-/*****************************************************************************
- * H/W TRIGGER STATE/LEVEL REGISTERS AND H/W TRIGGER VECTORS
- ****************************************************************************/
-/*
- * These values define memory mapped registers that give control over and
- * the state of hardware trigger sources both external to the META processor
- * and internal to it.
- */
-
-#define HWSTATMETA 0x04820000 /* Hardware status/clear META trig */
-#define HWSTATMETA_T0HALT_BITS 0xF
-#define HWSTATMETA_T0HALT_S 0
-#define HWSTATMETA_T0BHALT_BIT 0x1 /* Background HALT */
-#define HWSTATMETA_T0IHALT_BIT 0x2 /* Interrupt HALT */
-#define HWSTATMETA_T0PHALT_BIT 0x4 /* PF/RO Memory HALT */
-#define HWSTATMETA_T0AMATR_BIT 0x8 /* AMA trigger */
-#define HWSTATMETA_TnINT_S 4 /* Shift by (thread*4) */
-#define HWSTATEXT 0x04820010 /* H/W status/clear external trigs 0-31 */
-#define HWSTATEXT2 0x04820018 /* H/W status/clear external trigs 32-63 */
-#define HWSTATEXT4 0x04820020 /* H/W status/clear external trigs 64-95 */
-#define HWSTATEXT6 0x04820028 /* H/W status/clear external trigs 96-128 */
-#define HWLEVELEXT 0x04820030 /* Edge/Level type of external trigs 0-31 */
-#define HWLEVELEXT2 0x04820038 /* Edge/Level type of external trigs 32-63 */
-#define HWLEVELEXT4 0x04820040 /* Edge/Level type of external trigs 64-95 */
-#define HWLEVELEXT6 0x04820048 /* Edge/Level type of external trigs 96-128 */
-#define HWLEVELEXT_XXX_LEVEL 1 /* Level sense logic in HWSTATEXTn */
-#define HWLEVELEXT_XXX_EDGE 0
-#define HWMASKEXT 0x04820050 /* Enable/disable of external trigs 0-31 */
-#define HWMASKEXT2 0x04820058 /* Enable/disable of external trigs 32-63 */
-#define HWMASKEXT4 0x04820060 /* Enable/disable of external trigs 64-95 */
-#define HWMASKEXT6 0x04820068 /* Enable/disable of external trigs 96-128 */
-#define T0VECINT_BHALT 0x04820500 /* Background HALT trigger vector */
-#define TXVECXXX_BITS 0xF /* Per-trigger vector vals 0,1,4-15 */
-#define TXVECXXX_S 0
-#define T0VECINT_IHALT 0x04820508 /* Interrupt HALT */
-#define T0VECINT_PHALT 0x04820510 /* PF/RO memory fault */
-#define T0VECINT_AMATR 0x04820518 /* AMA trigger */
-#define TnVECINT_STRIDE 0x00000020 /* Per thread stride */
-#define HWVEC0EXT 0x04820700 /* Vectors for external triggers 0-31 */
-#define HWVEC20EXT 0x04821700 /* Vectors for external triggers 32-63 */
-#define HWVEC40EXT 0x04822700 /* Vectors for external triggers 64-95 */
-#define HWVEC60EXT 0x04823700 /* Vectors for external triggers 96-127 */
-#define HWVECnEXT_STRIDE 0x00000008 /* Per trigger stride */
-#define HWVECnEXT_DEBUG 0x1 /* Redirect trigger to debug i/f */
-
-/*
- * CORE HWCODE-BREAKPOINT REGISTERS/VALUES
- * ---------------------------------------
- */
-#define CODEB0ADDR 0x0480FF00 /* Address specifier */
-#define CODEBXADDR_MATCHX_BITS 0xFFFFFFFC
-#define CODEBXADDR_MATCHX_S 2
-#define CODEB0CTRL 0x0480FF08 /* Control */
-#define CODEBXCTRL_MATEN_BIT 0x80000000 /* Match 'Enable' */
-#define CODEBXCTRL_MATTXEN_BIT 0x10000000 /* Match threadn enable */
-#define CODEBXCTRL_HITC_BITS 0x00FF0000 /* Hit counter */
-#define CODEBXCTRL_HITC_S 16
-#define CODEBXHITC_NEXT 0xFF /* Next 'hit' will trigger */
-#define CODEBXHITC_HIT1 0x00 /* No 'hits' after trigger */
-#define CODEBXCTRL_MMASK_BITS 0x0000FFFC /* Mask ADDR_MATCH bits */
-#define CODEBXCTRL_MMASK_S 2
-#define CODEBXCTRL_MATLTX_BITS 0x00000003 /* Match threadn LOCAL addr */
-#define CODEBXCTRL_MATLTX_S 0 /* Match threadn LOCAL addr */
-#define CODEBnXXXX_STRIDE 0x00000010 /* Stride between CODEB reg sets */
-#define CODEBnXXXX_STRIDE_S 4
-#define CODEBnXXXX_LIMIT 3 /* Sets 0-3 */
-
-/*
- * CORE DATA-WATCHPOINT REGISTERS/VALUES
- * -------------------------------------
- */
-#define DATAW0ADDR 0x0480FF40 /* Address specifier */
-#define DATAWXADDR_MATCHR_BITS 0xFFFFFFF8
-#define DATAWXADDR_MATCHR_S 3
-#define DATAWXADDR_MATCHW_BITS 0xFFFFFFFF
-#define DATAWXADDR_MATCHW_S 0
-#define DATAW0CTRL 0x0480FF48 /* Control */
-#define DATAWXCTRL_MATRD_BIT 0x80000000 /* Match 'Read' */
-#ifndef METAC_1_2
-#define DATAWXCTRL_MATNOTTX_BIT 0x20000000 /* Invert threadn enable */
-#endif
-#define DATAWXCTRL_MATWR_BIT 0x40000000 /* Match 'Write' */
-#define DATAWXCTRL_MATTXEN_BIT 0x10000000 /* Match threadn enable */
-#define DATAWXCTRL_WRSIZE_BITS 0x0F000000 /* Write Match Size */
-#define DATAWXCTRL_WRSIZE_S 24
-#define DATAWWRSIZE_ANY 0 /* Any size transaction matches */
-#define DATAWWRSIZE_8BIT 1 /* Specific sizes ... */
-#define DATAWWRSIZE_16BIT 2
-#define DATAWWRSIZE_32BIT 3
-#define DATAWWRSIZE_64BIT 4
-#define DATAWXCTRL_HITC_BITS 0x00FF0000 /* Hit counter */
-#define DATAWXCTRL_HITC_S 16
-#define DATAWXHITC_NEXT 0xFF /* Next 'hit' will trigger */
-#define DATAWXHITC_HIT1 0x00 /* No 'hits' after trigger */
-#define DATAWXCTRL_MMASK_BITS 0x0000FFF8 /* Mask ADDR_MATCH bits */
-#define DATAWXCTRL_MMASK_S 3
-#define DATAWXCTRL_MATLTX_BITS 0x00000003 /* Match threadn LOCAL addr */
-#define DATAWXCTRL_MATLTX_S 0 /* Match threadn LOCAL addr */
-#define DATAW0DMATCH0 0x0480FF50 /* Write match data */
-#define DATAW0DMATCH1 0x0480FF58
-#define DATAW0DMASK0 0x0480FF60 /* Write match data mask */
-#define DATAW0DMASK1 0x0480FF68
-#define DATAWnXXXX_STRIDE 0x00000040 /* Stride between DATAW reg sets */
-#define DATAWnXXXX_STRIDE_S 6
-#define DATAWnXXXX_LIMIT 1 /* Sets 0,1 */
-
-/*
- * CHIP Automatic Mips Allocation control registers
- * ------------------------------------------------
- */
-
-/* CORE memory mapped AMA registers */
-#define T0AMAREG4 0x04800810
-#define TXAMAREG4_POOLSIZE_BITS 0x3FFFFF00
-#define TXAMAREG4_POOLSIZE_S 8
-#define TXAMAREG4_AVALUE_BITS 0x000000FF
-#define TXAMAREG4_AVALUE_S 0
-#define T0AMAREG5 0x04800818
-#define TXAMAREG5_POOLC_BITS 0x07FFFFFF
-#define TXAMAREG5_POOLC_S 0
-#define T0AMAREG6 0x04800820
-#define TXAMAREG6_DLINEDEF_BITS 0x00FFFFF0
-#define TXAMAREG6_DLINEDEF_S 0
-#define TnAMAREGX_STRIDE 0x00001000
-
-/*
- * Memory Management Control Unit Table Entries
- * --------------------------------------------
- */
-#define MMCU_ENTRY_S 4 /* -> Entry size */
-#define MMCU_ENTRY_ADDR_BITS 0xFFFFF000 /* Physical address */
-#define MMCU_ENTRY_ADDR_S 12 /* -> Page size */
-#define MMCU_ENTRY_CWIN_BITS 0x000000C0 /* Caching 'window' selection */
-#define MMCU_ENTRY_CWIN_S 6
-#define MMCU_CWIN_UNCACHED 0 /* May not be memory etc. */
-#define MMCU_CWIN_BURST 1 /* Cached but LRU unset */
-#define MMCU_CWIN_C1SET 2 /* Cached in 1 set only */
-#define MMCU_CWIN_CACHED 3 /* Fully cached */
-#define MMCU_ENTRY_CACHE_BIT 0x00000080 /* Set for cached region */
-#define MMCU_ECACHE1_FULL_BIT 0x00000040 /* Use all the sets */
-#define MMCU_ECACHE0_BURST_BIT 0x00000040 /* Match bursts */
-#define MMCU_ENTRY_SYS_BIT 0x00000010 /* Sys-coherent access required */
-#define MMCU_ENTRY_WRC_BIT 0x00000008 /* Write combining allowed */
-#define MMCU_ENTRY_PRIV_BIT 0x00000004 /* Privilege required */
-#define MMCU_ENTRY_WR_BIT 0x00000002 /* Writes allowed */
-#define MMCU_ENTRY_VAL_BIT 0x00000001 /* Entry is valid */
-
-#ifdef METAC_2_1
-/*
- * Extended first-level/top table entries have extra/larger fields in later
- * cores as bits 11:0 previously had no effect in such table entries.
- */
-#define MMCU_E1ENT_ADDR_BITS 0xFFFFFFC0 /* Physical address */
-#define MMCU_E1ENT_ADDR_S 6 /* -> resolution < page size */
-#define MMCU_E1ENT_PGSZ_BITS 0x0000001E /* Page size for 2nd level */
-#define MMCU_E1ENT_PGSZ_S 1
-#define MMCU_E1ENT_PGSZ0_POWER 12 /* PgSz 0 -> 4K */
-#define MMCU_E1ENT_PGSZ_MAX 10 /* PgSz 10 -> 4M maximum */
-#define MMCU_E1ENT_MINIM_BIT 0x00000020
-#endif /* METAC_2_1 */
-
-/* MMCU control register in SYSC region */
-#define MMCU_TABLE_PHYS_ADDR 0x04830010
-#define MMCU_TABLE_PHYS_ADDR_BITS 0xFFFFFFFC
-#ifdef METAC_2_1
-#define MMCU_TABLE_PHYS_EXTEND 0x00000001 /* See below */
-#endif
-#define MMCU_DCACHE_CTRL_ADDR 0x04830018
-#define MMCU_xCACHE_CTRL_ENABLE_BIT 0x00000001
-#define MMCU_xCACHE_CTRL_PARTITION_BIT 0x00000000 /* See xCPART below */
-#define MMCU_ICACHE_CTRL_ADDR 0x04830020
-
-#ifdef METAC_2_1
-
-/*
- * Allow direct access to physical memory used to implement MMU table.
- *
- * Each is based on a corresponding MMCU_TnLOCAL_TABLE_PHYSn or similar
- * MMCU_TnGLOBAL_TABLE_PHYSn register pair (see next).
- */
-#define LINSYSMEMT0L_BASE 0x05000000
-#define LINSYSMEMT0L_LIMIT 0x051FFFFF
-#define LINSYSMEMTnX_STRIDE 0x00200000 /* 2MB Local per thread */
-#define LINSYSMEMTnX_STRIDE_S 21
-#define LINSYSMEMTXG_OFFSET 0x00800000 /* +2MB Global per thread */
-#define LINSYSMEMTXG_OFFSET_S 23
-#define LINSYSMEMT1L_BASE 0x05200000
-#define LINSYSMEMT1L_LIMIT 0x053FFFFF
-#define LINSYSMEMT2L_BASE 0x05400000
-#define LINSYSMEMT2L_LIMIT 0x055FFFFF
-#define LINSYSMEMT3L_BASE 0x05600000
-#define LINSYSMEMT3L_LIMIT 0x057FFFFF
-#define LINSYSMEMT0G_BASE 0x05800000
-#define LINSYSMEMT0G_LIMIT 0x059FFFFF
-#define LINSYSMEMT1G_BASE 0x05A00000
-#define LINSYSMEMT1G_LIMIT 0x05BFFFFF
-#define LINSYSMEMT2G_BASE 0x05C00000
-#define LINSYSMEMT2G_LIMIT 0x05DFFFFF
-#define LINSYSMEMT3G_BASE 0x05E00000
-#define LINSYSMEMT3G_LIMIT 0x05FFFFFF
-
-/*
- * Extended MMU table functionality allows a sparse or flat table to be
- * described much more efficiently than before.
- */
-#define MMCU_T0LOCAL_TABLE_PHYS0 0x04830700
-#define MMCU_TnX_TABLE_PHYSX_STRIDE 0x20 /* Offset per thread */
-#define MMCU_TnX_TABLE_PHYSX_STRIDE_S 5
-#define MMCU_TXG_TABLE_PHYSX_OFFSET 0x10 /* Global versus local */
-#define MMCU_TXG_TABLE_PHYSX_OFFSET_S 4
-#define MMCU_TBLPHYS0_DCCTRL_BITS 0x000000DF /* DC controls */
-#define MMCU_TBLPHYS0_ENTLB_BIT 0x00000020 /* Cache in TLB */
-#define MMCU_TBLPHYS0_TBLSZ_BITS 0x00000F00 /* Area supported */
-#define MMCU_TBLPHYS0_TBLSZ_S 8
-#define MMCU_TBLPHYS0_TBLSZ0_POWER 22 /* 0 -> 4M */
-#define MMCU_TBLPHYS0_TBLSZ_MAX 9 /* 9 -> 2G */
-#define MMCU_TBLPHYS0_LINBASE_BITS 0xFFC00000 /* Linear base */
-#define MMCU_TBLPHYS0_LINBASE_S 22
-
-#define MMCU_T0LOCAL_TABLE_PHYS1 0x04830708
-#define MMCU_TBLPHYS1_ADDR_BITS 0xFFFFFFFC /* Physical base */
-#define MMCU_TBLPHYS1_ADDR_S 2
-
-#define MMCU_T0GLOBAL_TABLE_PHYS0 0x04830710
-#define MMCU_T0GLOBAL_TABLE_PHYS1 0x04830718
-#define MMCU_T1LOCAL_TABLE_PHYS0 0x04830720
-#define MMCU_T1LOCAL_TABLE_PHYS1 0x04830728
-#define MMCU_T1GLOBAL_TABLE_PHYS0 0x04830730
-#define MMCU_T1GLOBAL_TABLE_PHYS1 0x04830738
-#define MMCU_T2LOCAL_TABLE_PHYS0 0x04830740
-#define MMCU_T2LOCAL_TABLE_PHYS1 0x04830748
-#define MMCU_T2GLOBAL_TABLE_PHYS0 0x04830750
-#define MMCU_T2GLOBAL_TABLE_PHYS1 0x04830758
-#define MMCU_T3LOCAL_TABLE_PHYS0 0x04830760
-#define MMCU_T3LOCAL_TABLE_PHYS1 0x04830768
-#define MMCU_T3GLOBAL_TABLE_PHYS0 0x04830770
-#define MMCU_T3GLOBAL_TABLE_PHYS1 0x04830778
-
-#define MMCU_T0EBWCCTRL 0x04830640
-#define MMCU_TnEBWCCTRL_BITS 0x00000007
-#define MMCU_TnEBWCCTRL_S 0
-#define MMCU_TnEBWCCCTRL_DISABLE_ALL 0
-#define MMCU_TnEBWCCCTRL_ABIT25 1
-#define MMCU_TnEBWCCCTRL_ABIT26 2
-#define MMCU_TnEBWCCCTRL_ABIT27 3
-#define MMCU_TnEBWCCCTRL_ABIT28 4
-#define MMCU_TnEBWCCCTRL_ABIT29 5
-#define MMCU_TnEBWCCCTRL_ABIT30 6
-#define MMCU_TnEBWCCCTRL_ENABLE_ALL 7
-#define MMCU_TnEBWCCTRL_STRIDE 8
-
-#endif /* METAC_2_1 */
-
-
-/* Registers within the SYSC register region */
-#define METAC_ID 0x04830000
-#define METAC_ID_MAJOR_BITS 0xFF000000
-#define METAC_ID_MAJOR_S 24
-#define METAC_ID_MINOR_BITS 0x00FF0000
-#define METAC_ID_MINOR_S 16
-#define METAC_ID_REV_BITS 0x0000FF00
-#define METAC_ID_REV_S 8
-#define METAC_ID_MAINT_BITS 0x000000FF
-#define METAC_ID_MAINT_S 0
-
-#ifdef METAC_2_1
-/* Use of this section is strongly deprecated */
-#define METAC_ID2 0x04830008
-#define METAC_ID2_DESIGNER_BITS 0xFFFF0000 /* Modified by customer */
-#define METAC_ID2_DESIGNER_S 16
-#define METAC_ID2_MINOR2_BITS 0x00000F00 /* 3rd digit of prod rev */
-#define METAC_ID2_MINOR2_S 8
-#define METAC_ID2_CONFIG_BITS 0x000000FF /* Wrapper configuration */
-#define METAC_ID2_CONFIG_S 0
-
-/* Primary core identification and configuration information */
-#define METAC_CORE_ID 0x04831000
-#define METAC_COREID_GROUP_BITS 0xFF000000
-#define METAC_COREID_GROUP_S 24
-#define METAC_COREID_GROUP_METAG 0x14
-#define METAC_COREID_ID_BITS 0x00FF0000
-#define METAC_COREID_ID_S 16
-#define METAC_COREID_ID_W32 0x10 /* >= for 32-bit pipeline */
-#define METAC_COREID_CONFIG_BITS 0x0000FFFF
-#define METAC_COREID_CONFIG_S 0
-#define METAC_COREID_CFGCACHE_BITS 0x0007
-#define METAC_COREID_CFGCACHE_S 0
-#define METAC_COREID_CFGCACHE_NOM 0
-#define METAC_COREID_CFGCACHE_TYPE0 1
-#define METAC_COREID_CFGCACHE_NOMMU 1 /* Alias for TYPE0 */
-#define METAC_COREID_CFGCACHE_NOCACHE 2
-#define METAC_COREID_CFGCACHE_PRIVNOMMU 3
-#define METAC_COREID_CFGDSP_BITS 0x0038
-#define METAC_COREID_CFGDSP_S 3
-#define METAC_COREID_CFGDSP_NOM 0
-#define METAC_COREID_CFGDSP_MIN 1
-#define METAC_COREID_NOFPACC_BIT 0x0040 /* Set if no FPU accum */
-#define METAC_COREID_CFGFPU_BITS 0x0180
-#define METAC_COREID_CFGFPU_S 7
-#define METAC_COREID_CFGFPU_NOM 0
-#define METAC_COREID_CFGFPU_SNGL 1
-#define METAC_COREID_CFGFPU_DBL 2
-#define METAC_COREID_NOAMA_BIT 0x0200 /* Set if no AMA present */
-#define METAC_COREID_NOCOH_BIT 0x0400 /* Set if no Gbl coherency */
-
-/* Core revision information */
-#define METAC_CORE_REV 0x04831008
-#define METAC_COREREV_DESIGN_BITS 0xFF000000
-#define METAC_COREREV_DESIGN_S 24
-#define METAC_COREREV_MAJOR_BITS 0x00FF0000
-#define METAC_COREREV_MAJOR_S 16
-#define METAC_COREREV_MINOR_BITS 0x0000FF00
-#define METAC_COREREV_MINOR_S 8
-#define METAC_COREREV_MAINT_BITS 0x000000FF
-#define METAC_COREREV_MAINT_S 0
-
-/* Configuration information control outside the core */
-#define METAC_CORE_DESIGNER1 0x04831010 /* Arbitrary value */
-#define METAC_CORE_DESIGNER2 0x04831018 /* Arbitrary value */
-
-/* Configuration information covering presence/number of various features */
-#define METAC_CORE_CONFIG2 0x04831020
-#define METAC_CORECFG2_COREDBGTYPE_BITS 0x60000000 /* Core debug type */
-#define METAC_CORECFG2_COREDBGTYPE_S 29
-#define METAC_CORECFG2_DCSMALL_BIT 0x04000000 /* Data cache small */
-#define METAC_CORECFG2_ICSMALL_BIT 0x02000000 /* Inst cache small */
-#define METAC_CORECFG2_DCSZNP_BITS 0x01C00000 /* Data cache size np */
-#define METAC_CORECFG2_DCSZNP_S 22
-#define METAC_CORECFG2_ICSZNP_BITS 0x00380000 /* Inst cache size np */
-#define METAC_CORECFG2_ICSZNP_S 19
-#define METAC_CORECFG2_DCSZ_BITS 0x00070000 /* Data cache size */
-#define METAC_CORECFG2_DCSZ_S 16
-#define METAC_CORECFG2_xCSZ_4K 0 /* Allocated values */
-#define METAC_CORECFG2_xCSZ_8K 1
-#define METAC_CORECFG2_xCSZ_16K 2
-#define METAC_CORECFG2_xCSZ_32K 3
-#define METAC_CORECFG2_xCSZ_64K 4
-#define METAC_CORE_C2ICSZ_BITS 0x0000E000 /* Inst cache size */
-#define METAC_CORE_C2ICSZ_S 13
-#define METAC_CORE_GBLACC_BITS 0x00001800 /* Number of Global Acc */
-#define METAC_CORE_GBLACC_S 11
-#define METAC_CORE_GBLDXR_BITS 0x00000700 /* 0 -> 0, R -> 2^(R-1) */
-#define METAC_CORE_GBLDXR_S 8
-#define METAC_CORE_GBLAXR_BITS 0x000000E0 /* 0 -> 0, R -> 2^(R-1) */
-#define METAC_CORE_GBLAXR_S 5
-#define METAC_CORE_RTTRACE_BIT 0x00000010
-#define METAC_CORE_WATCHN_BITS 0x0000000C /* 0 -> 0, N -> 2^N */
-#define METAC_CORE_WATCHN_S 2
-#define METAC_CORE_BREAKN_BITS 0x00000003 /* 0 -> 0, N -> 2^N */
-#define METAC_CORE_BREAKN_S 0
-
-/* Configuration information covering presence/number of various features */
-#define METAC_CORE_CONFIG3 0x04831028
-#define METAC_CORECFG3_L2C_REV_ID_BITS 0x000F0000 /* Revision of L2 cache */
-#define METAC_CORECFG3_L2C_REV_ID_S 16
-#define METAC_CORECFG3_L2C_LINE_SIZE_BITS 0x00003000 /* L2 line size */
-#define METAC_CORECFG3_L2C_LINE_SIZE_S 12
-#define METAC_CORECFG3_L2C_LINE_SIZE_64B 0x0 /* 64 bytes */
-#define METAC_CORECFG3_L2C_NUM_WAYS_BITS 0x00000F00 /* L2 number of ways (2^n) */
-#define METAC_CORECFG3_L2C_NUM_WAYS_S 8
-#define METAC_CORECFG3_L2C_SIZE_BITS 0x000000F0 /* L2 size (2^n) */
-#define METAC_CORECFG3_L2C_SIZE_S 4
-#define METAC_CORECFG3_L2C_UNIFIED_BIT 0x00000004 /* Unified cache: */
-#define METAC_CORECFG3_L2C_UNIFIED_S 2
-#define METAC_CORECFG3_L2C_UNIFIED_UNIFIED 1 /* - Unified D/I cache */
-#define METAC_CORECFG3_L2C_UNIFIED_SEPARATE 0 /* - Separate D/I cache */
-#define METAC_CORECFG3_L2C_MODE_BIT 0x00000002 /* Cache Mode: */
-#define METAC_CORECFG3_L2C_MODE_S 1
-#define METAC_CORECFG3_L2C_MODE_WRITE_BACK 1 /* - Write back */
-#define METAC_CORECFG3_L2C_MODE_WRITE_THROUGH 0 /* - Write through */
-#define METAC_CORECFG3_L2C_HAVE_L2C_BIT 0x00000001 /* Have L2C */
-#define METAC_CORECFG3_L2C_HAVE_L2C_S 0
-
-#endif /* METAC_2_1 */
-
-#define SYSC_CACHE_MMU_CONFIG 0x04830028
-#ifdef METAC_2_1
-#define SYSC_CMMUCFG_DCSKEWABLE_BIT 0x00000040
-#define SYSC_CMMUCFG_ICSKEWABLE_BIT 0x00000020
-#define SYSC_CMMUCFG_DCSKEWOFF_BIT 0x00000010 /* Skew association override */
-#define SYSC_CMMUCFG_ICSKEWOFF_BIT 0x00000008 /* -> default 0 on if present */
-#define SYSC_CMMUCFG_MODE_BITS 0x00000007 /* Access to old state */
-#define SYSC_CMMUCFG_MODE_S 0
-#define SYSC_CMMUCFG_ON 0x7
-#define SYSC_CMMUCFG_EBYPASS 0x6 /* Enhanced by-pass mode */
-#define SYSC_CMMUCFG_EBYPASSIC 0x4 /* EB just inst cache */
-#define SYSC_CMMUCFG_EBYPASSDC 0x2 /* EB just data cache */
-#endif /* METAC_2_1 */
-/* Old definitions, Keep them for now */
-#define SYSC_CMMUCFG_MMU_ON_BIT 0x1
-#define SYSC_CMMUCFG_DC_ON_BIT 0x2
-#define SYSC_CMMUCFG_IC_ON_BIT 0x4
-
-#define SYSC_JTAG_THREAD 0x04830030
-#define SYSC_JTAG_TX_BITS 0x00000003 /* Read only bits! */
-#define SYSC_JTAG_TX_S 0
-#define SYSC_JTAG_PRIV_BIT 0x00000004
-#ifdef METAC_2_1
-#define SYSC_JTAG_SLAVETX_BITS 0x00000018
-#define SYSC_JTAG_SLAVETX_S 3
-#endif /* METAC_2_1 */
-
-#define SYSC_DCACHE_FLUSH 0x04830038
-#define SYSC_ICACHE_FLUSH 0x04830040
-#define SYSC_xCACHE_FLUSH_INIT 0x1
-#define MMCU_DIRECTMAP0_ADDR 0x04830080 /* LINSYSDIRECT_BASE -> */
-#define MMCU_DIRECTMAPn_STRIDE 0x00000010 /* 4 Region settings */
-#define MMCU_DIRECTMAPn_S 4
-#define MMCU_DIRECTMAPn_ADDR_BITS 0xFF800000
-#define MMCU_DIRECTMAPn_ADDR_S 23
-#define MMCU_DIRECTMAPn_ADDR_SCALE 0x00800000 /* 8M Regions */
-#ifdef METAC_2_1
-/*
- * These fields in the above registers provide MMCU_ENTRY_* values
- * for each direct mapped region to enable optimisation of these areas.
- * (LSB similar to VALID must be set for enhancments to be active)
- */
-#define MMCU_DIRECTMAPn_ENHANCE_BIT 0x00000001 /* 0 = no optim */
-#define MMCU_DIRECTMAPn_DCCTRL_BITS 0x000000DF /* Get DC Ctrl */
-#define MMCU_DIRECTMAPn_DCCTRL_S 0
-#define MMCU_DIRECTMAPn_ICCTRL_BITS 0x0000C000 /* Get IC Ctrl */
-#define MMCU_DIRECTMAPn_ICCTRL_S 8
-#define MMCU_DIRECTMAPn_ENTLB_BIT 0x00000020 /* Cache in TLB */
-#define MMCU_DIRECTMAPn_ICCWIN_BITS 0x0000C000 /* Get IC Win Bits */
-#define MMCU_DIRECTMAPn_ICCWIN_S 14
-#endif /* METAC_2_1 */
-
-#define MMCU_DIRECTMAP1_ADDR 0x04830090
-#define MMCU_DIRECTMAP2_ADDR 0x048300a0
-#define MMCU_DIRECTMAP3_ADDR 0x048300b0
-
-/*
- * These bits partion each threads use of data cache or instruction cache
- * resource by modifying the top 4 bits of the address within the cache
- * storage area.
- */
-#define SYSC_DCPART0 0x04830200
-#define SYSC_xCPARTn_STRIDE 0x00000008
-#define SYSC_xCPARTL_AND_BITS 0x0000000F /* Masks top 4 bits */
-#define SYSC_xCPARTL_AND_S 0
-#define SYSC_xCPARTG_AND_BITS 0x00000F00 /* Masks top 4 bits */
-#define SYSC_xCPARTG_AND_S 8
-#define SYSC_xCPARTL_OR_BITS 0x000F0000 /* Ors into top 4 bits */
-#define SYSC_xCPARTL_OR_S 16
-#ifdef METAC_2_1
-#define SYSC_DCPART_GCON_BIT 0x00100000 /* Coherent shared local */
-#endif /* METAC_2_1 */
-#define SYSC_xCPARTG_OR_BITS 0x0F000000 /* Ors into top 4 bits */
-#define SYSC_xCPARTG_OR_S 24
-#define SYSC_CWRMODE_BIT 0x80000000 /* Write cache mode bit */
-
-#define SYSC_DCPART1 0x04830208
-#define SYSC_DCPART2 0x04830210
-#define SYSC_DCPART3 0x04830218
-#define SYSC_ICPART0 0x04830220
-#define SYSC_ICPART1 0x04830228
-#define SYSC_ICPART2 0x04830230
-#define SYSC_ICPART3 0x04830238
-
-/*
- * META Core Memory and Cache Update registers
- */
-#define SYSC_MCMDATAX 0x04830300 /* 32-bit read/write data register */
-#define SYSC_MCMDATAT 0x04830308 /* Read or write data triggers oper */
-#define SYSC_MCMGCTRL 0x04830310 /* Control register */
-#define SYSC_MCMGCTRL_READ_BIT 0x00000001 /* Set to issue 1st read */
-#define SYSC_MCMGCTRL_AINC_BIT 0x00000002 /* Set for auto-increment */
-#define SYSC_MCMGCTRL_ADDR_BITS 0x000FFFFC /* Address or index */
-#define SYSC_MCMGCTRL_ADDR_S 2
-#define SYSC_MCMGCTRL_ID_BITS 0x0FF00000 /* Internal memory block Id */
-#define SYSC_MCMGCTRL_ID_S 20
-#define SYSC_MCMGID_NODEV 0xFF /* No Device Selected */
-#define SYSC_MCMGID_DSPRAM0A 0x04 /* DSP RAM D0 block A access */
-#define SYSC_MCMGID_DSPRAM0B 0x05 /* DSP RAM D0 block B access */
-#define SYSC_MCMGID_DSPRAM1A 0x06 /* DSP RAM D1 block A access */
-#define SYSC_MCMGID_DSPRAM1B 0x07 /* DSP RAM D1 block B access */
-#define SYSC_MCMGID_DCACHEL 0x08 /* DCACHE lines (64-bytes/line) */
-#ifdef METAC_2_1
-#define SYSC_MCMGID_DCACHETLB 0x09 /* DCACHE TLB ( Read Only ) */
-#endif /* METAC_2_1 */
-#define SYSC_MCMGID_DCACHET 0x0A /* DCACHE tags (32-bits/line) */
-#define SYSC_MCMGID_DCACHELRU 0x0B /* DCACHE LRU (8-bits/line) */
-#define SYSC_MCMGID_ICACHEL 0x0C /* ICACHE lines (64-bytes/line */
-#ifdef METAC_2_1
-#define SYSC_MCMGID_ICACHETLB 0x0D /* ICACHE TLB (Read Only ) */
-#endif /* METAC_2_1 */
-#define SYSC_MCMGID_ICACHET 0x0E /* ICACHE Tags (32-bits/line) */
-#define SYSC_MCMGID_ICACHELRU 0x0F /* ICACHE LRU (8-bits/line ) */
-#define SYSC_MCMGID_COREIRAM0 0x10 /* Core code mem id 0 */
-#define SYSC_MCMGID_COREIRAMn 0x17
-#define SYSC_MCMGID_COREDRAM0 0x18 /* Core data mem id 0 */
-#define SYSC_MCMGID_COREDRAMn 0x1F
-#ifdef METAC_2_1
-#define SYSC_MCMGID_DCACHEST 0x20 /* DCACHE ST ( Read Only ) */
-#define SYSC_MCMGID_ICACHEST 0x21 /* ICACHE ST ( Read Only ) */
-#define SYSC_MCMGID_DCACHETLBLRU 0x22 /* DCACHE TLB LRU ( Read Only )*/
-#define SYSC_MCMGID_ICACHETLBLRU 0x23 /* ICACHE TLB LRU( Read Only ) */
-#define SYSC_MCMGID_DCACHESTLRU 0x24 /* DCACHE ST LRU ( Read Only ) */
-#define SYSC_MCMGID_ICACHESTLRU 0x25 /* ICACHE ST LRU ( Read Only ) */
-#define SYSC_MCMGID_DEBUGTLB 0x26 /* DEBUG TLB ( Read Only ) */
-#define SYSC_MCMGID_DEBUGST 0x27 /* DEBUG ST ( Read Only ) */
-#define SYSC_MCMGID_L2CACHEL 0x30 /* L2 Cache Lines (64-bytes/line) */
-#define SYSC_MCMGID_L2CACHET 0x31 /* L2 Cache Tags (32-bits/line) */
-#define SYSC_MCMGID_COPROX0 0x70 /* Coprocessor port id 0 */
-#define SYSC_MCMGID_COPROXn 0x77
-#endif /* METAC_2_1 */
-#define SYSC_MCMGCTRL_TR31_BIT 0x80000000 /* Trigger 31 on completion */
-#define SYSC_MCMSTATUS 0x04830318 /* Status read only */
-#define SYSC_MCMSTATUS_IDLE_BIT 0x00000001
-
-/* META System Events */
-#define SYSC_SYS_EVENT 0x04830400
-#define SYSC_SYSEVT_ATOMIC_BIT 0x00000001
-#define SYSC_SYSEVT_CACHEX_BIT 0x00000002
-#define SYSC_ATOMIC_LOCK 0x04830408
-#define SYSC_ATOMIC_STATE_TX_BITS 0x0000000F
-#define SYSC_ATOMIC_STATE_TX_S 0
-#ifdef METAC_1_2
-#define SYSC_ATOMIC_STATE_DX_BITS 0x000000F0
-#define SYSC_ATOMIC_STATE_DX_S 4
-#else /* METAC_1_2 */
-#define SYSC_ATOMIC_SOURCE_BIT 0x00000010
-#endif /* !METAC_1_2 */
-
-
-#ifdef METAC_2_1
-
-/* These definitions replace the EXPAND_TIMER_DIV register defines which are to
- * be deprecated.
- */
-#define SYSC_TIMER_DIV 0x04830140
-#define SYSC_TIMDIV_BITS 0x000000FF
-#define SYSC_TIMDIV_S 0
-
-/* META Enhanced by-pass control for local and global region */
-#define MMCU_LOCAL_EBCTRL 0x04830600
-#define MMCU_GLOBAL_EBCTRL 0x04830608
-#define MMCU_EBCTRL_SINGLE_BIT 0x00000020 /* TLB Uncached */
-/*
- * These fields in the above registers provide MMCU_ENTRY_* values
- * for each direct mapped region to enable optimisation of these areas.
- */
-#define MMCU_EBCTRL_DCCTRL_BITS 0x000000C0 /* Get DC Ctrl */
-#define MMCU_EBCTRL_DCCTRL_S 0
-#define MMCU_EBCTRL_ICCTRL_BITS 0x0000C000 /* Get DC Ctrl */
-#define MMCU_EBCTRL_ICCTRL_S 8
-
-/* META Cached Core Mode Registers */
-#define MMCU_T0CCM_ICCTRL 0x04830680 /* Core cached code control */
-#define MMCU_TnCCM_xxCTRL_STRIDE 8
-#define MMCU_TnCCM_xxCTRL_STRIDE_S 3
-#define MMCU_T1CCM_ICCTRL 0x04830688
-#define MMCU_T2CCM_ICCTRL 0x04830690
-#define MMCU_T3CCM_ICCTRL 0x04830698
-#define MMCU_T0CCM_DCCTRL 0x048306C0 /* Core cached data control */
-#define MMCU_T1CCM_DCCTRL 0x048306C8
-#define MMCU_T2CCM_DCCTRL 0x048306D0
-#define MMCU_T3CCM_DCCTRL 0x048306D8
-#define MMCU_TnCCM_ENABLE_BIT 0x00000001
-#define MMCU_TnCCM_WIN3_BIT 0x00000002
-#define MMCU_TnCCM_DCWRITE_BIT 0x00000004 /* In DCCTRL only */
-#define MMCU_TnCCM_REGSZ_BITS 0x00000F00
-#define MMCU_TnCCM_REGSZ_S 8
-#define MMCU_TnCCM_REGSZ0_POWER 12 /* RegSz 0 -> 4K */
-#define MMCU_TnCCM_REGSZ_MAXBYTES 0x00080000 /* 512K max */
-#define MMCU_TnCCM_ADDR_BITS 0xFFFFF000
-#define MMCU_TnCCM_ADDR_S 12
-
-#endif /* METAC_2_1 */
-
-/*
- * Hardware performance counter registers
- * --------------------------------------
- */
-#ifdef METAC_2_1
-/* Two Performance Counter Internal Core Events Control registers */
-#define PERF_ICORE0 0x0480FFD0
-#define PERF_ICORE1 0x0480FFD8
-#define PERFI_CTRL_BITS 0x0000000F
-#define PERFI_CTRL_S 0
-#define PERFI_CAH_DMISS 0x0 /* Dcache Misses in cache (TLB Hit) */
-#define PERFI_CAH_IMISS 0x1 /* Icache Misses in cache (TLB Hit) */
-#define PERFI_TLB_DMISS 0x2 /* Dcache Misses in per-thread TLB */
-#define PERFI_TLB_IMISS 0x3 /* Icache Misses in per-thread TLB */
-#define PERFI_TLB_DWRHITS 0x4 /* DC Write-Hits in per-thread TLB */
-#define PERFI_TLB_DWRMISS 0x5 /* DC Write-Miss in per-thread TLB */
-#define PERFI_CAH_DLFETCH 0x8 /* DC Read cache line fetch */
-#define PERFI_CAH_ILFETCH 0x9 /* DC Read cache line fetch */
-#define PERFI_CAH_DWFETCH 0xA /* DC Read cache word fetch */
-#define PERFI_CAH_IWFETCH 0xB /* DC Read cache word fetch */
-#endif /* METAC_2_1 */
-
-/* Two memory-mapped hardware performance counter registers */
-#define PERF_COUNT0 0x0480FFE0
-#define PERF_COUNT1 0x0480FFE8
-
-/* Fields in PERF_COUNTn registers */
-#define PERF_COUNT_BITS 0x00ffffff /* Event count value */
-
-#define PERF_THREAD_BITS 0x0f000000 /* Thread mask selects threads */
-#define PERF_THREAD_S 24
-
-#define PERF_CTRL_BITS 0xf0000000 /* Event filter control */
-#define PERF_CTRL_S 28
-
-#define PERFCTRL_SUPER 0 /* Superthread cycles */
-#define PERFCTRL_REWIND 1 /* Rewinds due to Dcache Misses */
-#ifdef METAC_2_1
-#define PERFCTRL_SUPREW 2 /* Rewinds of superthreaded cycles (no mask) */
-
-#define PERFCTRL_CYCLES 3 /* Counts all cycles (no mask) */
-
-#define PERFCTRL_PREDBC 4 /* Conditional branch predictions */
-#define PERFCTRL_MISPBC 5 /* Conditional branch mispredictions */
-#define PERFCTRL_PREDRT 6 /* Return predictions */
-#define PERFCTRL_MISPRT 7 /* Return mispredictions */
-#endif /* METAC_2_1 */
-
-#define PERFCTRL_DHITS 8 /* Dcache Hits */
-#define PERFCTRL_IHITS 9 /* Icache Hits */
-#define PERFCTRL_IMISS 10 /* Icache Misses in cache or TLB */
-#ifdef METAC_2_1
-#define PERFCTRL_DCSTALL 11 /* Dcache+TLB o/p delayed (per-thread) */
-#define PERFCTRL_ICSTALL 12 /* Icache+TLB o/p delayed (per-thread) */
-
-#define PERFCTRL_INT 13 /* Internal core detailed events (see next) */
-#define PERFCTRL_EXT 15 /* External source in core periphery */
-#endif /* METAC_2_1 */
-
-#ifdef METAC_2_1
-/* These definitions replace the EXPAND_PERFCHANx register defines which are to
- * be deprecated.
- */
-#define PERF_CHAN0 0x04830150
-#define PERF_CHAN1 0x04830158
-#define PERF_CHAN_BITS 0x0000000F
-#define PERF_CHAN_S 0
-#define PERFCHAN_WRC_WRBURST 0x0 /* Write combiner write burst */
-#define PERFCHAN_WRC_WRITE 0x1 /* Write combiner write */
-#define PERFCHAN_WRC_RDBURST 0x2 /* Write combiner read burst */
-#define PERFCHAN_WRC_READ 0x3 /* Write combiner read */
-#define PERFCHAN_PREARB_DELAY 0x4 /* Pre-arbiter delay cycle */
- /* Cross-bar hold-off cycle: */
-#define PERFCHAN_XBAR_HOLDWRAP 0x5 /* wrapper register */
-#define PERFCHAN_XBAR_HOLDSBUS 0x6 /* system bus (ATP only) */
-#define PERFCHAN_XBAR_HOLDCREG 0x9 /* core registers */
-#define PERFCHAN_L2C_MISS 0x6 /* L2 Cache miss */
-#define PERFCHAN_L2C_HIT 0x7 /* L2 Cache hit */
-#define PERFCHAN_L2C_WRITEBACK 0x8 /* L2 Cache writeback */
- /* Admission delay cycle: */
-#define PERFCHAN_INPUT_CREG 0xB /* core registers */
-#define PERFCHAN_INPUT_INTR 0xC /* internal ram */
-#define PERFCHAN_INPUT_WRC 0xD /* write combiners(memory) */
-
-/* Should following be removed as not in TRM anywhere? */
-#define PERFCHAN_XBAR_HOLDINTR 0x8 /* internal ram */
-#define PERFCHAN_INPUT_SBUS 0xA /* register port */
-/* End of remove section. */
-
-#define PERFCHAN_MAINARB_DELAY 0xF /* Main arbiter delay cycle */
-
-#endif /* METAC_2_1 */
-
-#ifdef METAC_2_1
-/*
- * Write combiner registers
- * ------------------------
- *
- * These replace the EXPAND_T0WRCOMBINE register defines, which will be
- * deprecated.
- */
-#define WRCOMB_CONFIG0 0x04830100
-#define WRCOMB_LFFEn_BIT 0x00004000 /* Enable auto line full flush */
-#define WRCOMB_ENABLE_BIT 0x00002000 /* Enable write combiner */
-#define WRCOMB_TIMEOUT_ENABLE_BIT 0x00001000 /* Timeout flush enable */
-#define WRCOMB_TIMEOUT_COUNT_BITS 0x000003FF
-#define WRCOMB_TIMEOUT_COUNT_S 0
-#define WRCOMB_CONFIG4 0x04830180
-#define WRCOMB_PARTALLOC_BITS 0x000000C0
-#define WRCOMB_PARTALLOC_S 64
-#define WRCOMB_PARTSIZE_BITS 0x00000030
-#define WRCOMB_PARTSIZE_S 4
-#define WRCOMB_PARTOFFSET_BITS 0x0000000F
-#define WRCOMB_PARTOFFSET_S 0
-#define WRCOMB_CONFIG_STRIDE 8
-#endif /* METAC_2_1 */
-
-#ifdef METAC_2_1
-/*
- * Thread arbiter registers
- * ------------------------
- *
- * These replace the EXPAND_T0ARBITER register defines, which will be
- * deprecated.
- */
-#define ARBITER_ARBCONFIG0 0x04830120
-#define ARBCFG_BPRIORITY_BIT 0x02000000
-#define ARBCFG_IPRIORITY_BIT 0x01000000
-#define ARBCFG_PAGE_BITS 0x00FF0000
-#define ARBCFG_PAGE_S 16
-#define ARBCFG_BBASE_BITS 0x0000FF00
-#define ARGCFG_BBASE_S 8
-#define ARBCFG_IBASE_BITS 0x000000FF
-#define ARBCFG_IBASE_S 0
-#define ARBITER_TTECONFIG0 0x04820160
-#define ARBTTE_IUPPER_BITS 0xFF000000
-#define ARBTTE_IUPPER_S 24
-#define ARBTTE_ILOWER_BITS 0x00FF0000
-#define ARBTTE_ILOWER_S 16
-#define ARBTTE_BUPPER_BITS 0x0000FF00
-#define ARBTTE_BUPPER_S 8
-#define ARBTTE_BLOWER_BITS 0x000000FF
-#define ARBTTE_BLOWER_S 0
-#define ARBITER_STRIDE 8
-#endif /* METAC_2_1 */
-
-/*
- * Expansion area registers
- * --------------------------------------
- */
-
-/* These defines are to be deprecated. See above instead. */
-#define EXPAND_T0WRCOMBINE 0x03000000
-#ifdef METAC_2_1
-#define EXPWRC_LFFEn_BIT 0x00004000 /* Enable auto line full flush */
-#endif /* METAC_2_1 */
-#define EXPWRC_ENABLE_BIT 0x00002000 /* Enable write combiner */
-#define EXPWRC_TIMEOUT_ENABLE_BIT 0x00001000 /* Timeout flush enable */
-#define EXPWRC_TIMEOUT_COUNT_BITS 0x000003FF
-#define EXPWRC_TIMEOUT_COUNT_S 0
-#define EXPAND_TnWRCOMBINE_STRIDE 0x00000008
-
-/* These defines are to be deprecated. See above instead. */
-#define EXPAND_T0ARBITER 0x03000020
-#define EXPARB_BPRIORITY_BIT 0x02000000
-#define EXPARB_IPRIORITY_BIT 0x01000000
-#define EXPARB_PAGE_BITS 0x00FF0000
-#define EXPARB_PAGE_S 16
-#define EXPARB_BBASE_BITS 0x0000FF00
-#define EXPARB_BBASE_S 8
-#define EXPARB_IBASE_BITS 0x000000FF
-#define EXPARB_IBASE_S 0
-#define EXPAND_TnARBITER_STRIDE 0x00000008
-
-/* These definitions are to be deprecated. See above instead. */
-#define EXPAND_TIMER_DIV 0x03000040
-#define EXPTIM_DIV_BITS 0x000000FF
-#define EXPTIM_DIV_S 0
-
-/* These definitions are to be deprecated. See above instead. */
-#define EXPAND_PERFCHAN0 0x03000050
-#define EXPAND_PERFCHAN1 0x03000058
-#define EXPPERF_CTRL_BITS 0x0000000F
-#define EXPPERF_CTRL_S 0
-#define EXPPERF_WRC_WRBURST 0x0 /* Write combiner write burst */
-#define EXPPERF_WRC_WRITE 0x1 /* Write combiner write */
-#define EXPPERF_WRC_RDBURST 0x2 /* Write combiner read burst */
-#define EXPPERF_WRC_READ 0x3 /* Write combiner read */
-#define EXPPERF_PREARB_DELAY 0x4 /* Pre-arbiter delay cycle */
- /* Cross-bar hold-off cycle: */
-#define EXPPERF_XBAR_HOLDWRAP 0x5 /* wrapper register */
-#define EXPPERF_XBAR_HOLDSBUS 0x6 /* system bus */
-#ifdef METAC_1_2
-#define EXPPERF_XBAR_HOLDLBUS 0x7 /* local bus */
-#else /* METAC_1_2 */
-#define EXPPERF_XBAR_HOLDINTR 0x8 /* internal ram */
-#define EXPPERF_XBAR_HOLDCREG 0x9 /* core registers */
- /* Admission delay cycle: */
-#define EXPPERF_INPUT_SBUS 0xA /* register port */
-#define EXPPERF_INPUT_CREG 0xB /* core registers */
-#define EXPPERF_INPUT_INTR 0xC /* internal ram */
-#define EXPPERF_INPUT_WRC 0xD /* write combiners(memory) */
-#endif /* !METAC_1_2 */
-#define EXPPERF_MAINARB_DELAY 0xF /* Main arbiter delay cycle */
-
-/*
- * Debug port registers
- * --------------------------------------
- */
-
-/* Data Exchange Register */
-#define DBGPORT_MDBGDATAX 0x0
-
-/* Data Transfer register */
-#define DBGPORT_MDBGDATAT 0x4
-
-/* Control Register 0 */
-#define DBGPORT_MDBGCTRL0 0x8
-#define DBGPORT_MDBGCTRL0_ADDR_BITS 0xFFFFFFFC
-#define DBGPORT_MDBGCTRL0_ADDR_S 2
-#define DBGPORT_MDBGCTRL0_AUTOINCR_BIT 0x00000002
-#define DBGPORT_MDBGCTRL0_RD_BIT 0x00000001
-
-/* Control Register 1 */
-#define DBGPORT_MDBGCTRL1 0xC
-#ifdef METAC_2_1
-#define DBGPORT_MDBGCTRL1_DEFERRTHREAD_BITS 0xC0000000
-#define DBGPORT_MDBGCTRL1_DEFERRTHREAD_S 30
-#endif /* METAC_2_1 */
-#define DBGPORT_MDBGCTRL1_LOCK2_INTERLOCK_BIT 0x20000000
-#define DBGPORT_MDBGCTRL1_ATOMIC_INTERLOCK_BIT 0x10000000
-#define DBGPORT_MDBGCTRL1_TRIGSTATUS_BIT 0x08000000
-#define DBGPORT_MDBGCTRL1_GBLPORT_IDLE_BIT 0x04000000
-#define DBGPORT_MDBGCTRL1_COREMEM_IDLE_BIT 0x02000000
-#define DBGPORT_MDBGCTRL1_READY_BIT 0x01000000
-#ifdef METAC_2_1
-#define DBGPORT_MDBGCTRL1_DEFERRID_BITS 0x00E00000
-#define DBGPORT_MDBGCTRL1_DEFERRID_S 21
-#define DBGPORT_MDBGCTRL1_DEFERR_BIT 0x00100000
-#endif /* METAC_2_1 */
-#define DBGPORT_MDBGCTRL1_WR_ACTIVE_BIT 0x00040000
-#define DBGPORT_MDBGCTRL1_COND_LOCK2_BIT 0x00020000
-#define DBGPORT_MDBGCTRL1_LOCK2_BIT 0x00010000
-#define DBGPORT_MDBGCTRL1_DIAGNOSE_BIT 0x00008000
-#define DBGPORT_MDBGCTRL1_FORCEDIAG_BIT 0x00004000
-#define DBGPORT_MDBGCTRL1_MEMFAULT_BITS 0x00003000
-#define DBGPORT_MDBGCTRL1_MEMFAULT_S 12
-#define DBGPORT_MDBGCTRL1_TRIGGER_BIT 0x00000100
-#ifdef METAC_2_1
-#define DBGPORT_MDBGCTRL1_INTSPECIAL_BIT 0x00000080
-#define DBGPORT_MDBGCTRL1_INTRUSIVE_BIT 0x00000040
-#endif /* METAC_2_1 */
-#define DBGPORT_MDBGCTRL1_THREAD_BITS 0x00000030 /* Thread mask selects threads */
-#define DBGPORT_MDBGCTRL1_THREAD_S 4
-#define DBGPORT_MDBGCTRL1_TRANS_SIZE_BITS 0x0000000C
-#define DBGPORT_MDBGCTRL1_TRANS_SIZE_S 2
-#define DBGPORT_MDBGCTRL1_TRANS_SIZE_32_BIT 0x00000000
-#define DBGPORT_MDBGCTRL1_TRANS_SIZE_16_BIT 0x00000004
-#define DBGPORT_MDBGCTRL1_TRANS_SIZE_8_BIT 0x00000008
-#define DBGPORT_MDBGCTRL1_BYTE_ROUND_BITS 0x00000003
-#define DBGPORT_MDBGCTRL1_BYTE_ROUND_S 0
-#define DBGPORT_MDBGCTRL1_BYTE_ROUND_8_BIT 0x00000001
-#define DBGPORT_MDBGCTRL1_BYTE_ROUND_16_BIT 0x00000002
-
-
-/* L2 Cache registers */
-#define SYSC_L2C_INIT 0x048300C0
-#define SYSC_L2C_INIT_INIT 1
-#define SYSC_L2C_INIT_IN_PROGRESS 0
-#define SYSC_L2C_INIT_COMPLETE 1
-
-#define SYSC_L2C_ENABLE 0x048300D0
-#define SYSC_L2C_ENABLE_ENABLE_BIT 0x00000001
-#define SYSC_L2C_ENABLE_PFENABLE_BIT 0x00000002
-
-#define SYSC_L2C_PURGE 0x048300C8
-#define SYSC_L2C_PURGE_PURGE 1
-#define SYSC_L2C_PURGE_IN_PROGRESS 0
-#define SYSC_L2C_PURGE_COMPLETE 1
-
-#endif /* _ASM_METAG_MEM_H_ */
diff --git a/arch/metag/include/asm/metag_regs.h b/arch/metag/include/asm/metag_regs.h
deleted file mode 100644
index 60b750971d8a..000000000000
--- a/arch/metag/include/asm/metag_regs.h
+++ /dev/null
@@ -1,1184 +0,0 @@
-/*
- * asm/metag_regs.h
- *
- * Copyright (C) 2000-2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Various defines for Meta core (non memory-mapped) registers.
- */
-
-#ifndef _ASM_METAG_REGS_H_
-#define _ASM_METAG_REGS_H_
-
-/*
- * CHIP Unit Identifiers and Valid/Global register number masks
- * ------------------------------------------------------------
- */
-#define TXUCT_ID 0x0 /* Control unit regs */
-#ifdef METAC_1_2
-#define TXUCT_MASK 0xFF0FFFFF /* Valid regs 0..31 */
-#else
-#define TXUCT_MASK 0xFF1FFFFF /* Valid regs 0..31 */
-#endif
-#define TGUCT_MASK 0x00000000 /* No global regs */
-#define TXUD0_ID 0x1 /* Data unit regs */
-#define TXUD1_ID 0x2
-#define TXUDX_MASK 0xFFFFFFFF /* Valid regs 0..31 */
-#define TGUDX_MASK 0xFFFF0000 /* Global regs for base inst */
-#define TXUDXDSP_MASK 0x0F0FFFFF /* Valid DSP regs */
-#define TGUDXDSP_MASK 0x0E0E0000 /* Global DSP ACC regs */
-#define TXUA0_ID 0x3 /* Address unit regs */
-#define TXUA1_ID 0x4
-#define TXUAX_MASK 0x0000FFFF /* Valid regs 0-15 */
-#define TGUAX_MASK 0x0000FF00 /* Global regs 8-15 */
-#define TXUPC_ID 0x5 /* PC registers */
-#define TXUPC_MASK 0x00000003 /* Valid regs 0- 1 */
-#define TGUPC_MASK 0x00000000 /* No global regs */
-#define TXUPORT_ID 0x6 /* Ports are not registers */
-#define TXUTR_ID 0x7
-#define TXUTR_MASK 0x0000005F /* Valid regs 0-3,4,6 */
-#define TGUTR_MASK 0x00000000 /* No global regs */
-#ifdef METAC_2_1
-#define TXUTT_ID 0x8
-#define TXUTT_MASK 0x0000000F /* Valid regs 0-3 */
-#define TGUTT_MASK 0x00000010 /* Global reg 4 */
-#define TXUFP_ID 0x9 /* FPU regs */
-#define TXUFP_MASK 0x0000FFFF /* Valid regs 0-15 */
-#define TGUFP_MASK 0x00000000 /* No global regs */
-#endif /* METAC_2_1 */
-
-#ifdef METAC_1_2
-#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
- TXUAX_MASK, TXUPC_MASK, 0, TXUTR_MASK, \
- 0, 0, 0, 0, 0, 0, 0, 0 }
-#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
- TGUAX_MASK, TGUPC_MASK, 0, TGUTR_MASK, \
- 0, 0, 0, 0, 0, 0, 0, 0 }
-#else /* METAC_1_2 */
-#define TXUXX_MASKS { TXUCT_MASK, TXUDX_MASK, TXUDX_MASK, TXUAX_MASK, \
- TXUAX_MASK, TXUPC_MASK, 0, TXUTR_MASK, \
- TXUTT_MASK, TXUFP_MASK, 0, 0, \
- 0, 0, 0, 0 }
-#define TGUXX_MASKS { TGUCT_MASK, TGUDX_MASK, TGUDX_MASK, TGUAX_MASK, \
- TGUAX_MASK, TGUPC_MASK, 0, TGUTR_MASK, \
- TGUTT_MASK, TGUFP_MASK, 0, 0, \
- 0, 0, 0, 0 }
-#endif /* !METAC_1_2 */
-
-#define TXUXXDSP_MASKS { 0, TXUDXDSP_MASK, TXUDXDSP_MASK, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0 }
-#define TGUXXDSP_MASKS { 0, TGUDXDSP_MASK, TGUDXDSP_MASK, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0 }
-
-/* -------------------------------------------------------------------------
-; DATA AND ADDRESS UNIT REGISTERS
-; -----------------------------------------------------------------------*/
-/*
- Thread local D0 registers
- */
-/* D0.0 ; Holds 32-bit result, can be used as scratch */
-#define D0Re0 D0.0
-/* D0.1 ; Used to pass Arg6_32 */
-#define D0Ar6 D0.1
-/* D0.2 ; Used to pass Arg4_32 */
-#define D0Ar4 D0.2
-/* D0.3 ; Used to pass Arg2_32 to a called routine (see D1.3 below) */
-#define D0Ar2 D0.3
-/* D0.4 ; Can be used as scratch; used to save A0FrP in entry sequences */
-#define D0FrT D0.4
-/* D0.5 ; C compiler assumes preservation, save with D1.5 if used */
-/* D0.6 ; C compiler assumes preservation, save with D1.6 if used */
-/* D0.7 ; C compiler assumes preservation, save with D1.7 if used */
-/* D0.8 ; Use of D0.8 and above is not encouraged */
-/* D0.9 */
-/* D0.10 */
-/* D0.11 */
-/* D0.12 */
-/* D0.13 */
-/* D0.14 */
-/* D0.15 */
-/*
- Thread local D1 registers
- */
-/* D1.0 ; Holds top 32-bits of 64-bit result, can be used as scratch */
-#define D1Re0 D1.0
-/* D1.1 ; Used to pass Arg5_32 */
-#define D1Ar5 D1.1
-/* D1.2 ; Used to pass Arg3_32 */
-#define D1Ar3 D1.2
-/* D1.3 ; Used to pass Arg1_32 (first 32-bit argument) to a called routine */
-#define D1Ar1 D1.3
-/* D1.4 ; Used for Return Pointer, save during entry with A0FrP (via D0.4) */
-#define D1RtP D1.4
-/* D1.5 ; C compiler assumes preservation, save if used */
-/* D1.6 ; C compiler assumes preservation, save if used */
-/* D1.7 ; C compiler assumes preservation, save if used */
-/* D1.8 ; Use of D1.8 and above is not encouraged */
-/* D1.9 */
-/* D1.10 */
-/* D1.11 */
-/* D1.12 */
-/* D1.13 */
-/* D1.14 */
-/* D1.15 */
-/*
- Thread local A0 registers
- */
-/* A0.0 ; Primary stack pointer */
-#define A0StP A0.0
-/* A0.1 ; Used as local frame pointer in C, save if used (via D0.4) */
-#define A0FrP A0.1
-/* A0.2 */
-/* A0.3 */
-/* A0.4 ; Use of A0.4 and above is not encouraged */
-/* A0.5 */
-/* A0.6 */
-/* A0.7 */
-/*
- Thread local A1 registers
- */
-/* A1.0 ; Global static chain pointer - do not modify */
-#define A1GbP A1.0
-/* A1.1 ; Local static chain pointer in C, can be used as scratch */
-#define A1LbP A1.1
-/* A1.2 */
-/* A1.3 */
-/* A1.4 ; Use of A1.4 and above is not encouraged */
-/* A1.5 */
-/* A1.6 */
-/* A1.7 */
-#ifdef METAC_2_1
-/* Renameable registers for use with Fast Interrupts */
-/* The interrupt stack pointer (usually a global register) */
-#define A0IStP A0IReg
-/* The interrupt global pointer (usually a global register) */
-#define A1IGbP A1IReg
-#endif
-/*
- Further registers may be globally allocated via linkage/loading tools,
- normally they are not used.
- */
-/*-------------------------------------------------------------------------
-; STACK STRUCTURE and CALLING CONVENTION
-; -----------------------------------------------------------------------*/
-/*
-; Calling convention indicates that the following is the state of the
-; stack frame at the start of a routine-
-;
-; Arg9_32 [A0StP+#-12]
-; Arg8_32 [A0StP+#- 8]
-; Arg7_32 [A0StP+#- 4]
-; A0StP->
-;
-; Registers D1.3, D0.3, ..., to D0.1 are used to pass Arg1_32 to Arg6_32
-; respectively. If a routine needs to store them on the stack in order
-; to make sub-calls or because of the general complexity of the routine it
-; is best to dump these registers immediately at the start of a routine
-; using a MSETL or SETL instruction-
-;
-; MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2; Only dump arguments expected
-;or SETL [A0StP+#8++],D0Ar2 ; Up to two 32-bit args expected
-;
-; For non-leaf routines it is always necessary to save and restore at least
-; the return address value D1RtP on the stack. Also by convention if the
-; frame is saved then a new A0FrP value must be set-up. So for non-leaf
-; routines at this point both these registers must be saved onto the stack
-; using a SETL instruction and the new A0FrP value is then set-up-
-;
-; MOV D0FrT,A0FrP
-; ADD A0FrP,A0StP,#0
-; SETL [A0StP+#8++],D0FrT,D1RtP
-;
-; Registers D0.5, D1.5, to D1.7 are assumed to be preserved across calls so
-; a SETL or MSETL instruction can be used to save the current state
-; of these registers if they are modified by the current routine-
-;
-; MSETL [A0StP],D0.5,D0.6,D0.7 ; Only save registers modified
-;or SETL [A0StP+#8++],D0.5 ; Only D0.5 and/or D1.5 modified
-;
-; All of the above sequences can be combined into one maximal case-
-;
-; MOV D0FrT,A0FrP ; Save and calculate new frame pointer
-; ADD A0FrP,A0StP,#(ARS)
-; MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
-;
-; Having completed the above sequence the only remaining task on routine
-; entry is to reserve any local and outgoing argment storage space on the
-; stack. This instruction may be omitted if the size of this region is zero-
-;
-; ADD A0StP,A0StP,#(LCS)
-;
-; LCS is the first example use of one of a number of standard local defined
-; values that can be created to make assembler code more readable and
-; potentially more robust-
-;
-; #define ARS 0x18 ; Register arg bytes saved on stack
-; #define FRS 0x20 ; Frame save area size in bytes
-; #define LCS 0x00 ; Locals and Outgoing arg size
-; #define ARO (LCS+FRS) ; Stack offset to access args
-;
-; All of the above defines should be undefined (#undef) at the end of each
-; routine to avoid accidental use in the next routine.
-;
-; Given all of the above the following stack structure is expected during
-; the body of a routine if all args passed in registers are saved during
-; entry-
-;
-; ; 'Incoming args area'
-; Arg10_32 [A0StP+#-((10*4)+ARO)] Arg9_32 [A0StP+#-(( 9*4)+ARO)]
-; Arg8_32 [A0StP+#-(( 8*4)+ARO)] Arg7_32 [A0StP+#-(( 7*4)+ARO)]
-;--- Call point
-; D0Ar6= Arg6_32 [A0StP+#-(( 6*4)+ARO)] D1Ar5=Arg5_32 [A0StP+#-(( 5*4)+ARO)]
-; D0Ar4= Arg4_32 [A0StP+#-(( 4*4)+ARO)] D1Ar3=Arg3_32 [A0StP+#-(( 3*4)+ARO)]
-; D0Ar2= Arg2_32 [A0StP+#-(( 2*4)+ARO)] D1Ar2=Arg1_32 [A0StP+#-(( 1*4)+ARO)]
-; ; 'Frame area'
-; A0FrP-> D0FrT, D1RtP,
-; D0.5, D1.5,
-; D0.6, D1.6,
-; D0.7, D1.7,
-; ; 'Locals area'
-; Loc0_32 [A0StP+# (( 0*4)-LCS)], Loc1_32 [A0StP+# (( 1*4)-LCS)]
-; .... other locals
-; Locn_32 [A0StP+# (( n*4)-LCS)]
-; ; 'Outgoing args area'
-; Outm_32 [A0StP+#- ( m*4)] .... other outgoing args
-; Out8_32 [A0StP+#- ( 1*4)] Out7_32 [A0StP+#- ( 1*4)]
-; A0StP-> (Out1_32-Out6_32 in regs D1Ar1-D0Ar6)
-;
-; The exit sequence for a non-leaf routine can use the frame pointer created
-; in the entry sequence to optimise the recovery of the full state-
-;
-; MGETL D0FrT,D0.5,D0.6,D0.7,[A0FrP]
-; SUB A0StP,A0FrP,#(ARS+FRS)
-; MOV A0FrP,D0FrT
-; MOV PC,D1RtP
-;
-; Having described the most complex non-leaf case above, it is worth noting
-; that if a routine is a leaf and does not use any of the caller-preserved
-; state. The routine can be implemented as-
-;
-; ADD A0StP,A0StP,#LCS
-; .... body of routine
-; SUB A0StP,A0StP,#LCS
-; MOV PC,D1RtP
-;
-; The stack adjustments can also be omitted if no local storage is required.
-;
-; Another exit sequence structure is more applicable if for a leaf routine
-; with no local frame pointer saved/generated in which the call saved
-; registers need to be saved and restored-
-;
-; MSETL [A0StP],D0.5,D0.6,D0.7 ; Hence FRS is 0x18, ARS is 0x00
-; ADD A0StP,A0StP,#LCS
-; .... body of routine
-; GETL D0.5,D1.5,[A0StP+#((0*8)-(FRS+LCS))]
-; GETL D0.6,D1.6,[A0StP+#((1*8)-(FRS+LCS))]
-; GETL D0.7,D1.7,[A0StP+#((2*8)-(FRS+LCS))]
-; SUB A0StP,A0StP,#(ARS+FRS+LCS)
-; MOV PC,D1RtP
-;
-; Lastly, to support profiling assembler code should use a fixed entry/exit
-; sequence if the trigger define _GMON_ASM is defined-
-;
-; #ifndef _GMON_ASM
-; ... optimised entry code
-; #else
-; ; Profiling entry case
-; MOV D0FrT,A0FrP ; Save and calculate new frame pointer
-; ADD A0FrP,A0StP,#(ARS)
-; MSETL [A0StP],...,D0FrT,... or SETL [A0FrP],D0FrT,D1RtP
-; CALLR D0FrT,_mcount_wrapper
-; #endif
-; ... body of routine
-; #ifndef _GMON_ASM
-; ... optimised exit code
-; #else
-; ; Profiling exit case
-; MGETL D0FrT,...,[A0FrP] or GETL D0FrT,D1RtP,[A0FrP++]
-; SUB A0StP,A0FrP,#(ARS+FRS)
-; MOV A0FrP,D0FrT
-; MOV PC,D1RtP
-; #endif
-
-
-; -------------------------------------------------------------------------
-; CONTROL UNIT REGISTERS
-; -------------------------------------------------------------------------
-;
-; See the assembler guide, hardware documentation, or the field values
-; defined below for some details of the use of these registers.
-*/
-#define TXENABLE CT.0 /* Need to define bit-field values in these */
-#define TXMODE CT.1
-#define TXSTATUS CT.2 /* DEFAULT 0x00020000 */
-#define TXRPT CT.3
-#define TXTIMER CT.4
-#define TXL1START CT.5
-#define TXL1END CT.6
-#define TXL1COUNT CT.7
-#define TXL2START CT.8
-#define TXL2END CT.9
-#define TXL2COUNT CT.10
-#define TXBPOBITS CT.11
-#define TXMRSIZE CT.12
-#define TXTIMERI CT.13
-#define TXDRCTRL CT.14 /* DEFAULT 0x0XXXF0F0 */
-#define TXDRSIZE CT.15
-#define TXCATCH0 CT.16
-#define TXCATCH1 CT.17
-#define TXCATCH2 CT.18
-#define TXCATCH3 CT.19
-
-#ifdef METAC_2_1
-#define TXDEFR CT.20
-#define TXCPRS CT.21
-#endif
-
-#define TXINTERN0 CT.23
-#define TXAMAREG0 CT.24
-#define TXAMAREG1 CT.25
-#define TXAMAREG2 CT.26
-#define TXAMAREG3 CT.27
-#define TXDIVTIME CT.28 /* DEFAULT 0x00000001 */
-#define TXPRIVEXT CT.29 /* DEFAULT 0x003B0000 */
-#define TXTACTCYC CT.30
-#define TXIDLECYC CT.31
-
-/*****************************************************************************
- * CONTROL UNIT REGISTER BITS
- ****************************************************************************/
-/*
- * The following registers and where appropriate the sub-fields of those
- * registers are defined for pervasive use in controlling program flow.
- */
-
-/*
- * TXENABLE register fields - only the thread id is routinely useful
- */
-#define TXENABLE_REGNUM 0
-#define TXENABLE_THREAD_BITS 0x00000700
-#define TXENABLE_THREAD_S 8
-#define TXENABLE_REV_STEP_BITS 0x000000F0
-#define TXENABLE_REV_STEP_S 4
-
-/*
- * TXMODE register - controls extensions of the instruction set
- */
-#define TXMODE_REGNUM 1
-#define TXMODE_DEFAULT 0 /* All fields default to zero */
-
-/*
- * TXSTATUS register - contains a couple of stable bits that can be used
- * to determine the privilege processing level and interrupt
- * processing level of the current thread.
- */
-#define TXSTATUS_REGNUM 2
-#define TXSTATUS_PSTAT_BIT 0x00020000 /* -> Privilege active */
-#define TXSTATUS_PSTAT_S 17
-#define TXSTATUS_ISTAT_BIT 0x00010000 /* -> In interrupt state */
-#define TXSTATUS_ISTAT_S 16
-
-/*
- * These are all relatively boring registers, mostly full 32-bit
- */
-#define TXRPT_REGNUM 3 /* Repeat counter for XFR... instructions */
-#define TXTIMER_REGNUM 4 /* Timer-- causes timer trigger on overflow */
-#define TXL1START_REGNUM 5 /* Hardware Loop 1 Start-PC/End-PC/Count */
-#define TXL1END_REGNUM 6
-#define TXL1COUNT_REGNUM 7
-#define TXL2START_REGNUM 8 /* Hardware Loop 2 Start-PC/End-PC/Count */
-#define TXL2END_REGNUM 9
-#define TXL2COUNT_REGNUM 10
-#define TXBPOBITS_REGNUM 11 /* Branch predict override bits - tune perf */
-#define TXTIMERI_REGNUM 13 /* Timer-- time based interrupt trigger */
-
-/*
- * TXDIVTIME register is routinely read to calculate the time-base for
- * the TXTIMER register.
- */
-#define TXDIVTIME_REGNUM 28
-#define TXDIVTIME_DIV_BITS 0x000000FF
-#define TXDIVTIME_DIV_S 0
-#define TXDIVTIME_DIV_MIN 0x00000001 /* Maximum resolution */
-#define TXDIVTIME_DIV_MAX 0x00000100 /* 1/1 -> 1/256 resolution */
-#define TXDIVTIME_BASE_HZ 1000000 /* Timers run at 1Mhz @1/1 */
-
-/*
- * TXPRIVEXT register can be consulted to decide if write access to a
- * part of the threads register set is not permitted when in
- * unprivileged mode (PSTAT == 0).
- */
-#define TXPRIVEXT_REGNUM 29
-#define TXPRIVEXT_COPRO_BITS 0xFF000000 /* Co-processor 0-7 */
-#define TXPRIVEXT_COPRO_S 24
-#ifndef METAC_1_2
-#define TXPRIVEXT_TXTIMER_BIT 0x00080000 /* TXTIMER priv */
-#define TXPRIVEXT_TRACE_BIT 0x00040000 /* TTEXEC|TTCTRL|GTEXEC */
-#endif
-#define TXPRIVEXT_TXTRIGGER_BIT 0x00020000 /* TXSTAT|TXMASK|TXPOLL */
-#define TXPRIVEXT_TXGBLCREG_BIT 0x00010000 /* Global common regs */
-#define TXPRIVEXT_CBPRIV_BIT 0x00008000 /* Mem i/f dump priv */
-#define TXPRIVEXT_ILOCK_BIT 0x00004000 /* LOCK inst priv */
-#define TXPRIVEXT_TXITACCYC_BIT 0x00002000 /* TXIDLECYC|TXTACTCYC */
-#define TXPRIVEXT_TXDIVTIME_BIT 0x00001000 /* TXDIVTIME priv */
-#define TXPRIVEXT_TXAMAREGX_BIT 0x00000800 /* TXAMAREGX priv */
-#define TXPRIVEXT_TXTIMERI_BIT 0x00000400 /* TXTIMERI priv */
-#define TXPRIVEXT_TXSTATUS_BIT 0x00000200 /* TXSTATUS priv */
-#define TXPRIVEXT_TXDISABLE_BIT 0x00000100 /* TXENABLE priv */
-#ifndef METAC_1_2
-#define TXPRIVEXT_MINIMON_BIT 0x00000080 /* Enable Minim features */
-#define TXPRIVEXT_OLDBCCON_BIT 0x00000020 /* Restore Static predictions */
-#define TXPRIVEXT_ALIGNREW_BIT 0x00000010 /* Align & precise checks */
-#endif
-#define TXPRIVEXT_KEEPPRI_BIT 0x00000008 /* Use AMA_Priority if ISTAT=1*/
-#define TXPRIVEXT_TXTOGGLEI_BIT 0x00000001 /* TX.....I priv */
-
-/*
- * TXTACTCYC register - counts instructions issued for this thread
- */
-#define TXTACTCYC_REGNUM 30
-#define TXTACTCYC_COUNT_MASK 0x00FFFFFF
-
-/*
- * TXIDLECYC register - counts idle cycles
- */
-#define TXIDLECYC_REGNUM 31
-#define TXIDLECYC_COUNT_MASK 0x00FFFFFF
-
-/*****************************************************************************
- * DSP EXTENSIONS
- ****************************************************************************/
-/*
- * The following values relate to fields and controls that only a program
- * using the DSP extensions of the META instruction set need to know.
- */
-
-
-#ifndef METAC_1_2
-/*
- * Allow co-processor hardware to replace the read pipeline data source in
- * appropriate cases.
- */
-#define TXMODE_RDCPEN_BIT 0x00800000
-#endif
-
-/*
- * Address unit addressing modes
- */
-#define TXMODE_A1ADDR_BITS 0x00007000
-#define TXMODE_A1ADDR_S 12
-#define TXMODE_A0ADDR_BITS 0x00000700
-#define TXMODE_A0ADDR_S 8
-#define TXMODE_AXADDR_MODULO 3
-#define TXMODE_AXADDR_REVB 4
-#define TXMODE_AXADDR_REVW 5
-#define TXMODE_AXADDR_REVD 6
-#define TXMODE_AXADDR_REVL 7
-
-/*
- * Data unit OverScale select (default 0 -> normal, 1 -> top 16 bits)
- */
-#define TXMODE_DXOVERSCALE_BIT 0x00000080
-
-/*
- * Data unit MX mode select (default 0 -> MX16, 1 -> MX8)
- */
-#define TXMODE_M8_BIT 0x00000040
-
-/*
- * Data unit accumulator saturation point (default -> 40 bit accumulator)
- */
-#define TXMODE_DXACCSAT_BIT 0x00000020 /* Set for 32-bit accumulator */
-
-/*
- * Data unit accumulator saturation enable (default 0 -> no saturation)
- */
-#define TXMODE_DXSAT_BIT 0x00000010
-
-/*
- * Data unit master rounding control (default 0 -> normal, 1 -> convergent)
- */
-#define TXMODE_DXROUNDING_BIT 0x00000008
-
-/*
- * Data unit product shift for fractional arithmetic (default off)
- */
-#define TXMODE_DXPRODSHIFT_BIT 0x00000004
-
-/*
- * Select the arithmetic mode (multiply mostly) for both data units
- */
-#define TXMODE_DXARITH_BITS 0x00000003
-#define TXMODE_DXARITH_32 3
-#define TXMODE_DXARITH_32H 2
-#define TXMODE_DXARITH_S16 1
-#define TXMODE_DXARITH_16 0
-
-/*
- * TXMRSIZE register value only relevant when DSP modulo addressing active
- */
-#define TXMRSIZE_REGNUM 12
-#define TXMRSIZE_MIN 0x0002 /* 0, 1 -> normal addressing logic */
-#define TXMRSIZE_MAX 0xFFFF
-
-/*
- * TXDRCTRL register can be used to detect the actaul size of the DSP RAM
- * partitions allocated to this thread.
- */
-#define TXDRCTRL_REGNUM 14
-#define TXDRCTRL_SINESIZE_BITS 0x0F000000
-#define TXDRCTRL_SINESIZE_S 24
-#define TXDRCTRL_RAMSZPOW_BITS 0x001F0000 /* Limit = (1<<RAMSZPOW)-1 */
-#define TXDRCTRL_RAMSZPOW_S 16
-#define TXDRCTRL_D1RSZAND_BITS 0x0000F000 /* Mask top 4 bits - D1 */
-#define TXDRCTRL_D1RSZAND_S 12
-#define TXDRCTRL_D0RSZAND_BITS 0x000000F0 /* Mask top 4 bits - D0 */
-#define TXDRCTRL_D0RSZAND_S 4
-/* Given extracted RAMSZPOW and DnRSZAND fields this returns the size */
-#define TXDRCTRL_DXSIZE(Pow, AndBits) \
- ((((~(AndBits)) & 0x0f) + 1) << ((Pow)-4))
-
-/*
- * TXDRSIZE register provides modulo addressing options for each DSP RAM
- */
-#define TXDRSIZE_REGNUM 15
-#define TXDRSIZE_R1MOD_BITS 0xFFFF0000
-#define TXDRSIZE_R1MOD_S 16
-#define TXDRSIZE_R0MOD_BITS 0x0000FFFF
-#define TXDRSIZE_R0MOD_S 0
-
-#define TXDRSIZE_RBRAD_SCALE_BITS 0x70000000
-#define TXDRSIZE_RBRAD_SCALE_S 28
-#define TXDRSIZE_RBMODSIZE_BITS 0x0FFF0000
-#define TXDRSIZE_RBMODSIZE_S 16
-#define TXDRSIZE_RARAD_SCALE_BITS 0x00007000
-#define TXDRSIZE_RARAD_SCALE_S 12
-#define TXDRSIZE_RAMODSIZE_BITS 0x00000FFF
-#define TXDRSIZE_RAMODSIZE_S 0
-
-/*****************************************************************************
- * DEFERRED and BUS ERROR EXTENSION
- ****************************************************************************/
-
-/*
- * TXDEFR register - Deferred exception control
- */
-#define TXDEFR_REGNUM 20
-#define TXDEFR_DEFAULT 0 /* All fields default to zero */
-
-/*
- * Bus error state is a multi-bit positive/negative event notification from
- * the bus infrastructure.
- */
-#define TXDEFR_BUS_ERR_BIT 0x80000000 /* Set if error (LSB STATE) */
-#define TXDEFR_BUS_ERRI_BIT 0x40000000 /* Fetch returned error */
-#define TXDEFR_BUS_STATE_BITS 0x3F000000 /* Bus event/state data */
-#define TXDEFR_BUS_STATE_S 24
-#define TXDEFR_BUS_TRIG_BIT 0x00800000 /* Set when bus error seen */
-
-/*
- * Bus events are collected by background code in a deferred manner unless
- * selected to trigger an extended interrupt HALT trigger when they occur.
- */
-#define TXDEFR_BUS_ICTRL_BIT 0x00000080 /* Enable interrupt trigger */
-
-/*
- * CHIP Automatic Mips Allocation control registers
- * ------------------------------------------------
- */
-
-/* CT Bank AMA Registers */
-#define TXAMAREG0_REGNUM 24
-#ifdef METAC_1_2
-#define TXAMAREG0_CTRL_BITS 0x07000000
-#else /* METAC_1_2 */
-#define TXAMAREG0_RCOFF_BIT 0x08000000
-#define TXAMAREG0_DLINEHLT_BIT 0x04000000
-#define TXAMAREG0_DLINEDIS_BIT 0x02000000
-#define TXAMAREG0_CYCSTRICT_BIT 0x01000000
-#define TXAMAREG0_CTRL_BITS (TXAMAREG0_RCOFF_BIT | \
- TXAMAREG0_DLINEHLT_BIT | \
- TXAMAREG0_DLINEDIS_BIT | \
- TXAMAREG0_CYCSTRICT_BIT)
-#endif /* !METAC_1_2 */
-#define TXAMAREG0_CTRL_S 24
-#define TXAMAREG0_MDM_BIT 0x00400000
-#define TXAMAREG0_MPF_BIT 0x00200000
-#define TXAMAREG0_MPE_BIT 0x00100000
-#define TXAMAREG0_MASK_BITS (TXAMAREG0_MDM_BIT | \
- TXAMAREG0_MPF_BIT | \
- TXAMAREG0_MPE_BIT)
-#define TXAMAREG0_MASK_S 20
-#define TXAMAREG0_SDM_BIT 0x00040000
-#define TXAMAREG0_SPF_BIT 0x00020000
-#define TXAMAREG0_SPE_BIT 0x00010000
-#define TXAMAREG0_STATUS_BITS (TXAMAREG0_SDM_BIT | \
- TXAMAREG0_SPF_BIT | \
- TXAMAREG0_SPE_BIT)
-#define TXAMAREG0_STATUS_S 16
-#define TXAMAREG0_PRIORITY_BITS 0x0000FF00
-#define TXAMAREG0_PRIORITY_S 8
-#define TXAMAREG0_BVALUE_BITS 0x000000FF
-#define TXAMAREG0_BVALUE_S 0
-
-#define TXAMAREG1_REGNUM 25
-#define TXAMAREG1_DELAYC_BITS 0x07FFFFFF
-#define TXAMAREG1_DELAYC_S 0
-
-#define TXAMAREG2_REGNUM 26
-#ifdef METAC_1_2
-#define TXAMAREG2_DLINEC_BITS 0x00FFFFFF
-#define TXAMAREG2_DLINEC_S 0
-#else /* METAC_1_2 */
-#define TXAMAREG2_IRQPRIORITY_BIT 0xFF000000
-#define TXAMAREG2_IRQPRIORITY_S 24
-#define TXAMAREG2_DLINEC_BITS 0x00FFFFF0
-#define TXAMAREG2_DLINEC_S 4
-#endif /* !METAC_1_2 */
-
-#define TXAMAREG3_REGNUM 27
-#define TXAMAREG2_AMABLOCK_BIT 0x00080000
-#define TXAMAREG2_AMAC_BITS 0x0000FFFF
-#define TXAMAREG2_AMAC_S 0
-
-/*****************************************************************************
- * FPU EXTENSIONS
- ****************************************************************************/
-/*
- * The following registers only exist in FPU enabled cores.
- */
-
-/*
- * TXMODE register - FPU rounding mode control/status fields
- */
-#define TXMODE_FPURMODE_BITS 0x00030000
-#define TXMODE_FPURMODE_S 16
-#define TXMODE_FPURMODEWRITE_BIT 0x00040000 /* Set to change FPURMODE */
-
-/*
- * TXDEFR register - FPU exception handling/state is a significant source
- * of deferrable errors. Run-time S/W can move handling to interrupt level
- * using DEFR instruction to collect state.
- */
-#define TXDEFR_FPE_FE_BITS 0x003F0000 /* Set by FPU_FE events */
-#define TXDEFR_FPE_FE_S 16
-
-#define TXDEFR_FPE_INEXACT_FE_BIT 0x010000
-#define TXDEFR_FPE_UNDERFLOW_FE_BIT 0x020000
-#define TXDEFR_FPE_OVERFLOW_FE_BIT 0x040000
-#define TXDEFR_FPE_DIVBYZERO_FE_BIT 0x080000
-#define TXDEFR_FPE_INVALID_FE_BIT 0x100000
-#define TXDEFR_FPE_DENORMAL_FE_BIT 0x200000
-
-#define TXDEFR_FPE_ICTRL_BITS 0x000003F /* Route to interrupts */
-#define TXDEFR_FPE_ICTRL_S 0
-
-#define TXDEFR_FPE_INEXACT_ICTRL_BIT 0x01
-#define TXDEFR_FPE_UNDERFLOW_ICTRL_BIT 0x02
-#define TXDEFR_FPE_OVERFLOW_ICTRL_BIT 0x04
-#define TXDEFR_FPE_DIVBYZERO_ICTRL_BIT 0x08
-#define TXDEFR_FPE_INVALID_ICTRL_BIT 0x10
-#define TXDEFR_FPE_DENORMAL_ICTRL_BIT 0x20
-
-/*
- * DETAILED FPU RELATED VALUES
- * ---------------------------
- */
-
-/*
- * Rounding mode field in TXMODE can hold a number of logical values
- */
-#define METAG_FPURMODE_TONEAREST 0x0 /* Default */
-#define METAG_FPURMODE_TOWARDZERO 0x1
-#define METAG_FPURMODE_UPWARD 0x2
-#define METAG_FPURMODE_DOWNWARD 0x3
-
-/*
- * In order to set the TXMODE register field that controls the rounding mode
- * an extra bit must be set in the value written versus that read in order
- * to gate writes to the rounding mode field. This allows other non-FPU code
- * to modify TXMODE without knowledge of the FPU units presence and not
- * influence the FPU rounding mode. This macro adds the required bit so new
- * rounding modes are accepted.
- */
-#define TXMODE_FPURMODE_SET(FPURMode) \
- (TXMODE_FPURMODEWRITE_BIT + ((FPURMode)<<TXMODE_FPURMODE_S))
-
-/*
- * To successfully restore TXMODE to zero at the end of the function the
- * following value (rather than zero) must be used.
- */
-#define TXMODE_FPURMODE_RESET (TXMODE_FPURMODEWRITE_BIT)
-
-/*
- * In TXSTATUS a special bit exists to indicate if FPU H/W has been accessed
- * since it was last reset.
- */
-#define TXSTATUS_FPACTIVE_BIT 0x01000000
-
-/*
- * Exception state (see TXDEFR_FPU_FE_*) and enabling (for interrupt
- * level processing (see TXDEFR_FPU_ICTRL_*) are controlled by similar
- * bit mask locations within each field.
- */
-#define METAG_FPU_FE_INEXACT 0x01
-#define METAG_FPU_FE_UNDERFLOW 0x02
-#define METAG_FPU_FE_OVERFLOW 0x04
-#define METAG_FPU_FE_DIVBYZERO 0x08
-#define METAG_FPU_FE_INVALID 0x10
-#define METAG_FPU_FE_DENORMAL 0x20
-#define METAG_FPU_FE_ALL_EXCEPT (METAG_FPU_FE_INEXACT | \
- METAG_FPU_FE_UNDERFLOW | \
- METAG_FPU_FE_OVERFLOW | \
- METAG_FPU_FE_DIVBYZERO | \
- METAG_FPU_FE_INVALID | \
- METAG_FPU_FE_DENORMAL)
-
-/*****************************************************************************
- * THREAD CONTROL, ERROR, OR INTERRUPT STATE EXTENSIONS
- ****************************************************************************/
-/*
- * The following values are only relevant to code that externally controls
- * threads, handles errors/interrupts, and/or set-up interrupt/error handlers
- * for subsequent use.
- */
-
-/*
- * TXENABLE register fields - only ENABLE_BIT is potentially read/write
- */
-#define TXENABLE_MAJOR_REV_BITS 0xFF000000
-#define TXENABLE_MAJOR_REV_S 24
-#define TXENABLE_MINOR_REV_BITS 0x00FF0000
-#define TXENABLE_MINOR_REV_S 16
-#define TXENABLE_CLASS_BITS 0x0000F000
-#define TXENABLE_CLASS_S 12
-#define TXENABLE_CLASS_DSP 0x0 /* -> DSP Thread */
-#define TXENABLE_CLASS_LDSP 0x8 /* -> DSP LITE Thread */
-#define TXENABLE_CLASS_GP 0xC /* -> General Purpose Thread */
-#define TXENABLE_CLASSALT_LFPU 0x2 /* Set to indicate LITE FPU */
-#define TXENABLE_CLASSALT_FPUR8 0x1 /* Set to indicate 8xFPU regs */
-#define TXENABLE_MTXARCH_BIT 0x00000800
-#define TXENABLE_STEP_REV_BITS 0x000000F0
-#define TXENABLE_STEP_REV_S 4
-#define TXENABLE_STOPPED_BIT 0x00000004 /* TXOFF due to ENABLE->0 */
-#define TXENABLE_OFF_BIT 0x00000002 /* Thread is in off state */
-#define TXENABLE_ENABLE_BIT 0x00000001 /* Set if running */
-
-/*
- * TXSTATUS register - used by external/internal interrupt/error handler
- */
-#define TXSTATUS_CB1MARKER_BIT 0x00800000 /* -> int level mem state */
-#define TXSTATUS_CBMARKER_BIT 0x00400000 /* -> mem i/f state dumped */
-#define TXSTATUS_MEM_FAULT_BITS 0x00300000
-#define TXSTATUS_MEM_FAULT_S 20
-#define TXSTATUS_MEMFAULT_NONE 0x0 /* -> No memory fault */
-#define TXSTATUS_MEMFAULT_GEN 0x1 /* -> General fault */
-#define TXSTATUS_MEMFAULT_PF 0x2 /* -> Page fault */
-#define TXSTATUS_MEMFAULT_RO 0x3 /* -> Read only fault */
-#define TXSTATUS_MAJOR_HALT_BITS 0x000C0000
-#define TXSTATUS_MAJOR_HALT_S 18
-#define TXSTATUS_MAJHALT_TRAP 0x0 /* -> SWITCH inst used */
-#define TXSTATUS_MAJHALT_INST 0x1 /* -> Unknown inst or fetch */
-#define TXSTATUS_MAJHALT_PRIV 0x2 /* -> Internal privilege */
-#define TXSTATUS_MAJHALT_MEM 0x3 /* -> Memory i/f fault */
-#define TXSTATUS_L_STEP_BITS 0x00000800 /* -> Progress of L oper */
-#define TXSTATUS_LSM_STEP_BITS 0x00000700 /* -> Progress of L/S mult */
-#define TXSTATUS_LSM_STEP_S 8
-#define TXSTATUS_FLAG_BITS 0x0000001F /* -> All the flags */
-#define TXSTATUS_SCC_BIT 0x00000010 /* -> Split-16 flags ... */
-#define TXSTATUS_SCF_LZ_BIT 0x00000008 /* -> Split-16 Low Z flag */
-#define TXSTATUS_SCF_HZ_BIT 0x00000004 /* -> Split-16 High Z flag */
-#define TXSTATUS_SCF_HC_BIT 0x00000002 /* -> Split-16 High C flag */
-#define TXSTATUS_SCF_LC_BIT 0x00000001 /* -> Split-16 Low C flag */
-#define TXSTATUS_CF_Z_BIT 0x00000008 /* -> Condition Z flag */
-#define TXSTATUS_CF_N_BIT 0x00000004 /* -> Condition N flag */
-#define TXSTATUS_CF_O_BIT 0x00000002 /* -> Condition O flag */
-#define TXSTATUS_CF_C_BIT 0x00000001 /* -> Condition C flag */
-
-/*
- * TXCATCH0-3 register contents may store information on a memory operation
- * that has failed if the bit TXSTATUS_CBMARKER_BIT is set.
- */
-#define TXCATCH0_REGNUM 16
-#define TXCATCH1_REGNUM 17
-#define TXCATCH1_ADDR_BITS 0xFFFFFFFF /* TXCATCH1 is Addr 0-31 */
-#define TXCATCH1_ADDR_S 0
-#define TXCATCH2_REGNUM 18
-#define TXCATCH2_DATA0_BITS 0xFFFFFFFF /* TXCATCH2 is Data 0-31 */
-#define TXCATCH2_DATA0_S 0
-#define TXCATCH3_REGNUM 19
-#define TXCATCH3_DATA1_BITS 0xFFFFFFFF /* TXCATCH3 is Data 32-63 */
-#define TXCATCH3_DATA1_S 0
-
-/*
- * Detailed catch state information
- * --------------------------------
- */
-
-/* Contents of TXCATCH0 register */
-#define TXCATCH0_LDRXX_BITS 0xF8000000 /* Load destination reg 0-31 */
-#define TXCATCH0_LDRXX_S 27
-#define TXCATCH0_LDDST_BITS 0x07FF0000 /* Load destination bits */
-#define TXCATCH0_LDDST_S 16
-#define TXCATCH0_LDDST_D1DSP 0x400 /* One bit set if it's a LOAD */
-#define TXCATCH0_LDDST_D0DSP 0x200
-#define TXCATCH0_LDDST_TMPLT 0x100
-#define TXCATCH0_LDDST_TR 0x080
-#ifdef METAC_2_1
-#define TXCATCH0_LDDST_FPU 0x040
-#endif
-#define TXCATCH0_LDDST_PC 0x020
-#define TXCATCH0_LDDST_A1 0x010
-#define TXCATCH0_LDDST_A0 0x008
-#define TXCATCH0_LDDST_D1 0x004
-#define TXCATCH0_LDDST_D0 0x002
-#define TXCATCH0_LDDST_CT 0x001
-#ifdef METAC_2_1
-#define TXCATCH0_WATCHSTOP_BIT 0x00004000 /* Set if Data Watch set fault */
-#endif
-#define TXCATCH0_WATCHS_BIT 0x00004000 /* Set if Data Watch set fault */
-#define TXCATCH0_WATCH1_BIT 0x00002000 /* Set if Data Watch 1 matches */
-#define TXCATCH0_WATCH0_BIT 0x00001000 /* Set if Data Watch 0 matches */
-#define TXCATCH0_FAULT_BITS 0x00000C00 /* See TXSTATUS_MEMFAULT_* */
-#define TXCATCH0_FAULT_S 10
-#define TXCATCH0_PRIV_BIT 0x00000200 /* Privilege of transaction */
-#define TXCATCH0_READ_BIT 0x00000100 /* Set for Read or Load cases */
-
-#ifdef METAC_2_1
-/* LNKGET Marker bit in TXCATCH0 */
-#define TXCATCH0_LNKGET_MARKER_BIT 0x00000008
-#define TXCATCH0_PREPROC_BIT 0x00000004
-#endif
-
-/* Loads are indicated by one of the LDDST bits being set */
-#define TXCATCH0_LDM16_BIT 0x00000004 /* Load M16 flag */
-#define TXCATCH0_LDL2L1_BITS 0x00000003 /* Load data size L2,L1 */
-#define TXCATCH0_LDL2L1_S 0
-
-/* Reads are indicated by the READ bit being set without LDDST bits */
-#define TXCATCH0_RAXX_BITS 0x0000001F /* RAXX issue port for read */
-#define TXCATCH0_RAXX_S 0
-
-/* Write operations are all that remain if READ bit is not set */
-#define TXCATCH0_WMASK_BITS 0x000000FF /* Write byte lane mask */
-#define TXCATCH0_WMASK_S 0
-
-#ifdef METAC_2_1
-
-/* When a FPU exception is signalled then FPUSPEC == FPUSPEC_TAG */
-#define TXCATCH0_FPURDREG_BITS 0xF8000000
-#define TXCATCH0_FPURDREG_S 27
-#define TXCATCH0_FPUR1REG_BITS 0x07C00000
-#define TXCATCH0_FPUR1REG_S 22
-#define TXCATCH0_FPUSPEC_BITS 0x000F0000
-#define TXCATCH0_FPUSPEC_S 16
-#define TXCATCH0_FPUSPEC_TAG 0xF
-#define TXCATCH0_FPUINSTA_BIT 0x00001000
-#define TXCATCH0_FPUINSTQ_BIT 0x00000800
-#define TXCATCH0_FPUINSTZ_BIT 0x00000400
-#define TXCATCH0_FPUINSTN_BIT 0x00000200
-#define TXCATCH0_FPUINSTO3O_BIT 0x00000100
-#define TXCATCH0_FPUWIDTH_BITS 0x000000C0
-#define TXCATCH0_FPUWIDTH_S 6
-#define TXCATCH0_FPUWIDTH_FLOAT 0
-#define TXCATCH0_FPUWIDTH_DOUBLE 1
-#define TXCATCH0_FPUWIDTH_PAIRED 2
-#define TXCATCH0_FPUOPENC_BITS 0x0000003F
-#define TXCATCH0_FPUOPENC_S 0
-#define TXCATCH0_FPUOPENC_ADD 0 /* rop1=Rs1, rop3=Rs2 */
-#define TXCATCH0_FPUOPENC_SUB 1 /* rop1=Rs1, rop3=Rs2 */
-#define TXCATCH0_FPUOPENC_MUL 2 /* rop1=Rs1, rop2=Rs2 */
-#define TXCATCH0_FPUOPENC_ATOI 3 /* rop3=Rs */
-#define TXCATCH0_FPUOPENC_ATOX 4 /* rop3=Rs, uses #Imm */
-#define TXCATCH0_FPUOPENC_ITOA 5 /* rop3=Rs */
-#define TXCATCH0_FPUOPENC_XTOA 6 /* rop3=Rs, uses #Imm */
-#define TXCATCH0_FPUOPENC_ATOH 7 /* rop2=Rs */
-#define TXCATCH0_FPUOPENC_HTOA 8 /* rop2=Rs */
-#define TXCATCH0_FPUOPENC_DTOF 9 /* rop3=Rs */
-#define TXCATCH0_FPUOPENC_FTOD 10 /* rop3=Rs */
-#define TXCATCH0_FPUOPENC_DTOL 11 /* rop3=Rs */
-#define TXCATCH0_FPUOPENC_LTOD 12 /* rop3=Rs */
-#define TXCATCH0_FPUOPENC_DTOXL 13 /* rop3=Rs, uses #imm */
-#define TXCATCH0_FPUOPENC_XLTOD 14 /* rop3=Rs, uses #imm */
-#define TXCATCH0_FPUOPENC_CMP 15 /* rop1=Rs1, rop2=Rs2 */
-#define TXCATCH0_FPUOPENC_MIN 16 /* rop1=Rs1, rop2=Rs2 */
-#define TXCATCH0_FPUOPENC_MAX 17 /* rop1=Rs1, rop2=Rs2 */
-#define TXCATCH0_FPUOPENC_ADDRE 18 /* rop1=Rs1, rop3=Rs2 */
-#define TXCATCH0_FPUOPENC_SUBRE 19 /* rop1=Rs1, rop3=Rs2 */
-#define TXCATCH0_FPUOPENC_MULRE 20 /* rop1=Rs1, rop2=Rs2 */
-#define TXCATCH0_FPUOPENC_MXA 21 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
-#define TXCATCH0_FPUOPENC_MXAS 22 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
-#define TXCATCH0_FPUOPENC_MAR 23 /* rop1=Rs1, rop2=Rs2 */
-#define TXCATCH0_FPUOPENC_MARS 24 /* rop1=Rs1, rop2=Rs2 */
-#define TXCATCH0_FPUOPENC_MUZ 25 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
-#define TXCATCH0_FPUOPENC_MUZS 26 /* rop1=Rs1, rop2=Rs2, rop3=Rs3*/
-#define TXCATCH0_FPUOPENC_RCP 27 /* rop2=Rs */
-#define TXCATCH0_FPUOPENC_RSQ 28 /* rop2=Rs */
-
-/* For floating point exceptions TXCATCH1 is used to carry extra data */
-#define TXCATCH1_FPUR2REG_BITS 0xF8000000
-#define TXCATCH1_FPUR2REG_S 27
-#define TXCATCH1_FPUR3REG_BITS 0x07C00000 /* Undefined if O3O set */
-#define TXCATCH1_FPUR3REG_S 22
-#define TXCATCH1_FPUIMM16_BITS 0x0000FFFF
-#define TXCATCH1_FPUIMM16_S 0
-
-#endif /* METAC_2_1 */
-
-/*
- * TXDIVTIME register used to hold the partial base address of memory i/f
- * state dump area. Now deprecated.
- */
-#define TXDIVTIME_CBBASE_MASK 0x03FFFE00
-#define TXDIVTIME_CBBASE_LINBASE 0x80000000
-#define TXDIVTIME_CBBASE_LINBOFF 0x00000000 /* BGnd state */
-#define TXDIVTIME_CBBASE_LINIOFF 0x00000100 /* Int state */
-
-/*
- * TXDIVTIME register used to indicate if the read pipeline was dirty when a
- * thread was interrupted, halted, or generated an exception. It is invalid
- * to attempt to issue a further pipeline read address while the read
- * pipeline is in the dirty state.
- */
-#define TXDIVTIME_RPDIRTY_BIT 0x80000000
-
-/*
- * Further bits in the TXDIVTIME register allow interrupt handling code to
- * short-cut the discovery the most significant bit last read from TXSTATI.
- *
- * This is the bit number of the trigger line that a low level interrupt
- * handler should acknowledge and then perhaps the index of a corresponding
- * handler function.
- */
-#define TXDIVTIME_IRQENC_BITS 0x0F000000
-#define TXDIVTIME_IRQENC_S 24
-
-/*
- * If TXDIVTIME_RPVALID_BIT is set the read pipeline contained significant
- * information when the thread was interrupted|halted|exceptioned. Each slot
- * containing data is indicated by a one bit in the corresponding
- * TXDIVTIME_RPMASK_BITS bit (least significance bit relates to first
- * location in read pipeline - most likely to have the 1 state). Empty slots
- * contain zeroes with no interlock applied on reads if RPDIRTY is currently
- * set with RPMASK itself being read-only state.
- */
-#define TXDIVTIME_RPMASK_BITS 0x003F0000 /* -> Full (1) Empty (0) */
-#define TXDIVTIME_RPMASK_S 16
-
-/*
- * TXPRIVEXT register can be used to single step thread execution and
- * enforce synchronous memory i/f address checking for debugging purposes.
- */
-#define TXPRIVEXT_TXSTEP_BIT 0x00000004
-#define TXPRIVEXT_MEMCHECK_BIT 0x00000002
-
-/*
- * TXINTERNx registers holds internal state information for H/W debugging only
- */
-#define TXINTERN0_REGNUM 23
-#define TXINTERN0_LOCK2_BITS 0xF0000000
-#define TXINTERN0_LOCK2_S 28
-#define TXINTERN0_LOCK1_BITS 0x0F000000
-#define TXINTERN0_LOCK1_S 24
-#define TXINTERN0_TIFDF_BITS 0x0000F000
-#define TXINTERN0_TIFDF_S 12
-#define TXINTERN0_TIFIB_BITS 0x00000F00
-#define TXINTERN0_TIFIB_S 8
-#define TXINTERN0_TIFAF_BITS 0x000000F0
-#define TXINTERN0_TIFAF_S 4
-#define TXINTERN0_MSTATE_BITS 0x0000000F
-#define TXINTERN0_MSTATE_S 0
-
-/*
- * TXSTAT, TXMASK, TXPOLL, TXSTATI, TXMASKI, TXPOLLI registers from trigger
- * bank all have similar contents (upper kick count bits not in MASK regs)
- */
-#define TXSTAT_REGNUM 0
-#define TXSTAT_TIMER_BIT 0x00000001
-#define TXSTAT_TIMER_S 0
-#define TXSTAT_KICK_BIT 0x00000002
-#define TXSTAT_KICK_S 1
-#define TXSTAT_DEFER_BIT 0x00000008
-#define TXSTAT_DEFER_S 3
-#define TXSTAT_EXTTRIG_BITS 0x0000FFF0
-#define TXSTAT_EXTTRIG_S 4
-#define TXSTAT_FPE_BITS 0x003F0000
-#define TXSTAT_FPE_S 16
-#define TXSTAT_FPE_DENORMAL_BIT 0x00200000
-#define TXSTAT_FPE_DENORMAL_S 21
-#define TXSTAT_FPE_INVALID_BIT 0x00100000
-#define TXSTAT_FPE_INVALID_S 20
-#define TXSTAT_FPE_DIVBYZERO_BIT 0x00080000
-#define TXSTAT_FPE_DIVBYZERO_S 19
-#define TXSTAT_FPE_OVERFLOW_BIT 0x00040000
-#define TXSTAT_FPE_OVERFLOW_S 18
-#define TXSTAT_FPE_UNDERFLOW_BIT 0x00020000
-#define TXSTAT_FPE_UNDERFLOW_S 17
-#define TXSTAT_FPE_INEXACT_BIT 0x00010000
-#define TXSTAT_FPE_INEXACT_S 16
-#define TXSTAT_BUSERR_BIT 0x00800000 /* Set if bus error/ack state */
-#define TXSTAT_BUSERR_S 23
-#define TXSTAT_BUSSTATE_BITS 0xFF000000 /* Read only */
-#define TXSTAT_BUSSTATE_S 24
-#define TXSTAT_KICKCNT_BITS 0xFFFF0000
-#define TXSTAT_KICKCNT_S 16
-#define TXMASK_REGNUM 1
-#define TXSTATI_REGNUM 2
-#define TXSTATI_BGNDHALT_BIT 0x00000004
-#define TXMASKI_REGNUM 3
-#define TXPOLL_REGNUM 4
-#define TXPOLLI_REGNUM 6
-
-/*
- * TXDRCTRL register can be used to partition the DSP RAM space available to
- * this thread at startup. This is achieved by offsetting the region allocated
- * to each thread.
- */
-#define TXDRCTRL_D1PARTOR_BITS 0x00000F00 /* OR's into top 4 bits */
-#define TXDRCTRL_D1PARTOR_S 8
-#define TXDRCTRL_D0PARTOR_BITS 0x0000000F /* OR's into top 4 bits */
-#define TXDRCTRL_D0PARTOR_S 0
-/* Given extracted Pow and Or fields this is threads base within DSP RAM */
-#define TXDRCTRL_DXBASE(Pow, Or) ((Or)<<((Pow)-4))
-
-/*****************************************************************************
- * RUN TIME TRACE CONTROL REGISTERS
- ****************************************************************************/
-/*
- * The following values are only relevant to code that implements run-time
- * trace features within the META Core
- */
-#define TTEXEC TT.0
-#define TTCTRL TT.1
-#define TTMARK TT.2
-#define TTREC TT.3
-#define GTEXEC TT.4
-
-#define TTEXEC_REGNUM 0
-#define TTEXEC_EXTTRIGAND_BITS 0x7F000000
-#define TTEXEC_EXTTRIGAND_S 24
-#define TTEXEC_EXTTRIGEN_BIT 0x00008000
-#define TTEXEC_EXTTRIGMATCH_BITS 0x00007F00
-#define TTEXEC_EXTTRIGMATCH_S 8
-#define TTEXEC_TCMODE_BITS 0x00000003
-#define TTEXEC_TCMODE_S 0
-
-#define TTCTRL_REGNUM 1
-#define TTCTRL_TRACETT_BITS 0x00008000
-#define TTCTRL_TRACETT_S 15
-#define TTCTRL_TRACEALL_BITS 0x00002000
-#define TTCTRL_TRACEALL_S 13
-#ifdef METAC_2_1
-#define TTCTRL_TRACEALLTAG_BITS 0x00000400
-#define TTCTRL_TRACEALLTAG_S 10
-#endif /* METAC_2_1 */
-#define TTCTRL_TRACETAG_BITS 0x00000200
-#define TTCTRL_TRACETAG_S 9
-#define TTCTRL_TRACETTPC_BITS 0x00000080
-#define TTCTRL_TRACETTPC_S 7
-#define TTCTRL_TRACEMPC_BITS 0x00000020
-#define TTCTRL_TRACEMPC_S 5
-#define TTCTRL_TRACEEN_BITS 0x00000008
-#define TTCTRL_TRACEEN_S 3
-#define TTCTRL_TRACEEN1_BITS 0x00000004
-#define TTCTRL_TRACEEN1_S 2
-#define TTCTRL_TRACEPC_BITS 0x00000002
-#define TTCTRL_TRACEPC_S 1
-
-#ifdef METAC_2_1
-#define TTMARK_REGNUM 2
-#define TTMARK_BITS 0xFFFFFFFF
-#define TTMARK_S 0x0
-
-#define TTREC_REGNUM 3
-#define TTREC_BITS 0xFFFFFFFFFFFFFFFF
-#define TTREC_S 0x0
-#endif /* METAC_2_1 */
-
-#define GTEXEC_REGNUM 4
-#define GTEXEC_DCRUN_BITS 0x80000000
-#define GTEXEC_DCRUN_S 31
-#define GTEXEC_ICMODE_BITS 0x0C000000
-#define GTEXEC_ICMODE_S 26
-#define GTEXEC_TCMODE_BITS 0x03000000
-#define GTEXEC_TCMODE_S 24
-#define GTEXEC_PERF1CMODE_BITS 0x00040000
-#define GTEXEC_PERF1CMODE_S 18
-#define GTEXEC_PERF0CMODE_BITS 0x00010000
-#define GTEXEC_PERF0CMODE_S 16
-#define GTEXEC_REFMSEL_BITS 0x0000F000
-#define GTEXEC_REFMSEL_S 12
-#define GTEXEC_METRICTH_BITS 0x000003FF
-#define GTEXEC_METRICTH_S 0
-
-#ifdef METAC_2_1
-/*
- * Clock Control registers
- * -----------------------
- */
-#define TXCLKCTRL_REGNUM 22
-
-/*
- * Default setting is with clocks always on (DEFON), turning all clocks off
- * can only be done from external devices (OFF), enabling automatic clock
- * gating will allow clocks to stop as units fall idle.
- */
-#define TXCLKCTRL_ALL_OFF 0x02222222
-#define TXCLKCTRL_ALL_DEFON 0x01111111
-#define TXCLKCTRL_ALL_AUTO 0x02222222
-
-/*
- * Individual fields control caches, floating point and main data/addr units
- */
-#define TXCLKCTRL_CLOCKIC_BITS 0x03000000
-#define TXCLKCTRL_CLOCKIC_S 24
-#define TXCLKCTRL_CLOCKDC_BITS 0x00300000
-#define TXCLKCTRL_CLOCKDC_S 20
-#define TXCLKCTRL_CLOCKFP_BITS 0x00030000
-#define TXCLKCTRL_CLOCKFP_S 16
-#define TXCLKCTRL_CLOCKD1_BITS 0x00003000
-#define TXCLKCTRL_CLOCKD1_S 12
-#define TXCLKCTRL_CLOCKD0_BITS 0x00000300
-#define TXCLKCTRL_CLOCKD0_S 8
-#define TXCLKCTRL_CLOCKA1_BITS 0x00000030
-#define TXCLKCTRL_CLOCKA1_S 4
-#define TXCLKCTRL_CLOCKA0_BITS 0x00000003
-#define TXCLKCTRL_CLOCKA0_S 0
-
-/*
- * Individual settings for each field are common
- */
-#define TXCLKCTRL_CLOCKxx_OFF 0
-#define TXCLKCTRL_CLOCKxx_DEFON 1
-#define TXCLKCTRL_CLOCKxx_AUTO 2
-
-#endif /* METAC_2_1 */
-
-#ifdef METAC_2_1
-/*
- * Fast interrupt new bits
- * ------------------------------------
- */
-#define TXSTATUS_IPTOGGLE_BIT 0x80000000 /* Prev PToggle of TXPRIVEXT */
-#define TXSTATUS_ISTATE_BIT 0x40000000 /* IState bit */
-#define TXSTATUS_IWAIT_BIT 0x20000000 /* wait indefinitely in decision step*/
-#define TXSTATUS_IEXCEPT_BIT 0x10000000 /* Indicate an exception occurred */
-#define TXSTATUS_IRPCOUNT_BITS 0x0E000000 /* Number of 'dirty' date entries*/
-#define TXSTATUS_IRPCOUNT_S 25
-#define TXSTATUS_IRQSTAT_BITS 0x0000F000 /* IRQEnc bits, trigger or interrupts */
-#define TXSTATUS_IRQSTAT_S 12
-#define TXSTATUS_LNKSETOK_BIT 0x00000020 /* LNKSetOK bit, successful LNKSET */
-
-/* New fields in TXDE for fast interrupt system */
-#define TXDIVTIME_IACTIVE_BIT 0x00008000 /* Enable new interrupt system */
-#define TXDIVTIME_INONEST_BIT 0x00004000 /* Gate nested interrupt */
-#define TXDIVTIME_IREGIDXGATE_BIT 0x00002000 /* gate of the IRegIdex field */
-#define TXDIVTIME_IREGIDX_BITS 0x00001E00 /* Index of A0.0/1 replaces */
-#define TXDIVTIME_IREGIDX_S 9
-#define TXDIVTIME_NOST_BIT 0x00000100 /* disable superthreading bit */
-#endif
-
-#endif /* _ASM_METAG_REGS_H_ */
diff --git a/arch/metag/include/asm/mman.h b/arch/metag/include/asm/mman.h
deleted file mode 100644
index dcb0d20a64fd..000000000000
--- a/arch/metag/include/asm/mman.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __METAG_MMAN_H__
-#define __METAG_MMAN_H__
-
-#include <uapi/asm/mman.h>
-
-#ifndef __ASSEMBLY__
-#define arch_mmap_check metag_mmap_check
-int metag_mmap_check(unsigned long addr, unsigned long len,
- unsigned long flags);
-#endif
-#endif /* __METAG_MMAN_H__ */
diff --git a/arch/metag/include/asm/mmu.h b/arch/metag/include/asm/mmu.h
deleted file mode 100644
index cab5a01c3dcb..000000000000
--- a/arch/metag/include/asm/mmu.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __MMU_H
-#define __MMU_H
-
-#ifdef CONFIG_METAG_USER_TCM
-#include <linux/list.h>
-#endif
-
-#ifdef CONFIG_HUGETLB_PAGE
-#include <asm/page.h>
-#endif
-
-typedef struct {
- /* Software pgd base pointer used for Meta 1.x MMU. */
- unsigned long pgd_base;
-#ifdef CONFIG_METAG_USER_TCM
- struct list_head tcm;
-#endif
-#ifdef CONFIG_HUGETLB_PAGE
-#if HPAGE_SHIFT < HUGEPT_SHIFT
- /* last partially filled huge page table address */
- unsigned long part_huge;
-#endif
-#endif
-} mm_context_t;
-
-/* Given a virtual address, return the pte for the top level 4meg entry
- * that maps that address.
- * Returns 0 (an empty pte) if that range is not mapped.
- */
-unsigned long mmu_read_first_level_page(unsigned long vaddr);
-
-/* Given a linear (virtual) address, return the second level 4k pte
- * that maps that address. Returns 0 if the address is not mapped.
- */
-unsigned long mmu_read_second_level_page(unsigned long vaddr);
-
-/* Get the virtual base address of the MMU */
-unsigned long mmu_get_base(void);
-
-/* Initialize the MMU. */
-void mmu_init(unsigned long mem_end);
-
-#ifdef CONFIG_METAG_META21_MMU
-/*
- * For cpu "cpu" calculate and return the address of the
- * MMCU_TnLOCAL_TABLE_PHYS0 if running in local-space or
- * MMCU_TnGLOBAL_TABLE_PHYS0 if running in global-space.
- */
-static inline unsigned long mmu_phys0_addr(unsigned int cpu)
-{
- unsigned long phys0;
-
- phys0 = (MMCU_T0LOCAL_TABLE_PHYS0 +
- (MMCU_TnX_TABLE_PHYSX_STRIDE * cpu)) +
- (MMCU_TXG_TABLE_PHYSX_OFFSET * is_global_space(PAGE_OFFSET));
-
- return phys0;
-}
-
-/*
- * For cpu "cpu" calculate and return the address of the
- * MMCU_TnLOCAL_TABLE_PHYS1 if running in local-space or
- * MMCU_TnGLOBAL_TABLE_PHYS1 if running in global-space.
- */
-static inline unsigned long mmu_phys1_addr(unsigned int cpu)
-{
- unsigned long phys1;
-
- phys1 = (MMCU_T0LOCAL_TABLE_PHYS1 +
- (MMCU_TnX_TABLE_PHYSX_STRIDE * cpu)) +
- (MMCU_TXG_TABLE_PHYSX_OFFSET * is_global_space(PAGE_OFFSET));
-
- return phys1;
-}
-#endif /* CONFIG_METAG_META21_MMU */
-
-#endif
diff --git a/arch/metag/include/asm/mmu_context.h b/arch/metag/include/asm/mmu_context.h
deleted file mode 100644
index 7b4766379622..000000000000
--- a/arch/metag/include/asm/mmu_context.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __METAG_MMU_CONTEXT_H
-#define __METAG_MMU_CONTEXT_H
-
-#include <asm-generic/mm_hooks.h>
-
-#include <asm/page.h>
-#include <asm/mmu.h>
-#include <asm/tlbflush.h>
-#include <asm/cacheflush.h>
-
-#include <linux/io.h>
-#include <linux/mm_types.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm,
- struct task_struct *tsk)
-{
-}
-
-static inline int init_new_context(struct task_struct *tsk,
- struct mm_struct *mm)
-{
-#ifndef CONFIG_METAG_META21_MMU
- /* We use context to store a pointer to the page holding the
- * pgd of a process while it is running. While a process is not
- * running the pgd and context fields should be equal.
- */
- mm->context.pgd_base = (unsigned long) mm->pgd;
-#endif
-#ifdef CONFIG_METAG_USER_TCM
- INIT_LIST_HEAD(&mm->context.tcm);
-#endif
- return 0;
-}
-
-#ifdef CONFIG_METAG_USER_TCM
-
-#include <linux/slab.h>
-#include <asm/tcm.h>
-
-static inline void destroy_context(struct mm_struct *mm)
-{
- struct tcm_allocation *pos, *n;
-
- list_for_each_entry_safe(pos, n, &mm->context.tcm, list) {
- tcm_free(pos->tag, pos->addr, pos->size);
- list_del(&pos->list);
- kfree(pos);
- }
-}
-#else
-#define destroy_context(mm) do { } while (0)
-#endif
-
-#ifdef CONFIG_METAG_META21_MMU
-static inline void load_pgd(pgd_t *pgd, int thread)
-{
- unsigned long phys0 = mmu_phys0_addr(thread);
- unsigned long phys1 = mmu_phys1_addr(thread);
-
- /*
- * 0x900 2Gb address space
- * The permission bits apply to MMU table region which gives a 2MB
- * window into physical memory. We especially don't want userland to be
- * able to access this.
- */
- metag_out32(0x900 | _PAGE_CACHEABLE | _PAGE_PRIV | _PAGE_WRITE |
- _PAGE_PRESENT, phys0);
- /* Set new MMU base address */
- metag_out32(__pa(pgd) & MMCU_TBLPHYS1_ADDR_BITS, phys1);
-}
-#endif
-
-static inline void switch_mmu(struct mm_struct *prev, struct mm_struct *next)
-{
-#ifdef CONFIG_METAG_META21_MMU
- load_pgd(next->pgd, hard_processor_id());
-#else
- unsigned int i;
-
- /* prev->context == prev->pgd in the case where we are initially
- switching from the init task to the first process. */
- if (prev->context.pgd_base != (unsigned long) prev->pgd) {
- for (i = FIRST_USER_PGD_NR; i < USER_PTRS_PER_PGD; i++)
- ((pgd_t *) prev->context.pgd_base)[i] = prev->pgd[i];
- } else
- prev->pgd = (pgd_t *)mmu_get_base();
-
- next->pgd = prev->pgd;
- prev->pgd = (pgd_t *) prev->context.pgd_base;
-
- for (i = FIRST_USER_PGD_NR; i < USER_PTRS_PER_PGD; i++)
- next->pgd[i] = ((pgd_t *) next->context.pgd_base)[i];
-
- flush_cache_all();
-#endif
- flush_tlb_all();
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- if (prev != next)
- switch_mmu(prev, next);
-}
-
-static inline void activate_mm(struct mm_struct *prev_mm,
- struct mm_struct *next_mm)
-{
- switch_mmu(prev_mm, next_mm);
-}
-
-#define deactivate_mm(tsk, mm) do { } while (0)
-
-#endif
diff --git a/arch/metag/include/asm/mmzone.h b/arch/metag/include/asm/mmzone.h
deleted file mode 100644
index 8627fb532206..000000000000
--- a/arch/metag/include/asm/mmzone.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_MMZONE_H
-#define __ASM_METAG_MMZONE_H
-
-#ifdef CONFIG_NEED_MULTIPLE_NODES
-#include <linux/numa.h>
-
-extern struct pglist_data *node_data[];
-#define NODE_DATA(nid) (node_data[nid])
-
-static inline int pfn_to_nid(unsigned long pfn)
-{
- int nid;
-
- for (nid = 0; nid < MAX_NUMNODES; nid++)
- if (pfn >= node_start_pfn(nid) && pfn <= node_end_pfn(nid))
- break;
-
- return nid;
-}
-
-static inline struct pglist_data *pfn_to_pgdat(unsigned long pfn)
-{
- return NODE_DATA(pfn_to_nid(pfn));
-}
-
-/* arch/metag/mm/numa.c */
-void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end);
-#else
-static inline void
-setup_bootmem_node(int nid, unsigned long start, unsigned long end)
-{
-}
-#endif /* CONFIG_NEED_MULTIPLE_NODES */
-
-#ifdef CONFIG_NUMA
-/* SoC specific mem init */
-void __init soc_mem_setup(void);
-#else
-static inline void __init soc_mem_setup(void) {};
-#endif
-
-#endif /* __ASM_METAG_MMZONE_H */
diff --git a/arch/metag/include/asm/module.h b/arch/metag/include/asm/module.h
deleted file mode 100644
index e957171c320b..000000000000
--- a/arch/metag/include/asm/module.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_MODULE_H
-#define _ASM_METAG_MODULE_H
-
-#include <asm-generic/module.h>
-
-struct metag_plt_entry {
- /* Indirect jump instruction sequence. */
- unsigned long tramp[2];
-};
-
-struct mod_arch_specific {
- /* Indices of PLT sections within module. */
- unsigned int core_plt_section, init_plt_section;
-};
-
-#if defined CONFIG_METAG_META12
-#define MODULE_PROC_FAMILY "META 1.2 "
-#elif defined CONFIG_METAG_META21
-#define MODULE_PROC_FAMILY "META 2.1 "
-#else
-#define MODULE_PROC_FAMILY ""
-#endif
-
-#ifdef CONFIG_4KSTACKS
-#define MODULE_STACKSIZE "4KSTACKS "
-#else
-#define MODULE_STACKSIZE ""
-#endif
-
-#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_STACKSIZE
-
-#ifdef MODULE
-asm(".section .plt,\"ax\",@progbits; .balign 8; .previous");
-asm(".section .init.plt,\"ax\",@progbits; .balign 8; .previous");
-#endif
-
-#endif /* _ASM_METAG_MODULE_H */
diff --git a/arch/metag/include/asm/page.h b/arch/metag/include/asm/page.h
deleted file mode 100644
index 9e994d77069d..000000000000
--- a/arch/metag/include/asm/page.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_PAGE_H
-#define _METAG_PAGE_H
-
-#include <linux/const.h>
-
-#include <asm/metag_mem.h>
-
-/* PAGE_SHIFT determines the page size */
-#if defined(CONFIG_PAGE_SIZE_4K)
-#define PAGE_SHIFT 12
-#elif defined(CONFIG_PAGE_SIZE_8K)
-#define PAGE_SHIFT 13
-#elif defined(CONFIG_PAGE_SIZE_16K)
-#define PAGE_SHIFT 14
-#endif
-
-#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#if defined(CONFIG_HUGETLB_PAGE_SIZE_8K)
-# define HPAGE_SHIFT 13
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_16K)
-# define HPAGE_SHIFT 14
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_32K)
-# define HPAGE_SHIFT 15
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
-# define HPAGE_SHIFT 16
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_128K)
-# define HPAGE_SHIFT 17
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
-# define HPAGE_SHIFT 18
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
-# define HPAGE_SHIFT 19
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1M)
-# define HPAGE_SHIFT 20
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_2M)
-# define HPAGE_SHIFT 21
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4M)
-# define HPAGE_SHIFT 22
-#endif
-
-#ifdef CONFIG_HUGETLB_PAGE
-# define HPAGE_SIZE (1UL << HPAGE_SHIFT)
-# define HPAGE_MASK (~(HPAGE_SIZE-1))
-# define HUGETLB_PAGE_ORDER (HPAGE_SHIFT-PAGE_SHIFT)
-/*
- * We define our own hugetlb_get_unmapped_area so we don't corrupt 2nd level
- * page tables with normal pages in them.
- */
-# define HUGEPT_SHIFT (22)
-# define HUGEPT_ALIGN (1 << HUGEPT_SHIFT)
-# define HUGEPT_MASK (HUGEPT_ALIGN - 1)
-# define ALIGN_HUGEPT(x) ALIGN(x, HUGEPT_ALIGN)
-# define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* On the Meta, we would like to know if the address (heap) we have is
- * in local or global space.
- */
-#define is_global_space(addr) ((addr) > 0x7fffffff)
-#define is_local_space(addr) (!is_global_space(addr))
-
-extern void clear_page(void *to);
-extern void copy_page(void *to, void *from);
-
-#define clear_user_page(page, vaddr, pg) clear_page(page)
-#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x) ((x).pte)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) })
-#define __pgd(x) ((pgd_t) { (x) })
-#define __pgprot(x) ((pgprot_t) { (x) })
-
-/* The kernel must now ALWAYS live at either 0xC0000000 or 0x40000000 - that
- * being either global or local space.
- */
-#define PAGE_OFFSET (CONFIG_PAGE_OFFSET)
-
-#if PAGE_OFFSET >= LINGLOBAL_BASE
-#define META_MEMORY_BASE LINGLOBAL_BASE
-#define META_MEMORY_LIMIT LINGLOBAL_LIMIT
-#else
-#define META_MEMORY_BASE LINLOCAL_BASE
-#define META_MEMORY_LIMIT LINLOCAL_LIMIT
-#endif
-
-/* Offset between physical and virtual mapping of kernel memory. */
-extern unsigned int meta_memoffset;
-
-#define __pa(x) ((unsigned long)(((unsigned long)(x)) - meta_memoffset))
-#define __va(x) ((void *)((unsigned long)(((unsigned long)(x)) + meta_memoffset)))
-
-extern unsigned long pfn_base;
-#define ARCH_PFN_OFFSET (pfn_base)
-#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
-#ifdef CONFIG_FLATMEM
-extern unsigned long max_pfn;
-extern unsigned long min_low_pfn;
-#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_pfn)
-#endif
-
-#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* __ASSMEBLY__ */
-
-#endif /* _METAG_PAGE_H */
diff --git a/arch/metag/include/asm/perf_event.h b/arch/metag/include/asm/perf_event.h
deleted file mode 100644
index 105bbff0149f..000000000000
--- a/arch/metag/include/asm/perf_event.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_METAG_PERF_EVENT_H
-#define __ASM_METAG_PERF_EVENT_H
-
-#endif /* __ASM_METAG_PERF_EVENT_H */
diff --git a/arch/metag/include/asm/pgalloc.h b/arch/metag/include/asm/pgalloc.h
deleted file mode 100644
index 0b9d95d78b61..000000000000
--- a/arch/metag/include/asm/pgalloc.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_PGALLOC_H
-#define _METAG_PGALLOC_H
-
-#include <linux/threads.h>
-#include <linux/mm.h>
-
-#define pmd_populate_kernel(mm, pmd, pte) \
- set_pmd(pmd, __pmd(_PAGE_TABLE | __pa(pte)))
-
-#define pmd_populate(mm, pmd, pte) \
- set_pmd(pmd, __pmd(_PAGE_TABLE | page_to_phys(pte)))
-
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-#ifdef CONFIG_METAG_META21_MMU
-static inline void pgd_ctor(pgd_t *pgd)
-{
- memcpy(pgd + USER_PTRS_PER_PGD,
- swapper_pg_dir + USER_PTRS_PER_PGD,
- (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
-}
-#else
-#define pgd_ctor(x) do { } while (0)
-#endif
-
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- pgd_t *pgd = (pgd_t *)get_zeroed_page(GFP_KERNEL);
- if (pgd)
- pgd_ctor(pgd);
- return pgd;
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- free_page((unsigned long)pgd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
- unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
- return pte;
-}
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- struct page *pte;
- pte = alloc_pages(GFP_KERNEL | __GFP_ZERO, 0);
- if (!pte)
- return NULL;
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long)pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-#define __pte_free_tlb(tlb, pte, addr) \
- do { \
- pgtable_page_dtor(pte); \
- tlb_remove_page((tlb), (pte)); \
- } while (0)
-
-#define check_pgt_cache() do { } while (0)
-
-#endif
diff --git a/arch/metag/include/asm/pgtable-bits.h b/arch/metag/include/asm/pgtable-bits.h
deleted file mode 100644
index 5f6b82282a41..000000000000
--- a/arch/metag/include/asm/pgtable-bits.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Meta page table definitions.
- */
-
-#ifndef _METAG_PGTABLE_BITS_H
-#define _METAG_PGTABLE_BITS_H
-
-#include <asm/metag_mem.h>
-
-/*
- * Definitions for MMU descriptors
- *
- * These are the hardware bits in the MMCU pte entries.
- * Derived from the Meta toolkit headers.
- */
-#define _PAGE_PRESENT MMCU_ENTRY_VAL_BIT
-#define _PAGE_WRITE MMCU_ENTRY_WR_BIT
-#define _PAGE_PRIV MMCU_ENTRY_PRIV_BIT
-/* Write combine bit - this can cause writes to occur out of order */
-#define _PAGE_WR_COMBINE MMCU_ENTRY_WRC_BIT
-/* Sys coherent bit - this bit is never used by Linux */
-#define _PAGE_SYS_COHERENT MMCU_ENTRY_SYS_BIT
-#define _PAGE_ALWAYS_ZERO_1 0x020
-#define _PAGE_CACHE_CTRL0 0x040
-#define _PAGE_CACHE_CTRL1 0x080
-#define _PAGE_ALWAYS_ZERO_2 0x100
-#define _PAGE_ALWAYS_ZERO_3 0x200
-#define _PAGE_ALWAYS_ZERO_4 0x400
-#define _PAGE_ALWAYS_ZERO_5 0x800
-
-/* These are software bits that we stuff into the gaps in the hardware
- * pte entries that are not used. Note, these DO get stored in the actual
- * hardware, but the hardware just does not use them.
- */
-#define _PAGE_ACCESSED _PAGE_ALWAYS_ZERO_1
-#define _PAGE_DIRTY _PAGE_ALWAYS_ZERO_2
-
-/* Pages owned, and protected by, the kernel. */
-#define _PAGE_KERNEL _PAGE_PRIV
-
-/* No cacheing of this page */
-#define _PAGE_CACHE_WIN0 (MMCU_CWIN_UNCACHED << MMCU_ENTRY_CWIN_S)
-/* burst cacheing - good for data streaming */
-#define _PAGE_CACHE_WIN1 (MMCU_CWIN_BURST << MMCU_ENTRY_CWIN_S)
-/* One cache way per thread */
-#define _PAGE_CACHE_WIN2 (MMCU_CWIN_C1SET << MMCU_ENTRY_CWIN_S)
-/* Full on cacheing */
-#define _PAGE_CACHE_WIN3 (MMCU_CWIN_CACHED << MMCU_ENTRY_CWIN_S)
-
-#define _PAGE_CACHEABLE (_PAGE_CACHE_WIN3 | _PAGE_WR_COMBINE)
-
-/* which bits are used for cache control ... */
-#define _PAGE_CACHE_MASK (_PAGE_CACHE_CTRL0 | _PAGE_CACHE_CTRL1 | \
- _PAGE_WR_COMBINE)
-
-/* This is a mask of the bits that pte_modify is allowed to change. */
-#define _PAGE_CHG_MASK (PAGE_MASK)
-
-#define _PAGE_SZ_SHIFT 1
-#define _PAGE_SZ_4K (0x0)
-#define _PAGE_SZ_8K (0x1 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_16K (0x2 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_32K (0x3 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_64K (0x4 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_128K (0x5 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_256K (0x6 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_512K (0x7 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_1M (0x8 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_2M (0x9 << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_4M (0xa << _PAGE_SZ_SHIFT)
-#define _PAGE_SZ_MASK (0xf << _PAGE_SZ_SHIFT)
-
-#if defined(CONFIG_PAGE_SIZE_4K)
-#define _PAGE_SZ (_PAGE_SZ_4K)
-#elif defined(CONFIG_PAGE_SIZE_8K)
-#define _PAGE_SZ (_PAGE_SZ_8K)
-#elif defined(CONFIG_PAGE_SIZE_16K)
-#define _PAGE_SZ (_PAGE_SZ_16K)
-#endif
-#define _PAGE_TABLE (_PAGE_SZ | _PAGE_PRESENT)
-
-#if defined(CONFIG_HUGETLB_PAGE_SIZE_8K)
-# define _PAGE_SZHUGE (_PAGE_SZ_8K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_16K)
-# define _PAGE_SZHUGE (_PAGE_SZ_16K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_32K)
-# define _PAGE_SZHUGE (_PAGE_SZ_32K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
-# define _PAGE_SZHUGE (_PAGE_SZ_64K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_128K)
-# define _PAGE_SZHUGE (_PAGE_SZ_128K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
-# define _PAGE_SZHUGE (_PAGE_SZ_256K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
-# define _PAGE_SZHUGE (_PAGE_SZ_512K)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1M)
-# define _PAGE_SZHUGE (_PAGE_SZ_1M)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_2M)
-# define _PAGE_SZHUGE (_PAGE_SZ_2M)
-#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4M)
-# define _PAGE_SZHUGE (_PAGE_SZ_4M)
-#endif
-
-#endif /* _METAG_PGTABLE_BITS_H */
diff --git a/arch/metag/include/asm/pgtable.h b/arch/metag/include/asm/pgtable.h
deleted file mode 100644
index a3422f06c03b..000000000000
--- a/arch/metag/include/asm/pgtable.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Macros and functions to manipulate Meta page tables.
- */
-
-#ifndef _METAG_PGTABLE_H
-#define _METAG_PGTABLE_H
-
-#include <asm/pgtable-bits.h>
-#define __ARCH_USE_5LEVEL_HACK
-#include <asm-generic/pgtable-nopmd.h>
-
-/* Invalid regions on Meta: 0x00000000-0x001FFFFF and 0xFFFF0000-0xFFFFFFFF */
-#if PAGE_OFFSET >= LINGLOBAL_BASE
-#define CONSISTENT_START 0xF7000000
-#define CONSISTENT_END 0xF73FFFFF
-#define VMALLOC_START 0xF8000000
-#define VMALLOC_END 0xFFFEFFFF
-#else
-#define CONSISTENT_START 0x77000000
-#define CONSISTENT_END 0x773FFFFF
-#define VMALLOC_START 0x78000000
-#define VMALLOC_END 0x7FFFFFFF
-#endif
-
-/*
- * The Linux memory management assumes a three-level page table setup. On
- * Meta, we use that, but "fold" the mid level into the top-level page
- * table.
- */
-
-/* PGDIR_SHIFT determines the size of the area a second-level page table can
- * map. This is always 4MB.
- */
-
-#define PGDIR_SHIFT 22
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE-1))
-
-/*
- * Entries per page directory level: we use a two-level, so
- * we don't really have any PMD directory physically. First level tables
- * always map 2Gb (local or global) at a granularity of 4MB, second-level
- * tables map 4MB with a granularity between 4MB and 4kB (between 1 and
- * 1024 entries).
- */
-#define PTRS_PER_PTE (PGDIR_SIZE/PAGE_SIZE)
-#define HPTRS_PER_PTE (PGDIR_SIZE/HPAGE_SIZE)
-#define PTRS_PER_PGD 512
-
-#define USER_PTRS_PER_PGD 256
-#define FIRST_USER_ADDRESS META_MEMORY_BASE
-#define FIRST_USER_PGD_NR pgd_index(FIRST_USER_ADDRESS)
-
-#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
- _PAGE_CACHEABLE)
-
-#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \
- _PAGE_ACCESSED | _PAGE_CACHEABLE)
-#define PAGE_SHARED_C PAGE_SHARED
-#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
- _PAGE_CACHEABLE)
-#define PAGE_COPY_C PAGE_COPY
-
-#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
- _PAGE_CACHEABLE)
-#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
- _PAGE_ACCESSED | _PAGE_WRITE | \
- _PAGE_CACHEABLE | _PAGE_KERNEL)
-
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY
-#define __P101 PAGE_READONLY
-#define __P110 PAGE_COPY_C
-#define __P111 PAGE_COPY_C
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY
-#define __S101 PAGE_READONLY
-#define __S110 PAGE_SHARED_C
-#define __S111 PAGE_SHARED_C
-
-#ifndef __ASSEMBLY__
-
-#include <asm/page.h>
-
-/* zero page used for uninitialized stuff */
-extern unsigned long empty_zero_page;
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-/* Certain architectures need to do special things when pte's
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-
-#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
-
-#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#define pte_none(x) (!pte_val(x))
-#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
-#define pte_clear(mm, addr, xp) do { pte_val(*(xp)) = 0; } while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_bad(x) ((pmd_val(x) & ~(PAGE_MASK | _PAGE_SZ_MASK)) \
- != (_PAGE_TABLE & ~_PAGE_SZ_MASK))
-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
-#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
-
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-
-static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_special(pte_t pte) { return 0; }
-
-static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= (~_PAGE_WRITE); return pte; }
-static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-static inline pte_t pte_mkhuge(pte_t pte) { return pte; }
-
-/*
- * Macro and implementation to make a page protection as uncacheable.
- */
-#define pgprot_writecombine(prot) \
- __pgprot(pgprot_val(prot) & ~(_PAGE_CACHE_CTRL1 | _PAGE_CACHE_CTRL0))
-
-#define pgprot_noncached(prot) \
- __pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE)
-
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
- return pte;
-}
-
-static inline unsigned long pmd_page_vaddr(pmd_t pmd)
-{
- unsigned long paddr = pmd_val(pmd) & PAGE_MASK;
- if (!paddr)
- return 0;
- return (unsigned long)__va(paddr);
-}
-
-#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
-#define pmd_page_shift(pmd) (12 + ((pmd_val(pmd) & _PAGE_SZ_MASK) \
- >> _PAGE_SZ_SHIFT))
-#define pmd_num_ptrs(pmd) (PGDIR_SIZE >> pmd_page_shift(pmd))
-
-/*
- * Each pgd is only 2k, mapping 2Gb (local or global). If we're in global
- * space drop the top bit before indexing the pgd.
- */
-#if PAGE_OFFSET >= LINGLOBAL_BASE
-#define pgd_index(address) ((((address) & ~0x80000000) >> PGDIR_SHIFT) \
- & (PTRS_PER_PGD-1))
-#else
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-#endif
-
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-
-/* Find an entry in the second-level page table.. */
-#if !defined(CONFIG_HUGETLB_PAGE)
- /* all pages are of size (1 << PAGE_SHIFT), so no need to read 1st level pt */
-# define pte_index(pmd, address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#else
- /* some pages are huge, so read 1st level pt to find out */
-# define pte_index(pmd, address) \
- (((address) >> pmd_page_shift(pmd)) & (pmd_num_ptrs(pmd) - 1))
-#endif
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(*(dir), address))
-#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
-#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
-
-#define pte_unmap(pte) do { } while (0)
-#define pte_unmap_nested(pte) do { } while (0)
-
-#define pte_ERROR(e) \
- pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pgd_ERROR(e) \
- pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-/*
- * Meta doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- */
-static inline void update_mmu_cache(struct vm_area_struct *vma,
- unsigned long address, pte_t *pte)
-{
-}
-
-/*
- * Encode and decode a swap entry (must be !pte_none(e) && !pte_present(e))
- * Since PAGE_PRESENT is bit 1, we can use the bits above that.
- */
-#define __swp_type(x) (((x).val >> 1) & 0xff)
-#define __swp_offset(x) ((x).val >> 10)
-#define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 1) | \
- ((offset) << 10) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
-
-#define kern_addr_valid(addr) (1)
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init() do { } while (0)
-
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-void paging_init(unsigned long mem_end);
-
-#ifdef CONFIG_METAG_META12
-/* This is a workaround for an issue in Meta 1 cores. These cores cache
- * invalid entries in the TLB so we always need to flush whenever we add
- * a new pte. Unfortunately we can only flush the whole TLB not shoot down
- * single entries so this is sub-optimal. This implementation ensures that
- * we will get a flush at the second attempt, so we may still get repeated
- * faults, we just don't overflow the kernel stack handling them.
- */
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-({ \
- int __changed = !pte_same(*(__ptep), __entry); \
- if (__changed) { \
- set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
- } \
- flush_tlb_page(__vma, __address); \
- __changed; \
-})
-#endif
-
-#include <asm-generic/pgtable.h>
-
-#endif /* __ASSEMBLY__ */
-#endif /* _METAG_PGTABLE_H */
diff --git a/arch/metag/include/asm/processor.h b/arch/metag/include/asm/processor.h
deleted file mode 100644
index 9a0c502cd4a0..000000000000
--- a/arch/metag/include/asm/processor.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2005,2006,2007,2008 Imagination Technologies
- */
-
-#ifndef __ASM_METAG_PROCESSOR_H
-#define __ASM_METAG_PROCESSOR_H
-
-#include <linux/atomic.h>
-
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <asm/metag_regs.h>
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l; })
-
-/* The task stops where the kernel starts */
-#define TASK_SIZE PAGE_OFFSET
-/* Add an extra page of padding at the top of the stack for the guard page. */
-#define STACK_TOP (TASK_SIZE - PAGE_SIZE)
-#define STACK_TOP_MAX STACK_TOP
-/* Maximum virtual space for stack */
-#define STACK_SIZE_MAX (CONFIG_MAX_STACK_SIZE_MB*1024*1024)
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE META_MEMORY_BASE
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#ifdef CONFIG_METAG_FPU
-struct meta_fpu_context {
- TBICTXEXTFPU fpstate;
- union {
- struct {
- TBICTXEXTBB4 fx8_15;
- TBICTXEXTFPACC fpacc;
- } fx8_15;
- struct {
- TBICTXEXTFPACC fpacc;
- TBICTXEXTBB4 unused;
- } nofx8_15;
- } extfpstate;
- bool needs_restore;
-};
-#else
-struct meta_fpu_context {};
-#endif
-
-#ifdef CONFIG_METAG_DSP
-struct meta_ext_context {
- struct {
- TBIEXTCTX ctx;
- TBICTXEXTBB8 bb8;
- TBIDUAL ax[TBICTXEXTAXX_BYTES / sizeof(TBIDUAL)];
- TBICTXEXTHL2 hl2;
- TBICTXEXTTDPR ext;
- TBICTXEXTRP6 rp;
- } regs;
-
- /* DSPRAM A and B save areas. */
- void *ram[2];
-
- /* ECH encoded size of DSPRAM save areas. */
- unsigned int ram_sz[2];
-};
-#else
-struct meta_ext_context {};
-#endif
-
-struct thread_struct {
- PTBICTX kernel_context;
- /* A copy of the user process Sig.SaveMask. */
- unsigned int user_flags;
- struct meta_fpu_context *fpu_context;
- void __user *tls_ptr;
- unsigned short int_depth;
- unsigned short txdefr_failure;
- struct meta_ext_context *dsp_context;
-};
-
-#define INIT_THREAD { \
- NULL, /* kernel_context */ \
- 0, /* user_flags */ \
- NULL, /* fpu_context */ \
- NULL, /* tls_ptr */ \
- 1, /* int_depth - we start in kernel */ \
- 0, /* txdefr_failure */ \
- NULL, /* dsp_context */ \
-}
-
-/* Needed to make #define as we are referencing 'current', that is not visible
- * yet.
- *
- * Stack layout is as below.
-
- argc argument counter (integer)
- argv[0] program name (pointer)
- argv[1...N] program args (pointers)
- argv[argc-1] end of args (integer)
- NULL
- env[0...N] environment variables (pointers)
- NULL
-
- */
-#define start_thread(regs, pc, usp) do { \
- unsigned int *argc = (unsigned int *) bprm->exec; \
- current->thread.int_depth = 1; \
- /* Force this process down to user land */ \
- regs->ctx.SaveMask = TBICTX_PRIV_BIT; \
- regs->ctx.CurrPC = pc; \
- regs->ctx.AX[0].U0 = usp; \
- regs->ctx.DX[3].U1 = *((int *)argc); /* argc */ \
- regs->ctx.DX[3].U0 = (int)((int *)argc + 1); /* argv */ \
- regs->ctx.DX[2].U1 = (int)((int *)argc + \
- regs->ctx.DX[3].U1 + 2); /* envp */ \
- regs->ctx.DX[2].U0 = 0; /* rtld_fini */ \
-} while (0)
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-#define thread_saved_pc(tsk) \
- ((unsigned long)(tsk)->thread.kernel_context->CurrPC)
-#define thread_saved_sp(tsk) \
- ((unsigned long)(tsk)->thread.kernel_context->AX[0].U0)
-#define thread_saved_fp(tsk) \
- ((unsigned long)(tsk)->thread.kernel_context->AX[1].U0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ctx.CurrPC)
-#define KSTK_ESP(tsk) (task_pt_regs(tsk)->ctx.AX[0].U0)
-
-#define user_stack_pointer(regs) ((regs)->ctx.AX[0].U0)
-
-#define cpu_relax() barrier()
-
-extern void setup_priv(void);
-
-static inline unsigned int hard_processor_id(void)
-{
- unsigned int id;
-
- asm volatile ("MOV %0, TXENABLE\n"
- "AND %0, %0, %1\n"
- "LSR %0, %0, %2\n"
- : "=&d" (id)
- : "I" (TXENABLE_THREAD_BITS),
- "K" (TXENABLE_THREAD_S)
- );
-
- return id;
-}
-
-#define OP3_EXIT 0
-
-#define HALT_OK 0
-#define HALT_PANIC -1
-
-/*
- * Halt (stop) the hardware thread. This instruction sequence is the
- * standard way to cause a Meta hardware thread to exit. The exit code
- * is pushed onto the stack which is interpreted by the debug adapter.
- */
-static inline void hard_processor_halt(int exit_code)
-{
- asm volatile ("MOV D1Ar1, %0\n"
- "MOV D0Ar6, %1\n"
- "MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2\n"
- "1:\n"
- "SWITCH #0xC30006\n"
- "B 1b\n"
- : : "r" (exit_code), "K" (OP3_EXIT));
-}
-
-/* Set these hooks to call SoC specific code to restart/halt/power off. */
-extern void (*soc_restart)(char *cmd);
-extern void (*soc_halt)(void);
-
-extern void show_trace(struct task_struct *tsk, unsigned long *sp,
- struct pt_regs *regs);
-
-extern const struct seq_operations cpuinfo_op;
-
-#endif
diff --git a/arch/metag/include/asm/ptrace.h b/arch/metag/include/asm/ptrace.h
deleted file mode 100644
index 9074f254c9ca..000000000000
--- a/arch/metag/include/asm/ptrace.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_PTRACE_H
-#define _METAG_PTRACE_H
-
-#include <linux/compiler.h>
-#include <uapi/asm/ptrace.h>
-#include <asm/tbx.h>
-
-#ifndef __ASSEMBLY__
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-struct pt_regs {
- TBICTX ctx;
- TBICTXEXTCB0 extcb0[5];
-};
-
-#define user_mode(regs) (((regs)->ctx.SaveMask & TBICTX_PRIV_BIT) > 0)
-
-#define instruction_pointer(regs) ((unsigned long)(regs)->ctx.CurrPC)
-#define profile_pc(regs) instruction_pointer(regs)
-
-#define task_pt_regs(task) \
- ((struct pt_regs *)(task_stack_page(task) + \
- sizeof(struct thread_info)))
-
-#define current_pt_regs() \
- ((struct pt_regs *)((char *)current_thread_info() + \
- sizeof(struct thread_info)))
-
-int syscall_trace_enter(struct pt_regs *regs);
-void syscall_trace_leave(struct pt_regs *regs);
-
-/* copy a struct user_gp_regs out to user */
-int metag_gp_regs_copyout(const struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf);
-/* copy a struct user_gp_regs in from user */
-int metag_gp_regs_copyin(struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf);
-/* copy a struct user_cb_regs out to user */
-int metag_cb_regs_copyout(const struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf);
-/* copy a struct user_cb_regs in from user */
-int metag_cb_regs_copyin(struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf);
-/* copy a struct user_rp_state out to user */
-int metag_rp_state_copyout(const struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf);
-/* copy a struct user_rp_state in from user */
-int metag_rp_state_copyin(struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf);
-
-#endif /* __ASSEMBLY__ */
-#endif /* _METAG_PTRACE_H */
diff --git a/arch/metag/include/asm/setup.h b/arch/metag/include/asm/setup.h
deleted file mode 100644
index 504621d79ef5..000000000000
--- a/arch/metag/include/asm/setup.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_SETUP_H
-#define _ASM_METAG_SETUP_H
-
-#include <uapi/asm/setup.h>
-
-extern const struct machine_desc *setup_machine_fdt(void *dt);
-void per_cpu_trap_init(unsigned long);
-extern void __init dump_machine_table(void);
-#endif /* _ASM_METAG_SETUP_H */
diff --git a/arch/metag/include/asm/smp.h b/arch/metag/include/asm/smp.h
deleted file mode 100644
index 8d3683d83680..000000000000
--- a/arch/metag/include/asm/smp.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_SMP_H
-#define __ASM_SMP_H
-
-#include <linux/cpumask.h>
-
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-
-enum ipi_msg_type {
- IPI_CALL_FUNC,
- IPI_RESCHEDULE,
-};
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-asmlinkage void secondary_start_kernel(void);
-
-extern void secondary_startup(void);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern void __cpu_die(unsigned int cpu);
-extern int __cpu_disable(void);
-extern void cpu_die(void);
-#endif
-
-extern void smp_init_cpus(void);
-#endif /* __ASM_SMP_H */
diff --git a/arch/metag/include/asm/sparsemem.h b/arch/metag/include/asm/sparsemem.h
deleted file mode 100644
index 2942894bace5..000000000000
--- a/arch/metag/include/asm/sparsemem.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_SPARSEMEM_H
-#define __ASM_METAG_SPARSEMEM_H
-
-/*
- * SECTION_SIZE_BITS 2^N: how big each section will be
- * MAX_PHYSADDR_BITS 2^N: how much physical address space we have
- * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
- */
-#define SECTION_SIZE_BITS 26
-#define MAX_PHYSADDR_BITS 32
-#define MAX_PHYSMEM_BITS 32
-
-#endif /* __ASM_METAG_SPARSEMEM_H */
diff --git a/arch/metag/include/asm/spinlock.h b/arch/metag/include/asm/spinlock.h
deleted file mode 100644
index 4497c232d9c1..000000000000
--- a/arch/metag/include/asm/spinlock.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_SPINLOCK_H
-#define __ASM_SPINLOCK_H
-
-#include <asm/barrier.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_METAG_ATOMICITY_LOCK1
-#include <asm/spinlock_lock1.h>
-#else
-#include <asm/spinlock_lnkget.h>
-#endif
-
-/*
- * both lock1 and lnkget are test-and-set spinlocks with 0 unlocked and 1
- * locked.
- */
-
-#endif /* __ASM_SPINLOCK_H */
diff --git a/arch/metag/include/asm/spinlock_lnkget.h b/arch/metag/include/asm/spinlock_lnkget.h
deleted file mode 100644
index dfd780eab350..000000000000
--- a/arch/metag/include/asm/spinlock_lnkget.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_SPINLOCK_LNKGET_H
-#define __ASM_SPINLOCK_LNKGET_H
-
-/*
- * None of these asm statements clobber memory as LNKSET writes around
- * the cache so the memory it modifies cannot safely be read by any means
- * other than these accessors.
- */
-
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- int ret;
-
- asm volatile ("LNKGETD %0, [%1]\n"
- "TST %0, #1\n"
- "MOV %0, #1\n"
- "XORZ %0, %0, %0\n"
- : "=&d" (ret)
- : "da" (&lock->lock)
- : "cc");
- return ret;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- int tmp;
-
- asm volatile ("1: LNKGETD %0,[%1]\n"
- " TST %0, #1\n"
- " ADD %0, %0, #1\n"
- " LNKSETDZ [%1], %0\n"
- " BNZ 1b\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- : "=&d" (tmp)
- : "da" (&lock->lock)
- : "cc");
-
- smp_mb();
-}
-
-/* Returns 0 if failed to acquire lock */
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int tmp;
-
- asm volatile (" LNKGETD %0,[%1]\n"
- " TST %0, #1\n"
- " ADD %0, %0, #1\n"
- " LNKSETDZ [%1], %0\n"
- " BNZ 1f\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " MOV %0, #1\n"
- "1: XORNZ %0, %0, %0\n"
- : "=&d" (tmp)
- : "da" (&lock->lock)
- : "cc");
-
- smp_mb();
-
- return tmp;
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- smp_mb();
-
- asm volatile (" SETD [%0], %1\n"
- :
- : "da" (&lock->lock), "da" (0)
- : "memory");
-}
-
-/*
- * RWLOCKS
- *
- *
- * Write locks are easy - we just set bit 31. When unlocking, we can
- * just write zero since the lock is exclusively held.
- */
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- int tmp;
-
- asm volatile ("1: LNKGETD %0,[%1]\n"
- " CMP %0, #0\n"
- " ADD %0, %0, %2\n"
- " LNKSETDZ [%1], %0\n"
- " BNZ 1b\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- : "=&d" (tmp)
- : "da" (&rw->lock), "bd" (0x80000000)
- : "cc");
-
- smp_mb();
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
- int tmp;
-
- asm volatile (" LNKGETD %0,[%1]\n"
- " CMP %0, #0\n"
- " ADD %0, %0, %2\n"
- " LNKSETDZ [%1], %0\n"
- " BNZ 1f\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " MOV %0,#1\n"
- "1: XORNZ %0, %0, %0\n"
- : "=&d" (tmp)
- : "da" (&rw->lock), "bd" (0x80000000)
- : "cc");
-
- smp_mb();
-
- return tmp;
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- smp_mb();
-
- asm volatile (" SETD [%0], %1\n"
- :
- : "da" (&rw->lock), "da" (0)
- : "memory");
-}
-
-/*
- * Read locks are a bit more hairy:
- * - Exclusively load the lock value.
- * - Increment it.
- * - Store new lock value if positive, and we still own this location.
- * If the value is negative, we've already failed.
- * - If we failed to store the value, we want a negative result.
- * - If we failed, try again.
- * Unlocking is similarly hairy. We may have multiple read locks
- * currently active. However, we know we won't have any write
- * locks.
- */
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- int tmp;
-
- asm volatile ("1: LNKGETD %0,[%1]\n"
- " ADDS %0, %0, #1\n"
- " LNKSETDPL [%1], %0\n"
- " BMI 1b\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- : "=&d" (tmp)
- : "da" (&rw->lock)
- : "cc");
-
- smp_mb();
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- int tmp;
-
- smp_mb();
-
- asm volatile ("1: LNKGETD %0,[%1]\n"
- " SUB %0, %0, #1\n"
- " LNKSETD [%1], %0\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- : "=&d" (tmp)
- : "da" (&rw->lock)
- : "cc", "memory");
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
- int tmp;
-
- asm volatile (" LNKGETD %0,[%1]\n"
- " ADDS %0, %0, #1\n"
- " LNKSETDPL [%1], %0\n"
- " BMI 1f\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " MOV %0,#1\n"
- " BZ 2f\n"
- "1: MOV %0,#0\n"
- "2:\n"
- : "=&d" (tmp)
- : "da" (&rw->lock)
- : "cc");
-
- smp_mb();
-
- return tmp;
-}
-
-#endif /* __ASM_SPINLOCK_LNKGET_H */
diff --git a/arch/metag/include/asm/spinlock_lock1.h b/arch/metag/include/asm/spinlock_lock1.h
deleted file mode 100644
index c0bd81bbe18c..000000000000
--- a/arch/metag/include/asm/spinlock_lock1.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_SPINLOCK_LOCK1_H
-#define __ASM_SPINLOCK_LOCK1_H
-
-#include <asm/bug.h>
-#include <asm/global_lock.h>
-
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- int ret;
-
- barrier();
- ret = lock->lock;
- WARN_ON(ret != 0 && ret != 1);
- return ret;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- unsigned int we_won = 0;
- unsigned long flags;
-
-again:
- __global_lock1(flags);
- if (lock->lock == 0) {
- fence();
- lock->lock = 1;
- we_won = 1;
- }
- __global_unlock1(flags);
- if (we_won == 0)
- goto again;
- WARN_ON(lock->lock != 1);
-}
-
-/* Returns 0 if failed to acquire lock */
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- unsigned long flags;
- unsigned int ret;
-
- __global_lock1(flags);
- ret = lock->lock;
- if (ret == 0) {
- fence();
- lock->lock = 1;
- }
- __global_unlock1(flags);
- return (ret == 0);
-}
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- barrier();
- WARN_ON(!lock->lock);
- lock->lock = 0;
-}
-
-/*
- * RWLOCKS
- *
- *
- * Write locks are easy - we just set bit 31. When unlocking, we can
- * just write zero since the lock is exclusively held.
- */
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- unsigned long flags;
- unsigned int we_won = 0;
-
-again:
- __global_lock1(flags);
- if (rw->lock == 0) {
- fence();
- rw->lock = 0x80000000;
- we_won = 1;
- }
- __global_unlock1(flags);
- if (we_won == 0)
- goto again;
- WARN_ON(rw->lock != 0x80000000);
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
- unsigned long flags;
- unsigned int ret;
-
- __global_lock1(flags);
- ret = rw->lock;
- if (ret == 0) {
- fence();
- rw->lock = 0x80000000;
- }
- __global_unlock1(flags);
-
- return (ret == 0);
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- barrier();
- WARN_ON(rw->lock != 0x80000000);
- rw->lock = 0;
-}
-
-/*
- * Read locks are a bit more hairy:
- * - Exclusively load the lock value.
- * - Increment it.
- * - Store new lock value if positive, and we still own this location.
- * If the value is negative, we've already failed.
- * - If we failed to store the value, we want a negative result.
- * - If we failed, try again.
- * Unlocking is similarly hairy. We may have multiple read locks
- * currently active. However, we know we won't have any write
- * locks.
- */
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- unsigned long flags;
- unsigned int we_won = 0, ret;
-
-again:
- __global_lock1(flags);
- ret = rw->lock;
- if (ret < 0x80000000) {
- fence();
- rw->lock = ret + 1;
- we_won = 1;
- }
- __global_unlock1(flags);
- if (!we_won)
- goto again;
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- unsigned long flags;
- unsigned int ret;
-
- __global_lock1(flags);
- fence();
- ret = rw->lock--;
- __global_unlock1(flags);
- WARN_ON(ret == 0);
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
- unsigned long flags;
- unsigned int ret;
-
- __global_lock1(flags);
- ret = rw->lock;
- if (ret < 0x80000000) {
- fence();
- rw->lock = ret + 1;
- }
- __global_unlock1(flags);
- return (ret < 0x80000000);
-}
-
-#endif /* __ASM_SPINLOCK_LOCK1_H */
diff --git a/arch/metag/include/asm/spinlock_types.h b/arch/metag/include/asm/spinlock_types.h
deleted file mode 100644
index cd197f1bed59..000000000000
--- a/arch/metag/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_SPINLOCK_TYPES_H
-#define _ASM_METAG_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
- volatile unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- volatile unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { 0 }
-
-#endif /* _ASM_METAG_SPINLOCK_TYPES_H */
diff --git a/arch/metag/include/asm/stacktrace.h b/arch/metag/include/asm/stacktrace.h
deleted file mode 100644
index f45e3cb2bbb5..000000000000
--- a/arch/metag/include/asm/stacktrace.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_STACKTRACE_H
-#define __ASM_STACKTRACE_H
-
-struct stackframe {
- unsigned long fp;
- unsigned long sp;
- unsigned long lr;
- unsigned long pc;
-};
-
-struct metag_frame {
- unsigned long fp;
- unsigned long lr;
-};
-
-extern int unwind_frame(struct stackframe *frame);
-extern void walk_stackframe(struct stackframe *frame,
- int (*fn)(struct stackframe *, void *), void *data);
-
-#endif /* __ASM_STACKTRACE_H */
diff --git a/arch/metag/include/asm/string.h b/arch/metag/include/asm/string.h
deleted file mode 100644
index 86f9614d5fc6..000000000000
--- a/arch/metag/include/asm/string.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_STRING_H_
-#define _METAG_STRING_H_
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *__s, int __c, size_t __count);
-
-#define __HAVE_ARCH_MEMCPY
-void *memcpy(void *__to, __const__ void *__from, size_t __n);
-
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-
-#endif /* _METAG_STRING_H_ */
diff --git a/arch/metag/include/asm/switch.h b/arch/metag/include/asm/switch.h
deleted file mode 100644
index 1fd6a587c844..000000000000
--- a/arch/metag/include/asm/switch.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef _ASM_METAG_SWITCH_H
-#define _ASM_METAG_SWITCH_H
-
-/* metag SWITCH codes */
-#define __METAG_SW_PERM_BREAK 0x400002 /* compiled in breakpoint */
-#define __METAG_SW_SYS_LEGACY 0x440000 /* legacy system calls */
-#define __METAG_SW_SYS 0x440001 /* system calls */
-
-/* metag SWITCH instruction encoding */
-#define __METAG_SW_ENCODING(TYPE) (0xaf000000 | (__METAG_SW_##TYPE))
-
-#endif /* _ASM_METAG_SWITCH_H */
diff --git a/arch/metag/include/asm/syscall.h b/arch/metag/include/asm/syscall.h
deleted file mode 100644
index 24fc97939f77..000000000000
--- a/arch/metag/include/asm/syscall.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Access to user system call parameters and results
- *
- * Copyright (C) 2008 Imagination Technologies Ltd.
- *
- * This copyrighted material is made available to anyone wishing to use,
- * modify, copy, or redistribute it subject to the terms and conditions
- * of the GNU General Public License v.2.
- *
- * See asm-generic/syscall.h for descriptions of what we must do here.
- */
-
-#ifndef _ASM_METAG_SYSCALL_H
-#define _ASM_METAG_SYSCALL_H
-
-#include <linux/sched.h>
-#include <linux/err.h>
-#include <linux/uaccess.h>
-
-#include <asm/switch.h>
-
-static inline long syscall_get_nr(struct task_struct *task,
- struct pt_regs *regs)
-{
- unsigned long insn;
-
- /*
- * FIXME there's no way to find out how we got here other than to
- * examine the memory at the PC to see if it is a syscall
- * SWITCH instruction.
- */
- if (get_user(insn, (unsigned long *)(regs->ctx.CurrPC - 4)))
- return -1;
-
- if (insn == __METAG_SW_ENCODING(SYS))
- return regs->ctx.DX[0].U1;
- else
- return -1L;
-}
-
-static inline void syscall_rollback(struct task_struct *task,
- struct pt_regs *regs)
-{
- /* do nothing */
-}
-
-static inline long syscall_get_error(struct task_struct *task,
- struct pt_regs *regs)
-{
- unsigned long error = regs->ctx.DX[0].U0;
- return IS_ERR_VALUE(error) ? error : 0;
-}
-
-static inline long syscall_get_return_value(struct task_struct *task,
- struct pt_regs *regs)
-{
- return regs->ctx.DX[0].U0;
-}
-
-static inline void syscall_set_return_value(struct task_struct *task,
- struct pt_regs *regs,
- int error, long val)
-{
- regs->ctx.DX[0].U0 = (long) error ?: val;
-}
-
-static inline void syscall_get_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- unsigned long *args)
-{
- unsigned int reg, j;
- BUG_ON(i + n > 6);
-
- for (j = i, reg = 6 - i; j < (i + n); j++, reg--) {
- if (reg % 2)
- args[j] = regs->ctx.DX[(reg + 1) / 2].U0;
- else
- args[j] = regs->ctx.DX[reg / 2].U1;
- }
-}
-
-static inline void syscall_set_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- const unsigned long *args)
-{
- unsigned int reg;
- BUG_ON(i + n > 6);
-
- for (reg = 6 - i; i < (i + n); i++, reg--) {
- if (reg % 2)
- regs->ctx.DX[(reg + 1) / 2].U0 = args[i];
- else
- regs->ctx.DX[reg / 2].U1 = args[i];
- }
-}
-
-#define NR_syscalls __NR_syscalls
-
-/* generic syscall table */
-extern const void *sys_call_table[];
-
-#endif /* _ASM_METAG_SYSCALL_H */
diff --git a/arch/metag/include/asm/syscalls.h b/arch/metag/include/asm/syscalls.h
deleted file mode 100644
index eac0cf120323..000000000000
--- a/arch/metag/include/asm/syscalls.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_SYSCALLS_H
-#define _ASM_METAG_SYSCALLS_H
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-#include <linux/signal.h>
-
-/* kernel/signal.c */
-#define sys_rt_sigreturn sys_rt_sigreturn
-asmlinkage long sys_rt_sigreturn(void);
-
-#include <asm-generic/syscalls.h>
-
-/* kernel/sys_metag.c */
-asmlinkage int sys_metag_setglobalbit(char __user *, int);
-asmlinkage void sys_metag_set_fpu_flags(unsigned int);
-asmlinkage int sys_metag_set_tls(void __user *);
-asmlinkage void *sys_metag_get_tls(void);
-
-asmlinkage long sys_truncate64_metag(const char __user *, unsigned long,
- unsigned long);
-asmlinkage long sys_ftruncate64_metag(unsigned int, unsigned long,
- unsigned long);
-asmlinkage long sys_fadvise64_64_metag(int, unsigned long, unsigned long,
- unsigned long, unsigned long, int);
-asmlinkage long sys_readahead_metag(int, unsigned long, unsigned long, size_t);
-asmlinkage ssize_t sys_pread64_metag(unsigned long, char __user *, size_t,
- unsigned long, unsigned long);
-asmlinkage ssize_t sys_pwrite64_metag(unsigned long, char __user *, size_t,
- unsigned long, unsigned long);
-asmlinkage long sys_sync_file_range_metag(int, unsigned long, unsigned long,
- unsigned long, unsigned long,
- unsigned int);
-
-int do_work_pending(struct pt_regs *regs, unsigned int thread_flags,
- int syscall);
-
-#endif /* _ASM_METAG_SYSCALLS_H */
diff --git a/arch/metag/include/asm/tbx.h b/arch/metag/include/asm/tbx.h
deleted file mode 100644
index 5cd2a6c86223..000000000000
--- a/arch/metag/include/asm/tbx.h
+++ /dev/null
@@ -1,1420 +0,0 @@
-/*
- * asm/tbx.h
- *
- * Copyright (C) 2000-2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Thread binary interface header
- */
-
-#ifndef _ASM_METAG_TBX_H_
-#define _ASM_METAG_TBX_H_
-
-/* for CACHEW_* values */
-#include <asm/metag_isa.h>
-/* for LINSYSEVENT_* addresses */
-#include <asm/metag_mem.h>
-
-#ifdef TBI_1_4
-#ifndef TBI_MUTEXES_1_4
-#define TBI_MUTEXES_1_4
-#endif
-#ifndef TBI_SEMAPHORES_1_4
-#define TBI_SEMAPHORES_1_4
-#endif
-#ifndef TBI_ASYNC_SWITCH_1_4
-#define TBI_ASYNC_SWITCH_1_4
-#endif
-#ifndef TBI_FASTINT_1_4
-#define TBI_FASTINT_1_4
-#endif
-#endif
-
-
-/* Id values in the TBI system describe a segment using an arbitrary
- integer value and flags in the bottom 8 bits, the SIGPOLL value is
- used in cases where control over blocking or polling behaviour is
- needed. */
-#define TBID_SIGPOLL_BIT 0x02 /* Set bit in an Id value to poll vs block */
-/* Extended segment identifiers use strings in the string table */
-#define TBID_IS_SEGSTR( Id ) (((Id) & (TBID_SEGTYPE_BITS>>1)) == 0)
-
-/* Segment identifiers contain the following related bit-fields */
-#define TBID_SEGTYPE_BITS 0x0F /* One of the predefined segment types */
-#define TBID_SEGTYPE_S 0
-#define TBID_SEGSCOPE_BITS 0x30 /* Indicates the scope of the segment */
-#define TBID_SEGSCOPE_S 4
-#define TBID_SEGGADDR_BITS 0xC0 /* Indicates access possible via pGAddr */
-#define TBID_SEGGADDR_S 6
-
-/* Segments of memory can only really contain a few types of data */
-#define TBID_SEGTYPE_TEXT 0x02 /* Code segment */
-#define TBID_SEGTYPE_DATA 0x04 /* Data segment */
-#define TBID_SEGTYPE_STACK 0x06 /* Stack segment */
-#define TBID_SEGTYPE_HEAP 0x0A /* Heap segment */
-#define TBID_SEGTYPE_ROOT 0x0C /* Root block segments */
-#define TBID_SEGTYPE_STRING 0x0E /* String table segment */
-
-/* Segments have one of three possible scopes */
-#define TBID_SEGSCOPE_INIT 0 /* Temporary area for initialisation phase */
-#define TBID_SEGSCOPE_LOCAL 1 /* Private to this thread */
-#define TBID_SEGSCOPE_GLOBAL 2 /* Shared globally throughout the system */
-#define TBID_SEGSCOPE_SHARED 3 /* Limited sharing between local/global */
-
-/* For segment specifier a further field in two of the remaining bits
- indicates the usefulness of the pGAddr field in the segment descriptor
- descriptor. */
-#define TBID_SEGGADDR_NULL 0 /* pGAddr is NULL -> SEGSCOPE_(LOCAL|INIT) */
-#define TBID_SEGGADDR_READ 1 /* Only read via pGAddr */
-#define TBID_SEGGADDR_WRITE 2 /* Full access via pGAddr */
-#define TBID_SEGGADDR_EXEC 3 /* Only execute via pGAddr */
-
-/* The following values are common to both segment and signal Id value and
- live in the top 8 bits of the Id values. */
-
-/* The ISTAT bit indicates if segments are related to interrupt vs
- background level interfaces a thread can still handle all triggers at
- either level, but can also split these up if it wants to. */
-#define TBID_ISTAT_BIT 0x01000000
-#define TBID_ISTAT_S 24
-
-/* Privilege needed to access a segment is indicated by the next bit.
-
- This bit is set to mirror the current privilege level when starting a
- search for a segment - setting it yourself toggles the automatically
- generated state which is only useful to emulate unprivileged behaviour
- or access unprivileged areas of memory while at privileged level. */
-#define TBID_PSTAT_BIT 0x02000000
-#define TBID_PSTAT_S 25
-
-/* The top six bits of a signal/segment specifier identifies a thread within
- the system. This represents a segments owner. */
-#define TBID_THREAD_BITS 0xFC000000
-#define TBID_THREAD_S 26
-
-/* Special thread id values */
-#define TBID_THREAD_NULL (-32) /* Never matches any thread/segment id used */
-#define TBID_THREAD_GLOBAL (-31) /* Things global to all threads */
-#define TBID_THREAD_HOST ( -1) /* Host interface */
-#define TBID_THREAD_EXTIO (TBID_THREAD_HOST) /* Host based ExtIO i/f */
-
-/* Virtual Id's are used for external thread interface structures or the
- above special Id's */
-#define TBID_IS_VIRTTHREAD( Id ) ((Id) < 0)
-
-/* Real Id's are used for actual hardware threads that are local */
-#define TBID_IS_REALTHREAD( Id ) ((Id) >= 0)
-
-/* Generate a segment Id given Thread, Scope, and Type */
-#define TBID_SEG( Thread, Scope, Type ) (\
- ((Thread)<<TBID_THREAD_S) + ((Scope)<<TBID_SEGSCOPE_S) + (Type))
-
-/* Generate a signal Id given Thread and SigNum */
-#define TBID_SIG( Thread, SigNum ) (\
- ((Thread)<<TBID_THREAD_S) + ((SigNum)<<TBID_SIGNUM_S) + TBID_SIGNAL_BIT)
-
-/* Generate an Id that solely represents a thread - useful for cache ops */
-#define TBID_THD( Thread ) ((Thread)<<TBID_THREAD_S)
-#define TBID_THD_NULL ((TBID_THREAD_NULL) <<TBID_THREAD_S)
-#define TBID_THD_GLOBAL ((TBID_THREAD_GLOBAL)<<TBID_THREAD_S)
-
-/* Common exception handler (see TBID_SIGNUM_XXF below) receives hardware
- generated fault codes TBIXXF_SIGNUM_xxF in it's SigNum parameter */
-#define TBIXXF_SIGNUM_IIF 0x01 /* General instruction fault */
-#define TBIXXF_SIGNUM_PGF 0x02 /* Privilege general fault */
-#define TBIXXF_SIGNUM_DHF 0x03 /* Data access watchpoint HIT */
-#define TBIXXF_SIGNUM_IGF 0x05 /* Code fetch general read failure */
-#define TBIXXF_SIGNUM_DGF 0x07 /* Data access general read/write fault */
-#define TBIXXF_SIGNUM_IPF 0x09 /* Code fetch page fault */
-#define TBIXXF_SIGNUM_DPF 0x0B /* Data access page fault */
-#define TBIXXF_SIGNUM_IHF 0x0D /* Instruction breakpoint HIT */
-#define TBIXXF_SIGNUM_DWF 0x0F /* Data access read-only fault */
-
-/* Hardware signals communicate events between processing levels within a
- single thread all the _xxF cases are exceptions and are routed via a
- common exception handler, _SWx are software trap events and kicks including
- __TBISignal generated kicks, and finally _TRx are hardware triggers */
-#define TBID_SIGNUM_SW0 0x00 /* SWITCH GROUP 0 - Per thread user */
-#define TBID_SIGNUM_SW1 0x01 /* SWITCH GROUP 1 - Per thread system */
-#define TBID_SIGNUM_SW2 0x02 /* SWITCH GROUP 2 - Internal global request */
-#define TBID_SIGNUM_SW3 0x03 /* SWITCH GROUP 3 - External global request */
-#ifdef TBI_1_4
-#define TBID_SIGNUM_FPE 0x04 /* Deferred exception - Any IEEE 754 exception */
-#define TBID_SIGNUM_FPD 0x05 /* Deferred exception - Denormal exception */
-/* Reserved 0x6 for a reserved deferred exception */
-#define TBID_SIGNUM_BUS 0x07 /* Deferred exception - Bus Error */
-/* Reserved 0x08-0x09 */
-#else
-/* Reserved 0x04-0x09 */
-#endif
-/* Reserved 0x0A-0x0F */
-#define TBID_SIGNUM_TRT 0x10 /* Timer trigger */
-#define TBID_SIGNUM_LWK 0x11 /* Low level kick */
-#define TBID_SIGNUM_XXF 0x12 /* Fault handler - receives ALL _xxF sigs */
-#ifdef TBI_1_4
-#define TBID_SIGNUM_DFR 0x13 /* Deferred Exception handler */
-#else
-#define TBID_SIGNUM_FPE 0x13 /* FPE Exception handler */
-#endif
-/* External trigger one group 0x14 to 0x17 - per thread */
-#define TBID_SIGNUM_TR1(Thread) (0x14+(Thread))
-#define TBID_SIGNUM_T10 0x14
-#define TBID_SIGNUM_T11 0x15
-#define TBID_SIGNUM_T12 0x16
-#define TBID_SIGNUM_T13 0x17
-/* External trigger two group 0x18 to 0x1b - per thread */
-#define TBID_SIGNUM_TR2(Thread) (0x18+(Thread))
-#define TBID_SIGNUM_T20 0x18
-#define TBID_SIGNUM_T21 0x19
-#define TBID_SIGNUM_T22 0x1A
-#define TBID_SIGNUM_T23 0x1B
-#define TBID_SIGNUM_TR3 0x1C /* External trigger N-4 (global) */
-#define TBID_SIGNUM_TR4 0x1D /* External trigger N-3 (global) */
-#define TBID_SIGNUM_TR5 0x1E /* External trigger N-2 (global) */
-#define TBID_SIGNUM_TR6 0x1F /* External trigger N-1 (global) */
-#define TBID_SIGNUM_MAX 0x1F
-
-/* Return the trigger register(TXMASK[I]/TXSTAT[I]) bits related to
- each hardware signal, sometimes this is a many-to-one relationship. */
-#define TBI_TRIG_BIT(SigNum) (\
- ((SigNum) >= TBID_SIGNUM_TRT) ? 1<<((SigNum)-TBID_SIGNUM_TRT) :\
- ((SigNum) == TBID_SIGNUM_LWK) ? \
- TXSTAT_KICK_BIT : TXSTATI_BGNDHALT_BIT )
-
-/* Return the hardware trigger vector number for entries in the
- HWVEC0EXT table that will generate the required internal trigger. */
-#define TBI_TRIG_VEC(SigNum) (\
- ((SigNum) >= TBID_SIGNUM_T10) ? ((SigNum)-TBID_SIGNUM_TRT) : -1)
-
-/* Default trigger masks for each thread at background/interrupt level */
-#define TBI_TRIGS_INIT( Thread ) (\
- TXSTAT_KICK_BIT + TBI_TRIG_BIT(TBID_SIGNUM_TR1(Thread)) )
-#define TBI_INTS_INIT( Thread ) (\
- TXSTAT_KICK_BIT + TXSTATI_BGNDHALT_BIT \
- + TBI_TRIG_BIT(TBID_SIGNUM_TR2(Thread)) )
-
-#ifndef __ASSEMBLY__
-/* A spin-lock location is a zero-initialised location in memory */
-typedef volatile int TBISPIN, *PTBISPIN;
-
-/* A kick location is a hardware location you can write to
- * in order to cause a kick
- */
-typedef volatile int *PTBIKICK;
-
-#if defined(METAC_1_0) || defined(METAC_1_1)
-/* Macro to perform a kick */
-#define TBI_KICK( pKick ) do { pKick[0] = 1; } while (0)
-#else
-/* #define METAG_LIN_VALUES before including machine.h if required */
-#ifdef LINSYSEVENT_WR_COMBINE_FLUSH
-/* Macro to perform a kick - write combiners must be flushed */
-#define TBI_KICK( pKick ) do {\
- volatile int *pFlush = (volatile int *) LINSYSEVENT_WR_COMBINE_FLUSH; \
- pFlush[0] = 0; \
- pKick[0] = 1; } while (0)
-#endif
-#endif /* if defined(METAC_1_0) || defined(METAC_1_1) */
-#endif /* ifndef __ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-/* 64-bit dual unit state value */
-typedef struct _tbidual_tag_ {
- /* 32-bit value from a pair of registers in data or address units */
- int U0, U1;
-} TBIDUAL, *PTBIDUAL;
-#endif /* ifndef __ASSEMBLY__ */
-
-/* Byte offsets of fields within TBIDUAL */
-#define TBIDUAL_U0 (0)
-#define TBIDUAL_U1 (4)
-
-#define TBIDUAL_BYTES (8)
-
-#define TBICTX_CRIT_BIT 0x0001 /* ASync state saved in TBICTX */
-#define TBICTX_SOFT_BIT 0x0002 /* Sync state saved in TBICTX (other bits 0) */
-#ifdef TBI_FASTINT_1_4
-#define TBICTX_FINT_BIT 0x0004 /* Using Fast Interrupts */
-#endif
-#define TBICTX_FPAC_BIT 0x0010 /* FPU state in TBICTX, FPU active on entry */
-#define TBICTX_XMCC_BIT 0x0020 /* Bit to identify a MECC task */
-#define TBICTX_CBUF_BIT 0x0040 /* Hardware catch buffer flag from TXSTATUS */
-#define TBICTX_CBRP_BIT 0x0080 /* Read pipeline dirty from TXDIVTIME */
-#define TBICTX_XDX8_BIT 0x0100 /* Saved DX.8 to DX.15 too */
-#define TBICTX_XAXX_BIT 0x0200 /* Save remaining AX registers to AX.7 */
-#define TBICTX_XHL2_BIT 0x0400 /* Saved hardware loop registers too */
-#define TBICTX_XTDP_BIT 0x0800 /* Saved DSP registers too */
-#define TBICTX_XEXT_BIT 0x1000 /* Set if TBICTX.Ext.Ctx contains extended
- state save area, otherwise TBICTX.Ext.AX2
- just holds normal A0.2 and A1.2 states */
-#define TBICTX_WAIT_BIT 0x2000 /* Causes wait for trigger - sticky toggle */
-#define TBICTX_XCBF_BIT 0x4000 /* Catch buffer or RD extracted into TBICTX */
-#define TBICTX_PRIV_BIT 0x8000 /* Set if system uses 'privileged' model */
-
-#ifdef METAC_1_0
-#define TBICTX_XAX3_BIT 0x0200 /* Saved AX.5 to AX.7 for XAXX */
-#define TBICTX_AX_REGS 5 /* Ax.0 to Ax.4 are core GP regs on CHORUS */
-#else
-#define TBICTX_XAX4_BIT 0x0200 /* Saved AX.4 to AX.7 for XAXX */
-#define TBICTX_AX_REGS 4 /* Default is Ax.0 to Ax.3 */
-#endif
-
-#ifdef TBI_1_4
-#define TBICTX_CFGFPU_FX16_BIT 0x00010000 /* Save FX.8 to FX.15 too */
-
-/* The METAC_CORE_ID_CONFIG field indicates omitted DSP resources */
-#define METAC_COREID_CFGXCTX_MASK( Value ) (\
- ( (((Value & METAC_COREID_CFGDSP_BITS)>> \
- METAC_COREID_CFGDSP_S ) == METAC_COREID_CFGDSP_MIN) ? \
- ~(TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+ \
- TBICTX_XAXX_BIT+TBICTX_XDX8_BIT ) : ~0U ) )
-#endif
-
-/* Extended context state provides a standardised method for registering the
- arguments required by __TBICtxSave to save the additional register states
- currently in use by non general purpose code. The state of the __TBIExtCtx
- variable in the static space of the thread forms an extension of the base
- context of the thread.
-
- If ( __TBIExtCtx.Ctx.SaveMask == 0 ) then pExt is assumed to be NULL and
- the empty state of __TBIExtCtx is represented by the fact that
- TBICTX.SaveMask does not have the bit TBICTX_XEXT_BIT set.
-
- If ( __TBIExtCtx.Ctx.SaveMask != 0 ) then pExt should point at a suitably
- sized extended context save area (usually at the end of the stack space
- allocated by the current routine). This space should allow for the
- displaced state of A0.2 and A1.2 to be saved along with the other extended
- states indicated via __TBIExtCtx.Ctx.SaveMask. */
-#ifndef __ASSEMBLY__
-typedef union _tbiextctx_tag_ {
- long long Val;
- TBIDUAL AX2;
- struct _tbiextctxext_tag {
-#ifdef TBI_1_4
- short DspramSizes; /* DSPRAM sizes. Encoding varies between
- TBICtxAlloc and the ECH scheme. */
-#else
- short Reserved0;
-#endif
- short SaveMask; /* Flag bits for state saved */
- PTBIDUAL pExt; /* AX[2] state saved first plus Xxxx state */
-
- } Ctx;
-
-} TBIEXTCTX, *PTBIEXTCTX;
-
-/* Automatic registration of extended context save for __TBINestInts */
-extern TBIEXTCTX __TBIExtCtx;
-#endif /* ifndef __ASSEMBLY__ */
-
-/* Byte offsets of fields within TBIEXTCTX */
-#define TBIEXTCTX_AX2 (0)
-#define TBIEXTCTX_Ctx (0)
-#define TBIEXTCTX_Ctx_SaveMask (TBIEXTCTX_Ctx + 2)
-#define TBIEXTCTX_Ctx_pExt (TBIEXTCTX_Ctx + 2 + 2)
-
-/* Extended context data size calculation constants */
-#define TBICTXEXT_BYTES (8)
-#define TBICTXEXTBB8_BYTES (8*8)
-#define TBICTXEXTAX3_BYTES (3*8)
-#define TBICTXEXTAX4_BYTES (4*8)
-#ifdef METAC_1_0
-#define TBICTXEXTAXX_BYTES TBICTXEXTAX3_BYTES
-#else
-#define TBICTXEXTAXX_BYTES TBICTXEXTAX4_BYTES
-#endif
-#define TBICTXEXTHL2_BYTES (3*8)
-#define TBICTXEXTTDR_BYTES (27*8)
-#define TBICTXEXTTDP_BYTES TBICTXEXTTDR_BYTES
-
-#ifdef TBI_1_4
-#define TBICTXEXTFX8_BYTES (4*8)
-#define TBICTXEXTFPAC_BYTES (1*4 + 2*2 + 4*8)
-#define TBICTXEXTFACF_BYTES (3*8)
-#endif
-
-/* Maximum flag bits to be set via the TBICTX_EXTSET macro */
-#define TBICTXEXT_MAXBITS (TBICTX_XEXT_BIT| \
- TBICTX_XDX8_BIT|TBICTX_XAXX_BIT|\
- TBICTX_XHL2_BIT|TBICTX_XTDP_BIT )
-
-/* Maximum size of the extended context save area for current variant */
-#define TBICTXEXT_MAXBYTES (TBICTXEXT_BYTES+TBICTXEXTBB8_BYTES+\
- TBICTXEXTAXX_BYTES+TBICTXEXTHL2_BYTES+\
- TBICTXEXTTDP_BYTES )
-
-#ifdef TBI_FASTINT_1_4
-/* Maximum flag bits to be set via the TBICTX_EXTSET macro */
-#define TBICTX2EXT_MAXBITS (TBICTX_XDX8_BIT|TBICTX_XAXX_BIT|\
- TBICTX_XHL2_BIT|TBICTX_XTDP_BIT )
-
-/* Maximum size of the extended context save area for current variant */
-#define TBICTX2EXT_MAXBYTES (TBICTXEXTBB8_BYTES+TBICTXEXTAXX_BYTES\
- +TBICTXEXTHL2_BYTES+TBICTXEXTTDP_BYTES )
-#endif
-
-/* Specify extended resources being used by current routine, code must be
- assembler generated to utilise extended resources-
-
- MOV D0xxx,A0StP ; Perform alloca - routine should
- ADD A0StP,A0StP,#SaveSize ; setup/use A0FrP to access locals
- MOVT D1xxx,#SaveMask ; TBICTX_XEXT_BIT MUST be set
- SETL [A1GbP+#OG(___TBIExtCtx)],D0xxx,D1xxx
-
- NB: OG(___TBIExtCtx) is a special case supported for SETL/GETL operations
- on 64-bit sizes structures only, other accesses must be based on use
- of OGA(___TBIExtCtx).
-
- At exit of routine-
-
- MOV D0xxx,#0 ; Clear extended context save state
- MOV D1xxx,#0
- SETL [A1GbP+#OG(___TBIExtCtx)],D0xxx,D1xxx
- SUB A0StP,A0StP,#SaveSize ; If original A0StP required
-
- NB: Both the setting and clearing of the whole __TBIExtCtx MUST be done
- atomically in one 64-bit write operation.
-
- For simple interrupt handling only via __TBINestInts there should be no
- impact of the __TBIExtCtx system. If pre-emptive scheduling is being
- performed however (assuming __TBINestInts has already been called earlier
- on) then the following logic will correctly call __TBICtxSave if required
- and clear out the currently selected background task-
-
- if ( __TBIExtCtx.Ctx.SaveMask & TBICTX_XEXT_BIT )
- {
- / * Store extended states in pCtx * /
- State.Sig.SaveMask |= __TBIExtCtx.Ctx.SaveMask;
-
- (void) __TBICtxSave( State, (void *) __TBIExtCtx.Ctx.pExt );
- __TBIExtCtx.Val = 0;
- }
-
- and when restoring task states call __TBICtxRestore-
-
- / * Restore state from pCtx * /
- State.Sig.pCtx = pCtx;
- State.Sig.SaveMask = pCtx->SaveMask;
-
- if ( State.Sig.SaveMask & TBICTX_XEXT_BIT )
- {
- / * Restore extended states from pCtx * /
- __TBIExtCtx.Val = pCtx->Ext.Val;
-
- (void) __TBICtxRestore( State, (void *) __TBIExtCtx.Ctx.pExt );
- }
-
- */
-
-/* Critical thread state save area */
-#ifndef __ASSEMBLY__
-typedef struct _tbictx_tag_ {
- /* TXSTATUS_FLAG_BITS and TXSTATUS_LSM_STEP_BITS from TXSTATUS */
- short Flags;
- /* Mask indicates any extended context state saved; 0 -> Never run */
- short SaveMask;
- /* Saved PC value */
- int CurrPC;
- /* Saved critical register states */
- TBIDUAL DX[8];
- /* Background control register states - for cores without catch buffer
- base in DIVTIME the TXSTATUS bits RPVALID and RPMASK are stored with
- the real state TXDIVTIME in CurrDIVTIME */
- int CurrRPT, CurrBPOBITS, CurrMODE, CurrDIVTIME;
- /* Saved AX register states */
- TBIDUAL AX[2];
- TBIEXTCTX Ext;
- TBIDUAL AX3[TBICTX_AX_REGS-3];
-
- /* Any CBUF state to be restored by a handler return must be stored here.
- Other extended state can be stored anywhere - see __TBICtxSave and
- __TBICtxRestore. */
-
-} TBICTX, *PTBICTX;
-
-#ifdef TBI_FASTINT_1_4
-typedef struct _tbictx2_tag_ {
- TBIDUAL AX[2]; /* AU.0, AU.1 */
- TBIDUAL DX[2]; /* DU.0, DU.4 */
- int CurrMODE;
- int CurrRPT;
- int CurrSTATUS;
- void *CurrPC; /* PC in PC address space */
-} TBICTX2, *PTBICTX2;
-/* TBICTX2 is followed by:
- * TBICTXEXTCB0 if TXSTATUS.CBMarker
- * TBIDUAL * TXSTATUS.IRPCount if TXSTATUS.IRPCount > 0
- * TBICTXGP if using __TBIStdRootIntHandler or __TBIStdCtxSwitchRootIntHandler
- */
-
-typedef struct _tbictxgp_tag_ {
- short DspramSizes;
- short SaveMask;
- void *pExt;
- TBIDUAL DX[6]; /* DU.1-DU.3, DU.5-DU.7 */
- TBIDUAL AX[2]; /* AU.2-AU.3 */
-} TBICTXGP, *PTBICTXGP;
-
-#define TBICTXGP_DspramSizes (0)
-#define TBICTXGP_SaveMask (TBICTXGP_DspramSizes + 2)
-#define TBICTXGP_MAX_BYTES (2 + 2 + 4 + 8*(6+2))
-
-#endif
-#endif /* ifndef __ASSEMBLY__ */
-
-/* Byte offsets of fields within TBICTX */
-#define TBICTX_Flags (0)
-#define TBICTX_SaveMask (2)
-#define TBICTX_CurrPC (4)
-#define TBICTX_DX (2 + 2 + 4)
-#define TBICTX_CurrRPT (2 + 2 + 4 + 8 * 8)
-#define TBICTX_CurrMODE (2 + 2 + 4 + 8 * 8 + 4 + 4)
-#define TBICTX_AX (2 + 2 + 4 + 8 * 8 + 4 + 4 + 4 + 4)
-#define TBICTX_Ext (2 + 2 + 4 + 8 * 8 + 4 + 4 + 4 + 4 + 2 * 8)
-#define TBICTX_Ext_AX2 (TBICTX_Ext + TBIEXTCTX_AX2)
-#define TBICTX_Ext_AX2_U0 (TBICTX_Ext + TBIEXTCTX_AX2 + TBIDUAL_U0)
-#define TBICTX_Ext_AX2_U1 (TBICTX_Ext + TBIEXTCTX_AX2 + TBIDUAL_U1)
-#define TBICTX_Ext_Ctx_pExt (TBICTX_Ext + TBIEXTCTX_Ctx_pExt)
-#define TBICTX_Ext_Ctx_SaveMask (TBICTX_Ext + TBIEXTCTX_Ctx_SaveMask)
-
-#ifdef TBI_FASTINT_1_4
-#define TBICTX2_BYTES (8 * 2 + 8 * 2 + 4 + 4 + 4 + 4)
-#define TBICTXEXTCB0_BYTES (4 + 4 + 8)
-
-#define TBICTX2_CRIT_MAX_BYTES (TBICTX2_BYTES + TBICTXEXTCB0_BYTES + 6 * TBIDUAL_BYTES)
-#define TBI_SWITCH_NEXT_PC(PC, EXTRA) ((PC) + (EXTRA & 1) ? 8 : 4)
-#endif
-
-#ifndef __ASSEMBLY__
-/* Extended thread state save areas - catch buffer state element */
-typedef struct _tbictxextcb0_tag_ {
- /* Flags data and address value - see METAC_CATCH_VALUES in machine.h */
- unsigned long CBFlags, CBAddr;
- /* 64-bit data */
- TBIDUAL CBData;
-
-} TBICTXEXTCB0, *PTBICTXEXTCB0;
-
-/* Read pipeline state saved on later cores after single catch buffer slot */
-typedef struct _tbictxextrp6_tag_ {
- /* RPMask is TXSTATUS_RPMASK_BITS only, reserved is undefined */
- unsigned long RPMask, Reserved0;
- TBIDUAL CBData[6];
-
-} TBICTXEXTRP6, *PTBICTXEXTRP6;
-
-/* Extended thread state save areas - 8 DU register pairs */
-typedef struct _tbictxextbb8_tag_ {
- /* Remaining Data unit registers in 64-bit pairs */
- TBIDUAL UX[8];
-
-} TBICTXEXTBB8, *PTBICTXEXTBB8;
-
-/* Extended thread state save areas - 3 AU register pairs */
-typedef struct _tbictxextbb3_tag_ {
- /* Remaining Address unit registers in 64-bit pairs */
- TBIDUAL UX[3];
-
-} TBICTXEXTBB3, *PTBICTXEXTBB3;
-
-/* Extended thread state save areas - 4 AU register pairs or 4 FX pairs */
-typedef struct _tbictxextbb4_tag_ {
- /* Remaining Address unit or FPU registers in 64-bit pairs */
- TBIDUAL UX[4];
-
-} TBICTXEXTBB4, *PTBICTXEXTBB4;
-
-/* Extended thread state save areas - Hardware loop states (max 2) */
-typedef struct _tbictxexthl2_tag_ {
- /* Hardware looping register states */
- TBIDUAL Start, End, Count;
-
-} TBICTXEXTHL2, *PTBICTXEXTHL2;
-
-/* Extended thread state save areas - DSP register states */
-typedef struct _tbictxexttdp_tag_ {
- /* DSP 32-bit accumulator register state (Bits 31:0 of ACX.0) */
- TBIDUAL Acc32[1];
- /* DSP > 32-bit accumulator bits 63:32 of ACX.0 (zero-extended) */
- TBIDUAL Acc64[1];
- /* Twiddle register state, and three phase increment states */
- TBIDUAL PReg[4];
- /* Modulo region size, padded to 64-bits */
- int CurrMRSIZE, Reserved0;
-
-} TBICTXEXTTDP, *PTBICTXEXTTDP;
-
-/* Extended thread state save areas - DSP register states including DSP RAM */
-typedef struct _tbictxexttdpr_tag_ {
- /* DSP 32-bit accumulator register state (Bits 31:0 of ACX.0) */
- TBIDUAL Acc32[1];
- /* DSP 40-bit accumulator register state (Bits 39:8 of ACX.0) */
- TBIDUAL Acc40[1];
- /* DSP RAM Pointers */
- TBIDUAL RP0[2], WP0[2], RP1[2], WP1[2];
- /* DSP RAM Increments */
- TBIDUAL RPI0[2], WPI0[2], RPI1[2], WPI1[2];
- /* Template registers */
- unsigned long Tmplt[16];
- /* Modulo address region size and DSP RAM module region sizes */
- int CurrMRSIZE, CurrDRSIZE;
-
-} TBICTXEXTTDPR, *PTBICTXEXTTDPR;
-
-#ifdef TBI_1_4
-/* The METAC_ID_CORE register state is a marker for the FPU
- state that is then stored after this core header structure. */
-#define TBICTXEXTFPU_CONFIG_MASK ( (METAC_COREID_NOFPACC_BIT+ \
- METAC_COREID_CFGFPU_BITS ) << \
- METAC_COREID_CONFIG_BITS )
-
-/* Recorded FPU exception state from TXDEFR in DefrFpu */
-#define TBICTXEXTFPU_DEFRFPU_MASK (TXDEFR_FPU_FE_BITS)
-
-/* Extended thread state save areas - FPU register states */
-typedef struct _tbictxextfpu_tag_ {
- /* Stored METAC_CORE_ID CONFIG */
- int CfgFpu;
- /* Stored deferred TXDEFR bits related to FPU
- *
- * This is encoded as follows in order to fit into 16-bits:
- * DefrFPU:15 - 14 <= 0
- * :13 - 8 <= TXDEFR:21-16
- * : 7 - 6 <= 0
- * : 5 - 0 <= TXDEFR:5-0
- */
- short DefrFpu;
-
- /* TXMODE bits related to FPU */
- short ModeFpu;
-
- /* FPU Even/Odd register states */
- TBIDUAL FX[4];
-
- /* if CfgFpu & TBICTX_CFGFPU_FX16_BIT -> 1 then TBICTXEXTBB4 holds FX.8-15 */
- /* if CfgFpu & TBICTX_CFGFPU_NOACF_BIT -> 0 then TBICTXEXTFPACC holds state */
-} TBICTXEXTFPU, *PTBICTXEXTFPU;
-
-/* Extended thread state save areas - FPU accumulator state */
-typedef struct _tbictxextfpacc_tag_ {
- /* FPU accumulator register state - three 64-bit parts */
- TBIDUAL FAcc32[3];
-
-} TBICTXEXTFPACC, *PTBICTXEXTFPACC;
-#endif
-
-/* Prototype TBI structure */
-struct _tbi_tag_ ;
-
-/* A 64-bit return value used commonly in the TBI APIs */
-typedef union _tbires_tag_ {
- /* Save and load this value to get/set the whole result quickly */
- long long Val;
-
- /* Parameter of a fnSigs or __TBICtx* call */
- struct _tbires_sig_tag_ {
- /* TXMASK[I] bits zeroed upto and including current trigger level */
- unsigned short TrigMask;
- /* Control bits for handlers - see PTBIAPIFN documentation below */
- unsigned short SaveMask;
- /* Pointer to the base register context save area of the thread */
- PTBICTX pCtx;
- } Sig;
-
- /* Result of TBIThrdPrivId call */
- struct _tbires_thrdprivid_tag_ {
- /* Basic thread identifier; just TBID_THREAD_BITS */
- int Id;
- /* None thread number bits; TBID_ISTAT_BIT+TBID_PSTAT_BIT */
- int Priv;
- } Thrd;
-
- /* Parameter and Result of a __TBISwitch call */
- struct _tbires_switch_tag_ {
- /* Parameter passed across context switch */
- void *pPara;
- /* Thread context of other Thread includng restore flags */
- PTBICTX pCtx;
- } Switch;
-
- /* For extended S/W events only */
- struct _tbires_ccb_tag_ {
- void *pCCB;
- int COff;
- } CCB;
-
- struct _tbires_tlb_tag_ {
- int Leaf; /* TLB Leaf data */
- int Flags; /* TLB Flags */
- } Tlb;
-
-#ifdef TBI_FASTINT_1_4
- struct _tbires_intr_tag_ {
- short TrigMask;
- short SaveMask;
- PTBICTX2 pCtx;
- } Intr;
-#endif
-
-} TBIRES, *PTBIRES;
-#endif /* ifndef __ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-/* Prototype for all signal handler functions, called via ___TBISyncTrigger or
- ___TBIASyncTrigger.
-
- State.Sig.TrigMask will indicate the bits set within TXMASKI at
- the time of the handler call that have all been cleared to prevent
- nested interrupt occurring immediately.
-
- State.Sig.SaveMask is a bit-mask which will be set to Zero when a trigger
- occurs at background level and TBICTX_CRIT_BIT and optionally
- TBICTX_CBUF_BIT when a trigger occurs at interrupt level.
-
- TBICTX_CBUF_BIT reflects the state of TXSTATUS_CBMARKER_BIT for
- the interrupted background thread.
-
- State.Sig.pCtx will point at a TBICTX structure generated to hold the
- critical state of the interrupted thread at interrupt level and
- should be set to NULL when called at background level.
-
- Triggers will indicate the status of TXSTAT or TXSTATI sampled by the
- code that called the handler.
-
- Inst is defined as 'Inst' if the SigNum is TBID_SIGNUM_SWx and holds the
- actual SWITCH instruction detected, in other cases the value of this
- parameter is undefined.
-
- pTBI points at the PTBI structure related to the thread and processing
- level involved.
-
- TBIRES return value at both processing levels is similar in terms of any
- changes that the handler makes. By default the State argument value
- passed in should be returned.
-
- Sig.TrigMask value is bits to OR back into TXMASKI when the handler
- completes to enable currently disabled interrupts.
-
- Sig.SaveMask value is ignored.
-
- Sig.pCtx is ignored.
-
- */
-typedef TBIRES (*PTBIAPIFN)( TBIRES State, int SigNum,
- int Triggers, int Inst,
- volatile struct _tbi_tag_ *pTBI );
-#endif /* ifndef __ASSEMBLY__ */
-
-#ifndef __ASSEMBLY__
-/* The global memory map is described by a list of segment descriptors */
-typedef volatile struct _tbiseg_tag_ {
- volatile struct _tbiseg_tag_ *pLink;
- int Id; /* Id of the segment */
- TBISPIN Lock; /* Spin-lock for struct (normally 0) */
- unsigned int Bytes; /* Size of region in bytes */
- void *pGAddr; /* Base addr of region in global space */
- void *pLAddr; /* Base addr of region in local space */
- int Data[2]; /* Segment specific data (may be extended) */
-
-} TBISEG, *PTBISEG;
-#endif /* ifndef __ASSEMBLY__ */
-
-/* Offsets of fields in TBISEG structure */
-#define TBISEG_pLink ( 0)
-#define TBISEG_Id ( 4)
-#define TBISEG_Lock ( 8)
-#define TBISEG_Bytes (12)
-#define TBISEG_pGAddr (16)
-#define TBISEG_pLAddr (20)
-#define TBISEG_Data (24)
-
-#ifndef __ASSEMBLY__
-typedef volatile struct _tbi_tag_ {
- int SigMask; /* Bits set to represent S/W events */
- PTBIKICK pKick; /* Kick addr for S/W events */
- void *pCCB; /* Extended S/W events */
- PTBISEG pSeg; /* Related segment structure */
- PTBIAPIFN fnSigs[TBID_SIGNUM_MAX+1];/* Signal handler API table */
-} *PTBI, TBI;
-#endif /* ifndef __ASSEMBLY__ */
-
-/* Byte offsets of fields within TBI */
-#define TBI_SigMask (0)
-#define TBI_pKick (4)
-#define TBI_pCCB (8)
-#define TBI_pSeg (12)
-#define TBI_fnSigs (16)
-
-#ifdef TBI_1_4
-#ifndef __ASSEMBLY__
-/* This handler should be used for TBID_SIGNUM_DFR */
-extern TBIRES __TBIHandleDFR ( TBIRES State, int SigNum,
- int Triggers, int Inst,
- volatile struct _tbi_tag_ *pTBI );
-#endif
-#endif
-
-/* String table entry - special values */
-#define METAG_TBI_STRS (0x5300) /* Tag : If entry is valid */
-#define METAG_TBI_STRE (0x4500) /* Tag : If entry is end of table */
-#define METAG_TBI_STRG (0x4700) /* Tag : If entry is a gap */
-#define METAG_TBI_STRX (0x5A00) /* TransLen : If no translation present */
-
-#ifndef __ASSEMBLY__
-typedef volatile struct _tbistr_tag_ {
- short Bytes; /* Length of entry in Bytes */
- short Tag; /* Normally METAG_TBI_STRS(0x5300) */
- short Len; /* Length of the string entry (incl null) */
- short TransLen; /* Normally METAG_TBI_STRX(0x5A00) */
- char String[8]; /* Zero terminated (may-be bigger) */
-
-} TBISTR, *PTBISTR;
-#endif /* ifndef __ASSEMBLY__ */
-
-/* Cache size information - available as fields of Data[1] of global heap
- segment */
-#define METAG_TBI_ICACHE_SIZE_S 0 /* see comments below */
-#define METAG_TBI_ICACHE_SIZE_BITS 0x0000000F
-#define METAG_TBI_ICACHE_FILL_S 4
-#define METAG_TBI_ICACHE_FILL_BITS 0x000000F0
-#define METAG_TBI_DCACHE_SIZE_S 8
-#define METAG_TBI_DCACHE_SIZE_BITS 0x00000F00
-#define METAG_TBI_DCACHE_FILL_S 12
-#define METAG_TBI_DCACHE_FILL_BITS 0x0000F000
-
-/* METAG_TBI_xCACHE_SIZE
- Describes the physical cache size rounded up to the next power of 2
- relative to a 16K (2^14) cache. These sizes are encoded as a signed addend
- to this base power of 2, for example
- 4K -> 2^12 -> -2 (i.e. 12-14)
- 8K -> 2^13 -> -1
- 16K -> 2^14 -> 0
- 32K -> 2^15 -> +1
- 64K -> 2^16 -> +2
- 128K -> 2^17 -> +3
-
- METAG_TBI_xCACHE_FILL
- Describes the physical cache size within the power of 2 area given by
- the value above. For example a 10K cache may be represented as having
- nearest size 16K with a fill of 10 sixteenths. This is encoded as the
- number of unused 1/16ths, for example
- 0000 -> 0 -> 16/16
- 0001 -> 1 -> 15/16
- 0010 -> 2 -> 14/16
- ...
- 1111 -> 15 -> 1/16
- */
-
-#define METAG_TBI_CACHE_SIZE_BASE_LOG2 14
-
-/* Each declaration made by this macro generates a TBISTR entry */
-#ifndef __ASSEMBLY__
-#define TBISTR_DECL( Name, Str ) \
- __attribute__ ((__section__ (".tbistr") )) const char Name[] = #Str
-#endif
-
-/* META timer values - see below for Timer support routines */
-#define TBI_TIMERWAIT_MIN (-16) /* Minimum 'recommended' period */
-#define TBI_TIMERWAIT_MAX (-0x7FFFFFFF) /* Maximum 'recommended' period */
-
-#ifndef __ASSEMBLY__
-/* These macros allow direct access from C to any register known to the
- assembler or defined in machine.h. Example candidates are TXTACTCYC,
- TXIDLECYC, and TXPRIVEXT. Note that when higher level macros and routines
- like the timer and trigger handling features below these should be used in
- preference to this direct low-level access mechanism. */
-#define TBI_GETREG( Reg ) __extension__ ({\
- int __GRValue; \
- __asm__ volatile ("MOV\t%0," #Reg "\t/* (*TBI_GETREG OK) */" : \
- "=r" (__GRValue) ); \
- __GRValue; })
-
-#define TBI_SETREG( Reg, Value ) do {\
- int __SRValue = Value; \
- __asm__ volatile ("MOV\t" #Reg ",%0\t/* (*TBI_SETREG OK) */" : \
- : "r" (__SRValue) ); } while (0)
-
-#define TBI_SWAPREG( Reg, Value ) do {\
- int __XRValue = (Value); \
- __asm__ volatile ("SWAP\t" #Reg ",%0\t/* (*TBI_SWAPREG OK) */" : \
- "=r" (__XRValue) : "0" (__XRValue) ); \
- Value = __XRValue; } while (0)
-
-/* Obtain and/or release global critical section lock given that interrupts
- are already disabled and/or should remain disabled. */
-#define TBI_NOINTSCRITON do {\
- __asm__ volatile ("LOCK1\t\t/* (*TBI_NOINTSCRITON OK) */");} while (0)
-#define TBI_NOINTSCRITOFF do {\
- __asm__ volatile ("LOCK0\t\t/* (*TBI_NOINTSCRITOFF OK) */");} while (0)
-/* Optimised in-lining versions of the above macros */
-
-#define TBI_LOCK( TrigState ) do {\
- int __TRValue; \
- int __ALOCKHI = LINSYSEVENT_WR_ATOMIC_LOCK & 0xFFFF0000; \
- __asm__ volatile ("MOV %0,#0\t\t/* (*TBI_LOCK ... */\n\t" \
- "SWAP\t%0,TXMASKI\t/* ... */\n\t" \
- "LOCK2\t\t/* ... */\n\t" \
- "SETD\t[%1+#0x40],D1RtP /* ... OK) */" : \
- "=r&" (__TRValue) : "u" (__ALOCKHI) ); \
- TrigState = __TRValue; } while (0)
-#define TBI_CRITON( TrigState ) do {\
- int __TRValue; \
- __asm__ volatile ("MOV %0,#0\t\t/* (*TBI_CRITON ... */\n\t" \
- "SWAP\t%0,TXMASKI\t/* ... */\n\t" \
- "LOCK1\t\t/* ... OK) */" : \
- "=r" (__TRValue) ); \
- TrigState = __TRValue; } while (0)
-
-#define TBI_INTSX( TrigState ) do {\
- int __TRValue = TrigState; \
- __asm__ volatile ("SWAP\t%0,TXMASKI\t/* (*TBI_INTSX OK) */" : \
- "=r" (__TRValue) : "0" (__TRValue) ); \
- TrigState = __TRValue; } while (0)
-
-#define TBI_UNLOCK( TrigState ) do {\
- int __TRValue = TrigState; \
- int __ALOCKHI = LINSYSEVENT_WR_ATOMIC_LOCK & 0xFFFF0000; \
- __asm__ volatile ("SETD\t[%1+#0x00],D1RtP\t/* (*TBI_UNLOCK ... */\n\t" \
- "LOCK0\t\t/* ... */\n\t" \
- "MOV\tTXMASKI,%0\t/* ... OK) */" : \
- : "r" (__TRValue), "u" (__ALOCKHI) ); } while (0)
-
-#define TBI_CRITOFF( TrigState ) do {\
- int __TRValue = TrigState; \
- __asm__ volatile ("LOCK0\t\t/* (*TBI_CRITOFF ... */\n\t" \
- "MOV\tTXMASKI,%0\t/* ... OK) */" : \
- : "r" (__TRValue) ); } while (0)
-
-#define TBI_TRIGSX( SrcDst ) do { TBI_SWAPREG( TXMASK, SrcDst );} while (0)
-
-/* Composite macros to perform logic ops on INTS or TRIGS masks */
-#define TBI_INTSOR( Bits ) do {\
- int __TT = 0; TBI_INTSX(__TT); \
- __TT |= (Bits); TBI_INTSX(__TT); } while (0)
-
-#define TBI_INTSAND( Bits ) do {\
- int __TT = 0; TBI_INTSX(__TT); \
- __TT &= (Bits); TBI_INTSX(__TT); } while (0)
-
-#ifdef TBI_1_4
-#define TBI_DEFRICTRLSOR( Bits ) do {\
- int __TT = TBI_GETREG( CT.20 ); \
- __TT |= (Bits); TBI_SETREG( CT.20, __TT); } while (0)
-
-#define TBI_DEFRICTRLSAND( Bits ) do {\
- int __TT = TBI_GETREG( TXDEFR ); \
- __TT &= (Bits); TBI_SETREG( CT.20, __TT); } while (0)
-#endif
-
-#define TBI_TRIGSOR( Bits ) do {\
- int __TT = TBI_GETREG( TXMASK ); \
- __TT |= (Bits); TBI_SETREG( TXMASK, __TT); } while (0)
-
-#define TBI_TRIGSAND( Bits ) do {\
- int __TT = TBI_GETREG( TXMASK ); \
- __TT &= (Bits); TBI_SETREG( TXMASK, __TT); } while (0)
-
-/* Macros to disable and re-enable interrupts using TBI_INTSX, deliberate
- traps and exceptions can still be handled within the critical section. */
-#define TBI_STOPINTS( Value ) do {\
- int __TT = TBI_GETREG( TXMASKI ); \
- __TT &= TXSTATI_BGNDHALT_BIT; TBI_INTSX( __TT ); \
- Value = __TT; } while (0)
-#define TBI_RESTINTS( Value ) do {\
- int __TT = Value; TBI_INTSX( __TT ); } while (0)
-
-/* Return pointer to segment list at current privilege level */
-PTBISEG __TBISegList( void );
-
-/* Search the segment list for a match given Id, pStart can be NULL */
-PTBISEG __TBIFindSeg( PTBISEG pStart, int Id );
-
-/* Prepare a new segment structure using space from within another */
-PTBISEG __TBINewSeg( PTBISEG pFromSeg, int Id, unsigned int Bytes );
-
-/* Prepare a new segment using any global or local heap segments available */
-PTBISEG __TBIMakeNewSeg( int Id, unsigned int Bytes );
-
-/* Insert a new segment into the segment list so __TBIFindSeg can locate it */
-void __TBIAddSeg( PTBISEG pSeg );
-#define __TBIADDSEG_DEF /* Some versions failed to define this */
-
-/* Return Id of current thread; TBID_ISTAT_BIT+TBID_THREAD_BITS */
-int __TBIThreadId( void );
-
-/* Return TBIRES.Thrd data for current thread */
-TBIRES __TBIThrdPrivId( void );
-
-/* Return pointer to current threads TBI root block.
- Id implies whether Int or Background root block is required */
-PTBI __TBI( int Id );
-
-/* Try to set Mask bit using the spin-lock protocol, return 0 if fails and
- new state if succeeds */
-int __TBIPoll( PTBISPIN pLock, int Mask );
-
-/* Set Mask bits via the spin-lock protocol in *pLock, return new state */
-int __TBISpin( PTBISPIN pLock, int Mask );
-
-/* Default handler set up for all TBI.fnSigs entries during initialisation */
-TBIRES __TBIUnExpXXX( TBIRES State, int SigNum,
- int Triggers, int Inst, PTBI pTBI );
-
-/* Call this routine to service triggers at background processing level. The
- TBID_POLL_BIT of the Id parameter value will be used to indicate that the
- routine should return if no triggers need to be serviced initially. If this
- bit is not set the routine will block until one trigger handler is serviced
- and then behave like the poll case servicing any remaining triggers
- actually outstanding before returning. Normally the State parameter should
- be simply initialised to zero and the result should be ignored, other
- values/options are for internal use only. */
-TBIRES __TBISyncTrigger( TBIRES State, int Id );
-
-/* Call this routine to enable processing of triggers by signal handlers at
- interrupt level. The State parameter value passed is returned by this
- routine. The State.Sig.TrigMask field also specifies the initial
- state of the interrupt mask register TXMASKI to be setup by the call.
- The other parts of the State parameter are ignored unless the PRIV bit is
- set in the SaveMask field. In this case the State.Sig.pCtx field specifies
- the base of the stack to which the interrupt system should switch into
- as it saves the state of the previously executing code. In the case the
- thread will be unprivileged as it continues execution at the return
- point of this routine and it's future state will be effectively never
- trusted to be valid. */
-TBIRES __TBIASyncTrigger( TBIRES State );
-
-/* Call this to swap soft threads executing at the background processing level.
- The TBIRES returned to the new thread will be the same as the NextThread
- value specified to the call. The NextThread.Switch.pCtx value specifies
- which thread context to restore and the NextThread.Switch.Para value can
- hold an arbitrary expression to be passed between the threads. The saved
- state of the previous thread will be stored in a TBICTX descriptor created
- on it's stack and the address of this will be stored into the *rpSaveCtx
- location specified. */
-TBIRES __TBISwitch( TBIRES NextThread, PTBICTX *rpSaveCtx );
-
-/* Call this to initialise a stack frame ready for further use, up to four
- 32-bit arguments may be specified after the fixed args to be passed via
- the new stack pStack to the routine specified via fnMain. If the
- main-line routine ever returns the thread will operate as if main itself
- had returned and terminate with the return code given. */
-typedef int (*PTBIMAINFN)( TBIRES Arg /*, <= 4 additional 32-bit args */ );
-PTBICTX __TBISwitchInit( void *pStack, PTBIMAINFN fnMain, ... );
-
-/* Call this to resume a thread from a saved synchronous TBICTX state.
- The TBIRES returned to the new thread will be the same as the NextThread
- value specified to the call. The NextThread.Switch.pCtx value specifies
- which thread context to restore and the NextThread.Switch.Para value can
- hold an arbitrary expression to be passed between the threads. The context
- of the calling thread is lost and this routine never returns to the
- caller. The TrigsMask value supplied is ored into TXMASKI to enable
- interrupts after the context of the new thread is established. */
-void __TBISyncResume( TBIRES NextThread, int TrigsMask );
-
-/* Call these routines to save and restore the extended states of
- scheduled tasks. */
-void *__TBICtxSave( TBIRES State, void *pExt );
-void *__TBICtxRestore( TBIRES State, void *pExt );
-
-#ifdef TBI_1_4
-#ifdef TBI_FASTINT_1_4
-/* Call these routines to copy the GP state to a separate buffer
- * Only necessary for context switching.
- */
-PTBICTXGP __TBICtx2SaveCrit( PTBICTX2 pCurrentCtx, PTBICTX2 pSaveCtx );
-void *__TBICtx2SaveGP( PTBICTXGP pCurrentCtxGP, PTBICTXGP pSaveCtxGP );
-
-/* Call these routines to save and restore the extended states of
- scheduled tasks. */
-void *__TBICtx2Save( PTBICTXGP pCtxGP, short SaveMask, void *pExt );
-void *__TBICtx2Restore( PTBICTX2 pCtx, short SaveMask, void *pExt );
-#endif
-
-/* If FPAC flag is set then significant FPU context exists. Call these routine
- to save and restore it */
-void *__TBICtxFPUSave( TBIRES State, void *pExt );
-void *__TBICtxFPURestore( TBIRES State, void *pExt );
-
-#ifdef TBI_FASTINT_1_4
-extern void *__TBICtx2FPUSave (PTBICTXGP, short, void*);
-extern void *__TBICtx2FPURestore (PTBICTXGP, short, void*);
-#endif
-#endif
-
-#ifdef TBI_1_4
-/* Call these routines to save and restore DSPRAM. */
-void *__TBIDspramSaveA (short DspramSizes, void *pExt);
-void *__TBIDspramSaveB (short DspramSizes, void *pExt);
-void *__TBIDspramRestoreA (short DspramSizes, void *pExt);
-void *__TBIDspramRestoreB (short DspramSizes, void *pExt);
-#endif
-
-/* This routine should be used at the entrypoint of interrupt handlers to
- re-enable higher priority interrupts and/or save state from the previously
- executing background code. State is a TBIRES.Sig parameter with NoNestMask
- indicating the triggers (if any) that should remain disabled and SaveMask
- CBUF bit indicating the if the hardware catch buffer is dirty. Optionally
- any number of extended state bits X??? including XCBF can be specified to
- force a nested state save call to __TBICtxSave before the current routine
- continues. (In the latter case __TBICtxRestore should be called to restore
- any extended states before the background thread of execution is resumed)
-
- By default (no X??? bits specified in SaveMask) this routine performs a
- sub-call to __TBICtxSave with the pExt and State parameters specified IF
- some triggers could be serviced while the current interrupt handler
- executes and the hardware catch buffer is actually dirty. In this case
- this routine provides the XCBF bit in State.Sig.SaveMask to force the
- __TBICtxSave to extract the current catch state.
-
- The NoNestMask parameter should normally indicate that the same or lower
- triggers than those provoking the current handler call should not be
- serviced in nested calls, zero may be specified if all possible interrupts
- are to be allowed.
-
- The TBIRES.Sig value returned will be similar to the State parameter
- specified with the XCBF bit ORed into it's SaveMask if a context save was
- required and fewer bits set in it's TrigMask corresponding to the same/lower
- priority interrupt triggers still not enabled. */
-TBIRES __TBINestInts( TBIRES State, void *pExt, int NoNestMask );
-
-/* This routine causes the TBICTX structure specified in State.Sig.pCtx to
- be restored. This implies that execution will not return to the caller.
- The State.Sig.TrigMask field will be restored during the context switch
- such that any immediately occurring interrupts occur in the context of the
- newly specified task. The State.Sig.SaveMask parameter is ignored. */
-void __TBIASyncResume( TBIRES State );
-
-/* Call this routine to enable fastest possible processing of one or more
- interrupt triggers via a unified signal handler. The handler concerned
- must simple return after servicing the related hardware.
- The State.Sig.TrigMask parameter indicates the interrupt triggers to be
- enabled and the Thin.Thin.fnHandler specifies the routine to call and
- the whole Thin parameter value will be passed to this routine unaltered as
- it's first parameter. */
-void __TBIASyncThin( TBIRES State, TBIRES Thin );
-
-/* Do this before performing your own direct spin-lock access - use TBI_LOCK */
-int __TBILock( void );
-
-/* Do this after performing your own direct spin-lock access - use TBI_UNLOCK */
-void __TBIUnlock( int TrigState );
-
-/* Obtain and release global critical section lock - only stops execution
- of interrupts on this thread and similar critical section code on other
- local threads - use TBI_CRITON or TBI_CRITOFF */
-int __TBICritOn( void );
-void __TBICritOff( int TrigState );
-
-/* Change INTS (TXMASKI) - return old state - use TBI_INTSX */
-int __TBIIntsX( int NewMask );
-
-/* Change TRIGS (TXMASK) - return old state - use TBI_TRIGSX */
-int __TBITrigsX( int NewMask );
-
-/* This function initialises a timer for first use, only the TBID_ISTAT_BIT
- of the Id parameter is used to indicate which timer is to be modified. The
- Wait value should either be zero to disable the timer concerned or be in
- the recommended TBI_TIMERWAIT_* range to specify the delay required before
- the first timer trigger occurs.
-
- The TBID_ISTAT_BIT of the Id parameter similar effects all other timer
- support functions (see below). */
-void __TBITimerCtrl( int Id, int Wait );
-
-/* This routine returns a 64-bit time stamp value that is initialised to zero
- via a __TBITimerCtrl timer enabling call. */
-long long __TBITimeStamp( int Id );
-
-/* To manage a periodic timer each period elapsed should be subracted from
- the current timer value to attempt to set up the next timer trigger. The
- Wait parameter should be a value in the recommended TBI_TIMERWAIT_* range.
- The return value is the new aggregate value that the timer was updated to,
- if this is less than zero then a timer trigger is guaranteed to be
- generated after the number of ticks implied, if a positive result is
- returned either itterative or step-wise corrective action must be taken to
- resynchronise the timer and hence provoke a future timer trigger. */
-int __TBITimerAdd( int Id, int Wait );
-
-/* String table search function, pStart is first entry to check or NULL,
- pStr is string data to search for and MatchLen is either length of string
- to compare for an exact match or negative length to compare for partial
- match. */
-const TBISTR *__TBIFindStr( const TBISTR *pStart,
- const char *pStr, int MatchLen );
-
-/* String table translate function, pStr is text to translate and Len is
- it's length. Value returned may not be a string pointer if the
- translation value is really some other type, 64-bit alignment of the return
- pointer is guaranteed so almost any type including a structure could be
- located with this routine. */
-const void *__TBITransStr( const char *pStr, int Len );
-
-
-
-/* Arbitrary physical memory access windows, use different Channels to avoid
- conflict/thrashing within a single piece of code. */
-void *__TBIPhysAccess( int Channel, int PhysAddr, int Bytes );
-void __TBIPhysRelease( int Channel, void *pLinAddr );
-
-#ifdef METAC_1_0
-/* Data cache function nullified because data cache is off */
-#define TBIDCACHE_FLUSH( pAddr )
-#define TBIDCACHE_PRELOAD( Type, pAddr ) ((Type) (pAddr))
-#define TBIDCACHE_REFRESH( Type, pAddr ) ((Type) (pAddr))
-#endif
-#ifdef METAC_1_1
-/* To flush a single cache line from the data cache using a linear address */
-#define TBIDCACHE_FLUSH( pAddr ) ((volatile char *) \
- (((unsigned int) (pAddr))>>LINSYSLFLUSH_S))[0] = 0
-
-extern void * __builtin_dcache_preload (void *);
-
-/* Try to ensure that the data at the address concerned is in the cache */
-#define TBIDCACHE_PRELOAD( Type, Addr ) \
- ((Type) __builtin_dcache_preload ((void *)(Addr)))
-
-extern void * __builtin_dcache_refresh (void *);
-
-/* Flush any old version of data from address and re-load a new copy */
-#define TBIDCACHE_REFRESH( Type, Addr ) __extension__ ({ \
- Type __addr = (Type)(Addr); \
- (void)__builtin_dcache_refresh ((void *)(((unsigned int)(__addr))>>6)); \
- __addr; })
-
-#endif
-#ifndef METAC_1_0
-#ifndef METAC_1_1
-/* Support for DCACHE builtin */
-extern void __builtin_dcache_flush (void *);
-
-/* To flush a single cache line from the data cache using a linear address */
-#define TBIDCACHE_FLUSH( Addr ) \
- __builtin_dcache_flush ((void *)(Addr))
-
-extern void * __builtin_dcache_preload (void *);
-
-/* Try to ensure that the data at the address concerned is in the cache */
-#define TBIDCACHE_PRELOAD( Type, Addr ) \
- ((Type) __builtin_dcache_preload ((void *)(Addr)))
-
-extern void * __builtin_dcache_refresh (void *);
-
-/* Flush any old version of data from address and re-load a new copy */
-#define TBIDCACHE_REFRESH( Type, Addr ) \
- ((Type) __builtin_dcache_refresh ((void *)(Addr)))
-
-#endif
-#endif
-
-/* Flush the MMCU cache */
-#define TBIMCACHE_FLUSH() { ((volatile int *) LINSYSCFLUSH_MMCU)[0] = 0; }
-
-#ifdef METAC_2_1
-/* Obtain the MMU table entry for the specified address */
-#define TBIMTABLE_LEAFDATA(ADDR) TBIXCACHE_RD((int)(ADDR) & (-1<<6))
-
-#ifndef __ASSEMBLY__
-/* Obtain the full MMU table entry for the specified address */
-#define TBIMTABLE_DATA(ADDR) __extension__ ({ TBIRES __p; \
- __p.Val = TBIXCACHE_RL((int)(ADDR) & (-1<<6)); \
- __p; })
-#endif
-#endif
-
-/* Combine a physical base address, and a linear address
- * Internal use only
- */
-#define _TBIMTABLE_LIN2PHYS(PHYS, LIN, LMASK) (void*)(((int)(PHYS)&0xFFFFF000)\
- +((int)(LIN)&(LMASK)))
-
-/* Convert a linear to a physical address */
-#define TBIMTABLE_LIN2PHYS(LEAFDATA, ADDR) \
- (((LEAFDATA) & CRLINPHY0_VAL_BIT) \
- ? _TBIMTABLE_LIN2PHYS(LEAFDATA, ADDR, 0x00000FFF) \
- : 0)
-
-/* Debug support - using external debugger or host */
-void __TBIDumpSegListEntries( void );
-void __TBILogF( const char *pFmt, ... );
-void __TBIAssert( const char *pFile, int LineNum, const char *pExp );
-void __TBICont( const char *pMsg, ... ); /* TBIAssert -> 'wait for continue' */
-
-/* Array of signal name data for debug messages */
-extern const char __TBISigNames[];
-#endif /* ifndef __ASSEMBLY__ */
-
-
-
-/* Scale of sub-strings in the __TBISigNames string list */
-#define TBI_SIGNAME_SCALE 4
-#define TBI_SIGNAME_SCALE_S 2
-
-#define TBI_1_3
-
-#ifdef TBI_1_3
-
-#ifndef __ASSEMBLY__
-#define TBIXCACHE_RD(ADDR) __extension__ ({\
- void * __Addr = (void *)(ADDR); \
- int __Data; \
- __asm__ volatile ( "CACHERD\t%0,[%1+#0]" : \
- "=r" (__Data) : "r" (__Addr) ); \
- __Data; })
-
-#define TBIXCACHE_RL(ADDR) __extension__ ({\
- void * __Addr = (void *)(ADDR); \
- long long __Data; \
- __asm__ volatile ( "CACHERL\t%0,%t0,[%1+#0]" : \
- "=d" (__Data) : "r" (__Addr) ); \
- __Data; })
-
-#define TBIXCACHE_WD(ADDR, DATA) do {\
- void * __Addr = (void *)(ADDR); \
- int __Data = DATA; \
- __asm__ volatile ( "CACHEWD\t[%0+#0],%1" : \
- : "r" (__Addr), "r" (__Data) ); } while(0)
-
-#define TBIXCACHE_WL(ADDR, DATA) do {\
- void * __Addr = (void *)(ADDR); \
- long long __Data = DATA; \
- __asm__ volatile ( "CACHEWL\t[%0+#0],%1,%t1" : \
- : "r" (__Addr), "r" (__Data) ); } while(0)
-
-#ifdef TBI_4_0
-
-#define TBICACHE_FLUSH_L1D_L2(ADDR) \
- TBIXCACHE_WD(ADDR, CACHEW_FLUSH_L1D_L2)
-#define TBICACHE_WRITEBACK_L1D_L2(ADDR) \
- TBIXCACHE_WD(ADDR, CACHEW_WRITEBACK_L1D_L2)
-#define TBICACHE_INVALIDATE_L1D(ADDR) \
- TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1D)
-#define TBICACHE_INVALIDATE_L1D_L2(ADDR) \
- TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1D_L2)
-#define TBICACHE_INVALIDATE_L1DTLB(ADDR) \
- TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1DTLB)
-#define TBICACHE_INVALIDATE_L1I(ADDR) \
- TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1I)
-#define TBICACHE_INVALIDATE_L1ITLB(ADDR) \
- TBIXCACHE_WD(ADDR, CACHEW_INVALIDATE_L1ITLB)
-
-#endif /* TBI_4_0 */
-#endif /* ifndef __ASSEMBLY__ */
-
-/*
- * Calculate linear PC value from real PC and Minim mode control, the LSB of
- * the result returned indicates if address compression has occurred.
- */
-#ifndef __ASSEMBLY__
-#define METAG_LINPC( PCVal ) (\
- ( (TBI_GETREG(TXPRIVEXT) & TXPRIVEXT_MINIMON_BIT) != 0 ) ? ( \
- ( ((PCVal) & 0x00900000) == 0x00900000 ) ? \
- (((PCVal) & 0xFFE00000) + (((PCVal) & 0x001FFFFC)>>1) + 1) : \
- ( ((PCVal) & 0x00800000) == 0x00000000 ) ? \
- (((PCVal) & 0xFF800000) + (((PCVal) & 0x007FFFFC)>>1) + 1) : \
- (PCVal) ) \
- : (PCVal) )
-#define METAG_LINPC_X2BIT 0x00000001 /* Make (Size>>1) if compressed */
-
-/* Convert an arbitrary Linear address into a valid Minim PC or return 0 */
-#define METAG_PCMINIM( LinVal ) (\
- (((LinVal) & 0x00980000) == 0x00880000) ? \
- (((LinVal) & 0xFFE00000) + (((LinVal) & 0x000FFFFE)<<1)) : \
- (((LinVal) & 0x00C00000) == 0x00000000) ? \
- (((LinVal) & 0xFF800000) + (((LinVal) & 0x003FFFFE)<<1)) : 0 )
-
-/* Reverse a METAG_LINPC conversion step to return the original PCVal */
-#define METAG_PCLIN( LinVal ) ( 0xFFFFFFFC & (\
- ( (LinVal & METAG_LINPC_X2BIT) != 0 ) ? METAG_PCMINIM( LinVal ) : \
- (LinVal) ))
-
-/*
- * Flush the MMCU Table cache privately for each thread. On cores that do not
- * support per-thread flushing it will flush all threads mapping data.
- */
-#define TBIMCACHE_TFLUSH(Thread) do {\
- ((volatile int *)( LINSYSCFLUSH_TxMMCU_BASE + \
- (LINSYSCFLUSH_TxMMCU_STRIDE*(Thread)) ))[0] = 0; \
- } while(0)
-
-/*
- * To flush a single linear-matched cache line from the code cache. In
- * cases where Minim is possible the METAC_LINPC operation must be used
- * to pre-process the address being flushed.
- */
-#define TBIICACHE_FLUSH( pAddr ) TBIXCACHE_WD (pAddr, CACHEW_ICACHE_BIT)
-
-/* To flush a single linear-matched mapping from code/data MMU table cache */
-#define TBIMCACHE_AFLUSH( pAddr, SegType ) \
- TBIXCACHE_WD(pAddr, CACHEW_TLBFLUSH_BIT + ( \
- ((SegType) == TBID_SEGTYPE_TEXT) ? CACHEW_ICACHE_BIT : 0 ))
-
-/*
- * To flush translation data corresponding to a range of addresses without
- * using TBITCACHE_FLUSH to flush all of this threads translation data. It
- * is necessary to know what stride (>= 4K) must be used to flush a specific
- * region.
- *
- * For example direct mapped regions use the maximum page size (512K) which may
- * mean that only one flush is needed to cover the sub-set of the direct
- * mapped area used since it was setup.
- *
- * The function returns the stride on which flushes should be performed.
- *
- * If 0 is returned then the region is not subject to MMU caching, if -1 is
- * returned then this indicates that only TBIMCACHE_TFLUSH can be used to
- * flush the region concerned rather than TBIMCACHE_AFLUSH which this
- * function is designed to support.
- */
-int __TBIMMUCacheStride( const void *pStart, int Bytes );
-
-/*
- * This function will use the above lower level functions to achieve a MMU
- * table data flush in an optimal a fashion as possible. On a system that
- * supports linear address based caching this function will also call the
- * code or data cache flush functions to maintain address/data coherency.
- *
- * SegType should be TBID_SEGTYPE_TEXT if the address range is for code or
- * any other value such as TBID_SEGTYPE_DATA for data. If an area is
- * used in both ways then call this function twice; once for each.
- */
-void __TBIMMUCacheFlush( const void *pStart, int Bytes, int SegType );
-
-/*
- * Cached Core mode setup and flush functions allow one code and one data
- * region of the corresponding global or local cache partion size to be
- * locked into the corresponding cache memory. This prevents normal LRU
- * logic discarding the code or data and avoids write-thru bandwidth in
- * data areas. Code mappings are selected by specifying TBID_SEGTYPE_TEXT
- * for SegType, otherwise data mappings are created.
- *
- * Mode supplied should always contain the VALID bit and WINx selection data.
- * Data areas will be mapped read-only if the WRITE bit is not added.
- *
- * The address returned by the Opt function will either be the same as that
- * passed in (if optimisation cannot be supported) or the base of the new core
- * cached region in linear address space. The returned address must be passed
- * into the End function to remove the mapping when required. If a non-core
- * cached memory address is passed into it the End function has no effect.
- * Note that the region accessed MUST be flushed from the appropriate cache
- * before the End function is called to deliver correct operation.
- */
-void *__TBICoreCacheOpt( const void *pStart, int Bytes, int SegType, int Mode );
-void __TBICoreCacheEnd( const void *pOpt, int Bytes, int SegType );
-
-/*
- * Optimise physical access channel and flush side effects before releasing
- * the channel. If pStart is NULL the whole region must be flushed and this is
- * done automatically by the channel release function if optimisation is
- * enabled. Flushing the specific region that may have been accessed before
- * release should optimises this process. On physically cached systems we do
- * not flush the code/data caches only the MMU table data needs flushing.
- */
-void __TBIPhysOptim( int Channel, int IMode, int DMode );
-void __TBIPhysFlush( int Channel, const void *pStart, int Bytes );
-#endif
-#endif /* ifdef TBI_1_3 */
-
-#endif /* _ASM_METAG_TBX_H_ */
diff --git a/arch/metag/include/asm/tcm.h b/arch/metag/include/asm/tcm.h
deleted file mode 100644
index a0a4997e4b8a..000000000000
--- a/arch/metag/include/asm/tcm.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_TCM_H__
-#define __ASM_TCM_H__
-
-#include <linux/ioport.h>
-#include <linux/list.h>
-
-struct tcm_allocation {
- struct list_head list;
- unsigned int tag;
- unsigned long addr;
- unsigned long size;
-};
-
-/*
- * TCM memory region descriptor.
- */
-struct tcm_region {
- unsigned int tag;
- struct resource res;
-};
-
-#define TCM_INVALID_TAG 0xffffffff
-
-unsigned long tcm_alloc(unsigned int tag, size_t len);
-void tcm_free(unsigned int tag, unsigned long addr, size_t len);
-unsigned int tcm_lookup_tag(unsigned long p);
-
-int tcm_add_region(struct tcm_region *reg);
-
-#endif
diff --git a/arch/metag/include/asm/thread_info.h b/arch/metag/include/asm/thread_info.h
deleted file mode 100644
index a1a9c7f5ca8c..000000000000
--- a/arch/metag/include/asm/thread_info.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* thread_info.h: Meta low-level thread information
- *
- * Copyright (C) 2002 David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- *
- * Meta port by Imagination Technologies
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <linux/compiler.h>
-#include <asm/page.h>
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#endif
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants must
- * also be changed
- */
-#ifndef __ASSEMBLY__
-
-/* This must be 8 byte aligned so we can ensure stack alignment. */
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- unsigned long status; /* thread-synchronous flags */
- u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable, <0 => BUG */
-
- mm_segment_t addr_limit; /* thread address space */
-
- u8 supervisor_stack[0] __aligned(8);
-};
-
-#else /* !__ASSEMBLY__ */
-
-#include <generated/asm-offsets.h>
-
-#endif
-
-#ifdef CONFIG_4KSTACKS
-#define THREAD_SHIFT 12
-#else
-#define THREAD_SHIFT 13
-#endif
-
-#if THREAD_SHIFT >= PAGE_SHIFT
-#define THREAD_SIZE_ORDER (THREAD_SHIFT - PAGE_SHIFT)
-#else
-#define THREAD_SIZE_ORDER 0
-#endif
-
-#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
-
-#define STACK_WARN (THREAD_SIZE/8)
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-/* how to get the current stack pointer from C */
-register unsigned long current_stack_pointer asm("A0StP") __used;
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
- return (struct thread_info *)(current_stack_pointer &
- ~(THREAD_SIZE - 1));
-}
-
-#define __HAVE_ARCH_KSTACK_END
-static inline int kstack_end(void *addr)
-{
- return addr == (void *) (((unsigned long) addr & ~(THREAD_SIZE - 1))
- + sizeof(struct thread_info));
-}
-
-#endif
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to
- * access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_SINGLESTEP 3 /* restore singlestep on return to user
- mode */
-#define TIF_SYSCALL_AUDIT 4 /* syscall auditing active */
-#define TIF_SECCOMP 5 /* secure computing */
-#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */
-#define TIF_NOTIFY_RESUME 7 /* callback before returning to user */
-#define TIF_MEMDIE 8 /* is terminating due to OOM killer */
-#define TIF_SYSCALL_TRACEPOINT 9 /* syscall tracepoint instrumentation */
-
-
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_SECCOMP (1<<TIF_SECCOMP)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
-#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
-
-/* work to do in syscall trace */
-#define _TIF_WORK_SYSCALL_MASK (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP | \
- _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
- _TIF_SYSCALL_TRACEPOINT)
-
-/* work to do on any return to u-space */
-#define _TIF_ALLWORK_MASK (_TIF_SYSCALL_TRACE | _TIF_SIGPENDING | \
- _TIF_NEED_RESCHED | _TIF_SYSCALL_AUDIT | \
- _TIF_SINGLESTEP | _TIF_RESTORE_SIGMASK | \
- _TIF_NOTIFY_RESUME)
-
-/* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK (_TIF_ALLWORK_MASK & ~(_TIF_SYSCALL_TRACE | \
- _TIF_SYSCALL_AUDIT | _TIF_SINGLESTEP))
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/metag/include/asm/tlb.h b/arch/metag/include/asm/tlb.h
deleted file mode 100644
index fbe6ee91e8e7..000000000000
--- a/arch/metag/include/asm/tlb.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_TLB_H
-#define __ASM_METAG_TLB_H
-
-#include <asm/cacheflush.h>
-#include <asm/page.h>
-
-/* Note, read http://lkml.org/lkml/2004/1/15/6 */
-
-#ifdef CONFIG_METAG_META12
-
-#define tlb_start_vma(tlb, vma) \
- do { \
- if (!tlb->fullmm) \
- flush_cache_range(vma, vma->vm_start, vma->vm_end); \
- } while (0)
-
-#define tlb_end_vma(tlb, vma) \
- do { \
- if (!tlb->fullmm) \
- flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
- } while (0)
-
-
-#else
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-
-#endif
-
-#define __tlb_remove_tlb_entry(tlb, pte, addr) do { } while (0)
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif
diff --git a/arch/metag/include/asm/tlbflush.h b/arch/metag/include/asm/tlbflush.h
deleted file mode 100644
index f3e5d99a3891..000000000000
--- a/arch/metag/include/asm/tlbflush.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_METAG_TLBFLUSH_H
-#define __ASM_METAG_TLBFLUSH_H
-
-#include <linux/io.h>
-#include <linux/sched.h>
-#include <asm/metag_mem.h>
-#include <asm/pgalloc.h>
-
-/*
- * TLB flushing:
- *
- * - flush_tlb() flushes the current mm struct TLBs
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(mm, start, end) flushes a range of pages
- * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
- *
- * FIXME: Meta 2 can flush single TLB entries.
- *
- */
-
-#if defined(CONFIG_METAG_META21) && !defined(CONFIG_SMP)
-static inline void __flush_tlb(void)
-{
- /* flush TLB entries for just the current hardware thread */
- int thread = hard_processor_id();
- metag_out32(0, (LINSYSCFLUSH_TxMMCU_BASE +
- LINSYSCFLUSH_TxMMCU_STRIDE * thread));
-}
-#else
-static inline void __flush_tlb(void)
-{
- /* flush TLB entries for all hardware threads */
- metag_out32(0, LINSYSCFLUSH_MMCU);
-}
-#endif /* defined(CONFIG_METAG_META21) && !defined(CONFIG_SMP) */
-
-#define flush_tlb() __flush_tlb()
-
-#define flush_tlb_all() __flush_tlb()
-
-#define local_flush_tlb_all() __flush_tlb()
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
- if (mm == current->active_mm)
- __flush_tlb();
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma,
- unsigned long addr)
-{
- flush_tlb_mm(vma->vm_mm);
-}
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
-{
- flush_tlb_mm(vma->vm_mm);
-}
-
-static inline void flush_tlb_pgtables(struct mm_struct *mm,
- unsigned long start, unsigned long end)
-{
- flush_tlb_mm(mm);
-}
-
-static inline void flush_tlb_kernel_range(unsigned long start,
- unsigned long end)
-{
- flush_tlb_all();
-}
-
-#endif /* __ASM_METAG_TLBFLUSH_H */
-
diff --git a/arch/metag/include/asm/topology.h b/arch/metag/include/asm/topology.h
deleted file mode 100644
index df0d9e6b7f12..000000000000
--- a/arch/metag/include/asm/topology.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_METAG_TOPOLOGY_H
-#define _ASM_METAG_TOPOLOGY_H
-
-#ifdef CONFIG_NUMA
-
-#define cpu_to_node(cpu) ((void)(cpu), 0)
-
-#define cpumask_of_node(node) ((void)node, cpu_online_mask)
-
-#define pcibus_to_node(bus) ((void)(bus), -1)
-#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \
- cpu_all_mask : \
- cpumask_of_node(pcibus_to_node(bus)))
-
-#endif
-
-#define mc_capable() (1)
-
-const struct cpumask *cpu_coregroup_mask(unsigned int cpu);
-
-extern cpumask_t cpu_core_map[NR_CPUS];
-
-#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_METAG_TOPOLOGY_H */
diff --git a/arch/metag/include/asm/traps.h b/arch/metag/include/asm/traps.h
deleted file mode 100644
index ac808740bd84..000000000000
--- a/arch/metag/include/asm/traps.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2005,2008 Imagination Technologies
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _METAG_TBIVECTORS_H
-#define _METAG_TBIVECTORS_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/tbx.h>
-
-typedef TBIRES (*kick_irq_func_t)(TBIRES, int, int, int, PTBI, int *);
-
-extern TBIRES kick_handler(TBIRES, int, int, int, PTBI);
-struct kick_irq_handler {
- struct list_head list;
- kick_irq_func_t func;
-};
-
-extern void kick_register_func(struct kick_irq_handler *);
-extern void kick_unregister_func(struct kick_irq_handler *);
-
-extern void head_end(TBIRES, unsigned long);
-extern void restart_critical_section(TBIRES State);
-extern TBIRES tail_end_sys(TBIRES, int, int *);
-static inline TBIRES tail_end(TBIRES state)
-{
- return tail_end_sys(state, -1, NULL);
-}
-
-DECLARE_PER_CPU(PTBI, pTBI);
-extern PTBI pTBI_get(unsigned int);
-
-extern int ret_from_fork(TBIRES arg);
-
-extern int do_page_fault(struct pt_regs *regs, unsigned long address,
- unsigned int write_access, unsigned int trapno);
-
-extern TBIRES __TBIUnExpXXX(TBIRES State, int SigNum, int Triggers, int Inst,
- PTBI pTBI);
-
-#endif
-
-#endif /* _METAG_TBIVECTORS_H */
diff --git a/arch/metag/include/asm/uaccess.h b/arch/metag/include/asm/uaccess.h
deleted file mode 100644
index a5311eb36e32..000000000000
--- a/arch/metag/include/asm/uaccess.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __METAG_UACCESS_H
-#define __METAG_UACCESS_H
-
-/*
- * User space memory access functions
- */
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF)
-#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-static inline int __access_ok(unsigned long addr, unsigned long size)
-{
- /*
- * Allow access to the user mapped memory area, but not the system area
- * before it. The check extends to the top of the address space when
- * kernel access is allowed (there's no real reason to user copy to the
- * system area in any case).
- */
- if (likely(addr >= META_MEMORY_BASE && addr < get_fs().seg &&
- size <= get_fs().seg - addr))
- return true;
- /*
- * Explicitly allow NULL pointers here. Parts of the kernel such
- * as readv/writev use access_ok to validate pointers, but want
- * to allow NULL pointers for various reasons. NULL pointers are
- * safe to allow through because the first page is not mappable on
- * Meta.
- */
- if (!addr)
- return true;
- /* Allow access to core code memory area... */
- if (addr >= LINCORE_CODE_BASE && addr <= LINCORE_CODE_LIMIT &&
- size <= LINCORE_CODE_LIMIT + 1 - addr)
- return true;
- /* ... but no other areas. */
- return false;
-}
-
-#define access_ok(type, addr, size) __access_ok((unsigned long)(addr), \
- (unsigned long)(size))
-
-#include <asm/extable.h>
-
-/*
- * These are the main single-value transfer routines. They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x, ptr) \
- __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-#define __put_user(x, ptr) \
- __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
-
-extern void __put_user_bad(void);
-
-#define __put_user_nocheck(x, ptr, size) \
-({ \
- long __pu_err; \
- __put_user_size((x), (ptr), (size), __pu_err); \
- __pu_err; \
-})
-
-#define __put_user_check(x, ptr, size) \
-({ \
- long __pu_err = -EFAULT; \
- __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
- if (access_ok(VERIFY_WRITE, __pu_addr, size)) \
- __put_user_size((x), __pu_addr, (size), __pu_err); \
- __pu_err; \
-})
-
-extern long __put_user_asm_b(unsigned int x, void __user *addr);
-extern long __put_user_asm_w(unsigned int x, void __user *addr);
-extern long __put_user_asm_d(unsigned int x, void __user *addr);
-extern long __put_user_asm_l(unsigned long long x, void __user *addr);
-
-#define __put_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- switch (size) { \
- case 1: \
- retval = __put_user_asm_b((__force unsigned int)x, ptr);\
- break; \
- case 2: \
- retval = __put_user_asm_w((__force unsigned int)x, ptr);\
- break; \
- case 4: \
- retval = __put_user_asm_d((__force unsigned int)x, ptr);\
- break; \
- case 8: \
- retval = __put_user_asm_l((__force unsigned long long)x,\
- ptr); \
- break; \
- default: \
- __put_user_bad(); \
- } \
-} while (0)
-
-#define get_user(x, ptr) \
- __get_user_check((x), (ptr), sizeof(*(ptr)))
-#define __get_user(x, ptr) \
- __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-extern long __get_user_bad(void);
-
-#define __get_user_nocheck(x, ptr, size) \
-({ \
- long __gu_err; \
- long long __gu_val; \
- __get_user_size(__gu_val, (ptr), (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-#define __get_user_check(x, ptr, size) \
-({ \
- long __gu_err = -EFAULT; \
- long long __gu_val = 0; \
- const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
- if (access_ok(VERIFY_READ, __gu_addr, size)) \
- __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
- (x) = (__force __typeof__(*(ptr)))__gu_val; \
- __gu_err; \
-})
-
-extern unsigned char __get_user_asm_b(const void __user *addr, long *err);
-extern unsigned short __get_user_asm_w(const void __user *addr, long *err);
-extern unsigned int __get_user_asm_d(const void __user *addr, long *err);
-extern unsigned long long __get_user_asm_l(const void __user *addr, long *err);
-
-#define __get_user_size(x, ptr, size, retval) \
-do { \
- retval = 0; \
- switch (size) { \
- case 1: \
- x = __get_user_asm_b(ptr, &retval); break; \
- case 2: \
- x = __get_user_asm_w(ptr, &retval); break; \
- case 4: \
- x = __get_user_asm_d(ptr, &retval); break; \
- case 8: \
- x = __get_user_asm_l(ptr, &retval); break; \
- default: \
- (x) = __get_user_bad(); \
- } \
-} while (0)
-
-/*
- * Copy a null terminated string from userspace.
- *
- * Must return:
- * -EFAULT for an exception
- * count if we hit the buffer limit
- * bytes copied if we hit a null byte
- * (without the null byte)
- */
-
-extern long __must_check __strncpy_from_user(char *dst, const char __user *src,
- long count);
-
-static inline long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
- if (!access_ok(VERIFY_READ, src, 1))
- return -EFAULT;
- return __strncpy_from_user(dst, src, count);
-}
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-extern long __must_check strnlen_user(const char __user *src, long count);
-
-extern unsigned long raw_copy_from_user(void *to, const void __user *from,
- unsigned long n);
-extern unsigned long raw_copy_to_user(void __user *to, const void *from,
- unsigned long n);
-
-/*
- * Zero Userspace
- */
-
-extern unsigned long __must_check __do_clear_user(void __user *to,
- unsigned long n);
-
-static inline unsigned long clear_user(void __user *to, unsigned long n)
-{
- if (access_ok(VERIFY_WRITE, to, n))
- return __do_clear_user(to, n);
- return n;
-}
-
-#define __clear_user(to, n) __do_clear_user(to, n)
-
-#endif /* _METAG_UACCESS_H */
diff --git a/arch/metag/include/asm/unistd.h b/arch/metag/include/asm/unistd.h
deleted file mode 100644
index 32955a18fb32..000000000000
--- a/arch/metag/include/asm/unistd.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <uapi/asm/unistd.h>
-
-#define __ARCH_WANT_SYS_CLONE
diff --git a/arch/metag/include/asm/user_gateway.h b/arch/metag/include/asm/user_gateway.h
deleted file mode 100644
index cf2392b95a56..000000000000
--- a/arch/metag/include/asm/user_gateway.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2010 Imagination Technologies
- */
-
-#ifndef __ASM_METAG_USER_GATEWAY_H
-#define __ASM_METAG_USER_GATEWAY_H
-
-#include <asm/page.h>
-
-/* Page of kernel code accessible to userspace. */
-#define USER_GATEWAY_PAGE 0x6ffff000
-/* Offset of TLS pointer array in gateway page. */
-#define USER_GATEWAY_TLS 0x100
-
-#ifndef __ASSEMBLY__
-
-extern char __user_gateway_start;
-extern char __user_gateway_end;
-
-/* Kernel mapping of the gateway page. */
-extern void *gateway_page;
-
-static inline void set_gateway_tls(void __user *tls_ptr)
-{
- void **gateway_tls = (void **)(gateway_page + USER_GATEWAY_TLS +
- hard_processor_id() * 4);
-
- *gateway_tls = (__force void *)tls_ptr;
-#ifdef CONFIG_METAG_META12
- /* Avoid cache aliases on virtually tagged cache. */
- __builtin_dcache_flush((void *)USER_GATEWAY_PAGE + USER_GATEWAY_TLS +
- hard_processor_id() * sizeof(void *));
-#endif
-}
-
-extern int __kuser_get_tls(void);
-extern char *__kuser_get_tls_end[];
-
-extern int __kuser_cmpxchg(int, int, unsigned long *);
-extern char *__kuser_cmpxchg_end[];
-
-#endif
-
-#endif
diff --git a/arch/metag/include/uapi/asm/byteorder.h b/arch/metag/include/uapi/asm/byteorder.h
deleted file mode 100644
index e5e03ff7e20d..000000000000
--- a/arch/metag/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <linux/byteorder/little_endian.h>
diff --git a/arch/metag/include/uapi/asm/ech.h b/arch/metag/include/uapi/asm/ech.h
deleted file mode 100644
index 1e09f1ea4f7f..000000000000
--- a/arch/metag/include/uapi/asm/ech.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_METAG_ECH_H
-#define _UAPI_METAG_ECH_H
-
-/*
- * These bits can be set in the top half of the D0.8 register when DSP context
- * switching is enabled, in order to support partial DSP context save/restore.
- */
-
-#define TBICTX_XEXT_BIT 0x1000 /* Enable extended context save */
-#define TBICTX_XTDP_BIT 0x0800 /* DSP accumulators/RAM/templates */
-#define TBICTX_XHL2_BIT 0x0400 /* Hardware loops */
-#define TBICTX_XAXX_BIT 0x0200 /* Extended AX registers (A*.4-7) */
-#define TBICTX_XDX8_BIT 0x0100 /* Extended DX registers (D*.8-15) */
-
-#endif /* _UAPI_METAG_ECH_H */
diff --git a/arch/metag/include/uapi/asm/ptrace.h b/arch/metag/include/uapi/asm/ptrace.h
deleted file mode 100644
index 8ad9daa841c3..000000000000
--- a/arch/metag/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_METAG_PTRACE_H
-#define _UAPI_METAG_PTRACE_H
-
-#ifndef __ASSEMBLY__
-
-/*
- * These are the layouts of the regsets returned by the GETREGSET ptrace call
- */
-
-/* user_gp_regs::status */
-
-/* CBMarker bit (indicates catch state / catch replay) */
-#define USER_GP_REGS_STATUS_CATCH_BIT (1 << 22)
-#define USER_GP_REGS_STATUS_CATCH_S 22
-/* LSM_STEP field (load/store multiple step) */
-#define USER_GP_REGS_STATUS_LSM_STEP_BITS (0x7 << 8)
-#define USER_GP_REGS_STATUS_LSM_STEP_S 8
-/* SCC bit (indicates split 16x16 condition flags) */
-#define USER_GP_REGS_STATUS_SCC_BIT (1 << 4)
-#define USER_GP_REGS_STATUS_SCC_S 4
-
-/* normal condition flags */
-/* CF_Z bit (Zero flag) */
-#define USER_GP_REGS_STATUS_CF_Z_BIT (1 << 3)
-#define USER_GP_REGS_STATUS_CF_Z_S 3
-/* CF_N bit (Negative flag) */
-#define USER_GP_REGS_STATUS_CF_N_BIT (1 << 2)
-#define USER_GP_REGS_STATUS_CF_N_S 2
-/* CF_V bit (oVerflow flag) */
-#define USER_GP_REGS_STATUS_CF_V_BIT (1 << 1)
-#define USER_GP_REGS_STATUS_CF_V_S 1
-/* CF_C bit (Carry flag) */
-#define USER_GP_REGS_STATUS_CF_C_BIT (1 << 0)
-#define USER_GP_REGS_STATUS_CF_C_S 0
-
-/* split 16x16 condition flags */
-/* SCF_LZ bit (Low Zero flag) */
-#define USER_GP_REGS_STATUS_SCF_LZ_BIT (1 << 3)
-#define USER_GP_REGS_STATUS_SCF_LZ_S 3
-/* SCF_HZ bit (High Zero flag) */
-#define USER_GP_REGS_STATUS_SCF_HZ_BIT (1 << 2)
-#define USER_GP_REGS_STATUS_SCF_HZ_S 2
-/* SCF_HC bit (High Carry flag) */
-#define USER_GP_REGS_STATUS_SCF_HC_BIT (1 << 1)
-#define USER_GP_REGS_STATUS_SCF_HC_S 1
-/* SCF_LC bit (Low Carry flag) */
-#define USER_GP_REGS_STATUS_SCF_LC_BIT (1 << 0)
-#define USER_GP_REGS_STATUS_SCF_LC_S 0
-
-/**
- * struct user_gp_regs - User general purpose registers
- * @dx: GP data unit regs (dx[reg][unit] = D{unit:0-1}.{reg:0-7})
- * @ax: GP address unit regs (ax[reg][unit] = A{unit:0-1}.{reg:0-3})
- * @pc: PC register
- * @status: TXSTATUS register (condition flags, LSM_STEP etc)
- * @rpt: TXRPT registers (branch repeat counter)
- * @bpobits: TXBPOBITS register ("branch prediction other" bits)
- * @mode: TXMODE register
- * @_pad1: Reserved padding to make sizeof obviously 64bit aligned
- *
- * This is the user-visible general purpose register state structure.
- *
- * It can be accessed through PTRACE_GETREGSET with NT_PRSTATUS.
- *
- * It is also used in the signal context.
- */
-struct user_gp_regs {
- unsigned long dx[8][2];
- unsigned long ax[4][2];
- unsigned long pc;
- unsigned long status;
- unsigned long rpt;
- unsigned long bpobits;
- unsigned long mode;
- unsigned long _pad1;
-};
-
-/**
- * struct user_cb_regs - User catch buffer registers
- * @flags: TXCATCH0 register (fault flags)
- * @addr: TXCATCH1 register (fault address)
- * @data: TXCATCH2 and TXCATCH3 registers (low and high data word)
- *
- * This is the user-visible catch buffer register state structure containing
- * information about a failed memory access, and allowing the access to be
- * modified and replayed.
- *
- * It can be accessed through PTRACE_GETREGSET with NT_METAG_CBUF.
- */
-struct user_cb_regs {
- unsigned long flags;
- unsigned long addr;
- unsigned long long data;
-};
-
-/**
- * struct user_rp_state - User read pipeline state
- * @entries: Read pipeline entries
- * @mask: Mask of valid pipeline entries (RPMask from TXDIVTIME register)
- *
- * This is the user-visible read pipeline state structure containing the entries
- * currently in the read pipeline and the mask of valid entries.
- *
- * It can be accessed through PTRACE_GETREGSET with NT_METAG_RPIPE.
- */
-struct user_rp_state {
- unsigned long long entries[6];
- unsigned long mask;
-};
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _UAPI_METAG_PTRACE_H */
diff --git a/arch/metag/include/uapi/asm/sigcontext.h b/arch/metag/include/uapi/asm/sigcontext.h
deleted file mode 100644
index ac7e1f28d584..000000000000
--- a/arch/metag/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_METAG_SIGCONTEXT_H
-#define _ASM_METAG_SIGCONTEXT_H
-
-#include <asm/ptrace.h>
-
-/*
- * In a sigcontext structure we need to store the active state of the
- * user process so that it does not get trashed when we call the signal
- * handler. That not really the same as a user context that we are
- * going to store on syscall etc.
- */
-struct sigcontext {
- struct user_gp_regs regs; /* needs to be first */
-
- /*
- * Catch registers describing a memory fault.
- * If USER_GP_REGS_STATUS_CATCH_BIT is set in regs.status then catch
- * buffers have been saved and will be replayed on sigreturn.
- * Clear that bit to discard the catch state instead of replaying it.
- */
- struct user_cb_regs cb;
-
- /*
- * Read pipeline state. This will get restored on sigreturn.
- */
- struct user_rp_state rp;
-
- unsigned long oldmask;
-};
-
-#endif
diff --git a/arch/metag/include/uapi/asm/siginfo.h b/arch/metag/include/uapi/asm/siginfo.h
deleted file mode 100644
index 9a3f6cde9487..000000000000
--- a/arch/metag/include/uapi/asm/siginfo.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _METAG_SIGINFO_H
-#define _METAG_SIGINFO_H
-
-#define __ARCH_SI_TRAPNO
-
-#include <asm-generic/siginfo.h>
-
-/*
- * SIGFPE si_codes
- */
-#ifdef __KERNEL__
-#define FPE_FIXME 0 /* Broken dup of SI_USER */
-#endif /* __KERNEL__ */
-
-#endif
diff --git a/arch/metag/include/uapi/asm/swab.h b/arch/metag/include/uapi/asm/swab.h
deleted file mode 100644
index 30d696fcc237..000000000000
--- a/arch/metag/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef __ASM_METAG_SWAB_H
-#define __ASM_METAG_SWAB_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <asm-generic/swab.h>
-
-static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
-{
- return __builtin_metag_bswaps(x);
-}
-#define __arch_swab16 __arch_swab16
-
-static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
-{
- return __builtin_metag_bswap(x);
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
-{
- return __builtin_metag_bswapll(x);
-}
-#define __arch_swab64 __arch_swab64
-
-#endif /* __ASM_METAG_SWAB_H */
diff --git a/arch/metag/include/uapi/asm/unistd.h b/arch/metag/include/uapi/asm/unistd.h
deleted file mode 100644
index 9f72c4cfcfb5..000000000000
--- a/arch/metag/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/*
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#define __ARCH_WANT_RENAMEAT
-
-/* Use the standard ABI for syscalls. */
-#include <asm-generic/unistd.h>
-
-/* metag-specific syscalls. */
-#define __NR_metag_setglobalbit (__NR_arch_specific_syscall + 1)
-__SYSCALL(__NR_metag_setglobalbit, sys_metag_setglobalbit)
-#define __NR_metag_set_fpu_flags (__NR_arch_specific_syscall + 2)
-__SYSCALL(__NR_metag_set_fpu_flags, sys_metag_set_fpu_flags)
-#define __NR_metag_set_tls (__NR_arch_specific_syscall + 3)
-__SYSCALL(__NR_metag_set_tls, sys_metag_set_tls)
-#define __NR_metag_get_tls (__NR_arch_specific_syscall + 4)
-__SYSCALL(__NR_metag_get_tls, sys_metag_get_tls)
diff --git a/arch/metag/kernel/.gitignore b/arch/metag/kernel/.gitignore
deleted file mode 100644
index c5f676c3c224..000000000000
--- a/arch/metag/kernel/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-vmlinux.lds
diff --git a/arch/metag/kernel/Makefile b/arch/metag/kernel/Makefile
deleted file mode 100644
index 73441d8c0369..000000000000
--- a/arch/metag/kernel/Makefile
+++ /dev/null
@@ -1,40 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Linux/Meta kernel.
-#
-
-extra-y += head.o
-extra-y += vmlinux.lds
-
-obj-y += cachepart.o
-obj-y += clock.o
-obj-y += core_reg.o
-obj-y += devtree.o
-obj-y += dma.o
-obj-y += irq.o
-obj-y += kick.o
-obj-y += machines.o
-obj-y += process.o
-obj-y += ptrace.o
-obj-y += setup.o
-obj-y += signal.o
-obj-y += stacktrace.o
-obj-y += sys_metag.o
-obj-y += tbiunexp.o
-obj-y += time.o
-obj-y += topology.o
-obj-y += traps.o
-obj-y += user_gateway.o
-
-obj-$(CONFIG_PERF_EVENTS) += perf/
-
-obj-$(CONFIG_METAG_COREMEM) += coremem.o
-obj-$(CONFIG_METAG_DA) += da.o
-obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
-obj-$(CONFIG_FUNCTION_TRACER) += ftrace_stub.o
-obj-$(CONFIG_MODULES) += metag_ksyms.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_METAG_SUSPEND_MEM) += suspend.o
-obj-$(CONFIG_METAG_USER_TCM) += tcm.o
diff --git a/arch/metag/kernel/asm-offsets.c b/arch/metag/kernel/asm-offsets.c
deleted file mode 100644
index d9b348b99ff2..000000000000
--- a/arch/metag/kernel/asm-offsets.c
+++ /dev/null
@@ -1,15 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- */
-
-#include <linux/kbuild.h>
-#include <linux/thread_info.h>
-
-int main(void)
-{
- DEFINE(THREAD_INFO_SIZE, sizeof(struct thread_info));
- return 0;
-}
diff --git a/arch/metag/kernel/cachepart.c b/arch/metag/kernel/cachepart.c
deleted file mode 100644
index 6e0f8a80cc96..000000000000
--- a/arch/metag/kernel/cachepart.c
+++ /dev/null
@@ -1,132 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Meta cache partition manipulation.
- *
- * Copyright 2010 Imagination Technologies Ltd.
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <asm/processor.h>
-#include <asm/cachepart.h>
-#include <asm/metag_isa.h>
-#include <asm/metag_mem.h>
-
-#define SYSC_DCPART(n) (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
-#define SYSC_ICPART(n) (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
-
-#define CACHE_ASSOCIATIVITY 4 /* 4 way set-associative */
-#define ICACHE 0
-#define DCACHE 1
-
-/* The CORE_CONFIG2 register is not available on Meta 1 */
-#ifdef CONFIG_METAG_META21
-unsigned int get_dcache_size(void)
-{
- unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
- unsigned int sz = 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
- >> METAC_CORECFG2_DCSZ_S);
- if (config2 & METAC_CORECFG2_DCSMALL_BIT)
- sz >>= 6;
- return sz;
-}
-
-unsigned int get_icache_size(void)
-{
- unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
- unsigned int sz = 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
- >> METAC_CORE_C2ICSZ_S);
- if (config2 & METAC_CORECFG2_ICSMALL_BIT)
- sz >>= 6;
- return sz;
-}
-
-unsigned int get_global_dcache_size(void)
-{
- unsigned int cpart = metag_in32(SYSC_DCPART(hard_processor_id()));
- unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
- return (get_dcache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
-}
-
-unsigned int get_global_icache_size(void)
-{
- unsigned int cpart = metag_in32(SYSC_ICPART(hard_processor_id()));
- unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
- return (get_icache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
-}
-
-static int get_thread_cache_size(unsigned int cache, int thread_id)
-{
- unsigned int cache_size;
- unsigned int t_cache_part;
- unsigned int isEnabled;
- unsigned int offset = 0;
- isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 :
- metag_in32(MMCU_ICACHE_CTRL_ADDR) & 0x1);
- if (!isEnabled)
- return 0;
-#if PAGE_OFFSET >= LINGLOBAL_BASE
- /* Checking for global cache */
- cache_size = (cache == DCACHE ? get_global_dcache_size() :
- get_global_icache_size());
- offset = 8;
-#else
- cache_size = (cache == DCACHE ? get_dcache_size() :
- get_icache_size());
-#endif
- t_cache_part = (cache == DCACHE ?
- (metag_in32(SYSC_DCPART(thread_id)) >> offset) & 0xF :
- (metag_in32(SYSC_ICPART(thread_id)) >> offset) & 0xF);
- switch (t_cache_part) {
- case 0xF:
- return cache_size;
- case 0x7:
- return cache_size / 2;
- case 0x3:
- return cache_size / 4;
- case 0x1:
- return cache_size / 8;
- case 0:
- return cache_size / 16;
- }
- return -1;
-}
-
-void check_for_cache_aliasing(int thread_id)
-{
- int thread_cache_size;
- unsigned int cache_type;
- for (cache_type = ICACHE; cache_type <= DCACHE; cache_type++) {
- thread_cache_size =
- get_thread_cache_size(cache_type, thread_id);
- if (thread_cache_size < 0)
- pr_emerg("Can't read %s cache size\n",
- cache_type ? "DCACHE" : "ICACHE");
- else if (thread_cache_size == 0)
- /* Cache is off. No need to check for aliasing */
- continue;
- if (thread_cache_size / CACHE_ASSOCIATIVITY > PAGE_SIZE) {
- pr_emerg("Potential cache aliasing detected in %s on Thread %d\n",
- cache_type ? "DCACHE" : "ICACHE", thread_id);
- pr_warn("Total %s size: %u bytes\n",
- cache_type ? "DCACHE" : "ICACHE",
- cache_type ? get_dcache_size()
- : get_icache_size());
- pr_warn("Thread %s size: %d bytes\n",
- cache_type ? "CACHE" : "ICACHE",
- thread_cache_size);
- pr_warn("Page Size: %lu bytes\n", PAGE_SIZE);
- panic("Potential cache aliasing detected");
- }
- }
-}
-
-#else
-
-void check_for_cache_aliasing(int thread_id)
-{
- return;
-}
-
-#endif
diff --git a/arch/metag/kernel/clock.c b/arch/metag/kernel/clock.c
deleted file mode 100644
index 6339c9c6d0ab..000000000000
--- a/arch/metag/kernel/clock.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * arch/metag/kernel/clock.c
- *
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/of.h>
-
-#include <asm/param.h>
-#include <asm/clock.h>
-
-struct meta_clock_desc _meta_clock;
-
-/* Default machine get_core_freq callback. */
-static unsigned long get_core_freq_default(void)
-{
-#ifdef CONFIG_METAG_META21
- /*
- * Meta 2 cores divide down the core clock for the Meta timers, so we
- * can estimate the core clock from the divider.
- */
- return (metag_in32(EXPAND_TIMER_DIV) + 1) * 1000000;
-#else
- /*
- * On Meta 1 we don't know the core clock, but assuming the Meta timer
- * is correct it can be estimated based on loops_per_jiffy.
- */
- return (loops_per_jiffy * HZ * 5) >> 1;
-#endif
-}
-
-static struct clk *clk_core;
-
-/* Clk based get_core_freq callback. */
-static unsigned long get_core_freq_clk(void)
-{
- return clk_get_rate(clk_core);
-}
-
-/**
- * init_metag_core_clock() - Set up core clock from devicetree.
- *
- * Checks to see if a "core" clock is provided in the device tree, and overrides
- * the get_core_freq callback to use it.
- */
-static void __init init_metag_core_clock(void)
-{
- /*
- * See if a core clock is provided by the devicetree (and
- * registered by the init callback above).
- */
- struct device_node *node;
- node = of_find_compatible_node(NULL, NULL, "img,meta");
- if (!node) {
- pr_warn("%s: no compatible img,meta DT node found\n",
- __func__);
- return;
- }
-
- clk_core = of_clk_get_by_name(node, "core");
- if (IS_ERR(clk_core)) {
- pr_warn("%s: no core clock found in DT\n",
- __func__);
- return;
- }
-
- /*
- * Override the core frequency callback to use
- * this clk.
- */
- _meta_clock.get_core_freq = get_core_freq_clk;
-}
-
-/**
- * init_metag_clocks() - Set up clocks from devicetree.
- *
- * Set up important clocks from device tree. In particular any needed for clock
- * sources.
- */
-void __init init_metag_clocks(void)
-{
- init_metag_core_clock();
-
- pr_info("Core clock frequency: %lu Hz\n", get_coreclock());
-}
-
-/**
- * setup_meta_clocks() - Early set up of the Meta clock.
- * @desc: Clock descriptor usually provided by machine description
- *
- * Ensures all callbacks are valid.
- */
-void __init setup_meta_clocks(struct meta_clock_desc *desc)
-{
- /* copy callbacks */
- if (desc)
- _meta_clock = *desc;
-
- /* set fallback functions */
- if (!_meta_clock.get_core_freq)
- _meta_clock.get_core_freq = get_core_freq_default;
-}
-
diff --git a/arch/metag/kernel/core_reg.c b/arch/metag/kernel/core_reg.c
deleted file mode 100644
index df2833f2766f..000000000000
--- a/arch/metag/kernel/core_reg.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Support for reading and writing Meta core internal registers.
- *
- * Copyright (C) 2011 Imagination Technologies Ltd.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/export.h>
-
-#include <asm/core_reg.h>
-#include <asm/global_lock.h>
-#include <asm/hwthread.h>
-#include <asm/io.h>
-#include <asm/metag_mem.h>
-#include <asm/metag_regs.h>
-
-#define UNIT_BIT_MASK TXUXXRXRQ_UXX_BITS
-#define REG_BIT_MASK TXUXXRXRQ_RX_BITS
-#define THREAD_BIT_MASK TXUXXRXRQ_TX_BITS
-
-#define UNIT_SHIFTS TXUXXRXRQ_UXX_S
-#define REG_SHIFTS TXUXXRXRQ_RX_S
-#define THREAD_SHIFTS TXUXXRXRQ_TX_S
-
-#define UNIT_VAL(x) (((x) << UNIT_SHIFTS) & UNIT_BIT_MASK)
-#define REG_VAL(x) (((x) << REG_SHIFTS) & REG_BIT_MASK)
-#define THREAD_VAL(x) (((x) << THREAD_SHIFTS) & THREAD_BIT_MASK)
-
-/*
- * core_reg_write() - modify the content of a register in a core unit.
- * @unit: The unit to be modified.
- * @reg: Register number within the unit.
- * @thread: The thread we want to access.
- * @val: The new value to write.
- *
- * Check asm/metag_regs.h for a list/defines of supported units (ie: TXUPC_ID,
- * TXUTR_ID, etc), and regnums within the units (ie: TXMASKI_REGNUM,
- * TXPOLLI_REGNUM, etc).
- */
-void core_reg_write(int unit, int reg, int thread, unsigned int val)
-{
- unsigned long flags;
-
- /* TXUCT_ID has its own memory mapped registers */
- if (unit == TXUCT_ID) {
- void __iomem *cu_reg = __CU_addr(thread, reg);
- metag_out32(val, cu_reg);
- return;
- }
-
- __global_lock2(flags);
-
- /* wait for ready */
- while (!(metag_in32(TXUXXRXRQ) & TXUXXRXRQ_DREADY_BIT))
- udelay(10);
-
- /* set the value to write */
- metag_out32(val, TXUXXRXDT);
-
- /* set the register to write */
- val = UNIT_VAL(unit) | REG_VAL(reg) | THREAD_VAL(thread);
- metag_out32(val, TXUXXRXRQ);
-
- /* wait for finish */
- while (!(metag_in32(TXUXXRXRQ) & TXUXXRXRQ_DREADY_BIT))
- udelay(10);
-
- __global_unlock2(flags);
-}
-EXPORT_SYMBOL(core_reg_write);
-
-/*
- * core_reg_read() - read the content of a register in a core unit.
- * @unit: The unit to be modified.
- * @reg: Register number within the unit.
- * @thread: The thread we want to access.
- *
- * Check asm/metag_regs.h for a list/defines of supported units (ie: TXUPC_ID,
- * TXUTR_ID, etc), and regnums within the units (ie: TXMASKI_REGNUM,
- * TXPOLLI_REGNUM, etc).
- */
-unsigned int core_reg_read(int unit, int reg, int thread)
-{
- unsigned long flags;
- unsigned int val;
-
- /* TXUCT_ID has its own memory mapped registers */
- if (unit == TXUCT_ID) {
- void __iomem *cu_reg = __CU_addr(thread, reg);
- val = metag_in32(cu_reg);
- return val;
- }
-
- __global_lock2(flags);
-
- /* wait for ready */
- while (!(metag_in32(TXUXXRXRQ) & TXUXXRXRQ_DREADY_BIT))
- udelay(10);
-
- /* set the register to read */
- val = (UNIT_VAL(unit) | REG_VAL(reg) | THREAD_VAL(thread) |
- TXUXXRXRQ_RDnWR_BIT);
- metag_out32(val, TXUXXRXRQ);
-
- /* wait for finish */
- while (!(metag_in32(TXUXXRXRQ) & TXUXXRXRQ_DREADY_BIT))
- udelay(10);
-
- /* read the register value */
- val = metag_in32(TXUXXRXDT);
-
- __global_unlock2(flags);
-
- return val;
-}
-EXPORT_SYMBOL(core_reg_read);
diff --git a/arch/metag/kernel/da.c b/arch/metag/kernel/da.c
deleted file mode 100644
index a35dbed6fffa..000000000000
--- a/arch/metag/kernel/da.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Meta DA JTAG debugger control.
- *
- * Copyright 2012 Imagination Technologies Ltd.
- */
-
-
-#include <linux/export.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <asm/da.h>
-#include <asm/metag_mem.h>
-
-bool _metag_da_present;
-EXPORT_SYMBOL_GPL(_metag_da_present);
-
-int __init metag_da_probe(void)
-{
- _metag_da_present = (metag_in32(T0VECINT_BHALT) == 1);
- if (_metag_da_present)
- pr_info("DA present\n");
- else
- pr_info("DA not present\n");
- return 0;
-}
diff --git a/arch/metag/kernel/devtree.c b/arch/metag/kernel/devtree.c
deleted file mode 100644
index 6af749a64438..000000000000
--- a/arch/metag/kernel/devtree.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/arch/metag/kernel/devtree.c
- *
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * Based on ARM version:
- * Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/export.h>
-#include <linux/types.h>
-#include <linux/of_fdt.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-
-static const void * __init arch_get_next_mach(const char *const **match)
-{
- static const struct machine_desc *mdesc = __arch_info_begin;
- const struct machine_desc *m = mdesc;
-
- if (m >= __arch_info_end)
- return NULL;
-
- mdesc++;
- *match = m->dt_compat;
- return m;
-}
-
-/**
- * setup_machine_fdt - Machine setup when an dtb was passed to the kernel
- * @dt: virtual address pointer to dt blob
- *
- * If a dtb was passed to the kernel, then use it to choose the correct
- * machine_desc and to setup the system.
- */
-const struct machine_desc * __init setup_machine_fdt(void *dt)
-{
- const struct machine_desc *mdesc;
-
- /* check device tree validity */
- if (!early_init_dt_scan(dt))
- return NULL;
-
- mdesc = of_flat_dt_match_machine(NULL, arch_get_next_mach);
- if (!mdesc)
- dump_machine_table(); /* does not return */
- pr_info("Machine name: %s\n", mdesc->name);
-
- return mdesc;
-}
diff --git a/arch/metag/kernel/dma.c b/arch/metag/kernel/dma.c
deleted file mode 100644
index f0ab3a498328..000000000000
--- a/arch/metag/kernel/dma.c
+++ /dev/null
@@ -1,588 +0,0 @@
-/*
- * Meta version derived from arch/powerpc/lib/dma-noncoherent.c
- * Copyright (C) 2008 Imagination Technologies Ltd.
- *
- * PowerPC version derived from arch/arm/mm/consistent.c
- * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
- *
- * Copyright (C) 2000 Russell King
- *
- * Consistent memory allocators. Used for DMA devices that want to
- * share uncached memory with the processor core. The function return
- * is the virtual address and 'dma_handle' is the physical address.
- * Mostly stolen from the ARM port, with some changes for PowerPC.
- * -- Dan
- *
- * Reorganized to get rid of the arch-specific consistent_* functions
- * and provide non-coherent implementations for the DMA API. -Matt
- *
- * Added in_interrupt() safe dma_alloc_coherent()/dma_free_coherent()
- * implementation. This is pulled straight from ARM and barely
- * modified. -Matt
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/export.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/highmem.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-
-#include <asm/tlbflush.h>
-#include <asm/mmu.h>
-
-#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_START) \
- >> PAGE_SHIFT)
-
-static u64 get_coherent_dma_mask(struct device *dev)
-{
- u64 mask = ~0ULL;
-
- if (dev) {
- mask = dev->coherent_dma_mask;
-
- /*
- * Sanity check the DMA mask - it must be non-zero, and
- * must be able to be satisfied by a DMA allocation.
- */
- if (mask == 0) {
- dev_warn(dev, "coherent DMA mask is unset\n");
- return 0;
- }
- }
-
- return mask;
-}
-/*
- * This is the page table (2MB) covering uncached, DMA consistent allocations
- */
-static pte_t *consistent_pte;
-static DEFINE_SPINLOCK(consistent_lock);
-
-/*
- * VM region handling support.
- *
- * This should become something generic, handling VM region allocations for
- * vmalloc and similar (ioremap, module space, etc).
- *
- * I envisage vmalloc()'s supporting vm_struct becoming:
- *
- * struct vm_struct {
- * struct metag_vm_region region;
- * unsigned long flags;
- * struct page **pages;
- * unsigned int nr_pages;
- * unsigned long phys_addr;
- * };
- *
- * get_vm_area() would then call metag_vm_region_alloc with an appropriate
- * struct metag_vm_region head (eg):
- *
- * struct metag_vm_region vmalloc_head = {
- * .vm_list = LIST_HEAD_INIT(vmalloc_head.vm_list),
- * .vm_start = VMALLOC_START,
- * .vm_end = VMALLOC_END,
- * };
- *
- * However, vmalloc_head.vm_start is variable (typically, it is dependent on
- * the amount of RAM found at boot time.) I would imagine that get_vm_area()
- * would have to initialise this each time prior to calling
- * metag_vm_region_alloc().
- */
-struct metag_vm_region {
- struct list_head vm_list;
- unsigned long vm_start;
- unsigned long vm_end;
- struct page *vm_pages;
- int vm_active;
-};
-
-static struct metag_vm_region consistent_head = {
- .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
- .vm_start = CONSISTENT_START,
- .vm_end = CONSISTENT_END,
-};
-
-static struct metag_vm_region *metag_vm_region_alloc(struct metag_vm_region
- *head, size_t size,
- gfp_t gfp)
-{
- unsigned long addr = head->vm_start, end = head->vm_end - size;
- unsigned long flags;
- struct metag_vm_region *c, *new;
-
- new = kmalloc(sizeof(struct metag_vm_region), gfp);
- if (!new)
- goto out;
-
- spin_lock_irqsave(&consistent_lock, flags);
-
- list_for_each_entry(c, &head->vm_list, vm_list) {
- if ((addr + size) < addr)
- goto nospc;
- if ((addr + size) <= c->vm_start)
- goto found;
- addr = c->vm_end;
- if (addr > end)
- goto nospc;
- }
-
-found:
- /*
- * Insert this entry _before_ the one we found.
- */
- list_add_tail(&new->vm_list, &c->vm_list);
- new->vm_start = addr;
- new->vm_end = addr + size;
- new->vm_active = 1;
-
- spin_unlock_irqrestore(&consistent_lock, flags);
- return new;
-
-nospc:
- spin_unlock_irqrestore(&consistent_lock, flags);
- kfree(new);
-out:
- return NULL;
-}
-
-static struct metag_vm_region *metag_vm_region_find(struct metag_vm_region
- *head, unsigned long addr)
-{
- struct metag_vm_region *c;
-
- list_for_each_entry(c, &head->vm_list, vm_list) {
- if (c->vm_active && c->vm_start == addr)
- goto out;
- }
- c = NULL;
-out:
- return c;
-}
-
-/*
- * Allocate DMA-coherent memory space and return both the kernel remapped
- * virtual and bus address for that space.
- */
-static void *metag_dma_alloc(struct device *dev, size_t size,
- dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
-{
- struct page *page;
- struct metag_vm_region *c;
- unsigned long order;
- u64 mask = get_coherent_dma_mask(dev);
- u64 limit;
-
- if (!consistent_pte) {
- pr_err("%s: not initialised\n", __func__);
- dump_stack();
- return NULL;
- }
-
- if (!mask)
- goto no_page;
- size = PAGE_ALIGN(size);
- limit = (mask + 1) & ~mask;
- if ((limit && size >= limit)
- || size >= (CONSISTENT_END - CONSISTENT_START)) {
- pr_warn("coherent allocation too big (requested %#x mask %#Lx)\n",
- size, mask);
- return NULL;
- }
-
- order = get_order(size);
-
- if (mask != 0xffffffff)
- gfp |= GFP_DMA;
-
- page = alloc_pages(gfp, order);
- if (!page)
- goto no_page;
-
- /*
- * Invalidate any data that might be lurking in the
- * kernel direct-mapped region for device DMA.
- */
- {
- void *kaddr = page_address(page);
- memset(kaddr, 0, size);
- flush_dcache_region(kaddr, size);
- }
-
- /*
- * Allocate a virtual address in the consistent mapping region.
- */
- c = metag_vm_region_alloc(&consistent_head, size,
- gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
- if (c) {
- unsigned long vaddr = c->vm_start;
- pte_t *pte = consistent_pte + CONSISTENT_OFFSET(vaddr);
- struct page *end = page + (1 << order);
-
- c->vm_pages = page;
- split_page(page, order);
-
- /*
- * Set the "dma handle"
- */
- *handle = page_to_bus(page);
-
- do {
- BUG_ON(!pte_none(*pte));
-
- SetPageReserved(page);
- set_pte_at(&init_mm, vaddr,
- pte, mk_pte(page,
- pgprot_writecombine
- (PAGE_KERNEL)));
- page++;
- pte++;
- vaddr += PAGE_SIZE;
- } while (size -= PAGE_SIZE);
-
- /*
- * Free the otherwise unused pages.
- */
- while (page < end) {
- __free_page(page);
- page++;
- }
-
- return (void *)c->vm_start;
- }
-
- if (page)
- __free_pages(page, order);
-no_page:
- return NULL;
-}
-
-/*
- * free a page as defined by the above mapping.
- */
-static void metag_dma_free(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- struct metag_vm_region *c;
- unsigned long flags, addr;
- pte_t *ptep;
-
- size = PAGE_ALIGN(size);
-
- spin_lock_irqsave(&consistent_lock, flags);
-
- c = metag_vm_region_find(&consistent_head, (unsigned long)vaddr);
- if (!c)
- goto no_area;
-
- c->vm_active = 0;
- if ((c->vm_end - c->vm_start) != size) {
- pr_err("%s: freeing wrong coherent size (%ld != %d)\n",
- __func__, c->vm_end - c->vm_start, size);
- dump_stack();
- size = c->vm_end - c->vm_start;
- }
-
- ptep = consistent_pte + CONSISTENT_OFFSET(c->vm_start);
- addr = c->vm_start;
- do {
- pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
- unsigned long pfn;
-
- ptep++;
- addr += PAGE_SIZE;
-
- if (!pte_none(pte) && pte_present(pte)) {
- pfn = pte_pfn(pte);
-
- if (pfn_valid(pfn)) {
- struct page *page = pfn_to_page(pfn);
- __free_reserved_page(page);
- continue;
- }
- }
-
- pr_crit("%s: bad page in kernel page table\n",
- __func__);
- } while (size -= PAGE_SIZE);
-
- flush_tlb_kernel_range(c->vm_start, c->vm_end);
-
- list_del(&c->vm_list);
-
- spin_unlock_irqrestore(&consistent_lock, flags);
-
- kfree(c);
- return;
-
-no_area:
- spin_unlock_irqrestore(&consistent_lock, flags);
- pr_err("%s: trying to free invalid coherent area: %p\n",
- __func__, vaddr);
- dump_stack();
-}
-
-static int metag_dma_mmap(struct device *dev, struct vm_area_struct *vma,
- void *cpu_addr, dma_addr_t dma_addr, size_t size,
- unsigned long attrs)
-{
- unsigned long flags, user_size, kern_size;
- struct metag_vm_region *c;
- int ret = -ENXIO;
-
- if (attrs & DMA_ATTR_WRITE_COMBINE)
- vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
- else
- vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-
- user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
-
- spin_lock_irqsave(&consistent_lock, flags);
- c = metag_vm_region_find(&consistent_head, (unsigned long)cpu_addr);
- spin_unlock_irqrestore(&consistent_lock, flags);
-
- if (c) {
- unsigned long off = vma->vm_pgoff;
-
- kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT;
-
- if (off < kern_size &&
- user_size <= (kern_size - off)) {
- ret = remap_pfn_range(vma, vma->vm_start,
- page_to_pfn(c->vm_pages) + off,
- user_size << PAGE_SHIFT,
- vma->vm_page_prot);
- }
- }
-
-
- return ret;
-}
-
-/*
- * Initialise the consistent memory allocation.
- */
-static int __init dma_alloc_init(void)
-{
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte;
- int ret = 0;
-
- do {
- int offset = pgd_index(CONSISTENT_START);
- pgd = pgd_offset(&init_mm, CONSISTENT_START);
- pud = pud_alloc(&init_mm, pgd, CONSISTENT_START);
- pmd = pmd_alloc(&init_mm, pud, CONSISTENT_START);
- WARN_ON(!pmd_none(*pmd));
-
- pte = pte_alloc_kernel(pmd, CONSISTENT_START);
- if (!pte) {
- pr_err("%s: no pte tables\n", __func__);
- ret = -ENOMEM;
- break;
- }
-
- pgd_k = ((pgd_t *) mmu_get_base()) + offset;
- pud_k = pud_offset(pgd_k, CONSISTENT_START);
- pmd_k = pmd_offset(pud_k, CONSISTENT_START);
- set_pmd(pmd_k, *pmd);
-
- consistent_pte = pte;
- } while (0);
-
- return ret;
-}
-early_initcall(dma_alloc_init);
-
-/*
- * make an area consistent to devices.
- */
-static void dma_sync_for_device(void *vaddr, size_t size, int dma_direction)
-{
- /*
- * Ensure any writes get through the write combiner. This is necessary
- * even with DMA_FROM_DEVICE, or the write may dirty the cache after
- * we've invalidated it and get written back during the DMA.
- */
-
- barrier();
-
- switch (dma_direction) {
- case DMA_BIDIRECTIONAL:
- /*
- * Writeback to ensure the device can see our latest changes and
- * so that we have no dirty lines, and invalidate the cache
- * lines too in preparation for receiving the buffer back
- * (dma_sync_for_cpu) later.
- */
- flush_dcache_region(vaddr, size);
- break;
- case DMA_TO_DEVICE:
- /*
- * Writeback to ensure the device can see our latest changes.
- * There's no need to invalidate as the device shouldn't write
- * to the buffer.
- */
- writeback_dcache_region(vaddr, size);
- break;
- case DMA_FROM_DEVICE:
- /*
- * Invalidate to ensure we have no dirty lines that could get
- * written back during the DMA. It's also safe to flush
- * (writeback) here if necessary.
- */
- invalidate_dcache_region(vaddr, size);
- break;
- case DMA_NONE:
- BUG();
- }
-
- wmb();
-}
-
-/*
- * make an area consistent to the core.
- */
-static void dma_sync_for_cpu(void *vaddr, size_t size, int dma_direction)
-{
- /*
- * Hardware L2 cache prefetch doesn't occur across 4K physical
- * boundaries, however according to Documentation/DMA-API-HOWTO.txt
- * kmalloc'd memory is DMA'able, so accesses in nearby memory could
- * trigger a cache fill in the DMA buffer.
- *
- * This should never cause dirty lines, so a flush or invalidate should
- * be safe to allow us to see data from the device.
- */
- if (_meta_l2c_pf_is_enabled()) {
- switch (dma_direction) {
- case DMA_BIDIRECTIONAL:
- case DMA_FROM_DEVICE:
- invalidate_dcache_region(vaddr, size);
- break;
- case DMA_TO_DEVICE:
- /* The device shouldn't have written to the buffer */
- break;
- case DMA_NONE:
- BUG();
- }
- }
-
- rmb();
-}
-
-static dma_addr_t metag_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction, unsigned long attrs)
-{
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- dma_sync_for_device((void *)(page_to_phys(page) + offset),
- size, direction);
- return page_to_phys(page) + offset;
-}
-
-static void metag_dma_unmap_page(struct device *dev, dma_addr_t dma_address,
- size_t size, enum dma_data_direction direction,
- unsigned long attrs)
-{
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- dma_sync_for_cpu(phys_to_virt(dma_address), size, direction);
-}
-
-static int metag_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sglist, sg, nents, i) {
- BUG_ON(!sg_page(sg));
-
- sg->dma_address = sg_phys(sg);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
-
- dma_sync_for_device(sg_virt(sg), sg->length, direction);
- }
-
- return nents;
-}
-
-
-static void metag_dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
- int nhwentries, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sglist, sg, nhwentries, i) {
- BUG_ON(!sg_page(sg));
-
- sg->dma_address = sg_phys(sg);
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
-
- dma_sync_for_cpu(sg_virt(sg), sg->length, direction);
- }
-}
-
-static void metag_dma_sync_single_for_cpu(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- dma_sync_for_cpu(phys_to_virt(dma_handle), size, direction);
-}
-
-static void metag_dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- dma_sync_for_device(phys_to_virt(dma_handle), size, direction);
-}
-
-static void metag_dma_sync_sg_for_cpu(struct device *dev,
- struct scatterlist *sglist, int nelems,
- enum dma_data_direction direction)
-{
- int i;
- struct scatterlist *sg;
-
- for_each_sg(sglist, sg, nelems, i)
- dma_sync_for_cpu(sg_virt(sg), sg->length, direction);
-}
-
-static void metag_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sglist, int nelems,
- enum dma_data_direction direction)
-{
- int i;
- struct scatterlist *sg;
-
- for_each_sg(sglist, sg, nelems, i)
- dma_sync_for_device(sg_virt(sg), sg->length, direction);
-}
-
-const struct dma_map_ops metag_dma_ops = {
- .alloc = metag_dma_alloc,
- .free = metag_dma_free,
- .map_page = metag_dma_map_page,
- .map_sg = metag_dma_map_sg,
- .sync_single_for_device = metag_dma_sync_single_for_device,
- .sync_single_for_cpu = metag_dma_sync_single_for_cpu,
- .sync_sg_for_cpu = metag_dma_sync_sg_for_cpu,
- .mmap = metag_dma_mmap,
-};
-EXPORT_SYMBOL(metag_dma_ops);
diff --git a/arch/metag/kernel/ftrace.c b/arch/metag/kernel/ftrace.c
deleted file mode 100644
index f7b23d300881..000000000000
--- a/arch/metag/kernel/ftrace.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (C) 2008 Imagination Technologies Ltd.
- * Licensed under the GPL
- *
- * Dynamic ftrace support.
- */
-
-#include <linux/ftrace.h>
-#include <linux/io.h>
-#include <linux/uaccess.h>
-
-#include <asm/cacheflush.h>
-
-#define D04_MOVT_TEMPLATE 0x02200005
-#define D04_CALL_TEMPLATE 0xAC200005
-#define D1RTP_MOVT_TEMPLATE 0x03200005
-#define D1RTP_CALL_TEMPLATE 0xAC200006
-
-static const unsigned long NOP[2] = {0xa0fffffe, 0xa0fffffe};
-static unsigned long movt_and_call_insn[2];
-
-static unsigned char *ftrace_nop_replace(void)
-{
- return (char *)&NOP[0];
-}
-
-static unsigned char *ftrace_call_replace(unsigned long pc, unsigned long addr)
-{
- unsigned long hi16, low16;
-
- hi16 = (addr & 0xffff0000) >> 13;
- low16 = (addr & 0x0000ffff) << 3;
-
- /*
- * The compiler makes the call to mcount_wrapper()
- * (Meta's wrapper around mcount()) through the register
- * D0.4. So whenever we're patching one of those compiler-generated
- * calls we also need to go through D0.4. Otherwise use D1RtP.
- */
- if (pc == (unsigned long)&ftrace_call) {
- writel(D1RTP_MOVT_TEMPLATE | hi16, &movt_and_call_insn[0]);
- writel(D1RTP_CALL_TEMPLATE | low16, &movt_and_call_insn[1]);
- } else {
- writel(D04_MOVT_TEMPLATE | hi16, &movt_and_call_insn[0]);
- writel(D04_CALL_TEMPLATE | low16, &movt_and_call_insn[1]);
- }
-
- return (unsigned char *)&movt_and_call_insn[0];
-}
-
-static int ftrace_modify_code(unsigned long pc, unsigned char *old_code,
- unsigned char *new_code)
-{
- unsigned char replaced[MCOUNT_INSN_SIZE];
-
- /*
- * Note:
- * We are paranoid about modifying text, as if a bug was to happen, it
- * could cause us to read or write to someplace that could cause harm.
- * Carefully read and modify the code with probe_kernel_*(), and make
- * sure what we read is what we expected it to be before modifying it.
- */
-
- /* read the text we want to modify */
- if (probe_kernel_read(replaced, (void *)pc, MCOUNT_INSN_SIZE))
- return -EFAULT;
-
- /* Make sure it is what we expect it to be */
- if (memcmp(replaced, old_code, MCOUNT_INSN_SIZE) != 0)
- return -EINVAL;
-
- /* replace the text with the new text */
- if (probe_kernel_write((void *)pc, new_code, MCOUNT_INSN_SIZE))
- return -EPERM;
-
- flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
-
- return 0;
-}
-
-int ftrace_update_ftrace_func(ftrace_func_t func)
-{
- int ret;
- unsigned long pc;
- unsigned char old[MCOUNT_INSN_SIZE], *new;
-
- pc = (unsigned long)&ftrace_call;
- memcpy(old, &ftrace_call, MCOUNT_INSN_SIZE);
- new = ftrace_call_replace(pc, (unsigned long)func);
- ret = ftrace_modify_code(pc, old, new);
-
- return ret;
-}
-
-int ftrace_make_nop(struct module *mod,
- struct dyn_ftrace *rec, unsigned long addr)
-{
- unsigned char *new, *old;
- unsigned long ip = rec->ip;
-
- old = ftrace_call_replace(ip, addr);
- new = ftrace_nop_replace();
-
- return ftrace_modify_code(ip, old, new);
-}
-
-int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
-{
- unsigned char *new, *old;
- unsigned long ip = rec->ip;
-
- old = ftrace_nop_replace();
- new = ftrace_call_replace(ip, addr);
-
- return ftrace_modify_code(ip, old, new);
-}
-
-int __init ftrace_dyn_arch_init(void)
-{
- return 0;
-}
diff --git a/arch/metag/kernel/ftrace_stub.S b/arch/metag/kernel/ftrace_stub.S
deleted file mode 100644
index 3acc288217c0..000000000000
--- a/arch/metag/kernel/ftrace_stub.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 2008 Imagination Technologies Ltd.
- * Licensed under the GPL
- *
- */
-
-#include <asm/ftrace.h>
-
- .text
-#ifdef CONFIG_DYNAMIC_FTRACE
- .global _mcount_wrapper
- .type _mcount_wrapper,function
-_mcount_wrapper:
- MOV PC,D0.4
-
- .global _ftrace_caller
- .type _ftrace_caller,function
-_ftrace_caller:
- MSETL [A0StP], D0Ar6, D0Ar4, D0Ar2, D0.4
- MOV D1Ar1, D0.4
- MOV D0Ar2, D1RtP
- SUB D1Ar1,D1Ar1,#MCOUNT_INSN_SIZE
-
- .global _ftrace_call
-_ftrace_call:
- MOVT D1RtP,#HI(_ftrace_stub)
- CALL D1RtP,#LO(_ftrace_stub)
- GETL D0.4, D1RtP, [A0StP++#(-8)]
- GETL D0Ar2, D1Ar1, [A0StP++#(-8)]
- GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
- GETL D0Ar6, D1Ar5, [A0StP++#(-8)]
- MOV PC, D0.4
-#else
-
- .global _mcount_wrapper
- .type _mcount_wrapper,function
-_mcount_wrapper:
- MSETL [A0StP], D0Ar6, D0Ar4, D0Ar2, D0.4
- MOV D1Ar1, D0.4
- MOV D0Ar2, D1RtP
- MOVT D0Re0,#HI(_ftrace_trace_function)
- ADD D0Re0,D0Re0,#LO(_ftrace_trace_function)
- GET D1Ar3,[D0Re0]
- MOVT D1Re0,#HI(_ftrace_stub)
- ADD D1Re0,D1Re0,#LO(_ftrace_stub)
- CMP D1Ar3,D1Re0
- BEQ $Ltrace_exit
- MOV D1RtP,D1Ar3
- SUB D1Ar1,D1Ar1,#MCOUNT_INSN_SIZE
- SWAP PC,D1RtP
-$Ltrace_exit:
- GETL D0.4, D1RtP, [A0StP++#(-8)]
- GETL D0Ar2, D1Ar1, [A0StP++#(-8)]
- GETL D0Ar4, D1Ar3, [A0StP++#(-8)]
- GETL D0Ar6, D1Ar5, [A0StP++#(-8)]
- MOV PC, D0.4
-
-#endif /* CONFIG_DYNAMIC_FTRACE */
-
- .global _ftrace_stub
-_ftrace_stub:
- MOV PC,D1RtP
diff --git a/arch/metag/kernel/head.S b/arch/metag/kernel/head.S
deleted file mode 100644
index 3ed27813413e..000000000000
--- a/arch/metag/kernel/head.S
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
- ! Copyright 2005,2006,2007,2009 Imagination Technologies
-
-#include <linux/init.h>
-#include <asm/metag_mem.h>
-#include <generated/asm-offsets.h>
-#undef __exit
-
- __HEAD
- ! Setup the stack and get going into _metag_start_kernel
- .global __start
- .type __start,function
-__start:
- ! D1Ar1 contains pTBI (ISTAT)
- ! D0Ar2 contains pTBI
- ! D1Ar3 contains __pTBISegs
- ! D0Ar4 contains kernel arglist pointer
-
- MOVT D0Re0,#HI(___pTBIs)
- ADD D0Re0,D0Re0,#LO(___pTBIs)
- SETL [D0Re0],D0Ar2,D1Ar1
- MOVT D0Re0,#HI(___pTBISegs)
- ADD D0Re0,D0Re0,#LO(___pTBISegs)
- SETD [D0Re0],D1Ar3
- MOV A0FrP,#0
- MOV D0Re0,#0
- MOV D1Re0,#0
- MOV D1Ar3,#0
- MOV D1Ar1,D0Ar4 !Store kernel boot params
- MOV D1Ar5,#0
- MOV D0Ar6,#0
-#ifdef CONFIG_METAG_DSP
- MOV D0.8,#0
-#endif
- MOVT A0StP,#HI(_init_thread_union)
- ADD A0StP,A0StP,#LO(_init_thread_union)
- ADD A0StP,A0StP,#THREAD_INFO_SIZE
- MOVT D1RtP,#HI(_metag_start_kernel)
- CALL D1RtP,#LO(_metag_start_kernel)
- .size __start,.-__start
-
- !! Needed by TBX
- .global __exit
- .type __exit,function
-__exit:
- XOR TXENABLE,D0Re0,D0Re0
- .size __exit,.-__exit
-
-#ifdef CONFIG_SMP
- .global _secondary_startup
- .type _secondary_startup,function
-_secondary_startup:
-#if CONFIG_PAGE_OFFSET < LINGLOBAL_BASE
- ! In case GCOn has just been turned on we need to fence any writes that
- ! the boot thread might have performed prior to coherency taking effect.
- MOVT D0Re0,#HI(LINSYSEVENT_WR_ATOMIC_UNLOCK)
- MOV D1Re0,#0
- SETD [D0Re0], D1Re0
-#endif
- MOVT A0StP,#HI(_secondary_data_stack)
- ADD A0StP,A0StP,#LO(_secondary_data_stack)
- GETD A0StP,[A0StP]
- ADD A0StP,A0StP,#THREAD_INFO_SIZE
- B _secondary_start_kernel
- .size _secondary_startup,.-_secondary_startup
-#endif
diff --git a/arch/metag/kernel/irq.c b/arch/metag/kernel/irq.c
deleted file mode 100644
index 704cf17f8370..000000000000
--- a/arch/metag/kernel/irq.c
+++ /dev/null
@@ -1,293 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Linux/Meta general interrupt handling code
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irqchip/metag-ext.h>
-#include <linux/irqchip/metag.h>
-#include <linux/irqdomain.h>
-#include <linux/ratelimit.h>
-
-#include <asm/core_reg.h>
-#include <asm/mach/arch.h>
-#include <linux/uaccess.h>
-
-#ifdef CONFIG_4KSTACKS
-union irq_ctx {
- struct thread_info tinfo;
- u32 stack[THREAD_SIZE/sizeof(u32)];
-};
-
-static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
-static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
-#endif
-
-static struct irq_domain *root_domain;
-
-static unsigned int startup_meta_irq(struct irq_data *data)
-{
- tbi_startup_interrupt(data->hwirq);
- return 0;
-}
-
-static void shutdown_meta_irq(struct irq_data *data)
-{
- tbi_shutdown_interrupt(data->hwirq);
-}
-
-void do_IRQ(int irq, struct pt_regs *regs)
-{
- struct pt_regs *old_regs = set_irq_regs(regs);
-#ifdef CONFIG_4KSTACKS
- struct irq_desc *desc;
- union irq_ctx *curctx, *irqctx;
- u32 *isp;
-#endif
-
- irq_enter();
-
- irq = irq_linear_revmap(root_domain, irq);
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
- /* Debugging check for stack overflow: is there less than 1KB free? */
- {
- unsigned long sp;
-
- sp = __core_reg_get(A0StP);
- sp &= THREAD_SIZE - 1;
-
- if (unlikely(sp > (THREAD_SIZE - 1024)))
- pr_err("Stack overflow in do_IRQ: %ld\n", sp);
- }
-#endif
-
-
-#ifdef CONFIG_4KSTACKS
- curctx = (union irq_ctx *) current_thread_info();
- irqctx = hardirq_ctx[smp_processor_id()];
-
- /*
- * this is where we switch to the IRQ stack. However, if we are
- * already using the IRQ stack (because we interrupted a hardirq
- * handler) we can't do that and just have to keep using the
- * current stack (which is the irq stack already after all)
- */
- if (curctx != irqctx) {
- /* build the stack frame on the IRQ stack */
- isp = (u32 *) ((char *)irqctx + sizeof(struct thread_info));
- irqctx->tinfo.task = curctx->tinfo.task;
-
- /*
- * Copy the softirq bits in preempt_count so that the
- * softirq checks work in the hardirq context.
- */
- irqctx->tinfo.preempt_count =
- (irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
- (curctx->tinfo.preempt_count & SOFTIRQ_MASK);
-
- desc = irq_to_desc(irq);
-
- asm volatile (
- "MOV D0.5,%0\n"
- "MOV D1Ar1,%1\n"
- "MOV D1RtP,%2\n"
- "SWAP A0StP,D0.5\n"
- "SWAP PC,D1RtP\n"
- "MOV A0StP,D0.5\n"
- :
- : "r" (isp), "r" (desc), "r" (desc->handle_irq)
- : "memory", "cc", "D1Ar1", "D0Ar2", "D1Ar3", "D0Ar4",
- "D1Ar5", "D0Ar6", "D0Re0", "D1Re0", "D0.4", "D1RtP",
- "D0.5"
- );
- } else
-#endif
- generic_handle_irq(irq);
-
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-#ifdef CONFIG_4KSTACKS
-
-static char softirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
-
-static char hardirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
-
-/*
- * allocate per-cpu stacks for hardirq and for softirq processing
- */
-void irq_ctx_init(int cpu)
-{
- union irq_ctx *irqctx;
-
- if (hardirq_ctx[cpu])
- return;
-
- irqctx = (union irq_ctx *) &hardirq_stack[cpu * THREAD_SIZE];
- irqctx->tinfo.task = NULL;
- irqctx->tinfo.cpu = cpu;
- irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
- irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
-
- hardirq_ctx[cpu] = irqctx;
-
- irqctx = (union irq_ctx *) &softirq_stack[cpu * THREAD_SIZE];
- irqctx->tinfo.task = NULL;
- irqctx->tinfo.cpu = cpu;
- irqctx->tinfo.preempt_count = 0;
- irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
-
- softirq_ctx[cpu] = irqctx;
-
- pr_info("CPU %u irqstacks, hard=%p soft=%p\n",
- cpu, hardirq_ctx[cpu], softirq_ctx[cpu]);
-}
-
-void irq_ctx_exit(int cpu)
-{
- hardirq_ctx[smp_processor_id()] = NULL;
-}
-
-extern asmlinkage void __do_softirq(void);
-
-void do_softirq_own_stack(void)
-{
- struct thread_info *curctx;
- union irq_ctx *irqctx;
- u32 *isp;
-
- curctx = current_thread_info();
- irqctx = softirq_ctx[smp_processor_id()];
- irqctx->tinfo.task = curctx->task;
-
- /* build the stack frame on the softirq stack */
- isp = (u32 *) ((char *)irqctx + sizeof(struct thread_info));
-
- asm volatile (
- "MOV D0.5,%0\n"
- "SWAP A0StP,D0.5\n"
- "CALLR D1RtP,___do_softirq\n"
- "MOV A0StP,D0.5\n"
- :
- : "r" (isp)
- : "memory", "cc", "D1Ar1", "D0Ar2", "D1Ar3", "D0Ar4",
- "D1Ar5", "D0Ar6", "D0Re0", "D1Re0", "D0.4", "D1RtP",
- "D0.5"
- );
-}
-#endif
-
-static struct irq_chip meta_irq_type = {
- .name = "META-IRQ",
- .irq_startup = startup_meta_irq,
- .irq_shutdown = shutdown_meta_irq,
-};
-
-/**
- * tbisig_map() - Map a TBI signal number to a virtual IRQ number.
- * @hw: Number of the TBI signal. Must be in range.
- *
- * Returns: The virtual IRQ number of the TBI signal number IRQ specified by
- * @hw.
- */
-int tbisig_map(unsigned int hw)
-{
- return irq_create_mapping(root_domain, hw);
-}
-
-/**
- * metag_tbisig_map() - map a tbi signal to a Linux virtual IRQ number
- * @d: root irq domain
- * @irq: virtual irq number
- * @hw: hardware irq number (TBI signal number)
- *
- * This sets up a virtual irq for a specified TBI signal number.
- */
-static int metag_tbisig_map(struct irq_domain *d, unsigned int irq,
- irq_hw_number_t hw)
-{
-#ifdef CONFIG_SMP
- irq_set_chip_and_handler(irq, &meta_irq_type, handle_percpu_irq);
-#else
- irq_set_chip_and_handler(irq, &meta_irq_type, handle_simple_irq);
-#endif
- return 0;
-}
-
-static const struct irq_domain_ops metag_tbisig_domain_ops = {
- .map = metag_tbisig_map,
-};
-
-/*
- * void init_IRQ(void)
- *
- * Parameters: None
- *
- * Returns: Nothing
- *
- * This function should be called during kernel startup to initialize
- * the IRQ handling routines.
- */
-void __init init_IRQ(void)
-{
- root_domain = irq_domain_add_linear(NULL, 32,
- &metag_tbisig_domain_ops, NULL);
- if (unlikely(!root_domain))
- panic("init_IRQ: cannot add root IRQ domain");
-
- irq_ctx_init(smp_processor_id());
-
- init_internal_IRQ();
- init_external_IRQ();
-
- if (machine_desc->init_irq)
- machine_desc->init_irq();
-}
-
-int __init arch_probe_nr_irqs(void)
-{
- if (machine_desc->nr_irqs)
- nr_irqs = machine_desc->nr_irqs;
- return 0;
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-/*
- * The CPU has been marked offline. Migrate IRQs off this CPU. If
- * the affinity settings do not allow other CPUs, force them onto any
- * available CPU.
- */
-void migrate_irqs(void)
-{
- unsigned int i, cpu = smp_processor_id();
-
- for_each_active_irq(i) {
- struct irq_data *data = irq_get_irq_data(i);
- struct cpumask *mask;
- unsigned int newcpu;
-
- if (irqd_is_per_cpu(data))
- continue;
-
- mask = irq_data_get_affinity_mask(data);
- if (!cpumask_test_cpu(cpu, mask))
- continue;
-
- newcpu = cpumask_any_and(mask, cpu_online_mask);
-
- if (newcpu >= nr_cpu_ids) {
- pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
- i, cpu);
-
- cpumask_setall(mask);
- }
- irq_set_affinity(i, mask);
- }
-}
-#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/metag/kernel/kick.c b/arch/metag/kernel/kick.c
deleted file mode 100644
index beb377621322..000000000000
--- a/arch/metag/kernel/kick.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (C) 2009 Imagination Technologies
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- *
- * The Meta KICK interrupt mechanism is generally a useful feature, so
- * we provide an interface for registering multiple interrupt
- * handlers. All the registered interrupt handlers are "chained". When
- * a KICK interrupt is received the first function in the list is
- * called. If that interrupt handler cannot handle the KICK the next
- * one is called, then the next until someone handles it (or we run
- * out of functions). As soon as one function handles the interrupt no
- * other handlers are called.
- *
- * The only downside of chaining interrupt handlers is that each
- * handler must be able to detect whether the KICK was intended for it
- * or not. For example, when the IPI handler runs and it sees that
- * there are no IPI messages it must not signal that the KICK was
- * handled, thereby giving the other handlers a chance to run.
- *
- * The reason that we provide our own interface for calling KICK
- * handlers instead of using the generic kernel infrastructure is that
- * the KICK handlers require access to a CPU's pTBI structure. So we
- * pass it as an argument.
- */
-#include <linux/export.h>
-#include <linux/hardirq.h>
-#include <linux/irq.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/types.h>
-
-#include <asm/traps.h>
-
-/*
- * All accesses/manipulations of kick_handlers_list should be
- * performed while holding kick_handlers_lock.
- */
-static DEFINE_SPINLOCK(kick_handlers_lock);
-static LIST_HEAD(kick_handlers_list);
-
-void kick_register_func(struct kick_irq_handler *kh)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&kick_handlers_lock, flags);
-
- list_add_tail(&kh->list, &kick_handlers_list);
-
- spin_unlock_irqrestore(&kick_handlers_lock, flags);
-}
-EXPORT_SYMBOL(kick_register_func);
-
-void kick_unregister_func(struct kick_irq_handler *kh)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&kick_handlers_lock, flags);
-
- list_del(&kh->list);
-
- spin_unlock_irqrestore(&kick_handlers_lock, flags);
-}
-EXPORT_SYMBOL(kick_unregister_func);
-
-TBIRES
-kick_handler(TBIRES State, int SigNum, int Triggers, int Inst, PTBI pTBI)
-{
- struct pt_regs *old_regs;
- struct kick_irq_handler *kh;
- struct list_head *lh;
- int handled = 0;
- TBIRES ret;
-
- head_end(State, ~INTS_OFF_MASK);
-
- /* If we interrupted user code handle any critical sections. */
- if (State.Sig.SaveMask & TBICTX_PRIV_BIT)
- restart_critical_section(State);
-
- trace_hardirqs_off();
-
- old_regs = set_irq_regs((struct pt_regs *)State.Sig.pCtx);
- irq_enter();
-
- /*
- * There is no need to disable interrupts here because we
- * can't nest KICK interrupts in a KICK interrupt handler.
- */
- spin_lock(&kick_handlers_lock);
-
- list_for_each(lh, &kick_handlers_list) {
- kh = list_entry(lh, struct kick_irq_handler, list);
-
- ret = kh->func(State, SigNum, Triggers, Inst, pTBI, &handled);
- if (handled)
- break;
- }
-
- spin_unlock(&kick_handlers_lock);
-
- WARN_ON(!handled);
-
- irq_exit();
- set_irq_regs(old_regs);
-
- return tail_end(ret);
-}
diff --git a/arch/metag/kernel/machines.c b/arch/metag/kernel/machines.c
deleted file mode 100644
index e49790181051..000000000000
--- a/arch/metag/kernel/machines.c
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/metag/kernel/machines.c
- *
- * Copyright (C) 2012 Imagination Technologies Ltd.
- *
- * Generic Meta Boards.
- */
-
-#include <linux/init.h>
-#include <asm/irq.h>
-#include <asm/mach/arch.h>
-
-static const char *meta_boards_compat[] __initdata = {
- "img,meta",
- NULL,
-};
-
-MACHINE_START(META, "Generic Meta")
- .dt_compat = meta_boards_compat,
-MACHINE_END
diff --git a/arch/metag/kernel/metag_ksyms.c b/arch/metag/kernel/metag_ksyms.c
deleted file mode 100644
index e312386efb72..000000000000
--- a/arch/metag/kernel/metag_ksyms.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/export.h>
-#include <linux/types.h>
-
-#include <asm/checksum.h>
-#include <asm/div64.h>
-#include <asm/ftrace.h>
-#include <asm/page.h>
-#include <asm/string.h>
-#include <asm/tbx.h>
-
-EXPORT_SYMBOL(clear_page);
-EXPORT_SYMBOL(copy_page);
-
-#ifdef CONFIG_FLATMEM
-/* needed for the pfn_valid macro */
-EXPORT_SYMBOL(max_pfn);
-EXPORT_SYMBOL(min_low_pfn);
-#endif
-
-/* Network checksum functions */
-EXPORT_SYMBOL(csum_partial);
-
-/* TBI symbols */
-EXPORT_SYMBOL(__TBI);
-EXPORT_SYMBOL(__TBIFindSeg);
-EXPORT_SYMBOL(__TBIPoll);
-EXPORT_SYMBOL(__TBITimeStamp);
-
-#define DECLARE_EXPORT(name) extern void name(void); EXPORT_SYMBOL(name)
-
-/* libgcc functions */
-DECLARE_EXPORT(__ashldi3);
-DECLARE_EXPORT(__ashrdi3);
-DECLARE_EXPORT(__lshrdi3);
-DECLARE_EXPORT(__udivsi3);
-DECLARE_EXPORT(__divsi3);
-DECLARE_EXPORT(__umodsi3);
-DECLARE_EXPORT(__modsi3);
-DECLARE_EXPORT(__muldi3);
-DECLARE_EXPORT(__cmpdi2);
-DECLARE_EXPORT(__ucmpdi2);
-
-/* Maths functions */
-EXPORT_SYMBOL(div_u64);
-EXPORT_SYMBOL(div_s64);
-
-/* String functions */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-EXPORT_SYMBOL(memmove);
-
-#ifdef CONFIG_FUNCTION_TRACER
-EXPORT_SYMBOL(mcount_wrapper);
-#endif
diff --git a/arch/metag/kernel/module.c b/arch/metag/kernel/module.c
deleted file mode 100644
index bb8dfba9a763..000000000000
--- a/arch/metag/kernel/module.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/* Kernel module help for Meta.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-*/
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/sort.h>
-
-#include <asm/unaligned.h>
-
-/* Count how many different relocations (different symbol, different
- addend) */
-static unsigned int count_relocs(const Elf32_Rela *rela, unsigned int num)
-{
- unsigned int i, r_info, r_addend, _count_relocs;
-
- _count_relocs = 0;
- r_info = 0;
- r_addend = 0;
- for (i = 0; i < num; i++)
- /* Only count relbranch relocs, others don't need stubs */
- if (ELF32_R_TYPE(rela[i].r_info) == R_METAG_RELBRANCH &&
- (r_info != ELF32_R_SYM(rela[i].r_info) ||
- r_addend != rela[i].r_addend)) {
- _count_relocs++;
- r_info = ELF32_R_SYM(rela[i].r_info);
- r_addend = rela[i].r_addend;
- }
-
- return _count_relocs;
-}
-
-static int relacmp(const void *_x, const void *_y)
-{
- const Elf32_Rela *x, *y;
-
- y = (Elf32_Rela *)_x;
- x = (Elf32_Rela *)_y;
-
- /* Compare the entire r_info (as opposed to ELF32_R_SYM(r_info) only) to
- * make the comparison cheaper/faster. It won't affect the sorting or
- * the counting algorithms' performance
- */
- if (x->r_info < y->r_info)
- return -1;
- else if (x->r_info > y->r_info)
- return 1;
- else if (x->r_addend < y->r_addend)
- return -1;
- else if (x->r_addend > y->r_addend)
- return 1;
- else
- return 0;
-}
-
-static void relaswap(void *_x, void *_y, int size)
-{
- uint32_t *x, *y, tmp;
- int i;
-
- y = (uint32_t *)_x;
- x = (uint32_t *)_y;
-
- for (i = 0; i < sizeof(Elf32_Rela) / sizeof(uint32_t); i++) {
- tmp = x[i];
- x[i] = y[i];
- y[i] = tmp;
- }
-}
-
-/* Get the potential trampolines size required of the init and
- non-init sections */
-static unsigned long get_plt_size(const Elf32_Ehdr *hdr,
- const Elf32_Shdr *sechdrs,
- const char *secstrings,
- int is_init)
-{
- unsigned long ret = 0;
- unsigned i;
-
- /* Everything marked ALLOC (this includes the exported
- symbols) */
- for (i = 1; i < hdr->e_shnum; i++) {
- /* If it's called *.init*, and we're not init, we're
- not interested */
- if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != NULL)
- != is_init)
- continue;
-
- /* We don't want to look at debug sections. */
- if (strstr(secstrings + sechdrs[i].sh_name, ".debug") != NULL)
- continue;
-
- if (sechdrs[i].sh_type == SHT_RELA) {
- pr_debug("Found relocations in section %u\n", i);
- pr_debug("Ptr: %p. Number: %u\n",
- (void *)hdr + sechdrs[i].sh_offset,
- sechdrs[i].sh_size / sizeof(Elf32_Rela));
-
- /* Sort the relocation information based on a symbol and
- * addend key. This is a stable O(n*log n) complexity
- * alogrithm but it will reduce the complexity of
- * count_relocs() to linear complexity O(n)
- */
- sort((void *)hdr + sechdrs[i].sh_offset,
- sechdrs[i].sh_size / sizeof(Elf32_Rela),
- sizeof(Elf32_Rela), relacmp, relaswap);
-
- ret += count_relocs((void *)hdr
- + sechdrs[i].sh_offset,
- sechdrs[i].sh_size
- / sizeof(Elf32_Rela))
- * sizeof(struct metag_plt_entry);
- }
- }
-
- return ret;
-}
-
-int module_frob_arch_sections(Elf32_Ehdr *hdr,
- Elf32_Shdr *sechdrs,
- char *secstrings,
- struct module *me)
-{
- unsigned int i;
-
- /* Find .plt and .init.plt sections */
- for (i = 0; i < hdr->e_shnum; i++) {
- if (strcmp(secstrings + sechdrs[i].sh_name, ".init.plt") == 0)
- me->arch.init_plt_section = i;
- else if (strcmp(secstrings + sechdrs[i].sh_name, ".plt") == 0)
- me->arch.core_plt_section = i;
- }
- if (!me->arch.core_plt_section || !me->arch.init_plt_section) {
- pr_err("Module doesn't contain .plt or .init.plt sections.\n");
- return -ENOEXEC;
- }
-
- /* Override their sizes */
- sechdrs[me->arch.core_plt_section].sh_size
- = get_plt_size(hdr, sechdrs, secstrings, 0);
- sechdrs[me->arch.core_plt_section].sh_type = SHT_NOBITS;
- sechdrs[me->arch.init_plt_section].sh_size
- = get_plt_size(hdr, sechdrs, secstrings, 1);
- sechdrs[me->arch.init_plt_section].sh_type = SHT_NOBITS;
- return 0;
-}
-
-/* Set up a trampoline in the PLT to bounce us to the distant function */
-static uint32_t do_plt_call(void *location, Elf32_Addr val,
- Elf32_Shdr *sechdrs, struct module *mod)
-{
- struct metag_plt_entry *entry;
- /* Instructions used to do the indirect jump. */
- uint32_t tramp[2];
-
- /* We have to trash a register, so we assume that any control
- transfer more than 21-bits away must be a function call
- (so we can use a call-clobbered register). */
-
- /* MOVT D0Re0,#HI(v) */
- tramp[0] = 0x02000005 | (((val & 0xffff0000) >> 16) << 3);
- /* JUMP D0Re0,#LO(v) */
- tramp[1] = 0xac000001 | ((val & 0x0000ffff) << 3);
-
- /* Init, or core PLT? */
- if (location >= mod->core_layout.base
- && location < mod->core_layout.base + mod->core_layout.size)
- entry = (void *)sechdrs[mod->arch.core_plt_section].sh_addr;
- else
- entry = (void *)sechdrs[mod->arch.init_plt_section].sh_addr;
-
- /* Find this entry, or if that fails, the next avail. entry */
- while (entry->tramp[0])
- if (entry->tramp[0] == tramp[0] && entry->tramp[1] == tramp[1])
- return (uint32_t)entry;
- else
- entry++;
-
- entry->tramp[0] = tramp[0];
- entry->tramp[1] = tramp[1];
-
- return (uint32_t)entry;
-}
-
-int apply_relocate_add(Elf32_Shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct module *me)
-{
- unsigned int i;
- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf32_Sym *sym;
- Elf32_Addr relocation;
- uint32_t *location;
- int32_t value;
-
- pr_debug("Applying relocate section %u to %u\n", relsec,
- sechdrs[relsec].sh_info);
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* This is where to make the change */
- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
- + rel[i].r_offset;
- /* This is the symbol it is referring to. Note that all
- undefined symbols have been resolved. */
- sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
- + ELF32_R_SYM(rel[i].r_info);
- relocation = sym->st_value + rel[i].r_addend;
-
- switch (ELF32_R_TYPE(rel[i].r_info)) {
- case R_METAG_NONE:
- break;
- case R_METAG_HIADDR16:
- relocation >>= 16;
- case R_METAG_LOADDR16:
- *location = (*location & 0xfff80007) |
- ((relocation & 0xffff) << 3);
- break;
- case R_METAG_ADDR32:
- /*
- * Packed data structures may cause a misaligned
- * R_METAG_ADDR32 to be emitted.
- */
- put_unaligned(relocation, location);
- break;
- case R_METAG_GETSETOFF:
- *location += ((relocation & 0xfff) << 7);
- break;
- case R_METAG_RELBRANCH:
- if (*location & (0x7ffff << 5)) {
- pr_err("bad relbranch relocation\n");
- break;
- }
-
- /* This jump is too big for the offset slot. Build
- * a PLT to jump through to get to where we want to go.
- * NB: 21bit check - not scaled to 19bit yet
- */
- if (((int32_t)(relocation -
- (uint32_t)location) > 0xfffff) ||
- ((int32_t)(relocation -
- (uint32_t)location) < -0xfffff)) {
- relocation = do_plt_call(location, relocation,
- sechdrs, me);
- }
-
- value = relocation - (uint32_t)location;
-
- /* branch instruction aligned */
- value /= 4;
-
- if ((value > 0x7ffff) || (value < -0x7ffff)) {
- /*
- * this should have been caught by the code
- * above!
- */
- pr_err("overflow of relbranch reloc\n");
- }
-
- *location = (*location & (~(0x7ffff << 5))) |
- ((value & 0x7ffff) << 5);
- break;
-
- default:
- pr_err("module %s: Unknown relocation: %u\n",
- me->name, ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
- }
- return 0;
-}
diff --git a/arch/metag/kernel/perf/Makefile b/arch/metag/kernel/perf/Makefile
deleted file mode 100644
index b158cb27208d..000000000000
--- a/arch/metag/kernel/perf/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# Makefile for performance event core
-
-obj-y += perf_event.o
diff --git a/arch/metag/kernel/perf/perf_event.c b/arch/metag/kernel/perf/perf_event.c
deleted file mode 100644
index 7e793eb0c1fe..000000000000
--- a/arch/metag/kernel/perf/perf_event.c
+++ /dev/null
@@ -1,879 +0,0 @@
-/*
- * Meta performance counter support.
- * Copyright (C) 2012 Imagination Technologies Ltd
- *
- * This code is based on the sh pmu code:
- * Copyright (C) 2009 Paul Mundt
- *
- * and on the arm pmu code:
- * Copyright (C) 2009 picoChip Designs, Ltd., James Iles
- * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/atomic.h>
-#include <linux/export.h>
-#include <linux/init.h>
-#include <linux/irqchip/metag.h>
-#include <linux/perf_event.h>
-#include <linux/slab.h>
-
-#include <asm/core_reg.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/processor.h>
-
-#include "perf_event.h"
-
-static int _hw_perf_event_init(struct perf_event *);
-static void _hw_perf_event_destroy(struct perf_event *);
-
-/* Determines which core type we are */
-static struct metag_pmu *metag_pmu __read_mostly;
-
-/* Processor specific data */
-static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-/* PMU admin */
-const char *perf_pmu_name(void)
-{
- if (!metag_pmu)
- return NULL;
-
- return metag_pmu->name;
-}
-EXPORT_SYMBOL_GPL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
- if (metag_pmu)
- return metag_pmu->max_events;
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(perf_num_counters);
-
-static inline int metag_pmu_initialised(void)
-{
- return !!metag_pmu;
-}
-
-static void release_pmu_hardware(void)
-{
- int irq;
- unsigned int version = (metag_pmu->version &
- (METAC_ID_MINOR_BITS | METAC_ID_REV_BITS)) >>
- METAC_ID_REV_S;
-
- /* Early cores don't have overflow interrupts */
- if (version < 0x0104)
- return;
-
- irq = internal_irq_map(17);
- if (irq >= 0)
- free_irq(irq, (void *)1);
-
- irq = internal_irq_map(16);
- if (irq >= 0)
- free_irq(irq, (void *)0);
-}
-
-static int reserve_pmu_hardware(void)
-{
- int err = 0, irq[2];
- unsigned int version = (metag_pmu->version &
- (METAC_ID_MINOR_BITS | METAC_ID_REV_BITS)) >>
- METAC_ID_REV_S;
-
- /* Early cores don't have overflow interrupts */
- if (version < 0x0104)
- goto out;
-
- /*
- * Bit 16 on HWSTATMETA is the interrupt for performance counter 0;
- * similarly, 17 is the interrupt for performance counter 1.
- * We can't (yet) interrupt on the cycle counter, because it's a
- * register, however it holds a 32-bit value as opposed to 24-bit.
- */
- irq[0] = internal_irq_map(16);
- if (irq[0] < 0) {
- pr_err("unable to map internal IRQ %d\n", 16);
- goto out;
- }
- err = request_irq(irq[0], metag_pmu->handle_irq, IRQF_NOBALANCING,
- "metagpmu0", (void *)0);
- if (err) {
- pr_err("unable to request IRQ%d for metag PMU counters\n",
- irq[0]);
- goto out;
- }
-
- irq[1] = internal_irq_map(17);
- if (irq[1] < 0) {
- pr_err("unable to map internal IRQ %d\n", 17);
- goto out_irq1;
- }
- err = request_irq(irq[1], metag_pmu->handle_irq, IRQF_NOBALANCING,
- "metagpmu1", (void *)1);
- if (err) {
- pr_err("unable to request IRQ%d for metag PMU counters\n",
- irq[1]);
- goto out_irq1;
- }
-
- return 0;
-
-out_irq1:
- free_irq(irq[0], (void *)0);
-out:
- return err;
-}
-
-/* PMU operations */
-static void metag_pmu_enable(struct pmu *pmu)
-{
-}
-
-static void metag_pmu_disable(struct pmu *pmu)
-{
-}
-
-static int metag_pmu_event_init(struct perf_event *event)
-{
- int err = 0;
- atomic_t *active_events = &metag_pmu->active_events;
-
- if (!metag_pmu_initialised()) {
- err = -ENODEV;
- goto out;
- }
-
- if (has_branch_stack(event))
- return -EOPNOTSUPP;
-
- event->destroy = _hw_perf_event_destroy;
-
- if (!atomic_inc_not_zero(active_events)) {
- mutex_lock(&metag_pmu->reserve_mutex);
- if (atomic_read(active_events) == 0)
- err = reserve_pmu_hardware();
-
- if (!err)
- atomic_inc(active_events);
-
- mutex_unlock(&metag_pmu->reserve_mutex);
- }
-
- /* Hardware and caches counters */
- switch (event->attr.type) {
- case PERF_TYPE_HARDWARE:
- case PERF_TYPE_HW_CACHE:
- case PERF_TYPE_RAW:
- err = _hw_perf_event_init(event);
- break;
-
- default:
- return -ENOENT;
- }
-
- if (err)
- event->destroy(event);
-
-out:
- return err;
-}
-
-void metag_pmu_event_update(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- u64 prev_raw_count, new_raw_count;
- s64 delta;
-
- /*
- * If this counter is chained, it may be that the previous counter
- * value has been changed beneath us.
- *
- * To get around this, we read and exchange the new raw count, then
- * add the delta (new - prev) to the generic counter atomically.
- *
- * Without interrupts, this is the simplest approach.
- */
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = metag_pmu->read(idx);
-
- if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count)
- goto again;
-
- /*
- * Calculate the delta and add it to the counter.
- */
- delta = (new_raw_count - prev_raw_count) & MAX_PERIOD;
-
- local64_add(delta, &event->count);
- local64_sub(delta, &hwc->period_left);
-}
-
-int metag_pmu_event_set_period(struct perf_event *event,
- struct hw_perf_event *hwc, int idx)
-{
- s64 left = local64_read(&hwc->period_left);
- s64 period = hwc->sample_period;
- int ret = 0;
-
- /* The period may have been changed */
- if (unlikely(period != hwc->last_period))
- left += period - hwc->last_period;
-
- if (unlikely(left <= -period)) {
- left = period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
-
- if (unlikely(left <= 0)) {
- left += period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
-
- if (left > (s64)metag_pmu->max_period)
- left = metag_pmu->max_period;
-
- if (metag_pmu->write) {
- local64_set(&hwc->prev_count, -(s32)left);
- metag_pmu->write(idx, -left & MAX_PERIOD);
- }
-
- perf_event_update_userpage(event);
-
- return ret;
-}
-
-static void metag_pmu_start(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (WARN_ON_ONCE(idx == -1))
- return;
-
- /*
- * We always have to reprogram the period, so ignore PERF_EF_RELOAD.
- */
- if (flags & PERF_EF_RELOAD)
- WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
-
- hwc->state = 0;
-
- /*
- * Reset the period.
- * Some counters can't be stopped (i.e. are core global), so when the
- * counter was 'stopped' we merely disabled the IRQ. If we don't reset
- * the period, then we'll either: a) get an overflow too soon;
- * or b) too late if the overflow happened since disabling.
- * Obviously, this has little bearing on cores without the overflow
- * interrupt, as the performance counter resets to zero on write
- * anyway.
- */
- if (metag_pmu->max_period)
- metag_pmu_event_set_period(event, hwc, hwc->idx);
- cpuc->events[idx] = event;
- metag_pmu->enable(hwc, idx);
-}
-
-static void metag_pmu_stop(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
-
- /*
- * We should always update the counter on stop; see comment above
- * why.
- */
- if (!(hwc->state & PERF_HES_STOPPED)) {
- metag_pmu_event_update(event, hwc, hwc->idx);
- metag_pmu->disable(hwc, hwc->idx);
- hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
- }
-}
-
-static int metag_pmu_add(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = 0, ret = 0;
-
- perf_pmu_disable(event->pmu);
-
- /* check whether we're counting instructions */
- if (hwc->config == 0x100) {
- if (__test_and_set_bit(METAG_INST_COUNTER,
- cpuc->used_mask)) {
- ret = -EAGAIN;
- goto out;
- }
- idx = METAG_INST_COUNTER;
- } else {
- /* Check whether we have a spare counter */
- idx = find_first_zero_bit(cpuc->used_mask,
- atomic_read(&metag_pmu->active_events));
- if (idx >= METAG_INST_COUNTER) {
- ret = -EAGAIN;
- goto out;
- }
-
- __set_bit(idx, cpuc->used_mask);
- }
- hwc->idx = idx;
-
- /* Make sure the counter is disabled */
- metag_pmu->disable(hwc, idx);
-
- hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
- if (flags & PERF_EF_START)
- metag_pmu_start(event, PERF_EF_RELOAD);
-
- perf_event_update_userpage(event);
-out:
- perf_pmu_enable(event->pmu);
- return ret;
-}
-
-static void metag_pmu_del(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- WARN_ON(idx < 0);
- metag_pmu_stop(event, PERF_EF_UPDATE);
- cpuc->events[idx] = NULL;
- __clear_bit(idx, cpuc->used_mask);
-
- perf_event_update_userpage(event);
-}
-
-static void metag_pmu_read(struct perf_event *event)
-{
- struct hw_perf_event *hwc = &event->hw;
-
- /* Don't read disabled counters! */
- if (hwc->idx < 0)
- return;
-
- metag_pmu_event_update(event, hwc, hwc->idx);
-}
-
-static struct pmu pmu = {
- .pmu_enable = metag_pmu_enable,
- .pmu_disable = metag_pmu_disable,
-
- .event_init = metag_pmu_event_init,
-
- .add = metag_pmu_add,
- .del = metag_pmu_del,
- .start = metag_pmu_start,
- .stop = metag_pmu_stop,
- .read = metag_pmu_read,
-};
-
-/* Core counter specific functions */
-static const int metag_general_events[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = 0x03,
- [PERF_COUNT_HW_INSTRUCTIONS] = 0x100,
- [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
- [PERF_COUNT_HW_CACHE_MISSES] = -1,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
- [PERF_COUNT_HW_BRANCH_MISSES] = -1,
- [PERF_COUNT_HW_BUS_CYCLES] = -1,
- [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = -1,
- [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = -1,
- [PERF_COUNT_HW_REF_CPU_CYCLES] = -1,
-};
-
-static const int metag_pmu_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
- [C(L1D)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0x08,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- },
- [C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0x09,
- [C(RESULT_MISS)] = 0x0a,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- },
- [C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- },
- [C(DTLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0xd0,
- [C(RESULT_MISS)] = 0xd2,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = 0xd4,
- [C(RESULT_MISS)] = 0xd5,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- },
- [C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0xd1,
- [C(RESULT_MISS)] = 0xd3,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- },
- [C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- },
- [C(NODE)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
- [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
- },
- },
-};
-
-
-static void _hw_perf_event_destroy(struct perf_event *event)
-{
- atomic_t *active_events = &metag_pmu->active_events;
- struct mutex *pmu_mutex = &metag_pmu->reserve_mutex;
-
- if (atomic_dec_and_mutex_lock(active_events, pmu_mutex)) {
- release_pmu_hardware();
- mutex_unlock(pmu_mutex);
- }
-}
-
-static int _hw_perf_cache_event(int config, int *evp)
-{
- unsigned long type, op, result;
- int ev;
-
- if (!metag_pmu->cache_events)
- return -EINVAL;
-
- /* Unpack config */
- type = config & 0xff;
- op = (config >> 8) & 0xff;
- result = (config >> 16) & 0xff;
-
- if (type >= PERF_COUNT_HW_CACHE_MAX ||
- op >= PERF_COUNT_HW_CACHE_OP_MAX ||
- result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
- return -EINVAL;
-
- ev = (*metag_pmu->cache_events)[type][op][result];
- if (ev == 0)
- return -EOPNOTSUPP;
- if (ev == -1)
- return -EINVAL;
- *evp = ev;
- return 0;
-}
-
-static int _hw_perf_event_init(struct perf_event *event)
-{
- struct perf_event_attr *attr = &event->attr;
- struct hw_perf_event *hwc = &event->hw;
- int mapping = 0, err;
-
- switch (attr->type) {
- case PERF_TYPE_HARDWARE:
- if (attr->config >= PERF_COUNT_HW_MAX)
- return -EINVAL;
-
- mapping = metag_pmu->event_map(attr->config);
- break;
-
- case PERF_TYPE_HW_CACHE:
- err = _hw_perf_cache_event(attr->config, &mapping);
- if (err)
- return err;
- break;
-
- case PERF_TYPE_RAW:
- mapping = attr->config;
- break;
- }
-
- /* Return early if the event is unsupported */
- if (mapping == -1)
- return -EINVAL;
-
- /*
- * Don't assign an index until the event is placed into the hardware.
- * -1 signifies that we're still deciding where to put it. On SMP
- * systems each core has its own set of counters, so we can't do any
- * constraint checking yet.
- */
- hwc->idx = -1;
-
- /* Store the event encoding */
- hwc->config |= (unsigned long)mapping;
-
- /*
- * For non-sampling runs, limit the sample_period to half of the
- * counter width. This way, the new counter value should be less
- * likely to overtake the previous one (unless there are IRQ latency
- * issues...)
- */
- if (metag_pmu->max_period) {
- if (!hwc->sample_period) {
- hwc->sample_period = metag_pmu->max_period >> 1;
- hwc->last_period = hwc->sample_period;
- local64_set(&hwc->period_left, hwc->sample_period);
- }
- }
-
- return 0;
-}
-
-static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
-{
- struct cpu_hw_events *events = this_cpu_ptr(&cpu_hw_events);
- unsigned int config = event->config;
- unsigned int tmp = config & 0xf0;
- unsigned long flags;
-
- raw_spin_lock_irqsave(&events->pmu_lock, flags);
-
- /*
- * Check if we're enabling the instruction counter (index of
- * MAX_HWEVENTS - 1)
- */
- if (METAG_INST_COUNTER == idx) {
- WARN_ONCE((config != 0x100),
- "invalid configuration (%d) for counter (%d)\n",
- config, idx);
- local64_set(&event->prev_count, __core_reg_get(TXTACTCYC));
- goto unlock;
- }
-
- /* Check for a core internal or performance channel event. */
- if (tmp) {
- /* PERF_ICORE/PERF_CHAN only exist since Meta2 */
-#ifdef METAC_2_1
- void *perf_addr;
-
- /*
- * Anything other than a cycle count will write the low-
- * nibble to the correct counter register.
- */
- switch (tmp) {
- case 0xd0:
- perf_addr = (void *)PERF_ICORE(idx);
- break;
-
- case 0xf0:
- perf_addr = (void *)PERF_CHAN(idx);
- break;
-
- default:
- perf_addr = NULL;
- break;
- }
-
- if (perf_addr)
- metag_out32((config & 0x0f), perf_addr);
-#endif
-
- /*
- * Now we use the high nibble as the performance event to
- * to count.
- */
- config = tmp >> 4;
- }
-
- tmp = ((config & 0xf) << 28) |
- ((1 << 24) << hard_processor_id());
- if (metag_pmu->max_period)
- /*
- * Cores supporting overflow interrupts may have had the counter
- * set to a specific value that needs preserving.
- */
- tmp |= metag_in32(PERF_COUNT(idx)) & 0x00ffffff;
- else
- /*
- * Older cores reset the counter on write, so prev_count needs
- * resetting too so we can calculate a correct delta.
- */
- local64_set(&event->prev_count, 0);
-
- metag_out32(tmp, PERF_COUNT(idx));
-unlock:
- raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
-}
-
-static void metag_pmu_disable_counter(struct hw_perf_event *event, int idx)
-{
- struct cpu_hw_events *events = this_cpu_ptr(&cpu_hw_events);
- unsigned int tmp = 0;
- unsigned long flags;
-
- /*
- * The cycle counter can't be disabled per se, as it's a hardware
- * thread register which is always counting. We merely return if this
- * is the counter we're attempting to disable.
- */
- if (METAG_INST_COUNTER == idx)
- return;
-
- /*
- * The counter value _should_ have been read prior to disabling,
- * as if we're running on an early core then the value gets reset to
- * 0, and any read after that would be useless. On the newer cores,
- * however, it's better to read-modify-update this for purposes of
- * the overflow interrupt.
- * Here we remove the thread id AND the event nibble (there are at
- * least two events that count events that are core global and ignore
- * the thread id mask). This only works because we don't mix thread
- * performance counts, and event 0x00 requires a thread id mask!
- */
- raw_spin_lock_irqsave(&events->pmu_lock, flags);
-
- tmp = metag_in32(PERF_COUNT(idx));
- tmp &= 0x00ffffff;
- metag_out32(tmp, PERF_COUNT(idx));
-
- raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
-}
-
-static u64 metag_pmu_read_counter(int idx)
-{
- u32 tmp = 0;
-
- if (METAG_INST_COUNTER == idx) {
- tmp = __core_reg_get(TXTACTCYC);
- goto out;
- }
-
- tmp = metag_in32(PERF_COUNT(idx)) & 0x00ffffff;
-out:
- return tmp;
-}
-
-static void metag_pmu_write_counter(int idx, u32 val)
-{
- struct cpu_hw_events *events = this_cpu_ptr(&cpu_hw_events);
- u32 tmp = 0;
- unsigned long flags;
-
- /*
- * This _shouldn't_ happen, but if it does, then we can just
- * ignore the write, as the register is read-only and clear-on-write.
- */
- if (METAG_INST_COUNTER == idx)
- return;
-
- /*
- * We'll keep the thread mask and event id, and just update the
- * counter itself. Also , we should bound the value to 24-bits.
- */
- raw_spin_lock_irqsave(&events->pmu_lock, flags);
-
- val &= 0x00ffffff;
- tmp = metag_in32(PERF_COUNT(idx)) & 0xff000000;
- val |= tmp;
- metag_out32(val, PERF_COUNT(idx));
-
- raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
-}
-
-static int metag_pmu_event_map(int idx)
-{
- return metag_general_events[idx];
-}
-
-static irqreturn_t metag_pmu_counter_overflow(int irq, void *dev)
-{
- int idx = (int)dev;
- struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
- struct perf_event *event = cpuhw->events[idx];
- struct hw_perf_event *hwc = &event->hw;
- struct pt_regs *regs = get_irq_regs();
- struct perf_sample_data sampledata;
- unsigned long flags;
- u32 counter = 0;
-
- /*
- * We need to stop the core temporarily from generating another
- * interrupt while we disable this counter. However, we don't want
- * to flag the counter as free
- */
- __global_lock2(flags);
- counter = metag_in32(PERF_COUNT(idx));
- metag_out32((counter & 0x00ffffff), PERF_COUNT(idx));
- __global_unlock2(flags);
-
- /* Update the counts and reset the sample period */
- metag_pmu_event_update(event, hwc, idx);
- perf_sample_data_init(&sampledata, 0, hwc->last_period);
- metag_pmu_event_set_period(event, hwc, idx);
-
- /*
- * Enable the counter again once core overflow processing has
- * completed. Note the counter value may have been modified while it was
- * inactive to set it up ready for the next interrupt.
- */
- if (!perf_event_overflow(event, &sampledata, regs)) {
- __global_lock2(flags);
- counter = (counter & 0xff000000) |
- (metag_in32(PERF_COUNT(idx)) & 0x00ffffff);
- metag_out32(counter, PERF_COUNT(idx));
- __global_unlock2(flags);
- }
-
- return IRQ_HANDLED;
-}
-
-static struct metag_pmu _metag_pmu = {
- .handle_irq = metag_pmu_counter_overflow,
- .enable = metag_pmu_enable_counter,
- .disable = metag_pmu_disable_counter,
- .read = metag_pmu_read_counter,
- .write = metag_pmu_write_counter,
- .event_map = metag_pmu_event_map,
- .cache_events = &metag_pmu_cache_events,
- .max_period = MAX_PERIOD,
- .max_events = MAX_HWEVENTS,
-};
-
-/* PMU CPU hotplug notifier */
-static int metag_pmu_starting_cpu(unsigned int cpu)
-{
- struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
-
- memset(cpuc, 0, sizeof(struct cpu_hw_events));
- raw_spin_lock_init(&cpuc->pmu_lock);
-
- return 0;
-}
-
-/* PMU Initialisation */
-static int __init init_hw_perf_events(void)
-{
- int ret = 0, cpu;
- u32 version = *(u32 *)METAC_ID;
- int major = (version & METAC_ID_MAJOR_BITS) >> METAC_ID_MAJOR_S;
- int min_rev = (version & (METAC_ID_MINOR_BITS | METAC_ID_REV_BITS))
- >> METAC_ID_REV_S;
-
- /* Not a Meta 2 core, then not supported */
- if (0x02 > major) {
- pr_info("no hardware counter support available\n");
- goto out;
- } else if (0x02 == major) {
- metag_pmu = &_metag_pmu;
-
- if (min_rev < 0x0104) {
- /*
- * A core without overflow interrupts, and clear-on-
- * write counters.
- */
- metag_pmu->handle_irq = NULL;
- metag_pmu->write = NULL;
- metag_pmu->max_period = 0;
- }
-
- metag_pmu->name = "meta2";
- metag_pmu->version = version;
- metag_pmu->pmu = pmu;
- }
-
- pr_info("enabled with %s PMU driver, %d counters available\n",
- metag_pmu->name, metag_pmu->max_events);
-
- /*
- * Early cores have "limited" counters - they have no overflow
- * interrupts - and so are unable to do sampling without extra work
- * and timer assistance.
- */
- if (metag_pmu->max_period == 0) {
- metag_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
- }
-
- /* Initialise the active events and reservation mutex */
- atomic_set(&metag_pmu->active_events, 0);
- mutex_init(&metag_pmu->reserve_mutex);
-
- /* Clear the counters */
- metag_out32(0, PERF_COUNT(0));
- metag_out32(0, PERF_COUNT(1));
-
- cpuhp_setup_state(CPUHP_AP_PERF_METAG_STARTING,
- "perf/metag:starting", metag_pmu_starting_cpu,
- NULL);
-
- ret = perf_pmu_register(&pmu, metag_pmu->name, PERF_TYPE_RAW);
- if (ret)
- cpuhp_remove_state_nocalls(CPUHP_AP_PERF_METAG_STARTING);
- return ret;
-}
-early_initcall(init_hw_perf_events);
diff --git a/arch/metag/kernel/perf/perf_event.h b/arch/metag/kernel/perf/perf_event.h
deleted file mode 100644
index fd10a1345b67..000000000000
--- a/arch/metag/kernel/perf/perf_event.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Meta performance counter support.
- * Copyright (C) 2012 Imagination Technologies Ltd
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef METAG_PERF_EVENT_H_
-#define METAG_PERF_EVENT_H_
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/perf_event.h>
-
-/* For performance counter definitions */
-#include <asm/metag_mem.h>
-
-/*
- * The Meta core has two performance counters, with 24-bit resolution. Newer
- * cores generate an overflow interrupt on transition from 0xffffff to 0.
- *
- * Each counter consists of the counter id, hardware thread id, and the count
- * itself; each counter can be assigned to multiple hardware threads at any
- * one time, with the returned count being an aggregate of events. A small
- * number of events are thread global, i.e. they count the aggregate of all
- * threads' events, regardless of the thread selected.
- *
- * Newer cores can store an arbitrary 24-bit number in the counter, whereas
- * older cores will clear the counter bits on write.
- *
- * We also have a pseudo-counter in the form of the thread active cycles
- * counter (which, incidentally, is also bound to
- */
-
-#define MAX_HWEVENTS 3
-#define MAX_PERIOD ((1UL << 24) - 1)
-#define METAG_INST_COUNTER (MAX_HWEVENTS - 1)
-
-/**
- * struct cpu_hw_events - a processor core's performance events
- * @events: an array of perf_events active for a given index.
- * @used_mask: a bitmap of in-use counters.
- * @pmu_lock: a perf counter lock
- *
- * This is a per-cpu/core structure that maintains a record of its
- * performance counters' state.
- */
-struct cpu_hw_events {
- struct perf_event *events[MAX_HWEVENTS];
- unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
- raw_spinlock_t pmu_lock;
-};
-
-/**
- * struct metag_pmu - the Meta PMU structure
- * @pmu: core pmu structure
- * @name: pmu name
- * @version: core version
- * @handle_irq: overflow interrupt handler
- * @enable: enable a counter
- * @disable: disable a counter
- * @read: read the value of a counter
- * @write: write a value to a counter
- * @event_map: kernel event to counter event id map
- * @cache_events: kernel cache counter to core cache counter map
- * @max_period: maximum value of the counter before overflow
- * @max_events: maximum number of counters available at any one time
- * @active_events: number of active counters
- * @reserve_mutex: counter reservation mutex
- *
- * This describes the main functionality and data used by the performance
- * event core.
- */
-struct metag_pmu {
- struct pmu pmu;
- const char *name;
- u32 version;
- irqreturn_t (*handle_irq)(int irq_num, void *dev);
- void (*enable)(struct hw_perf_event *evt, int idx);
- void (*disable)(struct hw_perf_event *evt, int idx);
- u64 (*read)(int idx);
- void (*write)(int idx, u32 val);
- int (*event_map)(int idx);
- const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX];
- u32 max_period;
- int max_events;
- atomic_t active_events;
- struct mutex reserve_mutex;
-};
-
-/* Convenience macros for accessing the perf counters */
-/* Define some convenience accessors */
-#define PERF_COUNT(x) (PERF_COUNT0 + (sizeof(u64) * (x)))
-#define PERF_ICORE(x) (PERF_ICORE0 + (sizeof(u64) * (x)))
-#define PERF_CHAN(x) (PERF_CHAN0 + (sizeof(u64) * (x)))
-
-/* Cache index macros */
-#define C(x) PERF_COUNT_HW_CACHE_##x
-#define CACHE_OP_UNSUPPORTED 0xfffe
-#define CACHE_OP_NONSENSE 0xffff
-
-#endif
diff --git a/arch/metag/kernel/perf_callchain.c b/arch/metag/kernel/perf_callchain.c
deleted file mode 100644
index d325ba101de0..000000000000
--- a/arch/metag/kernel/perf_callchain.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Perf callchain handling code.
- *
- * Based on the ARM perf implementation.
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/perf_event.h>
-#include <linux/uaccess.h>
-#include <asm/ptrace.h>
-#include <asm/stacktrace.h>
-
-static bool is_valid_call(unsigned long calladdr)
-{
- unsigned int callinsn;
-
- /* Check the possible return address is aligned. */
- if (!(calladdr & 0x3)) {
- if (!get_user(callinsn, (unsigned int *)calladdr)) {
- /* Check for CALLR or SWAP PC,D1RtP. */
- if ((callinsn & 0xff000000) == 0xab000000 ||
- callinsn == 0xa3200aa0)
- return true;
- }
- }
- return false;
-}
-
-static struct metag_frame __user *
-user_backtrace(struct metag_frame __user *user_frame,
- struct perf_callchain_entry_ctx *entry)
-{
- struct metag_frame frame;
- unsigned long calladdr;
-
- /* We cannot rely on having frame pointers in user code. */
- while (1) {
- /* Also check accessibility of one struct frame beyond */
- if (!access_ok(VERIFY_READ, user_frame, sizeof(frame)))
- return 0;
- if (__copy_from_user_inatomic(&frame, user_frame,
- sizeof(frame)))
- return 0;
-
- --user_frame;
-
- calladdr = frame.lr - 4;
- if (is_valid_call(calladdr)) {
- perf_callchain_store(entry, calladdr);
- return user_frame;
- }
- }
-
- return 0;
-}
-
-void
-perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
-{
- unsigned long sp = regs->ctx.AX[0].U0;
- struct metag_frame __user *frame;
-
- frame = (struct metag_frame __user *)sp;
-
- --frame;
-
- while ((entry->nr < entry->max_stack) && frame)
- frame = user_backtrace(frame, entry);
-}
-
-/*
- * Gets called by walk_stackframe() for every stackframe. This will be called
- * whist unwinding the stackframe and is like a subroutine return so we use
- * the PC.
- */
-static int
-callchain_trace(struct stackframe *fr,
- void *data)
-{
- struct perf_callchain_entry_ctx *entry = data;
- perf_callchain_store(entry, fr->pc);
- return 0;
-}
-
-void
-perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
-{
- struct stackframe fr;
-
- fr.fp = regs->ctx.AX[1].U0;
- fr.sp = regs->ctx.AX[0].U0;
- fr.lr = regs->ctx.DX[4].U1;
- fr.pc = regs->ctx.CurrPC;
- walk_stackframe(&fr, callchain_trace, entry);
-}
diff --git a/arch/metag/kernel/process.c b/arch/metag/kernel/process.c
deleted file mode 100644
index 0909834c83a7..000000000000
--- a/arch/metag/kernel/process.c
+++ /dev/null
@@ -1,448 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2005,2006,2007,2008,2009,2010,2011 Imagination Technologies
- *
- * This file contains the architecture-dependent parts of process handling.
- *
- */
-
-#include <linux/errno.h>
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/reboot.h>
-#include <linux/elfcore.h>
-#include <linux/fs.h>
-#include <linux/tick.h>
-#include <linux/slab.h>
-#include <linux/mman.h>
-#include <linux/pm.h>
-#include <linux/syscalls.h>
-#include <linux/uaccess.h>
-#include <linux/smp.h>
-#include <asm/core_reg.h>
-#include <asm/user_gateway.h>
-#include <asm/tcm.h>
-#include <asm/traps.h>
-#include <asm/switch_to.h>
-
-/*
- * Wait for the next interrupt and enable local interrupts
- */
-void arch_cpu_idle(void)
-{
- int tmp;
-
- /*
- * Quickly jump straight into the interrupt entry point without actually
- * triggering an interrupt. When TXSTATI gets read the processor will
- * block until an interrupt is triggered.
- */
- asm volatile (/* Switch into ISTAT mode */
- "RTH\n\t"
- /* Enable local interrupts */
- "MOV TXMASKI, %1\n\t"
- /*
- * We can't directly "SWAP PC, PCX", so we swap via a
- * temporary. Essentially we do:
- * PCX_new = 1f (the place to continue execution)
- * PC = PCX_old
- */
- "ADD %0, CPC0, #(1f-.)\n\t"
- "SWAP PCX, %0\n\t"
- "MOV PC, %0\n"
- /* Continue execution here with interrupts enabled */
- "1:"
- : "=a" (tmp)
- : "r" (get_trigger_mask()));
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-void arch_cpu_idle_dead(void)
-{
- cpu_die();
-}
-#endif
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-void (*soc_restart)(char *cmd);
-void (*soc_halt)(void);
-
-void machine_restart(char *cmd)
-{
- if (soc_restart)
- soc_restart(cmd);
- hard_processor_halt(HALT_OK);
-}
-
-void machine_halt(void)
-{
- if (soc_halt)
- soc_halt();
- smp_send_stop();
- hard_processor_halt(HALT_OK);
-}
-
-void machine_power_off(void)
-{
- if (pm_power_off)
- pm_power_off();
- smp_send_stop();
- hard_processor_halt(HALT_OK);
-}
-
-#define FLAG_Z 0x8
-#define FLAG_N 0x4
-#define FLAG_O 0x2
-#define FLAG_C 0x1
-
-void show_regs(struct pt_regs *regs)
-{
- int i;
- const char *AX0_names[] = {"A0StP", "A0FrP"};
- const char *AX1_names[] = {"A1GbP", "A1LbP"};
-
- const char *DX0_names[] = {
- "D0Re0",
- "D0Ar6",
- "D0Ar4",
- "D0Ar2",
- "D0FrT",
- "D0.5 ",
- "D0.6 ",
- "D0.7 "
- };
-
- const char *DX1_names[] = {
- "D1Re0",
- "D1Ar5",
- "D1Ar3",
- "D1Ar1",
- "D1RtP",
- "D1.5 ",
- "D1.6 ",
- "D1.7 "
- };
-
- show_regs_print_info(KERN_INFO);
-
- pr_info(" pt_regs @ %p\n", regs);
- pr_info(" SaveMask = 0x%04hx\n", regs->ctx.SaveMask);
- pr_info(" Flags = 0x%04hx (%c%c%c%c)\n", regs->ctx.Flags,
- regs->ctx.Flags & FLAG_Z ? 'Z' : 'z',
- regs->ctx.Flags & FLAG_N ? 'N' : 'n',
- regs->ctx.Flags & FLAG_O ? 'O' : 'o',
- regs->ctx.Flags & FLAG_C ? 'C' : 'c');
- pr_info(" TXRPT = 0x%08x\n", regs->ctx.CurrRPT);
- pr_info(" PC = 0x%08x\n", regs->ctx.CurrPC);
-
- /* AX regs */
- for (i = 0; i < 2; i++) {
- pr_info(" %s = 0x%08x ",
- AX0_names[i],
- regs->ctx.AX[i].U0);
- printk(" %s = 0x%08x\n",
- AX1_names[i],
- regs->ctx.AX[i].U1);
- }
-
- if (regs->ctx.SaveMask & TBICTX_XEXT_BIT)
- pr_warn(" Extended state present - AX2.[01] will be WRONG\n");
-
- /* Special place with AXx.2 */
- pr_info(" A0.2 = 0x%08x ",
- regs->ctx.Ext.AX2.U0);
- printk(" A1.2 = 0x%08x\n",
- regs->ctx.Ext.AX2.U1);
-
- /* 'extended' AX regs (nominally, just AXx.3) */
- for (i = 0; i < (TBICTX_AX_REGS - 3); i++) {
- pr_info(" A0.%d = 0x%08x ", i + 3, regs->ctx.AX3[i].U0);
- printk(" A1.%d = 0x%08x\n", i + 3, regs->ctx.AX3[i].U1);
- }
-
- for (i = 0; i < 8; i++) {
- pr_info(" %s = 0x%08x ", DX0_names[i], regs->ctx.DX[i].U0);
- printk(" %s = 0x%08x\n", DX1_names[i], regs->ctx.DX[i].U1);
- }
-
- show_trace(NULL, (unsigned long *)regs->ctx.AX[0].U0, regs);
-}
-
-/*
- * Copy architecture-specific thread state
- */
-int copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long kthread_arg, struct task_struct *tsk)
-{
- struct pt_regs *childregs = task_pt_regs(tsk);
- void *kernel_context = ((void *) childregs +
- sizeof(struct pt_regs));
- unsigned long global_base;
-
- BUG_ON(((unsigned long)childregs) & 0x7);
- BUG_ON(((unsigned long)kernel_context) & 0x7);
-
- memset(&tsk->thread.kernel_context, 0,
- sizeof(tsk->thread.kernel_context));
-
- tsk->thread.kernel_context = __TBISwitchInit(kernel_context,
- ret_from_fork,
- 0, 0);
-
- if (unlikely(tsk->flags & PF_KTHREAD)) {
- /*
- * Make sure we don't leak any kernel data to child's regs
- * if kernel thread becomes a userspace thread in the future
- */
- memset(childregs, 0 , sizeof(struct pt_regs));
-
- global_base = __core_reg_get(A1GbP);
- childregs->ctx.AX[0].U1 = (unsigned long) global_base;
- childregs->ctx.AX[0].U0 = (unsigned long) kernel_context;
- /* Set D1Ar1=kthread_arg and D1RtP=usp (fn) */
- childregs->ctx.DX[4].U1 = usp;
- childregs->ctx.DX[3].U1 = kthread_arg;
- tsk->thread.int_depth = 2;
- return 0;
- }
-
- /*
- * Get a pointer to where the new child's register block should have
- * been pushed.
- * The Meta's stack grows upwards, and the context is the the first
- * thing to be pushed by TBX (phew)
- */
- *childregs = *current_pt_regs();
- /* Set the correct stack for the clone mode */
- if (usp)
- childregs->ctx.AX[0].U0 = ALIGN(usp, 8);
- tsk->thread.int_depth = 1;
-
- /* set return value for child process */
- childregs->ctx.DX[0].U0 = 0;
-
- /* The TLS pointer is passed as an argument to sys_clone. */
- if (clone_flags & CLONE_SETTLS)
- tsk->thread.tls_ptr =
- (__force void __user *)childregs->ctx.DX[1].U1;
-
-#ifdef CONFIG_METAG_FPU
- if (tsk->thread.fpu_context) {
- struct meta_fpu_context *ctx;
-
- ctx = kmemdup(tsk->thread.fpu_context,
- sizeof(struct meta_fpu_context), GFP_ATOMIC);
- tsk->thread.fpu_context = ctx;
- }
-#endif
-
-#ifdef CONFIG_METAG_DSP
- if (tsk->thread.dsp_context) {
- struct meta_ext_context *ctx;
- int i;
-
- ctx = kmemdup(tsk->thread.dsp_context,
- sizeof(struct meta_ext_context), GFP_ATOMIC);
- for (i = 0; i < 2; i++)
- ctx->ram[i] = kmemdup(ctx->ram[i], ctx->ram_sz[i],
- GFP_ATOMIC);
- tsk->thread.dsp_context = ctx;
- }
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_METAG_FPU
-static void alloc_fpu_context(struct thread_struct *thread)
-{
- thread->fpu_context = kzalloc(sizeof(struct meta_fpu_context),
- GFP_ATOMIC);
-}
-
-static void clear_fpu(struct thread_struct *thread)
-{
- thread->user_flags &= ~TBICTX_FPAC_BIT;
- kfree(thread->fpu_context);
- thread->fpu_context = NULL;
-}
-#else
-static void clear_fpu(struct thread_struct *thread)
-{
-}
-#endif
-
-#ifdef CONFIG_METAG_DSP
-static void clear_dsp(struct thread_struct *thread)
-{
- if (thread->dsp_context) {
- kfree(thread->dsp_context->ram[0]);
- kfree(thread->dsp_context->ram[1]);
-
- kfree(thread->dsp_context);
-
- thread->dsp_context = NULL;
- }
-
- __core_reg_set(D0.8, 0);
-}
-#else
-static void clear_dsp(struct thread_struct *thread)
-{
-}
-#endif
-
-struct task_struct *__sched __switch_to(struct task_struct *prev,
- struct task_struct *next)
-{
- TBIRES to, from;
-
- to.Switch.pCtx = next->thread.kernel_context;
- to.Switch.pPara = prev;
-
-#ifdef CONFIG_METAG_FPU
- if (prev->thread.user_flags & TBICTX_FPAC_BIT) {
- struct pt_regs *regs = task_pt_regs(prev);
- TBIRES state;
-
- state.Sig.SaveMask = prev->thread.user_flags;
- state.Sig.pCtx = &regs->ctx;
-
- if (!prev->thread.fpu_context)
- alloc_fpu_context(&prev->thread);
- if (prev->thread.fpu_context)
- __TBICtxFPUSave(state, prev->thread.fpu_context);
- }
- /*
- * Force a restore of the FPU context next time this process is
- * scheduled.
- */
- if (prev->thread.fpu_context)
- prev->thread.fpu_context->needs_restore = true;
-#endif
-
-
- from = __TBISwitch(to, &prev->thread.kernel_context);
-
- /* Restore TLS pointer for this process. */
- set_gateway_tls(current->thread.tls_ptr);
-
- return (struct task_struct *) from.Switch.pPara;
-}
-
-void flush_thread(void)
-{
- clear_fpu(&current->thread);
- clear_dsp(&current->thread);
-}
-
-/*
- * Free current thread data structures etc.
- */
-void exit_thread(struct task_struct *tsk)
-{
- clear_fpu(&tsk->thread);
- clear_dsp(&tsk->thread);
-}
-
-/* TODO: figure out how to unwind the kernel stack here to figure out
- * where we went to sleep. */
-unsigned long get_wchan(struct task_struct *p)
-{
- return 0;
-}
-
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
-{
- /* Returning 0 indicates that the FPU state was not stored (as it was
- * not in use) */
- return 0;
-}
-
-#ifdef CONFIG_METAG_USER_TCM
-
-#define ELF_MIN_ALIGN PAGE_SIZE
-
-#define ELF_PAGESTART(_v) ((_v) & ~(unsigned long)(ELF_MIN_ALIGN-1))
-#define ELF_PAGEOFFSET(_v) ((_v) & (ELF_MIN_ALIGN-1))
-#define ELF_PAGEALIGN(_v) (((_v) + ELF_MIN_ALIGN - 1) & ~(ELF_MIN_ALIGN - 1))
-
-#define BAD_ADDR(x) ((unsigned long)(x) >= TASK_SIZE)
-
-unsigned long __metag_elf_map(struct file *filep, unsigned long addr,
- struct elf_phdr *eppnt, int prot, int type,
- unsigned long total_size)
-{
- unsigned long map_addr, size;
- unsigned long page_off = ELF_PAGEOFFSET(eppnt->p_vaddr);
- unsigned long raw_size = eppnt->p_filesz + page_off;
- unsigned long off = eppnt->p_offset - page_off;
- unsigned int tcm_tag;
- addr = ELF_PAGESTART(addr);
- size = ELF_PAGEALIGN(raw_size);
-
- /* mmap() will return -EINVAL if given a zero size, but a
- * segment with zero filesize is perfectly valid */
- if (!size)
- return addr;
-
- tcm_tag = tcm_lookup_tag(addr);
-
- if (tcm_tag != TCM_INVALID_TAG)
- type &= ~MAP_FIXED;
-
- /*
- * total_size is the size of the ELF (interpreter) image.
- * The _first_ mmap needs to know the full size, otherwise
- * randomization might put this image into an overlapping
- * position with the ELF binary image. (since size < total_size)
- * So we first map the 'big' image - and unmap the remainder at
- * the end. (which unmap is needed for ELF images with holes.)
- */
- if (total_size) {
- total_size = ELF_PAGEALIGN(total_size);
- map_addr = vm_mmap(filep, addr, total_size, prot, type, off);
- if (!BAD_ADDR(map_addr))
- vm_munmap(map_addr+size, total_size-size);
- } else
- map_addr = vm_mmap(filep, addr, size, prot, type, off);
-
- if (!BAD_ADDR(map_addr) && tcm_tag != TCM_INVALID_TAG) {
- struct tcm_allocation *tcm;
- unsigned long tcm_addr;
-
- tcm = kmalloc(sizeof(*tcm), GFP_KERNEL);
- if (!tcm)
- return -ENOMEM;
-
- tcm_addr = tcm_alloc(tcm_tag, raw_size);
- if (tcm_addr != addr) {
- kfree(tcm);
- return -ENOMEM;
- }
-
- tcm->tag = tcm_tag;
- tcm->addr = tcm_addr;
- tcm->size = raw_size;
-
- list_add(&tcm->list, &current->mm->context.tcm);
-
- eppnt->p_vaddr = map_addr;
- if (copy_from_user((void *) addr, (void __user *) map_addr,
- raw_size))
- return -EFAULT;
- }
-
- return map_addr;
-}
-#endif
diff --git a/arch/metag/kernel/ptrace.c b/arch/metag/kernel/ptrace.c
deleted file mode 100644
index e615603a4b0a..000000000000
--- a/arch/metag/kernel/ptrace.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
- * Copyright (C) 2005-2012 Imagination Technologies Ltd.
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License. See the file COPYING in the main directory of
- * this archive for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/regset.h>
-#include <linux/tracehook.h>
-#include <linux/elf.h>
-#include <linux/uaccess.h>
-#include <linux/sched/task_stack.h>
-
-#include <trace/syscall.h>
-
-#define CREATE_TRACE_POINTS
-#include <trace/events/syscalls.h>
-
-/*
- * user_regset definitions.
- */
-
-static unsigned long user_txstatus(const struct pt_regs *regs)
-{
- unsigned long data = (unsigned long)regs->ctx.Flags;
-
- if (regs->ctx.SaveMask & TBICTX_CBUF_BIT)
- data |= USER_GP_REGS_STATUS_CATCH_BIT;
-
- return data;
-}
-
-int metag_gp_regs_copyout(const struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const void *ptr;
- unsigned long data;
- int ret;
-
- /* D{0-1}.{0-7} */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs->ctx.DX, 0, 4*16);
- if (ret)
- goto out;
- /* A{0-1}.{0-1} */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs->ctx.AX, 4*16, 4*20);
- if (ret)
- goto out;
- /* A{0-1}.2 */
- if (regs->ctx.SaveMask & TBICTX_XEXT_BIT)
- ptr = regs->ctx.Ext.Ctx.pExt;
- else
- ptr = &regs->ctx.Ext.AX2;
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- ptr, 4*20, 4*22);
- if (ret)
- goto out;
- /* A{0-1}.3 */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &regs->ctx.AX3, 4*22, 4*24);
- if (ret)
- goto out;
- /* PC */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &regs->ctx.CurrPC, 4*24, 4*25);
- if (ret)
- goto out;
- /* TXSTATUS */
- data = user_txstatus(regs);
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &data, 4*25, 4*26);
- if (ret)
- goto out;
- /* TXRPT, TXBPOBITS, TXMODE */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &regs->ctx.CurrRPT, 4*26, 4*29);
- if (ret)
- goto out;
- /* Padding */
- ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- 4*29, 4*30);
-out:
- return ret;
-}
-
-int metag_gp_regs_copyin(struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- void *ptr;
- unsigned long data;
- int ret;
-
- /* D{0-1}.{0-7} */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs->ctx.DX, 0, 4*16);
- if (ret)
- goto out;
- /* A{0-1}.{0-1} */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs->ctx.AX, 4*16, 4*20);
- if (ret)
- goto out;
- /* A{0-1}.2 */
- if (regs->ctx.SaveMask & TBICTX_XEXT_BIT)
- ptr = regs->ctx.Ext.Ctx.pExt;
- else
- ptr = &regs->ctx.Ext.AX2;
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- ptr, 4*20, 4*22);
- if (ret)
- goto out;
- /* A{0-1}.3 */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &regs->ctx.AX3, 4*22, 4*24);
- if (ret)
- goto out;
- /* PC */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &regs->ctx.CurrPC, 4*24, 4*25);
- if (ret)
- goto out;
- /* TXSTATUS */
- data = user_txstatus(regs);
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &data, 4*25, 4*26);
- if (ret)
- goto out;
- regs->ctx.Flags = data & 0xffff;
- if (data & USER_GP_REGS_STATUS_CATCH_BIT)
- regs->ctx.SaveMask |= TBICTX_XCBF_BIT | TBICTX_CBUF_BIT;
- else
- regs->ctx.SaveMask &= ~TBICTX_CBUF_BIT;
- /* TXRPT, TXBPOBITS, TXMODE */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &regs->ctx.CurrRPT, 4*26, 4*29);
-out:
- return ret;
-}
-
-static int metag_gp_regs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct pt_regs *regs = task_pt_regs(target);
- return metag_gp_regs_copyout(regs, pos, count, kbuf, ubuf);
-}
-
-static int metag_gp_regs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- return metag_gp_regs_copyin(regs, pos, count, kbuf, ubuf);
-}
-
-int metag_cb_regs_copyout(const struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- int ret;
-
- /* TXCATCH{0-3} */
- if (regs->ctx.SaveMask & TBICTX_XCBF_BIT)
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs->extcb0, 0, 4*4);
- else
- ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- 0, 4*4);
- return ret;
-}
-
-int metag_cb_regs_copyin(struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- int ret;
-
- /* TXCATCH{0-3} */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs->extcb0, 0, 4*4);
- return ret;
-}
-
-static int metag_cb_regs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct pt_regs *regs = task_pt_regs(target);
- return metag_cb_regs_copyout(regs, pos, count, kbuf, ubuf);
-}
-
-static int metag_cb_regs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- return metag_cb_regs_copyin(regs, pos, count, kbuf, ubuf);
-}
-
-int metag_rp_state_copyout(const struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- unsigned long mask;
- u64 *ptr;
- int ret, i;
-
- /* Empty read pipeline */
- if (!(regs->ctx.SaveMask & TBICTX_CBRP_BIT)) {
- ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- 0, 4*13);
- goto out;
- }
-
- mask = (regs->ctx.CurrDIVTIME & TXDIVTIME_RPMASK_BITS) >>
- TXDIVTIME_RPMASK_S;
-
- /* Read pipeline entries */
- ptr = (void *)&regs->extcb0[1];
- for (i = 0; i < 6; ++i, ++ptr) {
- if (mask & (1 << i))
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- ptr, 8*i, 8*(i + 1));
- else
- ret = user_regset_copyout_zero(&pos, &count, &kbuf,
- &ubuf, 8*i, 8*(i + 1));
- if (ret)
- goto out;
- }
- /* Mask of entries */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &mask, 4*12, 4*13);
-out:
- return ret;
-}
-
-int metag_rp_state_copyin(struct pt_regs *regs,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct user_rp_state rp;
- unsigned long long *ptr;
- int ret, i;
-
- if (count < 4*13)
- return -EINVAL;
- /* Read the entire pipeline before making any changes */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &rp, 0, 4*13);
- if (ret)
- goto out;
-
- /* Write pipeline entries */
- ptr = (void *)&regs->extcb0[1];
- for (i = 0; i < 6; ++i, ++ptr)
- if (rp.mask & (1 << i))
- *ptr = rp.entries[i];
-
- /* Update RPMask in TXDIVTIME */
- regs->ctx.CurrDIVTIME &= ~TXDIVTIME_RPMASK_BITS;
- regs->ctx.CurrDIVTIME |= (rp.mask << TXDIVTIME_RPMASK_S)
- & TXDIVTIME_RPMASK_BITS;
-
- /* Set/clear flags to indicate catch/read pipeline state */
- if (rp.mask)
- regs->ctx.SaveMask |= TBICTX_XCBF_BIT | TBICTX_CBRP_BIT;
- else
- regs->ctx.SaveMask &= ~TBICTX_CBRP_BIT;
-out:
- return ret;
-}
-
-static int metag_rp_state_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct pt_regs *regs = task_pt_regs(target);
- return metag_rp_state_copyout(regs, pos, count, kbuf, ubuf);
-}
-
-static int metag_rp_state_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- return metag_rp_state_copyin(regs, pos, count, kbuf, ubuf);
-}
-
-static int metag_tls_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- void __user *tls = target->thread.tls_ptr;
- return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
-}
-
-static int metag_tls_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- int ret;
- void __user *tls = target->thread.tls_ptr;
-
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &tls, 0, -1);
- if (ret)
- return ret;
-
- target->thread.tls_ptr = tls;
- return ret;
-}
-
-enum metag_regset {
- REGSET_GENERAL,
- REGSET_CBUF,
- REGSET_READPIPE,
- REGSET_TLS,
-};
-
-static const struct user_regset metag_regsets[] = {
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = ELF_NGREG,
- .size = sizeof(long),
- .align = sizeof(long long),
- .get = metag_gp_regs_get,
- .set = metag_gp_regs_set,
- },
- [REGSET_CBUF] = {
- .core_note_type = NT_METAG_CBUF,
- .n = sizeof(struct user_cb_regs) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long long),
- .get = metag_cb_regs_get,
- .set = metag_cb_regs_set,
- },
- [REGSET_READPIPE] = {
- .core_note_type = NT_METAG_RPIPE,
- .n = sizeof(struct user_rp_state) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long long),
- .get = metag_rp_state_get,
- .set = metag_rp_state_set,
- },
- [REGSET_TLS] = {
- .core_note_type = NT_METAG_TLS,
- .n = 1,
- .size = sizeof(void *),
- .align = sizeof(void *),
- .get = metag_tls_get,
- .set = metag_tls_set,
- },
-};
-
-static const struct user_regset_view user_metag_view = {
- .name = "metag",
- .e_machine = EM_METAG,
- .regsets = metag_regsets,
- .n = ARRAY_SIZE(metag_regsets)
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_metag_view;
-}
-
-/*
- * Called by kernel/ptrace.c when detaching..
- *
- * Make sure single step bits etc are not set.
- */
-void ptrace_disable(struct task_struct *child)
-{
- /* nothing to do.. */
-}
-
-long arch_ptrace(struct task_struct *child, long request, unsigned long addr,
- unsigned long data)
-{
- int ret;
-
- switch (request) {
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-int syscall_trace_enter(struct pt_regs *regs)
-{
- int ret = 0;
-
- if (test_thread_flag(TIF_SYSCALL_TRACE))
- ret = tracehook_report_syscall_entry(regs);
-
- if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
- trace_sys_enter(regs, regs->ctx.DX[0].U1);
-
- return ret ? -1 : regs->ctx.DX[0].U1;
-}
-
-void syscall_trace_leave(struct pt_regs *regs)
-{
- if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
- trace_sys_exit(regs, regs->ctx.DX[0].U1);
-
- if (test_thread_flag(TIF_SYSCALL_TRACE))
- tracehook_report_syscall_exit(regs, 0);
-}
diff --git a/arch/metag/kernel/setup.c b/arch/metag/kernel/setup.c
deleted file mode 100644
index 1166f1fbfd63..000000000000
--- a/arch/metag/kernel/setup.c
+++ /dev/null
@@ -1,622 +0,0 @@
-/*
- * Copyright (C) 2005-2012 Imagination Technologies Ltd.
- *
- * This file contains the architecture-dependant parts of system setup.
- *
- */
-
-#include <linux/export.h>
-#include <linux/bootmem.h>
-#include <linux/console.h>
-#include <linux/cpu.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/fs.h>
-#include <linux/genhd.h>
-#include <linux/init.h>
-#include <linux/initrd.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/memblock.h>
-#include <linux/mm.h>
-#include <linux/of_fdt.h>
-#include <linux/pfn.h>
-#include <linux/root_dev.h>
-#include <linux/sched.h>
-#include <linux/seq_file.h>
-#include <linux/start_kernel.h>
-#include <linux/string.h>
-
-#include <asm/cachepart.h>
-#include <asm/clock.h>
-#include <asm/core_reg.h>
-#include <asm/cpu.h>
-#include <asm/da.h>
-#include <asm/highmem.h>
-#include <asm/hwthread.h>
-#include <asm/l2cache.h>
-#include <asm/mach/arch.h>
-#include <asm/metag_mem.h>
-#include <asm/metag_regs.h>
-#include <asm/mmu.h>
-#include <asm/mmzone.h>
-#include <asm/processor.h>
-#include <asm/sections.h>
-#include <asm/setup.h>
-#include <asm/traps.h>
-
-/* Priv protect as many registers as possible. */
-#define DEFAULT_PRIV (TXPRIVEXT_COPRO_BITS | \
- TXPRIVEXT_TXTRIGGER_BIT | \
- TXPRIVEXT_TXGBLCREG_BIT | \
- TXPRIVEXT_ILOCK_BIT | \
- TXPRIVEXT_TXITACCYC_BIT | \
- TXPRIVEXT_TXDIVTIME_BIT | \
- TXPRIVEXT_TXAMAREGX_BIT | \
- TXPRIVEXT_TXTIMERI_BIT | \
- TXPRIVEXT_TXSTATUS_BIT | \
- TXPRIVEXT_TXDISABLE_BIT)
-
-/* Meta2 specific bits. */
-#ifdef CONFIG_METAG_META12
-#define META2_PRIV 0
-#else
-#define META2_PRIV (TXPRIVEXT_TXTIMER_BIT | \
- TXPRIVEXT_TRACE_BIT)
-#endif
-
-/* Unaligned access checking bits. */
-#ifdef CONFIG_METAG_UNALIGNED
-#define UNALIGNED_PRIV TXPRIVEXT_ALIGNREW_BIT
-#else
-#define UNALIGNED_PRIV 0
-#endif
-
-#define PRIV_BITS (DEFAULT_PRIV | \
- META2_PRIV | \
- UNALIGNED_PRIV)
-
-/*
- * Protect access to:
- * 0x06000000-0x07ffffff Direct mapped region
- * 0x05000000-0x05ffffff MMU table region (Meta1)
- * 0x04400000-0x047fffff Cache flush region
- * 0x84000000-0x87ffffff Core cache memory region (Meta2)
- *
- * Allow access to:
- * 0x80000000-0x81ffffff Core code memory region (Meta2)
- */
-#ifdef CONFIG_METAG_META12
-#define PRIVSYSR_BITS TXPRIVSYSR_ALL_BITS
-#else
-#define PRIVSYSR_BITS (TXPRIVSYSR_ALL_BITS & ~TXPRIVSYSR_CORECODE_BIT)
-#endif
-
-/* Protect all 0x02xxxxxx and 0x048xxxxx. */
-#define PIOREG_BITS 0xffffffff
-
-/*
- * Protect all 0x04000xx0 (system events)
- * except write combiner flush and write fence (system events 4 and 5).
- */
-#define PSYREG_BITS 0xfffffffb
-
-
-extern char _heap_start[];
-
-#ifdef CONFIG_DA_CONSOLE
-/* Our early channel based console driver */
-extern struct console dash_console;
-#endif
-
-const struct machine_desc *machine_desc __initdata;
-
-/*
- * Map a Linux CPU number to a hardware thread ID
- * In SMP this will be setup with the correct mapping at startup; in UP this
- * will map to the HW thread on which we are running.
- */
-u8 cpu_2_hwthread_id[NR_CPUS] __read_mostly = {
- [0 ... NR_CPUS-1] = BAD_HWTHREAD_ID
-};
-EXPORT_SYMBOL_GPL(cpu_2_hwthread_id);
-
-/*
- * Map a hardware thread ID to a Linux CPU number
- * In SMP this will be fleshed out with the correct CPU ID for a particular
- * hardware thread. In UP this will be initialised with the boot CPU ID.
- */
-u8 hwthread_id_2_cpu[4] __read_mostly = {
- [0 ... 3] = BAD_CPU_ID
-};
-
-/* The relative offset of the MMU mapped memory (from ldlk or bootloader)
- * to the real physical memory. This is needed as we have to use the
- * physical addresses in the MMU tables (pte entries), and not the virtual
- * addresses.
- * This variable is used in the __pa() and __va() macros, and should
- * probably only be used via them.
- */
-unsigned int meta_memoffset;
-EXPORT_SYMBOL(meta_memoffset);
-
-static char __initdata *original_cmd_line;
-
-DEFINE_PER_CPU(PTBI, pTBI);
-
-/*
- * Mapping are specified as "CPU_ID:HWTHREAD_ID", e.g.
- *
- * "hwthread_map=0:1,1:2,2:3,3:0"
- *
- * Linux CPU ID HWTHREAD_ID
- * ---------------------------
- * 0 1
- * 1 2
- * 2 3
- * 3 0
- */
-static int __init parse_hwthread_map(char *p)
-{
- int cpu;
-
- while (*p) {
- cpu = (*p++) - '0';
- if (cpu < 0 || cpu > 9)
- goto err_cpu;
-
- p++; /* skip semi-colon */
- cpu_2_hwthread_id[cpu] = (*p++) - '0';
- if (cpu_2_hwthread_id[cpu] >= 4)
- goto err_thread;
- hwthread_id_2_cpu[cpu_2_hwthread_id[cpu]] = cpu;
-
- if (*p == ',')
- p++; /* skip comma */
- }
-
- return 0;
-err_cpu:
- pr_err("%s: hwthread_map cpu argument out of range\n", __func__);
- return -EINVAL;
-err_thread:
- pr_err("%s: hwthread_map thread argument out of range\n", __func__);
- return -EINVAL;
-}
-early_param("hwthread_map", parse_hwthread_map);
-
-void __init dump_machine_table(void)
-{
- struct machine_desc *p;
- const char **compat;
-
- pr_info("Available machine support:\n\tNAME\t\tCOMPATIBLE LIST\n");
- for_each_machine_desc(p) {
- pr_info("\t%s\t[", p->name);
- for (compat = p->dt_compat; compat && *compat; ++compat)
- printk(" '%s'", *compat);
- printk(" ]\n");
- }
-
- pr_info("\nPlease check your kernel config and/or bootloader.\n");
-
- hard_processor_halt(HALT_PANIC);
-}
-
-#ifdef CONFIG_METAG_HALT_ON_PANIC
-static int metag_panic_event(struct notifier_block *this, unsigned long event,
- void *ptr)
-{
- hard_processor_halt(HALT_PANIC);
- return NOTIFY_DONE;
-}
-
-static struct notifier_block metag_panic_block = {
- metag_panic_event,
- NULL,
- 0
-};
-#endif
-
-void __init setup_arch(char **cmdline_p)
-{
- unsigned long start_pfn;
- unsigned long text_start = (unsigned long)(&_stext);
- unsigned long cpu = smp_processor_id();
- unsigned long heap_start, heap_end;
- unsigned long start_pte;
- PTBI _pTBI;
- PTBISEG p_heap;
- int heap_id, i;
-
- metag_cache_probe();
-
- metag_da_probe();
-#ifdef CONFIG_DA_CONSOLE
- if (metag_da_enabled()) {
- /* An early channel based console driver */
- register_console(&dash_console);
- add_preferred_console("ttyDA", 1, NULL);
- }
-#endif
-
- /* try interpreting the argument as a device tree */
- machine_desc = setup_machine_fdt(original_cmd_line);
- /* if it doesn't look like a device tree it must be a command line */
- if (!machine_desc) {
-#ifdef CONFIG_METAG_BUILTIN_DTB
- /* try the embedded device tree */
- machine_desc = setup_machine_fdt(__dtb_start);
- if (!machine_desc)
- panic("Invalid embedded device tree.");
-#else
- /* use the default machine description */
- machine_desc = default_machine_desc();
-#endif
-#ifndef CONFIG_CMDLINE_FORCE
- /* append the bootloader cmdline to any builtin fdt cmdline */
- if (boot_command_line[0] && original_cmd_line[0])
- strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
- strlcat(boot_command_line, original_cmd_line,
- COMMAND_LINE_SIZE);
-#endif
- }
- setup_meta_clocks(machine_desc->clocks);
-
- *cmdline_p = boot_command_line;
- parse_early_param();
-
- /*
- * Make sure we don't alias in dcache or icache
- */
- check_for_cache_aliasing(cpu);
-
-
-#ifdef CONFIG_METAG_HALT_ON_PANIC
- atomic_notifier_chain_register(&panic_notifier_list,
- &metag_panic_block);
-#endif
-
-#ifdef CONFIG_DUMMY_CONSOLE
- conswitchp = &dummy_con;
-#endif
-
- if (!(__core_reg_get(TXSTATUS) & TXSTATUS_PSTAT_BIT))
- panic("Privilege must be enabled for this thread.");
-
- _pTBI = __TBI(TBID_ISTAT_BIT);
-
- per_cpu(pTBI, cpu) = _pTBI;
-
- if (!per_cpu(pTBI, cpu))
- panic("No TBI found!");
-
- /*
- * Initialize all interrupt vectors to our copy of __TBIUnExpXXX,
- * rather than the version from the bootloader. This makes call
- * stacks easier to understand and may allow us to unmap the
- * bootloader at some point.
- */
- for (i = 0; i <= TBID_SIGNUM_MAX; i++)
- _pTBI->fnSigs[i] = __TBIUnExpXXX;
-
- /* A Meta requirement is that the kernel is loaded (virtually)
- * at the PAGE_OFFSET.
- */
- if (PAGE_OFFSET != text_start)
- panic("Kernel not loaded at PAGE_OFFSET (%#x) but at %#lx.",
- PAGE_OFFSET, text_start);
-
- start_pte = mmu_read_second_level_page(text_start);
-
- /*
- * Kernel pages should have the PRIV bit set by the bootloader.
- */
- if (!(start_pte & _PAGE_KERNEL))
- panic("kernel pte does not have PRIV set");
-
- /*
- * See __pa and __va in include/asm/page.h.
- * This value is negative when running in local space but the
- * calculations work anyway.
- */
- meta_memoffset = text_start - (start_pte & PAGE_MASK);
-
- /* Now lets look at the heap space */
- heap_id = (__TBIThreadId() & TBID_THREAD_BITS)
- + TBID_SEG(0, TBID_SEGSCOPE_LOCAL, TBID_SEGTYPE_HEAP);
-
- p_heap = __TBIFindSeg(NULL, heap_id);
-
- if (!p_heap)
- panic("Could not find heap from TBI!");
-
- /* The heap begins at the first full page after the kernel data. */
- heap_start = (unsigned long) &_heap_start;
-
- /* The heap ends at the end of the heap segment specified with
- * ldlk.
- */
- if (is_global_space(text_start)) {
- pr_debug("WARNING: running in global space!\n");
- heap_end = (unsigned long)p_heap->pGAddr + p_heap->Bytes;
- } else {
- heap_end = (unsigned long)p_heap->pLAddr + p_heap->Bytes;
- }
-
- ROOT_DEV = Root_RAM0;
-
- /* init_mm is the mm struct used for the first task. It is then
- * cloned for all other tasks spawned from that task.
- *
- * Note - we are using the virtual addresses here.
- */
- init_mm.start_code = (unsigned long)(&_stext);
- init_mm.end_code = (unsigned long)(&_etext);
- init_mm.end_data = (unsigned long)(&_edata);
- init_mm.brk = (unsigned long)heap_start;
-
- min_low_pfn = PFN_UP(__pa(text_start));
- max_low_pfn = PFN_DOWN(__pa(heap_end));
-
- pfn_base = min_low_pfn;
-
- /* Round max_pfn up to a 4Mb boundary. The free_bootmem_node()
- * call later makes sure to keep the rounded up pages marked reserved.
- */
- max_pfn = max_low_pfn + ((1 << MAX_ORDER) - 1);
- max_pfn &= ~((1 << MAX_ORDER) - 1);
-
- start_pfn = PFN_UP(__pa(heap_start));
-
- if (min_low_pfn & ((1 << MAX_ORDER) - 1)) {
- /* Theoretically, we could expand the space that the
- * bootmem allocator covers - much as we do for the
- * 'high' address, and then tell the bootmem system
- * that the lowest chunk is 'not available'. Right
- * now it is just much easier to constrain the
- * user to always MAX_ORDER align their kernel space.
- */
-
- panic("Kernel must be %d byte aligned, currently at %#lx.",
- 1 << (MAX_ORDER + PAGE_SHIFT),
- min_low_pfn << PAGE_SHIFT);
- }
-
-#ifdef CONFIG_HIGHMEM
- highstart_pfn = highend_pfn = max_pfn;
- high_memory = (void *) __va(PFN_PHYS(highstart_pfn));
-#else
- high_memory = (void *)__va(PFN_PHYS(max_pfn));
-#endif
-
- paging_init(heap_end);
-
- setup_priv();
-
- /* Setup the boot cpu's mapping. The rest will be setup below. */
- cpu_2_hwthread_id[smp_processor_id()] = hard_processor_id();
- hwthread_id_2_cpu[hard_processor_id()] = smp_processor_id();
-
- unflatten_and_copy_device_tree();
-
-#ifdef CONFIG_SMP
- smp_init_cpus();
-#endif
-
- if (machine_desc->init_early)
- machine_desc->init_early();
-}
-
-static int __init customize_machine(void)
-{
- /* customizes platform devices, or adds new ones */
- if (machine_desc->init_machine)
- machine_desc->init_machine();
-
- return 0;
-}
-arch_initcall(customize_machine);
-
-static int __init init_machine_late(void)
-{
- if (machine_desc->init_late)
- machine_desc->init_late();
- return 0;
-}
-late_initcall(init_machine_late);
-
-#ifdef CONFIG_PROC_FS
-/*
- * Get CPU information for use by the procfs.
- */
-static const char *get_cpu_capabilities(unsigned int txenable)
-{
-#ifdef CONFIG_METAG_META21
- /* See CORE_ID in META HTP.GP TRM - Architecture Overview 2.1.238 */
- int coreid = metag_in32(METAC_CORE_ID);
- unsigned int dsp_type = (coreid >> 3) & 7;
- unsigned int fpu_type = (coreid >> 7) & 3;
-
- switch (dsp_type | fpu_type << 3) {
- case (0x00): return "EDSP";
- case (0x01): return "DSP";
- case (0x08): return "EDSP+LFPU";
- case (0x09): return "DSP+LFPU";
- case (0x10): return "EDSP+FPU";
- case (0x11): return "DSP+FPU";
- }
- return "UNKNOWN";
-
-#else
- if (!(txenable & TXENABLE_CLASS_BITS))
- return "DSP";
- else
- return "";
-#endif
-}
-
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- const char *cpu;
- unsigned int txenable, thread_id, major, minor;
- unsigned long clockfreq = get_coreclock();
-#ifdef CONFIG_SMP
- int i;
- unsigned long lpj;
-#endif
-
- cpu = "META";
-
- txenable = __core_reg_get(TXENABLE);
- major = (txenable & TXENABLE_MAJOR_REV_BITS) >> TXENABLE_MAJOR_REV_S;
- minor = (txenable & TXENABLE_MINOR_REV_BITS) >> TXENABLE_MINOR_REV_S;
- thread_id = (txenable >> 8) & 0x3;
-
-#ifdef CONFIG_SMP
- for_each_online_cpu(i) {
- lpj = per_cpu(cpu_data, i).loops_per_jiffy;
- txenable = core_reg_read(TXUCT_ID, TXENABLE_REGNUM,
- cpu_2_hwthread_id[i]);
-
- seq_printf(m, "CPU:\t\t%s %d.%d (thread %d)\n"
- "Clocking:\t%lu.%1luMHz\n"
- "BogoMips:\t%lu.%02lu\n"
- "Calibration:\t%lu loops\n"
- "Capabilities:\t%s\n\n",
- cpu, major, minor, i,
- clockfreq / 1000000, (clockfreq / 100000) % 10,
- lpj / (500000 / HZ), (lpj / (5000 / HZ)) % 100,
- lpj,
- get_cpu_capabilities(txenable));
- }
-#else
- seq_printf(m, "CPU:\t\t%s %d.%d (thread %d)\n"
- "Clocking:\t%lu.%1luMHz\n"
- "BogoMips:\t%lu.%02lu\n"
- "Calibration:\t%lu loops\n"
- "Capabilities:\t%s\n",
- cpu, major, minor, thread_id,
- clockfreq / 1000000, (clockfreq / 100000) % 10,
- loops_per_jiffy / (500000 / HZ),
- (loops_per_jiffy / (5000 / HZ)) % 100,
- loops_per_jiffy,
- get_cpu_capabilities(txenable));
-#endif /* CONFIG_SMP */
-
-#ifdef CONFIG_METAG_L2C
- if (meta_l2c_is_present()) {
- seq_printf(m, "L2 cache:\t%s\n"
- "L2 cache size:\t%d KB\n",
- meta_l2c_is_enabled() ? "enabled" : "disabled",
- meta_l2c_size() >> 10);
- }
-#endif
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return (void *)(*pos == 0);
-}
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- return NULL;
-}
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-#endif /* CONFIG_PROC_FS */
-
-void __init metag_start_kernel(char *args)
-{
- /* Zero the timer register so timestamps are from the point at
- * which the kernel started running.
- */
- __core_reg_set(TXTIMER, 0);
-
- /* Clear the bss. */
- memset(__bss_start, 0,
- (unsigned long)__bss_stop - (unsigned long)__bss_start);
-
- /* Remember where these are for use in setup_arch */
- original_cmd_line = args;
-
- current_thread_info()->cpu = hard_processor_id();
-
- start_kernel();
-}
-
-/**
- * setup_priv() - Set up privilege protection registers.
- *
- * Set up privilege protection registers such as TXPRIVEXT to prevent userland
- * from touching our precious registers and sensitive memory areas.
- */
-void setup_priv(void)
-{
- unsigned int offset = hard_processor_id() << TXPRIVREG_STRIDE_S;
-
- __core_reg_set(TXPRIVEXT, PRIV_BITS);
-
- metag_out32(PRIVSYSR_BITS, T0PRIVSYSR + offset);
- metag_out32(PIOREG_BITS, T0PIOREG + offset);
- metag_out32(PSYREG_BITS, T0PSYREG + offset);
-}
-
-PTBI pTBI_get(unsigned int cpu)
-{
- return per_cpu(pTBI, cpu);
-}
-EXPORT_SYMBOL(pTBI_get);
-
-#if defined(CONFIG_METAG_DSP) && defined(CONFIG_METAG_FPU)
-static char capabilities[] = "dsp fpu";
-#elif defined(CONFIG_METAG_DSP)
-static char capabilities[] = "dsp";
-#elif defined(CONFIG_METAG_FPU)
-static char capabilities[] = "fpu";
-#else
-static char capabilities[] = "";
-#endif
-
-static struct ctl_table caps_kern_table[] = {
- {
- .procname = "capabilities",
- .data = capabilities,
- .maxlen = sizeof(capabilities),
- .mode = 0444,
- .proc_handler = proc_dostring,
- },
- {}
-};
-
-static struct ctl_table caps_root_table[] = {
- {
- .procname = "kernel",
- .mode = 0555,
- .child = caps_kern_table,
- },
- {}
-};
-
-static int __init capabilities_register_sysctl(void)
-{
- struct ctl_table_header *caps_table_header;
-
- caps_table_header = register_sysctl_table(caps_root_table);
- if (!caps_table_header) {
- pr_err("Unable to register CAPABILITIES sysctl\n");
- return -ENOMEM;
- }
-
- return 0;
-}
-
-core_initcall(capabilities_register_sysctl);
diff --git a/arch/metag/kernel/signal.c b/arch/metag/kernel/signal.c
deleted file mode 100644
index e64e8b0a9363..000000000000
--- a/arch/metag/kernel/signal.c
+++ /dev/null
@@ -1,336 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 1991,1992 Linus Torvalds
- * Copyright (C) 2005-2012 Imagination Technologies Ltd.
- *
- * 1997-11-28 Modified for POSIX.1b signals by Richard Henderson
- *
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/personality.h>
-#include <linux/uaccess.h>
-#include <linux/tracehook.h>
-
-#include <asm/ucontext.h>
-#include <asm/cacheflush.h>
-#include <asm/switch.h>
-#include <asm/syscall.h>
-#include <asm/syscalls.h>
-
-#define REG_FLAGS ctx.SaveMask
-#define REG_RETVAL ctx.DX[0].U0
-#define REG_SYSCALL ctx.DX[0].U1
-#define REG_SP ctx.AX[0].U0
-#define REG_ARG1 ctx.DX[3].U1
-#define REG_ARG2 ctx.DX[3].U0
-#define REG_ARG3 ctx.DX[2].U1
-#define REG_PC ctx.CurrPC
-#define REG_RTP ctx.DX[4].U1
-
-struct rt_sigframe {
- struct siginfo info;
- struct ucontext uc;
- unsigned long retcode[2];
-};
-
-static int restore_sigcontext(struct pt_regs *regs,
- struct sigcontext __user *sc)
-{
- int err;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- err = metag_gp_regs_copyin(regs, 0, sizeof(struct user_gp_regs), NULL,
- &sc->regs);
- if (!err)
- err = metag_cb_regs_copyin(regs, 0,
- sizeof(struct user_cb_regs), NULL,
- &sc->cb);
- if (!err)
- err = metag_rp_state_copyin(regs, 0,
- sizeof(struct user_rp_state), NULL,
- &sc->rp);
-
- /* This is a user-mode context. */
- regs->REG_FLAGS |= TBICTX_PRIV_BIT;
-
- return err;
-}
-
-long sys_rt_sigreturn(void)
-{
- /* NOTE - Meta stack goes UPWARDS - so we wind the stack back */
- struct pt_regs *regs = current_pt_regs();
- struct rt_sigframe __user *frame;
- sigset_t set;
-
- frame = (__force struct rt_sigframe __user *)(regs->REG_SP -
- sizeof(*frame));
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
-
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return regs->REG_RETVAL;
-
-badframe:
- force_sig(SIGSEGV, current);
-
- return 0;
-}
-
-static int setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
- unsigned long mask)
-{
- int err;
-
- err = metag_gp_regs_copyout(regs, 0, sizeof(struct user_gp_regs), NULL,
- &sc->regs);
-
- if (!err)
- err = metag_cb_regs_copyout(regs, 0,
- sizeof(struct user_cb_regs), NULL,
- &sc->cb);
- if (!err)
- err = metag_rp_state_copyout(regs, 0,
- sizeof(struct user_rp_state), NULL,
- &sc->rp);
-
- /* OK, clear that cbuf flag in the old context, or our stored
- * catch buffer will be restored when we go to call the signal
- * handler. Also clear out the CBRP RA/RD pipe bit incase
- * that is pending as well!
- * Note that as we have already stored this context, these
- * flags will get restored on sigreturn to their original
- * state.
- */
- regs->REG_FLAGS &= ~(TBICTX_XCBF_BIT | TBICTX_CBUF_BIT |
- TBICTX_CBRP_BIT);
-
- /* Clear out the LSM_STEP bits in case we are in the middle of
- * and MSET/MGET.
- */
- regs->ctx.Flags &= ~TXSTATUS_LSM_STEP_BITS;
-
- err |= __put_user(mask, &sc->oldmask);
-
- return err;
-}
-
-/*
- * Determine which stack to use..
- */
-static void __user *get_sigframe(struct ksignal *ksig, unsigned long sp)
-{
- sp = sigsp(sp, ksig);
- sp = (sp + 7) & ~7; /* 8byte align stack */
-
- return (void __user *)sp;
-}
-
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct rt_sigframe __user *frame;
- int err;
- unsigned long code;
-
- frame = get_sigframe(ksig, regs->REG_SP);
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- err = copy_siginfo_to_user(&frame->info, &ksig->info);
-
- /* Create the ucontext. */
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(0, (unsigned long __user *)&frame->uc.uc_link);
- err |= __save_altstack(&frame->uc.uc_stack, regs->REG_SP);
- err |= setup_sigcontext(&frame->uc.uc_mcontext,
- regs, set->sig[0]);
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-
- if (err)
- return -EFAULT;
-
- /* Set up to return from userspace. */
-
- /* MOV D1Re0 (D1.0), #__NR_rt_sigreturn */
- code = 0x03000004 | (__NR_rt_sigreturn << 3);
- err |= __put_user(code, (unsigned long __user *)(&frame->retcode[0]));
-
- /* SWITCH #__METAG_SW_SYS */
- code = __METAG_SW_ENCODING(SYS);
- err |= __put_user(code, (unsigned long __user *)(&frame->retcode[1]));
-
- if (err)
- return -EFAULT;
-
- /* Set up registers for signal handler */
- regs->REG_RTP = (unsigned long) frame->retcode;
- regs->REG_SP = (unsigned long) frame + sizeof(*frame);
- regs->REG_ARG1 = ksig->sig;
- regs->REG_ARG2 = (unsigned long) &frame->info;
- regs->REG_ARG3 = (unsigned long) &frame->uc;
- regs->REG_PC = (unsigned long) ksig->ka.sa.sa_handler;
-
- pr_debug("SIG deliver (%s:%d): sp=%p pc=%08x pr=%08x\n",
- current->comm, current->pid, frame, regs->REG_PC,
- regs->REG_RTP);
-
- /* Now pass size of 'new code' into sigtramp so we can do a more
- * effective cache flush - directed rather than 'full flush'.
- */
- flush_cache_sigtramp(regs->REG_RTP, sizeof(frame->retcode));
-
- return 0;
-}
-
-static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Set up the stack frame */
- ret = setup_rt_frame(ksig, oldset, regs);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-}
-
- /*
- * Notes for Meta.
- * We have moved from the old 2.4.9 SH way of using syscall_nr (in the stored
- * context) to passing in the syscall flag on the stack.
- * This is because having syscall_nr in our context does not fit with TBX, and
- * corrupted the stack.
- */
-static int do_signal(struct pt_regs *regs, int syscall)
-{
- unsigned int retval = 0, continue_addr = 0, restart_addr = 0;
- int restart = 0;
- struct ksignal ksig;
-
- /*
- * By the end of rt_sigreturn the context describes the point that the
- * signal was taken (which may happen to be just before a syscall if
- * it's already been restarted). This should *never* be mistaken for a
- * system call in need of restarting.
- */
- if (syscall == __NR_rt_sigreturn)
- syscall = -1;
-
- /* Did we come from a system call? */
- if (syscall >= 0) {
- continue_addr = regs->REG_PC;
- restart_addr = continue_addr - 4;
- retval = regs->REG_RETVAL;
-
- /*
- * Prepare for system call restart. We do this here so that a
- * debugger will see the already changed PC.
- */
- switch (retval) {
- case -ERESTART_RESTARTBLOCK:
- restart = -2;
- case -ERESTARTNOHAND:
- case -ERESTARTSYS:
- case -ERESTARTNOINTR:
- ++restart;
- regs->REG_PC = restart_addr;
- break;
- }
- }
-
- /*
- * Get the signal to deliver. When running under ptrace, at this point
- * the debugger may change all our registers ...
- */
- get_signal(&ksig);
-
- /*
- * Depending on the signal settings we may need to revert the decision
- * to restart the system call. But skip this if a debugger has chosen to
- * restart at a different PC.
- */
- if (regs->REG_PC != restart_addr)
- restart = 0;
- if (ksig.sig > 0) {
- if (unlikely(restart)) {
- if (retval == -ERESTARTNOHAND
- || retval == -ERESTART_RESTARTBLOCK
- || (retval == -ERESTARTSYS
- && !(ksig.ka.sa.sa_flags & SA_RESTART))) {
- regs->REG_RETVAL = -EINTR;
- regs->REG_PC = continue_addr;
- }
- }
-
- /* Whee! Actually deliver the signal. */
- handle_signal(&ksig, regs);
- return 0;
- }
-
- /* Handlerless -ERESTART_RESTARTBLOCK re-enters via restart_syscall */
- if (unlikely(restart < 0))
- regs->REG_SYSCALL = __NR_restart_syscall;
-
- /*
- * If there's no signal to deliver, we just put the saved sigmask back.
- */
- restore_saved_sigmask();
-
- return restart;
-}
-
-int do_work_pending(struct pt_regs *regs, unsigned int thread_flags,
- int syscall)
-{
- do {
- if (likely(thread_flags & _TIF_NEED_RESCHED)) {
- schedule();
- } else {
- if (unlikely(!user_mode(regs)))
- return 0;
- local_irq_enable();
- if (thread_flags & _TIF_SIGPENDING) {
- int restart = do_signal(regs, syscall);
- if (unlikely(restart)) {
- /*
- * Restart without handlers.
- * Deal with it without leaving
- * the kernel space.
- */
- return restart;
- }
- syscall = -1;
- } else {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
- }
- local_irq_disable();
- thread_flags = current_thread_info()->flags;
- } while (thread_flags & _TIF_WORK_MASK);
- return 0;
-}
diff --git a/arch/metag/kernel/smp.c b/arch/metag/kernel/smp.c
deleted file mode 100644
index 2dbbb7c66043..000000000000
--- a/arch/metag/kernel/smp.c
+++ /dev/null
@@ -1,668 +0,0 @@
-/*
- * Copyright (C) 2009,2010,2011 Imagination Technologies Ltd.
- *
- * Copyright (C) 2002 ARM Limited, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/atomic.h>
-#include <linux/completion.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/hotplug.h>
-#include <linux/sched/task_stack.h>
-#include <linux/interrupt.h>
-#include <linux/cache.h>
-#include <linux/profile.h>
-#include <linux/errno.h>
-#include <linux/mm.h>
-#include <linux/err.h>
-#include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#include <linux/bootmem.h>
-
-#include <asm/cacheflush.h>
-#include <asm/cachepart.h>
-#include <asm/core_reg.h>
-#include <asm/cpu.h>
-#include <asm/global_lock.h>
-#include <asm/metag_mem.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/processor.h>
-#include <asm/setup.h>
-#include <asm/tlbflush.h>
-#include <asm/hwthread.h>
-#include <asm/traps.h>
-
-#define SYSC_DCPART(n) (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
-#define SYSC_ICPART(n) (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
-
-DECLARE_PER_CPU(PTBI, pTBI);
-
-void *secondary_data_stack;
-
-/*
- * structures for inter-processor calls
- * - A collection of single bit ipi messages.
- */
-struct ipi_data {
- spinlock_t lock;
- unsigned long ipi_count;
- unsigned long bits;
-};
-
-static DEFINE_PER_CPU(struct ipi_data, ipi_data) = {
- .lock = __SPIN_LOCK_UNLOCKED(ipi_data.lock),
-};
-
-static DEFINE_SPINLOCK(boot_lock);
-
-static DECLARE_COMPLETION(cpu_running);
-
-/*
- * "thread" is assumed to be a valid Meta hardware thread ID.
- */
-static int boot_secondary(unsigned int thread, struct task_struct *idle)
-{
- u32 val;
-
- /*
- * set synchronisation state between this boot processor
- * and the secondary one
- */
- spin_lock(&boot_lock);
-
- core_reg_write(TXUPC_ID, 0, thread, (unsigned int)secondary_startup);
- core_reg_write(TXUPC_ID, 1, thread, 0);
-
- /*
- * Give the thread privilege (PSTAT) and clear potentially problematic
- * bits in the process (namely ISTAT, CBMarker, CBMarkerI, LSM_STEP).
- */
- core_reg_write(TXUCT_ID, TXSTATUS_REGNUM, thread, TXSTATUS_PSTAT_BIT);
-
- /* Clear the minim enable bit. */
- val = core_reg_read(TXUCT_ID, TXPRIVEXT_REGNUM, thread);
- core_reg_write(TXUCT_ID, TXPRIVEXT_REGNUM, thread, val & ~0x80);
-
- /*
- * set the ThreadEnable bit (0x1) in the TXENABLE register
- * for the specified thread - off it goes!
- */
- val = core_reg_read(TXUCT_ID, TXENABLE_REGNUM, thread);
- core_reg_write(TXUCT_ID, TXENABLE_REGNUM, thread, val | 0x1);
-
- /*
- * now the secondary core is starting up let it run its
- * calibrations, then wait for it to finish
- */
- spin_unlock(&boot_lock);
-
- return 0;
-}
-
-/**
- * describe_cachepart_change: describe a change to cache partitions.
- * @thread: Hardware thread number.
- * @label: Label of cache type, e.g. "dcache" or "icache".
- * @sz: Total size of the cache.
- * @old: Old cache partition configuration (*CPART* register).
- * @new: New cache partition configuration (*CPART* register).
- *
- * If the cache partition has changed, prints a message to the log describing
- * those changes.
- */
-static void describe_cachepart_change(unsigned int thread, const char *label,
- unsigned int sz, unsigned int old,
- unsigned int new)
-{
- unsigned int lor1, land1, gor1, gand1;
- unsigned int lor2, land2, gor2, gand2;
- unsigned int diff = old ^ new;
-
- if (!diff)
- return;
-
- pr_info("Thread %d: %s partition changed:", thread, label);
- if (diff & (SYSC_xCPARTL_OR_BITS | SYSC_xCPARTL_AND_BITS)) {
- lor1 = (old & SYSC_xCPARTL_OR_BITS) >> SYSC_xCPARTL_OR_S;
- lor2 = (new & SYSC_xCPARTL_OR_BITS) >> SYSC_xCPARTL_OR_S;
- land1 = (old & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
- land2 = (new & SYSC_xCPARTL_AND_BITS) >> SYSC_xCPARTL_AND_S;
- pr_cont(" L:%#x+%#x->%#x+%#x",
- (lor1 * sz) >> 4,
- ((land1 + 1) * sz) >> 4,
- (lor2 * sz) >> 4,
- ((land2 + 1) * sz) >> 4);
- }
- if (diff & (SYSC_xCPARTG_OR_BITS | SYSC_xCPARTG_AND_BITS)) {
- gor1 = (old & SYSC_xCPARTG_OR_BITS) >> SYSC_xCPARTG_OR_S;
- gor2 = (new & SYSC_xCPARTG_OR_BITS) >> SYSC_xCPARTG_OR_S;
- gand1 = (old & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
- gand2 = (new & SYSC_xCPARTG_AND_BITS) >> SYSC_xCPARTG_AND_S;
- pr_cont(" G:%#x+%#x->%#x+%#x",
- (gor1 * sz) >> 4,
- ((gand1 + 1) * sz) >> 4,
- (gor2 * sz) >> 4,
- ((gand2 + 1) * sz) >> 4);
- }
- if (diff & SYSC_CWRMODE_BIT)
- pr_cont(" %sWR",
- (new & SYSC_CWRMODE_BIT) ? "+" : "-");
- if (diff & SYSC_DCPART_GCON_BIT)
- pr_cont(" %sGCOn",
- (new & SYSC_DCPART_GCON_BIT) ? "+" : "-");
- pr_cont("\n");
-}
-
-/**
- * setup_smp_cache: ensure cache coherency for new SMP thread.
- * @thread: New hardware thread number.
- *
- * Ensures that coherency is enabled and that the threads share the same cache
- * partitions.
- */
-static void setup_smp_cache(unsigned int thread)
-{
- unsigned int this_thread, lflags;
- unsigned int dcsz, dcpart_this, dcpart_old, dcpart_new;
- unsigned int icsz, icpart_old, icpart_new;
-
- /*
- * Copy over the current thread's cache partition configuration to the
- * new thread so that they share cache partitions.
- */
- __global_lock2(lflags);
- this_thread = hard_processor_id();
- /* Share dcache partition */
- dcpart_this = metag_in32(SYSC_DCPART(this_thread));
- dcpart_old = metag_in32(SYSC_DCPART(thread));
- dcpart_new = dcpart_this;
-#if PAGE_OFFSET < LINGLOBAL_BASE
- /*
- * For the local data cache to be coherent the threads must also have
- * GCOn enabled.
- */
- dcpart_new |= SYSC_DCPART_GCON_BIT;
- metag_out32(dcpart_new, SYSC_DCPART(this_thread));
-#endif
- metag_out32(dcpart_new, SYSC_DCPART(thread));
- /* Share icache partition too */
- icpart_new = metag_in32(SYSC_ICPART(this_thread));
- icpart_old = metag_in32(SYSC_ICPART(thread));
- metag_out32(icpart_new, SYSC_ICPART(thread));
- __global_unlock2(lflags);
-
- /*
- * Log if the cache partitions were altered so the user is aware of any
- * potential unintentional cache wastage.
- */
- dcsz = get_dcache_size();
- icsz = get_dcache_size();
- describe_cachepart_change(this_thread, "dcache", dcsz,
- dcpart_this, dcpart_new);
- describe_cachepart_change(thread, "dcache", dcsz,
- dcpart_old, dcpart_new);
- describe_cachepart_change(thread, "icache", icsz,
- icpart_old, icpart_new);
-}
-
-int __cpu_up(unsigned int cpu, struct task_struct *idle)
-{
- unsigned int thread = cpu_2_hwthread_id[cpu];
- int ret;
-
- load_pgd(swapper_pg_dir, thread);
-
- flush_tlb_all();
-
- setup_smp_cache(thread);
-
- /*
- * Tell the secondary CPU where to find its idle thread's stack.
- */
- secondary_data_stack = task_stack_page(idle);
-
- wmb();
-
- /*
- * Now bring the CPU into our world.
- */
- ret = boot_secondary(thread, idle);
- if (ret == 0) {
- /*
- * CPU was successfully started, wait for it
- * to come online or time out.
- */
- wait_for_completion_timeout(&cpu_running,
- msecs_to_jiffies(1000));
-
- if (!cpu_online(cpu))
- ret = -EIO;
- }
-
- secondary_data_stack = NULL;
-
- if (ret) {
- pr_crit("CPU%u: processor failed to boot\n", cpu);
-
- /*
- * FIXME: We need to clean up the new idle thread. --rmk
- */
- }
-
- return ret;
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-/*
- * __cpu_disable runs on the processor to be shutdown.
- */
-int __cpu_disable(void)
-{
- unsigned int cpu = smp_processor_id();
-
- /*
- * Take this CPU offline. Once we clear this, we can't return,
- * and we must not schedule until we're ready to give up the cpu.
- */
- set_cpu_online(cpu, false);
-
- /*
- * OK - migrate IRQs away from this CPU
- */
- migrate_irqs();
-
- /*
- * Flush user cache and TLB mappings, and then remove this CPU
- * from the vm mask set of all processes.
- */
- flush_cache_all();
- local_flush_tlb_all();
-
- clear_tasks_mm_cpumask(cpu);
-
- return 0;
-}
-
-/*
- * called on the thread which is asking for a CPU to be shutdown -
- * waits until shutdown has completed, or it is timed out.
- */
-void __cpu_die(unsigned int cpu)
-{
- if (!cpu_wait_death(cpu, 1))
- pr_err("CPU%u: unable to kill\n", cpu);
-}
-
-/*
- * Called from the idle thread for the CPU which has been shutdown.
- *
- * Note that we do not return from this function. If this cpu is
- * brought online again it will need to run secondary_startup().
- */
-void cpu_die(void)
-{
- local_irq_disable();
- idle_task_exit();
- irq_ctx_exit(smp_processor_id());
-
- (void)cpu_report_death();
-
- asm ("XOR TXENABLE, D0Re0,D0Re0\n");
-}
-#endif /* CONFIG_HOTPLUG_CPU */
-
-/*
- * Called by both boot and secondaries to move global data into
- * per-processor storage.
- */
-void smp_store_cpu_info(unsigned int cpuid)
-{
- struct cpuinfo_metag *cpu_info = &per_cpu(cpu_data, cpuid);
-
- cpu_info->loops_per_jiffy = loops_per_jiffy;
-}
-
-/*
- * This is the secondary CPU boot entry. We're using this CPUs
- * idle thread stack and the global page tables.
- */
-asmlinkage void secondary_start_kernel(void)
-{
- struct mm_struct *mm = &init_mm;
- unsigned int cpu = smp_processor_id();
-
- /*
- * All kernel threads share the same mm context; grab a
- * reference and switch to it.
- */
- mmget(mm);
- mmgrab(mm);
- current->active_mm = mm;
- cpumask_set_cpu(cpu, mm_cpumask(mm));
- enter_lazy_tlb(mm, current);
- local_flush_tlb_all();
-
- /*
- * TODO: Some day it might be useful for each Linux CPU to
- * have its own TBI structure. That would allow each Linux CPU
- * to run different interrupt handlers for the same IRQ
- * number.
- *
- * For now, simply copying the pointer to the boot CPU's TBI
- * structure is sufficient because we always want to run the
- * same interrupt handler whatever CPU takes the interrupt.
- */
- per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT);
-
- if (!per_cpu(pTBI, cpu))
- panic("No TBI found!");
-
- per_cpu_trap_init(cpu);
- irq_ctx_init(cpu);
-
- preempt_disable();
-
- setup_priv();
-
- notify_cpu_starting(cpu);
-
- pr_info("CPU%u (thread %u): Booted secondary processor\n",
- cpu, cpu_2_hwthread_id[cpu]);
-
- calibrate_delay();
- smp_store_cpu_info(cpu);
-
- /*
- * OK, now it's safe to let the boot CPU continue
- */
- set_cpu_online(cpu, true);
- complete(&cpu_running);
-
- /*
- * Enable local interrupts.
- */
- tbi_startup_interrupt(TBID_SIGNUM_TRT);
- local_irq_enable();
-
- /*
- * OK, it's off to the idle thread for us
- */
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
-}
-
-void __init smp_cpus_done(unsigned int max_cpus)
-{
- int cpu;
- unsigned long bogosum = 0;
-
- for_each_online_cpu(cpu)
- bogosum += per_cpu(cpu_data, cpu).loops_per_jiffy;
-
- pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
- num_online_cpus(),
- bogosum / (500000/HZ),
- (bogosum / (5000/HZ)) % 100);
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- unsigned int cpu = smp_processor_id();
-
- init_new_context(current, &init_mm);
- current_thread_info()->cpu = cpu;
-
- smp_store_cpu_info(cpu);
- init_cpu_present(cpu_possible_mask);
-}
-
-void __init smp_prepare_boot_cpu(void)
-{
- unsigned int cpu = smp_processor_id();
-
- per_cpu(pTBI, cpu) = __TBI(TBID_ISTAT_BIT);
-
- if (!per_cpu(pTBI, cpu))
- panic("No TBI found!");
-}
-
-static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg);
-
-static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg)
-{
- unsigned long flags;
- unsigned int cpu;
- cpumask_t map;
-
- cpumask_clear(&map);
- local_irq_save(flags);
-
- for_each_cpu(cpu, mask) {
- struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
-
- spin_lock(&ipi->lock);
-
- /*
- * KICK interrupts are queued in hardware so we'll get
- * multiple interrupts if we call smp_cross_call()
- * multiple times for one msg. The problem is that we
- * only have one bit for each message - we can't queue
- * them in software.
- *
- * The first time through ipi_handler() we'll clear
- * the msg bit, having done all the work. But when we
- * return we'll get _another_ interrupt (and another,
- * and another until we've handled all the queued
- * KICKs). Running ipi_handler() when there's no work
- * to do is bad because that's how kick handler
- * chaining detects who the KICK was intended for.
- * See arch/metag/kernel/kick.c for more details.
- *
- * So only add 'cpu' to 'map' if we haven't already
- * queued a KICK interrupt for 'msg'.
- */
- if (!(ipi->bits & (1 << msg))) {
- ipi->bits |= 1 << msg;
- cpumask_set_cpu(cpu, &map);
- }
-
- spin_unlock(&ipi->lock);
- }
-
- /*
- * Call the platform specific cross-CPU call function.
- */
- smp_cross_call(map, msg);
-
- local_irq_restore(flags);
-}
-
-void arch_send_call_function_ipi_mask(const struct cpumask *mask)
-{
- send_ipi_message(mask, IPI_CALL_FUNC);
-}
-
-void arch_send_call_function_single_ipi(int cpu)
-{
- send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
-}
-
-void show_ipi_list(struct seq_file *p)
-{
- unsigned int cpu;
-
- seq_puts(p, "IPI:");
-
- for_each_present_cpu(cpu)
- seq_printf(p, " %10lu", per_cpu(ipi_data, cpu).ipi_count);
-
- seq_putc(p, '\n');
-}
-
-static DEFINE_SPINLOCK(stop_lock);
-
-/*
- * Main handler for inter-processor interrupts
- *
- * For Meta, the ipimask now only identifies a single
- * category of IPI (Bit 1 IPIs have been replaced by a
- * different mechanism):
- *
- * Bit 0 - Inter-processor function call
- */
-static int do_IPI(void)
-{
- unsigned int cpu = smp_processor_id();
- struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
- unsigned long msgs, nextmsg;
- int handled = 0;
-
- ipi->ipi_count++;
-
- spin_lock(&ipi->lock);
- msgs = ipi->bits;
- nextmsg = msgs & -msgs;
- ipi->bits &= ~nextmsg;
- spin_unlock(&ipi->lock);
-
- if (nextmsg) {
- handled = 1;
-
- nextmsg = ffz(~nextmsg);
- switch (nextmsg) {
- case IPI_RESCHEDULE:
- scheduler_ipi();
- break;
-
- case IPI_CALL_FUNC:
- generic_smp_call_function_interrupt();
- break;
-
- default:
- pr_crit("CPU%u: Unknown IPI message 0x%lx\n",
- cpu, nextmsg);
- break;
- }
- }
-
- return handled;
-}
-
-void smp_send_reschedule(int cpu)
-{
- send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
-}
-
-static void stop_this_cpu(void *data)
-{
- unsigned int cpu = smp_processor_id();
-
- if (system_state <= SYSTEM_RUNNING) {
- spin_lock(&stop_lock);
- pr_crit("CPU%u: stopping\n", cpu);
- dump_stack();
- spin_unlock(&stop_lock);
- }
-
- set_cpu_online(cpu, false);
-
- local_irq_disable();
-
- hard_processor_halt(HALT_OK);
-}
-
-void smp_send_stop(void)
-{
- smp_call_function(stop_this_cpu, NULL, 0);
-}
-
-/*
- * not supported here
- */
-int setup_profiling_timer(unsigned int multiplier)
-{
- return -EINVAL;
-}
-
-/*
- * We use KICKs for inter-processor interrupts.
- *
- * For every CPU in "callmap" the IPI data must already have been
- * stored in that CPU's "ipi_data" member prior to calling this
- * function.
- */
-static void kick_raise_softirq(cpumask_t callmap, unsigned int irq)
-{
- int cpu;
-
- for_each_cpu(cpu, &callmap) {
- unsigned int thread;
-
- thread = cpu_2_hwthread_id[cpu];
-
- BUG_ON(thread == BAD_HWTHREAD_ID);
-
- metag_out32(1, T0KICKI + (thread * TnXKICK_STRIDE));
- }
-}
-
-static TBIRES ipi_handler(TBIRES State, int SigNum, int Triggers,
- int Inst, PTBI pTBI, int *handled)
-{
- *handled = do_IPI();
-
- return State;
-}
-
-static struct kick_irq_handler ipi_irq = {
- .func = ipi_handler,
-};
-
-static void smp_cross_call(cpumask_t callmap, enum ipi_msg_type msg)
-{
- kick_raise_softirq(callmap, 1);
-}
-
-static inline unsigned int get_core_count(void)
-{
- int i;
- unsigned int ret = 0;
-
- for (i = 0; i < CONFIG_NR_CPUS; i++) {
- if (core_reg_read(TXUCT_ID, TXENABLE_REGNUM, i))
- ret++;
- }
-
- return ret;
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-void __init smp_init_cpus(void)
-{
- unsigned int i, ncores = get_core_count();
-
- /* If no hwthread_map early param was set use default mapping */
- for (i = 0; i < NR_CPUS; i++)
- if (cpu_2_hwthread_id[i] == BAD_HWTHREAD_ID) {
- cpu_2_hwthread_id[i] = i;
- hwthread_id_2_cpu[i] = i;
- }
-
- for (i = 0; i < ncores; i++)
- set_cpu_possible(i, true);
-
- kick_register_func(&ipi_irq);
-}
diff --git a/arch/metag/kernel/stacktrace.c b/arch/metag/kernel/stacktrace.c
deleted file mode 100644
index 09d67b7f51ca..000000000000
--- a/arch/metag/kernel/stacktrace.c
+++ /dev/null
@@ -1,187 +0,0 @@
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task_stack.h>
-#include <linux/stacktrace.h>
-
-#include <asm/stacktrace.h>
-
-#if defined(CONFIG_FRAME_POINTER)
-
-#ifdef CONFIG_KALLSYMS
-#include <linux/kallsyms.h>
-#include <linux/module.h>
-
-static unsigned long tbi_boing_addr;
-static unsigned long tbi_boing_size;
-
-static void tbi_boing_init(void)
-{
- /* We need to know where TBIBoingVec is and it's size */
- unsigned long size;
- unsigned long offset;
- char modname[MODULE_NAME_LEN];
- char name[KSYM_NAME_LEN];
- tbi_boing_addr = kallsyms_lookup_name("___TBIBoingVec");
- if (!tbi_boing_addr)
- tbi_boing_addr = 1;
- else if (!lookup_symbol_attrs(tbi_boing_addr, &size,
- &offset, modname, name))
- tbi_boing_size = size;
-}
-#endif
-
-/*
- * Unwind the current stack frame and store the new register values in the
- * structure passed as argument. Unwinding is equivalent to a function return,
- * hence the new PC value rather than LR should be used for backtrace.
- */
-int notrace unwind_frame(struct stackframe *frame)
-{
- struct metag_frame *fp = (struct metag_frame *)frame->fp;
- unsigned long lr;
- unsigned long fpnew;
-
- if (frame->fp & 0x7)
- return -EINVAL;
-
- fpnew = fp->fp;
- lr = fp->lr - 4;
-
-#ifdef CONFIG_KALLSYMS
- /* If we've reached TBIBoingVec then we're at an interrupt
- * entry point or a syscall entry point. The frame pointer
- * points to a pt_regs which can be used to continue tracing on
- * the other side of the boing.
- */
- if (!tbi_boing_addr)
- tbi_boing_init();
- if (tbi_boing_size && lr >= tbi_boing_addr &&
- lr < tbi_boing_addr + tbi_boing_size) {
- struct pt_regs *regs = (struct pt_regs *)fpnew;
- if (user_mode(regs))
- return -EINVAL;
- fpnew = regs->ctx.AX[1].U0;
- lr = regs->ctx.DX[4].U1;
- }
-#endif
-
- /* stack grows up, so frame pointers must decrease */
- if (fpnew < (ALIGN_DOWN((unsigned long)fp, THREAD_SIZE) +
- sizeof(struct thread_info)) || fpnew >= (unsigned long)fp)
- return -EINVAL;
-
- /* restore the registers from the stack frame */
- frame->fp = fpnew;
- frame->pc = lr;
-
- return 0;
-}
-#else
-int notrace unwind_frame(struct stackframe *frame)
-{
- struct metag_frame *sp = (struct metag_frame *)frame->sp;
-
- if (frame->sp & 0x7)
- return -EINVAL;
-
- while (!kstack_end(sp)) {
- unsigned long addr = sp->lr - 4;
- sp--;
-
- if (__kernel_text_address(addr)) {
- frame->sp = (unsigned long)sp;
- frame->pc = addr;
- return 0;
- }
- }
- return -EINVAL;
-}
-#endif
-
-void notrace walk_stackframe(struct stackframe *frame,
- int (*fn)(struct stackframe *, void *), void *data)
-{
- while (1) {
- int ret;
-
- if (fn(frame, data))
- break;
- ret = unwind_frame(frame);
- if (ret < 0)
- break;
- }
-}
-EXPORT_SYMBOL(walk_stackframe);
-
-#ifdef CONFIG_STACKTRACE
-struct stack_trace_data {
- struct stack_trace *trace;
- unsigned int no_sched_functions;
- unsigned int skip;
-};
-
-static int save_trace(struct stackframe *frame, void *d)
-{
- struct stack_trace_data *data = d;
- struct stack_trace *trace = data->trace;
- unsigned long addr = frame->pc;
-
- if (data->no_sched_functions && in_sched_functions(addr))
- return 0;
- if (data->skip) {
- data->skip--;
- return 0;
- }
-
- trace->entries[trace->nr_entries++] = addr;
-
- return trace->nr_entries >= trace->max_entries;
-}
-
-void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
-{
- struct stack_trace_data data;
- struct stackframe frame;
-
- data.trace = trace;
- data.skip = trace->skip;
-
- if (tsk != current) {
-#ifdef CONFIG_SMP
- /*
- * What guarantees do we have here that 'tsk' is not
- * running on another CPU? For now, ignore it as we
- * can't guarantee we won't explode.
- */
- if (trace->nr_entries < trace->max_entries)
- trace->entries[trace->nr_entries++] = ULONG_MAX;
- return;
-#else
- data.no_sched_functions = 1;
- frame.fp = thread_saved_fp(tsk);
- frame.sp = thread_saved_sp(tsk);
- frame.lr = 0; /* recovered from the stack */
- frame.pc = thread_saved_pc(tsk);
-#endif
- } else {
- register unsigned long current_sp asm ("A0StP");
-
- data.no_sched_functions = 0;
- frame.fp = (unsigned long)__builtin_frame_address(0);
- frame.sp = current_sp;
- frame.lr = (unsigned long)__builtin_return_address(0);
- frame.pc = (unsigned long)save_stack_trace_tsk;
- }
-
- walk_stackframe(&frame, save_trace, &data);
- if (trace->nr_entries < trace->max_entries)
- trace->entries[trace->nr_entries++] = ULONG_MAX;
-}
-
-void save_stack_trace(struct stack_trace *trace)
-{
- save_stack_trace_tsk(current, trace);
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
-#endif
diff --git a/arch/metag/kernel/sys_metag.c b/arch/metag/kernel/sys_metag.c
deleted file mode 100644
index 27d96499dd38..000000000000
--- a/arch/metag/kernel/sys_metag.c
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * This file contains various random system calls that
- * have a non-standard calling sequence on the Linux/Meta
- * platform.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/unistd.h>
-#include <asm/cacheflush.h>
-#include <asm/core_reg.h>
-#include <asm/global_lock.h>
-#include <asm/switch.h>
-#include <asm/syscall.h>
-#include <asm/syscalls.h>
-#include <asm/user_gateway.h>
-
-#define merge_64(hi, lo) ((((unsigned long long)(hi)) << 32) + \
- ((lo) & 0xffffffffUL))
-
-int metag_mmap_check(unsigned long addr, unsigned long len,
- unsigned long flags)
-{
- /* We can't have people trying to write to the bottom of the
- * memory map, there are mysterious unspecified things there that
- * we don't want people trampling on.
- */
- if ((flags & MAP_FIXED) && (addr < TASK_UNMAPPED_BASE))
- return -EINVAL;
-
- return 0;
-}
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
- unsigned long prot, unsigned long flags,
- unsigned long fd, unsigned long pgoff)
-{
- /* The shift for mmap2 is constant, regardless of PAGE_SIZE setting. */
- if (pgoff & ((1 << (PAGE_SHIFT - 12)) - 1))
- return -EINVAL;
-
- pgoff >>= PAGE_SHIFT - 12;
-
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
-}
-
-asmlinkage int sys_metag_setglobalbit(char __user *addr, int mask)
-{
- char tmp;
- int ret = 0;
- unsigned int flags;
-
- if (!((__force unsigned int)addr >= LINCORE_BASE))
- return -EFAULT;
-
- __global_lock2(flags);
-
- metag_data_cache_flush((__force void *)addr, sizeof(mask));
-
- ret = __get_user(tmp, addr);
- if (ret)
- goto out;
- tmp |= mask;
- ret = __put_user(tmp, addr);
-
- metag_data_cache_flush((__force void *)addr, sizeof(mask));
-
-out:
- __global_unlock2(flags);
-
- return ret;
-}
-
-#define TXDEFR_FPU_MASK ((0x1f << 16) | 0x1f)
-
-asmlinkage void sys_metag_set_fpu_flags(unsigned int flags)
-{
- unsigned int temp;
-
- flags &= TXDEFR_FPU_MASK;
-
- temp = __core_reg_get(TXDEFR);
- temp &= ~TXDEFR_FPU_MASK;
- temp |= flags;
- __core_reg_set(TXDEFR, temp);
-}
-
-asmlinkage int sys_metag_set_tls(void __user *ptr)
-{
- current->thread.tls_ptr = ptr;
- set_gateway_tls(ptr);
-
- return 0;
-}
-
-asmlinkage void *sys_metag_get_tls(void)
-{
- return (__force void *)current->thread.tls_ptr;
-}
-
-asmlinkage long sys_truncate64_metag(const char __user *path, unsigned long lo,
- unsigned long hi)
-{
- return sys_truncate64(path, merge_64(hi, lo));
-}
-
-asmlinkage long sys_ftruncate64_metag(unsigned int fd, unsigned long lo,
- unsigned long hi)
-{
- return sys_ftruncate64(fd, merge_64(hi, lo));
-}
-
-asmlinkage long sys_fadvise64_64_metag(int fd, unsigned long offs_lo,
- unsigned long offs_hi,
- unsigned long len_lo,
- unsigned long len_hi, int advice)
-{
- return sys_fadvise64_64(fd, merge_64(offs_hi, offs_lo),
- merge_64(len_hi, len_lo), advice);
-}
-
-asmlinkage long sys_readahead_metag(int fd, unsigned long lo, unsigned long hi,
- size_t count)
-{
- return sys_readahead(fd, merge_64(hi, lo), count);
-}
-
-asmlinkage ssize_t sys_pread64_metag(unsigned long fd, char __user *buf,
- size_t count, unsigned long lo,
- unsigned long hi)
-{
- return sys_pread64(fd, buf, count, merge_64(hi, lo));
-}
-
-asmlinkage ssize_t sys_pwrite64_metag(unsigned long fd, char __user *buf,
- size_t count, unsigned long lo,
- unsigned long hi)
-{
- return sys_pwrite64(fd, buf, count, merge_64(hi, lo));
-}
-
-asmlinkage long sys_sync_file_range_metag(int fd, unsigned long offs_lo,
- unsigned long offs_hi,
- unsigned long len_lo,
- unsigned long len_hi,
- unsigned int flags)
-{
- return sys_sync_file_range(fd, merge_64(offs_hi, offs_lo),
- merge_64(len_hi, len_lo), flags);
-}
-
-/* Provide the actual syscall number to call mapping. */
-#undef __SYSCALL
-#define __SYSCALL(nr, call) [nr] = (call),
-
-/*
- * We need wrappers for anything with unaligned 64bit arguments
- */
-#define sys_truncate64 sys_truncate64_metag
-#define sys_ftruncate64 sys_ftruncate64_metag
-#define sys_fadvise64_64 sys_fadvise64_64_metag
-#define sys_readahead sys_readahead_metag
-#define sys_pread64 sys_pread64_metag
-#define sys_pwrite64 sys_pwrite64_metag
-#define sys_sync_file_range sys_sync_file_range_metag
-
-/*
- * Note that we can't include <linux/unistd.h> here since the header
- * guard will defeat us; <asm/unistd.h> checks for __SYSCALL as well.
- */
-const void *sys_call_table[__NR_syscalls] = {
- [0 ... __NR_syscalls-1] = sys_ni_syscall,
-#include <asm/unistd.h>
-};
diff --git a/arch/metag/kernel/tbiunexp.S b/arch/metag/kernel/tbiunexp.S
deleted file mode 100644
index 2664808086c7..000000000000
--- a/arch/metag/kernel/tbiunexp.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Pass a breakpoint through to Codescape */
-
-#include <asm/tbx.h>
-
- .text
- .global ___TBIUnExpXXX
- .type ___TBIUnExpXXX,function
-___TBIUnExpXXX:
- TSTT D0Ar2,#TBICTX_CRIT_BIT ! Result of nestable int call?
- BZ $LTBINormCase ! UnExpXXX at background level
- MOV D0Re0,TXMASKI ! Read TXMASKI
- XOR TXMASKI,D1Re0,D1Re0 ! Turn off BGNDHALT handling!
- OR D0Ar2,D0Ar2,D0Re0 ! Preserve bits cleared
-$LTBINormCase:
- MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2 ! Save args on stack
- SETL [A0StP++],D0Ar2,D1Ar1 ! Init area for returned values
- SWITCH #0xC20208 ! Total stack frame size 8 Dwords
- ! write back size 2 Dwords
- GETL D0Re0,D1Re0,[--A0StP] ! Get result
- SUB A0StP,A0StP,#(8*3) ! Recover stack frame
- MOV PC,D1RtP
- .size ___TBIUnExpXXX,.-___TBIUnExpXXX
diff --git a/arch/metag/kernel/tcm.c b/arch/metag/kernel/tcm.c
deleted file mode 100644
index 1d7b4e33b114..000000000000
--- a/arch/metag/kernel/tcm.c
+++ /dev/null
@@ -1,152 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2010 Imagination Technologies Ltd.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/stddef.h>
-#include <linux/genalloc.h>
-#include <linux/string.h>
-#include <linux/list.h>
-#include <linux/slab.h>
-#include <asm/page.h>
-#include <asm/tcm.h>
-
-struct tcm_pool {
- struct list_head list;
- unsigned int tag;
- unsigned long start;
- unsigned long end;
- struct gen_pool *pool;
-};
-
-static LIST_HEAD(pool_list);
-
-static struct tcm_pool *find_pool(unsigned int tag)
-{
- struct list_head *lh;
- struct tcm_pool *pool;
-
- list_for_each(lh, &pool_list) {
- pool = list_entry(lh, struct tcm_pool, list);
- if (pool->tag == tag)
- return pool;
- }
-
- return NULL;
-}
-
-/**
- * tcm_alloc - allocate memory from a TCM pool
- * @tag: tag of the pool to allocate memory from
- * @len: number of bytes to be allocated
- *
- * Allocate the requested number of bytes from the pool matching
- * the specified tag. Returns the address of the allocated memory
- * or zero on failure.
- */
-unsigned long tcm_alloc(unsigned int tag, size_t len)
-{
- unsigned long vaddr;
- struct tcm_pool *pool;
-
- pool = find_pool(tag);
- if (!pool)
- return 0;
-
- vaddr = gen_pool_alloc(pool->pool, len);
- if (!vaddr)
- return 0;
-
- return vaddr;
-}
-
-/**
- * tcm_free - free a block of memory to a TCM pool
- * @tag: tag of the pool to free memory to
- * @addr: address of the memory to be freed
- * @len: number of bytes to be freed
- *
- * Free the requested number of bytes at a specific address to the
- * pool matching the specified tag.
- */
-void tcm_free(unsigned int tag, unsigned long addr, size_t len)
-{
- struct tcm_pool *pool;
-
- pool = find_pool(tag);
- if (!pool)
- return;
- gen_pool_free(pool->pool, addr, len);
-}
-
-/**
- * tcm_lookup_tag - find the tag matching an address
- * @p: memory address to lookup the tag for
- *
- * Find the tag of the tcm memory region that contains the
- * specified address. Returns %TCM_INVALID_TAG if no such
- * memory region could be found.
- */
-unsigned int tcm_lookup_tag(unsigned long p)
-{
- struct list_head *lh;
- struct tcm_pool *pool;
- unsigned long addr = (unsigned long) p;
-
- list_for_each(lh, &pool_list) {
- pool = list_entry(lh, struct tcm_pool, list);
- if (addr >= pool->start && addr < pool->end)
- return pool->tag;
- }
-
- return TCM_INVALID_TAG;
-}
-
-/**
- * tcm_add_region - add a memory region to TCM pool list
- * @reg: descriptor of region to be added
- *
- * Add a region of memory to the TCM pool list. Returns 0 on success.
- */
-int __init tcm_add_region(struct tcm_region *reg)
-{
- struct tcm_pool *pool;
-
- pool = kmalloc(sizeof(*pool), GFP_KERNEL);
- if (!pool) {
- pr_err("Failed to alloc memory for TCM pool!\n");
- return -ENOMEM;
- }
-
- pool->tag = reg->tag;
- pool->start = reg->res.start;
- pool->end = reg->res.end;
-
- /*
- * 2^3 = 8 bytes granularity to allow for 64bit access alignment.
- * -1 = NUMA node specifier.
- */
- pool->pool = gen_pool_create(3, -1);
-
- if (!pool->pool) {
- pr_err("Failed to create TCM pool!\n");
- kfree(pool);
- return -ENOMEM;
- }
-
- if (gen_pool_add(pool->pool, reg->res.start,
- reg->res.end - reg->res.start + 1, -1)) {
- pr_err("Failed to add memory to TCM pool!\n");
- return -ENOMEM;
- }
- pr_info("Added %s TCM pool (%08x bytes @ %08x)\n",
- reg->res.name, reg->res.end - reg->res.start + 1,
- reg->res.start);
-
- list_add_tail(&pool->list, &pool_list);
-
- return 0;
-}
diff --git a/arch/metag/kernel/time.c b/arch/metag/kernel/time.c
deleted file mode 100644
index 1e809e3b43d1..000000000000
--- a/arch/metag/kernel/time.c
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2005-2013 Imagination Technologies Ltd.
- *
- * This file contains the Meta-specific time handling details.
- *
- */
-
-#include <clocksource/metag_generic.h>
-#include <linux/clk-provider.h>
-#include <linux/init.h>
-#include <asm/clock.h>
-
-void __init time_init(void)
-{
-#ifdef CONFIG_COMMON_CLK
- /* Init clocks from device tree */
- of_clk_init(NULL);
-#endif
-
- /* Init meta clocks, particularly the core clock */
- init_metag_clocks();
-
- /* Set up the timer clock sources */
- metag_generic_timer_init();
-}
diff --git a/arch/metag/kernel/topology.c b/arch/metag/kernel/topology.c
deleted file mode 100644
index 4ba595701f7d..000000000000
--- a/arch/metag/kernel/topology.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (C) 2007 Paul Mundt
- * Copyright (C) 2010 Imagination Technolohies Ltd.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/cpu.h>
-#include <linux/cpumask.h>
-#include <linux/init.h>
-#include <linux/percpu.h>
-#include <linux/node.h>
-#include <linux/nodemask.h>
-#include <linux/topology.h>
-
-#include <asm/cpu.h>
-
-DEFINE_PER_CPU(struct cpuinfo_metag, cpu_data);
-
-cpumask_t cpu_core_map[NR_CPUS];
-EXPORT_SYMBOL(cpu_core_map);
-
-static cpumask_t cpu_coregroup_map(unsigned int cpu)
-{
- return *cpu_possible_mask;
-}
-
-const struct cpumask *cpu_coregroup_mask(unsigned int cpu)
-{
- return &cpu_core_map[cpu];
-}
-
-int arch_update_cpu_topology(void)
-{
- unsigned int cpu;
-
- for_each_possible_cpu(cpu)
- cpu_core_map[cpu] = cpu_coregroup_map(cpu);
-
- return 0;
-}
-
-static int __init topology_init(void)
-{
- int i, ret;
-
-#ifdef CONFIG_NEED_MULTIPLE_NODES
- for_each_online_node(i)
- register_one_node(i);
-#endif
-
- for_each_present_cpu(i) {
- struct cpuinfo_metag *cpuinfo = &per_cpu(cpu_data, i);
-#ifdef CONFIG_HOTPLUG_CPU
- cpuinfo->cpu.hotpluggable = 1;
-#endif
- ret = register_cpu(&cpuinfo->cpu, i);
- if (unlikely(ret))
- pr_warn("%s: register_cpu %d failed (%d)\n",
- __func__, i, ret);
- }
-
-#if defined(CONFIG_NUMA) && !defined(CONFIG_SMP)
- /*
- * In the UP case, make sure the CPU association is still
- * registered under each node. Without this, sysfs fails
- * to make the connection between nodes other than node0
- * and cpu0.
- */
- for_each_online_node(i)
- if (i != numa_node_id())
- register_cpu_under_node(raw_smp_processor_id(), i);
-#endif
-
- return 0;
-}
-subsys_initcall(topology_init);
diff --git a/arch/metag/kernel/traps.c b/arch/metag/kernel/traps.c
deleted file mode 100644
index 3b62b1b0c0b5..000000000000
--- a/arch/metag/kernel/traps.c
+++ /dev/null
@@ -1,992 +0,0 @@
-/*
- * Meta exception handling.
- *
- * Copyright (C) 2005,2006,2007,2008,2009,2012 Imagination Technologies Ltd.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/signal.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/preempt.h>
-#include <linux/ptrace.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/kdebug.h>
-#include <linux/kexec.h>
-#include <linux/unistd.h>
-#include <linux/smp.h>
-#include <linux/slab.h>
-#include <linux/syscalls.h>
-
-#include <asm/bug.h>
-#include <asm/core_reg.h>
-#include <asm/irqflags.h>
-#include <asm/siginfo.h>
-#include <asm/traps.h>
-#include <asm/hwthread.h>
-#include <asm/setup.h>
-#include <asm/switch.h>
-#include <asm/user_gateway.h>
-#include <asm/syscall.h>
-#include <asm/syscalls.h>
-
-/* Passing syscall arguments as long long is quicker. */
-typedef unsigned int (*LPSYSCALL) (unsigned long long,
- unsigned long long,
- unsigned long long);
-
-/*
- * Users of LNKSET should compare the bus error bits obtained from DEFR
- * against TXDEFR_LNKSET_SUCCESS only as the failure code will vary between
- * different cores revisions.
- */
-#define TXDEFR_LNKSET_SUCCESS 0x02000000
-#define TXDEFR_LNKSET_FAILURE 0x04000000
-
-/*
- * Our global TBI handle. Initialised from setup.c/setup_arch.
- */
-DECLARE_PER_CPU(PTBI, pTBI);
-
-#ifdef CONFIG_SMP
-static DEFINE_PER_CPU(unsigned int, trigger_mask);
-#else
-unsigned int global_trigger_mask;
-EXPORT_SYMBOL(global_trigger_mask);
-#endif
-
-unsigned long per_cpu__stack_save[NR_CPUS];
-
-static const char * const trap_names[] = {
- [TBIXXF_SIGNUM_IIF] = "Illegal instruction fault",
- [TBIXXF_SIGNUM_PGF] = "Privilege violation",
- [TBIXXF_SIGNUM_DHF] = "Unaligned data access fault",
- [TBIXXF_SIGNUM_IGF] = "Code fetch general read failure",
- [TBIXXF_SIGNUM_DGF] = "Data access general read/write fault",
- [TBIXXF_SIGNUM_IPF] = "Code fetch page fault",
- [TBIXXF_SIGNUM_DPF] = "Data access page fault",
- [TBIXXF_SIGNUM_IHF] = "Instruction breakpoint",
- [TBIXXF_SIGNUM_DWF] = "Read-only data access fault",
-};
-
-const char *trap_name(int trapno)
-{
- if (trapno >= 0 && trapno < ARRAY_SIZE(trap_names)
- && trap_names[trapno])
- return trap_names[trapno];
- return "Unknown fault";
-}
-
-static DEFINE_SPINLOCK(die_lock);
-
-void __noreturn die(const char *str, struct pt_regs *regs,
- long err, unsigned long addr)
-{
- static int die_counter;
-
- oops_enter();
-
- spin_lock_irq(&die_lock);
- console_verbose();
- bust_spinlocks(1);
- pr_err("%s: err %04lx (%s) addr %08lx [#%d]\n", str, err & 0xffff,
- trap_name(err & 0xffff), addr, ++die_counter);
-
- print_modules();
- show_regs(regs);
-
- pr_err("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
- task_pid_nr(current), task_stack_page(current) + THREAD_SIZE);
-
- bust_spinlocks(0);
- add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
- if (kexec_should_crash(current))
- crash_kexec(regs);
-
- if (in_interrupt())
- panic("Fatal exception in interrupt");
-
- if (panic_on_oops)
- panic("Fatal exception");
-
- spin_unlock_irq(&die_lock);
- oops_exit();
- do_exit(SIGSEGV);
-}
-
-#ifdef CONFIG_METAG_DSP
-/*
- * The ECH encoding specifies the size of a DSPRAM as,
- *
- * "slots" / 4
- *
- * A "slot" is the size of two DSPRAM bank entries; an entry from
- * DSPRAM bank A and an entry from DSPRAM bank B. One DSPRAM bank
- * entry is 4 bytes.
- */
-#define SLOT_SZ 8
-static inline unsigned int decode_dspram_size(unsigned int size)
-{
- unsigned int _sz = size & 0x7f;
-
- return _sz * SLOT_SZ * 4;
-}
-
-static void dspram_save(struct meta_ext_context *dsp_ctx,
- unsigned int ramA_sz, unsigned int ramB_sz)
-{
- unsigned int ram_sz[2];
- int i;
-
- ram_sz[0] = ramA_sz;
- ram_sz[1] = ramB_sz;
-
- for (i = 0; i < 2; i++) {
- if (ram_sz[i] != 0) {
- unsigned int sz;
-
- if (i == 0)
- sz = decode_dspram_size(ram_sz[i] >> 8);
- else
- sz = decode_dspram_size(ram_sz[i]);
-
- if (dsp_ctx->ram[i] == NULL) {
- dsp_ctx->ram[i] = kmalloc(sz, GFP_KERNEL);
-
- if (dsp_ctx->ram[i] == NULL)
- panic("couldn't save DSP context");
- } else {
- if (ram_sz[i] > dsp_ctx->ram_sz[i]) {
- kfree(dsp_ctx->ram[i]);
-
- dsp_ctx->ram[i] = kmalloc(sz,
- GFP_KERNEL);
-
- if (dsp_ctx->ram[i] == NULL)
- panic("couldn't save DSP context");
- }
- }
-
- if (i == 0)
- __TBIDspramSaveA(ram_sz[i], dsp_ctx->ram[i]);
- else
- __TBIDspramSaveB(ram_sz[i], dsp_ctx->ram[i]);
-
- dsp_ctx->ram_sz[i] = ram_sz[i];
- }
- }
-}
-#endif /* CONFIG_METAG_DSP */
-
-/*
- * Allow interrupts to be nested and save any "extended" register
- * context state, e.g. DSP regs and RAMs.
- */
-static void nest_interrupts(TBIRES State, unsigned long mask)
-{
-#ifdef CONFIG_METAG_DSP
- struct meta_ext_context *dsp_ctx;
- unsigned int D0_8;
-
- /*
- * D0.8 may contain an ECH encoding. The upper 16 bits
- * tell us what DSP resources the current process is
- * using. OR the bits into the SaveMask so that
- * __TBINestInts() knows what resources to save as
- * part of this context.
- *
- * Don't save the context if we're nesting interrupts in the
- * kernel because the kernel doesn't use DSP hardware.
- */
- D0_8 = __core_reg_get(D0.8);
-
- if (D0_8 && (State.Sig.SaveMask & TBICTX_PRIV_BIT)) {
- State.Sig.SaveMask |= (D0_8 >> 16);
-
- dsp_ctx = current->thread.dsp_context;
- if (dsp_ctx == NULL) {
- dsp_ctx = kzalloc(sizeof(*dsp_ctx), GFP_KERNEL);
- if (dsp_ctx == NULL)
- panic("couldn't save DSP context: ENOMEM");
-
- current->thread.dsp_context = dsp_ctx;
- }
-
- current->thread.user_flags |= (D0_8 & 0xffff0000);
- __TBINestInts(State, &dsp_ctx->regs, mask);
- dspram_save(dsp_ctx, D0_8 & 0x7f00, D0_8 & 0x007f);
- } else
- __TBINestInts(State, NULL, mask);
-#else
- __TBINestInts(State, NULL, mask);
-#endif
-}
-
-void head_end(TBIRES State, unsigned long mask)
-{
- unsigned int savemask = (unsigned short)State.Sig.SaveMask;
- unsigned int ctx_savemask = (unsigned short)State.Sig.pCtx->SaveMask;
-
- if (savemask & TBICTX_PRIV_BIT) {
- ctx_savemask |= TBICTX_PRIV_BIT;
- current->thread.user_flags = savemask;
- }
-
- /* Always undo the sleep bit */
- ctx_savemask &= ~TBICTX_WAIT_BIT;
-
- /* Always save the catch buffer and RD pipe if they are dirty */
- savemask |= TBICTX_XCBF_BIT;
-
- /* Only save the catch and RD if we have not already done so.
- * Note - the RD bits are in the pCtx only, and not in the
- * State.SaveMask.
- */
- if ((savemask & TBICTX_CBUF_BIT) ||
- (ctx_savemask & TBICTX_CBRP_BIT)) {
- /* Have we already saved the buffers though?
- * - See TestTrack 5071 */
- if (ctx_savemask & TBICTX_XCBF_BIT) {
- /* Strip off the bits so the call to __TBINestInts
- * won't save the buffers again. */
- savemask &= ~TBICTX_CBUF_BIT;
- ctx_savemask &= ~TBICTX_CBRP_BIT;
- }
- }
-
-#ifdef CONFIG_METAG_META21
- {
- unsigned int depth, txdefr;
-
- /*
- * Save TXDEFR state.
- *
- * The process may have been interrupted after a LNKSET, but
- * before it could read the DEFR state, so we mustn't lose that
- * state or it could end up retrying an atomic operation that
- * succeeded.
- *
- * All interrupts are disabled at this point so we
- * don't need to perform any locking. We must do this
- * dance before we use LNKGET or LNKSET.
- */
- BUG_ON(current->thread.int_depth > HARDIRQ_BITS);
-
- depth = current->thread.int_depth++;
-
- txdefr = __core_reg_get(TXDEFR);
-
- txdefr &= TXDEFR_BUS_STATE_BITS;
- if (txdefr & TXDEFR_LNKSET_SUCCESS)
- current->thread.txdefr_failure &= ~(1 << depth);
- else
- current->thread.txdefr_failure |= (1 << depth);
- }
-#endif
-
- State.Sig.SaveMask = savemask;
- State.Sig.pCtx->SaveMask = ctx_savemask;
-
- nest_interrupts(State, mask);
-
-#ifdef CONFIG_METAG_POISON_CATCH_BUFFERS
- /* Poison the catch registers. This shows up any mistakes we have
- * made in their handling MUCH quicker.
- */
- __core_reg_set(TXCATCH0, 0x87650021);
- __core_reg_set(TXCATCH1, 0x87654322);
- __core_reg_set(TXCATCH2, 0x87654323);
- __core_reg_set(TXCATCH3, 0x87654324);
-#endif /* CONFIG_METAG_POISON_CATCH_BUFFERS */
-}
-
-TBIRES tail_end_sys(TBIRES State, int syscall, int *restart)
-{
- struct pt_regs *regs = (struct pt_regs *)State.Sig.pCtx;
- unsigned long flags;
-
- local_irq_disable();
-
- if (user_mode(regs)) {
- flags = current_thread_info()->flags;
- if (flags & _TIF_WORK_MASK &&
- do_work_pending(regs, flags, syscall)) {
- *restart = 1;
- return State;
- }
-
-#ifdef CONFIG_METAG_FPU
- if (current->thread.fpu_context &&
- current->thread.fpu_context->needs_restore) {
- __TBICtxFPURestore(State, current->thread.fpu_context);
- /*
- * Clearing this bit ensures the FP unit is not made
- * active again unless it is used.
- */
- State.Sig.SaveMask &= ~TBICTX_FPAC_BIT;
- current->thread.fpu_context->needs_restore = false;
- }
- State.Sig.TrigMask |= TBI_TRIG_BIT(TBID_SIGNUM_DFR);
-#endif
- }
-
- /* TBI will turn interrupts back on at some point. */
- if (!irqs_disabled_flags((unsigned long)State.Sig.TrigMask))
- trace_hardirqs_on();
-
-#ifdef CONFIG_METAG_DSP
- /*
- * If we previously saved an extended context then restore it
- * now. Otherwise, clear D0.8 because this process is not
- * using DSP hardware.
- */
- if (State.Sig.pCtx->SaveMask & TBICTX_XEXT_BIT) {
- unsigned int D0_8;
- struct meta_ext_context *dsp_ctx = current->thread.dsp_context;
-
- /* Make sure we're going to return to userland. */
- BUG_ON(current->thread.int_depth != 1);
-
- if (dsp_ctx->ram_sz[0] > 0)
- __TBIDspramRestoreA(dsp_ctx->ram_sz[0],
- dsp_ctx->ram[0]);
- if (dsp_ctx->ram_sz[1] > 0)
- __TBIDspramRestoreB(dsp_ctx->ram_sz[1],
- dsp_ctx->ram[1]);
-
- State.Sig.SaveMask |= State.Sig.pCtx->SaveMask;
- __TBICtxRestore(State, current->thread.dsp_context);
- D0_8 = __core_reg_get(D0.8);
- D0_8 |= current->thread.user_flags & 0xffff0000;
- D0_8 |= (dsp_ctx->ram_sz[1] | dsp_ctx->ram_sz[0]) & 0xffff;
- __core_reg_set(D0.8, D0_8);
- } else
- __core_reg_set(D0.8, 0);
-#endif /* CONFIG_METAG_DSP */
-
-#ifdef CONFIG_METAG_META21
- {
- unsigned int depth, txdefr;
-
- /*
- * If there hasn't been a LNKSET since the last LNKGET then the
- * link flag will be set, causing the next LNKSET to succeed if
- * the addresses match. The two LNK operations may not be a pair
- * (e.g. see atomic_read()), so the LNKSET should fail.
- * We use a conditional-never LNKSET to clear the link flag
- * without side effects.
- */
- asm volatile("LNKSETDNV [D0Re0],D0Re0");
-
- depth = --current->thread.int_depth;
-
- BUG_ON(user_mode(regs) && depth);
-
- txdefr = __core_reg_get(TXDEFR);
-
- txdefr &= ~TXDEFR_BUS_STATE_BITS;
-
- /* Do we need to restore a failure code into TXDEFR? */
- if (current->thread.txdefr_failure & (1 << depth))
- txdefr |= (TXDEFR_LNKSET_FAILURE | TXDEFR_BUS_TRIG_BIT);
- else
- txdefr |= (TXDEFR_LNKSET_SUCCESS | TXDEFR_BUS_TRIG_BIT);
-
- __core_reg_set(TXDEFR, txdefr);
- }
-#endif
- return State;
-}
-
-#ifdef CONFIG_SMP
-/*
- * If we took an interrupt in the middle of __kuser_get_tls then we need
- * to rewind the PC to the start of the function in case the process
- * gets migrated to another thread (SMP only) and it reads the wrong tls
- * data.
- */
-static inline void _restart_critical_section(TBIRES State)
-{
- unsigned long get_tls_start;
- unsigned long get_tls_end;
-
- get_tls_start = (unsigned long)__kuser_get_tls -
- (unsigned long)&__user_gateway_start;
-
- get_tls_start += USER_GATEWAY_PAGE;
-
- get_tls_end = (unsigned long)__kuser_get_tls_end -
- (unsigned long)&__user_gateway_start;
-
- get_tls_end += USER_GATEWAY_PAGE;
-
- if ((State.Sig.pCtx->CurrPC >= get_tls_start) &&
- (State.Sig.pCtx->CurrPC < get_tls_end))
- State.Sig.pCtx->CurrPC = get_tls_start;
-}
-#else
-/*
- * If we took an interrupt in the middle of
- * __kuser_cmpxchg then we need to rewind the PC to the
- * start of the function.
- */
-static inline void _restart_critical_section(TBIRES State)
-{
- unsigned long cmpxchg_start;
- unsigned long cmpxchg_end;
-
- cmpxchg_start = (unsigned long)__kuser_cmpxchg -
- (unsigned long)&__user_gateway_start;
-
- cmpxchg_start += USER_GATEWAY_PAGE;
-
- cmpxchg_end = (unsigned long)__kuser_cmpxchg_end -
- (unsigned long)&__user_gateway_start;
-
- cmpxchg_end += USER_GATEWAY_PAGE;
-
- if ((State.Sig.pCtx->CurrPC >= cmpxchg_start) &&
- (State.Sig.pCtx->CurrPC < cmpxchg_end))
- State.Sig.pCtx->CurrPC = cmpxchg_start;
-}
-#endif
-
-/* Used by kick_handler() */
-void restart_critical_section(TBIRES State)
-{
- _restart_critical_section(State);
-}
-
-TBIRES trigger_handler(TBIRES State, int SigNum, int Triggers, int Inst,
- PTBI pTBI)
-{
- head_end(State, ~INTS_OFF_MASK);
-
- /* If we interrupted user code handle any critical sections. */
- if (State.Sig.SaveMask & TBICTX_PRIV_BIT)
- _restart_critical_section(State);
-
- trace_hardirqs_off();
-
- do_IRQ(SigNum, (struct pt_regs *)State.Sig.pCtx);
-
- return tail_end(State);
-}
-
-static unsigned int load_fault(PTBICTXEXTCB0 pbuf)
-{
- return pbuf->CBFlags & TXCATCH0_READ_BIT;
-}
-
-static unsigned long fault_address(PTBICTXEXTCB0 pbuf)
-{
- return pbuf->CBAddr;
-}
-
-static void unhandled_fault(struct pt_regs *regs, unsigned long addr,
- int signo, int code, int trapno)
-{
- if (user_mode(regs)) {
- siginfo_t info;
-
- if (show_unhandled_signals && unhandled_signal(current, signo)
- && printk_ratelimit()) {
-
- pr_info("pid %d unhandled fault: pc 0x%08x, addr 0x%08lx, trap %d (%s)\n",
- current->pid, regs->ctx.CurrPC, addr,
- trapno, trap_name(trapno));
- print_vma_addr(" in ", regs->ctx.CurrPC);
- print_vma_addr(" rtp in ", regs->ctx.DX[4].U1);
- printk("\n");
- show_regs(regs);
- }
-
- info.si_signo = signo;
- info.si_errno = 0;
- info.si_code = code;
- info.si_addr = (__force void __user *)addr;
- info.si_trapno = trapno;
- force_sig_info(signo, &info, current);
- } else {
- die("Oops", regs, trapno, addr);
- }
-}
-
-static int handle_data_fault(PTBICTXEXTCB0 pcbuf, struct pt_regs *regs,
- unsigned int data_address, int trapno)
-{
- int ret;
-
- ret = do_page_fault(regs, data_address, !load_fault(pcbuf), trapno);
-
- return ret;
-}
-
-static unsigned long get_inst_fault_address(struct pt_regs *regs)
-{
- return regs->ctx.CurrPC;
-}
-
-TBIRES fault_handler(TBIRES State, int SigNum, int Triggers,
- int Inst, PTBI pTBI)
-{
- struct pt_regs *regs = (struct pt_regs *)State.Sig.pCtx;
- PTBICTXEXTCB0 pcbuf = (PTBICTXEXTCB0)&regs->extcb0;
- unsigned long data_address;
-
- head_end(State, ~INTS_OFF_MASK);
-
- /* Hardware breakpoint or data watch */
- if ((SigNum == TBIXXF_SIGNUM_IHF) ||
- ((SigNum == TBIXXF_SIGNUM_DHF) &&
- (pcbuf[0].CBFlags & (TXCATCH0_WATCH1_BIT |
- TXCATCH0_WATCH0_BIT)))) {
- State = __TBIUnExpXXX(State, SigNum, Triggers, Inst,
- pTBI);
- return tail_end(State);
- }
-
- local_irq_enable();
-
- data_address = fault_address(pcbuf);
-
- switch (SigNum) {
- case TBIXXF_SIGNUM_IGF:
- /* 1st-level entry invalid (instruction fetch) */
- case TBIXXF_SIGNUM_IPF: {
- /* 2nd-level entry invalid (instruction fetch) */
- unsigned long addr = get_inst_fault_address(regs);
- do_page_fault(regs, addr, 0, SigNum);
- break;
- }
-
- case TBIXXF_SIGNUM_DGF:
- /* 1st-level entry invalid (data access) */
- case TBIXXF_SIGNUM_DPF:
- /* 2nd-level entry invalid (data access) */
- case TBIXXF_SIGNUM_DWF:
- /* Write to read only page */
- handle_data_fault(pcbuf, regs, data_address, SigNum);
- break;
-
- case TBIXXF_SIGNUM_IIF:
- /* Illegal instruction */
- unhandled_fault(regs, regs->ctx.CurrPC, SIGILL, ILL_ILLOPC,
- SigNum);
- break;
-
- case TBIXXF_SIGNUM_DHF:
- /* Unaligned access */
- unhandled_fault(regs, data_address, SIGBUS, BUS_ADRALN,
- SigNum);
- break;
- case TBIXXF_SIGNUM_PGF:
- /* Privilege violation */
- unhandled_fault(regs, data_address, SIGSEGV, SEGV_ACCERR,
- SigNum);
- break;
- default:
- BUG();
- break;
- }
-
- return tail_end(State);
-}
-
-static bool switch_is_syscall(unsigned int inst)
-{
- return inst == __METAG_SW_ENCODING(SYS);
-}
-
-static bool switch_is_legacy_syscall(unsigned int inst)
-{
- return inst == __METAG_SW_ENCODING(SYS_LEGACY);
-}
-
-static inline void step_over_switch(struct pt_regs *regs, unsigned int inst)
-{
- regs->ctx.CurrPC += 4;
-}
-
-static inline int test_syscall_work(void)
-{
- return current_thread_info()->flags & _TIF_WORK_SYSCALL_MASK;
-}
-
-TBIRES switch1_handler(TBIRES State, int SigNum, int Triggers,
- int Inst, PTBI pTBI)
-{
- struct pt_regs *regs = (struct pt_regs *)State.Sig.pCtx;
- unsigned int sysnumber;
- unsigned long long a1_a2, a3_a4, a5_a6;
- LPSYSCALL syscall_entry;
- int restart;
-
- head_end(State, ~INTS_OFF_MASK);
-
- /*
- * If this is not a syscall SWITCH it could be a breakpoint.
- */
- if (!switch_is_syscall(Inst)) {
- /*
- * Alert the user if they're trying to use legacy system
- * calls. This suggests they need to update their C
- * library and build against up to date kernel headers.
- */
- if (switch_is_legacy_syscall(Inst))
- pr_warn_once("WARNING: A legacy syscall was made. Your userland needs updating.\n");
- /*
- * We don't know how to handle the SWITCH and cannot
- * safely ignore it, so treat all unknown switches
- * (including breakpoints) as traps.
- */
- force_sig(SIGTRAP, current);
- return tail_end(State);
- }
-
- local_irq_enable();
-
-restart_syscall:
- restart = 0;
- sysnumber = regs->ctx.DX[0].U1;
-
- if (test_syscall_work())
- sysnumber = syscall_trace_enter(regs);
-
- /* Skip over the SWITCH instruction - or you just get 'stuck' on it! */
- step_over_switch(regs, Inst);
-
- if (sysnumber >= __NR_syscalls) {
- pr_debug("unknown syscall number: %d\n", sysnumber);
- syscall_entry = (LPSYSCALL) sys_ni_syscall;
- } else {
- syscall_entry = (LPSYSCALL) sys_call_table[sysnumber];
- }
-
- /* Use 64bit loads for speed. */
- a5_a6 = *(unsigned long long *)&regs->ctx.DX[1];
- a3_a4 = *(unsigned long long *)&regs->ctx.DX[2];
- a1_a2 = *(unsigned long long *)&regs->ctx.DX[3];
-
- /* here is the actual call to the syscall handler functions */
- regs->ctx.DX[0].U0 = syscall_entry(a1_a2, a3_a4, a5_a6);
-
- if (test_syscall_work())
- syscall_trace_leave(regs);
-
- State = tail_end_sys(State, sysnumber, &restart);
- /* Handlerless restarts shouldn't go via userland */
- if (restart)
- goto restart_syscall;
- return State;
-}
-
-TBIRES switchx_handler(TBIRES State, int SigNum, int Triggers,
- int Inst, PTBI pTBI)
-{
- struct pt_regs *regs = (struct pt_regs *)State.Sig.pCtx;
-
- /*
- * This can be caused by any user process simply executing an unusual
- * SWITCH instruction. If there's no DA, __TBIUnExpXXX will cause the
- * thread to stop, so signal a SIGTRAP instead.
- */
- head_end(State, ~INTS_OFF_MASK);
- if (user_mode(regs))
- force_sig(SIGTRAP, current);
- else
- State = __TBIUnExpXXX(State, SigNum, Triggers, Inst, pTBI);
- return tail_end(State);
-}
-
-#ifdef CONFIG_METAG_META21
-TBIRES fpe_handler(TBIRES State, int SigNum, int Triggers, int Inst, PTBI pTBI)
-{
- struct pt_regs *regs = (struct pt_regs *)State.Sig.pCtx;
- unsigned int error_state = Triggers;
- siginfo_t info;
-
- head_end(State, ~INTS_OFF_MASK);
-
- local_irq_enable();
-
- info.si_signo = SIGFPE;
-
- if (error_state & TXSTAT_FPE_INVALID_BIT)
- info.si_code = FPE_FLTINV;
- else if (error_state & TXSTAT_FPE_DIVBYZERO_BIT)
- info.si_code = FPE_FLTDIV;
- else if (error_state & TXSTAT_FPE_OVERFLOW_BIT)
- info.si_code = FPE_FLTOVF;
- else if (error_state & TXSTAT_FPE_UNDERFLOW_BIT)
- info.si_code = FPE_FLTUND;
- else if (error_state & TXSTAT_FPE_INEXACT_BIT)
- info.si_code = FPE_FLTRES;
- else
- info.si_code = FPE_FIXME;
- info.si_errno = 0;
- info.si_addr = (__force void __user *)regs->ctx.CurrPC;
- force_sig_info(SIGFPE, &info, current);
-
- return tail_end(State);
-}
-#endif
-
-#ifdef CONFIG_METAG_SUSPEND_MEM
-struct traps_context {
- PTBIAPIFN fnSigs[TBID_SIGNUM_MAX + 1];
-};
-
-static struct traps_context *metag_traps_context;
-
-int traps_save_context(void)
-{
- unsigned long cpu = smp_processor_id();
- PTBI _pTBI = per_cpu(pTBI, cpu);
- struct traps_context *context;
-
- context = kzalloc(sizeof(*context), GFP_ATOMIC);
- if (!context)
- return -ENOMEM;
-
- memcpy(context->fnSigs, (void *)_pTBI->fnSigs, sizeof(context->fnSigs));
-
- metag_traps_context = context;
- return 0;
-}
-
-int traps_restore_context(void)
-{
- unsigned long cpu = smp_processor_id();
- PTBI _pTBI = per_cpu(pTBI, cpu);
- struct traps_context *context = metag_traps_context;
-
- metag_traps_context = NULL;
-
- memcpy((void *)_pTBI->fnSigs, context->fnSigs, sizeof(context->fnSigs));
-
- kfree(context);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SMP
-static inline unsigned int _get_trigger_mask(void)
-{
- unsigned long cpu = smp_processor_id();
- return per_cpu(trigger_mask, cpu);
-}
-
-unsigned int get_trigger_mask(void)
-{
- return _get_trigger_mask();
-}
-EXPORT_SYMBOL(get_trigger_mask);
-
-static void set_trigger_mask(unsigned int mask)
-{
- unsigned long cpu = smp_processor_id();
- per_cpu(trigger_mask, cpu) = mask;
-}
-
-void arch_local_irq_enable(void)
-{
- preempt_disable();
- arch_local_irq_restore(_get_trigger_mask());
- preempt_enable_no_resched();
-}
-EXPORT_SYMBOL(arch_local_irq_enable);
-#else
-static void set_trigger_mask(unsigned int mask)
-{
- global_trigger_mask = mask;
-}
-#endif
-
-void per_cpu_trap_init(unsigned long cpu)
-{
- TBIRES int_context;
- unsigned int thread = cpu_2_hwthread_id[cpu];
-
- set_trigger_mask(TBI_INTS_INIT(thread) | /* interrupts */
- TBI_TRIG_BIT(TBID_SIGNUM_LWK) | /* low level kick */
- TBI_TRIG_BIT(TBID_SIGNUM_SW1));
-
- /* non-priv - use current stack */
- int_context.Sig.pCtx = NULL;
- /* Start with interrupts off */
- int_context.Sig.TrigMask = INTS_OFF_MASK;
- int_context.Sig.SaveMask = 0;
-
- /* And call __TBIASyncTrigger() */
- __TBIASyncTrigger(int_context);
-}
-
-void __init trap_init(void)
-{
- unsigned long cpu = smp_processor_id();
- PTBI _pTBI = per_cpu(pTBI, cpu);
-
- _pTBI->fnSigs[TBID_SIGNUM_XXF] = fault_handler;
- _pTBI->fnSigs[TBID_SIGNUM_SW0] = switchx_handler;
- _pTBI->fnSigs[TBID_SIGNUM_SW1] = switch1_handler;
- _pTBI->fnSigs[TBID_SIGNUM_SW2] = switchx_handler;
- _pTBI->fnSigs[TBID_SIGNUM_SW3] = switchx_handler;
- _pTBI->fnSigs[TBID_SIGNUM_LWK] = kick_handler;
-
-#ifdef CONFIG_METAG_META21
- _pTBI->fnSigs[TBID_SIGNUM_DFR] = __TBIHandleDFR;
- _pTBI->fnSigs[TBID_SIGNUM_FPE] = fpe_handler;
-#endif
-
- per_cpu_trap_init(cpu);
-}
-
-void tbi_startup_interrupt(int irq)
-{
- unsigned long cpu = smp_processor_id();
- PTBI _pTBI = per_cpu(pTBI, cpu);
-
- BUG_ON(irq > TBID_SIGNUM_MAX);
-
- /* For TR1 and TR2, the thread id is encoded in the irq number */
- if (irq >= TBID_SIGNUM_T10 && irq < TBID_SIGNUM_TR3)
- cpu = hwthread_id_2_cpu[(irq - TBID_SIGNUM_T10) % 4];
-
- set_trigger_mask(get_trigger_mask() | TBI_TRIG_BIT(irq));
-
- _pTBI->fnSigs[irq] = trigger_handler;
-}
-
-void tbi_shutdown_interrupt(int irq)
-{
- unsigned long cpu = smp_processor_id();
- PTBI _pTBI = per_cpu(pTBI, cpu);
-
- BUG_ON(irq > TBID_SIGNUM_MAX);
-
- set_trigger_mask(get_trigger_mask() & ~TBI_TRIG_BIT(irq));
-
- _pTBI->fnSigs[irq] = __TBIUnExpXXX;
-}
-
-int ret_from_fork(TBIRES arg)
-{
- struct task_struct *prev = arg.Switch.pPara;
- struct task_struct *tsk = current;
- struct pt_regs *regs = task_pt_regs(tsk);
- int (*fn)(void *);
- TBIRES Next;
-
- schedule_tail(prev);
-
- if (tsk->flags & PF_KTHREAD) {
- fn = (void *)regs->ctx.DX[4].U1;
- BUG_ON(!fn);
-
- fn((void *)regs->ctx.DX[3].U1);
- }
-
- if (test_syscall_work())
- syscall_trace_leave(regs);
-
- preempt_disable();
-
- Next.Sig.TrigMask = get_trigger_mask();
- Next.Sig.SaveMask = 0;
- Next.Sig.pCtx = &regs->ctx;
-
- set_gateway_tls(current->thread.tls_ptr);
-
- preempt_enable_no_resched();
-
- /* And interrupts should come back on when we resume the real usermode
- * code. Call __TBIASyncResume()
- */
- __TBIASyncResume(tail_end(Next));
- /* ASyncResume should NEVER return */
- BUG();
- return 0;
-}
-
-void show_trace(struct task_struct *tsk, unsigned long *sp,
- struct pt_regs *regs)
-{
- unsigned long addr;
-#ifdef CONFIG_FRAME_POINTER
- unsigned long fp, fpnew;
- unsigned long stack;
-#endif
-
- if (regs && user_mode(regs))
- return;
-
- printk("\nCall trace: ");
-#ifdef CONFIG_KALLSYMS
- printk("\n");
-#endif
-
- if (!tsk)
- tsk = current;
-
-#ifdef CONFIG_FRAME_POINTER
- if (regs) {
- print_ip_sym(regs->ctx.CurrPC);
- fp = regs->ctx.AX[1].U0;
- } else {
- fp = __core_reg_get(A0FrP);
- }
-
- /* detect when the frame pointer has been used for other purposes and
- * doesn't point to the stack (it may point completely elsewhere which
- * kstack_end may not detect).
- */
- stack = (unsigned long)task_stack_page(tsk);
- while (fp >= stack && fp + 8 <= stack + THREAD_SIZE) {
- addr = __raw_readl((unsigned long *)(fp + 4)) - 4;
- if (kernel_text_address(addr))
- print_ip_sym(addr);
- else
- break;
- /* stack grows up, so frame pointers must decrease */
- fpnew = __raw_readl((unsigned long *)(fp + 0));
- if (fpnew >= fp)
- break;
- fp = fpnew;
- }
-#else
- while (!kstack_end(sp)) {
- addr = (*sp--) - 4;
- if (kernel_text_address(addr))
- print_ip_sym(addr);
- }
-#endif
-
- printk("\n");
-
- debug_show_held_locks(tsk);
-}
-
-void show_stack(struct task_struct *tsk, unsigned long *sp)
-{
- if (!tsk)
- tsk = current;
- if (tsk == current)
- sp = (unsigned long *)current_stack_pointer;
- else
- sp = (unsigned long *)tsk->thread.kernel_context->AX[0].U0;
-
- show_trace(tsk, sp, NULL);
-}
diff --git a/arch/metag/kernel/user_gateway.S b/arch/metag/kernel/user_gateway.S
deleted file mode 100644
index 7833fb8f9ddd..000000000000
--- a/arch/metag/kernel/user_gateway.S
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2010 Imagination Technologies Ltd.
- *
- * This file contains code that can be accessed from userspace and can
- * access certain kernel data structures without the overhead of a system
- * call.
- */
-
-#include <asm/metag_regs.h>
-#include <asm/user_gateway.h>
-
-/*
- * User helpers.
- *
- * These are segment of kernel provided user code reachable from user space
- * at a fixed address in kernel memory. This is used to provide user space
- * with some operations which require kernel help because of unimplemented
- * native feature and/or instructions in some Meta CPUs. The idea is for
- * this code to be executed directly in user mode for best efficiency but
- * which is too intimate with the kernel counter part to be left to user
- * libraries. The kernel reserves the right to change this code as needed
- * without warning. Only the entry points and their results are guaranteed
- * to be stable.
- *
- * Each segment is 64-byte aligned. This mechanism should be used only for
- * for things that are really small and justified, and not be abused freely.
- */
- .text
- .global ___user_gateway_start
-___user_gateway_start:
-
- /* get_tls
- * Offset: 0
- * Description: Get the TLS pointer for this process.
- */
- .global ___kuser_get_tls
- .type ___kuser_get_tls,function
-___kuser_get_tls:
- MOVT D1Ar1,#HI(USER_GATEWAY_PAGE + USER_GATEWAY_TLS)
- ADD D1Ar1,D1Ar1,#LO(USER_GATEWAY_PAGE + USER_GATEWAY_TLS)
- MOV D1Ar3,TXENABLE
- AND D1Ar3,D1Ar3,#(TXENABLE_THREAD_BITS)
- LSR D1Ar3,D1Ar3,#(TXENABLE_THREAD_S - 2)
- GETD D0Re0,[D1Ar1+D1Ar3]
-___kuser_get_tls_end: /* Beyond this point the read will complete */
- MOV PC,D1RtP
- .size ___kuser_get_tls,.-___kuser_get_tls
- .global ___kuser_get_tls_end
-
- /* cmpxchg
- * Offset: 64
- * Description: Replace the value at 'ptr' with 'newval' if the current
- * value is 'oldval'. Return zero if we succeeded,
- * non-zero otherwise.
- *
- * Reference prototype:
- *
- * int __kuser_cmpxchg(int oldval, int newval, unsigned long *ptr)
- *
- */
- .balign 64
- .global ___kuser_cmpxchg
- .type ___kuser_cmpxchg,function
-___kuser_cmpxchg:
-#ifdef CONFIG_SMP
- /*
- * We must use LNKGET/LNKSET with an SMP kernel because the other method
- * does not provide atomicity across multiple CPUs.
- */
-0: LNKGETD D0Re0,[D1Ar3]
- CMP D0Re0,D1Ar1
- LNKSETDZ [D1Ar3],D0Ar2
- BNZ 1f
- DEFR D0Re0,TXSTAT
- ANDT D0Re0,D0Re0,#HI(0x3f000000)
- CMPT D0Re0,#HI(0x02000000)
- BNE 0b
-#ifdef CONFIG_METAG_LNKGET_AROUND_CACHE
- DCACHE [D1Ar3], D0Re0
-#endif
-1: MOV D0Re0,#1
- XORZ D0Re0,D0Re0,D0Re0
- MOV PC,D1RtP
-#else
- GETD D0Re0,[D1Ar3]
- CMP D0Re0,D1Ar1
- SETDZ [D1Ar3],D0Ar2
-___kuser_cmpxchg_end: /* Beyond this point the write will complete */
- MOV D0Re0,#1
- XORZ D0Re0,D0Re0,D0Re0
- MOV PC,D1RtP
-#endif /* CONFIG_SMP */
- .size ___kuser_cmpxchg,.-___kuser_cmpxchg
- .global ___kuser_cmpxchg_end
-
- .global ___user_gateway_end
-___user_gateway_end:
diff --git a/arch/metag/kernel/vmlinux.lds.S b/arch/metag/kernel/vmlinux.lds.S
deleted file mode 100644
index 1efadae2ea8e..000000000000
--- a/arch/metag/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,74 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ld script to make Meta Linux kernel */
-
-#include <asm/thread_info.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-
-#include <asm-generic/vmlinux.lds.h>
-
-OUTPUT_FORMAT("elf32-metag", "elf32-metag", "elf32-metag")
-OUTPUT_ARCH(metag)
-ENTRY(__start)
-
-_jiffies = _jiffies_64;
-SECTIONS
-{
- . = CONFIG_PAGE_OFFSET;
- _text = .;
- __text = .;
- __stext = .;
- HEAD_TEXT_SECTION
- .text : {
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- KPROBES_TEXT
- IRQENTRY_TEXT
- SOFTIRQENTRY_TEXT
- *(.text.*)
- *(.gnu.warning)
- }
-
- __etext = .; /* End of text section */
-
- __sdata = .;
- RO_DATA_SECTION(PAGE_SIZE)
- RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
- __edata = .; /* End of data section */
-
- EXCEPTION_TABLE(16)
- NOTES
-
- . = ALIGN(PAGE_SIZE); /* Init code and data */
- ___init_begin = .;
- INIT_TEXT_SECTION(PAGE_SIZE)
- INIT_DATA_SECTION(16)
-
- .init.arch.info : {
- ___arch_info_begin = .;
- *(.arch.info.init)
- ___arch_info_end = .;
- }
-
- PERCPU_SECTION(L1_CACHE_BYTES)
-
- ___init_end = .;
-
- BSS_SECTION(0, PAGE_SIZE, 0)
-
- __end = .;
-
- . = ALIGN(PAGE_SIZE);
- __heap_start = .;
-
- DWARF_DEBUG
-
- /* When something in the kernel is NOT compiled as a module, the
- * module cleanup code and data are put into these segments. Both
- * can then be thrown away, as cleanup code is never called unless
- * it's a module.
- */
- DISCARDS
-}
diff --git a/arch/metag/lib/Makefile b/arch/metag/lib/Makefile
deleted file mode 100644
index 3982850d692c..000000000000
--- a/arch/metag/lib/Makefile
+++ /dev/null
@@ -1,23 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for Meta-specific library files.
-#
-
-lib-y += usercopy.o
-lib-y += copy_page.o
-lib-y += clear_page.o
-lib-y += memcpy.o
-lib-y += memmove.o
-lib-y += memset.o
-lib-y += delay.o
-lib-y += div64.o
-lib-y += muldi3.o
-lib-y += ashrdi3.o
-lib-y += ashldi3.o
-lib-y += lshrdi3.o
-lib-y += divsi3.o
-lib-y += modsi3.o
-lib-y += cmpdi2.o
-lib-y += ucmpdi2.o
-lib-y += ip_fast_csum.o
-lib-y += checksum.o
diff --git a/arch/metag/lib/ashldi3.S b/arch/metag/lib/ashldi3.S
deleted file mode 100644
index 5055df9e5c7b..000000000000
--- a/arch/metag/lib/ashldi3.S
+++ /dev/null
@@ -1,34 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2012 by Imagination Technologies Ltd.
-!
-! 64-bit arithmetic shift left routine.
-!
-
- .text
- .global ___ashldi3
- .type ___ashldi3,function
-
-___ashldi3:
- MOV D0Re0,D0Ar2
- MOV D1Re0,D1Ar1
- CMP D1Ar3,#0 ! COUNT == 0
- MOVEQ PC,D1RtP ! Yes, return
-
- SUBS D0Ar4,D1Ar3,#32 ! N = COUNT - 32
- BGE $L10
-
-!! Shift < 32
- NEG D0Ar4,D0Ar4 ! N = - N
- LSL D1Re0,D1Re0,D1Ar3 ! HI = HI << COUNT
- LSR D0Ar6,D0Re0,D0Ar4 ! TMP= LO >> -(COUNT - 32)
- OR D1Re0,D1Re0,D0Ar6 ! HI = HI | TMP
- SWAP D0Ar4,D1Ar3
- LSL D0Re0,D0Re0,D0Ar4 ! LO = LO << COUNT
- MOV PC,D1RtP
-
-$L10:
-!! Shift >= 32
- LSL D1Re0,D0Re0,D0Ar4 ! HI = LO << N
- MOV D0Re0,#0 ! LO = 0
- MOV PC,D1RtP
- .size ___ashldi3,.-___ashldi3
diff --git a/arch/metag/lib/ashrdi3.S b/arch/metag/lib/ashrdi3.S
deleted file mode 100644
index 0c838fd9da85..000000000000
--- a/arch/metag/lib/ashrdi3.S
+++ /dev/null
@@ -1,34 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2012 by Imagination Technologies Ltd.
-!
-! 64-bit arithmetic shift right routine.
-!
-
- .text
- .global ___ashrdi3
- .type ___ashrdi3,function
-
-___ashrdi3:
- MOV D0Re0,D0Ar2
- MOV D1Re0,D1Ar1
- CMP D1Ar3,#0 ! COUNT == 0
- MOVEQ PC,D1RtP ! Yes, return
-
- MOV D0Ar4,D1Ar3
- SUBS D1Ar3,D1Ar3,#32 ! N = COUNT - 32
- BGE $L20
-
-!! Shift < 32
- NEG D1Ar3,D1Ar3 ! N = - N
- LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
- LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
- OR D0Re0,D0Re0,D0Ar6 ! LO = LO | TMP
- SWAP D1Ar3,D0Ar4
- ASR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
- MOV PC,D1RtP
-$L20:
-!! Shift >= 32
- ASR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
- ASR D1Re0,D1Re0,#31 ! HI = HI >> 31
- MOV PC,D1RtP
- .size ___ashrdi3,.-___ashrdi3
diff --git a/arch/metag/lib/checksum.c b/arch/metag/lib/checksum.c
deleted file mode 100644
index 5d6a98a05e9d..000000000000
--- a/arch/metag/lib/checksum.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- *
- * INET An implementation of the TCP/IP protocol suite for the LINUX
- * operating system. INET is implemented using the BSD Socket
- * interface as the means of communication with the user level.
- *
- * IP/TCP/UDP checksumming routines
- *
- * Authors: Jorge Cwik, <jorge@laser.satlink.net>
- * Arnt Gulbrandsen, <agulbra@nvg.unit.no>
- * Tom May, <ftom@netcom.com>
- * Andreas Schwab, <schwab@issan.informatik.uni-dortmund.de>
- * Lots of code moved from tcp.c and ip.c; see those files
- * for more names.
- *
- * 03/02/96 Jes Sorensen, Andreas Schwab, Roman Hodek:
- * Fixed some nasty bugs, causing some horrible crashes.
- * A: At some points, the sum (%0) was used as
- * length-counter instead of the length counter
- * (%1). Thanks to Roman Hodek for pointing this out.
- * B: GCC seems to mess up if one uses too many
- * data-registers to hold input values and one tries to
- * specify d0 and d1 as scratch registers. Letting gcc
- * choose these registers itself solves the problem.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-/* Revised by Kenneth Albanowski for m68knommu. Basic problem: unaligned access
- kills, so most of the assembly has to go. */
-
-#include <linux/module.h>
-#include <net/checksum.h>
-
-#include <asm/byteorder.h>
-
-static inline unsigned short from32to16(unsigned int x)
-{
- /* add up 16-bit and 16-bit for 16+c bit */
- x = (x & 0xffff) + (x >> 16);
- /* add up carry.. */
- x = (x & 0xffff) + (x >> 16);
- return x;
-}
-
-static unsigned int do_csum(const unsigned char *buff, int len)
-{
- int odd;
- unsigned int result = 0;
-
- if (len <= 0)
- goto out;
- odd = 1 & (unsigned long) buff;
- if (odd) {
-#ifdef __LITTLE_ENDIAN
- result += (*buff << 8);
-#else
- result = *buff;
-#endif
- len--;
- buff++;
- }
- if (len >= 2) {
- if (2 & (unsigned long) buff) {
- result += *(unsigned short *) buff;
- len -= 2;
- buff += 2;
- }
- if (len >= 4) {
- const unsigned char *end = buff + ((unsigned)len & ~3);
- unsigned int carry = 0;
- do {
- unsigned int w = *(unsigned int *) buff;
- buff += 4;
- result += carry;
- result += w;
- carry = (w > result);
- } while (buff < end);
- result += carry;
- result = (result & 0xffff) + (result >> 16);
- }
- if (len & 2) {
- result += *(unsigned short *) buff;
- buff += 2;
- }
- }
- if (len & 1)
-#ifdef __LITTLE_ENDIAN
- result += *buff;
-#else
- result += (*buff << 8);
-#endif
- result = from32to16(result);
- if (odd)
- result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
-out:
- return result;
-}
-EXPORT_SYMBOL(ip_fast_csum);
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum wsum)
-{
- unsigned int sum = (__force unsigned int)wsum;
- unsigned int result = do_csum(buff, len);
-
- /* add in old sum, and carry.. */
- result += sum;
- if (sum > result)
- result += 1;
- return (__force __wsum)result;
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-__sum16 ip_compute_csum(const void *buff, int len)
-{
- return (__force __sum16)~do_csum(buff, len);
-}
-EXPORT_SYMBOL(ip_compute_csum);
-
-/*
- * copy from fs while checksumming, otherwise like csum_partial
- */
-__wsum
-csum_partial_copy_from_user(const void __user *src, void *dst, int len,
- __wsum sum, int *csum_err)
-{
- int missing;
-
- missing = __copy_from_user(dst, src, len);
- if (missing) {
- memset(dst + len - missing, 0, missing);
- *csum_err = -EFAULT;
- } else
- *csum_err = 0;
-
- return csum_partial(dst, len, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-
-/*
- * copy from ds while checksumming, otherwise like csum_partial
- */
-__wsum
-csum_partial_copy(const void *src, void *dst, int len, __wsum sum)
-{
- memcpy(dst, src, len);
- return csum_partial(dst, len, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy);
diff --git a/arch/metag/lib/clear_page.S b/arch/metag/lib/clear_page.S
deleted file mode 100644
index 87756a5d1367..000000000000
--- a/arch/metag/lib/clear_page.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
- ! Copyright 2007,2008,2009 Imagination Technologies Ltd.
-
-#include <asm/page.h>
-
- .text
- .global _clear_page
- .type _clear_page,function
- !! D1Ar1 - page
-_clear_page:
- MOV TXRPT,#((PAGE_SIZE / 8) - 1)
- MOV D0Re0,#0
- MOV D1Re0,#0
-$Lclear_page_loop:
- SETL [D1Ar1++],D0Re0,D1Re0
- BR $Lclear_page_loop
- MOV PC,D1RtP
- .size _clear_page,.-_clear_page
diff --git a/arch/metag/lib/cmpdi2.S b/arch/metag/lib/cmpdi2.S
deleted file mode 100644
index ab70bd94fd81..000000000000
--- a/arch/metag/lib/cmpdi2.S
+++ /dev/null
@@ -1,33 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2012 by Imagination Technologies Ltd.
-!
-! 64-bit signed compare routine.
-!
-
- .text
- .global ___cmpdi2
- .type ___cmpdi2,function
-
-! low high
-! s64 a (D0Ar2, D1Ar1)
-! s64 b (D0Ar4, D1Ar3)
-___cmpdi2:
- ! start at 1 (equal) and conditionally increment or decrement
- MOV D0Re0,#1
-
- ! high words differ?
- CMP D1Ar1,D1Ar3
- BNE $Lhigh_differ
-
- ! unsigned compare low words
- CMP D0Ar2,D0Ar4
- SUBLO D0Re0,D0Re0,#1
- ADDHI D0Re0,D0Re0,#1
- MOV PC,D1RtP
-
-$Lhigh_differ:
- ! signed compare high words
- SUBLT D0Re0,D0Re0,#1
- ADDGT D0Re0,D0Re0,#1
- MOV PC,D1RtP
- .size ___cmpdi2,.-___cmpdi2
diff --git a/arch/metag/lib/copy_page.S b/arch/metag/lib/copy_page.S
deleted file mode 100644
index abbc75e94374..000000000000
--- a/arch/metag/lib/copy_page.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
- ! Copyright 2007,2008 Imagination Technologies Ltd.
-
-#include <asm/page.h>
-
- .text
- .global _copy_page
- .type _copy_page,function
- !! D1Ar1 - to
- !! D0Ar2 - from
-_copy_page:
- MOV D0FrT,#PAGE_SIZE
-$Lcopy_page_loop:
- GETL D0Re0,D1Re0,[D0Ar2++]
- GETL D0Ar6,D1Ar5,[D0Ar2++]
- SETL [D1Ar1++],D0Re0,D1Re0
- SETL [D1Ar1++],D0Ar6,D1Ar5
- SUBS D0FrT,D0FrT,#16
- BNZ $Lcopy_page_loop
- MOV PC,D1RtP
- .size _copy_page,.-_copy_page
diff --git a/arch/metag/lib/delay.c b/arch/metag/lib/delay.c
deleted file mode 100644
index 6754012a261f..000000000000
--- a/arch/metag/lib/delay.c
+++ /dev/null
@@ -1,57 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Precise Delay Loops for Meta
- *
- * Copyright (C) 1993 Linus Torvalds
- * Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
- * Copyright (C) 2007,2009 Imagination Technologies Ltd.
- *
- */
-
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-
-#include <asm/core_reg.h>
-#include <asm/processor.h>
-
-/*
- * TXTACTCYC is only 24 bits, so on chips with fast clocks it will wrap
- * many times per-second. If it does wrap __delay will return prematurely,
- * but this is only likely with large delay values.
- *
- * We also can't implement read_current_timer() with TXTACTCYC due to
- * this wrapping behaviour.
- */
-#define rdtimer(t) t = __core_reg_get(TXTACTCYC)
-
-void __delay(unsigned long loops)
-{
- unsigned long bclock, now;
-
- rdtimer(bclock);
- do {
- asm("NOP");
- rdtimer(now);
- } while ((now-bclock) < loops);
-}
-EXPORT_SYMBOL(__delay);
-
-inline void __const_udelay(unsigned long xloops)
-{
- u64 loops = (u64)xloops * (u64)loops_per_jiffy * HZ;
- __delay(loops >> 32);
-}
-EXPORT_SYMBOL(__const_udelay);
-
-void __udelay(unsigned long usecs)
-{
- __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
-}
-EXPORT_SYMBOL(__udelay);
-
-void __ndelay(unsigned long nsecs)
-{
- __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
-}
-EXPORT_SYMBOL(__ndelay);
diff --git a/arch/metag/lib/div64.S b/arch/metag/lib/div64.S
deleted file mode 100644
index 55eece273a6b..000000000000
--- a/arch/metag/lib/div64.S
+++ /dev/null
@@ -1,109 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2012 Imagination Technologies Ltd.
-!
-! Signed/unsigned 64-bit division routines.
-!
-
- .text
- .global _div_u64
- .type _div_u64,function
-
-_div_u64:
-$L1:
- ORS A0.3,D1Ar3,D0Ar4
- BNE $L3
-$L2:
- MOV D0Re0,D0Ar2
- MOV D1Re0,D1Ar1
- MOV PC,D1RtP
-$L3:
- CMP D1Ar3,D1Ar1
- CMPEQ D0Ar4,D0Ar2
- MOV D0Re0,#1
- MOV D1Re0,#0
- BHS $L6
-$L4:
- ADDS D0Ar6,D0Ar4,D0Ar4
- ADD D1Ar5,D1Ar3,D1Ar3
- ADDCS D1Ar5,D1Ar5,#1
- CMP D1Ar5,D1Ar3
- CMPEQ D0Ar6,D0Ar4
- BLO $L6
-$L5:
- MOV D0Ar4,D0Ar6
- MOV D1Ar3,D1Ar5
- ADDS D0Re0,D0Re0,D0Re0
- ADD D1Re0,D1Re0,D1Re0
- ADDCS D1Re0,D1Re0,#1
- CMP D1Ar3,D1Ar1
- CMPEQ D0Ar4,D0Ar2
- BLO $L4
-$L6:
- ORS A0.3,D1Re0,D0Re0
- MOV D0Ar6,#0
- MOV D1Ar5,D0Ar6
- BEQ $L10
-$L7:
- CMP D1Ar1,D1Ar3
- CMPEQ D0Ar2,D0Ar4
- BLO $L9
-$L8:
- ADDS D0Ar6,D0Ar6,D0Re0
- ADD D1Ar5,D1Ar5,D1Re0
- ADDCS D1Ar5,D1Ar5,#1
-
- SUBS D0Ar2,D0Ar2,D0Ar4
- SUB D1Ar1,D1Ar1,D1Ar3
- SUBCS D1Ar1,D1Ar1,#1
-$L9:
- LSL A0.3,D1Re0,#31
- LSR D0Re0,D0Re0,#1
- LSR D1Re0,D1Re0,#1
- OR D0Re0,D0Re0,A0.3
- LSL A0.3,D1Ar3,#31
- LSR D0Ar4,D0Ar4,#1
- LSR D1Ar3,D1Ar3,#1
- OR D0Ar4,D0Ar4,A0.3
- ORS A0.3,D1Re0,D0Re0
- BNE $L7
-$L10:
- MOV D0Re0,D0Ar6
- MOV D1Re0,D1Ar5
- MOV PC,D1RtP
- .size _div_u64,.-_div_u64
-
- .text
- .global _div_s64
- .type _div_s64,function
-_div_s64:
- MSETL [A0StP],D0FrT,D0.5
- XOR D0.5,D0Ar2,D0Ar4
- XOR D1.5,D1Ar1,D1Ar3
- TSTT D1Ar1,#HI(0x80000000)
- BZ $L25
-
- NEGS D0Ar2,D0Ar2
- NEG D1Ar1,D1Ar1
- SUBCS D1Ar1,D1Ar1,#1
-$L25:
- TSTT D1Ar3,#HI(0x80000000)
- BZ $L27
-
- NEGS D0Ar4,D0Ar4
- NEG D1Ar3,D1Ar3
- SUBCS D1Ar3,D1Ar3,#1
-$L27:
- CALLR D1RtP,_div_u64
- TSTT D1.5,#HI(0x80000000)
- BZ $L29
-
- NEGS D0Re0,D0Re0
- NEG D1Re0,D1Re0
- SUBCS D1Re0,D1Re0,#1
-$L29:
-
- GETL D0FrT,D1RtP,[A0StP+#(-16)]
- GETL D0.5,D1.5,[A0StP+#(-8)]
- SUB A0StP,A0StP,#16
- MOV PC,D1RtP
- .size _div_s64,.-_div_s64
diff --git a/arch/metag/lib/divsi3.S b/arch/metag/lib/divsi3.S
deleted file mode 100644
index 9e31abefb160..000000000000
--- a/arch/metag/lib/divsi3.S
+++ /dev/null
@@ -1,101 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
-! Imagination Technologies Ltd
-!
-! Integer divide routines.
-!
-
- .text
- .global ___udivsi3
- .type ___udivsi3,function
- .align 2
-___udivsi3:
-!!
-!! Since core is signed divide case, just set control variable
-!!
- MOV D1Re0,D0Ar2 ! Au already in A1Ar1, Bu -> D1Re0
- MOV D0Re0,#0 ! Result is 0
- MOV D0Ar4,#0 ! Return positive result
- B $LIDMCUStart
- .size ___udivsi3,.-___udivsi3
-
-!!
-!! 32-bit division signed i/p - passed signed 32-bit numbers
-!!
- .global ___divsi3
- .type ___divsi3,function
- .align 2
-___divsi3:
-!!
-!! A already in D1Ar1, B already in D0Ar2 -> make B abs(B)
-!!
- MOV D1Re0,D0Ar2 ! A already in A1Ar1, B -> D1Re0
- MOV D0Re0,#0 ! Result is 0
- XOR D0Ar4,D1Ar1,D1Re0 ! D0Ar4 -ive if result is -ive
- ABS D1Ar1,D1Ar1 ! abs(A) -> Au
- ABS D1Re0,D1Re0 ! abs(B) -> Bu
-$LIDMCUStart:
- CMP D1Ar1,D1Re0 ! Is ( Au > Bu )?
- LSR D1Ar3,D1Ar1,#2 ! Calculate (Au & (~3)) >> 2
- CMPHI D1Re0,D1Ar3 ! OR ( (Au & (~3)) <= (Bu << 2) )?
- LSLSHI D1Ar3,D1Re0,#1 ! Buq = Bu << 1
- BLS $LIDMCUSetup ! Yes: Do normal divide
-!!
-!! Quick divide setup can assume that CurBit only needs to start at 2
-!!
-$LIDMCQuick:
- CMP D1Ar1,D1Ar3 ! ( A >= Buq )?
- ADDCC D0Re0,D0Re0,#2 ! If yes result += 2
- SUBCC D1Ar1,D1Ar1,D1Ar3 ! and A -= Buq
- CMP D1Ar1,D1Re0 ! ( A >= Bu )?
- ADDCC D0Re0,D0Re0,#1 ! If yes result += 1
- SUBCC D1Ar1,D1Ar1,D1Re0 ! and A -= Bu
- ORS D0Ar4,D0Ar4,D0Ar4 ! Return neg result?
- NEG D0Ar2,D0Re0 ! Calculate neg result
- MOVMI D0Re0,D0Ar2 ! Yes: Take neg result
-$LIDMCRet:
- MOV PC,D1RtP
-!!
-!! Setup for general unsigned divide code
-!!
-!! D0Re0 is used to form the result, already set to Zero
-!! D1Re0 is the input Bu value, this gets trashed
-!! D0Ar6 is curbit which is set to 1 at the start and shifted up
-!! D0Ar4 is negative if we should return a negative result
-!! D1Ar1 is the input Au value, eventually this holds the remainder
-!!
-$LIDMCUSetup:
- CMP D1Ar1,D1Re0 ! Is ( Au < Bu )?
- MOV D0Ar6,#1 ! Set curbit to 1
- BCS $LIDMCRet ! Yes: Return 0 remainder Au
-!!
-!! Calculate alignment using FFB instruction
-!!
- FFB D1Ar5,D1Ar1 ! Find first bit of Au
- ANDN D1Ar5,D1Ar5,#31 ! Handle exceptional case.
- ORN D1Ar5,D1Ar5,#31 ! if N bit set, set to 31
- FFB D1Ar3,D1Re0 ! Find first bit of Bu
- ANDN D1Ar3,D1Ar3,#31 ! Handle exceptional case.
- ORN D1Ar3,D1Ar3,#31 ! if N bit set, set to 31
- SUBS D1Ar3,D1Ar5,D1Ar3 ! calculate diff, ffbA - ffbB
- MOV D0Ar2,D1Ar3 ! copy into bank 0
- LSLGT D1Re0,D1Re0,D1Ar3 ! ( > 0) ? left shift B
- LSLGT D0Ar6,D0Ar6,D0Ar2 ! ( > 0) ? left shift curbit
-!!
-!! Now we start the divide proper, logic is
-!!
-!! if ( A >= B ) add curbit to result and subtract B from A
-!! shift curbit and B down by 1 in either case
-!!
-$LIDMCLoop:
- CMP D1Ar1, D1Re0 ! ( A >= B )?
- ADDCC D0Re0, D0Re0, D0Ar6 ! If yes result += curbit
- SUBCC D1Ar1, D1Ar1, D1Re0 ! and A -= B
- LSRS D0Ar6, D0Ar6, #1 ! Shift down curbit, is it zero?
- LSR D1Re0, D1Re0, #1 ! Shift down B
- BNZ $LIDMCLoop ! Was single bit in curbit lost?
- ORS D0Ar4,D0Ar4,D0Ar4 ! Return neg result?
- NEG D0Ar2,D0Re0 ! Calculate neg result
- MOVMI D0Re0,D0Ar2 ! Yes: Take neg result
- MOV PC,D1RtP
- .size ___divsi3,.-___divsi3
diff --git a/arch/metag/lib/ip_fast_csum.S b/arch/metag/lib/ip_fast_csum.S
deleted file mode 100644
index 441f489d6a81..000000000000
--- a/arch/metag/lib/ip_fast_csum.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
- .text
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- *
- * extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
- *
- */
- .global _ip_fast_csum
- .type _ip_fast_csum,function
-_ip_fast_csum:
- !! TXRPT needs loops - 1
- SUBS TXRPT,D0Ar2,#1
- MOV D0Re0,#0
- BLO $Lfast_csum_exit
-$Lfast_csum_loop:
- GETD D1Ar3,[D1Ar1++]
- ADDS D0Re0,D0Re0,D1Ar3
- ADDCS D0Re0,D0Re0,#1
- BR $Lfast_csum_loop
- LSR D0Ar4,D0Re0,#16
- AND D0Re0,D0Re0,#0xffff
- AND D0Ar4,D0Ar4,#0xffff
- ADD D0Re0,D0Re0,D0Ar4
- LSR D0Ar4,D0Re0,#16
- ADD D0Re0,D0Re0,D0Ar4
- XOR D0Re0,D0Re0,#-1
- AND D0Re0,D0Re0,#0xffff
-$Lfast_csum_exit:
- MOV PC,D1RtP
- .size _ip_fast_csum,.-_ip_fast_csum
diff --git a/arch/metag/lib/lshrdi3.S b/arch/metag/lib/lshrdi3.S
deleted file mode 100644
index cf7ffc9b377f..000000000000
--- a/arch/metag/lib/lshrdi3.S
+++ /dev/null
@@ -1,34 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2012 by Imagination Technologies Ltd.
-!
-! 64-bit logical shift right routine.
-!
-
- .text
- .global ___lshrdi3
- .type ___lshrdi3,function
-
-___lshrdi3:
- MOV D0Re0,D0Ar2
- MOV D1Re0,D1Ar1
- CMP D1Ar3,#0 ! COUNT == 0
- MOVEQ PC,D1RtP ! Yes, return
-
- MOV D0Ar4,D1Ar3
- SUBS D1Ar3,D1Ar3,#32 ! N = COUNT - 32
- BGE $L30
-
-!! Shift < 32
- NEG D1Ar3,D1Ar3 ! N = - N
- LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
- LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
- OR D0Re0,D0Re0,D0Ar6 ! LO = LO | TMP
- SWAP D1Ar3,D0Ar4
- LSR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
- MOV PC,D1RtP
-$L30:
-!! Shift >= 32
- LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
- MOV D1Re0,#0 ! HI = 0
- MOV PC,D1RtP
- .size ___lshrdi3,.-___lshrdi3
diff --git a/arch/metag/lib/memcpy.S b/arch/metag/lib/memcpy.S
deleted file mode 100644
index c2e8395f9456..000000000000
--- a/arch/metag/lib/memcpy.S
+++ /dev/null
@@ -1,186 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2008-2012 Imagination Technologies Ltd.
-
- .text
- .global _memcpy
- .type _memcpy,function
-! D1Ar1 dst
-! D0Ar2 src
-! D1Ar3 cnt
-! D0Re0 dst
-_memcpy:
- CMP D1Ar3, #16
- MOV A1.2, D0Ar2 ! source pointer
- MOV A0.2, D1Ar1 ! destination pointer
- MOV A0.3, D1Ar1 ! for return value
-! If there are less than 16 bytes to copy use the byte copy loop
- BGE $Llong_copy
-
-$Lbyte_copy:
-! Simply copy a byte at a time
- SUBS TXRPT, D1Ar3, #1
- BLT $Lend
-$Lloop_byte:
- GETB D1Re0, [A1.2++]
- SETB [A0.2++], D1Re0
- BR $Lloop_byte
-
-$Lend:
-! Finally set return value and return
- MOV D0Re0, A0.3
- MOV PC, D1RtP
-
-$Llong_copy:
- ANDS D1Ar5, D1Ar1, #7 ! test destination alignment
- BZ $Laligned_dst
-
-! The destination address is not 8 byte aligned. We will copy bytes from
-! the source to the destination until the remaining data has an 8 byte
-! destination address alignment (i.e we should never copy more than 7
-! bytes here).
-$Lalign_dst:
- GETB D0Re0, [A1.2++]
- ADD D1Ar5, D1Ar5, #1 ! dest is aligned when D1Ar5 reaches #8
- SUB D1Ar3, D1Ar3, #1 ! decrement count of remaining bytes
- SETB [A0.2++], D0Re0
- CMP D1Ar5, #8
- BNE $Lalign_dst
-
-! We have at least (16 - 7) = 9 bytes to copy - calculate the number of 8 byte
-! blocks, then jump to the unaligned copy loop or fall through to the aligned
-! copy loop as appropriate.
-$Laligned_dst:
- MOV D0Ar4, A1.2
- LSR D1Ar5, D1Ar3, #3 ! D1Ar5 = number of 8 byte blocks
- ANDS D0Ar4, D0Ar4, #7 ! test source alignment
- BNZ $Lunaligned_copy ! if unaligned, use unaligned copy loop
-
-! Both source and destination are 8 byte aligned - the easy case.
-$Laligned_copy:
- LSRS D1Ar5, D1Ar3, #5 ! D1Ar5 = number of 32 byte blocks
- BZ $Lbyte_copy
- SUB TXRPT, D1Ar5, #1
-
-$Laligned_32:
- GETL D0Re0, D1Re0, [A1.2++]
- GETL D0Ar6, D1Ar5, [A1.2++]
- SETL [A0.2++], D0Re0, D1Re0
- SETL [A0.2++], D0Ar6, D1Ar5
- GETL D0Re0, D1Re0, [A1.2++]
- GETL D0Ar6, D1Ar5, [A1.2++]
- SETL [A0.2++], D0Re0, D1Re0
- SETL [A0.2++], D0Ar6, D1Ar5
- BR $Laligned_32
-
-! If there are any remaining bytes use the byte copy loop, otherwise we are done
- ANDS D1Ar3, D1Ar3, #0x1f
- BNZ $Lbyte_copy
- B $Lend
-
-! The destination is 8 byte aligned but the source is not, and there are 8
-! or more bytes to be copied.
-$Lunaligned_copy:
-! Adjust the source pointer (A1.2) to the 8 byte boundary before its
-! current value
- MOV D0Ar4, A1.2
- MOV D0Ar6, A1.2
- ANDMB D0Ar4, D0Ar4, #0xfff8
- MOV A1.2, D0Ar4
-! Save the number of bytes of mis-alignment in D0Ar4 for use later
- SUBS D0Ar6, D0Ar6, D0Ar4
- MOV D0Ar4, D0Ar6
-! if there is no mis-alignment after all, use the aligned copy loop
- BZ $Laligned_copy
-
-! prefetch 8 bytes
- GETL D0Re0, D1Re0, [A1.2]
-
- SUB TXRPT, D1Ar5, #1
-
-! There are 3 mis-alignment cases to be considered. Less than 4 bytes, exactly
-! 4 bytes, and more than 4 bytes.
- CMP D0Ar6, #4
- BLT $Lunaligned_1_2_3 ! use 1-3 byte mis-alignment loop
- BZ $Lunaligned_4 ! use 4 byte mis-alignment loop
-
-! The mis-alignment is more than 4 bytes
-$Lunaligned_5_6_7:
- SUB D0Ar6, D0Ar6, #4
-! Calculate the bit offsets required for the shift operations necesssary
-! to align the data.
-! D0Ar6 = bit offset, D1Ar5 = (32 - bit offset)
- MULW D0Ar6, D0Ar6, #8
- MOV D1Ar5, #32
- SUB D1Ar5, D1Ar5, D0Ar6
-! Move data 4 bytes before we enter the main loop
- MOV D0Re0, D1Re0
-
-$Lloop_5_6_7:
- GETL D0Ar2, D1Ar1, [++A1.2]
-! form 64-bit data in D0Re0, D1Re0
- LSR D0Re0, D0Re0, D0Ar6
- MOV D1Re0, D0Ar2
- LSL D1Re0, D1Re0, D1Ar5
- ADD D0Re0, D0Re0, D1Re0
-
- LSR D0Ar2, D0Ar2, D0Ar6
- LSL D1Re0, D1Ar1, D1Ar5
- ADD D1Re0, D1Re0, D0Ar2
-
- SETL [A0.2++], D0Re0, D1Re0
- MOV D0Re0, D1Ar1
- BR $Lloop_5_6_7
-
- B $Lunaligned_end
-
-$Lunaligned_1_2_3:
-! Calculate the bit offsets required for the shift operations necesssary
-! to align the data.
-! D0Ar6 = bit offset, D1Ar5 = (32 - bit offset)
- MULW D0Ar6, D0Ar6, #8
- MOV D1Ar5, #32
- SUB D1Ar5, D1Ar5, D0Ar6
-
-$Lloop_1_2_3:
-! form 64-bit data in D0Re0,D1Re0
- LSR D0Re0, D0Re0, D0Ar6
- LSL D1Ar1, D1Re0, D1Ar5
- ADD D0Re0, D0Re0, D1Ar1
- MOV D0Ar2, D1Re0
- LSR D0FrT, D0Ar2, D0Ar6
- GETL D0Ar2, D1Ar1, [++A1.2]
-
- MOV D1Re0, D0Ar2
- LSL D1Re0, D1Re0, D1Ar5
- ADD D1Re0, D1Re0, D0FrT
-
- SETL [A0.2++], D0Re0, D1Re0
- MOV D0Re0, D0Ar2
- MOV D1Re0, D1Ar1
- BR $Lloop_1_2_3
-
- B $Lunaligned_end
-
-! The 4 byte mis-alignment case - this does not require any shifting, just a
-! shuffling of registers.
-$Lunaligned_4:
- MOV D0Re0, D1Re0
-$Lloop_4:
- GETL D0Ar2, D1Ar1, [++A1.2]
- MOV D1Re0, D0Ar2
- SETL [A0.2++], D0Re0, D1Re0
- MOV D0Re0, D1Ar1
- BR $Lloop_4
-
-$Lunaligned_end:
-! If there are no remaining bytes to copy, we are done.
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lend
-! Re-adjust the source pointer (A1.2) back to the actual (unaligned) byte
-! address of the remaining bytes, and fall through to the byte copy loop.
- MOV D0Ar6, A1.2
- ADD D1Ar5, D0Ar4, D0Ar6
- MOV A1.2, D1Ar5
- B $Lbyte_copy
-
- .size _memcpy,.-_memcpy
diff --git a/arch/metag/lib/memmove.S b/arch/metag/lib/memmove.S
deleted file mode 100644
index 934abda0e680..000000000000
--- a/arch/metag/lib/memmove.S
+++ /dev/null
@@ -1,346 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2008-2012 Imagination Technologies Ltd.
-
- .text
- .global _memmove
- .type _memmove,function
-! D1Ar1 dst
-! D0Ar2 src
-! D1Ar3 cnt
-! D0Re0 dst
-_memmove:
- CMP D1Ar3, #0
- MOV D0Re0, D1Ar1
- BZ $LEND2
- MSETL [A0StP], D0.5, D0.6, D0.7
- MOV D1Ar5, D0Ar2
- CMP D1Ar1, D1Ar5
- BLT $Lforwards_copy
- SUB D0Ar4, D1Ar1, D1Ar3
- ADD D0Ar4, D0Ar4, #1
- CMP D0Ar2, D0Ar4
- BLT $Lforwards_copy
- ! should copy backwards
- MOV D1Re0, D0Ar2
- ! adjust pointer to the end of mem
- ADD D0Ar2, D1Re0, D1Ar3
- ADD D1Ar1, D1Ar1, D1Ar3
-
- MOV A1.2, D0Ar2
- MOV A0.2, D1Ar1
- CMP D1Ar3, #8
- BLT $Lbbyte_loop
-
- MOV D0Ar4, D0Ar2
- MOV D1Ar5, D1Ar1
-
- ! test 8 byte alignment
- ANDS D1Ar5, D1Ar5, #7
- BNE $Lbdest_unaligned
-
- ANDS D0Ar4, D0Ar4, #7
- BNE $Lbsrc_unaligned
-
- LSR D1Ar5, D1Ar3, #3
-
-$Lbaligned_loop:
- GETL D0Re0, D1Re0, [--A1.2]
- SETL [--A0.2], D0Re0, D1Re0
- SUBS D1Ar5, D1Ar5, #1
- BNE $Lbaligned_loop
-
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lbbyte_loop_exit
-$Lbbyte_loop:
- GETB D1Re0, [--A1.2]
- SETB [--A0.2], D1Re0
- SUBS D1Ar3, D1Ar3, #1
- BNE $Lbbyte_loop
-$Lbbyte_loop_exit:
- MOV D0Re0, A0.2
-$LEND:
- SUB A0.2, A0StP, #24
- MGETL D0.5, D0.6, D0.7, [A0.2]
- SUB A0StP, A0StP, #24
-$LEND2:
- MOV PC, D1RtP
-
-$Lbdest_unaligned:
- GETB D0Re0, [--A1.2]
- SETB [--A0.2], D0Re0
- SUBS D1Ar5, D1Ar5, #1
- SUB D1Ar3, D1Ar3, #1
- BNE $Lbdest_unaligned
- CMP D1Ar3, #8
- BLT $Lbbyte_loop
-$Lbsrc_unaligned:
- LSR D1Ar5, D1Ar3, #3
- ! adjust A1.2
- MOV D0Ar4, A1.2
- ! save original address
- MOV D0Ar6, A1.2
-
- ADD D0Ar4, D0Ar4, #7
- ANDMB D0Ar4, D0Ar4, #0xfff8
- ! new address is the 8-byte aligned one above the original
- MOV A1.2, D0Ar4
-
- ! A0.2 dst 64-bit is aligned
- ! measure the gap size
- SUB D0Ar6, D0Ar4, D0Ar6
- MOVS D0Ar4, D0Ar6
- ! keep this information for the later adjustment
- ! both aligned
- BZ $Lbaligned_loop
-
- ! prefetch
- GETL D0Re0, D1Re0, [--A1.2]
-
- CMP D0Ar6, #4
- BLT $Lbunaligned_1_2_3
- ! 32-bit aligned
- BZ $Lbaligned_4
-
- SUB D0Ar6, D0Ar6, #4
- ! D1.6 stores the gap size in bits
- MULW D1.6, D0Ar6, #8
- MOV D0.6, #32
- ! D0.6 stores the complement of the gap size
- SUB D0.6, D0.6, D1.6
-
-$Lbunaligned_5_6_7:
- GETL D0.7, D1.7, [--A1.2]
- ! form 64-bit data in D0Re0, D1Re0
- MOV D1Re0, D0Re0
- ! D1Re0 << gap-size
- LSL D1Re0, D1Re0, D1.6
- MOV D0Re0, D1.7
- ! D0Re0 >> complement
- LSR D0Re0, D0Re0, D0.6
- MOV D1.5, D0Re0
- ! combine the both
- ADD D1Re0, D1Re0, D1.5
-
- MOV D1.5, D1.7
- LSL D1.5, D1.5, D1.6
- MOV D0Re0, D0.7
- LSR D0Re0, D0Re0, D0.6
- MOV D0.5, D1.5
- ADD D0Re0, D0Re0, D0.5
-
- SETL [--A0.2], D0Re0, D1Re0
- MOV D0Re0, D0.7
- MOV D1Re0, D1.7
- SUBS D1Ar5, D1Ar5, #1
- BNE $Lbunaligned_5_6_7
-
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lbbyte_loop_exit
- ! Adjust A1.2
- ! A1.2 <- A1.2 +8 - gapsize
- ADD A1.2, A1.2, #8
- SUB A1.2, A1.2, D0Ar4
- B $Lbbyte_loop
-
-$Lbunaligned_1_2_3:
- MULW D1.6, D0Ar6, #8
- MOV D0.6, #32
- SUB D0.6, D0.6, D1.6
-
-$Lbunaligned_1_2_3_loop:
- GETL D0.7, D1.7, [--A1.2]
- ! form 64-bit data in D0Re0, D1Re0
- LSL D1Re0, D1Re0, D1.6
- ! save D0Re0 for later use
- MOV D0.5, D0Re0
- LSR D0Re0, D0Re0, D0.6
- MOV D1.5, D0Re0
- ADD D1Re0, D1Re0, D1.5
-
- ! orignal data in D0Re0
- MOV D1.5, D0.5
- LSL D1.5, D1.5, D1.6
- MOV D0Re0, D1.7
- LSR D0Re0, D0Re0, D0.6
- MOV D0.5, D1.5
- ADD D0Re0, D0Re0, D0.5
-
- SETL [--A0.2], D0Re0, D1Re0
- MOV D0Re0, D0.7
- MOV D1Re0, D1.7
- SUBS D1Ar5, D1Ar5, #1
- BNE $Lbunaligned_1_2_3_loop
-
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lbbyte_loop_exit
- ! Adjust A1.2
- ADD A1.2, A1.2, #8
- SUB A1.2, A1.2, D0Ar4
- B $Lbbyte_loop
-
-$Lbaligned_4:
- GETL D0.7, D1.7, [--A1.2]
- MOV D1Re0, D0Re0
- MOV D0Re0, D1.7
- SETL [--A0.2], D0Re0, D1Re0
- MOV D0Re0, D0.7
- MOV D1Re0, D1.7
- SUBS D1Ar5, D1Ar5, #1
- BNE $Lbaligned_4
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lbbyte_loop_exit
- ! Adjust A1.2
- ADD A1.2, A1.2, #8
- SUB A1.2, A1.2, D0Ar4
- B $Lbbyte_loop
-
-$Lforwards_copy:
- MOV A1.2, D0Ar2
- MOV A0.2, D1Ar1
- CMP D1Ar3, #8
- BLT $Lfbyte_loop
-
- MOV D0Ar4, D0Ar2
- MOV D1Ar5, D1Ar1
-
- ANDS D1Ar5, D1Ar5, #7
- BNE $Lfdest_unaligned
-
- ANDS D0Ar4, D0Ar4, #7
- BNE $Lfsrc_unaligned
-
- LSR D1Ar5, D1Ar3, #3
-
-$Lfaligned_loop:
- GETL D0Re0, D1Re0, [A1.2++]
- SUBS D1Ar5, D1Ar5, #1
- SETL [A0.2++], D0Re0, D1Re0
- BNE $Lfaligned_loop
-
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lfbyte_loop_exit
-$Lfbyte_loop:
- GETB D1Re0, [A1.2++]
- SETB [A0.2++], D1Re0
- SUBS D1Ar3, D1Ar3, #1
- BNE $Lfbyte_loop
-$Lfbyte_loop_exit:
- MOV D0Re0, D1Ar1
- B $LEND
-
-$Lfdest_unaligned:
- GETB D0Re0, [A1.2++]
- ADD D1Ar5, D1Ar5, #1
- SUB D1Ar3, D1Ar3, #1
- SETB [A0.2++], D0Re0
- CMP D1Ar5, #8
- BNE $Lfdest_unaligned
- CMP D1Ar3, #8
- BLT $Lfbyte_loop
-$Lfsrc_unaligned:
- ! adjust A1.2
- LSR D1Ar5, D1Ar3, #3
-
- MOV D0Ar4, A1.2
- MOV D0Ar6, A1.2
- ANDMB D0Ar4, D0Ar4, #0xfff8
- MOV A1.2, D0Ar4
-
- ! A0.2 dst 64-bit is aligned
- SUB D0Ar6, D0Ar6, D0Ar4
- ! keep the information for the later adjustment
- MOVS D0Ar4, D0Ar6
-
- ! both aligned
- BZ $Lfaligned_loop
-
- ! prefetch
- GETL D0Re0, D1Re0, [A1.2]
-
- CMP D0Ar6, #4
- BLT $Lfunaligned_1_2_3
- BZ $Lfaligned_4
-
- SUB D0Ar6, D0Ar6, #4
- MULW D0.6, D0Ar6, #8
- MOV D1.6, #32
- SUB D1.6, D1.6, D0.6
-
-$Lfunaligned_5_6_7:
- GETL D0.7, D1.7, [++A1.2]
- ! form 64-bit data in D0Re0, D1Re0
- MOV D0Re0, D1Re0
- LSR D0Re0, D0Re0, D0.6
- MOV D1Re0, D0.7
- LSL D1Re0, D1Re0, D1.6
- MOV D0.5, D1Re0
- ADD D0Re0, D0Re0, D0.5
-
- MOV D0.5, D0.7
- LSR D0.5, D0.5, D0.6
- MOV D1Re0, D1.7
- LSL D1Re0, D1Re0, D1.6
- MOV D1.5, D0.5
- ADD D1Re0, D1Re0, D1.5
-
- SETL [A0.2++], D0Re0, D1Re0
- MOV D0Re0, D0.7
- MOV D1Re0, D1.7
- SUBS D1Ar5, D1Ar5, #1
- BNE $Lfunaligned_5_6_7
-
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lfbyte_loop_exit
- ! Adjust A1.2
- ADD A1.2, A1.2, D0Ar4
- B $Lfbyte_loop
-
-$Lfunaligned_1_2_3:
- MULW D0.6, D0Ar6, #8
- MOV D1.6, #32
- SUB D1.6, D1.6, D0.6
-
-$Lfunaligned_1_2_3_loop:
- GETL D0.7, D1.7, [++A1.2]
- ! form 64-bit data in D0Re0, D1Re0
- LSR D0Re0, D0Re0, D0.6
- MOV D1.5, D1Re0
- LSL D1Re0, D1Re0, D1.6
- MOV D0.5, D1Re0
- ADD D0Re0, D0Re0, D0.5
-
- MOV D0.5, D1.5
- LSR D0.5, D0.5, D0.6
- MOV D1Re0, D0.7
- LSL D1Re0, D1Re0, D1.6
- MOV D1.5, D0.5
- ADD D1Re0, D1Re0, D1.5
-
- SETL [A0.2++], D0Re0, D1Re0
- MOV D0Re0, D0.7
- MOV D1Re0, D1.7
- SUBS D1Ar5, D1Ar5, #1
- BNE $Lfunaligned_1_2_3_loop
-
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lfbyte_loop_exit
- ! Adjust A1.2
- ADD A1.2, A1.2, D0Ar4
- B $Lfbyte_loop
-
-$Lfaligned_4:
- GETL D0.7, D1.7, [++A1.2]
- MOV D0Re0, D1Re0
- MOV D1Re0, D0.7
- SETL [A0.2++], D0Re0, D1Re0
- MOV D0Re0, D0.7
- MOV D1Re0, D1.7
- SUBS D1Ar5, D1Ar5, #1
- BNE $Lfaligned_4
- ANDS D1Ar3, D1Ar3, #7
- BZ $Lfbyte_loop_exit
- ! Adjust A1.2
- ADD A1.2, A1.2, D0Ar4
- B $Lfbyte_loop
-
- .size _memmove,.-_memmove
diff --git a/arch/metag/lib/memset.S b/arch/metag/lib/memset.S
deleted file mode 100644
index 6ee246d831c7..000000000000
--- a/arch/metag/lib/memset.S
+++ /dev/null
@@ -1,87 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2008-2012 Imagination Technologies Ltd.
-
- .text
- .global _memset
- .type _memset,function
-! D1Ar1 dst
-! D0Ar2 c
-! D1Ar3 cnt
-! D0Re0 dst
-_memset:
- AND D0Ar2,D0Ar2,#0xFF ! Ensure a byte input value
- MULW D0Ar2,D0Ar2,#0x0101 ! Duplicate byte value into 0-15
- ANDS D0Ar4,D1Ar1,#7 ! Extract bottom LSBs of dst
- LSL D0Re0,D0Ar2,#16 ! Duplicate byte value into 16-31
- ADD A0.2,D0Ar2,D0Re0 ! Duplicate byte value into 4 (A0.2)
- MOV D0Re0,D1Ar1 ! Return dst
- BZ $LLongStub ! if start address is aligned
- ! start address is not aligned on an 8 byte boundary, so we
- ! need the number of bytes up to the next 8 byte address
- ! boundary, or the length of the string if less than 8, in D1Ar5
- MOV D0Ar2,#8 ! Need 8 - N in D1Ar5 ...
- SUB D1Ar5,D0Ar2,D0Ar4 ! ... subtract N
- CMP D1Ar3,D1Ar5
- MOVMI D1Ar5,D1Ar3
- B $LByteStub ! dst is mis-aligned, do $LByteStub
-
-!
-! Preamble to LongLoop which generates 4*8 bytes per interation (5 cycles)
-!
-$LLongStub:
- LSRS D0Ar2,D1Ar3,#5
- AND D1Ar3,D1Ar3,#0x1F
- MOV A1.2,A0.2
- BEQ $LLongishStub
- SUB TXRPT,D0Ar2,#1
- CMP D1Ar3,#0
-$LLongLoop:
- SETL [D1Ar1++],A0.2,A1.2
- SETL [D1Ar1++],A0.2,A1.2
- SETL [D1Ar1++],A0.2,A1.2
- SETL [D1Ar1++],A0.2,A1.2
- BR $LLongLoop
- BZ $Lexit
-!
-! Preamble to LongishLoop which generates 1*8 bytes per interation (2 cycles)
-!
-$LLongishStub:
- LSRS D0Ar2,D1Ar3,#3
- AND D1Ar3,D1Ar3,#0x7
- MOV D1Ar5,D1Ar3
- BEQ $LByteStub
- SUB TXRPT,D0Ar2,#1
- CMP D1Ar3,#0
-$LLongishLoop:
- SETL [D1Ar1++],A0.2,A1.2
- BR $LLongishLoop
- BZ $Lexit
-!
-! This does a byte structured burst of up to 7 bytes
-!
-! D1Ar1 should point to the location required
-! D1Ar3 should be the remaining total byte count
-! D1Ar5 should be burst size (<= D1Ar3)
-!
-$LByteStub:
- SUBS D1Ar3,D1Ar3,D1Ar5 ! Reduce count
- ADD D1Ar1,D1Ar1,D1Ar5 ! Advance pointer to end of area
- MULW D1Ar5,D1Ar5,#4 ! Scale to (1*4), (2*4), (3*4)
- SUB D1Ar5,D1Ar5,#(8*4) ! Rebase to -(7*4), -(6*4), -(5*4), ...
- MOV A1.2,D1Ar5
- SUB PC,CPC1,A1.2 ! Jump into table below
- SETB [D1Ar1+#(-7)],A0.2
- SETB [D1Ar1+#(-6)],A0.2
- SETB [D1Ar1+#(-5)],A0.2
- SETB [D1Ar1+#(-4)],A0.2
- SETB [D1Ar1+#(-3)],A0.2
- SETB [D1Ar1+#(-2)],A0.2
- SETB [D1Ar1+#(-1)],A0.2
-!
-! Return if all data has been output, otherwise do $LLongStub
-!
- BNZ $LLongStub
-$Lexit:
- MOV PC,D1RtP
- .size _memset,.-_memset
-
diff --git a/arch/metag/lib/modsi3.S b/arch/metag/lib/modsi3.S
deleted file mode 100644
index d65a2e5b3154..000000000000
--- a/arch/metag/lib/modsi3.S
+++ /dev/null
@@ -1,39 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
-! Imagination Technologies Ltd
-!
-! Integer modulus routines.
-!
-!!
-!! 32-bit modulus unsigned i/p - passed unsigned 32-bit numbers
-!!
- .text
- .global ___umodsi3
- .type ___umodsi3,function
- .align 2
-___umodsi3:
- MOV D0FrT,D1RtP ! Save original return address
- CALLR D1RtP,___udivsi3
- MOV D1RtP,D0FrT ! Recover return address
- MOV D0Re0,D1Ar1 ! Return remainder
- MOV PC,D1RtP
- .size ___umodsi3,.-___umodsi3
-
-!!
-!! 32-bit modulus signed i/p - passed signed 32-bit numbers
-!!
- .global ___modsi3
- .type ___modsi3,function
- .align 2
-___modsi3:
- MOV D0FrT,D1RtP ! Save original return address
- MOV A0.2,D1Ar1 ! Save A in A0.2
- CALLR D1RtP,___divsi3
- MOV D1RtP,D0FrT ! Recover return address
- MOV D1Re0,A0.2 ! Recover A
- MOV D0Re0,D1Ar1 ! Return remainder
- ORS D1Re0,D1Re0,D1Re0 ! Was A negative?
- NEG D1Ar1,D1Ar1 ! Negate remainder
- MOVMI D0Re0,D1Ar1 ! Return neg remainder
- MOV PC, D1RtP
- .size ___modsi3,.-___modsi3
diff --git a/arch/metag/lib/muldi3.S b/arch/metag/lib/muldi3.S
deleted file mode 100644
index 9d106790244d..000000000000
--- a/arch/metag/lib/muldi3.S
+++ /dev/null
@@ -1,45 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2012 by Imagination Technologies Ltd.
-!
-! 64-bit multiply routine.
-!
-
-!
-! 64-bit signed/unsigned multiply
-!
-! A = D1Ar1:D0Ar2 = a 2^48 + b 2^32 + c 2^16 + d 2^0
-!
-! B = D1Ar3:D0Ar4 = w 2^48 + x 2^32 + y 2^16 + z 2^0
-!
- .text
- .global ___muldi3
- .type ___muldi3,function
-
-___muldi3:
- MULD D1Re0,D1Ar1,D0Ar4 ! (a 2^48 + b 2^32)(y 2^16 + z 2^0)
- MULD D0Re0,D0Ar2,D1Ar3 ! (w 2^48 + x 2^32)(c 2^16 + d 2^0)
- ADD D1Re0,D1Re0,D0Re0
-
- MULW D0Re0,D0Ar2,D0Ar4 ! (d 2^0) * (z 2^0)
-
- RTDW D0Ar2,D0Ar2
- MULW D0Ar6,D0Ar2,D0Ar4 ! (c 2^16)(z 2^0)
- LSR D1Ar5,D0Ar6,#16
- LSL D0Ar6,D0Ar6,#16
- ADDS D0Re0,D0Re0,D0Ar6
- ADDCS D1Re0,D1Re0,#1
- RTDW D0Ar4,D0Ar4
- ADD D1Re0,D1Re0,D1Ar5
-
- MULW D0Ar6,D0Ar2,D0Ar4 ! (c 2^16)(y 2^16)
- ADD D1Re0,D1Re0,D0Ar6
-
- RTDW D0Ar2,D0Ar2
- MULW D0Ar6,D0Ar2,D0Ar4 ! (d 2^0)(y 2^16)
- LSR D1Ar5,D0Ar6,#16
- LSL D0Ar6,D0Ar6,#16
- ADDS D0Re0,D0Re0,D0Ar6
- ADD D1Re0,D1Re0,D1Ar5
- ADDCS D1Re0,D1Re0,#1
- MOV PC, D1RtP
- .size ___muldi3,.-___muldi3
diff --git a/arch/metag/lib/ucmpdi2.S b/arch/metag/lib/ucmpdi2.S
deleted file mode 100644
index 46f5686db8b1..000000000000
--- a/arch/metag/lib/ucmpdi2.S
+++ /dev/null
@@ -1,28 +0,0 @@
-! SPDX-License-Identifier: GPL-2.0
-! Copyright (C) 2012 by Imagination Technologies Ltd.
-!
-! 64-bit unsigned compare routine.
-!
-
- .text
- .global ___ucmpdi2
- .type ___ucmpdi2,function
-
-! low high
-! u64 a (D0Ar2, D1Ar1)
-! u64 b (D0Ar4, D1Ar3)
-___ucmpdi2:
- ! start at 1 (equal) and conditionally increment or decrement
- MOV D0Re0,#1
-
- ! high words
- CMP D1Ar1,D1Ar3
- ! or if equal, low words
- CMPEQ D0Ar2,D0Ar4
-
- ! unsigned compare
- SUBLO D0Re0,D0Re0,#1
- ADDHI D0Re0,D0Re0,#1
-
- MOV PC,D1RtP
- .size ___ucmpdi2,.-___ucmpdi2
diff --git a/arch/metag/lib/usercopy.c b/arch/metag/lib/usercopy.c
deleted file mode 100644
index a48ef522c02d..000000000000
--- a/arch/metag/lib/usercopy.c
+++ /dev/null
@@ -1,1257 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * User address space access functions.
- * The non-inlined parts of asm-metag/uaccess.h are here.
- *
- * Copyright (C) 2006, Imagination Technologies.
- * Copyright (C) 2000, Axis Communications AB.
- *
- * Written by Hans-Peter Nilsson.
- * Pieces used from memcpy, originally by Kenny Ranerup long time ago.
- * Modified for Meta by Will Newton.
- */
-
-#include <linux/export.h>
-#include <linux/uaccess.h>
-#include <asm/cache.h> /* def of L1_CACHE_BYTES */
-
-#define USE_RAPF
-#define RAPF_MIN_BUF_SIZE (3*L1_CACHE_BYTES)
-
-
-/* The "double write" in this code is because the Meta will not fault
- * immediately unless the memory pipe is forced to by e.g. a data stall or
- * another memory op. The second write should be discarded by the write
- * combiner so should have virtually no cost.
- */
-
-#define __asm_copy_user_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- asm volatile ( \
- COPY \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " MOVT D1Ar1,#HI(1b)\n" \
- " JUMP D1Ar1,#LO(1b)\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous\n" \
- : "=r" (to), "=r" (from), "=r" (ret) \
- : "0" (to), "1" (from), "2" (ret) \
- : "D1Ar1", "memory")
-
-
-#define __asm_copy_to_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "2: SETB [%0++],D1Ar1\n", \
- "3: ADD %2,%2,#1\n", \
- " .long 2b,3b\n")
-
-#define __asm_copy_to_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " GETW D1Ar1,[%1++]\n" \
- " SETW [%0],D1Ar1\n" \
- "2: SETW [%0++],D1Ar1\n" COPY, \
- "3: ADD %2,%2,#2\n" FIXUP, \
- " .long 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_2(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_3(to, from, ret) \
- __asm_copy_to_user_2x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "4: SETB [%0++],D1Ar1\n", \
- "5: ADD %2,%2,#1\n", \
- " .long 4b,5b\n")
-
-#define __asm_copy_to_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " GETD D1Ar1,[%1++]\n" \
- " SETD [%0],D1Ar1\n" \
- "2: SETD [%0++],D1Ar1\n" COPY, \
- "3: ADD %2,%2,#4\n" FIXUP, \
- " .long 2b,3b\n" TENTRY)
-
-#define __asm_copy_to_user_4(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_5(to, from, ret) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "4: SETB [%0++],D1Ar1\n", \
- "5: ADD %2,%2,#1\n", \
- " .long 4b,5b\n")
-
-#define __asm_copy_to_user_6x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " GETW D1Ar1,[%1++]\n" \
- " SETW [%0],D1Ar1\n" \
- "4: SETW [%0++],D1Ar1\n" COPY, \
- "5: ADD %2,%2,#2\n" FIXUP, \
- " .long 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_6(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_7(to, from, ret) \
- __asm_copy_to_user_6x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "6: SETB [%0++],D1Ar1\n", \
- "7: ADD %2,%2,#1\n", \
- " .long 6b,7b\n")
-
-#define __asm_copy_to_user_8x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_4x_cont(to, from, ret, \
- " GETD D1Ar1,[%1++]\n" \
- " SETD [%0],D1Ar1\n" \
- "4: SETD [%0++],D1Ar1\n" COPY, \
- "5: ADD %2,%2,#4\n" FIXUP, \
- " .long 4b,5b\n" TENTRY)
-
-#define __asm_copy_to_user_8(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_9(to, from, ret) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "6: SETB [%0++],D1Ar1\n", \
- "7: ADD %2,%2,#1\n", \
- " .long 6b,7b\n")
-
-#define __asm_copy_to_user_10x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " GETW D1Ar1,[%1++]\n" \
- " SETW [%0],D1Ar1\n" \
- "6: SETW [%0++],D1Ar1\n" COPY, \
- "7: ADD %2,%2,#2\n" FIXUP, \
- " .long 6b,7b\n" TENTRY)
-
-#define __asm_copy_to_user_10(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_11(to, from, ret) \
- __asm_copy_to_user_10x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "8: SETB [%0++],D1Ar1\n", \
- "9: ADD %2,%2,#1\n", \
- " .long 8b,9b\n")
-
-#define __asm_copy_to_user_12x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_8x_cont(to, from, ret, \
- " GETD D1Ar1,[%1++]\n" \
- " SETD [%0],D1Ar1\n" \
- "6: SETD [%0++],D1Ar1\n" COPY, \
- "7: ADD %2,%2,#4\n" FIXUP, \
- " .long 6b,7b\n" TENTRY)
-#define __asm_copy_to_user_12(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_13(to, from, ret) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "8: SETB [%0++],D1Ar1\n", \
- "9: ADD %2,%2,#1\n", \
- " .long 8b,9b\n")
-
-#define __asm_copy_to_user_14x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " GETW D1Ar1,[%1++]\n" \
- " SETW [%0],D1Ar1\n" \
- "8: SETW [%0++],D1Ar1\n" COPY, \
- "9: ADD %2,%2,#2\n" FIXUP, \
- " .long 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_14(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_15(to, from, ret) \
- __asm_copy_to_user_14x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- " SETB [%0],D1Ar1\n" \
- "10: SETB [%0++],D1Ar1\n", \
- "11: ADD %2,%2,#1\n", \
- " .long 10b,11b\n")
-
-#define __asm_copy_to_user_16x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_to_user_12x_cont(to, from, ret, \
- " GETD D1Ar1,[%1++]\n" \
- " SETD [%0],D1Ar1\n" \
- "8: SETD [%0++],D1Ar1\n" COPY, \
- "9: ADD %2,%2,#4\n" FIXUP, \
- " .long 8b,9b\n" TENTRY)
-
-#define __asm_copy_to_user_16(to, from, ret) \
- __asm_copy_to_user_16x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_to_user_8x64(to, from, ret) \
- asm volatile ( \
- " GETL D0Ar2,D1Ar1,[%1++]\n" \
- " SETL [%0],D0Ar2,D1Ar1\n" \
- "2: SETL [%0++],D0Ar2,D1Ar1\n" \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: ADD %2,%2,#8\n" \
- " MOVT D0Ar2,#HI(1b)\n" \
- " JUMP D0Ar2,#LO(1b)\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .long 2b,3b\n" \
- " .previous\n" \
- : "=r" (to), "=r" (from), "=r" (ret) \
- : "0" (to), "1" (from), "2" (ret) \
- : "D1Ar1", "D0Ar2", "memory")
-
-/*
- * optimized copying loop using RAPF when 64 bit aligned
- *
- * n will be automatically decremented inside the loop
- * ret will be left intact. if error occurs we will rewind
- * so that the original non optimized code will fill up
- * this value correctly.
- *
- * on fault:
- * > n will hold total number of uncopied bytes
- *
- * > {'to','from'} will be rewind back so that
- * the non-optimized code will do the proper fix up
- *
- * DCACHE drops the cacheline which helps in reducing cache
- * pollution.
- *
- * We introduce an extra SETL at the end of the loop to
- * ensure we don't fall off the loop before we catch all
- * erros.
- *
- * NOTICE:
- * LSM_STEP in TXSTATUS must be cleared in fix up code.
- * since we're using M{S,G}ETL, a fault might happen at
- * any address in the middle of M{S,G}ETL causing
- * the value of LSM_STEP to be incorrect which can
- * cause subsequent use of M{S,G}ET{L,D} to go wrong.
- * ie: if LSM_STEP was 1 when a fault occurs, the
- * next call to M{S,G}ET{L,D} will skip the first
- * copy/getting as it think that the first 1 has already
- * been done.
- *
- */
-#define __asm_copy_user_64bit_rapf_loop( \
- to, from, ret, n, id, FIXUP) \
- asm volatile ( \
- ".balign 8\n" \
- " MOV RAPF, %1\n" \
- " MSETL [A0StP++], D0Ar6, D0FrT, D0.5, D0.6, D0.7\n" \
- " MOV D0Ar6, #0\n" \
- " LSR D1Ar5, %3, #6\n" \
- " SUB TXRPT, D1Ar5, #2\n" \
- " MOV RAPF, %1\n" \
- "$Lloop"id":\n" \
- " ADD RAPF, %1, #64\n" \
- "21: MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "22: MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "23: SUB %3, %3, #32\n" \
- "24: MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "25: MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "26: SUB %3, %3, #32\n" \
- " DCACHE [%1+#-64], D0Ar6\n" \
- " BR $Lloop"id"\n" \
- \
- " MOV RAPF, %1\n" \
- "27: MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "28: MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "29: SUB %3, %3, #32\n" \
- "30: MGETL D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "31: MSETL [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "32: SETL [%0+#-8], D0.7, D1.7\n" \
- " SUB %3, %3, #32\n" \
- "1: DCACHE [%1+#-64], D0Ar6\n" \
- " GETL D0Ar6, D1Ar5, [A0StP+#-40]\n" \
- " GETL D0FrT, D1RtP, [A0StP+#-32]\n" \
- " GETL D0.5, D1.5, [A0StP+#-24]\n" \
- " GETL D0.6, D1.6, [A0StP+#-16]\n" \
- " GETL D0.7, D1.7, [A0StP+#-8]\n" \
- " SUB A0StP, A0StP, #40\n" \
- " .section .fixup,\"ax\"\n" \
- "3: MOV D0Ar2, TXSTATUS\n" \
- " MOV D1Ar1, TXSTATUS\n" \
- " AND D1Ar1, D1Ar1, #0xFFFFF8FF\n" \
- " MOV TXSTATUS, D1Ar1\n" \
- FIXUP \
- " MOVT D0Ar2, #HI(1b)\n" \
- " JUMP D0Ar2, #LO(1b)\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .long 21b,3b\n" \
- " .long 22b,3b\n" \
- " .long 23b,3b\n" \
- " .long 24b,3b\n" \
- " .long 25b,3b\n" \
- " .long 26b,3b\n" \
- " .long 27b,3b\n" \
- " .long 28b,3b\n" \
- " .long 29b,3b\n" \
- " .long 30b,3b\n" \
- " .long 31b,3b\n" \
- " .long 32b,3b\n" \
- " .previous\n" \
- : "=r" (to), "=r" (from), "=r" (ret), "=d" (n) \
- : "0" (to), "1" (from), "2" (ret), "3" (n) \
- : "D1Ar1", "D0Ar2", "cc", "memory")
-
-/* rewind 'to' and 'from' pointers when a fault occurs
- *
- * Rationale:
- * A fault always occurs on writing to user buffer. A fault
- * is at a single address, so we need to rewind by only 4
- * bytes.
- * Since we do a complete read from kernel buffer before
- * writing, we need to rewind it also. The amount to be
- * rewind equals the number of faulty writes in MSETD
- * which is: [4 - (LSM_STEP-1)]*8
- * LSM_STEP is bits 10:8 in TXSTATUS which is already read
- * and stored in D0Ar2
- *
- * NOTE: If a fault occurs at the last operation in M{G,S}ETL
- * LSM_STEP will be 0. ie: we do 4 writes in our case, if
- * a fault happens at the 4th write, LSM_STEP will be 0
- * instead of 4. The code copes with that.
- *
- * n is updated by the number of successful writes, which is:
- * n = n - (LSM_STEP-1)*8
- */
-#define __asm_copy_to_user_64bit_rapf_loop(to, from, ret, n, id)\
- __asm_copy_user_64bit_rapf_loop(to, from, ret, n, id, \
- "LSR D0Ar2, D0Ar2, #8\n" \
- "ANDS D0Ar2, D0Ar2, #0x7\n" \
- "ADDZ D0Ar2, D0Ar2, #4\n" \
- "SUB D0Ar2, D0Ar2, #1\n" \
- "MOV D1Ar1, #4\n" \
- "SUB D0Ar2, D1Ar1, D0Ar2\n" \
- "LSL D0Ar2, D0Ar2, #3\n" \
- "LSL D1Ar1, D1Ar1, #3\n" \
- "SUB D1Ar1, D1Ar1, D0Ar2\n" \
- "SUB %0, %0, #8\n" \
- "SUB %1, %1,D0Ar2\n" \
- "SUB %3, %3, D1Ar1\n")
-
-/*
- * optimized copying loop using RAPF when 32 bit aligned
- *
- * n will be automatically decremented inside the loop
- * ret will be left intact. if error occurs we will rewind
- * so that the original non optimized code will fill up
- * this value correctly.
- *
- * on fault:
- * > n will hold total number of uncopied bytes
- *
- * > {'to','from'} will be rewind back so that
- * the non-optimized code will do the proper fix up
- *
- * DCACHE drops the cacheline which helps in reducing cache
- * pollution.
- *
- * We introduce an extra SETD at the end of the loop to
- * ensure we don't fall off the loop before we catch all
- * erros.
- *
- * NOTICE:
- * LSM_STEP in TXSTATUS must be cleared in fix up code.
- * since we're using M{S,G}ETL, a fault might happen at
- * any address in the middle of M{S,G}ETL causing
- * the value of LSM_STEP to be incorrect which can
- * cause subsequent use of M{S,G}ET{L,D} to go wrong.
- * ie: if LSM_STEP was 1 when a fault occurs, the
- * next call to M{S,G}ET{L,D} will skip the first
- * copy/getting as it think that the first 1 has already
- * been done.
- *
- */
-#define __asm_copy_user_32bit_rapf_loop( \
- to, from, ret, n, id, FIXUP) \
- asm volatile ( \
- ".balign 8\n" \
- " MOV RAPF, %1\n" \
- " MSETL [A0StP++], D0Ar6, D0FrT, D0.5, D0.6, D0.7\n" \
- " MOV D0Ar6, #0\n" \
- " LSR D1Ar5, %3, #6\n" \
- " SUB TXRPT, D1Ar5, #2\n" \
- " MOV RAPF, %1\n" \
- "$Lloop"id":\n" \
- " ADD RAPF, %1, #64\n" \
- "21: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "22: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "23: SUB %3, %3, #16\n" \
- "24: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "25: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "26: SUB %3, %3, #16\n" \
- "27: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "28: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "29: SUB %3, %3, #16\n" \
- "30: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "31: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "32: SUB %3, %3, #16\n" \
- " DCACHE [%1+#-64], D0Ar6\n" \
- " BR $Lloop"id"\n" \
- \
- " MOV RAPF, %1\n" \
- "33: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "34: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "35: SUB %3, %3, #16\n" \
- "36: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "37: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "38: SUB %3, %3, #16\n" \
- "39: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "40: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "41: SUB %3, %3, #16\n" \
- "42: MGETD D0FrT, D0.5, D0.6, D0.7, [%1++]\n" \
- "43: MSETD [%0++], D0FrT, D0.5, D0.6, D0.7\n" \
- "44: SETD [%0+#-4], D0.7\n" \
- " SUB %3, %3, #16\n" \
- "1: DCACHE [%1+#-64], D0Ar6\n" \
- " GETL D0Ar6, D1Ar5, [A0StP+#-40]\n" \
- " GETL D0FrT, D1RtP, [A0StP+#-32]\n" \
- " GETL D0.5, D1.5, [A0StP+#-24]\n" \
- " GETL D0.6, D1.6, [A0StP+#-16]\n" \
- " GETL D0.7, D1.7, [A0StP+#-8]\n" \
- " SUB A0StP, A0StP, #40\n" \
- " .section .fixup,\"ax\"\n" \
- "3: MOV D0Ar2, TXSTATUS\n" \
- " MOV D1Ar1, TXSTATUS\n" \
- " AND D1Ar1, D1Ar1, #0xFFFFF8FF\n" \
- " MOV TXSTATUS, D1Ar1\n" \
- FIXUP \
- " MOVT D0Ar2, #HI(1b)\n" \
- " JUMP D0Ar2, #LO(1b)\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .long 21b,3b\n" \
- " .long 22b,3b\n" \
- " .long 23b,3b\n" \
- " .long 24b,3b\n" \
- " .long 25b,3b\n" \
- " .long 26b,3b\n" \
- " .long 27b,3b\n" \
- " .long 28b,3b\n" \
- " .long 29b,3b\n" \
- " .long 30b,3b\n" \
- " .long 31b,3b\n" \
- " .long 32b,3b\n" \
- " .long 33b,3b\n" \
- " .long 34b,3b\n" \
- " .long 35b,3b\n" \
- " .long 36b,3b\n" \
- " .long 37b,3b\n" \
- " .long 38b,3b\n" \
- " .long 39b,3b\n" \
- " .long 40b,3b\n" \
- " .long 41b,3b\n" \
- " .long 42b,3b\n" \
- " .long 43b,3b\n" \
- " .long 44b,3b\n" \
- " .previous\n" \
- : "=r" (to), "=r" (from), "=r" (ret), "=d" (n) \
- : "0" (to), "1" (from), "2" (ret), "3" (n) \
- : "D1Ar1", "D0Ar2", "cc", "memory")
-
-/* rewind 'to' and 'from' pointers when a fault occurs
- *
- * Rationale:
- * A fault always occurs on writing to user buffer. A fault
- * is at a single address, so we need to rewind by only 4
- * bytes.
- * Since we do a complete read from kernel buffer before
- * writing, we need to rewind it also. The amount to be
- * rewind equals the number of faulty writes in MSETD
- * which is: [4 - (LSM_STEP-1)]*4
- * LSM_STEP is bits 10:8 in TXSTATUS which is already read
- * and stored in D0Ar2
- *
- * NOTE: If a fault occurs at the last operation in M{G,S}ETL
- * LSM_STEP will be 0. ie: we do 4 writes in our case, if
- * a fault happens at the 4th write, LSM_STEP will be 0
- * instead of 4. The code copes with that.
- *
- * n is updated by the number of successful writes, which is:
- * n = n - (LSM_STEP-1)*4
- */
-#define __asm_copy_to_user_32bit_rapf_loop(to, from, ret, n, id)\
- __asm_copy_user_32bit_rapf_loop(to, from, ret, n, id, \
- "LSR D0Ar2, D0Ar2, #8\n" \
- "ANDS D0Ar2, D0Ar2, #0x7\n" \
- "ADDZ D0Ar2, D0Ar2, #4\n" \
- "SUB D0Ar2, D0Ar2, #1\n" \
- "MOV D1Ar1, #4\n" \
- "SUB D0Ar2, D1Ar1, D0Ar2\n" \
- "LSL D0Ar2, D0Ar2, #2\n" \
- "LSL D1Ar1, D1Ar1, #2\n" \
- "SUB D1Ar1, D1Ar1, D0Ar2\n" \
- "SUB %0, %0, #4\n" \
- "SUB %1, %1, D0Ar2\n" \
- "SUB %3, %3, D1Ar1\n")
-
-unsigned long raw_copy_to_user(void __user *pdst, const void *psrc,
- unsigned long n)
-{
- register char __user *dst asm ("A0.2") = pdst;
- register const char *src asm ("A1.2") = psrc;
- unsigned long retn = 0;
-
- if (n == 0)
- return 0;
-
- if ((unsigned long) src & 1) {
- __asm_copy_to_user_1(dst, src, retn);
- n--;
- if (retn)
- return retn + n;
- }
- if ((unsigned long) dst & 1) {
- /* Worst case - byte copy */
- while (n > 0) {
- __asm_copy_to_user_1(dst, src, retn);
- n--;
- if (retn)
- return retn + n;
- }
- }
- if (((unsigned long) src & 2) && n >= 2) {
- __asm_copy_to_user_2(dst, src, retn);
- n -= 2;
- if (retn)
- return retn + n;
- }
- if ((unsigned long) dst & 2) {
- /* Second worst case - word copy */
- while (n >= 2) {
- __asm_copy_to_user_2(dst, src, retn);
- n -= 2;
- if (retn)
- return retn + n;
- }
- }
-
-#ifdef USE_RAPF
- /* 64 bit copy loop */
- if (!(((unsigned long) src | (__force unsigned long) dst) & 7)) {
- if (n >= RAPF_MIN_BUF_SIZE) {
- /* copy user using 64 bit rapf copy */
- __asm_copy_to_user_64bit_rapf_loop(dst, src, retn,
- n, "64cu");
- }
- while (n >= 8) {
- __asm_copy_to_user_8x64(dst, src, retn);
- n -= 8;
- if (retn)
- return retn + n;
- }
- }
- if (n >= RAPF_MIN_BUF_SIZE) {
- /* copy user using 32 bit rapf copy */
- __asm_copy_to_user_32bit_rapf_loop(dst, src, retn, n, "32cu");
- }
-#else
- /* 64 bit copy loop */
- if (!(((unsigned long) src | (__force unsigned long) dst) & 7)) {
- while (n >= 8) {
- __asm_copy_to_user_8x64(dst, src, retn);
- n -= 8;
- if (retn)
- return retn + n;
- }
- }
-#endif
-
- while (n >= 16) {
- __asm_copy_to_user_16(dst, src, retn);
- n -= 16;
- if (retn)
- return retn + n;
- }
-
- while (n >= 4) {
- __asm_copy_to_user_4(dst, src, retn);
- n -= 4;
- if (retn)
- return retn + n;
- }
-
- switch (n) {
- case 0:
- break;
- case 1:
- __asm_copy_to_user_1(dst, src, retn);
- break;
- case 2:
- __asm_copy_to_user_2(dst, src, retn);
- break;
- case 3:
- __asm_copy_to_user_3(dst, src, retn);
- break;
- }
-
- /*
- * If we get here, retn correctly reflects the number of failing
- * bytes.
- */
- return retn;
-}
-EXPORT_SYMBOL(raw_copy_to_user);
-
-#define __asm_copy_from_user_1(to, from, ret) \
- __asm_copy_user_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- "2: SETB [%0++],D1Ar1\n", \
- "3: ADD %2,%2,#1\n", \
- " .long 2b,3b\n")
-
-#define __asm_copy_from_user_2x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " GETW D1Ar1,[%1++]\n" \
- "2: SETW [%0++],D1Ar1\n" COPY, \
- "3: ADD %2,%2,#2\n" FIXUP, \
- " .long 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_2(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_3(to, from, ret) \
- __asm_copy_from_user_2x_cont(to, from, ret, \
- " GETB D1Ar1,[%1++]\n" \
- "4: SETB [%0++],D1Ar1\n", \
- "5: ADD %2,%2,#1\n", \
- " .long 4b,5b\n")
-
-#define __asm_copy_from_user_4x_cont(to, from, ret, COPY, FIXUP, TENTRY) \
- __asm_copy_user_cont(to, from, ret, \
- " GETD D1Ar1,[%1++]\n" \
- "2: SETD [%0++],D1Ar1\n" COPY, \
- "3: ADD %2,%2,#4\n" FIXUP, \
- " .long 2b,3b\n" TENTRY)
-
-#define __asm_copy_from_user_4(to, from, ret) \
- __asm_copy_from_user_4x_cont(to, from, ret, "", "", "")
-
-#define __asm_copy_from_user_8x64(to, from, ret) \
- asm volatile ( \
- " GETL D0Ar2,D1Ar1,[%1++]\n" \
- "2: SETL [%0++],D0Ar2,D1Ar1\n" \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: ADD %2,%2,#8\n" \
- " MOVT D0Ar2,#HI(1b)\n" \
- " JUMP D0Ar2,#LO(1b)\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .long 2b,3b\n" \
- " .previous\n" \
- : "=a" (to), "=r" (from), "=r" (ret) \
- : "0" (to), "1" (from), "2" (ret) \
- : "D1Ar1", "D0Ar2", "memory")
-
-/* rewind 'from' pointer when a fault occurs
- *
- * Rationale:
- * A fault occurs while reading from user buffer, which is the
- * source.
- * Since we don't write to kernel buffer until we read first,
- * the kernel buffer is at the right state and needn't be
- * corrected, but the source must be rewound to the beginning of
- * the block, which is LSM_STEP*8 bytes.
- * LSM_STEP is bits 10:8 in TXSTATUS which is already read
- * and stored in D0Ar2
- *
- * NOTE: If a fault occurs at the last operation in M{G,S}ETL
- * LSM_STEP will be 0. ie: we do 4 writes in our case, if
- * a fault happens at the 4th write, LSM_STEP will be 0
- * instead of 4. The code copes with that.
- */
-#define __asm_copy_from_user_64bit_rapf_loop(to, from, ret, n, id) \
- __asm_copy_user_64bit_rapf_loop(to, from, ret, n, id, \
- "LSR D0Ar2, D0Ar2, #5\n" \
- "ANDS D0Ar2, D0Ar2, #0x38\n" \
- "ADDZ D0Ar2, D0Ar2, #32\n" \
- "SUB %1, %1, D0Ar2\n")
-
-/* rewind 'from' pointer when a fault occurs
- *
- * Rationale:
- * A fault occurs while reading from user buffer, which is the
- * source.
- * Since we don't write to kernel buffer until we read first,
- * the kernel buffer is at the right state and needn't be
- * corrected, but the source must be rewound to the beginning of
- * the block, which is LSM_STEP*4 bytes.
- * LSM_STEP is bits 10:8 in TXSTATUS which is already read
- * and stored in D0Ar2
- *
- * NOTE: If a fault occurs at the last operation in M{G,S}ETL
- * LSM_STEP will be 0. ie: we do 4 writes in our case, if
- * a fault happens at the 4th write, LSM_STEP will be 0
- * instead of 4. The code copes with that.
- */
-#define __asm_copy_from_user_32bit_rapf_loop(to, from, ret, n, id) \
- __asm_copy_user_32bit_rapf_loop(to, from, ret, n, id, \
- "LSR D0Ar2, D0Ar2, #6\n" \
- "ANDS D0Ar2, D0Ar2, #0x1c\n" \
- "ADDZ D0Ar2, D0Ar2, #16\n" \
- "SUB %1, %1, D0Ar2\n")
-
-
-/*
- * Copy from user to kernel. The return-value is the number of bytes that were
- * inaccessible.
- */
-unsigned long raw_copy_from_user(void *pdst, const void __user *psrc,
- unsigned long n)
-{
- register char *dst asm ("A0.2") = pdst;
- register const char __user *src asm ("A1.2") = psrc;
- unsigned long retn = 0;
-
- if (n == 0)
- return 0;
-
- if ((unsigned long) src & 1) {
- __asm_copy_from_user_1(dst, src, retn);
- n--;
- if (retn)
- return retn + n;
- }
- if ((unsigned long) dst & 1) {
- /* Worst case - byte copy */
- while (n > 0) {
- __asm_copy_from_user_1(dst, src, retn);
- n--;
- if (retn)
- return retn + n;
- }
- }
- if (((unsigned long) src & 2) && n >= 2) {
- __asm_copy_from_user_2(dst, src, retn);
- n -= 2;
- if (retn)
- return retn + n;
- }
- if ((unsigned long) dst & 2) {
- /* Second worst case - word copy */
- while (n >= 2) {
- __asm_copy_from_user_2(dst, src, retn);
- n -= 2;
- if (retn)
- return retn + n;
- }
- }
-
-#ifdef USE_RAPF
- /* 64 bit copy loop */
- if (!(((unsigned long) src | (unsigned long) dst) & 7)) {
- if (n >= RAPF_MIN_BUF_SIZE) {
- /* Copy using fast 64bit rapf */
- __asm_copy_from_user_64bit_rapf_loop(dst, src, retn,
- n, "64cuz");
- }
- while (n >= 8) {
- __asm_copy_from_user_8x64(dst, src, retn);
- n -= 8;
- if (retn)
- return retn + n;
- }
- }
-
- if (n >= RAPF_MIN_BUF_SIZE) {
- /* Copy using fast 32bit rapf */
- __asm_copy_from_user_32bit_rapf_loop(dst, src, retn,
- n, "32cuz");
- }
-#else
- /* 64 bit copy loop */
- if (!(((unsigned long) src | (unsigned long) dst) & 7)) {
- while (n >= 8) {
- __asm_copy_from_user_8x64(dst, src, retn);
- n -= 8;
- if (retn)
- return retn + n;
- }
- }
-#endif
-
- while (n >= 4) {
- __asm_copy_from_user_4(dst, src, retn);
- n -= 4;
-
- if (retn)
- return retn + n;
- }
-
- /* If we get here, there were no memory read faults. */
- switch (n) {
- /* These copies are at least "naturally aligned" (so we don't
- have to check each byte), due to the src alignment code.
- The *_3 case *will* get the correct count for retn. */
- case 0:
- /* This case deliberately left in (if you have doubts check the
- generated assembly code). */
- break;
- case 1:
- __asm_copy_from_user_1(dst, src, retn);
- break;
- case 2:
- __asm_copy_from_user_2(dst, src, retn);
- break;
- case 3:
- __asm_copy_from_user_3(dst, src, retn);
- break;
- }
-
- /* If we get here, retn correctly reflects the number of failing
- bytes. */
- return retn;
-}
-EXPORT_SYMBOL(raw_copy_from_user);
-
-#define __asm_clear_8x64(to, ret) \
- asm volatile ( \
- " MOV D0Ar2,#0\n" \
- " MOV D1Ar1,#0\n" \
- " SETL [%0],D0Ar2,D1Ar1\n" \
- "2: SETL [%0++],D0Ar2,D1Ar1\n" \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: ADD %1,%1,#8\n" \
- " MOVT D0Ar2,#HI(1b)\n" \
- " JUMP D0Ar2,#LO(1b)\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .long 2b,3b\n" \
- " .previous\n" \
- : "=r" (to), "=r" (ret) \
- : "0" (to), "1" (ret) \
- : "D1Ar1", "D0Ar2", "memory")
-
-/* Zero userspace. */
-
-#define __asm_clear(to, ret, CLEAR, FIXUP, TENTRY) \
- asm volatile ( \
- " MOV D1Ar1,#0\n" \
- CLEAR \
- "1:\n" \
- " .section .fixup,\"ax\"\n" \
- FIXUP \
- " MOVT D1Ar1,#HI(1b)\n" \
- " JUMP D1Ar1,#LO(1b)\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- TENTRY \
- " .previous" \
- : "=r" (to), "=r" (ret) \
- : "0" (to), "1" (ret) \
- : "D1Ar1", "memory")
-
-#define __asm_clear_1(to, ret) \
- __asm_clear(to, ret, \
- " SETB [%0],D1Ar1\n" \
- "2: SETB [%0++],D1Ar1\n", \
- "3: ADD %1,%1,#1\n", \
- " .long 2b,3b\n")
-
-#define __asm_clear_2(to, ret) \
- __asm_clear(to, ret, \
- " SETW [%0],D1Ar1\n" \
- "2: SETW [%0++],D1Ar1\n", \
- "3: ADD %1,%1,#2\n", \
- " .long 2b,3b\n")
-
-#define __asm_clear_3(to, ret) \
- __asm_clear(to, ret, \
- "2: SETW [%0++],D1Ar1\n" \
- " SETB [%0],D1Ar1\n" \
- "3: SETB [%0++],D1Ar1\n", \
- "4: ADD %1,%1,#2\n" \
- "5: ADD %1,%1,#1\n", \
- " .long 2b,4b\n" \
- " .long 3b,5b\n")
-
-#define __asm_clear_4x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear(to, ret, \
- " SETD [%0],D1Ar1\n" \
- "2: SETD [%0++],D1Ar1\n" CLEAR, \
- "3: ADD %1,%1,#4\n" FIXUP, \
- " .long 2b,3b\n" TENTRY)
-
-#define __asm_clear_4(to, ret) \
- __asm_clear_4x_cont(to, ret, "", "", "")
-
-#define __asm_clear_8x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_4x_cont(to, ret, \
- " SETD [%0],D1Ar1\n" \
- "4: SETD [%0++],D1Ar1\n" CLEAR, \
- "5: ADD %1,%1,#4\n" FIXUP, \
- " .long 4b,5b\n" TENTRY)
-
-#define __asm_clear_8(to, ret) \
- __asm_clear_8x_cont(to, ret, "", "", "")
-
-#define __asm_clear_12x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_8x_cont(to, ret, \
- " SETD [%0],D1Ar1\n" \
- "6: SETD [%0++],D1Ar1\n" CLEAR, \
- "7: ADD %1,%1,#4\n" FIXUP, \
- " .long 6b,7b\n" TENTRY)
-
-#define __asm_clear_12(to, ret) \
- __asm_clear_12x_cont(to, ret, "", "", "")
-
-#define __asm_clear_16x_cont(to, ret, CLEAR, FIXUP, TENTRY) \
- __asm_clear_12x_cont(to, ret, \
- " SETD [%0],D1Ar1\n" \
- "8: SETD [%0++],D1Ar1\n" CLEAR, \
- "9: ADD %1,%1,#4\n" FIXUP, \
- " .long 8b,9b\n" TENTRY)
-
-#define __asm_clear_16(to, ret) \
- __asm_clear_16x_cont(to, ret, "", "", "")
-
-unsigned long __do_clear_user(void __user *pto, unsigned long pn)
-{
- register char __user *dst asm ("D0Re0") = pto;
- register unsigned long n asm ("D1Re0") = pn;
- register unsigned long retn asm ("D0Ar6") = 0;
-
- if ((unsigned long) dst & 1) {
- __asm_clear_1(dst, retn);
- n--;
- }
-
- if ((unsigned long) dst & 2) {
- __asm_clear_2(dst, retn);
- n -= 2;
- }
-
- /* 64 bit copy loop */
- if (!((__force unsigned long) dst & 7)) {
- while (n >= 8) {
- __asm_clear_8x64(dst, retn);
- n -= 8;
- }
- }
-
- while (n >= 16) {
- __asm_clear_16(dst, retn);
- n -= 16;
- }
-
- while (n >= 4) {
- __asm_clear_4(dst, retn);
- n -= 4;
- }
-
- switch (n) {
- case 0:
- break;
- case 1:
- __asm_clear_1(dst, retn);
- break;
- case 2:
- __asm_clear_2(dst, retn);
- break;
- case 3:
- __asm_clear_3(dst, retn);
- break;
- }
-
- return retn;
-}
-EXPORT_SYMBOL(__do_clear_user);
-
-unsigned char __get_user_asm_b(const void __user *addr, long *err)
-{
- register unsigned char x asm ("D0Re0") = 0;
- asm volatile (
- " GETB %0,[%2]\n"
- "1:\n"
- " GETB %0,[%2]\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
- "3: MOV D0FrT,%3\n"
- " SETD [%1],D0FrT\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- " .previous\n"
- : "=r" (x)
- : "r" (err), "r" (addr), "P" (-EFAULT)
- : "D0FrT");
- return x;
-}
-EXPORT_SYMBOL(__get_user_asm_b);
-
-unsigned short __get_user_asm_w(const void __user *addr, long *err)
-{
- register unsigned short x asm ("D0Re0") = 0;
- asm volatile (
- " GETW %0,[%2]\n"
- "1:\n"
- " GETW %0,[%2]\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
- "3: MOV D0FrT,%3\n"
- " SETD [%1],D0FrT\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- " .previous\n"
- : "=r" (x)
- : "r" (err), "r" (addr), "P" (-EFAULT)
- : "D0FrT");
- return x;
-}
-EXPORT_SYMBOL(__get_user_asm_w);
-
-unsigned int __get_user_asm_d(const void __user *addr, long *err)
-{
- register unsigned int x asm ("D0Re0") = 0;
- asm volatile (
- " GETD %0,[%2]\n"
- "1:\n"
- " GETD %0,[%2]\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
- "3: MOV D0FrT,%3\n"
- " SETD [%1],D0FrT\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- " .previous\n"
- : "=r" (x)
- : "r" (err), "r" (addr), "P" (-EFAULT)
- : "D0FrT");
- return x;
-}
-EXPORT_SYMBOL(__get_user_asm_d);
-
-unsigned long long __get_user_asm_l(const void __user *addr, long *err)
-{
- register unsigned long long x asm ("D0Re0") = 0;
- asm volatile (
- " GETL %0,%t0,[%2]\n"
- "1:\n"
- " GETL %0,%t0,[%2]\n"
- "2:\n"
- " .section .fixup,\"ax\"\n"
- "3: MOV D0FrT,%3\n"
- " SETD [%1],D0FrT\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- " .previous\n"
- : "=r" (x)
- : "r" (err), "r" (addr), "P" (-EFAULT)
- : "D0FrT");
- return x;
-}
-EXPORT_SYMBOL(__get_user_asm_l);
-
-long __put_user_asm_b(unsigned int x, void __user *addr)
-{
- register unsigned int err asm ("D0Re0") = 0;
- asm volatile (
- " MOV %0,#0\n"
- " SETB [%2],%1\n"
- "1:\n"
- " SETB [%2],%1\n"
- "2:\n"
- ".section .fixup,\"ax\"\n"
- "3: MOV %0,%3\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- ".previous"
- : "=r"(err)
- : "d" (x), "a" (addr), "P"(-EFAULT)
- : "D0FrT");
- return err;
-}
-EXPORT_SYMBOL(__put_user_asm_b);
-
-long __put_user_asm_w(unsigned int x, void __user *addr)
-{
- register unsigned int err asm ("D0Re0") = 0;
- asm volatile (
- " MOV %0,#0\n"
- " SETW [%2],%1\n"
- "1:\n"
- " SETW [%2],%1\n"
- "2:\n"
- ".section .fixup,\"ax\"\n"
- "3: MOV %0,%3\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- ".previous"
- : "=r"(err)
- : "d" (x), "a" (addr), "P"(-EFAULT)
- : "D0FrT");
- return err;
-}
-EXPORT_SYMBOL(__put_user_asm_w);
-
-long __put_user_asm_d(unsigned int x, void __user *addr)
-{
- register unsigned int err asm ("D0Re0") = 0;
- asm volatile (
- " MOV %0,#0\n"
- " SETD [%2],%1\n"
- "1:\n"
- " SETD [%2],%1\n"
- "2:\n"
- ".section .fixup,\"ax\"\n"
- "3: MOV %0,%3\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- ".previous"
- : "=r"(err)
- : "d" (x), "a" (addr), "P"(-EFAULT)
- : "D0FrT");
- return err;
-}
-EXPORT_SYMBOL(__put_user_asm_d);
-
-long __put_user_asm_l(unsigned long long x, void __user *addr)
-{
- register unsigned int err asm ("D0Re0") = 0;
- asm volatile (
- " MOV %0,#0\n"
- " SETL [%2],%1,%t1\n"
- "1:\n"
- " SETL [%2],%1,%t1\n"
- "2:\n"
- ".section .fixup,\"ax\"\n"
- "3: MOV %0,%3\n"
- " MOVT D0FrT,#HI(2b)\n"
- " JUMP D0FrT,#LO(2b)\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .long 1b,3b\n"
- ".previous"
- : "=r"(err)
- : "d" (x), "a" (addr), "P"(-EFAULT)
- : "D0FrT");
- return err;
-}
-EXPORT_SYMBOL(__put_user_asm_l);
-
-long strnlen_user(const char __user *src, long count)
-{
- long res;
-
- if (!access_ok(VERIFY_READ, src, 0))
- return 0;
-
- asm volatile (" MOV D0Ar4, %1\n"
- " MOV D0Ar6, %2\n"
- "0:\n"
- " SUBS D0FrT, D0Ar6, #0\n"
- " SUB D0Ar6, D0Ar6, #1\n"
- " BLE 2f\n"
- " GETB D0FrT, [D0Ar4+#1++]\n"
- "1:\n"
- " TST D0FrT, #255\n"
- " BNE 0b\n"
- "2:\n"
- " SUB %0, %2, D0Ar6\n"
- "3:\n"
- " .section .fixup,\"ax\"\n"
- "4:\n"
- " MOV %0, #0\n"
- " MOVT D0FrT,#HI(3b)\n"
- " JUMP D0FrT,#LO(3b)\n"
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .long 1b,4b\n"
- " .previous\n"
- : "=r" (res)
- : "r" (src), "r" (count)
- : "D0FrT", "D0Ar4", "D0Ar6", "cc");
-
- return res;
-}
-EXPORT_SYMBOL(strnlen_user);
-
-long __strncpy_from_user(char *dst, const char __user *src, long count)
-{
- long res;
-
- if (count == 0)
- return 0;
-
- /*
- * Currently, in 2.4.0-test9, most ports use a simple byte-copy loop.
- * So do we.
- *
- * This code is deduced from:
- *
- * char tmp2;
- * long tmp1, tmp3;
- * tmp1 = count;
- * while ((*dst++ = (tmp2 = *src++)) != 0
- * && --tmp1)
- * ;
- *
- * res = count - tmp1;
- *
- * with tweaks.
- */
-
- asm volatile (" MOV %0,%3\n"
- "1:\n"
- " GETB D0FrT,[%2++]\n"
- "2:\n"
- " CMP D0FrT,#0\n"
- " SETB [%1++],D0FrT\n"
- " BEQ 3f\n"
- " SUBS %0,%0,#1\n"
- " BNZ 1b\n"
- "3:\n"
- " SUB %0,%3,%0\n"
- "4:\n"
- " .section .fixup,\"ax\"\n"
- "5:\n"
- " MOV %0,%7\n"
- " MOVT D0FrT,#HI(4b)\n"
- " JUMP D0FrT,#LO(4b)\n"
- " .previous\n"
- " .section __ex_table,\"a\"\n"
- " .long 2b,5b\n"
- " .previous"
- : "=r" (res), "=r" (dst), "=r" (src), "=r" (count)
- : "3" (count), "1" (dst), "2" (src), "P" (-EFAULT)
- : "D0FrT", "memory", "cc");
-
- return res;
-}
-EXPORT_SYMBOL(__strncpy_from_user);
diff --git a/arch/metag/mm/Kconfig b/arch/metag/mm/Kconfig
deleted file mode 100644
index 9d4b2c67dcc1..000000000000
--- a/arch/metag/mm/Kconfig
+++ /dev/null
@@ -1,147 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Memory management options"
-
-config PAGE_OFFSET
- hex "Kernel page offset address"
- default "0x40000000"
- help
- This option allows you to set the virtual address at which the
- kernel will be mapped to.
-endmenu
-
-config KERNEL_4M_PAGES
- bool "Map kernel with 4MB pages"
- depends on METAG_META21_MMU
- default y
- help
- Map the kernel with large pages to reduce TLB pressure.
-
-choice
- prompt "User page size"
- default PAGE_SIZE_4K
-
-config PAGE_SIZE_4K
- bool "4kB"
- help
- This is the default page size used by all Meta cores.
-
-config PAGE_SIZE_8K
- bool "8kB"
- depends on METAG_META21_MMU
- help
- This enables 8kB pages as supported by Meta 2.x and later MMUs.
-
-config PAGE_SIZE_16K
- bool "16kB"
- depends on METAG_META21_MMU
- help
- This enables 16kB pages as supported by Meta 2.x and later MMUs.
-
-endchoice
-
-config NUMA
- bool "Non Uniform Memory Access (NUMA) Support"
- select ARCH_WANT_NUMA_VARIABLE_LOCALITY
- help
- Some Meta systems have MMU-mappable on-chip memories with
- lower latencies than main memory. This enables support for
- these blocks by binding them to nodes and allowing
- memory policies to be used for prioritizing and controlling
- allocation behaviour.
-
-config FORCE_MAX_ZONEORDER
- int "Maximum zone order"
- range 10 32
- default "10"
- help
- The kernel memory allocator divides physically contiguous memory
- blocks into "zones", where each zone is a power of two number of
- pages. This option selects the largest power of two that the kernel
- keeps in the memory allocator. If you need to allocate very large
- blocks of physically contiguous memory, then you may need to
- increase this value.
-
- This config option is actually maximum order plus one. For example,
- a value of 11 means that the largest free memory block is 2^10 pages.
-
- The page size is not necessarily 4KB. Keep this in mind
- when choosing a value for this option.
-
-config METAG_L2C
- bool "Level 2 Cache Support"
- depends on METAG_META21
- help
- Press y here to enable support for the Meta Level 2 (L2) cache. This
- will enable the cache at start up if it hasn't already been enabled
- by the bootloader.
-
- If the bootloader enables the L2 you must press y here to ensure the
- kernel takes the appropriate actions to keep the cache coherent.
-
-config NODES_SHIFT
- int
- default "1"
- depends on NEED_MULTIPLE_NODES
-
-config ARCH_FLATMEM_ENABLE
- def_bool y
- depends on !NUMA
-
-config ARCH_SPARSEMEM_ENABLE
- def_bool y
- select SPARSEMEM_STATIC
-
-config ARCH_SPARSEMEM_DEFAULT
- def_bool y
-
-config ARCH_SELECT_MEMORY_MODEL
- def_bool y
-
-config SYS_SUPPORTS_HUGETLBFS
- def_bool y
- depends on METAG_META21_MMU
-
-choice
- prompt "HugeTLB page size"
- depends on METAG_META21_MMU && HUGETLB_PAGE
- default HUGETLB_PAGE_SIZE_1M
-
-config HUGETLB_PAGE_SIZE_8K
- bool "8kB"
- depends on PAGE_SIZE_4K
-
-config HUGETLB_PAGE_SIZE_16K
- bool "16kB"
- depends on PAGE_SIZE_4K || PAGE_SIZE_8K
-
-config HUGETLB_PAGE_SIZE_32K
- bool "32kB"
-
-config HUGETLB_PAGE_SIZE_64K
- bool "64kB"
-
-config HUGETLB_PAGE_SIZE_128K
- bool "128kB"
-
-config HUGETLB_PAGE_SIZE_256K
- bool "256kB"
-
-config HUGETLB_PAGE_SIZE_512K
- bool "512kB"
-
-config HUGETLB_PAGE_SIZE_1M
- bool "1MB"
-
-config HUGETLB_PAGE_SIZE_2M
- bool "2MB"
-
-config HUGETLB_PAGE_SIZE_4M
- bool "4MB"
-
-endchoice
-
-config METAG_COREMEM
- bool
- default y if SUSPEND
-
-source "mm/Kconfig"
diff --git a/arch/metag/mm/Makefile b/arch/metag/mm/Makefile
deleted file mode 100644
index 0c7c91ba9fb9..000000000000
--- a/arch/metag/mm/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the linux Meta-specific parts of the memory manager.
-#
-
-obj-y += cache.o
-obj-y += extable.o
-obj-y += fault.o
-obj-y += init.o
-obj-y += ioremap.o
-obj-y += maccess.o
-
-mmu-y := mmu-meta1.o
-mmu-$(CONFIG_METAG_META21_MMU) := mmu-meta2.o
-obj-y += $(mmu-y)
-
-obj-$(CONFIG_HIGHMEM) += highmem.o
-obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
-obj-$(CONFIG_METAG_L2C) += l2cache.o
-obj-$(CONFIG_NUMA) += numa.o
diff --git a/arch/metag/mm/cache.c b/arch/metag/mm/cache.c
deleted file mode 100644
index a62285284ab8..000000000000
--- a/arch/metag/mm/cache.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * arch/metag/mm/cache.c
- *
- * Copyright (C) 2001, 2002, 2005, 2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Cache control code
- */
-
-#include <linux/export.h>
-#include <linux/io.h>
-#include <asm/cacheflush.h>
-#include <asm/core_reg.h>
-#include <asm/global_lock.h>
-#include <asm/metag_isa.h>
-#include <asm/metag_mem.h>
-#include <asm/metag_regs.h>
-
-#define DEFAULT_CACHE_WAYS_LOG2 2
-
-/*
- * Size of a set in the caches. Initialised for default 16K stride, adjusted
- * according to values passed through TBI global heap segment via LDLK (on ATP)
- * or config registers (on HTP/MTP)
- */
-static int dcache_set_shift = METAG_TBI_CACHE_SIZE_BASE_LOG2
- - DEFAULT_CACHE_WAYS_LOG2;
-static int icache_set_shift = METAG_TBI_CACHE_SIZE_BASE_LOG2
- - DEFAULT_CACHE_WAYS_LOG2;
-/*
- * The number of sets in the caches. Initialised for HTP/ATP, adjusted
- * according to NOMMU setting in config registers
- */
-static unsigned char dcache_sets_log2 = DEFAULT_CACHE_WAYS_LOG2;
-static unsigned char icache_sets_log2 = DEFAULT_CACHE_WAYS_LOG2;
-
-#ifndef CONFIG_METAG_META12
-/**
- * metag_lnkget_probe() - Probe whether lnkget/lnkset go around the cache
- */
-static volatile u32 lnkget_testdata[16] __initdata __aligned(64);
-
-#define LNKGET_CONSTANT 0xdeadbeef
-
-static void __init metag_lnkget_probe(void)
-{
- int temp;
- long flags;
-
- /*
- * It's conceivable the user has configured a globally coherent cache
- * shared with non-Linux hardware threads, so use LOCK2 to prevent them
- * from executing and causing cache eviction during the test.
- */
- __global_lock2(flags);
-
- /* read a value to bring it into the cache */
- (void)lnkget_testdata[0];
- lnkget_testdata[0] = 0;
-
- /* lnkget/lnkset it to modify it */
- asm volatile(
- "1: LNKGETD %0, [%1]\n"
- " LNKSETD [%1], %2\n"
- " DEFR %0, TXSTAT\n"
- " ANDT %0, %0, #HI(0x3f000000)\n"
- " CMPT %0, #HI(0x02000000)\n"
- " BNZ 1b\n"
- : "=&d" (temp)
- : "da" (&lnkget_testdata[0]), "bd" (LNKGET_CONSTANT)
- : "cc");
-
- /* re-read it to see if the cached value changed */
- temp = lnkget_testdata[0];
-
- __global_unlock2(flags);
-
- /* flush the cache line to fix any incoherency */
- __builtin_dcache_flush((void *)&lnkget_testdata[0]);
-
-#if defined(CONFIG_METAG_LNKGET_AROUND_CACHE)
- /* if the cache is right, LNKGET_AROUND_CACHE is unnecessary */
- if (temp == LNKGET_CONSTANT)
- pr_info("LNKGET/SET go through cache but CONFIG_METAG_LNKGET_AROUND_CACHE=y\n");
-#elif defined(CONFIG_METAG_ATOMICITY_LNKGET)
- /*
- * if the cache is wrong, LNKGET_AROUND_CACHE is really necessary
- * because the kernel is configured to use LNKGET/SET for atomicity
- */
- WARN(temp != LNKGET_CONSTANT,
- "LNKGET/SET go around cache but CONFIG_METAG_LNKGET_AROUND_CACHE=n\n"
- "Expect kernel failure as it's used for atomicity primitives\n");
-#elif defined(CONFIG_SMP)
- /*
- * if the cache is wrong, LNKGET_AROUND_CACHE should be used or the
- * gateway page won't flush and userland could break.
- */
- WARN(temp != LNKGET_CONSTANT,
- "LNKGET/SET go around cache but CONFIG_METAG_LNKGET_AROUND_CACHE=n\n"
- "Expect userland failure as it's used for user gateway page\n");
-#else
- /*
- * if the cache is wrong, LNKGET_AROUND_CACHE is set wrong, but it
- * doesn't actually matter as it doesn't have any effect on !SMP &&
- * !ATOMICITY_LNKGET.
- */
- if (temp != LNKGET_CONSTANT)
- pr_warn("LNKGET/SET go around cache but CONFIG_METAG_LNKGET_AROUND_CACHE=n\n");
-#endif
-}
-#endif /* !CONFIG_METAG_META12 */
-
-/**
- * metag_cache_probe() - Probe L1 cache configuration.
- *
- * Probe the L1 cache configuration to aid the L1 physical cache flushing
- * functions.
- */
-void __init metag_cache_probe(void)
-{
-#ifndef CONFIG_METAG_META12
- int coreid = metag_in32(METAC_CORE_ID);
- int config = metag_in32(METAC_CORE_CONFIG2);
- int cfgcache = coreid & METAC_COREID_CFGCACHE_BITS;
-
- if (cfgcache == METAC_COREID_CFGCACHE_TYPE0 ||
- cfgcache == METAC_COREID_CFGCACHE_PRIVNOMMU) {
- icache_sets_log2 = 1;
- dcache_sets_log2 = 1;
- }
-
- /* For normal size caches, the smallest size is 4Kb.
- For small caches, the smallest size is 64b */
- icache_set_shift = (config & METAC_CORECFG2_ICSMALL_BIT)
- ? 6 : 12;
- icache_set_shift += (config & METAC_CORE_C2ICSZ_BITS)
- >> METAC_CORE_C2ICSZ_S;
- icache_set_shift -= icache_sets_log2;
-
- dcache_set_shift = (config & METAC_CORECFG2_DCSMALL_BIT)
- ? 6 : 12;
- dcache_set_shift += (config & METAC_CORECFG2_DCSZ_BITS)
- >> METAC_CORECFG2_DCSZ_S;
- dcache_set_shift -= dcache_sets_log2;
-
- metag_lnkget_probe();
-#else
- /* Extract cache sizes from global heap segment */
- unsigned long val, u;
- int width, shift, addend;
- PTBISEG seg;
-
- seg = __TBIFindSeg(NULL, TBID_SEG(TBID_THREAD_GLOBAL,
- TBID_SEGSCOPE_GLOBAL,
- TBID_SEGTYPE_HEAP));
- if (seg != NULL) {
- val = seg->Data[1];
-
- /* Work out width of I-cache size bit-field */
- u = ((unsigned long) METAG_TBI_ICACHE_SIZE_BITS)
- >> METAG_TBI_ICACHE_SIZE_S;
- width = 0;
- while (u & 1) {
- width++;
- u >>= 1;
- }
- /* Extract sign-extended size addend value */
- shift = 32 - (METAG_TBI_ICACHE_SIZE_S + width);
- addend = (long) ((val & METAG_TBI_ICACHE_SIZE_BITS)
- << shift)
- >> (shift + METAG_TBI_ICACHE_SIZE_S);
- /* Now calculate I-cache set size */
- icache_set_shift = (METAG_TBI_CACHE_SIZE_BASE_LOG2
- - DEFAULT_CACHE_WAYS_LOG2)
- + addend;
-
- /* Similarly for D-cache */
- u = ((unsigned long) METAG_TBI_DCACHE_SIZE_BITS)
- >> METAG_TBI_DCACHE_SIZE_S;
- width = 0;
- while (u & 1) {
- width++;
- u >>= 1;
- }
- shift = 32 - (METAG_TBI_DCACHE_SIZE_S + width);
- addend = (long) ((val & METAG_TBI_DCACHE_SIZE_BITS)
- << shift)
- >> (shift + METAG_TBI_DCACHE_SIZE_S);
- dcache_set_shift = (METAG_TBI_CACHE_SIZE_BASE_LOG2
- - DEFAULT_CACHE_WAYS_LOG2)
- + addend;
- }
-#endif
-}
-
-static void metag_phys_data_cache_flush(const void *start)
-{
- unsigned long flush0, flush1, flush2, flush3;
- int loops, step;
- int thread;
- int part, offset;
- int set_shift;
-
- /* Use a sequence of writes to flush the cache region requested */
- thread = (__core_reg_get(TXENABLE) & TXENABLE_THREAD_BITS)
- >> TXENABLE_THREAD_S;
-
- /* Cache is broken into sets which lie in contiguous RAMs */
- set_shift = dcache_set_shift;
-
- /* Move to the base of the physical cache flush region */
- flush0 = LINSYSCFLUSH_DCACHE_LINE;
- step = 64;
-
- /* Get partition data for this thread */
- part = metag_in32(SYSC_DCPART0 +
- (SYSC_xCPARTn_STRIDE * thread));
-
- if ((int)start < 0)
- /* Access Global vs Local partition */
- part >>= SYSC_xCPARTG_AND_S
- - SYSC_xCPARTL_AND_S;
-
- /* Extract offset and move SetOff */
- offset = (part & SYSC_xCPARTL_OR_BITS)
- >> SYSC_xCPARTL_OR_S;
- flush0 += (offset << (set_shift - 4));
-
- /* Shrink size */
- part = (part & SYSC_xCPARTL_AND_BITS)
- >> SYSC_xCPARTL_AND_S;
- loops = ((part + 1) << (set_shift - 4));
-
- /* Reduce loops by step of cache line size */
- loops /= step;
-
- flush1 = flush0 + (1 << set_shift);
- flush2 = flush0 + (2 << set_shift);
- flush3 = flush0 + (3 << set_shift);
-
- if (dcache_sets_log2 == 1) {
- flush2 = flush1;
- flush3 = flush1 + step;
- flush1 = flush0 + step;
- step <<= 1;
- loops >>= 1;
- }
-
- /* Clear loops ways in cache */
- while (loops-- != 0) {
- /* Clear the ways. */
-#if 0
- /*
- * GCC doesn't generate very good code for this so we
- * provide inline assembly instead.
- */
- metag_out8(0, flush0);
- metag_out8(0, flush1);
- metag_out8(0, flush2);
- metag_out8(0, flush3);
-
- flush0 += step;
- flush1 += step;
- flush2 += step;
- flush3 += step;
-#else
- asm volatile (
- "SETB\t[%0+%4++],%5\n"
- "SETB\t[%1+%4++],%5\n"
- "SETB\t[%2+%4++],%5\n"
- "SETB\t[%3+%4++],%5\n"
- : "+e" (flush0),
- "+e" (flush1),
- "+e" (flush2),
- "+e" (flush3)
- : "e" (step), "a" (0));
-#endif
- }
-}
-
-void metag_data_cache_flush_all(const void *start)
-{
- if ((metag_in32(SYSC_CACHE_MMU_CONFIG) & SYSC_CMMUCFG_DC_ON_BIT) == 0)
- /* No need to flush the data cache it's not actually enabled */
- return;
-
- metag_phys_data_cache_flush(start);
-}
-
-void metag_data_cache_flush(const void *start, int bytes)
-{
- unsigned long flush0;
- int loops, step;
-
- if ((metag_in32(SYSC_CACHE_MMU_CONFIG) & SYSC_CMMUCFG_DC_ON_BIT) == 0)
- /* No need to flush the data cache it's not actually enabled */
- return;
-
- if (bytes >= 4096) {
- metag_phys_data_cache_flush(start);
- return;
- }
-
- /* Use linear cache flush mechanism on META IP */
- flush0 = (int)start;
- loops = ((int)start & (DCACHE_LINE_BYTES - 1)) + bytes +
- (DCACHE_LINE_BYTES - 1);
- loops >>= DCACHE_LINE_S;
-
-#define PRIM_FLUSH(addr, offset) do { \
- int __addr = ((int) (addr)) + ((offset) * 64); \
- __builtin_dcache_flush((void *)(__addr)); \
- } while (0)
-
-#define LOOP_INC (4*64)
-
- do {
- /* By default stop */
- step = 0;
-
- switch (loops) {
- /* Drop Thru Cases! */
- default:
- PRIM_FLUSH(flush0, 3);
- loops -= 4;
- step = 1;
- case 3:
- PRIM_FLUSH(flush0, 2);
- case 2:
- PRIM_FLUSH(flush0, 1);
- case 1:
- PRIM_FLUSH(flush0, 0);
- flush0 += LOOP_INC;
- case 0:
- break;
- }
- } while (step);
-}
-EXPORT_SYMBOL(metag_data_cache_flush);
-
-static void metag_phys_code_cache_flush(const void *start, int bytes)
-{
- unsigned long flush0, flush1, flush2, flush3, end_set;
- int loops, step;
- int thread;
- int set_shift, set_size;
- int part, offset;
-
- /* Use a sequence of writes to flush the cache region requested */
- thread = (__core_reg_get(TXENABLE) & TXENABLE_THREAD_BITS)
- >> TXENABLE_THREAD_S;
- set_shift = icache_set_shift;
-
- /* Move to the base of the physical cache flush region */
- flush0 = LINSYSCFLUSH_ICACHE_LINE;
- step = 64;
-
- /* Get partition code for this thread */
- part = metag_in32(SYSC_ICPART0 +
- (SYSC_xCPARTn_STRIDE * thread));
-
- if ((int)start < 0)
- /* Access Global vs Local partition */
- part >>= SYSC_xCPARTG_AND_S-SYSC_xCPARTL_AND_S;
-
- /* Extract offset and move SetOff */
- offset = (part & SYSC_xCPARTL_OR_BITS)
- >> SYSC_xCPARTL_OR_S;
- flush0 += (offset << (set_shift - 4));
-
- /* Shrink size */
- part = (part & SYSC_xCPARTL_AND_BITS)
- >> SYSC_xCPARTL_AND_S;
- loops = ((part + 1) << (set_shift - 4));
-
- /* Where does the Set end? */
- end_set = flush0 + loops;
- set_size = loops;
-
-#ifdef CONFIG_METAG_META12
- if ((bytes < 4096) && (bytes < loops)) {
- /* Unreachable on HTP/MTP */
- /* Only target the sets that could be relavent */
- flush0 += (loops - step) & ((int) start);
- loops = (((int) start) & (step-1)) + bytes + step - 1;
- }
-#endif
-
- /* Reduce loops by step of cache line size */
- loops /= step;
-
- flush1 = flush0 + (1<<set_shift);
- flush2 = flush0 + (2<<set_shift);
- flush3 = flush0 + (3<<set_shift);
-
- if (icache_sets_log2 == 1) {
- flush2 = flush1;
- flush3 = flush1 + step;
- flush1 = flush0 + step;
-#if 0
- /* flush0 will stop one line early in this case
- * (flush1 will do the final line).
- * However we don't correct end_set here at the moment
- * because it will never wrap on HTP/MTP
- */
- end_set -= step;
-#endif
- step <<= 1;
- loops >>= 1;
- }
-
- /* Clear loops ways in cache */
- while (loops-- != 0) {
-#if 0
- /*
- * GCC doesn't generate very good code for this so we
- * provide inline assembly instead.
- */
- /* Clear the ways */
- metag_out8(0, flush0);
- metag_out8(0, flush1);
- metag_out8(0, flush2);
- metag_out8(0, flush3);
-
- flush0 += step;
- flush1 += step;
- flush2 += step;
- flush3 += step;
-#else
- asm volatile (
- "SETB\t[%0+%4++],%5\n"
- "SETB\t[%1+%4++],%5\n"
- "SETB\t[%2+%4++],%5\n"
- "SETB\t[%3+%4++],%5\n"
- : "+e" (flush0),
- "+e" (flush1),
- "+e" (flush2),
- "+e" (flush3)
- : "e" (step), "a" (0));
-#endif
-
- if (flush0 == end_set) {
- /* Wrap within Set 0 */
- flush0 -= set_size;
- flush1 -= set_size;
- flush2 -= set_size;
- flush3 -= set_size;
- }
- }
-}
-
-void metag_code_cache_flush_all(const void *start)
-{
- if ((metag_in32(SYSC_CACHE_MMU_CONFIG) & SYSC_CMMUCFG_IC_ON_BIT) == 0)
- /* No need to flush the code cache it's not actually enabled */
- return;
-
- metag_phys_code_cache_flush(start, 4096);
-}
-EXPORT_SYMBOL(metag_code_cache_flush_all);
-
-void metag_code_cache_flush(const void *start, int bytes)
-{
-#ifndef CONFIG_METAG_META12
- void *flush;
- int loops, step;
-#endif /* !CONFIG_METAG_META12 */
-
- if ((metag_in32(SYSC_CACHE_MMU_CONFIG) & SYSC_CMMUCFG_IC_ON_BIT) == 0)
- /* No need to flush the code cache it's not actually enabled */
- return;
-
-#ifdef CONFIG_METAG_META12
- /* CACHEWD isn't available on Meta1, so always do full cache flush */
- metag_phys_code_cache_flush(start, bytes);
-
-#else /* CONFIG_METAG_META12 */
- /* If large size do full physical cache flush */
- if (bytes >= 4096) {
- metag_phys_code_cache_flush(start, bytes);
- return;
- }
-
- /* Use linear cache flush mechanism on META IP */
- flush = (void *)((int)start & ~(ICACHE_LINE_BYTES-1));
- loops = ((int)start & (ICACHE_LINE_BYTES-1)) + bytes +
- (ICACHE_LINE_BYTES-1);
- loops >>= ICACHE_LINE_S;
-
-#define PRIM_IFLUSH(addr, offset) \
- __builtin_meta2_cachewd(((addr) + ((offset) * 64)), CACHEW_ICACHE_BIT)
-
-#define LOOP_INC (4*64)
-
- do {
- /* By default stop */
- step = 0;
-
- switch (loops) {
- /* Drop Thru Cases! */
- default:
- PRIM_IFLUSH(flush, 3);
- loops -= 4;
- step = 1;
- case 3:
- PRIM_IFLUSH(flush, 2);
- case 2:
- PRIM_IFLUSH(flush, 1);
- case 1:
- PRIM_IFLUSH(flush, 0);
- flush += LOOP_INC;
- case 0:
- break;
- }
- } while (step);
-#endif /* !CONFIG_METAG_META12 */
-}
-EXPORT_SYMBOL(metag_code_cache_flush);
diff --git a/arch/metag/mm/fault.c b/arch/metag/mm/fault.c
deleted file mode 100644
index de54fe686080..000000000000
--- a/arch/metag/mm/fault.c
+++ /dev/null
@@ -1,247 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Meta page fault handling.
- *
- * Copyright (C) 2005-2012 Imagination Technologies Ltd.
- */
-
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-#include <linux/sched/debug.h>
-#include <linux/interrupt.h>
-#include <linux/uaccess.h>
-
-#include <asm/tlbflush.h>
-#include <asm/mmu.h>
-#include <asm/traps.h>
-
-/* Clear any pending catch buffer state. */
-static void clear_cbuf_entry(struct pt_regs *regs, unsigned long addr,
- unsigned int trapno)
-{
- PTBICTXEXTCB0 cbuf = regs->extcb0;
-
- switch (trapno) {
- /* Instruction fetch faults leave no catch buffer state. */
- case TBIXXF_SIGNUM_IGF:
- case TBIXXF_SIGNUM_IPF:
- return;
- default:
- if (cbuf[0].CBAddr == addr) {
- cbuf[0].CBAddr = 0;
- cbuf[0].CBFlags &= ~TXCATCH0_FAULT_BITS;
-
- /* And, as this is the ONLY catch entry, we
- * need to clear the cbuf bit from the context!
- */
- regs->ctx.SaveMask &= ~(TBICTX_CBUF_BIT |
- TBICTX_XCBF_BIT);
-
- return;
- }
- pr_err("Failed to clear cbuf entry!\n");
- }
-}
-
-int show_unhandled_signals = 1;
-
-int do_page_fault(struct pt_regs *regs, unsigned long address,
- unsigned int write_access, unsigned int trapno)
-{
- struct task_struct *tsk;
- struct mm_struct *mm;
- struct vm_area_struct *vma, *prev_vma;
- siginfo_t info;
- int fault;
- unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
-
- tsk = current;
-
- if ((address >= VMALLOC_START) && (address < VMALLOC_END)) {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Do _not_ use "tsk" here. We might be inside
- * an interrupt in the middle of a task switch..
- */
- int offset = pgd_index(address);
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd = ((pgd_t *)mmu_get_base()) + offset;
- pgd_k = swapper_pg_dir + offset;
-
- /* This will never happen with the folded page table. */
- if (!pgd_present(*pgd)) {
- if (!pgd_present(*pgd_k))
- goto bad_area_nosemaphore;
- set_pgd(pgd, *pgd_k);
- return 0;
- }
-
- pud = pud_offset(pgd, address);
- pud_k = pud_offset(pgd_k, address);
- if (!pud_present(*pud_k))
- goto bad_area_nosemaphore;
- set_pud(pud, *pud_k);
-
- pmd = pmd_offset(pud, address);
- pmd_k = pmd_offset(pud_k, address);
- if (!pmd_present(*pmd_k))
- goto bad_area_nosemaphore;
- set_pmd(pmd, *pmd_k);
-
- pte_k = pte_offset_kernel(pmd_k, address);
- if (!pte_present(*pte_k))
- goto bad_area_nosemaphore;
-
- /* May only be needed on Chorus2 */
- flush_tlb_all();
- return 0;
- }
-
- mm = tsk->mm;
-
- if (faulthandler_disabled() || !mm)
- goto no_context;
-
- if (user_mode(regs))
- flags |= FAULT_FLAG_USER;
-retry:
- down_read(&mm->mmap_sem);
-
- vma = find_vma_prev(mm, address, &prev_vma);
-
- if (!vma || address < vma->vm_start)
- goto check_expansion;
-
-good_area:
- if (write_access) {
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- } else {
- if (!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE)))
- goto bad_area;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
- fault = handle_mm_fault(vma, address, flags);
-
- if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
- return 0;
-
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
- if (flags & FAULT_FLAG_ALLOW_RETRY) {
- if (fault & VM_FAULT_MAJOR)
- tsk->maj_flt++;
- else
- tsk->min_flt++;
- if (fault & VM_FAULT_RETRY) {
- flags &= ~FAULT_FLAG_ALLOW_RETRY;
- flags |= FAULT_FLAG_TRIED;
-
- /*
- * No need to up_read(&mm->mmap_sem) as we would
- * have already released it in __lock_page_or_retry
- * in mm/filemap.c.
- */
-
- goto retry;
- }
- }
-
- up_read(&mm->mmap_sem);
- return 0;
-
-check_expansion:
- vma = prev_vma;
- if (vma && (expand_stack(vma, address) == 0))
- goto good_area;
-
-bad_area:
- up_read(&mm->mmap_sem);
-
-bad_area_nosemaphore:
- if (user_mode(regs)) {
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- info.si_code = SEGV_MAPERR;
- info.si_addr = (__force void __user *)address;
- info.si_trapno = trapno;
-
- if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
- printk_ratelimit()) {
- printk("%s%s[%d]: segfault at %lx pc %08x sp %08x write %d trap %#x (%s)",
- task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
- tsk->comm, task_pid_nr(tsk), address,
- regs->ctx.CurrPC, regs->ctx.AX[0].U0,
- write_access, trapno, trap_name(trapno));
- print_vma_addr(" in ", regs->ctx.CurrPC);
- print_vma_addr(" rtp in ", regs->ctx.DX[4].U1);
- printk("\n");
- show_regs(regs);
- }
- force_sig_info(SIGSEGV, &info, tsk);
- return 1;
- }
- goto no_context;
-
-do_sigbus:
- up_read(&mm->mmap_sem);
-
- /*
- * Send a sigbus, regardless of whether we were in kernel
- * or user mode.
- */
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (__force void __user *)address;
- info.si_trapno = trapno;
- force_sig_info(SIGBUS, &info, tsk);
-
- /* Kernel mode? Handle exceptions or die */
- if (!user_mode(regs))
- goto no_context;
-
- return 1;
-
- /*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-out_of_memory:
- up_read(&mm->mmap_sem);
- if (user_mode(regs)) {
- pagefault_out_of_memory();
- return 1;
- }
-
-no_context:
- /* Are we prepared to handle this kernel fault? */
- if (fixup_exception(regs)) {
- clear_cbuf_entry(regs, address, trapno);
- return 1;
- }
-
- die("Oops", regs, (write_access << 15) | trapno, address);
- do_exit(SIGKILL);
-}
diff --git a/arch/metag/mm/highmem.c b/arch/metag/mm/highmem.c
deleted file mode 100644
index 83527fc7c8a7..000000000000
--- a/arch/metag/mm/highmem.c
+++ /dev/null
@@ -1,122 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/export.h>
-#include <linux/highmem.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <asm/fixmap.h>
-#include <asm/tlbflush.h>
-
-static pte_t *kmap_pte;
-
-unsigned long highstart_pfn, highend_pfn;
-
-void *kmap(struct page *page)
-{
- might_sleep();
- if (!PageHighMem(page))
- return page_address(page);
- return kmap_high(page);
-}
-EXPORT_SYMBOL(kmap);
-
-void kunmap(struct page *page)
-{
- BUG_ON(in_interrupt());
- if (!PageHighMem(page))
- return;
- kunmap_high(page);
-}
-EXPORT_SYMBOL(kunmap);
-
-/*
- * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because
- * no global lock is needed and because the kmap code must perform a global TLB
- * invalidation when the kmap pool wraps.
- *
- * However when holding an atomic kmap is is not legal to sleep, so atomic
- * kmaps are appropriate for short, tight code paths only.
- */
-
-void *kmap_atomic(struct page *page)
-{
- enum fixed_addresses idx;
- unsigned long vaddr;
- int type;
-
- preempt_disable();
- pagefault_disable();
- if (!PageHighMem(page))
- return page_address(page);
-
- type = kmap_atomic_idx_push();
- idx = type + KM_TYPE_NR * smp_processor_id();
- vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-#ifdef CONFIG_DEBUG_HIGHMEM
- BUG_ON(!pte_none(*(kmap_pte - idx)));
-#endif
- set_pte(kmap_pte - idx, mk_pte(page, PAGE_KERNEL));
-
- return (void *)vaddr;
-}
-EXPORT_SYMBOL(kmap_atomic);
-
-void __kunmap_atomic(void *kvaddr)
-{
- unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
- int idx, type;
-
- if (kvaddr >= (void *)FIXADDR_START) {
- type = kmap_atomic_idx();
- idx = type + KM_TYPE_NR * smp_processor_id();
-
- /*
- * Force other mappings to Oops if they'll try to access this
- * pte without first remap it. Keeping stale mappings around
- * is a bad idea also, in case the page changes cacheability
- * attributes or becomes a protected page in a hypervisor.
- */
- pte_clear(&init_mm, vaddr, kmap_pte-idx);
- flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
-
- kmap_atomic_idx_pop();
- }
-
- pagefault_enable();
- preempt_enable();
-}
-EXPORT_SYMBOL(__kunmap_atomic);
-
-/*
- * This is the same as kmap_atomic() but can map memory that doesn't
- * have a struct page associated with it.
- */
-void *kmap_atomic_pfn(unsigned long pfn)
-{
- enum fixed_addresses idx;
- unsigned long vaddr;
- int type;
-
- preempt_disable();
- pagefault_disable();
-
- type = kmap_atomic_idx_push();
- idx = type + KM_TYPE_NR * smp_processor_id();
- vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-#ifdef CONFIG_DEBUG_HIGHMEM
- BUG_ON(!pte_none(*(kmap_pte - idx)));
-#endif
- set_pte(kmap_pte - idx, pfn_pte(pfn, PAGE_KERNEL));
- flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
-
- return (void *)vaddr;
-}
-
-void __init kmap_init(void)
-{
- unsigned long kmap_vstart;
-
- /* cache the first kmap pte */
- kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN);
- kmap_pte = kmap_get_fixmap_pte(kmap_vstart);
-}
diff --git a/arch/metag/mm/hugetlbpage.c b/arch/metag/mm/hugetlbpage.c
deleted file mode 100644
index 012ee4c80dc7..000000000000
--- a/arch/metag/mm/hugetlbpage.c
+++ /dev/null
@@ -1,251 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * arch/metag/mm/hugetlbpage.c
- *
- * METAG HugeTLB page support.
- *
- * Cloned from SuperH
- *
- * Cloned from sparc64 by Paul Mundt.
- *
- * Copyright (C) 2002, 2003 David S. Miller (davem@redhat.com)
- */
-
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/hugetlb.h>
-#include <linux/pagemap.h>
-#include <linux/sysctl.h>
-
-#include <asm/mman.h>
-#include <asm/pgalloc.h>
-#include <asm/tlb.h>
-#include <asm/tlbflush.h>
-#include <asm/cacheflush.h>
-
-/*
- * If the arch doesn't supply something else, assume that hugepage
- * size aligned regions are ok without further preparation.
- */
-int prepare_hugepage_range(struct file *file, unsigned long addr,
- unsigned long len)
-{
- struct mm_struct *mm = current->mm;
- struct hstate *h = hstate_file(file);
- struct vm_area_struct *vma;
-
- if (len & ~huge_page_mask(h))
- return -EINVAL;
- if (addr & ~huge_page_mask(h))
- return -EINVAL;
- if (TASK_SIZE - len < addr)
- return -EINVAL;
-
- vma = find_vma(mm, ALIGN_HUGEPT(addr));
- if (vma && !(vma->vm_flags & MAP_HUGETLB))
- return -EINVAL;
-
- vma = find_vma(mm, addr);
- if (vma) {
- if (addr + len > vma->vm_start)
- return -EINVAL;
- if (!(vma->vm_flags & MAP_HUGETLB) &&
- (ALIGN_HUGEPT(addr + len) > vma->vm_start))
- return -EINVAL;
- }
- return 0;
-}
-
-pte_t *huge_pte_alloc(struct mm_struct *mm,
- unsigned long addr, unsigned long sz)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
-
- pgd = pgd_offset(mm, addr);
- pud = pud_offset(pgd, addr);
- pmd = pmd_offset(pud, addr);
- pte = pte_alloc_map(mm, pmd, addr);
- pgd->pgd &= ~_PAGE_SZ_MASK;
- pgd->pgd |= _PAGE_SZHUGE;
-
- return pte;
-}
-
-pte_t *huge_pte_offset(struct mm_struct *mm,
- unsigned long addr, unsigned long sz)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte = NULL;
-
- pgd = pgd_offset(mm, addr);
- pud = pud_offset(pgd, addr);
- pmd = pmd_offset(pud, addr);
- pte = pte_offset_kernel(pmd, addr);
-
- return pte;
-}
-
-int pmd_huge(pmd_t pmd)
-{
- return pmd_page_shift(pmd) > PAGE_SHIFT;
-}
-
-int pud_huge(pud_t pud)
-{
- return 0;
-}
-
-struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address,
- pmd_t *pmd, int write)
-{
- return NULL;
-}
-
-#ifdef HAVE_ARCH_HUGETLB_UNMAPPED_AREA
-
-/*
- * Look for an unmapped area starting after another hugetlb vma.
- * There are guaranteed to be no huge pte's spare if all the huge pages are
- * full size (4MB), so in that case compile out this search.
- */
-#if HPAGE_SHIFT == HUGEPT_SHIFT
-static inline unsigned long
-hugetlb_get_unmapped_area_existing(unsigned long len)
-{
- return 0;
-}
-#else
-static unsigned long
-hugetlb_get_unmapped_area_existing(unsigned long len)
-{
- struct mm_struct *mm = current->mm;
- struct vm_area_struct *vma;
- unsigned long start_addr, addr;
- int after_huge;
-
- if (mm->context.part_huge) {
- start_addr = mm->context.part_huge;
- after_huge = 1;
- } else {
- start_addr = TASK_UNMAPPED_BASE;
- after_huge = 0;
- }
-new_search:
- addr = start_addr;
-
- for (vma = find_vma(mm, addr); ; vma = vma->vm_next) {
- if ((!vma && !after_huge) || TASK_SIZE - len < addr) {
- /*
- * Start a new search - just in case we missed
- * some holes.
- */
- if (start_addr != TASK_UNMAPPED_BASE) {
- start_addr = TASK_UNMAPPED_BASE;
- goto new_search;
- }
- return 0;
- }
- /* skip ahead if we've aligned right over some vmas */
- if (vma && vma->vm_end <= addr)
- continue;
- /* space before the next vma? */
- if (after_huge && (!vma || ALIGN_HUGEPT(addr + len)
- <= vma->vm_start)) {
- unsigned long end = addr + len;
- if (end & HUGEPT_MASK)
- mm->context.part_huge = end;
- else if (addr == mm->context.part_huge)
- mm->context.part_huge = 0;
- return addr;
- }
- if (vma->vm_flags & MAP_HUGETLB) {
- /* space after a huge vma in 2nd level page table? */
- if (vma->vm_end & HUGEPT_MASK) {
- after_huge = 1;
- /* no need to align to the next PT block */
- addr = vma->vm_end;
- continue;
- }
- }
- after_huge = 0;
- addr = ALIGN_HUGEPT(vma->vm_end);
- }
-}
-#endif
-
-/* Do a full search to find an area without any nearby normal pages. */
-static unsigned long
-hugetlb_get_unmapped_area_new_pmd(unsigned long len)
-{
- struct vm_unmapped_area_info info;
-
- info.flags = 0;
- info.length = len;
- info.low_limit = TASK_UNMAPPED_BASE;
- info.high_limit = TASK_SIZE;
- info.align_mask = PAGE_MASK & HUGEPT_MASK;
- info.align_offset = 0;
- return vm_unmapped_area(&info);
-}
-
-unsigned long
-hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
- unsigned long len, unsigned long pgoff, unsigned long flags)
-{
- struct hstate *h = hstate_file(file);
-
- if (len & ~huge_page_mask(h))
- return -EINVAL;
- if (len > TASK_SIZE)
- return -ENOMEM;
-
- if (flags & MAP_FIXED) {
- if (prepare_hugepage_range(file, addr, len))
- return -EINVAL;
- return addr;
- }
-
- if (addr) {
- addr = ALIGN(addr, huge_page_size(h));
- if (!prepare_hugepage_range(file, addr, len))
- return addr;
- }
-
- /*
- * Look for an existing hugetlb vma with space after it (this is to to
- * minimise fragmentation caused by huge pages.
- */
- addr = hugetlb_get_unmapped_area_existing(len);
- if (addr)
- return addr;
-
- /*
- * Find an unmapped naturally aligned set of 4MB blocks that we can use
- * for huge pages.
- */
- return hugetlb_get_unmapped_area_new_pmd(len);
-}
-
-#endif /*HAVE_ARCH_HUGETLB_UNMAPPED_AREA*/
-
-/* necessary for boot time 4MB huge page allocation */
-static __init int setup_hugepagesz(char *opt)
-{
- unsigned long ps = memparse(opt, &opt);
- if (ps == (1 << HPAGE_SHIFT)) {
- hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
- } else {
- hugetlb_bad_size();
- pr_err("hugepagesz: Unsupported page size %lu M\n",
- ps >> 20);
- return 0;
- }
- return 1;
-}
-__setup("hugepagesz=", setup_hugepagesz);
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
deleted file mode 100644
index 0e2ca9058998..000000000000
--- a/arch/metag/mm/init.c
+++ /dev/null
@@ -1,408 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2005,2006,2007,2008,2009,2010 Imagination Technologies
- *
- */
-
-#include <linux/export.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/pagemap.h>
-#include <linux/percpu.h>
-#include <linux/memblock.h>
-#include <linux/initrd.h>
-#include <linux/sched/task.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/mmu.h>
-#include <asm/mmu_context.h>
-#include <asm/sections.h>
-#include <asm/tlb.h>
-#include <asm/user_gateway.h>
-#include <asm/mmzone.h>
-#include <asm/fixmap.h>
-
-unsigned long pfn_base;
-EXPORT_SYMBOL(pfn_base);
-
-pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_data;
-
-unsigned long empty_zero_page;
-EXPORT_SYMBOL(empty_zero_page);
-
-extern char __user_gateway_start;
-extern char __user_gateway_end;
-
-void *gateway_page;
-
-/*
- * Insert the gateway page into a set of page tables, creating the
- * page tables if necessary.
- */
-static void insert_gateway_page(pgd_t *pgd, unsigned long address)
-{
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
-
- BUG_ON(!pgd_present(*pgd));
-
- pud = pud_offset(pgd, address);
- BUG_ON(!pud_present(*pud));
-
- pmd = pmd_offset(pud, address);
- if (!pmd_present(*pmd)) {
- pte = alloc_bootmem_pages(PAGE_SIZE);
- set_pmd(pmd, __pmd(_PAGE_TABLE | __pa(pte)));
- }
-
- pte = pte_offset_kernel(pmd, address);
- set_pte(pte, pfn_pte(__pa(gateway_page) >> PAGE_SHIFT, PAGE_READONLY));
-}
-
-/* Alloc and map a page in a known location accessible to userspace. */
-static void __init user_gateway_init(void)
-{
- unsigned long address = USER_GATEWAY_PAGE;
- int offset = pgd_index(address);
- pgd_t *pgd;
-
- gateway_page = alloc_bootmem_pages(PAGE_SIZE);
-
- pgd = swapper_pg_dir + offset;
- insert_gateway_page(pgd, address);
-
-#ifdef CONFIG_METAG_META12
- /*
- * Insert the gateway page into our current page tables even
- * though we've already inserted it into our reference page
- * table (swapper_pg_dir). This is because with a META1 mmu we
- * copy just the user address range and not the gateway page
- * entry on context switch, see switch_mmu().
- */
- pgd = (pgd_t *)mmu_get_base() + offset;
- insert_gateway_page(pgd, address);
-#endif /* CONFIG_METAG_META12 */
-
- BUG_ON((&__user_gateway_end - &__user_gateway_start) > PAGE_SIZE);
-
- gateway_page += (address & ~PAGE_MASK);
-
- memcpy(gateway_page, &__user_gateway_start,
- &__user_gateway_end - &__user_gateway_start);
-
- /*
- * We don't need to flush the TLB here, there should be no mapping
- * present at boot for this address and only valid mappings are in
- * the TLB (apart from on Meta 1.x, but those cached invalid
- * mappings should be impossible to hit here).
- *
- * We don't flush the code cache here even though we have written
- * code through the data cache and they may not be coherent. At
- * this point we assume there is no stale data in the code cache
- * for this address so there is no need to flush.
- */
-}
-
-static void __init allocate_pgdat(unsigned int nid)
-{
- unsigned long start_pfn, end_pfn;
-#ifdef CONFIG_NEED_MULTIPLE_NODES
- unsigned long phys;
-#endif
-
- get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
-
-#ifdef CONFIG_NEED_MULTIPLE_NODES
- phys = __memblock_alloc_base(sizeof(struct pglist_data),
- SMP_CACHE_BYTES, end_pfn << PAGE_SHIFT);
- /* Retry with all of system memory */
- if (!phys)
- phys = __memblock_alloc_base(sizeof(struct pglist_data),
- SMP_CACHE_BYTES,
- memblock_end_of_DRAM());
- if (!phys)
- panic("Can't allocate pgdat for node %d\n", nid);
-
- NODE_DATA(nid) = __va(phys);
- memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
-
- NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
-#endif
-
- NODE_DATA(nid)->node_start_pfn = start_pfn;
- NODE_DATA(nid)->node_spanned_pages = end_pfn - start_pfn;
-}
-
-static void __init bootmem_init_one_node(unsigned int nid)
-{
- unsigned long total_pages, paddr;
- unsigned long end_pfn;
- struct pglist_data *p;
-
- p = NODE_DATA(nid);
-
- /* Nothing to do.. */
- if (!p->node_spanned_pages)
- return;
-
- end_pfn = pgdat_end_pfn(p);
-#ifdef CONFIG_HIGHMEM
- if (end_pfn > max_low_pfn)
- end_pfn = max_low_pfn;
-#endif
-
- total_pages = bootmem_bootmap_pages(end_pfn - p->node_start_pfn);
-
- paddr = memblock_alloc(total_pages << PAGE_SHIFT, PAGE_SIZE);
- if (!paddr)
- panic("Can't allocate bootmap for nid[%d]\n", nid);
-
- init_bootmem_node(p, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
-
- free_bootmem_with_active_regions(nid, end_pfn);
-
- /*
- * XXX Handle initial reservations for the system memory node
- * only for the moment, we'll refactor this later for handling
- * reservations in other nodes.
- */
- if (nid == 0) {
- struct memblock_region *reg;
-
- /* Reserve the sections we're already using. */
- for_each_memblock(reserved, reg) {
- unsigned long size = reg->size;
-
-#ifdef CONFIG_HIGHMEM
- /* ...but not highmem */
- if (PFN_DOWN(reg->base) >= highstart_pfn)
- continue;
-
- if (PFN_UP(reg->base + size) > highstart_pfn)
- size = (highstart_pfn - PFN_DOWN(reg->base))
- << PAGE_SHIFT;
-#endif
-
- reserve_bootmem(reg->base, size, BOOTMEM_DEFAULT);
- }
- }
-
- sparse_memory_present_with_active_regions(nid);
-}
-
-static void __init do_init_bootmem(void)
-{
- struct memblock_region *reg;
- int i;
-
- /* Add active regions with valid PFNs. */
- for_each_memblock(memory, reg) {
- unsigned long start_pfn, end_pfn;
- start_pfn = memblock_region_memory_base_pfn(reg);
- end_pfn = memblock_region_memory_end_pfn(reg);
- memblock_set_node(PFN_PHYS(start_pfn),
- PFN_PHYS(end_pfn - start_pfn),
- &memblock.memory, 0);
- }
-
- /* All of system RAM sits in node 0 for the non-NUMA case */
- allocate_pgdat(0);
- node_set_online(0);
-
- soc_mem_setup();
-
- for_each_online_node(i)
- bootmem_init_one_node(i);
-
- sparse_init();
-}
-
-extern char _heap_start[];
-
-static void __init init_and_reserve_mem(void)
-{
- unsigned long start_pfn, heap_start;
- u64 base = min_low_pfn << PAGE_SHIFT;
- u64 size = (max_low_pfn << PAGE_SHIFT) - base;
-
- heap_start = (unsigned long) &_heap_start;
-
- memblock_add(base, size);
-
- /*
- * Partially used pages are not usable - thus
- * we are rounding upwards:
- */
- start_pfn = PFN_UP(__pa(heap_start));
-
- /*
- * Reserve the kernel text.
- */
- memblock_reserve(base, (PFN_PHYS(start_pfn) + PAGE_SIZE - 1) - base);
-
-#ifdef CONFIG_HIGHMEM
- /*
- * Add & reserve highmem, so page structures are initialised.
- */
- base = highstart_pfn << PAGE_SHIFT;
- size = (highend_pfn << PAGE_SHIFT) - base;
- if (size) {
- memblock_add(base, size);
- memblock_reserve(base, size);
- }
-#endif
-}
-
-#ifdef CONFIG_HIGHMEM
-/*
- * Ensure we have allocated page tables in swapper_pg_dir for the
- * fixed mappings range from 'start' to 'end'.
- */
-static void __init allocate_pgtables(unsigned long start, unsigned long end)
-{
- pgd_t *pgd;
- pmd_t *pmd;
- pte_t *pte;
- int i, j;
- unsigned long vaddr;
-
- vaddr = start;
- i = pgd_index(vaddr);
- j = pmd_index(vaddr);
- pgd = swapper_pg_dir + i;
-
- for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
- pmd = (pmd_t *)pgd;
- for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) {
- vaddr += PMD_SIZE;
-
- if (!pmd_none(*pmd))
- continue;
-
- pte = (pte_t *)alloc_bootmem_low_pages(PAGE_SIZE);
- pmd_populate_kernel(&init_mm, pmd, pte);
- }
- j = 0;
- }
-}
-
-static void __init fixedrange_init(void)
-{
- unsigned long vaddr, end;
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
-
- /*
- * Fixed mappings:
- */
- vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
- end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
- allocate_pgtables(vaddr, end);
-
- /*
- * Permanent kmaps:
- */
- vaddr = PKMAP_BASE;
- allocate_pgtables(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP);
-
- pgd = swapper_pg_dir + pgd_index(vaddr);
- pud = pud_offset(pgd, vaddr);
- pmd = pmd_offset(pud, vaddr);
- pte = pte_offset_kernel(pmd, vaddr);
- pkmap_page_table = pte;
-}
-#endif /* CONFIG_HIGHMEM */
-
-/*
- * paging_init() continues the virtual memory environment setup which
- * was begun by the code in arch/metag/kernel/setup.c.
- */
-void __init paging_init(unsigned long mem_end)
-{
- unsigned long max_zone_pfns[MAX_NR_ZONES];
- int nid;
-
- init_and_reserve_mem();
-
- memblock_allow_resize();
-
- memblock_dump_all();
-
- nodes_clear(node_online_map);
-
- init_new_context(&init_task, &init_mm);
-
- memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
-
- do_init_bootmem();
- mmu_init(mem_end);
-
-#ifdef CONFIG_HIGHMEM
- fixedrange_init();
- kmap_init();
-#endif
-
- /* Initialize the zero page to a bootmem page, already zeroed. */
- empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
-
- user_gateway_init();
-
- memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
-
- for_each_online_node(nid) {
- pg_data_t *pgdat = NODE_DATA(nid);
- unsigned long low, start_pfn;
-
- start_pfn = pgdat->bdata->node_min_pfn;
- low = pgdat->bdata->node_low_pfn;
-
- if (max_zone_pfns[ZONE_NORMAL] < low)
- max_zone_pfns[ZONE_NORMAL] = low;
-
-#ifdef CONFIG_HIGHMEM
- max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
-#endif
- pr_info("Node %u: start_pfn = 0x%lx, low = 0x%lx\n",
- nid, start_pfn, low);
- }
-
- free_area_init_nodes(max_zone_pfns);
-}
-
-void __init mem_init(void)
-{
-#ifdef CONFIG_HIGHMEM
- unsigned long tmp;
-
- /*
- * Explicitly reset zone->managed_pages because highmem pages are
- * freed before calling free_all_bootmem();
- */
- reset_all_zones_managed_pages();
- for (tmp = highstart_pfn; tmp < highend_pfn; tmp++)
- free_highmem_page(pfn_to_page(tmp));
-#endif /* CONFIG_HIGHMEM */
-
- free_all_bootmem();
- mem_init_print_info(NULL);
-}
-
-void free_initmem(void)
-{
- free_initmem_default(POISON_FREE_INITMEM);
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
- "initrd");
-}
-#endif
diff --git a/arch/metag/mm/ioremap.c b/arch/metag/mm/ioremap.c
deleted file mode 100644
index df2b59cb02eb..000000000000
--- a/arch/metag/mm/ioremap.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Re-map IO memory to kernel address space so that we can access it.
- * Needed for memory-mapped I/O devices mapped outside our normal DRAM
- * window (that is, all memory-mapped I/O devices).
- *
- * Copyright (C) 1995,1996 Linus Torvalds
- *
- * Meta port based on CRIS-port by Axis Communications AB
- */
-
-#include <linux/vmalloc.h>
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
-
-#include <asm/pgtable.h>
-
-/*
- * Remap an arbitrary physical address space into the kernel virtual
- * address space. Needed when the kernel wants to access high addresses
- * directly.
- *
- * NOTE! We need to allow non-page-aligned mappings too: we will obviously
- * have to convert them into an offset in a page-aligned mapping, but the
- * caller shouldn't need to know that small detail.
- */
-void __iomem *__ioremap(unsigned long phys_addr, size_t size,
- unsigned long flags)
-{
- unsigned long addr;
- struct vm_struct *area;
- unsigned long offset, last_addr;
- pgprot_t prot;
-
- /* Don't allow wraparound or zero size */
- last_addr = phys_addr + size - 1;
- if (!size || last_addr < phys_addr)
- return NULL;
-
- /* Custom region addresses are accessible and uncached by default. */
- if (phys_addr >= LINSYSCUSTOM_BASE &&
- phys_addr < (LINSYSCUSTOM_BASE + LINSYSCUSTOM_LIMIT))
- return (__force void __iomem *) phys_addr;
-
- /*
- * Mappings have to be page-aligned
- */
- offset = phys_addr & ~PAGE_MASK;
- phys_addr &= PAGE_MASK;
- size = PAGE_ALIGN(last_addr+1) - phys_addr;
- prot = __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_DIRTY |
- _PAGE_ACCESSED | _PAGE_KERNEL | _PAGE_CACHE_WIN0 |
- flags);
-
- /*
- * Ok, go for it..
- */
- area = get_vm_area(size, VM_IOREMAP);
- if (!area)
- return NULL;
- area->phys_addr = phys_addr;
- addr = (unsigned long) area->addr;
- if (ioremap_page_range(addr, addr + size, phys_addr, prot)) {
- vunmap((void *) addr);
- return NULL;
- }
- return (__force void __iomem *) (offset + (char *)addr);
-}
-EXPORT_SYMBOL(__ioremap);
-
-void __iounmap(void __iomem *addr)
-{
- struct vm_struct *p;
-
- if ((__force unsigned long)addr >= LINSYSCUSTOM_BASE &&
- (__force unsigned long)addr < (LINSYSCUSTOM_BASE +
- LINSYSCUSTOM_LIMIT))
- return;
-
- p = remove_vm_area((void *)(PAGE_MASK & (unsigned long __force)addr));
- if (unlikely(!p)) {
- pr_err("iounmap: bad address %p\n", addr);
- return;
- }
-
- kfree(p);
-}
-EXPORT_SYMBOL(__iounmap);
diff --git a/arch/metag/mm/l2cache.c b/arch/metag/mm/l2cache.c
deleted file mode 100644
index addffc58989c..000000000000
--- a/arch/metag/mm/l2cache.c
+++ /dev/null
@@ -1,193 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-
-#include <asm/l2cache.h>
-#include <asm/metag_isa.h>
-
-/* If non-0, then initialise the L2 cache */
-static int l2cache_init = 1;
-/* If non-0, then initialise the L2 cache prefetch */
-static int l2cache_init_pf = 1;
-
-int l2c_pfenable;
-
-static volatile u32 l2c_testdata[16] __initdata __aligned(64);
-
-static int __init parse_l2cache(char *p)
-{
- char *cp = p;
-
- if (get_option(&cp, &l2cache_init) != 1) {
- pr_err("Bad l2cache parameter (%s)\n", p);
- return 1;
- }
- return 0;
-}
-early_param("l2cache", parse_l2cache);
-
-static int __init parse_l2cache_pf(char *p)
-{
- char *cp = p;
-
- if (get_option(&cp, &l2cache_init_pf) != 1) {
- pr_err("Bad l2cache_pf parameter (%s)\n", p);
- return 1;
- }
- return 0;
-}
-early_param("l2cache_pf", parse_l2cache_pf);
-
-static int __init meta_l2c_setup(void)
-{
- /*
- * If the L2 cache isn't even present, don't do anything, but say so in
- * the log.
- */
- if (!meta_l2c_is_present()) {
- pr_info("L2 Cache: Not present\n");
- return 0;
- }
-
- /*
- * Check whether the line size is recognised.
- */
- if (!meta_l2c_linesize()) {
- pr_warn_once("L2 Cache: unknown line size id (config=0x%08x)\n",
- meta_l2c_config());
- }
-
- /*
- * Initialise state.
- */
- l2c_pfenable = _meta_l2c_pf_is_enabled();
-
- /*
- * Enable the L2 cache and print to log whether it was already enabled
- * by the bootloader.
- */
- if (l2cache_init) {
- pr_info("L2 Cache: Enabling... ");
- if (meta_l2c_enable())
- pr_cont("already enabled\n");
- else
- pr_cont("done\n");
- } else {
- pr_info("L2 Cache: Not enabling\n");
- }
-
- /*
- * Enable L2 cache prefetch.
- */
- if (l2cache_init_pf) {
- pr_info("L2 Cache: Enabling prefetch... ");
- if (meta_l2c_pf_enable(1))
- pr_cont("already enabled\n");
- else
- pr_cont("done\n");
- } else {
- pr_info("L2 Cache: Not enabling prefetch\n");
- }
-
- return 0;
-}
-core_initcall(meta_l2c_setup);
-
-int meta_l2c_disable(void)
-{
- unsigned long flags;
- int en;
-
- if (!meta_l2c_is_present())
- return 1;
-
- /*
- * Prevent other threads writing during the writeback, otherwise the
- * writes will get "lost" when the L2 is disabled.
- */
- __global_lock2(flags);
- en = meta_l2c_is_enabled();
- if (likely(en)) {
- _meta_l2c_pf_enable(0);
- wr_fence();
- _meta_l2c_purge();
- _meta_l2c_enable(0);
- }
- __global_unlock2(flags);
-
- return !en;
-}
-
-int meta_l2c_enable(void)
-{
- unsigned long flags;
- int en;
-
- if (!meta_l2c_is_present())
- return 0;
-
- /*
- * Init (clearing the L2) can happen while the L2 is disabled, so other
- * threads are safe to continue executing, however we must not init the
- * cache if it's already enabled (dirty lines would be discarded), so
- * this operation should still be atomic with other threads.
- */
- __global_lock1(flags);
- en = meta_l2c_is_enabled();
- if (likely(!en)) {
- _meta_l2c_init();
- _meta_l2c_enable(1);
- _meta_l2c_pf_enable(l2c_pfenable);
- }
- __global_unlock1(flags);
-
- return en;
-}
-
-int meta_l2c_pf_enable(int pfenable)
-{
- unsigned long flags;
- int en = l2c_pfenable;
-
- if (!meta_l2c_is_present())
- return 0;
-
- /*
- * We read modify write the enable register, so this operation must be
- * atomic with other threads.
- */
- __global_lock1(flags);
- en = l2c_pfenable;
- l2c_pfenable = pfenable;
- if (meta_l2c_is_enabled())
- _meta_l2c_pf_enable(pfenable);
- __global_unlock1(flags);
-
- return en;
-}
-
-int meta_l2c_flush(void)
-{
- unsigned long flags;
- int en;
-
- /*
- * Prevent other threads writing during the writeback. This also
- * involves read modify writes.
- */
- __global_lock2(flags);
- en = meta_l2c_is_enabled();
- if (likely(en)) {
- _meta_l2c_pf_enable(0);
- wr_fence();
- _meta_l2c_purge();
- _meta_l2c_enable(0);
- _meta_l2c_init();
- _meta_l2c_enable(1);
- _meta_l2c_pf_enable(l2c_pfenable);
- }
- __global_unlock2(flags);
-
- return !en;
-}
diff --git a/arch/metag/mm/maccess.c b/arch/metag/mm/maccess.c
deleted file mode 100644
index c22755165df9..000000000000
--- a/arch/metag/mm/maccess.c
+++ /dev/null
@@ -1,69 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * safe read and write memory routines callable while atomic
- *
- * Copyright 2012 Imagination Technologies
- */
-
-#include <linux/uaccess.h>
-#include <asm/io.h>
-
-/*
- * The generic probe_kernel_write() uses the user copy code which can split the
- * writes if the source is unaligned, and repeats writes to make exceptions
- * precise. We override it here to avoid these things happening to memory mapped
- * IO memory where they could have undesired effects.
- * Due to the use of CACHERD instruction this only works on Meta2 onwards.
- */
-#ifdef CONFIG_METAG_META21
-long probe_kernel_write(void *dst, const void *src, size_t size)
-{
- unsigned long ldst = (unsigned long)dst;
- void __iomem *iodst = (void __iomem *)dst;
- unsigned long lsrc = (unsigned long)src;
- const u8 *psrc = (u8 *)src;
- unsigned int pte, i;
- u8 bounce[8] __aligned(8);
-
- if (!size)
- return 0;
-
- /* Use the write combine bit to decide is the destination is MMIO. */
- pte = __builtin_meta2_cacherd(dst);
-
- /* Check the mapping is valid and writeable. */
- if ((pte & (MMCU_ENTRY_WR_BIT | MMCU_ENTRY_VAL_BIT))
- != (MMCU_ENTRY_WR_BIT | MMCU_ENTRY_VAL_BIT))
- return -EFAULT;
-
- /* Fall back to generic version for cases we're not interested in. */
- if (pte & MMCU_ENTRY_WRC_BIT || /* write combined memory */
- (ldst & (size - 1)) || /* destination unaligned */
- size > 8 || /* more than max write size */
- (size & (size - 1))) /* non power of 2 size */
- return __probe_kernel_write(dst, src, size);
-
- /* If src is unaligned, copy to the aligned bounce buffer first. */
- if (lsrc & (size - 1)) {
- for (i = 0; i < size; ++i)
- bounce[i] = psrc[i];
- psrc = bounce;
- }
-
- switch (size) {
- case 1:
- writeb(*psrc, iodst);
- break;
- case 2:
- writew(*(const u16 *)psrc, iodst);
- break;
- case 4:
- writel(*(const u32 *)psrc, iodst);
- break;
- case 8:
- writeq(*(const u64 *)psrc, iodst);
- break;
- }
- return 0;
-}
-#endif
diff --git a/arch/metag/mm/mmu-meta1.c b/arch/metag/mm/mmu-meta1.c
deleted file mode 100644
index 53190b13dc54..000000000000
--- a/arch/metag/mm/mmu-meta1.c
+++ /dev/null
@@ -1,157 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2005,2006,2007,2008,2009 Imagination Technologies
- *
- * Meta 1 MMU handling code.
- *
- */
-
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-
-#include <asm/mmu.h>
-
-#define DM3_BASE (LINSYSDIRECT_BASE + (MMCU_DIRECTMAPn_ADDR_SCALE * 3))
-
-/*
- * This contains the physical address of the top level 2k pgd table.
- */
-static unsigned long mmu_base_phys;
-
-/*
- * Given a physical address, return a mapped virtual address that can be used
- * to access that location.
- * In practice, we use the DirectMap region to make this happen.
- */
-static unsigned long map_addr(unsigned long phys)
-{
- static unsigned long dm_base = 0xFFFFFFFF;
- int offset;
-
- offset = phys - dm_base;
-
- /* Are we in the current map range ? */
- if ((offset < 0) || (offset >= MMCU_DIRECTMAPn_ADDR_SCALE)) {
- /* Calculate new DM area */
- dm_base = phys & ~(MMCU_DIRECTMAPn_ADDR_SCALE - 1);
-
- /* Actually map it in! */
- metag_out32(dm_base, MMCU_DIRECTMAP3_ADDR);
-
- /* And calculate how far into that area our reference is */
- offset = phys - dm_base;
- }
-
- return DM3_BASE + offset;
-}
-
-/*
- * Return the physical address of the base of our pgd table.
- */
-static inline unsigned long __get_mmu_base(void)
-{
- unsigned long base_phys;
- unsigned int stride;
-
- if (is_global_space(PAGE_OFFSET))
- stride = 4;
- else
- stride = hard_processor_id(); /* [0..3] */
-
- base_phys = metag_in32(MMCU_TABLE_PHYS_ADDR);
- base_phys += (0x800 * stride);
-
- return base_phys;
-}
-
-/* Given a virtual address, return the virtual address of the relevant pgd */
-static unsigned long pgd_entry_addr(unsigned long virt)
-{
- unsigned long pgd_phys;
- unsigned long pgd_virt;
-
- if (!mmu_base_phys)
- mmu_base_phys = __get_mmu_base();
-
- /*
- * Are we trying to map a global address. If so, then index
- * the global pgd table instead of our local one.
- */
- if (is_global_space(virt)) {
- /* Scale into 2gig map */
- virt &= ~0x80000000;
- }
-
- /* Base of the pgd table plus our 4Meg entry, 4bytes each */
- pgd_phys = mmu_base_phys + ((virt >> PGDIR_SHIFT) * 4);
-
- pgd_virt = map_addr(pgd_phys);
-
- return pgd_virt;
-}
-
-/* Given a virtual address, return the virtual address of the relevant pte */
-static unsigned long pgtable_entry_addr(unsigned long virt)
-{
- unsigned long pgtable_phys;
- unsigned long pgtable_virt, pte_virt;
-
- /* Find the physical address of the 4MB page table*/
- pgtable_phys = metag_in32(pgd_entry_addr(virt)) & MMCU_ENTRY_ADDR_BITS;
-
- /* Map it to a virtual address */
- pgtable_virt = map_addr(pgtable_phys);
-
- /* And index into it for our pte */
- pte_virt = pgtable_virt + ((virt >> PAGE_SHIFT) & 0x3FF) * 4;
-
- return pte_virt;
-}
-
-unsigned long mmu_read_first_level_page(unsigned long vaddr)
-{
- return metag_in32(pgd_entry_addr(vaddr));
-}
-
-unsigned long mmu_read_second_level_page(unsigned long vaddr)
-{
- return metag_in32(pgtable_entry_addr(vaddr));
-}
-
-unsigned long mmu_get_base(void)
-{
- static unsigned long __base;
-
- /* Find the base of our MMU pgd table */
- if (!__base)
- __base = pgd_entry_addr(0);
-
- return __base;
-}
-
-void __init mmu_init(unsigned long mem_end)
-{
- unsigned long entry, addr;
- pgd_t *p_swapper_pg_dir;
-
- /*
- * Now copy over any MMU pgd entries already in the mmu page tables
- * over to our root init process (swapper_pg_dir) map. This map is
- * then inherited by all other processes, which means all processes
- * inherit a map of the kernel space.
- */
- addr = PAGE_OFFSET;
- entry = pgd_index(PAGE_OFFSET);
- p_swapper_pg_dir = pgd_offset_k(0) + entry;
-
- while (addr <= META_MEMORY_LIMIT) {
- unsigned long pgd_entry;
- /* copy over the current MMU value */
- pgd_entry = mmu_read_first_level_page(addr);
- pgd_val(*p_swapper_pg_dir) = pgd_entry;
-
- p_swapper_pg_dir++;
- addr += PGDIR_SIZE;
- }
-}
diff --git a/arch/metag/mm/mmu-meta2.c b/arch/metag/mm/mmu-meta2.c
deleted file mode 100644
index 8b668a69c980..000000000000
--- a/arch/metag/mm/mmu-meta2.c
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2008,2009,2010,2011 Imagination Technologies Ltd.
- *
- * Meta 2 enhanced mode MMU handling code.
- *
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/bootmem.h>
-#include <linux/syscore_ops.h>
-
-#include <asm/mmu.h>
-#include <asm/mmu_context.h>
-
-unsigned long mmu_read_first_level_page(unsigned long vaddr)
-{
- unsigned int cpu = hard_processor_id();
- unsigned long offset, linear_base, linear_limit;
- unsigned int phys0;
- pgd_t *pgd, entry;
-
- if (is_global_space(vaddr))
- vaddr &= ~0x80000000;
-
- offset = vaddr >> PGDIR_SHIFT;
-
- phys0 = metag_in32(mmu_phys0_addr(cpu));
-
- /* Top bit of linear base is always zero. */
- linear_base = (phys0 >> PGDIR_SHIFT) & 0x1ff;
-
- /* Limit in the range 0 (4MB) to 9 (2GB). */
- linear_limit = 1 << ((phys0 >> 8) & 0xf);
- linear_limit += linear_base;
-
- /*
- * If offset is below linear base or above the limit then no
- * mapping exists.
- */
- if (offset < linear_base || offset > linear_limit)
- return 0;
-
- offset -= linear_base;
- pgd = (pgd_t *)mmu_get_base();
- entry = pgd[offset];
-
- return pgd_val(entry);
-}
-
-unsigned long mmu_read_second_level_page(unsigned long vaddr)
-{
- return __builtin_meta2_cacherd((void *)(vaddr & PAGE_MASK));
-}
-
-unsigned long mmu_get_base(void)
-{
- unsigned int cpu = hard_processor_id();
- unsigned long stride;
-
- stride = cpu * LINSYSMEMTnX_STRIDE;
-
- /*
- * Bits 18:2 of the MMCU_TnLocal_TABLE_PHYS1 register should be
- * used as an offset to the start of the top-level pgd table.
- */
- stride += (metag_in32(mmu_phys1_addr(cpu)) & 0x7fffc);
-
- if (is_global_space(PAGE_OFFSET))
- stride += LINSYSMEMTXG_OFFSET;
-
- return LINSYSMEMT0L_BASE + stride;
-}
-
-#define FIRST_LEVEL_MASK 0xffffffc0
-#define SECOND_LEVEL_MASK 0xfffff000
-#define SECOND_LEVEL_ALIGN 64
-
-static void repriv_mmu_tables(void)
-{
- unsigned long phys0_addr;
- unsigned int g;
-
- /*
- * Check that all the mmu table regions are priv protected, and if not
- * fix them and emit a warning. If we left them without priv protection
- * then userland processes would have access to a 2M window into
- * physical memory near where the page tables are.
- */
- phys0_addr = MMCU_T0LOCAL_TABLE_PHYS0;
- for (g = 0; g < 2; ++g) {
- unsigned int t, phys0;
- unsigned long flags;
- for (t = 0; t < 4; ++t) {
- __global_lock2(flags);
- phys0 = metag_in32(phys0_addr);
- if ((phys0 & _PAGE_PRESENT) && !(phys0 & _PAGE_PRIV)) {
- pr_warn("Fixing priv protection on T%d %s MMU table region\n",
- t,
- g ? "global" : "local");
- phys0 |= _PAGE_PRIV;
- metag_out32(phys0, phys0_addr);
- }
- __global_unlock2(flags);
-
- phys0_addr += MMCU_TnX_TABLE_PHYSX_STRIDE;
- }
-
- phys0_addr += MMCU_TXG_TABLE_PHYSX_OFFSET
- - 4*MMCU_TnX_TABLE_PHYSX_STRIDE;
- }
-}
-
-#ifdef CONFIG_METAG_SUSPEND_MEM
-static void mmu_resume(void)
-{
- /*
- * If a full suspend to RAM has happened then the original bad MMU table
- * priv may have been restored, so repriv them again.
- */
- repriv_mmu_tables();
-}
-#else
-#define mmu_resume NULL
-#endif /* CONFIG_METAG_SUSPEND_MEM */
-
-static struct syscore_ops mmu_syscore_ops = {
- .resume = mmu_resume,
-};
-
-void __init mmu_init(unsigned long mem_end)
-{
- unsigned long entry, addr;
- pgd_t *p_swapper_pg_dir;
-#ifdef CONFIG_KERNEL_4M_PAGES
- unsigned long mem_size = mem_end - PAGE_OFFSET;
- unsigned int pages = DIV_ROUND_UP(mem_size, 1 << 22);
- unsigned int second_level_entry = 0;
- unsigned long *second_level_table;
-#endif
-
- /*
- * Now copy over any MMU pgd entries already in the mmu page tables
- * over to our root init process (swapper_pg_dir) map. This map is
- * then inherited by all other processes, which means all processes
- * inherit a map of the kernel space.
- */
- addr = META_MEMORY_BASE;
- entry = pgd_index(META_MEMORY_BASE);
- p_swapper_pg_dir = pgd_offset_k(0) + entry;
-
- while (entry < (PTRS_PER_PGD - pgd_index(META_MEMORY_BASE))) {
- unsigned long pgd_entry;
- /* copy over the current MMU value */
- pgd_entry = mmu_read_first_level_page(addr);
- pgd_val(*p_swapper_pg_dir) = pgd_entry;
-
- p_swapper_pg_dir++;
- addr += PGDIR_SIZE;
- entry++;
- }
-
-#ifdef CONFIG_KERNEL_4M_PAGES
- /*
- * At this point we can also map the kernel with 4MB pages to
- * reduce TLB pressure.
- */
- second_level_table = alloc_bootmem_pages(SECOND_LEVEL_ALIGN * pages);
-
- addr = PAGE_OFFSET;
- entry = pgd_index(PAGE_OFFSET);
- p_swapper_pg_dir = pgd_offset_k(0) + entry;
-
- while (pages > 0) {
- unsigned long phys_addr, second_level_phys;
- pte_t *pte = (pte_t *)&second_level_table[second_level_entry];
-
- phys_addr = __pa(addr);
-
- second_level_phys = __pa(pte);
-
- pgd_val(*p_swapper_pg_dir) = ((second_level_phys &
- FIRST_LEVEL_MASK) |
- _PAGE_SZ_4M |
- _PAGE_PRESENT);
-
- pte_val(*pte) = ((phys_addr & SECOND_LEVEL_MASK) |
- _PAGE_PRESENT | _PAGE_DIRTY |
- _PAGE_ACCESSED | _PAGE_WRITE |
- _PAGE_CACHEABLE | _PAGE_KERNEL);
-
- p_swapper_pg_dir++;
- addr += PGDIR_SIZE;
- /* Second level pages must be 64byte aligned. */
- second_level_entry += (SECOND_LEVEL_ALIGN /
- sizeof(unsigned long));
- pages--;
- }
- load_pgd(swapper_pg_dir, hard_processor_id());
- flush_tlb_all();
-#endif
-
- repriv_mmu_tables();
- register_syscore_ops(&mmu_syscore_ops);
-}
diff --git a/arch/metag/mm/numa.c b/arch/metag/mm/numa.c
deleted file mode 100644
index 67b46c295072..000000000000
--- a/arch/metag/mm/numa.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Multiple memory node support for Meta machines
- *
- * Copyright (C) 2007 Paul Mundt
- * Copyright (C) 2010 Imagination Technologies Ltd.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/export.h>
-#include <linux/bootmem.h>
-#include <linux/memblock.h>
-#include <linux/mm.h>
-#include <linux/numa.h>
-#include <linux/pfn.h>
-#include <asm/sections.h>
-
-struct pglist_data *node_data[MAX_NUMNODES] __read_mostly;
-EXPORT_SYMBOL_GPL(node_data);
-
-extern char _heap_start[];
-
-/*
- * On Meta machines the conventional approach is to stash system RAM
- * in node 0, and other memory blocks in to node 1 and up, ordered by
- * latency. Each node's pgdat is node-local at the beginning of the node,
- * immediately followed by the node mem map.
- */
-void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
-{
- unsigned long bootmap_pages, bootmem_paddr;
- unsigned long start_pfn, end_pfn;
- unsigned long pgdat_paddr;
-
- /* Don't allow bogus node assignment */
- BUG_ON(nid >= MAX_NUMNODES || nid <= 0);
-
- start_pfn = start >> PAGE_SHIFT;
- end_pfn = end >> PAGE_SHIFT;
-
- memblock_add(start, end - start);
-
- memblock_set_node(PFN_PHYS(start_pfn),
- PFN_PHYS(end_pfn - start_pfn),
- &memblock.memory, nid);
-
- /* Node-local pgdat */
- pgdat_paddr = memblock_alloc_base(sizeof(struct pglist_data),
- SMP_CACHE_BYTES, end);
- NODE_DATA(nid) = __va(pgdat_paddr);
- memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
-
- NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
- NODE_DATA(nid)->node_start_pfn = start_pfn;
- NODE_DATA(nid)->node_spanned_pages = end_pfn - start_pfn;
-
- /* Node-local bootmap */
- bootmap_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
- bootmem_paddr = memblock_alloc_base(bootmap_pages << PAGE_SHIFT,
- PAGE_SIZE, end);
- init_bootmem_node(NODE_DATA(nid), bootmem_paddr >> PAGE_SHIFT,
- start_pfn, end_pfn);
-
- free_bootmem_with_active_regions(nid, end_pfn);
-
- /* Reserve the pgdat and bootmap space with the bootmem allocator */
- reserve_bootmem_node(NODE_DATA(nid), pgdat_paddr & PAGE_MASK,
- sizeof(struct pglist_data), BOOTMEM_DEFAULT);
- reserve_bootmem_node(NODE_DATA(nid), bootmem_paddr,
- bootmap_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
-
- /* It's up */
- node_set_online(nid);
-
- /* Kick sparsemem */
- sparse_memory_present_with_active_regions(nid);
-}
-
-void __init __weak soc_mem_setup(void)
-{
-}
diff --git a/arch/metag/oprofile/Makefile b/arch/metag/oprofile/Makefile
deleted file mode 100644
index dc92a4a3d618..000000000000
--- a/arch/metag/oprofile/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_OPROFILE) += oprofile.o
-
-oprofile-core-y += buffer_sync.o
-oprofile-core-y += cpu_buffer.o
-oprofile-core-y += event_buffer.o
-oprofile-core-y += oprof.o
-oprofile-core-y += oprofile_files.o
-oprofile-core-y += oprofile_stats.o
-oprofile-core-y += oprofilefs.o
-oprofile-core-y += timer_int.o
-oprofile-core-$(CONFIG_HW_PERF_EVENTS) += oprofile_perf.o
-
-oprofile-y += backtrace.o
-oprofile-y += common.o
-oprofile-y += $(addprefix ../../../drivers/oprofile/,$(oprofile-core-y))
-
-ccflags-y += -Werror
diff --git a/arch/metag/oprofile/backtrace.c b/arch/metag/oprofile/backtrace.c
deleted file mode 100644
index 7cc3f37cb40e..000000000000
--- a/arch/metag/oprofile/backtrace.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2010-2013 Imagination Technologies Ltd.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/oprofile.h>
-#include <linux/uaccess.h>
-#include <asm/processor.h>
-#include <asm/stacktrace.h>
-
-#include "backtrace.h"
-
-static void user_backtrace_fp(unsigned long __user *fp, unsigned int depth)
-{
- while (depth-- && access_ok(VERIFY_READ, fp, 8)) {
- unsigned long addr;
- unsigned long __user *fpnew;
- if (__copy_from_user_inatomic(&addr, fp + 1, sizeof(addr)))
- break;
- addr -= 4;
-
- oprofile_add_trace(addr);
-
- /* stack grows up, so frame pointers must decrease */
- if (__copy_from_user_inatomic(&fpnew, fp + 0, sizeof(fpnew)))
- break;
- if (fpnew >= fp)
- break;
- fp = fpnew;
- }
-}
-
-static int kernel_backtrace_frame(struct stackframe *frame, void *data)
-{
- unsigned int *depth = data;
-
- oprofile_add_trace(frame->pc);
-
- /* decrement depth and stop if we reach 0 */
- if ((*depth)-- == 0)
- return 1;
-
- /* otherwise onto the next frame */
- return 0;
-}
-
-void metag_backtrace(struct pt_regs * const regs, unsigned int depth)
-{
- if (user_mode(regs)) {
- unsigned long *fp = (unsigned long *)regs->ctx.AX[1].U0;
- user_backtrace_fp((unsigned long __user __force *)fp, depth);
- } else {
- struct stackframe frame;
- frame.fp = regs->ctx.AX[1].U0; /* A0FrP */
- frame.sp = user_stack_pointer(regs); /* A0StP */
- frame.lr = 0; /* from stack */
- frame.pc = regs->ctx.CurrPC; /* PC */
- walk_stackframe(&frame, &kernel_backtrace_frame, &depth);
- }
-}
diff --git a/arch/metag/oprofile/backtrace.h b/arch/metag/oprofile/backtrace.h
deleted file mode 100644
index 60adb862aa2c..000000000000
--- a/arch/metag/oprofile/backtrace.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _METAG_OPROFILE_BACKTRACE_H
-#define _METAG_OPROFILE_BACKTRACE_H
-
-void metag_backtrace(struct pt_regs * const regs, unsigned int depth);
-
-#endif
diff --git a/arch/metag/oprofile/common.c b/arch/metag/oprofile/common.c
deleted file mode 100644
index ba26152b3c00..000000000000
--- a/arch/metag/oprofile/common.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * arch/metag/oprofile/common.c
- *
- * Copyright (C) 2013 Imagination Technologies Ltd.
- *
- * Based on arch/sh/oprofile/common.c:
- *
- * Copyright (C) 2003 - 2010 Paul Mundt
- *
- * Based on arch/mips/oprofile/common.c:
- *
- * Copyright (C) 2004, 2005 Ralf Baechle
- * Copyright (C) 2005 MIPS Technologies, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/oprofile.h>
-#include <linux/perf_event.h>
-#include <linux/slab.h>
-
-#include "backtrace.h"
-
-#ifdef CONFIG_HW_PERF_EVENTS
-/*
- * This will need to be reworked when multiple PMUs are supported.
- */
-static char *metag_pmu_op_name;
-
-char *op_name_from_perf_id(void)
-{
- return metag_pmu_op_name;
-}
-
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- ops->backtrace = metag_backtrace;
-
- if (perf_num_counters() == 0)
- return -ENODEV;
-
- metag_pmu_op_name = kasprintf(GFP_KERNEL, "metag/%s",
- perf_pmu_name());
- if (unlikely(!metag_pmu_op_name))
- return -ENOMEM;
-
- return oprofile_perf_init(ops);
-}
-
-void oprofile_arch_exit(void)
-{
- oprofile_perf_exit();
- kfree(metag_pmu_op_name);
-}
-#else
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- ops->backtrace = metag_backtrace;
- /* fall back to timer interrupt PC sampling */
- return -ENODEV;
-}
-void oprofile_arch_exit(void) {}
-#endif /* CONFIG_HW_PERF_EVENTS */
diff --git a/arch/metag/tbx/Makefile b/arch/metag/tbx/Makefile
deleted file mode 100644
index 98bc5453cf24..000000000000
--- a/arch/metag/tbx/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for TBX library files..
-#
-
-asflags-y += -mmetac=2.1 -Wa,-mfpu=metac21 -mdsp
-asflags-$(CONFIG_SMP) += -DTBX_PERCPU_SP_SAVE
-
-ccflags-y += -mmetac=2.1
-
-lib-y += tbicore.o
-lib-y += tbictx.o
-lib-y += tbidefr.o
-lib-y += tbilogf.o
-lib-y += tbipcx.o
-lib-y += tbiroot.o
-lib-y += tbisoft.o
-lib-y += tbistring.o
-lib-y += tbitimer.o
-
-lib-$(CONFIG_METAG_DSP) += tbidspram.o
-lib-$(CONFIG_METAG_FPU) += tbictxfpu.o
diff --git a/arch/metag/tbx/tbicore.S b/arch/metag/tbx/tbicore.S
deleted file mode 100644
index a0838ebcb433..000000000000
--- a/arch/metag/tbx/tbicore.S
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * tbicore.S
- *
- * Copyright (C) 2001, 2002, 2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Core functions needed to support use of the thread binary interface for META
- * processors
- */
-
- .file "tbicore.S"
-/* Get data structures and defines from the TBI C header */
-#include <asm/metag_mem.h>
-#include <asm/metag_regs.h>
-#include <asm/tbx.h>
-
- .data
- .balign 8
- .global ___pTBISegs
- .type ___pTBISegs,object
-___pTBISegs:
- .quad 0 /* Segment list pointer with it's */
- .size ___pTBISegs,.-___pTBISegs
- /* own id or spin-lock location */
-/*
- * Return ___pTBISegs value specific to privilege level - not very complicated
- * at the moment
- *
- * Register Usage: D0Re0 is the result, D1Re0 is used as a scratch
- */
- .text
- .balign 4
- .global ___TBISegList
- .type ___TBISegList,function
-___TBISegList:
- MOVT A1LbP,#HI(___pTBISegs)
- ADD A1LbP,A1LbP,#LO(___pTBISegs)
- GETL D0Re0,D1Re0,[A1LbP]
- MOV PC,D1RtP
- .size ___TBISegList,.-___TBISegList
-
-/*
- * Search the segment list for a match given Id, pStart can be NULL
- *
- * Register Usage: D1Ar1 is pSeg, D0Ar2 is Id, D0Re0 is the result
- * D0Ar4, D1Ar3 are used as a scratch
- * NB: The PSTAT bit if Id in D0Ar2 may be toggled
- */
- .text
- .balign 4
- .global ___TBIFindSeg
- .type ___TBIFindSeg,function
-___TBIFindSeg:
- MOVT A1LbP,#HI(___pTBISegs)
- ADD A1LbP,A1LbP,#LO(___pTBISegs)
- GETL D1Ar3,D0Ar4,[A1LbP] /* Read segment list head */
- MOV D0Re0,TXSTATUS /* What priv level are we at? */
- CMP D1Ar1,#0 /* Is pStart provided? */
-/* Disable privilege adaption for now */
- ANDT D0Re0,D0Re0,#0 /*HI(TXSTATUS_PSTAT_BIT) ; Is PSTAT set? Zero if not */
- LSL D0Re0,D0Re0,#(TBID_PSTAT_S-TXSTATUS_PSTAT_S)
- XOR D0Ar2,D0Ar2,D0Re0 /* Toggle Id PSTAT if privileged */
- MOVNZ D1Ar3,D1Ar1 /* Use pStart if provided */
-$LFindSegLoop:
- ADDS D0Re0,D1Ar3,#0 /* End of list? Load result into D0Re0 */
- MOVZ PC,D1RtP /* If result is NULL we leave */
- GETL D1Ar3,D0Ar4,[D1Ar3] /* Read pLink and Id */
- CMP D0Ar4,D0Ar2 /* Does it match? */
- BNZ $LFindSegLoop /* Loop if there is no match */
- TST D0Re0,D0Re0 /* Clear zero flag - we found it! */
- MOV PC,D1RtP /* Return */
- .size ___TBIFindSeg,.-___TBIFindSeg
-
-/* Useful offsets to encode the lower bits of the lock/unlock addresses */
-#define UON (LINSYSEVENT_WR_ATOMIC_LOCK & 0xFFF8)
-#define UOFF (LINSYSEVENT_WR_ATOMIC_UNLOCK & 0xFFF8)
-
-/*
- * Perform a whole spin-lock sequence as used by the TBISignal routine
- *
- * Register Usage: D1Ar1 is pLock, D0Ar2 is Mask, D0Re0 is the result
- * (All other usage due to ___TBIPoll - D0Ar6, D1Re0)
- */
- .text
- .balign 4
- .global ___TBISpin
- .type ___TBISpin,function
-___TBISpin:
- SETL [A0StP++],D0FrT,D1RtP /* Save our return address */
- ORS D0Re0,D0Re0,#1 /* Clear zero flag */
- MOV D1RtP,PC /* Setup return address to form loop */
-$LSpinLoop:
- BNZ ___TBIPoll /* Keep repeating if fail to set */
- GETL D0FrT,D1RtP,[--A0StP] /* Restore return address */
- MOV PC,D1RtP /* Return */
- .size ___TBISpin,.-___TBISpin
-
-/*
- * Perform an attempt to gain access to a spin-lock and set some bits
- *
- * Register Usage: D1Ar1 is pLock, D0Ar2 is Mask, D0Re0 is the result
- * !!On return Zero flag is SET if we are sucessfull!!
- * A0.3 is used to hold base address of system event region
- * D1Re0 use to hold TXMASKI while interrupts are off
- */
- .text
- .balign 4
- .global ___TBIPoll
- .type ___TBIPoll,function
-___TBIPoll:
- MOV D1Re0,#0 /* Prepare to disable ints */
- MOVT A0.3,#HI(LINSYSEVENT_WR_ATOMIC_LOCK)
- SWAP D1Re0,TXMASKI /* Really stop ints */
- LOCK2 /* Gain all locks */
- SET [A0.3+#UON],D1RtP /* Stop shared memory access too */
- DCACHE [D1Ar1],A0.3 /* Flush Cache line */
- GETD D0Re0,[D1Ar1] /* Get new state from memory or hit */
- DCACHE [D1Ar1],A0.3 /* Flush Cache line */
- GETD D0Re0,[D1Ar1] /* Get current state */
- TST D0Re0,D0Ar2 /* Are we clear to send? */
- ORZ D0Re0,D0Re0,D0Ar2 /* Yes: So set bits and */
- SETDZ [D1Ar1],D0Re0 /* transmit new state */
- SET [A0.3+#UOFF],D1RtP /* Allow shared memory access */
- LOCK0 /* Release all locks */
- MOV TXMASKI,D1Re0 /* Allow ints */
-$LPollEnd:
- XORNZ D0Re0,D0Re0,D0Re0 /* No: Generate zero result */
- MOV PC,D1RtP /* Return (NZ indicates failure) */
- .size ___TBIPoll,.-___TBIPoll
-
-/*
- * End of tbicore.S
- */
diff --git a/arch/metag/tbx/tbictx.S b/arch/metag/tbx/tbictx.S
deleted file mode 100644
index 19af983a13ae..000000000000
--- a/arch/metag/tbx/tbictx.S
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * tbictx.S
- *
- * Copyright (C) 2001, 2002, 2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Explicit state save and restore routines forming part of the thread binary
- * interface for META processors
- */
-
- .file "tbictx.S"
-#include <asm/metag_regs.h>
-#include <asm/tbx.h>
-
-#ifdef METAC_1_0
-/* Ax.4 is NOT saved in XAX3 */
-#define A0_4
-#else
-/* Ax.4 is saved in XAX4 */
-#define A0_4 A0.4,
-#endif
-
-
-/* Size of the TBICTX structure */
-#define TBICTX_BYTES ((TBICTX_AX_REGS*8)+TBICTX_AX)
-
-/*
- * TBIRES __TBINestInts( TBIRES State, void *pExt, int NoNestMask )
- */
- .text
- .balign 4
- .global ___TBINestInts
- .type ___TBINestInts,function
-___TBINestInts:
- XOR D0Ar4,D0Ar4,#-1 /* D0Ar4 = ~TrigBit */
- AND D0Ar4,D0Ar4,#0xFFFF /* D0Ar4 &= 0xFFFF */
- MOV D0Ar6,TXMASKI /* BGNDHALT currently enabled? */
- TSTT D0Ar2,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XCBF_BIT
- AND D0Ar4,D0Ar2,D0Ar4 /* D0Ar4 = Ints to allow */
- XOR D0Ar2,D0Ar2,D0Ar4 /* Less Ints in TrigMask */
- BNZ ___TBINestInts2 /* Jump if ctx save required! */
- TSTT D0Ar2,#TBICTX_CBUF_BIT+TBICTX_CBRP_BIT /* Is catch state dirty? */
- OR D0Ar4,D0Ar4,D0Ar6 /* Or in TXMASKI BGNDHALT if set */
- TSTNZ D0Ar4,D0Ar4 /* Yes: AND triggers enabled */
- MOV D0Re0,D0Ar2 /* Update State argument */
- MOV D1Re0,D1Ar1 /* with less Ints in TrigMask */
- MOVZ TXMASKI,D0Ar4 /* Early return: Enable Ints */
- MOVZ PC,D1RtP /* Early return */
- .size ___TBINestInts,.-___TBINestInts
-/*
- * Drop thru into sub-function-
- */
- .global ___TBINestInts2
- .type ___TBINestInts2,function
-___TBINestInts2:
- MOV D0FrT,A0FrP /* Full entry sequence so we */
- ADD A0FrP,A0StP,#0 /* can make sub-calls */
- MSETL [A0StP],D0FrT,D0.5,D0.6 /* and preserve our result */
- ORT D0Ar2,D0Ar2,#TBICTX_XCBF_BIT /* Add in XCBF save request */
- MOV D0.5,D0Ar2 /* Save State in DX.5 */
- MOV D1.5,D1Ar1
- OR D0.6,D0Ar4,D0Ar6 /* Save TrigMask in D0.6 */
- MOVT D1RtP,#HI(___TBICtxSave) /* Save catch buffer */
- CALL D1RtP,#LO(___TBICtxSave)
- MOV TXMASKI,D0.6 /* Allow Ints */
- MOV D0Re0,D0.5 /* Return State */
- MOV D1Re0,D1.5
- MGETL D0FrT,D0.5,D0.6,[A0FrP] /* Full exit sequence */
- SUB A0StP,A0FrP,#(8*3)
- MOV A0FrP,D0FrT
- MOV PC,D1RtP
- .size ___TBINestInts2,.-___TBINestInts2
-
-/*
- * void *__TBICtxSave( TBIRES State, void *pExt )
- *
- * D0Ar2 contains TBICTX_*_BIT values that control what
- * extended data is to be saved beyond the end of D1Ar1.
- * These bits must be ored into the SaveMask of this structure.
- *
- * Virtually all possible scratch registers are used.
- *
- * The D1Ar1 parameter is only used as the basis for saving
- * CBUF state.
- */
-/*
- * If TBICTX_XEXT_BIT is specified in State. then State.pCtx->Ext is
- * utilised to save the base address of the context save area and
- * the extended states saved. The XEXT flag then indicates that the
- * original state of the A0.2 and A1.2 registers from TBICTX.Ext.AX2
- * are stored as the first part of the extended state structure.
- */
- .balign 4
- .global ___TBICtxSave
- .type ___TBICtxSave,function
-___TBICtxSave:
- GETD D0Re0,[D1Ar1+#TBICTX_SaveMask-2] /* Get SaveMask */
- TSTT D0Ar2,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XEXT_BIT
- /* Just XCBF to save? */
- MOV A0.2,D1Ar3 /* Save pointer into A0.2 */
- MOV A1.2,D1RtP /* Free off D0FrT:D1RtP pair */
- BZ $LCtxSaveCBUF /* Yes: Only XCBF may be saved */
- TSTT D0Ar2,#TBICTX_XEXT_BIT /* Extended base-state model? */
- BZ $LCtxSaveXDX8
- GETL D0Ar6,D1Ar5,[D1Ar1+#TBICTX_Ext_AX2] /* Get A0.2, A1.2 state */
- MOV D0Ar4,D0Ar2 /* Extract Ctx.SaveFlags value */
- ANDMT D0Ar4,D0Ar4,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XEXT_BIT
- SETD [D1Ar1+#TBICTX_Ext_Ctx_pExt],A0.2
- SETD [D1Ar1+#TBICTX_Ext_Ctx_SaveMask-2],D0Ar4
- SETL [A0.2++],D0Ar6,D1Ar5 /* Save A0.2, A1.2 state */
-$LCtxSaveXDX8:
- TSTT D0Ar2,#TBICTX_XDX8_BIT /* Save extended DX regs? */
- BZ $LCtxSaveXAXX
-/*
- * Save 8 extra DX registers
- */
- MSETL [A0.2],D0.8,D0.9,D0.10,D0.11,D0.12,D0.13,D0.14,D0.15
-$LCtxSaveXAXX:
- TSTT D0Ar2,#TBICTX_XAXX_BIT /* Save extended AX regs? */
- SWAP D0Re0,A0.2 /* pDst into D0Re0 */
- BZ $LCtxSaveXHL2
-/*
- * Save 4 extra AX registers
- */
- MSETL [D0Re0], A0_4 A0.5,A0.6,A0.7 /* Save 8*3 bytes */
-$LCtxSaveXHL2:
- TSTT D0Ar2,#TBICTX_XHL2_BIT /* Save hardware-loop regs? */
- SWAP D0Re0,A0.2 /* pDst back into A0.2 */
- MOV D0Ar6,TXL1START
- MOV D1Ar5,TXL2START
- BZ $LCtxSaveXTDP
-/*
- * Save hardware loop registers
- */
- SETL [A0.2++],D0Ar6,D1Ar5 /* Save 8*1 bytes */
- MOV D0Ar6,TXL1END
- MOV D1Ar5,TXL2END
- MOV D0FrT,TXL1COUNT
- MOV D1RtP,TXL2COUNT
- MSETL [A0.2],D0Ar6,D0FrT /* Save 8*2 bytes */
-/*
- * Clear loop counters to disable any current loops
- */
- XOR TXL1COUNT,D0FrT,D0FrT
- XOR TXL2COUNT,D1RtP,D1RtP
-$LCtxSaveXTDP:
- TSTT D0Ar2,#TBICTX_XTDP_BIT /* Save per-thread DSP regs? */
- BZ $LCtxSaveCBUF
-/*
- * Save per-thread DSP registers; ACC.0, PR.0, PI.1-3 (PI.0 is zero)
- */
-#ifndef CTX_NO_DSP
-D SETL [A0.2++],AC0.0,AC1.0 /* Save ACx.0 lower 32-bits */
-DH SETL [A0.2++],AC0.0,AC1.0 /* Save ACx.0 upper 32-bits */
-D SETL [A0.2++],D0AR.0,D1AR.0 /* Save DSP RAM registers */
-D SETL [A0.2++],D0AR.1,D1AR.1
-D SETL [A0.2++],D0AW.0,D1AW.0
-D SETL [A0.2++],D0AW.1,D1AW.1
-D SETL [A0.2++],D0BR.0,D1BR.0
-D SETL [A0.2++],D0BR.1,D1BR.1
-D SETL [A0.2++],D0BW.0,D1BW.0
-D SETL [A0.2++],D0BW.1,D1BW.1
-D SETL [A0.2++],D0ARI.0,D1ARI.0
-D SETL [A0.2++],D0ARI.1,D1ARI.1
-D SETL [A0.2++],D0AWI.0,D1AWI.0
-D SETL [A0.2++],D0AWI.1,D1AWI.1
-D SETL [A0.2++],D0BRI.0,D1BRI.0
-D SETL [A0.2++],D0BRI.1,D1BRI.1
-D SETL [A0.2++],D0BWI.0,D1BWI.0
-D SETL [A0.2++],D0BWI.1,D1BWI.1
-D SETD [A0.2++],T0
-D SETD [A0.2++],T1
-D SETD [A0.2++],T2
-D SETD [A0.2++],T3
-D SETD [A0.2++],T4
-D SETD [A0.2++],T5
-D SETD [A0.2++],T6
-D SETD [A0.2++],T7
-D SETD [A0.2++],T8
-D SETD [A0.2++],T9
-D SETD [A0.2++],TA
-D SETD [A0.2++],TB
-D SETD [A0.2++],TC
-D SETD [A0.2++],TD
-D SETD [A0.2++],TE
-D SETD [A0.2++],TF
-#else
- ADD A0.2,A0.2,#(8*18+4*16)
-#endif
- MOV D0Ar6,TXMRSIZE
- MOV D1Ar5,TXDRSIZE
- SETL [A0.2++],D0Ar6,D1Ar5 /* Save 8*1 bytes */
-
-$LCtxSaveCBUF:
-#ifdef TBI_1_3
- MOV D0Ar4,D0Re0 /* Copy Ctx Flags */
- ANDT D0Ar4,D0Ar4,#TBICTX_XCBF_BIT /* mask XCBF if already set */
- XOR D0Ar4,D0Ar4,#-1
- AND D0Ar2,D0Ar2,D0Ar4 /* remove XCBF if already set */
-#endif
- TSTT D0Ar2,#TBICTX_XCBF_BIT /* Want to save CBUF? */
- ANDT D0Ar2,D0Ar2,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XEXT_BIT
- OR D0Ar2,D0Ar2,D0Re0 /* Generate new SaveMask */
- SETD [D1Ar1+#TBICTX_SaveMask-2],D0Ar2/* Add in bits saved to TBICTX */
- MOV D0Re0,A0.2 /* Return end of save area */
- MOV D0Ar4,TXDIVTIME /* Get TXDIVTIME */
- MOVZ PC,A1.2 /* No: Early return */
- TSTT D0Ar2,#TBICTX_CBUF_BIT+TBICTX_CBRP_BIT /* Need to save CBUF? */
- MOVZ PC,A1.2 /* No: Early return */
- ORT D0Ar2,D0Ar2,#TBICTX_XCBF_BIT
- SETD [D1Ar1+#TBICTX_SaveMask-2],D0Ar2/* Add in XCBF bit to TBICTX */
- ADD A0.2,D1Ar1,#TBICTX_BYTES /* Dump CBUF state after TBICTX */
-/*
- * Save CBUF
- */
- SETD [A0.2+# 0],TXCATCH0 /* Restore TXCATCHn */
- SETD [A0.2+# 4],TXCATCH1
- TSTT D0Ar2,#TBICTX_CBRP_BIT /* ... RDDIRTY was/is set */
- SETD [A0.2+# 8],TXCATCH2
- SETD [A0.2+#12],TXCATCH3
- BZ $LCtxSaveComplete
- SETL [A0.2+#(2*8)],RD /* Save read pipeline */
- SETL [A0.2+#(3*8)],RD /* Save read pipeline */
- SETL [A0.2+#(4*8)],RD /* Save read pipeline */
- SETL [A0.2+#(5*8)],RD /* Save read pipeline */
- SETL [A0.2+#(6*8)],RD /* Save read pipeline */
- SETL [A0.2+#(7*8)],RD /* Save read pipeline */
- AND TXDIVTIME,D0Ar4,#TXDIVTIME_DIV_BITS /* Clear RPDIRTY */
-$LCtxSaveComplete:
- MOV PC,A1.2 /* Return */
- .size ___TBICtxSave,.-___TBICtxSave
-
-/*
- * void *__TBICtxRestore( TBIRES State, void *pExt )
- *
- * D0Ar2 contains TBICTX_*_BIT values that control what
- * extended data is to be recovered from D1Ar3 (pExt).
- *
- * Virtually all possible scratch registers are used.
- */
-/*
- * If TBICTX_XEXT_BIT is specified in State. Then the saved state of
- * the orginal A0.2 and A1.2 is restored from pExt and the XEXT
- * related flags are removed from State.pCtx->SaveMask.
- *
- */
- .balign 4
- .global ___TBICtxRestore
- .type ___TBICtxRestore,function
-___TBICtxRestore:
- GETD D0Ar6,[D1Ar1+#TBICTX_CurrMODE] /* Get TXMODE Value */
- ANDST D0Ar2,D0Ar2,#TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XEXT_BIT
- MOV D1Re0,D0Ar2 /* Keep flags in D1Re0 */
- MOV D0Re0,D1Ar3 /* D1Ar3 is default result */
- MOVZ PC,D1RtP /* Early return, nothing to do */
- ANDT D0Ar6,D0Ar6,#0xE000 /* Top bits of TXMODE required */
- MOV A0.3,D0Ar6 /* Save TXMODE for later */
- TSTT D1Re0,#TBICTX_XEXT_BIT /* Check for XEXT bit */
- BZ $LCtxRestXDX8
- GETD D0Ar4,[D1Ar1+#TBICTX_SaveMask-2]/* Get current SaveMask */
- GETL D0Ar6,D1Ar5,[D0Re0++] /* Restore A0.2, A1.2 state */
- ANDMT D0Ar4,D0Ar4,#(0xFFFF-(TBICTX_XDX8_BIT+TBICTX_XAXX_BIT+TBICTX_XHL2_BIT+TBICTX_XTDP_BIT+TBICTX_XEXT_BIT))
- SETD [D1Ar1+#TBICTX_SaveMask-2],D0Ar4/* New SaveMask */
-#ifdef METAC_1_0
- SETD [D1Ar1+#TBICTX_Ext_AX2_U0],D0Ar6
- MOV D0Ar6,D1Ar1
- SETD [D0Ar6+#TBICTX_Ext_AX2_U1],D1Ar5
-#else
- SETL [D1Ar1+#TBICTX_Ext_AX2],D0Ar6,D1Ar5
-#endif
-$LCtxRestXDX8:
- TSTT D1Re0,#TBICTX_XDX8_BIT /* Get extended DX regs? */
- MOV A1.2,D1RtP /* Free off D1RtP register */
- BZ $LCtxRestXAXX
-/*
- * Restore 8 extra DX registers
- */
- MGETL D0.8,D0.9,D0.10,D0.11,D0.12,D0.13,D0.14,D0.15,[D0Re0]
-$LCtxRestXAXX:
- TSTT D1Re0,#TBICTX_XAXX_BIT /* Get extended AX regs? */
- BZ $LCtxRestXHL2
-/*
- * Restore 3 extra AX registers
- */
- MGETL A0_4 A0.5,A0.6,A0.7,[D0Re0] /* Get 8*3 bytes */
-$LCtxRestXHL2:
- TSTT D1Re0,#TBICTX_XHL2_BIT /* Get hardware-loop regs? */
- BZ $LCtxRestXTDP
-/*
- * Get hardware loop registers
- */
- MGETL D0Ar6,D0Ar4,D0Ar2,[D0Re0] /* Get 8*3 bytes */
- MOV TXL1START,D0Ar6
- MOV TXL2START,D1Ar5
- MOV TXL1END,D0Ar4
- MOV TXL2END,D1Ar3
- MOV TXL1COUNT,D0Ar2
- MOV TXL2COUNT,D1Ar1
-$LCtxRestXTDP:
- TSTT D1Re0,#TBICTX_XTDP_BIT /* Get per-thread DSP regs? */
- MOVZ PC,A1.2 /* No: Early return */
-/*
- * Get per-thread DSP registers; ACC.0, PR.0, PI.1-3 (PI.0 is zero)
- */
- MOV A0.2,D0Re0
- GETL D0Ar6,D1Ar5,[D0Re0++#((16*4)+(18*8))]
-#ifndef CTX_NO_DSP
-D GETL AC0.0,AC1.0,[A0.2++] /* Restore ACx.0 lower 32-bits */
-DH GETL AC0.0,AC1.0,[A0.2++] /* Restore ACx.0 upper 32-bits */
-#else
- ADD A0.2,A0.2,#(2*8)
-#endif
- ADD D0Re0,D0Re0,#(2*4)
- MOV TXMODE,A0.3 /* Some TXMODE bits needed */
- MOV TXMRSIZE,D0Ar6
- MOV TXDRSIZE,D1Ar5
-#ifndef CTX_NO_DSP
-D GETL D0AR.0,D1AR.0,[A0.2++] /* Restore DSP RAM registers */
-D GETL D0AR.1,D1AR.1,[A0.2++]
-D GETL D0AW.0,D1AW.0,[A0.2++]
-D GETL D0AW.1,D1AW.1,[A0.2++]
-D GETL D0BR.0,D1BR.0,[A0.2++]
-D GETL D0BR.1,D1BR.1,[A0.2++]
-D GETL D0BW.0,D1BW.0,[A0.2++]
-D GETL D0BW.1,D1BW.1,[A0.2++]
-#else
- ADD A0.2,A0.2,#(8*8)
-#endif
- MOV TXMODE,#0 /* Restore TXMODE */
-#ifndef CTX_NO_DSP
-D GETL D0ARI.0,D1ARI.0,[A0.2++]
-D GETL D0ARI.1,D1ARI.1,[A0.2++]
-D GETL D0AWI.0,D1AWI.0,[A0.2++]
-D GETL D0AWI.1,D1AWI.1,[A0.2++]
-D GETL D0BRI.0,D1BRI.0,[A0.2++]
-D GETL D0BRI.1,D1BRI.1,[A0.2++]
-D GETL D0BWI.0,D1BWI.0,[A0.2++]
-D GETL D0BWI.1,D1BWI.1,[A0.2++]
-D GETD T0,[A0.2++]
-D GETD T1,[A0.2++]
-D GETD T2,[A0.2++]
-D GETD T3,[A0.2++]
-D GETD T4,[A0.2++]
-D GETD T5,[A0.2++]
-D GETD T6,[A0.2++]
-D GETD T7,[A0.2++]
-D GETD T8,[A0.2++]
-D GETD T9,[A0.2++]
-D GETD TA,[A0.2++]
-D GETD TB,[A0.2++]
-D GETD TC,[A0.2++]
-D GETD TD,[A0.2++]
-D GETD TE,[A0.2++]
-D GETD TF,[A0.2++]
-#else
- ADD A0.2,A0.2,#(8*8+4*16)
-#endif
- MOV PC,A1.2 /* Return */
- .size ___TBICtxRestore,.-___TBICtxRestore
-
-/*
- * End of tbictx.S
- */
diff --git a/arch/metag/tbx/tbictxfpu.S b/arch/metag/tbx/tbictxfpu.S
deleted file mode 100644
index e773bea3e7bd..000000000000
--- a/arch/metag/tbx/tbictxfpu.S
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * tbictxfpu.S
- *
- * Copyright (C) 2009, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Explicit state save and restore routines forming part of the thread binary
- * interface for META processors
- */
-
- .file "tbifpuctx.S"
-
-#include <asm/metag_regs.h>
-#include <asm/tbx.h>
-
-#ifdef TBI_1_4
-/*
- * void *__TBICtxFPUSave( TBIRES State, void *pExt )
- *
- * D0Ar2 contains TBICTX_*_BIT values that control what
- * extended data is to be saved.
- * These bits must be ored into the SaveMask of this structure.
- *
- * Virtually all possible scratch registers are used.
- */
- .text
- .balign 4
- .global ___TBICtxFPUSave
- .type ___TBICtxFPUSave,function
-___TBICtxFPUSave:
-
- /* D1Ar1:D0Ar2 - State
- * D1Ar3 - pExt
- * D0Ar4 - Value of METAC_CORE_ID
- * D1Ar5 - Scratch
- * D0Ar6 - Scratch
- */
-
- /* If the FPAC bit isnt set then there is nothing to do */
- TSTT D0Ar2,#TBICTX_FPAC_BIT
- MOVZ PC, D1RtP
-
- /* Obtain the Core config */
- MOVT D0Ar4, #HI(METAC_CORE_ID)
- ADD D0Ar4, D0Ar4, #LO(METAC_CORE_ID)
- GETD D0Ar4, [D0Ar4]
-
- /* Detect FX.8 - FX.15 and add to core config */
- MOV D0Ar6, TXENABLE
- AND D0Ar6, D0Ar6, #(TXENABLE_CLASSALT_FPUR8 << TXENABLE_CLASS_S)
- AND D0Ar4, D0Ar4, #LO(0x0000FFFF)
- ORT D0Ar4, D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT)
- XOR D0Ar4, D0Ar4, D0Ar6
-
- /* Save the relevant bits to the buffer */
- SETD [D1Ar3++], D0Ar4
-
- /* Save the relevant bits of TXDEFR (Assumes TXDEFR is coherent) ... */
- MOV D0Ar6, TXDEFR
- LSR D0Re0, D0Ar6, #8
- AND D0Re0, D0Re0, #LO(TXDEFR_FPE_FE_BITS>>8)
- AND D0Ar6, D0Ar6, #LO(TXDEFR_FPE_ICTRL_BITS)
- OR D0Re0, D0Re0, D0Ar6
-
- /* ... along with relevant bits of TXMODE to buffer */
- MOV D0Ar6, TXMODE
- ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS)
- ORT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODEWRITE_BIT)
- OR D0Ar6, D0Ar6, D0Re0
- SETD [D1Ar3++], D0Ar6
-
- GETD D0Ar6,[D1Ar1+#TBICTX_SaveMask-2] /* Get the current SaveMask */
- /* D0Ar6 - pCtx->SaveMask */
-
- TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
- * to avoid stalls
- */
- /* Save the standard FPU registers */
-F MSETL [D1Ar3++], FX.0, FX.2, FX.4, FX.6
-
- /* Save the extended FPU registers if they are present */
- BZ $Lskip_save_fx8_fx16
-F MSETL [D1Ar3++], FX.8, FX.10, FX.12, FX.14
-$Lskip_save_fx8_fx16:
-
- /* Save the FPU Accumulator if it is present */
- TST D0Ar4, #METAC_COREID_NOFPACC_BIT
- BNZ $Lskip_save_fpacc
-F SETL [D1Ar3++], ACF.0
-F SETL [D1Ar3++], ACF.1
-F SETL [D1Ar3++], ACF.2
-$Lskip_save_fpacc:
-
- /* Update pCtx->SaveMask */
- ANDT D0Ar2, D0Ar2, #TBICTX_FPAC_BIT
- OR D0Ar6, D0Ar6, D0Ar2
- SETD [D1Ar1+#TBICTX_SaveMask-2],D0Ar6/* Add in XCBF bit to TBICTX */
-
- MOV D0Re0, D1Ar3 /* Return end of save area */
- MOV PC, D1RtP
-
- .size ___TBICtxFPUSave,.-___TBICtxFPUSave
-
-/*
- * void *__TBICtxFPURestore( TBIRES State, void *pExt )
- *
- * D0Ar2 contains TBICTX_*_BIT values that control what
- * extended data is to be recovered from D1Ar3 (pExt).
- *
- * Virtually all possible scratch registers are used.
- */
-/*
- * If TBICTX_XEXT_BIT is specified in State. Then the saved state of
- * the orginal A0.2 and A1.2 is restored from pExt and the XEXT
- * related flags are removed from State.pCtx->SaveMask.
- *
- */
- .balign 4
- .global ___TBICtxFPURestore
- .type ___TBICtxFPURestore,function
-___TBICtxFPURestore:
-
- /* D1Ar1:D0Ar2 - State
- * D1Ar3 - pExt
- * D0Ar4 - Value of METAC_CORE_ID
- * D1Ar5 - Scratch
- * D0Ar6 - Scratch
- * D1Re0 - Scratch
- */
-
- /* If the FPAC bit isnt set then there is nothing to do */
- TSTT D0Ar2,#TBICTX_FPAC_BIT
- MOVZ PC, D1RtP
-
- /* Obtain the relevant bits of the Core config */
- GETD D0Ar4, [D1Ar3++]
-
- /* Restore FPU related parts of TXDEFR. Assumes TXDEFR is coherent */
- GETD D1Ar5, [D1Ar3++]
- MOV D0Ar6, D1Ar5
- LSL D1Re0, D1Ar5, #8
- ANDT D1Re0, D1Re0, #HI(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
- AND D1Ar5, D1Ar5, #LO(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
- OR D1Re0, D1Re0, D1Ar5
-
- MOV D1Ar5, TXDEFR
- ANDMT D1Ar5, D1Ar5, #HI(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
- ANDMB D1Ar5, D1Ar5, #LO(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
- OR D1Re0, D1Re0, D1Ar5
- MOV TXDEFR, D1Re0
-
- /* Restore relevant bits of TXMODE */
- MOV D1Ar5, TXMODE
- ANDMT D1Ar5, D1Ar5, #HI(~TXMODE_FPURMODE_BITS)
- ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS|TXMODE_FPURMODEWRITE_BIT)
- OR D0Ar6, D0Ar6, D1Ar5
- MOV TXMODE, D0Ar6
-
- TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
- * to avoid stalls
- */
- /* Save the standard FPU registers */
-F MGETL FX.0, FX.2, FX.4, FX.6, [D1Ar3++]
-
- /* Save the extended FPU registers if they are present */
- BZ $Lskip_restore_fx8_fx16
-F MGETL FX.8, FX.10, FX.12, FX.14, [D1Ar3++]
-$Lskip_restore_fx8_fx16:
-
- /* Save the FPU Accumulator if it is present */
- TST D0Ar4, #METAC_COREID_NOFPACC_BIT
- BNZ $Lskip_restore_fpacc
-F GETL ACF.0, [D1Ar3++]
-F GETL ACF.1, [D1Ar3++]
-F GETL ACF.2, [D1Ar3++]
-$Lskip_restore_fpacc:
-
- MOV D0Re0, D1Ar3 /* Return end of save area */
- MOV PC, D1RtP
-
- .size ___TBICtxFPURestore,.-___TBICtxFPURestore
-
-#endif /* TBI_1_4 */
-
-/*
- * End of tbictx.S
- */
diff --git a/arch/metag/tbx/tbidefr.S b/arch/metag/tbx/tbidefr.S
deleted file mode 100644
index 8f0902b22f70..000000000000
--- a/arch/metag/tbx/tbidefr.S
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * tbidefr.S
- *
- * Copyright (C) 2009, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Routing deferred exceptions
- */
-
-#include <asm/metag_regs.h>
-#include <asm/tbx.h>
-
- .text
- .balign 4
- .global ___TBIHandleDFR
- .type ___TBIHandleDFR,function
-/* D1Ar1:D0Ar2 -- State
- * D0Ar3 -- SigNum
- * D0Ar4 -- Triggers
- * D1Ar5 -- Inst
- * D0Ar6 -- pTBI (volatile)
- */
-___TBIHandleDFR:
-#ifdef META_BUG_MBN100212
- MSETL [A0StP++], D0FrT, D0.5
-
- /* D1Ar1,D0Ar2,D1Ar5,D0Ar6 -- Arguments to handler, must be preserved
- * D0Ar4 -- The deferred exceptions
- * D1Ar3 -- As per D0Ar4 but just the trigger bits
- * D0.5 -- The bgnd deferred exceptions
- * D1.5 -- TXDEFR with bgnd re-added
- */
-
- /* - Collect the pending deferred exceptions using TXSTAT,
- * (ack's the bgnd exceptions as a side-effect)
- * - Manually collect remaining (interrupt) deferred exceptions
- * using TXDEFR
- * - Replace the triggers (from TXSTATI) with the int deferred
- * exceptions DEFR ..., TXSTATI would have returned if it was valid
- * from bgnd code
- * - Reconstruct TXDEFR by or'ing bgnd deferred exceptions (except
- * the DEFER bit) and the int deferred exceptions. This will be
- * restored later
- */
- DEFR D0.5, TXSTAT
- MOV D1.5, TXDEFR
- ANDT D0.5, D0.5, #HI(0xFFFF0000)
- MOV D1Ar3, D1.5
- ANDT D1Ar3, D1Ar3, #HI(0xFFFF0000)
- OR D0Ar4, D1Ar3, #TXSTAT_DEFER_BIT
- OR D1.5, D1.5, D0.5
-
- /* Mask off anything unrelated to the deferred exception triggers */
- ANDT D1Ar3, D1Ar3, #HI(TXSTAT_BUSERR_BIT | TXSTAT_FPE_BITS)
-
- /* Can assume that at least one exception happened since this
- * handler wouldnt have been called otherwise.
- *
- * Replace the signal number and at the same time, prepare
- * the mask to acknowledge the exception
- *
- * D1Re0 -- The bits to acknowledge
- * D1Ar3 -- The signal number
- * D1RtP -- Scratch to deal with non-conditional insns
- */
- MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
- MOV D1RtP, #TXSTAT_FPE_INVALID_S
- FFB D1Ar3, D1Ar3
- CMP D1Ar3, #TXSTAT_FPE_INVALID_S
- MOVLE D1Ar3, D1RtP /* Collapse FPE triggers to a single signal */
- MOV D1RtP, #1
- LSLGT D1Re0, D1RtP, D1Ar3
-
- /* Get the handler using the signal number
- *
- * D1Ar3 -- The signal number
- * D0Re0 -- Offset into TBI struct containing handler address
- * D1Re0 -- Mask of triggers to keep
- * D1RtP -- Address of handler
- */
- SUB D1Ar3, D1Ar3, #(TXSTAT_FPE_INVALID_S - TBID_SIGNUM_FPE)
- LSL D0Re0, D1Ar3, #2
- XOR D1Re0, D1Re0, #-1 /* Prepare mask for acknowledge (avoids stall) */
- ADD D0Re0,D0Re0,#TBI_fnSigs
- GETD D1RtP, [D0Ar6+D0Re0]
-
- /* Acknowledge triggers */
- AND D1.5, D1.5, D1Re0
-
- /* Restore remaining exceptions
- * Do this here in case the handler enables nested interrupts
- *
- * D1.5 -- TXDEFR with this exception ack'd
- */
- MOV TXDEFR, D1.5
-
- /* Call the handler */
- SWAP D1RtP, PC
-
- GETL D0.5, D1.5, [--A0StP]
- GETL D0FrT, D1RtP, [--A0StP]
- MOV PC,D1RtP
-#else /* META_BUG_MBN100212 */
-
- /* D1Ar1,D0Ar2,D1Ar5,D0Ar6 -- Arguments to handler, must be preserved
- * D0Ar4 -- The deferred exceptions
- * D1Ar3 -- As per D0Ar4 but just the trigger bits
- */
-
- /* - Collect the pending deferred exceptions using TXSTAT,
- * (ack's the interrupt exceptions as a side-effect)
- */
- DEFR D0Ar4, TXSTATI
-
- /* Mask off anything unrelated to the deferred exception triggers */
- MOV D1Ar3, D0Ar4
- ANDT D1Ar3, D1Ar3, #HI(TXSTAT_BUSERR_BIT | TXSTAT_FPE_BITS)
-
- /* Can assume that at least one exception happened since this
- * handler wouldnt have been called otherwise.
- *
- * Replace the signal number and at the same time, prepare
- * the mask to acknowledge the exception
- *
- * The unusual code for 1<<D1Ar3 may need explanation.
- * Normally this would be done using 'MOV rs,#1' and 'LSL rd,rs,D1Ar3'
- * but only D1Re0 is available in D1 and no crossunit insns are available
- * Even worse, there is no conditional 'MOV r,#uimm8'.
- * Since the CMP proves that D1Ar3 >= 20, we can reuse the bottom 12-bits
- * of D1Re0 (using 'ORGT r,#1') in the knowledge that the top 20-bits will
- * be discarded without affecting the result.
- *
- * D1Re0 -- The bits to acknowledge
- * D1Ar3 -- The signal number
- */
- MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
- MOV D0Re0, #TXSTAT_FPE_INVALID_S
- FFB D1Ar3, D1Ar3
- CMP D1Ar3, #TXSTAT_FPE_INVALID_S
- MOVLE D1Ar3, D0Re0 /* Collapse FPE triggers to a single signal */
- ORGT D1Re0, D1Re0, #1
- LSLGT D1Re0, D1Re0, D1Ar3
-
- SUB D1Ar3, D1Ar3, #(TXSTAT_FPE_INVALID_S - TBID_SIGNUM_FPE)
-
- /* Acknowledge triggers and restore remaining exceptions
- * Do this here in case the handler enables nested interrupts
- *
- * (x | y) ^ y == x & ~y. It avoids the restrictive XOR ...,#-1 insn
- * and is the same length
- */
- MOV D0Re0, TXDEFR
- OR D0Re0, D0Re0, D1Re0
- XOR TXDEFR, D0Re0, D1Re0
-
- /* Get the handler using the signal number
- *
- * D1Ar3 -- The signal number
- * D0Re0 -- Address of handler
- */
- LSL D0Re0, D1Ar3, #2
- ADD D0Re0,D0Re0,#TBI_fnSigs
- GETD D0Re0, [D0Ar6+D0Re0]
-
- /* Tailcall the handler */
- MOV PC,D0Re0
-
-#endif /* META_BUG_MBN100212 */
- .size ___TBIHandleDFR,.-___TBIHandleDFR
-/*
- * End of tbidefr.S
- */
diff --git a/arch/metag/tbx/tbidspram.S b/arch/metag/tbx/tbidspram.S
deleted file mode 100644
index 2f27c0372212..000000000000
--- a/arch/metag/tbx/tbidspram.S
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * tbidspram.S
- *
- * Copyright (C) 2009, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Explicit state save and restore routines forming part of the thread binary
- * interface for META processors
- */
-
- .file "tbidspram.S"
-
-/* These aren't generally useful to a user so for now, they arent publically available */
-#define _TBIECH_DSPRAM_DUA_S 8
-#define _TBIECH_DSPRAM_DUA_BITS 0x7f00
-#define _TBIECH_DSPRAM_DUB_S 0
-#define _TBIECH_DSPRAM_DUB_BITS 0x007f
-
-/*
- * void *__TBIDspramSaveA( short DspramSizes, void *pExt )
- */
- .text
- .balign 4
- .global ___TBIDspramSaveA
- .type ___TBIDspramSaveA,function
-___TBIDspramSaveA:
-
- SETL [A0StP++], D0.5, D1.5
- MOV A0.3, D0Ar2
-
- /* D1Ar1 - Dspram Sizes
- * A0.4 - Pointer to buffer
- */
-
- /* Save the specified amount of dspram DUA */
-DL MOV D0AR.0, #0
- LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUA_S
- AND D1Ar1, D1Ar1, #(_TBIECH_DSPRAM_DUA_BITS >> _TBIECH_DSPRAM_DUA_S)
- SUB TXRPT, D1Ar1, #1
-$L1:
-DL MOV D0Re0, [D0AR.0++]
-DL MOV D0Ar6, [D0AR.0++]
-DL MOV D0Ar4, [D0AR.0++]
-DL MOV D0.5, [D0AR.0++]
- MSETL [A0.3++], D0Re0, D0Ar6, D0Ar4, D0.5
-
- BR $L1
-
- GETL D0.5, D1.5, [--A0StP]
- MOV PC, D1RtP
-
- .size ___TBIDspramSaveA,.-___TBIDspramSaveA
-
-/*
- * void *__TBIDspramSaveB( short DspramSizes, void *pExt )
- */
- .balign 4
- .global ___TBIDspramSaveB
- .type ___TBIDspramSaveB,function
-___TBIDspramSaveB:
-
- SETL [A0StP++], D0.5, D1.5
- MOV A0.3, D0Ar2
-
- /* D1Ar1 - Dspram Sizes
- * A0.3 - Pointer to buffer
- */
-
- /* Save the specified amount of dspram DUA */
-DL MOV D0BR.0, #0
- LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUB_S
- AND D1Ar1, D1Ar1, #(_TBIECH_DSPRAM_DUB_BITS >> _TBIECH_DSPRAM_DUB_S)
- SUB TXRPT, D1Ar1, #1
-$L2:
-DL MOV D0Re0, [D0BR.0++]
-DL MOV D0Ar6, [D0BR.0++]
-DL MOV D0Ar4, [D0BR.0++]
-DL MOV D0.5, [D0BR.0++]
- MSETL [A0.3++], D0Re0, D0Ar6, D0Ar4, D0.5
-
- BR $L2
-
- GETL D0.5, D1.5, [--A0StP]
- MOV PC, D1RtP
-
- .size ___TBIDspramSaveB,.-___TBIDspramSaveB
-
-/*
- * void *__TBIDspramRestoreA( short DspramSizes, void *pExt )
- */
- .balign 4
- .global ___TBIDspramRestoreA
- .type ___TBIDspramRestoreA,function
-___TBIDspramRestoreA:
-
- SETL [A0StP++], D0.5, D1.5
- MOV A0.3, D0Ar2
-
- /* D1Ar1 - Dspram Sizes
- * A0.3 - Pointer to buffer
- */
-
- /* Restore the specified amount of dspram DUA */
-DL MOV D0AW.0, #0
- LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUA_S
- AND D1Ar1, D1Ar1, #(_TBIECH_DSPRAM_DUA_BITS >> _TBIECH_DSPRAM_DUA_S)
- SUB TXRPT, D1Ar1, #1
-$L3:
- MGETL D0Re0, D0Ar6, D0Ar4, D0.5, [A0.3++]
-DL MOV [D0AW.0++], D0Re0
-DL MOV [D0AW.0++], D0Ar6
-DL MOV [D0AW.0++], D0Ar4
-DL MOV [D0AW.0++], D0.5
-
- BR $L3
-
- GETL D0.5, D1.5, [--A0StP]
- MOV PC, D1RtP
-
- .size ___TBIDspramRestoreA,.-___TBIDspramRestoreA
-
-/*
- * void *__TBIDspramRestoreB( short DspramSizes, void *pExt )
- */
- .balign 4
- .global ___TBIDspramRestoreB
- .type ___TBIDspramRestoreB,function
-___TBIDspramRestoreB:
-
- SETL [A0StP++], D0.5, D1.5
- MOV A0.3, D0Ar2
-
- /* D1Ar1 - Dspram Sizes
- * A0.3 - Pointer to buffer
- */
-
- /* Restore the specified amount of dspram DUA */
-DL MOV D0BW.0, #0
- LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUB_S
- AND D1Ar1, D1Ar1, #(_TBIECH_DSPRAM_DUB_BITS >> _TBIECH_DSPRAM_DUB_S)
- SUB TXRPT, D1Ar1, #1
-$L4:
- MGETL D0Re0, D0Ar6, D0Ar4, D0.5, [A0.3++]
-DL MOV [D0BW.0++], D0Re0
-DL MOV [D0BW.0++], D0Ar6
-DL MOV [D0BW.0++], D0Ar4
-DL MOV [D0BW.0++], D0.5
-
- BR $L4
-
- GETL D0.5, D1.5, [--A0StP]
- MOV PC, D1RtP
-
- .size ___TBIDspramRestoreB,.-___TBIDspramRestoreB
-
-/*
- * End of tbidspram.S
- */
diff --git a/arch/metag/tbx/tbilogf.S b/arch/metag/tbx/tbilogf.S
deleted file mode 100644
index 4a34d80657db..000000000000
--- a/arch/metag/tbx/tbilogf.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * tbilogf.S
- *
- * Copyright (C) 2001, 2002, 2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Defines __TBILogF trap code for debugging messages and __TBICont for debug
- * assert to be implemented on.
- */
-
- .file "tbilogf.S"
-
-/*
- * Perform console printf using external debugger or host support
- */
- .text
- .balign 4
- .global ___TBILogF
- .type ___TBILogF,function
-___TBILogF:
- MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2
- SWITCH #0xC10020
- MOV D0Re0,#0
- SUB A0StP,A0StP,#24
- MOV PC,D1RtP
- .size ___TBILogF,.-___TBILogF
-
-/*
- * Perform wait for continue under control of the debugger
- */
- .text
- .balign 4
- .global ___TBICont
- .type ___TBICont,function
-___TBICont:
- MOV D0Ar6,#1
- MSETL [A0StP],D0Ar6,D0Ar4,D0Ar2
- SWITCH #0xC30006 /* Returns if we are to continue */
- SUB A0StP,A0StP,#(8*3)
- MOV PC,D1RtP /* Return */
- .size ___TBICont,.-___TBICont
-
-/*
- * End of tbilogf.S
- */
diff --git a/arch/metag/tbx/tbipcx.S b/arch/metag/tbx/tbipcx.S
deleted file mode 100644
index 163c79ac913b..000000000000
--- a/arch/metag/tbx/tbipcx.S
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * tbipcx.S
- *
- * Copyright (C) 2001, 2002, 2007, 2009, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Asyncronous trigger handling including exceptions
- */
-
- .file "tbipcx.S"
-#include <asm/metag_regs.h>
-#include <asm/tbx.h>
-
-/* BEGIN HACK */
-/* define these for now while doing initial conversion to GAS
- will fix properly later */
-
-/* Signal identifiers always have the TBID_SIGNAL_BIT set and contain the
- following related bit-fields */
-#define TBID_SIGNUM_S 2
-
-/* END HACK */
-
-#ifdef METAC_1_0
-/* Ax.4 is saved in TBICTX */
-#define A0_4 ,A0.4
-#else
-/* Ax.4 is NOT saved in TBICTX */
-#define A0_4
-#endif
-
-/* Size of the TBICTX structure */
-#define TBICTX_BYTES ((TBICTX_AX_REGS*8)+TBICTX_AX)
-
-#ifdef METAC_1_1
-#ifndef BOOTROM
-#ifndef SPECIAL_BUILD
-/* Jump straight into the boot ROM version of this code */
-#define CODE_USES_BOOTROM
-#endif
-#endif
-#endif
-
-/* Define space needed for CATCH buffer state in traditional units */
-#define CATCH_ENTRIES 5
-#define CATCH_ENTRY_BYTES 16
-
-#ifndef CODE_USES_BOOTROM
-#define A0GblIStP A0.15 /* PTBICTX for current thread in PRIV system */
-#define A1GblIGbP A1.15 /* Interrupt A1GbP value in PRIV system */
-#endif
-
-/*
- * TBIRES __TBIASyncTrigger( TBIRES State )
- */
- .text
- .balign 4
- .global ___TBIASyncTrigger
- .type ___TBIASyncTrigger,function
-___TBIASyncTrigger:
-#ifdef CODE_USES_BOOTROM
- MOVT D0Re0,#HI(LINCORE_BASE)
- JUMP D0Re0,#0xA0
-#else
- MOV D0FrT,A0FrP /* Boing entry sequence */
- ADD A0FrP,A0StP,#0
- SETL [A0StP++],D0FrT,D1RtP
- MOV D0Re0,PCX /* Check for repeat call */
- MOVT D0FrT,#HI(___TBIBoingRTI+4)
- ADD D0FrT,D0FrT,#LO(___TBIBoingRTI+4)
- CMP D0Re0,D0FrT
- BEQ ___TBIBoingExit /* Already set up - come out */
- ADD D1Ar1,D1Ar1,#7 /* PRIV system stack here */
- MOV A0.2,A0StP /* else push context here */
- MOVS D0Re0,D0Ar2 /* Return in user mode? */
- ANDMB D1Ar1,D1Ar1,#0xfff8 /* align priv stack to 64-bit */
- MOV D1Re0,D1Ar1 /* and set result to arg */
- MOVMI A0.2,D1Ar1 /* use priv stack if PRIV set */
-/*
- * Generate an initial TBICTX to return to our own current call context
- */
- MOVT D1Ar5,#HI(___TBIBoingExit) /* Go here to return */
- ADD D1Ar5,D1Ar5,#LO(___TBIBoingExit)
- ADD A0.3,A0.2,#TBICTX_DX /* DX Save area */
- ANDT D0Ar2,D0Ar2,#TBICTX_PRIV_BIT /* Extract PRIV bit */
- MOVT D0Ar6,#TBICTX_SOFT_BIT /* Only soft thread state */
- ADD D0Ar6,D0Ar6,D0Ar2 /* Add in PRIV bit if requested */
- SETL [A0.2],D0Ar6,D1Ar5 /* Push header fields */
- ADD D0FrT,A0.2,#TBICTX_AX /* Address AX save area */
- MSETL [A0.3],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
- MOV D0Ar6,#0
- MOV D1Ar5,#0
- SETL [A0.3++],D0Ar6,D1Ar5 /* Zero CT register states */
- SETL [A0.3++],D0Ar6,D1Ar5
- MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
- MOV A0FrP,A0.2 /* Restore me! */
- B ___TBIResume
- .size ___TBIASyncTrigger,.-___TBIASyncTrigger
-
-/*
- * Optimised return to handler for META Core
- */
-___TBIBoingRTH:
- RTH /* Go to background level */
- MOVT A0.2, #HI($Lpcx_target)
- ADD A0.2,A0.2,#LO($Lpcx_target)
- MOV PCX,A0.2 /* Setup PCX for interrupts */
- MOV PC,D1Re0 /* Jump to handler */
-/*
- * This is where the code below needs to jump to wait for outermost interrupt
- * event in a non-privilege mode system (single shared interrupt stack).
- */
-___TBIBoingPCX:
- MGETL A0StP,A0FrP,A0.2,A0.3 A0_4,[D1Re0] /* Restore AX regs */
- MOV TXSTATUS,D0Re0 /* Restore flags */
- GETL D0Re0,D1Re0,[D1Re0+#TBICTX_DX-TBICTX_BYTES]
-___TBIBoingRTI:
- RTI /* Wait for interrupt */
-$Lpcx_target:
-/*
- * Save initial interrupt state on current stack
- */
- SETL [A0StP+#TBICTX_DX],D0Re0,D1Re0 /* Save key registers */
- ADD D1Re0,A0StP,#TBICTX_AX /* Address AX save area */
- MOV D0Re0,TXSTATUS /* Read TXSTATUS into D0Re0 */
- MOV TXSTATUS,#0 /* Clear TXSTATUS */
- MSETL [D1Re0],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX critical regs */
-/*
- * Register state at this point is-
- *
- * D0Re0 - Old TXSTATUS with PRIV and CBUF bits set if appropriate
- * A0StP - Is call stack frame and base of TBICTX being generated
- * A1GbP - Is valid static access link
- */
-___TBIBoing:
- LOCK0 /* Make sure we have no locks! */
- ADD A1.2,A0StP,#TBICTX_DX+(8*1) /* Address DX.1 save area */
- MOV A0FrP,A0StP /* Setup frame pointer */
- MSETL [A1.2],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
- MOV D0Ar4,TXRPT /* Save critical CT regs */
- MOV D1Ar3,TXBPOBITS
- MOV D1Ar1,TXDIVTIME /* Calc catch buffer pSrc */
- MOV D0Ar2,TXMODE
- MOV TXMODE,#0 /* Clear TXMODE */
-#ifdef TXDIVTIME_RPDIRTY_BIT
- TSTT D1Ar1,#HI(TXDIVTIME_RPDIRTY_BIT)/* NZ = RPDIRTY */
- MOVT D0Ar6,#TBICTX_CBRP_BIT
- ORNZ D0Re0,D0Re0,D0Ar6 /* Set CBRP if RPDIRTY set */
-#endif
- MSETL [A1.2],D0Ar4,D0Ar2 /* Save CT regs state */
- MOV D0Ar2,D0Re0 /* Copy TXSTATUS */
- ANDMT D0Ar2,D0Ar2,#TBICTX_CBUF_BIT+TBICTX_CBRP_BIT
-#ifdef TBI_1_4
- MOVT D1Ar1,#TBICTX_FPAC_BIT /* Copy FPActive into FPAC */
- TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
- ORNZ D0Ar2,D0Ar2,D1Ar1
-#endif
- MOV D1Ar1,PCX /* Read CurrPC */
- ORT D0Ar2,D0Ar2,#TBICTX_CRIT_BIT /* SaveMask + CRIT bit */
- SETL [A0FrP+#TBICTX_Flags],D0Ar2,D1Ar1 /* Set pCtx header fields */
-/*
- * Completed context save, now we need to make a call to an interrupt handler
- *
- * D0Re0 - holds PRIV, WAIT, CBUF flags, HALT reason if appropriate
- * A0FrP - interrupt stack frame and base of TBICTX being generated
- * A0StP - same as A0FrP
- */
-___TBIBoingWait:
- /* Reserve space for TBICTX and CBUF */
- ADD A0StP,A0StP,#TBICTX_BYTES+(CATCH_ENTRY_BYTES*CATCH_ENTRIES)
- MOV D0Ar4,TXSTATI /* Read the Triggers data */
- MOV D1Ar3,TXDIVTIME /* Read IRQEnc bits */
- MOV D0Ar2,D0Re0 /* Copy PRIV and WAIT flags */
- ANDT D0Ar2,D0Ar2,#TBICTX_PRIV_BIT+TBICTX_WAIT_BIT+TBICTX_CBUF_BIT
-#ifdef TBI_1_4
- MOVT D1Ar5,#TBICTX_FPAC_BIT /* Copy FPActive into FPAC */
- TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
- ORNZ D0Ar2,D0Ar2,D1Ar5
-#endif
- ANDT D1Ar3,D1Ar3,#HI(TXDIVTIME_IRQENC_BITS)
- LSR D1Ar3,D1Ar3,#TXDIVTIME_IRQENC_S
- AND TXSTATI,D0Ar4,#TXSTATI_BGNDHALT_BIT/* Ack any HALT seen */
- ANDS D0Ar4,D0Ar4,#0xFFFF-TXSTATI_BGNDHALT_BIT /* Only seen HALT? */
- ORT D0Ar2,D0Ar2,#TBICTX_CRIT_BIT /* Set CRIT */
-#ifndef BOOTROM
- MOVT A1LbP,#HI(___pTBIs)
- ADD A1LbP,A1LbP,#LO(___pTBIs)
- GETL D1Ar5,D0Ar6,[A1LbP] /* D0Ar6 = ___pTBIs[1] */
-#else
-/*
- * For BOOTROM support ___pTBIs must be allocated at offset 0 vs A1GbP
- */
- GETL D1Ar5,D0Ar6,[A1GbP] /* D0Ar6 = ___pTBIs[1] */
-#endif
- BZ ___TBIBoingHalt /* Yes: Service HALT */
-/*
- * Encode interrupt as signal vector, strip away same/lower TXMASKI bits
- */
- MOV D1Ar1,#1 /* Generate mask for this bit */
- MOV D0Re0,TXMASKI /* Get interrupt mask */
- LSL TXSTATI,D1Ar1,D1Ar3 /* Acknowledge trigger */
- AND TXMASKI,D0Re0,#TXSTATI_BGNDHALT_BIT /* Only allow HALTs */
- OR D0Ar2,D0Ar2,D0Re0 /* Set TBIRES.Sig.TrigMask */
- ADD D1Ar3,D1Ar3,#TBID_SIGNUM_TRT /* Offset into interrupt sigs */
- LSL D0Re0,D1Ar3,#TBID_SIGNUM_S /* Generate offset from SigNum */
-/*
- * This is a key moment we are about to call the handler, register state is
- * as follows-
- *
- * D0Re0 - Handler vector (SigNum<<TBID_SIGNUM_S)
- * D0Ar2 - TXMASKI:TBICTX_CRIT_BIT with optional CBUF and PRIV bits
- * D1Ar3 - SigNum
- * D0Ar4 - State read from TXSTATI
- * D1Ar5 - Inst for SWITCH trigger case only, otherwise undefined
- * D0Ar6 - pTBI
- */
-___TBIBoingVec:
- ADD D0Re0,D0Re0,#TBI_fnSigs /* Offset into signal table */
- GETD D1Re0,[D0Ar6+D0Re0] /* Get address for Handler */
-/*
- * Call handler at interrupt level, when it returns simply resume execution
- * of state indicated by D1Re0.
- */
- MOV D1Ar1,A0FrP /* Pass in pCtx */
- CALLR D1RtP,___TBIBoingRTH /* Use RTH to invoke handler */
-
-/*
- * Perform critical state restore and execute background thread.
- *
- * A0FrP - is pointer to TBICTX structure to resume
- * D0Re0 - contains additional TXMASKI triggers
- */
- .text
- .balign 4
-#ifdef BOOTROM
- .global ___TBIResume
-#endif
-___TBIResume:
-/*
- * New META IP method
- */
- RTH /* Go to interrupt level */
- MOV D0Ar4,TXMASKI /* Read TXMASKI */
- OR TXMASKI,D0Ar4,D0Re0 /* -Write-Modify TXMASKI */
- GETL D0Re0,D1Re0,[A0FrP+#TBICTX_Flags]/* Get Flags:SaveMask, CurrPC */
- MOV A0StP,A0FrP /* Position stack pointer */
- MOV D0Ar2,TXPOLLI /* Read pending triggers */
- MOV PCX,D1Re0 /* Set resumption PC */
- TST D0Ar2,#0xFFFF /* Any pending triggers? */
- BNZ ___TBIBoingWait /* Yes: Go for triggers */
- TSTT D0Re0,#TBICTX_WAIT_BIT /* Do we WAIT anyway? */
- BNZ ___TBIBoingWait /* Yes: Go for triggers */
- LSLS D1Ar5,D0Re0,#1 /* Test XCBF (MI) & PRIV (CS)? */
- ADD D1Re0,A0FrP,#TBICTX_CurrRPT /* Address CT save area */
- ADD A0StP,A0FrP,#TBICTX_DX+(8*1) /* Address DX.1 save area */
- MGETL A0.2,A0.3,[D1Re0] /* Get CT reg states */
- MOV D1Ar3,A1.3 /* Copy old TXDIVTIME */
- BPL ___TBIResCrit /* No: Skip logic */
- ADD D0Ar4,A0FrP,#TBICTX_BYTES /* Source is after TBICTX */
- ANDST D1Ar3,D1Ar3,#HI(TXDIVTIME_RPMASK_BITS)/* !Z if RPDIRTY */
- MGETL D0.5,D0.6,[D0Ar4] /* Read Catch state */
- MOV TXCATCH0,D0.5 /* Restore TXCATCHn */
- MOV TXCATCH1,D1.5
- MOV TXCATCH2,D0.6
- MOV TXCATCH3,D1.6
- BZ ___TBIResCrit
- MOV D0Ar2,#(1*8)
- LSRS D1Ar3,D1Ar3,#TXDIVTIME_RPMASK_S+1 /* 2nd RPMASK bit -> bit 0 */
- ADD RA,D0Ar4,#(0*8) /* Re-read read pipeline */
- ADDNZ RA,D0Ar4,D0Ar2 /* If Bit 0 set issue RA */
- LSRS D1Ar3,D1Ar3,#2 /* Bit 1 -> C, Bit 2 -> Bit 0 */
- ADD D0Ar2,D0Ar2,#8
- ADDCS RA,D0Ar4,D0Ar2 /* If C issue RA */
- ADD D0Ar2,D0Ar2,#8
- ADDNZ RA,D0Ar4,D0Ar2 /* If Bit 0 set issue RA */
- LSRS D1Ar3,D1Ar3,#2 /* Bit 1 -> C, Bit 2 -> Bit 0 */
- ADD D0Ar2,D0Ar2,#8
- ADDCS RA,D0Ar4,D0Ar2 /* If C issue RA */
- ADD D0Ar2,D0Ar2,#8
- ADDNZ RA,D0Ar4,D0Ar2 /* If Bit 0 set issue RA */
- MOV TXDIVTIME,A1.3 /* Set RPDIRTY again */
-___TBIResCrit:
- LSLS D1Ar5,D0Re0,#1 /* Test XCBF (MI) & PRIV (CS)? */
-#ifdef TBI_1_4
- ANDT D1Ar5,D1Ar5,#(TBICTX_FPAC_BIT*2)
- LSL D0Ar6,D1Ar5,#3 /* Convert FPAC into FPACTIVE */
-#endif
- ANDMT D0Re0,D0Re0,#TBICTX_CBUF_BIT /* Keep CBUF bit from SaveMask */
-#ifdef TBI_1_4
- OR D0Re0,D0Re0,D0Ar6 /* Combine FPACTIVE with others */
-#endif
- MGETL D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7,[A0StP] /* Restore DX */
- MOV TXRPT,A0.2 /* Restore CT regs */
- MOV TXBPOBITS,A1.2
- MOV TXMODE,A0.3
- BCC ___TBIBoingPCX /* Do non-PRIV wait! */
- MOV A1GblIGbP,A1GbP /* Save A1GbP too */
- MGETL A0StP,A0FrP,A0.2,A0.3 A0_4,[D1Re0] /* Restore AX regs */
-/*
- * Wait for the first interrupt/exception trigger in a privilege mode system
- * (interrupt stack area for current TASK to be pointed to by A0GblIStP
- * or per_cpu__stack_save[hwthread_id]).
- */
- MOV TXSTATUS,D0Re0 /* Restore flags */
- MOV D0Re0,TXPRIVEXT /* Set TXPRIVEXT_TXTOGGLEI_BIT */
- SUB D1Re0,D1Re0,#TBICTX_BYTES /* TBICTX is top of int stack */
-#ifdef TBX_PERCPU_SP_SAVE
- SWAP D1Ar3,A1GbP
- MOV D1Ar3,TXENABLE /* Which thread are we? */
- AND D1Ar3,D1Ar3,#TXENABLE_THREAD_BITS
- LSR D1Ar3,D1Ar3,#TXENABLE_THREAD_S-2
- ADDT D1Ar3,D1Ar3,#HI(_per_cpu__stack_save)
- ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
- SETD [D1Ar3],D1Re0
- SWAP D1Ar3,A1GbP
-#else
- MOV A0GblIStP, D1Re0
-#endif
- OR D0Re0,D0Re0,#TXPRIVEXT_TXTOGGLEI_BIT
- MOV TXPRIVEXT,D0Re0 /* Cannot set TXPRIVEXT if !priv */
- GETL D0Re0,D1Re0,[D1Re0+#TBICTX_DX]
- RTI /* Wait for interrupt */
-/*
- * Save initial interrupt state on A0GblIStP, switch to A0GblIStP if
- * BOOTROM code, save and switch to [A1GbP] otherwise.
- */
-___TBIBoingPCXP:
-#ifdef TBX_PERCPU_SP_SAVE
- SWAP D1Ar3,A1GbP /* Get PRIV stack base */
- MOV D1Ar3,TXENABLE /* Which thread are we? */
- AND D1Ar3,D1Ar3,#TXENABLE_THREAD_BITS
- LSR D1Ar3,D1Ar3,#TXENABLE_THREAD_S-2
- ADDT D1Ar3,D1Ar3,#HI(_per_cpu__stack_save)
- ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
- GETD D1Ar3,[D1Ar3]
-#else
- SWAP D1Ar3,A0GblIStP /* Get PRIV stack base */
-#endif
- SETL [D1Ar3+#TBICTX_DX],D0Re0,D1Re0 /* Save key registers */
- MOV D0Re0,TXPRIVEXT /* Clear TXPRIVEXT_TXTOGGLEI_BIT */
- ADD D1Re0,D1Ar3,#TBICTX_AX /* Address AX save area */
- ANDMB D0Re0,D0Re0,#0xFFFF-TXPRIVEXT_TXTOGGLEI_BIT
- MOV TXPRIVEXT,D0Re0 /* Cannot set TXPRIVEXT if !priv */
- MOV D0Re0,TXSTATUS /* Read TXSTATUS into D0Re0 */
- MOV TXSTATUS,#0 /* Clear TXSTATUS */
- MSETL [D1Re0],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX critical regs */
- MOV A0StP,D1Ar3 /* Switch stacks */
-#ifdef TBX_PERCPU_SP_SAVE
- MOV D1Ar3,A1GbP /* Get D1Ar2 back */
-#else
- MOV D1Ar3,A0GblIStP /* Get D1Ar2 back */
-#endif
- ORT D0Re0,D0Re0,#TBICTX_PRIV_BIT /* Add PRIV to TXSTATUS */
- MOV A1GbP,A1GblIGbP /* Restore A1GbP */
- B ___TBIBoing /* Enter common handler code */
-/*
- * At this point we know it's a background HALT case we are handling.
- * The restored TXSTATUS always needs to have zero in the reason bits.
- */
-___TBIBoingHalt:
- MOV D0Ar4,TXMASKI /* Get interrupt mask */
- ANDST D0Re0,D0Re0,#HI(TXSTATUS_MAJOR_HALT_BITS+TXSTATUS_MEM_FAULT_BITS)
- AND TXMASKI,D0Ar4,#TXSTATI_BGNDHALT_BIT /* Only allow HALTs */
- AND D0Ar4,D0Ar4,#0xFFFF-TXSTATI_BGNDHALT_BIT /* What ints are off? */
- OR D0Ar2,D0Ar2,D0Ar4 /* Set TBIRES.Sig.TrigMask */
- MOV D0Ar4,#TXSTATI_BGNDHALT_BIT /* This was the trigger state */
- LSR D1Ar3,D0Re0,#TXSTATUS_MAJOR_HALT_S
- MOV D0Re0,#TBID_SIGNUM_XXF<<TBID_SIGNUM_S
- BNZ ___TBIBoingVec /* Jump to XXF exception handler */
-/*
- * Only the SWITCH cases are left, PCX must be valid
- */
-#ifdef TBI_1_4
- MOV D1Ar5,TXPRIVEXT
- TST D1Ar5,#TXPRIVEXT_MINIMON_BIT
- LSR D1Ar3,D1Ar1,#1 /* Shift needed for MINIM paths (fill stall) */
- BZ $Lmeta /* If META only, skip */
- TSTT D1Ar1,#HI(0x00800000)
- ANDMT D1Ar3,D1Ar3,#HI(0x007FFFFF >> 1)/* Shifted mask for large MINIM */
- ANDT D1Ar1,D1Ar1,#HI(0xFFE00000) /* Static mask for small MINIM */
- BZ $Llarge_minim /* If large MINIM */
-$Lsmall_minim:
- TSTT D1Ar3,#HI(0x00100000 >> 1)
- ANDMT D1Ar3,D1Ar3,#HI(0x001FFFFF >> 1)/* Correct shifted mask for large MINIM */
- ADDZ D1Ar1,D1Ar1,D1Ar3 /* If META rgn, add twice to undo LSR #1 */
- B $Lrecombine
-$Llarge_minim:
- ANDST D1Ar1,D1Ar1,#HI(0xFF800000) /* Correct static mask for small MINIM */
- /* Z=0 (Cannot place code at NULL) */
-$Lrecombine:
- ADD D1Ar1,D1Ar1,D1Ar3 /* Combine static and shifted parts */
-$Lmeta:
- GETW D1Ar5,[D1Ar1++] /* META: lo-16, MINIM: lo-16 (all-16 if short) */
- GETW D1Ar3,[D1Ar1] /* META: hi-16, MINIM: hi-16 (only if long) */
- MOV D1Re0,D1Ar5
- XOR D1Re0,D1Re0,#0x4000
- LSLSNZ D1Re0,D1Re0,#(32-14) /* MINIM: If long C=0, if short C=1 */
- LSLCC D1Ar3,D1Ar3,#16 /* META/MINIM long: Move hi-16 up */
- LSLCS D1Ar3,D1Ar5,#16 /* MINIM short: Dup all-16 */
- ADD D1Ar5,D1Ar5,D1Ar3 /* ALL: Combine both 16-bit parts */
-#else
- GETD D1Ar5,[D1Ar1] /* Read instruction for switch */
-#endif
- LSR D1Ar3,D1Ar5,#22 /* Convert into signal number */
- AND D1Ar3,D1Ar3,#TBID_SIGNUM_SW3-TBID_SIGNUM_SW0
- LSL D0Re0,D1Ar3,#TBID_SIGNUM_S /* Generate offset from SigNum */
- B ___TBIBoingVec /* Jump to switch handler */
-/*
- * Exit from TBIASyncTrigger call
- */
-___TBIBoingExit:
- GETL D0FrT,D1RtP,[A0FrP++] /* Restore state from frame */
- SUB A0StP,A0FrP,#8 /* Unwind stack */
- MOV A0FrP,D0FrT /* Last memory read completes */
- MOV PC,D1RtP /* Return to caller */
-#endif /* ifdef CODE_USES_BOOTROM */
- .size ___TBIResume,.-___TBIResume
-
-#ifndef BOOTROM
-/*
- * void __TBIASyncResume( TBIRES State )
- */
- .text
- .balign 4
- .global ___TBIASyncResume
- .type ___TBIASyncResume,function
-___TBIASyncResume:
-/*
- * Perform CRIT|SOFT state restore and execute background thread.
- */
- MOV D1Ar3,D1Ar1 /* Restore this context */
- MOV D0Re0,D0Ar2 /* Carry in additional triggers */
- /* Reserve space for TBICTX */
- ADD D1Ar3,D1Ar3,#TBICTX_BYTES+(CATCH_ENTRY_BYTES*CATCH_ENTRIES)
- MOV A0StP,D1Ar3 /* Enter with protection of */
- MOV A0FrP,D1Ar1 /* TBICTX on our stack */
-#ifdef CODE_USES_BOOTROM
- MOVT D1Ar1,#HI(LINCORE_BASE)
- JUMP D1Ar1,#0xA4
-#else
- B ___TBIResume
-#endif
- .size ___TBIASyncResume,.-___TBIASyncResume
-#endif /* ifndef BOOTROM */
-
-/*
- * End of tbipcx.S
- */
diff --git a/arch/metag/tbx/tbiroot.S b/arch/metag/tbx/tbiroot.S
deleted file mode 100644
index 7d84daf1340b..000000000000
--- a/arch/metag/tbx/tbiroot.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * tbiroot.S
- *
- * Copyright (C) 2001, 2002, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Module that creates and via ___TBI function returns a TBI Root Block for
- * interrupt and background processing on the current thread.
- */
-
- .file "tbiroot.S"
-#include <asm/metag_regs.h>
-
-/*
- * Get data structures and defines from the TBI C header
- */
-#include <asm/tbx.h>
-
-
-/* If signals need to be exchanged we must create a TBI Root Block */
-
- .data
- .balign 8
- .global ___pTBIs
- .type ___pTBIs,object
-___pTBIs:
- .long 0 /* Bgnd+Int root block ptrs */
- .long 0
- .size ___pTBIs,.-___pTBIs
-
-
-/*
- * Return ___pTBIs value specific to execution level with promotion/demotion
- *
- * Register Usage: D1Ar1 is Id, D0Re0 is the primary result
- * D1Re0 is secondary result (___pTBIs for other exec level)
- */
- .text
- .balign 4
- .global ___TBI
- .type ___TBI,function
-___TBI:
- TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Bgnd or Int level? */
- MOVT A1LbP,#HI(___pTBIs)
- ADD A1LbP,A1LbP,#LO(___pTBIs)
- GETL D0Re0,D1Re0,[A1LbP] /* Base of root block table */
- SWAPNZ D0Re0,D1Re0 /* Swap if asked */
- MOV PC,D1RtP
- .size ___TBI,.-___TBI
-
-
-/*
- * Return identifier of the current thread in TBI segment or signal format with
- * secondary mask to indicate privilege and interrupt level of thread
- */
- .text
- .balign 4
- .global ___TBIThrdPrivId
- .type ___TBIThrdPrivId,function
-___TBIThrdPrivId:
- .global ___TBIThreadId
- .type ___TBIThreadId,function
-___TBIThreadId:
-#ifndef METAC_0_1
- MOV D1Re0,TXSTATUS /* Are we privileged or int? */
- MOV D0Re0,TXENABLE /* Which thread are we? */
-/* Disable privilege adaption for now */
- ANDT D1Re0,D1Re0,#HI(TXSTATUS_ISTAT_BIT) /* +TXSTATUS_PSTAT_BIT) */
- LSL D1Re0,D1Re0,#TBID_ISTAT_S-TXSTATUS_ISTAT_S
- AND D0Re0,D0Re0,#TXENABLE_THREAD_BITS
- LSL D0Re0,D0Re0,#TBID_THREAD_S-TXENABLE_THREAD_S
-#else
-/* Thread 0 only */
- XOR D0Re0,D0Re0,D0Re0
- XOR D1Re0,D1Re0,D1Re0
-#endif
- MOV PC,D1RtP /* Return */
- .size ___TBIThrdPrivId,.-___TBIThrdPrivId
- .size ___TBIThreadId,.-___TBIThreadId
-
-
-/*
- * End of tbiroot.S
- */
diff --git a/arch/metag/tbx/tbisoft.S b/arch/metag/tbx/tbisoft.S
deleted file mode 100644
index b04f50df8d91..000000000000
--- a/arch/metag/tbx/tbisoft.S
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * tbisoft.S
- *
- * Copyright (C) 2001, 2002, 2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * Support for soft threads and soft context switches
- */
-
- .file "tbisoft.S"
-
-#include <asm/tbx.h>
-
-#ifdef METAC_1_0
-/* Ax.4 is saved in TBICTX */
-#define A0_4 ,A0.4
-#define D0_5 ,D0.5
-#else
-/* Ax.4 is NOT saved in TBICTX */
-#define A0_4
-#define D0_5
-#endif
-
-/* Size of the TBICTX structure */
-#define TBICTX_BYTES ((TBICTX_AX_REGS*8)+TBICTX_AX)
-
- .text
- .balign 4
- .global ___TBISwitchTail
- .type ___TBISwitchTail,function
-___TBISwitchTail:
- B $LSwitchTail
- .size ___TBISwitchTail,.-___TBISwitchTail
-
-/*
- * TBIRES __TBIJumpX( TBIX64 ArgsA, PTBICTX *rpSaveCtx, int TrigsMask,
- * void (*fnMain)(), void *pStack );
- *
- * This is a combination of __TBISwitch and __TBIJump with the context of
- * the calling thread being saved in the rpSaveCtx location with a drop-thru
- * effect into the __TBIJump logic. ArgsB passes via __TBIJump to the
- * routine eventually invoked will reflect the rpSaveCtx value specified.
- */
- .text
- .balign 4
- .global ___TBIJumpX
- .type ___TBIJumpX,function
-___TBIJumpX:
- CMP D1RtP,#-1
- B $LSwitchStart
- .size ___TBIJumpX,.-___TBIJumpX
-
-/*
- * TBIRES __TBISwitch( TBIRES Switch, PTBICTX *rpSaveCtx )
- *
- * Software synchronous context switch between soft threads, save only the
- * registers which are actually valid on call entry.
- *
- * A0FrP, D0RtP, D0.5, D0.6, D0.7 - Saved on stack
- * A1GbP is global to all soft threads so not virtualised
- * A0StP is then saved as the base of the TBICTX of the thread
- *
- */
- .text
- .balign 4
- .global ___TBISwitch
- .type ___TBISwitch,function
-___TBISwitch:
- XORS D0Re0,D0Re0,D0Re0 /* Set ZERO flag */
-$LSwitchStart:
- MOV D0FrT,A0FrP /* Boing entry sequence */
- ADD A0FrP,A0StP,#0
- SETL [A0StP+#8++],D0FrT,D1RtP
-/*
- * Save current frame state - we save all regs because we don't want
- * uninitialised crap in the TBICTX structure that the asynchronous resumption
- * of a thread will restore.
- */
- MOVT D1Re0,#HI($LSwitchExit) /* ASync resume point here */
- ADD D1Re0,D1Re0,#LO($LSwitchExit)
- SETD [D1Ar3],A0StP /* Record pCtx of this thread */
- MOVT D0Re0,#TBICTX_SOFT_BIT /* Only soft thread state */
- SETL [A0StP++],D0Re0,D1Re0 /* Push header fields */
- ADD D0FrT,A0StP,#TBICTX_AX-TBICTX_DX /* Address AX save area */
- MOV D0Re0,#0 /* Setup 0:0 result for ASync */
- MOV D1Re0,#0 /* resume of the thread */
- MSETL [A0StP],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
- SETL [A0StP++],D0Re0,D1Re0 /* Zero CurrRPT, CurrBPOBITS, */
- SETL [A0StP++],D0Re0,D1Re0 /* Zero CurrMODE, CurrDIVTIME */
- ADD A0StP,A0StP,#(TBICTX_AX_REGS*8) /* Reserve AX save space */
- MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
- BNZ ___TBIJump
-/*
- * NextThread MUST be in TBICTX_SOFT_BIT state!
- */
-$LSwitchTail:
- MOV D0Re0,D0Ar2 /* Result from args */
- MOV D1Re0,D1Ar1
- ADD D1RtP,D1Ar1,#TBICTX_AX
- MGETL A0StP,A0FrP,[D1RtP] /* Get frame values */
-$LSwitchCmn:
- ADD A0.2,D1Ar1,#TBICTX_DX+(8*5)
- MGETL D0.5,D0.6,D0.7,[A0.2] /* Get caller-saved DX regs */
-$LSwitchExit:
- GETL D0FrT,D1RtP,[A0FrP++] /* Restore state from frame */
- SUB A0StP,A0FrP,#8 /* Unwind stack */
- MOV A0FrP,D0FrT /* Last memory read completes */
- MOV PC,D1RtP /* Return to caller */
- .size ___TBISwitch,.-___TBISwitch
-
-/*
- * void __TBISyncResume( TBIRES State, int TrigMask );
- *
- * This routine causes the TBICTX structure specified in State.Sig.pCtx to
- * be restored. This implies that execution will not return to the caller.
- * The State.Sig.TrigMask field will be ored into TXMASKI during the
- * context switch such that any immediately occurring interrupts occur in
- * the context of the newly specified task. The State.Sig.SaveMask parameter
- * is ignored.
- */
- .text
- .balign 4
- .global ___TBISyncResume
- .type ___TBISyncResume,function
-___TBISyncResume:
- MOV D0Re0,D0Ar2 /* Result from args */
- MOV D1Re0,D1Ar1
- XOR D1Ar5,D1Ar5,D1Ar5 /* D1Ar5 = 0 */
- ADD D1RtP,D1Ar1,#TBICTX_AX
- SWAP D1Ar5,TXMASKI /* D1Ar5 <-> TXMASKI */
- MGETL A0StP,A0FrP,[D1RtP] /* Get frame values */
- OR TXMASKI,D1Ar5,D1Ar3 /* New TXMASKI */
- B $LSwitchCmn
- .size ___TBISyncResume,.-___TBISyncResume
-
-/*
- * void __TBIJump( TBIX64 ArgsA, TBIX32 ArgsB, int TrigsMask,
- * void (*fnMain)(), void *pStack );
- *
- * Jump directly to a new routine on an arbitrary stack with arbitrary args
- * oring bits back into TXMASKI on route.
- */
- .text
- .balign 4
- .global ___TBIJump
- .type ___TBIJump,function
-___TBIJump:
- XOR D0Re0,D0Re0,D0Re0 /* D0Re0 = 0 */
- MOV A0StP,D0Ar6 /* Stack = Frame */
- SWAP D0Re0,TXMASKI /* D0Re0 <-> TXMASKI */
- MOV A0FrP,D0Ar6
- MOVT A1LbP,#HI(__exit)
- ADD A1LbP,A1LbP,#LO(__exit)
- MOV D1RtP,A1LbP /* D1RtP = __exit */
- OR TXMASKI,D0Re0,D0Ar4 /* New TXMASKI */
- MOV PC,D1Ar5 /* Jump to fnMain */
- .size ___TBIJump,.-___TBIJump
-
-/*
- * PTBICTX __TBISwitchInit( void *pStack, int (*fnMain)(),
- * .... 4 extra 32-bit args .... );
- *
- * Generate a new soft thread context ready for it's first outing.
- *
- * D1Ar1 - Region of memory to be used as the new soft thread stack
- * D0Ar2 - Main line routine for new soft thread
- * D1Ar3, D0Ar4, D1Ar5, D0Ar6 - arguments to be passed on stack
- * The routine returns the initial PTBICTX value for the new thread
- */
- .text
- .balign 4
- .global ___TBISwitchInit
- .type ___TBISwitchInit,function
-___TBISwitchInit:
- MOV D0FrT,A0FrP /* Need save return point */
- ADD A0FrP,A0StP,#0
- SETL [A0StP++],D0FrT,D1RtP /* Save return to caller */
- MOVT A1LbP,#HI(__exit)
- ADD A1LbP,A1LbP,#LO(__exit)
- MOV D1RtP,A1LbP /* Get address of __exit */
- ADD D1Ar1,D1Ar1,#7 /* Align stack to 64-bits */
- ANDMB D1Ar1,D1Ar1,#0xfff8 /* by rounding base up */
- MOV A0.2,D1Ar1 /* A0.2 is new stack */
- MOV D0FrT,D1Ar1 /* Initial puesdo-frame pointer */
- SETL [A0.2++],D0FrT,D1RtP /* Save return to __exit */
- MOV D1RtP,D0Ar2
- SETL [A0.2++],D0FrT,D1RtP /* Save return to fnMain */
- ADD D0FrT,D0FrT,#8 /* Advance puesdo-frame pointer */
- MSETL [A0.2],D0Ar6,D0Ar4 /* Save extra initial args */
- MOVT D1RtP,#HI(___TBIStart) /* Start up code for new stack */
- ADD D1RtP,D1RtP,#LO(___TBIStart)
- SETL [A0.2++],D0FrT,D1RtP /* Save return to ___TBIStart */
- ADD D0FrT,D0FrT,#(8*3) /* Advance puesdo-frame pointer */
- MOV D0Re0,A0.2 /* Return pCtx for new thread */
- MOV D1Re0,#0 /* pCtx:0 is default Arg1:Arg2 */
-/*
- * Generate initial TBICTX state
- */
- MOVT D1Ar1,#HI($LSwitchExit) /* Async restore code */
- ADD D1Ar1,D1Ar1,#LO($LSwitchExit)
- MOVT D0Ar2,#TBICTX_SOFT_BIT /* Only soft thread state */
- ADD D0Ar6,A0.2,#TBICTX_BYTES /* New A0StP */
- MOV D1Ar5,A1GbP /* Same A1GbP */
- MOV D0Ar4,D0FrT /* Initial A0FrP */
- MOV D1Ar3,A1LbP /* Same A1LbP */
- SETL [A0.2++],D0Ar2,D1Ar1 /* Set header fields */
- MSETL [A0.2],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
- MOV D0Ar2,#0 /* Zero values */
- MOV D1Ar1,#0
- SETL [A0.2++],D0Ar2,D1Ar1 /* Zero CurrRPT, CurrBPOBITS, */
- SETL [A0.2++],D0Ar2,D1Ar1 /* CurrMODE, and pCurrCBuf */
- MSETL [A0.2],D0Ar6,D0Ar4,D0Ar2,D0FrT D0_5 /* Set DX and then AX regs */
- B $LSwitchExit /* All done! */
- .size ___TBISwitchInit,.-___TBISwitchInit
-
- .text
- .balign 4
- .global ___TBIStart
- .type ___TBIStart,function
-___TBIStart:
- MOV D1Ar1,D1Re0 /* Pass TBIRES args to call */
- MOV D0Ar2,D0Re0
- MGETL D0Re0,D0Ar6,D0Ar4,[A0FrP] /* Get hidden args */
- SUB A0StP,A0FrP,#(8*3) /* Entry stack pointer */
- MOV A0FrP,D0Re0 /* Entry frame pointer */
- MOVT A1LbP,#HI(__exit)
- ADD A1LbP,A1LbP,#LO(__exit)
- MOV D1RtP,A1LbP /* D1RtP = __exit */
- MOV PC,D1Re0 /* Jump into fnMain */
- .size ___TBIStart,.-___TBIStart
-
-/*
- * End of tbisoft.S
- */
diff --git a/arch/metag/tbx/tbistring.c b/arch/metag/tbx/tbistring.c
deleted file mode 100644
index f90cd0822065..000000000000
--- a/arch/metag/tbx/tbistring.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * tbistring.c
- *
- * Copyright (C) 2001, 2002, 2003, 2005, 2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * String table functions provided as part of the thread binary interface for
- * Meta processors
- */
-
-#include <linux/export.h>
-#include <linux/string.h>
-#include <asm/tbx.h>
-
-/*
- * There are not any functions to modify the string table currently, if these
- * are required at some later point I suggest having a seperate module and
- * ensuring that creating new entries does not interfere with reading old
- * entries in any way.
- */
-
-const TBISTR *__TBIFindStr(const TBISTR *start,
- const char *str, int match_len)
-{
- const TBISTR *search = start;
- bool exact = true;
- const TBISEG *seg;
-
- if (match_len < 0) {
- /* Make match_len always positive for the inner loop */
- match_len = -match_len;
- exact = false;
- } else {
- /*
- * Also support historic behaviour, which expected match_len to
- * include null terminator
- */
- if (match_len && str[match_len-1] == '\0')
- match_len--;
- }
-
- if (!search) {
- /* Find global string table segment */
- seg = __TBIFindSeg(NULL, TBID_SEG(TBID_THREAD_GLOBAL,
- TBID_SEGSCOPE_GLOBAL,
- TBID_SEGTYPE_STRING));
-
- if (!seg || seg->Bytes < sizeof(TBISTR))
- /* No string table! */
- return NULL;
-
- /* Start of string table */
- search = seg->pGAddr;
- }
-
- for (;;) {
- while (!search->Tag)
- /* Allow simple gaps which are just zero initialised */
- search = (const TBISTR *)((const char *)search + 8);
-
- if (search->Tag == METAG_TBI_STRE) {
- /* Reached the end of the table */
- search = NULL;
- break;
- }
-
- if ((search->Len >= match_len) &&
- (!exact || (search->Len == match_len + 1)) &&
- (search->Tag != METAG_TBI_STRG)) {
- /* Worth searching */
- if (!strncmp(str, (const char *)search->String,
- match_len))
- break;
- }
-
- /* Next entry */
- search = (const TBISTR *)((const char *)search + search->Bytes);
- }
-
- return search;
-}
-
-const void *__TBITransStr(const char *str, int len)
-{
- const TBISTR *search = NULL;
- const void *res = NULL;
-
- for (;;) {
- /* Search onwards */
- search = __TBIFindStr(search, str, len);
-
- /* No translation returns NULL */
- if (!search)
- break;
-
- /* Skip matching entries with no translation data */
- if (search->TransLen != METAG_TBI_STRX) {
- /* Calculate base of translation string */
- res = (const char *)search->String +
- ((search->Len + 7) & ~7);
- break;
- }
-
- /* Next entry */
- search = (const TBISTR *)((const char *)search + search->Bytes);
- }
-
- /* Return base address of translation data or NULL */
- return res;
-}
-EXPORT_SYMBOL(__TBITransStr);
diff --git a/arch/metag/tbx/tbitimer.S b/arch/metag/tbx/tbitimer.S
deleted file mode 100644
index 5dbeddeee7ba..000000000000
--- a/arch/metag/tbx/tbitimer.S
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * tbitimer.S
- *
- * Copyright (C) 2001, 2002, 2007, 2012 Imagination Technologies.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- *
- * TBI timer support routines and data values
- */
-
- .file "tbitimer.S"
-/*
- * Get data structures and defines from the main C header
- */
-#include <asm/tbx.h>
-
- .data
- .balign 8
- .global ___TBITimeB
- .type ___TBITimeB,object
-___TBITimeB:
- .quad 0 /* Background 'lost' ticks */
- .size ___TBITimeB,.-___TBITimeB
-
- .data
- .balign 8
- .global ___TBITimeI
- .type ___TBITimeI,object
-___TBITimeI:
- .quad 0 /* Interrupt 'lost' ticks */
- .size ___TBITimeI,.-___TBITimeI
-
- .data
- .balign 8
- .global ___TBITimes
- .type ___TBITimes,object
-___TBITimes:
- .long ___TBITimeB /* Table of 'lost' tick values */
- .long ___TBITimeI
- .size ___TBITimes,.-___TBITimes
-
-/*
- * Flag bits for control of ___TBITimeCore
- */
-#define TIMER_SET_BIT 1
-#define TIMER_ADD_BIT 2
-
-/*
- * Initialise or stop timer support
- *
- * Register Usage: D1Ar1 holds Id, D1Ar2 is initial delay or 0
- * D0FrT is used to call ___TBITimeCore
- * D0Re0 is used for the result which is TXSTAT_TIMER_BIT
- * D0Ar4, D1Ar5, D0Ar6 are all used as scratch
- * Other registers are those set by ___TBITimeCore
- * A0.3 is assumed to point at ___TBITime(I/B)
- */
- .text
- .balign 4
- .global ___TBITimerCtrl
- .type ___TBITimerCtrl,function
-___TBITimerCtrl:
- MOV D1Ar5,#TIMER_SET_BIT /* Timer SET request */
- MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
- CALL D0FrT,#LO(___TBITimeCore) /* and perform register update */
- NEGS D0Ar6,D0Ar2 /* Set flags from time-stamp */
- ASR D1Ar5,D0Ar6,#31 /* Sign extend D0Ar6 into D1Ar5 */
- SETLNZ [A0.3],D0Ar6,D1Ar5 /* ___TBITime(B/I)=-Start if enable */
- MOV PC,D1RtP /* Return */
- .size ___TBITimerCtrl,.-___TBITimerCtrl
-
-/*
- * Return ___TBITimeStamp value
- *
- * Register Usage: D1Ar1 holds Id
- * D0FrT is used to call ___TBITimeCore
- * D0Re0, D1Re0 is used for the result
- * D1Ar3, D0Ar4, D1Ar5
- * Other registers are those set by ___TBITimeCore
- * D0Ar6 is assumed to be the timer value read
- * A0.3 is assumed to point at ___TBITime(I/B)
- */
- .text
- .balign 4
- .global ___TBITimeStamp
- .type ___TBITimeStamp,function
-___TBITimeStamp:
- MOV D1Ar5,#0 /* Timer GET request */
- MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
- CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
- ADDS D0Re0,D0Ar4,D0Ar6 /* Add current time value */
- ADD D1Re0,D1Ar3,D1Ar5 /* to 64-bit signed extend time */
- ADDCS D1Re0,D1Re0,#1 /* Support borrow too */
- MOV PC,D1RtP /* Return */
- .size ___TBITimeStamp,.-___TBITimeStamp
-
-/*
- * Perform ___TBITimerAdd logic
- *
- * Register Usage: D1Ar1 holds Id, D0Ar2 holds value to be added to the timer
- * D0Re0 is used for the result - new TIMER value
- * D1Ar5, D0Ar6 are used as scratch
- * Other registers are those set by ___TBITimeCore
- * D0Ar6 is assumed to be the timer value read
- * D0Ar4, D1Ar3 is the current value of ___TBITime(B/I)
- */
- .text
- .balign 4
- .global ___TBITimerAdd
- .type ___TBITimerAdd,function
-___TBITimerAdd:
- MOV D1Ar5,#TIMER_ADD_BIT /* Timer ADD request */
- MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
- CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
- ADD D0Re0,D0Ar2,D0Ar6 /* Regenerate new value = result */
- NEG D0Ar2,D0Ar2 /* Negate delta */
- ASR D1Re0,D0Ar2,#31 /* Sign extend negated delta */
- ADDS D0Ar4,D0Ar4,D0Ar2 /* Add time added to ... */
- ADD D1Ar3,D1Ar3,D1Re0 /* ... real timer ... */
- ADDCS D1Ar3,D1Ar3,#1 /* ... with carry */
- SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
- MOV PC,D1RtP /* Return */
- .size ___TBITimerAdd,.-___TBITimerAdd
-
-#ifdef TBI_1_4
-/*
- * Perform ___TBITimerDeadline logic
- * NB: Delays are positive compared to the Wait values which are -ive
- *
- * Register Usage: D1Ar1 holds Id
- * D0Ar2 holds Delay requested
- * D0Re0 is used for the result - old TIMER Delay value
- * D1Ar5, D0Ar6 are used as scratch
- * Other registers are those set by ___TBITimeCore
- * D0Ar6 is assumed to be the timer value read
- * D0Ar4, D1Ar3 is the current value of ___TBITime(B/I)
- *
- */
- .text
- .type ___TBITimerDeadline,function
- .global ___TBITimerDeadline
- .align 2
-___TBITimerDeadline:
- MOV D1Ar5,#TIMER_SET_BIT /* Timer SET request */
- MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
- CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
- MOV D0Re0,D0Ar6 /* Old value read = result */
- SUB D0Ar2,D0Ar6,D0Ar2 /* Delta from (old - new) */
- ASR D1Re0,D0Ar2,#31 /* Sign extend delta */
- ADDS D0Ar4,D0Ar4,D0Ar2 /* Add time added to ... */
- ADD D1Ar3,D1Ar3,D1Re0 /* ... real timer ... */
- ADDCS D1Ar3,D1Ar3,#1 /* ... with carry */
- SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
- MOV PC,D1RtP /* Return */
- .size ___TBITimerDeadline,.-___TBITimerDeadline
-#endif /* TBI_1_4 */
-
-/*
- * Perform core timer access logic
- *
- * Register Usage: D1Ar1 holds Id, D0Ar2 holds input value for SET and
- * input value for ADD
- * D1Ar5 controls op as SET or ADD as bit values
- * On return D0Ar6, D1Ar5 holds the old 64-bit timer value
- * A0.3 is setup to point at ___TBITime(I/B)
- * A1.3 is setup to point at ___TBITimes
- * D0Ar4, D1Ar3 is setup to value of ___TBITime(I/B)
- */
- .text
- .balign 4
- .global ___TBITimeCore
- .type ___TBITimeCore,function
-___TBITimeCore:
-#ifndef METAC_0_1
- TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Interrupt level timer? */
-#endif
- MOVT A1LbP,#HI(___TBITimes)
- ADD A1LbP,A1LbP,#LO(___TBITimes)
- MOV A1.3,A1LbP /* Get ___TBITimes address */
-#ifndef METAC_0_1
- BNZ $LTimeCoreI /* Yes: Service TXTIMERI! */
-#endif
- LSRS D1Ar5,D1Ar5,#1 /* Carry = SET, Zero = !ADD */
- GETD A0.3,[A1.3+#0] /* A0.3 == &___TBITimeB */
- MOV D0Ar6,TXTIMER /* Always GET old value */
- MOVCS TXTIMER,D0Ar2 /* Conditional SET operation */
- ADDNZ TXTIMER,D0Ar2,D0Ar6 /* Conditional ADD operation */
-#ifndef METAC_0_1
- B $LTimeCoreEnd
-$LTimeCoreI:
- LSRS D1Ar5,D1Ar5,#1 /* Carry = SET, Zero = !ADD */
- GETD A0.3,[A1.3+#4] /* A0.3 == &___TBITimeI */
- MOV D0Ar6,TXTIMERI /* Always GET old value */
- MOVCS TXTIMERI,D0Ar2 /* Conditional SET operation */
- ADDNZ TXTIMERI,D0Ar2,D0Ar6 /* Conditional ADD operation */
-$LTimeCoreEnd:
-#endif
- ASR D1Ar5,D0Ar6,#31 /* Sign extend D0Ar6 into D1Ar5 */
- GETL D0Ar4,D1Ar3,[A0.3] /* Read ___TBITime(B/I) */
- MOV PC,D0FrT /* Return quickly */
- .size ___TBITimeCore,.-___TBITimeCore
-
-/*
- * End of tbitimer.S
- */
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 4f798aa671dd..3817a3e2146c 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -24,6 +24,7 @@ config MICROBLAZE
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_TRACER
+ select NO_BOOTMEM
select HAVE_MEMBLOCK
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
diff --git a/arch/microblaze/Kconfig.platform b/arch/microblaze/Kconfig.platform
index 6996f397c16c..f7f1739c11b9 100644
--- a/arch/microblaze/Kconfig.platform
+++ b/arch/microblaze/Kconfig.platform
@@ -8,7 +8,6 @@ menu "Platform options"
config OPT_LIB_FUNCTION
bool "Optimalized lib function"
- depends on CPU_LITTLE_ENDIAN
default y
help
Allows turn on optimalized library function (memcpy and memmove).
@@ -21,6 +20,7 @@ config OPT_LIB_FUNCTION
config OPT_LIB_ASM
bool "Optimalized lib function ASM"
depends on OPT_LIB_FUNCTION && (XILINX_MICROBLAZE0_USE_BARREL = 1)
+ depends on CPU_BIG_ENDIAN
default n
help
Allows turn on optimalized library function (memcpy and memmove).
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index be84a4d3917f..7c968c1d1729 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -44,7 +44,6 @@ void machine_shutdown(void);
void machine_halt(void);
void machine_power_off(void);
-extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
# endif /* __ASSEMBLY__ */
diff --git a/arch/microblaze/kernel/sys_microblaze.c b/arch/microblaze/kernel/sys_microblaze.c
index f1e1f666ddde..ed9f34da1a2a 100644
--- a/arch/microblaze/kernel/sys_microblaze.c
+++ b/arch/microblaze/kernel/sys_microblaze.c
@@ -40,7 +40,7 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
if (pgoff & ~PAGE_MASK)
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> PAGE_SHIFT);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> PAGE_SHIFT);
}
SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
@@ -50,6 +50,6 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
if (pgoff & (~PAGE_MASK >> 12))
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- pgoff >> (PAGE_SHIFT - 12));
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ pgoff >> (PAGE_SHIFT - 12));
}
diff --git a/arch/microblaze/lib/fastcopy.S b/arch/microblaze/lib/fastcopy.S
index 62021d7e249e..fdc48bb065d8 100644
--- a/arch/microblaze/lib/fastcopy.S
+++ b/arch/microblaze/lib/fastcopy.S
@@ -29,10 +29,6 @@
* between mem locations with size of xfer spec'd in bytes
*/
-#ifdef __MICROBLAZEEL__
-#error Microblaze LE not support ASM optimized lib func. Disable OPT_LIB_ASM.
-#endif
-
#include <linux/linkage.h>
.text
.globl memcpy
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 434639f9a3a6..df6de7ccdc2e 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -32,9 +32,6 @@ int mem_init_done;
#ifndef CONFIG_MMU
unsigned int __page_offset;
EXPORT_SYMBOL(__page_offset);
-
-#else
-static int init_bootmem_done;
#endif /* CONFIG_MMU */
char *klimit = _end;
@@ -117,7 +114,6 @@ static void __init paging_init(void)
void __init setup_memory(void)
{
- unsigned long map_size;
struct memblock_region *reg;
#ifndef CONFIG_MMU
@@ -174,17 +170,6 @@ void __init setup_memory(void)
pr_info("%s: max_low_pfn: %#lx\n", __func__, max_low_pfn);
pr_info("%s: max_pfn: %#lx\n", __func__, max_pfn);
- /*
- * Find an area to use for the bootmem bitmap.
- * We look for the first area which is at least
- * 128kB in length (128kB is enough for a bitmap
- * for 4GB of memory, using 4kB pages), plus 1 page
- * (in case the address isn't page-aligned).
- */
- map_size = init_bootmem_node(NODE_DATA(0),
- PFN_UP(TOPHYS((u32)klimit)), min_low_pfn, max_low_pfn);
- memblock_reserve(PFN_UP(TOPHYS((u32)klimit)) << PAGE_SHIFT, map_size);
-
/* Add active regions with valid PFNs */
for_each_memblock(memory, reg) {
unsigned long start_pfn, end_pfn;
@@ -196,32 +181,9 @@ void __init setup_memory(void)
&memblock.memory, 0);
}
- /* free bootmem is whole main memory */
- free_bootmem_with_active_regions(0, max_low_pfn);
-
- /* reserve allocate blocks */
- for_each_memblock(reserved, reg) {
- unsigned long top = reg->base + reg->size - 1;
-
- pr_debug("reserved - 0x%08x-0x%08x, %lx, %lx\n",
- (u32) reg->base, (u32) reg->size, top,
- memory_start + lowmem_size - 1);
-
- if (top <= (memory_start + lowmem_size - 1)) {
- reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
- } else if (reg->base < (memory_start + lowmem_size - 1)) {
- unsigned long trunc_size = memory_start + lowmem_size -
- reg->base;
- reserve_bootmem(reg->base, trunc_size, BOOTMEM_DEFAULT);
- }
- }
-
/* XXX need to clip this if using highmem? */
sparse_memory_present_with_active_regions(0);
-#ifdef CONFIG_MMU
- init_bootmem_done = 1;
-#endif
paging_init();
}
@@ -398,30 +360,16 @@ asmlinkage void __init mmu_init(void)
/* This is only called until mem_init is done. */
void __init *early_get_page(void)
{
- void *p;
- if (init_bootmem_done) {
- p = alloc_bootmem_pages(PAGE_SIZE);
- } else {
- /*
- * Mem start + kernel_tlb -> here is limit
- * because of mem mapping from head.S
- */
- p = __va(memblock_alloc_base(PAGE_SIZE, PAGE_SIZE,
- memory_start + kernel_tlb));
- }
- return p;
+ /*
+ * Mem start + kernel_tlb -> here is limit
+ * because of mem mapping from head.S
+ */
+ return __va(memblock_alloc_base(PAGE_SIZE, PAGE_SIZE,
+ memory_start + kernel_tlb));
}
#endif /* CONFIG_MMU */
-void * __ref alloc_maybe_bootmem(size_t size, gfp_t mask)
-{
- if (mem_init_done)
- return kmalloc(size, mask);
- else
- return alloc_bootmem(size);
-}
-
void * __ref zalloc_maybe_bootmem(size_t size, gfp_t mask)
{
void *p;
diff --git a/arch/mips/ath25/board.c b/arch/mips/ath25/board.c
index 9ab48ff80c1c..6d11ae581ea7 100644
--- a/arch/mips/ath25/board.c
+++ b/arch/mips/ath25/board.c
@@ -135,6 +135,8 @@ int __init ath25_find_config(phys_addr_t base, unsigned long size)
}
board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
+ if (!board_data)
+ goto error;
ath25_board.config = (struct ath25_boarddata *)board_data;
memcpy_fromio(board_data, bcfg, 0x100);
if (broken_boarddata) {
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index c7bb8a407041..7b335ab21697 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -10,7 +10,7 @@
* IP32 changes by Ilya.
* Copyright (C) 2010 Cavium Networks, Inc.
*/
-#include <linux/dma-mapping.h>
+#include <linux/dma-direct.h>
#include <linux/scatterlist.h>
#include <linux/bootmem.h>
#include <linux/export.h>
@@ -182,7 +182,7 @@ struct octeon_dma_map_ops {
phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
};
-dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
struct octeon_dma_map_ops,
@@ -190,9 +190,9 @@ dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
return ops->phys_to_dma(dev, paddr);
}
-EXPORT_SYMBOL(phys_to_dma);
+EXPORT_SYMBOL(__phys_to_dma);
-phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
struct octeon_dma_map_ops,
@@ -200,7 +200,7 @@ phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
return ops->dma_to_phys(dev, daddr);
}
-EXPORT_SYMBOL(dma_to_phys);
+EXPORT_SYMBOL(__dma_to_phys);
static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
.dma_map_ops = {
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 5b3a3f6a9ad3..d99f5242169e 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -2277,6 +2277,8 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
}
host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
+ if (!host_data)
+ return -ENOMEM;
raw_spin_lock_init(&host_data->lock);
addr = of_get_address(ciu_node, 0, NULL, NULL);
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index 138edf6b5b48..6eb1ee548b11 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -69,8 +69,8 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
return addr + size - 1 <= *dev->dma_mask;
}
-dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
-phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
struct dma_map_ops;
extern const struct dma_map_ops *octeon_pci_dma_map_ops;
diff --git a/arch/mips/include/asm/mach-loongson64/dma-coherence.h b/arch/mips/include/asm/mach-loongson64/dma-coherence.h
index b1b575f5c6c1..64fc44dec0a8 100644
--- a/arch/mips/include/asm/mach-loongson64/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson64/dma-coherence.h
@@ -25,13 +25,13 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
return addr + size - 1 <= *dev->dma_mask;
}
-extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
-extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
+extern dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
+extern phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
#ifdef CONFIG_CPU_LOONGSON3
- return phys_to_dma(dev, virt_to_phys(addr));
+ return __phys_to_dma(dev, virt_to_phys(addr));
#else
return virt_to_phys(addr) | 0x80000000;
#endif
@@ -41,7 +41,7 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
#ifdef CONFIG_CPU_LOONGSON3
- return phys_to_dma(dev, page_to_phys(page));
+ return __phys_to_dma(dev, page_to_phys(page));
#else
return page_to_phys(page) | 0x80000000;
#endif
@@ -51,7 +51,7 @@ static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
#if defined(CONFIG_CPU_LOONGSON3) && defined(CONFIG_64BIT)
- return dma_to_phys(dev, dma_addr);
+ return __dma_to_phys(dev, dma_addr);
#elif defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
#else
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index b332f6fc1e72..318f1c05c5b3 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -67,8 +67,8 @@ SYSCALL_DEFINE6(32_mmap2, unsigned long, addr, unsigned long, len,
{
if (pgoff & (~PAGE_MASK >> 12))
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- pgoff >> (PAGE_SHIFT-12));
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ pgoff >> (PAGE_SHIFT-12));
}
#define RLIM_INFINITY32 0x7fffffff
@@ -82,13 +82,13 @@ struct rlimit32 {
SYSCALL_DEFINE4(32_truncate64, const char __user *, path,
unsigned long, __dummy, unsigned long, a2, unsigned long, a3)
{
- return sys_truncate(path, merge_64(a2, a3));
+ return ksys_truncate(path, merge_64(a2, a3));
}
SYSCALL_DEFINE4(32_ftruncate64, unsigned long, fd, unsigned long, __dummy,
unsigned long, a2, unsigned long, a3)
{
- return sys_ftruncate(fd, merge_64(a2, a3));
+ return ksys_ftruncate(fd, merge_64(a2, a3));
}
SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high,
@@ -105,13 +105,13 @@ SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high,
SYSCALL_DEFINE6(32_pread, unsigned long, fd, char __user *, buf, size_t, count,
unsigned long, unused, unsigned long, a4, unsigned long, a5)
{
- return sys_pread64(fd, buf, count, merge_64(a4, a5));
+ return ksys_pread64(fd, buf, count, merge_64(a4, a5));
}
SYSCALL_DEFINE6(32_pwrite, unsigned int, fd, const char __user *, buf,
size_t, count, u32, unused, u64, a4, u64, a5)
{
- return sys_pwrite64(fd, buf, count, merge_64(a4, a5));
+ return ksys_pwrite64(fd, buf, count, merge_64(a4, a5));
}
SYSCALL_DEFINE1(32_personality, unsigned long, personality)
@@ -131,7 +131,7 @@ SYSCALL_DEFINE1(32_personality, unsigned long, personality)
asmlinkage ssize_t sys32_readahead(int fd, u32 pad0, u64 a2, u64 a3,
size_t count)
{
- return sys_readahead(fd, merge_64(a2, a3), count);
+ return ksys_readahead(fd, merge_64(a2, a3), count);
}
asmlinkage long sys32_sync_file_range(int fd, int __pad,
@@ -139,7 +139,7 @@ asmlinkage long sys32_sync_file_range(int fd, int __pad,
unsigned long a4, unsigned long a5,
int flags)
{
- return sys_sync_file_range(fd,
+ return ksys_sync_file_range(fd,
merge_64(a2, a3), merge_64(a4, a5),
flags);
}
@@ -149,7 +149,7 @@ asmlinkage long sys32_fadvise64_64(int fd, int __pad,
unsigned long a4, unsigned long a5,
int flags)
{
- return sys_fadvise64_64(fd,
+ return ksys_fadvise64_64(fd,
merge_64(a2, a3), merge_64(a4, a5),
flags);
}
@@ -157,6 +157,6 @@ asmlinkage long sys32_fadvise64_64(int fd, int __pad,
asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2,
unsigned offset_a3, unsigned len_a4, unsigned len_a5)
{
- return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3),
- merge_64(len_a4, len_a5));
+ return ksys_fallocate(fd, mode, merge_64(offset_a2, offset_a3),
+ merge_64(len_a4, len_a5));
}
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 6668f67a61c3..ee73550f0b9a 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -711,7 +711,7 @@ static int validate_group(struct perf_event *event)
if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
return -EINVAL;
- list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+ for_each_sibling_event(sibling, leader) {
if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
return -EINVAL;
}
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 57028d49c202..b9e9bf628849 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -781,6 +781,8 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
atomic_set(&task->mm->context.fp_mode_switching, 0);
preempt_enable();
+ wake_up_var(&task->mm->context.fp_mode_switching);
+
return 0;
}
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 9d41732a9146..159e83add4bb 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -168,11 +168,11 @@ static void bmips_prepare_cpus(unsigned int max_cpus)
return;
}
- if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
- "smp_ipi0", NULL))
+ if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
panic("Can't request IPI0 interrupt");
- if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
- "smp_ipi1", NULL))
+ if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
+ IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
panic("Can't request IPI1 interrupt");
}
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 58c6f634b550..69c17b549fd3 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -63,7 +63,8 @@ SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
{
if (offset & ~PAGE_MASK)
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> PAGE_SHIFT);
}
SYSCALL_DEFINE6(mips_mmap2, unsigned long, addr, unsigned long, len,
@@ -73,7 +74,8 @@ SYSCALL_DEFINE6(mips_mmap2, unsigned long, addr, unsigned long, len,
if (pgoff & (~PAGE_MASK >> 12))
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT-12));
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ pgoff >> (PAGE_SHIFT - 12));
}
save_static_function(sys_fork);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0ae4a731cc12..967e9e4e795e 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1248,8 +1248,8 @@ static int enable_restore_fp_context(int msa)
* If an FP mode switch is currently underway, wait for it to
* complete before proceeding.
*/
- wait_on_atomic_t(&current->mm->context.fp_mode_switching,
- atomic_t_wait, TASK_KILLABLE);
+ wait_var_event(&current->mm->context.fp_mode_switching,
+ !atomic_read(&current->mm->context.fp_mode_switching));
if (!used_math()) {
/* First time FP context user. */
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 692ae85a3e3d..8e3a1fc2bc39 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -13,6 +13,8 @@ choice
config SOC_AMAZON_SE
bool "Amazon SE"
select SOC_TYPE_XWAY
+ select MFD_SYSCON
+ select MFD_CORE
config SOC_XWAY
bool "XWAY"
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 52500d3b7004..e0af39b33e28 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -549,9 +549,9 @@ void __init ltq_soc_init(void)
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
ltq_ar9_fpi_hz(), CLOCK_250M);
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
- clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
- clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
+ clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
@@ -560,7 +560,7 @@ void __init ltq_soc_init(void)
} else {
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
- clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
+ clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index bc2fdbfa8223..72af0c183969 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -7,6 +7,8 @@ choice
config LEMOTE_FULOONG2E
bool "Lemote Fuloong(2e) mini-PC"
select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_LOONGSON2E
@@ -33,6 +35,8 @@ config LEMOTE_FULOONG2E
config LEMOTE_MACH2F
bool "Lemote Loongson 2F family machines"
select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
select BOARD_SCACHE
select BOOT_ELF32
select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
@@ -62,6 +66,8 @@ config LEMOTE_MACH2F
config LOONGSON_MACH3X
bool "Generic Loongson 3 family machines"
select ARCH_SPARSEMEM_ENABLE
+ select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select BOOT_ELF32
select BOARD_SCACHE
diff --git a/arch/mips/loongson64/common/dma-swiotlb.c b/arch/mips/loongson64/common/dma-swiotlb.c
index 7bbcf89475f3..6a739f8ae110 100644
--- a/arch/mips/loongson64/common/dma-swiotlb.c
+++ b/arch/mips/loongson64/common/dma-swiotlb.c
@@ -63,7 +63,7 @@ static int loongson_dma_supported(struct device *dev, u64 mask)
return swiotlb_dma_supported(dev, mask);
}
-dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
long nid;
#ifdef CONFIG_PHYS48_TO_HT40
@@ -75,7 +75,7 @@ dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
return paddr;
}
-phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
long nid;
#ifdef CONFIG_PHYS48_TO_HT40
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 1b274742077d..d2718de60b9b 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -170,6 +170,28 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
u32 n1;
u32 rev;
+ /* Early detection of CMP support */
+ mips_cm_probe();
+ mips_cpc_probe();
+
+ if (mips_cps_numiocu(0)) {
+ /*
+ * mips_cm_probe() wipes out bootloader
+ * config for CM regions and we have to configure them
+ * again. This SoC cannot talk to pamlbus devices
+ * witout proper iocu region set up.
+ *
+ * FIXME: it would be better to do this with values
+ * from DT, but we need this very early because
+ * without this we cannot talk to pretty much anything
+ * including serial.
+ */
+ write_gcr_reg0_base(MT7621_PALMBUS_BASE);
+ write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
+ CM_GCR_REGn_MASK_CMTGT_IOCU0);
+ __sync();
+ }
+
n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
@@ -194,26 +216,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
rt2880_pinmux_data = mt7621_pinmux_data;
- /* Early detection of CMP support */
- mips_cm_probe();
- mips_cpc_probe();
-
- if (mips_cps_numiocu(0)) {
- /*
- * mips_cm_probe() wipes out bootloader
- * config for CM regions and we have to configure them
- * again. This SoC cannot talk to pamlbus devices
- * witout proper iocu region set up.
- *
- * FIXME: it would be better to do this with values
- * from DT, but we need this very early because
- * without this we cannot talk to pretty much anything
- * including serial.
- */
- write_gcr_reg0_base(MT7621_PALMBUS_BASE);
- write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
- CM_GCR_REGn_MASK_CMTGT_IOCU0);
- }
if (!register_cps_smp_ops())
return;
diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
index 64543d66e76b..e9531fea23a2 100644
--- a/arch/mips/ralink/reset.c
+++ b/arch/mips/ralink/reset.c
@@ -96,16 +96,9 @@ static void ralink_restart(char *command)
unreachable();
}
-static void ralink_halt(void)
-{
- local_irq_disable();
- unreachable();
-}
-
static int __init mips_reboot_setup(void)
{
_machine_restart = ralink_restart;
- _machine_halt = ralink_halt;
return 0;
}
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
deleted file mode 100644
index e9d8d60bd28b..000000000000
--- a/arch/mn10300/Kconfig
+++ /dev/null
@@ -1,499 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-config MN10300
- def_bool y
- select HAVE_EXIT_THREAD
- select HAVE_OPROFILE
- select HAVE_UID16
- select GENERIC_IRQ_SHOW
- select ARCH_WANT_IPC_PARSE_VERSION
- select HAVE_ARCH_TRACEHOOK
- select HAVE_ARCH_KGDB
- select GENERIC_ATOMIC64
- select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER
- select VIRT_TO_BUS
- select GENERIC_CLOCKEVENTS
- select MODULES_USE_ELF_RELA
- select OLD_SIGSUSPEND3
- select OLD_SIGACTION
- select HAVE_DEBUG_STACKOVERFLOW
- select ARCH_NO_COHERENT_DMA_MMAP
-
-config AM33_2
- def_bool n
-
-config AM33_3
- def_bool n
-
-config AM34_2
- def_bool n
- select MN10300_HAS_ATOMIC_OPS_UNIT
- select MN10300_HAS_CACHE_SNOOP
-
-config ERRATUM_NEED_TO_RELOAD_MMUCTR
- def_bool y if AM33_3 || AM34_2
-
-config MMU
- def_bool y
-
-config HIGHMEM
- def_bool n
-
-config NUMA
- def_bool n
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config RWSEM_XCHGADD_ALGORITHM
- bool
-
-config GENERIC_CALIBRATE_DELAY
- def_bool y
-
-config GENERIC_HWEIGHT
- def_bool y
-
-config GENERIC_BUG
- def_bool y
- depends on BUG
-
-config QUICKLIST
- def_bool y
-
-config ARCH_HAS_ILOG2_U32
- def_bool y
-
-config HOTPLUG_CPU
- def_bool n
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-
-menu "Panasonic MN10300 system setup"
-
-choice
- prompt "Unit type"
- default MN10300_UNIT_ASB2303
- help
- This option specifies board for which the kernel will be
- compiled. It affects the external peripherals catered for.
-
-config MN10300_UNIT_ASB2303
- bool "ASB2303"
-
-config MN10300_UNIT_ASB2305
- bool "ASB2305"
-
-config MN10300_UNIT_ASB2364
- bool "ASB2364"
- select SMSC911X_ARCH_HOOKS if SMSC911X
-
-endchoice
-
-choice
- prompt "Processor support"
- default MN10300_PROC_MN103E010
- help
- This option specifies the processor for which the kernel will be
- compiled. It affects the on-chip peripherals catered for.
-
-config MN10300_PROC_MN103E010
- bool "MN103E010"
- depends on MN10300_UNIT_ASB2303 || MN10300_UNIT_ASB2305
- select AM33_2
- select MN10300_PROC_HAS_TTYSM0
- select MN10300_PROC_HAS_TTYSM1
- select MN10300_PROC_HAS_TTYSM2
-
-config MN10300_PROC_MN2WS0050
- bool "MN2WS0050"
- depends on MN10300_UNIT_ASB2364
- select AM34_2
- select MN10300_PROC_HAS_TTYSM0
- select MN10300_PROC_HAS_TTYSM1
- select MN10300_PROC_HAS_TTYSM2
-
-endchoice
-
-config MN10300_HAS_ATOMIC_OPS_UNIT
- def_bool n
- help
- This should be enabled if the processor has an atomic ops unit
- capable of doing LL/SC equivalent operations.
-
-config FPU
- bool "FPU present"
- default y
- depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050
-
-config LAZY_SAVE_FPU
- bool "Save FPU state lazily"
- default y
- depends on FPU && !SMP
- help
- Enable this to be lazy in the saving of the FPU state to the owning
- task's thread struct. This is useful if most tasks on the system
- don't use the FPU as only those tasks that use it will pass it
- between them, and the state needn't be saved for a task that isn't
- using it.
-
- This can't be so easily used on SMP as the process that owns the FPU
- state on a CPU may be currently running on another CPU, so for the
- moment, it is disabled.
-
-source "arch/mn10300/mm/Kconfig.cache"
-
-config MN10300_TLB_USE_PIDR
- def_bool y
-
-menu "Memory layout options"
-
-config KERNEL_RAM_BASE_ADDRESS
- hex "Base address of kernel RAM"
- default "0x90000000"
-
-config INTERRUPT_VECTOR_BASE
- hex "Base address of vector table"
- default "0x90000000"
- help
- The base address of the vector table will be programmed into
- the TBR register. It must be on 16MiB address boundary.
-
-config KERNEL_TEXT_ADDRESS
- hex "Base address of kernel"
- default "0x90001000"
-
-config KERNEL_ZIMAGE_BASE_ADDRESS
- hex "Base address of compressed vmlinux image"
- default "0x50700000"
-
-config BOOT_STACK_OFFSET
- hex
- default "0xF00" if SMP
- default "0xFF0" if !SMP
-
-config BOOT_STACK_SIZE
- hex
- depends on SMP
- default "0x100"
-endmenu
-
-config SMP
- bool "Symmetric multi-processing support"
- default y
- depends on MN10300_PROC_MN2WS0050
- ---help---
- This enables support for systems with more than one CPU. If you have
- a system with only one CPU, say N. If you have a system with more
- than one CPU, say Y.
-
- If you say N here, the kernel will run on uni- and multiprocessor
- machines, but will use only one CPU of a multiprocessor machine. If
- you say Y here, the kernel will run on many, but not all,
- uniprocessor machines. On a uniprocessor machine, the kernel
- will run faster if you say N here.
-
- See also <file:Documentation/x86/i386/IO-APIC.txt>,
- <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
- <http://www.tldp.org/docs.html#howto>.
-
- If you don't know what to do here, say N.
-
-config NR_CPUS
- int
- depends on SMP
- default "2"
-
-source "kernel/Kconfig.preempt"
-
-config MN10300_CURRENT_IN_E2
- bool "Hold current task address in E2 register"
- depends on !SMP
- default y
- help
- This option removes the E2/R2 register from the set available to gcc
- for normal use and instead uses it to store the address of the
- current process's task_struct whilst in the kernel.
-
- This means the kernel doesn't need to calculate the address each time
- "current" is used (take SP, AND with mask and dereference pointer
- just to get the address), and instead can just use E2+offset
- addressing each time.
-
- This has no effect on userspace.
-
-config MN10300_USING_JTAG
- bool "Using JTAG to debug kernel"
- default y
- help
- This options indicates that JTAG will be used to debug the kernel. It
- suppresses the use of certain hardware debugging features, such as
- single-stepping, which are taken over completely by the JTAG unit.
-
-source "kernel/Kconfig.hz"
-
-config MN10300_RTC
- bool "Using MN10300 RTC"
- depends on MN10300_PROC_MN103E010 || MN10300_PROC_MN2WS0050
- select RTC_CLASS
- select RTC_DRV_CMOS
- select RTC_SYSTOHC
- default n
- help
- This option enables support for the RTC, thus enabling time to be
- tracked, even when system is powered down. This is available on-chip
- on the MN103E010.
-
-config MN10300_WD_TIMER
- bool "Using MN10300 watchdog timer"
- default y
- help
- This options indicates that the watchdog timer will be used.
-
-config PCI
- bool "Use PCI"
- depends on MN10300_UNIT_ASB2305
- default y
- select GENERIC_PCI_IOMAP
- help
- Some systems (such as the ASB2305) have PCI onboard. If you have one
- of these boards and you wish to use the PCI facilities, say Y here.
-
- The PCI-HOWTO, available from
- <http://www.tldp.org/docs.html#howto>, contains valuable
- information about which PCI hardware does work under Linux and which
- doesn't.
-
-source "drivers/pci/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-menu "MN10300 internal serial options"
-
-config MN10300_PROC_HAS_TTYSM0
- bool
- default n
-
-config MN10300_PROC_HAS_TTYSM1
- bool
- default n
-
-config MN10300_PROC_HAS_TTYSM2
- bool
- default n
-
-config MN10300_TTYSM
- bool "Support for ttySM serial ports"
- depends on MN10300
- default y
- select SERIAL_CORE
- help
- This option enables support for the on-chip serial ports that the
- MN10300 has available.
-
-config MN10300_TTYSM_CONSOLE
- bool "Support for console on ttySM serial ports"
- depends on MN10300_TTYSM
- select SERIAL_CORE_CONSOLE
- help
- This option enables support for a console on the on-chip serial ports
- that the MN10300 has available.
-
-#
-# /dev/ttySM0
-#
-config MN10300_TTYSM0
- bool "Enable SIF0 (/dev/ttySM0)"
- depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM0
- help
- Enable access to SIF0 through /dev/ttySM0 or gdb-stub
-
-choice
- prompt "Select the timer to supply the clock for SIF0"
- default MN10300_TTYSM0_TIMER8
- depends on MN10300_TTYSM0
-
-config MN10300_TTYSM0_TIMER8
- bool "Use timer 8 (16-bit)"
-
-config MN10300_TTYSM0_TIMER2
- bool "Use timer 2 (8-bit)"
-
-endchoice
-
-#
-# /dev/ttySM1
-#
-config MN10300_TTYSM1
- bool "Enable SIF1 (/dev/ttySM1)"
- depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM1
- help
- Enable access to SIF1 through /dev/ttySM1 or gdb-stub
-
-choice
- prompt "Select the timer to supply the clock for SIF1"
- default MN10300_TTYSM1_TIMER12 \
- if !(AM33_2 || AM33_3)
- default MN10300_TTYSM1_TIMER9 \
- if AM33_2 || AM33_3
- depends on MN10300_TTYSM1
-
-config MN10300_TTYSM1_TIMER12
- bool "Use timer 12 (16-bit)"
- depends on !(AM33_2 || AM33_3)
-
-config MN10300_TTYSM1_TIMER9
- bool "Use timer 9 (16-bit)"
- depends on AM33_2 || AM33_3
-
-config MN10300_TTYSM1_TIMER3
- bool "Use timer 3 (8-bit)"
- depends on AM33_2 || AM33_3
-
-endchoice
-
-#
-# /dev/ttySM2
-#
-config MN10300_TTYSM2
- bool "Enable SIF2 (/dev/ttySM2)"
- depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM2
- help
- Enable access to SIF2 through /dev/ttySM2 or gdb-stub
-
-choice
- prompt "Select the timer to supply the clock for SIF2"
- default MN10300_TTYSM2_TIMER3 \
- if !(AM33_2 || AM33_3)
- default MN10300_TTYSM2_TIMER10 \
- if AM33_2 || AM33_3
- depends on MN10300_TTYSM2
-
-config MN10300_TTYSM2_TIMER9
- bool "Use timer 9 (16-bit)"
- depends on !(AM33_2 || AM33_3)
-
-config MN10300_TTYSM2_TIMER1
- bool "Use timer 1 (8-bit)"
- depends on !(AM33_2 || AM33_3)
-
-config MN10300_TTYSM2_TIMER3
- bool "Use timer 3 (8-bit)"
- depends on !(AM33_2 || AM33_3)
-
-config MN10300_TTYSM2_TIMER10
- bool "Use timer 10 (16-bit)"
- depends on AM33_2 || AM33_3
-
-endchoice
-
-config MN10300_TTYSM2_CTS
- bool "Enable the use of the CTS line /dev/ttySM2"
- depends on MN10300_TTYSM2 && AM33_2
-
-endmenu
-
-menu "Interrupt request priority options"
-
-comment "[!] NOTE: A lower number/level indicates a higher priority (0 is highest, 6 is lowest)"
-
-comment "____Non-maskable interrupt levels____"
-comment "The following must be set to a higher priority than local_irq_disable() and on-chip serial"
-
-config DEBUGGER_IRQ_LEVEL
- int "DEBUGGER interrupt priority"
- depends on KERNEL_DEBUGGER
- range 0 1 if LINUX_CLI_LEVEL = 2
- range 0 2 if LINUX_CLI_LEVEL = 3
- range 0 3 if LINUX_CLI_LEVEL = 4
- range 0 4 if LINUX_CLI_LEVEL = 5
- range 0 5 if LINUX_CLI_LEVEL = 6
- default 0
-
-comment "The following must be set to a higher priority than local_irq_disable()"
-
-config MN10300_SERIAL_IRQ_LEVEL
- int "MN10300 on-chip serial interrupt priority"
- depends on MN10300_TTYSM
- range 1 1 if LINUX_CLI_LEVEL = 2
- range 1 2 if LINUX_CLI_LEVEL = 3
- range 1 3 if LINUX_CLI_LEVEL = 4
- range 1 4 if LINUX_CLI_LEVEL = 5
- range 1 5 if LINUX_CLI_LEVEL = 6
- default 1
-
-comment "-"
-comment "____Maskable interrupt levels____"
-
-config LINUX_CLI_LEVEL
- int "The highest interrupt priority excluded by local_irq_disable() (2-6)"
- range 2 6
- default 2
- help
- local_irq_disable() doesn't actually disable maskable interrupts -
- what it does is restrict the levels of interrupt which are permitted
- (a lower level indicates a higher priority) by lowering the value in
- EPSW.IM from 7. Any interrupt is permitted for which the level is
- lower than EPSW.IM.
-
- Certain interrupts, such as DEBUGGER and virtual MN10300 on-chip
- serial DMA interrupts are allowed to interrupt normal disabled
- sections.
-
-comment "The following must be set to a equal to or lower priority than LINUX_CLI_LEVEL"
-
-config TIMER_IRQ_LEVEL
- int "Kernel timer interrupt priority"
- range LINUX_CLI_LEVEL 6
- default 4
-
-config PCI_IRQ_LEVEL
- int "PCI interrupt priority"
- depends on PCI
- range LINUX_CLI_LEVEL 6
- default 5
-
-config ETHERNET_IRQ_LEVEL
- int "Ethernet interrupt priority"
- depends on SMC91X || SMC911X || SMSC911X
- range LINUX_CLI_LEVEL 6
- default 6
-
-config EXT_SERIAL_IRQ_LEVEL
- int "External serial port interrupt priority"
- depends on SERIAL_8250
- range LINUX_CLI_LEVEL 6
- default 6
-
-endmenu
-
-source "mm/Kconfig"
-
-menu "Power management options"
-source kernel/power/Kconfig
-endmenu
-
-endmenu
-
-
-menu "Executable formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/mn10300/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug
deleted file mode 100644
index 37ada651f756..000000000000
--- a/arch/mn10300/Kconfig.debug
+++ /dev/null
@@ -1,156 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config DEBUG_DECOMPRESS_KERNEL
- bool "Using serial port during decompressing kernel"
- depends on DEBUG_KERNEL
- default n
- help
- If you say Y here you will confirm the start and the end of
- decompressing Linux seeing "Uncompressing Linux... " and
- "Ok, booting the kernel.\n" on console.
-
-config TEST_MISALIGNMENT_HANDLER
- bool "Run tests on the misalignment handler"
- depends on DEBUG_KERNEL
- default n
- help
- If you say Y here the kernel will execute a list of misaligned memory
- accesses to make sure the misalignment handler deals them with
- correctly. If it does not, the kernel will throw a BUG.
-
-config KPROBES
- bool "Kprobes"
- depends on DEBUG_KERNEL
- help
- Kprobes allows you to trap at almost any kernel address and
- execute a callback function. register_kprobe() establishes
- a probepoint and specifies the callback. Kprobes is useful
- for kernel debugging, non-intrusive instrumentation and testing.
- If in doubt, say "N".
-
-config GDBSTUB
- bool "Remote GDB kernel debugging"
- depends on DEBUG_KERNEL && DEPRECATED
- select DEBUG_INFO
- select FRAME_POINTER
- help
- If you say Y here, it will be possible to remotely debug the kernel
- using gdb. This enlarges your kernel ELF image disk size by several
- megabytes and requires a machine with more than 16 MB, better 32 MB
- RAM to avoid excessive linking time. This is only useful for kernel
- hackers. If unsure, say N.
-
- This is deprecated in favour of KGDB and will be removed in a later
- version.
-
-config GDBSTUB_IMMEDIATE
- bool "Break into GDB stub immediately"
- depends on GDBSTUB
- help
- If you say Y here, GDB stub will break into the program as soon as
- possible, leaving the program counter at the beginning of
- start_kernel() in init/main.c.
-
-config GDBSTUB_ALLOW_SINGLE_STEP
- bool "Allow software single-stepping in GDB stub"
- depends on GDBSTUB && !SMP && !PREEMPT
- help
- Allow GDB stub to perform software single-stepping through the
- kernel. This doesn't work very well on SMP or preemptible kernels as
- it uses temporary breakpoints to emulate single-stepping.
-
-config GDB_CONSOLE
- bool "Console output to GDB"
- depends on GDBSTUB
- help
- If you are using GDB for remote debugging over a serial port and
- would like kernel messages to be formatted into GDB $O packets so
- that GDB prints them as program output, say 'Y'.
-
-config GDBSTUB_DEBUGGING
- bool "Debug GDB stub by messages to serial port"
- depends on GDBSTUB
- help
- This causes debugging messages to be displayed at various points
- during execution of the GDB stub routines. Such messages will be
- displayed on ttyS0 if that isn't the GDB stub's port, or ttySM0
- otherwise.
-
-config GDBSTUB_DEBUG_ENTRY
- bool "Debug GDB stub entry"
- depends on GDBSTUB_DEBUGGING
- help
- This option causes information to be displayed about entry to or exit
- from the main GDB stub routine.
-
-config GDBSTUB_DEBUG_PROTOCOL
- bool "Debug GDB stub protocol"
- depends on GDBSTUB_DEBUGGING
- help
- This option causes information to be displayed about the GDB remote
- protocol messages generated exchanged with GDB.
-
-config GDBSTUB_DEBUG_IO
- bool "Debug GDB stub I/O"
- depends on GDBSTUB_DEBUGGING
- help
- This option causes information to be displayed about GDB stub's
- low-level I/O.
-
-config GDBSTUB_DEBUG_BREAKPOINT
- bool "Debug GDB stub breakpoint management"
- depends on GDBSTUB_DEBUGGING
- help
- This option causes information to be displayed about GDB stub's
- breakpoint management.
-
-choice
- prompt "GDB stub port"
- default GDBSTUB_ON_TTYSM0
- depends on GDBSTUB
- help
- Select the serial port used for GDB-stub.
-
-config GDBSTUB_ON_TTYSM0
- bool "/dev/ttySM0 [SIF0]"
- depends on MN10300_TTYSM0
- select GDBSTUB_ON_TTYSMx
-
-config GDBSTUB_ON_TTYSM1
- bool "/dev/ttySM1 [SIF1]"
- depends on MN10300_TTYSM1
- select GDBSTUB_ON_TTYSMx
-
-config GDBSTUB_ON_TTYSM2
- bool "/dev/ttySM2 [SIF2]"
- depends on MN10300_TTYSM2
- select GDBSTUB_ON_TTYSMx
-
-config GDBSTUB_ON_TTYS0
- bool "/dev/ttyS0"
- select GDBSTUB_ON_TTYSx
-
-config GDBSTUB_ON_TTYS1
- bool "/dev/ttyS1"
- select GDBSTUB_ON_TTYSx
-
-endchoice
-
-config GDBSTUB_ON_TTYSMx
- bool
- depends on GDBSTUB_ON_TTYSM0 || GDBSTUB_ON_TTYSM1 || GDBSTUB_ON_TTYSM2
- default y
-
-config GDBSTUB_ON_TTYSx
- bool
- depends on GDBSTUB_ON_TTYS0 || GDBSTUB_ON_TTYS1
- default y
-
-endmenu
-
-config KERNEL_DEBUGGER
- def_bool y
- depends on GDBSTUB || KGDB
diff --git a/arch/mn10300/Makefile b/arch/mn10300/Makefile
deleted file mode 100644
index 3f1ea5ddc402..000000000000
--- a/arch/mn10300/Makefile
+++ /dev/null
@@ -1,99 +0,0 @@
-###############################################################################
-#
-# MN10300 Kernel makefile system specifications
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Modified by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-
-KBUILD_DEFCONFIG := asb2303_defconfig
-
-CCSPECS := $(shell $(CC) -v 2>&1 | grep "^Reading specs from " | head -1 | cut -c20-)
-CCDIR := $(strip $(patsubst %/specs,%,$(CCSPECS)))
-KBUILD_CPPFLAGS += -nostdinc -I$(CCDIR)/include
-
-LDFLAGS :=
-OBJCOPYFLAGS := -O binary -R .note -R .comment -R .GCC-command-line -R .note.gnu.build-id -S
-#LDFLAGS_vmlinux := -Map linkmap.txt
-CHECKFLAGS +=
-
-PROCESSOR := unset
-UNIT := unset
-
-KBUILD_CFLAGS += -mam33 -DCPU=AM33 $(call cc-option,-mmem-funcs,)
-KBUILD_AFLAGS += -mam33 -DCPU=AM33
-
-ifeq ($(CONFIG_MN10300_CURRENT_IN_E2),y)
-KBUILD_CFLAGS += -ffixed-e2 -fcall-saved-e5
-endif
-
-ifeq ($(CONFIG_MN10300_PROC_MN103E010),y)
-PROCESSOR := mn103e010
-endif
-ifeq ($(CONFIG_MN10300_PROC_MN2WS0050),y)
-PROCESSOR := mn2ws0050
-endif
-
-ifeq ($(CONFIG_MN10300_UNIT_ASB2303),y)
-UNIT := asb2303
-endif
-ifeq ($(CONFIG_MN10300_UNIT_ASB2305),y)
-UNIT := asb2305
-endif
-ifeq ($(CONFIG_MN10300_UNIT_ASB2364),y)
-UNIT := asb2364
-endif
-
-
-head-y := arch/mn10300/kernel/head.o
-
-core-y += arch/mn10300/kernel/ arch/mn10300/mm/
-
-ifneq ($(PROCESSOR),unset)
-core-y += arch/mn10300/proc-$(PROCESSOR)/
-endif
-ifneq ($(UNIT),unset)
-core-y += arch/mn10300/unit-$(UNIT)/
-endif
-libs-y += arch/mn10300/lib/
-
-drivers-$(CONFIG_OPROFILE) += arch/mn10300/oprofile/
-
-boot := arch/mn10300/boot
-
-.PHONY: zImage
-
-KBUILD_IMAGE := $(boot)/zImage
-CLEAN_FILES += $(boot)/zImage
-CLEAN_FILES += $(boot)/compressed/vmlinux
-CLEAN_FILES += $(boot)/compressed/vmlinux.bin
-CLEAN_FILES += $(boot)/compressed/vmlinux.bin.gz
-
-zImage: vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-all: zImage
-
-bootstrap:
- $(Q)$(MAKEBOOT) bootstrap
-
-archclean:
- $(Q)$(MAKE) $(clean)=arch/mn10300/proc-mn103e010
- $(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2303
- $(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2305
-
-define archhelp
- echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
-endef
-
-#
-# include the appropriate processor- and unit-specific headers
-#
-KBUILD_CPPFLAGS += -I$(srctree)/arch/mn10300/proc-$(PROCESSOR)/include
-KBUILD_CPPFLAGS += -I$(srctree)/arch/mn10300/unit-$(UNIT)/include
diff --git a/arch/mn10300/boot/.gitignore b/arch/mn10300/boot/.gitignore
deleted file mode 100644
index b6718de23693..000000000000
--- a/arch/mn10300/boot/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-zImage
diff --git a/arch/mn10300/boot/Makefile b/arch/mn10300/boot/Makefile
deleted file mode 100644
index 36c9caf8ea0a..000000000000
--- a/arch/mn10300/boot/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-# MN10300 kernel compressor and wrapper
-#
-# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-
-targets := vmlinux.bin zImage
-
-subdir- := compressed
-
-# ---------------------------------------------------------------------------
-
-
-$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
- $(call if_changed,objcopy)
- @echo 'Kernel: $@ is ready'
-
-$(obj)/vmlinux.bin: $(obj)/compressed/vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/compressed/vmlinux: FORCE
- $(Q)$(MAKE) $(build)=$(obj)/compressed IMAGE_OFFSET=$(IMAGE_OFFSET) $@
diff --git a/arch/mn10300/boot/compressed/Makefile b/arch/mn10300/boot/compressed/Makefile
deleted file mode 100644
index 9b9a48fc8e53..000000000000
--- a/arch/mn10300/boot/compressed/Makefile
+++ /dev/null
@@ -1,22 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Create a compressed vmlinux image from the original vmlinux
-#
-
-targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o
-
-LDFLAGS_vmlinux := -Ttext $(CONFIG_KERNEL_ZIMAGE_BASE_ADDRESS) -e startup_32
-
-$(obj)/vmlinux: $(obj)/head.o $(obj)/misc.o $(obj)/piggy.o FORCE
- $(call if_changed,ld)
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
-
-$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
- $(call if_changed,gzip)
-
-LDFLAGS_piggy.o := -r --format binary --oformat elf32-am33lin -T
-
-$(obj)/piggy.o: $(obj)/vmlinux.lds $(obj)/vmlinux.bin.gz FORCE
- $(call if_changed,ld)
diff --git a/arch/mn10300/boot/compressed/head.S b/arch/mn10300/boot/compressed/head.S
deleted file mode 100644
index 7b50345b9e84..000000000000
--- a/arch/mn10300/boot/compressed/head.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Boot entry point for a compressed MN10300 kernel
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
- .section .text
-
-#define DEBUG
-
-#include <linux/linkage.h>
-#include <asm/cpu-regs.h>
-#include <asm/cache.h>
-#ifdef CONFIG_SMP
-#include <proc/smp-regs.h>
-#endif
-
- .globl startup_32
-startup_32:
-#ifdef CONFIG_SMP
- #
- # Secondary CPUs jump directly to the kernel entry point
- #
- # Must save primary CPU's D0-D2 registers as they hold boot parameters
- #
- mov (CPUID), d3
- and CPUID_MASK,d3
- beq startup_primary
- mov CONFIG_KERNEL_TEXT_ADDRESS,a0
- jmp (a0)
-
-startup_primary:
-#endif /* CONFIG_SMP */
-
- # first save parameters from bootloader
- mov param_save_area,a0
- mov d0,(a0)
- mov d1,(4,a0)
- mov d2,(8,a0)
-
- mov sp,a3
- mov decomp_stack+0x2000-4,a0
- mov a0,sp
-
- # invalidate and enable both of the caches
- mov CHCTR,a0
- clr d0
- movhu d0,(a0) # turn off first
- mov CHCTR_ICINV|CHCTR_DCINV,d0
- movhu d0,(a0)
- setlb
- mov (a0),d0
- btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
- lne
-
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-#ifdef CONFIG_MN10300_CACHE_WBACK
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
-#else
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
-#endif /* WBACK */
- movhu d0,(a0) # enable
-#endif /* !ENABLED */
-
- # clear the BSS area
- mov __bss_start,a0
- mov _end,a1
- clr d0
-bssclear:
- cmp a1,a0
- bge bssclear_end
- movbu d0,(a0)
- inc a0
- bra bssclear
-bssclear_end:
-
- # decompress the kernel
- call decompress_kernel[],0
-#ifdef CONFIG_MN10300_CACHE_WBACK
- call mn10300_dcache_flush_inv[],0
-#endif
-
- # disable caches again
- mov CHCTR,a0
- clr d0
- movhu d0,(a0)
- setlb
- mov (a0),d0
- btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
- lne
-
- mov param_save_area,a0
- mov (a0),d0
- mov (4,a0),d1
- mov (8,a0),d2
-
- # jump to the kernel proper entry point
- mov a3,sp
- mov CONFIG_KERNEL_TEXT_ADDRESS,a0
- jmp (a0)
-
-
-###############################################################################
-#
-# Cache flush routines
-#
-###############################################################################
-#ifdef CONFIG_MN10300_CACHE_WBACK
-mn10300_dcache_flush_inv:
- movhu (CHCTR),d0
- btst CHCTR_DCEN,d0
- beq mn10300_dcache_flush_inv_end
-
- mov L1_CACHE_NENTRIES,d1
- clr a1
-
-mn10300_dcache_flush_inv_loop:
- mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge
- mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge
- mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge
- mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
-
- add L1_CACHE_BYTES,a1
- add -1,d1
- bne mn10300_dcache_flush_inv_loop
-
-mn10300_dcache_flush_inv_end:
- ret [],0
-#endif /* CONFIG_MN10300_CACHE_WBACK */
-
-
-###############################################################################
-#
-# Data areas
-#
-###############################################################################
- .data
- .align 4
-param_save_area:
- .rept 3
- .word 0
- .endr
-
- .section .bss
- .align 4
-decomp_stack:
- .space 0x2000
diff --git a/arch/mn10300/boot/compressed/misc.c b/arch/mn10300/boot/compressed/misc.c
deleted file mode 100644
index 42cbd77bd439..000000000000
--- a/arch/mn10300/boot/compressed/misc.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/* MN10300 Miscellaneous helper routines for kernel decompressor
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- * - Derived from arch/x86/boot/compressed/misc_32.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/compiler.h>
-#include <asm/serial-regs.h>
-#include "misc.h"
-
-#ifndef CONFIG_GDBSTUB_ON_TTYSx
-/* display 'Uncompressing Linux... ' messages on ttyS0 or ttyS1 */
-#if 1 /* ttyS0 */
-#define CYG_DEV_BASE 0xA6FB0000
-#else /* ttyS1 */
-#define CYG_DEV_BASE 0xA6FC0000
-#endif
-
-#define CYG_DEV_THR (*((volatile __u8*)(CYG_DEV_BASE + 0x00)))
-#define CYG_DEV_MCR (*((volatile __u8*)(CYG_DEV_BASE + 0x10)))
-#define SIO_MCR_DTR 0x01
-#define SIO_MCR_RTS 0x02
-#define CYG_DEV_LSR (*((volatile __u8*)(CYG_DEV_BASE + 0x14)))
-#define SIO_LSR_THRE 0x20 /* transmitter holding register empty */
-#define SIO_LSR_TEMT 0x40 /* transmitter register empty */
-#define CYG_DEV_MSR (*((volatile __u8*)(CYG_DEV_BASE + 0x18)))
-#define SIO_MSR_CTS 0x10 /* clear to send */
-#define SIO_MSR_DSR 0x20 /* data set ready */
-
-#define LSR_WAIT_FOR(STATE) \
- do { while (!(CYG_DEV_LSR & SIO_LSR_##STATE)) {} } while (0)
-#define FLOWCTL_QUERY(LINE) \
- ({ CYG_DEV_MSR & SIO_MSR_##LINE; })
-#define FLOWCTL_WAIT_FOR(LINE) \
- do { while (!(CYG_DEV_MSR & SIO_MSR_##LINE)) {} } while (0)
-#define FLOWCTL_CLEAR(LINE) \
- do { CYG_DEV_MCR &= ~SIO_MCR_##LINE; } while (0)
-#define FLOWCTL_SET(LINE) \
- do { CYG_DEV_MCR |= SIO_MCR_##LINE; } while (0)
-#endif
-
-/*
- * gzip declarations
- */
-
-#define OF(args) args
-#define STATIC static
-
-#undef memset
-#undef memcpy
-
-static inline void *memset(const void *s, int c, size_t n)
-{
- int i;
- char *ss = (char *) s;
-
- for (i = 0; i < n; i++)
- ss[i] = c;
- return (void *)s;
-}
-
-#define memzero(s, n) memset((s), 0, (n))
-
-static inline void *memcpy(void *__dest, const void *__src, size_t __n)
-{
- int i;
- const char *s = __src;
- char *d = __dest;
-
- for (i = 0; i < __n; i++)
- d[i] = s[i];
- return __dest;
-}
-
-typedef unsigned char uch;
-typedef unsigned short ush;
-typedef unsigned long ulg;
-
-#define WSIZE 0x8000 /* Window size must be at least 32k, and a power of
- * two */
-
-static uch *inbuf; /* input buffer */
-static uch window[WSIZE]; /* sliding window buffer */
-
-static unsigned insize; /* valid bytes in inbuf */
-static unsigned inptr; /* index of next byte to be processed in inbuf */
-static unsigned outcnt; /* bytes in output buffer */
-
-/* gzip flag byte */
-#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
-#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
-#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
-#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
-#define COMMENT 0x10 /* bit 4 set: file comment present */
-#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
-#define RESERVED 0xC0 /* bit 6,7: reserved */
-
-/* Diagnostic functions */
-#ifdef DEBUG
-# define Assert(cond, msg) { if (!(cond)) error(msg); }
-# define Trace(x) fprintf x
-# define Tracev(x) { if (verbose) fprintf x ; }
-# define Tracevv(x) { if (verbose > 1) fprintf x ; }
-# define Tracec(c, x) { if (verbose && (c)) fprintf x ; }
-# define Tracecv(c, x) { if (verbose > 1 && (c)) fprintf x ; }
-#else
-# define Assert(cond, msg)
-# define Trace(x)
-# define Tracev(x)
-# define Tracevv(x)
-# define Tracec(c, x)
-# define Tracecv(c, x)
-#endif
-
-static int fill_inbuf(void);
-static void flush_window(void);
-static void error(const char *) __attribute__((noreturn));
-static void kputs(const char *);
-
-static inline unsigned char get_byte(void)
-{
- unsigned char ch = inptr < insize ? inbuf[inptr++] : fill_inbuf();
-
-#if 0
- char hex[3];
- hex[0] = ((ch & 0x0f) > 9) ?
- ((ch & 0x0f) + 'A' - 0xa) : ((ch & 0x0f) + '0');
- hex[1] = ((ch >> 4) > 9) ?
- ((ch >> 4) + 'A' - 0xa) : ((ch >> 4) + '0');
- hex[2] = 0;
- kputs(hex);
-#endif
- return ch;
-}
-
-/*
- * This is set up by the setup-routine at boot-time
- */
-#define EXT_MEM_K (*(unsigned short *)0x90002)
-#ifndef STANDARD_MEMORY_BIOS_CALL
-#define ALT_MEM_K (*(unsigned long *) 0x901e0)
-#endif
-#define SCREEN_INFO (*(struct screen_info *)0x90000)
-
-static long bytes_out;
-static uch *output_data;
-static unsigned long output_ptr;
-
-
-static unsigned long free_mem_ptr = (unsigned long) &end;
-static unsigned long free_mem_end_ptr = (unsigned long) &end + 0x90000;
-
-#define INPLACE_MOVE_ROUTINE 0x1000
-#define LOW_BUFFER_START 0x2000
-#define LOW_BUFFER_END 0x90000
-#define LOW_BUFFER_SIZE (LOW_BUFFER_END - LOW_BUFFER_START)
-#define HEAP_SIZE 0x3000
-static int high_loaded;
-static uch *high_buffer_start /* = (uch *)(((ulg)&end) + HEAP_SIZE)*/;
-
-static char *vidmem = (char *)0xb8000;
-static int lines, cols;
-
-#define BOOTLOADER_INFLATE
-#include "../../../../lib/inflate.c"
-
-static inline void scroll(void)
-{
- int i;
-
- memcpy(vidmem, vidmem + cols * 2, (lines - 1) * cols * 2);
- for (i = (lines - 1) * cols * 2; i < lines * cols * 2; i += 2)
- vidmem[i] = ' ';
-}
-
-static inline void kputchar(unsigned char ch)
-{
-#ifdef CONFIG_MN10300_UNIT_ASB2305
- while (SC0STR & SC01STR_TBF)
- continue;
-
- if (ch == 0x0a) {
- SC0TXB = 0x0d;
- while (SC0STR & SC01STR_TBF)
- continue;
- }
-
- SC0TXB = ch;
-
-#else
- while (SC1STR & SC01STR_TBF)
- continue;
-
- if (ch == 0x0a) {
- SC1TXB = 0x0d;
- while (SC1STR & SC01STR_TBF)
- continue;
- }
-
- SC1TXB = ch;
-
-#endif
-}
-
-static void kputs(const char *s)
-{
-#ifdef CONFIG_DEBUG_DECOMPRESS_KERNEL
-#ifndef CONFIG_GDBSTUB_ON_TTYSx
- char ch;
-
- FLOWCTL_SET(DTR);
-
- while (*s) {
- LSR_WAIT_FOR(THRE);
-
- ch = *s++;
- if (ch == 0x0a) {
- CYG_DEV_THR = 0x0d;
- LSR_WAIT_FOR(THRE);
- }
- CYG_DEV_THR = ch;
- }
-
- FLOWCTL_CLEAR(DTR);
-#else
-
- for (; *s; s++)
- kputchar(*s);
-
-#endif
-#endif /* CONFIG_DEBUG_DECOMPRESS_KERNEL */
-}
-
-/* ===========================================================================
- * Fill the input buffer. This is called only when the buffer is empty
- * and at least one byte is really needed.
- */
-static int fill_inbuf()
-{
- if (insize != 0)
- error("ran out of input data\n");
-
- inbuf = input_data;
- insize = input_len;
- inptr = 1;
- return inbuf[0];
-}
-
-/* ===========================================================================
- * Write the output window window[0..outcnt-1] and update crc and bytes_out.
- * (Used for the decompressed data only.)
- */
-static void flush_window_low(void)
-{
- ulg c = crc; /* temporary variable */
- unsigned n;
- uch *in, *out, ch;
-
- in = window;
- out = &output_data[output_ptr];
- for (n = 0; n < outcnt; n++) {
- ch = *out++ = *in++;
- c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
- }
- crc = c;
- bytes_out += (ulg)outcnt;
- output_ptr += (ulg)outcnt;
- outcnt = 0;
-}
-
-static void flush_window_high(void)
-{
- ulg c = crc; /* temporary variable */
- unsigned n;
- uch *in, ch;
- in = window;
- for (n = 0; n < outcnt; n++) {
- ch = *output_data++ = *in++;
- if ((ulg) output_data == LOW_BUFFER_END)
- output_data = high_buffer_start;
- c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
- }
- crc = c;
- bytes_out += (ulg)outcnt;
- outcnt = 0;
-}
-
-static void flush_window(void)
-{
- if (high_loaded)
- flush_window_high();
- else
- flush_window_low();
-}
-
-static void error(const char *x)
-{
- kputs("\n\n");
- kputs(x);
- kputs("\n\n -- System halted");
-
- while (1)
- /* Halt */;
-}
-
-#define STACK_SIZE (4096)
-
-long user_stack[STACK_SIZE];
-
-struct {
- long *a;
- short b;
-} stack_start = { &user_stack[STACK_SIZE], 0 };
-
-void setup_normal_output_buffer(void)
-{
-#ifdef STANDARD_MEMORY_BIOS_CALL
- if (EXT_MEM_K < 1024)
- error("Less than 2MB of memory.\n");
-#else
- if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < 1024)
- error("Less than 2MB of memory.\n");
-#endif
- output_data = (char *) 0x100000; /* Points to 1M */
-}
-
-struct moveparams {
- uch *low_buffer_start;
- int lcount;
- uch *high_buffer_start;
- int hcount;
-};
-
-void setup_output_buffer_if_we_run_high(struct moveparams *mv)
-{
- high_buffer_start = (uch *)(((ulg) &end) + HEAP_SIZE);
-#ifdef STANDARD_MEMORY_BIOS_CALL
- if (EXT_MEM_K < (3 * 1024))
- error("Less than 4MB of memory.\n");
-#else
- if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < (3 * 1024))
- error("Less than 4MB of memory.\n");
-#endif
- mv->low_buffer_start = output_data = (char *) LOW_BUFFER_START;
- high_loaded = 1;
- free_mem_end_ptr = (long) high_buffer_start;
- if (0x100000 + LOW_BUFFER_SIZE > (ulg) high_buffer_start) {
- high_buffer_start = (uch *)(0x100000 + LOW_BUFFER_SIZE);
- mv->hcount = 0; /* say: we need not to move high_buffer */
- } else {
- mv->hcount = -1;
- }
- mv->high_buffer_start = high_buffer_start;
-}
-
-void close_output_buffer_if_we_run_high(struct moveparams *mv)
-{
- mv->lcount = bytes_out;
- if (bytes_out > LOW_BUFFER_SIZE) {
- mv->lcount = LOW_BUFFER_SIZE;
- if (mv->hcount)
- mv->hcount = bytes_out - LOW_BUFFER_SIZE;
- } else {
- mv->hcount = 0;
- }
-}
-
-#undef DEBUGFLAG
-#ifdef DEBUGFLAG
-int debugflag;
-#endif
-
-int decompress_kernel(struct moveparams *mv)
-{
-#ifdef DEBUGFLAG
- while (!debugflag)
- barrier();
-#endif
-
- output_data = (char *) CONFIG_KERNEL_TEXT_ADDRESS;
-
- makecrc();
- kputs("Uncompressing Linux... ");
- gunzip();
- kputs("Ok, booting the kernel.\n");
- return 0;
-}
diff --git a/arch/mn10300/boot/compressed/misc.h b/arch/mn10300/boot/compressed/misc.h
deleted file mode 100644
index da921cd172fb..000000000000
--- a/arch/mn10300/boot/compressed/misc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Internal definitions for the MN10300 kernel decompressor
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-extern int end;
-
-/*
- * vmlinux.lds
- */
-extern char input_data[];
-extern int input_len;
diff --git a/arch/mn10300/boot/compressed/vmlinux.lds b/arch/mn10300/boot/compressed/vmlinux.lds
deleted file mode 100644
index a084903603fe..000000000000
--- a/arch/mn10300/boot/compressed/vmlinux.lds
+++ /dev/null
@@ -1,9 +0,0 @@
-SECTIONS
-{
- .data : {
- input_len = .;
- LONG(input_data_end - input_data) input_data = .;
- *(.data)
- input_data_end = .;
- }
-}
diff --git a/arch/mn10300/boot/install.sh b/arch/mn10300/boot/install.sh
deleted file mode 100644
index abba30971191..000000000000
--- a/arch/mn10300/boot/install.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/sh
-#
-# arch/mn10300/boot/install -c.sh
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# Licence. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 1995 by Linus Torvalds
-#
-# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
-#
-# "make install -c" script for i386 architecture
-#
-# Arguments:
-# $1 - kernel version
-# $2 - kernel image file
-# $3 - kernel map file
-# $4 - default install -c path (blank if root directory)
-# $5 - boot rom file
-#
-
-# User may have a custom install -c script
-
-rm -fr $4/../usr/include/linux $4/../usr/include/asm
-install -c -m 0755 $2 $4/vmlinuz
-install -c -m 0755 $5 $4/boot.rom
-install -c -m 0755 -d $4/../usr/include/linux
-cd ${srctree}/include/linux
-for i in `find . -maxdepth 1 -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/linux
-done
-install -c -m 0755 -d $4/../usr/include/linux/byteorder
-cd ${srctree}/include/linux/byteorder
-for i in `find . -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/linux/byteorder
-done
-install -c -m 0755 -d $4/../usr/include/linux/lockd
-cd ${srctree}/include/linux/lockd
-for i in `find . -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/linux/lockd
-done
-install -c -m 0755 -d $4/../usr/include/linux/netfilter_ipv4
-cd ${srctree}/include/linux/netfilter_ipv4
-for i in `find . -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/linux/netfilter_ipv4
-done
-install -c -m 0755 -d $4/../usr/include/linux/nfsd
-cd ${srctree}/include/linux/nfsd
-for i in `find . -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/linux/nfsd/$i
-done
-install -c -m 0755 -d $4/../usr/include/linux/raid
-cd ${srctree}/include/linux/raid
-for i in `find . -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/linux/raid
-done
-install -c -m 0755 -d $4/../usr/include/linux/sunrpc
-cd ${srctree}/include/linux/sunrpc
-for i in `find . -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/linux/sunrpc
-done
-install -c -m 0755 -d $4/../usr/include/asm
-cd ${srctree}/include/asm
-for i in `find . -name '*.h' -print`; do
- install -c -m 0644 $i $4/../usr/include/asm
-done
diff --git a/arch/mn10300/boot/tools/build.c b/arch/mn10300/boot/tools/build.c
deleted file mode 100644
index 3ce158fe07b0..000000000000
--- a/arch/mn10300/boot/tools/build.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 1991, 1992 Linus Torvalds
- * Copyright (C) 1997 Martin Mares
- */
-
-/*
- * This file builds a disk-image from three different files:
- *
- * - bootsect: exactly 512 bytes of 8086 machine code, loads the rest
- * - setup: 8086 machine code, sets up system parm
- * - system: 80386 code for actual system
- *
- * It does some checking that all files are of the correct type, and
- * just writes the result to stdout, removing headers and padding to
- * the right amount. It also writes some system data to stderr.
- */
-
-/*
- * Changes by tytso to allow root device specification
- * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
- * Cross compiling fixes by Gertjan van Wingerde, July 1996
- * Rewritten by Martin Mares, April 1997
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/sysmacros.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <asm/boot.h>
-
-#define DEFAULT_MAJOR_ROOT 0
-#define DEFAULT_MINOR_ROOT 0
-
-/* Minimal number of setup sectors (see also bootsect.S) */
-#define SETUP_SECTS 4
-
-uint8_t buf[1024];
-int fd;
-int is_big_kernel;
-
-__attribute__((noreturn))
-void die(const char *str, ...)
-{
- va_list args;
- va_start(args, str);
- vfprintf(stderr, str, args);
- fputc('\n', stderr);
- exit(1);
-}
-
-void file_open(const char *name)
-{
- fd = open(name, O_RDONLY, 0);
- if (fd < 0)
- die("Unable to open `%s': %m", name);
-}
-
-__attribute__((noreturn))
-void usage(void)
-{
- die("Usage: build [-b] bootsect setup system [rootdev] [> image]");
-}
-
-int main(int argc, char **argv)
-{
- unsigned int i, c, sz, setup_sectors;
- uint32_t sys_size;
- uint8_t major_root, minor_root;
- struct stat sb;
-
- if (argc > 2 && !strcmp(argv[1], "-b")) {
- is_big_kernel = 1;
- argc--, argv++;
- }
- if ((argc < 4) || (argc > 5))
- usage();
- if (argc > 4) {
- if (!strcmp(argv[4], "CURRENT")) {
- if (stat("/", &sb)) {
- perror("/");
- die("Couldn't stat /");
- }
- major_root = major(sb.st_dev);
- minor_root = minor(sb.st_dev);
- } else if (strcmp(argv[4], "FLOPPY")) {
- if (stat(argv[4], &sb)) {
- perror(argv[4]);
- die("Couldn't stat root device.");
- }
- major_root = major(sb.st_rdev);
- minor_root = minor(sb.st_rdev);
- } else {
- major_root = 0;
- minor_root = 0;
- }
- } else {
- major_root = DEFAULT_MAJOR_ROOT;
- minor_root = DEFAULT_MINOR_ROOT;
- }
- fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
-
- file_open(argv[1]);
- i = read(fd, buf, sizeof(buf));
- fprintf(stderr, "Boot sector %d bytes.\n", i);
- if (i != 512)
- die("Boot block must be exactly 512 bytes");
- if (buf[510] != 0x55 || buf[511] != 0xaa)
- die("Boot block hasn't got boot flag (0xAA55)");
- buf[508] = minor_root;
- buf[509] = major_root;
- if (write(1, buf, 512) != 512)
- die("Write call failed");
- close(fd);
-
- /* Copy the setup code */
- file_open(argv[2]);
- for (i = 0; (c = read(fd, buf, sizeof(buf))) > 0; i += c)
- if (write(1, buf, c) != c)
- die("Write call failed");
- if (c != 0)
- die("read-error on `setup'");
- close(fd);
-
- /* Pad unused space with zeros */
- setup_sectors = (i + 511) / 512;
- /* for compatibility with ancient versions of LILO. */
- if (setup_sectors < SETUP_SECTS)
- setup_sectors = SETUP_SECTS;
- fprintf(stderr, "Setup is %d bytes.\n", i);
- memset(buf, 0, sizeof(buf));
- while (i < setup_sectors * 512) {
- c = setup_sectors * 512 - i;
- if (c > sizeof(buf))
- c = sizeof(buf);
- if (write(1, buf, c) != c)
- die("Write call failed");
- i += c;
- }
-
- file_open(argv[3]);
- if (fstat(fd, &sb))
- die("Unable to stat `%s': %m", argv[3]);
- sz = sb.st_size;
- fprintf(stderr, "System is %d kB\n", sz / 1024);
- sys_size = (sz + 15) / 16;
- /* 0x28000*16 = 2.5 MB, conservative estimate for the current maximum */
- if (sys_size > (is_big_kernel ? 0x28000 : DEF_SYSSIZE))
- die("System is too big. Try using %smodules.",
- is_big_kernel ? "" : "bzImage or ");
- if (sys_size > 0xffff)
- fprintf(stderr,
- "warning: kernel is too big for standalone boot "
- "from floppy\n");
- while (sz > 0) {
- int l, n;
-
- l = (sz > sizeof(buf)) ? sizeof(buf) : sz;
- n = read(fd, buf, l);
- if (n != l) {
- if (n < 0)
- die("Error reading %s: %m", argv[3]);
- else
- die("%s: Unexpected EOF", argv[3]);
- }
- if (write(1, buf, l) != l)
- die("Write failed");
- sz -= l;
- }
- close(fd);
-
- /* Write sizes to the bootsector */
- if (lseek(1, 497, SEEK_SET) != 497)
- die("Output: seek failed");
- buf[0] = setup_sectors;
- if (write(1, buf, 1) != 1)
- die("Write of setup sector count failed");
- if (lseek(1, 500, SEEK_SET) != 500)
- die("Output: seek failed");
- buf[0] = (sys_size & 0xff);
- buf[1] = ((sys_size >> 8) & 0xff);
- if (write(1, buf, 2) != 2)
- die("Write of image length failed");
-
- return 0;
-}
diff --git a/arch/mn10300/configs/asb2303_defconfig b/arch/mn10300/configs/asb2303_defconfig
deleted file mode 100644
index d06dae131139..000000000000
--- a/arch/mn10300/configs/asb2303_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_TINY_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-# CONFIG_BLOCK is not set
-CONFIG_PREEMPT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_MN10300_RTC=y
-CONFIG_MN10300_TTYSM_CONSOLE=y
-CONFIG_MN10300_TTYSM0=y
-CONFIG_MN10300_TTYSM1=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_I4=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_RTC=y
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_PROC_KCORE=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_STRIP_ASM_SYMS=y
diff --git a/arch/mn10300/configs/asb2364_defconfig b/arch/mn10300/configs/asb2364_defconfig
deleted file mode 100644
index a84c3153f22a..000000000000
--- a/arch/mn10300/configs/asb2364_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_FREEZER=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLOCK is not set
-CONFIG_MN10300_UNIT_ASB2364=y
-CONFIG_PREEMPT=y
-# CONFIG_MN10300_USING_JTAG is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_MN10300_TTYSM_CONSOLE=y
-CONFIG_MN10300_TTYSM0=y
-CONFIG_MN10300_TTYSM0_TIMER2=y
-CONFIG_MN10300_TTYSM1=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_IPV6=y
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-CONFIG_CONNECTOR=y
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_I4=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_PROC_KCORE=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
diff --git a/arch/mn10300/include/asm/Kbuild b/arch/mn10300/include/asm/Kbuild
deleted file mode 100644
index 509c45a75d1f..000000000000
--- a/arch/mn10300/include/asm/Kbuild
+++ /dev/null
@@ -1,13 +0,0 @@
-
-generic-y += barrier.h
-generic-y += device.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += irq_work.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += preempt.h
-generic-y += sections.h
-generic-y += trace_clock.h
-generic-y += word-at-a-time.h
diff --git a/arch/mn10300/include/asm/asm-offsets.h b/arch/mn10300/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/mn10300/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/mn10300/include/asm/atomic.h b/arch/mn10300/include/asm/atomic.h
deleted file mode 100644
index 36389efd45e8..000000000000
--- a/arch/mn10300/include/asm/atomic.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* MN10300 Atomic counter operations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_ATOMIC_H
-#define _ASM_ATOMIC_H
-
-#include <asm/irqflags.h>
-#include <asm/cmpxchg.h>
-#include <asm/barrier.h>
-
-#ifndef CONFIG_SMP
-#include <asm-generic/atomic.h>
-#else
-
-/*
- * Atomic operations that C can't guarantee us. Useful for
- * resource counting etc..
- */
-
-#define ATOMIC_INIT(i) { (i) }
-
-#ifdef __KERNEL__
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v. Note that the guaranteed
- */
-#define atomic_read(v) READ_ONCE((v)->counter)
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i. Note that the guaranteed
- */
-#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
-
-#define ATOMIC_OP(op) \
-static inline void atomic_##op(int i, atomic_t *v) \
-{ \
- int retval, status; \
- \
- asm volatile( \
- "1: mov %4,(_AAR,%3) \n" \
- " mov (_ADR,%3),%1 \n" \
- " " #op " %5,%1 \n" \
- " mov %1,(_ADR,%3) \n" \
- " mov (_ADR,%3),%0 \n" /* flush */ \
- " mov (_ASR,%3),%0 \n" \
- " or %0,%0 \n" \
- " bne 1b \n" \
- : "=&r"(status), "=&r"(retval), "=m"(v->counter) \
- : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
- : "memory", "cc"); \
-}
-
-#define ATOMIC_OP_RETURN(op) \
-static inline int atomic_##op##_return(int i, atomic_t *v) \
-{ \
- int retval, status; \
- \
- asm volatile( \
- "1: mov %4,(_AAR,%3) \n" \
- " mov (_ADR,%3),%1 \n" \
- " " #op " %5,%1 \n" \
- " mov %1,(_ADR,%3) \n" \
- " mov (_ADR,%3),%0 \n" /* flush */ \
- " mov (_ASR,%3),%0 \n" \
- " or %0,%0 \n" \
- " bne 1b \n" \
- : "=&r"(status), "=&r"(retval), "=m"(v->counter) \
- : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
- : "memory", "cc"); \
- return retval; \
-}
-
-#define ATOMIC_FETCH_OP(op) \
-static inline int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- int retval, status; \
- \
- asm volatile( \
- "1: mov %4,(_AAR,%3) \n" \
- " mov (_ADR,%3),%1 \n" \
- " mov %1,%0 \n" \
- " " #op " %5,%0 \n" \
- " mov %0,(_ADR,%3) \n" \
- " mov (_ADR,%3),%0 \n" /* flush */ \
- " mov (_ASR,%3),%0 \n" \
- " or %0,%0 \n" \
- " bne 1b \n" \
- : "=&r"(status), "=&r"(retval), "=m"(v->counter) \
- : "a"(ATOMIC_OPS_BASE_ADDR), "r"(&v->counter), "r"(i) \
- : "memory", "cc"); \
- return retval; \
-}
-
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_OP_RETURN(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(add)
-ATOMIC_OPS(sub)
-
-#undef ATOMIC_OPS
-#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
-
-ATOMIC_OPS(and)
-ATOMIC_OPS(or)
-ATOMIC_OPS(xor)
-
-#undef ATOMIC_OPS
-#undef ATOMIC_FETCH_OP
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
-
-static inline int atomic_add_negative(int i, atomic_t *v)
-{
- return atomic_add_return(i, v) < 0;
-}
-
-static inline void atomic_inc(atomic_t *v)
-{
- atomic_add_return(1, v);
-}
-
-static inline void atomic_dec(atomic_t *v)
-{
- atomic_sub_return(1, v);
-}
-
-#define atomic_dec_return(v) atomic_sub_return(1, (v))
-#define atomic_inc_return(v) atomic_add_return(1, (v))
-
-#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
-
-#define __atomic_add_unless(v, a, u) \
-({ \
- int c, old; \
- c = atomic_read(v); \
- while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
- c = old; \
- c; \
-})
-
-#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
-#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
-
-#endif /* __KERNEL__ */
-#endif /* CONFIG_SMP */
-#endif /* _ASM_ATOMIC_H */
diff --git a/arch/mn10300/include/asm/bitops.h b/arch/mn10300/include/asm/bitops.h
deleted file mode 100644
index fe6f8e2c3617..000000000000
--- a/arch/mn10300/include/asm/bitops.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* MN10300 bit operations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- *
- * These have to be done with inline assembly: that way the bit-setting
- * is guaranteed to be atomic. All bit operations return 0 if the bit
- * was cleared before the operation and != 0 if it was not.
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- */
-#ifndef __ASM_BITOPS_H
-#define __ASM_BITOPS_H
-
-#include <asm/cpu-regs.h>
-#include <asm/barrier.h>
-
-/*
- * set bit
- */
-#define __set_bit(nr, addr) \
-({ \
- volatile unsigned char *_a = (unsigned char *)(addr); \
- const unsigned shift = (nr) & 7; \
- _a += (nr) >> 3; \
- \
- asm volatile("bset %2,(%1) # set_bit reg" \
- : "=m"(*_a) \
- : "a"(_a), "d"(1 << shift), "m"(*_a) \
- : "memory", "cc"); \
-})
-
-#define set_bit(nr, addr) __set_bit((nr), (addr))
-
-/*
- * clear bit
- */
-#define ___clear_bit(nr, addr) \
-({ \
- volatile unsigned char *_a = (unsigned char *)(addr); \
- const unsigned shift = (nr) & 7; \
- _a += (nr) >> 3; \
- \
- asm volatile("bclr %2,(%1) # clear_bit reg" \
- : "=m"(*_a) \
- : "a"(_a), "d"(1 << shift), "m"(*_a) \
- : "memory", "cc"); \
-})
-
-#define clear_bit(nr, addr) ___clear_bit((nr), (addr))
-
-
-static inline void __clear_bit(unsigned long nr, volatile void *addr)
-{
- unsigned int *a = (unsigned int *) addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- *a &= ~mask;
-}
-
-/*
- * test bit
- */
-static inline int test_bit(unsigned long nr, const volatile void *addr)
-{
- return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31));
-}
-
-/*
- * change bit
- */
-static inline void __change_bit(unsigned long nr, volatile void *addr)
-{
- int mask;
- unsigned int *a = (unsigned int *) addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- *a ^= mask;
-}
-
-extern void change_bit(unsigned long nr, volatile void *addr);
-
-/*
- * test and set bit
- */
-#define __test_and_set_bit(nr,addr) \
-({ \
- volatile unsigned char *_a = (unsigned char *)(addr); \
- const unsigned shift = (nr) & 7; \
- unsigned epsw; \
- _a += (nr) >> 3; \
- \
- asm volatile("bset %3,(%2) # test_set_bit reg\n" \
- "mov epsw,%1" \
- : "=m"(*_a), "=d"(epsw) \
- : "a"(_a), "d"(1 << shift), "m"(*_a) \
- : "memory", "cc"); \
- \
- !(epsw & EPSW_FLAG_Z); \
-})
-
-#define test_and_set_bit(nr, addr) __test_and_set_bit((nr), (addr))
-
-/*
- * test and clear bit
- */
-#define __test_and_clear_bit(nr, addr) \
-({ \
- volatile unsigned char *_a = (unsigned char *)(addr); \
- const unsigned shift = (nr) & 7; \
- unsigned epsw; \
- _a += (nr) >> 3; \
- \
- asm volatile("bclr %3,(%2) # test_clear_bit reg\n" \
- "mov epsw,%1" \
- : "=m"(*_a), "=d"(epsw) \
- : "a"(_a), "d"(1 << shift), "m"(*_a) \
- : "memory", "cc"); \
- \
- !(epsw & EPSW_FLAG_Z); \
-})
-
-#define test_and_clear_bit(nr, addr) __test_and_clear_bit((nr), (addr))
-
-/*
- * test and change bit
- */
-static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
-{
- int mask, retval;
- unsigned int *a = (unsigned int *)addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- retval = (mask & *a) != 0;
- *a ^= mask;
-
- return retval;
-}
-
-extern int test_and_change_bit(unsigned long nr, volatile void *addr);
-
-#include <asm-generic/bitops/lock.h>
-
-#ifdef __KERNEL__
-
-/**
- * __ffs - find first bit set
- * @x: the word to search
- *
- * - return 31..0 to indicate bit 31..0 most least significant bit set
- * - if no bits are set in x, the result is undefined
- */
-static inline __attribute__((const))
-unsigned long __ffs(unsigned long x)
-{
- int bit;
- asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x) : "cc");
- return bit;
-}
-
-/*
- * special slimline version of fls() for calculating ilog2_u32()
- * - note: no protection against n == 0
- */
-static inline __attribute__((const))
-int __ilog2_u32(u32 n)
-{
- int bit;
- asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n) : "cc");
- return bit;
-}
-
-/**
- * fls - find last bit set
- * @x: the word to search
- *
- * This is defined the same way as ffs:
- * - return 32..1 to indicate bit 31..0 most significant bit set
- * - return 0 to indicate no bits set
- */
-static inline __attribute__((const))
-int fls(int x)
-{
- return (x != 0) ? __ilog2_u32(x) + 1 : 0;
-}
-
-/**
- * __fls - find last (most-significant) set bit in a long word
- * @word: the word to search
- *
- * Undefined if no set bit exists, so code should check against 0 first.
- */
-static inline unsigned long __fls(unsigned long word)
-{
- return __ilog2_u32(word);
-}
-
-/**
- * ffs - find first bit set
- * @x: the word to search
- *
- * - return 32..1 to indicate bit 31..0 most least significant bit set
- * - return 0 to indicate no bits set
- */
-static inline __attribute__((const))
-int ffs(int x)
-{
- /* Note: (x & -x) gives us a mask that is the least significant
- * (rightmost) 1-bit of the value in x.
- */
- return fls(x & -x);
-}
-
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/ext2-atomic-setbit.h>
-#include <asm-generic/bitops/le.h>
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_BITOPS_H */
diff --git a/arch/mn10300/include/asm/bug.h b/arch/mn10300/include/asm/bug.h
deleted file mode 100644
index 811414fb002d..000000000000
--- a/arch/mn10300/include/asm/bug.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* MN10300 Kernel bug reporting
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_BUG_H
-#define _ASM_BUG_H
-
-#ifdef CONFIG_BUG
-
-/*
- * Tell the user there is some problem.
- */
-#define BUG() \
-do { \
- asm volatile( \
- " syscall 15 \n" \
- "0: \n" \
- " .section __bug_table,\"aw\" \n" \
- " .long 0b,%0,%1 \n" \
- " .previous \n" \
- : \
- : "i"(__FILE__), "i"(__LINE__) \
- ); \
-} while (1)
-
-#define HAVE_ARCH_BUG
-#endif /* CONFIG_BUG */
-
-#include <asm-generic/bug.h>
-
-#endif /* _ASM_BUG_H */
diff --git a/arch/mn10300/include/asm/bugs.h b/arch/mn10300/include/asm/bugs.h
deleted file mode 100644
index 31c8bc592b47..000000000000
--- a/arch/mn10300/include/asm/bugs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* MN10300 Checks for architecture-dependent bugs
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_BUGS_H
-#define _ASM_BUGS_H
-
-#include <asm/processor.h>
-
-static inline void __init check_bugs(void)
-{
-}
-
-#endif /* _ASM_BUGS_H */
diff --git a/arch/mn10300/include/asm/busctl-regs.h b/arch/mn10300/include/asm/busctl-regs.h
deleted file mode 100644
index 1632aef73401..000000000000
--- a/arch/mn10300/include/asm/busctl-regs.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* AM33v2 on-board bus controller registers
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_BUSCTL_REGS_H
-#define _ASM_BUSCTL_REGS_H
-
-#include <asm/cpu-regs.h>
-
-#ifdef __KERNEL__
-
-/* bus controller registers */
-#define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */
-#define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */
-#define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */
-#define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */
-#define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */
-#define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */
-#define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */
-#define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */
-#define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */
-#define BCCR_BxAD_EXBUS 0x0 /* - direct to system bus controller */
-#define BCCR_BxAD_OPEXBUS 0x1 /* - direct to memory bus controller */
-#define BCCR_BxAD_OCMBUS 0x2 /* - direct to on chip memory */
-#define BCCR_API 0x00070000 /* bus arbitration priority */
-#define BCCR_API_DMACICD 0x00000000 /* - DMA > CI > CD */
-#define BCCR_API_DMACDCI 0x00010000 /* - DMA > CD > CI */
-#define BCCR_API_CICDDMA 0x00020000 /* - CI > CD > DMA */
-#define BCCR_API_CDCIDMA 0x00030000 /* - CD > CI > DMA */
-#define BCCR_API_ROUNDROBIN 0x00040000 /* - round robin */
-#define BCCR_BEPRI_DMACICD 0x00c00000 /* bus error address priority */
-#define BCCR_BEPRI_DMACDCI 0x00000000 /* - DMA > CI > CD */
-#define BCCR_BEPRI_CICDDMA 0x00400000 /* - DMA > CD > CI */
-#define BCCR_BEPRI_CDCIDMA 0x00800000 /* - CI > CD > DMA */
-#define BCCR_BEPRI 0x00c00000 /* - CD > CI > DMA */
-#define BCCR_TMON 0x03000000 /* timeout value settings */
-#define BCCR_TMON_16IOCLK 0x00000000 /* - 16 IOCLK cycles */
-#define BCCR_TMON_256IOCLK 0x01000000 /* - 256 IOCLK cycles */
-#define BCCR_TMON_4096IOCLK 0x02000000 /* - 4096 IOCLK cycles */
-#define BCCR_TMON_65536IOCLK 0x03000000 /* - 65536 IOCLK cycles */
-#define BCCR_TMOE 0x10000000 /* timeout detection enable */
-
-#define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */
-#define BCBERR_BESB 0x0000001f /* erroneous access destination space */
-#define BCBERR_BESB_MON 0x00000001 /* - monitor space */
-#define BCBERR_BESB_IO 0x00000002 /* - IO bus */
-#define BCBERR_BESB_EX 0x00000004 /* - EX bus */
-#define BCBERR_BESB_OPEX 0x00000008 /* - OpEX bus */
-#define BCBERR_BESB_OCM 0x00000010 /* - on chip memory */
-#define BCBERR_BERW 0x00000100 /* type of access */
-#define BCBERR_BERW_WRITE 0x00000000 /* - write */
-#define BCBERR_BERW_READ 0x00000100 /* - read */
-#define BCBERR_BESD 0x00000200 /* error detector */
-#define BCBERR_BESD_BCU 0x00000000 /* - BCU detected error */
-#define BCBERR_BESD_SLAVE_BUS 0x00000200 /* - slave bus detected error */
-#define BCBERR_BEBST 0x00000400 /* type of access */
-#define BCBERR_BEBST_SINGLE 0x00000000 /* - single */
-#define BCBERR_BEBST_BURST 0x00000400 /* - burst */
-#define BCBERR_BEME 0x00000800 /* multiple bus error flag */
-#define BCBERR_BEMR 0x00007000 /* master bus that caused the error */
-#define BCBERR_BEMR_NOERROR 0x00000000 /* - no error */
-#define BCBERR_BEMR_CI 0x00001000 /* - CPU instruction fetch bus caused error */
-#define BCBERR_BEMR_CD 0x00002000 /* - CPU data bus caused error */
-#define BCBERR_BEMR_DMA 0x00004000 /* - DMA bus caused error */
-
-#define BCBEAR __SYSREGC(0xc0002020, u32) /* bus error address reg */
-
-/* system bus controller registers */
-#define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */
-#define SBBASE_BE 0x00000001 /* bank enable */
-#define SBBASE_BAM 0x0000fffe /* bank address mask [31:17] */
-#define SBBASE_BBA 0xfffe0000 /* bank base address [31:17] */
-
-#define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */
-#define SBCNTRL0_WEH 0x00000f00 /* write enable hold */
-#define SBCNTRL0_REH 0x0000f000 /* read enable hold */
-#define SBCNTRL0_RWH 0x000f0000 /* SRW signal hold */
-#define SBCNTRL0_CSH 0x00f00000 /* chip select hold */
-#define SBCNTRL0_DAH 0x0f000000 /* data hold */
-#define SBCNTRL0_ADH 0xf0000000 /* address hold */
-
-#define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */
-#define SBCNTRL1_WED 0x00000f00 /* write enable delay */
-#define SBCNTRL1_RED 0x0000f000 /* read enable delay */
-#define SBCNTRL1_RWD 0x000f0000 /* SRW signal delay */
-#define SBCNTRL1_ASW 0x00f00000 /* address strobe width */
-#define SBCNTRL1_CSD 0x0f000000 /* chip select delay */
-#define SBCNTRL1_ASD 0xf0000000 /* address strobe delay */
-
-#define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */
-#define SBCNTRL2_WC 0x000000ff /* wait count */
-#define SBCNTRL2_BWC 0x00000f00 /* burst wait count */
-#define SBCNTRL2_WM 0x01000000 /* wait mode setting */
-#define SBCNTRL2_WM_FIXEDWAIT 0x00000000 /* - fixed wait access */
-#define SBCNTRL2_WM_HANDSHAKE 0x01000000 /* - handshake access */
-#define SBCNTRL2_BM 0x02000000 /* bus synchronisation mode */
-#define SBCNTRL2_BM_SYNC 0x00000000 /* - synchronous mode */
-#define SBCNTRL2_BM_ASYNC 0x02000000 /* - asynchronous mode */
-#define SBCNTRL2_BW 0x04000000 /* bus width */
-#define SBCNTRL2_BW_32 0x00000000 /* - 32 bits */
-#define SBCNTRL2_BW_16 0x04000000 /* - 16 bits */
-#define SBCNTRL2_RWINV 0x08000000 /* R/W signal invert polarity */
-#define SBCNTRL2_RWINV_NORM 0x00000000 /* - normal (read high) */
-#define SBCNTRL2_RWINV_INV 0x08000000 /* - inverted (read low) */
-#define SBCNTRL2_BT 0x70000000 /* bus type setting */
-#define SBCNTRL2_BT_SRAM 0x00000000 /* - SRAM interface */
-#define SBCNTRL2_BT_ADMUX 0x00000000 /* - addr/data multiplexed interface */
-#define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */
-#define SBCNTRL2_BTSE 0x80000000 /* burst enable */
-
-/* memory bus controller */
-#define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */
-#define SDBASE_CE 0x00000001 /* chip enable */
-#define SDBASE_CBAM 0x0000fff0 /* chip base address mask [31:20] */
-#define SDBASE_CBAM_SHIFT 16
-#define SDBASE_CBA 0xfff00000 /* chip base address [31:20] */
-
-#define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */
-#define SDRAMBUS_REFEN 0x00000004 /* refresh enable */
-#define SDRAMBUS_TRC 0x00000018 /* refresh command delay time */
-#define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */
-#define SDRAMBUS_PONSEQ 0x00000040 /* power on sequence */
-#define SDRAMBUS_SELFREQ 0x00000080 /* self-refresh mode request */
-#define SDRAMBUS_SELFON 0x00000100 /* self-refresh mode on */
-#define SDRAMBUS_SIZE 0x00030000 /* SDRAM size */
-#define SDRAMBUS_SIZE_64Mbit 0x00010000 /* 64Mbit SDRAM (x16) */
-#define SDRAMBUS_SIZE_128Mbit 0x00020000 /* 128Mbit SDRAM (x16) */
-#define SDRAMBUS_SIZE_256Mbit 0x00030000 /* 256Mbit SDRAM (x16) */
-#define SDRAMBUS_TRASWAIT 0x000c0000 /* row address precharge command cycle number */
-#define SDRAMBUS_REFNUM 0x00300000 /* refresh command number */
-#define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */
-#define SDRAMBUS_SETWAIT 0x03000000 /* mode register setting command cycle */
-#define SDRAMBUS_PREWAIT 0x0c000000 /* precharge command cycle */
-#define SDRAMBUS_RASLATE 0x30000000 /* RAS latency */
-#define SDRAMBUS_CASLATE 0xc0000000 /* CAS latency */
-
-#define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */
-#define SDREFCNT_PERI 0x00000fff /* refresh period */
-
-#define SDSHDW __SYSREG(0xda000010, u32) /* test reg */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_BUSCTL_REGS_H */
diff --git a/arch/mn10300/include/asm/cache.h b/arch/mn10300/include/asm/cache.h
deleted file mode 100644
index f29cde2cfc91..000000000000
--- a/arch/mn10300/include/asm/cache.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* MN10300 cache management registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-#include <asm/cpu-regs.h>
-#include <proc/cache.h>
-
-#ifndef __ASSEMBLY__
-#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES)
-#else
-#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES
-#endif
-
-#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-
-/* data cache purge registers
- * - read from the register to unconditionally purge that cache line
- * - write address & 0xffffff00 to conditionally purge that cache line
- * - clear LSB to request invalidation as well
- */
-#define DCACHE_PURGE(WAY, ENTRY) \
- __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
- (ENTRY) * L1_CACHE_BYTES, u32)
-
-#define DCACHE_PURGE_WAY0(ENTRY) \
- __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
-#define DCACHE_PURGE_WAY1(ENTRY) \
- __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
-#define DCACHE_PURGE_WAY2(ENTRY) \
- __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
-#define DCACHE_PURGE_WAY3(ENTRY) \
- __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
-
-/* instruction cache access registers */
-#define ICACHE_DATA(WAY, ENTRY, OFF) \
- __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \
- (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
-#define ICACHE_TAG(WAY, ENTRY) \
- __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \
- (ENTRY) * L1_CACHE_BYTES, u32)
-
-/* data cache access registers */
-#define DCACHE_DATA(WAY, ENTRY, OFF) \
- __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \
- (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
-#define DCACHE_TAG(WAY, ENTRY) \
- __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \
- (ENTRY) * L1_CACHE_BYTES, u32)
-
-#endif /* _ASM_CACHE_H */
diff --git a/arch/mn10300/include/asm/cacheflush.h b/arch/mn10300/include/asm/cacheflush.h
deleted file mode 100644
index 6d6df839948f..000000000000
--- a/arch/mn10300/include/asm/cacheflush.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/* MN10300 Cache flushing
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_CACHEFLUSH_H
-#define _ASM_CACHEFLUSH_H
-
-#ifndef __ASSEMBLY__
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-
-/*
- * Primitive routines
- */
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-extern void mn10300_local_icache_inv(void);
-extern void mn10300_local_icache_inv_page(unsigned long start);
-extern void mn10300_local_icache_inv_range(unsigned long start, unsigned long end);
-extern void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size);
-extern void mn10300_local_dcache_inv(void);
-extern void mn10300_local_dcache_inv_page(unsigned long start);
-extern void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end);
-extern void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size);
-extern void mn10300_icache_inv(void);
-extern void mn10300_icache_inv_page(unsigned long start);
-extern void mn10300_icache_inv_range(unsigned long start, unsigned long end);
-extern void mn10300_icache_inv_range2(unsigned long start, unsigned long size);
-extern void mn10300_dcache_inv(void);
-extern void mn10300_dcache_inv_page(unsigned long start);
-extern void mn10300_dcache_inv_range(unsigned long start, unsigned long end);
-extern void mn10300_dcache_inv_range2(unsigned long start, unsigned long size);
-#ifdef CONFIG_MN10300_CACHE_WBACK
-extern void mn10300_local_dcache_flush(void);
-extern void mn10300_local_dcache_flush_page(unsigned long start);
-extern void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end);
-extern void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size);
-extern void mn10300_local_dcache_flush_inv(void);
-extern void mn10300_local_dcache_flush_inv_page(unsigned long start);
-extern void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end);
-extern void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size);
-extern void mn10300_dcache_flush(void);
-extern void mn10300_dcache_flush_page(unsigned long start);
-extern void mn10300_dcache_flush_range(unsigned long start, unsigned long end);
-extern void mn10300_dcache_flush_range2(unsigned long start, unsigned long size);
-extern void mn10300_dcache_flush_inv(void);
-extern void mn10300_dcache_flush_inv_page(unsigned long start);
-extern void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end);
-extern void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size);
-#else
-#define mn10300_local_dcache_flush() do {} while (0)
-#define mn10300_local_dcache_flush_page(start) do {} while (0)
-#define mn10300_local_dcache_flush_range(start, end) do {} while (0)
-#define mn10300_local_dcache_flush_range2(start, size) do {} while (0)
-#define mn10300_local_dcache_flush_inv() \
- mn10300_local_dcache_inv()
-#define mn10300_local_dcache_flush_inv_page(start) \
- mn10300_local_dcache_inv_page(start)
-#define mn10300_local_dcache_flush_inv_range(start, end) \
- mn10300_local_dcache_inv_range(start, end)
-#define mn10300_local_dcache_flush_inv_range2(start, size) \
- mn10300_local_dcache_inv_range2(start, size)
-#define mn10300_dcache_flush() do {} while (0)
-#define mn10300_dcache_flush_page(start) do {} while (0)
-#define mn10300_dcache_flush_range(start, end) do {} while (0)
-#define mn10300_dcache_flush_range2(start, size) do {} while (0)
-#define mn10300_dcache_flush_inv() mn10300_dcache_inv()
-#define mn10300_dcache_flush_inv_page(start) \
- mn10300_dcache_inv_page((start))
-#define mn10300_dcache_flush_inv_range(start, end) \
- mn10300_dcache_inv_range((start), (end))
-#define mn10300_dcache_flush_inv_range2(start, size) \
- mn10300_dcache_inv_range2((start), (size))
-#endif /* CONFIG_MN10300_CACHE_WBACK */
-#else
-#define mn10300_local_icache_inv() do {} while (0)
-#define mn10300_local_icache_inv_page(start) do {} while (0)
-#define mn10300_local_icache_inv_range(start, end) do {} while (0)
-#define mn10300_local_icache_inv_range2(start, size) do {} while (0)
-#define mn10300_local_dcache_inv() do {} while (0)
-#define mn10300_local_dcache_inv_page(start) do {} while (0)
-#define mn10300_local_dcache_inv_range(start, end) do {} while (0)
-#define mn10300_local_dcache_inv_range2(start, size) do {} while (0)
-#define mn10300_local_dcache_flush() do {} while (0)
-#define mn10300_local_dcache_flush_inv_page(start) do {} while (0)
-#define mn10300_local_dcache_flush_inv() do {} while (0)
-#define mn10300_local_dcache_flush_inv_range(start, end)do {} while (0)
-#define mn10300_local_dcache_flush_inv_range2(start, size) do {} while (0)
-#define mn10300_local_dcache_flush_page(start) do {} while (0)
-#define mn10300_local_dcache_flush_range(start, end) do {} while (0)
-#define mn10300_local_dcache_flush_range2(start, size) do {} while (0)
-#define mn10300_icache_inv() do {} while (0)
-#define mn10300_icache_inv_page(start) do {} while (0)
-#define mn10300_icache_inv_range(start, end) do {} while (0)
-#define mn10300_icache_inv_range2(start, size) do {} while (0)
-#define mn10300_dcache_inv() do {} while (0)
-#define mn10300_dcache_inv_page(start) do {} while (0)
-#define mn10300_dcache_inv_range(start, end) do {} while (0)
-#define mn10300_dcache_inv_range2(start, size) do {} while (0)
-#define mn10300_dcache_flush() do {} while (0)
-#define mn10300_dcache_flush_inv_page(start) do {} while (0)
-#define mn10300_dcache_flush_inv() do {} while (0)
-#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)
-#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)
-#define mn10300_dcache_flush_page(start) do {} while (0)
-#define mn10300_dcache_flush_range(start, end) do {} while (0)
-#define mn10300_dcache_flush_range2(start, size) do {} while (0)
-#endif /* CONFIG_MN10300_CACHE_ENABLED */
-
-/*
- * Virtually-indexed cache management (our cache is physically indexed)
- */
-#define flush_cache_all() do {} while (0)
-#define flush_cache_mm(mm) do {} while (0)
-#define flush_cache_dup_mm(mm) do {} while (0)
-#define flush_cache_range(mm, start, end) do {} while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
-#define flush_cache_vmap(start, end) do {} while (0)
-#define flush_cache_vunmap(start, end) do {} while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do {} while (0)
-#define flush_dcache_mmap_lock(mapping) do {} while (0)
-#define flush_dcache_mmap_unlock(mapping) do {} while (0)
-
-/*
- * Physically-indexed cache management
- */
-#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE)
-extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
-extern void flush_icache_range(unsigned long start, unsigned long end);
-#elif defined(CONFIG_MN10300_CACHE_INV_ICACHE)
-static inline void flush_icache_page(struct vm_area_struct *vma,
- struct page *page)
-{
- mn10300_icache_inv_page(page_to_phys(page));
-}
-extern void flush_icache_range(unsigned long start, unsigned long end);
-#else
-#define flush_icache_range(start, end) do {} while (0)
-#define flush_icache_page(vma, pg) do {} while (0)
-#endif
-
-
-#define flush_icache_user_range(vma, pg, adr, len) \
- flush_icache_range(adr, adr + len)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
- do { \
- memcpy(dst, src, len); \
- flush_icache_page(vma, page); \
- } while (0)
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_CACHEFLUSH_H */
diff --git a/arch/mn10300/include/asm/checksum.h b/arch/mn10300/include/asm/checksum.h
deleted file mode 100644
index c80df5b504ac..000000000000
--- a/arch/mn10300/include/asm/checksum.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* MN10300 Optimised checksumming code
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_CHECKSUM_H
-#define _ASM_CHECKSUM_H
-
-extern __wsum csum_partial(const void *buff, int len, __wsum sum);
-extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum);
-extern __wsum csum_partial_copy_from_user(const void *src, void *dst,
- int len, __wsum sum,
- int *err_ptr);
-extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-extern __wsum csum_partial(const void *buff, int len, __wsum sum);
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#define csum_partial_copy_fromuser csum_partial_copy
-extern __wsum csum_partial_copy(const void *src, void *dst, int len,
- __wsum sum);
-
-static inline __sum16 csum_fold(__wsum sum)
-{
- asm(
- " add %1,%0 \n"
- " addc 0xffff,%0 \n"
- : "=r" (sum)
- : "r" (sum << 16), "0" (sum & 0xffff0000)
- : "cc"
- );
- return (~sum) >> 16;
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- __wsum tmp = (__wsum)((len + proto) << 8);
-
- asm(
- " add %1,%0 \n"
- " addc %2,%0 \n"
- " addc %3,%0 \n"
- " addc 0,%0 \n"
- : "=r" (sum)
- : "r" (daddr), "r"(saddr), "r"(tmp), "0"(sum)
- : "cc"
- );
- return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
- __u32 len, __u8 proto,
- __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-#undef _HAVE_ARCH_IPV6_CSUM
-
-/*
- * Copy and checksum to user
- */
-#define HAVE_CSUM_COPY_USER
-extern __wsum csum_and_copy_to_user(const void *src, void *dst, int len,
- __wsum sum, int *err_ptr);
-
-
-#endif /* _ASM_CHECKSUM_H */
diff --git a/arch/mn10300/include/asm/cmpxchg.h b/arch/mn10300/include/asm/cmpxchg.h
deleted file mode 100644
index 97a4aaf387a6..000000000000
--- a/arch/mn10300/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* MN10300 Atomic xchg/cmpxchg operations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_CMPXCHG_H
-#define _ASM_CMPXCHG_H
-
-#include <asm/irqflags.h>
-
-#ifdef CONFIG_SMP
-#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
-static inline
-unsigned long __xchg(volatile unsigned long *m, unsigned long val)
-{
- unsigned long status;
- unsigned long oldval;
-
- asm volatile(
- "1: mov %4,(_AAR,%3) \n"
- " mov (_ADR,%3),%1 \n"
- " mov %5,(_ADR,%3) \n"
- " mov (_ADR,%3),%0 \n" /* flush */
- " mov (_ASR,%3),%0 \n"
- " or %0,%0 \n"
- " bne 1b \n"
- : "=&r"(status), "=&r"(oldval), "=m"(*m)
- : "a"(ATOMIC_OPS_BASE_ADDR), "r"(m), "r"(val)
- : "memory", "cc");
-
- return oldval;
-}
-
-static inline unsigned long __cmpxchg(volatile unsigned long *m,
- unsigned long old, unsigned long new)
-{
- unsigned long status;
- unsigned long oldval;
-
- asm volatile(
- "1: mov %4,(_AAR,%3) \n"
- " mov (_ADR,%3),%1 \n"
- " cmp %5,%1 \n"
- " bne 2f \n"
- " mov %6,(_ADR,%3) \n"
- "2: mov (_ADR,%3),%0 \n" /* flush */
- " mov (_ASR,%3),%0 \n"
- " or %0,%0 \n"
- " bne 1b \n"
- : "=&r"(status), "=&r"(oldval), "=m"(*m)
- : "a"(ATOMIC_OPS_BASE_ADDR), "r"(m),
- "r"(old), "r"(new)
- : "memory", "cc");
-
- return oldval;
-}
-#else /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
-#error "No SMP atomic operation support!"
-#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
-
-#else /* CONFIG_SMP */
-
-/*
- * Emulate xchg for non-SMP MN10300
- */
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
-static inline
-unsigned long __xchg(volatile unsigned long *m, unsigned long val)
-{
- unsigned long oldval;
- unsigned long flags;
-
- flags = arch_local_cli_save();
- oldval = *m;
- *m = val;
- arch_local_irq_restore(flags);
- return oldval;
-}
-
-/*
- * Emulate cmpxchg for non-SMP MN10300
- */
-static inline unsigned long __cmpxchg(volatile unsigned long *m,
- unsigned long old, unsigned long new)
-{
- unsigned long oldval;
- unsigned long flags;
-
- flags = arch_local_cli_save();
- oldval = *m;
- if (oldval == old)
- *m = new;
- arch_local_irq_restore(flags);
- return oldval;
-}
-
-#endif /* CONFIG_SMP */
-
-#define xchg(ptr, v) \
- ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
- (unsigned long)(v)))
-
-#define cmpxchg(ptr, o, n) \
- ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
- (unsigned long)(o), \
- (unsigned long)(n)))
-
-#endif /* _ASM_CMPXCHG_H */
diff --git a/arch/mn10300/include/asm/cpu-regs.h b/arch/mn10300/include/asm/cpu-regs.h
deleted file mode 100644
index c54effae2202..000000000000
--- a/arch/mn10300/include/asm/cpu-regs.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/* MN10300 Core system registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_CPU_REGS_H
-#define _ASM_CPU_REGS_H
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-
-/* we tell the compiler to pretend to be AM33 so that it doesn't try and use
- * the FP regs, but tell the assembler that we're actually allowed AM33v2
- * instructions */
-#ifndef __ASSEMBLY__
-asm(" .am33_2\n");
-#else
-.am33_2
-#endif
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR))
-#define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR))
-#else
-#define __SYSREG(ADDR, TYPE) ADDR
-#define __SYSREGC(ADDR, TYPE) ADDR
-#endif
-
-/* CPU registers */
-#define EPSW_FLAG_Z 0x00000001 /* zero flag */
-#define EPSW_FLAG_N 0x00000002 /* negative flag */
-#define EPSW_FLAG_C 0x00000004 /* carry flag */
-#define EPSW_FLAG_V 0x00000008 /* overflow flag */
-#define EPSW_IM 0x00000700 /* interrupt mode */
-#define EPSW_IM_0 0x00000000 /* interrupt mode 0 */
-#define EPSW_IM_1 0x00000100 /* interrupt mode 1 */
-#define EPSW_IM_2 0x00000200 /* interrupt mode 2 */
-#define EPSW_IM_3 0x00000300 /* interrupt mode 3 */
-#define EPSW_IM_4 0x00000400 /* interrupt mode 4 */
-#define EPSW_IM_5 0x00000500 /* interrupt mode 5 */
-#define EPSW_IM_6 0x00000600 /* interrupt mode 6 */
-#define EPSW_IM_7 0x00000700 /* interrupt mode 7 */
-#define EPSW_IE 0x00000800 /* interrupt enable */
-#define EPSW_S 0x00003000 /* software auxiliary bits */
-#define EPSW_T 0x00008000 /* trace enable */
-#define EPSW_nSL 0x00010000 /* not supervisor level */
-#define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */
-#define EPSW_nAR 0x00040000 /* register bank control */
-#define EPSW_ML 0x00080000 /* monitor level */
-#define EPSW_FE 0x00100000 /* FPU enable */
-#define EPSW_IM_SHIFT 8 /* EPSW_IM_SHIFT determines the interrupt mode */
-
-#define NUM2EPSW_IM(num) ((num) << EPSW_IM_SHIFT)
-
-/* FPU registers */
-#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */
-#define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */
-#define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */
-#define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */
-#define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */
-#define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */
-#define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */
-#define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */
-#define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */
-#define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */
-#define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */
-#define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */
-#define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */
-#define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */
-#define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */
-#define FPCR_RM 0x00030000 /* rounding mode */
-#define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */
-#define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */
-#define FPCR_FCC_E 0x00080000 /* FPU equal condition code */
-#define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */
-#define FPCR_FCC_L 0x00200000 /* FPU less than condition code */
-#define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */
-
-/* CPU control registers */
-#define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
-#define CPUP_DWBD 0x0020 /* write buffer disable flag */
-#define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */
-#define CPUP_EXM 0x0080 /* exception operation mode */
-#define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */
-#define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */
-
-#define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
-#define CPUM_SLEEP 0x0004 /* set to enter sleep state */
-#define CPUM_HALT 0x0008 /* set to enter halt state */
-#define CPUM_STOP 0x0010 /* set to enter stop state */
-
-#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */
-#define CPUREV_TYPE 0x0000000f /* CPU type */
-#define CPUREV_TYPE_S 0
-#define CPUREV_TYPE_AM33_1 0x00000000 /* - AM33-1 core, AM33/1.00 arch */
-#define CPUREV_TYPE_AM33_2 0x00000001 /* - AM33-2 core, AM33/2.00 arch */
-#define CPUREV_TYPE_AM34_1 0x00000002 /* - AM34-1 core, AM33/2.00 arch */
-#define CPUREV_TYPE_AM33_3 0x00000003 /* - AM33-3 core, AM33/2.00 arch */
-#define CPUREV_TYPE_AM34_2 0x00000004 /* - AM34-2 core, AM33/3.00 arch */
-#define CPUREV_REVISION 0x000000f0 /* CPU revision */
-#define CPUREV_REVISION_S 4
-#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */
-#define CPUREV_ICWAY_S 8
-#define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */
-#define CPUREV_ICSIZE_S 12
-#define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */
-#define CPUREV_DCWAY_S 16
-#define CPUREV_DCSIZE 0x00f00000 /* data cache way size */
-#define CPUREV_DCSIZE_S 20
-#define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */
-#define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */
-#define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */
-
-#define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
-
-/* interrupt/exception control registers */
-#define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
-#define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
-#define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
-#define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
-#define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
-#define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */
-#define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */
-
-#define TBR __SYSREG(0xc0000024, u32) /* Trap table base */
-#define TBR_TB 0xff000000 /* table base address bits 31-24 */
-#define TBR_INT_CODE 0x00ffffff /* interrupt code */
-
-#define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */
-
-#define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */
-#define sISR_IRQICE 0x00000001 /* ICE interrupt */
-#define sISR_ISTEP 0x00000002 /* single step interrupt */
-#define sISR_MISSA 0x00000004 /* memory access address misalignment fault */
-#define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */
-#define sISR_PIEXE 0x00000010 /* program interrupt */
-#define sISR_MEMERR 0x00000020 /* illegal memory access fault */
-#define sISR_IBREAK 0x00000040 /* instraction break interrupt */
-#define sISR_DBSRL 0x00000080 /* debug serial interrupt */
-#define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */
-#define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */
-#define sISR_OBREAK 0x00000400 /* operand break interrupt */
-#define sISR_PRIV 0x00000800 /* privileged instruction execution fault */
-#define sISR_BUSERR 0x00001000 /* bus error fault */
-#define sISR_DBLFT 0x00002000 /* double fault */
-#define sISR_DBG 0x00008000 /* debug reserved interrupt */
-#define sISR_ITMISS 0x00010000 /* instruction TLB miss */
-#define sISR_DTMISS 0x00020000 /* data TLB miss */
-#define sISR_ITEX 0x00040000 /* instruction TLB access exception */
-#define sISR_DTEX 0x00080000 /* data TLB access exception */
-#define sISR_ILGIA 0x00100000 /* illegal instruction access exception */
-#define sISR_ILGDA 0x00200000 /* illegal data access exception */
-#define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */
-#define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */
-#define sISR_PRIDA 0x01000000 /* privileged space data access excep */
-#define sISR_DISA 0x02000000 /* data space instruction access excep */
-#define sISR_SYSC 0x04000000 /* system call instruction excep */
-#define sISR_FPUD 0x08000000 /* FPU disabled excep */
-#define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */
-#define sISR_FPUOP 0x20000000 /* FPU operation excep */
-#define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */
-
-/* cache control registers */
-#define CHCTR __SYSREG(0xc0000070, u16) /* cache control */
-#define CHCTR_ICEN 0x0001 /* instruction cache enable */
-#define CHCTR_DCEN 0x0002 /* data cache enable */
-#define CHCTR_ICBUSY 0x0004 /* instruction cache busy */
-#define CHCTR_DCBUSY 0x0008 /* data cache busy */
-#define CHCTR_ICINV 0x0010 /* instruction cache invalidate */
-#define CHCTR_DCINV 0x0020 /* data cache invalidate */
-#define CHCTR_DCWTMD 0x0040 /* data cache writing mode */
-#define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */
-#define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */
-#define CHCTR_DCALMD 0x0080 /* data cache allocation mode */
-#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */
-#define CHCTR_DCWMD 0xf000 /* data cache way mode */
-
-#ifdef CONFIG_AM34_2
-#define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */
-#define ICIVCR_ICIVBSY 0x00000008 /* icache area invalidate busy */
-#define ICIVCR_ICI 0x00000001 /* icache area invalidate */
-
-#define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */
-
-#define DCPGCR __SYSREG(0xc0000c10, u32) /* data cache area purge control */
-#define DCPGCR_DCPGBSY 0x00000008 /* data cache area purge busy */
-#define DCPGCR_DCP 0x00000002 /* data cache area purge */
-#define DCPGCR_DCI 0x00000001 /* data cache area invalidate */
-
-#define DCPGMR __SYSREG(0xc0000c14, u32) /* data cache area purge mask */
-#endif /* CONFIG_AM34_2 */
-
-/* MMU control registers */
-#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
-#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */
-#define MMUCTR_ITE 0x00000040 /* instruction TLB enable */
-#define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */
-#define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */
-#define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */
-#define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */
-#define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */
-#define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */
-#define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */
-#define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */
-#define MMUCTR_CE 0x00008000 /* cacheable bit enable */
-#define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */
-#define MMUCTR_DTE 0x00400000 /* data TLB enable */
-#define MMUCTR_DIV 0x00800000 /* data TLB invalidate */
-#define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */
-#define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */
-#define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */
-#define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */
-#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */
-#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */
-#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */
-#ifdef CONFIG_AM34_2
-#define MMUCTR_WTE 0x80000000 /* write-through cache TLB entry bit enable */
-#endif
-
-#define PIDR __SYSREG(0xc0000094, u16) /* PID register */
-#define PIDR_PID 0x00ff /* process identifier */
-
-#define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */
-
-#define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */
-#define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */
-#define xPTEL_V 0x00000001 /* TLB entry valid */
-#define xPTEL_UNUSED1 0x00000002 /* unused bit */
-#define xPTEL_UNUSED2 0x00000004 /* unused bit */
-#define xPTEL_C 0x00000008 /* cached if set */
-#define xPTEL_PV 0x00000010 /* page valid */
-#define xPTEL_D 0x00000020 /* dirty */
-#define xPTEL_PR 0x000001c0 /* page protection */
-#define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */
-#define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */
-#define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */
-#define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */
-#define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */
-#define xPTEL_G 0x00000200 /* global (use PID if 0) */
-#define xPTEL_PS 0x00000c00 /* page size */
-#define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */
-#define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */
-#define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */
-#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */
-#define xPTEL_PPN 0xfffff006 /* physical page number */
-
-#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
-#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
-#define xPTEU_VPN 0xfffffc00 /* virtual page number */
-#define xPTEU_PID 0x000000ff /* process identifier to which applicable */
-
-#define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */
-#define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */
-#define xPTEL2_V 0x00000001 /* TLB entry valid */
-#define xPTEL2_C 0x00000002 /* cacheable */
-#define xPTEL2_PV 0x00000004 /* page valid */
-#define xPTEL2_D 0x00000008 /* dirty */
-#define xPTEL2_PR 0x00000070 /* page protection */
-#define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */
-#define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */
-#define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */
-#define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */
-#define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */
-#define xPTEL2_G 0x00000080 /* global (use PID if 0) */
-#define xPTEL2_PS 0x00000300 /* page size */
-#define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */
-#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */
-#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */
-#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */
-#define xPTEL2_CWT 0x00000400 /* cacheable write-through */
-#define xPTEL2_UNUSED1 0x00000800 /* unused bit (broadcast mask) */
-#define xPTEL2_PPN 0xfffff000 /* physical page number */
-
-#define xPTEL2_V_BIT 0 /* bit numbers corresponding to above masks */
-#define xPTEL2_C_BIT 1
-#define xPTEL2_PV_BIT 2
-#define xPTEL2_D_BIT 3
-#define xPTEL2_G_BIT 7
-#define xPTEL2_UNUSED1_BIT 11
-
-#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
-#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
-#define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */
-#define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */
-#define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */
-#define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */
-#define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */
-#define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */
-#define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */
-#define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */
-#define MMUFCR_xFC_TYPE 0x0020 /* access type flag */
-#define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */
-#define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */
-#define MMUFCR_xFC_PR 0x01c0 /* page protection flag */
-#define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */
-#define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */
-#define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */
-#define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */
-#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */
-#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */
-
-#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
-/* atomic operation registers */
-#define AAR __SYSREG(0xc0000a00, u32) /* cacheable address */
-#define AAR2 __SYSREG(0xc0000a04, u32) /* uncacheable address */
-#define ADR __SYSREG(0xc0000a08, u32) /* data */
-#define ASR __SYSREG(0xc0000a0c, u32) /* status */
-#define AARU __SYSREG(0xd400aa00, u32) /* user address */
-#define ADRU __SYSREG(0xd400aa08, u32) /* user data */
-#define ASRU __SYSREG(0xd400aa0c, u32) /* user status */
-
-#define ASR_RW 0x00000008 /* read */
-#define ASR_BW 0x00000004 /* bus error */
-#define ASR_IW 0x00000002 /* interrupt */
-#define ASR_LW 0x00000001 /* bus lock */
-
-#define ASRU_RW ASR_RW /* read */
-#define ASRU_BW ASR_BW /* bus error */
-#define ASRU_IW ASR_IW /* interrupt */
-#define ASRU_LW ASR_LW /* bus lock */
-
-/* in inline ASM, we stick the base pointer in to a reg and use offsets from
- * it */
-#define ATOMIC_OPS_BASE_ADDR 0xc0000a00
-#ifndef __ASSEMBLY__
-asm(
- "_AAR = 0\n"
- "_AAR2 = 4\n"
- "_ADR = 8\n"
- "_ASR = 12\n");
-#else
-#define _AAR 0
-#define _AAR2 4
-#define _ADR 8
-#define _ASR 12
-#endif
-
-/* physical page address for userspace atomic operations registers */
-#define USER_ATOMIC_OPS_PAGE_ADDR 0xd400a000
-
-#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_CPU_REGS_H */
diff --git a/arch/mn10300/include/asm/current.h b/arch/mn10300/include/asm/current.h
deleted file mode 100644
index ca6027d83743..000000000000
--- a/arch/mn10300/include/asm/current.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* MN10300 Current task structure accessor
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_CURRENT_H
-#define _ASM_CURRENT_H
-
-#include <linux/thread_info.h>
-
-/*
- * dedicate E2 to keeping the current task pointer
- */
-#ifdef CONFIG_MN10300_CURRENT_IN_E2
-
-register struct task_struct *const current asm("e2") __attribute__((used));
-
-#define get_current() current
-
-extern struct task_struct *__current;
-
-#else
-static inline __attribute__((const))
-struct task_struct *get_current(void)
-{
- return current_thread_info()->task;
-}
-
-#define current get_current()
-#endif
-
-#endif /* _ASM_CURRENT_H */
diff --git a/arch/mn10300/include/asm/debugger.h b/arch/mn10300/include/asm/debugger.h
deleted file mode 100644
index e1d3b083696c..000000000000
--- a/arch/mn10300/include/asm/debugger.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Kernel debugger for MN10300
- *
- * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_DEBUGGER_H
-#define _ASM_DEBUGGER_H
-
-#if defined(CONFIG_KERNEL_DEBUGGER)
-
-extern int debugger_intercept(enum exception_code, int, int, struct pt_regs *);
-extern int at_debugger_breakpoint(struct pt_regs *);
-
-#ifndef CONFIG_MN10300_DEBUGGER_CACHE_NO_FLUSH
-extern void debugger_local_cache_flushinv(void);
-extern void debugger_local_cache_flushinv_one(u8 *);
-#else
-static inline void debugger_local_cache_flushinv(void) {}
-static inline void debugger_local_cache_flushinv_one(u8 *addr) {}
-#endif
-
-#else /* CONFIG_KERNEL_DEBUGGER */
-
-static inline int debugger_intercept(enum exception_code excep,
- int signo, int si_code,
- struct pt_regs *regs)
-{
- return 0;
-}
-
-static inline int at_debugger_breakpoint(struct pt_regs *regs)
-{
- return 0;
-}
-
-#endif /* CONFIG_KERNEL_DEBUGGER */
-#endif /* _ASM_DEBUGGER_H */
diff --git a/arch/mn10300/include/asm/delay.h b/arch/mn10300/include/asm/delay.h
deleted file mode 100644
index 34517b359399..000000000000
--- a/arch/mn10300/include/asm/delay.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* MN10300 Uninterruptible delay routines
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_DELAY_H
-#define _ASM_DELAY_H
-
-extern void __udelay(unsigned long usecs);
-extern void __delay(unsigned long loops);
-
-#define udelay(n) __udelay(n)
-
-#endif /* _ASM_DELAY_H */
diff --git a/arch/mn10300/include/asm/div64.h b/arch/mn10300/include/asm/div64.h
deleted file mode 100644
index 503efab2a516..000000000000
--- a/arch/mn10300/include/asm/div64.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* MN10300 64-bit division
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_DIV64
-#define _ASM_DIV64
-
-#include <linux/types.h>
-
-extern void ____unhandled_size_in_do_div___(void);
-
-/*
- * Beginning with gcc 4.6, the MDR register is represented explicitly. We
- * must, therefore, at least explicitly clobber the register when we make
- * changes to it. The following assembly fragments *could* be rearranged in
- * order to leave the moves to/from the MDR register to the compiler, but the
- * gains would be minimal at best.
- */
-#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
-# define CLOBBER_MDR_CC "mdr", "cc"
-#else
-# define CLOBBER_MDR_CC "cc"
-#endif
-
-/*
- * divide n by base, leaving the result in n and returning the remainder
- * - we can do this quite efficiently on the MN10300 by cascading the divides
- * through the MDR register
- */
-#define do_div(n, base) \
-({ \
- unsigned __rem = 0; \
- if (sizeof(n) <= 4) { \
- asm("mov %1,mdr \n" \
- "divu %2,%0 \n" \
- "mov mdr,%1 \n" \
- : "+r"(n), "=d"(__rem) \
- : "r"(base), "1"(__rem) \
- : CLOBBER_MDR_CC \
- ); \
- } else if (sizeof(n) <= 8) { \
- union { \
- unsigned long long l; \
- u32 w[2]; \
- } __quot; \
- __quot.l = n; \
- asm("mov %0,mdr \n" /* MDR = 0 */ \
- "divu %3,%1 \n" \
- /* __quot.MSL = __div.MSL / base, */ \
- /* MDR = MDR:__div.MSL % base */ \
- "divu %3,%2 \n" \
- /* __quot.LSL = MDR:__div.LSL / base, */ \
- /* MDR = MDR:__div.LSL % base */ \
- "mov mdr,%0 \n" \
- : "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \
- : "r"(base), "0"(__rem), "1"(__quot.w[1]), \
- "2"(__quot.w[0]) \
- : CLOBBER_MDR_CC \
- ); \
- n = __quot.l; \
- } else { \
- ____unhandled_size_in_do_div___(); \
- } \
- __rem; \
-})
-
-/*
- * do an unsigned 32-bit multiply and divide with intermediate 64-bit product
- * so as not to lose accuracy
- * - we use the MDR register to hold the MSW of the product
- */
-static inline __attribute__((const))
-unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div)
-{
- unsigned result;
-
- asm("mulu %2,%0 \n" /* MDR:val = val*mult */
- "divu %3,%0 \n" /* val = MDR:val/div;
- * MDR = MDR:val%div */
- : "=r"(result)
- : "0"(val), "ir"(mult), "r"(div)
- : CLOBBER_MDR_CC
- );
-
- return result;
-}
-
-/*
- * do a signed 32-bit multiply and divide with intermediate 64-bit product so
- * as not to lose accuracy
- * - we use the MDR register to hold the MSW of the product
- */
-static inline __attribute__((const))
-signed __muldiv64s(signed val, signed mult, signed div)
-{
- signed result;
-
- asm("mul %2,%0 \n" /* MDR:val = val*mult */
- "div %3,%0 \n" /* val = MDR:val/div;
- * MDR = MDR:val%div */
- : "=r"(result)
- : "0"(val), "ir"(mult), "r"(div)
- : CLOBBER_MDR_CC
- );
-
- return result;
-}
-
-#endif /* _ASM_DIV64 */
diff --git a/arch/mn10300/include/asm/dma-mapping.h b/arch/mn10300/include/asm/dma-mapping.h
deleted file mode 100644
index 439e474ed6d7..000000000000
--- a/arch/mn10300/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* DMA mapping routines for the MN10300 arch
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_DMA_MAPPING_H
-#define _ASM_DMA_MAPPING_H
-
-extern const struct dma_map_ops mn10300_dma_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return &mn10300_dma_ops;
-}
-
-#endif
diff --git a/arch/mn10300/include/asm/dma.h b/arch/mn10300/include/asm/dma.h
deleted file mode 100644
index 10b77d4628c2..000000000000
--- a/arch/mn10300/include/asm/dma.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* MN10300 ISA DMA handlers and definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <linux/spinlock.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#undef MAX_DMA_CHANNELS /* switch off linux/kernel/dma.c */
-#define MAX_DMA_ADDRESS 0xbfffffff
-
-extern spinlock_t dma_spin_lock;
-
-static inline unsigned long claim_dma_lock(void)
-{
- unsigned long flags;
- spin_lock_irqsave(&dma_spin_lock, flags);
- return flags;
-}
-
-static inline void release_dma_lock(unsigned long flags)
-{
- spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static inline void enable_dma(unsigned int dmanr)
-{
-}
-
-static inline void disable_dma(unsigned int dmanr)
-{
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static inline void clear_dma_ff(unsigned int dmanr)
-{
-}
-
-/* set mode (above) for a specific DMA channel */
-static inline void set_dma_mode(unsigned int dmanr, char mode)
-{
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static inline void set_dma_page(unsigned int dmanr, char pagenr)
-{
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static inline void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static inline int get_dma_residue(unsigned int dmanr)
-{
- return 0;
-}
-
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char *device_id);
-extern void free_dma(unsigned int dmanr);
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy (0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/arch/mn10300/include/asm/dmactl-regs.h b/arch/mn10300/include/asm/dmactl-regs.h
deleted file mode 100644
index 80337b339c90..000000000000
--- a/arch/mn10300/include/asm/dmactl-regs.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* MN10300 on-board DMA controller registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_DMACTL_REGS_H
-#define _ASM_DMACTL_REGS_H
-
-#include <proc/dmactl-regs.h>
-
-#endif /* _ASM_DMACTL_REGS_H */
diff --git a/arch/mn10300/include/asm/elf.h b/arch/mn10300/include/asm/elf.h
deleted file mode 100644
index f592d7a9f032..000000000000
--- a/arch/mn10300/include/asm/elf.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* MN10300 ELF constant and register definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_ELF_H
-#define _ASM_ELF_H
-
-#include <linux/utsname.h>
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/*
- * AM33 relocations
- */
-#define R_MN10300_NONE 0 /* No reloc. */
-#define R_MN10300_32 1 /* Direct 32 bit. */
-#define R_MN10300_16 2 /* Direct 16 bit. */
-#define R_MN10300_8 3 /* Direct 8 bit. */
-#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */
-#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */
-#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */
-#define R_MN10300_24 9 /* Direct 24 bit. */
-#define R_MN10300_RELATIVE 23 /* Adjust by program base. */
-#define R_MN10300_SYM_DIFF 33 /* Adjustment when relaxing. */
-#define R_MN10300_ALIGN 34 /* Alignment requirement. */
-
-/*
- * AM33/AM34 HW Capabilities
- */
-#define HWCAP_MN10300_ATOMIC_OP_UNIT 1 /* Has AM34 Atomic Operations */
-
-
-/*
- * ELF register definitions..
- */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG ((sizeof(struct pt_regs) / sizeof(elf_greg_t)) - 1)
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-#define ELF_NFPREG 32
-typedef float elf_fpreg_t;
-
-typedef struct {
- elf_fpreg_t fpregs[ELF_NFPREG];
- u_int32_t fpcr;
-} elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture
- */
-#define elf_check_arch(x) \
- (((x)->e_machine == EM_CYGNUS_MN10300) || \
- ((x)->e_machine == EM_MN10300))
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_MN10300
-
-/*
- * ELF process initialiser
- */
-#define ELF_PLAT_INIT(_r, load_addr) \
-do { \
- struct pt_regs *_ur = current->thread.uregs; \
- _ur->a3 = 0; _ur->a2 = 0; _ur->d3 = 0; _ur->d2 = 0; \
- _ur->mcvf = 0; _ur->mcrl = 0; _ur->mcrh = 0; _ur->mdrq = 0; \
- _ur->e1 = 0; _ur->e0 = 0; _ur->e7 = 0; _ur->e6 = 0; \
- _ur->e5 = 0; _ur->e4 = 0; _ur->e3 = 0; _ur->e2 = 0; \
- _ur->lar = 0; _ur->lir = 0; _ur->mdr = 0; \
- _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \
-} while (0)
-
-#define CORE_DUMP_USE_REGSET
-#define ELF_EXEC_PAGESIZE 4096
-
-/*
- * This is the location that an ET_DYN program is loaded if exec'ed. Typical
- * use of this is to invoke "./ld.so someprog" to test out a new version of
- * the loader. We need to make sure that it is out of the way of the program
- * that it will "exec", and that there is sufficient room for the brk.
- * - must clear the VMALLOC area
- */
-#define ELF_ET_DYN_BASE 0x04000000
-
-/*
- * regs is struct pt_regs, pr_reg is elf_gregset_t (which is
- * now struct user_regs, they are different)
- * - ELF_CORE_COPY_REGS has been guessed, and may be wrong
- */
-#define ELF_CORE_COPY_REGS(pr_reg, regs) \
-do { \
- pr_reg[0] = regs->a3; \
- pr_reg[1] = regs->a2; \
- pr_reg[2] = regs->d3; \
- pr_reg[3] = regs->d2; \
- pr_reg[4] = regs->mcvf; \
- pr_reg[5] = regs->mcrl; \
- pr_reg[6] = regs->mcrh; \
- pr_reg[7] = regs->mdrq; \
- pr_reg[8] = regs->e1; \
- pr_reg[9] = regs->e0; \
- pr_reg[10] = regs->e7; \
- pr_reg[11] = regs->e6; \
- pr_reg[12] = regs->e5; \
- pr_reg[13] = regs->e4; \
- pr_reg[14] = regs->e3; \
- pr_reg[15] = regs->e2; \
- pr_reg[16] = regs->sp; \
- pr_reg[17] = regs->lar; \
- pr_reg[18] = regs->lir; \
- pr_reg[19] = regs->mdr; \
- pr_reg[20] = regs->a1; \
- pr_reg[21] = regs->a0; \
- pr_reg[22] = regs->d1; \
- pr_reg[23] = regs->d0; \
- pr_reg[24] = regs->orig_d0; \
- pr_reg[25] = regs->epsw; \
- pr_reg[26] = regs->pc; \
-} while (0);
-
-/*
- * This yields a mask that user programs can use to figure out what
- * instruction set this CPU supports. This could be done in user space,
- * but it's not easy, and we've already done it here.
- */
-#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
-#define ELF_HWCAP (HWCAP_MN10300_ATOMIC_OP_UNIT)
-#else
-#define ELF_HWCAP (0)
-#endif
-
-/*
- * This yields a string that ld.so will use to load implementation
- * specific libraries for optimization. This is more specific in
- * intent than poking at uname or /proc/cpuinfo.
- *
- * For the moment, we have only optimizations for the Intel generations,
- * but that could change...
- */
-#define ELF_PLATFORM (NULL)
-
-#endif /* _ASM_ELF_H */
diff --git a/arch/mn10300/include/asm/emergency-restart.h b/arch/mn10300/include/asm/emergency-restart.h
deleted file mode 100644
index 3711bd9d50bd..000000000000
--- a/arch/mn10300/include/asm/emergency-restart.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/emergency-restart.h>
diff --git a/arch/mn10300/include/asm/exceptions.h b/arch/mn10300/include/asm/exceptions.h
deleted file mode 100644
index 95a4d42c3a06..000000000000
--- a/arch/mn10300/include/asm/exceptions.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* MN10300 Microcontroller core exceptions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_EXCEPTIONS_H
-#define _ASM_EXCEPTIONS_H
-
-#include <linux/linkage.h>
-
-/*
- * define the breakpoint instruction opcode to use
- * - note that the JTAG unit steals 0xFF, so you can't use JTAG and GDBSTUB at
- * the same time.
- */
-#define GDBSTUB_BKPT 0xFF
-
-#ifndef __ASSEMBLY__
-
-/*
- * enumeration of exception codes (as extracted from TBR MSW)
- */
-enum exception_code {
- EXCEP_RESET = 0x000000, /* reset */
-
- /* MMU exceptions */
- EXCEP_ITLBMISS = 0x000100, /* instruction TLB miss */
- EXCEP_DTLBMISS = 0x000108, /* data TLB miss */
- EXCEP_IAERROR = 0x000110, /* instruction address */
- EXCEP_DAERROR = 0x000118, /* data address */
-
- /* system exceptions */
- EXCEP_TRAP = 0x000128, /* program interrupt (PI instruction) */
- EXCEP_ISTEP = 0x000130, /* single step */
- EXCEP_IBREAK = 0x000150, /* instruction breakpoint */
- EXCEP_OBREAK = 0x000158, /* operand breakpoint */
- EXCEP_PRIVINS = 0x000160, /* privileged instruction execution */
- EXCEP_UNIMPINS = 0x000168, /* unimplemented instruction execution */
- EXCEP_UNIMPEXINS = 0x000170, /* unimplemented extended instruction execution */
- EXCEP_MEMERR = 0x000178, /* illegal memory access */
- EXCEP_MISALIGN = 0x000180, /* misalignment */
- EXCEP_BUSERROR = 0x000188, /* bus error */
- EXCEP_ILLINSACC = 0x000190, /* illegal instruction access */
- EXCEP_ILLDATACC = 0x000198, /* illegal data access */
- EXCEP_IOINSACC = 0x0001a0, /* I/O space instruction access */
- EXCEP_PRIVINSACC = 0x0001a8, /* privileged space instruction access */
- EXCEP_PRIVDATACC = 0x0001b0, /* privileged space data access */
- EXCEP_DATINSACC = 0x0001b8, /* data space instruction access */
- EXCEP_DOUBLE_FAULT = 0x000200, /* double fault */
-
- /* FPU exceptions */
- EXCEP_FPU_DISABLED = 0x0001c0, /* FPU disabled */
- EXCEP_FPU_UNIMPINS = 0x0001c8, /* FPU unimplemented operation */
- EXCEP_FPU_OPERATION = 0x0001d0, /* FPU operation */
-
- /* interrupts */
- EXCEP_WDT = 0x000240, /* watchdog timer overflow */
- EXCEP_NMI = 0x000248, /* non-maskable interrupt */
- EXCEP_IRQ_LEVEL0 = 0x000280, /* level 0 maskable interrupt */
- EXCEP_IRQ_LEVEL1 = 0x000288, /* level 1 maskable interrupt */
- EXCEP_IRQ_LEVEL2 = 0x000290, /* level 2 maskable interrupt */
- EXCEP_IRQ_LEVEL3 = 0x000298, /* level 3 maskable interrupt */
- EXCEP_IRQ_LEVEL4 = 0x0002a0, /* level 4 maskable interrupt */
- EXCEP_IRQ_LEVEL5 = 0x0002a8, /* level 5 maskable interrupt */
- EXCEP_IRQ_LEVEL6 = 0x0002b0, /* level 6 maskable interrupt */
-
- /* system calls */
- EXCEP_SYSCALL0 = 0x000300, /* system call 0 */
- EXCEP_SYSCALL1 = 0x000308, /* system call 1 */
- EXCEP_SYSCALL2 = 0x000310, /* system call 2 */
- EXCEP_SYSCALL3 = 0x000318, /* system call 3 */
- EXCEP_SYSCALL4 = 0x000320, /* system call 4 */
- EXCEP_SYSCALL5 = 0x000328, /* system call 5 */
- EXCEP_SYSCALL6 = 0x000330, /* system call 6 */
- EXCEP_SYSCALL7 = 0x000338, /* system call 7 */
- EXCEP_SYSCALL8 = 0x000340, /* system call 8 */
- EXCEP_SYSCALL9 = 0x000348, /* system call 9 */
- EXCEP_SYSCALL10 = 0x000350, /* system call 10 */
- EXCEP_SYSCALL11 = 0x000358, /* system call 11 */
- EXCEP_SYSCALL12 = 0x000360, /* system call 12 */
- EXCEP_SYSCALL13 = 0x000368, /* system call 13 */
- EXCEP_SYSCALL14 = 0x000370, /* system call 14 */
- EXCEP_SYSCALL15 = 0x000378, /* system call 15 */
-};
-
-extern void __set_intr_stub(enum exception_code code, void *handler);
-extern void set_intr_stub(enum exception_code code, void *handler);
-
-struct pt_regs;
-
-extern asmlinkage void __common_exception(void);
-extern asmlinkage void itlb_miss(void);
-extern asmlinkage void dtlb_miss(void);
-extern asmlinkage void itlb_aerror(void);
-extern asmlinkage void dtlb_aerror(void);
-extern asmlinkage void raw_bus_error(void);
-extern asmlinkage void double_fault(void);
-extern asmlinkage int system_call(struct pt_regs *);
-extern asmlinkage void nmi(struct pt_regs *, enum exception_code);
-extern asmlinkage void uninitialised_exception(struct pt_regs *,
- enum exception_code);
-extern asmlinkage void irq_handler(void);
-extern asmlinkage void profile_handler(void);
-extern asmlinkage void nmi_handler(void);
-extern asmlinkage void misalignment(struct pt_regs *, enum exception_code);
-
-extern void die(const char *, struct pt_regs *, enum exception_code)
- __noreturn;
-
-extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code);
-
-#define NUM2EXCEP_IRQ_LEVEL(num) (EXCEP_IRQ_LEVEL0 + (num) * 8)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_EXCEPTIONS_H */
diff --git a/arch/mn10300/include/asm/fpu.h b/arch/mn10300/include/asm/fpu.h
deleted file mode 100644
index a47e995d45f3..000000000000
--- a/arch/mn10300/include/asm/fpu.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* MN10300 FPU definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * Derived from include/asm-i386/i387.h: Copyright (C) 1994 Linus Torvalds
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_FPU_H
-#define _ASM_FPU_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/sched.h>
-#include <asm/exceptions.h>
-#include <asm/sigcontext.h>
-
-#ifdef __KERNEL__
-
-extern asmlinkage void fpu_disabled(void);
-
-#ifdef CONFIG_FPU
-
-#ifdef CONFIG_LAZY_SAVE_FPU
-/* the task that currently owns the FPU state */
-extern struct task_struct *fpu_state_owner;
-#endif
-
-#if (THREAD_USING_FPU & ~0xff)
-#error THREAD_USING_FPU must be smaller than 0x100.
-#endif
-
-static inline void set_using_fpu(struct task_struct *tsk)
-{
- asm volatile(
- "bset %0,(0,%1)"
- :
- : "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags)
- : "memory", "cc");
-}
-
-static inline void clear_using_fpu(struct task_struct *tsk)
-{
- asm volatile(
- "bclr %0,(0,%1)"
- :
- : "i"(THREAD_USING_FPU), "a"(&tsk->thread.fpu_flags)
- : "memory", "cc");
-}
-
-#define is_using_fpu(tsk) ((tsk)->thread.fpu_flags & THREAD_USING_FPU)
-
-extern asmlinkage void fpu_kill_state(struct task_struct *);
-extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code);
-extern asmlinkage void fpu_init_state(void);
-extern asmlinkage void fpu_save(struct fpu_state_struct *);
-extern int fpu_setup_sigcontext(struct fpucontext *buf);
-extern int fpu_restore_sigcontext(struct fpucontext *buf);
-
-static inline void unlazy_fpu(struct task_struct *tsk)
-{
- preempt_disable();
-#ifndef CONFIG_LAZY_SAVE_FPU
- if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
- fpu_save(&tsk->thread.fpu_state);
- tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
- tsk->thread.uregs->epsw &= ~EPSW_FE;
- }
-#else
- if (fpu_state_owner == tsk)
- fpu_save(&tsk->thread.fpu_state);
-#endif
- preempt_enable();
-}
-
-static inline void exit_fpu(struct task_struct *tsk)
-{
-#ifdef CONFIG_LAZY_SAVE_FPU
- preempt_disable();
- if (fpu_state_owner == tsk)
- fpu_state_owner = NULL;
- preempt_enable();
-#endif
-}
-
-static inline void flush_fpu(void)
-{
- struct task_struct *tsk = current;
-
- preempt_disable();
-#ifndef CONFIG_LAZY_SAVE_FPU
- if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
- tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
- tsk->thread.uregs->epsw &= ~EPSW_FE;
- }
-#else
- if (fpu_state_owner == tsk) {
- fpu_state_owner = NULL;
- tsk->thread.uregs->epsw &= ~EPSW_FE;
- }
-#endif
- preempt_enable();
- clear_using_fpu(tsk);
-}
-
-#else /* CONFIG_FPU */
-
-extern asmlinkage
-void unexpected_fpu_exception(struct pt_regs *, enum exception_code);
-#define fpu_exception unexpected_fpu_exception
-
-struct task_struct;
-struct fpu_state_struct;
-static inline bool is_using_fpu(struct task_struct *tsk) { return false; }
-static inline void set_using_fpu(struct task_struct *tsk) {}
-static inline void clear_using_fpu(struct task_struct *tsk) {}
-static inline void fpu_init_state(void) {}
-static inline void fpu_save(struct fpu_state_struct *s) {}
-static inline void fpu_kill_state(struct task_struct *tsk) {}
-static inline void unlazy_fpu(struct task_struct *tsk) {}
-static inline void exit_fpu(struct task_struct *tsk) {}
-static inline void flush_fpu(void) {}
-static inline int fpu_setup_sigcontext(struct fpucontext *buf) { return 0; }
-static inline int fpu_restore_sigcontext(struct fpucontext *buf) { return 0; }
-#endif /* CONFIG_FPU */
-
-#endif /* __KERNEL__ */
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_FPU_H */
diff --git a/arch/mn10300/include/asm/frame.inc b/arch/mn10300/include/asm/frame.inc
deleted file mode 100644
index 1c3eb4fda958..000000000000
--- a/arch/mn10300/include/asm/frame.inc
+++ /dev/null
@@ -1,97 +0,0 @@
-/* MN10300 Microcontroller core system register definitions -*- asm -*-
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_FRAME_INC
-#define _ASM_FRAME_INC
-
-#ifndef __ASSEMBLY__
-#error not for use in C files
-#endif
-
-#ifndef __ASM_OFFSETS_H__
-#include <asm/asm-offsets.h>
-#endif
-#include <asm/thread_info.h>
-
-#define pi break
-
-#define fp a3
-
-###############################################################################
-#
-# build a stack frame from the registers
-# - the caller has subtracted 4 from SP before coming here
-#
-###############################################################################
-.macro SAVE_ALL
- add -4,sp # next exception frame ptr save area
- movm [other],(sp)
- mov usp,a1
- mov a1,(sp) # USP in MOVM[other] dummy slot
- movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp)
- mov sp,fp # FRAME pointer in A3
- add -12,sp # allow for calls to be made
-
- # push the exception frame onto the front of the list
- GET_THREAD_INFO a1
- mov (TI_frame,a1),a0
- mov a0,(REG_NEXT,fp)
- mov fp,(TI_frame,a1)
-
- # disable the FPU inside the kernel
- and ~EPSW_FE,epsw
-
- # we may be holding current in E2
-#ifdef CONFIG_MN10300_CURRENT_IN_E2
- mov (__current),e2
-#endif
-.endm
-
-###############################################################################
-#
-# restore the registers from a stack frame
-#
-###############################################################################
-.macro RESTORE_ALL
- # peel back the stack to the calling frame
- # - we need that when returning from interrupts to kernel mode
- GET_THREAD_INFO a0
- mov (TI_frame,a0),fp
- mov fp,sp
- mov (REG_NEXT,fp),d0
- mov d0,(TI_frame,a0) # userspace has regs->next == 0
-
-#ifndef CONFIG_MN10300_USING_JTAG
- mov (REG_EPSW,fp),d0
- btst EPSW_T,d0
- beq 99f
-
- or EPSW_NMID,epsw
- movhu (DCR),d1
- or 0x0001, d1
- movhu d1,(DCR)
-
-99:
-#endif
- movm (sp),[d2,d3,a2,a3,exreg0,exreg1,exother]
-
- # must restore usp even if returning to kernel space,
- # when CONFIG_PREEMPT is enabled.
- mov (sp),a1 # USP in MOVM[other] dummy slot
- mov a1,usp
-
- movm (sp),[other]
- add 8,sp
- rti
-
-.endm
-
-
-#endif /* _ASM_FRAME_INC */
diff --git a/arch/mn10300/include/asm/ftrace.h b/arch/mn10300/include/asm/ftrace.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/mn10300/include/asm/ftrace.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/mn10300/include/asm/futex.h b/arch/mn10300/include/asm/futex.h
deleted file mode 100644
index 0b745828f42b..000000000000
--- a/arch/mn10300/include/asm/futex.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/futex.h>
diff --git a/arch/mn10300/include/asm/gdb-stub.h b/arch/mn10300/include/asm/gdb-stub.h
deleted file mode 100644
index f5495ad82b77..000000000000
--- a/arch/mn10300/include/asm/gdb-stub.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* MN10300 Kernel GDB stub definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_GDB_STUB_H
-#define _ASM_GDB_STUB_H
-
-#include <asm/exceptions.h>
-
-/*
- * register ID numbers in GDB remote protocol
- */
-
-#define GDB_REGID_PC 9
-#define GDB_REGID_FP 7
-#define GDB_REGID_SP 8
-
-/*
- * virtual stack layout for the GDB exception handler
- */
-#define NUMREGS 64
-
-#define GDB_FR_D0 (0 * 4)
-#define GDB_FR_D1 (1 * 4)
-#define GDB_FR_D2 (2 * 4)
-#define GDB_FR_D3 (3 * 4)
-#define GDB_FR_A0 (4 * 4)
-#define GDB_FR_A1 (5 * 4)
-#define GDB_FR_A2 (6 * 4)
-#define GDB_FR_A3 (7 * 4)
-
-#define GDB_FR_SP (8 * 4)
-#define GDB_FR_PC (9 * 4)
-#define GDB_FR_MDR (10 * 4)
-#define GDB_FR_EPSW (11 * 4)
-#define GDB_FR_LIR (12 * 4)
-#define GDB_FR_LAR (13 * 4)
-#define GDB_FR_MDRQ (14 * 4)
-
-#define GDB_FR_E0 (15 * 4)
-#define GDB_FR_E1 (16 * 4)
-#define GDB_FR_E2 (17 * 4)
-#define GDB_FR_E3 (18 * 4)
-#define GDB_FR_E4 (19 * 4)
-#define GDB_FR_E5 (20 * 4)
-#define GDB_FR_E6 (21 * 4)
-#define GDB_FR_E7 (22 * 4)
-
-#define GDB_FR_SSP (23 * 4)
-#define GDB_FR_MSP (24 * 4)
-#define GDB_FR_USP (25 * 4)
-#define GDB_FR_MCRH (26 * 4)
-#define GDB_FR_MCRL (27 * 4)
-#define GDB_FR_MCVF (28 * 4)
-
-#define GDB_FR_FPCR (29 * 4)
-#define GDB_FR_DUMMY0 (30 * 4)
-#define GDB_FR_DUMMY1 (31 * 4)
-
-#define GDB_FR_FS0 (32 * 4)
-
-#define GDB_FR_SIZE (NUMREGS * 4)
-
-#ifndef __ASSEMBLY__
-
-/*
- * This is the same as above, but for the high-level
- * part of the GDB stub.
- */
-
-struct gdb_regs {
- /* saved main processor registers */
- u32 d0, d1, d2, d3, a0, a1, a2, a3;
- u32 sp, pc, mdr, epsw, lir, lar, mdrq;
- u32 e0, e1, e2, e3, e4, e5, e6, e7;
- u32 ssp, msp, usp, mcrh, mcrl, mcvf;
-
- /* saved floating point registers */
- u32 fpcr, _dummy0, _dummy1;
- u32 fs0, fs1, fs2, fs3, fs4, fs5, fs6, fs7;
- u32 fs8, fs9, fs10, fs11, fs12, fs13, fs14, fs15;
- u32 fs16, fs17, fs18, fs19, fs20, fs21, fs22, fs23;
- u32 fs24, fs25, fs26, fs27, fs28, fs29, fs30, fs31;
-};
-
-/*
- * Prototypes
- */
-extern void show_registers_only(struct pt_regs *regs);
-
-extern asmlinkage void gdbstub_init(void);
-extern asmlinkage void gdbstub_exit(int status);
-extern asmlinkage void gdbstub_io_init(void);
-extern asmlinkage void gdbstub_io_set_baud(unsigned baud);
-extern asmlinkage int gdbstub_io_rx_char(unsigned char *_ch, int nonblock);
-extern asmlinkage void gdbstub_io_tx_char(unsigned char ch);
-extern asmlinkage void gdbstub_io_tx_flush(void);
-
-extern asmlinkage void gdbstub_io_rx_handler(void);
-extern asmlinkage void gdbstub_rx_irq(struct pt_regs *, enum exception_code);
-extern asmlinkage int gdbstub_intercept(struct pt_regs *, enum exception_code);
-extern asmlinkage void gdbstub_exception(struct pt_regs *, enum exception_code);
-extern asmlinkage void __gdbstub_bug_trap(void);
-extern asmlinkage void __gdbstub_pause(void);
-
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-extern asmlinkage void gdbstub_purge_cache(void);
-#else
-#define gdbstub_purge_cache() do {} while (0)
-#endif
-
-/* Used to prevent crashes in memory access */
-extern asmlinkage int gdbstub_read_byte(const u8 *, u8 *);
-extern asmlinkage int gdbstub_read_word(const u8 *, u8 *);
-extern asmlinkage int gdbstub_read_dword(const u8 *, u8 *);
-extern asmlinkage int gdbstub_write_byte(u32, u8 *);
-extern asmlinkage int gdbstub_write_word(u32, u8 *);
-extern asmlinkage int gdbstub_write_dword(u32, u8 *);
-
-extern asmlinkage void gdbstub_read_byte_guard(void);
-extern asmlinkage void gdbstub_read_byte_cont(void);
-extern asmlinkage void gdbstub_read_word_guard(void);
-extern asmlinkage void gdbstub_read_word_cont(void);
-extern asmlinkage void gdbstub_read_dword_guard(void);
-extern asmlinkage void gdbstub_read_dword_cont(void);
-extern asmlinkage void gdbstub_write_byte_guard(void);
-extern asmlinkage void gdbstub_write_byte_cont(void);
-extern asmlinkage void gdbstub_write_word_guard(void);
-extern asmlinkage void gdbstub_write_word_cont(void);
-extern asmlinkage void gdbstub_write_dword_guard(void);
-extern asmlinkage void gdbstub_write_dword_cont(void);
-
-extern u8 gdbstub_rx_buffer[PAGE_SIZE];
-extern u32 gdbstub_rx_inp;
-extern u32 gdbstub_rx_outp;
-extern u8 gdbstub_rx_overflow;
-extern u8 gdbstub_busy;
-extern u8 gdbstub_rx_unget;
-
-#ifdef CONFIG_GDBSTUB_DEBUGGING
-extern void gdbstub_printk(const char *fmt, ...)
- __attribute__((format(printf, 1, 2)));
-#else
-static inline __attribute__((format(printf, 1, 2)))
-void gdbstub_printk(const char *fmt, ...)
-{
-}
-#endif
-
-#ifdef CONFIG_GDBSTUB_DEBUG_ENTRY
-#define gdbstub_entry(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
-#else
-#define gdbstub_entry(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
-#endif
-
-#ifdef CONFIG_GDBSTUB_DEBUG_PROTOCOL
-#define gdbstub_proto(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
-#else
-#define gdbstub_proto(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
-#endif
-
-#ifdef CONFIG_GDBSTUB_DEBUG_IO
-#define gdbstub_io(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
-#else
-#define gdbstub_io(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
-#endif
-
-#ifdef CONFIG_GDBSTUB_DEBUG_BREAKPOINT
-#define gdbstub_bkpt(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
-#else
-#define gdbstub_bkpt(FMT, ...) no_printk(FMT, ##__VA_ARGS__)
-#endif
-
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_GDB_STUB_H */
diff --git a/arch/mn10300/include/asm/hardirq.h b/arch/mn10300/include/asm/hardirq.h
deleted file mode 100644
index 0000d650b55f..000000000000
--- a/arch/mn10300/include/asm/hardirq.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* MN10300 Hardware IRQ statistics and management
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_HARDIRQ_H
-#define _ASM_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/irq.h>
-#include <asm/exceptions.h>
-
-/* assembly code in softirq.h is sensitive to the offsets of these fields */
-typedef struct {
- unsigned int __softirq_pending;
-#ifdef CONFIG_MN10300_WD_TIMER
- unsigned int __nmi_count; /* arch dependent */
- unsigned int __irq_count; /* arch dependent */
-#endif
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
-
-extern void ack_bad_irq(int irq);
-
-/*
- * manipulate stubs in the MN10300 CPU Trap/Interrupt Vector table
- * - these should jump to __common_exception in entry.S unless there's a good
- * reason to do otherwise (see trap_preinit() in traps.c)
- */
-typedef void (*intr_stub_fnx)(struct pt_regs *regs,
- enum exception_code intcode);
-
-/*
- * manipulate pointers in the Exception table (see entry.S)
- * - these are indexed by decoding the lower 24 bits of the TBR register
- * - note that the MN103E010 doesn't always trap through the correct vector,
- * but does always set the TBR correctly
- */
-extern asmlinkage void set_excp_vector(enum exception_code code,
- intr_stub_fnx handler);
-
-#endif /* _ASM_HARDIRQ_H */
diff --git a/arch/mn10300/include/asm/highmem.h b/arch/mn10300/include/asm/highmem.h
deleted file mode 100644
index 1ddea5afba09..000000000000
--- a/arch/mn10300/include/asm/highmem.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* MN10300 Virtual kernel memory mappings for high memory
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-i386/highmem.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/highmem.h>
-#include <asm/kmap_types.h>
-#include <asm/pgtable.h>
-
-/* undef for production */
-#undef HIGHMEM_DEBUG
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-extern void __init kmap_init(void);
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-#define PKMAP_BASE 0xfe000000UL
-#define LAST_PKMAP 1024
-#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
-#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-extern unsigned long kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-static inline unsigned long kmap(struct page *page)
-{
- if (in_interrupt())
- BUG();
- if (page < highmem_start_page)
- return page_address(page);
- return kmap_high(page);
-}
-
-static inline void kunmap(struct page *page)
-{
- if (in_interrupt())
- BUG();
- if (page < highmem_start_page)
- return;
- kunmap_high(page);
-}
-
-/*
- * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
- * gives a more generic (and caching) interface. But kmap_atomic can
- * be used in IRQ contexts, so in some (very limited) cases we need
- * it.
- */
-static inline void *kmap_atomic(struct page *page)
-{
- unsigned long vaddr;
- int idx, type;
-
- preempt_disable();
- pagefault_disable();
- if (page < highmem_start_page)
- return page_address(page);
-
- type = kmap_atomic_idx_push();
- idx = type + KM_TYPE_NR * smp_processor_id();
- vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
-#if HIGHMEM_DEBUG
- if (!pte_none(*(kmap_pte - idx)))
- BUG();
-#endif
- set_pte(kmap_pte - idx, mk_pte(page, kmap_prot));
- local_flush_tlb_one(vaddr);
-
- return (void *)vaddr;
-}
-
-static inline void __kunmap_atomic(unsigned long vaddr)
-{
- int type;
-
- if (vaddr < FIXADDR_START) { /* FIXME */
- pagefault_enable();
- preempt_enable();
- return;
- }
-
- type = kmap_atomic_idx();
-
-#if HIGHMEM_DEBUG
- {
- unsigned int idx;
- idx = type + KM_TYPE_NR * smp_processor_id();
-
- if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx))
- BUG();
-
- /*
- * force other mappings to Oops if they'll try to access
- * this pte without first remap it
- */
- pte_clear(kmap_pte - idx);
- local_flush_tlb_one(vaddr);
- }
-#endif
-
- kmap_atomic_idx_pop();
- pagefault_enable();
- preempt_enable();
-}
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/mn10300/include/asm/hw_irq.h b/arch/mn10300/include/asm/hw_irq.h
deleted file mode 100644
index 70619901098e..000000000000
--- a/arch/mn10300/include/asm/hw_irq.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* MN10300 Hardware interrupt definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
-
-#endif /* _ASM_HW_IRQ_H */
diff --git a/arch/mn10300/include/asm/intctl-regs.h b/arch/mn10300/include/asm/intctl-regs.h
deleted file mode 100644
index d65bbeebe50a..000000000000
--- a/arch/mn10300/include/asm/intctl-regs.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* MN10300 On-board interrupt controller registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_INTCTL_REGS_H
-#define _ASM_INTCTL_REGS_H
-
-#include <asm/cpu-regs.h>
-
-#ifdef __KERNEL__
-
-/*
- * Interrupt controller registers
- * - Registers 64-191 are at addresses offset from the main array
- */
-#define GxICR(X) \
- __SYSREG(0xd4000000 + (X) * 4 + \
- (((X) >= 64) && ((X) < 192)) * 0xf00, u16)
-
-#define GxICR_u8(X) \
- __SYSREG(0xd4000000 + (X) * 4 + \
- (((X) >= 64) && ((X) < 192)) * 0xf00, u8)
-
-#include <proc/intctl-regs.h>
-
-#define XIRQ_TRIGGER_LOWLEVEL 0
-#define XIRQ_TRIGGER_HILEVEL 1
-#define XIRQ_TRIGGER_NEGEDGE 2
-#define XIRQ_TRIGGER_POSEDGE 3
-
-/* non-maskable interrupt control */
-#define NMIIRQ 0
-#define NMICR GxICR(NMIIRQ) /* NMI control register */
-#define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */
-#define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */
-#define NMICR_ABUSERR 0x0008 /* async bus error flag */
-
-/* maskable interrupt control */
-#define GxICR_DETECT 0x0001 /* interrupt detect flag */
-#define GxICR_REQUEST 0x0010 /* interrupt request flag */
-#define GxICR_ENABLE 0x0100 /* interrupt enable flag */
-#define GxICR_LEVEL 0x7000 /* interrupt priority level */
-#define GxICR_LEVEL_0 0x0000 /* - level 0 */
-#define GxICR_LEVEL_1 0x1000 /* - level 1 */
-#define GxICR_LEVEL_2 0x2000 /* - level 2 */
-#define GxICR_LEVEL_3 0x3000 /* - level 3 */
-#define GxICR_LEVEL_4 0x4000 /* - level 4 */
-#define GxICR_LEVEL_5 0x5000 /* - level 5 */
-#define GxICR_LEVEL_6 0x6000 /* - level 6 */
-#define GxICR_LEVEL_SHIFT 12
-#define GxICR_NMI 0x8000 /* nmi request flag */
-
-#define NUM2GxICR_LEVEL(num) ((num) << GxICR_LEVEL_SHIFT)
-
-#ifndef __ASSEMBLY__
-extern void set_intr_level(int irq, u16 level);
-extern void mn10300_set_lateack_irq_type(int irq);
-#endif
-
-/* external interrupts */
-#define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_INTCTL_REGS_H */
diff --git a/arch/mn10300/include/asm/io.h b/arch/mn10300/include/asm/io.h
deleted file mode 100644
index 62189353d2f6..000000000000
--- a/arch/mn10300/include/asm/io.h
+++ /dev/null
@@ -1,325 +0,0 @@
-/* MN10300 I/O port emulation and memory-mapped I/O
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#include <asm/page.h> /* I/O is all done through memory accesses */
-#include <asm/cpu-regs.h>
-#include <asm/cacheflush.h>
-#include <asm-generic/pci_iomap.h>
-
-#define mmiowb() do {} while (0)
-
-/*****************************************************************************/
-/*
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the x86 architecture, we just read/write the
- * memory location directly.
- */
-static inline u8 readb(const volatile void __iomem *addr)
-{
- return *(const volatile u8 *) addr;
-}
-
-static inline u16 readw(const volatile void __iomem *addr)
-{
- return *(const volatile u16 *) addr;
-}
-
-static inline u32 readl(const volatile void __iomem *addr)
-{
- return *(const volatile u32 *) addr;
-}
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
-
-static inline void writeb(u8 b, volatile void __iomem *addr)
-{
- *(volatile u8 *) addr = b;
-}
-
-static inline void writew(u16 b, volatile void __iomem *addr)
-{
- *(volatile u16 *) addr = b;
-}
-
-static inline void writel(u32 b, volatile void __iomem *addr)
-{
- *(volatile u32 *) addr = b;
-}
-
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-#define writeb_relaxed writeb
-#define writew_relaxed writew
-#define writel_relaxed writel
-
-/*****************************************************************************/
-/*
- * traditional input/output functions
- */
-static inline u8 inb_local(unsigned long addr)
-{
- return readb((volatile void __iomem *) addr);
-}
-
-static inline void outb_local(u8 b, unsigned long addr)
-{
- return writeb(b, (volatile void __iomem *) addr);
-}
-
-static inline u8 inb(unsigned long addr)
-{
- return readb((volatile void __iomem *) addr);
-}
-
-static inline u16 inw(unsigned long addr)
-{
- return readw((volatile void __iomem *) addr);
-}
-
-static inline u32 inl(unsigned long addr)
-{
- return readl((volatile void __iomem *) addr);
-}
-
-static inline void outb(u8 b, unsigned long addr)
-{
- return writeb(b, (volatile void __iomem *) addr);
-}
-
-static inline void outw(u16 b, unsigned long addr)
-{
- return writew(b, (volatile void __iomem *) addr);
-}
-
-static inline void outl(u32 b, unsigned long addr)
-{
- return writel(b, (volatile void __iomem *) addr);
-}
-
-#define inb_p(addr) inb(addr)
-#define inw_p(addr) inw(addr)
-#define inl_p(addr) inl(addr)
-#define outb_p(x, addr) outb((x), (addr))
-#define outw_p(x, addr) outw((x), (addr))
-#define outl_p(x, addr) outl((x), (addr))
-
-static inline void insb(unsigned long addr, void *buffer, int count)
-{
- if (count) {
- u8 *buf = buffer;
- do {
- u8 x = inb(addr);
- *buf++ = x;
- } while (--count);
- }
-}
-
-static inline void insw(unsigned long addr, void *buffer, int count)
-{
- if (count) {
- u16 *buf = buffer;
- do {
- u16 x = inw(addr);
- *buf++ = x;
- } while (--count);
- }
-}
-
-static inline void insl(unsigned long addr, void *buffer, int count)
-{
- if (count) {
- u32 *buf = buffer;
- do {
- u32 x = inl(addr);
- *buf++ = x;
- } while (--count);
- }
-}
-
-static inline void outsb(unsigned long addr, const void *buffer, int count)
-{
- if (count) {
- const u8 *buf = buffer;
- do {
- outb(*buf++, addr);
- } while (--count);
- }
-}
-
-static inline void outsw(unsigned long addr, const void *buffer, int count)
-{
- if (count) {
- const u16 *buf = buffer;
- do {
- outw(*buf++, addr);
- } while (--count);
- }
-}
-
-extern void __outsl(unsigned long addr, const void *buffer, int count);
-static inline void outsl(unsigned long addr, const void *buffer, int count)
-{
- if ((unsigned long) buffer & 0x3)
- return __outsl(addr, buffer, count);
-
- if (count) {
- const u32 *buf = buffer;
- do {
- outl(*buf++, addr);
- } while (--count);
- }
-}
-
-#define ioread8(addr) readb(addr)
-#define ioread16(addr) readw(addr)
-#define ioread32(addr) readl(addr)
-
-#define iowrite8(v, addr) writeb((v), (addr))
-#define iowrite16(v, addr) writew((v), (addr))
-#define iowrite32(v, addr) writel((v), (addr))
-
-#define ioread16be(addr) be16_to_cpu(readw(addr))
-#define ioread32be(addr) be32_to_cpu(readl(addr))
-#define iowrite16be(v, addr) writew(cpu_to_be16(v), (addr))
-#define iowrite32be(v, addr) writel(cpu_to_be32(v), (addr))
-
-#define ioread8_rep(p, dst, count) \
- insb((unsigned long) (p), (dst), (count))
-#define ioread16_rep(p, dst, count) \
- insw((unsigned long) (p), (dst), (count))
-#define ioread32_rep(p, dst, count) \
- insl((unsigned long) (p), (dst), (count))
-
-#define iowrite8_rep(p, src, count) \
- outsb((unsigned long) (p), (src), (count))
-#define iowrite16_rep(p, src, count) \
- outsw((unsigned long) (p), (src), (count))
-#define iowrite32_rep(p, src, count) \
- outsl((unsigned long) (p), (src), (count))
-
-#define readsb(p, dst, count) \
- insb((unsigned long) (p), (dst), (count))
-#define readsw(p, dst, count) \
- insw((unsigned long) (p), (dst), (count))
-#define readsl(p, dst, count) \
- insl((unsigned long) (p), (dst), (count))
-
-#define writesb(p, src, count) \
- outsb((unsigned long) (p), (src), (count))
-#define writesw(p, src, count) \
- outsw((unsigned long) (p), (src), (count))
-#define writesl(p, src, count) \
- outsl((unsigned long) (p), (src), (count))
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#ifdef __KERNEL__
-
-#include <linux/vmalloc.h>
-#define __io_virt(x) ((void *) (x))
-
-/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
-struct pci_dev;
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
-{
-}
-
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are pretty trivial
- */
-static inline unsigned long virt_to_phys(volatile void *address)
-{
- return __pa(address);
-}
-
-static inline void *phys_to_virt(unsigned long address)
-{
- return __va(address);
-}
-
-/*
- * Change "struct page" to physical address.
- */
-static inline void __iomem *__ioremap(unsigned long offset, unsigned long size,
- unsigned long flags)
-{
- return (void __iomem *) offset;
-}
-
-static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
-{
- return (void __iomem *)(offset & ~0x20000000);
-}
-
-/*
- * This one maps high address device memory and turns off caching for that
- * area. it's useful if some control registers are in such an area and write
- * combining or read caching is not desirable:
- */
-static inline void __iomem *ioremap_nocache(unsigned long offset, unsigned long size)
-{
- return (void __iomem *) (offset | 0x20000000);
-}
-
-#define ioremap_wc ioremap_nocache
-#define ioremap_wt ioremap_nocache
-#define ioremap_uc ioremap_nocache
-
-static inline void iounmap(void __iomem *addr)
-{
-}
-
-static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
-{
- return (void __iomem *) port;
-}
-
-static inline void ioport_unmap(void __iomem *p)
-{
-}
-
-#define xlate_dev_kmem_ptr(p) ((void *) (p))
-#define xlate_dev_mem_ptr(p) ((void *) (p))
-
-/*
- * PCI bus iomem addresses must be in the region 0x80000000-0x9fffffff
- */
-static inline unsigned long virt_to_bus(volatile void *address)
-{
- return ((unsigned long) address) & ~0x20000000;
-}
-
-static inline void *bus_to_virt(unsigned long address)
-{
- return (void *) address;
-}
-
-#define page_to_bus page_to_phys
-
-#define memset_io(a, b, c) memset(__io_virt(a), (b), (c))
-#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c))
-#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c))
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_IO_H */
diff --git a/arch/mn10300/include/asm/irq.h b/arch/mn10300/include/asm/irq.h
deleted file mode 100644
index 1a73fb3f60c6..000000000000
--- a/arch/mn10300/include/asm/irq.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* MN10300 Hardware interrupt definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-i386/irq.h:
- * - (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
-
-#include <asm/intctl-regs.h>
-#include <asm/reset-regs.h>
-#include <proc/irq.h>
-
-/* this number is used when no interrupt has been assigned */
-#define NO_IRQ INT_MAX
-
-/*
- * hardware irq numbers
- * - the ASB2364 has an FPGA with an IRQ multiplexer on it
- */
-#ifdef CONFIG_MN10300_UNIT_ASB2364
-#include <unit/irq.h>
-#else
-#define NR_CPU_IRQS GxICR_NUM_IRQS
-#define NR_IRQS NR_CPU_IRQS
-#endif
-
-/* external hardware irq numbers */
-#define NR_XIRQS GxICR_NUM_XIRQS
-
-#define irq_canonicalize(IRQ) (IRQ)
-
-#endif /* _ASM_IRQ_H */
diff --git a/arch/mn10300/include/asm/irq_regs.h b/arch/mn10300/include/asm/irq_regs.h
deleted file mode 100644
index 97d0cb5af807..000000000000
--- a/arch/mn10300/include/asm/irq_regs.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* MN10300 IRQ registers pointer definition
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_IRQ_REGS_H
-#define _ASM_IRQ_REGS_H
-
-/*
- * Per-cpu current frame pointer - the location of the last exception frame on
- * the stack
- */
-#define ARCH_HAS_OWN_IRQ_REGS
-
-#ifndef __ASSEMBLY__
-static inline __attribute__((const))
-struct pt_regs *get_irq_regs(void)
-{
- return current_frame();
-}
-#endif
-
-#endif /* _ASM_IRQ_REGS_H */
diff --git a/arch/mn10300/include/asm/irqflags.h b/arch/mn10300/include/asm/irqflags.h
deleted file mode 100644
index 8730c0a3c37d..000000000000
--- a/arch/mn10300/include/asm/irqflags.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/* MN10300 IRQ flag handling
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-#include <asm/cpu-regs.h>
-/* linux/smp.h <- linux/irqflags.h needs asm/smp.h first */
-#include <asm/smp.h>
-
-/*
- * interrupt control
- * - "disabled": run in IM1/2
- * - level 0 - kernel debugger
- * - level 1 - virtual serial DMA (if present)
- * - level 5 - normal interrupt priority
- * - level 6 - timer interrupt
- * - "enabled": run in IM7
- */
-#define MN10300_CLI_LEVEL (CONFIG_LINUX_CLI_LEVEL << EPSW_IM_SHIFT)
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
-
- asm volatile("mov epsw,%0" : "=d"(flags));
- return flags;
-}
-
-static inline void arch_local_irq_disable(void)
-{
- asm volatile(
- " and %0,epsw \n"
- " or %1,epsw \n"
- " nop \n"
- " nop \n"
- " nop \n"
- :
- : "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL)
- : "memory");
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
- flags = arch_local_save_flags();
- arch_local_irq_disable();
- return flags;
-}
-
-/*
- * we make sure arch_irq_enable() doesn't cause priority inversion
- */
-extern unsigned long __mn10300_irq_enabled_epsw[];
-
-static inline void arch_local_irq_enable(void)
-{
- unsigned long tmp;
- int cpu = raw_smp_processor_id();
-
- asm volatile(
- " mov epsw,%0 \n"
- " and %1,%0 \n"
- " or %2,%0 \n"
- " mov %0,epsw \n"
- : "=&d"(tmp)
- : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw[cpu])
- : "memory", "cc");
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile(
- " mov %0,epsw \n"
- " nop \n"
- " nop \n"
- " nop \n"
- :
- : "d"(flags)
- : "memory", "cc");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return (flags & (EPSW_IE | EPSW_IM)) != (EPSW_IE | EPSW_IM_7);
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-/*
- * Hook to save power by halting the CPU
- * - called from the idle loop
- * - must reenable interrupts (which takes three instruction cycles to complete)
- */
-static inline void arch_safe_halt(void)
-{
-#ifdef CONFIG_SMP
- arch_local_irq_enable();
-#else
- asm volatile(
- " or %0,epsw \n"
- " nop \n"
- " nop \n"
- " bset %2,(%1) \n"
- :
- : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP)
- : "cc");
-#endif
-}
-
-#define __sleep_cpu() \
-do { \
- asm volatile( \
- " bset %1,(%0)\n" \
- "1: btst %1,(%0)\n" \
- " bne 1b\n" \
- : \
- : "i"(&CPUM), "i"(CPUM_SLEEP) \
- : "cc" \
- ); \
-} while (0)
-
-static inline void arch_local_cli(void)
-{
- asm volatile(
- " and %0,epsw \n"
- " nop \n"
- " nop \n"
- " nop \n"
- :
- : "i"(~EPSW_IE)
- : "memory"
- );
-}
-
-static inline unsigned long arch_local_cli_save(void)
-{
- unsigned long flags = arch_local_save_flags();
- arch_local_cli();
- return flags;
-}
-
-static inline void arch_local_sti(void)
-{
- asm volatile(
- " or %0,epsw \n"
- :
- : "i"(EPSW_IE)
- : "memory");
-}
-
-static inline void arch_local_change_intr_mask_level(unsigned long level)
-{
- asm volatile(
- " and %0,epsw \n"
- " or %1,epsw \n"
- :
- : "i"(~EPSW_IM), "i"(EPSW_IE | level)
- : "cc", "memory");
-}
-
-#else /* !__ASSEMBLY__ */
-
-#define LOCAL_SAVE_FLAGS(reg) \
- mov epsw,reg
-
-#define LOCAL_IRQ_DISABLE \
- and ~EPSW_IM,epsw; \
- or EPSW_IE|MN10300_CLI_LEVEL,epsw; \
- nop; \
- nop; \
- nop
-
-#define LOCAL_IRQ_ENABLE \
- or EPSW_IE|EPSW_IM_7,epsw
-
-#define LOCAL_IRQ_RESTORE(reg) \
- mov reg,epsw
-
-#define LOCAL_CLI_SAVE(reg) \
- mov epsw,reg; \
- and ~EPSW_IE,epsw; \
- nop; \
- nop; \
- nop
-
-#define LOCAL_CLI \
- and ~EPSW_IE,epsw; \
- nop; \
- nop; \
- nop
-
-#define LOCAL_STI \
- or EPSW_IE,epsw
-
-#define LOCAL_CHANGE_INTR_MASK_LEVEL(level) \
- and ~EPSW_IM,epsw; \
- or EPSW_IE|(level),epsw
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_IRQFLAGS_H */
diff --git a/arch/mn10300/include/asm/kdebug.h b/arch/mn10300/include/asm/kdebug.h
deleted file mode 100644
index 0f47e112190c..000000000000
--- a/arch/mn10300/include/asm/kdebug.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* MN10300 In-kernel death knells
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_KDEBUG_H
-#define _ASM_KDEBUG_H
-
-/* Grossly misnamed. */
-enum die_val {
- DIE_OOPS = 1,
- DIE_BREAKPOINT,
- DIE_GPF,
-};
-
-#endif /* _ASM_KDEBUG_H */
diff --git a/arch/mn10300/include/asm/kgdb.h b/arch/mn10300/include/asm/kgdb.h
deleted file mode 100644
index eb245f18a708..000000000000
--- a/arch/mn10300/include/asm/kgdb.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Kernel debugger for MN10300
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_KGDB_H
-#define _ASM_KGDB_H
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound
- * buffers at least NUMREGBYTES*2 are needed for register packets
- * Longer buffer is needed to list all threads
- */
-#define BUFMAX 1024
-
-/*
- * Note that this register image is in a different order than the register
- * image that Linux produces at interrupt time.
- */
-enum regnames {
- GDB_FR_D0 = 0,
- GDB_FR_D1 = 1,
- GDB_FR_D2 = 2,
- GDB_FR_D3 = 3,
- GDB_FR_A0 = 4,
- GDB_FR_A1 = 5,
- GDB_FR_A2 = 6,
- GDB_FR_A3 = 7,
-
- GDB_FR_SP = 8,
- GDB_FR_PC = 9,
- GDB_FR_MDR = 10,
- GDB_FR_EPSW = 11,
- GDB_FR_LIR = 12,
- GDB_FR_LAR = 13,
- GDB_FR_MDRQ = 14,
-
- GDB_FR_E0 = 15,
- GDB_FR_E1 = 16,
- GDB_FR_E2 = 17,
- GDB_FR_E3 = 18,
- GDB_FR_E4 = 19,
- GDB_FR_E5 = 20,
- GDB_FR_E6 = 21,
- GDB_FR_E7 = 22,
-
- GDB_FR_SSP = 23,
- GDB_FR_MSP = 24,
- GDB_FR_USP = 25,
- GDB_FR_MCRH = 26,
- GDB_FR_MCRL = 27,
- GDB_FR_MCVF = 28,
-
- GDB_FR_FPCR = 29,
- GDB_FR_DUMMY0 = 30,
- GDB_FR_DUMMY1 = 31,
-
- GDB_FR_FS0 = 32,
-
- GDB_FR_SIZE = 64,
-};
-
-#define GDB_ORIG_D0 41
-#define NUMREGBYTES (GDB_FR_SIZE*4)
-
-static inline void arch_kgdb_breakpoint(void)
-{
- asm(".globl __arch_kgdb_breakpoint; __arch_kgdb_breakpoint: break");
-}
-extern u8 __arch_kgdb_breakpoint;
-
-#define BREAK_INSTR_SIZE 1
-#define CACHE_FLUSH_IS_SAFE 1
-
-#endif /* _ASM_KGDB_H */
diff --git a/arch/mn10300/include/asm/kmap_types.h b/arch/mn10300/include/asm/kmap_types.h
deleted file mode 100644
index f444d7ffa766..000000000000
--- a/arch/mn10300/include/asm/kmap_types.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-#include <asm-generic/kmap_types.h>
-
-#endif /* _ASM_KMAP_TYPES_H */
diff --git a/arch/mn10300/include/asm/kprobes.h b/arch/mn10300/include/asm/kprobes.h
deleted file mode 100644
index 7abea0bdb549..000000000000
--- a/arch/mn10300/include/asm/kprobes.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* MN10300 Kernel Probes support
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by Mark Salter (msalter@redhat.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public Licence as published by
- * the Free Software Foundation; either version 2 of the Licence, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public Licence for more details.
- *
- * You should have received a copy of the GNU General Public Licence
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- *
- */
-#ifndef _ASM_KPROBES_H
-#define _ASM_KPROBES_H
-
-#include <asm-generic/kprobes.h>
-
-#define BREAKPOINT_INSTRUCTION 0xff
-
-#ifdef CONFIG_KPROBES
-#include <linux/types.h>
-#include <linux/ptrace.h>
-
-struct kprobe;
-
-typedef unsigned char kprobe_opcode_t;
-#define MAX_INSN_SIZE 8
-#define MAX_STACK_SIZE 128
-
-/* Architecture specific copy of original instruction */
-struct arch_specific_insn {
- /* copy of original instruction
- */
- kprobe_opcode_t insn[MAX_INSN_SIZE];
-};
-
-extern const int kretprobe_blacklist_size;
-
-extern int kprobe_exceptions_notify(struct notifier_block *self,
- unsigned long val, void *data);
-
-#define flush_insn_slot(p) do {} while (0)
-
-extern void arch_remove_kprobe(struct kprobe *p);
-
-#endif /* CONFIG_KPROBES */
-#endif /* _ASM_KPROBES_H */
diff --git a/arch/mn10300/include/asm/linkage.h b/arch/mn10300/include/asm/linkage.h
deleted file mode 100644
index dda3002a5dfa..000000000000
--- a/arch/mn10300/include/asm/linkage.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* MN10300 Linkage and calling-convention overrides
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_LINKAGE_H
-#define _ASM_LINKAGE_H
-
-/* don't override anything */
-#define asmlinkage
-
-#define __ALIGN .align 4,0xcb
-#define __ALIGN_STR ".align 4,0xcb"
-
-#endif
diff --git a/arch/mn10300/include/asm/local.h b/arch/mn10300/include/asm/local.h
deleted file mode 100644
index c11c530f74d0..000000000000
--- a/arch/mn10300/include/asm/local.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local.h>
diff --git a/arch/mn10300/include/asm/local64.h b/arch/mn10300/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/mn10300/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/mn10300/include/asm/mc146818rtc.h b/arch/mn10300/include/asm/mc146818rtc.h
deleted file mode 100644
index df6bc6e0e8c6..000000000000
--- a/arch/mn10300/include/asm/mc146818rtc.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm/rtc-regs.h>
diff --git a/arch/mn10300/include/asm/mmu.h b/arch/mn10300/include/asm/mmu.h
deleted file mode 100644
index b9d6d41adace..000000000000
--- a/arch/mn10300/include/asm/mmu.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* MN10300 Memory management context
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-frv/mmu.h
- */
-
-#ifndef _ASM_MMU_H
-#define _ASM_MMU_H
-
-/*
- * MMU context
- */
-typedef struct {
- unsigned long tlbpid[NR_CPUS]; /* TLB PID for this process on
- * each CPU */
-} mm_context_t;
-
-#endif /* _ASM_MMU_H */
diff --git a/arch/mn10300/include/asm/mmu_context.h b/arch/mn10300/include/asm/mmu_context.h
deleted file mode 100644
index d2034f5e6eda..000000000000
--- a/arch/mn10300/include/asm/mmu_context.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/* MN10300 MMU context management
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- * - Derived from include/asm-m32r/mmu_context.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- *
- *
- * This implements an algorithm to provide TLB PID mappings to provide
- * selective access to the TLB for processes, thus reducing the number of TLB
- * flushes required.
- *
- * Note, however, that the M32R algorithm is technically broken as it does not
- * handle version wrap-around, and could, theoretically, have a problem with a
- * very long lived program that sleeps long enough for the version number to
- * wrap all the way around so that its TLB mappings appear valid once again.
- */
-#ifndef _ASM_MMU_CONTEXT_H
-#define _ASM_MMU_CONTEXT_H
-
-#include <linux/atomic.h>
-#include <linux/mm_types.h>
-
-#include <asm/pgalloc.h>
-#include <asm/tlbflush.h>
-#include <asm-generic/mm_hooks.h>
-
-#define MMU_CONTEXT_TLBPID_NR 256
-#define MMU_CONTEXT_TLBPID_MASK 0x000000ffUL
-#define MMU_CONTEXT_VERSION_MASK 0xffffff00UL
-#define MMU_CONTEXT_FIRST_VERSION 0x00000100UL
-#define MMU_NO_CONTEXT 0x00000000UL
-#define MMU_CONTEXT_TLBPID_LOCK_NR 0
-
-#define enter_lazy_tlb(mm, tsk) do {} while (0)
-
-static inline void cpu_ran_vm(int cpu, struct mm_struct *mm)
-{
-#ifdef CONFIG_SMP
- cpumask_set_cpu(cpu, mm_cpumask(mm));
-#endif
-}
-
-static inline bool cpu_maybe_ran_vm(int cpu, struct mm_struct *mm)
-{
-#ifdef CONFIG_SMP
- return cpumask_test_and_set_cpu(cpu, mm_cpumask(mm));
-#else
- return true;
-#endif
-}
-
-#ifdef CONFIG_MN10300_TLB_USE_PIDR
-extern unsigned long mmu_context_cache[NR_CPUS];
-#define mm_context(mm) (mm->context.tlbpid[smp_processor_id()])
-
-/**
- * allocate_mmu_context - Allocate storage for the arch-specific MMU data
- * @mm: The userspace VM context being set up
- */
-static inline unsigned long allocate_mmu_context(struct mm_struct *mm)
-{
- unsigned long *pmc = &mmu_context_cache[smp_processor_id()];
- unsigned long mc = ++(*pmc);
-
- if (!(mc & MMU_CONTEXT_TLBPID_MASK)) {
- /* we exhausted the TLB PIDs of this version on this CPU, so we
- * flush this CPU's TLB in its entirety and start new cycle */
- local_flush_tlb_all();
-
- /* fix the TLB version if needed (we avoid version #0 so as to
- * distinguish MMU_NO_CONTEXT) */
- if (!mc)
- *pmc = mc = MMU_CONTEXT_FIRST_VERSION;
- }
- mm_context(mm) = mc;
- return mc;
-}
-
-/*
- * get an MMU context if one is needed
- */
-static inline unsigned long get_mmu_context(struct mm_struct *mm)
-{
- unsigned long mc = MMU_NO_CONTEXT, cache;
-
- if (mm) {
- cache = mmu_context_cache[smp_processor_id()];
- mc = mm_context(mm);
-
- /* if we have an old version of the context, replace it */
- if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK)
- mc = allocate_mmu_context(mm);
- }
- return mc;
-}
-
-/*
- * initialise the context related info for a new mm_struct instance
- */
-static inline int init_new_context(struct task_struct *tsk,
- struct mm_struct *mm)
-{
- int num_cpus = NR_CPUS, i;
-
- for (i = 0; i < num_cpus; i++)
- mm->context.tlbpid[i] = MMU_NO_CONTEXT;
- return 0;
-}
-
-/*
- * after we have set current->mm to a new value, this activates the context for
- * the new mm so we see the new mappings.
- */
-static inline void activate_context(struct mm_struct *mm)
-{
- PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK;
-}
-#else /* CONFIG_MN10300_TLB_USE_PIDR */
-
-#define init_new_context(tsk, mm) (0)
-#define activate_context(mm) local_flush_tlb()
-
-#endif /* CONFIG_MN10300_TLB_USE_PIDR */
-
-/**
- * destroy_context - Destroy mm context information
- * @mm: The MM being destroyed.
- *
- * Destroy context related info for an mm_struct that is about to be put to
- * rest
- */
-#define destroy_context(mm) do {} while (0)
-
-/**
- * switch_mm - Change between userspace virtual memory contexts
- * @prev: The outgoing MM context.
- * @next: The incoming MM context.
- * @tsk: The incoming task.
- */
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- int cpu = smp_processor_id();
-
- if (prev != next) {
-#ifdef CONFIG_SMP
- per_cpu(cpu_tlbstate, cpu).active_mm = next;
-#endif
- cpu_ran_vm(cpu, next);
- PTBR = (unsigned long) next->pgd;
- activate_context(next);
- }
-}
-
-#define deactivate_mm(tsk, mm) do {} while (0)
-#define activate_mm(prev, next) switch_mm((prev), (next), NULL)
-
-#endif /* _ASM_MMU_CONTEXT_H */
diff --git a/arch/mn10300/include/asm/module.h b/arch/mn10300/include/asm/module.h
deleted file mode 100644
index 6571103b0518..000000000000
--- a/arch/mn10300/include/asm/module.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* MN10300 Arch-specific module definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by Mark Salter (msalter@redhat.com)
- * Derived from include/asm-i386/module.h
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_MODULE_H
-#define _ASM_MODULE_H
-
-#include <asm-generic/module.h>
-
-/*
- * Include the MN10300 architecture version.
- */
-#define MODULE_ARCH_VERMAGIC __stringify(PROCESSOR_MODEL_NAME) " "
-
-#endif /* _ASM_MODULE_H */
diff --git a/arch/mn10300/include/asm/nmi.h b/arch/mn10300/include/asm/nmi.h
deleted file mode 100644
index b05627597b1b..000000000000
--- a/arch/mn10300/include/asm/nmi.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* MN10300 NMI handling
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_NMI_H
-#define _ASM_NMI_H
-
-extern void arch_touch_nmi_watchdog(void);
-
-#endif /* _ASM_NMI_H */
diff --git a/arch/mn10300/include/asm/page.h b/arch/mn10300/include/asm/page.h
deleted file mode 100644
index dfe730a5ede0..000000000000
--- a/arch/mn10300/include/asm/page.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* MN10300 Page table definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PAGE_H
-#define _ASM_PAGE_H
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT 12
-
-#ifndef __ASSEMBLY__
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE - 1))
-#else
-#define PAGE_SIZE +(1 << PAGE_SHIFT) /* unary plus marks an
- * immediate val not an addr */
-#define PAGE_MASK +(~(PAGE_SIZE - 1))
-#endif
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
-#define copy_page(to, from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
-
-#define clear_user_page(addr, vaddr, page) clear_page(addr)
-#define copy_user_page(vto, vfrom, vaddr, to) copy_page(vto, vfrom)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define PTE_MASK PAGE_MASK
-#define HPAGE_SHIFT 22
-
-#ifdef CONFIG_HUGETLB_PAGE
-#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
-#define HPAGE_MASK (~(HPAGE_SIZE - 1))
-#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
-#endif
-
-#define pte_val(x) ((x).pte)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) })
-#define __pgd(x) ((pgd_t) { (x) })
-#define __pgprot(x) ((pgprot_t) { (x) })
-
-#define __ARCH_USE_5LEVEL_HACK
-#include <asm-generic/pgtable-nopmd.h>
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * This handles the memory map.. We could make this a config
- * option, but too many people screw it up, and too few need
- * it.
- *
- * A __PAGE_OFFSET of 0xC0000000 means that the kernel has
- * a virtual address space of one gigabyte, which limits the
- * amount of physical memory you can use to about 950MB.
- */
-
-#ifndef __ASSEMBLY__
-
-/* Pure 2^n version of get_order */
-static inline int get_order(unsigned long size) __attribute__((const));
-static inline int get_order(unsigned long size)
-{
- int order;
-
- size = (size - 1) >> (PAGE_SHIFT - 1);
- order = -1;
- do {
- size >>= 1;
- order++;
- } while (size);
- return order;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/page_offset.h>
-
-#define __PAGE_OFFSET (PAGE_OFFSET_RAW)
-#define PAGE_OFFSET ((unsigned long) __PAGE_OFFSET)
-
-/*
- * main RAM and kernel working space are coincident at 0x90000000, but to make
- * life more interesting, there's also an uncached virtual shadow at 0xb0000000
- * - these mappings are fixed in the MMU
- */
-#define __pfn_disp (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT)
-
-#define __pa(x) ((unsigned long)(x))
-#define __va(x) ((void *)(unsigned long)(x))
-#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
-#define pfn_to_page(pfn) (mem_map + ((pfn) - __pfn_disp))
-#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + __pfn_disp)
-#define __pfn_to_phys(pfn) PFN_PHYS(pfn)
-
-#define pfn_valid(pfn) \
-({ \
- unsigned long __pfn = (pfn) - __pfn_disp; \
- __pfn < max_mapnr; \
-})
-
-#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | \
- ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_PAGE_H */
diff --git a/arch/mn10300/include/asm/page_offset.h b/arch/mn10300/include/asm/page_offset.h
deleted file mode 100644
index 1e869aa09418..000000000000
--- a/arch/mn10300/include/asm/page_offset.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* MN10300 Kernel base address
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- */
-#ifndef _ASM_PAGE_OFFSET_H
-#define _ASM_PAGE_OFFSET_H
-
-#define PAGE_OFFSET_RAW CONFIG_KERNEL_RAM_BASE_ADDRESS
-
-#endif
diff --git a/arch/mn10300/include/asm/pci.h b/arch/mn10300/include/asm/pci.h
deleted file mode 100644
index 5b75a1b2c4f6..000000000000
--- a/arch/mn10300/include/asm/pci.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* MN10300 PCI definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PCI_H
-#define _ASM_PCI_H
-
-#ifdef __KERNEL__
-#include <linux/mm.h> /* for struct page */
-
-#if 0
-#define __pcbdebug(FMT, ADDR, ...) \
- printk(KERN_DEBUG "PCIBRIDGE[%08x]: "FMT"\n", \
- (u32)(ADDR), ##__VA_ARGS__)
-
-#define __pcidebug(FMT, BUS, DEVFN, WHERE,...) \
-do { \
- printk(KERN_DEBUG "PCI[%02x:%02x.%x + %02x]: "FMT"\n", \
- (BUS)->number, \
- PCI_SLOT(DEVFN), \
- PCI_FUNC(DEVFN), \
- (u32)(WHERE), ##__VA_ARGS__); \
-} while (0)
-
-#else
-#define __pcbdebug(FMT, ADDR, ...) do {} while (0)
-#define __pcidebug(FMT, BUS, DEVFN, WHERE, ...) do {} while (0)
-#endif
-
-/* Can be used to override the logic in pci_scan_bus for skipping
- * already-configured bus numbers - to be used for buggy BIOSes or
- * architectures with incomplete PCI setup by the loader */
-
-#ifdef CONFIG_PCI
-#define pcibios_assign_all_busses() 1
-extern void unit_pci_init(void);
-#else
-#define pcibios_assign_all_busses() 0
-#endif
-
-#define PCIBIOS_MIN_IO 0xBE000004
-#define PCIBIOS_MIN_MEM 0xB8000000
-
-/* Dynamic DMA mapping stuff.
- * i386 has everything mapped statically.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/scatterlist.h>
-#include <linux/string.h>
-#include <asm/io.h>
-
-/* The PCI address space does equal the physical memory
- * address space. The networking and block device layers use
- * this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS (1)
-
-/* Return the index of the PCI controller for device. */
-static inline int pci_controller_num(struct pci_dev *dev)
-{
- return 0;
-}
-
-#define HAVE_PCI_MMAP
-#define ARCH_GENERIC_PCI_MMAP_RESOURCE
-
-#endif /* __KERNEL__ */
-
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
- return channel ? 15 : 14;
-}
-
-#include <asm-generic/pci_iomap.h>
-
-#endif /* _ASM_PCI_H */
diff --git a/arch/mn10300/include/asm/percpu.h b/arch/mn10300/include/asm/percpu.h
deleted file mode 100644
index 06a959d67234..000000000000
--- a/arch/mn10300/include/asm/percpu.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/percpu.h>
diff --git a/arch/mn10300/include/asm/pgalloc.h b/arch/mn10300/include/asm/pgalloc.h
deleted file mode 100644
index 0f25d5fa86f3..000000000000
--- a/arch/mn10300/include/asm/pgalloc.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* MN10300 Page and page table/directory allocation
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PGALLOC_H
-#define _ASM_PGALLOC_H
-
-#include <asm/page.h>
-#include <linux/threads.h>
-#include <linux/mm.h> /* for struct page */
-
-struct mm_struct;
-struct page;
-
-/* attach a page table to a PMD entry */
-#define pmd_populate_kernel(mm, pmd, pte) \
- set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE))
-
-static inline
-void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte)
-{
- set_pmd(pmd, __pmd((page_to_pfn(pte) << PAGE_SHIFT) | _PAGE_TABLE));
-}
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Allocate and free page tables.
- */
-
-extern pgd_t *pgd_alloc(struct mm_struct *);
-extern void pgd_free(struct mm_struct *, pgd_t *);
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-extern struct page *pte_alloc_one(struct mm_struct *, unsigned long);
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_page((unsigned long) pte);
-}
-
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
-{
- pgtable_page_dtor(pte);
- __free_page(pte);
-}
-
-
-#define __pte_free_tlb(tlb, pte, addr) tlb_remove_page((tlb), (pte))
-
-#endif /* _ASM_PGALLOC_H */
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
deleted file mode 100644
index 96d3f9deb59c..000000000000
--- a/arch/mn10300/include/asm/pgtable.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/* MN10300 Page table manipulators and constants
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- *
- *
- * The Linux memory management assumes a three-level page table setup. On
- * the i386, we use that, but "fold" the mid level into the top-level page
- * table, so that we physically have the same two-level page table as the
- * i386 mmu expects.
- *
- * This file contains the functions and defines necessary to modify and use
- * the i386 page table tree for the purposes of the MN10300 TLB handler
- * functions.
- */
-#ifndef _ASM_PGTABLE_H
-#define _ASM_PGTABLE_H
-
-#include <asm/cpu-regs.h>
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <linux/threads.h>
-
-#include <asm/bitops.h>
-
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-extern unsigned long empty_zero_page[1024];
-extern spinlock_t pgd_lock;
-extern struct page *pgd_list;
-
-extern void pmd_ctor(void *, struct kmem_cache *, unsigned long);
-extern void pgtable_cache_init(void);
-extern void paging_init(void);
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * The Linux mn10300 paging architecture only implements both the traditional
- * 2-level page tables
- */
-#define PGDIR_SHIFT 22
-#define PTRS_PER_PGD 1024
-#define PTRS_PER_PUD 1 /* we don't really have any PUD physically */
-#define __PAGETABLE_PUD_FOLDED
-#define PTRS_PER_PMD 1 /* we don't really have any PMD physically */
-#define __PAGETABLE_PMD_FOLDED
-#define PTRS_PER_PTE 1024
-
-#define PGD_SIZE PAGE_SIZE
-#define PMD_SIZE (1UL << PMD_SHIFT)
-#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-
-#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD - USER_PGD_PTRS)
-
-#define TWOLEVEL_PGDIR_SHIFT 22
-#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
-#define BOOT_KERNEL_PGD_PTRS (1024 - BOOT_USER_PGD_PTRS)
-
-#ifndef __ASSEMBLY__
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-#endif
-
-/*
- * Unfortunately, due to the way the MMU works on the MN10300, the vmalloc VM
- * area has to be in the lower half of the virtual address range (the upper
- * half is not translated through the TLB).
- *
- * So in this case, the vmalloc area goes at the bottom of the address map
- * (leaving a hole at the very bottom to catch addressing errors), and
- * userspace starts immediately above.
- *
- * The vmalloc() routines also leaves a hole of 4kB between each vmalloced
- * area to catch addressing errors.
- */
-#ifndef __ASSEMBLY__
-#define VMALLOC_OFFSET (8UL * 1024 * 1024)
-#define VMALLOC_START (0x70000000UL)
-#define VMALLOC_END (0x7C000000UL)
-#else
-#define VMALLOC_OFFSET (8 * 1024 * 1024)
-#define VMALLOC_START (0x70000000)
-#define VMALLOC_END (0x7C000000)
-#endif
-
-#ifndef __ASSEMBLY__
-extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE];
-#endif
-
-/* IPTEL2/DPTEL2 bit assignments */
-#define _PAGE_BIT_VALID xPTEL2_V_BIT
-#define _PAGE_BIT_CACHE xPTEL2_C_BIT
-#define _PAGE_BIT_PRESENT xPTEL2_PV_BIT
-#define _PAGE_BIT_DIRTY xPTEL2_D_BIT
-#define _PAGE_BIT_GLOBAL xPTEL2_G_BIT
-#define _PAGE_BIT_ACCESSED xPTEL2_UNUSED1_BIT /* mustn't be loaded into IPTEL2/DPTEL2 */
-
-#define _PAGE_VALID xPTEL2_V
-#define _PAGE_CACHE xPTEL2_C
-#define _PAGE_PRESENT xPTEL2_PV
-#define _PAGE_DIRTY xPTEL2_D
-#define _PAGE_PROT xPTEL2_PR
-#define _PAGE_PROT_RKNU xPTEL2_PR_ROK
-#define _PAGE_PROT_WKNU xPTEL2_PR_RWK
-#define _PAGE_PROT_RKRU xPTEL2_PR_ROK_ROU
-#define _PAGE_PROT_WKRU xPTEL2_PR_RWK_ROU
-#define _PAGE_PROT_WKWU xPTEL2_PR_RWK_RWU
-#define _PAGE_GLOBAL xPTEL2_G
-#define _PAGE_PS_MASK xPTEL2_PS
-#define _PAGE_PS_4Kb xPTEL2_PS_4Kb
-#define _PAGE_PS_128Kb xPTEL2_PS_128Kb
-#define _PAGE_PS_1Kb xPTEL2_PS_1Kb
-#define _PAGE_PS_4Mb xPTEL2_PS_4Mb
-#define _PAGE_PSE xPTEL2_PS_4Mb /* 4MB page */
-#define _PAGE_CACHE_WT xPTEL2_CWT
-#define _PAGE_ACCESSED xPTEL2_UNUSED1
-#define _PAGE_NX 0 /* no-execute bit */
-
-/* If _PAGE_VALID is clear, we use these: */
-#define _PAGE_PROTNONE 0x000 /* If not present */
-
-#define __PAGE_PROT_UWAUX 0x010
-#define __PAGE_PROT_USER 0x020
-#define __PAGE_PROT_WRITE 0x040
-
-#define _PAGE_PRESENTV (_PAGE_PRESENT|_PAGE_VALID)
-
-#ifndef __ASSEMBLY__
-
-#define VMALLOC_VMADDR(x) ((unsigned long)(x))
-
-#define _PAGE_TABLE (_PAGE_PRESENTV | _PAGE_PROT_WKNU | _PAGE_ACCESSED | _PAGE_DIRTY)
-#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
-
-#define __PAGE_NONE (_PAGE_PRESENTV | _PAGE_PROT_RKNU | _PAGE_ACCESSED | _PAGE_CACHE)
-#define __PAGE_SHARED (_PAGE_PRESENTV | _PAGE_PROT_WKWU | _PAGE_ACCESSED | _PAGE_CACHE)
-#define __PAGE_COPY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE)
-#define __PAGE_READONLY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE)
-
-#define PAGE_NONE __pgprot(__PAGE_NONE | _PAGE_NX)
-#define PAGE_SHARED_NOEXEC __pgprot(__PAGE_SHARED | _PAGE_NX)
-#define PAGE_COPY_NOEXEC __pgprot(__PAGE_COPY | _PAGE_NX)
-#define PAGE_READONLY_NOEXEC __pgprot(__PAGE_READONLY | _PAGE_NX)
-#define PAGE_SHARED_EXEC __pgprot(__PAGE_SHARED)
-#define PAGE_COPY_EXEC __pgprot(__PAGE_COPY)
-#define PAGE_READONLY_EXEC __pgprot(__PAGE_READONLY)
-#define PAGE_COPY PAGE_COPY_NOEXEC
-#define PAGE_READONLY PAGE_READONLY_NOEXEC
-#define PAGE_SHARED PAGE_SHARED_EXEC
-
-#define __PAGE_KERNEL_BASE (_PAGE_PRESENTV | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
-
-#define __PAGE_KERNEL (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_CACHE | _PAGE_NX)
-#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_NX)
-#define __PAGE_KERNEL_EXEC (__PAGE_KERNEL & ~_PAGE_NX)
-#define __PAGE_KERNEL_RO (__PAGE_KERNEL_BASE | _PAGE_PROT_RKNU | _PAGE_CACHE | _PAGE_NX)
-#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
-#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
-
-#define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
-#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
-#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
-#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
-#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
-#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
-
-#define __PAGE_USERIO (__PAGE_KERNEL_BASE | _PAGE_PROT_WKWU | _PAGE_NX)
-#define PAGE_USERIO __pgprot(__PAGE_USERIO)
-
-/*
- * Whilst the MN10300 can do page protection for execute (given separate data
- * and insn TLBs), we are not supporting it at the moment. Write permission,
- * however, always implies read permission (but not execute permission).
- */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY_NOEXEC
-#define __P010 PAGE_COPY_NOEXEC
-#define __P011 PAGE_COPY_NOEXEC
-#define __P100 PAGE_READONLY_EXEC
-#define __P101 PAGE_READONLY_EXEC
-#define __P110 PAGE_COPY_EXEC
-#define __P111 PAGE_COPY_EXEC
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY_NOEXEC
-#define __S010 PAGE_SHARED_NOEXEC
-#define __S011 PAGE_SHARED_NOEXEC
-#define __S100 PAGE_READONLY_EXEC
-#define __S101 PAGE_READONLY_EXEC
-#define __S110 PAGE_SHARED_EXEC
-#define __S111 PAGE_SHARED_EXEC
-
-/*
- * Define this to warn about kernel memory accesses that are
- * done without a 'verify_area(VERIFY_WRITE,..)'
- */
-#undef TEST_VERIFY_AREA
-
-#define pte_present(x) (pte_val(x) & _PAGE_VALID)
-#define pte_clear(mm, addr, xp) \
-do { \
- set_pte_at((mm), (addr), (xp), __pte(0)); \
-} while (0)
-
-#define pmd_none(x) (!pmd_val(x))
-#define pmd_present(x) (!pmd_none(x))
-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x) 0
-
-
-#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
-
-#ifndef __ASSEMBLY__
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_user(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; }
-static inline int pte_read(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; }
-static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
-static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_write(pte_t pte) { return pte_val(pte) & __PAGE_PROT_WRITE; }
-static inline int pte_special(pte_t pte){ return 0; }
-
-static inline pte_t pte_rdprotect(pte_t pte)
-{
- pte_val(pte) &= ~(__PAGE_PROT_USER|__PAGE_PROT_UWAUX); return pte;
-}
-static inline pte_t pte_exprotect(pte_t pte)
-{
- pte_val(pte) |= _PAGE_NX; return pte;
-}
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- pte_val(pte) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); return pte;
-}
-
-static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_NX; return pte; }
-
-static inline pte_t pte_mkread(pte_t pte)
-{
- pte_val(pte) |= __PAGE_PROT_USER;
- if (pte_write(pte))
- pte_val(pte) |= __PAGE_PROT_UWAUX;
- return pte;
-}
-static inline pte_t pte_mkwrite(pte_t pte)
-{
- pte_val(pte) |= __PAGE_PROT_WRITE;
- if (pte_val(pte) & __PAGE_PROT_USER)
- pte_val(pte) |= __PAGE_PROT_UWAUX;
- return pte;
-}
-
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-
-#define pte_ERROR(e) \
- printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
- __FILE__, __LINE__, pte_val(e))
-#define pgd_ERROR(e) \
- printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
- __FILE__, __LINE__, pgd_val(e))
-
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-#define pgd_clear(xp) do { } while (0)
-
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte((ptep), (pteval))
-#define set_pte_atomic(pteptr, pteval) set_pte((pteptr), (pteval))
-
-/*
- * (pmds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
-
-#define ptep_get_and_clear(mm, addr, ptep) \
- __pte(xchg(&(ptep)->pte, 0))
-#define pte_same(a, b) (pte_val(a) == pte_val(b))
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-#define pte_none(x) (!pte_val(x))
-#define pte_pfn(x) ((unsigned long) (pte_val(x) >> PAGE_SHIFT))
-#define __pfn_addr(pfn) ((pfn) << PAGE_SHIFT)
-#define pfn_pte(pfn, prot) __pte(__pfn_addr(pfn) | pgprot_val(prot))
-#define pfn_pmd(pfn, prot) __pmd(__pfn_addr(pfn) | pgprot_val(prot))
-
-/*
- * All present user pages are user-executable:
- */
-static inline int pte_exec(pte_t pte)
-{
- return pte_user(pte);
-}
-
-/*
- * All present pages are kernel-executable:
- */
-static inline int pte_exec_kernel(pte_t pte)
-{
- return 1;
-}
-
-/* Encode and de-code a swap entry */
-#define __swp_type(x) (((x).val >> 1) & 0x3f)
-#define __swp_offset(x) ((x).val >> 7)
-#define __swp_entry(type, offset) \
- ((swp_entry_t) { ((type) << 1) | ((offset) << 7) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x) __pte((x).val)
-
-static inline
-int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr,
- pte_t *ptep)
-{
- if (!pte_dirty(*ptep))
- return 0;
- return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte);
-}
-
-static inline
-int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
- pte_t *ptep)
-{
- if (!pte_young(*ptep))
- return 0;
- return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte);
-}
-
-static inline
-void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
- pte_val(*ptep) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX);
-}
-
-static inline void ptep_mkdirty(pte_t *ptep)
-{
- set_bit(_PAGE_BIT_DIRTY, &ptep->pte);
-}
-
-/*
- * Macro to mark a page protection value as "uncacheable". On processors which
- * do not support it, this is a no-op.
- */
-#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHE)
-
-/*
- * Macro to mark a page protection value as "Write-Through".
- * On processors which do not support it, this is a no-op.
- */
-#define pgprot_through(prot) __pgprot(pgprot_val(prot) | _PAGE_CACHE_WT)
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-#define mk_pte_huge(entry) \
- ((entry).pte |= _PAGE_PRESENT | _PAGE_PSE | _PAGE_VALID)
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- pte_val(pte) &= _PAGE_CHG_MASK;
- pte_val(pte) |= pgprot_val(newprot);
- return pte;
-}
-
-#define page_pte(page) page_pte_prot((page), __pgprot(0))
-
-#define pmd_page_kernel(pmd) \
- ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
-#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
-
-#define pmd_large(pmd) \
- ((pmd_val(pmd) & (_PAGE_PSE | _PAGE_PRESENT)) == \
- (_PAGE_PSE | _PAGE_PRESENT))
-
-/*
- * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
- *
- * this macro returns the index of the entry in the pgd page which would
- * control the given virtual address
- */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-
-/*
- * pgd_offset() returns a (pgd_t *)
- * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
- */
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/*
- * a shortcut which implies the use of the kernel's pgd, instead
- * of a process's
- */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/*
- * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
- *
- * this macro returns the index of the entry in the pmd page which would
- * control the given virtual address
- */
-#define pmd_index(address) \
- (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
-
-/*
- * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
- *
- * this macro returns the index of the entry in the pte page which would
- * control the given virtual address
- */
-#define pte_index(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
-
-/*
- * Make a given kernel text page executable/non-executable.
- * Returns the previous executability setting of that page (which
- * is used to restore the previous state). Used by the SMP bootup code.
- * NOTE: this is an __init function for security reasons.
- */
-static inline int set_kernel_exec(unsigned long vaddr, int enable)
-{
- return 0;
-}
-
-#define pte_offset_map(dir, address) \
- ((pte_t *) page_address(pmd_page(*(dir))) + pte_index(address))
-#define pte_unmap(pte) do {} while (0)
-
-/*
- * The MN10300 has external MMU info in the form of a TLB: this is adapted from
- * the kernel page tables containing the necessary information by tlb-mn10300.S
- */
-extern void update_mmu_cache(struct vm_area_struct *vma,
- unsigned long address, pte_t *ptep);
-
-#endif /* !__ASSEMBLY__ */
-
-#define kern_addr_valid(addr) (1)
-
-#define MK_IOSPACE_PFN(space, pfn) (pfn)
-#define GET_IOSPACE(pfn) 0
-#define GET_PFN(pfn) (pfn)
-
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define __HAVE_ARCH_PTEP_MKDIRTY
-#define __HAVE_ARCH_PTE_SAME
-#include <asm-generic/pgtable.h>
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_PGTABLE_H */
diff --git a/arch/mn10300/include/asm/pio-regs.h b/arch/mn10300/include/asm/pio-regs.h
deleted file mode 100644
index 96bc8182d0ba..000000000000
--- a/arch/mn10300/include/asm/pio-regs.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/* MN10300 On-board I/O port module registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PIO_REGS_H
-#define _ASM_PIO_REGS_H
-
-#include <asm/cpu-regs.h>
-#include <asm/intctl-regs.h>
-
-#ifdef __KERNEL__
-
-/* I/O port 0 */
-#define P0MD __SYSREG(0xdb000000, u16) /* mode reg */
-#define P0MD_0 0x0003 /* mask */
-#define P0MD_0_IN 0x0000 /* input mode */
-#define P0MD_0_OUT 0x0001 /* output mode */
-#define P0MD_0_TM0IO 0x0002 /* timer 0 I/O mode */
-#define P0MD_0_EYECLK 0x0003 /* test signal output (clock) */
-#define P0MD_1 0x000c
-#define P0MD_1_IN 0x0000
-#define P0MD_1_OUT 0x0004
-#define P0MD_1_TM1IO 0x0008 /* timer 1 I/O mode */
-#define P0MD_1_EYED 0x000c /* test signal output (data) */
-#define P0MD_2 0x0030
-#define P0MD_2_IN 0x0000
-#define P0MD_2_OUT 0x0010
-#define P0MD_2_TM2IO 0x0020 /* timer 2 I/O mode */
-#define P0MD_3 0x00c0
-#define P0MD_3_IN 0x0000
-#define P0MD_3_OUT 0x0040
-#define P0MD_3_TM3IO 0x0080 /* timer 3 I/O mode */
-#define P0MD_4 0x0300
-#define P0MD_4_IN 0x0000
-#define P0MD_4_OUT 0x0100
-#define P0MD_4_TM4IO 0x0200 /* timer 4 I/O mode */
-#define P0MD_4_XCTS 0x0300 /* XCTS input for serial port 2 */
-#define P0MD_5 0x0c00
-#define P0MD_5_IN 0x0000
-#define P0MD_5_OUT 0x0400
-#define P0MD_5_TM5IO 0x0800 /* timer 5 I/O mode */
-#define P0MD_6 0x3000
-#define P0MD_6_IN 0x0000
-#define P0MD_6_OUT 0x1000
-#define P0MD_6_TM6IOA 0x2000 /* timer 6 I/O mode A */
-#define P0MD_7 0xc000
-#define P0MD_7_IN 0x0000
-#define P0MD_7_OUT 0x4000
-#define P0MD_7_TM6IOB 0x8000 /* timer 6 I/O mode B */
-
-#define P0IN __SYSREG(0xdb000004, u8) /* in reg */
-#define P0OUT __SYSREG(0xdb000008, u8) /* out reg */
-
-#define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */
-#define P0TMIO_TM0_IN 0x00
-#define P0TMIO_TM0_OUT 0x01
-#define P0TMIO_TM1_IN 0x00
-#define P0TMIO_TM1_OUT 0x02
-#define P0TMIO_TM2_IN 0x00
-#define P0TMIO_TM2_OUT 0x04
-#define P0TMIO_TM3_IN 0x00
-#define P0TMIO_TM3_OUT 0x08
-#define P0TMIO_TM4_IN 0x00
-#define P0TMIO_TM4_OUT 0x10
-#define P0TMIO_TM5_IN 0x00
-#define P0TMIO_TM5_OUT 0x20
-#define P0TMIO_TM6A_IN 0x00
-#define P0TMIO_TM6A_OUT 0x40
-#define P0TMIO_TM6B_IN 0x00
-#define P0TMIO_TM6B_OUT 0x80
-
-/* I/O port 1 */
-#define P1MD __SYSREG(0xdb000100, u16) /* mode reg */
-#define P1MD_0 0x0003 /* mask */
-#define P1MD_0_IN 0x0000 /* input mode */
-#define P1MD_0_OUT 0x0001 /* output mode */
-#define P1MD_0_TM7IO 0x0002 /* timer 7 I/O mode */
-#define P1MD_0_ADTRG 0x0003 /* A/D converter trigger mode */
-#define P1MD_1 0x000c
-#define P1MD_1_IN 0x0000
-#define P1MD_1_OUT 0x0004
-#define P1MD_1_TM8IO 0x0008 /* timer 8 I/O mode */
-#define P1MD_1_XDMR0 0x000c /* DMA request input 0 mode */
-#define P1MD_2 0x0030
-#define P1MD_2_IN 0x0000
-#define P1MD_2_OUT 0x0010
-#define P1MD_2_TM9IO 0x0020 /* timer 9 I/O mode */
-#define P1MD_2_XDMR1 0x0030 /* DMA request input 1 mode */
-#define P1MD_3 0x00c0
-#define P1MD_3_IN 0x0000
-#define P1MD_3_OUT 0x0040
-#define P1MD_3_TM10IO 0x0080 /* timer 10 I/O mode */
-#define P1MD_3_FRQS0 0x00c0 /* CPU clock multiplier setting input 0 mode */
-#define P1MD_4 0x0300
-#define P1MD_4_IN 0x0000
-#define P1MD_4_OUT 0x0100
-#define P1MD_4_TM11IO 0x0200 /* timer 11 I/O mode */
-#define P1MD_4_FRQS1 0x0300 /* CPU clock multiplier setting input 1 mode */
-
-#define P1IN __SYSREG(0xdb000104, u8) /* in reg */
-#define P1OUT __SYSREG(0xdb000108, u8) /* out reg */
-#define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */
-#define P1TMIO_TM11_IN 0x00
-#define P1TMIO_TM11_OUT 0x01
-#define P1TMIO_TM10_IN 0x00
-#define P1TMIO_TM10_OUT 0x02
-#define P1TMIO_TM9_IN 0x00
-#define P1TMIO_TM9_OUT 0x04
-#define P1TMIO_TM8_IN 0x00
-#define P1TMIO_TM8_OUT 0x08
-#define P1TMIO_TM7_IN 0x00
-#define P1TMIO_TM7_OUT 0x10
-
-/* I/O port 2 */
-#define P2MD __SYSREG(0xdb000200, u16) /* mode reg */
-#define P2MD_0 0x0003 /* mask */
-#define P2MD_0_IN 0x0000 /* input mode */
-#define P2MD_0_OUT 0x0001 /* output mode */
-#define P2MD_0_BOOTBW 0x0003 /* boot bus width selector mode */
-#define P2MD_1 0x000c
-#define P2MD_1_IN 0x0000
-#define P2MD_1_OUT 0x0004
-#define P2MD_1_BOOTSEL 0x000c /* boot device selector mode */
-#define P2MD_2 0x0030
-#define P2MD_2_IN 0x0000
-#define P2MD_2_OUT 0x0010
-#define P2MD_3 0x00c0
-#define P2MD_3_IN 0x0000
-#define P2MD_3_OUT 0x0040
-#define P2MD_3_CKIO 0x00c0 /* mode */
-#define P2MD_4 0x0300
-#define P2MD_4_IN 0x0000
-#define P2MD_4_OUT 0x0100
-#define P2MD_4_CMOD 0x0300 /* mode */
-
-#define P2IN __SYSREG(0xdb000204, u8) /* in reg */
-#define P2OUT __SYSREG(0xdb000208, u8) /* out reg */
-#define P2TMIO __SYSREG(0xdb00020c, u8) /* TM pin I/O control reg */
-
-/* I/O port 3 */
-#define P3MD __SYSREG(0xdb000300, u16) /* mode reg */
-#define P3MD_0 0x0003 /* mask */
-#define P3MD_0_IN 0x0000 /* input mode */
-#define P3MD_0_OUT 0x0001 /* output mode */
-#define P3MD_0_AFRXD 0x0002 /* AFR interface mode */
-#define P3MD_1 0x000c
-#define P3MD_1_IN 0x0000
-#define P3MD_1_OUT 0x0004
-#define P3MD_1_AFTXD 0x0008 /* AFR interface mode */
-#define P3MD_2 0x0030
-#define P3MD_2_IN 0x0000
-#define P3MD_2_OUT 0x0010
-#define P3MD_2_AFSCLK 0x0020 /* AFR interface mode */
-#define P3MD_3 0x00c0
-#define P3MD_3_IN 0x0000
-#define P3MD_3_OUT 0x0040
-#define P3MD_3_AFFS 0x0080 /* AFR interface mode */
-#define P3MD_4 0x0300
-#define P3MD_4_IN 0x0000
-#define P3MD_4_OUT 0x0100
-#define P3MD_4_AFEHC 0x0200 /* AFR interface mode */
-
-#define P3IN __SYSREG(0xdb000304, u8) /* in reg */
-#define P3OUT __SYSREG(0xdb000308, u8) /* out reg */
-
-/* I/O port 4 */
-#define P4MD __SYSREG(0xdb000400, u16) /* mode reg */
-#define P4MD_0 0x0003 /* mask */
-#define P4MD_0_IN 0x0000 /* input mode */
-#define P4MD_0_OUT 0x0001 /* output mode */
-#define P4MD_0_SCL0 0x0002 /* I2C/serial mode */
-#define P4MD_1 0x000c
-#define P4MD_1_IN 0x0000
-#define P4MD_1_OUT 0x0004
-#define P4MD_1_SDA0 0x0008
-#define P4MD_2 0x0030
-#define P4MD_2_IN 0x0000
-#define P4MD_2_OUT 0x0010
-#define P4MD_2_SCL1 0x0020
-#define P4MD_3 0x00c0
-#define P4MD_3_IN 0x0000
-#define P4MD_3_OUT 0x0040
-#define P4MD_3_SDA1 0x0080
-#define P4MD_4 0x0300
-#define P4MD_4_IN 0x0000
-#define P4MD_4_OUT 0x0100
-#define P4MD_4_SBO0 0x0200
-#define P4MD_5 0x0c00
-#define P4MD_5_IN 0x0000
-#define P4MD_5_OUT 0x0400
-#define P4MD_5_SBO1 0x0800
-#define P4MD_6 0x3000
-#define P4MD_6_IN 0x0000
-#define P4MD_6_OUT 0x1000
-#define P4MD_6_SBT0 0x2000
-#define P4MD_7 0xc000
-#define P4MD_7_IN 0x0000
-#define P4MD_7_OUT 0x4000
-#define P4MD_7_SBT1 0x8000
-
-#define P4IN __SYSREG(0xdb000404, u8) /* in reg */
-#define P4OUT __SYSREG(0xdb000408, u8) /* out reg */
-
-/* I/O port 5 */
-#define P5MD __SYSREG(0xdb000500, u16) /* mode reg */
-#define P5MD_0 0x0003 /* mask */
-#define P5MD_0_IN 0x0000 /* input mode */
-#define P5MD_0_OUT 0x0001 /* output mode */
-#define P5MD_0_IRTXD 0x0002 /* IrDA mode */
-#define P5MD_0_SOUT 0x0004 /* serial mode */
-#define P5MD_1 0x000c
-#define P5MD_1_IN 0x0000
-#define P5MD_1_OUT 0x0004
-#define P5MD_1_IRRXDS 0x0008 /* IrDA mode */
-#define P5MD_1_SIN 0x000c /* serial mode */
-#define P5MD_2 0x0030
-#define P5MD_2_IN 0x0000
-#define P5MD_2_OUT 0x0010
-#define P5MD_2_IRRXDF 0x0020 /* IrDA mode */
-
-#define P5IN __SYSREG(0xdb000504, u8) /* in reg */
-#define P5OUT __SYSREG(0xdb000508, u8) /* out reg */
-
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_PIO_REGS_H */
diff --git a/arch/mn10300/include/asm/processor.h b/arch/mn10300/include/asm/processor.h
deleted file mode 100644
index 3ae479117b42..000000000000
--- a/arch/mn10300/include/asm/processor.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* MN10300 Processor specifics
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROCESSOR_H
-#define _ASM_PROCESSOR_H
-
-#include <linux/threads.h>
-#include <linux/thread_info.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-#include <asm/cpu-regs.h>
-#include <asm/current.h>
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-struct mm_struct;
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() \
-({ \
- void *__pc; \
- asm("mov pc,%0" : "=a"(__pc)); \
- __pc; \
-})
-
-extern void get_mem_info(unsigned long *mem_base, unsigned long *mem_size);
-
-extern void show_registers(struct pt_regs *regs);
-
-/*
- * CPU type and hardware bug flags. Kept separately for each CPU.
- * Members of this structure are referenced in head.S, so think twice
- * before touching them. [mj]
- */
-
-struct mn10300_cpuinfo {
- int type;
- unsigned long loops_per_jiffy;
- char hard_math;
-};
-
-extern struct mn10300_cpuinfo boot_cpu_data;
-
-#ifdef CONFIG_SMP
-#if CONFIG_NR_CPUS < 2 || CONFIG_NR_CPUS > 8
-# error Sorry, NR_CPUS should be 2 to 8
-#endif
-extern struct mn10300_cpuinfo cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#else /* CONFIG_SMP */
-#define cpu_data &boot_cpu_data
-#define current_cpu_data boot_cpu_data
-#endif /* CONFIG_SMP */
-
-extern void identify_cpu(struct mn10300_cpuinfo *);
-extern void print_cpu_info(struct mn10300_cpuinfo *);
-extern void dodgy_tsc(void);
-
-#define cpu_relax() barrier()
-
-/*
- * User space process size: 1.75GB (default).
- */
-#define TASK_SIZE 0x70000000
-
-/*
- * Where to put the userspace stack by default
- */
-#define STACK_TOP 0x70000000
-#define STACK_TOP_MAX STACK_TOP
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE 0x30000000
-
-struct fpu_state_struct {
- unsigned long fs[32]; /* fpu registers */
- unsigned long fpcr; /* fpu control register */
-};
-
-struct thread_struct {
- struct pt_regs *uregs; /* userspace register frame */
- unsigned long pc; /* kernel PC */
- unsigned long sp; /* kernel SP */
- unsigned long a3; /* kernel FP */
- unsigned long wchan;
- unsigned long usp;
- unsigned long fpu_flags;
-#define THREAD_USING_FPU 0x00000001 /* T if this task is using the FPU */
-#define THREAD_HAS_FPU 0x00000002 /* T if this task owns the FPU right now */
- struct fpu_state_struct fpu_state;
-};
-
-#define INIT_THREAD \
-{ \
- .uregs = init_uregs, \
- .pc = 0, \
- .sp = 0, \
- .a3 = 0, \
- .wchan = 0, \
-}
-
-#define INIT_MMAP \
-{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, \
- NULL, NULL }
-
-/*
- * do necessary setup to start up a newly executed thread
- */
-static inline void start_thread(struct pt_regs *regs,
- unsigned long new_pc, unsigned long new_sp)
-{
- regs->epsw = EPSW_nSL | EPSW_IE | EPSW_IM;
- regs->pc = new_pc;
- regs->sp = new_sp;
-}
-
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define task_pt_regs(task) ((task)->thread.uregs)
-#define KSTK_EIP(task) (task_pt_regs(task)->pc)
-#define KSTK_ESP(task) (task_pt_regs(task)->sp)
-
-#define KSTK_TOP(info) \
-({ \
- (unsigned long)(info) + THREAD_SIZE; \
-})
-
-#define ARCH_HAS_PREFETCH
-#define ARCH_HAS_PREFETCHW
-
-static inline void prefetch(const void *x)
-{
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-#ifdef CONFIG_MN10300_PROC_MN103E010
- asm volatile ("nop; nop; dcpf (%0)" : : "r"(x));
-#else
- asm volatile ("dcpf (%0)" : : "r"(x));
-#endif
-#endif
-}
-
-static inline void prefetchw(const void *x)
-{
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-#ifdef CONFIG_MN10300_PROC_MN103E010
- asm volatile ("nop; nop; dcpf (%0)" : : "r"(x));
-#else
- asm volatile ("dcpf (%0)" : : "r"(x));
-#endif
-#endif
-}
-
-#endif /* _ASM_PROCESSOR_H */
diff --git a/arch/mn10300/include/asm/ptrace.h b/arch/mn10300/include/asm/ptrace.h
deleted file mode 100644
index 838a3830010e..000000000000
--- a/arch/mn10300/include/asm/ptrace.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* MN10300 Exception frame layout and ptrace constants
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PTRACE_H
-#define _ASM_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-
-#define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL)
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_stack_pointer(regs) ((regs)->sp)
-#define current_pt_regs() current_frame()
-
-#define arch_has_single_step() (1)
-
-#define profile_pc(regs) ((regs)->pc)
-
-#endif /* _ASM_PTRACE_H */
diff --git a/arch/mn10300/include/asm/reset-regs.h b/arch/mn10300/include/asm/reset-regs.h
deleted file mode 100644
index 8ca2a42d365b..000000000000
--- a/arch/mn10300/include/asm/reset-regs.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* MN10300 Reset controller and watchdog timer definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_RESET_REGS_H
-#define _ASM_RESET_REGS_H
-
-#include <asm/cpu-regs.h>
-#include <asm/exceptions.h>
-
-#ifdef __KERNEL__
-
-/*
- * watchdog timer registers
- */
-#define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */
-
-#define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */
-#define WDCTR_WDCK 0x07 /* clock source selection */
-#define WDCTR_WDCK_256th 0x00 /* - OSCI/256 */
-#define WDCTR_WDCK_1024th 0x01 /* - OSCI/1024 */
-#define WDCTR_WDCK_2048th 0x02 /* - OSCI/2048 */
-#define WDCTR_WDCK_16384th 0x03 /* - OSCI/16384 */
-#define WDCTR_WDCK_65536th 0x04 /* - OSCI/65536 */
-#define WDCTR_WDRST 0x40 /* binary counter reset */
-#define WDCTR_WDCNE 0x80 /* watchdog timer enable */
-
-#define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
-#define RSTCTR_CHIPRST 0x01 /* chip reset */
-#define RSTCTR_DBFRST 0x02 /* double fault reset flag */
-#define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */
-#define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */
-
-#ifndef __ASSEMBLY__
-
-static inline void mn10300_proc_hard_reset(void)
-{
- RSTCTR &= ~RSTCTR_CHIPRST;
- RSTCTR |= RSTCTR_CHIPRST;
-}
-
-extern unsigned int watchdog_alert_counter[];
-
-extern void watchdog_go(void);
-extern asmlinkage void watchdog_handler(void);
-extern asmlinkage
-void watchdog_interrupt(struct pt_regs *, enum exception_code);
-
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_RESET_REGS_H */
diff --git a/arch/mn10300/include/asm/rtc-regs.h b/arch/mn10300/include/asm/rtc-regs.h
deleted file mode 100644
index c81cacecb6e3..000000000000
--- a/arch/mn10300/include/asm/rtc-regs.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* MN10300 on-chip Real-Time Clock registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_RTC_REGS_H
-#define _ASM_RTC_REGS_H
-
-#include <asm/intctl-regs.h>
-
-#ifdef __KERNEL__
-
-#define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
-#define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
-#define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
-#define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
-#define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */
-#define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
-#define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
-#define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */
-#define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */
-#define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */
-
-#define RTCRA __SYSREG(0xd860000a, u8)/* RTC control reg A */
-#define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */
-#define RTCRA_RS_NONE 0x00 /* - off */
-#define RTCRA_RS_3_90625ms 0x01 /* - 3.90625ms (1/256s) */
-#define RTCRA_RS_7_8125ms 0x02 /* - 7.8125ms (1/128s) */
-#define RTCRA_RS_122_070us 0x03 /* - 122.070us (1/8192s) */
-#define RTCRA_RS_244_141us 0x04 /* - 244.141us (1/4096s) */
-#define RTCRA_RS_488_281us 0x05 /* - 488.281us (1/2048s) */
-#define RTCRA_RS_976_5625us 0x06 /* - 976.5625us (1/1024s) */
-#define RTCRA_RS_1_953125ms 0x07 /* - 1.953125ms (1/512s) */
-#define RTCRA_RS_3_90624ms 0x08 /* - 3.90624ms (1/256s) */
-#define RTCRA_RS_7_8125ms_b 0x09 /* - 7.8125ms (1/128s) */
-#define RTCRA_RS_15_625ms 0x0a /* - 15.625ms (1/64s) */
-#define RTCRA_RS_31_25ms 0x0b /* - 31.25ms (1/32s) */
-#define RTCRA_RS_62_5ms 0x0c /* - 62.5ms (1/16s) */
-#define RTCRA_RS_125ms 0x0d /* - 125ms (1/8s) */
-#define RTCRA_RS_250ms 0x0e /* - 250ms (1/4s) */
-#define RTCRA_RS_500ms 0x0f /* - 500ms (1/2s) */
-#define RTCRA_DVR 0x40 /* divider reset */
-#define RTCRA_UIP 0x80 /* clock update flag */
-
-#define RTCRB __SYSREG(0xd860000b, u8) /* RTC control reg B */
-#define RTCRB_DSE 0x01 /* daylight savings time enable */
-#define RTCRB_TM 0x02 /* time format */
-#define RTCRB_TM_12HR 0x00 /* - 12 hour format */
-#define RTCRB_TM_24HR 0x02 /* - 24 hour format */
-#define RTCRB_DM 0x04 /* numeric value format */
-#define RTCRB_DM_BCD 0x00 /* - BCD */
-#define RTCRB_DM_BINARY 0x04 /* - binary */
-#define RTCRB_UIE 0x10 /* update interrupt disable */
-#define RTCRB_AIE 0x20 /* alarm interrupt disable */
-#define RTCRB_PIE 0x40 /* periodic interrupt disable */
-#define RTCRB_SET 0x80 /* clock update enable */
-
-#define RTSRC __SYSREG(0xd860000c, u8) /* RTC status reg C */
-#define RTSRC_UF 0x10 /* update end interrupt flag */
-#define RTSRC_AF 0x20 /* alarm interrupt flag */
-#define RTSRC_PF 0x40 /* periodic interrupt flag */
-#define RTSRC_IRQF 0x80 /* interrupt flag */
-
-#define RTIRQ 32
-#define RTICR GxICR(RTIRQ)
-
-/*
- * MC146818 RTC compatibility defs for the MN10300 on-chip RTC
- */
-#define RTC_PORT(x) 0xd8600000
-#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
-
-#define CMOS_READ(addr) __SYSREG(0xd8600000 + (u32)(addr), u8)
-#define CMOS_WRITE(val, addr) \
- do { __SYSREG(0xd8600000 + (u32)(addr), u8) = val; } while (0)
-
-#define RTC_IRQ RTIRQ
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_RTC_REGS_H */
diff --git a/arch/mn10300/include/asm/rtc.h b/arch/mn10300/include/asm/rtc.h
deleted file mode 100644
index 07dc87656197..000000000000
--- a/arch/mn10300/include/asm/rtc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* MN10300 Real time clock definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_RTC_H
-#define _ASM_RTC_H
-
-#ifdef CONFIG_MN10300_RTC
-
-#include <linux/init.h>
-
-extern void __init calibrate_clock(void);
-
-#else /* !CONFIG_MN10300_RTC */
-
-static inline void calibrate_clock(void)
-{
-}
-
-#endif /* !CONFIG_MN10300_RTC */
-
-#endif /* _ASM_RTC_H */
diff --git a/arch/mn10300/include/asm/rwlock.h b/arch/mn10300/include/asm/rwlock.h
deleted file mode 100644
index 6d594d4a0e10..000000000000
--- a/arch/mn10300/include/asm/rwlock.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Helpers used by both rw spinlocks and rw semaphores.
- *
- * Based in part on code from semaphore.h and
- * spinlock.h Copyright 1996 Linus Torvalds.
- *
- * Copyright 1999 Red Hat, Inc.
- *
- * Written by Benjamin LaHaise.
- *
- * Modified by Matsushita Electric Industrial Co., Ltd.
- * Modifications:
- * 13-Nov-2006 MEI Temporarily delete lock functions for SMP support.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- */
-#ifndef _ASM_RWLOCK_H
-#define _ASM_RWLOCK_H
-
-#define RW_LOCK_BIAS 0x01000000
-
-#ifndef CONFIG_SMP
-
-typedef struct { unsigned long a[100]; } __dummy_lock_t;
-#define __dummy_lock(lock) (*(__dummy_lock_t *)(lock))
-
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __build_read_lock_ptr(rw, helper) \
- do { \
- asm volatile( \
- " mov (%0),d3 \n" \
- " sub 1,d3 \n" \
- " mov d3,(%0) \n" \
- " blt 1f \n" \
- " bra 2f \n" \
- "1: jmp 3f \n" \
- "2: \n" \
- " .section .text.lock,\"ax\" \n" \
- "3: call "helper"[],0 \n" \
- " jmp 2b \n" \
- " .previous" \
- : \
- : "d" (rw) \
- : "memory", "d3", "cc"); \
- } while (0)
-
-#define __build_read_lock_const(rw, helper) \
- do { \
- asm volatile( \
- " mov (%0),d3 \n" \
- " sub 1,d3 \n" \
- " mov d3,(%0) \n" \
- " blt 1f \n" \
- " bra 2f \n" \
- "1: jmp 3f \n" \
- "2: \n" \
- " .section .text.lock,\"ax\" \n" \
- "3: call "helper"[],0 \n" \
- " jmp 2b \n" \
- " .previous" \
- : \
- : "d" (rw) \
- : "memory", "d3", "cc"); \
- } while (0)
-
-#define __build_read_lock(rw, helper) \
- do { \
- if (__builtin_constant_p(rw)) \
- __build_read_lock_const(rw, helper); \
- else \
- __build_read_lock_ptr(rw, helper); \
- } while (0)
-
-#define __build_write_lock_ptr(rw, helper) \
- do { \
- asm volatile( \
- " mov (%0),d3 \n" \
- " sub 1,d3 \n" \
- " mov d3,(%0) \n" \
- " blt 1f \n" \
- " bra 2f \n" \
- "1: jmp 3f \n" \
- "2: \n" \
- " .section .text.lock,\"ax\" \n" \
- "3: call "helper"[],0 \n" \
- " jmp 2b \n" \
- " .previous" \
- : \
- : "d" (rw) \
- : "memory", "d3", "cc"); \
- } while (0)
-
-#define __build_write_lock_const(rw, helper) \
- do { \
- asm volatile( \
- " mov (%0),d3 \n" \
- " sub 1,d3 \n" \
- " mov d3,(%0) \n" \
- " blt 1f \n" \
- " bra 2f \n" \
- "1: jmp 3f \n" \
- "2: \n" \
- " .section .text.lock,\"ax\" \n" \
- "3: call "helper"[],0 \n" \
- " jmp 2b \n" \
- " .previous" \
- : \
- : "d" (rw) \
- : "memory", "d3", "cc"); \
- } while (0)
-
-#define __build_write_lock(rw, helper) \
- do { \
- if (__builtin_constant_p(rw)) \
- __build_write_lock_const(rw, helper); \
- else \
- __build_write_lock_ptr(rw, helper); \
- } while (0)
-
-#endif /* CONFIG_SMP */
-#endif /* _ASM_RWLOCK_H */
diff --git a/arch/mn10300/include/asm/serial-regs.h b/arch/mn10300/include/asm/serial-regs.h
deleted file mode 100644
index 8320cda32f5a..000000000000
--- a/arch/mn10300/include/asm/serial-regs.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/* MN10300 on-board serial port module registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_SERIAL_REGS_H
-#define _ASM_SERIAL_REGS_H
-
-#include <asm/cpu-regs.h>
-#include <asm/intctl-regs.h>
-
-#ifdef __KERNEL__
-
-/* serial port 0 */
-#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
-#define SC01CTR_CK 0x0007 /* clock source select */
-#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
-#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
-#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
-#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */
-#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
-#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
-#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */
-#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */
-#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
-#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */
-#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */
-#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 1 only) */
-#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */
-#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
-#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
-#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */
-#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
-#define SC1CTR_CK_TM12UFLOW_8 0x0000 /* - 1/8 timer 12 underflow (serial port 1 only) */
-#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
-#define SC01CTR_STB 0x0008 /* stop bit select */
-#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */
-#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */
-#define SC01CTR_PB 0x0070 /* parity bit select */
-#define SC01CTR_PB_NONE 0x0000 /* - no parity */
-#define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
-#define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
-#define SC01CTR_PB_EVEN 0x0060 /* - even parity */
-#define SC01CTR_PB_ODD 0x0070 /* - odd parity */
-#define SC01CTR_CLN 0x0080 /* character length */
-#define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
-#define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
-#define SC01CTR_TOE 0x0100 /* T input output enable */
-#define SC01CTR_OD 0x0200 /* bit order select */
-#define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */
-#define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */
-#define SC01CTR_MD 0x0c00 /* mode select */
-#define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */
-#define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */
-#define SC01CTR_MD_I2C 0x0800 /* - I2C mode */
-#define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */
-#define SC01CTR_IIC 0x1000 /* I2C mode select */
-#define SC01CTR_BKE 0x2000 /* break transmit enable */
-#define SC01CTR_RXE 0x4000 /* receive enable */
-#define SC01CTR_TXE 0x8000 /* transmit enable */
-
-#define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
-#define SC01ICR_DMD 0x80 /* output data mode */
-#define SC01ICR_TD 0x20 /* transmit DMA trigger cause */
-#define SC01ICR_TI 0x10 /* transmit interrupt cause */
-#define SC01ICR_RES 0x04 /* receive error select */
-#define SC01ICR_RI 0x01 /* receive interrupt cause */
-
-#define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
-#define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
-
-#define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
-#define SC01STR_OEF 0x0001 /* overrun error found */
-#define SC01STR_PEF 0x0002 /* parity error found */
-#define SC01STR_FEF 0x0004 /* framing error found */
-#define SC01STR_RBF 0x0010 /* receive buffer status */
-#define SC01STR_TBF 0x0020 /* transmit buffer status */
-#define SC01STR_RXF 0x0040 /* receive status */
-#define SC01STR_TXF 0x0080 /* transmit status */
-#define SC01STR_STF 0x0100 /* I2C start sequence found */
-#define SC01STR_SPF 0x0200 /* I2C stop sequence found */
-
-#define SC0RXIRQ 20 /* timer 0 Receive IRQ */
-#define SC0TXIRQ 21 /* timer 0 Transmit IRQ */
-
-#define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
-#define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
-
-/* serial port 1 */
-#define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
-#define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
-#define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
-#define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
-#define SC1STR __SYSREG(0xd400201c, u16) /* status reg */
-
-#define SC1RXIRQ 22 /* timer 1 Receive IRQ */
-#define SC1TXIRQ 23 /* timer 1 Transmit IRQ */
-
-#define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
-#define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
-
-/* serial port 2 */
-#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */
-#ifdef CONFIG_AM33_2
-#define SC2CTR_CK 0x0003 /* clock source select */
-#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */
-#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */
-#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */
-#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */
-#else /* CONFIG_AM33_2 */
-#define SC2CTR_CK 0x0007 /* clock source select */
-#define SC2CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow */
-#define SC2CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
-#define SC2CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
-#define SC2CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow */
-#define SC2CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow */
-#define SC2CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow */
-#define SC2CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
-#define SC2CTR_CK_EXTERN 0x0007 /* - external closk */
-#endif /* CONFIG_AM33_2 */
-#define SC2CTR_STB 0x0008 /* stop bit select */
-#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */
-#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */
-#define SC2CTR_PB 0x0070 /* parity bit select */
-#define SC2CTR_PB_NONE 0x0000 /* - no parity */
-#define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
-#define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
-#define SC2CTR_PB_EVEN 0x0060 /* - even parity */
-#define SC2CTR_PB_ODD 0x0070 /* - odd parity */
-#define SC2CTR_CLN 0x0080 /* character length */
-#define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
-#define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
-#define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */
-#define SC2CTR_OD 0x0200 /* bit order select */
-#define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */
-#define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */
-#define SC2CTR_TWS 0x1000 /* transmit wait select */
-#define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */
-#define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */
-#define SC2CTR_BKE 0x2000 /* break transmit enable */
-#define SC2CTR_RXE 0x4000 /* receive enable */
-#define SC2CTR_TXE 0x8000 /* transmit enable */
-
-#define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */
-#define SC2ICR_TD 0x20 /* transmit DMA trigger cause */
-#define SC2ICR_TI 0x10 /* transmit interrupt cause */
-#define SC2ICR_RES 0x04 /* receive error select */
-#define SC2ICR_RI 0x01 /* receive interrupt cause */
-
-#define SC2TXB __SYSREG(0xd4002028, u8) /* transmit buffer reg */
-#define SC2RXB __SYSREG(0xd4002029, u8) /* receive buffer reg */
-
-#ifdef CONFIG_AM33_2
-#define SC2STR __SYSREG(0xd400202c, u8) /* status reg */
-#else /* CONFIG_AM33_2 */
-#define SC2STR __SYSREG(0xd400202c, u16) /* status reg */
-#endif /* CONFIG_AM33_2 */
-#define SC2STR_OEF 0x0001 /* overrun error found */
-#define SC2STR_PEF 0x0002 /* parity error found */
-#define SC2STR_FEF 0x0004 /* framing error found */
-#define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */
-#define SC2STR_RBF 0x0010 /* receive buffer status */
-#define SC2STR_TBF 0x0020 /* transmit buffer status */
-#define SC2STR_RXF 0x0040 /* receive status */
-#define SC2STR_TXF 0x0080 /* transmit status */
-
-#ifdef CONFIG_AM33_2
-#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */
-#endif
-
-#ifdef CONFIG_AM33_2
-#define SC2RXIRQ 24 /* serial 2 Receive IRQ */
-#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */
-#else /* CONFIG_AM33_2 */
-#define SC2RXIRQ 68 /* serial 2 Receive IRQ */
-#define SC2TXIRQ 69 /* serial 2 Transmit IRQ */
-#endif /* CONFIG_AM33_2 */
-
-#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
-#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
-
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_SERIAL_REGS_H */
diff --git a/arch/mn10300/include/asm/serial.h b/arch/mn10300/include/asm/serial.h
deleted file mode 100644
index 594ebff15d3f..000000000000
--- a/arch/mn10300/include/asm/serial.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Standard UART definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_SERIAL_H
-#define _ASM_SERIAL_H
-
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
-#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ)
-#define STD_COM4_FLAGS (UPF_BOOT_AUTOCONF | UPF_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
-#define STD_COM4_FLAGS UPF_BOOT_AUTOCONF
-#endif
-
-#ifdef CONFIG_SERIAL_8250_MANY_PORTS
-#define FOURPORT_FLAGS UPF_FOURPORT
-#define ACCENT_FLAGS 0
-#define BOCA_FLAGS 0
-#define HUB6_FLAGS 0
-#define RS_TABLE_SIZE 64
-#else
-#define RS_TABLE_SIZE
-#endif
-
-#include <unit/serial.h>
-
-#endif /* _ASM_SERIAL_H */
diff --git a/arch/mn10300/include/asm/setup.h b/arch/mn10300/include/asm/setup.h
deleted file mode 100644
index fb024555d2a9..000000000000
--- a/arch/mn10300/include/asm/setup.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* MN10300 Setup declarations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_SETUP_H
-#define _ASM_SETUP_H
-
-#include <uapi/asm/setup.h>
-
-extern void __init unit_setup(void);
-extern void __init unit_init_IRQ(void);
-#endif /* _ASM_SETUP_H */
diff --git a/arch/mn10300/include/asm/shmparam.h b/arch/mn10300/include/asm/shmparam.h
deleted file mode 100644
index 3a31faaa4353..000000000000
--- a/arch/mn10300/include/asm/shmparam.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SHMPARAM_H
-#define _ASM_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
-
-#endif /* _ASM_SHMPARAM_H */
diff --git a/arch/mn10300/include/asm/signal.h b/arch/mn10300/include/asm/signal.h
deleted file mode 100644
index 214ff5e9fe60..000000000000
--- a/arch/mn10300/include/asm/signal.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* MN10300 Signal definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_SIGNAL_H
-#define _ASM_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-/* Most things should be clean enough to redefine this at will, if care
- is taken to make libc match. */
-
-#define _NSIG 64
-#define _NSIG_BPW 32
-#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t; /* at least 32 bits */
-
-typedef struct {
- unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#define __ARCH_HAS_SA_RESTORER
-
-#include <asm/sigcontext.h>
-
-#endif /* _ASM_SIGNAL_H */
diff --git a/arch/mn10300/include/asm/smp.h b/arch/mn10300/include/asm/smp.h
deleted file mode 100644
index 56c42417d428..000000000000
--- a/arch/mn10300/include/asm/smp.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* MN10300 SMP support
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * Modified by Matsushita Electric Industrial Co., Ltd.
- * Modifications:
- * 13-Nov-2006 MEI Define IPI-IRQ number and add inline/macro function
- * for SMP support.
- * 22-Jan-2007 MEI Add the define related to SMP_BOOT_IRQ.
- * 23-Feb-2007 MEI Add the define related to SMP icahce invalidate.
- * 23-Jun-2008 MEI Delete INTC_IPI.
- * 22-Jul-2008 MEI Add smp_nmi_call_function and related defines.
- * 04-Aug-2008 MEI Delete USE_DOIRQ_CACHE_IPI.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_SMP_H
-#define _ASM_SMP_H
-
-#ifndef __ASSEMBLY__
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/thread_info.h>
-#endif
-
-#ifdef CONFIG_SMP
-#include <proc/smp-regs.h>
-
-#define RESCHEDULE_IPI 63
-#define CALL_FUNC_SINGLE_IPI 192
-#define LOCAL_TIMER_IPI 193
-#define FLUSH_CACHE_IPI 194
-#define CALL_FUNCTION_NMI_IPI 195
-#define DEBUGGER_NMI_IPI 196
-
-#define SMP_BOOT_IRQ 195
-
-#define RESCHEDULE_GxICR_LV GxICR_LEVEL_6
-#define CALL_FUNCTION_GxICR_LV GxICR_LEVEL_4
-#define LOCAL_TIMER_GxICR_LV GxICR_LEVEL_4
-#define FLUSH_CACHE_GxICR_LV GxICR_LEVEL_0
-#define SMP_BOOT_GxICR_LV GxICR_LEVEL_0
-#define DEBUGGER_GxICR_LV CONFIG_DEBUGGER_IRQ_LEVEL
-
-#define TIME_OUT_COUNT_BOOT_IPI 100
-#define DELAY_TIME_BOOT_IPI 75000
-
-
-#ifndef __ASSEMBLY__
-
-/**
- * raw_smp_processor_id - Determine the raw CPU ID of the CPU running it
- *
- * What we really want to do is to use the CPUID hardware CPU register to get
- * this information, but accesses to that aren't cached, and run at system bus
- * speed, not CPU speed. A copy of this value is, however, stored in the
- * thread_info struct, and that can be cached.
- *
- * An alternate way of dealing with this could be to use the EPSW.S bits to
- * cache this information for systems with up to four CPUs.
- */
-#define arch_smp_processor_id() (CPUID)
-#if 0
-#define raw_smp_processor_id() (arch_smp_processor_id())
-#else
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-#endif
-
-static inline int cpu_logical_map(int cpu)
-{
- return cpu;
-}
-
-static inline int cpu_number_map(int cpu)
-{
- return cpu;
-}
-
-
-extern cpumask_t cpu_boot_map;
-
-extern void smp_init_cpus(void);
-extern void smp_cache_interrupt(void);
-extern void send_IPI_allbutself(int irq);
-extern int smp_nmi_call_function(void (*func)(void *), void *info, int wait);
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-
-#ifdef CONFIG_HOTPLUG_CPU
-extern int __cpu_disable(void);
-extern void __cpu_die(unsigned int cpu);
-#endif /* CONFIG_HOTPLUG_CPU */
-
-#endif /* __ASSEMBLY__ */
-#else /* CONFIG_SMP */
-#ifndef __ASSEMBLY__
-
-static inline void smp_init_cpus(void) {}
-#define raw_smp_processor_id() 0
-
-#endif /* __ASSEMBLY__ */
-#endif /* CONFIG_SMP */
-
-#endif /* _ASM_SMP_H */
diff --git a/arch/mn10300/include/asm/smsc911x.h b/arch/mn10300/include/asm/smsc911x.h
deleted file mode 100644
index 2fcd1080322b..000000000000
--- a/arch/mn10300/include/asm/smsc911x.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <unit/smsc911x.h>
diff --git a/arch/mn10300/include/asm/spinlock.h b/arch/mn10300/include/asm/spinlock.h
deleted file mode 100644
index 879cd0df53ba..000000000000
--- a/arch/mn10300/include/asm/spinlock.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/* MN10300 spinlock support
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_SPINLOCK_H
-#define _ASM_SPINLOCK_H
-
-#include <linux/atomic.h>
-#include <asm/barrier.h>
-#include <asm/processor.h>
-#include <asm/rwlock.h>
-#include <asm/page.h>
-
-/*
- * Simple spin lock operations. There are two variants, one clears IRQ's
- * on the local processor, one does not.
- *
- * We make no fairness assumptions. They have a cost.
- */
-
-#define arch_spin_is_locked(x) (*(volatile signed char *)(&(x)->slock) != 0)
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- asm volatile(
- " bclr 1,(0,%0) \n"
- :
- : "a"(&lock->slock)
- : "memory", "cc");
-}
-
-static inline int arch_spin_trylock(arch_spinlock_t *lock)
-{
- int ret;
-
- asm volatile(
- " mov 1,%0 \n"
- " bset %0,(%1) \n"
- " bne 1f \n"
- " clr %0 \n"
- "1: xor 1,%0 \n"
- : "=d"(ret)
- : "a"(&lock->slock)
- : "memory", "cc");
-
- return ret;
-}
-
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- asm volatile(
- "1: bset 1,(0,%0) \n"
- " bne 1b \n"
- :
- : "a"(&lock->slock)
- : "memory", "cc");
-}
-
-static inline void arch_spin_lock_flags(arch_spinlock_t *lock,
- unsigned long flags)
-{
- int temp;
-
- asm volatile(
- "1: bset 1,(0,%2) \n"
- " beq 3f \n"
- " mov %1,epsw \n"
- "2: mov (0,%2),%0 \n"
- " or %0,%0 \n"
- " bne 2b \n"
- " mov %3,%0 \n"
- " mov %0,epsw \n"
- " nop \n"
- " nop \n"
- " bra 1b\n"
- "3: \n"
- : "=&d" (temp)
- : "d" (flags), "a"(&lock->slock), "i"(EPSW_IE | MN10300_CLI_LEVEL)
- : "memory", "cc");
-}
-#define arch_spin_lock_flags arch_spin_lock_flags
-
-#ifdef __KERNEL__
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts
- * but no interrupt writers. For those circumstances we
- * can "mix" irq-safe locks - any writer needs to get a
- * irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- */
-
-/*
- * On mn10300, we implement read-write locks as a 32-bit counter
- * with the high bit (sign) being the "contended" bit.
- */
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
-#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
- __build_read_lock(rw, "__read_lock_failed");
-#else
- {
- atomic_t *count = (atomic_t *)rw;
- while (atomic_dec_return(count) < 0)
- atomic_inc(count);
- }
-#endif
-}
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
-#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
- __build_write_lock(rw, "__write_lock_failed");
-#else
- {
- atomic_t *count = (atomic_t *)rw;
- while (!atomic_sub_and_test(RW_LOCK_BIAS, count))
- atomic_add(RW_LOCK_BIAS, count);
- }
-#endif
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
-#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
- __build_read_unlock(rw);
-#else
- {
- atomic_t *count = (atomic_t *)rw;
- atomic_inc(count);
- }
-#endif
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
-#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
- __build_write_unlock(rw);
-#else
- {
- atomic_t *count = (atomic_t *)rw;
- atomic_add(RW_LOCK_BIAS, count);
- }
-#endif
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *lock)
-{
- atomic_t *count = (atomic_t *)lock;
- atomic_dec(count);
- if (atomic_read(count) >= 0)
- return 1;
- atomic_inc(count);
- return 0;
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *lock)
-{
- atomic_t *count = (atomic_t *)lock;
- if (atomic_sub_and_test(RW_LOCK_BIAS, count))
- return 1;
- atomic_add(RW_LOCK_BIAS, count);
- return 0;
-}
-
-#define _raw_spin_relax(lock) cpu_relax()
-#define _raw_read_relax(lock) cpu_relax()
-#define _raw_write_relax(lock) cpu_relax()
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mn10300/include/asm/spinlock_types.h b/arch/mn10300/include/asm/spinlock_types.h
deleted file mode 100644
index 32abdc89bbc7..000000000000
--- a/arch/mn10300/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SPINLOCK_TYPES_H
-#define _ASM_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct arch_spinlock {
- unsigned int slock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-typedef struct {
- unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { RW_LOCK_BIAS }
-
-#endif /* _ASM_SPINLOCK_TYPES_H */
diff --git a/arch/mn10300/include/asm/string.h b/arch/mn10300/include/asm/string.h
deleted file mode 100644
index 47dbd4346c32..000000000000
--- a/arch/mn10300/include/asm/string.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* MN10300 Optimised string functions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_STRING_H
-#define _ASM_STRING_H
-
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-
-extern void *memset(void *dest, int ch, size_t count);
-extern void *memcpy(void *dest, const void *src, size_t count);
-extern void *memmove(void *dest, const void *src, size_t count);
-
-
-extern void __struct_cpy_bug(void);
-#define struct_cpy(x, y) \
-({ \
- if (sizeof(*(x)) != sizeof(*(y))) \
- __struct_cpy_bug; \
- memcpy(x, y, sizeof(*(x))); \
-})
-
-#endif /* _ASM_STRING_H */
diff --git a/arch/mn10300/include/asm/switch_to.h b/arch/mn10300/include/asm/switch_to.h
deleted file mode 100644
index 67e333aa7629..000000000000
--- a/arch/mn10300/include/asm/switch_to.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* MN10300 task switching definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_SWITCH_TO_H
-#define _ASM_SWITCH_TO_H
-
-#include <asm/barrier.h>
-
-struct task_struct;
-struct thread_struct;
-
-#if defined(CONFIG_FPU) && !defined(CONFIG_LAZY_SAVE_FPU)
-struct fpu_state_struct;
-extern asmlinkage void fpu_save(struct fpu_state_struct *);
-#define switch_fpu(prev, next) \
- do { \
- if ((prev)->thread.fpu_flags & THREAD_HAS_FPU) { \
- (prev)->thread.fpu_flags &= ~THREAD_HAS_FPU; \
- (prev)->thread.uregs->epsw &= ~EPSW_FE; \
- fpu_save(&(prev)->thread.fpu_state); \
- } \
- } while (0)
-#else
-#define switch_fpu(prev, next) do {} while (0)
-#endif
-
-/* context switching is now performed out-of-line in switch_to.S */
-extern asmlinkage
-struct task_struct *__switch_to(struct thread_struct *prev,
- struct thread_struct *next,
- struct task_struct *prev_task);
-
-#define switch_to(prev, next, last) \
-do { \
- switch_fpu(prev, next); \
- current->thread.wchan = (u_long) __builtin_return_address(0); \
- (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
- mb(); \
- current->thread.wchan = 0; \
-} while (0)
-
-#endif /* _ASM_SWITCH_TO_H */
diff --git a/arch/mn10300/include/asm/syscall.h b/arch/mn10300/include/asm/syscall.h
deleted file mode 100644
index b44b0bb75a01..000000000000
--- a/arch/mn10300/include/asm/syscall.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Access to user system call parameters and results
- *
- * See asm-generic/syscall.h for function descriptions.
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_SYSCALL_H
-#define _ASM_SYSCALL_H
-
-#include <linux/sched.h>
-#include <linux/err.h>
-
-extern const unsigned long sys_call_table[];
-
-static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
-{
- return regs->orig_d0;
-}
-
-static inline void syscall_rollback(struct task_struct *task,
- struct pt_regs *regs)
-{
- regs->d0 = regs->orig_d0;
-}
-
-static inline long syscall_get_error(struct task_struct *task,
- struct pt_regs *regs)
-{
- unsigned long error = regs->d0;
- return IS_ERR_VALUE(error) ? error : 0;
-}
-
-static inline long syscall_get_return_value(struct task_struct *task,
- struct pt_regs *regs)
-{
- return regs->d0;
-}
-
-static inline void syscall_set_return_value(struct task_struct *task,
- struct pt_regs *regs,
- int error, long val)
-{
- regs->d0 = (long) error ?: val;
-}
-
-static inline void syscall_get_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- unsigned long *args)
-{
- switch (i) {
- case 0:
- if (!n--) break;
- *args++ = regs->a0;
- case 1:
- if (!n--) break;
- *args++ = regs->d1;
- case 2:
- if (!n--) break;
- *args++ = regs->a3;
- case 3:
- if (!n--) break;
- *args++ = regs->a2;
- case 4:
- if (!n--) break;
- *args++ = regs->d3;
- case 5:
- if (!n--) break;
- *args++ = regs->d2;
- case 6:
- if (!n--) break;
- default:
- BUG();
- break;
- }
-}
-
-static inline void syscall_set_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- const unsigned long *args)
-{
- switch (i) {
- case 0:
- if (!n--) break;
- regs->a0 = *args++;
- case 1:
- if (!n--) break;
- regs->d1 = *args++;
- case 2:
- if (!n--) break;
- regs->a3 = *args++;
- case 3:
- if (!n--) break;
- regs->a2 = *args++;
- case 4:
- if (!n--) break;
- regs->d3 = *args++;
- case 5:
- if (!n--) break;
- regs->d2 = *args++;
- case 6:
- if (!n--) break;
- default:
- BUG();
- break;
- }
-}
-
-#endif /* _ASM_SYSCALL_H */
diff --git a/arch/mn10300/include/asm/termios.h b/arch/mn10300/include/asm/termios.h
deleted file mode 100644
index 4010edcaa08e..000000000000
--- a/arch/mn10300/include/asm/termios.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TERMIOS_H
-#define _ASM_TERMIOS_H
-
-#include <uapi/asm/termios.h>
-
-/* intr=^C quit=^| erase=del kill=^U
- eof=^D vtime=\0 vmin=\1 sxtc=\0
- start=^Q stop=^S susp=^Z eol=\0
- reprint=^R discard=^U werase=^W lnext=^V
- eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#endif /* _ASM_TERMIOS_H */
diff --git a/arch/mn10300/include/asm/thread_info.h b/arch/mn10300/include/asm/thread_info.h
deleted file mode 100644
index 1748a7b25bf8..000000000000
--- a/arch/mn10300/include/asm/thread_info.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/* MN10300 Low-level thread information
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#include <asm/page.h>
-
-#ifdef CONFIG_4KSTACKS
-#define THREAD_SIZE (4096)
-#define THREAD_SIZE_ORDER (0)
-#else
-#define THREAD_SIZE (8192)
-#define THREAD_SIZE_ORDER (1)
-#endif
-
-#define STACK_WARN (THREAD_SIZE / 8)
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants
- * must also be changed
- */
-#ifndef __ASSEMBLY__
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-struct thread_info {
- struct task_struct *task; /* main task structure */
- struct pt_regs *frame; /* current exception frame */
- unsigned long flags; /* low level flags */
- __u32 cpu; /* current CPU */
- __s32 preempt_count; /* 0 => preemptable, <0 => BUG */
-
- mm_segment_t addr_limit; /* thread address space:
- 0-0xBFFFFFFF for user-thead
- 0-0xFFFFFFFF for kernel-thread
- */
-
- __u8 supervisor_stack[0];
-};
-
-#define thread_info_to_uregs(ti) \
- ((struct pt_regs *) \
- ((unsigned long)ti + THREAD_SIZE - sizeof(struct pt_regs)))
-
-#else /* !__ASSEMBLY__ */
-
-#ifndef __ASM_OFFSETS_H__
-#include <asm/asm-offsets.h>
-#endif
-
-#endif
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#ifndef __ASSEMBLY__
-
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
-}
-
-#define init_uregs \
- ((struct pt_regs *) \
- ((unsigned long) init_stack + THREAD_SIZE - sizeof(struct pt_regs)))
-
-extern struct thread_info *__current_ti;
-
-/* how to get the thread information struct from C */
-static inline __attribute__((const))
-struct thread_info *current_thread_info(void)
-{
- struct thread_info *ti;
- asm("mov sp,%0\n"
- "and %1,%0\n"
- : "=d" (ti)
- : "i" (~(THREAD_SIZE - 1))
- : "cc");
- return ti;
-}
-
-static inline __attribute__((const))
-struct pt_regs *current_frame(void)
-{
- return current_thread_info()->frame;
-}
-
-/* how to get the current stack pointer from C */
-static inline unsigned long current_stack_pointer(void)
-{
- unsigned long sp;
- asm("mov sp,%0; ":"=r" (sp));
- return sp;
-}
-
-#ifndef CONFIG_KGDB
-void arch_release_thread_stack(unsigned long *stack);
-#endif
-#define get_thread_info(ti) get_task_struct((ti)->task)
-#define put_thread_info(ti) put_task_struct((ti)->task)
-
-#else /* !__ASSEMBLY__ */
-
-#ifndef __VMLINUX_LDS__
-/* how to get the thread information struct from ASM */
-.macro GET_THREAD_INFO reg
- mov sp,\reg
- and -THREAD_SIZE,\reg
-.endm
-#endif
-#endif
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to
- * access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
-#define TIF_SIGPENDING 2 /* signal pending */
-#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
-#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
-#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
-#define TIF_MEMDIE 17 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE +(1 << TIF_SYSCALL_TRACE)
-#define _TIF_NOTIFY_RESUME +(1 << TIF_NOTIFY_RESUME)
-#define _TIF_SIGPENDING +(1 << TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED +(1 << TIF_NEED_RESCHED)
-#define _TIF_SINGLESTEP +(1 << TIF_SINGLESTEP)
-#define _TIF_POLLING_NRFLAG +(1 << TIF_POLLING_NRFLAG)
-
-#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
-#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/arch/mn10300/include/asm/timer-regs.h b/arch/mn10300/include/asm/timer-regs.h
deleted file mode 100644
index c634977caf66..000000000000
--- a/arch/mn10300/include/asm/timer-regs.h
+++ /dev/null
@@ -1,452 +0,0 @@
-/* AM33v2 on-board timer module registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_TIMER_REGS_H
-#define _ASM_TIMER_REGS_H
-
-#include <asm/cpu-regs.h>
-#include <asm/intctl-regs.h>
-
-#ifdef __KERNEL__
-
-/*
- * Timer prescalar control
- */
-#define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
-#define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */
-#define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */
-
-/*
- * 8-bit timers
- */
-#define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
-#define TM0MD_SRC 0x07 /* timer source */
-#define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */
-#define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */
-#endif /* CONFIG_AM33_2 */
-#define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */
-#define TM1MD_SRC 0x07 /* timer source */
-#define TM1MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM1MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM1MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */
-#define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */
-#endif /* CONFIG_AM33_2 */
-#define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */
-#define TM2MD_SRC 0x07 /* timer source */
-#define TM2MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM2MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM2MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */
-#define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */
-#endif /* CONFIG_AM33_2 */
-#define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */
-#define TM3MD_SRC 0x07 /* timer source */
-#define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM3MD_SRC_TM2CASCADE 0x03 /* - cascade with timer 2 */
-#define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */
-#endif /* CONFIG_AM33_2 */
-#define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
-
-#define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */
-#define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */
-#define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */
-#define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */
-#define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */
-
-#define TM0BC __SYSREGC(0xd4003020, u8) /* timer 0 binary counter */
-#define TM1BC __SYSREGC(0xd4003021, u8) /* timer 1 binary counter */
-#define TM2BC __SYSREGC(0xd4003022, u8) /* timer 2 binary counter */
-#define TM3BC __SYSREGC(0xd4003023, u8) /* timer 3 binary counter */
-#define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */
-
-#define TM0IRQ 2 /* timer 0 IRQ */
-#define TM1IRQ 3 /* timer 1 IRQ */
-#define TM2IRQ 4 /* timer 2 IRQ */
-#define TM3IRQ 5 /* timer 3 IRQ */
-
-#define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */
-#define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */
-#define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */
-#define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */
-
-/*
- * 16-bit timers 4,5 & 7-15
- */
-#define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */
-#define TM4MD_SRC 0x07 /* timer source */
-#define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM4MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM4MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */
-#endif /* CONFIG_AM33_2 */
-#define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM5MD __SYSREG(0xd4003082, u8) /* timer 5 mode register */
-#define TM5MD_SRC 0x07 /* timer source */
-#define TM5MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM5MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM5MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM5MD_SRC_TM4CASCADE 0x03 /* - cascade with timer 4 */
-#define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */
-#else /* !CONFIG_AM33_2 */
-#define TM5MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#endif /* CONFIG_AM33_2 */
-#define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM7MD __SYSREG(0xd4003086, u8) /* timer 7 mode register */
-#define TM7MD_SRC 0x07 /* timer source */
-#define TM7MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM7MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM7MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */
-#endif /* CONFIG_AM33_2 */
-#define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM8MD __SYSREG(0xd4003088, u8) /* timer 8 mode register */
-#define TM8MD_SRC 0x07 /* timer source */
-#define TM8MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM8MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM8MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM8MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */
-#define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */
-#else /* !CONFIG_AM33_2 */
-#define TM8MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#endif /* CONFIG_AM33_2 */
-#define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM9MD __SYSREG(0xd400308a, u8) /* timer 9 mode register */
-#define TM9MD_SRC 0x07 /* timer source */
-#define TM9MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM9MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM9MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM9MD_SRC_TM8CASCADE 0x03 /* - cascade with timer 8 */
-#define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */
-#else /* !CONFIG_AM33_2 */
-#define TM9MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#endif /* CONFIG_AM33_2 */
-#define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM10MD __SYSREG(0xd400308c, u8) /* timer 10 mode register */
-#define TM10MD_SRC 0x07 /* timer source */
-#define TM10MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM10MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM10MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM10MD_SRC_TM9CASCADE 0x03 /* - cascade with timer 9 */
-#define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */
-#else /* !CONFIG_AM33_2 */
-#define TM10MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#endif /* CONFIG_AM33_2 */
-#define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM11MD __SYSREG(0xd400308e, u8) /* timer 11 mode register */
-#define TM11MD_SRC 0x07 /* timer source */
-#define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-#define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */
-#else /* !CONFIG_AM33_2 */
-#define TM11MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#endif /* CONFIG_AM33_2 */
-#define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#if defined(CONFIG_AM34_2)
-#define TM12MD __SYSREG(0xd4003180, u8) /* timer 11 mode register */
-#define TM12MD_SRC 0x07 /* timer source */
-#define TM12MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM12MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM12MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM12MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM12MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM12MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#define TM12MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#define TM12MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM12MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM13MD __SYSREG(0xd4003182, u8) /* timer 11 mode register */
-#define TM13MD_SRC 0x07 /* timer source */
-#define TM13MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM13MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM13MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM13MD_SRC_TM12CASCADE 0x03 /* - cascade with timer 12 */
-#define TM13MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM13MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM13MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#define TM13MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#define TM13MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM13MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM14MD __SYSREG(0xd4003184, u8) /* timer 11 mode register */
-#define TM14MD_SRC 0x07 /* timer source */
-#define TM14MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM14MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM14MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM14MD_SRC_TM13CASCADE 0x03 /* - cascade with timer 13 */
-#define TM14MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM14MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM14MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#define TM14MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#define TM14MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM14MD_COUNT_ENABLE 0x80 /* timer count enable */
-
-#define TM15MD __SYSREG(0xd4003186, u8) /* timer 11 mode register */
-#define TM15MD_SRC 0x07 /* timer source */
-#define TM15MD_SRC_IOCLK 0x00 /* - IOCLK */
-#define TM15MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
-#define TM15MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
-#define TM15MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
-#define TM15MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
-#define TM15MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
-#define TM15MD_SRC_TM7UFLOW 0x07 /* - timer 7 underflow */
-#define TM15MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
-#define TM15MD_COUNT_ENABLE 0x80 /* timer count enable */
-#endif /* CONFIG_AM34_2 */
-
-
-#define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */
-#define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */
-#define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */
-#define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */
-#define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */
-#define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */
-#define TM89BR __SYSREG(0xd4003098, u32) /* timer 8:9 base register */
-#define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */
-#define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */
-#if defined(CONFIG_AM34_2)
-#define TM12BR __SYSREG(0xd4003190, u16) /* timer 12 base register */
-#define TM13BR __SYSREG(0xd4003192, u16) /* timer 13 base register */
-#define TM14BR __SYSREG(0xd4003194, u16) /* timer 14 base register */
-#define TM15BR __SYSREG(0xd4003196, u16) /* timer 15 base register */
-#endif /* CONFIG_AM34_2 */
-
-#define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */
-#define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */
-#define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */
-#define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */
-#define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */
-#define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */
-#define TM89BC __SYSREG(0xd40030a8, u32) /* timer 8:9 binary counter */
-#define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */
-#define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */
-#if defined(CONFIG_AM34_2)
-#define TM12BC __SYSREG(0xd40031a0, u16) /* timer 12 binary counter */
-#define TM13BC __SYSREG(0xd40031a2, u16) /* timer 13 binary counter */
-#define TM14BC __SYSREG(0xd40031a4, u16) /* timer 14 binary counter */
-#define TM15BC __SYSREG(0xd40031a6, u16) /* timer 15 binary counter */
-#endif /* CONFIG_AM34_2 */
-
-#define TM4IRQ 6 /* timer 4 IRQ */
-#define TM5IRQ 7 /* timer 5 IRQ */
-#define TM7IRQ 11 /* timer 7 IRQ */
-#define TM8IRQ 12 /* timer 8 IRQ */
-#define TM9IRQ 13 /* timer 9 IRQ */
-#define TM10IRQ 14 /* timer 10 IRQ */
-#define TM11IRQ 15 /* timer 11 IRQ */
-#if defined(CONFIG_AM34_2)
-#define TM12IRQ 64 /* timer 12 IRQ */
-#define TM13IRQ 65 /* timer 13 IRQ */
-#define TM14IRQ 66 /* timer 14 IRQ */
-#define TM15IRQ 67 /* timer 15 IRQ */
-#endif /* CONFIG_AM34_2 */
-
-#define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */
-#define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */
-#define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */
-#define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */
-#define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */
-#define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */
-#define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */
-#if defined(CONFIG_AM34_2)
-#define TM12ICR GxICR(TM12IRQ) /* timer 12 uflow intr ctrl reg */
-#define TM13ICR GxICR(TM13IRQ) /* timer 13 uflow intr ctrl reg */
-#define TM14ICR GxICR(TM14IRQ) /* timer 14 uflow intr ctrl reg */
-#define TM15ICR GxICR(TM15IRQ) /* timer 15 uflow intr ctrl reg */
-#endif /* CONFIG_AM34_2 */
-
-/*
- * 16-bit timer 6
- */
-#define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */
-#define TM6MD_SRC 0x0007 /* timer source */
-#define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */
-#define TM6MD_SRC_IOCLK_8 0x0001 /* - 1/8 IOCLK */
-#define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */
-#define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */
-#define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */
-#define TM6MD_SRC_TM2UFLOW 0x0006 /* - timer 2 underflow */
-#if defined(CONFIG_AM33_2)
-/* #define TM6MD_SRC_TM6IOB_BOTH 0x0006 */ /* - TM6IOB pin input (both edges) */
-#define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */
-#endif /* CONFIG_AM33_2 */
-#define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */
-#define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */
-#if defined(CONFIG_AM33_2)
-#define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */
-#define TM6MD_PWM 0x3800 /* PWM output mode */
-#define TM6MD_PWM_DIS 0x0000 /* - disabled */
-#define TM6MD_PWM_10BIT 0x1000 /* - 10 bits mode */
-#define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */
-#define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */
-#define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */
-#endif /* CONFIG_AM33_2 */
-
-#define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */
-#define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */
-
-#define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */
-#define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
-#define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
-#if defined(CONFIG_AM33_2)
-#define TM6MDA_OUT 0x07 /* output select */
-#define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */
-#define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */
-#define TM6MDA_OUT_SETA 0x02 /* - set at match A */
-#define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */
-#define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */
-#define TM6MDA_MODE 0xc0 /* compare A register mode */
-#define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
-#define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
-#define TM6MDA_EDGE 0x20 /* compare A edge select */
-#define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */
-#define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */
-#define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */
-#else /* !CONFIG_AM33_2 */
-#define TM6MDA_MODE 0x40 /* compare A register mode */
-#endif /* CONFIG_AM33_2 */
-
-#define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */
-#define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
-#define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
-#if defined(CONFIG_AM33_2)
-#define TM6MDB_OUT 0x07 /* output select */
-#define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */
-#define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */
-#define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */
-#define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */
-#define TM6MDB_MODE 0xc0 /* compare B register mode */
-#define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
-#define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
-#define TM6MDB_EDGE 0x20 /* compare B edge select */
-#define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */
-#define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */
-#define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */
-#else /* !CONFIG_AM33_2 */
-#define TM6MDB_MODE 0x40 /* compare B register mode */
-#endif /* CONFIG_AM33_2 */
-
-#define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */
-#define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */
-#define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */
-
-#define TM6IRQ 6 /* timer 6 IRQ */
-#define TM6AIRQ 9 /* timer 6A IRQ */
-#define TM6BIRQ 10 /* timer 6B IRQ */
-
-#define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */
-#define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */
-#define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */
-
-#if defined(CONFIG_AM34_2)
-/*
- * MTM: OS Tick-Timer
- */
-#define TMTMD __SYSREG(0xd4004100, u8) /* Tick Timer mode register */
-#define TMTMD_TMTLDE 0x40 /* initialize TMTBC = TMTBR */
-#define TMTMD_TMTCNE 0x80 /* timer count enable */
-
-#define TMTBR __SYSREG(0xd4004110, u32) /* Tick Timer mode reg */
-#define TMTBC __SYSREG(0xd4004120, u32) /* Tick Timer mode reg */
-
-/*
- * MTM: OS Timestamp-Timer
- */
-#define TMSMD __SYSREG(0xd4004140, u8) /* Tick Timer mode register */
-#define TMSMD_TMSLDE 0x40 /* initialize TMSBC = TMSBR */
-#define TMSMD_TMSCNE 0x80 /* timer count enable */
-
-#define TMSBR __SYSREG(0xd4004150, u32) /* Tick Timer mode register */
-#define TMSBC __SYSREG(0xd4004160, u32) /* Tick Timer mode register */
-
-#define TMTIRQ 119 /* OS Tick timer IRQ */
-#define TMSIRQ 120 /* Timestamp timer IRQ */
-
-#define TMTICR GxICR(TMTIRQ) /* OS Tick timer uflow intr ctrl reg */
-#define TMSICR GxICR(TMSIRQ) /* Timestamp timer uflow intr ctrl reg */
-#endif /* CONFIG_AM34_2 */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_TIMER_REGS_H */
diff --git a/arch/mn10300/include/asm/timex.h b/arch/mn10300/include/asm/timex.h
deleted file mode 100644
index f8e66425cbf8..000000000000
--- a/arch/mn10300/include/asm/timex.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* MN10300 Architecture time management specifications
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_TIMEX_H
-#define _ASM_TIMEX_H
-
-#include <unit/timex.h>
-
-#define TICK_SIZE (tick_nsec / 1000)
-
-#define CLOCK_TICK_RATE MN10300_JCCLK /* Underlying HZ */
-
-#ifdef __KERNEL__
-
-extern cycles_t cacheflush_time;
-
-static inline cycles_t get_cycles(void)
-{
- return read_timestamp_counter();
-}
-
-extern int init_clockevents(void);
-extern int init_clocksource(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_TIMEX_H */
diff --git a/arch/mn10300/include/asm/tlb.h b/arch/mn10300/include/asm/tlb.h
deleted file mode 100644
index 65d232b96613..000000000000
--- a/arch/mn10300/include/asm/tlb.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* MN10300 TLB definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_TLB_H
-#define _ASM_TLB_H
-
-#include <asm/tlbflush.h>
-
-extern void check_pgt_cache(void);
-
-/*
- * we don't need any special per-pte or per-vma handling...
- */
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it fills up
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-/* for now, just use the generic stuff */
-#include <asm-generic/tlb.h>
-
-#endif /* _ASM_TLB_H */
diff --git a/arch/mn10300/include/asm/tlbflush.h b/arch/mn10300/include/asm/tlbflush.h
deleted file mode 100644
index efddd6e1adea..000000000000
--- a/arch/mn10300/include/asm/tlbflush.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/* MN10300 TLB flushing functions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_TLBFLUSH_H
-#define _ASM_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/processor.h>
-
-struct tlb_state {
- struct mm_struct *active_mm;
- int state;
-};
-DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
-
-/**
- * local_flush_tlb - Flush the current MM's entries from the local CPU's TLBs
- */
-static inline void local_flush_tlb(void)
-{
- int w;
- asm volatile(
- " mov %1,%0 \n"
- " or %2,%0 \n"
- " mov %0,%1 \n"
- : "=d"(w)
- : "m"(MMUCTR), "i"(MMUCTR_IIV|MMUCTR_DIV)
- : "cc", "memory");
-}
-
-/**
- * local_flush_tlb_all - Flush all entries from the local CPU's TLBs
- */
-static inline void local_flush_tlb_all(void)
-{
- local_flush_tlb();
-}
-
-/**
- * local_flush_tlb_one - Flush one entry from the local CPU's TLBs
- */
-static inline void local_flush_tlb_one(unsigned long addr)
-{
- local_flush_tlb();
-}
-
-/**
- * local_flush_tlb_page - Flush a page's entry from the local CPU's TLBs
- * @mm: The MM to flush for
- * @addr: The address of the target page in RAM (not its page struct)
- */
-static inline
-void local_flush_tlb_page(struct mm_struct *mm, unsigned long addr)
-{
- unsigned long pteu, flags, cnx;
-
- addr &= PAGE_MASK;
-
- local_irq_save(flags);
-
- cnx = 1;
-#ifdef CONFIG_MN10300_TLB_USE_PIDR
- cnx = mm->context.tlbpid[smp_processor_id()];
-#endif
- if (cnx) {
- pteu = addr;
-#ifdef CONFIG_MN10300_TLB_USE_PIDR
- pteu |= cnx & xPTEU_PID;
-#endif
- IPTEU = pteu;
- DPTEU = pteu;
- if (IPTEL & xPTEL_V)
- IPTEL = 0;
- if (DPTEL & xPTEL_V)
- DPTEL = 0;
- }
- local_irq_restore(flags);
-}
-
-/*
- * TLB flushing:
- *
- * - flush_tlb() flushes the current mm struct TLBs
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(mm, start, end) flushes a range of pages
- * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
- */
-#ifdef CONFIG_SMP
-
-#include <asm/smp.h>
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_current_task(void);
-extern void flush_tlb_mm(struct mm_struct *);
-extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
-
-#define flush_tlb() flush_tlb_current_task()
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
-{
- flush_tlb_mm(vma->vm_mm);
-}
-
-#else /* CONFIG_SMP */
-
-static inline void flush_tlb_all(void)
-{
- preempt_disable();
- local_flush_tlb_all();
- preempt_enable();
-}
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
- preempt_disable();
- local_flush_tlb_all();
- preempt_enable();
-}
-
-static inline void flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
-{
- preempt_disable();
- local_flush_tlb_all();
- preempt_enable();
-}
-
-#define flush_tlb_page(vma, addr) local_flush_tlb_page((vma)->vm_mm, addr)
-#define flush_tlb() flush_tlb_all()
-
-#endif /* CONFIG_SMP */
-
-static inline void flush_tlb_kernel_range(unsigned long start,
- unsigned long end)
-{
- flush_tlb_all();
-}
-
-static inline void flush_tlb_pgtables(struct mm_struct *mm,
- unsigned long start, unsigned long end)
-{
-}
-
-#endif /* _ASM_TLBFLUSH_H */
diff --git a/arch/mn10300/include/asm/topology.h b/arch/mn10300/include/asm/topology.h
deleted file mode 100644
index 5428f333a02c..000000000000
--- a/arch/mn10300/include/asm/topology.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/topology.h>
diff --git a/arch/mn10300/include/asm/types.h b/arch/mn10300/include/asm/types.h
deleted file mode 100644
index 3d6e48311bef..000000000000
--- a/arch/mn10300/include/asm/types.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* MN10300 Basic type definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-#include <uapi/asm/types.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-
-#define BITS_PER_LONG 32
-
-#endif /* _ASM_TYPES_H */
diff --git a/arch/mn10300/include/asm/uaccess.h b/arch/mn10300/include/asm/uaccess.h
deleted file mode 100644
index 5af468fd1359..000000000000
--- a/arch/mn10300/include/asm/uaccess.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/* MN10300 userspace access functions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_UACCESS_H
-#define _ASM_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/kernel.h>
-#include <asm/page.h>
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
-
-#define KERNEL_XDS MAKE_MM_SEG(0xBFFFFFFF)
-#define KERNEL_DS MAKE_MM_SEG(0x9FFFFFFF)
-#define USER_DS MAKE_MM_SEG(TASK_SIZE)
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-#define __addr_ok(addr) \
- ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg))
-
-/*
- * check that a range of addresses falls within the current address limit
- */
-static inline int ___range_ok(unsigned long addr, unsigned int size)
-{
- int flag = 1, tmp;
-
- asm(" add %3,%1 \n" /* set C-flag if addr + size > 4Gb */
- " bcs 0f \n"
- " cmp %4,%1 \n" /* jump if addr+size>limit (error) */
- " bhi 0f \n"
- " clr %0 \n" /* mark okay */
- "0: \n"
- : "=r"(flag), "=&r"(tmp)
- : "1"(addr), "ir"(size),
- "r"(current_thread_info()->addr_limit.seg), "0"(flag)
- : "cc"
- );
-
- return flag;
-}
-
-#define __range_ok(addr, size) ___range_ok((unsigned long)(addr), (u32)(size))
-
-#define access_ok(type, addr, size) (__range_ok((addr), (size)) == 0)
-#define __access_ok(addr, size) (__range_ok((addr), (size)) == 0)
-
-#include <asm/extable.h>
-
-#define put_user(x, ptr) __put_user_check((x), (ptr), sizeof(*(ptr)))
-#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr)))
-
-/*
- * The "__xxx" versions do not do address space checking, useful when
- * doing multiple accesses to the same area (the user has to do the
- * checks by hand with "access_ok()")
- */
-#define __put_user(x, ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
-#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct *)(x))
-
-#define __get_user_nocheck(x, ptr, size) \
-({ \
- unsigned long __gu_addr; \
- int __gu_err; \
- __gu_addr = (unsigned long) (ptr); \
- switch (size) { \
- case 1: { \
- unsigned char __gu_val; \
- __get_user_asm("bu"); \
- (x) = *(__force __typeof__(*(ptr))*) &__gu_val; \
- break; \
- } \
- case 2: { \
- unsigned short __gu_val; \
- __get_user_asm("hu"); \
- (x) = *(__force __typeof__(*(ptr))*) &__gu_val; \
- break; \
- } \
- case 4: { \
- unsigned int __gu_val; \
- __get_user_asm(""); \
- (x) = *(__force __typeof__(*(ptr))*) &__gu_val; \
- break; \
- } \
- default: \
- __get_user_unknown(); \
- break; \
- } \
- __gu_err; \
-})
-
-#define __get_user_check(x, ptr, size) \
-({ \
- const __typeof__(*(ptr))* __guc_ptr = (ptr); \
- int _e; \
- if (likely(__access_ok((unsigned long) __guc_ptr, (size)))) \
- _e = __get_user_nocheck((x), __guc_ptr, (size)); \
- else { \
- _e = -EFAULT; \
- (x) = (__typeof__(x))0; \
- } \
- _e; \
-})
-
-#define __get_user_asm(INSN) \
-({ \
- asm volatile( \
- "1:\n" \
- " mov"INSN" %2,%1\n" \
- " mov 0,%0\n" \
- "2:\n" \
- " .section .fixup,\"ax\"\n" \
- "3:\n\t" \
- " mov 0,%1\n" \
- " mov %3,%0\n" \
- " jmp 2b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b, 3b\n" \
- " .previous" \
- : "=&r" (__gu_err), "=&r" (__gu_val) \
- : "m" (__m(__gu_addr)), "i" (-EFAULT)); \
-})
-
-extern int __get_user_unknown(void);
-
-#define __put_user_nocheck(x, ptr, size) \
-({ \
- union { \
- __typeof__(*(ptr)) val; \
- u32 bits[2]; \
- } __pu_val; \
- unsigned long __pu_addr; \
- int __pu_err; \
- __pu_val.val = (x); \
- __pu_addr = (unsigned long) (ptr); \
- switch (size) { \
- case 1: __put_user_asm("bu"); break; \
- case 2: __put_user_asm("hu"); break; \
- case 4: __put_user_asm("" ); break; \
- case 8: __put_user_asm8(); break; \
- default: __pu_err = __put_user_unknown(); break; \
- } \
- __pu_err; \
-})
-
-#define __put_user_check(x, ptr, size) \
-({ \
- union { \
- __typeof__(*(ptr)) val; \
- u32 bits[2]; \
- } __pu_val; \
- unsigned long __pu_addr; \
- int __pu_err; \
- __pu_val.val = (x); \
- __pu_addr = (unsigned long) (ptr); \
- if (likely(__access_ok(__pu_addr, size))) { \
- switch (size) { \
- case 1: __put_user_asm("bu"); break; \
- case 2: __put_user_asm("hu"); break; \
- case 4: __put_user_asm("" ); break; \
- case 8: __put_user_asm8(); break; \
- default: __pu_err = __put_user_unknown(); break; \
- } \
- } \
- else { \
- __pu_err = -EFAULT; \
- } \
- __pu_err; \
-})
-
-#define __put_user_asm(INSN) \
-({ \
- asm volatile( \
- "1:\n" \
- " mov"INSN" %1,%2\n" \
- " mov 0,%0\n" \
- "2:\n" \
- " .section .fixup,\"ax\"\n" \
- "3:\n" \
- " mov %3,%0\n" \
- " jmp 2b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 1b, 3b\n" \
- " .previous" \
- : "=&r" (__pu_err) \
- : "r" (__pu_val.val), "m" (__m(__pu_addr)), \
- "i" (-EFAULT) \
- ); \
-})
-
-#define __put_user_asm8() \
-({ \
- asm volatile( \
- "1: mov %1,%3 \n" \
- "2: mov %2,%4 \n" \
- " mov 0,%0 \n" \
- "3: \n" \
- " .section .fixup,\"ax\" \n" \
- "4: \n" \
- " mov %5,%0 \n" \
- " jmp 3b \n" \
- " .previous \n" \
- " .section __ex_table,\"a\"\n" \
- " .balign 4 \n" \
- " .long 1b, 4b \n" \
- " .long 2b, 4b \n" \
- " .previous \n" \
- : "=&r" (__pu_err) \
- : "r" (__pu_val.bits[0]), "r" (__pu_val.bits[1]), \
- "m" (__m(__pu_addr)), "m" (__m(__pu_addr+4)), \
- "i" (-EFAULT) \
- ); \
-})
-
-extern int __put_user_unknown(void);
-
-
-/*
- * Copy To/From Userspace
- */
-/* Generic arbitrary sized copy. */
-#define __copy_user(to, from, size) \
-do { \
- if (size) { \
- void *__to = to; \
- const void *__from = from; \
- int w; \
- asm volatile( \
- "0: movbu (%0),%3;\n" \
- "1: movbu %3,(%1);\n" \
- " inc %0;\n" \
- " inc %1;\n" \
- " add -1,%2;\n" \
- " bne 0b;\n" \
- "2:\n" \
- " .section .fixup,\"ax\"\n" \
- "3: jmp 2b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,3b\n" \
- " .long 1b,3b\n" \
- " .previous\n" \
- : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\
- : "0"(__from), "1"(__to), "2"(size) \
- : "cc", "memory"); \
- } \
-} while (0)
-
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long n)
-{
- __copy_user(to, from, n);
- return n;
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long n)
-{
- __copy_user(to, from, n);
- return n;
-}
-
-extern long strncpy_from_user(char *dst, const char __user *src, long count);
-extern long strnlen_user(const char __user *str, long n);
-extern unsigned long clear_user(void __user *mem, unsigned long len);
-extern unsigned long __clear_user(void __user *mem, unsigned long len);
-
-#endif /* _ASM_UACCESS_H */
diff --git a/arch/mn10300/include/asm/ucontext.h b/arch/mn10300/include/asm/ucontext.h
deleted file mode 100644
index fcab5c1d8e18..000000000000
--- a/arch/mn10300/include/asm/ucontext.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* MN10300 User context
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_UCONTEXT_H
-#define _ASM_UCONTEXT_H
-
-struct ucontext {
- unsigned long uc_flags;
- struct ucontext *uc_link;
- stack_t uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-#endif /* _ASM_UCONTEXT_H */
diff --git a/arch/mn10300/include/asm/unaligned.h b/arch/mn10300/include/asm/unaligned.h
deleted file mode 100644
index 0df671318ae4..000000000000
--- a/arch/mn10300/include/asm/unaligned.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* MN10300 Unaligned memory access handling
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_MN10300_UNALIGNED_H
-#define _ASM_MN10300_UNALIGNED_H
-
-#include <linux/unaligned/access_ok.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-
-#endif /* _ASM_MN10300_UNALIGNED_H */
diff --git a/arch/mn10300/include/asm/unistd.h b/arch/mn10300/include/asm/unistd.h
deleted file mode 100644
index 0522468f488b..000000000000
--- a/arch/mn10300/include/asm/unistd.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* MN10300 System call number list
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_UNISTD_H
-#define _ASM_UNISTD_H
-
-#include <uapi/asm/unistd.h>
-
-
-#define NR_syscalls 340
-
-/*
- * specify the deprecated syscalls we want to support on this arch
- */
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_IPC
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLD_SELECT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-#define __ARCH_WANT_SYS_CLONE
-
-#endif /* _ASM_UNISTD_H */
diff --git a/arch/mn10300/include/asm/user.h b/arch/mn10300/include/asm/user.h
deleted file mode 100644
index e1193908b78c..000000000000
--- a/arch/mn10300/include/asm/user.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* MN10300 User process data
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_USER_H
-#define _ASM_USER_H
-
-#include <asm/page.h>
-#include <linux/ptrace.h>
-
-#ifndef __ASSEMBLY__
-/*
- * When the kernel dumps core, it starts by dumping the user struct - this will
- * be used by gdb to figure out where the data and stack segments are within
- * the file, and what virtual addresses to use.
- */
-struct user {
- /* We start with the registers, to mimic the way that "memory" is
- * returned from the ptrace(3,...) function.
- */
- struct pt_regs regs; /* Where the registers are actually stored */
-
- /* The rest of this junk is to help gdb figure out what goes where */
- unsigned long int u_tsize; /* Text segment size (pages). */
- unsigned long int u_dsize; /* Data segment size (pages). */
- unsigned long int u_ssize; /* Stack segment size (pages). */
- unsigned long start_code; /* Starting virtual address of text. */
- unsigned long start_stack; /* Starting virtual address of stack area.
- This is actually the bottom of the stack,
- the top of the stack is always found in the
- esp register. */
- long int signal; /* Signal that caused the core dump. */
- int reserved; /* No longer used */
- struct user_pt_regs *u_ar0; /* Used by gdb to help find the values for */
-
- /* the registers */
- unsigned long magic; /* To uniquely identify a core file */
- char u_comm[32]; /* User command that was responsible */
-};
-#endif
-
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR +(u.start_code)
-#define HOST_STACK_END_ADDR +(u.start_stack + u.u_ssize * NBPG)
-
-#endif /* _ASM_USER_H */
diff --git a/arch/mn10300/include/asm/vga.h b/arch/mn10300/include/asm/vga.h
deleted file mode 100644
index 0163e50a3459..000000000000
--- a/arch/mn10300/include/asm/vga.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* MN10300 VGA register definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_VGA_H
-#define _ASM_VGA_H
-
-
-
-#endif /* _ASM_VGA_H */
diff --git a/arch/mn10300/include/asm/xor.h b/arch/mn10300/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/arch/mn10300/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/arch/mn10300/include/uapi/asm/Kbuild b/arch/mn10300/include/uapi/asm/Kbuild
deleted file mode 100644
index b04fd1632051..000000000000
--- a/arch/mn10300/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,6 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += bpf_perf_event.h
-generic-y += poll.h
-generic-y += siginfo.h
diff --git a/arch/mn10300/include/uapi/asm/auxvec.h b/arch/mn10300/include/uapi/asm/auxvec.h
deleted file mode 100644
index 4fdb60b2ae39..000000000000
--- a/arch/mn10300/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_AUXVEC_H
-#define _ASM_AUXVEC_H
-
-#endif
diff --git a/arch/mn10300/include/uapi/asm/bitsperlong.h b/arch/mn10300/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index 76da34b10f59..000000000000
--- a/arch/mn10300/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/mn10300/include/uapi/asm/byteorder.h b/arch/mn10300/include/uapi/asm/byteorder.h
deleted file mode 100644
index 3467df91216c..000000000000
--- a/arch/mn10300/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_BYTEORDER_H
-#define _ASM_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mn10300/include/uapi/asm/errno.h b/arch/mn10300/include/uapi/asm/errno.h
deleted file mode 100644
index 9addba592646..000000000000
--- a/arch/mn10300/include/uapi/asm/errno.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/errno.h>
diff --git a/arch/mn10300/include/uapi/asm/fcntl.h b/arch/mn10300/include/uapi/asm/fcntl.h
deleted file mode 100644
index a77648c505d1..000000000000
--- a/arch/mn10300/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/fcntl.h>
diff --git a/arch/mn10300/include/uapi/asm/ioctl.h b/arch/mn10300/include/uapi/asm/ioctl.h
deleted file mode 100644
index b809c4566e5f..000000000000
--- a/arch/mn10300/include/uapi/asm/ioctl.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ioctl.h>
diff --git a/arch/mn10300/include/uapi/asm/ioctls.h b/arch/mn10300/include/uapi/asm/ioctls.h
deleted file mode 100644
index 0955d4f854e9..000000000000
--- a/arch/mn10300/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_IOCTLS_H
-#define _ASM_IOCTLS_H
-
-#include <asm-generic/ioctls.h>
-
-#endif /* _ASM_IOCTLS_H */
diff --git a/arch/mn10300/include/uapi/asm/ipcbuf.h b/arch/mn10300/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 90d6445a14df..000000000000
--- a/arch/mn10300/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/mn10300/include/uapi/asm/kvm_para.h b/arch/mn10300/include/uapi/asm/kvm_para.h
deleted file mode 100644
index baacc4996d18..000000000000
--- a/arch/mn10300/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/kvm_para.h>
diff --git a/arch/mn10300/include/uapi/asm/mman.h b/arch/mn10300/include/uapi/asm/mman.h
deleted file mode 100644
index eb7f4798c036..000000000000
--- a/arch/mn10300/include/uapi/asm/mman.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/mman.h>
-
-#define MIN_MAP_ADDR PAGE_SIZE /* minimum fixed mmap address */
-
-#define arch_mmap_check(addr, len, flags) \
- (((flags) & MAP_FIXED && (addr) < MIN_MAP_ADDR) ? -EINVAL : 0)
diff --git a/arch/mn10300/include/uapi/asm/msgbuf.h b/arch/mn10300/include/uapi/asm/msgbuf.h
deleted file mode 100644
index 5982def83355..000000000000
--- a/arch/mn10300/include/uapi/asm/msgbuf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_MSGBUF_H
-#define _ASM_MSGBUF_H
-
-/*
- * The msqid64_ds structure for MN10300 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
- struct ipc64_perm msg_perm;
- __kernel_time_t msg_stime; /* last msgsnd time */
- unsigned long __unused1;
- __kernel_time_t msg_rtime; /* last msgrcv time */
- unsigned long __unused2;
- __kernel_time_t msg_ctime; /* last change time */
- unsigned long __unused3;
- unsigned long msg_cbytes; /* current number of bytes on queue */
- unsigned long msg_qnum; /* number of messages in queue */
- unsigned long msg_qbytes; /* max number of bytes on queue */
- __kernel_pid_t msg_lspid; /* pid of last msgsnd */
- __kernel_pid_t msg_lrpid; /* last receive pid */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-#endif /* _ASM_MSGBUF_H */
diff --git a/arch/mn10300/include/uapi/asm/param.h b/arch/mn10300/include/uapi/asm/param.h
deleted file mode 100644
index e0020d7742bd..000000000000
--- a/arch/mn10300/include/uapi/asm/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 Kernel parameters
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PARAM_H
-#define _ASM_PARAM_H
-
-#include <asm-generic/param.h>
-
-#define COMMAND_LINE_SIZE 256
-
-#endif /* _ASM_PARAM_H */
diff --git a/arch/mn10300/include/uapi/asm/posix_types.h b/arch/mn10300/include/uapi/asm/posix_types.h
deleted file mode 100644
index 6b4cfc7136e9..000000000000
--- a/arch/mn10300/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 POSIX types
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_POSIX_TYPES_H
-#define _ASM_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_mode_t;
-#define __kernel_mode_t __kernel_mode_t
-
-typedef unsigned short __kernel_ipc_pid_t;
-#define __kernel_ipc_pid_t __kernel_ipc_pid_t
-
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#define __kernel_uid_t __kernel_uid_t
-
-#if __GNUC__ == 4
-typedef unsigned int __kernel_size_t;
-typedef signed int __kernel_ssize_t;
-#else
-typedef unsigned long __kernel_size_t;
-typedef signed long __kernel_ssize_t;
-#endif
-typedef int __kernel_ptrdiff_t;
-#define __kernel_size_t __kernel_size_t
-
-typedef unsigned short __kernel_old_dev_t;
-#define __kernel_old_dev_t __kernel_old_dev_t
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _ASM_POSIX_TYPES_H */
diff --git a/arch/mn10300/include/uapi/asm/ptrace.h b/arch/mn10300/include/uapi/asm/ptrace.h
deleted file mode 100644
index f485c481a266..000000000000
--- a/arch/mn10300/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 Exception frame layout and ptrace constants
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _UAPI_ASM_PTRACE_H
-#define _UAPI_ASM_PTRACE_H
-
-#define PT_A3 0
-#define PT_A2 1
-#define PT_D3 2
-#define PT_D2 3
-#define PT_MCVF 4
-#define PT_MCRL 5
-#define PT_MCRH 6
-#define PT_MDRQ 7
-#define PT_E1 8
-#define PT_E0 9
-#define PT_E7 10
-#define PT_E6 11
-#define PT_E5 12
-#define PT_E4 13
-#define PT_E3 14
-#define PT_E2 15
-#define PT_SP 16
-#define PT_LAR 17
-#define PT_LIR 18
-#define PT_MDR 19
-#define PT_A1 20
-#define PT_A0 21
-#define PT_D1 22
-#define PT_D0 23
-#define PT_ORIG_D0 24
-#define PT_EPSW 25
-#define PT_PC 26
-#define NR_PTREGS 27
-
-/*
- * This defines the way registers are stored in the event of an exception
- * - the strange order is due to the MOVM instruction
- */
-struct pt_regs {
- unsigned long a3; /* syscall arg 3 */
- unsigned long a2; /* syscall arg 4 */
- unsigned long d3; /* syscall arg 5 */
- unsigned long d2; /* syscall arg 6 */
- unsigned long mcvf;
- unsigned long mcrl;
- unsigned long mcrh;
- unsigned long mdrq;
- unsigned long e1;
- unsigned long e0;
- unsigned long e7;
- unsigned long e6;
- unsigned long e5;
- unsigned long e4;
- unsigned long e3;
- unsigned long e2;
- unsigned long sp;
- unsigned long lar;
- unsigned long lir;
- unsigned long mdr;
- unsigned long a1;
- unsigned long a0; /* syscall arg 1 */
- unsigned long d1; /* syscall arg 2 */
- unsigned long d0; /* syscall ret */
- struct pt_regs *next; /* next frame pointer */
- unsigned long orig_d0; /* syscall number */
- unsigned long epsw;
- unsigned long pc;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-
-#endif /* _UAPI_ASM_PTRACE_H */
diff --git a/arch/mn10300/include/uapi/asm/resource.h b/arch/mn10300/include/uapi/asm/resource.h
deleted file mode 100644
index 49a81fbab43d..000000000000
--- a/arch/mn10300/include/uapi/asm/resource.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/resource.h>
diff --git a/arch/mn10300/include/uapi/asm/sembuf.h b/arch/mn10300/include/uapi/asm/sembuf.h
deleted file mode 100644
index ef44c42c7e0f..000000000000
--- a/arch/mn10300/include/uapi/asm/sembuf.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SEMBUF_H
-#define _ASM_SEMBUF_H
-
-/*
- * The semid64_ds structure for MN10300 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
- struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
- __kernel_time_t sem_otime; /* last semop time */
- unsigned long __unused1;
- __kernel_time_t sem_ctime; /* last change time */
- unsigned long __unused2;
- unsigned long sem_nsems; /* no. of semaphores in array */
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_SEMBUF_H */
diff --git a/arch/mn10300/include/uapi/asm/setup.h b/arch/mn10300/include/uapi/asm/setup.h
deleted file mode 100644
index 043dd4b92026..000000000000
--- a/arch/mn10300/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * There isn't anything here anymore, but the file must not be empty or patch
- * will delete it.
- */
diff --git a/arch/mn10300/include/uapi/asm/shmbuf.h b/arch/mn10300/include/uapi/asm/shmbuf.h
deleted file mode 100644
index 6e81f74f51c6..000000000000
--- a/arch/mn10300/include/uapi/asm/shmbuf.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SHMBUF_H
-#define _ASM_SHMBUF_H
-
-/*
- * The shmid64_ds structure for MN10300 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
- struct ipc64_perm shm_perm; /* operation perms */
- size_t shm_segsz; /* size of segment (bytes) */
- __kernel_time_t shm_atime; /* last attach time */
- unsigned long __unused1;
- __kernel_time_t shm_dtime; /* last detach time */
- unsigned long __unused2;
- __kernel_time_t shm_ctime; /* last change time */
- unsigned long __unused3;
- __kernel_pid_t shm_cpid; /* pid of creator */
- __kernel_pid_t shm_lpid; /* pid of last operator */
- unsigned long shm_nattch; /* no. of current attaches */
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-struct shminfo64 {
- unsigned long shmmax;
- unsigned long shmmin;
- unsigned long shmmni;
- unsigned long shmseg;
- unsigned long shmall;
- unsigned long __unused1;
- unsigned long __unused2;
- unsigned long __unused3;
- unsigned long __unused4;
-};
-
-#endif /* _ASM_SHMBUF_H */
diff --git a/arch/mn10300/include/uapi/asm/sigcontext.h b/arch/mn10300/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 1c361fabb977..000000000000
--- a/arch/mn10300/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 Userspace signal context
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_SIGCONTEXT_H
-#define _ASM_SIGCONTEXT_H
-
-struct fpucontext {
- /* Regular FPU environment */
- unsigned long fs[32]; /* fpu registers */
- unsigned long fpcr; /* fpu control register */
-};
-
-struct sigcontext {
- unsigned long d0;
- unsigned long d1;
- unsigned long d2;
- unsigned long d3;
- unsigned long a0;
- unsigned long a1;
- unsigned long a2;
- unsigned long a3;
- unsigned long e0;
- unsigned long e1;
- unsigned long e2;
- unsigned long e3;
- unsigned long e4;
- unsigned long e5;
- unsigned long e6;
- unsigned long e7;
- unsigned long lar;
- unsigned long lir;
- unsigned long mdr;
- unsigned long mcvf;
- unsigned long mcrl;
- unsigned long mcrh;
- unsigned long mdrq;
- unsigned long sp;
- unsigned long epsw;
- unsigned long pc;
- struct fpucontext *fpucontext;
- unsigned long oldmask;
-};
-
-
-#endif /* _ASM_SIGCONTEXT_H */
diff --git a/arch/mn10300/include/uapi/asm/signal.h b/arch/mn10300/include/uapi/asm/signal.h
deleted file mode 100644
index 566cb199d5ac..000000000000
--- a/arch/mn10300/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 Signal definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _UAPI_ASM_SIGNAL_H
-#define _UAPI_ASM_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems. */
-struct siginfo;
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-#define NSIG 32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP 1
-#define SIGINT 2
-#define SIGQUIT 3
-#define SIGILL 4
-#define SIGTRAP 5
-#define SIGABRT 6
-#define SIGIOT 6
-#define SIGBUS 7
-#define SIGFPE 8
-#define SIGKILL 9
-#define SIGUSR1 10
-#define SIGSEGV 11
-#define SIGUSR2 12
-#define SIGPIPE 13
-#define SIGALRM 14
-#define SIGTERM 15
-#define SIGSTKFLT 16
-#define SIGCHLD 17
-#define SIGCONT 18
-#define SIGSTOP 19
-#define SIGTSTP 20
-#define SIGTTIN 21
-#define SIGTTOU 22
-#define SIGURG 23
-#define SIGXCPU 24
-#define SIGXFSZ 25
-#define SIGVTALRM 26
-#define SIGPROF 27
-#define SIGWINCH 28
-#define SIGIO 29
-#define SIGPOLL SIGIO
-/*
-#define SIGLOST 29
-*/
-#define SIGPWR 30
-#define SIGSYS 31
-#define SIGUNUSED 31
-
-/* These should not be considered constants from userland. */
-#define SIGRTMIN 32
-#define SIGRTMAX _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP 0x00000001U
-#define SA_NOCLDWAIT 0x00000002U
-#define SA_SIGINFO 0x00000004U
-#define SA_ONSTACK 0x08000000U
-#define SA_RESTART 0x10000000U
-#define SA_NODEFER 0x40000000U
-#define SA_RESETHAND 0x80000000U
-
-#define SA_NOMASK SA_NODEFER
-#define SA_ONESHOT SA_RESETHAND
-
-#define SA_RESTORER 0x04000000
-
-#define MINSIGSTKSZ 2048
-#define SIGSTKSZ 8192
-
-#include <asm-generic/signal-defs.h>
-
-#ifndef __KERNEL__
-/* Here we must cater to libcs that poke about in kernel headers. */
-
-struct sigaction {
- union {
- __sighandler_t _sa_handler;
- void (*_sa_sigaction)(int, struct siginfo *, void *);
- } _u;
- sigset_t sa_mask;
- unsigned long sa_flags;
- void (*sa_restorer)(void);
-};
-
-#define sa_handler _u._sa_handler
-#define sa_sigaction _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
- void __user *ss_sp;
- int ss_flags;
- size_t ss_size;
-} stack_t;
-
-
-#endif /* _UAPI_ASM_SIGNAL_H */
diff --git a/arch/mn10300/include/uapi/asm/socket.h b/arch/mn10300/include/uapi/asm/socket.h
deleted file mode 100644
index b35eee132142..000000000000
--- a/arch/mn10300/include/uapi/asm/socket.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-#define SOL_SOCKET 1
-
-#define SO_DEBUG 1
-#define SO_REUSEADDR 2
-#define SO_TYPE 3
-#define SO_ERROR 4
-#define SO_DONTROUTE 5
-#define SO_BROADCAST 6
-#define SO_SNDBUF 7
-#define SO_RCVBUF 8
-#define SO_SNDBUFFORCE 32
-#define SO_RCVBUFFORCE 33
-#define SO_KEEPALIVE 9
-#define SO_OOBINLINE 10
-#define SO_NO_CHECK 11
-#define SO_PRIORITY 12
-#define SO_LINGER 13
-#define SO_BSDCOMPAT 14
-#define SO_REUSEPORT 15
-#define SO_PASSCRED 16
-#define SO_PEERCRED 17
-#define SO_RCVLOWAT 18
-#define SO_SNDLOWAT 19
-#define SO_RCVTIMEO 20
-#define SO_SNDTIMEO 21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION 22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
-#define SO_SECURITY_ENCRYPTION_NETWORK 24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER 26
-#define SO_DETACH_FILTER 27
-#define SO_GET_FILTER SO_ATTACH_FILTER
-
-#define SO_PEERNAME 28
-#define SO_TIMESTAMP 29
-#define SCM_TIMESTAMP SO_TIMESTAMP
-
-#define SO_ACCEPTCONN 30
-
-#define SO_PEERSEC 31
-#define SO_PASSSEC 34
-#define SO_TIMESTAMPNS 35
-#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
-
-#define SO_MARK 36
-
-#define SO_TIMESTAMPING 37
-#define SCM_TIMESTAMPING SO_TIMESTAMPING
-
-#define SO_PROTOCOL 38
-#define SO_DOMAIN 39
-
-#define SO_RXQ_OVFL 40
-
-#define SO_WIFI_STATUS 41
-#define SCM_WIFI_STATUS SO_WIFI_STATUS
-#define SO_PEEK_OFF 42
-
-/* Instruct lower device to use last 4-bytes of skb data as FCS */
-#define SO_NOFCS 43
-
-#define SO_LOCK_FILTER 44
-
-#define SO_SELECT_ERR_QUEUE 45
-
-#define SO_BUSY_POLL 46
-
-#define SO_MAX_PACING_RATE 47
-
-#define SO_BPF_EXTENSIONS 48
-
-#define SO_INCOMING_CPU 49
-
-#define SO_ATTACH_BPF 50
-#define SO_DETACH_BPF SO_DETACH_FILTER
-
-#define SO_ATTACH_REUSEPORT_CBPF 51
-#define SO_ATTACH_REUSEPORT_EBPF 52
-
-#define SO_CNX_ADVICE 53
-
-#define SCM_TIMESTAMPING_OPT_STATS 54
-
-#define SO_MEMINFO 55
-
-#define SO_INCOMING_NAPI_ID 56
-
-#define SO_COOKIE 57
-
-#define SCM_TIMESTAMPING_PKTINFO 58
-
-#define SO_PEERGROUPS 59
-
-#define SO_ZEROCOPY 60
-
-#endif /* _ASM_SOCKET_H */
diff --git a/arch/mn10300/include/uapi/asm/sockios.h b/arch/mn10300/include/uapi/asm/sockios.h
deleted file mode 100644
index 5706baa3cd0d..000000000000
--- a/arch/mn10300/include/uapi/asm/sockios.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SOCKIOS_H
-#define _ASM_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN 0x8901
-#define SIOCSPGRP 0x8902
-#define FIOGETOWN 0x8903
-#define SIOCGPGRP 0x8904
-#define SIOCATMARK 0x8905
-#define SIOCGSTAMP 0x8906 /* Get stamp */
-#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
-
-#endif /* _ASM_SOCKIOS_H */
diff --git a/arch/mn10300/include/uapi/asm/stat.h b/arch/mn10300/include/uapi/asm/stat.h
deleted file mode 100644
index 769f5f8829d4..000000000000
--- a/arch/mn10300/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_STAT_H
-#define _ASM_STAT_H
-
-struct __old_kernel_stat {
- unsigned short st_dev;
- unsigned short st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned short st_rdev;
- unsigned long st_size;
- unsigned long st_atime;
- unsigned long st_mtime;
- unsigned long st_ctime;
-};
-
-struct stat {
- unsigned long st_dev;
- unsigned long st_ino;
- unsigned short st_mode;
- unsigned short st_nlink;
- unsigned short st_uid;
- unsigned short st_gid;
- unsigned long st_rdev;
- unsigned long st_size;
- unsigned long st_blksize;
- unsigned long st_blocks;
- unsigned long st_atime;
- unsigned long st_atime_nsec;
- unsigned long st_mtime;
- unsigned long st_mtime_nsec;
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
- unsigned long __unused4;
- unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
- unsigned long long st_dev;
- unsigned char __pad0[4];
-
-#define STAT64_HAS_BROKEN_ST_INO 1
- unsigned long __st_ino;
-
- unsigned int st_mode;
- unsigned int st_nlink;
-
- unsigned long st_uid;
- unsigned long st_gid;
-
- unsigned long long st_rdev;
- unsigned char __pad3[4];
-
- long long st_size;
- unsigned long st_blksize;
-
- unsigned long st_blocks; /* Number 512-byte blocks allocated. */
- unsigned long __pad4; /* future possible st_blocks high bits */
-
- unsigned long st_atime;
- unsigned long st_atime_nsec;
-
- unsigned long st_mtime;
- unsigned int st_mtime_nsec;
-
- unsigned long st_ctime;
- unsigned long st_ctime_nsec;
-
- unsigned long long st_ino;
-};
-
-#define STAT_HAVE_NSEC 1
-
-#endif /* _ASM_STAT_H */
diff --git a/arch/mn10300/include/uapi/asm/statfs.h b/arch/mn10300/include/uapi/asm/statfs.h
deleted file mode 100644
index 0b91fe198c20..000000000000
--- a/arch/mn10300/include/uapi/asm/statfs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/statfs.h>
diff --git a/arch/mn10300/include/uapi/asm/swab.h b/arch/mn10300/include/uapi/asm/swab.h
deleted file mode 100644
index d2284dd27ad4..000000000000
--- a/arch/mn10300/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 Byte-order primitive construction
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_SWAB_H
-#define _ASM_SWAB_H
-
-#include <linux/types.h>
-
-#ifdef __GNUC__
-
-static inline __attribute__((const))
-__u32 __arch_swab32(__u32 x)
-{
- __u32 ret;
- asm("swap %1,%0" : "=r" (ret) : "r" (x));
- return ret;
-}
-#define __arch_swab32 __arch_swab32
-
-static inline __attribute__((const))
-__u16 __arch_swab16(__u16 x)
-{
- __u16 ret;
- asm("swaph %1,%0" : "=r" (ret) : "r" (x));
- return ret;
-}
-#define __arch_swab32 __arch_swab32
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#endif /* _ASM_SWAB_H */
diff --git a/arch/mn10300/include/uapi/asm/termbits.h b/arch/mn10300/include/uapi/asm/termbits.h
deleted file mode 100644
index fca82ea2ca2c..000000000000
--- a/arch/mn10300/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_TERMBITS_H
-#define _ASM_TERMBITS_H
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
-};
-
-struct termios2 {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-struct ktermios {
- tcflag_t c_iflag; /* input mode flags */
- tcflag_t c_oflag; /* output mode flags */
- tcflag_t c_cflag; /* control mode flags */
- tcflag_t c_lflag; /* local mode flags */
- cc_t c_line; /* line discipline */
- cc_t c_cc[NCCS]; /* control characters */
- speed_t c_ispeed; /* input speed */
- speed_t c_ospeed; /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-
-/* c_iflag bits */
-#define IGNBRK 0000001
-#define BRKINT 0000002
-#define IGNPAR 0000004
-#define PARMRK 0000010
-#define INPCK 0000020
-#define ISTRIP 0000040
-#define INLCR 0000100
-#define IGNCR 0000200
-#define ICRNL 0000400
-#define IUCLC 0001000
-#define IXON 0002000
-#define IXANY 0004000
-#define IXOFF 0010000
-#define IMAXBEL 0020000
-#define IUTF8 0040000
-
-/* c_oflag bits */
-#define OPOST 0000001
-#define OLCUC 0000002
-#define ONLCR 0000004
-#define OCRNL 0000010
-#define ONOCR 0000020
-#define ONLRET 0000040
-#define OFILL 0000100
-#define OFDEL 0000200
-#define NLDLY 0000400
-#define NL0 0000000
-#define NL1 0000400
-#define CRDLY 0003000
-#define CR0 0000000
-#define CR1 0001000
-#define CR2 0002000
-#define CR3 0003000
-#define TABDLY 0014000
-#define TAB0 0000000
-#define TAB1 0004000
-#define TAB2 0010000
-#define TAB3 0014000
-#define XTABS 0014000
-#define BSDLY 0020000
-#define BS0 0000000
-#define BS1 0020000
-#define VTDLY 0040000
-#define VT0 0000000
-#define VT1 0040000
-#define FFDLY 0100000
-#define FF0 0000000
-#define FF1 0100000
-
-/* c_cflag bit meaning */
-#define CBAUD 0010017
-#define B0 0000000 /* hang up */
-#define B50 0000001
-#define B75 0000002
-#define B110 0000003
-#define B134 0000004
-#define B150 0000005
-#define B200 0000006
-#define B300 0000007
-#define B600 0000010
-#define B1200 0000011
-#define B1800 0000012
-#define B2400 0000013
-#define B4800 0000014
-#define B9600 0000015
-#define B19200 0000016
-#define B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE 0000060
-#define CS5 0000000
-#define CS6 0000020
-#define CS7 0000040
-#define CS8 0000060
-#define CSTOPB 0000100
-#define CREAD 0000200
-#define PARENB 0000400
-#define PARODD 0001000
-#define HUPCL 0002000
-#define CLOCAL 0004000
-#define CBAUDEX 0010000
-#define BOTHER 0010000
-#define B57600 0010001
-#define B115200 0010002
-#define B230400 0010003
-#define B460800 0010004
-#define B500000 0010005
-#define B576000 0010006
-#define B921600 0010007
-#define B1000000 0010010
-#define B1152000 0010011
-#define B1500000 0010012
-#define B2000000 0010013
-#define B2500000 0010014
-#define B3000000 0010015
-#define B3500000 0010016
-#define B4000000 0010017
-#define CIBAUD 002003600000 /* input baud rate (not used) */
-#define CTVB 004000000000 /* VisioBraille Terminal flow control */
-#define CMSPAR 010000000000 /* mark or space (stick) parity */
-#define CRTSCTS 020000000000 /* flow control */
-
-#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG 0000001
-#define ICANON 0000002
-#define XCASE 0000004
-#define ECHO 0000010
-#define ECHOE 0000020
-#define ECHOK 0000040
-#define ECHONL 0000100
-#define NOFLSH 0000200
-#define TOSTOP 0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE 0004000
-#define FLUSHO 0010000
-#define PENDIN 0040000
-#define IEXTEN 0100000
-#define EXTPROC 0200000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF 0
-#define TCOON 1
-#define TCIOFF 2
-#define TCION 3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH 0
-#define TCOFLUSH 1
-#define TCIOFLUSH 2
-
-/* tcsetattr uses these */
-#define TCSANOW 0
-#define TCSADRAIN 1
-#define TCSAFLUSH 2
-
-#endif /* _ASM_TERMBITS_H */
diff --git a/arch/mn10300/include/uapi/asm/termios.h b/arch/mn10300/include/uapi/asm/termios.h
deleted file mode 100644
index 25981aadb8cd..000000000000
--- a/arch/mn10300/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_TERMIOS_H
-#define _UAPI_ASM_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
- unsigned short ws_row;
- unsigned short ws_col;
- unsigned short ws_xpixel;
- unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
- unsigned short c_iflag; /* input mode flags */
- unsigned short c_oflag; /* output mode flags */
- unsigned short c_cflag; /* control mode flags */
- unsigned short c_lflag; /* local mode flags */
- unsigned char c_line; /* line discipline */
- unsigned char c_cc[NCC]; /* control characters */
-};
-
-
-/* modem lines */
-#define TIOCM_LE 0x001
-#define TIOCM_DTR 0x002
-#define TIOCM_RTS 0x004
-#define TIOCM_ST 0x008
-#define TIOCM_SR 0x010
-#define TIOCM_CTS 0x020
-#define TIOCM_CAR 0x040
-#define TIOCM_RNG 0x080
-#define TIOCM_DSR 0x100
-#define TIOCM_CD TIOCM_CAR
-#define TIOCM_RI TIOCM_RNG
-#define TIOCM_OUT1 0x2000
-#define TIOCM_OUT2 0x4000
-#define TIOCM_LOOP 0x8000
-
-#define TIOCM_MODEM_BITS TIOCM_OUT2 /* IRDA support */
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
- unsigned short __tmp; \
- get_user(__tmp, &(termio)->x); \
- *(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
- SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
- SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
- copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
- put_user((termios)->c_iflag, &(termio)->c_iflag); \
- put_user((termios)->c_oflag, &(termio)->c_oflag); \
- put_user((termios)->c_cflag, &(termio)->c_cflag); \
- put_user((termios)->c_lflag, &(termio)->c_lflag); \
- put_user((termios)->c_line, &(termio)->c_line); \
- copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) \
- copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) \
- copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) \
- copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) \
- copy_to_user(u, k, sizeof(struct termios))
-
-#endif /* _UAPI_ASM_TERMIOS_H */
diff --git a/arch/mn10300/include/uapi/asm/types.h b/arch/mn10300/include/uapi/asm/types.h
deleted file mode 100644
index 7d2a697e2937..000000000000
--- a/arch/mn10300/include/uapi/asm/types.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 Basic type definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm-generic/int-ll64.h>
diff --git a/arch/mn10300/include/uapi/asm/unistd.h b/arch/mn10300/include/uapi/asm/unistd.h
deleted file mode 100644
index c0c96b650692..000000000000
--- a/arch/mn10300/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
-/* MN10300 System call number list
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _UAPI_ASM_UNISTD_H
-#define _UAPI_ASM_UNISTD_H
-
-#define __NR_restart_syscall 0
-#define __NR_exit 1
-#define __NR_fork 2
-#define __NR_read 3
-#define __NR_write 4
-#define __NR_open 5
-#define __NR_close 6
-#define __NR_waitpid 7
-#define __NR_creat 8
-#define __NR_link 9
-#define __NR_unlink 10
-#define __NR_execve 11
-#define __NR_chdir 12
-#define __NR_time 13
-#define __NR_mknod 14
-#define __NR_chmod 15
-#define __NR_lchown 16
-#define __NR_break 17
-#define __NR_oldstat 18
-#define __NR_lseek 19
-#define __NR_getpid 20
-#define __NR_mount 21
-#define __NR_umount 22
-#define __NR_setuid 23
-#define __NR_getuid 24
-#define __NR_stime 25
-#define __NR_ptrace 26
-#define __NR_alarm 27
-#define __NR_oldfstat 28
-#define __NR_pause 29
-#define __NR_utime 30
-#define __NR_stty 31
-#define __NR_gtty 32
-#define __NR_access 33
-#define __NR_nice 34
-#define __NR_ftime 35
-#define __NR_sync 36
-#define __NR_kill 37
-#define __NR_rename 38
-#define __NR_mkdir 39
-#define __NR_rmdir 40
-#define __NR_dup 41
-#define __NR_pipe 42
-#define __NR_times 43
-#define __NR_prof 44
-#define __NR_brk 45
-#define __NR_setgid 46
-#define __NR_getgid 47
-#define __NR_signal 48
-#define __NR_geteuid 49
-#define __NR_getegid 50
-#define __NR_acct 51
-#define __NR_umount2 52
-#define __NR_lock 53
-#define __NR_ioctl 54
-#define __NR_fcntl 55
-#define __NR_mpx 56
-#define __NR_setpgid 57
-#define __NR_ulimit 58
-#define __NR_oldolduname 59
-#define __NR_umask 60
-#define __NR_chroot 61
-#define __NR_ustat 62
-#define __NR_dup2 63
-#define __NR_getppid 64
-#define __NR_getpgrp 65
-#define __NR_setsid 66
-#define __NR_sigaction 67
-#define __NR_sgetmask 68
-#define __NR_ssetmask 69
-#define __NR_setreuid 70
-#define __NR_setregid 71
-#define __NR_sigsuspend 72
-#define __NR_sigpending 73
-#define __NR_sethostname 74
-#define __NR_setrlimit 75
-#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
-#define __NR_getrusage 77
-#define __NR_gettimeofday 78
-#define __NR_settimeofday 79
-#define __NR_getgroups 80
-#define __NR_setgroups 81
-#define __NR_select 82
-#define __NR_symlink 83
-#define __NR_oldlstat 84
-#define __NR_readlink 85
-#define __NR_uselib 86
-#define __NR_swapon 87
-#define __NR_reboot 88
-#define __NR_readdir 89
-#define __NR_mmap 90
-#define __NR_munmap 91
-#define __NR_truncate 92
-#define __NR_ftruncate 93
-#define __NR_fchmod 94
-#define __NR_fchown 95
-#define __NR_getpriority 96
-#define __NR_setpriority 97
-#define __NR_profil 98
-#define __NR_statfs 99
-#define __NR_fstatfs 100
-#define __NR_ioperm 101
-#define __NR_socketcall 102
-#define __NR_syslog 103
-#define __NR_setitimer 104
-#define __NR_getitimer 105
-#define __NR_stat 106
-#define __NR_lstat 107
-#define __NR_fstat 108
-#define __NR_olduname 109
-#define __NR_iopl 110
-#define __NR_vhangup 111
-#define __NR_idle 112
-#define __NR_vm86old 113
-#define __NR_wait4 114
-#define __NR_swapoff 115
-#define __NR_sysinfo 116
-#define __NR_ipc 117
-#define __NR_fsync 118
-#define __NR_sigreturn 119
-#define __NR_clone 120
-#define __NR_setdomainname 121
-#define __NR_uname 122
-#define __NR_modify_ldt 123
-#define __NR_adjtimex 124
-#define __NR_mprotect 125
-#define __NR_sigprocmask 126
-#define __NR_create_module 127
-#define __NR_init_module 128
-#define __NR_delete_module 129
-#define __NR_get_kernel_syms 130
-#define __NR_quotactl 131
-#define __NR_getpgid 132
-#define __NR_fchdir 133
-#define __NR_bdflush 134
-#define __NR_sysfs 135
-#define __NR_personality 136
-#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
-#define __NR_setfsuid 138
-#define __NR_setfsgid 139
-#define __NR__llseek 140
-#define __NR_getdents 141
-#define __NR__newselect 142
-#define __NR_flock 143
-#define __NR_msync 144
-#define __NR_readv 145
-#define __NR_writev 146
-#define __NR_getsid 147
-#define __NR_fdatasync 148
-#define __NR__sysctl 149
-#define __NR_mlock 150
-#define __NR_munlock 151
-#define __NR_mlockall 152
-#define __NR_munlockall 153
-#define __NR_sched_setparam 154
-#define __NR_sched_getparam 155
-#define __NR_sched_setscheduler 156
-#define __NR_sched_getscheduler 157
-#define __NR_sched_yield 158
-#define __NR_sched_get_priority_max 159
-#define __NR_sched_get_priority_min 160
-#define __NR_sched_rr_get_interval 161
-#define __NR_nanosleep 162
-#define __NR_mremap 163
-#define __NR_setresuid 164
-#define __NR_getresuid 165
-#define __NR_vm86 166
-#define __NR_query_module 167
-#define __NR_poll 168
-#define __NR_nfsservctl 169
-#define __NR_setresgid 170
-#define __NR_getresgid 171
-#define __NR_prctl 172
-#define __NR_rt_sigreturn 173
-#define __NR_rt_sigaction 174
-#define __NR_rt_sigprocmask 175
-#define __NR_rt_sigpending 176
-#define __NR_rt_sigtimedwait 177
-#define __NR_rt_sigqueueinfo 178
-#define __NR_rt_sigsuspend 179
-#define __NR_pread64 180
-#define __NR_pwrite64 181
-#define __NR_chown 182
-#define __NR_getcwd 183
-#define __NR_capget 184
-#define __NR_capset 185
-#define __NR_sigaltstack 186
-#define __NR_sendfile 187
-#define __NR_getpmsg 188 /* some people actually want streams */
-#define __NR_putpmsg 189 /* some people actually want streams */
-#define __NR_vfork 190
-#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
-#define __NR_mmap2 192
-#define __NR_truncate64 193
-#define __NR_ftruncate64 194
-#define __NR_stat64 195
-#define __NR_lstat64 196
-#define __NR_fstat64 197
-#define __NR_lchown32 198
-#define __NR_getuid32 199
-#define __NR_getgid32 200
-#define __NR_geteuid32 201
-#define __NR_getegid32 202
-#define __NR_setreuid32 203
-#define __NR_setregid32 204
-#define __NR_getgroups32 205
-#define __NR_setgroups32 206
-#define __NR_fchown32 207
-#define __NR_setresuid32 208
-#define __NR_getresuid32 209
-#define __NR_setresgid32 210
-#define __NR_getresgid32 211
-#define __NR_chown32 212
-#define __NR_setuid32 213
-#define __NR_setgid32 214
-#define __NR_setfsuid32 215
-#define __NR_setfsgid32 216
-#define __NR_pivot_root 217
-#define __NR_mincore 218
-#define __NR_madvise 219
-#define __NR_madvise1 219 /* delete when C lib stub is removed */
-#define __NR_getdents64 220
-#define __NR_fcntl64 221
-/* 223 is unused */
-#define __NR_gettid 224
-#define __NR_readahead 225
-#define __NR_setxattr 226
-#define __NR_lsetxattr 227
-#define __NR_fsetxattr 228
-#define __NR_getxattr 229
-#define __NR_lgetxattr 230
-#define __NR_fgetxattr 231
-#define __NR_listxattr 232
-#define __NR_llistxattr 233
-#define __NR_flistxattr 234
-#define __NR_removexattr 235
-#define __NR_lremovexattr 236
-#define __NR_fremovexattr 237
-#define __NR_tkill 238
-#define __NR_sendfile64 239
-#define __NR_futex 240
-#define __NR_sched_setaffinity 241
-#define __NR_sched_getaffinity 242
-#define __NR_set_thread_area 243
-#define __NR_get_thread_area 244
-#define __NR_io_setup 245
-#define __NR_io_destroy 246
-#define __NR_io_getevents 247
-#define __NR_io_submit 248
-#define __NR_io_cancel 249
-#define __NR_fadvise64 250
-
-#define __NR_exit_group 252
-#define __NR_lookup_dcookie 253
-#define __NR_epoll_create 254
-#define __NR_epoll_ctl 255
-#define __NR_epoll_wait 256
-#define __NR_remap_file_pages 257
-#define __NR_set_tid_address 258
-#define __NR_timer_create 259
-#define __NR_timer_settime (__NR_timer_create+1)
-#define __NR_timer_gettime (__NR_timer_create+2)
-#define __NR_timer_getoverrun (__NR_timer_create+3)
-#define __NR_timer_delete (__NR_timer_create+4)
-#define __NR_clock_settime (__NR_timer_create+5)
-#define __NR_clock_gettime (__NR_timer_create+6)
-#define __NR_clock_getres (__NR_timer_create+7)
-#define __NR_clock_nanosleep (__NR_timer_create+8)
-#define __NR_statfs64 268
-#define __NR_fstatfs64 269
-#define __NR_tgkill 270
-#define __NR_utimes 271
-#define __NR_fadvise64_64 272
-#define __NR_vserver 273
-#define __NR_mbind 274
-#define __NR_get_mempolicy 275
-#define __NR_set_mempolicy 276
-#define __NR_mq_open 277
-#define __NR_mq_unlink (__NR_mq_open+1)
-#define __NR_mq_timedsend (__NR_mq_open+2)
-#define __NR_mq_timedreceive (__NR_mq_open+3)
-#define __NR_mq_notify (__NR_mq_open+4)
-#define __NR_mq_getsetattr (__NR_mq_open+5)
-#define __NR_kexec_load 283
-#define __NR_waitid 284
-#define __NR_add_key 286
-#define __NR_request_key 287
-#define __NR_keyctl 288
-#define __NR_cacheflush 289
-#define __NR_ioprio_set 290
-#define __NR_ioprio_get 291
-#define __NR_inotify_init 292
-#define __NR_inotify_add_watch 293
-#define __NR_inotify_rm_watch 294
-#define __NR_migrate_pages 295
-#define __NR_openat 296
-#define __NR_mkdirat 297
-#define __NR_mknodat 298
-#define __NR_fchownat 299
-#define __NR_futimesat 300
-#define __NR_fstatat64 301
-#define __NR_unlinkat 302
-#define __NR_renameat 303
-#define __NR_linkat 304
-#define __NR_symlinkat 305
-#define __NR_readlinkat 306
-#define __NR_fchmodat 307
-#define __NR_faccessat 308
-#define __NR_pselect6 309
-#define __NR_ppoll 310
-#define __NR_unshare 311
-#define __NR_set_robust_list 312
-#define __NR_get_robust_list 313
-#define __NR_splice 314
-#define __NR_sync_file_range 315
-#define __NR_tee 316
-#define __NR_vmsplice 317
-#define __NR_move_pages 318
-#define __NR_getcpu 319
-#define __NR_epoll_pwait 320
-#define __NR_utimensat 321
-#define __NR_signalfd 322
-#define __NR_timerfd_create 323
-#define __NR_eventfd 324
-#define __NR_fallocate 325
-#define __NR_timerfd_settime 326
-#define __NR_timerfd_gettime 327
-#define __NR_signalfd4 328
-#define __NR_eventfd2 329
-#define __NR_epoll_create1 330
-#define __NR_dup3 331
-#define __NR_pipe2 332
-#define __NR_inotify_init1 333
-#define __NR_preadv 334
-#define __NR_pwritev 335
-#define __NR_rt_tgsigqueueinfo 336
-#define __NR_perf_event_open 337
-#define __NR_recvmmsg 338
-#define __NR_setns 339
-
-#endif /* _UAPI_ASM_UNISTD_H */
diff --git a/arch/mn10300/kernel/Makefile b/arch/mn10300/kernel/Makefile
deleted file mode 100644
index de32af0e4b6e..000000000000
--- a/arch/mn10300/kernel/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the MN10300-specific core kernel code
-#
-extra-y := head.o vmlinux.lds
-
-fpu-obj-y := fpu-nofpu.o fpu-nofpu-low.o
-fpu-obj-$(CONFIG_FPU) := fpu.o fpu-low.o
-
-obj-y := process.o signal.o entry.o traps.o irq.o \
- ptrace.o setup.o time.o sys_mn10300.o io.o \
- switch_to.o mn10300_ksyms.o $(fpu-obj-y) \
- csrc-mn10300.o cevt-mn10300.o
-
-obj-$(CONFIG_SMP) += smp.o smp-low.o
-
-obj-$(CONFIG_MN10300_WD_TIMER) += mn10300-watchdog.o mn10300-watchdog-low.o
-
-obj-$(CONFIG_MN10300_TTYSM) += mn10300-serial.o mn10300-serial-low.o \
- mn10300-debug.o
-obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-low.o
-obj-$(CONFIG_GDBSTUB_ON_TTYSx) += gdb-io-serial.o gdb-io-serial-low.o
-obj-$(CONFIG_GDBSTUB_ON_TTYSMx) += gdb-io-ttysm.o gdb-io-ttysm-low.o
-
-obj-$(CONFIG_MN10300_RTC) += rtc.o
-obj-$(CONFIG_PROFILE) += profile.o profile-low.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_KPROBES) += kprobes.o
-obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/mn10300/kernel/asm-offsets.c b/arch/mn10300/kernel/asm-offsets.c
deleted file mode 100644
index 57e6cc96267b..000000000000
--- a/arch/mn10300/kernel/asm-offsets.c
+++ /dev/null
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed
- * to extract and format the required data.
- */
-
-#include <linux/sched.h>
-#include <linux/signal.h>
-#include <linux/personality.h>
-#include <linux/kbuild.h>
-#include <asm/ucontext.h>
-#include <asm/processor.h>
-#include <asm/thread_info.h>
-#include <asm/ptrace.h>
-#include "sigframe.h"
-#include "mn10300-serial.h"
-
-void foo(void)
-{
- OFFSET(SIGCONTEXT_d0, sigcontext, d0);
- OFFSET(SIGCONTEXT_d1, sigcontext, d1);
- BLANK();
-
- OFFSET(TI_task, thread_info, task);
- OFFSET(TI_frame, thread_info, frame);
- OFFSET(TI_flags, thread_info, flags);
- OFFSET(TI_cpu, thread_info, cpu);
- OFFSET(TI_preempt_count, thread_info, preempt_count);
- OFFSET(TI_addr_limit, thread_info, addr_limit);
- BLANK();
-
- OFFSET(REG_D0, pt_regs, d0);
- OFFSET(REG_D1, pt_regs, d1);
- OFFSET(REG_D2, pt_regs, d2);
- OFFSET(REG_D3, pt_regs, d3);
- OFFSET(REG_A0, pt_regs, a0);
- OFFSET(REG_A1, pt_regs, a1);
- OFFSET(REG_A2, pt_regs, a2);
- OFFSET(REG_A3, pt_regs, a3);
- OFFSET(REG_E0, pt_regs, e0);
- OFFSET(REG_E1, pt_regs, e1);
- OFFSET(REG_E2, pt_regs, e2);
- OFFSET(REG_E3, pt_regs, e3);
- OFFSET(REG_E4, pt_regs, e4);
- OFFSET(REG_E5, pt_regs, e5);
- OFFSET(REG_E6, pt_regs, e6);
- OFFSET(REG_E7, pt_regs, e7);
- OFFSET(REG_SP, pt_regs, sp);
- OFFSET(REG_EPSW, pt_regs, epsw);
- OFFSET(REG_PC, pt_regs, pc);
- OFFSET(REG_LAR, pt_regs, lar);
- OFFSET(REG_LIR, pt_regs, lir);
- OFFSET(REG_MDR, pt_regs, mdr);
- OFFSET(REG_MCVF, pt_regs, mcvf);
- OFFSET(REG_MCRL, pt_regs, mcrl);
- OFFSET(REG_MCRH, pt_regs, mcrh);
- OFFSET(REG_MDRQ, pt_regs, mdrq);
- OFFSET(REG_ORIG_D0, pt_regs, orig_d0);
- OFFSET(REG_NEXT, pt_regs, next);
- DEFINE(REG__END, sizeof(struct pt_regs));
- BLANK();
-
- OFFSET(THREAD_UREGS, thread_struct, uregs);
- OFFSET(THREAD_PC, thread_struct, pc);
- OFFSET(THREAD_SP, thread_struct, sp);
- OFFSET(THREAD_A3, thread_struct, a3);
- OFFSET(THREAD_USP, thread_struct, usp);
-#ifdef CONFIG_FPU
- OFFSET(THREAD_FPU_FLAGS, thread_struct, fpu_flags);
- OFFSET(THREAD_FPU_STATE, thread_struct, fpu_state);
- DEFINE(__THREAD_USING_FPU, THREAD_USING_FPU);
- DEFINE(__THREAD_HAS_FPU, THREAD_HAS_FPU);
-#endif /* CONFIG_FPU */
- BLANK();
-
- OFFSET(TASK_THREAD, task_struct, thread);
- BLANK();
-
- DEFINE(CLONE_VM_asm, CLONE_VM);
- DEFINE(CLONE_FS_asm, CLONE_FS);
- DEFINE(CLONE_FILES_asm, CLONE_FILES);
- DEFINE(CLONE_SIGHAND_asm, CLONE_SIGHAND);
- DEFINE(CLONE_UNTRACED_asm, CLONE_UNTRACED);
- DEFINE(SIGCHLD_asm, SIGCHLD);
- BLANK();
-
- OFFSET(RT_SIGFRAME_sigcontext, rt_sigframe, uc.uc_mcontext);
-
- DEFINE(PAGE_SIZE_asm, PAGE_SIZE);
-
- OFFSET(__rx_buffer, mn10300_serial_port, rx_buffer);
- OFFSET(__rx_inp, mn10300_serial_port, rx_inp);
- OFFSET(__rx_outp, mn10300_serial_port, rx_outp);
- OFFSET(__uart_state, mn10300_serial_port, uart.state);
- OFFSET(__tx_xchar, mn10300_serial_port, tx_xchar);
- OFFSET(__tx_flags, mn10300_serial_port, tx_flags);
- OFFSET(__intr_flags, mn10300_serial_port, intr_flags);
- OFFSET(__rx_icr, mn10300_serial_port, rx_icr);
- OFFSET(__tx_icr, mn10300_serial_port, tx_icr);
- OFFSET(__tm_icr, mn10300_serial_port, _tmicr);
- OFFSET(__iobase, mn10300_serial_port, _iobase);
-
- DEFINE(__UART_XMIT_SIZE, UART_XMIT_SIZE);
- OFFSET(__xmit_buffer, uart_state, xmit.buf);
- OFFSET(__xmit_head, uart_state, xmit.head);
- OFFSET(__xmit_tail, uart_state, xmit.tail);
-}
diff --git a/arch/mn10300/kernel/cevt-mn10300.c b/arch/mn10300/kernel/cevt-mn10300.c
deleted file mode 100644
index 2b21bbc9efa4..000000000000
--- a/arch/mn10300/kernel/cevt-mn10300.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* MN10300 clockevents
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by Mark Salter (msalter@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/percpu.h>
-#include <linux/smp.h>
-#include <asm/timex.h>
-#include "internal.h"
-
-#ifdef CONFIG_SMP
-#if (CONFIG_NR_CPUS > 2) && !defined(CONFIG_GEENERIC_CLOCKEVENTS_BROADCAST)
-#error "This doesn't scale well! Need per-core local timers."
-#endif
-#else /* CONFIG_SMP */
-#define stop_jiffies_counter1()
-#define reload_jiffies_counter1(x)
-#define TMJC1IRQ TMJCIRQ
-#endif
-
-
-static int next_event(unsigned long delta,
- struct clock_event_device *evt)
-{
- unsigned int cpu = smp_processor_id();
-
- if (cpu == 0) {
- stop_jiffies_counter();
- reload_jiffies_counter(delta - 1);
- } else {
- stop_jiffies_counter1();
- reload_jiffies_counter1(delta - 1);
- }
- return 0;
-}
-
-static DEFINE_PER_CPU(struct clock_event_device, mn10300_clockevent_device);
-static DEFINE_PER_CPU(struct irqaction, timer_irq);
-
-static irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *cd;
- unsigned int cpu = smp_processor_id();
-
- if (cpu == 0)
- stop_jiffies_counter();
- else
- stop_jiffies_counter1();
-
- cd = &per_cpu(mn10300_clockevent_device, cpu);
- cd->event_handler(cd);
-
- return IRQ_HANDLED;
-}
-
-static void event_handler(struct clock_event_device *dev)
-{
-}
-
-static inline void setup_jiffies_interrupt(int irq,
- struct irqaction *action)
-{
- u16 tmp;
- setup_irq(irq, action);
- set_intr_level(irq, NUM2GxICR_LEVEL(CONFIG_TIMER_IRQ_LEVEL));
- GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
- tmp = GxICR(irq);
-}
-
-int __init init_clockevents(void)
-{
- struct clock_event_device *cd;
- struct irqaction *iact;
- unsigned int cpu = smp_processor_id();
-
- cd = &per_cpu(mn10300_clockevent_device, cpu);
-
- if (cpu == 0) {
- stop_jiffies_counter();
- cd->irq = TMJCIRQ;
- } else {
- stop_jiffies_counter1();
- cd->irq = TMJC1IRQ;
- }
-
- cd->name = "Timestamp";
- cd->features = CLOCK_EVT_FEAT_ONESHOT;
-
- /* Calculate shift/mult. We want to spawn at least 1 second */
- clockevents_calc_mult_shift(cd, MN10300_JCCLK, 1);
-
- /* Calculate the min / max delta */
- cd->max_delta_ns = clockevent_delta2ns(TMJCBR_MAX, cd);
- cd->max_delta_ticks = TMJCBR_MAX;
- cd->min_delta_ns = clockevent_delta2ns(100, cd);
- cd->min_delta_ticks = 100;
-
- cd->rating = 200;
- cd->cpumask = cpumask_of(smp_processor_id());
- cd->event_handler = event_handler;
- cd->set_next_event = next_event;
-
- iact = &per_cpu(timer_irq, cpu);
- iact->flags = IRQF_SHARED | IRQF_TIMER;
- iact->handler = timer_interrupt;
-
- clockevents_register_device(cd);
-
-#if defined(CONFIG_SMP) && !defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
- /* setup timer irq affinity so it only runs on this cpu */
- {
- struct irq_data *data;
- data = irq_get_irq_data(cd->irq);
- cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu));
- iact->flags |= IRQF_NOBALANCING;
- }
-#endif
-
- if (cpu == 0) {
- reload_jiffies_counter(MN10300_JC_PER_HZ - 1);
- iact->name = "CPU0 Timer";
- } else {
- reload_jiffies_counter1(MN10300_JC_PER_HZ - 1);
- iact->name = "CPU1 Timer";
- }
-
- setup_jiffies_interrupt(cd->irq, iact);
-
- return 0;
-}
diff --git a/arch/mn10300/kernel/csrc-mn10300.c b/arch/mn10300/kernel/csrc-mn10300.c
deleted file mode 100644
index 6b74df3661f2..000000000000
--- a/arch/mn10300/kernel/csrc-mn10300.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* MN10300 clocksource
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by Mark Salter (msalter@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/clocksource.h>
-#include <linux/init.h>
-#include <asm/timex.h>
-#include "internal.h"
-
-static u64 mn10300_read(struct clocksource *cs)
-{
- return read_timestamp_counter();
-}
-
-static struct clocksource clocksource_mn10300 = {
- .name = "TSC",
- .rating = 200,
- .read = mn10300_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-int __init init_clocksource(void)
-{
- startup_timestamp_counter();
- clocksource_register_hz(&clocksource_mn10300, MN10300_TSCCLK);
- return 0;
-}
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
deleted file mode 100644
index 177d61de51c9..000000000000
--- a/arch/mn10300/kernel/entry.S
+++ /dev/null
@@ -1,772 +0,0 @@
-###############################################################################
-#
-# MN10300 Exception and interrupt entry points
-#
-# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Modified by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/irqflags.h>
-#include <asm/thread_info.h>
-#include <asm/intctl-regs.h>
-#include <asm/busctl-regs.h>
-#include <asm/timer-regs.h>
-#include <unit/leds.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/errno.h>
-#include <asm/asm-offsets.h>
-#include <asm/frame.inc>
-
-#if defined(CONFIG_SMP) && defined(CONFIG_GDBSTUB)
-#include <asm/gdb-stub.h>
-#endif /* CONFIG_SMP && CONFIG_GDBSTUB */
-
-#ifdef CONFIG_PREEMPT
-#define preempt_stop LOCAL_IRQ_DISABLE
-#else
-#define preempt_stop
-#define resume_kernel restore_all
-#endif
-
- .am33_2
-
-###############################################################################
-#
-# the return path for a forked child
-# - on entry, D0 holds the address of the previous task to run
-#
-###############################################################################
-ENTRY(ret_from_fork)
- call schedule_tail[],0
- GET_THREAD_INFO a2
-
- # return 0 to indicate child process
- clr d0
- mov d0,(REG_D0,fp)
- jmp syscall_exit
-
-ENTRY(ret_from_kernel_thread)
- call schedule_tail[],0
- mov (REG_D0,fp),d0
- mov (REG_A0,fp),a0
- calls (a0)
- GET_THREAD_INFO a2 # A2 must be set on return from sys_exit()
- clr d0
- mov d0,(REG_D0,fp)
- jmp syscall_exit
-
-###############################################################################
-#
-# system call handler
-#
-###############################################################################
-ENTRY(system_call)
- add -4,sp
- SAVE_ALL
- mov d0,(REG_ORIG_D0,fp)
- GET_THREAD_INFO a2
- cmp nr_syscalls,d0
- bcc syscall_badsys
- btst _TIF_SYSCALL_TRACE,(TI_flags,a2)
- bne syscall_entry_trace
-syscall_call:
- add d0,d0,a1
- add a1,a1
- mov (REG_A0,fp),d0
- mov (sys_call_table,a1),a0
- calls (a0)
- mov d0,(REG_D0,fp)
-syscall_exit:
- # make sure we don't miss an interrupt setting need_resched or
- # sigpending between sampling and the rti
- LOCAL_IRQ_DISABLE
- mov (TI_flags,a2),d2
- btst _TIF_ALLWORK_MASK,d2
- bne syscall_exit_work
-restore_all:
- RESTORE_ALL
-
-###############################################################################
-#
-# perform work that needs to be done immediately before resumption and syscall
-# tracing
-#
-###############################################################################
- ALIGN
-syscall_exit_work:
- mov (REG_EPSW,fp),d0
- and EPSW_nSL,d0
- beq resume_kernel # returning to supervisor mode
-
- LOCAL_IRQ_ENABLE # could let syscall_trace_exit() call
- # schedule() instead
- btst _TIF_SYSCALL_TRACE,d2
- beq work_pending
- mov fp,d0
- call syscall_trace_exit[],0 # do_syscall_trace(regs)
- jmp resume_userspace
-
- ALIGN
-work_pending:
- btst _TIF_NEED_RESCHED,d2
- beq work_notifysig
-
-work_resched:
- call schedule[],0
-
-resume_userspace:
- # make sure we don't miss an interrupt setting need_resched or
- # sigpending between sampling and the rti
- LOCAL_IRQ_DISABLE
-
- # is there any work to be done other than syscall tracing?
- mov (TI_flags,a2),d2
- btst _TIF_WORK_MASK,d2
- beq restore_all
-
- LOCAL_IRQ_ENABLE
- btst _TIF_NEED_RESCHED,d2
- bne work_resched
-
- # deal with pending signals and notify-resume requests
-work_notifysig:
- mov fp,d0
- mov d2,d1
- call do_notify_resume[],0
- jmp resume_userspace
-
- # perform syscall entry tracing
-syscall_entry_trace:
- mov -ENOSYS,d0
- mov d0,(REG_D0,fp)
- mov fp,d0
- call syscall_trace_entry[],0 # returns the syscall number to actually use
- mov (REG_D1,fp),d1
- cmp nr_syscalls,d0
- bcs syscall_call
- jmp syscall_exit
-
-syscall_badsys:
- mov -ENOSYS,d0
- mov d0,(REG_D0,fp)
- jmp resume_userspace
-
- # userspace resumption stub bypassing syscall exit tracing
- .globl ret_from_exception, ret_from_intr
- ALIGN
-ret_from_exception:
- preempt_stop
-ret_from_intr:
- GET_THREAD_INFO a2
- mov (REG_EPSW,fp),d0 # need to deliver signals before
- # returning to userspace
- and EPSW_nSL,d0
- bne resume_userspace # returning to userspace
-
-#ifdef CONFIG_PREEMPT
-resume_kernel:
- LOCAL_IRQ_DISABLE
- mov (TI_preempt_count,a2),d0 # non-zero preempt_count ?
- cmp 0,d0
- bne restore_all
-
-need_resched:
- btst _TIF_NEED_RESCHED,(TI_flags,a2)
- beq restore_all
- mov (REG_EPSW,fp),d0
- and EPSW_IM,d0
- cmp EPSW_IM_7,d0 # interrupts off (exception path) ?
- bne restore_all
- call preempt_schedule_irq[],0
- jmp need_resched
-#else
- jmp resume_kernel
-#endif
-
-
-###############################################################################
-#
-# IRQ handler entry point
-# - intended to be entered at multiple priorities
-#
-###############################################################################
-ENTRY(irq_handler)
- add -4,sp
- SAVE_ALL
-
- # it's not a syscall
- mov 0xffffffff,d0
- mov d0,(REG_ORIG_D0,fp)
-
- mov fp,d0
- call do_IRQ[],0 # do_IRQ(regs)
-
- jmp ret_from_intr
-
-###############################################################################
-#
-# Double Fault handler entry point
-# - note that there will not be a stack, D0/A0 will hold EPSW/PC as were
-#
-###############################################################################
- .section .bss
- .balign THREAD_SIZE
- .space THREAD_SIZE
-__df_stack:
- .previous
-
-ENTRY(double_fault)
- mov a0,(__df_stack-4) # PC as was
- mov d0,(__df_stack-8) # EPSW as was
- mn10300_set_dbfleds # display 'db-f' on the LEDs
- mov 0xaa55aa55,d0
- mov d0,(__df_stack-12) # no ORIG_D0
- mov sp,a0 # save corrupted SP
- mov __df_stack-12,sp # emergency supervisor stack
- SAVE_ALL
- mov a0,(REG_A0,fp) # save corrupted SP as A0 (which got
- # clobbered by the CPU)
- mov fp,d0
- calls do_double_fault
-double_fault_loop:
- bra double_fault_loop
-
-###############################################################################
-#
-# Bus Error handler entry point
-# - handle external (async) bus errors separately
-#
-###############################################################################
-ENTRY(raw_bus_error)
- add -4,sp
- mov d0,(sp)
-#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR)
- mov (MMUCTR),d0
- mov d0,(MMUCTR)
-#endif
- mov (BCBERR),d0 # what
- btst BCBERR_BEMR_DMA,d0 # see if it was an external bus error
- beq __common_exception_aux # it wasn't
-
- SAVE_ALL
- mov (BCBEAR),d1 # destination of erroneous access
-
- mov (REG_ORIG_D0,fp),d2
- mov d2,(REG_D0,fp)
- mov -1,d2
- mov d2,(REG_ORIG_D0,fp)
-
- add -4,sp
- mov fp,(12,sp) # frame pointer
- call io_bus_error[],0
- jmp restore_all
-
-###############################################################################
-#
-# NMI exception entry points
-#
-# This is used by ordinary interrupt channels that have the GxICR_NMI bit set
-# in addition to the main NMI and Watchdog channels. SMP NMI IPIs use this
-# facility.
-#
-###############################################################################
-ENTRY(nmi_handler)
- add -4,sp
- mov d0,(sp)
- mov (TBR),d0
-
-#ifdef CONFIG_SMP
- add -4,sp
- mov d0,(sp) # save d0(TBR)
- movhu (NMIAGR),d0
- and NMIAGR_GN,d0
- lsr 0x2,d0
- cmp CALL_FUNCTION_NMI_IPI,d0
- bne nmi_not_smp_callfunc # if not call function, jump
-
- # function call nmi ipi
- add 4,sp # no need to store TBR
- mov GxICR_DETECT,d0 # clear NMI request
- movbu d0,(GxICR(CALL_FUNCTION_NMI_IPI))
- movhu (GxICR(CALL_FUNCTION_NMI_IPI)),d0
- and ~EPSW_NMID,epsw # enable NMI
-
- mov (sp),d0 # restore d0
- SAVE_ALL
- call smp_nmi_call_function_interrupt[],0
- RESTORE_ALL
-
-nmi_not_smp_callfunc:
-#ifdef CONFIG_KERNEL_DEBUGGER
- cmp DEBUGGER_NMI_IPI,d0
- bne nmi_not_debugger # if not kernel debugger NMI IPI, jump
-
- # kernel debugger NMI IPI
- add 4,sp # no need to store TBR
- mov GxICR_DETECT,d0 # clear NMI
- movbu d0,(GxICR(DEBUGGER_NMI_IPI))
- movhu (GxICR(DEBUGGER_NMI_IPI)),d0
- and ~EPSW_NMID,epsw # enable NMI
-
- mov (sp),d0
- SAVE_ALL
- mov fp,d0 # arg 0: stacked register file
- mov a2,d1 # arg 1: exception number
- call debugger_nmi_interrupt[],0
- RESTORE_ALL
-
-nmi_not_debugger:
-#endif /* CONFIG_KERNEL_DEBUGGER */
- mov (sp),d0 # restore TBR to d0
- add 4,sp
-#endif /* CONFIG_SMP */
-
- bra __common_exception_nonmi
-
-###############################################################################
-#
-# General exception entry point
-#
-###############################################################################
-ENTRY(__common_exception)
- add -4,sp
- mov d0,(sp)
-#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR)
- mov (MMUCTR),d0
- mov d0,(MMUCTR)
-#endif
-
-__common_exception_aux:
- mov (TBR),d0
- and ~EPSW_NMID,epsw # turn NMIs back on if not NMI
- or EPSW_IE,epsw
-
-__common_exception_nonmi:
- and 0x0000FFFF,d0 # turn the exception code into a vector
- # table index
-
- btst 0x00000007,d0
- bne 1f
- cmp 0x00000400,d0
- bge 1f
-
- SAVE_ALL # build the stack frame
-
- mov (REG_D0,fp),a2 # get the exception number
- mov (REG_ORIG_D0,fp),d0
- mov d0,(REG_D0,fp)
- mov -1,d0
- mov d0,(REG_ORIG_D0,fp)
-
-#ifdef CONFIG_GDBSTUB
-#ifdef CONFIG_SMP
- call gdbstub_busy_check[],0
- and d0,d0 # check return value
- beq 2f
-#else /* CONFIG_SMP */
- btst 0x01,(gdbstub_busy)
- beq 2f
-#endif /* CONFIG_SMP */
- and ~EPSW_IE,epsw
- mov fp,d0
- mov a2,d1
- call gdbstub_exception[],0 # gdbstub itself caused an exception
- bra restore_all
-2:
-#endif /* CONFIG_GDBSTUB */
-
- mov fp,d0 # arg 0: stacked register file
- mov a2,d1 # arg 1: exception number
- lsr 1,a2
-
- mov (exception_table,a2),a2
- calls (a2)
- jmp ret_from_exception
-
-1: pi # BUG() equivalent
-
-###############################################################################
-#
-# Exception handler functions table
-#
-###############################################################################
- .data
-ENTRY(exception_table)
- .rept 0x400>>1
- .long uninitialised_exception
- .endr
- .previous
-
-###############################################################################
-#
-# Change an entry in the exception table
-# - D0 exception code, D1 handler
-#
-###############################################################################
-ENTRY(set_excp_vector)
- lsr 1,d0
- add exception_table,d0
- mov d1,(d0)
- mov 4,d1
- ret [],0
-
-###############################################################################
-#
-# System call table
-#
-###############################################################################
- .data
-ENTRY(sys_call_table)
- .long sys_restart_syscall /* 0 */
- .long sys_exit
- .long sys_fork
- .long sys_read
- .long sys_write
- .long sys_open /* 5 */
- .long sys_close
- .long sys_waitpid
- .long sys_creat
- .long sys_link
- .long sys_unlink /* 10 */
- .long sys_execve
- .long sys_chdir
- .long sys_time
- .long sys_mknod
- .long sys_chmod /* 15 */
- .long sys_lchown16
- .long sys_ni_syscall /* old break syscall holder */
- .long sys_stat
- .long sys_lseek
- .long sys_getpid /* 20 */
- .long sys_mount
- .long sys_oldumount
- .long sys_setuid16
- .long sys_getuid16
- .long sys_stime /* 25 */
- .long sys_ptrace
- .long sys_alarm
- .long sys_fstat
- .long sys_pause
- .long sys_utime /* 30 */
- .long sys_ni_syscall /* old stty syscall holder */
- .long sys_ni_syscall /* old gtty syscall holder */
- .long sys_access
- .long sys_nice
- .long sys_ni_syscall /* 35 - old ftime syscall holder */
- .long sys_sync
- .long sys_kill
- .long sys_rename
- .long sys_mkdir
- .long sys_rmdir /* 40 */
- .long sys_dup
- .long sys_pipe
- .long sys_times
- .long sys_ni_syscall /* old prof syscall holder */
- .long sys_brk /* 45 */
- .long sys_setgid16
- .long sys_getgid16
- .long sys_signal
- .long sys_geteuid16
- .long sys_getegid16 /* 50 */
- .long sys_acct
- .long sys_umount /* recycled never used phys() */
- .long sys_ni_syscall /* old lock syscall holder */
- .long sys_ioctl
- .long sys_fcntl /* 55 */
- .long sys_ni_syscall /* old mpx syscall holder */
- .long sys_setpgid
- .long sys_ni_syscall /* old ulimit syscall holder */
- .long sys_ni_syscall /* old sys_olduname */
- .long sys_umask /* 60 */
- .long sys_chroot
- .long sys_ustat
- .long sys_dup2
- .long sys_getppid
- .long sys_getpgrp /* 65 */
- .long sys_setsid
- .long sys_sigaction
- .long sys_sgetmask
- .long sys_ssetmask
- .long sys_setreuid16 /* 70 */
- .long sys_setregid16
- .long sys_sigsuspend
- .long sys_sigpending
- .long sys_sethostname
- .long sys_setrlimit /* 75 */
- .long sys_old_getrlimit
- .long sys_getrusage
- .long sys_gettimeofday
- .long sys_settimeofday
- .long sys_getgroups16 /* 80 */
- .long sys_setgroups16
- .long sys_old_select
- .long sys_symlink
- .long sys_lstat
- .long sys_readlink /* 85 */
- .long sys_uselib
- .long sys_swapon
- .long sys_reboot
- .long sys_old_readdir
- .long old_mmap /* 90 */
- .long sys_munmap
- .long sys_truncate
- .long sys_ftruncate
- .long sys_fchmod
- .long sys_fchown16 /* 95 */
- .long sys_getpriority
- .long sys_setpriority
- .long sys_ni_syscall /* old profil syscall holder */
- .long sys_statfs
- .long sys_fstatfs /* 100 */
- .long sys_ni_syscall /* ioperm */
- .long sys_socketcall
- .long sys_syslog
- .long sys_setitimer
- .long sys_getitimer /* 105 */
- .long sys_newstat
- .long sys_newlstat
- .long sys_newfstat
- .long sys_ni_syscall /* old sys_uname */
- .long sys_ni_syscall /* 110 - iopl */
- .long sys_vhangup
- .long sys_ni_syscall /* old "idle" system call */
- .long sys_ni_syscall /* vm86old */
- .long sys_wait4
- .long sys_swapoff /* 115 */
- .long sys_sysinfo
- .long sys_ipc
- .long sys_fsync
- .long sys_sigreturn
- .long sys_clone /* 120 */
- .long sys_setdomainname
- .long sys_newuname
- .long sys_ni_syscall /* modify_ldt */
- .long sys_adjtimex
- .long sys_mprotect /* 125 */
- .long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
- .long sys_init_module
- .long sys_delete_module
- .long sys_ni_syscall /* 130: old "get_kernel_syms" */
- .long sys_quotactl
- .long sys_getpgid
- .long sys_fchdir
- .long sys_bdflush
- .long sys_sysfs /* 135 */
- .long sys_personality
- .long sys_ni_syscall /* reserved for afs_syscall */
- .long sys_setfsuid16
- .long sys_setfsgid16
- .long sys_llseek /* 140 */
- .long sys_getdents
- .long sys_select
- .long sys_flock
- .long sys_msync
- .long sys_readv /* 145 */
- .long sys_writev
- .long sys_getsid
- .long sys_fdatasync
- .long sys_sysctl
- .long sys_mlock /* 150 */
- .long sys_munlock
- .long sys_mlockall
- .long sys_munlockall
- .long sys_sched_setparam
- .long sys_sched_getparam /* 155 */
- .long sys_sched_setscheduler
- .long sys_sched_getscheduler
- .long sys_sched_yield
- .long sys_sched_get_priority_max
- .long sys_sched_get_priority_min /* 160 */
- .long sys_sched_rr_get_interval
- .long sys_nanosleep
- .long sys_mremap
- .long sys_setresuid16
- .long sys_getresuid16 /* 165 */
- .long sys_ni_syscall /* vm86 */
- .long sys_ni_syscall /* Old sys_query_module */
- .long sys_poll
- .long sys_ni_syscall /* was nfsservctl */
- .long sys_setresgid16 /* 170 */
- .long sys_getresgid16
- .long sys_prctl
- .long sys_rt_sigreturn
- .long sys_rt_sigaction
- .long sys_rt_sigprocmask /* 175 */
- .long sys_rt_sigpending
- .long sys_rt_sigtimedwait
- .long sys_rt_sigqueueinfo
- .long sys_rt_sigsuspend
- .long sys_pread64 /* 180 */
- .long sys_pwrite64
- .long sys_chown16
- .long sys_getcwd
- .long sys_capget
- .long sys_capset /* 185 */
- .long sys_sigaltstack
- .long sys_sendfile
- .long sys_ni_syscall /* reserved for streams1 */
- .long sys_ni_syscall /* reserved for streams2 */
- .long sys_vfork /* 190 */
- .long sys_getrlimit
- .long sys_mmap_pgoff
- .long sys_truncate64
- .long sys_ftruncate64
- .long sys_stat64 /* 195 */
- .long sys_lstat64
- .long sys_fstat64
- .long sys_lchown
- .long sys_getuid
- .long sys_getgid /* 200 */
- .long sys_geteuid
- .long sys_getegid
- .long sys_setreuid
- .long sys_setregid
- .long sys_getgroups /* 205 */
- .long sys_setgroups
- .long sys_fchown
- .long sys_setresuid
- .long sys_getresuid
- .long sys_setresgid /* 210 */
- .long sys_getresgid
- .long sys_chown
- .long sys_setuid
- .long sys_setgid
- .long sys_setfsuid /* 215 */
- .long sys_setfsgid
- .long sys_pivot_root
- .long sys_mincore
- .long sys_madvise
- .long sys_getdents64 /* 220 */
- .long sys_fcntl64
- .long sys_ni_syscall /* reserved for TUX */
- .long sys_ni_syscall
- .long sys_gettid
- .long sys_readahead /* 225 */
- .long sys_setxattr
- .long sys_lsetxattr
- .long sys_fsetxattr
- .long sys_getxattr
- .long sys_lgetxattr /* 230 */
- .long sys_fgetxattr
- .long sys_listxattr
- .long sys_llistxattr
- .long sys_flistxattr
- .long sys_removexattr /* 235 */
- .long sys_lremovexattr
- .long sys_fremovexattr
- .long sys_tkill
- .long sys_sendfile64
- .long sys_futex /* 240 */
- .long sys_sched_setaffinity
- .long sys_sched_getaffinity
- .long sys_ni_syscall /* sys_set_thread_area */
- .long sys_ni_syscall /* sys_get_thread_area */
- .long sys_io_setup /* 245 */
- .long sys_io_destroy
- .long sys_io_getevents
- .long sys_io_submit
- .long sys_io_cancel
- .long sys_fadvise64 /* 250 */
- .long sys_ni_syscall
- .long sys_exit_group
- .long sys_lookup_dcookie
- .long sys_epoll_create
- .long sys_epoll_ctl /* 255 */
- .long sys_epoll_wait
- .long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
- .long sys_statfs64
- .long sys_fstatfs64
- .long sys_tgkill /* 270 */
- .long sys_utimes
- .long sys_fadvise64_64
- .long sys_ni_syscall /* sys_vserver */
- .long sys_mbind
- .long sys_get_mempolicy /* 275 */
- .long sys_set_mempolicy
- .long sys_mq_open
- .long sys_mq_unlink
- .long sys_mq_timedsend
- .long sys_mq_timedreceive /* 280 */
- .long sys_mq_notify
- .long sys_mq_getsetattr
- .long sys_kexec_load
- .long sys_waitid
- .long sys_ni_syscall /* 285 */ /* available */
- .long sys_add_key
- .long sys_request_key
- .long sys_keyctl
- .long sys_cacheflush
- .long sys_ioprio_set /* 290 */
- .long sys_ioprio_get
- .long sys_inotify_init
- .long sys_inotify_add_watch
- .long sys_inotify_rm_watch
- .long sys_migrate_pages /* 295 */
- .long sys_openat
- .long sys_mkdirat
- .long sys_mknodat
- .long sys_fchownat
- .long sys_futimesat /* 300 */
- .long sys_fstatat64
- .long sys_unlinkat
- .long sys_renameat
- .long sys_linkat
- .long sys_symlinkat /* 305 */
- .long sys_readlinkat
- .long sys_fchmodat
- .long sys_faccessat
- .long sys_pselect6
- .long sys_ppoll /* 310 */
- .long sys_unshare
- .long sys_set_robust_list
- .long sys_get_robust_list
- .long sys_splice
- .long sys_sync_file_range /* 315 */
- .long sys_tee
- .long sys_vmsplice
- .long sys_move_pages
- .long sys_getcpu
- .long sys_epoll_pwait /* 320 */
- .long sys_utimensat
- .long sys_signalfd
- .long sys_timerfd_create
- .long sys_eventfd
- .long sys_fallocate /* 325 */
- .long sys_timerfd_settime
- .long sys_timerfd_gettime
- .long sys_signalfd4
- .long sys_eventfd2
- .long sys_epoll_create1 /* 330 */
- .long sys_dup3
- .long sys_pipe2
- .long sys_inotify_init1
- .long sys_preadv
- .long sys_pwritev /* 335 */
- .long sys_rt_tgsigqueueinfo
- .long sys_perf_event_open
- .long sys_recvmmsg
- .long sys_setns
-
-
-nr_syscalls=(.-sys_call_table)/4
diff --git a/arch/mn10300/kernel/fpu-low.S b/arch/mn10300/kernel/fpu-low.S
deleted file mode 100644
index 78df25cfae29..000000000000
--- a/arch/mn10300/kernel/fpu-low.S
+++ /dev/null
@@ -1,258 +0,0 @@
-/* MN10300 Low level FPU management operations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/linkage.h>
-#include <asm/cpu-regs.h>
-#include <asm/smp.h>
-#include <asm/thread_info.h>
-#include <asm/asm-offsets.h>
-#include <asm/frame.inc>
-
-.macro FPU_INIT_STATE_ALL
- fmov 0,fs0
- fmov fs0,fs1
- fmov fs0,fs2
- fmov fs0,fs3
- fmov fs0,fs4
- fmov fs0,fs5
- fmov fs0,fs6
- fmov fs0,fs7
- fmov fs0,fs8
- fmov fs0,fs9
- fmov fs0,fs10
- fmov fs0,fs11
- fmov fs0,fs12
- fmov fs0,fs13
- fmov fs0,fs14
- fmov fs0,fs15
- fmov fs0,fs16
- fmov fs0,fs17
- fmov fs0,fs18
- fmov fs0,fs19
- fmov fs0,fs20
- fmov fs0,fs21
- fmov fs0,fs22
- fmov fs0,fs23
- fmov fs0,fs24
- fmov fs0,fs25
- fmov fs0,fs26
- fmov fs0,fs27
- fmov fs0,fs28
- fmov fs0,fs29
- fmov fs0,fs30
- fmov fs0,fs31
- fmov FPCR_INIT,fpcr
-.endm
-
-.macro FPU_SAVE_ALL areg,dreg
- fmov fs0,(\areg+)
- fmov fs1,(\areg+)
- fmov fs2,(\areg+)
- fmov fs3,(\areg+)
- fmov fs4,(\areg+)
- fmov fs5,(\areg+)
- fmov fs6,(\areg+)
- fmov fs7,(\areg+)
- fmov fs8,(\areg+)
- fmov fs9,(\areg+)
- fmov fs10,(\areg+)
- fmov fs11,(\areg+)
- fmov fs12,(\areg+)
- fmov fs13,(\areg+)
- fmov fs14,(\areg+)
- fmov fs15,(\areg+)
- fmov fs16,(\areg+)
- fmov fs17,(\areg+)
- fmov fs18,(\areg+)
- fmov fs19,(\areg+)
- fmov fs20,(\areg+)
- fmov fs21,(\areg+)
- fmov fs22,(\areg+)
- fmov fs23,(\areg+)
- fmov fs24,(\areg+)
- fmov fs25,(\areg+)
- fmov fs26,(\areg+)
- fmov fs27,(\areg+)
- fmov fs28,(\areg+)
- fmov fs29,(\areg+)
- fmov fs30,(\areg+)
- fmov fs31,(\areg+)
- fmov fpcr,\dreg
- mov \dreg,(\areg)
-.endm
-
-.macro FPU_RESTORE_ALL areg,dreg
- fmov (\areg+),fs0
- fmov (\areg+),fs1
- fmov (\areg+),fs2
- fmov (\areg+),fs3
- fmov (\areg+),fs4
- fmov (\areg+),fs5
- fmov (\areg+),fs6
- fmov (\areg+),fs7
- fmov (\areg+),fs8
- fmov (\areg+),fs9
- fmov (\areg+),fs10
- fmov (\areg+),fs11
- fmov (\areg+),fs12
- fmov (\areg+),fs13
- fmov (\areg+),fs14
- fmov (\areg+),fs15
- fmov (\areg+),fs16
- fmov (\areg+),fs17
- fmov (\areg+),fs18
- fmov (\areg+),fs19
- fmov (\areg+),fs20
- fmov (\areg+),fs21
- fmov (\areg+),fs22
- fmov (\areg+),fs23
- fmov (\areg+),fs24
- fmov (\areg+),fs25
- fmov (\areg+),fs26
- fmov (\areg+),fs27
- fmov (\areg+),fs28
- fmov (\areg+),fs29
- fmov (\areg+),fs30
- fmov (\areg+),fs31
- mov (\areg),\dreg
- fmov \dreg,fpcr
-.endm
-
-###############################################################################
-#
-# void fpu_init_state(void)
-# - initialise the FPU
-#
-###############################################################################
- .globl fpu_init_state
- .type fpu_init_state,@function
-fpu_init_state:
- mov epsw,d0
- or EPSW_FE,epsw
-
-#ifdef CONFIG_MN10300_PROC_MN103E010
- nop
- nop
- nop
-#endif
- FPU_INIT_STATE_ALL
-#ifdef CONFIG_MN10300_PROC_MN103E010
- nop
- nop
- nop
-#endif
- mov d0,epsw
- ret [],0
-
- .size fpu_init_state,.-fpu_init_state
-
-###############################################################################
-#
-# void fpu_save(struct fpu_state_struct *)
-# - save the fpu state
-# - note that an FPU Operational exception might occur during this process
-#
-###############################################################################
- .globl fpu_save
- .type fpu_save,@function
-fpu_save:
- mov epsw,d1
- or EPSW_FE,epsw /* enable the FPU so we can access it */
-
-#ifdef CONFIG_MN10300_PROC_MN103E010
- nop
- nop
-#endif
- mov d0,a0
- FPU_SAVE_ALL a0,d0
-#ifdef CONFIG_MN10300_PROC_MN103E010
- nop
- nop
-#endif
-
- mov d1,epsw
- ret [],0
-
- .size fpu_save,.-fpu_save
-
-###############################################################################
-#
-# void fpu_disabled(void)
-# - handle an exception due to the FPU being disabled
-# when CONFIG_FPU is enabled
-#
-###############################################################################
- .type fpu_disabled,@function
- .globl fpu_disabled
-fpu_disabled:
- or EPSW_nAR|EPSW_FE,epsw
- nop
- nop
- nop
-
- mov sp,a1
- mov (a1),d1 /* get epsw of user context */
- and ~(THREAD_SIZE-1),a1 /* a1: (thread_info *ti) */
- mov (TI_task,a1),a2 /* a2: (task_struct *tsk) */
- btst EPSW_nSL,d1
- beq fpu_used_in_kernel
-
- or EPSW_FE,d1
- mov d1,(sp)
- mov (TASK_THREAD+THREAD_FPU_FLAGS,a2),d1
-#ifndef CONFIG_LAZY_SAVE_FPU
- or __THREAD_HAS_FPU,d1
- mov d1,(TASK_THREAD+THREAD_FPU_FLAGS,a2)
-#else /* !CONFIG_LAZY_SAVE_FPU */
- mov (fpu_state_owner),a0
- cmp 0,a0
- beq fpu_regs_save_end
-
- mov (TASK_THREAD+THREAD_UREGS,a0),a1
- add TASK_THREAD+THREAD_FPU_STATE,a0
- FPU_SAVE_ALL a0,d0
-
- mov (REG_EPSW,a1),d0
- and ~EPSW_FE,d0
- mov d0,(REG_EPSW,a1)
-
-fpu_regs_save_end:
- mov a2,(fpu_state_owner)
-#endif /* !CONFIG_LAZY_SAVE_FPU */
-
- btst __THREAD_USING_FPU,d1
- beq fpu_regs_init
- add TASK_THREAD+THREAD_FPU_STATE,a2
- FPU_RESTORE_ALL a2,d0
- rti
-
-fpu_regs_init:
- FPU_INIT_STATE_ALL
- add TASK_THREAD+THREAD_FPU_FLAGS,a2
- bset __THREAD_USING_FPU,(0,a2)
- rti
-
-fpu_used_in_kernel:
- and ~(EPSW_nAR|EPSW_FE),epsw
- nop
- nop
-
- add -4,sp
- SAVE_ALL
- mov -1,d0
- mov d0,(REG_ORIG_D0,fp)
-
- and ~EPSW_NMID,epsw
-
- mov fp,d0
- call fpu_disabled_in_kernel[],0
- jmp ret_from_exception
-
- .size fpu_disabled,.-fpu_disabled
diff --git a/arch/mn10300/kernel/fpu-nofpu-low.S b/arch/mn10300/kernel/fpu-nofpu-low.S
deleted file mode 100644
index 7ea087a549f4..000000000000
--- a/arch/mn10300/kernel/fpu-nofpu-low.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/* MN10300 Low level FPU management operations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/linkage.h>
-#include <asm/cpu-regs.h>
-#include <asm/smp.h>
-#include <asm/thread_info.h>
-#include <asm/asm-offsets.h>
-#include <asm/frame.inc>
-
-###############################################################################
-#
-# void fpu_disabled(void)
-# - handle an exception due to the FPU being disabled
-# when CONFIG_FPU is disabled
-#
-###############################################################################
- .type fpu_disabled,@function
- .globl fpu_disabled
-fpu_disabled:
- add -4,sp
- SAVE_ALL
- mov -1,d0
- mov d0,(REG_ORIG_D0,fp)
-
- and ~EPSW_NMID,epsw
-
- mov fp,d0
- call unexpected_fpu_exception[],0
- jmp ret_from_exception
-
- .size fpu_disabled,.-fpu_disabled
diff --git a/arch/mn10300/kernel/fpu-nofpu.c b/arch/mn10300/kernel/fpu-nofpu.c
deleted file mode 100644
index 8d0e041aa798..000000000000
--- a/arch/mn10300/kernel/fpu-nofpu.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* MN10300 FPU management
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm/fpu.h>
-#include <asm/elf.h>
-
-/*
- * handle an FPU operational exception
- * - there's a possibility that if the FPU is asynchronous, the signal might
- * be meant for a process other than the current one
- */
-asmlinkage
-void unexpected_fpu_exception(struct pt_regs *regs, enum exception_code code)
-{
- panic("An FPU exception was received, but there's no FPU enabled.");
-}
-
-/*
- * fill in the FPU structure for a core dump
- */
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpreg)
-{
- return 0; /* not valid */
-}
diff --git a/arch/mn10300/kernel/fpu.c b/arch/mn10300/kernel/fpu.c
deleted file mode 100644
index 50ce7b447fed..000000000000
--- a/arch/mn10300/kernel/fpu.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* MN10300 FPU management
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/uaccess.h>
-#include <linux/sched/signal.h>
-
-#include <asm/fpu.h>
-#include <asm/elf.h>
-#include <asm/exceptions.h>
-
-#ifdef CONFIG_LAZY_SAVE_FPU
-struct task_struct *fpu_state_owner;
-#endif
-
-/*
- * error functions in FPU disabled exception
- */
-asmlinkage void fpu_disabled_in_kernel(struct pt_regs *regs)
-{
- die_if_no_fixup("An FPU Disabled exception happened in kernel space\n",
- regs, EXCEP_FPU_DISABLED);
-}
-
-/*
- * handle an FPU operational exception
- * - there's a possibility that if the FPU is asynchronous, the signal might
- * be meant for a process other than the current one
- */
-asmlinkage void fpu_exception(struct pt_regs *regs, enum exception_code code)
-{
- struct task_struct *tsk = current;
- siginfo_t info;
- u32 fpcr;
-
- if (!user_mode(regs))
- die_if_no_fixup("An FPU Operation exception happened in"
- " kernel space\n",
- regs, code);
-
- if (!is_using_fpu(tsk))
- die_if_no_fixup("An FPU Operation exception happened,"
- " but the FPU is not in use",
- regs, code);
-
- info.si_signo = SIGFPE;
- info.si_errno = 0;
- info.si_addr = (void *) tsk->thread.uregs->pc;
- info.si_code = FPE_FLTINV;
-
- unlazy_fpu(tsk);
-
- fpcr = tsk->thread.fpu_state.fpcr;
-
- if (fpcr & FPCR_EC_Z)
- info.si_code = FPE_FLTDIV;
- else if (fpcr & FPCR_EC_O)
- info.si_code = FPE_FLTOVF;
- else if (fpcr & FPCR_EC_U)
- info.si_code = FPE_FLTUND;
- else if (fpcr & FPCR_EC_I)
- info.si_code = FPE_FLTRES;
-
- force_sig_info(SIGFPE, &info, tsk);
-}
-
-/*
- * save the FPU state to a signal context
- */
-int fpu_setup_sigcontext(struct fpucontext *fpucontext)
-{
- struct task_struct *tsk = current;
-
- if (!is_using_fpu(tsk))
- return 0;
-
- /* transfer the current FPU state to memory and cause fpu_init() to be
- * triggered by the next attempted FPU operation by the current
- * process.
- */
- preempt_disable();
-
-#ifndef CONFIG_LAZY_SAVE_FPU
- if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
- fpu_save(&tsk->thread.fpu_state);
- tsk->thread.uregs->epsw &= ~EPSW_FE;
- tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
- }
-#else /* !CONFIG_LAZY_SAVE_FPU */
- if (fpu_state_owner == tsk) {
- fpu_save(&tsk->thread.fpu_state);
- fpu_state_owner->thread.uregs->epsw &= ~EPSW_FE;
- fpu_state_owner = NULL;
- }
-#endif /* !CONFIG_LAZY_SAVE_FPU */
-
- preempt_enable();
-
- /* we no longer have a valid current FPU state */
- clear_using_fpu(tsk);
-
- /* transfer the saved FPU state onto the userspace stack */
- if (copy_to_user(fpucontext,
- &tsk->thread.fpu_state,
- min(sizeof(struct fpu_state_struct),
- sizeof(struct fpucontext))))
- return -1;
-
- return 1;
-}
-
-/*
- * kill a process's FPU state during restoration after signal handling
- */
-void fpu_kill_state(struct task_struct *tsk)
-{
- /* disown anything left in the FPU */
- preempt_disable();
-
-#ifndef CONFIG_LAZY_SAVE_FPU
- if (tsk->thread.fpu_flags & THREAD_HAS_FPU) {
- tsk->thread.uregs->epsw &= ~EPSW_FE;
- tsk->thread.fpu_flags &= ~THREAD_HAS_FPU;
- }
-#else /* !CONFIG_LAZY_SAVE_FPU */
- if (fpu_state_owner == tsk) {
- fpu_state_owner->thread.uregs->epsw &= ~EPSW_FE;
- fpu_state_owner = NULL;
- }
-#endif /* !CONFIG_LAZY_SAVE_FPU */
-
- preempt_enable();
-
- /* we no longer have a valid current FPU state */
- clear_using_fpu(tsk);
-}
-
-/*
- * restore the FPU state from a signal context
- */
-int fpu_restore_sigcontext(struct fpucontext *fpucontext)
-{
- struct task_struct *tsk = current;
- int ret;
-
- /* load up the old FPU state */
- ret = copy_from_user(&tsk->thread.fpu_state, fpucontext,
- min(sizeof(struct fpu_state_struct),
- sizeof(struct fpucontext)));
- if (!ret)
- set_using_fpu(tsk);
-
- return ret;
-}
-
-/*
- * fill in the FPU structure for a core dump
- */
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpreg)
-{
- struct task_struct *tsk = current;
- int fpvalid;
-
- fpvalid = is_using_fpu(tsk);
- if (fpvalid) {
- unlazy_fpu(tsk);
- memcpy(fpreg, &tsk->thread.fpu_state, sizeof(*fpreg));
- }
-
- return fpvalid;
-}
diff --git a/arch/mn10300/kernel/gdb-io-serial-low.S b/arch/mn10300/kernel/gdb-io-serial-low.S
deleted file mode 100644
index b1d0152e96cb..000000000000
--- a/arch/mn10300/kernel/gdb-io-serial-low.S
+++ /dev/null
@@ -1,91 +0,0 @@
-###############################################################################
-#
-# 16550 serial Rx interrupt handler for gdbstub I/O
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/cpu-regs.h>
-#include <asm/thread_info.h>
-#include <asm/frame.inc>
-#include <asm/intctl-regs.h>
-#include <asm/irqflags.h>
-#include <unit/serial.h>
-
- .text
-
-###############################################################################
-#
-# GDB stub serial receive interrupt entry point
-# - intended to run at interrupt priority 0
-#
-###############################################################################
- .globl gdbstub_io_rx_handler
- .type gdbstub_io_rx_handler,@function
-gdbstub_io_rx_handler:
- movm [d2,d3,a2,a3],(sp)
-
-#if 1
- movbu (GDBPORT_SERIAL_IIR),d2
-#endif
-
- mov (gdbstub_rx_inp),a3
-gdbstub_io_rx_more:
- mov a3,a2
- add 2,a3
- and 0x00000fff,a3
- mov (gdbstub_rx_outp),d3
- cmp a3,d3
- beq gdbstub_io_rx_overflow
-
- movbu (GDBPORT_SERIAL_LSR),d3
- btst UART_LSR_DR,d3
- beq gdbstub_io_rx_done
- movbu (GDBPORT_SERIAL_RX),d2
- movbu d3,(gdbstub_rx_buffer+1,a2)
- movbu d2,(gdbstub_rx_buffer,a2)
- mov a3,(gdbstub_rx_inp)
- bra gdbstub_io_rx_more
-
-gdbstub_io_rx_done:
- mov GxICR_DETECT,d2
- movbu d2,(XIRQxICR(GDBPORT_SERIAL_IRQ)) # ACK the interrupt
- movhu (XIRQxICR(GDBPORT_SERIAL_IRQ)),d2 # flush
- movm (sp),[d2,d3,a2,a3]
- bset 0x01,(gdbstub_busy)
- beq gdbstub_io_rx_enter
- rti
-
-gdbstub_io_rx_overflow:
- bset 0x01,(gdbstub_rx_overflow)
- bra gdbstub_io_rx_done
-
-gdbstub_io_rx_enter:
- LOCAL_CHANGE_INTR_MASK_LEVEL(NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL+1))
- add -4,sp
- SAVE_ALL
-
- mov 0xffffffff,d0
- mov d0,(REG_ORIG_D0,fp)
- mov 0x280,d1
-
- mov fp,d0
- call gdbstub_rx_irq[],0 # gdbstub_rx_irq(regs,excep)
-
- LOCAL_CLI
- bclr 0x01,(gdbstub_busy)
-
- .globl gdbstub_return
-gdbstub_return:
- RESTORE_ALL
-
- .size gdbstub_io_rx_handler,.-gdbstub_io_rx_handler
diff --git a/arch/mn10300/kernel/gdb-io-serial.c b/arch/mn10300/kernel/gdb-io-serial.c
deleted file mode 100644
index df51242744cc..000000000000
--- a/arch/mn10300/kernel/gdb-io-serial.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* 16550 serial driver for gdbstub I/O
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/nmi.h>
-
-#include <asm/pgtable.h>
-#include <asm/gdb-stub.h>
-#include <asm/exceptions.h>
-#include <asm/serial-regs.h>
-#include <unit/serial.h>
-#include <asm/smp.h>
-
-/*
- * initialise the GDB stub
- */
-void gdbstub_io_init(void)
-{
- u16 tmp;
-
- /* set up the serial port */
- GDBPORT_SERIAL_LCR = UART_LCR_WLEN8; /* 1N8 */
- GDBPORT_SERIAL_FCR = (UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
- UART_FCR_CLEAR_XMIT);
-
- FLOWCTL_CLEAR(DTR);
- FLOWCTL_SET(RTS);
-
- gdbstub_io_set_baud(115200);
-
- /* we want to get serial receive interrupts */
- XIRQxICR(GDBPORT_SERIAL_IRQ) = 0;
- tmp = XIRQxICR(GDBPORT_SERIAL_IRQ);
-
-#if CONFIG_GDBSTUB_IRQ_LEVEL == 0
- IVAR0 = EXCEP_IRQ_LEVEL0;
-#elif CONFIG_GDBSTUB_IRQ_LEVEL == 1
- IVAR1 = EXCEP_IRQ_LEVEL1;
-#elif CONFIG_GDBSTUB_IRQ_LEVEL == 2
- IVAR2 = EXCEP_IRQ_LEVEL2;
-#elif CONFIG_GDBSTUB_IRQ_LEVEL == 3
- IVAR3 = EXCEP_IRQ_LEVEL3;
-#elif CONFIG_GDBSTUB_IRQ_LEVEL == 4
- IVAR4 = EXCEP_IRQ_LEVEL4;
-#elif CONFIG_GDBSTUB_IRQ_LEVEL == 5
- IVAR5 = EXCEP_IRQ_LEVEL5;
-#else
-#error "Unknown irq level for gdbstub."
-#endif
-
- set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL),
- gdbstub_io_rx_handler);
-
- XIRQxICR(GDBPORT_SERIAL_IRQ) &= ~GxICR_REQUEST;
- XIRQxICR(GDBPORT_SERIAL_IRQ) =
- GxICR_ENABLE | NUM2GxICR_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL);
- tmp = XIRQxICR(GDBPORT_SERIAL_IRQ);
-
- GDBPORT_SERIAL_IER = UART_IER_RDI | UART_IER_RLSI;
-
- /* permit level 0 IRQs to take place */
- arch_local_change_intr_mask_level(
- NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
-}
-
-/*
- * set up the GDB stub serial port baud rate timers
- */
-void gdbstub_io_set_baud(unsigned baud)
-{
- unsigned value;
- u8 lcr;
-
- value = 18432000 / 16 / baud;
-
- lcr = GDBPORT_SERIAL_LCR;
- GDBPORT_SERIAL_LCR |= UART_LCR_DLAB;
- GDBPORT_SERIAL_DLL = value & 0xff;
- GDBPORT_SERIAL_DLM = (value >> 8) & 0xff;
- GDBPORT_SERIAL_LCR = lcr;
-}
-
-/*
- * wait for a character to come from the debugger
- */
-int gdbstub_io_rx_char(unsigned char *_ch, int nonblock)
-{
- unsigned ix;
- u8 ch, st;
-#if defined(CONFIG_MN10300_WD_TIMER)
- int cpu;
-#endif
-
- *_ch = 0xff;
-
- if (gdbstub_rx_unget) {
- *_ch = gdbstub_rx_unget;
- gdbstub_rx_unget = 0;
- return 0;
- }
-
- try_again:
- /* pull chars out of the buffer */
- ix = gdbstub_rx_outp;
- barrier();
- if (ix == gdbstub_rx_inp) {
- if (nonblock)
- return -EAGAIN;
-#ifdef CONFIG_MN10300_WD_TIMER
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- watchdog_alert_counter[cpu] = 0;
-#endif
- goto try_again;
- }
-
- ch = gdbstub_rx_buffer[ix++];
- st = gdbstub_rx_buffer[ix++];
- barrier();
- gdbstub_rx_outp = ix & 0x00000fff;
-
- if (st & UART_LSR_BI) {
- gdbstub_proto("### GDB Rx Break Detected ###\n");
- return -EINTR;
- } else if (st & (UART_LSR_FE | UART_LSR_OE | UART_LSR_PE)) {
- gdbstub_proto("### GDB Rx Error (st=%02x) ###\n", st);
- return -EIO;
- } else {
- gdbstub_proto("### GDB Rx %02x (st=%02x) ###\n", ch, st);
- *_ch = ch & 0x7f;
- return 0;
- }
-}
-
-/*
- * send a character to the debugger
- */
-void gdbstub_io_tx_char(unsigned char ch)
-{
- FLOWCTL_SET(DTR);
- LSR_WAIT_FOR(THRE);
- /* FLOWCTL_WAIT_FOR(CTS); */
-
- if (ch == 0x0a) {
- GDBPORT_SERIAL_TX = 0x0d;
- LSR_WAIT_FOR(THRE);
- /* FLOWCTL_WAIT_FOR(CTS); */
- }
- GDBPORT_SERIAL_TX = ch;
-
- FLOWCTL_CLEAR(DTR);
-}
-
-/*
- * send a character to the debugger
- */
-void gdbstub_io_tx_flush(void)
-{
- LSR_WAIT_FOR(TEMT);
- LSR_WAIT_FOR(THRE);
- FLOWCTL_CLEAR(DTR);
-}
diff --git a/arch/mn10300/kernel/gdb-io-ttysm-low.S b/arch/mn10300/kernel/gdb-io-ttysm-low.S
deleted file mode 100644
index 060b7cca735d..000000000000
--- a/arch/mn10300/kernel/gdb-io-ttysm-low.S
+++ /dev/null
@@ -1,93 +0,0 @@
-###############################################################################
-#
-# MN10300 On-chip serial Rx interrupt handler for GDB stub I/O
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/thread_info.h>
-#include <asm/cpu-regs.h>
-#include <asm/frame.inc>
-#include <asm/intctl-regs.h>
-#include <unit/serial.h>
-#include "mn10300-serial.h"
-
- .text
-
-###############################################################################
-#
-# GDB stub serial receive interrupt entry point
-# - intended to run at interrupt priority 0
-#
-###############################################################################
- .globl gdbstub_io_rx_handler
- .type gdbstub_io_rx_handler,@function
-gdbstub_io_rx_handler:
- movm [d2,d3,a2,a3],(sp)
-
- mov (gdbstub_rx_inp),a3
-gdbstub_io_rx_more:
- mov a3,a2
- add 2,a3
- and PAGE_SIZE_asm-1,a3
- mov (gdbstub_rx_outp),d3
- cmp a3,d3
- beq gdbstub_io_rx_overflow
-
- movbu (SCgSTR),d3
- btst SC01STR_RBF,d3
- beq gdbstub_io_rx_done
- movbu (SCgRXB),d2
- movbu d3,(gdbstub_rx_buffer+1,a2)
- movbu d2,(gdbstub_rx_buffer,a2)
- mov a3,(gdbstub_rx_inp)
- bra gdbstub_io_rx_more
-
-gdbstub_io_rx_done:
- mov GxICR_DETECT,d2
- movbu d2,(GxICR(SCgRXIRQ)) # ACK the interrupt
- movhu (GxICR(SCgRXIRQ)),d2 # flush
-
- movm (sp),[d2,d3,a2,a3]
- bset 0x01,(gdbstub_busy)
- beq gdbstub_io_rx_enter
- rti
-
-gdbstub_io_rx_overflow:
- bset 0x01,(gdbstub_rx_overflow)
- bra gdbstub_io_rx_done
-
-###############################################################################
-#
-# debugging interrupt - enter the GDB stub proper
-#
-###############################################################################
-gdbstub_io_rx_enter:
- or EPSW_IE|EPSW_IM_1,epsw
- add -4,sp
- SAVE_ALL
-
- mov 0xffffffff,d0
- mov d0,(REG_ORIG_D0,fp)
- mov 0x280,d1
-
- mov fp,d0
- call gdbstub_rx_irq[],0 # gdbstub_io_rx_irq(regs,excep)
-
- and ~EPSW_IE,epsw
- bclr 0x01,(gdbstub_busy)
-
- .globl gdbstub_return
-gdbstub_return:
- RESTORE_ALL
-
- .size gdbstub_io_rx_handler,.-gdbstub_io_rx_handler
diff --git a/arch/mn10300/kernel/gdb-io-ttysm.c b/arch/mn10300/kernel/gdb-io-ttysm.c
deleted file mode 100644
index caae8cac9db1..000000000000
--- a/arch/mn10300/kernel/gdb-io-ttysm.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/* MN10300 On-chip serial driver for gdbstub I/O
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/tty.h>
-#include <asm/pgtable.h>
-#include <asm/gdb-stub.h>
-#include <asm/exceptions.h>
-#include <unit/clock.h>
-#include "mn10300-serial.h"
-
-#if defined(CONFIG_GDBSTUB_ON_TTYSM0)
-struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif0;
-#elif defined(CONFIG_GDBSTUB_ON_TTYSM1)
-struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif1;
-#else
-struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif2;
-#endif
-
-
-/*
- * initialise the GDB stub I/O routines
- */
-void __init gdbstub_io_init(void)
-{
- uint16_t scxctr;
- int tmp;
-
- switch (gdbstub_port->clock_src) {
- case MNSCx_CLOCK_SRC_IOCLK:
- gdbstub_port->ioclk = MN10300_IOCLK;
- break;
-
-#ifdef MN10300_IOBCLK
- case MNSCx_CLOCK_SRC_IOBCLK:
- gdbstub_port->ioclk = MN10300_IOBCLK;
- break;
-#endif
- default:
- BUG();
- }
-
- /* set up the serial port */
- gdbstub_io_set_baud(115200);
-
- /* we want to get serial receive interrupts */
- set_intr_level(gdbstub_port->rx_irq,
- NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
- set_intr_level(gdbstub_port->tx_irq,
- NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
- set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL),
- gdbstub_io_rx_handler);
-
- *gdbstub_port->rx_icr |= GxICR_ENABLE;
- tmp = *gdbstub_port->rx_icr;
-
- /* enable the device */
- scxctr = SC01CTR_CLN_8BIT; /* 1N8 */
- switch (gdbstub_port->div_timer) {
- case MNSCx_DIV_TIMER_16BIT:
- scxctr |= SC0CTR_CK_TM8UFLOW_8; /* == SC1CTR_CK_TM9UFLOW_8
- == SC2CTR_CK_TM10UFLOW_8 */
- break;
-
- case MNSCx_DIV_TIMER_8BIT:
- scxctr |= SC0CTR_CK_TM2UFLOW_8;
- break;
- }
-
- scxctr |= SC01CTR_TXE | SC01CTR_RXE;
-
- *gdbstub_port->_control = scxctr;
- tmp = *gdbstub_port->_control;
-
- /* permit level 0 IRQs only */
- arch_local_change_intr_mask_level(
- NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1));
-}
-
-/*
- * set up the GDB stub serial port baud rate timers
- */
-void gdbstub_io_set_baud(unsigned baud)
-{
- const unsigned bits = 10; /* 1 [start] + 8 [data] + 0 [parity] +
- * 1 [stop] */
- unsigned long ioclk = gdbstub_port->ioclk;
- unsigned xdiv, tmp;
- uint16_t tmxbr;
- uint8_t tmxmd;
-
- if (!baud) {
- baud = 9600;
- } else if (baud == 134) {
- baud = 269; /* 134 is really 134.5 */
- xdiv = 2;
- }
-
-try_alternative:
- xdiv = 1;
-
- switch (gdbstub_port->div_timer) {
- case MNSCx_DIV_TIMER_16BIT:
- tmxmd = TM8MD_SRC_IOCLK;
- tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 65535)
- goto timer_okay;
-
- tmxmd = TM8MD_SRC_IOCLK_8;
- tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 65535)
- goto timer_okay;
-
- tmxmd = TM8MD_SRC_IOCLK_32;
- tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 65535)
- goto timer_okay;
-
- break;
-
- case MNSCx_DIV_TIMER_8BIT:
- tmxmd = TM2MD_SRC_IOCLK;
- tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 255)
- goto timer_okay;
-
- tmxmd = TM2MD_SRC_IOCLK_8;
- tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 255)
- goto timer_okay;
-
- tmxmd = TM2MD_SRC_IOCLK_32;
- tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 255)
- goto timer_okay;
- break;
- }
-
- /* as a last resort, if the quotient is zero, default to 9600 bps */
- baud = 9600;
- goto try_alternative;
-
-timer_okay:
- gdbstub_port->uart.timeout = (2 * bits * HZ) / baud;
- gdbstub_port->uart.timeout += HZ / 50;
-
- /* set the timer to produce the required baud rate */
- switch (gdbstub_port->div_timer) {
- case MNSCx_DIV_TIMER_16BIT:
- *gdbstub_port->_tmxmd = 0;
- *gdbstub_port->_tmxbr = tmxbr;
- *gdbstub_port->_tmxmd = TM8MD_INIT_COUNTER;
- *gdbstub_port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
- break;
-
- case MNSCx_DIV_TIMER_8BIT:
- *gdbstub_port->_tmxmd = 0;
- *(volatile u8 *) gdbstub_port->_tmxbr = (u8)tmxbr;
- *gdbstub_port->_tmxmd = TM2MD_INIT_COUNTER;
- *gdbstub_port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
- break;
- }
-}
-
-/*
- * wait for a character to come from the debugger
- */
-int gdbstub_io_rx_char(unsigned char *_ch, int nonblock)
-{
- unsigned ix;
- u8 ch, st;
-#if defined(CONFIG_MN10300_WD_TIMER)
- int cpu;
-#endif
-
- *_ch = 0xff;
-
- if (gdbstub_rx_unget) {
- *_ch = gdbstub_rx_unget;
- gdbstub_rx_unget = 0;
- return 0;
- }
-
-try_again:
- /* pull chars out of the buffer */
- ix = gdbstub_rx_outp;
- barrier();
- if (ix == gdbstub_rx_inp) {
- if (nonblock)
- return -EAGAIN;
-#ifdef CONFIG_MN10300_WD_TIMER
- for (cpu = 0; cpu < NR_CPUS; cpu++)
- watchdog_alert_counter[cpu] = 0;
-#endif
- goto try_again;
- }
-
- ch = gdbstub_rx_buffer[ix++];
- st = gdbstub_rx_buffer[ix++];
- barrier();
- gdbstub_rx_outp = ix & (PAGE_SIZE - 1);
-
- st &= SC01STR_RXF | SC01STR_RBF | SC01STR_FEF | SC01STR_PEF |
- SC01STR_OEF;
-
- /* deal with what we've got
- * - note that the UART doesn't do BREAK-detection for us
- */
- if (st & SC01STR_FEF && ch == 0) {
- switch (gdbstub_port->rx_brk) {
- case 0: gdbstub_port->rx_brk = 1; goto try_again;
- case 1: gdbstub_port->rx_brk = 2; goto try_again;
- case 2:
- gdbstub_port->rx_brk = 3;
- gdbstub_proto("### GDB MNSERIAL Rx Break Detected"
- " ###\n");
- return -EINTR;
- default:
- goto try_again;
- }
- } else if (st & SC01STR_FEF) {
- if (gdbstub_port->rx_brk)
- goto try_again;
-
- gdbstub_proto("### GDB MNSERIAL Framing Error ###\n");
- return -EIO;
- } else if (st & SC01STR_OEF) {
- if (gdbstub_port->rx_brk)
- goto try_again;
-
- gdbstub_proto("### GDB MNSERIAL Overrun Error ###\n");
- return -EIO;
- } else if (st & SC01STR_PEF) {
- if (gdbstub_port->rx_brk)
- goto try_again;
-
- gdbstub_proto("### GDB MNSERIAL Parity Error ###\n");
- return -EIO;
- } else {
- /* look for the tail-end char on a break run */
- if (gdbstub_port->rx_brk == 3) {
- switch (ch) {
- case 0xFF:
- case 0xFE:
- case 0xFC:
- case 0xF8:
- case 0xF0:
- case 0xE0:
- case 0xC0:
- case 0x80:
- case 0x00:
- gdbstub_port->rx_brk = 0;
- goto try_again;
- default:
- break;
- }
- }
-
- gdbstub_port->rx_brk = 0;
- gdbstub_io("### GDB Rx %02x (st=%02x) ###\n", ch, st);
- *_ch = ch & 0x7f;
- return 0;
- }
-}
-
-/*
- * send a character to the debugger
- */
-void gdbstub_io_tx_char(unsigned char ch)
-{
- while (*gdbstub_port->_status & SC01STR_TBF)
- continue;
-
- if (ch == 0x0a) {
- *(u8 *) gdbstub_port->_txb = 0x0d;
- while (*gdbstub_port->_status & SC01STR_TBF)
- continue;
- }
-
- *(u8 *) gdbstub_port->_txb = ch;
-}
-
-/*
- * flush the transmission buffers
- */
-void gdbstub_io_tx_flush(void)
-{
- while (*gdbstub_port->_status & (SC01STR_TBF | SC01STR_TXF))
- continue;
-}
diff --git a/arch/mn10300/kernel/gdb-low.S b/arch/mn10300/kernel/gdb-low.S
deleted file mode 100644
index e2725552cd82..000000000000
--- a/arch/mn10300/kernel/gdb-low.S
+++ /dev/null
@@ -1,115 +0,0 @@
-###############################################################################
-#
-# MN10300 Low-level gdbstub routines
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/cache.h>
-#include <asm/cpu-regs.h>
-#include <asm/exceptions.h>
-#include <asm/frame.inc>
-#include <asm/serial-regs.h>
-
- .text
-
-###############################################################################
-#
-# GDB stub read memory with guard
-# - D0 holds the memory address to read
-# - D1 holds the address to store the byte into
-#
-###############################################################################
- .globl gdbstub_read_byte_guard
- .globl gdbstub_read_byte_cont
-ENTRY(gdbstub_read_byte)
- mov d0,a0
- mov d1,a1
- clr d0
-gdbstub_read_byte_guard:
- movbu (a0),d1
-gdbstub_read_byte_cont:
- movbu d1,(a1)
- ret [],0
-
- .globl gdbstub_read_word_guard
- .globl gdbstub_read_word_cont
-ENTRY(gdbstub_read_word)
- mov d0,a0
- mov d1,a1
- clr d0
-gdbstub_read_word_guard:
- movhu (a0),d1
-gdbstub_read_word_cont:
- movhu d1,(a1)
- ret [],0
-
- .globl gdbstub_read_dword_guard
- .globl gdbstub_read_dword_cont
-ENTRY(gdbstub_read_dword)
- mov d0,a0
- mov d1,a1
- clr d0
-gdbstub_read_dword_guard:
- mov (a0),d1
-gdbstub_read_dword_cont:
- mov d1,(a1)
- ret [],0
-
-###############################################################################
-#
-# GDB stub write memory with guard
-# - D0 holds the byte to store
-# - D1 holds the memory address to write
-#
-###############################################################################
- .globl gdbstub_write_byte_guard
- .globl gdbstub_write_byte_cont
-ENTRY(gdbstub_write_byte)
- mov d0,a0
- mov d1,a1
- clr d0
-gdbstub_write_byte_guard:
- movbu a0,(a1)
-gdbstub_write_byte_cont:
- ret [],0
-
- .globl gdbstub_write_word_guard
- .globl gdbstub_write_word_cont
-ENTRY(gdbstub_write_word)
- mov d0,a0
- mov d1,a1
- clr d0
-gdbstub_write_word_guard:
- movhu a0,(a1)
-gdbstub_write_word_cont:
- ret [],0
-
- .globl gdbstub_write_dword_guard
- .globl gdbstub_write_dword_cont
-ENTRY(gdbstub_write_dword)
- mov d0,a0
- mov d1,a1
- clr d0
-gdbstub_write_dword_guard:
- mov a0,(a1)
-gdbstub_write_dword_cont:
- ret [],0
-
-###############################################################################
-#
-# GDB stub BUG() trap
-#
-###############################################################################
-ENTRY(__gdbstub_bug_trap)
- .byte 0xF7,0xF7 # don't use 0xFF as the JTAG unit preempts that
- ret [],0
diff --git a/arch/mn10300/kernel/gdb-stub.c b/arch/mn10300/kernel/gdb-stub.c
deleted file mode 100644
index 3399d5699804..000000000000
--- a/arch/mn10300/kernel/gdb-stub.c
+++ /dev/null
@@ -1,1924 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/* MN10300 GDB stub
- *
- * Originally written by Glenn Engel, Lake Stevens Instrument Division
- *
- * Contributed by HP Systems
- *
- * Modified for SPARC by Stu Grossman, Cygnus Support.
- *
- * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
- * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
- *
- * Copyright (C) 1995 Andreas Busse
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified for Linux/mn10300 by David Howells <dhowells@redhat.com>
- */
-
-/*
- * To enable debugger support, two things need to happen. One, a
- * call to set_debug_traps() is necessary in order to allow any breakpoints
- * or error conditions to be properly intercepted and reported to gdb.
- * Two, a breakpoint needs to be generated to begin communication. This
- * is most easily accomplished by a call to breakpoint(). Breakpoint()
- * simulates a breakpoint by executing a BREAK instruction.
- *
- *
- * The following gdb commands are supported:
- *
- * command function Return value
- *
- * g return the value of the CPU registers hex data or ENN
- * G set the value of the CPU registers OK or ENN
- *
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
- *
- * c Resume at current address SNN ( signal NN)
- * cAA..AA Continue at address AA..AA SNN
- *
- * s Step one instruction SNN
- * sAA..AA Step one instruction from AA..AA SNN
- *
- * k kill
- *
- * ? What was the last sigval ? SNN (signal NN)
- *
- * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
- * baud rate
- *
- * All commands and responses are sent with a packet which includes a
- * checksum. A packet consists of
- *
- * $<packet info>#<checksum>.
- *
- * where
- * <packet info> :: <characters representing the command or response>
- * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
- *
- * When a packet is received, it is first acknowledged with either '+' or '-'.
- * '+' indicates a successful transfer. '-' indicates a failed transfer.
- *
- * Example:
- *
- * Host: Reply:
- * $m0,10#2a +$00010203040506070809101112131415#42
- *
- *
- * ==============
- * MORE EXAMPLES:
- * ==============
- *
- * For reference -- the following are the steps that one
- * company took (RidgeRun Inc) to get remote gdb debugging
- * going. In this scenario the host machine was a PC and the
- * target platform was a Galileo EVB64120A MIPS evaluation
- * board.
- *
- * Step 1:
- * First download gdb-5.0.tar.gz from the internet.
- * and then build/install the package.
- *
- * Example:
- * $ tar zxf gdb-5.0.tar.gz
- * $ cd gdb-5.0
- * $ ./configure --target=am33_2.0-linux-gnu
- * $ make
- * $ install
- * am33_2.0-linux-gnu-gdb
- *
- * Step 2:
- * Configure linux for remote debugging and build it.
- *
- * Example:
- * $ cd ~/linux
- * $ make menuconfig <go to "Kernel Hacking" and turn on remote debugging>
- * $ make dep; make vmlinux
- *
- * Step 3:
- * Download the kernel to the remote target and start
- * the kernel running. It will promptly halt and wait
- * for the host gdb session to connect. It does this
- * since the "Kernel Hacking" option has defined
- * CONFIG_REMOTE_DEBUG which in turn enables your calls
- * to:
- * set_debug_traps();
- * breakpoint();
- *
- * Step 4:
- * Start the gdb session on the host.
- *
- * Example:
- * $ am33_2.0-linux-gnu-gdb vmlinux
- * (gdb) set remotebaud 115200
- * (gdb) target remote /dev/ttyS1
- * ...at this point you are connected to
- * the remote target and can use gdb
- * in the normal fasion. Setting
- * breakpoints, single stepping,
- * printing variables, etc.
- *
- */
-
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/bug.h>
-
-#include <asm/pgtable.h>
-#include <asm/gdb-stub.h>
-#include <asm/exceptions.h>
-#include <asm/debugger.h>
-#include <asm/serial-regs.h>
-#include <asm/busctl-regs.h>
-#include <unit/leds.h>
-#include <unit/serial.h>
-
-/* define to use F7F7 rather than FF which is subverted by JTAG debugger */
-#undef GDBSTUB_USE_F7F7_AS_BREAKPOINT
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound buffers
- * at least NUMREGBYTES*2 are needed for register packets
- */
-#define BUFMAX 2048
-
-static const char gdbstub_banner[] =
- "Linux/MN10300 GDB Stub (c) RedHat 2007\n";
-
-u8 gdbstub_rx_buffer[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
-u32 gdbstub_rx_inp;
-u32 gdbstub_rx_outp;
-u8 gdbstub_busy;
-u8 gdbstub_rx_overflow;
-u8 gdbstub_rx_unget;
-
-static u8 gdbstub_flush_caches;
-static char input_buffer[BUFMAX];
-static char output_buffer[BUFMAX];
-static char trans_buffer[BUFMAX];
-
-struct gdbstub_bkpt {
- u8 *addr; /* address of breakpoint */
- u8 len; /* size of breakpoint */
- u8 origbytes[7]; /* original bytes */
-};
-
-static struct gdbstub_bkpt gdbstub_bkpts[256];
-
-/*
- * local prototypes
- */
-static void getpacket(char *buffer);
-static int putpacket(char *buffer);
-static int computeSignal(enum exception_code excep);
-static int hex(unsigned char ch);
-static int hexToInt(char **ptr, int *intValue);
-static unsigned char *mem2hex(const void *mem, char *buf, int count,
- int may_fault);
-static const char *hex2mem(const char *buf, void *_mem, int count,
- int may_fault);
-
-/*
- * Convert ch from a hex digit to an int
- */
-static int hex(unsigned char ch)
-{
- if (ch >= 'a' && ch <= 'f')
- return ch - 'a' + 10;
- if (ch >= '0' && ch <= '9')
- return ch - '0';
- if (ch >= 'A' && ch <= 'F')
- return ch - 'A' + 10;
- return -1;
-}
-
-#ifdef CONFIG_GDBSTUB_DEBUGGING
-
-void debug_to_serial(const char *p, int n)
-{
- __debug_to_serial(p, n);
- /* gdbstub_console_write(NULL, p, n); */
-}
-
-void gdbstub_printk(const char *fmt, ...)
-{
- va_list args;
- int len;
-
- /* Emit the output into the temporary buffer */
- va_start(args, fmt);
- len = vsnprintf(trans_buffer, sizeof(trans_buffer), fmt, args);
- va_end(args);
- debug_to_serial(trans_buffer, len);
-}
-
-#endif
-
-static inline char *gdbstub_strcpy(char *dst, const char *src)
-{
- int loop = 0;
- while ((dst[loop] = src[loop]))
- loop++;
- return dst;
-}
-
-/*
- * scan for the sequence $<data>#<checksum>
- */
-static void getpacket(char *buffer)
-{
- unsigned char checksum;
- unsigned char xmitcsum;
- unsigned char ch;
- int count, i, ret, error;
-
- for (;;) {
- /*
- * wait around for the start character,
- * ignore all other characters
- */
- do {
- gdbstub_io_rx_char(&ch, 0);
- } while (ch != '$');
-
- checksum = 0;
- xmitcsum = -1;
- count = 0;
- error = 0;
-
- /*
- * now, read until a # or end of buffer is found
- */
- while (count < BUFMAX) {
- ret = gdbstub_io_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
-
- if (ch == '#')
- break;
- checksum += ch;
- buffer[count] = ch;
- count++;
- }
-
- if (error == -EIO) {
- gdbstub_proto("### GDB Rx Error - Skipping packet"
- " ###\n");
- gdbstub_proto("### GDB Tx NAK\n");
- gdbstub_io_tx_char('-');
- continue;
- }
-
- if (count >= BUFMAX || error)
- continue;
-
- buffer[count] = 0;
-
- /* read the checksum */
- ret = gdbstub_io_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
- xmitcsum = hex(ch) << 4;
-
- ret = gdbstub_io_rx_char(&ch, 0);
- if (ret < 0)
- error = ret;
- xmitcsum |= hex(ch);
-
- if (error) {
- if (error == -EIO)
- gdbstub_io("### GDB Rx Error -"
- " Skipping packet\n");
- gdbstub_io("### GDB Tx NAK\n");
- gdbstub_io_tx_char('-');
- continue;
- }
-
- /* check the checksum */
- if (checksum != xmitcsum) {
- gdbstub_io("### GDB Tx NAK\n");
- gdbstub_io_tx_char('-'); /* failed checksum */
- continue;
- }
-
- gdbstub_proto("### GDB Rx '$%s#%02x' ###\n", buffer, checksum);
- gdbstub_io("### GDB Tx ACK\n");
- gdbstub_io_tx_char('+'); /* successful transfer */
-
- /*
- * if a sequence char is present,
- * reply the sequence ID
- */
- if (buffer[2] == ':') {
- gdbstub_io_tx_char(buffer[0]);
- gdbstub_io_tx_char(buffer[1]);
-
- /*
- * remove sequence chars from buffer
- */
- count = 0;
- while (buffer[count])
- count++;
- for (i = 3; i <= count; i++)
- buffer[i - 3] = buffer[i];
- }
-
- break;
- }
-}
-
-/*
- * send the packet in buffer.
- * - return 0 if successfully ACK'd
- * - return 1 if abandoned due to new incoming packet
- */
-static int putpacket(char *buffer)
-{
- unsigned char checksum;
- unsigned char ch;
- int count;
-
- /*
- * $<packet info>#<checksum>.
- */
- gdbstub_proto("### GDB Tx $'%s'#?? ###\n", buffer);
-
- do {
- gdbstub_io_tx_char('$');
- checksum = 0;
- count = 0;
-
- while ((ch = buffer[count]) != 0) {
- gdbstub_io_tx_char(ch);
- checksum += ch;
- count += 1;
- }
-
- gdbstub_io_tx_char('#');
- gdbstub_io_tx_char(hex_asc_hi(checksum));
- gdbstub_io_tx_char(hex_asc_lo(checksum));
-
- } while (gdbstub_io_rx_char(&ch, 0),
- ch == '-' && (gdbstub_io("### GDB Rx NAK\n"), 0),
- ch != '-' && ch != '+' &&
- (gdbstub_io("### GDB Rx ??? %02x\n", ch), 0),
- ch != '+' && ch != '$');
-
- if (ch == '+') {
- gdbstub_io("### GDB Rx ACK\n");
- return 0;
- }
-
- gdbstub_io("### GDB Tx Abandoned\n");
- gdbstub_rx_unget = ch;
- return 1;
-}
-
-/*
- * While we find nice hex chars, build an int.
- * Return number of chars processed.
- */
-static int hexToInt(char **ptr, int *intValue)
-{
- int numChars = 0;
- int hexValue;
-
- *intValue = 0;
-
- while (**ptr) {
- hexValue = hex(**ptr);
- if (hexValue < 0)
- break;
-
- *intValue = (*intValue << 4) | hexValue;
- numChars++;
-
- (*ptr)++;
- }
-
- return (numChars);
-}
-
-#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP
-/*
- * We single-step by setting breakpoints. When an exception
- * is handled, we need to restore the instructions hoisted
- * when the breakpoints were set.
- *
- * This is where we save the original instructions.
- */
-static struct gdb_bp_save {
- u8 *addr;
- u8 opcode[2];
-} step_bp[2];
-
-static const unsigned char gdbstub_insn_sizes[256] =
-{
- /* 1 2 3 4 5 6 7 8 9 a b c d e f */
- 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */
- 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */
- 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */
- 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */
- 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */
- 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */
-};
-
-static int __gdbstub_mark_bp(u8 *addr, int ix)
-{
- /* vmalloc area */
- if (((u8 *) VMALLOC_START <= addr) && (addr < (u8 *) VMALLOC_END))
- goto okay;
- /* SRAM, SDRAM */
- if (((u8 *) 0x80000000UL <= addr) && (addr < (u8 *) 0xa0000000UL))
- goto okay;
- return 0;
-
-okay:
- if (gdbstub_read_byte(addr + 0, &step_bp[ix].opcode[0]) < 0 ||
- gdbstub_read_byte(addr + 1, &step_bp[ix].opcode[1]) < 0)
- return 0;
-
- step_bp[ix].addr = addr;
- return 1;
-}
-
-static inline void __gdbstub_restore_bp(void)
-{
-#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
- if (step_bp[0].addr) {
- gdbstub_write_byte(step_bp[0].opcode[0], step_bp[0].addr + 0);
- gdbstub_write_byte(step_bp[0].opcode[1], step_bp[0].addr + 1);
- }
- if (step_bp[1].addr) {
- gdbstub_write_byte(step_bp[1].opcode[0], step_bp[1].addr + 0);
- gdbstub_write_byte(step_bp[1].opcode[1], step_bp[1].addr + 1);
- }
-#else
- if (step_bp[0].addr)
- gdbstub_write_byte(step_bp[0].opcode[0], step_bp[0].addr + 0);
- if (step_bp[1].addr)
- gdbstub_write_byte(step_bp[1].opcode[0], step_bp[1].addr + 0);
-#endif
-
- gdbstub_flush_caches = 1;
-
- step_bp[0].addr = NULL;
- step_bp[0].opcode[0] = 0;
- step_bp[0].opcode[1] = 0;
- step_bp[1].addr = NULL;
- step_bp[1].opcode[0] = 0;
- step_bp[1].opcode[1] = 0;
-}
-
-/*
- * emulate single stepping by means of breakpoint instructions
- */
-static int gdbstub_single_step(struct pt_regs *regs)
-{
- unsigned size;
- uint32_t x;
- uint8_t cur, *pc, *sp;
-
- step_bp[0].addr = NULL;
- step_bp[0].opcode[0] = 0;
- step_bp[0].opcode[1] = 0;
- step_bp[1].addr = NULL;
- step_bp[1].opcode[0] = 0;
- step_bp[1].opcode[1] = 0;
- x = 0;
-
- pc = (u8 *) regs->pc;
- sp = (u8 *) (regs + 1);
- if (gdbstub_read_byte(pc, &cur) < 0)
- return -EFAULT;
-
- gdbstub_bkpt("Single Step from %p { %02x }\n", pc, cur);
-
- gdbstub_flush_caches = 1;
-
- size = gdbstub_insn_sizes[cur];
- if (size > 0) {
- if (!__gdbstub_mark_bp(pc + size, 0))
- goto fault;
- } else {
- switch (cur) {
- /* Bxx (d8,PC) */
- case 0xc0 ... 0xca:
- if (gdbstub_read_byte(pc + 1, (u8 *) &x) < 0)
- goto fault;
- if (!__gdbstub_mark_bp(pc + 2, 0))
- goto fault;
- if ((x < 0 || x > 2) &&
- !__gdbstub_mark_bp(pc + (s8) x, 1))
- goto fault;
- break;
-
- /* LXX (d8,PC) */
- case 0xd0 ... 0xda:
- if (!__gdbstub_mark_bp(pc + 1, 0))
- goto fault;
- if (regs->pc != regs->lar &&
- !__gdbstub_mark_bp((u8 *) regs->lar, 1))
- goto fault;
- break;
-
- /* SETLB - loads the next for bytes into the LIR
- * register */
- case 0xdb:
- if (!__gdbstub_mark_bp(pc + 1, 0))
- goto fault;
- break;
-
- /* JMP (d16,PC) or CALL (d16,PC) */
- case 0xcc:
- case 0xcd:
- if (gdbstub_read_byte(pc + 1, ((u8 *) &x) + 0) < 0 ||
- gdbstub_read_byte(pc + 2, ((u8 *) &x) + 1) < 0)
- goto fault;
- if (!__gdbstub_mark_bp(pc + (s16) x, 0))
- goto fault;
- break;
-
- /* JMP (d32,PC) or CALL (d32,PC) */
- case 0xdc:
- case 0xdd:
- if (gdbstub_read_byte(pc + 1, ((u8 *) &x) + 0) < 0 ||
- gdbstub_read_byte(pc + 2, ((u8 *) &x) + 1) < 0 ||
- gdbstub_read_byte(pc + 3, ((u8 *) &x) + 2) < 0 ||
- gdbstub_read_byte(pc + 4, ((u8 *) &x) + 3) < 0)
- goto fault;
- if (!__gdbstub_mark_bp(pc + (s32) x, 0))
- goto fault;
- break;
-
- /* RETF */
- case 0xde:
- if (!__gdbstub_mark_bp((u8 *) regs->mdr, 0))
- goto fault;
- break;
-
- /* RET */
- case 0xdf:
- if (gdbstub_read_byte(pc + 2, (u8 *) &x) < 0)
- goto fault;
- sp += (s8)x;
- if (gdbstub_read_byte(sp + 0, ((u8 *) &x) + 0) < 0 ||
- gdbstub_read_byte(sp + 1, ((u8 *) &x) + 1) < 0 ||
- gdbstub_read_byte(sp + 2, ((u8 *) &x) + 2) < 0 ||
- gdbstub_read_byte(sp + 3, ((u8 *) &x) + 3) < 0)
- goto fault;
- if (!__gdbstub_mark_bp((u8 *) x, 0))
- goto fault;
- break;
-
- case 0xf0:
- if (gdbstub_read_byte(pc + 1, &cur) < 0)
- goto fault;
-
- if (cur >= 0xf0 && cur <= 0xf7) {
- /* JMP (An) / CALLS (An) */
- switch (cur & 3) {
- case 0: x = regs->a0; break;
- case 1: x = regs->a1; break;
- case 2: x = regs->a2; break;
- case 3: x = regs->a3; break;
- }
- if (!__gdbstub_mark_bp((u8 *) x, 0))
- goto fault;
- } else if (cur == 0xfc) {
- /* RETS */
- if (gdbstub_read_byte(
- sp + 0, ((u8 *) &x) + 0) < 0 ||
- gdbstub_read_byte(
- sp + 1, ((u8 *) &x) + 1) < 0 ||
- gdbstub_read_byte(
- sp + 2, ((u8 *) &x) + 2) < 0 ||
- gdbstub_read_byte(
- sp + 3, ((u8 *) &x) + 3) < 0)
- goto fault;
- if (!__gdbstub_mark_bp((u8 *) x, 0))
- goto fault;
- } else if (cur == 0xfd) {
- /* RTI */
- if (gdbstub_read_byte(
- sp + 4, ((u8 *) &x) + 0) < 0 ||
- gdbstub_read_byte(
- sp + 5, ((u8 *) &x) + 1) < 0 ||
- gdbstub_read_byte(
- sp + 6, ((u8 *) &x) + 2) < 0 ||
- gdbstub_read_byte(
- sp + 7, ((u8 *) &x) + 3) < 0)
- goto fault;
- if (!__gdbstub_mark_bp((u8 *) x, 0))
- goto fault;
- } else {
- if (!__gdbstub_mark_bp(pc + 2, 0))
- goto fault;
- }
-
- break;
-
- /* potential 3-byte conditional branches */
- case 0xf8:
- if (gdbstub_read_byte(pc + 1, &cur) < 0)
- goto fault;
- if (!__gdbstub_mark_bp(pc + 3, 0))
- goto fault;
-
- if (cur >= 0xe8 && cur <= 0xeb) {
- if (gdbstub_read_byte(
- pc + 2, ((u8 *) &x) + 0) < 0)
- goto fault;
- if ((x < 0 || x > 3) &&
- !__gdbstub_mark_bp(pc + (s8) x, 1))
- goto fault;
- }
- break;
-
- case 0xfa:
- if (gdbstub_read_byte(pc + 1, &cur) < 0)
- goto fault;
-
- if (cur == 0xff) {
- /* CALLS (d16,PC) */
- if (gdbstub_read_byte(
- pc + 2, ((u8 *) &x) + 0) < 0 ||
- gdbstub_read_byte(
- pc + 3, ((u8 *) &x) + 1) < 0)
- goto fault;
- if (!__gdbstub_mark_bp(pc + (s16) x, 0))
- goto fault;
- } else {
- if (!__gdbstub_mark_bp(pc + 4, 0))
- goto fault;
- }
- break;
-
- case 0xfc:
- if (gdbstub_read_byte(pc + 1, &cur) < 0)
- goto fault;
- if (cur == 0xff) {
- /* CALLS (d32,PC) */
- if (gdbstub_read_byte(
- pc + 2, ((u8 *) &x) + 0) < 0 ||
- gdbstub_read_byte(
- pc + 3, ((u8 *) &x) + 1) < 0 ||
- gdbstub_read_byte(
- pc + 4, ((u8 *) &x) + 2) < 0 ||
- gdbstub_read_byte(
- pc + 5, ((u8 *) &x) + 3) < 0)
- goto fault;
- if (!__gdbstub_mark_bp(
- pc + (s32) x, 0))
- goto fault;
- } else {
- if (!__gdbstub_mark_bp(
- pc + 6, 0))
- goto fault;
- }
- break;
-
- }
- }
-
- gdbstub_bkpt("Step: %02x at %p; %02x at %p\n",
- step_bp[0].opcode[0], step_bp[0].addr,
- step_bp[1].opcode[0], step_bp[1].addr);
-
- if (step_bp[0].addr) {
-#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
- if (gdbstub_write_byte(0xF7, step_bp[0].addr + 0) < 0 ||
- gdbstub_write_byte(0xF7, step_bp[0].addr + 1) < 0)
- goto fault;
-#else
- if (gdbstub_write_byte(0xFF, step_bp[0].addr + 0) < 0)
- goto fault;
-#endif
- }
-
- if (step_bp[1].addr) {
-#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
- if (gdbstub_write_byte(0xF7, step_bp[1].addr + 0) < 0 ||
- gdbstub_write_byte(0xF7, step_bp[1].addr + 1) < 0)
- goto fault;
-#else
- if (gdbstub_write_byte(0xFF, step_bp[1].addr + 0) < 0)
- goto fault;
-#endif
- }
-
- return 0;
-
- fault:
- /* uh-oh - silly address alert, try and restore things */
- __gdbstub_restore_bp();
- return -EFAULT;
-}
-#endif /* CONFIG_GDBSTUB_ALLOW_SINGLE_STEP */
-
-#ifdef CONFIG_GDBSTUB_CONSOLE
-
-void gdbstub_console_write(struct console *con, const char *p, unsigned n)
-{
- static const char gdbstub_cr[] = { 0x0d };
- char outbuf[26];
- int qty;
- u8 busy;
-
- busy = gdbstub_busy;
- gdbstub_busy = 1;
-
- outbuf[0] = 'O';
-
- while (n > 0) {
- qty = 1;
-
- while (n > 0 && qty < 20) {
- mem2hex(p, outbuf + qty, 2, 0);
- qty += 2;
- if (*p == 0x0a) {
- mem2hex(gdbstub_cr, outbuf + qty, 2, 0);
- qty += 2;
- }
- p++;
- n--;
- }
-
- outbuf[qty] = 0;
- putpacket(outbuf);
- }
-
- gdbstub_busy = busy;
-}
-
-static kdev_t gdbstub_console_dev(struct console *con)
-{
- return MKDEV(1, 3); /* /dev/null */
-}
-
-static struct console gdbstub_console = {
- .name = "gdb",
- .write = gdbstub_console_write,
- .device = gdbstub_console_dev,
- .flags = CON_PRINTBUFFER,
- .index = -1,
-};
-
-#endif
-
-/*
- * Convert the memory pointed to by mem into hex, placing result in buf.
- * - if successful, return a pointer to the last char put in buf (NUL)
- * - in case of mem fault, return NULL
- * may_fault is non-zero if we are reading from arbitrary memory, but is
- * currently not used.
- */
-static
-unsigned char *mem2hex(const void *_mem, char *buf, int count, int may_fault)
-{
- const u8 *mem = _mem;
- u8 ch[4];
-
- if ((u32) mem & 1 && count >= 1) {
- if (gdbstub_read_byte(mem, ch) != 0)
- return 0;
- buf = hex_byte_pack(buf, ch[0]);
- mem++;
- count--;
- }
-
- if ((u32) mem & 3 && count >= 2) {
- if (gdbstub_read_word(mem, ch) != 0)
- return 0;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- mem += 2;
- count -= 2;
- }
-
- while (count >= 4) {
- if (gdbstub_read_dword(mem, ch) != 0)
- return 0;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- buf = hex_byte_pack(buf, ch[2]);
- buf = hex_byte_pack(buf, ch[3]);
- mem += 4;
- count -= 4;
- }
-
- if (count >= 2) {
- if (gdbstub_read_word(mem, ch) != 0)
- return 0;
- buf = hex_byte_pack(buf, ch[0]);
- buf = hex_byte_pack(buf, ch[1]);
- mem += 2;
- count -= 2;
- }
-
- if (count >= 1) {
- if (gdbstub_read_byte(mem, ch) != 0)
- return 0;
- buf = hex_byte_pack(buf, ch[0]);
- }
-
- *buf = 0;
- return buf;
-}
-
-/*
- * convert the hex array pointed to by buf into binary to be placed in mem
- * return a pointer to the character AFTER the last byte written
- * may_fault is non-zero if we are reading from arbitrary memory, but is
- * currently not used.
- */
-static
-const char *hex2mem(const char *buf, void *_mem, int count, int may_fault)
-{
- u8 *mem = _mem;
- union {
- u32 val;
- u8 b[4];
- } ch;
-
- if ((u32) mem & 1 && count >= 1) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- if (gdbstub_write_byte(ch.val, mem) != 0)
- return 0;
- mem++;
- count--;
- }
-
- if ((u32) mem & 3 && count >= 2) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- if (gdbstub_write_word(ch.val, mem) != 0)
- return 0;
- mem += 2;
- count -= 2;
- }
-
- while (count >= 4) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- ch.b[2] = hex(*buf++) << 4;
- ch.b[2] |= hex(*buf++);
- ch.b[3] = hex(*buf++) << 4;
- ch.b[3] |= hex(*buf++);
- if (gdbstub_write_dword(ch.val, mem) != 0)
- return 0;
- mem += 4;
- count -= 4;
- }
-
- if (count >= 2) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- ch.b[1] = hex(*buf++) << 4;
- ch.b[1] |= hex(*buf++);
- if (gdbstub_write_word(ch.val, mem) != 0)
- return 0;
- mem += 2;
- count -= 2;
- }
-
- if (count >= 1) {
- ch.b[0] = hex(*buf++) << 4;
- ch.b[0] |= hex(*buf++);
- if (gdbstub_write_byte(ch.val, mem) != 0)
- return 0;
- }
-
- return buf;
-}
-
-/*
- * This table contains the mapping between MN10300 exception codes, and
- * signals, which are primarily what GDB understands. It also indicates
- * which hardware traps we need to commandeer when initializing the stub.
- */
-static const struct excep_to_sig_map {
- enum exception_code excep; /* MN10300 exception code */
- unsigned char signo; /* Signal that we map this into */
-} excep_to_sig_map[] = {
- { EXCEP_ITLBMISS, SIGSEGV },
- { EXCEP_DTLBMISS, SIGSEGV },
- { EXCEP_TRAP, SIGTRAP },
- { EXCEP_ISTEP, SIGTRAP },
- { EXCEP_IBREAK, SIGTRAP },
- { EXCEP_OBREAK, SIGTRAP },
- { EXCEP_UNIMPINS, SIGILL },
- { EXCEP_UNIMPEXINS, SIGILL },
- { EXCEP_MEMERR, SIGSEGV },
- { EXCEP_MISALIGN, SIGSEGV },
- { EXCEP_BUSERROR, SIGBUS },
- { EXCEP_ILLINSACC, SIGSEGV },
- { EXCEP_ILLDATACC, SIGSEGV },
- { EXCEP_IOINSACC, SIGSEGV },
- { EXCEP_PRIVINSACC, SIGSEGV },
- { EXCEP_PRIVDATACC, SIGSEGV },
- { EXCEP_FPU_DISABLED, SIGFPE },
- { EXCEP_FPU_UNIMPINS, SIGFPE },
- { EXCEP_FPU_OPERATION, SIGFPE },
- { EXCEP_WDT, SIGALRM },
- { EXCEP_NMI, SIGQUIT },
- { EXCEP_IRQ_LEVEL0, SIGINT },
- { EXCEP_IRQ_LEVEL1, SIGINT },
- { EXCEP_IRQ_LEVEL2, SIGINT },
- { EXCEP_IRQ_LEVEL3, SIGINT },
- { EXCEP_IRQ_LEVEL4, SIGINT },
- { EXCEP_IRQ_LEVEL5, SIGINT },
- { EXCEP_IRQ_LEVEL6, SIGINT },
- { 0, 0}
-};
-
-/*
- * convert the MN10300 exception code into a UNIX signal number
- */
-static int computeSignal(enum exception_code excep)
-{
- const struct excep_to_sig_map *map;
-
- for (map = excep_to_sig_map; map->signo; map++)
- if (map->excep == excep)
- return map->signo;
-
- return SIGHUP; /* default for things we don't know about */
-}
-
-static u32 gdbstub_fpcr, gdbstub_fpufs_array[32];
-
-/*
- *
- */
-static void gdbstub_store_fpu(void)
-{
-#ifdef CONFIG_FPU
-
- asm volatile(
- "or %2,epsw\n"
-#ifdef CONFIG_MN10300_PROC_MN103E010
- "nop\n"
- "nop\n"
-#endif
- "mov %1, a1\n"
- "fmov fs0, (a1+)\n"
- "fmov fs1, (a1+)\n"
- "fmov fs2, (a1+)\n"
- "fmov fs3, (a1+)\n"
- "fmov fs4, (a1+)\n"
- "fmov fs5, (a1+)\n"
- "fmov fs6, (a1+)\n"
- "fmov fs7, (a1+)\n"
- "fmov fs8, (a1+)\n"
- "fmov fs9, (a1+)\n"
- "fmov fs10, (a1+)\n"
- "fmov fs11, (a1+)\n"
- "fmov fs12, (a1+)\n"
- "fmov fs13, (a1+)\n"
- "fmov fs14, (a1+)\n"
- "fmov fs15, (a1+)\n"
- "fmov fs16, (a1+)\n"
- "fmov fs17, (a1+)\n"
- "fmov fs18, (a1+)\n"
- "fmov fs19, (a1+)\n"
- "fmov fs20, (a1+)\n"
- "fmov fs21, (a1+)\n"
- "fmov fs22, (a1+)\n"
- "fmov fs23, (a1+)\n"
- "fmov fs24, (a1+)\n"
- "fmov fs25, (a1+)\n"
- "fmov fs26, (a1+)\n"
- "fmov fs27, (a1+)\n"
- "fmov fs28, (a1+)\n"
- "fmov fs29, (a1+)\n"
- "fmov fs30, (a1+)\n"
- "fmov fs31, (a1+)\n"
- "fmov fpcr, %0\n"
- : "=d"(gdbstub_fpcr)
- : "g" (&gdbstub_fpufs_array), "i"(EPSW_FE)
- : "a1"
- );
-#endif
-}
-
-/*
- *
- */
-static void gdbstub_load_fpu(void)
-{
-#ifdef CONFIG_FPU
-
- asm volatile(
- "or %1,epsw\n"
-#ifdef CONFIG_MN10300_PROC_MN103E010
- "nop\n"
- "nop\n"
-#endif
- "mov %0, a1\n"
- "fmov (a1+), fs0\n"
- "fmov (a1+), fs1\n"
- "fmov (a1+), fs2\n"
- "fmov (a1+), fs3\n"
- "fmov (a1+), fs4\n"
- "fmov (a1+), fs5\n"
- "fmov (a1+), fs6\n"
- "fmov (a1+), fs7\n"
- "fmov (a1+), fs8\n"
- "fmov (a1+), fs9\n"
- "fmov (a1+), fs10\n"
- "fmov (a1+), fs11\n"
- "fmov (a1+), fs12\n"
- "fmov (a1+), fs13\n"
- "fmov (a1+), fs14\n"
- "fmov (a1+), fs15\n"
- "fmov (a1+), fs16\n"
- "fmov (a1+), fs17\n"
- "fmov (a1+), fs18\n"
- "fmov (a1+), fs19\n"
- "fmov (a1+), fs20\n"
- "fmov (a1+), fs21\n"
- "fmov (a1+), fs22\n"
- "fmov (a1+), fs23\n"
- "fmov (a1+), fs24\n"
- "fmov (a1+), fs25\n"
- "fmov (a1+), fs26\n"
- "fmov (a1+), fs27\n"
- "fmov (a1+), fs28\n"
- "fmov (a1+), fs29\n"
- "fmov (a1+), fs30\n"
- "fmov (a1+), fs31\n"
- "fmov %2, fpcr\n"
- :
- : "g" (&gdbstub_fpufs_array), "i"(EPSW_FE), "d"(gdbstub_fpcr)
- : "a1"
- );
-#endif
-}
-
-/*
- * set a software breakpoint
- */
-int gdbstub_set_breakpoint(u8 *addr, int len)
-{
- int bkpt, loop, xloop;
-
-#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
- len = (len + 1) & ~1;
-#endif
-
- gdbstub_bkpt("setbkpt(%p,%d)\n", addr, len);
-
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (!gdbstub_bkpts[bkpt].addr)
- break;
- if (bkpt < 0)
- return -ENOSPC;
-
- for (loop = 0; loop < len; loop++)
- if (gdbstub_read_byte(&addr[loop],
- &gdbstub_bkpts[bkpt].origbytes[loop]
- ) < 0)
- return -EFAULT;
-
- gdbstub_flush_caches = 1;
-
-#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
- for (loop = 0; loop < len; loop++)
- if (gdbstub_write_byte(0xF7, &addr[loop]) < 0)
- goto restore;
-#else
- for (loop = 0; loop < len; loop++)
- if (gdbstub_write_byte(0xFF, &addr[loop]) < 0)
- goto restore;
-#endif
-
- gdbstub_bkpts[bkpt].addr = addr;
- gdbstub_bkpts[bkpt].len = len;
-
- gdbstub_bkpt("Set BKPT[%02x]: %p-%p {%02x%02x%02x%02x%02x%02x%02x}\n",
- bkpt,
- gdbstub_bkpts[bkpt].addr,
- gdbstub_bkpts[bkpt].addr + gdbstub_bkpts[bkpt].len - 1,
- gdbstub_bkpts[bkpt].origbytes[0],
- gdbstub_bkpts[bkpt].origbytes[1],
- gdbstub_bkpts[bkpt].origbytes[2],
- gdbstub_bkpts[bkpt].origbytes[3],
- gdbstub_bkpts[bkpt].origbytes[4],
- gdbstub_bkpts[bkpt].origbytes[5],
- gdbstub_bkpts[bkpt].origbytes[6]
- );
-
- return 0;
-
-restore:
- for (xloop = 0; xloop < loop; xloop++)
- gdbstub_write_byte(gdbstub_bkpts[bkpt].origbytes[xloop],
- addr + xloop);
- return -EFAULT;
-}
-
-/*
- * clear a software breakpoint
- */
-int gdbstub_clear_breakpoint(u8 *addr, int len)
-{
- int bkpt, loop;
-
-#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
- len = (len + 1) & ~1;
-#endif
-
- gdbstub_bkpt("clearbkpt(%p,%d)\n", addr, len);
-
- for (bkpt = 255; bkpt >= 0; bkpt--)
- if (gdbstub_bkpts[bkpt].addr == addr &&
- gdbstub_bkpts[bkpt].len == len)
- break;
- if (bkpt < 0)
- return -ENOENT;
-
- gdbstub_bkpts[bkpt].addr = NULL;
-
- gdbstub_flush_caches = 1;
-
- for (loop = 0; loop < len; loop++)
- if (gdbstub_write_byte(gdbstub_bkpts[bkpt].origbytes[loop],
- addr + loop) < 0)
- return -EFAULT;
-
- return 0;
-}
-
-/*
- * This function does all command processing for interfacing to gdb
- * - returns 0 if the exception should be skipped, -ERROR otherwise.
- */
-static int gdbstub(struct pt_regs *regs, enum exception_code excep)
-{
- unsigned long *stack;
- unsigned long epsw, mdr;
- uint32_t zero, ssp;
- uint8_t broke;
- char *ptr;
- int sigval;
- int addr;
- int length;
- int loop;
-
- if (excep == EXCEP_FPU_DISABLED)
- return -ENOTSUPP;
-
- gdbstub_flush_caches = 0;
-
- mn10300_set_gdbleds(1);
-
- asm volatile("mov mdr,%0" : "=d"(mdr));
- local_save_flags(epsw);
- arch_local_change_intr_mask_level(
- NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1));
-
- gdbstub_store_fpu();
-
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- /* skip the initial pause loop */
- if (regs->pc == (unsigned long) __gdbstub_pause)
- regs->pc = (unsigned long) start_kernel;
-#endif
-
- /* if we were single stepping, restore the opcodes hoisted for the
- * breakpoint[s] */
- broke = 0;
-#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP
- if ((step_bp[0].addr && step_bp[0].addr == (u8 *) regs->pc) ||
- (step_bp[1].addr && step_bp[1].addr == (u8 *) regs->pc))
- broke = 1;
-
- __gdbstub_restore_bp();
-#endif
-
- if (gdbstub_rx_unget) {
- sigval = SIGINT;
- if (gdbstub_rx_unget != 3)
- goto packet_waiting;
- gdbstub_rx_unget = 0;
- }
-
- stack = (unsigned long *) regs->sp;
- sigval = broke ? SIGTRAP : computeSignal(excep);
-
- /* send information about a BUG() */
- if (!user_mode(regs) && excep == EXCEP_SYSCALL15) {
- const struct bug_entry *bug;
-
- bug = find_bug(regs->pc);
- if (bug)
- goto found_bug;
- length = snprintf(trans_buffer, sizeof(trans_buffer),
- "BUG() at address %lx\n", regs->pc);
- goto send_bug_pkt;
-
- found_bug:
- length = snprintf(trans_buffer, sizeof(trans_buffer),
- "BUG() at address %lx (%s:%d)\n",
- regs->pc, bug->file, bug->line);
-
- send_bug_pkt:
- ptr = output_buffer;
- *ptr++ = 'O';
- ptr = mem2hex(trans_buffer, ptr, length, 0);
- *ptr = 0;
- putpacket(output_buffer);
-
- regs->pc -= 2;
- sigval = SIGABRT;
- } else if (regs->pc == (unsigned long) __gdbstub_bug_trap) {
- regs->pc = regs->mdr;
- sigval = SIGABRT;
- }
-
- /*
- * send a message to the debugger's user saying what happened if it may
- * not be clear cut (we can't map exceptions onto signals properly)
- */
- if (sigval != SIGINT && sigval != SIGTRAP && sigval != SIGILL) {
- static const char title[] = "Excep ", tbcberr[] = "BCBERR ";
- static const char crlf[] = "\r\n";
- char hx;
- u32 bcberr = BCBERR;
-
- ptr = output_buffer;
- *ptr++ = 'O';
- ptr = mem2hex(title, ptr, sizeof(title) - 1, 0);
-
- hx = hex_asc_hi(excep >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(excep >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(excep);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(excep);
- ptr = hex_byte_pack(ptr, hx);
-
- ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0);
- *ptr = 0;
- putpacket(output_buffer); /* send it off... */
-
- /* BCBERR */
- ptr = output_buffer;
- *ptr++ = 'O';
- ptr = mem2hex(tbcberr, ptr, sizeof(tbcberr) - 1, 0);
-
- hx = hex_asc_hi(bcberr >> 24);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(bcberr >> 24);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(bcberr >> 16);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(bcberr >> 16);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(bcberr >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(bcberr >> 8);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_hi(bcberr);
- ptr = hex_byte_pack(ptr, hx);
- hx = hex_asc_lo(bcberr);
- ptr = hex_byte_pack(ptr, hx);
-
- ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0);
- *ptr = 0;
- putpacket(output_buffer); /* send it off... */
- }
-
- /*
- * tell the debugger that an exception has occurred
- */
- ptr = output_buffer;
-
- /*
- * Send trap type (converted to signal)
- */
- *ptr++ = 'T';
- ptr = hex_byte_pack(ptr, sigval);
-
- /*
- * Send Error PC
- */
- ptr = hex_byte_pack(ptr, GDB_REGID_PC);
- *ptr++ = ':';
- ptr = mem2hex(&regs->pc, ptr, 4, 0);
- *ptr++ = ';';
-
- /*
- * Send frame pointer
- */
- ptr = hex_byte_pack(ptr, GDB_REGID_FP);
- *ptr++ = ':';
- ptr = mem2hex(&regs->a3, ptr, 4, 0);
- *ptr++ = ';';
-
- /*
- * Send stack pointer
- */
- ssp = (unsigned long) (regs + 1);
- ptr = hex_byte_pack(ptr, GDB_REGID_SP);
- *ptr++ = ':';
- ptr = mem2hex(&ssp, ptr, 4, 0);
- *ptr++ = ';';
-
- *ptr++ = 0;
- putpacket(output_buffer); /* send it off... */
-
-packet_waiting:
- /*
- * Wait for input from remote GDB
- */
- while (1) {
- output_buffer[0] = 0;
- getpacket(input_buffer);
-
- switch (input_buffer[0]) {
- /* request repeat of last signal number */
- case '?':
- output_buffer[0] = 'S';
- output_buffer[1] = hex_asc_hi(sigval);
- output_buffer[2] = hex_asc_lo(sigval);
- output_buffer[3] = 0;
- break;
-
- case 'd':
- /* toggle debug flag */
- break;
-
- /*
- * Return the value of the CPU registers
- */
- case 'g':
- zero = 0;
- ssp = (u32) (regs + 1);
- ptr = output_buffer;
- ptr = mem2hex(&regs->d0, ptr, 4, 0);
- ptr = mem2hex(&regs->d1, ptr, 4, 0);
- ptr = mem2hex(&regs->d2, ptr, 4, 0);
- ptr = mem2hex(&regs->d3, ptr, 4, 0);
- ptr = mem2hex(&regs->a0, ptr, 4, 0);
- ptr = mem2hex(&regs->a1, ptr, 4, 0);
- ptr = mem2hex(&regs->a2, ptr, 4, 0);
- ptr = mem2hex(&regs->a3, ptr, 4, 0);
-
- ptr = mem2hex(&ssp, ptr, 4, 0); /* 8 */
- ptr = mem2hex(&regs->pc, ptr, 4, 0);
- ptr = mem2hex(&regs->mdr, ptr, 4, 0);
- ptr = mem2hex(&regs->epsw, ptr, 4, 0);
- ptr = mem2hex(&regs->lir, ptr, 4, 0);
- ptr = mem2hex(&regs->lar, ptr, 4, 0);
- ptr = mem2hex(&regs->mdrq, ptr, 4, 0);
-
- ptr = mem2hex(&regs->e0, ptr, 4, 0); /* 15 */
- ptr = mem2hex(&regs->e1, ptr, 4, 0);
- ptr = mem2hex(&regs->e2, ptr, 4, 0);
- ptr = mem2hex(&regs->e3, ptr, 4, 0);
- ptr = mem2hex(&regs->e4, ptr, 4, 0);
- ptr = mem2hex(&regs->e5, ptr, 4, 0);
- ptr = mem2hex(&regs->e6, ptr, 4, 0);
- ptr = mem2hex(&regs->e7, ptr, 4, 0);
-
- ptr = mem2hex(&ssp, ptr, 4, 0);
- ptr = mem2hex(&regs, ptr, 4, 0);
- ptr = mem2hex(&regs->sp, ptr, 4, 0);
- ptr = mem2hex(&regs->mcrh, ptr, 4, 0); /* 26 */
- ptr = mem2hex(&regs->mcrl, ptr, 4, 0);
- ptr = mem2hex(&regs->mcvf, ptr, 4, 0);
-
- ptr = mem2hex(&gdbstub_fpcr, ptr, 4, 0); /* 29 - FPCR */
- ptr = mem2hex(&zero, ptr, 4, 0);
- ptr = mem2hex(&zero, ptr, 4, 0);
- for (loop = 0; loop < 32; loop++)
- ptr = mem2hex(&gdbstub_fpufs_array[loop],
- ptr, 4, 0); /* 32 - FS0-31 */
-
- break;
-
- /*
- * set the value of the CPU registers - return OK
- */
- case 'G':
- {
- const char *ptr;
-
- ptr = &input_buffer[1];
- ptr = hex2mem(ptr, &regs->d0, 4, 0);
- ptr = hex2mem(ptr, &regs->d1, 4, 0);
- ptr = hex2mem(ptr, &regs->d2, 4, 0);
- ptr = hex2mem(ptr, &regs->d3, 4, 0);
- ptr = hex2mem(ptr, &regs->a0, 4, 0);
- ptr = hex2mem(ptr, &regs->a1, 4, 0);
- ptr = hex2mem(ptr, &regs->a2, 4, 0);
- ptr = hex2mem(ptr, &regs->a3, 4, 0);
-
- ptr = hex2mem(ptr, &ssp, 4, 0); /* 8 */
- ptr = hex2mem(ptr, &regs->pc, 4, 0);
- ptr = hex2mem(ptr, &regs->mdr, 4, 0);
- ptr = hex2mem(ptr, &regs->epsw, 4, 0);
- ptr = hex2mem(ptr, &regs->lir, 4, 0);
- ptr = hex2mem(ptr, &regs->lar, 4, 0);
- ptr = hex2mem(ptr, &regs->mdrq, 4, 0);
-
- ptr = hex2mem(ptr, &regs->e0, 4, 0); /* 15 */
- ptr = hex2mem(ptr, &regs->e1, 4, 0);
- ptr = hex2mem(ptr, &regs->e2, 4, 0);
- ptr = hex2mem(ptr, &regs->e3, 4, 0);
- ptr = hex2mem(ptr, &regs->e4, 4, 0);
- ptr = hex2mem(ptr, &regs->e5, 4, 0);
- ptr = hex2mem(ptr, &regs->e6, 4, 0);
- ptr = hex2mem(ptr, &regs->e7, 4, 0);
-
- ptr = hex2mem(ptr, &ssp, 4, 0);
- ptr = hex2mem(ptr, &zero, 4, 0);
- ptr = hex2mem(ptr, &regs->sp, 4, 0);
- ptr = hex2mem(ptr, &regs->mcrh, 4, 0); /* 26 */
- ptr = hex2mem(ptr, &regs->mcrl, 4, 0);
- ptr = hex2mem(ptr, &regs->mcvf, 4, 0);
-
- ptr = hex2mem(ptr, &zero, 4, 0); /* 29 - FPCR */
- ptr = hex2mem(ptr, &zero, 4, 0);
- ptr = hex2mem(ptr, &zero, 4, 0);
- for (loop = 0; loop < 32; loop++) /* 32 - FS0-31 */
- ptr = hex2mem(ptr, &zero, 4, 0);
-
-#if 0
- /*
- * See if the stack pointer has moved. If so, then copy
- * the saved locals and ins to the new location.
- */
- unsigned long *newsp = (unsigned long *) registers[SP];
- if (sp != newsp)
- sp = memcpy(newsp, sp, 16 * 4);
-#endif
-
- gdbstub_strcpy(output_buffer, "OK");
- }
- break;
-
- /*
- * mAA..AA,LLLL Read LLLL bytes at address AA..AA
- */
- case 'm':
- ptr = &input_buffer[1];
-
- if (hexToInt(&ptr, &addr) &&
- *ptr++ == ',' &&
- hexToInt(&ptr, &length)
- ) {
- if (mem2hex((char *) addr, output_buffer,
- length, 1))
- break;
- gdbstub_strcpy(output_buffer, "E03");
- } else {
- gdbstub_strcpy(output_buffer, "E01");
- }
- break;
-
- /*
- * MAA..AA,LLLL: Write LLLL bytes at address AA.AA
- * return OK
- */
- case 'M':
- ptr = &input_buffer[1];
-
- if (hexToInt(&ptr, &addr) &&
- *ptr++ == ',' &&
- hexToInt(&ptr, &length) &&
- *ptr++ == ':'
- ) {
- if (hex2mem(ptr, (char *) addr, length, 1))
- gdbstub_strcpy(output_buffer, "OK");
- else
- gdbstub_strcpy(output_buffer, "E03");
-
- gdbstub_flush_caches = 1;
- } else {
- gdbstub_strcpy(output_buffer, "E02");
- }
- break;
-
- /*
- * cAA..AA Continue at address AA..AA(optional)
- */
- case 'c':
- /* try to read optional parameter, pc unchanged if no
- * parm */
-
- ptr = &input_buffer[1];
- if (hexToInt(&ptr, &addr))
- regs->pc = addr;
- goto done;
-
- /*
- * kill the program
- */
- case 'k' :
- goto done; /* just continue */
-
- /*
- * Reset the whole machine (FIXME: system dependent)
- */
- case 'r':
- break;
-
- /*
- * Step to next instruction
- */
- case 's':
- /* Using the T flag doesn't seem to perform single
- * stepping (it seems to wind up being caught by the
- * JTAG unit), so we have to use breakpoints and
- * continue instead.
- */
-#ifdef CONFIG_GDBSTUB_ALLOW_SINGLE_STEP
- if (gdbstub_single_step(regs) < 0)
- /* ignore any fault error for now */
- gdbstub_printk("unable to set single-step"
- " bp\n");
- goto done;
-#else
- gdbstub_strcpy(output_buffer, "E01");
- break;
-#endif
-
- /*
- * Set baud rate (bBB)
- */
- case 'b':
- do {
- int baudrate;
-
- ptr = &input_buffer[1];
- if (!hexToInt(&ptr, &baudrate)) {
- gdbstub_strcpy(output_buffer, "B01");
- break;
- }
-
- if (baudrate) {
- /* ACK before changing speed */
- putpacket("OK");
- gdbstub_io_set_baud(baudrate);
- }
- } while (0);
- break;
-
- /*
- * Set breakpoint
- */
- case 'Z':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr, &loop) || *ptr++ != ',' ||
- !hexToInt(&ptr, &addr) || *ptr++ != ',' ||
- !hexToInt(&ptr, &length)
- ) {
- gdbstub_strcpy(output_buffer, "E01");
- break;
- }
-
- /* only support software breakpoints */
- gdbstub_strcpy(output_buffer, "E03");
- if (loop != 0 ||
- length < 1 ||
- length > 7 ||
- (unsigned long) addr < 4096)
- break;
-
- if (gdbstub_set_breakpoint((u8 *) addr, length) < 0)
- break;
-
- gdbstub_strcpy(output_buffer, "OK");
- break;
-
- /*
- * Clear breakpoint
- */
- case 'z':
- ptr = &input_buffer[1];
-
- if (!hexToInt(&ptr, &loop) || *ptr++ != ',' ||
- !hexToInt(&ptr, &addr) || *ptr++ != ',' ||
- !hexToInt(&ptr, &length)
- ) {
- gdbstub_strcpy(output_buffer, "E01");
- break;
- }
-
- /* only support software breakpoints */
- gdbstub_strcpy(output_buffer, "E03");
- if (loop != 0 ||
- length < 1 ||
- length > 7 ||
- (unsigned long) addr < 4096)
- break;
-
- if (gdbstub_clear_breakpoint((u8 *) addr, length) < 0)
- break;
-
- gdbstub_strcpy(output_buffer, "OK");
- break;
-
- default:
- gdbstub_proto("### GDB Unsupported Cmd '%s'\n",
- input_buffer);
- break;
- }
-
- /* reply to the request */
- putpacket(output_buffer);
- }
-
-done:
- /*
- * Need to flush the instruction cache here, as we may
- * have deposited a breakpoint, and the icache probably
- * has no way of knowing that a data ref to some location
- * may have changed something that is in the instruction
- * cache.
- * NB: We flush both caches, just to be sure...
- */
- if (gdbstub_flush_caches)
- debugger_local_cache_flushinv();
-
- gdbstub_load_fpu();
- mn10300_set_gdbleds(0);
- if (excep == EXCEP_NMI)
- NMICR = NMICR_NMIF;
-
- touch_softlockup_watchdog();
-
- local_irq_restore(epsw);
- return 0;
-}
-
-/*
- * Determine if we hit a debugger special breakpoint that needs skipping over
- * automatically.
- */
-int at_debugger_breakpoint(struct pt_regs *regs)
-{
- return 0;
-}
-
-/*
- * handle event interception
- */
-asmlinkage int debugger_intercept(enum exception_code excep,
- int signo, int si_code, struct pt_regs *regs)
-{
- static u8 notfirst = 1;
- int ret;
-
- if (gdbstub_busy)
- gdbstub_printk("--> gdbstub reentered itself\n");
- gdbstub_busy = 1;
-
- if (notfirst) {
- unsigned long mdr;
- asm("mov mdr,%0" : "=d"(mdr));
-
- gdbstub_entry(
- "--> debugger_intercept(%p,%04x) [MDR=%lx PC=%lx]\n",
- regs, excep, mdr, regs->pc);
-
- gdbstub_entry(
- "PC: %08lx EPSW: %08lx SSP: %08lx mode: %s\n",
- regs->pc, regs->epsw, (unsigned long) &ret,
- user_mode(regs) ? "User" : "Super");
- gdbstub_entry(
- "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
- regs->d0, regs->d1, regs->d2, regs->d3);
- gdbstub_entry(
- "a0: %08lx a1: %08lx a2: %08lx a3: %08lx\n",
- regs->a0, regs->a1, regs->a2, regs->a3);
- gdbstub_entry(
- "e0: %08lx e1: %08lx e2: %08lx e3: %08lx\n",
- regs->e0, regs->e1, regs->e2, regs->e3);
- gdbstub_entry(
- "e4: %08lx e5: %08lx e6: %08lx e7: %08lx\n",
- regs->e4, regs->e5, regs->e6, regs->e7);
- gdbstub_entry(
- "lar: %08lx lir: %08lx mdr: %08lx usp: %08lx\n",
- regs->lar, regs->lir, regs->mdr, regs->sp);
- gdbstub_entry(
- "cvf: %08lx crl: %08lx crh: %08lx drq: %08lx\n",
- regs->mcvf, regs->mcrl, regs->mcrh, regs->mdrq);
- gdbstub_entry(
- "threadinfo=%p task=%p)\n",
- current_thread_info(), current);
- } else {
- notfirst = 1;
- }
-
- ret = gdbstub(regs, excep);
-
- gdbstub_entry("<-- debugger_intercept()\n");
- gdbstub_busy = 0;
- return ret;
-}
-
-/*
- * handle the GDB stub itself causing an exception
- */
-asmlinkage void gdbstub_exception(struct pt_regs *regs,
- enum exception_code excep)
-{
- unsigned long mdr;
-
- asm("mov mdr,%0" : "=d"(mdr));
- gdbstub_entry("--> gdbstub exception({%p},%04x) [MDR=%lx]\n",
- regs, excep, mdr);
-
- while ((unsigned long) regs == 0xffffffff) {}
-
- /* handle guarded memory accesses where we know it might fault */
- if (regs->pc == (unsigned) gdbstub_read_byte_guard) {
- regs->pc = (unsigned) gdbstub_read_byte_cont;
- goto fault;
- }
-
- if (regs->pc == (unsigned) gdbstub_read_word_guard) {
- regs->pc = (unsigned) gdbstub_read_word_cont;
- goto fault;
- }
-
- if (regs->pc == (unsigned) gdbstub_read_dword_guard) {
- regs->pc = (unsigned) gdbstub_read_dword_cont;
- goto fault;
- }
-
- if (regs->pc == (unsigned) gdbstub_write_byte_guard) {
- regs->pc = (unsigned) gdbstub_write_byte_cont;
- goto fault;
- }
-
- if (regs->pc == (unsigned) gdbstub_write_word_guard) {
- regs->pc = (unsigned) gdbstub_write_word_cont;
- goto fault;
- }
-
- if (regs->pc == (unsigned) gdbstub_write_dword_guard) {
- regs->pc = (unsigned) gdbstub_write_dword_cont;
- goto fault;
- }
-
- gdbstub_printk("\n### GDB stub caused an exception ###\n");
-
- /* something went horribly wrong */
- console_verbose();
- show_registers(regs);
-
- panic("GDB Stub caused an unexpected exception - can't continue\n");
-
- /* we caught an attempt by the stub to access silly memory */
-fault:
- gdbstub_entry("<-- gdbstub exception() = EFAULT\n");
- regs->d0 = -EFAULT;
- return;
-}
-
-/*
- * send an exit message to GDB
- */
-void gdbstub_exit(int status)
-{
- unsigned char checksum;
- unsigned char ch;
- int count;
-
- gdbstub_busy = 1;
- output_buffer[0] = 'W';
- output_buffer[1] = hex_asc_hi(status);
- output_buffer[2] = hex_asc_lo(status);
- output_buffer[3] = 0;
-
- gdbstub_io_tx_char('$');
- checksum = 0;
- count = 0;
-
- while ((ch = output_buffer[count]) != 0) {
- gdbstub_io_tx_char(ch);
- checksum += ch;
- count += 1;
- }
-
- gdbstub_io_tx_char('#');
- gdbstub_io_tx_char(hex_asc_hi(checksum));
- gdbstub_io_tx_char(hex_asc_lo(checksum));
-
- /* make sure the output is flushed, or else RedBoot might clobber it */
- gdbstub_io_tx_flush();
-
- gdbstub_busy = 0;
-}
-
-/*
- * initialise the GDB stub
- */
-asmlinkage void __init gdbstub_init(void)
-{
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- unsigned char ch;
- int ret;
-#endif
-
- gdbstub_busy = 1;
-
- printk(KERN_INFO "%s", gdbstub_banner);
-
- gdbstub_io_init();
-
- gdbstub_entry("--> gdbstub_init\n");
-
- /* try to talk to GDB (or anyone insane enough to want to type GDB
- * protocol by hand) */
- gdbstub_io("### GDB Tx ACK\n");
- gdbstub_io_tx_char('+'); /* 'hello world' */
-
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- gdbstub_printk("GDB Stub waiting for packet\n");
-
- /* in case GDB is started before us, ACK any packets that are already
- * sitting there (presumably "$?#xx")
- */
- do { gdbstub_io_rx_char(&ch, 0); } while (ch != '$');
- do { gdbstub_io_rx_char(&ch, 0); } while (ch != '#');
- /* eat first csum byte */
- do { ret = gdbstub_io_rx_char(&ch, 0); } while (ret != 0);
- /* eat second csum byte */
- do { ret = gdbstub_io_rx_char(&ch, 0); } while (ret != 0);
-
- gdbstub_io("### GDB Tx NAK\n");
- gdbstub_io_tx_char('-'); /* NAK it */
-
-#else
- printk("GDB Stub ready\n");
-#endif
-
- gdbstub_busy = 0;
- gdbstub_entry("<-- gdbstub_init\n");
-}
-
-/*
- * register the console at a more appropriate time
- */
-#ifdef CONFIG_GDBSTUB_CONSOLE
-static int __init gdbstub_postinit(void)
-{
- printk(KERN_NOTICE "registering console\n");
- register_console(&gdbstub_console);
- return 0;
-}
-
-__initcall(gdbstub_postinit);
-#endif
-
-/*
- * handle character reception on GDB serial port
- * - jump into the GDB stub if BREAK is detected on the serial line
- */
-asmlinkage void gdbstub_rx_irq(struct pt_regs *regs, enum exception_code excep)
-{
- char ch;
- int ret;
-
- gdbstub_entry("--> gdbstub_rx_irq\n");
-
- do {
- ret = gdbstub_io_rx_char(&ch, 1);
- if (ret != -EIO && ret != -EAGAIN) {
- if (ret != -EINTR)
- gdbstub_rx_unget = ch;
- gdbstub(regs, excep);
- }
- } while (ret != -EAGAIN);
-
- gdbstub_entry("<-- gdbstub_rx_irq\n");
-}
diff --git a/arch/mn10300/kernel/head.S b/arch/mn10300/kernel/head.S
deleted file mode 100644
index 0b15f759e0d2..000000000000
--- a/arch/mn10300/kernel/head.S
+++ /dev/null
@@ -1,442 +0,0 @@
-/* Boot entry point for MN10300 kernel
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/init.h>
-#include <linux/threads.h>
-#include <linux/linkage.h>
-#include <linux/serial_reg.h>
-#include <asm/thread_info.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/frame.inc>
-#include <asm/param.h>
-#include <unit/serial.h>
-#ifdef CONFIG_SMP
-#include <asm/smp.h>
-#include <asm/intctl-regs.h>
-#include <asm/cpu-regs.h>
-#include <proc/smp-regs.h>
-#endif /* CONFIG_SMP */
-
- __HEAD
-
-###############################################################################
-#
-# bootloader entry point
-#
-###############################################################################
- .globl _start
- .type _start,@function
-_start:
-#ifdef CONFIG_SMP
- #
- # If this is a secondary CPU (AP), then deal with that elsewhere
- #
- mov (CPUID),d3
- and CPUID_MASK,d3
- bne startup_secondary
-
- #
- # We're dealing with the primary CPU (BP) here, then.
- # Keep BP's D0,D1,D2 register for boot check.
- #
-
- # Set up the Boot IPI for each secondary CPU
- mov 0x1,a0
-loop_set_secondary_icr:
- mov a0,a1
- asl CROSS_ICR_CPU_SHIFT,a1
- add CROSS_GxICR(SMP_BOOT_IRQ,0),a1
- movhu (a1),d3
- or GxICR_ENABLE|GxICR_LEVEL_0,d3
- movhu d3,(a1)
- movhu (a1),d3 # flush
- inc a0
- cmp NR_CPUS,a0
- bne loop_set_secondary_icr
-#endif /* CONFIG_SMP */
-
- # save commandline pointer
- mov d0,a3
-
- # preload the PGD pointer register
- mov swapper_pg_dir,d0
- mov d0,(PTBR)
- clr d0
- movbu d0,(PIDR)
-
- # turn on the TLBs
- mov MMUCTR_IIV|MMUCTR_DIV,d0
- mov d0,(MMUCTR)
-#ifdef CONFIG_AM34_2
- mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0
-#else
- mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0
-#endif
- mov d0,(MMUCTR)
-
- # turn on AM33v2 exception handling mode and set the trap table base
- movhu (CPUP),d0
- or CPUP_EXM_AM33V2,d0
- movhu d0,(CPUP)
- mov CONFIG_INTERRUPT_VECTOR_BASE,d0
- mov d0,(TBR)
-
- # invalidate and enable both of the caches
-#ifdef CONFIG_SMP
- mov ECHCTR,a0
- clr d0
- mov d0,(a0)
-#endif
- mov CHCTR,a0
- clr d0
- movhu d0,(a0) # turn off first
- mov CHCTR_ICINV|CHCTR_DCINV,d0
- movhu d0,(a0)
- setlb
- mov (a0),d0
- btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
- lne
-
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-#ifdef CONFIG_MN10300_CACHE_WBACK
-#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
-#else
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0
-#endif /* NOWRALLOC */
-#else
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
-#endif /* WBACK */
- movhu d0,(a0) # enable
-#endif /* ENABLED */
-
- # turn on RTS on the debug serial port if applicable
-#ifdef CONFIG_MN10300_UNIT_ASB2305
- bset UART_MCR_RTS,(ASB2305_DEBUG_MCR)
-#endif
-
- # clear the BSS area
- mov __bss_start,a0
- mov __bss_stop,a1
- clr d0
-bssclear:
- cmp a1,a0
- bge bssclear_end
- mov d0,(a0)
- inc4 a0
- bra bssclear
-bssclear_end:
-
- # retrieve the parameters (including command line) before we overwrite
- # them
- cmp 0xabadcafe,d1
- bne __no_parameters
-
-__copy_parameters:
- mov redboot_command_line,a0
- mov a0,a1
- add COMMAND_LINE_SIZE,a1
-1:
- movbu (a3),d0
- inc a3
- movbu d0,(a0)
- inc a0
- cmp a1,a0
- blt 1b
-
- mov redboot_platform_name,a0
- mov a0,a1
- add COMMAND_LINE_SIZE,a1
- mov d2,a3
-1:
- movbu (a3),d0
- inc a3
- movbu d0,(a0)
- inc a0
- cmp a1,a0
- blt 1b
-
-__no_parameters:
-
- # set up the registers with recognisable rubbish in them
- mov init_thread_union+THREAD_SIZE-12,sp
-
- mov 0xea01eaea,d0
- mov d0,(4,sp) # EPSW save area
- mov 0xea02eaea,d0
- mov d0,(8,sp) # PC save area
-
- mov 0xeb0060ed,d0
- mov d0,mdr
- mov 0xeb0061ed,d0
- mov d0,mdrq
- mov 0xeb0062ed,d0
- mov d0,mcrh
- mov 0xeb0063ed,d0
- mov d0,mcrl
- mov 0xeb0064ed,d0
- mov d0,mcvf
- mov 0xed0065ed,a3
- mov a3,usp
-
- mov 0xed00e0ed,e0
- mov 0xed00e1ed,e1
- mov 0xed00e2ed,e2
- mov 0xed00e3ed,e3
- mov 0xed00e4ed,e4
- mov 0xed00e5ed,e5
- mov 0xed00e6ed,e6
- mov 0xed00e7ed,e7
-
- mov 0xed00d0ed,d0
- mov 0xed00d1ed,d1
- mov 0xed00d2ed,d2
- mov 0xed00d3ed,d3
- mov 0xed00a0ed,a0
- mov 0xed00a1ed,a1
- mov 0xed00a2ed,a2
- mov 0,a3
-
- # set up the initial kernel stack
- SAVE_ALL
- mov 0xffffffff,d0
- mov d0,(REG_ORIG_D0,fp)
-
- # put different recognisable rubbish in the regs
- mov 0xfb0060ed,d0
- mov d0,mdr
- mov 0xfb0061ed,d0
- mov d0,mdrq
- mov 0xfb0062ed,d0
- mov d0,mcrh
- mov 0xfb0063ed,d0
- mov d0,mcrl
- mov 0xfb0064ed,d0
- mov d0,mcvf
- mov 0xfd0065ed,a0
- mov a0,usp
-
- mov 0xfd00e0ed,e0
- mov 0xfd00e1ed,e1
- mov 0xfd00e2ed,e2
- mov 0xfd00e3ed,e3
- mov 0xfd00e4ed,e4
- mov 0xfd00e5ed,e5
- mov 0xfd00e6ed,e6
- mov 0xfd00e7ed,e7
-
- mov 0xfd00d0ed,d0
- mov 0xfd00d1ed,d1
- mov 0xfd00d2ed,d2
- mov 0xfd00d3ed,d3
- mov 0xfd00a0ed,a0
- mov 0xfd00a1ed,a1
- mov 0xfd00a2ed,a2
-
- # we may be holding current in E2
-#ifdef CONFIG_MN10300_CURRENT_IN_E2
- mov init_task,e2
-#endif
-
- # initialise the processor and the unit
- call processor_init[],0
- call unit_init[],0
-
-#ifdef CONFIG_SMP
- # mark the primary CPU in cpu_boot_map
- mov cpu_boot_map,a0
- mov 0x1,d0
- mov d0,(a0)
-
- # signal each secondary CPU to begin booting
- mov 0x1,d2 # CPU ID
-
-loop_request_boot_secondary:
- mov d2,a0
- # send SMP_BOOT_IPI to secondary CPU
- asl CROSS_ICR_CPU_SHIFT,a0
- add CROSS_GxICR(SMP_BOOT_IRQ,0),a0
- movhu (a0),d0
- or GxICR_REQUEST|GxICR_DETECT,d0
- movhu d0,(a0)
- movhu (a0),d0 # flush
-
- # wait up to 100ms for AP's IPI to be received
- clr d3
-wait_on_secondary_boot:
- mov DELAY_TIME_BOOT_IPI,d0
- call __delay[],0
- inc d3
- mov cpu_boot_map,a0
- mov (a0),d0
- lsr d2,d0
- btst 0x1,d0
- bne 1f
- cmp TIME_OUT_COUNT_BOOT_IPI,d3
- bne wait_on_secondary_boot
-1:
- inc d2
- cmp NR_CPUS,d2
- bne loop_request_boot_secondary
-#endif /* CONFIG_SMP */
-
-#ifdef CONFIG_GDBSTUB
- call gdbstub_init[],0
-
-#ifdef CONFIG_GDBSTUB_IMMEDIATE
- .globl __gdbstub_pause
-__gdbstub_pause:
- bra __gdbstub_pause
-#endif
-#endif
-
- jmp start_kernel
- .size _start,.-_start
-
-###############################################################################
-#
-# Secondary CPU boot point
-#
-###############################################################################
-#ifdef CONFIG_SMP
-startup_secondary:
- # preload the PGD pointer register
- mov swapper_pg_dir,d0
- mov d0,(PTBR)
- clr d0
- movbu d0,(PIDR)
-
- # turn on the TLBs
- mov MMUCTR_IIV|MMUCTR_DIV,d0
- mov d0,(MMUCTR)
-#ifdef CONFIG_AM34_2
- mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0
-#else
- mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0
-#endif
- mov d0,(MMUCTR)
-
- # turn on AM33v2 exception handling mode and set the trap table base
- movhu (CPUP),d0
- or CPUP_EXM_AM33V2,d0
- movhu d0,(CPUP)
-
- # set the interrupt vector table
- mov CONFIG_INTERRUPT_VECTOR_BASE,d0
- mov d0,(TBR)
-
- # invalidate and enable both of the caches
- mov ECHCTR,a0
- clr d0
- mov d0,(a0)
- mov CHCTR,a0
- clr d0
- movhu d0,(a0) # turn off first
- mov CHCTR_ICINV|CHCTR_DCINV,d0
- movhu d0,(a0)
- setlb
- mov (a0),d0
- btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer)
- lne
-
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-#ifdef CONFIG_MN10300_CACHE_WBACK
-#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
-#else
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0
-#endif /* !NOWRALLOC */
-#else
- mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
-#endif /* WBACK */
- movhu d0,(a0) # enable
-#endif /* ENABLED */
-
- # Clear the boot IPI interrupt for this CPU
- movhu (GxICR(SMP_BOOT_IRQ)),d0
- and ~GxICR_REQUEST,d0
- movhu d0,(GxICR(SMP_BOOT_IRQ))
- movhu (GxICR(SMP_BOOT_IRQ)),d0 # flush
-
- /* get stack */
- mov CONFIG_INTERRUPT_VECTOR_BASE + CONFIG_BOOT_STACK_OFFSET,a0
- mov (CPUID),d0
- and CPUID_MASK,d0
- mulu CONFIG_BOOT_STACK_SIZE,d0
- sub d0,a0
- mov a0,sp
-
- # init interrupt for AP
- call smp_prepare_cpu_init[],0
-
- # mark this secondary CPU in cpu_boot_map
- mov (CPUID),d0
- mov 0x1,d1
- asl d0,d1
- mov cpu_boot_map,a0
- bset d1,(a0)
-
- or EPSW_IE|EPSW_IM_1,epsw # permit level 0 interrupts
- nop
- nop
-#ifdef CONFIG_MN10300_CACHE_WBACK
- # flush the local cache if it's in writeback mode
- call mn10300_local_dcache_flush_inv[],0
- setlb
- mov (CHCTR),d0
- btst CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer)
- lne
-#endif
-
- # now sleep waiting for further instructions
-secondary_sleep:
- mov CPUM_SLEEP,d0
- movhu d0,(CPUM)
- nop
- nop
- bra secondary_sleep
- .size startup_secondary,.-startup_secondary
-#endif /* CONFIG_SMP */
-
-###############################################################################
-#
-#
-#
-###############################################################################
-ENTRY(__head_end)
-
-/*
- * This is initialized to disallow all access to the low 2G region
- * - the high 2G region is managed directly by the MMU
- * - range 0x70000000-0x7C000000 are initialised for use by VMALLOC
- */
- .section .bss
- .balign PAGE_SIZE
-ENTRY(swapper_pg_dir)
- .space PTRS_PER_PGD*4
-
-/*
- * The page tables are initialized to only 8MB here - the final page
- * tables are set up later depending on memory size.
- */
-
- .balign PAGE_SIZE
-ENTRY(empty_zero_page)
- .space PAGE_SIZE
-
- .balign PAGE_SIZE
-ENTRY(large_page_table)
- .space PAGE_SIZE
-
- .balign PAGE_SIZE
-ENTRY(kernel_vmalloc_ptes)
- .space ((VMALLOC_END-VMALLOC_START)/PAGE_SIZE)*4
diff --git a/arch/mn10300/kernel/internal.h b/arch/mn10300/kernel/internal.h
deleted file mode 100644
index 561785581f6c..000000000000
--- a/arch/mn10300/kernel/internal.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Internal definitions for the arch part of the core kernel
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/irqreturn.h>
-
-struct clocksource;
-struct clock_event_device;
-
-/*
- * entry.S
- */
-extern void ret_from_fork(struct task_struct *) __attribute__((noreturn));
-extern void ret_from_kernel_thread(struct task_struct *) __attribute__((noreturn));
-
-/*
- * smp-low.S
- */
-#ifdef CONFIG_SMP
-extern void mn10300_low_ipi_handler(void);
-#endif
-
-/*
- * smp.c
- */
-#ifdef CONFIG_SMP
-extern void smp_jump_to_debugger(void);
-#endif
-
-/*
- * time.c
- */
-extern irqreturn_t local_timer_interrupt(void);
diff --git a/arch/mn10300/kernel/io.c b/arch/mn10300/kernel/io.c
deleted file mode 100644
index e96fdf6bb542..000000000000
--- a/arch/mn10300/kernel/io.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* MN10300 Misaligned multibyte-word I/O
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/io.h>
-
-/*
- * output data from a potentially misaligned buffer
- */
-void __outsl(unsigned long addr, const void *buffer, int count)
-{
- const unsigned char *buf = buffer;
- unsigned long val;
-
- while (count--) {
- memcpy(&val, buf, 4);
- outl(val, addr);
- buf += 4;
- }
-}
-EXPORT_SYMBOL(__outsl);
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c
deleted file mode 100644
index c716437baa2c..000000000000
--- a/arch/mn10300/kernel/irq.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* MN10300 Arch-specific interrupt handling
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/seq_file.h>
-#include <linux/cpumask.h>
-#include <asm/setup.h>
-#include <asm/serial-regs.h>
-
-unsigned long __mn10300_irq_enabled_epsw[NR_CPUS] __cacheline_aligned_in_smp = {
- [0 ... NR_CPUS - 1] = EPSW_IE | EPSW_IM_7
-};
-EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);
-
-#ifdef CONFIG_SMP
-static char irq_affinity_online[NR_IRQS] = {
- [0 ... NR_IRQS - 1] = 0
-};
-
-#define NR_IRQ_WORDS ((NR_IRQS + 31) / 32)
-static unsigned long irq_affinity_request[NR_IRQ_WORDS] = {
- [0 ... NR_IRQ_WORDS - 1] = 0
-};
-#endif /* CONFIG_SMP */
-
-atomic_t irq_err_count;
-
-/*
- * MN10300 interrupt controller operations
- */
-static void mn10300_cpupic_ack(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
- GxICR_u8(irq) = GxICR_DETECT;
- tmp = GxICR(irq);
- arch_local_irq_restore(flags);
-}
-
-static void __mask_and_set_icr(unsigned int irq,
- unsigned int mask, unsigned int set)
-{
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
- tmp = GxICR(irq);
- GxICR(irq) = (tmp & mask) | set;
- tmp = GxICR(irq);
- arch_local_irq_restore(flags);
-}
-
-static void mn10300_cpupic_mask(struct irq_data *d)
-{
- __mask_and_set_icr(d->irq, GxICR_LEVEL, 0);
-}
-
-static void mn10300_cpupic_mask_ack(struct irq_data *d)
-{
- unsigned int irq = d->irq;
-#ifdef CONFIG_SMP
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
-
- if (!test_and_clear_bit(irq, irq_affinity_request)) {
- tmp = GxICR(irq);
- GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
- tmp = GxICR(irq);
- } else {
- u16 tmp2;
- tmp = GxICR(irq);
- GxICR(irq) = (tmp & GxICR_LEVEL);
- tmp2 = GxICR(irq);
-
- irq_affinity_online[irq] =
- cpumask_any_and(irq_data_get_affinity_mask(d),
- cpu_online_mask);
- CROSS_GxICR(irq, irq_affinity_online[irq]) =
- (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT;
- tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
- }
-
- arch_local_irq_restore(flags);
-#else /* CONFIG_SMP */
- __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_DETECT);
-#endif /* CONFIG_SMP */
-}
-
-static void mn10300_cpupic_unmask(struct irq_data *d)
-{
- __mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE);
-}
-
-static void mn10300_cpupic_unmask_clear(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- /* the MN10300 PIC latches its interrupt request bit, even after the
- * device has ceased to assert its interrupt line and the interrupt
- * channel has been disabled in the PIC, so for level-triggered
- * interrupts we need to clear the request bit when we re-enable */
-#ifdef CONFIG_SMP
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
-
- if (!test_and_clear_bit(irq, irq_affinity_request)) {
- tmp = GxICR(irq);
- GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
- tmp = GxICR(irq);
- } else {
- tmp = GxICR(irq);
-
- irq_affinity_online[irq] = cpumask_any_and(irq_data_get_affinity_mask(d),
- cpu_online_mask);
- CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
- tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
- }
-
- arch_local_irq_restore(flags);
-#else /* CONFIG_SMP */
- __mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE | GxICR_DETECT);
-#endif /* CONFIG_SMP */
-}
-
-#ifdef CONFIG_SMP
-static int
-mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask,
- bool force)
-{
- unsigned long flags;
-
- flags = arch_local_cli_save();
- set_bit(d->irq, irq_affinity_request);
- arch_local_irq_restore(flags);
- return 0;
-}
-#endif /* CONFIG_SMP */
-
-/*
- * MN10300 PIC level-triggered IRQ handling.
- *
- * The PIC has no 'ACK' function per se. It is possible to clear individual
- * channel latches, but each latch relatches whether or not the channel is
- * masked, so we need to clear the latch when we unmask the channel.
- *
- * Also for this reason, we don't supply an ack() op (it's unused anyway if
- * mask_ack() is provided), and mask_ack() just masks.
- */
-static struct irq_chip mn10300_cpu_pic_level = {
- .name = "cpu_l",
- .irq_disable = mn10300_cpupic_mask,
- .irq_enable = mn10300_cpupic_unmask_clear,
- .irq_ack = NULL,
- .irq_mask = mn10300_cpupic_mask,
- .irq_mask_ack = mn10300_cpupic_mask,
- .irq_unmask = mn10300_cpupic_unmask_clear,
-#ifdef CONFIG_SMP
- .irq_set_affinity = mn10300_cpupic_setaffinity,
-#endif
-};
-
-/*
- * MN10300 PIC edge-triggered IRQ handling.
- *
- * We use the latch clearing function of the PIC as the 'ACK' function.
- */
-static struct irq_chip mn10300_cpu_pic_edge = {
- .name = "cpu_e",
- .irq_disable = mn10300_cpupic_mask,
- .irq_enable = mn10300_cpupic_unmask,
- .irq_ack = mn10300_cpupic_ack,
- .irq_mask = mn10300_cpupic_mask,
- .irq_mask_ack = mn10300_cpupic_mask_ack,
- .irq_unmask = mn10300_cpupic_unmask,
-#ifdef CONFIG_SMP
- .irq_set_affinity = mn10300_cpupic_setaffinity,
-#endif
-};
-
-/*
- * 'what should we do if we get a hw irq event on an illegal vector'.
- * each architecture has to answer this themselves.
- */
-void ack_bad_irq(int irq)
-{
- printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
-}
-
-/*
- * change the level at which an IRQ executes
- * - must not be called whilst interrupts are being processed!
- */
-void set_intr_level(int irq, u16 level)
-{
- BUG_ON(in_interrupt());
-
- __mask_and_set_icr(irq, GxICR_ENABLE, level);
-}
-
-/*
- * mark an interrupt to be ACK'd after interrupt handlers have been run rather
- * than before
- */
-void mn10300_set_lateack_irq_type(int irq)
-{
- irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level,
- handle_level_irq);
-}
-
-/*
- * initialise the interrupt system
- */
-void __init init_IRQ(void)
-{
- int irq;
-
- for (irq = 0; irq < NR_IRQS; irq++)
- if (irq_get_chip(irq) == &no_irq_chip)
- /* due to the PIC latching interrupt requests, even
- * when the IRQ is disabled, IRQ_PENDING is superfluous
- * and we can use handle_level_irq() for edge-triggered
- * interrupts */
- irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge,
- handle_level_irq);
-
- unit_init_IRQ();
-}
-
-/*
- * handle normal device IRQs
- */
-asmlinkage void do_IRQ(void)
-{
- unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw;
- unsigned int cpu_id = smp_processor_id();
- int irq;
-
- sp = current_stack_pointer();
- BUG_ON(sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN);
-
- /* make sure local_irq_enable() doesn't muck up the interrupt priority
- * setting in EPSW */
- old_irq_enabled_epsw = __mn10300_irq_enabled_epsw[cpu_id];
- local_save_flags(epsw);
- __mn10300_irq_enabled_epsw[cpu_id] = EPSW_IE | (EPSW_IM & epsw);
- irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL;
-
-#ifdef CONFIG_MN10300_WD_TIMER
- __IRQ_STAT(cpu_id, __irq_count)++;
-#endif
-
- irq_enter();
-
- for (;;) {
- /* ask the interrupt controller for the next IRQ to process
- * - the result we get depends on EPSW.IM
- */
- irq = IAGR & IAGR_GN;
- if (!irq)
- break;
-
- local_irq_restore(irq_disabled_epsw);
-
- generic_handle_irq(irq >> 2);
-
- /* restore IRQ controls for IAGR access */
- local_irq_restore(epsw);
- }
-
- __mn10300_irq_enabled_epsw[cpu_id] = old_irq_enabled_epsw;
-
- irq_exit();
-}
-
-/*
- * Display interrupt management information through /proc/interrupts
- */
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
-#ifdef CONFIG_MN10300_WD_TIMER
- int j;
-
- seq_printf(p, "%*s: ", prec, "NMI");
- for (j = 0; j < NR_CPUS; j++)
- if (cpu_online(j))
- seq_printf(p, "%10u ", nmi_count(j));
- seq_putc(p, '\n');
-#endif
-
- seq_printf(p, "%*s: ", prec, "ERR");
- seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
- return 0;
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-void migrate_irqs(void)
-{
- int irq;
- unsigned int self, new;
- unsigned long flags;
-
- self = smp_processor_id();
- for (irq = 0; irq < NR_IRQS; irq++) {
- struct irq_data *data = irq_get_irq_data(irq);
- struct cpumask *mask = irq_data_get_affinity_mask(data);
-
- if (irqd_is_per_cpu(data))
- continue;
-
- if (cpumask_test_cpu(self, mask) &&
- !cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) {
- int cpu_id;
- cpu_id = cpumask_first(cpu_online_mask);
- cpumask_set_cpu(cpu_id, mask);
- }
- /* We need to operate irq_affinity_online atomically. */
- arch_local_cli_save(flags);
- if (irq_affinity_online[irq] == self) {
- u16 x, tmp;
-
- x = GxICR(irq);
- GxICR(irq) = x & GxICR_LEVEL;
- tmp = GxICR(irq);
-
- new = cpumask_any_and(mask, cpu_online_mask);
- irq_affinity_online[irq] = new;
-
- CROSS_GxICR(irq, new) =
- (x & GxICR_LEVEL) | GxICR_DETECT;
- tmp = CROSS_GxICR(irq, new);
-
- x &= GxICR_LEVEL | GxICR_ENABLE;
- if (GxICR(irq) & GxICR_REQUEST)
- x |= GxICR_REQUEST | GxICR_DETECT;
- CROSS_GxICR(irq, new) = x;
- tmp = CROSS_GxICR(irq, new);
- }
- arch_local_irq_restore(flags);
- }
-}
-#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mn10300/kernel/kgdb.c b/arch/mn10300/kernel/kgdb.c
deleted file mode 100644
index 2d7986c386fe..000000000000
--- a/arch/mn10300/kernel/kgdb.c
+++ /dev/null
@@ -1,502 +0,0 @@
-/* kgdb support for MN10300
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/slab.h>
-#include <linux/ptrace.h>
-#include <linux/kgdb.h>
-#include <linux/uaccess.h>
-#include <unit/leds.h>
-#include <unit/serial.h>
-#include <asm/debugger.h>
-#include <asm/serial-regs.h>
-#include "internal.h"
-
-/*
- * Software single-stepping breakpoint save (used by __switch_to())
- */
-static struct thread_info *kgdb_sstep_thread;
-u8 *kgdb_sstep_bp_addr[2];
-u8 kgdb_sstep_bp[2];
-
-/*
- * Copy kernel exception frame registers to the GDB register file
- */
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- unsigned long ssp = (unsigned long) (regs + 1);
-
- gdb_regs[GDB_FR_D0] = regs->d0;
- gdb_regs[GDB_FR_D1] = regs->d1;
- gdb_regs[GDB_FR_D2] = regs->d2;
- gdb_regs[GDB_FR_D3] = regs->d3;
- gdb_regs[GDB_FR_A0] = regs->a0;
- gdb_regs[GDB_FR_A1] = regs->a1;
- gdb_regs[GDB_FR_A2] = regs->a2;
- gdb_regs[GDB_FR_A3] = regs->a3;
- gdb_regs[GDB_FR_SP] = (regs->epsw & EPSW_nSL) ? regs->sp : ssp;
- gdb_regs[GDB_FR_PC] = regs->pc;
- gdb_regs[GDB_FR_MDR] = regs->mdr;
- gdb_regs[GDB_FR_EPSW] = regs->epsw;
- gdb_regs[GDB_FR_LIR] = regs->lir;
- gdb_regs[GDB_FR_LAR] = regs->lar;
- gdb_regs[GDB_FR_MDRQ] = regs->mdrq;
- gdb_regs[GDB_FR_E0] = regs->e0;
- gdb_regs[GDB_FR_E1] = regs->e1;
- gdb_regs[GDB_FR_E2] = regs->e2;
- gdb_regs[GDB_FR_E3] = regs->e3;
- gdb_regs[GDB_FR_E4] = regs->e4;
- gdb_regs[GDB_FR_E5] = regs->e5;
- gdb_regs[GDB_FR_E6] = regs->e6;
- gdb_regs[GDB_FR_E7] = regs->e7;
- gdb_regs[GDB_FR_SSP] = ssp;
- gdb_regs[GDB_FR_MSP] = 0;
- gdb_regs[GDB_FR_USP] = regs->sp;
- gdb_regs[GDB_FR_MCRH] = regs->mcrh;
- gdb_regs[GDB_FR_MCRL] = regs->mcrl;
- gdb_regs[GDB_FR_MCVF] = regs->mcvf;
- gdb_regs[GDB_FR_DUMMY0] = 0;
- gdb_regs[GDB_FR_DUMMY1] = 0;
- gdb_regs[GDB_FR_FS0] = 0;
-}
-
-/*
- * Extracts kernel SP/PC values understandable by gdb from the values
- * saved by switch_to().
- */
-void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
-{
- gdb_regs[GDB_FR_SSP] = p->thread.sp;
- gdb_regs[GDB_FR_PC] = p->thread.pc;
- gdb_regs[GDB_FR_A3] = p->thread.a3;
- gdb_regs[GDB_FR_USP] = p->thread.usp;
- gdb_regs[GDB_FR_FPCR] = p->thread.fpu_state.fpcr;
-}
-
-/*
- * Fill kernel exception frame registers from the GDB register file
- */
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
- regs->d0 = gdb_regs[GDB_FR_D0];
- regs->d1 = gdb_regs[GDB_FR_D1];
- regs->d2 = gdb_regs[GDB_FR_D2];
- regs->d3 = gdb_regs[GDB_FR_D3];
- regs->a0 = gdb_regs[GDB_FR_A0];
- regs->a1 = gdb_regs[GDB_FR_A1];
- regs->a2 = gdb_regs[GDB_FR_A2];
- regs->a3 = gdb_regs[GDB_FR_A3];
- regs->sp = gdb_regs[GDB_FR_SP];
- regs->pc = gdb_regs[GDB_FR_PC];
- regs->mdr = gdb_regs[GDB_FR_MDR];
- regs->epsw = gdb_regs[GDB_FR_EPSW];
- regs->lir = gdb_regs[GDB_FR_LIR];
- regs->lar = gdb_regs[GDB_FR_LAR];
- regs->mdrq = gdb_regs[GDB_FR_MDRQ];
- regs->e0 = gdb_regs[GDB_FR_E0];
- regs->e1 = gdb_regs[GDB_FR_E1];
- regs->e2 = gdb_regs[GDB_FR_E2];
- regs->e3 = gdb_regs[GDB_FR_E3];
- regs->e4 = gdb_regs[GDB_FR_E4];
- regs->e5 = gdb_regs[GDB_FR_E5];
- regs->e6 = gdb_regs[GDB_FR_E6];
- regs->e7 = gdb_regs[GDB_FR_E7];
- regs->sp = gdb_regs[GDB_FR_SSP];
- /* gdb_regs[GDB_FR_MSP]; */
- // regs->usp = gdb_regs[GDB_FR_USP];
- regs->mcrh = gdb_regs[GDB_FR_MCRH];
- regs->mcrl = gdb_regs[GDB_FR_MCRL];
- regs->mcvf = gdb_regs[GDB_FR_MCVF];
- /* gdb_regs[GDB_FR_DUMMY0]; */
- /* gdb_regs[GDB_FR_DUMMY1]; */
-
- // regs->fpcr = gdb_regs[GDB_FR_FPCR];
- // regs->fs0 = gdb_regs[GDB_FR_FS0];
-}
-
-struct kgdb_arch arch_kgdb_ops = {
- .gdb_bpt_instr = { 0xff },
- .flags = KGDB_HW_BREAKPOINT,
-};
-
-static const unsigned char mn10300_kgdb_insn_sizes[256] =
-{
- /* 1 2 3 4 5 6 7 8 9 a b c d e f */
- 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */
- 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */
- 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */
- 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */
- 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */
- 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */
-};
-
-/*
- * Attempt to emulate single stepping by means of breakpoint instructions.
- * Although there is a single-step trace flag in EPSW, its use is not
- * sufficiently documented and is only intended for use with the JTAG debugger.
- */
-static int kgdb_arch_do_singlestep(struct pt_regs *regs)
-{
- unsigned long arg;
- unsigned size;
- u8 *pc = (u8 *)regs->pc, *sp = (u8 *)(regs + 1), cur;
- u8 *x = NULL, *y = NULL;
- int ret;
-
- ret = probe_kernel_read(&cur, pc, 1);
- if (ret < 0)
- return ret;
-
- size = mn10300_kgdb_insn_sizes[cur];
- if (size > 0) {
- x = pc + size;
- goto set_x;
- }
-
- switch (cur) {
- /* Bxx (d8,PC) */
- case 0xc0 ... 0xca:
- ret = probe_kernel_read(&arg, pc + 1, 1);
- if (ret < 0)
- return ret;
- x = pc + 2;
- if (arg >= 0 && arg <= 2)
- goto set_x;
- y = pc + (s8)arg;
- goto set_x_and_y;
-
- /* LXX (d8,PC) */
- case 0xd0 ... 0xda:
- x = pc + 1;
- if (regs->pc == regs->lar)
- goto set_x;
- y = (u8 *)regs->lar;
- goto set_x_and_y;
-
- /* SETLB - loads the next four bytes into the LIR register
- * (which mustn't include a breakpoint instruction) */
- case 0xdb:
- x = pc + 5;
- goto set_x;
-
- /* JMP (d16,PC) or CALL (d16,PC) */
- case 0xcc:
- case 0xcd:
- ret = probe_kernel_read(&arg, pc + 1, 2);
- if (ret < 0)
- return ret;
- x = pc + (s16)arg;
- goto set_x;
-
- /* JMP (d32,PC) or CALL (d32,PC) */
- case 0xdc:
- case 0xdd:
- ret = probe_kernel_read(&arg, pc + 1, 4);
- if (ret < 0)
- return ret;
- x = pc + (s32)arg;
- goto set_x;
-
- /* RETF */
- case 0xde:
- x = (u8 *)regs->mdr;
- goto set_x;
-
- /* RET */
- case 0xdf:
- ret = probe_kernel_read(&arg, pc + 2, 1);
- if (ret < 0)
- return ret;
- ret = probe_kernel_read(&x, sp + (s8)arg, 4);
- if (ret < 0)
- return ret;
- goto set_x;
-
- case 0xf0:
- ret = probe_kernel_read(&cur, pc + 1, 1);
- if (ret < 0)
- return ret;
-
- if (cur >= 0xf0 && cur <= 0xf7) {
- /* JMP (An) / CALLS (An) */
- switch (cur & 3) {
- case 0: x = (u8 *)regs->a0; break;
- case 1: x = (u8 *)regs->a1; break;
- case 2: x = (u8 *)regs->a2; break;
- case 3: x = (u8 *)regs->a3; break;
- }
- goto set_x;
- } else if (cur == 0xfc) {
- /* RETS */
- ret = probe_kernel_read(&x, sp, 4);
- if (ret < 0)
- return ret;
- goto set_x;
- } else if (cur == 0xfd) {
- /* RTI */
- ret = probe_kernel_read(&x, sp + 4, 4);
- if (ret < 0)
- return ret;
- goto set_x;
- } else {
- x = pc + 2;
- goto set_x;
- }
- break;
-
- /* potential 3-byte conditional branches */
- case 0xf8:
- ret = probe_kernel_read(&cur, pc + 1, 1);
- if (ret < 0)
- return ret;
- x = pc + 3;
-
- if (cur >= 0xe8 && cur <= 0xeb) {
- ret = probe_kernel_read(&arg, pc + 2, 1);
- if (ret < 0)
- return ret;
- if (arg >= 0 && arg <= 3)
- goto set_x;
- y = pc + (s8)arg;
- goto set_x_and_y;
- }
- goto set_x;
-
- case 0xfa:
- ret = probe_kernel_read(&cur, pc + 1, 1);
- if (ret < 0)
- return ret;
-
- if (cur == 0xff) {
- /* CALLS (d16,PC) */
- ret = probe_kernel_read(&arg, pc + 2, 2);
- if (ret < 0)
- return ret;
- x = pc + (s16)arg;
- goto set_x;
- }
-
- x = pc + 4;
- goto set_x;
-
- case 0xfc:
- ret = probe_kernel_read(&cur, pc + 1, 1);
- if (ret < 0)
- return ret;
-
- if (cur == 0xff) {
- /* CALLS (d32,PC) */
- ret = probe_kernel_read(&arg, pc + 2, 4);
- if (ret < 0)
- return ret;
- x = pc + (s32)arg;
- goto set_x;
- }
-
- x = pc + 6;
- goto set_x;
- }
-
- return 0;
-
-set_x:
- kgdb_sstep_bp_addr[0] = x;
- kgdb_sstep_bp_addr[1] = NULL;
- ret = probe_kernel_read(&kgdb_sstep_bp[0], x, 1);
- if (ret < 0)
- return ret;
- ret = probe_kernel_write(x, &arch_kgdb_ops.gdb_bpt_instr, 1);
- if (ret < 0)
- return ret;
- kgdb_sstep_thread = current_thread_info();
- debugger_local_cache_flushinv_one(x);
- return ret;
-
-set_x_and_y:
- kgdb_sstep_bp_addr[0] = x;
- kgdb_sstep_bp_addr[1] = y;
- ret = probe_kernel_read(&kgdb_sstep_bp[0], x, 1);
- if (ret < 0)
- return ret;
- ret = probe_kernel_read(&kgdb_sstep_bp[1], y, 1);
- if (ret < 0)
- return ret;
- ret = probe_kernel_write(x, &arch_kgdb_ops.gdb_bpt_instr, 1);
- if (ret < 0)
- return ret;
- ret = probe_kernel_write(y, &arch_kgdb_ops.gdb_bpt_instr, 1);
- if (ret < 0) {
- probe_kernel_write(kgdb_sstep_bp_addr[0],
- &kgdb_sstep_bp[0], 1);
- } else {
- kgdb_sstep_thread = current_thread_info();
- }
- debugger_local_cache_flushinv_one(x);
- debugger_local_cache_flushinv_one(y);
- return ret;
-}
-
-/*
- * Remove emplaced single-step breakpoints, returning true if we hit one of
- * them.
- */
-static bool kgdb_arch_undo_singlestep(struct pt_regs *regs)
-{
- bool hit = false;
- u8 *x = kgdb_sstep_bp_addr[0], *y = kgdb_sstep_bp_addr[1];
- u8 opcode;
-
- if (kgdb_sstep_thread == current_thread_info()) {
- if (x) {
- if (x == (u8 *)regs->pc)
- hit = true;
- if (probe_kernel_read(&opcode, x,
- 1) < 0 ||
- opcode != 0xff)
- BUG();
- probe_kernel_write(x, &kgdb_sstep_bp[0], 1);
- debugger_local_cache_flushinv_one(x);
- }
- if (y) {
- if (y == (u8 *)regs->pc)
- hit = true;
- if (probe_kernel_read(&opcode, y,
- 1) < 0 ||
- opcode != 0xff)
- BUG();
- probe_kernel_write(y, &kgdb_sstep_bp[1], 1);
- debugger_local_cache_flushinv_one(y);
- }
- }
-
- kgdb_sstep_bp_addr[0] = NULL;
- kgdb_sstep_bp_addr[1] = NULL;
- kgdb_sstep_thread = NULL;
- return hit;
-}
-
-/*
- * Catch a single-step-pending thread being deleted and make sure the global
- * single-step state is cleared. At this point the breakpoints should have
- * been removed by __switch_to().
- */
-void arch_release_thread_stack(unsigned long *stack)
-{
- struct thread_info *ti = (void *)stack;
- if (kgdb_sstep_thread == ti) {
- kgdb_sstep_thread = NULL;
-
- /* However, we may now be running in degraded mode, with most
- * of the CPUs disabled until such a time as KGDB is reentered,
- * so force immediate reentry */
- kgdb_breakpoint();
- }
-}
-
-/*
- * Handle unknown packets and [CcsDk] packets
- * - at this point breakpoints have been installed
- */
-int kgdb_arch_handle_exception(int vector, int signo, int err_code,
- char *remcom_in_buffer, char *remcom_out_buffer,
- struct pt_regs *regs)
-{
- long addr;
- char *ptr;
-
- switch (remcom_in_buffer[0]) {
- case 'c':
- case 's':
- /* try to read optional parameter, pc unchanged if no parm */
- ptr = &remcom_in_buffer[1];
- if (kgdb_hex2long(&ptr, &addr))
- regs->pc = addr;
- case 'D':
- case 'k':
- atomic_set(&kgdb_cpu_doing_single_step, -1);
-
- if (remcom_in_buffer[0] == 's') {
- kgdb_arch_do_singlestep(regs);
- kgdb_single_step = 1;
- atomic_set(&kgdb_cpu_doing_single_step,
- raw_smp_processor_id());
- }
- return 0;
- }
- return -1; /* this means that we do not want to exit from the handler */
-}
-
-/*
- * Handle event interception
- * - returns 0 if the exception should be skipped, -ERROR otherwise.
- */
-int debugger_intercept(enum exception_code excep, int signo, int si_code,
- struct pt_regs *regs)
-{
- int ret;
-
- if (kgdb_arch_undo_singlestep(regs)) {
- excep = EXCEP_TRAP;
- signo = SIGTRAP;
- si_code = TRAP_TRACE;
- }
-
- ret = kgdb_handle_exception(excep, signo, si_code, regs);
-
- debugger_local_cache_flushinv();
-
- return ret;
-}
-
-/*
- * Determine if we've hit a debugger special breakpoint
- */
-int at_debugger_breakpoint(struct pt_regs *regs)
-{
- return regs->pc == (unsigned long)&__arch_kgdb_breakpoint;
-}
-
-/*
- * Initialise kgdb
- */
-int kgdb_arch_init(void)
-{
- return 0;
-}
-
-/*
- * Do something, perhaps, but don't know what.
- */
-void kgdb_arch_exit(void)
-{
-}
-
-#ifdef CONFIG_SMP
-void debugger_nmi_interrupt(struct pt_regs *regs, enum exception_code code)
-{
- kgdb_nmicallback(arch_smp_processor_id(), regs);
- debugger_local_cache_flushinv();
-}
-
-void kgdb_roundup_cpus(unsigned long flags)
-{
- smp_jump_to_debugger();
-}
-#endif
diff --git a/arch/mn10300/kernel/kprobes.c b/arch/mn10300/kernel/kprobes.c
deleted file mode 100644
index 0311a7fcea16..000000000000
--- a/arch/mn10300/kernel/kprobes.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/* MN10300 Kernel probes implementation
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by Mark Salter (msalter@redhat.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public Licence as published by
- * the Free Software Foundation; either version 2 of the Licence, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public Licence for more details.
- *
- * You should have received a copy of the GNU General Public Licence
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-#include <linux/kprobes.h>
-#include <linux/ptrace.h>
-#include <linux/spinlock.h>
-#include <linux/preempt.h>
-#include <linux/kdebug.h>
-#include <asm/cacheflush.h>
-
-struct kretprobe_blackpoint kretprobe_blacklist[] = { { NULL, NULL } };
-const int kretprobe_blacklist_size = ARRAY_SIZE(kretprobe_blacklist);
-
-/* kprobe_status settings */
-#define KPROBE_HIT_ACTIVE 0x00000001
-#define KPROBE_HIT_SS 0x00000002
-
-static struct kprobe *cur_kprobe;
-static unsigned long cur_kprobe_orig_pc;
-static unsigned long cur_kprobe_next_pc;
-static int cur_kprobe_ss_flags;
-static unsigned long kprobe_status;
-static kprobe_opcode_t cur_kprobe_ss_buf[MAX_INSN_SIZE + 2];
-static unsigned long cur_kprobe_bp_addr;
-
-DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
-
-
-/* singlestep flag bits */
-#define SINGLESTEP_BRANCH 1
-#define SINGLESTEP_PCREL 2
-
-#define READ_BYTE(p, valp) \
- do { *(u8 *)(valp) = *(u8 *)(p); } while (0)
-
-#define READ_WORD16(p, valp) \
- do { \
- READ_BYTE((p), (valp)); \
- READ_BYTE((u8 *)(p) + 1, (u8 *)(valp) + 1); \
- } while (0)
-
-#define READ_WORD32(p, valp) \
- do { \
- READ_BYTE((p), (valp)); \
- READ_BYTE((u8 *)(p) + 1, (u8 *)(valp) + 1); \
- READ_BYTE((u8 *)(p) + 2, (u8 *)(valp) + 2); \
- READ_BYTE((u8 *)(p) + 3, (u8 *)(valp) + 3); \
- } while (0)
-
-
-static const u8 mn10300_insn_sizes[256] =
-{
- /* 1 2 3 4 5 6 7 8 9 a b c d e f */
- 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */
- 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */
- 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */
- 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */
- 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */
- 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */
- 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */
-};
-
-#define LT (1 << 0)
-#define GT (1 << 1)
-#define GE (1 << 2)
-#define LE (1 << 3)
-#define CS (1 << 4)
-#define HI (1 << 5)
-#define CC (1 << 6)
-#define LS (1 << 7)
-#define EQ (1 << 8)
-#define NE (1 << 9)
-#define RA (1 << 10)
-#define VC (1 << 11)
-#define VS (1 << 12)
-#define NC (1 << 13)
-#define NS (1 << 14)
-
-static const u16 cond_table[] = {
- /* V C N Z */
- /* 0 0 0 0 */ (NE | NC | CC | VC | GE | GT | HI),
- /* 0 0 0 1 */ (EQ | NC | CC | VC | GE | LE | LS),
- /* 0 0 1 0 */ (NE | NS | CC | VC | LT | LE | HI),
- /* 0 0 1 1 */ (EQ | NS | CC | VC | LT | LE | LS),
- /* 0 1 0 0 */ (NE | NC | CS | VC | GE | GT | LS),
- /* 0 1 0 1 */ (EQ | NC | CS | VC | GE | LE | LS),
- /* 0 1 1 0 */ (NE | NS | CS | VC | LT | LE | LS),
- /* 0 1 1 1 */ (EQ | NS | CS | VC | LT | LE | LS),
- /* 1 0 0 0 */ (NE | NC | CC | VS | LT | LE | HI),
- /* 1 0 0 1 */ (EQ | NC | CC | VS | LT | LE | LS),
- /* 1 0 1 0 */ (NE | NS | CC | VS | GE | GT | HI),
- /* 1 0 1 1 */ (EQ | NS | CC | VS | GE | LE | LS),
- /* 1 1 0 0 */ (NE | NC | CS | VS | LT | LE | LS),
- /* 1 1 0 1 */ (EQ | NC | CS | VS | LT | LE | LS),
- /* 1 1 1 0 */ (NE | NS | CS | VS | GE | GT | LS),
- /* 1 1 1 1 */ (EQ | NS | CS | VS | GE | LE | LS),
-};
-
-/*
- * Calculate what the PC will be after executing next instruction
- */
-static unsigned find_nextpc(struct pt_regs *regs, int *flags)
-{
- unsigned size;
- s8 x8;
- s16 x16;
- s32 x32;
- u8 opc, *pc, *sp, *next;
-
- next = 0;
- *flags = SINGLESTEP_PCREL;
-
- pc = (u8 *) regs->pc;
- sp = (u8 *) (regs + 1);
- opc = *pc;
-
- size = mn10300_insn_sizes[opc];
- if (size > 0) {
- next = pc + size;
- } else {
- switch (opc) {
- /* Bxx (d8,PC) */
- case 0xc0 ... 0xca:
- x8 = 2;
- if (cond_table[regs->epsw & 0xf] & (1 << (opc & 0xf)))
- x8 = (s8)pc[1];
- next = pc + x8;
- *flags |= SINGLESTEP_BRANCH;
- break;
-
- /* JMP (d16,PC) or CALL (d16,PC) */
- case 0xcc:
- case 0xcd:
- READ_WORD16(pc + 1, &x16);
- next = pc + x16;
- *flags |= SINGLESTEP_BRANCH;
- break;
-
- /* JMP (d32,PC) or CALL (d32,PC) */
- case 0xdc:
- case 0xdd:
- READ_WORD32(pc + 1, &x32);
- next = pc + x32;
- *flags |= SINGLESTEP_BRANCH;
- break;
-
- /* RETF */
- case 0xde:
- next = (u8 *)regs->mdr;
- *flags &= ~SINGLESTEP_PCREL;
- *flags |= SINGLESTEP_BRANCH;
- break;
-
- /* RET */
- case 0xdf:
- sp += pc[2];
- READ_WORD32(sp, &x32);
- next = (u8 *)x32;
- *flags &= ~SINGLESTEP_PCREL;
- *flags |= SINGLESTEP_BRANCH;
- break;
-
- case 0xf0:
- next = pc + 2;
- opc = pc[1];
- if (opc >= 0xf0 && opc <= 0xf7) {
- /* JMP (An) / CALLS (An) */
- switch (opc & 3) {
- case 0:
- next = (u8 *)regs->a0;
- break;
- case 1:
- next = (u8 *)regs->a1;
- break;
- case 2:
- next = (u8 *)regs->a2;
- break;
- case 3:
- next = (u8 *)regs->a3;
- break;
- }
- *flags &= ~SINGLESTEP_PCREL;
- *flags |= SINGLESTEP_BRANCH;
- } else if (opc == 0xfc) {
- /* RETS */
- READ_WORD32(sp, &x32);
- next = (u8 *)x32;
- *flags &= ~SINGLESTEP_PCREL;
- *flags |= SINGLESTEP_BRANCH;
- } else if (opc == 0xfd) {
- /* RTI */
- READ_WORD32(sp + 4, &x32);
- next = (u8 *)x32;
- *flags &= ~SINGLESTEP_PCREL;
- *flags |= SINGLESTEP_BRANCH;
- }
- break;
-
- /* potential 3-byte conditional branches */
- case 0xf8:
- next = pc + 3;
- opc = pc[1];
- if (opc >= 0xe8 && opc <= 0xeb &&
- (cond_table[regs->epsw & 0xf] &
- (1 << ((opc & 0xf) + 3)))
- ) {
- READ_BYTE(pc+2, &x8);
- next = pc + x8;
- *flags |= SINGLESTEP_BRANCH;
- }
- break;
-
- case 0xfa:
- if (pc[1] == 0xff) {
- /* CALLS (d16,PC) */
- READ_WORD16(pc + 2, &x16);
- next = pc + x16;
- } else
- next = pc + 4;
- *flags |= SINGLESTEP_BRANCH;
- break;
-
- case 0xfc:
- x32 = 6;
- if (pc[1] == 0xff) {
- /* CALLS (d32,PC) */
- READ_WORD32(pc + 2, &x32);
- }
- next = pc + x32;
- *flags |= SINGLESTEP_BRANCH;
- break;
- /* LXX (d8,PC) */
- /* SETLB - loads the next four bytes into the LIR reg */
- case 0xd0 ... 0xda:
- case 0xdb:
- panic("Can't singlestep Lxx/SETLB\n");
- break;
- }
- }
- return (unsigned)next;
-
-}
-
-/*
- * set up out of place singlestep of some branching instructions
- */
-static unsigned __kprobes singlestep_branch_setup(struct pt_regs *regs)
-{
- u8 opc, *pc, *sp, *next;
-
- next = NULL;
- pc = (u8 *) regs->pc;
- sp = (u8 *) (regs + 1);
-
- switch (pc[0]) {
- case 0xc0 ... 0xca: /* Bxx (d8,PC) */
- case 0xcc: /* JMP (d16,PC) */
- case 0xdc: /* JMP (d32,PC) */
- case 0xf8: /* Bxx (d8,PC) 3-byte version */
- /* don't really need to do anything except cause trap */
- next = pc;
- break;
-
- case 0xcd: /* CALL (d16,PC) */
- pc[1] = 5;
- pc[2] = 0;
- next = pc + 5;
- break;
-
- case 0xdd: /* CALL (d32,PC) */
- pc[1] = 7;
- pc[2] = 0;
- pc[3] = 0;
- pc[4] = 0;
- next = pc + 7;
- break;
-
- case 0xde: /* RETF */
- next = pc + 3;
- regs->mdr = (unsigned) next;
- break;
-
- case 0xdf: /* RET */
- sp += pc[2];
- next = pc + 3;
- *(unsigned *)sp = (unsigned) next;
- break;
-
- case 0xf0:
- next = pc + 2;
- opc = pc[1];
- if (opc >= 0xf0 && opc <= 0xf3) {
- /* CALLS (An) */
- /* use CALLS (d16,PC) to avoid mucking with An */
- pc[0] = 0xfa;
- pc[1] = 0xff;
- pc[2] = 4;
- pc[3] = 0;
- next = pc + 4;
- } else if (opc >= 0xf4 && opc <= 0xf7) {
- /* JMP (An) */
- next = pc;
- } else if (opc == 0xfc) {
- /* RETS */
- next = pc + 2;
- *(unsigned *) sp = (unsigned) next;
- } else if (opc == 0xfd) {
- /* RTI */
- next = pc + 2;
- *(unsigned *)(sp + 4) = (unsigned) next;
- }
- break;
-
- case 0xfa: /* CALLS (d16,PC) */
- pc[2] = 4;
- pc[3] = 0;
- next = pc + 4;
- break;
-
- case 0xfc: /* CALLS (d32,PC) */
- pc[2] = 6;
- pc[3] = 0;
- pc[4] = 0;
- pc[5] = 0;
- next = pc + 6;
- break;
-
- case 0xd0 ... 0xda: /* LXX (d8,PC) */
- case 0xdb: /* SETLB */
- panic("Can't singlestep Lxx/SETLB\n");
- }
-
- return (unsigned) next;
-}
-
-int __kprobes arch_prepare_kprobe(struct kprobe *p)
-{
- return 0;
-}
-
-void __kprobes arch_copy_kprobe(struct kprobe *p)
-{
- memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE);
-}
-
-void __kprobes arch_arm_kprobe(struct kprobe *p)
-{
- *p->addr = BREAKPOINT_INSTRUCTION;
- flush_icache_range((unsigned long) p->addr,
- (unsigned long) p->addr + sizeof(kprobe_opcode_t));
-}
-
-void __kprobes arch_disarm_kprobe(struct kprobe *p)
-{
-#ifndef CONFIG_MN10300_CACHE_SNOOP
- mn10300_dcache_flush();
- mn10300_icache_inv();
-#endif
-}
-
-void arch_remove_kprobe(struct kprobe *p)
-{
-}
-
-static inline
-void __kprobes disarm_kprobe(struct kprobe *p, struct pt_regs *regs)
-{
- *p->addr = p->opcode;
- regs->pc = (unsigned long) p->addr;
-#ifndef CONFIG_MN10300_CACHE_SNOOP
- mn10300_dcache_flush();
- mn10300_icache_inv();
-#endif
-}
-
-static inline
-void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
-{
- unsigned long nextpc;
-
- cur_kprobe_orig_pc = regs->pc;
- memcpy(cur_kprobe_ss_buf, &p->ainsn.insn[0], MAX_INSN_SIZE);
- regs->pc = (unsigned long) cur_kprobe_ss_buf;
-
- nextpc = find_nextpc(regs, &cur_kprobe_ss_flags);
- if (cur_kprobe_ss_flags & SINGLESTEP_PCREL)
- cur_kprobe_next_pc = cur_kprobe_orig_pc + (nextpc - regs->pc);
- else
- cur_kprobe_next_pc = nextpc;
-
- /* branching instructions need special handling */
- if (cur_kprobe_ss_flags & SINGLESTEP_BRANCH)
- nextpc = singlestep_branch_setup(regs);
-
- cur_kprobe_bp_addr = nextpc;
-
- *(u8 *) nextpc = BREAKPOINT_INSTRUCTION;
- mn10300_dcache_flush_range2((unsigned) cur_kprobe_ss_buf,
- sizeof(cur_kprobe_ss_buf));
- mn10300_icache_inv();
-}
-
-static inline int __kprobes kprobe_handler(struct pt_regs *regs)
-{
- struct kprobe *p;
- int ret = 0;
- unsigned int *addr = (unsigned int *) regs->pc;
-
- /* We're in an interrupt, but this is clear and BUG()-safe. */
- preempt_disable();
-
- /* Check we're not actually recursing */
- if (kprobe_running()) {
- /* We *are* holding lock here, so this is safe.
- Disarm the probe we just hit, and ignore it. */
- p = get_kprobe(addr);
- if (p) {
- disarm_kprobe(p, regs);
- ret = 1;
- } else {
- p = cur_kprobe;
- if (p->break_handler && p->break_handler(p, regs))
- goto ss_probe;
- }
- /* If it's not ours, can't be delete race, (we hold lock). */
- goto no_kprobe;
- }
-
- p = get_kprobe(addr);
- if (!p) {
- if (*addr != BREAKPOINT_INSTRUCTION) {
- /* The breakpoint instruction was removed right after
- * we hit it. Another cpu has removed either a
- * probepoint or a debugger breakpoint at this address.
- * In either case, no further handling of this
- * interrupt is appropriate.
- */
- ret = 1;
- }
- /* Not one of ours: let kernel handle it */
- goto no_kprobe;
- }
-
- kprobe_status = KPROBE_HIT_ACTIVE;
- cur_kprobe = p;
- if (p->pre_handler(p, regs)) {
- /* handler has already set things up, so skip ss setup */
- return 1;
- }
-
-ss_probe:
- prepare_singlestep(p, regs);
- kprobe_status = KPROBE_HIT_SS;
- return 1;
-
-no_kprobe:
- preempt_enable_no_resched();
- return ret;
-}
-
-/*
- * Called after single-stepping. p->addr is the address of the
- * instruction whose first byte has been replaced by the "breakpoint"
- * instruction. To avoid the SMP problems that can occur when we
- * temporarily put back the original opcode to single-step, we
- * single-stepped a copy of the instruction. The address of this
- * copy is p->ainsn.insn.
- */
-static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
-{
- /* we may need to fixup regs/stack after singlestepping a call insn */
- if (cur_kprobe_ss_flags & SINGLESTEP_BRANCH) {
- regs->pc = cur_kprobe_orig_pc;
- switch (p->ainsn.insn[0]) {
- case 0xcd: /* CALL (d16,PC) */
- *(unsigned *) regs->sp = regs->mdr = regs->pc + 5;
- break;
- case 0xdd: /* CALL (d32,PC) */
- /* fixup mdr and return address on stack */
- *(unsigned *) regs->sp = regs->mdr = regs->pc + 7;
- break;
- case 0xf0:
- if (p->ainsn.insn[1] >= 0xf0 &&
- p->ainsn.insn[1] <= 0xf3) {
- /* CALLS (An) */
- /* fixup MDR and return address on stack */
- regs->mdr = regs->pc + 2;
- *(unsigned *) regs->sp = regs->mdr;
- }
- break;
-
- case 0xfa: /* CALLS (d16,PC) */
- /* fixup MDR and return address on stack */
- *(unsigned *) regs->sp = regs->mdr = regs->pc + 4;
- break;
-
- case 0xfc: /* CALLS (d32,PC) */
- /* fixup MDR and return address on stack */
- *(unsigned *) regs->sp = regs->mdr = regs->pc + 6;
- break;
- }
- }
-
- regs->pc = cur_kprobe_next_pc;
- cur_kprobe_bp_addr = 0;
-}
-
-static inline int __kprobes post_kprobe_handler(struct pt_regs *regs)
-{
- if (!kprobe_running())
- return 0;
-
- if (cur_kprobe->post_handler)
- cur_kprobe->post_handler(cur_kprobe, regs, 0);
-
- resume_execution(cur_kprobe, regs);
- reset_current_kprobe();
- preempt_enable_no_resched();
- return 1;
-}
-
-/* Interrupts disabled, kprobe_lock held. */
-static inline
-int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
-{
- if (cur_kprobe->fault_handler &&
- cur_kprobe->fault_handler(cur_kprobe, regs, trapnr))
- return 1;
-
- if (kprobe_status & KPROBE_HIT_SS) {
- resume_execution(cur_kprobe, regs);
- reset_current_kprobe();
- preempt_enable_no_resched();
- }
- return 0;
-}
-
-/*
- * Wrapper routine to for handling exceptions.
- */
-int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
- unsigned long val, void *data)
-{
- struct die_args *args = data;
-
- switch (val) {
- case DIE_BREAKPOINT:
- if (cur_kprobe_bp_addr != args->regs->pc) {
- if (kprobe_handler(args->regs))
- return NOTIFY_STOP;
- } else {
- if (post_kprobe_handler(args->regs))
- return NOTIFY_STOP;
- }
- break;
- case DIE_GPF:
- if (kprobe_running() &&
- kprobe_fault_handler(args->regs, args->trapnr))
- return NOTIFY_STOP;
- break;
- default:
- break;
- }
- return NOTIFY_DONE;
-}
-
-/* Jprobes support. */
-static struct pt_regs jprobe_saved_regs;
-static struct pt_regs *jprobe_saved_regs_location;
-static kprobe_opcode_t jprobe_saved_stack[MAX_STACK_SIZE];
-
-int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
-{
- struct jprobe *jp = container_of(p, struct jprobe, kp);
-
- jprobe_saved_regs_location = regs;
- memcpy(&jprobe_saved_regs, regs, sizeof(struct pt_regs));
-
- /* Save a whole stack frame, this gets arguments
- * pushed onto the stack after using up all the
- * arg registers.
- */
- memcpy(&jprobe_saved_stack, regs + 1, sizeof(jprobe_saved_stack));
-
- /* setup return addr to the jprobe handler routine */
- regs->pc = (unsigned long) jp->entry;
- return 1;
-}
-
-void __kprobes jprobe_return(void)
-{
- void *orig_sp = jprobe_saved_regs_location + 1;
-
- preempt_enable_no_resched();
- asm volatile(" mov %0,sp\n"
- ".globl jprobe_return_bp_addr\n"
- "jprobe_return_bp_addr:\n\t"
- " .byte 0xff\n"
- : : "d" (orig_sp));
-}
-
-extern void jprobe_return_bp_addr(void);
-
-int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
-{
- u8 *addr = (u8 *) regs->pc;
-
- if (addr == (u8 *) jprobe_return_bp_addr) {
- if (jprobe_saved_regs_location != regs) {
- printk(KERN_ERR"JPROBE:"
- " Current regs (%p) does not match saved regs"
- " (%p).\n",
- regs, jprobe_saved_regs_location);
- BUG();
- }
-
- /* Restore old register state.
- */
- memcpy(regs, &jprobe_saved_regs, sizeof(struct pt_regs));
-
- memcpy(regs + 1, &jprobe_saved_stack,
- sizeof(jprobe_saved_stack));
- return 1;
- }
- return 0;
-}
-
-int __init arch_init_kprobes(void)
-{
- return 0;
-}
diff --git a/arch/mn10300/kernel/mn10300-debug.c b/arch/mn10300/kernel/mn10300-debug.c
deleted file mode 100644
index bd8196478cbc..000000000000
--- a/arch/mn10300/kernel/mn10300-debug.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Debugging stuff for the MN10300-based processors
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <asm/serial-regs.h>
-
-#undef MN10300_CONSOLE_ON_SERIO
-
-/*
- * write a string directly through one of the serial ports on-board the MN10300
- */
-#ifdef MN10300_CONSOLE_ON_SERIO
-void debug_to_serial_mnser(const char *p, int n)
-{
- char ch;
-
- for (; n > 0; n--) {
- ch = *p++;
-
-#if MN10300_CONSOLE_ON_SERIO == 0
- while (SC0STR & (SC01STR_TBF)) continue;
- SC0TXB = ch;
- while (SC0STR & (SC01STR_TBF)) continue;
- if (ch == 0x0a) {
- SC0TXB = 0x0d;
- while (SC0STR & (SC01STR_TBF)) continue;
- }
-
-#elif MN10300_CONSOLE_ON_SERIO == 1
- while (SC1STR & (SC01STR_TBF)) continue;
- SC1TXB = ch;
- while (SC1STR & (SC01STR_TBF)) continue;
- if (ch == 0x0a) {
- SC1TXB = 0x0d;
- while (SC1STR & (SC01STR_TBF)) continue;
- }
-
-#elif MN10300_CONSOLE_ON_SERIO == 2
- while (SC2STR & (SC2STR_TBF)) continue;
- SC2TXB = ch;
- while (SC2STR & (SC2STR_TBF)) continue;
- if (ch == 0x0a) {
- SC2TXB = 0x0d;
- while (SC2STR & (SC2STR_TBF)) continue;
- }
-
-#endif
- }
-}
-#endif
-
diff --git a/arch/mn10300/kernel/mn10300-serial-low.S b/arch/mn10300/kernel/mn10300-serial-low.S
deleted file mode 100644
index b95e76caf4fa..000000000000
--- a/arch/mn10300/kernel/mn10300-serial-low.S
+++ /dev/null
@@ -1,194 +0,0 @@
-###############################################################################
-#
-# Virtual DMA driver for MN10300 serial ports
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/page.h>
-#include <asm/smp.h>
-#include <asm/cpu-regs.h>
-#include <asm/frame.inc>
-#include <asm/timer-regs.h>
-#include <proc/cache.h>
-#include <unit/timex.h>
-#include "mn10300-serial.h"
-
-#define SCxCTR 0x00
-#define SCxICR 0x04
-#define SCxTXB 0x08
-#define SCxRXB 0x09
-#define SCxSTR 0x0c
-#define SCxTIM 0x0d
-
- .text
-
-###############################################################################
-#
-# serial port interrupt virtual DMA entry point
-# - intended to run at interrupt priority 1 (not affected by local_irq_disable)
-#
-###############################################################################
- .balign L1_CACHE_BYTES
-ENTRY(mn10300_serial_vdma_interrupt)
-# or EPSW_IE,psw # permit overriding by
- # debugging interrupts
- movm [d2,d3,a2,a3,exreg0],(sp)
-
- movhu (IAGR),a2 # see if which interrupt is
- # pending
- and IAGR_GN,a2
- add a2,a2
- add mn10300_serial_int_tbl,a2
-
- mov (a2+),a3
- mov (__iobase,a3),e2
- mov (a2),a2
- jmp (a2)
-
-###############################################################################
-#
-# serial port receive interrupt virtual DMA entry point
-# - intended to run at interrupt priority 1 (not affected by local_irq_disable)
-# - stores data/status byte pairs in the ring buffer
-# - induces a scheduler tick timer interrupt when done, which we then subvert
-# on entry:
-# A3 struct mn10300_serial_port *
-# E2 I/O port base
-#
-###############################################################################
-ENTRY(mn10300_serial_vdma_rx_handler)
- mov (__rx_icr,a3),e3
- mov GxICR_DETECT,d2
- movbu d2,(e3) # ACK the interrupt
- movhu (e3),d2 # flush
-
- mov (__rx_inp,a3),d3
- mov d3,a2
- add 2,d3
- and MNSC_BUFFER_SIZE-1,d3
- mov (__rx_outp,a3),d2
- cmp d3,d2
- beq mnsc_vdma_rx_overflow
-
- mov (__rx_buffer,a3),d2
- add d2,a2
- movhu (SCxSTR,e2),d2
- movbu d2,(1,a2)
- movbu (SCxRXB,e2),d2
- movbu d2,(a2)
- mov d3,(__rx_inp,a3)
- bset MNSCx_RX_AVAIL,(__intr_flags,a3)
-
-mnsc_vdma_rx_done:
- mov (__tm_icr,a3),a2
- mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2
- movhu d2,(a2) # request a slow interrupt
- movhu (a2),d2 # flush
-
- movm (sp),[d2,d3,a2,a3,exreg0]
- rti
-
-mnsc_vdma_rx_overflow:
- bset MNSCx_RX_OVERF,(__intr_flags,a3)
- bra mnsc_vdma_rx_done
-
-###############################################################################
-#
-# serial port transmit interrupt virtual DMA entry point
-# - intended to run at interrupt priority 1 (not affected by local_irq_disable)
-# - retrieves data bytes from the ring buffer and passes them to the serial port
-# - induces a scheduler tick timer interrupt when done, which we then subvert
-# A3 struct mn10300_serial_port *
-# E2 I/O port base
-#
-###############################################################################
- .balign L1_CACHE_BYTES
-ENTRY(mn10300_serial_vdma_tx_handler)
- mov (__tx_icr,a3),e3
- mov GxICR_DETECT,d2
- movbu d2,(e3) # ACK the interrupt
- movhu (e3),d2 # flush
-
- btst 0xFF,(__tx_flags,a3) # handle transmit flags
- bne mnsc_vdma_tx_flags
-
- movbu (SCxSTR,e2),d2 # don't try and transmit a char if the
- # buffer is not empty
- btst SC01STR_TBF,d2 # (may have tried to jumpstart)
- bne mnsc_vdma_tx_noint
-
- movbu (__tx_xchar,a3),d2 # handle hi-pri XON/XOFF
- or d2,d2
- bne mnsc_vdma_tx_xchar
-
- mov (__uart_state,a3),a2 # see if the TTY Tx queue has anything in it
- mov (__xmit_tail,a2),d3
- mov (__xmit_head,a2),d2
- cmp d3,d2
- beq mnsc_vdma_tx_empty
-
- mov (__xmit_buffer,a2),d2 # get a char from the buffer and
- # transmit it
- movbu (d3,d2),d2
- movbu d2,(SCxTXB,e2) # Tx
-
- inc d3 # advance the buffer pointer
- and __UART_XMIT_SIZE-1,d3
- mov (__xmit_head,a2),d2
- mov d3,(__xmit_tail,a2)
-
- sub d3,d2 # see if we've written everything
- beq mnsc_vdma_tx_empty
-
- and __UART_XMIT_SIZE-1,d2 # see if we just made a hole
- cmp __UART_XMIT_SIZE-2,d2
- beq mnsc_vdma_tx_made_hole
-
-mnsc_vdma_tx_done:
- mov (__tm_icr,a3),a2
- mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2
- movhu d2,(a2) # request a slow interrupt
- movhu (a2),d2 # flush
-
-mnsc_vdma_tx_noint:
- movm (sp),[d2,d3,a2,a3,exreg0]
- rti
-
-mnsc_vdma_tx_empty:
- mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2
- movhu d2,(e3) # disable the interrupt
- movhu (e3),d2 # flush
-
- bset MNSCx_TX_EMPTY,(__intr_flags,a3)
- bra mnsc_vdma_tx_done
-
-mnsc_vdma_tx_flags:
- btst MNSCx_TX_STOP,(__tx_flags,a3)
- bne mnsc_vdma_tx_stop
- movhu (SCxCTR,e2),d2 # turn on break mode
- or SC01CTR_BKE,d2
- movhu d2,(SCxCTR,e2)
-mnsc_vdma_tx_stop:
- mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2
- movhu d2,(e3) # disable transmit interrupts on this
- # channel
- movhu (e3),d2 # flush
- bra mnsc_vdma_tx_noint
-
-mnsc_vdma_tx_xchar:
- bclr 0xff,(__tx_xchar,a3)
- movbu d2,(SCxTXB,e2)
- bra mnsc_vdma_tx_done
-
-mnsc_vdma_tx_made_hole:
- bset MNSCx_TX_SPACE,(__intr_flags,a3)
- bra mnsc_vdma_tx_done
diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c
deleted file mode 100644
index 4994b570dfd9..000000000000
--- a/arch/mn10300/kernel/mn10300-serial.c
+++ /dev/null
@@ -1,1790 +0,0 @@
-/* MN10300 On-chip serial port UART driver
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-static const char serial_name[] = "MN10300 Serial driver";
-static const char serial_version[] = "mn10300_serial-1.0";
-static const char serial_revdate[] = "2007-11-06";
-
-#if defined(CONFIG_MN10300_TTYSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
-#define SUPPORT_SYSRQ
-#endif
-
-#include <linux/module.h>
-#include <linux/serial.h>
-#include <linux/circ_buf.h>
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/timer.h>
-#include <linux/interrupt.h>
-#include <linux/tty.h>
-#include <linux/tty_flip.h>
-#include <linux/major.h>
-#include <linux/string.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/console.h>
-#include <linux/sysrq.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/bitops.h>
-#include <asm/serial-regs.h>
-#include <unit/timex.h>
-#include "mn10300-serial.h"
-
-#ifdef CONFIG_SMP
-#undef GxICR
-#define GxICR(X) CROSS_GxICR(X, 0)
-#endif /* CONFIG_SMP */
-
-#define kenter(FMT, ...) \
- printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
-#define _enter(FMT, ...) \
- no_printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
-#define kdebug(FMT, ...) \
- printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
-#define _debug(FMT, ...) \
- no_printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
-#define kproto(FMT, ...) \
- printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
-#define _proto(FMT, ...) \
- no_printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
-
-#ifndef CODMSB
-/* c_cflag bit meaning */
-#define CODMSB 004000000000 /* change Transfer bit-order */
-#endif
-
-#define NR_UARTS 3
-
-#ifdef CONFIG_MN10300_TTYSM_CONSOLE
-static void mn10300_serial_console_write(struct console *co,
- const char *s, unsigned count);
-static int __init mn10300_serial_console_setup(struct console *co,
- char *options);
-
-static struct uart_driver mn10300_serial_driver;
-static struct console mn10300_serial_console = {
- .name = "ttySM",
- .write = mn10300_serial_console_write,
- .device = uart_console_device,
- .setup = mn10300_serial_console_setup,
- .flags = CON_PRINTBUFFER,
- .index = -1,
- .data = &mn10300_serial_driver,
-};
-#endif
-
-static struct uart_driver mn10300_serial_driver = {
- .owner = NULL,
- .driver_name = "mn10300-serial",
- .dev_name = "ttySM",
- .major = TTY_MAJOR,
- .minor = 128,
- .nr = NR_UARTS,
-#ifdef CONFIG_MN10300_TTYSM_CONSOLE
- .cons = &mn10300_serial_console,
-#endif
-};
-
-static unsigned int mn10300_serial_tx_empty(struct uart_port *);
-static void mn10300_serial_set_mctrl(struct uart_port *, unsigned int mctrl);
-static unsigned int mn10300_serial_get_mctrl(struct uart_port *);
-static void mn10300_serial_stop_tx(struct uart_port *);
-static void mn10300_serial_start_tx(struct uart_port *);
-static void mn10300_serial_send_xchar(struct uart_port *, char ch);
-static void mn10300_serial_stop_rx(struct uart_port *);
-static void mn10300_serial_enable_ms(struct uart_port *);
-static void mn10300_serial_break_ctl(struct uart_port *, int ctl);
-static int mn10300_serial_startup(struct uart_port *);
-static void mn10300_serial_shutdown(struct uart_port *);
-static void mn10300_serial_set_termios(struct uart_port *,
- struct ktermios *new,
- struct ktermios *old);
-static const char *mn10300_serial_type(struct uart_port *);
-static void mn10300_serial_release_port(struct uart_port *);
-static int mn10300_serial_request_port(struct uart_port *);
-static void mn10300_serial_config_port(struct uart_port *, int);
-static int mn10300_serial_verify_port(struct uart_port *,
- struct serial_struct *);
-#ifdef CONFIG_CONSOLE_POLL
-static void mn10300_serial_poll_put_char(struct uart_port *, unsigned char);
-static int mn10300_serial_poll_get_char(struct uart_port *);
-#endif
-
-static const struct uart_ops mn10300_serial_ops = {
- .tx_empty = mn10300_serial_tx_empty,
- .set_mctrl = mn10300_serial_set_mctrl,
- .get_mctrl = mn10300_serial_get_mctrl,
- .stop_tx = mn10300_serial_stop_tx,
- .start_tx = mn10300_serial_start_tx,
- .send_xchar = mn10300_serial_send_xchar,
- .stop_rx = mn10300_serial_stop_rx,
- .enable_ms = mn10300_serial_enable_ms,
- .break_ctl = mn10300_serial_break_ctl,
- .startup = mn10300_serial_startup,
- .shutdown = mn10300_serial_shutdown,
- .set_termios = mn10300_serial_set_termios,
- .type = mn10300_serial_type,
- .release_port = mn10300_serial_release_port,
- .request_port = mn10300_serial_request_port,
- .config_port = mn10300_serial_config_port,
- .verify_port = mn10300_serial_verify_port,
-#ifdef CONFIG_CONSOLE_POLL
- .poll_put_char = mn10300_serial_poll_put_char,
- .poll_get_char = mn10300_serial_poll_get_char,
-#endif
-};
-
-static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id);
-
-/*
- * the first on-chip serial port: ttySM0 (aka SIF0)
- */
-#ifdef CONFIG_MN10300_TTYSM0
-struct mn10300_serial_port mn10300_serial_port_sif0 = {
- .uart.ops = &mn10300_serial_ops,
- .uart.membase = (void __iomem *) &SC0CTR,
- .uart.mapbase = (unsigned long) &SC0CTR,
- .uart.iotype = UPIO_MEM,
- .uart.irq = 0,
- .uart.uartclk = 0, /* MN10300_IOCLK, */
- .uart.fifosize = 1,
- .uart.flags = UPF_BOOT_AUTOCONF,
- .uart.line = 0,
- .uart.type = PORT_MN10300,
- .uart.lock =
- __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif0.uart.lock),
- .name = "ttySM0",
- ._iobase = &SC0CTR,
- ._control = &SC0CTR,
- ._status = (volatile u8 *)&SC0STR,
- ._intr = &SC0ICR,
- ._rxb = &SC0RXB,
- ._txb = &SC0TXB,
- .rx_name = "ttySM0:Rx",
- .tx_name = "ttySM0:Tx",
-#if defined(CONFIG_MN10300_TTYSM0_TIMER8)
- .tm_name = "ttySM0:Timer8",
- ._tmxmd = &TM8MD,
- ._tmxbr = &TM8BR,
- ._tmicr = &TM8ICR,
- .tm_irq = TM8IRQ,
- .div_timer = MNSCx_DIV_TIMER_16BIT,
-#elif defined(CONFIG_MN10300_TTYSM0_TIMER0)
- .tm_name = "ttySM0:Timer0",
- ._tmxmd = &TM0MD,
- ._tmxbr = (volatile u16 *)&TM0BR,
- ._tmicr = &TM0ICR,
- .tm_irq = TM0IRQ,
- .div_timer = MNSCx_DIV_TIMER_8BIT,
-#elif defined(CONFIG_MN10300_TTYSM0_TIMER2)
- .tm_name = "ttySM0:Timer2",
- ._tmxmd = &TM2MD,
- ._tmxbr = (volatile u16 *)&TM2BR,
- ._tmicr = &TM2ICR,
- .tm_irq = TM2IRQ,
- .div_timer = MNSCx_DIV_TIMER_8BIT,
-#else
-#error "Unknown config for ttySM0"
-#endif
- .rx_irq = SC0RXIRQ,
- .tx_irq = SC0TXIRQ,
- .rx_icr = &GxICR(SC0RXIRQ),
- .tx_icr = &GxICR(SC0TXIRQ),
- .clock_src = MNSCx_CLOCK_SRC_IOCLK,
- .options = 0,
-#ifdef CONFIG_GDBSTUB_ON_TTYSM0
- .gdbstub = 1,
-#endif
-};
-#endif /* CONFIG_MN10300_TTYSM0 */
-
-/*
- * the second on-chip serial port: ttySM1 (aka SIF1)
- */
-#ifdef CONFIG_MN10300_TTYSM1
-struct mn10300_serial_port mn10300_serial_port_sif1 = {
- .uart.ops = &mn10300_serial_ops,
- .uart.membase = (void __iomem *) &SC1CTR,
- .uart.mapbase = (unsigned long) &SC1CTR,
- .uart.iotype = UPIO_MEM,
- .uart.irq = 0,
- .uart.uartclk = 0, /* MN10300_IOCLK, */
- .uart.fifosize = 1,
- .uart.flags = UPF_BOOT_AUTOCONF,
- .uart.line = 1,
- .uart.type = PORT_MN10300,
- .uart.lock =
- __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif1.uart.lock),
- .name = "ttySM1",
- ._iobase = &SC1CTR,
- ._control = &SC1CTR,
- ._status = (volatile u8 *)&SC1STR,
- ._intr = &SC1ICR,
- ._rxb = &SC1RXB,
- ._txb = &SC1TXB,
- .rx_name = "ttySM1:Rx",
- .tx_name = "ttySM1:Tx",
-#if defined(CONFIG_MN10300_TTYSM1_TIMER9)
- .tm_name = "ttySM1:Timer9",
- ._tmxmd = &TM9MD,
- ._tmxbr = &TM9BR,
- ._tmicr = &TM9ICR,
- .tm_irq = TM9IRQ,
- .div_timer = MNSCx_DIV_TIMER_16BIT,
-#elif defined(CONFIG_MN10300_TTYSM1_TIMER3)
- .tm_name = "ttySM1:Timer3",
- ._tmxmd = &TM3MD,
- ._tmxbr = (volatile u16 *)&TM3BR,
- ._tmicr = &TM3ICR,
- .tm_irq = TM3IRQ,
- .div_timer = MNSCx_DIV_TIMER_8BIT,
-#elif defined(CONFIG_MN10300_TTYSM1_TIMER12)
- .tm_name = "ttySM1/Timer12",
- ._tmxmd = &TM12MD,
- ._tmxbr = &TM12BR,
- ._tmicr = &TM12ICR,
- .tm_irq = TM12IRQ,
- .div_timer = MNSCx_DIV_TIMER_16BIT,
-#else
-#error "Unknown config for ttySM1"
-#endif
- .rx_irq = SC1RXIRQ,
- .tx_irq = SC1TXIRQ,
- .rx_icr = &GxICR(SC1RXIRQ),
- .tx_icr = &GxICR(SC1TXIRQ),
- .clock_src = MNSCx_CLOCK_SRC_IOCLK,
- .options = 0,
-#ifdef CONFIG_GDBSTUB_ON_TTYSM1
- .gdbstub = 1,
-#endif
-};
-#endif /* CONFIG_MN10300_TTYSM1 */
-
-/*
- * the third on-chip serial port: ttySM2 (aka SIF2)
- */
-#ifdef CONFIG_MN10300_TTYSM2
-struct mn10300_serial_port mn10300_serial_port_sif2 = {
- .uart.ops = &mn10300_serial_ops,
- .uart.membase = (void __iomem *) &SC2CTR,
- .uart.mapbase = (unsigned long) &SC2CTR,
- .uart.iotype = UPIO_MEM,
- .uart.irq = 0,
- .uart.uartclk = 0, /* MN10300_IOCLK, */
- .uart.fifosize = 1,
- .uart.flags = UPF_BOOT_AUTOCONF,
- .uart.line = 2,
-#ifdef CONFIG_MN10300_TTYSM2_CTS
- .uart.type = PORT_MN10300_CTS,
-#else
- .uart.type = PORT_MN10300,
-#endif
- .uart.lock =
- __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif2.uart.lock),
- .name = "ttySM2",
- ._iobase = &SC2CTR,
- ._control = &SC2CTR,
- ._status = (volatile u8 *)&SC2STR,
- ._intr = &SC2ICR,
- ._rxb = &SC2RXB,
- ._txb = &SC2TXB,
- .rx_name = "ttySM2:Rx",
- .tx_name = "ttySM2:Tx",
-#if defined(CONFIG_MN10300_TTYSM2_TIMER10)
- .tm_name = "ttySM2/Timer10",
- ._tmxmd = &TM10MD,
- ._tmxbr = &TM10BR,
- ._tmicr = &TM10ICR,
- .tm_irq = TM10IRQ,
- .div_timer = MNSCx_DIV_TIMER_16BIT,
-#elif defined(CONFIG_MN10300_TTYSM2_TIMER9)
- .tm_name = "ttySM2/Timer9",
- ._tmxmd = &TM9MD,
- ._tmxbr = &TM9BR,
- ._tmicr = &TM9ICR,
- .tm_irq = TM9IRQ,
- .div_timer = MNSCx_DIV_TIMER_16BIT,
-#elif defined(CONFIG_MN10300_TTYSM2_TIMER1)
- .tm_name = "ttySM2/Timer1",
- ._tmxmd = &TM1MD,
- ._tmxbr = (volatile u16 *)&TM1BR,
- ._tmicr = &TM1ICR,
- .tm_irq = TM1IRQ,
- .div_timer = MNSCx_DIV_TIMER_8BIT,
-#elif defined(CONFIG_MN10300_TTYSM2_TIMER3)
- .tm_name = "ttySM2/Timer3",
- ._tmxmd = &TM3MD,
- ._tmxbr = (volatile u16 *)&TM3BR,
- ._tmicr = &TM3ICR,
- .tm_irq = TM3IRQ,
- .div_timer = MNSCx_DIV_TIMER_8BIT,
-#else
-#error "Unknown config for ttySM2"
-#endif
- .rx_irq = SC2RXIRQ,
- .tx_irq = SC2TXIRQ,
- .rx_icr = &GxICR(SC2RXIRQ),
- .tx_icr = &GxICR(SC2TXIRQ),
- .clock_src = MNSCx_CLOCK_SRC_IOCLK,
-#ifdef CONFIG_MN10300_TTYSM2_CTS
- .options = MNSCx_OPT_CTS,
-#else
- .options = 0,
-#endif
-#ifdef CONFIG_GDBSTUB_ON_TTYSM2
- .gdbstub = 1,
-#endif
-};
-#endif /* CONFIG_MN10300_TTYSM2 */
-
-
-/*
- * list of available serial ports
- */
-struct mn10300_serial_port *mn10300_serial_ports[NR_UARTS + 1] = {
-#ifdef CONFIG_MN10300_TTYSM0
- [0] = &mn10300_serial_port_sif0,
-#endif
-#ifdef CONFIG_MN10300_TTYSM1
- [1] = &mn10300_serial_port_sif1,
-#endif
-#ifdef CONFIG_MN10300_TTYSM2
- [2] = &mn10300_serial_port_sif2,
-#endif
- [NR_UARTS] = NULL,
-};
-
-
-/*
- * we abuse the serial ports' baud timers' interrupt lines to get the ability
- * to deliver interrupts to userspace as we use the ports' interrupt lines to
- * do virtual DMA on account of the ports having no hardware FIFOs
- *
- * we can generate an interrupt manually in the assembly stubs by writing to
- * the enable and detect bits in the interrupt control register, so all we need
- * to do here is disable the interrupt line
- *
- * note that we can't just leave the line enabled as the baud rate timer *also*
- * generates interrupts
- */
-static void mn10300_serial_mask_ack(unsigned int irq)
-{
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
- GxICR(irq) = GxICR_LEVEL_6;
- tmp = GxICR(irq); /* flush write buffer */
- arch_local_irq_restore(flags);
-}
-
-static void mn10300_serial_chip_mask_ack(struct irq_data *d)
-{
- mn10300_serial_mask_ack(d->irq);
-}
-
-static void mn10300_serial_nop(struct irq_data *d)
-{
-}
-
-static struct irq_chip mn10300_serial_pic = {
- .name = "mnserial",
- .irq_ack = mn10300_serial_chip_mask_ack,
- .irq_mask = mn10300_serial_chip_mask_ack,
- .irq_mask_ack = mn10300_serial_chip_mask_ack,
- .irq_unmask = mn10300_serial_nop,
-};
-
-static void mn10300_serial_low_mask(struct irq_data *d)
-{
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
- GxICR(d->irq) = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
- tmp = GxICR(d->irq); /* flush write buffer */
- arch_local_irq_restore(flags);
-}
-
-static void mn10300_serial_low_unmask(struct irq_data *d)
-{
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
- GxICR(d->irq) =
- NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL) | GxICR_ENABLE;
- tmp = GxICR(d->irq); /* flush write buffer */
- arch_local_irq_restore(flags);
-}
-
-static struct irq_chip mn10300_serial_low_pic = {
- .name = "mnserial-low",
- .irq_mask = mn10300_serial_low_mask,
- .irq_unmask = mn10300_serial_low_unmask,
-};
-
-/*
- * serial virtual DMA interrupt jump table
- */
-struct mn10300_serial_int mn10300_serial_int_tbl[NR_IRQS];
-
-static void mn10300_serial_dis_tx_intr(struct mn10300_serial_port *port)
-{
- int retries = 100;
- u16 x;
-
- /* nothing to do if irq isn't set up */
- if (!mn10300_serial_int_tbl[port->tx_irq].port)
- return;
-
- port->tx_flags |= MNSCx_TX_STOP;
- mb();
-
- /*
- * Here we wait for the irq to be disabled. Either it already is
- * disabled or we wait some number of retries for the VDMA handler
- * to disable it. The retries give the VDMA handler enough time to
- * run to completion if it was already in progress. If the VDMA IRQ
- * is enabled but the handler is not yet running when arrive here,
- * the STOP flag will prevent the handler from conflicting with the
- * driver code following this loop.
- */
- while ((*port->tx_icr & GxICR_ENABLE) && retries-- > 0)
- ;
- if (retries <= 0) {
- *port->tx_icr =
- NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
- x = *port->tx_icr;
- }
-}
-
-static void mn10300_serial_en_tx_intr(struct mn10300_serial_port *port)
-{
- u16 x;
-
- /* nothing to do if irq isn't set up */
- if (!mn10300_serial_int_tbl[port->tx_irq].port)
- return;
-
- /* stop vdma irq if not already stopped */
- if (!(port->tx_flags & MNSCx_TX_STOP))
- mn10300_serial_dis_tx_intr(port);
-
- port->tx_flags &= ~MNSCx_TX_STOP;
- mb();
-
- *port->tx_icr =
- NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL) |
- GxICR_ENABLE | GxICR_REQUEST | GxICR_DETECT;
- x = *port->tx_icr;
-}
-
-static void mn10300_serial_dis_rx_intr(struct mn10300_serial_port *port)
-{
- unsigned long flags;
- u16 x;
-
- flags = arch_local_cli_save();
- *port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
- x = *port->rx_icr;
- arch_local_irq_restore(flags);
-}
-
-/*
- * multi-bit equivalent of test_and_clear_bit()
- */
-static int mask_test_and_clear(volatile u8 *ptr, u8 mask)
-{
- u32 epsw;
- asm volatile(" bclr %1,(%2) \n"
- " mov epsw,%0 \n"
- : "=d"(epsw) : "d"(mask), "a"(ptr)
- : "cc", "memory");
- return !(epsw & EPSW_FLAG_Z);
-}
-
-/*
- * receive chars from the ring buffer for this serial port
- * - must do break detection here (not done in the UART)
- */
-static void mn10300_serial_receive_interrupt(struct mn10300_serial_port *port)
-{
- struct uart_icount *icount = &port->uart.icount;
- struct tty_port *tport = &port->uart.state->port;
- unsigned ix;
- int count;
- u8 st, ch, push, status, overrun;
-
- _enter("%s", port->name);
-
- push = 0;
-
- count = CIRC_CNT(port->rx_inp, port->rx_outp, MNSC_BUFFER_SIZE);
- count = tty_buffer_request_room(tport, count);
- if (count == 0) {
- if (!tport->low_latency)
- tty_flip_buffer_push(tport);
- return;
- }
-
-try_again:
- /* pull chars out of the hat */
- ix = READ_ONCE(port->rx_outp);
- if (CIRC_CNT(port->rx_inp, ix, MNSC_BUFFER_SIZE) == 0) {
- if (push && !tport->low_latency)
- tty_flip_buffer_push(tport);
- return;
- }
-
- /* READ_ONCE() enforces dependency, but dangerous through integer!!! */
- ch = port->rx_buffer[ix++];
- st = port->rx_buffer[ix++];
- smp_mb();
- port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
- port->uart.icount.rx++;
-
- st &= SC01STR_FEF | SC01STR_PEF | SC01STR_OEF;
- status = 0;
- overrun = 0;
-
- /* the UART doesn't detect BREAK, so we have to do that ourselves
- * - it starts as a framing error on a NUL character
- * - then we count another two NUL characters before issuing TTY_BREAK
- * - then we end on a normal char or one that has all the bottom bits
- * zero and the top bits set
- */
- switch (port->rx_brk) {
- case 0:
- /* not breaking at the moment */
- break;
-
- case 1:
- if (st & SC01STR_FEF && ch == 0) {
- port->rx_brk = 2;
- goto try_again;
- }
- goto not_break;
-
- case 2:
- if (st & SC01STR_FEF && ch == 0) {
- port->rx_brk = 3;
- _proto("Rx Break Detected");
- icount->brk++;
- if (uart_handle_break(&port->uart))
- goto ignore_char;
- status |= 1 << TTY_BREAK;
- goto insert;
- }
- goto not_break;
-
- default:
- if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF))
- goto try_again; /* still breaking */
-
- port->rx_brk = 0; /* end of the break */
-
- switch (ch) {
- case 0xFF:
- case 0xFE:
- case 0xFC:
- case 0xF8:
- case 0xF0:
- case 0xE0:
- case 0xC0:
- case 0x80:
- case 0x00:
- /* discard char at probable break end */
- goto try_again;
- }
- break;
- }
-
-process_errors:
- /* handle framing error */
- if (st & SC01STR_FEF) {
- if (ch == 0) {
- /* framing error with NUL char is probably a BREAK */
- port->rx_brk = 1;
- goto try_again;
- }
-
- _proto("Rx Framing Error");
- icount->frame++;
- status |= 1 << TTY_FRAME;
- }
-
- /* handle parity error */
- if (st & SC01STR_PEF) {
- _proto("Rx Parity Error");
- icount->parity++;
- status = TTY_PARITY;
- }
-
- /* handle normal char */
- if (status == 0) {
- if (uart_handle_sysrq_char(&port->uart, ch))
- goto ignore_char;
- status = (1 << TTY_NORMAL);
- }
-
- /* handle overrun error */
- if (st & SC01STR_OEF) {
- if (port->rx_brk)
- goto try_again;
-
- _proto("Rx Overrun Error");
- icount->overrun++;
- overrun = 1;
- }
-
-insert:
- status &= port->uart.read_status_mask;
-
- if (!overrun && !(status & port->uart.ignore_status_mask)) {
- int flag;
-
- if (status & (1 << TTY_BREAK))
- flag = TTY_BREAK;
- else if (status & (1 << TTY_PARITY))
- flag = TTY_PARITY;
- else if (status & (1 << TTY_FRAME))
- flag = TTY_FRAME;
- else
- flag = TTY_NORMAL;
-
- tty_insert_flip_char(tport, ch, flag);
- }
-
- /* overrun is special, since it's reported immediately, and doesn't
- * affect the current character
- */
- if (overrun)
- tty_insert_flip_char(tport, 0, TTY_OVERRUN);
-
- count--;
- if (count <= 0) {
- if (!tport->low_latency)
- tty_flip_buffer_push(tport);
- return;
- }
-
-ignore_char:
- push = 1;
- goto try_again;
-
-not_break:
- port->rx_brk = 0;
- goto process_errors;
-}
-
-/*
- * handle an interrupt from the serial transmission "virtual DMA" driver
- * - note: the interrupt routine will disable its own interrupts when the Tx
- * buffer is empty
- */
-static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port)
-{
- _enter("%s", port->name);
-
- if (!port->uart.state || !port->uart.state->port.tty) {
- mn10300_serial_dis_tx_intr(port);
- return;
- }
-
- if (uart_tx_stopped(&port->uart) ||
- uart_circ_empty(&port->uart.state->xmit))
- mn10300_serial_dis_tx_intr(port);
-
- if (uart_circ_chars_pending(&port->uart.state->xmit) < WAKEUP_CHARS)
- uart_write_wakeup(&port->uart);
-}
-
-/*
- * deal with a change in the status of the CTS line
- */
-static void mn10300_serial_cts_changed(struct mn10300_serial_port *port, u8 st)
-{
- u16 ctr;
-
- port->tx_cts = st;
- port->uart.icount.cts++;
-
- /* flip the CTS state selector flag to interrupt when it changes
- * back */
- ctr = *port->_control;
- ctr ^= SC2CTR_TWS;
- *port->_control = ctr;
-
- uart_handle_cts_change(&port->uart, st & SC2STR_CTS);
- wake_up_interruptible(&port->uart.state->port.delta_msr_wait);
-}
-
-/*
- * handle a virtual interrupt generated by the lower level "virtual DMA"
- * routines (irq is the baud timer interrupt)
- */
-static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id)
-{
- struct mn10300_serial_port *port = dev_id;
- u8 st;
-
- spin_lock(&port->uart.lock);
-
- if (port->intr_flags) {
- _debug("INT %s: %x", port->name, port->intr_flags);
-
- if (mask_test_and_clear(&port->intr_flags, MNSCx_RX_AVAIL))
- mn10300_serial_receive_interrupt(port);
-
- if (mask_test_and_clear(&port->intr_flags,
- MNSCx_TX_SPACE | MNSCx_TX_EMPTY))
- mn10300_serial_transmit_interrupt(port);
- }
-
- /* the only modem control line amongst the whole lot is CTS on
- * serial port 2 */
- if (port->type == PORT_MN10300_CTS) {
- st = *port->_status;
- if ((port->tx_cts ^ st) & SC2STR_CTS)
- mn10300_serial_cts_changed(port, st);
- }
-
- spin_unlock(&port->uart.lock);
-
- return IRQ_HANDLED;
-}
-
-/*
- * return indication of whether the hardware transmit buffer is empty
- */
-static unsigned int mn10300_serial_tx_empty(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s", port->name);
-
- return (*port->_status & (SC01STR_TXF | SC01STR_TBF)) ?
- 0 : TIOCSER_TEMT;
-}
-
-/*
- * set the modem control lines (we don't have any)
- */
-static void mn10300_serial_set_mctrl(struct uart_port *_port,
- unsigned int mctrl)
-{
- struct mn10300_serial_port *port __attribute__ ((unused)) =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s,%x", port->name, mctrl);
-}
-
-/*
- * get the modem control line statuses
- */
-static unsigned int mn10300_serial_get_mctrl(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s", port->name);
-
- if (port->type == PORT_MN10300_CTS && !(*port->_status & SC2STR_CTS))
- return TIOCM_CAR | TIOCM_DSR;
-
- return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
-}
-
-/*
- * stop transmitting characters
- */
-static void mn10300_serial_stop_tx(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s", port->name);
-
- /* disable the virtual DMA */
- mn10300_serial_dis_tx_intr(port);
-}
-
-/*
- * start transmitting characters
- * - jump-start transmission if it has stalled
- * - enable the serial Tx interrupt (used by the virtual DMA controller)
- * - force an interrupt to happen if necessary
- */
-static void mn10300_serial_start_tx(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s{%lu}",
- port->name,
- CIRC_CNT(&port->uart.state->xmit.head,
- &port->uart.state->xmit.tail,
- UART_XMIT_SIZE));
-
- /* kick the virtual DMA controller */
- mn10300_serial_en_tx_intr(port);
-
- _debug("CTR=%04hx ICR=%02hx STR=%04x TMD=%02hx TBR=%04hx ICR=%04hx",
- *port->_control, *port->_intr, *port->_status,
- *port->_tmxmd,
- (port->div_timer == MNSCx_DIV_TIMER_8BIT) ?
- *(volatile u8 *)port->_tmxbr : *port->_tmxbr,
- *port->tx_icr);
-}
-
-/*
- * transmit a high-priority XON/XOFF character
- */
-static void mn10300_serial_send_xchar(struct uart_port *_port, char ch)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
- unsigned long flags;
-
- _enter("%s,%02x", port->name, ch);
-
- if (likely(port->gdbstub)) {
- port->tx_xchar = ch;
- if (ch) {
- spin_lock_irqsave(&port->uart.lock, flags);
- mn10300_serial_en_tx_intr(port);
- spin_unlock_irqrestore(&port->uart.lock, flags);
- }
- }
-}
-
-/*
- * stop receiving characters
- * - called whilst the port is being closed
- */
-static void mn10300_serial_stop_rx(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- u16 ctr;
-
- _enter("%s", port->name);
-
- ctr = *port->_control;
- ctr &= ~SC01CTR_RXE;
- *port->_control = ctr;
-
- mn10300_serial_dis_rx_intr(port);
-}
-
-/*
- * enable modem status interrupts
- */
-static void mn10300_serial_enable_ms(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- u16 ctr, cts;
-
- _enter("%s", port->name);
-
- if (port->type == PORT_MN10300_CTS) {
- /* want to interrupt when CTS goes low if CTS is now high and
- * vice versa
- */
- port->tx_cts = *port->_status;
-
- cts = (port->tx_cts & SC2STR_CTS) ?
- SC2CTR_TWE : SC2CTR_TWE | SC2CTR_TWS;
-
- ctr = *port->_control;
- ctr &= ~SC2CTR_TWS;
- ctr |= cts;
- *port->_control = ctr;
-
- mn10300_serial_en_tx_intr(port);
- }
-}
-
-/*
- * transmit or cease transmitting a break signal
- */
-static void mn10300_serial_break_ctl(struct uart_port *_port, int ctl)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
- unsigned long flags;
-
- _enter("%s,%d", port->name, ctl);
-
- spin_lock_irqsave(&port->uart.lock, flags);
- if (ctl) {
- /* tell the virtual DMA handler to assert BREAK */
- port->tx_flags |= MNSCx_TX_BREAK;
- mn10300_serial_en_tx_intr(port);
- } else {
- port->tx_flags &= ~MNSCx_TX_BREAK;
- *port->_control &= ~SC01CTR_BKE;
- mn10300_serial_en_tx_intr(port);
- }
- spin_unlock_irqrestore(&port->uart.lock, flags);
-}
-
-/*
- * grab the interrupts and enable the port for reception
- */
-static int mn10300_serial_startup(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
- struct mn10300_serial_int *pint;
-
- _enter("%s{%d}", port->name, port->gdbstub);
-
- if (unlikely(port->gdbstub))
- return -EBUSY;
-
- /* allocate an Rx buffer for the virtual DMA handler */
- port->rx_buffer = kmalloc(MNSC_BUFFER_SIZE, GFP_KERNEL);
- if (!port->rx_buffer)
- return -ENOMEM;
-
- port->rx_inp = port->rx_outp = 0;
- port->tx_flags = 0;
-
- /* finally, enable the device */
- *port->_intr = SC01ICR_TI;
- *port->_control |= SC01CTR_TXE | SC01CTR_RXE;
-
- pint = &mn10300_serial_int_tbl[port->rx_irq];
- pint->port = port;
- pint->vdma = mn10300_serial_vdma_rx_handler;
- pint = &mn10300_serial_int_tbl[port->tx_irq];
- pint->port = port;
- pint->vdma = mn10300_serial_vdma_tx_handler;
-
- irq_set_chip(port->rx_irq, &mn10300_serial_low_pic);
- irq_set_chip(port->tx_irq, &mn10300_serial_low_pic);
- irq_set_chip(port->tm_irq, &mn10300_serial_pic);
-
- if (request_irq(port->rx_irq, mn10300_serial_interrupt,
- IRQF_NOBALANCING,
- port->rx_name, port) < 0)
- goto error;
-
- if (request_irq(port->tx_irq, mn10300_serial_interrupt,
- IRQF_NOBALANCING,
- port->tx_name, port) < 0)
- goto error2;
-
- if (request_irq(port->tm_irq, mn10300_serial_interrupt,
- IRQF_NOBALANCING,
- port->tm_name, port) < 0)
- goto error3;
- mn10300_serial_mask_ack(port->tm_irq);
-
- return 0;
-
-error3:
- free_irq(port->tx_irq, port);
-error2:
- free_irq(port->rx_irq, port);
-error:
- kfree(port->rx_buffer);
- port->rx_buffer = NULL;
- return -EBUSY;
-}
-
-/*
- * shutdown the port and release interrupts
- */
-static void mn10300_serial_shutdown(struct uart_port *_port)
-{
- unsigned long flags;
- u16 x;
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s", port->name);
-
- spin_lock_irqsave(&_port->lock, flags);
- mn10300_serial_dis_tx_intr(port);
-
- *port->rx_icr = NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL);
- x = *port->rx_icr;
- port->tx_flags = 0;
- spin_unlock_irqrestore(&_port->lock, flags);
-
- /* disable the serial port and its baud rate timer */
- *port->_control &= ~(SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
- *port->_tmxmd = 0;
-
- if (port->rx_buffer) {
- void *buf = port->rx_buffer;
- port->rx_buffer = NULL;
- kfree(buf);
- }
-
- /* disable all intrs */
- free_irq(port->tm_irq, port);
- free_irq(port->rx_irq, port);
- free_irq(port->tx_irq, port);
-
- mn10300_serial_int_tbl[port->tx_irq].port = NULL;
- mn10300_serial_int_tbl[port->rx_irq].port = NULL;
-}
-
-/*
- * this routine is called to set the UART divisor registers to match the
- * specified baud rate for a serial port.
- */
-static void mn10300_serial_change_speed(struct mn10300_serial_port *port,
- struct ktermios *new,
- struct ktermios *old)
-{
- unsigned long flags;
- unsigned long ioclk = port->ioclk;
- unsigned cflag;
- int baud, bits, xdiv, tmp;
- u16 tmxbr, scxctr;
- u8 tmxmd, battempt;
- u8 div_timer = port->div_timer;
-
- _enter("%s{%lu}", port->name, ioclk);
-
- /* byte size and parity */
- cflag = new->c_cflag;
- switch (cflag & CSIZE) {
- case CS7: scxctr = SC01CTR_CLN_7BIT; bits = 9; break;
- case CS8: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
- default: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
- }
-
- if (cflag & CSTOPB) {
- scxctr |= SC01CTR_STB_2BIT;
- bits++;
- }
-
- if (cflag & PARENB) {
- bits++;
- if (cflag & PARODD)
- scxctr |= SC01CTR_PB_ODD;
-#ifdef CMSPAR
- else if (cflag & CMSPAR)
- scxctr |= SC01CTR_PB_FIXED0;
-#endif
- else
- scxctr |= SC01CTR_PB_EVEN;
- }
-
- /* Determine divisor based on baud rate */
- battempt = 0;
-
- switch (port->uart.line) {
-#ifdef CONFIG_MN10300_TTYSM0
- case 0: /* ttySM0 */
-#if defined(CONFIG_MN10300_TTYSM0_TIMER8)
- scxctr |= SC0CTR_CK_TM8UFLOW_8;
-#elif defined(CONFIG_MN10300_TTYSM0_TIMER0)
- scxctr |= SC0CTR_CK_TM0UFLOW_8;
-#elif defined(CONFIG_MN10300_TTYSM0_TIMER2)
- scxctr |= SC0CTR_CK_TM2UFLOW_8;
-#else
-#error "Unknown config for ttySM0"
-#endif
- break;
-#endif /* CONFIG_MN10300_TTYSM0 */
-
-#ifdef CONFIG_MN10300_TTYSM1
- case 1: /* ttySM1 */
-#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
-#if defined(CONFIG_MN10300_TTYSM1_TIMER9)
- scxctr |= SC1CTR_CK_TM9UFLOW_8;
-#elif defined(CONFIG_MN10300_TTYSM1_TIMER3)
- scxctr |= SC1CTR_CK_TM3UFLOW_8;
-#else
-#error "Unknown config for ttySM1"
-#endif
-#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
-#if defined(CONFIG_MN10300_TTYSM1_TIMER12)
- scxctr |= SC1CTR_CK_TM12UFLOW_8;
-#else
-#error "Unknown config for ttySM1"
-#endif
-#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
- break;
-#endif /* CONFIG_MN10300_TTYSM1 */
-
-#ifdef CONFIG_MN10300_TTYSM2
- case 2: /* ttySM2 */
-#if defined(CONFIG_AM33_2)
-#if defined(CONFIG_MN10300_TTYSM2_TIMER10)
- scxctr |= SC2CTR_CK_TM10UFLOW;
-#else
-#error "Unknown config for ttySM2"
-#endif
-#else /* CONFIG_AM33_2 */
-#if defined(CONFIG_MN10300_TTYSM2_TIMER9)
- scxctr |= SC2CTR_CK_TM9UFLOW_8;
-#elif defined(CONFIG_MN10300_TTYSM2_TIMER1)
- scxctr |= SC2CTR_CK_TM1UFLOW_8;
-#elif defined(CONFIG_MN10300_TTYSM2_TIMER3)
- scxctr |= SC2CTR_CK_TM3UFLOW_8;
-#else
-#error "Unknown config for ttySM2"
-#endif
-#endif /* CONFIG_AM33_2 */
- break;
-#endif /* CONFIG_MN10300_TTYSM2 */
-
- default:
- break;
- }
-
-try_alternative:
- baud = uart_get_baud_rate(&port->uart, new, old, 0,
- port->ioclk / 8);
-
- _debug("ALT %d [baud %d]", battempt, baud);
-
- if (!baud)
- baud = 9600; /* B0 transition handled in rs_set_termios */
- xdiv = 1;
- if (baud == 134) {
- baud = 269; /* 134 is really 134.5 */
- xdiv = 2;
- }
-
- if (baud == 38400 &&
- (port->uart.flags & UPF_SPD_MASK) == UPF_SPD_CUST
- ) {
- _debug("CUSTOM %u", port->uart.custom_divisor);
-
- if (div_timer == MNSCx_DIV_TIMER_16BIT) {
- if (port->uart.custom_divisor <= 65535) {
- tmxmd = TM8MD_SRC_IOCLK;
- tmxbr = port->uart.custom_divisor;
- port->uart.uartclk = ioclk;
- goto timer_okay;
- }
- if (port->uart.custom_divisor / 8 <= 65535) {
- tmxmd = TM8MD_SRC_IOCLK_8;
- tmxbr = port->uart.custom_divisor / 8;
- port->uart.custom_divisor = tmxbr * 8;
- port->uart.uartclk = ioclk / 8;
- goto timer_okay;
- }
- if (port->uart.custom_divisor / 32 <= 65535) {
- tmxmd = TM8MD_SRC_IOCLK_32;
- tmxbr = port->uart.custom_divisor / 32;
- port->uart.custom_divisor = tmxbr * 32;
- port->uart.uartclk = ioclk / 32;
- goto timer_okay;
- }
-
- } else if (div_timer == MNSCx_DIV_TIMER_8BIT) {
- if (port->uart.custom_divisor <= 255) {
- tmxmd = TM2MD_SRC_IOCLK;
- tmxbr = port->uart.custom_divisor;
- port->uart.uartclk = ioclk;
- goto timer_okay;
- }
- if (port->uart.custom_divisor / 8 <= 255) {
- tmxmd = TM2MD_SRC_IOCLK_8;
- tmxbr = port->uart.custom_divisor / 8;
- port->uart.custom_divisor = tmxbr * 8;
- port->uart.uartclk = ioclk / 8;
- goto timer_okay;
- }
- if (port->uart.custom_divisor / 32 <= 255) {
- tmxmd = TM2MD_SRC_IOCLK_32;
- tmxbr = port->uart.custom_divisor / 32;
- port->uart.custom_divisor = tmxbr * 32;
- port->uart.uartclk = ioclk / 32;
- goto timer_okay;
- }
- }
- }
-
- switch (div_timer) {
- case MNSCx_DIV_TIMER_16BIT:
- port->uart.uartclk = ioclk;
- tmxmd = TM8MD_SRC_IOCLK;
- tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 65535)
- goto timer_okay;
-
- port->uart.uartclk = ioclk / 8;
- tmxmd = TM8MD_SRC_IOCLK_8;
- tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 65535)
- goto timer_okay;
-
- port->uart.uartclk = ioclk / 32;
- tmxmd = TM8MD_SRC_IOCLK_32;
- tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 65535)
- goto timer_okay;
- break;
-
- case MNSCx_DIV_TIMER_8BIT:
- port->uart.uartclk = ioclk;
- tmxmd = TM2MD_SRC_IOCLK;
- tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 255)
- goto timer_okay;
-
- port->uart.uartclk = ioclk / 8;
- tmxmd = TM2MD_SRC_IOCLK_8;
- tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 255)
- goto timer_okay;
-
- port->uart.uartclk = ioclk / 32;
- tmxmd = TM2MD_SRC_IOCLK_32;
- tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
- if (tmp > 0 && tmp <= 255)
- goto timer_okay;
- break;
-
- default:
- BUG();
- return;
- }
-
- /* refuse to change to a baud rate we can't support */
- _debug("CAN'T SUPPORT");
-
- switch (battempt) {
- case 0:
- if (old) {
- new->c_cflag &= ~CBAUD;
- new->c_cflag |= (old->c_cflag & CBAUD);
- battempt = 1;
- goto try_alternative;
- }
-
- case 1:
- /* as a last resort, if the quotient is zero, default to 9600
- * bps */
- new->c_cflag &= ~CBAUD;
- new->c_cflag |= B9600;
- battempt = 2;
- goto try_alternative;
-
- default:
- /* hmmm... can't seem to support 9600 either
- * - we could try iterating through the speeds we know about to
- * find the lowest
- */
- new->c_cflag &= ~CBAUD;
- new->c_cflag |= B0;
-
- if (div_timer == MNSCx_DIV_TIMER_16BIT)
- tmxmd = TM8MD_SRC_IOCLK_32;
- else if (div_timer == MNSCx_DIV_TIMER_8BIT)
- tmxmd = TM2MD_SRC_IOCLK_32;
- tmxbr = 1;
-
- port->uart.uartclk = ioclk / 32;
- break;
- }
-timer_okay:
-
- _debug("UARTCLK: %u / %hu", port->uart.uartclk, tmxbr);
-
- /* make the changes */
- spin_lock_irqsave(&port->uart.lock, flags);
-
- uart_update_timeout(&port->uart, new->c_cflag, baud);
-
- /* set the timer to produce the required baud rate */
- switch (div_timer) {
- case MNSCx_DIV_TIMER_16BIT:
- *port->_tmxmd = 0;
- *port->_tmxbr = tmxbr;
- *port->_tmxmd = TM8MD_INIT_COUNTER;
- *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
- break;
-
- case MNSCx_DIV_TIMER_8BIT:
- *port->_tmxmd = 0;
- *(volatile u8 *) port->_tmxbr = (u8) tmxbr;
- *port->_tmxmd = TM2MD_INIT_COUNTER;
- *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
- break;
- }
-
- /* CTS flow control flag and modem status interrupts */
- scxctr &= ~(SC2CTR_TWE | SC2CTR_TWS);
-
- if (port->type == PORT_MN10300_CTS && cflag & CRTSCTS) {
- /* want to interrupt when CTS goes low if CTS is now
- * high and vice versa
- */
- port->tx_cts = *port->_status;
-
- if (port->tx_cts & SC2STR_CTS)
- scxctr |= SC2CTR_TWE;
- else
- scxctr |= SC2CTR_TWE | SC2CTR_TWS;
- }
-
- /* set up parity check flag */
- port->uart.read_status_mask = (1 << TTY_NORMAL) | (1 << TTY_OVERRUN);
- if (new->c_iflag & INPCK)
- port->uart.read_status_mask |=
- (1 << TTY_PARITY) | (1 << TTY_FRAME);
- if (new->c_iflag & (BRKINT | PARMRK))
- port->uart.read_status_mask |= (1 << TTY_BREAK);
-
- /* characters to ignore */
- port->uart.ignore_status_mask = 0;
- if (new->c_iflag & IGNPAR)
- port->uart.ignore_status_mask |=
- (1 << TTY_PARITY) | (1 << TTY_FRAME);
- if (new->c_iflag & IGNBRK) {
- port->uart.ignore_status_mask |= (1 << TTY_BREAK);
- /*
- * If we're ignoring parity and break indicators,
- * ignore overruns to (for real raw support).
- */
- if (new->c_iflag & IGNPAR)
- port->uart.ignore_status_mask |= (1 << TTY_OVERRUN);
- }
-
- /* Ignore all characters if CREAD is not set */
- if ((new->c_cflag & CREAD) == 0)
- port->uart.ignore_status_mask |= (1 << TTY_NORMAL);
-
- scxctr |= SC01CTR_TXE | SC01CTR_RXE;
- scxctr |= *port->_control & SC01CTR_BKE;
- *port->_control = scxctr;
-
- spin_unlock_irqrestore(&port->uart.lock, flags);
-}
-
-/*
- * set the terminal I/O parameters
- */
-static void mn10300_serial_set_termios(struct uart_port *_port,
- struct ktermios *new,
- struct ktermios *old)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s,%p,%p", port->name, new, old);
-
- mn10300_serial_change_speed(port, new, old);
-
- /* handle turning off CRTSCTS */
- if (!(new->c_cflag & CRTSCTS)) {
- u16 ctr = *port->_control;
- ctr &= ~SC2CTR_TWE;
- *port->_control = ctr;
- }
-
- /* change Transfer bit-order (LSB/MSB) */
- if (new->c_cflag & CODMSB)
- *port->_control |= SC01CTR_OD_MSBFIRST; /* MSB MODE */
- else
- *port->_control &= ~SC01CTR_OD_MSBFIRST; /* LSB MODE */
-}
-
-/*
- * return description of port type
- */
-static const char *mn10300_serial_type(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- if (port->uart.type == PORT_MN10300_CTS)
- return "MN10300 SIF_CTS";
-
- return "MN10300 SIF";
-}
-
-/*
- * release I/O and memory regions in use by port
- */
-static void mn10300_serial_release_port(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s", port->name);
-
- release_mem_region((unsigned long) port->_iobase, 16);
-}
-
-/*
- * request I/O and memory regions for port
- */
-static int mn10300_serial_request_port(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s", port->name);
-
- request_mem_region((unsigned long) port->_iobase, 16, port->name);
- return 0;
-}
-
-/*
- * configure the type and reserve the ports
- */
-static void mn10300_serial_config_port(struct uart_port *_port, int type)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
-
- _enter("%s", port->name);
-
- port->uart.type = PORT_MN10300;
-
- if (port->options & MNSCx_OPT_CTS)
- port->uart.type = PORT_MN10300_CTS;
-
- mn10300_serial_request_port(_port);
-}
-
-/*
- * verify serial parameters are suitable for this port type
- */
-static int mn10300_serial_verify_port(struct uart_port *_port,
- struct serial_struct *ss)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
- void *mapbase = (void *) (unsigned long) port->uart.mapbase;
-
- _enter("%s", port->name);
-
- /* these things may not be changed */
- if (ss->irq != port->uart.irq ||
- ss->port != port->uart.iobase ||
- ss->io_type != port->uart.iotype ||
- ss->iomem_base != mapbase ||
- ss->iomem_reg_shift != port->uart.regshift ||
- ss->hub6 != port->uart.hub6 ||
- ss->xmit_fifo_size != port->uart.fifosize)
- return -EINVAL;
-
- /* type may be changed on a port that supports CTS */
- if (ss->type != port->uart.type) {
- if (!(port->options & MNSCx_OPT_CTS))
- return -EINVAL;
-
- if (ss->type != PORT_MN10300 &&
- ss->type != PORT_MN10300_CTS)
- return -EINVAL;
- }
-
- return 0;
-}
-
-/*
- * initialise the MN10300 on-chip UARTs
- */
-static int __init mn10300_serial_init(void)
-{
- struct mn10300_serial_port *port;
- int ret, i;
-
- printk(KERN_INFO "%s version %s (%s)\n",
- serial_name, serial_version, serial_revdate);
-
-#if defined(CONFIG_MN10300_TTYSM2) && defined(CONFIG_AM33_2)
- {
- int tmp;
- SC2TIM = 8; /* make the baud base of timer 2 IOCLK/8 */
- tmp = SC2TIM;
- }
-#endif
-
- set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL),
- mn10300_serial_vdma_interrupt);
-
- ret = uart_register_driver(&mn10300_serial_driver);
- if (!ret) {
- for (i = 0 ; i < NR_PORTS ; i++) {
- port = mn10300_serial_ports[i];
- if (!port || port->gdbstub)
- continue;
-
- switch (port->clock_src) {
- case MNSCx_CLOCK_SRC_IOCLK:
- port->ioclk = MN10300_IOCLK;
- break;
-
-#ifdef MN10300_IOBCLK
- case MNSCx_CLOCK_SRC_IOBCLK:
- port->ioclk = MN10300_IOBCLK;
- break;
-#endif
- default:
- BUG();
- }
-
- ret = uart_add_one_port(&mn10300_serial_driver,
- &port->uart);
-
- if (ret < 0) {
- _debug("ERROR %d", -ret);
- break;
- }
- }
-
- if (ret)
- uart_unregister_driver(&mn10300_serial_driver);
- }
-
- return ret;
-}
-
-__initcall(mn10300_serial_init);
-
-
-#ifdef CONFIG_MN10300_TTYSM_CONSOLE
-
-/*
- * print a string to the serial port without disturbing the real user of the
- * port too much
- * - the console must be locked by the caller
- */
-static void mn10300_serial_console_write(struct console *co,
- const char *s, unsigned count)
-{
- struct mn10300_serial_port *port;
- unsigned i;
- u16 scxctr;
- u8 tmxmd;
- unsigned long flags;
- int locked = 1;
-
- port = mn10300_serial_ports[co->index];
-
- local_irq_save(flags);
- if (port->uart.sysrq) {
- /* mn10300_serial_interrupt() already took the lock */
- locked = 0;
- } else if (oops_in_progress) {
- locked = spin_trylock(&port->uart.lock);
- } else
- spin_lock(&port->uart.lock);
-
- /* firstly hijack the serial port from the "virtual DMA" controller */
- mn10300_serial_dis_tx_intr(port);
-
- /* the transmitter may be disabled */
- scxctr = *port->_control;
- if (!(scxctr & SC01CTR_TXE)) {
- /* restart the UART clock */
- tmxmd = *port->_tmxmd;
-
- switch (port->div_timer) {
- case MNSCx_DIV_TIMER_16BIT:
- *port->_tmxmd = 0;
- *port->_tmxmd = TM8MD_INIT_COUNTER;
- *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
- break;
-
- case MNSCx_DIV_TIMER_8BIT:
- *port->_tmxmd = 0;
- *port->_tmxmd = TM2MD_INIT_COUNTER;
- *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
- break;
- }
-
- /* enable the transmitter */
- *port->_control = (scxctr & ~SC01CTR_BKE) | SC01CTR_TXE;
-
- } else if (scxctr & SC01CTR_BKE) {
- /* stop transmitting BREAK */
- *port->_control = (scxctr & ~SC01CTR_BKE);
- }
-
- /* send the chars into the serial port (with LF -> LFCR conversion) */
- for (i = 0; i < count; i++) {
- char ch = *s++;
-
- while (*port->_status & SC01STR_TBF)
- continue;
- *port->_txb = ch;
-
- if (ch == 0x0a) {
- while (*port->_status & SC01STR_TBF)
- continue;
- *port->_txb = 0xd;
- }
- }
-
- /* can't let the transmitter be turned off if it's actually
- * transmitting */
- while (*port->_status & (SC01STR_TXF | SC01STR_TBF))
- continue;
-
- /* disable the transmitter if we re-enabled it */
- if (!(scxctr & SC01CTR_TXE))
- *port->_control = scxctr;
-
- mn10300_serial_en_tx_intr(port);
-
- if (locked)
- spin_unlock(&port->uart.lock);
- local_irq_restore(flags);
-}
-
-/*
- * set up a serial port as a console
- * - construct a cflag setting for the first rs_open()
- * - initialize the serial port
- * - return non-zero if we didn't find a serial port.
- */
-static int __init mn10300_serial_console_setup(struct console *co,
- char *options)
-{
- struct mn10300_serial_port *port;
- int i, parity = 'n', baud = 9600, bits = 8, flow = 0;
-
- for (i = 0 ; i < NR_PORTS ; i++) {
- port = mn10300_serial_ports[i];
- if (port && !port->gdbstub && port->uart.line == co->index)
- goto found_device;
- }
-
- return -ENODEV;
-
-found_device:
- switch (port->clock_src) {
- case MNSCx_CLOCK_SRC_IOCLK:
- port->ioclk = MN10300_IOCLK;
- break;
-
-#ifdef MN10300_IOBCLK
- case MNSCx_CLOCK_SRC_IOBCLK:
- port->ioclk = MN10300_IOBCLK;
- break;
-#endif
- default:
- BUG();
- }
-
- if (options)
- uart_parse_options(options, &baud, &parity, &bits, &flow);
-
- return uart_set_options(&port->uart, co, baud, parity, bits, flow);
-}
-
-/*
- * register console
- */
-static int __init mn10300_serial_console_init(void)
-{
- register_console(&mn10300_serial_console);
- return 0;
-}
-
-console_initcall(mn10300_serial_console_init);
-#endif
-
-#ifdef CONFIG_CONSOLE_POLL
-/*
- * Polled character reception for the kernel debugger
- */
-static int mn10300_serial_poll_get_char(struct uart_port *_port)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
- unsigned ix;
- u8 st, ch;
-
- _enter("%s", port->name);
-
- if (mn10300_serial_int_tbl[port->rx_irq].port != NULL) {
- do {
- /* pull chars out of the hat */
- ix = READ_ONCE(port->rx_outp);
- if (CIRC_CNT(port->rx_inp, ix, MNSC_BUFFER_SIZE) == 0)
- return NO_POLL_CHAR;
-
- /*
- * READ_ONCE() enforces dependency, but dangerous
- * through integer!!!
- */
- ch = port->rx_buffer[ix++];
- st = port->rx_buffer[ix++];
- smp_mb();
- port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
-
- } while (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF));
- } else {
- do {
- st = *port->_status;
- if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF))
- continue;
- } while (!(st & SC01STR_RBF));
-
- ch = *port->_rxb;
- }
-
- return ch;
-}
-
-
-/*
- * Polled character transmission for the kernel debugger
- */
-static void mn10300_serial_poll_put_char(struct uart_port *_port,
- unsigned char ch)
-{
- struct mn10300_serial_port *port =
- container_of(_port, struct mn10300_serial_port, uart);
- u8 intr, tmp;
-
- /* wait for the transmitter to finish anything it might be doing (and
- * this includes the virtual DMA handler, so it might take a while) */
- while (*port->_status & (SC01STR_TBF | SC01STR_TXF))
- continue;
-
- /* disable the Tx ready interrupt */
- intr = *port->_intr;
- *port->_intr = intr & ~SC01ICR_TI;
- tmp = *port->_intr;
-
- if (ch == 0x0a) {
- *port->_txb = 0x0d;
- while (*port->_status & SC01STR_TBF)
- continue;
- }
-
- *port->_txb = ch;
- while (*port->_status & SC01STR_TBF)
- continue;
-
- /* restore the Tx interrupt flag */
- *port->_intr = intr;
- tmp = *port->_intr;
-}
-
-#endif /* CONFIG_CONSOLE_POLL */
diff --git a/arch/mn10300/kernel/mn10300-serial.h b/arch/mn10300/kernel/mn10300-serial.h
deleted file mode 100644
index 01791c68ea1f..000000000000
--- a/arch/mn10300/kernel/mn10300-serial.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* MN10300 On-chip serial port driver definitions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _MN10300_SERIAL_H
-#define _MN10300_SERIAL_H
-
-#ifndef __ASSEMBLY__
-#include <linux/serial_core.h>
-#include <linux/termios.h>
-#endif
-
-#include <asm/page.h>
-#include <asm/serial-regs.h>
-
-#define NR_PORTS 3 /* should be set 3 or 9 or 16 */
-
-#define MNSC_BUFFER_SIZE +(PAGE_SIZE / 2)
-
-/* intr_flags bits */
-#define MNSCx_RX_AVAIL 0x01
-#define MNSCx_RX_OVERF 0x02
-#define MNSCx_TX_SPACE 0x04
-#define MNSCx_TX_EMPTY 0x08
-
-/* tx_flags bits */
-#define MNSCx_TX_BREAK 0x01
-#define MNSCx_TX_STOP 0x02
-
-#ifndef __ASSEMBLY__
-
-struct mn10300_serial_port {
- char *rx_buffer; /* reception buffer base */
- unsigned rx_inp; /* pointer to rx input offset */
- unsigned rx_outp; /* pointer to rx output offset */
- u8 tx_xchar; /* high-priority XON/XOFF buffer */
- u8 tx_flags; /* transmit break/stop request */
- u8 intr_flags; /* interrupt flags */
- volatile u16 *rx_icr; /* Rx interrupt control register */
- volatile u16 *tx_icr; /* Tx interrupt control register */
- int rx_irq; /* reception IRQ */
- int tx_irq; /* transmission IRQ */
- int tm_irq; /* timer IRQ */
-
- const char *name; /* name of serial port */
- const char *rx_name; /* Rx interrupt handler name of serial port */
- const char *tx_name; /* Tx interrupt handler name of serial port */
- const char *tm_name; /* Timer interrupt handler name */
- unsigned short type; /* type of serial port */
- unsigned char isconsole; /* T if it's a console */
- volatile void *_iobase; /* pointer to base of I/O control regs */
- volatile u16 *_control; /* control register pointer */
- volatile u8 *_status; /* status register pointer */
- volatile u8 *_intr; /* interrupt register pointer */
- volatile u8 *_rxb; /* receive buffer register pointer */
- volatile u8 *_txb; /* transmit buffer register pointer */
- volatile u16 *_tmicr; /* timer interrupt control register */
- volatile u8 *_tmxmd; /* baud rate timer mode register */
- volatile u16 *_tmxbr; /* baud rate timer base register */
-
- /* this must come down here so that assembly can use BSET to access the
- * above fields */
- struct uart_port uart;
-
- unsigned short rx_brk; /* current break reception status */
- u16 tx_cts; /* current CTS status */
- int gdbstub; /* preemptively stolen by GDB stub */
-
- u8 clock_src; /* clock source */
-#define MNSCx_CLOCK_SRC_IOCLK 0
-#define MNSCx_CLOCK_SRC_IOBCLK 1
-
- u8 div_timer; /* timer used as divisor */
-#define MNSCx_DIV_TIMER_16BIT 0
-#define MNSCx_DIV_TIMER_8BIT 1
-
- u16 options; /* options */
-#define MNSCx_OPT_CTS 0x0001
-
- unsigned long ioclk; /* base clock rate */
-};
-
-#ifdef CONFIG_MN10300_TTYSM0
-extern struct mn10300_serial_port mn10300_serial_port_sif0;
-#endif
-
-#ifdef CONFIG_MN10300_TTYSM1
-extern struct mn10300_serial_port mn10300_serial_port_sif1;
-#endif
-
-#ifdef CONFIG_MN10300_TTYSM2
-extern struct mn10300_serial_port mn10300_serial_port_sif2;
-#endif
-
-extern struct mn10300_serial_port *mn10300_serial_ports[];
-
-struct mn10300_serial_int {
- struct mn10300_serial_port *port;
- asmlinkage void (*vdma)(void);
-};
-
-extern struct mn10300_serial_int mn10300_serial_int_tbl[];
-
-extern asmlinkage void mn10300_serial_vdma_interrupt(void);
-extern asmlinkage void mn10300_serial_vdma_rx_handler(void);
-extern asmlinkage void mn10300_serial_vdma_tx_handler(void);
-
-#endif /* __ASSEMBLY__ */
-
-#if defined(CONFIG_GDBSTUB_ON_TTYSM0)
-#define SCgSTR SC0STR
-#define SCgRXB SC0RXB
-#define SCgRXIRQ SC0RXIRQ
-#elif defined(CONFIG_GDBSTUB_ON_TTYSM1)
-#define SCgSTR SC1STR
-#define SCgRXB SC1RXB
-#define SCgRXIRQ SC1RXIRQ
-#elif defined(CONFIG_GDBSTUB_ON_TTYSM2)
-#define SCgSTR SC2STR
-#define SCgRXB SC2RXB
-#define SCgRXIRQ SC2RXIRQ
-#endif
-
-#endif /* _MN10300_SERIAL_H */
diff --git a/arch/mn10300/kernel/mn10300-watchdog-low.S b/arch/mn10300/kernel/mn10300-watchdog-low.S
deleted file mode 100644
index 34f8773de7d0..000000000000
--- a/arch/mn10300/kernel/mn10300-watchdog-low.S
+++ /dev/null
@@ -1,66 +0,0 @@
-###############################################################################
-#
-# MN10300 Watchdog interrupt handler
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/intctl-regs.h>
-#include <asm/timer-regs.h>
-#include <asm/frame.inc>
-#include <linux/threads.h>
-
- .text
-
-###############################################################################
-#
-# Watchdog handler entry point
-# - special non-maskable interrupt
-#
-###############################################################################
- .globl watchdog_handler
- .type watchdog_handler,@function
-watchdog_handler:
- add -4,sp
- SAVE_ALL
-
- mov 0xffffffff,d0
- mov d0,(REG_ORIG_D0,fp)
-
- mov fp,d0
- lsr 2,d1
- call watchdog_interrupt[],0 # watchdog_interrupt(regs,irq)
-
- jmp ret_from_intr
-
- .size watchdog_handler,.-watchdog_handler
-
-###############################################################################
-#
-# Watchdog touch entry point
-# - kept to absolute minimum (unfortunately, it's prototyped in linux/nmi.h so
-# we can't inline it)
-#
-###############################################################################
- .globl arch_touch_nmi_watchdog
- .type arch_touch_nmi_watchdog,@function
-arch_touch_nmi_watchdog:
- clr d0
- clr d1
- mov watchdog_alert_counter, a0
- setlb
- mov d0, (a0+)
- inc d1
- cmp NR_CPUS, d1
- lne
- ret [],0
-
- .size arch_touch_nmi_watchdog,.-arch_touch_nmi_watchdog
diff --git a/arch/mn10300/kernel/mn10300-watchdog.c b/arch/mn10300/kernel/mn10300-watchdog.c
deleted file mode 100644
index 0d5641beadf5..000000000000
--- a/arch/mn10300/kernel/mn10300-watchdog.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* MN10300 Watchdog timer
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/i386/kernel/nmi.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/nmi.h>
-#include <asm/processor.h>
-#include <linux/atomic.h>
-#include <asm/intctl-regs.h>
-#include <asm/rtc-regs.h>
-#include <asm/div64.h>
-#include <asm/smp.h>
-#include <asm/gdb-stub.h>
-#include <proc/clock.h>
-
-static DEFINE_SPINLOCK(watchdog_print_lock);
-static unsigned int watchdog;
-static unsigned int watchdog_hz = 1;
-unsigned int watchdog_alert_counter[NR_CPUS];
-
-EXPORT_SYMBOL(arch_touch_nmi_watchdog);
-
-/*
- * the best way to detect whether a CPU has a 'hard lockup' problem
- * is to check its timer makes IRQ counts. If they are not
- * changing then that CPU has some problem.
- *
- * since NMIs dont listen to _any_ locks, we have to be extremely
- * careful not to rely on unsafe variables. The printk might lock
- * up though, so we have to break up any console locks first ...
- * [when there will be more tty-related locks, break them up
- * here too!]
- */
-static unsigned int last_irq_sums[NR_CPUS];
-
-int __init check_watchdog(void)
-{
- irq_cpustat_t tmp[1];
-
- printk(KERN_INFO "Testing Watchdog... ");
-
- memcpy(tmp, irq_stat, sizeof(tmp));
- local_irq_enable();
- mdelay((10 * 1000) / watchdog_hz); /* wait 10 ticks */
- local_irq_disable();
-
- if (nmi_count(0) - tmp[0].__nmi_count <= 5) {
- printk(KERN_WARNING "CPU#%d: Watchdog appears to be stuck!\n",
- 0);
- return -1;
- }
-
- printk(KERN_INFO "OK.\n");
-
- /* now that we know it works we can reduce NMI frequency to something
- * more reasonable; makes a difference in some configs
- */
- watchdog_hz = 1;
-
- return 0;
-}
-
-static int __init setup_watchdog(char *str)
-{
- unsigned tmp;
- int opt;
- u8 ctr;
-
- get_option(&str, &opt);
- if (opt != 1)
- return 0;
-
- watchdog = opt;
- if (watchdog) {
- set_intr_stub(EXCEP_WDT, watchdog_handler);
- ctr = WDCTR_WDCK_65536th;
- WDCTR = WDCTR_WDRST | ctr;
- WDCTR = ctr;
- tmp = WDCTR;
-
- tmp = __muldiv64u(1 << (16 + ctr * 2), 1000000, MN10300_WDCLK);
- tmp = 1000000000 / tmp;
- watchdog_hz = (tmp + 500) / 1000;
- }
-
- return 1;
-}
-
-__setup("watchdog=", setup_watchdog);
-
-void __init watchdog_go(void)
-{
- u8 wdt;
-
- if (watchdog) {
- printk(KERN_INFO "Watchdog: running at %uHz\n", watchdog_hz);
- wdt = WDCTR & ~WDCTR_WDCNE;
- WDCTR = wdt | WDCTR_WDRST;
- wdt = WDCTR;
- WDCTR = wdt | WDCTR_WDCNE;
- wdt = WDCTR;
-
- check_watchdog();
- }
-}
-
-#ifdef CONFIG_SMP
-static void watchdog_dump_register(void *dummy)
-{
- printk(KERN_ERR "--- Register Dump (CPU%d) ---\n", CPUID);
- show_registers(current_frame());
-}
-#endif
-
-asmlinkage
-void watchdog_interrupt(struct pt_regs *regs, enum exception_code excep)
-{
- /*
- * Since current-> is always on the stack, and we always switch
- * the stack NMI-atomically, it's safe to use smp_processor_id().
- */
- int sum, cpu;
- int irq = NMIIRQ;
- u8 wdt, tmp;
-
- wdt = WDCTR & ~WDCTR_WDCNE;
- WDCTR = wdt;
- tmp = WDCTR;
- NMICR = NMICR_WDIF;
-
- nmi_count(smp_processor_id())++;
- kstat_incr_irq_this_cpu(irq);
-
- for_each_online_cpu(cpu) {
-
- sum = irq_stat[cpu].__irq_count;
-
- if ((last_irq_sums[cpu] == sum)
-#if defined(CONFIG_GDBSTUB) && defined(CONFIG_SMP)
- && !(CHK_GDBSTUB_BUSY()
- || atomic_read(&cpu_doing_single_step))
-#endif
- ) {
- /*
- * Ayiee, looks like this CPU is stuck ...
- * wait a few IRQs (5 seconds) before doing the oops ...
- */
- watchdog_alert_counter[cpu]++;
- if (watchdog_alert_counter[cpu] == 5 * watchdog_hz) {
- spin_lock(&watchdog_print_lock);
- /*
- * We are in trouble anyway, lets at least try
- * to get a message out.
- */
- bust_spinlocks(1);
- printk(KERN_ERR
- "NMI Watchdog detected LOCKUP on CPU%d,"
- " pc %08lx, registers:\n",
- cpu, regs->pc);
-#ifdef CONFIG_SMP
- printk(KERN_ERR
- "--- Register Dump (CPU%d) ---\n",
- CPUID);
-#endif
- show_registers(regs);
-#ifdef CONFIG_SMP
- smp_nmi_call_function(watchdog_dump_register,
- NULL, 1);
-#endif
- printk(KERN_NOTICE "console shuts up ...\n");
- console_silent();
- spin_unlock(&watchdog_print_lock);
- bust_spinlocks(0);
-#ifdef CONFIG_GDBSTUB
- if (CHK_GDBSTUB_BUSY_AND_ACTIVE())
- gdbstub_exception(regs, excep);
- else
- gdbstub_intercept(regs, excep);
-#endif
- do_exit(SIGSEGV);
- }
- } else {
- last_irq_sums[cpu] = sum;
- watchdog_alert_counter[cpu] = 0;
- }
- }
-
- WDCTR = wdt | WDCTR_WDRST;
- tmp = WDCTR;
- WDCTR = wdt | WDCTR_WDCNE;
- tmp = WDCTR;
-}
diff --git a/arch/mn10300/kernel/mn10300_ksyms.c b/arch/mn10300/kernel/mn10300_ksyms.c
deleted file mode 100644
index 66fb68d0ca8a..000000000000
--- a/arch/mn10300/kernel/mn10300_ksyms.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* MN10300 Miscellaneous and library kernel exports
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-
-
-EXPORT_SYMBOL(empty_zero_page);
-
-EXPORT_SYMBOL(change_bit);
-EXPORT_SYMBOL(test_and_change_bit);
-
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memmove);
-EXPORT_SYMBOL(memset);
-
-EXPORT_SYMBOL(strncpy_from_user);
-EXPORT_SYMBOL(clear_user);
-EXPORT_SYMBOL(__clear_user);
-EXPORT_SYMBOL(strnlen_user);
-
-extern u64 __ashrdi3(u64, unsigned);
-extern u64 __ashldi3(u64, unsigned);
-extern u64 __lshrdi3(u64, unsigned);
-extern s64 __negdi2(s64);
-extern int __ucmpdi2(u64, u64);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__negdi2);
-EXPORT_SYMBOL(__ucmpdi2);
diff --git a/arch/mn10300/kernel/module.c b/arch/mn10300/kernel/module.c
deleted file mode 100644
index 216ad23c9570..000000000000
--- a/arch/mn10300/kernel/module.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* MN10300 Kernel module helper routines
- *
- * Copyright (C) 2007, 2008, 2009 Red Hat, Inc. All Rights Reserved.
- * Written by Mark Salter (msalter@redhat.com)
- * - Derived from arch/i386/kernel/module.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public Licence as published by
- * the Free Software Foundation; either version 2 of the Licence, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public Licence for more details.
- *
- * You should have received a copy of the GNU General Public Licence
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <linux/bug.h>
-
-#if 0
-#define DEBUGP printk
-#else
-#define DEBUGP(fmt, ...)
-#endif
-
-static void reloc_put16(uint8_t *p, uint32_t val)
-{
- p[0] = val & 0xff;
- p[1] = (val >> 8) & 0xff;
-}
-
-static void reloc_put24(uint8_t *p, uint32_t val)
-{
- reloc_put16(p, val);
- p[2] = (val >> 16) & 0xff;
-}
-
-static void reloc_put32(uint8_t *p, uint32_t val)
-{
- reloc_put16(p, val);
- reloc_put16(p+2, val >> 16);
-}
-
-/*
- * apply a RELA relocation
- */
-int apply_relocate_add(Elf32_Shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct module *me)
-{
- unsigned int i, sym_diff_seen = 0;
- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf32_Sym *sym;
- Elf32_Addr relocation, sym_diff_val = 0;
- uint8_t *location;
- uint32_t value;
-
- DEBUGP("Applying relocate section %u to %u\n",
- relsec, sechdrs[relsec].sh_info);
-
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* this is where to make the change */
- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
- + rel[i].r_offset;
-
- /* this is the symbol the relocation is referring to (note that
- * all undefined symbols have been resolved by the caller) */
- sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
- + ELF32_R_SYM(rel[i].r_info);
-
- /* this is the adjustment to be made */
- relocation = sym->st_value + rel[i].r_addend;
-
- if (sym_diff_seen) {
- switch (ELF32_R_TYPE(rel[i].r_info)) {
- case R_MN10300_32:
- case R_MN10300_24:
- case R_MN10300_16:
- case R_MN10300_8:
- relocation -= sym_diff_val;
- sym_diff_seen = 0;
- break;
- default:
- printk(KERN_ERR "module %s: Unexpected SYM_DIFF relocation: %u\n",
- me->name, ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
- }
-
- switch (ELF32_R_TYPE(rel[i].r_info)) {
- /* for the first four relocation types, we simply
- * store the adjustment at the location given */
- case R_MN10300_32:
- reloc_put32(location, relocation);
- break;
- case R_MN10300_24:
- reloc_put24(location, relocation);
- break;
- case R_MN10300_16:
- reloc_put16(location, relocation);
- break;
- case R_MN10300_8:
- *location = relocation;
- break;
-
- /* for the next three relocation types, we write the
- * adjustment with the address subtracted over the
- * value at the location given */
- case R_MN10300_PCREL32:
- value = relocation - (uint32_t) location;
- reloc_put32(location, value);
- break;
- case R_MN10300_PCREL16:
- value = relocation - (uint32_t) location;
- reloc_put16(location, value);
- break;
- case R_MN10300_PCREL8:
- *location = relocation - (uint32_t) location;
- break;
-
- case R_MN10300_SYM_DIFF:
- /* This is used to adjust the next reloc as required
- * by relaxation. */
- sym_diff_seen = 1;
- sym_diff_val = sym->st_value;
- break;
-
- case R_MN10300_ALIGN:
- /* Just ignore the ALIGN relocs.
- * Only interesting if kernel performed relaxation. */
- continue;
-
- default:
- printk(KERN_ERR "module %s: Unknown relocation: %u\n",
- me->name, ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
- }
- if (sym_diff_seen) {
- printk(KERN_ERR "module %s: Nothing follows SYM_DIFF relocation: %u\n",
- me->name, ELF32_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
- return 0;
-}
diff --git a/arch/mn10300/kernel/process.c b/arch/mn10300/kernel/process.c
deleted file mode 100644
index 7c475fd99c46..000000000000
--- a/arch/mn10300/kernel/process.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* MN10300 Process handling code
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/reboot.h>
-#include <linux/percpu.h>
-#include <linux/err.h>
-#include <linux/fs.h>
-#include <linux/slab.h>
-#include <linux/rcupdate.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mmu_context.h>
-#include <asm/fpu.h>
-#include <asm/reset-regs.h>
-#include <asm/gdb-stub.h>
-#include "internal.h"
-
-/*
- * power off function, if any
- */
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-/*
- * On SMP it's slightly faster (but much more power-consuming!)
- * to poll the ->work.need_resched flag instead of waiting for the
- * cross-CPU IPI to arrive. Use this option with caution.
- *
- * tglx: No idea why this depends on HOTPLUG_CPU !?!
- */
-#if !defined(CONFIG_SMP) || defined(CONFIG_HOTPLUG_CPU)
-void arch_cpu_idle(void)
-{
- safe_halt();
-}
-#endif
-
-void machine_restart(char *cmd)
-{
-#ifdef CONFIG_KERNEL_DEBUGGER
- gdbstub_exit(0);
-#endif
-
-#ifdef mn10300_unit_hard_reset
- mn10300_unit_hard_reset();
-#else
- mn10300_proc_hard_reset();
-#endif
-}
-
-void machine_halt(void)
-{
-#ifdef CONFIG_KERNEL_DEBUGGER
- gdbstub_exit(0);
-#endif
-}
-
-void machine_power_off(void)
-{
-#ifdef CONFIG_KERNEL_DEBUGGER
- gdbstub_exit(0);
-#endif
-}
-
-void show_regs(struct pt_regs *regs)
-{
- show_regs_print_info(KERN_DEFAULT);
-}
-
-/*
- * free current thread data structures etc..
- */
-void exit_thread(struct task_struct *tsk)
-{
- exit_fpu(tsk);
-}
-
-void flush_thread(void)
-{
- flush_fpu();
-}
-
-void release_thread(struct task_struct *dead_task)
-{
-}
-
-/*
- * this gets called so that we can store lazy state into memory and copy the
- * current task into the new thread.
- */
-int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
-{
- unlazy_fpu(src);
- *dst = *src;
- return 0;
-}
-
-/*
- * set up the kernel stack for a new thread and copy arch-specific thread
- * control information
- */
-int copy_thread(unsigned long clone_flags,
- unsigned long c_usp, unsigned long ustk_size,
- struct task_struct *p)
-{
- struct thread_info *ti = task_thread_info(p);
- struct pt_regs *c_regs;
- unsigned long c_ksp;
-
- c_ksp = (unsigned long) task_stack_page(p) + THREAD_SIZE;
-
- /* allocate the userspace exception frame and set it up */
- c_ksp -= sizeof(struct pt_regs);
- c_regs = (struct pt_regs *) c_ksp;
- c_ksp -= 12; /* allocate function call ABI slack */
-
- /* set up things up so the scheduler can start the new task */
- p->thread.uregs = c_regs;
- ti->frame = c_regs;
- p->thread.a3 = (unsigned long) c_regs;
- p->thread.sp = c_ksp;
- p->thread.wchan = p->thread.pc;
- p->thread.usp = c_usp;
-
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(c_regs, 0, sizeof(struct pt_regs));
- c_regs->a0 = c_usp; /* function */
- c_regs->d0 = ustk_size; /* argument */
- local_save_flags(c_regs->epsw);
- c_regs->epsw |= EPSW_IE | EPSW_IM_7;
- p->thread.pc = (unsigned long) ret_from_kernel_thread;
- return 0;
- }
- *c_regs = *current_pt_regs();
- if (c_usp)
- c_regs->sp = c_usp;
- c_regs->epsw &= ~EPSW_FE; /* my FPU */
-
- /* the new TLS pointer is passed in as arg #5 to sys_clone() */
- if (clone_flags & CLONE_SETTLS)
- c_regs->e2 = current_frame()->d3;
-
- p->thread.pc = (unsigned long) ret_from_fork;
-
- return 0;
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
- return p->thread.wchan;
-}
diff --git a/arch/mn10300/kernel/profile-low.S b/arch/mn10300/kernel/profile-low.S
deleted file mode 100644
index 94ffac12d02d..000000000000
--- a/arch/mn10300/kernel/profile-low.S
+++ /dev/null
@@ -1,72 +0,0 @@
-###############################################################################
-#
-# Fast profiling interrupt handler
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/segment.h>
-#include <asm/smp.h>
-#include <asm/intctl-regs.h>
-#include <asm/timer-regs.h>
-
-#define pi break
-
- .balign 4
-counter:
- .long -1
-
-###############################################################################
-#
-# Profiling interrupt entry point
-# - intended to run at interrupt priority 1
-#
-###############################################################################
-ENTRY(profile_handler)
- movm [d2,d3,a2],(sp)
-
- # ignore userspace
- mov (12,sp),d2
- and EPSW_nSL,d2
- bne out
-
- # do nothing if there's no buffer
- mov (prof_buffer),a2
- and a2,a2
- beq out
- or 0x20000000,a2
-
- # calculate relative position in text segment
- mov (16,sp),d2
- sub _stext,d2
- mov (prof_shift),d3
- lsr d3,d2
- mov (prof_len),d3
- cmp d3,d2
- bcc outside_text
-
- # increment the appropriate profile bucket
-do_inc:
- asl2 d2
- mov (a2,d2),d3
- inc d3
- mov d3,(a2,d2)
-out:
- mov GxICR_DETECT,d2
- movbu d2,(TM11ICR) # ACK the interrupt
- movbu (TM11ICR),d2
- movm (sp),[d2,d3,a2]
- rti
-
-outside_text:
- sub 1,d3
- mov d3,d2
- bra do_inc
diff --git a/arch/mn10300/kernel/profile.c b/arch/mn10300/kernel/profile.c
deleted file mode 100644
index 4f342f75d00c..000000000000
--- a/arch/mn10300/kernel/profile.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* MN10300 Profiling setup
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-/*
- * initialise the profiling if enabled
- * - using with gdbstub will give anomalous results
- * - can't be used with gdbstub if running at IRQ priority 0
- */
-static __init int profile_init(void)
-{
- u16 tmp;
-
- if (!prof_buffer)
- return 0;
-
- /* use timer 11 to drive the profiling interrupts */
- set_intr_stub(EXCEP_IRQ_LEVEL0, profile_handler);
-
- /* set IRQ priority at which to run */
- set_intr_level(TM11IRQ, GxICR_LEVEL_0);
-
- /* set up timer 11
- * - source: (IOCLK 33MHz)*2 = 66MHz
- * - frequency: (33330000*2) / 8 / 20625 = 202Hz
- */
- TM11BR = 20625 - 1;
- TM11MD = TM8MD_SRC_IOCLK_8;
- TM11MD |= TM8MD_INIT_COUNTER;
- TM11MD &= ~TM8MD_INIT_COUNTER;
- TM11MD |= TM8MD_COUNT_ENABLE;
-
- TM11ICR |= GxICR_ENABLE;
- tmp = TM11ICR;
-
- printk(KERN_INFO "Profiling initiated on timer 11, priority 0, %uHz\n",
- MN10300_IOCLK / 8 / (TM11BR + 1));
- printk(KERN_INFO "Profile histogram stored %p-%p\n",
- prof_buffer, (u8 *)(prof_buffer + prof_len) - 1);
-
- return 0;
-}
-
-__initcall(profile_init);
diff --git a/arch/mn10300/kernel/ptrace.c b/arch/mn10300/kernel/ptrace.c
deleted file mode 100644
index 8009876a7ac4..000000000000
--- a/arch/mn10300/kernel/ptrace.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/* MN10300 Process tracing
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/regset.h>
-#include <linux/elf.h>
-#include <linux/tracehook.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/cacheflush.h>
-#include <asm/fpu.h>
-#include <asm/asm-offsets.h>
-
-/*
- * translate ptrace register IDs into struct pt_regs offsets
- */
-static const u8 ptrace_regid_to_frame[] = {
- [PT_A3 << 2] = REG_A3,
- [PT_A2 << 2] = REG_A2,
- [PT_D3 << 2] = REG_D3,
- [PT_D2 << 2] = REG_D2,
- [PT_MCVF << 2] = REG_MCVF,
- [PT_MCRL << 2] = REG_MCRL,
- [PT_MCRH << 2] = REG_MCRH,
- [PT_MDRQ << 2] = REG_MDRQ,
- [PT_E1 << 2] = REG_E1,
- [PT_E0 << 2] = REG_E0,
- [PT_E7 << 2] = REG_E7,
- [PT_E6 << 2] = REG_E6,
- [PT_E5 << 2] = REG_E5,
- [PT_E4 << 2] = REG_E4,
- [PT_E3 << 2] = REG_E3,
- [PT_E2 << 2] = REG_E2,
- [PT_SP << 2] = REG_SP,
- [PT_LAR << 2] = REG_LAR,
- [PT_LIR << 2] = REG_LIR,
- [PT_MDR << 2] = REG_MDR,
- [PT_A1 << 2] = REG_A1,
- [PT_A0 << 2] = REG_A0,
- [PT_D1 << 2] = REG_D1,
- [PT_D0 << 2] = REG_D0,
- [PT_ORIG_D0 << 2] = REG_ORIG_D0,
- [PT_EPSW << 2] = REG_EPSW,
- [PT_PC << 2] = REG_PC,
-};
-
-static inline int get_stack_long(struct task_struct *task, int offset)
-{
- return *(unsigned long *)
- ((unsigned long) task->thread.uregs + offset);
-}
-
-static inline
-int put_stack_long(struct task_struct *task, int offset, unsigned long data)
-{
- unsigned long stack;
-
- stack = (unsigned long) task->thread.uregs + offset;
- *(unsigned long *) stack = data;
- return 0;
-}
-
-/*
- * retrieve the contents of MN10300 userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* we need to skip regs->next */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs, 0, PT_ORIG_D0 * sizeof(long));
- if (ret < 0)
- return ret;
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- &regs->orig_d0, PT_ORIG_D0 * sizeof(long),
- NR_PTREGS * sizeof(long));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- NR_PTREGS * sizeof(long), -1);
-}
-
-/*
- * update the contents of the MN10300 userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- unsigned long tmp;
- int ret;
-
- /* we need to skip regs->next */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs, 0, PT_ORIG_D0 * sizeof(long));
- if (ret < 0)
- return ret;
-
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &regs->orig_d0, PT_ORIG_D0 * sizeof(long),
- PT_EPSW * sizeof(long));
- if (ret < 0)
- return ret;
-
- /* we need to mask off changes to EPSW */
- tmp = regs->epsw;
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &tmp, PT_EPSW * sizeof(long),
- PT_PC * sizeof(long));
- tmp &= EPSW_FLAG_V | EPSW_FLAG_C | EPSW_FLAG_N | EPSW_FLAG_Z;
- tmp |= regs->epsw & ~(EPSW_FLAG_V | EPSW_FLAG_C | EPSW_FLAG_N |
- EPSW_FLAG_Z);
- regs->epsw = tmp;
-
- if (ret < 0)
- return ret;
-
- /* and finally load the PC */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &regs->pc, PT_PC * sizeof(long),
- NR_PTREGS * sizeof(long));
-
- if (ret < 0)
- return ret;
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- NR_PTREGS * sizeof(long), -1);
-}
-
-/*
- * retrieve the contents of MN10300 userspace FPU registers
- */
-static int fpuregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct fpu_state_struct *fpregs = &target->thread.fpu_state;
- int ret;
-
- unlazy_fpu(target);
-
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- fpregs, 0, sizeof(*fpregs));
- if (ret < 0)
- return ret;
-
- return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(*fpregs), -1);
-}
-
-/*
- * update the contents of the MN10300 userspace FPU registers
- */
-static int fpuregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct fpu_state_struct fpu_state = target->thread.fpu_state;
- int ret;
-
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- &fpu_state, 0, sizeof(fpu_state));
- if (ret < 0)
- return ret;
-
- fpu_kill_state(target);
- target->thread.fpu_state = fpu_state;
- set_using_fpu(target);
-
- return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- sizeof(fpu_state), -1);
-}
-
-/*
- * determine if the FPU registers have actually been used
- */
-static int fpuregs_active(struct task_struct *target,
- const struct user_regset *regset)
-{
- return is_using_fpu(target) ? regset->n : 0;
-}
-
-/*
- * Define the register sets available on the MN10300 under Linux
- */
-enum mn10300_regset {
- REGSET_GENERAL,
- REGSET_FPU,
-};
-
-static const struct user_regset mn10300_regsets[] = {
- /*
- * General register format is:
- * A3, A2, D3, D2, MCVF, MCRL, MCRH, MDRQ
- * E1, E0, E7...E2, SP, LAR, LIR, MDR
- * A1, A0, D1, D0, ORIG_D0, EPSW, PC
- */
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = ELF_NGREG,
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
- /*
- * FPU register format is:
- * FS0-31, FPCR
- */
- [REGSET_FPU] = {
- .core_note_type = NT_PRFPREG,
- .n = sizeof(struct fpu_state_struct) / sizeof(long),
- .size = sizeof(long),
- .align = sizeof(long),
- .get = fpuregs_get,
- .set = fpuregs_set,
- .active = fpuregs_active,
- },
-};
-
-static const struct user_regset_view user_mn10300_native_view = {
- .name = "mn10300",
- .e_machine = EM_MN10300,
- .regsets = mn10300_regsets,
- .n = ARRAY_SIZE(mn10300_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_mn10300_native_view;
-}
-
-/*
- * set the single-step bit
- */
-void user_enable_single_step(struct task_struct *child)
-{
-#ifndef CONFIG_MN10300_USING_JTAG
- struct user *dummy = NULL;
- long tmp;
-
- tmp = get_stack_long(child, (unsigned long) &dummy->regs.epsw);
- tmp |= EPSW_T;
- put_stack_long(child, (unsigned long) &dummy->regs.epsw, tmp);
-#endif
-}
-
-/*
- * make sure the single-step bit is not set
- */
-void user_disable_single_step(struct task_struct *child)
-{
-#ifndef CONFIG_MN10300_USING_JTAG
- struct user *dummy = NULL;
- long tmp;
-
- tmp = get_stack_long(child, (unsigned long) &dummy->regs.epsw);
- tmp &= ~EPSW_T;
- put_stack_long(child, (unsigned long) &dummy->regs.epsw, tmp);
-#endif
-}
-
-void ptrace_disable(struct task_struct *child)
-{
- user_disable_single_step(child);
-}
-
-/*
- * handle the arch-specific side of process tracing
- */
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- unsigned long tmp;
- int ret;
- unsigned long __user *datap = (unsigned long __user *) data;
-
- switch (request) {
- /* read the word at location addr in the USER area. */
- case PTRACE_PEEKUSR:
- ret = -EIO;
- if ((addr & 3) || addr > sizeof(struct user) - 3)
- break;
-
- tmp = 0; /* Default return condition */
- if (addr < NR_PTREGS << 2)
- tmp = get_stack_long(child,
- ptrace_regid_to_frame[addr]);
- ret = put_user(tmp, datap);
- break;
-
- /* write the word at location addr in the USER area */
- case PTRACE_POKEUSR:
- ret = -EIO;
- if ((addr & 3) || addr > sizeof(struct user) - 3)
- break;
-
- ret = 0;
- if (addr < NR_PTREGS << 2)
- ret = put_stack_long(child, ptrace_regid_to_frame[addr],
- data);
- break;
-
- case PTRACE_GETREGS: /* Get all integer regs from the child. */
- return copy_regset_to_user(child, &user_mn10300_native_view,
- REGSET_GENERAL,
- 0, NR_PTREGS * sizeof(long),
- datap);
-
- case PTRACE_SETREGS: /* Set all integer regs in the child. */
- return copy_regset_from_user(child, &user_mn10300_native_view,
- REGSET_GENERAL,
- 0, NR_PTREGS * sizeof(long),
- datap);
-
- case PTRACE_GETFPREGS: /* Get the child FPU state. */
- return copy_regset_to_user(child, &user_mn10300_native_view,
- REGSET_FPU,
- 0, sizeof(struct fpu_state_struct),
- datap);
-
- case PTRACE_SETFPREGS: /* Set the child FPU state. */
- return copy_regset_from_user(child, &user_mn10300_native_view,
- REGSET_FPU,
- 0, sizeof(struct fpu_state_struct),
- datap);
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-/*
- * handle tracing of system call entry
- * - return the revised system call number or ULONG_MAX to cause ENOSYS
- */
-asmlinkage unsigned long syscall_trace_entry(struct pt_regs *regs)
-{
- if (tracehook_report_syscall_entry(regs))
- /* tracing decided this syscall should not happen, so
- * We'll return a bogus call number to get an ENOSYS
- * error, but leave the original number in
- * regs->orig_d0
- */
- return ULONG_MAX;
-
- return regs->orig_d0;
-}
-
-/*
- * handle tracing of system call exit
- */
-asmlinkage void syscall_trace_exit(struct pt_regs *regs)
-{
- tracehook_report_syscall_exit(regs, 0);
-}
diff --git a/arch/mn10300/kernel/rtc.c b/arch/mn10300/kernel/rtc.c
deleted file mode 100644
index f81f37025072..000000000000
--- a/arch/mn10300/kernel/rtc.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* MN10300 RTC management
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/mc146818rtc.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-
-#include <asm/rtc-regs.h>
-#include <asm/rtc.h>
-
-DEFINE_SPINLOCK(rtc_lock);
-EXPORT_SYMBOL(rtc_lock);
-
-static const __initdata struct resource res[] = {
- DEFINE_RES_IO(RTC_PORT(0), RTC_IO_EXTENT),
- DEFINE_RES_IRQ(RTC_IRQ),
-};
-
-/*
- * calibrate the TSC clock against the RTC
- */
-void __init calibrate_clock(void)
-{
- unsigned char status;
-
- /* make sure the RTC is running and is set to operate in 24hr mode */
- status = RTSRC;
- RTCRB |= RTCRB_SET;
- RTCRB |= RTCRB_TM_24HR;
- RTCRB &= ~RTCRB_DM_BINARY;
- RTCRA |= RTCRA_DVR;
- RTCRA &= ~RTCRA_DVR;
- RTCRB &= ~RTCRB_SET;
-
- platform_device_register_simple("rtc_cmos", -1, res, ARRAY_SIZE(res));
-}
diff --git a/arch/mn10300/kernel/setup.c b/arch/mn10300/kernel/setup.c
deleted file mode 100644
index 1b3d80d8a171..000000000000
--- a/arch/mn10300/kernel/setup.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* MN10300 Arch-specific initialisation
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/user.h>
-#include <linux/tty.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/bootmem.h>
-#include <linux/seq_file.h>
-#include <linux/cpu.h>
-#include <asm/processor.h>
-#include <linux/console.h>
-#include <linux/uaccess.h>
-#include <asm/setup.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <proc/proc.h>
-#include <asm/fpu.h>
-#include <asm/sections.h>
-
-struct mn10300_cpuinfo boot_cpu_data;
-
-static char __initdata cmd_line[COMMAND_LINE_SIZE];
-char redboot_command_line[COMMAND_LINE_SIZE] =
- "console=ttyS0,115200 root=/dev/mtdblock3 rw";
-
-char __initdata redboot_platform_name[COMMAND_LINE_SIZE];
-
-static struct resource code_resource = {
- .start = 0x100000,
- .end = 0,
- .name = "Kernel code",
-};
-
-static struct resource data_resource = {
- .start = 0,
- .end = 0,
- .name = "Kernel data",
-};
-
-static unsigned long __initdata phys_memory_base;
-static unsigned long __initdata phys_memory_end;
-static unsigned long __initdata memory_end;
-unsigned long memory_size;
-
-struct thread_info *__current_ti = &init_thread_union.thread_info;
-struct task_struct *__current = &init_task;
-
-#define mn10300_known_cpus 5
-static const char *const mn10300_cputypes[] = {
- "am33-1",
- "am33-2",
- "am34-1",
- "am33-3",
- "am34-2",
- "unknown"
-};
-
-/*
- * Pick out the memory size. We look for mem=size,
- * where size is "size[KkMm]"
- */
-static int __init early_mem(char *p)
-{
- memory_size = memparse(p, &p);
-
- if (memory_size == 0)
- panic("Memory size not known\n");
-
- return 0;
-}
-early_param("mem", early_mem);
-
-/*
- * architecture specific setup
- */
-void __init setup_arch(char **cmdline_p)
-{
- unsigned long bootmap_size;
- unsigned long kstart_pfn, start_pfn, free_pfn, end_pfn;
-
- cpu_init();
- unit_setup();
- smp_init_cpus();
-
- /* save unparsed command line copy for /proc/cmdline */
- strlcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
-
- /* populate cmd_line too for later use, preserving boot_command_line */
- strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
- *cmdline_p = cmd_line;
-
- parse_early_param();
-
- memory_end = (unsigned long) CONFIG_KERNEL_RAM_BASE_ADDRESS +
- memory_size;
- if (memory_end > phys_memory_end)
- memory_end = phys_memory_end;
-
- init_mm.start_code = (unsigned long)&_text;
- init_mm.end_code = (unsigned long) &_etext;
- init_mm.end_data = (unsigned long) &_edata;
- init_mm.brk = (unsigned long) &_end;
-
- code_resource.start = virt_to_bus(&_text);
- code_resource.end = virt_to_bus(&_etext)-1;
- data_resource.start = virt_to_bus(&_etext);
- data_resource.end = virt_to_bus(&_edata)-1;
-
- start_pfn = (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT);
- kstart_pfn = PFN_UP(__pa(&_text));
- free_pfn = PFN_UP(__pa(&_end));
- end_pfn = PFN_DOWN(__pa(memory_end));
-
- bootmap_size = init_bootmem_node(&contig_page_data,
- free_pfn,
- start_pfn,
- end_pfn);
-
- if (kstart_pfn > start_pfn)
- free_bootmem(PFN_PHYS(start_pfn),
- PFN_PHYS(kstart_pfn - start_pfn));
-
- free_bootmem(PFN_PHYS(free_pfn),
- PFN_PHYS(end_pfn - free_pfn));
-
- /* If interrupt vector table is in main ram, then we need to
- reserve the page it is occupying. */
- if (CONFIG_INTERRUPT_VECTOR_BASE >= CONFIG_KERNEL_RAM_BASE_ADDRESS &&
- CONFIG_INTERRUPT_VECTOR_BASE < memory_end)
- reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, PAGE_SIZE,
- BOOTMEM_DEFAULT);
-
- reserve_bootmem(PAGE_ALIGN(PFN_PHYS(free_pfn)), bootmap_size,
- BOOTMEM_DEFAULT);
-
-#ifdef CONFIG_VT
-#if defined(CONFIG_VGA_CONSOLE)
- conswitchp = &vga_con;
-#elif defined(CONFIG_DUMMY_CONSOLE)
- conswitchp = &dummy_con;
-#endif
-#endif
-
- paging_init();
-}
-
-/*
- * perform CPU initialisation
- */
-void __init cpu_init(void)
-{
- unsigned long cpurev = CPUREV, type;
-
- type = (CPUREV & CPUREV_TYPE) >> CPUREV_TYPE_S;
- if (type > mn10300_known_cpus)
- type = mn10300_known_cpus;
-
- printk(KERN_INFO "Panasonic %s, rev %ld\n",
- mn10300_cputypes[type],
- (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S);
-
- get_mem_info(&phys_memory_base, &memory_size);
- phys_memory_end = phys_memory_base + memory_size;
-
- fpu_init_state();
-}
-
-static struct cpu cpu_devices[NR_CPUS];
-
-static int __init topology_init(void)
-{
- int i;
-
- for_each_present_cpu(i)
- register_cpu(&cpu_devices[i], i);
-
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-/*
- * Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
-#ifdef CONFIG_SMP
- struct mn10300_cpuinfo *c = v;
- unsigned long cpu_id = c - cpu_data;
- unsigned long cpurev = c->type, type, icachesz, dcachesz;
-#else /* CONFIG_SMP */
- unsigned long cpu_id = 0;
- unsigned long cpurev = CPUREV, type, icachesz, dcachesz;
-#endif /* CONFIG_SMP */
-
-#ifdef CONFIG_SMP
- if (!cpu_online(cpu_id))
- return 0;
-#endif
-
- type = (cpurev & CPUREV_TYPE) >> CPUREV_TYPE_S;
- if (type > mn10300_known_cpus)
- type = mn10300_known_cpus;
-
- icachesz =
- ((cpurev & CPUREV_ICWAY ) >> CPUREV_ICWAY_S) *
- ((cpurev & CPUREV_ICSIZE) >> CPUREV_ICSIZE_S) *
- 1024;
-
- dcachesz =
- ((cpurev & CPUREV_DCWAY ) >> CPUREV_DCWAY_S) *
- ((cpurev & CPUREV_DCSIZE) >> CPUREV_DCSIZE_S) *
- 1024;
-
- seq_printf(m,
- "processor : %ld\n"
- "vendor_id : " PROCESSOR_VENDOR_NAME "\n"
- "cpu core : %s\n"
- "cpu rev : %lu\n"
- "model name : " PROCESSOR_MODEL_NAME "\n"
- "icache size: %lu\n"
- "dcache size: %lu\n",
- cpu_id,
- mn10300_cputypes[type],
- (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S,
- icachesz,
- dcachesz
- );
-
- seq_printf(m,
- "ioclk speed: %lu.%02luMHz\n"
- "bogomips : %lu.%02lu\n\n",
- MN10300_IOCLK / 1000000,
- (MN10300_IOCLK / 10000) % 100,
-#ifdef CONFIG_SMP
- c->loops_per_jiffy / (500000 / HZ),
- (c->loops_per_jiffy / (5000 / HZ)) % 100
-#else /* CONFIG_SMP */
- loops_per_jiffy / (500000 / HZ),
- (loops_per_jiffy / (5000 / HZ)) % 100
-#endif /* CONFIG_SMP */
- );
-
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return *pos < NR_CPUS ? cpu_data + *pos : NULL;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
diff --git a/arch/mn10300/kernel/sigframe.h b/arch/mn10300/kernel/sigframe.h
deleted file mode 100644
index 0decba28ae84..000000000000
--- a/arch/mn10300/kernel/sigframe.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* MN10300 Signal frame definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-struct sigframe
-{
- void (*pretcode)(void);
- int sig;
- struct sigcontext *psc;
- struct sigcontext sc;
- struct fpucontext fpuctx;
- unsigned long extramask[_NSIG_WORDS-1];
- char retcode[8];
-};
-
-struct rt_sigframe
-{
- void (*pretcode)(void);
- int sig;
- struct siginfo *pinfo;
- void *puc;
- struct siginfo info;
- struct ucontext uc;
- struct fpucontext fpuctx;
- char retcode[8];
-};
diff --git a/arch/mn10300/kernel/signal.c b/arch/mn10300/kernel/signal.c
deleted file mode 100644
index 2f3cb5734235..000000000000
--- a/arch/mn10300/kernel/signal.c
+++ /dev/null
@@ -1,431 +0,0 @@
-/* MN10300 Signal handling
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/tty.h>
-#include <linux/personality.h>
-#include <linux/suspend.h>
-#include <linux/tracehook.h>
-#include <asm/cacheflush.h>
-#include <asm/ucontext.h>
-#include <linux/uaccess.h>
-#include <asm/fpu.h>
-#include "sigframe.h"
-
-#define DEBUG_SIG 0
-
-/*
- * do a signal return; undo the signal stack.
- */
-static int restore_sigcontext(struct pt_regs *regs,
- struct sigcontext __user *sc, long *_d0)
-{
- unsigned int err = 0;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- if (is_using_fpu(current))
- fpu_kill_state(current);
-
-#define COPY(x) err |= __get_user(regs->x, &sc->x)
- COPY(d1); COPY(d2); COPY(d3);
- COPY(a0); COPY(a1); COPY(a2); COPY(a3);
- COPY(e0); COPY(e1); COPY(e2); COPY(e3);
- COPY(e4); COPY(e5); COPY(e6); COPY(e7);
- COPY(lar); COPY(lir);
- COPY(mdr); COPY(mdrq);
- COPY(mcvf); COPY(mcrl); COPY(mcrh);
- COPY(sp); COPY(pc);
-#undef COPY
-
- {
- unsigned int tmpflags;
-#ifndef CONFIG_MN10300_USING_JTAG
-#define USER_EPSW (EPSW_FLAG_Z | EPSW_FLAG_N | EPSW_FLAG_C | EPSW_FLAG_V | \
- EPSW_T | EPSW_nAR)
-#else
-#define USER_EPSW (EPSW_FLAG_Z | EPSW_FLAG_N | EPSW_FLAG_C | EPSW_FLAG_V | \
- EPSW_nAR)
-#endif
- err |= __get_user(tmpflags, &sc->epsw);
- regs->epsw = (regs->epsw & ~USER_EPSW) |
- (tmpflags & USER_EPSW);
- regs->orig_d0 = -1; /* disable syscall checks */
- }
-
- {
- struct fpucontext *buf;
- err |= __get_user(buf, &sc->fpucontext);
- if (buf) {
- if (!access_ok(VERIFY_READ, buf, sizeof(*buf)))
- goto badframe;
- err |= fpu_restore_sigcontext(buf);
- }
- }
-
- err |= __get_user(*_d0, &sc->d0);
- return err;
-
-badframe:
- return 1;
-}
-
-/*
- * standard signal return syscall
- */
-asmlinkage long sys_sigreturn(void)
-{
- struct sigframe __user *frame;
- sigset_t set;
- long d0;
-
- frame = (struct sigframe __user *) current_frame()->sp;
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__get_user(set.sig[0], &frame->sc.oldmask))
- goto badframe;
-
- if (_NSIG_WORDS > 1 &&
- __copy_from_user(&set.sig[1], &frame->extramask,
- sizeof(frame->extramask)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(current_frame(), &frame->sc, &d0))
- goto badframe;
-
- return d0;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/*
- * realtime signal return syscall
- */
-asmlinkage long sys_rt_sigreturn(void)
-{
- struct rt_sigframe __user *frame;
- sigset_t set;
- long d0;
-
- frame = (struct rt_sigframe __user *) current_frame()->sp;
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(current_frame(), &frame->uc.uc_mcontext, &d0))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return d0;
-
-badframe:
- force_sig(SIGSEGV, current);
- return 0;
-}
-
-/*
- * store the userspace context into a signal frame
- */
-static int setup_sigcontext(struct sigcontext __user *sc,
- struct fpucontext *fpuctx,
- struct pt_regs *regs,
- unsigned long mask)
-{
- int tmp, err = 0;
-
-#define COPY(x) err |= __put_user(regs->x, &sc->x)
- COPY(d0); COPY(d1); COPY(d2); COPY(d3);
- COPY(a0); COPY(a1); COPY(a2); COPY(a3);
- COPY(e0); COPY(e1); COPY(e2); COPY(e3);
- COPY(e4); COPY(e5); COPY(e6); COPY(e7);
- COPY(lar); COPY(lir);
- COPY(mdr); COPY(mdrq);
- COPY(mcvf); COPY(mcrl); COPY(mcrh);
- COPY(sp); COPY(epsw); COPY(pc);
-#undef COPY
-
- tmp = fpu_setup_sigcontext(fpuctx);
- if (tmp < 0)
- err = 1;
- else
- err |= __put_user(tmp ? fpuctx : NULL, &sc->fpucontext);
-
- /* non-iBCS2 extensions.. */
- err |= __put_user(mask, &sc->oldmask);
-
- return err;
-}
-
-/*
- * determine which stack to use..
- */
-static inline void __user *get_sigframe(struct ksignal *ksig,
- struct pt_regs *regs,
- size_t frame_size)
-{
- unsigned long sp = sigsp(regs->sp, ksig);
-
- return (void __user *) ((sp - frame_size) & ~7UL);
-}
-
-/*
- * set up a normal signal frame
- */
-static int setup_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct sigframe __user *frame;
- int sig = ksig->sig;
-
- frame = get_sigframe(ksig, regs, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- if (__put_user(sig, &frame->sig) < 0 ||
- __put_user(&frame->sc, &frame->psc) < 0)
- return -EFAULT;
-
- if (setup_sigcontext(&frame->sc, &frame->fpuctx, regs, set->sig[0]))
- return -EFAULT;
-
- if (_NSIG_WORDS > 1) {
- if (__copy_to_user(frame->extramask, &set->sig[1],
- sizeof(frame->extramask)))
- return -EFAULT;
- }
-
- /* set up to return from userspace. If provided, use a stub already in
- * userspace */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode))
- return -EFAULT;
- } else {
- if (__put_user((void (*)(void))frame->retcode,
- &frame->pretcode))
- return -EFAULT;
- /* this is mov $,d0; syscall 0 */
- if (__put_user(0x2c, (char *)(frame->retcode + 0)) ||
- __put_user(__NR_sigreturn, (char *)(frame->retcode + 1)) ||
- __put_user(0x00, (char *)(frame->retcode + 2)) ||
- __put_user(0xf0, (char *)(frame->retcode + 3)) ||
- __put_user(0xe0, (char *)(frame->retcode + 4)))
- return -EFAULT;
- flush_icache_range((unsigned long) frame->retcode,
- (unsigned long) frame->retcode + 5);
- }
-
- /* set up registers for signal handler */
- regs->sp = (unsigned long) frame;
- regs->pc = (unsigned long) ksig->ka.sa.sa_handler;
- regs->d0 = sig;
- regs->d1 = (unsigned long) &frame->sc;
-
-#if DEBUG_SIG
- printk(KERN_DEBUG "SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
- sig, current->comm, current->pid, frame, regs->pc,
- frame->pretcode);
-#endif
-
- return 0;
-}
-
-/*
- * set up a realtime signal frame
- */
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- struct rt_sigframe __user *frame;
- int sig = ksig->sig;
-
- frame = get_sigframe(ksig, regs, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- if (__put_user(sig, &frame->sig) ||
- __put_user(&frame->info, &frame->pinfo) ||
- __put_user(&frame->uc, &frame->puc) ||
- copy_siginfo_to_user(&frame->info, &ksig->info))
- return -EFAULT;
-
- /* create the ucontext. */
- if (__put_user(0, &frame->uc.uc_flags) ||
- __put_user(0, &frame->uc.uc_link) ||
- __save_altstack(&frame->uc.uc_stack, regs->sp) ||
- setup_sigcontext(&frame->uc.uc_mcontext,
- &frame->fpuctx, regs, set->sig[0]) ||
- __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)))
- return -EFAULT;
-
- /* set up to return from userspace. If provided, use a stub already in
- * userspace */
- if (ksig->ka.sa.sa_flags & SA_RESTORER) {
- if (__put_user(ksig->ka.sa.sa_restorer, &frame->pretcode))
- return -EFAULT;
-
- } else {
- if (__put_user((void(*)(void))frame->retcode,
- &frame->pretcode) ||
- /* This is mov $,d0; syscall 0 */
- __put_user(0x2c, (char *)(frame->retcode + 0)) ||
- __put_user(__NR_rt_sigreturn,
- (char *)(frame->retcode + 1)) ||
- __put_user(0x00, (char *)(frame->retcode + 2)) ||
- __put_user(0xf0, (char *)(frame->retcode + 3)) ||
- __put_user(0xe0, (char *)(frame->retcode + 4)))
- return -EFAULT;
-
- flush_icache_range((u_long) frame->retcode,
- (u_long) frame->retcode + 5);
- }
-
- /* Set up registers for signal handler */
- regs->sp = (unsigned long) frame;
- regs->pc = (unsigned long) ksig->ka.sa.sa_handler;
- regs->d0 = sig;
- regs->d1 = (long) &frame->info;
-
-#if DEBUG_SIG
- printk(KERN_DEBUG "SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
- sig, current->comm, current->pid, frame, regs->pc,
- frame->pretcode);
-#endif
-
- return 0;
-}
-
-static inline void stepback(struct pt_regs *regs)
-{
- regs->pc -= 2;
- regs->orig_d0 = -1;
-}
-
-/*
- * handle the actual delivery of a signal to userspace
- */
-static int handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Are we from a system call? */
- if (regs->orig_d0 >= 0) {
- /* If so, check system call restarting.. */
- switch (regs->d0) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- regs->d0 = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->d0 = -EINTR;
- break;
- }
-
- /* fallthrough */
- case -ERESTARTNOINTR:
- regs->d0 = regs->orig_d0;
- stepback(regs);
- }
- }
-
- /* Set up the stack frame */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO)
- ret = setup_rt_frame(ksig, oldset, regs);
- else
- ret = setup_frame(ksig, oldset, regs);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
- return 0;
-}
-
-/*
- * handle a potential signal
- */
-static void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- if (get_signal(&ksig)) {
- handle_signal(&ksig, regs);
- return;
- }
-
- /* did we come from a system call? */
- if (regs->orig_d0 >= 0) {
- /* restart the system call - no handlers present */
- switch (regs->d0) {
- case -ERESTARTNOHAND:
- case -ERESTARTSYS:
- case -ERESTARTNOINTR:
- regs->d0 = regs->orig_d0;
- stepback(regs);
- break;
-
- case -ERESTART_RESTARTBLOCK:
- regs->d0 = __NR_restart_syscall;
- stepback(regs);
- break;
- }
- }
-
- /* if there's no signal to deliver, we just put the saved sigmask
- * back */
- restore_saved_sigmask();
-}
-
-/*
- * notification of userspace execution resumption
- * - triggered by current->work.notify_resume
- */
-asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags)
-{
- /* Pending single-step? */
- if (thread_info_flags & _TIF_SINGLESTEP) {
-#ifndef CONFIG_MN10300_USING_JTAG
- regs->epsw |= EPSW_T;
- clear_thread_flag(TIF_SINGLESTEP);
-#else
- BUG(); /* no h/w single-step if using JTAG unit */
-#endif
- }
-
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal(regs);
-
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(current_frame());
- }
-}
diff --git a/arch/mn10300/kernel/smp-low.S b/arch/mn10300/kernel/smp-low.S
deleted file mode 100644
index 71f1b2faaa0b..000000000000
--- a/arch/mn10300/kernel/smp-low.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SMP IPI low-level handler
- *
- * Copyright (C) 2006-2007 Matsushita Electric Industrial Co., Ltd.
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/thread_info.h>
-#include <asm/cpu-regs.h>
-#include <asm/intctl-regs.h>
-#include <proc/smp-regs.h>
-#include <asm/asm-offsets.h>
-#include <asm/frame.inc>
-
- .am33_2
-
-###############################################################################
-#
-# IPI interrupt handler
-#
-###############################################################################
- .globl mn10300_low_ipi_handler
-mn10300_low_ipi_handler:
- add -4,sp
- mov d0,(sp)
- movhu (IAGR),d0
- and IAGR_GN,d0
- lsr 0x2,d0
-#ifdef CONFIG_MN10300_CACHE_ENABLED
- cmp FLUSH_CACHE_IPI,d0
- beq mn10300_flush_cache_ipi
-#endif
- cmp SMP_BOOT_IRQ,d0
- beq mn10300_smp_boot_ipi
- /* OTHERS */
- mov (sp),d0
- add 4,sp
-#ifdef CONFIG_GDBSTUB
- jmp gdbstub_io_rx_handler
-#else
- jmp end
-#endif
-
-###############################################################################
-#
-# Cache flush IPI interrupt handler
-#
-###############################################################################
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-mn10300_flush_cache_ipi:
- mov (sp),d0
- add 4,sp
-
- /* FLUSH_CACHE_IPI */
- add -4,sp
- SAVE_ALL
- mov GxICR_DETECT,d2
- movbu d2,(GxICR(FLUSH_CACHE_IPI)) # ACK the interrupt
- movhu (GxICR(FLUSH_CACHE_IPI)),d2
- call smp_cache_interrupt[],0
- RESTORE_ALL
- jmp end
-#endif
-
-###############################################################################
-#
-# SMP boot CPU IPI interrupt handler
-#
-###############################################################################
-mn10300_smp_boot_ipi:
- /* clear interrupt */
- movhu (GxICR(SMP_BOOT_IRQ)),d0
- and ~GxICR_REQUEST,d0
- movhu d0,(GxICR(SMP_BOOT_IRQ))
- mov (sp),d0
- add 4,sp
-
- # get stack
- mov (CPUID),a0
- add -1,a0
- add a0,a0
- add a0,a0
- mov (start_stack,a0),a0
- mov a0,sp
- jmp initialize_secondary
-
-
-# Jump here after RTI to suppress the icache lookahead
-end:
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
deleted file mode 100644
index 35d2c3fe6f76..000000000000
--- a/arch/mn10300/kernel/smp.c
+++ /dev/null
@@ -1,1186 +0,0 @@
-/* SMP support routines.
- *
- * Copyright (C) 2006-2008 Panasonic Corporation
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/init.h>
-#include <linux/jiffies.h>
-#include <linux/cpumask.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task.h>
-#include <linux/profile.h>
-#include <linux/smp.h>
-#include <linux/cpu.h>
-#include <asm/tlbflush.h>
-#include <asm/bitops.h>
-#include <asm/processor.h>
-#include <asm/bug.h>
-#include <asm/exceptions.h>
-#include <asm/hardirq.h>
-#include <asm/fpu.h>
-#include <asm/mmu_context.h>
-#include <asm/thread_info.h>
-#include <asm/cpu-regs.h>
-#include <asm/intctl-regs.h>
-#include "internal.h"
-
-#ifdef CONFIG_HOTPLUG_CPU
-#include <asm/cacheflush.h>
-
-static unsigned long sleep_mode[NR_CPUS];
-
-static void run_sleep_cpu(unsigned int cpu);
-static void run_wakeup_cpu(unsigned int cpu);
-#endif /* CONFIG_HOTPLUG_CPU */
-
-/*
- * Debug Message function
- */
-
-#undef DEBUG_SMP
-#ifdef DEBUG_SMP
-#define Dprintk(fmt, ...) printk(KERN_DEBUG fmt, ##__VA_ARGS__)
-#else
-#define Dprintk(fmt, ...) no_printk(KERN_DEBUG fmt, ##__VA_ARGS__)
-#endif
-
-/* timeout value in msec for smp_nmi_call_function. zero is no timeout. */
-#define CALL_FUNCTION_NMI_IPI_TIMEOUT 0
-
-/*
- * Structure and data for smp_nmi_call_function().
- */
-struct nmi_call_data_struct {
- smp_call_func_t func;
- void *info;
- cpumask_t started;
- cpumask_t finished;
- int wait;
- char size_alignment[0]
- __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
-} __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
-
-static DEFINE_SPINLOCK(smp_nmi_call_lock);
-static struct nmi_call_data_struct *nmi_call_data;
-
-/*
- * Data structures and variables
- */
-static cpumask_t cpu_callin_map; /* Bitmask of callin CPUs */
-static cpumask_t cpu_callout_map; /* Bitmask of callout CPUs */
-cpumask_t cpu_boot_map; /* Bitmask of boot APs */
-unsigned long start_stack[NR_CPUS - 1];
-
-/*
- * Per CPU parameters
- */
-struct mn10300_cpuinfo cpu_data[NR_CPUS] __cacheline_aligned;
-
-static int cpucount; /* The count of boot CPUs */
-static cpumask_t smp_commenced_mask;
-cpumask_t cpu_initialized __initdata = CPU_MASK_NONE;
-
-/*
- * Function Prototypes
- */
-static int do_boot_cpu(int);
-static void smp_show_cpu_info(int cpu_id);
-static void smp_callin(void);
-static void smp_online(void);
-static void smp_store_cpu_info(int);
-static void smp_cpu_init(void);
-static void smp_tune_scheduling(void);
-static void send_IPI_mask(const cpumask_t *cpumask, int irq);
-static void init_ipi(void);
-
-/*
- * IPI Initialization interrupt definitions
- */
-static void mn10300_ipi_disable(unsigned int irq);
-static void mn10300_ipi_enable(unsigned int irq);
-static void mn10300_ipi_chip_disable(struct irq_data *d);
-static void mn10300_ipi_chip_enable(struct irq_data *d);
-static void mn10300_ipi_ack(struct irq_data *d);
-static void mn10300_ipi_nop(struct irq_data *d);
-
-static struct irq_chip mn10300_ipi_type = {
- .name = "cpu_ipi",
- .irq_disable = mn10300_ipi_chip_disable,
- .irq_enable = mn10300_ipi_chip_enable,
- .irq_ack = mn10300_ipi_ack,
- .irq_eoi = mn10300_ipi_nop
-};
-
-static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id);
-static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id);
-
-static struct irqaction reschedule_ipi = {
- .handler = smp_reschedule_interrupt,
- .flags = IRQF_NOBALANCING,
- .name = "smp reschedule IPI"
-};
-static struct irqaction call_function_ipi = {
- .handler = smp_call_function_interrupt,
- .flags = IRQF_NOBALANCING,
- .name = "smp call function IPI"
-};
-
-#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
-static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id);
-static struct irqaction local_timer_ipi = {
- .handler = smp_ipi_timer_interrupt,
- .flags = IRQF_NOBALANCING,
- .name = "smp local timer IPI"
-};
-#endif
-
-/**
- * init_ipi - Initialise the IPI mechanism
- */
-static void init_ipi(void)
-{
- unsigned long flags;
- u16 tmp16;
-
- /* set up the reschedule IPI */
- irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type,
- handle_percpu_irq);
- setup_irq(RESCHEDULE_IPI, &reschedule_ipi);
- set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV);
- mn10300_ipi_enable(RESCHEDULE_IPI);
-
- /* set up the call function IPI */
- irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type,
- handle_percpu_irq);
- setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi);
- set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV);
- mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI);
-
- /* set up the local timer IPI */
-#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \
- defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
- irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type,
- handle_percpu_irq);
- setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi);
- set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV);
- mn10300_ipi_enable(LOCAL_TIMER_IPI);
-#endif
-
-#ifdef CONFIG_MN10300_CACHE_ENABLED
- /* set up the cache flush IPI */
- irq_set_chip(FLUSH_CACHE_IPI, &mn10300_ipi_type);
- flags = arch_local_cli_save();
- __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(FLUSH_CACHE_GxICR_LV),
- mn10300_low_ipi_handler);
- GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT;
- mn10300_ipi_enable(FLUSH_CACHE_IPI);
- arch_local_irq_restore(flags);
-#endif
-
- /* set up the NMI call function IPI */
- irq_set_chip(CALL_FUNCTION_NMI_IPI, &mn10300_ipi_type);
- flags = arch_local_cli_save();
- GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT;
- tmp16 = GxICR(CALL_FUNCTION_NMI_IPI);
- arch_local_irq_restore(flags);
-
- /* set up the SMP boot IPI */
- flags = arch_local_cli_save();
- __set_intr_stub(NUM2EXCEP_IRQ_LEVEL(SMP_BOOT_GxICR_LV),
- mn10300_low_ipi_handler);
- arch_local_irq_restore(flags);
-
-#ifdef CONFIG_KERNEL_DEBUGGER
- irq_set_chip(DEBUGGER_NMI_IPI, &mn10300_ipi_type);
-#endif
-}
-
-/**
- * mn10300_ipi_shutdown - Shut down handling of an IPI
- * @irq: The IPI to be shut down.
- */
-static void mn10300_ipi_shutdown(unsigned int irq)
-{
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
-
- tmp = GxICR(irq);
- GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
- tmp = GxICR(irq);
-
- arch_local_irq_restore(flags);
-}
-
-/**
- * mn10300_ipi_enable - Enable an IPI
- * @irq: The IPI to be enabled.
- */
-static void mn10300_ipi_enable(unsigned int irq)
-{
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
-
- tmp = GxICR(irq);
- GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
- tmp = GxICR(irq);
-
- arch_local_irq_restore(flags);
-}
-
-static void mn10300_ipi_chip_enable(struct irq_data *d)
-{
- mn10300_ipi_enable(d->irq);
-}
-
-/**
- * mn10300_ipi_disable - Disable an IPI
- * @irq: The IPI to be disabled.
- */
-static void mn10300_ipi_disable(unsigned int irq)
-{
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
-
- tmp = GxICR(irq);
- GxICR(irq) = tmp & GxICR_LEVEL;
- tmp = GxICR(irq);
-
- arch_local_irq_restore(flags);
-}
-
-static void mn10300_ipi_chip_disable(struct irq_data *d)
-{
- mn10300_ipi_disable(d->irq);
-}
-
-
-/**
- * mn10300_ipi_ack - Acknowledge an IPI interrupt in the PIC
- * @irq: The IPI to be acknowledged.
- *
- * Clear the interrupt detection flag for the IPI on the appropriate interrupt
- * channel in the PIC.
- */
-static void mn10300_ipi_ack(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- unsigned long flags;
- u16 tmp;
-
- flags = arch_local_cli_save();
- GxICR_u8(irq) = GxICR_DETECT;
- tmp = GxICR(irq);
- arch_local_irq_restore(flags);
-}
-
-/**
- * mn10300_ipi_nop - Dummy IPI action
- * @irq: The IPI to be acted upon.
- */
-static void mn10300_ipi_nop(struct irq_data *d)
-{
-}
-
-/**
- * send_IPI_mask - Send IPIs to all CPUs in list
- * @cpumask: The list of CPUs to target.
- * @irq: The IPI request to be sent.
- *
- * Send the specified IPI to all the CPUs in the list, not waiting for them to
- * finish before returning. The caller is responsible for synchronisation if
- * that is needed.
- */
-static void send_IPI_mask(const cpumask_t *cpumask, int irq)
-{
- int i;
- u16 tmp;
-
- for (i = 0; i < NR_CPUS; i++) {
- if (cpumask_test_cpu(i, cpumask)) {
- /* send IPI */
- tmp = CROSS_GxICR(irq, i);
- CROSS_GxICR(irq, i) =
- tmp | GxICR_REQUEST | GxICR_DETECT;
- tmp = CROSS_GxICR(irq, i); /* flush write buffer */
- }
- }
-}
-
-/**
- * send_IPI_self - Send an IPI to this CPU.
- * @irq: The IPI request to be sent.
- *
- * Send the specified IPI to the current CPU.
- */
-void send_IPI_self(int irq)
-{
- send_IPI_mask(cpumask_of(smp_processor_id()), irq);
-}
-
-/**
- * send_IPI_allbutself - Send IPIs to all the other CPUs.
- * @irq: The IPI request to be sent.
- *
- * Send the specified IPI to all CPUs in the system barring the current one,
- * not waiting for them to finish before returning. The caller is responsible
- * for synchronisation if that is needed.
- */
-void send_IPI_allbutself(int irq)
-{
- cpumask_t cpumask;
-
- cpumask_copy(&cpumask, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &cpumask);
- send_IPI_mask(&cpumask, irq);
-}
-
-void arch_send_call_function_ipi_mask(const struct cpumask *mask)
-{
- BUG();
- /*send_IPI_mask(mask, CALL_FUNCTION_IPI);*/
-}
-
-void arch_send_call_function_single_ipi(int cpu)
-{
- send_IPI_mask(cpumask_of(cpu), CALL_FUNC_SINGLE_IPI);
-}
-
-/**
- * smp_send_reschedule - Send reschedule IPI to a CPU
- * @cpu: The CPU to target.
- */
-void smp_send_reschedule(int cpu)
-{
- send_IPI_mask(cpumask_of(cpu), RESCHEDULE_IPI);
-}
-
-/**
- * smp_nmi_call_function - Send a call function NMI IPI to all CPUs
- * @func: The function to ask to be run.
- * @info: The context data to pass to that function.
- * @wait: If true, wait (atomically) until function is run on all CPUs.
- *
- * Send a non-maskable request to all CPUs in the system, requesting them to
- * run the specified function with the given context data, and, potentially, to
- * wait for completion of that function on all CPUs.
- *
- * Returns 0 if successful, -ETIMEDOUT if we were asked to wait, but hit the
- * timeout.
- */
-int smp_nmi_call_function(smp_call_func_t func, void *info, int wait)
-{
- struct nmi_call_data_struct data;
- unsigned long flags;
- unsigned int cnt;
- int cpus, ret = 0;
-
- cpus = num_online_cpus() - 1;
- if (cpus < 1)
- return 0;
-
- data.func = func;
- data.info = info;
- cpumask_copy(&data.started, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &data.started);
- data.wait = wait;
- if (wait)
- data.finished = data.started;
-
- spin_lock_irqsave(&smp_nmi_call_lock, flags);
- nmi_call_data = &data;
- smp_mb();
-
- /* Send a message to all other CPUs and wait for them to respond */
- send_IPI_allbutself(CALL_FUNCTION_NMI_IPI);
-
- /* Wait for response */
- if (CALL_FUNCTION_NMI_IPI_TIMEOUT > 0) {
- for (cnt = 0;
- cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
- !cpumask_empty(&data.started);
- cnt++)
- mdelay(1);
-
- if (wait && cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT) {
- for (cnt = 0;
- cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
- !cpumask_empty(&data.finished);
- cnt++)
- mdelay(1);
- }
-
- if (cnt >= CALL_FUNCTION_NMI_IPI_TIMEOUT)
- ret = -ETIMEDOUT;
-
- } else {
- /* If timeout value is zero, wait until cpumask has been
- * cleared */
- while (!cpumask_empty(&data.started))
- barrier();
- if (wait)
- while (!cpumask_empty(&data.finished))
- barrier();
- }
-
- spin_unlock_irqrestore(&smp_nmi_call_lock, flags);
- return ret;
-}
-
-/**
- * smp_jump_to_debugger - Make other CPUs enter the debugger by sending an IPI
- *
- * Send a non-maskable request to all other CPUs in the system, instructing
- * them to jump into the debugger. The caller is responsible for checking that
- * the other CPUs responded to the instruction.
- *
- * The caller should make sure that this CPU's debugger IPI is disabled.
- */
-void smp_jump_to_debugger(void)
-{
- if (num_online_cpus() > 1)
- /* Send a message to all other CPUs */
- send_IPI_allbutself(DEBUGGER_NMI_IPI);
-}
-
-/**
- * stop_this_cpu - Callback to stop a CPU.
- * @unused: Callback context (ignored).
- */
-void stop_this_cpu(void *unused)
-{
- static volatile int stopflag;
- unsigned long flags;
-
-#ifdef CONFIG_GDBSTUB
- /* In case of single stepping smp_send_stop by other CPU,
- * clear procindebug to avoid deadlock.
- */
- atomic_set(&procindebug[smp_processor_id()], 0);
-#endif /* CONFIG_GDBSTUB */
-
- flags = arch_local_cli_save();
- set_cpu_online(smp_processor_id(), false);
-
- while (!stopflag)
- cpu_relax();
-
- set_cpu_online(smp_processor_id(), true);
- arch_local_irq_restore(flags);
-}
-
-/**
- * smp_send_stop - Send a stop request to all CPUs.
- */
-void smp_send_stop(void)
-{
- smp_nmi_call_function(stop_this_cpu, NULL, 0);
-}
-
-/**
- * smp_reschedule_interrupt - Reschedule IPI handler
- * @irq: The interrupt number.
- * @dev_id: The device ID.
- *
- * Returns IRQ_HANDLED to indicate we handled the interrupt successfully.
- */
-static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id)
-{
- scheduler_ipi();
- return IRQ_HANDLED;
-}
-
-/**
- * smp_call_function_interrupt - Call function IPI handler
- * @irq: The interrupt number.
- * @dev_id: The device ID.
- *
- * Returns IRQ_HANDLED to indicate we handled the interrupt successfully.
- */
-static irqreturn_t smp_call_function_interrupt(int irq, void *dev_id)
-{
- /* generic_smp_call_function_interrupt(); */
- generic_smp_call_function_single_interrupt();
- return IRQ_HANDLED;
-}
-
-/**
- * smp_nmi_call_function_interrupt - Non-maskable call function IPI handler
- */
-void smp_nmi_call_function_interrupt(void)
-{
- smp_call_func_t func = nmi_call_data->func;
- void *info = nmi_call_data->info;
- int wait = nmi_call_data->wait;
-
- /* Notify the initiating CPU that I've grabbed the data and am about to
- * execute the function
- */
- smp_mb();
- cpumask_clear_cpu(smp_processor_id(), &nmi_call_data->started);
- (*func)(info);
-
- if (wait) {
- smp_mb();
- cpumask_clear_cpu(smp_processor_id(),
- &nmi_call_data->finished);
- }
-}
-
-#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \
- defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
-/**
- * smp_ipi_timer_interrupt - Local timer IPI handler
- * @irq: The interrupt number.
- * @dev_id: The device ID.
- *
- * Returns IRQ_HANDLED to indicate we handled the interrupt successfully.
- */
-static irqreturn_t smp_ipi_timer_interrupt(int irq, void *dev_id)
-{
- return local_timer_interrupt();
-}
-#endif
-
-void __init smp_init_cpus(void)
-{
- int i;
- for (i = 0; i < NR_CPUS; i++) {
- set_cpu_possible(i, true);
- set_cpu_present(i, true);
- }
-}
-
-/**
- * smp_cpu_init - Initialise AP in start_secondary.
- *
- * For this Application Processor, set up init_mm, initialise FPU and set
- * interrupt level 0-6 setting.
- */
-static void __init smp_cpu_init(void)
-{
- unsigned long flags;
- int cpu_id = smp_processor_id();
- u16 tmp16;
-
- if (test_and_set_bit(cpu_id, &cpu_initialized)) {
- printk(KERN_WARNING "CPU#%d already initialized!\n", cpu_id);
- for (;;)
- local_irq_enable();
- }
- printk(KERN_INFO "Initializing CPU#%d\n", cpu_id);
-
- mmgrab(&init_mm);
- current->active_mm = &init_mm;
- BUG_ON(current->mm);
-
- enter_lazy_tlb(&init_mm, current);
-
- /* Force FPU initialization */
- clear_using_fpu(current);
-
- GxICR(CALL_FUNC_SINGLE_IPI) = CALL_FUNCTION_GxICR_LV | GxICR_DETECT;
- mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI);
-
- GxICR(LOCAL_TIMER_IPI) = LOCAL_TIMER_GxICR_LV | GxICR_DETECT;
- mn10300_ipi_enable(LOCAL_TIMER_IPI);
-
- GxICR(RESCHEDULE_IPI) = RESCHEDULE_GxICR_LV | GxICR_DETECT;
- mn10300_ipi_enable(RESCHEDULE_IPI);
-
-#ifdef CONFIG_MN10300_CACHE_ENABLED
- GxICR(FLUSH_CACHE_IPI) = FLUSH_CACHE_GxICR_LV | GxICR_DETECT;
- mn10300_ipi_enable(FLUSH_CACHE_IPI);
-#endif
-
- mn10300_ipi_shutdown(SMP_BOOT_IRQ);
-
- /* Set up the non-maskable call function IPI */
- flags = arch_local_cli_save();
- GxICR(CALL_FUNCTION_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT;
- tmp16 = GxICR(CALL_FUNCTION_NMI_IPI);
- arch_local_irq_restore(flags);
-}
-
-/**
- * smp_prepare_cpu_init - Initialise CPU in startup_secondary
- *
- * Set interrupt level 0-6 setting and init ICR of the kernel debugger.
- */
-void smp_prepare_cpu_init(void)
-{
- int loop;
-
- /* Set the interrupt vector registers */
- IVAR0 = EXCEP_IRQ_LEVEL0;
- IVAR1 = EXCEP_IRQ_LEVEL1;
- IVAR2 = EXCEP_IRQ_LEVEL2;
- IVAR3 = EXCEP_IRQ_LEVEL3;
- IVAR4 = EXCEP_IRQ_LEVEL4;
- IVAR5 = EXCEP_IRQ_LEVEL5;
- IVAR6 = EXCEP_IRQ_LEVEL6;
-
- /* Disable all interrupts and set to priority 6 (lowest) */
- for (loop = 0; loop < GxICR_NUM_IRQS; loop++)
- GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
-
-#ifdef CONFIG_KERNEL_DEBUGGER
- /* initialise the kernel debugger interrupt */
- do {
- unsigned long flags;
- u16 tmp16;
-
- flags = arch_local_cli_save();
- GxICR(DEBUGGER_NMI_IPI) = GxICR_NMI | GxICR_ENABLE | GxICR_DETECT;
- tmp16 = GxICR(DEBUGGER_NMI_IPI);
- arch_local_irq_restore(flags);
- } while (0);
-#endif
-}
-
-/**
- * start_secondary - Activate a secondary CPU (AP)
- * @unused: Thread parameter (ignored).
- */
-int __init start_secondary(void *unused)
-{
- smp_cpu_init();
- smp_callin();
- while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask))
- cpu_relax();
-
- local_flush_tlb();
- preempt_disable();
- smp_online();
-
-#ifdef CONFIG_GENERIC_CLOCKEVENTS
- init_clockevents();
-#endif
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
- return 0;
-}
-
-/**
- * smp_prepare_cpus - Boot up secondary CPUs (APs)
- * @max_cpus: Maximum number of CPUs to boot.
- *
- * Call do_boot_cpu, and boot up APs.
- */
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- int phy_id;
-
- /* Setup boot CPU information */
- smp_store_cpu_info(0);
- smp_tune_scheduling();
-
- init_ipi();
-
- /* If SMP should be disabled, then finish */
- if (max_cpus == 0) {
- printk(KERN_INFO "SMP mode deactivated.\n");
- goto smp_done;
- }
-
- /* Boot secondary CPUs (for which phy_id > 0) */
- for (phy_id = 0; phy_id < NR_CPUS; phy_id++) {
- /* Don't boot primary CPU */
- if (max_cpus <= cpucount + 1)
- continue;
- if (phy_id != 0)
- do_boot_cpu(phy_id);
- set_cpu_possible(phy_id, true);
- smp_show_cpu_info(phy_id);
- }
-
-smp_done:
- Dprintk("Boot done.\n");
-}
-
-/**
- * smp_store_cpu_info - Save a CPU's information
- * @cpu: The CPU to save for.
- *
- * Save boot_cpu_data and jiffy for the specified CPU.
- */
-static void __init smp_store_cpu_info(int cpu)
-{
- struct mn10300_cpuinfo *ci = &cpu_data[cpu];
-
- *ci = boot_cpu_data;
- ci->loops_per_jiffy = loops_per_jiffy;
- ci->type = CPUREV;
-}
-
-/**
- * smp_tune_scheduling - Set time slice value
- *
- * Nothing to do here.
- */
-static void __init smp_tune_scheduling(void)
-{
-}
-
-/**
- * do_boot_cpu: Boot up one CPU
- * @phy_id: Physical ID of CPU to boot.
- *
- * Send an IPI to a secondary CPU to boot it. Returns 0 on success, 1
- * otherwise.
- */
-static int __init do_boot_cpu(int phy_id)
-{
- struct task_struct *idle;
- unsigned long send_status, callin_status;
- int timeout, cpu_id;
-
- send_status = GxICR_REQUEST;
- callin_status = 0;
- timeout = 0;
- cpu_id = phy_id;
-
- cpucount++;
-
- /* Create idle thread for this CPU */
- idle = fork_idle(cpu_id);
- if (IS_ERR(idle))
- panic("Failed fork for CPU#%d.", cpu_id);
-
- idle->thread.pc = (unsigned long)start_secondary;
-
- printk(KERN_NOTICE "Booting CPU#%d\n", cpu_id);
- start_stack[cpu_id - 1] = idle->thread.sp;
-
- task_thread_info(idle)->cpu = cpu_id;
-
- /* Send boot IPI to AP */
- send_IPI_mask(cpumask_of(phy_id), SMP_BOOT_IRQ);
-
- Dprintk("Waiting for send to finish...\n");
-
- /* Wait for AP's IPI receive in 100[ms] */
- do {
- udelay(1000);
- send_status =
- CROSS_GxICR(SMP_BOOT_IRQ, phy_id) & GxICR_REQUEST;
- } while (send_status == GxICR_REQUEST && timeout++ < 100);
-
- Dprintk("Waiting for cpu_callin_map.\n");
-
- if (send_status == 0) {
- /* Allow AP to start initializing */
- cpumask_set_cpu(cpu_id, &cpu_callout_map);
-
- /* Wait for setting cpu_callin_map */
- timeout = 0;
- do {
- udelay(1000);
- callin_status = cpumask_test_cpu(cpu_id,
- &cpu_callin_map);
- } while (callin_status == 0 && timeout++ < 5000);
-
- if (callin_status == 0)
- Dprintk("Not responding.\n");
- } else {
- printk(KERN_WARNING "IPI not delivered.\n");
- }
-
- if (send_status == GxICR_REQUEST || callin_status == 0) {
- cpumask_clear_cpu(cpu_id, &cpu_callout_map);
- cpumask_clear_cpu(cpu_id, &cpu_callin_map);
- cpumask_clear_cpu(cpu_id, &cpu_initialized);
- cpucount--;
- return 1;
- }
- return 0;
-}
-
-/**
- * smp_show_cpu_info - Show SMP CPU information
- * @cpu: The CPU of interest.
- */
-static void __init smp_show_cpu_info(int cpu)
-{
- struct mn10300_cpuinfo *ci = &cpu_data[cpu];
-
- printk(KERN_INFO
- "CPU#%d : ioclk speed: %lu.%02luMHz : bogomips : %lu.%02lu\n",
- cpu,
- MN10300_IOCLK / 1000000,
- (MN10300_IOCLK / 10000) % 100,
- ci->loops_per_jiffy / (500000 / HZ),
- (ci->loops_per_jiffy / (5000 / HZ)) % 100);
-}
-
-/**
- * smp_callin - Set cpu_callin_map of the current CPU ID
- */
-static void __init smp_callin(void)
-{
- unsigned long timeout;
- int cpu;
-
- cpu = smp_processor_id();
- timeout = jiffies + (2 * HZ);
-
- if (cpumask_test_cpu(cpu, &cpu_callin_map)) {
- printk(KERN_ERR "CPU#%d already present.\n", cpu);
- BUG();
- }
- Dprintk("CPU#%d waiting for CALLOUT\n", cpu);
-
- /* Wait for AP startup 2s total */
- while (time_before(jiffies, timeout)) {
- if (cpumask_test_cpu(cpu, &cpu_callout_map))
- break;
- cpu_relax();
- }
-
- if (!time_before(jiffies, timeout)) {
- printk(KERN_ERR
- "BUG: CPU#%d started up but did not get a callout!\n",
- cpu);
- BUG();
- }
-
-#ifdef CONFIG_CALIBRATE_DELAY
- calibrate_delay(); /* Get our bogomips */
-#endif
-
- /* Save our processor parameters */
- smp_store_cpu_info(cpu);
-
- /* Allow the boot processor to continue */
- cpumask_set_cpu(cpu, &cpu_callin_map);
-}
-
-/**
- * smp_online - Set cpu_online_mask
- */
-static void __init smp_online(void)
-{
- int cpu;
-
- cpu = smp_processor_id();
-
- notify_cpu_starting(cpu);
-
- set_cpu_online(cpu, true);
-
- local_irq_enable();
-}
-
-/**
- * smp_cpus_done -
- * @max_cpus: Maximum CPU count.
- *
- * Do nothing.
- */
-void __init smp_cpus_done(unsigned int max_cpus)
-{
-}
-
-/*
- * smp_prepare_boot_cpu - Set up stuff for the boot processor.
- *
- * Set up the cpu_online_mask, cpu_callout_map and cpu_callin_map of the boot
- * processor (CPU 0).
- */
-void smp_prepare_boot_cpu(void)
-{
- cpumask_set_cpu(0, &cpu_callout_map);
- cpumask_set_cpu(0, &cpu_callin_map);
- current_thread_info()->cpu = 0;
-}
-
-/*
- * initialize_secondary - Initialise a secondary CPU (Application Processor).
- *
- * Set SP register and jump to thread's PC address.
- */
-void initialize_secondary(void)
-{
- asm volatile (
- "mov %0,sp \n"
- "jmp (%1) \n"
- :
- : "a"(current->thread.sp), "a"(current->thread.pc));
-}
-
-/**
- * __cpu_up - Set smp_commenced_mask for the nominated CPU
- * @cpu: The target CPU.
- */
-int __cpu_up(unsigned int cpu, struct task_struct *tidle)
-{
- int timeout;
-
-#ifdef CONFIG_HOTPLUG_CPU
- if (sleep_mode[cpu])
- run_wakeup_cpu(cpu);
-#endif /* CONFIG_HOTPLUG_CPU */
-
- cpumask_set_cpu(cpu, &smp_commenced_mask);
-
- /* Wait 5s total for a response */
- for (timeout = 0 ; timeout < 5000 ; timeout++) {
- if (cpu_online(cpu))
- break;
- udelay(1000);
- }
-
- BUG_ON(!cpu_online(cpu));
- return 0;
-}
-
-/**
- * setup_profiling_timer - Set up the profiling timer
- * @multiplier - The frequency multiplier to use
- *
- * The frequency of the profiling timer can be changed by writing a multiplier
- * value into /proc/profile.
- */
-int setup_profiling_timer(unsigned int multiplier)
-{
- return -EINVAL;
-}
-
-/*
- * CPU hotplug routines
- */
-#ifdef CONFIG_HOTPLUG_CPU
-
-static DEFINE_PER_CPU(struct cpu, cpu_devices);
-
-static int __init topology_init(void)
-{
- int cpu, ret;
-
- for_each_cpu(cpu) {
- ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL);
- if (ret)
- printk(KERN_WARNING
- "topology_init: register_cpu %d failed (%d)\n",
- cpu, ret);
- }
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-int __cpu_disable(void)
-{
- int cpu = smp_processor_id();
- if (cpu == 0)
- return -EBUSY;
-
- migrate_irqs();
- cpumask_clear_cpu(cpu, &mm_cpumask(current->active_mm));
- return 0;
-}
-
-void __cpu_die(unsigned int cpu)
-{
- run_sleep_cpu(cpu);
-}
-
-#ifdef CONFIG_MN10300_CACHE_ENABLED
-static inline void hotplug_cpu_disable_cache(void)
-{
- int tmp;
- asm volatile(
- " movhu (%1),%0 \n"
- " and %2,%0 \n"
- " movhu %0,(%1) \n"
- "1: movhu (%1),%0 \n"
- " btst %3,%0 \n"
- " bne 1b \n"
- : "=&r"(tmp)
- : "a"(&CHCTR),
- "i"(~(CHCTR_ICEN | CHCTR_DCEN)),
- "i"(CHCTR_ICBUSY | CHCTR_DCBUSY)
- : "memory", "cc");
-}
-
-static inline void hotplug_cpu_enable_cache(void)
-{
- int tmp;
- asm volatile(
- "movhu (%1),%0 \n"
- "or %2,%0 \n"
- "movhu %0,(%1) \n"
- : "=&r"(tmp)
- : "a"(&CHCTR),
- "i"(CHCTR_ICEN | CHCTR_DCEN)
- : "memory", "cc");
-}
-
-static inline void hotplug_cpu_invalidate_cache(void)
-{
- int tmp;
- asm volatile (
- "movhu (%1),%0 \n"
- "or %2,%0 \n"
- "movhu %0,(%1) \n"
- : "=&r"(tmp)
- : "a"(&CHCTR),
- "i"(CHCTR_ICINV | CHCTR_DCINV)
- : "cc");
-}
-
-#else /* CONFIG_MN10300_CACHE_ENABLED */
-#define hotplug_cpu_disable_cache() do {} while (0)
-#define hotplug_cpu_enable_cache() do {} while (0)
-#define hotplug_cpu_invalidate_cache() do {} while (0)
-#endif /* CONFIG_MN10300_CACHE_ENABLED */
-
-/**
- * hotplug_cpu_nmi_call_function - Call a function on other CPUs for hotplug
- * @cpumask: List of target CPUs.
- * @func: The function to call on those CPUs.
- * @info: The context data for the function to be called.
- * @wait: Whether to wait for the calls to complete.
- *
- * Non-maskably call a function on another CPU for hotplug purposes.
- *
- * This function must be called with maskable interrupts disabled.
- */
-static int hotplug_cpu_nmi_call_function(cpumask_t cpumask,
- smp_call_func_t func, void *info,
- int wait)
-{
- /*
- * The address and the size of nmi_call_func_mask_data
- * need to be aligned on L1_CACHE_BYTES.
- */
- static struct nmi_call_data_struct nmi_call_func_mask_data
- __cacheline_aligned;
- unsigned long start, end;
-
- start = (unsigned long)&nmi_call_func_mask_data;
- end = start + sizeof(struct nmi_call_data_struct);
-
- nmi_call_func_mask_data.func = func;
- nmi_call_func_mask_data.info = info;
- nmi_call_func_mask_data.started = cpumask;
- nmi_call_func_mask_data.wait = wait;
- if (wait)
- nmi_call_func_mask_data.finished = cpumask;
-
- spin_lock(&smp_nmi_call_lock);
- nmi_call_data = &nmi_call_func_mask_data;
- mn10300_local_dcache_flush_range(start, end);
- smp_wmb();
-
- send_IPI_mask(cpumask, CALL_FUNCTION_NMI_IPI);
-
- do {
- mn10300_local_dcache_inv_range(start, end);
- barrier();
- } while (!cpumask_empty(&nmi_call_func_mask_data.started));
-
- if (wait) {
- do {
- mn10300_local_dcache_inv_range(start, end);
- barrier();
- } while (!cpumask_empty(&nmi_call_func_mask_data.finished));
- }
-
- spin_unlock(&smp_nmi_call_lock);
- return 0;
-}
-
-static void restart_wakeup_cpu(void)
-{
- unsigned int cpu = smp_processor_id();
-
- cpumask_set_cpu(cpu, &cpu_callin_map);
- local_flush_tlb();
- set_cpu_online(cpu, true);
- smp_wmb();
-}
-
-static void prepare_sleep_cpu(void *unused)
-{
- sleep_mode[smp_processor_id()] = 1;
- smp_mb();
- mn10300_local_dcache_flush_inv();
- hotplug_cpu_disable_cache();
- hotplug_cpu_invalidate_cache();
-}
-
-/* when this function called, IE=0, NMID=0. */
-static void sleep_cpu(void *unused)
-{
- unsigned int cpu_id = smp_processor_id();
- /*
- * CALL_FUNCTION_NMI_IPI for wakeup_cpu() shall not be requested,
- * before this cpu goes in SLEEP mode.
- */
- do {
- smp_mb();
- __sleep_cpu();
- } while (sleep_mode[cpu_id]);
- restart_wakeup_cpu();
-}
-
-static void run_sleep_cpu(unsigned int cpu)
-{
- unsigned long flags;
- cpumask_t cpumask;
-
- cpumask_copy(&cpumask, &cpumask_of(cpu));
- flags = arch_local_cli_save();
- hotplug_cpu_nmi_call_function(cpumask, prepare_sleep_cpu, NULL, 1);
- hotplug_cpu_nmi_call_function(cpumask, sleep_cpu, NULL, 0);
- udelay(1); /* delay for the cpu to sleep. */
- arch_local_irq_restore(flags);
-}
-
-static void wakeup_cpu(void)
-{
- hotplug_cpu_invalidate_cache();
- hotplug_cpu_enable_cache();
- smp_mb();
- sleep_mode[smp_processor_id()] = 0;
-}
-
-static void run_wakeup_cpu(unsigned int cpu)
-{
- unsigned long flags;
-
- flags = arch_local_cli_save();
-#if NR_CPUS == 2
- mn10300_local_dcache_flush_inv();
-#else
- /*
- * Before waking up the cpu,
- * all online cpus should stop and flush D-Cache for global data.
- */
-#error not support NR_CPUS > 2, when CONFIG_HOTPLUG_CPU=y.
-#endif
- hotplug_cpu_nmi_call_function(cpumask_of(cpu), wakeup_cpu, NULL, 1);
- arch_local_irq_restore(flags);
-}
-
-#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mn10300/kernel/switch_to.S b/arch/mn10300/kernel/switch_to.S
deleted file mode 100644
index de3e74fc9ea0..000000000000
--- a/arch/mn10300/kernel/switch_to.S
+++ /dev/null
@@ -1,179 +0,0 @@
-###############################################################################
-#
-# MN10300 Context switch operation
-#
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Written by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/thread_info.h>
-#include <asm/cpu-regs.h>
-#ifdef CONFIG_SMP
-#include <proc/smp-regs.h>
-#endif /* CONFIG_SMP */
-
- .text
-
-###############################################################################
-#
-# struct task_struct *__switch_to(struct thread_struct *prev,
-# struct thread_struct *next,
-# struct task_struct *prev_task)
-#
-###############################################################################
-ENTRY(__switch_to)
- movm [d2,d3,a2,a3,exreg1],(sp)
- or EPSW_NMID,epsw
-
- mov (44,sp),d2
-
- mov d0,a0
- mov d1,a1
-
- # save prev context
- mov __switch_back,d0
- mov sp,a2
- mov a2,(THREAD_SP,a0)
- mov a3,(THREAD_A3,a0)
-
-#ifdef CONFIG_KGDB
- btst 0xff,(kgdb_single_step)
- bne __switch_to__lift_sstep_bp
-__switch_to__continue:
-#endif
- mov d0,(THREAD_PC,a0)
-
- mov (THREAD_A3,a1),a3
- mov (THREAD_SP,a1),a2
-
- # switch
- mov a2,sp
-
- # load next context
- GET_THREAD_INFO a2
- mov a2,(__current_ti)
- mov (TI_task,a2),a2
- mov a2,(__current)
-#ifdef CONFIG_MN10300_CURRENT_IN_E2
- mov a2,e2
-#endif
-
- mov (THREAD_PC,a1),a2
- mov d2,d0 # for ret_from_fork
- mov d0,a0 # for __switch_to
-
- jmp (a2)
-
-__switch_back:
- and ~EPSW_NMID,epsw
- ret [d2,d3,a2,a3,exreg1],32
-
-#ifdef CONFIG_KGDB
-###############################################################################
-#
-# Lift the single-step breakpoints when the task being traced is switched out
-# A0 = prev
-# A1 = next
-#
-###############################################################################
-__switch_to__lift_sstep_bp:
- add -12,sp
- mov a0,e4
- mov a1,e5
-
- # Clear the single-step flag to prevent us coming this way until we get
- # switched back in
- bclr 0xff,(kgdb_single_step)
-
- # Remove first breakpoint
- mov (kgdb_sstep_bp_addr),a2
- cmp 0,a2
- beq 1f
- movbu (kgdb_sstep_bp),d0
- movbu d0,(a2)
-#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE)
- mov a2,d0
- mov a2,d1
- add 1,d1
- calls flush_icache_range
-#endif
-1:
-
- # Remove second breakpoint
- mov (kgdb_sstep_bp_addr+4),a2
- cmp 0,a2
- beq 2f
- movbu (kgdb_sstep_bp+1),d0
- movbu d0,(a2)
-#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE)
- mov a2,d0
- mov a2,d1
- add 1,d1
- calls flush_icache_range
-#endif
-2:
-
- # Change the resumption address and return
- mov __switch_back__reinstall_sstep_bp,d0
- mov e4,a0
- mov e5,a1
- add 12,sp
- bra __switch_to__continue
-
-###############################################################################
-#
-# Reinstall the single-step breakpoints when the task being traced is switched
-# back in (A1 points to the new thread_struct).
-#
-###############################################################################
-__switch_back__reinstall_sstep_bp:
- add -12,sp
- mov a0,e4 # save the return value
- mov 0xff,d3
-
- # Reinstall first breakpoint
- mov (kgdb_sstep_bp_addr),a2
- cmp 0,a2
- beq 1f
- movbu (a2),d0
- movbu d0,(kgdb_sstep_bp)
- movbu d3,(a2)
-#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE)
- mov a2,d0
- mov a2,d1
- add 1,d1
- calls flush_icache_range
-#endif
-1:
-
- # Reinstall second breakpoint
- mov (kgdb_sstep_bp_addr+4),a2
- cmp 0,a2
- beq 2f
- movbu (a2),d0
- movbu d0,(kgdb_sstep_bp+1)
- movbu d3,(a2)
-#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE) || defined(CONFIG_MN10300_CACHE_INV_ICACHE)
- mov a2,d0
- mov a2,d1
- add 1,d1
- calls flush_icache_range
-#endif
-2:
-
- mov d3,(kgdb_single_step)
-
- # Restore the return value (the previous thread_struct pointer)
- mov e4,a0
- mov a0,d0
- add 12,sp
- bra __switch_back
-
-#endif /* CONFIG_KGDB */
diff --git a/arch/mn10300/kernel/sys_mn10300.c b/arch/mn10300/kernel/sys_mn10300.c
deleted file mode 100644
index f999981e55c0..000000000000
--- a/arch/mn10300/kernel/sys_mn10300.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* MN10300 Weird system calls
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/syscalls.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/tty.h>
-
-#include <linux/uaccess.h>
-
-asmlinkage long old_mmap(unsigned long addr, unsigned long len,
- unsigned long prot, unsigned long flags,
- unsigned long fd, unsigned long offset)
-{
- if (offset & ~PAGE_MASK)
- return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
-}
diff --git a/arch/mn10300/kernel/time.c b/arch/mn10300/kernel/time.c
deleted file mode 100644
index 06b83b17c5f1..000000000000
--- a/arch/mn10300/kernel/time.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* MN10300 Low level time management
- *
- * Copyright (C) 2007-2008 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/i386/kernel/time.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/sched/clock.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/profile.h>
-#include <linux/cnt32_to_63.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <asm/irq.h>
-#include <asm/div64.h>
-#include <asm/processor.h>
-#include <asm/intctl-regs.h>
-#include <asm/rtc.h>
-#include "internal.h"
-
-static unsigned long mn10300_last_tsc; /* time-stamp counter at last time
- * interrupt occurred */
-
-static unsigned long sched_clock_multiplier;
-
-/*
- * scheduler clock - returns current time in nanosec units.
- */
-unsigned long long sched_clock(void)
-{
- union {
- unsigned long long ll;
- unsigned l[2];
- } tsc64, result;
- unsigned long tmp;
- unsigned product[3]; /* 96-bit intermediate value */
-
- /* cnt32_to_63() is not safe with preemption */
- preempt_disable();
-
- /* expand the tsc to 64-bits.
- * - sched_clock() must be called once a minute or better or the
- * following will go horribly wrong - see cnt32_to_63()
- */
- tsc64.ll = cnt32_to_63(get_cycles()) & 0x7fffffffffffffffULL;
-
- preempt_enable();
-
- /* scale the 64-bit TSC value to a nanosecond value via a 96-bit
- * intermediate
- */
- asm("mulu %2,%0,%3,%0 \n" /* LSW * mult -> 0:%3:%0 */
- "mulu %2,%1,%2,%1 \n" /* MSW * mult -> %2:%1:0 */
- "add %3,%1 \n"
- "addc 0,%2 \n" /* result in %2:%1:%0 */
- : "=r"(product[0]), "=r"(product[1]), "=r"(product[2]), "=r"(tmp)
- : "0"(tsc64.l[0]), "1"(tsc64.l[1]), "2"(sched_clock_multiplier)
- : "cc");
-
- result.l[0] = product[1] << 16 | product[0] >> 16;
- result.l[1] = product[2] << 16 | product[1] >> 16;
-
- return result.ll;
-}
-
-/*
- * initialise the scheduler clock
- */
-static void __init mn10300_sched_clock_init(void)
-{
- sched_clock_multiplier =
- __muldiv64u(NSEC_PER_SEC, 1 << 16, MN10300_TSCCLK);
-}
-
-/**
- * local_timer_interrupt - Local timer interrupt handler
- *
- * Handle local timer interrupts for this CPU. They may have been propagated
- * to this CPU from the CPU that actually gets them by way of an IPI.
- */
-irqreturn_t local_timer_interrupt(void)
-{
- profile_tick(CPU_PROFILING);
- update_process_times(user_mode(get_irq_regs()));
- return IRQ_HANDLED;
-}
-
-/*
- * initialise the various timers used by the main part of the kernel
- */
-void __init time_init(void)
-{
- /* we need the prescalar running to be able to use IOCLK/8
- * - IOCLK runs at 1/4 (ST5 open) or 1/8 (ST5 closed) internal CPU clock
- * - IOCLK runs at Fosc rate (crystal speed)
- */
- TMPSCNT |= TMPSCNT_ENABLE;
-
- init_clocksource();
-
- printk(KERN_INFO
- "timestamp counter I/O clock running at %lu.%02lu"
- " (calibrated against RTC)\n",
- MN10300_TSCCLK / 1000000, (MN10300_TSCCLK / 10000) % 100);
-
- mn10300_last_tsc = read_timestamp_counter();
-
- init_clockevents();
-
-#ifdef CONFIG_MN10300_WD_TIMER
- /* start the watchdog timer */
- watchdog_go();
-#endif
-
- mn10300_sched_clock_init();
-}
diff --git a/arch/mn10300/kernel/traps.c b/arch/mn10300/kernel/traps.c
deleted file mode 100644
index 72d1015b2ae7..000000000000
--- a/arch/mn10300/kernel/traps.c
+++ /dev/null
@@ -1,615 +0,0 @@
-/* MN10300 Exception handling
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/kdebug.h>
-#include <linux/bug.h>
-#include <linux/irq.h>
-#include <linux/export.h>
-#include <asm/processor.h>
-#include <linux/uaccess.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-#include <asm/smp.h>
-#include <asm/pgalloc.h>
-#include <asm/cacheflush.h>
-#include <asm/cpu-regs.h>
-#include <asm/busctl-regs.h>
-#include <unit/leds.h>
-#include <asm/fpu.h>
-#include <asm/sections.h>
-#include <asm/debugger.h>
-#include "internal.h"
-
-#if (CONFIG_INTERRUPT_VECTOR_BASE & 0xffffff)
-#error "INTERRUPT_VECTOR_BASE not aligned to 16MiB boundary!"
-#endif
-
-int kstack_depth_to_print = 24;
-
-spinlock_t die_lock = __SPIN_LOCK_UNLOCKED(die_lock);
-
-struct exception_to_signal_map {
- u8 signo;
- u32 si_code;
-};
-
-static const struct exception_to_signal_map exception_to_signal_map[256] = {
- /* MMU exceptions */
- [EXCEP_ITLBMISS >> 3] = { 0, 0 },
- [EXCEP_DTLBMISS >> 3] = { 0, 0 },
- [EXCEP_IAERROR >> 3] = { 0, 0 },
- [EXCEP_DAERROR >> 3] = { 0, 0 },
-
- /* system exceptions */
- [EXCEP_TRAP >> 3] = { SIGTRAP, TRAP_BRKPT },
- [EXCEP_ISTEP >> 3] = { SIGTRAP, TRAP_TRACE }, /* Monitor */
- [EXCEP_IBREAK >> 3] = { SIGTRAP, TRAP_HWBKPT }, /* Monitor */
- [EXCEP_OBREAK >> 3] = { SIGTRAP, TRAP_HWBKPT }, /* Monitor */
- [EXCEP_PRIVINS >> 3] = { SIGILL, ILL_PRVOPC },
- [EXCEP_UNIMPINS >> 3] = { SIGILL, ILL_ILLOPC },
- [EXCEP_UNIMPEXINS >> 3] = { SIGILL, ILL_ILLOPC },
- [EXCEP_MEMERR >> 3] = { SIGSEGV, SEGV_ACCERR },
- [EXCEP_MISALIGN >> 3] = { SIGBUS, BUS_ADRALN },
- [EXCEP_BUSERROR >> 3] = { SIGBUS, BUS_ADRERR },
- [EXCEP_ILLINSACC >> 3] = { SIGSEGV, SEGV_ACCERR },
- [EXCEP_ILLDATACC >> 3] = { SIGSEGV, SEGV_ACCERR },
- [EXCEP_IOINSACC >> 3] = { SIGSEGV, SEGV_ACCERR },
- [EXCEP_PRIVINSACC >> 3] = { SIGSEGV, SEGV_ACCERR }, /* userspace */
- [EXCEP_PRIVDATACC >> 3] = { SIGSEGV, SEGV_ACCERR }, /* userspace */
- [EXCEP_DATINSACC >> 3] = { SIGSEGV, SEGV_ACCERR },
- [EXCEP_DOUBLE_FAULT >> 3] = { SIGILL, ILL_BADSTK },
-
- /* FPU exceptions */
- [EXCEP_FPU_DISABLED >> 3] = { SIGILL, ILL_COPROC },
- [EXCEP_FPU_UNIMPINS >> 3] = { SIGILL, ILL_COPROC },
- [EXCEP_FPU_OPERATION >> 3] = { SIGFPE, FPE_INTDIV },
-
- /* interrupts */
- [EXCEP_WDT >> 3] = { SIGALRM, 0 },
- [EXCEP_NMI >> 3] = { SIGQUIT, 0 },
- [EXCEP_IRQ_LEVEL0 >> 3] = { SIGINT, 0 },
- [EXCEP_IRQ_LEVEL1 >> 3] = { 0, 0 },
- [EXCEP_IRQ_LEVEL2 >> 3] = { 0, 0 },
- [EXCEP_IRQ_LEVEL3 >> 3] = { 0, 0 },
- [EXCEP_IRQ_LEVEL4 >> 3] = { 0, 0 },
- [EXCEP_IRQ_LEVEL5 >> 3] = { 0, 0 },
- [EXCEP_IRQ_LEVEL6 >> 3] = { 0, 0 },
-
- /* system calls */
- [EXCEP_SYSCALL0 >> 3] = { 0, 0 },
- [EXCEP_SYSCALL1 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL2 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL3 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL4 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL5 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL6 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL7 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL8 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL9 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL10 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL11 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL12 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL13 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL14 >> 3] = { SIGILL, ILL_ILLTRP },
- [EXCEP_SYSCALL15 >> 3] = { SIGABRT, 0 },
-};
-
-/*
- * Handle kernel exceptions.
- *
- * See if there's a fixup handler we can force a jump to when an exception
- * happens due to something kernel code did
- */
-int die_if_no_fixup(const char *str, struct pt_regs *regs,
- enum exception_code code)
-{
- u8 opcode;
- int signo, si_code;
-
- if (user_mode(regs))
- return 0;
-
- peripheral_leds_display_exception(code);
-
- signo = exception_to_signal_map[code >> 3].signo;
- si_code = exception_to_signal_map[code >> 3].si_code;
-
- switch (code) {
- /* see if we can fixup the kernel accessing memory */
- case EXCEP_ITLBMISS:
- case EXCEP_DTLBMISS:
- case EXCEP_IAERROR:
- case EXCEP_DAERROR:
- case EXCEP_MEMERR:
- case EXCEP_MISALIGN:
- case EXCEP_BUSERROR:
- case EXCEP_ILLDATACC:
- case EXCEP_IOINSACC:
- case EXCEP_PRIVINSACC:
- case EXCEP_PRIVDATACC:
- case EXCEP_DATINSACC:
- if (fixup_exception(regs))
- return 1;
- break;
-
- case EXCEP_TRAP:
- case EXCEP_UNIMPINS:
- if (probe_kernel_read(&opcode, (u8 *)regs->pc, 1) < 0)
- break;
- if (opcode == 0xff) {
- if (notify_die(DIE_BREAKPOINT, str, regs, code, 0, 0))
- return 1;
- if (at_debugger_breakpoint(regs))
- regs->pc++;
- signo = SIGTRAP;
- si_code = TRAP_BRKPT;
- }
- break;
-
- case EXCEP_SYSCALL1 ... EXCEP_SYSCALL14:
- /* syscall return addr is _after_ the instruction */
- regs->pc -= 2;
- break;
-
- case EXCEP_SYSCALL15:
- if (report_bug(regs->pc, regs) == BUG_TRAP_TYPE_WARN)
- return 1;
-
- /* syscall return addr is _after_ the instruction */
- regs->pc -= 2;
- break;
-
- default:
- break;
- }
-
- if (debugger_intercept(code, signo, si_code, regs) == 0)
- return 1;
-
- if (notify_die(DIE_GPF, str, regs, code, 0, 0))
- return 1;
-
- /* make the process die as the last resort */
- die(str, regs, code);
-}
-
-/*
- * General exception handler
- */
-asmlinkage void handle_exception(struct pt_regs *regs, u32 intcode)
-{
- siginfo_t info;
-
- /* deal with kernel exceptions here */
- if (die_if_no_fixup(NULL, regs, intcode))
- return;
-
- /* otherwise it's a userspace exception */
- info.si_signo = exception_to_signal_map[intcode >> 3].signo;
- info.si_code = exception_to_signal_map[intcode >> 3].si_code;
- info.si_errno = 0;
- info.si_addr = (void *) regs->pc;
- force_sig_info(info.si_signo, &info, current);
-}
-
-/*
- * handle NMI
- */
-asmlinkage void nmi(struct pt_regs *regs, enum exception_code code)
-{
- /* see if gdbstub wants to deal with it */
- if (debugger_intercept(code, SIGQUIT, 0, regs))
- return;
-
- printk(KERN_WARNING "--- Register Dump ---\n");
- show_registers(regs);
- printk(KERN_WARNING "---------------------\n");
-}
-
-/*
- * show a stack trace from the specified stack pointer
- */
-void show_trace(unsigned long *sp)
-{
- unsigned long bottom, stack, addr, fp, raslot;
-
- printk(KERN_EMERG "\nCall Trace:\n");
-
- //stack = (unsigned long)sp;
- asm("mov sp,%0" : "=a"(stack));
- asm("mov a3,%0" : "=r"(fp));
-
- raslot = ULONG_MAX;
- bottom = (stack + THREAD_SIZE) & ~(THREAD_SIZE - 1);
- for (; stack < bottom; stack += sizeof(addr)) {
- addr = *(unsigned long *)stack;
- if (stack == fp) {
- if (addr > stack && addr < bottom) {
- fp = addr;
- raslot = stack + sizeof(addr);
- continue;
- }
- fp = 0;
- raslot = ULONG_MAX;
- }
-
- if (__kernel_text_address(addr)) {
- printk(" [<%08lx>]", addr);
- if (stack >= raslot)
- raslot = ULONG_MAX;
- else
- printk(" ?");
- printk(" %pS\n", (void *)addr);
- }
- }
-
- printk("\n");
-}
-
-/*
- * show the raw stack from the specified stack pointer
- */
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
- unsigned long *stack;
- int i;
-
- if (!sp)
- sp = (unsigned long *) &sp;
-
- stack = sp;
- printk(KERN_EMERG "Stack:");
- for (i = 0; i < kstack_depth_to_print; i++) {
- if (((long) stack & (THREAD_SIZE - 1)) == 0)
- break;
- if ((i % 8) == 0)
- printk(KERN_EMERG " ");
- printk("%08lx ", *stack++);
- }
-
- show_trace(sp);
-}
-
-/*
- * dump the register file in the specified exception frame
- */
-void show_registers_only(struct pt_regs *regs)
-{
- unsigned long ssp;
-
- ssp = (unsigned long) regs + sizeof(*regs);
-
- printk(KERN_EMERG "PC: %08lx EPSW: %08lx SSP: %08lx mode: %s\n",
- regs->pc, regs->epsw, ssp, user_mode(regs) ? "User" : "Super");
- printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
- regs->d0, regs->d1, regs->d2, regs->d3);
- printk(KERN_EMERG "a0: %08lx a1: %08lx a2: %08lx a3: %08lx\n",
- regs->a0, regs->a1, regs->a2, regs->a3);
- printk(KERN_EMERG "e0: %08lx e1: %08lx e2: %08lx e3: %08lx\n",
- regs->e0, regs->e1, regs->e2, regs->e3);
- printk(KERN_EMERG "e4: %08lx e5: %08lx e6: %08lx e7: %08lx\n",
- regs->e4, regs->e5, regs->e6, regs->e7);
- printk(KERN_EMERG "lar: %08lx lir: %08lx mdr: %08lx usp: %08lx\n",
- regs->lar, regs->lir, regs->mdr, regs->sp);
- printk(KERN_EMERG "cvf: %08lx crl: %08lx crh: %08lx drq: %08lx\n",
- regs->mcvf, regs->mcrl, regs->mcrh, regs->mdrq);
- printk(KERN_EMERG "threadinfo=%p task=%p)\n",
- current_thread_info(), current);
-
- if ((unsigned long) current >= PAGE_OFFSET &&
- (unsigned long) current < (unsigned long)high_memory)
- printk(KERN_EMERG "Process %s (pid: %d)\n",
- current->comm, current->pid);
-
-#ifdef CONFIG_SMP
- printk(KERN_EMERG "CPUID: %08x\n", CPUID);
-#endif
- printk(KERN_EMERG "CPUP: %04hx\n", CPUP);
- printk(KERN_EMERG "TBR: %08x\n", TBR);
- printk(KERN_EMERG "DEAR: %08x\n", DEAR);
- printk(KERN_EMERG "sISR: %08x\n", sISR);
- printk(KERN_EMERG "NMICR: %04hx\n", NMICR);
- printk(KERN_EMERG "BCBERR: %08x\n", BCBERR);
- printk(KERN_EMERG "BCBEAR: %08x\n", BCBEAR);
- printk(KERN_EMERG "MMUFCR: %08x\n", MMUFCR);
- printk(KERN_EMERG "IPTEU : %08x IPTEL2: %08x\n", IPTEU, IPTEL2);
- printk(KERN_EMERG "DPTEU: %08x DPTEL2: %08x\n", DPTEU, DPTEL2);
-}
-
-/*
- * dump the registers and the stack
- */
-void show_registers(struct pt_regs *regs)
-{
- unsigned long sp;
- int i;
-
- show_registers_only(regs);
-
- if (!user_mode(regs))
- sp = (unsigned long) regs + sizeof(*regs);
- else
- sp = regs->sp;
-
- /* when in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (!user_mode(regs)) {
- printk(KERN_EMERG "\n");
- show_stack(current, (unsigned long *) sp);
-
-#if 0
- printk(KERN_EMERG "\nCode: ");
- if (regs->pc < PAGE_OFFSET)
- goto bad;
-
- for (i = 0; i < 20; i++) {
- unsigned char c;
- if (__get_user(c, &((unsigned char *) regs->pc)[i]))
- goto bad;
- printk("%02x ", c);
- }
-#else
- i = 0;
-#endif
- }
-
- printk("\n");
- return;
-
-#if 0
-bad:
- printk(KERN_EMERG " Bad PC value.");
- break;
-#endif
-}
-
-/*
- *
- */
-void show_trace_task(struct task_struct *tsk)
-{
- unsigned long sp = tsk->thread.sp;
-
- /* User space on another CPU? */
- if ((sp ^ (unsigned long) tsk) & (PAGE_MASK << 1))
- return;
-
- show_trace((unsigned long *) sp);
-}
-
-/*
- * note the untimely death of part of the kernel
- */
-void die(const char *str, struct pt_regs *regs, enum exception_code code)
-{
- console_verbose();
- spin_lock_irq(&die_lock);
- printk(KERN_EMERG "\n%s: %04x\n",
- str, code & 0xffff);
- show_registers(regs);
-
- if (regs->pc >= 0x02000000 && regs->pc < 0x04000000 &&
- (regs->epsw & (EPSW_IM | EPSW_IE)) != (EPSW_IM | EPSW_IE)) {
- printk(KERN_EMERG "Exception in usermode interrupt handler\n");
- printk(KERN_EMERG "\nPlease connect to kernel debugger !!\n");
- asm volatile ("0: bra 0b");
- }
-
- spin_unlock_irq(&die_lock);
- do_exit(SIGSEGV);
-}
-
-/*
- * display the register file when the stack pointer gets clobbered
- */
-asmlinkage void do_double_fault(struct pt_regs *regs)
-{
- struct task_struct *tsk = current;
-
- strcpy(tsk->comm, "emergency tsk");
- tsk->pid = 0;
- console_verbose();
- printk(KERN_EMERG "--- double fault ---\n");
- show_registers(regs);
-}
-
-/*
- * asynchronous bus error (external, usually I/O DMA)
- */
-asmlinkage void io_bus_error(u32 bcberr, u32 bcbear, struct pt_regs *regs)
-{
- console_verbose();
-
- printk(KERN_EMERG "Asynchronous I/O Bus Error\n");
- printk(KERN_EMERG "==========================\n");
-
- if (bcberr & BCBERR_BEME)
- printk(KERN_EMERG "- Multiple recorded errors\n");
-
- printk(KERN_EMERG "- Faulting Buses:%s%s%s\n",
- bcberr & BCBERR_BEMR_CI ? " CPU-Ins-Fetch" : "",
- bcberr & BCBERR_BEMR_CD ? " CPU-Data" : "",
- bcberr & BCBERR_BEMR_DMA ? " DMA" : "");
-
- printk(KERN_EMERG "- %s %s access made to %s at address %08x\n",
- bcberr & BCBERR_BEBST ? "Burst" : "Single",
- bcberr & BCBERR_BERW ? "Read" : "Write",
- bcberr & BCBERR_BESB_MON ? "Monitor Space" :
- bcberr & BCBERR_BESB_IO ? "Internal CPU I/O Space" :
- bcberr & BCBERR_BESB_EX ? "External I/O Bus" :
- bcberr & BCBERR_BESB_OPEX ? "External Memory Bus" :
- "On Chip Memory",
- bcbear
- );
-
- printk(KERN_EMERG "- Detected by the %s\n",
- bcberr&BCBERR_BESD ? "Bus Control Unit" : "Slave Bus");
-
-#ifdef CONFIG_PCI
-#define BRIDGEREGB(X) (*(volatile __u8 *)(0xBE040000 + (X)))
-#define BRIDGEREGW(X) (*(volatile __u16 *)(0xBE040000 + (X)))
-#define BRIDGEREGL(X) (*(volatile __u32 *)(0xBE040000 + (X)))
-
- printk(KERN_EMERG "- PCI Memory Paging Reg: %08x\n",
- *(volatile __u32 *) (0xBFFFFFF4));
- printk(KERN_EMERG "- PCI Bridge Base Address 0: %08x\n",
- BRIDGEREGL(PCI_BASE_ADDRESS_0));
- printk(KERN_EMERG "- PCI Bridge AMPCI Base Address: %08x\n",
- BRIDGEREGL(0x48));
- printk(KERN_EMERG "- PCI Bridge Command: %04hx\n",
- BRIDGEREGW(PCI_COMMAND));
- printk(KERN_EMERG "- PCI Bridge Status: %04hx\n",
- BRIDGEREGW(PCI_STATUS));
- printk(KERN_EMERG "- PCI Bridge Int Status: %08hx\n",
- BRIDGEREGL(0x4c));
-#endif
-
- printk(KERN_EMERG "\n");
- show_registers(regs);
-
- panic("Halted due to asynchronous I/O Bus Error\n");
-}
-
-/*
- * handle an exception for which a handler has not yet been installed
- */
-asmlinkage void uninitialised_exception(struct pt_regs *regs,
- enum exception_code code)
-{
-
- /* see if gdbstub wants to deal with it */
- if (debugger_intercept(code, SIGSYS, 0, regs) == 0)
- return;
-
- peripheral_leds_display_exception(code);
- printk(KERN_EMERG "Uninitialised Exception 0x%04x\n", code & 0xFFFF);
- show_registers(regs);
-
- for (;;)
- continue;
-}
-
-/*
- * set an interrupt stub to jump to a handler
- * ! NOTE: this does *not* flush the caches
- */
-void __init __set_intr_stub(enum exception_code code, void *handler)
-{
- unsigned long addr;
- u8 *vector = (u8 *)(CONFIG_INTERRUPT_VECTOR_BASE + code);
-
- addr = (unsigned long) handler - (unsigned long) vector;
- vector[0] = 0xdc; /* JMP handler */
- vector[1] = addr;
- vector[2] = addr >> 8;
- vector[3] = addr >> 16;
- vector[4] = addr >> 24;
- vector[5] = 0xcb;
- vector[6] = 0xcb;
- vector[7] = 0xcb;
-}
-
-/*
- * set an interrupt stub to jump to a handler
- */
-void __init set_intr_stub(enum exception_code code, void *handler)
-{
- unsigned long addr;
- u8 *vector = (u8 *)(CONFIG_INTERRUPT_VECTOR_BASE + code);
- unsigned long flags;
-
- addr = (unsigned long) handler - (unsigned long) vector;
-
- flags = arch_local_cli_save();
-
- vector[0] = 0xdc; /* JMP handler */
- vector[1] = addr;
- vector[2] = addr >> 8;
- vector[3] = addr >> 16;
- vector[4] = addr >> 24;
- vector[5] = 0xcb;
- vector[6] = 0xcb;
- vector[7] = 0xcb;
-
- arch_local_irq_restore(flags);
-
-#ifndef CONFIG_MN10300_CACHE_SNOOP
- mn10300_dcache_flush_inv();
- mn10300_icache_inv();
-#endif
-}
-
-/*
- * initialise the exception table
- */
-void __init trap_init(void)
-{
- set_excp_vector(EXCEP_TRAP, handle_exception);
- set_excp_vector(EXCEP_ISTEP, handle_exception);
- set_excp_vector(EXCEP_IBREAK, handle_exception);
- set_excp_vector(EXCEP_OBREAK, handle_exception);
-
- set_excp_vector(EXCEP_PRIVINS, handle_exception);
- set_excp_vector(EXCEP_UNIMPINS, handle_exception);
- set_excp_vector(EXCEP_UNIMPEXINS, handle_exception);
- set_excp_vector(EXCEP_MEMERR, handle_exception);
- set_excp_vector(EXCEP_MISALIGN, misalignment);
- set_excp_vector(EXCEP_BUSERROR, handle_exception);
- set_excp_vector(EXCEP_ILLINSACC, handle_exception);
- set_excp_vector(EXCEP_ILLDATACC, handle_exception);
- set_excp_vector(EXCEP_IOINSACC, handle_exception);
- set_excp_vector(EXCEP_PRIVINSACC, handle_exception);
- set_excp_vector(EXCEP_PRIVDATACC, handle_exception);
- set_excp_vector(EXCEP_DATINSACC, handle_exception);
- set_excp_vector(EXCEP_FPU_UNIMPINS, handle_exception);
- set_excp_vector(EXCEP_FPU_OPERATION, fpu_exception);
-
- set_excp_vector(EXCEP_NMI, nmi);
-
- set_excp_vector(EXCEP_SYSCALL1, handle_exception);
- set_excp_vector(EXCEP_SYSCALL2, handle_exception);
- set_excp_vector(EXCEP_SYSCALL3, handle_exception);
- set_excp_vector(EXCEP_SYSCALL4, handle_exception);
- set_excp_vector(EXCEP_SYSCALL5, handle_exception);
- set_excp_vector(EXCEP_SYSCALL6, handle_exception);
- set_excp_vector(EXCEP_SYSCALL7, handle_exception);
- set_excp_vector(EXCEP_SYSCALL8, handle_exception);
- set_excp_vector(EXCEP_SYSCALL9, handle_exception);
- set_excp_vector(EXCEP_SYSCALL10, handle_exception);
- set_excp_vector(EXCEP_SYSCALL11, handle_exception);
- set_excp_vector(EXCEP_SYSCALL12, handle_exception);
- set_excp_vector(EXCEP_SYSCALL13, handle_exception);
- set_excp_vector(EXCEP_SYSCALL14, handle_exception);
- set_excp_vector(EXCEP_SYSCALL15, handle_exception);
-}
-
-/*
- * determine if a program counter value is a valid bug address
- */
-int is_valid_bugaddr(unsigned long pc)
-{
- return pc >= PAGE_OFFSET;
-}
diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S
deleted file mode 100644
index 2d5f1c3f1afb..000000000000
--- a/arch/mn10300/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/* MN10300 Main kernel linker script
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#define __VMLINUX_LDS__
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/thread_info.h>
-#include <asm/page.h>
-
-OUTPUT_FORMAT("elf32-am33lin", "elf32-am33lin", "elf32-am33lin")
-OUTPUT_ARCH(mn10300)
-ENTRY(_start)
-jiffies = jiffies_64;
-#ifndef CONFIG_MN10300_CURRENT_IN_E2
-current = __current;
-#endif
-SECTIONS
-{
- . = CONFIG_KERNEL_TEXT_ADDRESS;
- /* read-only */
- _stext = .;
- _text = .; /* Text and read-only data */
- .text : {
- HEAD_TEXT
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- KPROBES_TEXT
- *(.fixup)
- *(.gnu.warning)
- } = 0xcb
-
- _etext = .; /* End of text section */
-
- EXCEPTION_TABLE(16)
- BUG_TABLE
-
- RO_DATA(PAGE_SIZE)
-
- /* writeable */
- _sdata = .; /* Start of rw data section */
- RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE)
- _edata = .;
-
- /* might get freed after init */
- . = ALIGN(PAGE_SIZE);
- .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
- __smp_locks = .;
- *(.smp_locks)
- __smp_locks_end = .;
- }
-
- /* will be freed after init */
- . = ALIGN(PAGE_SIZE); /* Init code and data */
- __init_begin = .;
- INIT_TEXT_SECTION(PAGE_SIZE)
- INIT_DATA_SECTION(16)
- . = ALIGN(4);
- __alt_instructions = .;
- .altinstructions : { *(.altinstructions) }
- __alt_instructions_end = .;
- .altinstr_replacement : { *(.altinstr_replacement) }
- /* .exit.text is discard at runtime, not link time, to deal with references
- from .altinstructions and .eh_frame */
- .exit.text : { EXIT_TEXT; }
- .exit.data : { EXIT_DATA; }
-
- PERCPU_SECTION(32)
- . = ALIGN(PAGE_SIZE);
- __init_end = .;
- /* freed after init ends here */
-
- BSS_SECTION(0, PAGE_SIZE, 4)
-
- _end = . ;
-
- /* This is where the kernel creates the early boot page tables */
- . = ALIGN(PAGE_SIZE);
- pg0 = .;
-
- STABS_DEBUG
-
- DWARF_DEBUG
-
- /* Sections to be discarded */
- DISCARDS
-}
diff --git a/arch/mn10300/lib/Makefile b/arch/mn10300/lib/Makefile
deleted file mode 100644
index 0cd2346f4c13..000000000000
--- a/arch/mn10300/lib/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for the MN10300-specific library files..
-#
-
-lib-y = delay.o usercopy.o checksum.o bitops.o memcpy.o memmove.o memset.o
-lib-y += do_csum.o
-lib-y += __ashldi3.o __ashrdi3.o __lshrdi3.o negdi2.o __ucmpdi2.o
diff --git a/arch/mn10300/lib/__ashldi3.S b/arch/mn10300/lib/__ashldi3.S
deleted file mode 100644
index a51a9506f00c..000000000000
--- a/arch/mn10300/lib/__ashldi3.S
+++ /dev/null
@@ -1,51 +0,0 @@
-/* MN10300 64-bit arithmetic left shift
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm/cache.h>
-
- .text
- .balign L1_CACHE_BYTES
-
-###############################################################################
-#
-# unsigned long long __ashldi3(unsigned long long value [D1:D0],
-# unsigned by [(12,SP)])
-#
-###############################################################################
- .globl __ashldi3
- .type __ashldi3,@function
-__ashldi3:
- mov (12,sp),a0
- and +63,a0
- beq __ashldi3_zero
-
- cmp +31,a0
- bhi __ashldi3_32plus
-
- # the count is in the range 1-31
- asl a0,d1
-
- mov +32,a1
- sub a0,a1,a1 # a1 = 32 - count
- lsr a1,d0,a1 # get overflow from LSW -> MSW
-
- or_asl a1,d1,a0,d0 # insert overflow into MSW and
- # shift the LSW
- rets
-
- .balign L1_CACHE_BYTES
- # the count is in the range 32-63
-__ashldi3_32plus:
- asl a0,d0,d1
- clr d0
-__ashldi3_zero:
- rets
-
- .size __ashldi3, .-__ashldi3
diff --git a/arch/mn10300/lib/__ashrdi3.S b/arch/mn10300/lib/__ashrdi3.S
deleted file mode 100644
index 6f42382728cb..000000000000
--- a/arch/mn10300/lib/__ashrdi3.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/* MN10300 64-bit arithmetic right shift
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm/cache.h>
-
- .text
- .balign L1_CACHE_BYTES
-
-###############################################################################
-#
-# unsigned long long __ashrdi3(unsigned long long value [D1:D0],
-# unsigned by [(12,SP)])
-#
-###############################################################################
- .globl __ashrdi3
- .type __ashrdi3,@function
-__ashrdi3:
- mov (12,sp),a0
- and +63,a0
- beq __ashrdi3_zero
-
- cmp +31,a0
- bhi __ashrdi3_32plus
-
- # the count is in the range 1-31
- lsr a0,d0
-
- mov +32,a1
- sub a0,a1,a1 # a1 = 32 - count
- asl a1,d1,a1 # get underflow from MSW -> LSW
-
- or_asr a1,d0,a0,d1 # insert underflow into LSW and
- # shift the MSW
- rets
-
- .balign L1_CACHE_BYTES
- # the count is in the range 32-63
-__ashrdi3_32plus:
- asr a0,d1,d0
- ext d0 # sign-extend result through MDR
- mov mdr,d1
-__ashrdi3_zero:
- rets
-
- .size __ashrdi3, .-__ashrdi3
diff --git a/arch/mn10300/lib/__lshrdi3.S b/arch/mn10300/lib/__lshrdi3.S
deleted file mode 100644
index a686aef31e90..000000000000
--- a/arch/mn10300/lib/__lshrdi3.S
+++ /dev/null
@@ -1,52 +0,0 @@
-/* MN10300 64-bit logical right shift
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <asm/cache.h>
-
- .text
- .balign L1_CACHE_BYTES
-
-###############################################################################
-#
-# unsigned long long __lshrdi3(unsigned long long value [D1:D0],
-# unsigned by [(12,SP)])
-#
-###############################################################################
- .globl __lshrdi3
- .type __lshrdi3,@function
-__lshrdi3:
- mov (12,sp),a0
- and +63,a0
- beq __lshrdi3_zero
-
- cmp +31,a0
- bhi __lshrdi3_32plus
-
- # the count is in the range 1-31
- lsr a0,d0
-
- mov +32,a1
- sub a0,a1,a1 # a1 = 32 - count
- asl a1,d1,a1 # get underflow from MSW -> LSW
-
- or_lsr a1,d0,a0,d1 # insert underflow into LSW and
- # shift the MSW
- rets
-
- .balign L1_CACHE_BYTES
- # the count is in the range 32-63
-__lshrdi3_32plus:
- lsr a0,d1,d0
- clr d1
-__lshrdi3_zero:
- rets
-
- .size __lshrdi3, .-__lshrdi3
diff --git a/arch/mn10300/lib/__ucmpdi2.S b/arch/mn10300/lib/__ucmpdi2.S
deleted file mode 100644
index 60dcbdfe386c..000000000000
--- a/arch/mn10300/lib/__ucmpdi2.S
+++ /dev/null
@@ -1,43 +0,0 @@
-/* __ucmpdi2.S: 64-bit unsigned compare
- *
- * Copyright (C) 2008 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-
- .text
- .p2align 4
-
-###############################################################################
-#
-# int __ucmpdi2(unsigned long long a [D0:D1],
-# unsigned long long b [(SP,12),(SP,16)])
-#
-# - returns 0, 1, or 2 as a <, =, > b respectively.
-#
-###############################################################################
- .globl __ucmpdi2
- .type __ucmpdi2,@function
-__ucmpdi2:
- mov (12,sp),a0 # b.lsw
- mov (16,sp),a1 # b.msw
-
- sub a0,d0
- subc a1,d1 # may clear Z, never sets it
- bne __ucmpdi2_differ # a.msw != b.msw
- mov +1,d0
- rets
-
-__ucmpdi2_differ:
- # C flag is set if LE, clear if GE
- subc d0,d0 # -1 if LE, 0 if GE
- add +1,d0 # 0 if LE, 1 if GE
- add d0,d0 # 0 if LE, 2 if GE
- rets
-
- .size __ucmpdi2, .-__ucmpdi2
diff --git a/arch/mn10300/lib/ashrdi3.c b/arch/mn10300/lib/ashrdi3.c
deleted file mode 100644
index c54f61ddf0b5..000000000000
--- a/arch/mn10300/lib/ashrdi3.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* ashrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */
-/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public Licence as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public Licence for more details.
-
-You should have received a copy of the GNU General Public Licence
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define BITS_PER_UNIT 8
-
-typedef int SItype __attribute__((mode(SI)));
-typedef unsigned int USItype __attribute__((mode(SI)));
-typedef int DItype __attribute__((mode(DI)));
-typedef int word_type __attribute__((mode(__word__)));
-
-struct DIstruct {
- SItype low;
- SItype high;
-};
-
-union DIunion {
- struct DIstruct s;
- DItype ll;
-};
-
-DItype __ashrdi3(DItype u, word_type b)
-{
- union DIunion w;
- union DIunion uu;
- word_type bm;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- /* w.s.high = 1..1 or 0..0 */
- w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
- w.s.low = uu.s.high >> -bm;
- } else {
- USItype carries = (USItype)uu.s.high << bm;
- w.s.high = uu.s.high >> b;
- w.s.low = ((USItype)uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/mn10300/lib/bitops.c b/arch/mn10300/lib/bitops.c
deleted file mode 100644
index 37309cdb7584..000000000000
--- a/arch/mn10300/lib/bitops.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* MN10300 Non-trivial bit operations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <asm/bitops.h>
-
-/*
- * try flipping a bit using BSET and BCLR
- */
-void change_bit(unsigned long nr, volatile void *addr)
-{
- if (test_bit(nr, addr))
- goto try_clear_bit;
-
-try_set_bit:
- if (!test_and_set_bit(nr, addr))
- return;
-
-try_clear_bit:
- if (test_and_clear_bit(nr, addr))
- return;
-
- goto try_set_bit;
-}
-
-/*
- * try flipping a bit using BSET and BCLR and returning the old value
- */
-int test_and_change_bit(unsigned long nr, volatile void *addr)
-{
- if (test_bit(nr, addr))
- goto try_clear_bit;
-
-try_set_bit:
- if (!test_and_set_bit(nr, addr))
- return 0;
-
-try_clear_bit:
- if (test_and_clear_bit(nr, addr))
- return 1;
-
- goto try_set_bit;
-}
diff --git a/arch/mn10300/lib/checksum.c b/arch/mn10300/lib/checksum.c
deleted file mode 100644
index 0f569151ef11..000000000000
--- a/arch/mn10300/lib/checksum.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* MN10300 Optimised checksumming wrappers
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <asm/byteorder.h>
-#include <linux/uaccess.h>
-#include <asm/checksum.h>
-#include "internal.h"
-
-static inline unsigned short from32to16(__wsum sum)
-{
- asm(" add %1,%0 \n"
- " addc 0xffff,%0 \n"
- : "=r" (sum)
- : "r" (sum << 16), "0" (sum & 0xffff0000)
- : "cc"
- );
- return sum >> 16;
-}
-
-__sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- return ~do_csum(iph, ihl * 4);
-}
-EXPORT_SYMBOL(ip_fast_csum);
-
-__wsum csum_partial(const void *buff, int len, __wsum sum)
-{
- __wsum result;
-
- result = do_csum(buff, len);
- result += sum;
- if (sum > result)
- result++;
- return result;
-}
-EXPORT_SYMBOL(csum_partial);
-
-__sum16 ip_compute_csum(const void *buff, int len)
-{
- return ~from32to16(do_csum(buff, len));
-}
-EXPORT_SYMBOL(ip_compute_csum);
-
-__wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum)
-{
- copy_from_user(dst, src, len);
- return csum_partial(dst, len, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy);
-
-__wsum csum_partial_copy_nocheck(const void *src, void *dst,
- int len, __wsum sum)
-{
- sum = csum_partial(src, len, sum);
- memcpy(dst, src, len);
- return sum;
-}
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
-
-__wsum csum_partial_copy_from_user(const void *src, void *dst,
- int len, __wsum sum,
- int *err_ptr)
-{
- int missing;
-
- missing = copy_from_user(dst, src, len);
- if (missing) {
- memset(dst + len - missing, 0, missing);
- *err_ptr = -EFAULT;
- }
-
- return csum_partial(dst, len, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy_from_user);
-
-__wsum csum_and_copy_to_user(const void *src, void *dst,
- int len, __wsum sum,
- int *err_ptr)
-{
- int missing;
-
- missing = copy_to_user(dst, src, len);
- if (missing) {
- memset(dst + len - missing, 0, missing);
- *err_ptr = -EFAULT;
- }
-
- return csum_partial(src, len, sum);
-}
-EXPORT_SYMBOL(csum_and_copy_to_user);
diff --git a/arch/mn10300/lib/delay.c b/arch/mn10300/lib/delay.c
deleted file mode 100644
index 8e7ceb8ba33d..000000000000
--- a/arch/mn10300/lib/delay.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* MN10300 Short delay interpolation routines
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/delay.h>
-#include <asm/div64.h>
-
-/*
- * basic delay loop
- */
-void __delay(unsigned long loops)
-{
- int d0;
-
- asm volatile(
- " bra 1f \n"
- " .align 4 \n"
- "1: bra 2f \n"
- " .align 4 \n"
- "2: add -1,%0 \n"
- " bne 2b \n"
- : "=&d" (d0)
- : "0" (loops)
- : "cc");
-}
-EXPORT_SYMBOL(__delay);
-
-/*
- * handle a delay specified in terms of microseconds
- */
-void __udelay(unsigned long usecs)
-{
- unsigned long start, stop, cnt;
-
- /* usecs * CLK / 1E6 */
- stop = __muldiv64u(usecs, MN10300_TSCCLK, 1000000);
- start = TMTSCBC;
-
- do {
- cnt = start - TMTSCBC;
- } while (cnt < stop);
-}
-EXPORT_SYMBOL(__udelay);
diff --git a/arch/mn10300/lib/do_csum.S b/arch/mn10300/lib/do_csum.S
deleted file mode 100644
index 1d27bba0cd8f..000000000000
--- a/arch/mn10300/lib/do_csum.S
+++ /dev/null
@@ -1,157 +0,0 @@
-/* Optimised simple memory checksum
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm/cache.h>
-
- .section .text
- .balign L1_CACHE_BYTES
-
-###############################################################################
-#
-# unsigned int do_csum(const unsigned char *buff, int len)
-#
-###############################################################################
- .globl do_csum
- .type do_csum,@function
-do_csum:
- movm [d2,d3],(sp)
- mov d1,d2 # count
- mov d0,a0 # buff
- mov a0,a1
- clr d1 # accumulator
-
- cmp +0,d2
- ble do_csum_done # check for zero length or negative
-
- # 4-byte align the buffer pointer
- btst +3,a0
- beq do_csum_now_4b_aligned
-
- btst +1,a0
- beq do_csum_addr_not_odd
- movbu (a0),d0
- inc a0
- asl +8,d0
- add d0,d1
- add -1,d2
-
-do_csum_addr_not_odd:
- cmp +2,d2
- bcs do_csum_fewer_than_4
- btst +2,a0
- beq do_csum_now_4b_aligned
- movhu (a0+),d0
- add d0,d1
- add -2,d2
- cmp +4,d2
- bcs do_csum_fewer_than_4
-
-do_csum_now_4b_aligned:
- # we want to checksum as much as we can in chunks of 32 bytes
- cmp +31,d2
- bls do_csum_remainder # 4-byte aligned remainder
-
- add -32,d2
- mov +32,d3
-
-do_csum_loop:
- mov (a0+),d0
- mov (a0+),e0
- mov (a0+),e1
- mov (a0+),e3
- add d0,d1
- addc e0,d1
- addc e1,d1
- addc e3,d1
- mov (a0+),d0
- mov (a0+),e0
- mov (a0+),e1
- mov (a0+),e3
- addc d0,d1
- addc e0,d1
- addc e1,d1
- addc e3,d1
- addc +0,d1
-
- sub d3,d2
- bcc do_csum_loop
-
- add d3,d2
- beq do_csum_done
-
-do_csum_remainder:
- # cut 16-31 bytes down to 0-15
- cmp +16,d2
- bcs do_csum_fewer_than_16
- mov (a0+),d0
- mov (a0+),e0
- mov (a0+),e1
- mov (a0+),e3
- add d0,d1
- addc e0,d1
- addc e1,d1
- addc e3,d1
- addc +0,d1
- add -16,d2
- beq do_csum_done
-
-do_csum_fewer_than_16:
- # copy the remaining whole words
- cmp +4,d2
- bcs do_csum_fewer_than_4
- cmp +8,d2
- bcs do_csum_one_word
- cmp +12,d2
- bcs do_csum_two_words
- mov (a0+),d0
- add d0,d1
- addc +0,d1
-do_csum_two_words:
- mov (a0+),d0
- add d0,d1
- addc +0,d1
-do_csum_one_word:
- mov (a0+),d0
- add d0,d1
- addc +0,d1
-
-do_csum_fewer_than_4:
- and +3,d2
- beq do_csum_done
- xor_cmp d0,d0,+2,d2
- bcs do_csum_fewer_than_2
- movhu (a0+),d0
- and +1,d2
- beq do_csum_add_last_bit
-do_csum_fewer_than_2:
- movbu (a0),d3
- add d3,d0
-do_csum_add_last_bit:
- add d0,d1
- addc +0,d1
-
-do_csum_done:
- # compress the checksum down to 16 bits
- mov +0xffff0000,d0
- and d1,d0
- asl +16,d1
- add d1,d0
- addc +0xffff,d0
- lsr +16,d0
-
- # flip the halves of the word result if the buffer was oddly aligned
- and +1,a1
- beq do_csum_not_oddly_aligned
- swaph d0,d0 # exchange bits 15:8 with 7:0
-
-do_csum_not_oddly_aligned:
- ret [d2,d3],8
-
- .size do_csum, .-do_csum
diff --git a/arch/mn10300/lib/internal.h b/arch/mn10300/lib/internal.h
deleted file mode 100644
index 0014eee5f04f..000000000000
--- a/arch/mn10300/lib/internal.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Internal definitions for the arch part of the kernel library
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-/*
- * do_csum.S
- */
-extern unsigned int do_csum(const unsigned char *, size_t);
diff --git a/arch/mn10300/lib/lshrdi3.c b/arch/mn10300/lib/lshrdi3.c
deleted file mode 100644
index e05e64e9ce96..000000000000
--- a/arch/mn10300/lib/lshrdi3.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* lshrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */
-/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public Licence as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public Licence for more details.
-
-You should have received a copy of the GNU General Public Licence
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define BITS_PER_UNIT 8
-
-typedef int SItype __attribute__((mode(SI)));
-typedef unsigned int USItype __attribute__((mode(SI)));
-typedef int DItype __attribute__((mode(DI)));
-typedef int word_type __attribute__((mode(__word__)));
-
-struct DIstruct {
- SItype low;
- SItype high;
-};
-
-union DIunion {
- struct DIstruct s;
- DItype ll;
-};
-
-DItype __lshrdi3(DItype u, word_type b)
-{
- union DIunion w;
- word_type bm;
- union DIunion uu;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
-
- bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
- if (bm <= 0) {
- w.s.high = 0;
- w.s.low = (USItype) uu.s.high >> -bm;
- } else {
- USItype carries = (USItype) uu.s.high << bm;
- w.s.high = (USItype) uu.s.high >> b;
- w.s.low = ((USItype) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
diff --git a/arch/mn10300/lib/memcpy.S b/arch/mn10300/lib/memcpy.S
deleted file mode 100644
index 25fb9bb2604f..000000000000
--- a/arch/mn10300/lib/memcpy.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/* MN10300 Optimised simple memory to memory copy
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm/cache.h>
-
- .section .text
- .balign L1_CACHE_BYTES
-
-###############################################################################
-#
-# void *memcpy(void *dst, const void *src, size_t n)
-#
-###############################################################################
- .globl memcpy
- .type memcpy,@function
-memcpy:
- movm [d2,d3],(sp)
- mov d0,(12,sp)
- mov d1,(16,sp)
- mov (20,sp),d2 # count
- mov d0,a0 # dst
- mov d1,a1 # src
- mov d0,e3 # the return value
-
- cmp +0,d2
- beq memcpy_done # return if zero-length copy
-
- # see if the three parameters are all four-byte aligned
- or d0,d1,d3
- or d2,d3
- and +3,d3
- bne memcpy_1 # jump if not
-
- # we want to transfer as much as we can in chunks of 32 bytes
- cmp +31,d2
- bls memcpy_4_remainder # 4-byte aligned remainder
-
- movm [exreg1],(sp)
- add -32,d2
- mov +32,d3
-
-memcpy_4_loop:
- mov (a1+),d0
- mov (a1+),d1
- mov (a1+),e0
- mov (a1+),e1
- mov (a1+),e4
- mov (a1+),e5
- mov (a1+),e6
- mov (a1+),e7
- mov d0,(a0+)
- mov d1,(a0+)
- mov e0,(a0+)
- mov e1,(a0+)
- mov e4,(a0+)
- mov e5,(a0+)
- mov e6,(a0+)
- mov e7,(a0+)
-
- sub d3,d2
- bcc memcpy_4_loop
-
- movm (sp),[exreg1]
- add d3,d2
- beq memcpy_4_no_remainder
-
-memcpy_4_remainder:
- # cut 4-7 words down to 0-3
- cmp +16,d2
- bcs memcpy_4_three_or_fewer_words
- mov (a1+),d0
- mov (a1+),d1
- mov (a1+),e0
- mov (a1+),e1
- mov d0,(a0+)
- mov d1,(a0+)
- mov e0,(a0+)
- mov e1,(a0+)
- add -16,d2
- beq memcpy_4_no_remainder
-
- # copy the remaining 1, 2 or 3 words
-memcpy_4_three_or_fewer_words:
- cmp +8,d2
- bcs memcpy_4_one_word
- beq memcpy_4_two_words
- mov (a1+),d0
- mov d0,(a0+)
-memcpy_4_two_words:
- mov (a1+),d0
- mov d0,(a0+)
-memcpy_4_one_word:
- mov (a1+),d0
- mov d0,(a0+)
-
-memcpy_4_no_remainder:
- # check we copied the correct amount
- # TODO: REMOVE CHECK
- sub e3,a0,d2
- mov (20,sp),d1
- cmp d2,d1
- beq memcpy_done
- break
- break
- break
-
-memcpy_done:
- mov e3,a0
- ret [d2,d3],8
-
- # handle misaligned copying
-memcpy_1:
- add -1,d2
- mov +1,d3
- setlb # setlb requires the next insns
- # to occupy exactly 4 bytes
-
- sub d3,d2
- movbu (a1),d0
- movbu d0,(a0)
- add_add d3,a1,d3,a0
- lcc
-
- mov e3,a0
- ret [d2,d3],8
-
-memcpy_end:
- .size memcpy, memcpy_end-memcpy
diff --git a/arch/mn10300/lib/memmove.S b/arch/mn10300/lib/memmove.S
deleted file mode 100644
index 20b07b62b77c..000000000000
--- a/arch/mn10300/lib/memmove.S
+++ /dev/null
@@ -1,160 +0,0 @@
-/* MN10300 Optimised simple memory to memory copy, with support for overlapping
- * regions
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm/cache.h>
-
- .section .text
- .balign L1_CACHE_BYTES
-
-###############################################################################
-#
-# void *memmove(void *dst, const void *src, size_t n)
-#
-###############################################################################
- .globl memmove
- .type memmove,@function
-memmove:
- # fall back to memcpy if dst < src to work bottom up
- cmp d1,d0
- bcs memmove_memcpy
-
- # work top down
- movm [d2,d3],(sp)
- mov d0,(12,sp)
- mov d1,(16,sp)
- mov (20,sp),d2 # count
- add d0,d2,a0 # dst end
- add d1,d2,a1 # src end
- mov d0,e3 # the return value
-
- cmp +0,d2
- beq memmove_done # return if zero-length copy
-
- # see if the three parameters are all four-byte aligned
- or d0,d1,d3
- or d2,d3
- and +3,d3
- bne memmove_1 # jump if not
-
- # we want to transfer as much as we can in chunks of 32 bytes
- add -4,a1
- cmp +31,d2
- bls memmove_4_remainder # 4-byte aligned remainder
-
- add -32,d2
- mov +32,d3
-
-memmove_4_loop:
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
- mov (a1),d1
- sub_sub +4,a1,+4,a0
- mov d1,(a0)
-
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
- mov (a1),d1
- sub_sub +4,a1,+4,a0
- mov d1,(a0)
-
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
- mov (a1),d1
- sub_sub +4,a1,+4,a0
- mov d1,(a0)
-
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
- mov (a1),d1
- sub_sub +4,a1,+4,a0
- mov d1,(a0)
-
- sub d3,d2
- bcc memmove_4_loop
-
- add d3,d2
- beq memmove_4_no_remainder
-
-memmove_4_remainder:
- # cut 4-7 words down to 0-3
- cmp +16,d2
- bcs memmove_4_three_or_fewer_words
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
- mov (a1),d1
- sub_sub +4,a1,+4,a0
- mov d1,(a0)
- mov (a1),e0
- sub_sub +4,a1,+4,a0
- mov e0,(a0)
- mov (a1),e1
- sub_sub +4,a1,+4,a0
- mov e1,(a0)
- add -16,d2
- beq memmove_4_no_remainder
-
- # copy the remaining 1, 2 or 3 words
-memmove_4_three_or_fewer_words:
- cmp +8,d2
- bcs memmove_4_one_word
- beq memmove_4_two_words
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
-memmove_4_two_words:
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
-memmove_4_one_word:
- mov (a1),d0
- sub_sub +4,a1,+4,a0
- mov d0,(a0)
-
-memmove_4_no_remainder:
- # check we copied the correct amount
- # TODO: REMOVE CHECK
- sub e3,a0,d2
- beq memmove_done
- break
- break
- break
-
-memmove_done:
- mov e3,a0
- ret [d2,d3],8
-
- # handle misaligned copying
-memmove_1:
- add -1,a1
- add -1,d2
- mov +1,d3
- setlb # setlb requires the next insns
- # to occupy exactly 4 bytes
-
- sub d3,d2
- movbu (a1),d0
- sub_sub d3,a1,d3,a0
- movbu d0,(a0)
- lcc
-
- mov e3,a0
- ret [d2,d3],8
-
-memmove_memcpy:
- jmp memcpy
-
-memmove_end:
- .size memmove, memmove_end-memmove
diff --git a/arch/mn10300/lib/memset.S b/arch/mn10300/lib/memset.S
deleted file mode 100644
index bc02e39629b7..000000000000
--- a/arch/mn10300/lib/memset.S
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Optimised simple memory fill
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <asm/cache.h>
-
- .section .text
- .balign L1_CACHE_BYTES
-
-###############################################################################
-#
-# void *memset(void *dst, int c, size_t n)
-#
-###############################################################################
- .globl memset
- .type memset,@function
-memset:
- movm [d2,d3],(sp)
- mov d0,(12,sp)
- mov d1,(16,sp)
- mov (20,sp),d2 # count
- mov d0,a0 # dst
- mov d0,e3 # the return value
-
- cmp +0,d2
- beq memset_done # return if zero-length fill
-
- # see if the region parameters are four-byte aligned
- or d0,d2,d3
- and +3,d3
- bne memset_1 # jump if not
-
- extbu d1
- mov_asl d1,d3,8,d1
- or_asl d1,d3,8,d1
- or_asl d1,d3,8,d1
- or d3,d1
-
- # we want to transfer as much as we can in chunks of 32 bytes
- cmp +31,d2
- bls memset_4_remainder # 4-byte aligned remainder
-
- add -32,d2
- mov +32,d3
-
-memset_4_loop:
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
-
- sub d3,d2
- bcc memset_4_loop
-
- add d3,d2
- beq memset_4_no_remainder
-
-memset_4_remainder:
- # cut 4-7 words down to 0-3
- cmp +16,d2
- bcs memset_4_three_or_fewer_words
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
- mov d1,(a0+)
- add -16,d2
- beq memset_4_no_remainder
-
- # copy the remaining 1, 2 or 3 words
-memset_4_three_or_fewer_words:
- cmp +8,d2
- bcs memset_4_one_word
- beq memset_4_two_words
- mov d1,(a0+)
-memset_4_two_words:
- mov d1,(a0+)
-memset_4_one_word:
- mov d1,(a0+)
-
-memset_4_no_remainder:
- # check we set the correct amount
- # TODO: REMOVE CHECK
- sub e3,a0,d2
- mov (20,sp),d1
- cmp d2,d1
- beq memset_done
- break
- break
- break
-
-memset_done:
- mov e3,a0
- ret [d2,d3],8
-
- # handle misaligned copying
-memset_1:
- add -1,d2
- mov +1,d3
- setlb # setlb requires the next insns
- # to occupy exactly 4 bytes
-
- sub d3,d2
- movbu d1,(a0)
- inc a0
- lcc
-
- mov e3,a0
- ret [d2,d3],8
-
-memset_end:
- .size memset, memset_end-memset
diff --git a/arch/mn10300/lib/negdi2.c b/arch/mn10300/lib/negdi2.c
deleted file mode 100644
index eae4ecdd5f69..000000000000
--- a/arch/mn10300/lib/negdi2.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* More subroutines needed by GCC output code on some machines. */
-/* Compile this one with gcc. */
-/* Copyright (C) 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public Licence as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-In addition to the permissions in the GNU General Public Licence, the
-Free Software Foundation gives you unlimited permission to link the
-compiled version of this file into combinations with other programs,
-and to distribute those combinations without any restriction coming
-from the use of this file. (The General Public Licence restrictions
-do apply in other respects; for example, they cover modification of
-the file, and distribution when not linked into a combine
-executable.)
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public Licence for more details.
-
-You should have received a copy of the GNU General Public Licence
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-/* It is incorrect to include config.h here, because this file is being
- compiled for the target, and hence definitions concerning only the host
- do not apply. */
-
-#include <linux/types.h>
-
-union DWunion {
- s64 ll;
- struct {
- s32 low;
- s32 high;
- } s;
-};
-
-s64 __negdi2(s64 u)
-{
- union DWunion w;
- union DWunion uu;
-
- uu.ll = u;
-
- w.s.low = -uu.s.low;
- w.s.high = -uu.s.high - ((u32) w.s.low > 0);
-
- return w.ll;
-}
diff --git a/arch/mn10300/lib/usercopy.c b/arch/mn10300/lib/usercopy.c
deleted file mode 100644
index 39626912de98..000000000000
--- a/arch/mn10300/lib/usercopy.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* MN10300 Userspace accessor functions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/uaccess.h>
-
-/*
- * Copy a null terminated string from userspace.
- */
-#define __do_strncpy_from_user(dst, src, count, res) \
-do { \
- int w; \
- asm volatile( \
- " mov %1,%0\n" \
- " cmp 0,%1\n" \
- " beq 2f\n" \
- "0:\n" \
- " movbu (%5),%2\n" \
- "1:\n" \
- " movbu %2,(%6)\n" \
- " inc %5\n" \
- " inc %6\n" \
- " cmp 0,%2\n" \
- " beq 2f\n" \
- " add -1,%1\n" \
- " bne 0b\n" \
- "2:\n" \
- " sub %1,%0\n" \
- "3:\n" \
- " .section .fixup,\"ax\"\n" \
- "4:\n" \
- " mov %3,%0\n" \
- " jmp 3b\n" \
- " .previous\n" \
- " .section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,4b\n" \
- " .long 1b,4b\n" \
- " .previous" \
- :"=&r"(res), "=r"(count), "=&r"(w) \
- :"i"(-EFAULT), "1"(count), "a"(src), "a"(dst) \
- : "memory", "cc"); \
-} while (0)
-
-long
-strncpy_from_user(char *dst, const char *src, long count)
-{
- long res = -EFAULT;
- if (access_ok(VERIFY_READ, src, 1))
- __do_strncpy_from_user(dst, src, count, res);
- return res;
-}
-
-
-/*
- * Clear a userspace memory
- */
-#define __do_clear_user(addr, size) \
-do { \
- int w; \
- asm volatile( \
- " cmp 0,%0\n" \
- " beq 1f\n" \
- " clr %1\n" \
- "0: movbu %1,(%3,%2)\n" \
- " inc %3\n" \
- " cmp %0,%3\n" \
- " bne 0b\n" \
- "1:\n" \
- " sub %3,%0\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3: jmp 2b\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- " .balign 4\n" \
- " .long 0b,3b\n" \
- ".previous\n" \
- : "+r"(size), "=&r"(w) \
- : "a"(addr), "d"(0) \
- : "memory", "cc"); \
-} while (0)
-
-unsigned long
-__clear_user(void *to, unsigned long n)
-{
- __do_clear_user(to, n);
- return n;
-}
-
-unsigned long
-clear_user(void *to, unsigned long n)
-{
- if (access_ok(VERIFY_WRITE, to, n))
- __do_clear_user(to, n);
- return n;
-}
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-long strnlen_user(const char *s, long n)
-{
- unsigned long res, w;
-
- if (!__addr_ok(s))
- return 0;
-
- if (n < 0 || n + (u_long) s > current_thread_info()->addr_limit.seg)
- n = current_thread_info()->addr_limit.seg - (u_long)s;
-
- asm volatile(
- "0: cmp %4,%0\n"
- " beq 2f\n"
- "1: movbu (%0,%3),%1\n"
- " inc %0\n"
- " cmp 0,%1\n"
- " beq 3f\n"
- " bra 0b\n"
- "2: clr %0\n"
- "3:\n"
- ".section .fixup,\"ax\"\n"
- "4: jmp 2b\n"
- ".previous\n"
- ".section __ex_table,\"a\"\n"
- " .balign 4\n"
- " .long 1b,4b\n"
- ".previous\n"
- :"=d"(res), "=&r"(w)
- :"0"(0), "a"(s), "r"(n)
- : "memory", "cc");
- return res;
-}
diff --git a/arch/mn10300/mm/Kconfig.cache b/arch/mn10300/mm/Kconfig.cache
deleted file mode 100644
index 8cc5d9ec3b6c..000000000000
--- a/arch/mn10300/mm/Kconfig.cache
+++ /dev/null
@@ -1,148 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# MN10300 CPU cache options
-#
-
-choice
- prompt "CPU Caching mode"
- default MN10300_CACHE_WBACK
- help
- This option determines the caching mode for the kernel.
-
- Write-Back caching mode involves the all reads and writes causing
- the affected cacheline to be read into the cache first before being
- operated upon. Memory is not then updated by a write until the cache
- is filled and a cacheline needs to be displaced from the cache to
- make room. Only at that point is it written back.
-
- Write-Through caching only fetches cachelines from memory on a
- read. Writes always get written directly to memory. If the affected
- cacheline is also in cache, it will be updated too.
-
- The final option is to turn of caching entirely.
-
-config MN10300_CACHE_WBACK
- bool "Write-Back"
- help
- The dcache operates in delayed write-back mode. It must be manually
- flushed if writes are made that subsequently need to be executed or
- to be DMA'd by a device.
-
-config MN10300_CACHE_WTHRU
- bool "Write-Through"
- help
- The dcache operates in immediate write-through mode. Writes are
- committed to RAM immediately in addition to being stored in the
- cache. This means that the written data is immediately available for
- execution or DMA.
-
- This is not available for use with an SMP kernel if cache flushing
- and invalidation by automatic purge register is not selected.
-
-config MN10300_CACHE_DISABLED
- bool "Disabled"
- help
- The icache and dcache are disabled.
-
-endchoice
-
-config MN10300_CACHE_ENABLED
- def_bool y if !MN10300_CACHE_DISABLED
-
-
-choice
- prompt "CPU cache flush/invalidate method"
- default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2
- default MN10300_CACHE_MANAGE_BY_REG if AM34_2
- depends on MN10300_CACHE_ENABLED
- help
- This determines the method by which CPU cache flushing and
- invalidation is performed.
-
-config MN10300_CACHE_MANAGE_BY_TAG
- bool "Use the cache tag registers directly"
- depends on !(SMP && MN10300_CACHE_WTHRU)
-
-config MN10300_CACHE_MANAGE_BY_REG
- bool "Flush areas by way of automatic purge registers (AM34 only)"
- depends on AM34_2
-
-endchoice
-
-config MN10300_CACHE_INV_BY_TAG
- def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED
-
-config MN10300_CACHE_INV_BY_REG
- def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED
-
-config MN10300_CACHE_FLUSH_BY_TAG
- def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK
-
-config MN10300_CACHE_FLUSH_BY_REG
- def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK
-
-
-config MN10300_HAS_CACHE_SNOOP
- def_bool n
-
-config MN10300_CACHE_SNOOP
- bool "Use CPU Cache Snooping"
- depends on MN10300_CACHE_ENABLED && MN10300_HAS_CACHE_SNOOP
- default y
-
-config MN10300_CACHE_FLUSH_ICACHE
- def_bool y if MN10300_CACHE_WBACK && !MN10300_CACHE_SNOOP
- help
- Set if we need the dcache flushing before the icache is invalidated.
-
-config MN10300_CACHE_INV_ICACHE
- def_bool y if MN10300_CACHE_WTHRU && !MN10300_CACHE_SNOOP
- help
- Set if we need the icache to be invalidated, even if the dcache is in
- write-through mode and doesn't need flushing.
-
-#
-# The kernel debugger gets its own separate cache flushing functions
-#
-config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG
- def_bool y if KERNEL_DEBUGGER && \
- MN10300_CACHE_WBACK && \
- !MN10300_CACHE_SNOOP && \
- MN10300_CACHE_MANAGE_BY_TAG
- help
- Set if the debugger needs to flush the dcache and invalidate the
- icache using the cache tag registers to make breakpoints work.
-
-config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG
- def_bool y if KERNEL_DEBUGGER && \
- MN10300_CACHE_WBACK && \
- !MN10300_CACHE_SNOOP && \
- MN10300_CACHE_MANAGE_BY_REG
- help
- Set if the debugger needs to flush the dcache and invalidate the
- icache using automatic purge registers to make breakpoints work.
-
-config MN10300_DEBUGGER_CACHE_INV_BY_TAG
- def_bool y if KERNEL_DEBUGGER && \
- MN10300_CACHE_WTHRU && \
- !MN10300_CACHE_SNOOP && \
- MN10300_CACHE_MANAGE_BY_TAG
- help
- Set if the debugger needs to invalidate the icache using the cache
- tag registers to make breakpoints work.
-
-config MN10300_DEBUGGER_CACHE_INV_BY_REG
- def_bool y if KERNEL_DEBUGGER && \
- MN10300_CACHE_WTHRU && \
- !MN10300_CACHE_SNOOP && \
- MN10300_CACHE_MANAGE_BY_REG
- help
- Set if the debugger needs to invalidate the icache using automatic
- purge registers to make breakpoints work.
-
-config MN10300_DEBUGGER_CACHE_NO_FLUSH
- def_bool y if KERNEL_DEBUGGER && \
- (MN10300_CACHE_DISABLED || MN10300_CACHE_SNOOP)
- help
- Set if the debugger does not need to flush the dcache and/or
- invalidate the icache to make breakpoints work.
diff --git a/arch/mn10300/mm/Makefile b/arch/mn10300/mm/Makefile
deleted file mode 100644
index 048ba6f67f9a..000000000000
--- a/arch/mn10300/mm/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the MN10300-specific memory management code
-#
-
-cache-smp-wback-$(CONFIG_MN10300_CACHE_WBACK) := cache-smp-flush.o
-
-cacheflush-y := cache.o
-cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y)
-cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
-cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o
-cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o
-cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
-cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o
-cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o
-
-cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG) += \
- cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o
-cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG) += \
- cache-dbg-flush-by-reg.o
-cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG) += \
- cache-dbg-inv-by-tag.o cache-dbg-inv.o
-cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_REG) += \
- cache-dbg-inv-by-reg.o cache-dbg-inv.o
-
-cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o
-
-obj-y := \
- init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \
- misalignment.o dma-alloc.o $(cacheflush-y)
-
-obj-$(CONFIG_SMP) += tlb-smp.o
diff --git a/arch/mn10300/mm/cache-dbg-flush-by-reg.S b/arch/mn10300/mm/cache-dbg-flush-by-reg.S
deleted file mode 100644
index a775ea5d7cee..000000000000
--- a/arch/mn10300/mm/cache-dbg-flush-by-reg.S
+++ /dev/null
@@ -1,160 +0,0 @@
-/* MN10300 CPU cache invalidation routines, using automatic purge registers
- *
- * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-#include <asm/cacheflush.h>
-#include "cache.inc"
-
- .am33_2
-
-###############################################################################
-#
-# void debugger_local_cache_flushinv(void)
-# Flush the entire data cache back to RAM and invalidate the icache
-#
-###############################################################################
- ALIGN
- .globl debugger_local_cache_flushinv
- .type debugger_local_cache_flushinv,@function
-debugger_local_cache_flushinv:
- #
- # firstly flush the dcache
- #
- movhu (CHCTR),d0
- btst CHCTR_DCEN|CHCTR_ICEN,d0
- beq debugger_local_cache_flushinv_end
-
- mov DCPGCR,a0
-
- mov epsw,d1
- and ~EPSW_IE,epsw
- or EPSW_NMID,epsw
- nop
-
- btst CHCTR_DCEN,d0
- beq debugger_local_cache_flushinv_no_dcache
-
- # wait for busy bit of area purge
- setlb
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
- # set mask
- clr d0
- mov d0,(DCPGMR)
-
- # area purge
- #
- # DCPGCR = DCPGCR_DCP
- #
- mov DCPGCR_DCP,d0
- mov d0,(a0)
-
- # wait for busy bit of area purge
- setlb
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
-debugger_local_cache_flushinv_no_dcache:
- #
- # secondly, invalidate the icache if it is enabled
- #
- mov CHCTR,a0
- movhu (a0),d0
- btst CHCTR_ICEN,d0
- beq debugger_local_cache_flushinv_done
-
- invalidate_icache 0
-
-debugger_local_cache_flushinv_done:
- mov d1,epsw
-
-debugger_local_cache_flushinv_end:
- ret [],0
- .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv
-
-###############################################################################
-#
-# void debugger_local_cache_flushinv_one(u8 *addr)
-#
-# Invalidate one particular cacheline if it's in the icache
-#
-###############################################################################
- ALIGN
- .globl debugger_local_cache_flushinv_one
- .type debugger_local_cache_flushinv_one,@function
-debugger_local_cache_flushinv_one:
- movhu (CHCTR),d1
- btst CHCTR_DCEN|CHCTR_ICEN,d1
- beq debugger_local_cache_flushinv_one_end
- btst CHCTR_DCEN,d1
- beq debugger_local_cache_flushinv_one_no_dcache
-
- # round cacheline addr down
- and L1_CACHE_TAG_MASK,d0
- mov d0,a1
- mov d0,d1
-
- # determine the dcache purge control reg address
- mov DCACHE_PURGE(0,0),a0
- and L1_CACHE_TAG_ENTRY,d0
- add d0,a0
-
- # retain valid entries in the cache
- or L1_CACHE_TAG_VALID,d1
-
- # conditionally purge this line in all ways
- mov d1,(L1_CACHE_WAYDISP*0,a0)
-
-debugger_local_cache_flushinv_one_no_dcache:
- #
- # now try to flush the icache
- #
- mov CHCTR,a0
- movhu (a0),d0
- btst CHCTR_ICEN,d0
- beq debugger_local_cache_flushinv_one_end
-
- LOCAL_CLI_SAVE(d1)
-
- mov ICIVCR,a0
-
- # wait for the invalidator to quiesce
- setlb
- mov (a0),d0
- btst ICIVCR_ICIVBSY,d0
- lne
-
- # set the mask
- mov L1_CACHE_TAG_MASK,d0
- mov d0,(ICIVMR)
-
- # invalidate the cache line at the given address
- or ICIVCR_ICI,a1
- mov a1,(a0)
-
- # wait for the invalidator to quiesce again
- setlb
- mov (a0),d0
- btst ICIVCR_ICIVBSY,d0
- lne
-
- LOCAL_IRQ_RESTORE(d1)
-
-debugger_local_cache_flushinv_one_end:
- ret [],0
- .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one
diff --git a/arch/mn10300/mm/cache-dbg-flush-by-tag.S b/arch/mn10300/mm/cache-dbg-flush-by-tag.S
deleted file mode 100644
index bf56930e6e70..000000000000
--- a/arch/mn10300/mm/cache-dbg-flush-by-tag.S
+++ /dev/null
@@ -1,114 +0,0 @@
-/* MN10300 CPU cache invalidation routines, using direct tag flushing
- *
- * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-#include <asm/cacheflush.h>
-#include "cache.inc"
-
- .am33_2
-
-###############################################################################
-#
-# void debugger_local_cache_flushinv(void)
-#
-# Flush the entire data cache back to RAM and invalidate the icache
-#
-###############################################################################
- ALIGN
- .globl debugger_local_cache_flushinv
- .type debugger_local_cache_flushinv,@function
-debugger_local_cache_flushinv:
- #
- # firstly flush the dcache
- #
- movhu (CHCTR),d0
- btst CHCTR_DCEN|CHCTR_ICEN,d0
- beq debugger_local_cache_flushinv_end
-
- btst CHCTR_DCEN,d0
- beq debugger_local_cache_flushinv_no_dcache
-
- # read the addresses tagged in the cache's tag RAM and attempt to flush
- # those addresses specifically
- # - we rely on the hardware to filter out invalid tag entry addresses
- mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
- mov DCACHE_PURGE(0,0),a1 # dcache purge request address
- mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,e0 # total number of entries
-
-mn10300_local_dcache_flush_loop:
- mov (a0),d0
- and L1_CACHE_TAG_MASK,d0
- or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
- # cache
- mov d0,(a1) # conditional purge
-
- add L1_CACHE_BYTES,a0
- add L1_CACHE_BYTES,a1
- add -1,e0
- bne mn10300_local_dcache_flush_loop
-
-debugger_local_cache_flushinv_no_dcache:
- #
- # secondly, invalidate the icache if it is enabled
- #
- mov CHCTR,a0
- movhu (a0),d0
- btst CHCTR_ICEN,d0
- beq debugger_local_cache_flushinv_end
-
- invalidate_icache 1
-
-debugger_local_cache_flushinv_end:
- ret [],0
- .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv
-
-###############################################################################
-#
-# void debugger_local_cache_flushinv_one(u8 *addr)
-#
-# Invalidate one particular cacheline if it's in the icache
-#
-###############################################################################
- ALIGN
- .globl debugger_local_cache_flushinv_one
- .type debugger_local_cache_flushinv_one,@function
-debugger_local_cache_flushinv_one:
- movhu (CHCTR),d1
- btst CHCTR_DCEN|CHCTR_ICEN,d1
- beq debugger_local_cache_flushinv_one_end
- btst CHCTR_DCEN,d1
- beq debugger_local_cache_flushinv_one_icache
-
- # round cacheline addr down
- and L1_CACHE_TAG_MASK,d0
- mov d0,a1
-
- # determine the dcache purge control reg address
- mov DCACHE_PURGE(0,0),a0
- and L1_CACHE_TAG_ENTRY,d0
- add d0,a0
-
- # retain valid entries in the cache
- or L1_CACHE_TAG_VALID,a1
-
- # conditionally purge this line in all ways
- mov a1,(L1_CACHE_WAYDISP*0,a0)
-
- # now go and do the icache
- bra debugger_local_cache_flushinv_one_icache
-
-debugger_local_cache_flushinv_one_end:
- ret [],0
- .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one
diff --git a/arch/mn10300/mm/cache-dbg-inv-by-reg.S b/arch/mn10300/mm/cache-dbg-inv-by-reg.S
deleted file mode 100644
index c4e6252941b1..000000000000
--- a/arch/mn10300/mm/cache-dbg-inv-by-reg.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/* MN10300 CPU cache invalidation routines, using automatic purge registers
- *
- * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-#include <asm/cacheflush.h>
-#include "cache.inc"
-
- .am33_2
-
- .globl debugger_local_cache_flushinv_one
-
-###############################################################################
-#
-# void debugger_local_cache_flushinv_one(u8 *addr)
-#
-# Invalidate one particular cacheline if it's in the icache
-#
-###############################################################################
- ALIGN
- .globl debugger_local_cache_flushinv_one
- .type debugger_local_cache_flushinv_one,@function
-debugger_local_cache_flushinv_one:
- mov d0,a1
-
- mov CHCTR,a0
- movhu (a0),d0
- btst CHCTR_ICEN,d0
- beq mn10300_local_icache_inv_range_reg_end
-
- LOCAL_CLI_SAVE(d1)
-
- mov ICIVCR,a0
-
- # wait for the invalidator to quiesce
- setlb
- mov (a0),d0
- btst ICIVCR_ICIVBSY,d0
- lne
-
- # set the mask
- mov ~L1_CACHE_TAG_MASK,d0
- mov d0,(ICIVMR)
-
- # invalidate the cache line at the given address
- and ~L1_CACHE_TAG_MASK,a1
- or ICIVCR_ICI,a1
- mov a1,(a0)
-
- # wait for the invalidator to quiesce again
- setlb
- mov (a0),d0
- btst ICIVCR_ICIVBSY,d0
- lne
-
- LOCAL_IRQ_RESTORE(d1)
-
-mn10300_local_icache_inv_range_reg_end:
- ret [],0
- .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one
diff --git a/arch/mn10300/mm/cache-dbg-inv-by-tag.S b/arch/mn10300/mm/cache-dbg-inv-by-tag.S
deleted file mode 100644
index d8ec821e5f88..000000000000
--- a/arch/mn10300/mm/cache-dbg-inv-by-tag.S
+++ /dev/null
@@ -1,120 +0,0 @@
-/* MN10300 CPU cache invalidation routines, using direct tag flushing
- *
- * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-#include <asm/cacheflush.h>
-#include "cache.inc"
-
- .am33_2
-
- .globl debugger_local_cache_flushinv_one_icache
-
-###############################################################################
-#
-# void debugger_local_cache_flushinv_one(u8 *addr)
-#
-# Invalidate one particular cacheline if it's in the icache
-#
-###############################################################################
- ALIGN
- .globl debugger_local_cache_flushinv_one_icache
- .type debugger_local_cache_flushinv_one_icache,@function
-debugger_local_cache_flushinv_one_icache:
- movm [d3,a2],(sp)
-
- mov CHCTR,a2
- movhu (a2),d0
- btst CHCTR_ICEN,d0
- beq debugger_local_cache_flushinv_one_icache_end
-
- mov d0,a1
- and L1_CACHE_TAG_MASK,a1
-
- # read the tags from the tag RAM, and if they indicate a matching valid
- # cache line then we invalidate that line
- mov ICACHE_TAG(0,0),a0
- mov a1,d0
- and L1_CACHE_TAG_ENTRY,d0
- add d0,a0 # starting icache tag RAM
- # access address
-
- and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base
- or L1_CACHE_TAG_VALID,a1
- mov L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_VALID,d1
-
- LOCAL_CLI_SAVE(d3)
-
- # disable the icache
- movhu (a2),d0
- and ~CHCTR_ICEN,d0
- movhu d0,(a2)
-
- # and wait for it to calm down
- setlb
- movhu (a2),d0
- btst CHCTR_ICBUSY,d0
- lne
-
- # check all the way tags for this cache entry
- mov (a0),d0 # read the tag in the way 0 slot
- xor a1,d0
- and d1,d0
- beq debugger_local_icache_kill # jump if matched
-
- add L1_CACHE_WAYDISP,a0
- mov (a0),d0 # read the tag in the way 1 slot
- xor a1,d0
- and d1,d0
- beq debugger_local_icache_kill # jump if matched
-
- add L1_CACHE_WAYDISP,a0
- mov (a0),d0 # read the tag in the way 2 slot
- xor a1,d0
- and d1,d0
- beq debugger_local_icache_kill # jump if matched
-
- add L1_CACHE_WAYDISP,a0
- mov (a0),d0 # read the tag in the way 3 slot
- xor a1,d0
- and d1,d0
- bne debugger_local_icache_finish # jump if not matched
-
-debugger_local_icache_kill:
- mov d0,(a0) # kill the tag (D0 is 0 at this point)
-
-debugger_local_icache_finish:
- # wait for the cache to finish what it's doing
- setlb
- movhu (a2),d0
- btst CHCTR_ICBUSY,d0
- lne
-
- # and reenable it
- or CHCTR_ICEN,d0
- movhu d0,(a2)
- movhu (a2),d0
-
- # re-enable interrupts
- LOCAL_IRQ_RESTORE(d3)
-
-debugger_local_cache_flushinv_one_icache_end:
- ret [d3,a2],8
- .size debugger_local_cache_flushinv_one_icache,.-debugger_local_cache_flushinv_one_icache
-
-#ifdef CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG
- .globl debugger_local_cache_flushinv_one
- .type debugger_local_cache_flushinv_one,@function
-debugger_local_cache_flushinv_one = debugger_local_cache_flushinv_one_icache
-#endif
diff --git a/arch/mn10300/mm/cache-dbg-inv.S b/arch/mn10300/mm/cache-dbg-inv.S
deleted file mode 100644
index eba2d6dca066..000000000000
--- a/arch/mn10300/mm/cache-dbg-inv.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/* MN10300 CPU cache invalidation routines
- *
- * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-#include <asm/cacheflush.h>
-#include "cache.inc"
-
- .am33_2
-
- .globl debugger_local_cache_flushinv
-
-###############################################################################
-#
-# void debugger_local_cache_flushinv(void)
-#
-# Invalidate the entire icache
-#
-###############################################################################
- ALIGN
- .globl debugger_local_cache_flushinv
- .type debugger_local_cache_flushinv,@function
-debugger_local_cache_flushinv:
- #
- # we only need to invalidate the icache in this cache mode
- #
- mov CHCTR,a0
- movhu (a0),d0
- btst CHCTR_ICEN,d0
- beq debugger_local_cache_flushinv_end
-
- invalidate_icache 1
-
-debugger_local_cache_flushinv_end:
- ret [],0
- .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv
diff --git a/arch/mn10300/mm/cache-disabled.c b/arch/mn10300/mm/cache-disabled.c
deleted file mode 100644
index f669ea42aba6..000000000000
--- a/arch/mn10300/mm/cache-disabled.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Handle the cache being disabled
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/mm.h>
-
-/*
- * allow userspace to flush the instruction cache
- */
-asmlinkage long sys_cacheflush(unsigned long start, unsigned long end)
-{
- if (end < start)
- return -EINVAL;
- return 0;
-}
diff --git a/arch/mn10300/mm/cache-flush-by-reg.S b/arch/mn10300/mm/cache-flush-by-reg.S
deleted file mode 100644
index 1dcae0211671..000000000000
--- a/arch/mn10300/mm/cache-flush-by-reg.S
+++ /dev/null
@@ -1,308 +0,0 @@
-/* MN10300 CPU core caching routines, using indirect regs on cache controller
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-
- .am33_2
-
-#ifndef CONFIG_SMP
- .globl mn10300_dcache_flush
- .globl mn10300_dcache_flush_page
- .globl mn10300_dcache_flush_range
- .globl mn10300_dcache_flush_range2
- .globl mn10300_dcache_flush_inv
- .globl mn10300_dcache_flush_inv_page
- .globl mn10300_dcache_flush_inv_range
- .globl mn10300_dcache_flush_inv_range2
-
-mn10300_dcache_flush = mn10300_local_dcache_flush
-mn10300_dcache_flush_page = mn10300_local_dcache_flush_page
-mn10300_dcache_flush_range = mn10300_local_dcache_flush_range
-mn10300_dcache_flush_range2 = mn10300_local_dcache_flush_range2
-mn10300_dcache_flush_inv = mn10300_local_dcache_flush_inv
-mn10300_dcache_flush_inv_page = mn10300_local_dcache_flush_inv_page
-mn10300_dcache_flush_inv_range = mn10300_local_dcache_flush_inv_range
-mn10300_dcache_flush_inv_range2 = mn10300_local_dcache_flush_inv_range2
-
-#endif /* !CONFIG_SMP */
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush(void)
-# Flush the entire data cache back to RAM
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush
- .type mn10300_local_dcache_flush,@function
-mn10300_local_dcache_flush:
- movhu (CHCTR),d0
- btst CHCTR_DCEN,d0
- beq mn10300_local_dcache_flush_end
-
- mov DCPGCR,a0
-
- LOCAL_CLI_SAVE(d1)
-
- # wait for busy bit of area purge
- setlb
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
- # set mask
- clr d0
- mov d0,(DCPGMR)
-
- # area purge
- #
- # DCPGCR = DCPGCR_DCP
- #
- mov DCPGCR_DCP,d0
- mov d0,(a0)
-
- # wait for busy bit of area purge
- setlb
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
- LOCAL_IRQ_RESTORE(d1)
-
-mn10300_local_dcache_flush_end:
- ret [],0
- .size mn10300_local_dcache_flush,.-mn10300_local_dcache_flush
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush_page(unsigned long start)
-# void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end)
-# void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size)
-# Flush a range of addresses on a page in the dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush_page
- .globl mn10300_local_dcache_flush_range
- .globl mn10300_local_dcache_flush_range2
- .type mn10300_local_dcache_flush_page,@function
- .type mn10300_local_dcache_flush_range,@function
- .type mn10300_local_dcache_flush_range2,@function
-mn10300_local_dcache_flush_page:
- and ~(PAGE_SIZE-1),d0
- mov PAGE_SIZE,d1
-mn10300_local_dcache_flush_range2:
- add d0,d1
-mn10300_local_dcache_flush_range:
- movm [d2,d3,a2],(sp)
-
- movhu (CHCTR),d2
- btst CHCTR_DCEN,d2
- beq mn10300_local_dcache_flush_range_end
-
- # calculate alignsize
- #
- # alignsize = L1_CACHE_BYTES;
- # for (i = (end - start - 1) / L1_CACHE_BYTES ; i > 0; i >>= 1)
- # alignsize <<= 1;
- # d2 = alignsize;
- #
- mov L1_CACHE_BYTES,d2
- sub d0,d1,d3
- add -1,d3
- lsr L1_CACHE_SHIFT,d3
- beq 2f
-1:
- add d2,d2
- lsr 1,d3
- bne 1b
-2:
- mov d1,a1 # a1 = end
-
- LOCAL_CLI_SAVE(d3)
- mov DCPGCR,a0
-
- # wait for busy bit of area purge
- setlb
- mov (a0),d1
- btst DCPGCR_DCPGBSY,d1
- lne
-
- # determine the mask
- mov d2,d1
- add -1,d1
- not d1 # d1 = mask = ~(alignsize-1)
- mov d1,(DCPGMR)
-
- and d1,d0,a2 # a2 = mask & start
-
-dcpgloop:
- # area purge
- mov a2,d0
- or DCPGCR_DCP,d0
- mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCP
-
- # wait for busy bit of area purge
- setlb
- mov (a0),d1
- btst DCPGCR_DCPGBSY,d1
- lne
-
- # check purge of end address
- add d2,a2 # a2 += alignsize
- cmp a1,a2 # if (a2 < end) goto dcpgloop
- bns dcpgloop
-
- LOCAL_IRQ_RESTORE(d3)
-
-mn10300_local_dcache_flush_range_end:
- ret [d2,d3,a2],12
-
- .size mn10300_local_dcache_flush_page,.-mn10300_local_dcache_flush_page
- .size mn10300_local_dcache_flush_range,.-mn10300_local_dcache_flush_range
- .size mn10300_local_dcache_flush_range2,.-mn10300_local_dcache_flush_range2
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush_inv(void)
-# Flush the entire data cache and invalidate all entries
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush_inv
- .type mn10300_local_dcache_flush_inv,@function
-mn10300_local_dcache_flush_inv:
- movhu (CHCTR),d0
- btst CHCTR_DCEN,d0
- beq mn10300_local_dcache_flush_inv_end
-
- mov DCPGCR,a0
-
- LOCAL_CLI_SAVE(d1)
-
- # wait for busy bit of area purge & invalidate
- setlb
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
- # set the mask to cover everything
- clr d0
- mov d0,(DCPGMR)
-
- # area purge & invalidate
- mov DCPGCR_DCP|DCPGCR_DCI,d0
- mov d0,(a0)
-
- # wait for busy bit of area purge & invalidate
- setlb
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
- LOCAL_IRQ_RESTORE(d1)
-
-mn10300_local_dcache_flush_inv_end:
- ret [],0
- .size mn10300_local_dcache_flush_inv,.-mn10300_local_dcache_flush_inv
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush_inv_page(unsigned long start)
-# void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end)
-# void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size)
-# Flush and invalidate a range of addresses on a page in the dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush_inv_page
- .globl mn10300_local_dcache_flush_inv_range
- .globl mn10300_local_dcache_flush_inv_range2
- .type mn10300_local_dcache_flush_inv_page,@function
- .type mn10300_local_dcache_flush_inv_range,@function
- .type mn10300_local_dcache_flush_inv_range2,@function
-mn10300_local_dcache_flush_inv_page:
- and ~(PAGE_SIZE-1),d0
- mov PAGE_SIZE,d1
-mn10300_local_dcache_flush_inv_range2:
- add d0,d1
-mn10300_local_dcache_flush_inv_range:
- movm [d2,d3,a2],(sp)
-
- movhu (CHCTR),d2
- btst CHCTR_DCEN,d2
- beq mn10300_local_dcache_flush_inv_range_end
-
- # calculate alignsize
- #
- # alignsize = L1_CACHE_BYTES;
- # for (i = (end - start - 1) / L1_CACHE_BYTES; i > 0; i >>= 1)
- # alignsize <<= 1;
- # d2 = alignsize
- #
- mov L1_CACHE_BYTES,d2
- sub d0,d1,d3
- add -1,d3
- lsr L1_CACHE_SHIFT,d3
- beq 2f
-1:
- add d2,d2
- lsr 1,d3
- bne 1b
-2:
- mov d1,a1 # a1 = end
-
- LOCAL_CLI_SAVE(d3)
- mov DCPGCR,a0
-
- # wait for busy bit of area purge & invalidate
- setlb
- mov (a0),d1
- btst DCPGCR_DCPGBSY,d1
- lne
-
- # set the mask
- mov d2,d1
- add -1,d1
- not d1 # d1 = mask = ~(alignsize-1)
- mov d1,(DCPGMR)
-
- and d1,d0,a2 # a2 = mask & start
-
-dcpgivloop:
- # area purge & invalidate
- mov a2,d0
- or DCPGCR_DCP|DCPGCR_DCI,d0
- mov d0,(a0) # DCPGCR = (mask & start)|DCPGCR_DCP|DCPGCR_DCI
-
- # wait for busy bit of area purge & invalidate
- setlb
- mov (a0),d1
- btst DCPGCR_DCPGBSY,d1
- lne
-
- # check purge & invalidate of end address
- add d2,a2 # a2 += alignsize
- cmp a1,a2 # if (a2 < end) goto dcpgivloop
- bns dcpgivloop
-
- LOCAL_IRQ_RESTORE(d3)
-
-mn10300_local_dcache_flush_inv_range_end:
- ret [d2,d3,a2],12
- .size mn10300_local_dcache_flush_inv_page,.-mn10300_local_dcache_flush_inv_page
- .size mn10300_local_dcache_flush_inv_range,.-mn10300_local_dcache_flush_inv_range
- .size mn10300_local_dcache_flush_inv_range2,.-mn10300_local_dcache_flush_inv_range2
diff --git a/arch/mn10300/mm/cache-flush-by-tag.S b/arch/mn10300/mm/cache-flush-by-tag.S
deleted file mode 100644
index 1ddc06849242..000000000000
--- a/arch/mn10300/mm/cache-flush-by-tag.S
+++ /dev/null
@@ -1,250 +0,0 @@
-/* MN10300 CPU core caching routines, using direct tag flushing
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-
- .am33_2
-
-#ifndef CONFIG_SMP
- .globl mn10300_dcache_flush
- .globl mn10300_dcache_flush_page
- .globl mn10300_dcache_flush_range
- .globl mn10300_dcache_flush_range2
- .globl mn10300_dcache_flush_inv
- .globl mn10300_dcache_flush_inv_page
- .globl mn10300_dcache_flush_inv_range
- .globl mn10300_dcache_flush_inv_range2
-
-mn10300_dcache_flush = mn10300_local_dcache_flush
-mn10300_dcache_flush_page = mn10300_local_dcache_flush_page
-mn10300_dcache_flush_range = mn10300_local_dcache_flush_range
-mn10300_dcache_flush_range2 = mn10300_local_dcache_flush_range2
-mn10300_dcache_flush_inv = mn10300_local_dcache_flush_inv
-mn10300_dcache_flush_inv_page = mn10300_local_dcache_flush_inv_page
-mn10300_dcache_flush_inv_range = mn10300_local_dcache_flush_inv_range
-mn10300_dcache_flush_inv_range2 = mn10300_local_dcache_flush_inv_range2
-
-#endif /* !CONFIG_SMP */
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush(void)
-# Flush the entire data cache back to RAM
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush
- .type mn10300_local_dcache_flush,@function
-mn10300_local_dcache_flush:
- movhu (CHCTR),d0
- btst CHCTR_DCEN,d0
- beq mn10300_local_dcache_flush_end
-
- # read the addresses tagged in the cache's tag RAM and attempt to flush
- # those addresses specifically
- # - we rely on the hardware to filter out invalid tag entry addresses
- mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
- mov DCACHE_PURGE(0,0),a1 # dcache purge request address
- mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries
-
-mn10300_local_dcache_flush_loop:
- mov (a0),d0
- and L1_CACHE_TAG_MASK,d0
- or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
- # cache
- mov d0,(a1) # conditional purge
-
- add L1_CACHE_BYTES,a0
- add L1_CACHE_BYTES,a1
- add -1,d1
- bne mn10300_local_dcache_flush_loop
-
-mn10300_local_dcache_flush_end:
- ret [],0
- .size mn10300_local_dcache_flush,.-mn10300_local_dcache_flush
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush_page(unsigned long start)
-# void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end)
-# void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size)
-# Flush a range of addresses on a page in the dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush_page
- .globl mn10300_local_dcache_flush_range
- .globl mn10300_local_dcache_flush_range2
- .type mn10300_local_dcache_flush_page,@function
- .type mn10300_local_dcache_flush_range,@function
- .type mn10300_local_dcache_flush_range2,@function
-mn10300_local_dcache_flush_page:
- and ~(PAGE_SIZE-1),d0
- mov PAGE_SIZE,d1
-mn10300_local_dcache_flush_range2:
- add d0,d1
-mn10300_local_dcache_flush_range:
- movm [d2],(sp)
-
- movhu (CHCTR),d2
- btst CHCTR_DCEN,d2
- beq mn10300_local_dcache_flush_range_end
-
- sub d0,d1,a0
- cmp MN10300_DCACHE_FLUSH_BORDER,a0
- ble 1f
-
- movm (sp),[d2]
- bra mn10300_local_dcache_flush
-1:
-
- # round start addr down
- and L1_CACHE_TAG_MASK,d0
- mov d0,a1
-
- add L1_CACHE_BYTES,d1 # round end addr up
- and L1_CACHE_TAG_MASK,d1
-
- # write a request to flush all instances of an address from the cache
- mov DCACHE_PURGE(0,0),a0
- mov a1,d0
- and L1_CACHE_TAG_ENTRY,d0
- add d0,a0 # starting dcache purge control
- # reg address
-
- sub a1,d1
- lsr L1_CACHE_SHIFT,d1 # total number of entries to
- # examine
-
- or L1_CACHE_TAG_VALID,a1 # retain valid entries in the
- # cache
-
-mn10300_local_dcache_flush_range_loop:
- mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line
- # all ways
-
- add L1_CACHE_BYTES,a0
- add L1_CACHE_BYTES,a1
- and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0
- add -1,d1
- bne mn10300_local_dcache_flush_range_loop
-
-mn10300_local_dcache_flush_range_end:
- ret [d2],4
-
- .size mn10300_local_dcache_flush_page,.-mn10300_local_dcache_flush_page
- .size mn10300_local_dcache_flush_range,.-mn10300_local_dcache_flush_range
- .size mn10300_local_dcache_flush_range2,.-mn10300_local_dcache_flush_range2
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush_inv(void)
-# Flush the entire data cache and invalidate all entries
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush_inv
- .type mn10300_local_dcache_flush_inv,@function
-mn10300_local_dcache_flush_inv:
- movhu (CHCTR),d0
- btst CHCTR_DCEN,d0
- beq mn10300_local_dcache_flush_inv_end
-
- mov L1_CACHE_NENTRIES,d1
- clr a1
-
-mn10300_local_dcache_flush_inv_loop:
- mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge
- mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge
- mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge
- mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
-
- add L1_CACHE_BYTES,a1
- add -1,d1
- bne mn10300_local_dcache_flush_inv_loop
-
-mn10300_local_dcache_flush_inv_end:
- ret [],0
- .size mn10300_local_dcache_flush_inv,.-mn10300_local_dcache_flush_inv
-
-###############################################################################
-#
-# void mn10300_local_dcache_flush_inv_page(unsigned long start)
-# void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end)
-# void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size)
-# Flush and invalidate a range of addresses on a page in the dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_flush_inv_page
- .globl mn10300_local_dcache_flush_inv_range
- .globl mn10300_local_dcache_flush_inv_range2
- .type mn10300_local_dcache_flush_inv_page,@function
- .type mn10300_local_dcache_flush_inv_range,@function
- .type mn10300_local_dcache_flush_inv_range2,@function
-mn10300_local_dcache_flush_inv_page:
- and ~(PAGE_SIZE-1),d0
- mov PAGE_SIZE,d1
-mn10300_local_dcache_flush_inv_range2:
- add d0,d1
-mn10300_local_dcache_flush_inv_range:
- movm [d2],(sp)
-
- movhu (CHCTR),d2
- btst CHCTR_DCEN,d2
- beq mn10300_local_dcache_flush_inv_range_end
-
- sub d0,d1,a0
- cmp MN10300_DCACHE_FLUSH_INV_BORDER,a0
- ble 1f
-
- movm (sp),[d2]
- bra mn10300_local_dcache_flush_inv
-1:
-
- and L1_CACHE_TAG_MASK,d0 # round start addr down
- mov d0,a1
-
- add L1_CACHE_BYTES,d1 # round end addr up
- and L1_CACHE_TAG_MASK,d1
-
- # write a request to flush and invalidate all instances of an address
- # from the cache
- mov DCACHE_PURGE(0,0),a0
- mov a1,d0
- and L1_CACHE_TAG_ENTRY,d0
- add d0,a0 # starting dcache purge control
- # reg address
-
- sub a1,d1
- lsr L1_CACHE_SHIFT,d1 # total number of entries to
- # examine
-
-mn10300_local_dcache_flush_inv_range_loop:
- mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line
- # in all ways
-
- add L1_CACHE_BYTES,a0
- add L1_CACHE_BYTES,a1
- and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0
- add -1,d1
- bne mn10300_local_dcache_flush_inv_range_loop
-
-mn10300_local_dcache_flush_inv_range_end:
- ret [d2],4
- .size mn10300_local_dcache_flush_inv_page,.-mn10300_local_dcache_flush_inv_page
- .size mn10300_local_dcache_flush_inv_range,.-mn10300_local_dcache_flush_inv_range
- .size mn10300_local_dcache_flush_inv_range2,.-mn10300_local_dcache_flush_inv_range2
diff --git a/arch/mn10300/mm/cache-flush-icache.c b/arch/mn10300/mm/cache-flush-icache.c
deleted file mode 100644
index fdb1a9db20f0..000000000000
--- a/arch/mn10300/mm/cache-flush-icache.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Flush dcache and invalidate icache when the dcache is in writeback mode
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <asm/cacheflush.h>
-#include <asm/smp.h>
-#include "cache-smp.h"
-
-/**
- * flush_icache_page - Flush a page from the dcache and invalidate the icache
- * @vma: The VMA the page is part of.
- * @page: The page to be flushed.
- *
- * Write a page back from the dcache and invalidate the icache so that we can
- * run code from it that we've just written into it
- */
-void flush_icache_page(struct vm_area_struct *vma, struct page *page)
-{
- unsigned long start = page_to_phys(page);
- unsigned long flags;
-
- flags = smp_lock_cache();
-
- mn10300_local_dcache_flush_page(start);
- mn10300_local_icache_inv_page(start);
-
- smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, start + PAGE_SIZE);
- smp_unlock_cache(flags);
-}
-EXPORT_SYMBOL(flush_icache_page);
-
-/**
- * flush_icache_page_range - Flush dcache and invalidate icache for part of a
- * single page
- * @start: The starting virtual address of the page part.
- * @end: The ending virtual address of the page part.
- *
- * Flush the dcache and invalidate the icache for part of a single page, as
- * determined by the virtual addresses given. The page must be in the paged
- * area.
- */
-static void flush_icache_page_range(unsigned long start, unsigned long end)
-{
- unsigned long addr, size, off;
- struct page *page;
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *ppte, pte;
-
- /* work out how much of the page to flush */
- off = start & ~PAGE_MASK;
- size = end - start;
-
- /* get the physical address the page is mapped to from the page
- * tables */
- pgd = pgd_offset(current->mm, start);
- if (!pgd || !pgd_val(*pgd))
- return;
-
- pud = pud_offset(pgd, start);
- if (!pud || !pud_val(*pud))
- return;
-
- pmd = pmd_offset(pud, start);
- if (!pmd || !pmd_val(*pmd))
- return;
-
- ppte = pte_offset_map(pmd, start);
- if (!ppte)
- return;
- pte = *ppte;
- pte_unmap(ppte);
-
- if (pte_none(pte))
- return;
-
- page = pte_page(pte);
- if (!page)
- return;
-
- addr = page_to_phys(page);
-
- /* flush the dcache and invalidate the icache coverage on that
- * region */
- mn10300_local_dcache_flush_range2(addr + off, size);
- mn10300_local_icache_inv_range2(addr + off, size);
- smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, end);
-}
-
-/**
- * flush_icache_range - Globally flush dcache and invalidate icache for region
- * @start: The starting virtual address of the region.
- * @end: The ending virtual address of the region.
- *
- * This is used by the kernel to globally flush some code it has just written
- * from the dcache back to RAM and then to globally invalidate the icache over
- * that region so that that code can be run on all CPUs in the system.
- */
-void flush_icache_range(unsigned long start, unsigned long end)
-{
- unsigned long start_page, end_page;
- unsigned long flags;
-
- flags = smp_lock_cache();
-
- if (end > 0x80000000UL) {
- /* addresses above 0xa0000000 do not go through the cache */
- if (end > 0xa0000000UL) {
- end = 0xa0000000UL;
- if (start >= end)
- goto done;
- }
-
- /* kernel addresses between 0x80000000 and 0x9fffffff do not
- * require page tables, so we just map such addresses
- * directly */
- start_page = (start >= 0x80000000UL) ? start : 0x80000000UL;
- mn10300_local_dcache_flush_range(start_page, end);
- mn10300_local_icache_inv_range(start_page, end);
- smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start_page, end);
- if (start_page == start)
- goto done;
- end = start_page;
- }
-
- start_page = start & PAGE_MASK;
- end_page = (end - 1) & PAGE_MASK;
-
- if (start_page == end_page) {
- /* the first and last bytes are on the same page */
- flush_icache_page_range(start, end);
- } else if (start_page + 1 == end_page) {
- /* split over two virtually contiguous pages */
- flush_icache_page_range(start, end_page);
- flush_icache_page_range(end_page, end);
- } else {
- /* more than 2 pages; just flush the entire cache */
- mn10300_dcache_flush();
- mn10300_icache_inv();
- smp_cache_call(SMP_IDCACHE_INV_FLUSH, 0, 0);
- }
-
-done:
- smp_unlock_cache(flags);
-}
-EXPORT_SYMBOL(flush_icache_range);
diff --git a/arch/mn10300/mm/cache-inv-by-reg.S b/arch/mn10300/mm/cache-inv-by-reg.S
deleted file mode 100644
index a60825b91e77..000000000000
--- a/arch/mn10300/mm/cache-inv-by-reg.S
+++ /dev/null
@@ -1,350 +0,0 @@
-/* MN10300 CPU cache invalidation routines, using automatic purge registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-#include <asm/cacheflush.h>
-#include "cache.inc"
-
-#define mn10300_local_dcache_inv_range_intr_interval \
- +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1)
-
-#if mn10300_local_dcache_inv_range_intr_interval > 0xff
-#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less
-#endif
-
- .am33_2
-
-#ifndef CONFIG_SMP
- .globl mn10300_icache_inv
- .globl mn10300_icache_inv_page
- .globl mn10300_icache_inv_range
- .globl mn10300_icache_inv_range2
- .globl mn10300_dcache_inv
- .globl mn10300_dcache_inv_page
- .globl mn10300_dcache_inv_range
- .globl mn10300_dcache_inv_range2
-
-mn10300_icache_inv = mn10300_local_icache_inv
-mn10300_icache_inv_page = mn10300_local_icache_inv_page
-mn10300_icache_inv_range = mn10300_local_icache_inv_range
-mn10300_icache_inv_range2 = mn10300_local_icache_inv_range2
-mn10300_dcache_inv = mn10300_local_dcache_inv
-mn10300_dcache_inv_page = mn10300_local_dcache_inv_page
-mn10300_dcache_inv_range = mn10300_local_dcache_inv_range
-mn10300_dcache_inv_range2 = mn10300_local_dcache_inv_range2
-
-#endif /* !CONFIG_SMP */
-
-###############################################################################
-#
-# void mn10300_local_icache_inv(void)
-# Invalidate the entire icache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_icache_inv
- .type mn10300_local_icache_inv,@function
-mn10300_local_icache_inv:
- mov CHCTR,a0
-
- movhu (a0),d0
- btst CHCTR_ICEN,d0
- beq mn10300_local_icache_inv_end
-
- invalidate_icache 1
-
-mn10300_local_icache_inv_end:
- ret [],0
- .size mn10300_local_icache_inv,.-mn10300_local_icache_inv
-
-###############################################################################
-#
-# void mn10300_local_dcache_inv(void)
-# Invalidate the entire dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_inv
- .type mn10300_local_dcache_inv,@function
-mn10300_local_dcache_inv:
- mov CHCTR,a0
-
- movhu (a0),d0
- btst CHCTR_DCEN,d0
- beq mn10300_local_dcache_inv_end
-
- invalidate_dcache 1
-
-mn10300_local_dcache_inv_end:
- ret [],0
- .size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv
-
-###############################################################################
-#
-# void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end)
-# void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size)
-# void mn10300_local_dcache_inv_page(unsigned long start)
-# Invalidate a range of addresses on a page in the dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_inv_page
- .globl mn10300_local_dcache_inv_range
- .globl mn10300_local_dcache_inv_range2
- .type mn10300_local_dcache_inv_page,@function
- .type mn10300_local_dcache_inv_range,@function
- .type mn10300_local_dcache_inv_range2,@function
-mn10300_local_dcache_inv_page:
- and ~(PAGE_SIZE-1),d0
- mov PAGE_SIZE,d1
-mn10300_local_dcache_inv_range2:
- add d0,d1
-mn10300_local_dcache_inv_range:
- # If we are in writeback mode we check the start and end alignments,
- # and if they're not cacheline-aligned, we must flush any bits outside
- # the range that share cachelines with stuff inside the range
-#ifdef CONFIG_MN10300_CACHE_WBACK
- btst ~L1_CACHE_TAG_MASK,d0
- bne 1f
- btst ~L1_CACHE_TAG_MASK,d1
- beq 2f
-1:
- bra mn10300_local_dcache_flush_inv_range
-2:
-#endif /* CONFIG_MN10300_CACHE_WBACK */
-
- movm [d2,d3,a2],(sp)
-
- mov CHCTR,a0
- movhu (a0),d2
- btst CHCTR_DCEN,d2
- beq mn10300_local_dcache_inv_range_end
-
- # round the addresses out to be full cachelines, unless we're in
- # writeback mode, in which case we would be in flush and invalidate by
- # now
-#ifndef CONFIG_MN10300_CACHE_WBACK
- and L1_CACHE_TAG_MASK,d0 # round start addr down
-
- mov L1_CACHE_BYTES-1,d2
- add d2,d1
- and L1_CACHE_TAG_MASK,d1 # round end addr up
-#endif /* !CONFIG_MN10300_CACHE_WBACK */
-
- sub d0,d1,d2 # calculate the total size
- mov d0,a2 # A2 = start address
- mov d1,a1 # A1 = end address
-
- LOCAL_CLI_SAVE(d3)
-
- mov DCPGCR,a0 # make sure the purger isn't busy
- setlb
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
- # skip initial address alignment calculation if address is zero
- mov d2,d1
- cmp 0,a2
- beq 1f
-
-dcivloop:
- /* calculate alignsize
- *
- * alignsize = L1_CACHE_BYTES;
- * while (! start & alignsize) {
- * alignsize <<=1;
- * }
- * d1 = alignsize;
- */
- mov L1_CACHE_BYTES,d1
- lsr 1,d1
- setlb
- add d1,d1
- mov d1,d0
- and a2,d0
- leq
-
-1:
- /* calculate invsize
- *
- * if (totalsize > alignsize) {
- * invsize = alignsize;
- * } else {
- * invsize = totalsize;
- * tmp = 0x80000000;
- * while (! invsize & tmp) {
- * tmp >>= 1;
- * }
- * invsize = tmp;
- * }
- * d1 = invsize
- */
- cmp d2,d1
- bns 2f
- mov d2,d1
-
- mov 0x80000000,d0 # start from 31bit=1
- setlb
- lsr 1,d0
- mov d0,e0
- and d1,e0
- leq
- mov d0,d1
-
-2:
- /* set mask
- *
- * mask = ~(invsize-1);
- * DCPGMR = mask;
- */
- mov d1,d0
- add -1,d0
- not d0
- mov d0,(DCPGMR)
-
- # invalidate area
- mov a2,d0
- or DCPGCR_DCI,d0
- mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCI
-
- setlb # wait for the purge to complete
- mov (a0),d0
- btst DCPGCR_DCPGBSY,d0
- lne
-
- sub d1,d2 # decrease size remaining
- add d1,a2 # increase next start address
-
- /* check invalidating of end address
- *
- * a2 = a2 + invsize
- * if (a2 < end) {
- * goto dcivloop;
- * } */
- cmp a1,a2
- bns dcivloop
-
- LOCAL_IRQ_RESTORE(d3)
-
-mn10300_local_dcache_inv_range_end:
- ret [d2,d3,a2],12
- .size mn10300_local_dcache_inv_page,.-mn10300_local_dcache_inv_page
- .size mn10300_local_dcache_inv_range,.-mn10300_local_dcache_inv_range
- .size mn10300_local_dcache_inv_range2,.-mn10300_local_dcache_inv_range2
-
-###############################################################################
-#
-# void mn10300_local_icache_inv_page(unsigned long start)
-# void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size)
-# void mn10300_local_icache_inv_range(unsigned long start, unsigned long end)
-# Invalidate a range of addresses on a page in the icache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_icache_inv_page
- .globl mn10300_local_icache_inv_range
- .globl mn10300_local_icache_inv_range2
- .type mn10300_local_icache_inv_page,@function
- .type mn10300_local_icache_inv_range,@function
- .type mn10300_local_icache_inv_range2,@function
-mn10300_local_icache_inv_page:
- and ~(PAGE_SIZE-1),d0
- mov PAGE_SIZE,d1
-mn10300_local_icache_inv_range2:
- add d0,d1
-mn10300_local_icache_inv_range:
- movm [d2,d3,a2],(sp)
-
- mov CHCTR,a0
- movhu (a0),d2
- btst CHCTR_ICEN,d2
- beq mn10300_local_icache_inv_range_reg_end
-
- /* calculate alignsize
- *
- * alignsize = L1_CACHE_BYTES;
- * for (i = (end - start - 1) / L1_CACHE_BYTES ; i > 0; i >>= 1) {
- * alignsize <<= 1;
- * }
- * d2 = alignsize;
- */
- mov L1_CACHE_BYTES,d2
- sub d0,d1,d3
- add -1,d3
- lsr L1_CACHE_SHIFT,d3
- beq 2f
-1:
- add d2,d2
- lsr 1,d3
- bne 1b
-2:
-
- /* a1 = end */
- mov d1,a1
-
- LOCAL_CLI_SAVE(d3)
-
- mov ICIVCR,a0
- /* wait for busy bit of area invalidation */
- setlb
- mov (a0),d1
- btst ICIVCR_ICIVBSY,d1
- lne
-
- /* set mask
- *
- * mask = ~(alignsize-1);
- * ICIVMR = mask;
- */
- mov d2,d1
- add -1,d1
- not d1
- mov d1,(ICIVMR)
- /* a2 = mask & start */
- and d1,d0,a2
-
-icivloop:
- /* area invalidate
- *
- * ICIVCR = (mask & start) | ICIVCR_ICI
- */
- mov a2,d0
- or ICIVCR_ICI,d0
- mov d0,(a0)
-
- /* wait for busy bit of area invalidation */
- setlb
- mov (a0),d1
- btst ICIVCR_ICIVBSY,d1
- lne
-
- /* check invalidating of end address
- *
- * a2 = a2 + alignsize
- * if (a2 < end) {
- * goto icivloop;
- * } */
- add d2,a2
- cmp a1,a2
- bns icivloop
-
- LOCAL_IRQ_RESTORE(d3)
-
-mn10300_local_icache_inv_range_reg_end:
- ret [d2,d3,a2],12
- .size mn10300_local_icache_inv_page,.-mn10300_local_icache_inv_page
- .size mn10300_local_icache_inv_range,.-mn10300_local_icache_inv_range
- .size mn10300_local_icache_inv_range2,.-mn10300_local_icache_inv_range2
diff --git a/arch/mn10300/mm/cache-inv-by-tag.S b/arch/mn10300/mm/cache-inv-by-tag.S
deleted file mode 100644
index ccedce9c144d..000000000000
--- a/arch/mn10300/mm/cache-inv-by-tag.S
+++ /dev/null
@@ -1,276 +0,0 @@
-/* MN10300 CPU core caching routines
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/irqflags.h>
-#include <asm/cacheflush.h>
-#include "cache.inc"
-
-#define mn10300_local_dcache_inv_range_intr_interval \
- +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1)
-
-#if mn10300_local_dcache_inv_range_intr_interval > 0xff
-#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less
-#endif
-
- .am33_2
-
- .globl mn10300_local_icache_inv_page
- .globl mn10300_local_icache_inv_range
- .globl mn10300_local_icache_inv_range2
-
-mn10300_local_icache_inv_page = mn10300_local_icache_inv
-mn10300_local_icache_inv_range = mn10300_local_icache_inv
-mn10300_local_icache_inv_range2 = mn10300_local_icache_inv
-
-#ifndef CONFIG_SMP
- .globl mn10300_icache_inv
- .globl mn10300_icache_inv_page
- .globl mn10300_icache_inv_range
- .globl mn10300_icache_inv_range2
- .globl mn10300_dcache_inv
- .globl mn10300_dcache_inv_page
- .globl mn10300_dcache_inv_range
- .globl mn10300_dcache_inv_range2
-
-mn10300_icache_inv = mn10300_local_icache_inv
-mn10300_icache_inv_page = mn10300_local_icache_inv_page
-mn10300_icache_inv_range = mn10300_local_icache_inv_range
-mn10300_icache_inv_range2 = mn10300_local_icache_inv_range2
-mn10300_dcache_inv = mn10300_local_dcache_inv
-mn10300_dcache_inv_page = mn10300_local_dcache_inv_page
-mn10300_dcache_inv_range = mn10300_local_dcache_inv_range
-mn10300_dcache_inv_range2 = mn10300_local_dcache_inv_range2
-
-#endif /* !CONFIG_SMP */
-
-###############################################################################
-#
-# void mn10300_local_icache_inv(void)
-# Invalidate the entire icache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_icache_inv
- .type mn10300_local_icache_inv,@function
-mn10300_local_icache_inv:
- mov CHCTR,a0
-
- movhu (a0),d0
- btst CHCTR_ICEN,d0
- beq mn10300_local_icache_inv_end
-
- invalidate_icache 1
-
-mn10300_local_icache_inv_end:
- ret [],0
- .size mn10300_local_icache_inv,.-mn10300_local_icache_inv
-
-###############################################################################
-#
-# void mn10300_local_dcache_inv(void)
-# Invalidate the entire dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_inv
- .type mn10300_local_dcache_inv,@function
-mn10300_local_dcache_inv:
- mov CHCTR,a0
-
- movhu (a0),d0
- btst CHCTR_DCEN,d0
- beq mn10300_local_dcache_inv_end
-
- invalidate_dcache 1
-
-mn10300_local_dcache_inv_end:
- ret [],0
- .size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv
-
-###############################################################################
-#
-# void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end)
-# void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size)
-# void mn10300_local_dcache_inv_page(unsigned long start)
-# Invalidate a range of addresses on a page in the dcache
-#
-###############################################################################
- ALIGN
- .globl mn10300_local_dcache_inv_page
- .globl mn10300_local_dcache_inv_range
- .globl mn10300_local_dcache_inv_range2
- .type mn10300_local_dcache_inv_page,@function
- .type mn10300_local_dcache_inv_range,@function
- .type mn10300_local_dcache_inv_range2,@function
-mn10300_local_dcache_inv_page:
- and ~(PAGE_SIZE-1),d0
- mov PAGE_SIZE,d1
-mn10300_local_dcache_inv_range2:
- add d0,d1
-mn10300_local_dcache_inv_range:
- # If we are in writeback mode we check the start and end alignments,
- # and if they're not cacheline-aligned, we must flush any bits outside
- # the range that share cachelines with stuff inside the range
-#ifdef CONFIG_MN10300_CACHE_WBACK
- btst ~L1_CACHE_TAG_MASK,d0
- bne 1f
- btst ~L1_CACHE_TAG_MASK,d1
- beq 2f
-1:
- bra mn10300_local_dcache_flush_inv_range
-2:
-#endif /* CONFIG_MN10300_CACHE_WBACK */
-
- movm [d2,d3,a2],(sp)
-
- mov CHCTR,a2
- movhu (a2),d2
- btst CHCTR_DCEN,d2
- beq mn10300_local_dcache_inv_range_end
-
-#ifndef CONFIG_MN10300_CACHE_WBACK
- and L1_CACHE_TAG_MASK,d0 # round start addr down
-
- add L1_CACHE_BYTES,d1 # round end addr up
- and L1_CACHE_TAG_MASK,d1
-#endif /* !CONFIG_MN10300_CACHE_WBACK */
- mov d0,a1
-
- clr d2 # we're going to clear tag RAM
- # entries
-
- # read the tags from the tag RAM, and if they indicate a valid dirty
- # cache line then invalidate that line
- mov DCACHE_TAG(0,0),a0
- mov a1,d0
- and L1_CACHE_TAG_ENTRY,d0
- add d0,a0 # starting dcache tag RAM
- # access address
-
- sub a1,d1
- lsr L1_CACHE_SHIFT,d1 # total number of entries to
- # examine
-
- and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base
-
-mn10300_local_dcache_inv_range_outer_loop:
- LOCAL_CLI_SAVE(d3)
-
- # disable the dcache
- movhu (a2),d0
- and ~CHCTR_DCEN,d0
- movhu d0,(a2)
-
- # and wait for it to calm down
- setlb
- movhu (a2),d0
- btst CHCTR_DCBUSY,d0
- lne
-
-mn10300_local_dcache_inv_range_loop:
-
- # process the way 0 slot
- mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot
- btst L1_CACHE_TAG_VALID,d0
- beq mn10300_local_dcache_inv_range_skip_0 # jump if this cacheline
- # is not valid
-
- xor a1,d0
- lsr 12,d0
- bne mn10300_local_dcache_inv_range_skip_0 # jump if not this cacheline
-
- mov d2,(L1_CACHE_WAYDISP*0,a0) # kill the tag
-
-mn10300_local_dcache_inv_range_skip_0:
-
- # process the way 1 slot
- mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot
- btst L1_CACHE_TAG_VALID,d0
- beq mn10300_local_dcache_inv_range_skip_1 # jump if this cacheline
- # is not valid
-
- xor a1,d0
- lsr 12,d0
- bne mn10300_local_dcache_inv_range_skip_1 # jump if not this cacheline
-
- mov d2,(L1_CACHE_WAYDISP*1,a0) # kill the tag
-
-mn10300_local_dcache_inv_range_skip_1:
-
- # process the way 2 slot
- mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot
- btst L1_CACHE_TAG_VALID,d0
- beq mn10300_local_dcache_inv_range_skip_2 # jump if this cacheline
- # is not valid
-
- xor a1,d0
- lsr 12,d0
- bne mn10300_local_dcache_inv_range_skip_2 # jump if not this cacheline
-
- mov d2,(L1_CACHE_WAYDISP*2,a0) # kill the tag
-
-mn10300_local_dcache_inv_range_skip_2:
-
- # process the way 3 slot
- mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot
- btst L1_CACHE_TAG_VALID,d0
- beq mn10300_local_dcache_inv_range_skip_3 # jump if this cacheline
- # is not valid
-
- xor a1,d0
- lsr 12,d0
- bne mn10300_local_dcache_inv_range_skip_3 # jump if not this cacheline
-
- mov d2,(L1_CACHE_WAYDISP*3,a0) # kill the tag
-
-mn10300_local_dcache_inv_range_skip_3:
-
- # approx every N steps we re-enable the cache and see if there are any
- # interrupts to be processed
- # we also break out if we've reached the end of the loop
- # (the bottom nibble of the count is zero in both cases)
- add L1_CACHE_BYTES,a0
- add L1_CACHE_BYTES,a1
- and ~L1_CACHE_WAYDISP,a0
- add -1,d1
- btst mn10300_local_dcache_inv_range_intr_interval,d1
- bne mn10300_local_dcache_inv_range_loop
-
- # wait for the cache to finish what it's doing
- setlb
- movhu (a2),d0
- btst CHCTR_DCBUSY,d0
- lne
-
- # and reenable it
- or CHCTR_DCEN,d0
- movhu d0,(a2)
- movhu (a2),d0
-
- # re-enable interrupts
- # - we don't bother with delay NOPs as we'll have enough instructions
- # before we disable interrupts again to give the interrupts a chance
- # to happen
- LOCAL_IRQ_RESTORE(d3)
-
- # go around again if the counter hasn't yet reached zero
- add 0,d1
- bne mn10300_local_dcache_inv_range_outer_loop
-
-mn10300_local_dcache_inv_range_end:
- ret [d2,d3,a2],12
- .size mn10300_local_dcache_inv_page,.-mn10300_local_dcache_inv_page
- .size mn10300_local_dcache_inv_range,.-mn10300_local_dcache_inv_range
- .size mn10300_local_dcache_inv_range2,.-mn10300_local_dcache_inv_range2
diff --git a/arch/mn10300/mm/cache-inv-icache.c b/arch/mn10300/mm/cache-inv-icache.c
deleted file mode 100644
index a6b63dde603d..000000000000
--- a/arch/mn10300/mm/cache-inv-icache.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Invalidate icache when dcache doesn't need invalidation as it's in
- * write-through mode
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <asm/cacheflush.h>
-#include <asm/smp.h>
-#include "cache-smp.h"
-
-/**
- * flush_icache_page_range - Flush dcache and invalidate icache for part of a
- * single page
- * @start: The starting virtual address of the page part.
- * @end: The ending virtual address of the page part.
- *
- * Invalidate the icache for part of a single page, as determined by the
- * virtual addresses given. The page must be in the paged area. The dcache is
- * not flushed as the cache must be in write-through mode to get here.
- */
-static void flush_icache_page_range(unsigned long start, unsigned long end)
-{
- unsigned long addr, size, off;
- struct page *page;
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *ppte, pte;
-
- /* work out how much of the page to flush */
- off = start & ~PAGE_MASK;
- size = end - start;
-
- /* get the physical address the page is mapped to from the page
- * tables */
- pgd = pgd_offset(current->mm, start);
- if (!pgd || !pgd_val(*pgd))
- return;
-
- pud = pud_offset(pgd, start);
- if (!pud || !pud_val(*pud))
- return;
-
- pmd = pmd_offset(pud, start);
- if (!pmd || !pmd_val(*pmd))
- return;
-
- ppte = pte_offset_map(pmd, start);
- if (!ppte)
- return;
- pte = *ppte;
- pte_unmap(ppte);
-
- if (pte_none(pte))
- return;
-
- page = pte_page(pte);
- if (!page)
- return;
-
- addr = page_to_phys(page);
-
- /* invalidate the icache coverage on that region */
- mn10300_local_icache_inv_range2(addr + off, size);
- smp_cache_call(SMP_ICACHE_INV_RANGE, start, end);
-}
-
-/**
- * flush_icache_range - Globally flush dcache and invalidate icache for region
- * @start: The starting virtual address of the region.
- * @end: The ending virtual address of the region.
- *
- * This is used by the kernel to globally flush some code it has just written
- * from the dcache back to RAM and then to globally invalidate the icache over
- * that region so that that code can be run on all CPUs in the system.
- */
-void flush_icache_range(unsigned long start, unsigned long end)
-{
- unsigned long start_page, end_page;
- unsigned long flags;
-
- flags = smp_lock_cache();
-
- if (end > 0x80000000UL) {
- /* addresses above 0xa0000000 do not go through the cache */
- if (end > 0xa0000000UL) {
- end = 0xa0000000UL;
- if (start >= end)
- goto done;
- }
-
- /* kernel addresses between 0x80000000 and 0x9fffffff do not
- * require page tables, so we just map such addresses
- * directly */
- start_page = (start >= 0x80000000UL) ? start : 0x80000000UL;
- mn10300_icache_inv_range(start_page, end);
- smp_cache_call(SMP_ICACHE_INV_RANGE, start, end);
- if (start_page == start)
- goto done;
- end = start_page;
- }
-
- start_page = start & PAGE_MASK;
- end_page = (end - 1) & PAGE_MASK;
-
- if (start_page == end_page) {
- /* the first and last bytes are on the same page */
- flush_icache_page_range(start, end);
- } else if (start_page + 1 == end_page) {
- /* split over two virtually contiguous pages */
- flush_icache_page_range(start, end_page);
- flush_icache_page_range(end_page, end);
- } else {
- /* more than 2 pages; just flush the entire cache */
- mn10300_local_icache_inv();
- smp_cache_call(SMP_ICACHE_INV, 0, 0);
- }
-
-done:
- smp_unlock_cache(flags);
-}
-EXPORT_SYMBOL(flush_icache_range);
diff --git a/arch/mn10300/mm/cache-smp-flush.c b/arch/mn10300/mm/cache-smp-flush.c
deleted file mode 100644
index fd51af5eaf70..000000000000
--- a/arch/mn10300/mm/cache-smp-flush.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Functions for global dcache flush when writeback caching in SMP
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/mm.h>
-#include <asm/cacheflush.h>
-#include "cache-smp.h"
-
-/**
- * mn10300_dcache_flush - Globally flush data cache
- *
- * Flush the data cache on all CPUs.
- */
-void mn10300_dcache_flush(void)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush();
- smp_cache_call(SMP_DCACHE_FLUSH, 0, 0);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_flush_page - Globally flush a page of data cache
- * @start: The address of the page of memory to be flushed.
- *
- * Flush a range of addresses in the data cache on all CPUs covering
- * the page that includes the given address.
- */
-void mn10300_dcache_flush_page(unsigned long start)
-{
- unsigned long flags;
-
- start &= ~(PAGE_SIZE-1);
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush_page(start);
- smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, start + PAGE_SIZE);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_flush_range - Globally flush range of data cache
- * @start: The start address of the region to be flushed.
- * @end: The end address of the region to be flushed.
- *
- * Flush a range of addresses in the data cache on all CPUs, between start and
- * end-1 inclusive.
- */
-void mn10300_dcache_flush_range(unsigned long start, unsigned long end)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush_range(start, end);
- smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, end);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_flush_range2 - Globally flush range of data cache
- * @start: The start address of the region to be flushed.
- * @size: The size of the region to be flushed.
- *
- * Flush a range of addresses in the data cache on all CPUs, between start and
- * start+size-1 inclusive.
- */
-void mn10300_dcache_flush_range2(unsigned long start, unsigned long size)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush_range2(start, size);
- smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, start + size);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_flush_inv - Globally flush and invalidate data cache
- *
- * Flush and invalidate the data cache on all CPUs.
- */
-void mn10300_dcache_flush_inv(void)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush_inv();
- smp_cache_call(SMP_DCACHE_FLUSH_INV, 0, 0);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_flush_inv_page - Globally flush and invalidate a page of data
- * cache
- * @start: The address of the page of memory to be flushed and invalidated.
- *
- * Flush and invalidate a range of addresses in the data cache on all CPUs
- * covering the page that includes the given address.
- */
-void mn10300_dcache_flush_inv_page(unsigned long start)
-{
- unsigned long flags;
-
- start &= ~(PAGE_SIZE-1);
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush_inv_page(start);
- smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, start + PAGE_SIZE);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_flush_inv_range - Globally flush and invalidate range of data
- * cache
- * @start: The start address of the region to be flushed and invalidated.
- * @end: The end address of the region to be flushed and invalidated.
- *
- * Flush and invalidate a range of addresses in the data cache on all CPUs,
- * between start and end-1 inclusive.
- */
-void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush_inv_range(start, end);
- smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, end);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_flush_inv_range2 - Globally flush and invalidate range of data
- * cache
- * @start: The start address of the region to be flushed and invalidated.
- * @size: The size of the region to be flushed and invalidated.
- *
- * Flush and invalidate a range of addresses in the data cache on all CPUs,
- * between start and start+size-1 inclusive.
- */
-void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_flush_inv_range2(start, size);
- smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, start + size);
- smp_unlock_cache(flags);
-}
diff --git a/arch/mn10300/mm/cache-smp-inv.c b/arch/mn10300/mm/cache-smp-inv.c
deleted file mode 100644
index ff1787358c8e..000000000000
--- a/arch/mn10300/mm/cache-smp-inv.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Functions for global i/dcache invalidation when caching in SMP
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/mm.h>
-#include <asm/cacheflush.h>
-#include "cache-smp.h"
-
-/**
- * mn10300_icache_inv - Globally invalidate instruction cache
- *
- * Invalidate the instruction cache on all CPUs.
- */
-void mn10300_icache_inv(void)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_icache_inv();
- smp_cache_call(SMP_ICACHE_INV, 0, 0);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_icache_inv_page - Globally invalidate a page of instruction cache
- * @start: The address of the page of memory to be invalidated.
- *
- * Invalidate a range of addresses in the instruction cache on all CPUs
- * covering the page that includes the given address.
- */
-void mn10300_icache_inv_page(unsigned long start)
-{
- unsigned long flags;
-
- start &= ~(PAGE_SIZE-1);
-
- flags = smp_lock_cache();
- mn10300_local_icache_inv_page(start);
- smp_cache_call(SMP_ICACHE_INV_RANGE, start, start + PAGE_SIZE);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_icache_inv_range - Globally invalidate range of instruction cache
- * @start: The start address of the region to be invalidated.
- * @end: The end address of the region to be invalidated.
- *
- * Invalidate a range of addresses in the instruction cache on all CPUs,
- * between start and end-1 inclusive.
- */
-void mn10300_icache_inv_range(unsigned long start, unsigned long end)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_icache_inv_range(start, end);
- smp_cache_call(SMP_ICACHE_INV_RANGE, start, end);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_icache_inv_range2 - Globally invalidate range of instruction cache
- * @start: The start address of the region to be invalidated.
- * @size: The size of the region to be invalidated.
- *
- * Invalidate a range of addresses in the instruction cache on all CPUs,
- * between start and start+size-1 inclusive.
- */
-void mn10300_icache_inv_range2(unsigned long start, unsigned long size)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_icache_inv_range2(start, size);
- smp_cache_call(SMP_ICACHE_INV_RANGE, start, start + size);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_inv - Globally invalidate data cache
- *
- * Invalidate the data cache on all CPUs.
- */
-void mn10300_dcache_inv(void)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_inv();
- smp_cache_call(SMP_DCACHE_INV, 0, 0);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_inv_page - Globally invalidate a page of data cache
- * @start: The address of the page of memory to be invalidated.
- *
- * Invalidate a range of addresses in the data cache on all CPUs covering the
- * page that includes the given address.
- */
-void mn10300_dcache_inv_page(unsigned long start)
-{
- unsigned long flags;
-
- start &= ~(PAGE_SIZE-1);
-
- flags = smp_lock_cache();
- mn10300_local_dcache_inv_page(start);
- smp_cache_call(SMP_DCACHE_INV_RANGE, start, start + PAGE_SIZE);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_inv_range - Globally invalidate range of data cache
- * @start: The start address of the region to be invalidated.
- * @end: The end address of the region to be invalidated.
- *
- * Invalidate a range of addresses in the data cache on all CPUs, between start
- * and end-1 inclusive.
- */
-void mn10300_dcache_inv_range(unsigned long start, unsigned long end)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_inv_range(start, end);
- smp_cache_call(SMP_DCACHE_INV_RANGE, start, end);
- smp_unlock_cache(flags);
-}
-
-/**
- * mn10300_dcache_inv_range2 - Globally invalidate range of data cache
- * @start: The start address of the region to be invalidated.
- * @size: The size of the region to be invalidated.
- *
- * Invalidate a range of addresses in the data cache on all CPUs, between start
- * and start+size-1 inclusive.
- */
-void mn10300_dcache_inv_range2(unsigned long start, unsigned long size)
-{
- unsigned long flags;
-
- flags = smp_lock_cache();
- mn10300_local_dcache_inv_range2(start, size);
- smp_cache_call(SMP_DCACHE_INV_RANGE, start, start + size);
- smp_unlock_cache(flags);
-}
diff --git a/arch/mn10300/mm/cache-smp.c b/arch/mn10300/mm/cache-smp.c
deleted file mode 100644
index e80996064d3d..000000000000
--- a/arch/mn10300/mm/cache-smp.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SMP global caching code
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/mman.h>
-#include <linux/threads.h>
-#include <linux/interrupt.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <linux/uaccess.h>
-#include <asm/smp.h>
-#include "cache-smp.h"
-
-DEFINE_SPINLOCK(smp_cache_lock);
-static unsigned long smp_cache_mask;
-static unsigned long smp_cache_start;
-static unsigned long smp_cache_end;
-static cpumask_t smp_cache_ipi_map; /* Bitmask of cache IPI done CPUs */
-
-/**
- * smp_cache_interrupt - Handle IPI request to flush caches.
- *
- * Handle a request delivered by IPI to flush the current CPU's
- * caches. The parameters are stored in smp_cache_*.
- */
-void smp_cache_interrupt(void)
-{
- unsigned long opr_mask = smp_cache_mask;
-
- switch ((enum smp_dcache_ops)(opr_mask & SMP_DCACHE_OP_MASK)) {
- case SMP_DCACHE_NOP:
- break;
- case SMP_DCACHE_INV:
- mn10300_local_dcache_inv();
- break;
- case SMP_DCACHE_INV_RANGE:
- mn10300_local_dcache_inv_range(smp_cache_start, smp_cache_end);
- break;
- case SMP_DCACHE_FLUSH:
- mn10300_local_dcache_flush();
- break;
- case SMP_DCACHE_FLUSH_RANGE:
- mn10300_local_dcache_flush_range(smp_cache_start,
- smp_cache_end);
- break;
- case SMP_DCACHE_FLUSH_INV:
- mn10300_local_dcache_flush_inv();
- break;
- case SMP_DCACHE_FLUSH_INV_RANGE:
- mn10300_local_dcache_flush_inv_range(smp_cache_start,
- smp_cache_end);
- break;
- }
-
- switch ((enum smp_icache_ops)(opr_mask & SMP_ICACHE_OP_MASK)) {
- case SMP_ICACHE_NOP:
- break;
- case SMP_ICACHE_INV:
- mn10300_local_icache_inv();
- break;
- case SMP_ICACHE_INV_RANGE:
- mn10300_local_icache_inv_range(smp_cache_start, smp_cache_end);
- break;
- }
-
- cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map);
-}
-
-/**
- * smp_cache_call - Issue an IPI to request the other CPUs flush caches
- * @opr_mask: Cache operation flags
- * @start: Start address of request
- * @end: End address of request
- *
- * Send cache flush IPI to other CPUs. This invokes smp_cache_interrupt()
- * above on those other CPUs and then waits for them to finish.
- *
- * The caller must hold smp_cache_lock.
- */
-void smp_cache_call(unsigned long opr_mask,
- unsigned long start, unsigned long end)
-{
- smp_cache_mask = opr_mask;
- smp_cache_start = start;
- smp_cache_end = end;
- cpumask_copy(&smp_cache_ipi_map, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map);
-
- send_IPI_allbutself(FLUSH_CACHE_IPI);
-
- while (!cpumask_empty(&smp_cache_ipi_map))
- /* nothing. lockup detection does not belong here */
- mb();
-}
diff --git a/arch/mn10300/mm/cache-smp.h b/arch/mn10300/mm/cache-smp.h
deleted file mode 100644
index cb52892aa66a..000000000000
--- a/arch/mn10300/mm/cache-smp.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* SMP caching definitions
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-
-/*
- * Operation requests for smp_cache_call().
- *
- * One of smp_icache_ops and one of smp_dcache_ops can be OR'd together.
- */
-enum smp_icache_ops {
- SMP_ICACHE_NOP = 0x0000,
- SMP_ICACHE_INV = 0x0001,
- SMP_ICACHE_INV_RANGE = 0x0002,
-};
-#define SMP_ICACHE_OP_MASK 0x0003
-
-enum smp_dcache_ops {
- SMP_DCACHE_NOP = 0x0000,
- SMP_DCACHE_INV = 0x0004,
- SMP_DCACHE_INV_RANGE = 0x0008,
- SMP_DCACHE_FLUSH = 0x000c,
- SMP_DCACHE_FLUSH_RANGE = 0x0010,
- SMP_DCACHE_FLUSH_INV = 0x0014,
- SMP_DCACHE_FLUSH_INV_RANGE = 0x0018,
-};
-#define SMP_DCACHE_OP_MASK 0x001c
-
-#define SMP_IDCACHE_INV_FLUSH (SMP_ICACHE_INV | SMP_DCACHE_FLUSH)
-#define SMP_IDCACHE_INV_FLUSH_RANGE (SMP_ICACHE_INV_RANGE | SMP_DCACHE_FLUSH_RANGE)
-
-/*
- * cache-smp.c
- */
-#ifdef CONFIG_SMP
-extern spinlock_t smp_cache_lock;
-
-extern void smp_cache_call(unsigned long opr_mask,
- unsigned long addr, unsigned long end);
-
-static inline unsigned long smp_lock_cache(void)
- __acquires(&smp_cache_lock)
-{
- unsigned long flags;
- spin_lock_irqsave(&smp_cache_lock, flags);
- return flags;
-}
-
-static inline void smp_unlock_cache(unsigned long flags)
- __releases(&smp_cache_lock)
-{
- spin_unlock_irqrestore(&smp_cache_lock, flags);
-}
-
-#else
-static inline unsigned long smp_lock_cache(void) { return 0; }
-static inline void smp_unlock_cache(unsigned long flags) {}
-static inline void smp_cache_call(unsigned long opr_mask,
- unsigned long addr, unsigned long end)
-{
-}
-#endif /* CONFIG_SMP */
diff --git a/arch/mn10300/mm/cache.c b/arch/mn10300/mm/cache.c
deleted file mode 100644
index 0b925cce2b83..000000000000
--- a/arch/mn10300/mm/cache.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* MN10300 Cache flushing routines
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/mman.h>
-#include <linux/threads.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/cacheflush.h>
-#include <asm/io.h>
-#include <linux/uaccess.h>
-#include <asm/smp.h>
-#include "cache-smp.h"
-
-EXPORT_SYMBOL(mn10300_icache_inv);
-EXPORT_SYMBOL(mn10300_icache_inv_range);
-EXPORT_SYMBOL(mn10300_icache_inv_range2);
-EXPORT_SYMBOL(mn10300_icache_inv_page);
-EXPORT_SYMBOL(mn10300_dcache_inv);
-EXPORT_SYMBOL(mn10300_dcache_inv_range);
-EXPORT_SYMBOL(mn10300_dcache_inv_range2);
-EXPORT_SYMBOL(mn10300_dcache_inv_page);
-
-#ifdef CONFIG_MN10300_CACHE_WBACK
-EXPORT_SYMBOL(mn10300_dcache_flush);
-EXPORT_SYMBOL(mn10300_dcache_flush_inv);
-EXPORT_SYMBOL(mn10300_dcache_flush_inv_range);
-EXPORT_SYMBOL(mn10300_dcache_flush_inv_range2);
-EXPORT_SYMBOL(mn10300_dcache_flush_inv_page);
-EXPORT_SYMBOL(mn10300_dcache_flush_range);
-EXPORT_SYMBOL(mn10300_dcache_flush_range2);
-EXPORT_SYMBOL(mn10300_dcache_flush_page);
-#endif
-
-/*
- * allow userspace to flush the instruction cache
- */
-asmlinkage long sys_cacheflush(unsigned long start, unsigned long end)
-{
- if (end < start)
- return -EINVAL;
-
- flush_icache_range(start, end);
- return 0;
-}
diff --git a/arch/mn10300/mm/cache.inc b/arch/mn10300/mm/cache.inc
deleted file mode 100644
index 394a119b9c73..000000000000
--- a/arch/mn10300/mm/cache.inc
+++ /dev/null
@@ -1,133 +0,0 @@
-/* MN10300 CPU core caching macros -*- asm -*-
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-
-###############################################################################
-#
-# Invalidate the instruction cache.
-# A0: Should hold CHCTR
-# D0: Should have been read from CHCTR
-# D1: Will be clobbered
-#
-# On some cores it is necessary to disable the icache whilst we do this.
-#
-###############################################################################
- .macro invalidate_icache,disable_irq
-
-#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
- .if \disable_irq
- # don't want an interrupt routine seeing a disabled cache
- mov epsw,d1
- and ~EPSW_IE,epsw
- or EPSW_NMID,epsw
- nop
- nop
- .endif
-
- # disable the icache
- and ~CHCTR_ICEN,d0
- movhu d0,(a0)
-
- # and wait for it to calm down
- setlb
- movhu (a0),d0
- btst CHCTR_ICBUSY,d0
- lne
-
- # invalidate
- or CHCTR_ICINV,d0
- movhu d0,(a0)
-
- # wait for the cache to finish
- setlb
- movhu (a0),d0
- btst CHCTR_ICBUSY,d0
- lne
-
- # and reenable it
- or CHCTR_ICEN,d0
- movhu d0,(a0)
- movhu (a0),d0
-
- .if \disable_irq
- LOCAL_IRQ_RESTORE(d1)
- .endif
-
-#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
-
- # invalidate
- or CHCTR_ICINV,d0
- movhu d0,(a0)
- movhu (a0),d0
-
-#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
- .endm
-
-###############################################################################
-#
-# Invalidate the data cache.
-# A0: Should hold CHCTR
-# D0: Should have been read from CHCTR
-# D1: Will be clobbered
-#
-# On some cores it is necessary to disable the dcache whilst we do this.
-#
-###############################################################################
- .macro invalidate_dcache,disable_irq
-
-#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
- .if \disable_irq
- # don't want an interrupt routine seeing a disabled cache
- mov epsw,d1
- and ~EPSW_IE,epsw
- or EPSW_NMID,epsw
- nop
- nop
- .endif
-
- # disable the dcache
- and ~CHCTR_DCEN,d0
- movhu d0,(a0)
-
- # and wait for it to calm down
- setlb
- movhu (a0),d0
- btst CHCTR_DCBUSY,d0
- lne
-
- # invalidate
- or CHCTR_DCINV,d0
- movhu d0,(a0)
-
- # wait for the cache to finish
- setlb
- movhu (a0),d0
- btst CHCTR_DCBUSY,d0
- lne
-
- # and reenable it
- or CHCTR_DCEN,d0
- movhu d0,(a0)
- movhu (a0),d0
-
- .if \disable_irq
- LOCAL_IRQ_RESTORE(d1)
- .endif
-
-#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
-
- # invalidate
- or CHCTR_DCINV,d0
- movhu d0,(a0)
- movhu (a0),d0
-
-#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
- .endm
diff --git a/arch/mn10300/mm/dma-alloc.c b/arch/mn10300/mm/dma-alloc.c
deleted file mode 100644
index e3910d4db102..000000000000
--- a/arch/mn10300/mm/dma-alloc.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* MN10300 Dynamic DMA mapping support
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * Derived from: arch/i386/kernel/pci-dma.c
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/gfp.h>
-#include <linux/export.h>
-#include <asm/io.h>
-
-static unsigned long pci_sram_allocated = 0xbc000000;
-
-static void *mn10300_dma_alloc(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
-{
- unsigned long addr;
- void *ret;
-
- pr_debug("dma_alloc_coherent(%s,%zu,%x)\n",
- dev ? dev_name(dev) : "?", size, gfp);
-
- if (0xbe000000 - pci_sram_allocated >= size) {
- size = (size + 255) & ~255;
- addr = pci_sram_allocated;
- pci_sram_allocated += size;
- ret = (void *) addr;
- goto done;
- }
-
- if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
- gfp |= GFP_DMA;
-
- addr = __get_free_pages(gfp, get_order(size));
- if (!addr)
- return NULL;
-
- /* map the coherent memory through the uncached memory window */
- ret = (void *) (addr | 0x20000000);
-
- /* fill the memory with obvious rubbish */
- memset((void *) addr, 0xfb, size);
-
- /* write back and evict all cache lines covering this region */
- mn10300_dcache_flush_inv_range2(virt_to_phys((void *) addr), PAGE_SIZE);
-
-done:
- *dma_handle = virt_to_bus((void *) addr);
- printk("dma_alloc_coherent() = %p [%x]\n", ret, *dma_handle);
- return ret;
-}
-
-static void mn10300_dma_free(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- unsigned long addr = (unsigned long) vaddr & ~0x20000000;
-
- if (addr >= 0x9c000000)
- return;
-
- free_pages(addr, get_order(size));
-}
-
-static int mn10300_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- for_each_sg(sglist, sg, nents, i) {
- BUG_ON(!sg_page(sg));
-
- sg->dma_address = sg_phys(sg);
- }
-
- mn10300_dcache_flush_inv();
- return nents;
-}
-
-static dma_addr_t mn10300_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction, unsigned long attrs)
-{
- return page_to_bus(page) + offset;
-}
-
-static void mn10300_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
- size_t size, enum dma_data_direction direction)
-{
- mn10300_dcache_flush_inv();
-}
-
-static void mn10300_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
- int nelems, enum dma_data_direction direction)
-{
- mn10300_dcache_flush_inv();
-}
-
-static int mn10300_dma_supported(struct device *dev, u64 mask)
-{
- /*
- * we fall back to GFP_DMA when the mask isn't all 1s, so we can't
- * guarantee allocations that must be within a tighter range than
- * GFP_DMA
- */
- if (mask < 0x00ffffff)
- return 0;
- return 1;
-}
-
-const struct dma_map_ops mn10300_dma_ops = {
- .alloc = mn10300_dma_alloc,
- .free = mn10300_dma_free,
- .map_page = mn10300_dma_map_page,
- .map_sg = mn10300_dma_map_sg,
- .sync_single_for_device = mn10300_dma_sync_single_for_device,
- .sync_sg_for_device = mn10300_dma_sync_sg_for_device,
-};
diff --git a/arch/mn10300/mm/extable.c b/arch/mn10300/mm/extable.c
deleted file mode 100644
index 045a903ee6b9..000000000000
--- a/arch/mn10300/mm/extable.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* MN10300 In-kernel exception handling
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/extable.h>
-#include <linux/spinlock.h>
-#include <linux/uaccess.h>
-
-int fixup_exception(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
-
- fixup = search_exception_tables(regs->pc);
- if (fixup) {
- regs->pc = fixup->fixup;
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/mn10300/mm/fault.c b/arch/mn10300/mm/fault.c
deleted file mode 100644
index f0bfa1448744..000000000000
--- a/arch/mn10300/mm/fault.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/* MN10300 MMU Fault handler
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/vt_kern.h> /* For unblank_screen() */
-#include <linux/uaccess.h>
-
-#include <asm/pgalloc.h>
-#include <asm/hardirq.h>
-#include <asm/cpu-regs.h>
-#include <asm/debugger.h>
-#include <asm/gdb-stub.h>
-
-/*
- * Unlock any spinlocks which will prevent us from getting the
- * message out
- */
-void bust_spinlocks(int yes)
-{
- if (yes) {
- oops_in_progress = 1;
- } else {
- int loglevel_save = console_loglevel;
-#ifdef CONFIG_VT
- unblank_screen();
-#endif
- oops_in_progress = 0;
- /*
- * OK, the message is on the console. Now we call printk()
- * without oops_in_progress set so that printk will give klogd
- * a poke. Hold onto your hats...
- */
- console_loglevel = 15; /* NMI oopser may have shut the console
- * up */
- printk(" ");
- console_loglevel = loglevel_save;
- }
-}
-
-void do_BUG(const char *file, int line)
-{
- bust_spinlocks(1);
- printk(KERN_EMERG CUT_HERE);
- printk(KERN_EMERG "kernel BUG at %s:%d!\n", file, line);
-}
-
-#if 0
-static void print_pagetable_entries(pgd_t *pgdir, unsigned long address)
-{
- pgd_t *pgd;
- pmd_t *pmd;
- pte_t *pte;
-
- pgd = pgdir + __pgd_offset(address);
- printk(KERN_DEBUG "pgd entry %p: %016Lx\n",
- pgd, (long long) pgd_val(*pgd));
-
- if (!pgd_present(*pgd)) {
- printk(KERN_DEBUG "... pgd not present!\n");
- return;
- }
- pmd = pmd_offset(pgd, address);
- printk(KERN_DEBUG "pmd entry %p: %016Lx\n",
- pmd, (long long)pmd_val(*pmd));
-
- if (!pmd_present(*pmd)) {
- printk(KERN_DEBUG "... pmd not present!\n");
- return;
- }
- pte = pte_offset(pmd, address);
- printk(KERN_DEBUG "pte entry %p: %016Lx\n",
- pte, (long long) pte_val(*pte));
-
- if (!pte_present(*pte))
- printk(KERN_DEBUG "... pte not present!\n");
-}
-#endif
-
-/*
- * This routine handles page faults. It determines the address,
- * and the problem, and then passes it off to one of the appropriate
- * routines.
- *
- * fault_code:
- * - LSW: either MMUFCR_IFC or MMUFCR_DFC as appropriate
- * - MSW: 0 if data access, 1 if instruction access
- * - bit 0: TLB miss flag
- * - bit 1: initial write
- * - bit 2: page invalid
- * - bit 3: protection violation
- * - bit 4: accessor (0=user 1=kernel)
- * - bit 5: 0=read 1=write
- * - bit 6-8: page protection spec
- * - bit 9: illegal address
- * - bit 16: 0=data 1=ins
- *
- */
-asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long fault_code,
- unsigned long address)
-{
- struct vm_area_struct *vma;
- struct task_struct *tsk;
- struct mm_struct *mm;
- unsigned long page;
- siginfo_t info;
- int fault;
- unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
-
-#ifdef CONFIG_GDBSTUB
- /* handle GDB stub causing a fault */
- if (gdbstub_busy) {
- gdbstub_exception(regs, TBR & TBR_INT_CODE);
- return;
- }
-#endif
-
-#if 0
- printk(KERN_DEBUG "--- do_page_fault(%p,%s:%04lx,%08lx)\n",
- regs,
- fault_code & 0x10000 ? "ins" : "data",
- fault_code & 0xffff, address);
-#endif
-
- tsk = current;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- *
- * This verifies that the fault happens in kernel space
- * and that the fault was a page not present (invalid) error
- */
- if (address >= VMALLOC_START && address < VMALLOC_END &&
- (fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR &&
- (fault_code & MMUFCR_xFC_PGINVAL) == MMUFCR_xFC_PGINVAL
- )
- goto vmalloc_fault;
-
- mm = tsk->mm;
- info.si_code = SEGV_MAPERR;
-
- /*
- * If we're in an interrupt or have no user
- * context, we must not take the fault..
- */
- if (faulthandler_disabled() || !mm)
- goto no_context;
-
- if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR)
- flags |= FAULT_FLAG_USER;
-retry:
- down_read(&mm->mmap_sem);
-
- vma = find_vma(mm, address);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= address)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
-
- if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) {
- /* accessing the stack below the stack pointer is always a
- * bug */
- if ((address & PAGE_MASK) + 2 * PAGE_SIZE < regs->sp) {
-#if 0
- printk(KERN_WARNING
- "[%d] ### Access below stack @%lx (sp=%lx)\n",
- current->pid, address, regs->sp);
- printk(KERN_WARNING
- "vma [%08x - %08x]\n",
- vma->vm_start, vma->vm_end);
- show_registers(regs);
- printk(KERN_WARNING
- "[%d] ### Code: [%08lx]"
- " %02x %02x %02x %02x %02x %02x %02x %02x\n",
- current->pid,
- regs->pc,
- ((u8 *) regs->pc)[0],
- ((u8 *) regs->pc)[1],
- ((u8 *) regs->pc)[2],
- ((u8 *) regs->pc)[3],
- ((u8 *) regs->pc)[4],
- ((u8 *) regs->pc)[5],
- ((u8 *) regs->pc)[6],
- ((u8 *) regs->pc)[7]
- );
-#endif
- goto bad_area;
- }
- }
-
- if (expand_stack(vma, address))
- goto bad_area;
-
-/*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
-good_area:
- info.si_code = SEGV_ACCERR;
- switch (fault_code & (MMUFCR_xFC_PGINVAL|MMUFCR_xFC_TYPE)) {
- default: /* 3: write, present */
- case MMUFCR_xFC_TYPE_WRITE:
-#ifdef TEST_VERIFY_AREA
- if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR)
- printk(KERN_DEBUG "WP fault at %08lx\n", regs->pc);
-#endif
- /* write to absent page */
- case MMUFCR_xFC_PGINVAL | MMUFCR_xFC_TYPE_WRITE:
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- break;
-
- /* read from protected page */
- case MMUFCR_xFC_TYPE_READ:
- goto bad_area;
-
- /* read from absent page present */
- case MMUFCR_xFC_PGINVAL | MMUFCR_xFC_TYPE_READ:
- if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
- goto bad_area;
- break;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
- fault = handle_mm_fault(vma, address, flags);
-
- if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
- return;
-
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
- if (flags & FAULT_FLAG_ALLOW_RETRY) {
- if (fault & VM_FAULT_MAJOR)
- current->maj_flt++;
- else
- current->min_flt++;
- if (fault & VM_FAULT_RETRY) {
- flags &= ~FAULT_FLAG_ALLOW_RETRY;
-
- /* No need to up_read(&mm->mmap_sem) as we would
- * have already released it in __lock_page_or_retry
- * in mm/filemap.c.
- */
-
- goto retry;
- }
- }
-
- up_read(&mm->mmap_sem);
- return;
-
-/*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
-bad_area:
- up_read(&mm->mmap_sem);
-
- /* User mode accesses just cause a SIGSEGV */
- if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) {
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
- info.si_addr = (void *)address;
- force_sig_info(SIGSEGV, &info, tsk);
- return;
- }
-
-no_context:
- /* Are we prepared to handle this kernel fault? */
- if (fixup_exception(regs))
- return;
-
-/*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- bust_spinlocks(1);
-
- if (address < PAGE_SIZE)
- printk(KERN_ALERT
- "Unable to handle kernel NULL pointer dereference");
- else
- printk(KERN_ALERT
- "Unable to handle kernel paging request");
- printk(" at virtual address %08lx\n", address);
- printk(" printing pc:\n");
- printk(KERN_ALERT "%08lx\n", regs->pc);
-
- debugger_intercept(fault_code & 0x00010000 ? EXCEP_IAERROR : EXCEP_DAERROR,
- SIGSEGV, SEGV_ACCERR, regs);
-
- page = PTBR;
- page = ((unsigned long *) __va(page))[address >> 22];
- printk(KERN_ALERT "*pde = %08lx\n", page);
- if (page & 1) {
- page &= PAGE_MASK;
- address &= 0x003ff000;
- page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
- printk(KERN_ALERT "*pte = %08lx\n", page);
- }
-
- die("Oops", regs, fault_code);
- do_exit(SIGKILL);
-
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-out_of_memory:
- up_read(&mm->mmap_sem);
- if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) {
- pagefault_out_of_memory();
- return;
- }
- goto no_context;
-
-do_sigbus:
- up_read(&mm->mmap_sem);
-
- /*
- * Send a sigbus, regardless of whether we were in kernel
- * or user mode.
- */
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (void *)address;
- force_sig_info(SIGBUS, &info, tsk);
-
- /* Kernel mode? Handle exceptions or die */
- if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR)
- goto no_context;
- return;
-
-vmalloc_fault:
- {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Do _not_ use "tsk" here. We might be inside
- * an interrupt in the middle of a task switch..
- */
- int index = pgd_index(address);
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd_k = init_mm.pgd + index;
-
- if (!pgd_present(*pgd_k))
- goto no_context;
-
- pud_k = pud_offset(pgd_k, address);
- if (!pud_present(*pud_k))
- goto no_context;
-
- pmd_k = pmd_offset(pud_k, address);
- if (!pmd_present(*pmd_k))
- goto no_context;
-
- pgd = (pgd_t *) PTBR + index;
- pud = pud_offset(pgd, address);
- pmd = pmd_offset(pud, address);
- set_pmd(pmd, *pmd_k);
-
- pte_k = pte_offset_kernel(pmd_k, address);
- if (!pte_present(*pte_k))
- goto no_context;
- return;
- }
-}
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
deleted file mode 100644
index 8ce677d5575e..000000000000
--- a/arch/mn10300/mm/init.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* MN10300 Memory management initialisation
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/initrd.h>
-#include <linux/highmem.h>
-#include <linux/pagemap.h>
-#include <linux/bootmem.h>
-#include <linux/gfp.h>
-
-#include <asm/processor.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/dma.h>
-#include <asm/tlb.h>
-#include <asm/sections.h>
-
-unsigned long highstart_pfn, highend_pfn;
-
-#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
-static struct vm_struct user_iomap_vm;
-#endif
-
-/*
- * set up paging
- */
-void __init paging_init(void)
-{
- unsigned long zones_size[MAX_NR_ZONES] = {0,};
- pte_t *ppte;
- int loop;
-
- /* main kernel space -> RAM mapping is handled as 1:1 transparent by
- * the MMU */
- memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
- memset(kernel_vmalloc_ptes, 0, sizeof(kernel_vmalloc_ptes));
-
- /* load the VMALLOC area PTE table addresses into the kernel PGD */
- ppte = kernel_vmalloc_ptes;
- for (loop = VMALLOC_START / (PAGE_SIZE * PTRS_PER_PTE);
- loop < VMALLOC_END / (PAGE_SIZE * PTRS_PER_PTE);
- loop++
- ) {
- set_pgd(swapper_pg_dir + loop, __pgd(__pa(ppte) | _PAGE_TABLE));
- ppte += PAGE_SIZE / sizeof(pte_t);
- }
-
- /* declare the sizes of the RAM zones (only use the normal zone) */
- zones_size[ZONE_NORMAL] =
- contig_page_data.bdata->node_low_pfn -
- contig_page_data.bdata->node_min_pfn;
-
- /* pass the memory from the bootmem allocator to the main allocator */
- free_area_init(zones_size);
-
-#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
- /* The Atomic Operation Unit registers need to be mapped to userspace
- * for all processes. The following uses vm_area_register_early() to
- * reserve the first page of the vmalloc area and sets the pte for that
- * page.
- *
- * glibc hardcodes this virtual mapping, so we're pretty much stuck with
- * it from now on.
- */
- user_iomap_vm.flags = VM_USERMAP;
- user_iomap_vm.size = 1 << PAGE_SHIFT;
- vm_area_register_early(&user_iomap_vm, PAGE_SIZE);
- ppte = kernel_vmalloc_ptes;
- set_pte(ppte, pfn_pte(USER_ATOMIC_OPS_PAGE_ADDR >> PAGE_SHIFT,
- PAGE_USERIO));
-#endif
-
- local_flush_tlb_all();
-}
-
-/*
- * transfer all the memory from the bootmem allocator to the runtime allocator
- */
-void __init mem_init(void)
-{
- BUG_ON(!mem_map);
-
-#define START_PFN (contig_page_data.bdata->node_min_pfn)
-#define MAX_LOW_PFN (contig_page_data.bdata->node_low_pfn)
-
- max_mapnr = MAX_LOW_PFN - START_PFN;
- high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
-
- /* clear the zero-page */
- memset(empty_zero_page, 0, PAGE_SIZE);
-
- /* this will put all low memory onto the freelists */
- free_all_bootmem();
-
- mem_init_print_info(NULL);
-}
-
-/*
- * recycle memory containing stuff only required for initialisation
- */
-void free_initmem(void)
-{
- free_initmem_default(POISON_FREE_INITMEM);
-}
-
-/*
- * dispose of the memory on which the initial ramdisk resided
- */
-#ifdef CONFIG_BLK_DEV_INITRD
-void free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
- "initrd");
-}
-#endif
diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c
deleted file mode 100644
index 8ace89617c1c..000000000000
--- a/arch/mn10300/mm/misalignment.c
+++ /dev/null
@@ -1,966 +0,0 @@
-/* MN10300 Misalignment fixup handler
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/extable.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/errno.h>
-#include <linux/ptrace.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <asm/processor.h>
-#include <linux/uaccess.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-#include <asm/smp.h>
-#include <asm/pgalloc.h>
-#include <asm/cpu-regs.h>
-#include <asm/busctl-regs.h>
-#include <asm/fpu.h>
-#include <asm/gdb-stub.h>
-#include <asm/asm-offsets.h>
-
-#if 0
-#define kdebug(FMT, ...) printk(KERN_DEBUG "MISALIGN: "FMT"\n", ##__VA_ARGS__)
-#else
-#define kdebug(FMT, ...) do {} while (0)
-#endif
-
-static int misalignment_addr(unsigned long *registers, unsigned long sp,
- unsigned params, unsigned opcode,
- unsigned long disp,
- void **_address, unsigned long **_postinc,
- unsigned long *_inc);
-
-static int misalignment_reg(unsigned long *registers, unsigned params,
- unsigned opcode, unsigned long disp,
- unsigned long **_register);
-
-static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
-
-static const unsigned Dreg_index[] = {
- REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
-};
-
-static const unsigned Areg_index[] = {
- REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
-};
-
-static const unsigned Rreg_index[] = {
- REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
- REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
- REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
- REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
-};
-
-enum format_id {
- FMT_S0,
- FMT_S1,
- FMT_S2,
- FMT_S4,
- FMT_D0,
- FMT_D1,
- FMT_D2,
- FMT_D4,
- FMT_D6,
- FMT_D7,
- FMT_D8,
- FMT_D9,
- FMT_D10,
-};
-
-static const struct {
- u_int8_t opsz, dispsz;
-} format_tbl[16] = {
- [FMT_S0] = { 8, 0 },
- [FMT_S1] = { 8, 8 },
- [FMT_S2] = { 8, 16 },
- [FMT_S4] = { 8, 32 },
- [FMT_D0] = { 16, 0 },
- [FMT_D1] = { 16, 8 },
- [FMT_D2] = { 16, 16 },
- [FMT_D4] = { 16, 32 },
- [FMT_D6] = { 24, 0 },
- [FMT_D7] = { 24, 8 },
- [FMT_D8] = { 24, 24 },
- [FMT_D9] = { 24, 32 },
- [FMT_D10] = { 32, 0 },
-};
-
-enum value_id {
- DM0, /* data reg in opcode in bits 0-1 */
- DM1, /* data reg in opcode in bits 2-3 */
- DM2, /* data reg in opcode in bits 4-5 */
- AM0, /* addr reg in opcode in bits 0-1 */
- AM1, /* addr reg in opcode in bits 2-3 */
- AM2, /* addr reg in opcode in bits 4-5 */
- RM0, /* reg in opcode in bits 0-3 */
- RM1, /* reg in opcode in bits 2-5 */
- RM2, /* reg in opcode in bits 4-7 */
- RM4, /* reg in opcode in bits 8-11 */
- RM6, /* reg in opcode in bits 12-15 */
-
- RD0, /* reg in displacement in bits 0-3 */
- RD2, /* reg in displacement in bits 4-7 */
-
- SP, /* stack pointer */
-
- SD8, /* 8-bit signed displacement */
- SD16, /* 16-bit signed displacement */
- SD24, /* 24-bit signed displacement */
- SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
- SIMM8, /* 8-bit signed immediate */
- IMM8, /* 8-bit unsigned immediate */
- IMM16, /* 16-bit unsigned immediate */
- IMM24, /* 24-bit unsigned immediate */
- IMM32, /* 32-bit unsigned immediate */
- IMM32_HIGH8, /* 32-bit unsigned immediate, LSB in opcode */
-
- IMM32_MEM, /* 32-bit unsigned displacement */
- IMM32_HIGH8_MEM, /* 32-bit unsigned displacement, LSB in opcode */
-
- DN0 = DM0,
- DN1 = DM1,
- DN2 = DM2,
- AN0 = AM0,
- AN1 = AM1,
- AN2 = AM2,
- RN0 = RM0,
- RN1 = RM1,
- RN2 = RM2,
- RN4 = RM4,
- RN6 = RM6,
- DI = DM1,
- RI = RM2,
-
-};
-
-struct mn10300_opcode {
- const char name[8];
- u_int32_t opcode;
- u_int32_t opmask;
- unsigned exclusion;
-
- enum format_id format;
-
- unsigned cpu_mask;
-#define AM33 330
-
- unsigned params[2];
-#define MEM(ADDR) (0x80000000 | (ADDR))
-#define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2))
-#define MEMINC(ADDR) (0x81000000 | (ADDR))
-#define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC))
-};
-
-/* LIBOPCODES EXCERPT
- Assemble Matsushita MN10300 instructions.
- Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public Licence as published by
- the Free Software Foundation; either version 2 of the Licence, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public Licence for more details.
-
- You should have received a copy of the GNU General Public Licence
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-*/
-static const struct mn10300_opcode mn10300_opcodes[] = {
-{ "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
-{ "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
-{ "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
-{ "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
-{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
-{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
-{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
-{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
-{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
-{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
-{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
-{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
-{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
-{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
-{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
-{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
-{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
-{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
-{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
-{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
-{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
-{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
-{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
-{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
-{ "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
-{ "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
-{ "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
-{ "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
-{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
-{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
-{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
-{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
-{ "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
-{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
-{ "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
-{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
-{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
-{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
-{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
-{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
-{ "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
-{ "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
-{ "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
-{ "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
-{ "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
-{ "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
-{ "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
-{ "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
-{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
-{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
-{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
-{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
-{ "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
-{ "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
-{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
-{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
-{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
-{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
-{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
-{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
-{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
-{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
-{ "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
-{ "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
-
-{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
-{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
-{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
-{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
-{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
-{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
-{ "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
-{ "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
-{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
-{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
-{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
-{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
-{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
-{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
-{ "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
-{ "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
-{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
-{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
-{ "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
-{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
-{ "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
-{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
-{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
-{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
-{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
-{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
-{ "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
-{ "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
-{ "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
-{ "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
-{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
-{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
-{ "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
-{ "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
-{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
-{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
-{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
-{ "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
-{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
-{ "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
-{ "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
-{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
-{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
-{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
-
-{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
-
-{ "", 0, 0, 0, 0, 0, {0}},
-};
-
-/*
- * fix up misalignment problems where possible
- */
-asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
-{
- const struct exception_table_entry *fixup;
- const struct mn10300_opcode *pop;
- unsigned long *registers = (unsigned long *) regs;
- unsigned long data, *store, *postinc, disp, inc, sp;
- mm_segment_t seg;
- siginfo_t info;
- uint32_t opcode, noc, xo, xm;
- uint8_t *pc, byte, datasz;
- void *address;
- unsigned tmp, npop, dispsz, loop;
-
- /* we don't fix up userspace misalignment faults */
- if (user_mode(regs))
- goto bus_error;
-
- sp = (unsigned long) regs + sizeof(*regs);
-
- kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp);
-
- if (regs->epsw & EPSW_IE)
- asm volatile("or %0,epsw" : : "i"(EPSW_IE));
-
- seg = get_fs();
- set_fs(KERNEL_DS);
-
- fixup = search_exception_tables(regs->pc);
-
- /* first thing to do is to match the opcode */
- pc = (u_int8_t *) regs->pc;
-
- if (__get_user(byte, pc) != 0)
- goto fetch_error;
- opcode = byte;
- noc = 8;
-
- for (pop = mn10300_opcodes; pop->name[0]; pop++) {
- npop = ilog2(pop->opcode | pop->opmask);
- if (npop <= 0 || npop > 31)
- continue;
- npop = (npop + 8) & ~7;
-
- got_more_bits:
- if (npop == noc) {
- if ((opcode & pop->opmask) == pop->opcode)
- goto found_opcode;
- } else if (npop > noc) {
- xo = pop->opcode >> (npop - noc);
- xm = pop->opmask >> (npop - noc);
-
- if ((opcode & xm) != xo)
- continue;
-
- /* we've got a partial match (an exact match on the
- * first N bytes), so we need to get some more data */
- pc++;
- if (__get_user(byte, pc) != 0)
- goto fetch_error;
- opcode = opcode << 8 | byte;
- noc += 8;
- goto got_more_bits;
- } else {
- /* there's already been a partial match as long as the
- * complete match we're now considering, so this one
- * should't match */
- continue;
- }
- }
-
- /* didn't manage to find a fixup */
- printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
- regs->pc, opcode);
-
-failed:
- set_fs(seg);
- if (die_if_no_fixup("misalignment error", regs, code))
- return;
-
-bus_error:
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRALN;
- info.si_addr = (void *) regs->pc;
- force_sig_info(SIGBUS, &info, current);
- return;
-
- /* error reading opcodes */
-fetch_error:
- printk(KERN_CRIT
- "MISALIGN: %p: fault whilst reading instruction data\n",
- pc);
- goto failed;
-
-bad_addr_mode:
- printk(KERN_CRIT
- "MISALIGN: %lx: unsupported addressing mode %x\n",
- regs->pc, opcode);
- goto failed;
-
-bad_reg_mode:
- printk(KERN_CRIT
- "MISALIGN: %lx: unsupported register mode %x\n",
- regs->pc, opcode);
- goto failed;
-
-unsupported_instruction:
- printk(KERN_CRIT
- "MISALIGN: %lx: unsupported instruction %x (%s)\n",
- regs->pc, opcode, pop->name);
- goto failed;
-
-transfer_failed:
- set_fs(seg);
- if (fixup) {
- regs->pc = fixup->fixup;
- return;
- }
- if (die_if_no_fixup("misalignment fixup", regs, code))
- return;
-
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- info.si_code = SEGV_MAPERR;
- info.si_addr = (void *) regs->pc;
- force_sig_info(SIGSEGV, &info, current);
- return;
-
- /* we matched the opcode */
-found_opcode:
- kdebug("%lx: %x==%x { %x, %x }",
- regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
-
- tmp = format_tbl[pop->format].opsz;
- BUG_ON(tmp > noc); /* match was less complete than it ought to have been */
-
- if (tmp < noc) {
- tmp = noc - tmp;
- opcode >>= tmp;
- pc -= tmp >> 3;
- }
-
- /* grab the extra displacement (note it's LSB first) */
- disp = 0;
- dispsz = format_tbl[pop->format].dispsz;
- for (loop = 0; loop < dispsz; loop += 8) {
- pc++;
- if (__get_user(byte, pc) != 0)
- goto fetch_error;
- disp |= byte << loop;
- kdebug("{%p} disp[%02x]=%02x", pc, loop, byte);
- }
-
- kdebug("disp=%lx", disp);
-
- set_fs(KERNEL_XDS);
- if (fixup)
- set_fs(seg);
-
- tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
- if (!tmp) {
- printk(KERN_CRIT
- "MISALIGN: %lx: insn not move to/from memory %x\n",
- regs->pc, opcode);
- goto failed;
- }
-
- /* determine the data transfer size of the move */
- if (pop->name[3] == 0 || /* "mov" */
- pop->name[4] == 'l') /* mov_lcc */
- inc = datasz = 4;
- else if (pop->name[3] == 'h') /* movhu */
- inc = datasz = 2;
- else
- goto unsupported_instruction;
-
- if (pop->params[0] & 0x80000000) {
- /* move memory to register */
- if (!misalignment_addr(registers, sp,
- pop->params[0], opcode, disp,
- &address, &postinc, &inc))
- goto bad_addr_mode;
-
- if (!misalignment_reg(registers, pop->params[1], opcode, disp,
- &store))
- goto bad_reg_mode;
-
- kdebug("mov%u (%p),DARn", datasz, address);
- if (copy_from_user(&data, (void *) address, datasz) != 0)
- goto transfer_failed;
- if (pop->params[0] & 0x1000000) {
- kdebug("inc=%lx", inc);
- *postinc += inc;
- }
-
- *store = data;
- kdebug("loaded %lx", data);
- } else {
- /* move register to memory */
- if (!misalignment_reg(registers, pop->params[0], opcode, disp,
- &store))
- goto bad_reg_mode;
-
- if (!misalignment_addr(registers, sp,
- pop->params[1], opcode, disp,
- &address, &postinc, &inc))
- goto bad_addr_mode;
-
- data = *store;
-
- kdebug("mov%u %lx,(%p)", datasz, data, address);
- if (copy_to_user((void *) address, &data, datasz) != 0)
- goto transfer_failed;
- if (pop->params[1] & 0x1000000)
- *postinc += inc;
- }
-
- tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
- regs->pc += tmp >> 3;
-
- /* handle MOV_Lcc, which are currently the only FMT_D10 insns that
- * access memory */
- if (pop->format == FMT_D10)
- misalignment_MOV_Lcc(regs, opcode);
-
- set_fs(seg);
-}
-
-/*
- * determine the address that was being accessed
- */
-static int misalignment_addr(unsigned long *registers, unsigned long sp,
- unsigned params, unsigned opcode,
- unsigned long disp,
- void **_address, unsigned long **_postinc,
- unsigned long *_inc)
-{
- unsigned long *postinc = NULL, address = 0, tmp;
-
- if (!(params & 0x1000000)) {
- kdebug("noinc");
- *_inc = 0;
- _inc = NULL;
- }
-
- params &= 0x00ffffff;
-
- do {
- switch (params & 0xff) {
- case DM0:
- postinc = &registers[Dreg_index[opcode & 0x03]];
- address += *postinc;
- break;
- case DM1:
- postinc = &registers[Dreg_index[opcode >> 2 & 0x03]];
- address += *postinc;
- break;
- case DM2:
- postinc = &registers[Dreg_index[opcode >> 4 & 0x03]];
- address += *postinc;
- break;
- case AM0:
- postinc = &registers[Areg_index[opcode & 0x03]];
- address += *postinc;
- break;
- case AM1:
- postinc = &registers[Areg_index[opcode >> 2 & 0x03]];
- address += *postinc;
- break;
- case AM2:
- postinc = &registers[Areg_index[opcode >> 4 & 0x03]];
- address += *postinc;
- break;
- case RM0:
- postinc = &registers[Rreg_index[opcode & 0x0f]];
- address += *postinc;
- break;
- case RM1:
- postinc = &registers[Rreg_index[opcode >> 2 & 0x0f]];
- address += *postinc;
- break;
- case RM2:
- postinc = &registers[Rreg_index[opcode >> 4 & 0x0f]];
- address += *postinc;
- break;
- case RM4:
- postinc = &registers[Rreg_index[opcode >> 8 & 0x0f]];
- address += *postinc;
- break;
- case RM6:
- postinc = &registers[Rreg_index[opcode >> 12 & 0x0f]];
- address += *postinc;
- break;
- case RD0:
- postinc = &registers[Rreg_index[disp & 0x0f]];
- address += *postinc;
- break;
- case RD2:
- postinc = &registers[Rreg_index[disp >> 4 & 0x0f]];
- address += *postinc;
- break;
- case SP:
- address += sp;
- break;
-
- /* displacements are either to be added to the address
- * before use, or, in the case of post-inc addressing,
- * to be added into the base register after use */
- case SD8:
- case SIMM8:
- disp = (long) (int8_t) (disp & 0xff);
- goto displace_or_inc;
- case SD16:
- disp = (long) (int16_t) (disp & 0xffff);
- goto displace_or_inc;
- case SD24:
- tmp = disp << 8;
- asm("asr 8,%0" : "=r"(tmp) : "0"(tmp) : "cc");
- disp = (long) tmp;
- goto displace_or_inc;
- case SIMM4_2:
- tmp = opcode >> 4 & 0x0f;
- tmp <<= 28;
- asm("asr 28,%0" : "=r"(tmp) : "0"(tmp) : "cc");
- disp = (long) tmp;
- goto displace_or_inc;
- case IMM8:
- disp &= 0x000000ff;
- goto displace_or_inc;
- case IMM16:
- disp &= 0x0000ffff;
- goto displace_or_inc;
- case IMM24:
- disp &= 0x00ffffff;
- goto displace_or_inc;
- case IMM32:
- case IMM32_MEM:
- case IMM32_HIGH8:
- case IMM32_HIGH8_MEM:
- displace_or_inc:
- kdebug("%s %lx", _inc ? "incr" : "disp", disp);
- if (!_inc)
- address += disp;
- else
- *_inc = disp;
- break;
- default:
- BUG();
- return 0;
- }
- } while ((params >>= 8));
-
- *_address = (void *) address;
- *_postinc = postinc;
- return 1;
-}
-
-/*
- * determine the register that is acting as source/dest
- */
-static int misalignment_reg(unsigned long *registers, unsigned params,
- unsigned opcode, unsigned long disp,
- unsigned long **_register)
-{
- params &= 0x7fffffff;
-
- if (params & 0xffffff00)
- return 0;
-
- switch (params & 0xff) {
- case DM0:
- *_register = &registers[Dreg_index[opcode & 0x03]];
- break;
- case DM1:
- *_register = &registers[Dreg_index[opcode >> 2 & 0x03]];
- break;
- case DM2:
- *_register = &registers[Dreg_index[opcode >> 4 & 0x03]];
- break;
- case AM0:
- *_register = &registers[Areg_index[opcode & 0x03]];
- break;
- case AM1:
- *_register = &registers[Areg_index[opcode >> 2 & 0x03]];
- break;
- case AM2:
- *_register = &registers[Areg_index[opcode >> 4 & 0x03]];
- break;
- case RM0:
- *_register = &registers[Rreg_index[opcode & 0x0f]];
- break;
- case RM1:
- *_register = &registers[Rreg_index[opcode >> 2 & 0x0f]];
- break;
- case RM2:
- *_register = &registers[Rreg_index[opcode >> 4 & 0x0f]];
- break;
- case RM4:
- *_register = &registers[Rreg_index[opcode >> 8 & 0x0f]];
- break;
- case RM6:
- *_register = &registers[Rreg_index[opcode >> 12 & 0x0f]];
- break;
- case RD0:
- *_register = &registers[Rreg_index[disp & 0x0f]];
- break;
- case RD2:
- *_register = &registers[Rreg_index[disp >> 4 & 0x0f]];
- break;
- case SP:
- *_register = &registers[REG_SP >> 2];
- break;
-
- default:
- BUG();
- return 0;
- }
-
- return 1;
-}
-
-/*
- * handle the conditional loop part of the move-and-loop instructions
- */
-static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode)
-{
- unsigned long epsw = regs->epsw;
- unsigned long NxorV;
-
- kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf);
-
- /* calculate N^V and shift onto the same bit position as Z */
- NxorV = ((epsw >> 3) ^ epsw >> 1) & 1;
-
- switch (opcode & 0xf) {
- case 0x0: /* MOV_LLT: N^V */
- if (NxorV)
- goto take_the_loop;
- return;
- case 0x1: /* MOV_LGT: ~(Z or (N^V))*/
- if (!((epsw & EPSW_FLAG_Z) | NxorV))
- goto take_the_loop;
- return;
- case 0x2: /* MOV_LGE: ~(N^V) */
- if (!NxorV)
- goto take_the_loop;
- return;
- case 0x3: /* MOV_LLE: Z or (N^V) */
- if ((epsw & EPSW_FLAG_Z) | NxorV)
- goto take_the_loop;
- return;
-
- case 0x4: /* MOV_LCS: C */
- if (epsw & EPSW_FLAG_C)
- goto take_the_loop;
- return;
- case 0x5: /* MOV_LHI: ~(C or Z) */
- if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)))
- goto take_the_loop;
- return;
- case 0x6: /* MOV_LCC: ~C */
- if (!(epsw & EPSW_FLAG_C))
- goto take_the_loop;
- return;
- case 0x7: /* MOV_LLS: C or Z */
- if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))
- goto take_the_loop;
- return;
-
- case 0x8: /* MOV_LEQ: Z */
- if (epsw & EPSW_FLAG_Z)
- goto take_the_loop;
- return;
- case 0x9: /* MOV_LNE: ~Z */
- if (!(epsw & EPSW_FLAG_Z))
- goto take_the_loop;
- return;
- case 0xa: /* MOV_LRA: always */
- goto take_the_loop;
-
- default:
- BUG();
- }
-
-take_the_loop:
- /* wind the PC back to just after the SETLB insn */
- kdebug("loop LAR=%lx", regs->lar);
- regs->pc = regs->lar - 4;
-}
-
-/*
- * misalignment handler tests
- */
-#ifdef CONFIG_TEST_MISALIGNMENT_HANDLER
-static u8 __initdata testbuf[512] __attribute__((aligned(16))) = {
- [257] = 0x11,
- [258] = 0x22,
- [259] = 0x33,
- [260] = 0x44,
-};
-
-#define ASSERTCMP(X, OP, Y) \
-do { \
- if (unlikely(!((X) OP (Y)))) { \
- printk(KERN_ERR "\n"); \
- printk(KERN_ERR "MISALIGN: Assertion failed at line %u\n", \
- __LINE__); \
- printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
- (unsigned long)(X), (unsigned long)(Y)); \
- BUG(); \
- } \
-} while(0)
-
-static int __init test_misalignment(void)
-{
- register void *r asm("e0");
- register u32 y asm("e1");
- void *p = testbuf, *q;
- u32 tmp, tmp2, x;
-
- printk(KERN_NOTICE "==>test_misalignment() [testbuf=%p]\n", p);
- p++;
-
- printk(KERN_NOTICE "___ MOV (Am),Dn ___\n");
- q = p + 256;
- asm volatile("mov (%0),%1" : "+a"(q), "=d"(x));
- ASSERTCMP(q, ==, p + 256);
- ASSERTCMP(x, ==, 0x44332211);
-
- printk(KERN_NOTICE "___ MOV (256,Am),Dn ___\n");
- q = p;
- asm volatile("mov (256,%0),%1" : "+a"(q), "=d"(x));
- ASSERTCMP(q, ==, p);
- ASSERTCMP(x, ==, 0x44332211);
-
- printk(KERN_NOTICE "___ MOV (Di,Am),Dn ___\n");
- tmp = 256;
- q = p;
- asm volatile("mov (%2,%0),%1" : "+a"(q), "=d"(x), "+d"(tmp));
- ASSERTCMP(q, ==, p);
- ASSERTCMP(x, ==, 0x44332211);
- ASSERTCMP(tmp, ==, 256);
-
- printk(KERN_NOTICE "___ MOV (256,Rm),Rn ___\n");
- r = p;
- asm volatile("mov (256,%0),%1" : "+r"(r), "=r"(y));
- ASSERTCMP(r, ==, p);
- ASSERTCMP(y, ==, 0x44332211);
-
- printk(KERN_NOTICE "___ MOV (Rm+),Rn ___\n");
- r = p + 256;
- asm volatile("mov (%0+),%1" : "+r"(r), "=r"(y));
- ASSERTCMP(r, ==, p + 256 + 4);
- ASSERTCMP(y, ==, 0x44332211);
-
- printk(KERN_NOTICE "___ MOV (Rm+,8),Rn ___\n");
- r = p + 256;
- asm volatile("mov (%0+,8),%1" : "+r"(r), "=r"(y));
- ASSERTCMP(r, ==, p + 256 + 8);
- ASSERTCMP(y, ==, 0x44332211);
-
- printk(KERN_NOTICE "___ MOV (7,SP),Rn ___\n");
- asm volatile(
- "add -16,sp \n"
- "mov +0x11,%0 \n"
- "movbu %0,(7,sp) \n"
- "mov +0x22,%0 \n"
- "movbu %0,(8,sp) \n"
- "mov +0x33,%0 \n"
- "movbu %0,(9,sp) \n"
- "mov +0x44,%0 \n"
- "movbu %0,(10,sp) \n"
- "mov (7,sp),%1 \n"
- "add +16,sp \n"
- : "+a"(q), "=d"(x));
- ASSERTCMP(x, ==, 0x44332211);
-
- printk(KERN_NOTICE "___ MOV (259,SP),Rn ___\n");
- asm volatile(
- "add -264,sp \n"
- "mov +0x11,%0 \n"
- "movbu %0,(259,sp) \n"
- "mov +0x22,%0 \n"
- "movbu %0,(260,sp) \n"
- "mov +0x33,%0 \n"
- "movbu %0,(261,sp) \n"
- "mov +0x55,%0 \n"
- "movbu %0,(262,sp) \n"
- "mov (259,sp),%1 \n"
- "add +264,sp \n"
- : "+d"(tmp), "=d"(x));
- ASSERTCMP(x, ==, 0x55332211);
-
- printk(KERN_NOTICE "___ MOV (260,SP),Rn ___\n");
- asm volatile(
- "add -264,sp \n"
- "mov +0x11,%0 \n"
- "movbu %0,(260,sp) \n"
- "mov +0x22,%0 \n"
- "movbu %0,(261,sp) \n"
- "mov +0x33,%0 \n"
- "movbu %0,(262,sp) \n"
- "mov +0x55,%0 \n"
- "movbu %0,(263,sp) \n"
- "mov (260,sp),%1 \n"
- "add +264,sp \n"
- : "+d"(tmp), "=d"(x));
- ASSERTCMP(x, ==, 0x55332211);
-
-
- printk(KERN_NOTICE "___ MOV_LNE ___\n");
- tmp = 1;
- tmp2 = 2;
- q = p + 256;
- asm volatile(
- "setlb \n"
- "mov %2,%3 \n"
- "mov %1,%2 \n"
- "cmp +0,%1 \n"
- "mov_lne (%0+,4),%1"
- : "+r"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
- :
- : "cc");
- ASSERTCMP(q, ==, p + 256 + 12);
- ASSERTCMP(x, ==, 0x44332211);
-
- printk(KERN_NOTICE "___ MOV in SETLB ___\n");
- tmp = 1;
- tmp2 = 2;
- q = p + 256;
- asm volatile(
- "setlb \n"
- "mov %1,%3 \n"
- "mov (%0+),%1 \n"
- "cmp +0,%1 \n"
- "lne "
- : "+a"(q), "+d"(tmp), "+d"(tmp2), "=d"(x)
- :
- : "cc");
-
- ASSERTCMP(q, ==, p + 256 + 8);
- ASSERTCMP(x, ==, 0x44332211);
-
- printk(KERN_NOTICE "<==test_misalignment()\n");
- return 0;
-}
-
-arch_initcall(test_misalignment);
-
-#endif /* CONFIG_TEST_MISALIGNMENT_HANDLER */
diff --git a/arch/mn10300/mm/mmu-context.c b/arch/mn10300/mm/mmu-context.c
deleted file mode 100644
index a4f7d3dcc6e6..000000000000
--- a/arch/mn10300/mm/mmu-context.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* MN10300 MMU context allocation and management
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/mmu_context.h>
-#include <asm/tlbflush.h>
-
-#ifdef CONFIG_MN10300_TLB_USE_PIDR
-/*
- * list of the MMU contexts last allocated on each CPU
- */
-unsigned long mmu_context_cache[NR_CPUS] = {
- [0 ... NR_CPUS - 1] =
- MMU_CONTEXT_FIRST_VERSION * 2 - (1 - MMU_CONTEXT_TLBPID_LOCK_NR),
-};
-#endif /* CONFIG_MN10300_TLB_USE_PIDR */
-
-/*
- * preemptively set a TLB entry
- */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
-{
- unsigned long pteu, ptel, cnx, flags;
- pte_t pte = *ptep;
-
- addr &= PAGE_MASK;
- ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2);
-
- /* make sure the context doesn't migrate and defend against
- * interference from vmalloc'd regions */
- local_irq_save(flags);
-
- cnx = ~MMU_NO_CONTEXT;
-#ifdef CONFIG_MN10300_TLB_USE_PIDR
- cnx = mm_context(vma->vm_mm);
-#endif
-
- if (cnx != MMU_NO_CONTEXT) {
- pteu = addr;
-#ifdef CONFIG_MN10300_TLB_USE_PIDR
- pteu |= cnx & MMU_CONTEXT_TLBPID_MASK;
-#endif
- if (!(pte_val(pte) & _PAGE_NX)) {
- IPTEU = pteu;
- if (IPTEL & xPTEL_V)
- IPTEL = ptel;
- }
- DPTEU = pteu;
- if (DPTEL & xPTEL_V)
- DPTEL = ptel;
- }
-
- local_irq_restore(flags);
-}
diff --git a/arch/mn10300/mm/pgtable.c b/arch/mn10300/mm/pgtable.c
deleted file mode 100644
index 9577cf768875..000000000000
--- a/arch/mn10300/mm/pgtable.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* MN10300 Page table management
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Modified by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/gfp.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/smp.h>
-#include <linux/highmem.h>
-#include <linux/pagemap.h>
-#include <linux/spinlock.h>
-#include <linux/quicklist.h>
-
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/tlb.h>
-#include <asm/tlbflush.h>
-
-/*
- * Associate a large virtual page frame with a given physical page frame
- * and protection flags for that frame. pfn is for the base of the page,
- * vaddr is what the page gets mapped to - both must be properly aligned.
- * The pmd must already be instantiated. Assumes PAE mode.
- */
-void set_pmd_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
-
- if (vaddr & (PMD_SIZE-1)) { /* vaddr is misaligned */
- printk(KERN_ERR "set_pmd_pfn: vaddr misaligned\n");
- return; /* BUG(); */
- }
- if (pfn & (PTRS_PER_PTE-1)) { /* pfn is misaligned */
- printk(KERN_ERR "set_pmd_pfn: pfn misaligned\n");
- return; /* BUG(); */
- }
- pgd = swapper_pg_dir + pgd_index(vaddr);
- if (pgd_none(*pgd)) {
- printk(KERN_ERR "set_pmd_pfn: pgd_none\n");
- return; /* BUG(); */
- }
- pud = pud_offset(pgd, vaddr);
- pmd = pmd_offset(pud, vaddr);
- set_pmd(pmd, pfn_pmd(pfn, flags));
- /*
- * It's enough to flush this one mapping.
- * (PGE mappings get flushed as well)
- */
- local_flush_tlb_one(vaddr);
-}
-
-pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL);
- if (pte)
- clear_page(pte);
- return pte;
-}
-
-struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *pte;
-
-#ifdef CONFIG_HIGHPTE
- pte = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM, 0);
-#else
- pte = alloc_pages(GFP_KERNEL, 0);
-#endif
- if (!pte)
- return NULL;
- clear_highpage(pte);
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-/*
- * List of all pgd's needed for non-PAE so it can invalidate entries
- * in both cached and uncached pgd's; not needed for PAE since the
- * kernel pmd is shared. If PAE were not to share the pmd a similar
- * tactic would be needed. This is essentially codepath-based locking
- * against pageattr.c; it is the unique case in which a valid change
- * of kernel pagetables can't be lazily synchronized by vmalloc faults.
- * vmalloc faults work because attached pagetables are never freed.
- * If the locking proves to be non-performant, a ticketing scheme with
- * checks at dup_mmap(), exec(), and other mmlist addition points
- * could be used. The locking scheme was chosen on the basis of
- * manfred's recommendations and having no core impact whatsoever.
- * -- nyc
- */
-DEFINE_SPINLOCK(pgd_lock);
-struct page *pgd_list;
-
-static inline void pgd_list_add(pgd_t *pgd)
-{
- struct page *page = virt_to_page(pgd);
- page->index = (unsigned long) pgd_list;
- if (pgd_list)
- set_page_private(pgd_list, (unsigned long) &page->index);
- pgd_list = page;
- set_page_private(page, (unsigned long) &pgd_list);
-}
-
-static inline void pgd_list_del(pgd_t *pgd)
-{
- struct page *next, **pprev, *page = virt_to_page(pgd);
- next = (struct page *) page->index;
- pprev = (struct page **) page_private(page);
- *pprev = next;
- if (next)
- set_page_private(next, (unsigned long) pprev);
-}
-
-void pgd_ctor(void *pgd)
-{
- unsigned long flags;
-
- if (PTRS_PER_PMD == 1)
- spin_lock_irqsave(&pgd_lock, flags);
-
- memcpy((pgd_t *)pgd + USER_PTRS_PER_PGD,
- swapper_pg_dir + USER_PTRS_PER_PGD,
- (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
-
- if (PTRS_PER_PMD > 1)
- return;
-
- pgd_list_add(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
- memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
-}
-
-/* never called when PTRS_PER_PMD > 1 */
-void pgd_dtor(void *pgd)
-{
- unsigned long flags; /* can be called from interrupt context */
-
- spin_lock_irqsave(&pgd_lock, flags);
- pgd_list_del(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
-}
-
-pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- return quicklist_alloc(0, GFP_KERNEL, pgd_ctor);
-}
-
-void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- quicklist_free(0, pgd_dtor, pgd);
-}
-
-void __init pgtable_cache_init(void)
-{
-}
-
-void check_pgt_cache(void)
-{
- quicklist_trim(0, pgd_dtor, 25, 16);
-}
diff --git a/arch/mn10300/mm/tlb-mn10300.S b/arch/mn10300/mm/tlb-mn10300.S
deleted file mode 100644
index b9940177d81b..000000000000
--- a/arch/mn10300/mm/tlb-mn10300.S
+++ /dev/null
@@ -1,220 +0,0 @@
-###############################################################################
-#
-# TLB loading functions
-#
-# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
-# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
-# Modified by David Howells (dhowells@redhat.com)
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public Licence
-# as published by the Free Software Foundation; either version
-# 2 of the Licence, or (at your option) any later version.
-#
-###############################################################################
-#include <linux/sys.h>
-#include <linux/linkage.h>
-#include <asm/smp.h>
-#include <asm/intctl-regs.h>
-#include <asm/frame.inc>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
-###############################################################################
-#
-# Instruction TLB Miss handler entry point
-#
-###############################################################################
- .type itlb_miss,@function
-ENTRY(itlb_miss)
-#ifdef CONFIG_GDBSTUB
- movm [d2,d3,a2],(sp)
-#else
- or EPSW_nAR,epsw # switch D0-D3 & A0-A3 to the alternate
- # register bank
- nop
- nop
- nop
-#endif
-
-#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR)
- mov (MMUCTR),d2
- mov d2,(MMUCTR)
-#endif
-
- and ~EPSW_NMID,epsw
- mov (IPTEU),d3
- mov (PTBR),a2
- mov d3,d2
- and 0xffc00000,d2
- lsr 20,d2
- mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22]
- btst _PAGE_VALID,a2
- beq itlb_miss_fault # jump if doesn't point anywhere
-
- and ~(PAGE_SIZE-1),a2
- mov d3,d2
- and 0x003ff000,d2
- lsr 10,d2
- add d2,a2
- mov (a2),d2 # get pte from PTD[addr 21..12]
- btst _PAGE_VALID,d2
- beq itlb_miss_fault # jump if doesn't point to a page
- # (might be a swap id)
-#if ((_PAGE_ACCESSED & 0xffffff00) == 0)
- bset _PAGE_ACCESSED,(0,a2)
-#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0)
- bset +(_PAGE_ACCESSED >> 8),(1,a2)
-#else
-#error "_PAGE_ACCESSED value is out of range"
-#endif
- and ~xPTEL2_UNUSED1,d2
-itlb_miss_set:
- mov d2,(IPTEL2) # change the TLB
-#ifdef CONFIG_GDBSTUB
- movm (sp),[d2,d3,a2]
-#endif
- rti
-
-itlb_miss_fault:
- mov _PAGE_VALID,d2 # force address error handler to be
- # invoked
- bra itlb_miss_set
-
- .size itlb_miss, . - itlb_miss
-
-###############################################################################
-#
-# Data TLB Miss handler entry point
-#
-###############################################################################
- .type dtlb_miss,@function
-ENTRY(dtlb_miss)
-#ifdef CONFIG_GDBSTUB
- movm [d2,d3,a2],(sp)
-#else
- or EPSW_nAR,epsw # switch D0-D3 & A0-A3 to the alternate
- # register bank
- nop
- nop
- nop
-#endif
-
-#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR)
- mov (MMUCTR),d2
- mov d2,(MMUCTR)
-#endif
-
- and ~EPSW_NMID,epsw
- mov (DPTEU),d3
- mov (PTBR),a2
- mov d3,d2
- and 0xffc00000,d2
- lsr 20,d2
- mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22]
- btst _PAGE_VALID,a2
- beq dtlb_miss_fault # jump if doesn't point anywhere
-
- and ~(PAGE_SIZE-1),a2
- mov d3,d2
- and 0x003ff000,d2
- lsr 10,d2
- add d2,a2
- mov (a2),d2 # get pte from PTD[addr 21..12]
- btst _PAGE_VALID,d2
- beq dtlb_miss_fault # jump if doesn't point to a page
- # (might be a swap id)
-#if ((_PAGE_ACCESSED & 0xffffff00) == 0)
- bset _PAGE_ACCESSED,(0,a2)
-#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0)
- bset +(_PAGE_ACCESSED >> 8),(1,a2)
-#else
-#error "_PAGE_ACCESSED value is out of range"
-#endif
- and ~xPTEL2_UNUSED1,d2
-dtlb_miss_set:
- mov d2,(DPTEL2) # change the TLB
-#ifdef CONFIG_GDBSTUB
- movm (sp),[d2,d3,a2]
-#endif
- rti
-
-dtlb_miss_fault:
- mov _PAGE_VALID,d2 # force address error handler to be
- # invoked
- bra dtlb_miss_set
- .size dtlb_miss, . - dtlb_miss
-
-###############################################################################
-#
-# Instruction TLB Address Error handler entry point
-#
-###############################################################################
- .type itlb_aerror,@function
-ENTRY(itlb_aerror)
- add -4,sp
- SAVE_ALL
-
-#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR)
- mov (MMUCTR),d1
- mov d1,(MMUCTR)
-#endif
-
- and ~EPSW_NMID,epsw
- add -4,sp # need to pass three params
-
- # calculate the fault code
- movhu (MMUFCR_IFC),d1
- or 0x00010000,d1 # it's an instruction fetch
-
- # determine the page address
- mov (IPTEU),d0
- and PAGE_MASK,d0
- mov d0,(12,sp)
-
- clr d0
- mov d0,(IPTEL2)
-
- or EPSW_IE,epsw
- mov fp,d0
- call do_page_fault[],0 # do_page_fault(regs,code,addr
-
- jmp ret_from_exception
- .size itlb_aerror, . - itlb_aerror
-
-###############################################################################
-#
-# Data TLB Address Error handler entry point
-#
-###############################################################################
- .type dtlb_aerror,@function
-ENTRY(dtlb_aerror)
- add -4,sp
- SAVE_ALL
-
-#if defined(CONFIG_ERRATUM_NEED_TO_RELOAD_MMUCTR)
- mov (MMUCTR),d1
- mov d1,(MMUCTR)
-#endif
-
- add -4,sp # need to pass three params
- and ~EPSW_NMID,epsw
-
- # calculate the fault code
- movhu (MMUFCR_DFC),d1
-
- # determine the page address
- mov (DPTEU),a2
- mov a2,d0
- and PAGE_MASK,d0
- mov d0,(12,sp)
-
- clr d0
- mov d0,(DPTEL2)
-
- or EPSW_IE,epsw
- mov fp,d0
- call do_page_fault[],0 # do_page_fault(regs,code,addr
-
- jmp ret_from_exception
- .size dtlb_aerror, . - dtlb_aerror
diff --git a/arch/mn10300/mm/tlb-smp.c b/arch/mn10300/mm/tlb-smp.c
deleted file mode 100644
index 085f2bb691ac..000000000000
--- a/arch/mn10300/mm/tlb-smp.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* SMP TLB support routines.
- *
- * Copyright (C) 2006-2008 Panasonic Corporation
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/init.h>
-#include <linux/jiffies.h>
-#include <linux/cpumask.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/sched/mm.h>
-#include <linux/profile.h>
-#include <linux/smp.h>
-#include <asm/tlbflush.h>
-#include <asm/bitops.h>
-#include <asm/processor.h>
-#include <asm/bug.h>
-#include <asm/exceptions.h>
-#include <asm/hardirq.h>
-#include <asm/fpu.h>
-#include <asm/mmu_context.h>
-#include <asm/thread_info.h>
-#include <asm/cpu-regs.h>
-#include <asm/intctl-regs.h>
-
-/*
- * For flush TLB
- */
-#define FLUSH_ALL 0xffffffff
-
-static cpumask_t flush_cpumask;
-static struct mm_struct *flush_mm;
-static unsigned long flush_va;
-static DEFINE_SPINLOCK(tlbstate_lock);
-
-DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = {
- &init_mm, 0
-};
-
-static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
- unsigned long va);
-static void do_flush_tlb_all(void *info);
-
-/**
- * smp_flush_tlb - Callback to invalidate the TLB.
- * @unused: Callback context (ignored).
- */
-void smp_flush_tlb(void *unused)
-{
- unsigned long cpu_id;
-
- cpu_id = get_cpu();
-
- if (!cpumask_test_cpu(cpu_id, &flush_cpumask))
- /* This was a BUG() but until someone can quote me the line
- * from the intel manual that guarantees an IPI to multiple
- * CPUs is retried _only_ on the erroring CPUs its staying as a
- * return
- *
- * BUG();
- */
- goto out;
-
- if (flush_va == FLUSH_ALL)
- local_flush_tlb();
- else
- local_flush_tlb_page(flush_mm, flush_va);
-
- smp_mb__before_atomic();
- cpumask_clear_cpu(cpu_id, &flush_cpumask);
- smp_mb__after_atomic();
-out:
- put_cpu();
-}
-
-/**
- * flush_tlb_others - Tell the specified CPUs to invalidate their TLBs
- * @cpumask: The list of CPUs to target.
- * @mm: The VM context to flush from (if va!=FLUSH_ALL).
- * @va: Virtual address to flush or FLUSH_ALL to flush everything.
- */
-static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
- unsigned long va)
-{
- cpumask_t tmp;
-
- /* A couple of sanity checks (to be removed):
- * - mask must not be empty
- * - current CPU must not be in mask
- * - we do not send IPIs to as-yet unbooted CPUs.
- */
- BUG_ON(!mm);
- BUG_ON(cpumask_empty(&cpumask));
- BUG_ON(cpumask_test_cpu(smp_processor_id(), &cpumask));
-
- cpumask_and(&tmp, &cpumask, cpu_online_mask);
- BUG_ON(!cpumask_equal(&cpumask, &tmp));
-
- /* I'm not happy about this global shared spinlock in the MM hot path,
- * but we'll see how contended it is.
- *
- * Temporarily this turns IRQs off, so that lockups are detected by the
- * NMI watchdog.
- */
- spin_lock(&tlbstate_lock);
-
- flush_mm = mm;
- flush_va = va;
-#if NR_CPUS <= BITS_PER_LONG
- atomic_or(cpumask.bits[0], (atomic_t *)&flush_cpumask.bits[0]);
-#else
-#error Not supported.
-#endif
-
- /* FIXME: if NR_CPUS>=3, change send_IPI_mask */
- smp_call_function(smp_flush_tlb, NULL, 1);
-
- while (!cpumask_empty(&flush_cpumask))
- /* Lockup detection does not belong here */
- smp_mb();
-
- flush_mm = NULL;
- flush_va = 0;
- spin_unlock(&tlbstate_lock);
-}
-
-/**
- * flush_tlb_mm - Invalidate TLB of specified VM context
- * @mm: The VM context to invalidate.
- */
-void flush_tlb_mm(struct mm_struct *mm)
-{
- cpumask_t cpu_mask;
-
- preempt_disable();
- cpumask_copy(&cpu_mask, mm_cpumask(mm));
- cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-
- local_flush_tlb();
- if (!cpumask_empty(&cpu_mask))
- flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
-
- preempt_enable();
-}
-
-/**
- * flush_tlb_current_task - Invalidate TLB of current task
- */
-void flush_tlb_current_task(void)
-{
- struct mm_struct *mm = current->mm;
- cpumask_t cpu_mask;
-
- preempt_disable();
- cpumask_copy(&cpu_mask, mm_cpumask(mm));
- cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-
- local_flush_tlb();
- if (!cpumask_empty(&cpu_mask))
- flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
-
- preempt_enable();
-}
-
-/**
- * flush_tlb_page - Invalidate TLB of page
- * @vma: The VM context to invalidate the page for.
- * @va: The virtual address of the page to invalidate.
- */
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
-{
- struct mm_struct *mm = vma->vm_mm;
- cpumask_t cpu_mask;
-
- preempt_disable();
- cpumask_copy(&cpu_mask, mm_cpumask(mm));
- cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-
- local_flush_tlb_page(mm, va);
- if (!cpumask_empty(&cpu_mask))
- flush_tlb_others(cpu_mask, mm, va);
-
- preempt_enable();
-}
-
-/**
- * do_flush_tlb_all - Callback to completely invalidate a TLB
- * @unused: Callback context (ignored).
- */
-static void do_flush_tlb_all(void *unused)
-{
- local_flush_tlb_all();
-}
-
-/**
- * flush_tlb_all - Completely invalidate TLBs on all CPUs
- */
-void flush_tlb_all(void)
-{
- on_each_cpu(do_flush_tlb_all, 0, 1);
-}
diff --git a/arch/mn10300/oprofile/Makefile b/arch/mn10300/oprofile/Makefile
deleted file mode 100644
index 9fa95aaf496b..000000000000
--- a/arch/mn10300/oprofile/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the MN10300-specific profiling code
-#
-obj-$(CONFIG_OPROFILE) += oprofile.o
-
-DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
- oprof.o cpu_buffer.o buffer_sync.o \
- event_buffer.o oprofile_files.o \
- oprofilefs.o oprofile_stats.o \
- timer_int.o )
-
-oprofile-y := $(DRIVER_OBJS) op_model_null.o
-
diff --git a/arch/mn10300/oprofile/op_model_null.c b/arch/mn10300/oprofile/op_model_null.c
deleted file mode 100644
index cd4ab374bc4f..000000000000
--- a/arch/mn10300/oprofile/op_model_null.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Null profiling driver
- *
- * Copyright (C) 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * Licence. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/kernel.h>
-#include <linux/oprofile.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-
-int __init oprofile_arch_init(struct oprofile_operations *ops)
-{
- return -ENODEV;
-}
-
-void oprofile_arch_exit(void)
-{
-}
-
diff --git a/arch/mn10300/proc-mn103e010/Makefile b/arch/mn10300/proc-mn103e010/Makefile
deleted file mode 100644
index ac2c9784cd21..000000000000
--- a/arch/mn10300/proc-mn103e010/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the MN103E010 processor chip specific code
-#
-obj-y := proc-init.o
-
diff --git a/arch/mn10300/proc-mn103e010/include/proc/cache.h b/arch/mn10300/proc-mn103e010/include/proc/cache.h
deleted file mode 100644
index 967d144f307e..000000000000
--- a/arch/mn10300/proc-mn103e010/include/proc/cache.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* MN103E010 Cache specification
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PROC_CACHE_H
-#define _ASM_PROC_CACHE_H
-
-/* L1 cache */
-
-#define L1_CACHE_NWAYS 4 /* number of ways in caches */
-#define L1_CACHE_NENTRIES 256 /* number of entries in each way */
-#define L1_CACHE_BYTES 16 /* bytes per entry */
-#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */
-#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */
-
-#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */
-#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
-#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */
-#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
-#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY)
-
-/*
- * specification of the interval between interrupt checking intervals whilst
- * managing the cache with the interrupts disabled
- */
-#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4
-
-/*
- * The size of range at which it becomes more economical to just flush the
- * whole cache rather than trying to flush the specified range.
- */
-#define MN10300_DCACHE_FLUSH_BORDER \
- +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
-#define MN10300_DCACHE_FLUSH_INV_BORDER \
- +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
-
-#endif /* _ASM_PROC_CACHE_H */
diff --git a/arch/mn10300/proc-mn103e010/include/proc/clock.h b/arch/mn10300/proc-mn103e010/include/proc/clock.h
deleted file mode 100644
index 704a819f1f4b..000000000000
--- a/arch/mn10300/proc-mn103e010/include/proc/clock.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* MN103E010-specific clocks
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_PROC_CLOCK_H
-#define _ASM_PROC_CLOCK_H
-
-#include <unit/clock.h>
-
-#endif /* _ASM_PROC_CLOCK_H */
diff --git a/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h
deleted file mode 100644
index d72d328d1f9c..000000000000
--- a/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* MN103E010 on-board DMA controller registers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROC_DMACTL_REGS_H
-#define _ASM_PROC_DMACTL_REGS_H
-
-#include <asm/cpu-regs.h>
-
-#ifdef __KERNEL__
-
-/* DMA registers */
-#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
-#define DMxCTR_BG 0x0000001f /* transfer request source */
-#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
-#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
-#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
-#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
-#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
-#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
-#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
-#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
-#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
-#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
-#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
-#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
-#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */
-#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */
-#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */
-#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */
-#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */
-#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */
-#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */
-#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */
-#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */
-#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
-#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
-#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
-#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */
-#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
-#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
-#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
-#define DMxCTR_TM 0x00001800 /* DMA transfer mode */
-#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */
-#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */
-#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
-#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
-#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
-#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
-#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
-#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
-#define DMxCTR_RQM 0x00060000 /* external request input source mode */
-#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
-#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
-#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
-#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
-#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
-#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
-
-#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
-
-#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
-
-#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
-#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
-
-#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
- * size reg */
-#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
-
-#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
-#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
-#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
-#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
-
-#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
-#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
-#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
-#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
-
-#ifndef __ASSEMBLY__
-
-struct mn10300_dmactl_regs {
- u32 ctr;
- const void *src;
- void *dst;
- u32 siz;
- u32 cyc;
-} __attribute__((aligned(0x100)));
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_PROC_DMACTL_REGS_H */
diff --git a/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h b/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h
deleted file mode 100644
index 516afe824055..000000000000
--- a/arch/mn10300/proc-mn103e010/include/proc/intctl-regs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_PROC_INTCTL_REGS_H
-#define _ASM_PROC_INTCTL_REGS_H
-
-#ifndef _ASM_INTCTL_REGS_H
-# error "please don't include this file directly"
-#endif
-
-/* intr acceptance group reg */
-#define IAGR __SYSREG(0xd4000100, u16)
-
-/* group number register */
-#define IAGR_GN 0x00fc
-
-#define __GET_XIRQ_TRIGGER(X, Z) (((Z) >> ((X) * 2)) & 3)
-
-#define __SET_XIRQ_TRIGGER(X, Y, Z) \
-({ \
- typeof(Z) x = (Z); \
- x &= ~(3 << ((X) * 2)); \
- x |= ((Y) & 3) << ((X) * 2); \
- (Z) = x; \
-})
-
-/* external pin intr spec reg */
-#define EXTMD __SYSREG(0xd4000200, u16)
-#define GET_XIRQ_TRIGGER(X) __GET_XIRQ_TRIGGER(X, EXTMD)
-#define SET_XIRQ_TRIGGER(X, Y) __SET_XIRQ_TRIGGER(X, Y, EXTMD)
-
-#endif /* _ASM_PROC_INTCTL_REGS_H */
diff --git a/arch/mn10300/proc-mn103e010/include/proc/irq.h b/arch/mn10300/proc-mn103e010/include/proc/irq.h
deleted file mode 100644
index aa6ee8f98b1b..000000000000
--- a/arch/mn10300/proc-mn103e010/include/proc/irq.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* MN103E010 On-board interrupt controller numbers
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROC_IRQ_H
-#define _ASM_PROC_IRQ_H
-
-#ifdef __KERNEL__
-
-#define GxICR_NUM_IRQS 42
-
-#define GxICR_NUM_XIRQS 8
-
-#define XIRQ0 34
-#define XIRQ1 35
-#define XIRQ2 36
-#define XIRQ3 37
-#define XIRQ4 38
-#define XIRQ5 39
-#define XIRQ6 40
-#define XIRQ7 41
-
-#define XIRQ2IRQ(num) (XIRQ0 + num)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_PROC_IRQ_H */
diff --git a/arch/mn10300/proc-mn103e010/include/proc/proc.h b/arch/mn10300/proc-mn103e010/include/proc/proc.h
deleted file mode 100644
index 39c4f8e7d2d3..000000000000
--- a/arch/mn10300/proc-mn103e010/include/proc/proc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* MN103E010 Processor description
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROC_PROC_H
-#define _ASM_PROC_PROC_H
-
-#define PROCESSOR_VENDOR_NAME "Panasonic"
-#define PROCESSOR_MODEL_NAME "mn103e010"
-
-#endif /* _ASM_PROC_PROC_H */
diff --git a/arch/mn10300/proc-mn103e010/proc-init.c b/arch/mn10300/proc-mn103e010/proc-init.c
deleted file mode 100644
index 102d86a6ae56..000000000000
--- a/arch/mn10300/proc-mn103e010/proc-init.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* MN103E010 Processor initialisation
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <asm/cacheflush.h>
-#include <asm/fpu.h>
-#include <asm/irq.h>
-#include <asm/rtc.h>
-#include <asm/busctl-regs.h>
-
-/*
- * initialise the on-silicon processor peripherals
- */
-asmlinkage void __init processor_init(void)
-{
- int loop;
-
- /* set up the exception table first */
- for (loop = 0x000; loop < 0x400; loop += 8)
- __set_intr_stub(loop, __common_exception);
-
- __set_intr_stub(EXCEP_ITLBMISS, itlb_miss);
- __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss);
- __set_intr_stub(EXCEP_IAERROR, itlb_aerror);
- __set_intr_stub(EXCEP_DAERROR, dtlb_aerror);
- __set_intr_stub(EXCEP_BUSERROR, raw_bus_error);
- __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault);
- __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled);
- __set_intr_stub(EXCEP_SYSCALL0, system_call);
-
- __set_intr_stub(EXCEP_NMI, nmi_handler);
- __set_intr_stub(EXCEP_WDT, nmi_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler);
-
- IVAR0 = EXCEP_IRQ_LEVEL0;
- IVAR1 = EXCEP_IRQ_LEVEL1;
- IVAR2 = EXCEP_IRQ_LEVEL2;
- IVAR3 = EXCEP_IRQ_LEVEL3;
- IVAR4 = EXCEP_IRQ_LEVEL4;
- IVAR5 = EXCEP_IRQ_LEVEL5;
- IVAR6 = EXCEP_IRQ_LEVEL6;
-
- mn10300_dcache_flush_inv();
- mn10300_icache_inv();
-
- /* disable all interrupts and set to priority 6 (lowest) */
- for (loop = 0; loop < NR_IRQS; loop++)
- GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
-
- /* clear the timers */
- TM0MD = 0;
- TM1MD = 0;
- TM2MD = 0;
- TM3MD = 0;
- TM4MD = 0;
- TM5MD = 0;
- TM6MD = 0;
- TM6MDA = 0;
- TM6MDB = 0;
- TM7MD = 0;
- TM8MD = 0;
- TM9MD = 0;
- TM10MD = 0;
- TM11MD = 0;
-
- calibrate_clock();
-}
-
-/*
- * determine the memory size and base from the memory controller regs
- */
-void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size)
-{
- unsigned long base, size;
-
- *mem_base = 0;
- *mem_size = 0;
-
- base = SDBASE(0);
- if (base & SDBASE_CE) {
- size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
- size = ~size + 1;
- base &= SDBASE_CBA;
-
- printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base);
- *mem_size += size;
- *mem_base = base;
- }
-
- base = SDBASE(1);
- if (base & SDBASE_CE) {
- size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
- size = ~size + 1;
- base &= SDBASE_CBA;
-
- printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base);
- *mem_size += size;
- if (*mem_base == 0)
- *mem_base = base;
- }
-}
diff --git a/arch/mn10300/proc-mn2ws0050/Makefile b/arch/mn10300/proc-mn2ws0050/Makefile
deleted file mode 100644
index d4ca13309a85..000000000000
--- a/arch/mn10300/proc-mn2ws0050/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := proc-init.o
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h
deleted file mode 100644
index bcb5df2d892f..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Cache specification
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * Modified by Matsushita Electric Industrial Co., Ltd.
- * Modifications:
- * 13-Nov-2006 MEI Add L1_CACHE_SHIFT_MAX definition.
- * 29-Jul-2008 MEI Add define for MN10300_HAS_AREAPURGE_REG.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_PROC_CACHE_H
-#define _ASM_PROC_CACHE_H
-
-/*
- * L1 cache
- */
-#define L1_CACHE_NWAYS 4 /* number of ways in caches */
-#define L1_CACHE_NENTRIES 128 /* number of entries in each way */
-#define L1_CACHE_BYTES 32 /* bytes per entry */
-#define L1_CACHE_SHIFT 5 /* shift for bytes per entry */
-#define L1_CACHE_WAYDISP 0x1000 /* distance from one way to the next */
-
-#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */
-#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
-#define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */
-#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
-#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY)
-
-/*
- * specification of the interval between interrupt checking intervals whilst
- * managing the cache with the interrupts disabled
- */
-#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4
-
-/*
- * The size of range at which it becomes more economical to just flush the
- * whole cache rather than trying to flush the specified range.
- */
-#define MN10300_DCACHE_FLUSH_BORDER \
- +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
-#define MN10300_DCACHE_FLUSH_INV_BORDER \
- +(L1_CACHE_NWAYS * L1_CACHE_NENTRIES * L1_CACHE_BYTES)
-
-#endif /* _ASM_PROC_CACHE_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/clock.h b/arch/mn10300/proc-mn2ws0050/include/proc/clock.h
deleted file mode 100644
index fe4c0a4a53a2..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/clock.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* clock.h: proc-specific clocks
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * Modified by Matsushita Electric Industrial Co., Ltd.
- * Modifications:
- * 23-Feb-2007 MEI Delete define for watchdog timer.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_PROC_CLOCK_H
-#define _ASM_PROC_CLOCK_H
-
-#include <unit/clock.h>
-
-#endif /* _ASM_PROC_CLOCK_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h
deleted file mode 100644
index 4c4319e241d1..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/dmactl-regs.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* MN2WS0050 on-board DMA controller registers
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- */
-
-#ifndef _ASM_PROC_DMACTL_REGS_H
-#define _ASM_PROC_DMACTL_REGS_H
-
-#include <asm/cpu-regs.h>
-
-#ifdef __KERNEL__
-
-/* DMA registers */
-#define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */
-#define DMxCTR_BG 0x0000001f /* transfer request source */
-#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
-#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
-#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
-#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
-#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
-#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
-#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
-#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
-#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
-#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
-#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
-#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
-#define DMxCTR_BG_RYBY 0x0000000d /* - NAND Flash RY/BY request source */
-#define DMxCTR_BG_RMC 0x0000000e /* - remote controller output */
-#define DMxCTR_BG_XIRQ12 0x00000011 /* - XIRQ12 pin interrupt source */
-#define DMxCTR_BG_XIRQ13 0x00000012 /* - XIRQ13 pin interrupt source */
-#define DMxCTR_BG_TCK 0x00000014 /* - tick timer underflow */
-#define DMxCTR_BG_SC4TX 0x00000019 /* - serial port4 transmission */
-#define DMxCTR_BG_SC4RX 0x0000001a /* - serial port4 reception */
-#define DMxCTR_BG_SC5TX 0x0000001b /* - serial port5 transmission */
-#define DMxCTR_BG_SC5RX 0x0000001c /* - serial port5 reception */
-#define DMxCTR_BG_SC6TX 0x0000001d /* - serial port6 transmission */
-#define DMxCTR_BG_SC6RX 0x0000001e /* - serial port6 reception */
-#define DMxCTR_BG_TMSUFLOW 0x0000001f /* - timestamp timer underflow */
-#define DMxCTR_SAM 0x00000060 /* DMA transfer src addr mode */
-#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
-#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
-#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
-#define DMxCTR_DAM 0x00000300 /* DMA transfer dest addr mode */
-#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
-#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
-#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
-#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
-#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
-#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
-#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
-#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
-#define DMxCTR_RRE 0x00008000 /* DMA round robin enable */
-#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
-#define DMxCTR_RQM 0x00060000 /* external request input source mode */
-#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
-#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
-#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
-#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
-#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
-#define DMxCTR_PERR 0x40000000 /* DMA transfer parameter error flag */
-#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
-
-#define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */
-
-#define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */
-
-#define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */
-#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
-
-#define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */
-#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
-
-#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
-#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
-#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
-#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
-
-#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
-#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
-#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
-#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
-
-#ifndef __ASSEMBLY__
-
-struct mn10300_dmactl_regs {
- u32 ctr;
- const void *src;
- void *dst;
- u32 siz;
- u32 cyc;
-} __attribute__((aligned(0x100)));
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_PROC_DMACTL_REGS_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h
deleted file mode 100644
index 4d4084ea6694..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/intctl-regs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_PROC_INTCTL_REGS_H
-#define _ASM_PROC_INTCTL_REGS_H
-
-#ifndef _ASM_INTCTL_REGS_H
-# error "please don't include this file directly"
-#endif
-
-/* intr acceptance group reg */
-#define IAGR __SYSREG(0xd4000100, u16)
-
-/* group number register */
-#define IAGR_GN 0x003fc
-
-#define __GET_XIRQ_TRIGGER(X, Z) (((Z) >> ((X) * 2)) & 3)
-
-#define __SET_XIRQ_TRIGGER(X, Y, Z) \
-({ \
- typeof(Z) x = (Z); \
- x &= ~(3 << ((X) * 2)); \
- x |= ((Y) & 3) << ((X) * 2); \
- (Z) = x; \
-})
-
-/* external pin intr spec reg */
-#define EXTMD0 __SYSREG(0xd4000200, u32)
-#define GET_XIRQ_TRIGGER(X) __GET_XIRQ_TRIGGER(X, EXTMD0)
-#define SET_XIRQ_TRIGGER(X, Y) __SET_XIRQ_TRIGGER(X, Y, EXTMD0)
-
-#endif /* _ASM_PROC_INTCTL_REGS_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/irq.h b/arch/mn10300/proc-mn2ws0050/include/proc/irq.h
deleted file mode 100644
index 37777a85ab6f..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/irq.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* MN2WS0050 on-board interrupt controller registers
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * Modified by Matsushita Electric Industrial Co., Ltd.
- * Modifications:
- * 13-Nov-2006 MEI Define extended IRQ number for SMP support.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _PROC_IRQ_H
-#define _PROC_IRQ_H
-
-#ifdef __KERNEL__
-
-#define GxICR_NUM_IRQS 163
-#ifdef CONFIG_SMP
-#define GxICR_NUM_EXT_IRQS 197
-#endif /* CONFIG_SMP */
-
-#define GxICR_NUM_XIRQS 16
-
-#define XIRQ0 34
-#define XIRQ1 35
-#define XIRQ2 36
-#define XIRQ3 37
-#define XIRQ4 38
-#define XIRQ5 39
-#define XIRQ6 40
-#define XIRQ7 41
-#define XIRQ8 42
-#define XIRQ9 43
-#define XIRQ10 44
-#define XIRQ11 45
-#define XIRQ12 46
-#define XIRQ13 47
-#define XIRQ14 48
-#define XIRQ15 49
-
-#define XIRQ2IRQ(num) (XIRQ0 + num)
-
-#endif /* __KERNEL__ */
-
-#endif /* _PROC_IRQ_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h
deleted file mode 100644
index 84448f3828b3..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* NAND flash interface register definitions
- *
- * Copyright (C) 2008-2009 Panasonic Corporation
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _PROC_NAND_REGS_H_
-#define _PROC_NAND_REGS_H_
-
-/* command register */
-#define FCOMMAND_0 __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */
-#define FCOMMAND_1 __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */
-#define FCOMMAND_2 __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */
-#define FCOMMAND_3 __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */
-
-/* for dma 16 byte trans, use FCOMMAND2 register */
-#define FCOMMAND2_0 __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */
-#define FCOMMAND2_1 __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */
-#define FCOMMAND2_2 __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */
-#define FCOMMAND2_3 __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */
-
-#define FCOMMAND_FIEN 0x80 /* nand flash I/F enable */
-#define FCOMMAND_BW_8BIT 0x00 /* 8bit bus width */
-#define FCOMMAND_BW_16BIT 0x40 /* 16bit bus width */
-#define FCOMMAND_BLOCKSZ_SMALL 0x00 /* small block */
-#define FCOMMAND_BLOCKSZ_LARGE 0x20 /* large block */
-#define FCOMMAND_DMASTART 0x10 /* dma start */
-#define FCOMMAND_RYBY 0x08 /* ready/busy flag */
-#define FCOMMAND_RYBYINTMSK 0x04 /* mask ready/busy interrupt */
-#define FCOMMAND_XFWP 0x02 /* write protect enable */
-#define FCOMMAND_XFCE 0x01 /* flash device disable */
-#define FCOMMAND_SEQKILL 0x10 /* stop seq-read */
-#define FCOMMAND_ANUM 0x07 /* address cycle */
-#define FCOMMAND_ANUM_NONE 0x00 /* address cycle none */
-#define FCOMMAND_ANUM_1CYC 0x01 /* address cycle 1cycle */
-#define FCOMMAND_ANUM_2CYC 0x02 /* address cycle 2cycle */
-#define FCOMMAND_ANUM_3CYC 0x03 /* address cycle 3cycle */
-#define FCOMMAND_ANUM_4CYC 0x04 /* address cycle 4cycle */
-#define FCOMMAND_ANUM_5CYC 0x05 /* address cycle 5cycle */
-#define FCOMMAND_FCMD_READ0 0x00 /* read1 command */
-#define FCOMMAND_FCMD_SEQIN 0x80 /* page program 1st command */
-#define FCOMMAND_FCMD_PAGEPROG 0x10 /* page program 2nd command */
-#define FCOMMAND_FCMD_RESET 0xff /* reset command */
-#define FCOMMAND_FCMD_ERASE1 0x60 /* erase 1st command */
-#define FCOMMAND_FCMD_ERASE2 0xd0 /* erase 2nd command */
-#define FCOMMAND_FCMD_STATUS 0x70 /* read status command */
-#define FCOMMAND_FCMD_READID 0x90 /* read id command */
-#define FCOMMAND_FCMD_READOOB 0x50 /* read3 command */
-/* address register */
-#define FADD __SYSREG(0xd8f00004, u32)
-/* address register 2 */
-#define FADD2 __SYSREG(0xd8f00008, u32)
-/* error judgement register */
-#define FJUDGE __SYSREG(0xd8f0000c, u32)
-#define FJUDGE_NOERR 0x0 /* no error */
-#define FJUDGE_1BITERR 0x1 /* 1bit error in data area */
-#define FJUDGE_PARITYERR 0x2 /* parity error */
-#define FJUDGE_UNCORRECTABLE 0x3 /* uncorrectable error */
-#define FJUDGE_ERRJDG_MSK 0x3 /* mask of judgement result */
-/* 1st ECC store register */
-#define FECC11 __SYSREG(0xd8f00010, u32)
-/* 2nd ECC store register */
-#define FECC12 __SYSREG(0xd8f00014, u32)
-/* 3rd ECC store register */
-#define FECC21 __SYSREG(0xd8f00018, u32)
-/* 4th ECC store register */
-#define FECC22 __SYSREG(0xd8f0001c, u32)
-/* 5th ECC store register */
-#define FECC31 __SYSREG(0xd8f00020, u32)
-/* 6th ECC store register */
-#define FECC32 __SYSREG(0xd8f00024, u32)
-/* 7th ECC store register */
-#define FECC41 __SYSREG(0xd8f00028, u32)
-/* 8th ECC store register */
-#define FECC42 __SYSREG(0xd8f0002c, u32)
-/* data register */
-#define FDATA __SYSREG(0xd8f00030, u32)
-/* access pulse register */
-#define FPWS __SYSREG(0xd8f00100, u32)
-#define FPWS_PWS1W_2CLK 0x00000000 /* write pulse width 1clock */
-#define FPWS_PWS1W_3CLK 0x01000000 /* write pulse width 2clock */
-#define FPWS_PWS1W_4CLK 0x02000000 /* write pulse width 4clock */
-#define FPWS_PWS1W_5CLK 0x03000000 /* write pulse width 5clock */
-#define FPWS_PWS1W_6CLK 0x04000000 /* write pulse width 6clock */
-#define FPWS_PWS1W_7CLK 0x05000000 /* write pulse width 7clock */
-#define FPWS_PWS1W_8CLK 0x06000000 /* write pulse width 8clock */
-#define FPWS_PWS1R_3CLK 0x00010000 /* read pulse width 3clock */
-#define FPWS_PWS1R_4CLK 0x00020000 /* read pulse width 4clock */
-#define FPWS_PWS1R_5CLK 0x00030000 /* read pulse width 5clock */
-#define FPWS_PWS1R_6CLK 0x00040000 /* read pulse width 6clock */
-#define FPWS_PWS1R_7CLK 0x00050000 /* read pulse width 7clock */
-#define FPWS_PWS1R_8CLK 0x00060000 /* read pulse width 8clock */
-#define FPWS_PWS2W_2CLK 0x00000100 /* write pulse interval 2clock */
-#define FPWS_PWS2W_3CLK 0x00000200 /* write pulse interval 3clock */
-#define FPWS_PWS2W_4CLK 0x00000300 /* write pulse interval 4clock */
-#define FPWS_PWS2W_5CLK 0x00000400 /* write pulse interval 5clock */
-#define FPWS_PWS2W_6CLK 0x00000500 /* write pulse interval 6clock */
-#define FPWS_PWS2R_2CLK 0x00000001 /* read pulse interval 2clock */
-#define FPWS_PWS2R_3CLK 0x00000002 /* read pulse interval 3clock */
-#define FPWS_PWS2R_4CLK 0x00000003 /* read pulse interval 4clock */
-#define FPWS_PWS2R_5CLK 0x00000004 /* read pulse interval 5clock */
-#define FPWS_PWS2R_6CLK 0x00000005 /* read pulse interval 6clock */
-/* command register 2 */
-#define FCOMMAND2 __SYSREG(0xd8f00110, u32)
-/* transfer frequency register */
-#define FNUM __SYSREG(0xd8f00114, u32)
-#define FSDATA_ADDR 0xd8f00400
-/* active data register */
-#define FSDATA __SYSREG(FSDATA_ADDR, u32)
-
-#endif /* _PROC_NAND_REGS_H_ */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/proc.h b/arch/mn10300/proc-mn2ws0050/include/proc/proc.h
deleted file mode 100644
index 90d5cadd05bd..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/proc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* proc.h: MN2WS0050 processor description
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROC_PROC_H
-#define _ASM_PROC_PROC_H
-
-#define PROCESSOR_VENDOR_NAME "Panasonic"
-#define PROCESSOR_MODEL_NAME "mn2ws0050"
-
-#endif /* _ASM_PROC_PROC_H */
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h b/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h
deleted file mode 100644
index 22f277fbb4de..000000000000
--- a/arch/mn10300/proc-mn2ws0050/include/proc/smp-regs.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* MN10300/AM33v2 Microcontroller SMP registers
- *
- * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd.
- * All Rights Reserved.
- * Created:
- * 13-Nov-2006 MEI Add extended cache and atomic operation register
- * for SMP support.
- * 23-Feb-2007 MEI Add define for gdbstub SMP.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_PROC_SMP_REGS_H
-#define _ASM_PROC_SMP_REGS_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-#include <asm/cpu-regs.h>
-
-/*
- * Reference to the interrupt controllers of other CPUs
- */
-#define CROSS_ICR_CPU_SHIFT 16
-
-#define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
- ((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16)
-#define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \
- (((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8)
-
-/* CPU ID register */
-#define CPUID __SYSREGC(0xc0000054, u32)
-#define CPUID_MASK 0x00000007 /* CPU ID mask */
-
-/* extended cache control register */
-#define ECHCTR __SYSREG(0xc0000c20, u32)
-#define ECHCTR_IBCM 0x00000001 /* instruction cache broad cast mask */
-#define ECHCTR_DBCM 0x00000002 /* data cache broad cast mask */
-#define ECHCTR_ISPM 0x00000004 /* instruction cache snoop mask */
-#define ECHCTR_DSPM 0x00000008 /* data cache snoop mask */
-
-#define NMIAGR __SYSREG(0xd400013c, u16)
-#define NMIAGR_GN 0x03fc
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_PROC_SMP_REGS_H */
diff --git a/arch/mn10300/proc-mn2ws0050/proc-init.c b/arch/mn10300/proc-mn2ws0050/proc-init.c
deleted file mode 100644
index 25b1b453c515..000000000000
--- a/arch/mn10300/proc-mn2ws0050/proc-init.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* MN2WS0050 processor initialisation
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-
-#include <asm/cacheflush.h>
-#include <asm/processor.h>
-#include <linux/uaccess.h>
-#include <asm/io.h>
-#include <linux/atomic.h>
-#include <asm/smp.h>
-#include <asm/pgalloc.h>
-#include <asm/busctl-regs.h>
-#include <unit/timex.h>
-#include <asm/fpu.h>
-#include <asm/rtc.h>
-
-#define MEMCONF __SYSREGC(0xdf800400, u32)
-
-/*
- * initialise the on-silicon processor peripherals
- */
-asmlinkage void __init processor_init(void)
-{
- int loop;
-
- /* set up the exception table first */
- for (loop = 0x000; loop < 0x400; loop += 8)
- __set_intr_stub(loop, __common_exception);
-
- __set_intr_stub(EXCEP_ITLBMISS, itlb_miss);
- __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss);
- __set_intr_stub(EXCEP_IAERROR, itlb_aerror);
- __set_intr_stub(EXCEP_DAERROR, dtlb_aerror);
- __set_intr_stub(EXCEP_BUSERROR, raw_bus_error);
- __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault);
- __set_intr_stub(EXCEP_FPU_DISABLED, fpu_disabled);
- __set_intr_stub(EXCEP_SYSCALL0, system_call);
-
- __set_intr_stub(EXCEP_NMI, nmi_handler);
- __set_intr_stub(EXCEP_WDT, nmi_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler);
- __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler);
-
- IVAR0 = EXCEP_IRQ_LEVEL0;
- IVAR1 = EXCEP_IRQ_LEVEL1;
- IVAR2 = EXCEP_IRQ_LEVEL2;
- IVAR3 = EXCEP_IRQ_LEVEL3;
- IVAR4 = EXCEP_IRQ_LEVEL4;
- IVAR5 = EXCEP_IRQ_LEVEL5;
- IVAR6 = EXCEP_IRQ_LEVEL6;
-
-#ifndef CONFIG_MN10300_HAS_CACHE_SNOOP
- mn10300_dcache_flush_inv();
- mn10300_icache_inv();
-#endif
-
- /* disable all interrupts and set to priority 6 (lowest) */
-#ifdef CONFIG_SMP
- for (loop = 0; loop < GxICR_NUM_IRQS; loop++)
- GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
-#else /* !CONFIG_SMP */
- for (loop = 0; loop < NR_IRQS; loop++)
- GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
-#endif /* !CONFIG_SMP */
-
- /* clear the timers */
- TM0MD = 0;
- TM1MD = 0;
- TM2MD = 0;
- TM3MD = 0;
- TM4MD = 0;
- TM5MD = 0;
- TM6MD = 0;
- TM6MDA = 0;
- TM6MDB = 0;
- TM7MD = 0;
- TM8MD = 0;
- TM9MD = 0;
- TM10MD = 0;
- TM11MD = 0;
- TM12MD = 0;
- TM13MD = 0;
- TM14MD = 0;
- TM15MD = 0;
-
- calibrate_clock();
-}
-
-/*
- * determine the memory size and base from the memory controller regs
- */
-void __init get_mem_info(unsigned long *mem_base, unsigned long *mem_size)
-{
- unsigned long memconf = MEMCONF;
- unsigned long size = 0; /* order: MByte */
-
- *mem_base = 0x90000000; /* fixed address */
-
- switch (memconf & 0x00000003) {
- case 0x01:
- size = 256 / 8; /* 256 Mbit per chip */
- break;
- case 0x02:
- size = 512 / 8; /* 512 Mbit per chip */
- break;
- case 0x03:
- size = 1024 / 8; /* 1 Gbit per chip */
- break;
- default:
- panic("Invalid SDRAM size");
- break;
- }
-
- printk(KERN_INFO "DDR2-SDRAM: %luMB x 2 @%08lx\n", size, *mem_base);
-
- *mem_size = (size * 2) << 20;
-}
diff --git a/arch/mn10300/unit-asb2303/Makefile b/arch/mn10300/unit-asb2303/Makefile
deleted file mode 100644
index 38a5bb43b0bb..000000000000
--- a/arch/mn10300/unit-asb2303/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-###############################################################################
-#
-# Makefile for the ASB2303 board
-#
-###############################################################################
-obj-y := unit-init.o smc91111.o flash.o leds.o
diff --git a/arch/mn10300/unit-asb2303/flash.c b/arch/mn10300/unit-asb2303/flash.c
deleted file mode 100644
index b03d8738d67c..000000000000
--- a/arch/mn10300/unit-asb2303/flash.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Handle mapping of the flash on the ASB2303 board
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-
-#define ASB2303_PROM_ADDR 0xA0000000 /* Boot PROM */
-#define ASB2303_PROM_SIZE (2 * 1024 * 1024)
-#define ASB2303_FLASH_ADDR 0xA4000000 /* System Flash */
-#define ASB2303_FLASH_SIZE (32 * 1024 * 1024)
-#define ASB2303_CONFIG_ADDR 0xA6000000 /* System Config EEPROM */
-#define ASB2303_CONFIG_SIZE (8 * 1024)
-
-/*
- * default MTD partition table for both main flash devices, expected to be
- * overridden by RedBoot
- */
-static struct mtd_partition asb2303_partitions[] = {
- {
- .name = "Bootloader",
- .size = 0x00040000,
- .offset = 0,
- .mask_flags = MTD_CAP_ROM /* force read-only */
- }, {
- .name = "Kernel",
- .size = 0x00400000,
- .offset = 0x00040000,
- }, {
- .name = "Filesystem",
- .size = MTDPART_SIZ_FULL,
- .offset = 0x00440000
- }
-};
-
-/*
- * the ASB2303 Boot PROM definition
- */
-static struct physmap_flash_data asb2303_bootprom_data = {
- .width = 2,
- .nr_parts = 1,
- .parts = asb2303_partitions,
-};
-
-static struct resource asb2303_bootprom_resource = {
- .start = ASB2303_PROM_ADDR,
- .end = ASB2303_PROM_ADDR + ASB2303_PROM_SIZE,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device asb2303_bootprom = {
- .name = "physmap-flash",
- .id = 0,
- .dev.platform_data = &asb2303_bootprom_data,
- .num_resources = 1,
- .resource = &asb2303_bootprom_resource,
-};
-
-/*
- * the ASB2303 System Flash definition
- */
-static struct physmap_flash_data asb2303_sysflash_data = {
- .width = 4,
- .nr_parts = 1,
- .parts = asb2303_partitions,
-};
-
-static struct resource asb2303_sysflash_resource = {
- .start = ASB2303_FLASH_ADDR,
- .end = ASB2303_FLASH_ADDR + ASB2303_FLASH_SIZE,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device asb2303_sysflash = {
- .name = "physmap-flash",
- .id = 1,
- .dev.platform_data = &asb2303_sysflash_data,
- .num_resources = 1,
- .resource = &asb2303_sysflash_resource,
-};
-
-/*
- * register the ASB2303 flashes
- */
-static int __init asb2303_mtd_init(void)
-{
- platform_device_register(&asb2303_bootprom);
- platform_device_register(&asb2303_sysflash);
- return 0;
-}
-device_initcall(asb2303_mtd_init);
diff --git a/arch/mn10300/unit-asb2303/include/unit/clock.h b/arch/mn10300/unit-asb2303/include/unit/clock.h
deleted file mode 100644
index 0316907a012e..000000000000
--- a/arch/mn10300/unit-asb2303/include/unit/clock.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* ASB2303-specific clocks
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_CLOCK_H
-#define _ASM_UNIT_CLOCK_H
-
-#ifndef __ASSEMBLY__
-
-#define MN10300_IOCLK 33333333UL
-/* #define MN10300_IOBCLK 66666666UL */
-
-#endif /* !__ASSEMBLY__ */
-
-#define MN10300_WDCLK MN10300_IOCLK
-
-#endif /* _ASM_UNIT_CLOCK_H */
diff --git a/arch/mn10300/unit-asb2303/include/unit/leds.h b/arch/mn10300/unit-asb2303/include/unit/leds.h
deleted file mode 100644
index 3a7543ea7b5c..000000000000
--- a/arch/mn10300/unit-asb2303/include/unit/leds.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* ASB2303-specific LEDs
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_LEDS_H
-#define _ASM_UNIT_LEDS_H
-
-#include <asm/pio-regs.h>
-#include <asm/cpu-regs.h>
-#include <asm/exceptions.h>
-
-#define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32)
-#define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32)
-
-/*
- * use the 7-segment LEDs to indicate states
- */
-
-/* flip the 7-segment LEDs between "G" and "-" */
-#define mn10300_set_gdbleds(ONOFF) \
-do { \
- ASB2303_7SEGLEDS = (ONOFF) ? 0x85 : 0x7f; \
-} while (0)
-
-/* indicate double-fault by displaying "d" on the LEDs */
-#define mn10300_set_dbfleds \
- mov 0x43,d0 ; \
- movbu d0,(ASB2303_7SEGLEDS)
-
-#ifndef __ASSEMBLY__
-extern void peripheral_leds_display_exception(enum exception_code code);
-extern void peripheral_leds_led_chase(void);
-extern void debug_to_serial(const char *p, int n);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_UNIT_LEDS_H */
diff --git a/arch/mn10300/unit-asb2303/include/unit/serial.h b/arch/mn10300/unit-asb2303/include/unit/serial.h
deleted file mode 100644
index 991e356bac5f..000000000000
--- a/arch/mn10300/unit-asb2303/include/unit/serial.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* ASB2303-specific 8250 serial ports
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_SERIAL_H
-#define _ASM_UNIT_SERIAL_H
-
-#include <asm/cpu-regs.h>
-#include <proc/irq.h>
-#include <linux/serial_reg.h>
-
-#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000
-#define SERIAL_PORT1_BASE_ADDRESS 0xA6FC0000
-
-#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */
-
-/*
- * The ASB2303 has an 18.432 MHz clock the UART
- */
-#define BASE_BAUD (18432000 / 16)
-
-/*
- * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports
- */
-#ifndef CONFIG_GDBSTUB_ON_TTYSx
-
-#define SERIAL_PORT_DFNS \
- { \
- .baud_base = BASE_BAUD, \
- .irq = SERIAL_IRQ, \
- .flags = STD_COM_FLAGS, \
- .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \
- .iomem_reg_shift = 2, \
- .io_type = SERIAL_IO_MEM, \
- }, \
- { \
- .baud_base = BASE_BAUD, \
- .irq = SERIAL_IRQ, \
- .flags = STD_COM_FLAGS, \
- .iomem_base = (u8 *) SERIAL_PORT1_BASE_ADDRESS, \
- .iomem_reg_shift = 2, \
- .io_type = SERIAL_IO_MEM, \
- },
-
-#ifndef __ASSEMBLY__
-
-static inline void __debug_to_serial(const char *p, int n)
-{
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#else /* CONFIG_GDBSTUB_ON_TTYSx */
-
-#define SERIAL_PORT_DFNS /* both stolen by gdb-stub because they share an IRQ */
-
-#if defined(CONFIG_GDBSTUB_ON_TTYS0)
-#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
-#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
-#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
-#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
-#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
-#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
-#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
-#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
-#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
-#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
-#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
-#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8)
-#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
-
-#elif defined(CONFIG_GDBSTUB_ON_TTYS1)
-#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_RX * 4, u8)
-#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_TX * 4, u8)
-#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLL * 4, u8)
-#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLM * 4, u8)
-#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IER * 4, u8)
-#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IIR * 4, u8)
-#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_FCR * 4, u8)
-#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LCR * 4, u8)
-#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MCR * 4, u8)
-#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LSR * 4, u8)
-#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MSR * 4, u8)
-#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_SCR * 4, u8)
-#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
-#endif
-
-#ifndef __ASSEMBLY__
-
-#define LSR_WAIT_FOR(STATE) \
-do { \
- while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE)) {} \
-} while (0)
-#define FLOWCTL_WAIT_FOR(LINE) \
-do { \
- while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) {} \
-} while (0)
-#define FLOWCTL_CLEAR(LINE) \
-do { \
- GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; \
-} while (0)
-#define FLOWCTL_SET(LINE) \
-do { \
- GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; \
-} while (0)
-#define FLOWCTL_QUERY(LINE) ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; })
-
-static inline void __debug_to_serial(const char *p, int n)
-{
- char ch;
-
- FLOWCTL_SET(DTR);
-
- for (; n > 0; n--) {
- LSR_WAIT_FOR(THRE);
- FLOWCTL_WAIT_FOR(CTS);
-
- ch = *p++;
- if (ch == 0x0a) {
- GDBPORT_SERIAL_TX = 0x0d;
- LSR_WAIT_FOR(THRE);
- FLOWCTL_WAIT_FOR(CTS);
- }
- GDBPORT_SERIAL_TX = ch;
- }
-
- FLOWCTL_CLEAR(DTR);
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* CONFIG_GDBSTUB_ON_TTYSx */
-
-#endif /* _ASM_UNIT_SERIAL_H */
diff --git a/arch/mn10300/unit-asb2303/include/unit/smc91111.h b/arch/mn10300/unit-asb2303/include/unit/smc91111.h
deleted file mode 100644
index dd4e2946438e..000000000000
--- a/arch/mn10300/unit-asb2303/include/unit/smc91111.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Support for the SMC91C111 NIC on an ASB2303
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_UNIT_SMC91111_H
-#define _ASM_UNIT_SMC91111_H
-
-#include <asm/intctl-regs.h>
-
-#define SMC91111_BASE 0xAA000300UL
-#define SMC91111_BASE_END 0xAA000400UL
-#define SMC91111_IRQ XIRQ3
-
-#define SMC_CAN_USE_8BIT 0
-#define SMC_CAN_USE_16BIT 1
-#define SMC_CAN_USE_32BIT 0
-#define SMC_NOWAIT 1
-#define SMC_IRQ_FLAGS (0)
-
-#if SMC_CAN_USE_8BIT
-#define SMC_inb(a, r) inb((unsigned long) ((a) + (r)))
-#define SMC_outb(v, a, r) outb(v, (unsigned long) ((a) + (r)))
-#endif
-
-#if SMC_CAN_USE_16BIT
-#define SMC_inw(a, r) inw((unsigned long) ((a) + (r)))
-#define SMC_outw(lp, v, a, r) outw(v, (unsigned long) ((a) + (r)))
-#define SMC_insw(a, r, p, l) insw((unsigned long) ((a) + (r)), (p), (l))
-#define SMC_outsw(a, r, p, l) outsw((unsigned long) ((a) + (r)), (p), (l))
-#endif
-
-#if SMC_CAN_USE_32BIT
-#define SMC_inl(a, r) inl((unsigned long) ((a) + (r)))
-#define SMC_outl(v, a, r) outl(v, (unsigned long) ((a) + (r)))
-#define SMC_insl(a, r, p, l) insl((unsigned long) ((a) + (r)), (p), (l))
-#define SMC_outsl(a, r, p, l) outsl((unsigned long) ((a) + (r)), (p), (l))
-#endif
-
-#define RPC_LSA_DEFAULT RPC_LED_100_10
-#define RPC_LSB_DEFAULT RPC_LED_TX_RX
-
-#define set_irq_type(irq, type)
-
-#endif /* _ASM_UNIT_SMC91111_H */
diff --git a/arch/mn10300/unit-asb2303/include/unit/timex.h b/arch/mn10300/unit-asb2303/include/unit/timex.h
deleted file mode 100644
index c37f9832cf17..000000000000
--- a/arch/mn10300/unit-asb2303/include/unit/timex.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* ASB2303-specific timer specifications
- *
- * Copyright (C) 2007, 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_UNIT_TIMEX_H
-#define _ASM_UNIT_TIMEX_H
-
-#include <asm/timer-regs.h>
-#include <unit/clock.h>
-#include <asm/param.h>
-
-/*
- * jiffies counter specifications
- */
-
-#define TMJCBR_MAX 0xffff
-#define TMJCIRQ TM1IRQ
-#define TMJCICR TM1ICR
-
-#ifndef __ASSEMBLY__
-
-#define MN10300_SRC_IOCLK MN10300_IOCLK
-
-#ifndef HZ
-# error HZ undeclared.
-#endif /* !HZ */
-/* use as little prescaling as possible to avoid losing accuracy */
-#if (MN10300_SRC_IOCLK + HZ / 2) / HZ - 1 <= TMJCBR_MAX
-# define IOCLK_PRESCALE 1
-# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK
-# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK
-#elif (MN10300_SRC_IOCLK / 8 + HZ / 2) / HZ - 1 <= TMJCBR_MAX
-# define IOCLK_PRESCALE 8
-# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_8
-# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_8
-#elif (MN10300_SRC_IOCLK / 32 + HZ / 2) / HZ - 1 <= TMJCBR_MAX
-# define IOCLK_PRESCALE 32
-# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_32
-# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_32
-#else
-# error You lose.
-#endif
-
-#define MN10300_JCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE)
-#define MN10300_TSCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE)
-
-#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ)
-#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ)
-
-static inline void stop_jiffies_counter(void)
-{
- u16 tmp;
- TM01MD = JC_TIMER_CLKSRC | TM1MD_SRC_TM0CASCADE << 8;
- tmp = TM01MD;
-}
-
-static inline void reload_jiffies_counter(u32 cnt)
-{
- u32 tmp;
-
- TM01BR = cnt;
- tmp = TM01BR;
-
- TM01MD = JC_TIMER_CLKSRC | \
- TM1MD_SRC_TM0CASCADE << 8 | \
- TM0MD_INIT_COUNTER | \
- TM1MD_INIT_COUNTER << 8;
-
-
- TM01MD = JC_TIMER_CLKSRC | \
- TM1MD_SRC_TM0CASCADE << 8 | \
- TM0MD_COUNT_ENABLE | \
- TM1MD_COUNT_ENABLE << 8;
-
- tmp = TM01MD;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-
-/*
- * timestamp counter specifications
- */
-
-#define TMTSCBR_MAX 0xffffffff
-#define TMTSCBC TM45BC
-
-#ifndef __ASSEMBLY__
-
-static inline void startup_timestamp_counter(void)
-{
- u32 t32;
-
- /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time
- * - count down from 4Gig-1 to 0 and wrap at IOCLK rate
- */
- TM45BR = TMTSCBR_MAX;
- t32 = TM45BR;
-
- TM4MD = TSC_TIMER_CLKSRC;
- TM4MD |= TM4MD_INIT_COUNTER;
- TM4MD &= ~TM4MD_INIT_COUNTER;
- TM4ICR = 0;
- t32 = TM4ICR;
-
- TM5MD = TM5MD_SRC_TM4CASCADE;
- TM5MD |= TM5MD_INIT_COUNTER;
- TM5MD &= ~TM5MD_INIT_COUNTER;
- TM5ICR = 0;
- t32 = TM5ICR;
-
- TM5MD |= TM5MD_COUNT_ENABLE;
- TM4MD |= TM4MD_COUNT_ENABLE;
- t32 = TM5MD;
- t32 = TM4MD;
-}
-
-static inline void shutdown_timestamp_counter(void)
-{
- u8 t8;
- TM4MD = 0;
- TM5MD = 0;
- t8 = TM4MD;
- t8 = TM5MD;
-}
-
-/*
- * we use a cascaded pair of 16-bit down-counting timers to count I/O
- * clock cycles for the purposes of time keeping
- */
-typedef unsigned long cycles_t;
-
-static inline cycles_t read_timestamp_counter(void)
-{
- return (cycles_t)~TMTSCBC;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_UNIT_TIMEX_H */
diff --git a/arch/mn10300/unit-asb2303/leds.c b/arch/mn10300/unit-asb2303/leds.c
deleted file mode 100644
index c03839357a14..000000000000
--- a/arch/mn10300/unit-asb2303/leds.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* ASB2303 peripheral 7-segment LEDs x1 support
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/intctl-regs.h>
-#include <asm/rtc-regs.h>
-#include <unit/leds.h>
-
-#if 0
-static const u8 asb2303_led_hex_tbl[16] = {
- 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0,
- 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c
-};
-#endif
-
-static const u8 asb2303_led_chase_tbl[6] = {
- ~0x02, /* top - segA */
- ~0x04, /* right top - segB */
- ~0x08, /* right bottom - segC */
- ~0x10, /* bottom - segD */
- ~0x20, /* left bottom - segE */
- ~0x40, /* left top - segF */
-};
-
-static unsigned asb2303_led_chase;
-
-void peripheral_leds_display_exception(enum exception_code code)
-{
- ASB2303_GPIO0DEF = 0x5555; /* configure as an output port */
- ASB2303_7SEGLEDS = 0x6d; /* triple horizontal bar */
-}
-
-void peripheral_leds_led_chase(void)
-{
- ASB2303_GPIO0DEF = 0x5555; /* configure as an output port */
- ASB2303_7SEGLEDS = asb2303_led_chase_tbl[asb2303_led_chase];
- asb2303_led_chase++;
- if (asb2303_led_chase >= 6)
- asb2303_led_chase = 0;
-}
diff --git a/arch/mn10300/unit-asb2303/smc91111.c b/arch/mn10300/unit-asb2303/smc91111.c
deleted file mode 100644
index 53677694b165..000000000000
--- a/arch/mn10300/unit-asb2303/smc91111.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* ASB2303 initialisation
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/timex.h>
-#include <asm/processor.h>
-#include <asm/intctl-regs.h>
-#include <unit/smc91111.h>
-
-static struct resource smc91c111_resources[] = {
- [0] = {
- .start = SMC91111_BASE,
- .end = SMC91111_BASE_END,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = SMC91111_IRQ,
- .end = SMC91111_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device smc91c111_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91c111_resources),
- .resource = smc91c111_resources,
-};
-
-/*
- * add platform devices
- */
-static int __init unit_device_init(void)
-{
- platform_device_register(&smc91c111_device);
- return 0;
-}
-
-device_initcall(unit_device_init);
diff --git a/arch/mn10300/unit-asb2303/unit-init.c b/arch/mn10300/unit-asb2303/unit-init.c
deleted file mode 100644
index 834a76aa551a..000000000000
--- a/arch/mn10300/unit-asb2303/unit-init.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* ASB2303 initialisation
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-#include <asm/intctl-regs.h>
-
-/*
- * initialise some of the unit hardware before gdbstub is set up
- */
-asmlinkage void __init unit_init(void)
-{
- /* set up the external interrupts */
- SET_XIRQ_TRIGGER(0, XIRQ_TRIGGER_HILEVEL);
- SET_XIRQ_TRIGGER(2, XIRQ_TRIGGER_LOWLEVEL);
- SET_XIRQ_TRIGGER(3, XIRQ_TRIGGER_HILEVEL);
- SET_XIRQ_TRIGGER(4, XIRQ_TRIGGER_LOWLEVEL);
- SET_XIRQ_TRIGGER(5, XIRQ_TRIGGER_LOWLEVEL);
-
-#ifdef CONFIG_EXT_SERIAL_IRQ_LEVEL
- set_intr_level(XIRQ0, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL));
-#endif
-
-#ifdef CONFIG_ETHERNET_IRQ_LEVEL
- set_intr_level(XIRQ3, NUM2GxICR_LEVEL(CONFIG_ETHERNET_IRQ_LEVEL));
-#endif
-}
-
-/*
- * initialise the rest of the unit hardware after gdbstub is ready
- */
-void __init unit_setup(void)
-{
-}
-
-/*
- * initialise the external interrupts used by a unit of this type
- */
-void __init unit_init_IRQ(void)
-{
- unsigned int extnum;
-
- for (extnum = 0; extnum < NR_XIRQS; extnum++) {
- switch (GET_XIRQ_TRIGGER(extnum)) {
- case XIRQ_TRIGGER_HILEVEL:
- case XIRQ_TRIGGER_LOWLEVEL:
- mn10300_set_lateack_irq_type(XIRQ2IRQ(extnum));
- break;
- default:
- break;
- }
- }
-}
diff --git a/arch/mn10300/unit-asb2305/Makefile b/arch/mn10300/unit-asb2305/Makefile
deleted file mode 100644
index cbc5abaa939a..000000000000
--- a/arch/mn10300/unit-asb2305/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-###############################################################################
-#
-# Makefile for the ASB2305 board
-#
-###############################################################################
-obj-y := unit-init.o leds.o
-
-obj-$(CONFIG_PCI) += pci.o pci-asb2305.o pci-irq.o
diff --git a/arch/mn10300/unit-asb2305/include/unit/clock.h b/arch/mn10300/unit-asb2305/include/unit/clock.h
deleted file mode 100644
index 29e3425431cf..000000000000
--- a/arch/mn10300/unit-asb2305/include/unit/clock.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* ASB2305-specific clocks
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_CLOCK_H
-#define _ASM_UNIT_CLOCK_H
-
-#ifndef __ASSEMBLY__
-
-#define MN10300_IOCLK 33333333UL
-/* #define MN10300_IOBCLK 66666666UL */
-
-#endif /* !__ASSEMBLY__ */
-
-#define MN10300_WDCLK MN10300_IOCLK
-
-#endif /* _ASM_UNIT_CLOCK_H */
diff --git a/arch/mn10300/unit-asb2305/include/unit/leds.h b/arch/mn10300/unit-asb2305/include/unit/leds.h
deleted file mode 100644
index bc471f617fd1..000000000000
--- a/arch/mn10300/unit-asb2305/include/unit/leds.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* ASB2305-specific LEDs
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_LEDS_H
-#define _ASM_UNIT_LEDS_H
-
-#include <asm/pio-regs.h>
-#include <asm/cpu-regs.h>
-#include <asm/exceptions.h>
-
-#define ASB2305_7SEGLEDS __SYSREG(0xA6F90000, u32)
-
-/* perform a hard reset by driving PIO06 low */
-#define mn10300_unit_hard_reset() \
-do { \
- P0OUT &= 0xbf; \
- P0MD = (P0MD & P0MD_6) | P0MD_6_OUT; \
-} while (0)
-
-/*
- * use the 7-segment LEDs to indicate states
- */
-/* indicate double-fault by displaying "db-f" on the LEDs */
-#define mn10300_set_dbfleds \
- mov 0x43077f1d,d0 ; \
- mov d0,(ASB2305_7SEGLEDS)
-
-/* flip the 7-segment LEDs between "Gdb-" and "----" */
-#define mn10300_set_gdbleds(ONOFF) \
-do { \
- ASB2305_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f; \
-} while (0)
-
-#ifndef __ASSEMBLY__
-extern void peripheral_leds_display_exception(enum exception_code);
-extern void peripheral_leds_led_chase(void);
-extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int);
-extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int);
-extern void peripheral_leds7x4_display_minssecs(unsigned int, unsigned int);
-extern void peripheral_leds7x4_display_rtc(void);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_UNIT_LEDS_H */
diff --git a/arch/mn10300/unit-asb2305/include/unit/serial.h b/arch/mn10300/unit-asb2305/include/unit/serial.h
deleted file mode 100644
index 88c08219315f..000000000000
--- a/arch/mn10300/unit-asb2305/include/unit/serial.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* ASB2305-specific 8250 serial ports
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_UNIT_SERIAL_H
-#define _ASM_UNIT_SERIAL_H
-
-#include <asm/cpu-regs.h>
-#include <proc/irq.h>
-#include <linux/serial_reg.h>
-
-#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000
-#define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8)
-
-#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */
-
-/*
- * The ASB2305 has an 18.432 MHz clock the UART
- */
-#define BASE_BAUD (18432000 / 16)
-
-/*
- * dispose of the /dev/ttyS0 serial port
- */
-#ifndef CONFIG_GDBSTUB_ON_TTYSx
-
-#define SERIAL_PORT_DFNS \
- { \
- .baud_base = BASE_BAUD, \
- .irq = SERIAL_IRQ, \
- .flags = STD_COM_FLAGS, \
- .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \
- .iomem_reg_shift = 2, \
- .io_type = SERIAL_IO_MEM, \
- },
-
-#ifndef __ASSEMBLY__
-
-static inline void __debug_to_serial(const char *p, int n)
-{
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#else /* CONFIG_GDBSTUB_ON_TTYSx */
-
-#define SERIAL_PORT_DFNS /* stolen by gdb-stub */
-
-#if defined(CONFIG_GDBSTUB_ON_TTYS0)
-#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
-#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
-#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
-#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
-#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
-#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
-#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
-#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
-#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
-#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
-#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
-#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8)
-#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
-
-#elif defined(CONFIG_GDBSTUB_ON_TTYS1)
-#error The ASB2305 doesnt have a /dev/ttyS1
-#endif
-
-#ifndef __ASSEMBLY__
-
-#define TTYS0_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
-#define TTYS0_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
-#define TTYS0_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
-#define TTYS0_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
-
-#define LSR_WAIT_FOR(STATE) \
-do { \
- while (!(TTYS0_LSR & UART_LSR_##STATE)) {} \
-} while (0)
-#define FLOWCTL_WAIT_FOR(LINE) \
-do { \
- while (!(TTYS0_MSR & UART_MSR_##LINE)) {} \
-} while (0)
-#define FLOWCTL_CLEAR(LINE) \
-do { \
- TTYS0_MCR &= ~UART_MCR_##LINE; \
-} while (0)
-#define FLOWCTL_SET(LINE) \
-do { \
- TTYS0_MCR |= UART_MCR_##LINE; \
-} while (0)
-#define FLOWCTL_QUERY(LINE) ({ TTYS0_MSR & UART_MSR_##LINE; })
-
-static inline void __debug_to_serial(const char *p, int n)
-{
- char ch;
-
- FLOWCTL_SET(DTR);
-
- for (; n > 0; n--) {
- LSR_WAIT_FOR(THRE);
- FLOWCTL_WAIT_FOR(CTS);
-
- ch = *p++;
- if (ch == 0x0a) {
- TTYS0_TX = 0x0d;
- LSR_WAIT_FOR(THRE);
- FLOWCTL_WAIT_FOR(CTS);
- }
- TTYS0_TX = ch;
- }
-
- FLOWCTL_CLEAR(DTR);
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* CONFIG_GDBSTUB_ON_TTYSx */
-
-#endif /* _ASM_UNIT_SERIAL_H */
diff --git a/arch/mn10300/unit-asb2305/include/unit/timex.h b/arch/mn10300/unit-asb2305/include/unit/timex.h
deleted file mode 100644
index 4cefc224f448..000000000000
--- a/arch/mn10300/unit-asb2305/include/unit/timex.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* ASB2305-specific timer specifications
- *
- * Copyright (C) 2007, 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _ASM_UNIT_TIMEX_H
-#define _ASM_UNIT_TIMEX_H
-
-#include <asm/timer-regs.h>
-#include <unit/clock.h>
-#include <asm/param.h>
-
-/*
- * jiffies counter specifications
- */
-
-#define TMJCBR_MAX 0xffff
-#define TMJCIRQ TM1IRQ
-#define TMJCICR TM1ICR
-
-#ifndef __ASSEMBLY__
-
-#define MN10300_SRC_IOCLK MN10300_IOCLK
-
-#ifndef HZ
-# error HZ undeclared.
-#endif /* !HZ */
-/* use as little prescaling as possible to avoid losing accuracy */
-#if (MN10300_SRC_IOCLK + HZ / 2) / HZ - 1 <= TMJCBR_MAX
-# define IOCLK_PRESCALE 1
-# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK
-# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK
-#elif (MN10300_SRC_IOCLK / 8 + HZ / 2) / HZ - 1 <= TMJCBR_MAX
-# define IOCLK_PRESCALE 8
-# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_8
-# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_8
-#elif (MN10300_SRC_IOCLK / 32 + HZ / 2) / HZ - 1 <= TMJCBR_MAX
-# define IOCLK_PRESCALE 32
-# define JC_TIMER_CLKSRC TM0MD_SRC_IOCLK_32
-# define TSC_TIMER_CLKSRC TM4MD_SRC_IOCLK_32
-#else
-# error You lose.
-#endif
-
-#define MN10300_JCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE)
-#define MN10300_TSCCLK (MN10300_SRC_IOCLK / IOCLK_PRESCALE)
-
-#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ)
-#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ)
-
-static inline void stop_jiffies_counter(void)
-{
- u16 tmp;
- TM01MD = JC_TIMER_CLKSRC | TM1MD_SRC_TM0CASCADE << 8;
- tmp = TM01MD;
-}
-
-static inline void reload_jiffies_counter(u32 cnt)
-{
- u32 tmp;
-
- TM01BR = cnt;
- tmp = TM01BR;
-
- TM01MD = JC_TIMER_CLKSRC | \
- TM1MD_SRC_TM0CASCADE << 8 | \
- TM0MD_INIT_COUNTER | \
- TM1MD_INIT_COUNTER << 8;
-
-
- TM01MD = JC_TIMER_CLKSRC | \
- TM1MD_SRC_TM0CASCADE << 8 | \
- TM0MD_COUNT_ENABLE | \
- TM1MD_COUNT_ENABLE << 8;
-
- tmp = TM01MD;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-
-/*
- * timestamp counter specifications
- */
-
-#define TMTSCBR_MAX 0xffffffff
-#define TMTSCBC TM45BC
-
-#ifndef __ASSEMBLY__
-
-static inline void startup_timestamp_counter(void)
-{
- u32 t32;
-
- /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time
- * - count down from 4Gig-1 to 0 and wrap at IOCLK rate
- */
- TM45BR = TMTSCBR_MAX;
- t32 = TM45BR;
-
- TM4MD = TSC_TIMER_CLKSRC;
- TM4MD |= TM4MD_INIT_COUNTER;
- TM4MD &= ~TM4MD_INIT_COUNTER;
- TM4ICR = 0;
- t32 = TM4ICR;
-
- TM5MD = TM5MD_SRC_TM4CASCADE;
- TM5MD |= TM5MD_INIT_COUNTER;
- TM5MD &= ~TM5MD_INIT_COUNTER;
- TM5ICR = 0;
- t32 = TM5ICR;
-
- TM5MD |= TM5MD_COUNT_ENABLE;
- TM4MD |= TM4MD_COUNT_ENABLE;
- t32 = TM5MD;
- t32 = TM4MD;
-}
-
-static inline void shutdown_timestamp_counter(void)
-{
- u8 t8;
- TM4MD = 0;
- TM5MD = 0;
- t8 = TM4MD;
- t8 = TM5MD;
-}
-
-/*
- * we use a cascaded pair of 16-bit down-counting timers to count I/O
- * clock cycles for the purposes of time keeping
- */
-typedef unsigned long cycles_t;
-
-static inline cycles_t read_timestamp_counter(void)
-{
- return (cycles_t)~TMTSCBC;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_UNIT_TIMEX_H */
diff --git a/arch/mn10300/unit-asb2305/leds.c b/arch/mn10300/unit-asb2305/leds.c
deleted file mode 100644
index 6f8de9954026..000000000000
--- a/arch/mn10300/unit-asb2305/leds.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* ASB2305 Peripheral 7-segment LEDs x4 support
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/intctl-regs.h>
-#include <asm/rtc-regs.h>
-#include <unit/leds.h>
-
-static const u8 asb2305_led_hex_tbl[16] = {
- 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0,
- 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c
-};
-
-static const u32 asb2305_led_chase_tbl[6] = {
- ~0x02020202, /* top - segA */
- ~0x04040404, /* right top - segB */
- ~0x08080808, /* right bottom - segC */
- ~0x10101010, /* bottom - segD */
- ~0x20202020, /* left bottom - segE */
- ~0x40404040, /* left top - segF */
-};
-
-static unsigned asb2305_led_chase;
-
-void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points)
-{
- u32 leds;
-
- leds = asb2305_led_hex_tbl[(val/1000) % 10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[(val/100) % 10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[(val/10) % 10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[val % 10];
- leds |= points^0x01010101;
-
- ASB2305_7SEGLEDS = leds;
-}
-
-void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points)
-{
- u32 leds;
-
- leds = asb2305_led_hex_tbl[(val/1000) % 10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[(val/100) % 10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[(val/10) % 10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[val % 10];
- leds |= points^0x01010101;
-
- ASB2305_7SEGLEDS = leds;
-}
-
-void peripheral_leds_display_exception(enum exception_code code)
-{
- u32 leds;
-
- leds = asb2305_led_hex_tbl[(code/0x100) % 0x10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[(code/0x10) % 0x10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[code % 0x10];
- leds |= 0x6d010101;
-
- ASB2305_7SEGLEDS = leds;
-}
-
-void peripheral_leds7x4_display_minssecs(unsigned int time, unsigned int points)
-{
- u32 leds;
-
- leds = asb2305_led_hex_tbl[(time/600) % 6];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[(time/60) % 10];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[(time/10) % 6];
- leds <<= 8;
- leds |= asb2305_led_hex_tbl[time % 10];
- leds |= points^0x01010101;
-
- ASB2305_7SEGLEDS = leds;
-}
-
-void peripheral_leds7x4_display_rtc(void)
-{
- unsigned int clock;
- u8 mins, secs;
-
- mins = RTMCR;
- secs = RTSCR;
-
- clock = ((mins & 0xf0) >> 4);
- clock *= 10;
- clock += (mins & 0x0f);
- clock *= 6;
-
- clock += ((secs & 0xf0) >> 4);
- clock *= 10;
- clock += (secs & 0x0f);
-
- peripheral_leds7x4_display_minssecs(clock, 0);
-}
-
-void peripheral_leds_led_chase(void)
-{
- ASB2305_7SEGLEDS = asb2305_led_chase_tbl[asb2305_led_chase];
- asb2305_led_chase++;
- if (asb2305_led_chase >= 6)
- asb2305_led_chase = 0;
-}
diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.c b/arch/mn10300/unit-asb2305/pci-asb2305.c
deleted file mode 100644
index e0f4617c0c7a..000000000000
--- a/arch/mn10300/unit-asb2305/pci-asb2305.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* ASB2305 PCI resource stuff
- *
- * Copyright (C) 2001 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * - Derived from arch/i386/pci-i386.c
- * - Copyright 1997--2000 Martin Mares <mj@suse.cz>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/errno.h>
-#include "pci-asb2305.h"
-
-/*
- * We need to avoid collisions with `mirrored' VGA ports
- * and other strange ISA hardware, so we always want the
- * addresses to be allocated in the 0x000-0x0ff region
- * modulo 0x400.
- *
- * Why? Because some silly external IO cards only decode
- * the low 10 bits of the IO address. The 0x00-0xff region
- * is reserved for motherboard devices that decode all 16
- * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
- * but we want to try to avoid allocating at 0x2900-0x2bff
- * which might have be mirrored at 0x0100-0x03ff..
- */
-resource_size_t pcibios_align_resource(void *data, const struct resource *res,
- resource_size_t size, resource_size_t align)
-{
- resource_size_t start = res->start;
-
-#if 0
- struct pci_dev *dev = data;
-
- printk(KERN_DEBUG
- "### PCIBIOS_ALIGN_RESOURCE(%s,,{%08lx-%08lx,%08lx},%lx)\n",
- pci_name(dev),
- res->start,
- res->end,
- res->flags,
- size
- );
-#endif
-
- if ((res->flags & IORESOURCE_IO) && (start & 0x300))
- start = (start + 0x3ff) & ~0x3ff;
-
- return start;
-}
-
-
-/*
- * Handle resources of PCI devices. If the world were perfect, we could
- * just allocate all the resource regions and do nothing more. It isn't.
- * On the other hand, we cannot just re-allocate all devices, as it would
- * require us to know lots of host bridge internals. So we attempt to
- * keep as much of the original configuration as possible, but tweak it
- * when it's found to be wrong.
- *
- * Known BIOS problems we have to work around:
- * - I/O or memory regions not configured
- * - regions configured, but not enabled in the command register
- * - bogus I/O addresses above 64K used
- * - expansion ROMs left enabled (this may sound harmless, but given
- * the fact the PCI specs explicitly allow address decoders to be
- * shared between expansion ROMs and other resource regions, it's
- * at least dangerous)
- *
- * Our solution:
- * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
- * This gives us fixed barriers on where we can allocate.
- * (2) Allocate resources for all enabled devices. If there is
- * a collision, just mark the resource as unallocated. Also
- * disable expansion ROMs during this step.
- * (3) Try to allocate resources for disabled devices. If the
- * resources were assigned correctly, everything goes well,
- * if they weren't, they won't disturb allocation of other
- * resources.
- * (4) Assign new addresses to resources which were either
- * not configured at all or misconfigured. If explicitly
- * requested by the user, configure expansion ROM address
- * as well.
- */
-static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
-{
- struct pci_bus *bus;
- struct pci_dev *dev;
- int idx;
- struct resource *r;
-
- /* Depth-First Search on bus tree */
- list_for_each_entry(bus, bus_list, node) {
- dev = bus->self;
- if (dev) {
- for (idx = PCI_BRIDGE_RESOURCES;
- idx < PCI_NUM_RESOURCES;
- idx++) {
- r = &dev->resource[idx];
- if (!r->flags)
- continue;
- if (!r->start ||
- pci_claim_bridge_resource(dev, idx) < 0) {
- printk(KERN_ERR "PCI:"
- " Cannot allocate resource"
- " region %d of bridge %s\n",
- idx, pci_name(dev));
- /* Something is wrong with the region.
- * Invalidate the resource to prevent
- * child resource allocations in this
- * range. */
- r->start = r->end = 0;
- r->flags = 0;
- }
- }
- }
- pcibios_allocate_bus_resources(&bus->children);
- }
-}
-
-static void __init pcibios_allocate_resources(int pass)
-{
- struct pci_dev *dev = NULL;
- int idx, disabled;
- u16 command;
- struct resource *r;
-
- for_each_pci_dev(dev) {
- pci_read_config_word(dev, PCI_COMMAND, &command);
- for (idx = 0; idx < 6; idx++) {
- r = &dev->resource[idx];
- if (r->parent) /* Already allocated */
- continue;
- if (!r->start) /* Address not assigned */
- continue;
- if (r->flags & IORESOURCE_IO)
- disabled = !(command & PCI_COMMAND_IO);
- else
- disabled = !(command & PCI_COMMAND_MEMORY);
- if (pass == disabled) {
- DBG("PCI[%s]: Resource %08lx-%08lx"
- " (f=%lx, d=%d, p=%d)\n",
- pci_name(dev), r->start, r->end, r->flags,
- disabled, pass);
- if (pci_claim_resource(dev, idx) < 0) {
- printk(KERN_ERR "PCI:"
- " Cannot allocate resource"
- " region %d of device %s\n",
- idx, pci_name(dev));
- /* We'll assign a new address later */
- r->end -= r->start;
- r->start = 0;
- }
- }
- }
- if (!pass) {
- r = &dev->resource[PCI_ROM_RESOURCE];
- if (r->flags & IORESOURCE_ROM_ENABLE) {
- /* Turn the ROM off, leave the resource region,
- * but keep it unregistered. */
- u32 reg;
- DBG("PCI: Switching off ROM of %s\n",
- pci_name(dev));
- r->flags &= ~IORESOURCE_ROM_ENABLE;
- pci_read_config_dword(
- dev, dev->rom_base_reg, &reg);
- pci_write_config_dword(
- dev, dev->rom_base_reg,
- reg & ~PCI_ROM_ADDRESS_ENABLE);
- }
- }
- }
-}
-
-static int __init pcibios_assign_resources(void)
-{
- struct pci_dev *dev = NULL;
- struct resource *r;
-
- /* Try to use BIOS settings for ROMs, otherwise let
- pci_assign_unassigned_resources() allocate the new
- addresses. */
- for_each_pci_dev(dev) {
- r = &dev->resource[PCI_ROM_RESOURCE];
- if (!r->flags || !r->start)
- continue;
- if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
- r->end -= r->start;
- r->start = 0;
- }
- }
-
- pci_assign_unassigned_resources();
-
- return 0;
-}
-
-fs_initcall(pcibios_assign_resources);
-
-void __init pcibios_resource_survey(void)
-{
- DBG("PCI: Allocating resources\n");
- pcibios_allocate_bus_resources(&pci_root_buses);
- pcibios_allocate_resources(0);
- pcibios_allocate_resources(1);
-}
diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.h b/arch/mn10300/unit-asb2305/pci-asb2305.h
deleted file mode 100644
index 0667f613b023..000000000000
--- a/arch/mn10300/unit-asb2305/pci-asb2305.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* ASB2305 Arch-specific PCI declarations
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * Derived from: arch/i386/kernel/pci-i386.h: (c) 1999 Martin Mares <mj@ucw.cz>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _PCI_ASB2305_H
-#define _PCI_ASB2305_H
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-extern unsigned int pci_probe;
-
-/* pci-asb2305.c */
-
-extern void pcibios_resource_survey(void);
-
-/* pci.c */
-
-extern struct pci_ops *pci_root_ops;
-
-/* pci-irq.c */
-
-struct irq_info {
- u8 bus, devfn; /* Bus, device and function */
- struct {
- u8 link; /* IRQ line ID, chipset dependent,
- * 0=not routed */
- u16 bitmap; /* Available IRQs */
- } __attribute__((packed)) irq[4];
- u8 slot; /* Slot number, 0=onboard */
- u8 rfu;
-} __attribute__((packed));
-
-struct irq_routing_table {
- u32 signature; /* PIRQ_SIGNATURE should be here */
- u16 version; /* PIRQ_VERSION */
- u16 size; /* Table size in bytes */
- u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
- u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
- u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
- u32 miniport_data; /* Crap */
- u8 rfu[11];
- u8 checksum; /* Modulo 256 checksum must give zero */
- struct irq_info slots[0];
-} __attribute__((packed));
-
-extern unsigned int pcibios_irq_mask;
-
-extern void pcibios_irq_init(void);
-extern void pcibios_fixup_irqs(void);
-extern void pcibios_enable_irq(struct pci_dev *dev);
-
-#endif /* PCI_ASB2305_H */
diff --git a/arch/mn10300/unit-asb2305/pci-irq.c b/arch/mn10300/unit-asb2305/pci-irq.c
deleted file mode 100644
index fcb28ceb824d..000000000000
--- a/arch/mn10300/unit-asb2305/pci-irq.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* PCI IRQ routing on the MN103E010 based ASB2305
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- *
- * This is simple: All PCI interrupts route through the CPU's XIRQ1 pin [IRQ 35]
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include "pci-asb2305.h"
-
-void __init pcibios_irq_init(void)
-{
-}
-
-void __init pcibios_fixup_irqs(void)
-{
- struct pci_dev *dev = NULL;
- u8 line, pin;
-
- for_each_pci_dev(dev) {
- pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
- if (pin) {
- dev->irq = XIRQ1;
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
- dev->irq);
- }
- pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line);
- }
-}
-
-void pcibios_enable_irq(struct pci_dev *dev)
-{
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-}
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
deleted file mode 100644
index 3dfe2d31c67b..000000000000
--- a/arch/mn10300/unit-asb2305/pci.c
+++ /dev/null
@@ -1,505 +0,0 @@
-/* ASB2305 PCI support
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- * Derived from arch/i386/kernel/pci-pc.c
- * (c) 1999--2000 Martin Mares <mj@suse.cz>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include "pci-asb2305.h"
-
-unsigned int pci_probe = 1;
-
-struct pci_ops *pci_root_ops;
-
-/*
- * The accessible PCI window does not cover the entire CPU address space, but
- * there are devices we want to access outside of that window, so we need to
- * insert specific PCI bus resources instead of using the platform-level bus
- * resources directly for the PCI root bus.
- *
- * These are configured and inserted by pcibios_init().
- */
-static struct resource pci_ioport_resource = {
- .name = "PCI IO",
- .start = 0xbe000000,
- .end = 0xbe03ffff,
- .flags = IORESOURCE_IO,
-};
-
-static struct resource pci_iomem_resource = {
- .name = "PCI mem",
- .start = 0xb8000000,
- .end = 0xbbffffff,
- .flags = IORESOURCE_MEM,
-};
-
-/*
- * Functions for accessing PCI configuration space
- */
-
-#define CONFIG_CMD(bus, devfn, where) \
- (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
-
-#define MEM_PAGING_REG (*(volatile __u32 *) 0xBFFFFFF4)
-#define CONFIG_ADDRESS (*(volatile __u32 *) 0xBFFFFFF8)
-#define CONFIG_DATAL(X) (*(volatile __u32 *) 0xBFFFFFFC)
-#define CONFIG_DATAW(X) (*(volatile __u16 *) (0xBFFFFFFC + ((X) & 2)))
-#define CONFIG_DATAB(X) (*(volatile __u8 *) (0xBFFFFFFC + ((X) & 3)))
-
-#define BRIDGEREGB(X) (*(volatile __u8 *) (0xBE040000 + (X)))
-#define BRIDGEREGW(X) (*(volatile __u16 *) (0xBE040000 + (X)))
-#define BRIDGEREGL(X) (*(volatile __u32 *) (0xBE040000 + (X)))
-
-static inline int __query(const struct pci_bus *bus, unsigned int devfn)
-{
-#if 0
- return bus->number == 0 && (devfn == PCI_DEVFN(0, 0));
- return bus->number == 1;
- return bus->number == 0 &&
- (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0));
-#endif
- return 1;
-}
-
-/*
- *
- */
-static int pci_ampci_read_config_byte(struct pci_bus *bus, unsigned int devfn,
- int where, u32 *_value)
-{
- u32 rawval, value;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- value = BRIDGEREGB(where);
- __pcbdebug("=> %02hx", &BRIDGEREGL(where), value);
- } else {
- CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
- rawval = CONFIG_ADDRESS;
- value = CONFIG_DATAB(where);
- if (__query(bus, devfn))
- __pcidebug("=> %02hx", bus, devfn, where, value);
- }
-
- *_value = value;
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_ampci_read_config_word(struct pci_bus *bus, unsigned int devfn,
- int where, u32 *_value)
-{
- u32 rawval, value;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- value = BRIDGEREGW(where);
- __pcbdebug("=> %04hx", &BRIDGEREGL(where), value);
- } else {
- CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
- rawval = CONFIG_ADDRESS;
- value = CONFIG_DATAW(where);
- if (__query(bus, devfn))
- __pcidebug("=> %04hx", bus, devfn, where, value);
- }
-
- *_value = value;
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_ampci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
- int where, u32 *_value)
-{
- u32 rawval, value;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- value = BRIDGEREGL(where);
- __pcbdebug("=> %08x", &BRIDGEREGL(where), value);
- } else {
- CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
- rawval = CONFIG_ADDRESS;
- value = CONFIG_DATAL(where);
- if (__query(bus, devfn))
- __pcidebug("=> %08x", bus, devfn, where, value);
- }
-
- *_value = value;
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_ampci_write_config_byte(struct pci_bus *bus, unsigned int devfn,
- int where, u8 value)
-{
- u32 rawval;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __pcbdebug("<= %02x", &BRIDGEREGB(where), value);
- BRIDGEREGB(where) = value;
- } else {
- if (bus->number == 0 &&
- (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0))
- )
- __pcidebug("<= %02x", bus, devfn, where, value);
- CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
- rawval = CONFIG_ADDRESS;
- CONFIG_DATAB(where) = value;
- }
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_ampci_write_config_word(struct pci_bus *bus, unsigned int devfn,
- int where, u16 value)
-{
- u32 rawval;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __pcbdebug("<= %04hx", &BRIDGEREGW(where), value);
- BRIDGEREGW(where) = value;
- } else {
- if (__query(bus, devfn))
- __pcidebug("<= %04hx", bus, devfn, where, value);
- CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
- rawval = CONFIG_ADDRESS;
- CONFIG_DATAW(where) = value;
- }
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_ampci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
- int where, u32 value)
-{
- u32 rawval;
-
- if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
- __pcbdebug("<= %08x", &BRIDGEREGL(where), value);
- BRIDGEREGL(where) = value;
- } else {
- if (__query(bus, devfn))
- __pcidebug("<= %08x", bus, devfn, where, value);
- CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
- rawval = CONFIG_ADDRESS;
- CONFIG_DATAL(where) = value;
- }
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int pci_ampci_read_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- switch (size) {
- case 1:
- return pci_ampci_read_config_byte(bus, devfn, where, val);
- case 2:
- return pci_ampci_read_config_word(bus, devfn, where, val);
- case 4:
- return pci_ampci_read_config_dword(bus, devfn, where, val);
- default:
- BUG();
- return -EOPNOTSUPP;
- }
-}
-
-static int pci_ampci_write_config(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- switch (size) {
- case 1:
- return pci_ampci_write_config_byte(bus, devfn, where, val);
- case 2:
- return pci_ampci_write_config_word(bus, devfn, where, val);
- case 4:
- return pci_ampci_write_config_dword(bus, devfn, where, val);
- default:
- BUG();
- return -EOPNOTSUPP;
- }
-}
-
-static struct pci_ops pci_direct_ampci = {
- .read = pci_ampci_read_config,
- .write = pci_ampci_write_config,
-};
-
-/*
- * Before we decide to use direct hardware access mechanisms, we try to do some
- * trivial checks to ensure it at least _seems_ to be working -- we just test
- * whether bus 00 contains a host bridge (this is similar to checking
- * techniques used in XFree86, but ours should be more reliable since we
- * attempt to make use of direct access hints provided by the PCI BIOS).
- *
- * This should be close to trivial, but it isn't, because there are buggy
- * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
- */
-static int __init pci_sanity_check(struct pci_ops *o)
-{
- struct pci_bus bus; /* Fake bus and device */
- u32 x;
-
- bus.number = 0;
-
- if ((!o->read(&bus, 0, PCI_CLASS_DEVICE, 2, &x) &&
- (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
- (!o->read(&bus, 0, PCI_VENDOR_ID, 2, &x) &&
- (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
- return 1;
-
- printk(KERN_ERR "PCI: Sanity check failed\n");
- return 0;
-}
-
-static int __init pci_check_direct(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
-
- /*
- * Check if access works.
- */
- if (pci_sanity_check(&pci_direct_ampci)) {
- local_irq_restore(flags);
- printk(KERN_INFO "PCI: Using configuration ampci\n");
- request_mem_region(0xBE040000, 256, "AMPCI bridge");
- request_mem_region(0xBFFFFFF4, 12, "PCI ampci");
- request_mem_region(0xBC000000, 32 * 1024 * 1024, "PCI SRAM");
- return 0;
- }
-
- local_irq_restore(flags);
- return -ENODEV;
-}
-
-static void pcibios_fixup_device_resources(struct pci_dev *dev)
-{
- int idx;
-
- if (!dev->bus)
- return;
-
- for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) {
- struct resource *r = &dev->resource[idx];
-
- if (!r->flags || r->parent || !r->start)
- continue;
-
- pci_claim_resource(dev, idx);
- }
-}
-
-static void pcibios_fixup_bridge_resources(struct pci_dev *dev)
-{
- int idx;
-
- if (!dev->bus)
- return;
-
- for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
- struct resource *r = &dev->resource[idx];
-
- if (!r->flags || r->parent || !r->start)
- continue;
-
- pci_claim_bridge_resource(dev, idx);
- }
-}
-
-/*
- * Called after each bus is probed, but before its children
- * are examined.
- */
-void pcibios_fixup_bus(struct pci_bus *bus)
-{
- struct pci_dev *dev;
-
- if (bus->self) {
- pci_read_bridge_bases(bus);
- pcibios_fixup_bridge_resources(bus->self);
- }
-
- list_for_each_entry(dev, &bus->devices, bus_list)
- pcibios_fixup_device_resources(dev);
-}
-
-/*
- * Initialization. Try all known PCI access methods. Note that we support
- * using both PCI BIOS and direct access: in such cases, we use I/O ports
- * to access config space, but we still keep BIOS order of cards to be
- * compatible with 2.0.X. This should go away some day.
- */
-static int __init pcibios_init(void)
-{
- resource_size_t io_offset, mem_offset;
- LIST_HEAD(resources);
- struct pci_bus *bus;
-
- ioport_resource.start = 0xA0000000;
- ioport_resource.end = 0xDFFFFFFF;
- iomem_resource.start = 0xA0000000;
- iomem_resource.end = 0xDFFFFFFF;
-
- if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0)
- panic("Unable to insert PCI IOMEM resource\n");
- if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0)
- panic("Unable to insert PCI IOPORT resource\n");
-
- if (!pci_probe)
- return 0;
-
- if (pci_check_direct() < 0) {
- printk(KERN_WARNING "PCI: No PCI bus detected\n");
- return 0;
- }
-
- printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
- MEM_PAGING_REG);
-
- io_offset = pci_ioport_resource.start -
- (pci_ioport_resource.start & 0x00ffffff);
- mem_offset = pci_iomem_resource.start -
- ((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG);
-
- pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset);
- pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset);
- bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources);
- if (!bus)
- return 0;
-
- pcibios_irq_init();
- pcibios_fixup_irqs();
- pcibios_resource_survey();
- pci_bus_add_devices(bus);
- return 0;
-}
-
-arch_initcall(pcibios_init);
-
-char *__init pcibios_setup(char *str)
-{
- if (!strcmp(str, "off")) {
- pci_probe = 0;
- return NULL;
- }
-
- return str;
-}
-
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
- int err;
-
- err = pci_enable_resources(dev, mask);
- if (err == 0)
- pcibios_enable_irq(dev);
- return err;
-}
-
-/*
- * disable the ethernet chipset
- */
-static void __init unit_disable_pcnet(struct pci_bus *bus, struct pci_ops *o)
-{
- u32 x;
-
- bus->number = 0;
-
- o->read (bus, PCI_DEVFN(2, 0), PCI_VENDOR_ID, 4, &x);
- o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x);
- x |= PCI_COMMAND_MASTER |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
- o->write(bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, x);
- o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x);
- o->write(bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, 0x00030001);
- o->read (bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, &x);
-
-#define RDP (*(volatile u32 *) 0xBE030010)
-#define RAP (*(volatile u32 *) 0xBE030014)
-#define __set_RAP(X) do { RAP = (X); x = RAP; } while (0)
-#define __set_RDP(X) do { RDP = (X); x = RDP; } while (0)
-#define __get_RDP() ({ RDP & 0xffff; })
-
- __set_RAP(0);
- __set_RDP(0x0004); /* CSR0 = STOP */
-
- __set_RAP(88); /* check CSR88 indicates an Am79C973 */
- BUG_ON(__get_RDP() != 0x5003);
-
- for (x = 0; x < 100; x++)
- asm volatile("nop");
-
- __set_RDP(0x0004); /* CSR0 = STOP */
-}
-
-/*
- * initialise the unit hardware
- */
-asmlinkage void __init unit_pci_init(void)
-{
- struct pci_bus bus; /* Fake bus and device */
- struct pci_ops *o = &pci_direct_ampci;
- u32 x;
-
- set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_PCI_IRQ_LEVEL));
-
- memset(&bus, 0, sizeof(bus));
-
- MEM_PAGING_REG = 0xE8000000;
-
- /* we need to set up the bridge _now_ or we won't be able to access the
- * PCI config registers
- */
- BRIDGEREGW(PCI_COMMAND) |=
- PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER;
- BRIDGEREGW(PCI_STATUS) = 0xF800;
- BRIDGEREGB(PCI_LATENCY_TIMER) = 0x10;
- BRIDGEREGL(PCI_BASE_ADDRESS_0) = 0x80000000;
- BRIDGEREGB(PCI_INTERRUPT_LINE) = 1;
- BRIDGEREGL(0x48) = 0x98000000; /* AMPCI base addr */
- BRIDGEREGB(0x41) = 0x00; /* secondary bus
- * number */
- BRIDGEREGB(0x42) = 0x01; /* subordinate bus
- * number */
- BRIDGEREGB(0x44) = 0x01;
- BRIDGEREGL(0x50) = 0x00000001;
- BRIDGEREGL(0x58) = 0x00001002;
- BRIDGEREGL(0x5C) = 0x00000011;
-
- /* we also need to set up the PCI-PCI bridge */
- bus.number = 0;
-
- /* IO: 0x00000000-0x00020000 */
- o->read (&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, &x);
- x |= PCI_COMMAND_MASTER |
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
- o->write(&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, x);
-
- o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
- o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
- o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
- o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
-
- o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, 0x01);
- o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
- o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, 0x00020000);
- o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
- o->write(&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, 0xEBB0EA00);
- o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
- o->write(&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, 0xE9F0E800);
- o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
-
- unit_disable_pcnet(&bus, o);
-}
diff --git a/arch/mn10300/unit-asb2305/unit-init.c b/arch/mn10300/unit-asb2305/unit-init.c
deleted file mode 100644
index bc4adfaf815c..000000000000
--- a/arch/mn10300/unit-asb2305/unit-init.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* ASB2305 Initialisation
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/processor.h>
-#include <asm/intctl-regs.h>
-#include <asm/serial-regs.h>
-#include <unit/serial.h>
-
-/*
- * initialise some of the unit hardware before gdbstub is set up
- */
-asmlinkage void __init unit_init(void)
-{
-#ifndef CONFIG_GDBSTUB_ON_TTYSx
- /* set the 16550 interrupt line to level 3 if not being used for GDB */
-#ifdef CONFIG_EXT_SERIAL_IRQ_LEVEL
- set_intr_level(XIRQ0, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL));
-#endif
-#endif /* CONFIG_GDBSTUB_ON_TTYSx */
-}
-
-/*
- * initialise the rest of the unit hardware after gdbstub is ready
- */
-void __init unit_setup(void)
-{
-#ifdef CONFIG_PCI
- unit_pci_init();
-#endif
-}
-
-/*
- * initialise the external interrupts used by a unit of this type
- */
-void __init unit_init_IRQ(void)
-{
- unsigned int extnum;
-
- for (extnum = 0; extnum < NR_XIRQS; extnum++) {
- switch (GET_XIRQ_TRIGGER(extnum)) {
- case XIRQ_TRIGGER_HILEVEL:
- case XIRQ_TRIGGER_LOWLEVEL:
- mn10300_set_lateack_irq_type(XIRQ2IRQ(extnum));
- break;
- default:
- break;
- }
- }
-}
diff --git a/arch/mn10300/unit-asb2364/Makefile b/arch/mn10300/unit-asb2364/Makefile
deleted file mode 100644
index b3263ecfc4ff..000000000000
--- a/arch/mn10300/unit-asb2364/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-# Note! Dependencies are done automagically by 'make dep', which also
-# removes any old dependencies. DON'T put your own dependencies here
-# unless it's something special (ie not a .c file).
-#
-# Note 2! The CFLAGS definitions are now in the main makefile...
-
-obj-y := unit-init.o leds.o irq-fpga.o
-
-obj-$(CONFIG_SMSC911X) += smsc911x.o
diff --git a/arch/mn10300/unit-asb2364/include/unit/clock.h b/arch/mn10300/unit-asb2364/include/unit/clock.h
deleted file mode 100644
index d34ac9a7508b..000000000000
--- a/arch/mn10300/unit-asb2364/include/unit/clock.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* clock.h: unit-specific clocks
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * Modified by Matsushita Electric Industrial Co., Ltd.
- * Modifications:
- * 23-Feb-2007 MEI Add define for watchdog timer.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_CLOCK_H
-#define _ASM_UNIT_CLOCK_H
-
-#ifndef __ASSEMBLY__
-
-#define MN10300_IOCLK 100000000UL /* for DDR800 */
-/*#define MN10300_IOCLK 83333333UL */ /* for DDR667 */
-#define MN10300_IOBCLK MN10300_IOCLK /* IOBCLK is equal to IOCLK */
-
-#endif /* !__ASSEMBLY__ */
-
-#define MN10300_WDCLK 27000000UL
-
-#endif /* _ASM_UNIT_CLOCK_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
deleted file mode 100644
index 2901ed344b3d..000000000000
--- a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* ASB2364 FPGA registers
- */
-
-#ifndef _ASM_UNIT_FPGA_REGS_H
-#define _ASM_UNIT_FPGA_REGS_H
-
-#include <asm/cpu-regs.h>
-
-#ifdef __KERNEL__
-
-#define ASB2364_FPGA_REG_RESET_LAN __SYSREG(0xa9001300, u16)
-#define ASB2364_FPGA_REG_RESET_UART __SYSREG(0xa9001304, u16)
-#define ASB2364_FPGA_REG_RESET_I2C __SYSREG(0xa9001308, u16)
-#define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16)
-#define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16)
-
-#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16)
-#define ASB2364_FPGA_REG_IRQ_LAN ASB2364_FPGA_REG_IRQ(0)
-#define ASB2364_FPGA_REG_IRQ_UART ASB2364_FPGA_REG_IRQ(1)
-#define ASB2364_FPGA_REG_IRQ_I2C ASB2364_FPGA_REG_IRQ(2)
-#define ASB2364_FPGA_REG_IRQ_USB ASB2364_FPGA_REG_IRQ(3)
-#define ASB2364_FPGA_REG_IRQ_FPGA ASB2364_FPGA_REG_IRQ(5)
-
-#define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16)
-#define ASB2364_FPGA_REG_MASK_LAN ASB2364_FPGA_REG_MASK(0)
-#define ASB2364_FPGA_REG_MASK_UART ASB2364_FPGA_REG_MASK(1)
-#define ASB2364_FPGA_REG_MASK_I2C ASB2364_FPGA_REG_MASK(2)
-#define ASB2364_FPGA_REG_MASK_USB ASB2364_FPGA_REG_MASK(3)
-#define ASB2364_FPGA_REG_MASK_FPGA ASB2364_FPGA_REG_MASK(5)
-
-#define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16)
-#define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16)
-#define ASB2364_FPGA_REG_CPLD6_SET1 __SYSREG(0xa9002600, u16)
-#define ASB2364_FPGA_REG_CPLD6_SET2 __SYSREG(0xa9002604, u16)
-#define ASB2364_FPGA_REG_CPLD7_SET1 __SYSREG(0xa9002700, u16)
-#define ASB2364_FPGA_REG_CPLD7_SET2 __SYSREG(0xa9002704, u16)
-#define ASB2364_FPGA_REG_CPLD8_SET1 __SYSREG(0xa9002800, u16)
-#define ASB2364_FPGA_REG_CPLD8_SET2 __SYSREG(0xa9002804, u16)
-#define ASB2364_FPGA_REG_CPLD9_SET1 __SYSREG(0xa9002900, u16)
-#define ASB2364_FPGA_REG_CPLD9_SET2 __SYSREG(0xa9002904, u16)
-#define ASB2364_FPGA_REG_CPLD10_SET1 __SYSREG(0xa9002a00, u16)
-#define ASB2364_FPGA_REG_CPLD10_SET2 __SYSREG(0xa9002a04, u16)
-
-#define SyncExBus() \
- do { \
- unsigned short w; \
- w = *(volatile short *)0xa9000000; \
- } while (0)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_UNIT_FPGA_REGS_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/irq.h b/arch/mn10300/unit-asb2364/include/unit/irq.h
deleted file mode 100644
index 786148e46565..000000000000
--- a/arch/mn10300/unit-asb2364/include/unit/irq.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* ASB2364 FPGA irq numbers
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#ifndef _UNIT_IRQ_H
-#define _UNIT_IRQ_H
-
-#ifndef __ASSEMBLY__
-
-#ifdef CONFIG_SMP
-#define NR_CPU_IRQS GxICR_NUM_EXT_IRQS
-#else
-#define NR_CPU_IRQS GxICR_NUM_IRQS
-#endif
-
-enum {
- FPGA_LAN_IRQ = NR_CPU_IRQS,
- FPGA_UART_IRQ,
- FPGA_I2C_IRQ,
- FPGA_USB_IRQ,
- FPGA_RESERVED_IRQ,
- FPGA_FPGA_IRQ,
- NR_IRQS
-};
-
-extern void __init irq_fpga_init(void);
-
-#endif /* !__ASSEMBLY__ */
-#endif /* _UNIT_IRQ_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/leds.h b/arch/mn10300/unit-asb2364/include/unit/leds.h
deleted file mode 100644
index 03a3933ad323..000000000000
--- a/arch/mn10300/unit-asb2364/include/unit/leds.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Unit-specific leds
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_LEDS_H
-#define _ASM_UNIT_LEDS_H
-
-#include <asm/pio-regs.h>
-#include <asm/cpu-regs.h>
-#include <asm/exceptions.h>
-
-#define MN10300_USE_7SEGLEDS 0
-
-#define ASB2364_7SEGLEDS __SYSREG(0xA9001630, u32)
-
-/*
- * use the 7-segment LEDs to indicate states
- */
-
-#if MN10300_USE_7SEGLEDS
-/* flip the 7-segment LEDs between "Gdb-" and "----" */
-#define mn10300_set_gdbleds(ONOFF) \
- do { \
- ASB2364_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f; \
- } while (0)
-#else
-#define mn10300_set_gdbleds(ONOFF) do {} while (0)
-#endif
-
-#if MN10300_USE_7SEGLEDS
-/* indicate double-fault by displaying "db-f" on the LEDs */
-#define mn10300_set_dbfleds \
- mov 0x43077f1d,d0 ; \
- mov d0,(ASB2364_7SEGLEDS)
-#else
-#define mn10300_set_dbfleds
-#endif
-
-#ifndef __ASSEMBLY__
-extern void peripheral_leds_display_exception(enum exception_code);
-extern void peripheral_leds_led_chase(void);
-extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int);
-extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int);
-extern void debug_to_serial(const char *, int);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_UNIT_LEDS_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/serial.h b/arch/mn10300/unit-asb2364/include/unit/serial.h
deleted file mode 100644
index 92f224a97efc..000000000000
--- a/arch/mn10300/unit-asb2364/include/unit/serial.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* Unit-specific 8250 serial ports
- *
- * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_UNIT_SERIAL_H
-#define _ASM_UNIT_SERIAL_H
-
-#include <asm/cpu-regs.h>
-#include <proc/irq.h>
-#include <unit/fpga-regs.h>
-#include <linux/serial_reg.h>
-
-#define SERIAL_PORT0_BASE_ADDRESS 0xA8200000
-
-#define SERIAL_IRQ XIRQ1 /* single serial (TL16C550C) (Lo) */
-
-/*
- * The ASB2364 has an 12.288 MHz clock
- * for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- */
-#define BASE_BAUD (12288000 / 16)
-
-/*
- * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports
- */
-#ifndef CONFIG_GDBSTUB_ON_TTYSx
-
-#define SERIAL_PORT_DFNS \
- { \
- .baud_base = BASE_BAUD, \
- .irq = SERIAL_IRQ, \
- .flags = STD_COM_FLAGS, \
- .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \
- .iomem_reg_shift = 1, \
- .io_type = SERIAL_IO_MEM, \
- },
-
-#ifndef __ASSEMBLY__
-
-static inline void __debug_to_serial(const char *p, int n)
-{
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#else /* CONFIG_GDBSTUB_ON_TTYSx */
-
-#define SERIAL_PORT_DFNS /* stolen by gdb-stub */
-
-#if defined(CONFIG_GDBSTUB_ON_TTYS0)
-#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 2, u8)
-#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 2, u8)
-#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 2, u8)
-#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 2, u8)
-#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)
-#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 2, u8)
-#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8)
-#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8)
-#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 2, u8)
-#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 2, u8)
-#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 2, u8)
-#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 2, u8)
-#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
-
-#elif defined(CONFIG_GDBSTUB_ON_TTYS1)
-#error The ASB2364 does not have a /dev/ttyS1
-#endif
-
-#ifndef __ASSEMBLY__
-
-static inline void __debug_to_serial(const char *p, int n)
-{
- char ch;
-
-#define LSR_WAIT_FOR(STATE) \
- do {} while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE))
-#define FLOWCTL_QUERY(LINE) \
- ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; })
-#define FLOWCTL_WAIT_FOR(LINE) \
- do {} while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE))
-#define FLOWCTL_CLEAR(LINE) \
- do { GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; } while (0)
-#define FLOWCTL_SET(LINE) \
- do { GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; } while (0)
-
- FLOWCTL_SET(DTR);
-
- for (; n > 0; n--) {
- LSR_WAIT_FOR(THRE);
- FLOWCTL_WAIT_FOR(CTS);
-
- ch = *p++;
- if (ch == 0x0a) {
- GDBPORT_SERIAL_TX = 0x0d;
- LSR_WAIT_FOR(THRE);
- FLOWCTL_WAIT_FOR(CTS);
- }
- GDBPORT_SERIAL_TX = ch;
- }
-
- FLOWCTL_CLEAR(DTR);
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* CONFIG_GDBSTUB_ON_TTYSx */
-
-#define SERIAL_INITIALIZE \
-do { \
- /* release reset */ \
- ASB2364_FPGA_REG_RESET_UART = 0x0001; \
- SyncExBus(); \
-} while (0)
-
-#define SERIAL_CHECK_INTERRUPT \
-do { \
- if ((ASB2364_FPGA_REG_IRQ_UART & 0x0001) == 0x0001) { \
- return IRQ_NONE; \
- } \
-} while (0)
-
-#define SERIAL_CLEAR_INTERRUPT \
-do { \
- ASB2364_FPGA_REG_IRQ_UART = 0x0001; \
- SyncExBus(); \
-} while (0)
-
-#define SERIAL_SET_INT_MASK \
-do { \
- ASB2364_FPGA_REG_MASK_UART = 0x0001; \
- SyncExBus(); \
-} while (0)
-
-#define SERIAL_CLEAR_INT_MASK \
-do { \
- ASB2364_FPGA_REG_MASK_UART = 0x0000; \
- SyncExBus(); \
-} while (0)
-
-#endif /* _ASM_UNIT_SERIAL_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/smsc911x.h b/arch/mn10300/unit-asb2364/include/unit/smsc911x.h
deleted file mode 100644
index 4c1ede535fa9..000000000000
--- a/arch/mn10300/unit-asb2364/include/unit/smsc911x.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Support for the SMSC911x NIC
- *
- * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd.
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_UNIT_SMSC911X_H
-#define _ASM_UNIT_SMSC911X_H
-
-#include <linux/netdevice.h>
-#include <proc/irq.h>
-#include <unit/fpga-regs.h>
-
-#define MN10300_USE_EXT_EEPROM
-
-
-#define SMSC911X_BASE 0xA8000000UL
-#define SMSC911X_BASE_END 0xA8000100UL
-#define SMSC911X_IRQ FPGA_LAN_IRQ
-
-/*
- * Allow the FPGA to be initialised by the SMSC911x driver
- */
-#undef SMSC_INITIALIZE
-#define SMSC_INITIALIZE() \
-do { \
- /* release reset */ \
- ASB2364_FPGA_REG_RESET_LAN = 0x0001; \
- SyncExBus(); \
-} while (0)
-
-#ifdef MN10300_USE_EXT_EEPROM
-#include <linux/delay.h>
-#include <unit/clock.h>
-
-#define EEPROM_ADDRESS 0xA0
-#define MAC_OFFSET 0x0008
-#define USE_IIC_CH 0 /* 0 or 1 */
-#define IIC_OFFSET (0x80000 * USE_IIC_CH)
-#define IIC_DTRM __SYSREG(0xd8400000 + IIC_OFFSET, u32)
-#define IIC_DREC __SYSREG(0xd8400004 + IIC_OFFSET, u32)
-#define IIC_MYADD __SYSREG(0xd8400008 + IIC_OFFSET, u32)
-#define IIC_CLK __SYSREG(0xd840000c + IIC_OFFSET, u32)
-#define IIC_BRST __SYSREG(0xd8400010 + IIC_OFFSET, u32)
-#define IIC_HOLD __SYSREG(0xd8400014 + IIC_OFFSET, u32)
-#define IIC_BSTS __SYSREG(0xd8400018 + IIC_OFFSET, u32)
-#define IIC_ICR __SYSREG(0xd4000080 + 4 * USE_IIC_CH, u16)
-
-#define IIC_CLK_PLS ((unsigned short)(MN10300_IOCLK / 100000 - 1))
-#define IIC_CLK_LOW ((unsigned short)(IIC_CLK_PLS / 2))
-
-#define SYS_IIC_DTRM_Bit_STA ((unsigned short)0x0400)
-#define SYS_IIC_DTRM_Bit_STO ((unsigned short)0x0200)
-#define SYS_IIC_DTRM_Bit_ACK ((unsigned short)0x0100)
-#define SYS_IIC_DTRM_Bit_DATA ((unsigned short)0x00FF)
-
-static inline void POLL_INT_REQ(volatile u16 *icr)
-{
- unsigned long flags;
- u16 tmp;
-
- while (!(*icr & GxICR_REQUEST))
- ;
- flags = arch_local_cli_save();
- tmp = *icr;
- *icr = (tmp & GxICR_LEVEL) | GxICR_DETECT;
- tmp = *icr;
- arch_local_irq_restore(flags);
-}
-
-/*
- * Implement the SMSC911x hook for MAC address retrieval
- */
-#undef smsc_get_mac
-static inline int smsc_get_mac(struct net_device *dev)
-{
- unsigned char *mac_buf = dev->dev_addr;
- int i;
- unsigned short value;
- unsigned int data;
- int mac_length = 6;
- int check;
- u16 orig_gicr, tmp;
- unsigned long flags;
-
- /* save original GnICR and clear GnICR.IE */
- flags = arch_local_cli_save();
- orig_gicr = IIC_ICR;
- IIC_ICR = orig_gicr & GxICR_LEVEL;
- tmp = IIC_ICR;
- arch_local_irq_restore(flags);
-
- IIC_MYADD = 0x00000008;
- IIC_CLK = (IIC_CLK_LOW << 16) + (IIC_CLK_PLS);
- /* bus hung recovery */
-
- while (1) {
- check = 0;
- for (i = 0; i < 3; i++) {
- if ((IIC_BSTS & 0x00000003) == 0x00000003)
- check++;
- udelay(3);
- }
-
- if (check == 3) {
- IIC_BRST = 0x00000003;
- break;
- } else {
- for (i = 0; i < 3; i++) {
- IIC_BRST = 0x00000002;
- udelay(8);
- IIC_BRST = 0x00000003;
- udelay(8);
- }
- }
- }
-
- IIC_BRST = 0x00000002;
- IIC_BRST = 0x00000003;
-
- value = SYS_IIC_DTRM_Bit_STA | SYS_IIC_DTRM_Bit_ACK;
- value |= (((unsigned short)EEPROM_ADDRESS & SYS_IIC_DTRM_Bit_DATA) |
- (unsigned short)0x0000);
- IIC_DTRM = value;
- POLL_INT_REQ(&IIC_ICR);
-
- /** send offset of MAC address in EEPROM **/
- IIC_DTRM = (unsigned char)((MAC_OFFSET & 0xFF00) >> 8);
- POLL_INT_REQ(&IIC_ICR);
-
- IIC_DTRM = (unsigned char)(MAC_OFFSET & 0x00FF);
- POLL_INT_REQ(&IIC_ICR);
-
- udelay(1000);
-
- value = SYS_IIC_DTRM_Bit_STA;
- value |= (((unsigned short)EEPROM_ADDRESS & SYS_IIC_DTRM_Bit_DATA) |
- (unsigned short)0x0001);
- IIC_DTRM = value;
- POLL_INT_REQ(&IIC_ICR);
-
- IIC_DTRM = 0x00000000;
- while (mac_length > 0) {
- POLL_INT_REQ(&IIC_ICR);
-
- data = IIC_DREC;
- mac_length--;
- if (mac_length == 0)
- value = 0x00000300; /* stop IIC bus */
- else if (mac_length == 1)
- value = 0x00000100; /* no ack */
- else
- value = 0x00000000; /* ack */
- IIC_DTRM = value;
- *mac_buf++ = (unsigned char)(data & 0xff);
- }
-
- /* restore GnICR.LV and GnICR.IE */
- flags = arch_local_cli_save();
- IIC_ICR = (orig_gicr & (GxICR_LEVEL | GxICR_ENABLE));
- tmp = IIC_ICR;
- arch_local_irq_restore(flags);
-
- return 0;
-}
-#endif /* MN10300_USE_EXT_EEPROM */
-#endif /* _ASM_UNIT_SMSC911X_H */
diff --git a/arch/mn10300/unit-asb2364/include/unit/timex.h b/arch/mn10300/unit-asb2364/include/unit/timex.h
deleted file mode 100644
index 42f32db75087..000000000000
--- a/arch/mn10300/unit-asb2364/include/unit/timex.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* timex.h: MN2WS0038 architecture timer specifications
- *
- * Copyright (C) 2002, 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_UNIT_TIMEX_H
-#define _ASM_UNIT_TIMEX_H
-
-#include <asm/timer-regs.h>
-#include <unit/clock.h>
-#include <asm/param.h>
-
-/*
- * jiffies counter specifications
- */
-
-#define TMJCBR_MAX 0xffffff /* 24bit */
-#define TMJCIRQ TMTIRQ
-
-#ifndef __ASSEMBLY__
-
-#define MN10300_SRC_IOBCLK MN10300_IOBCLK
-
-#ifndef HZ
-# error HZ undeclared.
-#endif /* !HZ */
-
-#define MN10300_JCCLK (MN10300_SRC_IOBCLK)
-#define MN10300_TSCCLK (MN10300_SRC_IOBCLK)
-
-#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ)
-#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ)
-
-/* Check bit width of MTM interval value that sets base register */
-#if (MN10300_JC_PER_HZ - 1) > TMJCBR_MAX
-# error MTM tick timer interval value is overflow.
-#endif
-
-static inline void stop_jiffies_counter(void)
-{
- u16 tmp;
- TMTMD = 0;
- tmp = TMTMD;
-}
-
-static inline void reload_jiffies_counter(u32 cnt)
-{
- u32 tmp;
-
- TMTBR = cnt;
- tmp = TMTBR;
-
- TMTMD = TMTMD_TMTLDE;
- TMTMD = TMTMD_TMTCNE;
- tmp = TMTMD;
-}
-
-#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS) && \
- !defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
-/*
- * If we aren't using broadcasting, each core needs its own event timer.
- * Since CPU0 uses the tick timer which is 24-bits, we use timer 4 & 5
- * cascaded to 32-bits for CPU1 (but only really use 24-bits to match
- * CPU0).
- */
-
-#define TMJC1IRQ TM5IRQ
-
-static inline void stop_jiffies_counter1(void)
-{
- u8 tmp;
- TM4MD = 0;
- TM5MD = 0;
- tmp = TM4MD;
- tmp = TM5MD;
-}
-
-static inline void reload_jiffies_counter1(u32 cnt)
-{
- u32 tmp;
-
- TM45BR = cnt;
- tmp = TM45BR;
-
- TM4MD = TM4MD_INIT_COUNTER;
- tmp = TM4MD;
-
- TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_INIT_COUNTER;
- TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_COUNT_ENABLE;
- tmp = TM5MD;
-
- TM4MD = TM4MD_COUNT_ENABLE;
- tmp = TM4MD;
-}
-#endif /* CONFIG_SMP&GENERIC_CLOCKEVENTS&!GENERIC_CLOCKEVENTS_BROADCAST */
-
-#endif /* !__ASSEMBLY__ */
-
-
-/*
- * timestamp counter specifications
- */
-#define TMTSCBR_MAX 0xffffffff
-
-#ifndef __ASSEMBLY__
-
-/* Use 32-bit timestamp counter */
-#define TMTSCMD TMSMD
-#define TMTSCBR TMSBR
-#define TMTSCBC TMSBC
-#define TMTSCICR TMSICR
-
-static inline void startup_timestamp_counter(void)
-{
- u32 sync;
-
- /* set up TMS(Timestamp) 32bit timer register to count real time
- * - count down from 4Gig-1 to 0 and wrap at IOBCLK rate
- */
-
- TMTSCBR = TMTSCBR_MAX;
- sync = TMTSCBR;
-
- TMTSCICR = 0;
- sync = TMTSCICR;
-
- TMTSCMD = TMTMD_TMTLDE;
- TMTSCMD = TMTMD_TMTCNE;
- sync = TMTSCMD;
-}
-
-static inline void shutdown_timestamp_counter(void)
-{
- TMTSCMD = 0;
-}
-
-/*
- * we use a cascaded pair of 16-bit down-counting timers to count I/O
- * clock cycles for the purposes of time keeping
- */
-typedef unsigned long cycles_t;
-
-static inline cycles_t read_timestamp_counter(void)
-{
- return (cycles_t)~TMTSCBC;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_UNIT_TIMEX_H */
diff --git a/arch/mn10300/unit-asb2364/irq-fpga.c b/arch/mn10300/unit-asb2364/irq-fpga.c
deleted file mode 100644
index 073e2ccc4a44..000000000000
--- a/arch/mn10300/unit-asb2364/irq-fpga.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* ASB2364 FPGA interrupt multiplexing
- *
- * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <unit/fpga-regs.h>
-
-/*
- * FPGA PIC operations
- */
-static void asb2364_fpga_mask(struct irq_data *d)
-{
- ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001;
- SyncExBus();
-}
-
-static void asb2364_fpga_ack(struct irq_data *d)
-{
- ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001;
- SyncExBus();
-}
-
-static void asb2364_fpga_mask_ack(struct irq_data *d)
-{
- ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001;
- SyncExBus();
-}
-
-static void asb2364_fpga_unmask(struct irq_data *d)
-{
- ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0000;
- SyncExBus();
-}
-
-static struct irq_chip asb2364_fpga_pic = {
- .name = "fpga",
- .irq_ack = asb2364_fpga_ack,
- .irq_mask = asb2364_fpga_mask,
- .irq_mask_ack = asb2364_fpga_mask_ack,
- .irq_unmask = asb2364_fpga_unmask,
-};
-
-/*
- * FPGA PIC interrupt handler
- */
-static irqreturn_t fpga_interrupt(int irq, void *_mask)
-{
- if ((ASB2364_FPGA_REG_IRQ_LAN & 0x0001) != 0x0001)
- generic_handle_irq(FPGA_LAN_IRQ);
- if ((ASB2364_FPGA_REG_IRQ_UART & 0x0001) != 0x0001)
- generic_handle_irq(FPGA_UART_IRQ);
- if ((ASB2364_FPGA_REG_IRQ_I2C & 0x0001) != 0x0001)
- generic_handle_irq(FPGA_I2C_IRQ);
- if ((ASB2364_FPGA_REG_IRQ_USB & 0x0001) != 0x0001)
- generic_handle_irq(FPGA_USB_IRQ);
- if ((ASB2364_FPGA_REG_IRQ_FPGA & 0x0001) != 0x0001)
- generic_handle_irq(FPGA_FPGA_IRQ);
-
- return IRQ_HANDLED;
-}
-
-/*
- * Define an interrupt action for each FPGA PIC output
- */
-static struct irqaction fpga_irq[] = {
- [0] = {
- .handler = fpga_interrupt,
- .flags = IRQF_SHARED,
- .name = "fpga",
- },
-};
-
-/*
- * Initialise the FPGA's PIC
- */
-void __init irq_fpga_init(void)
-{
- int irq;
-
- ASB2364_FPGA_REG_MASK_LAN = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_MASK_UART = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_MASK_I2C = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_MASK_USB = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_MASK_FPGA = 0x0001;
- SyncExBus();
-
- for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++)
- irq_set_chip_and_handler(irq, &asb2364_fpga_pic,
- handle_level_irq);
-
- /* the FPGA drives the XIRQ1 input on the CPU PIC */
- setup_irq(XIRQ1, &fpga_irq[0]);
-}
diff --git a/arch/mn10300/unit-asb2364/leds.c b/arch/mn10300/unit-asb2364/leds.c
deleted file mode 100644
index 1ff830c372b3..000000000000
--- a/arch/mn10300/unit-asb2364/leds.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* leds.c: ASB2364 peripheral 7seg LEDs x4 support
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/intctl-regs.h>
-#include <asm/rtc-regs.h>
-#include <unit/leds.h>
-
-#if MN10300_USE_7SEGLEDS
-static const u8 asb2364_led_hex_tbl[16] = {
- 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0,
- 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c
-};
-
-static const u32 asb2364_led_chase_tbl[6] = {
- ~0x02020202, /* top - segA */
- ~0x04040404, /* right top - segB */
- ~0x08080808, /* right bottom - segC */
- ~0x10101010, /* bottom - segD */
- ~0x20202020, /* left bottom - segE */
- ~0x40404040, /* left top - segF */
-};
-
-static unsigned asb2364_led_chase;
-
-void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points)
-{
- u32 leds;
-
- leds = asb2364_led_hex_tbl[(val/1000) % 10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[(val/100) % 10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[(val/10) % 10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[val % 10];
- leds |= points^0x01010101;
-
- ASB2364_7SEGLEDS = leds;
-}
-
-void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points)
-{
- u32 leds;
-
- leds = asb2364_led_hex_tbl[(val/1000) % 10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[(val/100) % 10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[(val/10) % 10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[val % 10];
- leds |= points^0x01010101;
-
- ASB2364_7SEGLEDS = leds;
-}
-
-/* display triple horizontal bar and exception code */
-void peripheral_leds_display_exception(enum exception_code code)
-{
- u32 leds;
-
- leds = asb2364_led_hex_tbl[(code/0x100) % 0x10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[(code/0x10) % 0x10];
- leds <<= 8;
- leds |= asb2364_led_hex_tbl[code % 0x10];
- leds |= 0x6d010101;
-
- ASB2364_7SEGLEDS = leds;
-}
-
-void peripheral_leds_led_chase(void)
-{
- ASB2364_7SEGLEDS = asb2364_led_chase_tbl[asb2364_led_chase];
- asb2364_led_chase++;
- if (asb2364_led_chase >= 6)
- asb2364_led_chase = 0;
-}
-#else /* MN10300_USE_7SEGLEDS */
-void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points) { }
-void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points) { }
-void peripheral_leds_display_exception(enum exception_code code) { }
-void peripheral_leds_led_chase(void) { }
-#endif /* MN10300_USE_7SEGLEDS */
diff --git a/arch/mn10300/unit-asb2364/smsc911x.c b/arch/mn10300/unit-asb2364/smsc911x.c
deleted file mode 100644
index 544a73e94c81..000000000000
--- a/arch/mn10300/unit-asb2364/smsc911x.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Specification for the SMSC911x NIC
- *
- * Copyright (C) 2006 Matsushita Electric Industrial Co., Ltd.
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/smsc911x.h>
-#include <unit/smsc911x.h>
-
-static struct smsc911x_platform_config smsc911x_config = {
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .flags = SMSC911X_USE_32BIT,
-};
-
-static struct resource smsc911x_resources[] = {
- [0] = {
- .start = SMSC911X_BASE,
- .end = SMSC911X_BASE_END,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = SMSC911X_IRQ,
- .end = SMSC911X_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- }
-};
-
-/*
- * add platform devices
- */
-static int __init unit_device_init(void)
-{
- platform_device_register(&smsc911x_device);
- return 0;
-}
-
-device_initcall(unit_device_init);
diff --git a/arch/mn10300/unit-asb2364/unit-init.c b/arch/mn10300/unit-asb2364/unit-init.c
deleted file mode 100644
index 6359b41ce7e9..000000000000
--- a/arch/mn10300/unit-asb2364/unit-init.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* ASB2364 initialisation
- *
- * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/param.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <asm/processor.h>
-#include <asm/irq.h>
-#include <asm/intctl-regs.h>
-#include <asm/serial-regs.h>
-#include <unit/fpga-regs.h>
-#include <unit/serial.h>
-#include <unit/smsc911x.h>
-
-#define TTYS0_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)
-#define LAN_IRQ_CFG __SYSREG(SMSC911X_BASE + 0x54, u32)
-#define LAN_INT_EN __SYSREG(SMSC911X_BASE + 0x5c, u32)
-
-/*
- * initialise some of the unit hardware before gdbstub is set up
- */
-asmlinkage void __init unit_init(void)
-{
- /* Make sure we aren't going to get unexpected interrupts */
- TTYS0_SERIAL_IER = 0;
- SC0RXICR = 0;
- SC0TXICR = 0;
- SC1RXICR = 0;
- SC1TXICR = 0;
- SC2RXICR = 0;
- SC2TXICR = 0;
-
- /* Attempt to reset the FPGA attached peripherals */
- ASB2364_FPGA_REG_RESET_LAN = 0x0000;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_UART = 0x0000;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_I2C = 0x0000;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_USB = 0x0000;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_AV = 0x0000;
- SyncExBus();
-
- /* set up the external interrupts */
-
- /* XIRQ[0]: NAND RXBY */
- /* SET_XIRQ_TRIGGER(0, XIRQ_TRIGGER_LOWLEVEL); */
-
- /* XIRQ[1]: LAN, UART, I2C, USB, PCI, FPGA */
- SET_XIRQ_TRIGGER(1, XIRQ_TRIGGER_LOWLEVEL);
-
- /* XIRQ[2]: Extend Slot 1-9 */
- /* SET_XIRQ_TRIGGER(2, XIRQ_TRIGGER_LOWLEVEL); */
-
-#if defined(CONFIG_EXT_SERIAL_IRQ_LEVEL) && \
- defined(CONFIG_ETHERNET_IRQ_LEVEL) && \
- (CONFIG_EXT_SERIAL_IRQ_LEVEL != CONFIG_ETHERNET_IRQ_LEVEL)
-# error CONFIG_EXT_SERIAL_IRQ_LEVEL != CONFIG_ETHERNET_IRQ_LEVEL
-#endif
-
-#if defined(CONFIG_EXT_SERIAL_IRQ_LEVEL)
- set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_EXT_SERIAL_IRQ_LEVEL));
-#elif defined(CONFIG_ETHERNET_IRQ_LEVEL)
- set_intr_level(XIRQ1, NUM2GxICR_LEVEL(CONFIG_ETHERNET_IRQ_LEVEL));
-#endif
-}
-
-/*
- * initialise the rest of the unit hardware after gdbstub is ready
- */
-asmlinkage void __init unit_setup(void)
-{
- /* Release the reset on the SMSC911X so that it is ready by the time we
- * need it */
- ASB2364_FPGA_REG_RESET_LAN = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_UART = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_I2C = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_USB = 0x0001;
- SyncExBus();
- ASB2364_FPGA_REG_RESET_AV = 0x0001;
- SyncExBus();
-
- /* Make sure the ethernet chipset isn't going to give us an interrupt
- * storm from stuff it was doing pre-reset */
- LAN_IRQ_CFG = 0;
- LAN_INT_EN = 0;
-}
-
-/*
- * initialise the external interrupts used by a unit of this type
- */
-void __init unit_init_IRQ(void)
-{
- unsigned int extnum;
-
- for (extnum = 0 ; extnum < NR_XIRQS ; extnum++) {
- switch (GET_XIRQ_TRIGGER(extnum)) {
- /* LEVEL triggered interrupts should be made
- * post-ACK'able as they hold their lines until
- * serviced
- */
- case XIRQ_TRIGGER_HILEVEL:
- case XIRQ_TRIGGER_LOWLEVEL:
- mn10300_set_lateack_irq_type(XIRQ2IRQ(extnum));
- break;
- default:
- break;
- }
- }
-
-#define IRQCTL __SYSREG(0xd5000090, u32)
- IRQCTL |= 0x02;
-
- irq_fpga_init();
-}
diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
new file mode 100644
index 000000000000..249f38d3388f
--- /dev/null
+++ b/arch/nds32/Kconfig
@@ -0,0 +1,103 @@
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+config NDS32
+ def_bool y
+ select ARCH_WANT_FRAME_POINTERS if FTRACE
+ select CLKSRC_MMIO
+ select CLONE_BACKWARDS
+ select COMMON_CLK
+ select GENERIC_ATOMIC64
+ select GENERIC_CPU_DEVICES
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select GENERIC_IRQ_SHOW
+ select GENERIC_STRNCPY_FROM_USER
+ select GENERIC_STRNLEN_USER
+ select GENERIC_TIME_VSYSCALL
+ select HANDLE_DOMAIN_IRQ
+ select HAVE_ARCH_TRACEHOOK
+ select HAVE_DEBUG_KMEMLEAK
+ select HAVE_MEMBLOCK
+ select HAVE_REGS_AND_STACK_ACCESS_API
+ select IRQ_DOMAIN
+ select LOCKDEP_SUPPORT
+ select MODULES_USE_ELF_RELA
+ select OF
+ select OF_EARLY_FLATTREE
+ select NO_BOOTMEM
+ select NO_IOPORT_MAP
+ select RTC_LIB
+ select THREAD_INFO_IN_TASK
+ help
+ Andes(nds32) Linux support.
+
+config GENERIC_CALIBRATE_DELAY
+ def_bool y
+
+config GENERIC_CSUM
+ def_bool y
+
+config GENERIC_HWEIGHT
+ def_bool y
+
+config GENERIC_LOCKBREAK
+ def_bool y
+ depends on PREEMPT
+
+config RWSEM_GENERIC_SPINLOCK
+ def_bool y
+
+config TRACE_IRQFLAGS_SUPPORT
+ def_bool y
+
+config STACKTRACE_SUPPORT
+ def_bool y
+
+config FIX_EARLYCON_MEM
+ def_bool y
+
+config PGTABLE_LEVELS
+ default 2
+
+source "init/Kconfig"
+
+menu "System Type"
+source "arch/nds32/Kconfig.cpu"
+config NR_CPUS
+ int
+ default 1
+
+config MMU
+ def_bool y
+
+config NDS32_BUILTIN_DTB
+ string "Builtin DTB"
+ default ""
+ help
+ User can use it to specify the dts of the SoC
+endmenu
+
+menu "Kernel Features"
+source "kernel/Kconfig.preempt"
+source "mm/Kconfig"
+source "kernel/Kconfig.hz"
+endmenu
+
+menu "Executable file formats"
+source "fs/Kconfig.binfmt"
+endmenu
+
+source "net/Kconfig"
+source "drivers/Kconfig"
+source "fs/Kconfig"
+
+menu "Kernel hacking"
+source "lib/Kconfig.debug"
+endmenu
+
+source "security/Kconfig"
+source "crypto/Kconfig"
+source "lib/Kconfig"
diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu
new file mode 100644
index 000000000000..ba44cc539da9
--- /dev/null
+++ b/arch/nds32/Kconfig.cpu
@@ -0,0 +1,174 @@
+comment "Processor Features"
+
+config CPU_BIG_ENDIAN
+ bool "Big endian"
+
+config CPU_LITTLE_ENDIAN
+ def_bool !CPU_BIG_ENDIAN
+
+config HWZOL
+ bool "hardware zero overhead loop support"
+ depends on CPU_D10 || CPU_D15
+ default n
+ help
+ A set of Zero-Overhead Loop mechanism is provided to reduce the
+ instruction fetch and execution overhead of loop-control instructions.
+ It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
+ You don't need to save these registers if you can make sure your user
+ program doesn't use these registers.
+
+ If unsure, say N.
+
+config CPU_CACHE_ALIASING
+ bool "Aliasing cache"
+ depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
+ default y
+ help
+ If this CPU is using VIPT data cache and its cache way size is larger
+ than page size, say Y. If it is using PIPT data cache, say N.
+
+ If unsure, say Y.
+
+choice
+ prompt "minimum CPU type"
+ default CPU_V3
+ help
+ The data cache of N15/D15 is implemented as PIPT and it will not cause
+ the cache aliasing issue. The rest cpus(N13, N10 and D10) are
+ implemented as VIPT data cache. It may cause the cache aliasing issue
+ if its cache way size is larger than page size. You can specify the
+ CPU type direcly or choose CPU_V3 if unsure.
+
+ A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
+ A kernel built for N15 is able to run on N15 or D15.
+ A kernel built for D10 is able to run on D10 or D15.
+ A kernel built for D15 is able to run on D15.
+ A kernel built for N13 is able to run on N15, N13 or D15.
+
+config CPU_N15
+ bool "AndesCore N15"
+config CPU_N13
+ bool "AndesCore N13"
+ select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
+config CPU_N10
+ bool "AndesCore N10"
+ select CPU_CACHE_ALIASING
+config CPU_D15
+ bool "AndesCore D15"
+config CPU_D10
+ bool "AndesCore D10"
+ select CPU_CACHE_ALIASING
+config CPU_V3
+ bool "AndesCore v3 compatible"
+ select CPU_CACHE_ALIASING
+endchoice
+choice
+ prompt "Paging -- page size "
+ default ANDES_PAGE_SIZE_4KB
+config ANDES_PAGE_SIZE_4KB
+ bool "use 4KB page size"
+config ANDES_PAGE_SIZE_8KB
+ bool "use 8KB page size"
+endchoice
+
+config CPU_ICACHE_DISABLE
+ bool "Disable I-Cache"
+ help
+ Say Y here to disable the processor instruction cache. Unless
+ you have a reason not to or are unsure, say N.
+
+config CPU_DCACHE_DISABLE
+ bool "Disable D-Cache"
+ help
+ Say Y here to disable the processor data cache. Unless
+ you have a reason not to or are unsure, say N.
+
+config CPU_DCACHE_WRITETHROUGH
+ bool "Force write through D-cache"
+ depends on !CPU_DCACHE_DISABLE
+ help
+ Say Y here to use the data cache in writethrough mode. Unless you
+ specifically require this or are unsure, say N.
+
+config WBNA
+ bool "WBNA"
+ default n
+ help
+ Say Y here to enable write-back memory with no-write-allocation policy.
+
+config ALIGNMENT_TRAP
+ bool "Kernel support unaligned access handling by sw"
+ depends on PROC_FS
+ default n
+ help
+ Andes processors cannot load/store information which is not
+ naturally aligned on the bus, i.e., a 4 byte load must start at an
+ address divisible by 4. On 32-bit Andes processors, these non-aligned
+ load/store instructions will be emulated in software if you say Y
+ here, which has a severe performance impact. With an IP-only
+ configuration it is safe to say N, otherwise say Y.
+
+config HW_SUPPORT_UNALIGNMENT_ACCESS
+ bool "Kernel support unaligned access handling by hw"
+ depends on !ALIGNMENT_TRAP
+ default n
+ help
+ Andes processors load/store world/half-word instructions can access
+ unaligned memory locations without generating the Data Alignment
+ Check exceptions. With an IP-only configuration it is safe to say N,
+ otherwise say Y.
+
+config HIGHMEM
+ bool "High Memory Support"
+ depends on MMU && !CPU_CACHE_ALIASING
+ help
+ The address space of Andes processors is only 4 Gigabytes large
+ and it has to accommodate user address space, kernel address
+ space as well as some memory mapped IO. That means that, if you
+ have a large amount of physical memory and/or IO, not all of the
+ memory can be "permanently mapped" by the kernel. The physical
+ memory that is not permanently mapped is called "high memory".
+
+ Depending on the selected kernel/user memory split, minimum
+ vmalloc space and actual amount of RAM, you may not need this
+ option which should result in a slightly faster kernel.
+
+ If unsure, say N.
+
+config CACHE_L2
+ bool "Support L2 cache"
+ default y
+ help
+ Say Y here to enable L2 cache if your SoC are integrated with L2CC.
+ If unsure, say N.
+
+menu "Memory configuration"
+
+choice
+ prompt "Memory split"
+ depends on MMU
+ default VMSPLIT_3G_OPT
+ help
+ Select the desired split between kernel and user memory.
+
+ If you are not absolutely sure what you are doing, leave this
+ option alone!
+
+ config VMSPLIT_3G
+ bool "3G/1G user/kernel split"
+ config VMSPLIT_3G_OPT
+ bool "3G/1G user/kernel split (for full 1G low memory)"
+ config VMSPLIT_2G
+ bool "2G/2G user/kernel split"
+ config VMSPLIT_1G
+ bool "1G/3G user/kernel split"
+endchoice
+
+config PAGE_OFFSET
+ hex
+ default 0x40000000 if VMSPLIT_1G
+ default 0x80000000 if VMSPLIT_2G
+ default 0xB0000000 if VMSPLIT_3G_OPT
+ default 0xC0000000
+
+endmenu
diff --git a/arch/nds32/Makefile b/arch/nds32/Makefile
new file mode 100644
index 000000000000..91f933d5a962
--- /dev/null
+++ b/arch/nds32/Makefile
@@ -0,0 +1,67 @@
+LDFLAGS_vmlinux := --no-undefined -X
+OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment -S
+
+KBUILD_DEFCONFIG := defconfig
+
+comma = ,
+
+KBUILD_CFLAGS += $(call cc-option, -mno-sched-prolog-epilog)
+KBUILD_CFLAGS += -mcmodel=large
+
+KBUILD_CFLAGS +=$(arch-y) $(tune-y)
+KBUILD_AFLAGS +=$(arch-y) $(tune-y)
+
+#Default value
+head-y := arch/nds32/kernel/head.o
+textaddr-y := $(CONFIG_PAGE_OFFSET)+0xc000
+
+TEXTADDR := $(textaddr-y)
+
+export TEXTADDR
+
+
+# If we have a machine-specific directory, then include it in the build.
+core-y += arch/nds32/kernel/ arch/nds32/mm/
+libs-y += arch/nds32/lib/
+LIBGCC_PATH := \
+ $(shell $(CC) $(KBUILD_CFLAGS) $(KCFLAGS) -print-libgcc-file-name)
+libs-y += $(LIBGCC_PATH)
+
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := y
+else
+BUILTIN_DTB := n
+endif
+
+ifdef CONFIG_CPU_LITTLE_ENDIAN
+KBUILD_CFLAGS += $(call cc-option, -EL)
+else
+KBUILD_CFLAGS += $(call cc-option, -EB)
+endif
+
+boot := arch/nds32/boot
+core-$(BUILTIN_DTB) += $(boot)/dts/
+
+.PHONY: FORCE
+
+Image: vmlinux
+ $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+
+
+PHONY += vdso_install
+vdso_install:
+ $(Q)$(MAKE) $(build)=arch/nds32/kernel/vdso $@
+
+prepare: vdso_prepare
+vdso_prepare: prepare0
+ $(Q)$(MAKE) $(build)=arch/nds32/kernel/vdso include/generated/vdso-offsets.h
+
+CLEAN_FILES += include/asm-nds32/constants.h*
+
+# We use MRPROPER_FILES and CLEAN_FILES now
+archclean:
+ $(Q)$(MAKE) $(clean)=$(boot)
+
+define archhelp
+ echo ' Image - kernel image (arch/$(ARCH)/boot/Image)'
+endef
diff --git a/arch/nds32/boot/Makefile b/arch/nds32/boot/Makefile
new file mode 100644
index 000000000000..3f9b86f68d8f
--- /dev/null
+++ b/arch/nds32/boot/Makefile
@@ -0,0 +1,15 @@
+targets := Image Image.gz
+
+$(obj)/Image: vmlinux FORCE
+ $(call if_changed,objcopy)
+
+$(obj)/Image.gz: $(obj)/Image FORCE
+ $(call if_changed,gzip)
+
+install: $(obj)/Image
+ $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+ $(obj)/Image System.map "$(INSTALL_PATH)"
+
+zinstall: $(obj)/Image.gz
+ $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
+ $(obj)/Image.gz System.map "$(INSTALL_PATH)"
diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile
new file mode 100644
index 000000000000..d31faa8a1d50
--- /dev/null
+++ b/arch/nds32/boot/dts/Makefile
@@ -0,0 +1,8 @@
+ifneq '$(CONFIG_NDS32_BUILTIN_DTB)' '""'
+BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_NDS32_BUILTIN_DTB)).dtb.o
+else
+BUILTIN_DTB :=
+endif
+obj-$(CONFIG_OF) += $(BUILTIN_DTB)
+
+clean-files := *.dtb *.dtb.S
diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts
new file mode 100644
index 000000000000..bb39749a6673
--- /dev/null
+++ b/arch/nds32/boot/dts/ae3xx.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+/ {
+ compatible = "andestech,ae3xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "andestech,n13", "andestech,nds32v3";
+ reg = <0>;
+ clock-frequency = <60000000>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ intc: interrupt-controller {
+ compatible = "andestech,ativic32";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ clock: clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ serial0: serial@f0300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0xf0300000 0x1000>;
+ interrupts = <8>;
+ clock-frequency = <14745600>;
+ reg-shift = <2>;
+ reg-offset = <32>;
+ no-loopback-test = <1>;
+ };
+
+ timer0: timer@f0400000 {
+ compatible = "andestech,atcpit100";
+ reg = <0xf0400000 0x1000>;
+ interrupts = <2>;
+ clocks = <&clock>;
+ clock-names = "PCLK";
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ L2: cache-controller@e0500000 {
+ compatible = "andestech,atl2c";
+ reg = <0xe0500000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ mac0: ethernet@e0100000 {
+ compatible = "andestech,atmac100";
+ reg = <0xe0100000 0x1000>;
+ interrupts = <18>;
+ };
+ };
+};
diff --git a/arch/nds32/configs/defconfig b/arch/nds32/configs/defconfig
new file mode 100644
index 000000000000..2546d8770785
--- /dev/null
+++ b/arch/nds32/configs/defconfig
@@ -0,0 +1,104 @@
+CONFIG_CROSS_COMPILE="nds32le-linux-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CACHE_L2 is not set
+CONFIG_PREEMPT=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_FTMAC100=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_USE_LEGACY_DNS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF4=y
+CONFIG_GDB_SCRIPTS=y
+CONFIG_READABLE_ASM=y
+CONFIG_HEADERS_CHECK=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_PANIC_ON_OOPS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=300
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/nds32/include/asm/Kbuild b/arch/nds32/include/asm/Kbuild
new file mode 100644
index 000000000000..06bdf8167f5a
--- /dev/null
+++ b/arch/nds32/include/asm/Kbuild
@@ -0,0 +1,55 @@
+generic-y += asm-offsets.h
+generic-y += atomic.h
+generic-y += bitops.h
+generic-y += bitsperlong.h
+generic-y += bpf_perf_event.h
+generic-y += bug.h
+generic-y += bugs.h
+generic-y += checksum.h
+generic-y += clkdev.h
+generic-y += cmpxchg.h
+generic-y += cmpxchg-local.h
+generic-y += cputime.h
+generic-y += device.h
+generic-y += div64.h
+generic-y += dma.h
+generic-y += emergency-restart.h
+generic-y += errno.h
+generic-y += exec.h
+generic-y += fb.h
+generic-y += fcntl.h
+generic-y += ftrace.h
+generic-y += gpio.h
+generic-y += hardirq.h
+generic-y += hw_irq.h
+generic-y += ioctl.h
+generic-y += ioctls.h
+generic-y += irq.h
+generic-y += irq_regs.h
+generic-y += irq_work.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += kprobes.h
+generic-y += kvm_para.h
+generic-y += limits.h
+generic-y += local.h
+generic-y += mm-arch-hooks.h
+generic-y += mman.h
+generic-y += parport.h
+generic-y += pci.h
+generic-y += percpu.h
+generic-y += preempt.h
+generic-y += sections.h
+generic-y += segment.h
+generic-y += serial.h
+generic-y += shmbuf.h
+generic-y += sizes.h
+generic-y += stat.h
+generic-y += switch_to.h
+generic-y += timex.h
+generic-y += topology.h
+generic-y += trace_clock.h
+generic-y += unaligned.h
+generic-y += user.h
+generic-y += vga.h
+generic-y += word-at-a-time.h
diff --git a/arch/nds32/include/asm/assembler.h b/arch/nds32/include/asm/assembler.h
new file mode 100644
index 000000000000..c3855782a541
--- /dev/null
+++ b/arch/nds32/include/asm/assembler.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASSEMBLER_H__
+#define __NDS32_ASSEMBLER_H__
+
+.macro gie_disable
+ setgie.d
+ dsb
+.endm
+
+.macro gie_enable
+ setgie.e
+ dsb
+.endm
+
+.macro gie_save oldpsw
+ mfsr \oldpsw, $ir0
+ setgie.d
+ dsb
+.endm
+
+.macro gie_restore oldpsw
+ andi \oldpsw, \oldpsw, #0x1
+ beqz \oldpsw, 7001f
+ setgie.e
+ dsb
+7001:
+.endm
+
+
+#define USER(insn, reg, addr, opr) \
+9999: insn reg, addr, opr; \
+ .section __ex_table,"a"; \
+ .align 3; \
+ .long 9999b, 9001f; \
+ .previous
+
+#endif /* __NDS32_ASSEMBLER_H__ */
diff --git a/arch/nds32/include/asm/barrier.h b/arch/nds32/include/asm/barrier.h
new file mode 100644
index 000000000000..faafc373ea6c
--- /dev/null
+++ b/arch/nds32/include/asm/barrier.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_ASM_BARRIER_H
+#define __NDS32_ASM_BARRIER_H
+
+#ifndef __ASSEMBLY__
+#define mb() asm volatile("msync all":::"memory")
+#define rmb() asm volatile("msync all":::"memory")
+#define wmb() asm volatile("msync store":::"memory")
+#include <asm-generic/barrier.h>
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __NDS32_ASM_BARRIER_H */
diff --git a/arch/nds32/include/asm/bitfield.h b/arch/nds32/include/asm/bitfield.h
new file mode 100644
index 000000000000..c73f71d67744
--- /dev/null
+++ b/arch/nds32/include/asm/bitfield.h
@@ -0,0 +1,963 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BITFIELD_H__
+#define __NDS32_BITFIELD_H__
+/******************************************************************************
+ * cr0: CPU_VER (CPU Version Register)
+ *****************************************************************************/
+#define CPU_VER_offCFGID 0 /* Minor configuration */
+#define CPU_VER_offREV 16 /* Revision of the CPU version */
+#define CPU_VER_offCPUID 24 /* Major CPU versions */
+
+#define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID )
+#define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV )
+#define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID )
+
+/******************************************************************************
+ * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
+ *****************************************************************************/
+#define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */
+#define ICM_CFG_offIWAY 3 /* I-cache ways */
+#define ICM_CFG_offISZ 6 /* I-cache line size */
+#define ICM_CFG_offILCK 9 /* I-cache locking support */
+#define ICM_CFG_offILMB 10 /* On-chip ILM banks */
+#define ICM_CFG_offBSAV 13 /* ILM base register alignment version */
+/* bit 15:31 reserved */
+
+#define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET )
+#define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY )
+#define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ )
+#define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK )
+#define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB )
+#define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV )
+
+/******************************************************************************
+ * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
+ *****************************************************************************/
+#define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */
+#define DCM_CFG_offDWAY 3 /* D-cache ways */
+#define DCM_CFG_offDSZ 6 /* D-cache line size */
+#define DCM_CFG_offDLCK 9 /* D-cache locking support */
+#define DCM_CFG_offDLMB 10 /* On-chip DLM banks */
+#define DCM_CFG_offBSAV 13 /* DLM base register alignment version */
+/* bit 15:31 reserved */
+
+#define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET )
+#define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY )
+#define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ )
+#define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK )
+#define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB )
+#define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV )
+
+/******************************************************************************
+ * cr3: MMU_CFG (MMU Configuration Register)
+ *****************************************************************************/
+#define MMU_CFG_offMMPS 0 /* Memory management protection scheme */
+#define MMU_CFG_offMMPV 2 /* Memory management protection version number */
+#define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */
+
+#define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */
+#define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */
+/* bit 14:14 reserved */
+
+#define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */
+#define MMU_CFG_offfEPSZ 16 /* Extra page size supported */
+#define MMU_CFG_offTLBLCK 24 /* TLB locking support */
+#define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */
+#define MMU_CFG_offDE 26 /* Default endian */
+#define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */
+#define MMU_CFG_offIVTB 28 /* Invisible TLB */
+#define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */
+#define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */
+/* bit 31 reserved */
+
+#define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS )
+#define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV )
+#define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB )
+#define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW )
+#define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS )
+#define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 )
+#define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ )
+#define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK )
+#define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK )
+#define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE )
+#define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT )
+#define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB )
+#define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT )
+#define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME )
+
+/******************************************************************************
+ * cr4: MSC_CFG (Misc Configuration Register)
+ *****************************************************************************/
+#define MSC_CFG_offEDM 0
+#define MSC_CFG_offLMDMA 1
+#define MSC_CFG_offPFM 2
+#define MSC_CFG_offHSMP 3
+#define MSC_CFG_offTRACE 4
+#define MSC_CFG_offDIV 5
+#define MSC_CFG_offMAC 6
+#define MSC_CFG_offAUDIO 7
+#define MSC_CFG_offL2C 9
+#define MSC_CFG_offRDREG 10
+#define MSC_CFG_offADR24 11
+#define MSC_CFG_offINTLC 12
+#define MSC_CFG_offBASEV 13
+#define MSC_CFG_offNOD 16
+/* bit 13:31 reserved */
+
+#define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM )
+#define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA )
+#define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM )
+#define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP )
+#define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE )
+#define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV )
+#define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC )
+#define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO )
+#define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C )
+#define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG )
+#define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 )
+#define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC )
+#define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV )
+#define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD )
+
+/******************************************************************************
+ * cr5: CORE_CFG (Core Identification Register)
+ *****************************************************************************/
+#define CORE_ID_offCOREID 0
+/* bit 4:31 reserved */
+
+#define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID )
+
+/******************************************************************************
+ * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register)
+ *****************************************************************************/
+#define FUCOP_EXIST_offCP0EX 0
+#define FUCOP_EXIST_offCP1EX 1
+#define FUCOP_EXIST_offCP2EX 2
+#define FUCOP_EXIST_offCP3EX 3
+#define FUCOP_EXIST_offCP0ISFPU 31
+
+#define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX )
+#define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX )
+#define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX )
+#define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX )
+#define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU )
+
+/******************************************************************************
+ * ir0: PSW (Processor Status Word Register)
+ * ir1: IPSW (Interruption PSW Register)
+ * ir2: P_IPSW (Previous IPSW Register)
+ *****************************************************************************/
+#define PSW_offGIE 0 /* Global Interrupt Enable */
+#define PSW_offINTL 1 /* Interruption Stack Level */
+#define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */
+#define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */
+#define PSW_offIT 6 /* Enable instruction address translation */
+#define PSW_offDT 7 /* Enable data address translation */
+#define PSW_offIME 8 /* Instruction Machine Error flag */
+#define PSW_offDME 9 /* Data Machine Error flag */
+#define PSW_offDEX 10 /* Debug Exception */
+#define PSW_offHSS 11 /* Hardware Single Stepping */
+#define PSW_offDRBE 12 /* Device Register Endian Mode */
+#define PSW_offAEN 13 /* Audio ISA special feature */
+#define PSW_offWBNA 14 /* Write Back Non-Allocate */
+#define PSW_offIFCON 15 /* IFC On */
+#define PSW_offCPL 16 /* Current Priority Level */
+/* bit 19:31 reserved */
+
+#define PSW_mskGIE ( 0x1 << PSW_offGIE )
+#define PSW_mskINTL ( 0x3 << PSW_offINTL )
+#define PSW_mskPOM ( 0x3 << PSW_offPOM )
+#define PSW_mskBE ( 0x1 << PSW_offBE )
+#define PSW_mskIT ( 0x1 << PSW_offIT )
+#define PSW_mskDT ( 0x1 << PSW_offDT )
+#define PSW_mskIME ( 0x1 << PSW_offIME )
+#define PSW_mskDME ( 0x1 << PSW_offDME )
+#define PSW_mskDEX ( 0x1 << PSW_offDEX )
+#define PSW_mskHSS ( 0x1 << PSW_offHSS )
+#define PSW_mskDRBE ( 0x1 << PSW_offDRBE )
+#define PSW_mskAEN ( 0x1 << PSW_offAEN )
+#define PSW_mskWBNA ( 0x1 << PSW_offWBNA )
+#define PSW_mskIFCON ( 0x1 << PSW_offIFCON )
+#define PSW_mskCPL ( 0x7 << PSW_offCPL )
+
+#define PSW_SYSTEM ( 1 << PSW_offPOM )
+#define PSW_INTL_1 ( 1 << PSW_offINTL )
+#define PSW_CPL_NO ( 0 << PSW_offCPL )
+#define PSW_CPL_ANY ( 7 << PSW_offCPL )
+
+#define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA)
+#ifdef __NDS32_EB__
+#ifdef CONFIG_WBNA
+#define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
+#else
+#define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
+#endif
+#else
+#ifdef CONFIG_WBNA
+#define PSW_init (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
+#else
+#define PSW_init ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
+#endif
+#endif
+/******************************************************************************
+ * ir3: IVB (Interruption Vector Base Register)
+ *****************************************************************************/
+/* bit 0:12 reserved */
+#define IVB_offNIVIC 1 /* Number of input for IVIC Controller */
+#define IVB_offIVIC_VER 11 /* IVIC Version */
+#define IVB_offEVIC 13 /* External Vector Interrupt Controller mode */
+#define IVB_offESZ 14 /* Size of each vector entry */
+#define IVB_offIVBASE 16 /* BasePA of interrupt vector table */
+
+#define IVB_mskNIVIC ( 0x7 << IVB_offNIVIC )
+#define IVB_mskIVIC_VER ( 0x3 << IVB_offIVIC_VER )
+#define IVB_mskEVIC ( 0x1 << IVB_offEVIC )
+#define IVB_mskESZ ( 0x3 << IVB_offESZ )
+#define IVB_mskIVBASE ( 0xFFFF << IVB_offIVBASE )
+
+#define IVB_valESZ4 0
+#define IVB_valESZ16 1
+#define IVB_valESZ64 2
+#define IVB_valESZ256 3
+/******************************************************************************
+ * ir4: EVA (Exception Virtual Address Register)
+ * ir5: P_EVA (Previous EVA Register)
+ *****************************************************************************/
+
+ /* This register contains the VA that causes the exception */
+
+/******************************************************************************
+ * ir6: ITYPE (Interruption Type Register)
+ * ir7: P_ITYPE (Previous ITYPE Register)
+ *****************************************************************************/
+#define ITYPE_offETYPE 0 /* Exception Type */
+#define ITYPE_offINST 4 /* Exception caused by insn fetch or data access */
+/* bit 5:15 reserved */
+#define ITYPE_offVECTOR 5 /* Vector */
+#define ITYPE_offSWID 16 /* SWID of debugging exception */
+/* bit 31:31 reserved */
+
+#define ITYPE_mskETYPE ( 0xF << ITYPE_offETYPE )
+#define ITYPE_mskINST ( 0x1 << ITYPE_offINST )
+#define ITYPE_mskVECTOR ( 0x7F << ITYPE_offVECTOR )
+#define ITYPE_mskSWID ( 0x7FFF << ITYPE_offSWID )
+
+/* Additional definitions for ITYPE register */
+#define ITYPE_offSTYPE 16 /* Arithmetic Sub Type */
+#define ITYPE_offCPID 20 /* Co-Processor ID which generate the exception */
+
+#define ITYPE_mskSTYPE ( 0xF << ITYPE_offSTYPE )
+#define ITYPE_mskCPID ( 0x3 << ITYPE_offCPID )
+
+#define NDS32_VECTOR_mskNONEXCEPTION 0x78
+#define NDS32_VECTOR_offEXCEPTION 8
+#define NDS32_VECTOR_offINTERRUPT 9
+
+/* Interrupt vector entry */
+#define ENTRY_RESET_NMI 0
+#define ENTRY_TLB_FILL 1
+#define ENTRY_PTE_NOT_PRESENT 2
+#define ENTRY_TLB_MISC 3
+#define ENTRY_TLB_VLPT_MISS 4
+#define ENTRY_MACHINE_ERROR 5
+#define ENTRY_DEBUG_RELATED 6
+#define ENTRY_GENERAL_EXCPETION 7
+#define ENTRY_SYSCALL 8
+
+/* PTE not present exception definition */
+#define ETYPE_NON_LEAF_PTE_NOT_PRESENT 0
+#define ETYPE_LEAF_PTE_NOT_PRESENT 1
+
+/* General exception ETYPE definition */
+#define ETYPE_ALIGNMENT_CHECK 0
+#define ETYPE_RESERVED_INSTRUCTION 1
+#define ETYPE_TRAP 2
+#define ETYPE_ARITHMETIC 3
+#define ETYPE_PRECISE_BUS_ERROR 4
+#define ETYPE_IMPRECISE_BUS_ERROR 5
+#define ETYPE_COPROCESSOR 6
+#define ETYPE_RESERVED_VALUE 7
+#define ETYPE_NONEXISTENT_MEM_ADDRESS 8
+#define ETYPE_MPZIU_CONTROL 9
+#define ETYPE_NEXT_PRECISE_STACK_OFL 10
+
+/* Kerenl reserves software ID */
+#define SWID_RAISE_INTERRUPT_LEVEL 0x1a /* SWID_RAISE_INTERRUPT_LEVEL is used to
+ * raise interrupt level for debug exception
+ */
+
+/******************************************************************************
+ * ir8: MERR (Machine Error Log Register)
+ *****************************************************************************/
+/* bit 0:30 reserved */
+#define MERR_offBUSERR 31 /* Bus error caused by a load insn */
+
+#define MERR_mskBUSERR ( 0x1 << MERR_offBUSERR )
+
+/******************************************************************************
+ * ir9: IPC (Interruption Program Counter Register)
+ * ir10: P_IPC (Previous IPC Register)
+ * ir11: OIPC (Overflow Interruption Program Counter Register)
+ *****************************************************************************/
+
+ /* This is the shadow stack register of the Program Counter */
+
+/******************************************************************************
+ * ir12: P_P0 (Previous P0 Register)
+ * ir13: P_P1 (Previous P1 Register)
+ *****************************************************************************/
+
+ /* These are shadow registers of $p0 and $p1 */
+
+/******************************************************************************
+ * ir14: INT_MASK (Interruption Masking Register)
+ *****************************************************************************/
+#define INT_MASK_offH0IM 0 /* Hardware Interrupt 0 Mask bit */
+#define INT_MASK_offH1IM 1 /* Hardware Interrupt 1 Mask bit */
+#define INT_MASK_offH2IM 2 /* Hardware Interrupt 2 Mask bit */
+#define INT_MASK_offH3IM 3 /* Hardware Interrupt 3 Mask bit */
+#define INT_MASK_offH4IM 4 /* Hardware Interrupt 4 Mask bit */
+#define INT_MASK_offH5IM 5 /* Hardware Interrupt 5 Mask bit */
+/* bit 6:15 reserved */
+#define INT_MASK_offSIM 16 /* Software Interrupt Mask bit */
+/* bit 17:29 reserved */
+#define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */
+#define INT_MASK_offDSSIM 31 /* Default Single Stepping Interruption Mask */
+
+#define INT_MASK_mskH0IM ( 0x1 << INT_MASK_offH0IM )
+#define INT_MASK_mskH1IM ( 0x1 << INT_MASK_offH1IM )
+#define INT_MASK_mskH2IM ( 0x1 << INT_MASK_offH2IM )
+#define INT_MASK_mskH3IM ( 0x1 << INT_MASK_offH3IM )
+#define INT_MASK_mskH4IM ( 0x1 << INT_MASK_offH4IM )
+#define INT_MASK_mskH5IM ( 0x1 << INT_MASK_offH5IM )
+#define INT_MASK_mskSIM ( 0x1 << INT_MASK_offSIM )
+#define INT_MASK_mskIDIVZE ( 0x1 << INT_MASK_offIDIVZE )
+#define INT_MASK_mskDSSIM ( 0x1 << INT_MASK_offDSSIM )
+
+#define INT_MASK_INITAIAL_VAL 0x10003
+
+/******************************************************************************
+ * ir15: INT_PEND (Interrupt Pending Register)
+ *****************************************************************************/
+#define INT_PEND_offH0I 0 /* Hardware Interrupt 0 pending bit */
+#define INT_PEND_offH1I 1 /* Hardware Interrupt 1 pending bit */
+#define INT_PEND_offH2I 2 /* Hardware Interrupt 2 pending bit */
+#define INT_PEND_offH3I 3 /* Hardware Interrupt 3 pending bit */
+#define INT_PEND_offH4I 4 /* Hardware Interrupt 4 pending bit */
+#define INT_PEND_offH5I 5 /* Hardware Interrupt 5 pending bit */
+
+#define INT_PEND_offCIPL 0 /* Current Interrupt Priority Level */
+
+/* bit 6:15 reserved */
+#define INT_PEND_offSWI 16 /* Software Interrupt pending bit */
+/* bit 17:31 reserved */
+
+#define INT_PEND_mskH0I ( 0x1 << INT_PEND_offH0I )
+#define INT_PEND_mskH1I ( 0x1 << INT_PEND_offH1I )
+#define INT_PEND_mskH2I ( 0x1 << INT_PEND_offH2I )
+#define INT_PEND_mskH3I ( 0x1 << INT_PEND_offH3I )
+#define INT_PEND_mskH4I ( 0x1 << INT_PEND_offH4I )
+#define INT_PEND_mskH5I ( 0x1 << INT_PEND_offH5I )
+#define INT_PEND_mskCIPL ( 0x1 << INT_PEND_offCIPL )
+#define INT_PEND_mskSWI ( 0x1 << INT_PEND_offSWI )
+
+/******************************************************************************
+ * mr0: MMU_CTL (MMU Control Register)
+ *****************************************************************************/
+#define MMU_CTL_offD 0 /* Default minimum page size */
+#define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */
+#define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */
+#define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */
+#define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */
+#define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */
+#define MMU_CTL_offMPZIU 10 /* Multiple Page Size In Use bit */
+#define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */
+#define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */
+#define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */
+#define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */
+#define MMU_CTL_offUNA 23 /* Unaligned access */
+/* bit 24:31 reserved */
+
+#define MMU_CTL_mskD ( 0x1 << MMU_CTL_offD )
+#define MMU_CTL_mskNTC0 ( 0x3 << MMU_CTL_offNTC0 )
+#define MMU_CTL_mskNTC1 ( 0x3 << MMU_CTL_offNTC1 )
+#define MMU_CTL_mskNTC2 ( 0x3 << MMU_CTL_offNTC2 )
+#define MMU_CTL_mskNTC3 ( 0x3 << MMU_CTL_offNTC3 )
+#define MMU_CTL_mskTBALCK ( 0x1 << MMU_CTL_offTBALCK )
+#define MMU_CTL_mskMPZIU ( 0x1 << MMU_CTL_offMPZIU )
+#define MMU_CTL_mskNTM0 ( 0x3 << MMU_CTL_offNTM0 )
+#define MMU_CTL_mskNTM1 ( 0x3 << MMU_CTL_offNTM1 )
+#define MMU_CTL_mskNTM2 ( 0x3 << MMU_CTL_offNTM2 )
+#define MMU_CTL_mskNTM3 ( 0x3 << MMU_CTL_offNTM3 )
+
+#define MMU_CTL_D4KB 0
+#define MMU_CTL_D8KB 1
+#define MMU_CTL_UNA ( 0x1 << MMU_CTL_offUNA )
+
+#define MMU_CTL_CACHEABLE_WB 2
+#define MMU_CTL_CACHEABLE_WT 3
+
+/******************************************************************************
+ * mr1: L1_PPTB (L1 Physical Page Table Base Register)
+ *****************************************************************************/
+#define L1_PPTB_offNV 0 /* Enable Hardware Page Table Walker (HPTWK) */
+/* bit 1:11 reserved */
+#define L1_PPTB_offBASE 12 /* First level physical page table base address */
+
+#define L1_PPTB_mskNV ( 0x1 << L1_PPTB_offNV )
+#define L1_PPTB_mskBASE ( 0xFFFFF << L1_PPTB_offBASE )
+
+/******************************************************************************
+ * mr2: TLB_VPN (TLB Access VPN Register)
+ *****************************************************************************/
+/* bit 0:11 reserved */
+#define TLB_VPN_offVPN 12 /* Virtual Page Number */
+
+#define TLB_VPN_mskVPN ( 0xFFFFF << TLB_VPN_offVPN )
+
+/******************************************************************************
+ * mr3: TLB_DATA (TLB Access Data Register)
+ *****************************************************************************/
+#define TLB_DATA_offV 0 /* PTE is valid and present */
+#define TLB_DATA_offM 1 /* Page read/write access privilege */
+#define TLB_DATA_offD 4 /* Dirty bit */
+#define TLB_DATA_offX 5 /* Executable bit */
+#define TLB_DATA_offA 6 /* Access bit */
+#define TLB_DATA_offG 7 /* Global page (shared across contexts) */
+#define TLB_DATA_offC 8 /* Cacheability atribute */
+/* bit 11:11 reserved */
+#define TLB_DATA_offPPN 12 /* Phisical Page Number */
+
+#define TLB_DATA_mskV ( 0x1 << TLB_DATA_offV )
+#define TLB_DATA_mskM ( 0x7 << TLB_DATA_offM )
+#define TLB_DATA_mskD ( 0x1 << TLB_DATA_offD )
+#define TLB_DATA_mskX ( 0x1 << TLB_DATA_offX )
+#define TLB_DATA_mskA ( 0x1 << TLB_DATA_offA )
+#define TLB_DATA_mskG ( 0x1 << TLB_DATA_offG )
+#define TLB_DATA_mskC ( 0x7 << TLB_DATA_offC )
+#define TLB_DATA_mskPPN ( 0xFFFFF << TLB_DATA_offPPN )
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|TLB_DATA_mskC)
+#else
+#define TLB_DATA_kernel_text_attr (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|(0x6 << TLB_DATA_offC))
+#endif
+
+/******************************************************************************
+ * mr4: TLB_MISC (TLB Access Misc Register)
+ *****************************************************************************/
+#define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */
+#define TLB_MISC_offCID 4 /* Context id */
+/* bit 13:31 reserved */
+
+#define TLB_MISC_mskACC_PSZ ( 0xF << TLB_MISC_offACC_PSZ )
+#define TLB_MISC_mskCID ( 0x1FF << TLB_MISC_offCID )
+
+/******************************************************************************
+ * mr5: VLPT_IDX (Virtual Linear Page Table Index Register)
+ *****************************************************************************/
+#define VLPT_IDX_offZERO 0 /* Always 0 */
+#define VLPT_IDX_offEVPN 2 /* Exception Virtual Page Number */
+#define VLPT_IDX_offVLPTB 22 /* Base VA of VLPT */
+
+#define VLPT_IDX_mskZERO ( 0x3 << VLPT_IDX_offZERO )
+#define VLPT_IDX_mskEVPN ( 0xFFFFF << VLPT_IDX_offEVPN )
+#define VLPT_IDX_mskVLPTB ( 0x3FF << VLPT_IDX_offVLPTB )
+
+/******************************************************************************
+ * mr6: ILMB (Instruction Local Memory Base Register)
+ *****************************************************************************/
+#define ILMB_offIEN 0 /* Enable ILM */
+#define ILMB_offILMSZ 1 /* Size of ILM */
+/* bit 5:19 reserved */
+#define ILMB_offIBPA 20 /* Base PA of ILM */
+
+#define ILMB_mskIEN ( 0x1 << ILMB_offIEN )
+#define ILMB_mskILMSZ ( 0xF << ILMB_offILMSZ )
+#define ILMB_mskIBPA ( 0xFFF << ILMB_offIBPA )
+
+/******************************************************************************
+ * mr7: DLMB (Data Local Memory Base Register)
+ *****************************************************************************/
+#define DLMB_offDEN 0 /* Enable DLM */
+#define DLMB_offDLMSZ 1 /* Size of DLM */
+#define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */
+#define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */
+/* bit 7:19 reserved */
+#define DLMB_offDBPA 20 /* Base PA of DLM */
+
+#define DLMB_mskDEN ( 0x1 << DLMB_offDEN )
+#define DLMB_mskDLMSZ ( 0xF << DLMB_offDLMSZ )
+#define DLMB_mskDBM ( 0x1 << DLMB_offDBM )
+#define DLMB_mskDBB ( 0x1 << DLMB_offDBB )
+#define DLMB_mskDBPA ( 0xFFF << DLMB_offDBPA )
+
+/******************************************************************************
+ * mr8: CACHE_CTL (Cache Control Register)
+ *****************************************************************************/
+#define CACHE_CTL_offIC_EN 0 /* Enable I-cache */
+#define CACHE_CTL_offDC_EN 1 /* Enable D-cache */
+#define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */
+#define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */
+#define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */
+#define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */
+/* bit 6:31 reserved */
+
+#define CACHE_CTL_mskIC_EN ( 0x1 << CACHE_CTL_offIC_EN )
+#define CACHE_CTL_mskDC_EN ( 0x1 << CACHE_CTL_offDC_EN )
+#define CACHE_CTL_mskICALCK ( 0x1 << CACHE_CTL_offICALCK )
+#define CACHE_CTL_mskDCALCK ( 0x1 << CACHE_CTL_offDCALCK )
+#define CACHE_CTL_mskDCCWF ( 0x1 << CACHE_CTL_offDCCWF )
+#define CACHE_CTL_mskDCPMW ( 0x1 << CACHE_CTL_offDCPMW )
+
+/******************************************************************************
+ * mr9: HSMP_SADDR (High Speed Memory Port Starting Address)
+ *****************************************************************************/
+#define HSMP_SADDR_offEN 0 /* Enable control bit for the High Speed Memory port */
+/* bit 1:19 reserved */
+
+#define HSMP_SADDR_offRANGE 1 /* Denote the address range (only defined in HSMP v2 ) */
+#define HSMP_SADDR_offSADDR 20 /* Starting base PA of the High Speed Memory Port region */
+
+#define HSMP_SADDR_mskEN ( 0x1 << HSMP_SADDR_offEN )
+#define HSMP_SADDR_mskRANGE ( 0xFFF << HSMP_SADDR_offRANGE )
+#define HSMP_SADDR_mskSADDR ( 0xFFF << HSMP_SADDR_offSADDR )
+
+/******************************************************************************
+ * mr10: HSMP_EADDR (High Speed Memory Port Ending Address)
+ *****************************************************************************/
+/* bit 0:19 reserved */
+#define HSMP_EADDR_offEADDR 20
+
+#define HSMP_EADDR_mskEADDR ( 0xFFF << HSMP_EADDR_offEADDR )
+
+/******************************************************************************
+ * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register)
+ *****************************************************************************/
+#define BPC_offWP 0 /* Configuration of BPAn */
+#define BPC_offEL 1 /* Enable BPAn */
+#define BPC_offS 2 /* Data address comparison for a store instruction */
+#define BPC_offP 3 /* Compared data address is PA */
+#define BPC_offC 4 /* CID value is compared with the BPCIDn register */
+#define BPC_offBE0 5 /* Enable byte mask for the comparison with register */
+#define BPC_offBE1 6 /* Enable byte mask for the comparison with register */
+#define BPC_offBE2 7 /* Enable byte mask for the comparison with register */
+#define BPC_offBE3 8 /* Enable byte mask for the comparison with register */
+#define BPC_offT 9 /* Enable breakpoint Embedded Tracer triggering operation */
+
+#define BPC_mskWP ( 0x1 << BPC_offWP )
+#define BPC_mskEL ( 0x1 << BPC_offEL )
+#define BPC_mskS ( 0x1 << BPC_offS )
+#define BPC_mskP ( 0x1 << BPC_offP )
+#define BPC_mskC ( 0x1 << BPC_offC )
+#define BPC_mskBE0 ( 0x1 << BPC_offBE0 )
+#define BPC_mskBE1 ( 0x1 << BPC_offBE1 )
+#define BPC_mskBE2 ( 0x1 << BPC_offBE2 )
+#define BPC_mskBE3 ( 0x1 << BPC_offBE3 )
+#define BPC_mskT ( 0x1 << BPC_offT )
+
+/******************************************************************************
+ * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register)
+ *****************************************************************************/
+
+ /* These registers contain break point address */
+
+/******************************************************************************
+ * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register)
+ *****************************************************************************/
+
+ /* These registerd contain the address comparison mask for the BPAn register */
+
+/******************************************************************************
+ * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register
+ *****************************************************************************/
+
+ /* The BPVn register contains the data value that will be compared with the
+ * incoming load/store data value */
+
+/******************************************************************************
+ * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register)
+ *****************************************************************************/
+#define BPCID_offCID 0 /* CID that will be compared with a process's CID */
+/* bit 9:31 reserved */
+
+#define BPCID_mskCID ( 0x1FF << BPCID_offCID )
+
+/******************************************************************************
+ * dr40: EDM_CFG (EDM Configuration Register)
+ *****************************************************************************/
+#define EDM_CFG_offBC 0 /* Number of hardware breakpoint sets implemented */
+#define EDM_CFG_offDIMU 3 /* Debug Instruction Memory Unit exists */
+/* bit 4:15 reserved */
+#define EDM_CFG_offVER 16 /* EDM version */
+
+#define EDM_CFG_mskBC ( 0x7 << EDM_CFG_offBC )
+#define EDM_CFG_mskDIMU ( 0x1 << EDM_CFG_offDIMU )
+#define EDM_CFG_mskVER ( 0xFFFF << EDM_CFG_offVER )
+
+/******************************************************************************
+ * dr41: EDMSW (EDM Status Word)
+ *****************************************************************************/
+#define EDMSW_offWV 0 /* Write Valid */
+#define EDMSW_offRV 1 /* Read Valid */
+#define EDMSW_offDE 2 /* Debug exception has occurred for this core */
+/* bit 3:31 reserved */
+
+#define EDMSW_mskWV ( 0x1 << EDMSW_offWV )
+#define EDMSW_mskRV ( 0x1 << EDMSW_offRV )
+#define EDMSW_mskDE ( 0x1 << EDMSW_offDE )
+
+/******************************************************************************
+ * dr42: EDM_CTL (EDM Control Register)
+ *****************************************************************************/
+/* bit 0:30 reserved */
+#define EDM_CTL_offV3_EDM_MODE 6 /* EDM compatibility control bit */
+#define EDM_CTL_offDEH_SEL 31 /* Controls where debug exception is directed to */
+
+#define EDM_CTL_mskV3_EDM_MODE ( 0x1 << EDM_CTL_offV3_EDM_MODE )
+#define EDM_CTL_mskDEH_SEL ( 0x1 << EDM_CTL_offDEH_SEL )
+
+/******************************************************************************
+ * dr43: EDM_DTR (EDM Data Transfer Register)
+ *****************************************************************************/
+
+ /* This is used to exchange data between the embedded EDM logic
+ * and the processor core */
+
+/******************************************************************************
+ * dr44: BPMTC (Breakpoint Match Trigger Counter Register)
+ *****************************************************************************/
+#define BPMTC_offBPMTC 0 /* Breakpoint match trigger counter value */
+/* bit 16:31 reserved */
+
+#define BPMTC_mskBPMTC ( 0xFFFF << BPMTC_offBPMTC )
+
+/******************************************************************************
+ * dr45: DIMBR (Debug Instruction Memory Base Register)
+ *****************************************************************************/
+/* bit 0:11 reserved */
+#define DIMBR_offDIMB 12 /* Base address of the Debug Instruction Memory (DIM) */
+#define DIMBR_mskDIMB ( 0xFFFFF << DIMBR_offDIMB )
+
+/******************************************************************************
+ * dr46: TECR0(Trigger Event Control register 0)
+ * dr47: TECR1 (Trigger Event Control register 1)
+ *****************************************************************************/
+#define TECR_offBP 0 /* Controld which BP is used as a trigger source */
+#define TECR_offNMI 8 /* Use NMI as a trigger source */
+#define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */
+#define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */
+#define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */
+#define TECR_offDBG 17 /* Enable debug exception as a trigger source */
+#define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */
+#define TECR_offE 19 /* An exception is used as a trigger source */
+/* bit 20:30 reserved */
+#define TECR_offL 31 /* Link/Cascade TECR0 trigger event to TECR1 trigger event */
+
+#define TECR_mskBP ( 0xFF << TECR_offBP )
+#define TECR_mskNMI ( 0x1 << TECR_offBNMI )
+#define TECR_mskHWINT ( 0x3F << TECR_offBHWINT )
+#define TECR_mskEVIC ( 0x1 << TECR_offBEVIC )
+#define TECR_mskSYS ( 0x1 << TECR_offBSYS )
+#define TECR_mskDBG ( 0x1 << TECR_offBDBG )
+#define TECR_mskMRE ( 0x1 << TECR_offBMRE )
+#define TECR_mskE ( 0x1 << TECR_offE )
+#define TECR_mskL ( 0x1 << TECR_offL )
+
+/******************************************************************************
+ * pfr0-2: PFMC0-2 (Performance Counter Register 0-2)
+ *****************************************************************************/
+
+ /* These registers contains performance event count */
+
+/******************************************************************************
+ * pfr3: PFM_CTL (Performance Counter Control Register)
+ *****************************************************************************/
+#define PFM_CTL_offEN0 0 /* Enable PFMC0 */
+#define PFM_CTL_offEN1 1 /* Enable PFMC1 */
+#define PFM_CTL_offEN2 2 /* Enable PFMC2 */
+#define PFM_CTL_offIE0 3 /* Enable interrupt for PFMC0 */
+#define PFM_CTL_offIE1 4 /* Enable interrupt for PFMC1 */
+#define PFM_CTL_offIE2 5 /* Enable interrupt for PFMC2 */
+#define PFM_CTL_offOVF0 6 /* Overflow bit of PFMC0 */
+#define PFM_CTL_offOVF1 7 /* Overflow bit of PFMC1 */
+#define PFM_CTL_offOVF2 8 /* Overflow bit of PFMC2 */
+#define PFM_CTL_offKS0 9 /* Enable superuser mode event counting for PFMC0 */
+#define PFM_CTL_offKS1 10 /* Enable superuser mode event counting for PFMC1 */
+#define PFM_CTL_offKS2 11 /* Enable superuser mode event counting for PFMC2 */
+#define PFM_CTL_offKU0 12 /* Enable user mode event counting for PFMC0 */
+#define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */
+#define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */
+#define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */
+#define PFM_CTL_offSEL1 21 /* The event selection for PFMC1 */
+#define PFM_CTL_offSEL2 27 /* The event selection for PFMC2 */
+/* bit 28:31 reserved */
+
+#define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 )
+#define PFM_CTL_mskEN1 ( 0x01 << PFM_CTL_offEN1 )
+#define PFM_CTL_mskEN2 ( 0x01 << PFM_CTL_offEN2 )
+#define PFM_CTL_mskIE0 ( 0x01 << PFM_CTL_offIE0 )
+#define PFM_CTL_mskIE1 ( 0x01 << PFM_CTL_offIE1 )
+#define PFM_CTL_mskIE2 ( 0x01 << PFM_CTL_offIE2 )
+#define PFM_CTL_mskOVF0 ( 0x01 << PFM_CTL_offOVF0 )
+#define PFM_CTL_mskOVF1 ( 0x01 << PFM_CTL_offOVF1 )
+#define PFM_CTL_mskOVF2 ( 0x01 << PFM_CTL_offOVF2 )
+#define PFM_CTL_mskKS0 ( 0x01 << PFM_CTL_offKS0 )
+#define PFM_CTL_mskKS1 ( 0x01 << PFM_CTL_offKS1 )
+#define PFM_CTL_mskKS2 ( 0x01 << PFM_CTL_offKS2 )
+#define PFM_CTL_mskKU0 ( 0x01 << PFM_CTL_offKU0 )
+#define PFM_CTL_mskKU1 ( 0x01 << PFM_CTL_offKU1 )
+#define PFM_CTL_mskKU2 ( 0x01 << PFM_CTL_offKU2 )
+#define PFM_CTL_mskSEL0 ( 0x01 << PFM_CTL_offSEL0 )
+#define PFM_CTL_mskSEL1 ( 0x3F << PFM_CTL_offSEL1 )
+#define PFM_CTL_mskSEL2 ( 0x3F << PFM_CTL_offSEL2 )
+
+/******************************************************************************
+ * SDZ_CTL (Structure Downsizing Control Register)
+ *****************************************************************************/
+#define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */
+#define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */
+#define SDZ_CTL_offMTBDZ 6 /* MTLB downsizing control */
+#define SDZ_CTL_offBTBDZ 9 /* Branch Target Table downsizing control */
+/* bit 12:31 reserved */
+#define SDZ_CTL_mskICDZ ( 0x07 << SDZ_CTL_offICDZ )
+#define SDZ_CTL_mskDCDZ ( 0x07 << SDZ_CTL_offDCDZ )
+#define SDZ_CTL_mskMTBDZ ( 0x07 << SDZ_CTL_offMTBDZ )
+#define SDZ_CTL_mskBTBDZ ( 0x07 << SDZ_CTL_offBTBDZ )
+
+/******************************************************************************
+ * N13MISC_CTL (N13 Miscellaneous Control Register)
+ *****************************************************************************/
+#define N13MISC_CTL_offBTB 0 /* Disable Branch Target Buffer */
+#define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */
+#define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */
+#define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */
+/* bit 6, 9:31 reserved */
+
+#define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB )
+#define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP )
+#define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF )
+#define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN )
+
+#define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN)
+
+/******************************************************************************
+ * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
+ *****************************************************************************/
+#define PRUSR_ACC_CTL_offDMA_EN 0 /* Allow user mode access of DMA registers */
+#define PRUSR_ACC_CTL_offPFM_EN 1 /* Allow user mode access of PFM registers */
+
+#define PRUSR_ACC_CTL_mskDMA_EN ( 0x1 << PRUSR_ACC_CTL_offDMA_EN )
+#define PRUSR_ACC_CTL_mskPFM_EN ( 0x1 << PRUSR_ACC_CTL_offPFM_EN )
+
+/******************************************************************************
+ * dmar0: DMA_CFG (DMA Configuration Register)
+ *****************************************************************************/
+#define DMA_CFG_offNCHN 0 /* The number of DMA channels implemented */
+#define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */
+#define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */
+/* bit 4:15 reserved */
+#define DMA_CFG_offVER 16 /* DMA architecture and implementation version */
+
+#define DMA_CFG_mskNCHN ( 0x3 << DMA_CFG_offNCHN )
+#define DMA_CFG_mskUNEA ( 0x1 << DMA_CFG_offUNEA )
+#define DMA_CFG_msk2DET ( 0x1 << DMA_CFG_off2DET )
+#define DMA_CFG_mskVER ( 0xFFFF << DMA_CFG_offVER )
+
+/******************************************************************************
+ * dmar1: DMA_GCSW (DMA Global Control and Status Word Register)
+ *****************************************************************************/
+#define DMA_GCSW_offC0STAT 0 /* DMA channel 0 state */
+#define DMA_GCSW_offC1STAT 3 /* DMA channel 1 state */
+/* bit 6:11 reserved */
+#define DMA_GCSW_offC0INT 12 /* DMA channel 0 generate interrupt */
+#define DMA_GCSW_offC1INT 13 /* DMA channel 1 generate interrupt */
+/* bit 14:30 reserved */
+#define DMA_GCSW_offEN 31 /* Enable DMA engine */
+
+#define DMA_GCSW_mskC0STAT ( 0x7 << DMA_GCSW_offC0STAT )
+#define DMA_GCSW_mskC1STAT ( 0x7 << DMA_GCSW_offC1STAT )
+#define DMA_GCSW_mskC0INT ( 0x1 << DMA_GCSW_offC0INT )
+#define DMA_GCSW_mskC1INT ( 0x1 << DMA_GCSW_offC1INT )
+#define DMA_GCSW_mskEN ( 0x1 << DMA_GCSW_offEN )
+
+/******************************************************************************
+ * dmar2: DMA_CHNSEL (DMA Channel Selection Register)
+ *****************************************************************************/
+#define DMA_CHNSEL_offCHAN 0 /* Selected channel number */
+/* bit 2:31 reserved */
+
+#define DMA_CHNSEL_mskCHAN ( 0x3 << DMA_CHNSEL_offCHAN )
+
+/******************************************************************************
+ * dmar3: DMA_ACT (DMA Action Register)
+ *****************************************************************************/
+#define DMA_ACT_offACMD 0 /* DMA Action Command */
+/* bit 2:31 reserved */
+#define DMA_ACT_mskACMD ( 0x3 << DMA_ACT_offACMD )
+
+/******************************************************************************
+ * dmar4: DMA_SETUP (DMA Setup Register)
+ *****************************************************************************/
+#define DMA_SETUP_offLM 0 /* Local Memory Selection */
+#define DMA_SETUP_offTDIR 1 /* Transfer Direction */
+#define DMA_SETUP_offTES 2 /* Transfer Element Size */
+#define DMA_SETUP_offESTR 4 /* External memory transfer Stride */
+#define DMA_SETUP_offCIE 16 /* Interrupt Enable on Completion */
+#define DMA_SETUP_offSIE 17 /* Interrupt Enable on explicit Stop */
+#define DMA_SETUP_offEIE 18 /* Interrupt Enable on Error */
+#define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */
+#define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */
+#define DMA_SETUP_offCOA 21 /* Transfer Coalescable */
+/* bit 22:31 reserved */
+
+#define DMA_SETUP_mskLM ( 0x1 << DMA_SETUP_offLM )
+#define DMA_SETUP_mskTDIR ( 0x1 << DMA_SETUP_offTDIR )
+#define DMA_SETUP_mskTES ( 0x3 << DMA_SETUP_offTES )
+#define DMA_SETUP_mskESTR ( 0xFFF << DMA_SETUP_offESTR )
+#define DMA_SETUP_mskCIE ( 0x1 << DMA_SETUP_offCIE )
+#define DMA_SETUP_mskSIE ( 0x1 << DMA_SETUP_offSIE )
+#define DMA_SETUP_mskEIE ( 0x1 << DMA_SETUP_offEIE )
+#define DMA_SETUP_mskUE ( 0x1 << DMA_SETUP_offUE )
+#define DMA_SETUP_msk2DE ( 0x1 << DMA_SETUP_off2DE )
+#define DMA_SETUP_mskCOA ( 0x1 << DMA_SETUP_offCOA )
+
+/******************************************************************************
+ * dmar5: DMA_ISADDR (DMA Internal Start Address Register)
+ *****************************************************************************/
+#define DMA_ISADDR_offISADDR 0 /* Internal Start Address */
+/* bit 20:31 reserved */
+#define DMA_ISADDR_mskISADDR ( 0xFFFFF << DMA_ISADDR_offISADDR )
+
+/******************************************************************************
+ * dmar6: DMA_ESADDR (DMA External Start Address Register)
+ *****************************************************************************/
+/* This register holds External Start Address */
+
+/******************************************************************************
+ * dmar7: DMA_TCNT (DMA Transfer Element Count Register)
+ *****************************************************************************/
+#define DMA_TCNT_offTCNT 0 /* DMA transfer element count */
+/* bit 18:31 reserved */
+#define DMA_TCNT_mskTCNT ( 0x3FFFF << DMA_TCNT_offTCNT )
+
+/******************************************************************************
+ * dmar8: DMA_STATUS (DMA Status Register)
+ *****************************************************************************/
+#define DMA_STATUS_offSTAT 0 /* DMA channel state */
+#define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */
+#define DMA_STATUS_offDERR 4 /* DMA Transfer Disruption Error */
+#define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */
+#define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */
+#define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */
+#define DMA_STATUS_offEBUS 8 /* Bus Error on an External DMA transfer */
+#define DMA_STATUS_offESUP 9 /* DMA setup error */
+/* bit 10:31 reserved */
+
+#define DMA_STATUS_mskSTAT ( 0x7 << DMA_STATUS_offSTAT )
+#define DMA_STATUS_mskSTUNA ( 0x1 << DMDMA_STATUS_offSTUNA )
+#define DMA_STATUS_mskDERR ( 0x1 << DMDMA_STATUS_offDERR )
+#define DMA_STATUS_mskEUNA ( 0x1 << DMDMA_STATUS_offEUNA )
+#define DMA_STATUS_mskIUNA ( 0x1 << DMDMA_STATUS_offIUNA )
+#define DMA_STATUS_mskIOOR ( 0x1 << DMDMA_STATUS_offIOOR )
+#define DMA_STATUS_mskEBUS ( 0x1 << DMDMA_STATUS_offEBUS )
+#define DMA_STATUS_mskESUP ( 0x1 << DMDMA_STATUS_offESUP )
+
+/******************************************************************************
+ * dmar9: DMA_2DSET (DMA 2D Setup Register)
+ *****************************************************************************/
+#define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */
+#define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */
+
+#define DMA_2DSET_mskHTSTR ( 0xFFFF << DMA_2DSET_offHTSTR )
+#define DMA_2DSET_mskWECNT ( 0xFFFF << DMA_2DSET_offWECNT )
+
+/******************************************************************************
+ * dmar10: DMA_2DSCTL (DMA 2D Startup Control Register)
+ *****************************************************************************/
+#define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */
+/* bit 16:31 reserved */
+
+#define DMA_2DSCTL_mskSTWECNT ( 0xFFFF << DMA_2DSCTL_offSTWECNT )
+
+/******************************************************************************
+ * fpcsr: FPCSR (Floating-Point Control Status Register)
+ *****************************************************************************/
+#define FPCSR_offRM 0
+#define FPCSR_offIVO 2
+#define FPCSR_offDBZ 3
+#define FPCSR_offOVF 4
+#define FPCSR_offUDF 5
+#define FPCSR_offIEX 6
+#define FPCSR_offIVOE 7
+#define FPCSR_offDBZE 8
+#define FPCSR_offOVFE 9
+#define FPCSR_offUDFE 10
+#define FPCSR_offIEXE 11
+#define FPCSR_offDNZ 12
+#define FPCSR_offIVOT 13
+#define FPCSR_offDBZT 14
+#define FPCSR_offOVFT 15
+#define FPCSR_offUDFT 16
+#define FPCSR_offIEXT 17
+#define FPCSR_offDNIT 18
+#define FPCSR_offRIT 19
+
+#define FPCSR_mskRM ( 0x3 << FPCSR_offRM )
+#define FPCSR_mskIVO ( 0x1 << FPCSR_offIVO )
+#define FPCSR_mskDBZ ( 0x1 << FPCSR_offDBZ )
+#define FPCSR_mskOVF ( 0x1 << FPCSR_offOVF )
+#define FPCSR_mskUDF ( 0x1 << FPCSR_offUDF )
+#define FPCSR_mskIEX ( 0x1 << FPCSR_offIEX )
+#define FPCSR_mskIVOE ( 0x1 << FPCSR_offIVOE )
+#define FPCSR_mskDBZE ( 0x1 << FPCSR_offDBZE )
+#define FPCSR_mskOVFE ( 0x1 << FPCSR_offOVFE )
+#define FPCSR_mskUDFE ( 0x1 << FPCSR_offUDFE )
+#define FPCSR_mskIEXE ( 0x1 << FPCSR_offIEXE )
+#define FPCSR_mskDNZ ( 0x1 << FPCSR_offDNZ )
+#define FPCSR_mskIVOT ( 0x1 << FPCSR_offIVOT )
+#define FPCSR_mskDBZT ( 0x1 << FPCSR_offDBZT )
+#define FPCSR_mskOVFT ( 0x1 << FPCSR_offOVFT )
+#define FPCSR_mskUDFT ( 0x1 << FPCSR_offUDFT )
+#define FPCSR_mskIEXT ( 0x1 << FPCSR_offIEXT )
+#define FPCSR_mskDNIT ( 0x1 << FPCSR_offDNIT )
+#define FPCSR_mskRIT ( 0x1 << FPCSR_offRIT )
+#define FPCSR_mskALL (FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX)
+#define FPCSR_mskALLE (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE)
+#define FPCSR_mskALLT (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT)
+
+/******************************************************************************
+ * fpcfg: FPCFG (Floating-Point Configuration Register)
+ *****************************************************************************/
+#define FPCFG_offSP 0
+#define FPCFG_offDP 1
+#define FPCFG_offFREG 2
+#define FPCFG_offFMA 4
+#define FPCFG_offIMVER 22
+#define FPCFG_offAVER 27
+
+#define FPCFG_mskSP ( 0x1 << FPCFG_offSP )
+#define FPCFG_mskDP ( 0x1 << FPCFG_offDP )
+#define FPCFG_mskFREG ( 0x3 << FPCFG_offFREG )
+#define FPCFG_mskFMA ( 0x1 << FPCFG_offFMA )
+#define FPCFG_mskIMVER ( 0x1F << FPCFG_offIMVER )
+#define FPCFG_mskAVER ( 0x1F << FPCFG_offAVER )
+
+/******************************************************************************
+ * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register)
+ *****************************************************************************/
+#define FUCOP_CTL_offCP0EN 0
+#define FUCOP_CTL_offCP1EN 1
+#define FUCOP_CTL_offCP2EN 2
+#define FUCOP_CTL_offCP3EN 3
+#define FUCOP_CTL_offAUEN 31
+
+#define FUCOP_CTL_mskCP0EN ( 0x1 << FUCOP_CTL_offCP0EN )
+#define FUCOP_CTL_mskCP1EN ( 0x1 << FUCOP_CTL_offCP1EN )
+#define FUCOP_CTL_mskCP2EN ( 0x1 << FUCOP_CTL_offCP2EN )
+#define FUCOP_CTL_mskCP3EN ( 0x1 << FUCOP_CTL_offCP3EN )
+#define FUCOP_CTL_mskAUEN ( 0x1 << FUCOP_CTL_offAUEN )
+
+#endif /* __NDS32_BITFIELD_H__ */
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 000000000000..347db4881c5f
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHE_H__
+#define __NDS32_CACHE_H__
+
+#define L1_CACHE_BYTES 32
+#define L1_CACHE_SHIFT 5
+
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
+#endif /* __NDS32_CACHE_H__ */
diff --git a/arch/nds32/include/asm/cache_info.h b/arch/nds32/include/asm/cache_info.h
new file mode 100644
index 000000000000..38ec458ba543
--- /dev/null
+++ b/arch/nds32/include/asm/cache_info.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+struct cache_info {
+ unsigned char ways;
+ unsigned char line_size;
+ unsigned short sets;
+ unsigned short size;
+#if defined(CONFIG_CPU_CACHE_ALIASING)
+ unsigned short aliasing_num;
+ unsigned int aliasing_mask;
+#endif
+};
diff --git a/arch/nds32/include/asm/cacheflush.h b/arch/nds32/include/asm/cacheflush.h
new file mode 100644
index 000000000000..7b9b20a381cb
--- /dev/null
+++ b/arch/nds32/include/asm/cacheflush.h
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_CACHEFLUSH_H__
+#define __NDS32_CACHEFLUSH_H__
+
+#include <linux/mm.h>
+
+#define PG_dcache_dirty PG_arch_1
+
+#ifdef CONFIG_CPU_CACHE_ALIASING
+void flush_cache_mm(struct mm_struct *mm);
+void flush_cache_dup_mm(struct mm_struct *mm);
+void flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end);
+void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long pfn);
+void flush_cache_kmaps(void);
+void flush_cache_vmap(unsigned long start, unsigned long end);
+void flush_cache_vunmap(unsigned long start, unsigned long end);
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+void flush_dcache_page(struct page *page);
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+ unsigned long vaddr, void *dst, void *src, int len);
+void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+ unsigned long vaddr, void *dst, void *src, int len);
+
+#define ARCH_HAS_FLUSH_ANON_PAGE
+void flush_anon_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr);
+
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+void flush_kernel_dcache_page(struct page *page);
+void flush_icache_range(unsigned long start, unsigned long end);
+void flush_icache_page(struct vm_area_struct *vma, struct page *page);
+#define flush_dcache_mmap_lock(mapping) spin_lock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_unlock(mapping) spin_unlock_irq(&(mapping)->tree_lock)
+
+#else
+#include <asm-generic/cacheflush.h>
+#endif
+
+#endif /* __NDS32_CACHEFLUSH_H__ */
diff --git a/arch/nds32/include/asm/current.h b/arch/nds32/include/asm/current.h
new file mode 100644
index 000000000000..b4dcd22b7bcb
--- /dev/null
+++ b/arch/nds32/include/asm/current.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_CURRENT_H
+#define _ASM_NDS32_CURRENT_H
+
+#ifndef __ASSEMBLY__
+register struct task_struct *current asm("$r25");
+#endif /* __ASSEMBLY__ */
+#define tsk $r25
+
+#endif /* _ASM_NDS32_CURRENT_H */
diff --git a/arch/nds32/include/asm/delay.h b/arch/nds32/include/asm/delay.h
new file mode 100644
index 000000000000..519ba97acb6e
--- /dev/null
+++ b/arch/nds32/include/asm/delay.h
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_DELAY_H__
+#define __NDS32_DELAY_H__
+
+#include <asm/param.h>
+
+/* There is no clocksource cycle counter in the CPU. */
+static inline void __delay(unsigned long loops)
+{
+ __asm__ __volatile__(".align 2\n"
+ "1:\n"
+ "\taddi\t%0, %0, -1\n"
+ "\tbgtz\t%0, 1b\n"
+ :"=r"(loops)
+ :"0"(loops));
+}
+
+static inline void __udelay(unsigned long usecs, unsigned long lpj)
+{
+ usecs *= (unsigned long)(((0x8000000000000000ULL / (500000 / HZ)) +
+ 0x80000000ULL) >> 32);
+ usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32);
+ __delay(usecs);
+}
+
+#define udelay(usecs) __udelay((usecs), loops_per_jiffy)
+
+/* make sure "usecs *= ..." in udelay do not overflow. */
+#if HZ >= 1000
+#define MAX_UDELAY_MS 1
+#elif HZ <= 200
+#define MAX_UDELAY_MS 5
+#else
+#define MAX_UDELAY_MS (1000 / HZ)
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/dma-mapping.h b/arch/nds32/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..2dd47d245c25
--- /dev/null
+++ b/arch/nds32/include/asm/dma-mapping.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef ASMNDS32_DMA_MAPPING_H
+#define ASMNDS32_DMA_MAPPING_H
+
+extern struct dma_map_ops nds32_dma_ops;
+
+static inline struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
+{
+ return &nds32_dma_ops;
+}
+
+#endif
diff --git a/arch/nds32/include/asm/elf.h b/arch/nds32/include/asm/elf.h
new file mode 100644
index 000000000000..56c479058802
--- /dev/null
+++ b/arch/nds32/include/asm/elf.h
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASMNDS32_ELF_H
+#define __ASMNDS32_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_freg_t[3];
+
+extern unsigned int elf_hwcap;
+
+#define EM_NDS32 167
+
+#define R_NDS32_NONE 0
+#define R_NDS32_16_RELA 19
+#define R_NDS32_32_RELA 20
+#define R_NDS32_9_PCREL_RELA 22
+#define R_NDS32_15_PCREL_RELA 23
+#define R_NDS32_17_PCREL_RELA 24
+#define R_NDS32_25_PCREL_RELA 25
+#define R_NDS32_HI20_RELA 26
+#define R_NDS32_LO12S3_RELA 27
+#define R_NDS32_LO12S2_RELA 28
+#define R_NDS32_LO12S1_RELA 29
+#define R_NDS32_LO12S0_RELA 30
+#define R_NDS32_SDA15S3_RELA 31
+#define R_NDS32_SDA15S2_RELA 32
+#define R_NDS32_SDA15S1_RELA 33
+#define R_NDS32_SDA15S0_RELA 34
+#define R_NDS32_GOT20 37
+#define R_NDS32_25_PLTREL 38
+#define R_NDS32_COPY 39
+#define R_NDS32_GLOB_DAT 40
+#define R_NDS32_JMP_SLOT 41
+#define R_NDS32_RELATIVE 42
+#define R_NDS32_GOTOFF 43
+#define R_NDS32_GOTPC20 44
+#define R_NDS32_GOT_HI20 45
+#define R_NDS32_GOT_LO12 46
+#define R_NDS32_GOTPC_HI20 47
+#define R_NDS32_GOTPC_LO12 48
+#define R_NDS32_GOTOFF_HI20 49
+#define R_NDS32_GOTOFF_LO12 50
+#define R_NDS32_INSN16 51
+#define R_NDS32_LABEL 52
+#define R_NDS32_LONGCALL1 53
+#define R_NDS32_LONGCALL2 54
+#define R_NDS32_LONGCALL3 55
+#define R_NDS32_LONGJUMP1 56
+#define R_NDS32_LONGJUMP2 57
+#define R_NDS32_LONGJUMP3 58
+#define R_NDS32_LOADSTORE 59
+#define R_NDS32_9_FIXED_RELA 60
+#define R_NDS32_15_FIXED_RELA 61
+#define R_NDS32_17_FIXED_RELA 62
+#define R_NDS32_25_FIXED_RELA 63
+#define R_NDS32_PLTREL_HI20 64
+#define R_NDS32_PLTREL_LO12 65
+#define R_NDS32_PLT_GOTREL_HI20 66
+#define R_NDS32_PLT_GOTREL_LO12 67
+#define R_NDS32_LO12S0_ORI_RELA 72
+#define R_NDS32_DWARF2_OP1_RELA 77
+#define R_NDS32_DWARF2_OP2_RELA 78
+#define R_NDS32_DWARF2_LEB_RELA 79
+#define R_NDS32_WORD_9_PCREL_RELA 94
+#define R_NDS32_LONGCALL4 107
+#define R_NDS32_RELA_NOP_MIX 192
+#define R_NDS32_RELA_NOP_MAX 255
+
+#define ELF_NGREG (sizeof (struct user_pt_regs) / sizeof(elf_greg_t))
+#define ELF_CORE_COPY_REGS(dest, regs) \
+ *(struct user_pt_regs *)&(dest) = (regs)->user_regs;
+
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+/* Core file format: The core file is written in such a way that gdb
+ can understand it and provide useful information to the user (under
+ linux we use the 'trad-core' bfd). There are quite a number of
+ obstacles to being able to view the contents of the floating point
+ registers, and until these are solved you will not be able to view the
+ contents of them. Actually, you can read in the core file and look at
+ the contents of the user struct to find out what the floating point
+ registers contain.
+ The actual file contents are as follows:
+ UPAGE: 1 page consisting of a user struct that tells gdb what is present
+ in the file. Directly after this is a copy of the task_struct, which
+ is currently not used by gdb, but it may come in useful at some point.
+ All of the registers are stored as part of the upage. The upage should
+ always be only one page.
+ DATA: The data area is stored. We use current->end_text to
+ current->brk to pick up all of the user variables, plus any memory
+ that may have been malloced. No attempt is made to determine if a page
+ is demand-zero or if a page is totally unused, we just cover the entire
+ range. All of the addresses are rounded in such a way that an integral
+ number of pages is written.
+ STACK: We need the stack information in order to get a meaningful
+ backtrace. We need to write the data from (esp) to
+ current->start_stack, so we round each of these off in order to be able
+ to write an integer number of pages.
+ The minimum core file size is 3 pages, or 12288 bytes.
+*/
+
+struct user_fp {
+ unsigned long long fd_regs[32];
+ unsigned long fpcsr;
+};
+
+typedef struct user_fp elf_fpregset_t;
+
+struct elf32_hdr;
+#define elf_check_arch(x) ((x)->e_machine == EM_NDS32)
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS ELFCLASS32
+#ifdef __NDS32_EB__
+#define ELF_DATA ELFDATA2MSB;
+#else
+#define ELF_DATA ELFDATA2LSB;
+#endif
+#define ELF_ARCH EM_NDS32
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE PAGE_SIZE
+
+/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
+ use of this is to invoke "./ld.so someprog" to test out a new version of
+ the loader. We need to make sure that it is out of the way of the program
+ that it will "exec", and that there is sufficient room for the brk. */
+
+#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
+
+/* When the program starts, a1 contains a pointer to a function to be
+ registered with atexit, as per the SVR4 ABI. A value of 0 means we
+ have no such handler. */
+#define ELF_PLAT_INIT(_r, load_addr) (_r)->uregs[0] = 0
+
+/* This yields a mask that user programs can use to figure out what
+ instruction set this cpu supports. */
+
+#define ELF_HWCAP (elf_hwcap)
+
+#ifdef __KERNEL__
+
+#define ELF_PLATFORM (NULL)
+
+/* Old NetWinder binaries were compiled in such a way that the iBCS
+ heuristic always trips on them. Until these binaries become uncommon
+ enough not to care, don't trust the `ibcs' flag here. In any case
+ there is no other ELF system currently supported by iBCS.
+ @@ Could print a warning message to encourage users to upgrade. */
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+
+#endif
+
+#define ARCH_DLINFO \
+do { \
+ NEW_AUX_ENT(AT_SYSINFO_EHDR, \
+ (elf_addr_t)current->mm->context.vdso); \
+} while (0)
+#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
+struct linux_binprm;
+int arch_setup_additional_pages(struct linux_binprm *, int);
+
+#endif
diff --git a/arch/nds32/include/asm/fixmap.h b/arch/nds32/include/asm/fixmap.h
new file mode 100644
index 000000000000..0e60e153a71a
--- /dev/null
+++ b/arch/nds32/include/asm/fixmap.h
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_FIXMAP_H
+#define __ASM_NDS32_FIXMAP_H
+
+#ifdef CONFIG_HIGHMEM
+#include <linux/threads.h>
+#include <asm/kmap_types.h>
+#endif
+
+enum fixed_addresses {
+ FIX_HOLE,
+ FIX_KMAP_RESERVED,
+ FIX_KMAP_BEGIN,
+#ifdef CONFIG_HIGHMEM
+ FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS),
+#endif
+ FIX_EARLYCON_MEM_BASE,
+ __end_of_fixed_addresses
+};
+#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE)))
+#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT)
+#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
+#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE)
+void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot);
+
+#include <asm-generic/fixmap.h>
+#endif /* __ASM_NDS32_FIXMAP_H */
diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h
new file mode 100644
index 000000000000..eab5e84bd991
--- /dev/null
+++ b/arch/nds32/include/asm/futex.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_FUTEX_H__
+#define __NDS32_FUTEX_H__
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+#define __futex_atomic_ex_table(err_reg) \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 4f\n" \
+ " .long 2b, 4f\n" \
+ " .popsection\n" \
+ " .pushsection .fixup,\"ax\"\n" \
+ "4: move %0, " err_reg "\n" \
+ " j 3b\n" \
+ " .popsection"
+
+#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
+ smp_mb(); \
+ asm volatile( \
+ " movi $ta, #0\n" \
+ "1: llw %1, [%2+$ta]\n" \
+ " " insn "\n" \
+ "2: scw %0, [%2+$ta]\n" \
+ " beqz %0, 1b\n" \
+ " movi %0, #0\n" \
+ "3:\n" \
+ __futex_atomic_ex_table("%4") \
+ : "=&r" (ret), "=&r" (oldval) \
+ : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \
+ : "cc", "memory")
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr,
+ u32 oldval, u32 newval)
+{
+ int ret = 0;
+ u32 val, tmp, flags;
+
+ if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+ return -EFAULT;
+
+ smp_mb();
+ asm volatile (" movi $ta, #0\n"
+ "1: llw %1, [%6 + $ta]\n"
+ " sub %3, %1, %4\n"
+ " cmovz %2, %5, %3\n"
+ " cmovn %2, %1, %3\n"
+ "2: scw %2, [%6 + $ta]\n"
+ " beqz %2, 1b\n"
+ "3:\n " __futex_atomic_ex_table("%7")
+ :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags)
+ :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT)
+ :"$ta", "memory");
+ smp_mb();
+
+ *uval = val;
+ return ret;
+}
+
+static inline int
+arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
+{
+ int oldval = 0, ret;
+
+
+ pagefault_disable();
+ switch (op) {
+ case FUTEX_OP_SET:
+ __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr,
+ oparg);
+ break;
+ case FUTEX_OP_ADD:
+ __futex_atomic_op("add %0, %1, %3", ret, oldval, tmp, uaddr,
+ oparg);
+ break;
+ case FUTEX_OP_OR:
+ __futex_atomic_op("or %0, %1, %3", ret, oldval, tmp, uaddr,
+ oparg);
+ break;
+ case FUTEX_OP_ANDN:
+ __futex_atomic_op("and %0, %1, %3", ret, oldval, tmp, uaddr,
+ ~oparg);
+ break;
+ case FUTEX_OP_XOR:
+ __futex_atomic_op("xor %0, %1, %3", ret, oldval, tmp, uaddr,
+ oparg);
+ break;
+ default:
+ ret = -ENOSYS;
+ }
+
+ pagefault_enable();
+
+ if (!ret)
+ *oval = oldval;
+
+ return ret;
+}
+#endif /* __NDS32_FUTEX_H__ */
diff --git a/arch/metag/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h
index 8b0dfd684e15..425d546cb059 100644
--- a/arch/metag/include/asm/highmem.h
+++ b/arch/nds32/include/asm/highmem.h
@@ -1,10 +1,13 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
#ifndef _ASM_HIGHMEM_H
#define _ASM_HIGHMEM_H
-#include <asm/cacheflush.h>
+#include <asm/proc-fns.h>
#include <asm/kmap_types.h>
#include <asm/fixmap.h>
+#include <asm/pgtable.h>
/*
* Right now we initialize only a single pte table. It can be extended
@@ -24,17 +27,16 @@
* VMALLOC_START
* VMALLOC_END
*/
-#define PKMAP_BASE (FIXADDR_START - PMD_SIZE)
+#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK))
#define LAST_PKMAP PTRS_PER_PTE
#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
-#define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
#define kmap_prot PAGE_KERNEL
static inline void flush_cache_kmaps(void)
{
- flush_cache_all();
+ cpu_dcache_wbinval_all();
}
/* declarations for highmem.c */
@@ -57,6 +59,7 @@ extern void kunmap(struct page *page);
extern void *kmap_atomic(struct page *page);
extern void __kunmap_atomic(void *kvaddr);
extern void *kmap_atomic_pfn(unsigned long pfn);
+extern struct page *kmap_atomic_to_page(void *ptr);
#endif
#endif
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 000000000000..966e71b3c960
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_IO_H
+#define __ASM_NDS32_IO_H
+
+extern void iounmap(volatile void __iomem *addr);
+#define __raw_writeb __raw_writeb
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+ asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writew __raw_writew
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+ asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_writel __raw_writel
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+ asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr));
+}
+
+#define __raw_readb __raw_readb
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+ u8 val;
+
+ asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#define __raw_readw __raw_readw
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+ u16 val;
+
+ asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#define __raw_readl __raw_readl
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+ u32 val;
+
+ asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr));
+ return val;
+}
+
+#define __iormb() rmb()
+#define __iowmb() wmb()
+
+#define mmiowb() __asm__ __volatile__ ("msync all" : : : "memory");
+
+/*
+ * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
+ * are not guaranteed to provide ordering against spinlocks or memory
+ * accesses.
+ */
+
+#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
+#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
+#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
+#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
+#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
+#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
+
+/*
+ * {read,write}{b,w,l,q}() access little endian memory and return result in
+ * native endianness.
+ */
+#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
+#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
+#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
+#include <asm-generic/io.h>
+#endif /* __ASM_NDS32_IO_H */
diff --git a/arch/nds32/include/asm/irqflags.h b/arch/nds32/include/asm/irqflags.h
new file mode 100644
index 000000000000..2bfd00f8bc48
--- /dev/null
+++ b/arch/nds32/include/asm/irqflags.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <asm/nds32.h>
+#include <nds32_intrinsic.h>
+
+#define arch_local_irq_disable() \
+ GIE_DISABLE();
+
+#define arch_local_irq_enable() \
+ GIE_ENABLE();
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags;
+ flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+ GIE_DISABLE();
+ return flags;
+}
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ unsigned long flags;
+ flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE;
+ return flags;
+}
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ if(flags)
+ GIE_ENABLE();
+}
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+ return !flags;
+}
diff --git a/arch/nds32/include/asm/l2_cache.h b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index 000000000000..37dd5ef61de8
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#define L2_IF_CONF_OFF 0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF 0xC
+#define L2CC_CTRL_OFF 0x10
+#define L2_INT_EN_OFF 0x20
+#define L2_STA_OFF 0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF 0x30
+#define IMPL3ERR_ADDR_OFF 0x34
+#define L2_CNT0_CTRL_OFF 0x40
+#define L2_EVNT_CNT0_OFF 0x44
+#define L2_CNT1_CTRL_OFF 0x48
+#define L2_EVNT_CNT1_OFF 0x4c
+#define L2_CCTL_CMD_OFF 0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF 0x68
+#define L2_LINE_DPT_OFF 0x70
+
+#define CCTL_CMD_L2_IX_INVAL 0x0
+#define CCTL_CMD_L2_PA_INVAL 0x1
+#define CCTL_CMD_L2_IX_WB 0x2
+#define CCTL_CMD_L2_PA_WB 0x3
+#define CCTL_CMD_L2_PA_WBINVAL 0x5
+#define CCTL_CMD_L2_SYNC 0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD 0x10
+#define CCTL_ALL_CMD 0x10
+
+/******************************************************************************
+ * L2_CA_CONF (Cache architecture configuration)
+ *****************************************************************************/
+#define L2_CA_CONF_offL2SET 0
+#define L2_CA_CONF_offL2WAY 4
+#define L2_CA_CONF_offL2CLSZ 8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER 16
+
+#define L2_CA_CONF_mskL2SET (0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY (0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ (0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER (0xFFFFUL << L2_CA_CONF_offL2VER)
+
+/******************************************************************************
+ * L2CC_SETUP (L2CC Setup register)
+ *****************************************************************************/
+#define L2CC_SETUP_offPART 0
+#define L2CC_SETUP_mskPART (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC 4
+#define L2CC_SETUP_mskDDLATC (0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC 8
+#define L2CC_SETUP_mskTDLATC (0x3UL << L2CC_SETUP_offTDLATC)
+
+/******************************************************************************
+ * L2CC_PROT (L2CC Protect register)
+ *****************************************************************************/
+#define L2CC_PROT_offMRWEN 31
+#define L2CC_PROT_mskMRWEN (0x1UL << L2CC_PROT_offMRWEN)
+
+/******************************************************************************
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ *****************************************************************************/
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/******************************************************************************
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ *****************************************************************************/
+#define L2_CCTL_STATUS_offCMD_COMP 31
+#define L2_CCTL_STATUS_mskCMD_COMP (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+
+extern void __iomem *atl2c_base;
+#include <linux/smp.h>
+#include <asm/io.h>
+#include <asm/bitfield.h>
+
+#define L2C_R_REG(offset) readl(atl2c_base + offset)
+#define L2C_W_REG(offset, value) writel(value, atl2c_base + offset)
+
+#define L2_CMD_RDY() \
+ do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & L2_CCTL_STATUS_mskCMD_COMP) == 0)
+
+static inline unsigned long L2_CACHE_SET(void)
+{
+ return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+}
+
+static inline unsigned long L2_CACHE_WAY(void)
+{
+ return 1 +
+ ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
+ L2_CA_CONF_offL2WAY);
+}
+
+static inline unsigned long L2_CACHE_LINE_SIZE(void)
+{
+
+ return 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >>
+ L2_CA_CONF_offL2CLSZ);
+}
+
+static inline unsigned long GET_L2CC_CTRL_CPU(unsigned long cpu)
+{
+ if (cpu == smp_processor_id())
+ return L2C_R_REG(L2CC_CTRL_OFF);
+ return L2C_R_REG(L2CC_CTRL_OFF + (cpu << 8));
+}
+
+static inline void SET_L2CC_CTRL_CPU(unsigned long cpu, unsigned long val)
+{
+ if (cpu == smp_processor_id())
+ L2C_W_REG(L2CC_CTRL_OFF, val);
+ else
+ L2C_W_REG(L2CC_CTRL_OFF + (cpu << 8), val);
+}
+
+static inline unsigned long GET_L2CC_STATUS_CPU(unsigned long cpu)
+{
+ if (cpu == smp_processor_id())
+ return L2C_R_REG(L2_CCTL_STATUS_OFF);
+ return L2C_R_REG(L2_CCTL_STATUS_OFF + (cpu << 8));
+}
+#endif
diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h
new file mode 100644
index 000000000000..e708c8bdb926
--- /dev/null
+++ b/arch/nds32/include/asm/linkage.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+/* This file is required by include/linux/linkage.h */
+#define __ALIGN .align 2
+#define __ALIGN_STR ".align 2"
+
+#endif
diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h
new file mode 100644
index 000000000000..60efc726b56e
--- /dev/null
+++ b/arch/nds32/include/asm/memory.h
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MEMORY_H
+#define __ASM_NDS32_MEMORY_H
+
+#include <linux/compiler.h>
+#include <linux/sizes.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/page.h>
+#endif
+
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET (0x0)
+#endif
+
+#ifndef __virt_to_bus
+#define __virt_to_bus __virt_to_phys
+#endif
+
+#ifndef __bus_to_virt
+#define __bus_to_virt __phys_to_virt
+#endif
+
+/*
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
+ */
+#define TASK_SIZE ((CONFIG_PAGE_OFFSET) - (SZ_32M))
+#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_32M)
+#define PAGE_OFFSET (CONFIG_PAGE_OFFSET)
+
+/*
+ * Physical vs virtual RAM address space conversion. These are
+ * private definitions which should NOT be used outside memory.h
+ * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
+ */
+#ifndef __virt_to_phys
+#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
+#endif
+
+/*
+ * The module space lives between the addresses given by TASK_SIZE
+ * and PAGE_OFFSET - it must be within 32MB of the kernel text.
+ */
+#define MODULES_END (PAGE_OFFSET)
+#define MODULES_VADDR (MODULES_END - SZ_32M)
+
+#if TASK_SIZE > MODULES_VADDR
+#error Top of user space clashes with start of module space
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
+ *
+ * This is the PFN of the first RAM page in the kernel
+ * direct-mapped view. We assume this is the first page
+ * of RAM in the mem_map as well.
+ */
+#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
+
+/*
+ * Drivers should NOT use these either.
+ */
+#define __pa(x) __virt_to_phys((unsigned long)(x))
+#define __va(x) ((void *)__phys_to_virt((unsigned long)(x)))
+
+/*
+ * Conversion between a struct page and a physical address.
+ *
+ * Note: when converting an unknown physical address to a
+ * struct page, the resulting pointer must be validated
+ * using VALID_PAGE(). It must return an invalid struct page
+ * for any physical address not corresponding to a system
+ * RAM address.
+ *
+ * pfn_valid(pfn) indicates whether a PFN number is valid
+ *
+ * virt_to_page(k) convert a _valid_ virtual address to struct page *
+ * virt_addr_valid(k) indicates whether a virtual address is valid
+ */
+#ifndef CONFIG_DISCONTIGMEM
+
+#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
+#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+
+#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT))
+#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
+
+#else /* CONFIG_DISCONTIGMEM */
+#error CONFIG_DISCONTIGMEM is not supported yet.
+#endif /* !CONFIG_DISCONTIGMEM */
+
+#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
+
+#endif
+
+#include <asm-generic/memory_model.h>
+
+#endif
diff --git a/arch/nds32/include/asm/mmu.h b/arch/nds32/include/asm/mmu.h
new file mode 100644
index 000000000000..88b9ee8c1064
--- /dev/null
+++ b/arch/nds32/include/asm/mmu.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_MMU_H
+#define __NDS32_MMU_H
+
+typedef struct {
+ unsigned int id;
+ void *vdso;
+} mm_context_t;
+
+#endif
diff --git a/arch/nds32/include/asm/mmu_context.h b/arch/nds32/include/asm/mmu_context.h
new file mode 100644
index 000000000000..fd7d13cefccc
--- /dev/null
+++ b/arch/nds32/include/asm/mmu_context.h
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_MMU_CONTEXT_H
+#define __ASM_NDS32_MMU_CONTEXT_H
+
+#include <linux/spinlock.h>
+#include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
+#include <asm-generic/mm_hooks.h>
+
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+ mm->context.id = 0;
+ return 0;
+}
+
+#define destroy_context(mm) do { } while(0)
+
+#define CID_BITS 9
+extern spinlock_t cid_lock;
+extern unsigned int cpu_last_cid;
+
+static inline void __new_context(struct mm_struct *mm)
+{
+ unsigned int cid;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cid_lock, flags);
+ cid = cpu_last_cid;
+ cpu_last_cid += 1 << TLB_MISC_offCID;
+ if (cpu_last_cid == 0)
+ cpu_last_cid = 1 << TLB_MISC_offCID << CID_BITS;
+
+ if ((cid & TLB_MISC_mskCID) == 0)
+ flush_tlb_all();
+ spin_unlock_irqrestore(&cid_lock, flags);
+
+ mm->context.id = cid;
+}
+
+static inline void check_context(struct mm_struct *mm)
+{
+ if (unlikely
+ ((mm->context.id ^ cpu_last_cid) >> TLB_MISC_offCID >> CID_BITS))
+ __new_context(mm);
+}
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+ struct task_struct *tsk)
+{
+ unsigned int cpu = smp_processor_id();
+
+ if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
+ check_context(next);
+ cpu_switch_mm(next);
+ }
+}
+
+#define deactivate_mm(tsk,mm) do { } while (0)
+#define activate_mm(prev,next) switch_mm(prev, next, NULL)
+
+#endif
diff --git a/arch/nds32/include/asm/module.h b/arch/nds32/include/asm/module.h
new file mode 100644
index 000000000000..16cf9c7237ad
--- /dev/null
+++ b/arch/nds32/include/asm/module.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_MODULE_H
+#define _ASM_NDS32_MODULE_H
+
+#include <asm-generic/module.h>
+
+#define MODULE_ARCH_VERMAGIC "NDS32v3"
+
+#endif /* _ASM_NDS32_MODULE_H */
diff --git a/arch/nds32/include/asm/nds32.h b/arch/nds32/include/asm/nds32.h
new file mode 100644
index 000000000000..19b19394a936
--- /dev/null
+++ b/arch/nds32/include/asm/nds32.h
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_NDS32_H_
+#define _ASM_NDS32_NDS32_H_
+
+#include <asm/bitfield.h>
+#include <asm/cachectl.h>
+
+#ifndef __ASSEMBLY__
+#include <linux/init.h>
+#include <asm/barrier.h>
+#include <nds32_intrinsic.h>
+
+#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
+#define FP_OFFSET (-3)
+#else
+#define FP_OFFSET (-2)
+#endif
+
+extern void __init early_trap_init(void);
+static inline void GIE_ENABLE(void)
+{
+ mb();
+ __nds32__gie_en();
+}
+
+static inline void GIE_DISABLE(void)
+{
+ mb();
+ __nds32__gie_dis();
+}
+
+static inline unsigned long CACHE_SET(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>
+ ICM_CFG_offISET);
+ else
+ return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>
+ DCM_CFG_offDSET);
+}
+
+static inline unsigned long CACHE_WAY(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 1 +
+ ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
+ else
+ return 1 +
+ ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
+}
+
+static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)
+{
+
+ if (cache == ICACHE)
+ return 8 <<
+ (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
+ else
+ return 8 <<
+ (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned
+ * We defined at the start of the physical memory */
+
+/* dispatched sub-entry exception handler numbering */
+#define RD_PROT 0 /* read protrection */
+#define WRT_PROT 1 /* write protection */
+#define NOEXEC 2 /* non executable */
+#define PAGE_MODIFY 3 /* page modified */
+#define ACC_BIT 4 /* access bit */
+#define RESVED_PTE 5 /* reserved PTE attribute */
+/* reserved 6 ~ 16 */
+
+#endif /* _ASM_NDS32_NDS32_H_ */
diff --git a/arch/nds32/include/asm/page.h b/arch/nds32/include/asm/page.h
new file mode 100644
index 000000000000..e27365c097b6
--- /dev/null
+++ b/arch/nds32/include/asm/page.h
@@ -0,0 +1,67 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ */
+
+#ifndef _ASMNDS32_PAGE_H
+#define _ASMNDS32_PAGE_H
+
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+#define PAGE_SHIFT 12
+#endif
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+#define PAGE_SHIFT 13
+#endif
+#include <linux/const.h>
+#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
+#define PAGE_MASK (~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+struct page;
+struct vm_area_struct;
+#ifdef CONFIG_CPU_CACHE_ALIASING
+extern void copy_user_highpage(struct page *to, struct page *from,
+ unsigned long vaddr, struct vm_area_struct *vma);
+extern void clear_user_highpage(struct page *page, unsigned long vaddr);
+
+#define __HAVE_ARCH_COPY_USER_HIGHPAGE
+#define clear_user_highpage clear_user_highpage
+#else
+#define clear_user_page(page, vaddr, pg) clear_page(page)
+#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
+#endif
+
+void clear_page(void *page);
+void copy_page(void *to, void *from);
+
+typedef unsigned long pte_t;
+typedef unsigned long pmd_t;
+typedef unsigned long pgd_t;
+typedef unsigned long pgprot_t;
+
+#define pte_val(x) (x)
+#define pmd_val(x) (x)
+#define pgd_val(x) (x)
+#define pgprot_val(x) (x)
+
+#define __pte(x) (x)
+#define __pmd(x) (x)
+#define __pgd(x) (x)
+#define __pgprot(x) (x)
+
+typedef struct page *pgtable_t;
+
+#include <asm/memory.h>
+#include <asm-generic/getorder.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/pgalloc.h b/arch/nds32/include/asm/pgalloc.h
new file mode 100644
index 000000000000..27448869131a
--- /dev/null
+++ b/arch/nds32/include/asm/pgalloc.h
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_PGALLOC_H
+#define _ASMNDS32_PGALLOC_H
+
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
+
+/*
+ * Since we have only two-level page tables, these are trivial
+ */
+#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(mm, pmd) do { } while (0)
+#define pgd_populate(mm, pmd, pte) BUG()
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(struct mm_struct *mm, pgd_t * pgd);
+
+#define check_pgt_cache() do { } while (0)
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long addr)
+{
+ pte_t *pte;
+
+ pte =
+ (pte_t *) __get_free_page(GFP_KERNEL | __GFP_RETRY_MAYFAIL |
+ __GFP_ZERO);
+
+ return pte;
+}
+
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+ pgtable_t pte;
+
+ pte = alloc_pages(GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_ZERO, 0);
+ if (pte)
+ cpu_dcache_wb_page((unsigned long)page_address(pte));
+
+ return pte;
+}
+
+/*
+ * Free one PTE table.
+ */
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t * pte)
+{
+ if (pte) {
+ free_page((unsigned long)pte);
+ }
+}
+
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+{
+ __free_page(pte);
+}
+
+/*
+ * Populate the pmdp entry with a pointer to the pte. This pmd is part
+ * of the mm address space.
+ *
+ * Ensure that we always set both PMD entries.
+ */
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmdp, pte_t * ptep)
+{
+ unsigned long pte_ptr = (unsigned long)ptep;
+ unsigned long pmdval;
+
+ BUG_ON(mm != &init_mm);
+
+ /*
+ * The pmd must be loaded with the physical
+ * address of the PTE table
+ */
+ pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE;
+ set_pmd(pmdp, __pmd(pmdval));
+}
+
+static inline void
+pmd_populate(struct mm_struct *mm, pmd_t * pmdp, pgtable_t ptep)
+{
+ unsigned long pmdval;
+
+ BUG_ON(mm == &init_mm);
+
+ pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE;
+ set_pmd(pmdp, __pmd(pmdval));
+}
+
+#endif
diff --git a/arch/nds32/include/asm/pgtable.h b/arch/nds32/include/asm/pgtable.h
new file mode 100644
index 000000000000..6783937edbeb
--- /dev/null
+++ b/arch/nds32/include/asm/pgtable.h
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_PGTABLE_H
+#define _ASMNDS32_PGTABLE_H
+
+#define __PAGETABLE_PMD_FOLDED
+#include <asm-generic/4level-fixup.h>
+#include <asm-generic/sizes.h>
+
+#include <asm/memory.h>
+#include <asm/nds32.h>
+#ifndef __ASSEMBLY__
+#include <asm/fixmap.h>
+#include <asm/io.h>
+#include <nds32_intrinsic.h>
+#endif
+
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+#define PGDIR_SHIFT 22
+#define PTRS_PER_PGD 1024
+#define PMD_SHIFT 22
+#define PTRS_PER_PMD 1
+#define PTRS_PER_PTE 1024
+#endif
+
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+#define PGDIR_SHIFT 24
+#define PTRS_PER_PGD 256
+#define PMD_SHIFT 24
+#define PTRS_PER_PMD 1
+#define PTRS_PER_PTE 2048
+#endif
+
+#ifndef __ASSEMBLY__
+extern void __pte_error(const char *file, int line, unsigned long val);
+extern void __pmd_error(const char *file, int line, unsigned long val);
+extern void __pgd_error(const char *file, int line, unsigned long val);
+
+#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
+#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
+#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
+#endif /* !__ASSEMBLY__ */
+
+#define PMD_SIZE (1UL << PMD_SHIFT)
+#define PMD_MASK (~(PMD_SIZE-1))
+#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE-1))
+
+/*
+ * This is the lowest virtual address we can permit any user space
+ * mapping to be mapped at. This is particularly important for
+ * non-high vector CPUs.
+ */
+#define FIRST_USER_ADDRESS 0x8000
+
+#ifdef CONFIG_HIGHMEM
+#define CONSISTENT_BASE ((PKMAP_BASE) - (SZ_2M))
+#define CONSISTENT_END (PKMAP_BASE)
+#else
+#define CONSISTENT_BASE (FIXADDR_START - SZ_2M)
+#define CONSISTENT_END (FIXADDR_START)
+#endif
+#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
+
+#ifdef CONFIG_HIGHMEM
+#ifndef __ASSEMBLY__
+#include <asm/highmem.h>
+#endif
+#endif
+
+#define VMALLOC_RESERVE SZ_128M
+#define VMALLOC_END (CONSISTENT_BASE - PAGE_SIZE)
+#define VMALLOC_START ((VMALLOC_END) - VMALLOC_RESERVE)
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define MAXMEM __pa(VMALLOC_START)
+#define MAXMEM_PFN PFN_DOWN(MAXMEM)
+
+#define FIRST_USER_PGD_NR 0
+#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) + FIRST_USER_PGD_NR)
+
+/* L2 PTE */
+#define _PAGE_V (1UL << 0)
+
+#define _PAGE_M_XKRW (0UL << 1)
+#define _PAGE_M_UR_KR (1UL << 1)
+#define _PAGE_M_UR_KRW (2UL << 1)
+#define _PAGE_M_URW_KRW (3UL << 1)
+#define _PAGE_M_KR (5UL << 1)
+#define _PAGE_M_KRW (7UL << 1)
+
+#define _PAGE_D (1UL << 4)
+#define _PAGE_E (1UL << 5)
+#define _PAGE_A (1UL << 6)
+#define _PAGE_G (1UL << 7)
+
+#define _PAGE_C_DEV (0UL << 8)
+#define _PAGE_C_DEV_WB (1UL << 8)
+#define _PAGE_C_MEM (2UL << 8)
+#define _PAGE_C_MEM_SHRD_WB (4UL << 8)
+#define _PAGE_C_MEM_SHRD_WT (5UL << 8)
+#define _PAGE_C_MEM_WB (6UL << 8)
+#define _PAGE_C_MEM_WT (7UL << 8)
+
+#define _PAGE_L (1UL << 11)
+
+#define _HAVE_PAGE_L (_PAGE_L)
+#define _PAGE_FILE (1UL << 1)
+#define _PAGE_YOUNG 0
+#define _PAGE_M_MASK _PAGE_M_KRW
+#define _PAGE_C_MASK _PAGE_C_MEM_WT
+
+#ifdef CONFIG_SMP
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WT
+#else
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WB
+#endif
+#else
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WT
+#else
+#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WB
+#endif
+#endif
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define _PAGE_CACHE _PAGE_C_MEM_WT
+#else
+#define _PAGE_CACHE _PAGE_C_MEM_WB
+#endif
+
+/*
+ * + Level 1 descriptor (PMD)
+ */
+#define PMD_TYPE_TABLE 0
+
+#ifndef __ASSEMBLY__
+
+#define _PAGE_USER_TABLE PMD_TYPE_TABLE
+#define _PAGE_KERNEL_TABLE PMD_TYPE_TABLE
+
+#define PAGE_EXEC __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_E)
+#define PAGE_NONE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_A)
+#define PAGE_READ __pgprot(_PAGE_V | _PAGE_M_UR_KR)
+#define PAGE_RDWR __pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D)
+#define PAGE_COPY __pgprot(_PAGE_V | _PAGE_M_UR_KR)
+
+#define PAGE_UXKRWX_V1 __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_UXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_URXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_UR_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_CACHE_L1 __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE)
+#define PAGE_MEMORY __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_KERNEL __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD)
+#define PAGE_DEVICE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV)
+#endif /* __ASSEMBLY__ */
+
+/* xwr */
+#define __P000 (PAGE_NONE | _PAGE_CACHE_SHRD)
+#define __P001 (PAGE_READ | _PAGE_CACHE_SHRD)
+#define __P010 (PAGE_COPY | _PAGE_CACHE_SHRD)
+#define __P011 (PAGE_COPY | _PAGE_CACHE_SHRD)
+#define __P100 (PAGE_EXEC | _PAGE_CACHE_SHRD)
+#define __P101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __P110 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __P111 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD)
+
+#define __S000 (PAGE_NONE | _PAGE_CACHE_SHRD)
+#define __S001 (PAGE_READ | _PAGE_CACHE_SHRD)
+#define __S010 (PAGE_RDWR | _PAGE_CACHE_SHRD)
+#define __S011 (PAGE_RDWR | _PAGE_CACHE_SHRD)
+#define __S100 (PAGE_EXEC | _PAGE_CACHE_SHRD)
+#define __S101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __S110 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
+#define __S111 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD)
+
+#ifndef __ASSEMBLY__
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern struct page *empty_zero_page;
+extern void paging_init(void);
+#define ZERO_PAGE(vaddr) (empty_zero_page)
+
+#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
+#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+
+#define pte_none(pte) !(pte_val(pte))
+#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0))
+#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
+
+#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, address) ((pte_t *)pmd_page_kernel(*(dir)) + pte_index(address))
+#define pte_offset_map(dir, address) ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
+#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
+#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+
+#define pte_unmap(pte) do { } while (0)
+#define pte_unmap_nested(pte) do { } while (0)
+
+#define pmd_off_k(address) pmd_offset(pgd_offset_k(address), address)
+
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+/*
+ * Set a level 1 translation table entry, and clean it out of
+ * any caches such that the MMUs can load it correctly.
+ */
+static inline void set_pmd(pmd_t * pmdp, pmd_t pmd)
+{
+
+ *pmdp = pmd;
+#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (pmdp):"memory");
+ __nds32__msync_all();
+ __nds32__dsb();
+#endif
+}
+
+/*
+ * Set a PTE and flush it out
+ */
+static inline void set_pte(pte_t * ptep, pte_t pte)
+{
+
+ *ptep = pte;
+#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (ptep):"memory");
+ __nds32__msync_all();
+ __nds32__dsb();
+#endif
+}
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+
+/*
+ * pte_write: this page is writeable for user mode
+ * pte_read: this page is readable for user mode
+ * pte_kernel_write: this page is writeable for kernel mode
+ *
+ * We don't have pte_kernel_read because kernel always can read.
+ *
+ * */
+
+#define pte_present(pte) (pte_val(pte) & _PAGE_V)
+#define pte_write(pte) ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW)
+#define pte_read(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KR) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW))
+#define pte_kernel_write(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \
+ ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_KRW) || \
+ (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_XKRW) && pte_exec(pte)))
+#define pte_exec(pte) (pte_val(pte) & _PAGE_E)
+#define pte_dirty(pte) (pte_val(pte) & _PAGE_D)
+#define pte_young(pte) (pte_val(pte) & _PAGE_YOUNG)
+
+/*
+ * The following only works if pte_present() is not true.
+ */
+#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
+#define pte_to_pgoff(x) (pte_val(x) >> 2)
+#define pgoff_to_pte(x) __pte(((x) << 2) | _PAGE_FILE)
+
+#define PTE_FILE_MAX_BITS 29
+
+#define PTE_BIT_FUNC(fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
+ pte_val(pte) = pte_val(pte) | _PAGE_M_UR_KR;
+ return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+ pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK;
+ pte_val(pte) = pte_val(pte) | _PAGE_M_URW_KRW;
+ return pte;
+}
+
+PTE_BIT_FUNC(exprotect, &=~_PAGE_E);
+PTE_BIT_FUNC(mkexec, |=_PAGE_E);
+PTE_BIT_FUNC(mkclean, &=~_PAGE_D);
+PTE_BIT_FUNC(mkdirty, |=_PAGE_D);
+PTE_BIT_FUNC(mkold, &=~_PAGE_YOUNG);
+PTE_BIT_FUNC(mkyoung, |=_PAGE_YOUNG);
+static inline int pte_special(pte_t pte)
+{
+ return 0;
+}
+
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+ return pte;
+}
+
+/*
+ * Mark the prot value as uncacheable and unbufferable.
+ */
+#define pgprot_noncached(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV)
+#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV_WB)
+
+#define pmd_none(pmd) (pmd_val(pmd)&0x1)
+#define pmd_present(pmd) (!pmd_none(pmd))
+#define pmd_bad(pmd) pmd_none(pmd)
+
+#define copy_pmd(pmdpd,pmdps) set_pmd((pmdpd), *(pmdps))
+#define pmd_clear(pmdp) set_pmd((pmdp), __pmd(1))
+
+static inline pmd_t __mk_pmd(pte_t * ptep, unsigned long prot)
+{
+ unsigned long ptr = (unsigned long)ptep;
+ pmd_t pmd;
+
+ /*
+ * The pmd must be loaded with the physical
+ * address of the PTE table
+ */
+
+ pmd_val(pmd) = __virt_to_phys(ptr) | prot;
+ return pmd;
+}
+
+#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
+
+/*
+ * Permanent address of a page. We never have highmem, so this is trivial.
+ */
+#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+#define pgd_none(pgd) (0)
+#define pgd_bad(pgd) (0)
+#define pgd_present(pgd) (1)
+#define pgd_clear(pgdp) do { } while (0)
+
+#define page_pte_prot(page,prot) mk_pte(page, prot)
+#define page_pte(page) mk_pte(page, __pgprot(0))
+/*
+ * L1PTE = $mr1 + ((virt >> PMD_SHIFT) << 2);
+ * L2PTE = (((virt >> PAGE_SHIFT) & (PTRS_PER_PTE -1 )) << 2);
+ * PPN = (phys & 0xfffff000);
+ *
+*/
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
+
+/* Find an entry in the second-level page table.. */
+#define pmd_offset(dir, addr) ((pmd_t *)(dir))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ const unsigned long mask = 0xfff;
+ pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
+ return pte;
+}
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+/* Encode and decode a swap entry.
+ *
+ * We support up to 32GB of swap on 4k machines
+ */
+#define __swp_type(x) (((x).val >> 2) & 0x7f)
+#define __swp_offset(x) ((x).val >> 9)
+#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr) (1)
+
+#include <asm-generic/pgtable.h>
+
+/*
+ * We provide our own arch_get_unmapped_area to cope with VIPT caches.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+/*
+ * remap a physical address `phys' of size `size' with page protection `prot'
+ * into virtual address `from'
+ */
+
+#define pgtable_cache_init() do { } while (0)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASMNDS32_PGTABLE_H */
diff --git a/arch/nds32/include/asm/proc-fns.h b/arch/nds32/include/asm/proc-fns.h
new file mode 100644
index 000000000000..bedc4f59e064
--- /dev/null
+++ b/arch/nds32/include/asm/proc-fns.h
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_PROCFNS_H__
+#define __NDS32_PROCFNS_H__
+
+#ifdef __KERNEL__
+#include <asm/page.h>
+
+struct mm_struct;
+struct vm_area_struct;
+extern void cpu_proc_init(void);
+extern void cpu_proc_fin(void);
+extern void cpu_do_idle(void);
+extern void cpu_reset(unsigned long reset);
+extern void cpu_switch_mm(struct mm_struct *mm);
+
+extern void cpu_dcache_inval_all(void);
+extern void cpu_dcache_wbinval_all(void);
+extern void cpu_dcache_inval_page(unsigned long page);
+extern void cpu_dcache_wb_page(unsigned long page);
+extern void cpu_dcache_wbinval_page(unsigned long page);
+extern void cpu_dcache_inval_range(unsigned long start, unsigned long end);
+extern void cpu_dcache_wb_range(unsigned long start, unsigned long end);
+extern void cpu_dcache_wbinval_range(unsigned long start, unsigned long end);
+
+extern void cpu_icache_inval_all(void);
+extern void cpu_icache_inval_page(unsigned long page);
+extern void cpu_icache_inval_range(unsigned long start, unsigned long end);
+
+extern void cpu_cache_wbinval_page(unsigned long page, int flushi);
+extern void cpu_cache_wbinval_range(unsigned long start,
+ unsigned long end, int flushi);
+extern void cpu_cache_wbinval_range_check(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end, bool flushi,
+ bool wbd);
+
+extern void cpu_dma_wb_range(unsigned long start, unsigned long end);
+extern void cpu_dma_inval_range(unsigned long start, unsigned long end);
+extern void cpu_dma_wbinval_range(unsigned long start, unsigned long end);
+
+#endif /* __KERNEL__ */
+#endif /* __NDS32_PROCFNS_H__ */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 000000000000..9c83caf4269f
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PROCESSOR_H
+#define __ASM_NDS32_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#ifdef __KERNEL__
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+#include <asm/sigcontext.h>
+
+#define KERNEL_STACK_SIZE PAGE_SIZE
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX TASK_SIZE
+
+struct cpu_context {
+ unsigned long r6;
+ unsigned long r7;
+ unsigned long r8;
+ unsigned long r9;
+ unsigned long r10;
+ unsigned long r11;
+ unsigned long r12;
+ unsigned long r13;
+ unsigned long r14;
+ unsigned long fp;
+ unsigned long pc;
+ unsigned long sp;
+};
+
+struct thread_struct {
+ struct cpu_context cpu_context; /* cpu context */
+ /* fault info */
+ unsigned long address;
+ unsigned long trap_no;
+ unsigned long error_code;
+};
+
+#define INIT_THREAD { }
+
+#ifdef __NDS32_EB__
+#define PSW_DE PSW_mskBE
+#else
+#define PSW_DE 0x0
+#endif
+
+#ifdef CONFIG_WBNA
+#define PSW_valWBNA PSW_mskWBNA
+#else
+#define PSW_valWBNA 0x0
+#endif
+
+#ifdef CONFIG_HWZOL
+#define PSW_valINIT (PSW_CPL_ANY | PSW_mskAEN | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE | PSW_mskGIE)
+#else
+#define PSW_valINIT (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE | PSW_mskGIE)
+#endif
+
+#define start_thread(regs,pc,stack) \
+({ \
+ memzero(regs, sizeof(struct pt_regs)); \
+ forget_syscall(regs); \
+ regs->ipsw = PSW_valINIT; \
+ regs->ir0 = (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE | PSW_SYSTEM | PSW_INTL_1); \
+ regs->ipc = pc; \
+ regs->sp = stack; \
+})
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk) do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define cpu_relax() barrier()
+
+#define task_pt_regs(task) \
+ ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+ - 8) - 1)
+
+/*
+ * Create a new kernel thread
+ */
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
+
+#define KSTK_EIP(tsk) instruction_pointer(task_pt_regs(tsk))
+#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
+
+#endif
+
+#endif /* __ASM_NDS32_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 000000000000..c4538839055c
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PTRACE_H
+#define __ASM_NDS32_PTRACE_H
+
+#include <uapi/asm/ptrace.h>
+
+/*
+ * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
+ * a syscall -- i.e., its most recent entry into the kernel from
+ * userspace was not via syscall, or otherwise a tracer cancelled the
+ * syscall.
+ *
+ * This must have the value -1, for ABI compatibility with ptrace etc.
+ */
+#define NO_SYSCALL (-1)
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+struct pt_regs {
+ union {
+ struct user_pt_regs user_regs;
+ struct {
+ long uregs[26];
+ long fp;
+ long gp;
+ long lp;
+ long sp;
+ long ipc;
+#if defined(CONFIG_HWZOL)
+ long lb;
+ long le;
+ long lc;
+#else
+ long dummy[3];
+#endif
+ long syscallno;
+ };
+ };
+ long orig_r0;
+ long ir0;
+ long ipsw;
+ long pipsw;
+ long pipc;
+ long pp0;
+ long pp1;
+ long fucop_ctl;
+ long osp;
+};
+
+static inline bool in_syscall(struct pt_regs const *regs)
+{
+ return regs->syscallno != NO_SYSCALL;
+}
+
+static inline void forget_syscall(struct pt_regs *regs)
+{
+ regs->syscallno = NO_SYSCALL;
+}
+static inline unsigned long regs_return_value(struct pt_regs *regs)
+{
+ return regs->uregs[0];
+}
+extern void show_regs(struct pt_regs *);
+/* Avoid circular header include via sched.h */
+struct task_struct;
+
+#define arch_has_single_step() (1)
+#define user_mode(regs) (((regs)->ipsw & PSW_mskPOM) == 0)
+#define interrupts_enabled(regs) (!!((regs)->ipsw & PSW_mskGIE))
+#define user_stack_pointer(regs) ((regs)->sp)
+#define instruction_pointer(regs) ((regs)->ipc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/nds32/include/asm/shmparam.h b/arch/nds32/include/asm/shmparam.h
new file mode 100644
index 000000000000..fd1cff64b68e
--- /dev/null
+++ b/arch/nds32/include/asm/shmparam.h
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_SHMPARAM_H
+#define _ASMNDS32_SHMPARAM_H
+
+/*
+ * This should be the size of the virtually indexed cache/ways,
+ * whichever is greater since the cache aliases every size/ways
+ * bytes.
+ */
+#define SHMLBA (4 * SZ_8K) /* attach addr a multiple of this */
+
+/*
+ * Enforce SHMLBA in shmat
+ */
+#define __ARCH_FORCE_SHMLBA
+
+#endif /* _ASMNDS32_SHMPARAM_H */
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 000000000000..179272caa540
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_STRING_H
+#define __ASM_NDS32_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+extern void *memzero(void *ptr, __kernel_size_t n);
+#endif
diff --git a/arch/nds32/include/asm/swab.h b/arch/nds32/include/asm/swab.h
new file mode 100644
index 000000000000..e01a755a37d2
--- /dev/null
+++ b/arch/nds32/include/asm/swab.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_SWAB_H__
+#define __NDS32_SWAB_H__
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+ __asm__("wsbh %0, %0\n\t" /* word swap byte within halfword */
+ "rotri %0, %0, #16\n"
+ :"=r"(x)
+ :"0"(x));
+ return x;
+}
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+ __asm__("wsbh %0, %0\n" /* word swap byte within halfword */
+ :"=r"(x)
+ :"0"(x));
+ return x;
+}
+
+#define __arch_swab32(x) ___arch__swab32(x)
+#define __arch_swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#define __BYTEORDER_HAS_U64__
+#define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __NDS32_SWAB_H__ */
diff --git a/arch/nds32/include/asm/syscall.h b/arch/nds32/include/asm/syscall.h
new file mode 100644
index 000000000000..f7e5e86765fe
--- /dev/null
+++ b/arch/nds32/include/asm/syscall.h
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2008-2009 Red Hat, Inc. All rights reserved.
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASM_NDS32_SYSCALL_H
+#define _ASM_NDS32_SYSCALL_H 1
+
+#include <linux/err.h>
+struct task_struct;
+struct pt_regs;
+
+/**
+ * syscall_get_nr - find what system call a task is executing
+ * @task: task of interest, must be blocked
+ * @regs: task_pt_regs() of @task
+ *
+ * If @task is executing a system call or is at system call
+ * tracing about to attempt one, returns the system call number.
+ * If @task is not executing a system call, i.e. it's blocked
+ * inside the kernel for a fault or signal, returns -1.
+ *
+ * Note this returns int even on 64-bit machines. Only 32 bits of
+ * system call number can be meaningful. If the actual arch value
+ * is 64 bits, this truncates to 32 bits so 0xffffffff means -1.
+ *
+ * It's only valid to call this when @task is known to be blocked.
+ */
+int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->syscallno;
+}
+
+/**
+ * syscall_rollback - roll back registers after an aborted system call
+ * @task: task of interest, must be in system call exit tracing
+ * @regs: task_pt_regs() of @task
+ *
+ * It's only valid to call this when @task is stopped for system
+ * call exit tracing (due to TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT),
+ * after tracehook_report_syscall_entry() returned nonzero to prevent
+ * the system call from taking place.
+ *
+ * This rolls back the register state in @regs so it's as if the
+ * system call instruction was a no-op. The registers containing
+ * the system call number and arguments are as they were before the
+ * system call instruction. This may not be the same as what the
+ * register state looked like at system call entry tracing.
+ */
+void syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+ regs->uregs[0] = regs->orig_r0;
+}
+
+/**
+ * syscall_get_error - check result of traced system call
+ * @task: task of interest, must be blocked
+ * @regs: task_pt_regs() of @task
+ *
+ * Returns 0 if the system call succeeded, or -ERRORCODE if it failed.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+ unsigned long error = regs->uregs[0];
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+/**
+ * syscall_get_return_value - get the return value of a traced system call
+ * @task: task of interest, must be blocked
+ * @regs: task_pt_regs() of @task
+ *
+ * Returns the return value of the successful system call.
+ * This value is meaningless if syscall_get_error() returned nonzero.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+long syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->uregs[0];
+}
+
+/**
+ * syscall_set_return_value - change the return value of a traced system call
+ * @task: task of interest, must be blocked
+ * @regs: task_pt_regs() of @task
+ * @error: negative error code, or zero to indicate success
+ * @val: user return value if @error is zero
+ *
+ * This changes the results of the system call that user mode will see.
+ * If @error is zero, the user sees a successful system call with a
+ * return value of @val. If @error is nonzero, it's a negated errno
+ * code; the user sees a failed system call with this errno code.
+ *
+ * It's only valid to call this when @task is stopped for tracing on exit
+ * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ */
+void syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+ int error, long val)
+{
+ regs->uregs[0] = (long)error ? error : val;
+}
+
+/**
+ * syscall_get_arguments - extract system call parameter values
+ * @task: task of interest, must be blocked
+ * @regs: task_pt_regs() of @task
+ * @i: argument index [0,5]
+ * @n: number of arguments; n+i must be [1,6].
+ * @args: array filled with argument values
+ *
+ * Fetches @n arguments to the system call starting with the @i'th argument
+ * (from 0 through 5). Argument @i is stored in @args[0], and so on.
+ * An arch inline version is probably optimal when @i and @n are constants.
+ *
+ * It's only valid to call this when @task is stopped for tracing on
+ * entry to a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ * It's invalid to call this with @i + @n > 6; we only support system calls
+ * taking up to 6 arguments.
+ */
+#define SYSCALL_MAX_ARGS 6
+void syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, unsigned long *args)
+{
+ if (n == 0)
+ return;
+ if (i + n > SYSCALL_MAX_ARGS) {
+ unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+ unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+ pr_warning("%s called with max args %d, handling only %d\n",
+ __func__, i + n, SYSCALL_MAX_ARGS);
+ memset(args_bad, 0, n_bad * sizeof(args[0]));
+ memset(args_bad, 0, n_bad * sizeof(args[0]));
+ }
+
+ if (i == 0) {
+ args[0] = regs->orig_r0;
+ args++;
+ i++;
+ n--;
+ }
+
+ memcpy(args, &regs->uregs[0] + i, n * sizeof(args[0]));
+}
+
+/**
+ * syscall_set_arguments - change system call parameter value
+ * @task: task of interest, must be in system call entry tracing
+ * @regs: task_pt_regs() of @task
+ * @i: argument index [0,5]
+ * @n: number of arguments; n+i must be [1,6].
+ * @args: array of argument values to store
+ *
+ * Changes @n arguments to the system call starting with the @i'th argument.
+ * Argument @i gets value @args[0], and so on.
+ * An arch inline version is probably optimal when @i and @n are constants.
+ *
+ * It's only valid to call this when @task is stopped for tracing on
+ * entry to a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT.
+ * It's invalid to call this with @i + @n > 6; we only support system calls
+ * taking up to 6 arguments.
+ */
+void syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n,
+ const unsigned long *args)
+{
+ if (n == 0)
+ return;
+
+ if (i + n > SYSCALL_MAX_ARGS) {
+ pr_warn("%s called with max args %d, handling only %d\n",
+ __func__, i + n, SYSCALL_MAX_ARGS);
+ n = SYSCALL_MAX_ARGS - i;
+ }
+
+ if (i == 0) {
+ regs->orig_r0 = args[0];
+ args++;
+ i++;
+ n--;
+ }
+
+ memcpy(&regs->uregs[0] + i, args, n * sizeof(args[0]));
+}
+#endif /* _ASM_NDS32_SYSCALL_H */
diff --git a/arch/nds32/include/asm/syscalls.h b/arch/nds32/include/asm/syscalls.h
new file mode 100644
index 000000000000..78778ecff60c
--- /dev/null
+++ b/arch/nds32/include/asm/syscalls.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_SYSCALLS_H
+#define __ASM_NDS32_SYSCALLS_H
+
+asmlinkage long sys_cacheflush(unsigned long addr, unsigned long len, unsigned int op);
+asmlinkage long sys_fadvise64_64_wrapper(int fd, int advice, loff_t offset, loff_t len);
+asmlinkage long sys_rt_sigreturn_wrapper(void);
+
+#include <asm-generic/syscalls.h>
+
+#endif /* __ASM_NDS32_SYSCALLS_H */
diff --git a/arch/nds32/include/asm/thread_info.h b/arch/nds32/include/asm/thread_info.h
new file mode 100644
index 000000000000..bff741ff337b
--- /dev/null
+++ b/arch/nds32/include/asm/thread_info.h
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_THREAD_INFO_H
+#define __ASM_NDS32_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#define THREAD_SIZE_ORDER (1)
+#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+typedef unsigned long mm_segment_t;
+
+/*
+ * low level task data that entry.S needs immediate access to.
+ * __switch_to() assumes cpu_context follows immediately after cpu_domain.
+ */
+struct thread_info {
+ unsigned long flags; /* low level flags */
+ __s32 preempt_count; /* 0 => preemptable, <0 => bug */
+ mm_segment_t addr_limit; /* address limit */
+};
+#define INIT_THREAD_INFO(tsk) \
+{ \
+ .preempt_count = INIT_PREEMPT_COUNT, \
+ .addr_limit = KERNEL_DS, \
+}
+#define thread_saved_pc(tsk) ((unsigned long)(tsk->thread.cpu_context.pc))
+#define thread_saved_fp(tsk) ((unsigned long)(tsk->thread.cpu_context.fp))
+#endif
+
+/*
+ * thread information flags:
+ * TIF_SYSCALL_TRACE - syscall trace active
+ * TIF_SIGPENDING - signal pending
+ * TIF_NEED_RESCHED - rescheduling necessary
+ * TIF_NOTIFY_RESUME - callback before returning to user
+ * TIF_USEDFPU - FPU was used by this task this quantum (SMP)
+ * TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED
+ */
+#define TIF_SIGPENDING 1
+#define TIF_NEED_RESCHED 2
+#define TIF_SINGLESTEP 3
+#define TIF_NOTIFY_RESUME 4 /* callback before returning to user */
+#define TIF_SYSCALL_TRACE 8
+#define TIF_USEDFPU 16
+#define TIF_POLLING_NRFLAG 17
+#define TIF_MEMDIE 18
+#define TIF_FREEZE 19
+#define TIF_RESTORE_SIGMASK 20
+
+#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
+#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
+#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
+#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
+#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE (1 << TIF_FREEZE)
+#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
+
+/*
+ * Change these and you break ASM code in entry-common.S
+ */
+#define _TIF_WORK_MASK 0x000000ff
+#define _TIF_WORK_SYSCALL_ENTRY (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)
+#define _TIF_WORK_SYSCALL_LEAVE (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_NDS32_THREAD_INFO_H */
diff --git a/arch/nds32/include/asm/tlb.h b/arch/nds32/include/asm/tlb.h
new file mode 100644
index 000000000000..b35ae5eae3ab
--- /dev/null
+++ b/arch/nds32/include/asm/tlb.h
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASMNDS32_TLB_H
+#define __ASMNDS32_TLB_H
+
+#define tlb_start_vma(tlb,vma) \
+ do { \
+ if (!tlb->fullmm) \
+ flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+ } while (0)
+
+#define tlb_end_vma(tlb,vma) \
+ do { \
+ if(!tlb->fullmm) \
+ flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
+ } while (0)
+
+#define __tlb_remove_tlb_entry(tlb, pte, addr) do { } while (0)
+
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, pte)
+#define __pmd_free_tlb(tlb, pmd, addr) pmd_free((tln)->mm, pmd)
+
+#endif
diff --git a/arch/nds32/include/asm/tlbflush.h b/arch/nds32/include/asm/tlbflush.h
new file mode 100644
index 000000000000..9b411f401903
--- /dev/null
+++ b/arch/nds32/include/asm/tlbflush.h
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_TLBFLUSH_H
+#define _ASMNDS32_TLBFLUSH_H
+
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <nds32_intrinsic.h>
+
+static inline void local_flush_tlb_all(void)
+{
+ __nds32__tlbop_flua();
+ __nds32__isb();
+}
+
+static inline void local_flush_tlb_mm(struct mm_struct *mm)
+{
+ __nds32__tlbop_flua();
+ __nds32__isb();
+}
+
+static inline void local_flush_tlb_kernel_range(unsigned long start,
+ unsigned long end)
+{
+ while (start < end) {
+ __nds32__tlbop_inv(start);
+ __nds32__isb();
+ start += PAGE_SIZE;
+ }
+}
+
+void local_flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end);
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
+
+#define flush_tlb_all local_flush_tlb_all
+#define flush_tlb_mm local_flush_tlb_mm
+#define flush_tlb_range local_flush_tlb_range
+#define flush_tlb_page local_flush_tlb_page
+#define flush_tlb_kernel_range local_flush_tlb_kernel_range
+
+void update_mmu_cache(struct vm_area_struct *vma,
+ unsigned long address, pte_t * pte);
+void tlb_migrate_finish(struct mm_struct *mm);
+
+#endif
diff --git a/arch/nds32/include/asm/uaccess.h b/arch/nds32/include/asm/uaccess.h
new file mode 100644
index 000000000000..18a009f3804d
--- /dev/null
+++ b/arch/nds32/include/asm/uaccess.h
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMANDES_UACCESS_H
+#define _ASMANDES_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/sched.h>
+#include <asm/errno.h>
+#include <asm/memory.h>
+#include <asm/types.h>
+#include <linux/mm.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue. No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path. This means when everything is well,
+ * we don't even have to jump over them. Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+ unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+#define KERNEL_DS ((mm_segment_t) { ~0UL })
+#define USER_DS ((mm_segment_t) {TASK_SIZE - 1})
+
+#define get_ds() (KERNEL_DS)
+#define get_fs() (current_thread_info()->addr_limit)
+#define user_addr_max get_fs
+
+static inline void set_fs(mm_segment_t fs)
+{
+ current_thread_info()->addr_limit = fs;
+}
+
+#define segment_eq(a, b) ((a) == (b))
+
+#define __range_ok(addr, size) (size <= get_fs() && addr <= (get_fs() -size))
+
+#define access_ok(type, addr, size) \
+ __range_ok((unsigned long)addr, (unsigned long)size)
+/*
+ * Single-value transfer routines. They automatically use the right
+ * size if we just have the right pointer type. Note that the functions
+ * which read from user space (*get_*) need to take care not to leak
+ * kernel data even if the calling code is buggy and fails to check
+ * the return value. This means zeroing out the destination variable
+ * or buffer on error. Normally this is done out of line by the
+ * fixup code, but there are a few places where it intrudes on the
+ * main code path. When we only write to user space, there is no
+ * problem.
+ *
+ * The "__xxx" versions of the user access functions do not verify the
+ * address space - it must have been done previously with a separate
+ * "access_ok()" call.
+ *
+ * The "xxx_error" versions set the third argument to EFAULT if an
+ * error occurs, and leave it unchanged on success. Note that these
+ * versions are void (ie, don't return a value as such).
+ */
+
+#define get_user(x,p) \
+({ \
+ long __e = -EFAULT; \
+ if(likely(access_ok(VERIFY_READ, p, sizeof(*p)))) { \
+ __e = __get_user(x,p); \
+ } else \
+ x = 0; \
+ __e; \
+})
+#define __get_user(x,ptr) \
+({ \
+ long __gu_err = 0; \
+ __get_user_err((x),(ptr),__gu_err); \
+ __gu_err; \
+})
+
+#define __get_user_error(x,ptr,err) \
+({ \
+ __get_user_err((x),(ptr),err); \
+ (void) 0; \
+})
+
+#define __get_user_err(x,ptr,err) \
+do { \
+ unsigned long __gu_addr = (unsigned long)(ptr); \
+ unsigned long __gu_val; \
+ __chk_user_ptr(ptr); \
+ switch (sizeof(*(ptr))) { \
+ case 1: \
+ __get_user_asm("lbi",__gu_val,__gu_addr,err); \
+ break; \
+ case 2: \
+ __get_user_asm("lhi",__gu_val,__gu_addr,err); \
+ break; \
+ case 4: \
+ __get_user_asm("lwi",__gu_val,__gu_addr,err); \
+ break; \
+ case 8: \
+ __get_user_asm_dword(__gu_val,__gu_addr,err); \
+ break; \
+ default: \
+ BUILD_BUG(); \
+ break; \
+ } \
+ (x) = (__typeof__(*(ptr)))__gu_val; \
+} while (0)
+
+#define __get_user_asm(inst,x,addr,err) \
+ asm volatile( \
+ "1: "inst" %1,[%2]\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "3: move %0, %3\n" \
+ " move %1, #0\n" \
+ " b 2b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 3b\n" \
+ " .previous" \
+ : "+r" (err), "=&r" (x) \
+ : "r" (addr), "i" (-EFAULT) \
+ : "cc")
+
+#ifdef __NDS32_EB__
+#define __gu_reg_oper0 "%H1"
+#define __gu_reg_oper1 "%L1"
+#else
+#define __gu_reg_oper0 "%L1"
+#define __gu_reg_oper1 "%H1"
+#endif
+
+#define __get_user_asm_dword(x, addr, err) \
+ asm volatile( \
+ "\n1:\tlwi " __gu_reg_oper0 ",[%2]\n" \
+ "\n2:\tlwi " __gu_reg_oper1 ",[%2+4]\n" \
+ "3:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "4: move %0, %3\n" \
+ " b 3b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 4b\n" \
+ " .long 2b, 4b\n" \
+ " .previous" \
+ : "+r"(err), "=&r"(x) \
+ : "r"(addr), "i"(-EFAULT) \
+ : "cc")
+#define put_user(x,p) \
+({ \
+ long __e = -EFAULT; \
+ if(likely(access_ok(VERIFY_WRITE, p, sizeof(*p)))) { \
+ __e = __put_user(x,p); \
+ } \
+ __e; \
+})
+#define __put_user(x,ptr) \
+({ \
+ long __pu_err = 0; \
+ __put_user_err((x),(ptr),__pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_error(x,ptr,err) \
+({ \
+ __put_user_err((x),(ptr),err); \
+ (void) 0; \
+})
+
+#define __put_user_err(x,ptr,err) \
+do { \
+ unsigned long __pu_addr = (unsigned long)(ptr); \
+ __typeof__(*(ptr)) __pu_val = (x); \
+ __chk_user_ptr(ptr); \
+ switch (sizeof(*(ptr))) { \
+ case 1: \
+ __put_user_asm("sbi",__pu_val,__pu_addr,err); \
+ break; \
+ case 2: \
+ __put_user_asm("shi",__pu_val,__pu_addr,err); \
+ break; \
+ case 4: \
+ __put_user_asm("swi",__pu_val,__pu_addr,err); \
+ break; \
+ case 8: \
+ __put_user_asm_dword(__pu_val,__pu_addr,err); \
+ break; \
+ default: \
+ BUILD_BUG(); \
+ break; \
+ } \
+} while (0)
+
+#define __put_user_asm(inst,x,addr,err) \
+ asm volatile( \
+ "1: "inst" %1,[%2]\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "3: move %0, %3\n" \
+ " b 2b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 3b\n" \
+ " .previous" \
+ : "+r" (err) \
+ : "r" (x), "r" (addr), "i" (-EFAULT) \
+ : "cc")
+
+#ifdef __NDS32_EB__
+#define __pu_reg_oper0 "%H2"
+#define __pu_reg_oper1 "%L2"
+#else
+#define __pu_reg_oper0 "%L2"
+#define __pu_reg_oper1 "%H2"
+#endif
+
+#define __put_user_asm_dword(x, addr, err) \
+ asm volatile( \
+ "\n1:\tswi " __pu_reg_oper0 ",[%1]\n" \
+ "\n2:\tswi " __pu_reg_oper1 ",[%1+4]\n" \
+ "3:\n" \
+ " .section .fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "4: move %0, %3\n" \
+ " b 3b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 4b\n" \
+ " .long 2b, 4b\n" \
+ " .previous" \
+ : "+r"(err) \
+ : "r"(addr), "r"(x), "i"(-EFAULT) \
+ : "cc")
+extern unsigned long __arch_clear_user(void __user * addr, unsigned long n);
+extern long strncpy_from_user(char *dest, const char __user * src, long count);
+extern __must_check long strlen_user(const char __user * str);
+extern __must_check long strnlen_user(const char __user * str, long n);
+extern unsigned long __arch_copy_from_user(void *to, const void __user * from,
+ unsigned long n);
+extern unsigned long __arch_copy_to_user(void __user * to, const void *from,
+ unsigned long n);
+
+#define raw_copy_from_user __arch_copy_from_user
+#define raw_copy_to_user __arch_copy_to_user
+
+#define INLINE_COPY_FROM_USER
+#define INLINE_COPY_TO_USER
+static inline unsigned long clear_user(void __user * to, unsigned long n)
+{
+ if (access_ok(VERIFY_WRITE, to, n))
+ n = __arch_clear_user(to, n);
+ return n;
+}
+
+static inline unsigned long __clear_user(void __user * to, unsigned long n)
+{
+ return __arch_clear_user(to, n);
+}
+
+#endif /* _ASMNDS32_UACCESS_H */
diff --git a/arch/nds32/include/asm/unistd.h b/arch/nds32/include/asm/unistd.h
new file mode 100644
index 000000000000..b586a2862beb
--- /dev/null
+++ b/arch/nds32/include/asm/unistd.h
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#define __ARCH_WANT_SYS_CLONE
+
+#include <uapi/asm/unistd.h>
diff --git a/arch/nds32/include/asm/vdso.h b/arch/nds32/include/asm/vdso.h
new file mode 100644
index 000000000000..af2c6afc2469
--- /dev/null
+++ b/arch/nds32/include/asm/vdso.h
@@ -0,0 +1,24 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ */
+
+#ifndef __ASM_VDSO_H
+#define __ASM_VDSO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+#include <generated/vdso-offsets.h>
+
+#define VDSO_SYMBOL(base, name) \
+({ \
+ (unsigned long)(vdso_offset_##name + (unsigned long)(base)); \
+})
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_H */
diff --git a/arch/nds32/include/asm/vdso_datapage.h b/arch/nds32/include/asm/vdso_datapage.h
new file mode 100644
index 000000000000..79db5a12ca5e
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_datapage.h
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+#ifndef __ASM_VDSO_DATAPAGE_H
+#define __ASM_VDSO_DATAPAGE_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+
+struct vdso_data {
+ bool cycle_count_down; /* timer cyclye counter is decrease with time */
+ u32 cycle_count_offset; /* offset of timer cycle counter register */
+ u32 seq_count; /* sequence count - odd during updates */
+ u32 xtime_coarse_sec; /* coarse time */
+ u32 xtime_coarse_nsec;
+
+ u32 wtm_clock_sec; /* wall to monotonic offset */
+ u32 wtm_clock_nsec;
+ u32 xtime_clock_sec; /* CLOCK_REALTIME - seconds */
+ u32 cs_mult; /* clocksource multiplier */
+ u32 cs_shift; /* Cycle to nanosecond divisor (power of two) */
+
+ u64 cs_cycle_last; /* last cycle value */
+ u64 cs_mask; /* clocksource mask */
+
+ u64 xtime_clock_nsec; /* CLOCK_REALTIME sub-ns base */
+ u32 tz_minuteswest; /* timezone info for gettimeofday(2) */
+ u32 tz_dsttime;
+};
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_VDSO_DATAPAGE_H */
diff --git a/arch/nds32/include/asm/vdso_timer_info.h b/arch/nds32/include/asm/vdso_timer_info.h
new file mode 100644
index 000000000000..50ba117cff12
--- /dev/null
+++ b/arch/nds32/include/asm/vdso_timer_info.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+extern struct timer_info_t timer_info;
+#define EMPTY_VALUE ~(0UL)
+#define EMPTY_TIMER_MAPPING EMPTY_VALUE
+#define EMPTY_REG_OFFSET EMPTY_VALUE
+
+struct timer_info_t
+{
+ bool cycle_count_down;
+ unsigned long mapping_base;
+ unsigned long cycle_count_reg_offset;
+};
diff --git a/arch/metag/include/uapi/asm/Kbuild b/arch/nds32/include/uapi/asm/Kbuild
index f9eaf07d29f8..40be972faf9e 100644
--- a/arch/metag/include/uapi/asm/Kbuild
+++ b/arch/nds32/include/uapi/asm/Kbuild
@@ -1,29 +1,27 @@
# UAPI Header export list
include include/uapi/asm-generic/Kbuild.asm
-generic-y += auxvec.h
-generic-y += bitsperlong.h
generic-y += bpf_perf_event.h
generic-y += errno.h
-generic-y += fcntl.h
generic-y += ioctl.h
generic-y += ioctls.h
generic-y += ipcbuf.h
-generic-y += kvm_para.h
+generic-y += shmbuf.h
+generic-y += bitsperlong.h
+generic-y += fcntl.h
+generic-y += stat.h
generic-y += mman.h
generic-y += msgbuf.h
-generic-y += param.h
generic-y += poll.h
generic-y += posix_types.h
generic-y += resource.h
generic-y += sembuf.h
generic-y += setup.h
-generic-y += shmbuf.h
-generic-y += shmparam.h
+generic-y += siginfo.h
generic-y += signal.h
generic-y += socket.h
generic-y += sockios.h
-generic-y += stat.h
+generic-y += swab.h
generic-y += statfs.h
generic-y += termbits.h
generic-y += termios.h
diff --git a/arch/nds32/include/uapi/asm/auxvec.h b/arch/nds32/include/uapi/asm/auxvec.h
new file mode 100644
index 000000000000..56043ce4972f
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/auxvec.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_AUXVEC_H
+#define __ASM_AUXVEC_H
+
+/* VDSO location */
+#define AT_SYSINFO_EHDR 33
+
+#define AT_VECTOR_SIZE_ARCH 1
+
+#endif
diff --git a/arch/nds32/include/uapi/asm/byteorder.h b/arch/nds32/include/uapi/asm/byteorder.h
new file mode 100644
index 000000000000..a23f6f3a2468
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/byteorder.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __NDS32_BYTEORDER_H__
+#define __NDS32_BYTEORDER_H__
+
+#ifdef __NDS32_EB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif /* __NDS32_BYTEORDER_H__ */
diff --git a/arch/nds32/include/uapi/asm/cachectl.h b/arch/nds32/include/uapi/asm/cachectl.h
new file mode 100644
index 000000000000..4cdca9b23974
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/cachectl.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+// Copyright (C) 2005-2017 Andes Technology Corporation
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE 0 /* flush instruction cache */
+#define DCACHE 1 /* writeback and flush data cache */
+#define BCACHE 2 /* flush instruction cache + writeback and flush data cache */
+
+#endif /* _ASM_CACHECTL */
diff --git a/arch/nds32/include/uapi/asm/param.h b/arch/nds32/include/uapi/asm/param.h
new file mode 100644
index 000000000000..e3fb723ee362
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/param.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __ASM_NDS32_PARAM_H
+#define __ASM_NDS32_PARAM_H
+
+#define EXEC_PAGESIZE 8192
+
+#include <asm-generic/param.h>
+
+#endif /* __ASM_NDS32_PARAM_H */
diff --git a/arch/nds32/include/uapi/asm/ptrace.h b/arch/nds32/include/uapi/asm/ptrace.h
new file mode 100644
index 000000000000..358c99e399d0
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/ptrace.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef __UAPI_ASM_NDS32_PTRACE_H
+#define __UAPI_ASM_NDS32_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * User structures for general purpose register.
+ */
+struct user_pt_regs {
+ long uregs[26];
+ long fp;
+ long gp;
+ long lp;
+ long sp;
+ long ipc;
+ long lb;
+ long le;
+ long lc;
+ long syscallno;
+};
+#endif
+#endif
diff --git a/arch/nds32/include/uapi/asm/sigcontext.h b/arch/nds32/include/uapi/asm/sigcontext.h
new file mode 100644
index 000000000000..00567b237b0c
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/sigcontext.h
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#ifndef _ASMNDS32_SIGCONTEXT_H
+#define _ASMNDS32_SIGCONTEXT_H
+
+/*
+ * Signal context structure - contains all info to do with the state
+ * before the signal handler was invoked. Note: only add new entries
+ * to the end of the structure.
+ */
+
+struct zol_struct {
+ unsigned long nds32_lc; /* $LC */
+ unsigned long nds32_le; /* $LE */
+ unsigned long nds32_lb; /* $LB */
+};
+
+struct sigcontext {
+ unsigned long trap_no;
+ unsigned long error_code;
+ unsigned long oldmask;
+ unsigned long nds32_r0;
+ unsigned long nds32_r1;
+ unsigned long nds32_r2;
+ unsigned long nds32_r3;
+ unsigned long nds32_r4;
+ unsigned long nds32_r5;
+ unsigned long nds32_r6;
+ unsigned long nds32_r7;
+ unsigned long nds32_r8;
+ unsigned long nds32_r9;
+ unsigned long nds32_r10;
+ unsigned long nds32_r11;
+ unsigned long nds32_r12;
+ unsigned long nds32_r13;
+ unsigned long nds32_r14;
+ unsigned long nds32_r15;
+ unsigned long nds32_r16;
+ unsigned long nds32_r17;
+ unsigned long nds32_r18;
+ unsigned long nds32_r19;
+ unsigned long nds32_r20;
+ unsigned long nds32_r21;
+ unsigned long nds32_r22;
+ unsigned long nds32_r23;
+ unsigned long nds32_r24;
+ unsigned long nds32_r25;
+ unsigned long nds32_fp; /* $r28 */
+ unsigned long nds32_gp; /* $r29 */
+ unsigned long nds32_lp; /* $r30 */
+ unsigned long nds32_sp; /* $r31 */
+ unsigned long nds32_ipc;
+ unsigned long fault_address;
+ unsigned long used_math_flag;
+ /* FPU Registers */
+ struct zol_struct zol;
+};
+
+#endif
diff --git a/arch/nds32/include/uapi/asm/unistd.h b/arch/nds32/include/uapi/asm/unistd.h
new file mode 100644
index 000000000000..6e95901cabe3
--- /dev/null
+++ b/arch/nds32/include/uapi/asm/unistd.h
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#define __ARCH_WANT_SYNC_FILE_RANGE2
+
+/* Use the standard ABI for syscalls */
+#include <asm-generic/unistd.h>
+
+/* Additional NDS32 specific syscalls. */
+#define __NR_cacheflush (__NR_arch_specific_syscall)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/nds32/kernel/Makefile b/arch/nds32/kernel/Makefile
new file mode 100644
index 000000000000..42792743e8b9
--- /dev/null
+++ b/arch/nds32/kernel/Makefile
@@ -0,0 +1,23 @@
+#
+# Makefile for the linux kernel.
+#
+
+CPPFLAGS_vmlinux.lds := -DTEXTADDR=$(TEXTADDR)
+AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR)
+
+# Object file lists.
+
+obj-y := ex-entry.o ex-exit.o ex-scall.o irq.o \
+ process.o ptrace.o setup.o signal.o \
+ sys_nds32.o time.o traps.o cacheinfo.o \
+ dma.o syscall_table.o vdso.o
+
+obj-$(CONFIG_MODULES) += nds32_ksyms.o module.o
+obj-$(CONFIG_STACKTRACE) += stacktrace.o
+obj-$(CONFIG_OF) += devtree.o
+obj-$(CONFIG_CACHE_L2) += atl2c.o
+
+extra-y := head.o vmlinux.lds
+
+
+obj-y += vdso/
diff --git a/arch/nds32/kernel/asm-offsets.c b/arch/nds32/kernel/asm-offsets.c
new file mode 100644
index 000000000000..3541d5981de7
--- /dev/null
+++ b/arch/nds32/kernel/asm-offsets.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/sched.h>
+#include <linux/sched/task_stack.h>
+#include <linux/kbuild.h>
+#include <asm/thread_info.h>
+#include <asm/ptrace.h>
+
+int main(void)
+{
+ DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
+ DEFINE(TSK_TI_PREEMPT,
+ offsetof(struct task_struct, thread_info.preempt_count));
+ DEFINE(THREAD_CPU_CONTEXT,
+ offsetof(struct task_struct, thread.cpu_context));
+ DEFINE(OSP_OFFSET, offsetof(struct pt_regs, osp));
+ DEFINE(SP_OFFSET, offsetof(struct pt_regs, sp));
+ DEFINE(FUCOP_CTL_OFFSET, offsetof(struct pt_regs, fucop_ctl));
+ DEFINE(IPSW_OFFSET, offsetof(struct pt_regs, ipsw));
+ DEFINE(SYSCALLNO_OFFSET, offsetof(struct pt_regs, syscallno));
+ DEFINE(IPC_OFFSET, offsetof(struct pt_regs, ipc));
+ DEFINE(R0_OFFSET, offsetof(struct pt_regs, uregs[0]));
+ DEFINE(R15_OFFSET, offsetof(struct pt_regs, uregs[15]));
+ DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
+ DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
+ return 0;
+}
diff --git a/arch/nds32/kernel/atl2c.c b/arch/nds32/kernel/atl2c.c
new file mode 100644
index 000000000000..0c6d031a1c4a
--- /dev/null
+++ b/arch/nds32/kernel/atl2c.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/compiler.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <asm/l2_cache.h>
+
+void __iomem *atl2c_base;
+static const struct of_device_id atl2c_ids[] __initconst = {
+ {.compatible = "andestech,atl2c",}
+};
+
+static int __init atl2c_of_init(void)
+{
+ struct device_node *np;
+ struct resource res;
+ unsigned long tmp = 0;
+ unsigned long l2set, l2way, l2clsz;
+
+ if (!(__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C))
+ return -ENODEV;
+
+ np = of_find_matching_node(NULL, atl2c_ids);
+ if (!np)
+ return -ENODEV;
+
+ if (of_address_to_resource(np, 0, &res))
+ return -ENODEV;
+
+ atl2c_base = ioremap(res.start, resource_size(&res));
+ if (!atl2c_base)
+ return -ENOMEM;
+
+ l2set =
+ 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
+ L2_CA_CONF_offL2SET);
+ l2way =
+ 1 +
+ ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
+ L2_CA_CONF_offL2WAY);
+ l2clsz =
+ 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >>
+ L2_CA_CONF_offL2CLSZ);
+ pr_info("L2:%luKB/%luS/%luW/%luB\n",
+ l2set * l2way * l2clsz / 1024, l2set, l2way, l2clsz);
+
+ tmp = L2C_R_REG(L2CC_PROT_OFF);
+ tmp &= ~L2CC_PROT_mskMRWEN;
+ L2C_W_REG(L2CC_PROT_OFF, tmp);
+
+ tmp = L2C_R_REG(L2CC_SETUP_OFF);
+ tmp &= ~L2CC_SETUP_mskPART;
+ L2C_W_REG(L2CC_SETUP_OFF, tmp);
+
+ tmp = L2C_R_REG(L2CC_CTRL_OFF);
+ tmp |= L2CC_CTRL_mskEN;
+ L2C_W_REG(L2CC_CTRL_OFF, tmp);
+
+ return 0;
+}
+
+subsys_initcall(atl2c_of_init);
diff --git a/arch/nds32/kernel/cacheinfo.c b/arch/nds32/kernel/cacheinfo.c
new file mode 100644
index 000000000000..0a7bc696dd55
--- /dev/null
+++ b/arch/nds32/kernel/cacheinfo.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/bitops.h>
+#include <linux/cacheinfo.h>
+#include <linux/cpu.h>
+
+static void ci_leaf_init(struct cacheinfo *this_leaf,
+ enum cache_type type, unsigned int level)
+{
+ char cache_type = (type & CACHE_TYPE_INST ? ICACHE : DCACHE);
+
+ this_leaf->level = level;
+ this_leaf->type = type;
+ this_leaf->coherency_line_size = CACHE_LINE_SIZE(cache_type);
+ this_leaf->number_of_sets = CACHE_SET(cache_type);;
+ this_leaf->ways_of_associativity = CACHE_WAY(cache_type);
+ this_leaf->size = this_leaf->number_of_sets *
+ this_leaf->coherency_line_size * this_leaf->ways_of_associativity;
+#if defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
+ this_leaf->attributes = CACHE_WRITE_THROUGH;
+#else
+ this_leaf->attributes = CACHE_WRITE_BACK;
+#endif
+}
+
+int init_cache_level(unsigned int cpu)
+{
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+
+ /* Only 1 level and I/D cache seperate. */
+ this_cpu_ci->num_levels = 1;
+ this_cpu_ci->num_leaves = 2;
+ return 0;
+}
+
+int populate_cache_leaves(unsigned int cpu)
+{
+ unsigned int level, idx;
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+
+ for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
+ idx < this_cpu_ci->num_leaves; idx++, level++) {
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+ }
+ return 0;
+}
diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c
new file mode 100644
index 000000000000..bdce0fe5af9f
--- /dev/null
+++ b/arch/nds32/kernel/devtree.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/bug.h>
+#include <linux/printk.h>
+#include <linux/of_fdt.h>
+
+void __init early_init_devtree(void *params)
+{
+ if (!params || !early_init_dt_scan(params)) {
+ pr_crit("\n"
+ "Error: invalid device tree blob at (virtual address 0x%p)\n"
+ "\nPlease check your bootloader.", params);
+
+ BUG_ON(1);
+ }
+
+ dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
+}
diff --git a/arch/nds32/kernel/dma.c b/arch/nds32/kernel/dma.c
new file mode 100644
index 000000000000..d291800fc621
--- /dev/null
+++ b/arch/nds32/kernel/dma.c
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/export.h>
+#include <linux/string.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/cache.h>
+#include <linux/highmem.h>
+#include <linux/slab.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/dma-mapping.h>
+#include <asm/proc-fns.h>
+
+/*
+ * This is the page table (2MB) covering uncached, DMA consistent allocations
+ */
+static pte_t *consistent_pte;
+static DEFINE_RAW_SPINLOCK(consistent_lock);
+
+enum master_type {
+ FOR_CPU = 0,
+ FOR_DEVICE = 1,
+};
+
+/*
+ * VM region handling support.
+ *
+ * This should become something generic, handling VM region allocations for
+ * vmalloc and similar (ioremap, module space, etc).
+ *
+ * I envisage vmalloc()'s supporting vm_struct becoming:
+ *
+ * struct vm_struct {
+ * struct vm_region region;
+ * unsigned long flags;
+ * struct page **pages;
+ * unsigned int nr_pages;
+ * unsigned long phys_addr;
+ * };
+ *
+ * get_vm_area() would then call vm_region_alloc with an appropriate
+ * struct vm_region head (eg):
+ *
+ * struct vm_region vmalloc_head = {
+ * .vm_list = LIST_HEAD_INIT(vmalloc_head.vm_list),
+ * .vm_start = VMALLOC_START,
+ * .vm_end = VMALLOC_END,
+ * };
+ *
+ * However, vmalloc_head.vm_start is variable (typically, it is dependent on
+ * the amount of RAM found at boot time.) I would imagine that get_vm_area()
+ * would have to initialise this each time prior to calling vm_region_alloc().
+ */
+struct arch_vm_region {
+ struct list_head vm_list;
+ unsigned long vm_start;
+ unsigned long vm_end;
+ struct page *vm_pages;
+};
+
+static struct arch_vm_region consistent_head = {
+ .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
+ .vm_start = CONSISTENT_BASE,
+ .vm_end = CONSISTENT_END,
+};
+
+static struct arch_vm_region *vm_region_alloc(struct arch_vm_region *head,
+ size_t size, int gfp)
+{
+ unsigned long addr = head->vm_start, end = head->vm_end - size;
+ unsigned long flags;
+ struct arch_vm_region *c, *new;
+
+ new = kmalloc(sizeof(struct arch_vm_region), gfp);
+ if (!new)
+ goto out;
+
+ raw_spin_lock_irqsave(&consistent_lock, flags);
+
+ list_for_each_entry(c, &head->vm_list, vm_list) {
+ if ((addr + size) < addr)
+ goto nospc;
+ if ((addr + size) <= c->vm_start)
+ goto found;
+ addr = c->vm_end;
+ if (addr > end)
+ goto nospc;
+ }
+
+found:
+ /*
+ * Insert this entry _before_ the one we found.
+ */
+ list_add_tail(&new->vm_list, &c->vm_list);
+ new->vm_start = addr;
+ new->vm_end = addr + size;
+
+ raw_spin_unlock_irqrestore(&consistent_lock, flags);
+ return new;
+
+nospc:
+ raw_spin_unlock_irqrestore(&consistent_lock, flags);
+ kfree(new);
+out:
+ return NULL;
+}
+
+static struct arch_vm_region *vm_region_find(struct arch_vm_region *head,
+ unsigned long addr)
+{
+ struct arch_vm_region *c;
+
+ list_for_each_entry(c, &head->vm_list, vm_list) {
+ if (c->vm_start == addr)
+ goto out;
+ }
+ c = NULL;
+out:
+ return c;
+}
+
+/* FIXME: attrs is not used. */
+static void *nds32_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t * handle, gfp_t gfp,
+ unsigned long attrs)
+{
+ struct page *page;
+ struct arch_vm_region *c;
+ unsigned long order;
+ u64 mask = ~0ULL, limit;
+ pgprot_t prot = pgprot_noncached(PAGE_KERNEL);
+
+ if (!consistent_pte) {
+ pr_err("%s: not initialized\n", __func__);
+ dump_stack();
+ return NULL;
+ }
+
+ if (dev) {
+ mask = dev->coherent_dma_mask;
+
+ /*
+ * Sanity check the DMA mask - it must be non-zero, and
+ * must be able to be satisfied by a DMA allocation.
+ */
+ if (mask == 0) {
+ dev_warn(dev, "coherent DMA mask is unset\n");
+ goto no_page;
+ }
+
+ }
+
+ /*
+ * Sanity check the allocation size.
+ */
+ size = PAGE_ALIGN(size);
+ limit = (mask + 1) & ~mask;
+ if ((limit && size >= limit) ||
+ size >= (CONSISTENT_END - CONSISTENT_BASE)) {
+ pr_warn("coherent allocation too big "
+ "(requested %#x mask %#llx)\n", size, mask);
+ goto no_page;
+ }
+
+ order = get_order(size);
+
+ if (mask != 0xffffffff)
+ gfp |= GFP_DMA;
+
+ page = alloc_pages(gfp, order);
+ if (!page)
+ goto no_page;
+
+ /*
+ * Invalidate any data that might be lurking in the
+ * kernel direct-mapped region for device DMA.
+ */
+ {
+ unsigned long kaddr = (unsigned long)page_address(page);
+ memset(page_address(page), 0, size);
+ cpu_dma_wbinval_range(kaddr, kaddr + size);
+ }
+
+ /*
+ * Allocate a virtual address in the consistent mapping region.
+ */
+ c = vm_region_alloc(&consistent_head, size,
+ gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
+ if (c) {
+ pte_t *pte = consistent_pte + CONSISTENT_OFFSET(c->vm_start);
+ struct page *end = page + (1 << order);
+
+ c->vm_pages = page;
+
+ /*
+ * Set the "dma handle"
+ */
+ *handle = page_to_phys(page);
+
+ do {
+ BUG_ON(!pte_none(*pte));
+
+ /*
+ * x86 does not mark the pages reserved...
+ */
+ SetPageReserved(page);
+ set_pte(pte, mk_pte(page, prot));
+ page++;
+ pte++;
+ } while (size -= PAGE_SIZE);
+
+ /*
+ * Free the otherwise unused pages.
+ */
+ while (page < end) {
+ __free_page(page);
+ page++;
+ }
+
+ return (void *)c->vm_start;
+ }
+
+ if (page)
+ __free_pages(page, order);
+no_page:
+ *handle = ~0;
+ return NULL;
+}
+
+static void nds32_dma_free(struct device *dev, size_t size, void *cpu_addr,
+ dma_addr_t handle, unsigned long attrs)
+{
+ struct arch_vm_region *c;
+ unsigned long flags, addr;
+ pte_t *ptep;
+
+ size = PAGE_ALIGN(size);
+
+ raw_spin_lock_irqsave(&consistent_lock, flags);
+
+ c = vm_region_find(&consistent_head, (unsigned long)cpu_addr);
+ if (!c)
+ goto no_area;
+
+ if ((c->vm_end - c->vm_start) != size) {
+ pr_err("%s: freeing wrong coherent size (%ld != %d)\n",
+ __func__, c->vm_end - c->vm_start, size);
+ dump_stack();
+ size = c->vm_end - c->vm_start;
+ }
+
+ ptep = consistent_pte + CONSISTENT_OFFSET(c->vm_start);
+ addr = c->vm_start;
+ do {
+ pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
+ unsigned long pfn;
+
+ ptep++;
+ addr += PAGE_SIZE;
+
+ if (!pte_none(pte) && pte_present(pte)) {
+ pfn = pte_pfn(pte);
+
+ if (pfn_valid(pfn)) {
+ struct page *page = pfn_to_page(pfn);
+
+ /*
+ * x86 does not mark the pages reserved...
+ */
+ ClearPageReserved(page);
+
+ __free_page(page);
+ continue;
+ }
+ }
+
+ pr_crit("%s: bad page in kernel page table\n", __func__);
+ } while (size -= PAGE_SIZE);
+
+ flush_tlb_kernel_range(c->vm_start, c->vm_end);
+
+ list_del(&c->vm_list);
+
+ raw_spin_unlock_irqrestore(&consistent_lock, flags);
+
+ kfree(c);
+ return;
+
+no_area:
+ raw_spin_unlock_irqrestore(&consistent_lock, flags);
+ pr_err("%s: trying to free invalid coherent area: %p\n",
+ __func__, cpu_addr);
+ dump_stack();
+}
+
+/*
+ * Initialise the consistent memory allocation.
+ */
+static int __init consistent_init(void)
+{
+ pgd_t *pgd;
+ pmd_t *pmd;
+ pte_t *pte;
+ int ret = 0;
+
+ do {
+ pgd = pgd_offset(&init_mm, CONSISTENT_BASE);
+ pmd = pmd_alloc(&init_mm, pgd, CONSISTENT_BASE);
+ if (!pmd) {
+ pr_err("%s: no pmd tables\n", __func__);
+ ret = -ENOMEM;
+ break;
+ }
+ /* The first level mapping may be created in somewhere.
+ * It's not necessary to warn here. */
+ /* WARN_ON(!pmd_none(*pmd)); */
+
+ pte = pte_alloc_kernel(pmd, CONSISTENT_BASE);
+ if (!pte) {
+ ret = -ENOMEM;
+ break;
+ }
+
+ consistent_pte = pte;
+ } while (0);
+
+ return ret;
+}
+
+core_initcall(consistent_init);
+static void consistent_sync(void *vaddr, size_t size, int direction, int master_type);
+static dma_addr_t nds32_dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+ consistent_sync((void *)(page_address(page) + offset), size, dir, FOR_DEVICE);
+ return page_to_phys(page) + offset;
+}
+
+static void nds32_dma_unmap_page(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+ consistent_sync(phys_to_virt(handle), size, dir, FOR_CPU);
+}
+
+/*
+ * Make an area consistent for devices.
+ */
+static void consistent_sync(void *vaddr, size_t size, int direction, int master_type)
+{
+ unsigned long start = (unsigned long)vaddr;
+ unsigned long end = start + size;
+
+ if (master_type == FOR_CPU) {
+ switch (direction) {
+ case DMA_TO_DEVICE:
+ break;
+ case DMA_FROM_DEVICE:
+ case DMA_BIDIRECTIONAL:
+ cpu_dma_inval_range(start, end);
+ break;
+ default:
+ BUG();
+ }
+ } else {
+ /* FOR_DEVICE */
+ switch (direction) {
+ case DMA_FROM_DEVICE:
+ break;
+ case DMA_TO_DEVICE:
+ case DMA_BIDIRECTIONAL:
+ cpu_dma_wb_range(start, end);
+ break;
+ default:
+ BUG();
+ }
+ }
+}
+
+static int nds32_dma_map_sg(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+ int i;
+
+ for (i = 0; i < nents; i++, sg++) {
+ void *virt;
+ unsigned long pfn;
+ struct page *page = sg_page(sg);
+
+ sg->dma_address = sg_phys(sg);
+ pfn = page_to_pfn(page) + sg->offset / PAGE_SIZE;
+ page = pfn_to_page(pfn);
+ if (PageHighMem(page)) {
+ virt = kmap_atomic(page);
+ consistent_sync(virt, sg->length, dir, FOR_CPU);
+ kunmap_atomic(virt);
+ } else {
+ if (sg->offset > PAGE_SIZE)
+ panic("sg->offset:%08x > PAGE_SIZE\n",
+ sg->offset);
+ virt = page_address(page) + sg->offset;
+ consistent_sync(virt, sg->length, dir, FOR_CPU);
+ }
+ }
+ return nents;
+}
+
+static void nds32_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+ int nhwentries, enum dma_data_direction dir,
+ unsigned long attrs)
+{
+}
+
+static void
+nds32_dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir)
+{
+ consistent_sync((void *)phys_to_virt(handle), size, dir, FOR_CPU);
+}
+
+static void
+nds32_dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
+ size_t size, enum dma_data_direction dir)
+{
+ consistent_sync((void *)phys_to_virt(handle), size, dir, FOR_DEVICE);
+}
+
+static void
+nds32_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
+ enum dma_data_direction dir)
+{
+ int i;
+
+ for (i = 0; i < nents; i++, sg++) {
+ char *virt =
+ page_address((struct page *)sg->page_link) + sg->offset;
+ consistent_sync(virt, sg->length, dir, FOR_CPU);
+ }
+}
+
+static void
+nds32_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+ int nents, enum dma_data_direction dir)
+{
+ int i;
+
+ for (i = 0; i < nents; i++, sg++) {
+ char *virt =
+ page_address((struct page *)sg->page_link) + sg->offset;
+ consistent_sync(virt, sg->length, dir, FOR_DEVICE);
+ }
+}
+
+struct dma_map_ops nds32_dma_ops = {
+ .alloc = nds32_dma_alloc_coherent,
+ .free = nds32_dma_free,
+ .map_page = nds32_dma_map_page,
+ .unmap_page = nds32_dma_unmap_page,
+ .map_sg = nds32_dma_map_sg,
+ .unmap_sg = nds32_dma_unmap_sg,
+ .sync_single_for_device = nds32_dma_sync_single_for_device,
+ .sync_single_for_cpu = nds32_dma_sync_single_for_cpu,
+ .sync_sg_for_cpu = nds32_dma_sync_sg_for_cpu,
+ .sync_sg_for_device = nds32_dma_sync_sg_for_device,
+};
+
+EXPORT_SYMBOL(nds32_dma_ops);
diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S
new file mode 100644
index 000000000000..a72e83d804f5
--- /dev/null
+++ b/arch/nds32/kernel/ex-entry.S
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/memory.h>
+#include <asm/nds32.h>
+#include <asm/errno.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+
+#ifdef CONFIG_HWZOL
+ .macro push_zol
+ mfusr $r14, $LB
+ mfusr $r15, $LE
+ mfusr $r16, $LC
+ .endm
+#endif
+
+ .macro save_user_regs
+
+ smw.adm $sp, [$sp], $sp, #0x1
+ /* move $SP to the bottom of pt_regs */
+ addi $sp, $sp, -OSP_OFFSET
+
+ /* push $r0 ~ $r25 */
+ smw.bim $r0, [$sp], $r25
+ /* push $fp, $gp, $lp */
+ smw.bim $sp, [$sp], $sp, #0xe
+
+ mfsr $r12, $SP_USR
+ mfsr $r13, $IPC
+#ifdef CONFIG_HWZOL
+ push_zol
+#endif
+ movi $r17, -1
+ move $r18, $r0
+ mfsr $r19, $PSW
+ mfsr $r20, $IPSW
+ mfsr $r21, $P_IPSW
+ mfsr $r22, $P_IPC
+ mfsr $r23, $P_P0
+ mfsr $r24, $P_P1
+ smw.bim $r12, [$sp], $r24, #0
+ addi $sp, $sp, -FUCOP_CTL_OFFSET
+
+ /* Initialize kernel space $fp */
+ andi $p0, $r20, #PSW_mskPOM
+ movi $p1, #0x0
+ cmovz $fp, $p1, $p0
+
+ andi $r16, $r19, #PSW_mskINTL
+ slti $r17, $r16, #4
+ bnez $r17, 1f
+ addi $r17, $r19, #-2
+ mtsr $r17, $PSW
+ isb
+1:
+ /* If it was superuser mode, we don't need to update $r25 */
+ bnez $p0, 2f
+ la $p0, __entry_task
+ lw $r25, [$p0]
+2:
+ .endm
+
+ .text
+
+/*
+ * Exception Vector
+ */
+exception_handlers:
+ .long unhandled_exceptions !Reset/NMI
+ .long unhandled_exceptions !TLB fill
+ .long do_page_fault !PTE not present
+ .long do_dispatch_tlb_misc !TLB misc
+ .long unhandled_exceptions !TLB VLPT
+ .long unhandled_exceptions !Machine Error
+ .long do_debug_trap !Debug related
+ .long do_dispatch_general !General exception
+ .long eh_syscall !Syscall
+ .long asm_do_IRQ !IRQ
+
+common_exception_handler:
+ save_user_regs
+ mfsr $p0, $ITYPE
+ andi $p0, $p0, #ITYPE_mskVECTOR
+ srli $p0, $p0, #ITYPE_offVECTOR
+ andi $p1, $p0, #NDS32_VECTOR_mskNONEXCEPTION
+ bnez $p1, 1f
+ sethi $lp, hi20(ret_from_exception)
+ ori $lp, $lp, lo12(ret_from_exception)
+ sethi $p1, hi20(exception_handlers)
+ ori $p1, $p1, lo12(exception_handlers)
+ lw $p1, [$p1+$p0<<2]
+ move $r0, $p0
+ mfsr $r1, $EVA
+ mfsr $r2, $ITYPE
+ move $r3, $sp
+ mfsr $r4, $OIPC
+ /* enable gie if it is enabled in IPSW. */
+ mfsr $r21, $PSW
+ andi $r20, $r20, #PSW_mskGIE /* r20 is $IPSW*/
+ or $r21, $r21, $r20
+ mtsr $r21, $PSW
+ dsb
+ jr $p1
+
+ /* syscall */
+1:
+ addi $p1, $p0, #-NDS32_VECTOR_offEXCEPTION
+ bnez $p1, 2f
+ sethi $lp, hi20(ret_from_exception)
+ ori $lp, $lp, lo12(ret_from_exception)
+ sethi $p1, hi20(exception_handlers)
+ ori $p1, $p1, lo12(exception_handlers)
+ lwi $p1, [$p1+#NDS32_VECTOR_offEXCEPTION<<2]
+ jr $p1
+
+ /* interrupt */
+2:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ jal arch_trace_hardirqs_off
+#endif
+ move $r0, $sp
+ sethi $lp, hi20(ret_from_intr)
+ ori $lp, $lp, lo12(ret_from_intr)
+ sethi $p0, hi20(exception_handlers)
+ ori $p0, $p0, lo12(exception_handlers)
+ lwi $p0, [$p0+#NDS32_VECTOR_offINTERRUPT<<2]
+ jr $p0
+
+ .macro EXCEPTION_VECTOR_DEBUG
+ .align 4
+ mfsr $p0, $EDM_CTL
+ andi $p0, $p0, EDM_CTL_mskV3_EDM_MODE
+ tnez $p0, SWID_RAISE_INTERRUPT_LEVEL
+ .endm
+
+ .macro EXCEPTION_VECTOR
+ .align 4
+ sethi $p0, hi20(common_exception_handler)
+ ori $p0, $p0, lo12(common_exception_handler)
+ jral.ton $p0, $p0
+ .endm
+
+ .section ".text.init", #alloc, #execinstr
+ .global exception_vector
+exception_vector:
+.rept 6
+ EXCEPTION_VECTOR
+.endr
+ EXCEPTION_VECTOR_DEBUG
+.rept 121
+ EXCEPTION_VECTOR
+.endr
+ .align 4
+ .global exception_vector_end
+exception_vector_end:
diff --git a/arch/nds32/kernel/ex-exit.S b/arch/nds32/kernel/ex-exit.S
new file mode 100644
index 000000000000..03e4f7788a18
--- /dev/null
+++ b/arch/nds32/kernel/ex-exit.S
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+#include <asm/assembler.h>
+#include <asm/nds32.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/current.h>
+
+
+
+#ifdef CONFIG_HWZOL
+ .macro pop_zol
+ mtusr $r14, $LB
+ mtusr $r15, $LE
+ mtusr $r16, $LC
+ .endm
+#endif
+
+ .macro restore_user_regs_first
+ setgie.d
+ isb
+
+ addi $sp, $sp, FUCOP_CTL_OFFSET
+
+ lmw.adm $r12, [$sp], $r24, #0x0
+ mtsr $r12, $SP_USR
+ mtsr $r13, $IPC
+#ifdef CONFIG_HWZOL
+ pop_zol
+#endif
+ mtsr $r19, $PSW
+ mtsr $r20, $IPSW
+ mtsr $r21, $P_IPSW
+ mtsr $r22, $P_IPC
+ mtsr $r23, $P_P0
+ mtsr $r24, $P_P1
+ lmw.adm $sp, [$sp], $sp, #0xe
+ .endm
+
+ .macro restore_user_regs_last
+ pop $p0
+ cmovn $sp, $p0, $p0
+
+ iret
+ nop
+
+ .endm
+
+ .macro restore_user_regs
+ restore_user_regs_first
+ lmw.adm $r0, [$sp], $r25, #0x0
+ addi $sp, $sp, OSP_OFFSET
+ restore_user_regs_last
+ .endm
+
+ .macro fast_restore_user_regs
+ restore_user_regs_first
+ lmw.adm $r1, [$sp], $r25, #0x0
+ addi $sp, $sp, OSP_OFFSET-4
+ restore_user_regs_last
+ .endm
+
+#ifdef CONFIG_PREEMPT
+ .macro preempt_stop
+ .endm
+#else
+ .macro preempt_stop
+ setgie.d
+ isb
+ .endm
+#define resume_kernel no_work_pending
+#endif
+
+ENTRY(ret_from_exception)
+ preempt_stop
+ENTRY(ret_from_intr)
+
+/*
+ * judge Kernel or user mode
+ *
+ */
+ lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
+ andi $p0, $p0, #PSW_mskINTL
+ bnez $p0, resume_kernel ! done with iret
+ j resume_userspace
+
+
+/*
+ * This is the fast syscall return path. We do as little as
+ * possible here, and this includes saving $r0 back into the SVC
+ * stack.
+ * fixed: tsk - $r25, syscall # - $r7, syscall table pointer - $r8
+ */
+ENTRY(ret_fast_syscall)
+ gie_disable
+ lwi $r1, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $r1, #_TIF_WORK_MASK
+ bnez $p1, fast_work_pending
+ fast_restore_user_regs ! iret
+
+/*
+ * Ok, we need to do extra processing,
+ * enter the slow path returning from syscall, while pending work.
+ */
+fast_work_pending:
+ swi $r0, [$sp+(#R0_OFFSET)] ! what is different from ret_from_exception
+work_pending:
+ andi $p1, $r1, #_TIF_NEED_RESCHED
+ bnez $p1, work_resched
+
+ andi $p1, $r1, #_TIF_SIGPENDING|#_TIF_NOTIFY_RESUME
+ beqz $p1, no_work_pending
+
+ move $r0, $sp ! 'regs'
+ gie_enable
+ bal do_notify_resume
+ b ret_slow_syscall
+work_resched:
+ bal schedule ! path, return to user mode
+
+/*
+ * "slow" syscall return path.
+ */
+ENTRY(resume_userspace)
+ENTRY(ret_slow_syscall)
+ gie_disable
+ lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt
+ andi $p0, $p0, #PSW_mskINTL
+ bnez $p0, no_work_pending ! done with iret
+ lwi $r1, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $r1, #_TIF_WORK_MASK
+ bnez $p1, work_pending ! handle work_resched, sig_pend
+
+no_work_pending:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ lwi $p0, [$sp+(#IPSW_OFFSET)]
+ andi $p0, $p0, #0x1
+ la $r10, trace_hardirqs_off
+ la $r9, trace_hardirqs_on
+ cmovz $r9, $p0, $r10
+ jral $r9
+#endif
+ restore_user_regs ! return from iret
+
+
+/*
+ * preemptive kernel
+ */
+#ifdef CONFIG_PREEMPT
+resume_kernel:
+ gie_disable
+ lwi $t0, [tsk+#TSK_TI_PREEMPT]
+ bnez $t0, no_work_pending
+need_resched:
+ lwi $t0, [tsk+#TSK_TI_FLAGS]
+ andi $p1, $t0, #_TIF_NEED_RESCHED
+ beqz $p1, no_work_pending
+
+ lwi $t0, [$sp+(#IPSW_OFFSET)] ! Interrupts off?
+ andi $t0, $t0, #1
+ beqz $t0, no_work_pending
+
+ jal preempt_schedule_irq
+ b need_resched
+#endif
+
+/*
+ * This is how we return from a fork.
+ */
+ENTRY(ret_from_fork)
+ bal schedule_tail
+ beqz $r6, 1f ! r6 stores fn for kernel thread
+ move $r0, $r7 ! prepare kernel thread arg
+ jral $r6
+1:
+ lwi $r1, [tsk+#TSK_TI_FLAGS] ! check for syscall tracing
+ andi $p1, $r1, #_TIF_WORK_SYSCALL_LEAVE ! are we tracing syscalls?
+ beqz $p1, ret_slow_syscall
+ move $r0, $sp
+ bal syscall_trace_leave
+ b ret_slow_syscall
diff --git a/arch/nds32/kernel/ex-scall.S b/arch/nds32/kernel/ex-scall.S
new file mode 100644
index 000000000000..36aa87ecdabd
--- /dev/null
+++ b/arch/nds32/kernel/ex-scall.S
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+#include <asm/assembler.h>
+#include <asm/nds32.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/current.h>
+
+/*
+ * $r0 = previous task_struct,
+ * $r1 = next task_struct,
+ * previous and next are guaranteed not to be the same.
+ */
+
+ENTRY(__switch_to)
+
+ la $p0, __entry_task
+ sw $r1, [$p0]
+ move $p1, $r0
+ addi $p1, $p1, #THREAD_CPU_CONTEXT
+ smw.bi $r6, [$p1], $r14, #0xb ! push r6~r14, fp, lp, sp
+ move $r25, $r1
+ addi $r1, $r1, #THREAD_CPU_CONTEXT
+ lmw.bi $r6, [$r1], $r14, #0xb ! pop r6~r14, fp, lp, sp
+ ret
+
+
+#define tbl $r8
+
+/*
+ * $r7 will be writen as syscall nr
+ */
+ .macro get_scno
+ lwi $r7, [$sp + R15_OFFSET]
+ swi $r7, [$sp + SYSCALLNO_OFFSET]
+ .endm
+
+ .macro updateipc
+ addi $r17, $r13, #4 ! $r13 is $IPC
+ swi $r17, [$sp + IPC_OFFSET]
+ .endm
+
+ENTRY(eh_syscall)
+ updateipc
+
+ get_scno
+ gie_enable
+
+ lwi $p0, [tsk+#TSK_TI_FLAGS] ! check for syscall tracing
+
+ andi $p1, $p0, #_TIF_WORK_SYSCALL_ENTRY ! are we tracing syscalls?
+ bnez $p1, __sys_trace
+
+ la $lp, ret_fast_syscall ! return address
+jmp_systbl:
+ addi $p1, $r7, #-__NR_syscalls ! syscall number of syscall instruction is guarded by addembler
+ bgez $p1, _SCNO_EXCEED ! call sys_* routine
+ la tbl, sys_call_table ! load syscall table pointer
+ slli $p1, $r7, #2
+ add $p1, tbl, $p1
+ lwi $p1, [$p1]
+ jr $p1 ! no return
+
+_SCNO_EXCEED:
+ ori $r0, $r7, #0
+ ori $r1, $sp, #0
+ b bad_syscall
+
+/*
+ * This is the really slow path. We're going to be doing
+ * context switches, and waiting for our parent to respond.
+ */
+__sys_trace:
+ move $r0, $sp
+ bal syscall_trace_enter
+ move $r7, $r0
+ la $lp, __sys_trace_return ! return address
+
+ addi $p1, $r7, #1
+ beqz $p1, ret_slow_syscall ! fatal signal is pending
+
+ addi $p1, $sp, #R0_OFFSET ! pointer to regs
+ lmw.bi $r0, [$p1], $r5 ! have to reload $r0 - $r5
+ b jmp_systbl
+
+__sys_trace_return:
+ swi $r0, [$sp+#R0_OFFSET] ! T: save returned $r0
+ move $r0, $sp ! set pt_regs for syscall_trace_leave
+ bal syscall_trace_leave
+ b ret_slow_syscall
+
+ENTRY(sys_rt_sigreturn_wrapper)
+ addi $r0, $sp, #0
+ b sys_rt_sigreturn
+ENDPROC(sys_rt_sigreturn_wrapper)
diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S
new file mode 100644
index 000000000000..71f57bd70f3b
--- /dev/null
+++ b/arch/nds32/kernel/head.S
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/sizes.h>
+#include <asm/thread_info.h>
+
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0
+#endif
+
+ .globl swapper_pg_dir
+ .equ swapper_pg_dir, TEXTADDR - 0x4000
+
+/*
+ * Kernel startup entry point.
+ */
+ .section ".head.text", "ax"
+ .type _stext, %function
+ENTRY(_stext)
+ setgie.d ! Disable interrupt
+ isb
+/*
+ * Disable I/D-cache and enable it at a proper time
+ */
+ mfsr $r0, $mr8
+ li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
+ and $r0, $r0, $r1
+ mtsr $r0, $mr8
+
+/*
+ * Process device tree blob
+ */
+ andi $r0,$r2,#0x3
+ li $r10, 0
+ bne $r0, $r10, _nodtb
+ lwi $r0, [$r2]
+ li $r1, OF_DT_MAGIC
+ bne $r0, $r1, _nodtb
+ move $r10, $r2
+_nodtb:
+
+/*
+ * Create a temporary mapping area for booting, before start_kernel
+ */
+ sethi $r4, hi20(swapper_pg_dir)
+ li $p0, (PAGE_OFFSET - PHYS_OFFSET)
+ sub $r4, $r4, $p0
+ tlbop FlushAll ! invalidate TLB\n"
+ isb
+ mtsr $r4, $L1_PPTB ! load page table pointer\n"
+
+/* set NTC0 cacheable/writeback, mutliple page size in use */
+ mfsr $r3, $MMU_CTL
+ li $r0, #~MMU_CTL_mskNTC0
+ and $r3, $r3, $r0
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+ ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0))
+#else
+ ori $r3, $r3, #(MMU_CTL_mskMPZIU|(MMU_CTL_CACHEABLE_WB << MMU_CTL_offNTC0)|MMU_CTL_D8KB)
+#endif
+#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
+ li $r0, #MMU_CTL_UNA
+ or $r3, $r3, $r0
+#endif
+ mtsr $r3, $MMU_CTL
+ isb
+
+/* set page size and size of kernel image */
+ mfsr $r0, $MMU_CFG
+ srli $r3, $r0, MMU_CFG_offfEPSZ
+ zeb $r3, $r3
+ bnez $r3, _extra_page_size_support
+#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
+ li $r5, #SZ_4K ! Use 4KB page size
+#else
+ li $r5, #SZ_8K ! Use 8KB page size
+ li $r3, #1
+#endif
+ mtsr $r3, $TLB_MISC
+ b _image_size_check
+
+_extra_page_size_support: ! Use epzs pages size
+ clz $r6, $r3
+ subri $r2, $r6, #31
+ li $r3, #1
+ sll $r3, $r3, $r2
+ /* MMU_CFG.EPSZ value -> meaning */
+ mul $r5, $r3, $r3
+ slli $r5, $r5, #14
+ /* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */
+ addi $r3, $r2, #0x2
+ mtsr $r3, $TLB_MISC
+
+_image_size_check:
+ /* calculate the image maximum size accepted by TLB config */
+ andi $r6, $r0, MMU_CFG_mskTBW
+ andi $r0, $r0, MMU_CFG_mskTBS
+ srli $r6, $r6, MMU_CFG_offTBW
+ srli $r0, $r0, MMU_CFG_offTBS
+ /*
+ * we just map the kernel to the maximum way - 1 of tlb
+ * reserver one way for UART VA mapping
+ * it will cause page fault if UART mapping cover the kernel mapping
+ *
+ * direct mapping is not supported now.
+ */
+ li $r2, 't'
+ beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin
+ addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning
+ sll $r0, $r6, $r0 ! entries = k-way * n-set
+ mul $r6, $r0, $r5 ! max size = entries * page size
+ /* check kernel image size */
+ la $r3, (_end - PAGE_OFFSET)
+ li $r2, 's'
+ bgt $r3, $r6, __error
+
+ li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
+ li $r3, PAGE_OFFSET
+ add $r6, $r6, $r3
+
+_tlb:
+ mtsr $r3, $TLB_VPN
+ dsb
+ tlbop $r2, RWR
+ isb
+ add $r3, $r3, $r5
+ add $r2, $r2, $r5
+ bgt $r6, $r3, _tlb
+ mfsr $r3, $TLB_MISC ! setup access page size
+ li $r2, #~0xf
+ and $r3, $r3, $r2
+#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
+ ori $r3, $r3, #0x1
+#endif
+ mtsr $r3, $TLB_MISC
+
+ mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
+ ori $r0, $r0, #MISC_init
+ mtsr $r0, $MISC_CTL
+
+ mfsr $p1, $PSW
+ li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE
+ and $p1, $p1, $r15
+ ori $p1, $p1, #PSW_init
+ mtsr $p1, $IPSW ! when iret, it will automatically enable MMU
+ la $lp, __mmap_switched
+ mtsr $lp, $IPC
+ iret
+ nop
+
+ .type __switch_data, %object
+__switch_data:
+ .long __bss_start ! $r6
+ .long _end ! $r7
+ .long __atags_pointer ! $atag_pointer
+ .long init_task ! $r9, move to $r25
+ .long init_thread_union + THREAD_SIZE ! $sp
+
+
+/*
+ * The following fragment of code is executed with the MMU on in MMU mode,
+ * and uses absolute addresses; this is not position independent.
+ */
+ .align
+ .type __mmap_switched, %function
+__mmap_switched:
+ la $r3, __switch_data
+ lmw.bim $r6, [$r3], $r9, #0b0001
+ move $r25, $r9
+ move $fp, #0 ! Clear BSS (and zero $fp)
+ beq $r7, $r6, _RRT
+1: swi.bi $fp, [$r6], #4
+ bne $r7, $r6, 1b
+ swi $r10, [$r8]
+
+_RRT:
+ b start_kernel
+
+__error:
+ b __error
diff --git a/arch/nds32/kernel/irq.c b/arch/nds32/kernel/irq.c
new file mode 100644
index 000000000000..6ff5a672be27
--- /dev/null
+++ b/arch/nds32/kernel/irq.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/irqchip.h>
+
+void __init init_IRQ(void)
+{
+ irqchip_init();
+}
diff --git a/arch/nds32/kernel/module.c b/arch/nds32/kernel/module.c
new file mode 100644
index 000000000000..4167283d8293
--- /dev/null
+++ b/arch/nds32/kernel/module.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/module.h>
+#include <linux/elf.h>
+#include <linux/vmalloc.h>
+#include <linux/moduleloader.h>
+#include <asm/pgtable.h>
+
+void *module_alloc(unsigned long size)
+{
+ return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END,
+ GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,
+ __builtin_return_address(0));
+}
+
+void module_free(struct module *module, void *region)
+{
+ vfree(region);
+}
+
+int module_frob_arch_sections(Elf_Ehdr * hdr,
+ Elf_Shdr * sechdrs,
+ char *secstrings, struct module *mod)
+{
+ return 0;
+}
+
+void do_reloc16(unsigned int val, unsigned int *loc, unsigned int val_mask,
+ unsigned int val_shift, unsigned int loc_mask,
+ unsigned int partial_in_place, unsigned int swap)
+{
+ unsigned int tmp = 0, tmp2 = 0;
+
+ __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n"
+ "\tbeqz\t%3, 1f\n"
+ "\twsbh\t%0, %1\n"
+ "1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+ );
+
+ tmp2 = tmp & loc_mask;
+ if (partial_in_place) {
+ tmp &= (!loc_mask);
+ tmp =
+ tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+ } else {
+ tmp = tmp2 | ((val & val_mask) >> val_shift);
+ }
+
+ __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+ "\twsbh\t%0, %1\n"
+ "2:\n"
+ "\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp),
+ "r"(loc), "r"(swap)
+ );
+}
+
+void do_reloc32(unsigned int val, unsigned int *loc, unsigned int val_mask,
+ unsigned int val_shift, unsigned int loc_mask,
+ unsigned int partial_in_place, unsigned int swap)
+{
+ unsigned int tmp = 0, tmp2 = 0;
+
+ __asm__ __volatile__("\tlmw.bi\t%0, [%2], %0, 0\n"
+ "\tbeqz\t%3, 1f\n"
+ "\twsbh\t%0, %1\n"
+ "\trotri\t%0, %1, 16\n"
+ "1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap)
+ );
+
+ tmp2 = tmp & loc_mask;
+ if (partial_in_place) {
+ tmp &= (!loc_mask);
+ tmp =
+ tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask);
+ } else {
+ tmp = tmp2 | ((val & val_mask) >> val_shift);
+ }
+
+ __asm__ __volatile__("\tbeqz\t%3, 2f\n"
+ "\twsbh\t%0, %1\n"
+ "\trotri\t%0, %1, 16\n"
+ "2:\n"
+ "\tsmw.bi\t%0, [%2], %0, 0\n":"=r"(tmp):"0"(tmp),
+ "r"(loc), "r"(swap)
+ );
+}
+
+static inline int exceed_limit(int offset, unsigned int val_mask,
+ struct module *module, Elf32_Rela * rel,
+ unsigned int relindex, unsigned int reloc_order)
+{
+ int abs_off = offset < 0 ? ~offset : offset;
+
+ if (abs_off & (~val_mask)) {
+ pr_err("\n%s: relocation type %d out of range.\n"
+ "please rebuild the kernel module with gcc option \"-Wa,-mno-small-text\".\n",
+ module->name, ELF32_R_TYPE(rel->r_info));
+ pr_err("section %d reloc %d offset 0x%x relative 0x%x.\n",
+ relindex, reloc_order, rel->r_offset, offset);
+ return true;
+ }
+ return false;
+}
+
+#ifdef __NDS32_EL__
+#define NEED_SWAP 1
+#else
+#define NEED_SWAP 0
+#endif
+
+int
+apply_relocate_add(Elf32_Shdr * sechdrs, const char *strtab,
+ unsigned int symindex, unsigned int relindex,
+ struct module *module)
+{
+ Elf32_Shdr *symsec = sechdrs + symindex;
+ Elf32_Shdr *relsec = sechdrs + relindex;
+ Elf32_Shdr *dstsec = sechdrs + relsec->sh_info;
+ Elf32_Rela *rel = (void *)relsec->sh_addr;
+ unsigned int i;
+
+ for (i = 0; i < relsec->sh_size / sizeof(Elf32_Rela); i++, rel++) {
+ Elf32_Addr *loc;
+ Elf32_Sym *sym;
+ Elf32_Addr v;
+ s32 offset;
+
+ offset = ELF32_R_SYM(rel->r_info);
+ if (offset < 0
+ || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
+ pr_err("%s: bad relocation\n", module->name);
+ pr_err("section %d reloc %d\n", relindex, i);
+ return -ENOEXEC;
+ }
+
+ sym = ((Elf32_Sym *) symsec->sh_addr) + offset;
+
+ if (rel->r_offset < 0
+ || rel->r_offset > dstsec->sh_size - sizeof(u16)) {
+ pr_err("%s: out of bounds relocation\n", module->name);
+ pr_err("section %d reloc %d offset 0x%0x size %d\n",
+ relindex, i, rel->r_offset, dstsec->sh_size);
+ return -ENOEXEC;
+ }
+
+ loc = (Elf32_Addr *) (dstsec->sh_addr + rel->r_offset);
+ v = sym->st_value + rel->r_addend;
+
+ switch (ELF32_R_TYPE(rel->r_info)) {
+ case R_NDS32_NONE:
+ case R_NDS32_INSN16:
+ case R_NDS32_LABEL:
+ case R_NDS32_LONGCALL1:
+ case R_NDS32_LONGCALL2:
+ case R_NDS32_LONGCALL3:
+ case R_NDS32_LONGCALL4:
+ case R_NDS32_LONGJUMP1:
+ case R_NDS32_LONGJUMP2:
+ case R_NDS32_LONGJUMP3:
+ case R_NDS32_9_FIXED_RELA:
+ case R_NDS32_15_FIXED_RELA:
+ case R_NDS32_17_FIXED_RELA:
+ case R_NDS32_25_FIXED_RELA:
+ case R_NDS32_LOADSTORE:
+ case R_NDS32_DWARF2_OP1_RELA:
+ case R_NDS32_DWARF2_OP2_RELA:
+ case R_NDS32_DWARF2_LEB_RELA:
+ case R_NDS32_RELA_NOP_MIX ... R_NDS32_RELA_NOP_MAX:
+ break;
+
+ case R_NDS32_32_RELA:
+ do_reloc32(v, loc, 0xffffffff, 0, 0, 0, 0);
+ break;
+
+ case R_NDS32_HI20_RELA:
+ do_reloc32(v, loc, 0xfffff000, 12, 0xfff00000, 0,
+ NEED_SWAP);
+ break;
+
+ case R_NDS32_LO12S3_RELA:
+ do_reloc32(v, loc, 0x00000fff, 3, 0xfffff000, 0,
+ NEED_SWAP);
+ break;
+
+ case R_NDS32_LO12S2_RELA:
+ do_reloc32(v, loc, 0x00000fff, 2, 0xfffff000, 0,
+ NEED_SWAP);
+ break;
+
+ case R_NDS32_LO12S1_RELA:
+ do_reloc32(v, loc, 0x00000fff, 1, 0xfffff000, 0,
+ NEED_SWAP);
+ break;
+
+ case R_NDS32_LO12S0_RELA:
+ case R_NDS32_LO12S0_ORI_RELA:
+ do_reloc32(v, loc, 0x00000fff, 0, 0xfffff000, 0,
+ NEED_SWAP);
+ break;
+
+ case R_NDS32_9_PCREL_RELA:
+ if (exceed_limit
+ ((v - (Elf32_Addr) loc), 0x000000ff, module, rel,
+ relindex, i))
+ return -ENOEXEC;
+ do_reloc16(v - (Elf32_Addr) loc, loc, 0x000001ff, 1,
+ 0xffffff00, 0, NEED_SWAP);
+ break;
+
+ case R_NDS32_15_PCREL_RELA:
+ if (exceed_limit
+ ((v - (Elf32_Addr) loc), 0x00003fff, module, rel,
+ relindex, i))
+ return -ENOEXEC;
+ do_reloc32(v - (Elf32_Addr) loc, loc, 0x00007fff, 1,
+ 0xffffc000, 0, NEED_SWAP);
+ break;
+
+ case R_NDS32_17_PCREL_RELA:
+ if (exceed_limit
+ ((v - (Elf32_Addr) loc), 0x0000ffff, module, rel,
+ relindex, i))
+ return -ENOEXEC;
+ do_reloc32(v - (Elf32_Addr) loc, loc, 0x0001ffff, 1,
+ 0xffff0000, 0, NEED_SWAP);
+ break;
+
+ case R_NDS32_25_PCREL_RELA:
+ if (exceed_limit
+ ((v - (Elf32_Addr) loc), 0x00ffffff, module, rel,
+ relindex, i))
+ return -ENOEXEC;
+ do_reloc32(v - (Elf32_Addr) loc, loc, 0x01ffffff, 1,
+ 0xff000000, 0, NEED_SWAP);
+ break;
+ case R_NDS32_WORD_9_PCREL_RELA:
+ if (exceed_limit
+ ((v - (Elf32_Addr) loc), 0x000000ff, module, rel,
+ relindex, i))
+ return -ENOEXEC;
+ do_reloc32(v - (Elf32_Addr) loc, loc, 0x000001ff, 1,
+ 0xffffff00, 0, NEED_SWAP);
+ break;
+
+ case R_NDS32_SDA15S3_RELA:
+ case R_NDS32_SDA15S2_RELA:
+ case R_NDS32_SDA15S1_RELA:
+ case R_NDS32_SDA15S0_RELA:
+ pr_err("%s: unsupported relocation type %d.\n",
+ module->name, ELF32_R_TYPE(rel->r_info));
+ pr_err
+ ("Small data section access doesn't work in the kernel space; "
+ "please rebuild the kernel module with gcc option -mcmodel=large.\n");
+ pr_err("section %d reloc %d offset 0x%x size %d\n",
+ relindex, i, rel->r_offset, dstsec->sh_size);
+ break;
+
+ default:
+ pr_err("%s: unsupported relocation type %d.\n",
+ module->name, ELF32_R_TYPE(rel->r_info));
+ pr_err("section %d reloc %d offset 0x%x size %d\n",
+ relindex, i, rel->r_offset, dstsec->sh_size);
+ }
+ }
+ return 0;
+}
+
+int
+module_finalize(const Elf32_Ehdr * hdr, const Elf_Shdr * sechdrs,
+ struct module *module)
+{
+ return 0;
+}
+
+void module_arch_cleanup(struct module *mod)
+{
+}
diff --git a/arch/nds32/kernel/nds32_ksyms.c b/arch/nds32/kernel/nds32_ksyms.c
new file mode 100644
index 000000000000..5ecebd0e60cb
--- /dev/null
+++ b/arch/nds32/kernel/nds32_ksyms.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/in6.h>
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+
+#include <asm/checksum.h>
+#include <asm/io.h>
+#include <asm/ftrace.h>
+#include <asm/proc-fns.h>
+
+/* mem functions */
+EXPORT_SYMBOL(memset);
+EXPORT_SYMBOL(memcpy);
+EXPORT_SYMBOL(memmove);
+EXPORT_SYMBOL(memzero);
+
+/* user mem (segment) */
+EXPORT_SYMBOL(__arch_copy_from_user);
+EXPORT_SYMBOL(__arch_copy_to_user);
+EXPORT_SYMBOL(__arch_clear_user);
+
+/* cache handling */
+EXPORT_SYMBOL(cpu_icache_inval_all);
+EXPORT_SYMBOL(cpu_dcache_wbinval_all);
+EXPORT_SYMBOL(cpu_dma_inval_range);
+EXPORT_SYMBOL(cpu_dma_wb_range);
diff --git a/arch/nds32/kernel/process.c b/arch/nds32/kernel/process.c
new file mode 100644
index 000000000000..65fda986e55f
--- /dev/null
+++ b/arch/nds32/kernel/process.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/sched.h>
+#include <linux/sched/debug.h>
+#include <linux/sched/task_stack.h>
+#include <linux/delay.h>
+#include <linux/kallsyms.h>
+#include <linux/uaccess.h>
+#include <asm/elf.h>
+#include <asm/proc-fns.h>
+#include <linux/ptrace.h>
+#include <linux/reboot.h>
+
+extern void setup_mm_for_reboot(char mode);
+#ifdef CONFIG_PROC_FS
+struct proc_dir_entry *proc_dir_cpu;
+EXPORT_SYMBOL(proc_dir_cpu);
+#endif
+
+extern inline void arch_reset(char mode)
+{
+ if (mode == 's') {
+ /* Use cpu handler, jump to 0 */
+ cpu_reset(0);
+ }
+}
+
+void (*pm_power_off) (void);
+EXPORT_SYMBOL(pm_power_off);
+
+static char reboot_mode_nds32 = 'h';
+
+int __init reboot_setup(char *str)
+{
+ reboot_mode_nds32 = str[0];
+ return 1;
+}
+
+static int cpub_pwroff(void)
+{
+ return 0;
+}
+
+__setup("reboot=", reboot_setup);
+
+void machine_halt(void)
+{
+ cpub_pwroff();
+}
+
+EXPORT_SYMBOL(machine_halt);
+
+void machine_power_off(void)
+{
+ if (pm_power_off)
+ pm_power_off();
+}
+
+EXPORT_SYMBOL(machine_power_off);
+
+void machine_restart(char *cmd)
+{
+ /*
+ * Clean and disable cache, and turn off interrupts
+ */
+ cpu_proc_fin();
+
+ /*
+ * Tell the mm system that we are going to reboot -
+ * we may need it to insert some 1:1 mappings so that
+ * soft boot works.
+ */
+ setup_mm_for_reboot(reboot_mode_nds32);
+
+ /* Execute kernel restart handler call chain */
+ do_kernel_restart(cmd);
+
+ /*
+ * Now call the architecture specific reboot code.
+ */
+ arch_reset(reboot_mode_nds32);
+
+ /*
+ * Whoops - the architecture was unable to reboot.
+ * Tell the user!
+ */
+ mdelay(1000);
+ pr_info("Reboot failed -- System halted\n");
+ while (1) ;
+}
+
+EXPORT_SYMBOL(machine_restart);
+
+void show_regs(struct pt_regs *regs)
+{
+ printk("PC is at %pS\n", (void *)instruction_pointer(regs));
+ printk("LP is at %pS\n", (void *)regs->lp);
+ pr_info("pc : [<%08lx>] lp : [<%08lx>] %s\n"
+ "sp : %08lx fp : %08lx gp : %08lx\n",
+ instruction_pointer(regs),
+ regs->lp, print_tainted(), regs->sp, regs->fp, regs->gp);
+ pr_info("r25: %08lx r24: %08lx\n", regs->uregs[25], regs->uregs[24]);
+
+ pr_info("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n",
+ regs->uregs[23], regs->uregs[22],
+ regs->uregs[21], regs->uregs[20]);
+ pr_info("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n",
+ regs->uregs[19], regs->uregs[18],
+ regs->uregs[17], regs->uregs[16]);
+ pr_info("r15: %08lx r14: %08lx r13: %08lx r12: %08lx\n",
+ regs->uregs[15], regs->uregs[14],
+ regs->uregs[13], regs->uregs[12]);
+ pr_info("r11: %08lx r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->uregs[11], regs->uregs[10],
+ regs->uregs[9], regs->uregs[8]);
+ pr_info("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->uregs[7], regs->uregs[6], regs->uregs[5], regs->uregs[4]);
+ pr_info("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->uregs[3], regs->uregs[2], regs->uregs[1], regs->uregs[0]);
+ pr_info(" IRQs o%s Segment %s\n",
+ interrupts_enabled(regs) ? "n" : "ff",
+ segment_eq(get_fs(), get_ds())? "kernel" : "user");
+}
+
+EXPORT_SYMBOL(show_regs);
+
+void flush_thread(void)
+{
+}
+
+DEFINE_PER_CPU(struct task_struct *, __entry_task);
+
+asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
+int copy_thread(unsigned long clone_flags, unsigned long stack_start,
+ unsigned long stk_sz, struct task_struct *p)
+{
+ struct pt_regs *childregs = task_pt_regs(p);
+
+ memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
+
+ if (unlikely(p->flags & PF_KTHREAD)) {
+ memset(childregs, 0, sizeof(struct pt_regs));
+ /* kernel thread fn */
+ p->thread.cpu_context.r6 = stack_start;
+ /* kernel thread argument */
+ p->thread.cpu_context.r7 = stk_sz;
+ } else {
+ *childregs = *current_pt_regs();
+ if (stack_start)
+ childregs->sp = stack_start;
+ /* child get zero as ret. */
+ childregs->uregs[0] = 0;
+ childregs->osp = 0;
+ if (clone_flags & CLONE_SETTLS)
+ childregs->uregs[25] = childregs->uregs[3];
+ }
+ /* cpu context switching */
+ p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
+ p->thread.cpu_context.sp = (unsigned long)childregs;
+
+#ifdef CONFIG_HWZOL
+ childregs->lb = 0;
+ childregs->le = 0;
+ childregs->lc = 0;
+#endif
+
+ return 0;
+}
+
+/*
+ * fill in the fpe structure for a core dump...
+ */
+int dump_fpu(struct pt_regs *regs, elf_fpregset_t * fpu)
+{
+ int fpvalid = 0;
+ return fpvalid;
+}
+
+EXPORT_SYMBOL(dump_fpu);
+
+unsigned long get_wchan(struct task_struct *p)
+{
+ unsigned long fp, lr;
+ unsigned long stack_start, stack_end;
+ int count = 0;
+
+ if (!p || p == current || p->state == TASK_RUNNING)
+ return 0;
+
+ if (IS_ENABLED(CONFIG_FRAME_POINTER)) {
+ stack_start = (unsigned long)end_of_stack(p);
+ stack_end = (unsigned long)task_stack_page(p) + THREAD_SIZE;
+
+ fp = thread_saved_fp(p);
+ do {
+ if (fp < stack_start || fp > stack_end)
+ return 0;
+ lr = ((unsigned long *)fp)[0];
+ if (!in_sched_functions(lr))
+ return lr;
+ fp = *(unsigned long *)(fp + 4);
+ } while (count++ < 16);
+ }
+ return 0;
+}
+
+EXPORT_SYMBOL(get_wchan);
diff --git a/arch/nds32/kernel/ptrace.c b/arch/nds32/kernel/ptrace.c
new file mode 100644
index 000000000000..eaaf7a999b20
--- /dev/null
+++ b/arch/nds32/kernel/ptrace.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/ptrace.h>
+#include <linux/regset.h>
+#include <linux/tracehook.h>
+#include <linux/elf.h>
+#include <linux/sched/task_stack.h>
+
+enum nds32_regset {
+ REGSET_GPR,
+};
+
+static int gpr_get(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ void *kbuf, void __user * ubuf)
+{
+ struct user_pt_regs *uregs = &task_pt_regs(target)->user_regs;
+ return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, -1);
+}
+
+static int gpr_set(struct task_struct *target, const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user * ubuf)
+{
+ int err;
+ struct user_pt_regs newregs = task_pt_regs(target)->user_regs;
+
+ err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1);
+ if (err)
+ return err;
+
+ task_pt_regs(target)->user_regs = newregs;
+ return 0;
+}
+
+static const struct user_regset nds32_regsets[] = {
+ [REGSET_GPR] = {
+ .core_note_type = NT_PRSTATUS,
+ .n = sizeof(struct user_pt_regs) / sizeof(u32),
+ .size = sizeof(elf_greg_t),
+ .align = sizeof(elf_greg_t),
+ .get = gpr_get,
+ .set = gpr_set}
+};
+
+static const struct user_regset_view nds32_user_view = {
+ .name = "nds32",
+ .e_machine = EM_NDS32,
+ .regsets = nds32_regsets,
+ .n = ARRAY_SIZE(nds32_regsets)
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+ return &nds32_user_view;
+}
+
+void ptrace_disable(struct task_struct *child)
+{
+ user_disable_single_step(child);
+}
+
+/* do_ptrace()
+ *
+ * Provide ptrace defined service.
+ */
+long arch_ptrace(struct task_struct *child, long request, unsigned long addr,
+ unsigned long data)
+{
+ int ret = -EIO;
+
+ switch (request) {
+ default:
+ ret = ptrace_request(child, request, addr, data);
+ break;
+ }
+
+ return ret;
+}
+
+void user_enable_single_step(struct task_struct *child)
+{
+ struct pt_regs *regs;
+ regs = task_pt_regs(child);
+ regs->ipsw |= PSW_mskHSS;
+ set_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+
+void user_disable_single_step(struct task_struct *child)
+{
+ struct pt_regs *regs;
+ regs = task_pt_regs(child);
+ regs->ipsw &= ~PSW_mskHSS;
+ clear_tsk_thread_flag(child, TIF_SINGLESTEP);
+}
+
+/* sys_trace()
+ *
+ * syscall trace handler.
+ */
+
+asmlinkage int syscall_trace_enter(struct pt_regs *regs)
+{
+ if (test_thread_flag(TIF_SYSCALL_TRACE)) {
+ if (tracehook_report_syscall_entry(regs))
+ forget_syscall(regs);
+ }
+ return regs->syscallno;
+}
+
+asmlinkage void syscall_trace_leave(struct pt_regs *regs)
+{
+ int step = test_thread_flag(TIF_SINGLESTEP);
+ if (step || test_thread_flag(TIF_SYSCALL_TRACE))
+ tracehook_report_syscall_exit(regs, step);
+
+}
diff --git a/arch/nds32/kernel/setup.c b/arch/nds32/kernel/setup.c
new file mode 100644
index 000000000000..ba910e9e4ecb
--- /dev/null
+++ b/arch/nds32/kernel/setup.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/cpu.h>
+#include <linux/bootmem.h>
+#include <linux/seq_file.h>
+#include <linux/memblock.h>
+#include <linux/console.h>
+#include <linux/screen_info.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <asm/setup.h>
+#include <asm/sections.h>
+#include <asm/proc-fns.h>
+#include <asm/cache_info.h>
+#include <asm/elf.h>
+#include <nds32_intrinsic.h>
+
+#define HWCAP_MFUSR_PC 0x000001
+#define HWCAP_EXT 0x000002
+#define HWCAP_EXT2 0x000004
+#define HWCAP_FPU 0x000008
+#define HWCAP_AUDIO 0x000010
+#define HWCAP_BASE16 0x000020
+#define HWCAP_STRING 0x000040
+#define HWCAP_REDUCED_REGS 0x000080
+#define HWCAP_VIDEO 0x000100
+#define HWCAP_ENCRYPT 0x000200
+#define HWCAP_EDM 0x000400
+#define HWCAP_LMDMA 0x000800
+#define HWCAP_PFM 0x001000
+#define HWCAP_HSMP 0x002000
+#define HWCAP_TRACE 0x004000
+#define HWCAP_DIV 0x008000
+#define HWCAP_MAC 0x010000
+#define HWCAP_L2C 0x020000
+#define HWCAP_FPU_DP 0x040000
+#define HWCAP_V2 0x080000
+#define HWCAP_DX_REGS 0x100000
+
+unsigned long cpu_id, cpu_rev, cpu_cfgid;
+char cpu_series;
+char *endianness = NULL;
+
+unsigned int __atags_pointer __initdata;
+unsigned int elf_hwcap;
+EXPORT_SYMBOL(elf_hwcap);
+
+/*
+ * The following string table, must sync with HWCAP_xx bitmask,
+ * which is defined in <asm/procinfo.h>
+ */
+static const char *hwcap_str[] = {
+ "mfusr_pc",
+ "perf1",
+ "perf2",
+ "fpu",
+ "audio",
+ "16b",
+ "string",
+ "reduced_regs",
+ "video",
+ "encrypt",
+ "edm",
+ "lmdma",
+ "pfm",
+ "hsmp",
+ "trace",
+ "div",
+ "mac",
+ "l2c",
+ "dx_regs",
+ "v2",
+ NULL,
+};
+
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define WRITE_METHOD "write through"
+#else
+#define WRITE_METHOD "write back"
+#endif
+
+struct cache_info L1_cache_info[2];
+static void __init dump_cpu_info(int cpu)
+{
+ int i, p = 0;
+ char str[sizeof(hwcap_str) + 16];
+
+ for (i = 0; hwcap_str[i]; i++) {
+ if (elf_hwcap & (1 << i)) {
+ sprintf(str + p, "%s ", hwcap_str[i]);
+ p += strlen(hwcap_str[i]) + 1;
+ }
+ }
+
+ pr_info("CPU%d Features: %s\n", cpu, str);
+
+ L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE);
+ L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE);
+ L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE);
+ L1_cache_info[ICACHE].size =
+ L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size *
+ L1_cache_info[ICACHE].sets / 1024;
+ pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size,
+ L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways,
+ L1_cache_info[ICACHE].line_size);
+ L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE);
+ L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE);
+ L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE);
+ L1_cache_info[DCACHE].size =
+ L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size *
+ L1_cache_info[DCACHE].sets / 1024;
+ pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size,
+ L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways,
+ L1_cache_info[DCACHE].line_size);
+ pr_info("L1 D-Cache is %s\n", WRITE_METHOD);
+ if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES)
+ pr_crit
+ ("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n",
+ L1_cache_info[DCACHE].size, L1_CACHE_BYTES);
+#ifdef CONFIG_CPU_CACHE_ALIASING
+ {
+ int aliasing_num;
+ aliasing_num =
+ L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE /
+ L1_cache_info[ICACHE].ways;
+ L1_cache_info[ICACHE].aliasing_num = aliasing_num;
+ L1_cache_info[ICACHE].aliasing_mask =
+ (aliasing_num - 1) << PAGE_SHIFT;
+ aliasing_num =
+ L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE /
+ L1_cache_info[DCACHE].ways;
+ L1_cache_info[DCACHE].aliasing_num = aliasing_num;
+ L1_cache_info[DCACHE].aliasing_mask =
+ (aliasing_num - 1) << PAGE_SHIFT;
+ }
+#endif
+}
+
+static void __init setup_cpuinfo(void)
+{
+ unsigned long tmp = 0, cpu_name;
+
+ cpu_dcache_inval_all();
+ cpu_icache_inval_all();
+ __nds32__isb();
+
+ cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID;
+ cpu_name = ((cpu_id) & 0xf0) >> 4;
+ cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N';
+ cpu_id = cpu_id & 0xf;
+ cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV;
+ cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID;
+
+ pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n",
+ cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid);
+
+ elf_hwcap |= HWCAP_MFUSR_PC;
+
+ if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) {
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV)
+ elf_hwcap |= HWCAP_DIV;
+
+ if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC)
+ || (cpu_id == 12 && cpu_rev < 4))
+ elf_hwcap |= HWCAP_MAC;
+ } else {
+ elf_hwcap |= HWCAP_V2;
+ elf_hwcap |= HWCAP_DIV;
+ elf_hwcap |= HWCAP_MAC;
+ }
+
+ if (cpu_cfgid & 0x0001)
+ elf_hwcap |= HWCAP_EXT;
+
+ if (cpu_cfgid & 0x0002)
+ elf_hwcap |= HWCAP_BASE16;
+
+ if (cpu_cfgid & 0x0004)
+ elf_hwcap |= HWCAP_EXT2;
+
+ if (cpu_cfgid & 0x0008)
+ elf_hwcap |= HWCAP_FPU;
+
+ if (cpu_cfgid & 0x0010)
+ elf_hwcap |= HWCAP_STRING;
+
+ if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE)
+ endianness = "MSB";
+ else
+ endianness = "LSB";
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM)
+ elf_hwcap |= HWCAP_EDM;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA)
+ elf_hwcap |= HWCAP_LMDMA;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM)
+ elf_hwcap |= HWCAP_PFM;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP)
+ elf_hwcap |= HWCAP_HSMP;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE)
+ elf_hwcap |= HWCAP_TRACE;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO)
+ elf_hwcap |= HWCAP_AUDIO;
+
+ if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
+ elf_hwcap |= HWCAP_L2C;
+
+ tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
+ if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
+ tmp |= CACHE_CTL_mskDC_EN;
+
+ if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE))
+ tmp |= CACHE_CTL_mskIC_EN;
+ __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
+
+ dump_cpu_info(smp_processor_id());
+}
+
+static void __init setup_memory(void)
+{
+ unsigned long ram_start_pfn;
+ unsigned long free_ram_start_pfn;
+ phys_addr_t memory_start, memory_end;
+ struct memblock_region *region;
+
+ memory_end = memory_start = 0;
+
+ /* Find main memory where is the kernel */
+ for_each_memblock(memory, region) {
+ memory_start = region->base;
+ memory_end = region->base + region->size;
+ pr_info("%s: Memory: 0x%x-0x%x\n", __func__,
+ memory_start, memory_end);
+ }
+
+ if (!memory_end) {
+ panic("No memory!");
+ }
+
+ ram_start_pfn = PFN_UP(memblock_start_of_DRAM());
+ /* free_ram_start_pfn is first page after kernel */
+ free_ram_start_pfn = PFN_UP(__pa(&_end));
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+ /* it could update max_pfn */
+ if (max_pfn - ram_start_pfn <= MAXMEM_PFN)
+ max_low_pfn = max_pfn;
+ else {
+ max_low_pfn = MAXMEM_PFN + ram_start_pfn;
+ if (!IS_ENABLED(CONFIG_HIGHMEM))
+ max_pfn = MAXMEM_PFN + ram_start_pfn;
+ }
+ /* high_memory is related with VMALLOC */
+ high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
+ min_low_pfn = free_ram_start_pfn;
+
+ /*
+ * initialize the boot-time allocator (with low memory only).
+ *
+ * This makes the memory from the end of the kernel to the end of
+ * RAM usable.
+ */
+ memblock_set_bottom_up(true);
+ memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn));
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+}
+
+void __init setup_arch(char **cmdline_p)
+{
+ early_init_devtree( __dtb_start);
+
+ setup_cpuinfo();
+
+ init_mm.start_code = (unsigned long)&_stext;
+ init_mm.end_code = (unsigned long)&_etext;
+ init_mm.end_data = (unsigned long)&_edata;
+ init_mm.brk = (unsigned long)&_end;
+
+ /* setup bootmem allocator */
+ setup_memory();
+
+ /* paging_init() sets up the MMU and marks all pages as reserved */
+ paging_init();
+
+ /* use generic way to parse */
+ parse_early_param();
+
+ unflatten_and_copy_device_tree();
+
+ if(IS_ENABLED(CONFIG_VT)) {
+ if(IS_ENABLED(CONFIG_DUMMY_CONSOLE))
+ conswitchp = &dummy_con;
+ }
+
+ *cmdline_p = boot_command_line;
+ early_trap_init();
+}
+
+static int c_show(struct seq_file *m, void *v)
+{
+ int i;
+
+ seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n",
+ cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid);
+
+ seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n",
+ CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) *
+ CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE),
+ CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE));
+
+ seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n",
+ CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) *
+ CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE),
+ CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE));
+
+ seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
+ loops_per_jiffy / (500000 / HZ),
+ (loops_per_jiffy / (5000 / HZ)) % 100);
+
+ /* dump out the processor features */
+ seq_puts(m, "Features\t: ");
+
+ for (i = 0; hwcap_str[i]; i++)
+ if (elf_hwcap & (1 << i))
+ seq_printf(m, "%s ", hwcap_str[i]);
+
+ seq_puts(m, "\n\n");
+
+ return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t * pos)
+{
+ return *pos < 1 ? (void *)1 : NULL;
+}
+
+static void *c_next(struct seq_file *m, void *v, loff_t * pos)
+{
+ ++*pos;
+ return NULL;
+}
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+struct seq_operations cpuinfo_op = {
+ .start = c_start,
+ .next = c_next,
+ .stop = c_stop,
+ .show = c_show
+};
diff --git a/arch/nds32/kernel/signal.c b/arch/nds32/kernel/signal.c
new file mode 100644
index 000000000000..5d01f6e33cb8
--- /dev/null
+++ b/arch/nds32/kernel/signal.c
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/ptrace.h>
+#include <linux/personality.h>
+#include <linux/freezer.h>
+#include <linux/tracehook.h>
+#include <linux/uaccess.h>
+
+#include <asm/cacheflush.h>
+#include <asm/ucontext.h>
+#include <asm/unistd.h>
+
+#include <asm/ptrace.h>
+#include <asm/vdso.h>
+
+struct rt_sigframe {
+ struct siginfo info;
+ struct ucontext uc;
+};
+
+static int restore_sigframe(struct pt_regs *regs,
+ struct rt_sigframe __user * sf)
+{
+ sigset_t set;
+ int err;
+
+ err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
+ if (err == 0) {
+ set_current_blocked(&set);
+ }
+
+ __get_user_error(regs->uregs[0], &sf->uc.uc_mcontext.nds32_r0, err);
+ __get_user_error(regs->uregs[1], &sf->uc.uc_mcontext.nds32_r1, err);
+ __get_user_error(regs->uregs[2], &sf->uc.uc_mcontext.nds32_r2, err);
+ __get_user_error(regs->uregs[3], &sf->uc.uc_mcontext.nds32_r3, err);
+ __get_user_error(regs->uregs[4], &sf->uc.uc_mcontext.nds32_r4, err);
+ __get_user_error(regs->uregs[5], &sf->uc.uc_mcontext.nds32_r5, err);
+ __get_user_error(regs->uregs[6], &sf->uc.uc_mcontext.nds32_r6, err);
+ __get_user_error(regs->uregs[7], &sf->uc.uc_mcontext.nds32_r7, err);
+ __get_user_error(regs->uregs[8], &sf->uc.uc_mcontext.nds32_r8, err);
+ __get_user_error(regs->uregs[9], &sf->uc.uc_mcontext.nds32_r9, err);
+ __get_user_error(regs->uregs[10], &sf->uc.uc_mcontext.nds32_r10, err);
+ __get_user_error(regs->uregs[11], &sf->uc.uc_mcontext.nds32_r11, err);
+ __get_user_error(regs->uregs[12], &sf->uc.uc_mcontext.nds32_r12, err);
+ __get_user_error(regs->uregs[13], &sf->uc.uc_mcontext.nds32_r13, err);
+ __get_user_error(regs->uregs[14], &sf->uc.uc_mcontext.nds32_r14, err);
+ __get_user_error(regs->uregs[15], &sf->uc.uc_mcontext.nds32_r15, err);
+ __get_user_error(regs->uregs[16], &sf->uc.uc_mcontext.nds32_r16, err);
+ __get_user_error(regs->uregs[17], &sf->uc.uc_mcontext.nds32_r17, err);
+ __get_user_error(regs->uregs[18], &sf->uc.uc_mcontext.nds32_r18, err);
+ __get_user_error(regs->uregs[19], &sf->uc.uc_mcontext.nds32_r19, err);
+ __get_user_error(regs->uregs[20], &sf->uc.uc_mcontext.nds32_r20, err);
+ __get_user_error(regs->uregs[21], &sf->uc.uc_mcontext.nds32_r21, err);
+ __get_user_error(regs->uregs[22], &sf->uc.uc_mcontext.nds32_r22, err);
+ __get_user_error(regs->uregs[23], &sf->uc.uc_mcontext.nds32_r23, err);
+ __get_user_error(regs->uregs[24], &sf->uc.uc_mcontext.nds32_r24, err);
+ __get_user_error(regs->uregs[25], &sf->uc.uc_mcontext.nds32_r25, err);
+
+ __get_user_error(regs->fp, &sf->uc.uc_mcontext.nds32_fp, err);
+ __get_user_error(regs->gp, &sf->uc.uc_mcontext.nds32_gp, err);
+ __get_user_error(regs->lp, &sf->uc.uc_mcontext.nds32_lp, err);
+ __get_user_error(regs->sp, &sf->uc.uc_mcontext.nds32_sp, err);
+ __get_user_error(regs->ipc, &sf->uc.uc_mcontext.nds32_ipc, err);
+#if defined(CONFIG_HWZOL)
+ __get_user_error(regs->lc, &sf->uc.uc_mcontext.zol.nds32_lc, err);
+ __get_user_error(regs->le, &sf->uc.uc_mcontext.zol.nds32_le, err);
+ __get_user_error(regs->lb, &sf->uc.uc_mcontext.zol.nds32_lb, err);
+#endif
+
+ /*
+ * Avoid sys_rt_sigreturn() restarting.
+ */
+ forget_syscall(regs);
+ return err;
+}
+
+asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
+{
+ struct rt_sigframe __user *frame;
+
+ /* Always make any pending restarted system calls return -EINTR */
+ current->restart_block.fn = do_no_restart_syscall;
+
+ /*
+ * Since we stacked the signal on a 64-bit boundary,
+ * then 'sp' should be two-word aligned here. If it's
+ * not, then the user is trying to mess with us.
+ */
+ if (regs->sp & 7)
+ goto badframe;
+
+ frame = (struct rt_sigframe __user *)regs->sp;
+
+ if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+ goto badframe;
+
+ if (restore_sigframe(regs, frame))
+ goto badframe;
+
+ if (restore_altstack(&frame->uc.uc_stack))
+ goto badframe;
+
+ return regs->uregs[0];
+
+badframe:
+ force_sig(SIGSEGV, current);
+ return 0;
+}
+
+static int
+setup_sigframe(struct rt_sigframe __user * sf, struct pt_regs *regs,
+ sigset_t * set)
+{
+ int err = 0;
+
+ __put_user_error(regs->uregs[0], &sf->uc.uc_mcontext.nds32_r0, err);
+ __put_user_error(regs->uregs[1], &sf->uc.uc_mcontext.nds32_r1, err);
+ __put_user_error(regs->uregs[2], &sf->uc.uc_mcontext.nds32_r2, err);
+ __put_user_error(regs->uregs[3], &sf->uc.uc_mcontext.nds32_r3, err);
+ __put_user_error(regs->uregs[4], &sf->uc.uc_mcontext.nds32_r4, err);
+ __put_user_error(regs->uregs[5], &sf->uc.uc_mcontext.nds32_r5, err);
+ __put_user_error(regs->uregs[6], &sf->uc.uc_mcontext.nds32_r6, err);
+ __put_user_error(regs->uregs[7], &sf->uc.uc_mcontext.nds32_r7, err);
+ __put_user_error(regs->uregs[8], &sf->uc.uc_mcontext.nds32_r8, err);
+ __put_user_error(regs->uregs[9], &sf->uc.uc_mcontext.nds32_r9, err);
+ __put_user_error(regs->uregs[10], &sf->uc.uc_mcontext.nds32_r10, err);
+ __put_user_error(regs->uregs[11], &sf->uc.uc_mcontext.nds32_r11, err);
+ __put_user_error(regs->uregs[12], &sf->uc.uc_mcontext.nds32_r12, err);
+ __put_user_error(regs->uregs[13], &sf->uc.uc_mcontext.nds32_r13, err);
+ __put_user_error(regs->uregs[14], &sf->uc.uc_mcontext.nds32_r14, err);
+ __put_user_error(regs->uregs[15], &sf->uc.uc_mcontext.nds32_r15, err);
+ __put_user_error(regs->uregs[16], &sf->uc.uc_mcontext.nds32_r16, err);
+ __put_user_error(regs->uregs[17], &sf->uc.uc_mcontext.nds32_r17, err);
+ __put_user_error(regs->uregs[18], &sf->uc.uc_mcontext.nds32_r18, err);
+ __put_user_error(regs->uregs[19], &sf->uc.uc_mcontext.nds32_r19, err);
+ __put_user_error(regs->uregs[20], &sf->uc.uc_mcontext.nds32_r20, err);
+
+ __put_user_error(regs->uregs[21], &sf->uc.uc_mcontext.nds32_r21, err);
+ __put_user_error(regs->uregs[22], &sf->uc.uc_mcontext.nds32_r22, err);
+ __put_user_error(regs->uregs[23], &sf->uc.uc_mcontext.nds32_r23, err);
+ __put_user_error(regs->uregs[24], &sf->uc.uc_mcontext.nds32_r24, err);
+ __put_user_error(regs->uregs[25], &sf->uc.uc_mcontext.nds32_r25, err);
+ __put_user_error(regs->fp, &sf->uc.uc_mcontext.nds32_fp, err);
+ __put_user_error(regs->gp, &sf->uc.uc_mcontext.nds32_gp, err);
+ __put_user_error(regs->lp, &sf->uc.uc_mcontext.nds32_lp, err);
+ __put_user_error(regs->sp, &sf->uc.uc_mcontext.nds32_sp, err);
+ __put_user_error(regs->ipc, &sf->uc.uc_mcontext.nds32_ipc, err);
+#if defined(CONFIG_HWZOL)
+ __put_user_error(regs->lc, &sf->uc.uc_mcontext.zol.nds32_lc, err);
+ __put_user_error(regs->le, &sf->uc.uc_mcontext.zol.nds32_le, err);
+ __put_user_error(regs->lb, &sf->uc.uc_mcontext.zol.nds32_lb, err);
+#endif
+
+ __put_user_error(current->thread.trap_no, &sf->uc.uc_mcontext.trap_no,
+ err);
+ __put_user_error(current->thread.error_code,
+ &sf->uc.uc_mcontext.error_code, err);
+ __put_user_error(current->thread.address,
+ &sf->uc.uc_mcontext.fault_address, err);
+ __put_user_error(set->sig[0], &sf->uc.uc_mcontext.oldmask, err);
+
+ err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(*set));
+
+ return err;
+}
+
+static inline void __user *get_sigframe(struct ksignal *ksig,
+ struct pt_regs *regs, int framesize)
+{
+ unsigned long sp;
+
+ /* Default to using normal stack */
+ sp = regs->sp;
+
+ /*
+ * If we are on the alternate signal stack and would overflow it, don't.
+ * Return an always-bogus address instead so we will die with SIGSEGV.
+ */
+ if (on_sig_stack(sp) && !likely(on_sig_stack(sp - framesize)))
+ return (void __user __force *)(-1UL);
+
+ /* This is the X/Open sanctioned signal stack switching. */
+ sp = (sigsp(sp, ksig) - framesize);
+
+ /*
+ * nds32 mandates 8-byte alignment
+ */
+ sp &= ~0x7UL;
+
+ return (void __user *)sp;
+}
+
+static int
+setup_return(struct pt_regs *regs, struct ksignal *ksig, void __user * frame)
+{
+ unsigned long handler = (unsigned long)ksig->ka.sa.sa_handler;
+ unsigned long retcode;
+
+ retcode = VDSO_SYMBOL(current->mm->context.vdso, rt_sigtramp);
+ regs->uregs[0] = ksig->sig;
+ regs->sp = (unsigned long)frame;
+ regs->lp = retcode;
+ regs->ipc = handler;
+
+ return 0;
+}
+
+static int
+setup_rt_frame(struct ksignal *ksig, sigset_t * set, struct pt_regs *regs)
+{
+ struct rt_sigframe __user *frame =
+ get_sigframe(ksig, regs, sizeof(*frame));
+ int err = 0;
+
+ if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+ return -EFAULT;
+
+ __put_user_error(0, &frame->uc.uc_flags, err);
+ __put_user_error(NULL, &frame->uc.uc_link, err);
+
+ err |= __save_altstack(&frame->uc.uc_stack, regs->sp);
+ err |= setup_sigframe(frame, regs, set);
+ if (err == 0) {
+ setup_return(regs, ksig, frame);
+ if (ksig->ka.sa.sa_flags & SA_SIGINFO) {
+ err |= copy_siginfo_to_user(&frame->info, &ksig->info);
+ regs->uregs[1] = (unsigned long)&frame->info;
+ regs->uregs[2] = (unsigned long)&frame->uc;
+ }
+ }
+ return err;
+}
+
+/*
+ * OK, we're invoking a handler
+ */
+static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
+{
+ int ret;
+ sigset_t *oldset = sigmask_to_save();
+
+ if (in_syscall(regs)) {
+ /* Avoid additional syscall restarting via ret_slow_syscall. */
+ forget_syscall(regs);
+
+ switch (regs->uregs[0]) {
+ case -ERESTART_RESTARTBLOCK:
+ case -ERESTARTNOHAND:
+ regs->uregs[0] = -EINTR;
+ break;
+ case -ERESTARTSYS:
+ if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
+ regs->uregs[0] = -EINTR;
+ break;
+ }
+ case -ERESTARTNOINTR:
+ regs->uregs[0] = regs->orig_r0;
+ regs->ipc -= 4;
+ break;
+ }
+ }
+ /*
+ * Set up the stack frame
+ */
+ ret = setup_rt_frame(ksig, oldset, regs);
+
+ signal_setup_done(ret, ksig, 0);
+}
+
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ *
+ * Note that we go through the signals twice: once to check the signals that
+ * the kernel can handle, and then we build all the user-level signal handling
+ * stack-frames in one go after that.
+ */
+static void do_signal(struct pt_regs *regs)
+{
+ struct ksignal ksig;
+
+ if (get_signal(&ksig)) {
+ handle_signal(&ksig, regs);
+ return;
+ }
+
+ /*
+ * If we were from a system call, check for system call restarting...
+ */
+ if (in_syscall(regs)) {
+ /* Restart the system call - no handlers present */
+
+ /* Avoid additional syscall restarting via ret_slow_syscall. */
+ forget_syscall(regs);
+
+ switch (regs->uregs[0]) {
+ case -ERESTART_RESTARTBLOCK:
+ regs->uregs[15] = __NR_restart_syscall;
+ case -ERESTARTNOHAND:
+ case -ERESTARTSYS:
+ case -ERESTARTNOINTR:
+ regs->uregs[0] = regs->orig_r0;
+ regs->ipc -= 0x4;
+ break;
+ }
+ }
+ restore_saved_sigmask();
+}
+
+asmlinkage void
+do_notify_resume(struct pt_regs *regs, unsigned int thread_flags)
+{
+ if (thread_flags & _TIF_SIGPENDING)
+ do_signal(regs);
+
+ if (thread_flags & _TIF_NOTIFY_RESUME) {
+ clear_thread_flag(TIF_NOTIFY_RESUME);
+ tracehook_notify_resume(regs);
+ }
+}
diff --git a/arch/nds32/kernel/stacktrace.c b/arch/nds32/kernel/stacktrace.c
new file mode 100644
index 000000000000..bc70113c0e84
--- /dev/null
+++ b/arch/nds32/kernel/stacktrace.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/sched/debug.h>
+#include <linux/sched/task_stack.h>
+#include <linux/stacktrace.h>
+
+void save_stack_trace(struct stack_trace *trace)
+{
+ save_stack_trace_tsk(current, trace);
+}
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+ unsigned long *fpn;
+ int skip = trace->skip;
+ int savesched;
+
+ if (tsk == current) {
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(fpn));
+ savesched = 1;
+ } else {
+ fpn = (unsigned long *)thread_saved_fp(tsk);
+ savesched = 0;
+ }
+
+ while (!kstack_end(fpn) && !((unsigned long)fpn & 0x3)
+ && (fpn >= (unsigned long *)TASK_SIZE)) {
+ unsigned long lpp, fpp;
+
+ lpp = fpn[-1];
+ fpp = fpn[FP_OFFSET];
+ if (!__kernel_text_address(lpp))
+ break;
+
+ if (savesched || !in_sched_functions(lpp)) {
+ if (skip) {
+ skip--;
+ } else {
+ trace->entries[trace->nr_entries++] = lpp;
+ if (trace->nr_entries >= trace->max_entries)
+ break;
+ }
+ }
+ fpn = (unsigned long *)fpp;
+ }
+}
diff --git a/arch/nds32/kernel/sys_nds32.c b/arch/nds32/kernel/sys_nds32.c
new file mode 100644
index 000000000000..9de93ab4c52b
--- /dev/null
+++ b/arch/nds32/kernel/sys_nds32.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+
+#include <asm/cachectl.h>
+#include <asm/proc-fns.h>
+
+SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
+ unsigned long, prot, unsigned long, flags,
+ unsigned long, fd, unsigned long, pgoff)
+{
+ if (pgoff & (~PAGE_MASK >> 12))
+ return -EINVAL;
+
+ return sys_mmap_pgoff(addr, len, prot, flags, fd,
+ pgoff >> (PAGE_SHIFT - 12));
+}
+
+SYSCALL_DEFINE4(fadvise64_64_wrapper,int, fd, int, advice, loff_t, offset,
+ loff_t, len)
+{
+ return sys_fadvise64_64(fd, offset, len, advice);
+}
+
+SYSCALL_DEFINE3(cacheflush, unsigned int, start, unsigned int, end, int, cache)
+{
+ struct vm_area_struct *vma;
+ bool flushi = true, wbd = true;
+
+ vma = find_vma(current->mm, start);
+ if (!vma)
+ return -EFAULT;
+ switch (cache) {
+ case ICACHE:
+ wbd = false;
+ break;
+ case DCACHE:
+ flushi = false;
+ break;
+ case BCACHE:
+ break;
+ default:
+ return -EINVAL;
+ }
+ cpu_cache_wbinval_range_check(vma, start, end, flushi, wbd);
+
+ return 0;
+}
diff --git a/arch/nds32/kernel/syscall_table.c b/arch/nds32/kernel/syscall_table.c
new file mode 100644
index 000000000000..7879c061b87f
--- /dev/null
+++ b/arch/nds32/kernel/syscall_table.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/syscalls.h>
+#include <linux/signal.h>
+#include <linux/unistd.h>
+#include <asm/syscalls.h>
+
+#undef __SYSCALL
+#define __SYSCALL(nr, call) [nr] = (call),
+
+#define sys_rt_sigreturn sys_rt_sigreturn_wrapper
+#define sys_fadvise64_64 sys_fadvise64_64_wrapper
+void *sys_call_table[__NR_syscalls] __aligned(8192) = {
+ [0 ... __NR_syscalls - 1] = sys_ni_syscall,
+#include <asm/unistd.h>
+};
diff --git a/arch/nds32/kernel/time.c b/arch/nds32/kernel/time.c
new file mode 100644
index 000000000000..ac9d78ce3a81
--- /dev/null
+++ b/arch/nds32/kernel/time.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
+
+void __init time_init(void)
+{
+ of_clk_init(NULL);
+ timer_probe();
+}
diff --git a/arch/nds32/kernel/traps.c b/arch/nds32/kernel/traps.c
new file mode 100644
index 000000000000..6e34eb9824a4
--- /dev/null
+++ b/arch/nds32/kernel/traps.c
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/module.h>
+#include <linux/personality.h>
+#include <linux/kallsyms.h>
+#include <linux/hardirq.h>
+#include <linux/kdebug.h>
+#include <linux/sched/task_stack.h>
+#include <linux/uaccess.h>
+
+#include <asm/proc-fns.h>
+#include <asm/unistd.h>
+
+#include <linux/ptrace.h>
+#include <nds32_intrinsic.h>
+
+extern void show_pte(struct mm_struct *mm, unsigned long addr);
+
+/*
+ * Dump out the contents of some memory nicely...
+ */
+void dump_mem(const char *lvl, unsigned long bottom, unsigned long top)
+{
+ unsigned long first;
+ mm_segment_t fs;
+ int i;
+
+ /*
+ * We need to switch to kernel mode so that we can use __get_user
+ * to safely read from kernel space. Note that we now dump the
+ * code first, just in case the backtrace kills us.
+ */
+ fs = get_fs();
+ set_fs(KERNEL_DS);
+
+ pr_emerg("%s(0x%08lx to 0x%08lx)\n", lvl, bottom, top);
+
+ for (first = bottom & ~31; first < top; first += 32) {
+ unsigned long p;
+ char str[sizeof(" 12345678") * 8 + 1];
+
+ memset(str, ' ', sizeof(str));
+ str[sizeof(str) - 1] = '\0';
+
+ for (p = first, i = 0; i < 8 && p < top; i++, p += 4) {
+ if (p >= bottom && p < top) {
+ unsigned long val;
+ if (__get_user(val, (unsigned long *)p) == 0)
+ sprintf(str + i * 9, " %08lx", val);
+ else
+ sprintf(str + i * 9, " ????????");
+ }
+ }
+ pr_emerg("%s%04lx:%s\n", lvl, first & 0xffff, str);
+ }
+
+ set_fs(fs);
+}
+
+EXPORT_SYMBOL(dump_mem);
+
+static void dump_instr(struct pt_regs *regs)
+{
+ unsigned long addr = instruction_pointer(regs);
+ mm_segment_t fs;
+ char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
+ int i;
+
+ return;
+ /*
+ * We need to switch to kernel mode so that we can use __get_user
+ * to safely read from kernel space. Note that we now dump the
+ * code first, just in case the backtrace kills us.
+ */
+ fs = get_fs();
+ set_fs(KERNEL_DS);
+
+ pr_emerg("Code: ");
+ for (i = -4; i < 1; i++) {
+ unsigned int val, bad;
+
+ bad = __get_user(val, &((u32 *) addr)[i]);
+
+ if (!bad) {
+ p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
+ } else {
+ p += sprintf(p, "bad PC value");
+ break;
+ }
+ }
+ pr_emerg("Code: %s\n", str);
+
+ set_fs(fs);
+}
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#include <linux/ftrace.h>
+static void
+get_real_ret_addr(unsigned long *addr, struct task_struct *tsk, int *graph)
+{
+ if (*addr == (unsigned long)return_to_handler) {
+ int index = tsk->curr_ret_stack;
+
+ if (tsk->ret_stack && index >= *graph) {
+ index -= *graph;
+ *addr = tsk->ret_stack[index].ret;
+ (*graph)++;
+ }
+ }
+}
+#else
+static inline void
+get_real_ret_addr(unsigned long *addr, struct task_struct *tsk, int *graph)
+{
+}
+#endif
+
+#define LOOP_TIMES (100)
+static void __dump(struct task_struct *tsk, unsigned long *base_reg)
+{
+ unsigned long ret_addr;
+ int cnt = LOOP_TIMES, graph = 0;
+ pr_emerg("Call Trace:\n");
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER)) {
+ while (!kstack_end(base_reg)) {
+ ret_addr = *base_reg++;
+ if (__kernel_text_address(ret_addr)) {
+ get_real_ret_addr(&ret_addr, tsk, &graph);
+ print_ip_sym(ret_addr);
+ }
+ if (--cnt < 0)
+ break;
+ }
+ } else {
+ while (!kstack_end((void *)base_reg) &&
+ !((unsigned long)base_reg & 0x3) &&
+ ((unsigned long)base_reg >= TASK_SIZE)) {
+ unsigned long next_fp;
+#if !defined(NDS32_ABI_2)
+ ret_addr = base_reg[0];
+ next_fp = base_reg[1];
+#else
+ ret_addr = base_reg[-1];
+ next_fp = base_reg[FP_OFFSET];
+#endif
+ if (__kernel_text_address(ret_addr)) {
+ get_real_ret_addr(&ret_addr, tsk, &graph);
+ print_ip_sym(ret_addr);
+ }
+ if (--cnt < 0)
+ break;
+ base_reg = (unsigned long *)next_fp;
+ }
+ }
+ pr_emerg("\n");
+}
+
+void show_stack(struct task_struct *tsk, unsigned long *sp)
+{
+ unsigned long *base_reg;
+
+ if (!tsk)
+ tsk = current;
+ if (!IS_ENABLED(CONFIG_FRAME_POINTER)) {
+ if (tsk != current)
+ base_reg = (unsigned long *)(tsk->thread.cpu_context.sp);
+ else
+ __asm__ __volatile__("\tori\t%0, $sp, #0\n":"=r"(base_reg));
+ } else {
+ if (tsk != current)
+ base_reg = (unsigned long *)(tsk->thread.cpu_context.fp);
+ else
+ __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(base_reg));
+ }
+ __dump(tsk, base_reg);
+ barrier();
+}
+
+DEFINE_SPINLOCK(die_lock);
+
+/*
+ * This function is protected against re-entrancy.
+ */
+void die(const char *str, struct pt_regs *regs, int err)
+{
+ struct task_struct *tsk = current;
+ static int die_counter;
+
+ console_verbose();
+ spin_lock_irq(&die_lock);
+ bust_spinlocks(1);
+
+ pr_emerg("Internal error: %s: %x [#%d]\n", str, err, ++die_counter);
+ print_modules();
+ pr_emerg("CPU: %i\n", smp_processor_id());
+ show_regs(regs);
+ pr_emerg("Process %s (pid: %d, stack limit = 0x%p)\n",
+ tsk->comm, tsk->pid, task_thread_info(tsk) + 1);
+
+ if (!user_mode(regs) || in_interrupt()) {
+ dump_mem("Stack: ", regs->sp,
+ THREAD_SIZE + (unsigned long)task_thread_info(tsk));
+ dump_instr(regs);
+ dump_stack();
+ }
+
+ bust_spinlocks(0);
+ spin_unlock_irq(&die_lock);
+ do_exit(SIGSEGV);
+}
+
+EXPORT_SYMBOL(die);
+
+void die_if_kernel(const char *str, struct pt_regs *regs, int err)
+{
+ if (user_mode(regs))
+ return;
+
+ die(str, regs, err);
+}
+
+int bad_syscall(int n, struct pt_regs *regs)
+{
+ siginfo_t info;
+
+ if (current->personality != PER_LINUX) {
+ send_sig(SIGSEGV, current, 1);
+ return regs->uregs[0];
+ }
+
+ info.si_signo = SIGILL;
+ info.si_errno = 0;
+ info.si_code = ILL_ILLTRP;
+ info.si_addr = (void __user *)instruction_pointer(regs) - 4;
+
+ force_sig_info(SIGILL, &info, current);
+ die_if_kernel("Oops - bad syscall", regs, n);
+ return regs->uregs[0];
+}
+
+void __pte_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pte %08lx.\n", file, line, val);
+}
+
+void __pmd_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pmd %08lx.\n", file, line, val);
+}
+
+void __pgd_error(const char *file, int line, unsigned long val)
+{
+ pr_emerg("%s:%d: bad pgd %08lx.\n", file, line, val);
+}
+
+extern char *exception_vector, *exception_vector_end;
+void __init trap_init(void)
+{
+ return;
+}
+
+void __init early_trap_init(void)
+{
+ unsigned long ivb = 0;
+ unsigned long base = PAGE_OFFSET;
+
+ memcpy((unsigned long *)base, (unsigned long *)&exception_vector,
+ ((unsigned long)&exception_vector_end -
+ (unsigned long)&exception_vector));
+ ivb = __nds32__mfsr(NDS32_SR_IVB);
+ /* Check platform support. */
+ if (((ivb & IVB_mskNIVIC) >> IVB_offNIVIC) < 2)
+ panic
+ ("IVIC mode is not allowed on the platform with interrupt controller\n");
+ __nds32__mtsr((ivb & ~IVB_mskESZ) | (IVB_valESZ16 << IVB_offESZ) |
+ IVB_BASE, NDS32_SR_IVB);
+ __nds32__mtsr(INT_MASK_INITAIAL_VAL, NDS32_SR_INT_MASK);
+
+ /*
+ * 0x800 = 128 vectors * 16byte.
+ * It should be enough to flush a page.
+ */
+ cpu_cache_wbinval_page(base, true);
+}
+
+void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
+ int error_code, int si_code)
+{
+ struct siginfo info;
+
+ tsk->thread.trap_no = ENTRY_DEBUG_RELATED;
+ tsk->thread.error_code = error_code;
+
+ memset(&info, 0, sizeof(info));
+ info.si_signo = SIGTRAP;
+ info.si_code = si_code;
+ info.si_addr = (void __user *)instruction_pointer(regs);
+ force_sig_info(SIGTRAP, &info, tsk);
+}
+
+void do_debug_trap(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ if (notify_die(DIE_OOPS, "Oops", regs, addr, type, SIGTRAP)
+ == NOTIFY_STOP)
+ return;
+
+ if (user_mode(regs)) {
+ /* trap_signal */
+ send_sigtrap(current, regs, 0, TRAP_BRKPT);
+ } else {
+ /* kernel_trap */
+ if (!fixup_exception(regs))
+ die("unexpected kernel_trap", regs, 0);
+ }
+}
+
+void unhandled_interruption(struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("unhandled_interruption\n");
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGKILL);
+ si.si_signo = SIGKILL;
+ si.si_errno = 0;
+ force_sig_info(SIGKILL, &si, current);
+}
+
+void unhandled_exceptions(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("Unhandled Exception: entry: %lx addr:%lx itype:%lx\n", entry,
+ addr, type);
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGKILL);
+ si.si_signo = SIGKILL;
+ si.si_errno = 0;
+ si.si_addr = (void *)addr;
+ force_sig_info(SIGKILL, &si, current);
+}
+
+extern int do_page_fault(unsigned long entry, unsigned long addr,
+ unsigned int error_code, struct pt_regs *regs);
+
+/*
+ * 2:DEF dispatch for TLB MISC exception handler
+*/
+
+void do_dispatch_tlb_misc(unsigned long entry, unsigned long addr,
+ unsigned long type, struct pt_regs *regs)
+{
+ type = type & (ITYPE_mskINST | ITYPE_mskETYPE);
+ if ((type & ITYPE_mskETYPE) < 5) {
+ /* Permission exceptions */
+ do_page_fault(entry, addr, type, regs);
+ } else
+ unhandled_exceptions(entry, addr, type, regs);
+}
+
+void do_revinsn(struct pt_regs *regs)
+{
+ siginfo_t si;
+ pr_emerg("Reserved Instruction\n");
+ show_regs(regs);
+ if (!user_mode(regs))
+ do_exit(SIGILL);
+ si.si_signo = SIGILL;
+ si.si_errno = 0;
+ force_sig_info(SIGILL, &si, current);
+}
+
+#ifdef CONFIG_ALIGNMENT_TRAP
+extern int unalign_access_mode;
+extern int do_unaligned_access(unsigned long addr, struct pt_regs *regs);
+#endif
+void do_dispatch_general(unsigned long entry, unsigned long addr,
+ unsigned long itype, struct pt_regs *regs,
+ unsigned long oipc)
+{
+ unsigned int swid = itype >> ITYPE_offSWID;
+ unsigned long type = itype & (ITYPE_mskINST | ITYPE_mskETYPE);
+ if (type == ETYPE_ALIGNMENT_CHECK) {
+#ifdef CONFIG_ALIGNMENT_TRAP
+ /* Alignment check */
+ if (user_mode(regs) && unalign_access_mode) {
+ int ret;
+ ret = do_unaligned_access(addr, regs);
+
+ if (ret == 0)
+ return;
+
+ if (ret == -EFAULT)
+ pr_emerg
+ ("Unhandled unaligned access exception\n");
+ }
+#endif
+ do_page_fault(entry, addr, type, regs);
+ } else if (type == ETYPE_RESERVED_INSTRUCTION) {
+ /* Reserved instruction */
+ do_revinsn(regs);
+ } else if (type == ETYPE_TRAP && swid == SWID_RAISE_INTERRUPT_LEVEL) {
+ /* trap, used on v3 EDM target debugging workaround */
+ /*
+ * DIPC(OIPC) is passed as parameter before
+ * interrupt is enabled, so the DIPC will not be corrupted
+ * even though interrupts are coming in
+ */
+ /*
+ * 1. update ipc
+ * 2. update pt_regs ipc with oipc
+ * 3. update pt_regs ipsw (clear DEX)
+ */
+ __asm__ volatile ("mtsr %0, $IPC\n\t"::"r" (oipc));
+ regs->ipc = oipc;
+ if (regs->pipsw & PSW_mskDEX) {
+ pr_emerg
+ ("Nested Debug exception is possibly happened\n");
+ pr_emerg("ipc:%08x pipc:%08x\n",
+ (unsigned int)regs->ipc,
+ (unsigned int)regs->pipc);
+ }
+ do_debug_trap(entry, addr, itype, regs);
+ regs->ipsw &= ~PSW_mskDEX;
+ } else
+ unhandled_exceptions(entry, addr, type, regs);
+}
diff --git a/arch/nds32/kernel/vdso.c b/arch/nds32/kernel/vdso.c
new file mode 100644
index 000000000000..f1198d7a5654
--- /dev/null
+++ b/arch/nds32/kernel/vdso.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/cache.h>
+#include <linux/clocksource.h>
+#include <linux/elf.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/slab.h>
+#include <linux/timekeeper_internal.h>
+#include <linux/vmalloc.h>
+#include <linux/random.h>
+
+#include <asm/cacheflush.h>
+#include <asm/vdso.h>
+#include <asm/vdso_datapage.h>
+#include <asm/vdso_timer_info.h>
+#include <asm/cache_info.h>
+extern struct cache_info L1_cache_info[2];
+extern char vdso_start, vdso_end;
+static unsigned long vdso_pages __ro_after_init;
+static unsigned long timer_mapping_base;
+
+struct timer_info_t timer_info = {
+ .cycle_count_down = true,
+ .mapping_base = EMPTY_TIMER_MAPPING,
+ .cycle_count_reg_offset = EMPTY_REG_OFFSET
+};
+/*
+ * The vDSO data page.
+ */
+static struct page *no_pages[] = { NULL };
+
+static union {
+ struct vdso_data data;
+ u8 page[PAGE_SIZE];
+} vdso_data_store __page_aligned_data;
+struct vdso_data *vdso_data = &vdso_data_store.data;
+static struct vm_special_mapping vdso_spec[2] __ro_after_init = {
+ {
+ .name = "[vvar]",
+ .pages = no_pages,
+ },
+ {
+ .name = "[vdso]",
+ },
+};
+
+static void get_timer_node_info(void)
+{
+ timer_mapping_base = timer_info.mapping_base;
+ vdso_data->cycle_count_offset =
+ timer_info.cycle_count_reg_offset;
+ vdso_data->cycle_count_down =
+ timer_info.cycle_count_down;
+}
+
+static int __init vdso_init(void)
+{
+ int i;
+ struct page **vdso_pagelist;
+
+ if (memcmp(&vdso_start, "\177ELF", 4)) {
+ pr_err("vDSO is not a valid ELF object!\n");
+ return -EINVAL;
+ }
+ /* Creat a timer io mapping to get clock cycles counter */
+ get_timer_node_info();
+
+ vdso_pages = (&vdso_end - &vdso_start) >> PAGE_SHIFT;
+ pr_info("vdso: %ld pages (%ld code @ %p, %ld data @ %p)\n",
+ vdso_pages + 1, vdso_pages, &vdso_start, 1L, vdso_data);
+
+ /* Allocate the vDSO pagelist */
+ vdso_pagelist = kcalloc(vdso_pages, sizeof(struct page *), GFP_KERNEL);
+ if (vdso_pagelist == NULL)
+ return -ENOMEM;
+
+ for (i = 0; i < vdso_pages; i++)
+ vdso_pagelist[i] = virt_to_page(&vdso_start + i * PAGE_SIZE);
+ vdso_spec[1].pages = &vdso_pagelist[0];
+
+ return 0;
+}
+
+arch_initcall(vdso_init);
+
+unsigned long inline vdso_random_addr(unsigned long vdso_mapping_len)
+{
+ unsigned long start = current->mm->mmap_base, end, offset, addr;
+ start = PAGE_ALIGN(start);
+
+ /* Round the lowest possible end address up to a PMD boundary. */
+ end = (start + vdso_mapping_len + PMD_SIZE - 1) & PMD_MASK;
+ if (end >= TASK_SIZE)
+ end = TASK_SIZE;
+ end -= vdso_mapping_len;
+
+ if (end > start) {
+ offset = get_random_int() % (((end - start) >> PAGE_SHIFT) + 1);
+ addr = start + (offset << PAGE_SHIFT);
+ } else {
+ addr = start;
+ }
+ return addr;
+}
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+ struct mm_struct *mm = current->mm;
+ unsigned long vdso_base, vdso_text_len, vdso_mapping_len;
+ struct vm_area_struct *vma;
+ unsigned long addr = 0;
+ pgprot_t prot;
+ int ret, vvar_page_num = 2;
+
+ vdso_text_len = vdso_pages << PAGE_SHIFT;
+
+ if(timer_mapping_base == EMPTY_VALUE)
+ vvar_page_num = 1;
+ /* Be sure to map the data page */
+ vdso_mapping_len = vdso_text_len + vvar_page_num * PAGE_SIZE;
+#ifdef CONFIG_CPU_CACHE_ALIASING
+ vdso_mapping_len += L1_cache_info[DCACHE].aliasing_num - 1;
+#endif
+
+ if (down_write_killable(&mm->mmap_sem))
+ return -EINTR;
+
+ addr = vdso_random_addr(vdso_mapping_len);
+ vdso_base = get_unmapped_area(NULL, addr, vdso_mapping_len, 0, 0);
+ if (IS_ERR_VALUE(vdso_base)) {
+ ret = vdso_base;
+ goto up_fail;
+ }
+
+#ifdef CONFIG_CPU_CACHE_ALIASING
+ {
+ unsigned int aliasing_mask =
+ L1_cache_info[DCACHE].aliasing_mask;
+ unsigned int page_colour_ofs;
+ page_colour_ofs = ((unsigned int)vdso_data & aliasing_mask) -
+ (vdso_base & aliasing_mask);
+ vdso_base += page_colour_ofs & aliasing_mask;
+ }
+#endif
+
+ vma = _install_special_mapping(mm, vdso_base, vvar_page_num * PAGE_SIZE,
+ VM_READ | VM_MAYREAD, &vdso_spec[0]);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto up_fail;
+ }
+
+ /*Map vdata to user space */
+ ret = io_remap_pfn_range(vma, vdso_base,
+ virt_to_phys(vdso_data) >> PAGE_SHIFT,
+ PAGE_SIZE, vma->vm_page_prot);
+ if (ret)
+ goto up_fail;
+
+ /*Map timer to user space */
+ vdso_base += PAGE_SIZE;
+ prot = __pgprot(_PAGE_V | _PAGE_M_UR_KR | _PAGE_D | _PAGE_C_DEV);
+ ret = io_remap_pfn_range(vma, vdso_base, timer_mapping_base >> PAGE_SHIFT,
+ PAGE_SIZE, prot);
+ if (ret)
+ goto up_fail;
+
+ /*Map vdso to user space */
+ vdso_base += PAGE_SIZE;
+ mm->context.vdso = (void *)vdso_base;
+ vma = _install_special_mapping(mm, vdso_base, vdso_text_len,
+ VM_READ | VM_EXEC |
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
+ &vdso_spec[1]);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto up_fail;
+ }
+
+ up_write(&mm->mmap_sem);
+ return 0;
+
+up_fail:
+ mm->context.vdso = NULL;
+ up_write(&mm->mmap_sem);
+ return ret;
+}
+
+static void vdso_write_begin(struct vdso_data *vdata)
+{
+ ++vdso_data->seq_count;
+ smp_wmb(); /* Pairs with smp_rmb in vdso_read_retry */
+}
+
+static void vdso_write_end(struct vdso_data *vdata)
+{
+ smp_wmb(); /* Pairs with smp_rmb in vdso_read_begin */
+ ++vdso_data->seq_count;
+}
+
+void update_vsyscall(struct timekeeper *tk)
+{
+ vdso_write_begin(vdso_data);
+ vdso_data->cs_mask = tk->tkr_mono.mask;
+ vdso_data->cs_mult = tk->tkr_mono.mult;
+ vdso_data->cs_shift = tk->tkr_mono.shift;
+ vdso_data->cs_cycle_last = tk->tkr_mono.cycle_last;
+ vdso_data->wtm_clock_sec = tk->wall_to_monotonic.tv_sec;
+ vdso_data->wtm_clock_nsec = tk->wall_to_monotonic.tv_nsec;
+ vdso_data->xtime_clock_sec = tk->xtime_sec;
+ vdso_data->xtime_clock_nsec = tk->tkr_mono.xtime_nsec;
+ vdso_data->xtime_coarse_sec = tk->xtime_sec;
+ vdso_data->xtime_coarse_nsec = tk->tkr_mono.xtime_nsec >>
+ tk->tkr_mono.shift;
+ vdso_write_end(vdso_data);
+}
+
+void update_vsyscall_tz(void)
+{
+ vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
+ vdso_data->tz_dsttime = sys_tz.tz_dsttime;
+}
diff --git a/arch/nds32/kernel/vdso/Makefile b/arch/nds32/kernel/vdso/Makefile
new file mode 100644
index 000000000000..e6c50a701313
--- /dev/null
+++ b/arch/nds32/kernel/vdso/Makefile
@@ -0,0 +1,82 @@
+#
+# Building a vDSO image for AArch64.
+#
+# Author: Will Deacon <will.deacon@arm.com>
+# Heavily based on the vDSO Makefiles for other archs.
+#
+
+obj-vdso := note.o datapage.o sigreturn.o gettimeofday.o
+
+# Build rules
+targets := $(obj-vdso) vdso.so vdso.so.dbg
+obj-vdso := $(addprefix $(obj)/, $(obj-vdso))
+
+ccflags-y := -shared -fno-common -fno-builtin
+ccflags-y += -nostdlib -Wl,-soname=linux-vdso.so.1 \
+ $(call cc-ldoption, -Wl$(comma)--hash-style=sysv)
+ccflags-y += -fPIC -Wl,-shared -g
+
+# Disable gcov profiling for VDSO code
+GCOV_PROFILE := n
+
+
+obj-y += vdso.o
+extra-y += vdso.lds
+CPPFLAGS_vdso.lds += -P -C -U$(ARCH)
+
+# Force dependency
+$(obj)/vdso.o : $(obj)/vdso.so
+
+# Link rule for the .so file, .lds has to be first
+$(obj)/vdso.so.dbg: $(src)/vdso.lds $(obj-vdso)
+ $(call if_changed,vdsold)
+
+
+# Strip rule for the .so file
+$(obj)/%.so: OBJCOPYFLAGS := -S
+$(obj)/%.so: $(obj)/%.so.dbg FORCE
+ $(call if_changed,objcopy)
+
+# Generate VDSO offsets using helper script
+gen-vdsosym := $(srctree)/$(src)/gen_vdso_offsets.sh
+quiet_cmd_vdsosym = VDSOSYM $@
+define cmd_vdsosym
+ $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@
+endef
+
+include/generated/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE
+ $(call if_changed,vdsosym)
+
+
+
+# Assembly rules for the .S files
+
+sigreturn.o : sigreturn.S
+ $(call if_changed_dep,vdsoas)
+
+note.o : note.S
+ $(call if_changed_dep,vdsoas)
+
+datapage.o : datapage.S
+ $(call if_changed_dep,vdsoas)
+
+gettimeofday.o : gettimeofday.c FORCE
+ $(call if_changed_dep,vdsocc)
+
+# Actual build commands
+quiet_cmd_vdsold = VDSOL $@
+ cmd_vdsold = $(CC) $(c_flags) -Wl,-n -Wl,-T $^ -o $@
+quiet_cmd_vdsoas = VDSOA $@
+ cmd_vdsoas = $(CC) $(a_flags) -c -o $@ $<
+quiet_cmd_vdsocc = VDSOA $@
+ cmd_vdsocc = $(CC) $(c_flags) -c -o $@ $<
+
+# Install commands for the unstripped file
+quiet_cmd_vdso_install = INSTALL $@
+ cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@
+
+vdso.so: $(obj)/vdso.so.dbg
+ @mkdir -p $(MODLIB)/vdso
+ $(call cmd,vdso_install)
+
+vdso_install: vdso.so
diff --git a/arch/nds32/kernel/vdso/datapage.S b/arch/nds32/kernel/vdso/datapage.S
new file mode 100644
index 000000000000..4a62c3cab1c8
--- /dev/null
+++ b/arch/nds32/kernel/vdso/datapage.S
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/page.h>
+
+ENTRY(__get_timerpage)
+ sethi $r0, hi20(. + PAGE_SIZE + 8)
+ ori $r0, $r0, lo12(. + PAGE_SIZE + 4)
+ mfusr $r1, $pc
+ sub $r0, $r1, $r0
+ ret
+ENDPROC(__get_timerpage)
+
+ENTRY(__get_datapage)
+ sethi $r0, hi20(. + 2*PAGE_SIZE + 8)
+ ori $r0, $r0, lo12(. + 2*PAGE_SIZE + 4)
+ mfusr $r1, $pc
+ sub $r0, $r1, $r0
+ ret
+ENDPROC(__get_datapage)
diff --git a/arch/nds32/kernel/vdso/gen_vdso_offsets.sh b/arch/nds32/kernel/vdso/gen_vdso_offsets.sh
new file mode 100755
index 000000000000..01924ff071ad
--- /dev/null
+++ b/arch/nds32/kernel/vdso/gen_vdso_offsets.sh
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+#
+# Match symbols in the DSO that look like VDSO_*; produce a header file
+# of constant offsets into the shared object.
+#
+# Doing this inside the Makefile will break the $(filter-out) function,
+# causing Kbuild to rebuild the vdso-offsets header file every time.
+#
+# Author: Will Deacon <will.deacon@arm.com
+#
+
+LC_ALL=C
+sed -n -e 's/^00*/0/' -e \
+'s/^\([0-9a-fA-F]*\) . VDSO_\([a-zA-Z0-9_]*\)$/\#define vdso_offset_\2\t0x\1/p'
diff --git a/arch/nds32/kernel/vdso/gettimeofday.c b/arch/nds32/kernel/vdso/gettimeofday.c
new file mode 100644
index 000000000000..038721af40e3
--- /dev/null
+++ b/arch/nds32/kernel/vdso/gettimeofday.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/compiler.h>
+#include <linux/hrtimer.h>
+#include <linux/time.h>
+#include <asm/io.h>
+#include <asm/barrier.h>
+#include <asm/bug.h>
+#include <asm/page.h>
+#include <asm/unistd.h>
+#include <asm/vdso_datapage.h>
+#include <asm/vdso_timer_info.h>
+#include <asm/asm-offsets.h>
+
+#define X(x) #x
+#define Y(x) X(x)
+
+extern struct vdso_data *__get_datapage(void);
+extern struct vdso_data *__get_timerpage(void);
+
+static notrace unsigned int __vdso_read_begin(const struct vdso_data *vdata)
+{
+ u32 seq;
+repeat:
+ seq = READ_ONCE(vdata->seq_count);
+ if (seq & 1) {
+ cpu_relax();
+ goto repeat;
+ }
+ return seq;
+}
+
+static notrace unsigned int vdso_read_begin(const struct vdso_data *vdata)
+{
+ unsigned int seq;
+
+ seq = __vdso_read_begin(vdata);
+
+ smp_rmb(); /* Pairs with smp_wmb in vdso_write_end */
+ return seq;
+}
+
+static notrace int vdso_read_retry(const struct vdso_data *vdata, u32 start)
+{
+ smp_rmb(); /* Pairs with smp_wmb in vdso_write_begin */
+ return vdata->seq_count != start;
+}
+
+static notrace long clock_gettime_fallback(clockid_t _clkid,
+ struct timespec *_ts)
+{
+ register struct timespec *ts asm("$r1") = _ts;
+ register clockid_t clkid asm("$r0") = _clkid;
+ register long ret asm("$r0");
+
+ asm volatile ("movi $r15, %3\n"
+ "syscall 0x0\n"
+ :"=r" (ret)
+ :"r"(clkid), "r"(ts), "i"(__NR_clock_gettime)
+ :"$r15", "memory");
+
+ return ret;
+}
+
+static notrace int do_realtime_coarse(struct timespec *ts,
+ struct vdso_data *vdata)
+{
+ u32 seq;
+
+ do {
+ seq = vdso_read_begin(vdata);
+
+ ts->tv_sec = vdata->xtime_coarse_sec;
+ ts->tv_nsec = vdata->xtime_coarse_nsec;
+
+ } while (vdso_read_retry(vdata, seq));
+ return 0;
+}
+
+static notrace int do_monotonic_coarse(struct timespec *ts,
+ struct vdso_data *vdata)
+{
+ struct timespec tomono;
+ u32 seq;
+
+ do {
+ seq = vdso_read_begin(vdata);
+
+ ts->tv_sec = vdata->xtime_coarse_sec;
+ ts->tv_nsec = vdata->xtime_coarse_nsec;
+
+ tomono.tv_sec = vdata->wtm_clock_sec;
+ tomono.tv_nsec = vdata->wtm_clock_nsec;
+
+ } while (vdso_read_retry(vdata, seq));
+
+ ts->tv_sec += tomono.tv_sec;
+ timespec_add_ns(ts, tomono.tv_nsec);
+ return 0;
+}
+
+static notrace inline u64 vgetsns(struct vdso_data *vdso)
+{
+ u32 cycle_now;
+ u32 cycle_delta;
+ u32 *timer_cycle_base;
+
+ timer_cycle_base =
+ (u32 *) ((char *)__get_timerpage() + vdso->cycle_count_offset);
+ cycle_now = readl_relaxed(timer_cycle_base);
+ if (true == vdso->cycle_count_down)
+ cycle_now = ~(*timer_cycle_base);
+ cycle_delta = cycle_now - (u32) vdso->cs_cycle_last;
+ return ((u64) cycle_delta & vdso->cs_mask) * vdso->cs_mult;
+}
+
+static notrace int do_realtime(struct timespec *ts, struct vdso_data *vdata)
+{
+ unsigned count;
+ u64 ns;
+ do {
+ count = vdso_read_begin(vdata);
+ ts->tv_sec = vdata->xtime_clock_sec;
+ ns = vdata->xtime_clock_nsec;
+ ns += vgetsns(vdata);
+ ns >>= vdata->cs_shift;
+ } while (vdso_read_retry(vdata, count));
+
+ ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
+ ts->tv_nsec = ns;
+
+ return 0;
+}
+
+static notrace int do_monotonic(struct timespec *ts, struct vdso_data *vdata)
+{
+ struct timespec tomono;
+ u64 nsecs;
+ u32 seq;
+
+ do {
+ seq = vdso_read_begin(vdata);
+
+ ts->tv_sec = vdata->xtime_clock_sec;
+ nsecs = vdata->xtime_clock_nsec;
+ nsecs += vgetsns(vdata);
+ nsecs >>= vdata->cs_shift;
+
+ tomono.tv_sec = vdata->wtm_clock_sec;
+ tomono.tv_nsec = vdata->wtm_clock_nsec;
+
+ } while (vdso_read_retry(vdata, seq));
+
+ ts->tv_sec += tomono.tv_sec;
+ ts->tv_nsec = 0;
+ timespec_add_ns(ts, nsecs + tomono.tv_nsec);
+ return 0;
+}
+
+notrace int __vdso_clock_gettime(clockid_t clkid, struct timespec *ts)
+{
+ struct vdso_data *vdata;
+ int ret = -1;
+
+ vdata = __get_datapage();
+ if (vdata->cycle_count_offset == EMPTY_REG_OFFSET)
+ return clock_gettime_fallback(clkid, ts);
+
+ switch (clkid) {
+ case CLOCK_REALTIME_COARSE:
+ ret = do_realtime_coarse(ts, vdata);
+ break;
+ case CLOCK_MONOTONIC_COARSE:
+ ret = do_monotonic_coarse(ts, vdata);
+ break;
+ case CLOCK_REALTIME:
+ ret = do_realtime(ts, vdata);
+ break;
+ case CLOCK_MONOTONIC:
+ ret = do_monotonic(ts, vdata);
+ break;
+ default:
+ break;
+ }
+
+ if (ret)
+ ret = clock_gettime_fallback(clkid, ts);
+
+ return ret;
+}
+
+static notrace int clock_getres_fallback(clockid_t _clk_id,
+ struct timespec *_res)
+{
+ register clockid_t clk_id asm("$r0") = _clk_id;
+ register struct timespec *res asm("$r1") = _res;
+ register int ret asm("$r0");
+
+ asm volatile ("movi $r15, %3\n"
+ "syscall 0x0\n"
+ :"=r" (ret)
+ :"r"(clk_id), "r"(res), "i"(__NR_clock_getres)
+ :"$r15", "memory");
+
+ return ret;
+}
+
+notrace int __vdso_clock_getres(clockid_t clk_id, struct timespec *res)
+{
+ if (res == NULL)
+ return 0;
+ switch (clk_id) {
+ case CLOCK_REALTIME:
+ case CLOCK_MONOTONIC:
+ case CLOCK_MONOTONIC_RAW:
+ res->tv_sec = 0;
+ res->tv_nsec = CLOCK_REALTIME_RES;
+ break;
+ case CLOCK_REALTIME_COARSE:
+ case CLOCK_MONOTONIC_COARSE:
+ res->tv_sec = 0;
+ res->tv_nsec = CLOCK_COARSE_RES;
+ break;
+ default:
+ return clock_getres_fallback(clk_id, res);
+ }
+ return 0;
+}
+
+static notrace inline int gettimeofday_fallback(struct timeval *_tv,
+ struct timezone *_tz)
+{
+ register struct timeval *tv asm("$r0") = _tv;
+ register struct timezone *tz asm("$r1") = _tz;
+ register int ret asm("$r0");
+
+ asm volatile ("movi $r15, %3\n"
+ "syscall 0x0\n"
+ :"=r" (ret)
+ :"r"(tv), "r"(tz), "i"(__NR_gettimeofday)
+ :"$r15", "memory");
+
+ return ret;
+}
+
+notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
+{
+ struct timespec ts;
+ struct vdso_data *vdata;
+ int ret;
+
+ vdata = __get_datapage();
+
+ if (vdata->cycle_count_offset == EMPTY_REG_OFFSET)
+ return gettimeofday_fallback(tv, tz);
+
+ ret = do_realtime(&ts, vdata);
+
+ if (tv) {
+ tv->tv_sec = ts.tv_sec;
+ tv->tv_usec = ts.tv_nsec / 1000;
+ }
+ if (tz) {
+ tz->tz_minuteswest = vdata->tz_minuteswest;
+ tz->tz_dsttime = vdata->tz_dsttime;
+ }
+
+ return ret;
+}
diff --git a/arch/nds32/kernel/vdso/note.S b/arch/nds32/kernel/vdso/note.S
new file mode 100644
index 000000000000..0aeaa19b05f0
--- /dev/null
+++ b/arch/nds32/kernel/vdso/note.S
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/uts.h>
+#include <linux/version.h>
+#include <linux/elfnote.h>
+
+ELFNOTE_START(Linux, 0, "a")
+ .long LINUX_VERSION_CODE
+ELFNOTE_END
diff --git a/arch/nds32/kernel/vdso/sigreturn.S b/arch/nds32/kernel/vdso/sigreturn.S
new file mode 100644
index 000000000000..67e4d1d1612a
--- /dev/null
+++ b/arch/nds32/kernel/vdso/sigreturn.S
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+
+ .text
+
+ENTRY(__kernel_rt_sigreturn)
+ .cfi_startproc
+ movi $r15, __NR_rt_sigreturn
+ /*
+ * The SWID of syscall should be __NR_rt_sigreturn to synchronize
+ * the unwinding scheme in gcc
+ */
+ syscall __NR_rt_sigreturn
+ .cfi_endproc
+ENDPROC(__kernel_rt_sigreturn)
diff --git a/arch/nds32/kernel/vdso/vdso.S b/arch/nds32/kernel/vdso/vdso.S
new file mode 100644
index 000000000000..16737c11e55b
--- /dev/null
+++ b/arch/nds32/kernel/vdso/vdso.S
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2012 ARM Limited
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/const.h>
+#include <asm/page.h>
+
+ .globl vdso_start, vdso_end
+ .section .rodata
+ .balign PAGE_SIZE
+vdso_start:
+ .incbin "arch/nds32/kernel/vdso/vdso.so"
+ .balign PAGE_SIZE
+vdso_end:
+
+ .previous
diff --git a/arch/nds32/kernel/vdso/vdso.lds.S b/arch/nds32/kernel/vdso/vdso.lds.S
new file mode 100644
index 000000000000..1f2b16004594
--- /dev/null
+++ b/arch/nds32/kernel/vdso/vdso.lds.S
@@ -0,0 +1,75 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ */
+
+
+#include <linux/const.h>
+#include <asm/page.h>
+#include <asm/vdso.h>
+
+OUTPUT_ARCH(nds32)
+
+SECTIONS
+{
+ . = SIZEOF_HEADERS;
+
+ .hash : { *(.hash) } :text
+ .gnu.hash : { *(.gnu.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+
+ .note : { *(.note.*) } :text :note
+
+
+ .text : { *(.text*) } :text
+
+ .eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr
+ .eh_frame : { KEEP (*(.eh_frame)) } :text
+
+ .dynamic : { *(.dynamic) } :text :dynamic
+
+ .rodata : { *(.rodata*) } :text
+
+
+ /DISCARD/ : {
+ *(.note.GNU-stack)
+ *(.data .data.* .gnu.linkonce.d.* .sdata*)
+ *(.bss .sbss .dynbss .dynsbss)
+ }
+}
+
+/*
+ * We must supply the ELF program headers explicitly to get just one
+ * PT_LOAD segment, and set the flags explicitly to make segments read-only.
+ */
+PHDRS
+{
+ text PT_LOAD FLAGS(5) FILEHDR PHDRS; /* PF_R|PF_X */
+ dynamic PT_DYNAMIC FLAGS(4); /* PF_R */
+ note PT_NOTE FLAGS(4); /* PF_R */
+ eh_frame_hdr PT_GNU_EH_FRAME;
+}
+
+/*
+ * This controls what symbols we export from the DSO.
+ */
+VERSION
+{
+ LINUX_4 {
+ global:
+ __kernel_rt_sigreturn;
+ __vdso_gettimeofday;
+ __vdso_clock_getres;
+ __vdso_clock_gettime;
+ local: *;
+ };
+}
+
+/*
+ * Make the rt_sigreturn code visible to the kernel.
+ */
+VDSO_rt_sigtramp = __kernel_rt_sigreturn;
diff --git a/arch/nds32/kernel/vmlinux.lds.S b/arch/nds32/kernel/vmlinux.lds.S
new file mode 100644
index 000000000000..288313b886ef
--- /dev/null
+++ b/arch/nds32/kernel/vmlinux.lds.S
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <asm/page.h>
+#include <asm/thread_info.h>
+#include <asm/cache.h>
+#include <asm/memory.h>
+
+#define LOAD_OFFSET (PAGE_OFFSET - PHYS_OFFSET)
+#include <asm-generic/vmlinux.lds.h>
+
+OUTPUT_ARCH(nds32)
+ENTRY(_stext_lma)
+jiffies = jiffies_64;
+
+SECTIONS
+{
+ _stext_lma = TEXTADDR - LOAD_OFFSET;
+ . = TEXTADDR;
+ __init_begin = .;
+ HEAD_TEXT_SECTION
+ INIT_TEXT_SECTION(PAGE_SIZE)
+ INIT_DATA_SECTION(16)
+ PERCPU_SECTION(L1_CACHE_BYTES)
+ __init_end = .;
+
+ . = ALIGN(PAGE_SIZE);
+ _stext = .;
+ /* Real text segment */
+ .text : AT(ADDR(.text) - LOAD_OFFSET) {
+ _text = .; /* Text and read-only data */
+ TEXT_TEXT
+ SCHED_TEXT
+ CPUIDLE_TEXT
+ LOCK_TEXT
+ KPROBES_TEXT
+ IRQENTRY_TEXT
+ *(.fixup)
+ }
+
+ _etext = .; /* End of text and rodata section */
+
+ _sdata = .;
+ RO_DATA_SECTION(PAGE_SIZE)
+ RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
+ _edata = .;
+
+ EXCEPTION_TABLE(16)
+ NOTES
+ BSS_SECTION(4, 4, 4)
+ _end = .;
+
+ STABS_DEBUG
+ DWARF_DEBUG
+
+ DISCARDS
+}
diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile
new file mode 100644
index 000000000000..0f9840103f03
--- /dev/null
+++ b/arch/nds32/lib/Makefile
@@ -0,0 +1,3 @@
+lib-y := copy_page.o memcpy.o memmove.o \
+ memset.o memzero.o \
+ copy_from_user.o copy_to_user.o clear_user.o
diff --git a/arch/nds32/lib/clear_user.S b/arch/nds32/lib/clear_user.S
new file mode 100644
index 000000000000..805dfcd25bf8
--- /dev/null
+++ b/arch/nds32/lib/clear_user.S
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+
+/* Prototype: int __arch_clear_user(void *addr, size_t sz)
+ * Purpose : clear some user memory
+ * Params : addr - user memory address to clear
+ * : sz - number of bytes to clear
+ * Returns : number of bytes NOT cleared
+ */
+ .text
+ .align 5
+ENTRY(__arch_clear_user)
+ add $r5, $r0, $r1
+ beqz $r1, clear_exit
+ xor $p1, $p1, $p1 ! Use $p1=0 to clear mem
+ srli $p0, $r1, #2 ! $p0 = number of word to clear
+ andi $r1, $r1, #3 ! Bytes less than a word to copy
+ beqz $p0, byte_clear ! Only less than a word to clear
+word_clear:
+USER( smw.bim,$p1, [$r0], $p1) ! Clear the word
+ addi $p0, $p0, #-1 ! Decrease word count
+ bnez $p0, word_clear ! Continue looping to clear all words
+ beqz $r1, clear_exit ! No left bytes to copy
+byte_clear:
+USER( sbi.bi, $p1, [$r0], #1) ! Clear the byte
+ addi $r1, $r1, #-1 ! Decrease byte count
+ bnez $r1, byte_clear ! Continue looping to clear all left bytes
+clear_exit:
+ move $r0, $r1 ! Set return value
+ ret
+
+ .section .fixup,"ax"
+ .align 0
+9001:
+ sub $r0, $r5, $r0 ! Bytes left to copy
+ ret
+ .previous
+ENDPROC(__arch_clear_user)
diff --git a/arch/nds32/lib/copy_from_user.S b/arch/nds32/lib/copy_from_user.S
new file mode 100644
index 000000000000..ad1857b20067
--- /dev/null
+++ b/arch/nds32/lib/copy_from_user.S
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+
+.macro lbi1 dst, addr, adj
+USER( lbi.bi, \dst, [\addr], \adj)
+.endm
+
+.macro sbi1 src, addr, adj
+sbi.bi \src, [\addr], \adj
+.endm
+
+.macro lmw1 start_reg, addr, end_reg
+USER( lmw.bim, \start_reg, [\addr], \end_reg)
+.endm
+
+.macro smw1 start_reg, addr, end_reg
+smw.bim \start_reg, [\addr], \end_reg
+.endm
+
+
+/* Prototype: int __arch_copy_from_user(void *to, const char *from, size_t n)
+ * Purpose : copy a block from user memory to kernel memory
+ * Params : to - kernel memory
+ * : from - user memory
+ * : n - number of bytes to copy
+ * Returns : Number of bytes NOT copied.
+ */
+
+.text
+ENTRY(__arch_copy_from_user)
+ add $r5, $r0, $r2
+#include "copy_template.S"
+ move $r0, $r2
+ ret
+.section .fixup,"ax"
+.align 2
+9001:
+ sub $r0, $r5, $r0
+ ret
+.previous
+ENDPROC(__arch_copy_from_user)
diff --git a/arch/nds32/lib/copy_page.S b/arch/nds32/lib/copy_page.S
new file mode 100644
index 000000000000..4a2ff85f17ee
--- /dev/null
+++ b/arch/nds32/lib/copy_page.S
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/page.h>
+
+ .text
+ENTRY(copy_page)
+ pushm $r2, $r10
+ movi $r2, PAGE_SIZE >> 5
+.Lcopy_loop:
+ lmw.bim $r3, [$r1], $r10
+ smw.bim $r3, [$r0], $r10
+ subi45 $r2, #1
+ bnez38 $r2, .Lcopy_loop
+ popm $r2, $r10
+ ret
+ENDPROC(copy_page)
+
+ENTRY(clear_page)
+ pushm $r1, $r9
+ movi $r1, PAGE_SIZE >> 5
+ movi55 $r2, #0
+ movi55 $r3, #0
+ movi55 $r4, #0
+ movi55 $r5, #0
+ movi55 $r6, #0
+ movi55 $r7, #0
+ movi55 $r8, #0
+ movi55 $r9, #0
+.Lclear_loop:
+ smw.bim $r2, [$r0], $r9
+ subi45 $r1, #1
+ bnez38 $r1, .Lclear_loop
+ popm $r1, $r9
+ ret
+ENDPROC(clear_page)
diff --git a/arch/nds32/lib/copy_template.S b/arch/nds32/lib/copy_template.S
new file mode 100644
index 000000000000..3a9a2de468c2
--- /dev/null
+++ b/arch/nds32/lib/copy_template.S
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+
+ beq $r1, $r0, quit_memcpy
+ beqz $r2, quit_memcpy
+ srli $r3, $r2, #5 ! check if len < cache-line size 32
+ beqz $r3, word_copy_entry
+ andi $r4, $r0, #0x3 ! check byte-align
+ beqz $r4, unalign_word_copy_entry
+
+ addi $r4, $r4,#-4
+ abs $r4, $r4 ! check how many un-align byte to copy
+ sub $r2, $r2, $r4 ! update $R2
+
+unalign_byte_copy:
+ lbi1 $r3, $r1, #1
+ addi $r4, $r4, #-1
+ sbi1 $r3, $r0, #1
+ bnez $r4, unalign_byte_copy
+ beqz $r2, quit_memcpy
+
+unalign_word_copy_entry:
+ andi $r3, $r0, 0x1f ! check cache-line unaligncount
+ beqz $r3, cache_copy
+
+ addi $r3, $r3, #-32
+ abs $r3, $r3
+ sub $r2, $r2, $r3 ! update $R2
+
+unalign_word_copy:
+ lmw1 $r4, $r1, $r4
+ addi $r3, $r3, #-4
+ smw1 $r4, $r0, $r4
+ bnez $r3, unalign_word_copy
+ beqz $r2, quit_memcpy
+
+ addi $r3, $r2, #-32 ! to check $r2< cache_line , than go to word_copy
+ bltz $r3, word_copy_entry
+cache_copy:
+ srli $r3, $r2, #5
+ beqz $r3, word_copy_entry
+3:
+ lmw1 $r17, $r1, $r24
+ addi $r3, $r3, #-1
+ smw1 $r17, $r0, $r24
+ bnez $r3, 3b
+
+word_copy_entry:
+ andi $r2, $r2, #31
+
+ beqz $r2, quit_memcpy
+5:
+ srli $r3, $r2, #2
+ beqz $r3, byte_copy
+word_copy:
+ lmw1 $r4, $r1, $r4
+ addi $r3, $r3, #-1
+ smw1 $r4, $r0, $r4
+ bnez $r3, word_copy
+ andi $r2, $r2, #3
+ beqz $r2, quit_memcpy
+byte_copy:
+ lbi1 $r3, $r1, #1
+ addi $r2, $r2, #-1
+
+ sbi1 $r3, $r0, #1
+ bnez $r2, byte_copy
+quit_memcpy:
diff --git a/arch/nds32/lib/copy_to_user.S b/arch/nds32/lib/copy_to_user.S
new file mode 100644
index 000000000000..3230044dcfb8
--- /dev/null
+++ b/arch/nds32/lib/copy_to_user.S
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+
+.macro lbi1 dst, addr, adj
+lbi.bi \dst, [\addr], \adj
+.endm
+
+.macro sbi1 src, addr, adj
+USER( sbi.bi, \src, [\addr], \adj)
+.endm
+
+.macro lmw1 start_reg, addr, end_reg
+lmw.bim \start_reg, [\addr], \end_reg
+.endm
+
+.macro smw1 start_reg, addr, end_reg
+USER( smw.bim, \start_reg, [\addr], \end_reg)
+.endm
+
+
+/* Prototype: int __arch_copy_to_user(void *to, const char *from, size_t n)
+ * Purpose : copy a block to user memory from kernel memory
+ * Params : to - user memory
+ * : from - kernel memory
+ * : n - number of bytes to copy
+ * Returns : Number of bytes NOT copied.
+ */
+
+.text
+ENTRY(__arch_copy_to_user)
+ add $r5, $r0, $r2
+#include "copy_template.S"
+ move $r0, $r2
+ ret
+.section .fixup,"ax"
+.align 2
+9001:
+ sub $r0, $r5, $r0
+ ret
+.previous
+ENDPROC(__arch_copy_to_user)
diff --git a/arch/nds32/lib/memcpy.S b/arch/nds32/lib/memcpy.S
new file mode 100644
index 000000000000..a2345ea721e4
--- /dev/null
+++ b/arch/nds32/lib/memcpy.S
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+
+
+.macro lbi1 dst, addr, adj
+lbi.bi \dst, [\addr], \adj
+.endm
+
+.macro sbi1 src, addr, adj
+sbi.bi \src, [\addr], \adj
+.endm
+
+.macro lmw1 start_reg, addr, end_reg
+lmw.bim \start_reg, [\addr], \end_reg
+.endm
+
+.macro smw1 start_reg, addr, end_reg
+smw.bim \start_reg, [\addr], \end_reg
+.endm
+
+.text
+ENTRY(memcpy)
+ move $r5, $r0
+#include "copy_template.S"
+ move $r0, $r5
+ ret
+
+ENDPROC(memcpy)
diff --git a/arch/nds32/lib/memmove.S b/arch/nds32/lib/memmove.S
new file mode 100644
index 000000000000..c823aada2271
--- /dev/null
+++ b/arch/nds32/lib/memmove.S
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+
+/*
+ void *memmove(void *dst, const void *src, int n);
+
+ dst: $r0
+ src: $r1
+ n : $r2
+ ret: $r0 - pointer to the memory area dst.
+*/
+ .text
+
+ENTRY(memmove)
+ move $r5, $r0 ! Set return value = det
+ beq $r0, $r1, exit_memcpy ! Exit when det = src
+ beqz $r2, exit_memcpy ! Exit when n = 0
+ pushm $t0, $t1 ! Save reg
+ srli $p1, $r2, #2 ! $p1 is how many words to copy
+
+ ! Avoid data lost when memory overlap
+ ! Copy data reversely when src < dst
+ slt $p0, $r0, $r1 ! check if $r0 < $r1
+ beqz $p0, do_reverse ! branch if dst > src
+
+ ! No reverse, dst < src
+ andi $r2, $r2, #3 ! How many bytes are less than a word
+ li $t0, #1 ! Determining copy direction in byte_cpy
+ beqz $p1, byte_cpy ! When n is less than a word
+
+word_cpy:
+ lmw.bim $p0, [$r1], $p0 ! Read a word from src
+ addi $p1, $p1, #-1 ! How many words left to copy
+ smw.bim $p0, [$r0], $p0 ! Copy the word to det
+ bnez $p1, word_cpy ! If remained words > 0
+ beqz $r2, end_memcpy ! No left bytes to copy
+ b byte_cpy
+
+do_reverse:
+ add $r0, $r0, $r2 ! Start with the end of $r0
+ add $r1, $r1, $r2 ! Start with the end of $r1
+ andi $r2, $r2, #3 ! How many bytes are less than a word
+ li $t0, #-1 ! Determining copy direction in byte_cpy
+ beqz $p1, reverse_byte_cpy ! When n is less than a word
+
+reverse_word_cpy:
+ lmw.adm $p0, [$r1], $p0 ! Read a word from src
+ addi $p1, $p1, #-1 ! How many words left to copy
+ smw.adm $p0, [$r0], $p0 ! Copy the word to det
+ bnez $p1, reverse_word_cpy ! If remained words > 0
+ beqz $r2, end_memcpy ! No left bytes to copy
+
+reverse_byte_cpy:
+ addi $r0, $r0, #-1
+ addi $r1, $r1, #-1
+byte_cpy: ! Less than 4 bytes to copy now
+ lb.bi $p0, [$r1], $t0 ! Read a byte from src
+ addi $r2, $r2, #-1 ! How many bytes left to copy
+ sb.bi $p0, [$r0], $t0 ! copy the byte to det
+ bnez $r2, byte_cpy ! If remained bytes > 0
+
+end_memcpy:
+ popm $t0, $t1
+exit_memcpy:
+ move $r0, $r5
+ ret
+
+ENDPROC(memmove)
diff --git a/arch/nds32/lib/memset.S b/arch/nds32/lib/memset.S
new file mode 100644
index 000000000000..193cb6ce21a9
--- /dev/null
+++ b/arch/nds32/lib/memset.S
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+
+ .text
+ENTRY(memset)
+ move $r5, $r0 ! Return value
+ beqz $r2, end_memset ! Exit when len = 0
+ srli $p1, $r2, 2 ! $p1 is how many words to copy
+ andi $r2, $r2, 3 ! How many bytes are less than a word
+ beqz $p1, byte_set ! When n is less than a word
+
+ ! set $r1 from ??????ab to abababab
+ andi $r1, $r1, #0x00ff ! $r1 = 000000ab
+ slli $p0, $r1, #8 ! $p0 = 0000ab00
+ or $r1, $r1, $p0 ! $r1 = 0000abab
+ slli $p0, $r1, #16 ! $p0 = abab0000
+ or $r1, $r1, $p0 ! $r1 = abababab
+word_set:
+ addi $p1, $p1, #-1 ! How many words left to copy
+ smw.bim $r1, [$r0], $r1 ! Copy the word to det
+ bnez $p1, word_set ! Still words to set, continue looping
+ beqz $r2, end_memset ! No left byte to set
+byte_set: ! Less than 4 bytes left to set
+ addi $r2, $r2, #-1 ! Decrease len by 1
+ sbi.bi $r1, [$r0], #1 ! Set data of the next byte to $r1
+ bnez $r2, byte_set ! Still bytes left to set
+end_memset:
+ move $r0, $r5
+ ret
+
+ENDPROC(memset)
diff --git a/arch/nds32/lib/memzero.S b/arch/nds32/lib/memzero.S
new file mode 100644
index 000000000000..f055972c9343
--- /dev/null
+++ b/arch/nds32/lib/memzero.S
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/linkage.h>
+
+ .text
+ENTRY(memzero)
+ beqz $r1, 1f
+ push $lp
+ move $r2, $r1
+ move $r1, #0
+ push $r0
+ bal memset
+ pop $r0
+ pop $lp
+1:
+ ret
+ENDPROC(memzero)
diff --git a/arch/nds32/mm/Makefile b/arch/nds32/mm/Makefile
new file mode 100644
index 000000000000..6b6855852223
--- /dev/null
+++ b/arch/nds32/mm/Makefile
@@ -0,0 +1,7 @@
+obj-y := extable.o tlb.o \
+ fault.o init.o ioremap.o mmap.o \
+ mm-nds32.o cacheflush.o proc.o
+
+obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o
+obj-$(CONFIG_HIGHMEM) += highmem.o
+CFLAGS_proc-n13.o += -fomit-frame-pointer
diff --git a/arch/nds32/mm/alignment.c b/arch/nds32/mm/alignment.c
new file mode 100644
index 000000000000..b96a01b10ca7
--- /dev/null
+++ b/arch/nds32/mm/alignment.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/proc_fs.h>
+#include <linux/uaccess.h>
+#include <linux/sysctl.h>
+#include <asm/unaligned.h>
+
+#define DEBUG(enable, tagged, ...) \
+ do{ \
+ if (enable) { \
+ if (tagged) \
+ pr_warn("[ %30s() ] ", __func__); \
+ pr_warn(__VA_ARGS__); \
+ } \
+ } while (0)
+
+#define RT(inst) (((inst) >> 20) & 0x1FUL)
+#define RA(inst) (((inst) >> 15) & 0x1FUL)
+#define RB(inst) (((inst) >> 10) & 0x1FUL)
+#define SV(inst) (((inst) >> 8) & 0x3UL)
+#define IMM(inst) (((inst) >> 0) & 0x3FFFUL)
+
+#define RA3(inst) (((inst) >> 3) & 0x7UL)
+#define RT3(inst) (((inst) >> 6) & 0x7UL)
+#define IMM3U(inst) (((inst) >> 0) & 0x7UL)
+
+#define RA5(inst) (((inst) >> 0) & 0x1FUL)
+#define RT4(inst) (((inst) >> 5) & 0xFUL)
+
+#define __get8_data(val,addr,err) \
+ __asm__( \
+ "1: lbi.bi %1, [%2], #1\n" \
+ "2:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "3: movi %0, #1\n" \
+ " j 2b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 3b\n" \
+ " .popsection\n" \
+ : "=r" (err), "=&r" (val), "=r" (addr) \
+ : "0" (err), "2" (addr))
+
+#define get16_data(addr, val_ptr) \
+ do { \
+ unsigned int err = 0, v, a = addr; \
+ __get8_data(v,a,err); \
+ *val_ptr = v << 0; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 8; \
+ if (err) \
+ goto fault; \
+ *val_ptr = le16_to_cpu(*val_ptr); \
+ } while(0)
+
+#define get32_data(addr, val_ptr) \
+ do { \
+ unsigned int err = 0, v, a = addr; \
+ __get8_data(v,a,err); \
+ *val_ptr = v << 0; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 8; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 16; \
+ __get8_data(v,a,err); \
+ *val_ptr |= v << 24; \
+ if (err) \
+ goto fault; \
+ *val_ptr = le32_to_cpu(*val_ptr); \
+ } while(0)
+
+#define get_data(addr, val_ptr, len) \
+ if (len == 2) \
+ get16_data(addr, val_ptr); \
+ else \
+ get32_data(addr, val_ptr);
+
+#define set16_data(addr, val) \
+ do { \
+ unsigned int err = 0, *ptr = addr ; \
+ val = le32_to_cpu(val); \
+ __asm__( \
+ "1: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "2: sbi %2, [%1]\n" \
+ "3:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "4: movi %0, #1\n" \
+ " j 3b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 4b\n" \
+ " .long 2b, 4b\n" \
+ " .popsection\n" \
+ : "=r" (err), "+r" (ptr), "+r" (val) \
+ : "0" (err) \
+ ); \
+ if (err) \
+ goto fault; \
+ } while(0)
+
+#define set32_data(addr, val) \
+ do { \
+ unsigned int err = 0, *ptr = addr ; \
+ val = le32_to_cpu(val); \
+ __asm__( \
+ "1: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "2: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "3: sbi.bi %2, [%1], #1\n" \
+ " srli %2, %2, #8\n" \
+ "4: sbi %2, [%1]\n" \
+ "5:\n" \
+ " .pushsection .text.fixup,\"ax\"\n" \
+ " .align 2\n" \
+ "6: movi %0, #1\n" \
+ " j 5b\n" \
+ " .popsection\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 6b\n" \
+ " .long 2b, 6b\n" \
+ " .long 3b, 6b\n" \
+ " .long 4b, 6b\n" \
+ " .popsection\n" \
+ : "=r" (err), "+r" (ptr), "+r" (val) \
+ : "0" (err) \
+ ); \
+ if (err) \
+ goto fault; \
+ } while(0)
+#define set_data(addr, val, len) \
+ if (len == 2) \
+ set16_data(addr, val); \
+ else \
+ set32_data(addr, val);
+#define NDS32_16BIT_INSTRUCTION 0x80000000
+
+extern pte_t va_present(struct mm_struct *mm, unsigned long addr);
+extern pte_t va_kernel_present(unsigned long addr);
+extern int va_readable(struct pt_regs *regs, unsigned long addr);
+extern int va_writable(struct pt_regs *regs, unsigned long addr);
+
+int unalign_access_mode = 0, unalign_access_debug = 0;
+
+static inline unsigned long *idx_to_addr(struct pt_regs *regs, int idx)
+{
+ /* this should be consistent with ptrace.h */
+ if (idx >= 0 && idx <= 25) /* R0-R25 */
+ return &regs->uregs[0] + idx;
+ else if (idx >= 28 && idx <= 30) /* FP, GP, LP */
+ return &regs->fp + (idx - 28);
+ else if (idx == 31) /* SP */
+ return &regs->sp;
+ else
+ return NULL; /* cause a segfault */
+}
+
+static inline unsigned long get_inst(unsigned long addr)
+{
+ return be32_to_cpu(get_unaligned((u32 *) addr));
+}
+
+static inline unsigned long sign_extend(unsigned long val, int len)
+{
+ unsigned long ret = 0;
+ unsigned char *s, *t;
+ int i = 0;
+
+ val = cpu_to_le32(val);
+
+ s = (void *)&val;
+ t = (void *)&ret;
+
+ while (i++ < len)
+ *t++ = *s++;
+
+ if (((*(t - 1)) & 0x80) && (i < 4)) {
+
+ while (i++ <= 4)
+ *t++ = 0xff;
+ }
+
+ return le32_to_cpu(ret);
+}
+
+static inline int do_16(unsigned long inst, struct pt_regs *regs)
+{
+ int imm, regular, load, len, addr_mode, idx_mode;
+ unsigned long unaligned_addr, target_val, source_idx, target_idx,
+ shift = 0;
+ switch ((inst >> 9) & 0x3F) {
+
+ case 0x12: /* LHI333 */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x10: /* LWI333 */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x11: /* LWI333.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x1A: /* LWI450 */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 4;
+ addr_mode = 5;
+ idx_mode = 4;
+ break;
+ case 0x16: /* SHI333 */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 2;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x14: /* SWI333 */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x15: /* SWI333.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 4;
+ addr_mode = 3;
+ idx_mode = 3;
+ break;
+ case 0x1B: /* SWI450 */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 4;
+ addr_mode = 5;
+ idx_mode = 4;
+ break;
+
+ default:
+ return -EFAULT;
+ }
+
+ if (addr_mode == 3) {
+ unaligned_addr = *idx_to_addr(regs, RA3(inst));
+ source_idx = RA3(inst);
+ } else {
+ unaligned_addr = *idx_to_addr(regs, RA5(inst));
+ source_idx = RA5(inst);
+ }
+
+ if (idx_mode == 3)
+ target_idx = RT3(inst);
+ else
+ target_idx = RT4(inst);
+
+ if (imm)
+ shift = IMM3U(inst) * len;
+
+ if (regular)
+ unaligned_addr += shift;
+
+ if (load) {
+ if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ get_data(unaligned_addr, &target_val, len);
+ *idx_to_addr(regs, target_idx) = target_val;
+ } else {
+ if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
+ return -EACCES;
+ target_val = *idx_to_addr(regs, target_idx);
+ set_data((void *)unaligned_addr, target_val, len);
+ }
+
+ if (!regular)
+ *idx_to_addr(regs, source_idx) = unaligned_addr + shift;
+ regs->ipc += 2;
+
+ return 0;
+fault:
+ return -EACCES;
+}
+
+static inline int do_32(unsigned long inst, struct pt_regs *regs)
+{
+ int imm, regular, load, len, sign_ext;
+ unsigned long unaligned_addr, target_val, shift;
+
+ unaligned_addr = *idx_to_addr(regs, RA(inst));
+
+ switch ((inst >> 25) << 1) {
+
+ case 0x02: /* LHI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0A: /* LHI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x22: /* LHSI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x2A: /* LHSI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x04: /* LWI */
+ imm = 1;
+ regular = 1;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x0C: /* LWI.bi */
+ imm = 1;
+ regular = 0;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x12: /* SHI */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x1A: /* SHI.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x14: /* SWI */
+ imm = 1;
+ regular = 1;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x1C: /* SWI.bi */
+ imm = 1;
+ regular = 0;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+
+ default:
+ switch (inst & 0xff) {
+
+ case 0x01: /* LH */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x05: /* LH.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x11: /* LHS */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x15: /* LHS.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 2;
+ sign_ext = 1;
+ break;
+ case 0x02: /* LW */
+ imm = 0;
+ regular = 1;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x06: /* LW.bi */
+ imm = 0;
+ regular = 0;
+ load = 1;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x09: /* SH */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0D: /* SH.bi */
+ imm = 0;
+ regular = 0;
+ load = 0;
+ len = 2;
+ sign_ext = 0;
+ break;
+ case 0x0A: /* SW */
+ imm = 0;
+ regular = 1;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+ case 0x0E: /* SW.bi */
+ imm = 0;
+ regular = 0;
+ load = 0;
+ len = 4;
+ sign_ext = 0;
+ break;
+
+ default:
+ return -EFAULT;
+ }
+ }
+
+ if (imm)
+ shift = IMM(inst) * len;
+ else
+ shift = *idx_to_addr(regs, RB(inst)) << SV(inst);
+
+ if (regular)
+ unaligned_addr += shift;
+
+ if (load) {
+
+ if (!access_ok(VERIFY_READ, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ get_data(unaligned_addr, &target_val, len);
+
+ if (sign_ext)
+ *idx_to_addr(regs, RT(inst)) =
+ sign_extend(target_val, len);
+ else
+ *idx_to_addr(regs, RT(inst)) = target_val;
+ } else {
+
+ if (!access_ok(VERIFY_WRITE, (void *)unaligned_addr, len))
+ return -EACCES;
+
+ target_val = *idx_to_addr(regs, RT(inst));
+ set_data((void *)unaligned_addr, target_val, len);
+ }
+
+ if (!regular)
+ *idx_to_addr(regs, RA(inst)) = unaligned_addr + shift;
+
+ regs->ipc += 4;
+
+ return 0;
+fault:
+ return -EACCES;
+}
+
+int do_unaligned_access(unsigned long addr, struct pt_regs *regs)
+{
+ unsigned long inst;
+ int ret = -EFAULT;
+ mm_segment_t seg = get_fs();
+
+ inst = get_inst(regs->ipc);
+
+ DEBUG((unalign_access_debug > 0), 1,
+ "Faulting addr: 0x%08lx, pc: 0x%08lx [inst: 0x%08lx ]\n", addr,
+ regs->ipc, inst);
+
+ set_fs(USER_DS);
+
+ if (inst & NDS32_16BIT_INSTRUCTION)
+ ret = do_16((inst >> 16) & 0xffff, regs);
+ else
+ ret = do_32(inst, regs);
+ set_fs(seg);
+
+ return ret;
+}
+
+#ifdef CONFIG_PROC_FS
+
+static struct ctl_table alignment_tbl[3] = {
+ {
+ .procname = "enable",
+ .data = &unalign_access_mode,
+ .maxlen = sizeof(unalign_access_mode),
+ .mode = 0666,
+ .proc_handler = &proc_dointvec
+ }
+ ,
+ {
+ .procname = "debug_info",
+ .data = &unalign_access_debug,
+ .maxlen = sizeof(unalign_access_debug),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec
+ }
+ ,
+ {}
+};
+
+static struct ctl_table nds32_sysctl_table[2] = {
+ {
+ .procname = "unaligned_acess",
+ .mode = 0555,
+ .child = alignment_tbl},
+ {}
+};
+
+static struct ctl_path nds32_path[2] = {
+ {.procname = "nds32"},
+ {}
+};
+
+/*
+ * Initialize nds32 alignment-correction interface
+ */
+static int __init nds32_sysctl_init(void)
+{
+ register_sysctl_paths(nds32_path, nds32_sysctl_table);
+ return 0;
+}
+
+__initcall(nds32_sysctl_init);
+#endif /* CONFIG_PROC_FS */
diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
new file mode 100644
index 000000000000..6eb786a399a2
--- /dev/null
+++ b/arch/nds32/mm/cacheflush.c
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/pagemap.h>
+#include <linux/module.h>
+#include <asm/cacheflush.h>
+#include <asm/proc-fns.h>
+#include <asm/shmparam.h>
+#include <asm/cache_info.h>
+
+extern struct cache_info L1_cache_info[2];
+
+#ifndef CONFIG_CPU_CACHE_ALIASING
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+ pte_t * pte)
+{
+ struct page *page;
+ unsigned long pfn = pte_pfn(*pte);
+ unsigned long flags;
+
+ if (!pfn_valid(pfn))
+ return;
+
+ if (vma->vm_mm == current->active_mm) {
+ local_irq_save(flags);
+ __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
+ __nds32__tlbop_rwr(*pte);
+ __nds32__isb();
+ local_irq_restore(flags);
+ }
+ page = pfn_to_page(pfn);
+
+ if ((test_and_clear_bit(PG_dcache_dirty, &page->flags)) ||
+ (vma->vm_flags & VM_EXEC)) {
+
+ if (!PageHighMem(page)) {
+ cpu_cache_wbinval_page((unsigned long)
+ page_address(page),
+ vma->vm_flags & VM_EXEC);
+ } else {
+ unsigned long kaddr = (unsigned long)kmap_atomic(page);
+ cpu_cache_wbinval_page(kaddr, vma->vm_flags & VM_EXEC);
+ kunmap_atomic((void *)kaddr);
+ }
+ }
+}
+#else
+extern pte_t va_present(struct mm_struct *mm, unsigned long addr);
+
+static inline unsigned long aliasing(unsigned long addr, unsigned long page)
+{
+ return ((addr & PAGE_MASK) ^ page) & (SHMLBA - 1);
+}
+
+static inline unsigned long kremap0(unsigned long uaddr, unsigned long pa)
+{
+ unsigned long kaddr, pte;
+
+#define BASE_ADDR0 0xffffc000
+ kaddr = BASE_ADDR0 | (uaddr & L1_cache_info[DCACHE].aliasing_mask);
+ pte = (pa | PAGE_KERNEL);
+ __nds32__mtsr_dsb(kaddr, NDS32_SR_TLB_VPN);
+ __nds32__tlbop_rwlk(pte);
+ __nds32__isb();
+ return kaddr;
+}
+
+static inline void kunmap01(unsigned long kaddr)
+{
+ __nds32__tlbop_unlk(kaddr);
+ __nds32__tlbop_inv(kaddr);
+ __nds32__isb();
+}
+
+static inline unsigned long kremap1(unsigned long uaddr, unsigned long pa)
+{
+ unsigned long kaddr, pte;
+
+#define BASE_ADDR1 0xffff8000
+ kaddr = BASE_ADDR1 | (uaddr & L1_cache_info[DCACHE].aliasing_mask);
+ pte = (pa | PAGE_KERNEL);
+ __nds32__mtsr_dsb(kaddr, NDS32_SR_TLB_VPN);
+ __nds32__tlbop_rwlk(pte);
+ __nds32__isb();
+ return kaddr;
+}
+
+void flush_cache_mm(struct mm_struct *mm)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ cpu_dcache_wbinval_all();
+ cpu_icache_inval_all();
+ local_irq_restore(flags);
+}
+
+void flush_cache_dup_mm(struct mm_struct *mm)
+{
+}
+
+void flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ unsigned long flags;
+
+ if ((end - start) > 8 * PAGE_SIZE) {
+ cpu_dcache_wbinval_all();
+ if (vma->vm_flags & VM_EXEC)
+ cpu_icache_inval_all();
+ return;
+ }
+ local_irq_save(flags);
+ while (start < end) {
+ if (va_present(vma->vm_mm, start))
+ cpu_cache_wbinval_page(start, vma->vm_flags & VM_EXEC);
+ start += PAGE_SIZE;
+ }
+ local_irq_restore(flags);
+ return;
+}
+
+void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long addr, unsigned long pfn)
+{
+ unsigned long vto, flags;
+
+ local_irq_save(flags);
+ vto = kremap0(addr, pfn << PAGE_SHIFT);
+ cpu_cache_wbinval_page(vto, vma->vm_flags & VM_EXEC);
+ kunmap01(vto);
+ local_irq_restore(flags);
+}
+
+void flush_cache_vmap(unsigned long start, unsigned long end)
+{
+ cpu_dcache_wbinval_all();
+ cpu_icache_inval_all();
+}
+
+void flush_cache_vunmap(unsigned long start, unsigned long end)
+{
+ cpu_dcache_wbinval_all();
+ cpu_icache_inval_all();
+}
+
+void copy_user_highpage(struct page *to, struct page *from,
+ unsigned long vaddr, struct vm_area_struct *vma)
+{
+ unsigned long vto, vfrom, flags, kto, kfrom, pfrom, pto;
+ kto = ((unsigned long)page_address(to) & PAGE_MASK);
+ kfrom = ((unsigned long)page_address(from) & PAGE_MASK);
+ pto = page_to_phys(to);
+ pfrom = page_to_phys(from);
+
+ if (aliasing(vaddr, (unsigned long)kfrom))
+ cpu_dcache_wb_page((unsigned long)kfrom);
+ if (aliasing(vaddr, (unsigned long)kto))
+ cpu_dcache_inval_page((unsigned long)kto);
+ local_irq_save(flags);
+ vto = kremap0(vaddr, pto);
+ vfrom = kremap1(vaddr, pfrom);
+ copy_page((void *)vto, (void *)vfrom);
+ kunmap01(vfrom);
+ kunmap01(vto);
+ local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(copy_user_highpage);
+
+void clear_user_highpage(struct page *page, unsigned long vaddr)
+{
+ unsigned long vto, flags, kto;
+
+ kto = ((unsigned long)page_address(page) & PAGE_MASK);
+
+ local_irq_save(flags);
+ if (aliasing(kto, vaddr) && kto != 0) {
+ cpu_dcache_inval_page(kto);
+ cpu_icache_inval_page(kto);
+ }
+ vto = kremap0(vaddr, page_to_phys(page));
+ clear_page((void *)vto);
+ kunmap01(vto);
+ local_irq_restore(flags);
+}
+
+EXPORT_SYMBOL(clear_user_highpage);
+
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping;
+
+ mapping = page_mapping(page);
+ if (mapping && !mapping_mapped(mapping))
+ set_bit(PG_dcache_dirty, &page->flags);
+ else {
+ int i, pc;
+ unsigned long vto, kaddr, flags;
+ kaddr = (unsigned long)page_address(page);
+ cpu_dcache_wbinval_page(kaddr);
+ pc = CACHE_SET(DCACHE) * CACHE_LINE_SIZE(DCACHE) / PAGE_SIZE;
+ local_irq_save(flags);
+ for (i = 0; i < pc; i++) {
+ vto =
+ kremap0(kaddr + i * PAGE_SIZE, page_to_phys(page));
+ cpu_dcache_wbinval_page(vto);
+ kunmap01(vto);
+ }
+ local_irq_restore(flags);
+ }
+}
+
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+ unsigned long vaddr, void *dst, void *src, int len)
+{
+ unsigned long line_size, start, end, vto, flags;
+
+ local_irq_save(flags);
+ vto = kremap0(vaddr, page_to_phys(page));
+ dst = (void *)(vto | (vaddr & (PAGE_SIZE - 1)));
+ memcpy(dst, src, len);
+ if (vma->vm_flags & VM_EXEC) {
+ line_size = L1_cache_info[DCACHE].line_size;
+ start = (unsigned long)dst & ~(line_size - 1);
+ end =
+ ((unsigned long)dst + len + line_size - 1) & ~(line_size -
+ 1);
+ cpu_cache_wbinval_range(start, end, 1);
+ }
+ kunmap01(vto);
+ local_irq_restore(flags);
+}
+
+void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
+ unsigned long vaddr, void *dst, void *src, int len)
+{
+ unsigned long vto, flags;
+
+ local_irq_save(flags);
+ vto = kremap0(vaddr, page_to_phys(page));
+ src = (void *)(vto | (vaddr & (PAGE_SIZE - 1)));
+ memcpy(dst, src, len);
+ kunmap01(vto);
+ local_irq_restore(flags);
+}
+
+void flush_anon_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr)
+{
+ unsigned long flags;
+ if (!PageAnon(page))
+ return;
+
+ if (vma->vm_mm != current->active_mm)
+ return;
+
+ local_irq_save(flags);
+ if (vma->vm_flags & VM_EXEC)
+ cpu_icache_inval_page(vaddr & PAGE_MASK);
+ cpu_dcache_wbinval_page((unsigned long)page_address(page));
+ local_irq_restore(flags);
+}
+
+void flush_kernel_dcache_page(struct page *page)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ cpu_dcache_wbinval_page((unsigned long)page_address(page));
+ local_irq_restore(flags);
+}
+
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size, flags;
+ line_size = L1_cache_info[DCACHE].line_size;
+ start = start & ~(line_size - 1);
+ end = (end + line_size - 1) & ~(line_size - 1);
+ local_irq_save(flags);
+ cpu_cache_wbinval_range(start, end, 1);
+ local_irq_restore(flags);
+}
+
+void flush_icache_page(struct vm_area_struct *vma, struct page *page)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ cpu_cache_wbinval_page((unsigned long)page_address(page),
+ vma->vm_flags & VM_EXEC);
+ local_irq_restore(flags);
+}
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+ pte_t * pte)
+{
+ struct page *page;
+ unsigned long flags;
+ unsigned long pfn = pte_pfn(*pte);
+
+ if (!pfn_valid(pfn))
+ return;
+
+ if (vma->vm_mm == current->active_mm) {
+ local_irq_save(flags);
+ __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
+ __nds32__tlbop_rwr(*pte);
+ __nds32__isb();
+ local_irq_restore(flags);
+ }
+
+ page = pfn_to_page(pfn);
+ if (test_and_clear_bit(PG_dcache_dirty, &page->flags) ||
+ (vma->vm_flags & VM_EXEC)) {
+ local_irq_save(flags);
+ cpu_dcache_wbinval_page((unsigned long)page_address(page));
+ local_irq_restore(flags);
+ }
+}
+#endif
diff --git a/arch/metag/mm/extable.c b/arch/nds32/mm/extable.c
index 9b92d3ad7f9c..db7f0a7c8966 100644
--- a/arch/metag/mm/extable.c
+++ b/arch/nds32/mm/extable.c
@@ -1,15 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
#include <linux/extable.h>
#include <linux/uaccess.h>
int fixup_exception(struct pt_regs *regs)
{
const struct exception_table_entry *fixup;
- unsigned long pc = instruction_pointer(regs);
- fixup = search_exception_tables(pc);
+ fixup = search_exception_tables(instruction_pointer(regs));
if (fixup)
- regs->ctx.CurrPC = fixup->fixup;
+ regs->ipc = fixup->fixup;
return fixup != NULL;
}
diff --git a/arch/nds32/mm/fault.c b/arch/nds32/mm/fault.c
new file mode 100644
index 000000000000..3a246fb8098c
--- /dev/null
+++ b/arch/nds32/mm/fault.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/extable.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/ptrace.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/hardirq.h>
+#include <linux/uaccess.h>
+
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+
+extern void die(const char *str, struct pt_regs *regs, long err);
+
+/*
+ * This is useful to dump out the page tables associated with
+ * 'addr' in mm 'mm'.
+ */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{
+ pgd_t *pgd;
+ if (!mm)
+ mm = &init_mm;
+
+ pr_alert("pgd = %p\n", mm->pgd);
+ pgd = pgd_offset(mm, addr);
+ pr_alert("[%08lx] *pgd=%08lx", addr, pgd_val(*pgd));
+
+ do {
+ pmd_t *pmd;
+
+ if (pgd_none(*pgd))
+ break;
+
+ if (pgd_bad(*pgd)) {
+ pr_alert("(bad)");
+ break;
+ }
+
+ pmd = pmd_offset(pgd, addr);
+#if PTRS_PER_PMD != 1
+ pr_alert(", *pmd=%08lx", pmd_val(*pmd));
+#endif
+
+ if (pmd_none(*pmd))
+ break;
+
+ if (pmd_bad(*pmd)) {
+ pr_alert("(bad)");
+ break;
+ }
+
+ if (IS_ENABLED(CONFIG_HIGHMEM))
+ {
+ pte_t *pte;
+ /* We must not map this if we have highmem enabled */
+ pte = pte_offset_map(pmd, addr);
+ pr_alert(", *pte=%08lx", pte_val(*pte));
+ pte_unmap(pte);
+ }
+ } while (0);
+
+ pr_alert("\n");
+}
+
+void do_page_fault(unsigned long entry, unsigned long addr,
+ unsigned int error_code, struct pt_regs *regs)
+{
+ struct task_struct *tsk;
+ struct mm_struct *mm;
+ struct vm_area_struct *vma;
+ siginfo_t info;
+ int fault;
+ unsigned int mask = VM_READ | VM_WRITE | VM_EXEC;
+ unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+
+ error_code = error_code & (ITYPE_mskINST | ITYPE_mskETYPE);
+ tsk = current;
+ mm = tsk->mm;
+ info.si_code = SEGV_MAPERR;
+ /*
+ * We fault-in kernel-space virtual memory on-demand. The
+ * 'reference' page table is init_mm.pgd.
+ *
+ * NOTE! We MUST NOT take any locks for this case. We may
+ * be in an interrupt or a critical region, and should
+ * only copy the information from the master page table,
+ * nothing more.
+ */
+ if (addr >= TASK_SIZE) {
+ if (user_mode(regs))
+ goto bad_area_nosemaphore;
+
+ if (addr >= TASK_SIZE && addr < VMALLOC_END
+ && (entry == ENTRY_PTE_NOT_PRESENT))
+ goto vmalloc_fault;
+ else
+ goto no_context;
+ }
+
+ /* Send a signal to the task for handling the unalignment access. */
+ if (entry == ENTRY_GENERAL_EXCPETION
+ && error_code == ETYPE_ALIGNMENT_CHECK) {
+ if (user_mode(regs))
+ goto bad_area_nosemaphore;
+ else
+ goto no_context;
+ }
+
+ /*
+ * If we're in an interrupt or have no user
+ * context, we must not take the fault..
+ */
+ if (unlikely(faulthandler_disabled() || !mm))
+ goto no_context;
+
+ /*
+ * As per x86, we may deadlock here. However, since the kernel only
+ * validly references user space from well defined areas of the code,
+ * we can bug out early if this is from code which shouldn't.
+ */
+ if (unlikely(!down_read_trylock(&mm->mmap_sem))) {
+ if (!user_mode(regs) &&
+ !search_exception_tables(instruction_pointer(regs)))
+ goto no_context;
+retry:
+ down_read(&mm->mmap_sem);
+ } else {
+ /*
+ * The above down_read_trylock() might have succeeded in which
+ * case, we'll have missed the might_sleep() from down_read().
+ */
+ might_sleep();
+ if (IS_ENABLED(CONFIG_DEBUG_VM)) {
+ if (!user_mode(regs) &&
+ !search_exception_tables(instruction_pointer(regs)))
+ goto no_context;
+ }
+ }
+
+ vma = find_vma(mm, addr);
+
+ if (unlikely(!vma))
+ goto bad_area;
+
+ if (vma->vm_start <= addr)
+ goto good_area;
+
+ if (unlikely(!(vma->vm_flags & VM_GROWSDOWN)))
+ goto bad_area;
+
+ if (unlikely(expand_stack(vma, addr)))
+ goto bad_area;
+
+ /*
+ * Ok, we have a good vm_area for this memory access, so
+ * we can handle it..
+ */
+
+good_area:
+ info.si_code = SEGV_ACCERR;
+
+ /* first do some preliminary protection checks */
+ if (entry == ENTRY_PTE_NOT_PRESENT) {
+ if (error_code & ITYPE_mskINST)
+ mask = VM_EXEC;
+ else {
+ mask = VM_READ | VM_WRITE;
+ if (vma->vm_flags & VM_WRITE)
+ flags |= FAULT_FLAG_WRITE;
+ }
+ } else if (entry == ENTRY_TLB_MISC) {
+ switch (error_code & ITYPE_mskETYPE) {
+ case RD_PROT:
+ mask = VM_READ;
+ break;
+ case WRT_PROT:
+ mask = VM_WRITE;
+ flags |= FAULT_FLAG_WRITE;
+ break;
+ case NOEXEC:
+ mask = VM_EXEC;
+ break;
+ case PAGE_MODIFY:
+ mask = VM_WRITE;
+ flags |= FAULT_FLAG_WRITE;
+ break;
+ case ACC_BIT:
+ BUG();
+ default:
+ break;
+ }
+
+ }
+ if (!(vma->vm_flags & mask))
+ goto bad_area;
+
+ /*
+ * If for any reason at all we couldn't handle the fault,
+ * make sure we exit gracefully rather than endlessly redo
+ * the fault.
+ */
+
+ fault = handle_mm_fault(vma, addr, flags);
+
+ /*
+ * If we need to retry but a fatal signal is pending, handle the
+ * signal first. We do not need to release the mmap_sem because it
+ * would already be released in __lock_page_or_retry in mm/filemap.c.
+ */
+ if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) {
+ if (!user_mode(regs))
+ goto no_context;
+ return;
+ }
+
+ if (unlikely(fault & VM_FAULT_ERROR)) {
+ if (fault & VM_FAULT_OOM)
+ goto out_of_memory;
+ else if (fault & VM_FAULT_SIGBUS)
+ goto do_sigbus;
+ else
+ goto bad_area;
+ }
+
+ /*
+ * Major/minor page fault accounting is only done on the initial
+ * attempt. If we go through a retry, it is extremely likely that the
+ * page will be found in page cache at that point.
+ */
+ if (flags & FAULT_FLAG_ALLOW_RETRY) {
+ if (fault & VM_FAULT_MAJOR)
+ tsk->maj_flt++;
+ else
+ tsk->min_flt++;
+ if (fault & VM_FAULT_RETRY) {
+ flags &= ~FAULT_FLAG_ALLOW_RETRY;
+ flags |= FAULT_FLAG_TRIED;
+
+ /* No need to up_read(&mm->mmap_sem) as we would
+ * have already released it in __lock_page_or_retry
+ * in mm/filemap.c.
+ */
+ goto retry;
+ }
+ }
+
+ up_read(&mm->mmap_sem);
+ return;
+
+ /*
+ * Something tried to access memory that isn't in our memory map..
+ * Fix it, but check if it's kernel or user first..
+ */
+bad_area:
+ up_read(&mm->mmap_sem);
+
+bad_area_nosemaphore:
+
+ /* User mode accesses just cause a SIGSEGV */
+
+ if (user_mode(regs)) {
+ tsk->thread.address = addr;
+ tsk->thread.error_code = error_code;
+ tsk->thread.trap_no = entry;
+ info.si_signo = SIGSEGV;
+ info.si_errno = 0;
+ /* info.si_code has been set above */
+ info.si_addr = (void *)addr;
+ force_sig_info(SIGSEGV, &info, tsk);
+ return;
+ }
+
+no_context:
+
+ /* Are we prepared to handle this kernel fault?
+ *
+ * (The kernel has valid exception-points in the source
+ * when it acesses user-memory. When it fails in one
+ * of those points, we find it in a table and do a jump
+ * to some fixup code that loads an appropriate error
+ * code)
+ */
+
+ {
+ const struct exception_table_entry *entry;
+
+ if ((entry =
+ search_exception_tables(instruction_pointer(regs))) !=
+ NULL) {
+ /* Adjust the instruction pointer in the stackframe */
+ instruction_pointer(regs) = entry->fixup;
+ return;
+ }
+ }
+
+ /*
+ * Oops. The kernel tried to access some bad page. We'll have to
+ * terminate things with extreme prejudice.
+ */
+
+ bust_spinlocks(1);
+ pr_alert("Unable to handle kernel %s at virtual address %08lx\n",
+ (addr < PAGE_SIZE) ? "NULL pointer dereference" :
+ "paging request", addr);
+
+ show_pte(mm, addr);
+ die("Oops", regs, error_code);
+ bust_spinlocks(0);
+ do_exit(SIGKILL);
+
+ return;
+
+ /*
+ * We ran out of memory, or some other thing happened to us that made
+ * us unable to handle the page fault gracefully.
+ */
+
+out_of_memory:
+ up_read(&mm->mmap_sem);
+ if (!user_mode(regs))
+ goto no_context;
+ pagefault_out_of_memory();
+ return;
+
+do_sigbus:
+ up_read(&mm->mmap_sem);
+
+ /* Kernel mode? Handle exceptions or die */
+ if (!user_mode(regs))
+ goto no_context;
+
+ /*
+ * Send a sigbus
+ */
+ tsk->thread.address = addr;
+ tsk->thread.error_code = error_code;
+ tsk->thread.trap_no = entry;
+ info.si_signo = SIGBUS;
+ info.si_errno = 0;
+ info.si_code = BUS_ADRERR;
+ info.si_addr = (void *)addr;
+ force_sig_info(SIGBUS, &info, tsk);
+
+ return;
+
+vmalloc_fault:
+ {
+ /*
+ * Synchronize this task's top level page-table
+ * with the 'reference' page table.
+ *
+ * Use current_pgd instead of tsk->active_mm->pgd
+ * since the latter might be unavailable if this
+ * code is executed in a misfortunately run irq
+ * (like inside schedule() between switch_mm and
+ * switch_to...).
+ */
+
+ unsigned int index = pgd_index(addr);
+ pgd_t *pgd, *pgd_k;
+ pud_t *pud, *pud_k;
+ pmd_t *pmd, *pmd_k;
+ pte_t *pte_k;
+
+ pgd = (pgd_t *) __va(__nds32__mfsr(NDS32_SR_L1_PPTB)) + index;
+ pgd_k = init_mm.pgd + index;
+
+ if (!pgd_present(*pgd_k))
+ goto no_context;
+
+ pud = pud_offset(pgd, addr);
+ pud_k = pud_offset(pgd_k, addr);
+ if (!pud_present(*pud_k))
+ goto no_context;
+
+ pmd = pmd_offset(pud, addr);
+ pmd_k = pmd_offset(pud_k, addr);
+ if (!pmd_present(*pmd_k))
+ goto no_context;
+
+ if (!pmd_present(*pmd))
+ set_pmd(pmd, *pmd_k);
+ else
+ BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k));
+
+ /*
+ * Since the vmalloc area is global, we don't
+ * need to copy individual PTE's, it is enough to
+ * copy the pgd pointer into the pte page of the
+ * root task. If that is there, we'll find our pte if
+ * it exists.
+ */
+
+ /* Make sure the actual PTE exists as well to
+ * catch kernel vmalloc-area accesses to non-mapped
+ * addres. If we don't do this, this will just
+ * silently loop forever.
+ */
+
+ pte_k = pte_offset_kernel(pmd_k, addr);
+ if (!pte_present(*pte_k))
+ goto no_context;
+
+ return;
+ }
+}
diff --git a/arch/nds32/mm/highmem.c b/arch/nds32/mm/highmem.c
new file mode 100644
index 000000000000..e17cb8a69315
--- /dev/null
+++ b/arch/nds32/mm/highmem.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/export.h>
+#include <linux/highmem.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/bootmem.h>
+#include <asm/fixmap.h>
+#include <asm/tlbflush.h>
+
+void *kmap(struct page *page)
+{
+ unsigned long vaddr;
+ might_sleep();
+ if (!PageHighMem(page))
+ return page_address(page);
+ vaddr = (unsigned long)kmap_high(page);
+ return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap);
+
+void kunmap(struct page *page)
+{
+ BUG_ON(in_interrupt());
+ if (!PageHighMem(page))
+ return;
+ kunmap_high(page);
+}
+
+EXPORT_SYMBOL(kunmap);
+
+void *kmap_atomic(struct page *page)
+{
+ unsigned int idx;
+ unsigned long vaddr, pte;
+ int type;
+ pte_t *ptep;
+
+ preempt_disable();
+ pagefault_disable();
+ if (!PageHighMem(page))
+ return page_address(page);
+
+ type = kmap_atomic_idx_push();
+
+ idx = type + KM_TYPE_NR * smp_processor_id();
+ vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+ pte = (page_to_pfn(page) << PAGE_SHIFT) | (PAGE_KERNEL);
+ ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+ set_pte(ptep, pte);
+
+ __nds32__tlbop_inv(vaddr);
+ __nds32__mtsr_dsb(vaddr, NDS32_SR_TLB_VPN);
+ __nds32__tlbop_rwr(pte);
+ __nds32__isb();
+ return (void *)vaddr;
+}
+
+EXPORT_SYMBOL(kmap_atomic);
+
+void __kunmap_atomic(void *kvaddr)
+{
+ if (kvaddr >= (void *)FIXADDR_START) {
+ unsigned long vaddr = (unsigned long)kvaddr;
+ pte_t *ptep;
+ kmap_atomic_idx_pop();
+ __nds32__tlbop_inv(vaddr);
+ __nds32__isb();
+ ptep = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
+ set_pte(ptep, 0);
+ }
+ pagefault_enable();
+ preempt_enable();
+}
+
+EXPORT_SYMBOL(__kunmap_atomic);
diff --git a/arch/nds32/mm/init.c b/arch/nds32/mm/init.c
new file mode 100644
index 000000000000..93ee0160720b
--- /dev/null
+++ b/arch/nds32/mm/init.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 1995-2005 Russell King
+// Copyright (C) 2012 ARM Ltd.
+// Copyright (C) 2013-2017 Andes Technology Corporation
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/swap.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/mman.h>
+#include <linux/nodemask.h>
+#include <linux/initrd.h>
+#include <linux/highmem.h>
+#include <linux/memblock.h>
+
+#include <asm/sections.h>
+#include <asm/setup.h>
+#include <asm/tlb.h>
+#include <asm/page.h>
+
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+DEFINE_SPINLOCK(anon_alias_lock);
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern unsigned long phys_initrd_start;
+extern unsigned long phys_initrd_size;
+
+/*
+ * empty_zero_page is a special page that is used for
+ * zero-initialized data and COW.
+ */
+struct page *empty_zero_page;
+
+static void __init zone_sizes_init(void)
+{
+ unsigned long zones_size[MAX_NR_ZONES];
+
+ /* Clear the zone sizes */
+ memset(zones_size, 0, sizeof(zones_size));
+
+ zones_size[ZONE_NORMAL] = max_low_pfn;
+#ifdef CONFIG_HIGHMEM
+ zones_size[ZONE_HIGHMEM] = max_pfn;
+#endif
+ free_area_init(zones_size);
+
+}
+
+/*
+ * Map all physical memory under high_memory into kernel's address space.
+ *
+ * This is explicitly coded for two-level page tables, so if you need
+ * something else then this needs to change.
+ */
+static void __init map_ram(void)
+{
+ unsigned long v, p, e;
+ pgd_t *pge;
+ pud_t *pue;
+ pmd_t *pme;
+ pte_t *pte;
+ /* These mark extents of read-only kernel pages...
+ * ...from vmlinux.lds.S
+ */
+
+ p = (u32) memblock_start_of_DRAM() & PAGE_MASK;
+ e = min((u32) memblock_end_of_DRAM(), (u32) __pa(high_memory));
+
+ v = (u32) __va(p);
+ pge = pgd_offset_k(v);
+
+ while (p < e) {
+ int j;
+ pue = pud_offset(pge, v);
+ pme = pmd_offset(pue, v);
+
+ if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) {
+ panic("%s: Kernel hardcoded for "
+ "two-level page tables", __func__);
+ }
+
+ /* Alloc one page for holding PTE's... */
+ pte = (pte_t *) __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+ memset(pte, 0, PAGE_SIZE);
+ set_pmd(pme, __pmd(__pa(pte) + _PAGE_KERNEL_TABLE));
+
+ /* Fill the newly allocated page with PTE'S */
+ for (j = 0; p < e && j < PTRS_PER_PTE;
+ v += PAGE_SIZE, p += PAGE_SIZE, j++, pte++) {
+ /* Create mapping between p and v. */
+ /* TODO: more fine grant for page access permission */
+ set_pte(pte, __pte(p + pgprot_val(PAGE_KERNEL)));
+ }
+
+ pge++;
+ }
+}
+static pmd_t *fixmap_pmd_p;
+static void __init fixedrange_init(void)
+{
+ unsigned long vaddr;
+ pgd_t *pgd;
+ pud_t *pud;
+ pmd_t *pmd;
+#ifdef CONFIG_HIGHMEM
+ pte_t *pte;
+#endif /* CONFIG_HIGHMEM */
+
+ /*
+ * Fixed mappings:
+ */
+ vaddr = __fix_to_virt(__end_of_fixed_addresses - 1);
+ pgd = swapper_pg_dir + pgd_index(vaddr);
+ pud = pud_offset(pgd, vaddr);
+ pmd = pmd_offset(pud, vaddr);
+ fixmap_pmd_p = (pmd_t *) __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+ memset(fixmap_pmd_p, 0, PAGE_SIZE);
+ set_pmd(pmd, __pmd(__pa(fixmap_pmd_p) + _PAGE_KERNEL_TABLE));
+
+#ifdef CONFIG_HIGHMEM
+ /*
+ * Permanent kmaps:
+ */
+ vaddr = PKMAP_BASE;
+
+ pgd = swapper_pg_dir + pgd_index(vaddr);
+ pud = pud_offset(pgd, vaddr);
+ pmd = pmd_offset(pud, vaddr);
+ pte = (pte_t *) __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+ memset(pte, 0, PAGE_SIZE);
+ set_pmd(pmd, __pmd(__pa(pte) + _PAGE_KERNEL_TABLE));
+ pkmap_page_table = pte;
+#endif /* CONFIG_HIGHMEM */
+}
+
+/*
+ * paging_init() sets up the page tables, initialises the zone memory
+ * maps, and sets up the zero page, bad page and bad page tables.
+ */
+void __init paging_init(void)
+{
+ int i;
+ void *zero_page;
+
+ pr_info("Setting up paging and PTEs.\n");
+ /* clear out the init_mm.pgd that will contain the kernel's mappings */
+ for (i = 0; i < PTRS_PER_PGD; i++)
+ swapper_pg_dir[i] = __pgd(1);
+
+ map_ram();
+
+ fixedrange_init();
+
+ /* allocate space for empty_zero_page */
+ zero_page = __va(memblock_alloc(PAGE_SIZE, PAGE_SIZE));
+ memset(zero_page, 0, PAGE_SIZE);
+ zone_sizes_init();
+
+ empty_zero_page = virt_to_page(zero_page);
+ flush_dcache_page(empty_zero_page);
+}
+
+static inline void __init free_highmem(void)
+{
+#ifdef CONFIG_HIGHMEM
+ unsigned long pfn;
+ for (pfn = PFN_UP(__pa(high_memory)); pfn < max_pfn; pfn++) {
+ phys_addr_t paddr = (phys_addr_t) pfn << PAGE_SHIFT;
+ if (!memblock_is_reserved(paddr))
+ free_highmem_page(pfn_to_page(pfn));
+ }
+#endif
+}
+
+static void __init set_max_mapnr_init(void)
+{
+ max_mapnr = max_pfn;
+}
+
+/*
+ * mem_init() marks the free areas in the mem_map and tells us how much
+ * memory is free. This is done after various parts of the system have
+ * claimed their memory after the kernel image.
+ */
+void __init mem_init(void)
+{
+ phys_addr_t memory_start = memblock_start_of_DRAM();
+ BUG_ON(!mem_map);
+ set_max_mapnr_init();
+
+ free_highmem();
+
+ /* this will put all low memory onto the freelists */
+ free_all_bootmem();
+ mem_init_print_info(NULL);
+
+ pr_info("virtual kernel memory layout:\n"
+ " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n"
+#ifdef CONFIG_HIGHMEM
+ " pkmap : 0x%08lx - 0x%08lx (%4ld kB)\n"
+#endif
+ " consist : 0x%08lx - 0x%08lx (%4ld MB)\n"
+ " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n"
+ " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n"
+ " .init : 0x%08lx - 0x%08lx (%4ld kB)\n"
+ " .data : 0x%08lx - 0x%08lx (%4ld kB)\n"
+ " .text : 0x%08lx - 0x%08lx (%4ld kB)\n",
+ FIXADDR_START, FIXADDR_TOP, (FIXADDR_TOP - FIXADDR_START) >> 10,
+#ifdef CONFIG_HIGHMEM
+ PKMAP_BASE, PKMAP_BASE + LAST_PKMAP * PAGE_SIZE,
+ (LAST_PKMAP * PAGE_SIZE) >> 10,
+#endif
+ CONSISTENT_BASE, CONSISTENT_END,
+ ((CONSISTENT_END) - (CONSISTENT_BASE)) >> 20, VMALLOC_START,
+ (unsigned long)VMALLOC_END, (VMALLOC_END - VMALLOC_START) >> 20,
+ (unsigned long)__va(memory_start), (unsigned long)high_memory,
+ ((unsigned long)high_memory -
+ (unsigned long)__va(memory_start)) >> 20,
+ (unsigned long)&__init_begin, (unsigned long)&__init_end,
+ ((unsigned long)&__init_end -
+ (unsigned long)&__init_begin) >> 10, (unsigned long)&_etext,
+ (unsigned long)&_edata,
+ ((unsigned long)&_edata - (unsigned long)&_etext) >> 10,
+ (unsigned long)&_text, (unsigned long)&_etext,
+ ((unsigned long)&_etext - (unsigned long)&_text) >> 10);
+
+ /*
+ * Check boundaries twice: Some fundamental inconsistencies can
+ * be detected at build time already.
+ */
+#ifdef CONFIG_HIGHMEM
+ BUILD_BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > FIXADDR_START);
+ BUILD_BUG_ON((CONSISTENT_END) > PKMAP_BASE);
+#endif
+ BUILD_BUG_ON(VMALLOC_END > CONSISTENT_BASE);
+ BUILD_BUG_ON(VMALLOC_START >= VMALLOC_END);
+
+#ifdef CONFIG_HIGHMEM
+ BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > FIXADDR_START);
+ BUG_ON(CONSISTENT_END > PKMAP_BASE);
+#endif
+ BUG_ON(VMALLOC_END > CONSISTENT_BASE);
+ BUG_ON(VMALLOC_START >= VMALLOC_END);
+ BUG_ON((unsigned long)high_memory > VMALLOC_START);
+
+ return;
+}
+
+void free_initmem(void)
+{
+ free_initmem_default(-1);
+}
+
+#ifdef CONFIG_BLK_DEV_INITRD
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+ free_reserved_area((void *)start, (void *)end, -1, "initrd");
+}
+#endif
+
+void __set_fixmap(enum fixed_addresses idx,
+ phys_addr_t phys, pgprot_t flags)
+{
+ unsigned long addr = __fix_to_virt(idx);
+ pte_t *pte;
+
+ BUG_ON(idx <= FIX_HOLE || idx >= __end_of_fixed_addresses);
+
+ pte = (pte_t *)&fixmap_pmd_p[pte_index(addr)];;
+
+ if (pgprot_val(flags)) {
+ set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
+ } else {
+ pte_clear(&init_mm, addr, pte);
+ flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
+ }
+}
diff --git a/arch/nds32/mm/ioremap.c b/arch/nds32/mm/ioremap.c
new file mode 100644
index 000000000000..690140bb23a2
--- /dev/null
+++ b/arch/nds32/mm/ioremap.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/vmalloc.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <asm/pgtable.h>
+
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size);
+
+static void __iomem *__ioremap_caller(phys_addr_t phys_addr, size_t size,
+ void *caller)
+{
+ struct vm_struct *area;
+ unsigned long addr, offset, last_addr;
+ pgprot_t prot;
+
+ /* Don't allow wraparound or zero size */
+ last_addr = phys_addr + size - 1;
+ if (!size || last_addr < phys_addr)
+ return NULL;
+
+ /*
+ * Mappings have to be page-aligned
+ */
+ offset = phys_addr & ~PAGE_MASK;
+ phys_addr &= PAGE_MASK;
+ size = PAGE_ALIGN(last_addr + 1) - phys_addr;
+
+ /*
+ * Ok, go for it..
+ */
+ area = get_vm_area_caller(size, VM_IOREMAP, caller);
+ if (!area)
+ return NULL;
+
+ area->phys_addr = phys_addr;
+ addr = (unsigned long)area->addr;
+ prot = __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D |
+ _PAGE_G | _PAGE_C_DEV);
+ if (ioremap_page_range(addr, addr + size, phys_addr, prot)) {
+ vunmap((void *)addr);
+ return NULL;
+ }
+ return (__force void __iomem *)(offset + (char *)addr);
+
+}
+
+void __iomem *ioremap(phys_addr_t phys_addr, size_t size)
+{
+ return __ioremap_caller(phys_addr, size,
+ __builtin_return_address(0));
+}
+
+EXPORT_SYMBOL(ioremap);
+
+void iounmap(volatile void __iomem * addr)
+{
+ vunmap((void *)(PAGE_MASK & (unsigned long)addr));
+}
+
+EXPORT_SYMBOL(iounmap);
diff --git a/arch/nds32/mm/mm-nds32.c b/arch/nds32/mm/mm-nds32.c
new file mode 100644
index 000000000000..3b43798d754f
--- /dev/null
+++ b/arch/nds32/mm/mm-nds32.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/init_task.h>
+#include <asm/pgalloc.h>
+
+#define FIRST_KERNEL_PGD_NR (USER_PTRS_PER_PGD)
+
+/*
+ * need to get a page for level 1
+ */
+
+pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+ pgd_t *new_pgd, *init_pgd;
+ int i;
+
+ new_pgd = (pgd_t *) __get_free_pages(GFP_KERNEL, 0);
+ if (!new_pgd)
+ return NULL;
+ for (i = 0; i < PTRS_PER_PGD; i++) {
+ (*new_pgd) = 1;
+ new_pgd++;
+ }
+ new_pgd -= PTRS_PER_PGD;
+
+ init_pgd = pgd_offset_k(0);
+
+ memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
+ (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
+
+ cpu_dcache_wb_range((unsigned long)new_pgd,
+ (unsigned long)new_pgd +
+ PTRS_PER_PGD * sizeof(pgd_t));
+ inc_zone_page_state(virt_to_page((unsigned long *)new_pgd),
+ NR_PAGETABLE);
+
+ return new_pgd;
+}
+
+void pgd_free(struct mm_struct *mm, pgd_t * pgd)
+{
+ pmd_t *pmd;
+ struct page *pte;
+
+ if (!pgd)
+ return;
+
+ pmd = (pmd_t *) pgd;
+ if (pmd_none(*pmd))
+ goto free;
+ if (pmd_bad(*pmd)) {
+ pmd_ERROR(*pmd);
+ pmd_clear(pmd);
+ goto free;
+ }
+
+ pte = pmd_page(*pmd);
+ pmd_clear(pmd);
+ dec_zone_page_state(virt_to_page((unsigned long *)pgd), NR_PAGETABLE);
+ pte_free(mm, pte);
+ mm_dec_nr_ptes(mm);
+ pmd_free(mm, pmd);
+free:
+ free_pages((unsigned long)pgd, 0);
+}
+
+/*
+ * In order to soft-boot, we need to insert a 1:1 mapping in place of
+ * the user-mode pages. This will then ensure that we have predictable
+ * results when turning the mmu off
+ */
+void setup_mm_for_reboot(char mode)
+{
+ unsigned long pmdval;
+ pgd_t *pgd;
+ pmd_t *pmd;
+ int i;
+
+ if (current->mm && current->mm->pgd)
+ pgd = current->mm->pgd;
+ else
+ pgd = init_mm.pgd;
+
+ for (i = 0; i < USER_PTRS_PER_PGD; i++) {
+ pmdval = (i << PGDIR_SHIFT);
+ pmd = pmd_offset(pgd + i, i << PGDIR_SHIFT);
+ set_pmd(pmd, __pmd(pmdval));
+ }
+}
diff --git a/arch/nds32/mm/mmap.c b/arch/nds32/mm/mmap.c
new file mode 100644
index 000000000000..c206b31ce07a
--- /dev/null
+++ b/arch/nds32/mm/mmap.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/sched.h>
+#include <linux/mman.h>
+#include <linux/shm.h>
+
+#define COLOUR_ALIGN(addr,pgoff) \
+ ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \
+ (((pgoff)<<PAGE_SHIFT) & (SHMLBA-1)))
+
+/*
+ * We need to ensure that shared mappings are correctly aligned to
+ * avoid aliasing issues with VIPT caches. We need to ensure that
+ * a specific page of an object is always mapped at a multiple of
+ * SHMLBA bytes.
+ *
+ * We unconditionally provide this function for all cases, however
+ * in the VIVT case, we optimise out the alignment rules.
+ */
+unsigned long
+arch_get_unmapped_area(struct file *filp, unsigned long addr,
+ unsigned long len, unsigned long pgoff,
+ unsigned long flags)
+{
+ struct mm_struct *mm = current->mm;
+ struct vm_area_struct *vma;
+ int do_align = 0;
+ struct vm_unmapped_area_info info;
+ int aliasing = 0;
+ if(IS_ENABLED(CONFIG_CPU_CACHE_ALIASING))
+ aliasing = 1;
+
+ /*
+ * We only need to do colour alignment if either the I or D
+ * caches alias.
+ */
+ if (aliasing)
+ do_align = filp || (flags & MAP_SHARED);
+
+ /*
+ * We enforce the MAP_FIXED case.
+ */
+ if (flags & MAP_FIXED) {
+ if (aliasing && flags & MAP_SHARED &&
+ (addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1))
+ return -EINVAL;
+ return addr;
+ }
+
+ if (len > TASK_SIZE)
+ return -ENOMEM;
+
+ if (addr) {
+ if (do_align)
+ addr = COLOUR_ALIGN(addr, pgoff);
+ else
+ addr = PAGE_ALIGN(addr);
+
+ vma = find_vma(mm, addr);
+ if (TASK_SIZE - len >= addr &&
+ (!vma || addr + len <= vma->vm_start))
+ return addr;
+ }
+
+ info.flags = 0;
+ info.length = len;
+ info.low_limit = mm->mmap_base;
+ info.high_limit = TASK_SIZE;
+ info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
+ info.align_offset = pgoff << PAGE_SHIFT;
+ return vm_unmapped_area(&info);
+}
diff --git a/arch/nds32/mm/proc.c b/arch/nds32/mm/proc.c
new file mode 100644
index 000000000000..ba80992d13a2
--- /dev/null
+++ b/arch/nds32/mm/proc.c
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/nds32.h>
+#include <asm/pgtable.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+#include <asm/l2_cache.h>
+#include <nds32_intrinsic.h>
+
+#include <asm/cache_info.h>
+extern struct cache_info L1_cache_info[2];
+
+int va_kernel_present(unsigned long addr)
+{
+ pmd_t *pmd;
+ pte_t *ptep, pte;
+
+ pmd = pmd_offset(pgd_offset_k(addr), addr);
+ if (!pmd_none(*pmd)) {
+ ptep = pte_offset_map(pmd, addr);
+ pte = *ptep;
+ if (pte_present(pte))
+ return pte;
+ }
+ return 0;
+}
+
+pte_t va_present(struct mm_struct * mm, unsigned long addr)
+{
+ pgd_t *pgd;
+ pud_t *pud;
+ pmd_t *pmd;
+ pte_t *ptep, pte;
+
+ pgd = pgd_offset(mm, addr);
+ if (!pgd_none(*pgd)) {
+ pud = pud_offset(pgd, addr);
+ if (!pud_none(*pud)) {
+ pmd = pmd_offset(pud, addr);
+ if (!pmd_none(*pmd)) {
+ ptep = pte_offset_map(pmd, addr);
+ pte = *ptep;
+ if (pte_present(pte))
+ return pte;
+ }
+ }
+ }
+ return 0;
+
+}
+
+int va_readable(struct pt_regs *regs, unsigned long addr)
+{
+ struct mm_struct *mm = current->mm;
+ pte_t pte;
+ int ret = 0;
+
+ if (user_mode(regs)) {
+ /* user mode */
+ pte = va_present(mm, addr);
+ if (!pte && pte_read(pte))
+ ret = 1;
+ } else {
+ /* superuser mode is always readable, so we can only
+ * check it is present or not*/
+ return (! !va_kernel_present(addr));
+ }
+ return ret;
+}
+
+int va_writable(struct pt_regs *regs, unsigned long addr)
+{
+ struct mm_struct *mm = current->mm;
+ pte_t pte;
+ int ret = 0;
+
+ if (user_mode(regs)) {
+ /* user mode */
+ pte = va_present(mm, addr);
+ if (!pte && pte_write(pte))
+ ret = 1;
+ } else {
+ /* superuser mode */
+ pte = va_kernel_present(addr);
+ if (!pte && pte_kernel_write(pte))
+ ret = 1;
+ }
+ return ret;
+}
+
+/*
+ * All
+ */
+void cpu_icache_inval_all(void)
+{
+ unsigned long end, line_size;
+
+ line_size = L1_cache_info[ICACHE].line_size;
+ end =
+ line_size * L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].sets;
+
+ do {
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end));
+ } while (end > 0);
+ __nds32__isb();
+}
+
+void cpu_dcache_inval_all(void)
+{
+ __nds32__cctl_l1d_invalall();
+}
+
+#ifdef CONFIG_CACHE_L2
+void dcache_wb_all_level(void)
+{
+ unsigned long flags, cmd;
+ local_irq_save(flags);
+ __nds32__cctl_l1d_wball_alvl();
+ /* Section 1: Ensure the section 2 & 3 program code execution after */
+ __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
+
+ /* Section 2: Confirm the writeback all level is done in CPU and L2C */
+ cmd = CCTL_CMD_L2_SYNC;
+ L2_CMD_RDY();
+ L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
+ L2_CMD_RDY();
+
+ /* Section 3: Writeback whole L2 cache */
+ cmd = CCTL_ALL_CMD | CCTL_CMD_L2_IX_WB;
+ L2_CMD_RDY();
+ L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
+ L2_CMD_RDY();
+ __nds32__msync_all();
+ local_irq_restore(flags);
+}
+EXPORT_SYMBOL(dcache_wb_all_level);
+#endif
+
+void cpu_dcache_wb_all(void)
+{
+ __nds32__cctl_l1d_wball_one_lvl();
+ __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
+}
+
+void cpu_dcache_wbinval_all(void)
+{
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ unsigned long flags;
+ local_irq_save(flags);
+#endif
+ cpu_dcache_wb_all();
+ cpu_dcache_inval_all();
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ local_irq_restore(flags);
+#endif
+}
+
+/*
+ * Page
+ */
+void cpu_icache_inval_page(unsigned long start)
+{
+ unsigned long line_size, end;
+
+ line_size = L1_cache_info[ICACHE].line_size;
+ end = start + PAGE_SIZE;
+
+ do {
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end));
+ } while (end != start);
+ __nds32__isb();
+}
+
+void cpu_dcache_inval_page(unsigned long start)
+{
+ unsigned long line_size, end;
+
+ line_size = L1_cache_info[DCACHE].line_size;
+ end = start + PAGE_SIZE;
+
+ do {
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ } while (end != start);
+}
+
+void cpu_dcache_wb_page(unsigned long start)
+{
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ unsigned long line_size, end;
+
+ line_size = L1_cache_info[DCACHE].line_size;
+ end = start + PAGE_SIZE;
+
+ do {
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+ end -= line_size;
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+ } while (end != start);
+ __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
+#endif
+}
+
+void cpu_dcache_wbinval_page(unsigned long start)
+{
+ unsigned long line_size, end;
+
+ line_size = L1_cache_info[DCACHE].line_size;
+ end = start + PAGE_SIZE;
+
+ do {
+ end -= line_size;
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+#endif
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ end -= line_size;
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+#endif
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ end -= line_size;
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+#endif
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ end -= line_size;
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end));
+#endif
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end));
+ } while (end != start);
+ __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
+}
+
+void cpu_cache_wbinval_page(unsigned long page, int flushi)
+{
+ cpu_dcache_wbinval_page(page);
+ if (flushi)
+ cpu_icache_inval_page(page);
+}
+
+/*
+ * Range
+ */
+void cpu_icache_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = L1_cache_info[ICACHE].line_size;
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (start));
+ start += line_size;
+ }
+ __nds32__isb();
+}
+
+void cpu_dcache_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = L1_cache_info[DCACHE].line_size;
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));
+ start += line_size;
+ }
+}
+
+void cpu_dcache_wb_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ unsigned long line_size;
+
+ line_size = L1_cache_info[DCACHE].line_size;
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));
+ start += line_size;
+ }
+ __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
+#endif
+}
+
+void cpu_dcache_wbinval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = L1_cache_info[DCACHE].line_size;
+
+ while (end > start) {
+#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));
+#endif
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));
+ start += line_size;
+ }
+ __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0);
+}
+
+void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi)
+{
+ unsigned long line_size, align_start, align_end;
+
+ line_size = L1_cache_info[DCACHE].line_size;
+ align_start = start & ~(line_size - 1);
+ align_end = (end + line_size - 1) & ~(line_size - 1);
+ cpu_dcache_wbinval_range(align_start, align_end);
+
+ if (flushi) {
+ line_size = L1_cache_info[ICACHE].line_size;
+ align_start = start & ~(line_size - 1);
+ align_end = (end + line_size - 1) & ~(line_size - 1);
+ cpu_icache_inval_range(align_start, align_end);
+ }
+}
+
+void cpu_cache_wbinval_range_check(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end,
+ bool flushi, bool wbd)
+{
+ unsigned long line_size, t_start, t_end;
+
+ if (!flushi && !wbd)
+ return;
+ line_size = L1_cache_info[DCACHE].line_size;
+ start = start & ~(line_size - 1);
+ end = (end + line_size - 1) & ~(line_size - 1);
+
+ if ((end - start) > (8 * PAGE_SIZE)) {
+ if (wbd)
+ cpu_dcache_wbinval_all();
+ if (flushi)
+ cpu_icache_inval_all();
+ return;
+ }
+
+ t_start = (start + PAGE_SIZE) & PAGE_MASK;
+ t_end = ((end - 1) & PAGE_MASK);
+
+ if ((start & PAGE_MASK) == t_end) {
+ if (va_present(vma->vm_mm, start)) {
+ if (wbd)
+ cpu_dcache_wbinval_range(start, end);
+ if (flushi)
+ cpu_icache_inval_range(start, end);
+ }
+ return;
+ }
+
+ if (va_present(vma->vm_mm, start)) {
+ if (wbd)
+ cpu_dcache_wbinval_range(start, t_start);
+ if (flushi)
+ cpu_icache_inval_range(start, t_start);
+ }
+
+ if (va_present(vma->vm_mm, end - 1)) {
+ if (wbd)
+ cpu_dcache_wbinval_range(t_end, end);
+ if (flushi)
+ cpu_icache_inval_range(t_end, end);
+ }
+
+ while (t_start < t_end) {
+ if (va_present(vma->vm_mm, t_start)) {
+ if (wbd)
+ cpu_dcache_wbinval_page(t_start);
+ if (flushi)
+ cpu_icache_inval_page(t_start);
+ }
+ t_start += PAGE_SIZE;
+ }
+}
+
+#ifdef CONFIG_CACHE_L2
+static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op)
+{
+ if (atl2c_base) {
+ unsigned long p_start = __pa(start);
+ unsigned long p_end = __pa(end);
+ unsigned long cmd;
+ unsigned long line_size;
+ /* TODO Can Use PAGE Mode to optimize if range large than PAGE_SIZE */
+ line_size = L2_CACHE_LINE_SIZE();
+ p_start = p_start & (~(line_size - 1));
+ p_end = (p_end + line_size - 1) & (~(line_size - 1));
+ cmd =
+ (p_start & ~(line_size - 1)) | op |
+ CCTL_SINGLE_CMD;
+ do {
+ L2_CMD_RDY();
+ L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
+ cmd += line_size;
+ p_start += line_size;
+ } while (p_end > p_start);
+ cmd = CCTL_CMD_L2_SYNC;
+ L2_CMD_RDY();
+ L2C_W_REG(L2_CCTL_CMD_OFF, cmd);
+ L2_CMD_RDY();
+ }
+}
+#else
+#define cpu_l2cache_op(start,end,op) do { } while (0)
+#endif
+/*
+ * DMA
+ */
+void cpu_dma_wb_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+ unsigned long flags;
+ line_size = L1_cache_info[DCACHE].line_size;
+ start = start & (~(line_size - 1));
+ end = (end + line_size - 1) & (~(line_size - 1));
+ if (unlikely(start == end))
+ return;
+
+ local_irq_save(flags);
+ cpu_dcache_wb_range(start, end);
+ cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB);
+ __nds32__msync_all();
+ local_irq_restore(flags);
+}
+
+void cpu_dma_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+ unsigned long old_start = start;
+ unsigned long old_end = end;
+ unsigned long flags;
+ line_size = L1_cache_info[DCACHE].line_size;
+ start = start & (~(line_size - 1));
+ end = (end + line_size - 1) & (~(line_size - 1));
+ if (unlikely(start == end))
+ return;
+ local_irq_save(flags);
+ if (start != old_start) {
+ cpu_dcache_wbinval_range(start, start + line_size);
+ cpu_l2cache_op(start, start + line_size, CCTL_CMD_L2_PA_WBINVAL);
+ }
+ if (end != old_end) {
+ cpu_dcache_wbinval_range(end - line_size, end);
+ cpu_l2cache_op(end - line_size, end, CCTL_CMD_L2_PA_WBINVAL);
+ }
+ cpu_dcache_inval_range(start, end);
+ cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL);
+ __nds32__msync_all();
+ local_irq_restore(flags);
+
+}
+
+void cpu_dma_wbinval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+ unsigned long flags;
+ line_size = L1_cache_info[DCACHE].line_size;
+ start = start & (~(line_size - 1));
+ end = (end + line_size - 1) & (~(line_size - 1));
+ if (unlikely(start == end))
+ return;
+
+ local_irq_save(flags);
+ cpu_dcache_wbinval_range(start, end);
+ cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL);
+ __nds32__msync_all();
+ local_irq_restore(flags);
+}
+
+void cpu_proc_init(void)
+{
+}
+
+void cpu_proc_fin(void)
+{
+}
+
+void cpu_do_idle(void)
+{
+ __nds32__standby_no_wake_grant();
+}
+
+void cpu_reset(unsigned long reset)
+{
+ u32 tmp;
+ GIE_DISABLE();
+ tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
+ tmp &= ~(CACHE_CTL_mskIC_EN | CACHE_CTL_mskDC_EN);
+ __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL);
+ cpu_dcache_wbinval_all();
+ cpu_icache_inval_all();
+
+ __asm__ __volatile__("jr.toff %0\n\t"::"r"(reset));
+}
+
+void cpu_switch_mm(struct mm_struct *mm)
+{
+ unsigned long cid;
+ cid = __nds32__mfsr(NDS32_SR_TLB_MISC);
+ cid = (cid & ~TLB_MISC_mskCID) | mm->context.id;
+ __nds32__mtsr_dsb(cid, NDS32_SR_TLB_MISC);
+ __nds32__mtsr_isb(__pa(mm->pgd), NDS32_SR_L1_PPTB);
+}
diff --git a/arch/nds32/mm/tlb.c b/arch/nds32/mm/tlb.c
new file mode 100644
index 000000000000..dd41f5e0712f
--- /dev/null
+++ b/arch/nds32/mm/tlb.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2005-2017 Andes Technology Corporation
+
+#include <linux/spinlock_types.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <asm/nds32.h>
+#include <nds32_intrinsic.h>
+
+unsigned int cpu_last_cid = { TLB_MISC_mskCID + (2 << TLB_MISC_offCID) };
+
+DEFINE_SPINLOCK(cid_lock);
+
+void local_flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ unsigned long flags, ocid, ncid;
+
+ if ((end - start) > 0x400000) {
+ __nds32__tlbop_flua();
+ __nds32__isb();
+ return;
+ }
+
+ spin_lock_irqsave(&cid_lock, flags);
+ ocid = __nds32__mfsr(NDS32_SR_TLB_MISC);
+ ncid = (ocid & ~TLB_MISC_mskCID) | vma->vm_mm->context.id;
+ __nds32__mtsr_dsb(ncid, NDS32_SR_TLB_MISC);
+ while (start < end) {
+ __nds32__tlbop_inv(start);
+ __nds32__isb();
+ start += PAGE_SIZE;
+ }
+ __nds32__mtsr_dsb(ocid, NDS32_SR_TLB_MISC);
+ spin_unlock_irqrestore(&cid_lock, flags);
+}
+
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
+{
+ unsigned long flags, ocid, ncid;
+
+ spin_lock_irqsave(&cid_lock, flags);
+ ocid = __nds32__mfsr(NDS32_SR_TLB_MISC);
+ ncid = (ocid & ~TLB_MISC_mskCID) | vma->vm_mm->context.id;
+ __nds32__mtsr_dsb(ncid, NDS32_SR_TLB_MISC);
+ __nds32__tlbop_inv(addr);
+ __nds32__isb();
+ __nds32__mtsr_dsb(ocid, NDS32_SR_TLB_MISC);
+ spin_unlock_irqrestore(&cid_lock, flags);
+}
diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
index ce072ba0f8dd..9010243077ab 100644
--- a/arch/nios2/include/asm/io.h
+++ b/arch/nios2/include/asm/io.h
@@ -45,6 +45,7 @@ static inline void iounmap(void __iomem *addr)
__iounmap(addr);
}
+#define ioremap_nocache ioremap_nocache
#define ioremap_wc ioremap_nocache
#define ioremap_wt ioremap_nocache
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index 7c691399da3f..6709b28a0221 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -29,13 +29,14 @@
#define PIO_OFFSET 0
#define PIO_MASK 0
+#define ioremap_nocache ioremap_nocache
#include <asm-generic/io.h>
#include <asm/pgtable.h>
extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size,
pgprot_t prot);
-static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
+static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
{
return __ioremap(offset, size, PAGE_KERNEL);
}
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 79089778725b..e3b45546d589 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -543,7 +543,8 @@ void flush_cache_mm(struct mm_struct *mm)
rp3440, etc. So, avoid it if the mm isn't too big. */
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
mm_total_size(mm) >= parisc_cache_flush_threshold) {
- flush_tlb_all();
+ if (mm->context)
+ flush_tlb_all();
flush_cache_all();
return;
}
@@ -571,6 +572,8 @@ void flush_cache_mm(struct mm_struct *mm)
pfn = pte_pfn(*ptep);
if (!pfn_valid(pfn))
continue;
+ if (unlikely(mm->context))
+ flush_tlb_page(vma, addr);
__flush_cache_page(vma, addr, PFN_PHYS(pfn));
}
}
@@ -579,26 +582,46 @@ void flush_cache_mm(struct mm_struct *mm)
void flush_cache_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
+ pgd_t *pgd;
+ unsigned long addr;
+
if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
end - start >= parisc_cache_flush_threshold) {
- flush_tlb_range(vma, start, end);
+ if (vma->vm_mm->context)
+ flush_tlb_range(vma, start, end);
flush_cache_all();
return;
}
- flush_user_dcache_range_asm(start, end);
- if (vma->vm_flags & VM_EXEC)
- flush_user_icache_range_asm(start, end);
- flush_tlb_range(vma, start, end);
+ if (vma->vm_mm->context == mfsp(3)) {
+ flush_user_dcache_range_asm(start, end);
+ if (vma->vm_flags & VM_EXEC)
+ flush_user_icache_range_asm(start, end);
+ flush_tlb_range(vma, start, end);
+ return;
+ }
+
+ pgd = vma->vm_mm->pgd;
+ for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {
+ unsigned long pfn;
+ pte_t *ptep = get_ptep(pgd, addr);
+ if (!ptep)
+ continue;
+ pfn = pte_pfn(*ptep);
+ if (pfn_valid(pfn)) {
+ if (unlikely(vma->vm_mm->context))
+ flush_tlb_page(vma, addr);
+ __flush_cache_page(vma, addr, PFN_PHYS(pfn));
+ }
+ }
}
void
flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
{
- BUG_ON(!vma->vm_mm->context);
-
if (pfn_valid(pfn)) {
- flush_tlb_page(vma, vmaddr);
+ if (likely(vma->vm_mm->context))
+ flush_tlb_page(vma, vmaddr);
__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
}
}
diff --git a/arch/parisc/kernel/sys_parisc.c b/arch/parisc/kernel/sys_parisc.c
index 378a754ca186..8c99ebbe2bac 100644
--- a/arch/parisc/kernel/sys_parisc.c
+++ b/arch/parisc/kernel/sys_parisc.c
@@ -270,8 +270,8 @@ asmlinkage unsigned long sys_mmap2(unsigned long addr, unsigned long len,
{
/* Make sure the shift for mmap2 is constant (12), no matter what PAGE_SIZE
we have. */
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- pgoff >> (PAGE_SHIFT - 12));
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ pgoff >> (PAGE_SHIFT - 12));
}
asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
@@ -279,7 +279,7 @@ asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
unsigned long offset)
{
if (!(offset & ~PAGE_MASK)) {
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
offset >> PAGE_SHIFT);
} else {
return -EINVAL;
@@ -292,24 +292,24 @@ asmlinkage unsigned long sys_mmap(unsigned long addr, unsigned long len,
asmlinkage long parisc_truncate64(const char __user * path,
unsigned int high, unsigned int low)
{
- return sys_truncate(path, (long)high << 32 | low);
+ return ksys_truncate(path, (long)high << 32 | low);
}
asmlinkage long parisc_ftruncate64(unsigned int fd,
unsigned int high, unsigned int low)
{
- return sys_ftruncate(fd, (long)high << 32 | low);
+ return ksys_ftruncate(fd, (long)high << 32 | low);
}
/* stubs for the benefit of the syscall_table since truncate64 and truncate
* are identical on LP64 */
asmlinkage long sys_truncate64(const char __user * path, unsigned long length)
{
- return sys_truncate(path, length);
+ return ksys_truncate(path, length);
}
asmlinkage long sys_ftruncate64(unsigned int fd, unsigned long length)
{
- return sys_ftruncate(fd, length);
+ return ksys_ftruncate(fd, length);
}
asmlinkage long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg)
{
@@ -320,7 +320,7 @@ asmlinkage long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg
asmlinkage long parisc_truncate64(const char __user * path,
unsigned int high, unsigned int low)
{
- return sys_truncate64(path, (loff_t)high << 32 | low);
+ return ksys_truncate(path, (loff_t)high << 32 | low);
}
asmlinkage long parisc_ftruncate64(unsigned int fd,
@@ -333,26 +333,26 @@ asmlinkage long parisc_ftruncate64(unsigned int fd,
asmlinkage ssize_t parisc_pread64(unsigned int fd, char __user *buf, size_t count,
unsigned int high, unsigned int low)
{
- return sys_pread64(fd, buf, count, (loff_t)high << 32 | low);
+ return ksys_pread64(fd, buf, count, (loff_t)high << 32 | low);
}
asmlinkage ssize_t parisc_pwrite64(unsigned int fd, const char __user *buf,
size_t count, unsigned int high, unsigned int low)
{
- return sys_pwrite64(fd, buf, count, (loff_t)high << 32 | low);
+ return ksys_pwrite64(fd, buf, count, (loff_t)high << 32 | low);
}
asmlinkage ssize_t parisc_readahead(int fd, unsigned int high, unsigned int low,
size_t count)
{
- return sys_readahead(fd, (loff_t)high << 32 | low, count);
+ return ksys_readahead(fd, (loff_t)high << 32 | low, count);
}
asmlinkage long parisc_fadvise64_64(int fd,
unsigned int high_off, unsigned int low_off,
unsigned int high_len, unsigned int low_len, int advice)
{
- return sys_fadvise64_64(fd, (loff_t)high_off << 32 | low_off,
+ return ksys_fadvise64_64(fd, (loff_t)high_off << 32 | low_off,
(loff_t)high_len << 32 | low_len, advice);
}
@@ -360,15 +360,15 @@ asmlinkage long parisc_sync_file_range(int fd,
u32 hi_off, u32 lo_off, u32 hi_nbytes, u32 lo_nbytes,
unsigned int flags)
{
- return sys_sync_file_range(fd, (loff_t)hi_off << 32 | lo_off,
+ return ksys_sync_file_range(fd, (loff_t)hi_off << 32 | lo_off,
(loff_t)hi_nbytes << 32 | lo_nbytes, flags);
}
asmlinkage long parisc_fallocate(int fd, int mode, u32 offhi, u32 offlo,
u32 lenhi, u32 lenlo)
{
- return sys_fallocate(fd, mode, ((u64)offhi << 32) | offlo,
- ((u64)lenhi << 32) | lenlo);
+ return ksys_fallocate(fd, mode, ((u64)offhi << 32) | offlo,
+ ((u64)lenhi << 32) | lenlo);
}
long parisc_personality(unsigned long personality)
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index ef6549e57157..26d5d2a5b8e9 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -101,7 +101,8 @@ $(addprefix $(obj)/,$(zlib-y)): \
libfdt := fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
libfdtheader := fdt.h libfdt.h libfdt_internal.h
-$(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o opal.o): \
+$(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o opal.o \
+ treeboot-akebono.o treeboot-currituck.o treeboot-iss4xx.o): \
$(addprefix $(obj)/,$(libfdtheader))
src-wlib-y := string.S crt0.S stdio.c decompress.c main.c \
diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h
index 0abeb0e2d616..37671feb2bf6 100644
--- a/arch/powerpc/include/asm/book3s/64/mmu.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu.h
@@ -87,6 +87,9 @@ typedef struct {
/* Number of bits in the mm_cpumask */
atomic_t active_cpus;
+ /* Number of users of the external (Nest) MMU */
+ atomic_t copros;
+
/* NPU NMMU context */
struct npu_context *npu_context;
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
index 8eea90f80e45..19b45ba6caf9 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
@@ -47,9 +47,6 @@ extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmad
#endif
extern void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr);
extern void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr);
-extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
- unsigned long page_size);
-extern void radix__flush_tlb_lpid(unsigned long lpid);
extern void radix__flush_tlb_all(void);
extern void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
unsigned long address);
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index a2c5c95882cf..2e2bacbdf6ed 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -203,6 +203,7 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
+#define CPU_FTR_P9_TLBIE_BUG LONG_ASM_CONST(0x2000000000000000)
#define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000)
#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x8000000000000000)
@@ -465,7 +466,7 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | \
- CPU_FTR_PKEY)
+ CPU_FTR_PKEY | CPU_FTR_P9_TLBIE_BUG)
#define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
(~CPU_FTR_SAO))
#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
diff --git a/arch/powerpc/include/asm/dma-direct.h b/arch/powerpc/include/asm/dma-direct.h
index a5b59c765426..7702875aabb7 100644
--- a/arch/powerpc/include/asm/dma-direct.h
+++ b/arch/powerpc/include/asm/dma-direct.h
@@ -17,12 +17,12 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
return addr + size - 1 <= *dev->dma_mask;
}
-static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
return paddr + get_dma_offset(dev);
}
-static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
return daddr - get_dma_offset(dev);
}
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index 051b3d63afe3..3a15b6db9501 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -92,15 +92,23 @@ static inline void dec_mm_active_cpus(struct mm_struct *mm)
static inline void mm_context_add_copro(struct mm_struct *mm)
{
/*
- * On hash, should only be called once over the lifetime of
- * the context, as we can't decrement the active cpus count
- * and flush properly for the time being.
+ * If any copro is in use, increment the active CPU count
+ * in order to force TLB invalidations to be global as to
+ * propagate to the Nest MMU.
*/
- inc_mm_active_cpus(mm);
+ if (atomic_inc_return(&mm->context.copros) == 1)
+ inc_mm_active_cpus(mm);
}
static inline void mm_context_remove_copro(struct mm_struct *mm)
{
+ int c;
+
+ c = atomic_dec_if_positive(&mm->context.copros);
+
+ /* Detect imbalance between add and remove */
+ WARN_ON(c < 0);
+
/*
* Need to broadcast a global flush of the full mm before
* decrementing active_cpus count, as the next TLBI may be
@@ -111,7 +119,7 @@ static inline void mm_context_remove_copro(struct mm_struct *mm)
* for the time being. Invalidations will remain global if
* used on hash.
*/
- if (radix_enabled()) {
+ if (c == 0 && radix_enabled()) {
flush_all_mm(mm);
dec_mm_active_cpus(mm);
}
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 945e2c29ad2d..8ca5d5b74618 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -709,6 +709,9 @@ static __init void cpufeatures_cpu_quirks(void)
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1;
else if ((version & 0xffffefff) == 0x004e0201)
cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
+
+ if ((version & 0xffff0000) == 0x004e0000)
+ cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG;
}
static void __init cpufeatures_setup_finished(void)
@@ -720,6 +723,9 @@ static void __init cpufeatures_setup_finished(void)
cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
}
+ /* Make sure powerpc_base_platform is non-NULL */
+ powerpc_base_platform = cur_cpu_spec->platform;
+
system_registers.lpcr = mfspr(SPRN_LPCR);
system_registers.hfscr = mfspr(SPRN_HFSCR);
system_registers.fscr = mfspr(SPRN_FSCR);
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 3ac87e53b3da..1ecfd8ffb098 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -706,7 +706,7 @@ EXC_COMMON_BEGIN(bad_addr_slb)
ld r3, PACA_EXSLB+EX_DAR(r13)
std r3, _DAR(r1)
beq cr6, 2f
- li r10, 0x480 /* fix trap number for I-SLB miss */
+ li r10, 0x481 /* fix trap number for I-SLB miss */
std r10, _TRAP(r1)
2: bl save_nvgprs
addi r3, r1, STACK_FRAME_OVERHEAD
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index f88038847790..061aa0f47bb1 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -476,6 +476,14 @@ void force_external_irq_replay(void)
*/
WARN_ON(!arch_irqs_disabled());
+ /*
+ * Interrupts must always be hard disabled before irq_happened is
+ * modified (to prevent lost update in case of interrupt between
+ * load and store).
+ */
+ __hard_irq_disable();
+ local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
+
/* Indicate in the PACA that we have an interrupt to replay */
local_paca->irq_happened |= PACA_IRQ_EE;
}
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index d22c41c26bb3..acf4b2e0530c 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -874,7 +874,6 @@ struct ibm_arch_vec __cacheline_aligned ibm_architecture_vec = {
.mmu = 0,
.hash_ext = 0,
.radix_ext = 0,
- .byte22 = 0,
},
/* option vector 6: IBM PAPR hints */
diff --git a/arch/powerpc/kernel/sys_ppc32.c b/arch/powerpc/kernel/sys_ppc32.c
index 15f216d022e2..c11c73373691 100644
--- a/arch/powerpc/kernel/sys_ppc32.c
+++ b/arch/powerpc/kernel/sys_ppc32.c
@@ -77,44 +77,44 @@ unsigned long compat_sys_mmap2(unsigned long addr, size_t len,
compat_ssize_t compat_sys_pread64(unsigned int fd, char __user *ubuf, compat_size_t count,
u32 reg6, u32 poshi, u32 poslo)
{
- return sys_pread64(fd, ubuf, count, ((loff_t)poshi << 32) | poslo);
+ return ksys_pread64(fd, ubuf, count, ((loff_t)poshi << 32) | poslo);
}
compat_ssize_t compat_sys_pwrite64(unsigned int fd, const char __user *ubuf, compat_size_t count,
u32 reg6, u32 poshi, u32 poslo)
{
- return sys_pwrite64(fd, ubuf, count, ((loff_t)poshi << 32) | poslo);
+ return ksys_pwrite64(fd, ubuf, count, ((loff_t)poshi << 32) | poslo);
}
compat_ssize_t compat_sys_readahead(int fd, u32 r4, u32 offhi, u32 offlo, u32 count)
{
- return sys_readahead(fd, ((loff_t)offhi << 32) | offlo, count);
+ return ksys_readahead(fd, ((loff_t)offhi << 32) | offlo, count);
}
asmlinkage int compat_sys_truncate64(const char __user * path, u32 reg4,
unsigned long high, unsigned long low)
{
- return sys_truncate(path, (high << 32) | low);
+ return ksys_truncate(path, (high << 32) | low);
}
asmlinkage long compat_sys_fallocate(int fd, int mode, u32 offhi, u32 offlo,
u32 lenhi, u32 lenlo)
{
- return sys_fallocate(fd, mode, ((loff_t)offhi << 32) | offlo,
+ return ksys_fallocate(fd, mode, ((loff_t)offhi << 32) | offlo,
((loff_t)lenhi << 32) | lenlo);
}
asmlinkage int compat_sys_ftruncate64(unsigned int fd, u32 reg4, unsigned long high,
unsigned long low)
{
- return sys_ftruncate(fd, (high << 32) | low);
+ return ksys_ftruncate(fd, (high << 32) | low);
}
long ppc32_fadvise64(int fd, u32 unused, u32 offset_high, u32 offset_low,
size_t len, int advice)
{
- return sys_fadvise64(fd, (u64)offset_high << 32 | offset_low, len,
- advice);
+ return ksys_fadvise64_64(fd, (u64)offset_high << 32 | offset_low, len,
+ advice);
}
asmlinkage long compat_sys_sync_file_range2(int fd, unsigned int flags,
@@ -124,5 +124,5 @@ asmlinkage long compat_sys_sync_file_range2(int fd, unsigned int flags,
loff_t offset = ((loff_t)offset_hi << 32) | offset_lo;
loff_t nbytes = ((loff_t)nbytes_hi << 32) | nbytes_lo;
- return sys_sync_file_range(fd, offset, nbytes, flags);
+ return ksys_sync_file_range(fd, offset, nbytes, flags);
}
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
index a877bf8269fe..1ef3b80b62a6 100644
--- a/arch/powerpc/kernel/syscalls.c
+++ b/arch/powerpc/kernel/syscalls.c
@@ -57,7 +57,7 @@ static inline long do_mmap2(unsigned long addr, size_t len,
off >>= shift;
}
- ret = sys_mmap_pgoff(addr, len, prot, flags, fd, off);
+ ret = ksys_mmap_pgoff(addr, len, prot, flags, fd, off);
out:
return ret;
}
@@ -119,8 +119,8 @@ long ppc64_personality(unsigned long personality)
long ppc_fadvise64_64(int fd, int advice, u32 offset_high, u32 offset_low,
u32 len_high, u32 len_low)
{
- return sys_fadvise64(fd, (u64)offset_high << 32 | offset_low,
- (u64)len_high << 32 | len_low, advice);
+ return ksys_fadvise64_64(fd, (u64)offset_high << 32 | offset_low,
+ (u64)len_high << 32 | len_low, advice);
}
long sys_switch_endian(void)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c
index 0c854816e653..5d9bafe9a371 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_radix.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c
@@ -157,6 +157,9 @@ static void kvmppc_radix_tlbie_page(struct kvm *kvm, unsigned long addr,
asm volatile("ptesync": : :"memory");
asm volatile(PPC_TLBIE_5(%0, %1, 0, 0, 1)
: : "r" (addr), "r" (kvm->arch.lpid) : "memory");
+ if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG))
+ asm volatile(PPC_TLBIE_5(%0, %1, 0, 0, 1)
+ : : "r" (addr), "r" (kvm->arch.lpid) : "memory");
asm volatile("ptesync": : :"memory");
}
@@ -195,6 +198,12 @@ static void kvmppc_pte_free(pte_t *ptep)
kmem_cache_free(kvm_pte_cache, ptep);
}
+/* Like pmd_huge() and pmd_large(), but works regardless of config options */
+static inline int pmd_is_leaf(pmd_t pmd)
+{
+ return !!(pmd_val(pmd) & _PAGE_PTE);
+}
+
static int kvmppc_create_pte(struct kvm *kvm, pte_t pte, unsigned long gpa,
unsigned int level, unsigned long mmu_seq)
{
@@ -219,7 +228,7 @@ static int kvmppc_create_pte(struct kvm *kvm, pte_t pte, unsigned long gpa,
else
new_pmd = pmd_alloc_one(kvm->mm, gpa);
- if (level == 0 && !(pmd && pmd_present(*pmd)))
+ if (level == 0 && !(pmd && pmd_present(*pmd) && !pmd_is_leaf(*pmd)))
new_ptep = kvmppc_pte_alloc();
/* Check if we might have been invalidated; let the guest retry if so */
@@ -244,12 +253,30 @@ static int kvmppc_create_pte(struct kvm *kvm, pte_t pte, unsigned long gpa,
new_pmd = NULL;
}
pmd = pmd_offset(pud, gpa);
- if (pmd_large(*pmd)) {
- /* Someone else has instantiated a large page here; retry */
- ret = -EAGAIN;
- goto out_unlock;
- }
- if (level == 1 && !pmd_none(*pmd)) {
+ if (pmd_is_leaf(*pmd)) {
+ unsigned long lgpa = gpa & PMD_MASK;
+
+ /*
+ * If we raced with another CPU which has just put
+ * a 2MB pte in after we saw a pte page, try again.
+ */
+ if (level == 0 && !new_ptep) {
+ ret = -EAGAIN;
+ goto out_unlock;
+ }
+ /* Valid 2MB page here already, remove it */
+ old = kvmppc_radix_update_pte(kvm, pmdp_ptep(pmd),
+ ~0UL, 0, lgpa, PMD_SHIFT);
+ kvmppc_radix_tlbie_page(kvm, lgpa, PMD_SHIFT);
+ if (old & _PAGE_DIRTY) {
+ unsigned long gfn = lgpa >> PAGE_SHIFT;
+ struct kvm_memory_slot *memslot;
+ memslot = gfn_to_memslot(kvm, gfn);
+ if (memslot && memslot->dirty_bitmap)
+ kvmppc_update_dirty_map(memslot,
+ gfn, PMD_SIZE);
+ }
+ } else if (level == 1 && !pmd_none(*pmd)) {
/*
* There's a page table page here, but we wanted
* to install a large page. Tell the caller and let
@@ -412,28 +439,24 @@ int kvmppc_book3s_radix_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
} else {
page = pages[0];
pfn = page_to_pfn(page);
- if (PageHuge(page)) {
- page = compound_head(page);
- pte_size <<= compound_order(page);
+ if (PageCompound(page)) {
+ pte_size <<= compound_order(compound_head(page));
/* See if we can insert a 2MB large-page PTE here */
if (pte_size >= PMD_SIZE &&
- (gpa & PMD_MASK & PAGE_MASK) ==
- (hva & PMD_MASK & PAGE_MASK)) {
+ (gpa & (PMD_SIZE - PAGE_SIZE)) ==
+ (hva & (PMD_SIZE - PAGE_SIZE))) {
level = 1;
pfn &= ~((PMD_SIZE >> PAGE_SHIFT) - 1);
}
}
/* See if we can provide write access */
if (writing) {
- /*
- * We assume gup_fast has set dirty on the host PTE.
- */
pgflags |= _PAGE_WRITE;
} else {
local_irq_save(flags);
ptep = find_current_mm_pte(current->mm->pgd,
hva, NULL, NULL);
- if (ptep && pte_write(*ptep) && pte_dirty(*ptep))
+ if (ptep && pte_write(*ptep))
pgflags |= _PAGE_WRITE;
local_irq_restore(flags);
}
@@ -459,18 +482,15 @@ int kvmppc_book3s_radix_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
pte = pfn_pte(pfn, __pgprot(pgflags));
ret = kvmppc_create_pte(kvm, pte, gpa, level, mmu_seq);
}
- if (ret == 0 || ret == -EAGAIN)
- ret = RESUME_GUEST;
if (page) {
- /*
- * We drop pages[0] here, not page because page might
- * have been set to the head page of a compound, but
- * we have to drop the reference on the correct tail
- * page to match the get inside gup()
- */
- put_page(pages[0]);
+ if (!ret && (pgflags & _PAGE_WRITE))
+ set_page_dirty_lock(page);
+ put_page(page);
}
+
+ if (ret == 0 || ret == -EAGAIN)
+ ret = RESUME_GUEST;
return ret;
}
@@ -644,7 +664,7 @@ void kvmppc_free_radix(struct kvm *kvm)
continue;
pmd = pmd_offset(pud, 0);
for (im = 0; im < PTRS_PER_PMD; ++im, ++pmd) {
- if (pmd_huge(*pmd)) {
+ if (pmd_is_leaf(*pmd)) {
pmd_clear(pmd);
continue;
}
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 89707354c2ef..9cb9448163c4 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -2885,7 +2885,7 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
*/
trace_hardirqs_on();
- guest_enter();
+ guest_enter_irqoff();
srcu_idx = srcu_read_lock(&vc->kvm->srcu);
@@ -2893,8 +2893,6 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
srcu_read_unlock(&vc->kvm->srcu, srcu_idx);
- guest_exit();
-
trace_hardirqs_off();
set_irq_happened(trap);
@@ -2937,6 +2935,7 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
kvmppc_set_host_core(pcpu);
local_irq_enable();
+ guest_exit();
/* Let secondaries go back to the offline loop */
for (i = 0; i < controlled_threads; ++i) {
@@ -3656,15 +3655,17 @@ static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu)
goto up_out;
psize = vma_kernel_pagesize(vma);
- porder = __ilog2(psize);
up_read(&current->mm->mmap_sem);
/* We can handle 4k, 64k or 16M pages in the VRMA */
- err = -EINVAL;
- if (!(psize == 0x1000 || psize == 0x10000 ||
- psize == 0x1000000))
- goto out_srcu;
+ if (psize >= 0x1000000)
+ psize = 0x1000000;
+ else if (psize >= 0x10000)
+ psize = 0x10000;
+ else
+ psize = 0x1000;
+ porder = __ilog2(psize);
senc = slb_pgsize_encoding(psize);
kvm->arch.vrma_slb_v = senc | SLB_VSID_B_1T |
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 8888e625a999..e1c083fbe434 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -473,6 +473,17 @@ static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
trace_tlbie(kvm->arch.lpid, 0, rbvalues[i],
kvm->arch.lpid, 0, 0, 0);
}
+
+ if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
+ /*
+ * Need the extra ptesync to make sure we don't
+ * re-order the tlbie
+ */
+ asm volatile("ptesync": : :"memory");
+ asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
+ "r" (rbvalues[0]), "r" (kvm->arch.lpid));
+ }
+
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
kvm->arch.tlbie_lock = 0;
} else {
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index f31f357b8c5a..f86a20270e50 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -320,7 +320,6 @@ kvm_novcpu_exit:
stw r12, STACK_SLOT_TRAP(r1)
bl kvmhv_commence_exit
nop
- lwz r12, STACK_SLOT_TRAP(r1)
b kvmhv_switch_to_host
/*
@@ -1220,6 +1219,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
secondary_too_late:
li r12, 0
+ stw r12, STACK_SLOT_TRAP(r1)
cmpdi r4, 0
beq 11f
stw r12, VCPU_TRAP(r4)
@@ -1557,13 +1557,31 @@ mc_cont:
ptesync
3: stw r5,VCPU_SLB_MAX(r9)
+ /* load host SLB entries */
+BEGIN_MMU_FTR_SECTION
+ b 0f
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
+ ld r8,PACA_SLBSHADOWPTR(r13)
+
+ .rept SLB_NUM_BOLTED
+ li r3, SLBSHADOW_SAVEAREA
+ LDX_BE r5, r8, r3
+ addi r3, r3, 8
+ LDX_BE r6, r8, r3
+ andis. r7,r5,SLB_ESID_V@h
+ beq 1f
+ slbmte r6,r5
+1: addi r8,r8,16
+ .endr
+0:
+
guest_bypass:
+ stw r12, STACK_SLOT_TRAP(r1)
mr r3, r12
/* Increment exit count, poke other threads to exit */
bl kvmhv_commence_exit
nop
ld r9, HSTATE_KVM_VCPU(r13)
- lwz r12, VCPU_TRAP(r9)
/* Stop others sending VCPU interrupts to this physical CPU */
li r0, -1
@@ -1898,6 +1916,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
* POWER7/POWER8 guest -> host partition switch code.
* We don't have to lock against tlbies but we do
* have to coordinate the hardware threads.
+ * Here STACK_SLOT_TRAP(r1) contains the trap number.
*/
kvmhv_switch_to_host:
/* Secondary threads wait for primary to do partition switch */
@@ -1950,12 +1969,12 @@ BEGIN_FTR_SECTION
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
/* If HMI, call kvmppc_realmode_hmi_handler() */
+ lwz r12, STACK_SLOT_TRAP(r1)
cmpwi r12, BOOK3S_INTERRUPT_HMI
bne 27f
bl kvmppc_realmode_hmi_handler
nop
cmpdi r3, 0
- li r12, BOOK3S_INTERRUPT_HMI
/*
* At this point kvmppc_realmode_hmi_handler may have resync-ed
* the TB, and if it has, we must not subtract the guest timebase
@@ -2008,10 +2027,8 @@ BEGIN_FTR_SECTION
lwz r8, KVM_SPLIT_DO_RESTORE(r3)
cmpwi r8, 0
beq 47f
- stw r12, STACK_SLOT_TRAP(r1)
bl kvmhv_p9_restore_lpcr
nop
- lwz r12, STACK_SLOT_TRAP(r1)
b 48f
47:
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
@@ -2019,23 +2036,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
mtspr SPRN_LPCR,r8
isync
48:
- /* load host SLB entries */
-BEGIN_MMU_FTR_SECTION
- b 0f
-END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
- ld r8,PACA_SLBSHADOWPTR(r13)
-
- .rept SLB_NUM_BOLTED
- li r3, SLBSHADOW_SAVEAREA
- LDX_BE r5, r8, r3
- addi r3, r3, 8
- LDX_BE r6, r8, r3
- andis. r7,r5,SLB_ESID_V@h
- beq 1f
- slbmte r6,r5
-1: addi r8,r8,16
- .endr
-0:
#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
/* Finish timing, if we have a vcpu */
ld r4, HSTATE_KVM_VCPU(r13)
@@ -2049,6 +2049,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
li r0, KVM_GUEST_MODE_NONE
stb r0, HSTATE_IN_GUEST(r13)
+ lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
ld r0, SFS+PPC_LR_STKOFF(r1)
addi r1, r1, SFS
mtlr r0
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 403e642c78f5..52c205373986 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -1345,7 +1345,7 @@ static int kvmppc_emulate_mmio_vsx_loadstore(struct kvm_vcpu *vcpu,
int kvmppc_handle_load128_by2x64(struct kvm_run *run, struct kvm_vcpu *vcpu,
unsigned int rt, int is_default_endian)
{
- enum emulation_result emulated;
+ enum emulation_result emulated = EMULATE_DONE;
while (vcpu->arch.mmio_vmx_copy_nums) {
emulated = __kvmppc_handle_load(run, vcpu, rt, 8,
@@ -1608,7 +1608,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
kvm_sigset_deactivate(vcpu);
+#ifdef CONFIG_ALTIVEC
out:
+#endif
vcpu_put(vcpu);
return r;
}
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index a0675e91ad7d..656933c85925 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -201,6 +201,15 @@ static inline unsigned long ___tlbie(unsigned long vpn, int psize,
return va;
}
+static inline void fixup_tlbie(unsigned long vpn, int psize, int apsize, int ssize)
+{
+ if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
+ /* Need the extra ptesync to ensure we don't reorder tlbie*/
+ asm volatile("ptesync": : :"memory");
+ ___tlbie(vpn, psize, apsize, ssize);
+ }
+}
+
static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
{
unsigned long rb;
@@ -278,6 +287,7 @@ static inline void tlbie(unsigned long vpn, int psize, int apsize,
asm volatile("ptesync": : :"memory");
} else {
__tlbie(vpn, psize, apsize, ssize);
+ fixup_tlbie(vpn, psize, apsize, ssize);
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
if (lock_tlbie && !use_local)
@@ -771,7 +781,7 @@ static void native_hpte_clear(void)
*/
static void native_flush_hash_range(unsigned long number, int local)
{
- unsigned long vpn;
+ unsigned long vpn = 0;
unsigned long hash, index, hidx, shift, slot;
struct hash_pte *hptep;
unsigned long hpte_v;
@@ -843,6 +853,10 @@ static void native_flush_hash_range(unsigned long number, int local)
__tlbie(vpn, psize, psize, ssize);
} pte_iterate_hashed_end();
}
+ /*
+ * Just do one more with the last used values.
+ */
+ fixup_tlbie(vpn, psize, psize, ssize);
asm volatile("eieio; tlbsync; ptesync":::"memory");
if (lock_tlbie)
diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c
index 929d9ef7083f..3f980baade4c 100644
--- a/arch/powerpc/mm/mmu_context_book3s64.c
+++ b/arch/powerpc/mm/mmu_context_book3s64.c
@@ -173,6 +173,7 @@ int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
mm_iommu_init(mm);
#endif
atomic_set(&mm->context.active_cpus, 0);
+ atomic_set(&mm->context.copros, 0);
return 0;
}
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 28c980eb4422..adf469f312f2 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -481,6 +481,7 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
"r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
}
+ /* do we need fixup here ?*/
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
}
EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry);
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 71d1b19ad1c0..a07f5372a4bf 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -119,6 +119,49 @@ static inline void __tlbie_pid(unsigned long pid, unsigned long ric)
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
+static inline void __tlbiel_va(unsigned long va, unsigned long pid,
+ unsigned long ap, unsigned long ric)
+{
+ unsigned long rb,rs,prs,r;
+
+ rb = va & ~(PPC_BITMASK(52, 63));
+ rb |= ap << PPC_BITLSHIFT(58);
+ rs = pid << PPC_BITLSHIFT(31);
+ prs = 1; /* process scoped */
+ r = 1; /* raidx format */
+
+ asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
+ : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
+ trace_tlbie(0, 1, rb, rs, ric, prs, r);
+}
+
+static inline void __tlbie_va(unsigned long va, unsigned long pid,
+ unsigned long ap, unsigned long ric)
+{
+ unsigned long rb,rs,prs,r;
+
+ rb = va & ~(PPC_BITMASK(52, 63));
+ rb |= ap << PPC_BITLSHIFT(58);
+ rs = pid << PPC_BITLSHIFT(31);
+ prs = 1; /* process scoped */
+ r = 1; /* raidx format */
+
+ asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+ : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
+ trace_tlbie(0, 0, rb, rs, ric, prs, r);
+}
+
+static inline void fixup_tlbie(void)
+{
+ unsigned long pid = 0;
+ unsigned long va = ((1UL << 52) - 1);
+
+ if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
+ asm volatile("ptesync": : :"memory");
+ __tlbie_va(va, pid, mmu_get_ap(MMU_PAGE_64K), RIC_FLUSH_TLB);
+ }
+}
+
/*
* We use 128 set in radix mode and 256 set in hpt mode.
*/
@@ -151,24 +194,25 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
{
asm volatile("ptesync": : :"memory");
- __tlbie_pid(pid, ric);
- asm volatile("eieio; tlbsync; ptesync": : :"memory");
-}
-static inline void __tlbiel_va(unsigned long va, unsigned long pid,
- unsigned long ap, unsigned long ric)
-{
- unsigned long rb,rs,prs,r;
-
- rb = va & ~(PPC_BITMASK(52, 63));
- rb |= ap << PPC_BITLSHIFT(58);
- rs = pid << PPC_BITLSHIFT(31);
- prs = 1; /* process scoped */
- r = 1; /* raidx format */
-
- asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
- : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
- trace_tlbie(0, 1, rb, rs, ric, prs, r);
+ /*
+ * Workaround the fact that the "ric" argument to __tlbie_pid
+ * must be a compile-time contraint to match the "i" constraint
+ * in the asm statement.
+ */
+ switch (ric) {
+ case RIC_FLUSH_TLB:
+ __tlbie_pid(pid, RIC_FLUSH_TLB);
+ break;
+ case RIC_FLUSH_PWC:
+ __tlbie_pid(pid, RIC_FLUSH_PWC);
+ break;
+ case RIC_FLUSH_ALL:
+ default:
+ __tlbie_pid(pid, RIC_FLUSH_ALL);
+ }
+ fixup_tlbie();
+ asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
static inline void __tlbiel_va_range(unsigned long start, unsigned long end,
@@ -203,22 +247,6 @@ static inline void _tlbiel_va_range(unsigned long start, unsigned long end,
asm volatile("ptesync": : :"memory");
}
-static inline void __tlbie_va(unsigned long va, unsigned long pid,
- unsigned long ap, unsigned long ric)
-{
- unsigned long rb,rs,prs,r;
-
- rb = va & ~(PPC_BITMASK(52, 63));
- rb |= ap << PPC_BITLSHIFT(58);
- rs = pid << PPC_BITLSHIFT(31);
- prs = 1; /* process scoped */
- r = 1; /* raidx format */
-
- asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
- : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
- trace_tlbie(0, 0, rb, rs, ric, prs, r);
-}
-
static inline void __tlbie_va_range(unsigned long start, unsigned long end,
unsigned long pid, unsigned long page_size,
unsigned long psize)
@@ -237,6 +265,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
asm volatile("ptesync": : :"memory");
__tlbie_va(va, pid, ap, ric);
+ fixup_tlbie();
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
@@ -248,6 +277,7 @@ static inline void _tlbie_va_range(unsigned long start, unsigned long end,
if (also_pwc)
__tlbie_pid(pid, RIC_FLUSH_PWC);
__tlbie_va_range(start, end, pid, page_size, psize);
+ fixup_tlbie();
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
@@ -311,6 +341,16 @@ void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmadd
}
EXPORT_SYMBOL(radix__local_flush_tlb_page);
+static bool mm_needs_flush_escalation(struct mm_struct *mm)
+{
+ /*
+ * P9 nest MMU has issues with the page walk cache
+ * caching PTEs and not flushing them properly when
+ * RIC = 0 for a PID/LPID invalidate
+ */
+ return atomic_read(&mm->context.copros) != 0;
+}
+
#ifdef CONFIG_SMP
void radix__flush_tlb_mm(struct mm_struct *mm)
{
@@ -321,9 +361,12 @@ void radix__flush_tlb_mm(struct mm_struct *mm)
return;
preempt_disable();
- if (!mm_is_thread_local(mm))
- _tlbie_pid(pid, RIC_FLUSH_TLB);
- else
+ if (!mm_is_thread_local(mm)) {
+ if (mm_needs_flush_escalation(mm))
+ _tlbie_pid(pid, RIC_FLUSH_ALL);
+ else
+ _tlbie_pid(pid, RIC_FLUSH_TLB);
+ } else
_tlbiel_pid(pid, RIC_FLUSH_TLB);
preempt_enable();
}
@@ -435,10 +478,14 @@ void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
}
if (full) {
- if (local)
+ if (local) {
_tlbiel_pid(pid, RIC_FLUSH_TLB);
- else
- _tlbie_pid(pid, RIC_FLUSH_TLB);
+ } else {
+ if (mm_needs_flush_escalation(mm))
+ _tlbie_pid(pid, RIC_FLUSH_ALL);
+ else
+ _tlbie_pid(pid, RIC_FLUSH_TLB);
+ }
} else {
bool hflush = false;
unsigned long hstart, hend;
@@ -465,6 +512,7 @@ void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
if (hflush)
__tlbie_va_range(hstart, hend, pid,
HPAGE_PMD_SIZE, MMU_PAGE_2M);
+ fixup_tlbie();
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
}
@@ -548,6 +596,9 @@ static inline void __radix__flush_tlb_range_psize(struct mm_struct *mm,
}
if (full) {
+ if (!local && mm_needs_flush_escalation(mm))
+ also_pwc = true;
+
if (local)
_tlbiel_pid(pid, also_pwc ? RIC_FLUSH_ALL : RIC_FLUSH_TLB);
else
@@ -603,46 +654,6 @@ void radix__flush_tlb_collapsed_pmd(struct mm_struct *mm, unsigned long addr)
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
-void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
- unsigned long page_size)
-{
- unsigned long rb,rs,prs,r;
- unsigned long ap;
- unsigned long ric = RIC_FLUSH_TLB;
-
- ap = mmu_get_ap(radix_get_mmu_psize(page_size));
- rb = gpa & ~(PPC_BITMASK(52, 63));
- rb |= ap << PPC_BITLSHIFT(58);
- rs = lpid & ((1UL << 32) - 1);
- prs = 0; /* process scoped */
- r = 1; /* raidx format */
-
- asm volatile("ptesync": : :"memory");
- asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
- : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
- asm volatile("eieio; tlbsync; ptesync": : :"memory");
- trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
-}
-EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
-
-void radix__flush_tlb_lpid(unsigned long lpid)
-{
- unsigned long rb,rs,prs,r;
- unsigned long ric = RIC_FLUSH_ALL;
-
- rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
- rs = lpid & ((1UL << 32) - 1);
- prs = 0; /* partition scoped */
- r = 1; /* raidx format */
-
- asm volatile("ptesync": : :"memory");
- asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
- : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
- asm volatile("eieio; tlbsync; ptesync": : :"memory");
- trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
-}
-EXPORT_SYMBOL(radix__flush_tlb_lpid);
-
void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index f89bbd54ecec..f8908ea4ea73 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1426,7 +1426,7 @@ static int collect_events(struct perf_event *group, int max_count,
flags[n] = group->hw.event_base;
events[n++] = group->hw.config;
}
- list_for_each_entry(event, &group->sibling_list, group_entry) {
+ for_each_sibling_event(event, group) {
if (event->pmu->task_ctx_nr == perf_hw_context &&
event->state != PERF_EVENT_STATE_OFF) {
if (n >= max_count)
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 5d747b4cb8ee..85f1d18e5fd3 100644
--- a/arch/powerpc/perf/core-fsl-emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
@@ -277,7 +277,7 @@ static int collect_events(struct perf_event *group, int max_count,
ctrs[n] = group;
n++;
}
- list_for_each_entry(event, &group->sibling_list, group_entry) {
+ for_each_sibling_event(event, group) {
if (!is_software_event(event) &&
event->state != PERF_EVENT_STATE_OFF) {
if (n >= max_count)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 79c78668258e..f7181ed8aafc 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -24,8 +24,8 @@ static long riscv_sys_mmap(unsigned long addr, unsigned long len,
{
if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- offset >> (PAGE_SHIFT - page_shift_offset));
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - page_shift_offset));
}
#ifdef CONFIG_64BIT
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index 79b7a3438d54..8ac38d51ed7d 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -89,18 +89,18 @@
COMPAT_SYSCALL_DEFINE3(s390_chown16, const char __user *, filename,
u16, user, u16, group)
{
- return sys_chown(filename, low2highuid(user), low2highgid(group));
+ return ksys_chown(filename, low2highuid(user), low2highgid(group));
}
COMPAT_SYSCALL_DEFINE3(s390_lchown16, const char __user *,
filename, u16, user, u16, group)
{
- return sys_lchown(filename, low2highuid(user), low2highgid(group));
+ return ksys_lchown(filename, low2highuid(user), low2highgid(group));
}
COMPAT_SYSCALL_DEFINE3(s390_fchown16, unsigned int, fd, u16, user, u16, group)
{
- return sys_fchown(fd, low2highuid(user), low2highgid(group));
+ return ksys_fchown(fd, low2highuid(user), low2highgid(group));
}
COMPAT_SYSCALL_DEFINE2(s390_setregid16, u16, rgid, u16, egid)
@@ -302,12 +302,12 @@ COMPAT_SYSCALL_DEFINE5(s390_ipc, uint, call, int, first, compat_ulong_t, second,
COMPAT_SYSCALL_DEFINE3(s390_truncate64, const char __user *, path, u32, high, u32, low)
{
- return sys_truncate(path, (unsigned long)high << 32 | low);
+ return ksys_truncate(path, (unsigned long)high << 32 | low);
}
COMPAT_SYSCALL_DEFINE3(s390_ftruncate64, unsigned int, fd, u32, high, u32, low)
{
- return sys_ftruncate(fd, (unsigned long)high << 32 | low);
+ return ksys_ftruncate(fd, (unsigned long)high << 32 | low);
}
COMPAT_SYSCALL_DEFINE5(s390_pread64, unsigned int, fd, char __user *, ubuf,
@@ -315,7 +315,7 @@ COMPAT_SYSCALL_DEFINE5(s390_pread64, unsigned int, fd, char __user *, ubuf,
{
if ((compat_ssize_t) count < 0)
return -EINVAL;
- return sys_pread64(fd, ubuf, count, (unsigned long)high << 32 | low);
+ return ksys_pread64(fd, ubuf, count, (unsigned long)high << 32 | low);
}
COMPAT_SYSCALL_DEFINE5(s390_pwrite64, unsigned int, fd, const char __user *, ubuf,
@@ -323,12 +323,12 @@ COMPAT_SYSCALL_DEFINE5(s390_pwrite64, unsigned int, fd, const char __user *, ubu
{
if ((compat_ssize_t) count < 0)
return -EINVAL;
- return sys_pwrite64(fd, ubuf, count, (unsigned long)high << 32 | low);
+ return ksys_pwrite64(fd, ubuf, count, (unsigned long)high << 32 | low);
}
COMPAT_SYSCALL_DEFINE4(s390_readahead, int, fd, u32, high, u32, low, s32, count)
{
- return sys_readahead(fd, (unsigned long)high << 32 | low, count);
+ return ksys_readahead(fd, (unsigned long)high << 32 | low, count);
}
struct stat64_emu31 {
@@ -442,8 +442,8 @@ COMPAT_SYSCALL_DEFINE1(s390_old_mmap, struct mmap_arg_struct_emu31 __user *, arg
return -EFAULT;
if (a.offset & ~PAGE_MASK)
return -EINVAL;
- return sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
- a.offset >> PAGE_SHIFT);
+ return ksys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
+ a.offset >> PAGE_SHIFT);
}
COMPAT_SYSCALL_DEFINE1(s390_mmap2, struct mmap_arg_struct_emu31 __user *, arg)
@@ -452,7 +452,7 @@ COMPAT_SYSCALL_DEFINE1(s390_mmap2, struct mmap_arg_struct_emu31 __user *, arg)
if (copy_from_user(&a, arg, sizeof(a)))
return -EFAULT;
- return sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
+ return ksys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
}
COMPAT_SYSCALL_DEFINE3(s390_read, unsigned int, fd, char __user *, buf, compat_size_t, count)
@@ -460,7 +460,7 @@ COMPAT_SYSCALL_DEFINE3(s390_read, unsigned int, fd, char __user *, buf, compat_s
if ((compat_ssize_t) count < 0)
return -EINVAL;
- return sys_read(fd, buf, count);
+ return ksys_read(fd, buf, count);
}
COMPAT_SYSCALL_DEFINE3(s390_write, unsigned int, fd, const char __user *, buf, compat_size_t, count)
@@ -468,7 +468,7 @@ COMPAT_SYSCALL_DEFINE3(s390_write, unsigned int, fd, const char __user *, buf, c
if ((compat_ssize_t) count < 0)
return -EINVAL;
- return sys_write(fd, buf, count);
+ return ksys_write(fd, buf, count);
}
/*
@@ -483,7 +483,8 @@ COMPAT_SYSCALL_DEFINE5(s390_fadvise64, int, fd, u32, high, u32, low, compat_size
advise = POSIX_FADV_DONTNEED;
else if (advise == 5)
advise = POSIX_FADV_NOREUSE;
- return sys_fadvise64(fd, (unsigned long)high << 32 | low, len, advise);
+ return ksys_fadvise64_64(fd, (unsigned long)high << 32 | low, len,
+ advise);
}
struct fadvise64_64_args {
@@ -503,19 +504,19 @@ COMPAT_SYSCALL_DEFINE1(s390_fadvise64_64, struct fadvise64_64_args __user *, arg
a.advice = POSIX_FADV_DONTNEED;
else if (a.advice == 5)
a.advice = POSIX_FADV_NOREUSE;
- return sys_fadvise64_64(a.fd, a.offset, a.len, a.advice);
+ return ksys_fadvise64_64(a.fd, a.offset, a.len, a.advice);
}
COMPAT_SYSCALL_DEFINE6(s390_sync_file_range, int, fd, u32, offhigh, u32, offlow,
u32, nhigh, u32, nlow, unsigned int, flags)
{
- return sys_sync_file_range(fd, ((loff_t)offhigh << 32) + offlow,
+ return ksys_sync_file_range(fd, ((loff_t)offhigh << 32) + offlow,
((u64)nhigh << 32) + nlow, flags);
}
COMPAT_SYSCALL_DEFINE6(s390_fallocate, int, fd, int, mode, u32, offhigh, u32, offlow,
u32, lenhigh, u32, lenlow)
{
- return sys_fallocate(fd, mode, ((loff_t)offhigh << 32) + offlow,
- ((u64)lenhigh << 32) + lenlow);
+ return ksys_fallocate(fd, mode, ((loff_t)offhigh << 32) + offlow,
+ ((u64)lenhigh << 32) + lenlow);
}
diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c
index 0090037ab148..31cefe0c28c0 100644
--- a/arch/s390/kernel/sys_s390.c
+++ b/arch/s390/kernel/sys_s390.c
@@ -53,7 +53,7 @@ SYSCALL_DEFINE1(mmap2, struct s390_mmap_arg_struct __user *, arg)
if (copy_from_user(&a, arg, sizeof(a)))
goto out;
- error = sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
+ error = ksys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
out:
return error;
}
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 77d7818130db..339ac0964590 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -86,6 +86,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
{ "deliver_prefix_signal", VCPU_STAT(deliver_prefix_signal) },
{ "deliver_restart_signal", VCPU_STAT(deliver_restart_signal) },
{ "deliver_program_interruption", VCPU_STAT(deliver_program_int) },
+ { "deliver_io_interrupt", VCPU_STAT(deliver_io_int) },
{ "exit_wait_state", VCPU_STAT(exit_wait_state) },
{ "instruction_epsw", VCPU_STAT(instruction_epsw) },
{ "instruction_gs", VCPU_STAT(instruction_gs) },
@@ -2146,6 +2147,7 @@ static void sca_add_vcpu(struct kvm_vcpu *vcpu)
/* we still need the basic sca for the ipte control */
vcpu->arch.sie_block->scaoh = (__u32)(((__u64)sca) >> 32);
vcpu->arch.sie_block->scaol = (__u32)(__u64)sca;
+ return;
}
read_lock(&vcpu->kvm->arch.sca_lock);
if (vcpu->kvm->arch.use_esca) {
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
deleted file mode 100644
index d881f99c9ddd..000000000000
--- a/arch/score/Kconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Machine selection"
-
-config SCORE
- def_bool y
- select GENERIC_IRQ_SHOW
- select GENERIC_IOMAP
- select GENERIC_ATOMIC64
- select HAVE_MEMBLOCK
- select HAVE_MEMBLOCK_NODE_MAP
- select ARCH_DISCARD_MEMBLOCK
- select GENERIC_CPU_DEVICES
- select GENERIC_CLOCKEVENTS
- select HAVE_MOD_ARCH_SPECIFIC
- select VIRT_TO_BUS
- select MODULES_USE_ELF_REL
- select CLONE_BACKWARDS
- select CPU_NO_EFFICIENT_FFS
-
-choice
- prompt "System type"
- default MACH_SPCT6600
-
-config ARCH_SCORE7
- bool "SCORE7 processor"
- select SYS_SUPPORTS_32BIT_KERNEL
-
-config MACH_SPCT6600
- bool "SPCT6600 series based machines"
- select SYS_SUPPORTS_32BIT_KERNEL
-
-config SCORE_SIM
- bool "Score simulator"
- select SYS_SUPPORTS_32BIT_KERNEL
-endchoice
-
-endmenu
-
-config NO_DMA
- bool
- default y
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config GENERIC_HWEIGHT
- def_bool y
-
-config GENERIC_CALIBRATE_DELAY
- def_bool y
-
-menu "Kernel type"
-
-config 32BIT
- def_bool y
-
-config ARCH_FLATMEM_ENABLE
- def_bool y
-
-source "mm/Kconfig"
-
-config MEMORY_START
- hex
- default 0xa0000000
-
-source "kernel/Kconfig.hz"
-source "kernel/Kconfig.preempt"
-
-endmenu
-
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-config LOCKDEP_SUPPORT
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-config MMU
- def_bool y
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/score/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
-
-config NO_IOMEM
- def_bool y
diff --git a/arch/score/Kconfig.debug b/arch/score/Kconfig.debug
deleted file mode 100644
index 041e51dcdafb..000000000000
--- a/arch/score/Kconfig.debug
+++ /dev/null
@@ -1,29 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-config TRACE_IRQFLAGS_SUPPORT
- bool
- default y
-
-source "lib/Kconfig.debug"
-
-config CMDLINE
- string "Default kernel command string"
- default ""
- help
- On some platforms, there is currently no way for the boot loader to
- pass arguments to the kernel. For these platforms, you can supply
- some command-line options at build time by entering them here. In
- other cases you can specify kernel args so that you don't have
- to set them up in board prom initialization routines.
-
-config RUNTIME_DEBUG
- bool "Enable run-time debugging"
- depends on DEBUG_KERNEL
- help
- If you say Y here, some debugging macros will do run-time checking.
- If you say N here, those macros will mostly turn to no-ops. See
- include/asm-score/debug.h for debugging macros.
- If unsure, say N.
-
-endmenu
diff --git a/arch/score/Makefile b/arch/score/Makefile
deleted file mode 100644
index 9e3e060290e0..000000000000
--- a/arch/score/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# arch/score/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-KBUILD_DEFCONFIG := spct6600_defconfig
-CROSS_COMPILE := score-linux-
-
-#
-# CPU-dependent compiler/assembler options for optimization.
-#
-cflags-y += -G0 -pipe -mel -mnhwloop -D__SCOREEL__ \
- -D__linux__ -ffunction-sections -ffreestanding
-
-#
-# Board-dependent options and extra files
-#
-KBUILD_AFLAGS += $(cflags-y)
-KBUILD_CFLAGS += $(cflags-y)
-KBUILD_AFLAGS_MODULE +=
-KBUILD_CFLAGS_MODULE +=
-LDFLAGS += --oformat elf32-littlescore
-LDFLAGS_vmlinux += -G0 -static -nostdlib
-
-head-y := arch/score/kernel/head.o
-libs-y += arch/score/lib/
-core-y += arch/score/kernel/ arch/score/mm/
-
-boot := arch/score/boot
-
-vmlinux.bin: vmlinux
- $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
-
-archclean:
- @$(MAKE) $(clean)=$(boot)
-
-define archhelp
- echo ' vmlinux.bin - Raw binary boot image'
- echo
- echo ' These will be default as appropriate for a configured platform.'
-endef
diff --git a/arch/score/boot/Makefile b/arch/score/boot/Makefile
deleted file mode 100644
index 0c5fbd0fb696..000000000000
--- a/arch/score/boot/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# arch/score/boot/Makefile
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-
-targets := vmlinux.bin
-
-$(obj)/vmlinux.bin: vmlinux FORCE
- $(call if_changed,objcopy)
- @echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
-
-clean-files += vmlinux.bin
diff --git a/arch/score/configs/spct6600_defconfig b/arch/score/configs/spct6600_defconfig
deleted file mode 100644
index b2d8802f43b4..000000000000
--- a/arch/score/configs/spct6600_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_HZ_100=y
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=12
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_ARPD=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-# CONFIG_MISC_DEVICES is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_STALDRV=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_PROC_KCORE=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SECURITY=y
-CONFIG_SECURITY_NETWORK=y
-CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/score/include/asm/Kbuild b/arch/score/include/asm/Kbuild
deleted file mode 100644
index 1a0ee72f6a7c..000000000000
--- a/arch/score/include/asm/Kbuild
+++ /dev/null
@@ -1,13 +0,0 @@
-generic-y += barrier.h
-generic-y += current.h
-generic-y += extable.h
-generic-y += irq_work.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += preempt.h
-generic-y += sections.h
-generic-y += trace_clock.h
-generic-y += xor.h
-generic-y += serial.h
-generic-y += word-at-a-time.h
-generic-y += kprobes.h
diff --git a/arch/score/include/asm/asm-offsets.h b/arch/score/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/score/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/score/include/asm/asmmacro.h b/arch/score/include/asm/asmmacro.h
deleted file mode 100644
index 7370a35d17d1..000000000000
--- a/arch/score/include/asm/asmmacro.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_ASMMACRO_H
-#define _ASM_SCORE_ASMMACRO_H
-
-#include <asm/asm-offsets.h>
-
-#ifdef __ASSEMBLY__
-
-.macro SAVE_ALL
- mfcr r30, cr0
- mv r31, r0
- nop
- /* if UMs == 1, change stack. */
- slli.c r30, r30, 28
- bpl 1f
- la r31, kernelsp
- lw r31, [r31]
-1:
- mv r30, r0
- addri r0, r31, -PT_SIZE
-
- sw r30, [r0, PT_R0]
- .set r1
- sw r1, [r0, PT_R1]
- .set nor1
- sw r2, [r0, PT_R2]
- sw r3, [r0, PT_R3]
- sw r4, [r0, PT_R4]
- sw r5, [r0, PT_R5]
- sw r6, [r0, PT_R6]
- sw r7, [r0, PT_R7]
-
- sw r8, [r0, PT_R8]
- sw r9, [r0, PT_R9]
- sw r10, [r0, PT_R10]
- sw r11, [r0, PT_R11]
- sw r12, [r0, PT_R12]
- sw r13, [r0, PT_R13]
- sw r14, [r0, PT_R14]
- sw r15, [r0, PT_R15]
-
- sw r16, [r0, PT_R16]
- sw r17, [r0, PT_R17]
- sw r18, [r0, PT_R18]
- sw r19, [r0, PT_R19]
- sw r20, [r0, PT_R20]
- sw r21, [r0, PT_R21]
- sw r22, [r0, PT_R22]
- sw r23, [r0, PT_R23]
-
- sw r24, [r0, PT_R24]
- sw r25, [r0, PT_R25]
- sw r25, [r0, PT_R25]
- sw r26, [r0, PT_R26]
- sw r27, [r0, PT_R27]
-
- sw r28, [r0, PT_R28]
- sw r29, [r0, PT_R29]
- orri r28, r0, 0x1fff
- li r31, 0x00001fff
- xor r28, r28, r31
-
- mfcehl r30, r31
- sw r30, [r0, PT_CEH]
- sw r31, [r0, PT_CEL]
-
- mfcr r31, cr0
- sw r31, [r0, PT_PSR]
-
- mfcr r31, cr1
- sw r31, [r0, PT_CONDITION]
-
- mfcr r31, cr2
- sw r31, [r0, PT_ECR]
-
- mfcr r31, cr5
- srli r31, r31, 1
- slli r31, r31, 1
- sw r31, [r0, PT_EPC]
-.endm
-
-.macro RESTORE_ALL_AND_RET
- mfcr r30, cr0
- srli r30, r30, 1
- slli r30, r30, 1
- mtcr r30, cr0
- nop
- nop
- nop
- nop
- nop
-
- .set r1
- ldis r1, 0x00ff
- and r30, r30, r1
- not r1, r1
- lw r31, [r0, PT_PSR]
- and r31, r31, r1
- .set nor1
- or r31, r31, r30
- mtcr r31, cr0
- nop
- nop
- nop
- nop
- nop
-
- lw r30, [r0, PT_CONDITION]
- mtcr r30, cr1
- nop
- nop
- nop
- nop
- nop
-
- lw r30, [r0, PT_CEH]
- lw r31, [r0, PT_CEL]
- mtcehl r30, r31
-
- .set r1
- lw r1, [r0, PT_R1]
- .set nor1
- lw r2, [r0, PT_R2]
- lw r3, [r0, PT_R3]
- lw r4, [r0, PT_R4]
- lw r5, [r0, PT_R5]
- lw r6, [r0, PT_R6]
- lw r7, [r0, PT_R7]
-
- lw r8, [r0, PT_R8]
- lw r9, [r0, PT_R9]
- lw r10, [r0, PT_R10]
- lw r11, [r0, PT_R11]
- lw r12, [r0, PT_R12]
- lw r13, [r0, PT_R13]
- lw r14, [r0, PT_R14]
- lw r15, [r0, PT_R15]
-
- lw r16, [r0, PT_R16]
- lw r17, [r0, PT_R17]
- lw r18, [r0, PT_R18]
- lw r19, [r0, PT_R19]
- lw r20, [r0, PT_R20]
- lw r21, [r0, PT_R21]
- lw r22, [r0, PT_R22]
- lw r23, [r0, PT_R23]
-
- lw r24, [r0, PT_R24]
- lw r25, [r0, PT_R25]
- lw r26, [r0, PT_R26]
- lw r27, [r0, PT_R27]
- lw r28, [r0, PT_R28]
- lw r29, [r0, PT_R29]
-
- lw r30, [r0, PT_EPC]
- lw r0, [r0, PT_R0]
- mtcr r30, cr5
- rte
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* _ASM_SCORE_ASMMACRO_H */
diff --git a/arch/score/include/asm/atomic.h b/arch/score/include/asm/atomic.h
deleted file mode 100644
index 56700980b9be..000000000000
--- a/arch/score/include/asm/atomic.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_ATOMIC_H
-#define _ASM_SCORE_ATOMIC_H
-
-#include <asm/cmpxchg.h>
-#include <asm-generic/atomic.h>
-
-#endif /* _ASM_SCORE_ATOMIC_H */
diff --git a/arch/score/include/asm/bitops.h b/arch/score/include/asm/bitops.h
deleted file mode 100644
index 6342b0123725..000000000000
--- a/arch/score/include/asm/bitops.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_BITOPS_H
-#define _ASM_SCORE_BITOPS_H
-
-#include <asm/byteorder.h> /* swab32 */
-#include <asm/barrier.h>
-
-#include <asm-generic/bitops.h>
-#include <asm-generic/bitops/__fls.h>
-
-#endif /* _ASM_SCORE_BITOPS_H */
diff --git a/arch/score/include/asm/bug.h b/arch/score/include/asm/bug.h
deleted file mode 100644
index 966b2e9e8d74..000000000000
--- a/arch/score/include/asm/bug.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_BUG_H
-#define _ASM_SCORE_BUG_H
-
-#include <asm-generic/bug.h>
-
-struct pt_regs;
-extern void __die(const char *, struct pt_regs *, const char *,
- const char *, unsigned long) __attribute__((noreturn));
-extern void __die_if_kernel(const char *, struct pt_regs *, const char *,
- const char *, unsigned long);
-
-#define die(msg, regs) \
- __die(msg, regs, __FILE__ ":", __func__, __LINE__)
-#define die_if_kernel(msg, regs) \
- __die_if_kernel(msg, regs, __FILE__ ":", __func__, __LINE__)
-
-#endif /* _ASM_SCORE_BUG_H */
diff --git a/arch/score/include/asm/bugs.h b/arch/score/include/asm/bugs.h
deleted file mode 100644
index 81185dced763..000000000000
--- a/arch/score/include/asm/bugs.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_BUGS_H
-#define _ASM_SCORE_BUGS_H
-
-#include <asm-generic/bugs.h>
-
-#endif /* _ASM_SCORE_BUGS_H */
diff --git a/arch/score/include/asm/cache.h b/arch/score/include/asm/cache.h
deleted file mode 100644
index d55de3cbbb9f..000000000000
--- a/arch/score/include/asm/cache.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_CACHE_H
-#define _ASM_SCORE_CACHE_H
-
-#define L1_CACHE_SHIFT 4
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#endif /* _ASM_SCORE_CACHE_H */
diff --git a/arch/score/include/asm/cacheflush.h b/arch/score/include/asm/cacheflush.h
deleted file mode 100644
index cf1e609634fd..000000000000
--- a/arch/score/include/asm/cacheflush.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_CACHEFLUSH_H
-#define _ASM_SCORE_CACHEFLUSH_H
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-
-extern void flush_cache_all(void);
-extern void flush_cache_mm(struct mm_struct *mm);
-extern void flush_cache_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
-extern void flush_cache_page(struct vm_area_struct *vma,
- unsigned long page, unsigned long pfn);
-extern void flush_cache_sigtramp(unsigned long addr);
-extern void flush_icache_all(void);
-extern void flush_icache_range(unsigned long start, unsigned long end);
-extern void flush_dcache_range(unsigned long start, unsigned long end);
-extern void flush_dcache_page(struct page *page);
-
-#define PG_dcache_dirty PG_arch_1
-
-#define flush_cache_dup_mm(mm) do {} while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_mmap_lock(mapping) do {} while (0)
-#define flush_dcache_mmap_unlock(mapping) do {} while (0)
-#define flush_cache_vmap(start, end) do {} while (0)
-#define flush_cache_vunmap(start, end) do {} while (0)
-
-static inline void flush_icache_page(struct vm_area_struct *vma,
- struct page *page)
-{
- if (vma->vm_flags & VM_EXEC) {
- void *v = page_address(page);
- flush_icache_range((unsigned long) v,
- (unsigned long) v + PAGE_SIZE);
- }
-}
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
- do { \
- memcpy(dst, src, len); \
- if ((vma->vm_flags & VM_EXEC)) \
- flush_cache_page(vma, vaddr, page_to_pfn(page));\
- } while (0)
-
-#endif /* _ASM_SCORE_CACHEFLUSH_H */
diff --git a/arch/score/include/asm/checksum.h b/arch/score/include/asm/checksum.h
deleted file mode 100644
index 9f00ca5fd49d..000000000000
--- a/arch/score/include/asm/checksum.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_CHECKSUM_H
-#define _ASM_SCORE_CHECKSUM_H
-
-#include <linux/in6.h>
-#include <linux/uaccess.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-unsigned int csum_partial(const void *buff, int len, __wsum sum);
-unsigned int csum_partial_copy_from_user(const char *src, char *dst, int len,
- unsigned int sum, int *csum_err);
-unsigned int csum_partial_copy(const char *src, char *dst,
- int len, unsigned int sum);
-
-/*
- * this is a new version of the above that records errors it finds in *errp,
- * but continues and zeros the rest of the buffer.
- */
-
-/*
- * Copy and checksum to user
- */
-#define HAVE_CSUM_COPY_USER
-static inline
-__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
- __wsum sum, int *err_ptr)
-{
- sum = csum_partial(src, len, sum);
- if (copy_to_user(dst, src, len)) {
- *err_ptr = -EFAULT;
- return (__force __wsum) -1; /* invalid checksum */
- }
- return sum;
-}
-
-
-#define csum_partial_copy_nocheck csum_partial_copy
-/*
- * Fold a partial checksum without adding pseudo headers
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
- /* the while loop is unnecessary really, it's always enough with two
- iterations */
- __asm__ __volatile__(
- ".set volatile\n\t"
- ".set\tr1\n\t"
- "slli\tr1,%0, 16\n\t"
- "add\t%0,%0, r1\n\t"
- "cmp.c\tr1, %0\n\t"
- "srli\t%0, %0, 16\n\t"
- "bleu\t1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:ldi\tr30, 0xffff\n\t"
- "xor\t%0, %0, r30\n\t"
- "slli\t%0, %0, 16\n\t"
- "srli\t%0, %0, 16\n\t"
- ".set\tnor1\n\t"
- ".set optimize\n\t"
- : "=r" (sum)
- : "0" (sum));
- return sum;
-}
-
-/*
- * This is a version of ip_compute_csum() optimized for IP headers,
- * which always checksum on 4 octet boundaries.
- *
- * By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
- * Arnt Gulbrandsen.
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
- unsigned int sum;
- unsigned long dummy;
-
- __asm__ __volatile__(
- ".set volatile\n\t"
- ".set\tnor1\n\t"
- "lw\t%0, [%1]\n\t"
- "subri\t%2, %2, 4\n\t"
- "slli\t%2, %2, 2\n\t"
- "lw\t%3, [%1, 4]\n\t"
- "add\t%2, %2, %1\n\t"
- "add\t%0, %0, %3\n\t"
- "cmp.c\t%3, %0\n\t"
- "lw\t%3, [%1, 8]\n\t"
- "bleu\t1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:\n\t"
- "add\t%0, %0, %3\n\t"
- "cmp.c\t%3, %0\n\t"
- "lw\t%3, [%1, 12]\n\t"
- "bleu\t1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %3\n\t"
- "cmp.c\t%3, %0\n\t"
- "bleu\t1f\n\t"
- "addi\t%0, 0x1\n"
-
- "1:\tlw\t%3, [%1, 16]\n\t"
- "addi\t%1, 4\n\t"
- "add\t%0, %0, %3\n\t"
- "cmp.c\t%3, %0\n\t"
- "bleu\t2f\n\t"
- "addi\t%0, 0x1\n"
- "2:cmp.c\t%2, %1\n\t"
- "bne\t1b\n\t"
-
- ".set\tr1\n\t"
- ".set optimize\n\t"
- : "=&r" (sum), "=&r" (iph), "=&r" (ihl), "=&r" (dummy)
- : "1" (iph), "2" (ihl));
-
- return csum_fold(sum);
-}
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- unsigned long tmp = (len + proto) << 8;
- __asm__ __volatile__(
- ".set volatile\n\t"
- "add\t%0, %0, %2\n\t"
- "cmp.c\t%2, %0\n\t"
- "bleu\t1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:\n\t"
- "add\t%0, %0, %3\n\t"
- "cmp.c\t%3, %0\n\t"
- "bleu\t1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:\n\t"
- "add\t%0, %0, %4\n\t"
- "cmp.c\t%4, %0\n\t"
- "bleu\t1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:\n\t"
- ".set optimize\n\t"
- : "=r" (sum)
- : "0" (daddr), "r"(saddr),
- "r" (tmp),
- "r" (sum));
- return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, __u32 len,
- __u8 proto, __wsum sum)
-{
- return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-static inline unsigned short ip_compute_csum(const void *buff, int len)
-{
- return csum_fold(csum_partial(buff, len, 0));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
- const struct in6_addr *daddr,
- __u32 len, __u8 proto, __wsum sum)
-{
- __asm__ __volatile__(
- ".set\tvolatile\t\t\t# csum_ipv6_magic\n\t"
- "add\t%0, %0, %5\t\t\t# proto (long in network byte order)\n\t"
- "cmp.c\t%5, %0\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %6\t\t\t# csum\n\t"
- "cmp.c\t%6, %0\n\t"
- "lw\t%1, [%2, 0]\t\t\t# four words source address\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %1\n\t"
- "cmp.c\t%1, %0\n\t"
- "1:lw\t%1, [%2, 4]\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %1\n\t"
- "cmp.c\t%1, %0\n\t"
- "lw\t%1, [%2,8]\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %1\n\t"
- "cmp.c\t%1, %0\n\t"
- "lw\t%1, [%2, 12]\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0,%1\n\t"
- "cmp.c\t%1, %0\n\t"
- "lw\t%1, [%3, 0]\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %1\n\t"
- "cmp.c\t%1, %0\n\t"
- "lw\t%1, [%3, 4]\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %1\n\t"
- "cmp.c\t%1, %0\n\t"
- "lw\t%1, [%3, 8]\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %1\n\t"
- "cmp.c\t%1, %0\n\t"
- "lw\t%1, [%3, 12]\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:add\t%0, %0, %1\n\t"
- "cmp.c\t%1, %0\n\t"
- "bleu 1f\n\t"
- "addi\t%0, 0x1\n\t"
- "1:\n\t"
- ".set\toptimize"
- : "=r" (sum), "=r" (proto)
- : "r" (saddr), "r" (daddr),
- "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
-
- return csum_fold(sum);
-}
-#endif /* _ASM_SCORE_CHECKSUM_H */
diff --git a/arch/score/include/asm/cmpxchg.h b/arch/score/include/asm/cmpxchg.h
deleted file mode 100644
index e503073c8978..000000000000
--- a/arch/score/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_CMPXCHG_H
-#define _ASM_SCORE_CMPXCHG_H
-
-#include <linux/irqflags.h>
-
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
-static inline
-unsigned long __xchg(volatile unsigned long *m, unsigned long val)
-{
- unsigned long retval;
- unsigned long flags;
-
- local_irq_save(flags);
- retval = *m;
- *m = val;
- local_irq_restore(flags);
- return retval;
-}
-
-#define xchg(ptr, v) \
- ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
- (unsigned long)(v)))
-
-static inline unsigned long __cmpxchg(volatile unsigned long *m,
- unsigned long old, unsigned long new)
-{
- unsigned long retval;
- unsigned long flags;
-
- local_irq_save(flags);
- retval = *m;
- if (retval == old)
- *m = new;
- local_irq_restore(flags);
- return retval;
-}
-
-#define cmpxchg(ptr, o, n) \
- ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
- (unsigned long)(o), \
- (unsigned long)(n)))
-
-#include <asm-generic/cmpxchg-local.h>
-
-#endif /* _ASM_SCORE_CMPXCHG_H */
diff --git a/arch/score/include/asm/delay.h b/arch/score/include/asm/delay.h
deleted file mode 100644
index a4bd2c748ab4..000000000000
--- a/arch/score/include/asm/delay.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_DELAY_H
-#define _ASM_SCORE_DELAY_H
-
-#include <asm-generic/param.h>
-
-static inline void __delay(unsigned long loops)
-{
- /* 3 cycles per loop. */
- __asm__ __volatile__ (
- "1:\tsubi\t%0, 3\n\t"
- "cmpz.c\t%0\n\t"
- "ble\t1b\n\t"
- : "=r" (loops)
- : "0" (loops));
-}
-
-static inline void __udelay(unsigned long usecs)
-{
- unsigned long loops_per_usec;
-
- loops_per_usec = (loops_per_jiffy * HZ) / 1000000;
-
- __delay(usecs * loops_per_usec);
-}
-
-#define udelay(usecs) __udelay(usecs)
-
-#endif /* _ASM_SCORE_DELAY_H */
diff --git a/arch/score/include/asm/device.h b/arch/score/include/asm/device.h
deleted file mode 100644
index 818ad4d01197..000000000000
--- a/arch/score/include/asm/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_DEVICE_H
-#define _ASM_SCORE_DEVICE_H
-
-#include <asm-generic/device.h>
-
-#endif /* _ASM_SCORE_DEVICE_H */
diff --git a/arch/score/include/asm/div64.h b/arch/score/include/asm/div64.h
deleted file mode 100644
index cf73dc218bec..000000000000
--- a/arch/score/include/asm/div64.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_DIV64_H
-#define _ASM_SCORE_DIV64_H
-
-#include <asm-generic/div64.h>
-
-#endif /* _ASM_SCORE_DIV64_H */
diff --git a/arch/score/include/asm/dma.h b/arch/score/include/asm/dma.h
deleted file mode 100644
index fd44a9cbee4f..000000000000
--- a/arch/score/include/asm/dma.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_DMA_H
-#define _ASM_SCORE_DMA_H
-
-#include <asm/io.h>
-
-#define MAX_DMA_ADDRESS (0)
-
-#endif /* _ASM_SCORE_DMA_H */
diff --git a/arch/score/include/asm/elf.h b/arch/score/include/asm/elf.h
deleted file mode 100644
index c970ac160f3c..000000000000
--- a/arch/score/include/asm/elf.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_ELF_H
-#define _ASM_SCORE_ELF_H
-
-#include <linux/ptrace.h>
-
-#define EM_SCORE7 135
-
-/* Relocation types. */
-#define R_SCORE_NONE 0
-#define R_SCORE_HI16 1
-#define R_SCORE_LO16 2
-#define R_SCORE_BCMP 3
-#define R_SCORE_24 4
-#define R_SCORE_PC19 5
-#define R_SCORE16_11 6
-#define R_SCORE16_PC8 7
-#define R_SCORE_ABS32 8
-#define R_SCORE_ABS16 9
-#define R_SCORE_DUMMY2 10
-#define R_SCORE_GP15 11
-#define R_SCORE_GNU_VTINHERIT 12
-#define R_SCORE_GNU_VTENTRY 13
-#define R_SCORE_GOT15 14
-#define R_SCORE_GOT_LO16 15
-#define R_SCORE_CALL15 16
-#define R_SCORE_GPREL32 17
-#define R_SCORE_REL32 18
-#define R_SCORE_DUMMY_HI16 19
-#define R_SCORE_IMM30 20
-#define R_SCORE_IMM32 21
-
-/* ELF register definitions */
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* Score does not have fp regs. */
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t;
-
-#define elf_check_arch(x) ((x)->e_machine == EM_SCORE7)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS ELFCLASS32
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_DATA ELFDATA2LSB
-#define ELF_ARCH EM_SCORE7
-
-struct task_struct;
-struct pt_regs;
-
-#define CORE_DUMP_USE_REGSET
-#define ELF_EXEC_PAGESIZE PAGE_SIZE
-
-/* This yields a mask that user programs can use to figure out what
- instruction set this cpu supports. This could be done in userspace,
- but it's not easy, and we've already done it here. */
-
-#define ELF_HWCAP (0)
-
-/* This yields a string that ld.so will use to load implementation
- specific libraries for optimization. This is more specific in
- intent than poking at uname or /proc/cpuinfo.
-
- For the moment, we have only optimizations for the Intel generations,
- but that could change... */
-
-#define ELF_PLATFORM (NULL)
-
-#define ELF_PLAT_INIT(_r, load_addr) \
-do { \
- _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \
- _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \
- _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \
- _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \
- _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \
- _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \
- _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \
- _r->regs[30] = _r->regs[31] = 0; \
-} while (0)
-
-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
- use of this is to invoke "./ld.so someprog" to test out a new version of
- the loader. We need to make sure that it is out of the way of the program
- that it will "exec", and that there is sufficient room for the brk. */
-
-#ifndef ELF_ET_DYN_BASE
-#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
-#endif
-
-#endif /* _ASM_SCORE_ELF_H */
diff --git a/arch/score/include/asm/emergency-restart.h b/arch/score/include/asm/emergency-restart.h
deleted file mode 100644
index b0612c677764..000000000000
--- a/arch/score/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_EMERGENCY_RESTART_H
-#define _ASM_SCORE_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_SCORE_EMERGENCY_RESTART_H */
diff --git a/arch/score/include/asm/exec.h b/arch/score/include/asm/exec.h
deleted file mode 100644
index a1f95e1d8a31..000000000000
--- a/arch/score/include/asm/exec.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_EXEC_H
-#define _ASM_SCORE_EXEC_H
-
-extern unsigned long arch_align_stack(unsigned long sp);
-
-#endif /* _ASM_SCORE_EXEC_H */
diff --git a/arch/score/include/asm/fixmap.h b/arch/score/include/asm/fixmap.h
deleted file mode 100644
index 68ca314830c9..000000000000
--- a/arch/score/include/asm/fixmap.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_FIXMAP_H
-#define _ASM_SCORE_FIXMAP_H
-
-#include <asm/page.h>
-
-#define PHY_RAM_BASE 0x00000000
-#define PHY_IO_BASE 0x10000000
-
-#define VIRTUAL_RAM_BASE 0xa0000000
-#define VIRTUAL_IO_BASE 0xb0000000
-
-#define RAM_SPACE_SIZE 0x10000000
-#define IO_SPACE_SIZE 0x10000000
-
-/* Kernel unmapped, cached 512MB */
-#define KSEG1 0xa0000000
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special addresses
- * from the end of virtual memory (0xfffff000) backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * highger than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-
-/*
- * on UP currently we will have no trace of the fixmap mechanizm,
- * no page table allocations, etc. This might change in the
- * future, say framebuffers for the console driver(s) could be
- * fix-mapped?
- */
-enum fixed_addresses {
-#define FIX_N_COLOURS 8
- FIX_CMAP_BEGIN,
- FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
- __end_of_fixed_addresses
-};
-
-/*
- * used by vmalloc.c.
- *
- * Leave one empty page between vmalloc'ed areas and
- * the start of the fixmap, and leave one page empty
- * at the top of mem..
- */
-#define FIXADDR_TOP ((unsigned long)(long)(int)0xfefe0000)
-#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
-
-#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x) \
- ((FIXADDR_TOP - ((x) & PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
- return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
- return __virt_to_fix(vaddr);
-}
-
-#endif /* _ASM_SCORE_FIXMAP_H */
diff --git a/arch/score/include/asm/ftrace.h b/arch/score/include/asm/ftrace.h
deleted file mode 100644
index 79d6f10e1f5b..000000000000
--- a/arch/score/include/asm/ftrace.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_SCORE_FTRACE_H
-#define _ASM_SCORE_FTRACE_H
-
-#endif /* _ASM_SCORE_FTRACE_H */
diff --git a/arch/score/include/asm/futex.h b/arch/score/include/asm/futex.h
deleted file mode 100644
index ec247fb364c9..000000000000
--- a/arch/score/include/asm/futex.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_FUTEX_H
-#define _ASM_SCORE_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif /* _ASM_SCORE_FUTEX_H */
diff --git a/arch/score/include/asm/hardirq.h b/arch/score/include/asm/hardirq.h
deleted file mode 100644
index d8dd8909cb18..000000000000
--- a/arch/score/include/asm/hardirq.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_HARDIRQ_H
-#define _ASM_SCORE_HARDIRQ_H
-
-#include <asm-generic/hardirq.h>
-
-#endif /* _ASM_SCORE_HARDIRQ_H */
diff --git a/arch/score/include/asm/hw_irq.h b/arch/score/include/asm/hw_irq.h
deleted file mode 100644
index 4caafb2b509a..000000000000
--- a/arch/score/include/asm/hw_irq.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_SCORE_HW_IRQ_H
-#define _ASM_SCORE_HW_IRQ_H
-
-#endif /* _ASM_SCORE_HW_IRQ_H */
diff --git a/arch/score/include/asm/io.h b/arch/score/include/asm/io.h
deleted file mode 100644
index 37ce8723b06b..000000000000
--- a/arch/score/include/asm/io.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_IO_H
-#define _ASM_SCORE_IO_H
-
-#include <asm-generic/io.h>
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-#endif /* _ASM_SCORE_IO_H */
diff --git a/arch/score/include/asm/irq.h b/arch/score/include/asm/irq.h
deleted file mode 100644
index c1434c889de2..000000000000
--- a/arch/score/include/asm/irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_IRQ_H
-#define _ASM_SCORE_IRQ_H
-
-#define EXCEPTION_VECTOR_BASE_ADDR 0xa0000000
-#define VECTOR_ADDRESS_OFFSET_MODE4 0
-#define VECTOR_ADDRESS_OFFSET_MODE16 1
-
-#define DEBUG_VECTOR_SIZE (0x4)
-#define DEBUG_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x1fc)
-
-#define GENERAL_VECTOR_SIZE (0x10)
-#define GENERAL_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x200)
-
-#define NR_IRQS 64
-#define IRQ_VECTOR_SIZE (0x10)
-#define IRQ_VECTOR_BASE_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x210)
-#define IRQ_VECTOR_END_ADDR ((EXCEPTION_VECTOR_BASE_ADDR) + 0x5f0)
-
-#define irq_canonicalize(irq) (irq)
-
-#define IRQ_TIMER (7) /* Timer IRQ number of SPCT6600 */
-
-extern void interrupt_exception_vector(void);
-
-#endif /* _ASM_SCORE_IRQ_H */
diff --git a/arch/score/include/asm/irq_regs.h b/arch/score/include/asm/irq_regs.h
deleted file mode 100644
index 740b2315d848..000000000000
--- a/arch/score/include/asm/irq_regs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_IRQ_REGS_H
-#define _ASM_SCORE_IRQ_REGS_H
-
-#include <linux/thread_info.h>
-
-static inline struct pt_regs *get_irq_regs(void)
-{
- return current_thread_info()->regs;
-}
-
-#endif /* _ASM_SCORE_IRQ_REGS_H */
diff --git a/arch/score/include/asm/irqflags.h b/arch/score/include/asm/irqflags.h
deleted file mode 100644
index 354c1979ea8d..000000000000
--- a/arch/score/include/asm/irqflags.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_IRQFLAGS_H
-#define _ASM_SCORE_IRQFLAGS_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-static inline unsigned long arch_local_save_flags(void)
-{
- unsigned long flags;
-
- asm volatile(
- " mfcr r8, cr0 \n"
- " nop \n"
- " nop \n"
- " mv %0, r8 \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " ldi r9, 0x1 \n"
- " and %0, %0, r9 \n"
- : "=r" (flags)
- :
- : "r8", "r9");
- return flags;
-}
-
-static inline unsigned long arch_local_irq_save(void)
-{
- unsigned long flags;
-
- asm volatile(
- " mfcr r8, cr0 \n"
- " li r9, 0xfffffffe \n"
- " nop \n"
- " mv %0, r8 \n"
- " and r8, r8, r9 \n"
- " mtcr r8, cr0 \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- : "=r" (flags)
- :
- : "r8", "r9", "memory");
-
- return flags;
-}
-
-static inline void arch_local_irq_restore(unsigned long flags)
-{
- asm volatile(
- " mfcr r8, cr0 \n"
- " ldi r9, 0x1 \n"
- " and %0, %0, r9 \n"
- " or r8, r8, %0 \n"
- " mtcr r8, cr0 \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- :
- : "r"(flags)
- : "r8", "r9", "memory");
-}
-
-static inline void arch_local_irq_enable(void)
-{
- asm volatile(
- " mfcr r8,cr0 \n"
- " nop \n"
- " nop \n"
- " ori r8,0x1 \n"
- " mtcr r8,cr0 \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- :
- :
- : "r8", "memory");
-}
-
-static inline void arch_local_irq_disable(void)
-{
- asm volatile(
- " mfcr r8,cr0 \n"
- " nop \n"
- " nop \n"
- " srli r8,r8,1 \n"
- " slli r8,r8,1 \n"
- " mtcr r8,cr0 \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- " nop \n"
- :
- :
- : "r8", "memory");
-}
-
-static inline bool arch_irqs_disabled_flags(unsigned long flags)
-{
- return !(flags & 1);
-}
-
-static inline bool arch_irqs_disabled(void)
-{
- return arch_irqs_disabled_flags(arch_local_save_flags());
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_SCORE_IRQFLAGS_H */
diff --git a/arch/score/include/asm/kdebug.h b/arch/score/include/asm/kdebug.h
deleted file mode 100644
index 481ba1fb5372..000000000000
--- a/arch/score/include/asm/kdebug.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_KDEBUG_H
-#define _ASM_SCORE_KDEBUG_H
-
-#include <asm-generic/kdebug.h>
-
-#endif /* _ASM_SCORE_KDEBUG_H */
diff --git a/arch/score/include/asm/kmap_types.h b/arch/score/include/asm/kmap_types.h
deleted file mode 100644
index 14261872c9c7..000000000000
--- a/arch/score/include/asm/kmap_types.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_KMAP_TYPES_H
-#define _ASM_SCORE_KMAP_TYPES_H
-
-#include <asm-generic/kmap_types.h>
-
-#endif /* _ASM_SCORE_KMAP_TYPES_H */
diff --git a/arch/score/include/asm/linkage.h b/arch/score/include/asm/linkage.h
deleted file mode 100644
index 0c11c009969a..000000000000
--- a/arch/score/include/asm/linkage.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_LINKAGE_H
-#define _ASM_SCORE_LINKAGE_H
-
-#define __ALIGN .align 2
-#define __ALIGN_STR ".align 2"
-
-#endif /* _ASM_SCORE_LINKAGE_H */
diff --git a/arch/score/include/asm/local.h b/arch/score/include/asm/local.h
deleted file mode 100644
index 00bdebdf75f2..000000000000
--- a/arch/score/include/asm/local.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_LOCAL_H
-#define _ASM_SCORE_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif /* _ASM_SCORE_LOCAL_H */
diff --git a/arch/score/include/asm/local64.h b/arch/score/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/score/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/score/include/asm/mmu.h b/arch/score/include/asm/mmu.h
deleted file mode 100644
index d913369adda3..000000000000
--- a/arch/score/include/asm/mmu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_MMU_H
-#define _ASM_SCORE_MMU_H
-
-typedef unsigned long mm_context_t;
-
-#endif /* _ASM_SCORE_MMU_H */
diff --git a/arch/score/include/asm/mmu_context.h b/arch/score/include/asm/mmu_context.h
deleted file mode 100644
index d0aa2a5aebca..000000000000
--- a/arch/score/include/asm/mmu_context.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_MMU_CONTEXT_H
-#define _ASM_SCORE_MMU_CONTEXT_H
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm_types.h>
-#include <linux/slab.h>
-
-#include <asm-generic/mm_hooks.h>
-
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <asm/scoreregs.h>
-
-/*
- * For the fast tlb miss handlers, we keep a per cpu array of pointers
- * to the current pgd for each processor. Also, the proc. id is stuffed
- * into the context register.
- */
-extern unsigned long asid_cache;
-extern unsigned long pgd_current;
-
-#define TLBMISS_HANDLER_SETUP_PGD(pgd) (pgd_current = (unsigned long)(pgd))
-
-#define TLBMISS_HANDLER_SETUP() \
-do { \
- write_c0_context(0); \
- TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) \
-} while (0)
-
-/*
- * All unused by hardware upper bits will be considered
- * as a software asid extension.
- */
-#define ASID_VERSION_MASK 0xfffff000
-#define ASID_FIRST_VERSION 0x1000
-
-/* PEVN --------- VPN ---------- --ASID--- -NA- */
-/* binary: 0000 0000 0000 0000 0000 0000 0001 0000 */
-/* binary: 0000 0000 0000 0000 0000 1111 1111 0000 */
-#define ASID_INC 0x10
-#define ASID_MASK 0xff0
-
-static inline void enter_lazy_tlb(struct mm_struct *mm,
- struct task_struct *tsk)
-{}
-
-static inline void
-get_new_mmu_context(struct mm_struct *mm)
-{
- unsigned long asid = asid_cache + ASID_INC;
-
- if (!(asid & ASID_MASK)) {
- local_flush_tlb_all(); /* start new asid cycle */
- if (!asid) /* fix version if needed */
- asid = ASID_FIRST_VERSION;
- }
-
- mm->context = asid;
- asid_cache = asid;
-}
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- mm->context = 0;
- return 0;
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- if ((next->context ^ asid_cache) & ASID_VERSION_MASK)
- get_new_mmu_context(next);
-
- pevn_set(next->context);
- TLBMISS_HANDLER_SETUP_PGD(next->pgd);
- local_irq_restore(flags);
-}
-
-/*
- * Destroy context related info for an mm_struct that is about
- * to be put to rest.
- */
-static inline void destroy_context(struct mm_struct *mm)
-{}
-
-static inline void
-deactivate_mm(struct task_struct *task, struct mm_struct *mm)
-{}
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-static inline void
-activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- get_new_mmu_context(next);
- pevn_set(next->context);
- TLBMISS_HANDLER_SETUP_PGD(next->pgd);
- local_irq_restore(flags);
-}
-
-#endif /* _ASM_SCORE_MMU_CONTEXT_H */
diff --git a/arch/score/include/asm/module.h b/arch/score/include/asm/module.h
deleted file mode 100644
index 33777ed32e9e..000000000000
--- a/arch/score/include/asm/module.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_MODULE_H
-#define _ASM_SCORE_MODULE_H
-
-#include <linux/list.h>
-#include <asm/extable.h>
-#include <asm-generic/module.h>
-
-struct mod_arch_specific {
- /* Data Bus Error exception tables */
- struct list_head dbe_list;
- const struct exception_table_entry *dbe_start;
- const struct exception_table_entry *dbe_end;
-};
-
-typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */
-
-/* Given an address, look for it in the exception tables. */
-#ifdef CONFIG_MODULES
-const struct exception_table_entry *search_module_dbetables(unsigned long addr);
-#else
-static inline const struct exception_table_entry
-*search_module_dbetables(unsigned long addr)
-{
- return NULL;
-}
-#endif
-
-#define MODULE_PROC_FAMILY "SCORE7"
-#define MODULE_KERNEL_TYPE "32BIT "
-#define MODULE_KERNEL_SMTC ""
-
-#define MODULE_ARCH_VERMAGIC \
- MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC
-
-#endif /* _ASM_SCORE_MODULE_H */
diff --git a/arch/score/include/asm/page.h b/arch/score/include/asm/page.h
deleted file mode 100644
index 17d9c68b6bd5..000000000000
--- a/arch/score/include/asm/page.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_PAGE_H
-#define _ASM_SCORE_PAGE_H
-
-#include <linux/pfn.h>
-#include <linux/const.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT (12)
-#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE-1))
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-#define PAGE_UP(addr) (((addr)+((PAGE_SIZE)-1))&(~((PAGE_SIZE)-1)))
-#define PAGE_DOWN(addr) ((addr)&(~((PAGE_SIZE)-1)))
-
-/* align addr on a size boundary - adjust address up/down if needed */
-#define _ALIGN_UP(addr, size) (((addr)+((size)-1))&(~((size)-1)))
-#define _ALIGN_DOWN(addr, size) ((addr)&(~((size)-1)))
-
-/* align addr on a size boundary - adjust address up if needed */
-#define _ALIGN(addr, size) _ALIGN_UP(addr, size)
-
-/*
- * PAGE_OFFSET -- the first address of the first page of memory. When not
- * using MMU this corresponds to the first free page in physical memory (aligned
- * on a page boundary).
- */
-#define PAGE_OFFSET (0xA0000000UL)
-
-#define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE)
-#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE)
-#define copy_user_page(vto, vfrom, vaddr, topg) \
- memcpy((vto), (vfrom), PAGE_SIZE)
-
-/*
- * These are used to make use of C type-checking..
- */
-
-typedef struct { unsigned long pte; } pte_t; /* page table entry */
-typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x) ((x).pte)
-#define pgd_val(x) ((x).pgd)
-#define pgprot_val(x) ((x).pgprot)
-
-#define __pte(x) ((pte_t) { (x) })
-#define __pgd(x) ((pgd_t) { (x) })
-#define __pgprot(x) ((pgprot_t) { (x) })
-
-extern unsigned long max_low_pfn;
-extern unsigned long min_low_pfn;
-extern unsigned long max_pfn;
-
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
-#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
-
-#define phys_to_pfn(phys) (PFN_DOWN(phys))
-#define pfn_to_phys(pfn) (PFN_PHYS(pfn))
-
-#define virt_to_pfn(vaddr) (phys_to_pfn((__pa(vaddr))))
-#define pfn_to_virt(pfn) __va(pfn_to_phys((pfn)))
-
-#define virt_to_page(vaddr) (pfn_to_page(virt_to_pfn(vaddr)))
-#define page_to_virt(page) (pfn_to_virt(page_to_pfn(page)))
-
-#define page_to_phys(page) (pfn_to_phys(page_to_pfn(page)))
-#define page_to_bus(page) (page_to_phys(page))
-#define phys_to_page(paddr) (pfn_to_page(phys_to_pfn(paddr)))
-
-#define pfn_valid(pfn) (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn))
-
-#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT)
-
-#endif /* __ASSEMBLY__ */
-
-#define virt_addr_valid(vaddr) (pfn_valid(virt_to_pfn(vaddr)))
-
-#endif /* __KERNEL__ */
-
-#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/getorder.h>
-
-#endif /* _ASM_SCORE_PAGE_H */
diff --git a/arch/score/include/asm/pci.h b/arch/score/include/asm/pci.h
deleted file mode 100644
index 3f3cfd82549c..000000000000
--- a/arch/score/include/asm/pci.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_SCORE_PCI_H
-#define _ASM_SCORE_PCI_H
-
-#endif /* _ASM_SCORE_PCI_H */
diff --git a/arch/score/include/asm/percpu.h b/arch/score/include/asm/percpu.h
deleted file mode 100644
index 5a6a2f7e5d62..000000000000
--- a/arch/score/include/asm/percpu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_PERCPU_H
-#define _ASM_SCORE_PERCPU_H
-
-#include <asm-generic/percpu.h>
-
-#endif /* _ASM_SCORE_PERCPU_H */
diff --git a/arch/score/include/asm/pgalloc.h b/arch/score/include/asm/pgalloc.h
deleted file mode 100644
index 7dfc5c163093..000000000000
--- a/arch/score/include/asm/pgalloc.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_PGALLOC_H
-#define _ASM_SCORE_PGALLOC_H
-
-#include <linux/mm.h>
-#include <linux/highmem.h>
-static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
- pte_t *pte)
-{
- set_pmd(pmd, __pmd((unsigned long)pte));
-}
-
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- pgtable_t pte)
-{
- set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
-}
-
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- pgd_t *ret, *init;
-
- ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
- if (ret) {
- init = pgd_offset(&init_mm, 0UL);
- pgd_init((unsigned long)ret);
- memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
- (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
- }
-
- return ret;
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- free_pages((unsigned long)pgd, PGD_ORDER);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
- unsigned long address)
-{
- pte_t *pte;
-
- pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_ZERO, PTE_ORDER);
-
- return pte;
-}
-
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- struct page *pte;
-
- pte = alloc_pages(GFP_KERNEL, PTE_ORDER);
- if (!pte)
- return NULL;
- clear_highpage(pte);
- if (!pgtable_page_ctor(pte)) {
- __free_page(pte);
- return NULL;
- }
- return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- free_pages((unsigned long)pte, PTE_ORDER);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
- pgtable_page_dtor(pte);
- __free_pages(pte, PTE_ORDER);
-}
-
-#define __pte_free_tlb(tlb, pte, buf) \
-do { \
- pgtable_page_dtor(pte); \
- tlb_remove_page((tlb), pte); \
-} while (0)
-
-#define check_pgt_cache() do {} while (0)
-
-#endif /* _ASM_SCORE_PGALLOC_H */
diff --git a/arch/score/include/asm/pgtable-bits.h b/arch/score/include/asm/pgtable-bits.h
deleted file mode 100644
index fb8f306f4d11..000000000000
--- a/arch/score/include/asm/pgtable-bits.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_PGTABLE_BITS_H
-#define _ASM_SCORE_PGTABLE_BITS_H
-
-#define _PAGE_ACCESSED (1<<5) /* implemented in software */
-#define _PAGE_READ (1<<6) /* implemented in software */
-#define _PAGE_WRITE (1<<7) /* implemented in software */
-#define _PAGE_PRESENT (1<<9) /* implemented in software */
-#define _PAGE_MODIFIED (1<<10) /* implemented in software */
-
-#define _PAGE_GLOBAL (1<<0)
-#define _PAGE_VALID (1<<1)
-#define _PAGE_SILENT_READ (1<<1) /* synonym */
-#define _PAGE_DIRTY (1<<2) /* Write bit */
-#define _PAGE_SILENT_WRITE (1<<2)
-#define _PAGE_CACHE (1<<3) /* cache */
-#define _CACHE_MASK (1<<3)
-#define _PAGE_BUFFERABLE (1<<4) /*Fallow Spec. */
-
-#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-#define _PAGE_CHG_MASK \
- (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_CACHE)
-
-#endif /* _ASM_SCORE_PGTABLE_BITS_H */
diff --git a/arch/score/include/asm/pgtable.h b/arch/score/include/asm/pgtable.h
deleted file mode 100644
index c14226be0559..000000000000
--- a/arch/score/include/asm/pgtable.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_PGTABLE_H
-#define _ASM_SCORE_PGTABLE_H
-
-#include <linux/const.h>
-#define __ARCH_USE_5LEVEL_HACK
-#include <asm-generic/pgtable-nopmd.h>
-
-#include <asm/fixmap.h>
-#include <asm/setup.h>
-#include <asm/pgtable-bits.h>
-
-extern void load_pgd(unsigned long pg_dir);
-extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT 22
-#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
-#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-
-/*
- * Entries per page directory level: we use two-level, so
- * we don't really have any PUD/PMD directory physically.
- */
-#define PGD_ORDER 0
-#define PTE_ORDER 0
-
-#define PTRS_PER_PGD 1024
-#define PTRS_PER_PTE 1024
-
-#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
-#define FIRST_USER_ADDRESS 0UL
-
-#define VMALLOC_START (0xc0000000UL)
-
-#define PKMAP_BASE (0xfd000000UL)
-
-#define VMALLOC_END (FIXADDR_START - 2*PAGE_SIZE)
-
-#define pte_ERROR(e) \
- printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
- __FILE__, __LINE__, pte_val(e))
-#define pgd_ERROR(e) \
- printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
- __FILE__, __LINE__, pgd_val(e))
-
-/*
- * Empty pgd/pmd entries point to the invalid_pte_table.
- */
-static inline int pmd_none(pmd_t pmd)
-{
- return pmd_val(pmd) == (unsigned long) invalid_pte_table;
-}
-
-#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
-
-static inline int pmd_present(pmd_t pmd)
-{
- return pmd_val(pmd) != (unsigned long) invalid_pte_table;
-}
-
-static inline void pmd_clear(pmd_t *pmdp)
-{
- pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
-}
-
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot) \
- __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
-
-#define __pgd_offset(address) pgd_index(address)
-#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
-#define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-
-/* to find an entry in a page-table-directory */
-#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
-
-/* Find an entry in the third-level page table.. */
-#define __pte_offset(address) \
- (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_kernel(dir, address) \
- ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-
-#define pte_offset_map(dir, address) \
- ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-#define pte_unmap(pte) ((void)(pte))
-
-#define __pte_to_swp_entry(pte) \
- ((swp_entry_t) { pte_val(pte)})
-#define __swp_entry_to_pte(x) ((pte_t) {(x).val})
-
-#define pmd_phys(pmd) __pa((void *)pmd_val(pmd))
-#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
-#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
-static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
-
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-#define pte_clear(mm, addr, xp) \
- do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
-
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-#define pgd_present(pgd) (1)
-#define pgd_none(pgd) (0)
-#define pgd_bad(pgd) (0)
-#define pgd_clear(pgdp) do { } while (0)
-
-#define kern_addr_valid(addr) (1)
-#define pmd_page_vaddr(pmd) pmd_val(pmd)
-
-#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
-#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
-
-#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_CACHE)
-#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
- _PAGE_CACHE)
-#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHE)
-#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_CACHE)
-#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
- _PAGE_GLOBAL | _PAGE_CACHE)
-#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
- __WRITEABLE | _PAGE_GLOBAL & ~_PAGE_CACHE)
-
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY
-#define __P101 PAGE_READONLY
-#define __P110 PAGE_COPY
-#define __P111 PAGE_COPY
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY
-#define __S101 PAGE_READONLY
-#define __S110 PAGE_SHARED
-#define __S111 PAGE_SHARED
-
-#define pgprot_noncached pgprot_noncached
-
-static inline pgprot_t pgprot_noncached(pgprot_t _prot)
-{
- unsigned long prot = pgprot_val(_prot);
-
- prot = (prot & ~_CACHE_MASK);
-
- return __pgprot(prot);
-}
-
-#define __swp_type(x) ((x).val & 0x1f)
-#define __swp_offset(x) ((x).val >> 10)
-#define __swp_entry(type, offset) ((swp_entry_t){(type) | ((offset) << 10)})
-
-extern unsigned long empty_zero_page;
-extern unsigned long zero_page_mask;
-
-#define ZERO_PAGE(vaddr) \
- (virt_to_page((void *)(empty_zero_page + \
- (((unsigned long)(vaddr)) & zero_page_mask))))
-
-#define pgtable_cache_init() do {} while (0)
-
-#define arch_enter_lazy_cpu_mode() do {} while (0)
-
-static inline int pte_write(pte_t pte)
-{
- return pte_val(pte) & _PAGE_WRITE;
-}
-
-static inline int pte_dirty(pte_t pte)
-{
- return pte_val(pte) & _PAGE_MODIFIED;
-}
-
-static inline int pte_young(pte_t pte)
-{
- return pte_val(pte) & _PAGE_ACCESSED;
-}
-
-#define pte_special(pte) (0)
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
- return pte;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
- return pte;
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
- pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
- return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
- pte_val(pte) |= _PAGE_WRITE;
- if (pte_val(pte) & _PAGE_MODIFIED)
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
- pte_val(pte) |= _PAGE_MODIFIED;
- if (pte_val(pte) & _PAGE_WRITE)
- pte_val(pte) |= _PAGE_SILENT_WRITE;
- return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
- pte_val(pte) |= _PAGE_ACCESSED;
- if (pte_val(pte) & _PAGE_READ)
- pte_val(pte) |= _PAGE_SILENT_READ;
- return pte;
-}
-
-#define set_pmd(pmdptr, pmdval) \
- do { *(pmdptr) = (pmdval); } while (0)
-#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
-
-extern unsigned long pgd_current;
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-extern void paging_init(void);
-
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
-}
-
-extern void __update_tlb(struct vm_area_struct *vma,
- unsigned long address, pte_t pte);
-extern void __update_cache(struct vm_area_struct *vma,
- unsigned long address, pte_t pte);
-
-static inline void update_mmu_cache(struct vm_area_struct *vma,
- unsigned long address, pte_t *ptep)
-{
- pte_t pte = *ptep;
- __update_tlb(vma, address, pte);
- __update_cache(vma, address, pte);
-}
-
-#ifndef __ASSEMBLY__
-#include <asm-generic/pgtable.h>
-
-void setup_memory(void);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_SCORE_PGTABLE_H */
diff --git a/arch/score/include/asm/processor.h b/arch/score/include/asm/processor.h
deleted file mode 100644
index 1412c774c6b1..000000000000
--- a/arch/score/include/asm/processor.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_PROCESSOR_H
-#define _ASM_SCORE_PROCESSOR_H
-
-#include <linux/cpumask.h>
-#include <linux/threads.h>
-
-#include <asm/segment.h>
-
-struct task_struct;
-
-/*
- * System setup and hardware flags..
- */
-extern void (*cpu_wait)(void);
-
-extern void start_thread(struct pt_regs *regs,
- unsigned long pc, unsigned long sp);
-extern unsigned long get_wchan(struct task_struct *p);
-
-/*
- * Return current * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l; })
-
-#define cpu_relax() barrier()
-#define release_thread(thread) do {} while (0)
-
-/*
- * User space process size: 2GB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-#define TASK_SIZE 0x7fff8000UL
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE))
-
-#ifdef __KERNEL__
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX TASK_SIZE
-#endif
-
-/*
- * If you change thread_struct remember to change the #defines below too!
- */
-struct thread_struct {
- unsigned long reg0, reg2, reg3;
- unsigned long reg12, reg13, reg14, reg15, reg16;
- unsigned long reg17, reg18, reg19, reg20, reg21;
-
- unsigned long cp0_psr;
- unsigned long cp0_ema; /* Last user fault */
- unsigned long cp0_badvaddr; /* Last user fault */
- unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
- unsigned long error_code;
- unsigned long trap_no;
-
- unsigned long mflags;
- unsigned long reg29;
-
- unsigned long single_step;
- unsigned long ss_nextcnt;
-
- unsigned long insn1_type;
- unsigned long addr1;
- unsigned long insn1;
-
- unsigned long insn2_type;
- unsigned long addr2;
- unsigned long insn2;
-
- mm_segment_t current_ds;
-};
-
-#define INIT_THREAD { \
- .reg0 = 0, \
- .reg2 = 0, \
- .reg3 = 0, \
- .reg12 = 0, \
- .reg13 = 0, \
- .reg14 = 0, \
- .reg15 = 0, \
- .reg16 = 0, \
- .reg17 = 0, \
- .reg18 = 0, \
- .reg19 = 0, \
- .reg20 = 0, \
- .reg21 = 0, \
- .cp0_psr = 0, \
- .error_code = 0, \
- .trap_no = 0, \
-}
-
-#define kstk_tos(tsk) \
- ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32)
-#define task_pt_regs(tsk) ((struct pt_regs *)kstk_tos(tsk) - 1)
-
-#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
-#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
-
-#endif /* _ASM_SCORE_PROCESSOR_H */
diff --git a/arch/score/include/asm/ptrace.h b/arch/score/include/asm/ptrace.h
deleted file mode 100644
index 026b9c51bee8..000000000000
--- a/arch/score/include/asm/ptrace.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_PTRACE_H
-#define _ASM_SCORE_PTRACE_H
-
-#include <uapi/asm/ptrace.h>
-
-
-struct task_struct;
-
-/*
- * Does the process account for user or for system time?
- */
-#define user_mode(regs) ((regs->cp0_psr & 8) == 8)
-
-#define instruction_pointer(regs) ((unsigned long)(regs)->cp0_epc)
-#define profile_pc(regs) instruction_pointer(regs)
-#define user_stack_pointer(r) ((unsigned long)(r)->regs[0])
-
-extern void do_syscall_trace(struct pt_regs *regs, int entryexit);
-extern int read_tsk_long(struct task_struct *, unsigned long, unsigned long *);
-extern int read_tsk_short(struct task_struct *, unsigned long,
- unsigned short *);
-
-#define arch_has_single_step() (1)
-
-#endif /* _ASM_SCORE_PTRACE_H */
diff --git a/arch/score/include/asm/scoreregs.h b/arch/score/include/asm/scoreregs.h
deleted file mode 100644
index ff8d20a49aa7..000000000000
--- a/arch/score/include/asm/scoreregs.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_SCOREREGS_H
-#define _ASM_SCORE_SCOREREGS_H
-
-#include <linux/linkage.h>
-
-/* TIMER register */
-#define TIME0BASE 0x96080000
-#define P_TIMER0_CTRL (TIME0BASE + 0x00)
-#define P_TIMER0_CPP_CTRL (TIME0BASE + 0x04)
-#define P_TIMER0_PRELOAD (TIME0BASE + 0x08)
-#define P_TIMER0_CPP_REG (TIME0BASE + 0x0C)
-#define P_TIMER0_UPCNT (TIME0BASE + 0x10)
-
-/* Timer Controller Register */
-/* bit 0 Timer enable */
-#define TMR_DISABLE 0x0000
-#define TMR_ENABLE 0x0001
-
-/* bit 1 Interrupt enable */
-#define TMR_IE_DISABLE 0x0000
-#define TMR_IE_ENABLE 0x0002
-
-/* bit 2 Output enable */
-#define TMR_OE_DISABLE 0x0004
-#define TMR_OE_ENABLE 0x0000
-
-/* bit4 Up/Down counting selection */
-#define TMR_UD_DOWN 0x0000
-#define TMR_UD_UP 0x0010
-
-/* bit5 Up/Down counting control selection */
-#define TMR_UDS_UD 0x0000
-#define TMR_UDS_EXTUD 0x0020
-
-/* bit6 Time output mode */
-#define TMR_OM_TOGGLE 0x0000
-#define TMR_OM_PILSE 0x0040
-
-/* bit 8..9 External input active edge selection */
-#define TMR_ES_PE 0x0000
-#define TMR_ES_NE 0x0100
-#define TMR_ES_BOTH 0x0200
-
-/* bit 10..11 Operating mode */
-#define TMR_M_FREE 0x0000 /* free running timer mode */
-#define TMR_M_PERIODIC 0x0400 /* periodic timer mode */
-#define TMR_M_FC 0x0800 /* free running counter mode */
-#define TMR_M_PC 0x0c00 /* periodic counter mode */
-
-#define SYSTEM_CLOCK (27*1000000/4) /* 27 MHz */
-#endif /* _ASM_SCORE_SCOREREGS_H */
diff --git a/arch/score/include/asm/segment.h b/arch/score/include/asm/segment.h
deleted file mode 100644
index b00c277e17ff..000000000000
--- a/arch/score/include/asm/segment.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_SEGMENT_H
-#define _ASM_SCORE_SEGMENT_H
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-#define KERNEL_DS ((mm_segment_t){0})
-#define USER_DS KERNEL_DS
-
-# define get_ds() (KERNEL_DS)
-# define get_fs() (current_thread_info()->addr_limit)
-# define set_fs(x) \
- do { current_thread_info()->addr_limit = (x); } while (0)
-
-# define segment_eq(a, b) ((a).seg == (b).seg)
-
-# endif /* __ASSEMBLY__ */
-#endif /* _ASM_SCORE_SEGMENT_H */
diff --git a/arch/score/include/asm/setup.h b/arch/score/include/asm/setup.h
deleted file mode 100644
index a596d0bd0632..000000000000
--- a/arch/score/include/asm/setup.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_SETUP_H
-#define _ASM_SCORE_SETUP_H
-
-#include <uapi/asm/setup.h>
-
-
-extern void pagetable_init(void);
-extern void pgd_init(unsigned long page);
-
-extern void setup_early_printk(void);
-extern void cpu_cache_init(void);
-extern void tlb_init(void);
-
-extern void handle_nmi(void);
-extern void handle_adelinsn(void);
-extern void handle_adedata(void);
-extern void handle_ibe(void);
-extern void handle_pel(void);
-extern void handle_sys(void);
-extern void handle_ccu(void);
-extern void handle_ri(void);
-extern void handle_tr(void);
-extern void handle_ades(void);
-extern void handle_cee(void);
-extern void handle_cpe(void);
-extern void handle_dve(void);
-extern void handle_dbe(void);
-extern void handle_reserved(void);
-extern void handle_tlb_refill(void);
-extern void handle_tlb_invaild(void);
-extern void handle_mod(void);
-extern void debug_exception_vector(void);
-extern void general_exception_vector(void);
-extern void interrupt_exception_vector(void);
-
-#endif /* _ASM_SCORE_SETUP_H */
diff --git a/arch/score/include/asm/shmparam.h b/arch/score/include/asm/shmparam.h
deleted file mode 100644
index 01a3d0eaed80..000000000000
--- a/arch/score/include/asm/shmparam.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_SHMPARAM_H
-#define _ASM_SCORE_SHMPARAM_H
-
-#include <asm-generic/shmparam.h>
-
-#endif /* _ASM_SCORE_SHMPARAM_H */
diff --git a/arch/score/include/asm/string.h b/arch/score/include/asm/string.h
deleted file mode 100644
index 3debf3b234b7..000000000000
--- a/arch/score/include/asm/string.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_STRING_H
-#define _ASM_SCORE_STRING_H
-
-extern void *memset(void *__s, int __c, size_t __count);
-extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
-extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-
-#endif /* _ASM_SCORE_STRING_H */
diff --git a/arch/score/include/asm/switch_to.h b/arch/score/include/asm/switch_to.h
deleted file mode 100644
index ce730e60cd43..000000000000
--- a/arch/score/include/asm/switch_to.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_SWITCH_TO_H
-#define _ASM_SCORE_SWITCH_TO_H
-
-extern void *resume(void *last, void *next, void *next_ti);
-
-#define switch_to(prev, next, last) \
-do { \
- (last) = resume(prev, next, task_thread_info(next)); \
-} while (0)
-
-#endif /* _ASM_SCORE_SWITCH_TO_H */
diff --git a/arch/score/include/asm/syscalls.h b/arch/score/include/asm/syscalls.h
deleted file mode 100644
index caa099fd9a8e..000000000000
--- a/arch/score/include/asm/syscalls.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_SYSCALLS_H
-#define _ASM_SCORE_SYSCALLS_H
-
-asmlinkage long score_rt_sigreturn(struct pt_regs *regs);
-
-#include <asm-generic/syscalls.h>
-
-#endif /* _ASM_SCORE_SYSCALLS_H */
diff --git a/arch/score/include/asm/thread_info.h b/arch/score/include/asm/thread_info.h
deleted file mode 100644
index bc4c7c90550f..000000000000
--- a/arch/score/include/asm/thread_info.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_THREAD_INFO_H
-#define _ASM_SCORE_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#define KU_MASK 0x08
-#define KU_USER 0x08
-#define KU_KERN 0x00
-
-#include <asm/page.h>
-#include <linux/const.h>
-
-/* thread information allocation */
-#define THREAD_SIZE_ORDER (1)
-#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
-#define THREAD_MASK (THREAD_SIZE - _AC(1,UL))
-
-#ifndef __ASSEMBLY__
-
-#include <asm/processor.h>
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants
- * must also be changed
- */
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- unsigned long tp_value; /* thread pointer */
- __u32 cpu; /* current CPU */
-
- /* 0 => preemptable, < 0 => BUG */
- int preempt_count;
-
- /*
- * thread address space:
- * 0-0xBFFFFFFF for user-thead
- * 0-0xFFFFFFFF for kernel-thread
- */
- mm_segment_t addr_limit;
- struct pt_regs *regs;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- *
- * preempt_count needs to be 1 initially, until the scheduler is functional.
- */
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .cpu = 0, \
- .preempt_count = 1, \
- .addr_limit = KERNEL_DS, \
-}
-
-/* How to get the thread information struct from C. */
-register struct thread_info *__current_thread_info __asm__("r28");
-#define current_thread_info() __current_thread_info
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to
- * access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
-#define TIF_SIGPENDING 1 /* signal pending */
-#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
-#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
-#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
-#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
-
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-
-#define _TIF_WORK_MASK (0x0000ffff)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_SCORE_THREAD_INFO_H */
diff --git a/arch/score/include/asm/timex.h b/arch/score/include/asm/timex.h
deleted file mode 100644
index ea8e7ff49e57..000000000000
--- a/arch/score/include/asm/timex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_TIMEX_H
-#define _ASM_SCORE_TIMEX_H
-
-#define CLOCK_TICK_RATE 27000000 /* Timer input freq. */
-
-#include <asm-generic/timex.h>
-
-#endif /* _ASM_SCORE_TIMEX_H */
diff --git a/arch/score/include/asm/tlb.h b/arch/score/include/asm/tlb.h
deleted file mode 100644
index 6e7206428877..000000000000
--- a/arch/score/include/asm/tlb.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_TLB_H
-#define _ASM_SCORE_TLB_H
-
-/*
- * SCORE doesn't need any special per-pte or per-vma handling, except
- * we need to flush cache for area to be unmapped.
- */
-#define tlb_start_vma(tlb, vma) do {} while (0)
-#define tlb_end_vma(tlb, vma) do {} while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do {} while (0)
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-extern void score7_FTLB_refill_Handler(void);
-
-#include <asm-generic/tlb.h>
-
-#endif /* _ASM_SCORE_TLB_H */
diff --git a/arch/score/include/asm/tlbflush.h b/arch/score/include/asm/tlbflush.h
deleted file mode 100644
index f48722f4b00e..000000000000
--- a/arch/score/include/asm/tlbflush.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_TLBFLUSH_H
-#define _ASM_SCORE_TLBFLUSH_H
-
-#include <linux/mm.h>
-
-/*
- * TLB flushing:
- *
- * - flush_tlb_all() flushes all processes TLB entries
- * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(vma, start, end) flushes a range of pages
- * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- */
-extern void local_flush_tlb_all(void);
-extern void local_flush_tlb_mm(struct mm_struct *mm);
-extern void local_flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
-extern void local_flush_tlb_kernel_range(unsigned long start,
- unsigned long end);
-extern void local_flush_tlb_page(struct vm_area_struct *vma,
- unsigned long page);
-extern void local_flush_tlb_one(unsigned long vaddr);
-
-#define flush_tlb_all() local_flush_tlb_all()
-#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
-#define flush_tlb_range(vma, vmaddr, end) \
- local_flush_tlb_range(vma, vmaddr, end)
-#define flush_tlb_kernel_range(vmaddr, end) \
- local_flush_tlb_kernel_range(vmaddr, end)
-#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
-#define flush_tlb_one(vaddr) local_flush_tlb_one(vaddr)
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned long pevn_get(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- "mfcr %0, cr11\n"
- "nop\nnop\n"
- : "=r" (val));
-
- return val;
-}
-
-static inline void pevn_set(unsigned long val)
-{
- __asm__ __volatile__(
- "mtcr %0, cr11\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (val));
-}
-
-static inline void pectx_set(unsigned long val)
-{
- __asm__ __volatile__(
- "mtcr %0, cr12\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (val));
-}
-
-static inline unsigned long pectx_get(void)
-{
- unsigned long val;
- __asm__ __volatile__(
- "mfcr %0, cr12\n"
- "nop\nnop\n"
- : "=r" (val));
- return val;
-}
-static inline unsigned long tlblock_get(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- "mfcr %0, cr7\n"
- "nop\nnop\n"
- : "=r" (val));
- return val;
-}
-static inline void tlblock_set(unsigned long val)
-{
- __asm__ __volatile__(
- "mtcr %0, cr7\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (val));
-}
-
-static inline void tlbpt_set(unsigned long val)
-{
- __asm__ __volatile__(
- "mtcr %0, cr8\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (val));
-}
-
-static inline long tlbpt_get(void)
-{
- long val;
-
- __asm__ __volatile__(
- "mfcr %0, cr8\n"
- "nop\nnop\n"
- : "=r" (val));
-
- return val;
-}
-
-static inline void peaddr_set(unsigned long val)
-{
- __asm__ __volatile__(
- "mtcr %0, cr9\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (val));
-}
-
-/* TLB operations. */
-static inline void tlb_probe(void)
-{
- __asm__ __volatile__("stlb;nop;nop;nop;nop;nop");
-}
-
-static inline void tlb_read(void)
-{
- __asm__ __volatile__("mftlb;nop;nop;nop;nop;nop");
-}
-
-static inline void tlb_write_indexed(void)
-{
- __asm__ __volatile__("mtptlb;nop;nop;nop;nop;nop");
-}
-
-static inline void tlb_write_random(void)
-{
- __asm__ __volatile__("mtrtlb;nop;nop;nop;nop;nop");
-}
-
-#endif /* Not __ASSEMBLY__ */
-
-#endif /* _ASM_SCORE_TLBFLUSH_H */
diff --git a/arch/score/include/asm/topology.h b/arch/score/include/asm/topology.h
deleted file mode 100644
index 06577d2a1808..000000000000
--- a/arch/score/include/asm/topology.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_TOPOLOGY_H
-#define _ASM_SCORE_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_SCORE_TOPOLOGY_H */
diff --git a/arch/score/include/asm/uaccess.h b/arch/score/include/asm/uaccess.h
deleted file mode 100644
index a233f3236846..000000000000
--- a/arch/score/include/asm/uaccess.h
+++ /dev/null
@@ -1,373 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SCORE_UACCESS_H
-#define __SCORE_UACCESS_H
-
-#include <linux/kernel.h>
-#include <asm/extable.h>
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-/*
- * Is a address valid? This does a straighforward calculation rather
- * than tests.
- *
- * Address valid if:
- * - "addr" doesn't have any high-bits set
- * - AND "size" doesn't have any high-bits set
- * - AND "addr+size" doesn't have any high-bits set
- * - OR we are in kernel mode.
- *
- * __ua_size() is a trick to avoid runtime checking of positive constant
- * sizes; for those we already know at compile time that the size is ok.
- */
-#define __ua_size(size) \
- ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size))
-
-/*
- * access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
- * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- * to write to a block, it is always safe to read from it.
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns true (nonzero) if the memory block may be valid, false (zero)
- * if it is definitely invalid.
- *
- * Note that, depending on architecture, this function probably just
- * checks that the pointer is in the user space range - after calling
- * this function, memory access functions may still return -EFAULT.
- */
-
-#define __access_ok(addr, size) \
- (((long)((get_fs().seg) & \
- ((addr) | ((addr) + (size)) | \
- __ua_size(size)))) == 0)
-
-#define access_ok(type, addr, size) \
- likely(__access_ok((unsigned long)(addr), (size)))
-
-/*
- * put_user: - Write a simple value into user space.
- * @x: Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple value from kernel space to user
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define put_user(x, ptr) __put_user_check((x), (ptr), sizeof(*(ptr)))
-
-/*
- * get_user: - Get a simple variable from user space.
- * @x: Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple variable from user space to kernel
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr)))
-
-/*
- * __put_user: - Write a simple value into user space, with less checking.
- * @x: Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple value from kernel space to user
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define __put_user(x, ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-/*
- * __get_user: - Get a simple variable from user space, with less checking.
- * @x: Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple variable from user space to kernel
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct __user *)(x))
-
-/*
- * Yuck. We need two variants, one for 64bit operation and one
- * for 32 bit mode and old iron.
- */
-extern void __get_user_unknown(void);
-
-#define __get_user_common(val, size, ptr) \
-do { \
- switch (size) { \
- case 1: \
- __get_user_asm(val, "lb", ptr); \
- break; \
- case 2: \
- __get_user_asm(val, "lh", ptr); \
- break; \
- case 4: \
- __get_user_asm(val, "lw", ptr); \
- break; \
- case 8: \
- if (__copy_from_user((void *)&val, ptr, 8) == 0) \
- __gu_err = 0; \
- else \
- __gu_err = -EFAULT; \
- break; \
- default: \
- __get_user_unknown(); \
- break; \
- } \
-} while (0)
-
-#define __get_user_nocheck(x, ptr, size) \
-({ \
- long __gu_err = 0; \
- __get_user_common((x), size, ptr); \
- __gu_err; \
-})
-
-#define __get_user_check(x, ptr, size) \
-({ \
- long __gu_err = -EFAULT; \
- const __typeof__(*(ptr)) __user *__gu_ptr = (ptr); \
- \
- if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \
- __get_user_common((x), size, __gu_ptr); \
- else \
- (x) = 0; \
- \
- __gu_err; \
-})
-
-#define __get_user_asm(val, insn, addr) \
-{ \
- long __gu_tmp; \
- \
- __asm__ __volatile__( \
- "1:" insn " %1, %3\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3:li %0, %4\n" \
- "li %1, 0\n" \
- "j 2b\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- ".word 1b, 3b\n" \
- ".previous\n" \
- : "=r" (__gu_err), "=r" (__gu_tmp) \
- : "0" (0), "o" (__m(addr)), "i" (-EFAULT)); \
- \
- (val) = (__typeof__(*(addr))) __gu_tmp; \
-}
-
-/*
- * Yuck. We need two variants, one for 64bit operation and one
- * for 32 bit mode and old iron.
- */
-#define __put_user_nocheck(val, ptr, size) \
-({ \
- __typeof__(*(ptr)) __pu_val; \
- long __pu_err = 0; \
- \
- __pu_val = (val); \
- switch (size) { \
- case 1: \
- __put_user_asm("sb", ptr); \
- break; \
- case 2: \
- __put_user_asm("sh", ptr); \
- break; \
- case 4: \
- __put_user_asm("sw", ptr); \
- break; \
- case 8: \
- if ((__copy_to_user((void *)ptr, &__pu_val, 8)) == 0) \
- __pu_err = 0; \
- else \
- __pu_err = -EFAULT; \
- break; \
- default: \
- __put_user_unknown(); \
- break; \
- } \
- __pu_err; \
-})
-
-
-#define __put_user_check(val, ptr, size) \
-({ \
- __typeof__(*(ptr)) __user *__pu_addr = (ptr); \
- __typeof__(*(ptr)) __pu_val = (val); \
- long __pu_err = -EFAULT; \
- \
- if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \
- switch (size) { \
- case 1: \
- __put_user_asm("sb", __pu_addr); \
- break; \
- case 2: \
- __put_user_asm("sh", __pu_addr); \
- break; \
- case 4: \
- __put_user_asm("sw", __pu_addr); \
- break; \
- case 8: \
- if ((__copy_to_user((void *)__pu_addr, &__pu_val, 8)) == 0)\
- __pu_err = 0; \
- else \
- __pu_err = -EFAULT; \
- break; \
- default: \
- __put_user_unknown(); \
- break; \
- } \
- } \
- __pu_err; \
-})
-
-#define __put_user_asm(insn, ptr) \
- __asm__ __volatile__( \
- "1:" insn " %2, %3\n" \
- "2:\n" \
- ".section .fixup,\"ax\"\n" \
- "3:li %0, %4\n" \
- "j 2b\n" \
- ".previous\n" \
- ".section __ex_table,\"a\"\n" \
- ".word 1b, 3b\n" \
- ".previous\n" \
- : "=r" (__pu_err) \
- : "0" (0), "r" (__pu_val), "o" (__m(ptr)), \
- "i" (-EFAULT));
-
-extern void __put_user_unknown(void);
-extern int __copy_tofrom_user(void *to, const void *from, unsigned long len);
-
-static inline unsigned long
-raw_copy_from_user(void *to, const void __user *from, unsigned long len)
-{
- return __copy_tofrom_user(to, (__force const void *)from, len);
-}
-
-static inline unsigned long
-raw_copy_to_user(void __user *to, const void *from, unsigned long len)
-{
- return __copy_tofrom_user((__force void *)to, from, len);
-}
-
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-
-/*
- * __clear_user: - Zero a block of memory in user space, with less checking.
- * @to: Destination address, in user space.
- * @n: Number of bytes to zero.
- *
- * Zero a block of memory in user space. Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-extern unsigned long __clear_user(void __user *src, unsigned long size);
-
-static inline unsigned long clear_user(char *src, unsigned long size)
-{
- if (access_ok(VERIFY_WRITE, src, size))
- return __clear_user(src, size);
-
- return -EFAULT;
-}
-/*
- * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
- * @dst: Destination address, in kernel space. This buffer must be at
- * least @count bytes long.
- * @src: Source address, in user space.
- * @count: Maximum number of bytes to copy, including the trailing NUL.
- *
- * Copies a NUL-terminated string from userspace to kernel space.
- * Caller must check the specified block with access_ok() before calling
- * this function.
- *
- * On success, returns the length of the string (not including the trailing
- * NUL).
- *
- * If access to userspace fails, returns -EFAULT (some data may have been
- * copied).
- *
- * If @count is smaller than the length of the string, copies @count bytes
- * and returns @count.
- */
-extern int __strncpy_from_user(char *dst, const char *src, long len);
-
-static inline int strncpy_from_user(char *dst, const char *src, long len)
-{
- if (access_ok(VERIFY_READ, src, 1))
- return __strncpy_from_user(dst, src, len);
-
- return -EFAULT;
-}
-
-extern int __strnlen_user(const char *str, long len);
-static inline long strnlen_user(const char __user *str, long len)
-{
- if (!access_ok(VERIFY_READ, str, 0))
- return 0;
- else
- return __strnlen_user(str, len);
-}
-
-#endif /* __SCORE_UACCESS_H */
-
diff --git a/arch/score/include/asm/ucontext.h b/arch/score/include/asm/ucontext.h
deleted file mode 100644
index 9bc07b9f30fb..000000000000
--- a/arch/score/include/asm/ucontext.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ucontext.h>
diff --git a/arch/score/include/asm/unaligned.h b/arch/score/include/asm/unaligned.h
deleted file mode 100644
index 5db6c805ce7e..000000000000
--- a/arch/score/include/asm/unaligned.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_UNALIGNED_H
-#define _ASM_SCORE_UNALIGNED_H
-
-#include <asm-generic/unaligned.h>
-
-#endif /* _ASM_SCORE_UNALIGNED_H */
diff --git a/arch/score/include/asm/user.h b/arch/score/include/asm/user.h
deleted file mode 100644
index f7b0f3434e72..000000000000
--- a/arch/score/include/asm/user.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_SCORE_USER_H
-#define _ASM_SCORE_USER_H
-
-struct user_regs_struct {
- unsigned long regs[32];
-
- unsigned long cel;
- unsigned long ceh;
-
- unsigned long sr0; /* cnt */
- unsigned long sr1; /* lcr */
- unsigned long sr2; /* scr */
-
- unsigned long cp0_epc;
- unsigned long cp0_ema;
- unsigned long cp0_psr;
- unsigned long cp0_ecr;
- unsigned long cp0_condition;
-};
-
-#endif /* _ASM_SCORE_USER_H */
diff --git a/arch/score/include/uapi/asm/Kbuild b/arch/score/include/uapi/asm/Kbuild
deleted file mode 100644
index b04fd1632051..000000000000
--- a/arch/score/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,6 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += bpf_perf_event.h
-generic-y += poll.h
-generic-y += siginfo.h
diff --git a/arch/score/include/uapi/asm/auxvec.h b/arch/score/include/uapi/asm/auxvec.h
deleted file mode 100644
index f69151565aee..000000000000
--- a/arch/score/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_SCORE_AUXVEC_H
-#define _ASM_SCORE_AUXVEC_H
-
-#endif /* _ASM_SCORE_AUXVEC_H */
diff --git a/arch/score/include/uapi/asm/bitsperlong.h b/arch/score/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index df48f2717da2..000000000000
--- a/arch/score/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_BITSPERLONG_H
-#define _ASM_SCORE_BITSPERLONG_H
-
-#include <asm-generic/bitsperlong.h>
-
-#endif /* _ASM_SCORE_BITSPERLONG_H */
diff --git a/arch/score/include/uapi/asm/byteorder.h b/arch/score/include/uapi/asm/byteorder.h
deleted file mode 100644
index a5247ea66c03..000000000000
--- a/arch/score/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_BYTEORDER_H
-#define _ASM_SCORE_BYTEORDER_H
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _ASM_SCORE_BYTEORDER_H */
diff --git a/arch/score/include/uapi/asm/errno.h b/arch/score/include/uapi/asm/errno.h
deleted file mode 100644
index 1b914865714f..000000000000
--- a/arch/score/include/uapi/asm/errno.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_ERRNO_H
-#define _ASM_SCORE_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif /* _ASM_SCORE_ERRNO_H */
diff --git a/arch/score/include/uapi/asm/fcntl.h b/arch/score/include/uapi/asm/fcntl.h
deleted file mode 100644
index 9c5053b87c66..000000000000
--- a/arch/score/include/uapi/asm/fcntl.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_FCNTL_H
-#define _ASM_SCORE_FCNTL_H
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _ASM_SCORE_FCNTL_H */
diff --git a/arch/score/include/uapi/asm/ioctl.h b/arch/score/include/uapi/asm/ioctl.h
deleted file mode 100644
index d6cb6dc33d5f..000000000000
--- a/arch/score/include/uapi/asm/ioctl.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_IOCTL_H
-#define _ASM_SCORE_IOCTL_H
-
-#include <asm-generic/ioctl.h>
-
-#endif /* _ASM_SCORE_IOCTL_H */
diff --git a/arch/score/include/uapi/asm/ioctls.h b/arch/score/include/uapi/asm/ioctls.h
deleted file mode 100644
index b93b011f02aa..000000000000
--- a/arch/score/include/uapi/asm/ioctls.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_IOCTLS_H
-#define _ASM_SCORE_IOCTLS_H
-
-#include <asm-generic/ioctls.h>
-
-#endif /* _ASM_SCORE_IOCTLS_H */
diff --git a/arch/score/include/uapi/asm/ipcbuf.h b/arch/score/include/uapi/asm/ipcbuf.h
deleted file mode 100644
index 195ee525308d..000000000000
--- a/arch/score/include/uapi/asm/ipcbuf.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_IPCBUF_H
-#define _ASM_SCORE_IPCBUF_H
-
-#include <asm-generic/ipcbuf.h>
-
-#endif /* _ASM_SCORE_IPCBUF_H */
diff --git a/arch/score/include/uapi/asm/kvm_para.h b/arch/score/include/uapi/asm/kvm_para.h
deleted file mode 100644
index baacc4996d18..000000000000
--- a/arch/score/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/kvm_para.h>
diff --git a/arch/score/include/uapi/asm/mman.h b/arch/score/include/uapi/asm/mman.h
deleted file mode 100644
index b22b83809432..000000000000
--- a/arch/score/include/uapi/asm/mman.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_MMAN_H
-#define _ASM_SCORE_MMAN_H
-
-#include <asm-generic/mman.h>
-
-#endif /* _ASM_SCORE_MMAN_H */
diff --git a/arch/score/include/uapi/asm/msgbuf.h b/arch/score/include/uapi/asm/msgbuf.h
deleted file mode 100644
index b05a238756ab..000000000000
--- a/arch/score/include/uapi/asm/msgbuf.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_MSGBUF_H
-#define _ASM_SCORE_MSGBUF_H
-
-#include <asm-generic/msgbuf.h>
-
-#endif /* _ASM_SCORE_MSGBUF_H */
diff --git a/arch/score/include/uapi/asm/param.h b/arch/score/include/uapi/asm/param.h
deleted file mode 100644
index ce09e2632681..000000000000
--- a/arch/score/include/uapi/asm/param.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_PARAM_H
-#define _ASM_SCORE_PARAM_H
-
-#include <asm-generic/param.h>
-
-#endif /* _ASM_SCORE_PARAM_H */
diff --git a/arch/score/include/uapi/asm/posix_types.h b/arch/score/include/uapi/asm/posix_types.h
deleted file mode 100644
index 63200d56a4a9..000000000000
--- a/arch/score/include/uapi/asm/posix_types.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_POSIX_TYPES_H
-#define _ASM_SCORE_POSIX_TYPES_H
-
-#include <asm-generic/posix_types.h>
-
-#endif /* _ASM_SCORE_POSIX_TYPES_H */
diff --git a/arch/score/include/uapi/asm/ptrace.h b/arch/score/include/uapi/asm/ptrace.h
deleted file mode 100644
index e8bd4923f96e..000000000000
--- a/arch/score/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_SCORE_PTRACE_H
-#define _UAPI_ASM_SCORE_PTRACE_H
-
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-
-#define SINGLESTEP16_INSN 0x7006
-#define SINGLESTEP32_INSN 0x840C8000
-#define BREAKPOINT16_INSN 0x7002 /* work on SPG300 */
-#define BREAKPOINT32_INSN 0x84048000 /* work on SPG300 */
-
-/* Define instruction mask */
-#define INSN32_MASK 0x80008000
-
-#define J32 0x88008000 /* 1_00010_0000000000_1_000000000000000 */
-#define J32M 0xFC008000 /* 1_11111_0000000000_1_000000000000000 */
-
-#define B32 0x90008000 /* 1_00100_0000000000_1_000000000000000 */
-#define B32M 0xFC008000
-#define BL32 0x90008001 /* 1_00100_0000000000_1_000000000000001 */
-#define BL32M B32
-#define BR32 0x80008008 /* 1_00000_0000000000_1_00000000_000100_0 */
-#define BR32M 0xFFE0807E
-#define BRL32 0x80008009 /* 1_00000_0000000000_1_00000000_000100_1 */
-#define BRL32M BR32M
-
-#define B32_SET (J32 | B32 | BL32 | BR32 | BRL32)
-
-#define J16 0x3000 /* 0_011_....... */
-#define J16M 0xF000
-#define B16 0x4000 /* 0_100_....... */
-#define B16M 0xF000
-#define BR16 0x0004 /* 0_000.......0100 */
-#define BR16M 0xF00F
-#define B16_SET (J16 | B16 | BR16)
-
-
-/*
- * This struct defines the way the registers are stored on the stack during a
- * system call/exception. As usual the registers k0/k1 aren't being saved.
- */
-struct pt_regs {
- unsigned long pad0[6]; /* stack arguments */
- unsigned long orig_r4;
- unsigned long orig_r7;
- long is_syscall;
-
- unsigned long regs[32];
-
- unsigned long cel;
- unsigned long ceh;
-
- unsigned long sr0; /* cnt */
- unsigned long sr1; /* lcr */
- unsigned long sr2; /* scr */
-
- unsigned long cp0_epc;
- unsigned long cp0_ema;
- unsigned long cp0_psr;
- unsigned long cp0_ecr;
- unsigned long cp0_condition;
-};
-
-
-#endif /* _UAPI_ASM_SCORE_PTRACE_H */
diff --git a/arch/score/include/uapi/asm/resource.h b/arch/score/include/uapi/asm/resource.h
deleted file mode 100644
index df3fb9c942c4..000000000000
--- a/arch/score/include/uapi/asm/resource.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_RESOURCE_H
-#define _ASM_SCORE_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _ASM_SCORE_RESOURCE_H */
diff --git a/arch/score/include/uapi/asm/sembuf.h b/arch/score/include/uapi/asm/sembuf.h
deleted file mode 100644
index c16e7a94725d..000000000000
--- a/arch/score/include/uapi/asm/sembuf.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_SEMBUF_H
-#define _ASM_SCORE_SEMBUF_H
-
-#include <asm-generic/sembuf.h>
-
-#endif /* _ASM_SCORE_SEMBUF_H */
diff --git a/arch/score/include/uapi/asm/setup.h b/arch/score/include/uapi/asm/setup.h
deleted file mode 100644
index dee58323847e..000000000000
--- a/arch/score/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _UAPI_ASM_SCORE_SETUP_H
-#define _UAPI_ASM_SCORE_SETUP_H
-
-#define COMMAND_LINE_SIZE 256
-#define MEMORY_START 0
-#define MEMORY_SIZE 0x2000000
-
-
-#endif /* _UAPI_ASM_SCORE_SETUP_H */
diff --git a/arch/score/include/uapi/asm/shmbuf.h b/arch/score/include/uapi/asm/shmbuf.h
deleted file mode 100644
index f38acfe733cd..000000000000
--- a/arch/score/include/uapi/asm/shmbuf.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_SHMBUF_H
-#define _ASM_SCORE_SHMBUF_H
-
-#include <asm-generic/shmbuf.h>
-
-#endif /* _ASM_SCORE_SHMBUF_H */
diff --git a/arch/score/include/uapi/asm/sigcontext.h b/arch/score/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 2b0cd93a71f6..000000000000
--- a/arch/score/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_SIGCONTEXT_H
-#define _ASM_SCORE_SIGCONTEXT_H
-
-/*
- * Keep this struct definition in sync with the sigcontext fragment
- * in arch/score/tools/offset.c
- */
-struct sigcontext {
- unsigned int sc_regmask;
- unsigned int sc_psr;
- unsigned int sc_condition;
- unsigned long sc_pc;
- unsigned long sc_regs[32];
- unsigned int sc_ssflags;
- unsigned int sc_mdceh;
- unsigned int sc_mdcel;
- unsigned int sc_ecr;
- unsigned long sc_ema;
- unsigned long sc_sigset[4];
-};
-
-#endif /* _ASM_SCORE_SIGCONTEXT_H */
diff --git a/arch/score/include/uapi/asm/signal.h b/arch/score/include/uapi/asm/signal.h
deleted file mode 100644
index 7fb694972302..000000000000
--- a/arch/score/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_SIGNAL_H
-#define _ASM_SCORE_SIGNAL_H
-
-#include <asm-generic/signal.h>
-
-#endif /* _ASM_SCORE_SIGNAL_H */
diff --git a/arch/score/include/uapi/asm/socket.h b/arch/score/include/uapi/asm/socket.h
deleted file mode 100644
index f76ba1f72354..000000000000
--- a/arch/score/include/uapi/asm/socket.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_SOCKET_H
-#define _ASM_SCORE_SOCKET_H
-
-#include <asm-generic/socket.h>
-
-#endif /* _ASM_SCORE_SOCKET_H */
diff --git a/arch/score/include/uapi/asm/sockios.h b/arch/score/include/uapi/asm/sockios.h
deleted file mode 100644
index d0af8ce4373b..000000000000
--- a/arch/score/include/uapi/asm/sockios.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_SOCKIOS_H
-#define _ASM_SCORE_SOCKIOS_H
-
-#include <asm-generic/sockios.h>
-
-#endif /* _ASM_SCORE_SOCKIOS_H */
diff --git a/arch/score/include/uapi/asm/stat.h b/arch/score/include/uapi/asm/stat.h
deleted file mode 100644
index 669b69f764df..000000000000
--- a/arch/score/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_STAT_H
-#define _ASM_SCORE_STAT_H
-
-#include <asm-generic/stat.h>
-
-#endif /* _ASM_SCORE_STAT_H */
diff --git a/arch/score/include/uapi/asm/statfs.h b/arch/score/include/uapi/asm/statfs.h
deleted file mode 100644
index bb92b3e5525d..000000000000
--- a/arch/score/include/uapi/asm/statfs.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_STATFS_H
-#define _ASM_SCORE_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif /* _ASM_SCORE_STATFS_H */
diff --git a/arch/score/include/uapi/asm/swab.h b/arch/score/include/uapi/asm/swab.h
deleted file mode 100644
index 52b0927282b1..000000000000
--- a/arch/score/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_SWAB_H
-#define _ASM_SCORE_SWAB_H
-
-#include <asm-generic/swab.h>
-
-#endif /* _ASM_SCORE_SWAB_H */
diff --git a/arch/score/include/uapi/asm/termbits.h b/arch/score/include/uapi/asm/termbits.h
deleted file mode 100644
index 4a6f5511cd56..000000000000
--- a/arch/score/include/uapi/asm/termbits.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_TERMBITS_H
-#define _ASM_SCORE_TERMBITS_H
-
-#include <asm-generic/termbits.h>
-
-#endif /* _ASM_SCORE_TERMBITS_H */
diff --git a/arch/score/include/uapi/asm/termios.h b/arch/score/include/uapi/asm/termios.h
deleted file mode 100644
index fabb598ecfa3..000000000000
--- a/arch/score/include/uapi/asm/termios.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_TERMIOS_H
-#define _ASM_SCORE_TERMIOS_H
-
-#include <asm-generic/termios.h>
-
-#endif /* _ASM_SCORE_TERMIOS_H */
diff --git a/arch/score/include/uapi/asm/types.h b/arch/score/include/uapi/asm/types.h
deleted file mode 100644
index 8515287f412a..000000000000
--- a/arch/score/include/uapi/asm/types.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#ifndef _ASM_SCORE_TYPES_H
-#define _ASM_SCORE_TYPES_H
-
-#include <asm-generic/types.h>
-
-#endif /* _ASM_SCORE_TYPES_H */
diff --git a/arch/score/include/uapi/asm/unistd.h b/arch/score/include/uapi/asm/unistd.h
deleted file mode 100644
index 04da47bd3d46..000000000000
--- a/arch/score/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#define __ARCH_HAVE_MMU
-
-#define __ARCH_WANT_RENAMEAT
-#define __ARCH_WANT_SYSCALL_NO_AT
-#define __ARCH_WANT_SYSCALL_NO_FLAGS
-#define __ARCH_WANT_SYSCALL_OFF_T
-#define __ARCH_WANT_SYSCALL_DEPRECATED
-#define __ARCH_WANT_SYS_CLONE
-#define __ARCH_WANT_SYS_FORK
-#define __ARCH_WANT_SYS_VFORK
-
-#include <asm-generic/unistd.h>
diff --git a/arch/score/kernel/Makefile b/arch/score/kernel/Makefile
deleted file mode 100644
index 42def8cff873..000000000000
--- a/arch/score/kernel/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Linux/SCORE kernel.
-#
-
-extra-y := head.o vmlinux.lds
-
-obj-y += entry.o irq.o process.o ptrace.o \
- setup.o signal.o sys_score.o time.o traps.o \
- sys_call_table.o
-
-obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/score/kernel/asm-offsets.c b/arch/score/kernel/asm-offsets.c
deleted file mode 100644
index 52794f9421e2..000000000000
--- a/arch/score/kernel/asm-offsets.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * arch/score/kernel/asm-offsets.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/kbuild.h>
-#include <linux/interrupt.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-
-#include <asm-generic/cmpxchg-local.h>
-
-void output_ptreg_defines(void)
-{
- COMMENT("SCORE pt_regs offsets.");
- OFFSET(PT_R0, pt_regs, regs[0]);
- OFFSET(PT_R1, pt_regs, regs[1]);
- OFFSET(PT_R2, pt_regs, regs[2]);
- OFFSET(PT_R3, pt_regs, regs[3]);
- OFFSET(PT_R4, pt_regs, regs[4]);
- OFFSET(PT_R5, pt_regs, regs[5]);
- OFFSET(PT_R6, pt_regs, regs[6]);
- OFFSET(PT_R7, pt_regs, regs[7]);
- OFFSET(PT_R8, pt_regs, regs[8]);
- OFFSET(PT_R9, pt_regs, regs[9]);
- OFFSET(PT_R10, pt_regs, regs[10]);
- OFFSET(PT_R11, pt_regs, regs[11]);
- OFFSET(PT_R12, pt_regs, regs[12]);
- OFFSET(PT_R13, pt_regs, regs[13]);
- OFFSET(PT_R14, pt_regs, regs[14]);
- OFFSET(PT_R15, pt_regs, regs[15]);
- OFFSET(PT_R16, pt_regs, regs[16]);
- OFFSET(PT_R17, pt_regs, regs[17]);
- OFFSET(PT_R18, pt_regs, regs[18]);
- OFFSET(PT_R19, pt_regs, regs[19]);
- OFFSET(PT_R20, pt_regs, regs[20]);
- OFFSET(PT_R21, pt_regs, regs[21]);
- OFFSET(PT_R22, pt_regs, regs[22]);
- OFFSET(PT_R23, pt_regs, regs[23]);
- OFFSET(PT_R24, pt_regs, regs[24]);
- OFFSET(PT_R25, pt_regs, regs[25]);
- OFFSET(PT_R26, pt_regs, regs[26]);
- OFFSET(PT_R27, pt_regs, regs[27]);
- OFFSET(PT_R28, pt_regs, regs[28]);
- OFFSET(PT_R29, pt_regs, regs[29]);
- OFFSET(PT_R30, pt_regs, regs[30]);
- OFFSET(PT_R31, pt_regs, regs[31]);
-
- OFFSET(PT_ORIG_R4, pt_regs, orig_r4);
- OFFSET(PT_ORIG_R7, pt_regs, orig_r7);
- OFFSET(PT_CEL, pt_regs, cel);
- OFFSET(PT_CEH, pt_regs, ceh);
- OFFSET(PT_SR0, pt_regs, sr0);
- OFFSET(PT_SR1, pt_regs, sr1);
- OFFSET(PT_SR2, pt_regs, sr2);
- OFFSET(PT_EPC, pt_regs, cp0_epc);
- OFFSET(PT_EMA, pt_regs, cp0_ema);
- OFFSET(PT_PSR, pt_regs, cp0_psr);
- OFFSET(PT_ECR, pt_regs, cp0_ecr);
- OFFSET(PT_CONDITION, pt_regs, cp0_condition);
- OFFSET(PT_IS_SYSCALL, pt_regs, is_syscall);
-
- DEFINE(PT_SIZE, sizeof(struct pt_regs));
- BLANK();
-}
-
-void output_task_defines(void)
-{
- COMMENT("SCORE task_struct offsets.");
- OFFSET(TASK_STATE, task_struct, state);
- OFFSET(TASK_THREAD_INFO, task_struct, stack);
- OFFSET(TASK_FLAGS, task_struct, flags);
- OFFSET(TASK_MM, task_struct, mm);
- OFFSET(TASK_PID, task_struct, pid);
- DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
- BLANK();
-}
-
-void output_thread_info_defines(void)
-{
- COMMENT("SCORE thread_info offsets.");
- OFFSET(TI_TASK, thread_info, task);
- OFFSET(TI_FLAGS, thread_info, flags);
- OFFSET(TI_TP_VALUE, thread_info, tp_value);
- OFFSET(TI_CPU, thread_info, cpu);
- OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
- OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
- OFFSET(TI_REGS, thread_info, regs);
- DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
- DEFINE(KERNEL_STACK_MASK, THREAD_MASK);
- BLANK();
-}
-
-void output_thread_defines(void)
-{
- COMMENT("SCORE specific thread_struct offsets.");
- OFFSET(THREAD_REG0, task_struct, thread.reg0);
- OFFSET(THREAD_REG2, task_struct, thread.reg2);
- OFFSET(THREAD_REG3, task_struct, thread.reg3);
- OFFSET(THREAD_REG12, task_struct, thread.reg12);
- OFFSET(THREAD_REG13, task_struct, thread.reg13);
- OFFSET(THREAD_REG14, task_struct, thread.reg14);
- OFFSET(THREAD_REG15, task_struct, thread.reg15);
- OFFSET(THREAD_REG16, task_struct, thread.reg16);
- OFFSET(THREAD_REG17, task_struct, thread.reg17);
- OFFSET(THREAD_REG18, task_struct, thread.reg18);
- OFFSET(THREAD_REG19, task_struct, thread.reg19);
- OFFSET(THREAD_REG20, task_struct, thread.reg20);
- OFFSET(THREAD_REG21, task_struct, thread.reg21);
- OFFSET(THREAD_REG29, task_struct, thread.reg29);
-
- OFFSET(THREAD_PSR, task_struct, thread.cp0_psr);
- OFFSET(THREAD_EMA, task_struct, thread.cp0_ema);
- OFFSET(THREAD_BADUADDR, task_struct, thread.cp0_baduaddr);
- OFFSET(THREAD_ECODE, task_struct, thread.error_code);
- OFFSET(THREAD_TRAPNO, task_struct, thread.trap_no);
- BLANK();
-}
-
-void output_mm_defines(void)
-{
- COMMENT("Size of struct page");
- DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
- BLANK();
- COMMENT("Linux mm_struct offsets.");
- OFFSET(MM_USERS, mm_struct, mm_users);
- OFFSET(MM_PGD, mm_struct, pgd);
- OFFSET(MM_CONTEXT, mm_struct, context);
- BLANK();
- DEFINE(_PAGE_SIZE, PAGE_SIZE);
- DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
- BLANK();
- DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
- DEFINE(_PTE_T_SIZE, sizeof(pte_t));
- BLANK();
- DEFINE(_PGD_ORDER, PGD_ORDER);
- DEFINE(_PTE_ORDER, PTE_ORDER);
- BLANK();
- DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
- BLANK();
- DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
- DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
- BLANK();
-}
-
-void output_sc_defines(void)
-{
- COMMENT("Linux sigcontext offsets.");
- OFFSET(SC_REGS, sigcontext, sc_regs);
- OFFSET(SC_MDCEH, sigcontext, sc_mdceh);
- OFFSET(SC_MDCEL, sigcontext, sc_mdcel);
- OFFSET(SC_PC, sigcontext, sc_pc);
- OFFSET(SC_PSR, sigcontext, sc_psr);
- OFFSET(SC_ECR, sigcontext, sc_ecr);
- OFFSET(SC_EMA, sigcontext, sc_ema);
- BLANK();
-}
-
-void output_signal_defined(void)
-{
- COMMENT("Linux signal numbers.");
- DEFINE(_SIGHUP, SIGHUP);
- DEFINE(_SIGINT, SIGINT);
- DEFINE(_SIGQUIT, SIGQUIT);
- DEFINE(_SIGILL, SIGILL);
- DEFINE(_SIGTRAP, SIGTRAP);
- DEFINE(_SIGIOT, SIGIOT);
- DEFINE(_SIGABRT, SIGABRT);
- DEFINE(_SIGFPE, SIGFPE);
- DEFINE(_SIGKILL, SIGKILL);
- DEFINE(_SIGBUS, SIGBUS);
- DEFINE(_SIGSEGV, SIGSEGV);
- DEFINE(_SIGSYS, SIGSYS);
- DEFINE(_SIGPIPE, SIGPIPE);
- DEFINE(_SIGALRM, SIGALRM);
- DEFINE(_SIGTERM, SIGTERM);
- DEFINE(_SIGUSR1, SIGUSR1);
- DEFINE(_SIGUSR2, SIGUSR2);
- DEFINE(_SIGCHLD, SIGCHLD);
- DEFINE(_SIGPWR, SIGPWR);
- DEFINE(_SIGWINCH, SIGWINCH);
- DEFINE(_SIGURG, SIGURG);
- DEFINE(_SIGIO, SIGIO);
- DEFINE(_SIGSTOP, SIGSTOP);
- DEFINE(_SIGTSTP, SIGTSTP);
- DEFINE(_SIGCONT, SIGCONT);
- DEFINE(_SIGTTIN, SIGTTIN);
- DEFINE(_SIGTTOU, SIGTTOU);
- DEFINE(_SIGVTALRM, SIGVTALRM);
- DEFINE(_SIGPROF, SIGPROF);
- DEFINE(_SIGXCPU, SIGXCPU);
- DEFINE(_SIGXFSZ, SIGXFSZ);
- BLANK();
-}
diff --git a/arch/score/kernel/entry.S b/arch/score/kernel/entry.S
deleted file mode 100644
index befb87d30a89..000000000000
--- a/arch/score/kernel/entry.S
+++ /dev/null
@@ -1,493 +0,0 @@
-/*
- * arch/score/kernel/entry.S
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/linkage.h>
-
-#include <asm/asmmacro.h>
-#include <asm/thread_info.h>
-#include <asm/unistd.h>
-
-/*
- * disable interrupts.
- */
-.macro disable_irq
- mfcr r8, cr0
- srli r8, r8, 1
- slli r8, r8, 1
- mtcr r8, cr0
- nop
- nop
- nop
- nop
- nop
-.endm
-
-/*
- * enable interrupts.
- */
-.macro enable_irq
- mfcr r8, cr0
- ori r8, 1
- mtcr r8, cr0
- nop
- nop
- nop
- nop
- nop
-.endm
-
-__INIT
-ENTRY(debug_exception_vector)
- nop!
- nop!
- nop!
- nop!
- nop!
- nop!
- nop!
- nop!
-
-ENTRY(general_exception_vector) # should move to addr 0x200
- j general_exception
- nop!
- nop!
- nop!
- nop!
- nop!
- nop!
-
-ENTRY(interrupt_exception_vector) # should move to addr 0x210
- j interrupt_exception
- nop!
- nop!
- nop!
- nop!
- nop!
- nop!
-
- .section ".text", "ax"
- .align 2;
-general_exception:
- mfcr r31, cr2
- nop
- la r30, exception_handlers
- andi r31, 0x1f # get ecr.exc_code
- slli r31, r31, 2
- add r30, r30, r31
- lw r30, [r30]
- br r30
-
-interrupt_exception:
- SAVE_ALL
- mfcr r4, cr2
- nop
- lw r16, [r28, TI_REGS]
- sw r0, [r28, TI_REGS]
- la r3, ret_from_irq
- srli r4, r4, 18 # get ecr.ip[7:2], interrupt No.
- mv r5, r0
- j do_IRQ
-
-ENTRY(handle_nmi) # NMI #1
- SAVE_ALL
- mv r4, r0
- la r8, nmi_exception_handler
- brl r8
- j restore_all
-
-ENTRY(handle_adelinsn) # AdEL-instruction #2
- SAVE_ALL
- mfcr r8, cr6
- nop
- nop
- sw r8, [r0, PT_EMA]
- mv r4, r0
- la r8, do_adelinsn
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_ibe) # BusEL-instruction #5
- SAVE_ALL
- mv r4, r0
- la r8, do_be
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_pel) # P-EL #6
- SAVE_ALL
- mv r4, r0
- la r8, do_pel
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_ccu) # CCU #8
- SAVE_ALL
- mv r4, r0
- la r8, do_ccu
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_ri) # RI #9
- SAVE_ALL
- mv r4, r0
- la r8, do_ri
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_tr) # Trap #10
- SAVE_ALL
- mv r4, r0
- la r8, do_tr
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_adedata) # AdES-instruction #12
- SAVE_ALL
- mfcr r8, cr6
- nop
- nop
- sw r8, [r0, PT_EMA]
- mv r4, r0
- la r8, do_adedata
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_cee) # CeE #16
- SAVE_ALL
- mv r4, r0
- la r8, do_cee
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_cpe) # CpE #17
- SAVE_ALL
- mv r4, r0
- la r8, do_cpe
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_dbe) # BusEL-data #18
- SAVE_ALL
- mv r4, r0
- la r8, do_be
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-ENTRY(handle_reserved) # others
- SAVE_ALL
- mv r4, r0
- la r8, do_reserved
- brl r8
- mv r4, r0
- j ret_from_exception
- nop
-
-#ifndef CONFIG_PREEMPT
-#define resume_kernel restore_all
-#else
-#define __ret_from_irq ret_from_exception
-#endif
-
- .align 2
-#ifndef CONFIG_PREEMPT
-ENTRY(ret_from_exception)
- disable_irq # preempt stop
- nop
- j __ret_from_irq
- nop
-#endif
-
-ENTRY(ret_from_irq)
- sw r16, [r28, TI_REGS]
-
-ENTRY(__ret_from_irq)
- lw r8, [r0, PT_PSR] # returning to kernel mode?
- andri.c r8, r8, KU_USER
- beq resume_kernel
-
-resume_userspace:
- disable_irq
- lw r6, [r28, TI_FLAGS] # current->work
- li r8, _TIF_WORK_MASK
- and.c r8, r8, r6 # ignoring syscall_trace
- bne work_pending
- nop
- j restore_all
- nop
-
-#ifdef CONFIG_PREEMPT
-resume_kernel:
- disable_irq
- lw r8, [r28, TI_PRE_COUNT]
- cmpz.c r8
- bne restore_all
-need_resched:
- lw r8, [r28, TI_FLAGS]
- andri.c r9, r8, _TIF_NEED_RESCHED
- beq restore_all
- lw r8, [r28, PT_PSR] # Interrupts off?
- andri.c r8, r8, 1
- beq restore_all
- bl preempt_schedule_irq
- nop
- j need_resched
- nop
-#endif
-
-ENTRY(ret_from_kernel_thread)
- bl schedule_tail # r4=struct task_struct *prev
- nop
- mv r4, r13
- brl r12
- j syscall_exit
-
-ENTRY(ret_from_fork)
- bl schedule_tail # r4=struct task_struct *prev
-
-ENTRY(syscall_exit)
- nop
- disable_irq
- lw r6, [r28, TI_FLAGS] # current->work
- li r8, _TIF_WORK_MASK
- and.c r8, r6, r8
- bne syscall_exit_work
-
-ENTRY(restore_all) # restore full frame
- RESTORE_ALL_AND_RET
-
-work_pending:
- andri.c r8, r6, _TIF_NEED_RESCHED # r6 is preloaded with TI_FLAGS
- beq work_notifysig
-work_resched:
- bl schedule
- nop
- disable_irq
- lw r6, [r28, TI_FLAGS]
- li r8, _TIF_WORK_MASK
- and.c r8, r6, r8 # is there any work to be done
- # other than syscall tracing?
- beq restore_all
- andri.c r8, r6, _TIF_NEED_RESCHED
- bne work_resched
-
-work_notifysig:
- mv r4, r0
- li r5, 0
- bl do_notify_resume # r6 already loaded
- nop
- j resume_userspace
- nop
-
-ENTRY(syscall_exit_work)
- li r8, _TIF_SYSCALL_TRACE
- and.c r8, r8, r6 # r6 is preloaded with TI_FLAGS
- beq work_pending # trace bit set?
- nop
- enable_irq
- mv r4, r0
- li r5, 1
- bl do_syscall_trace
- nop
- b resume_userspace
- nop
-
-.macro save_context reg
- sw r12, [\reg, THREAD_REG12];
- sw r13, [\reg, THREAD_REG13];
- sw r14, [\reg, THREAD_REG14];
- sw r15, [\reg, THREAD_REG15];
- sw r16, [\reg, THREAD_REG16];
- sw r17, [\reg, THREAD_REG17];
- sw r18, [\reg, THREAD_REG18];
- sw r19, [\reg, THREAD_REG19];
- sw r20, [\reg, THREAD_REG20];
- sw r21, [\reg, THREAD_REG21];
- sw r29, [\reg, THREAD_REG29];
- sw r2, [\reg, THREAD_REG2];
- sw r0, [\reg, THREAD_REG0]
-.endm
-
-.macro restore_context reg
- lw r12, [\reg, THREAD_REG12];
- lw r13, [\reg, THREAD_REG13];
- lw r14, [\reg, THREAD_REG14];
- lw r15, [\reg, THREAD_REG15];
- lw r16, [\reg, THREAD_REG16];
- lw r17, [\reg, THREAD_REG17];
- lw r18, [\reg, THREAD_REG18];
- lw r19, [\reg, THREAD_REG19];
- lw r20, [\reg, THREAD_REG20];
- lw r21, [\reg, THREAD_REG21];
- lw r29, [\reg, THREAD_REG29];
- lw r0, [\reg, THREAD_REG0];
- lw r2, [\reg, THREAD_REG2];
- lw r3, [\reg, THREAD_REG3]
-.endm
-
-/*
- * task_struct *resume(task_struct *prev, task_struct *next,
- * struct thread_info *next_ti)
- */
-ENTRY(resume)
- mfcr r9, cr0
- nop
- nop
- sw r9, [r4, THREAD_PSR]
- save_context r4
- sw r3, [r4, THREAD_REG3]
-
- mv r28, r6
- restore_context r5
- mv r8, r6
- addi r8, KERNEL_STACK_SIZE
- subi r8, 32
- la r9, kernelsp;
- sw r8, [r9];
-
- mfcr r9, cr0
- ldis r7, 0x00ff
- nop
- and r9, r9, r7
- lw r6, [r5, THREAD_PSR]
- not r7, r7
- and r6, r6, r7
- or r6, r6, r9
- mtcr r6, cr0
- nop; nop; nop; nop; nop
- br r3
-
-ENTRY(handle_sys)
- SAVE_ALL
- sw r8, [r0, 16] # argument 5 from user r8
- sw r9, [r0, 20] # argument 6 from user r9
- enable_irq
-
- sw r4, [r0, PT_ORIG_R4] #for restart syscall
- sw r7, [r0, PT_ORIG_R7] #for restart syscall
- sw r27, [r0, PT_IS_SYSCALL] # it from syscall
-
- lw r9, [r0, PT_EPC] # skip syscall on return
- addi r9, 4
- sw r9, [r0, PT_EPC]
-
- cmpi.c r27, __NR_syscalls # check syscall number
- bcs illegal_syscall
-
- slli r8, r27, 2 # get syscall routine
- la r11, sys_call_table
- add r11, r11, r8
- lw r10, [r11] # get syscall entry
-
- cmpz.c r10
- beq illegal_syscall
-
- lw r8, [r28, TI_FLAGS]
- li r9, _TIF_SYSCALL_TRACE
- and.c r8, r8, r9
- bne syscall_trace_entry
-
- brl r10 # Do The Real system call
-
- cmpi.c r4, 0
- blt 1f
- ldi r8, 0
- sw r8, [r0, PT_R7]
- b 2f
-1:
- cmpi.c r4, -MAX_ERRNO - 1
- ble 2f
- ldi r8, 0x1;
- sw r8, [r0, PT_R7]
- neg r4, r4
-2:
- sw r4, [r0, PT_R4] # save result
-
-syscall_return:
- disable_irq
- lw r6, [r28, TI_FLAGS] # current->work
- li r8, _TIF_WORK_MASK
- and.c r8, r6, r8
- bne syscall_return_work
- j restore_all
-
-syscall_return_work:
- j syscall_exit_work
-
-syscall_trace_entry:
- mv r16, r10
- mv r4, r0
- li r5, 0
- bl do_syscall_trace
-
- mv r8, r16
- lw r4, [r0, PT_R4] # Restore argument registers
- lw r5, [r0, PT_R5]
- lw r6, [r0, PT_R6]
- lw r7, [r0, PT_R7]
- brl r8
-
- li r8, -MAX_ERRNO - 1
- sw r8, [r0, PT_R7] # set error flag
-
- neg r4, r4 # error
- sw r4, [r0, PT_R0] # set flag for syscall
- # restarting
-1: sw r4, [r0, PT_R2] # result
- j syscall_exit
-
-illegal_syscall:
- ldi r4, -ENOSYS # error
- sw r4, [r0, PT_ORIG_R4]
- sw r4, [r0, PT_R4]
- ldi r9, 1 # set error flag
- sw r9, [r0, PT_R7]
- j syscall_return
-
-ENTRY(sys_rt_sigreturn)
- mv r4, r0
- la r8, score_rt_sigreturn
- br r8
diff --git a/arch/score/kernel/head.S b/arch/score/kernel/head.S
deleted file mode 100644
index 22a7e3c7292b..000000000000
--- a/arch/score/kernel/head.S
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/score/kernel/head.S
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#include <linux/init.h>
-#include <linux/linkage.h>
-
-#include <asm/asm-offsets.h>
-
- .extern start_kernel
- .global init_thread_union
- .global kernelsp
-
-__INIT
-ENTRY(_stext)
- la r30, __bss_start /* initialize BSS segment. */
- la r31, _end
- xor r8, r8, r8
-
-1: cmp.c r31, r30
- beq 2f
-
- sw r8, [r30] /* clean memory. */
- addi r30, 4
- b 1b
-
-2: la r28, init_thread_union /* set kernel stack. */
- mv r0, r28
- addi r0, KERNEL_STACK_SIZE - 32
- la r30, kernelsp
- sw r0, [r30]
- subi r0, 4*4
- xor r30, r30, r30
- ori r30, 0x02 /* enable MMU. */
- mtcr r30, cr4
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* there is no parameter */
- xor r4, r4, r4
- xor r5, r5, r5
- xor r6, r6, r6
- xor r7, r7, r7
- la r30, start_kernel /* jump to init_arch */
- br r30
diff --git a/arch/score/kernel/irq.c b/arch/score/kernel/irq.c
deleted file mode 100644
index d4196732c65e..000000000000
--- a/arch/score/kernel/irq.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * arch/score/kernel/irq.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/seq_file.h>
-
-#include <asm/io.h>
-
-/* the interrupt controller is hardcoded at this address */
-#define SCORE_PIC ((u32 __iomem __force *)0x95F50000)
-
-#define INT_PNDL 0
-#define INT_PNDH 1
-#define INT_PRIORITY_M 2
-#define INT_PRIORITY_SG0 4
-#define INT_PRIORITY_SG1 5
-#define INT_PRIORITY_SG2 6
-#define INT_PRIORITY_SG3 7
-#define INT_MASKL 8
-#define INT_MASKH 9
-
-/*
- * handles all normal device IRQs
- */
-asmlinkage void do_IRQ(int irq)
-{
- irq_enter();
- generic_handle_irq(irq);
- irq_exit();
-}
-
-static void score_mask(struct irq_data *d)
-{
- unsigned int irq_source = 63 - d->irq;
-
- if (irq_source < 32)
- __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \
- (1 << irq_source)), SCORE_PIC + INT_MASKL);
- else
- __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) | \
- (1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
-}
-
-static void score_unmask(struct irq_data *d)
-{
- unsigned int irq_source = 63 - d->irq;
-
- if (irq_source < 32)
- __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \
- ~(1 << irq_source)), SCORE_PIC + INT_MASKL);
- else
- __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \
- ~(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
-}
-
-struct irq_chip score_irq_chip = {
- .name = "Score7-level",
- .irq_mask = score_mask,
- .irq_mask_ack = score_mask,
- .irq_unmask = score_unmask,
-};
-
-/*
- * initialise the interrupt system
- */
-void __init init_IRQ(void)
-{
- int index;
- unsigned long target_addr;
-
- for (index = 0; index < NR_IRQS; ++index)
- irq_set_chip_and_handler(index, &score_irq_chip,
- handle_level_irq);
-
- for (target_addr = IRQ_VECTOR_BASE_ADDR;
- target_addr <= IRQ_VECTOR_END_ADDR;
- target_addr += IRQ_VECTOR_SIZE)
- memcpy((void *)target_addr, \
- interrupt_exception_vector, IRQ_VECTOR_SIZE);
-
- __raw_writel(0xffffffff, SCORE_PIC + INT_MASKL);
- __raw_writel(0xffffffff, SCORE_PIC + INT_MASKH);
-
- __asm__ __volatile__(
- "mtcr %0, cr3\n\t"
- : : "r" (EXCEPTION_VECTOR_BASE_ADDR | \
- VECTOR_ADDRESS_OFFSET_MODE16));
-}
diff --git a/arch/score/kernel/module.c b/arch/score/kernel/module.c
deleted file mode 100644
index 1378d99baa3d..000000000000
--- a/arch/score/kernel/module.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * arch/score/kernel/module.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/moduleloader.h>
-#include <linux/module.h>
-#include <linux/vmalloc.h>
-
-int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
- unsigned int symindex, unsigned int relindex,
- struct module *me)
-{
- Elf32_Shdr *symsec = sechdrs + symindex;
- Elf32_Shdr *relsec = sechdrs + relindex;
- Elf32_Shdr *dstsec = sechdrs + relsec->sh_info;
- Elf32_Rel *rel = (void *)relsec->sh_addr;
- unsigned int i;
-
- for (i = 0; i < relsec->sh_size / sizeof(Elf32_Rel); i++, rel++) {
- unsigned long loc;
- Elf32_Sym *sym;
- s32 r_offset;
-
- r_offset = ELF32_R_SYM(rel->r_info);
- if ((r_offset < 0) ||
- (r_offset > (symsec->sh_size / sizeof(Elf32_Sym)))) {
- printk(KERN_ERR "%s: bad relocation, section %d reloc %d\n",
- me->name, relindex, i);
- return -ENOEXEC;
- }
-
- sym = ((Elf32_Sym *)symsec->sh_addr) + r_offset;
-
- if ((rel->r_offset < 0) ||
- (rel->r_offset > dstsec->sh_size - sizeof(u32))) {
- printk(KERN_ERR "%s: out of bounds relocation, "
- "section %d reloc %d offset %d size %d\n",
- me->name, relindex, i, rel->r_offset,
- dstsec->sh_size);
- return -ENOEXEC;
- }
-
- loc = dstsec->sh_addr + rel->r_offset;
- switch (ELF32_R_TYPE(rel->r_info)) {
- case R_SCORE_NONE:
- break;
- case R_SCORE_ABS32:
- *(unsigned long *)loc += sym->st_value;
- break;
- case R_SCORE_HI16:
- break;
- case R_SCORE_LO16: {
- unsigned long hi16_offset, offset;
- unsigned long uvalue;
- unsigned long temp, temp_hi;
- temp_hi = *((unsigned long *)loc - 1);
- temp = *(unsigned long *)loc;
-
- hi16_offset = (((((temp_hi) >> 16) & 0x3) << 15) |
- ((temp_hi) & 0x7fff)) >> 1;
- offset = ((temp >> 16 & 0x03) << 15) |
- ((temp & 0x7fff) >> 1);
- offset = (hi16_offset << 16) | (offset & 0xffff);
- uvalue = sym->st_value + offset;
- hi16_offset = (uvalue >> 16) << 1;
-
- temp_hi = ((temp_hi) & (~(0x37fff))) |
- (hi16_offset & 0x7fff) |
- ((hi16_offset << 1) & 0x30000);
- *((unsigned long *)loc - 1) = temp_hi;
-
- offset = (uvalue & 0xffff) << 1;
- temp = (temp & (~(0x37fff))) | (offset & 0x7fff) |
- ((offset << 1) & 0x30000);
- *(unsigned long *)loc = temp;
- break;
- }
- case R_SCORE_24: {
- unsigned long hi16_offset, offset;
- unsigned long uvalue;
- unsigned long temp;
-
- temp = *(unsigned long *)loc;
- offset = (temp & 0x03FF7FFE);
- hi16_offset = (offset & 0xFFFF0000);
- offset = (hi16_offset | ((offset & 0xFFFF) << 1)) >> 2;
-
- uvalue = (sym->st_value + offset) >> 1;
- uvalue = uvalue & 0x00ffffff;
-
- temp = (temp & 0xfc008001) |
- ((uvalue << 2) & 0x3ff0000) |
- ((uvalue & 0x3fff) << 1);
- *(unsigned long *)loc = temp;
- break;
- }
- default:
- printk(KERN_ERR "%s: unknown relocation: %u\n",
- me->name, ELF32_R_TYPE(rel->r_info));
- return -ENOEXEC;
- }
- }
-
- return 0;
-}
-
-/* Given an address, look for it in the module exception tables. */
-const struct exception_table_entry *search_module_dbetables(unsigned long addr)
-{
- return NULL;
-}
diff --git a/arch/score/kernel/process.c b/arch/score/kernel/process.c
deleted file mode 100644
index 6e20241a1ed4..000000000000
--- a/arch/score/kernel/process.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/score/kernel/process.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/reboot.h>
-#include <linux/elfcore.h>
-#include <linux/pm.h>
-#include <linux/rcupdate.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
-
-/* If or when software machine-restart is implemented, add code here. */
-void machine_restart(char *command) {}
-
-/* If or when software machine-halt is implemented, add code here. */
-void machine_halt(void) {}
-
-/* If or when software machine-power-off is implemented, add code here. */
-void machine_power_off(void) {}
-
-void ret_from_fork(void);
-void ret_from_kernel_thread(void);
-
-void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp)
-{
- unsigned long status;
-
- /* New thread loses kernel privileges. */
- status = regs->cp0_psr & ~(KU_MASK);
- status |= KU_USER;
- regs->cp0_psr = status;
- regs->cp0_epc = pc;
- regs->regs[0] = sp;
-}
-
-/*
- * When a process does an "exec", machine state like FPU and debug
- * registers need to be reset. This is a hook function for that.
- * Currently we don't have any such state to reset, so this is empty.
- */
-void flush_thread(void) {}
-
-/*
- * set up the kernel stack and exception frames for a new process
- */
-int copy_thread(unsigned long clone_flags, unsigned long usp,
- unsigned long arg, struct task_struct *p)
-{
- struct thread_info *ti = task_thread_info(p);
- struct pt_regs *childregs = task_pt_regs(p);
- struct pt_regs *regs = current_pt_regs();
-
- p->thread.reg0 = (unsigned long) childregs;
- if (unlikely(p->flags & PF_KTHREAD)) {
- memset(childregs, 0, sizeof(struct pt_regs));
- p->thread.reg12 = usp;
- p->thread.reg13 = arg;
- p->thread.reg3 = (unsigned long) ret_from_kernel_thread;
- } else {
- *childregs = *current_pt_regs();
- childregs->regs[7] = 0; /* Clear error flag */
- childregs->regs[4] = 0; /* Child gets zero as return value */
- if (usp)
- childregs->regs[0] = usp; /* user fork */
- p->thread.reg3 = (unsigned long) ret_from_fork;
- }
-
- p->thread.cp0_psr = 0;
-
- return 0;
-}
-
-/* Fill in the fpu structure for a core dump. */
-int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
-{
- return 1;
-}
-
-unsigned long get_wchan(struct task_struct *task)
-{
- if (!task || task == current || task->state == TASK_RUNNING)
- return 0;
-
- if (!task_stack_page(task))
- return 0;
-
- return task_pt_regs(task)->cp0_epc;
-}
-
-unsigned long arch_align_stack(unsigned long sp)
-{
- return sp;
-}
diff --git a/arch/score/kernel/ptrace.c b/arch/score/kernel/ptrace.c
deleted file mode 100644
index d8455e60bce0..000000000000
--- a/arch/score/kernel/ptrace.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * arch/score/kernel/ptrace.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/elf.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/ptrace.h>
-#include <linux/regset.h>
-#include <linux/sched/task_stack.h>
-
-#include <linux/uaccess.h>
-
-/*
- * retrieve the contents of SCORE userspace general registers
- */
-static int genregs_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- const struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* skip 9 * sizeof(unsigned long) not use for pt_regs */
- ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- 0, offsetof(struct pt_regs, regs));
-
- /* r0 - r31, cel, ceh, sr0, sr1, sr2, epc, ema, psr, ecr, condition */
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- regs->regs,
- offsetof(struct pt_regs, regs),
- offsetof(struct pt_regs, cp0_condition));
-
- if (!ret)
- ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
- sizeof(struct pt_regs), -1);
-
- return ret;
-}
-
-/*
- * update the contents of the SCORE userspace general registers
- */
-static int genregs_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- struct pt_regs *regs = task_pt_regs(target);
- int ret;
-
- /* skip 9 * sizeof(unsigned long) */
- ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- 0, offsetof(struct pt_regs, regs));
-
- /* r0 - r31, cel, ceh, sr0, sr1, sr2, epc, ema, psr, ecr, condition */
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
- regs->regs,
- offsetof(struct pt_regs, regs),
- offsetof(struct pt_regs, cp0_condition));
-
- if (!ret)
- ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
- sizeof(struct pt_regs), -1);
-
- return ret;
-}
-
-/*
- * Define the register sets available on the score7 under Linux
- */
-enum score7_regset {
- REGSET_GENERAL,
-};
-
-static const struct user_regset score7_regsets[] = {
- [REGSET_GENERAL] = {
- .core_note_type = NT_PRSTATUS,
- .n = ELF_NGREG,
- .size = sizeof(long),
- .align = sizeof(long),
- .get = genregs_get,
- .set = genregs_set,
- },
-};
-
-static const struct user_regset_view user_score_native_view = {
- .name = "score7",
- .e_machine = EM_SCORE7,
- .regsets = score7_regsets,
- .n = ARRAY_SIZE(score7_regsets),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &user_score_native_view;
-}
-
-static int is_16bitinsn(unsigned long insn)
-{
- if ((insn & INSN32_MASK) == INSN32_MASK)
- return 0;
- else
- return 1;
-}
-
-int
-read_tsk_long(struct task_struct *child,
- unsigned long addr, unsigned long *res)
-{
- int copied;
-
- copied = access_process_vm(child, addr, res, sizeof(*res), FOLL_FORCE);
-
- return copied != sizeof(*res) ? -EIO : 0;
-}
-
-int
-read_tsk_short(struct task_struct *child,
- unsigned long addr, unsigned short *res)
-{
- int copied;
-
- copied = access_process_vm(child, addr, res, sizeof(*res), FOLL_FORCE);
-
- return copied != sizeof(*res) ? -EIO : 0;
-}
-
-static int
-write_tsk_short(struct task_struct *child,
- unsigned long addr, unsigned short val)
-{
- int copied;
-
- copied = access_process_vm(child, addr, &val, sizeof(val),
- FOLL_FORCE | FOLL_WRITE);
-
- return copied != sizeof(val) ? -EIO : 0;
-}
-
-static int
-write_tsk_long(struct task_struct *child,
- unsigned long addr, unsigned long val)
-{
- int copied;
-
- copied = access_process_vm(child, addr, &val, sizeof(val),
- FOLL_FORCE | FOLL_WRITE);
-
- return copied != sizeof(val) ? -EIO : 0;
-}
-
-void user_enable_single_step(struct task_struct *child)
-{
- /* far_epc is the target of branch */
- unsigned int epc, far_epc = 0;
- unsigned long epc_insn, far_epc_insn;
- int ninsn_type; /* next insn type 0=16b, 1=32b */
- unsigned int tmp, tmp2;
- struct pt_regs *regs = task_pt_regs(child);
- child->thread.single_step = 1;
- child->thread.ss_nextcnt = 1;
- epc = regs->cp0_epc;
-
- read_tsk_long(child, epc, &epc_insn);
-
- if (is_16bitinsn(epc_insn)) {
- if ((epc_insn & J16M) == J16) {
- tmp = epc_insn & 0xFFE;
- epc = (epc & 0xFFFFF000) | tmp;
- } else if ((epc_insn & B16M) == B16) {
- child->thread.ss_nextcnt = 2;
- tmp = (epc_insn & 0xFF) << 1;
- tmp = tmp << 23;
- tmp = (unsigned int)((int) tmp >> 23);
- far_epc = epc + tmp;
- epc += 2;
- } else if ((epc_insn & BR16M) == BR16) {
- child->thread.ss_nextcnt = 2;
- tmp = (epc_insn >> 4) & 0xF;
- far_epc = regs->regs[tmp];
- epc += 2;
- } else
- epc += 2;
- } else {
- if ((epc_insn & J32M) == J32) {
- tmp = epc_insn & 0x03FFFFFE;
- tmp2 = tmp & 0x7FFF;
- tmp = (((tmp >> 16) & 0x3FF) << 15) | tmp2;
- epc = (epc & 0xFFC00000) | tmp;
- } else if ((epc_insn & B32M) == B32) {
- child->thread.ss_nextcnt = 2;
- tmp = epc_insn & 0x03FFFFFE; /* discard LK bit */
- tmp2 = tmp & 0x3FF;
- tmp = (((tmp >> 16) & 0x3FF) << 10) | tmp2; /* 20bit */
- tmp = tmp << 12;
- tmp = (unsigned int)((int) tmp >> 12);
- far_epc = epc + tmp;
- epc += 4;
- } else if ((epc_insn & BR32M) == BR32) {
- child->thread.ss_nextcnt = 2;
- tmp = (epc_insn >> 16) & 0x1F;
- far_epc = regs->regs[tmp];
- epc += 4;
- } else
- epc += 4;
- }
-
- if (child->thread.ss_nextcnt == 1) {
- read_tsk_long(child, epc, &epc_insn);
-
- if (is_16bitinsn(epc_insn)) {
- write_tsk_short(child, epc, SINGLESTEP16_INSN);
- ninsn_type = 0;
- } else {
- write_tsk_long(child, epc, SINGLESTEP32_INSN);
- ninsn_type = 1;
- }
-
- if (ninsn_type == 0) { /* 16bits */
- child->thread.insn1_type = 0;
- child->thread.addr1 = epc;
- /* the insn may have 32bit data */
- child->thread.insn1 = (short)epc_insn;
- } else {
- child->thread.insn1_type = 1;
- child->thread.addr1 = epc;
- child->thread.insn1 = epc_insn;
- }
- } else {
- /* branch! have two target child->thread.ss_nextcnt=2 */
- read_tsk_long(child, epc, &epc_insn);
- read_tsk_long(child, far_epc, &far_epc_insn);
- if (is_16bitinsn(epc_insn)) {
- write_tsk_short(child, epc, SINGLESTEP16_INSN);
- ninsn_type = 0;
- } else {
- write_tsk_long(child, epc, SINGLESTEP32_INSN);
- ninsn_type = 1;
- }
-
- if (ninsn_type == 0) { /* 16bits */
- child->thread.insn1_type = 0;
- child->thread.addr1 = epc;
- /* the insn may have 32bit data */
- child->thread.insn1 = (short)epc_insn;
- } else {
- child->thread.insn1_type = 1;
- child->thread.addr1 = epc;
- child->thread.insn1 = epc_insn;
- }
-
- if (is_16bitinsn(far_epc_insn)) {
- write_tsk_short(child, far_epc, SINGLESTEP16_INSN);
- ninsn_type = 0;
- } else {
- write_tsk_long(child, far_epc, SINGLESTEP32_INSN);
- ninsn_type = 1;
- }
-
- if (ninsn_type == 0) { /* 16bits */
- child->thread.insn2_type = 0;
- child->thread.addr2 = far_epc;
- /* the insn may have 32bit data */
- child->thread.insn2 = (short)far_epc_insn;
- } else {
- child->thread.insn2_type = 1;
- child->thread.addr2 = far_epc;
- child->thread.insn2 = far_epc_insn;
- }
- }
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- if (child->thread.insn1_type == 0)
- write_tsk_short(child, child->thread.addr1,
- child->thread.insn1);
-
- if (child->thread.insn1_type == 1)
- write_tsk_long(child, child->thread.addr1,
- child->thread.insn1);
-
- if (child->thread.ss_nextcnt == 2) { /* branch */
- if (child->thread.insn1_type == 0)
- write_tsk_short(child, child->thread.addr1,
- child->thread.insn1);
- if (child->thread.insn1_type == 1)
- write_tsk_long(child, child->thread.addr1,
- child->thread.insn1);
- if (child->thread.insn2_type == 0)
- write_tsk_short(child, child->thread.addr2,
- child->thread.insn2);
- if (child->thread.insn2_type == 1)
- write_tsk_long(child, child->thread.addr2,
- child->thread.insn2);
- }
-
- child->thread.single_step = 0;
- child->thread.ss_nextcnt = 0;
-}
-
-void ptrace_disable(struct task_struct *child)
-{
- user_disable_single_step(child);
-}
-
-long
-arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- int ret;
- unsigned long __user *datap = (void __user *)data;
-
- switch (request) {
- case PTRACE_GETREGS:
- ret = copy_regset_to_user(child, &user_score_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
- break;
-
- case PTRACE_SETREGS:
- ret = copy_regset_from_user(child, &user_score_native_view,
- REGSET_GENERAL,
- 0, sizeof(struct pt_regs),
- datap);
- break;
-
- default:
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-/*
- * Notification of system call entry/exit
- * - triggered by current->work.syscall_trace
- */
-asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
-{
- if (!(current->ptrace & PT_PTRACED))
- return;
-
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return;
-
- /* The 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery. */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
- 0x80 : 0));
-
- /*
- * this isn't the same as continuing with a signal, but it will do
- * for normal use. strace only continues with a signal if the
- * stopping signal is not SIGTRAP. -brl
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
-}
diff --git a/arch/score/kernel/setup.c b/arch/score/kernel/setup.c
deleted file mode 100644
index 627416bbd0b1..000000000000
--- a/arch/score/kernel/setup.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * arch/score/kernel/setup.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/bootmem.h>
-#include <linux/initrd.h>
-#include <linux/ioport.h>
-#include <linux/memblock.h>
-#include <linux/mm.h>
-#include <linux/seq_file.h>
-#include <linux/screen_info.h>
-
-#include <asm-generic/sections.h>
-#include <asm/setup.h>
-
-struct screen_info screen_info;
-unsigned long kernelsp;
-
-static char command_line[COMMAND_LINE_SIZE];
-static struct resource code_resource = { .name = "Kernel code",};
-static struct resource data_resource = { .name = "Kernel data",};
-
-static void __init bootmem_init(void)
-{
- unsigned long start_pfn, bootmap_size;
- unsigned long size = initrd_end - initrd_start;
-
- start_pfn = PFN_UP(__pa(&_end));
-
- min_low_pfn = PFN_UP(MEMORY_START);
- max_low_pfn = PFN_UP(MEMORY_START + MEMORY_SIZE);
- max_mapnr = max_low_pfn - min_low_pfn;
-
- /* Initialize the boot-time allocator with low memory only. */
- bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
- min_low_pfn, max_low_pfn);
- memblock_add_node(PFN_PHYS(min_low_pfn),
- PFN_PHYS(max_low_pfn - min_low_pfn), 0);
-
- free_bootmem(PFN_PHYS(start_pfn),
- (max_low_pfn - start_pfn) << PAGE_SHIFT);
- memory_present(0, start_pfn, max_low_pfn);
-
- /* Reserve space for the bootmem bitmap. */
- reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size, BOOTMEM_DEFAULT);
-
- if (size == 0) {
- printk(KERN_INFO "Initrd not found or empty");
- goto disable;
- }
-
- if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) {
- printk(KERN_ERR "Initrd extends beyond end of memory");
- goto disable;
- }
-
- /* Reserve space for the initrd bitmap. */
- reserve_bootmem(__pa(initrd_start), size, BOOTMEM_DEFAULT);
- initrd_below_start_ok = 1;
-
- pr_info("Initial ramdisk at: 0x%lx (%lu bytes)\n",
- initrd_start, size);
- return;
-disable:
- printk(KERN_CONT " - disabling initrd\n");
- initrd_start = 0;
- initrd_end = 0;
-}
-
-static void __init resource_init(void)
-{
- struct resource *res;
-
- code_resource.start = __pa(&_text);
- code_resource.end = __pa(&_etext) - 1;
- data_resource.start = __pa(&_etext);
- data_resource.end = __pa(&_edata) - 1;
-
- res = alloc_bootmem(sizeof(struct resource));
- res->name = "System RAM";
- res->start = MEMORY_START;
- res->end = MEMORY_START + MEMORY_SIZE - 1;
- res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
- request_resource(&iomem_resource, res);
-
- request_resource(res, &code_resource);
- request_resource(res, &data_resource);
-}
-
-void __init setup_arch(char **cmdline_p)
-{
- randomize_va_space = 0;
- *cmdline_p = command_line;
-
- cpu_cache_init();
- tlb_init();
- bootmem_init();
- paging_init();
- resource_init();
-}
-
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- unsigned long n = (unsigned long) v - 1;
-
- seq_printf(m, "processor\t\t: %ld\n\n", n);
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- unsigned long i = *pos;
-
- return i < 1 ? (void *) (i + 1) : NULL;
-}
-
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-static int __init topology_init(void)
-{
- return 0;
-}
-
-subsys_initcall(topology_init);
diff --git a/arch/score/kernel/signal.c b/arch/score/kernel/signal.c
deleted file mode 100644
index e381c8c4ff65..000000000000
--- a/arch/score/kernel/signal.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * arch/score/kernel/signal.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/errno.h>
-#include <linux/signal.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/uaccess.h>
-#include <linux/tracehook.h>
-
-#include <asm/cacheflush.h>
-#include <asm/syscalls.h>
-#include <asm/ucontext.h>
-
-struct rt_sigframe {
- u32 rs_ass[4]; /* argument save space */
- u32 rs_code[2]; /* signal trampoline */
- struct siginfo rs_info;
- struct ucontext rs_uc;
-};
-
-static int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
-{
- int err = 0;
- unsigned long reg;
-
- reg = regs->cp0_epc; err |= __put_user(reg, &sc->sc_pc);
- err |= __put_user(regs->cp0_psr, &sc->sc_psr);
- err |= __put_user(regs->cp0_condition, &sc->sc_condition);
-
-
-#define save_gp_reg(i) { \
- reg = regs->regs[i]; \
- err |= __put_user(reg, &sc->sc_regs[i]); \
-} while (0)
- save_gp_reg(0); save_gp_reg(1); save_gp_reg(2);
- save_gp_reg(3); save_gp_reg(4); save_gp_reg(5);
- save_gp_reg(6); save_gp_reg(7); save_gp_reg(8);
- save_gp_reg(9); save_gp_reg(10); save_gp_reg(11);
- save_gp_reg(12); save_gp_reg(13); save_gp_reg(14);
- save_gp_reg(15); save_gp_reg(16); save_gp_reg(17);
- save_gp_reg(18); save_gp_reg(19); save_gp_reg(20);
- save_gp_reg(21); save_gp_reg(22); save_gp_reg(23);
- save_gp_reg(24); save_gp_reg(25); save_gp_reg(26);
- save_gp_reg(27); save_gp_reg(28); save_gp_reg(29);
-#undef save_gp_reg
-
- reg = regs->ceh; err |= __put_user(reg, &sc->sc_mdceh);
- reg = regs->cel; err |= __put_user(reg, &sc->sc_mdcel);
- err |= __put_user(regs->cp0_ecr, &sc->sc_ecr);
- err |= __put_user(regs->cp0_ema, &sc->sc_ema);
-
- return err;
-}
-
-static int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
-{
- int err = 0;
- u32 reg;
-
- err |= __get_user(regs->cp0_epc, &sc->sc_pc);
- err |= __get_user(regs->cp0_condition, &sc->sc_condition);
-
- err |= __get_user(reg, &sc->sc_mdceh);
- regs->ceh = (int) reg;
- err |= __get_user(reg, &sc->sc_mdcel);
- regs->cel = (int) reg;
-
- err |= __get_user(reg, &sc->sc_psr);
- regs->cp0_psr = (int) reg;
- err |= __get_user(reg, &sc->sc_ecr);
- regs->cp0_ecr = (int) reg;
- err |= __get_user(reg, &sc->sc_ema);
- regs->cp0_ema = (int) reg;
-
-#define restore_gp_reg(i) do { \
- err |= __get_user(reg, &sc->sc_regs[i]); \
- regs->regs[i] = reg; \
-} while (0)
- restore_gp_reg(0); restore_gp_reg(1); restore_gp_reg(2);
- restore_gp_reg(3); restore_gp_reg(4); restore_gp_reg(5);
- restore_gp_reg(6); restore_gp_reg(7); restore_gp_reg(8);
- restore_gp_reg(9); restore_gp_reg(10); restore_gp_reg(11);
- restore_gp_reg(12); restore_gp_reg(13); restore_gp_reg(14);
- restore_gp_reg(15); restore_gp_reg(16); restore_gp_reg(17);
- restore_gp_reg(18); restore_gp_reg(19); restore_gp_reg(20);
- restore_gp_reg(21); restore_gp_reg(22); restore_gp_reg(23);
- restore_gp_reg(24); restore_gp_reg(25); restore_gp_reg(26);
- restore_gp_reg(27); restore_gp_reg(28); restore_gp_reg(29);
-#undef restore_gp_reg
-
- return err;
-}
-
-/*
- * Determine which stack to use..
- */
-static void __user *get_sigframe(struct k_sigaction *ka,
- struct pt_regs *regs, size_t frame_size)
-{
- unsigned long sp;
-
- /* Default to using normal stack */
- sp = regs->regs[0];
- sp -= 32;
-
- /* This is the X/Open sanctioned signal stack switching. */
- if ((ka->sa.sa_flags & SA_ONSTACK) && (!on_sig_stack(sp)))
- sp = current->sas_ss_sp + current->sas_ss_size;
-
- return (void __user*)((sp - frame_size) & ~7);
-}
-
-asmlinkage long
-score_rt_sigreturn(struct pt_regs *regs)
-{
- struct rt_sigframe __user *frame;
- sigset_t set;
- int sig;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- frame = (struct rt_sigframe __user *) regs->regs[0];
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->rs_uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- sig = restore_sigcontext(regs, &frame->rs_uc.uc_mcontext);
- if (sig < 0)
- goto badframe;
- else if (sig)
- force_sig(sig, current);
-
- if (restore_altstack(&frame->rs_uc.uc_stack))
- goto badframe;
- regs->is_syscall = 0;
-
- __asm__ __volatile__(
- "mv\tr0, %0\n\t"
- "la\tr8, syscall_exit\n\t"
- "br\tr8\n\t"
- : : "r" (regs) : "r8");
-
-badframe:
- force_sig(SIGSEGV, current);
-
- return 0;
-}
-
-static int setup_rt_frame(struct ksignal *ksig, struct pt_regs *regs,
- sigset_t *set)
-{
- struct rt_sigframe __user *frame;
- int err = 0;
-
- frame = get_sigframe(&ksig->ka, regs, sizeof(*frame));
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- return -EFAULT;
-
- /*
- * Set up the return code ...
- *
- * li v0, __NR_rt_sigreturn
- * syscall
- */
- err |= __put_user(0x87788000 + __NR_rt_sigreturn*2,
- frame->rs_code + 0);
- err |= __put_user(0x80008002, frame->rs_code + 1);
- flush_cache_sigtramp((unsigned long) frame->rs_code);
-
- err |= copy_siginfo_to_user(&frame->rs_info, &ksig->info);
- err |= __put_user(0, &frame->rs_uc.uc_flags);
- err |= __put_user(NULL, &frame->rs_uc.uc_link);
- err |= __save_altstack(&frame->rs_uc.uc_stack, regs->regs[0]);
- err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
- err |= __copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set));
-
- if (err)
- return -EFAULT;
-
- regs->regs[0] = (unsigned long) frame;
- regs->regs[3] = (unsigned long) frame->rs_code;
- regs->regs[4] = ksig->sig;
- regs->regs[5] = (unsigned long) &frame->rs_info;
- regs->regs[6] = (unsigned long) &frame->rs_uc;
- regs->regs[29] = (unsigned long) ksig->ka.sa.sa_handler;
- regs->cp0_epc = (unsigned long) ksig->ka.sa.sa_handler;
-
- return 0;
-}
-
-static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- int ret;
-
- if (regs->is_syscall) {
- switch (regs->regs[4]) {
- case ERESTART_RESTARTBLOCK:
- case ERESTARTNOHAND:
- regs->regs[4] = EINTR;
- break;
- case ERESTARTSYS:
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->regs[4] = EINTR;
- break;
- }
- case ERESTARTNOINTR:
- regs->regs[4] = regs->orig_r4;
- regs->regs[7] = regs->orig_r7;
- regs->cp0_epc -= 8;
- }
-
- regs->is_syscall = 0;
- }
-
- /*
- * Set up the stack frame
- */
- ret = setup_rt_frame(ksig, regs, sigmask_to_save());
-
- signal_setup_done(ret, ksig, 0);
-}
-
-static void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- /*
- * We want the common case to go fast, which is why we may in certain
- * cases get here from kernel mode. Just return without doing anything
- * if so.
- */
- if (!user_mode(regs))
- return;
-
- if (get_signal(&ksig)) {
- /* Actually deliver the signal. */
- handle_signal(&ksig, regs);
- return;
- }
-
- if (regs->is_syscall) {
- if (regs->regs[4] == ERESTARTNOHAND ||
- regs->regs[4] == ERESTARTSYS ||
- regs->regs[4] == ERESTARTNOINTR) {
- regs->regs[4] = regs->orig_r4;
- regs->regs[7] = regs->orig_r7;
- regs->cp0_epc -= 8;
- }
-
- if (regs->regs[4] == ERESTART_RESTARTBLOCK) {
- regs->regs[27] = __NR_restart_syscall;
- regs->regs[4] = regs->orig_r4;
- regs->regs[7] = regs->orig_r7;
- regs->cp0_epc -= 8;
- }
-
- regs->is_syscall = 0; /* Don't deal with this again. */
- }
-
- /*
- * If there's no signal to deliver, we just put the saved sigmask
- * back
- */
- restore_saved_sigmask();
-}
-
-/*
- * notification of userspace execution resumption
- * - triggered by the TIF_WORK_MASK flags
- */
-asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
- __u32 thread_info_flags)
-{
- /* deal with pending signal delivery */
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal(regs);
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-}
diff --git a/arch/score/kernel/sys_call_table.c b/arch/score/kernel/sys_call_table.c
deleted file mode 100644
index 9e6ae793e690..000000000000
--- a/arch/score/kernel/sys_call_table.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/syscalls.h>
-#include <linux/signal.h>
-#include <linux/unistd.h>
-
-#include <asm/syscalls.h>
-
-#undef __SYSCALL
-#define __SYSCALL(nr, call) [nr] = (call),
-
-void *sys_call_table[__NR_syscalls] = {
-#include <asm/unistd.h>
-};
diff --git a/arch/score/kernel/sys_score.c b/arch/score/kernel/sys_score.c
deleted file mode 100644
index 47c20ba46167..000000000000
--- a/arch/score/kernel/sys_score.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/score/kernel/syscall.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/file.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/mman.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/unistd.h>
-#include <linux/syscalls.h>
-#include <asm/syscalls.h>
-
-asmlinkage long
-sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
- unsigned long flags, unsigned long fd, unsigned long pgoff)
-{
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
-}
-
-asmlinkage long
-sys_mmap(unsigned long addr, unsigned long len, unsigned long prot,
- unsigned long flags, unsigned long fd, off_t offset)
-{
- if (unlikely(offset & ~PAGE_MASK))
- return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
-}
diff --git a/arch/score/kernel/time.c b/arch/score/kernel/time.c
deleted file mode 100644
index 29aafc741f69..000000000000
--- a/arch/score/kernel/time.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * arch/score/kernel/time.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-
-#include <asm/scoreregs.h>
-
-static irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evdev = dev_id;
-
- /* clear timer interrupt flag */
- outl(1, P_TIMER0_CPP_REG);
- evdev->event_handler(evdev);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction timer_irq = {
- .handler = timer_interrupt,
- .flags = IRQF_TIMER,
- .name = "timer",
-};
-
-static int score_timer_set_next_event(unsigned long delta,
- struct clock_event_device *evdev)
-{
- outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL);
- outl(delta, P_TIMER0_PRELOAD);
- outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL);
-
- return 0;
-}
-
-static int score_timer_set_periodic(struct clock_event_device *evt)
-{
- outl((TMR_M_PERIODIC | TMR_IE_ENABLE), P_TIMER0_CTRL);
- outl(SYSTEM_CLOCK / HZ, P_TIMER0_PRELOAD);
- outl(inl(P_TIMER0_CTRL) | TMR_ENABLE, P_TIMER0_CTRL);
- return 0;
-}
-
-static struct clock_event_device score_clockevent = {
- .name = "score_clockevent",
- .features = CLOCK_EVT_FEAT_PERIODIC,
- .shift = 16,
- .set_next_event = score_timer_set_next_event,
- .set_state_periodic = score_timer_set_periodic,
-};
-
-void __init time_init(void)
-{
- timer_irq.dev_id = &score_clockevent;
- setup_irq(IRQ_TIMER , &timer_irq);
-
- /* setup COMPARE clockevent */
- score_clockevent.mult = div_sc(SYSTEM_CLOCK, NSEC_PER_SEC,
- score_clockevent.shift);
- score_clockevent.max_delta_ns = clockevent_delta2ns((u32)~0,
- &score_clockevent);
- score_clockevent.max_delta_ticks = (u32)~0;
- score_clockevent.min_delta_ns = clockevent_delta2ns(50,
- &score_clockevent) + 1;
- score_clockevent.min_delta_ticks = 50;
- score_clockevent.cpumask = cpumask_of(0);
- clockevents_register_device(&score_clockevent);
-}
diff --git a/arch/score/kernel/traps.c b/arch/score/kernel/traps.c
deleted file mode 100644
index 12daf45369b4..000000000000
--- a/arch/score/kernel/traps.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * arch/score/kernel/traps.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/extable.h>
-#include <linux/ptrace.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/debug.h>
-#include <linux/mm_types.h>
-
-#include <asm/cacheflush.h>
-#include <asm/irq.h>
-#include <asm/irq_regs.h>
-#include <linux/uaccess.h>
-
-unsigned long exception_handlers[32];
-
-/*
- * The architecture-independent show_stack generator
- */
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
- int i;
- long stackdata;
-
- sp = sp ? sp : (unsigned long *)&sp;
-
- printk(KERN_NOTICE "Stack: ");
- i = 1;
- while ((long) sp & (PAGE_SIZE - 1)) {
- if (i && ((i % 8) == 0))
- printk(KERN_NOTICE "\n");
- if (i > 40) {
- printk(KERN_NOTICE " ...");
- break;
- }
-
- if (__get_user(stackdata, sp++)) {
- printk(KERN_NOTICE " (Bad stack address)");
- break;
- }
-
- printk(KERN_NOTICE " %08lx", stackdata);
- i++;
- }
- printk(KERN_NOTICE "\n");
-}
-
-static void show_trace(long *sp)
-{
- int i;
- long addr;
-
- sp = sp ? sp : (long *) &sp;
-
- printk(KERN_NOTICE "Call Trace: ");
- i = 1;
- while ((long) sp & (PAGE_SIZE - 1)) {
- if (__get_user(addr, sp++)) {
- if (i && ((i % 6) == 0))
- printk(KERN_NOTICE "\n");
- printk(KERN_NOTICE " (Bad stack address)\n");
- break;
- }
-
- if (kernel_text_address(addr)) {
- if (i && ((i % 6) == 0))
- printk(KERN_NOTICE "\n");
- if (i > 40) {
- printk(KERN_NOTICE " ...");
- break;
- }
-
- printk(KERN_NOTICE " [<%08lx>]", addr);
- i++;
- }
- }
- printk(KERN_NOTICE "\n");
-}
-
-static void show_code(unsigned int *pc)
-{
- long i;
-
- printk(KERN_NOTICE "\nCode:");
-
- for (i = -3; i < 6; i++) {
- unsigned long insn;
- if (__get_user(insn, pc + i)) {
- printk(KERN_NOTICE " (Bad address in epc)\n");
- break;
- }
- printk(KERN_NOTICE "%c%08lx%c", (i ? ' ' : '<'),
- insn, (i ? ' ' : '>'));
- }
-}
-
-/*
- * FIXME: really the generic show_regs should take a const pointer argument.
- */
-void show_regs(struct pt_regs *regs)
-{
- show_regs_print_info(KERN_DEFAULT);
-
- printk("r0 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- regs->regs[0], regs->regs[1], regs->regs[2], regs->regs[3],
- regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
- printk("r8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11],
- regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
- printk("r16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19],
- regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
- printk("r24: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
- regs->regs[24], regs->regs[25], regs->regs[26], regs->regs[27],
- regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
-
- printk("CEH : %08lx\n", regs->ceh);
- printk("CEL : %08lx\n", regs->cel);
-
- printk("EMA:%08lx, epc:%08lx %s\nPSR: %08lx\nECR:%08lx\nCondition : %08lx\n",
- regs->cp0_ema, regs->cp0_epc, print_tainted(), regs->cp0_psr,
- regs->cp0_ecr, regs->cp0_condition);
-}
-
-static void show_registers(struct pt_regs *regs)
-{
- show_regs(regs);
- printk(KERN_NOTICE "Process %s (pid: %d, stackpage=%08lx)\n",
- current->comm, current->pid, (unsigned long) current);
- show_stack(current_thread_info()->task, (long *) regs->regs[0]);
- show_trace((long *) regs->regs[0]);
- show_code((unsigned int *) regs->cp0_epc);
- printk(KERN_NOTICE "\n");
-}
-
-void __die(const char *str, struct pt_regs *regs, const char *file,
- const char *func, unsigned long line)
-{
- console_verbose();
- printk("%s", str);
- if (file && func)
- printk(" in %s:%s, line %ld", file, func, line);
- printk(":\n");
- show_registers(regs);
- do_exit(SIGSEGV);
-}
-
-void __die_if_kernel(const char *str, struct pt_regs *regs,
- const char *file, const char *func, unsigned long line)
-{
- if (!user_mode(regs))
- __die(str, regs, file, func, line);
-}
-
-asmlinkage void do_adelinsn(struct pt_regs *regs)
-{
- printk("do_ADE-linsn:ema:0x%08lx:epc:0x%08lx\n",
- regs->cp0_ema, regs->cp0_epc);
- die_if_kernel("do_ade execution Exception\n", regs);
- force_sig(SIGBUS, current);
-}
-
-asmlinkage void do_adedata(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
- fixup = search_exception_tables(regs->cp0_epc);
- if (fixup) {
- regs->cp0_epc = fixup->fixup;
- return;
- }
- printk("do_ADE-data:ema:0x%08lx:epc:0x%08lx\n",
- regs->cp0_ema, regs->cp0_epc);
- die_if_kernel("do_ade execution Exception\n", regs);
- force_sig(SIGBUS, current);
-}
-
-asmlinkage void do_pel(struct pt_regs *regs)
-{
- die_if_kernel("do_pel execution Exception", regs);
- force_sig(SIGFPE, current);
-}
-
-asmlinkage void do_cee(struct pt_regs *regs)
-{
- die_if_kernel("do_cee execution Exception", regs);
- force_sig(SIGFPE, current);
-}
-
-asmlinkage void do_cpe(struct pt_regs *regs)
-{
- die_if_kernel("do_cpe execution Exception", regs);
- force_sig(SIGFPE, current);
-}
-
-asmlinkage void do_be(struct pt_regs *regs)
-{
- die_if_kernel("do_be execution Exception", regs);
- force_sig(SIGBUS, current);
-}
-
-asmlinkage void do_ov(struct pt_regs *regs)
-{
- siginfo_t info;
-
- die_if_kernel("do_ov execution Exception", regs);
-
- info.si_code = FPE_INTOVF;
- info.si_signo = SIGFPE;
- info.si_errno = 0;
- info.si_addr = (void *)regs->cp0_epc;
- force_sig_info(SIGFPE, &info, current);
-}
-
-asmlinkage void do_tr(struct pt_regs *regs)
-{
- die_if_kernel("do_tr execution Exception", regs);
- force_sig(SIGTRAP, current);
-}
-
-asmlinkage void do_ri(struct pt_regs *regs)
-{
- unsigned long epc_insn;
- unsigned long epc = regs->cp0_epc;
-
- read_tsk_long(current, epc, &epc_insn);
- if (current->thread.single_step == 1) {
- if ((epc == current->thread.addr1) ||
- (epc == current->thread.addr2)) {
- user_disable_single_step(current);
- force_sig(SIGTRAP, current);
- return;
- } else
- BUG();
- } else if ((epc_insn == BREAKPOINT32_INSN) ||
- ((epc_insn & 0x0000FFFF) == 0x7002) ||
- ((epc_insn & 0xFFFF0000) == 0x70020000)) {
- force_sig(SIGTRAP, current);
- return;
- } else {
- die_if_kernel("do_ri execution Exception", regs);
- force_sig(SIGILL, current);
- }
-}
-
-asmlinkage void do_ccu(struct pt_regs *regs)
-{
- die_if_kernel("do_ccu execution Exception", regs);
- force_sig(SIGILL, current);
-}
-
-asmlinkage void do_reserved(struct pt_regs *regs)
-{
- /*
- * Game over - no way to handle this if it ever occurs. Most probably
- * caused by a new unknown cpu type or after another deadly
- * hard/software error.
- */
- die_if_kernel("do_reserved execution Exception", regs);
- show_regs(regs);
- panic("Caught reserved exception - should not happen.");
-}
-
-/*
- * NMI exception handler.
- */
-void nmi_exception_handler(struct pt_regs *regs)
-{
- die_if_kernel("nmi_exception_handler execution Exception", regs);
- die("NMI", regs);
-}
-
-/* Install CPU exception handler */
-void *set_except_vector(int n, void *addr)
-{
- unsigned long handler = (unsigned long) addr;
- unsigned long old_handler = exception_handlers[n];
-
- exception_handlers[n] = handler;
- return (void *)old_handler;
-}
-
-void __init trap_init(void)
-{
- int i;
-
- pgd_current = (unsigned long)init_mm.pgd;
- /* DEBUG EXCEPTION */
- memcpy((void *)DEBUG_VECTOR_BASE_ADDR,
- &debug_exception_vector, DEBUG_VECTOR_SIZE);
- /* NMI EXCEPTION */
- memcpy((void *)GENERAL_VECTOR_BASE_ADDR,
- &general_exception_vector, GENERAL_VECTOR_SIZE);
-
- /*
- * Initialise exception handlers
- */
- for (i = 0; i <= 31; i++)
- set_except_vector(i, handle_reserved);
-
- set_except_vector(1, handle_nmi);
- set_except_vector(2, handle_adelinsn);
- set_except_vector(3, handle_tlb_refill);
- set_except_vector(4, handle_tlb_invaild);
- set_except_vector(5, handle_ibe);
- set_except_vector(6, handle_pel);
- set_except_vector(7, handle_sys);
- set_except_vector(8, handle_ccu);
- set_except_vector(9, handle_ri);
- set_except_vector(10, handle_tr);
- set_except_vector(11, handle_adedata);
- set_except_vector(12, handle_adedata);
- set_except_vector(13, handle_tlb_refill);
- set_except_vector(14, handle_tlb_invaild);
- set_except_vector(15, handle_mod);
- set_except_vector(16, handle_cee);
- set_except_vector(17, handle_cpe);
- set_except_vector(18, handle_dbe);
- flush_icache_range(DEBUG_VECTOR_BASE_ADDR, IRQ_VECTOR_BASE_ADDR);
-
- mmgrab(&init_mm);
- current->active_mm = &init_mm;
- cpu_cache_init();
-}
diff --git a/arch/score/kernel/vmlinux.lds.S b/arch/score/kernel/vmlinux.lds.S
deleted file mode 100644
index 4117890b1db1..000000000000
--- a/arch/score/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * arch/score/kernel/vmlinux.lds.S
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/thread_info.h>
-#include <asm/page.h>
-
-OUTPUT_ARCH(score)
-ENTRY(_stext)
-
-jiffies = jiffies_64;
-
-SECTIONS
-{
- . = CONFIG_MEMORY_START + 0x2000;
- /* read-only */
- .text : {
- _text = .; /* Text and read-only data */
- TEXT_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- KPROBES_TEXT
- *(.text.*)
- *(.fixup)
- . = ALIGN (4) ;
- _etext = .; /* End of text section */
- }
-
- . = ALIGN(16);
- _sdata = .; /* Start of data section */
- RODATA
-
- EXCEPTION_TABLE(16)
-
- RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE)
-
- /* We want the small data sections together, so single-instruction offsets
- can access them all, and initialized data all before uninitialized, so
- we can shorten the on-disk segment size. */
- . = ALIGN(8);
- .sdata : {
- *(.sdata)
- }
- _edata = .; /* End of data section */
-
- /* will be freed after init */
- . = ALIGN(PAGE_SIZE); /* Init code and data */
- __init_begin = .;
-
- INIT_TEXT_SECTION(PAGE_SIZE)
- INIT_DATA_SECTION(16)
-
- /* .exit.text is discarded at runtime, not link time, to deal with
- * references from .rodata
- */
- .exit.text : {
- EXIT_TEXT
- }
- .exit.data : {
- EXIT_DATA
- }
- . = ALIGN(PAGE_SIZE);
- __init_end = .;
- /* freed after init ends here */
-
- BSS_SECTION(0, 0, 0)
- _end = .;
-}
diff --git a/arch/score/lib/Makefile b/arch/score/lib/Makefile
deleted file mode 100644
index 553e30e81faf..000000000000
--- a/arch/score/lib/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for SCORE-specific library files..
-#
-
-lib-y += string.o checksum.o checksum_copy.o
-
-# libgcc-style stuff needed in the kernel
-obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/score/lib/ashldi3.c b/arch/score/lib/ashldi3.c
deleted file mode 100644
index 15691a910431..000000000000
--- a/arch/score/lib/ashldi3.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/score/lib/ashldi3.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include "libgcc.h"
-
-long long __ashldi3(long long u, word_type b)
-{
- DWunion uu, w;
- word_type bm;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
- bm = 32 - b;
-
- if (bm <= 0) {
- w.s.low = 0;
- w.s.high = (unsigned int) uu.s.low << -bm;
- } else {
- const unsigned int carries = (unsigned int) uu.s.low >> bm;
-
- w.s.low = (unsigned int) uu.s.low << b;
- w.s.high = ((unsigned int) uu.s.high << b) | carries;
- }
-
- return w.ll;
-}
-EXPORT_SYMBOL(__ashldi3);
diff --git a/arch/score/lib/ashrdi3.c b/arch/score/lib/ashrdi3.c
deleted file mode 100644
index d9814a5d8d30..000000000000
--- a/arch/score/lib/ashrdi3.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * arch/score/lib/ashrdi3.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include "libgcc.h"
-
-long long __ashrdi3(long long u, word_type b)
-{
- DWunion uu, w;
- word_type bm;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
- bm = 32 - b;
-
- if (bm <= 0) {
- /* w.s.high = 1..1 or 0..0 */
- w.s.high =
- uu.s.high >> 31;
- w.s.low = uu.s.high >> -bm;
- } else {
- const unsigned int carries = (unsigned int) uu.s.high << bm;
-
- w.s.high = uu.s.high >> b;
- w.s.low = ((unsigned int) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
-EXPORT_SYMBOL(__ashrdi3);
diff --git a/arch/score/lib/checksum.S b/arch/score/lib/checksum.S
deleted file mode 100644
index 1141f2b4a501..000000000000
--- a/arch/score/lib/checksum.S
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * arch/score/lib/csum_partial.S
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#include <linux/linkage.h>
-
-#define ADDC(sum,reg) \
- add sum, sum, reg; \
- cmp.c reg, sum; \
- bleu 9f; \
- addi sum, 0x1; \
-9:
-
-#define CSUM_BIGCHUNK(src, offset, sum) \
- lw r8, [src, offset + 0x00]; \
- lw r9, [src, offset + 0x04]; \
- lw r10, [src, offset + 0x08]; \
- lw r11, [src, offset + 0x0c]; \
- ADDC(sum, r8); \
- ADDC(sum, r9); \
- ADDC(sum, r10); \
- ADDC(sum, r11); \
- lw r8, [src, offset + 0x10]; \
- lw r9, [src, offset + 0x14]; \
- lw r10, [src, offset + 0x18]; \
- lw r11, [src, offset + 0x1c]; \
- ADDC(sum, r8); \
- ADDC(sum, r9); \
- ADDC(sum, r10); \
- ADDC(sum, r11); \
-
-#define src r4
-#define dest r5
-#define sum r27
-
- .text
-/* unknown src alignment and < 8 bytes to go */
-small_csumcpy:
- mv r5, r10
- ldi r9, 0x0
- cmpi.c r25, 0x1
- beq pass_small_set_t7 /*already set, jump to pass_small_set_t7*/
- andri.c r25,r4 , 0x1 /*Is src 2 bytes aligned?*/
-
-pass_small_set_t7:
- beq aligned
- cmpi.c r5, 0x0
- beq fold
- lbu r9, [src]
- slli r9,r9, 0x8 /*Little endian*/
- ADDC(sum, r9)
- addi src, 0x1
- subi.c r5, 0x1
-
- /*len still a full word */
-aligned:
- andri.c r8, r5, 0x4 /*Len >= 4?*/
- beq len_less_4bytes
-
- /* Still a full word (4byte) to go,and the src is word aligned.*/
- andri.c r8, src, 0x3 /*src is 4bytes aligned, so use LW!!*/
- beq four_byte_aligned
- lhu r9, [src]
- addi src, 2
- ADDC(sum, r9)
- lhu r9, [src]
- addi src, 2
- ADDC(sum, r9)
- b len_less_4bytes
-
-four_byte_aligned: /* Len >=4 and four byte aligned */
- lw r9, [src]
- addi src, 4
- ADDC(sum, r9)
-
-len_less_4bytes: /* 2 byte aligned aligned and length<4B */
- andri.c r8, r5, 0x2
- beq len_less_2bytes
- lhu r9, [src]
- addi src, 0x2 /* src+=2 */
- ADDC(sum, r9)
-
-len_less_2bytes: /* len = 1 */
- andri.c r8, r5, 0x1
- beq fold /* less than 2 and not equal 1--> len=0 -> fold */
- lbu r9, [src]
-
-fold_ADDC:
- ADDC(sum, r9)
-fold:
- /* fold checksum */
- slli r26, sum, 16
- add sum, sum, r26
- cmp.c r26, sum
- srli sum, sum, 16
- bleu 1f /* if r26<=sum */
- addi sum, 0x1 /* r26>sum */
-1:
- /* odd buffer alignment? r25 was set in csum_partial */
- cmpi.c r25, 0x0
- beq 1f
- slli r26, sum, 8
- srli sum, sum, 8
- or sum, sum, r26
- andi sum, 0xffff
-1:
- .set optimize
- /* Add the passed partial csum. */
- ADDC(sum, r6)
- mv r4, sum
- br r3
- .set volatile
-
- .align 5
-ENTRY(csum_partial)
- ldi sum, 0
- ldi r25, 0
- mv r10, r5
- cmpi.c r5, 0x8
- blt small_csumcpy /* < 8(signed) bytes to copy */
- cmpi.c r5, 0x0
- beq out
- andri.c r25, src, 0x1 /* odd buffer? */
-
- beq word_align
-hword_align: /* 1 byte */
- lbu r8, [src]
- subi r5, 0x1
- slli r8, r8, 8
- ADDC(sum, r8)
- addi src, 0x1
-
-word_align: /* 2 bytes */
- andri.c r8, src, 0x2 /* 4bytes(dword)_aligned? */
- beq dword_align /* not, maybe dword_align */
- lhu r8, [src]
- subi r5, 0x2
- ADDC(sum, r8)
- addi src, 0x2
-
-dword_align: /* 4bytes */
- mv r26, r5 /* maybe useless when len >=56 */
- ldi r8, 56
- cmp.c r8, r5
- bgtu do_end_words /* if a1(len)<t0(56) ,unsigned */
- andri.c r26, src, 0x4
- beq qword_align
- lw r8, [src]
- subi r5, 0x4
- ADDC(sum, r8)
- addi src, 0x4
-
-qword_align: /* 8 bytes */
- andri.c r26, src, 0x8
- beq oword_align
- lw r8, [src, 0x0]
- lw r9, [src, 0x4]
- subi r5, 0x8 /* len-=0x8 */
- ADDC(sum, r8)
- ADDC(sum, r9)
- addi src, 0x8
-
-oword_align: /* 16bytes */
- andri.c r26, src, 0x10
- beq begin_movement
- lw r10, [src, 0x08]
- lw r11, [src, 0x0c]
- lw r8, [src, 0x00]
- lw r9, [src, 0x04]
- ADDC(sum, r10)
- ADDC(sum, r11)
- ADDC(sum, r8)
- ADDC(sum, r9)
- subi r5, 0x10
- addi src, 0x10
-
-begin_movement:
- srli.c r26, r5, 0x7 /* len>=128? */
- beq 1f /* len<128 */
-
-/* r26 is the result that computed in oword_align */
-move_128bytes:
- CSUM_BIGCHUNK(src, 0x00, sum)
- CSUM_BIGCHUNK(src, 0x20, sum)
- CSUM_BIGCHUNK(src, 0x40, sum)
- CSUM_BIGCHUNK(src, 0x60, sum)
- subi.c r26, 0x01 /* r26 equals len/128 */
- addi src, 0x80
- bne move_128bytes
-
-1: /* len<128,we process 64byte here */
- andri.c r10, r5, 0x40
- beq 1f
-
-move_64bytes:
- CSUM_BIGCHUNK(src, 0x00, sum)
- CSUM_BIGCHUNK(src, 0x20, sum)
- addi src, 0x40
-
-1: /* len<64 */
- andri r26, r5, 0x1c /* 0x1c=28 */
- andri.c r10, r5, 0x20
- beq do_end_words /* decided by andri */
-
-move_32bytes:
- CSUM_BIGCHUNK(src, 0x00, sum)
- andri r26, r5, 0x1c
- addri src, src, 0x20
-
-do_end_words: /* len<32 */
- /* r26 was set already in dword_align */
- cmpi.c r26, 0x0
- beq maybe_end_cruft /* len<28 or len<56 */
- srli r26, r26, 0x2
-
-end_words:
- lw r8, [src]
- subi.c r26, 0x1 /* unit is 4 byte */
- ADDC(sum, r8)
- addi src, 0x4
- cmpi.c r26, 0x0
- bne end_words /* r26!=0 */
-
-maybe_end_cruft: /* len<4 */
- andri r10, r5, 0x3
-
-small_memcpy:
- mv r5, r10
- j small_csumcpy
-
-out:
- mv r4, sum
- br r3
-
-END(csum_partial)
diff --git a/arch/score/lib/checksum_copy.c b/arch/score/lib/checksum_copy.c
deleted file mode 100644
index 39b99ef61804..000000000000
--- a/arch/score/lib/checksum_copy.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/score/lib/csum_partial_copy.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <net/checksum.h>
-
-#include <linux/uaccess.h>
-
-unsigned int csum_partial_copy(const char *src, char *dst,
- int len, unsigned int sum)
-{
- sum = csum_partial(src, len, sum);
- memcpy(dst, src, len);
-
- return sum;
-}
-
-unsigned int csum_partial_copy_from_user(const char *src, char *dst,
- int len, unsigned int sum,
- int *err_ptr)
-{
- int missing;
-
- missing = copy_from_user(dst, src, len);
- if (missing) {
- memset(dst + len - missing, 0, missing);
- *err_ptr = -EFAULT;
- }
-
- return csum_partial(dst, len, sum);
-}
-EXPORT_SYMBOL(csum_partial_copy_from_user);
diff --git a/arch/score/lib/cmpdi2.c b/arch/score/lib/cmpdi2.c
deleted file mode 100644
index 1ed5290c66ed..000000000000
--- a/arch/score/lib/cmpdi2.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * arch/score/lib/cmpdi2.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include "libgcc.h"
-
-word_type __cmpdi2(long long a, long long b)
-{
- const DWunion au = {
- .ll = a
- };
- const DWunion bu = {
- .ll = b
- };
-
- if (au.s.high < bu.s.high)
- return 0;
- else if (au.s.high > bu.s.high)
- return 2;
-
- if ((unsigned int) au.s.low < (unsigned int) bu.s.low)
- return 0;
- else if ((unsigned int) au.s.low > (unsigned int) bu.s.low)
- return 2;
-
- return 1;
-}
-EXPORT_SYMBOL(__cmpdi2);
diff --git a/arch/score/lib/libgcc.h b/arch/score/lib/libgcc.h
deleted file mode 100644
index 0f12543d9f31..000000000000
--- a/arch/score/lib/libgcc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/score/lib/libgcc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef __ASM_LIBGCC_H
-#define __ASM_LIBGCC_H
-
-#include <asm/byteorder.h>
-
-typedef int word_type __attribute__((mode(__word__)));
-
-struct DWstruct {
- int low, high;
-};
-
-typedef union {
- struct DWstruct s;
- long long ll;
-} DWunion;
-
-#endif /* __ASM_LIBGCC_H */
diff --git a/arch/score/lib/lshrdi3.c b/arch/score/lib/lshrdi3.c
deleted file mode 100644
index ce21175fd791..000000000000
--- a/arch/score/lib/lshrdi3.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * arch/score/lib/lshrdi3.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#include <linux/module.h>
-#include "libgcc.h"
-
-long long __lshrdi3(long long u, word_type b)
-{
- DWunion uu, w;
- word_type bm;
-
- if (b == 0)
- return u;
-
- uu.ll = u;
- bm = 32 - b;
-
- if (bm <= 0) {
- w.s.high = 0;
- w.s.low = (unsigned int) uu.s.high >> -bm;
- } else {
- const unsigned int carries = (unsigned int) uu.s.high << bm;
-
- w.s.high = (unsigned int) uu.s.high >> b;
- w.s.low = ((unsigned int) uu.s.low >> b) | carries;
- }
-
- return w.ll;
-}
-EXPORT_SYMBOL(__lshrdi3);
diff --git a/arch/score/lib/string.S b/arch/score/lib/string.S
deleted file mode 100644
index e0c0318c9010..000000000000
--- a/arch/score/lib/string.S
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/score/lib/string.S
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Chen Liqin <liqin.chen@sunplusct.com>
- * Lennox Wu <lennox.wu@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/linkage.h>
-#include <asm-generic/errno.h>
-
- .text
- .align 2
-ENTRY(__strncpy_from_user)
- cmpi.c r6, 0
- mv r9, r6
- ble .L2
-0: lbu r7, [r5]
- ldi r8, 0
-1: sb r7, [r4]
-2: lb r6, [r5]
- cmp.c r6, r8
- beq .L2
-
-.L5:
- addi r8, 1
- cmp.c r8, r9
- beq .L7
-3: lbu r6, [r5, 1]+
-4: sb r6, [r4, 1]+
-5: lb r7, [r5]
- cmpi.c r7, 0
- bne .L5
-.L7:
- mv r4, r8
- br r3
-.L2:
- ldi r8, 0
- mv r4, r8
- br r3
- .section .fixup, "ax"
-99:
- ldi r4, -EFAULT
- br r3
- .previous
- .section __ex_table, "a"
- .align 2
- .word 0b ,99b
- .word 1b ,99b
- .word 2b ,99b
- .word 3b ,99b
- .word 4b ,99b
- .word 5b ,99b
- .previous
-
- .align 2
-ENTRY(__strnlen_user)
- cmpi.c r5, 0
- ble .L11
-0: lb r6, [r4]
- ldi r7, 0
- cmp.c r6, r7
- beq .L11
-.L15:
- addi r7, 1
- cmp.c r7, r5
- beq .L23
-1: lb r6, [r4,1]+
- cmpi.c r6, 0
- bne .L15
-.L23:
- addri r4, r7, 1
- br r3
-
-.L11:
- ldi r4, 1
- br r3
- .section .fixup, "ax"
-99:
- ldi r4, 0
- br r3
-
- .section __ex_table,"a"
- .align 2
- .word 0b, 99b
- .word 1b, 99b
- .previous
-
- .align 2
-ENTRY(__copy_tofrom_user)
- cmpi.c r6, 0
- mv r10,r6
- beq .L32
- ldi r9, 0
-.L34:
- add r6, r5, r9
-0: lbu r8, [r6]
- add r7, r4, r9
-1: sb r8, [r7]
- addi r9, 1
- cmp.c r9, r10
- bne .L34
-.L32:
- ldi r4, 0
- br r3
- .section .fixup, "ax"
-99:
- sub r4, r10, r9
- br r3
- .previous
- .section __ex_table, "a"
- .align 2
- .word 0b, 99b
- .word 1b, 99b
- .previous
-
- .align 2
-ENTRY(__clear_user)
- cmpi.c r5, 0
- beq .L38
- ldi r6, 0
- mv r7, r6
-.L40:
- addi r6, 1
-0: sb r7, [r4]+, 1
- cmp.c r6, r5
- bne .L40
-.L38:
- ldi r4, 0
- br r3
-
- .section .fixup, "ax"
-99:
- br r3
- .previous
- .section __ex_table, "a"
- .align 2
- .word 0b, 99b
- .previous
diff --git a/arch/score/lib/ucmpdi2.c b/arch/score/lib/ucmpdi2.c
deleted file mode 100644
index b15241e0b079..000000000000
--- a/arch/score/lib/ucmpdi2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * arch/score/lib/ucmpdi2.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include "libgcc.h"
-
-word_type __ucmpdi2(unsigned long long a, unsigned long long b)
-{
- const DWunion au = {.ll = a};
- const DWunion bu = {.ll = b};
-
- if ((unsigned int) au.s.high < (unsigned int) bu.s.high)
- return 0;
- else if ((unsigned int) au.s.high > (unsigned int) bu.s.high)
- return 2;
- if ((unsigned int) au.s.low < (unsigned int) bu.s.low)
- return 0;
- else if ((unsigned int) au.s.low > (unsigned int) bu.s.low)
- return 2;
- return 1;
-}
-EXPORT_SYMBOL(__ucmpdi2);
diff --git a/arch/score/mm/Makefile b/arch/score/mm/Makefile
deleted file mode 100644
index 7b1e29b1f8cd..000000000000
--- a/arch/score/mm/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for the Linux/SCORE-specific parts of the memory manager.
-#
-
-obj-y += cache.o extable.o fault.o init.o \
- tlb-miss.o tlb-score.o pgtable.o
diff --git a/arch/score/mm/cache.c b/arch/score/mm/cache.c
deleted file mode 100644
index b4bcfd3e8393..000000000000
--- a/arch/score/mm/cache.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * arch/score/mm/cache.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/fs.h>
-
-#include <asm/mmu_context.h>
-
-/*
-Just flush entire Dcache!!
-You must ensure the page doesn't include instructions, because
-the function will not flush the Icache.
-The addr must be cache aligned.
-*/
-static void flush_data_cache_page(unsigned long addr)
-{
- unsigned int i;
- for (i = 0; i < (PAGE_SIZE / L1_CACHE_BYTES); i += L1_CACHE_BYTES) {
- __asm__ __volatile__(
- "cache 0x0e, [%0, 0]\n"
- "cache 0x1a, [%0, 0]\n"
- "nop\n"
- : : "r" (addr));
- addr += L1_CACHE_BYTES;
- }
-}
-
-void flush_dcache_page(struct page *page)
-{
- struct address_space *mapping = page_mapping(page);
- unsigned long addr;
-
- if (PageHighMem(page))
- return;
- if (mapping && !mapping_mapped(mapping)) {
- set_bit(PG_dcache_dirty, &(page)->flags);
- return;
- }
-
- /*
- * We could delay the flush for the !page_mapping case too. But that
- * case is for exec env/arg pages and those are %99 certainly going to
- * get faulted into the tlb (and thus flushed) anyways.
- */
- addr = (unsigned long) page_address(page);
- flush_data_cache_page(addr);
-}
-EXPORT_SYMBOL(flush_dcache_page);
-
-/* called by update_mmu_cache. */
-void __update_cache(struct vm_area_struct *vma, unsigned long address,
- pte_t pte)
-{
- struct page *page;
- unsigned long pfn, addr;
- int exec = (vma->vm_flags & VM_EXEC);
-
- pfn = pte_pfn(pte);
- if (unlikely(!pfn_valid(pfn)))
- return;
- page = pfn_to_page(pfn);
- if (page_mapping(page) && test_bit(PG_dcache_dirty, &(page)->flags)) {
- addr = (unsigned long) page_address(page);
- if (exec)
- flush_data_cache_page(addr);
- clear_bit(PG_dcache_dirty, &(page)->flags);
- }
-}
-
-static inline void setup_protection_map(void)
-{
- protection_map[0] = PAGE_NONE;
- protection_map[1] = PAGE_READONLY;
- protection_map[2] = PAGE_COPY;
- protection_map[3] = PAGE_COPY;
- protection_map[4] = PAGE_READONLY;
- protection_map[5] = PAGE_READONLY;
- protection_map[6] = PAGE_COPY;
- protection_map[7] = PAGE_COPY;
- protection_map[8] = PAGE_NONE;
- protection_map[9] = PAGE_READONLY;
- protection_map[10] = PAGE_SHARED;
- protection_map[11] = PAGE_SHARED;
- protection_map[12] = PAGE_READONLY;
- protection_map[13] = PAGE_READONLY;
- protection_map[14] = PAGE_SHARED;
- protection_map[15] = PAGE_SHARED;
-}
-
-void cpu_cache_init(void)
-{
- setup_protection_map();
-}
-
-void flush_icache_all(void)
-{
- __asm__ __volatile__(
- "la r8, flush_icache_all\n"
- "cache 0x10, [r8, 0]\n"
- "nop\nnop\nnop\nnop\nnop\nnop\n"
- : : : "r8");
-}
-
-void flush_dcache_all(void)
-{
- __asm__ __volatile__(
- "la r8, flush_dcache_all\n"
- "cache 0x1f, [r8, 0]\n"
- "nop\nnop\nnop\nnop\nnop\nnop\n"
- "cache 0x1a, [r8, 0]\n"
- "nop\nnop\nnop\nnop\nnop\nnop\n"
- : : : "r8");
-}
-
-void flush_cache_all(void)
-{
- __asm__ __volatile__(
- "la r8, flush_cache_all\n"
- "cache 0x10, [r8, 0]\n"
- "nop\nnop\nnop\nnop\nnop\nnop\n"
- "cache 0x1f, [r8, 0]\n"
- "nop\nnop\nnop\nnop\nnop\nnop\n"
- "cache 0x1a, [r8, 0]\n"
- "nop\nnop\nnop\nnop\nnop\nnop\n"
- : : : "r8");
-}
-
-void flush_cache_mm(struct mm_struct *mm)
-{
- if (!(mm->context))
- return;
- flush_cache_all();
-}
-
-/*if we flush a range precisely , the processing may be very long.
-We must check each page in the range whether present. If the page is present,
-we can flush the range in the page. Be careful, the range may be cross two
-page, a page is present and another is not present.
-*/
-/*
-The interface is provided in hopes that the port can find
-a suitably efficient method for removing multiple page
-sized regions from the cache.
-*/
-void flush_cache_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
-{
- struct mm_struct *mm = vma->vm_mm;
- int exec = vma->vm_flags & VM_EXEC;
- pgd_t *pgdp;
- pud_t *pudp;
- pmd_t *pmdp;
- pte_t *ptep;
-
- if (!(mm->context))
- return;
-
- pgdp = pgd_offset(mm, start);
- pudp = pud_offset(pgdp, start);
- pmdp = pmd_offset(pudp, start);
- ptep = pte_offset(pmdp, start);
-
- while (start <= end) {
- unsigned long tmpend;
- pgdp = pgd_offset(mm, start);
- pudp = pud_offset(pgdp, start);
- pmdp = pmd_offset(pudp, start);
- ptep = pte_offset(pmdp, start);
-
- if (!(pte_val(*ptep) & _PAGE_PRESENT)) {
- start = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1);
- continue;
- }
- tmpend = (start | (PAGE_SIZE-1)) > end ?
- end : (start | (PAGE_SIZE-1));
-
- flush_dcache_range(start, tmpend);
- if (exec)
- flush_icache_range(start, tmpend);
- start = (start + PAGE_SIZE) & ~(PAGE_SIZE - 1);
- }
-}
-
-void flush_cache_page(struct vm_area_struct *vma,
- unsigned long addr, unsigned long pfn)
-{
- int exec = vma->vm_flags & VM_EXEC;
- unsigned long kaddr = 0xa0000000 | (pfn << PAGE_SHIFT);
-
- flush_dcache_range(kaddr, kaddr + PAGE_SIZE);
-
- if (exec)
- flush_icache_range(kaddr, kaddr + PAGE_SIZE);
-}
-
-void flush_cache_sigtramp(unsigned long addr)
-{
- __asm__ __volatile__(
- "cache 0x02, [%0, 0]\n"
- "nop\nnop\nnop\nnop\nnop\n"
- "cache 0x02, [%0, 0x4]\n"
- "nop\nnop\nnop\nnop\nnop\n"
-
- "cache 0x0d, [%0, 0]\n"
- "nop\nnop\nnop\nnop\nnop\n"
- "cache 0x0d, [%0, 0x4]\n"
- "nop\nnop\nnop\nnop\nnop\n"
-
- "cache 0x1a, [%0, 0]\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (addr));
-}
-
-/*
-1. WB and invalid a cache line of Dcache
-2. Drain Write Buffer
-the range must be smaller than PAGE_SIZE
-*/
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
- int size, i;
-
- start = start & ~(L1_CACHE_BYTES - 1);
- end = end & ~(L1_CACHE_BYTES - 1);
- size = end - start;
- /* flush dcache to ram, and invalidate dcache lines. */
- for (i = 0; i < size; i += L1_CACHE_BYTES) {
- __asm__ __volatile__(
- "cache 0x0e, [%0, 0]\n"
- "nop\nnop\nnop\nnop\nnop\n"
- "cache 0x1a, [%0, 0]\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (start));
- start += L1_CACHE_BYTES;
- }
-}
-
-void flush_icache_range(unsigned long start, unsigned long end)
-{
- int size, i;
- start = start & ~(L1_CACHE_BYTES - 1);
- end = end & ~(L1_CACHE_BYTES - 1);
-
- size = end - start;
- /* invalidate icache lines. */
- for (i = 0; i < size; i += L1_CACHE_BYTES) {
- __asm__ __volatile__(
- "cache 0x02, [%0, 0]\n"
- "nop\nnop\nnop\nnop\nnop\n"
- : : "r" (start));
- start += L1_CACHE_BYTES;
- }
-}
-EXPORT_SYMBOL(flush_icache_range);
diff --git a/arch/score/mm/extable.c b/arch/score/mm/extable.c
deleted file mode 100644
index 6736a3ad6286..000000000000
--- a/arch/score/mm/extable.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/score/mm/extable.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/extable.h>
-#include <linux/ptrace.h>
-#include <asm/extable.h>
-
-int fixup_exception(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
-
- fixup = search_exception_tables(regs->cp0_epc);
- if (fixup) {
- regs->cp0_epc = fixup->fixup;
- return 1;
- }
- return 0;
-}
diff --git a/arch/score/mm/fault.c b/arch/score/mm/fault.c
deleted file mode 100644
index b85fad4f0874..000000000000
--- a/arch/score/mm/fault.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * arch/score/mm/fault.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/errno.h>
-#include <linux/interrupt.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/mman.h>
-#include <linux/extable.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/uaccess.h>
-
-/*
- * This routine handles page faults. It determines the address,
- * and the problem, and then passes it off to one of the appropriate
- * routines.
- */
-asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
- unsigned long address)
-{
- struct vm_area_struct *vma = NULL;
- struct task_struct *tsk = current;
- struct mm_struct *mm = tsk->mm;
- const int field = sizeof(unsigned long) * 2;
- unsigned long flags = 0;
- siginfo_t info;
- int fault;
-
- info.si_code = SEGV_MAPERR;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- */
- if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END))
- goto vmalloc_fault;
-#ifdef MODULE_START
- if (unlikely(address >= MODULE_START && address < MODULE_END))
- goto vmalloc_fault;
-#endif
-
- /*
- * If we're in an interrupt or have no user
- * context, we must not take the fault..
- */
- if (pagefault_disabled() || !mm)
- goto bad_area_nosemaphore;
-
- if (user_mode(regs))
- flags |= FAULT_FLAG_USER;
-
- down_read(&mm->mmap_sem);
- vma = find_vma(mm, address);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= address)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
- if (expand_stack(vma, address))
- goto bad_area;
- /*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
-good_area:
- info.si_code = SEGV_ACCERR;
-
- if (write) {
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- } else {
- if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
- goto bad_area;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
- fault = handle_mm_fault(vma, address, flags);
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
- if (fault & VM_FAULT_MAJOR)
- tsk->maj_flt++;
- else
- tsk->min_flt++;
-
- up_read(&mm->mmap_sem);
- return;
-
- /*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
-bad_area:
- up_read(&mm->mmap_sem);
-
-bad_area_nosemaphore:
- /* User mode accesses just cause a SIGSEGV */
- if (user_mode(regs)) {
- tsk->thread.cp0_badvaddr = address;
- tsk->thread.error_code = write;
- info.si_signo = SIGSEGV;
- info.si_errno = 0;
- /* info.si_code has been set above */
- info.si_addr = (void __user *) address;
- force_sig_info(SIGSEGV, &info, tsk);
- return;
- }
-
-no_context:
- /* Are we prepared to handle this kernel fault? */
- if (fixup_exception(regs)) {
- current->thread.cp0_baduaddr = address;
- return;
- }
-
- /*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
- bust_spinlocks(1);
-
- printk(KERN_ALERT "CPU %d Unable to handle kernel paging request at "
- "virtual address %0*lx, epc == %0*lx, ra == %0*lx\n",
- 0, field, address, field, regs->cp0_epc,
- field, regs->regs[3]);
- die("Oops", regs);
-
- /*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-out_of_memory:
- up_read(&mm->mmap_sem);
- if (!user_mode(regs))
- goto no_context;
- pagefault_out_of_memory();
- return;
-
-do_sigbus:
- up_read(&mm->mmap_sem);
- /* Kernel mode? Handle exceptions or die */
- if (!user_mode(regs))
- goto no_context;
- else
- /*
- * Send a sigbus, regardless of whether we were in kernel
- * or user mode.
- */
- tsk->thread.cp0_badvaddr = address;
- info.si_signo = SIGBUS;
- info.si_errno = 0;
- info.si_code = BUS_ADRERR;
- info.si_addr = (void __user *) address;
- force_sig_info(SIGBUS, &info, tsk);
- return;
-vmalloc_fault:
- {
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- *
- * Do _not_ use "tsk" here. We might be inside
- * an interrupt in the middle of a task switch..
- */
- int offset = __pgd_offset(address);
- pgd_t *pgd, *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
- pte_t *pte_k;
-
- pgd = (pgd_t *) pgd_current + offset;
- pgd_k = init_mm.pgd + offset;
-
- if (!pgd_present(*pgd_k))
- goto no_context;
- set_pgd(pgd, *pgd_k);
-
- pud = pud_offset(pgd, address);
- pud_k = pud_offset(pgd_k, address);
- if (!pud_present(*pud_k))
- goto no_context;
-
- pmd = pmd_offset(pud, address);
- pmd_k = pmd_offset(pud_k, address);
- if (!pmd_present(*pmd_k))
- goto no_context;
- set_pmd(pmd, *pmd_k);
-
- pte_k = pte_offset_kernel(pmd_k, address);
- if (!pte_present(*pte_k))
- goto no_context;
- return;
- }
-}
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
deleted file mode 100644
index 444c26c0f750..000000000000
--- a/arch/score/mm/init.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * arch/score/mm/init.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/errno.h>
-#include <linux/bootmem.h>
-#include <linux/kernel.h>
-#include <linux/gfp.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/mman.h>
-#include <linux/pagemap.h>
-#include <linux/kcore.h>
-#include <linux/sched.h>
-#include <linux/initrd.h>
-
-#include <asm/sections.h>
-#include <asm/tlb.h>
-
-unsigned long empty_zero_page;
-EXPORT_SYMBOL_GPL(empty_zero_page);
-
-static void setup_zero_page(void)
-{
- struct page *page;
-
- empty_zero_page = __get_free_pages(GFP_KERNEL | __GFP_ZERO, 0);
- if (!empty_zero_page)
- panic("Oh boy, that early out of memory?");
-
- page = virt_to_page((void *) empty_zero_page);
- mark_page_reserved(page);
-}
-
-#ifndef CONFIG_NEED_MULTIPLE_NODES
-int page_is_ram(unsigned long pagenr)
-{
- if (pagenr >= min_low_pfn && pagenr < max_low_pfn)
- return 1;
- else
- return 0;
-}
-
-void __init paging_init(void)
-{
- unsigned long max_zone_pfns[MAX_NR_ZONES];
- unsigned long lastpfn;
-
- pagetable_init();
- max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
- lastpfn = max_low_pfn;
- free_area_init_nodes(max_zone_pfns);
-}
-
-void __init mem_init(void)
-{
- high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
- free_all_bootmem();
- setup_zero_page(); /* Setup zeroed pages. */
-
- mem_init_print_info(NULL);
-}
-#endif /* !CONFIG_NEED_MULTIPLE_NODES */
-
-#ifdef CONFIG_BLK_DEV_INITRD
-void free_initrd_mem(unsigned long start, unsigned long end)
-{
- free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
- "initrd");
-}
-#endif
-
-void __ref free_initmem(void)
-{
- free_initmem_default(POISON_FREE_INITMEM);
-}
-
-unsigned long pgd_current;
-
-#define __page_aligned(order) __attribute__((__aligned__(PAGE_SIZE<<order)))
-
-/*
- * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
- * are constants. So we use the variants from asm-offset.h until that gcc
- * will officially be retired.
- */
-pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned(PTE_ORDER);
-pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER);
diff --git a/arch/score/mm/pgtable.c b/arch/score/mm/pgtable.c
deleted file mode 100644
index 6408bb73d3cc..000000000000
--- a/arch/score/mm/pgtable.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/score/mm/pgtable-32.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/bootmem.h>
-#include <linux/init.h>
-#include <linux/pfn.h>
-#include <linux/mm.h>
-
-void pgd_init(unsigned long page)
-{
- unsigned long *p = (unsigned long *) page;
- int i;
-
- for (i = 0; i < USER_PTRS_PER_PGD; i += 8) {
- p[i + 0] = (unsigned long) invalid_pte_table;
- p[i + 1] = (unsigned long) invalid_pte_table;
- p[i + 2] = (unsigned long) invalid_pte_table;
- p[i + 3] = (unsigned long) invalid_pte_table;
- p[i + 4] = (unsigned long) invalid_pte_table;
- p[i + 5] = (unsigned long) invalid_pte_table;
- p[i + 6] = (unsigned long) invalid_pte_table;
- p[i + 7] = (unsigned long) invalid_pte_table;
- }
-}
-
-void __init pagetable_init(void)
-{
- /* Initialize the entire pgd. */
- pgd_init((unsigned long)swapper_pg_dir);
-}
diff --git a/arch/score/mm/tlb-miss.S b/arch/score/mm/tlb-miss.S
deleted file mode 100644
index f27651914e8d..000000000000
--- a/arch/score/mm/tlb-miss.S
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * arch/score/mm/tlbex.S
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <asm/asmmacro.h>
-#include <asm/pgtable-bits.h>
-#include <asm/scoreregs.h>
-
-/*
-* After this macro runs, the pte faulted on is
-* in register PTE, a ptr into the table in which
-* the pte belongs is in PTR.
-*/
- .macro load_pte, pte, ptr
- la \ptr, pgd_current
- lw \ptr, [\ptr, 0]
- mfcr \pte, cr6
- srli \pte, \pte, 22
- slli \pte, \pte, 2
- add \ptr, \ptr, \pte
- lw \ptr, [\ptr, 0]
- mfcr \pte, cr6
- srli \pte, \pte, 10
- andi \pte, 0xffc
- add \ptr, \ptr, \pte
- lw \pte, [\ptr, 0]
- .endm
-
- .macro pte_reload, ptr
- lw \ptr, [\ptr, 0]
- mtcr \ptr, cr12
- nop
- nop
- nop
- nop
- nop
- .endm
-
- .macro do_fault, write
- SAVE_ALL
- mfcr r6, cr6
- mv r4, r0
- ldi r5, \write
- la r8, do_page_fault
- brl r8
- j ret_from_exception
- .endm
-
- .macro pte_writable, pte, ptr, label
- andi \pte, 0x280
- cmpi.c \pte, 0x280
- bne \label
- lw \pte, [\ptr, 0] /*reload PTE*/
- .endm
-
-/*
- * Make PTE writable, update software status bits as well,
- * then store at PTR.
- */
- .macro pte_makewrite, pte, ptr
- ori \pte, 0x426
- sw \pte, [\ptr, 0]
- .endm
-
- .text
-ENTRY(score7_FTLB_refill_Handler)
- la r31, pgd_current /* get pgd pointer */
- lw r31, [r31, 0] /* get the address of PGD */
- mfcr r30, cr6
- srli r30, r30, 22 /* PGDIR_SHIFT = 22*/
- slli r30, r30, 2
- add r31, r31, r30
- lw r31, [r31, 0] /* get the address of the start address of PTE table */
-
- mfcr r30, cr9
- andi r30, 0xfff /* equivalent to get PET index and right shift 2 bits */
- add r31, r31, r30
- lw r30, [r31, 0] /* load pte entry */
- mtcr r30, cr12
- nop
- nop
- nop
- nop
- nop
- mtrtlb
- nop
- nop
- nop
- nop
- nop
- rte /* 6 cycles to make sure tlb entry works */
-
-ENTRY(score7_KSEG_refill_Handler)
- la r31, pgd_current /* get pgd pointer */
- lw r31, [r31, 0] /* get the address of PGD */
- mfcr r30, cr6
- srli r30, r30, 22 /* PGDIR_SHIFT = 22 */
- slli r30, r30, 2
- add r31, r31, r30
- lw r31, [r31, 0] /* get the address of the start address of PTE table */
-
- mfcr r30, cr6 /* get Bad VPN */
- srli r30, r30, 10
- andi r30, 0xffc /* PTE VPN mask (bit 11~2) */
-
- add r31, r31, r30
- lw r30, [r31, 0] /* load pte entry */
- mtcr r30, cr12
- nop
- nop
- nop
- nop
- nop
- mtrtlb
- nop
- nop
- nop
- nop
- nop
- rte /* 6 cycles to make sure tlb entry works */
-
-nopage_tlbl:
- do_fault 0 /* Read */
-
-ENTRY(handle_tlb_refill)
- load_pte r30, r31
- pte_writable r30, r31, handle_tlb_refill_nopage
- pte_makewrite r30, r31 /* Access|Modify|Dirty|Valid */
- pte_reload r31
- mtrtlb
- nop
- nop
- nop
- nop
- nop
- rte
-handle_tlb_refill_nopage:
- do_fault 0 /* Read */
-
-ENTRY(handle_tlb_invaild)
- load_pte r30, r31
- stlb /* find faulting entry */
- pte_writable r30, r31, handle_tlb_invaild_nopage
- pte_makewrite r30, r31 /* Access|Modify|Dirty|Valid */
- pte_reload r31
- mtptlb
- nop
- nop
- nop
- nop
- nop
- rte
-handle_tlb_invaild_nopage:
- do_fault 0 /* Read */
-
-ENTRY(handle_mod)
- load_pte r30, r31
- stlb /* find faulting entry */
- andi r30, _PAGE_WRITE /* Writable? */
- cmpz.c r30
- beq nowrite_mod
- lw r30, [r31, 0] /* reload into r30 */
-
- /* Present and writable bits set, set accessed and dirty bits. */
- pte_makewrite r30, r31
-
- /* Now reload the entry into the tlb. */
- pte_reload r31
- mtptlb
- nop
- nop
- nop
- nop
- nop
- rte
-
-nowrite_mod:
- do_fault 1 /* Write */
diff --git a/arch/score/mm/tlb-score.c b/arch/score/mm/tlb-score.c
deleted file mode 100644
index 004073717de0..000000000000
--- a/arch/score/mm/tlb-score.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * arch/score/mm/tlb-score.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- * Lennox Wu <lennox.wu@sunplusct.com>
- * Chen Liqin <liqin.chen@sunplusct.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/highmem.h>
-#include <linux/module.h>
-
-#include <asm/irq.h>
-#include <asm/mmu_context.h>
-#include <asm/tlb.h>
-
-#define TLBSIZE 32
-
-unsigned long asid_cache = ASID_FIRST_VERSION;
-EXPORT_SYMBOL(asid_cache);
-
-void local_flush_tlb_all(void)
-{
- unsigned long flags;
- unsigned long old_ASID;
- int entry;
-
- local_irq_save(flags);
- old_ASID = pevn_get() & ASID_MASK;
- pectx_set(0); /* invalid */
- entry = tlblock_get(); /* skip locked entries*/
-
- for (; entry < TLBSIZE; entry++) {
- tlbpt_set(entry);
- pevn_set(KSEG1);
- barrier();
- tlb_write_indexed();
- }
- pevn_set(old_ASID);
- local_irq_restore(flags);
-}
-
-/*
- * If mm is currently active_mm, we can't really drop it. Instead,
- * we will get a new one for it.
- */
-static inline void
-drop_mmu_context(struct mm_struct *mm)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- get_new_mmu_context(mm);
- pevn_set(mm->context & ASID_MASK);
- local_irq_restore(flags);
-}
-
-void local_flush_tlb_mm(struct mm_struct *mm)
-{
- if (mm->context != 0)
- drop_mmu_context(mm);
-}
-
-void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- unsigned long end)
-{
- struct mm_struct *mm = vma->vm_mm;
- unsigned long vma_mm_context = mm->context;
- if (mm->context != 0) {
- unsigned long flags;
- int size;
-
- local_irq_save(flags);
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- if (size <= TLBSIZE) {
- int oldpid = pevn_get() & ASID_MASK;
- int newpid = vma_mm_context & ASID_MASK;
-
- start &= PAGE_MASK;
- end += (PAGE_SIZE - 1);
- end &= PAGE_MASK;
- while (start < end) {
- int idx;
-
- pevn_set(start | newpid);
- start += PAGE_SIZE;
- barrier();
- tlb_probe();
- idx = tlbpt_get();
- pectx_set(0);
- pevn_set(KSEG1);
- if (idx < 0)
- continue;
- tlb_write_indexed();
- }
- pevn_set(oldpid);
- } else {
- /* Bigger than TLBSIZE, get new ASID directly */
- get_new_mmu_context(mm);
- if (mm == current->active_mm)
- pevn_set(vma_mm_context & ASID_MASK);
- }
- local_irq_restore(flags);
- }
-}
-
-void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
-{
- unsigned long flags;
- int size;
-
- local_irq_save(flags);
- size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- if (size <= TLBSIZE) {
- int pid = pevn_get();
-
- start &= PAGE_MASK;
- end += PAGE_SIZE - 1;
- end &= PAGE_MASK;
-
- while (start < end) {
- long idx;
-
- pevn_set(start);
- start += PAGE_SIZE;
- tlb_probe();
- idx = tlbpt_get();
- if (idx < 0)
- continue;
- pectx_set(0);
- pevn_set(KSEG1);
- barrier();
- tlb_write_indexed();
- }
- pevn_set(pid);
- } else {
- local_flush_tlb_all();
- }
-
- local_irq_restore(flags);
-}
-
-void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
- if (vma && vma->vm_mm->context != 0) {
- unsigned long flags;
- int oldpid, newpid, idx;
- unsigned long vma_ASID = vma->vm_mm->context;
-
- newpid = vma_ASID & ASID_MASK;
- page &= PAGE_MASK;
- local_irq_save(flags);
- oldpid = pevn_get() & ASID_MASK;
- pevn_set(page | newpid);
- barrier();
- tlb_probe();
- idx = tlbpt_get();
- pectx_set(0);
- pevn_set(KSEG1);
- if (idx < 0) /* p_bit(31) - 1: miss, 0: hit*/
- goto finish;
- barrier();
- tlb_write_indexed();
-finish:
- pevn_set(oldpid);
- local_irq_restore(flags);
- }
-}
-
-/*
- * This one is only used for pages with the global bit set so we don't care
- * much about the ASID.
- */
-void local_flush_tlb_one(unsigned long page)
-{
- unsigned long flags;
- int oldpid, idx;
-
- local_irq_save(flags);
- oldpid = pevn_get();
- page &= (PAGE_MASK << 1);
- pevn_set(page);
- barrier();
- tlb_probe();
- idx = tlbpt_get();
- pectx_set(0);
- if (idx >= 0) {
- /* Make sure all entries differ. */
- pevn_set(KSEG1);
- barrier();
- tlb_write_indexed();
- }
- pevn_set(oldpid);
- local_irq_restore(flags);
-}
-
-void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
-{
- unsigned long flags;
- int idx, pid;
-
- /*
- * Handle debugger faulting in for debugee.
- */
- if (current->active_mm != vma->vm_mm)
- return;
-
- pid = pevn_get() & ASID_MASK;
-
- local_irq_save(flags);
- address &= PAGE_MASK;
- pevn_set(address | pid);
- barrier();
- tlb_probe();
- idx = tlbpt_get();
- pectx_set(pte_val(pte));
- pevn_set(address | pid);
- if (idx < 0)
- tlb_write_random();
- else
- tlb_write_indexed();
-
- pevn_set(pid);
- local_irq_restore(flags);
-}
-
-void tlb_init(void)
-{
- tlblock_set(0);
- local_flush_tlb_all();
- memcpy((void *)(EXCEPTION_VECTOR_BASE_ADDR + 0x100),
- &score7_FTLB_refill_Handler, 0xFC);
- flush_icache_range(EXCEPTION_VECTOR_BASE_ADDR + 0x100,
- EXCEPTION_VECTOR_BASE_ADDR + 0x1FC);
-}
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 724911c59e7d..f8afc014e084 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -35,7 +35,7 @@ asmlinkage int old_mmap(unsigned long addr, unsigned long len,
{
if (off & ~PAGE_MASK)
return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, off>>PAGE_SHIFT);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, off>>PAGE_SHIFT);
}
asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
@@ -51,7 +51,7 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
pgoff >>= PAGE_SHIFT - 12;
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
}
/* sys_cacheflush -- flush (part of) the processor cache. */
diff --git a/arch/sh/kernel/sys_sh32.c b/arch/sh/kernel/sys_sh32.c
index f8dc8bfd4606..9dca568509a5 100644
--- a/arch/sh/kernel/sys_sh32.c
+++ b/arch/sh/kernel/sys_sh32.c
@@ -39,23 +39,23 @@ asmlinkage int sys_sh_pipe(void)
asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char __user *buf,
size_t count, long dummy, loff_t pos)
{
- return sys_pread64(fd, buf, count, pos);
+ return ksys_pread64(fd, buf, count, pos);
}
asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char __user *buf,
size_t count, long dummy, loff_t pos)
{
- return sys_pwrite64(fd, buf, count, pos);
+ return ksys_pwrite64(fd, buf, count, pos);
}
asmlinkage int sys_fadvise64_64_wrapper(int fd, u32 offset0, u32 offset1,
u32 len0, u32 len1, int advice)
{
#ifdef __LITTLE_ENDIAN__
- return sys_fadvise64_64(fd, (u64)offset1 << 32 | offset0,
- (u64)len1 << 32 | len0, advice);
+ return ksys_fadvise64_64(fd, (u64)offset1 << 32 | offset0,
+ (u64)len1 << 32 | len0, advice);
#else
- return sys_fadvise64_64(fd, (u64)offset0 << 32 | offset1,
- (u64)len0 << 32 | len1, advice);
+ return ksys_fadvise64_64(fd, (u64)offset0 << 32 | offset1,
+ (u64)len0 << 32 | len1, advice);
#endif
}
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index cd51a89b393c..df2dc1784673 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -127,12 +127,7 @@ static inline void sbus_memcpy_toio(volatile void __iomem *dst,
* Bus number may be embedded in the higher bits of the physical address.
* This is why we have no bus number argument to ioremap().
*/
-void __iomem *ioremap(unsigned long offset, unsigned long size);
-#define ioremap_nocache(X,Y) ioremap((X),(Y))
-#define ioremap_wc(X,Y) ioremap((X),(Y))
-#define ioremap_wt(X,Y) ioremap((X),(Y))
void iounmap(volatile void __iomem *addr);
-
/* Create a virtual mapping cookie for an IO port range */
void __iomem *ioport_map(unsigned long port, unsigned int nr);
void ioport_unmap(void __iomem *);
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 7eeef80c02f7..3bcef9ce74df 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -122,12 +122,12 @@ static void xres_free(struct xresource *xrp) {
*
* Bus type is always zero on IIep.
*/
-void __iomem *ioremap(unsigned long offset, unsigned long size)
+void __iomem *ioremap(phys_addr_t offset, size_t size)
{
char name[14];
sprintf(name, "phys_%08x", (u32)offset);
- return _sparc_alloc_io(0, offset, size, name);
+ return _sparc_alloc_io(0, (unsigned long)offset, size, name);
}
EXPORT_SYMBOL(ioremap);
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 5c1f54758312..d3149baaa33c 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1342,7 +1342,7 @@ static int collect_events(struct perf_event *group, int max_count,
events[n] = group->hw.event_base;
current_idx[n++] = PIC_NO_INDEX;
}
- list_for_each_entry(event, &group->sibling_list, group_entry) {
+ for_each_sibling_event(event, group) {
if (!is_software_event(event) &&
event->state != PERF_EVENT_STATE_OFF) {
if (n >= max_count)
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 2e3a3e203061..13664c377196 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -86,7 +86,7 @@ static void prom_sync_me(void)
show_free_areas(0, NULL);
if (!is_idle_task(current)) {
local_irq_enable();
- sys_sync();
+ ksys_sync();
local_irq_disable();
}
prom_printf("Returning to prom\n");
diff --git a/arch/sparc/kernel/sys_sparc32.c b/arch/sparc/kernel/sys_sparc32.c
index 6d964bdefbaa..f166e5bbf506 100644
--- a/arch/sparc/kernel/sys_sparc32.c
+++ b/arch/sparc/kernel/sys_sparc32.c
@@ -57,7 +57,7 @@ asmlinkage long sys32_truncate64(const char __user * path, unsigned long high, u
if ((int)high < 0)
return -EINVAL;
else
- return sys_truncate(path, (high << 32) | low);
+ return ksys_truncate(path, (high << 32) | low);
}
asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long high, unsigned long low)
@@ -65,7 +65,7 @@ asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long high, unsigned
if ((int)high < 0)
return -EINVAL;
else
- return sys_ftruncate(fd, (high << 32) | low);
+ return ksys_ftruncate(fd, (high << 32) | low);
}
static int cp_compat_stat64(struct kstat *stat,
@@ -200,7 +200,7 @@ asmlinkage compat_ssize_t sys32_pread64(unsigned int fd,
unsigned long poshi,
unsigned long poslo)
{
- return sys_pread64(fd, ubuf, count, (poshi << 32) | poslo);
+ return ksys_pread64(fd, ubuf, count, (poshi << 32) | poslo);
}
asmlinkage compat_ssize_t sys32_pwrite64(unsigned int fd,
@@ -209,7 +209,7 @@ asmlinkage compat_ssize_t sys32_pwrite64(unsigned int fd,
unsigned long poshi,
unsigned long poslo)
{
- return sys_pwrite64(fd, ubuf, count, (poshi << 32) | poslo);
+ return ksys_pwrite64(fd, ubuf, count, (poshi << 32) | poslo);
}
asmlinkage long compat_sys_readahead(int fd,
@@ -217,7 +217,7 @@ asmlinkage long compat_sys_readahead(int fd,
unsigned long offlo,
compat_size_t count)
{
- return sys_readahead(fd, (offhi << 32) | offlo, count);
+ return ksys_readahead(fd, (offhi << 32) | offlo, count);
}
long compat_sys_fadvise64(int fd,
@@ -225,7 +225,7 @@ long compat_sys_fadvise64(int fd,
unsigned long offlo,
compat_size_t len, int advice)
{
- return sys_fadvise64_64(fd, (offhi << 32) | offlo, len, advice);
+ return ksys_fadvise64_64(fd, (offhi << 32) | offlo, len, advice);
}
long compat_sys_fadvise64_64(int fd,
@@ -233,15 +233,15 @@ long compat_sys_fadvise64_64(int fd,
unsigned long lenhi, unsigned long lenlo,
int advice)
{
- return sys_fadvise64_64(fd,
- (offhi << 32) | offlo,
- (lenhi << 32) | lenlo,
- advice);
+ return ksys_fadvise64_64(fd,
+ (offhi << 32) | offlo,
+ (lenhi << 32) | lenlo,
+ advice);
}
long sys32_sync_file_range(unsigned int fd, unsigned long off_high, unsigned long off_low, unsigned long nb_high, unsigned long nb_low, unsigned int flags)
{
- return sys_sync_file_range(fd,
+ return ksys_sync_file_range(fd,
(off_high << 32) | off_low,
(nb_high << 32) | nb_low,
flags);
@@ -250,6 +250,6 @@ long sys32_sync_file_range(unsigned int fd, unsigned long off_high, unsigned lon
asmlinkage long compat_sys_fallocate(int fd, int mode, u32 offhi, u32 offlo,
u32 lenhi, u32 lenlo)
{
- return sys_fallocate(fd, mode, ((loff_t)offhi << 32) | offlo,
- ((loff_t)lenhi << 32) | lenlo);
+ return ksys_fallocate(fd, mode, ((loff_t)offhi << 32) | offlo,
+ ((loff_t)lenhi << 32) | lenlo);
}
diff --git a/arch/sparc/kernel/sys_sparc_32.c b/arch/sparc/kernel/sys_sparc_32.c
index 990703b7cf4d..d980da4ffd7b 100644
--- a/arch/sparc/kernel/sys_sparc_32.c
+++ b/arch/sparc/kernel/sys_sparc_32.c
@@ -104,8 +104,8 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
{
/* Make sure the shift for mmap2 is constant (12), no matter what PAGE_SIZE
we have. */
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- pgoff >> (PAGE_SHIFT - 12));
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ pgoff >> (PAGE_SHIFT - 12));
}
asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
@@ -113,7 +113,7 @@ asmlinkage long sys_mmap(unsigned long addr, unsigned long len,
unsigned long off)
{
/* no alignment check? */
- return sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
}
long sparc_remap_file_pages(unsigned long start, unsigned long size,
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 55416db482ad..ebb84dc8a5a7 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -458,7 +458,7 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
goto out;
if (off & ~PAGE_MASK)
goto out;
- retval = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ retval = ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
out:
return retval;
}
diff --git a/arch/sparc/mm/tlb.c b/arch/sparc/mm/tlb.c
index 847ddffbf38a..b5cfab711651 100644
--- a/arch/sparc/mm/tlb.c
+++ b/arch/sparc/mm/tlb.c
@@ -163,13 +163,10 @@ static void tlb_batch_pmd_scan(struct mm_struct *mm, unsigned long vaddr,
pte_unmap(pte);
}
-void set_pmd_at(struct mm_struct *mm, unsigned long addr,
- pmd_t *pmdp, pmd_t pmd)
-{
- pmd_t orig = *pmdp;
-
- *pmdp = pmd;
+static void __set_pmd_acct(struct mm_struct *mm, unsigned long addr,
+ pmd_t orig, pmd_t pmd)
+{
if (mm == &init_mm)
return;
@@ -219,6 +216,15 @@ void set_pmd_at(struct mm_struct *mm, unsigned long addr,
}
}
+void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+ pmd_t *pmdp, pmd_t pmd)
+{
+ pmd_t orig = *pmdp;
+
+ *pmdp = pmd;
+ __set_pmd_acct(mm, addr, orig, pmd);
+}
+
static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
unsigned long address, pmd_t *pmdp, pmd_t pmd)
{
@@ -227,6 +233,7 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
do {
old = *pmdp;
} while (cmpxchg64(&pmdp->pmd, old.pmd, pmd.pmd) != old.pmd);
+ __set_pmd_acct(vma->vm_mm, address, old, pmd);
return old;
}
diff --git a/arch/tile/Kbuild b/arch/tile/Kbuild
deleted file mode 100644
index a9b922716092..000000000000
--- a/arch/tile/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += kernel/
-obj-y += mm/
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
deleted file mode 100644
index ef9d403cbbe4..000000000000
--- a/arch/tile/Kconfig
+++ /dev/null
@@ -1,481 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-
-config TILE
- def_bool y
- select ARCH_HAS_DEVMEM_IS_ALLOWED
- select ARCH_HAVE_NMI_SAFE_CMPXCHG
- select ARCH_WANT_FRAME_POINTERS
- select CC_OPTIMIZE_FOR_SIZE
- select EDAC_SUPPORT
- select GENERIC_CLOCKEVENTS
- select GENERIC_FIND_FIRST_BIT
- select GENERIC_IRQ_PROBE
- select GENERIC_IRQ_SHOW
- select GENERIC_PENDING_IRQ if SMP
- select GENERIC_STRNCPY_FROM_USER
- select GENERIC_STRNLEN_USER
- select HAVE_ARCH_SECCOMP_FILTER
- select HAVE_ARCH_TRACEHOOK
- select HAVE_CONTEXT_TRACKING
- select HAVE_DEBUG_BUGVERBOSE
- select HAVE_DEBUG_KMEMLEAK
- select HAVE_DEBUG_STACKOVERFLOW
- select HAVE_DMA_API_DEBUG
- select HAVE_EXIT_THREAD
- select HAVE_KVM if !TILEGX
- select HAVE_NMI if USE_PMC
- select HAVE_PERF_EVENTS
- select HAVE_SYSCALL_TRACEPOINTS
- select MODULES_USE_ELF_RELA
- select SYSCTL_EXCEPTION_TRACE
- select SYS_HYPERVISOR
- select USER_STACKTRACE_SUPPORT
- select USE_PMC if PERF_EVENTS
- select VIRT_TO_BUS
-
-config MMU
- def_bool y
-
-config GENERIC_CSUM
- def_bool y
-
-config HAVE_ARCH_ALLOC_REMAP
- def_bool y
-
-config HAVE_SETUP_PER_CPU_AREA
- def_bool y
-
-config NEED_PER_CPU_PAGE_FIRST_CHUNK
- def_bool y
-
-config SYS_SUPPORTS_HUGETLBFS
- def_bool y
-
-# Support for additional huge page sizes besides HPAGE_SIZE.
-# The software support is currently only present in the TILE-Gx
-# hypervisor. TILEPro in any case does not support page sizes
-# larger than the default HPAGE_SIZE.
-config HUGETLB_SUPER_PAGES
- depends on HUGETLB_PAGE && TILEGX
- def_bool y
-
-config GENERIC_TIME_VSYSCALL
- def_bool y
-
-# Enable PMC if PERF_EVENTS, OPROFILE, or WATCHPOINTS are enabled.
-config USE_PMC
- bool
-
-# FIXME: tilegx can implement a more efficient rwsem.
-config RWSEM_GENERIC_SPINLOCK
- def_bool y
-
-# We only support gcc 4.4 and above, so this should work.
-config ARCH_SUPPORTS_OPTIMIZED_INLINING
- def_bool y
-
-config ARCH_PHYS_ADDR_T_64BIT
- def_bool y
-
-config ARCH_DMA_ADDR_T_64BIT
- def_bool y
-
-config NEED_DMA_MAP_STATE
- def_bool y
-
-config ARCH_HAS_DMA_SET_COHERENT_MASK
- bool
-
-config LOCKDEP_SUPPORT
- def_bool y
-
-config STACKTRACE_SUPPORT
- def_bool y
- select STACKTRACE
-
-# We use discontigmem for now; at some point we may want to switch
-# to sparsemem (Tilera bug 7996).
-config ARCH_DISCONTIGMEM_ENABLE
- def_bool y
-
-config ARCH_DISCONTIGMEM_DEFAULT
- def_bool y
-
-config TRACE_IRQFLAGS_SUPPORT
- def_bool y
-
-# SMP is required for Tilera Linux.
-config SMP
- def_bool y
-
-config HVC_TILE
- depends on TTY
- select HVC_DRIVER
- select HVC_IRQ if TILEGX
- def_bool y
-
-# Building with ARCH=tilegx (or ARCH=tile) implies using the
-# 64-bit TILE-Gx toolchain, so force CONFIG_TILEGX on.
-config TILEGX
- def_bool ARCH != "tilepro"
- select ARCH_SUPPORTS_ATOMIC_RMW
- select GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
- select HAVE_ARCH_JUMP_LABEL
- select HAVE_ARCH_KGDB
- select HAVE_DYNAMIC_FTRACE
- select HAVE_FTRACE_MCOUNT_RECORD
- select HAVE_FUNCTION_GRAPH_TRACER
- select HAVE_FUNCTION_TRACER
- select HAVE_KPROBES
- select HAVE_KRETPROBES
- select SPARSE_IRQ
-
-config TILEPRO
- def_bool !TILEGX
-
-config 64BIT
- def_bool TILEGX
-
-config ARCH_DEFCONFIG
- string
- default "arch/tile/configs/tilepro_defconfig" if !TILEGX
- default "arch/tile/configs/tilegx_defconfig" if TILEGX
-
-config PGTABLE_LEVELS
- int
- default 3 if 64BIT
- default 2
-
-source "init/Kconfig"
-
-source "kernel/Kconfig.freezer"
-
-menu "Tilera-specific configuration"
-
-config NR_CPUS
- int "Maximum number of tiles (2-255)"
- range 2 255
- depends on SMP
- default "64"
- ---help---
- Building with 64 is the recommended value, but a slightly
- smaller kernel memory footprint results from using a smaller
- value on chips with fewer tiles.
-
-choice
- prompt "Kernel page size"
- default PAGE_SIZE_64KB
- help
- This lets you select the page size of the kernel. For best
- performance on memory-intensive applications, a page size of 64KB
- is recommended. For workloads involving many small files, many
- connections, etc., it may be better to select 16KB, which uses
- memory more efficiently at some cost in TLB performance.
-
- Note that for TILEPro, you must also rebuild the hypervisor
- with a matching page size.
-
-config PAGE_SIZE_4KB
- bool "4KB" if TILEPRO
-
-config PAGE_SIZE_16KB
- bool "16KB"
-
-config PAGE_SIZE_64KB
- bool "64KB"
-
-endchoice
-
-source "kernel/Kconfig.hz"
-
-config KEXEC
- bool "kexec system call"
- select KEXEC_CORE
- ---help---
- kexec is a system call that implements the ability to shutdown your
- current kernel, and to start another kernel. It is like a reboot
- but it is independent of the system firmware. It is used
- to implement the "mboot" Tilera booter.
-
- The name comes from the similarity to the exec system call.
-
-config COMPAT
- bool "Support 32-bit TILE-Gx binaries in addition to 64-bit"
- depends on TILEGX
- select COMPAT_BINFMT_ELF
- default y
- ---help---
- If enabled, the kernel will support running TILE-Gx binaries
- that were built with the -m32 option.
-
-config SECCOMP
- bool "Enable seccomp to safely compute untrusted bytecode"
- depends on PROC_FS
- help
- This kernel feature is useful for number crunching applications
- that may need to compute untrusted bytecode during their
- execution. By using pipes or other transports made available to
- the process as file descriptors supporting the read/write
- syscalls, it's possible to isolate those applications in
- their own address space using seccomp. Once seccomp is
- enabled via prctl, it cannot be disabled and the task is only
- allowed to execute a few safe syscalls defined by each seccomp
- mode.
-
- If unsure, say N.
-
-config SYSVIPC_COMPAT
- def_bool y
- depends on COMPAT && SYSVIPC
-
-# We do not currently support disabling HIGHMEM on tilepro.
-config HIGHMEM
- bool # "Support for more than 512 MB of RAM"
- default !TILEGX
- ---help---
- Linux can use the full amount of RAM in the system by
- default. However, the address space of TILE processors is
- only 4 Gigabytes large. That means that, if you have a large
- amount of physical memory, not all of it can be "permanently
- mapped" by the kernel. The physical memory that's not
- permanently mapped is called "high memory".
-
- If you are compiling a kernel which will never run on a
- machine with more than 512 MB total physical RAM, answer
- "false" here. This will result in the kernel mapping all of
- physical memory into the top 1 GB of virtual memory space.
-
- If unsure, say "true".
-
-config ZONE_DMA32
- def_bool y
-
-config IOMMU_HELPER
- bool
-
-config NEED_SG_DMA_LENGTH
- bool
-
-config SWIOTLB
- bool
- default TILEGX
- select DMA_DIRECT_OPS
- select IOMMU_HELPER
- select NEED_SG_DMA_LENGTH
- select ARCH_HAS_DMA_SET_COHERENT_MASK
-
-# We do not currently support disabling NUMA.
-config NUMA
- bool # "NUMA Memory Allocation and Scheduler Support"
- depends on SMP && DISCONTIGMEM
- default y
- ---help---
- NUMA memory allocation is required for TILE processors
- unless booting with memory striping enabled in the
- hypervisor, or with only a single memory controller.
- It is recommended that this option always be enabled.
-
-config NODES_SHIFT
- int "Log base 2 of the max number of memory controllers"
- default 2
- depends on NEED_MULTIPLE_NODES
- ---help---
- By default, 2, i.e. 2^2 == 4 DDR2 controllers.
- In a system with more controllers, this value should be raised.
-
-choice
- depends on !TILEGX
- prompt "Memory split" if EXPERT
- default VMSPLIT_3G
- ---help---
- Select the desired split between kernel and user memory.
-
- If the address range available to the kernel is less than the
- physical memory installed, the remaining memory will be available
- as "high memory". Accessing high memory is a little more costly
- than low memory, as it needs to be mapped into the kernel first.
- Note that increasing the kernel address space limits the range
- available to user programs, making the address space there
- tighter. Selecting anything other than the default 3G/1G split
- will also likely make your kernel incompatible with binary-only
- kernel modules.
-
- If you are not absolutely sure what you are doing, leave this
- option alone!
-
- config VMSPLIT_3_75G
- bool "3.75G/0.25G user/kernel split (no kernel networking)"
- config VMSPLIT_3_5G
- bool "3.5G/0.5G user/kernel split"
- config VMSPLIT_3G
- bool "3G/1G user/kernel split"
- config VMSPLIT_2_75G
- bool "2.75G/1.25G user/kernel split (for full 1G low memory)"
- config VMSPLIT_2_5G
- bool "2.5G/1.5G user/kernel split"
- config VMSPLIT_2_25G
- bool "2.25G/1.75G user/kernel split"
- config VMSPLIT_2G
- bool "2G/2G user/kernel split"
- config VMSPLIT_1G
- bool "1G/3G user/kernel split"
-endchoice
-
-config PAGE_OFFSET
- hex
- depends on !64BIT
- default 0xF0000000 if VMSPLIT_3_75G
- default 0xE0000000 if VMSPLIT_3_5G
- default 0xB0000000 if VMSPLIT_2_75G
- default 0xA0000000 if VMSPLIT_2_5G
- default 0x90000000 if VMSPLIT_2_25G
- default 0x80000000 if VMSPLIT_2G
- default 0x40000000 if VMSPLIT_1G
- default 0xC0000000
-
-source "mm/Kconfig"
-
-source "kernel/Kconfig.preempt"
-
-config CMDLINE_BOOL
- bool "Built-in kernel command line"
- default n
- ---help---
- Allow for specifying boot arguments to the kernel at
- build time. On some systems (e.g. embedded ones), it is
- necessary or convenient to provide some or all of the
- kernel boot arguments with the kernel itself (that is,
- to not rely on the boot loader to provide them.)
-
- To compile command line arguments into the kernel,
- set this option to 'Y', then fill in the
- the boot arguments in CONFIG_CMDLINE.
-
- Systems with fully functional boot loaders (e.g. mboot, or
- if booting over PCI) should leave this option set to 'N'.
-
-config CMDLINE
- string "Built-in kernel command string"
- depends on CMDLINE_BOOL
- default ""
- ---help---
- Enter arguments here that should be compiled into the kernel
- image and used at boot time. If the boot loader provides a
- command line at boot time, it is appended to this string to
- form the full kernel command line, when the system boots.
-
- However, you can use the CONFIG_CMDLINE_OVERRIDE option to
- change this behavior.
-
- In most cases, the command line (whether built-in or provided
- by the boot loader) should specify the device for the root
- file system.
-
-config CMDLINE_OVERRIDE
- bool "Built-in command line overrides boot loader arguments"
- default n
- depends on CMDLINE_BOOL
- ---help---
- Set this option to 'Y' to have the kernel ignore the boot loader
- command line, and use ONLY the built-in command line.
-
- This is used to work around broken boot loaders. This should
- be set to 'N' under normal conditions.
-
-config VMALLOC_RESERVE
- hex
- default 0x2000000
-
-config HARDWALL
- bool "Hardwall support to allow access to user dynamic network"
- default y
-
-config KERNEL_PL
- int "Processor protection level for kernel"
- range 1 2
- default 2 if TILEGX
- default 1 if !TILEGX
- ---help---
- Since MDE 4.2, the Tilera hypervisor runs the kernel
- at PL2 by default. If running under an older hypervisor,
- or as a KVM guest, you must run at PL1. (The current
- hypervisor may also be recompiled with "make HV_PL=2" to
- allow it to run a kernel at PL1, but clients running at PL1
- are not expected to be supported indefinitely.)
-
- If you're not sure, don't change the default.
-
-source "arch/tile/gxio/Kconfig"
-
-endmenu # Tilera-specific configuration
-
-menu "Bus options"
-
-config PCI
- bool "PCI support"
- default y
- select PCI_DOMAINS
- select GENERIC_PCI_IOMAP
- select TILE_GXIO_TRIO if TILEGX
- select PCI_MSI if TILEGX
- ---help---
- Enable PCI root complex support, so PCIe endpoint devices can
- be attached to the Tile chip. Many, but not all, PCI devices
- are supported under Tilera's root complex driver.
-
-config PCI_DOMAINS
- bool
-
-config NO_IOMEM
- def_bool !PCI
-
-config NO_IOPORT_MAP
- def_bool !PCI
-
-config TILE_PCI_IO
- bool "PCI I/O space support"
- default n
- depends on PCI
- depends on TILEGX
- ---help---
- Enable PCI I/O space support on TILEGx. Since the PCI I/O space
- is used by few modern PCIe endpoint devices, its support is disabled
- by default to save the TRIO PIO Region resource for other purposes.
-
-source "drivers/pci/Kconfig"
-
-config TILE_USB
- tristate "Tilera USB host adapter support"
- default y
- depends on USB
- depends on TILEGX
- select TILE_GXIO_USB_HOST
- ---help---
- Provides USB host adapter support for the built-in EHCI and OHCI
- interfaces on TILE-Gx chips.
-
-endmenu
-
-menu "Executable file formats"
-
-source "fs/Kconfig.binfmt"
-
-endmenu
-
-source "net/Kconfig"
-
-source "drivers/Kconfig"
-
-source "fs/Kconfig"
-
-source "arch/tile/Kconfig.debug"
-
-source "security/Kconfig"
-
-source "crypto/Kconfig"
-
-source "lib/Kconfig"
-
-source "arch/tile/kvm/Kconfig"
diff --git a/arch/tile/Kconfig.debug b/arch/tile/Kconfig.debug
deleted file mode 100644
index 9f665d1a805f..000000000000
--- a/arch/tile/Kconfig.debug
+++ /dev/null
@@ -1,26 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-menu "Kernel hacking"
-
-source "lib/Kconfig.debug"
-
-config EARLY_PRINTK
- bool "Early printk" if EXPERT && DEBUG_KERNEL
- default y
- help
- Write kernel log output directly via the hypervisor console.
-
- This is useful for kernel debugging when your machine crashes very
- early before the console code is initialized. For normal operation
- it is not recommended because it looks ugly and doesn't cooperate
- with klogd/syslogd. You should normally N here,
- unless you want to debug such a crash.
-
-config TILE_HVGLUE_TRACE
- bool "Provide wrapper functions for hypervisor ABI calls"
- default n
- help
- Provide wrapper functions for the hypervisor ABI calls
- defined in arch/tile/kernel/hvglue.S. This allows tracing
- mechanisms, etc., to have visibility into those calls.
-
-endmenu
diff --git a/arch/tile/Makefile b/arch/tile/Makefile
deleted file mode 100644
index 8fa0befba32b..000000000000
--- a/arch/tile/Makefile
+++ /dev/null
@@ -1,77 +0,0 @@
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License. See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# This file is included by the global makefile so that you can add your own
-# architecture-specific flags and dependencies. Remember to do have actions
-# for "archclean" and "archdep" for cleaning up and making dependencies for
-# this architecture
-
-# If building with TILERA_ROOT set (i.e. using the Tilera Multicore
-# Development Environment) we can set CROSS_COMPILE based on that.
-# If we're not cross-compiling, make sure we're on the right architecture.
-# Only bother to test for a few common targets, to avoid useless errors.
-ifeq ($(CROSS_COMPILE),)
- ifdef TILERA_ROOT
- CROSS_COMPILE := $(TILERA_ROOT)/bin/tile-
- else
- goals := $(if $(MAKECMDGOALS), $(MAKECMDGOALS), all)
- ifneq ($(strip $(filter vmlinux modules all,$(goals))),)
- HOST_ARCH := $(shell uname -m)
- ifneq ($(HOST_ARCH),$(ARCH))
-$(error Set TILERA_ROOT or CROSS_COMPILE when building $(ARCH) on $(HOST_ARCH))
- endif
- endif
- endif
-endif
-
-# The tile compiler may emit .eh_frame information for backtracing.
-# In kernel modules, this causes load failures due to unsupported relocations.
-KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
-
-LIBGCC_PATH := \
- $(shell $(CC) $(KBUILD_CFLAGS) $(KCFLAGS) -print-libgcc-file-name)
-
-# Provide the path to use for "make defconfig".
-# We default to the newer TILE-Gx architecture if only "tile" is given.
-ifeq ($(ARCH),tile)
- KBUILD_DEFCONFIG := tilegx_defconfig
-else
- KBUILD_DEFCONFIG := $(ARCH)_defconfig
-endif
-
-# Used as a file extension when useful, e.g. head_$(BITS).o
-# Not needed for (e.g.) "$(CC) -m32" since the compiler automatically
-# uses the right default anyway.
-export BITS
-ifeq ($(CONFIG_TILEGX),y)
-BITS := 64
-else
-BITS := 32
-endif
-
-CHECKFLAGS += -m$(BITS)
-
-head-y := arch/tile/kernel/head_$(BITS).o
-
-libs-y += arch/tile/lib/
-libs-y += $(LIBGCC_PATH)
-
-# See arch/tile/Kbuild for content of core part of the kernel
-core-y += arch/tile/
-
-core-$(CONFIG_TILE_GXIO) += arch/tile/gxio/
-
-ifdef TILERA_ROOT
-INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot
-endif
-
-install:
- install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
- install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
- install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
-
-define archhelp
- echo ' install - install kernel into $(INSTALL_PATH)'
-endef
diff --git a/arch/tile/configs/tilegx_defconfig b/arch/tile/configs/tilegx_defconfig
deleted file mode 100644
index 357a4c271ad4..000000000000
--- a/arch/tile/configs/tilegx_defconfig
+++ /dev/null
@@ -1,411 +0,0 @@
-CONFIG_TILEGX=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_FHANDLE=y
-CONFIG_AUDIT=y
-CONFIG_NO_HZ=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CPUSETS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_CGROUP=y
-CONFIG_NAMESPACES=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_RD_XZ=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_EMBEDDED=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_PROFILING=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_SGI_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_CFQ_GROUP_IOSCHED=y
-CONFIG_NR_CPUS=100
-CONFIG_HZ_100=y
-# CONFIG_COMPACTION is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_TILE_PCI_IO=y
-CONFIG_PCI_DEBUG=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_NET_IPIP=m
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=m
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_NETLABEL=y
-CONFIG_RDS=m
-CONFIG_RDS_TCP=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_PHONET=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-CONFIG_NET_ACT_SIMP=m
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_CLS_IND=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_CONNECTOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_ATA_OVER_ETH=m
-CONFIG_RAID_ATTRS=m
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SAS_ATA=y
-CONFIG_ISCSI_TCP=m
-CONFIG_SCSI_MVSAS=y
-# CONFIG_SCSI_MVSAS_DEBUG is not set
-CONFIG_SCSI_MVSAS_TASKLET=y
-CONFIG_ATA=y
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_SIL24=y
-# CONFIG_ATA_SFF is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_FAULTY=m
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_DEBUG=y
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_UEVENT=y
-CONFIG_TARGET_CORE=m
-CONFIG_TCM_IBLOCK=m
-CONFIG_TCM_FILEIO=m
-CONFIG_TCM_PSCSI=m
-CONFIG_LOOPBACK_TARGET=m
-CONFIG_ISCSI_TARGET=m
-CONFIG_FUSION=y
-CONFIG_FUSION_SAS=y
-CONFIG_NETDEVICES=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_IFB=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_TUN=y
-CONFIG_VETH=m
-CONFIG_NET_DSA_MV88E6060=y
-CONFIG_NET_DSA_MV88E6XXX=y
-CONFIG_SKY2=y
-CONFIG_PTP_1588_CLOCK_TILEGX=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_TILEGX=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=m
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_VGA_ARB is not set
-CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
-CONFIG_DRM_R128=m
-CONFIG_DRM_MGA=m
-CONFIG_DRM_VIA=m
-CONFIG_DRM_SAVAGE=m
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_EDAC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TILE=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT2_FS_XIP=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_QFMT_V2=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=y
-CONFIG_CUSE=m
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-CONFIG_CACHEFILES=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_HUGETLBFS=y
-CONFIG_ECRYPT_FS=m
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_FSCACHE=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_FSCACHE=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-CONFIG_DLM_DEBUG=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_INFO_REDUCED=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_FS=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_FRAME_POINTER is not set
-CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
-CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_STACKOVERFLOW=y
-CONFIG_LOCKUP_DETECTOR=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_LIST=y
-CONFIG_DEBUG_CREDENTIALS=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_ASYNC_RAID6_TEST=m
-CONFIG_KGDB=y
-CONFIG_SECURITY=y
-CONFIG_SECURITYFS=y
-CONFIG_SECURITY_NETWORK=y
-CONFIG_SECURITY_NETWORK_XFRM=y
-CONFIG_SECURITY_SELINUX=y
-CONFIG_SECURITY_SELINUX_BOOTPARAM=y
-CONFIG_SECURITY_SELINUX_DISABLE=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CTS=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_LZO=m
diff --git a/arch/tile/configs/tilepro_defconfig b/arch/tile/configs/tilepro_defconfig
deleted file mode 100644
index da2858755fa1..000000000000
--- a/arch/tile/configs/tilepro_defconfig
+++ /dev/null
@@ -1,524 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_AUDIT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_LOG_BUF_SHIFT=19
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_DEVICE=y
-CONFIG_CPUSETS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_BLK_CGROUP=y
-CONFIG_NAMESPACES=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_RD_XZ=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_EMBEDDED=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_SGI_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_KARMA_PARTITION=y
-CONFIG_CFQ_GROUP_IOSCHED=y
-CONFIG_HZ_100=y
-# CONFIG_COMPACTION is not set
-CONFIG_PREEMPT_VOLUNTARY=y
-CONFIG_PCI_DEBUG=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_XFRM_SUB_POLICY=y
-CONFIG_XFRM_STATISTICS=y
-CONFIG_NET_KEY=m
-CONFIG_NET_KEY_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_NET_IPIP=m
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=m
-CONFIG_TCP_CONG_ADVANCED=y
-CONFIG_TCP_CONG_HSTCP=m
-CONFIG_TCP_CONG_HYBLA=m
-CONFIG_TCP_CONG_SCALABLE=m
-CONFIG_TCP_CONG_LP=m
-CONFIG_TCP_CONG_VENO=m
-CONFIG_TCP_CONG_YEAH=m
-CONFIG_TCP_CONG_ILLINOIS=m
-CONFIG_TCP_MD5SIG=y
-CONFIG_IPV6=y
-CONFIG_IPV6_ROUTER_PREF=y
-CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_IPV6_OPTIMISTIC_DAD=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_MROUTE=y
-CONFIG_IPV6_PIMSM_V2=y
-CONFIG_NETLABEL=y
-CONFIG_NETFILTER=y
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_ZONES=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_DCCP=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_DSCP=m
-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
-CONFIG_NETFILTER_XT_TARGET_TEE=m
-CONFIG_NETFILTER_XT_TARGET_TPROXY=m
-CONFIG_NETFILTER_XT_TARGET_TRACE=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
-CONFIG_NETFILTER_XT_MATCH_IPVS=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_OSF=m
-CONFIG_NETFILTER_XT_MATCH_OWNER=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_RATEEST=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_RECENT=m
-CONFIG_NETFILTER_XT_MATCH_SOCKET=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-CONFIG_IP_VS=m
-CONFIG_IP_VS_IPV6=y
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_PROTO_SCTP=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_NF_CONNTRACK_IPV4=m
-# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
-CONFIG_IP_NF_IPTABLES=y
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=y
-CONFIG_IP_NF_TARGET_REJECT=y
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_SECURITY=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-CONFIG_IP6_NF_SECURITY=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_IP6=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_BRIDGE_EBT_ULOG=m
-CONFIG_BRIDGE_EBT_NFLOG=m
-CONFIG_RDS=m
-CONFIG_RDS_TCP=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_VLAN_8021Q_GVRP=y
-CONFIG_PHONET=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_SCH_DRR=m
-CONFIG_NET_SCH_INGRESS=m
-CONFIG_NET_CLS_BASIC=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_CLS_U32_PERF=y
-CONFIG_CLS_U32_MARK=y
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
-CONFIG_NET_CLS_CGROUP=y
-CONFIG_NET_EMATCH=y
-CONFIG_NET_EMATCH_CMP=m
-CONFIG_NET_EMATCH_NBYTE=m
-CONFIG_NET_EMATCH_U32=m
-CONFIG_NET_EMATCH_META=m
-CONFIG_NET_EMATCH_TEXT=m
-CONFIG_NET_CLS_ACT=y
-CONFIG_NET_ACT_POLICE=m
-CONFIG_NET_ACT_GACT=m
-CONFIG_GACT_PROB=y
-CONFIG_NET_ACT_MIRRED=m
-CONFIG_NET_ACT_IPT=m
-CONFIG_NET_ACT_NAT=m
-CONFIG_NET_ACT_PEDIT=m
-CONFIG_NET_ACT_SIMP=m
-CONFIG_NET_ACT_SKBEDIT=m
-CONFIG_NET_CLS_IND=y
-CONFIG_DCB=y
-CONFIG_DNS_RESOLVER=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_CONNECTOR=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_SX8=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_ATA_OVER_ETH=m
-CONFIG_RAID_ATTRS=m
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_ATA=y
-CONFIG_SATA_SIL24=y
-# CONFIG_ATA_SFF is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID456=m
-CONFIG_MD_FAULTY=m
-CONFIG_BLK_DEV_DM=m
-CONFIG_DM_DEBUG=y
-CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
-CONFIG_DM_MIRROR=m
-CONFIG_DM_LOG_USERSPACE=m
-CONFIG_DM_ZERO=m
-CONFIG_DM_MULTIPATH=m
-CONFIG_DM_MULTIPATH_QL=m
-CONFIG_DM_MULTIPATH_ST=m
-CONFIG_DM_DELAY=m
-CONFIG_DM_UEVENT=y
-CONFIG_FUSION=y
-CONFIG_FUSION_SAS=y
-CONFIG_NETDEVICES=y
-CONFIG_BONDING=m
-CONFIG_DUMMY=m
-CONFIG_IFB=m
-CONFIG_MACVLAN=m
-CONFIG_MACVTAP=m
-CONFIG_NETCONSOLE=m
-CONFIG_NETCONSOLE_DYNAMIC=y
-CONFIG_TUN=y
-CONFIG_VETH=m
-CONFIG_NET_DSA_MV88E6060=y
-CONFIG_NET_DSA_MV88E6XXX=y
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_E1000E=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_TIMERIOMEM=m
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_VGA_ARB is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EDAC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_TILE=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT2_FS_XIP=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_GFS2_FS=m
-CONFIG_GFS2_FS_LOCKING_DLM=y
-CONFIG_BTRFS_FS=m
-CONFIG_BTRFS_FS_POSIX_ACL=y
-CONFIG_QUOTA=y
-CONFIG_QUOTA_NETLINK_INTERFACE=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_QFMT_V2=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=y
-CONFIG_CUSE=m
-CONFIG_FSCACHE=m
-CONFIG_FSCACHE_STATS=y
-CONFIG_CACHEFILES=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_HUGETLBFS=y
-CONFIG_CONFIGFS_FS=m
-CONFIG_ECRYPT_FS=m
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=m
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_FSCACHE=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_UPCALL=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-CONFIG_CIFS_DFS_UPCALL=y
-CONFIG_CIFS_FSCACHE=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-CONFIG_DLM_DEBUG=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_INFO_REDUCED=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_FRAME_WARN=2048
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_FS=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_FRAME_POINTER is not set
-CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_VM=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_STACKOVERFLOW=y
-CONFIG_LOCKUP_DETECTOR=y
-CONFIG_SCHEDSTATS=y
-CONFIG_TIMER_STATS=y
-CONFIG_DEBUG_LIST=y
-CONFIG_DEBUG_CREDENTIALS=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=60
-CONFIG_ASYNC_RAID6_TEST=m
-CONFIG_SECURITY=y
-CONFIG_SECURITYFS=y
-CONFIG_SECURITY_NETWORK=y
-CONFIG_SECURITY_NETWORK_XFRM=y
-CONFIG_SECURITY_SELINUX=y
-CONFIG_SECURITY_SELINUX_BOOTPARAM=y
-CONFIG_SECURITY_SELINUX_DISABLE=y
-CONFIG_CRYPTO_PCRYPT=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_CCM=m
-CONFIG_CRYPTO_GCM=m
-CONFIG_CRYPTO_CTS=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_RMD128=m
-CONFIG_CRYPTO_RMD160=m
-CONFIG_CRYPTO_RMD256=m
-CONFIG_CRYPTO_RMD320=m
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_LZO=m
-CONFIG_CRC_CCITT=m
-CONFIG_CRC7=m
diff --git a/arch/tile/gxio/Kconfig b/arch/tile/gxio/Kconfig
deleted file mode 100644
index 903c8646bdd7..000000000000
--- a/arch/tile/gxio/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# Support direct access to TILE-Gx hardware from user space, via the
-# gxio library, or from kernel space, via kernel IORPC support.
-config TILE_GXIO
- bool
- depends on TILEGX
-
-# Support direct access to the common I/O DMA facility within the
-# TILE-Gx mPIPE and Trio hardware from kernel space.
-config TILE_GXIO_DMA
- bool
- select TILE_GXIO
-
-# Support direct access to the TILE-Gx mPIPE hardware from kernel space.
-config TILE_GXIO_MPIPE
- bool
- select TILE_GXIO
- select TILE_GXIO_DMA
-
-# Support direct access to the TILE-Gx TRIO hardware from kernel space.
-config TILE_GXIO_TRIO
- bool
- select TILE_GXIO
- select TILE_GXIO_DMA
-
-# Support direct access to the TILE-Gx USB hardware from kernel space.
-config TILE_GXIO_USB_HOST
- bool
- select TILE_GXIO
-
-# Support direct access to the TILE-Gx UART hardware from kernel space.
-config TILE_GXIO_UART
- bool
- select TILE_GXIO
diff --git a/arch/tile/gxio/Makefile b/arch/tile/gxio/Makefile
deleted file mode 100644
index fcc903c4cf87..000000000000
--- a/arch/tile/gxio/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Tile-Gx device access support.
-#
-
-obj-$(CONFIG_TILE_GXIO) += iorpc_globals.o kiorpc.o
-obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o
-obj-$(CONFIG_TILE_GXIO_MPIPE) += mpipe.o iorpc_mpipe.o iorpc_mpipe_info.o
-obj-$(CONFIG_TILE_GXIO_TRIO) += trio.o iorpc_trio.o
-obj-$(CONFIG_TILE_GXIO_UART) += uart.o iorpc_uart.o
-obj-$(CONFIG_TILE_GXIO_USB_HOST) += usb_host.o iorpc_usb_host.o
diff --git a/arch/tile/gxio/dma_queue.c b/arch/tile/gxio/dma_queue.c
deleted file mode 100644
index b7ba577d82ca..000000000000
--- a/arch/tile/gxio/dma_queue.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/io.h>
-#include <linux/atomic.h>
-#include <linux/module.h>
-#include <gxio/dma_queue.h>
-
-/* Wait for a memory read to complete. */
-#define wait_for_value(val) \
- __asm__ __volatile__("move %0, %0" :: "r"(val))
-
-/* The index is in the low 16. */
-#define DMA_QUEUE_INDEX_MASK ((1 << 16) - 1)
-
-/*
- * The hardware descriptor-ring type.
- * This matches the types used by mpipe (MPIPE_EDMA_POST_REGION_VAL_t)
- * and trio (TRIO_PUSH_DMA_REGION_VAL_t or TRIO_PULL_DMA_REGION_VAL_t).
- * See those types for more documentation on the individual fields.
- */
-typedef union {
- struct {
-#ifndef __BIG_ENDIAN__
- uint64_t ring_idx:16;
- uint64_t count:16;
- uint64_t gen:1;
- uint64_t __reserved:31;
-#else
- uint64_t __reserved:31;
- uint64_t gen:1;
- uint64_t count:16;
- uint64_t ring_idx:16;
-#endif
- };
- uint64_t word;
-} __gxio_ring_t;
-
-void __gxio_dma_queue_init(__gxio_dma_queue_t *dma_queue,
- void *post_region_addr, unsigned int num_entries)
-{
- /*
- * Limit 65536 entry rings to 65535 credits because we only have a
- * 16 bit completion counter.
- */
- int64_t credits = (num_entries < 65536) ? num_entries : 65535;
-
- memset(dma_queue, 0, sizeof(*dma_queue));
-
- dma_queue->post_region_addr = post_region_addr;
- dma_queue->hw_complete_count = 0;
- dma_queue->credits_and_next_index = credits << DMA_QUEUE_CREDIT_SHIFT;
-}
-
-EXPORT_SYMBOL_GPL(__gxio_dma_queue_init);
-
-void __gxio_dma_queue_update_credits(__gxio_dma_queue_t *dma_queue)
-{
- __gxio_ring_t val;
- uint64_t count;
- uint64_t delta;
- uint64_t new_count;
-
- /*
- * Read the 64-bit completion count without touching the cache, so
- * we later avoid having to evict any sharers of this cache line
- * when we update it below.
- */
- uint64_t orig_hw_complete_count =
- cmpxchg(&dma_queue->hw_complete_count,
- -1, -1);
-
- /* Make sure the load completes before we access the hardware. */
- wait_for_value(orig_hw_complete_count);
-
- /* Read the 16-bit count of how many packets it has completed. */
- val.word = __gxio_mmio_read(dma_queue->post_region_addr);
- count = val.count;
-
- /*
- * Calculate the number of completions since we last updated the
- * 64-bit counter. It's safe to ignore the high bits because the
- * maximum credit value is 65535.
- */
- delta = (count - orig_hw_complete_count) & 0xffff;
- if (delta == 0)
- return;
-
- /*
- * Try to write back the count, advanced by delta. If we race with
- * another thread, this might fail, in which case we return
- * immediately on the assumption that some credits are (or at least
- * were) available.
- */
- new_count = orig_hw_complete_count + delta;
- if (cmpxchg(&dma_queue->hw_complete_count,
- orig_hw_complete_count,
- new_count) != orig_hw_complete_count)
- return;
-
- /*
- * We succeeded in advancing the completion count; add back the
- * corresponding number of egress credits.
- */
- __insn_fetchadd(&dma_queue->credits_and_next_index,
- (delta << DMA_QUEUE_CREDIT_SHIFT));
-}
-
-EXPORT_SYMBOL_GPL(__gxio_dma_queue_update_credits);
-
-/*
- * A separate 'blocked' method for put() so that backtraces and
- * profiles will clearly indicate that we're wasting time spinning on
- * egress availability rather than actually posting commands.
- */
-int64_t __gxio_dma_queue_wait_for_credits(__gxio_dma_queue_t *dma_queue,
- int64_t modifier)
-{
- int backoff = 16;
- int64_t old;
-
- do {
- int i;
- /* Back off to avoid spamming memory networks. */
- for (i = backoff; i > 0; i--)
- __insn_mfspr(SPR_PASS);
-
- /* Check credits again. */
- __gxio_dma_queue_update_credits(dma_queue);
- old = __insn_fetchaddgez(&dma_queue->credits_and_next_index,
- modifier);
-
- /* Calculate bounded exponential backoff for next iteration. */
- if (backoff < 256)
- backoff *= 2;
- } while (old + modifier < 0);
-
- return old;
-}
-
-EXPORT_SYMBOL_GPL(__gxio_dma_queue_wait_for_credits);
-
-int64_t __gxio_dma_queue_reserve_aux(__gxio_dma_queue_t *dma_queue,
- unsigned int num, int wait)
-{
- return __gxio_dma_queue_reserve(dma_queue, num, wait != 0, true);
-}
-
-EXPORT_SYMBOL_GPL(__gxio_dma_queue_reserve_aux);
-
-int __gxio_dma_queue_is_complete(__gxio_dma_queue_t *dma_queue,
- int64_t completion_slot, int update)
-{
- if (update) {
- if (READ_ONCE(dma_queue->hw_complete_count) >
- completion_slot)
- return 1;
-
- __gxio_dma_queue_update_credits(dma_queue);
- }
-
- return READ_ONCE(dma_queue->hw_complete_count) > completion_slot;
-}
-
-EXPORT_SYMBOL_GPL(__gxio_dma_queue_is_complete);
diff --git a/arch/tile/gxio/iorpc_globals.c b/arch/tile/gxio/iorpc_globals.c
deleted file mode 100644
index e178e90805a2..000000000000
--- a/arch/tile/gxio/iorpc_globals.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#include "gxio/iorpc_globals.h"
-
-struct arm_pollfd_param {
- union iorpc_pollfd pollfd;
-};
-
-int __iorpc_arm_pollfd(int fd, int pollfd_cookie)
-{
- struct arm_pollfd_param temp;
- struct arm_pollfd_param *params = &temp;
-
- params->pollfd.kernel.cookie = pollfd_cookie;
-
- return hv_dev_pwrite(fd, 0, (HV_VirtAddr) params, sizeof(*params),
- IORPC_OP_ARM_POLLFD);
-}
-
-EXPORT_SYMBOL(__iorpc_arm_pollfd);
-
-struct close_pollfd_param {
- union iorpc_pollfd pollfd;
-};
-
-int __iorpc_close_pollfd(int fd, int pollfd_cookie)
-{
- struct close_pollfd_param temp;
- struct close_pollfd_param *params = &temp;
-
- params->pollfd.kernel.cookie = pollfd_cookie;
-
- return hv_dev_pwrite(fd, 0, (HV_VirtAddr) params, sizeof(*params),
- IORPC_OP_CLOSE_POLLFD);
-}
-
-EXPORT_SYMBOL(__iorpc_close_pollfd);
-
-struct get_mmio_base_param {
- HV_PTE base;
-};
-
-int __iorpc_get_mmio_base(int fd, HV_PTE *base)
-{
- int __result;
- struct get_mmio_base_param temp;
- struct get_mmio_base_param *params = &temp;
-
- __result =
- hv_dev_pread(fd, 0, (HV_VirtAddr) params, sizeof(*params),
- IORPC_OP_GET_MMIO_BASE);
- *base = params->base;
-
- return __result;
-}
-
-EXPORT_SYMBOL(__iorpc_get_mmio_base);
-
-struct check_mmio_offset_param {
- unsigned long offset;
- unsigned long size;
-};
-
-int __iorpc_check_mmio_offset(int fd, unsigned long offset, unsigned long size)
-{
- struct check_mmio_offset_param temp;
- struct check_mmio_offset_param *params = &temp;
-
- params->offset = offset;
- params->size = size;
-
- return hv_dev_pwrite(fd, 0, (HV_VirtAddr) params, sizeof(*params),
- IORPC_OP_CHECK_MMIO_OFFSET);
-}
-
-EXPORT_SYMBOL(__iorpc_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_mpipe.c b/arch/tile/gxio/iorpc_mpipe.c
deleted file mode 100644
index e19325c4c431..000000000000
--- a/arch/tile/gxio/iorpc_mpipe.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#include "gxio/iorpc_mpipe.h"
-
-struct alloc_buffer_stacks_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_mpipe_alloc_buffer_stacks(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags)
-{
- struct alloc_buffer_stacks_param temp;
- struct alloc_buffer_stacks_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_ALLOC_BUFFER_STACKS);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_alloc_buffer_stacks);
-
-struct init_buffer_stack_aux_param {
- union iorpc_mem_buffer buffer;
- unsigned int stack;
- unsigned int buffer_size_enum;
-};
-
-int gxio_mpipe_init_buffer_stack_aux(gxio_mpipe_context_t *context,
- void *mem_va, size_t mem_size,
- unsigned int mem_flags, unsigned int stack,
- unsigned int buffer_size_enum)
-{
- int __result;
- unsigned long long __cpa;
- pte_t __pte;
- struct init_buffer_stack_aux_param temp;
- struct init_buffer_stack_aux_param *params = &temp;
-
- __result = va_to_cpa_and_pte(mem_va, &__cpa, &__pte);
- if (__result != 0)
- return __result;
- params->buffer.kernel.cpa = __cpa;
- params->buffer.kernel.size = mem_size;
- params->buffer.kernel.pte = __pte;
- params->buffer.kernel.flags = mem_flags;
- params->stack = stack;
- params->buffer_size_enum = buffer_size_enum;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_INIT_BUFFER_STACK_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_init_buffer_stack_aux);
-
-
-struct alloc_notif_rings_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_mpipe_alloc_notif_rings(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags)
-{
- struct alloc_notif_rings_param temp;
- struct alloc_notif_rings_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_ALLOC_NOTIF_RINGS);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_alloc_notif_rings);
-
-struct init_notif_ring_aux_param {
- union iorpc_mem_buffer buffer;
- unsigned int ring;
-};
-
-int gxio_mpipe_init_notif_ring_aux(gxio_mpipe_context_t *context, void *mem_va,
- size_t mem_size, unsigned int mem_flags,
- unsigned int ring)
-{
- int __result;
- unsigned long long __cpa;
- pte_t __pte;
- struct init_notif_ring_aux_param temp;
- struct init_notif_ring_aux_param *params = &temp;
-
- __result = va_to_cpa_and_pte(mem_va, &__cpa, &__pte);
- if (__result != 0)
- return __result;
- params->buffer.kernel.cpa = __cpa;
- params->buffer.kernel.size = mem_size;
- params->buffer.kernel.pte = __pte;
- params->buffer.kernel.flags = mem_flags;
- params->ring = ring;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_INIT_NOTIF_RING_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_init_notif_ring_aux);
-
-struct request_notif_ring_interrupt_param {
- union iorpc_interrupt interrupt;
- unsigned int ring;
-};
-
-int gxio_mpipe_request_notif_ring_interrupt(gxio_mpipe_context_t *context,
- int inter_x, int inter_y,
- int inter_ipi, int inter_event,
- unsigned int ring)
-{
- struct request_notif_ring_interrupt_param temp;
- struct request_notif_ring_interrupt_param *params = &temp;
-
- params->interrupt.kernel.x = inter_x;
- params->interrupt.kernel.y = inter_y;
- params->interrupt.kernel.ipi = inter_ipi;
- params->interrupt.kernel.event = inter_event;
- params->ring = ring;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_REQUEST_NOTIF_RING_INTERRUPT);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_request_notif_ring_interrupt);
-
-struct enable_notif_ring_interrupt_param {
- unsigned int ring;
-};
-
-int gxio_mpipe_enable_notif_ring_interrupt(gxio_mpipe_context_t *context,
- unsigned int ring)
-{
- struct enable_notif_ring_interrupt_param temp;
- struct enable_notif_ring_interrupt_param *params = &temp;
-
- params->ring = ring;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_ENABLE_NOTIF_RING_INTERRUPT);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_enable_notif_ring_interrupt);
-
-struct alloc_notif_groups_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_mpipe_alloc_notif_groups(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags)
-{
- struct alloc_notif_groups_param temp;
- struct alloc_notif_groups_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_ALLOC_NOTIF_GROUPS);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_alloc_notif_groups);
-
-struct init_notif_group_param {
- unsigned int group;
- gxio_mpipe_notif_group_bits_t bits;
-};
-
-int gxio_mpipe_init_notif_group(gxio_mpipe_context_t *context,
- unsigned int group,
- gxio_mpipe_notif_group_bits_t bits)
-{
- struct init_notif_group_param temp;
- struct init_notif_group_param *params = &temp;
-
- params->group = group;
- params->bits = bits;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_INIT_NOTIF_GROUP);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_init_notif_group);
-
-struct alloc_buckets_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_mpipe_alloc_buckets(gxio_mpipe_context_t *context, unsigned int count,
- unsigned int first, unsigned int flags)
-{
- struct alloc_buckets_param temp;
- struct alloc_buckets_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_ALLOC_BUCKETS);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_alloc_buckets);
-
-struct init_bucket_param {
- unsigned int bucket;
- MPIPE_LBL_INIT_DAT_BSTS_TBL_t bucket_info;
-};
-
-int gxio_mpipe_init_bucket(gxio_mpipe_context_t *context, unsigned int bucket,
- MPIPE_LBL_INIT_DAT_BSTS_TBL_t bucket_info)
-{
- struct init_bucket_param temp;
- struct init_bucket_param *params = &temp;
-
- params->bucket = bucket;
- params->bucket_info = bucket_info;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_INIT_BUCKET);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_init_bucket);
-
-struct alloc_edma_rings_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_mpipe_alloc_edma_rings(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags)
-{
- struct alloc_edma_rings_param temp;
- struct alloc_edma_rings_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_ALLOC_EDMA_RINGS);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_alloc_edma_rings);
-
-struct init_edma_ring_aux_param {
- union iorpc_mem_buffer buffer;
- unsigned int ring;
- unsigned int channel;
-};
-
-int gxio_mpipe_init_edma_ring_aux(gxio_mpipe_context_t *context, void *mem_va,
- size_t mem_size, unsigned int mem_flags,
- unsigned int ring, unsigned int channel)
-{
- int __result;
- unsigned long long __cpa;
- pte_t __pte;
- struct init_edma_ring_aux_param temp;
- struct init_edma_ring_aux_param *params = &temp;
-
- __result = va_to_cpa_and_pte(mem_va, &__cpa, &__pte);
- if (__result != 0)
- return __result;
- params->buffer.kernel.cpa = __cpa;
- params->buffer.kernel.size = mem_size;
- params->buffer.kernel.pte = __pte;
- params->buffer.kernel.flags = mem_flags;
- params->ring = ring;
- params->channel = channel;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_INIT_EDMA_RING_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_init_edma_ring_aux);
-
-
-int gxio_mpipe_commit_rules(gxio_mpipe_context_t *context, const void *blob,
- size_t blob_size)
-{
- const void *params = blob;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params, blob_size,
- GXIO_MPIPE_OP_COMMIT_RULES);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_commit_rules);
-
-struct register_client_memory_param {
- unsigned int iotlb;
- HV_PTE pte;
- unsigned int flags;
-};
-
-int gxio_mpipe_register_client_memory(gxio_mpipe_context_t *context,
- unsigned int iotlb, HV_PTE pte,
- unsigned int flags)
-{
- struct register_client_memory_param temp;
- struct register_client_memory_param *params = &temp;
-
- params->iotlb = iotlb;
- params->pte = pte;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_REGISTER_CLIENT_MEMORY);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_register_client_memory);
-
-struct link_open_aux_param {
- _gxio_mpipe_link_name_t name;
- unsigned int flags;
-};
-
-int gxio_mpipe_link_open_aux(gxio_mpipe_context_t *context,
- _gxio_mpipe_link_name_t name, unsigned int flags)
-{
- struct link_open_aux_param temp;
- struct link_open_aux_param *params = &temp;
-
- params->name = name;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_LINK_OPEN_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_link_open_aux);
-
-struct link_close_aux_param {
- int mac;
-};
-
-int gxio_mpipe_link_close_aux(gxio_mpipe_context_t *context, int mac)
-{
- struct link_close_aux_param temp;
- struct link_close_aux_param *params = &temp;
-
- params->mac = mac;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_LINK_CLOSE_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_link_close_aux);
-
-struct link_set_attr_aux_param {
- int mac;
- uint32_t attr;
- int64_t val;
-};
-
-int gxio_mpipe_link_set_attr_aux(gxio_mpipe_context_t *context, int mac,
- uint32_t attr, int64_t val)
-{
- struct link_set_attr_aux_param temp;
- struct link_set_attr_aux_param *params = &temp;
-
- params->mac = mac;
- params->attr = attr;
- params->val = val;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_LINK_SET_ATTR_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_link_set_attr_aux);
-
-struct get_timestamp_aux_param {
- uint64_t sec;
- uint64_t nsec;
- uint64_t cycles;
-};
-
-int gxio_mpipe_get_timestamp_aux(gxio_mpipe_context_t *context, uint64_t *sec,
- uint64_t *nsec, uint64_t *cycles)
-{
- int __result;
- struct get_timestamp_aux_param temp;
- struct get_timestamp_aux_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- GXIO_MPIPE_OP_GET_TIMESTAMP_AUX);
- *sec = params->sec;
- *nsec = params->nsec;
- *cycles = params->cycles;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_mpipe_get_timestamp_aux);
-
-struct set_timestamp_aux_param {
- uint64_t sec;
- uint64_t nsec;
- uint64_t cycles;
-};
-
-int gxio_mpipe_set_timestamp_aux(gxio_mpipe_context_t *context, uint64_t sec,
- uint64_t nsec, uint64_t cycles)
-{
- struct set_timestamp_aux_param temp;
- struct set_timestamp_aux_param *params = &temp;
-
- params->sec = sec;
- params->nsec = nsec;
- params->cycles = cycles;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_SET_TIMESTAMP_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_set_timestamp_aux);
-
-struct adjust_timestamp_aux_param {
- int64_t nsec;
-};
-
-int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t *context, int64_t nsec)
-{
- struct adjust_timestamp_aux_param temp;
- struct adjust_timestamp_aux_param *params = &temp;
-
- params->nsec = nsec;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_ADJUST_TIMESTAMP_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_aux);
-
-struct config_edma_ring_blks_param {
- unsigned int ering;
- unsigned int max_blks;
- unsigned int min_snf_blks;
- unsigned int db;
-};
-
-int gxio_mpipe_config_edma_ring_blks(gxio_mpipe_context_t *context,
- unsigned int ering, unsigned int max_blks,
- unsigned int min_snf_blks, unsigned int db)
-{
- struct config_edma_ring_blks_param temp;
- struct config_edma_ring_blks_param *params = &temp;
-
- params->ering = ering;
- params->max_blks = max_blks;
- params->min_snf_blks = min_snf_blks;
- params->db = db;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_CONFIG_EDMA_RING_BLKS);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_config_edma_ring_blks);
-
-struct adjust_timestamp_freq_param {
- int32_t ppb;
-};
-
-int gxio_mpipe_adjust_timestamp_freq(gxio_mpipe_context_t *context, int32_t ppb)
-{
- struct adjust_timestamp_freq_param temp;
- struct adjust_timestamp_freq_param *params = &temp;
-
- params->ppb = ppb;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_OP_ADJUST_TIMESTAMP_FREQ);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_freq);
-
-struct arm_pollfd_param {
- union iorpc_pollfd pollfd;
-};
-
-int gxio_mpipe_arm_pollfd(gxio_mpipe_context_t *context, int pollfd_cookie)
-{
- struct arm_pollfd_param temp;
- struct arm_pollfd_param *params = &temp;
-
- params->pollfd.kernel.cookie = pollfd_cookie;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_ARM_POLLFD);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_arm_pollfd);
-
-struct close_pollfd_param {
- union iorpc_pollfd pollfd;
-};
-
-int gxio_mpipe_close_pollfd(gxio_mpipe_context_t *context, int pollfd_cookie)
-{
- struct close_pollfd_param temp;
- struct close_pollfd_param *params = &temp;
-
- params->pollfd.kernel.cookie = pollfd_cookie;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_CLOSE_POLLFD);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_close_pollfd);
-
-struct get_mmio_base_param {
- HV_PTE base;
-};
-
-int gxio_mpipe_get_mmio_base(gxio_mpipe_context_t *context, HV_PTE *base)
-{
- int __result;
- struct get_mmio_base_param temp;
- struct get_mmio_base_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- GXIO_MPIPE_OP_GET_MMIO_BASE);
- *base = params->base;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_mpipe_get_mmio_base);
-
-struct check_mmio_offset_param {
- unsigned long offset;
- unsigned long size;
-};
-
-int gxio_mpipe_check_mmio_offset(gxio_mpipe_context_t *context,
- unsigned long offset, unsigned long size)
-{
- struct check_mmio_offset_param temp;
- struct check_mmio_offset_param *params = &temp;
-
- params->offset = offset;
- params->size = size;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_OP_CHECK_MMIO_OFFSET);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_mpipe_info.c b/arch/tile/gxio/iorpc_mpipe_info.c
deleted file mode 100644
index 77019c6e9b4a..000000000000
--- a/arch/tile/gxio/iorpc_mpipe_info.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#include "gxio/iorpc_mpipe_info.h"
-
-struct instance_aux_param {
- _gxio_mpipe_link_name_t name;
-};
-
-int gxio_mpipe_info_instance_aux(gxio_mpipe_info_context_t *context,
- _gxio_mpipe_link_name_t name)
-{
- struct instance_aux_param temp;
- struct instance_aux_param *params = &temp;
-
- params->name = name;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_MPIPE_INFO_OP_INSTANCE_AUX);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_info_instance_aux);
-
-struct enumerate_aux_param {
- _gxio_mpipe_link_name_t name;
- _gxio_mpipe_link_mac_t mac;
-};
-
-int gxio_mpipe_info_enumerate_aux(gxio_mpipe_info_context_t *context,
- unsigned int idx,
- _gxio_mpipe_link_name_t *name,
- _gxio_mpipe_link_mac_t *mac)
-{
- int __result;
- struct enumerate_aux_param temp;
- struct enumerate_aux_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- (((uint64_t)idx << 32) |
- GXIO_MPIPE_INFO_OP_ENUMERATE_AUX));
- *name = params->name;
- *mac = params->mac;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_mpipe_info_enumerate_aux);
-
-struct get_mmio_base_param {
- HV_PTE base;
-};
-
-int gxio_mpipe_info_get_mmio_base(gxio_mpipe_info_context_t *context,
- HV_PTE *base)
-{
- int __result;
- struct get_mmio_base_param temp;
- struct get_mmio_base_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- GXIO_MPIPE_INFO_OP_GET_MMIO_BASE);
- *base = params->base;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_mpipe_info_get_mmio_base);
-
-struct check_mmio_offset_param {
- unsigned long offset;
- unsigned long size;
-};
-
-int gxio_mpipe_info_check_mmio_offset(gxio_mpipe_info_context_t *context,
- unsigned long offset, unsigned long size)
-{
- struct check_mmio_offset_param temp;
- struct check_mmio_offset_param *params = &temp;
-
- params->offset = offset;
- params->size = size;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_MPIPE_INFO_OP_CHECK_MMIO_OFFSET);
-}
-
-EXPORT_SYMBOL(gxio_mpipe_info_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_trio.c b/arch/tile/gxio/iorpc_trio.c
deleted file mode 100644
index 1d3cedb9aeb4..000000000000
--- a/arch/tile/gxio/iorpc_trio.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#include "gxio/iorpc_trio.h"
-
-struct alloc_asids_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_trio_alloc_asids(gxio_trio_context_t *context, unsigned int count,
- unsigned int first, unsigned int flags)
-{
- struct alloc_asids_param temp;
- struct alloc_asids_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_ALLOC_ASIDS);
-}
-
-EXPORT_SYMBOL(gxio_trio_alloc_asids);
-
-
-struct alloc_memory_maps_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_trio_alloc_memory_maps(gxio_trio_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags)
-{
- struct alloc_memory_maps_param temp;
- struct alloc_memory_maps_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_ALLOC_MEMORY_MAPS);
-}
-
-EXPORT_SYMBOL(gxio_trio_alloc_memory_maps);
-
-struct alloc_scatter_queues_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_trio_alloc_scatter_queues(gxio_trio_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags)
-{
- struct alloc_scatter_queues_param temp;
- struct alloc_scatter_queues_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_TRIO_OP_ALLOC_SCATTER_QUEUES);
-}
-
-EXPORT_SYMBOL(gxio_trio_alloc_scatter_queues);
-
-struct alloc_pio_regions_param {
- unsigned int count;
- unsigned int first;
- unsigned int flags;
-};
-
-int gxio_trio_alloc_pio_regions(gxio_trio_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags)
-{
- struct alloc_pio_regions_param temp;
- struct alloc_pio_regions_param *params = &temp;
-
- params->count = count;
- params->first = first;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_ALLOC_PIO_REGIONS);
-}
-
-EXPORT_SYMBOL(gxio_trio_alloc_pio_regions);
-
-struct init_pio_region_aux_param {
- unsigned int pio_region;
- unsigned int mac;
- uint32_t bus_address_hi;
- unsigned int flags;
-};
-
-int gxio_trio_init_pio_region_aux(gxio_trio_context_t *context,
- unsigned int pio_region, unsigned int mac,
- uint32_t bus_address_hi, unsigned int flags)
-{
- struct init_pio_region_aux_param temp;
- struct init_pio_region_aux_param *params = &temp;
-
- params->pio_region = pio_region;
- params->mac = mac;
- params->bus_address_hi = bus_address_hi;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_INIT_PIO_REGION_AUX);
-}
-
-EXPORT_SYMBOL(gxio_trio_init_pio_region_aux);
-
-
-struct init_memory_map_mmu_aux_param {
- unsigned int map;
- unsigned long va;
- uint64_t size;
- unsigned int asid;
- unsigned int mac;
- uint64_t bus_address;
- unsigned int node;
- unsigned int order_mode;
-};
-
-int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t *context,
- unsigned int map, unsigned long va,
- uint64_t size, unsigned int asid,
- unsigned int mac, uint64_t bus_address,
- unsigned int node,
- unsigned int order_mode)
-{
- struct init_memory_map_mmu_aux_param temp;
- struct init_memory_map_mmu_aux_param *params = &temp;
-
- params->map = map;
- params->va = va;
- params->size = size;
- params->asid = asid;
- params->mac = mac;
- params->bus_address = bus_address;
- params->node = node;
- params->order_mode = order_mode;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX);
-}
-
-EXPORT_SYMBOL(gxio_trio_init_memory_map_mmu_aux);
-
-struct get_port_property_param {
- struct pcie_trio_ports_property trio_ports;
-};
-
-int gxio_trio_get_port_property(gxio_trio_context_t *context,
- struct pcie_trio_ports_property *trio_ports)
-{
- int __result;
- struct get_port_property_param temp;
- struct get_port_property_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- GXIO_TRIO_OP_GET_PORT_PROPERTY);
- *trio_ports = params->trio_ports;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_trio_get_port_property);
-
-struct config_legacy_intr_param {
- union iorpc_interrupt interrupt;
- unsigned int mac;
- unsigned int intx;
-};
-
-int gxio_trio_config_legacy_intr(gxio_trio_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event,
- unsigned int mac, unsigned int intx)
-{
- struct config_legacy_intr_param temp;
- struct config_legacy_intr_param *params = &temp;
-
- params->interrupt.kernel.x = inter_x;
- params->interrupt.kernel.y = inter_y;
- params->interrupt.kernel.ipi = inter_ipi;
- params->interrupt.kernel.event = inter_event;
- params->mac = mac;
- params->intx = intx;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_CONFIG_LEGACY_INTR);
-}
-
-EXPORT_SYMBOL(gxio_trio_config_legacy_intr);
-
-struct config_msi_intr_param {
- union iorpc_interrupt interrupt;
- unsigned int mac;
- unsigned int mem_map;
- uint64_t mem_map_base;
- uint64_t mem_map_limit;
- unsigned int asid;
-};
-
-int gxio_trio_config_msi_intr(gxio_trio_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event,
- unsigned int mac, unsigned int mem_map,
- uint64_t mem_map_base, uint64_t mem_map_limit,
- unsigned int asid)
-{
- struct config_msi_intr_param temp;
- struct config_msi_intr_param *params = &temp;
-
- params->interrupt.kernel.x = inter_x;
- params->interrupt.kernel.y = inter_y;
- params->interrupt.kernel.ipi = inter_ipi;
- params->interrupt.kernel.event = inter_event;
- params->mac = mac;
- params->mem_map = mem_map;
- params->mem_map_base = mem_map_base;
- params->mem_map_limit = mem_map_limit;
- params->asid = asid;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_CONFIG_MSI_INTR);
-}
-
-EXPORT_SYMBOL(gxio_trio_config_msi_intr);
-
-
-struct set_mps_mrs_param {
- uint16_t mps;
- uint16_t mrs;
- unsigned int mac;
-};
-
-int gxio_trio_set_mps_mrs(gxio_trio_context_t *context, uint16_t mps,
- uint16_t mrs, unsigned int mac)
-{
- struct set_mps_mrs_param temp;
- struct set_mps_mrs_param *params = &temp;
-
- params->mps = mps;
- params->mrs = mrs;
- params->mac = mac;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_SET_MPS_MRS);
-}
-
-EXPORT_SYMBOL(gxio_trio_set_mps_mrs);
-
-struct force_rc_link_up_param {
- unsigned int mac;
-};
-
-int gxio_trio_force_rc_link_up(gxio_trio_context_t *context, unsigned int mac)
-{
- struct force_rc_link_up_param temp;
- struct force_rc_link_up_param *params = &temp;
-
- params->mac = mac;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_FORCE_RC_LINK_UP);
-}
-
-EXPORT_SYMBOL(gxio_trio_force_rc_link_up);
-
-struct force_ep_link_up_param {
- unsigned int mac;
-};
-
-int gxio_trio_force_ep_link_up(gxio_trio_context_t *context, unsigned int mac)
-{
- struct force_ep_link_up_param temp;
- struct force_ep_link_up_param *params = &temp;
-
- params->mac = mac;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_FORCE_EP_LINK_UP);
-}
-
-EXPORT_SYMBOL(gxio_trio_force_ep_link_up);
-
-struct get_mmio_base_param {
- HV_PTE base;
-};
-
-int gxio_trio_get_mmio_base(gxio_trio_context_t *context, HV_PTE *base)
-{
- int __result;
- struct get_mmio_base_param temp;
- struct get_mmio_base_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- GXIO_TRIO_OP_GET_MMIO_BASE);
- *base = params->base;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_trio_get_mmio_base);
-
-struct check_mmio_offset_param {
- unsigned long offset;
- unsigned long size;
-};
-
-int gxio_trio_check_mmio_offset(gxio_trio_context_t *context,
- unsigned long offset, unsigned long size)
-{
- struct check_mmio_offset_param temp;
- struct check_mmio_offset_param *params = &temp;
-
- params->offset = offset;
- params->size = size;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_TRIO_OP_CHECK_MMIO_OFFSET);
-}
-
-EXPORT_SYMBOL(gxio_trio_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_uart.c b/arch/tile/gxio/iorpc_uart.c
deleted file mode 100644
index b9a6d6193d73..000000000000
--- a/arch/tile/gxio/iorpc_uart.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#include "gxio/iorpc_uart.h"
-
-struct cfg_interrupt_param {
- union iorpc_interrupt interrupt;
-};
-
-int gxio_uart_cfg_interrupt(gxio_uart_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event)
-{
- struct cfg_interrupt_param temp;
- struct cfg_interrupt_param *params = &temp;
-
- params->interrupt.kernel.x = inter_x;
- params->interrupt.kernel.y = inter_y;
- params->interrupt.kernel.ipi = inter_ipi;
- params->interrupt.kernel.event = inter_event;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_UART_OP_CFG_INTERRUPT);
-}
-
-EXPORT_SYMBOL(gxio_uart_cfg_interrupt);
-
-struct get_mmio_base_param {
- HV_PTE base;
-};
-
-int gxio_uart_get_mmio_base(gxio_uart_context_t *context, HV_PTE *base)
-{
- int __result;
- struct get_mmio_base_param temp;
- struct get_mmio_base_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- GXIO_UART_OP_GET_MMIO_BASE);
- *base = params->base;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_uart_get_mmio_base);
-
-struct check_mmio_offset_param {
- unsigned long offset;
- unsigned long size;
-};
-
-int gxio_uart_check_mmio_offset(gxio_uart_context_t *context,
- unsigned long offset, unsigned long size)
-{
- struct check_mmio_offset_param temp;
- struct check_mmio_offset_param *params = &temp;
-
- params->offset = offset;
- params->size = size;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_UART_OP_CHECK_MMIO_OFFSET);
-}
-
-EXPORT_SYMBOL(gxio_uart_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_usb_host.c b/arch/tile/gxio/iorpc_usb_host.c
deleted file mode 100644
index 9c820073bfc0..000000000000
--- a/arch/tile/gxio/iorpc_usb_host.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#include "gxio/iorpc_usb_host.h"
-
-struct cfg_interrupt_param {
- union iorpc_interrupt interrupt;
-};
-
-int gxio_usb_host_cfg_interrupt(gxio_usb_host_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event)
-{
- struct cfg_interrupt_param temp;
- struct cfg_interrupt_param *params = &temp;
-
- params->interrupt.kernel.x = inter_x;
- params->interrupt.kernel.y = inter_y;
- params->interrupt.kernel.ipi = inter_ipi;
- params->interrupt.kernel.event = inter_event;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params), GXIO_USB_HOST_OP_CFG_INTERRUPT);
-}
-
-EXPORT_SYMBOL(gxio_usb_host_cfg_interrupt);
-
-struct register_client_memory_param {
- HV_PTE pte;
- unsigned int flags;
-};
-
-int gxio_usb_host_register_client_memory(gxio_usb_host_context_t *context,
- HV_PTE pte, unsigned int flags)
-{
- struct register_client_memory_param temp;
- struct register_client_memory_param *params = &temp;
-
- params->pte = pte;
- params->flags = flags;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_USB_HOST_OP_REGISTER_CLIENT_MEMORY);
-}
-
-EXPORT_SYMBOL(gxio_usb_host_register_client_memory);
-
-struct get_mmio_base_param {
- HV_PTE base;
-};
-
-int gxio_usb_host_get_mmio_base(gxio_usb_host_context_t *context, HV_PTE *base)
-{
- int __result;
- struct get_mmio_base_param temp;
- struct get_mmio_base_param *params = &temp;
-
- __result =
- hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
- GXIO_USB_HOST_OP_GET_MMIO_BASE);
- *base = params->base;
-
- return __result;
-}
-
-EXPORT_SYMBOL(gxio_usb_host_get_mmio_base);
-
-struct check_mmio_offset_param {
- unsigned long offset;
- unsigned long size;
-};
-
-int gxio_usb_host_check_mmio_offset(gxio_usb_host_context_t *context,
- unsigned long offset, unsigned long size)
-{
- struct check_mmio_offset_param temp;
- struct check_mmio_offset_param *params = &temp;
-
- params->offset = offset;
- params->size = size;
-
- return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
- sizeof(*params),
- GXIO_USB_HOST_OP_CHECK_MMIO_OFFSET);
-}
-
-EXPORT_SYMBOL(gxio_usb_host_check_mmio_offset);
diff --git a/arch/tile/gxio/kiorpc.c b/arch/tile/gxio/kiorpc.c
deleted file mode 100644
index c8096aa5a3fc..000000000000
--- a/arch/tile/gxio/kiorpc.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE-Gx IORPC support for kernel I/O drivers.
- */
-
-#include <linux/mmzone.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <gxio/iorpc_globals.h>
-#include <gxio/kiorpc.h>
-
-#ifdef DEBUG_IORPC
-#define TRACE(FMT, ...) pr_info(SIMPLE_MSG_LINE FMT, ## __VA_ARGS__)
-#else
-#define TRACE(...)
-#endif
-
-/* Create kernel-VA-space MMIO mapping for an on-chip IO device. */
-void __iomem *iorpc_ioremap(int hv_fd, resource_size_t offset,
- unsigned long size)
-{
- pgprot_t mmio_base, prot = { 0 };
- unsigned long pfn;
- int err;
-
- /* Look up the shim's lotar and base PA. */
- err = __iorpc_get_mmio_base(hv_fd, &mmio_base);
- if (err) {
- TRACE("get_mmio_base() failure: %d\n", err);
- return NULL;
- }
-
- /* Make sure the HV driver approves of our offset and size. */
- err = __iorpc_check_mmio_offset(hv_fd, offset, size);
- if (err) {
- TRACE("check_mmio_offset() failure: %d\n", err);
- return NULL;
- }
-
- /*
- * mmio_base contains a base pfn and homing coordinates. Turn
- * it into an MMIO pgprot and offset pfn.
- */
- prot = hv_pte_set_lotar(prot, hv_pte_get_lotar(mmio_base));
- pfn = pte_pfn(mmio_base) + PFN_DOWN(offset);
-
- return ioremap_prot(PFN_PHYS(pfn), size, prot);
-}
-
-EXPORT_SYMBOL(iorpc_ioremap);
diff --git a/arch/tile/gxio/mpipe.c b/arch/tile/gxio/mpipe.c
deleted file mode 100644
index 34de300ab320..000000000000
--- a/arch/tile/gxio/mpipe.c
+++ /dev/null
@@ -1,584 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * Implementation of mpipe gxio calls.
- */
-
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/string.h>
-
-#include <gxio/iorpc_globals.h>
-#include <gxio/iorpc_mpipe.h>
-#include <gxio/iorpc_mpipe_info.h>
-#include <gxio/kiorpc.h>
-#include <gxio/mpipe.h>
-
-/* HACK: Avoid pointless "shadow" warnings. */
-#define link link_shadow
-
-int gxio_mpipe_init(gxio_mpipe_context_t *context, unsigned int mpipe_index)
-{
- char file[32];
-
- int fd;
- int i;
-
- if (mpipe_index >= GXIO_MPIPE_INSTANCE_MAX)
- return -EINVAL;
-
- snprintf(file, sizeof(file), "mpipe/%d/iorpc", mpipe_index);
- fd = hv_dev_open((HV_VirtAddr) file, 0);
-
- context->fd = fd;
-
- if (fd < 0) {
- if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
- return fd;
- else
- return -ENODEV;
- }
-
- /* Map in the MMIO space. */
- context->mmio_cfg_base = (void __force *)
- iorpc_ioremap(fd, HV_MPIPE_CONFIG_MMIO_OFFSET,
- HV_MPIPE_CONFIG_MMIO_SIZE);
- if (context->mmio_cfg_base == NULL)
- goto cfg_failed;
-
- context->mmio_fast_base = (void __force *)
- iorpc_ioremap(fd, HV_MPIPE_FAST_MMIO_OFFSET,
- HV_MPIPE_FAST_MMIO_SIZE);
- if (context->mmio_fast_base == NULL)
- goto fast_failed;
-
- /* Initialize the stacks. */
- for (i = 0; i < 8; i++)
- context->__stacks.stacks[i] = 255;
-
- context->instance = mpipe_index;
-
- return 0;
-
- fast_failed:
- iounmap((void __force __iomem *)(context->mmio_cfg_base));
- cfg_failed:
- hv_dev_close(context->fd);
- context->fd = -1;
- return -ENODEV;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_init);
-
-int gxio_mpipe_destroy(gxio_mpipe_context_t *context)
-{
- iounmap((void __force __iomem *)(context->mmio_cfg_base));
- iounmap((void __force __iomem *)(context->mmio_fast_base));
- return hv_dev_close(context->fd);
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_destroy);
-
-static int16_t gxio_mpipe_buffer_sizes[8] =
- { 128, 256, 512, 1024, 1664, 4096, 10368, 16384 };
-
-gxio_mpipe_buffer_size_enum_t gxio_mpipe_buffer_size_to_buffer_size_enum(size_t
- size)
-{
- int i;
- for (i = 0; i < 7; i++)
- if (size <= gxio_mpipe_buffer_sizes[i])
- break;
- return i;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_buffer_size_to_buffer_size_enum);
-
-size_t gxio_mpipe_buffer_size_enum_to_buffer_size(gxio_mpipe_buffer_size_enum_t
- buffer_size_enum)
-{
- if (buffer_size_enum > 7)
- buffer_size_enum = 7;
-
- return gxio_mpipe_buffer_sizes[buffer_size_enum];
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_buffer_size_enum_to_buffer_size);
-
-size_t gxio_mpipe_calc_buffer_stack_bytes(unsigned long buffers)
-{
- const int BUFFERS_PER_LINE = 12;
-
- /* Count the number of cachelines. */
- unsigned long lines =
- (buffers + BUFFERS_PER_LINE - 1) / BUFFERS_PER_LINE;
-
- /* Convert to bytes. */
- return lines * CHIP_L2_LINE_SIZE();
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_calc_buffer_stack_bytes);
-
-int gxio_mpipe_init_buffer_stack(gxio_mpipe_context_t *context,
- unsigned int stack,
- gxio_mpipe_buffer_size_enum_t
- buffer_size_enum, void *mem, size_t mem_size,
- unsigned int mem_flags)
-{
- int result;
-
- memset(mem, 0, mem_size);
-
- result = gxio_mpipe_init_buffer_stack_aux(context, mem, mem_size,
- mem_flags, stack,
- buffer_size_enum);
- if (result < 0)
- return result;
-
- /* Save the stack. */
- context->__stacks.stacks[buffer_size_enum] = stack;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_init_buffer_stack);
-
-int gxio_mpipe_init_notif_ring(gxio_mpipe_context_t *context,
- unsigned int ring,
- void *mem, size_t mem_size,
- unsigned int mem_flags)
-{
- return gxio_mpipe_init_notif_ring_aux(context, mem, mem_size,
- mem_flags, ring);
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_init_notif_ring);
-
-int gxio_mpipe_init_notif_group_and_buckets(gxio_mpipe_context_t *context,
- unsigned int group,
- unsigned int ring,
- unsigned int num_rings,
- unsigned int bucket,
- unsigned int num_buckets,
- gxio_mpipe_bucket_mode_t mode)
-{
- int i;
- int result;
-
- gxio_mpipe_bucket_info_t bucket_info = { {
- .group = group,
- .mode = mode,
- }
- };
-
- gxio_mpipe_notif_group_bits_t bits = { {0} };
-
- for (i = 0; i < num_rings; i++)
- gxio_mpipe_notif_group_add_ring(&bits, ring + i);
-
- result = gxio_mpipe_init_notif_group(context, group, bits);
- if (result != 0)
- return result;
-
- for (i = 0; i < num_buckets; i++) {
- bucket_info.notifring = ring + (i % num_rings);
-
- result = gxio_mpipe_init_bucket(context, bucket + i,
- bucket_info);
- if (result != 0)
- return result;
- }
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_init_notif_group_and_buckets);
-
-int gxio_mpipe_init_edma_ring(gxio_mpipe_context_t *context,
- unsigned int ring, unsigned int channel,
- void *mem, size_t mem_size,
- unsigned int mem_flags)
-{
- memset(mem, 0, mem_size);
-
- return gxio_mpipe_init_edma_ring_aux(context, mem, mem_size, mem_flags,
- ring, channel);
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_init_edma_ring);
-
-void gxio_mpipe_rules_init(gxio_mpipe_rules_t *rules,
- gxio_mpipe_context_t *context)
-{
- rules->context = context;
- memset(&rules->list, 0, sizeof(rules->list));
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_rules_init);
-
-int gxio_mpipe_rules_begin(gxio_mpipe_rules_t *rules,
- unsigned int bucket, unsigned int num_buckets,
- gxio_mpipe_rules_stacks_t *stacks)
-{
- int i;
- int stack = 255;
-
- gxio_mpipe_rules_list_t *list = &rules->list;
-
- /* Current rule. */
- gxio_mpipe_rules_rule_t *rule =
- (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
-
- unsigned int head = list->tail;
-
- /*
- * Align next rule properly.
- *Note that "dmacs_and_vlans" will also be aligned.
- */
- unsigned int pad = 0;
- while (((head + pad) % __alignof__(gxio_mpipe_rules_rule_t)) != 0)
- pad++;
-
- /*
- * Verify room.
- * ISSUE: Mark rules as broken on error?
- */
- if (head + pad + sizeof(*rule) >= sizeof(list->rules))
- return GXIO_MPIPE_ERR_RULES_FULL;
-
- /* Verify num_buckets is a power of 2. */
- if (__builtin_popcount(num_buckets) != 1)
- return GXIO_MPIPE_ERR_RULES_INVALID;
-
- /* Add padding to previous rule. */
- rule->size += pad;
-
- /* Start a new rule. */
- list->head = head + pad;
-
- rule = (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
-
- /* Default some values. */
- rule->headroom = 2;
- rule->tailroom = 0;
- rule->capacity = 16384;
-
- /* Save the bucket info. */
- rule->bucket_mask = num_buckets - 1;
- rule->bucket_first = bucket;
-
- for (i = 8 - 1; i >= 0; i--) {
- int maybe =
- stacks ? stacks->stacks[i] : rules->context->__stacks.
- stacks[i];
- if (maybe != 255)
- stack = maybe;
- rule->stacks.stacks[i] = stack;
- }
-
- if (stack == 255)
- return GXIO_MPIPE_ERR_RULES_INVALID;
-
- /* NOTE: Only entries at the end of the array can be 255. */
- for (i = 8 - 1; i > 0; i--) {
- if (rule->stacks.stacks[i] == 255) {
- rule->stacks.stacks[i] = stack;
- rule->capacity =
- gxio_mpipe_buffer_size_enum_to_buffer_size(i -
- 1);
- }
- }
-
- rule->size = sizeof(*rule);
- list->tail = list->head + rule->size;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_rules_begin);
-
-int gxio_mpipe_rules_add_channel(gxio_mpipe_rules_t *rules,
- unsigned int channel)
-{
- gxio_mpipe_rules_list_t *list = &rules->list;
-
- gxio_mpipe_rules_rule_t *rule =
- (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
-
- /* Verify channel. */
- if (channel >= 32)
- return GXIO_MPIPE_ERR_RULES_INVALID;
-
- /* Verify begun. */
- if (list->tail == 0)
- return GXIO_MPIPE_ERR_RULES_EMPTY;
-
- rule->channel_bits |= (1UL << channel);
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_rules_add_channel);
-
-int gxio_mpipe_rules_set_headroom(gxio_mpipe_rules_t *rules, uint8_t headroom)
-{
- gxio_mpipe_rules_list_t *list = &rules->list;
-
- gxio_mpipe_rules_rule_t *rule =
- (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
-
- /* Verify begun. */
- if (list->tail == 0)
- return GXIO_MPIPE_ERR_RULES_EMPTY;
-
- rule->headroom = headroom;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_rules_set_headroom);
-
-int gxio_mpipe_rules_commit(gxio_mpipe_rules_t *rules)
-{
- gxio_mpipe_rules_list_t *list = &rules->list;
- unsigned int size =
- offsetof(gxio_mpipe_rules_list_t, rules) + list->tail;
- return gxio_mpipe_commit_rules(rules->context, list, size);
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_rules_commit);
-
-int gxio_mpipe_iqueue_init(gxio_mpipe_iqueue_t *iqueue,
- gxio_mpipe_context_t *context,
- unsigned int ring,
- void *mem, size_t mem_size, unsigned int mem_flags)
-{
- /* The init call below will verify that "mem_size" is legal. */
- unsigned int num_entries = mem_size / sizeof(gxio_mpipe_idesc_t);
-
- iqueue->context = context;
- iqueue->idescs = (gxio_mpipe_idesc_t *)mem;
- iqueue->ring = ring;
- iqueue->num_entries = num_entries;
- iqueue->mask_num_entries = num_entries - 1;
- iqueue->log2_num_entries = __builtin_ctz(num_entries);
- iqueue->head = 1;
-#ifdef __BIG_ENDIAN__
- iqueue->swapped = 0;
-#endif
-
- /* Initialize the "tail". */
- __gxio_mmio_write(mem, iqueue->head);
-
- return gxio_mpipe_init_notif_ring(context, ring, mem, mem_size,
- mem_flags);
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_iqueue_init);
-
-int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
- gxio_mpipe_context_t *context,
- unsigned int ering,
- unsigned int channel,
- void *mem, unsigned int mem_size,
- unsigned int mem_flags)
-{
- /* The init call below will verify that "mem_size" is legal. */
- unsigned int num_entries = mem_size / sizeof(gxio_mpipe_edesc_t);
-
- /* Offset used to read number of completed commands. */
- MPIPE_EDMA_POST_REGION_ADDR_t offset;
-
- int result = gxio_mpipe_init_edma_ring(context, ering, channel,
- mem, mem_size, mem_flags);
- if (result < 0)
- return result;
-
- memset(equeue, 0, sizeof(*equeue));
-
- offset.word = 0;
- offset.region =
- MPIPE_MMIO_ADDR__REGION_VAL_EDMA -
- MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
- offset.ring = ering;
-
- __gxio_dma_queue_init(&equeue->dma_queue,
- context->mmio_fast_base + offset.word,
- num_entries);
- equeue->edescs = mem;
- equeue->mask_num_entries = num_entries - 1;
- equeue->log2_num_entries = __builtin_ctz(num_entries);
- equeue->context = context;
- equeue->ering = ering;
- equeue->channel = channel;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_equeue_init);
-
-int gxio_mpipe_set_timestamp(gxio_mpipe_context_t *context,
- const struct timespec64 *ts)
-{
- cycles_t cycles = get_cycles();
- return gxio_mpipe_set_timestamp_aux(context, (uint64_t)ts->tv_sec,
- (uint64_t)ts->tv_nsec,
- (uint64_t)cycles);
-}
-EXPORT_SYMBOL_GPL(gxio_mpipe_set_timestamp);
-
-int gxio_mpipe_get_timestamp(gxio_mpipe_context_t *context,
- struct timespec64 *ts)
-{
- int ret;
- cycles_t cycles_prev, cycles_now, clock_rate;
- cycles_prev = get_cycles();
- ret = gxio_mpipe_get_timestamp_aux(context, (uint64_t *)&ts->tv_sec,
- (uint64_t *)&ts->tv_nsec,
- (uint64_t *)&cycles_now);
- if (ret < 0) {
- return ret;
- }
-
- clock_rate = get_clock_rate();
- ts->tv_nsec -= (cycles_now - cycles_prev) * 1000000000LL / clock_rate;
- if (ts->tv_nsec < 0) {
- ts->tv_nsec += 1000000000LL;
- ts->tv_sec -= 1;
- }
- return ret;
-}
-EXPORT_SYMBOL_GPL(gxio_mpipe_get_timestamp);
-
-int gxio_mpipe_adjust_timestamp(gxio_mpipe_context_t *context, int64_t delta)
-{
- return gxio_mpipe_adjust_timestamp_aux(context, delta);
-}
-EXPORT_SYMBOL_GPL(gxio_mpipe_adjust_timestamp);
-
-/* Get our internal context used for link name access. This context is
- * special in that it is not associated with an mPIPE service domain.
- */
-static gxio_mpipe_context_t *_gxio_get_link_context(void)
-{
- static gxio_mpipe_context_t context;
- static gxio_mpipe_context_t *contextp;
- static int tried_open = 0;
- static DEFINE_MUTEX(mutex);
-
- mutex_lock(&mutex);
-
- if (!tried_open) {
- int i = 0;
- tried_open = 1;
-
- /*
- * "4" here is the maximum possible number of mPIPE shims; it's
- * an exaggeration but we shouldn't ever go beyond 2 anyway.
- */
- for (i = 0; i < 4; i++) {
- char file[80];
-
- snprintf(file, sizeof(file), "mpipe/%d/iorpc_info", i);
- context.fd = hv_dev_open((HV_VirtAddr) file, 0);
- if (context.fd < 0)
- continue;
-
- contextp = &context;
- break;
- }
- }
-
- mutex_unlock(&mutex);
-
- return contextp;
-}
-
-int gxio_mpipe_link_instance(const char *link_name)
-{
- _gxio_mpipe_link_name_t name;
- gxio_mpipe_context_t *context = _gxio_get_link_context();
-
- if (!context)
- return GXIO_ERR_NO_DEVICE;
-
- if (strscpy(name.name, link_name, sizeof(name.name)) < 0)
- return GXIO_ERR_NO_DEVICE;
-
- return gxio_mpipe_info_instance_aux(context, name);
-}
-EXPORT_SYMBOL_GPL(gxio_mpipe_link_instance);
-
-int gxio_mpipe_link_enumerate_mac(int idx, char *link_name, uint8_t *link_mac)
-{
- int rv;
- _gxio_mpipe_link_name_t name;
- _gxio_mpipe_link_mac_t mac;
-
- gxio_mpipe_context_t *context = _gxio_get_link_context();
- if (!context)
- return GXIO_ERR_NO_DEVICE;
-
- rv = gxio_mpipe_info_enumerate_aux(context, idx, &name, &mac);
- if (rv >= 0) {
- if (strscpy(link_name, name.name, sizeof(name.name)) < 0)
- return GXIO_ERR_INVAL_MEMORY_SIZE;
- memcpy(link_mac, mac.mac, sizeof(mac.mac));
- }
-
- return rv;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_link_enumerate_mac);
-
-int gxio_mpipe_link_open(gxio_mpipe_link_t *link,
- gxio_mpipe_context_t *context, const char *link_name,
- unsigned int flags)
-{
- _gxio_mpipe_link_name_t name;
- int rv;
-
- if (strscpy(name.name, link_name, sizeof(name.name)) < 0)
- return GXIO_ERR_NO_DEVICE;
-
- rv = gxio_mpipe_link_open_aux(context, name, flags);
- if (rv < 0)
- return rv;
-
- link->context = context;
- link->channel = rv >> 8;
- link->mac = rv & 0xFF;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_link_open);
-
-int gxio_mpipe_link_close(gxio_mpipe_link_t *link)
-{
- return gxio_mpipe_link_close_aux(link->context, link->mac);
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_link_close);
-
-int gxio_mpipe_link_set_attr(gxio_mpipe_link_t *link, uint32_t attr,
- int64_t val)
-{
- return gxio_mpipe_link_set_attr_aux(link->context, link->mac, attr,
- val);
-}
-
-EXPORT_SYMBOL_GPL(gxio_mpipe_link_set_attr);
diff --git a/arch/tile/gxio/trio.c b/arch/tile/gxio/trio.c
deleted file mode 100644
index 69f0b8df3ce3..000000000000
--- a/arch/tile/gxio/trio.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * Implementation of trio gxio calls.
- */
-
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/module.h>
-
-#include <gxio/trio.h>
-#include <gxio/iorpc_globals.h>
-#include <gxio/iorpc_trio.h>
-#include <gxio/kiorpc.h>
-
-int gxio_trio_init(gxio_trio_context_t *context, unsigned int trio_index)
-{
- char file[32];
- int fd;
-
- snprintf(file, sizeof(file), "trio/%d/iorpc", trio_index);
- fd = hv_dev_open((HV_VirtAddr) file, 0);
- if (fd < 0) {
- context->fd = -1;
-
- if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
- return fd;
- else
- return -ENODEV;
- }
-
- context->fd = fd;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_trio_init);
diff --git a/arch/tile/gxio/uart.c b/arch/tile/gxio/uart.c
deleted file mode 100644
index ba585175ef88..000000000000
--- a/arch/tile/gxio/uart.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * Implementation of UART gxio calls.
- */
-
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-
-#include <gxio/uart.h>
-#include <gxio/iorpc_globals.h>
-#include <gxio/iorpc_uart.h>
-#include <gxio/kiorpc.h>
-
-int gxio_uart_init(gxio_uart_context_t *context, int uart_index)
-{
- char file[32];
- int fd;
-
- snprintf(file, sizeof(file), "uart/%d/iorpc", uart_index);
- fd = hv_dev_open((HV_VirtAddr) file, 0);
- if (fd < 0) {
- if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
- return fd;
- else
- return -ENODEV;
- }
-
- context->fd = fd;
-
- /* Map in the MMIO space. */
- context->mmio_base = (void __force *)
- iorpc_ioremap(fd, HV_UART_MMIO_OFFSET, HV_UART_MMIO_SIZE);
-
- if (context->mmio_base == NULL) {
- hv_dev_close(context->fd);
- context->fd = -1;
- return -ENODEV;
- }
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_uart_init);
-
-int gxio_uart_destroy(gxio_uart_context_t *context)
-{
- iounmap((void __force __iomem *)(context->mmio_base));
- hv_dev_close(context->fd);
-
- context->mmio_base = NULL;
- context->fd = -1;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_uart_destroy);
-
-/* UART register write wrapper. */
-void gxio_uart_write(gxio_uart_context_t *context, uint64_t offset,
- uint64_t word)
-{
- __gxio_mmio_write(context->mmio_base + offset, word);
-}
-
-EXPORT_SYMBOL_GPL(gxio_uart_write);
-
-/* UART register read wrapper. */
-uint64_t gxio_uart_read(gxio_uart_context_t *context, uint64_t offset)
-{
- return __gxio_mmio_read(context->mmio_base + offset);
-}
-
-EXPORT_SYMBOL_GPL(gxio_uart_read);
diff --git a/arch/tile/gxio/usb_host.c b/arch/tile/gxio/usb_host.c
deleted file mode 100644
index 785afad7922e..000000000000
--- a/arch/tile/gxio/usb_host.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- *
- * Implementation of USB gxio calls.
- */
-
-#include <linux/io.h>
-#include <linux/errno.h>
-#include <linux/module.h>
-
-#include <gxio/iorpc_globals.h>
-#include <gxio/iorpc_usb_host.h>
-#include <gxio/kiorpc.h>
-#include <gxio/usb_host.h>
-
-int gxio_usb_host_init(gxio_usb_host_context_t *context, int usb_index,
- int is_ehci)
-{
- char file[32];
- int fd;
-
- if (is_ehci)
- snprintf(file, sizeof(file), "usb_host/%d/iorpc/ehci",
- usb_index);
- else
- snprintf(file, sizeof(file), "usb_host/%d/iorpc/ohci",
- usb_index);
-
- fd = hv_dev_open((HV_VirtAddr) file, 0);
- if (fd < 0) {
- if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
- return fd;
- else
- return -ENODEV;
- }
-
- context->fd = fd;
-
- // Map in the MMIO space.
- context->mmio_base =
- (void __force *)iorpc_ioremap(fd, 0, HV_USB_HOST_MMIO_SIZE);
-
- if (context->mmio_base == NULL) {
- hv_dev_close(context->fd);
- return -ENODEV;
- }
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_usb_host_init);
-
-int gxio_usb_host_destroy(gxio_usb_host_context_t *context)
-{
- iounmap((void __force __iomem *)(context->mmio_base));
- hv_dev_close(context->fd);
-
- context->mmio_base = NULL;
- context->fd = -1;
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(gxio_usb_host_destroy);
-
-void *gxio_usb_host_get_reg_start(gxio_usb_host_context_t *context)
-{
- return context->mmio_base;
-}
-
-EXPORT_SYMBOL_GPL(gxio_usb_host_get_reg_start);
-
-size_t gxio_usb_host_get_reg_len(gxio_usb_host_context_t *context)
-{
- return HV_USB_HOST_MMIO_SIZE;
-}
-
-EXPORT_SYMBOL_GPL(gxio_usb_host_get_reg_len);
diff --git a/arch/tile/include/arch/mpipe.h b/arch/tile/include/arch/mpipe.h
deleted file mode 100644
index 904538e754d8..000000000000
--- a/arch/tile/include/arch/mpipe.h
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_MPIPE_H__
-#define __ARCH_MPIPE_H__
-
-#include <arch/abi.h>
-#include <arch/mpipe_def.h>
-
-#ifndef __ASSEMBLER__
-
-/*
- * MMIO Ingress DMA Release Region Address.
- * This is a description of the physical addresses used to manipulate ingress
- * credit counters. Accesses to this address space should use an address of
- * this form and a value like that specified in IDMA_RELEASE_REGION_VAL.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Reserved. */
- uint_reg_t __reserved_0 : 3;
- /* NotifRing to be released */
- uint_reg_t ring : 8;
- /* Bucket to be released */
- uint_reg_t bucket : 13;
- /* Enable NotifRing release */
- uint_reg_t ring_enable : 1;
- /* Enable Bucket release */
- uint_reg_t bucket_enable : 1;
- /*
- * This field of the address selects the region (address space) to be
- * accessed. For the iDMA release region, this field must be 4.
- */
- uint_reg_t region : 3;
- /* Reserved. */
- uint_reg_t __reserved_1 : 6;
- /* This field of the address indexes the 32 entry service domain table. */
- uint_reg_t svc_dom : 5;
- /* Reserved. */
- uint_reg_t __reserved_2 : 24;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_2 : 24;
- uint_reg_t svc_dom : 5;
- uint_reg_t __reserved_1 : 6;
- uint_reg_t region : 3;
- uint_reg_t bucket_enable : 1;
- uint_reg_t ring_enable : 1;
- uint_reg_t bucket : 13;
- uint_reg_t ring : 8;
- uint_reg_t __reserved_0 : 3;
-#endif
- };
-
- uint_reg_t word;
-} MPIPE_IDMA_RELEASE_REGION_ADDR_t;
-
-/*
- * MMIO Ingress DMA Release Region Value - Release NotifRing and/or Bucket.
- * Provides release of the associated NotifRing. The address of the MMIO
- * operation is described in IDMA_RELEASE_REGION_ADDR.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * Number of packets being released. The load balancer's count of
- * inflight packets will be decremented by this amount for the associated
- * Bucket and/or NotifRing
- */
- uint_reg_t count : 16;
- /* Reserved. */
- uint_reg_t __reserved : 48;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved : 48;
- uint_reg_t count : 16;
-#endif
- };
-
- uint_reg_t word;
-} MPIPE_IDMA_RELEASE_REGION_VAL_t;
-
-/*
- * MMIO Buffer Stack Manager Region Address.
- * This MMIO region is used for posting or fetching buffers to/from the
- * buffer stack manager. On an MMIO load, this pops a buffer descriptor from
- * the top of stack if one is available. On an MMIO store, this pushes a
- * buffer to the stack. The value read or written is described in
- * BSM_REGION_VAL.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Reserved. */
- uint_reg_t __reserved_0 : 3;
- /* BufferStack being accessed. */
- uint_reg_t stack : 5;
- /* Reserved. */
- uint_reg_t __reserved_1 : 18;
- /*
- * This field of the address selects the region (address space) to be
- * accessed. For the buffer stack manager region, this field must be 6.
- */
- uint_reg_t region : 3;
- /* Reserved. */
- uint_reg_t __reserved_2 : 6;
- /* This field of the address indexes the 32 entry service domain table. */
- uint_reg_t svc_dom : 5;
- /* Reserved. */
- uint_reg_t __reserved_3 : 24;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_3 : 24;
- uint_reg_t svc_dom : 5;
- uint_reg_t __reserved_2 : 6;
- uint_reg_t region : 3;
- uint_reg_t __reserved_1 : 18;
- uint_reg_t stack : 5;
- uint_reg_t __reserved_0 : 3;
-#endif
- };
-
- uint_reg_t word;
-} MPIPE_BSM_REGION_ADDR_t;
-
-/*
- * MMIO Buffer Stack Manager Region Value.
- * This MMIO region is used for posting or fetching buffers to/from the
- * buffer stack manager. On an MMIO load, this pops a buffer descriptor from
- * the top of stack if one is available. On an MMIO store, this pushes a
- * buffer to the stack. The address of the MMIO operation is described in
- * BSM_REGION_ADDR.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Reserved. */
- uint_reg_t __reserved_0 : 7;
- /*
- * Base virtual address of the buffer. Must be sign extended by consumer.
- */
- int_reg_t va : 35;
- /* Reserved. */
- uint_reg_t __reserved_1 : 6;
- /*
- * Index of the buffer stack to which this buffer belongs. Ignored on
- * writes since the offset bits specify the stack being accessed.
- */
- uint_reg_t stack_idx : 5;
- /* Reserved. */
- uint_reg_t __reserved_2 : 3;
- /*
- * Instance ID. For devices that support automatic buffer return between
- * mPIPE instances, this field indicates the buffer owner. If the INST
- * field does not match the mPIPE's instance number when a packet is
- * egressed, buffers with HWB set will be returned to the other mPIPE
- * instance. Note that not all devices support multi-mPIPE buffer
- * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates
- * whether the INST field in the buffer descriptor is populated by iDMA
- * hardware. This field is ignored on writes.
- */
- uint_reg_t inst : 2;
- /*
- * Reads as one to indicate that this is a hardware managed buffer.
- * Ignored on writes since all buffers on a given stack are the same size.
- */
- uint_reg_t hwb : 1;
- /*
- * Encoded size of buffer (ignored on writes):
- * 0 = 128 bytes
- * 1 = 256 bytes
- * 2 = 512 bytes
- * 3 = 1024 bytes
- * 4 = 1664 bytes
- * 5 = 4096 bytes
- * 6 = 10368 bytes
- * 7 = 16384 bytes
- */
- uint_reg_t size : 3;
- /*
- * Valid indication for the buffer. Ignored on writes.
- * 0 : Valid buffer descriptor popped from stack.
- * 3 : Could not pop a buffer from the stack. Either the stack is empty,
- * or the hardware's prefetch buffer is empty for this stack.
- */
- uint_reg_t c : 2;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t c : 2;
- uint_reg_t size : 3;
- uint_reg_t hwb : 1;
- uint_reg_t inst : 2;
- uint_reg_t __reserved_2 : 3;
- uint_reg_t stack_idx : 5;
- uint_reg_t __reserved_1 : 6;
- int_reg_t va : 35;
- uint_reg_t __reserved_0 : 7;
-#endif
- };
-
- uint_reg_t word;
-} MPIPE_BSM_REGION_VAL_t;
-
-/*
- * MMIO Egress DMA Post Region Address.
- * Used to post descriptor locations to the eDMA descriptor engine. The
- * value to be written is described in EDMA_POST_REGION_VAL
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Reserved. */
- uint_reg_t __reserved_0 : 3;
- /* eDMA ring being accessed */
- uint_reg_t ring : 6;
- /* Reserved. */
- uint_reg_t __reserved_1 : 17;
- /*
- * This field of the address selects the region (address space) to be
- * accessed. For the egress DMA post region, this field must be 5.
- */
- uint_reg_t region : 3;
- /* Reserved. */
- uint_reg_t __reserved_2 : 6;
- /* This field of the address indexes the 32 entry service domain table. */
- uint_reg_t svc_dom : 5;
- /* Reserved. */
- uint_reg_t __reserved_3 : 24;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_3 : 24;
- uint_reg_t svc_dom : 5;
- uint_reg_t __reserved_2 : 6;
- uint_reg_t region : 3;
- uint_reg_t __reserved_1 : 17;
- uint_reg_t ring : 6;
- uint_reg_t __reserved_0 : 3;
-#endif
- };
-
- uint_reg_t word;
-} MPIPE_EDMA_POST_REGION_ADDR_t;
-
-/*
- * MMIO Egress DMA Post Region Value.
- * Used to post descriptor locations to the eDMA descriptor engine. The
- * address is described in EDMA_POST_REGION_ADDR.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * For writes, this specifies the current ring tail pointer prior to any
- * post. For example, to post 1 or more descriptors starting at location
- * 23, this would contain 23 (not 24). On writes, this index must be
- * masked based on the ring size. The new tail pointer after this post
- * is COUNT+RING_IDX (masked by the ring size).
- *
- * For reads, this provides the hardware descriptor fetcher's head
- * pointer. The descriptors prior to the head pointer, however, may not
- * yet have been processed so this indicator is only used to determine
- * how full the ring is and if software may post more descriptors.
- */
- uint_reg_t ring_idx : 16;
- /*
- * For writes, this specifies number of contiguous descriptors that are
- * being posted. Software may post up to RingSize descriptors with a
- * single MMIO store. A zero in this field on a write will "wake up" an
- * eDMA ring and cause it fetch descriptors regardless of the hardware's
- * current view of the state of the tail pointer.
- *
- * For reads, this field provides a rolling count of the number of
- * descriptors that have been completely processed. This may be used by
- * software to determine when buffers associated with a descriptor may be
- * returned or reused. When the ring's flush bit is cleared by software
- * (after having been set by HW or SW), the COUNT will be cleared.
- */
- uint_reg_t count : 16;
- /*
- * For writes, this specifies the generation number of the tail being
- * posted. Note that if tail+cnt wraps to the beginning of the ring, the
- * eDMA hardware assumes that the descriptors posted at the beginning of
- * the ring are also valid so it is okay to post around the wrap point.
- *
- * For reads, this is the current generation number. Valid descriptors
- * will have the inverse of this generation number.
- */
- uint_reg_t gen : 1;
- /* Reserved. */
- uint_reg_t __reserved : 31;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved : 31;
- uint_reg_t gen : 1;
- uint_reg_t count : 16;
- uint_reg_t ring_idx : 16;
-#endif
- };
-
- uint_reg_t word;
-} MPIPE_EDMA_POST_REGION_VAL_t;
-
-/*
- * Load Balancer Bucket Status Data.
- * Read/Write data for load balancer Bucket-Status Table. 4160 entries
- * indexed by LBL_INIT_CTL.IDX when LBL_INIT_CTL.STRUCT_SEL is BSTS_TBL
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* NotifRing currently assigned to this bucket. */
- uint_reg_t notifring : 8;
- /* Current reference count. */
- uint_reg_t count : 16;
- /* Group associated with this bucket. */
- uint_reg_t group : 5;
- /* Mode select for this bucket. */
- uint_reg_t mode : 3;
- /* Reserved. */
- uint_reg_t __reserved : 32;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved : 32;
- uint_reg_t mode : 3;
- uint_reg_t group : 5;
- uint_reg_t count : 16;
- uint_reg_t notifring : 8;
-#endif
- };
-
- uint_reg_t word;
-} MPIPE_LBL_INIT_DAT_BSTS_TBL_t;
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_MPIPE_H__) */
diff --git a/arch/tile/include/arch/mpipe_constants.h b/arch/tile/include/arch/mpipe_constants.h
deleted file mode 100644
index 84022ac5fe82..000000000000
--- a/arch/tile/include/arch/mpipe_constants.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-
-#ifndef __ARCH_MPIPE_CONSTANTS_H__
-#define __ARCH_MPIPE_CONSTANTS_H__
-
-#define MPIPE_NUM_CLASSIFIERS 16
-#define MPIPE_CLS_MHZ 1200
-
-#define MPIPE_NUM_EDMA_RINGS 64
-
-#define MPIPE_NUM_SGMII_MACS 16
-#define MPIPE_NUM_XAUI_MACS 16
-#define MPIPE_NUM_LOOPBACK_CHANNELS 4
-#define MPIPE_NUM_NON_LB_CHANNELS 28
-
-#define MPIPE_NUM_IPKT_BLOCKS 1536
-
-#define MPIPE_NUM_BUCKETS 4160
-
-#define MPIPE_NUM_NOTIF_RINGS 256
-
-#define MPIPE_NUM_NOTIF_GROUPS 32
-
-#define MPIPE_NUM_TLBS_PER_ASID 16
-#define MPIPE_TLB_IDX_WIDTH 4
-
-#define MPIPE_MMIO_NUM_SVC_DOM 32
-
-#endif /* __ARCH_MPIPE_CONSTANTS_H__ */
diff --git a/arch/tile/include/arch/mpipe_def.h b/arch/tile/include/arch/mpipe_def.h
deleted file mode 100644
index c3d30217fc66..000000000000
--- a/arch/tile/include/arch/mpipe_def.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_MPIPE_DEF_H__
-#define __ARCH_MPIPE_DEF_H__
-#define MPIPE_MMIO_ADDR__REGION_SHIFT 26
-#define MPIPE_MMIO_ADDR__REGION_VAL_CFG 0x0
-#define MPIPE_MMIO_ADDR__REGION_VAL_IDMA 0x4
-#define MPIPE_MMIO_ADDR__REGION_VAL_EDMA 0x5
-#define MPIPE_MMIO_ADDR__REGION_VAL_BSM 0x6
-#define MPIPE_BSM_REGION_VAL__VA_SHIFT 7
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_128 0x0
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_256 0x1
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_512 0x2
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1024 0x3
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1664 0x4
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_4096 0x5
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_10368 0x6
-#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_16384 0x7
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_DFA 0x0
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_FIXED 0x1
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_ALWAYS_PICK 0x2
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY 0x3
-#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY_RAND 0x7
-#define MPIPE_LBL_NR_STATE__FIRST_WORD 0x2138
-#endif /* !defined(__ARCH_MPIPE_DEF_H__) */
diff --git a/arch/tile/include/arch/mpipe_shm.h b/arch/tile/include/arch/mpipe_shm.h
deleted file mode 100644
index 13b3c4300e50..000000000000
--- a/arch/tile/include/arch/mpipe_shm.h
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-
-#ifndef __ARCH_MPIPE_SHM_H__
-#define __ARCH_MPIPE_SHM_H__
-
-#include <arch/abi.h>
-#include <arch/mpipe_shm_def.h>
-
-#ifndef __ASSEMBLER__
-/**
- * MPIPE eDMA Descriptor.
- * The eDMA descriptor is written by software and consumed by hardware. It
- * is used to specify the location of egress packet data to be sent out of
- * the chip via one of the packet interfaces.
- */
-
-__extension__
-typedef union
-{
- struct
- {
- /* Word 0 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Generation number. Used to indicate a valid descriptor in ring. When
- * a new descriptor is written into the ring, software must toggle this
- * bit. The net effect is that the GEN bit being written into new
- * descriptors toggles each time the ring tail pointer wraps.
- */
- uint_reg_t gen : 1;
- /**
- * For devices with EDMA reorder support, this field allows the
- * descriptor to select the egress FIFO. The associated DMA ring must
- * have ALLOW_EFIFO_SEL enabled.
- */
- uint_reg_t efifo_sel : 6;
- /** Reserved. Must be zero. */
- uint_reg_t r0 : 1;
- /** Checksum generation enabled for this transfer. */
- uint_reg_t csum : 1;
- /**
- * Nothing to be sent. Used, for example, when software has dropped a
- * packet but still wishes to return all of the associated buffers.
- */
- uint_reg_t ns : 1;
- /**
- * Notification interrupt will be delivered when packet has been egressed.
- */
- uint_reg_t notif : 1;
- /**
- * Boundary indicator. When 1, this transfer includes the EOP for this
- * command. Must be clear on all but the last descriptor for an egress
- * packet.
- */
- uint_reg_t bound : 1;
- /** Reserved. Must be zero. */
- uint_reg_t r1 : 4;
- /**
- * Number of bytes to be sent for this descriptor. When zero, no data
- * will be moved and the buffer descriptor will be ignored. If the
- * buffer descriptor indicates that it is chained, the low 7 bits of the
- * VA indicate the offset within the first buffer (e.g. 127 bytes is the
- * maximum offset into the first buffer). If the size exceeds a single
- * buffer, subsequent buffer descriptors will be fetched prior to
- * processing the next eDMA descriptor in the ring.
- */
- uint_reg_t xfer_size : 14;
- /** Reserved. Must be zero. */
- uint_reg_t r2 : 2;
- /**
- * Destination of checksum relative to CSUM_START relative to the first
- * byte moved by this descriptor. Must be zero if CSUM=0 in this
- * descriptor. Must be less than XFER_SIZE (e.g. the first byte of the
- * CSUM_DEST must be within the span of this descriptor).
- */
- uint_reg_t csum_dest : 8;
- /**
- * Start byte of checksum relative to the first byte moved by this
- * descriptor. If this is not the first descriptor for the egress
- * packet, CSUM_START is still relative to the first byte in this
- * descriptor. Must be zero if CSUM=0 in this descriptor.
- */
- uint_reg_t csum_start : 8;
- /**
- * Initial value for 16-bit 1's compliment checksum if enabled via CSUM.
- * Specified in network order. That is, bits[7:0] will be added to the
- * byte pointed to by CSUM_START and bits[15:8] will be added to the byte
- * pointed to by CSUM_START+1 (with appropriate 1's compliment carries).
- * Must be zero if CSUM=0 in this descriptor.
- */
- uint_reg_t csum_seed : 16;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t csum_seed : 16;
- uint_reg_t csum_start : 8;
- uint_reg_t csum_dest : 8;
- uint_reg_t r2 : 2;
- uint_reg_t xfer_size : 14;
- uint_reg_t r1 : 4;
- uint_reg_t bound : 1;
- uint_reg_t notif : 1;
- uint_reg_t ns : 1;
- uint_reg_t csum : 1;
- uint_reg_t r0 : 1;
- uint_reg_t efifo_sel : 6;
- uint_reg_t gen : 1;
-#endif
-
- /* Word 1 */
-
-#ifndef __BIG_ENDIAN__
- /** Virtual address. Must be sign extended by consumer. */
- int_reg_t va : 42;
- /** Reserved. */
- uint_reg_t __reserved_0 : 6;
- /** Index of the buffer stack to which this buffer belongs. */
- uint_reg_t stack_idx : 5;
- /** Reserved. */
- uint_reg_t __reserved_1 : 3;
- /**
- * Instance ID. For devices that support automatic buffer return between
- * mPIPE instances, this field indicates the buffer owner. If the INST
- * field does not match the mPIPE's instance number when a packet is
- * egressed, buffers with HWB set will be returned to the other mPIPE
- * instance. Note that not all devices support multi-mPIPE buffer
- * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates
- * whether the INST field in the buffer descriptor is populated by iDMA
- * hardware.
- */
- uint_reg_t inst : 2;
- /**
- * Always set to one by hardware in iDMA packet descriptors. For eDMA,
- * indicates whether the buffer will be released to the buffer stack
- * manager. When 0, software is responsible for releasing the buffer.
- */
- uint_reg_t hwb : 1;
- /**
- * Encoded size of buffer. Set by the ingress hardware for iDMA packet
- * descriptors. For eDMA descriptors, indicates the buffer size if .c
- * indicates a chained packet. If an eDMA descriptor is not chained and
- * the .hwb bit is not set, this field is ignored and the size is
- * specified by the .xfer_size field.
- * 0 = 128 bytes
- * 1 = 256 bytes
- * 2 = 512 bytes
- * 3 = 1024 bytes
- * 4 = 1664 bytes
- * 5 = 4096 bytes
- * 6 = 10368 bytes
- * 7 = 16384 bytes
- */
- uint_reg_t size : 3;
- /**
- * Chaining configuration for the buffer. Indicates that an ingress
- * packet or egress command is chained across multiple buffers, with each
- * buffer's size indicated by the .size field.
- */
- uint_reg_t c : 2;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t c : 2;
- uint_reg_t size : 3;
- uint_reg_t hwb : 1;
- uint_reg_t inst : 2;
- uint_reg_t __reserved_1 : 3;
- uint_reg_t stack_idx : 5;
- uint_reg_t __reserved_0 : 6;
- int_reg_t va : 42;
-#endif
-
- };
-
- /** Word access */
- uint_reg_t words[2];
-} MPIPE_EDMA_DESC_t;
-
-/**
- * MPIPE Packet Descriptor.
- * The packet descriptor is filled by the mPIPE's classification,
- * load-balancing, and buffer management services. Some fields are consumed
- * by mPIPE hardware, and others are consumed by Tile software.
- */
-
-__extension__
-typedef union
-{
- struct
- {
- /* Word 0 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Notification ring into which this packet descriptor is written.
- * Typically written by load balancer, but can be overridden by
- * classification program if NR is asserted.
- */
- uint_reg_t notif_ring : 8;
- /** Source channel for this packet. Written by mPIPE DMA hardware. */
- uint_reg_t channel : 5;
- /** Reserved. */
- uint_reg_t __reserved_0 : 1;
- /**
- * MAC Error.
- * Generated by the MAC interface. Asserted if there was an overrun of
- * the MAC's receive FIFO. This condition generally only occurs if the
- * mPIPE clock is running too slowly.
- */
- uint_reg_t me : 1;
- /**
- * Truncation Error.
- * Written by the iDMA hardware. Asserted if packet was truncated due to
- * insufficient space in iPkt buffer
- */
- uint_reg_t tr : 1;
- /**
- * Written by the iDMA hardware. Indicates the number of bytes written
- * to Tile memory. In general, this is the actual size of the packet as
- * received from the MAC. But if the packet is truncated due to running
- * out of buffers or due to the iPkt buffer filling up, then the L2_SIZE
- * will be reduced to reflect the actual number of valid bytes written to
- * Tile memory.
- */
- uint_reg_t l2_size : 14;
- /**
- * CRC Error.
- * Generated by the MAC. Asserted if MAC indicated an L2 CRC error or
- * other L2 error (bad length etc.) on the packet.
- */
- uint_reg_t ce : 1;
- /**
- * Cut Through.
- * Written by the iDMA hardware. Asserted if packet was not completely
- * received before being sent to classifier. L2_Size will indicate
- * number of bytes received so far.
- */
- uint_reg_t ct : 1;
- /**
- * Written by the classification program. Used by the load balancer to
- * select the ring into which this packet descriptor is written.
- */
- uint_reg_t bucket_id : 13;
- /** Reserved. */
- uint_reg_t __reserved_1 : 3;
- /**
- * Checksum.
- * Written by classification program. When 1, the checksum engine will
- * perform checksum based on the CSUM_SEED, CSUM_START, and CSUM_BYTES
- * fields. The result will be placed in CSUM_VAL.
- */
- uint_reg_t cs : 1;
- /**
- * Notification Ring Select.
- * Written by the classification program. When 1, the NotifRingIDX is
- * set by classification program rather than being set by load balancer.
- */
- uint_reg_t nr : 1;
- /**
- * Written by classification program. Indicates whether packet and
- * descriptor should both be dropped, both be delivered, or only the
- * descriptor should be delivered.
- */
- uint_reg_t dest : 2;
- /**
- * General Purpose Sequence Number Enable.
- * Written by the classification program. When 1, the GP_SQN_SEL field
- * contains the sequence number selector and the GP_SQN field will be
- * replaced with the associated sequence number. When clear, the GP_SQN
- * field is left intact and be used as "Custom" bytes.
- */
- uint_reg_t sq : 1;
- /**
- * TimeStamp Enable.
- * Enable TimeStamp insertion. When clear, timestamp field may be filled
- * with custom data by classifier. When set, hardware inserts the
- * timestamp when the start of packet is received from the MAC.
- */
- uint_reg_t ts : 1;
- /**
- * Packet Sequence Number Enable.
- * Enable PacketSQN insertion. When clear, PacketSQN field may be filled
- * with custom data by classifier. When set, hardware inserts the packet
- * sequence number when the packet descriptor is written to a
- * notification ring.
- */
- uint_reg_t ps : 1;
- /**
- * Buffer Error.
- * Written by the iDMA hardware. Asserted if iDMA ran out of buffers
- * while writing the packet. Software must still return any buffer
- * descriptors whose C field indicates a valid descriptor was consumed.
- */
- uint_reg_t be : 1;
- /**
- * Written by the classification program. The associated counter is
- * incremented when the packet is sent.
- */
- uint_reg_t ctr0 : 5;
- /** Reserved. */
- uint_reg_t __reserved_2 : 3;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_2 : 3;
- uint_reg_t ctr0 : 5;
- uint_reg_t be : 1;
- uint_reg_t ps : 1;
- uint_reg_t ts : 1;
- uint_reg_t sq : 1;
- uint_reg_t dest : 2;
- uint_reg_t nr : 1;
- uint_reg_t cs : 1;
- uint_reg_t __reserved_1 : 3;
- uint_reg_t bucket_id : 13;
- uint_reg_t ct : 1;
- uint_reg_t ce : 1;
- uint_reg_t l2_size : 14;
- uint_reg_t tr : 1;
- uint_reg_t me : 1;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t channel : 5;
- uint_reg_t notif_ring : 8;
-#endif
-
- /* Word 1 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Written by the classification program. The associated counter is
- * incremented when the packet is sent.
- */
- uint_reg_t ctr1 : 5;
- /** Reserved. */
- uint_reg_t __reserved_3 : 3;
- /**
- * Written by classification program. Indicates the start byte for
- * checksum. Relative to 1st byte received from MAC.
- */
- uint_reg_t csum_start : 8;
- /**
- * Checksum seed written by classification program. Overwritten with
- * resultant checksum if CS bit is asserted. The endianness of the CSUM
- * value bits when viewed by Tile software match the packet byte order.
- * That is, bits[7:0] of the resulting checksum value correspond to
- * earlier (more significant) bytes in the packet. To avoid classifier
- * software from having to byte swap the CSUM_SEED, the iDMA checksum
- * engine byte swaps the classifier's result before seeding the checksum
- * calculation. Thus, the CSUM_START byte of packet data is added to
- * bits[15:8] of the CSUM_SEED field generated by the classifier. This
- * byte swap will be visible to Tile software if the CS bit is clear.
- */
- uint_reg_t csum_seed_val : 16;
- /**
- * Written by the classification program. Not interpreted by mPIPE
- * hardware.
- */
- uint_reg_t custom0 : 32;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t custom0 : 32;
- uint_reg_t csum_seed_val : 16;
- uint_reg_t csum_start : 8;
- uint_reg_t __reserved_3 : 3;
- uint_reg_t ctr1 : 5;
-#endif
-
- /* Word 2 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Written by the classification program. Not interpreted by mPIPE
- * hardware.
- */
- uint_reg_t custom1 : 64;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t custom1 : 64;
-#endif
-
- /* Word 3 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Written by the classification program. Not interpreted by mPIPE
- * hardware.
- */
- uint_reg_t custom2 : 64;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t custom2 : 64;
-#endif
-
- /* Word 4 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Written by the classification program. Not interpreted by mPIPE
- * hardware.
- */
- uint_reg_t custom3 : 64;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t custom3 : 64;
-#endif
-
- /* Word 5 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Sequence number applied when packet is distributed. Classifier
- * selects which sequence number is to be applied by writing the 13-bit
- * SQN-selector into this field. For devices that support EXT_SQN (as
- * indicated in IDMA_INFO.EXT_SQN_SUPPORT), the GP_SQN can be extended to
- * 32-bits via the IDMA_CTL.EXT_SQN register. In this case the
- * PACKET_SQN will be reduced to 32 bits.
- */
- uint_reg_t gp_sqn : 16;
- /**
- * Written by notification hardware. The packet sequence number is
- * incremented for each packet that wasn't dropped.
- */
- uint_reg_t packet_sqn : 48;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t packet_sqn : 48;
- uint_reg_t gp_sqn : 16;
-#endif
-
- /* Word 6 */
-
-#ifndef __BIG_ENDIAN__
- /**
- * Written by hardware when the start-of-packet is received by the mPIPE
- * from the MAC. This is the nanoseconds part of the packet timestamp.
- */
- uint_reg_t time_stamp_ns : 32;
- /**
- * Written by hardware when the start-of-packet is received by the mPIPE
- * from the MAC. This is the seconds part of the packet timestamp.
- */
- uint_reg_t time_stamp_sec : 32;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t time_stamp_sec : 32;
- uint_reg_t time_stamp_ns : 32;
-#endif
-
- /* Word 7 */
-
-#ifndef __BIG_ENDIAN__
- /** Virtual address. Must be sign extended by consumer. */
- int_reg_t va : 42;
- /** Reserved. */
- uint_reg_t __reserved_4 : 6;
- /** Index of the buffer stack to which this buffer belongs. */
- uint_reg_t stack_idx : 5;
- /** Reserved. */
- uint_reg_t __reserved_5 : 3;
- /**
- * Instance ID. For devices that support automatic buffer return between
- * mPIPE instances, this field indicates the buffer owner. If the INST
- * field does not match the mPIPE's instance number when a packet is
- * egressed, buffers with HWB set will be returned to the other mPIPE
- * instance. Note that not all devices support multi-mPIPE buffer
- * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates
- * whether the INST field in the buffer descriptor is populated by iDMA
- * hardware.
- */
- uint_reg_t inst : 2;
- /**
- * Always set to one by hardware in iDMA packet descriptors. For eDMA,
- * indicates whether the buffer will be released to the buffer stack
- * manager. When 0, software is responsible for releasing the buffer.
- */
- uint_reg_t hwb : 1;
- /**
- * Encoded size of buffer. Set by the ingress hardware for iDMA packet
- * descriptors. For eDMA descriptors, indicates the buffer size if .c
- * indicates a chained packet. If an eDMA descriptor is not chained and
- * the .hwb bit is not set, this field is ignored and the size is
- * specified by the .xfer_size field.
- * 0 = 128 bytes
- * 1 = 256 bytes
- * 2 = 512 bytes
- * 3 = 1024 bytes
- * 4 = 1664 bytes
- * 5 = 4096 bytes
- * 6 = 10368 bytes
- * 7 = 16384 bytes
- */
- uint_reg_t size : 3;
- /**
- * Chaining configuration for the buffer. Indicates that an ingress
- * packet or egress command is chained across multiple buffers, with each
- * buffer's size indicated by the .size field.
- */
- uint_reg_t c : 2;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t c : 2;
- uint_reg_t size : 3;
- uint_reg_t hwb : 1;
- uint_reg_t inst : 2;
- uint_reg_t __reserved_5 : 3;
- uint_reg_t stack_idx : 5;
- uint_reg_t __reserved_4 : 6;
- int_reg_t va : 42;
-#endif
-
- };
-
- /** Word access */
- uint_reg_t words[8];
-} MPIPE_PDESC_t;
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_MPIPE_SHM_H__) */
diff --git a/arch/tile/include/arch/mpipe_shm_def.h b/arch/tile/include/arch/mpipe_shm_def.h
deleted file mode 100644
index 6124d39c8318..000000000000
--- a/arch/tile/include/arch/mpipe_shm_def.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_MPIPE_SHM_DEF_H__
-#define __ARCH_MPIPE_SHM_DEF_H__
-#define MPIPE_EDMA_DESC_WORD1__C_VAL_UNCHAINED 0x0
-#define MPIPE_EDMA_DESC_WORD1__C_VAL_CHAINED 0x1
-#define MPIPE_EDMA_DESC_WORD1__C_VAL_NOT_RDY 0x2
-#define MPIPE_EDMA_DESC_WORD1__C_VAL_INVALID 0x3
-#endif /* !defined(__ARCH_MPIPE_SHM_DEF_H__) */
diff --git a/arch/tile/include/arch/spr_def.h b/arch/tile/include/arch/spr_def.h
deleted file mode 100644
index 2de83e7aff3e..000000000000
--- a/arch/tile/include/arch/spr_def.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-#ifndef __ARCH_SPR_DEF_H__
-#define __ARCH_SPR_DEF_H__
-
-#include <uapi/arch/spr_def.h>
-
-
-/*
- * In addition to including the proper base SPR definition file, depending
- * on machine architecture, this file defines several macros which allow
- * kernel code to use protection-level dependent SPRs without worrying
- * about which PL it's running at. In these macros, the PL that the SPR
- * or interrupt number applies to is replaced by K.
- */
-
-#if CONFIG_KERNEL_PL != 1 && CONFIG_KERNEL_PL != 2
-#error CONFIG_KERNEL_PL must be 1 or 2
-#endif
-
-/* Concatenate 4 strings. */
-#define __concat4(a, b, c, d) a ## b ## c ## d
-#define _concat4(a, b, c, d) __concat4(a, b, c, d)
-
-#ifdef __tilegx__
-
-/* TILE-Gx dependent, protection-level dependent SPRs. */
-
-#define SPR_INTERRUPT_MASK_K \
- _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL,,)
-#define SPR_INTERRUPT_MASK_SET_K \
- _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL,,)
-#define SPR_INTERRUPT_MASK_RESET_K \
- _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL,,)
-#define SPR_INTERRUPT_VECTOR_BASE_K \
- _concat4(SPR_INTERRUPT_VECTOR_BASE_, CONFIG_KERNEL_PL,,)
-
-#define SPR_IPI_MASK_K \
- _concat4(SPR_IPI_MASK_, CONFIG_KERNEL_PL,,)
-#define SPR_IPI_MASK_RESET_K \
- _concat4(SPR_IPI_MASK_RESET_, CONFIG_KERNEL_PL,,)
-#define SPR_IPI_MASK_SET_K \
- _concat4(SPR_IPI_MASK_SET_, CONFIG_KERNEL_PL,,)
-#define SPR_IPI_EVENT_K \
- _concat4(SPR_IPI_EVENT_, CONFIG_KERNEL_PL,,)
-#define SPR_IPI_EVENT_RESET_K \
- _concat4(SPR_IPI_EVENT_RESET_, CONFIG_KERNEL_PL,,)
-#define SPR_IPI_EVENT_SET_K \
- _concat4(SPR_IPI_EVENT_SET_, CONFIG_KERNEL_PL,,)
-#define INT_IPI_K \
- _concat4(INT_IPI_, CONFIG_KERNEL_PL,,)
-
-#define SPR_SINGLE_STEP_CONTROL_K \
- _concat4(SPR_SINGLE_STEP_CONTROL_, CONFIG_KERNEL_PL,,)
-#define SPR_SINGLE_STEP_EN_K_K \
- _concat4(SPR_SINGLE_STEP_EN_, CONFIG_KERNEL_PL, _, CONFIG_KERNEL_PL)
-#define INT_SINGLE_STEP_K \
- _concat4(INT_SINGLE_STEP_, CONFIG_KERNEL_PL,,)
-
-#else
-
-/* TILEPro dependent, protection-level dependent SPRs. */
-
-#define SPR_INTERRUPT_MASK_K_0 \
- _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _0,)
-#define SPR_INTERRUPT_MASK_K_1 \
- _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _1,)
-#define SPR_INTERRUPT_MASK_SET_K_0 \
- _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _0,)
-#define SPR_INTERRUPT_MASK_SET_K_1 \
- _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _1,)
-#define SPR_INTERRUPT_MASK_RESET_K_0 \
- _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _0,)
-#define SPR_INTERRUPT_MASK_RESET_K_1 \
- _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _1,)
-
-#endif
-
-/* Generic protection-level dependent SPRs. */
-
-#define SPR_SYSTEM_SAVE_K_0 \
- _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _0,)
-#define SPR_SYSTEM_SAVE_K_1 \
- _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _1,)
-#define SPR_SYSTEM_SAVE_K_2 \
- _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _2,)
-#define SPR_SYSTEM_SAVE_K_3 \
- _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _3,)
-#define SPR_EX_CONTEXT_K_0 \
- _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _0,)
-#define SPR_EX_CONTEXT_K_1 \
- _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _1,)
-#define SPR_INTCTRL_K_STATUS \
- _concat4(SPR_INTCTRL_, CONFIG_KERNEL_PL, _STATUS,)
-#define INT_INTCTRL_K \
- _concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,)
-
-#endif /* __ARCH_SPR_DEF_H__ */
diff --git a/arch/tile/include/arch/trio.h b/arch/tile/include/arch/trio.h
deleted file mode 100644
index c0ddedcae085..000000000000
--- a/arch/tile/include/arch/trio.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_TRIO_H__
-#define __ARCH_TRIO_H__
-
-#include <arch/abi.h>
-#include <arch/trio_def.h>
-
-#ifndef __ASSEMBLER__
-
-/*
- * Map SQ Doorbell Format.
- * This describes the format of the write-only doorbell register that exists
- * in the last 8-bytes of the MAP_SQ_BASE/LIM range. This register is only
- * writable from PCIe space. Writes to this register will not be written to
- * Tile memory space and thus no IO VA translation is required if the last
- * page of the BASE/LIM range is not otherwise written.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * When written with a 1, the associated MAP_SQ region's doorbell
- * interrupt will be triggered once all previous writes are visible to
- * Tile software.
- */
- uint_reg_t doorbell : 1;
- /*
- * When written with a 1, the descriptor at the head of the associated
- * MAP_SQ's FIFO will be dequeued.
- */
- uint_reg_t pop : 1;
- /* Reserved. */
- uint_reg_t __reserved : 62;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved : 62;
- uint_reg_t pop : 1;
- uint_reg_t doorbell : 1;
-#endif
- };
-
- uint_reg_t word;
-} TRIO_MAP_SQ_DOORBELL_FMT_t;
-
-
-/*
- * Tile PIO Region Configuration - CFG Address Format.
- * This register describes the address format for PIO accesses when the
- * associated region is setup with TYPE=CFG.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Register Address (full byte address). */
- uint_reg_t reg_addr : 12;
- /* Function Number */
- uint_reg_t fn : 3;
- /* Device Number */
- uint_reg_t dev : 5;
- /* BUS Number */
- uint_reg_t bus : 8;
- /* Config Type: 0 for access to directly-attached device. 1 otherwise. */
- uint_reg_t type : 1;
- /* Reserved. */
- uint_reg_t __reserved_0 : 1;
- /*
- * MAC select. This must match the configuration in
- * TILE_PIO_REGION_SETUP.MAC.
- */
- uint_reg_t mac : 2;
- /* Reserved. */
- uint_reg_t __reserved_1 : 32;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_1 : 32;
- uint_reg_t mac : 2;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t type : 1;
- uint_reg_t bus : 8;
- uint_reg_t dev : 5;
- uint_reg_t fn : 3;
- uint_reg_t reg_addr : 12;
-#endif
- };
-
- uint_reg_t word;
-} TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t;
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_TRIO_H__) */
diff --git a/arch/tile/include/arch/trio_constants.h b/arch/tile/include/arch/trio_constants.h
deleted file mode 100644
index 85647e91a458..000000000000
--- a/arch/tile/include/arch/trio_constants.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-
-#ifndef __ARCH_TRIO_CONSTANTS_H__
-#define __ARCH_TRIO_CONSTANTS_H__
-
-#define TRIO_NUM_ASIDS 32
-#define TRIO_NUM_TLBS_PER_ASID 16
-
-#define TRIO_NUM_TPIO_REGIONS 8
-#define TRIO_LOG2_NUM_TPIO_REGIONS 3
-
-#define TRIO_NUM_MAP_MEM_REGIONS 32
-#define TRIO_LOG2_NUM_MAP_MEM_REGIONS 5
-#define TRIO_NUM_MAP_SQ_REGIONS 8
-#define TRIO_LOG2_NUM_MAP_SQ_REGIONS 3
-
-#define TRIO_LOG2_NUM_SQ_FIFO_ENTRIES 6
-
-#define TRIO_NUM_PUSH_DMA_RINGS 64
-
-#define TRIO_NUM_PULL_DMA_RINGS 64
-
-#endif /* __ARCH_TRIO_CONSTANTS_H__ */
diff --git a/arch/tile/include/arch/trio_def.h b/arch/tile/include/arch/trio_def.h
deleted file mode 100644
index e80500317dc4..000000000000
--- a/arch/tile/include/arch/trio_def.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_TRIO_DEF_H__
-#define __ARCH_TRIO_DEF_H__
-#define TRIO_CFG_REGION_ADDR__REG_SHIFT 0
-#define TRIO_CFG_REGION_ADDR__INTFC_SHIFT 16
-#define TRIO_CFG_REGION_ADDR__INTFC_VAL_TRIO 0x0
-#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE 0x1
-#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD 0x2
-#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED 0x3
-#define TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT 18
-#define TRIO_CFG_REGION_ADDR__PROT_SHIFT 20
-#define TRIO_PIO_REGIONS_ADDR__REGION_SHIFT 32
-#define TRIO_MAP_MEM_REG_INT0 0x1000000000
-#define TRIO_MAP_MEM_REG_INT1 0x1000000008
-#define TRIO_MAP_MEM_REG_INT2 0x1000000010
-#define TRIO_MAP_MEM_REG_INT3 0x1000000018
-#define TRIO_MAP_MEM_REG_INT4 0x1000000020
-#define TRIO_MAP_MEM_REG_INT5 0x1000000028
-#define TRIO_MAP_MEM_REG_INT6 0x1000000030
-#define TRIO_MAP_MEM_REG_INT7 0x1000000038
-#define TRIO_MAP_MEM_LIM__ADDR_SHIFT 12
-#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED 0x0
-#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT 0x1
-#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD 0x2
-#define TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT 30
-#endif /* !defined(__ARCH_TRIO_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_intfc.h b/arch/tile/include/arch/trio_pcie_intfc.h
deleted file mode 100644
index 0487fdb9d581..000000000000
--- a/arch/tile/include/arch/trio_pcie_intfc.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_TRIO_PCIE_INTFC_H__
-#define __ARCH_TRIO_PCIE_INTFC_H__
-
-#include <arch/abi.h>
-#include <arch/trio_pcie_intfc_def.h>
-
-#ifndef __ASSEMBLER__
-
-/*
- * Port Configuration.
- * Configuration of the PCIe Port
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Provides the state of the strapping pins for this port. */
- uint_reg_t strap_state : 3;
- /* Reserved. */
- uint_reg_t __reserved_0 : 1;
- /*
- * When 1, the device type will be overridden using OVD_DEV_TYPE_VAL.
- * When 0, the device type is determined based on the STRAP_STATE.
- */
- uint_reg_t ovd_dev_type : 1;
- /* Provides the device type when OVD_DEV_TYPE is 1. */
- uint_reg_t ovd_dev_type_val : 4;
- /* Determines how link is trained. */
- uint_reg_t train_mode : 2;
- /* Reserved. */
- uint_reg_t __reserved_1 : 1;
- /*
- * For PCIe, used to flip physical RX lanes that were not properly wired.
- * This is not the same as lane reversal which is handled automatically
- * during link training. When 0, RX Lane0 must be wired to the link
- * partner (either to its Lane0 or it's LaneN). When RX_LANE_FLIP is 1,
- * the highest numbered lane for this port becomes Lane0 and Lane0 does
- * NOT have to be wired to the link partner.
- */
- uint_reg_t rx_lane_flip : 1;
- /*
- * For PCIe, used to flip physical TX lanes that were not properly wired.
- * This is not the same as lane reversal which is handled automatically
- * during link training. When 0, TX Lane0 must be wired to the link
- * partner (either to its Lane0 or it's LaneN). When TX_LANE_FLIP is 1,
- * the highest numbered lane for this port becomes Lane0 and Lane0 does
- * NOT have to be wired to the link partner.
- */
- uint_reg_t tx_lane_flip : 1;
- /*
- * For StreamIO port, configures the width of the port when TRAIN_MODE is
- * not STRAP.
- */
- uint_reg_t stream_width : 2;
- /*
- * For StreamIO port, configures the rate of the port when TRAIN_MODE is
- * not STRAP.
- */
- uint_reg_t stream_rate : 2;
- /* Reserved. */
- uint_reg_t __reserved_2 : 46;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_2 : 46;
- uint_reg_t stream_rate : 2;
- uint_reg_t stream_width : 2;
- uint_reg_t tx_lane_flip : 1;
- uint_reg_t rx_lane_flip : 1;
- uint_reg_t __reserved_1 : 1;
- uint_reg_t train_mode : 2;
- uint_reg_t ovd_dev_type_val : 4;
- uint_reg_t ovd_dev_type : 1;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t strap_state : 3;
-#endif
- };
-
- uint_reg_t word;
-} TRIO_PCIE_INTFC_PORT_CONFIG_t;
-
-/*
- * Port Status.
- * Status of the PCIe Port. This register applies to the StreamIO port when
- * StreamIO is enabled.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * Indicates the DL state of the port. When 1, the port is up and ready
- * to receive traffic.
- */
- uint_reg_t dl_up : 1;
- /*
- * Indicates the number of times the link has gone down. Clears on read.
- */
- uint_reg_t dl_down_cnt : 7;
- /* Indicates the SERDES PLL has spun up and is providing a valid clock. */
- uint_reg_t clock_ready : 1;
- /* Reserved. */
- uint_reg_t __reserved_0 : 7;
- /* Device revision ID. */
- uint_reg_t device_rev : 8;
- /* Link state (PCIe). */
- uint_reg_t ltssm_state : 6;
- /* Link power management state (PCIe). */
- uint_reg_t pm_state : 3;
- /* Reserved. */
- uint_reg_t __reserved_1 : 31;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_1 : 31;
- uint_reg_t pm_state : 3;
- uint_reg_t ltssm_state : 6;
- uint_reg_t device_rev : 8;
- uint_reg_t __reserved_0 : 7;
- uint_reg_t clock_ready : 1;
- uint_reg_t dl_down_cnt : 7;
- uint_reg_t dl_up : 1;
-#endif
- };
-
- uint_reg_t word;
-} TRIO_PCIE_INTFC_PORT_STATUS_t;
-
-/*
- * Transmit FIFO Control.
- * Contains TX FIFO thresholds. These registers are for diagnostics purposes
- * only. Changing these values causes undefined behavior.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * Almost-Empty level for TX0 data. Typically set to at least
- * roundup(38.0*M/N) where N=tclk frequency and M=MAC symbol rate in MHz
- * for a x4 port (250MHz).
- */
- uint_reg_t tx0_data_ae_lvl : 7;
- /* Reserved. */
- uint_reg_t __reserved_0 : 1;
- /* Almost-Empty level for TX1 data. */
- uint_reg_t tx1_data_ae_lvl : 7;
- /* Reserved. */
- uint_reg_t __reserved_1 : 1;
- /* Almost-Full level for TX0 data. */
- uint_reg_t tx0_data_af_lvl : 7;
- /* Reserved. */
- uint_reg_t __reserved_2 : 1;
- /* Almost-Full level for TX1 data. */
- uint_reg_t tx1_data_af_lvl : 7;
- /* Reserved. */
- uint_reg_t __reserved_3 : 1;
- /* Almost-Full level for TX0 info. */
- uint_reg_t tx0_info_af_lvl : 5;
- /* Reserved. */
- uint_reg_t __reserved_4 : 3;
- /* Almost-Full level for TX1 info. */
- uint_reg_t tx1_info_af_lvl : 5;
- /* Reserved. */
- uint_reg_t __reserved_5 : 3;
- /*
- * This register provides performance adjustment for high bandwidth
- * flows. The MAC will assert almost-full to TRIO if non-posted credits
- * fall below this level. Note that setting this larger than the initial
- * PORT_CREDIT.NPH value will cause READS to never be sent. If the
- * initial credit value from the link partner is smaller than this value
- * when the link comes up, the value will be reset to the initial credit
- * value to prevent lockup.
- */
- uint_reg_t min_np_credits : 8;
- /*
- * This register provides performance adjustment for high bandwidth
- * flows. The MAC will assert almost-full to TRIO if posted credits fall
- * below this level. Note that setting this larger than the initial
- * PORT_CREDIT.PH value will cause WRITES to never be sent. If the
- * initial credit value from the link partner is smaller than this value
- * when the link comes up, the value will be reset to the initial credit
- * value to prevent lockup.
- */
- uint_reg_t min_p_credits : 8;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t min_p_credits : 8;
- uint_reg_t min_np_credits : 8;
- uint_reg_t __reserved_5 : 3;
- uint_reg_t tx1_info_af_lvl : 5;
- uint_reg_t __reserved_4 : 3;
- uint_reg_t tx0_info_af_lvl : 5;
- uint_reg_t __reserved_3 : 1;
- uint_reg_t tx1_data_af_lvl : 7;
- uint_reg_t __reserved_2 : 1;
- uint_reg_t tx0_data_af_lvl : 7;
- uint_reg_t __reserved_1 : 1;
- uint_reg_t tx1_data_ae_lvl : 7;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t tx0_data_ae_lvl : 7;
-#endif
- };
-
- uint_reg_t word;
-} TRIO_PCIE_INTFC_TX_FIFO_CTL_t;
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_intfc_def.h b/arch/tile/include/arch/trio_pcie_intfc_def.h
deleted file mode 100644
index d3fd6781fb24..000000000000
--- a/arch/tile/include/arch/trio_pcie_intfc_def.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_TRIO_PCIE_INTFC_DEF_H__
-#define __ARCH_TRIO_PCIE_INTFC_DEF_H__
-#define TRIO_PCIE_INTFC_MAC_INT_STS 0x0000
-#define TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK 0xf000
-#define TRIO_PCIE_INTFC_PORT_CONFIG 0x0018
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_DISABLED 0x0
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT 0x1
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC 0x2
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 0x3
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1 0x4
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_XLINK 0x5
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X1 0x6
-#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X4 0x7
-#define TRIO_PCIE_INTFC_PORT_STATUS 0x0020
-#define TRIO_PCIE_INTFC_TX_FIFO_CTL 0x0050
-#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_rc.h b/arch/tile/include/arch/trio_pcie_rc.h
deleted file mode 100644
index 6a25d0aca857..000000000000
--- a/arch/tile/include/arch/trio_pcie_rc.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_TRIO_PCIE_RC_H__
-#define __ARCH_TRIO_PCIE_RC_H__
-
-#include <arch/abi.h>
-#include <arch/trio_pcie_rc_def.h>
-
-#ifndef __ASSEMBLER__
-
-/* Device Capabilities Register. */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * Max_Payload_Size Supported, writablethrough the MAC_STANDARD interface
- */
- uint_reg_t mps_sup : 3;
- /*
- * This field is writable through the MAC_STANDARD interface. However,
- * Phantom Function is not supported. Therefore, the application must
- * not write any value other than 0x0 to this field.
- */
- uint_reg_t phantom_function_supported : 2;
- /* This bit is writable through the MAC_STANDARD interface. */
- uint_reg_t ext_tag_field_supported : 1;
- /* Reserved. */
- uint_reg_t __reserved_0 : 3;
- /* Endpoint L1 Acceptable Latency Must be 0x0 for non-Endpoint devices. */
- uint_reg_t l1_lat : 3;
- /*
- * Undefined since PCI Express 1.1 (Was Attention Button Present for PCI
- * Express 1.0a)
- */
- uint_reg_t r1 : 1;
- /*
- * Undefined since PCI Express 1.1 (Was Attention Indicator Present for
- * PCI Express 1.0a)
- */
- uint_reg_t r2 : 1;
- /*
- * Undefined since PCI Express 1.1 (Was Power Indicator Present for PCI
- * Express 1.0a)
- */
- uint_reg_t r3 : 1;
- /*
- * Role-Based Error Reporting, writable through the MAC_STANDARD
- * interface. Required to be set for device compliant to 1.1 spec and
- * later.
- */
- uint_reg_t rer : 1;
- /* Reserved. */
- uint_reg_t __reserved_1 : 2;
- /* Captured Slot Power Limit Value Upstream port only. */
- uint_reg_t slot_pwr_lim : 8;
- /* Captured Slot Power Limit Scale Upstream port only. */
- uint_reg_t slot_pwr_scale : 2;
- /* Reserved. */
- uint_reg_t __reserved_2 : 4;
- /* Endpoint L0s Acceptable LatencyMust be 0x0 for non-Endpoint devices. */
- uint_reg_t l0s_lat : 1;
- /* Reserved. */
- uint_reg_t __reserved_3 : 31;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_3 : 31;
- uint_reg_t l0s_lat : 1;
- uint_reg_t __reserved_2 : 4;
- uint_reg_t slot_pwr_scale : 2;
- uint_reg_t slot_pwr_lim : 8;
- uint_reg_t __reserved_1 : 2;
- uint_reg_t rer : 1;
- uint_reg_t r3 : 1;
- uint_reg_t r2 : 1;
- uint_reg_t r1 : 1;
- uint_reg_t l1_lat : 3;
- uint_reg_t __reserved_0 : 3;
- uint_reg_t ext_tag_field_supported : 1;
- uint_reg_t phantom_function_supported : 2;
- uint_reg_t mps_sup : 3;
-#endif
- };
-
- uint_reg_t word;
-} TRIO_PCIE_RC_DEVICE_CAP_t;
-
-/* Device Control Register. */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Correctable Error Reporting Enable */
- uint_reg_t cor_err_ena : 1;
- /* Non-Fatal Error Reporting Enable */
- uint_reg_t nf_err_ena : 1;
- /* Fatal Error Reporting Enable */
- uint_reg_t fatal_err_ena : 1;
- /* Unsupported Request Reporting Enable */
- uint_reg_t ur_ena : 1;
- /* Relaxed orderring enable */
- uint_reg_t ro_ena : 1;
- /* Max Payload Size */
- uint_reg_t max_payload_size : 3;
- /* Extended Tag Field Enable */
- uint_reg_t ext_tag : 1;
- /* Phantom Function Enable */
- uint_reg_t ph_fn_ena : 1;
- /* AUX Power PM Enable */
- uint_reg_t aux_pm_ena : 1;
- /* Enable NoSnoop */
- uint_reg_t no_snoop : 1;
- /* Max read request size */
- uint_reg_t max_read_req_sz : 3;
- /* Reserved. */
- uint_reg_t __reserved : 49;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved : 49;
- uint_reg_t max_read_req_sz : 3;
- uint_reg_t no_snoop : 1;
- uint_reg_t aux_pm_ena : 1;
- uint_reg_t ph_fn_ena : 1;
- uint_reg_t ext_tag : 1;
- uint_reg_t max_payload_size : 3;
- uint_reg_t ro_ena : 1;
- uint_reg_t ur_ena : 1;
- uint_reg_t fatal_err_ena : 1;
- uint_reg_t nf_err_ena : 1;
- uint_reg_t cor_err_ena : 1;
-#endif
- };
-
- uint_reg_t word;
-} TRIO_PCIE_RC_DEVICE_CONTROL_t;
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_TRIO_PCIE_RC_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_rc_def.h b/arch/tile/include/arch/trio_pcie_rc_def.h
deleted file mode 100644
index 74081a65b6f2..000000000000
--- a/arch/tile/include/arch/trio_pcie_rc_def.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_TRIO_PCIE_RC_DEF_H__
-#define __ARCH_TRIO_PCIE_RC_DEF_H__
-#define TRIO_PCIE_RC_DEVICE_CAP 0x0074
-#define TRIO_PCIE_RC_DEVICE_CONTROL 0x0078
-#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID 0x0000
-#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT 16
-#define TRIO_PCIE_RC_REVISION_ID 0x0008
-#endif /* !defined(__ARCH_TRIO_PCIE_RC_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_shm.h b/arch/tile/include/arch/trio_shm.h
deleted file mode 100644
index 3382e38245af..000000000000
--- a/arch/tile/include/arch/trio_shm.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-
-#ifndef __ARCH_TRIO_SHM_H__
-#define __ARCH_TRIO_SHM_H__
-
-#include <arch/abi.h>
-#include <arch/trio_shm_def.h>
-
-#ifndef __ASSEMBLER__
-/**
- * TRIO DMA Descriptor.
- * The TRIO DMA descriptor is written by software and consumed by hardware.
- * It is used to specify the location of transaction data in the IO and Tile
- * domains.
- */
-
-__extension__
-typedef union
-{
- struct
- {
- /* Word 0 */
-
-#ifndef __BIG_ENDIAN__
- /** Tile side virtual address. */
- int_reg_t va : 42;
- /**
- * Encoded size of buffer used on push DMA when C=1:
- * 0 = 128 bytes
- * 1 = 256 bytes
- * 2 = 512 bytes
- * 3 = 1024 bytes
- * 4 = 1664 bytes
- * 5 = 4096 bytes
- * 6 = 10368 bytes
- * 7 = 16384 bytes
- */
- uint_reg_t bsz : 3;
- /**
- * Chaining designation. Always zero for pull DMA
- * 0 : Unchained buffer pointer
- * 1 : Chained buffer pointer. Next buffer descriptor (e.g. VA) stored
- * in 1st 8-bytes in buffer. For chained buffers, first 8-bytes of each
- * buffer contain the next buffer descriptor formatted exactly like a PDE
- * buffer descriptor. This allows a chained PDE buffer to be sent using
- * push DMA.
- */
- uint_reg_t c : 1;
- /**
- * Notification interrupt will be delivered when the transaction has
- * completed (all data has been read from or written to the Tile-side
- * buffer).
- */
- uint_reg_t notif : 1;
- /**
- * When 0, the XSIZE field specifies the total byte count for the
- * transaction. When 1, the XSIZE field is encoded as 2^(N+14) for N in
- * {0..6}:
- * 0 = 16KB
- * 1 = 32KB
- * 2 = 64KB
- * 3 = 128KB
- * 4 = 256KB
- * 5 = 512KB
- * 6 = 1MB
- * All other encodings of the XSIZE field are reserved when SMOD=1
- */
- uint_reg_t smod : 1;
- /**
- * Total number of bytes to move for this transaction. When SMOD=1,
- * this field is encoded - see SMOD description.
- */
- uint_reg_t xsize : 14;
- /** Reserved. */
- uint_reg_t __reserved_0 : 1;
- /**
- * Generation number. Used to indicate a valid descriptor in ring. When
- * a new descriptor is written into the ring, software must toggle this
- * bit. The net effect is that the GEN bit being written into new
- * descriptors toggles each time the ring tail pointer wraps.
- */
- uint_reg_t gen : 1;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t gen : 1;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t xsize : 14;
- uint_reg_t smod : 1;
- uint_reg_t notif : 1;
- uint_reg_t c : 1;
- uint_reg_t bsz : 3;
- int_reg_t va : 42;
-#endif
-
- /* Word 1 */
-
-#ifndef __BIG_ENDIAN__
- /** IO-side address */
- uint_reg_t io_address : 64;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t io_address : 64;
-#endif
-
- };
-
- /** Word access */
- uint_reg_t words[2];
-} TRIO_DMA_DESC_t;
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_TRIO_SHM_H__) */
diff --git a/arch/tile/include/arch/trio_shm_def.h b/arch/tile/include/arch/trio_shm_def.h
deleted file mode 100644
index 72a59c88b06a..000000000000
--- a/arch/tile/include/arch/trio_shm_def.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_TRIO_SHM_DEF_H__
-#define __ARCH_TRIO_SHM_DEF_H__
-#endif /* !defined(__ARCH_TRIO_SHM_DEF_H__) */
diff --git a/arch/tile/include/arch/uart.h b/arch/tile/include/arch/uart.h
deleted file mode 100644
index 07966970adad..000000000000
--- a/arch/tile/include/arch/uart.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_UART_H__
-#define __ARCH_UART_H__
-
-#include <arch/abi.h>
-#include <arch/uart_def.h>
-
-#ifndef __ASSEMBLER__
-
-/* Divisor. */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * Baud Rate Divisor. Desired_baud_rate = REF_CLK frequency / (baud *
- * 16).
- * Note: REF_CLK is always 125 MHz, the default
- * divisor = 68, baud rate = 125M/(68*16) = 115200 baud.
- */
- uint_reg_t divisor : 12;
- /* Reserved. */
- uint_reg_t __reserved : 52;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved : 52;
- uint_reg_t divisor : 12;
-#endif
- };
-
- uint_reg_t word;
-} UART_DIVISOR_t;
-
-/* FIFO Count. */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /*
- * n: n active entries in the receive FIFO (max is 2**8). Each entry has
- * 8 bits.
- * 0: no active entry in the receive FIFO (that is empty).
- */
- uint_reg_t rfifo_count : 9;
- /* Reserved. */
- uint_reg_t __reserved_0 : 7;
- /*
- * n: n active entries in the transmit FIFO (max is 2**8). Each entry has
- * 8 bits.
- * 0: no active entry in the transmit FIFO (that is empty).
- */
- uint_reg_t tfifo_count : 9;
- /* Reserved. */
- uint_reg_t __reserved_1 : 7;
- /*
- * n: n active entries in the write FIFO (max is 2**2). Each entry has 8
- * bits.
- * 0: no active entry in the write FIFO (that is empty).
- */
- uint_reg_t wfifo_count : 3;
- /* Reserved. */
- uint_reg_t __reserved_2 : 29;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_2 : 29;
- uint_reg_t wfifo_count : 3;
- uint_reg_t __reserved_1 : 7;
- uint_reg_t tfifo_count : 9;
- uint_reg_t __reserved_0 : 7;
- uint_reg_t rfifo_count : 9;
-#endif
- };
-
- uint_reg_t word;
-} UART_FIFO_COUNT_t;
-
-/* FLAG. */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Reserved. */
- uint_reg_t __reserved_0 : 1;
- /* 1: receive FIFO is empty */
- uint_reg_t rfifo_empty : 1;
- /* 1: write FIFO is empty. */
- uint_reg_t wfifo_empty : 1;
- /* 1: transmit FIFO is empty. */
- uint_reg_t tfifo_empty : 1;
- /* 1: receive FIFO is full. */
- uint_reg_t rfifo_full : 1;
- /* 1: write FIFO is full. */
- uint_reg_t wfifo_full : 1;
- /* 1: transmit FIFO is full. */
- uint_reg_t tfifo_full : 1;
- /* Reserved. */
- uint_reg_t __reserved_1 : 57;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_1 : 57;
- uint_reg_t tfifo_full : 1;
- uint_reg_t wfifo_full : 1;
- uint_reg_t rfifo_full : 1;
- uint_reg_t tfifo_empty : 1;
- uint_reg_t wfifo_empty : 1;
- uint_reg_t rfifo_empty : 1;
- uint_reg_t __reserved_0 : 1;
-#endif
- };
-
- uint_reg_t word;
-} UART_FLAG_t;
-
-/*
- * Interrupt Vector Mask.
- * Each bit in this register corresponds to a specific interrupt. When set,
- * the associated interrupt will not be dispatched.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Read data FIFO read and no data available */
- uint_reg_t rdat_err : 1;
- /* Write FIFO was written but it was full */
- uint_reg_t wdat_err : 1;
- /* Stop bit not found when current data was received */
- uint_reg_t frame_err : 1;
- /* Parity error was detected when current data was received */
- uint_reg_t parity_err : 1;
- /* Data was received but the receive FIFO was full */
- uint_reg_t rfifo_overflow : 1;
- /*
- * An almost full event is reached when data is to be written to the
- * receive FIFO, and the receive FIFO has more than or equal to
- * BUFFER_THRESHOLD.RFIFO_AFULL bytes.
- */
- uint_reg_t rfifo_afull : 1;
- /* Reserved. */
- uint_reg_t __reserved_0 : 1;
- /* An entry in the transmit FIFO was popped */
- uint_reg_t tfifo_re : 1;
- /* An entry has been pushed into the receive FIFO */
- uint_reg_t rfifo_we : 1;
- /* An entry of the write FIFO has been popped */
- uint_reg_t wfifo_re : 1;
- /* Rshim read receive FIFO in protocol mode */
- uint_reg_t rfifo_err : 1;
- /*
- * An almost empty event is reached when data is to be read from the
- * transmit FIFO, and the transmit FIFO has less than or equal to
- * BUFFER_THRESHOLD.TFIFO_AEMPTY bytes.
- */
- uint_reg_t tfifo_aempty : 1;
- /* Reserved. */
- uint_reg_t __reserved_1 : 52;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_1 : 52;
- uint_reg_t tfifo_aempty : 1;
- uint_reg_t rfifo_err : 1;
- uint_reg_t wfifo_re : 1;
- uint_reg_t rfifo_we : 1;
- uint_reg_t tfifo_re : 1;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t rfifo_afull : 1;
- uint_reg_t rfifo_overflow : 1;
- uint_reg_t parity_err : 1;
- uint_reg_t frame_err : 1;
- uint_reg_t wdat_err : 1;
- uint_reg_t rdat_err : 1;
-#endif
- };
-
- uint_reg_t word;
-} UART_INTERRUPT_MASK_t;
-
-/*
- * Interrupt vector, write-one-to-clear.
- * Each bit in this register corresponds to a specific interrupt. Hardware
- * sets the bit when the associated condition has occurred. Writing a 1
- * clears the status bit.
- */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Read data FIFO read and no data available */
- uint_reg_t rdat_err : 1;
- /* Write FIFO was written but it was full */
- uint_reg_t wdat_err : 1;
- /* Stop bit not found when current data was received */
- uint_reg_t frame_err : 1;
- /* Parity error was detected when current data was received */
- uint_reg_t parity_err : 1;
- /* Data was received but the receive FIFO was full */
- uint_reg_t rfifo_overflow : 1;
- /*
- * Data was received and the receive FIFO is now almost full (more than
- * BUFFER_THRESHOLD.RFIFO_AFULL bytes in it)
- */
- uint_reg_t rfifo_afull : 1;
- /* Reserved. */
- uint_reg_t __reserved_0 : 1;
- /* An entry in the transmit FIFO was popped */
- uint_reg_t tfifo_re : 1;
- /* An entry has been pushed into the receive FIFO */
- uint_reg_t rfifo_we : 1;
- /* An entry of the write FIFO has been popped */
- uint_reg_t wfifo_re : 1;
- /* Rshim read receive FIFO in protocol mode */
- uint_reg_t rfifo_err : 1;
- /*
- * Data was read from the transmit FIFO and now it is almost empty (less
- * than or equal to BUFFER_THRESHOLD.TFIFO_AEMPTY bytes in it).
- */
- uint_reg_t tfifo_aempty : 1;
- /* Reserved. */
- uint_reg_t __reserved_1 : 52;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_1 : 52;
- uint_reg_t tfifo_aempty : 1;
- uint_reg_t rfifo_err : 1;
- uint_reg_t wfifo_re : 1;
- uint_reg_t rfifo_we : 1;
- uint_reg_t tfifo_re : 1;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t rfifo_afull : 1;
- uint_reg_t rfifo_overflow : 1;
- uint_reg_t parity_err : 1;
- uint_reg_t frame_err : 1;
- uint_reg_t wdat_err : 1;
- uint_reg_t rdat_err : 1;
-#endif
- };
-
- uint_reg_t word;
-} UART_INTERRUPT_STATUS_t;
-
-/* Type. */
-
-__extension__
-typedef union
-{
- struct
- {
-#ifndef __BIG_ENDIAN__
- /* Number of stop bits, rx and tx */
- uint_reg_t sbits : 1;
- /* Reserved. */
- uint_reg_t __reserved_0 : 1;
- /* Data word size, rx and tx */
- uint_reg_t dbits : 1;
- /* Reserved. */
- uint_reg_t __reserved_1 : 1;
- /* Parity selection, rx and tx */
- uint_reg_t ptype : 3;
- /* Reserved. */
- uint_reg_t __reserved_2 : 57;
-#else /* __BIG_ENDIAN__ */
- uint_reg_t __reserved_2 : 57;
- uint_reg_t ptype : 3;
- uint_reg_t __reserved_1 : 1;
- uint_reg_t dbits : 1;
- uint_reg_t __reserved_0 : 1;
- uint_reg_t sbits : 1;
-#endif
- };
-
- uint_reg_t word;
-} UART_TYPE_t;
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_UART_H__) */
diff --git a/arch/tile/include/arch/uart_def.h b/arch/tile/include/arch/uart_def.h
deleted file mode 100644
index 42bcaf535379..000000000000
--- a/arch/tile/include/arch/uart_def.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_UART_DEF_H__
-#define __ARCH_UART_DEF_H__
-#define UART_DIVISOR 0x0158
-#define UART_FIFO_COUNT 0x0110
-#define UART_FLAG 0x0108
-#define UART_INTERRUPT_MASK 0x0208
-#define UART_INTERRUPT_MASK__RDAT_ERR_SHIFT 0
-#define UART_INTERRUPT_MASK__RDAT_ERR_WIDTH 1
-#define UART_INTERRUPT_MASK__RDAT_ERR_RESET_VAL 1
-#define UART_INTERRUPT_MASK__RDAT_ERR_RMASK 0x1
-#define UART_INTERRUPT_MASK__RDAT_ERR_MASK 0x1
-#define UART_INTERRUPT_MASK__RDAT_ERR_FIELD 0,0
-#define UART_INTERRUPT_MASK__WDAT_ERR_SHIFT 1
-#define UART_INTERRUPT_MASK__WDAT_ERR_WIDTH 1
-#define UART_INTERRUPT_MASK__WDAT_ERR_RESET_VAL 1
-#define UART_INTERRUPT_MASK__WDAT_ERR_RMASK 0x1
-#define UART_INTERRUPT_MASK__WDAT_ERR_MASK 0x2
-#define UART_INTERRUPT_MASK__WDAT_ERR_FIELD 1,1
-#define UART_INTERRUPT_MASK__FRAME_ERR_SHIFT 2
-#define UART_INTERRUPT_MASK__FRAME_ERR_WIDTH 1
-#define UART_INTERRUPT_MASK__FRAME_ERR_RESET_VAL 1
-#define UART_INTERRUPT_MASK__FRAME_ERR_RMASK 0x1
-#define UART_INTERRUPT_MASK__FRAME_ERR_MASK 0x4
-#define UART_INTERRUPT_MASK__FRAME_ERR_FIELD 2,2
-#define UART_INTERRUPT_MASK__PARITY_ERR_SHIFT 3
-#define UART_INTERRUPT_MASK__PARITY_ERR_WIDTH 1
-#define UART_INTERRUPT_MASK__PARITY_ERR_RESET_VAL 1
-#define UART_INTERRUPT_MASK__PARITY_ERR_RMASK 0x1
-#define UART_INTERRUPT_MASK__PARITY_ERR_MASK 0x8
-#define UART_INTERRUPT_MASK__PARITY_ERR_FIELD 3,3
-#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_SHIFT 4
-#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_WIDTH 1
-#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RESET_VAL 1
-#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RMASK 0x1
-#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_MASK 0x10
-#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_FIELD 4,4
-#define UART_INTERRUPT_MASK__RFIFO_AFULL_SHIFT 5
-#define UART_INTERRUPT_MASK__RFIFO_AFULL_WIDTH 1
-#define UART_INTERRUPT_MASK__RFIFO_AFULL_RESET_VAL 1
-#define UART_INTERRUPT_MASK__RFIFO_AFULL_RMASK 0x1
-#define UART_INTERRUPT_MASK__RFIFO_AFULL_MASK 0x20
-#define UART_INTERRUPT_MASK__RFIFO_AFULL_FIELD 5,5
-#define UART_INTERRUPT_MASK__TFIFO_RE_SHIFT 7
-#define UART_INTERRUPT_MASK__TFIFO_RE_WIDTH 1
-#define UART_INTERRUPT_MASK__TFIFO_RE_RESET_VAL 1
-#define UART_INTERRUPT_MASK__TFIFO_RE_RMASK 0x1
-#define UART_INTERRUPT_MASK__TFIFO_RE_MASK 0x80
-#define UART_INTERRUPT_MASK__TFIFO_RE_FIELD 7,7
-#define UART_INTERRUPT_MASK__RFIFO_WE_SHIFT 8
-#define UART_INTERRUPT_MASK__RFIFO_WE_WIDTH 1
-#define UART_INTERRUPT_MASK__RFIFO_WE_RESET_VAL 1
-#define UART_INTERRUPT_MASK__RFIFO_WE_RMASK 0x1
-#define UART_INTERRUPT_MASK__RFIFO_WE_MASK 0x100
-#define UART_INTERRUPT_MASK__RFIFO_WE_FIELD 8,8
-#define UART_INTERRUPT_MASK__WFIFO_RE_SHIFT 9
-#define UART_INTERRUPT_MASK__WFIFO_RE_WIDTH 1
-#define UART_INTERRUPT_MASK__WFIFO_RE_RESET_VAL 1
-#define UART_INTERRUPT_MASK__WFIFO_RE_RMASK 0x1
-#define UART_INTERRUPT_MASK__WFIFO_RE_MASK 0x200
-#define UART_INTERRUPT_MASK__WFIFO_RE_FIELD 9,9
-#define UART_INTERRUPT_MASK__RFIFO_ERR_SHIFT 10
-#define UART_INTERRUPT_MASK__RFIFO_ERR_WIDTH 1
-#define UART_INTERRUPT_MASK__RFIFO_ERR_RESET_VAL 1
-#define UART_INTERRUPT_MASK__RFIFO_ERR_RMASK 0x1
-#define UART_INTERRUPT_MASK__RFIFO_ERR_MASK 0x400
-#define UART_INTERRUPT_MASK__RFIFO_ERR_FIELD 10,10
-#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_SHIFT 11
-#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_WIDTH 1
-#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RESET_VAL 1
-#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RMASK 0x1
-#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_MASK 0x800
-#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_FIELD 11,11
-#define UART_INTERRUPT_STATUS 0x0200
-#define UART_RECEIVE_DATA 0x0148
-#define UART_TRANSMIT_DATA 0x0140
-#define UART_TYPE 0x0160
-#define UART_TYPE__SBITS_SHIFT 0
-#define UART_TYPE__SBITS_WIDTH 1
-#define UART_TYPE__SBITS_RESET_VAL 1
-#define UART_TYPE__SBITS_RMASK 0x1
-#define UART_TYPE__SBITS_MASK 0x1
-#define UART_TYPE__SBITS_FIELD 0,0
-#define UART_TYPE__SBITS_VAL_ONE_SBITS 0x0
-#define UART_TYPE__SBITS_VAL_TWO_SBITS 0x1
-#define UART_TYPE__DBITS_SHIFT 2
-#define UART_TYPE__DBITS_WIDTH 1
-#define UART_TYPE__DBITS_RESET_VAL 0
-#define UART_TYPE__DBITS_RMASK 0x1
-#define UART_TYPE__DBITS_MASK 0x4
-#define UART_TYPE__DBITS_FIELD 2,2
-#define UART_TYPE__DBITS_VAL_EIGHT_DBITS 0x0
-#define UART_TYPE__DBITS_VAL_SEVEN_DBITS 0x1
-#define UART_TYPE__PTYPE_SHIFT 4
-#define UART_TYPE__PTYPE_WIDTH 3
-#define UART_TYPE__PTYPE_RESET_VAL 3
-#define UART_TYPE__PTYPE_RMASK 0x7
-#define UART_TYPE__PTYPE_MASK 0x70
-#define UART_TYPE__PTYPE_FIELD 4,6
-#define UART_TYPE__PTYPE_VAL_NONE 0x0
-#define UART_TYPE__PTYPE_VAL_MARK 0x1
-#define UART_TYPE__PTYPE_VAL_SPACE 0x2
-#define UART_TYPE__PTYPE_VAL_EVEN 0x3
-#define UART_TYPE__PTYPE_VAL_ODD 0x4
-#endif /* !defined(__ARCH_UART_DEF_H__) */
diff --git a/arch/tile/include/arch/usb_host.h b/arch/tile/include/arch/usb_host.h
deleted file mode 100644
index d09f32683962..000000000000
--- a/arch/tile/include/arch/usb_host.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_USB_HOST_H__
-#define __ARCH_USB_HOST_H__
-
-#include <arch/abi.h>
-#include <arch/usb_host_def.h>
-
-#ifndef __ASSEMBLER__
-#endif /* !defined(__ASSEMBLER__) */
-
-#endif /* !defined(__ARCH_USB_HOST_H__) */
diff --git a/arch/tile/include/arch/usb_host_def.h b/arch/tile/include/arch/usb_host_def.h
deleted file mode 100644
index aeed7753e8e1..000000000000
--- a/arch/tile/include/arch/usb_host_def.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Machine-generated file; do not edit. */
-
-#ifndef __ARCH_USB_HOST_DEF_H__
-#define __ARCH_USB_HOST_DEF_H__
-#endif /* !defined(__ARCH_USB_HOST_DEF_H__) */
diff --git a/arch/tile/include/asm/Kbuild b/arch/tile/include/asm/Kbuild
deleted file mode 100644
index 414dfc3a1808..000000000000
--- a/arch/tile/include/asm/Kbuild
+++ /dev/null
@@ -1,18 +0,0 @@
-generic-y += bug.h
-generic-y += bugs.h
-generic-y += emergency-restart.h
-generic-y += exec.h
-generic-y += extable.h
-generic-y += fb.h
-generic-y += hw_irq.h
-generic-y += irq_regs.h
-generic-y += local.h
-generic-y += local64.h
-generic-y += mcs_spinlock.h
-generic-y += mm-arch-hooks.h
-generic-y += parport.h
-generic-y += preempt.h
-generic-y += seccomp.h
-generic-y += serial.h
-generic-y += trace_clock.h
-generic-y += xor.h
diff --git a/arch/tile/include/asm/asm-offsets.h b/arch/tile/include/asm/asm-offsets.h
deleted file mode 100644
index d370ee36a182..000000000000
--- a/arch/tile/include/asm/asm-offsets.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <generated/asm-offsets.h>
diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h
deleted file mode 100644
index 8dda3c8ff5ab..000000000000
--- a/arch/tile/include/asm/atomic.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Atomic primitives.
- */
-
-#ifndef _ASM_TILE_ATOMIC_H
-#define _ASM_TILE_ATOMIC_H
-
-#include <asm/cmpxchg.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-#define ATOMIC_INIT(i) { (i) }
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-static inline int atomic_read(const atomic_t *v)
-{
- return READ_ONCE(v->counter);
-}
-
-/**
- * atomic_sub_return - subtract integer and return
- * @v: pointer of type atomic_t
- * @i: integer value to subtract
- *
- * Atomically subtracts @i from @v and returns @v - @i
- */
-#define atomic_sub_return(i, v) atomic_add_return((int)(-(i)), (v))
-
-#define atomic_fetch_sub(i, v) atomic_fetch_add(-(int)(i), (v))
-
-/**
- * atomic_sub - subtract integer from atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-#define atomic_sub(i, v) atomic_add((int)(-(i)), (v))
-
-/**
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns true if the result is
- * zero, or false for all other cases.
- */
-#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
-
-/**
- * atomic_inc_return - increment memory and return
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1 and returns the new value.
- */
-#define atomic_inc_return(v) atomic_add_return(1, (v))
-
-/**
- * atomic_dec_return - decrement memory and return
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and returns the new value.
- */
-#define atomic_dec_return(v) atomic_sub_return(1, (v))
-
-/**
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-#define atomic_inc(v) atomic_add(1, (v))
-
-/**
- * atomic_dec - decrement atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-#define atomic_dec(v) atomic_sub(1, (v))
-
-/**
- * atomic_dec_and_test - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and returns true if the result is 0.
- */
-#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
-
-/**
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1 and returns true if the result is 0.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-/**
- * atomic_xchg - atomically exchange contents of memory with a new value
- * @v: pointer of type atomic_t
- * @i: integer value to store in memory
- *
- * Atomically sets @v to @i and returns old @v
- */
-static inline int atomic_xchg(atomic_t *v, int n)
-{
- return xchg(&v->counter, n);
-}
-
-/**
- * atomic_cmpxchg - atomically exchange contents of memory if it matches
- * @v: pointer of type atomic_t
- * @o: old value that memory should have
- * @n: new value to write to memory if it matches
- *
- * Atomically checks if @v holds @o and replaces it with @n if so.
- * Returns the old value at @v.
- */
-static inline int atomic_cmpxchg(atomic_t *v, int o, int n)
-{
- return cmpxchg(&v->counter, o, n);
-}
-
-/**
- * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true if the result is
- * negative, or false when result is greater than or equal to zero.
- */
-#define atomic_add_negative(i, v) (atomic_add_return((i), (v)) < 0)
-
-#endif /* __ASSEMBLY__ */
-
-#ifndef __tilegx__
-#include <asm/atomic_32.h>
-#else
-#include <asm/atomic_64.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-/**
- * atomic64_xchg - atomically exchange contents of memory with a new value
- * @v: pointer of type atomic64_t
- * @i: integer value to store in memory
- *
- * Atomically sets @v to @i and returns old @v
- */
-static inline long long atomic64_xchg(atomic64_t *v, long long n)
-{
- return xchg64(&v->counter, n);
-}
-
-/**
- * atomic64_cmpxchg - atomically exchange contents of memory if it matches
- * @v: pointer of type atomic64_t
- * @o: old value that memory should have
- * @n: new value to write to memory if it matches
- *
- * Atomically checks if @v holds @o and replaces it with @n if so.
- * Returns the old value at @v.
- */
-static inline long long atomic64_cmpxchg(atomic64_t *v, long long o,
- long long n)
-{
- return cmpxchg64(&v->counter, o, n);
-}
-
-static inline long long atomic64_dec_if_positive(atomic64_t *v)
-{
- long long c, old, dec;
-
- c = atomic64_read(v);
- for (;;) {
- dec = c - 1;
- if (unlikely(dec < 0))
- break;
- old = atomic64_cmpxchg((v), c, dec);
- if (likely(old == c))
- break;
- c = old;
- }
- return dec;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_TILE_ATOMIC_H */
diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h
deleted file mode 100644
index 53a423e7cb92..000000000000
--- a/arch/tile/include/asm/atomic_32.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Do not include directly; use <linux/atomic.h>.
- */
-
-#ifndef _ASM_TILE_ATOMIC_32_H
-#define _ASM_TILE_ATOMIC_32_H
-
-#include <asm/barrier.h>
-#include <arch/chip.h>
-
-#ifndef __ASSEMBLY__
-
-/**
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic_add(int i, atomic_t *v)
-{
- _atomic_xchg_add(&v->counter, i);
-}
-
-#define ATOMIC_OPS(op) \
-unsigned long _atomic_fetch_##op(volatile unsigned long *p, unsigned long mask); \
-static inline void atomic_##op(int i, atomic_t *v) \
-{ \
- _atomic_fetch_##op((unsigned long *)&v->counter, i); \
-} \
-static inline int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- smp_mb(); \
- return _atomic_fetch_##op((unsigned long *)&v->counter, i); \
-}
-
-ATOMIC_OPS(and)
-ATOMIC_OPS(or)
-ATOMIC_OPS(xor)
-
-#undef ATOMIC_OPS
-
-static inline int atomic_fetch_add(int i, atomic_t *v)
-{
- smp_mb();
- return _atomic_xchg_add(&v->counter, i);
-}
-
-/**
- * atomic_add_return - add integer and return
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline int atomic_add_return(int i, atomic_t *v)
-{
- smp_mb(); /* barrier for proper semantics */
- return _atomic_xchg_add(&v->counter, i) + i;
-}
-
-/**
- * __atomic_add_unless - add unless the number is already a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as @v was not already @u.
- * Returns the old value of @v.
- */
-static inline int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- smp_mb(); /* barrier for proper semantics */
- return _atomic_xchg_add_unless(&v->counter, a, u);
-}
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- *
- * atomic_set() can't be just a raw store, since it would be lost if it
- * fell between the load and store of one of the other atomic ops.
- */
-static inline void atomic_set(atomic_t *v, int n)
-{
- _atomic_xchg(&v->counter, n);
-}
-
-#define atomic_set_release(v, i) atomic_set((v), (i))
-
-/* A 64bit atomic type */
-
-typedef struct {
- long long counter;
-} atomic64_t;
-
-#define ATOMIC64_INIT(val) { (val) }
-
-/**
- * atomic64_read - read atomic variable
- * @v: pointer of type atomic64_t
- *
- * Atomically reads the value of @v.
- */
-static inline long long atomic64_read(const atomic64_t *v)
-{
- /*
- * Requires an atomic op to read both 32-bit parts consistently.
- * Casting away const is safe since the atomic support routines
- * do not write to memory if the value has not been modified.
- */
- return _atomic64_xchg_add((long long *)&v->counter, 0);
-}
-
-/**
- * atomic64_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic64_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic64_add(long long i, atomic64_t *v)
-{
- _atomic64_xchg_add(&v->counter, i);
-}
-
-#define ATOMIC64_OPS(op) \
-long long _atomic64_fetch_##op(long long *v, long long n); \
-static inline void atomic64_##op(long long i, atomic64_t *v) \
-{ \
- _atomic64_fetch_##op(&v->counter, i); \
-} \
-static inline long long atomic64_fetch_##op(long long i, atomic64_t *v) \
-{ \
- smp_mb(); \
- return _atomic64_fetch_##op(&v->counter, i); \
-}
-
-ATOMIC64_OPS(and)
-ATOMIC64_OPS(or)
-ATOMIC64_OPS(xor)
-
-#undef ATOMIC64_OPS
-
-static inline long long atomic64_fetch_add(long long i, atomic64_t *v)
-{
- smp_mb();
- return _atomic64_xchg_add(&v->counter, i);
-}
-
-/**
- * atomic64_add_return - add integer and return
- * @v: pointer of type atomic64_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline long long atomic64_add_return(long long i, atomic64_t *v)
-{
- smp_mb(); /* barrier for proper semantics */
- return _atomic64_xchg_add(&v->counter, i) + i;
-}
-
-/**
- * atomic64_add_unless - add unless the number is already a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as @v was not already @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline long long atomic64_add_unless(atomic64_t *v, long long a,
- long long u)
-{
- smp_mb(); /* barrier for proper semantics */
- return _atomic64_xchg_add_unless(&v->counter, a, u) != u;
-}
-
-/**
- * atomic64_set - set atomic variable
- * @v: pointer of type atomic64_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- *
- * atomic64_set() can't be just a raw store, since it would be lost if it
- * fell between the load and store of one of the other atomic ops.
- */
-static inline void atomic64_set(atomic64_t *v, long long n)
-{
- _atomic64_xchg(&v->counter, n);
-}
-
-#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
-#define atomic64_inc(v) atomic64_add(1LL, (v))
-#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
-#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
-#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
-#define atomic64_fetch_sub(i, v) atomic64_fetch_add(-(i), (v))
-#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
-#define atomic64_sub(i, v) atomic64_add(-(i), (v))
-#define atomic64_dec(v) atomic64_sub(1LL, (v))
-#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
-#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Internal definitions only beyond this point.
- */
-
-/*
- * Number of atomic locks in atomic_locks[]. Must be a power of two.
- * There is no reason for more than PAGE_SIZE / 8 entries, since that
- * is the maximum number of pointer bits we can use to index this.
- * And we cannot have more than PAGE_SIZE / 4, since this has to
- * fit on a single page and each entry takes 4 bytes.
- */
-#define ATOMIC_HASH_SHIFT (PAGE_SHIFT - 3)
-#define ATOMIC_HASH_SIZE (1 << ATOMIC_HASH_SHIFT)
-
-#ifndef __ASSEMBLY__
-extern int atomic_locks[];
-#endif
-
-/*
- * All the code that may fault while holding an atomic lock must
- * place the pointer to the lock in ATOMIC_LOCK_REG so the fault code
- * can correctly release and reacquire the lock. Note that we
- * mention the register number in a comment in "lib/atomic_asm.S" to help
- * assembly coders from using this register by mistake, so if it
- * is changed here, change that comment as well.
- */
-#define ATOMIC_LOCK_REG 20
-#define ATOMIC_LOCK_REG_NAME r20
-
-#ifndef __ASSEMBLY__
-/* Called from setup to initialize a hash table to point to per_cpu locks. */
-void __init_atomic_per_cpu(void);
-
-#ifdef CONFIG_SMP
-/* Support releasing the atomic lock in do_page_fault_ics(). */
-void __atomic_fault_unlock(int *lock_ptr);
-#endif
-
-/* Return a pointer to the lock for the given address. */
-int *__atomic_hashed_lock(volatile void *v);
-
-/* Private helper routines in lib/atomic_asm_32.S */
-struct __get_user {
- unsigned long val;
- int err;
-};
-extern struct __get_user __atomic32_cmpxchg(volatile int *p,
- int *lock, int o, int n);
-extern struct __get_user __atomic32_xchg(volatile int *p, int *lock, int n);
-extern struct __get_user __atomic32_xchg_add(volatile int *p, int *lock, int n);
-extern struct __get_user __atomic32_xchg_add_unless(volatile int *p,
- int *lock, int o, int n);
-extern struct __get_user __atomic32_fetch_or(volatile int *p, int *lock, int n);
-extern struct __get_user __atomic32_fetch_and(volatile int *p, int *lock, int n);
-extern struct __get_user __atomic32_fetch_andn(volatile int *p, int *lock, int n);
-extern struct __get_user __atomic32_fetch_xor(volatile int *p, int *lock, int n);
-extern long long __atomic64_cmpxchg(volatile long long *p, int *lock,
- long long o, long long n);
-extern long long __atomic64_xchg(volatile long long *p, int *lock, long long n);
-extern long long __atomic64_xchg_add(volatile long long *p, int *lock,
- long long n);
-extern long long __atomic64_xchg_add_unless(volatile long long *p,
- int *lock, long long o, long long n);
-extern long long __atomic64_fetch_and(volatile long long *p, int *lock, long long n);
-extern long long __atomic64_fetch_or(volatile long long *p, int *lock, long long n);
-extern long long __atomic64_fetch_xor(volatile long long *p, int *lock, long long n);
-
-/* Return failure from the atomic wrappers. */
-struct __get_user __atomic_bad_address(int __user *addr);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_TILE_ATOMIC_32_H */
diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h
deleted file mode 100644
index 4cefa0c9fd81..000000000000
--- a/arch/tile/include/asm/atomic_64.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Do not include directly; use <linux/atomic.h>.
- */
-
-#ifndef _ASM_TILE_ATOMIC_64_H
-#define _ASM_TILE_ATOMIC_64_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/barrier.h>
-#include <arch/spr_def.h>
-
-/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
-
-#define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
-
-/*
- * The smp_mb() operations throughout are to support the fact that
- * Linux requires memory barriers before and after the operation,
- * on any routine which updates memory and returns a value.
- */
-
-/*
- * Note a subtlety of the locking here. We are required to provide a
- * full memory barrier before and after the operation. However, we
- * only provide an explicit mb before the operation. After the
- * operation, we use barrier() to get a full mb for free, because:
- *
- * (1) The barrier directive to the compiler prohibits any instructions
- * being statically hoisted before the barrier;
- * (2) the microarchitecture will not issue any further instructions
- * until the fetchadd result is available for the "+ i" add instruction;
- * (3) the smb_mb before the fetchadd ensures that no other memory
- * operations are in flight at this point.
- */
-static inline int atomic_add_return(int i, atomic_t *v)
-{
- int val;
- smp_mb(); /* barrier for proper semantics */
- val = __insn_fetchadd4((void *)&v->counter, i) + i;
- barrier(); /* equivalent to smp_mb(); see block comment above */
- return val;
-}
-
-#define ATOMIC_OPS(op) \
-static inline int atomic_fetch_##op(int i, atomic_t *v) \
-{ \
- int val; \
- smp_mb(); \
- val = __insn_fetch##op##4((void *)&v->counter, i); \
- smp_mb(); \
- return val; \
-} \
-static inline void atomic_##op(int i, atomic_t *v) \
-{ \
- __insn_fetch##op##4((void *)&v->counter, i); \
-}
-
-ATOMIC_OPS(add)
-ATOMIC_OPS(and)
-ATOMIC_OPS(or)
-
-#undef ATOMIC_OPS
-
-static inline int atomic_fetch_xor(int i, atomic_t *v)
-{
- int guess, oldval = v->counter;
- smp_mb();
- do {
- guess = oldval;
- __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
- oldval = __insn_cmpexch4(&v->counter, guess ^ i);
- } while (guess != oldval);
- smp_mb();
- return oldval;
-}
-
-static inline void atomic_xor(int i, atomic_t *v)
-{
- int guess, oldval = v->counter;
- do {
- guess = oldval;
- __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
- oldval = __insn_cmpexch4(&v->counter, guess ^ i);
- } while (guess != oldval);
-}
-
-static inline int __atomic_add_unless(atomic_t *v, int a, int u)
-{
- int guess, oldval = v->counter;
- do {
- if (oldval == u)
- break;
- guess = oldval;
- oldval = cmpxchg(&v->counter, guess, guess + a);
- } while (guess != oldval);
- return oldval;
-}
-
-/* Now the true 64-bit operations. */
-
-#define ATOMIC64_INIT(i) { (i) }
-
-#define atomic64_read(v) READ_ONCE((v)->counter)
-#define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
-
-static inline long atomic64_add_return(long i, atomic64_t *v)
-{
- int val;
- smp_mb(); /* barrier for proper semantics */
- val = __insn_fetchadd((void *)&v->counter, i) + i;
- barrier(); /* equivalent to smp_mb; see atomic_add_return() */
- return val;
-}
-
-#define ATOMIC64_OPS(op) \
-static inline long atomic64_fetch_##op(long i, atomic64_t *v) \
-{ \
- long val; \
- smp_mb(); \
- val = __insn_fetch##op((void *)&v->counter, i); \
- smp_mb(); \
- return val; \
-} \
-static inline void atomic64_##op(long i, atomic64_t *v) \
-{ \
- __insn_fetch##op((void *)&v->counter, i); \
-}
-
-ATOMIC64_OPS(add)
-ATOMIC64_OPS(and)
-ATOMIC64_OPS(or)
-
-#undef ATOMIC64_OPS
-
-static inline long atomic64_fetch_xor(long i, atomic64_t *v)
-{
- long guess, oldval = v->counter;
- smp_mb();
- do {
- guess = oldval;
- __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
- oldval = __insn_cmpexch(&v->counter, guess ^ i);
- } while (guess != oldval);
- smp_mb();
- return oldval;
-}
-
-static inline void atomic64_xor(long i, atomic64_t *v)
-{
- long guess, oldval = v->counter;
- do {
- guess = oldval;
- __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
- oldval = __insn_cmpexch(&v->counter, guess ^ i);
- } while (guess != oldval);
-}
-
-static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
-{
- long guess, oldval = v->counter;
- do {
- if (oldval == u)
- break;
- guess = oldval;
- oldval = cmpxchg(&v->counter, guess, guess + a);
- } while (guess != oldval);
- return oldval != u;
-}
-
-#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
-#define atomic64_fetch_sub(i, v) atomic64_fetch_add(-(i), (v))
-#define atomic64_sub(i, v) atomic64_add(-(i), (v))
-#define atomic64_inc_return(v) atomic64_add_return(1, (v))
-#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
-#define atomic64_inc(v) atomic64_add(1, (v))
-#define atomic64_dec(v) atomic64_sub(1, (v))
-
-#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
-#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
-#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
-#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_TILE_ATOMIC_64_H */
diff --git a/arch/tile/include/asm/backtrace.h b/arch/tile/include/asm/backtrace.h
deleted file mode 100644
index bd5399a69edf..000000000000
--- a/arch/tile/include/asm/backtrace.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_BACKTRACE_H
-#define _ASM_TILE_BACKTRACE_H
-
-#include <linux/types.h>
-
-/* Reads 'size' bytes from 'address' and writes the data to 'result'.
- * Returns true if successful, else false (e.g. memory not readable).
- */
-typedef bool (*BacktraceMemoryReader)(void *result,
- unsigned long address,
- unsigned int size,
- void *extra);
-
-typedef struct {
- /* Current PC. */
- unsigned long pc;
-
- /* Current stack pointer value. */
- unsigned long sp;
-
- /* Current frame pointer value (i.e. caller's stack pointer) */
- unsigned long fp;
-
- /* Internal use only: caller's PC for first frame. */
- unsigned long initial_frame_caller_pc;
-
- /* Internal use only: callback to read memory. */
- BacktraceMemoryReader read_memory_func;
-
- /* Internal use only: arbitrary argument to read_memory_func. */
- void *read_memory_func_extra;
-
-} BacktraceIterator;
-
-
-typedef enum {
-
- /* We have no idea what the caller's pc is. */
- PC_LOC_UNKNOWN,
-
- /* The caller's pc is currently in lr. */
- PC_LOC_IN_LR,
-
- /* The caller's pc can be found by dereferencing the caller's sp. */
- PC_LOC_ON_STACK
-
-} CallerPCLocation;
-
-
-typedef enum {
-
- /* We have no idea what the caller's sp is. */
- SP_LOC_UNKNOWN,
-
- /* The caller's sp is currently in r52. */
- SP_LOC_IN_R52,
-
- /* The caller's sp can be found by adding a certain constant
- * to the current value of sp.
- */
- SP_LOC_OFFSET
-
-} CallerSPLocation;
-
-
-/* Bit values ORed into CALLER_* values for info ops. */
-enum {
- /* Setting the low bit on any of these values means the info op
- * applies only to one bundle ago.
- */
- ONE_BUNDLE_AGO_FLAG = 1,
-
- /* Setting this bit on a CALLER_SP_* value means the PC is in LR.
- * If not set, PC is on the stack.
- */
- PC_IN_LR_FLAG = 2,
-
- /* This many of the low bits of a CALLER_SP_* value are for the
- * flag bits above.
- */
- NUM_INFO_OP_FLAGS = 2,
-
- /* We cannot have one in the memory pipe so this is the maximum. */
- MAX_INFO_OPS_PER_BUNDLE = 2
-};
-
-
-/* Internal constants used to define 'info' operands. */
-enum {
- /* 0 and 1 are reserved, as are all negative numbers. */
-
- CALLER_UNKNOWN_BASE = 2,
-
- CALLER_SP_IN_R52_BASE = 4,
-
- CALLER_SP_OFFSET_BASE = 8,
-};
-
-
-/* Current backtracer state describing where it thinks the caller is. */
-typedef struct {
- /*
- * Public fields
- */
-
- /* How do we find the caller's PC? */
- CallerPCLocation pc_location : 8;
-
- /* How do we find the caller's SP? */
- CallerSPLocation sp_location : 8;
-
- /* If sp_location == SP_LOC_OFFSET, then caller_sp == sp +
- * loc->sp_offset. Else this field is undefined.
- */
- uint16_t sp_offset;
-
- /* In the most recently visited bundle a terminating bundle? */
- bool at_terminating_bundle;
-
- /*
- * Private fields
- */
-
- /* Will the forward scanner see someone clobbering sp
- * (i.e. changing it with something other than addi sp, sp, N?)
- */
- bool sp_clobber_follows;
-
- /* Operand to next "visible" info op (no more than one bundle past
- * the next terminating bundle), or -32768 if none.
- */
- int16_t next_info_operand;
-
- /* Is the info of in next_info_op in the very next bundle? */
- bool is_next_info_operand_adjacent;
-
-} CallerLocation;
-
-extern void backtrace_init(BacktraceIterator *state,
- BacktraceMemoryReader read_memory_func,
- void *read_memory_func_extra,
- unsigned long pc, unsigned long lr,
- unsigned long sp, unsigned long r52);
-
-
-extern bool backtrace_next(BacktraceIterator *state);
-
-#endif /* _ASM_TILE_BACKTRACE_H */
diff --git a/arch/tile/include/asm/barrier.h b/arch/tile/include/asm/barrier.h
deleted file mode 100644
index 4c419ab95ab7..000000000000
--- a/arch/tile/include/asm/barrier.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_BARRIER_H
-#define _ASM_TILE_BARRIER_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <arch/chip.h>
-#include <arch/spr_def.h>
-#include <asm/timex.h>
-
-#define __sync() __insn_mf()
-
-#include <hv/syscall_public.h>
-/*
- * Issue an uncacheable load to each memory controller, then
- * wait until those loads have completed.
- */
-static inline void __mb_incoherent(void)
-{
- long clobber_r10;
- asm volatile("swint2"
- : "=R10" (clobber_r10)
- : "R10" (HV_SYS_fence_incoherent)
- : "r0", "r1", "r2", "r3", "r4",
- "r5", "r6", "r7", "r8", "r9",
- "r11", "r12", "r13", "r14",
- "r15", "r16", "r17", "r18", "r19",
- "r20", "r21", "r22", "r23", "r24",
- "r25", "r26", "r27", "r28", "r29");
-}
-
-/* Fence to guarantee visibility of stores to incoherent memory. */
-static inline void
-mb_incoherent(void)
-{
- __insn_mf();
-
- {
-#if CHIP_HAS_TILE_WRITE_PENDING()
- const unsigned long WRITE_TIMEOUT_CYCLES = 400;
- unsigned long start = get_cycles_low();
- do {
- if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
- return;
- } while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
-#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
- (void) __mb_incoherent();
- }
-}
-
-#define fast_wmb() __sync()
-#define fast_rmb() __sync()
-#define fast_mb() __sync()
-#define fast_iob() mb_incoherent()
-
-#define wmb() fast_wmb()
-#define rmb() fast_rmb()
-#define mb() fast_mb()
-#define iob() fast_iob()
-
-#ifndef __tilegx__ /* 32 bit */
-/*
- * We need to barrier before modifying the word, since the _atomic_xxx()
- * routines just tns the lock and then read/modify/write of the word.
- * But after the word is updated, the routine issues an "mf" before returning,
- * and since it's a function call, we don't even need a compiler barrier.
- */
-#define __smp_mb__before_atomic() __smp_mb()
-#define __smp_mb__after_atomic() do { } while (0)
-#define smp_mb__after_atomic() __smp_mb__after_atomic()
-#else /* 64 bit */
-#define __smp_mb__before_atomic() __smp_mb()
-#define __smp_mb__after_atomic() __smp_mb()
-#endif
-
-/*
- * The TILE architecture does not do speculative reads; this ensures
- * that a control dependency also orders against loads and already provides
- * a LOAD->{LOAD,STORE} order and can forgo the additional RMB.
- */
-#define smp_acquire__after_ctrl_dep() barrier()
-
-#include <asm-generic/barrier.h>
-
-#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_TILE_BARRIER_H */
diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h
deleted file mode 100644
index 20caa346ac06..000000000000
--- a/arch/tile/include/asm/bitops.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright 1992, Linus Torvalds.
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_BITOPS_H
-#define _ASM_TILE_BITOPS_H
-
-#include <linux/types.h>
-#include <asm/barrier.h>
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#ifdef __tilegx__
-#include <asm/bitops_64.h>
-#else
-#include <asm/bitops_32.h>
-#endif
-
-/**
- * ffz - find first zero bit in word
- * @word: The word to search
- *
- * Undefined if no zero exists, so code should check against ~0UL first.
- */
-static inline unsigned long ffz(unsigned long word)
-{
- return __builtin_ctzl(~word);
-}
-
-static inline int fls64(__u64 w)
-{
- return (sizeof(__u64) * 8) - __builtin_clzll(w);
-}
-
-/**
- * fls - find last set bit in word
- * @x: the word to search
- *
- * This is defined in a similar way as the libc and compiler builtin
- * ffs, but returns the position of the most significant set bit.
- *
- * fls(value) returns 0 if value is 0 or the position of the last
- * set bit if value is nonzero. The last (most significant) bit is
- * at position 32.
- */
-static inline int fls(int x)
-{
- return fls64((unsigned int) x);
-}
-
-static inline unsigned int __arch_hweight32(unsigned int w)
-{
- return __builtin_popcount(w);
-}
-
-static inline unsigned int __arch_hweight16(unsigned int w)
-{
- return __builtin_popcount(w & 0xffff);
-}
-
-static inline unsigned int __arch_hweight8(unsigned int w)
-{
- return __builtin_popcount(w & 0xff);
-}
-
-static inline unsigned long __arch_hweight64(__u64 w)
-{
- return __builtin_popcountll(w);
-}
-
-#include <asm-generic/bitops/builtin-__ffs.h>
-#include <asm-generic/bitops/builtin-__fls.h>
-#include <asm-generic/bitops/builtin-ffs.h>
-#include <asm-generic/bitops/const_hweight.h>
-#include <asm-generic/bitops/lock.h>
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/non-atomic.h>
-#include <asm-generic/bitops/le.h>
-
-#endif /* _ASM_TILE_BITOPS_H */
diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h
deleted file mode 100644
index d1406a95f6b7..000000000000
--- a/arch/tile/include/asm/bitops_32.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_BITOPS_32_H
-#define _ASM_TILE_BITOPS_32_H
-
-#include <linux/compiler.h>
-#include <asm/barrier.h>
-
-/* Tile-specific routines to support <asm/bitops.h>. */
-unsigned long _atomic_fetch_or(volatile unsigned long *p, unsigned long mask);
-unsigned long _atomic_fetch_andn(volatile unsigned long *p, unsigned long mask);
-unsigned long _atomic_fetch_xor(volatile unsigned long *p, unsigned long mask);
-
-/**
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.
- * See __set_bit() if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void set_bit(unsigned nr, volatile unsigned long *addr)
-{
- _atomic_fetch_or(addr + BIT_WORD(nr), BIT_MASK(nr));
-}
-
-/**
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered.
- * See __clear_bit() if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- *
- * clear_bit() may not contain a memory barrier, so if it is used for
- * locking purposes, you should call smp_mb__before_atomic() and/or
- * smp_mb__after_atomic() to ensure changes are visible on other cpus.
- */
-static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
-{
- _atomic_fetch_andn(addr + BIT_WORD(nr), BIT_MASK(nr));
-}
-
-/**
- * change_bit - Toggle a bit in memory
- * @nr: Bit to change
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * See __change_bit() if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void change_bit(unsigned nr, volatile unsigned long *addr)
-{
- _atomic_fetch_xor(addr + BIT_WORD(nr), BIT_MASK(nr));
-}
-
-/**
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
-{
- unsigned long mask = BIT_MASK(nr);
- addr += BIT_WORD(nr);
- smp_mb(); /* barrier for proper semantics */
- return (_atomic_fetch_or(addr, mask) & mask) != 0;
-}
-
-/**
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
-{
- unsigned long mask = BIT_MASK(nr);
- addr += BIT_WORD(nr);
- smp_mb(); /* barrier for proper semantics */
- return (_atomic_fetch_andn(addr, mask) & mask) != 0;
-}
-
-/**
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_change_bit(unsigned nr,
- volatile unsigned long *addr)
-{
- unsigned long mask = BIT_MASK(nr);
- addr += BIT_WORD(nr);
- smp_mb(); /* barrier for proper semantics */
- return (_atomic_fetch_xor(addr, mask) & mask) != 0;
-}
-
-#include <asm-generic/bitops/ext2-atomic.h>
-
-#endif /* _ASM_TILE_BITOPS_32_H */
diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h
deleted file mode 100644
index bb1a29221fcd..000000000000
--- a/arch/tile/include/asm/bitops_64.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_BITOPS_64_H
-#define _ASM_TILE_BITOPS_64_H
-
-#include <linux/compiler.h>
-#include <asm/cmpxchg.h>
-
-/* See <asm/bitops.h> for API comments. */
-
-static inline void set_bit(unsigned nr, volatile unsigned long *addr)
-{
- unsigned long mask = (1UL << (nr % BITS_PER_LONG));
- __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask);
-}
-
-static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
-{
- unsigned long mask = (1UL << (nr % BITS_PER_LONG));
- __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask);
-}
-
-static inline void change_bit(unsigned nr, volatile unsigned long *addr)
-{
- unsigned long mask = (1UL << (nr % BITS_PER_LONG));
- unsigned long guess, oldval;
- addr += nr / BITS_PER_LONG;
- oldval = *addr;
- do {
- guess = oldval;
- oldval = cmpxchg(addr, guess, guess ^ mask);
- } while (guess != oldval);
-}
-
-
-/*
- * The test_and_xxx_bit() routines require a memory fence before we
- * start the operation, and after the operation completes. We use
- * smp_mb() before, and rely on the "!= 0" comparison, plus a compiler
- * barrier(), to block until the atomic op is complete.
- */
-
-static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
-{
- int val;
- unsigned long mask = (1UL << (nr % BITS_PER_LONG));
- smp_mb(); /* barrier for proper semantics */
- val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask)
- & mask) != 0;
- barrier();
- return val;
-}
-
-
-static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
-{
- int val;
- unsigned long mask = (1UL << (nr % BITS_PER_LONG));
- smp_mb(); /* barrier for proper semantics */
- val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask)
- & mask) != 0;
- barrier();
- return val;
-}
-
-
-static inline int test_and_change_bit(unsigned nr,
- volatile unsigned long *addr)
-{
- unsigned long mask = (1UL << (nr % BITS_PER_LONG));
- unsigned long guess, oldval;
- addr += nr / BITS_PER_LONG;
- oldval = *addr;
- do {
- guess = oldval;
- oldval = cmpxchg(addr, guess, guess ^ mask);
- } while (guess != oldval);
- return (oldval & mask) != 0;
-}
-
-#include <asm-generic/bitops/ext2-atomic-setbit.h>
-
-#endif /* _ASM_TILE_BITOPS_64_H */
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
deleted file mode 100644
index 7d6aaa128e8b..000000000000
--- a/arch/tile/include/asm/cache.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_CACHE_H
-#define _ASM_TILE_CACHE_H
-
-#include <arch/chip.h>
-
-/* bytes per L1 data cache line */
-#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-/* bytes per L2 cache line */
-#define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE()
-#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
-#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
-
-/*
- * TILEPro I/O is not always coherent (networking typically uses coherent
- * I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the
- * L2 cacheline size helps ensure that kernel heap allocations are aligned.
- * TILE-Gx I/O is always coherent when used on hash-for-home pages.
- *
- * However, it's possible at runtime to request not to use hash-for-home
- * for the kernel heap, in which case the kernel will use flush-and-inval
- * to manage coherence. As a result, we use L2_CACHE_BYTES for the
- * DMA minimum alignment to avoid false sharing in the kernel heap.
- */
-#define ARCH_DMA_MINALIGN L2_CACHE_BYTES
-
-/* use the cache line size for the L2, which is where it counts */
-#define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
-#define SMP_CACHE_BYTES L2_CACHE_BYTES
-#define INTERNODE_CACHE_SHIFT L2_CACHE_SHIFT
-#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES
-
-/* Group together read-mostly things to avoid cache false sharing */
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-
-/*
- * Originally we used small TLB pages for kernel data and grouped some
- * things together as ro-after-init, enforcing the property at the end
- * of initialization by making those pages read-only and non-coherent.
- * This allowed better cache utilization since cache inclusion did not
- * need to be maintained. However, to do this requires an extra TLB
- * entry, which on balance is more of a performance hit than the
- * non-coherence is a performance gain, so we now just make "read
- * mostly" and "ro-after-init" be synonyms. We keep the attribute
- * separate in case we change our minds at a future date.
- */
-#define __ro_after_init __read_mostly
-
-#endif /* _ASM_TILE_CACHE_H */
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
deleted file mode 100644
index 92ee4c8a4f76..000000000000
--- a/arch/tile/include/asm/cacheflush.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_CACHEFLUSH_H
-#define _ASM_TILE_CACHEFLUSH_H
-
-#include <arch/chip.h>
-
-/* Keep includes the same across arches. */
-#include <linux/mm.h>
-#include <linux/cache.h>
-#include <arch/icache.h>
-
-/* Caches are physically-indexed and so don't need special treatment */
-#define flush_cache_all() do { } while (0)
-#define flush_cache_mm(mm) do { } while (0)
-#define flush_cache_dup_mm(mm) do { } while (0)
-#define flush_cache_range(vma, start, end) do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-#define flush_dcache_page(page) do { } while (0)
-#define flush_dcache_mmap_lock(mapping) do { } while (0)
-#define flush_dcache_mmap_unlock(mapping) do { } while (0)
-#define flush_cache_vmap(start, end) do { } while (0)
-#define flush_cache_vunmap(start, end) do { } while (0)
-#define flush_icache_page(vma, pg) do { } while (0)
-#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
-
-/* Flush the icache just on this cpu */
-extern void __flush_icache_range(unsigned long start, unsigned long end);
-
-/* Flush the entire icache on this cpu. */
-#define __flush_icache() __flush_icache_range(0, CHIP_L1I_CACHE_SIZE())
-
-#ifdef CONFIG_SMP
-/*
- * When the kernel writes to its own text we need to do an SMP
- * broadcast to make the L1I coherent everywhere. This includes
- * module load and single step.
- */
-extern void flush_icache_range(unsigned long start, unsigned long end);
-#else
-#define flush_icache_range __flush_icache_range
-#endif
-
-/*
- * An update to an executable user page requires icache flushing.
- * We could carefully update only tiles that are running this process,
- * and rely on the fact that we flush the icache on every context
- * switch to avoid doing extra work here. But for now, I'll be
- * conservative and just do a global icache flush.
- */
-static inline void copy_to_user_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vaddr,
- void *dst, void *src, int len)
-{
- memcpy(dst, src, len);
- if (vma->vm_flags & VM_EXEC) {
- flush_icache_range((unsigned long) dst,
- (unsigned long) dst + len);
- }
-}
-
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
- memcpy((dst), (src), (len))
-
-/* Flush a VA range; pads to L2 cacheline boundaries. */
-static inline void __flush_buffer(void *buffer, size_t size)
-{
- char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
- char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
- while (next < finish) {
- __insn_flush(next);
- next += CHIP_FLUSH_STRIDE();
- }
-}
-
-/* Flush & invalidate a VA range; pads to L2 cacheline boundaries. */
-static inline void __finv_buffer(void *buffer, size_t size)
-{
- char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
- char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
- while (next < finish) {
- __insn_finv(next);
- next += CHIP_FINV_STRIDE();
- }
-}
-
-
-/*
- * Flush a locally-homecached VA range and wait for the evicted
- * cachelines to hit memory.
- */
-static inline void flush_buffer_local(void *buffer, size_t size)
-{
- __flush_buffer(buffer, size);
- mb_incoherent();
-}
-
-/*
- * Flush and invalidate a locally-homecached VA range and wait for the
- * evicted cachelines to hit memory.
- */
-static inline void finv_buffer_local(void *buffer, size_t size)
-{
- __finv_buffer(buffer, size);
- mb_incoherent();
-}
-
-#ifdef __tilepro__
-/* Invalidate a VA range; pads to L2 cacheline boundaries. */
-static inline void __inv_buffer(void *buffer, size_t size)
-{
- char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
- char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
- while (next < finish) {
- __insn_inv(next);
- next += CHIP_INV_STRIDE();
- }
-}
-
-/* Invalidate a VA range and wait for it to be complete. */
-static inline void inv_buffer(void *buffer, size_t size)
-{
- __inv_buffer(buffer, size);
- mb();
-}
-#endif
-
-/*
- * Flush and invalidate a VA range that is homed remotely, waiting
- * until the memory controller holds the flushed values. If "hfh" is
- * true, we will do a more expensive flush involving additional loads
- * to make sure we have touched all the possible home cpus of a buffer
- * that is homed with "hash for home".
- */
-void finv_buffer_remote(void *buffer, size_t size, int hfh);
-
-/*
- * On SMP systems, when the scheduler does migration-cost autodetection,
- * it needs a way to flush as much of the CPU's caches as possible:
- *
- * TODO: fill this in!
- */
-static inline void sched_cacheflush(void)
-{
-}
-
-#endif /* _ASM_TILE_CACHEFLUSH_H */
diff --git a/arch/tile/include/asm/checksum.h b/arch/tile/include/asm/checksum.h
deleted file mode 100644
index b21a2fdec9f7..000000000000
--- a/arch/tile/include/asm/checksum.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_CHECKSUM_H
-#define _ASM_TILE_CHECKSUM_H
-
-#include <asm-generic/checksum.h>
-
-/* Allow us to provide a more optimized do_csum(). */
-__wsum do_csum(const unsigned char *buff, int len);
-#define do_csum do_csum
-
-/*
- * Return the sum of all the 16-bit subwords in a long.
- * This sums two subwords on a 32-bit machine, and four on 64 bits.
- * The implementation does two vector adds to capture any overflow.
- */
-static inline unsigned int csum_long(unsigned long x)
-{
- unsigned long ret;
-#ifdef __tilegx__
- ret = __insn_v2sadu(x, 0);
- ret = __insn_v2sadu(ret, 0);
-#else
- ret = __insn_sadh_u(x, 0);
- ret = __insn_sadh_u(ret, 0);
-#endif
- return ret;
-}
-
-#endif /* _ASM_TILE_CHECKSUM_H */
diff --git a/arch/tile/include/asm/cmpxchg.h b/arch/tile/include/asm/cmpxchg.h
deleted file mode 100644
index 25d5899497be..000000000000
--- a/arch/tile/include/asm/cmpxchg.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * cmpxchg.h -- forked from asm/atomic.h with this copyright:
- *
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _ASM_TILE_CMPXCHG_H
-#define _ASM_TILE_CMPXCHG_H
-
-#ifndef __ASSEMBLY__
-
-#include <asm/barrier.h>
-
-/* Nonexistent functions intended to cause compile errors. */
-extern void __xchg_called_with_bad_pointer(void)
- __compiletime_error("Bad argument size for xchg");
-extern void __cmpxchg_called_with_bad_pointer(void)
- __compiletime_error("Bad argument size for cmpxchg");
-
-#ifndef __tilegx__
-
-/* Note the _atomic_xxx() routines include a final mb(). */
-int _atomic_xchg(int *ptr, int n);
-int _atomic_xchg_add(int *v, int i);
-int _atomic_xchg_add_unless(int *v, int a, int u);
-int _atomic_cmpxchg(int *ptr, int o, int n);
-long long _atomic64_xchg(long long *v, long long n);
-long long _atomic64_xchg_add(long long *v, long long i);
-long long _atomic64_xchg_add_unless(long long *v, long long a, long long u);
-long long _atomic64_cmpxchg(long long *v, long long o, long long n);
-
-#define xchg(ptr, n) \
- ({ \
- if (sizeof(*(ptr)) != 4) \
- __xchg_called_with_bad_pointer(); \
- smp_mb(); \
- (typeof(*(ptr)))_atomic_xchg((int *)(ptr), (int)(n)); \
- })
-
-#define cmpxchg(ptr, o, n) \
- ({ \
- if (sizeof(*(ptr)) != 4) \
- __cmpxchg_called_with_bad_pointer(); \
- smp_mb(); \
- (typeof(*(ptr)))_atomic_cmpxchg((int *)ptr, (int)o, \
- (int)n); \
- })
-
-#define xchg64(ptr, n) \
- ({ \
- if (sizeof(*(ptr)) != 8) \
- __xchg_called_with_bad_pointer(); \
- smp_mb(); \
- (typeof(*(ptr)))_atomic64_xchg((long long *)(ptr), \
- (long long)(n)); \
- })
-
-#define cmpxchg64(ptr, o, n) \
- ({ \
- if (sizeof(*(ptr)) != 8) \
- __cmpxchg_called_with_bad_pointer(); \
- smp_mb(); \
- (typeof(*(ptr)))_atomic64_cmpxchg((long long *)ptr, \
- (long long)o, (long long)n); \
- })
-
-#else
-
-#define xchg(ptr, n) \
- ({ \
- typeof(*(ptr)) __x; \
- smp_mb(); \
- switch (sizeof(*(ptr))) { \
- case 4: \
- __x = (typeof(__x))(unsigned long) \
- __insn_exch4((ptr), \
- (u32)(unsigned long)(n)); \
- break; \
- case 8: \
- __x = (typeof(__x)) \
- __insn_exch((ptr), (unsigned long)(n)); \
- break; \
- default: \
- __xchg_called_with_bad_pointer(); \
- break; \
- } \
- smp_mb(); \
- __x; \
- })
-
-#define cmpxchg(ptr, o, n) \
- ({ \
- typeof(*(ptr)) __x; \
- __insn_mtspr(SPR_CMPEXCH_VALUE, (unsigned long)(o)); \
- smp_mb(); \
- switch (sizeof(*(ptr))) { \
- case 4: \
- __x = (typeof(__x))(unsigned long) \
- __insn_cmpexch4((ptr), \
- (u32)(unsigned long)(n)); \
- break; \
- case 8: \
- __x = (typeof(__x))__insn_cmpexch((ptr), \
- (long long)(n)); \
- break; \
- default: \
- __cmpxchg_called_with_bad_pointer(); \
- break; \
- } \
- smp_mb(); \
- __x; \
- })
-
-#define xchg64 xchg
-#define cmpxchg64 cmpxchg
-
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_TILE_CMPXCHG_H */
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
deleted file mode 100644
index 769ff6ac0bf5..000000000000
--- a/arch/tile/include/asm/compat.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_COMPAT_H
-#define _ASM_TILE_COMPAT_H
-
-/*
- * Architecture specific compatibility types
- */
-#include <linux/types.h>
-#include <linux/sched.h>
-
-#define COMPAT_USER_HZ 100
-
-/* "long" and pointer-based types are different. */
-typedef s32 compat_long_t;
-typedef u32 compat_ulong_t;
-typedef u32 compat_size_t;
-typedef s32 compat_ssize_t;
-typedef s32 compat_off_t;
-typedef s32 compat_time_t;
-typedef s32 compat_clock_t;
-typedef u32 compat_ino_t;
-typedef u32 compat_caddr_t;
-typedef u32 compat_uptr_t;
-
-/* Many types are "int" or otherwise the same. */
-typedef __kernel_pid_t compat_pid_t;
-typedef __kernel_uid_t __compat_uid_t;
-typedef __kernel_gid_t __compat_gid_t;
-typedef __kernel_uid32_t __compat_uid32_t;
-typedef __kernel_uid32_t __compat_gid32_t;
-typedef __kernel_mode_t compat_mode_t;
-typedef __kernel_dev_t compat_dev_t;
-typedef __kernel_loff_t compat_loff_t;
-typedef __kernel_ipc_pid_t compat_ipc_pid_t;
-typedef __kernel_daddr_t compat_daddr_t;
-typedef __kernel_fsid_t compat_fsid_t;
-typedef __kernel_timer_t compat_timer_t;
-typedef __kernel_key_t compat_key_t;
-typedef int compat_int_t;
-typedef s64 compat_s64;
-typedef uint compat_uint_t;
-typedef u64 compat_u64;
-
-/* We use the same register dump format in 32-bit images. */
-typedef unsigned long compat_elf_greg_t;
-#define COMPAT_ELF_NGREG (sizeof(struct pt_regs) / sizeof(compat_elf_greg_t))
-typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
-
-struct compat_timespec {
- compat_time_t tv_sec;
- s32 tv_nsec;
-};
-
-struct compat_timeval {
- compat_time_t tv_sec;
- s32 tv_usec;
-};
-
-#define compat_stat stat
-#define compat_statfs statfs
-
-struct compat_sysctl {
- unsigned int name;
- int nlen;
- unsigned int oldval;
- unsigned int oldlenp;
- unsigned int newval;
- unsigned int newlen;
- unsigned int __unused[4];
-};
-
-
-struct compat_flock {
- short l_type;
- short l_whence;
- compat_off_t l_start;
- compat_off_t l_len;
- compat_pid_t l_pid;
-};
-
-#define F_GETLK64 12 /* using 'struct flock64' */
-#define F_SETLK64 13
-#define F_SETLKW64 14
-
-struct compat_flock64 {
- short l_type;
- short l_whence;
- compat_loff_t l_start;
- compat_loff_t l_len;
- compat_pid_t l_pid;
-};
-
-#define COMPAT_RLIM_INFINITY 0xffffffff
-
-#define _COMPAT_NSIG 64
-#define _COMPAT_NSIG_BPW 32
-
-typedef u32 compat_sigset_word;
-
-#define COMPAT_OFF_T_MAX 0x7fffffff
-
-struct compat_ipc64_perm {
- compat_key_t key;
- __compat_uid32_t uid;
- __compat_gid32_t gid;
- __compat_uid32_t cuid;
- __compat_gid32_t cgid;
- unsigned short mode;
- unsigned short __pad1;
- unsigned short seq;
- unsigned short __pad2;
- compat_ulong_t unused1;
- compat_ulong_t unused2;
-};
-
-struct compat_semid64_ds {
- struct compat_ipc64_perm sem_perm;
- compat_time_t sem_otime;
- compat_ulong_t __unused1;
- compat_time_t sem_ctime;
- compat_ulong_t __unused2;
- compat_ulong_t sem_nsems;
- compat_ulong_t __unused3;
- compat_ulong_t __unused4;
-};
-
-struct compat_msqid64_ds {
- struct compat_ipc64_perm msg_perm;
- compat_time_t msg_stime;
- compat_ulong_t __unused1;
- compat_time_t msg_rtime;
- compat_ulong_t __unused2;
- compat_time_t msg_ctime;
- compat_ulong_t __unused3;
- compat_ulong_t msg_cbytes;
- compat_ulong_t msg_qnum;
- compat_ulong_t msg_qbytes;
- compat_pid_t msg_lspid;
- compat_pid_t msg_lrpid;
- compat_ulong_t __unused4;
- compat_ulong_t __unused5;
-};
-
-struct compat_shmid64_ds {
- struct compat_ipc64_perm shm_perm;
- compat_size_t shm_segsz;
- compat_time_t shm_atime;
- compat_ulong_t __unused1;
- compat_time_t shm_dtime;
- compat_ulong_t __unused2;
- compat_time_t shm_ctime;
- compat_ulong_t __unused3;
- compat_pid_t shm_cpid;
- compat_pid_t shm_lpid;
- compat_ulong_t shm_nattch;
- compat_ulong_t __unused4;
- compat_ulong_t __unused5;
-};
-
-/*
- * A pointer passed in from user mode. This should not
- * be used for syscall parameters, just declare them
- * as pointers because the syscall entry code will have
- * appropriately converted them already.
- */
-
-static inline void __user *compat_ptr(compat_uptr_t uptr)
-{
- return (void __user *)(long)(s32)uptr;
-}
-
-static inline compat_uptr_t ptr_to_compat(void __user *uptr)
-{
- return (u32)(unsigned long)uptr;
-}
-
-/* Sign-extend when storing a kernel pointer to a user's ptregs. */
-static inline unsigned long ptr_to_compat_reg(void __user *uptr)
-{
- return (long)(int)(long __force)uptr;
-}
-
-static inline void __user *arch_compat_alloc_user_space(long len)
-{
- struct pt_regs *regs = task_pt_regs(current);
- return (void __user *)regs->sp - len;
-}
-
-static inline int is_compat_task(void)
-{
- return current_thread_info()->status & TS_COMPAT;
-}
-
-extern int compat_setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs);
-
-/* Compat syscalls. */
-struct compat_siginfo;
-struct compat_sigaltstack;
-long compat_sys_rt_sigreturn(void);
-long compat_sys_truncate64(char __user *filename, u32 dummy, u32 low, u32 high);
-long compat_sys_ftruncate64(unsigned int fd, u32 dummy, u32 low, u32 high);
-long compat_sys_pread64(unsigned int fd, char __user *ubuf, size_t count,
- u32 dummy, u32 low, u32 high);
-long compat_sys_pwrite64(unsigned int fd, char __user *ubuf, size_t count,
- u32 dummy, u32 low, u32 high);
-long compat_sys_sync_file_range2(int fd, unsigned int flags,
- u32 offset_lo, u32 offset_hi,
- u32 nbytes_lo, u32 nbytes_hi);
-long compat_sys_fallocate(int fd, int mode,
- u32 offset_lo, u32 offset_hi,
- u32 len_lo, u32 len_hi);
-long compat_sys_llseek(unsigned int fd, unsigned int offset_high,
- unsigned int offset_low, loff_t __user * result,
- unsigned int origin);
-
-/* Assembly trampoline to avoid clobbering r0. */
-long _compat_sys_rt_sigreturn(void);
-
-#endif /* _ASM_TILE_COMPAT_H */
diff --git a/arch/tile/include/asm/current.h b/arch/tile/include/asm/current.h
deleted file mode 100644
index da21acf020d3..000000000000
--- a/arch/tile/include/asm/current.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_CURRENT_H
-#define _ASM_TILE_CURRENT_H
-
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct *get_current(void)
-{
- return current_thread_info()->task;
-}
-#define current get_current()
-
-/* Return a usable "task_struct" pointer even if the real one is corrupt. */
-struct task_struct *validate_current(void);
-
-#endif /* _ASM_TILE_CURRENT_H */
diff --git a/arch/tile/include/asm/delay.h b/arch/tile/include/asm/delay.h
deleted file mode 100644
index 97b0e69e704e..000000000000
--- a/arch/tile/include/asm/delay.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_DELAY_H
-#define _ASM_TILE_DELAY_H
-
-/* Undefined functions to get compile-time errors. */
-extern void __bad_udelay(void);
-extern void __bad_ndelay(void);
-
-extern void __udelay(unsigned long usecs);
-extern void __ndelay(unsigned long nsecs);
-extern void __delay(unsigned long loops);
-
-#define udelay(n) (__builtin_constant_p(n) ? \
- ((n) > 20000 ? __bad_udelay() : __ndelay((n) * 1000)) : \
- __udelay(n))
-
-#define ndelay(n) (__builtin_constant_p(n) ? \
- ((n) > 20000 ? __bad_ndelay() : __ndelay(n)) : \
- __ndelay(n))
-
-#endif /* _ASM_TILE_DELAY_H */
diff --git a/arch/tile/include/asm/device.h b/arch/tile/include/asm/device.h
deleted file mode 100644
index 1cf45422a0df..000000000000
--- a/arch/tile/include/asm/device.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- * Arch specific extensions to struct device
- */
-
-#ifndef _ASM_TILE_DEVICE_H
-#define _ASM_TILE_DEVICE_H
-
-struct dev_archdata {
- /* Offset of the DMA address from the PA. */
- dma_addr_t dma_offset;
-
- /*
- * Highest DMA address that can be generated by devices that
- * have limited DMA capability, i.e. non 64-bit capable.
- */
- dma_addr_t max_direct_dma_addr;
-};
-
-struct pdev_archdata {
-};
-
-#endif /* _ASM_TILE_DEVICE_H */
diff --git a/arch/tile/include/asm/div64.h b/arch/tile/include/asm/div64.h
deleted file mode 100644
index a0a798344d5f..000000000000
--- a/arch/tile/include/asm/div64.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_TILE_DIV64_H
-#define _ASM_TILE_DIV64_H
-
-#include <linux/types.h>
-
-#ifdef __tilegx__
-static inline u64 mul_u32_u32(u32 a, u32 b)
-{
- return __insn_mul_lu_lu(a, b);
-}
-#define mul_u32_u32 mul_u32_u32
-#endif
-
-#include <asm-generic/div64.h>
-
-#endif /* _ASM_TILE_DIV64_H */
diff --git a/arch/tile/include/asm/dma-mapping.h b/arch/tile/include/asm/dma-mapping.h
deleted file mode 100644
index d25fce101fc0..000000000000
--- a/arch/tile/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_DMA_MAPPING_H
-#define _ASM_TILE_DMA_MAPPING_H
-
-#include <linux/mm.h>
-#include <linux/scatterlist.h>
-#include <linux/cache.h>
-#include <linux/io.h>
-
-#ifdef __tilegx__
-#define ARCH_HAS_DMA_GET_REQUIRED_MASK
-#endif
-
-extern const struct dma_map_ops *tile_dma_map_ops;
-extern const struct dma_map_ops *gx_pci_dma_map_ops;
-extern const struct dma_map_ops *gx_legacy_pci_dma_map_ops;
-extern const struct dma_map_ops *gx_hybrid_pci_dma_map_ops;
-
-static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
-{
- return tile_dma_map_ops;
-}
-
-static inline dma_addr_t get_dma_offset(struct device *dev)
-{
- return dev->archdata.dma_offset;
-}
-
-static inline void set_dma_offset(struct device *dev, dma_addr_t off)
-{
- dev->archdata.dma_offset = off;
-}
-
-#define HAVE_ARCH_DMA_SET_MASK 1
-int dma_set_mask(struct device *dev, u64 mask);
-
-#endif /* _ASM_TILE_DMA_MAPPING_H */
diff --git a/arch/tile/include/asm/dma.h b/arch/tile/include/asm/dma.h
deleted file mode 100644
index 12a7ca16d164..000000000000
--- a/arch/tile/include/asm/dma.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_DMA_H
-#define _ASM_TILE_DMA_H
-
-#include <asm-generic/dma.h>
-
-/* Needed by drivers/pci/quirks.c */
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#endif
-
-#endif /* _ASM_TILE_DMA_H */
diff --git a/arch/tile/include/asm/elf.h b/arch/tile/include/asm/elf.h
deleted file mode 100644
index e9d54a06736f..000000000000
--- a/arch/tile/include/asm/elf.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_ELF_H
-#define _ASM_TILE_ELF_H
-
-/*
- * ELF register definitions.
- */
-
-#include <arch/chip.h>
-
-#include <linux/ptrace.h>
-#include <linux/elf-em.h>
-#include <asm/byteorder.h>
-#include <asm/page.h>
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct pt_regs) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-/* Provide a nominal data structure. */
-#define ELF_NFPREG 0
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-#ifdef __tilegx__
-#define ELF_CLASS ELFCLASS64
-#else
-#define ELF_CLASS ELFCLASS32
-#endif
-#ifdef __BIG_ENDIAN__
-#define ELF_DATA ELFDATA2MSB
-#else
-#define ELF_DATA ELFDATA2LSB
-#endif
-
-/*
- * There seems to be a bug in how compat_binfmt_elf.c works: it
- * #undefs ELF_ARCH, but it is then used in binfmt_elf.c for fill_note_info().
- * Hack around this by providing an enum value of ELF_ARCH.
- */
-enum { ELF_ARCH = CHIP_ELF_TYPE() };
-#define ELF_ARCH ELF_ARCH
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) \
- ((x)->e_ident[EI_CLASS] == ELF_CLASS && \
- (x)->e_ident[EI_DATA] == ELF_DATA && \
- (x)->e_machine == CHIP_ELF_TYPE())
-
-/* The module loader only handles a few relocation types. */
-#ifndef __tilegx__
-#define R_TILE_32 1
-#define R_TILE_JOFFLONG_X1 15
-#define R_TILE_IMM16_X0_LO 25
-#define R_TILE_IMM16_X1_LO 26
-#define R_TILE_IMM16_X0_HA 29
-#define R_TILE_IMM16_X1_HA 30
-#else
-#define R_TILEGX_64 1
-#define R_TILEGX_JUMPOFF_X1 21
-#define R_TILEGX_IMM16_X0_HW0 36
-#define R_TILEGX_IMM16_X1_HW0 37
-#define R_TILEGX_IMM16_X0_HW1 38
-#define R_TILEGX_IMM16_X1_HW1 39
-#define R_TILEGX_IMM16_X0_HW2_LAST 48
-#define R_TILEGX_IMM16_X1_HW2_LAST 49
-#endif
-
-/* Use standard page size for core dumps. */
-#define ELF_EXEC_PAGESIZE PAGE_SIZE
-
-/*
- * This is the location that an ET_DYN program is loaded if exec'ed. Typical
- * use of this is to invoke "./ld.so someprog" to test out a new version of
- * the loader. We need to make sure that it is out of the way of the program
- * that it will "exec", and that there is sufficient room for the brk.
- */
-#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
-
-#define ELF_CORE_COPY_REGS(_dest, _regs) \
- memcpy((char *) &_dest, (char *) _regs, \
- sizeof(struct pt_regs));
-
-/* No additional FP registers to copy. */
-#define ELF_CORE_COPY_FPREGS(t, fpu) 0
-
-/*
- * This yields a mask that user programs can use to figure out what
- * instruction set this CPU supports. This could be done in user space,
- * but it's not easy, and we've already done it here.
- */
-#define ELF_HWCAP (0)
-
-/*
- * This yields a string that ld.so will use to load implementation
- * specific libraries for optimization. This is more specific in
- * intent than poking at uname or /proc/cpuinfo.
- */
-#define ELF_PLATFORM (NULL)
-
-extern void elf_plat_init(struct pt_regs *regs, unsigned long load_addr);
-
-#define ELF_PLAT_INIT(_r, load_addr) elf_plat_init(_r, load_addr)
-
-extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
-#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
-
-/* Tilera Linux has no personalities currently, so no need to do anything. */
-#define SET_PERSONALITY(ex) do { } while (0)
-
-#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
-/* Support auto-mapping of the user interrupt vectors. */
-struct linux_binprm;
-extern int arch_setup_additional_pages(struct linux_binprm *bprm,
- int executable_stack);
-/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
-#define ARCH_DLINFO \
-do { \
- NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE); \
-} while (0)
-
-struct mm_struct;
-extern unsigned long arch_randomize_brk(struct mm_struct *mm);
-#define arch_randomize_brk arch_randomize_brk
-
-#ifdef CONFIG_COMPAT
-
-#define COMPAT_ELF_PLATFORM "tilegx-m32"
-
-/*
- * "Compat" binaries have the same machine type, but 32-bit class,
- * since they're not a separate machine type, but just a 32-bit
- * variant of the standard 64-bit architecture.
- */
-#define compat_elf_check_arch(x) \
- ((x)->e_ident[EI_CLASS] == ELFCLASS32 && \
- (x)->e_machine == CHIP_ELF_TYPE())
-
-#define compat_start_thread(regs, ip, usp) do { \
- regs->pc = ptr_to_compat_reg((void *)(ip)); \
- regs->sp = ptr_to_compat_reg((void *)(usp)); \
- single_step_execve(); \
- } while (0)
-
-/*
- * Use SET_PERSONALITY to indicate compatibility via TS_COMPAT.
- */
-#undef SET_PERSONALITY
-#define SET_PERSONALITY(ex) \
-do { \
- set_personality(PER_LINUX | (current->personality & (~PER_MASK))); \
- current_thread_info()->status &= ~TS_COMPAT; \
-} while (0)
-#define COMPAT_SET_PERSONALITY(ex) \
-do { \
- set_personality(PER_LINUX | (current->personality & (~PER_MASK))); \
- current_thread_info()->status |= TS_COMPAT; \
-} while (0)
-
-#define COMPAT_ELF_ET_DYN_BASE (0xffffffff / 3 * 2)
-
-#endif /* CONFIG_COMPAT */
-
-#define CORE_DUMP_USE_REGSET
-
-#endif /* _ASM_TILE_ELF_H */
diff --git a/arch/tile/include/asm/fixmap.h b/arch/tile/include/asm/fixmap.h
deleted file mode 100644
index ffe2637aeb31..000000000000
--- a/arch/tile/include/asm/fixmap.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 1998 Ingo Molnar
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_FIXMAP_H
-#define _ASM_TILE_FIXMAP_H
-
-#include <asm/page.h>
-
-#ifndef __ASSEMBLY__
-#include <linux/kernel.h>
-#ifdef CONFIG_HIGHMEM
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#endif
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special addresses
- * from the end of supervisor virtual memory backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * higher than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-enum fixed_addresses {
-#ifdef __tilegx__
- /*
- * TILEPro has unmapped memory above so the hole isn't needed,
- * and in any case the hole pushes us over a single 16MB pmd.
- */
- FIX_HOLE,
-#endif
-#ifdef CONFIG_HIGHMEM
- FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
- FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
-#ifdef __tilegx__ /* see homecache.c */
- FIX_HOMECACHE_BEGIN,
- FIX_HOMECACHE_END = FIX_HOMECACHE_BEGIN+(NR_CPUS)-1,
-#endif
- __end_of_permanent_fixed_addresses,
-
- /*
- * Temporary boot-time mappings, used before ioremap() is functional.
- * Not currently needed by the Tile architecture.
- */
-#define NR_FIX_BTMAPS 0
-#if NR_FIX_BTMAPS
- FIX_BTMAP_END = __end_of_permanent_fixed_addresses,
- FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS - 1,
- __end_of_fixed_addresses
-#else
- __end_of_fixed_addresses = __end_of_permanent_fixed_addresses
-#endif
-};
-
-#define __FIXADDR_SIZE (__end_of_permanent_fixed_addresses << PAGE_SHIFT)
-#define __FIXADDR_BOOT_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START (FIXADDR_TOP + PAGE_SIZE - __FIXADDR_SIZE)
-#define FIXADDR_BOOT_START (FIXADDR_TOP + PAGE_SIZE - __FIXADDR_BOOT_SIZE)
-
-#include <asm-generic/fixmap.h>
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_TILE_FIXMAP_H */
diff --git a/arch/tile/include/asm/ftrace.h b/arch/tile/include/asm/ftrace.h
deleted file mode 100644
index 738d239b792f..000000000000
--- a/arch/tile/include/asm/ftrace.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_FTRACE_H
-#define _ASM_TILE_FTRACE_H
-
-#ifdef CONFIG_FUNCTION_TRACER
-
-#define MCOUNT_ADDR ((unsigned long)(__mcount))
-#define MCOUNT_INSN_SIZE 8 /* sizeof mcount call */
-
-#ifndef __ASSEMBLY__
-extern void __mcount(void);
-
-#define ARCH_SUPPORTS_FTRACE_OPS 1
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-static inline unsigned long ftrace_call_adjust(unsigned long addr)
-{
- return addr;
-}
-
-struct dyn_arch_ftrace {
-};
-#endif /* CONFIG_DYNAMIC_FTRACE */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* CONFIG_FUNCTION_TRACER */
-
-#endif /* _ASM_TILE_FTRACE_H */
diff --git a/arch/tile/include/asm/futex.h b/arch/tile/include/asm/futex.h
deleted file mode 100644
index 83c1e639b411..000000000000
--- a/arch/tile/include/asm/futex.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * These routines make two important assumptions:
- *
- * 1. atomic_t is really an int and can be freely cast back and forth
- * (validated in __init_atomic_per_cpu).
- *
- * 2. userspace uses sys_cmpxchg() for all atomic operations, thus using
- * the same locking convention that all the kernel atomic routines use.
- */
-
-#ifndef _ASM_TILE_FUTEX_H
-#define _ASM_TILE_FUTEX_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-#include <linux/errno.h>
-#include <asm/atomic.h>
-
-/*
- * Support macros for futex operations. Do not use these macros directly.
- * They assume "ret", "val", "oparg", and "uaddr" in the lexical context.
- * __futex_cmpxchg() additionally assumes "oldval".
- */
-
-#ifdef __tilegx__
-
-#define __futex_asm(OP) \
- asm("1: {" #OP " %1, %3, %4; movei %0, 0 }\n" \
- ".pushsection .fixup,\"ax\"\n" \
- "0: { movei %0, %5; j 9f }\n" \
- ".section __ex_table,\"a\"\n" \
- ".align 8\n" \
- ".quad 1b, 0b\n" \
- ".popsection\n" \
- "9:" \
- : "=r" (ret), "=r" (val), "+m" (*(uaddr)) \
- : "r" (uaddr), "r" (oparg), "i" (-EFAULT))
-
-#define __futex_set() __futex_asm(exch4)
-#define __futex_add() __futex_asm(fetchadd4)
-#define __futex_or() __futex_asm(fetchor4)
-#define __futex_andn() ({ oparg = ~oparg; __futex_asm(fetchand4); })
-#define __futex_cmpxchg() \
- ({ __insn_mtspr(SPR_CMPEXCH_VALUE, oldval); __futex_asm(cmpexch4); })
-
-#define __futex_xor() \
- ({ \
- u32 oldval, n = oparg; \
- if ((ret = __get_user(oldval, uaddr)) == 0) { \
- do { \
- oparg = oldval ^ n; \
- __futex_cmpxchg(); \
- } while (ret == 0 && oldval != val); \
- } \
- })
-
-/* No need to prefetch, since the atomic ops go to the home cache anyway. */
-#define __futex_prolog()
-
-#else
-
-#define __futex_call(FN) \
- { \
- struct __get_user gu = FN((u32 __force *)uaddr, lock, oparg); \
- val = gu.val; \
- ret = gu.err; \
- }
-
-#define __futex_set() __futex_call(__atomic32_xchg)
-#define __futex_add() __futex_call(__atomic32_xchg_add)
-#define __futex_or() __futex_call(__atomic32_fetch_or)
-#define __futex_andn() __futex_call(__atomic32_fetch_andn)
-#define __futex_xor() __futex_call(__atomic32_fetch_xor)
-
-#define __futex_cmpxchg() \
- { \
- struct __get_user gu = __atomic32_cmpxchg((u32 __force *)uaddr, \
- lock, oldval, oparg); \
- val = gu.val; \
- ret = gu.err; \
- }
-
-/*
- * Find the lock pointer for the atomic calls to use, and issue a
- * prefetch to the user address to bring it into cache. Similar to
- * __atomic_setup(), but we can't do a read into the L1 since it might
- * fault; instead we do a prefetch into the L2.
- */
-#define __futex_prolog() \
- int *lock; \
- __insn_prefetch(uaddr); \
- lock = __atomic_hashed_lock((int __force *)uaddr)
-#endif
-
-static inline int arch_futex_atomic_op_inuser(int op, u32 oparg, int *oval,
- u32 __user *uaddr)
-{
- int uninitialized_var(val), ret;
-
- __futex_prolog();
-
- /* The 32-bit futex code makes this assumption, so validate it here. */
- BUILD_BUG_ON(sizeof(atomic_t) != sizeof(int));
-
- pagefault_disable();
- switch (op) {
- case FUTEX_OP_SET:
- __futex_set();
- break;
- case FUTEX_OP_ADD:
- __futex_add();
- break;
- case FUTEX_OP_OR:
- __futex_or();
- break;
- case FUTEX_OP_ANDN:
- __futex_andn();
- break;
- case FUTEX_OP_XOR:
- __futex_xor();
- break;
- default:
- ret = -ENOSYS;
- break;
- }
- pagefault_enable();
-
- if (!ret)
- *oval = val;
-
- return ret;
-}
-
-static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
- u32 oldval, u32 oparg)
-{
- int ret, val;
-
- __futex_prolog();
-
- if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
- return -EFAULT;
-
- __futex_cmpxchg();
-
- *uval = val;
- return ret;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_TILE_FUTEX_H */
diff --git a/arch/tile/include/asm/hardirq.h b/arch/tile/include/asm/hardirq.h
deleted file mode 100644
index 54110af23985..000000000000
--- a/arch/tile/include/asm/hardirq.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_HARDIRQ_H
-#define _ASM_TILE_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/cache.h>
-
-#include <asm/irq.h>
-
-typedef struct {
- unsigned int __softirq_pending;
- long idle_timestamp;
-
- /* Hard interrupt statistics. */
- unsigned int irq_timer_count;
- unsigned int irq_syscall_count;
- unsigned int irq_resched_count;
- unsigned int irq_hv_flush_count;
- unsigned int irq_call_count;
- unsigned int irq_hv_msg_count;
- unsigned int irq_dev_intr_count;
-
-} ____cacheline_aligned irq_cpustat_t;
-
-DECLARE_PER_CPU(irq_cpustat_t, irq_stat);
-
-#define __ARCH_IRQ_STAT
-#define __IRQ_STAT(cpu, member) (per_cpu(irq_stat, cpu).member)
-
-#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
-
-#endif /* _ASM_TILE_HARDIRQ_H */
diff --git a/arch/tile/include/asm/hardwall.h b/arch/tile/include/asm/hardwall.h
deleted file mode 100644
index 44d2765bde2b..000000000000
--- a/arch/tile/include/asm/hardwall.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Provide methods for access control of per-cpu resources like
- * UDN, IDN, or IPI.
- */
-#ifndef _ASM_TILE_HARDWALL_H
-#define _ASM_TILE_HARDWALL_H
-
-#include <uapi/asm/hardwall.h>
-
-/* /proc hooks for hardwall. */
-struct proc_dir_entry;
-#ifdef CONFIG_HARDWALL
-void proc_tile_hardwall_init(struct proc_dir_entry *root);
-int proc_pid_hardwall(struct seq_file *m, struct pid_namespace *ns, struct pid *pid, struct task_struct *task);
-#else
-static inline void proc_tile_hardwall_init(struct proc_dir_entry *root) {}
-#endif
-#endif /* _ASM_TILE_HARDWALL_H */
diff --git a/arch/tile/include/asm/highmem.h b/arch/tile/include/asm/highmem.h
deleted file mode 100644
index 979579b38e57..000000000000
--- a/arch/tile/include/asm/highmem.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- * Gerhard.Wichert@pdb.siemens.de
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- */
-
-#ifndef _ASM_TILE_HIGHMEM_H
-#define _ASM_TILE_HIGHMEM_H
-
-#include <linux/interrupt.h>
-#include <linux/threads.h>
-#include <asm/tlbflush.h>
-#include <asm/homecache.h>
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-extern pte_t *pkmap_page_table;
-
-/*
- * Ordering is:
- *
- * FIXADDR_TOP
- * fixed_addresses
- * FIXADDR_START
- * temp fixed addresses
- * FIXADDR_BOOT_START
- * Persistent kmap area
- * PKMAP_BASE
- * VMALLOC_END
- * Vmalloc area
- * VMALLOC_START
- * high_memory
- */
-#define LAST_PKMAP_MASK (LAST_PKMAP-1)
-#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-void *kmap_high(struct page *page);
-void kunmap_high(struct page *page);
-void *kmap(struct page *page);
-void kunmap(struct page *page);
-void *kmap_fix_kpte(struct page *page, int finished);
-
-/* This macro is used only in map_new_virtual() to map "page". */
-#define kmap_prot page_to_kpgprot(page)
-
-void *kmap_atomic(struct page *page);
-void __kunmap_atomic(void *kvaddr);
-void *kmap_atomic_pfn(unsigned long pfn);
-void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot);
-void *kmap_atomic_prot(struct page *page, pgprot_t prot);
-void kmap_atomic_fix_kpte(struct page *page, int finished);
-
-#define flush_cache_kmaps() do { } while (0)
-
-#endif /* _ASM_TILE_HIGHMEM_H */
diff --git a/arch/tile/include/asm/homecache.h b/arch/tile/include/asm/homecache.h
deleted file mode 100644
index 7ddd1b8d6910..000000000000
--- a/arch/tile/include/asm/homecache.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Handle issues around the Tile "home cache" model of coherence.
- */
-
-#ifndef _ASM_TILE_HOMECACHE_H
-#define _ASM_TILE_HOMECACHE_H
-
-#include <asm/page.h>
-#include <linux/cpumask.h>
-
-struct page;
-struct task_struct;
-struct vm_area_struct;
-struct zone;
-
-/*
- * Coherence point for the page is its memory controller.
- * It is not present in any cache (L1 or L2).
- */
-#define PAGE_HOME_UNCACHED -1
-
-/*
- * Is this page immutable (unwritable) and thus able to be cached more
- * widely than would otherwise be possible? This means we have "nc" set.
- */
-#define PAGE_HOME_IMMUTABLE -2
-
-/*
- * Each cpu considers its own cache to be the home for the page,
- * which makes it incoherent.
- */
-#define PAGE_HOME_INCOHERENT -3
-
-/* Home for the page is distributed via hash-for-home. */
-#define PAGE_HOME_HASH -4
-
-/* Support wrapper to use instead of explicit hv_flush_remote(). */
-extern void flush_remote(unsigned long cache_pfn, unsigned long cache_length,
- const struct cpumask *cache_cpumask,
- HV_VirtAddr tlb_va, unsigned long tlb_length,
- unsigned long tlb_pgsize,
- const struct cpumask *tlb_cpumask,
- HV_Remote_ASID *asids, int asidcount);
-
-/* Set homing-related bits in a PTE (can also pass a pgprot_t). */
-extern pte_t pte_set_home(pte_t pte, int home);
-
-/* Do a cache eviction on the specified cpus. */
-extern void homecache_evict(const struct cpumask *mask);
-
-/*
- * Change a kernel page's homecache. It must not be mapped in user space.
- * If !CONFIG_HOMECACHE, only usable on LOWMEM, and can only be called when
- * no other cpu can reference the page, and causes a full-chip cache/TLB flush.
- */
-extern void homecache_change_page_home(struct page *, int order, int home);
-
-/*
- * Flush a page out of whatever cache(s) it is in.
- * This is more than just finv, since it properly handles waiting
- * for the data to reach memory, but it can be quite
- * heavyweight, particularly on incoherent or immutable memory.
- */
-extern void homecache_finv_page(struct page *);
-
-/*
- * Flush a page out of the specified home cache.
- * Note that the specified home need not be the actual home of the page,
- * as for example might be the case when coordinating with I/O devices.
- */
-extern void homecache_finv_map_page(struct page *, int home);
-
-/*
- * Allocate a page with the given GFP flags, home, and optionally
- * node. These routines are actually just wrappers around the normal
- * alloc_pages() / alloc_pages_node() functions, which set and clear
- * a per-cpu variable to communicate with homecache_new_kernel_page().
- * If !CONFIG_HOMECACHE, uses homecache_change_page_home().
- */
-extern struct page *homecache_alloc_pages(gfp_t gfp_mask,
- unsigned int order, int home);
-extern struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
- unsigned int order, int home);
-#define homecache_alloc_page(gfp_mask, home) \
- homecache_alloc_pages(gfp_mask, 0, home)
-
-/*
- * These routines are just pass-throughs to free_pages() when
- * we support full homecaching. If !CONFIG_HOMECACHE, then these
- * routines use homecache_change_page_home() to reset the home
- * back to the default before returning the page to the allocator.
- */
-void __homecache_free_pages(struct page *, unsigned int order);
-void homecache_free_pages(unsigned long addr, unsigned int order);
-#define __homecache_free_page(page) __homecache_free_pages((page), 0)
-#define homecache_free_page(page) homecache_free_pages((page), 0)
-
-
-/*
- * Report the page home for LOWMEM pages by examining their kernel PTE,
- * or for highmem pages as the default home.
- */
-extern int page_home(struct page *);
-
-#define homecache_migrate_kthread() do {} while (0)
-
-#define homecache_kpte_lock() 0
-#define homecache_kpte_unlock(flags) do {} while (0)
-
-
-#endif /* _ASM_TILE_HOMECACHE_H */
diff --git a/arch/tile/include/asm/hugetlb.h b/arch/tile/include/asm/hugetlb.h
deleted file mode 100644
index 2fac5be4de26..000000000000
--- a/arch/tile/include/asm/hugetlb.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_HUGETLB_H
-#define _ASM_TILE_HUGETLB_H
-
-#include <asm/page.h>
-#include <asm-generic/hugetlb.h>
-
-
-static inline int is_hugepage_only_range(struct mm_struct *mm,
- unsigned long addr,
- unsigned long len) {
- return 0;
-}
-
-/*
- * If the arch doesn't supply something else, assume that hugepage
- * size aligned regions are ok without further preparation.
- */
-static inline int prepare_hugepage_range(struct file *file,
- unsigned long addr, unsigned long len)
-{
- struct hstate *h = hstate_file(file);
- if (len & ~huge_page_mask(h))
- return -EINVAL;
- if (addr & ~huge_page_mask(h))
- return -EINVAL;
- return 0;
-}
-
-static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
- unsigned long addr, unsigned long end,
- unsigned long floor,
- unsigned long ceiling)
-{
- free_pgd_range(tlb, addr, end, floor, ceiling);
-}
-
-static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, pte_t pte)
-{
- set_pte(ptep, pte);
-}
-
-static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- return ptep_get_and_clear(mm, addr, ptep);
-}
-
-static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep)
-{
- ptep_clear_flush(vma, addr, ptep);
-}
-
-static inline int huge_pte_none(pte_t pte)
-{
- return pte_none(pte);
-}
-
-static inline pte_t huge_pte_wrprotect(pte_t pte)
-{
- return pte_wrprotect(pte);
-}
-
-static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- ptep_set_wrprotect(mm, addr, ptep);
-}
-
-static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep,
- pte_t pte, int dirty)
-{
- return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
-}
-
-static inline pte_t huge_ptep_get(pte_t *ptep)
-{
- return *ptep;
-}
-
-static inline void arch_clear_hugepage_flags(struct page *page)
-{
-}
-
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
-static inline pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma,
- struct page *page, int writable)
-{
- size_t pagesize = huge_page_size(hstate_vma(vma));
- if (pagesize != PUD_SIZE && pagesize != PMD_SIZE)
- entry = pte_mksuper(entry);
- return entry;
-}
-#define arch_make_huge_pte arch_make_huge_pte
-
-/* Sizes to scale up page size for PTEs with HV_PTE_SUPER bit. */
-enum {
- HUGE_SHIFT_PGDIR = 0,
- HUGE_SHIFT_PMD = 1,
- HUGE_SHIFT_PAGE = 2,
- HUGE_SHIFT_ENTRIES
-};
-extern int huge_shift[HUGE_SHIFT_ENTRIES];
-#endif
-
-#endif /* _ASM_TILE_HUGETLB_H */
diff --git a/arch/tile/include/asm/hv_driver.h b/arch/tile/include/asm/hv_driver.h
deleted file mode 100644
index ad614de899b3..000000000000
--- a/arch/tile/include/asm/hv_driver.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * This header defines a wrapper interface for managing hypervisor
- * device calls that will result in an interrupt at some later time.
- * In particular, this provides wrappers for hv_preada() and
- * hv_pwritea().
- */
-
-#ifndef _ASM_TILE_HV_DRIVER_H
-#define _ASM_TILE_HV_DRIVER_H
-
-#include <hv/hypervisor.h>
-
-struct hv_driver_cb;
-
-/* A callback to be invoked when an operation completes. */
-typedef void hv_driver_callback_t(struct hv_driver_cb *cb, __hv32 result);
-
-/*
- * A structure to hold information about an outstanding call.
- * The driver must allocate a separate structure for each call.
- */
-struct hv_driver_cb {
- hv_driver_callback_t *callback; /* Function to call on interrupt. */
- void *dev; /* Driver-specific state variable. */
-};
-
-/* Wrapper for invoking hv_dev_preada(). */
-static inline int
-tile_hv_dev_preada(int devhdl, __hv32 flags, __hv32 sgl_len,
- HV_SGL sgl[/* sgl_len */], __hv64 offset,
- struct hv_driver_cb *callback)
-{
- return hv_dev_preada(devhdl, flags, sgl_len, sgl,
- offset, (HV_IntArg)callback);
-}
-
-/* Wrapper for invoking hv_dev_pwritea(). */
-static inline int
-tile_hv_dev_pwritea(int devhdl, __hv32 flags, __hv32 sgl_len,
- HV_SGL sgl[/* sgl_len */], __hv64 offset,
- struct hv_driver_cb *callback)
-{
- return hv_dev_pwritea(devhdl, flags, sgl_len, sgl,
- offset, (HV_IntArg)callback);
-}
-
-
-#endif /* _ASM_TILE_HV_DRIVER_H */
diff --git a/arch/tile/include/asm/ide.h b/arch/tile/include/asm/ide.h
deleted file mode 100644
index 3c6f2ed894ce..000000000000
--- a/arch/tile/include/asm/ide.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_IDE_H
-#define _ASM_TILE_IDE_H
-
-/* For IDE on PCI */
-#define MAX_HWIFS 10
-
-#define ide_default_io_ctl(base) (0)
-
-#include <asm-generic/ide_iops.h>
-
-#endif /* _ASM_TILE_IDE_H */
diff --git a/arch/tile/include/asm/insn.h b/arch/tile/include/asm/insn.h
deleted file mode 100644
index f78ba5c16722..000000000000
--- a/arch/tile/include/asm/insn.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2015 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-#ifndef __ASM_TILE_INSN_H
-#define __ASM_TILE_INSN_H
-
-#include <arch/opcode.h>
-
-static inline tilegx_bundle_bits NOP(void)
-{
- return create_UnaryOpcodeExtension_X0(FNOP_UNARY_OPCODE_X0) |
- create_RRROpcodeExtension_X0(UNARY_RRR_0_OPCODE_X0) |
- create_Opcode_X0(RRR_0_OPCODE_X0) |
- create_UnaryOpcodeExtension_X1(NOP_UNARY_OPCODE_X1) |
- create_RRROpcodeExtension_X1(UNARY_RRR_0_OPCODE_X1) |
- create_Opcode_X1(RRR_0_OPCODE_X1);
-}
-
-static inline tilegx_bundle_bits tilegx_gen_branch(unsigned long pc,
- unsigned long addr,
- bool link)
-{
- tilegx_bundle_bits opcode_x0, opcode_x1;
- long pcrel_by_instr = (addr - pc) >> TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES;
-
- if (link) {
- /* opcode: jal addr */
- opcode_x1 =
- create_Opcode_X1(JUMP_OPCODE_X1) |
- create_JumpOpcodeExtension_X1(JAL_JUMP_OPCODE_X1) |
- create_JumpOff_X1(pcrel_by_instr);
- } else {
- /* opcode: j addr */
- opcode_x1 =
- create_Opcode_X1(JUMP_OPCODE_X1) |
- create_JumpOpcodeExtension_X1(J_JUMP_OPCODE_X1) |
- create_JumpOff_X1(pcrel_by_instr);
- }
-
- /* opcode: fnop */
- opcode_x0 =
- create_UnaryOpcodeExtension_X0(FNOP_UNARY_OPCODE_X0) |
- create_RRROpcodeExtension_X0(UNARY_RRR_0_OPCODE_X0) |
- create_Opcode_X0(RRR_0_OPCODE_X0);
-
- return opcode_x1 | opcode_x0;
-}
-
-#endif /* __ASM_TILE_INSN_H */
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
deleted file mode 100644
index 30f4a210d148..000000000000
--- a/arch/tile/include/asm/io.h
+++ /dev/null
@@ -1,509 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_IO_H
-#define _ASM_TILE_IO_H
-
-#include <linux/kernel.h>
-#include <linux/bug.h>
-#include <asm/page.h>
-
-/* Maximum PCI I/O space address supported. */
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access.
- */
-#define xlate_dev_mem_ptr(p) __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer.
- */
-#define xlate_dev_kmem_ptr(p) p
-
-/*
- * Change "struct page" to physical address.
- */
-#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
-
-/*
- * Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
- * long before casting it to a pointer to avoid compiler warnings.
- */
-#if CHIP_HAS_MMIO()
-extern void __iomem *ioremap(resource_size_t offset, unsigned long size);
-extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
- pgprot_t pgprot);
-extern void iounmap(volatile void __iomem *addr);
-#else
-#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
-#define iounmap(addr) ((void)0)
-#endif
-
-#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
-#define ioremap_wc(physaddr, size) ioremap(physaddr, size)
-#define ioremap_wt(physaddr, size) ioremap(physaddr, size)
-#define ioremap_uc(physaddr, size) ioremap(physaddr, size)
-#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)
-
-#define mmiowb()
-
-/* Conversion between virtual and physical mappings. */
-#define mm_ptov(addr) ((void *)phys_to_virt(addr))
-#define mm_vtop(addr) ((unsigned long)virt_to_phys(addr))
-
-#if CHIP_HAS_MMIO()
-
-/*
- * We use inline assembly to guarantee that the compiler does not
- * split an access into multiple byte-sized accesses as it might
- * sometimes do if a register data structure is marked "packed".
- * Obviously on tile we can't tolerate such an access being
- * actually unaligned, but we want to avoid the case where the
- * compiler conservatively would generate multiple accesses even
- * for an aligned read or write.
- */
-
-static inline u8 __raw_readb(const volatile void __iomem *addr)
-{
- return *(const volatile u8 __force *)addr;
-}
-
-static inline u16 __raw_readw(const volatile void __iomem *addr)
-{
- u16 ret;
- asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
- barrier();
- return le16_to_cpu(ret);
-}
-
-static inline u32 __raw_readl(const volatile void __iomem *addr)
-{
- u32 ret;
- /* Sign-extend to conform to u32 ABI sign-extension convention. */
- asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
- barrier();
- return le32_to_cpu(ret);
-}
-
-static inline u64 __raw_readq(const volatile void __iomem *addr)
-{
- u64 ret;
- asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
- barrier();
- return le64_to_cpu(ret);
-}
-
-static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
-{
- *(volatile u8 __force *)addr = val;
-}
-
-static inline void __raw_writew(u16 val, volatile void __iomem *addr)
-{
- asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
-}
-
-static inline void __raw_writel(u32 val, volatile void __iomem *addr)
-{
- asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
-}
-
-static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
-{
- asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
-}
-
-/*
- * The on-chip I/O hardware on tilegx is configured with VA=PA for the
- * kernel's PA range. The low-level APIs and field names use "va" and
- * "void *" nomenclature, to be consistent with the general notion
- * that the addresses in question are virtualizable, but in the kernel
- * context we are actually manipulating PA values. (In other contexts,
- * e.g. access from user space, we do in fact use real virtual addresses
- * in the va fields.) To allow readers of the code to understand what's
- * happening, we direct their attention to this comment by using the
- * following two functions that just duplicate __va() and __pa().
- */
-typedef unsigned long tile_io_addr_t;
-static inline tile_io_addr_t va_to_tile_io_addr(void *va)
-{
- BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
- return __pa(va);
-}
-static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
-{
- return __va(tile_io_addr);
-}
-
-#else /* CHIP_HAS_MMIO() */
-
-#ifdef CONFIG_PCI
-
-extern u8 _tile_readb(unsigned long addr);
-extern u16 _tile_readw(unsigned long addr);
-extern u32 _tile_readl(unsigned long addr);
-extern u64 _tile_readq(unsigned long addr);
-extern void _tile_writeb(u8 val, unsigned long addr);
-extern void _tile_writew(u16 val, unsigned long addr);
-extern void _tile_writel(u32 val, unsigned long addr);
-extern void _tile_writeq(u64 val, unsigned long addr);
-
-#define __raw_readb(addr) _tile_readb((unsigned long)(addr))
-#define __raw_readw(addr) _tile_readw((unsigned long)(addr))
-#define __raw_readl(addr) _tile_readl((unsigned long)(addr))
-#define __raw_readq(addr) _tile_readq((unsigned long)(addr))
-#define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)(addr))
-#define __raw_writew(val, addr) _tile_writew(val, (unsigned long)(addr))
-#define __raw_writel(val, addr) _tile_writel(val, (unsigned long)(addr))
-#define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)(addr))
-
-#else /* CONFIG_PCI */
-
-/*
- * The tilepro architecture does not support IOMEM unless PCI is enabled.
- * Unfortunately we can't yet simply not declare these methods,
- * since some generic code that compiles into the kernel, but
- * we never run, uses them unconditionally.
- */
-
-static inline int iomem_panic(void)
-{
- panic("readb/writeb and friends do not exist on tile without PCI");
- return 0;
-}
-
-static inline u8 readb(unsigned long addr)
-{
- return iomem_panic();
-}
-
-static inline u16 _readw(unsigned long addr)
-{
- return iomem_panic();
-}
-
-static inline u32 readl(unsigned long addr)
-{
- return iomem_panic();
-}
-
-static inline u64 readq(unsigned long addr)
-{
- return iomem_panic();
-}
-
-static inline void writeb(u8 val, unsigned long addr)
-{
- iomem_panic();
-}
-
-static inline void writew(u16 val, unsigned long addr)
-{
- iomem_panic();
-}
-
-static inline void writel(u32 val, unsigned long addr)
-{
- iomem_panic();
-}
-
-static inline void writeq(u64 val, unsigned long addr)
-{
- iomem_panic();
-}
-
-#endif /* CONFIG_PCI */
-
-#endif /* CHIP_HAS_MMIO() */
-
-#define readb __raw_readb
-#define readw __raw_readw
-#define readl __raw_readl
-#define readq __raw_readq
-#define writeb __raw_writeb
-#define writew __raw_writew
-#define writel __raw_writel
-#define writeq __raw_writeq
-
-#define readb_relaxed readb
-#define readw_relaxed readw
-#define readl_relaxed readl
-#define readq_relaxed readq
-#define writeb_relaxed writeb
-#define writew_relaxed writew
-#define writel_relaxed writel
-#define writeq_relaxed writeq
-
-#define ioread8 readb
-#define ioread16 readw
-#define ioread32 readl
-#define ioread64 readq
-#define iowrite8 writeb
-#define iowrite16 writew
-#define iowrite32 writel
-#define iowrite64 writeq
-
-#if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
-
-static inline void memset_io(volatile void *dst, int val, size_t len)
-{
- size_t x;
- BUG_ON((unsigned long)dst & 0x3);
- val = (val & 0xff) * 0x01010101;
- for (x = 0; x < len; x += 4)
- writel(val, dst + x);
-}
-
-static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
- size_t len)
-{
- size_t x;
- BUG_ON((unsigned long)src & 0x3);
- for (x = 0; x < len; x += 4)
- *(u32 *)(dst + x) = readl(src + x);
-}
-
-static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
- size_t len)
-{
- size_t x;
- BUG_ON((unsigned long)dst & 0x3);
- for (x = 0; x < len; x += 4)
- writel(*(u32 *)(src + x), dst + x);
-}
-
-#endif
-
-#if CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO)
-
-static inline u8 inb(unsigned long addr)
-{
- return readb((volatile void __iomem *) addr);
-}
-
-static inline u16 inw(unsigned long addr)
-{
- return readw((volatile void __iomem *) addr);
-}
-
-static inline u32 inl(unsigned long addr)
-{
- return readl((volatile void __iomem *) addr);
-}
-
-static inline void outb(u8 b, unsigned long addr)
-{
- writeb(b, (volatile void __iomem *) addr);
-}
-
-static inline void outw(u16 b, unsigned long addr)
-{
- writew(b, (volatile void __iomem *) addr);
-}
-
-static inline void outl(u32 b, unsigned long addr)
-{
- writel(b, (volatile void __iomem *) addr);
-}
-
-static inline void insb(unsigned long addr, void *buffer, int count)
-{
- if (count) {
- u8 *buf = buffer;
- do {
- u8 x = inb(addr);
- *buf++ = x;
- } while (--count);
- }
-}
-
-static inline void insw(unsigned long addr, void *buffer, int count)
-{
- if (count) {
- u16 *buf = buffer;
- do {
- u16 x = inw(addr);
- *buf++ = x;
- } while (--count);
- }
-}
-
-static inline void insl(unsigned long addr, void *buffer, int count)
-{
- if (count) {
- u32 *buf = buffer;
- do {
- u32 x = inl(addr);
- *buf++ = x;
- } while (--count);
- }
-}
-
-static inline void outsb(unsigned long addr, const void *buffer, int count)
-{
- if (count) {
- const u8 *buf = buffer;
- do {
- outb(*buf++, addr);
- } while (--count);
- }
-}
-
-static inline void outsw(unsigned long addr, const void *buffer, int count)
-{
- if (count) {
- const u16 *buf = buffer;
- do {
- outw(*buf++, addr);
- } while (--count);
- }
-}
-
-static inline void outsl(unsigned long addr, const void *buffer, int count)
-{
- if (count) {
- const u32 *buf = buffer;
- do {
- outl(*buf++, addr);
- } while (--count);
- }
-}
-
-extern void __iomem *ioport_map(unsigned long port, unsigned int len);
-extern void ioport_unmap(void __iomem *addr);
-
-#else
-
-/*
- * The TilePro architecture does not support IOPORT, even with PCI.
- * Unfortunately we can't yet simply not declare these methods,
- * since some generic code that compiles into the kernel, but
- * we never run, uses them unconditionally.
- */
-
-static inline long ioport_panic(void)
-{
-#ifdef __tilegx__
- panic("PCI IO space support is disabled. Configure the kernel with CONFIG_TILE_PCI_IO to enable it");
-#else
- panic("inb/outb and friends do not exist on tile");
-#endif
- return 0;
-}
-
-static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
-{
- pr_info("ioport_map: mapping IO resources is unsupported on tile\n");
- return NULL;
-}
-
-static inline void ioport_unmap(void __iomem *addr)
-{
- ioport_panic();
-}
-
-static inline u8 inb(unsigned long addr)
-{
- return ioport_panic();
-}
-
-static inline u16 inw(unsigned long addr)
-{
- return ioport_panic();
-}
-
-static inline u32 inl(unsigned long addr)
-{
- return ioport_panic();
-}
-
-static inline void outb(u8 b, unsigned long addr)
-{
- ioport_panic();
-}
-
-static inline void outw(u16 b, unsigned long addr)
-{
- ioport_panic();
-}
-
-static inline void outl(u32 b, unsigned long addr)
-{
- ioport_panic();
-}
-
-static inline void insb(unsigned long addr, void *buffer, int count)
-{
- ioport_panic();
-}
-
-static inline void insw(unsigned long addr, void *buffer, int count)
-{
- ioport_panic();
-}
-
-static inline void insl(unsigned long addr, void *buffer, int count)
-{
- ioport_panic();
-}
-
-static inline void outsb(unsigned long addr, const void *buffer, int count)
-{
- ioport_panic();
-}
-
-static inline void outsw(unsigned long addr, const void *buffer, int count)
-{
- ioport_panic();
-}
-
-static inline void outsl(unsigned long addr, const void *buffer, int count)
-{
- ioport_panic();
-}
-
-#endif /* CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO) */
-
-#define inb_p(addr) inb(addr)
-#define inw_p(addr) inw(addr)
-#define inl_p(addr) inl(addr)
-#define outb_p(x, addr) outb((x), (addr))
-#define outw_p(x, addr) outw((x), (addr))
-#define outl_p(x, addr) outl((x), (addr))
-
-#define ioread16be(addr) be16_to_cpu(ioread16(addr))
-#define ioread32be(addr) be32_to_cpu(ioread32(addr))
-#define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
-#define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr))
-
-#define ioread8_rep(p, dst, count) \
- insb((unsigned long) (p), (dst), (count))
-#define ioread16_rep(p, dst, count) \
- insw((unsigned long) (p), (dst), (count))
-#define ioread32_rep(p, dst, count) \
- insl((unsigned long) (p), (dst), (count))
-
-#define iowrite8_rep(p, src, count) \
- outsb((unsigned long) (p), (src), (count))
-#define iowrite16_rep(p, src, count) \
- outsw((unsigned long) (p), (src), (count))
-#define iowrite32_rep(p, src, count) \
- outsl((unsigned long) (p), (src), (count))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-#endif /* _ASM_TILE_IO_H */
diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h
deleted file mode 100644
index 1fa1f2544ff9..000000000000
--- a/arch/tile/include/asm/irq.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_IRQ_H
-#define _ASM_TILE_IRQ_H
-
-#include <linux/hardirq.h>
-
-/* The hypervisor interface provides 32 IRQs. */
-#define NR_IRQS 32
-
-/* IRQ numbers used for linux IPIs. */
-#define IRQ_RESCHEDULE 0
-/* Interrupts for dynamic allocation start at 1. Let the core allocate irq0 */
-#define NR_IRQS_LEGACY 1
-
-#define irq_canonicalize(irq) (irq)
-
-void ack_bad_irq(unsigned int irq);
-
-/*
- * Different ways of handling interrupts. Tile interrupts are always
- * per-cpu; there is no global interrupt controller to implement
- * enable/disable. Most onboard devices can send their interrupts to
- * many tiles at the same time, and Tile-specific drivers know how to
- * deal with this.
- *
- * However, generic devices (usually PCIE based, sometimes GPIO)
- * expect that interrupts will fire on a single core at a time and
- * that the irq can be enabled or disabled from any core at any time.
- * We implement this by directing such interrupts to a single core.
- *
- * One added wrinkle is that PCI interrupts can be either
- * hardware-cleared (legacy interrupts) or software cleared (MSI).
- * Other generic device systems (GPIO) are always software-cleared.
- *
- * The enums below are used by drivers for onboard devices, including
- * the internals of PCI root complex and GPIO. They allow the driver
- * to tell the generic irq code what kind of interrupt is mapped to a
- * particular IRQ number.
- */
-enum {
- /* per-cpu interrupt; use enable/disable_percpu_irq() to mask */
- TILE_IRQ_PERCPU,
- /* global interrupt, hardware responsible for clearing. */
- TILE_IRQ_HW_CLEAR,
- /* global interrupt, software responsible for clearing. */
- TILE_IRQ_SW_CLEAR,
-};
-
-
-/*
- * Paravirtualized drivers should call this when they dynamically
- * allocate a new IRQ or discover an IRQ that was pre-allocated by the
- * hypervisor for use with their particular device. This gives the
- * IRQ subsystem an opportunity to do interrupt-type-specific
- * initialization.
- *
- * ISSUE: We should modify this API so that registering anything
- * except percpu interrupts also requires providing callback methods
- * for enabling and disabling the interrupt. This would allow the
- * generic IRQ code to proxy enable/disable_irq() calls back into the
- * PCI subsystem, which in turn could enable or disable the interrupt
- * at the PCI shim.
- */
-void tile_irq_activate(unsigned int irq, int tile_irq_type);
-
-void setup_irq_regs(void);
-
-#ifdef __tilegx__
-void arch_trigger_cpumask_backtrace(const struct cpumask *mask,
- bool exclude_self);
-#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
-#endif
-
-#endif /* _ASM_TILE_IRQ_H */
diff --git a/arch/tile/include/asm/irq_work.h b/arch/tile/include/asm/irq_work.h
deleted file mode 100644
index 78d3b6a7b27a..000000000000
--- a/arch/tile/include/asm/irq_work.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_IRQ_WORK_H
-#define __ASM_IRQ_WORK_H
-
-static inline bool arch_irq_work_has_interrupt(void)
-{
-#ifdef CONFIG_SMP
- extern bool self_interrupt_ok;
- return self_interrupt_ok;
-#else
- return false;
-#endif
-}
-
-#endif /* __ASM_IRQ_WORK_H */
diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h
deleted file mode 100644
index 60d62a292fce..000000000000
--- a/arch/tile/include/asm/irqflags.h
+++ /dev/null
@@ -1,311 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_IRQFLAGS_H
-#define _ASM_TILE_IRQFLAGS_H
-
-#include <arch/interrupts.h>
-#include <arch/chip.h>
-
-/*
- * The set of interrupts we want to allow when interrupts are nominally
- * disabled. The remainder are effectively "NMI" interrupts from
- * the point of view of the generic Linux code. Note that synchronous
- * interrupts (aka "non-queued") are not blocked by the mask in any case.
- */
-#define LINUX_MASKABLE_INTERRUPTS \
- (~((_AC(1,ULL) << INT_PERF_COUNT) | (_AC(1,ULL) << INT_AUX_PERF_COUNT)))
-
-#if CHIP_HAS_SPLIT_INTR_MASK()
-/* The same macro, but for the two 32-bit SPRs separately. */
-#define LINUX_MASKABLE_INTERRUPTS_LO (-1)
-#define LINUX_MASKABLE_INTERRUPTS_HI \
- (~((1 << (INT_PERF_COUNT - 32)) | (1 << (INT_AUX_PERF_COUNT - 32))))
-#endif
-
-#ifndef __ASSEMBLY__
-
-/* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
-#include <asm/percpu.h>
-#include <arch/spr_def.h>
-
-/*
- * Set and clear kernel interrupt masks.
- *
- * NOTE: __insn_mtspr() is a compiler builtin marked as a memory
- * clobber. We rely on it being equivalent to a compiler barrier in
- * this code since arch_local_irq_save() and friends must act as
- * compiler barriers. This compiler semantic is baked into enough
- * places that the compiler will maintain it going forward.
- */
-#if CHIP_HAS_SPLIT_INTR_MASK()
-#if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32 || INT_MEM_ERROR >= 32
-# error Fix assumptions about which word various interrupts are in
-#endif
-#define interrupt_mask_set(n) do { \
- int __n = (n); \
- int __mask = 1 << (__n & 0x1f); \
- if (__n < 32) \
- __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
- else \
- __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
-} while (0)
-#define interrupt_mask_reset(n) do { \
- int __n = (n); \
- int __mask = 1 << (__n & 0x1f); \
- if (__n < 32) \
- __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
- else \
- __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
-} while (0)
-#define interrupt_mask_check(n) ({ \
- int __n = (n); \
- (((__n < 32) ? \
- __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
- __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
- >> (__n & 0x1f)) & 1; \
-})
-#define interrupt_mask_set_mask(mask) do { \
- unsigned long long __m = (mask); \
- __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
- __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
-} while (0)
-#define interrupt_mask_reset_mask(mask) do { \
- unsigned long long __m = (mask); \
- __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
- __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
-} while (0)
-#define interrupt_mask_save_mask() \
- (__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_0) | \
- (((unsigned long long)__insn_mfspr(SPR_INTERRUPT_MASK_SET_K_1))<<32))
-#define interrupt_mask_restore_mask(mask) do { \
- unsigned long long __m = (mask); \
- __insn_mtspr(SPR_INTERRUPT_MASK_K_0, (unsigned long)(__m)); \
- __insn_mtspr(SPR_INTERRUPT_MASK_K_1, (unsigned long)(__m>>32)); \
-} while (0)
-#else
-#define interrupt_mask_set(n) \
- __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
-#define interrupt_mask_reset(n) \
- __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
-#define interrupt_mask_check(n) \
- ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
-#define interrupt_mask_set_mask(mask) \
- __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
-#define interrupt_mask_reset_mask(mask) \
- __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
-#define interrupt_mask_save_mask() \
- __insn_mfspr(SPR_INTERRUPT_MASK_K)
-#define interrupt_mask_restore_mask(mask) \
- __insn_mtspr(SPR_INTERRUPT_MASK_K, (mask))
-#endif
-
-/*
- * The set of interrupts we want active if irqs are enabled.
- * Note that in particular, the tile timer interrupt comes and goes
- * from this set, since we have no other way to turn off the timer.
- * Likewise, INTCTRL_K is removed and re-added during device
- * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
- * We use a low bit (MEM_ERROR) as our sentinel value and make sure it
- * is always claimed as an "active interrupt" so we can query that bit
- * to know our current state.
- */
-DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
-#define INITIAL_INTERRUPTS_ENABLED (1ULL << INT_MEM_ERROR)
-
-#ifdef CONFIG_DEBUG_PREEMPT
-/* Due to inclusion issues, we can't rely on <linux/smp.h> here. */
-extern unsigned int debug_smp_processor_id(void);
-# define smp_processor_id() debug_smp_processor_id()
-#endif
-
-/* Disable interrupts. */
-#define arch_local_irq_disable() \
- interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
-
-/* Disable all interrupts, including NMIs. */
-#define arch_local_irq_disable_all() \
- interrupt_mask_set_mask(-1ULL)
-
-/*
- * Read the set of maskable interrupts.
- * We avoid the preemption warning here via raw_cpu_ptr since even
- * if irqs are already enabled, it's harmless to read the wrong cpu's
- * enabled mask.
- */
-#define arch_local_irqs_enabled() \
- (*raw_cpu_ptr(&interrupts_enabled_mask))
-
-/* Re-enable all maskable interrupts. */
-#define arch_local_irq_enable() \
- interrupt_mask_reset_mask(arch_local_irqs_enabled())
-
-/* Disable or enable interrupts based on flag argument. */
-#define arch_local_irq_restore(disabled) do { \
- if (disabled) \
- arch_local_irq_disable(); \
- else \
- arch_local_irq_enable(); \
-} while (0)
-
-/* Return true if "flags" argument means interrupts are disabled. */
-#define arch_irqs_disabled_flags(flags) ((flags) != 0)
-
-/* Return true if interrupts are currently disabled. */
-#define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
-
-/* Save whether interrupts are currently disabled. */
-#define arch_local_save_flags() arch_irqs_disabled()
-
-/* Save whether interrupts are currently disabled, then disable them. */
-#define arch_local_irq_save() ({ \
- unsigned long __flags = arch_local_save_flags(); \
- arch_local_irq_disable(); \
- __flags; })
-
-/* Prevent the given interrupt from being enabled next time we enable irqs. */
-#define arch_local_irq_mask(interrupt) \
- this_cpu_and(interrupts_enabled_mask, ~(1ULL << (interrupt)))
-
-/* Prevent the given interrupt from being enabled immediately. */
-#define arch_local_irq_mask_now(interrupt) do { \
- arch_local_irq_mask(interrupt); \
- interrupt_mask_set(interrupt); \
-} while (0)
-
-/* Allow the given interrupt to be enabled next time we enable irqs. */
-#define arch_local_irq_unmask(interrupt) \
- this_cpu_or(interrupts_enabled_mask, (1ULL << (interrupt)))
-
-/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
-#define arch_local_irq_unmask_now(interrupt) do { \
- arch_local_irq_unmask(interrupt); \
- if (!irqs_disabled()) \
- interrupt_mask_reset(interrupt); \
-} while (0)
-
-#else /* __ASSEMBLY__ */
-
-/* We provide a somewhat more restricted set for assembly. */
-
-#ifdef __tilegx__
-
-#if INT_MEM_ERROR != 0
-# error Fix IRQS_DISABLED() macro
-#endif
-
-/* Return 0 or 1 to indicate whether interrupts are currently disabled. */
-#define IRQS_DISABLED(tmp) \
- mfspr tmp, SPR_INTERRUPT_MASK_K; \
- andi tmp, tmp, 1
-
-/* Load up a pointer to &interrupts_enabled_mask. */
-#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
- moveli reg, hw2_last(interrupts_enabled_mask); \
- shl16insli reg, reg, hw1(interrupts_enabled_mask); \
- shl16insli reg, reg, hw0(interrupts_enabled_mask); \
- add reg, reg, tp
-
-/* Disable interrupts. */
-#define IRQ_DISABLE(tmp0, tmp1) \
- moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \
- shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \
- shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \
- mtspr SPR_INTERRUPT_MASK_SET_K, tmp0
-
-/* Disable ALL synchronous interrupts (used by NMI entry). */
-#define IRQ_DISABLE_ALL(tmp) \
- movei tmp, -1; \
- mtspr SPR_INTERRUPT_MASK_SET_K, tmp
-
-/* Enable interrupts. */
-#define IRQ_ENABLE_LOAD(tmp0, tmp1) \
- GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
- ld tmp0, tmp0
-#define IRQ_ENABLE_APPLY(tmp0, tmp1) \
- mtspr SPR_INTERRUPT_MASK_RESET_K, tmp0
-
-#else /* !__tilegx__ */
-
-/*
- * Return 0 or 1 to indicate whether interrupts are currently disabled.
- * Note that it's important that we use a bit from the "low" mask word,
- * since when we are enabling, that is the word we write first, so if we
- * are interrupted after only writing half of the mask, the interrupt
- * handler will correctly observe that we have interrupts enabled, and
- * will enable interrupts itself on return from the interrupt handler
- * (making the original code's write of the "high" mask word idempotent).
- */
-#define IRQS_DISABLED(tmp) \
- mfspr tmp, SPR_INTERRUPT_MASK_K_0; \
- shri tmp, tmp, INT_MEM_ERROR; \
- andi tmp, tmp, 1
-
-/* Load up a pointer to &interrupts_enabled_mask. */
-#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
- moveli reg, lo16(interrupts_enabled_mask); \
- auli reg, reg, ha16(interrupts_enabled_mask); \
- add reg, reg, tp
-
-/* Disable interrupts. */
-#define IRQ_DISABLE(tmp0, tmp1) \
- { \
- movei tmp0, LINUX_MASKABLE_INTERRUPTS_LO; \
- moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
- }; \
- { \
- mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp0; \
- auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI) \
- }; \
- mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1
-
-/* Disable ALL synchronous interrupts (used by NMI entry). */
-#define IRQ_DISABLE_ALL(tmp) \
- movei tmp, -1; \
- mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp; \
- mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp
-
-/* Enable interrupts. */
-#define IRQ_ENABLE_LOAD(tmp0, tmp1) \
- GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
- { \
- lw tmp0, tmp0; \
- addi tmp1, tmp0, 4 \
- }; \
- lw tmp1, tmp1
-#define IRQ_ENABLE_APPLY(tmp0, tmp1) \
- mtspr SPR_INTERRUPT_MASK_RESET_K_0, tmp0; \
- mtspr SPR_INTERRUPT_MASK_RESET_K_1, tmp1
-#endif
-
-#define IRQ_ENABLE(tmp0, tmp1) \
- IRQ_ENABLE_LOAD(tmp0, tmp1); \
- IRQ_ENABLE_APPLY(tmp0, tmp1)
-
-/*
- * Do the CPU's IRQ-state tracing from assembly code. We call a
- * C function, but almost everywhere we do, we don't mind clobbering
- * all the caller-saved registers.
- */
-#ifdef CONFIG_TRACE_IRQFLAGS
-# define TRACE_IRQS_ON jal trace_hardirqs_on
-# define TRACE_IRQS_OFF jal trace_hardirqs_off
-#else
-# define TRACE_IRQS_ON
-# define TRACE_IRQS_OFF
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_TILE_IRQFLAGS_H */
diff --git a/arch/tile/include/asm/jump_label.h b/arch/tile/include/asm/jump_label.h
deleted file mode 100644
index cde7573f397b..000000000000
--- a/arch/tile/include/asm/jump_label.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright 2015 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_JUMP_LABEL_H
-#define _ASM_TILE_JUMP_LABEL_H
-
-#include <arch/opcode.h>
-
-#define JUMP_LABEL_NOP_SIZE TILE_BUNDLE_SIZE_IN_BYTES
-
-static __always_inline bool arch_static_branch(struct static_key *key,
- bool branch)
-{
- asm_volatile_goto("1:\n\t"
- "nop" "\n\t"
- ".pushsection __jump_table, \"aw\"\n\t"
- ".quad 1b, %l[l_yes], %0 + %1 \n\t"
- ".popsection\n\t"
- : : "i" (key), "i" (branch) : : l_yes);
- return false;
-l_yes:
- return true;
-}
-
-static __always_inline bool arch_static_branch_jump(struct static_key *key,
- bool branch)
-{
- asm_volatile_goto("1:\n\t"
- "j %l[l_yes]" "\n\t"
- ".pushsection __jump_table, \"aw\"\n\t"
- ".quad 1b, %l[l_yes], %0 + %1 \n\t"
- ".popsection\n\t"
- : : "i" (key), "i" (branch) : : l_yes);
- return false;
-l_yes:
- return true;
-}
-
-typedef u64 jump_label_t;
-
-struct jump_entry {
- jump_label_t code;
- jump_label_t target;
- jump_label_t key;
-};
-
-#endif /* _ASM_TILE_JUMP_LABEL_H */
diff --git a/arch/tile/include/asm/kdebug.h b/arch/tile/include/asm/kdebug.h
deleted file mode 100644
index 5bbbfa904c2d..000000000000
--- a/arch/tile/include/asm/kdebug.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_KDEBUG_H
-#define _ASM_TILE_KDEBUG_H
-
-#include <linux/notifier.h>
-
-enum die_val {
- DIE_OOPS = 1,
- DIE_BREAK,
- DIE_SSTEPBP,
- DIE_PAGE_FAULT,
- DIE_COMPILED_BPT
-};
-
-#endif /* _ASM_TILE_KDEBUG_H */
diff --git a/arch/tile/include/asm/kexec.h b/arch/tile/include/asm/kexec.h
deleted file mode 100644
index fc98ccfc98ac..000000000000
--- a/arch/tile/include/asm/kexec.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * based on kexec.h from other architectures in linux-2.6.18
- */
-
-#ifndef _ASM_TILE_KEXEC_H
-#define _ASM_TILE_KEXEC_H
-
-#include <asm/page.h>
-
-#ifndef __tilegx__
-/* Maximum physical address we can use pages from. */
-#define KEXEC_SOURCE_MEMORY_LIMIT TASK_SIZE
-/* Maximum address we can reach in physical address mode. */
-#define KEXEC_DESTINATION_MEMORY_LIMIT TASK_SIZE
-/* Maximum address we can use for the control code buffer. */
-#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
-#else
-/* We need to limit the memory below PGDIR_SIZE since
- * we only setup page table for [0, PGDIR_SIZE) before final kexec.
- */
-/* Maximum physical address we can use pages from. */
-#define KEXEC_SOURCE_MEMORY_LIMIT PGDIR_SIZE
-/* Maximum address we can reach in physical address mode. */
-#define KEXEC_DESTINATION_MEMORY_LIMIT PGDIR_SIZE
-/* Maximum address we can use for the control code buffer. */
-#define KEXEC_CONTROL_MEMORY_LIMIT PGDIR_SIZE
-#endif
-
-#define KEXEC_CONTROL_PAGE_SIZE PAGE_SIZE
-
-/*
- * We don't bother to provide a unique identifier, since we can only
- * reboot with a single type of kernel image anyway.
- */
-#define KEXEC_ARCH KEXEC_ARCH_DEFAULT
-
-/* Use the tile override for the page allocator. */
-struct page *kimage_alloc_pages_arch(gfp_t gfp_mask, unsigned int order);
-#define kimage_alloc_pages_arch kimage_alloc_pages_arch
-
-#define MAX_NOTE_BYTES 1024
-
-/* Defined in arch/tile/kernel/relocate_kernel.S */
-extern const unsigned char relocate_new_kernel[];
-extern const unsigned long relocate_new_kernel_size;
-extern void relocate_new_kernel_end(void);
-
-/* Provide a dummy definition to avoid build failures. */
-static inline void crash_setup_regs(struct pt_regs *n, struct pt_regs *o)
-{
-}
-
-#endif /* _ASM_TILE_KEXEC_H */
diff --git a/arch/tile/include/asm/kgdb.h b/arch/tile/include/asm/kgdb.h
deleted file mode 100644
index 280c181cf0db..000000000000
--- a/arch/tile/include/asm/kgdb.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE-Gx KGDB support.
- */
-
-#ifndef __TILE_KGDB_H__
-#define __TILE_KGDB_H__
-
-#include <linux/kdebug.h>
-#include <arch/opcode.h>
-
-#define GDB_SIZEOF_REG sizeof(unsigned long)
-
-/*
- * TILE-Gx gdb is expecting the following register layout:
- * 56 GPRs(R0 - R52, TP, SP, LR), 8 special GPRs(networks and ZERO),
- * plus the PC and the faultnum.
- *
- * Even though kernel not use the 8 special GPRs, they need to be present
- * in the registers sent for correct processing in the host-side gdb.
- *
- */
-#define DBG_MAX_REG_NUM (56+8+2)
-#define NUMREGBYTES (DBG_MAX_REG_NUM * GDB_SIZEOF_REG)
-
-/*
- * BUFMAX defines the maximum number of characters in inbound/outbound
- * buffers at least NUMREGBYTES*2 are needed for register packets,
- * Longer buffer is needed to list all threads.
- */
-#define BUFMAX 2048
-
-#define BREAK_INSTR_SIZE TILEGX_BUNDLE_SIZE_IN_BYTES
-
-/*
- * Require cache flush for set/clear a software breakpoint or write memory.
- */
-#define CACHE_FLUSH_IS_SAFE 1
-
-/*
- * The compiled-in breakpoint instruction can be used to "break" into
- * the debugger via magic system request key (sysrq-G).
- */
-static tile_bundle_bits compiled_bpt = TILEGX_BPT_BUNDLE | DIE_COMPILED_BPT;
-
-enum tilegx_regnum {
- TILEGX_PC_REGNUM = TREG_LAST_GPR + 9,
- TILEGX_FAULTNUM_REGNUM,
-};
-
-/*
- * Generate a breakpoint exception to "break" into the debugger.
- */
-static inline void arch_kgdb_breakpoint(void)
-{
- asm volatile (".quad %0\n\t"
- ::""(compiled_bpt));
-}
-
-#endif /* __TILE_KGDB_H__ */
diff --git a/arch/tile/include/asm/kmap_types.h b/arch/tile/include/asm/kmap_types.h
deleted file mode 100644
index 92b28e3e9972..000000000000
--- a/arch/tile/include/asm/kmap_types.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_KMAP_TYPES_H
-#define _ASM_TILE_KMAP_TYPES_H
-
-/*
- * In 32-bit TILE Linux we have to balance the desire to have a lot of
- * nested atomic mappings with the fact that large page sizes and many
- * processors chew up address space quickly. In a typical
- * 64-processor, 64KB-page layout build, making KM_TYPE_NR one larger
- * adds 4MB of required address-space. For now we leave KM_TYPE_NR
- * set to depth 8.
- */
-#define KM_TYPE_NR 8
-
-#endif /* _ASM_TILE_KMAP_TYPES_H */
diff --git a/arch/tile/include/asm/kprobes.h b/arch/tile/include/asm/kprobes.h
deleted file mode 100644
index 4a8b1cadca24..000000000000
--- a/arch/tile/include/asm/kprobes.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * arch/tile/include/asm/kprobes.h
- *
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_KPROBES_H
-#define _ASM_TILE_KPROBES_H
-
-#include <asm-generic/kprobes.h>
-
-#ifdef CONFIG_KPROBES
-
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/percpu.h>
-#include <arch/opcode.h>
-
-#define __ARCH_WANT_KPROBES_INSN_SLOT
-#define MAX_INSN_SIZE 2
-
-#define kretprobe_blacklist_size 0
-
-typedef tile_bundle_bits kprobe_opcode_t;
-
-#define flush_insn_slot(p) \
- flush_icache_range((unsigned long)p->addr, \
- (unsigned long)p->addr + \
- (MAX_INSN_SIZE * sizeof(kprobe_opcode_t)))
-
-struct kprobe;
-
-/* Architecture specific copy of original instruction. */
-struct arch_specific_insn {
- kprobe_opcode_t *insn;
-};
-
-struct prev_kprobe {
- struct kprobe *kp;
- unsigned long status;
- unsigned long saved_pc;
-};
-
-#define MAX_JPROBES_STACK_SIZE 128
-#define MAX_JPROBES_STACK_ADDR \
- (((unsigned long)current_thread_info()) + THREAD_SIZE - 32 \
- - sizeof(struct pt_regs))
-
-#define MIN_JPROBES_STACK_SIZE(ADDR) \
- ((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR) \
- ? MAX_JPROBES_STACK_ADDR - (ADDR) \
- : MAX_JPROBES_STACK_SIZE)
-
-/* per-cpu kprobe control block. */
-struct kprobe_ctlblk {
- unsigned long kprobe_status;
- unsigned long kprobe_saved_pc;
- unsigned long jprobe_saved_sp;
- struct prev_kprobe prev_kprobe;
- struct pt_regs jprobe_saved_regs;
- char jprobes_stack[MAX_JPROBES_STACK_SIZE];
-};
-
-extern tile_bundle_bits breakpoint2_insn;
-extern tile_bundle_bits breakpoint_insn;
-
-void arch_remove_kprobe(struct kprobe *);
-
-extern int kprobe_exceptions_notify(struct notifier_block *self,
- unsigned long val, void *data);
-
-#endif /* CONFIG_KPROBES */
-#endif /* _ASM_TILE_KPROBES_H */
diff --git a/arch/tile/include/asm/linkage.h b/arch/tile/include/asm/linkage.h
deleted file mode 100644
index e121c39751a7..000000000000
--- a/arch/tile/include/asm/linkage.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_LINKAGE_H
-#define _ASM_TILE_LINKAGE_H
-
-#include <feedback.h>
-
-#define __ALIGN .align 8
-
-/*
- * The STD_ENTRY and STD_ENDPROC macros put the function in a
- * self-named .text.foo section, and if linker feedback collection
- * is enabled, add a suitable call to the feedback collection code.
- * STD_ENTRY_SECTION lets you specify a non-standard section name.
- */
-
-#define STD_ENTRY(name) \
- .pushsection .text.##name, "ax"; \
- ENTRY(name); \
- FEEDBACK_ENTER(name)
-
-#define STD_ENTRY_SECTION(name, section) \
- .pushsection section, "ax"; \
- ENTRY(name); \
- FEEDBACK_ENTER_EXPLICIT(name, section, .Lend_##name - name)
-
-#define STD_ENDPROC(name) \
- ENDPROC(name); \
- .Lend_##name:; \
- .popsection
-
-/* Create a file-static function entry set up for feedback gathering. */
-#define STD_ENTRY_LOCAL(name) \
- .pushsection .text.##name, "ax"; \
- ALIGN; \
- name:; \
- FEEDBACK_ENTER(name)
-
-#endif /* _ASM_TILE_LINKAGE_H */
diff --git a/arch/tile/include/asm/mmu.h b/arch/tile/include/asm/mmu.h
deleted file mode 100644
index 0cab1182bde1..000000000000
--- a/arch/tile/include/asm/mmu.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_MMU_H
-#define _ASM_TILE_MMU_H
-
-/* Capture any arch- and mm-specific information. */
-struct mm_context {
- /*
- * Written under the mmap_sem semaphore; read without the
- * semaphore but atomically, but it is conservatively set.
- */
- unsigned long priority_cached;
- unsigned long vdso_base;
-};
-
-typedef struct mm_context mm_context_t;
-
-void leave_mm(int cpu);
-
-#endif /* _ASM_TILE_MMU_H */
diff --git a/arch/tile/include/asm/mmu_context.h b/arch/tile/include/asm/mmu_context.h
deleted file mode 100644
index 45a4b4c424cf..000000000000
--- a/arch/tile/include/asm/mmu_context.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_MMU_CONTEXT_H
-#define _ASM_TILE_MMU_CONTEXT_H
-
-#include <linux/smp.h>
-#include <linux/mm_types.h>
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/pgtable.h>
-#include <asm/tlbflush.h>
-#include <asm/homecache.h>
-#include <asm-generic/mm_hooks.h>
-
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
- return 0;
-}
-
-/*
- * Note that arch/tile/kernel/head_NN.S and arch/tile/mm/migrate_NN.S
- * also call hv_install_context().
- */
-static inline void __install_page_table(pgd_t *pgdir, int asid, pgprot_t prot)
-{
- /* FIXME: DIRECTIO should not always be set. FIXME. */
- int rc = hv_install_context(__pa(pgdir), prot, asid,
- HV_CTX_DIRECTIO | CTX_PAGE_FLAG);
- if (rc < 0)
- panic("hv_install_context failed: %d", rc);
-}
-
-static inline void install_page_table(pgd_t *pgdir, int asid)
-{
- pte_t *ptep = virt_to_kpte((unsigned long)pgdir);
- __install_page_table(pgdir, asid, *ptep);
-}
-
-/*
- * "Lazy" TLB mode is entered when we are switching to a kernel task,
- * which borrows the mm of the previous task. The goal of this
- * optimization is to avoid having to install a new page table. On
- * early x86 machines (where the concept originated) you couldn't do
- * anything short of a full page table install for invalidation, so
- * handling a remote TLB invalidate required doing a page table
- * re-install. Someone clearly decided that it was silly to keep
- * doing this while in "lazy" TLB mode, so the optimization involves
- * installing the swapper page table instead the first time one
- * occurs, and clearing the cpu out of cpu_vm_mask, so the cpu running
- * the kernel task doesn't need to take any more interrupts. At that
- * point it's then necessary to explicitly reinstall it when context
- * switching back to the original mm.
- *
- * On Tile, we have to do a page-table install whenever DMA is enabled,
- * so in that case lazy mode doesn't help anyway. And more generally,
- * we have efficient per-page TLB shootdown, and don't expect to spend
- * that much time in kernel tasks in general, so just leaving the
- * kernel task borrowing the old page table, but handling TLB
- * shootdowns, is a reasonable thing to do. And importantly, this
- * lets us use the hypervisor's internal APIs for TLB shootdown, which
- * means we don't have to worry about having TLB shootdowns blocked
- * when Linux is disabling interrupts; see the page migration code for
- * an example of where it's important for TLB shootdowns to complete
- * even when interrupts are disabled at the Linux level.
- */
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *t)
-{
-#if CHIP_HAS_TILE_DMA()
- /*
- * We have to do an "identity" page table switch in order to
- * clear any pending DMA interrupts.
- */
- if (current->thread.tile_dma_state.enabled)
- install_page_table(mm->pgd, __this_cpu_read(current_asid));
-#endif
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- if (likely(prev != next)) {
-
- int cpu = smp_processor_id();
-
- /* Pick new ASID. */
- int asid = __this_cpu_read(current_asid) + 1;
- if (asid > max_asid) {
- asid = min_asid;
- local_flush_tlb();
- }
- __this_cpu_write(current_asid, asid);
-
- /* Clear cpu from the old mm, and set it in the new one. */
- cpumask_clear_cpu(cpu, mm_cpumask(prev));
- cpumask_set_cpu(cpu, mm_cpumask(next));
-
- /* Re-load page tables */
- install_page_table(next->pgd, asid);
-
- /* See how we should set the red/black cache info */
- check_mm_caching(prev, next);
-
- /*
- * Since we're changing to a new mm, we have to flush
- * the icache in case some physical page now being mapped
- * has subsequently been repurposed and has new code.
- */
- __flush_icache();
-
- }
-}
-
-static inline void activate_mm(struct mm_struct *prev_mm,
- struct mm_struct *next_mm)
-{
- switch_mm(prev_mm, next_mm, NULL);
-}
-
-#define destroy_context(mm) do { } while (0)
-#define deactivate_mm(tsk, mm) do { } while (0)
-
-#endif /* _ASM_TILE_MMU_CONTEXT_H */
diff --git a/arch/tile/include/asm/mmzone.h b/arch/tile/include/asm/mmzone.h
deleted file mode 100644
index 804f1098b6cd..000000000000
--- a/arch/tile/include/asm/mmzone.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_MMZONE_H
-#define _ASM_TILE_MMZONE_H
-
-extern struct pglist_data node_data[];
-#define NODE_DATA(nid) (&node_data[nid])
-
-extern void get_memcfg_numa(void);
-
-#ifdef CONFIG_DISCONTIGMEM
-
-#include <asm/page.h>
-
-/*
- * Generally, memory ranges are always doled out by the hypervisor in
- * fixed-size, power-of-two increments. That would make computing the node
- * very easy. We could just take a couple high bits of the PA, which
- * denote the memory shim, and we'd be done. However, when we're doing
- * memory striping, this may not be true; PAs with different high bit
- * values might be in the same node. Thus, we keep a lookup table to
- * translate the high bits of the PFN to the node number.
- */
-extern int highbits_to_node[];
-
-static inline int pfn_to_nid(unsigned long pfn)
-{
- return highbits_to_node[__pfn_to_highbits(pfn)];
-}
-
-#define kern_addr_valid(kaddr) virt_addr_valid((void *)kaddr)
-
-static inline int pfn_valid(unsigned long pfn)
-{
- int nid = pfn_to_nid(pfn);
-
- if (nid >= 0)
- return (pfn < node_end_pfn(nid));
- return 0;
-}
-
-/* Information on the NUMA nodes that we compute early */
-extern unsigned long node_start_pfn[];
-extern unsigned long node_end_pfn[];
-extern unsigned long node_memmap_pfn[];
-extern unsigned long node_percpu_pfn[];
-extern unsigned long node_free_pfn[];
-#ifdef CONFIG_HIGHMEM
-extern unsigned long node_lowmem_end_pfn[];
-#endif
-#ifdef CONFIG_PCI
-extern unsigned long pci_reserve_start_pfn;
-extern unsigned long pci_reserve_end_pfn;
-#endif
-
-#endif /* CONFIG_DISCONTIGMEM */
-
-#endif /* _ASM_TILE_MMZONE_H */
diff --git a/arch/tile/include/asm/module.h b/arch/tile/include/asm/module.h
deleted file mode 100644
index 44ed07ccd3d2..000000000000
--- a/arch/tile/include/asm/module.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_MODULE_H
-#define _ASM_TILE_MODULE_H
-
-#include <arch/chip.h>
-
-#include <asm-generic/module.h>
-
-/* We can't use modules built with different page sizes. */
-#if defined(CONFIG_PAGE_SIZE_16KB)
-# define MODULE_PGSZ " 16KB"
-#elif defined(CONFIG_PAGE_SIZE_64KB)
-# define MODULE_PGSZ " 64KB"
-#else
-# define MODULE_PGSZ ""
-#endif
-
-/* We don't really support no-SMP so tag if someone tries. */
-#ifdef CONFIG_SMP
-#define MODULE_NOSMP ""
-#else
-#define MODULE_NOSMP " nosmp"
-#endif
-
-#define MODULE_ARCH_VERMAGIC CHIP_ARCH_NAME MODULE_PGSZ MODULE_NOSMP
-
-#endif /* _ASM_TILE_MODULE_H */
diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h
deleted file mode 100644
index 498a5f71245d..000000000000
--- a/arch/tile/include/asm/page.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_PAGE_H
-#define _ASM_TILE_PAGE_H
-
-#include <linux/const.h>
-#include <hv/hypervisor.h>
-#include <arch/chip.h>
-
-/* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */
-#if defined(CONFIG_PAGE_SIZE_4KB) /* tilepro only */
-#define PAGE_SHIFT 12
-#define CTX_PAGE_FLAG HV_CTX_PG_SM_4K
-#elif defined(CONFIG_PAGE_SIZE_16KB)
-#define PAGE_SHIFT 14
-#define CTX_PAGE_FLAG HV_CTX_PG_SM_16K
-#elif defined(CONFIG_PAGE_SIZE_64KB)
-#define PAGE_SHIFT 16
-#define CTX_PAGE_FLAG HV_CTX_PG_SM_64K
-#else
-#error Page size not specified in Kconfig
-#endif
-#define HPAGE_SHIFT HV_LOG2_DEFAULT_PAGE_SIZE_LARGE
-
-#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
-#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
-
-#define PAGE_MASK (~(PAGE_SIZE - 1))
-#define HPAGE_MASK (~(HPAGE_SIZE - 1))
-
-/*
- * If the Kconfig doesn't specify, set a maximum zone order that
- * is enough so that we can create huge pages from small pages given
- * the respective sizes of the two page types. See <linux/mmzone.h>.
- */
-#ifndef CONFIG_FORCE_MAX_ZONEORDER
-#define CONFIG_FORCE_MAX_ZONEORDER (HPAGE_SHIFT - PAGE_SHIFT + 1)
-#endif
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-#include <linux/string.h>
-
-struct page;
-
-static inline void clear_page(void *page)
-{
- memset(page, 0, PAGE_SIZE);
-}
-
-static inline void copy_page(void *to, void *from)
-{
- memcpy(to, from, PAGE_SIZE);
-}
-
-static inline void clear_user_page(void *page, unsigned long vaddr,
- struct page *pg)
-{
- clear_page(page);
-}
-
-static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
- struct page *topage)
-{
- copy_page(to, from);
-}
-
-/*
- * Hypervisor page tables are made of the same basic structure.
- */
-
-typedef HV_PTE pte_t;
-typedef HV_PTE pgd_t;
-typedef HV_PTE pgprot_t;
-
-/*
- * User L2 page tables are managed as one L2 page table per page,
- * because we use the page allocator for them. This keeps the allocation
- * simple, but it's also inefficient, since L2 page tables are much smaller
- * than pages (currently 2KB vs 64KB). So we should revisit this.
- */
-typedef struct page *pgtable_t;
-
-/* Must be a macro since it is used to create constants. */
-#define __pgprot(val) hv_pte(val)
-
-/* Rarely-used initializers, typically with a "zero" value. */
-#define __pte(x) hv_pte(x)
-#define __pgd(x) hv_pte(x)
-
-static inline u64 pgprot_val(pgprot_t pgprot)
-{
- return hv_pte_val(pgprot);
-}
-
-static inline u64 pte_val(pte_t pte)
-{
- return hv_pte_val(pte);
-}
-
-static inline u64 pgd_val(pgd_t pgd)
-{
- return hv_pte_val(pgd);
-}
-
-#ifdef __tilegx__
-
-typedef HV_PTE pmd_t;
-
-#define __pmd(x) hv_pte(x)
-
-static inline u64 pmd_val(pmd_t pmd)
-{
- return hv_pte_val(pmd);
-}
-
-#endif
-
-static inline __attribute_const__ int get_order(unsigned long size)
-{
- return BITS_PER_LONG - __builtin_clzl((size - 1) >> PAGE_SHIFT);
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
-
-#define HUGE_MAX_HSTATE 6
-
-#ifdef CONFIG_HUGETLB_PAGE
-#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
-#endif
-
-/* Allow overriding how much VA or PA the kernel will use. */
-#define MAX_PA_WIDTH CHIP_PA_WIDTH()
-#define MAX_VA_WIDTH CHIP_VA_WIDTH()
-
-/* Each memory controller has PAs distinct in their high bits. */
-#define NR_PA_HIGHBIT_SHIFT (MAX_PA_WIDTH - CHIP_LOG_NUM_MSHIMS())
-#define NR_PA_HIGHBIT_VALUES (1 << CHIP_LOG_NUM_MSHIMS())
-#define __pa_to_highbits(pa) ((phys_addr_t)(pa) >> NR_PA_HIGHBIT_SHIFT)
-#define __pfn_to_highbits(pfn) ((pfn) >> (NR_PA_HIGHBIT_SHIFT - PAGE_SHIFT))
-
-#ifdef __tilegx__
-
-/*
- * We reserve the lower half of memory for user-space programs, and the
- * upper half for system code. We re-map all of physical memory in the
- * upper half, which takes a quarter of our VA space. Then we have
- * the vmalloc regions. The supervisor code lives at the highest address,
- * with the hypervisor above that.
- *
- * Loadable kernel modules are placed immediately after the static
- * supervisor code, with each being allocated a 256MB region of
- * address space, so we don't have to worry about the range of "jal"
- * and other branch instructions.
- *
- * For now we keep life simple and just allocate one pmd (4GB) for vmalloc.
- * Similarly, for now we don't play any struct page mapping games.
- */
-
-#if MAX_PA_WIDTH + 2 > MAX_VA_WIDTH
-# error Too much PA to map with the VA available!
-#endif
-
-#define PAGE_OFFSET (-(_AC(1, UL) << (MAX_VA_WIDTH - 1)))
-#define KERNEL_HIGH_VADDR _AC(0xfffffff800000000, UL) /* high 32GB */
-#define FIXADDR_BASE (KERNEL_HIGH_VADDR - 0x300000000) /* 4 GB */
-#define FIXADDR_TOP (KERNEL_HIGH_VADDR - 0x200000000) /* 4 GB */
-#define _VMALLOC_START FIXADDR_TOP
-#define MEM_SV_START (KERNEL_HIGH_VADDR - 0x100000000) /* 256 MB */
-#define MEM_MODULE_START (MEM_SV_START + (256*1024*1024)) /* 256 MB */
-#define MEM_MODULE_END (MEM_MODULE_START + (256*1024*1024))
-
-#else /* !__tilegx__ */
-
-/*
- * A PAGE_OFFSET of 0xC0000000 means that the kernel has
- * a virtual address space of one gigabyte, which limits the
- * amount of physical memory you can use to about 768MB.
- * If you want more physical memory than this then see the CONFIG_HIGHMEM
- * option in the kernel configuration.
- *
- * The top 16MB chunk in the table below is unavailable to Linux. Since
- * the kernel interrupt vectors must live at ether 0xfe000000 or 0xfd000000
- * (depending on whether the kernel is at PL2 or Pl1), we map all of the
- * bottom of RAM at this address with a huge page table entry to minimize
- * its ITLB footprint (as well as at PAGE_OFFSET). The last architected
- * requirement is that user interrupt vectors live at 0xfc000000, so we
- * make that range of memory available to user processes. The remaining
- * regions are sized as shown; the first four addresses use the PL 1
- * values, and after that, we show "typical" values, since the actual
- * addresses depend on kernel #defines.
- *
- * MEM_HV_START 0xfe000000
- * MEM_SV_START (kernel code) 0xfd000000
- * MEM_USER_INTRPT (user vector) 0xfc000000
- * FIX_KMAP_xxx 0xfa000000 (via NR_CPUS * KM_TYPE_NR)
- * PKMAP_BASE 0xf9000000 (via LAST_PKMAP)
- * VMALLOC_START 0xf7000000 (via VMALLOC_RESERVE)
- * mapped LOWMEM 0xc0000000
- */
-
-#define MEM_USER_INTRPT _AC(0xfc000000, UL)
-#define MEM_SV_START _AC(0xfd000000, UL)
-#define MEM_HV_START _AC(0xfe000000, UL)
-
-#define INTRPT_SIZE 0x4000
-
-/* Tolerate page size larger than the architecture interrupt region size. */
-#if PAGE_SIZE > INTRPT_SIZE
-#undef INTRPT_SIZE
-#define INTRPT_SIZE PAGE_SIZE
-#endif
-
-#define KERNEL_HIGH_VADDR MEM_USER_INTRPT
-#define FIXADDR_TOP (KERNEL_HIGH_VADDR - PAGE_SIZE)
-
-#define PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL)
-
-/* On 32-bit architectures we mix kernel modules in with other vmaps. */
-#define MEM_MODULE_START VMALLOC_START
-#define MEM_MODULE_END VMALLOC_END
-
-#endif /* __tilegx__ */
-
-#if !defined(__ASSEMBLY__) && !defined(VDSO_BUILD)
-
-#ifdef CONFIG_HIGHMEM
-
-/* Map kernel virtual addresses to page frames, in HPAGE_SIZE chunks. */
-extern unsigned long pbase_map[];
-extern void *vbase_map[];
-
-static inline unsigned long kaddr_to_pfn(const volatile void *_kaddr)
-{
- unsigned long kaddr = (unsigned long)_kaddr;
- return pbase_map[kaddr >> HPAGE_SHIFT] +
- ((kaddr & (HPAGE_SIZE - 1)) >> PAGE_SHIFT);
-}
-
-static inline void *pfn_to_kaddr(unsigned long pfn)
-{
- return vbase_map[__pfn_to_highbits(pfn)] + (pfn << PAGE_SHIFT);
-}
-
-static inline phys_addr_t virt_to_phys(const volatile void *kaddr)
-{
- unsigned long pfn = kaddr_to_pfn(kaddr);
- return ((phys_addr_t)pfn << PAGE_SHIFT) +
- ((unsigned long)kaddr & (PAGE_SIZE-1));
-}
-
-static inline void *phys_to_virt(phys_addr_t paddr)
-{
- return pfn_to_kaddr(paddr >> PAGE_SHIFT) + (paddr & (PAGE_SIZE-1));
-}
-
-/* With HIGHMEM, we pack PAGE_OFFSET through high_memory with all valid VAs. */
-static inline int virt_addr_valid(const volatile void *kaddr)
-{
- extern void *high_memory; /* copied from <linux/mm.h> */
- return ((unsigned long)kaddr >= PAGE_OFFSET && kaddr < high_memory);
-}
-
-#else /* !CONFIG_HIGHMEM */
-
-static inline unsigned long kaddr_to_pfn(const volatile void *kaddr)
-{
- return ((unsigned long)kaddr - PAGE_OFFSET) >> PAGE_SHIFT;
-}
-
-static inline void *pfn_to_kaddr(unsigned long pfn)
-{
- return (void *)((pfn << PAGE_SHIFT) + PAGE_OFFSET);
-}
-
-static inline phys_addr_t virt_to_phys(const volatile void *kaddr)
-{
- return (phys_addr_t)((unsigned long)kaddr - PAGE_OFFSET);
-}
-
-static inline void *phys_to_virt(phys_addr_t paddr)
-{
- return (void *)((unsigned long)paddr + PAGE_OFFSET);
-}
-
-/* Check that the given address is within some mapped range of PAs. */
-#define virt_addr_valid(kaddr) pfn_valid(kaddr_to_pfn(kaddr))
-
-#endif /* !CONFIG_HIGHMEM */
-
-/* All callers are not consistent in how they call these functions. */
-#define __pa(kaddr) virt_to_phys((void *)(unsigned long)(kaddr))
-#define __va(paddr) phys_to_virt((phys_addr_t)(paddr))
-
-extern int devmem_is_allowed(unsigned long pagenr);
-
-#ifdef CONFIG_FLATMEM
-static inline int pfn_valid(unsigned long pfn)
-{
- return pfn < max_mapnr;
-}
-#endif
-
-/* Provide as macros since these require some other headers included. */
-#define page_to_pa(page) ((phys_addr_t)(page_to_pfn(page)) << PAGE_SHIFT)
-#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn((void *)(kaddr)))
-#define page_to_virt(page) pfn_to_kaddr(page_to_pfn(page))
-
-/*
- * The kernel text is mapped at MEM_SV_START as read-only. To allow
- * modifying kernel text, it is also mapped at PAGE_OFFSET as read-write.
- * This macro converts a kernel address to its writable kernel text mapping,
- * which is used to modify the text code on a running kernel by kgdb,
- * ftrace, kprobe, jump label, etc.
- */
-#define ktext_writable_addr(kaddr) \
- ((unsigned long)(kaddr) - MEM_SV_START + PAGE_OFFSET)
-
-struct mm_struct;
-extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
-extern pte_t *virt_to_kpte(unsigned long kaddr);
-
-#endif /* !__ASSEMBLY__ */
-
-#define VM_DATA_DEFAULT_FLAGS \
- (VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-
-#endif /* _ASM_TILE_PAGE_H */
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
deleted file mode 100644
index fe3de505b024..000000000000
--- a/arch/tile/include/asm/pci.h
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_PCI_H
-#define _ASM_TILE_PCI_H
-
-#include <linux/dma-mapping.h>
-#include <linux/pci.h>
-#include <asm-generic/pci_iomap.h>
-
-#ifndef __tilegx__
-
-/*
- * Structure of a PCI controller (host bridge)
- */
-struct pci_controller {
- int index; /* PCI domain number */
- struct pci_bus *root_bus;
-
- int last_busno;
-
- int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
- int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
-
- struct pci_ops *ops;
-
- int irq_base; /* Base IRQ from the Hypervisor */
- int plx_gen1; /* flag for PLX Gen 1 configuration */
-
- /* Address ranges that are routed to this controller/bridge. */
- struct resource mem_resources[3];
-};
-
-/*
- * This flag tells if the platform is TILEmpower that needs
- * special configuration for the PLX switch chip.
- */
-extern int tile_plx_gen1;
-
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
-
-#define TILE_NUM_PCIE 2
-
-/*
- * The hypervisor maps the entirety of CPA-space as bus addresses, so
- * bus addresses are physical addresses. The networking and block
- * device layers use this boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS 1
-
-/* generic pci stuff */
-#include <asm-generic/pci.h>
-
-#else
-
-#include <asm/page.h>
-#include <gxio/trio.h>
-
-/**
- * We reserve the hugepage-size address range at the top of the 64-bit address
- * space to serve as the PCI window, emulating the BAR0 space of an endpoint
- * device. This window is used by the chip-to-chip applications running on
- * the RC node. The reason for carving out this window is that Mem-Maps that
- * back up this window will not overlap with those that map the real physical
- * memory.
- */
-#define PCIE_HOST_BAR0_SIZE HPAGE_SIZE
-#define PCIE_HOST_BAR0_START HPAGE_MASK
-
-/**
- * The first PAGE_SIZE of the above "BAR" window is mapped to the
- * gxpci_host_regs structure.
- */
-#define PCIE_HOST_REGS_SIZE PAGE_SIZE
-
-/*
- * This is the PCI address where the Mem-Map interrupt regions start.
- * We use the 2nd to the last huge page of the 64-bit address space.
- * The last huge page is used for the rootcomplex "bar", for C2C purpose.
- */
-#define MEM_MAP_INTR_REGIONS_BASE (HPAGE_MASK - HPAGE_SIZE)
-
-/*
- * Each Mem-Map interrupt region occupies 4KB.
- */
-#define MEM_MAP_INTR_REGION_SIZE (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT)
-
-/*
- * Allocate the PCI BAR window right below 4GB.
- */
-#define TILE_PCI_BAR_WINDOW_TOP (1ULL << 32)
-
-/*
- * Allocate 1GB for the PCI BAR window.
- */
-#define TILE_PCI_BAR_WINDOW_SIZE (1 << 30)
-
-/*
- * This is the highest bus address targeting the host memory that
- * can be generated by legacy PCI devices with 32-bit or less
- * DMA capability, dictated by the BAR window size and location.
- */
-#define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \
- (TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1)
-
-/*
- * We shift the PCI bus range for all the physical memory up by the whole PA
- * range. The corresponding CPA of an incoming PCI request will be the PCI
- * address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies
- * that the 64-bit capable devices will be given DMA addresses as
- * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
- * devices, we create a separate map region that handles the low
- * 4GB.
- *
- * This design lets us avoid the "PCI hole" problem where the host bridge
- * won't pass DMA traffic with target addresses that happen to fall within the
- * BAR space. This enables us to use all the physical memory for DMA, instead
- * of wasting the same amount of physical memory as the BAR window size.
- */
-#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH())
-
-/*
- * Start of the PCI memory resource, which starts at the end of the
- * maximum system physical RAM address.
- */
-#define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH())
-
-/*
- * Structure of a PCI controller (host bridge) on Gx.
- */
-struct pci_controller {
-
- /* Pointer back to the TRIO that this PCIe port is connected to. */
- gxio_trio_context_t *trio;
- int mac; /* PCIe mac index on the TRIO shim */
- int trio_index; /* Index of TRIO shim that contains the MAC. */
-
- int pio_mem_index; /* PIO region index for memory access */
-
-#ifdef CONFIG_TILE_PCI_IO
- int pio_io_index; /* PIO region index for I/O space access */
-#endif
-
- /*
- * Mem-Map regions for all the memory controllers so that Linux can
- * map all of its physical memory space to the PCI bus.
- */
- int mem_maps[MAX_NUMNODES];
-
- int index; /* PCI domain number */
- struct pci_bus *root_bus;
-
- /* PCI I/O space resource for this controller. */
- struct resource io_space;
- char io_space_name[32];
-
- /* PCI memory space resource for this controller. */
- struct resource mem_space;
- char mem_space_name[32];
-
- uint64_t mem_offset; /* cpu->bus memory mapping offset. */
-
- int first_busno;
-
- struct pci_ops *ops;
-
- /* Table that maps the INTx numbers to Linux irq numbers. */
- int irq_intx_table[4];
-};
-
-extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
-extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
-extern int num_trio_shims;
-
-extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
-
-/*
- * The PCI address space does not equal the physical memory address
- * space (we have an IOMMU). The IDE and SCSI device layers use this
- * boolean for bounce buffer decisions.
- */
-#define PCI_DMA_BUS_IS_PHYS 0
-
-#endif /* __tilegx__ */
-
-int __init tile_pci_init(void);
-int __init pcibios_init(void);
-
-void pcibios_fixup_bus(struct pci_bus *bus);
-
-#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
-
-/*
- * This decides whether to display the domain number in /proc.
- */
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
- return 1;
-}
-
-/*
- * pcibios_assign_all_busses() tells whether or not the bus numbers
- * should be reassigned, in case the BIOS didn't do it correctly, or
- * in case we don't have a BIOS and we want to let Linux do it.
- */
-static inline int pcibios_assign_all_busses(void)
-{
- return 1;
-}
-
-#define PCIBIOS_MIN_MEM 0
-/* Minimum PCI I/O address, starting at the page boundary. */
-#define PCIBIOS_MIN_IO PAGE_SIZE
-
-/* Use any cpu for PCI. */
-#define cpumask_of_pcibus(bus) cpu_online_mask
-
-#endif /* _ASM_TILE_PCI_H */
diff --git a/arch/tile/include/asm/percpu.h b/arch/tile/include/asm/percpu.h
deleted file mode 100644
index 4f7ae39fa202..000000000000
--- a/arch/tile/include/asm/percpu.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_PERCPU_H
-#define _ASM_TILE_PERCPU_H
-
-register unsigned long my_cpu_offset_reg asm("tp");
-
-#ifdef CONFIG_PREEMPT
-/*
- * For full preemption, we can't just use the register variable
- * directly, since we need barrier() to hazard against it, causing the
- * compiler to reload anything computed from a previous "tp" value.
- * But we also don't want to use volatile asm, since we'd like the
- * compiler to be able to cache the value across multiple percpu reads.
- * So we use a fake stack read as a hazard against barrier().
- * The 'U' constraint is like 'm' but disallows postincrement.
- */
-static inline unsigned long __my_cpu_offset(void)
-{
- unsigned long tp;
- register unsigned long *sp asm("sp");
- asm("move %0, tp" : "=r" (tp) : "U" (*sp));
- return tp;
-}
-#define __my_cpu_offset __my_cpu_offset()
-#else
-/*
- * We don't need to hazard against barrier() since "tp" doesn't ever
- * change with PREEMPT_NONE, and with PREEMPT_VOLUNTARY it only
- * changes at function call points, at which we are already re-reading
- * the value of "tp" due to "my_cpu_offset_reg" being a global variable.
- */
-#define __my_cpu_offset my_cpu_offset_reg
-#endif
-
-#define set_my_cpu_offset(tp) (my_cpu_offset_reg = (tp))
-
-#include <asm-generic/percpu.h>
-
-#endif /* _ASM_TILE_PERCPU_H */
diff --git a/arch/tile/include/asm/perf_event.h b/arch/tile/include/asm/perf_event.h
deleted file mode 100644
index 59c5b164e5b6..000000000000
--- a/arch/tile/include/asm/perf_event.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2014 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_PERF_EVENT_H
-#define _ASM_TILE_PERF_EVENT_H
-
-#include <linux/percpu.h>
-DECLARE_PER_CPU(u64, perf_irqs);
-
-unsigned long handle_syscall_link_address(void);
-#endif /* _ASM_TILE_PERF_EVENT_H */
diff --git a/arch/tile/include/asm/pgalloc.h b/arch/tile/include/asm/pgalloc.h
deleted file mode 100644
index 1b902508b664..000000000000
--- a/arch/tile/include/asm/pgalloc.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_PGALLOC_H
-#define _ASM_TILE_PGALLOC_H
-
-#include <linux/threads.h>
-#include <linux/mm.h>
-#include <linux/mmzone.h>
-#include <asm/fixmap.h>
-#include <asm/page.h>
-#include <hv/hypervisor.h>
-
-/* Bits for the size of the second-level page table. */
-#define L2_KERNEL_PGTABLE_SHIFT _HV_LOG2_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
-
-/* How big is a kernel L2 page table? */
-#define L2_KERNEL_PGTABLE_SIZE (1UL << L2_KERNEL_PGTABLE_SHIFT)
-
-/* We currently allocate user L2 page tables by page (unlike kernel L2s). */
-#if L2_KERNEL_PGTABLE_SHIFT < PAGE_SHIFT
-#define L2_USER_PGTABLE_SHIFT PAGE_SHIFT
-#else
-#define L2_USER_PGTABLE_SHIFT L2_KERNEL_PGTABLE_SHIFT
-#endif
-
-/* How many pages do we need, as an "order", for a user L2 page table? */
-#define L2_USER_PGTABLE_ORDER (L2_USER_PGTABLE_SHIFT - PAGE_SHIFT)
-
-static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
-{
-#ifdef CONFIG_64BIT
- set_pte(pmdp, pmd);
-#else
- set_pte(&pmdp->pud.pgd, pmd.pud.pgd);
-#endif
-}
-
-static inline void pmd_populate_kernel(struct mm_struct *mm,
- pmd_t *pmd, pte_t *ptep)
-{
- set_pmd(pmd, ptfn_pmd(HV_CPA_TO_PTFN(__pa(ptep)),
- __pgprot(_PAGE_PRESENT)));
-}
-
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- pgtable_t page)
-{
- set_pmd(pmd, ptfn_pmd(HV_CPA_TO_PTFN(PFN_PHYS(page_to_pfn(page))),
- __pgprot(_PAGE_PRESENT)));
-}
-
-/*
- * Allocate and free page tables.
- */
-
-extern pgd_t *pgd_alloc(struct mm_struct *mm);
-extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
-
-extern pgtable_t pgtable_alloc_one(struct mm_struct *mm, unsigned long address,
- int order);
-extern void pgtable_free(struct mm_struct *mm, struct page *pte, int order);
-
-static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
-{
- return pgtable_alloc_one(mm, address, L2_USER_PGTABLE_ORDER);
-}
-
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
-{
- pgtable_free(mm, pte, L2_USER_PGTABLE_ORDER);
-}
-
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-static inline pte_t *
-pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- return pfn_to_kaddr(page_to_pfn(pte_alloc_one(mm, address)));
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
- BUG_ON((unsigned long)pte & (PAGE_SIZE-1));
- pte_free(mm, virt_to_page(pte));
-}
-
-extern void __pgtable_free_tlb(struct mmu_gather *tlb, struct page *pte,
- unsigned long address, int order);
-static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte,
- unsigned long address)
-{
- __pgtable_free_tlb(tlb, pte, address, L2_USER_PGTABLE_ORDER);
-}
-
-#define check_pgt_cache() do { } while (0)
-
-/*
- * Get the small-page pte_t lowmem entry for a given pfn.
- * This may or may not be in use, depending on whether the initial
- * huge-page entry for the page has already been shattered.
- */
-pte_t *get_prealloc_pte(unsigned long pfn);
-
-/* During init, we can shatter kernel huge pages if needed. */
-void shatter_pmd(pmd_t *pmd);
-
-/* After init, a more complex technique is required. */
-void shatter_huge_page(unsigned long addr);
-
-#ifdef __tilegx__
-
-#define pud_populate(mm, pud, pmd) \
- pmd_populate_kernel((mm), (pmd_t *)(pud), (pte_t *)(pmd))
-
-/* Bits for the size of the L1 (intermediate) page table. */
-#define L1_KERNEL_PGTABLE_SHIFT _HV_LOG2_L1_SIZE(HPAGE_SHIFT)
-
-/* How big is a kernel L2 page table? */
-#define L1_KERNEL_PGTABLE_SIZE (1UL << L1_KERNEL_PGTABLE_SHIFT)
-
-/* We currently allocate L1 page tables by page. */
-#if L1_KERNEL_PGTABLE_SHIFT < PAGE_SHIFT
-#define L1_USER_PGTABLE_SHIFT PAGE_SHIFT
-#else
-#define L1_USER_PGTABLE_SHIFT L1_KERNEL_PGTABLE_SHIFT
-#endif
-
-/* How many pages do we need, as an "order", for an L1 page table? */
-#define L1_USER_PGTABLE_ORDER (L1_USER_PGTABLE_SHIFT - PAGE_SHIFT)
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *p = pgtable_alloc_one(mm, address, L1_USER_PGTABLE_ORDER);
- return (pmd_t *)page_to_virt(p);
-}
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmdp)
-{
- pgtable_free(mm, virt_to_page(pmdp), L1_USER_PGTABLE_ORDER);
-}
-
-static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
- unsigned long address)
-{
- __pgtable_free_tlb(tlb, virt_to_page(pmdp), address,
- L1_USER_PGTABLE_ORDER);
-}
-
-#endif /* __tilegx__ */
-
-#endif /* _ASM_TILE_PGALLOC_H */
diff --git a/arch/tile/include/asm/pgtable.h b/arch/tile/include/asm/pgtable.h
deleted file mode 100644
index adfa21b18488..000000000000
--- a/arch/tile/include/asm/pgtable.h
+++ /dev/null
@@ -1,518 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * This file contains the functions and defines necessary to modify and use
- * the TILE page table tree.
- */
-
-#ifndef _ASM_TILE_PGTABLE_H
-#define _ASM_TILE_PGTABLE_H
-
-#include <hv/hypervisor.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/bitops.h>
-#include <linux/threads.h>
-#include <linux/slab.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/pfn.h>
-#include <asm/processor.h>
-#include <asm/fixmap.h>
-#include <asm/page.h>
-
-struct mm_struct;
-struct vm_area_struct;
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-
-extern pgd_t swapper_pg_dir[];
-extern pgprot_t swapper_pgprot;
-extern struct kmem_cache *pgd_cache;
-extern spinlock_t pgd_lock;
-extern struct list_head pgd_list;
-
-/*
- * The very last slots in the pgd_t are for addresses unusable by Linux
- * (pgd_addr_invalid() returns true). So we use them for the list structure.
- * The x86 code we are modelled on uses the page->private/index fields
- * (older 2.6 kernels) or the lru list (newer 2.6 kernels), but since
- * our pgds are so much smaller than a page, it seems a waste to
- * spend a whole page on each pgd.
- */
-#define PGD_LIST_OFFSET \
- ((PTRS_PER_PGD * sizeof(pgd_t)) - sizeof(struct list_head))
-#define pgd_to_list(pgd) \
- ((struct list_head *)((char *)(pgd) + PGD_LIST_OFFSET))
-#define list_to_pgd(list) \
- ((pgd_t *)((char *)(list) - PGD_LIST_OFFSET))
-
-extern void pgtable_cache_init(void);
-extern void paging_init(void);
-extern void set_page_homes(void);
-
-#define FIRST_USER_ADDRESS 0UL
-
-#define _PAGE_PRESENT HV_PTE_PRESENT
-#define _PAGE_HUGE_PAGE HV_PTE_PAGE
-#define _PAGE_SUPER_PAGE HV_PTE_SUPER
-#define _PAGE_READABLE HV_PTE_READABLE
-#define _PAGE_WRITABLE HV_PTE_WRITABLE
-#define _PAGE_EXECUTABLE HV_PTE_EXECUTABLE
-#define _PAGE_ACCESSED HV_PTE_ACCESSED
-#define _PAGE_DIRTY HV_PTE_DIRTY
-#define _PAGE_GLOBAL HV_PTE_GLOBAL
-#define _PAGE_USER HV_PTE_USER
-
-/*
- * All the "standard" bits. Cache-control bits are managed elsewhere.
- * This is used to test for valid level-2 page table pointers by checking
- * all the bits, and to mask away the cache control bits for mprotect.
- */
-#define _PAGE_ALL (\
- _PAGE_PRESENT | \
- _PAGE_HUGE_PAGE | \
- _PAGE_SUPER_PAGE | \
- _PAGE_READABLE | \
- _PAGE_WRITABLE | \
- _PAGE_EXECUTABLE | \
- _PAGE_ACCESSED | \
- _PAGE_DIRTY | \
- _PAGE_GLOBAL | \
- _PAGE_USER \
-)
-
-#define PAGE_NONE \
- __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-#define PAGE_SHARED \
- __pgprot(_PAGE_PRESENT | _PAGE_READABLE | _PAGE_WRITABLE | \
- _PAGE_USER | _PAGE_ACCESSED)
-
-#define PAGE_SHARED_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_READABLE | _PAGE_WRITABLE | \
- _PAGE_EXECUTABLE | _PAGE_USER | _PAGE_ACCESSED)
-#define PAGE_COPY_NOEXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_READABLE)
-#define PAGE_COPY_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | \
- _PAGE_READABLE | _PAGE_EXECUTABLE)
-#define PAGE_COPY \
- PAGE_COPY_NOEXEC
-#define PAGE_READONLY \
- __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_READABLE)
-#define PAGE_READONLY_EXEC \
- __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | \
- _PAGE_READABLE | _PAGE_EXECUTABLE)
-
-#define _PAGE_KERNEL_RO \
- (_PAGE_PRESENT | _PAGE_GLOBAL | _PAGE_READABLE | _PAGE_ACCESSED)
-#define _PAGE_KERNEL \
- (_PAGE_KERNEL_RO | _PAGE_WRITABLE | _PAGE_DIRTY)
-#define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXECUTABLE)
-
-#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
-#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
-#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
-
-#define page_to_kpgprot(p) PAGE_KERNEL
-
-/*
- * We could tighten these up, but for now writable or executable
- * implies readable.
- */
-#define __P000 PAGE_NONE
-#define __P001 PAGE_READONLY
-#define __P010 PAGE_COPY /* this is write-only, which we won't support */
-#define __P011 PAGE_COPY
-#define __P100 PAGE_READONLY_EXEC
-#define __P101 PAGE_READONLY_EXEC
-#define __P110 PAGE_COPY_EXEC
-#define __P111 PAGE_COPY_EXEC
-
-#define __S000 PAGE_NONE
-#define __S001 PAGE_READONLY
-#define __S010 PAGE_SHARED
-#define __S011 PAGE_SHARED
-#define __S100 PAGE_READONLY_EXEC
-#define __S101 PAGE_READONLY_EXEC
-#define __S110 PAGE_SHARED_EXEC
-#define __S111 PAGE_SHARED_EXEC
-
-/*
- * All the normal _PAGE_ALL bits are ignored for PMDs, except PAGE_PRESENT
- * and PAGE_HUGE_PAGE, which must be one and zero, respectively.
- * We set the ignored bits to zero.
- */
-#define _PAGE_TABLE _PAGE_PRESENT
-
-/* Inherit the caching flags from the old protection bits. */
-#define pgprot_modify(oldprot, newprot) \
- (pgprot_t) { ((oldprot).val & ~_PAGE_ALL) | (newprot).val }
-
-/* Just setting the PFN to zero suffices. */
-#define pte_pgprot(x) hv_pte_set_pa((x), 0)
-
-/*
- * For PTEs and PDEs, we must clear the Present bit first when
- * clearing a page table entry, so clear the bottom half first and
- * enforce ordering with a barrier.
- */
-static inline void __pte_clear(pte_t *ptep)
-{
-#ifdef __tilegx__
- ptep->val = 0;
-#else
- u32 *tmp = (u32 *)ptep;
- tmp[0] = 0;
- barrier();
- tmp[1] = 0;
-#endif
-}
-#define pte_clear(mm, addr, ptep) __pte_clear(ptep)
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-#define pte_present hv_pte_get_present
-#define pte_mknotpresent hv_pte_clear_present
-#define pte_user hv_pte_get_user
-#define pte_read hv_pte_get_readable
-#define pte_dirty hv_pte_get_dirty
-#define pte_young hv_pte_get_accessed
-#define pte_write hv_pte_get_writable
-#define pte_exec hv_pte_get_executable
-#define pte_huge hv_pte_get_page
-#define pte_super hv_pte_get_super
-#define pte_rdprotect hv_pte_clear_readable
-#define pte_exprotect hv_pte_clear_executable
-#define pte_mkclean hv_pte_clear_dirty
-#define pte_mkold hv_pte_clear_accessed
-#define pte_wrprotect hv_pte_clear_writable
-#define pte_mksmall hv_pte_clear_page
-#define pte_mkread hv_pte_set_readable
-#define pte_mkexec hv_pte_set_executable
-#define pte_mkdirty hv_pte_set_dirty
-#define pte_mkyoung hv_pte_set_accessed
-#define pte_mkwrite hv_pte_set_writable
-#define pte_mkhuge hv_pte_set_page
-#define pte_mksuper hv_pte_set_super
-
-#define pte_special(pte) 0
-#define pte_mkspecial(pte) (pte)
-
-/*
- * Use some spare bits in the PTE for user-caching tags.
- */
-#define pte_set_forcecache hv_pte_set_client0
-#define pte_get_forcecache hv_pte_get_client0
-#define pte_clear_forcecache hv_pte_clear_client0
-#define pte_set_anyhome hv_pte_set_client1
-#define pte_get_anyhome hv_pte_get_client1
-#define pte_clear_anyhome hv_pte_clear_client1
-
-/*
- * A migrating PTE has PAGE_PRESENT clear but all the other bits preserved.
- */
-#define pte_migrating hv_pte_get_migrating
-#define pte_mkmigrate(x) hv_pte_set_migrating(hv_pte_clear_present(x))
-#define pte_donemigrate(x) hv_pte_set_present(hv_pte_clear_migrating(x))
-
-#define pte_ERROR(e) \
- pr_err("%s:%d: bad pte 0x%016llx\n", __FILE__, __LINE__, pte_val(e))
-#define pgd_ERROR(e) \
- pr_err("%s:%d: bad pgd 0x%016llx\n", __FILE__, __LINE__, pgd_val(e))
-
-/* Return PA and protection info for a given kernel VA. */
-int va_to_cpa_and_pte(void *va, phys_addr_t *cpa, pte_t *pte);
-
-/*
- * __set_pte() ensures we write the 64-bit PTE with 32-bit words in
- * the right order on 32-bit platforms and also allows us to write
- * hooks to check valid PTEs, etc., if we want.
- */
-void __set_pte(pte_t *ptep, pte_t pte);
-
-/*
- * set_pte() sets the given PTE and also sanity-checks the
- * requested PTE against the page homecaching. Unspecified parts
- * of the PTE are filled in when it is written to memory, i.e. all
- * caching attributes if "!forcecache", or the home cpu if "anyhome".
- */
-extern void set_pte(pte_t *ptep, pte_t pte);
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-#define set_pte_atomic(pteptr, pteval) set_pte(pteptr, pteval)
-
-#define pte_page(x) pfn_to_page(pte_pfn(x))
-
-static inline int pte_none(pte_t pte)
-{
- return !pte.val;
-}
-
-static inline unsigned long pte_pfn(pte_t pte)
-{
- return PFN_DOWN(hv_pte_get_pa(pte));
-}
-
-/* Set or get the remote cache cpu in a pgprot with remote caching. */
-extern pgprot_t set_remote_cache_cpu(pgprot_t prot, int cpu);
-extern int get_remote_cache_cpu(pgprot_t prot);
-
-static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
-{
- return hv_pte_set_pa(prot, PFN_PHYS(pfn));
-}
-
-/* Support for priority mappings. */
-extern void start_mm_caching(struct mm_struct *mm);
-extern void check_mm_caching(struct mm_struct *prev, struct mm_struct *next);
-
-/*
- * Encode and de-code a swap entry (see <linux/swapops.h>).
- * We put the swap file type+offset in the 32 high bits;
- * I believe we can just leave the low bits clear.
- */
-#define __swp_type(swp) ((swp).val & 0x1f)
-#define __swp_offset(swp) ((swp).val >> 5)
-#define __swp_entry(type, off) ((swp_entry_t) { (type) | ((off) << 5) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).val >> 32 })
-#define __swp_entry_to_pte(swp) ((pte_t) { (((long long) ((swp).val)) << 32) })
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-
-#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
-
-/*
- * If we are doing an mprotect(), just accept the new vma->vm_page_prot
- * value and combine it with the PFN from the old PTE to get a new PTE.
- */
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
- return pfn_pte(pte_pfn(pte), newprot);
-}
-
-/*
- * The pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
- *
- * This macro returns the index of the entry in the pgd page which would
- * control the given virtual address.
- */
-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
-
-/*
- * pgd_offset() returns a (pgd_t *)
- * pgd_index() is used get the offset into the pgd page's array of pgd_t's.
- */
-#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
-
-/*
- * A shortcut which implies the use of the kernel's pgd, instead
- * of a process's.
- */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
-#define pte_unmap(pte) do { } while (0)
-
-/* Clear a non-executable kernel PTE and flush it from the TLB. */
-#define kpte_clear_flush(ptep, vaddr) \
-do { \
- pte_clear(&init_mm, (vaddr), (ptep)); \
- local_flush_tlb_page(FLUSH_NONEXEC, (vaddr), PAGE_SIZE); \
-} while (0)
-
-/*
- * The kernel page tables contain what we need, and we flush when we
- * change specific page table entries.
- */
-#define update_mmu_cache(vma, address, pte) do { } while (0)
-
-#ifdef CONFIG_FLATMEM
-#define kern_addr_valid(addr) (1)
-#endif /* CONFIG_FLATMEM */
-
-extern void vmalloc_sync_all(void);
-
-#endif /* !__ASSEMBLY__ */
-
-#ifdef __tilegx__
-#include <asm/pgtable_64.h>
-#else
-#include <asm/pgtable_32.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-static inline int pmd_none(pmd_t pmd)
-{
- /*
- * Only check low word on 32-bit platforms, since it might be
- * out of sync with upper half.
- */
- return (unsigned long)pmd_val(pmd) == 0;
-}
-
-static inline int pmd_present(pmd_t pmd)
-{
- return pmd_val(pmd) & _PAGE_PRESENT;
-}
-
-static inline int pmd_bad(pmd_t pmd)
-{
- return ((pmd_val(pmd) & _PAGE_ALL) != _PAGE_TABLE);
-}
-
-static inline unsigned long pages_to_mb(unsigned long npg)
-{
- return npg >> (20 - PAGE_SHIFT);
-}
-
-/*
- * The pmd can be thought of an array like this: pmd_t[PTRS_PER_PMD]
- *
- * This function returns the index of the entry in the pmd which would
- * control the given virtual address.
- */
-static inline unsigned long pmd_index(unsigned long address)
-{
- return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
-}
-
-#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
-static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
- unsigned long address,
- pmd_t *pmdp)
-{
- return ptep_test_and_clear_young(vma, address, pmdp_ptep(pmdp));
-}
-
-#define __HAVE_ARCH_PMDP_SET_WRPROTECT
-static inline void pmdp_set_wrprotect(struct mm_struct *mm,
- unsigned long address, pmd_t *pmdp)
-{
- ptep_set_wrprotect(mm, address, pmdp_ptep(pmdp));
-}
-
-
-#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
-static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
- unsigned long address,
- pmd_t *pmdp)
-{
- return pte_pmd(ptep_get_and_clear(mm, address, pmdp_ptep(pmdp)));
-}
-
-static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
-{
- set_pte(pmdp_ptep(pmdp), pmd_pte(pmdval));
-}
-
-#define set_pmd_at(mm, addr, pmdp, pmdval) __set_pmd(pmdp, pmdval)
-
-/* Create a pmd from a PTFN. */
-static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
-{
- return pte_pmd(hv_pte_set_ptfn(prot, ptfn));
-}
-
-/* Return the page-table frame number (ptfn) that a pmd_t points at. */
-#define pmd_ptfn(pmd) hv_pte_get_ptfn(pmd_pte(pmd))
-
-/*
- * A given kernel pmd_t maps to a specific virtual address (either a
- * kernel huge page or a kernel pte_t table). Since kernel pte_t
- * tables can be aligned at sub-page granularity, this function can
- * return non-page-aligned pointers, despite its name.
- */
-static inline unsigned long pmd_page_vaddr(pmd_t pmd)
-{
- phys_addr_t pa =
- (phys_addr_t)pmd_ptfn(pmd) << HV_LOG2_PAGE_TABLE_ALIGN;
- return (unsigned long)__va(pa);
-}
-
-/*
- * A pmd_t points to the base of a huge page or to a pte_t array.
- * If a pte_t array, since we can have multiple per page, we don't
- * have a one-to-one mapping of pmd_t's to pages. However, this is
- * OK for pte_lockptr(), since we just end up with potentially one
- * lock being used for several pte_t arrays.
- */
-#define pmd_page(pmd) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pmd_ptfn(pmd))))
-
-static inline void pmd_clear(pmd_t *pmdp)
-{
- __pte_clear(pmdp_ptep(pmdp));
-}
-
-#define pmd_mknotpresent(pmd) pte_pmd(pte_mknotpresent(pmd_pte(pmd)))
-#define pmd_young(pmd) pte_young(pmd_pte(pmd))
-#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
-#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
-#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
-#define pmd_write(pmd) pte_write(pmd_pte(pmd))
-#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
-#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
-#define pmd_huge_page(pmd) pte_huge(pmd_pte(pmd))
-#define pmd_mkhuge(pmd) pte_pmd(pte_mkhuge(pmd_pte(pmd)))
-
-#define pfn_pmd(pfn, pgprot) pte_pmd(pfn_pte((pfn), (pgprot)))
-#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
-#define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
-
-static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
-{
- return pfn_pmd(pmd_pfn(pmd), newprot);
-}
-
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
-#define pmd_trans_huge pmd_huge_page
-#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
-
-/*
- * The pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
- *
- * This macro returns the index of the entry in the pte page which would
- * control the given virtual address.
- */
-static inline unsigned long pte_index(unsigned long address)
-{
- return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
-}
-
-static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address)
-{
- return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address);
-}
-
-#include <asm-generic/pgtable.h>
-
-/* Support /proc/NN/pgtable API. */
-struct seq_file;
-int arch_proc_pgtable_show(struct seq_file *m, struct mm_struct *mm,
- unsigned long vaddr, unsigned long pagesize,
- pte_t *ptep, void **datap);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_TILE_PGTABLE_H */
diff --git a/arch/tile/include/asm/pgtable_32.h b/arch/tile/include/asm/pgtable_32.h
deleted file mode 100644
index 5f8c615cb5e9..000000000000
--- a/arch/tile/include/asm/pgtable_32.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _ASM_TILE_PGTABLE_32_H
-#define _ASM_TILE_PGTABLE_32_H
-
-/*
- * The level-1 index is defined by the huge page size. A PGD is composed
- * of PTRS_PER_PGD pgd_t's and is the top level of the page table.
- */
-#define PGDIR_SHIFT HPAGE_SHIFT
-#define PGDIR_SIZE HPAGE_SIZE
-#define PGDIR_MASK (~(PGDIR_SIZE-1))
-#define PTRS_PER_PGD _HV_L1_ENTRIES(HPAGE_SHIFT)
-#define PGD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT)
-#define SIZEOF_PGD _HV_L1_SIZE(HPAGE_SHIFT)
-
-/*
- * The level-2 index is defined by the difference between the huge
- * page size and the normal page size. A PTE is composed of
- * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
- * Note that the hypervisor docs use PTE for what we call pte_t, so
- * this nomenclature is somewhat confusing.
- */
-#define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
-#define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
-#define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
-
-#ifndef __ASSEMBLY__
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- *
- * HOWEVER, if we are using an allocation scheme with slop after the
- * end of the page table (e.g. where our L2 page tables are 2KB but
- * our pages are 64KB and we are allocating via the page allocator)
- * we can't extend it easily.
- */
-#define LAST_PKMAP PTRS_PER_PTE
-
-#define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE*LAST_PKMAP) & PGDIR_MASK)
-
-#ifdef CONFIG_HIGHMEM
-# define _VMALLOC_END (PKMAP_BASE & ~(HPAGE_SIZE-1))
-#else
-# define _VMALLOC_END (FIXADDR_START & ~(HPAGE_SIZE-1))
-#endif
-
-/*
- * Align the vmalloc area to an L2 page table, and leave a guard page
- * at the beginning and end. The vmalloc code also puts in an internal
- * guard page between each allocation.
- */
-#define VMALLOC_END (_VMALLOC_END - PAGE_SIZE)
-extern unsigned long VMALLOC_RESERVE /* = CONFIG_VMALLOC_RESERVE */;
-#define _VMALLOC_START (_VMALLOC_END - VMALLOC_RESERVE)
-#define VMALLOC_START (_VMALLOC_START + PAGE_SIZE)
-
-/* This is the maximum possible amount of lowmem. */
-#define MAXMEM (_VMALLOC_START - PAGE_OFFSET)
-
-/* We have no pmd or pud since we are strictly a two-level page table */
-#define __ARCH_USE_5LEVEL_HACK
-#include <asm-generic/pgtable-nopmd.h>
-
-static inline int pud_huge_page(pud_t pud) { return 0; }
-
-/* We don't define any pgds for these addresses. */
-static inline int pgd_addr_invalid(unsigned long addr)
-{
- return addr >= MEM_HV_START;
-}
-
-/*
- * Provide versions of these routines that can be used safely when
- * the hypervisor may be asynchronously modifying dirty/accessed bits.
- * ptep_get_and_clear() matches the generic one but we provide it to
- * be parallel with the 64-bit code.
- */
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-
-extern int ptep_test_and_clear_young(struct vm_area_struct *,
- unsigned long addr, pte_t *);
-extern void ptep_set_wrprotect(struct mm_struct *,
- unsigned long addr, pte_t *);
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- pte_t pte = *ptep;
- pte_clear(_mm, addr, ptep);
- return pte;
-}
-
-/*
- * pmds are wrappers around pgds, which are the same as ptes.
- * It's often convenient to "cast" back and forth and use the pte methods,
- * which are the methods supplied by the hypervisor.
- */
-#define pmd_pte(pmd) ((pmd).pud.pgd)
-#define pmdp_ptep(pmdp) (&(pmdp)->pud.pgd)
-#define pte_pmd(pte) ((pmd_t){ { (pte) } })
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_TILE_PGTABLE_32_H */
diff --git a/arch/tile/include/asm/pgtable_64.h b/arch/tile/include/asm/pgtable_64.h
deleted file mode 100644
index 96fe58b45118..000000000000
--- a/arch/tile/include/asm/pgtable_64.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _ASM_TILE_PGTABLE_64_H
-#define _ASM_TILE_PGTABLE_64_H
-
-/* The level-0 page table breaks the address space into 32-bit chunks. */
-#define PGDIR_SHIFT HV_LOG2_L1_SPAN
-#define PGDIR_SIZE HV_L1_SPAN
-#define PGDIR_MASK (~(PGDIR_SIZE-1))
-#define PTRS_PER_PGD HV_L0_ENTRIES
-#define PGD_INDEX(va) HV_L0_INDEX(va)
-#define SIZEOF_PGD HV_L0_SIZE
-
-/*
- * The level-1 index is defined by the huge page size. A PMD is composed
- * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
- */
-#define PMD_SHIFT HPAGE_SHIFT
-#define PMD_SIZE HPAGE_SIZE
-#define PMD_MASK (~(PMD_SIZE-1))
-#define PTRS_PER_PMD _HV_L1_ENTRIES(HPAGE_SHIFT)
-#define PMD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT)
-#define SIZEOF_PMD _HV_L1_SIZE(HPAGE_SHIFT)
-
-/*
- * The level-2 index is defined by the difference between the huge
- * page size and the normal page size. A PTE is composed of
- * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
- * Note that the hypervisor docs use PTE for what we call pte_t, so
- * this nomenclature is somewhat confusing.
- */
-#define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
-#define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
-#define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
-
-/*
- * Align the vmalloc area to an L2 page table. Omit guard pages at
- * the beginning and end for simplicity (particularly in the per-cpu
- * memory allocation code). The vmalloc code puts in an internal
- * guard page between each allocation.
- */
-#define _VMALLOC_END MEM_SV_START
-#define VMALLOC_END _VMALLOC_END
-#define VMALLOC_START _VMALLOC_START
-
-#ifndef __ASSEMBLY__
-
-/* We have no pud since we are a three-level page table. */
-#define __ARCH_USE_5LEVEL_HACK
-#include <asm-generic/pgtable-nopud.h>
-
-/*
- * pmds are the same as pgds and ptes, so converting is a no-op.
- */
-#define pmd_pte(pmd) (pmd)
-#define pmdp_ptep(pmdp) (pmdp)
-#define pte_pmd(pte) (pte)
-
-#define pud_pte(pud) ((pud).pgd)
-
-static inline int pud_none(pud_t pud)
-{
- return pud_val(pud) == 0;
-}
-
-static inline int pud_present(pud_t pud)
-{
- return pud_val(pud) & _PAGE_PRESENT;
-}
-
-static inline int pud_huge_page(pud_t pud)
-{
- return pud_val(pud) & _PAGE_HUGE_PAGE;
-}
-
-#define pmd_ERROR(e) \
- pr_err("%s:%d: bad pmd 0x%016llx\n", __FILE__, __LINE__, pmd_val(e))
-
-static inline void pud_clear(pud_t *pudp)
-{
- __pte_clear(&pudp->pgd);
-}
-
-static inline int pud_bad(pud_t pud)
-{
- return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
-}
-
-/* Return the page-table frame number (ptfn) that a pud_t points at. */
-#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
-
-/* Return the page frame number (pfn) that a pud_t points at. */
-#define pud_pfn(pud) pte_pfn(pud_pte(pud))
-
-/*
- * A given kernel pud_t maps to a kernel pmd_t table at a specific
- * virtual address. Since kernel pmd_t tables can be aligned at
- * sub-page granularity, this macro can return non-page-aligned
- * pointers, despite its name.
- */
-#define pud_page_vaddr(pud) \
- (__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
-
-/*
- * A pud_t points to a pmd_t array. Since we can have multiple per
- * page, we don't have a one-to-one mapping of pud_t's to pages.
- */
-#define pud_page(pud) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pud_ptfn(pud))))
-
-static inline unsigned long pud_index(unsigned long address)
-{
- return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
-}
-
-#define pmd_offset(pud, address) \
- ((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
-
-/* Normalize an address to having the correct high bits set. */
-#define pgd_addr_normalize pgd_addr_normalize
-static inline unsigned long pgd_addr_normalize(unsigned long addr)
-{
- return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
- (CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
-}
-
-/* We don't define any pgds for these addresses. */
-static inline int pgd_addr_invalid(unsigned long addr)
-{
- return addr >= KERNEL_HIGH_VADDR || addr != pgd_addr_normalize(addr);
-}
-
-/*
- * Use atomic instructions to provide atomicity against the hypervisor.
- */
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep)
-{
- return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
- HV_PTE_INDEX_ACCESSED) & 0x1;
-}
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- __insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
-}
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
- return hv_pte(__insn_exch(&ptep->val, 0UL));
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _ASM_TILE_PGTABLE_64_H */
diff --git a/arch/tile/include/asm/pmc.h b/arch/tile/include/asm/pmc.h
deleted file mode 100644
index 7ae3956d9008..000000000000
--- a/arch/tile/include/asm/pmc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2014 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_PMC_H
-#define _ASM_TILE_PMC_H
-
-#include <linux/ptrace.h>
-
-#define TILE_BASE_COUNTERS 2
-
-/* Bitfields below are derived from SPR PERF_COUNT_CTL*/
-#ifndef __tilegx__
-/* PERF_COUNT_CTL on TILEPro */
-#define TILE_CTL_EXCL_USER (1 << 7) /* exclude user level */
-#define TILE_CTL_EXCL_KERNEL (1 << 8) /* exclude kernel level */
-#define TILE_CTL_EXCL_HV (1 << 9) /* exclude hypervisor level */
-
-#define TILE_SEL_MASK 0x7f /* 7 bits for event SEL,
- COUNT_0_SEL */
-#define TILE_PLM_MASK 0x780 /* 4 bits priv level msks,
- COUNT_0_MASK*/
-#define TILE_EVENT_MASK (TILE_SEL_MASK | TILE_PLM_MASK)
-
-#else /* __tilegx__*/
-/* PERF_COUNT_CTL on TILEGx*/
-#define TILE_CTL_EXCL_USER (1 << 10) /* exclude user level */
-#define TILE_CTL_EXCL_KERNEL (1 << 11) /* exclude kernel level */
-#define TILE_CTL_EXCL_HV (1 << 12) /* exclude hypervisor level */
-
-#define TILE_SEL_MASK 0x3f /* 6 bits for event SEL,
- COUNT_0_SEL*/
-#define TILE_BOX_MASK 0x1c0 /* 3 bits box msks,
- COUNT_0_BOX */
-#define TILE_PLM_MASK 0x3c00 /* 4 bits priv level msks,
- COUNT_0_MASK */
-#define TILE_EVENT_MASK (TILE_SEL_MASK | TILE_BOX_MASK | TILE_PLM_MASK)
-#endif /* __tilegx__*/
-
-/* Takes register and fault number. Returns error to disable the interrupt. */
-typedef int (*perf_irq_t)(struct pt_regs *, int);
-
-int userspace_perf_handler(struct pt_regs *regs, int fault);
-
-perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq);
-void release_pmc_hardware(void);
-
-unsigned long pmc_get_overflow(void);
-void pmc_ack_overflow(unsigned long status);
-
-void unmask_pmc_interrupts(void);
-void mask_pmc_interrupts(void);
-
-#endif /* _ASM_TILE_PMC_H */
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
deleted file mode 100644
index f71e5206650b..000000000000
--- a/arch/tile/include/asm/processor.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_PROCESSOR_H
-#define _ASM_TILE_PROCESSOR_H
-
-#include <arch/chip.h>
-
-#ifndef __ASSEMBLY__
-
-/*
- * NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
- * normally would, due to #include dependencies.
- */
-#include <linux/types.h>
-#include <asm/ptrace.h>
-#include <asm/percpu.h>
-
-#include <arch/spr_def.h>
-
-struct task_struct;
-struct thread_struct;
-
-typedef struct {
- unsigned long seg;
-} mm_segment_t;
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-void *current_text_addr(void);
-
-#if CHIP_HAS_TILE_DMA()
-/* Capture the state of a suspended DMA. */
-struct tile_dma_state {
- int enabled;
- unsigned long src;
- unsigned long dest;
- unsigned long strides;
- unsigned long chunk_size;
- unsigned long src_chunk;
- unsigned long dest_chunk;
- unsigned long byte;
- unsigned long status;
-};
-
-/*
- * A mask of the DMA status register for selecting only the 'running'
- * and 'done' bits.
- */
-#define DMA_STATUS_MASK \
- (SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK)
-#endif
-
-/*
- * Track asynchronous TLB events (faults and access violations)
- * that occur while we are in kernel mode from DMA or the SN processor.
- */
-struct async_tlb {
- short fault_num; /* original fault number; 0 if none */
- char is_fault; /* was it a fault (vs an access violation) */
- char is_write; /* for fault: was it caused by a write? */
- unsigned long address; /* what address faulted? */
-};
-
-#ifdef CONFIG_HARDWALL
-struct hardwall_info;
-struct hardwall_task {
- /* Which hardwall is this task tied to? (or NULL if none) */
- struct hardwall_info *info;
- /* Chains this task into the list at info->task_head. */
- struct list_head list;
-};
-#ifdef __tilepro__
-#define HARDWALL_TYPES 1 /* udn */
-#else
-#define HARDWALL_TYPES 3 /* udn, idn, and ipi */
-#endif
-#endif
-
-struct thread_struct {
- /* kernel stack pointer */
- unsigned long ksp;
- /* kernel PC */
- unsigned long pc;
- /* starting user stack pointer (for page migration) */
- unsigned long usp0;
- /* pid of process that created this one */
- pid_t creator_pid;
-#if CHIP_HAS_TILE_DMA()
- /* DMA info for suspended threads (byte == 0 means no DMA state) */
- struct tile_dma_state tile_dma_state;
-#endif
- /* User EX_CONTEXT registers */
- unsigned long ex_context[2];
- /* User SYSTEM_SAVE registers */
- unsigned long system_save[4];
- /* User interrupt mask */
- unsigned long long interrupt_mask;
- /* User interrupt-control 0 state */
- unsigned long intctrl_0;
- /* Any other miscellaneous processor state bits */
- unsigned long proc_status;
-#if !CHIP_HAS_FIXED_INTVEC_BASE()
- /* Interrupt base for PL0 interrupts */
- unsigned long interrupt_vector_base;
-#endif
- /* Tile cache retry fifo high-water mark */
- unsigned long tile_rtf_hwm;
-#if CHIP_HAS_DSTREAM_PF()
- /* Data stream prefetch control */
- unsigned long dstream_pf;
-#endif
-#ifdef CONFIG_HARDWALL
- /* Hardwall information for various resources. */
- struct hardwall_task hardwall[HARDWALL_TYPES];
-#endif
-#if CHIP_HAS_TILE_DMA()
- /* Async DMA TLB fault information */
- struct async_tlb dma_async_tlb;
-#endif
-};
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Start with "sp" this many bytes below the top of the kernel stack.
- * This allows us to be cache-aware when handling the initial save
- * of the pt_regs value to the stack.
- */
-#define STACK_TOP_DELTA 64
-
-/*
- * When entering the kernel via a fault, start with the top of the
- * pt_regs structure this many bytes below the top of the page.
- * This aligns the pt_regs structure optimally for cache-line access.
- */
-#ifdef __tilegx__
-#define KSTK_PTREGS_GAP 48
-#else
-#define KSTK_PTREGS_GAP 56
-#endif
-
-#ifndef __ASSEMBLY__
-
-#ifdef __tilegx__
-#define TASK_SIZE_MAX (_AC(1, UL) << (MAX_VA_WIDTH - 1))
-#else
-#define TASK_SIZE_MAX PAGE_OFFSET
-#endif
-
-/* TASK_SIZE and related variables are always checked in "current" context. */
-#ifdef CONFIG_COMPAT
-#define COMPAT_TASK_SIZE (1UL << 31)
-#define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\
- COMPAT_TASK_SIZE : TASK_SIZE_MAX)
-#else
-#define TASK_SIZE TASK_SIZE_MAX
-#endif
-
-#define VDSO_BASE ((unsigned long)current->active_mm->context.vdso_base)
-#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
-
-#define STACK_TOP TASK_SIZE
-
-/* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
-#define STACK_TOP_MAX TASK_SIZE_MAX
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's, if it is using bottom-up mapping.
- */
-#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
-
-#define HAVE_ARCH_PICK_MMAP_LAYOUT
-
-#define INIT_THREAD { \
- .ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
- .interrupt_mask = -1ULL \
-}
-
-/* Kernel stack top for the task that first boots on this cpu. */
-DECLARE_PER_CPU(unsigned long, boot_sp);
-
-/* PC to boot from on this cpu. */
-DECLARE_PER_CPU(unsigned long, boot_pc);
-
-/* Do necessary setup to start up a newly executed thread. */
-static inline void start_thread(struct pt_regs *regs,
- unsigned long pc, unsigned long usp)
-{
- regs->pc = pc;
- regs->sp = usp;
- single_step_execve();
-}
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
- /* Nothing for now */
-}
-
-extern void prepare_exit_to_usermode(struct pt_regs *regs, u32 flags);
-
-unsigned long get_wchan(struct task_struct *p);
-
-/* Return initial ksp value for given task. */
-#define task_ksp0(task) \
- ((unsigned long)(task)->stack + THREAD_SIZE - STACK_TOP_DELTA)
-
-/* Return some info about the user process TASK. */
-#define task_pt_regs(task) \
- ((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
-#define current_pt_regs() \
- ((struct pt_regs *)((stack_pointer | (THREAD_SIZE - 1)) - \
- STACK_TOP_DELTA - (KSTK_PTREGS_GAP - 1)) - 1)
-#define task_sp(task) (task_pt_regs(task)->sp)
-#define task_pc(task) (task_pt_regs(task)->pc)
-/* Aliases for pc and sp (used in fs/proc/array.c) */
-#define KSTK_EIP(task) task_pc(task)
-#define KSTK_ESP(task) task_sp(task)
-
-/* Fine-grained unaligned JIT support */
-#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
-#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
-
-extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
-extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
-
-/* Standard format for printing registers and other word-size data. */
-#ifdef __tilegx__
-# define REGFMT "0x%016lx"
-#else
-# define REGFMT "0x%08lx"
-#endif
-
-/*
- * Do some slow action (e.g. read a slow SPR).
- * Note that this must also have compiler-barrier semantics since
- * it may be used in a busy loop reading memory.
- */
-static inline void cpu_relax(void)
-{
- __insn_mfspr(SPR_PASS);
- barrier();
-}
-
-/* Info on this processor (see fs/proc/cpuinfo.c) */
-struct seq_operations;
-extern const struct seq_operations cpuinfo_op;
-
-/* Provide information about the chip model. */
-extern char chip_model[64];
-
-/* Data on which physical memory controller corresponds to which NUMA node. */
-extern int node_controller[];
-
-/* Does the heap allocator return hash-for-home pages by default? */
-extern int hash_default;
-
-/* Should kernel stack pages be hash-for-home? */
-extern int kstack_hash;
-
-/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
-#define uheap_hash hash_default
-
-
-/* Are we using huge pages in the TLB for kernel data? */
-extern int kdata_huge;
-
-/* Support standard Linux prefetching. */
-#define ARCH_HAS_PREFETCH
-#define prefetch(x) __builtin_prefetch(x)
-#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
-
-/* Bring a value into the L1D, faulting the TLB if necessary. */
-#ifdef __tilegx__
-#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
-#else
-#define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
-#endif
-
-#else /* __ASSEMBLY__ */
-
-/* Do some slow action (e.g. read a slow SPR). */
-#define CPU_RELAX mfspr zero, SPR_PASS
-
-#endif /* !__ASSEMBLY__ */
-
-/* Assembly code assumes that the PL is in the low bits. */
-#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
-# error Fix assembly assumptions about PL
-#endif
-
-/* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
-#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \
- SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \
- SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \
- SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
-# error Fix assumptions that EX1 macros work for both PL0 and PL1
-#endif
-
-/* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
-#define EX1_PL(ex1) \
- (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
-#define EX1_ICS(ex1) \
- (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
-#define PL_ICS_EX1(pl, ics) \
- (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
- ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
-
-/*
- * Provide symbolic constants for PLs.
- */
-#define USER_PL 0
-#if CONFIG_KERNEL_PL == 2
-#define GUEST_PL 1
-#endif
-#define KERNEL_PL CONFIG_KERNEL_PL
-
-/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
-#ifdef __tilegx__
-#define CPU_SHIFT 48
-#if CHIP_VA_WIDTH() > CPU_SHIFT
-# error Too many VA bits!
-#endif
-#define MAX_CPU_ID ((1 << (64 - CPU_SHIFT)) - 1)
-#define raw_smp_processor_id() \
- ((int)(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) >> CPU_SHIFT))
-#define get_current_ksp0() \
- ((unsigned long)(((long)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) << \
- (64 - CPU_SHIFT)) >> (64 - CPU_SHIFT)))
-#define next_current_ksp0(task) ({ \
- unsigned long __ksp0 = task_ksp0(task) & ((1UL << CPU_SHIFT) - 1); \
- unsigned long __cpu = (long)raw_smp_processor_id() << CPU_SHIFT; \
- __ksp0 | __cpu; \
-})
-#else
-#define LOG2_NR_CPU_IDS 6
-#define MAX_CPU_ID ((1 << LOG2_NR_CPU_IDS) - 1)
-#define raw_smp_processor_id() \
- ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & MAX_CPU_ID)
-#define get_current_ksp0() \
- (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~MAX_CPU_ID)
-#define next_current_ksp0(task) ({ \
- unsigned long __ksp0 = task_ksp0(task); \
- int __cpu = raw_smp_processor_id(); \
- BUG_ON(__ksp0 & MAX_CPU_ID); \
- __ksp0 | __cpu; \
-})
-#endif
-#if CONFIG_NR_CPUS > (MAX_CPU_ID + 1)
-# error Too many cpus!
-#endif
-
-#endif /* _ASM_TILE_PROCESSOR_H */
diff --git a/arch/tile/include/asm/ptrace.h b/arch/tile/include/asm/ptrace.h
deleted file mode 100644
index b9620c077abc..000000000000
--- a/arch/tile/include/asm/ptrace.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-#ifndef _ASM_TILE_PTRACE_H
-#define _ASM_TILE_PTRACE_H
-
-#include <linux/compiler.h>
-
-#ifndef __ASSEMBLY__
-/* Benefit from consistent use of "long" on all chips. */
-typedef unsigned long pt_reg_t;
-#endif
-
-#include <uapi/asm/ptrace.h>
-
-#define PTRACE_O_MASK_TILE (PTRACE_O_TRACEMIGRATE)
-#define PT_TRACE_MIGRATE PT_EVENT_FLAG(PTRACE_EVENT_MIGRATE)
-
-/* Flag bits in pt_regs.flags */
-#define PT_FLAGS_DISABLE_IRQ 1 /* on return to kernel, disable irqs */
-#define PT_FLAGS_CALLER_SAVES 2 /* caller-save registers are valid */
-#define PT_FLAGS_RESTORE_REGS 4 /* restore callee-save regs on return */
-
-#ifndef __ASSEMBLY__
-
-#define regs_return_value(regs) ((regs)->regs[0])
-#define instruction_pointer(regs) ((regs)->pc)
-#define profile_pc(regs) instruction_pointer(regs)
-#define user_stack_pointer(regs) ((regs)->sp)
-
-/* Does the process account for user or for system time? */
-#define user_mode(regs) (EX1_PL((regs)->ex1) < KERNEL_PL)
-
-/* Fill in a struct pt_regs with the current kernel registers. */
-struct pt_regs *get_pt_regs(struct pt_regs *);
-
-/* Trace the current syscall. */
-extern int do_syscall_trace_enter(struct pt_regs *regs);
-extern void do_syscall_trace_exit(struct pt_regs *regs);
-
-#define arch_has_single_step() (1)
-
-/*
- * A structure for all single-stepper state.
- *
- * Also update defines in assembler section if it changes
- */
-struct single_step_state {
- /* the page to which we will write hacked-up bundles */
- void __user *buffer;
-
- union {
- int flags;
- struct {
- unsigned long is_enabled:1, update:1, update_reg:6;
- };
- };
-
- unsigned long orig_pc; /* the original PC */
- unsigned long next_pc; /* return PC if no branch (PC + 1) */
- unsigned long branch_next_pc; /* return PC if we did branch/jump */
- unsigned long update_value; /* value to restore to update_target */
-};
-
-/* Single-step the instruction at regs->pc */
-extern void single_step_once(struct pt_regs *regs);
-
-/* Clean up after execve(). */
-extern void single_step_execve(void);
-
-struct task_struct;
-
-extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs);
-
-#ifdef __tilegx__
-/* We need this since sigval_t has a user pointer in it, for GETSIGINFO etc. */
-#define __ARCH_WANT_COMPAT_SYS_PTRACE
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#define SINGLESTEP_STATE_MASK_IS_ENABLED 0x1
-#define SINGLESTEP_STATE_MASK_UPDATE 0x2
-#define SINGLESTEP_STATE_TARGET_LB 2
-#define SINGLESTEP_STATE_TARGET_UB 7
-
-#endif /* _ASM_TILE_PTRACE_H */
diff --git a/arch/tile/include/asm/sections.h b/arch/tile/include/asm/sections.h
deleted file mode 100644
index 50343bfe7936..000000000000
--- a/arch/tile/include/asm/sections.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SECTIONS_H
-#define _ASM_TILE_SECTIONS_H
-
-#define arch_is_kernel_data arch_is_kernel_data
-
-#include <asm-generic/sections.h>
-
-extern char vdso_start[], vdso_end[];
-#ifdef CONFIG_COMPAT
-extern char vdso32_start[], vdso32_end[];
-#endif
-
-/* Not exactly sections, but PC comparison points in the code. */
-extern char __rt_sigreturn[], __rt_sigreturn_end[];
-#ifdef __tilegx__
-extern char __start_unalign_asm_code[], __end_unalign_asm_code[];
-#else
-extern char sys_cmpxchg[], __sys_cmpxchg_end[];
-extern char __sys_cmpxchg_grab_lock[];
-extern char __start_atomic_asm_code[], __end_atomic_asm_code[];
-#endif
-
-/* Handle the discontiguity between _sdata and _text. */
-static inline int arch_is_kernel_data(unsigned long addr)
-{
- return addr >= (unsigned long)_sdata &&
- addr < (unsigned long)_end;
-}
-
-#endif /* _ASM_TILE_SECTIONS_H */
diff --git a/arch/tile/include/asm/setup.h b/arch/tile/include/asm/setup.h
deleted file mode 100644
index 2a0347af0702..000000000000
--- a/arch/tile/include/asm/setup.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-#ifndef _ASM_TILE_SETUP_H
-#define _ASM_TILE_SETUP_H
-
-
-#include <linux/pfn.h>
-#include <linux/init.h>
-#include <uapi/asm/setup.h>
-
-/*
- * Reserved space for vmalloc and iomap - defined in asm/page.h
- */
-#define MAXMEM_PFN PFN_DOWN(MAXMEM)
-
-int tile_console_write(const char *buf, int count);
-
-#ifdef CONFIG_EARLY_PRINTK
-void early_panic(const char *fmt, ...);
-#else
-#define early_panic panic
-#endif
-
-/* Init-time routine to do tile-specific per-cpu setup. */
-void setup_cpu(int boot);
-
-/* User-level DMA management functions */
-void grant_dma_mpls(void);
-void restrict_dma_mpls(void);
-
-#ifdef CONFIG_HARDWALL
-/* User-level network management functions */
-void reset_network_state(void);
-struct task_struct;
-void hardwall_switch_tasks(struct task_struct *prev, struct task_struct *next);
-void hardwall_deactivate_all(struct task_struct *task);
-int hardwall_ipi_valid(int cpu);
-
-/* Hook hardwall code into changes in affinity. */
-#define arch_set_cpus_allowed(p, new_mask) do { \
- if (!cpumask_equal(&p->cpus_allowed, new_mask)) \
- hardwall_deactivate_all(p); \
-} while (0)
-#endif
-
-#endif /* _ASM_TILE_SETUP_H */
diff --git a/arch/tile/include/asm/sigframe.h b/arch/tile/include/asm/sigframe.h
deleted file mode 100644
index 994d3d30205f..000000000000
--- a/arch/tile/include/asm/sigframe.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SIGFRAME_H
-#define _ASM_TILE_SIGFRAME_H
-
-/* Indicate that syscall return should not examine r0 */
-#define INT_SWINT_1_SIGRETURN (~0)
-
-#ifndef __ASSEMBLY__
-
-#include <arch/abi.h>
-
-struct rt_sigframe {
- unsigned char save_area[C_ABI_SAVE_AREA_SIZE]; /* caller save area */
- struct siginfo info;
- struct ucontext uc;
-};
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_TILE_SIGFRAME_H */
diff --git a/arch/tile/include/asm/signal.h b/arch/tile/include/asm/signal.h
deleted file mode 100644
index 10e183de96d3..000000000000
--- a/arch/tile/include/asm/signal.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-#ifndef _ASM_TILE_SIGNAL_H
-#define _ASM_TILE_SIGNAL_H
-
-#include <uapi/asm/signal.h>
-
-#if !defined(__ASSEMBLY__)
-struct pt_regs;
-int restore_sigcontext(struct pt_regs *, struct sigcontext __user *);
-int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
-void do_signal(struct pt_regs *regs);
-void signal_fault(const char *type, struct pt_regs *,
- void __user *frame, int sig);
-void trace_unhandled_signal(const char *type, struct pt_regs *regs,
- unsigned long address, int signo);
-#endif
-#endif /* _ASM_TILE_SIGNAL_H */
diff --git a/arch/tile/include/asm/smp.h b/arch/tile/include/asm/smp.h
deleted file mode 100644
index 735e7f144733..000000000000
--- a/arch/tile/include/asm/smp.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SMP_H
-#define _ASM_TILE_SMP_H
-
-#ifdef CONFIG_SMP
-
-#include <asm/processor.h>
-#include <linux/cpumask.h>
-#include <linux/irqreturn.h>
-#include <hv/hypervisor.h>
-
-/* Set up this tile to support receiving hypervisor messages */
-void init_messaging(void);
-
-/* Set up this tile to support receiving device interrupts and IPIs. */
-void init_per_tile_IRQs(void);
-
-/* Send a message to processors specified in mask */
-void send_IPI_many(const struct cpumask *mask, int tag);
-
-/* Send a message to all but the sending processor */
-void send_IPI_allbutself(int tag);
-
-/* Send a message to a specific processor */
-void send_IPI_single(int dest, int tag);
-
-/* Process an IPI message */
-void evaluate_message(int tag);
-
-/* Boot a secondary cpu */
-void online_secondary(void);
-
-/* Topology of the supervisor tile grid, and coordinates of boot processor */
-extern HV_Topology smp_topology;
-
-/* Accessors for grid size */
-#define smp_height (smp_topology.height)
-#define smp_width (smp_topology.width)
-
-/* Convenience functions for converting cpu <-> coords. */
-static inline int cpu_x(int cpu)
-{
- return cpu % smp_width;
-}
-static inline int cpu_y(int cpu)
-{
- return cpu / smp_width;
-}
-static inline int xy_to_cpu(int x, int y)
-{
- return y * smp_width + x;
-}
-
-/* Hypervisor message tags sent via the tile send_IPI*() routines. */
-#define MSG_TAG_START_CPU 1
-#define MSG_TAG_STOP_CPU 2
-#define MSG_TAG_CALL_FUNCTION_MANY 3
-#define MSG_TAG_CALL_FUNCTION_SINGLE 4
-#define MSG_TAG_IRQ_WORK 5
-
-/* Hook for the generic smp_call_function_many() routine. */
-static inline void arch_send_call_function_ipi_mask(struct cpumask *mask)
-{
- send_IPI_many(mask, MSG_TAG_CALL_FUNCTION_MANY);
-}
-
-/* Hook for the generic smp_call_function_single() routine. */
-static inline void arch_send_call_function_single_ipi(int cpu)
-{
- send_IPI_single(cpu, MSG_TAG_CALL_FUNCTION_SINGLE);
-}
-
-/* Print out the boot string describing which cpus were disabled. */
-void print_disabled_cpus(void);
-
-#else /* !CONFIG_SMP */
-
-#define smp_master_cpu 0
-#define smp_height 1
-#define smp_width 1
-#define cpu_x(cpu) 0
-#define cpu_y(cpu) 0
-#define xy_to_cpu(x, y) 0
-
-#endif /* !CONFIG_SMP */
-
-
-/* Which cpus may be used as the lotar in a page table entry. */
-extern struct cpumask cpu_lotar_map;
-#define cpu_is_valid_lotar(cpu) cpumask_test_cpu((cpu), &cpu_lotar_map)
-
-/* Which processors are used for hash-for-home mapping */
-extern struct cpumask hash_for_home_map;
-
-/* Which cpus can have their cache flushed by hv_flush_remote(). */
-extern struct cpumask cpu_cacheable_map;
-#define cpu_cacheable(cpu) cpumask_test_cpu((cpu), &cpu_cacheable_map)
-
-/* Convert an HV_LOTAR value into a cpu. */
-static inline int hv_lotar_to_cpu(HV_LOTAR lotar)
-{
- return HV_LOTAR_X(lotar) + (HV_LOTAR_Y(lotar) * smp_width);
-}
-
-/*
- * Extension of <linux/cpumask.h> functionality when you just want
- * to express a mask or suppression or inclusion region without
- * being too concerned about exactly which cpus are valid in that region.
- */
-int bitmap_parselist_crop(const char *bp, unsigned long *maskp, int nmaskbits);
-
-#define cpulist_parse_crop(buf, dst) \
- __cpulist_parse_crop((buf), (dst), NR_CPUS)
-static inline int __cpulist_parse_crop(const char *buf, struct cpumask *dstp,
- int nbits)
-{
- return bitmap_parselist_crop(buf, cpumask_bits(dstp), nbits);
-}
-
-/* Initialize the IPI subsystem. */
-void ipi_init(void);
-
-/* Function for start-cpu message to cause us to jump to. */
-extern unsigned long start_cpu_function_addr;
-
-#endif /* _ASM_TILE_SMP_H */
diff --git a/arch/tile/include/asm/spinlock.h b/arch/tile/include/asm/spinlock.h
deleted file mode 100644
index 1a8bd4740c28..000000000000
--- a/arch/tile/include/asm/spinlock.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SPINLOCK_H
-#define _ASM_TILE_SPINLOCK_H
-
-#ifdef __tilegx__
-#include <asm/spinlock_64.h>
-#else
-#include <asm/spinlock_32.h>
-#endif
-
-#endif /* _ASM_TILE_SPINLOCK_H */
diff --git a/arch/tile/include/asm/spinlock_32.h b/arch/tile/include/asm/spinlock_32.h
deleted file mode 100644
index fb5313d77315..000000000000
--- a/arch/tile/include/asm/spinlock_32.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * 32-bit SMP spinlocks.
- */
-
-#ifndef _ASM_TILE_SPINLOCK_32_H
-#define _ASM_TILE_SPINLOCK_32_H
-
-#include <linux/atomic.h>
-#include <asm/page.h>
-#include <linux/compiler.h>
-
-/*
- * We only use even ticket numbers so the '1' inserted by a tns is
- * an unambiguous "ticket is busy" flag.
- */
-#define TICKET_QUANTUM 2
-
-
-/*
- * SMP ticket spinlocks, allowing only a single CPU anywhere
- *
- * (the type definitions are in asm/spinlock_types.h)
- */
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- /*
- * Note that even if a new ticket is in the process of being
- * acquired, so lock->next_ticket is 1, it's still reasonable
- * to claim the lock is held, since it will be momentarily
- * if not already. There's no need to wait for a "valid"
- * lock->next_ticket to become available.
- * Use READ_ONCE() to ensure that calling this in a loop is OK.
- */
- int curr = READ_ONCE(lock->current_ticket);
- int next = READ_ONCE(lock->next_ticket);
-
- return next != curr;
-}
-
-void arch_spin_lock(arch_spinlock_t *lock);
-
-int arch_spin_trylock(arch_spinlock_t *lock);
-
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- /* For efficiency, overlap fetching the old ticket with the wmb(). */
- int old_ticket = lock->current_ticket;
- wmb(); /* guarantee anything modified under the lock is visible */
- lock->current_ticket = old_ticket + TICKET_QUANTUM;
-}
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * We use a "tns/store-back" technique on a single word to manage
- * the lock state, looping around to retry if the tns returns 1.
- */
-
-/* Internal layout of the word; do not use. */
-#define _WR_NEXT_SHIFT 8
-#define _WR_CURR_SHIFT 16
-#define _WR_WIDTH 8
-#define _RD_COUNT_SHIFT 24
-#define _RD_COUNT_WIDTH 8
-
-/**
- * arch_read_lock() - acquire a read lock.
- */
-void arch_read_lock(arch_rwlock_t *rwlock);
-
-/**
- * arch_write_lock() - acquire a write lock.
- */
-void arch_write_lock(arch_rwlock_t *rwlock);
-
-/**
- * arch_read_trylock() - try to acquire a read lock.
- */
-int arch_read_trylock(arch_rwlock_t *rwlock);
-
-/**
- * arch_write_trylock() - try to acquire a write lock.
- */
-int arch_write_trylock(arch_rwlock_t *rwlock);
-
-/**
- * arch_read_unlock() - release a read lock.
- */
-void arch_read_unlock(arch_rwlock_t *rwlock);
-
-/**
- * arch_write_unlock() - release a write lock.
- */
-void arch_write_unlock(arch_rwlock_t *rwlock);
-
-#endif /* _ASM_TILE_SPINLOCK_32_H */
diff --git a/arch/tile/include/asm/spinlock_64.h b/arch/tile/include/asm/spinlock_64.h
deleted file mode 100644
index 5b616ef642a8..000000000000
--- a/arch/tile/include/asm/spinlock_64.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * 64-bit SMP ticket spinlocks, allowing only a single CPU anywhere
- * (the type definitions are in asm/spinlock_types.h)
- */
-
-#ifndef _ASM_TILE_SPINLOCK_64_H
-#define _ASM_TILE_SPINLOCK_64_H
-
-#include <linux/compiler.h>
-
-/* Shifts and masks for the various fields in "lock". */
-#define __ARCH_SPIN_CURRENT_SHIFT 17
-#define __ARCH_SPIN_NEXT_MASK 0x7fff
-#define __ARCH_SPIN_NEXT_OVERFLOW 0x8000
-
-/*
- * Return the "current" portion of a ticket lock value,
- * i.e. the number that currently owns the lock.
- */
-static inline u32 arch_spin_current(u32 val)
-{
- return val >> __ARCH_SPIN_CURRENT_SHIFT;
-}
-
-/*
- * Return the "next" portion of a ticket lock value,
- * i.e. the number that the next task to try to acquire the lock will get.
- */
-static inline u32 arch_spin_next(u32 val)
-{
- return val & __ARCH_SPIN_NEXT_MASK;
-}
-
-/* The lock is locked if a task would have to wait to get it. */
-static inline int arch_spin_is_locked(arch_spinlock_t *lock)
-{
- /* Use READ_ONCE() to ensure that calling this in a loop is OK. */
- u32 val = READ_ONCE(lock->lock);
- return arch_spin_current(val) != arch_spin_next(val);
-}
-
-/* Bump the current ticket so the next task owns the lock. */
-static inline void arch_spin_unlock(arch_spinlock_t *lock)
-{
- wmb(); /* guarantee anything modified under the lock is visible */
- __insn_fetchadd4(&lock->lock, 1U << __ARCH_SPIN_CURRENT_SHIFT);
-}
-
-void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
-
-/* Grab the "next" ticket number and bump it atomically.
- * If the current ticket is not ours, go to the slow path.
- * We also take the slow path if the "next" value overflows.
- */
-static inline void arch_spin_lock(arch_spinlock_t *lock)
-{
- u32 val = __insn_fetchadd4(&lock->lock, 1);
- u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW);
- if (unlikely(arch_spin_current(val) != ticket))
- arch_spin_lock_slow(lock, ticket);
-}
-
-/* Try to get the lock, and return whether we succeeded. */
-int arch_spin_trylock(arch_spinlock_t *lock);
-
-/*
- * Read-write spinlocks, allowing multiple readers
- * but only one writer.
- *
- * We use fetchadd() for readers, and fetchor() with the sign bit
- * for writers.
- */
-
-#define __WRITE_LOCK_BIT (1 << 31)
-
-static inline int arch_write_val_locked(int val)
-{
- return val < 0; /* Optimize "val & __WRITE_LOCK_BIT". */
-}
-
-extern void __read_lock_failed(arch_rwlock_t *rw);
-
-static inline void arch_read_lock(arch_rwlock_t *rw)
-{
- u32 val = __insn_fetchaddgez4(&rw->lock, 1);
- if (unlikely(arch_write_val_locked(val)))
- __read_lock_failed(rw);
-}
-
-extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
-
-static inline void arch_write_lock(arch_rwlock_t *rw)
-{
- u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
- if (unlikely(val != 0))
- __write_lock_failed(rw, val);
-}
-
-static inline void arch_read_unlock(arch_rwlock_t *rw)
-{
- __insn_mf();
- __insn_fetchadd4(&rw->lock, -1);
-}
-
-static inline void arch_write_unlock(arch_rwlock_t *rw)
-{
- __insn_mf();
- __insn_exch4(&rw->lock, 0); /* Avoid waiting in the write buffer. */
-}
-
-static inline int arch_read_trylock(arch_rwlock_t *rw)
-{
- return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1));
-}
-
-static inline int arch_write_trylock(arch_rwlock_t *rw)
-{
- u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
- if (likely(val == 0))
- return 1;
- if (!arch_write_val_locked(val))
- __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
- return 0;
-}
-
-#endif /* _ASM_TILE_SPINLOCK_64_H */
diff --git a/arch/tile/include/asm/spinlock_types.h b/arch/tile/include/asm/spinlock_types.h
deleted file mode 100644
index a71f59b49c50..000000000000
--- a/arch/tile/include/asm/spinlock_types.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SPINLOCK_TYPES_H
-#define _ASM_TILE_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-#ifdef __tilegx__
-
-/* Low 15 bits are "next"; high 15 bits are "current". */
-typedef struct arch_spinlock {
- unsigned int lock;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
-
-/* High bit is "writer owns"; low 31 bits are a count of readers. */
-typedef struct arch_rwlock {
- unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { 0 }
-
-#else
-
-typedef struct arch_spinlock {
- /* Next ticket number to hand out. */
- int next_ticket;
- /* The ticket number that currently owns this lock. */
- int current_ticket;
-} arch_spinlock_t;
-
-#define __ARCH_SPIN_LOCK_UNLOCKED { 0, 0 }
-
-/*
- * Byte 0 for tns (only the low bit is used), byte 1 for ticket-lock "next",
- * byte 2 for ticket-lock "current", byte 3 for reader count.
- */
-typedef struct arch_rwlock {
- unsigned int lock;
-} arch_rwlock_t;
-
-#define __ARCH_RW_LOCK_UNLOCKED { 0 }
-
-#endif
-#endif /* _ASM_TILE_SPINLOCK_TYPES_H */
diff --git a/arch/tile/include/asm/stack.h b/arch/tile/include/asm/stack.h
deleted file mode 100644
index 3573325e340b..000000000000
--- a/arch/tile/include/asm/stack.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_STACK_H
-#define _ASM_TILE_STACK_H
-
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-
-#include <asm/backtrace.h>
-#include <asm/page.h>
-#include <hv/hypervisor.h>
-
-/* Everything we need to keep track of a backtrace iteration */
-struct KBacktraceIterator {
- BacktraceIterator it;
- struct task_struct *task; /* task we are backtracing */
- int end; /* iteration complete. */
- int new_context; /* new context is starting */
- int profile; /* profiling, so stop on async intrpt */
- int verbose; /* printk extra info (don't want to
- * do this for profiling) */
- int is_current; /* backtracing current task */
-};
-
-/* Iteration methods for kernel backtraces */
-
-/*
- * Initialize a KBacktraceIterator from a task_struct, and optionally from
- * a set of registers. If the registers are omitted, the process is
- * assumed to be descheduled, and registers are read from the process's
- * thread_struct and stack. "verbose" means to printk some additional
- * information about fault handlers as we pass them on the stack.
- */
-extern void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
- struct task_struct *, struct pt_regs *);
-
-/* Initialize iterator based on current stack. */
-extern void KBacktraceIterator_init_current(struct KBacktraceIterator *kbt);
-
-/* Helper method for above. */
-extern void _KBacktraceIterator_init_current(struct KBacktraceIterator *kbt,
- ulong pc, ulong lr, ulong sp, ulong r52);
-
-/* No more frames? */
-extern int KBacktraceIterator_end(struct KBacktraceIterator *kbt);
-
-/* Advance to the next frame. */
-extern void KBacktraceIterator_next(struct KBacktraceIterator *kbt);
-
-/* Dump just the contents of the pt_regs structure. */
-extern void tile_show_regs(struct pt_regs *);
-
-/*
- * Dump stack given complete register info. Use only from the
- * architecture-specific code; show_stack()
- * and dump_stack() are architecture-independent entry points.
- */
-extern void tile_show_stack(struct KBacktraceIterator *);
-
-#endif /* _ASM_TILE_STACK_H */
diff --git a/arch/tile/include/asm/string.h b/arch/tile/include/asm/string.h
deleted file mode 100644
index 92b271bd9ebd..000000000000
--- a/arch/tile/include/asm/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_STRING_H
-#define _ASM_TILE_STRING_H
-
-#define __HAVE_ARCH_MEMCHR
-#define __HAVE_ARCH_MEMSET
-#define __HAVE_ARCH_MEMCPY
-#define __HAVE_ARCH_MEMMOVE
-#define __HAVE_ARCH_STRCHR
-#define __HAVE_ARCH_STRLEN
-#define __HAVE_ARCH_STRNLEN
-
-extern __kernel_size_t strlen(const char *);
-extern __kernel_size_t strnlen(const char *, __kernel_size_t);
-extern char *strchr(const char *s, int c);
-extern void *memchr(const void *s, int c, size_t n);
-extern void *memset(void *, int, __kernel_size_t);
-extern void *memcpy(void *, const void *, __kernel_size_t);
-extern void *memmove(void *, const void *, __kernel_size_t);
-
-#endif /* _ASM_TILE_STRING_H */
diff --git a/arch/tile/include/asm/switch_to.h b/arch/tile/include/asm/switch_to.h
deleted file mode 100644
index 34ee72705521..000000000000
--- a/arch/tile/include/asm/switch_to.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SWITCH_TO_H
-#define _ASM_TILE_SWITCH_TO_H
-
-#include <arch/sim_def.h>
-
-/*
- * switch_to(n) should switch tasks to task nr n, first
- * checking that n isn't the current task, in which case it does nothing.
- * The number of callee-saved registers saved on the kernel stack
- * is defined here for use in copy_thread() and must agree with __switch_to().
- */
-#define CALLEE_SAVED_FIRST_REG 30
-#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
-
-#ifndef __ASSEMBLY__
-
-struct task_struct;
-
-/*
- * Pause the DMA engine and static network before task switching.
- */
-#define prepare_arch_switch(next) _prepare_arch_switch(next)
-void _prepare_arch_switch(struct task_struct *next);
-
-struct task_struct;
-#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
-extern struct task_struct *_switch_to(struct task_struct *prev,
- struct task_struct *next);
-
-/* Helper function for _switch_to(). */
-extern struct task_struct *__switch_to(struct task_struct *prev,
- struct task_struct *next,
- unsigned long new_system_save_k_0);
-
-/* Address that switched-away from tasks are at. */
-extern unsigned long get_switch_to_pc(void);
-
-/*
- * Kernel threads can check to see if they need to migrate their
- * stack whenever they return from a context switch; for user
- * threads, we defer until they are returning to user-space.
- * We defer homecache migration until the runqueue lock is released.
- */
-#define finish_arch_post_lock_switch() do { \
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
- (current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
- if (current->mm == NULL && !kstack_hash && \
- current_thread_info()->homecache_cpu != raw_smp_processor_id()) \
- homecache_migrate_kthread(); \
-} while (0)
-
-/* Support function for forking a new task. */
-void ret_from_fork(void);
-
-/* Support function for forking a new kernel thread. */
-void ret_from_kernel_thread(void *fn, void *arg);
-
-/* Called from ret_from_xxx() when a new process starts up. */
-struct task_struct *sim_notify_fork(struct task_struct *prev);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_TILE_SWITCH_TO_H */
diff --git a/arch/tile/include/asm/syscall.h b/arch/tile/include/asm/syscall.h
deleted file mode 100644
index 373d73064ea1..000000000000
--- a/arch/tile/include/asm/syscall.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (C) 2008-2009 Red Hat, Inc. All rights reserved.
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * See asm-generic/syscall.h for descriptions of what we must do here.
- */
-
-#ifndef _ASM_TILE_SYSCALL_H
-#define _ASM_TILE_SYSCALL_H
-
-#include <linux/sched.h>
-#include <linux/err.h>
-#include <linux/audit.h>
-#include <linux/compat.h>
-#include <arch/abi.h>
-
-/* The array of function pointers for syscalls. */
-extern void *sys_call_table[];
-#ifdef CONFIG_COMPAT
-extern void *compat_sys_call_table[];
-#endif
-
-/*
- * Only the low 32 bits of orig_r0 are meaningful, so we return int.
- * This importantly ignores the high bits on 64-bit, so comparisons
- * sign-extend the low 32 bits.
- */
-static inline int syscall_get_nr(struct task_struct *t, struct pt_regs *regs)
-{
- return regs->regs[TREG_SYSCALL_NR];
-}
-
-static inline void syscall_rollback(struct task_struct *task,
- struct pt_regs *regs)
-{
- regs->regs[0] = regs->orig_r0;
-}
-
-static inline long syscall_get_error(struct task_struct *task,
- struct pt_regs *regs)
-{
- unsigned long error = regs->regs[0];
- return IS_ERR_VALUE(error) ? error : 0;
-}
-
-static inline long syscall_get_return_value(struct task_struct *task,
- struct pt_regs *regs)
-{
- return regs->regs[0];
-}
-
-static inline void syscall_set_return_value(struct task_struct *task,
- struct pt_regs *regs,
- int error, long val)
-{
- if (error) {
- /* R0 is the passed-in negative error, R1 is positive. */
- regs->regs[0] = error;
- regs->regs[1] = -error;
- } else {
- /* R1 set to zero to indicate no error. */
- regs->regs[0] = val;
- regs->regs[1] = 0;
- }
-}
-
-static inline void syscall_get_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- unsigned long *args)
-{
- BUG_ON(i + n > 6);
- memcpy(args, &regs[i], n * sizeof(args[0]));
-}
-
-static inline void syscall_set_arguments(struct task_struct *task,
- struct pt_regs *regs,
- unsigned int i, unsigned int n,
- const unsigned long *args)
-{
- BUG_ON(i + n > 6);
- memcpy(&regs[i], args, n * sizeof(args[0]));
-}
-
-/*
- * We don't care about endianness (__AUDIT_ARCH_LE bit) here because
- * tile has the same system calls both on little- and big- endian.
- */
-static inline int syscall_get_arch(void)
-{
- if (is_compat_task())
- return AUDIT_ARCH_TILEGX32;
-
-#ifdef CONFIG_TILEGX
- return AUDIT_ARCH_TILEGX;
-#else
- return AUDIT_ARCH_TILEPRO;
-#endif
-}
-
-#endif /* _ASM_TILE_SYSCALL_H */
diff --git a/arch/tile/include/asm/syscalls.h b/arch/tile/include/asm/syscalls.h
deleted file mode 100644
index 07b298450ef2..000000000000
--- a/arch/tile/include/asm/syscalls.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * syscalls.h - Linux syscall interfaces (arch-specific)
- *
- * Copyright (c) 2008 Jaswinder Singh Rajput
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SYSCALLS_H
-#define _ASM_TILE_SYSCALLS_H
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <linux/signal.h>
-#include <linux/types.h>
-#include <linux/compat.h>
-
-/*
- * Note that by convention, any syscall which requires the current
- * register set takes an additional "struct pt_regs *" pointer; a
- * _sys_xxx() trampoline in intvec*.S just sets up the pointer and
- * jumps to sys_xxx().
- */
-
-/* kernel/sys.c */
-ssize_t sys32_readahead(int fd, u32 offset_lo, u32 offset_hi, u32 count);
-long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi,
- u32 len, int advice);
-int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi,
- u32 len_lo, u32 len_hi, int advice);
-long sys_cacheflush(unsigned long addr, unsigned long len,
- unsigned long flags);
-#ifndef __tilegx__ /* No mmap() in the 32-bit kernel. */
-#define sys_mmap sys_mmap
-#endif
-
-#ifndef __tilegx__
-/* mm/fault.c */
-long sys_cmpxchg_badaddr(unsigned long address);
-#endif
-
-#ifdef CONFIG_COMPAT
-/* These four are not defined for 64-bit, but serve as "compat" syscalls. */
-long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg);
-long sys_fstat64(unsigned long fd, struct stat64 __user *statbuf);
-long sys_truncate64(const char __user *path, loff_t length);
-long sys_ftruncate64(unsigned int fd, loff_t length);
-#endif
-
-/* Provide versions of standard syscalls that use current_pt_regs(). */
-long sys_rt_sigreturn(void);
-#define sys_rt_sigreturn sys_rt_sigreturn
-
-/* These are the intvec*.S trampolines. */
-long _sys_rt_sigreturn(void);
-long _sys_clone(unsigned long clone_flags, unsigned long newsp,
- void __user *parent_tid, void __user *child_tid);
-
-#include <asm-generic/syscalls.h>
-
-#endif /* _ASM_TILE_SYSCALLS_H */
diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h
deleted file mode 100644
index 2adcacd85749..000000000000
--- a/arch/tile/include/asm/thread_info.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright (C) 2002 David Howells (dhowells@redhat.com)
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_THREAD_INFO_H
-#define _ASM_TILE_THREAD_INFO_H
-
-#include <asm/processor.h>
-#include <asm/page.h>
-#ifndef __ASSEMBLY__
-
-/*
- * Low level task data that assembly code needs immediate access to.
- * The structure is placed at the bottom of the supervisor stack.
- */
-struct thread_info {
- struct task_struct *task; /* main task structure */
- unsigned long flags; /* low level flags */
- unsigned long status; /* thread-synchronous flags */
- __u32 homecache_cpu; /* CPU we are homecached on */
- __u32 cpu; /* current CPU */
- int preempt_count; /* 0 => preemptable,
- <0 => BUG */
-
- mm_segment_t addr_limit; /* thread address space
- (KERNEL_DS or USER_DS) */
- struct single_step_state *step_state; /* single step state
- (if non-zero) */
- int align_ctl; /* controls unaligned access */
-#ifdef __tilegx__
- unsigned long unalign_jit_tmp[4]; /* temp r0..r3 storage */
- void __user *unalign_jit_base; /* unalign fixup JIT base */
-#endif
- bool in_backtrace; /* currently doing backtrace? */
-};
-
-/*
- * macros/functions for gaining access to the thread information structure.
- */
-#define INIT_THREAD_INFO(tsk) \
-{ \
- .task = &tsk, \
- .flags = 0, \
- .cpu = 0, \
- .preempt_count = INIT_PREEMPT_COUNT, \
- .addr_limit = KERNEL_DS, \
- .step_state = NULL, \
- .align_ctl = 0, \
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#if PAGE_SIZE < 8192
-#define THREAD_SIZE_ORDER (13 - PAGE_SHIFT)
-#else
-#define THREAD_SIZE_ORDER (0)
-#endif
-#define THREAD_SIZE_PAGES (1 << THREAD_SIZE_ORDER)
-
-#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
-#define LOG2_THREAD_SIZE (PAGE_SHIFT + THREAD_SIZE_ORDER)
-
-#define STACK_WARN (THREAD_SIZE/8)
-
-#ifndef __ASSEMBLY__
-
-void arch_release_thread_stack(unsigned long *stack);
-
-/* How to get the thread information struct from C. */
-register unsigned long stack_pointer __asm__("sp");
-
-#define current_thread_info() \
- ((struct thread_info *)(stack_pointer & -THREAD_SIZE))
-
-/* Sit on a nap instruction until interrupted. */
-extern void smp_nap(void);
-
-/* Enable interrupts racelessly and nap forever: helper for arch_cpu_idle(). */
-extern void _cpu_idle(void);
-
-#else /* __ASSEMBLY__ */
-
-/*
- * How to get the thread information struct from assembly.
- * Note that we use different macros since different architectures
- * have different semantics in their "mm" instruction and we would
- * like to guarantee that the macro expands to exactly one instruction.
- */
-#ifdef __tilegx__
-#define EXTRACT_THREAD_INFO(reg) mm reg, zero, LOG2_THREAD_SIZE, 63
-#else
-#define GET_THREAD_INFO(reg) mm reg, sp, zero, LOG2_THREAD_SIZE, 31
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Thread information flags that various assembly files may need to access.
- * Keep flags accessed frequently in low bits, particular since it makes
- * it easier to build constants in assembly.
- */
-#define TIF_SIGPENDING 0 /* signal pending */
-#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
-#define TIF_SINGLESTEP 2 /* restore singlestep on return to
- user mode */
-#define TIF_ASYNC_TLB 3 /* got an async TLB fault in kernel */
-#define TIF_SYSCALL_TRACE 4 /* syscall trace active */
-#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
-#define TIF_SECCOMP 6 /* secure computing */
-#define TIF_MEMDIE 7 /* OOM killer at work */
-#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
-#define TIF_SYSCALL_TRACEPOINT 9 /* syscall tracepoint instrumentation */
-#define TIF_POLLING_NRFLAG 10 /* idle is polling for TIF_NEED_RESCHED */
-#define TIF_NOHZ 11 /* in adaptive nohz mode */
-
-#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
-#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
-#define _TIF_ASYNC_TLB (1<<TIF_ASYNC_TLB)
-#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_SECCOMP (1<<TIF_SECCOMP)
-#define _TIF_MEMDIE (1<<TIF_MEMDIE)
-#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
-#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
-#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
-#define _TIF_NOHZ (1<<TIF_NOHZ)
-
-/* Work to do as we loop to exit to user space. */
-#define _TIF_WORK_MASK \
- (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
- _TIF_ASYNC_TLB | _TIF_NOTIFY_RESUME)
-
-/* Work to do on any return to user space. */
-#define _TIF_ALLWORK_MASK \
- (_TIF_WORK_MASK | _TIF_SINGLESTEP | _TIF_NOHZ)
-
-/* Work to do at syscall entry. */
-#define _TIF_SYSCALL_ENTRY_WORK \
- (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT | _TIF_NOHZ)
-
-/* Work to do at syscall exit. */
-#define _TIF_SYSCALL_EXIT_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_TRACEPOINT)
-
-/*
- * Thread-synchronous status.
- *
- * This is different from the flags in that nobody else
- * ever touches our thread-synchronous status, so we don't
- * have to worry about atomic accesses.
- */
-#ifdef __tilegx__
-#define TS_COMPAT 0x0001 /* 32-bit compatibility mode */
-#endif
-
-#endif /* _ASM_TILE_THREAD_INFO_H */
diff --git a/arch/tile/include/asm/tile-desc.h b/arch/tile/include/asm/tile-desc.h
deleted file mode 100644
index 43849bf79dcb..000000000000
--- a/arch/tile/include/asm/tile-desc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __tilegx__
-#include <asm/tile-desc_32.h>
-#else
-#include <asm/tile-desc_64.h>
-#endif
diff --git a/arch/tile/include/asm/tile-desc_32.h b/arch/tile/include/asm/tile-desc_32.h
deleted file mode 100644
index f09c5c43b0b2..000000000000
--- a/arch/tile/include/asm/tile-desc_32.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/* TILEPro opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-#ifndef opcode_tilepro_h
-#define opcode_tilepro_h
-
-#include <arch/opcode.h>
-
-
-enum
-{
- TILEPRO_MAX_OPERANDS = 5 /* mm */
-};
-
-typedef enum
-{
- TILEPRO_OPC_BPT,
- TILEPRO_OPC_INFO,
- TILEPRO_OPC_INFOL,
- TILEPRO_OPC_J,
- TILEPRO_OPC_JAL,
- TILEPRO_OPC_MOVE,
- TILEPRO_OPC_MOVE_SN,
- TILEPRO_OPC_MOVEI,
- TILEPRO_OPC_MOVEI_SN,
- TILEPRO_OPC_MOVELI,
- TILEPRO_OPC_MOVELI_SN,
- TILEPRO_OPC_MOVELIS,
- TILEPRO_OPC_PREFETCH,
- TILEPRO_OPC_RAISE,
- TILEPRO_OPC_ADD,
- TILEPRO_OPC_ADD_SN,
- TILEPRO_OPC_ADDB,
- TILEPRO_OPC_ADDB_SN,
- TILEPRO_OPC_ADDBS_U,
- TILEPRO_OPC_ADDBS_U_SN,
- TILEPRO_OPC_ADDH,
- TILEPRO_OPC_ADDH_SN,
- TILEPRO_OPC_ADDHS,
- TILEPRO_OPC_ADDHS_SN,
- TILEPRO_OPC_ADDI,
- TILEPRO_OPC_ADDI_SN,
- TILEPRO_OPC_ADDIB,
- TILEPRO_OPC_ADDIB_SN,
- TILEPRO_OPC_ADDIH,
- TILEPRO_OPC_ADDIH_SN,
- TILEPRO_OPC_ADDLI,
- TILEPRO_OPC_ADDLI_SN,
- TILEPRO_OPC_ADDLIS,
- TILEPRO_OPC_ADDS,
- TILEPRO_OPC_ADDS_SN,
- TILEPRO_OPC_ADIFFB_U,
- TILEPRO_OPC_ADIFFB_U_SN,
- TILEPRO_OPC_ADIFFH,
- TILEPRO_OPC_ADIFFH_SN,
- TILEPRO_OPC_AND,
- TILEPRO_OPC_AND_SN,
- TILEPRO_OPC_ANDI,
- TILEPRO_OPC_ANDI_SN,
- TILEPRO_OPC_AULI,
- TILEPRO_OPC_AVGB_U,
- TILEPRO_OPC_AVGB_U_SN,
- TILEPRO_OPC_AVGH,
- TILEPRO_OPC_AVGH_SN,
- TILEPRO_OPC_BBNS,
- TILEPRO_OPC_BBNS_SN,
- TILEPRO_OPC_BBNST,
- TILEPRO_OPC_BBNST_SN,
- TILEPRO_OPC_BBS,
- TILEPRO_OPC_BBS_SN,
- TILEPRO_OPC_BBST,
- TILEPRO_OPC_BBST_SN,
- TILEPRO_OPC_BGEZ,
- TILEPRO_OPC_BGEZ_SN,
- TILEPRO_OPC_BGEZT,
- TILEPRO_OPC_BGEZT_SN,
- TILEPRO_OPC_BGZ,
- TILEPRO_OPC_BGZ_SN,
- TILEPRO_OPC_BGZT,
- TILEPRO_OPC_BGZT_SN,
- TILEPRO_OPC_BITX,
- TILEPRO_OPC_BITX_SN,
- TILEPRO_OPC_BLEZ,
- TILEPRO_OPC_BLEZ_SN,
- TILEPRO_OPC_BLEZT,
- TILEPRO_OPC_BLEZT_SN,
- TILEPRO_OPC_BLZ,
- TILEPRO_OPC_BLZ_SN,
- TILEPRO_OPC_BLZT,
- TILEPRO_OPC_BLZT_SN,
- TILEPRO_OPC_BNZ,
- TILEPRO_OPC_BNZ_SN,
- TILEPRO_OPC_BNZT,
- TILEPRO_OPC_BNZT_SN,
- TILEPRO_OPC_BYTEX,
- TILEPRO_OPC_BYTEX_SN,
- TILEPRO_OPC_BZ,
- TILEPRO_OPC_BZ_SN,
- TILEPRO_OPC_BZT,
- TILEPRO_OPC_BZT_SN,
- TILEPRO_OPC_CLZ,
- TILEPRO_OPC_CLZ_SN,
- TILEPRO_OPC_CRC32_32,
- TILEPRO_OPC_CRC32_32_SN,
- TILEPRO_OPC_CRC32_8,
- TILEPRO_OPC_CRC32_8_SN,
- TILEPRO_OPC_CTZ,
- TILEPRO_OPC_CTZ_SN,
- TILEPRO_OPC_DRAIN,
- TILEPRO_OPC_DTLBPR,
- TILEPRO_OPC_DWORD_ALIGN,
- TILEPRO_OPC_DWORD_ALIGN_SN,
- TILEPRO_OPC_FINV,
- TILEPRO_OPC_FLUSH,
- TILEPRO_OPC_FNOP,
- TILEPRO_OPC_ICOH,
- TILEPRO_OPC_ILL,
- TILEPRO_OPC_INTHB,
- TILEPRO_OPC_INTHB_SN,
- TILEPRO_OPC_INTHH,
- TILEPRO_OPC_INTHH_SN,
- TILEPRO_OPC_INTLB,
- TILEPRO_OPC_INTLB_SN,
- TILEPRO_OPC_INTLH,
- TILEPRO_OPC_INTLH_SN,
- TILEPRO_OPC_INV,
- TILEPRO_OPC_IRET,
- TILEPRO_OPC_JALB,
- TILEPRO_OPC_JALF,
- TILEPRO_OPC_JALR,
- TILEPRO_OPC_JALRP,
- TILEPRO_OPC_JB,
- TILEPRO_OPC_JF,
- TILEPRO_OPC_JR,
- TILEPRO_OPC_JRP,
- TILEPRO_OPC_LB,
- TILEPRO_OPC_LB_SN,
- TILEPRO_OPC_LB_U,
- TILEPRO_OPC_LB_U_SN,
- TILEPRO_OPC_LBADD,
- TILEPRO_OPC_LBADD_SN,
- TILEPRO_OPC_LBADD_U,
- TILEPRO_OPC_LBADD_U_SN,
- TILEPRO_OPC_LH,
- TILEPRO_OPC_LH_SN,
- TILEPRO_OPC_LH_U,
- TILEPRO_OPC_LH_U_SN,
- TILEPRO_OPC_LHADD,
- TILEPRO_OPC_LHADD_SN,
- TILEPRO_OPC_LHADD_U,
- TILEPRO_OPC_LHADD_U_SN,
- TILEPRO_OPC_LNK,
- TILEPRO_OPC_LNK_SN,
- TILEPRO_OPC_LW,
- TILEPRO_OPC_LW_SN,
- TILEPRO_OPC_LW_NA,
- TILEPRO_OPC_LW_NA_SN,
- TILEPRO_OPC_LWADD,
- TILEPRO_OPC_LWADD_SN,
- TILEPRO_OPC_LWADD_NA,
- TILEPRO_OPC_LWADD_NA_SN,
- TILEPRO_OPC_MAXB_U,
- TILEPRO_OPC_MAXB_U_SN,
- TILEPRO_OPC_MAXH,
- TILEPRO_OPC_MAXH_SN,
- TILEPRO_OPC_MAXIB_U,
- TILEPRO_OPC_MAXIB_U_SN,
- TILEPRO_OPC_MAXIH,
- TILEPRO_OPC_MAXIH_SN,
- TILEPRO_OPC_MF,
- TILEPRO_OPC_MFSPR,
- TILEPRO_OPC_MINB_U,
- TILEPRO_OPC_MINB_U_SN,
- TILEPRO_OPC_MINH,
- TILEPRO_OPC_MINH_SN,
- TILEPRO_OPC_MINIB_U,
- TILEPRO_OPC_MINIB_U_SN,
- TILEPRO_OPC_MINIH,
- TILEPRO_OPC_MINIH_SN,
- TILEPRO_OPC_MM,
- TILEPRO_OPC_MNZ,
- TILEPRO_OPC_MNZ_SN,
- TILEPRO_OPC_MNZB,
- TILEPRO_OPC_MNZB_SN,
- TILEPRO_OPC_MNZH,
- TILEPRO_OPC_MNZH_SN,
- TILEPRO_OPC_MTSPR,
- TILEPRO_OPC_MULHH_SS,
- TILEPRO_OPC_MULHH_SS_SN,
- TILEPRO_OPC_MULHH_SU,
- TILEPRO_OPC_MULHH_SU_SN,
- TILEPRO_OPC_MULHH_UU,
- TILEPRO_OPC_MULHH_UU_SN,
- TILEPRO_OPC_MULHHA_SS,
- TILEPRO_OPC_MULHHA_SS_SN,
- TILEPRO_OPC_MULHHA_SU,
- TILEPRO_OPC_MULHHA_SU_SN,
- TILEPRO_OPC_MULHHA_UU,
- TILEPRO_OPC_MULHHA_UU_SN,
- TILEPRO_OPC_MULHHSA_UU,
- TILEPRO_OPC_MULHHSA_UU_SN,
- TILEPRO_OPC_MULHL_SS,
- TILEPRO_OPC_MULHL_SS_SN,
- TILEPRO_OPC_MULHL_SU,
- TILEPRO_OPC_MULHL_SU_SN,
- TILEPRO_OPC_MULHL_US,
- TILEPRO_OPC_MULHL_US_SN,
- TILEPRO_OPC_MULHL_UU,
- TILEPRO_OPC_MULHL_UU_SN,
- TILEPRO_OPC_MULHLA_SS,
- TILEPRO_OPC_MULHLA_SS_SN,
- TILEPRO_OPC_MULHLA_SU,
- TILEPRO_OPC_MULHLA_SU_SN,
- TILEPRO_OPC_MULHLA_US,
- TILEPRO_OPC_MULHLA_US_SN,
- TILEPRO_OPC_MULHLA_UU,
- TILEPRO_OPC_MULHLA_UU_SN,
- TILEPRO_OPC_MULHLSA_UU,
- TILEPRO_OPC_MULHLSA_UU_SN,
- TILEPRO_OPC_MULLL_SS,
- TILEPRO_OPC_MULLL_SS_SN,
- TILEPRO_OPC_MULLL_SU,
- TILEPRO_OPC_MULLL_SU_SN,
- TILEPRO_OPC_MULLL_UU,
- TILEPRO_OPC_MULLL_UU_SN,
- TILEPRO_OPC_MULLLA_SS,
- TILEPRO_OPC_MULLLA_SS_SN,
- TILEPRO_OPC_MULLLA_SU,
- TILEPRO_OPC_MULLLA_SU_SN,
- TILEPRO_OPC_MULLLA_UU,
- TILEPRO_OPC_MULLLA_UU_SN,
- TILEPRO_OPC_MULLLSA_UU,
- TILEPRO_OPC_MULLLSA_UU_SN,
- TILEPRO_OPC_MVNZ,
- TILEPRO_OPC_MVNZ_SN,
- TILEPRO_OPC_MVZ,
- TILEPRO_OPC_MVZ_SN,
- TILEPRO_OPC_MZ,
- TILEPRO_OPC_MZ_SN,
- TILEPRO_OPC_MZB,
- TILEPRO_OPC_MZB_SN,
- TILEPRO_OPC_MZH,
- TILEPRO_OPC_MZH_SN,
- TILEPRO_OPC_NAP,
- TILEPRO_OPC_NOP,
- TILEPRO_OPC_NOR,
- TILEPRO_OPC_NOR_SN,
- TILEPRO_OPC_OR,
- TILEPRO_OPC_OR_SN,
- TILEPRO_OPC_ORI,
- TILEPRO_OPC_ORI_SN,
- TILEPRO_OPC_PACKBS_U,
- TILEPRO_OPC_PACKBS_U_SN,
- TILEPRO_OPC_PACKHB,
- TILEPRO_OPC_PACKHB_SN,
- TILEPRO_OPC_PACKHS,
- TILEPRO_OPC_PACKHS_SN,
- TILEPRO_OPC_PACKLB,
- TILEPRO_OPC_PACKLB_SN,
- TILEPRO_OPC_PCNT,
- TILEPRO_OPC_PCNT_SN,
- TILEPRO_OPC_RL,
- TILEPRO_OPC_RL_SN,
- TILEPRO_OPC_RLI,
- TILEPRO_OPC_RLI_SN,
- TILEPRO_OPC_S1A,
- TILEPRO_OPC_S1A_SN,
- TILEPRO_OPC_S2A,
- TILEPRO_OPC_S2A_SN,
- TILEPRO_OPC_S3A,
- TILEPRO_OPC_S3A_SN,
- TILEPRO_OPC_SADAB_U,
- TILEPRO_OPC_SADAB_U_SN,
- TILEPRO_OPC_SADAH,
- TILEPRO_OPC_SADAH_SN,
- TILEPRO_OPC_SADAH_U,
- TILEPRO_OPC_SADAH_U_SN,
- TILEPRO_OPC_SADB_U,
- TILEPRO_OPC_SADB_U_SN,
- TILEPRO_OPC_SADH,
- TILEPRO_OPC_SADH_SN,
- TILEPRO_OPC_SADH_U,
- TILEPRO_OPC_SADH_U_SN,
- TILEPRO_OPC_SB,
- TILEPRO_OPC_SBADD,
- TILEPRO_OPC_SEQ,
- TILEPRO_OPC_SEQ_SN,
- TILEPRO_OPC_SEQB,
- TILEPRO_OPC_SEQB_SN,
- TILEPRO_OPC_SEQH,
- TILEPRO_OPC_SEQH_SN,
- TILEPRO_OPC_SEQI,
- TILEPRO_OPC_SEQI_SN,
- TILEPRO_OPC_SEQIB,
- TILEPRO_OPC_SEQIB_SN,
- TILEPRO_OPC_SEQIH,
- TILEPRO_OPC_SEQIH_SN,
- TILEPRO_OPC_SH,
- TILEPRO_OPC_SHADD,
- TILEPRO_OPC_SHL,
- TILEPRO_OPC_SHL_SN,
- TILEPRO_OPC_SHLB,
- TILEPRO_OPC_SHLB_SN,
- TILEPRO_OPC_SHLH,
- TILEPRO_OPC_SHLH_SN,
- TILEPRO_OPC_SHLI,
- TILEPRO_OPC_SHLI_SN,
- TILEPRO_OPC_SHLIB,
- TILEPRO_OPC_SHLIB_SN,
- TILEPRO_OPC_SHLIH,
- TILEPRO_OPC_SHLIH_SN,
- TILEPRO_OPC_SHR,
- TILEPRO_OPC_SHR_SN,
- TILEPRO_OPC_SHRB,
- TILEPRO_OPC_SHRB_SN,
- TILEPRO_OPC_SHRH,
- TILEPRO_OPC_SHRH_SN,
- TILEPRO_OPC_SHRI,
- TILEPRO_OPC_SHRI_SN,
- TILEPRO_OPC_SHRIB,
- TILEPRO_OPC_SHRIB_SN,
- TILEPRO_OPC_SHRIH,
- TILEPRO_OPC_SHRIH_SN,
- TILEPRO_OPC_SLT,
- TILEPRO_OPC_SLT_SN,
- TILEPRO_OPC_SLT_U,
- TILEPRO_OPC_SLT_U_SN,
- TILEPRO_OPC_SLTB,
- TILEPRO_OPC_SLTB_SN,
- TILEPRO_OPC_SLTB_U,
- TILEPRO_OPC_SLTB_U_SN,
- TILEPRO_OPC_SLTE,
- TILEPRO_OPC_SLTE_SN,
- TILEPRO_OPC_SLTE_U,
- TILEPRO_OPC_SLTE_U_SN,
- TILEPRO_OPC_SLTEB,
- TILEPRO_OPC_SLTEB_SN,
- TILEPRO_OPC_SLTEB_U,
- TILEPRO_OPC_SLTEB_U_SN,
- TILEPRO_OPC_SLTEH,
- TILEPRO_OPC_SLTEH_SN,
- TILEPRO_OPC_SLTEH_U,
- TILEPRO_OPC_SLTEH_U_SN,
- TILEPRO_OPC_SLTH,
- TILEPRO_OPC_SLTH_SN,
- TILEPRO_OPC_SLTH_U,
- TILEPRO_OPC_SLTH_U_SN,
- TILEPRO_OPC_SLTI,
- TILEPRO_OPC_SLTI_SN,
- TILEPRO_OPC_SLTI_U,
- TILEPRO_OPC_SLTI_U_SN,
- TILEPRO_OPC_SLTIB,
- TILEPRO_OPC_SLTIB_SN,
- TILEPRO_OPC_SLTIB_U,
- TILEPRO_OPC_SLTIB_U_SN,
- TILEPRO_OPC_SLTIH,
- TILEPRO_OPC_SLTIH_SN,
- TILEPRO_OPC_SLTIH_U,
- TILEPRO_OPC_SLTIH_U_SN,
- TILEPRO_OPC_SNE,
- TILEPRO_OPC_SNE_SN,
- TILEPRO_OPC_SNEB,
- TILEPRO_OPC_SNEB_SN,
- TILEPRO_OPC_SNEH,
- TILEPRO_OPC_SNEH_SN,
- TILEPRO_OPC_SRA,
- TILEPRO_OPC_SRA_SN,
- TILEPRO_OPC_SRAB,
- TILEPRO_OPC_SRAB_SN,
- TILEPRO_OPC_SRAH,
- TILEPRO_OPC_SRAH_SN,
- TILEPRO_OPC_SRAI,
- TILEPRO_OPC_SRAI_SN,
- TILEPRO_OPC_SRAIB,
- TILEPRO_OPC_SRAIB_SN,
- TILEPRO_OPC_SRAIH,
- TILEPRO_OPC_SRAIH_SN,
- TILEPRO_OPC_SUB,
- TILEPRO_OPC_SUB_SN,
- TILEPRO_OPC_SUBB,
- TILEPRO_OPC_SUBB_SN,
- TILEPRO_OPC_SUBBS_U,
- TILEPRO_OPC_SUBBS_U_SN,
- TILEPRO_OPC_SUBH,
- TILEPRO_OPC_SUBH_SN,
- TILEPRO_OPC_SUBHS,
- TILEPRO_OPC_SUBHS_SN,
- TILEPRO_OPC_SUBS,
- TILEPRO_OPC_SUBS_SN,
- TILEPRO_OPC_SW,
- TILEPRO_OPC_SWADD,
- TILEPRO_OPC_SWINT0,
- TILEPRO_OPC_SWINT1,
- TILEPRO_OPC_SWINT2,
- TILEPRO_OPC_SWINT3,
- TILEPRO_OPC_TBLIDXB0,
- TILEPRO_OPC_TBLIDXB0_SN,
- TILEPRO_OPC_TBLIDXB1,
- TILEPRO_OPC_TBLIDXB1_SN,
- TILEPRO_OPC_TBLIDXB2,
- TILEPRO_OPC_TBLIDXB2_SN,
- TILEPRO_OPC_TBLIDXB3,
- TILEPRO_OPC_TBLIDXB3_SN,
- TILEPRO_OPC_TNS,
- TILEPRO_OPC_TNS_SN,
- TILEPRO_OPC_WH64,
- TILEPRO_OPC_XOR,
- TILEPRO_OPC_XOR_SN,
- TILEPRO_OPC_XORI,
- TILEPRO_OPC_XORI_SN,
- TILEPRO_OPC_NONE
-} tilepro_mnemonic;
-
-
-
-
-typedef enum
-{
- TILEPRO_PIPELINE_X0,
- TILEPRO_PIPELINE_X1,
- TILEPRO_PIPELINE_Y0,
- TILEPRO_PIPELINE_Y1,
- TILEPRO_PIPELINE_Y2,
-} tilepro_pipeline;
-
-#define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1)
-
-typedef enum
-{
- TILEPRO_OP_TYPE_REGISTER,
- TILEPRO_OP_TYPE_IMMEDIATE,
- TILEPRO_OP_TYPE_ADDRESS,
- TILEPRO_OP_TYPE_SPR
-} tilepro_operand_type;
-
-struct tilepro_operand
-{
- /* Is this operand a register, immediate or address? */
- tilepro_operand_type type;
-
- /* The default relocation type for this operand. */
- signed int default_reloc : 16;
-
- /* How many bits is this value? (used for range checking) */
- unsigned int num_bits : 5;
-
- /* Is the value signed? (used for range checking) */
- unsigned int is_signed : 1;
-
- /* Is this operand a source register? */
- unsigned int is_src_reg : 1;
-
- /* Is this operand written? (i.e. is it a destination register) */
- unsigned int is_dest_reg : 1;
-
- /* Is this operand PC-relative? */
- unsigned int is_pc_relative : 1;
-
- /* By how many bits do we right shift the value before inserting? */
- unsigned int rightshift : 2;
-
- /* Return the bits for this operand to be ORed into an existing bundle. */
- tilepro_bundle_bits (*insert) (int op);
-
- /* Extract this operand and return it. */
- unsigned int (*extract) (tilepro_bundle_bits bundle);
-};
-
-
-extern const struct tilepro_operand tilepro_operands[];
-
-/* One finite-state machine per pipe for rapid instruction decoding. */
-extern const unsigned short * const
-tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS];
-
-
-struct tilepro_opcode
-{
- /* The opcode mnemonic, e.g. "add" */
- const char *name;
-
- /* The enum value for this mnemonic. */
- tilepro_mnemonic mnemonic;
-
- /* A bit mask of which of the five pipes this instruction
- is compatible with:
- X0 0x01
- X1 0x02
- Y0 0x04
- Y1 0x08
- Y2 0x10 */
- unsigned char pipes;
-
- /* How many operands are there? */
- unsigned char num_operands;
-
- /* Which register does this write implicitly, or TREG_ZERO if none? */
- unsigned char implicitly_written_register;
-
- /* Can this be bundled with other instructions (almost always true). */
- unsigned char can_bundle;
-
- /* The description of the operands. Each of these is an
- * index into the tilepro_operands[] table. */
- unsigned char operands[TILEPRO_NUM_PIPELINE_ENCODINGS][TILEPRO_MAX_OPERANDS];
-
-};
-
-extern const struct tilepro_opcode tilepro_opcodes[];
-
-
-/* Used for non-textual disassembly into structs. */
-struct tilepro_decoded_instruction
-{
- const struct tilepro_opcode *opcode;
- const struct tilepro_operand *operands[TILEPRO_MAX_OPERANDS];
- int operand_values[TILEPRO_MAX_OPERANDS];
-};
-
-
-/* Disassemble a bundle into a struct for machine processing. */
-extern int parse_insn_tilepro(tilepro_bundle_bits bits,
- unsigned int pc,
- struct tilepro_decoded_instruction
- decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]);
-
-
-/* Given a set of bundle bits and a specific pipe, returns which
- * instruction the bundle contains in that pipe.
- */
-extern const struct tilepro_opcode *
-find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe);
-
-
-
-#endif /* opcode_tilepro_h */
diff --git a/arch/tile/include/asm/tile-desc_64.h b/arch/tile/include/asm/tile-desc_64.h
deleted file mode 100644
index 1819efcba54d..000000000000
--- a/arch/tile/include/asm/tile-desc_64.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/* TILE-Gx opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-#ifndef opcode_tile_h
-#define opcode_tile_h
-
-#include <arch/opcode.h>
-
-
-enum
-{
- TILEGX_MAX_OPERANDS = 4 /* bfexts */
-};
-
-typedef enum
-{
- TILEGX_OPC_BPT,
- TILEGX_OPC_INFO,
- TILEGX_OPC_INFOL,
- TILEGX_OPC_MOVE,
- TILEGX_OPC_MOVEI,
- TILEGX_OPC_MOVELI,
- TILEGX_OPC_PREFETCH,
- TILEGX_OPC_PREFETCH_ADD_L1,
- TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L2,
- TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
- TILEGX_OPC_PREFETCH_ADD_L3,
- TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- TILEGX_OPC_PREFETCH_L1,
- TILEGX_OPC_PREFETCH_L1_FAULT,
- TILEGX_OPC_PREFETCH_L2,
- TILEGX_OPC_PREFETCH_L2_FAULT,
- TILEGX_OPC_PREFETCH_L3,
- TILEGX_OPC_PREFETCH_L3_FAULT,
- TILEGX_OPC_RAISE,
- TILEGX_OPC_ADD,
- TILEGX_OPC_ADDI,
- TILEGX_OPC_ADDLI,
- TILEGX_OPC_ADDX,
- TILEGX_OPC_ADDXI,
- TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXSC,
- TILEGX_OPC_AND,
- TILEGX_OPC_ANDI,
- TILEGX_OPC_BEQZ,
- TILEGX_OPC_BEQZT,
- TILEGX_OPC_BFEXTS,
- TILEGX_OPC_BFEXTU,
- TILEGX_OPC_BFINS,
- TILEGX_OPC_BGEZ,
- TILEGX_OPC_BGEZT,
- TILEGX_OPC_BGTZ,
- TILEGX_OPC_BGTZT,
- TILEGX_OPC_BLBC,
- TILEGX_OPC_BLBCT,
- TILEGX_OPC_BLBS,
- TILEGX_OPC_BLBST,
- TILEGX_OPC_BLEZ,
- TILEGX_OPC_BLEZT,
- TILEGX_OPC_BLTZ,
- TILEGX_OPC_BLTZT,
- TILEGX_OPC_BNEZ,
- TILEGX_OPC_BNEZT,
- TILEGX_OPC_CLZ,
- TILEGX_OPC_CMOVEQZ,
- TILEGX_OPC_CMOVNEZ,
- TILEGX_OPC_CMPEQ,
- TILEGX_OPC_CMPEQI,
- TILEGX_OPC_CMPEXCH,
- TILEGX_OPC_CMPEXCH4,
- TILEGX_OPC_CMPLES,
- TILEGX_OPC_CMPLEU,
- TILEGX_OPC_CMPLTS,
- TILEGX_OPC_CMPLTSI,
- TILEGX_OPC_CMPLTU,
- TILEGX_OPC_CMPLTUI,
- TILEGX_OPC_CMPNE,
- TILEGX_OPC_CMUL,
- TILEGX_OPC_CMULA,
- TILEGX_OPC_CMULAF,
- TILEGX_OPC_CMULF,
- TILEGX_OPC_CMULFR,
- TILEGX_OPC_CMULH,
- TILEGX_OPC_CMULHR,
- TILEGX_OPC_CRC32_32,
- TILEGX_OPC_CRC32_8,
- TILEGX_OPC_CTZ,
- TILEGX_OPC_DBLALIGN,
- TILEGX_OPC_DBLALIGN2,
- TILEGX_OPC_DBLALIGN4,
- TILEGX_OPC_DBLALIGN6,
- TILEGX_OPC_DRAIN,
- TILEGX_OPC_DTLBPR,
- TILEGX_OPC_EXCH,
- TILEGX_OPC_EXCH4,
- TILEGX_OPC_FDOUBLE_ADD_FLAGS,
- TILEGX_OPC_FDOUBLE_ADDSUB,
- TILEGX_OPC_FDOUBLE_MUL_FLAGS,
- TILEGX_OPC_FDOUBLE_PACK1,
- TILEGX_OPC_FDOUBLE_PACK2,
- TILEGX_OPC_FDOUBLE_SUB_FLAGS,
- TILEGX_OPC_FDOUBLE_UNPACK_MAX,
- TILEGX_OPC_FDOUBLE_UNPACK_MIN,
- TILEGX_OPC_FETCHADD,
- TILEGX_OPC_FETCHADD4,
- TILEGX_OPC_FETCHADDGEZ,
- TILEGX_OPC_FETCHADDGEZ4,
- TILEGX_OPC_FETCHAND,
- TILEGX_OPC_FETCHAND4,
- TILEGX_OPC_FETCHOR,
- TILEGX_OPC_FETCHOR4,
- TILEGX_OPC_FINV,
- TILEGX_OPC_FLUSH,
- TILEGX_OPC_FLUSHWB,
- TILEGX_OPC_FNOP,
- TILEGX_OPC_FSINGLE_ADD1,
- TILEGX_OPC_FSINGLE_ADDSUB2,
- TILEGX_OPC_FSINGLE_MUL1,
- TILEGX_OPC_FSINGLE_MUL2,
- TILEGX_OPC_FSINGLE_PACK1,
- TILEGX_OPC_FSINGLE_PACK2,
- TILEGX_OPC_FSINGLE_SUB1,
- TILEGX_OPC_ICOH,
- TILEGX_OPC_ILL,
- TILEGX_OPC_INV,
- TILEGX_OPC_IRET,
- TILEGX_OPC_J,
- TILEGX_OPC_JAL,
- TILEGX_OPC_JALR,
- TILEGX_OPC_JALRP,
- TILEGX_OPC_JR,
- TILEGX_OPC_JRP,
- TILEGX_OPC_LD,
- TILEGX_OPC_LD1S,
- TILEGX_OPC_LD1S_ADD,
- TILEGX_OPC_LD1U,
- TILEGX_OPC_LD1U_ADD,
- TILEGX_OPC_LD2S,
- TILEGX_OPC_LD2S_ADD,
- TILEGX_OPC_LD2U,
- TILEGX_OPC_LD2U_ADD,
- TILEGX_OPC_LD4S,
- TILEGX_OPC_LD4S_ADD,
- TILEGX_OPC_LD4U,
- TILEGX_OPC_LD4U_ADD,
- TILEGX_OPC_LD_ADD,
- TILEGX_OPC_LDNA,
- TILEGX_OPC_LDNA_ADD,
- TILEGX_OPC_LDNT,
- TILEGX_OPC_LDNT1S,
- TILEGX_OPC_LDNT1S_ADD,
- TILEGX_OPC_LDNT1U,
- TILEGX_OPC_LDNT1U_ADD,
- TILEGX_OPC_LDNT2S,
- TILEGX_OPC_LDNT2S_ADD,
- TILEGX_OPC_LDNT2U,
- TILEGX_OPC_LDNT2U_ADD,
- TILEGX_OPC_LDNT4S,
- TILEGX_OPC_LDNT4S_ADD,
- TILEGX_OPC_LDNT4U,
- TILEGX_OPC_LDNT4U_ADD,
- TILEGX_OPC_LDNT_ADD,
- TILEGX_OPC_LNK,
- TILEGX_OPC_MF,
- TILEGX_OPC_MFSPR,
- TILEGX_OPC_MM,
- TILEGX_OPC_MNZ,
- TILEGX_OPC_MTSPR,
- TILEGX_OPC_MUL_HS_HS,
- TILEGX_OPC_MUL_HS_HU,
- TILEGX_OPC_MUL_HS_LS,
- TILEGX_OPC_MUL_HS_LU,
- TILEGX_OPC_MUL_HU_HU,
- TILEGX_OPC_MUL_HU_LS,
- TILEGX_OPC_MUL_HU_LU,
- TILEGX_OPC_MUL_LS_LS,
- TILEGX_OPC_MUL_LS_LU,
- TILEGX_OPC_MUL_LU_LU,
- TILEGX_OPC_MULA_HS_HS,
- TILEGX_OPC_MULA_HS_HU,
- TILEGX_OPC_MULA_HS_LS,
- TILEGX_OPC_MULA_HS_LU,
- TILEGX_OPC_MULA_HU_HU,
- TILEGX_OPC_MULA_HU_LS,
- TILEGX_OPC_MULA_HU_LU,
- TILEGX_OPC_MULA_LS_LS,
- TILEGX_OPC_MULA_LS_LU,
- TILEGX_OPC_MULA_LU_LU,
- TILEGX_OPC_MULAX,
- TILEGX_OPC_MULX,
- TILEGX_OPC_MZ,
- TILEGX_OPC_NAP,
- TILEGX_OPC_NOP,
- TILEGX_OPC_NOR,
- TILEGX_OPC_OR,
- TILEGX_OPC_ORI,
- TILEGX_OPC_PCNT,
- TILEGX_OPC_REVBITS,
- TILEGX_OPC_REVBYTES,
- TILEGX_OPC_ROTL,
- TILEGX_OPC_ROTLI,
- TILEGX_OPC_SHL,
- TILEGX_OPC_SHL16INSLI,
- TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADDX,
- TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADDX,
- TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADDX,
- TILEGX_OPC_SHLI,
- TILEGX_OPC_SHLX,
- TILEGX_OPC_SHLXI,
- TILEGX_OPC_SHRS,
- TILEGX_OPC_SHRSI,
- TILEGX_OPC_SHRU,
- TILEGX_OPC_SHRUI,
- TILEGX_OPC_SHRUX,
- TILEGX_OPC_SHRUXI,
- TILEGX_OPC_SHUFFLEBYTES,
- TILEGX_OPC_ST,
- TILEGX_OPC_ST1,
- TILEGX_OPC_ST1_ADD,
- TILEGX_OPC_ST2,
- TILEGX_OPC_ST2_ADD,
- TILEGX_OPC_ST4,
- TILEGX_OPC_ST4_ADD,
- TILEGX_OPC_ST_ADD,
- TILEGX_OPC_STNT,
- TILEGX_OPC_STNT1,
- TILEGX_OPC_STNT1_ADD,
- TILEGX_OPC_STNT2,
- TILEGX_OPC_STNT2_ADD,
- TILEGX_OPC_STNT4,
- TILEGX_OPC_STNT4_ADD,
- TILEGX_OPC_STNT_ADD,
- TILEGX_OPC_SUB,
- TILEGX_OPC_SUBX,
- TILEGX_OPC_SUBXSC,
- TILEGX_OPC_SWINT0,
- TILEGX_OPC_SWINT1,
- TILEGX_OPC_SWINT2,
- TILEGX_OPC_SWINT3,
- TILEGX_OPC_TBLIDXB0,
- TILEGX_OPC_TBLIDXB1,
- TILEGX_OPC_TBLIDXB2,
- TILEGX_OPC_TBLIDXB3,
- TILEGX_OPC_V1ADD,
- TILEGX_OPC_V1ADDI,
- TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADIFFU,
- TILEGX_OPC_V1AVGU,
- TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPEQI,
- TILEGX_OPC_V1CMPLES,
- TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTSI,
- TILEGX_OPC_V1CMPLTU,
- TILEGX_OPC_V1CMPLTUI,
- TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1DDOTPU,
- TILEGX_OPC_V1DDOTPUA,
- TILEGX_OPC_V1DDOTPUS,
- TILEGX_OPC_V1DDOTPUSA,
- TILEGX_OPC_V1DOTP,
- TILEGX_OPC_V1DOTPA,
- TILEGX_OPC_V1DOTPU,
- TILEGX_OPC_V1DOTPUA,
- TILEGX_OPC_V1DOTPUS,
- TILEGX_OPC_V1DOTPUSA,
- TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_L,
- TILEGX_OPC_V1MAXU,
- TILEGX_OPC_V1MAXUI,
- TILEGX_OPC_V1MINU,
- TILEGX_OPC_V1MINUI,
- TILEGX_OPC_V1MNZ,
- TILEGX_OPC_V1MULTU,
- TILEGX_OPC_V1MULU,
- TILEGX_OPC_V1MULUS,
- TILEGX_OPC_V1MZ,
- TILEGX_OPC_V1SADAU,
- TILEGX_OPC_V1SADU,
- TILEGX_OPC_V1SHL,
- TILEGX_OPC_V1SHLI,
- TILEGX_OPC_V1SHRS,
- TILEGX_OPC_V1SHRSI,
- TILEGX_OPC_V1SHRU,
- TILEGX_OPC_V1SHRUI,
- TILEGX_OPC_V1SUB,
- TILEGX_OPC_V1SUBUC,
- TILEGX_OPC_V2ADD,
- TILEGX_OPC_V2ADDI,
- TILEGX_OPC_V2ADDSC,
- TILEGX_OPC_V2ADIFFS,
- TILEGX_OPC_V2AVGS,
- TILEGX_OPC_V2CMPEQ,
- TILEGX_OPC_V2CMPEQI,
- TILEGX_OPC_V2CMPLES,
- TILEGX_OPC_V2CMPLEU,
- TILEGX_OPC_V2CMPLTS,
- TILEGX_OPC_V2CMPLTSI,
- TILEGX_OPC_V2CMPLTU,
- TILEGX_OPC_V2CMPLTUI,
- TILEGX_OPC_V2CMPNE,
- TILEGX_OPC_V2DOTP,
- TILEGX_OPC_V2DOTPA,
- TILEGX_OPC_V2INT_H,
- TILEGX_OPC_V2INT_L,
- TILEGX_OPC_V2MAXS,
- TILEGX_OPC_V2MAXSI,
- TILEGX_OPC_V2MINS,
- TILEGX_OPC_V2MINSI,
- TILEGX_OPC_V2MNZ,
- TILEGX_OPC_V2MULFSC,
- TILEGX_OPC_V2MULS,
- TILEGX_OPC_V2MULTS,
- TILEGX_OPC_V2MZ,
- TILEGX_OPC_V2PACKH,
- TILEGX_OPC_V2PACKL,
- TILEGX_OPC_V2PACKUC,
- TILEGX_OPC_V2SADAS,
- TILEGX_OPC_V2SADAU,
- TILEGX_OPC_V2SADS,
- TILEGX_OPC_V2SADU,
- TILEGX_OPC_V2SHL,
- TILEGX_OPC_V2SHLI,
- TILEGX_OPC_V2SHLSC,
- TILEGX_OPC_V2SHRS,
- TILEGX_OPC_V2SHRSI,
- TILEGX_OPC_V2SHRU,
- TILEGX_OPC_V2SHRUI,
- TILEGX_OPC_V2SUB,
- TILEGX_OPC_V2SUBSC,
- TILEGX_OPC_V4ADD,
- TILEGX_OPC_V4ADDSC,
- TILEGX_OPC_V4INT_H,
- TILEGX_OPC_V4INT_L,
- TILEGX_OPC_V4PACKSC,
- TILEGX_OPC_V4SHL,
- TILEGX_OPC_V4SHLSC,
- TILEGX_OPC_V4SHRS,
- TILEGX_OPC_V4SHRU,
- TILEGX_OPC_V4SUB,
- TILEGX_OPC_V4SUBSC,
- TILEGX_OPC_WH64,
- TILEGX_OPC_XOR,
- TILEGX_OPC_XORI,
- TILEGX_OPC_NONE
-} tilegx_mnemonic;
-
-
-
-typedef enum
-{
- TILEGX_PIPELINE_X0,
- TILEGX_PIPELINE_X1,
- TILEGX_PIPELINE_Y0,
- TILEGX_PIPELINE_Y1,
- TILEGX_PIPELINE_Y2,
-} tilegx_pipeline;
-
-#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
-
-typedef enum
-{
- TILEGX_OP_TYPE_REGISTER,
- TILEGX_OP_TYPE_IMMEDIATE,
- TILEGX_OP_TYPE_ADDRESS,
- TILEGX_OP_TYPE_SPR
-} tilegx_operand_type;
-
-struct tilegx_operand
-{
- /* Is this operand a register, immediate or address? */
- tilegx_operand_type type;
-
- /* The default relocation type for this operand. */
- signed int default_reloc : 16;
-
- /* How many bits is this value? (used for range checking) */
- unsigned int num_bits : 5;
-
- /* Is the value signed? (used for range checking) */
- unsigned int is_signed : 1;
-
- /* Is this operand a source register? */
- unsigned int is_src_reg : 1;
-
- /* Is this operand written? (i.e. is it a destination register) */
- unsigned int is_dest_reg : 1;
-
- /* Is this operand PC-relative? */
- unsigned int is_pc_relative : 1;
-
- /* By how many bits do we right shift the value before inserting? */
- unsigned int rightshift : 2;
-
- /* Return the bits for this operand to be ORed into an existing bundle. */
- tilegx_bundle_bits (*insert) (int op);
-
- /* Extract this operand and return it. */
- unsigned int (*extract) (tilegx_bundle_bits bundle);
-};
-
-
-extern const struct tilegx_operand tilegx_operands[];
-
-/* One finite-state machine per pipe for rapid instruction decoding. */
-extern const unsigned short * const
-tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
-
-
-struct tilegx_opcode
-{
- /* The opcode mnemonic, e.g. "add" */
- const char *name;
-
- /* The enum value for this mnemonic. */
- tilegx_mnemonic mnemonic;
-
- /* A bit mask of which of the five pipes this instruction
- is compatible with:
- X0 0x01
- X1 0x02
- Y0 0x04
- Y1 0x08
- Y2 0x10 */
- unsigned char pipes;
-
- /* How many operands are there? */
- unsigned char num_operands;
-
- /* Which register does this write implicitly, or TREG_ZERO if none? */
- unsigned char implicitly_written_register;
-
- /* Can this be bundled with other instructions (almost always true). */
- unsigned char can_bundle;
-
- /* The description of the operands. Each of these is an
- * index into the tilegx_operands[] table. */
- unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
-
-};
-
-extern const struct tilegx_opcode tilegx_opcodes[];
-
-/* Used for non-textual disassembly into structs. */
-struct tilegx_decoded_instruction
-{
- const struct tilegx_opcode *opcode;
- const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
- long long operand_values[TILEGX_MAX_OPERANDS];
-};
-
-
-/* Disassemble a bundle into a struct for machine processing. */
-extern int parse_insn_tilegx(tilegx_bundle_bits bits,
- unsigned long long pc,
- struct tilegx_decoded_instruction
- decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
-
-
-
-#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/timex.h b/arch/tile/include/asm/timex.h
deleted file mode 100644
index dc987d53e2a9..000000000000
--- a/arch/tile/include/asm/timex.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_TIMEX_H
-#define _ASM_TILE_TIMEX_H
-
-/*
- * This rate should be a multiple of the possible HZ values (100, 250, 1000)
- * and a fraction of the possible hardware timer frequencies. Our timer
- * frequency is highly tunable but also quite precise, so for the primary use
- * of this value (setting ACT_HZ from HZ) we just pick a value that causes
- * ACT_HZ to be set to HZ. We make the value somewhat large just to be
- * more robust in case someone tries out a new value of HZ.
- */
-#define CLOCK_TICK_RATE 1000000
-
-typedef unsigned long long cycles_t;
-
-#if CHIP_HAS_SPLIT_CYCLE()
-cycles_t get_cycles(void);
-#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
-#else
-static inline cycles_t get_cycles(void)
-{
- return __insn_mfspr(SPR_CYCLE);
-}
-#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
-#endif
-
-cycles_t get_clock_rate(void);
-
-/* Convert nanoseconds to core clock cycles. */
-cycles_t ns2cycles(unsigned long nsecs);
-
-/* Called at cpu initialization to set some low-level constants. */
-void setup_clock(void);
-
-/* Called at cpu initialization to start the tile-timer clock device. */
-void setup_tile_timer(void);
-
-#endif /* _ASM_TILE_TIMEX_H */
diff --git a/arch/tile/include/asm/tlb.h b/arch/tile/include/asm/tlb.h
deleted file mode 100644
index 4a891a1a8df3..000000000000
--- a/arch/tile/include/asm/tlb.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_TLB_H
-#define _ASM_TILE_TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* _ASM_TILE_TLB_H */
diff --git a/arch/tile/include/asm/tlbflush.h b/arch/tile/include/asm/tlbflush.h
deleted file mode 100644
index dcf91b25a1e5..000000000000
--- a/arch/tile/include/asm/tlbflush.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_TLBFLUSH_H
-#define _ASM_TILE_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-#include <asm/cacheflush.h>
-#include <asm/page.h>
-#include <hv/hypervisor.h>
-
-/*
- * Rather than associating each mm with its own ASID, we just use
- * ASIDs to allow us to lazily flush the TLB when we switch mms.
- * This way we only have to do an actual TLB flush on mm switch
- * every time we wrap ASIDs, not every single time we switch.
- *
- * FIXME: We might improve performance by keeping ASIDs around
- * properly, though since the hypervisor direct-maps VAs to TSB
- * entries, we're likely to have lost at least the executable page
- * mappings by the time we switch back to the original mm.
- */
-DECLARE_PER_CPU(int, current_asid);
-
-/* The hypervisor tells us what ASIDs are available to us. */
-extern int min_asid, max_asid;
-
-/* Pass as vma pointer for non-executable mapping, if no vma available. */
-#define FLUSH_NONEXEC ((struct vm_area_struct *)-1UL)
-
-/* Flush a single user page on this cpu. */
-static inline void local_flush_tlb_page(struct vm_area_struct *vma,
- unsigned long addr,
- unsigned long page_size)
-{
- int rc = hv_flush_page(addr, page_size);
- if (rc < 0)
- panic("hv_flush_page(%#lx,%#lx) failed: %d",
- addr, page_size, rc);
- if (!vma || (vma != FLUSH_NONEXEC && (vma->vm_flags & VM_EXEC)))
- __flush_icache();
-}
-
-/* Flush range of user pages on this cpu. */
-static inline void local_flush_tlb_pages(struct vm_area_struct *vma,
- unsigned long addr,
- unsigned long page_size,
- unsigned long len)
-{
- int rc = hv_flush_pages(addr, page_size, len);
- if (rc < 0)
- panic("hv_flush_pages(%#lx,%#lx,%#lx) failed: %d",
- addr, page_size, len, rc);
- if (!vma || (vma != FLUSH_NONEXEC && (vma->vm_flags & VM_EXEC)))
- __flush_icache();
-}
-
-/* Flush all user pages on this cpu. */
-static inline void local_flush_tlb(void)
-{
- int rc = hv_flush_all(1); /* preserve global mappings */
- if (rc < 0)
- panic("hv_flush_all(1) failed: %d", rc);
- __flush_icache();
-}
-
-/*
- * Global pages have to be flushed a bit differently. Not a real
- * performance problem because this does not happen often.
- */
-static inline void local_flush_tlb_all(void)
-{
- int i;
- for (i = 0; ; ++i) {
- HV_VirtAddrRange r = hv_inquire_virtual(i);
- if (r.size == 0)
- break;
- local_flush_tlb_pages(NULL, r.start, PAGE_SIZE, r.size);
- local_flush_tlb_pages(NULL, r.start, HPAGE_SIZE, r.size);
- }
-}
-
-/*
- * TLB flushing:
- *
- * - flush_tlb() flushes the current mm struct TLBs
- * - flush_tlb_all() flushes all processes TLBs
- * - flush_tlb_mm(mm) flushes the specified mm context TLB's
- * - flush_tlb_page(vma, vmaddr) flushes one page
- * - flush_tlb_range(vma, start, end) flushes a range of pages
- * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- * - flush_tlb_others(cpumask, mm, va) flushes TLBs on other cpus
- *
- * Here (as in vm_area_struct), "end" means the first byte after
- * our end address.
- */
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
-extern void flush_tlb_current_task(void);
-extern void flush_tlb_mm(struct mm_struct *);
-extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void flush_tlb_page_mm(struct vm_area_struct *,
- struct mm_struct *, unsigned long);
-extern void flush_tlb_range(struct vm_area_struct *,
- unsigned long start, unsigned long end);
-
-#define flush_tlb() flush_tlb_current_task()
-
-#endif /* _ASM_TILE_TLBFLUSH_H */
diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h
deleted file mode 100644
index 635a0a4596f0..000000000000
--- a/arch/tile/include/asm/topology.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_TOPOLOGY_H
-#define _ASM_TILE_TOPOLOGY_H
-
-#ifdef CONFIG_NUMA
-
-#include <linux/cpumask.h>
-
-/* Mappings between logical cpu number and node number. */
-extern struct cpumask node_2_cpu_mask[];
-extern char cpu_2_node[];
-
-/* Returns the number of the node containing CPU 'cpu'. */
-static inline int cpu_to_node(int cpu)
-{
- return cpu_2_node[cpu];
-}
-
-/* Returns a bitmask of CPUs on Node 'node'. */
-static inline const struct cpumask *cpumask_of_node(int node)
-{
- return &node_2_cpu_mask[node];
-}
-
-/* For now, use numa node -1 for global allocation. */
-#define pcibus_to_node(bus) ((void)(bus), -1)
-
-#endif /* CONFIG_NUMA */
-
-#include <asm-generic/topology.h>
-
-#ifdef CONFIG_SMP
-#define topology_physical_package_id(cpu) ((void)(cpu), 0)
-#define topology_core_id(cpu) (cpu)
-#define topology_core_cpumask(cpu) ((void)(cpu), cpu_online_mask)
-#define topology_sibling_cpumask(cpu) cpumask_of(cpu)
-#endif
-
-#endif /* _ASM_TILE_TOPOLOGY_H */
diff --git a/arch/tile/include/asm/traps.h b/arch/tile/include/asm/traps.h
deleted file mode 100644
index 11c82270c1f5..000000000000
--- a/arch/tile/include/asm/traps.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_TRAPS_H
-#define _ASM_TILE_TRAPS_H
-
-#ifndef __ASSEMBLY__
-#include <arch/chip.h>
-
-/* mm/fault.c */
-void do_page_fault(struct pt_regs *, int fault_num,
- unsigned long address, unsigned long write);
-#if CHIP_HAS_TILE_DMA()
-void do_async_page_fault(struct pt_regs *);
-#endif
-
-#ifndef __tilegx__
-/*
- * We return this structure in registers to avoid having to write
- * additional save/restore code in the intvec.S caller.
- */
-struct intvec_state {
- void *handler;
- unsigned long vecnum;
- unsigned long fault_num;
- unsigned long info;
- unsigned long retval;
-};
-struct intvec_state do_page_fault_ics(struct pt_regs *regs, int fault_num,
- unsigned long address,
- unsigned long info);
-#endif
-
-/* kernel/traps.c */
-void do_trap(struct pt_regs *, int fault_num, unsigned long reason);
-void kernel_double_fault(int dummy, ulong pc, ulong lr, ulong sp, ulong r52);
-
-/* kernel/time.c */
-void do_timer_interrupt(struct pt_regs *, int fault_num);
-
-/* kernel/messaging.c */
-void hv_message_intr(struct pt_regs *, int intnum);
-
-#define TILE_NMI_DUMP_STACK 1 /* Dump stack for sysrq+'l' */
-
-/* kernel/process.c */
-void do_nmi_dump_stack(struct pt_regs *regs);
-
-/* kernel/traps.c */
-void do_nmi(struct pt_regs *, int fault_num, unsigned long reason);
-
-/* kernel/irq.c */
-void tile_dev_intr(struct pt_regs *, int intnum);
-
-#ifdef CONFIG_HARDWALL
-/* kernel/hardwall.c */
-void do_hardwall_trap(struct pt_regs *, int fault_num);
-#endif
-
-/* kernel/ptrace.c */
-void do_breakpoint(struct pt_regs *, int fault_num);
-
-
-#ifdef __tilegx__
-/* kernel/single_step.c */
-void gx_singlestep_handle(struct pt_regs *, int fault_num);
-
-/* kernel/intvec_64.S */
-void fill_ra_stack(void);
-
-/* Handle unalign data fixup. */
-extern void do_unaligned(struct pt_regs *regs, int vecnum);
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#ifdef __tilegx__
-/* 128 byte JIT per unalign fixup. */
-#define UNALIGN_JIT_SHIFT 7
-#endif
-
-#endif /* _ASM_TILE_TRAPS_H */
diff --git a/arch/tile/include/asm/uaccess.h b/arch/tile/include/asm/uaccess.h
deleted file mode 100644
index cb4fbe7e4f88..000000000000
--- a/arch/tile/include/asm/uaccess.h
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_UACCESS_H
-#define _ASM_TILE_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/mm.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not. If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-#define MAKE_MM_SEG(a) ((mm_segment_t) { (a) })
-
-#define KERNEL_DS MAKE_MM_SEG(-1UL)
-#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
-
-#define get_ds() (KERNEL_DS)
-#define get_fs() (current_thread_info()->addr_limit)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b) ((a).seg == (b).seg)
-
-#ifndef __tilegx__
-/*
- * We could allow mapping all 16 MB at 0xfc000000, but we set up a
- * special hack in arch_setup_additional_pages() to auto-create a mapping
- * for the first 16 KB, and it would seem strange to have different
- * user-accessible semantics for memory at 0xfc000000 and above 0xfc004000.
- */
-static inline int is_arch_mappable_range(unsigned long addr,
- unsigned long size)
-{
- return (addr >= MEM_USER_INTRPT &&
- addr < (MEM_USER_INTRPT + INTRPT_SIZE) &&
- size <= (MEM_USER_INTRPT + INTRPT_SIZE) - addr);
-}
-#define is_arch_mappable_range is_arch_mappable_range
-#else
-#define is_arch_mappable_range(addr, size) 0
-#endif
-
-/*
- * Note that using this definition ignores is_arch_mappable_range(),
- * so on tilepro code that uses user_addr_max() is constrained not
- * to reference the tilepro user-interrupt region.
- */
-#define user_addr_max() (current_thread_info()->addr_limit.seg)
-
-/*
- * Test whether a block of memory is a valid user space address.
- * Returns 0 if the range is valid, nonzero otherwise.
- */
-int __range_ok(unsigned long addr, unsigned long size);
-
-/**
- * access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
- * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- * to write to a block, it is always safe to read from it.
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns true (nonzero) if the memory block may be valid, false (zero)
- * if it is definitely invalid.
- *
- * Note that, depending on architecture, this function probably just
- * checks that the pointer is in the user space range - after calling
- * this function, memory access functions may still return -EFAULT.
- */
-#define access_ok(type, addr, size) ({ \
- __chk_user_ptr(addr); \
- likely(__range_ok((unsigned long)(addr), (size)) == 0); \
-})
-
-#include <asm/extable.h>
-
-/*
- * This is a type: either unsigned long, if the argument fits into
- * that type, or otherwise unsigned long long.
- */
-#define __inttype(x) \
- __typeof__(__builtin_choose_expr(sizeof(x) > sizeof(0UL), 0ULL, 0UL))
-
-/*
- * Support macros for __get_user().
- * Note that __get_user() and __put_user() assume proper alignment.
- */
-
-#ifdef __LP64__
-#define _ASM_PTR ".quad"
-#define _ASM_ALIGN ".align 8"
-#else
-#define _ASM_PTR ".long"
-#define _ASM_ALIGN ".align 4"
-#endif
-
-#define __get_user_asm(OP, x, ptr, ret) \
- asm volatile("1: {" #OP " %1, %2; movei %0, 0 }\n" \
- ".pushsection .fixup,\"ax\"\n" \
- "0: { movei %1, 0; movei %0, %3 }\n" \
- "j 9f\n" \
- ".section __ex_table,\"a\"\n" \
- _ASM_ALIGN "\n" \
- _ASM_PTR " 1b, 0b\n" \
- ".popsection\n" \
- "9:" \
- : "=r" (ret), "=r" (x) \
- : "r" (ptr), "i" (-EFAULT))
-
-#ifdef __tilegx__
-#define __get_user_1(x, ptr, ret) __get_user_asm(ld1u, x, ptr, ret)
-#define __get_user_2(x, ptr, ret) __get_user_asm(ld2u, x, ptr, ret)
-#define __get_user_4(x, ptr, ret) __get_user_asm(ld4s, x, ptr, ret)
-#define __get_user_8(x, ptr, ret) __get_user_asm(ld, x, ptr, ret)
-#else
-#define __get_user_1(x, ptr, ret) __get_user_asm(lb_u, x, ptr, ret)
-#define __get_user_2(x, ptr, ret) __get_user_asm(lh_u, x, ptr, ret)
-#define __get_user_4(x, ptr, ret) __get_user_asm(lw, x, ptr, ret)
-#ifdef __LITTLE_ENDIAN
-#define __lo32(a, b) a
-#define __hi32(a, b) b
-#else
-#define __lo32(a, b) b
-#define __hi32(a, b) a
-#endif
-#define __get_user_8(x, ptr, ret) \
- ({ \
- unsigned int __a, __b; \
- asm volatile("1: { lw %1, %3; addi %2, %3, 4 }\n" \
- "2: { lw %2, %2; movei %0, 0 }\n" \
- ".pushsection .fixup,\"ax\"\n" \
- "0: { movei %1, 0; movei %2, 0 }\n" \
- "{ movei %0, %4; j 9f }\n" \
- ".section __ex_table,\"a\"\n" \
- ".align 4\n" \
- ".word 1b, 0b\n" \
- ".word 2b, 0b\n" \
- ".popsection\n" \
- "9:" \
- : "=r" (ret), "=r" (__a), "=&r" (__b) \
- : "r" (ptr), "i" (-EFAULT)); \
- (x) = (__force __typeof(x))(__inttype(x)) \
- (((u64)__hi32(__a, __b) << 32) | \
- __lo32(__a, __b)); \
- })
-#endif
-
-extern int __get_user_bad(void)
- __attribute__((warning("sizeof __get_user argument not 1, 2, 4 or 8")));
-
-/**
- * __get_user: - Get a simple variable from user space, with less checking.
- * @x: Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple variable from user space to kernel
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- */
-#define __get_user(x, ptr) \
- ({ \
- int __ret; \
- typeof(x) _x; \
- __chk_user_ptr(ptr); \
- switch (sizeof(*(ptr))) { \
- case 1: __get_user_1(_x, ptr, __ret); break; \
- case 2: __get_user_2(_x, ptr, __ret); break; \
- case 4: __get_user_4(_x, ptr, __ret); break; \
- case 8: __get_user_8(_x, ptr, __ret); break; \
- default: __ret = __get_user_bad(); break; \
- } \
- (x) = (typeof(*(ptr))) _x; \
- __ret; \
- })
-
-/* Support macros for __put_user(). */
-
-#define __put_user_asm(OP, x, ptr, ret) \
- asm volatile("1: {" #OP " %1, %2; movei %0, 0 }\n" \
- ".pushsection .fixup,\"ax\"\n" \
- "0: { movei %0, %3; j 9f }\n" \
- ".section __ex_table,\"a\"\n" \
- _ASM_ALIGN "\n" \
- _ASM_PTR " 1b, 0b\n" \
- ".popsection\n" \
- "9:" \
- : "=r" (ret) \
- : "r" (ptr), "r" (x), "i" (-EFAULT))
-
-#ifdef __tilegx__
-#define __put_user_1(x, ptr, ret) __put_user_asm(st1, x, ptr, ret)
-#define __put_user_2(x, ptr, ret) __put_user_asm(st2, x, ptr, ret)
-#define __put_user_4(x, ptr, ret) __put_user_asm(st4, x, ptr, ret)
-#define __put_user_8(x, ptr, ret) __put_user_asm(st, x, ptr, ret)
-#else
-#define __put_user_1(x, ptr, ret) __put_user_asm(sb, x, ptr, ret)
-#define __put_user_2(x, ptr, ret) __put_user_asm(sh, x, ptr, ret)
-#define __put_user_4(x, ptr, ret) __put_user_asm(sw, x, ptr, ret)
-#define __put_user_8(x, ptr, ret) \
- ({ \
- u64 __x = (__force __inttype(x))(x); \
- int __lo = (int) __x, __hi = (int) (__x >> 32); \
- asm volatile("1: { sw %1, %2; addi %0, %1, 4 }\n" \
- "2: { sw %0, %3; movei %0, 0 }\n" \
- ".pushsection .fixup,\"ax\"\n" \
- "0: { movei %0, %4; j 9f }\n" \
- ".section __ex_table,\"a\"\n" \
- ".align 4\n" \
- ".word 1b, 0b\n" \
- ".word 2b, 0b\n" \
- ".popsection\n" \
- "9:" \
- : "=&r" (ret) \
- : "r" (ptr), "r" (__lo32(__lo, __hi)), \
- "r" (__hi32(__lo, __hi)), "i" (-EFAULT)); \
- })
-#endif
-
-extern int __put_user_bad(void)
- __attribute__((warning("sizeof __put_user argument not 1, 2, 4 or 8")));
-
-/**
- * __put_user: - Write a simple value into user space, with less checking.
- * @x: Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only. This function may sleep if pagefaults are
- * enabled.
- *
- * This macro copies a single simple value from kernel space to user
- * space. It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define __put_user(x, ptr) \
-({ \
- int __ret; \
- typeof(*(ptr)) _x = (x); \
- __chk_user_ptr(ptr); \
- switch (sizeof(*(ptr))) { \
- case 1: __put_user_1(_x, ptr, __ret); break; \
- case 2: __put_user_2(_x, ptr, __ret); break; \
- case 4: __put_user_4(_x, ptr, __ret); break; \
- case 8: __put_user_8(_x, ptr, __ret); break; \
- default: __ret = __put_user_bad(); break; \
- } \
- __ret; \
-})
-
-/*
- * The versions of get_user and put_user without initial underscores
- * check the address of their arguments to make sure they are not
- * in kernel space.
- */
-#define put_user(x, ptr) \
-({ \
- __typeof__(*(ptr)) __user *__Pu_addr = (ptr); \
- access_ok(VERIFY_WRITE, (__Pu_addr), sizeof(*(__Pu_addr))) ? \
- __put_user((x), (__Pu_addr)) : \
- -EFAULT; \
-})
-
-#define get_user(x, ptr) \
-({ \
- __typeof__(*(ptr)) const __user *__Gu_addr = (ptr); \
- access_ok(VERIFY_READ, (__Gu_addr), sizeof(*(__Gu_addr))) ? \
- __get_user((x), (__Gu_addr)) : \
- ((x) = 0, -EFAULT); \
-})
-
-extern unsigned long __must_check
-raw_copy_to_user(void __user *to, const void *from, unsigned long n);
-extern unsigned long __must_check
-raw_copy_from_user(void *to, const void __user *from, unsigned long n);
-#define INLINE_COPY_FROM_USER
-#define INLINE_COPY_TO_USER
-
-#ifdef __tilegx__
-extern unsigned long raw_copy_in_user(
- void __user *to, const void __user *from, unsigned long n);
-#endif
-
-
-extern long strnlen_user(const char __user *str, long n);
-extern long strncpy_from_user(char *dst, const char __user *src, long);
-
-/**
- * clear_user: - Zero a block of memory in user space.
- * @mem: Destination address, in user space.
- * @len: Number of bytes to zero.
- *
- * Zero a block of memory in user space.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-extern unsigned long clear_user_asm(void __user *mem, unsigned long len);
-static inline unsigned long __must_check __clear_user(
- void __user *mem, unsigned long len)
-{
- might_fault();
- return clear_user_asm(mem, len);
-}
-static inline unsigned long __must_check clear_user(
- void __user *mem, unsigned long len)
-{
- if (access_ok(VERIFY_WRITE, mem, len))
- return __clear_user(mem, len);
- return len;
-}
-
-/**
- * flush_user: - Flush a block of memory in user space from cache.
- * @mem: Destination address, in user space.
- * @len: Number of bytes to flush.
- *
- * Returns number of bytes that could not be flushed.
- * On success, this will be zero.
- */
-extern unsigned long flush_user_asm(void __user *mem, unsigned long len);
-static inline unsigned long __must_check __flush_user(
- void __user *mem, unsigned long len)
-{
- int retval;
-
- might_fault();
- retval = flush_user_asm(mem, len);
- mb_incoherent();
- return retval;
-}
-
-static inline unsigned long __must_check flush_user(
- void __user *mem, unsigned long len)
-{
- if (access_ok(VERIFY_WRITE, mem, len))
- return __flush_user(mem, len);
- return len;
-}
-
-/**
- * finv_user: - Flush-inval a block of memory in user space from cache.
- * @mem: Destination address, in user space.
- * @len: Number of bytes to invalidate.
- *
- * Returns number of bytes that could not be flush-invalidated.
- * On success, this will be zero.
- */
-extern unsigned long finv_user_asm(void __user *mem, unsigned long len);
-static inline unsigned long __must_check __finv_user(
- void __user *mem, unsigned long len)
-{
- int retval;
-
- might_fault();
- retval = finv_user_asm(mem, len);
- mb_incoherent();
- return retval;
-}
-static inline unsigned long __must_check finv_user(
- void __user *mem, unsigned long len)
-{
- if (access_ok(VERIFY_WRITE, mem, len))
- return __finv_user(mem, len);
- return len;
-}
-
-#endif /* _ASM_TILE_UACCESS_H */
diff --git a/arch/tile/include/asm/unaligned.h b/arch/tile/include/asm/unaligned.h
deleted file mode 100644
index 5a58a0d11449..000000000000
--- a/arch/tile/include/asm/unaligned.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_UNALIGNED_H
-#define _ASM_TILE_UNALIGNED_H
-
-/*
- * We could implement faster get_unaligned_[be/le]64 using the ldna
- * instruction on tilegx; however, we need to either copy all of the
- * other generic functions to here (which is pretty ugly) or else
- * modify both the generic code and other arch code to allow arch
- * specific unaligned data access functions. Given these functions
- * are not often called, we'll stick with the generic version.
- */
-#include <asm-generic/unaligned.h>
-
-/*
- * Is the kernel doing fixups of unaligned accesses? If <0, no kernel
- * intervention occurs and SIGBUS is delivered with no data address
- * info. If 0, the kernel single-steps the instruction to discover
- * the data address to provide with the SIGBUS. If 1, the kernel does
- * a fixup.
- */
-extern int unaligned_fixup;
-
-/* Is the kernel printing on each unaligned fixup? */
-extern int unaligned_printk;
-
-/* Number of unaligned fixups performed */
-extern unsigned int unaligned_fixup_count;
-
-#endif /* _ASM_TILE_UNALIGNED_H */
diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
deleted file mode 100644
index 940831fe9e94..000000000000
--- a/arch/tile/include/asm/unistd.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-/* In compat mode, we use sys_llseek() for compat_sys_llseek(). */
-#ifdef CONFIG_COMPAT
-#define __ARCH_WANT_SYS_LLSEEK
-#endif
-#define __ARCH_WANT_SYS_NEWFSTATAT
-#define __ARCH_WANT_SYS_CLONE
-#include <uapi/asm/unistd.h>
diff --git a/arch/tile/include/asm/user.h b/arch/tile/include/asm/user.h
deleted file mode 100644
index cbc8b4d5a5ce..000000000000
--- a/arch/tile/include/asm/user.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- */
-
-#ifndef _ASM_TILE_USER_H
-#define _ASM_TILE_USER_H
-
-/* This header is for a.out file formats, which TILE does not support. */
-
-#endif /* _ASM_TILE_USER_H */
diff --git a/arch/tile/include/asm/vdso.h b/arch/tile/include/asm/vdso.h
deleted file mode 100644
index 9b069692153f..000000000000
--- a/arch/tile/include/asm/vdso.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __TILE_VDSO_H__
-#define __TILE_VDSO_H__
-
-#include <linux/seqlock.h>
-#include <linux/types.h>
-
-/*
- * Note about the vdso_data structure:
- *
- * NEVER USE THEM IN USERSPACE CODE DIRECTLY. The layout of the
- * structure is supposed to be known only to the function in the vdso
- * itself and may change without notice.
- */
-
-struct vdso_data {
- seqcount_t tz_seq; /* Timezone seqlock */
- seqcount_t tb_seq; /* Timebase seqlock */
- __u64 cycle_last; /* TOD clock for xtime */
- __u64 mask; /* Cycle mask */
- __u32 mult; /* Cycle to nanosecond multiplier */
- __u32 shift; /* Cycle to nanosecond divisor (power of two) */
- __u64 wall_time_sec;
- __u64 wall_time_snsec;
- __u64 monotonic_time_sec;
- __u64 monotonic_time_snsec;
- __u64 wall_time_coarse_sec;
- __u64 wall_time_coarse_nsec;
- __u64 monotonic_time_coarse_sec;
- __u64 monotonic_time_coarse_nsec;
- __u32 tz_minuteswest; /* Minutes west of Greenwich */
- __u32 tz_dsttime; /* Type of dst correction */
-};
-
-extern struct vdso_data *vdso_data;
-
-/* __vdso_rt_sigreturn is defined with the addresses in the vdso page. */
-extern void __vdso_rt_sigreturn(void);
-
-extern int setup_vdso_pages(void);
-
-#endif /* __TILE_VDSO_H__ */
diff --git a/arch/tile/include/asm/vga.h b/arch/tile/include/asm/vga.h
deleted file mode 100644
index 7b46e754d611..000000000000
--- a/arch/tile/include/asm/vga.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Access to VGA videoram.
- */
-
-#ifndef _ASM_TILE_VGA_H
-#define _ASM_TILE_VGA_H
-
-#include <asm/io.h>
-
-#define VT_BUF_HAVE_RW
-
-static inline void scr_writew(u16 val, volatile u16 *addr)
-{
- __raw_writew(val, (volatile u16 __iomem *) addr);
-}
-
-static inline u16 scr_readw(volatile const u16 *addr)
-{
- return __raw_readw((volatile const u16 __iomem *) addr);
-}
-
-#define vga_readb(a) readb((u8 __iomem *)(a))
-#define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
-
-#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap(x, s))
-
-#endif
diff --git a/arch/tile/include/asm/word-at-a-time.h b/arch/tile/include/asm/word-at-a-time.h
deleted file mode 100644
index 2f2515867760..000000000000
--- a/arch/tile/include/asm/word-at-a-time.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_WORD_AT_A_TIME_H
-#define _ASM_WORD_AT_A_TIME_H
-
-#include <asm/byteorder.h>
-
-struct word_at_a_time { /* unused */ };
-#define WORD_AT_A_TIME_CONSTANTS {}
-
-/* Generate 0x01 byte values for zero bytes using a SIMD instruction. */
-static inline unsigned long has_zero(unsigned long val, unsigned long *data,
- const struct word_at_a_time *c)
-{
-#ifdef __tilegx__
- unsigned long mask = __insn_v1cmpeqi(val, 0);
-#else /* tilepro */
- unsigned long mask = __insn_seqib(val, 0);
-#endif
- *data = mask;
- return mask;
-}
-
-/* These operations are both nops. */
-#define prep_zero_mask(val, data, c) (data)
-#define create_zero_mask(data) (data)
-
-/* And this operation just depends on endianness. */
-static inline long find_zero(unsigned long mask)
-{
-#ifdef __BIG_ENDIAN
- return __builtin_clzl(mask) >> 3;
-#else
- return __builtin_ctzl(mask) >> 3;
-#endif
-}
-
-#ifdef __BIG_ENDIAN
-#define zero_bytemask(mask) (~1ul << (63 - __builtin_clzl(mask)))
-#else
-#define zero_bytemask(mask) ((2ul << __builtin_ctzl(mask)) - 1)
-#endif
-
-#endif /* _ASM_WORD_AT_A_TIME_H */
diff --git a/arch/tile/include/gxio/common.h b/arch/tile/include/gxio/common.h
deleted file mode 100644
index 724595a24d04..000000000000
--- a/arch/tile/include/gxio/common.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _GXIO_COMMON_H_
-#define _GXIO_COMMON_H_
-
-/*
- * Routines shared between the various GXIO device components.
- */
-
-#include <hv/iorpc.h>
-
-#include <linux/types.h>
-#include <linux/compiler.h>
-#include <linux/io.h>
-
-/* Define the standard gxio MMIO functions using kernel functions. */
-#define __gxio_mmio_read8(addr) readb(addr)
-#define __gxio_mmio_read16(addr) readw(addr)
-#define __gxio_mmio_read32(addr) readl(addr)
-#define __gxio_mmio_read64(addr) readq(addr)
-#define __gxio_mmio_write8(addr, val) writeb((val), (addr))
-#define __gxio_mmio_write16(addr, val) writew((val), (addr))
-#define __gxio_mmio_write32(addr, val) writel((val), (addr))
-#define __gxio_mmio_write64(addr, val) writeq((val), (addr))
-#define __gxio_mmio_read(addr) __gxio_mmio_read64(addr)
-#define __gxio_mmio_write(addr, val) __gxio_mmio_write64((addr), (val))
-
-#endif /* !_GXIO_COMMON_H_ */
diff --git a/arch/tile/include/gxio/dma_queue.h b/arch/tile/include/gxio/dma_queue.h
deleted file mode 100644
index c8fd47edba30..000000000000
--- a/arch/tile/include/gxio/dma_queue.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _GXIO_DMA_QUEUE_H_
-#define _GXIO_DMA_QUEUE_H_
-
-/*
- * DMA queue management APIs shared between TRIO and mPIPE.
- */
-
-#include <gxio/common.h>
-
-/* The credit counter lives in the high 32 bits. */
-#define DMA_QUEUE_CREDIT_SHIFT 32
-
-/*
- * State object that tracks a DMA queue's head and tail indices, as
- * well as the number of commands posted and completed. The
- * structure is accessed via a thread-safe, lock-free algorithm.
- */
-typedef struct {
- /*
- * Address of a MPIPE_EDMA_POST_REGION_VAL_t,
- * TRIO_PUSH_DMA_REGION_VAL_t, or TRIO_PULL_DMA_REGION_VAL_t
- * register. These register have identical encodings and provide
- * information about how many commands have been processed.
- */
- void *post_region_addr;
-
- /*
- * A lazily-updated count of how many edescs the hardware has
- * completed.
- */
- uint64_t hw_complete_count __attribute__ ((aligned(64)));
-
- /*
- * High 32 bits are a count of available egress command credits,
- * low 24 bits are the next egress "slot".
- */
- int64_t credits_and_next_index;
-
-} __gxio_dma_queue_t;
-
-/* Initialize a dma queue. */
-extern void __gxio_dma_queue_init(__gxio_dma_queue_t *dma_queue,
- void *post_region_addr,
- unsigned int num_entries);
-
-/*
- * Update the "credits_and_next_index" and "hw_complete_count" fields
- * based on pending hardware completions. Note that some other thread
- * may have already done this and, importantly, may still be in the
- * process of updating "credits_and_next_index".
- */
-extern void __gxio_dma_queue_update_credits(__gxio_dma_queue_t *dma_queue);
-
-/* Wait for credits to become available. */
-extern int64_t __gxio_dma_queue_wait_for_credits(__gxio_dma_queue_t *dma_queue,
- int64_t modifier);
-
-/* Reserve slots in the queue, optionally waiting for slots to become
- * available, and optionally returning a "completion_slot" suitable for
- * direct comparison to "hw_complete_count".
- */
-static inline int64_t __gxio_dma_queue_reserve(__gxio_dma_queue_t *dma_queue,
- unsigned int num, bool wait,
- bool completion)
-{
- uint64_t slot;
-
- /*
- * Try to reserve 'num' egress command slots. We do this by
- * constructing a constant that subtracts N credits and adds N to
- * the index, and using fetchaddgez to only apply it if the credits
- * count doesn't go negative.
- */
- int64_t modifier = (((int64_t)(-num)) << DMA_QUEUE_CREDIT_SHIFT) | num;
- int64_t old =
- __insn_fetchaddgez(&dma_queue->credits_and_next_index,
- modifier);
-
- if (unlikely(old + modifier < 0)) {
- /*
- * We're out of credits. Try once to get more by checking for
- * completed egress commands. If that fails, wait or fail.
- */
- __gxio_dma_queue_update_credits(dma_queue);
- old = __insn_fetchaddgez(&dma_queue->credits_and_next_index,
- modifier);
- if (old + modifier < 0) {
- if (wait)
- old = __gxio_dma_queue_wait_for_credits
- (dma_queue, modifier);
- else
- return GXIO_ERR_DMA_CREDITS;
- }
- }
-
- /* The bottom 24 bits of old encode the "slot". */
- slot = (old & 0xffffff);
-
- if (completion) {
- /*
- * A "completion_slot" is a "slot" which can be compared to
- * "hw_complete_count" at any time in the future. To convert
- * "slot" into a "completion_slot", we access "hw_complete_count"
- * once (knowing that we have reserved a slot, and thus, it will
- * be "basically" accurate), and combine its high 40 bits with
- * the 24 bit "slot", and handle "wrapping" by adding "1 << 24"
- * if the result is LESS than "hw_complete_count".
- */
- uint64_t complete;
- complete = READ_ONCE(dma_queue->hw_complete_count);
- slot |= (complete & 0xffffffffff000000);
- if (slot < complete)
- slot += 0x1000000;
- }
-
- /*
- * If any of our slots mod 256 were equivalent to 0, go ahead and
- * collect some egress credits, and update "hw_complete_count", and
- * make sure the index doesn't overflow into the credits.
- */
- if (unlikely(((old + num) & 0xff) < num)) {
- __gxio_dma_queue_update_credits(dma_queue);
-
- /* Make sure the index doesn't overflow into the credits. */
-#ifdef __BIG_ENDIAN__
- *(((uint8_t *)&dma_queue->credits_and_next_index) + 4) = 0;
-#else
- *(((uint8_t *)&dma_queue->credits_and_next_index) + 3) = 0;
-#endif
- }
-
- return slot;
-}
-
-/* Non-inlinable "__gxio_dma_queue_reserve(..., true)". */
-extern int64_t __gxio_dma_queue_reserve_aux(__gxio_dma_queue_t *dma_queue,
- unsigned int num, int wait);
-
-/* Check whether a particular "completion slot" has completed.
- *
- * Note that this function requires a "completion slot", and thus
- * cannot be used with the result of any "reserve_fast" function.
- */
-extern int __gxio_dma_queue_is_complete(__gxio_dma_queue_t *dma_queue,
- int64_t completion_slot, int update);
-
-#endif /* !_GXIO_DMA_QUEUE_H_ */
diff --git a/arch/tile/include/gxio/iorpc_globals.h b/arch/tile/include/gxio/iorpc_globals.h
deleted file mode 100644
index 52c721f8dad9..000000000000
--- a/arch/tile/include/gxio/iorpc_globals.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#ifndef __IORPC_LINUX_RPC_H__
-#define __IORPC_LINUX_RPC_H__
-
-#include <hv/iorpc.h>
-
-#include <linux/string.h>
-#include <linux/module.h>
-#include <asm/pgtable.h>
-
-#define IORPC_OP_ARM_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9000)
-#define IORPC_OP_CLOSE_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9001)
-#define IORPC_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
-#define IORPC_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
-
-int __iorpc_arm_pollfd(int fd, int pollfd_cookie);
-
-int __iorpc_close_pollfd(int fd, int pollfd_cookie);
-
-int __iorpc_get_mmio_base(int fd, HV_PTE *base);
-
-int __iorpc_check_mmio_offset(int fd, unsigned long offset, unsigned long size);
-
-#endif /* !__IORPC_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_mpipe.h b/arch/tile/include/gxio/iorpc_mpipe.h
deleted file mode 100644
index 4cda03de734f..000000000000
--- a/arch/tile/include/gxio/iorpc_mpipe.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#ifndef __GXIO_MPIPE_LINUX_RPC_H__
-#define __GXIO_MPIPE_LINUX_RPC_H__
-
-#include <hv/iorpc.h>
-
-#include <hv/drv_mpipe_intf.h>
-#include <asm/page.h>
-#include <gxio/kiorpc.h>
-#include <gxio/mpipe.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <asm/pgtable.h>
-
-#define GXIO_MPIPE_OP_ALLOC_BUFFER_STACKS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1200)
-#define GXIO_MPIPE_OP_INIT_BUFFER_STACK_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x1201)
-
-#define GXIO_MPIPE_OP_ALLOC_NOTIF_RINGS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1203)
-#define GXIO_MPIPE_OP_INIT_NOTIF_RING_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x1204)
-#define GXIO_MPIPE_OP_REQUEST_NOTIF_RING_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1205)
-#define GXIO_MPIPE_OP_ENABLE_NOTIF_RING_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1206)
-#define GXIO_MPIPE_OP_ALLOC_NOTIF_GROUPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1207)
-#define GXIO_MPIPE_OP_INIT_NOTIF_GROUP IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1208)
-#define GXIO_MPIPE_OP_ALLOC_BUCKETS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1209)
-#define GXIO_MPIPE_OP_INIT_BUCKET IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120a)
-#define GXIO_MPIPE_OP_ALLOC_EDMA_RINGS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120b)
-#define GXIO_MPIPE_OP_INIT_EDMA_RING_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x120c)
-
-#define GXIO_MPIPE_OP_COMMIT_RULES IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120f)
-#define GXIO_MPIPE_OP_REGISTER_CLIENT_MEMORY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1210)
-#define GXIO_MPIPE_OP_LINK_OPEN_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1211)
-#define GXIO_MPIPE_OP_LINK_CLOSE_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1212)
-#define GXIO_MPIPE_OP_LINK_SET_ATTR_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1213)
-
-#define GXIO_MPIPE_OP_GET_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x121e)
-#define GXIO_MPIPE_OP_SET_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x121f)
-#define GXIO_MPIPE_OP_ADJUST_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1220)
-#define GXIO_MPIPE_OP_CONFIG_EDMA_RING_BLKS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1221)
-#define GXIO_MPIPE_OP_ADJUST_TIMESTAMP_FREQ IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1222)
-#define GXIO_MPIPE_OP_ARM_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9000)
-#define GXIO_MPIPE_OP_CLOSE_POLLFD IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9001)
-#define GXIO_MPIPE_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
-#define GXIO_MPIPE_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
-
-int gxio_mpipe_alloc_buffer_stacks(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-int gxio_mpipe_init_buffer_stack_aux(gxio_mpipe_context_t *context,
- void *mem_va, size_t mem_size,
- unsigned int mem_flags, unsigned int stack,
- unsigned int buffer_size_enum);
-
-
-int gxio_mpipe_alloc_notif_rings(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-int gxio_mpipe_init_notif_ring_aux(gxio_mpipe_context_t *context, void *mem_va,
- size_t mem_size, unsigned int mem_flags,
- unsigned int ring);
-
-int gxio_mpipe_request_notif_ring_interrupt(gxio_mpipe_context_t *context,
- int inter_x, int inter_y,
- int inter_ipi, int inter_event,
- unsigned int ring);
-
-int gxio_mpipe_enable_notif_ring_interrupt(gxio_mpipe_context_t *context,
- unsigned int ring);
-
-int gxio_mpipe_alloc_notif_groups(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-int gxio_mpipe_init_notif_group(gxio_mpipe_context_t *context,
- unsigned int group,
- gxio_mpipe_notif_group_bits_t bits);
-
-int gxio_mpipe_alloc_buckets(gxio_mpipe_context_t *context, unsigned int count,
- unsigned int first, unsigned int flags);
-
-int gxio_mpipe_init_bucket(gxio_mpipe_context_t *context, unsigned int bucket,
- MPIPE_LBL_INIT_DAT_BSTS_TBL_t bucket_info);
-
-int gxio_mpipe_alloc_edma_rings(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-int gxio_mpipe_init_edma_ring_aux(gxio_mpipe_context_t *context, void *mem_va,
- size_t mem_size, unsigned int mem_flags,
- unsigned int ring, unsigned int channel);
-
-
-int gxio_mpipe_commit_rules(gxio_mpipe_context_t *context, const void *blob,
- size_t blob_size);
-
-int gxio_mpipe_register_client_memory(gxio_mpipe_context_t *context,
- unsigned int iotlb, HV_PTE pte,
- unsigned int flags);
-
-int gxio_mpipe_link_open_aux(gxio_mpipe_context_t *context,
- _gxio_mpipe_link_name_t name, unsigned int flags);
-
-int gxio_mpipe_link_close_aux(gxio_mpipe_context_t *context, int mac);
-
-int gxio_mpipe_link_set_attr_aux(gxio_mpipe_context_t *context, int mac,
- uint32_t attr, int64_t val);
-
-int gxio_mpipe_get_timestamp_aux(gxio_mpipe_context_t *context, uint64_t *sec,
- uint64_t *nsec, uint64_t *cycles);
-
-int gxio_mpipe_set_timestamp_aux(gxio_mpipe_context_t *context, uint64_t sec,
- uint64_t nsec, uint64_t cycles);
-
-int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t *context,
- int64_t nsec);
-
-int gxio_mpipe_adjust_timestamp_freq(gxio_mpipe_context_t *context,
- int32_t ppb);
-
-int gxio_mpipe_arm_pollfd(gxio_mpipe_context_t *context, int pollfd_cookie);
-
-int gxio_mpipe_close_pollfd(gxio_mpipe_context_t *context, int pollfd_cookie);
-
-int gxio_mpipe_get_mmio_base(gxio_mpipe_context_t *context, HV_PTE *base);
-
-int gxio_mpipe_check_mmio_offset(gxio_mpipe_context_t *context,
- unsigned long offset, unsigned long size);
-
-#endif /* !__GXIO_MPIPE_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_mpipe_info.h b/arch/tile/include/gxio/iorpc_mpipe_info.h
deleted file mode 100644
index f0b04284468b..000000000000
--- a/arch/tile/include/gxio/iorpc_mpipe_info.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#ifndef __GXIO_MPIPE_INFO_LINUX_RPC_H__
-#define __GXIO_MPIPE_INFO_LINUX_RPC_H__
-
-#include <hv/iorpc.h>
-
-#include <hv/drv_mpipe_intf.h>
-#include <asm/page.h>
-#include <gxio/kiorpc.h>
-#include <gxio/mpipe.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <asm/pgtable.h>
-
-
-#define GXIO_MPIPE_INFO_OP_INSTANCE_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1250)
-#define GXIO_MPIPE_INFO_OP_ENUMERATE_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1251)
-#define GXIO_MPIPE_INFO_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
-#define GXIO_MPIPE_INFO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
-
-
-int gxio_mpipe_info_instance_aux(gxio_mpipe_info_context_t *context,
- _gxio_mpipe_link_name_t name);
-
-int gxio_mpipe_info_enumerate_aux(gxio_mpipe_info_context_t *context,
- unsigned int idx,
- _gxio_mpipe_link_name_t *name,
- _gxio_mpipe_link_mac_t *mac);
-
-int gxio_mpipe_info_get_mmio_base(gxio_mpipe_info_context_t *context,
- HV_PTE *base);
-
-int gxio_mpipe_info_check_mmio_offset(gxio_mpipe_info_context_t *context,
- unsigned long offset, unsigned long size);
-
-#endif /* !__GXIO_MPIPE_INFO_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_trio.h b/arch/tile/include/gxio/iorpc_trio.h
deleted file mode 100644
index 376a4f771167..000000000000
--- a/arch/tile/include/gxio/iorpc_trio.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#ifndef __GXIO_TRIO_LINUX_RPC_H__
-#define __GXIO_TRIO_LINUX_RPC_H__
-
-#include <hv/iorpc.h>
-
-#include <hv/drv_trio_intf.h>
-#include <gxio/trio.h>
-#include <gxio/kiorpc.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <asm/pgtable.h>
-
-#define GXIO_TRIO_OP_DEALLOC_ASID IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1400)
-#define GXIO_TRIO_OP_ALLOC_ASIDS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1401)
-
-#define GXIO_TRIO_OP_ALLOC_MEMORY_MAPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1404)
-
-#define GXIO_TRIO_OP_ALLOC_SCATTER_QUEUES IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140e)
-#define GXIO_TRIO_OP_ALLOC_PIO_REGIONS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1412)
-
-#define GXIO_TRIO_OP_INIT_PIO_REGION_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1414)
-
-#define GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141e)
-#define GXIO_TRIO_OP_GET_PORT_PROPERTY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141f)
-#define GXIO_TRIO_OP_CONFIG_LEGACY_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1420)
-#define GXIO_TRIO_OP_CONFIG_MSI_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1421)
-
-#define GXIO_TRIO_OP_SET_MPS_MRS IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1423)
-#define GXIO_TRIO_OP_FORCE_RC_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1424)
-#define GXIO_TRIO_OP_FORCE_EP_LINK_UP IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1425)
-#define GXIO_TRIO_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
-#define GXIO_TRIO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
-
-int gxio_trio_alloc_asids(gxio_trio_context_t *context, unsigned int count,
- unsigned int first, unsigned int flags);
-
-
-int gxio_trio_alloc_memory_maps(gxio_trio_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-
-int gxio_trio_alloc_scatter_queues(gxio_trio_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-int gxio_trio_alloc_pio_regions(gxio_trio_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-int gxio_trio_init_pio_region_aux(gxio_trio_context_t *context,
- unsigned int pio_region, unsigned int mac,
- uint32_t bus_address_hi, unsigned int flags);
-
-
-int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t *context,
- unsigned int map, unsigned long va,
- uint64_t size, unsigned int asid,
- unsigned int mac, uint64_t bus_address,
- unsigned int node,
- unsigned int order_mode);
-
-int gxio_trio_get_port_property(gxio_trio_context_t *context,
- struct pcie_trio_ports_property *trio_ports);
-
-int gxio_trio_config_legacy_intr(gxio_trio_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event,
- unsigned int mac, unsigned int intx);
-
-int gxio_trio_config_msi_intr(gxio_trio_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event,
- unsigned int mac, unsigned int mem_map,
- uint64_t mem_map_base, uint64_t mem_map_limit,
- unsigned int asid);
-
-
-int gxio_trio_set_mps_mrs(gxio_trio_context_t *context, uint16_t mps,
- uint16_t mrs, unsigned int mac);
-
-int gxio_trio_force_rc_link_up(gxio_trio_context_t *context, unsigned int mac);
-
-int gxio_trio_force_ep_link_up(gxio_trio_context_t *context, unsigned int mac);
-
-int gxio_trio_get_mmio_base(gxio_trio_context_t *context, HV_PTE *base);
-
-int gxio_trio_check_mmio_offset(gxio_trio_context_t *context,
- unsigned long offset, unsigned long size);
-
-#endif /* !__GXIO_TRIO_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_uart.h b/arch/tile/include/gxio/iorpc_uart.h
deleted file mode 100644
index 55429d48ea56..000000000000
--- a/arch/tile/include/gxio/iorpc_uart.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#ifndef __GXIO_UART_LINUX_RPC_H__
-#define __GXIO_UART_LINUX_RPC_H__
-
-#include <hv/iorpc.h>
-
-#include <hv/drv_uart_intf.h>
-#include <gxio/uart.h>
-#include <gxio/kiorpc.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <asm/pgtable.h>
-
-#define GXIO_UART_OP_CFG_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1900)
-#define GXIO_UART_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
-#define GXIO_UART_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
-
-int gxio_uart_cfg_interrupt(gxio_uart_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event);
-
-int gxio_uart_get_mmio_base(gxio_uart_context_t *context, HV_PTE *base);
-
-int gxio_uart_check_mmio_offset(gxio_uart_context_t *context,
- unsigned long offset, unsigned long size);
-
-#endif /* !__GXIO_UART_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_usb_host.h b/arch/tile/include/gxio/iorpc_usb_host.h
deleted file mode 100644
index 79962a97de8e..000000000000
--- a/arch/tile/include/gxio/iorpc_usb_host.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* This file is machine-generated; DO NOT EDIT! */
-#ifndef __GXIO_USB_HOST_LINUX_RPC_H__
-#define __GXIO_USB_HOST_LINUX_RPC_H__
-
-#include <hv/iorpc.h>
-
-#include <hv/drv_usb_host_intf.h>
-#include <asm/page.h>
-#include <gxio/kiorpc.h>
-#include <gxio/usb_host.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <asm/pgtable.h>
-
-#define GXIO_USB_HOST_OP_CFG_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1800)
-#define GXIO_USB_HOST_OP_REGISTER_CLIENT_MEMORY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1801)
-#define GXIO_USB_HOST_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
-#define GXIO_USB_HOST_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
-
-int gxio_usb_host_cfg_interrupt(gxio_usb_host_context_t *context, int inter_x,
- int inter_y, int inter_ipi, int inter_event);
-
-int gxio_usb_host_register_client_memory(gxio_usb_host_context_t *context,
- HV_PTE pte, unsigned int flags);
-
-int gxio_usb_host_get_mmio_base(gxio_usb_host_context_t *context,
- HV_PTE *base);
-
-int gxio_usb_host_check_mmio_offset(gxio_usb_host_context_t *context,
- unsigned long offset, unsigned long size);
-
-#endif /* !__GXIO_USB_HOST_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/kiorpc.h b/arch/tile/include/gxio/kiorpc.h
deleted file mode 100644
index ee5820979ff3..000000000000
--- a/arch/tile/include/gxio/kiorpc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Support routines for kernel IORPC drivers.
- */
-
-#ifndef _GXIO_KIORPC_H
-#define _GXIO_KIORPC_H
-
-#include <linux/types.h>
-#include <asm/page.h>
-#include <arch/chip.h>
-
-#if CHIP_HAS_MMIO()
-void __iomem *iorpc_ioremap(int hv_fd, resource_size_t offset,
- unsigned long size);
-#endif
-
-#endif /* _GXIO_KIORPC_H */
diff --git a/arch/tile/include/gxio/mpipe.h b/arch/tile/include/gxio/mpipe.h
deleted file mode 100644
index 73e83a187866..000000000000
--- a/arch/tile/include/gxio/mpipe.h
+++ /dev/null
@@ -1,1871 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _GXIO_MPIPE_H_
-#define _GXIO_MPIPE_H_
-
-/*
- *
- * An API for allocating, configuring, and manipulating mPIPE hardware
- * resources.
- */
-
-#include <gxio/common.h>
-#include <gxio/dma_queue.h>
-
-#include <linux/time.h>
-
-#include <arch/mpipe_def.h>
-#include <arch/mpipe_shm.h>
-
-#include <hv/drv_mpipe_intf.h>
-#include <hv/iorpc.h>
-
-/*
- *
- * The TILE-Gx mPIPE&tm; shim provides Ethernet connectivity, packet
- * classification, and packet load balancing services. The
- * gxio_mpipe_ API, declared in <gxio/mpipe.h>, allows applications to
- * allocate mPIPE IO channels, configure packet distribution
- * parameters, and send and receive Ethernet packets. The API is
- * designed to be a minimal wrapper around the mPIPE hardware, making
- * system calls only where necessary to preserve inter-process
- * protection guarantees.
- *
- * The APIs described below allow the programmer to allocate and
- * configure mPIPE resources. As described below, the mPIPE is a
- * single shared hardware device that provides partitionable resources
- * that are shared between all applications in the system. The
- * gxio_mpipe_ API allows userspace code to make resource request
- * calls to the hypervisor, which in turns keeps track of the
- * resources in use by all applications, maintains protection
- * guarantees, and resets resources upon application shutdown.
- *
- * We strongly recommend reading the mPIPE section of the IO Device
- * Guide (UG404) before working with this API. Most functions in the
- * gxio_mpipe_ API are directly analogous to hardware interfaces and
- * the documentation assumes that the reader understands those
- * hardware interfaces.
- *
- * @section mpipe__ingress mPIPE Ingress Hardware Resources
- *
- * The mPIPE ingress hardware provides extensive hardware offload for
- * tasks like packet header parsing, load balancing, and memory
- * management. This section provides a brief introduction to the
- * hardware components and the gxio_mpipe_ calls used to manage them;
- * see the IO Device Guide for a much more detailed description of the
- * mPIPE's capabilities.
- *
- * When a packet arrives at one of the mPIPE's Ethernet MACs, it is
- * assigned a channel number indicating which MAC received it. It
- * then proceeds through the following hardware pipeline:
- *
- * @subsection mpipe__classification Classification
- *
- * A set of classification processors run header parsing code on each
- * incoming packet, extracting information including the destination
- * MAC address, VLAN, Ethernet type, and five-tuple hash. Some of
- * this information is then used to choose which buffer stack will be
- * used to hold the packet, and which bucket will be used by the load
- * balancer to determine which application will receive the packet.
- *
- * The rules by which the buffer stack and bucket are chosen can be
- * configured via the @ref gxio_mpipe_classifier API. A given app can
- * specify multiple rules, each one specifying a bucket range, and a
- * set of buffer stacks, to be used for packets matching the rule.
- * Each rule can optionally specify a restricted set of channels,
- * VLANs, and/or dMACs, in which it is interested. By default, a
- * given rule starts out matching all channels associated with the
- * mPIPE context's set of open links; all VLANs; and all dMACs.
- * Subsequent restrictions can then be added.
- *
- * @subsection mpipe__load_balancing Load Balancing
- *
- * The mPIPE load balancer is responsible for choosing the NotifRing
- * to which the packet will be delivered. This decision is based on
- * the bucket number indicated by the classification program. In
- * general, the bucket number is based on some number of low bits of
- * the packet's flow hash (applications that aren't interested in flow
- * hashing use a single bucket). Each load balancer bucket keeps a
- * record of the NotifRing to which packets directed to that bucket
- * are currently being delivered. Based on the bucket's load
- * balancing mode (@ref gxio_mpipe_bucket_mode_t), the load balancer
- * either forwards the packet to the previously assigned NotifRing or
- * decides to choose a new NotifRing. If a new NotifRing is required,
- * the load balancer chooses the least loaded ring in the NotifGroup
- * associated with the bucket.
- *
- * The load balancer is a shared resource. Each application needs to
- * explicitly allocate NotifRings, NotifGroups, and buckets, using
- * gxio_mpipe_alloc_notif_rings(), gxio_mpipe_alloc_notif_groups(),
- * and gxio_mpipe_alloc_buckets(). Then the application needs to
- * configure them using gxio_mpipe_init_notif_ring() and
- * gxio_mpipe_init_notif_group_and_buckets().
- *
- * @subsection mpipe__buffers Buffer Selection and Packet Delivery
- *
- * Once the load balancer has chosen the destination NotifRing, the
- * mPIPE DMA engine pops at least one buffer off of the 'buffer stack'
- * chosen by the classification program and DMAs the packet data into
- * that buffer. Each buffer stack provides a hardware-accelerated
- * stack of data buffers with the same size. If the packet data is
- * larger than the buffers provided by the chosen buffer stack, the
- * mPIPE hardware pops off multiple buffers and chains the packet data
- * through a multi-buffer linked list. Once the packet data is
- * delivered to the buffer(s), the mPIPE hardware writes the
- * ::gxio_mpipe_idesc_t metadata object (calculated by the classifier)
- * into the NotifRing and increments the number of packets delivered
- * to that ring.
- *
- * Applications can push buffers onto a buffer stack by calling
- * gxio_mpipe_push_buffer() or by egressing a packet with the
- * ::gxio_mpipe_edesc_t::hwb bit set, indicating that the egressed
- * buffers should be returned to the stack.
- *
- * Applications can allocate and initialize buffer stacks with the
- * gxio_mpipe_alloc_buffer_stacks() and gxio_mpipe_init_buffer_stack()
- * APIs.
- *
- * The application must also register the memory pages that will hold
- * packets. This requires calling gxio_mpipe_register_page() for each
- * memory page that will hold packets allocated by the application for
- * a given buffer stack. Since each buffer stack is limited to 16
- * registered pages, it may be necessary to use huge pages, or even
- * extremely huge pages, to hold all the buffers.
- *
- * @subsection mpipe__iqueue NotifRings
- *
- * Each NotifRing is a region of shared memory, allocated by the
- * application, to which the mPIPE delivers packet descriptors
- * (::gxio_mpipe_idesc_t). The application can allocate them via
- * gxio_mpipe_alloc_notif_rings(). The application can then either
- * explicitly initialize them with gxio_mpipe_init_notif_ring() and
- * then read from them manually, or can make use of the convenience
- * wrappers provided by @ref gxio_mpipe_wrappers.
- *
- * @section mpipe__egress mPIPE Egress Hardware
- *
- * Applications use eDMA rings to queue packets for egress. The
- * application can allocate them via gxio_mpipe_alloc_edma_rings().
- * The application can then either explicitly initialize them with
- * gxio_mpipe_init_edma_ring() and then write to them manually, or
- * can make use of the convenience wrappers provided by
- * @ref gxio_mpipe_wrappers.
- *
- * @section gxio__shortcomings Plans for Future API Revisions
- *
- * The API defined here is only an initial version of the mPIPE API.
- * Future plans include:
- *
- * - Higher level wrapper functions to provide common initialization
- * patterns. This should help users start writing mPIPE programs
- * without having to learn the details of the hardware.
- *
- * - Support for reset and deallocation of resources, including
- * cleanup upon application shutdown.
- *
- * - Support for calling these APIs in the BME.
- *
- * - Support for IO interrupts.
- *
- * - Clearer definitions of thread safety guarantees.
- *
- * @section gxio__mpipe_examples Examples
- *
- * See the following mPIPE example programs for more information about
- * allocating mPIPE resources and using them in real applications:
- *
- * - @ref mpipe/ingress/app.c : Receiving packets.
- *
- * - @ref mpipe/forward/app.c : Forwarding packets.
- *
- * Note that there are several more examples.
- */
-
-/* Flags that can be passed to resource allocation functions. */
-enum gxio_mpipe_alloc_flags_e {
- /* Require an allocation to start at a specified resource index. */
- GXIO_MPIPE_ALLOC_FIXED = HV_MPIPE_ALLOC_FIXED,
-};
-
-/* Flags that can be passed to memory registration functions. */
-enum gxio_mpipe_mem_flags_e {
- /* Do not fill L3 when writing, and invalidate lines upon egress. */
- GXIO_MPIPE_MEM_FLAG_NT_HINT = IORPC_MEM_BUFFER_FLAG_NT_HINT,
-
- /* L3 cache fills should only populate IO cache ways. */
- GXIO_MPIPE_MEM_FLAG_IO_PIN = IORPC_MEM_BUFFER_FLAG_IO_PIN,
-};
-
-/* An ingress packet descriptor. When a packet arrives, the mPIPE
- * hardware generates this structure and writes it into a NotifRing.
- */
-typedef MPIPE_PDESC_t gxio_mpipe_idesc_t;
-
-/* An egress command descriptor. Applications write this structure
- * into eDMA rings and the hardware performs the indicated operation
- * (normally involving egressing some bytes). Note that egressing a
- * single packet may involve multiple egress command descriptors.
- */
-typedef MPIPE_EDMA_DESC_t gxio_mpipe_edesc_t;
-
-/*
- * Max # of mpipe instances. 2 currently.
- */
-#define GXIO_MPIPE_INSTANCE_MAX HV_MPIPE_INSTANCE_MAX
-
-#define NR_MPIPE_MAX GXIO_MPIPE_INSTANCE_MAX
-
-/* Get the "va" field from an "idesc".
- *
- * This is the address at which the ingress hardware copied the first
- * byte of the packet.
- *
- * If the classifier detected a custom header, then this will point to
- * the custom header, and gxio_mpipe_idesc_get_l2_start() will point
- * to the actual L2 header.
- *
- * Note that this value may be misleading if "idesc->be" is set.
- *
- * @param idesc An ingress packet descriptor.
- */
-static inline unsigned char *gxio_mpipe_idesc_get_va(gxio_mpipe_idesc_t *idesc)
-{
- return (unsigned char *)(long)idesc->va;
-}
-
-/* Get the "xfer_size" from an "idesc".
- *
- * This is the actual number of packet bytes transferred into memory
- * by the hardware.
- *
- * Note that this value may be misleading if "idesc->be" is set.
- *
- * @param idesc An ingress packet descriptor.
- *
- * ISSUE: Is this the best name for this?
- * FIXME: Add more docs about chaining, clipping, etc.
- */
-static inline unsigned int gxio_mpipe_idesc_get_xfer_size(gxio_mpipe_idesc_t
- *idesc)
-{
- return idesc->l2_size;
-}
-
-/* Get the "l2_offset" from an "idesc".
- *
- * Extremely customized classifiers might not support this function.
- *
- * This is the number of bytes between the "va" and the L2 header.
- *
- * The L2 header consists of a destination mac address, a source mac
- * address, and an initial ethertype. Various initial ethertypes
- * allow encoding extra information in the L2 header, often including
- * a vlan, and/or a new ethertype.
- *
- * Note that the "l2_offset" will be non-zero if (and only if) the
- * classifier processed a custom header for the packet.
- *
- * @param idesc An ingress packet descriptor.
- */
-static inline uint8_t gxio_mpipe_idesc_get_l2_offset(gxio_mpipe_idesc_t *idesc)
-{
- return (idesc->custom1 >> 32) & 0xFF;
-}
-
-/* Get the "l2_start" from an "idesc".
- *
- * This is simply gxio_mpipe_idesc_get_va() plus
- * gxio_mpipe_idesc_get_l2_offset().
- *
- * @param idesc An ingress packet descriptor.
- */
-static inline unsigned char *gxio_mpipe_idesc_get_l2_start(gxio_mpipe_idesc_t
- *idesc)
-{
- unsigned char *va = gxio_mpipe_idesc_get_va(idesc);
- return va + gxio_mpipe_idesc_get_l2_offset(idesc);
-}
-
-/* Get the "l2_length" from an "idesc".
- *
- * This is simply gxio_mpipe_idesc_get_xfer_size() minus
- * gxio_mpipe_idesc_get_l2_offset().
- *
- * @param idesc An ingress packet descriptor.
- */
-static inline unsigned int gxio_mpipe_idesc_get_l2_length(gxio_mpipe_idesc_t
- *idesc)
-{
- unsigned int xfer_size = idesc->l2_size;
- return xfer_size - gxio_mpipe_idesc_get_l2_offset(idesc);
-}
-
-/* A context object used to manage mPIPE hardware resources. */
-typedef struct {
-
- /* File descriptor for calling up to Linux (and thus the HV). */
- int fd;
-
- /* Corresponding mpipe instance #. */
- int instance;
-
- /* The VA at which configuration registers are mapped. */
- char *mmio_cfg_base;
-
- /* The VA at which IDMA, EDMA, and buffer manager are mapped. */
- char *mmio_fast_base;
-
- /* The "initialized" buffer stacks. */
- gxio_mpipe_rules_stacks_t __stacks;
-
-} gxio_mpipe_context_t;
-
-/* This is only used internally, but it's most easily made visible here. */
-typedef gxio_mpipe_context_t gxio_mpipe_info_context_t;
-
-/* Initialize an mPIPE context.
- *
- * This function allocates an mPIPE "service domain" and maps the MMIO
- * registers into the caller's VA space.
- *
- * @param context Context object to be initialized.
- * @param mpipe_instance Instance number of mPIPE shim to be controlled via
- * context.
- */
-extern int gxio_mpipe_init(gxio_mpipe_context_t *context,
- unsigned int mpipe_instance);
-
-/* Destroy an mPIPE context.
- *
- * This function frees the mPIPE "service domain" and unmaps the MMIO
- * registers from the caller's VA space.
- *
- * If a user process exits without calling this routine, the kernel
- * will destroy the mPIPE context as part of process teardown.
- *
- * @param context Context object to be destroyed.
- */
-extern int gxio_mpipe_destroy(gxio_mpipe_context_t *context);
-
-/*****************************************************************
- * Buffer Stacks *
- ******************************************************************/
-
-/* Allocate a set of buffer stacks.
- *
- * The return value is NOT interesting if count is zero.
- *
- * @param context An initialized mPIPE context.
- * @param count Number of stacks required.
- * @param first Index of first stack if ::GXIO_MPIPE_ALLOC_FIXED flag is set,
- * otherwise ignored.
- * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
- * @return Index of first allocated buffer stack, or
- * ::GXIO_MPIPE_ERR_NO_BUFFER_STACK if allocation failed.
- */
-extern int gxio_mpipe_alloc_buffer_stacks(gxio_mpipe_context_t *context,
- unsigned int count,
- unsigned int first,
- unsigned int flags);
-
-/* Enum codes for buffer sizes supported by mPIPE. */
-typedef enum {
- /* 128 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_128 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_128,
- /* 256 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_256 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_256,
- /* 512 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_512 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_512,
- /* 1024 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_1024 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1024,
- /* 1664 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_1664 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1664,
- /* 4096 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_4096 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_4096,
- /* 10368 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_10368 =
- MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_10368,
- /* 16384 byte packet data buffer. */
- GXIO_MPIPE_BUFFER_SIZE_16384 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_16384
-} gxio_mpipe_buffer_size_enum_t;
-
-/* Convert a buffer size in bytes into a buffer size enum. */
-extern gxio_mpipe_buffer_size_enum_t
-gxio_mpipe_buffer_size_to_buffer_size_enum(size_t size);
-
-/* Convert a buffer size enum into a buffer size in bytes. */
-extern size_t
-gxio_mpipe_buffer_size_enum_to_buffer_size(gxio_mpipe_buffer_size_enum_t
- buffer_size_enum);
-
-/* Calculate the number of bytes required to store a given number of
- * buffers in the memory registered with a buffer stack via
- * gxio_mpipe_init_buffer_stack().
- */
-extern size_t gxio_mpipe_calc_buffer_stack_bytes(unsigned long buffers);
-
-/* Initialize a buffer stack. This function binds a region of memory
- * to be used by the hardware for storing buffer addresses pushed via
- * gxio_mpipe_push_buffer() or as the result of sending a buffer out
- * the egress with the 'push to stack when done' bit set. Once this
- * function returns, the memory region's contents may be arbitrarily
- * modified by the hardware at any time and software should not access
- * the memory region again.
- *
- * @param context An initialized mPIPE context.
- * @param stack The buffer stack index.
- * @param buffer_size_enum The size of each buffer in the buffer stack,
- * as an enum.
- * @param mem The address of the buffer stack. This memory must be
- * physically contiguous and aligned to a 64kB boundary.
- * @param mem_size The size of the buffer stack, in bytes.
- * @param mem_flags ::gxio_mpipe_mem_flags_e memory flags.
- * @return Zero on success, ::GXIO_MPIPE_ERR_INVAL_BUFFER_SIZE if
- * buffer_size_enum is invalid, ::GXIO_MPIPE_ERR_BAD_BUFFER_STACK if
- * stack has not been allocated.
- */
-extern int gxio_mpipe_init_buffer_stack(gxio_mpipe_context_t *context,
- unsigned int stack,
- gxio_mpipe_buffer_size_enum_t
- buffer_size_enum, void *mem,
- size_t mem_size,
- unsigned int mem_flags);
-
-/* Push a buffer onto a previously initialized buffer stack.
- *
- * The size of the buffer being pushed must match the size that was
- * registered with gxio_mpipe_init_buffer_stack(). All packet buffer
- * addresses are 128-byte aligned; the low 7 bits of the specified
- * buffer address will be ignored.
- *
- * @param context An initialized mPIPE context.
- * @param stack The buffer stack index.
- * @param buffer The buffer (the low seven bits are ignored).
- */
-static inline void gxio_mpipe_push_buffer(gxio_mpipe_context_t *context,
- unsigned int stack, void *buffer)
-{
- MPIPE_BSM_REGION_ADDR_t offset = { {0} };
- MPIPE_BSM_REGION_VAL_t val = { {0} };
-
- /*
- * The mmio_fast_base region starts at the IDMA region, so subtract
- * off that initial offset.
- */
- offset.region =
- MPIPE_MMIO_ADDR__REGION_VAL_BSM -
- MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
- offset.stack = stack;
-
-#if __SIZEOF_POINTER__ == 4
- val.va = ((ulong) buffer) >> MPIPE_BSM_REGION_VAL__VA_SHIFT;
-#else
- val.va = ((long)buffer) >> MPIPE_BSM_REGION_VAL__VA_SHIFT;
-#endif
-
- __gxio_mmio_write(context->mmio_fast_base + offset.word, val.word);
-}
-
-/* Pop a buffer off of a previously initialized buffer stack.
- *
- * @param context An initialized mPIPE context.
- * @param stack The buffer stack index.
- * @return The buffer, or NULL if the stack is empty.
- */
-static inline void *gxio_mpipe_pop_buffer(gxio_mpipe_context_t *context,
- unsigned int stack)
-{
- MPIPE_BSM_REGION_ADDR_t offset = { {0} };
-
- /*
- * The mmio_fast_base region starts at the IDMA region, so subtract
- * off that initial offset.
- */
- offset.region =
- MPIPE_MMIO_ADDR__REGION_VAL_BSM -
- MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
- offset.stack = stack;
-
- while (1) {
- /*
- * Case 1: val.c == ..._UNCHAINED, va is non-zero.
- * Case 2: val.c == ..._INVALID, va is zero.
- * Case 3: val.c == ..._NOT_RDY, va is zero.
- */
- MPIPE_BSM_REGION_VAL_t val;
- val.word =
- __gxio_mmio_read(context->mmio_fast_base +
- offset.word);
-
- /*
- * Handle case 1 and 2 by returning the buffer (or NULL).
- * Handle case 3 by waiting for the prefetch buffer to refill.
- */
- if (val.c != MPIPE_EDMA_DESC_WORD1__C_VAL_NOT_RDY)
- return (void *)((unsigned long)val.
- va << MPIPE_BSM_REGION_VAL__VA_SHIFT);
- }
-}
-
-/*****************************************************************
- * NotifRings *
- ******************************************************************/
-
-/* Allocate a set of NotifRings.
- *
- * The return value is NOT interesting if count is zero.
- *
- * Note that NotifRings are allocated in chunks, so allocating one at
- * a time is much less efficient than allocating several at once.
- *
- * @param context An initialized mPIPE context.
- * @param count Number of NotifRings required.
- * @param first Index of first NotifRing if ::GXIO_MPIPE_ALLOC_FIXED flag
- * is set, otherwise ignored.
- * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
- * @return Index of first allocated buffer NotifRing, or
- * ::GXIO_MPIPE_ERR_NO_NOTIF_RING if allocation failed.
- */
-extern int gxio_mpipe_alloc_notif_rings(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-/* Initialize a NotifRing, using the given memory and size.
- *
- * @param context An initialized mPIPE context.
- * @param ring The NotifRing index.
- * @param mem A physically contiguous region of memory to be filled
- * with a ring of ::gxio_mpipe_idesc_t structures.
- * @param mem_size Number of bytes in the ring. Must be 128, 512,
- * 2048, or 65536 * sizeof(gxio_mpipe_idesc_t).
- * @param mem_flags ::gxio_mpipe_mem_flags_e memory flags.
- *
- * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_NOTIF_RING or
- * ::GXIO_ERR_INVAL_MEMORY_SIZE on failure.
- */
-extern int gxio_mpipe_init_notif_ring(gxio_mpipe_context_t *context,
- unsigned int ring,
- void *mem, size_t mem_size,
- unsigned int mem_flags);
-
-/* Configure an interrupt to be sent to a tile on incoming NotifRing
- * traffic. Once an interrupt is sent for a particular ring, no more
- * will be sent until gxio_mica_enable_notif_ring_interrupt() is called.
- *
- * @param context An initialized mPIPE context.
- * @param x X coordinate of interrupt target tile.
- * @param y Y coordinate of interrupt target tile.
- * @param i Index of the IPI register which will receive the interrupt.
- * @param e Specific event which will be set in the target IPI register when
- * the interrupt occurs.
- * @param ring The NotifRing index.
- * @return Zero on success, GXIO_ERR_INVAL if params are out of range.
- */
-extern int gxio_mpipe_request_notif_ring_interrupt(gxio_mpipe_context_t
- *context, int x, int y,
- int i, int e,
- unsigned int ring);
-
-/* Enable an interrupt on incoming NotifRing traffic.
- *
- * @param context An initialized mPIPE context.
- * @param ring The NotifRing index.
- * @return Zero on success, GXIO_ERR_INVAL if params are out of range.
- */
-extern int gxio_mpipe_enable_notif_ring_interrupt(gxio_mpipe_context_t
- *context, unsigned int ring);
-
-/* Map all of a client's memory via the given IOTLB.
- * @param context An initialized mPIPE context.
- * @param iotlb IOTLB index.
- * @param pte Page table entry.
- * @param flags Flags.
- * @return Zero on success, or a negative error code.
- */
-extern int gxio_mpipe_register_client_memory(gxio_mpipe_context_t *context,
- unsigned int iotlb, HV_PTE pte,
- unsigned int flags);
-
-/*****************************************************************
- * Notif Groups *
- ******************************************************************/
-
-/* Allocate a set of NotifGroups.
- *
- * The return value is NOT interesting if count is zero.
- *
- * @param context An initialized mPIPE context.
- * @param count Number of NotifGroups required.
- * @param first Index of first NotifGroup if ::GXIO_MPIPE_ALLOC_FIXED flag
- * is set, otherwise ignored.
- * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
- * @return Index of first allocated buffer NotifGroup, or
- * ::GXIO_MPIPE_ERR_NO_NOTIF_GROUP if allocation failed.
- */
-extern int gxio_mpipe_alloc_notif_groups(gxio_mpipe_context_t *context,
- unsigned int count,
- unsigned int first,
- unsigned int flags);
-
-/* Add a NotifRing to a NotifGroup. This only sets a bit in the
- * application's 'group' object; the hardware NotifGroup can be
- * initialized by passing 'group' to gxio_mpipe_init_notif_group() or
- * gxio_mpipe_init_notif_group_and_buckets().
- */
-static inline void
-gxio_mpipe_notif_group_add_ring(gxio_mpipe_notif_group_bits_t *bits, int ring)
-{
- bits->ring_mask[ring / 64] |= (1ull << (ring % 64));
-}
-
-/* Set a particular NotifGroup bitmask. Since the load balancer
- * makes decisions based on both bucket and NotifGroup state, most
- * applications should use gxio_mpipe_init_notif_group_and_buckets()
- * rather than using this function to configure just a NotifGroup.
- */
-extern int gxio_mpipe_init_notif_group(gxio_mpipe_context_t *context,
- unsigned int group,
- gxio_mpipe_notif_group_bits_t bits);
-
-/*****************************************************************
- * Load Balancer *
- ******************************************************************/
-
-/* Allocate a set of load balancer buckets.
- *
- * The return value is NOT interesting if count is zero.
- *
- * Note that buckets are allocated in chunks, so allocating one at
- * a time is much less efficient than allocating several at once.
- *
- * Note that the buckets are actually divided into two sub-ranges, of
- * different sizes, and different chunk sizes, and the range you get
- * by default is determined by the size of the request. Allocations
- * cannot span the two sub-ranges.
- *
- * @param context An initialized mPIPE context.
- * @param count Number of buckets required.
- * @param first Index of first bucket if ::GXIO_MPIPE_ALLOC_FIXED flag is set,
- * otherwise ignored.
- * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
- * @return Index of first allocated buffer bucket, or
- * ::GXIO_MPIPE_ERR_NO_BUCKET if allocation failed.
- */
-extern int gxio_mpipe_alloc_buckets(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-/* The legal modes for gxio_mpipe_bucket_info_t and
- * gxio_mpipe_init_notif_group_and_buckets().
- *
- * All modes except ::GXIO_MPIPE_BUCKET_ROUND_ROBIN expect that the user
- * will allocate a power-of-two number of buckets and initialize them
- * to the same mode. The classifier program then uses the appropriate
- * number of low bits from the incoming packet's flow hash to choose a
- * load balancer bucket. Based on that bucket's load balancing mode,
- * reference count, and currently active NotifRing, the load balancer
- * chooses the NotifRing to which the packet will be delivered.
- */
-typedef enum {
- /* All packets for a bucket go to the same NotifRing unless the
- * NotifRing gets full, in which case packets will be dropped. If
- * the bucket reference count ever reaches zero, a new NotifRing may
- * be chosen.
- */
- GXIO_MPIPE_BUCKET_DYNAMIC_FLOW_AFFINITY =
- MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_DFA,
-
- /* All packets for a bucket always go to the same NotifRing.
- */
- GXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY =
- MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_FIXED,
-
- /* All packets for a bucket go to the least full NotifRing in the
- * group, providing load balancing round robin behavior.
- */
- GXIO_MPIPE_BUCKET_ROUND_ROBIN =
- MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_ALWAYS_PICK,
-
- /* All packets for a bucket go to the same NotifRing unless the
- * NotifRing gets full, at which point the bucket starts using the
- * least full NotifRing in the group. If all NotifRings in the
- * group are full, packets will be dropped.
- */
- GXIO_MPIPE_BUCKET_STICKY_FLOW_LOCALITY =
- MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY,
-
- /* All packets for a bucket go to the same NotifRing unless the
- * NotifRing gets full, or a random timer fires, at which point the
- * bucket starts using the least full NotifRing in the group. If
- * all NotifRings in the group are full, packets will be dropped.
- * WARNING: This mode is BROKEN on chips with fewer than 64 tiles.
- */
- GXIO_MPIPE_BUCKET_PREFER_FLOW_LOCALITY =
- MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY_RAND,
-
-} gxio_mpipe_bucket_mode_t;
-
-/* Copy a set of bucket initialization values into the mPIPE
- * hardware. Since the load balancer makes decisions based on both
- * bucket and NotifGroup state, most applications should use
- * gxio_mpipe_init_notif_group_and_buckets() rather than using this
- * function to configure a single bucket.
- *
- * @param context An initialized mPIPE context.
- * @param bucket Bucket index to be initialized.
- * @param bucket_info Initial reference count, NotifRing index, and mode.
- * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_BUCKET on failure.
- */
-extern int gxio_mpipe_init_bucket(gxio_mpipe_context_t *context,
- unsigned int bucket,
- gxio_mpipe_bucket_info_t bucket_info);
-
-/* Initializes a group and range of buckets and range of rings such
- * that the load balancer runs a particular load balancing function.
- *
- * First, the group is initialized with the given rings.
- *
- * Second, each bucket is initialized with the mode and group, and a
- * ring chosen round-robin from the given rings.
- *
- * Normally, the classifier picks a bucket, and then the load balancer
- * picks a ring, based on the bucket's mode, group, and current ring,
- * possibly updating the bucket's ring.
- *
- * @param context An initialized mPIPE context.
- * @param group The group.
- * @param ring The first ring.
- * @param num_rings The number of rings.
- * @param bucket The first bucket.
- * @param num_buckets The number of buckets.
- * @param mode The load balancing mode.
- *
- * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_BUCKET,
- * ::GXIO_MPIPE_ERR_BAD_NOTIF_GROUP, or
- * ::GXIO_MPIPE_ERR_BAD_NOTIF_RING on failure.
- */
-extern int gxio_mpipe_init_notif_group_and_buckets(gxio_mpipe_context_t
- *context,
- unsigned int group,
- unsigned int ring,
- unsigned int num_rings,
- unsigned int bucket,
- unsigned int num_buckets,
- gxio_mpipe_bucket_mode_t
- mode);
-
-/* Return credits to a NotifRing and/or bucket.
- *
- * @param context An initialized mPIPE context.
- * @param ring The NotifRing index, or -1.
- * @param bucket The bucket, or -1.
- * @param count The number of credits to return.
- */
-static inline void gxio_mpipe_credit(gxio_mpipe_context_t *context,
- int ring, int bucket, unsigned int count)
-{
- /* NOTE: Fancy struct initialization would break "C89" header test. */
-
- MPIPE_IDMA_RELEASE_REGION_ADDR_t offset = { {0} };
- MPIPE_IDMA_RELEASE_REGION_VAL_t val = { {0} };
-
- /*
- * The mmio_fast_base region starts at the IDMA region, so subtract
- * off that initial offset.
- */
- offset.region =
- MPIPE_MMIO_ADDR__REGION_VAL_IDMA -
- MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
- offset.ring = ring;
- offset.bucket = bucket;
- offset.ring_enable = (ring >= 0);
- offset.bucket_enable = (bucket >= 0);
- val.count = count;
-
- __gxio_mmio_write(context->mmio_fast_base + offset.word, val.word);
-}
-
-/*****************************************************************
- * Egress Rings *
- ******************************************************************/
-
-/* Allocate a set of eDMA rings.
- *
- * The return value is NOT interesting if count is zero.
- *
- * @param context An initialized mPIPE context.
- * @param count Number of eDMA rings required.
- * @param first Index of first eDMA ring if ::GXIO_MPIPE_ALLOC_FIXED flag
- * is set, otherwise ignored.
- * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
- * @return Index of first allocated buffer eDMA ring, or
- * ::GXIO_MPIPE_ERR_NO_EDMA_RING if allocation failed.
- */
-extern int gxio_mpipe_alloc_edma_rings(gxio_mpipe_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-/* Initialize an eDMA ring, using the given memory and size.
- *
- * @param context An initialized mPIPE context.
- * @param ering The eDMA ring index.
- * @param channel The channel to use. This must be one of the channels
- * associated with the context's set of open links.
- * @param mem A physically contiguous region of memory to be filled
- * with a ring of ::gxio_mpipe_edesc_t structures.
- * @param mem_size Number of bytes in the ring. Must be 512, 2048,
- * 8192 or 65536, times 16 (i.e. sizeof(gxio_mpipe_edesc_t)).
- * @param mem_flags ::gxio_mpipe_mem_flags_e memory flags.
- *
- * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_EDMA_RING or
- * ::GXIO_ERR_INVAL_MEMORY_SIZE on failure.
- */
-extern int gxio_mpipe_init_edma_ring(gxio_mpipe_context_t *context,
- unsigned int ering, unsigned int channel,
- void *mem, size_t mem_size,
- unsigned int mem_flags);
-
-/* Set the "max_blks", "min_snf_blks", and "db" fields of
- * ::MPIPE_EDMA_RG_INIT_DAT_THRESH_t for a given edma ring.
- *
- * The global pool of dynamic blocks will be automatically adjusted.
- *
- * This function should not be called after any egress has been done
- * on the edma ring.
- *
- * Most applications should just use gxio_mpipe_equeue_set_snf_size().
- *
- * @param context An initialized mPIPE context.
- * @param ering The eDMA ring index.
- * @param max_blks The number of blocks to dedicate to the ring
- * (normally min_snf_blks + 1). Must be greater than min_snf_blocks.
- * @param min_snf_blks The number of blocks which must be stored
- * prior to starting to send the packet (normally 12).
- * @param db Whether to allow use of dynamic blocks by the ring
- * (normally 1).
- *
- * @return 0 on success, negative on error.
- */
-extern int gxio_mpipe_config_edma_ring_blks(gxio_mpipe_context_t *context,
- unsigned int ering,
- unsigned int max_blks,
- unsigned int min_snf_blks,
- unsigned int db);
-
-/*****************************************************************
- * Classifier Program *
- ******************************************************************/
-
-/*
- *
- * Functions for loading or configuring the mPIPE classifier program.
- *
- * The mPIPE classification processors all run a special "classifier"
- * program which, for each incoming packet, parses the packet headers,
- * encodes some packet metadata in the "idesc", and either drops the
- * packet, or picks a notif ring to handle the packet, and a buffer
- * stack to contain the packet, usually based on the channel, VLAN,
- * dMAC, flow hash, and packet size, under the guidance of the "rules"
- * API described below.
- *
- * @section gxio_mpipe_classifier_default Default Classifier
- *
- * The MDE provides a simple "default" classifier program. It is
- * shipped as source in "$TILERA_ROOT/src/sys/mpipe/classifier.c",
- * which serves as its official documentation. It is shipped as a
- * binary program in "$TILERA_ROOT/tile/boot/classifier", which is
- * automatically included in bootroms created by "tile-monitor", and
- * is automatically loaded by the hypervisor at boot time.
- *
- * The L2 analysis handles LLC packets, SNAP packets, and "VLAN
- * wrappers" (keeping the outer VLAN).
- *
- * The L3 analysis handles IPv4 and IPv6, dropping packets with bad
- * IPv4 header checksums, requesting computation of a TCP/UDP checksum
- * if appropriate, and hashing the dest and src IP addresses, plus the
- * ports for TCP/UDP packets, into the flow hash. No special analysis
- * is done for "fragmented" packets or "tunneling" protocols. Thus,
- * the first fragment of a fragmented TCP/UDP packet is hashed using
- * src/dest IP address and ports and all subsequent fragments are only
- * hashed according to src/dest IP address.
- *
- * The L3 analysis handles other packets too, hashing the dMAC
- * smac into a flow hash.
- *
- * The channel, VLAN, and dMAC used to pick a "rule" (see the
- * "rules" APIs below), which in turn is used to pick a buffer stack
- * (based on the packet size) and a bucket (based on the flow hash).
- *
- * To receive traffic matching a particular (channel/VLAN/dMAC
- * pattern, an application should allocate its own buffer stacks and
- * load balancer buckets, and map traffic to those stacks and buckets,
- * as decribed by the "rules" API below.
- *
- * Various packet metadata is encoded in the idesc. The flow hash is
- * four bytes at 0x0C. The VLAN is two bytes at 0x10. The ethtype is
- * two bytes at 0x12. The l3 start is one byte at 0x14. The l4 start
- * is one byte at 0x15 for IPv4 and IPv6 packets, and otherwise zero.
- * The protocol is one byte at 0x16 for IPv4 and IPv6 packets, and
- * otherwise zero.
- *
- * @section gxio_mpipe_classifier_custom Custom Classifiers.
- *
- * A custom classifier may be created using "tile-mpipe-cc" with a
- * customized version of the default classifier sources.
- *
- * The custom classifier may be included in bootroms using the
- * "--classifier" option to "tile-monitor", or loaded dynamically
- * using gxio_mpipe_classifier_load_from_file().
- *
- * Be aware that "extreme" customizations may break the assumptions of
- * the "rules" APIs described below, but simple customizations, such
- * as adding new packet metadata, should be fine.
- */
-
-/* A set of classifier rules, plus a context. */
-typedef struct {
-
- /* The context. */
- gxio_mpipe_context_t *context;
-
- /* The actual rules. */
- gxio_mpipe_rules_list_t list;
-
-} gxio_mpipe_rules_t;
-
-/* Initialize a classifier program rules list.
- *
- * This function can be called on a previously initialized rules list
- * to discard any previously added rules.
- *
- * @param rules Rules list to initialize.
- * @param context An initialized mPIPE context.
- */
-extern void gxio_mpipe_rules_init(gxio_mpipe_rules_t *rules,
- gxio_mpipe_context_t *context);
-
-/* Begin a new rule on the indicated rules list.
- *
- * Note that an empty rule matches all packets, but an empty rule list
- * matches no packets.
- *
- * @param rules Rules list to which new rule is appended.
- * @param bucket First load balancer bucket to which packets will be
- * delivered.
- * @param num_buckets Number of buckets (must be a power of two) across
- * which packets will be distributed based on the "flow hash".
- * @param stacks Either NULL, to assign each packet to the smallest
- * initialized buffer stack which does not induce chaining (and to
- * drop packets which exceed the largest initialized buffer stack
- * buffer size), or an array, with each entry indicating which buffer
- * stack should be used for packets up to that size (with 255
- * indicating that those packets should be dropped).
- * @return 0 on success, or a negative error code on failure.
- */
-extern int gxio_mpipe_rules_begin(gxio_mpipe_rules_t *rules,
- unsigned int bucket,
- unsigned int num_buckets,
- gxio_mpipe_rules_stacks_t *stacks);
-
-/* Set the headroom of the current rule.
- *
- * @param rules Rules list whose current rule will be modified.
- * @param headroom The headroom.
- * @return 0 on success, or a negative error code on failure.
- */
-extern int gxio_mpipe_rules_set_headroom(gxio_mpipe_rules_t *rules,
- uint8_t headroom);
-
-/* Indicate that packets from a particular channel can be delivered
- * to the buckets and buffer stacks associated with the current rule.
- *
- * Channels added must be associated with links opened by the mPIPE context
- * used in gxio_mpipe_rules_init(). A rule with no channels is equivalent
- * to a rule naming all such associated channels.
- *
- * @param rules Rules list whose current rule will be modified.
- * @param channel The channel to add.
- * @return 0 on success, or a negative error code on failure.
- */
-extern int gxio_mpipe_rules_add_channel(gxio_mpipe_rules_t *rules,
- unsigned int channel);
-
-/* Commit rules.
- *
- * The rules are sent to the hypervisor, where they are combined with
- * the rules from other apps, and used to program the hardware classifier.
- *
- * Note that if this function returns an error, then the rules will NOT
- * have been committed, even if the error is due to interactions with
- * rules from another app.
- *
- * @param rules Rules list to commit.
- * @return 0 on success, or a negative error code on failure.
- */
-extern int gxio_mpipe_rules_commit(gxio_mpipe_rules_t *rules);
-
-/*****************************************************************
- * Ingress Queue Wrapper *
- ******************************************************************/
-
-/*
- *
- * Convenience functions for receiving packets from a NotifRing and
- * sending packets via an eDMA ring.
- *
- * The mpipe ingress and egress hardware uses shared memory packet
- * descriptors to describe packets that have arrived on ingress or
- * are destined for egress. These descriptors are stored in shared
- * memory ring buffers and written or read by hardware as necessary.
- * The gxio library provides wrapper functions that manage the head and
- * tail pointers for these rings, allowing the user to easily read or
- * write packet descriptors.
- *
- * The initialization interface for ingress and egress rings is quite
- * similar. For example, to create an ingress queue, the user passes
- * a ::gxio_mpipe_iqueue_t state object, a ring number from
- * gxio_mpipe_alloc_notif_rings(), and the address of memory to hold a
- * ring buffer to the gxio_mpipe_iqueue_init() function. The function
- * returns success when the state object has been initialized and the
- * hardware configured to deliver packets to the specified ring
- * buffer. Similarly, gxio_mpipe_equeue_init() takes a
- * ::gxio_mpipe_equeue_t state object, a ring number from
- * gxio_mpipe_alloc_edma_rings(), and a shared memory buffer.
- *
- * @section gxio_mpipe_iqueue Working with Ingress Queues
- *
- * Once initialized, the gxio_mpipe_iqueue_t API provides two flows
- * for getting the ::gxio_mpipe_idesc_t packet descriptor associated
- * with incoming packets. The simplest is to call
- * gxio_mpipe_iqueue_get() or gxio_mpipe_iqueue_try_get(). These
- * functions copy the oldest packet descriptor out of the NotifRing and
- * into a descriptor provided by the caller. They also immediately
- * inform the hardware that a descriptor has been processed.
- *
- * For applications with stringent performance requirements, higher
- * efficiency can be achieved by avoiding the packet descriptor copy
- * and processing multiple descriptors at once. The
- * gxio_mpipe_iqueue_peek() and gxio_mpipe_iqueue_try_peek() functions
- * allow such optimizations. These functions provide a pointer to the
- * next valid ingress descriptor in the NotifRing's shared memory ring
- * buffer, and a count of how many contiguous descriptors are ready to
- * be processed. The application can then process any number of those
- * descriptors in place, calling gxio_mpipe_iqueue_consume() to inform
- * the hardware after each one has been processed.
- *
- * @section gxio_mpipe_equeue Working with Egress Queues
- *
- * Similarly, the egress queue API provides a high-performance
- * interface plus a simple wrapper for use in posting
- * ::gxio_mpipe_edesc_t egress packet descriptors. The simple
- * version, gxio_mpipe_equeue_put(), allows the programmer to wait for
- * an eDMA ring slot to become available and write a single descriptor
- * into the ring.
- *
- * Alternatively, you can reserve slots in the eDMA ring using
- * gxio_mpipe_equeue_reserve() or gxio_mpipe_equeue_try_reserve(), and
- * then fill in each slot using gxio_mpipe_equeue_put_at(). This
- * capability can be used to amortize the cost of reserving slots
- * across several packets. It also allows gather operations to be
- * performed on a shared equeue, by ensuring that the edescs for all
- * the fragments are all contiguous in the eDMA ring.
- *
- * The gxio_mpipe_equeue_reserve() and gxio_mpipe_equeue_try_reserve()
- * functions return a 63-bit "completion slot", which is actually a
- * sequence number, the low bits of which indicate the ring buffer
- * index and the high bits the number of times the application has
- * gone around the egress ring buffer. The extra bits allow an
- * application to check for egress completion by calling
- * gxio_mpipe_equeue_is_complete() to see whether a particular 'slot'
- * number has finished. Given the maximum packet rates of the Gx
- * processor, the 63-bit slot number will never wrap.
- *
- * In practice, most applications use the ::gxio_mpipe_edesc_t::hwb
- * bit to indicate that the buffers containing egress packet data
- * should be pushed onto a buffer stack when egress is complete. Such
- * applications generally do not need to know when an egress operation
- * completes (since there is no need to free a buffer post-egress),
- * and thus can use the optimized gxio_mpipe_equeue_reserve_fast() or
- * gxio_mpipe_equeue_try_reserve_fast() functions, which return a 24
- * bit "slot", instead of a 63-bit "completion slot".
- *
- * Once a slot has been "reserved", it MUST be filled. If the
- * application reserves a slot and then decides that it does not
- * actually need it, it can set the ::gxio_mpipe_edesc_t::ns (no send)
- * bit on the descriptor passed to gxio_mpipe_equeue_put_at() to
- * indicate that no data should be sent. This technique can also be
- * used to drop an incoming packet, instead of forwarding it, since
- * any buffer will still be pushed onto the buffer stack when the
- * egress descriptor is processed.
- */
-
-/* A convenient interface to a NotifRing, for use by a single thread.
- */
-typedef struct {
-
- /* The context. */
- gxio_mpipe_context_t *context;
-
- /* The actual NotifRing. */
- gxio_mpipe_idesc_t *idescs;
-
- /* The number of entries. */
- unsigned long num_entries;
-
- /* The number of entries minus one. */
- unsigned long mask_num_entries;
-
- /* The log2() of the number of entries. */
- unsigned long log2_num_entries;
-
- /* The next entry. */
- unsigned int head;
-
- /* The NotifRing id. */
- unsigned int ring;
-
-#ifdef __BIG_ENDIAN__
- /* The number of byteswapped entries. */
- unsigned int swapped;
-#endif
-
-} gxio_mpipe_iqueue_t;
-
-/* Initialize an "iqueue".
- *
- * Takes the iqueue plus the same args as gxio_mpipe_init_notif_ring().
- */
-extern int gxio_mpipe_iqueue_init(gxio_mpipe_iqueue_t *iqueue,
- gxio_mpipe_context_t *context,
- unsigned int ring,
- void *mem, size_t mem_size,
- unsigned int mem_flags);
-
-/* Advance over some old entries in an iqueue.
- *
- * Please see the documentation for gxio_mpipe_iqueue_consume().
- *
- * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
- * @param count The number of entries to advance over.
- */
-static inline void gxio_mpipe_iqueue_advance(gxio_mpipe_iqueue_t *iqueue,
- int count)
-{
- /* Advance with proper wrap. */
- int head = iqueue->head + count;
- iqueue->head =
- (head & iqueue->mask_num_entries) +
- (head >> iqueue->log2_num_entries);
-
-#ifdef __BIG_ENDIAN__
- /* HACK: Track swapped entries. */
- iqueue->swapped -= count;
-#endif
-}
-
-/* Release the ring and bucket for an old entry in an iqueue.
- *
- * Releasing the ring allows more packets to be delivered to the ring.
- *
- * Releasing the bucket allows flows using the bucket to be moved to a
- * new ring when using GXIO_MPIPE_BUCKET_DYNAMIC_FLOW_AFFINITY.
- *
- * This function is shorthand for "gxio_mpipe_credit(iqueue->context,
- * iqueue->ring, idesc->bucket_id, 1)", and it may be more convenient
- * to make that underlying call, using those values, instead of
- * tracking the entire "idesc".
- *
- * If packet processing is deferred, optimal performance requires that
- * the releasing be deferred as well.
- *
- * Please see the documentation for gxio_mpipe_iqueue_consume().
- *
- * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
- * @param idesc The descriptor which was processed.
- */
-static inline void gxio_mpipe_iqueue_release(gxio_mpipe_iqueue_t *iqueue,
- gxio_mpipe_idesc_t *idesc)
-{
- gxio_mpipe_credit(iqueue->context, iqueue->ring, idesc->bucket_id, 1);
-}
-
-/* Consume a packet from an "iqueue".
- *
- * After processing packets peeked at via gxio_mpipe_iqueue_peek()
- * or gxio_mpipe_iqueue_try_peek(), you must call this function, or
- * gxio_mpipe_iqueue_advance() plus gxio_mpipe_iqueue_release(), to
- * advance over those entries, and release their rings and buckets.
- *
- * You may call this function as each packet is processed, or you can
- * wait until several packets have been processed.
- *
- * Note that if you are using a single bucket, and you are handling
- * batches of N packets, then you can replace several calls to this
- * function with calls to "gxio_mpipe_iqueue_advance(iqueue, N)" and
- * "gxio_mpipe_credit(iqueue->context, iqueue->ring, bucket, N)".
- *
- * Note that if your classifier sets "idesc->nr", then you should
- * explicitly call "gxio_mpipe_iqueue_advance(iqueue, idesc)" plus
- * "gxio_mpipe_credit(iqueue->context, iqueue->ring, -1, 1)", to
- * avoid incorrectly crediting the (unused) bucket.
- *
- * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
- * @param idesc The descriptor which was processed.
- */
-static inline void gxio_mpipe_iqueue_consume(gxio_mpipe_iqueue_t *iqueue,
- gxio_mpipe_idesc_t *idesc)
-{
- gxio_mpipe_iqueue_advance(iqueue, 1);
- gxio_mpipe_iqueue_release(iqueue, idesc);
-}
-
-/* Peek at the next packet(s) in an "iqueue", without waiting.
- *
- * If no packets are available, fills idesc_ref with NULL, and then
- * returns ::GXIO_MPIPE_ERR_IQUEUE_EMPTY. Otherwise, fills idesc_ref
- * with the address of the next valid packet descriptor, and returns
- * the maximum number of valid descriptors which can be processed.
- * You may process fewer descriptors if desired.
- *
- * Call gxio_mpipe_iqueue_consume() on each packet once it has been
- * processed (or dropped), to allow more packets to be delivered.
- *
- * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
- * @param idesc_ref A pointer to a packet descriptor pointer.
- * @return The (positive) number of packets which can be processed,
- * or ::GXIO_MPIPE_ERR_IQUEUE_EMPTY if no packets are available.
- */
-static inline int gxio_mpipe_iqueue_try_peek(gxio_mpipe_iqueue_t *iqueue,
- gxio_mpipe_idesc_t **idesc_ref)
-{
- gxio_mpipe_idesc_t *next;
-
- uint64_t head = iqueue->head;
- uint64_t tail = __gxio_mmio_read(iqueue->idescs);
-
- /* Available entries. */
- uint64_t avail =
- (tail >= head) ? (tail - head) : (iqueue->num_entries - head);
-
- if (avail == 0) {
- *idesc_ref = NULL;
- return GXIO_MPIPE_ERR_IQUEUE_EMPTY;
- }
-
- next = &iqueue->idescs[head];
-
- /* ISSUE: Is this helpful? */
- __insn_prefetch(next);
-
-#ifdef __BIG_ENDIAN__
- /* HACK: Swap new entries directly in memory. */
- {
- int i, j;
- for (i = iqueue->swapped; i < avail; i++) {
- for (j = 0; j < 8; j++)
- next[i].words[j] =
- __builtin_bswap64(next[i].words[j]);
- }
- iqueue->swapped = avail;
- }
-#endif
-
- *idesc_ref = next;
-
- return avail;
-}
-
-/* Drop a packet by pushing its buffer (if appropriate).
- *
- * NOTE: The caller must still call gxio_mpipe_iqueue_consume() if idesc
- * came from gxio_mpipe_iqueue_try_peek() or gxio_mpipe_iqueue_peek().
- *
- * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
- * @param idesc A packet descriptor.
- */
-static inline void gxio_mpipe_iqueue_drop(gxio_mpipe_iqueue_t *iqueue,
- gxio_mpipe_idesc_t *idesc)
-{
- /* FIXME: Handle "chaining" properly. */
-
- if (!idesc->be) {
- unsigned char *va = gxio_mpipe_idesc_get_va(idesc);
- gxio_mpipe_push_buffer(iqueue->context, idesc->stack_idx, va);
- }
-}
-
-/*****************************************************************
- * Egress Queue Wrapper *
- ******************************************************************/
-
-/* A convenient, thread-safe interface to an eDMA ring. */
-typedef struct {
-
- /* State object for tracking head and tail pointers. */
- __gxio_dma_queue_t dma_queue;
-
- /* The ring entries. */
- gxio_mpipe_edesc_t *edescs;
-
- /* The number of entries minus one. */
- unsigned long mask_num_entries;
-
- /* The log2() of the number of entries. */
- unsigned long log2_num_entries;
-
- /* The context. */
- gxio_mpipe_context_t *context;
-
- /* The ering. */
- unsigned int ering;
-
- /* The channel. */
- unsigned int channel;
-
-} gxio_mpipe_equeue_t;
-
-/* Initialize an "equeue".
- *
- * This function uses gxio_mpipe_init_edma_ring() to initialize the
- * underlying edma_ring using the provided arguments.
- *
- * @param equeue An egress queue to be initialized.
- * @param context An initialized mPIPE context.
- * @param ering The eDMA ring index.
- * @param channel The channel to use. This must be one of the channels
- * associated with the context's set of open links.
- * @param mem A physically contiguous region of memory to be filled
- * with a ring of ::gxio_mpipe_edesc_t structures.
- * @param mem_size Number of bytes in the ring. Must be 512, 2048,
- * 8192 or 65536, times 16 (i.e. sizeof(gxio_mpipe_edesc_t)).
- * @param mem_flags ::gxio_mpipe_mem_flags_e memory flags.
- *
- * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_EDMA_RING or
- * ::GXIO_ERR_INVAL_MEMORY_SIZE on failure.
- */
-extern int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
- gxio_mpipe_context_t *context,
- unsigned int ering,
- unsigned int channel,
- void *mem, unsigned int mem_size,
- unsigned int mem_flags);
-
-/* Reserve completion slots for edescs.
- *
- * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
- *
- * This function is slower than gxio_mpipe_equeue_reserve_fast(), but
- * returns a full 64 bit completion slot, which can be used with
- * gxio_mpipe_equeue_is_complete().
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param num Number of slots to reserve (must be non-zero).
- * @return The first reserved completion slot, or a negative error code.
- */
-static inline int64_t gxio_mpipe_equeue_reserve(gxio_mpipe_equeue_t *equeue,
- unsigned int num)
-{
- return __gxio_dma_queue_reserve_aux(&equeue->dma_queue, num, true);
-}
-
-/* Reserve completion slots for edescs, if possible.
- *
- * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
- *
- * This function is slower than gxio_mpipe_equeue_try_reserve_fast(),
- * but returns a full 64 bit completion slot, which can be used with
- * gxio_mpipe_equeue_is_complete().
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param num Number of slots to reserve (must be non-zero).
- * @return The first reserved completion slot, or a negative error code.
- */
-static inline int64_t gxio_mpipe_equeue_try_reserve(gxio_mpipe_equeue_t
- *equeue, unsigned int num)
-{
- return __gxio_dma_queue_reserve_aux(&equeue->dma_queue, num, false);
-}
-
-/* Reserve slots for edescs.
- *
- * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
- *
- * This function is faster than gxio_mpipe_equeue_reserve(), but
- * returns a 24 bit slot (instead of a 64 bit completion slot), which
- * thus cannot be used with gxio_mpipe_equeue_is_complete().
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param num Number of slots to reserve (should be non-zero).
- * @return The first reserved slot, or a negative error code.
- */
-static inline int64_t gxio_mpipe_equeue_reserve_fast(gxio_mpipe_equeue_t
- *equeue, unsigned int num)
-{
- return __gxio_dma_queue_reserve(&equeue->dma_queue, num, true, false);
-}
-
-/* Reserve slots for edescs, if possible.
- *
- * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
- *
- * This function is faster than gxio_mpipe_equeue_try_reserve(), but
- * returns a 24 bit slot (instead of a 64 bit completion slot), which
- * thus cannot be used with gxio_mpipe_equeue_is_complete().
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param num Number of slots to reserve (should be non-zero).
- * @return The first reserved slot, or a negative error code.
- */
-static inline int64_t gxio_mpipe_equeue_try_reserve_fast(gxio_mpipe_equeue_t
- *equeue,
- unsigned int num)
-{
- return __gxio_dma_queue_reserve(&equeue->dma_queue, num, false, false);
-}
-
-/*
- * HACK: This helper function tricks gcc 4.6 into avoiding saving
- * a copy of "edesc->words[0]" on the stack for no obvious reason.
- */
-
-static inline void gxio_mpipe_equeue_put_at_aux(gxio_mpipe_equeue_t *equeue,
- uint_reg_t ew[2],
- unsigned long slot)
-{
- unsigned long edma_slot = slot & equeue->mask_num_entries;
- gxio_mpipe_edesc_t *edesc_p = &equeue->edescs[edma_slot];
-
- /*
- * ISSUE: Could set eDMA ring to be on generation 1 at start, which
- * would avoid the negation here, perhaps allowing "__insn_bfins()".
- */
- ew[0] |= !((slot >> equeue->log2_num_entries) & 1);
-
- /*
- * NOTE: We use "__gxio_mpipe_write()", plus the fact that the eDMA
- * queue alignment restrictions ensure that these two words are on
- * the same cacheline, to force proper ordering between the stores.
- */
- __gxio_mmio_write64(&edesc_p->words[1], ew[1]);
- __gxio_mmio_write64(&edesc_p->words[0], ew[0]);
-}
-
-/* Post an edesc to a given slot in an equeue.
- *
- * This function copies the supplied edesc into entry "slot mod N" in
- * the underlying ring, setting the "gen" bit to the appropriate value
- * based on "(slot mod N*2)", where "N" is the size of the ring. Note
- * that the higher bits of slot are unused, and thus, this function
- * can handle "slots" as well as "completion slots".
- *
- * Normally this function is used to fill in slots reserved by
- * gxio_mpipe_equeue_try_reserve(), gxio_mpipe_equeue_reserve(),
- * gxio_mpipe_equeue_try_reserve_fast(), or
- * gxio_mpipe_equeue_reserve_fast(),
- *
- * This function can also be used without "reserving" slots, if the
- * application KNOWS that the ring can never overflow, for example, by
- * pushing fewer buffers into the buffer stacks than there are total
- * slots in the equeue, but this is NOT recommended.
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param edesc The egress descriptor to be posted.
- * @param slot An egress slot (only the low bits are actually used).
- */
-static inline void gxio_mpipe_equeue_put_at(gxio_mpipe_equeue_t *equeue,
- gxio_mpipe_edesc_t edesc,
- unsigned long slot)
-{
- gxio_mpipe_equeue_put_at_aux(equeue, edesc.words, slot);
-}
-
-/* Post an edesc to the next slot in an equeue.
- *
- * This is a convenience wrapper around
- * gxio_mpipe_equeue_reserve_fast() and gxio_mpipe_equeue_put_at().
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param edesc The egress descriptor to be posted.
- * @return 0 on success.
- */
-static inline int gxio_mpipe_equeue_put(gxio_mpipe_equeue_t *equeue,
- gxio_mpipe_edesc_t edesc)
-{
- int64_t slot = gxio_mpipe_equeue_reserve_fast(equeue, 1);
- if (slot < 0)
- return (int)slot;
-
- gxio_mpipe_equeue_put_at(equeue, edesc, slot);
-
- return 0;
-}
-
-/* Ask the mPIPE hardware to egress outstanding packets immediately.
- *
- * This call is not necessary, but may slightly reduce overall latency.
- *
- * Technically, you should flush all gxio_mpipe_equeue_put_at() writes
- * to memory before calling this function, to ensure the descriptors
- * are visible in memory before the mPIPE hardware actually looks for
- * them. But this should be very rare, and the only side effect would
- * be increased latency, so it is up to the caller to decide whether
- * or not to flush memory.
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- */
-static inline void gxio_mpipe_equeue_flush(gxio_mpipe_equeue_t *equeue)
-{
- /* Use "ring_idx = 0" and "count = 0" to "wake up" the eDMA ring. */
- MPIPE_EDMA_POST_REGION_VAL_t val = { {0} };
- /* Flush the write buffers. */
- __insn_flushwb();
- __gxio_mmio_write(equeue->dma_queue.post_region_addr, val.word);
-}
-
-/* Determine if a given edesc has been completed.
- *
- * Note that this function requires a "completion slot", and thus may
- * NOT be used with a "slot" from gxio_mpipe_equeue_reserve_fast() or
- * gxio_mpipe_equeue_try_reserve_fast().
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param completion_slot The completion slot used by the edesc.
- * @param update If true, and the desc does not appear to have completed
- * yet, then update any software cache of the hardware completion counter,
- * and check again. This should normally be true.
- * @return True iff the given edesc has been completed.
- */
-static inline int gxio_mpipe_equeue_is_complete(gxio_mpipe_equeue_t *equeue,
- int64_t completion_slot,
- int update)
-{
- return __gxio_dma_queue_is_complete(&equeue->dma_queue,
- completion_slot, update);
-}
-
-/* Set the snf (store and forward) size for an equeue.
- *
- * The snf size for an equeue defaults to 1536, and encodes the size
- * of the largest packet for which egress is guaranteed to avoid
- * transmission underruns and/or corrupt checksums under heavy load.
- *
- * The snf size affects a global resource pool which cannot support,
- * for example, all 24 equeues each requesting an snf size of 8K.
- *
- * To ensure that jumbo packets can be egressed properly, the snf size
- * should be set to the size of the largest possible packet, which
- * will usually be limited by the size of the app's largest buffer.
- *
- * This is a convenience wrapper around
- * gxio_mpipe_config_edma_ring_blks().
- *
- * This function should not be called after any egress has been done
- * on the equeue.
- *
- * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
- * @param size The snf size, in bytes.
- * @return Zero on success, negative error otherwise.
- */
-static inline int gxio_mpipe_equeue_set_snf_size(gxio_mpipe_equeue_t *equeue,
- size_t size)
-{
- int blks = (size + 127) / 128;
- return gxio_mpipe_config_edma_ring_blks(equeue->context, equeue->ering,
- blks + 1, blks, 1);
-}
-
-/*****************************************************************
- * Link Management *
- ******************************************************************/
-
-/*
- *
- * Functions for manipulating and sensing the state and configuration
- * of physical network links.
- *
- * @section gxio_mpipe_link_perm Link Permissions
- *
- * Opening a link (with gxio_mpipe_link_open()) requests a set of link
- * permissions, which control what may be done with the link, and potentially
- * what permissions may be granted to other processes.
- *
- * Data permission allows the process to receive packets from the link by
- * specifying the link's channel number in mPIPE packet distribution rules,
- * and to send packets to the link by using the link's channel number as
- * the target for an eDMA ring.
- *
- * Stats permission allows the process to retrieve link attributes (such as
- * the speeds it is capable of running at, or whether it is currently up), and
- * to read and write certain statistics-related registers in the link's MAC.
- *
- * Control permission allows the process to retrieve and modify link attributes
- * (so that it may, for example, bring the link up and take it down), and
- * read and write many registers in the link's MAC and PHY.
- *
- * Any permission may be requested as shared, which allows other processes
- * to also request shared permission, or exclusive, which prevents other
- * processes from requesting it. In keeping with GXIO's typical usage in
- * an embedded environment, the defaults for all permissions are shared.
- *
- * Permissions are granted on a first-come, first-served basis, so if two
- * applications request an exclusive permission on the same link, the one
- * to run first will win. Note, however, that some system components, like
- * the kernel Ethernet driver, may get an opportunity to open links before
- * any applications run.
- *
- * @section gxio_mpipe_link_names Link Names
- *
- * Link names are of the form gbe<em>number</em> (for Gigabit Ethernet),
- * xgbe<em>number</em> (for 10 Gigabit Ethernet), loop<em>number</em> (for
- * internal mPIPE loopback), or ilk<em>number</em>/<em>channel</em>
- * (for Interlaken links); for instance, gbe0, xgbe1, loop3, and
- * ilk0/12 are all possible link names. The correspondence between
- * the link name and an mPIPE instance number or mPIPE channel number is
- * system-dependent; all links will not exist on all systems, and the set
- * of numbers used for a particular link type may not start at zero and may
- * not be contiguous. Use gxio_mpipe_link_enumerate() to retrieve the set of
- * links which exist on a system, and always use gxio_mpipe_link_instance()
- * to determine which mPIPE controls a particular link.
- *
- * Note that in some cases, links may share hardware, such as PHYs, or
- * internal mPIPE buffers; in these cases, only one of the links may be
- * opened at a time. This is especially common with xgbe and gbe ports,
- * since each xgbe port uses 4 SERDES lanes, each of which may also be
- * configured as one gbe port.
- *
- * @section gxio_mpipe_link_states Link States
- *
- * The mPIPE link management model revolves around three different states,
- * which are maintained for each link:
- *
- * 1. The <em>current</em> link state: is the link up now, and if so, at
- * what speed?
- *
- * 2. The <em>desired</em> link state: what do we want the link state to be?
- * The system is always working to make this state the current state;
- * thus, if the desired state is up, and the link is down, we'll be
- * constantly trying to bring it up, automatically.
- *
- * 3. The <em>possible</em> link state: what speeds are valid for this
- * particular link? Or, in other words, what are the capabilities of
- * the link hardware?
- *
- * These link states are not, strictly speaking, related to application
- * state; they may be manipulated at any time, whether or not the link
- * is currently being used for data transfer. However, for convenience,
- * gxio_mpipe_link_open() and gxio_mpipe_link_close() (or application exit)
- * can affect the link state. These implicit link management operations
- * may be modified or disabled by the use of link open flags.
- *
- * From an application, you can use gxio_mpipe_link_get_attr()
- * and gxio_mpipe_link_set_attr() to manipulate the link states.
- * gxio_mpipe_link_get_attr() with ::GXIO_MPIPE_LINK_POSSIBLE_STATE
- * gets you the possible link state. gxio_mpipe_link_get_attr() with
- * ::GXIO_MPIPE_LINK_CURRENT_STATE gets you the current link state.
- * Finally, gxio_mpipe_link_set_attr() and gxio_mpipe_link_get_attr()
- * with ::GXIO_MPIPE_LINK_DESIRED_STATE allow you to modify or retrieve
- * the desired link state.
- *
- * If you want to manage a link from a part of your application which isn't
- * involved in packet processing, you can use the ::GXIO_MPIPE_LINK_NO_DATA
- * flags on a gxio_mpipe_link_open() call. This opens the link, but does
- * not request data permission, so it does not conflict with any exclusive
- * permissions which may be held by other processes. You can then can use
- * gxio_mpipe_link_get_attr() and gxio_mpipe_link_set_attr() on this link
- * object to bring up or take down the link.
- *
- * Some links support link state bits which support various loopback
- * modes. ::GXIO_MPIPE_LINK_LOOP_MAC tests datapaths within the Tile
- * Processor itself; ::GXIO_MPIPE_LINK_LOOP_PHY tests the datapath between
- * the Tile Processor and the external physical layer interface chip; and
- * ::GXIO_MPIPE_LINK_LOOP_EXT tests the entire network datapath with the
- * aid of an external loopback connector. In addition to enabling hardware
- * testing, such configuration can be useful for software testing, as well.
- *
- * When LOOP_MAC or LOOP_PHY is enabled, packets transmitted on a channel
- * will be received by that channel, instead of being emitted on the
- * physical link, and packets received on the physical link will be ignored.
- * Other than that, all standard GXIO operations work as you might expect.
- * Note that loopback operation requires that the link be brought up using
- * one or more of the GXIO_MPIPE_LINK_SPEED_xxx link state bits.
- *
- * Those familiar with previous versions of the MDE on TILEPro hardware
- * will notice significant similarities between the NetIO link management
- * model and the mPIPE link management model. However, the NetIO model
- * was developed in stages, and some of its features -- for instance,
- * the default setting of certain flags -- were shaped by the need to be
- * compatible with previous versions of NetIO. Since the features provided
- * by the mPIPE hardware and the mPIPE GXIO library are significantly
- * different than those provided by NetIO, in some cases, we have made
- * different choices in the mPIPE link management API. Thus, please read
- * this documentation carefully before assuming that mPIPE link management
- * operations are exactly equivalent to their NetIO counterparts.
- */
-
-/* An object used to manage mPIPE link state and resources. */
-typedef struct {
- /* The overall mPIPE context. */
- gxio_mpipe_context_t *context;
-
- /* The channel number used by this link. */
- uint8_t channel;
-
- /* The MAC index used by this link. */
- uint8_t mac;
-} gxio_mpipe_link_t;
-
-/* Translate a link name to the instance number of the mPIPE shim which is
- * connected to that link. This call does not verify whether the link is
- * currently available, and does not reserve any link resources;
- * gxio_mpipe_link_open() must be called to perform those functions.
- *
- * Typically applications will call this function to translate a link name
- * to an mPIPE instance number; call gxio_mpipe_init(), passing it that
- * instance number, to initialize the mPIPE shim; and then call
- * gxio_mpipe_link_open(), passing it the same link name plus the mPIPE
- * context, to configure the link.
- *
- * @param link_name Name of the link; see @ref gxio_mpipe_link_names.
- * @return The mPIPE instance number which is associated with the named
- * link, or a negative error code (::GXIO_ERR_NO_DEVICE) if the link does
- * not exist.
- */
-extern int gxio_mpipe_link_instance(const char *link_name);
-
-/* Retrieve one of this system's legal link names, and its MAC address.
- *
- * @param index Link name index. If a system supports N legal link names,
- * then indices between 0 and N - 1, inclusive, each correspond to one of
- * those names. Thus, to retrieve all of a system's legal link names,
- * call this function in a loop, starting with an index of zero, and
- * incrementing it once per iteration until -1 is returned.
- * @param link_name Pointer to the buffer which will receive the retrieved
- * link name. The buffer should contain space for at least
- * ::GXIO_MPIPE_LINK_NAME_LEN bytes; the returned name, including the
- * terminating null byte, will be no longer than that.
- * @param link_name Pointer to the buffer which will receive the retrieved
- * MAC address. The buffer should contain space for at least 6 bytes.
- * @return Zero if a link name was successfully retrieved; -1 if one was
- * not.
- */
-extern int gxio_mpipe_link_enumerate_mac(int index, char *link_name,
- uint8_t *mac_addr);
-
-/* Open an mPIPE link.
- *
- * A link must be opened before it may be used to send or receive packets,
- * and before its state may be examined or changed. Depending up on the
- * link's intended use, one or more link permissions may be requested via
- * the flags parameter; see @ref gxio_mpipe_link_perm. In addition, flags
- * may request that the link's state be modified at open time. See @ref
- * gxio_mpipe_link_states and @ref gxio_mpipe_link_open_flags for more detail.
- *
- * @param link A link state object, which will be initialized if this
- * function completes successfully.
- * @param context An initialized mPIPE context.
- * @param link_name Name of the link.
- * @param flags Zero or more @ref gxio_mpipe_link_open_flags, ORed together.
- * @return 0 if the link was successfully opened, or a negative error code.
- *
- */
-extern int gxio_mpipe_link_open(gxio_mpipe_link_t *link,
- gxio_mpipe_context_t *context,
- const char *link_name, unsigned int flags);
-
-/* Close an mPIPE link.
- *
- * Closing a link makes it available for use by other processes. Once
- * a link has been closed, packets may no longer be sent on or received
- * from the link, and its state may not be examined or changed.
- *
- * @param link A link state object, which will no longer be initialized
- * if this function completes successfully.
- * @return 0 if the link was successfully closed, or a negative error code.
- *
- */
-extern int gxio_mpipe_link_close(gxio_mpipe_link_t *link);
-
-/* Return a link's channel number.
- *
- * @param link A properly initialized link state object.
- * @return The channel number for the link.
- */
-static inline int gxio_mpipe_link_channel(gxio_mpipe_link_t *link)
-{
- return link->channel;
-}
-
-/* Set a link attribute.
- *
- * @param link A properly initialized link state object.
- * @param attr An attribute from the set of @ref gxio_mpipe_link_attrs.
- * @param val New value of the attribute.
- * @return 0 if the attribute was successfully set, or a negative error
- * code.
- */
-extern int gxio_mpipe_link_set_attr(gxio_mpipe_link_t *link, uint32_t attr,
- int64_t val);
-
-///////////////////////////////////////////////////////////////////
-// Timestamp //
-///////////////////////////////////////////////////////////////////
-
-/* Get the timestamp of mPIPE when this routine is called.
- *
- * @param context An initialized mPIPE context.
- * @param ts A timespec structure to store the current clock.
- * @return If the call was successful, zero; otherwise, a negative error
- * code.
- */
-extern int gxio_mpipe_get_timestamp(gxio_mpipe_context_t *context,
- struct timespec64 *ts);
-
-/* Set the timestamp of mPIPE.
- *
- * @param context An initialized mPIPE context.
- * @param ts A timespec structure to store the requested clock.
- * @return If the call was successful, zero; otherwise, a negative error
- * code.
- */
-extern int gxio_mpipe_set_timestamp(gxio_mpipe_context_t *context,
- const struct timespec64 *ts);
-
-/* Adjust the timestamp of mPIPE.
- *
- * @param context An initialized mPIPE context.
- * @param delta A signed time offset to adjust, in nanoseconds.
- * The absolute value of this parameter must be less than or
- * equal to 1000000000.
- * @return If the call was successful, zero; otherwise, a negative error
- * code.
- */
-extern int gxio_mpipe_adjust_timestamp(gxio_mpipe_context_t *context,
- int64_t delta);
-
-/** Adjust the mPIPE timestamp clock frequency.
- *
- * @param context An initialized mPIPE context.
- * @param ppb A 32-bit signed PPB (Parts Per Billion) value to adjust.
- * The absolute value of ppb must be less than or equal to 1000000000.
- * Values less than about 30000 will generally cause a GXIO_ERR_INVAL
- * return due to the granularity of the hardware that converts reference
- * clock cycles into seconds and nanoseconds.
- * @return If the call was successful, zero; otherwise, a negative error
- * code.
- */
-extern int gxio_mpipe_adjust_timestamp_freq(gxio_mpipe_context_t* context,
- int32_t ppb);
-
-#endif /* !_GXIO_MPIPE_H_ */
diff --git a/arch/tile/include/gxio/trio.h b/arch/tile/include/gxio/trio.h
deleted file mode 100644
index df10a662cc25..000000000000
--- a/arch/tile/include/gxio/trio.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- *
- * An API for allocating, configuring, and manipulating TRIO hardware
- * resources
- */
-
-/*
- *
- * The TILE-Gx TRIO shim provides connections to external devices via
- * PCIe or other transaction IO standards. The gxio_trio_ API,
- * declared in <gxio/trio.h>, allows applications to allocate and
- * configure TRIO IO resources like DMA command rings, memory map
- * windows, and device interrupts. The following sections introduce
- * the various components of the API. We strongly recommend reading
- * the TRIO section of the IO Device Guide (UG404) before working with
- * this API.
- *
- * @section trio__ingress TRIO Ingress Hardware Resources
- *
- * The TRIO ingress hardware is responsible for examining incoming
- * PCIe or StreamIO packets and choosing a processing mechanism based
- * on the packets' bus address. The gxio_trio_ API can be used to
- * configure different handlers for different ranges of bus address
- * space. The user can configure "mapped memory" and "scatter queue"
- * regions to match incoming packets within 4kB-aligned ranges of bus
- * addresses. Each range specifies a different set of mapping
- * parameters to be applied when handling the ingress packet. The
- * following sections describe how to work with MapMem and scatter
- * queue regions.
- *
- * @subsection trio__mapmem TRIO MapMem Regions
- *
- * TRIO mapped memory (or MapMem) regions allow the user to map
- * incoming read and write requests directly to the application's
- * memory space. MapMem regions are allocated via
- * gxio_trio_alloc_memory_maps(). Given an integer MapMem number,
- * applications can use gxio_trio_init_memory_map() to specify the
- * range of bus addresses that will match the region and the range of
- * virtual addresses to which those packets will be applied.
- *
- * As with many other gxio APIs, the programmer must be sure to
- * register memory pages that will be used with MapMem regions. Pages
- * can be registered with TRIO by allocating an ASID (address space
- * identifier) and then using gxio_trio_register_page() to register up to
- * 16 pages with the hardware. The initialization functions for
- * resources that require registered memory (MapMem, scatter queues,
- * push DMA, and pull DMA) then take an 'asid' parameter in order to
- * configure which set of registered pages is used by each resource.
- *
- * @subsection trio__scatter_queue TRIO Scatter Queues
- *
- * The TRIO shim's scatter queue regions allow users to dynamically
- * map buffers from a large address space into a small range of bus
- * addresses. This is particularly helpful for PCIe endpoint devices,
- * where the host generally limits the size of BARs to tens of
- * megabytes.
- *
- * Each scatter queue consists of a memory map region, a queue of
- * tile-side buffer VAs to be mapped to that region, and a bus-mapped
- * "doorbell" register that the remote endpoint can write to trigger a
- * dequeue of the current buffer VA, thus swapping in a new buffer.
- * The VAs pushed onto a scatter queue must be 4kB aligned, so
- * applications may need to use higher-level protocols to inform
- * remote entities that they should apply some additional, sub-4kB
- * offset when reading or writing the scatter queue region. For more
- * information, see the IO Device Guide (UG404).
- *
- * @section trio__egress TRIO Egress Hardware Resources
- *
- * The TRIO shim supports two mechanisms for egress packet generation:
- * programmed IO (PIO) and push/pull DMA. PIO allows applications to
- * create MMIO mappings for PCIe or StreamIO address space, such that
- * the application can generate word-sized read or write transactions
- * by issuing load or store instructions. Push and pull DMA are tuned
- * for larger transactions; they use specialized hardware engines to
- * transfer large blocks of data at line rate.
- *
- * @subsection trio__pio TRIO Programmed IO
- *
- * Programmed IO allows applications to create MMIO mappings for PCIe
- * or StreamIO address space. The hardware PIO regions support access
- * to PCIe configuration, IO, and memory space, but the gxio_trio API
- * only supports memory space accesses. PIO regions are allocated
- * with gxio_trio_alloc_pio_regions() and initialized via
- * gxio_trio_init_pio_region(). Once a region is bound to a range of
- * bus address via the initialization function, the application can
- * use gxio_trio_map_pio_region() to create MMIO mappings from its VA
- * space onto the range of bus addresses supported by the PIO region.
- *
- * @subsection trio_dma TRIO Push and Pull DMA
- *
- * The TRIO push and pull DMA engines allow users to copy blocks of
- * data between application memory and the bus. Push DMA generates
- * write packets that copy from application memory to the bus and pull
- * DMA generates read packets that copy from the bus into application
- * memory. The DMA engines are managed via an API that is very
- * similar to the mPIPE eDMA interface. For a detailed explanation of
- * the eDMA queue API, see @ref gxio_mpipe_wrappers.
- *
- * Push and pull DMA queues are allocated via
- * gxio_trio_alloc_push_dma_ring() / gxio_trio_alloc_pull_dma_ring().
- * Once allocated, users generally use a ::gxio_trio_dma_queue_t
- * object to manage the queue, providing easy wrappers for reserving
- * command slots in the DMA command ring, filling those slots, and
- * waiting for commands to complete. DMA queues can be initialized
- * via gxio_trio_init_push_dma_queue() or
- * gxio_trio_init_pull_dma_queue().
- *
- * See @ref trio/push_dma/app.c for an example of how to use push DMA.
- *
- * @section trio_shortcomings Plans for Future API Revisions
- *
- * The simulation framework is incomplete. Future features include:
- *
- * - Support for reset and deallocation of resources.
- *
- * - Support for pull DMA.
- *
- * - Support for interrupt regions and user-space interrupt delivery.
- *
- * - Support for getting BAR mappings and reserving regions of BAR
- * address space.
- */
-#ifndef _GXIO_TRIO_H_
-#define _GXIO_TRIO_H_
-
-#include <linux/types.h>
-
-#include <gxio/common.h>
-#include <gxio/dma_queue.h>
-
-#include <arch/trio_constants.h>
-#include <arch/trio.h>
-#include <arch/trio_pcie_intfc.h>
-#include <arch/trio_pcie_rc.h>
-#include <arch/trio_shm.h>
-#include <hv/drv_trio_intf.h>
-#include <hv/iorpc.h>
-
-/* A context object used to manage TRIO hardware resources. */
-typedef struct {
-
- /* File descriptor for calling up to Linux (and thus the HV). */
- int fd;
-
- /* The VA at which the MAC MMIO registers are mapped. */
- char *mmio_base_mac;
-
- /* The VA at which the PIO config space are mapped for each PCIe MAC.
- Gx36 has max 3 PCIe MACs per TRIO shim. */
- char *mmio_base_pio_cfg[TILEGX_TRIO_PCIES];
-
-#ifdef USE_SHARED_PCIE_CONFIG_REGION
- /* Index of the shared PIO region for PCI config access. */
- int pio_cfg_index;
-#else
- /* Index of the PIO region for PCI config access per MAC. */
- int pio_cfg_index[TILEGX_TRIO_PCIES];
-#endif
-
- /* The VA at which the push DMA MMIO registers are mapped. */
- char *mmio_push_dma[TRIO_NUM_PUSH_DMA_RINGS];
-
- /* The VA at which the pull DMA MMIO registers are mapped. */
- char *mmio_pull_dma[TRIO_NUM_PUSH_DMA_RINGS];
-
- /* Application space ID. */
- unsigned int asid;
-
-} gxio_trio_context_t;
-
-/* Command descriptor for push or pull DMA. */
-typedef TRIO_DMA_DESC_t gxio_trio_dma_desc_t;
-
-/* A convenient, thread-safe interface to an eDMA ring. */
-typedef struct {
-
- /* State object for tracking head and tail pointers. */
- __gxio_dma_queue_t dma_queue;
-
- /* The ring entries. */
- gxio_trio_dma_desc_t *dma_descs;
-
- /* The number of entries minus one. */
- unsigned long mask_num_entries;
-
- /* The log2() of the number of entries. */
- unsigned int log2_num_entries;
-
-} gxio_trio_dma_queue_t;
-
-/* Initialize a TRIO context.
- *
- * This function allocates a TRIO "service domain" and maps the MMIO
- * registers into the the caller's VA space.
- *
- * @param trio_index Which TRIO shim; Gx36 must pass 0.
- * @param context Context object to be initialized.
- */
-extern int gxio_trio_init(gxio_trio_context_t *context,
- unsigned int trio_index);
-
-/* This indicates that an ASID hasn't been allocated. */
-#define GXIO_ASID_NULL -1
-
-/* Ordering modes for map memory regions and scatter queue regions. */
-typedef enum gxio_trio_order_mode_e {
- /* Writes are not ordered. Reads always wait for previous writes. */
- GXIO_TRIO_ORDER_MODE_UNORDERED =
- TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED,
- /* Both writes and reads wait for previous transactions to complete. */
- GXIO_TRIO_ORDER_MODE_STRICT =
- TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT,
- /* Writes are ordered unless the incoming packet has the
- relaxed-ordering attributes set. */
- GXIO_TRIO_ORDER_MODE_OBEY_PACKET =
- TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD
-} gxio_trio_order_mode_t;
-
-/* Initialize a memory mapping region.
- *
- * @param context An initialized TRIO context.
- * @param map A Memory map region allocated by gxio_trio_alloc_memory_map().
- * @param target_mem VA of backing memory, should be registered via
- * gxio_trio_register_page() and aligned to 4kB.
- * @param target_size Length of the memory mapping, must be a multiple
- * of 4kB.
- * @param asid ASID to be used for Tile-side address translation.
- * @param mac MAC number.
- * @param bus_address Bus address at which the mapping starts.
- * @param order_mode Memory ordering mode for this mapping.
- * @return Zero on success, else ::GXIO_TRIO_ERR_BAD_MEMORY_MAP,
- * GXIO_TRIO_ERR_BAD_ASID, or ::GXIO_TRIO_ERR_BAD_BUS_RANGE.
- */
-extern int gxio_trio_init_memory_map(gxio_trio_context_t *context,
- unsigned int map, void *target_mem,
- size_t target_size, unsigned int asid,
- unsigned int mac, uint64_t bus_address,
- gxio_trio_order_mode_t order_mode);
-
-/* Flags that can be passed to resource allocation functions. */
-enum gxio_trio_alloc_flags_e {
- GXIO_TRIO_ALLOC_FIXED = HV_TRIO_ALLOC_FIXED,
-};
-
-/* Flags that can be passed to memory registration functions. */
-enum gxio_trio_mem_flags_e {
- /* Do not fill L3 when writing, and invalidate lines upon egress. */
- GXIO_TRIO_MEM_FLAG_NT_HINT = IORPC_MEM_BUFFER_FLAG_NT_HINT,
-
- /* L3 cache fills should only populate IO cache ways. */
- GXIO_TRIO_MEM_FLAG_IO_PIN = IORPC_MEM_BUFFER_FLAG_IO_PIN,
-};
-
-/* Flag indicating a request generator uses a special traffic
- class. */
-#define GXIO_TRIO_FLAG_TRAFFIC_CLASS(N) HV_TRIO_FLAG_TC(N)
-
-/* Flag indicating a request generator uses a virtual function
- number. */
-#define GXIO_TRIO_FLAG_VFUNC(N) HV_TRIO_FLAG_VFUNC(N)
-
-/*****************************************************************
- * Memory Registration *
- ******************************************************************/
-
-/* Allocate Application Space Identifiers (ASIDs). Each ASID can
- * register up to 16 page translations. ASIDs are used by memory map
- * regions, scatter queues, and DMA queues to translate application
- * VAs into memory system PAs.
- *
- * @param context An initialized TRIO context.
- * @param count Number of ASIDs required.
- * @param first Index of first ASID if ::GXIO_TRIO_ALLOC_FIXED flag
- * is set, otherwise ignored.
- * @param flags Flag bits, including bits from ::gxio_trio_alloc_flags_e.
- * @return Index of first ASID, or ::GXIO_TRIO_ERR_NO_ASID if allocation
- * failed.
- */
-extern int gxio_trio_alloc_asids(gxio_trio_context_t *context,
- unsigned int count, unsigned int first,
- unsigned int flags);
-
-#endif /* ! _GXIO_TRIO_H_ */
diff --git a/arch/tile/include/gxio/uart.h b/arch/tile/include/gxio/uart.h
deleted file mode 100644
index 438ee7e46c7b..000000000000
--- a/arch/tile/include/gxio/uart.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _GXIO_UART_H_
-#define _GXIO_UART_H_
-
-#include "common.h"
-
-#include <hv/drv_uart_intf.h>
-#include <hv/iorpc.h>
-
-/*
- *
- * An API for manipulating UART interface.
- */
-
-/*
- *
- * The Rshim allows access to the processor's UART interface.
- */
-
-/* A context object used to manage UART resources. */
-typedef struct {
-
- /* File descriptor for calling up to the hypervisor. */
- int fd;
-
- /* The VA at which our MMIO registers are mapped. */
- char *mmio_base;
-
-} gxio_uart_context_t;
-
-/* Request UART interrupts.
- *
- * Request that interrupts be delivered to a tile when the UART's
- * Receive FIFO is written, or the Write FIFO is read.
- *
- * @param context Pointer to a properly initialized gxio_uart_context_t.
- * @param bind_cpu_x X coordinate of CPU to which interrupt will be delivered.
- * @param bind_cpu_y Y coordinate of CPU to which interrupt will be delivered.
- * @param bind_interrupt IPI interrupt number.
- * @param bind_event Sub-interrupt event bit number; a negative value can
- * disable the interrupt.
- * @return Zero if all of the requested UART events were successfully
- * configured to interrupt.
- */
-extern int gxio_uart_cfg_interrupt(gxio_uart_context_t *context,
- int bind_cpu_x,
- int bind_cpu_y,
- int bind_interrupt, int bind_event);
-
-/* Initialize a UART context.
- *
- * A properly initialized context must be obtained before any of the other
- * gxio_uart routines may be used.
- *
- * @param context Pointer to a gxio_uart_context_t, which will be initialized
- * by this routine, if it succeeds.
- * @param uart_index Index of the UART to use.
- * @return Zero if the context was successfully initialized, else a
- * GXIO_ERR_xxx error code.
- */
-extern int gxio_uart_init(gxio_uart_context_t *context, int uart_index);
-
-/* Destroy a UART context.
- *
- * Once destroyed, a context may not be used with any gxio_uart routines
- * other than gxio_uart_init(). After this routine returns, no further
- * interrupts requested on this context will be delivered. The state and
- * configuration of the pins which had been attached to this context are
- * unchanged by this operation.
- *
- * @param context Pointer to a gxio_uart_context_t.
- * @return Zero if the context was successfully destroyed, else a
- * GXIO_ERR_xxx error code.
- */
-extern int gxio_uart_destroy(gxio_uart_context_t *context);
-
-/* Write UART register.
- * @param context Pointer to a gxio_uart_context_t.
- * @param offset UART register offset.
- * @param word Data will be wrote to UART reigister.
- */
-extern void gxio_uart_write(gxio_uart_context_t *context, uint64_t offset,
- uint64_t word);
-
-/* Read UART register.
- * @param context Pointer to a gxio_uart_context_t.
- * @param offset UART register offset.
- * @return Data read from UART register.
- */
-extern uint64_t gxio_uart_read(gxio_uart_context_t *context, uint64_t offset);
-
-#endif /* _GXIO_UART_H_ */
diff --git a/arch/tile/include/gxio/usb_host.h b/arch/tile/include/gxio/usb_host.h
deleted file mode 100644
index 93c9636d2dd7..000000000000
--- a/arch/tile/include/gxio/usb_host.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-#ifndef _GXIO_USB_H_
-#define _GXIO_USB_H_
-
-#include <gxio/common.h>
-
-#include <hv/drv_usb_host_intf.h>
-#include <hv/iorpc.h>
-
-/*
- *
- * An API for manipulating general-purpose I/O pins.
- */
-
-/*
- *
- * The USB shim allows access to the processor's Universal Serial Bus
- * connections.
- */
-
-/* A context object used to manage USB hardware resources. */
-typedef struct {
-
- /* File descriptor for calling up to the hypervisor. */
- int fd;
-
- /* The VA at which our MMIO registers are mapped. */
- char *mmio_base;
-} gxio_usb_host_context_t;
-
-/* Initialize a USB context.
- *
- * A properly initialized context must be obtained before any of the other
- * gxio_usb_host routines may be used.
- *
- * @param context Pointer to a gxio_usb_host_context_t, which will be
- * initialized by this routine, if it succeeds.
- * @param usb_index Index of the USB shim to use.
- * @param is_ehci Nonzero to use the EHCI interface; zero to use the OHCI
- * intereface.
- * @return Zero if the context was successfully initialized, else a
- * GXIO_ERR_xxx error code.
- */
-extern int gxio_usb_host_init(gxio_usb_host_context_t *context, int usb_index,
- int is_ehci);
-
-/* Destroy a USB context.
- *
- * Once destroyed, a context may not be used with any gxio_usb_host routines
- * other than gxio_usb_host_init(). After this routine returns, no further
- * interrupts or signals requested on this context will be delivered. The
- * state and configuration of the pins which had been attached to this
- * context are unchanged by this operation.
- *
- * @param context Pointer to a gxio_usb_host_context_t.
- * @return Zero if the context was successfully destroyed, else a
- * GXIO_ERR_xxx error code.
- */
-extern int gxio_usb_host_destroy(gxio_usb_host_context_t *context);
-
-/* Retrieve the address of the shim's MMIO registers.
- *
- * @param context Pointer to a properly initialized gxio_usb_host_context_t.
- * @return The address of the shim's MMIO registers.
- */
-extern void *gxio_usb_host_get_reg_start(gxio_usb_host_context_t *context);
-
-/* Retrieve the length of the shim's MMIO registers.
- *
- * @param context Pointer to a properly initialized gxio_usb_host_context_t.
- * @return The length of the shim's MMIO registers.
- */
-extern size_t gxio_usb_host_get_reg_len(gxio_usb_host_context_t *context);
-
-#endif /* _GXIO_USB_H_ */
diff --git a/arch/tile/include/hv/drv_mpipe_intf.h b/arch/tile/include/hv/drv_mpipe_intf.h
deleted file mode 100644
index ff7f50f970a5..000000000000
--- a/arch/tile/include/hv/drv_mpipe_intf.h
+++ /dev/null
@@ -1,605 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * Interface definitions for the mpipe driver.
- */
-
-#ifndef _SYS_HV_DRV_MPIPE_INTF_H
-#define _SYS_HV_DRV_MPIPE_INTF_H
-
-#include <arch/mpipe.h>
-#include <arch/mpipe_constants.h>
-
-
-/** Number of mPIPE instances supported */
-#define HV_MPIPE_INSTANCE_MAX (2)
-
-/** Number of buffer stacks (32). */
-#define HV_MPIPE_NUM_BUFFER_STACKS \
- (MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH)
-
-/** Number of NotifRings (256). */
-#define HV_MPIPE_NUM_NOTIF_RINGS (MPIPE_NUM_NOTIF_RINGS)
-
-/** Number of NotifGroups (32). */
-#define HV_MPIPE_NUM_NOTIF_GROUPS (MPIPE_NUM_NOTIF_GROUPS)
-
-/** Number of buckets (4160). */
-#define HV_MPIPE_NUM_BUCKETS (MPIPE_NUM_BUCKETS)
-
-/** Number of "lo" buckets (4096). */
-#define HV_MPIPE_NUM_LO_BUCKETS 4096
-
-/** Number of "hi" buckets (64). */
-#define HV_MPIPE_NUM_HI_BUCKETS \
- (HV_MPIPE_NUM_BUCKETS - HV_MPIPE_NUM_LO_BUCKETS)
-
-/** Number of edma rings (24). */
-#define HV_MPIPE_NUM_EDMA_RINGS \
- (MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH)
-
-
-
-
-/** A flag bit indicating a fixed resource allocation. */
-#define HV_MPIPE_ALLOC_FIXED 0x01
-
-/** Offset for the config register MMIO region. */
-#define HV_MPIPE_CONFIG_MMIO_OFFSET \
- (MPIPE_MMIO_ADDR__REGION_VAL_CFG << MPIPE_MMIO_ADDR__REGION_SHIFT)
-
-/** Size of the config register MMIO region. */
-#define HV_MPIPE_CONFIG_MMIO_SIZE (64 * 1024)
-
-/** Offset for the config register MMIO region. */
-#define HV_MPIPE_FAST_MMIO_OFFSET \
- (MPIPE_MMIO_ADDR__REGION_VAL_IDMA << MPIPE_MMIO_ADDR__REGION_SHIFT)
-
-/** Size of the fast register MMIO region (IDMA, EDMA, buffer stack). */
-#define HV_MPIPE_FAST_MMIO_SIZE \
- ((MPIPE_MMIO_ADDR__REGION_VAL_BSM + 1 - MPIPE_MMIO_ADDR__REGION_VAL_IDMA) \
- << MPIPE_MMIO_ADDR__REGION_SHIFT)
-
-
-/*
- * Each type of resource allocation comes in quantized chunks, where
- * XXX_BITS is the number of chunks, and XXX_RES_PER_BIT is the number
- * of resources in each chunk.
- */
-
-/** Number of buffer stack chunks available (32). */
-#define HV_MPIPE_ALLOC_BUFFER_STACKS_BITS \
- MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH
-
-/** Granularity of buffer stack allocation (1). */
-#define HV_MPIPE_ALLOC_BUFFER_STACKS_RES_PER_BIT \
- (HV_MPIPE_NUM_BUFFER_STACKS / HV_MPIPE_ALLOC_BUFFER_STACKS_BITS)
-
-/** Number of NotifRing chunks available (32). */
-#define HV_MPIPE_ALLOC_NOTIF_RINGS_BITS \
- MPIPE_MMIO_INIT_DAT_GX36_0__NOTIF_RING_MASK_WIDTH
-
-/** Granularity of NotifRing allocation (8). */
-#define HV_MPIPE_ALLOC_NOTIF_RINGS_RES_PER_BIT \
- (HV_MPIPE_NUM_NOTIF_RINGS / HV_MPIPE_ALLOC_NOTIF_RINGS_BITS)
-
-/** Number of NotifGroup chunks available (32). */
-#define HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS \
- HV_MPIPE_NUM_NOTIF_GROUPS
-
-/** Granularity of NotifGroup allocation (1). */
-#define HV_MPIPE_ALLOC_NOTIF_GROUPS_RES_PER_BIT \
- (HV_MPIPE_NUM_NOTIF_GROUPS / HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS)
-
-/** Number of lo bucket chunks available (16). */
-#define HV_MPIPE_ALLOC_LO_BUCKETS_BITS \
- MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_LO_WIDTH
-
-/** Granularity of lo bucket allocation (256). */
-#define HV_MPIPE_ALLOC_LO_BUCKETS_RES_PER_BIT \
- (HV_MPIPE_NUM_LO_BUCKETS / HV_MPIPE_ALLOC_LO_BUCKETS_BITS)
-
-/** Number of hi bucket chunks available (16). */
-#define HV_MPIPE_ALLOC_HI_BUCKETS_BITS \
- MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_HI_WIDTH
-
-/** Granularity of hi bucket allocation (4). */
-#define HV_MPIPE_ALLOC_HI_BUCKETS_RES_PER_BIT \
- (HV_MPIPE_NUM_HI_BUCKETS / HV_MPIPE_ALLOC_HI_BUCKETS_BITS)
-
-/** Number of eDMA ring chunks available (24). */
-#define HV_MPIPE_ALLOC_EDMA_RINGS_BITS \
- MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH
-
-/** Granularity of eDMA ring allocation (1). */
-#define HV_MPIPE_ALLOC_EDMA_RINGS_RES_PER_BIT \
- (HV_MPIPE_NUM_EDMA_RINGS / HV_MPIPE_ALLOC_EDMA_RINGS_BITS)
-
-
-
-
-/** Bit vector encoding which NotifRings are in a NotifGroup. */
-typedef struct
-{
- /** The actual bits. */
- uint64_t ring_mask[4];
-
-} gxio_mpipe_notif_group_bits_t;
-
-
-/** Another name for MPIPE_LBL_INIT_DAT_BSTS_TBL_t. */
-typedef MPIPE_LBL_INIT_DAT_BSTS_TBL_t gxio_mpipe_bucket_info_t;
-
-
-
-/** Eight buffer stack ids. */
-typedef struct
-{
- /** The stacks. */
- uint8_t stacks[8];
-
-} gxio_mpipe_rules_stacks_t;
-
-
-/** A destination mac address. */
-typedef struct
-{
- /** The octets. */
- uint8_t octets[6];
-
-} gxio_mpipe_rules_dmac_t;
-
-
-/** A vlan. */
-typedef uint16_t gxio_mpipe_rules_vlan_t;
-
-
-
-/** Maximum number of characters in a link name. */
-#define GXIO_MPIPE_LINK_NAME_LEN 32
-
-
-/** Structure holding a link name. Only needed, and only typedef'ed,
- * because the IORPC stub generator only handles types which are single
- * words coming before the parameter name. */
-typedef struct
-{
- /** The name itself. */
- char name[GXIO_MPIPE_LINK_NAME_LEN];
-}
-_gxio_mpipe_link_name_t;
-
-/** Maximum number of characters in a symbol name. */
-#define GXIO_MPIPE_SYMBOL_NAME_LEN 128
-
-
-/** Structure holding a symbol name. Only needed, and only typedef'ed,
- * because the IORPC stub generator only handles types which are single
- * words coming before the parameter name. */
-typedef struct
-{
- /** The name itself. */
- char name[GXIO_MPIPE_SYMBOL_NAME_LEN];
-}
-_gxio_mpipe_symbol_name_t;
-
-
-/** Structure holding a MAC address. */
-typedef struct
-{
- /** The address. */
- uint8_t mac[6];
-}
-_gxio_mpipe_link_mac_t;
-
-
-
-/** Request shared data permission -- that is, the ability to send and
- * receive packets -- on the specified link. Other processes may also
- * request shared data permission on the same link.
- *
- * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
- * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
- */
-#define GXIO_MPIPE_LINK_DATA 0x00000001UL
-
-/** Do not request data permission on the specified link.
- *
- * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
- * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
- */
-#define GXIO_MPIPE_LINK_NO_DATA 0x00000002UL
-
-/** Request exclusive data permission -- that is, the ability to send and
- * receive packets -- on the specified link. No other processes may
- * request data permission on this link, and if any process already has
- * data permission on it, this open will fail.
- *
- * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
- * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
- */
-#define GXIO_MPIPE_LINK_EXCL_DATA 0x00000004UL
-
-/** Request shared stats permission -- that is, the ability to read and write
- * registers which contain link statistics, and to get link attributes --
- * on the specified link. Other processes may also request shared stats
- * permission on the same link.
- *
- * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
- * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
- */
-#define GXIO_MPIPE_LINK_STATS 0x00000008UL
-
-/** Do not request stats permission on the specified link.
- *
- * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
- * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
- */
-#define GXIO_MPIPE_LINK_NO_STATS 0x00000010UL
-
-/** Request exclusive stats permission -- that is, the ability to read and
- * write registers which contain link statistics, and to get link
- * attributes -- on the specified link. No other processes may request
- * stats permission on this link, and if any process already
- * has stats permission on it, this open will fail.
- *
- * Requesting exclusive stats permission is normally a very bad idea, since
- * it prevents programs like mpipe-stat from providing information on this
- * link. Applications should only do this if they use MAC statistics
- * registers, and cannot tolerate any of the clear-on-read registers being
- * reset by other statistics programs.
- *
- * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
- * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
- */
-#define GXIO_MPIPE_LINK_EXCL_STATS 0x00000020UL
-
-/** Request shared control permission -- that is, the ability to modify link
- * attributes, and read and write MAC and MDIO registers -- on the
- * specified link. Other processes may also request shared control
- * permission on the same link.
- *
- * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
- * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
- */
-#define GXIO_MPIPE_LINK_CTL 0x00000040UL
-
-/** Do not request control permission on the specified link.
- *
- * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
- * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
- */
-#define GXIO_MPIPE_LINK_NO_CTL 0x00000080UL
-
-/** Request exclusive control permission -- that is, the ability to modify
- * link attributes, and read and write MAC and MDIO registers -- on the
- * specified link. No other processes may request control permission on
- * this link, and if any process already has control permission on it,
- * this open will fail.
- *
- * Requesting exclusive control permission is not always a good idea, since
- * it prevents programs like mpipe-link from configuring the link.
- *
- * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
- * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
- */
-#define GXIO_MPIPE_LINK_EXCL_CTL 0x00000100UL
-
-/** Set the desired state of the link to up, allowing any speeds which are
- * supported by the link hardware, as part of this open operation; do not
- * change the desired state of the link when it is closed or the process
- * exits. No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
- * ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
- * ::GXIO_MPIPE_LINK_AUTO_NONE may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
- */
-#define GXIO_MPIPE_LINK_AUTO_UP 0x00000200UL
-
-/** Set the desired state of the link to up, allowing any speeds which are
- * supported by the link hardware, as part of this open operation; when the
- * link is closed or this process exits, if no other process has the link
- * open, set the desired state of the link to down. No more than one of
- * ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
- * ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
- * specified in a gxio_mpipe_link_open() call. If none are specified,
- * ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
- */
-#define GXIO_MPIPE_LINK_AUTO_UPDOWN 0x00000400UL
-
-/** Do not change the desired state of the link as part of the open
- * operation; when the link is closed or this process exits, if no other
- * process has the link open, set the desired state of the link to down.
- * No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
- * ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
- * ::GXIO_MPIPE_LINK_AUTO_NONE may be specified in a gxio_mpipe_link_open()
- * call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
- */
-#define GXIO_MPIPE_LINK_AUTO_DOWN 0x00000800UL
-
-/** Do not change the desired state of the link as part of the open
- * operation; do not change the desired state of the link when it is
- * closed or the process exits. No more than one of
- * ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
- * ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
- * specified in a gxio_mpipe_link_open() call. If none are specified,
- * ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
- */
-#define GXIO_MPIPE_LINK_AUTO_NONE 0x00001000UL
-
-/** Request that this open call not complete until the network link is up.
- * The process will wait as long as necessary for this to happen;
- * applications which wish to abandon waiting for the link after a
- * specific time period should not specify this flag when opening a link,
- * but should instead call gxio_mpipe_link_wait() afterward. The link
- * must be opened with stats permission. Note that this flag by itself
- * does not change the desired link state; if other open flags or previous
- * link state changes have not requested a desired state of up, the open
- * call will never complete. This flag is not available to kernel
- * clients.
- */
-#define GXIO_MPIPE_LINK_WAIT 0x00002000UL
-
-
-/*
- * Note: link attributes must fit in 24 bits, since we use the top 8 bits
- * of the IORPC offset word for the channel number.
- */
-
-/** Determine whether jumbo frames may be received. If this attribute's
- * value value is nonzero, the MAC will accept frames of up to 10240 bytes.
- * If the value is zero, the MAC will only accept frames of up to 1544
- * bytes. The default value is zero. */
-#define GXIO_MPIPE_LINK_RECEIVE_JUMBO 0x010000
-
-/** Determine whether to send pause frames on this link if the mPIPE packet
- * FIFO is nearly full. If the value is zero, pause frames are not sent.
- * If the value is nonzero, it is the delay value which will be sent in any
- * pause frames which are output, in units of 512 bit times.
- *
- * Bear in mind that in almost all circumstances, the mPIPE packet FIFO
- * will never fill up, since mPIPE will empty it as fast as or faster than
- * the incoming data rate, by either delivering or dropping packets. The
- * only situation in which this is not true is if the memory and cache
- * subsystem is extremely heavily loaded, and mPIPE cannot perform DMA of
- * packet data to memory in a timely fashion. In particular, pause frames
- * will <em>not</em> be sent if packets cannot be delivered because
- * NotifRings are full, buckets are full, or buffers are not available in
- * a buffer stack. */
-#define GXIO_MPIPE_LINK_SEND_PAUSE 0x020000
-
-/** Determine whether to suspend output on the receipt of pause frames.
- * If the value is nonzero, mPIPE shim will suspend output on the link's
- * channel when a pause frame is received. If the value is zero, pause
- * frames will be ignored. The default value is zero. */
-#define GXIO_MPIPE_LINK_RECEIVE_PAUSE 0x030000
-
-/** Interface MAC address. The value is a 6-byte MAC address, in the least
- * significant 48 bits of the value; in other words, an address which would
- * be printed as '12:34:56:78:90:AB' in IEEE 802 canonical format would
- * be returned as 0x12345678ab.
- *
- * Depending upon the overall system design, a MAC address may or may not
- * be available for each interface. Note that the interface's MAC address
- * does not limit the packets received on its channel, although the
- * classifier's rules could be configured to do that. Similarly, the MAC
- * address is not used when transmitting packets, although applications
- * could certainly decide to use the assigned address as a source MAC
- * address when doing so. This attribute may only be retrieved with
- * gxio_mpipe_link_get_attr(); it may not be modified.
- */
-#define GXIO_MPIPE_LINK_MAC 0x040000
-
-/** Determine whether to discard egress packets on link down. If this value
- * is nonzero, packets sent on this link while the link is down will be
- * discarded. If this value is zero, no packets will be sent on this link
- * while it is down. The default value is one. */
-#define GXIO_MPIPE_LINK_DISCARD_IF_DOWN 0x050000
-
-/** Possible link state. The value is a combination of link state flags,
- * ORed together, that indicate link modes which are actually supported by
- * the hardware. This attribute may only be retrieved with
- * gxio_mpipe_link_get_attr(); it may not be modified. */
-#define GXIO_MPIPE_LINK_POSSIBLE_STATE 0x060000
-
-/** Current link state. The value is a combination of link state flags,
- * ORed together, that indicate the current state of the hardware. If the
- * link is down, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will be zero;
- * if the link is up, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will
- * result in exactly one of the speed values, indicating the current speed.
- * This attribute may only be retrieved with gxio_mpipe_link_get_attr(); it
- * may not be modified. */
-#define GXIO_MPIPE_LINK_CURRENT_STATE 0x070000
-
-/** Desired link state. The value is a conbination of flags, which specify
- * the desired state for the link. With gxio_mpipe_link_set_attr(), this
- * will, in the background, attempt to bring up the link using whichever of
- * the requested flags are reasonable, or take down the link if the flags
- * are zero. The actual link up or down operation may happen after this
- * call completes. If the link state changes in the future, the system
- * will continue to try to get back to the desired link state; for
- * instance, if the link is brought up successfully, and then the network
- * cable is disconnected, the link will go down. However, the desired
- * state of the link is still up, so if the cable is reconnected, the link
- * will be brought up again.
- *
- * With gxio_mpipe_link_set_attr(), this will indicate the desired state
- * for the link, as set with a previous gxio_mpipe_link_set_attr() call,
- * or implicitly by a gxio_mpipe_link_open() or link close operation.
- * This may not reflect the current state of the link; to get that, use
- * ::GXIO_MPIPE_LINK_CURRENT_STATE.
- */
-#define GXIO_MPIPE_LINK_DESIRED_STATE 0x080000
-
-
-
-/** Link can run, should run, or is running at 10 Mbps. */
-#define GXIO_MPIPE_LINK_10M 0x0000000000000001UL
-
-/** Link can run, should run, or is running at 100 Mbps. */
-#define GXIO_MPIPE_LINK_100M 0x0000000000000002UL
-
-/** Link can run, should run, or is running at 1 Gbps. */
-#define GXIO_MPIPE_LINK_1G 0x0000000000000004UL
-
-/** Link can run, should run, or is running at 10 Gbps. */
-#define GXIO_MPIPE_LINK_10G 0x0000000000000008UL
-
-/** Link can run, should run, or is running at 20 Gbps. */
-#define GXIO_MPIPE_LINK_20G 0x0000000000000010UL
-
-/** Link can run, should run, or is running at 25 Gbps. */
-#define GXIO_MPIPE_LINK_25G 0x0000000000000020UL
-
-/** Link can run, should run, or is running at 50 Gbps. */
-#define GXIO_MPIPE_LINK_50G 0x0000000000000040UL
-
-/** Link should run at the highest speed supported by the link and by
- * the device connected to the link. Only usable as a value for
- * the link's desired state; never returned as a value for the current
- * or possible states. */
-#define GXIO_MPIPE_LINK_ANYSPEED 0x0000000000000800UL
-
-/** All legal link speeds. This value is provided for use in extracting
- * the speed-related subset of the link state flags; it is not intended
- * to be set directly as a value for one of the GXIO_MPIPE_LINK_xxx_STATE
- * attributes. A link is up or is requested to be up if its current or
- * desired state, respectively, ANDED with this value, is nonzero. */
-#define GXIO_MPIPE_LINK_SPEED_MASK 0x0000000000000FFFUL
-
-/** Link can run, should run, or is running in MAC loopback mode. This
- * loops transmitted packets back to the receiver, inside the Tile
- * Processor. */
-#define GXIO_MPIPE_LINK_LOOP_MAC 0x0000000000001000UL
-
-/** Link can run, should run, or is running in PHY loopback mode. This
- * loops transmitted packets back to the receiver, inside the external
- * PHY chip. */
-#define GXIO_MPIPE_LINK_LOOP_PHY 0x0000000000002000UL
-
-/** Link can run, should run, or is running in external loopback mode.
- * This requires that an external loopback plug be installed on the
- * Ethernet port. Note that only some links require that this be
- * configured via the gxio_mpipe_link routines; other links can do
- * external loopack with the plug and no special configuration. */
-#define GXIO_MPIPE_LINK_LOOP_EXT 0x0000000000004000UL
-
-/** All legal loopback types. */
-#define GXIO_MPIPE_LINK_LOOP_MASK 0x000000000000F000UL
-
-/** Link can run, should run, or is running in full-duplex mode.
- * If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
- * specified in a set of desired state flags, both are assumed. */
-#define GXIO_MPIPE_LINK_FDX 0x0000000000010000UL
-
-/** Link can run, should run, or is running in half-duplex mode.
- * If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
- * specified in a set of desired state flags, both are assumed. */
-#define GXIO_MPIPE_LINK_HDX 0x0000000000020000UL
-
-
-/** An individual rule. */
-typedef struct
-{
- /** The total size. */
- uint16_t size;
-
- /** The priority. */
- int16_t priority;
-
- /** The "headroom" in each buffer. */
- uint8_t headroom;
-
- /** The "tailroom" in each buffer. */
- uint8_t tailroom;
-
- /** The "capacity" of the largest buffer. */
- uint16_t capacity;
-
- /** The mask for converting a flow hash into a bucket. */
- uint16_t bucket_mask;
-
- /** The offset for converting a flow hash into a bucket. */
- uint16_t bucket_first;
-
- /** The buffer stack ids. */
- gxio_mpipe_rules_stacks_t stacks;
-
- /** The actual channels. */
- uint32_t channel_bits;
-
- /** The number of dmacs. */
- uint16_t num_dmacs;
-
- /** The number of vlans. */
- uint16_t num_vlans;
-
- /** The actual dmacs and vlans. */
- uint8_t dmacs_and_vlans[];
-
-} gxio_mpipe_rules_rule_t;
-
-
-/** A list of classifier rules. */
-typedef struct
-{
- /** The offset to the end of the current rule. */
- uint16_t tail;
-
- /** The offset to the start of the current rule. */
- uint16_t head;
-
- /** The actual rules. */
- uint8_t rules[4096 - 4];
-
-} gxio_mpipe_rules_list_t;
-
-
-
-
-/** mPIPE statistics structure. These counters include all relevant
- * events occurring on all links within the mPIPE shim. */
-typedef struct
-{
- /** Number of ingress packets dropped for any reason. */
- uint64_t ingress_drops;
- /** Number of ingress packets dropped because a buffer stack was empty. */
- uint64_t ingress_drops_no_buf;
- /** Number of ingress packets dropped or truncated due to lack of space in
- * the iPkt buffer. */
- uint64_t ingress_drops_ipkt;
- /** Number of ingress packets dropped by the classifier or load balancer */
- uint64_t ingress_drops_cls_lb;
- /** Total number of ingress packets. */
- uint64_t ingress_packets;
- /** Total number of egress packets. */
- uint64_t egress_packets;
- /** Total number of ingress bytes. */
- uint64_t ingress_bytes;
- /** Total number of egress bytes. */
- uint64_t egress_bytes;
-}
-gxio_mpipe_stats_t;
-
-
-#endif /* _SYS_HV_DRV_MPIPE_INTF_H */
diff --git a/arch/tile/include/hv/drv_mshim_intf.h b/arch/tile/include/hv/drv_mshim_intf.h
deleted file mode 100644
index c6ef3bdc55cf..000000000000
--- a/arch/tile/include/hv/drv_mshim_intf.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file drv_mshim_intf.h
- * Interface definitions for the Linux EDAC memory controller driver.
- */
-
-#ifndef _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H
-#define _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H
-
-/** Number of memory controllers in the public API. */
-#define TILE_MAX_MSHIMS 4
-
-/** Memory info under each memory controller. */
-struct mshim_mem_info
-{
- uint64_t mem_size; /**< Total memory size in bytes. */
- uint8_t mem_type; /**< Memory type, DDR2 or DDR3. */
- uint8_t mem_ecc; /**< Memory supports ECC. */
-};
-
-/**
- * DIMM error structure.
- * For now, only correctable errors are counted and the mshim doesn't record
- * the error PA. HV takes panic upon uncorrectable errors.
- */
-struct mshim_mem_error
-{
- uint32_t sbe_count; /**< Number of single-bit errors. */
-};
-
-/** Read this offset to get the memory info per mshim. */
-#define MSHIM_MEM_INFO_OFF 0x100
-
-/** Read this offset to check DIMM error. */
-#define MSHIM_MEM_ERROR_OFF 0x200
-
-#endif /* _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H */
diff --git a/arch/tile/include/hv/drv_pcie_rc_intf.h b/arch/tile/include/hv/drv_pcie_rc_intf.h
deleted file mode 100644
index 9bd2243bece0..000000000000
--- a/arch/tile/include/hv/drv_pcie_rc_intf.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file drv_pcie_rc_intf.h
- * Interface definitions for the PCIE Root Complex.
- */
-
-#ifndef _SYS_HV_DRV_PCIE_RC_INTF_H
-#define _SYS_HV_DRV_PCIE_RC_INTF_H
-
-/** File offset for reading the interrupt base number used for PCIE legacy
- interrupts and PLX Gen 1 requirement flag */
-#define PCIE_RC_CONFIG_MASK_OFF 0
-
-
-/**
- * Structure used for obtaining PCIe config information, read from the PCIE
- * subsystem /ctl file at initialization
- */
-typedef struct pcie_rc_config
-{
- int intr; /**< interrupt number used for downcall */
- int plx_gen1; /**< flag for PLX Gen 1 configuration */
-} pcie_rc_config_t;
-
-#endif /* _SYS_HV_DRV_PCIE_RC_INTF_H */
diff --git a/arch/tile/include/hv/drv_srom_intf.h b/arch/tile/include/hv/drv_srom_intf.h
deleted file mode 100644
index 6395faa6d9e6..000000000000
--- a/arch/tile/include/hv/drv_srom_intf.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file drv_srom_intf.h
- * Interface definitions for the SPI Flash ROM driver.
- */
-
-#ifndef _SYS_HV_INCLUDE_DRV_SROM_INTF_H
-#define _SYS_HV_INCLUDE_DRV_SROM_INTF_H
-
-/** Read this offset to get the total device size. */
-#define SROM_TOTAL_SIZE_OFF 0xF0000000
-
-/** Read this offset to get the device sector size. */
-#define SROM_SECTOR_SIZE_OFF 0xF0000004
-
-/** Read this offset to get the device page size. */
-#define SROM_PAGE_SIZE_OFF 0xF0000008
-
-/** Write this offset to flush any pending writes. */
-#define SROM_FLUSH_OFF 0xF1000000
-
-/** Write this offset, plus the byte offset of the start of a sector, to
- * erase a sector. Any write data is ignored, but there must be at least
- * one byte of write data. Only applies when the driver is in MTD mode.
- */
-#define SROM_ERASE_OFF 0xF2000000
-
-#endif /* _SYS_HV_INCLUDE_DRV_SROM_INTF_H */
diff --git a/arch/tile/include/hv/drv_trio_intf.h b/arch/tile/include/hv/drv_trio_intf.h
deleted file mode 100644
index 237e04dee66c..000000000000
--- a/arch/tile/include/hv/drv_trio_intf.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * Interface definitions for the trio driver.
- */
-
-#ifndef _SYS_HV_DRV_TRIO_INTF_H
-#define _SYS_HV_DRV_TRIO_INTF_H
-
-#include <arch/trio.h>
-
-/** The vendor ID for all Tilera processors. */
-#define TILERA_VENDOR_ID 0x1a41
-
-/** The device ID for the Gx36 processor. */
-#define TILERA_GX36_DEV_ID 0x0200
-
-/** Device ID for our internal bridge when running as RC. */
-#define TILERA_GX36_RC_DEV_ID 0x2000
-
-/** Maximum number of TRIO interfaces. */
-#define TILEGX_NUM_TRIO 2
-
-/** Gx36 has max 3 PCIe MACs per TRIO interface. */
-#define TILEGX_TRIO_PCIES 3
-
-/** Specify port properties for a PCIe MAC. */
-struct pcie_port_property
-{
- /** If true, the link can be configured in PCIe root complex mode. */
- uint8_t allow_rc: 1;
-
- /** If true, the link can be configured in PCIe endpoint mode. */
- uint8_t allow_ep: 1;
-
- /** If true, the link can be configured in StreamIO mode. */
- uint8_t allow_sio: 1;
-
- /** If true, the link is allowed to support 1-lane operation. Software
- * will not consider it an error if the link comes up as a x1 link. */
- uint8_t allow_x1: 1;
-
- /** If true, the link is allowed to support 2-lane operation. Software
- * will not consider it an error if the link comes up as a x2 link. */
- uint8_t allow_x2: 1;
-
- /** If true, the link is allowed to support 4-lane operation. Software
- * will not consider it an error if the link comes up as a x4 link. */
- uint8_t allow_x4: 1;
-
- /** If true, the link is allowed to support 8-lane operation. Software
- * will not consider it an error if the link comes up as a x8 link. */
- uint8_t allow_x8: 1;
-
- /** If true, this link is connected to a device which may or may not
- * be present. */
- uint8_t removable: 1;
-
-};
-
-/** Configurations can be issued to configure a char stream interrupt. */
-typedef enum pcie_stream_intr_config_sel_e
-{
- /** Interrupt configuration for memory map regions. */
- MEM_MAP_SEL,
-
- /** Interrupt configuration for push DMAs. */
- PUSH_DMA_SEL,
-
- /** Interrupt configuration for pull DMAs. */
- PULL_DMA_SEL,
-}
-pcie_stream_intr_config_sel_t;
-
-
-/** The mmap file offset (PA) of the TRIO config region. */
-#define HV_TRIO_CONFIG_OFFSET \
- ((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_CFG << \
- TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT)
-
-/** The maximum size of the TRIO config region. */
-#define HV_TRIO_CONFIG_SIZE \
- (1ULL << TRIO_CFG_REGION_ADDR__REGION_SHIFT)
-
-/** Size of the config region mapped into client. We can't use
- * TRIO_MMIO_ADDRESS_SPACE__OFFSET_WIDTH because it
- * will require the kernel to allocate 4GB VA space
- * from the VMALLOC region which has a total range
- * of 4GB.
- */
-#define HV_TRIO_CONFIG_IOREMAP_SIZE \
- ((uint64_t) 1 << TRIO_CFG_REGION_ADDR__PROT_SHIFT)
-
-/** The mmap file offset (PA) of a scatter queue region. */
-#define HV_TRIO_SQ_OFFSET(queue) \
- (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_SQ << \
- TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
- ((queue) << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT))
-
-/** The maximum size of a scatter queue region. */
-#define HV_TRIO_SQ_SIZE \
- (1ULL << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT)
-
-
-/** The "hardware MMIO region" of the first PIO region. */
-#define HV_TRIO_FIRST_PIO_REGION 8
-
-/** The mmap file offset (PA) of a PIO region. */
-#define HV_TRIO_PIO_OFFSET(region) \
- (((unsigned long long)(region) + HV_TRIO_FIRST_PIO_REGION) \
- << TRIO_PIO_REGIONS_ADDR__REGION_SHIFT)
-
-/** The maximum size of a PIO region. */
-#define HV_TRIO_PIO_SIZE (1ULL << TRIO_PIO_REGIONS_ADDR__ADDR_WIDTH)
-
-
-/** The mmap file offset (PA) of a push DMA region. */
-#define HV_TRIO_PUSH_DMA_OFFSET(ring) \
- (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PUSH_DMA << \
- TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
- ((ring) << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT))
-
-/** The mmap file offset (PA) of a pull DMA region. */
-#define HV_TRIO_PULL_DMA_OFFSET(ring) \
- (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PULL_DMA << \
- TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
- ((ring) << TRIO_PULL_DMA_REGION_ADDR__RING_SEL_SHIFT))
-
-/** The maximum size of a DMA region. */
-#define HV_TRIO_DMA_REGION_SIZE \
- (1ULL << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT)
-
-
-/** The mmap file offset (PA) of a Mem-Map interrupt region. */
-#define HV_TRIO_MEM_MAP_INTR_OFFSET(map) \
- (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_MEM << \
- TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
- ((map) << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT))
-
-/** The maximum size of a Mem-Map interrupt region. */
-#define HV_TRIO_MEM_MAP_INTR_SIZE \
- (1ULL << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT)
-
-
-/** A flag bit indicating a fixed resource allocation. */
-#define HV_TRIO_ALLOC_FIXED 0x01
-
-/** TRIO requires that all mappings have 4kB aligned start addresses. */
-#define HV_TRIO_PAGE_SHIFT 12
-
-/** TRIO requires that all mappings have 4kB aligned start addresses. */
-#define HV_TRIO_PAGE_SIZE (1ull << HV_TRIO_PAGE_SHIFT)
-
-
-/* Specify all PCIe port properties for a TRIO. */
-struct pcie_trio_ports_property
-{
- struct pcie_port_property ports[TILEGX_TRIO_PCIES];
-
- /** Set if this TRIO belongs to a Gx72 device. */
- uint8_t is_gx72;
-};
-
-/* Flags indicating traffic class. */
-#define HV_TRIO_FLAG_TC_SHIFT 4
-#define HV_TRIO_FLAG_TC_RMASK 0xf
-#define HV_TRIO_FLAG_TC(N) \
- ((((N) & HV_TRIO_FLAG_TC_RMASK) + 1) << HV_TRIO_FLAG_TC_SHIFT)
-
-/* Flags indicating virtual functions. */
-#define HV_TRIO_FLAG_VFUNC_SHIFT 8
-#define HV_TRIO_FLAG_VFUNC_RMASK 0xff
-#define HV_TRIO_FLAG_VFUNC(N) \
- ((((N) & HV_TRIO_FLAG_VFUNC_RMASK) + 1) << HV_TRIO_FLAG_VFUNC_SHIFT)
-
-
-/* Flag indicating an ordered PIO region. */
-#define HV_TRIO_PIO_FLAG_ORDERED (1 << 16)
-
-/* Flags indicating special types of PIO regions. */
-#define HV_TRIO_PIO_FLAG_SPACE_SHIFT 17
-#define HV_TRIO_PIO_FLAG_SPACE_MASK (0x3 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
-#define HV_TRIO_PIO_FLAG_CONFIG_SPACE (0x1 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
-#define HV_TRIO_PIO_FLAG_IO_SPACE (0x2 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
-
-
-#endif /* _SYS_HV_DRV_TRIO_INTF_H */
diff --git a/arch/tile/include/hv/drv_uart_intf.h b/arch/tile/include/hv/drv_uart_intf.h
deleted file mode 100644
index f5379e2404fd..000000000000
--- a/arch/tile/include/hv/drv_uart_intf.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * Interface definitions for the UART driver.
- */
-
-#ifndef _SYS_HV_DRV_UART_INTF_H
-#define _SYS_HV_DRV_UART_INTF_H
-
-#include <arch/uart.h>
-
-/** Number of UART ports supported. */
-#define TILEGX_UART_NR 2
-
-/** The mmap file offset (PA) of the UART MMIO region. */
-#define HV_UART_MMIO_OFFSET 0
-
-/** The maximum size of the UARTs MMIO region (64K Bytes). */
-#define HV_UART_MMIO_SIZE (1UL << 16)
-
-#endif /* _SYS_HV_DRV_UART_INTF_H */
diff --git a/arch/tile/include/hv/drv_usb_host_intf.h b/arch/tile/include/hv/drv_usb_host_intf.h
deleted file mode 100644
index 24ce774a3f1d..000000000000
--- a/arch/tile/include/hv/drv_usb_host_intf.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * Interface definitions for the USB host driver.
- */
-
-#ifndef _SYS_HV_DRV_USB_HOST_INTF_H
-#define _SYS_HV_DRV_USB_HOST_INTF_H
-
-#include <arch/usb_host.h>
-
-
-/** Offset for the EHCI register MMIO region. */
-#define HV_USB_HOST_MMIO_OFFSET_EHCI ((uint64_t) USB_HOST_HCCAPBASE_REG)
-
-/** Offset for the OHCI register MMIO region. */
-#define HV_USB_HOST_MMIO_OFFSET_OHCI ((uint64_t) USB_HOST_OHCD_HC_REVISION_REG)
-
-/** Size of the register MMIO region. This turns out to be the same for
- * both EHCI and OHCI. */
-#define HV_USB_HOST_MMIO_SIZE ((uint64_t) 0x1000)
-
-/** The number of service domains supported by the USB host shim. */
-#define HV_USB_HOST_NUM_SVC_DOM 1
-
-
-#endif /* _SYS_HV_DRV_USB_HOST_INTF_H */
diff --git a/arch/tile/include/hv/drv_xgbe_impl.h b/arch/tile/include/hv/drv_xgbe_impl.h
deleted file mode 100644
index 3a73b2b44913..000000000000
--- a/arch/tile/include/hv/drv_xgbe_impl.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file drivers/xgbe/impl.h
- * Implementation details for the NetIO library.
- */
-
-#ifndef __DRV_XGBE_IMPL_H__
-#define __DRV_XGBE_IMPL_H__
-
-#include <hv/netio_errors.h>
-#include <hv/netio_intf.h>
-#include <hv/drv_xgbe_intf.h>
-
-
-/** How many groups we have (log2). */
-#define LOG2_NUM_GROUPS (12)
-/** How many groups we have. */
-#define NUM_GROUPS (1 << LOG2_NUM_GROUPS)
-
-/** Number of output requests we'll buffer per tile. */
-#define EPP_REQS_PER_TILE (32)
-
-/** Words used in an eDMA command without checksum acceleration. */
-#define EDMA_WDS_NO_CSUM 8
-/** Words used in an eDMA command with checksum acceleration. */
-#define EDMA_WDS_CSUM 10
-/** Total available words in the eDMA command FIFO. */
-#define EDMA_WDS_TOTAL 128
-
-
-/*
- * FIXME: These definitions are internal and should have underscores!
- * NOTE: The actual numeric values here are intentional and allow us to
- * optimize the concept "if small ... else if large ... else ...", by
- * checking for the low bit being set, and then for non-zero.
- * These are used as array indices, so they must have the values (0, 1, 2)
- * in some order.
- */
-#define SIZE_SMALL (1) /**< Small packet queue. */
-#define SIZE_LARGE (2) /**< Large packet queue. */
-#define SIZE_JUMBO (0) /**< Jumbo packet queue. */
-
-/** The number of "SIZE_xxx" values. */
-#define NETIO_NUM_SIZES 3
-
-
-/*
- * Default numbers of packets for IPP drivers. These values are chosen
- * such that CIPP1 will not overflow its L2 cache.
- */
-
-/** The default number of small packets. */
-#define NETIO_DEFAULT_SMALL_PACKETS 2750
-/** The default number of large packets. */
-#define NETIO_DEFAULT_LARGE_PACKETS 2500
-/** The default number of jumbo packets. */
-#define NETIO_DEFAULT_JUMBO_PACKETS 250
-
-
-/** Log2 of the size of a memory arena. */
-#define NETIO_ARENA_SHIFT 24 /* 16 MB */
-/** Size of a memory arena. */
-#define NETIO_ARENA_SIZE (1 << NETIO_ARENA_SHIFT)
-
-
-/** A queue of packets.
- *
- * This structure partially defines a queue of packets waiting to be
- * processed. The queue as a whole is written to by an interrupt handler and
- * read by non-interrupt code; this data structure is what's touched by the
- * interrupt handler. The other part of the queue state, the read offset, is
- * kept in user space, not in hypervisor space, so it is in a separate data
- * structure.
- *
- * The read offset (__packet_receive_read in the user part of the queue
- * structure) points to the next packet to be read. When the read offset is
- * equal to the write offset, the queue is empty; therefore the queue must
- * contain one more slot than the required maximum queue size.
- *
- * Here's an example of all 3 state variables and what they mean. All
- * pointers move left to right.
- *
- * @code
- * I I V V V V I I I I
- * 0 1 2 3 4 5 6 7 8 9 10
- * ^ ^ ^ ^
- * | | |
- * | | __last_packet_plus_one
- * | __buffer_write
- * __packet_receive_read
- * @endcode
- *
- * This queue has 10 slots, and thus can hold 9 packets (_last_packet_plus_one
- * = 10). The read pointer is at 2, and the write pointer is at 6; thus,
- * there are valid, unread packets in slots 2, 3, 4, and 5. The remaining
- * slots are invalid (do not contain a packet).
- */
-typedef struct {
- /** Byte offset of the next notify packet to be written: zero for the first
- * packet on the queue, sizeof (netio_pkt_t) for the second packet on the
- * queue, etc. */
- volatile uint32_t __packet_write;
-
- /** Offset of the packet after the last valid packet (i.e., when any
- * pointer is incremented to this value, it wraps back to zero). */
- uint32_t __last_packet_plus_one;
-}
-__netio_packet_queue_t;
-
-
-/** A queue of buffers.
- *
- * This structure partially defines a queue of empty buffers which have been
- * obtained via requests to the IPP. (The elements of the queue are packet
- * handles, which are transformed into a full netio_pkt_t when the buffer is
- * retrieved.) The queue as a whole is written to by an interrupt handler and
- * read by non-interrupt code; this data structure is what's touched by the
- * interrupt handler. The other parts of the queue state, the read offset and
- * requested write offset, are kept in user space, not in hypervisor space, so
- * they are in a separate data structure.
- *
- * The read offset (__buffer_read in the user part of the queue structure)
- * points to the next buffer to be read. When the read offset is equal to the
- * write offset, the queue is empty; therefore the queue must contain one more
- * slot than the required maximum queue size.
- *
- * The requested write offset (__buffer_requested_write in the user part of
- * the queue structure) points to the slot which will hold the next buffer we
- * request from the IPP, once we get around to sending such a request. When
- * the requested write offset is equal to the write offset, no requests for
- * new buffers are outstanding; when the requested write offset is one greater
- * than the read offset, no more requests may be sent.
- *
- * Note that, unlike the packet_queue, the buffer_queue places incoming
- * buffers at decreasing addresses. This makes the check for "is it time to
- * wrap the buffer pointer" cheaper in the assembly code which receives new
- * buffers, and means that the value which defines the queue size,
- * __last_buffer, is different than in the packet queue. Also, the offset
- * used in the packet_queue is already scaled by the size of a packet; here we
- * use unscaled slot indices for the offsets. (These differences are
- * historical, and in the future it's possible that the packet_queue will look
- * more like this queue.)
- *
- * @code
- * Here's an example of all 4 state variables and what they mean. Remember:
- * all pointers move right to left.
- *
- * V V V I I R R V V V
- * 0 1 2 3 4 5 6 7 8 9
- * ^ ^ ^ ^
- * | | | |
- * | | | __last_buffer
- * | | __buffer_write
- * | __buffer_requested_write
- * __buffer_read
- * @endcode
- *
- * This queue has 10 slots, and thus can hold 9 buffers (_last_buffer = 9).
- * The read pointer is at 2, and the write pointer is at 6; thus, there are
- * valid, unread buffers in slots 2, 1, 0, 9, 8, and 7. The requested write
- * pointer is at 4; thus, requests have been made to the IPP for buffers which
- * will be placed in slots 6 and 5 when they arrive. Finally, the remaining
- * slots are invalid (do not contain a buffer).
- */
-typedef struct
-{
- /** Ordinal number of the next buffer to be written: 0 for the first slot in
- * the queue, 1 for the second slot in the queue, etc. */
- volatile uint32_t __buffer_write;
-
- /** Ordinal number of the last buffer (i.e., when any pointer is decremented
- * below zero, it is reloaded with this value). */
- uint32_t __last_buffer;
-}
-__netio_buffer_queue_t;
-
-
-/**
- * An object for providing Ethernet packets to a process.
- */
-typedef struct __netio_queue_impl_t
-{
- /** The queue of packets waiting to be received. */
- __netio_packet_queue_t __packet_receive_queue;
- /** The intr bit mask that IDs this device. */
- unsigned int __intr_id;
- /** Offset to queues of empty buffers, one per size. */
- uint32_t __buffer_queue[NETIO_NUM_SIZES];
- /** The address of the first EPP tile, or -1 if no EPP. */
- /* ISSUE: Actually this is always "0" or "~0". */
- uint32_t __epp_location;
- /** The queue ID that this queue represents. */
- unsigned int __queue_id;
- /** Number of acknowledgements received. */
- volatile uint32_t __acks_received;
- /** Last completion number received for packet_sendv. */
- volatile uint32_t __last_completion_rcv;
- /** Number of packets allowed to be outstanding. */
- uint32_t __max_outstanding;
- /** First VA available for packets. */
- void* __va_0;
- /** First VA in second range available for packets. */
- void* __va_1;
- /** Padding to align the "__packets" field to the size of a netio_pkt_t. */
- uint32_t __padding[3];
- /** The packets themselves. */
- netio_pkt_t __packets[0];
-}
-netio_queue_impl_t;
-
-
-/**
- * An object for managing the user end of a NetIO queue.
- */
-typedef struct __netio_queue_user_impl_t
-{
- /** The next incoming packet to be read. */
- uint32_t __packet_receive_read;
- /** The next empty buffers to be read, one index per size. */
- uint8_t __buffer_read[NETIO_NUM_SIZES];
- /** Where the empty buffer we next request from the IPP will go, one index
- * per size. */
- uint8_t __buffer_requested_write[NETIO_NUM_SIZES];
- /** PCIe interface flag. */
- uint8_t __pcie;
- /** Number of packets left to be received before we send a credit update. */
- uint32_t __receive_credit_remaining;
- /** Value placed in __receive_credit_remaining when it reaches zero. */
- uint32_t __receive_credit_interval;
- /** First fast I/O routine index. */
- uint32_t __fastio_index;
- /** Number of acknowledgements expected. */
- uint32_t __acks_outstanding;
- /** Last completion number requested. */
- uint32_t __last_completion_req;
- /** File descriptor for driver. */
- int __fd;
-}
-netio_queue_user_impl_t;
-
-
-#define NETIO_GROUP_CHUNK_SIZE 64 /**< Max # groups in one IPP request */
-#define NETIO_BUCKET_CHUNK_SIZE 64 /**< Max # buckets in one IPP request */
-
-
-/** Internal structure used to convey packet send information to the
- * hypervisor. FIXME: Actually, it's not used for that anymore, but
- * netio_packet_send() still uses it internally.
- */
-typedef struct
-{
- uint16_t flags; /**< Packet flags (__NETIO_SEND_FLG_xxx) */
- uint16_t transfer_size; /**< Size of packet */
- uint32_t va; /**< VA of start of packet */
- __netio_pkt_handle_t handle; /**< Packet handle */
- uint32_t csum0; /**< First checksum word */
- uint32_t csum1; /**< Second checksum word */
-}
-__netio_send_cmd_t;
-
-
-/** Flags used in two contexts:
- * - As the "flags" member in the __netio_send_cmd_t, above; used only
- * for netio_pkt_send_{prepare,commit}.
- * - As part of the flags passed to the various send packet fast I/O calls.
- */
-
-/** Need acknowledgement on this packet. Note that some code in the
- * normal send_pkt fast I/O handler assumes that this is equal to 1. */
-#define __NETIO_SEND_FLG_ACK 0x1
-
-/** Do checksum on this packet. (Only used with the __netio_send_cmd_t;
- * normal packet sends use a special fast I/O index to denote checksumming,
- * and multi-segment sends test the checksum descriptor.) */
-#define __NETIO_SEND_FLG_CSUM 0x2
-
-/** Get a completion on this packet. Only used with multi-segment sends. */
-#define __NETIO_SEND_FLG_COMPLETION 0x4
-
-/** Position of the number-of-extra-segments value in the flags word.
- Only used with multi-segment sends. */
-#define __NETIO_SEND_FLG_XSEG_SHIFT 3
-
-/** Width of the number-of-extra-segments value in the flags word. */
-#define __NETIO_SEND_FLG_XSEG_WIDTH 2
-
-#endif /* __DRV_XGBE_IMPL_H__ */
diff --git a/arch/tile/include/hv/drv_xgbe_intf.h b/arch/tile/include/hv/drv_xgbe_intf.h
deleted file mode 100644
index 2a20b266d944..000000000000
--- a/arch/tile/include/hv/drv_xgbe_intf.h
+++ /dev/null
@@ -1,615 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file drv_xgbe_intf.h
- * Interface to the hypervisor XGBE driver.
- */
-
-#ifndef __DRV_XGBE_INTF_H__
-#define __DRV_XGBE_INTF_H__
-
-/**
- * An object for forwarding VAs and PAs to the hypervisor.
- * @ingroup types
- *
- * This allows the supervisor to specify a number of areas of memory to
- * store packet buffers.
- */
-typedef struct
-{
- /** The physical address of the memory. */
- HV_PhysAddr pa;
- /** Page table entry for the memory. This is only used to derive the
- * memory's caching mode; the PA bits are ignored. */
- HV_PTE pte;
- /** The virtual address of the memory. */
- HV_VirtAddr va;
- /** Size (in bytes) of the memory area. */
- int size;
-
-}
-netio_ipp_address_t;
-
-/** The various pread/pwrite offsets into the hypervisor-level driver.
- * @ingroup types
- */
-typedef enum
-{
- /** Inform the Linux driver of the address of the NetIO arena memory.
- * This offset is actually only used to convey information from netio
- * to the Linux driver; it never makes it from there to the hypervisor.
- * Write-only; takes a uint32_t specifying the VA address. */
- NETIO_FIXED_ADDR = 0x5000000000000000ULL,
-
- /** Inform the Linux driver of the size of the NetIO arena memory.
- * This offset is actually only used to convey information from netio
- * to the Linux driver; it never makes it from there to the hypervisor.
- * Write-only; takes a uint32_t specifying the VA size. */
- NETIO_FIXED_SIZE = 0x5100000000000000ULL,
-
- /** Register current tile with IPP. Write then read: write, takes a
- * netio_input_config_t, read returns a pointer to a netio_queue_impl_t. */
- NETIO_IPP_INPUT_REGISTER_OFF = 0x6000000000000000ULL,
-
- /** Unregister current tile from IPP. Write-only, takes a dummy argument. */
- NETIO_IPP_INPUT_UNREGISTER_OFF = 0x6100000000000000ULL,
-
- /** Start packets flowing. Write-only, takes a dummy argument. */
- NETIO_IPP_INPUT_INIT_OFF = 0x6200000000000000ULL,
-
- /** Stop packets flowing. Write-only, takes a dummy argument. */
- NETIO_IPP_INPUT_UNINIT_OFF = 0x6300000000000000ULL,
-
- /** Configure group (typically we group on VLAN). Write-only: takes an
- * array of netio_group_t's, low 24 bits of the offset is the base group
- * number times the size of a netio_group_t. */
- NETIO_IPP_INPUT_GROUP_CFG_OFF = 0x6400000000000000ULL,
-
- /** Configure bucket. Write-only: takes an array of netio_bucket_t's, low
- * 24 bits of the offset is the base bucket number times the size of a
- * netio_bucket_t. */
- NETIO_IPP_INPUT_BUCKET_CFG_OFF = 0x6500000000000000ULL,
-
- /** Get/set a parameter. Read or write: read or write data is the parameter
- * value, low 32 bits of the offset is a __netio_getset_offset_t. */
- NETIO_IPP_PARAM_OFF = 0x6600000000000000ULL,
-
- /** Get fast I/O index. Read-only; returns a 4-byte base index value. */
- NETIO_IPP_GET_FASTIO_OFF = 0x6700000000000000ULL,
-
- /** Configure hijack IP address. Packets with this IPv4 dest address
- * go to bucket NETIO_NUM_BUCKETS - 1. Write-only: takes an IP address
- * in some standard form. FIXME: Define the form! */
- NETIO_IPP_INPUT_HIJACK_CFG_OFF = 0x6800000000000000ULL,
-
- /**
- * Offsets beyond this point are reserved for the supervisor (although that
- * enforcement must be done by the supervisor driver itself).
- */
- NETIO_IPP_USER_MAX_OFF = 0x6FFFFFFFFFFFFFFFULL,
-
- /** Register I/O memory. Write-only, takes a netio_ipp_address_t. */
- NETIO_IPP_IOMEM_REGISTER_OFF = 0x7000000000000000ULL,
-
- /** Unregister I/O memory. Write-only, takes a netio_ipp_address_t. */
- NETIO_IPP_IOMEM_UNREGISTER_OFF = 0x7100000000000000ULL,
-
- /* Offsets greater than 0x7FFFFFFF can't be used directly from Linux
- * userspace code due to limitations in the pread/pwrite syscalls. */
-
- /** Drain LIPP buffers. */
- NETIO_IPP_DRAIN_OFF = 0xFA00000000000000ULL,
-
- /** Supply a netio_ipp_address_t to be used as shared memory for the
- * LEPP command queue. */
- NETIO_EPP_SHM_OFF = 0xFB00000000000000ULL,
-
- /* 0xFC... is currently unused. */
-
- /** Stop IPP/EPP tiles. Write-only, takes a dummy argument. */
- NETIO_IPP_STOP_SHIM_OFF = 0xFD00000000000000ULL,
-
- /** Start IPP/EPP tiles. Write-only, takes a dummy argument. */
- NETIO_IPP_START_SHIM_OFF = 0xFE00000000000000ULL,
-
- /** Supply packet arena. Write-only, takes an array of
- * netio_ipp_address_t values. */
- NETIO_IPP_ADDRESS_OFF = 0xFF00000000000000ULL,
-} netio_hv_offset_t;
-
-/** Extract the base offset from an offset */
-#define NETIO_BASE_OFFSET(off) ((off) & 0xFF00000000000000ULL)
-/** Extract the local offset from an offset */
-#define NETIO_LOCAL_OFFSET(off) ((off) & 0x00FFFFFFFFFFFFFFULL)
-
-
-/**
- * Get/set offset.
- */
-typedef union
-{
- struct
- {
- uint64_t addr:48; /**< Class-specific address */
- unsigned int class:8; /**< Class (e.g., NETIO_PARAM) */
- unsigned int opcode:8; /**< High 8 bits of NETIO_IPP_PARAM_OFF */
- }
- bits; /**< Bitfields */
- uint64_t word; /**< Aggregated value to use as the offset */
-}
-__netio_getset_offset_t;
-
-/**
- * Fast I/O index offsets (must be contiguous).
- */
-typedef enum
-{
- NETIO_FASTIO_ALLOCATE = 0, /**< Get empty packet buffer */
- NETIO_FASTIO_FREE_BUFFER = 1, /**< Give buffer back to IPP */
- NETIO_FASTIO_RETURN_CREDITS = 2, /**< Give credits to IPP */
- NETIO_FASTIO_SEND_PKT_NOCK = 3, /**< Send a packet, no checksum */
- NETIO_FASTIO_SEND_PKT_CK = 4, /**< Send a packet, with checksum */
- NETIO_FASTIO_SEND_PKT_VEC = 5, /**< Send a vector of packets */
- NETIO_FASTIO_SENDV_PKT = 6, /**< Sendv one packet */
- NETIO_FASTIO_NUM_INDEX = 7, /**< Total number of fast I/O indices */
-} netio_fastio_index_t;
-
-/** 3-word return type for Fast I/O call. */
-typedef struct
-{
- int err; /**< Error code. */
- uint32_t val0; /**< Value. Meaning depends upon the specific call. */
- uint32_t val1; /**< Value. Meaning depends upon the specific call. */
-} netio_fastio_rv3_t;
-
-/** 0-argument fast I/O call */
-int __netio_fastio0(uint32_t fastio_index);
-/** 1-argument fast I/O call */
-int __netio_fastio1(uint32_t fastio_index, uint32_t arg0);
-/** 3-argument fast I/O call, 2-word return value */
-netio_fastio_rv3_t __netio_fastio3_rv3(uint32_t fastio_index, uint32_t arg0,
- uint32_t arg1, uint32_t arg2);
-/** 4-argument fast I/O call */
-int __netio_fastio4(uint32_t fastio_index, uint32_t arg0, uint32_t arg1,
- uint32_t arg2, uint32_t arg3);
-/** 6-argument fast I/O call */
-int __netio_fastio6(uint32_t fastio_index, uint32_t arg0, uint32_t arg1,
- uint32_t arg2, uint32_t arg3, uint32_t arg4, uint32_t arg5);
-/** 9-argument fast I/O call */
-int __netio_fastio9(uint32_t fastio_index, uint32_t arg0, uint32_t arg1,
- uint32_t arg2, uint32_t arg3, uint32_t arg4, uint32_t arg5,
- uint32_t arg6, uint32_t arg7, uint32_t arg8);
-
-/** Allocate an empty packet.
- * @param fastio_index Fast I/O index.
- * @param size Size of the packet to allocate.
- */
-#define __netio_fastio_allocate(fastio_index, size) \
- __netio_fastio1((fastio_index) + NETIO_FASTIO_ALLOCATE, size)
-
-/** Free a buffer.
- * @param fastio_index Fast I/O index.
- * @param handle Handle for the packet to free.
- */
-#define __netio_fastio_free_buffer(fastio_index, handle) \
- __netio_fastio1((fastio_index) + NETIO_FASTIO_FREE_BUFFER, handle)
-
-/** Increment our receive credits.
- * @param fastio_index Fast I/O index.
- * @param credits Number of credits to add.
- */
-#define __netio_fastio_return_credits(fastio_index, credits) \
- __netio_fastio1((fastio_index) + NETIO_FASTIO_RETURN_CREDITS, credits)
-
-/** Send packet, no checksum.
- * @param fastio_index Fast I/O index.
- * @param ackflag Nonzero if we want an ack.
- * @param size Size of the packet.
- * @param va Virtual address of start of packet.
- * @param handle Packet handle.
- */
-#define __netio_fastio_send_pkt_nock(fastio_index, ackflag, size, va, handle) \
- __netio_fastio4((fastio_index) + NETIO_FASTIO_SEND_PKT_NOCK, ackflag, \
- size, va, handle)
-
-/** Send packet, calculate checksum.
- * @param fastio_index Fast I/O index.
- * @param ackflag Nonzero if we want an ack.
- * @param size Size of the packet.
- * @param va Virtual address of start of packet.
- * @param handle Packet handle.
- * @param csum0 Shim checksum header.
- * @param csum1 Checksum seed.
- */
-#define __netio_fastio_send_pkt_ck(fastio_index, ackflag, size, va, handle, \
- csum0, csum1) \
- __netio_fastio6((fastio_index) + NETIO_FASTIO_SEND_PKT_CK, ackflag, \
- size, va, handle, csum0, csum1)
-
-
-/** Format for the "csum0" argument to the __netio_fastio_send routines
- * and LEPP. Note that this is currently exactly identical to the
- * ShimProtocolOffloadHeader.
- */
-typedef union
-{
- struct
- {
- unsigned int start_byte:7; /**< The first byte to be checksummed */
- unsigned int count:14; /**< Number of bytes to be checksummed. */
- unsigned int destination_byte:7; /**< The byte to write the checksum to. */
- unsigned int reserved:4; /**< Reserved. */
- } bits; /**< Decomposed method of access. */
- unsigned int word; /**< To send out the IDN. */
-} __netio_checksum_header_t;
-
-
-/** Sendv packet with 1 or 2 segments.
- * @param fastio_index Fast I/O index.
- * @param flags Ack/csum/notify flags in low 3 bits; number of segments minus
- * 1 in next 2 bits; expected checksum in high 16 bits.
- * @param confno Confirmation number to request, if notify flag set.
- * @param csum0 Checksum descriptor; if zero, no checksum.
- * @param va_F Virtual address of first segment.
- * @param va_L Virtual address of last segment, if 2 segments.
- * @param len_F_L Length of first segment in low 16 bits; length of last
- * segment, if 2 segments, in high 16 bits.
- */
-#define __netio_fastio_sendv_pkt_1_2(fastio_index, flags, confno, csum0, \
- va_F, va_L, len_F_L) \
- __netio_fastio6((fastio_index) + NETIO_FASTIO_SENDV_PKT, flags, confno, \
- csum0, va_F, va_L, len_F_L)
-
-/** Send packet on PCIe interface.
- * @param fastio_index Fast I/O index.
- * @param flags Ack/csum/notify flags in low 3 bits.
- * @param confno Confirmation number to request, if notify flag set.
- * @param csum0 Checksum descriptor; Hard wired 0, not needed for PCIe.
- * @param va_F Virtual address of the packet buffer.
- * @param va_L Virtual address of last segment, if 2 segments. Hard wired 0.
- * @param len_F_L Length of the packet buffer in low 16 bits.
- */
-#define __netio_fastio_send_pcie_pkt(fastio_index, flags, confno, csum0, \
- va_F, va_L, len_F_L) \
- __netio_fastio6((fastio_index) + PCIE_FASTIO_SENDV_PKT, flags, confno, \
- csum0, va_F, va_L, len_F_L)
-
-/** Sendv packet with 3 or 4 segments.
- * @param fastio_index Fast I/O index.
- * @param flags Ack/csum/notify flags in low 3 bits; number of segments minus
- * 1 in next 2 bits; expected checksum in high 16 bits.
- * @param confno Confirmation number to request, if notify flag set.
- * @param csum0 Checksum descriptor; if zero, no checksum.
- * @param va_F Virtual address of first segment.
- * @param va_L Virtual address of last segment (third segment if 3 segments,
- * fourth segment if 4 segments).
- * @param len_F_L Length of first segment in low 16 bits; length of last
- * segment in high 16 bits.
- * @param va_M0 Virtual address of "middle 0" segment; this segment is sent
- * second when there are three segments, and third if there are four.
- * @param va_M1 Virtual address of "middle 1" segment; this segment is sent
- * second when there are four segments.
- * @param len_M0_M1 Length of middle 0 segment in low 16 bits; length of middle
- * 1 segment, if 4 segments, in high 16 bits.
- */
-#define __netio_fastio_sendv_pkt_3_4(fastio_index, flags, confno, csum0, va_F, \
- va_L, len_F_L, va_M0, va_M1, len_M0_M1) \
- __netio_fastio9((fastio_index) + NETIO_FASTIO_SENDV_PKT, flags, confno, \
- csum0, va_F, va_L, len_F_L, va_M0, va_M1, len_M0_M1)
-
-/** Send vector of packets.
- * @param fastio_index Fast I/O index.
- * @param seqno Number of packets transmitted so far on this interface;
- * used to decide which packets should be acknowledged.
- * @param nentries Number of entries in vector.
- * @param va Virtual address of start of vector entry array.
- * @return 3-word netio_fastio_rv3_t structure. The structure's err member
- * is an error code, or zero if no error. The val0 member is the
- * updated value of seqno; it has been incremented by 1 for each
- * packet sent. That increment may be less than nentries if an
- * error occurred, or if some of the entries in the vector contain
- * handles equal to NETIO_PKT_HANDLE_NONE. The val1 member is the
- * updated value of nentries; it has been decremented by 1 for each
- * vector entry processed. Again, that decrement may be less than
- * nentries (leaving the returned value positive) if an error
- * occurred.
- */
-#define __netio_fastio_send_pkt_vec(fastio_index, seqno, nentries, va) \
- __netio_fastio3_rv3((fastio_index) + NETIO_FASTIO_SEND_PKT_VEC, seqno, \
- nentries, va)
-
-
-/** An egress DMA command for LEPP. */
-typedef struct
-{
- /** Is this a TSO transfer?
- *
- * NOTE: This field is always 0, to distinguish it from
- * lepp_tso_cmd_t. It must come first!
- */
- uint8_t tso : 1;
-
- /** Unused padding bits. */
- uint8_t _unused : 3;
-
- /** Should this packet be sent directly from caches instead of DRAM,
- * using hash-for-home to locate the packet data?
- */
- uint8_t hash_for_home : 1;
-
- /** Should we compute a checksum? */
- uint8_t compute_checksum : 1;
-
- /** Is this the final buffer for this packet?
- *
- * A single packet can be split over several input buffers (a "gather"
- * operation). This flag indicates that this is the last buffer
- * in a packet.
- */
- uint8_t end_of_packet : 1;
-
- /** Should LEPP advance 'comp_busy' when this DMA is fully finished? */
- uint8_t send_completion : 1;
-
- /** High bits of Client Physical Address of the start of the buffer
- * to be egressed.
- *
- * NOTE: Only 6 bits are actually needed here, as CPAs are
- * currently 38 bits. So two bits could be scavenged from this.
- */
- uint8_t cpa_hi;
-
- /** The number of bytes to be egressed. */
- uint16_t length;
-
- /** Low 32 bits of Client Physical Address of the start of the buffer
- * to be egressed.
- */
- uint32_t cpa_lo;
-
- /** Checksum information (only used if 'compute_checksum'). */
- __netio_checksum_header_t checksum_data;
-
-} lepp_cmd_t;
-
-
-/** A chunk of physical memory for a TSO egress. */
-typedef struct
-{
- /** The low bits of the CPA. */
- uint32_t cpa_lo;
- /** The high bits of the CPA. */
- uint16_t cpa_hi : 15;
- /** Should this packet be sent directly from caches instead of DRAM,
- * using hash-for-home to locate the packet data?
- */
- uint16_t hash_for_home : 1;
- /** The length in bytes. */
- uint16_t length;
-} lepp_frag_t;
-
-
-/** An LEPP command that handles TSO. */
-typedef struct
-{
- /** Is this a TSO transfer?
- *
- * NOTE: This field is always 1, to distinguish it from
- * lepp_cmd_t. It must come first!
- */
- uint8_t tso : 1;
-
- /** Unused padding bits. */
- uint8_t _unused : 7;
-
- /** Size of the header[] array in bytes. It must be in the range
- * [40, 127], which are the smallest header for a TCP packet over
- * Ethernet and the maximum possible prepend size supported by
- * hardware, respectively. Note that the array storage must be
- * padded out to a multiple of four bytes so that the following
- * LEPP command is aligned properly.
- */
- uint8_t header_size;
-
- /** Byte offset of the IP header in header[]. */
- uint8_t ip_offset;
-
- /** Byte offset of the TCP header in header[]. */
- uint8_t tcp_offset;
-
- /** The number of bytes to use for the payload of each packet,
- * except of course the last one, which may not have enough bytes.
- * This means that each Ethernet packet except the last will have a
- * size of header_size + payload_size.
- */
- uint16_t payload_size;
-
- /** The length of the 'frags' array that follows this struct. */
- uint16_t num_frags;
-
- /** The actual frags. */
- lepp_frag_t frags[0 /* Variable-sized; num_frags entries. */];
-
- /*
- * The packet header template logically follows frags[],
- * but you can't declare that in C.
- *
- * uint32_t header[header_size_in_words_rounded_up];
- */
-
-} lepp_tso_cmd_t;
-
-
-/** An LEPP completion ring entry. */
-typedef void* lepp_comp_t;
-
-
-/** Maximum number of frags for one TSO command. This is adapted from
- * linux's "MAX_SKB_FRAGS", and presumably over-estimates by one, for
- * our page size of exactly 65536. We add one for a "body" fragment.
- */
-#define LEPP_MAX_FRAGS (65536 / HV_DEFAULT_PAGE_SIZE_SMALL + 2 + 1)
-
-/** Total number of bytes needed for an lepp_tso_cmd_t. */
-#define LEPP_TSO_CMD_SIZE(num_frags, header_size) \
- (sizeof(lepp_tso_cmd_t) + \
- (num_frags) * sizeof(lepp_frag_t) + \
- (((header_size) + 3) & -4))
-
-/** The size of the lepp "cmd" queue. */
-#define LEPP_CMD_QUEUE_BYTES \
- (((CHIP_L2_CACHE_SIZE() - 2 * CHIP_L2_LINE_SIZE()) / \
- (sizeof(lepp_cmd_t) + sizeof(lepp_comp_t))) * sizeof(lepp_cmd_t))
-
-/** The largest possible command that can go in lepp_queue_t::cmds[]. */
-#define LEPP_MAX_CMD_SIZE LEPP_TSO_CMD_SIZE(LEPP_MAX_FRAGS, 128)
-
-/** The largest possible value of lepp_queue_t::cmd_{head, tail} (inclusive).
- */
-#define LEPP_CMD_LIMIT \
- (LEPP_CMD_QUEUE_BYTES - LEPP_MAX_CMD_SIZE)
-
-/** The maximum number of completions in an LEPP queue. */
-#define LEPP_COMP_QUEUE_SIZE \
- ((LEPP_CMD_LIMIT + sizeof(lepp_cmd_t) - 1) / sizeof(lepp_cmd_t))
-
-/** Increment an index modulo the queue size. */
-#define LEPP_QINC(var) \
- (var = __insn_mnz(var - (LEPP_COMP_QUEUE_SIZE - 1), var + 1))
-
-/** A queue used to convey egress commands from the client to LEPP. */
-typedef struct
-{
- /** Index of first completion not yet processed by user code.
- * If this is equal to comp_busy, there are no such completions.
- *
- * NOTE: This is only read/written by the user.
- */
- unsigned int comp_head;
-
- /** Index of first completion record not yet completed.
- * If this is equal to comp_tail, there are no such completions.
- * This index gets advanced (modulo LEPP_QUEUE_SIZE) whenever
- * a command with the 'completion' bit set is finished.
- *
- * NOTE: This is only written by LEPP, only read by the user.
- */
- volatile unsigned int comp_busy;
-
- /** Index of the first empty slot in the completion ring.
- * Entries from this up to but not including comp_head (in ring order)
- * can be filled in with completion data.
- *
- * NOTE: This is only read/written by the user.
- */
- unsigned int comp_tail;
-
- /** Byte index of first command enqueued for LEPP but not yet processed.
- *
- * This is always divisible by sizeof(void*) and always <= LEPP_CMD_LIMIT.
- *
- * NOTE: LEPP advances this counter as soon as it no longer needs
- * the cmds[] storage for this entry, but the transfer is not actually
- * complete (i.e. the buffer pointed to by the command is no longer
- * needed) until comp_busy advances.
- *
- * If this is equal to cmd_tail, the ring is empty.
- *
- * NOTE: This is only written by LEPP, only read by the user.
- */
- volatile unsigned int cmd_head;
-
- /** Byte index of first empty slot in the command ring. This field can
- * be incremented up to but not equal to cmd_head (because that would
- * mean the ring is empty).
- *
- * This is always divisible by sizeof(void*) and always <= LEPP_CMD_LIMIT.
- *
- * NOTE: This is read/written by the user, only read by LEPP.
- */
- volatile unsigned int cmd_tail;
-
- /** A ring of variable-sized egress DMA commands.
- *
- * NOTE: Only written by the user, only read by LEPP.
- */
- char cmds[LEPP_CMD_QUEUE_BYTES]
- __attribute__((aligned(CHIP_L2_LINE_SIZE())));
-
- /** A ring of user completion data.
- * NOTE: Only read/written by the user.
- */
- lepp_comp_t comps[LEPP_COMP_QUEUE_SIZE]
- __attribute__((aligned(CHIP_L2_LINE_SIZE())));
-} lepp_queue_t;
-
-
-/** An internal helper function for determining the number of entries
- * available in a ring buffer, given that there is one sentinel.
- */
-static inline unsigned int
-_lepp_num_free_slots(unsigned int head, unsigned int tail)
-{
- /*
- * One entry is reserved for use as a sentinel, to distinguish
- * "empty" from "full". So we compute
- * (head - tail - 1) % LEPP_QUEUE_SIZE, but without using a slow % operation.
- */
- return (head - tail - 1) + ((head <= tail) ? LEPP_COMP_QUEUE_SIZE : 0);
-}
-
-
-/** Returns how many new comp entries can be enqueued. */
-static inline unsigned int
-lepp_num_free_comp_slots(const lepp_queue_t* q)
-{
- return _lepp_num_free_slots(q->comp_head, q->comp_tail);
-}
-
-static inline int
-lepp_qsub(int v1, int v2)
-{
- int delta = v1 - v2;
- return delta + ((delta >> 31) & LEPP_COMP_QUEUE_SIZE);
-}
-
-
-/** FIXME: Check this from linux, via a new "pwrite()" call. */
-#define LIPP_VERSION 1
-
-
-/** We use exactly two bytes of alignment padding. */
-#define LIPP_PACKET_PADDING 2
-
-/** The minimum size of a "small" buffer (including the padding). */
-#define LIPP_SMALL_PACKET_SIZE 128
-
-/*
- * NOTE: The following two values should total to less than around
- * 13582, to keep the total size used for "lipp_state_t" below 64K.
- */
-
-/** The maximum number of "small" buffers.
- * This is enough for 53 network cpus with 128 credits. Note that
- * if these are exhausted, we will fall back to using large buffers.
- */
-#define LIPP_SMALL_BUFFERS 6785
-
-/** The maximum number of "large" buffers.
- * This is enough for 53 network cpus with 128 credits.
- */
-#define LIPP_LARGE_BUFFERS 6785
-
-#endif /* __DRV_XGBE_INTF_H__ */
diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/include/hv/hypervisor.h
deleted file mode 100644
index f10b332b3b65..000000000000
--- a/arch/tile/include/hv/hypervisor.h
+++ /dev/null
@@ -1,2656 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file hypervisor.h
- * The hypervisor's public API.
- */
-
-#ifndef _HV_HV_H
-#define _HV_HV_H
-
-#include <arch/chip.h>
-
-/* Linux builds want unsigned long constants, but assembler wants numbers */
-#ifdef __ASSEMBLER__
-/** One, for assembler */
-#define __HV_SIZE_ONE 1
-#elif !defined(__tile__) && CHIP_VA_WIDTH() > 32
-/** One, for 64-bit on host */
-#define __HV_SIZE_ONE 1ULL
-#else
-/** One, for Linux */
-#define __HV_SIZE_ONE 1UL
-#endif
-
-/** The log2 of the span of a level-1 page table, in bytes.
- */
-#define HV_LOG2_L1_SPAN 32
-
-/** The span of a level-1 page table, in bytes.
- */
-#define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN)
-
-/** The log2 of the initial size of small pages, in bytes.
- * See HV_DEFAULT_PAGE_SIZE_SMALL.
- */
-#define HV_LOG2_DEFAULT_PAGE_SIZE_SMALL 16
-
-/** The initial size of small pages, in bytes. This value should be verified
- * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
- * It may also be modified when installing a new context.
- */
-#define HV_DEFAULT_PAGE_SIZE_SMALL \
- (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_SMALL)
-
-/** The log2 of the initial size of large pages, in bytes.
- * See HV_DEFAULT_PAGE_SIZE_LARGE.
- */
-#define HV_LOG2_DEFAULT_PAGE_SIZE_LARGE 24
-
-/** The initial size of large pages, in bytes. This value should be verified
- * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
- * It may also be modified when installing a new context.
- */
-#define HV_DEFAULT_PAGE_SIZE_LARGE \
- (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_LARGE)
-
-#if CHIP_VA_WIDTH() > 32
-
-/** The log2 of the initial size of jumbo pages, in bytes.
- * See HV_DEFAULT_PAGE_SIZE_JUMBO.
- */
-#define HV_LOG2_DEFAULT_PAGE_SIZE_JUMBO 32
-
-/** The initial size of jumbo pages, in bytes. This value should
- * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_JUMBO).
- * It may also be modified when installing a new context.
- */
-#define HV_DEFAULT_PAGE_SIZE_JUMBO \
- (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_JUMBO)
-
-#endif
-
-/** The log2 of the granularity at which page tables must be aligned;
- * in other words, the CPA for a page table must have this many zero
- * bits at the bottom of the address.
- */
-#define HV_LOG2_PAGE_TABLE_ALIGN 11
-
-/** The granularity at which page tables must be aligned.
- */
-#define HV_PAGE_TABLE_ALIGN (__HV_SIZE_ONE << HV_LOG2_PAGE_TABLE_ALIGN)
-
-/** Normal start of hypervisor glue in client physical memory. */
-#define HV_GLUE_START_CPA 0x10000
-
-/** This much space is reserved at HV_GLUE_START_CPA
- * for the hypervisor glue. The client program must start at
- * some address higher than this, and in particular the address of
- * its text section should be equal to zero modulo HV_PAGE_SIZE_LARGE
- * so that relative offsets to the HV glue are correct.
- */
-#define HV_GLUE_RESERVED_SIZE 0x10000
-
-/** Each entry in the hv dispatch array takes this many bytes. */
-#define HV_DISPATCH_ENTRY_SIZE 32
-
-/** Version of the hypervisor interface defined by this file */
-#define _HV_VERSION 13
-
-/** Last version of the hypervisor interface with old hv_init() ABI.
- *
- * The change from version 12 to version 13 corresponds to launching
- * the client by default at PL2 instead of PL1 (corresponding to the
- * hv itself running at PL3 instead of PL2). To make this explicit,
- * the hv_init() API was also extended so the client can report its
- * desired PL, resulting in a more helpful failure diagnostic. If you
- * call hv_init() with _HV_VERSION_OLD_HV_INIT and omit the client_pl
- * argument, the hypervisor will assume client_pl = 1.
- *
- * Note that this is a deprecated solution and we do not expect to
- * support clients of the Tilera hypervisor running at PL1 indefinitely.
- */
-#define _HV_VERSION_OLD_HV_INIT 12
-
-/* Index into hypervisor interface dispatch code blocks.
- *
- * Hypervisor calls are invoked from user space by calling code
- * at an address HV_BASE_ADDRESS + (index) * HV_DISPATCH_ENTRY_SIZE,
- * where index is one of these enum values.
- *
- * Normally a supervisor is expected to produce a set of symbols
- * starting at HV_BASE_ADDRESS that obey this convention, but a user
- * program could call directly through function pointers if desired.
- *
- * These numbers are part of the binary API and will not be changed
- * without updating HV_VERSION, which should be a rare event.
- */
-
-/** reserved. */
-#define _HV_DISPATCH_RESERVED 0
-
-/** hv_init */
-#define HV_DISPATCH_INIT 1
-
-/** hv_install_context */
-#define HV_DISPATCH_INSTALL_CONTEXT 2
-
-/** hv_sysconf */
-#define HV_DISPATCH_SYSCONF 3
-
-/** hv_get_rtc */
-#define HV_DISPATCH_GET_RTC 4
-
-/** hv_set_rtc */
-#define HV_DISPATCH_SET_RTC 5
-
-/** hv_flush_asid */
-#define HV_DISPATCH_FLUSH_ASID 6
-
-/** hv_flush_page */
-#define HV_DISPATCH_FLUSH_PAGE 7
-
-/** hv_flush_pages */
-#define HV_DISPATCH_FLUSH_PAGES 8
-
-/** hv_restart */
-#define HV_DISPATCH_RESTART 9
-
-/** hv_halt */
-#define HV_DISPATCH_HALT 10
-
-/** hv_power_off */
-#define HV_DISPATCH_POWER_OFF 11
-
-/** hv_inquire_physical */
-#define HV_DISPATCH_INQUIRE_PHYSICAL 12
-
-/** hv_inquire_memory_controller */
-#define HV_DISPATCH_INQUIRE_MEMORY_CONTROLLER 13
-
-/** hv_inquire_virtual */
-#define HV_DISPATCH_INQUIRE_VIRTUAL 14
-
-/** hv_inquire_asid */
-#define HV_DISPATCH_INQUIRE_ASID 15
-
-/** hv_nanosleep */
-#define HV_DISPATCH_NANOSLEEP 16
-
-/** hv_console_read_if_ready */
-#define HV_DISPATCH_CONSOLE_READ_IF_READY 17
-
-/** hv_console_write */
-#define HV_DISPATCH_CONSOLE_WRITE 18
-
-/** hv_downcall_dispatch */
-#define HV_DISPATCH_DOWNCALL_DISPATCH 19
-
-/** hv_inquire_topology */
-#define HV_DISPATCH_INQUIRE_TOPOLOGY 20
-
-/** hv_fs_findfile */
-#define HV_DISPATCH_FS_FINDFILE 21
-
-/** hv_fs_fstat */
-#define HV_DISPATCH_FS_FSTAT 22
-
-/** hv_fs_pread */
-#define HV_DISPATCH_FS_PREAD 23
-
-/** hv_physaddr_read64 */
-#define HV_DISPATCH_PHYSADDR_READ64 24
-
-/** hv_physaddr_write64 */
-#define HV_DISPATCH_PHYSADDR_WRITE64 25
-
-/** hv_get_command_line */
-#define HV_DISPATCH_GET_COMMAND_LINE 26
-
-/** hv_set_caching */
-#define HV_DISPATCH_SET_CACHING 27
-
-/** hv_bzero_page */
-#define HV_DISPATCH_BZERO_PAGE 28
-
-/** hv_register_message_state */
-#define HV_DISPATCH_REGISTER_MESSAGE_STATE 29
-
-/** hv_send_message */
-#define HV_DISPATCH_SEND_MESSAGE 30
-
-/** hv_receive_message */
-#define HV_DISPATCH_RECEIVE_MESSAGE 31
-
-/** hv_inquire_context */
-#define HV_DISPATCH_INQUIRE_CONTEXT 32
-
-/** hv_start_all_tiles */
-#define HV_DISPATCH_START_ALL_TILES 33
-
-/** hv_dev_open */
-#define HV_DISPATCH_DEV_OPEN 34
-
-/** hv_dev_close */
-#define HV_DISPATCH_DEV_CLOSE 35
-
-/** hv_dev_pread */
-#define HV_DISPATCH_DEV_PREAD 36
-
-/** hv_dev_pwrite */
-#define HV_DISPATCH_DEV_PWRITE 37
-
-/** hv_dev_poll */
-#define HV_DISPATCH_DEV_POLL 38
-
-/** hv_dev_poll_cancel */
-#define HV_DISPATCH_DEV_POLL_CANCEL 39
-
-/** hv_dev_preada */
-#define HV_DISPATCH_DEV_PREADA 40
-
-/** hv_dev_pwritea */
-#define HV_DISPATCH_DEV_PWRITEA 41
-
-/** hv_flush_remote */
-#define HV_DISPATCH_FLUSH_REMOTE 42
-
-/** hv_console_putc */
-#define HV_DISPATCH_CONSOLE_PUTC 43
-
-/** hv_inquire_tiles */
-#define HV_DISPATCH_INQUIRE_TILES 44
-
-/** hv_confstr */
-#define HV_DISPATCH_CONFSTR 45
-
-/** hv_reexec */
-#define HV_DISPATCH_REEXEC 46
-
-/** hv_set_command_line */
-#define HV_DISPATCH_SET_COMMAND_LINE 47
-
-#if !CHIP_HAS_IPI()
-
-/** hv_clear_intr */
-#define HV_DISPATCH_CLEAR_INTR 48
-
-/** hv_enable_intr */
-#define HV_DISPATCH_ENABLE_INTR 49
-
-/** hv_disable_intr */
-#define HV_DISPATCH_DISABLE_INTR 50
-
-/** hv_raise_intr */
-#define HV_DISPATCH_RAISE_INTR 51
-
-/** hv_trigger_ipi */
-#define HV_DISPATCH_TRIGGER_IPI 52
-
-#endif /* !CHIP_HAS_IPI() */
-
-/** hv_store_mapping */
-#define HV_DISPATCH_STORE_MAPPING 53
-
-/** hv_inquire_realpa */
-#define HV_DISPATCH_INQUIRE_REALPA 54
-
-/** hv_flush_all */
-#define HV_DISPATCH_FLUSH_ALL 55
-
-#if CHIP_HAS_IPI()
-/** hv_get_ipi_pte */
-#define HV_DISPATCH_GET_IPI_PTE 56
-#endif
-
-/** hv_set_pte_super_shift */
-#define HV_DISPATCH_SET_PTE_SUPER_SHIFT 57
-
-/** hv_console_set_ipi */
-#define HV_DISPATCH_CONSOLE_SET_IPI 63
-
-/** hv_send_nmi */
-#define HV_DISPATCH_SEND_NMI 65
-
-/** One more than the largest dispatch value */
-#define _HV_DISPATCH_END 66
-
-
-#ifndef __ASSEMBLER__
-
-#ifdef __KERNEL__
-#include <asm/types.h>
-typedef u32 __hv32; /**< 32-bit value */
-typedef u64 __hv64; /**< 64-bit value */
-#else
-#include <stdint.h>
-typedef uint32_t __hv32; /**< 32-bit value */
-typedef uint64_t __hv64; /**< 64-bit value */
-#endif
-
-
-/** Hypervisor physical address. */
-typedef __hv64 HV_PhysAddr;
-
-#if CHIP_VA_WIDTH() > 32
-/** Hypervisor virtual address. */
-typedef __hv64 HV_VirtAddr;
-#else
-/** Hypervisor virtual address. */
-typedef __hv32 HV_VirtAddr;
-#endif /* CHIP_VA_WIDTH() > 32 */
-
-/** Hypervisor ASID. */
-typedef unsigned int HV_ASID;
-
-/** Hypervisor tile location for a memory access
- * ("location overridden target").
- */
-typedef unsigned int HV_LOTAR;
-
-/** Hypervisor size of a page. */
-typedef unsigned long HV_PageSize;
-
-/** A page table entry.
- */
-typedef struct
-{
- __hv64 val; /**< Value of PTE */
-} HV_PTE;
-
-/** Hypervisor error code. */
-typedef int HV_Errno;
-
-#endif /* !__ASSEMBLER__ */
-
-#define HV_OK 0 /**< No error */
-#define HV_EINVAL -801 /**< Invalid argument */
-#define HV_ENODEV -802 /**< No such device */
-#define HV_ENOENT -803 /**< No such file or directory */
-#define HV_EBADF -804 /**< Bad file number */
-#define HV_EFAULT -805 /**< Bad address */
-#define HV_ERECIP -806 /**< Bad recipients */
-#define HV_E2BIG -807 /**< Message too big */
-#define HV_ENOTSUP -808 /**< Service not supported */
-#define HV_EBUSY -809 /**< Device busy */
-#define HV_ENOSYS -810 /**< Invalid syscall */
-#define HV_EPERM -811 /**< No permission */
-#define HV_ENOTREADY -812 /**< Device not ready */
-#define HV_EIO -813 /**< I/O error */
-#define HV_ENOMEM -814 /**< Out of memory */
-#define HV_EAGAIN -815 /**< Try again */
-
-#define HV_ERR_MAX -801 /**< Largest HV error code */
-#define HV_ERR_MIN -815 /**< Smallest HV error code */
-
-#ifndef __ASSEMBLER__
-
-/** Pass HV_VERSION to hv_init to request this version of the interface. */
-typedef enum {
- HV_VERSION = _HV_VERSION,
- HV_VERSION_OLD_HV_INIT = _HV_VERSION_OLD_HV_INIT,
-
-} HV_VersionNumber;
-
-/** Initializes the hypervisor.
- *
- * @param interface_version_number The version of the hypervisor interface
- * that this program expects, typically HV_VERSION.
- * @param chip_num Architecture number of the chip the client was built for.
- * @param chip_rev_num Revision number of the chip the client was built for.
- * @param client_pl Privilege level the client is built for
- * (not required if interface_version_number == HV_VERSION_OLD_HV_INIT).
- */
-void hv_init(HV_VersionNumber interface_version_number,
- int chip_num, int chip_rev_num, int client_pl);
-
-
-/** Queries we can make for hv_sysconf().
- *
- * These numbers are part of the binary API and guaranteed not to change.
- */
-typedef enum {
- /** An invalid value; do not use. */
- _HV_SYSCONF_RESERVED = 0,
-
- /** The length of the glue section containing the hv_ procs, in bytes. */
- HV_SYSCONF_GLUE_SIZE = 1,
-
- /** The size of small pages, in bytes. */
- HV_SYSCONF_PAGE_SIZE_SMALL = 2,
-
- /** The size of large pages, in bytes. */
- HV_SYSCONF_PAGE_SIZE_LARGE = 3,
-
- /** Processor clock speed, in hertz. */
- HV_SYSCONF_CPU_SPEED = 4,
-
- /** Processor temperature, in degrees Kelvin. The value
- * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
- * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
- * that the temperature has hit an upper limit and is no longer being
- * accurately tracked.
- */
- HV_SYSCONF_CPU_TEMP = 5,
-
- /** Board temperature, in degrees Kelvin. The value
- * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
- * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
- * that the temperature has hit an upper limit and is no longer being
- * accurately tracked.
- */
- HV_SYSCONF_BOARD_TEMP = 6,
-
- /** Legal page size bitmask for hv_install_context().
- * For example, if 16KB and 64KB small pages are supported,
- * it would return "HV_CTX_PG_SM_16K | HV_CTX_PG_SM_64K".
- */
- HV_SYSCONF_VALID_PAGE_SIZES = 7,
-
- /** The size of jumbo pages, in bytes.
- * If no jumbo pages are available, zero will be returned.
- */
- HV_SYSCONF_PAGE_SIZE_JUMBO = 8,
-
-} HV_SysconfQuery;
-
-/** Offset to subtract from returned Kelvin temperature to get degrees
- Celsius. */
-#define HV_SYSCONF_TEMP_KTOC 273
-
-/** Pseudo-temperature value indicating that the temperature has
- * pegged at its upper limit and is no longer accurate; note that this is
- * the value after subtracting HV_SYSCONF_TEMP_KTOC. */
-#define HV_SYSCONF_OVERTEMP 999
-
-/** Query a configuration value from the hypervisor.
- * @param query Which value is requested (HV_SYSCONF_xxx).
- * @return The requested value, or -1 the requested value is illegal or
- * unavailable.
- */
-long hv_sysconf(HV_SysconfQuery query);
-
-
-/** Queries we can make for hv_confstr().
- *
- * These numbers are part of the binary API and guaranteed not to change.
- */
-typedef enum {
- /** An invalid value; do not use. */
- _HV_CONFSTR_RESERVED = 0,
-
- /** Board part number. */
- HV_CONFSTR_BOARD_PART_NUM = 1,
-
- /** Board serial number. */
- HV_CONFSTR_BOARD_SERIAL_NUM = 2,
-
- /** Chip serial number. */
- HV_CONFSTR_CHIP_SERIAL_NUM = 3,
-
- /** Board revision level. */
- HV_CONFSTR_BOARD_REV = 4,
-
- /** Hypervisor software version. */
- HV_CONFSTR_HV_SW_VER = 5,
-
- /** The name for this chip model. */
- HV_CONFSTR_CHIP_MODEL = 6,
-
- /** Human-readable board description. */
- HV_CONFSTR_BOARD_DESC = 7,
-
- /** Human-readable description of the hypervisor configuration. */
- HV_CONFSTR_HV_CONFIG = 8,
-
- /** Human-readable version string for the boot image (for instance,
- * who built it and when, what configuration file was used). */
- HV_CONFSTR_HV_CONFIG_VER = 9,
-
- /** Mezzanine part number. */
- HV_CONFSTR_MEZZ_PART_NUM = 10,
-
- /** Mezzanine serial number. */
- HV_CONFSTR_MEZZ_SERIAL_NUM = 11,
-
- /** Mezzanine revision level. */
- HV_CONFSTR_MEZZ_REV = 12,
-
- /** Human-readable mezzanine description. */
- HV_CONFSTR_MEZZ_DESC = 13,
-
- /** Control path for the onboard network switch. */
- HV_CONFSTR_SWITCH_CONTROL = 14,
-
- /** Chip revision level. */
- HV_CONFSTR_CHIP_REV = 15,
-
- /** CPU module part number. */
- HV_CONFSTR_CPUMOD_PART_NUM = 16,
-
- /** CPU module serial number. */
- HV_CONFSTR_CPUMOD_SERIAL_NUM = 17,
-
- /** CPU module revision level. */
- HV_CONFSTR_CPUMOD_REV = 18,
-
- /** Human-readable CPU module description. */
- HV_CONFSTR_CPUMOD_DESC = 19,
-
- /** Per-tile hypervisor statistics. When this identifier is specified,
- * the hv_confstr call takes two extra arguments. The first is the
- * HV_XY_TO_LOTAR of the target tile's coordinates. The second is
- * a flag word. The only current flag is the lowest bit, which means
- * "zero out the stats instead of retrieving them"; in this case the
- * buffer and buffer length are ignored. */
- HV_CONFSTR_HV_STATS = 20
-
-} HV_ConfstrQuery;
-
-/** Query a configuration string from the hypervisor.
- *
- * @param query Identifier for the specific string to be retrieved
- * (HV_CONFSTR_xxx). Some strings may require or permit extra
- * arguments to be appended which select specific objects to be
- * described; see the string descriptions above.
- * @param buf Buffer in which to place the string.
- * @param len Length of the buffer.
- * @return If query is valid, then the length of the corresponding string,
- * including the trailing null; if this is greater than len, the string
- * was truncated. If query is invalid, HV_EINVAL. If the specified
- * buffer is not writable by the client, HV_EFAULT.
- */
-int hv_confstr(HV_ConfstrQuery query, HV_VirtAddr buf, int len, ...);
-
-/** Tile coordinate */
-typedef struct
-{
- /** X coordinate, relative to supervisor's top-left coordinate */
- int x;
-
- /** Y coordinate, relative to supervisor's top-left coordinate */
- int y;
-} HV_Coord;
-
-
-#if CHIP_HAS_IPI()
-
-/** Get the PTE for sending an IPI to a particular tile.
- *
- * @param tile Tile which will receive the IPI.
- * @param pl Indicates which IPI registers: 0 = IPI_0, 1 = IPI_1.
- * @param pte Filled with resulting PTE.
- * @result Zero if no error, non-zero for invalid parameters.
- */
-int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte);
-
-/** Configure the console interrupt.
- *
- * When the console client interrupt is enabled, the hypervisor will
- * deliver the specified IPI to the client in the following situations:
- *
- * - The console has at least one character available for input.
- *
- * - The console can accept new characters for output, and the last call
- * to hv_console_write() did not write all of the characters requested
- * by the client.
- *
- * Note that in some system configurations, console interrupt will not
- * be available; clients should be prepared for this routine to fail and
- * to fall back to periodic console polling in that case.
- *
- * @param ipi Index of the IPI register which will receive the interrupt.
- * @param event IPI event number for console interrupt. If less than 0,
- * disable the console IPI interrupt.
- * @param coord Tile to be targeted for console interrupt.
- * @return 0 on success, otherwise, HV_EINVAL if illegal parameter,
- * HV_ENOTSUP if console interrupt are not available.
- */
-int hv_console_set_ipi(int ipi, int event, HV_Coord coord);
-
-#else /* !CHIP_HAS_IPI() */
-
-/** A set of interrupts. */
-typedef __hv32 HV_IntrMask;
-
-/** The low interrupt numbers are reserved for use by the client in
- * delivering IPIs. Any interrupt numbers higher than this value are
- * reserved for use by HV device drivers. */
-#define HV_MAX_IPI_INTERRUPT 7
-
-/** Enable a set of device interrupts.
- *
- * @param enab_mask Bitmap of interrupts to enable.
- */
-void hv_enable_intr(HV_IntrMask enab_mask);
-
-/** Disable a set of device interrupts.
- *
- * @param disab_mask Bitmap of interrupts to disable.
- */
-void hv_disable_intr(HV_IntrMask disab_mask);
-
-/** Clear a set of device interrupts.
- *
- * @param clear_mask Bitmap of interrupts to clear.
- */
-void hv_clear_intr(HV_IntrMask clear_mask);
-
-/** Raise a set of device interrupts.
- *
- * @param raise_mask Bitmap of interrupts to raise.
- */
-void hv_raise_intr(HV_IntrMask raise_mask);
-
-/** Trigger a one-shot interrupt on some tile
- *
- * @param tile Which tile to interrupt.
- * @param interrupt Interrupt number to trigger; must be between 0 and
- * HV_MAX_IPI_INTERRUPT.
- * @return HV_OK on success, or a hypervisor error code.
- */
-HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
-
-#endif /* !CHIP_HAS_IPI() */
-
-/** Store memory mapping in debug memory so that external debugger can read it.
- * A maximum of 16 entries can be stored.
- *
- * @param va VA of memory that is mapped.
- * @param len Length of mapped memory.
- * @param pa PA of memory that is mapped.
- * @return 0 on success, -1 if the maximum number of mappings is exceeded.
- */
-int hv_store_mapping(HV_VirtAddr va, unsigned int len, HV_PhysAddr pa);
-
-/** Given a client PA and a length, return its real (HV) PA.
- *
- * @param cpa Client physical address.
- * @param len Length of mapped memory.
- * @return physical address, or -1 if cpa or len is not valid.
- */
-HV_PhysAddr hv_inquire_realpa(HV_PhysAddr cpa, unsigned int len);
-
-/** RTC return flag for no RTC chip present.
- */
-#define HV_RTC_NO_CHIP 0x1
-
-/** RTC return flag for low-voltage condition, indicating that battery had
- * died and time read is unreliable.
- */
-#define HV_RTC_LOW_VOLTAGE 0x2
-
-/** Date/Time of day */
-typedef struct {
-#if CHIP_WORD_SIZE() > 32
- __hv64 tm_sec; /**< Seconds, 0-59 */
- __hv64 tm_min; /**< Minutes, 0-59 */
- __hv64 tm_hour; /**< Hours, 0-23 */
- __hv64 tm_mday; /**< Day of month, 0-30 */
- __hv64 tm_mon; /**< Month, 0-11 */
- __hv64 tm_year; /**< Years since 1900, 0-199 */
- __hv64 flags; /**< Return flags, 0 if no error */
-#else
- __hv32 tm_sec; /**< Seconds, 0-59 */
- __hv32 tm_min; /**< Minutes, 0-59 */
- __hv32 tm_hour; /**< Hours, 0-23 */
- __hv32 tm_mday; /**< Day of month, 0-30 */
- __hv32 tm_mon; /**< Month, 0-11 */
- __hv32 tm_year; /**< Years since 1900, 0-199 */
- __hv32 flags; /**< Return flags, 0 if no error */
-#endif
-} HV_RTCTime;
-
-/** Read the current time-of-day clock.
- * @return HV_RTCTime of current time (GMT).
- */
-HV_RTCTime hv_get_rtc(void);
-
-
-/** Set the current time-of-day clock.
- * @param time time to reset time-of-day to (GMT).
- */
-void hv_set_rtc(HV_RTCTime time);
-
-/** Installs a context, comprising a page table and other attributes.
- *
- * Once this service completes, page_table will be used to translate
- * subsequent virtual address references to physical memory.
- *
- * Installing a context does not cause an implicit TLB flush. Before
- * reusing an ASID value for a different address space, the client is
- * expected to flush old references from the TLB with hv_flush_asid().
- * (Alternately, hv_flush_all() may be used to flush many ASIDs at once.)
- * After invalidating a page table entry, changing its attributes, or
- * changing its target CPA, the client is expected to flush old references
- * from the TLB with hv_flush_page() or hv_flush_pages(). Making a
- * previously invalid page valid does not require a flush.
- *
- * Specifying an invalid ASID, or an invalid CPA (client physical address)
- * (either as page_table_pointer, or within the referenced table),
- * or another page table data item documented as above as illegal may
- * lead to client termination; since the validation of the table is
- * done as needed, this may happen before the service returns, or at
- * some later time, or never, depending upon the client's pattern of
- * memory references. Page table entries which supply translations for
- * invalid virtual addresses may result in client termination, or may
- * be silently ignored. "Invalid" in this context means a value which
- * was not provided to the client via the appropriate hv_inquire_* routine.
- *
- * To support changing the instruction VAs at the same time as
- * installing the new page table, this call explicitly supports
- * setting the "lr" register to a different address and then jumping
- * directly to the hv_install_context() routine. In this case, the
- * new page table does not need to contain any mapping for the
- * hv_install_context address itself.
- *
- * At most one HV_CTX_PG_SM_* flag may be specified in "flags";
- * if multiple flags are specified, HV_EINVAL is returned.
- * Specifying none of the flags results in using the default page size.
- * All cores participating in a given client must request the same
- * page size, or the results are undefined.
- *
- * @param page_table Root of the page table.
- * @param access PTE providing info on how to read the page table. This
- * value must be consistent between multiple tiles sharing a page table,
- * and must also be consistent with any virtual mappings the client
- * may be using to access the page table.
- * @param asid HV_ASID the page table is to be used for.
- * @param flags Context flags, denoting attributes or privileges of the
- * current context (HV_CTX_xxx).
- * @return Zero on success, or a hypervisor error code on failure.
- */
-int hv_install_context(HV_PhysAddr page_table, HV_PTE access, HV_ASID asid,
- __hv32 flags);
-
-#endif /* !__ASSEMBLER__ */
-
-#define HV_CTX_DIRECTIO 0x1 /**< Direct I/O requests are accepted from
- PL0. */
-
-#define HV_CTX_PG_SM_4K 0x10 /**< Use 4K small pages, if available. */
-#define HV_CTX_PG_SM_16K 0x20 /**< Use 16K small pages, if available. */
-#define HV_CTX_PG_SM_64K 0x40 /**< Use 64K small pages, if available. */
-#define HV_CTX_PG_SM_MASK 0xf0 /**< Mask of all possible small pages. */
-
-#ifndef __ASSEMBLER__
-
-
-/** Set the number of pages ganged together by HV_PTE_SUPER at a
- * particular level of the page table.
- *
- * The current TILE-Gx hardware only supports powers of four
- * (i.e. log2_count must be a multiple of two), and the requested
- * "super" page size must be less than the span of the next level in
- * the page table. The largest size that can be requested is 64GB.
- *
- * The shift value is initially "0" for all page table levels,
- * indicating that the HV_PTE_SUPER bit is effectively ignored.
- *
- * If you change the count from one non-zero value to another, the
- * hypervisor will flush the entire TLB and TSB to avoid confusion.
- *
- * @param level Page table level (0, 1, or 2)
- * @param log2_count Base-2 log of the number of pages to gang together,
- * i.e. how much to shift left the base page size for the super page size.
- * @return Zero on success, or a hypervisor error code on failure.
- */
-int hv_set_pte_super_shift(int level, int log2_count);
-
-
-/** Value returned from hv_inquire_context(). */
-typedef struct
-{
- /** Physical address of page table */
- HV_PhysAddr page_table;
-
- /** PTE which defines access method for top of page table */
- HV_PTE access;
-
- /** ASID associated with this page table */
- HV_ASID asid;
-
- /** Context flags */
- __hv32 flags;
-} HV_Context;
-
-/** Retrieve information about the currently installed context.
- * @return The data passed to the last successful hv_install_context call.
- */
-HV_Context hv_inquire_context(void);
-
-
-/** Flushes all translations associated with the named address space
- * identifier from the TLB and any other hypervisor data structures.
- * Translations installed with the "global" bit are not flushed.
- *
- * Specifying an invalid ASID may lead to client termination. "Invalid"
- * in this context means a value which was not provided to the client
- * via <tt>hv_inquire_asid()</tt>.
- *
- * @param asid HV_ASID whose entries are to be flushed.
- * @return Zero on success, or a hypervisor error code on failure.
-*/
-int hv_flush_asid(HV_ASID asid);
-
-
-/** Flushes all translations associated with the named virtual address
- * and page size from the TLB and other hypervisor data structures. Only
- * pages visible to the current ASID are affected; note that this includes
- * global pages in addition to pages specific to the current ASID.
- *
- * The supplied VA need not be aligned; it may be anywhere in the
- * subject page.
- *
- * Specifying an invalid virtual address may lead to client termination,
- * or may silently succeed. "Invalid" in this context means a value
- * which was not provided to the client via hv_inquire_virtual.
- *
- * @param address Address of the page to flush.
- * @param page_size Size of pages to assume.
- * @return Zero on success, or a hypervisor error code on failure.
- */
-int hv_flush_page(HV_VirtAddr address, HV_PageSize page_size);
-
-
-/** Flushes all translations associated with the named virtual address range
- * and page size from the TLB and other hypervisor data structures. Only
- * pages visible to the current ASID are affected; note that this includes
- * global pages in addition to pages specific to the current ASID.
- *
- * The supplied VA need not be aligned; it may be anywhere in the
- * subject page.
- *
- * Specifying an invalid virtual address may lead to client termination,
- * or may silently succeed. "Invalid" in this context means a value
- * which was not provided to the client via hv_inquire_virtual.
- *
- * @param start Address to flush.
- * @param page_size Size of pages to assume.
- * @param size The number of bytes to flush. Any page in the range
- * [start, start + size) will be flushed from the TLB.
- * @return Zero on success, or a hypervisor error code on failure.
- */
-int hv_flush_pages(HV_VirtAddr start, HV_PageSize page_size,
- unsigned long size);
-
-
-/** Flushes all non-global translations (if preserve_global is true),
- * or absolutely all translations (if preserve_global is false).
- *
- * @param preserve_global Non-zero if we want to preserve "global" mappings.
- * @return Zero on success, or a hypervisor error code on failure.
-*/
-int hv_flush_all(int preserve_global);
-
-
-/** Restart machine with optional restart command and optional args.
- * @param cmd Const pointer to command to restart with, or NULL
- * @param args Const pointer to argument string to restart with, or NULL
- */
-void hv_restart(HV_VirtAddr cmd, HV_VirtAddr args);
-
-
-/** Halt machine. */
-void hv_halt(void);
-
-
-/** Power off machine. */
-void hv_power_off(void);
-
-
-/** Re-enter virtual-is-physical memory translation mode and restart
- * execution at a given address.
- * @param entry Client physical address at which to begin execution.
- * @return A hypervisor error code on failure; if the operation is
- * successful the call does not return.
- */
-int hv_reexec(HV_PhysAddr entry);
-
-
-/** Chip topology */
-typedef struct
-{
- /** Relative coordinates of the querying tile */
- HV_Coord coord;
-
- /** Width of the querying supervisor's tile rectangle. */
- int width;
-
- /** Height of the querying supervisor's tile rectangle. */
- int height;
-
-} HV_Topology;
-
-/** Returns information about the tile coordinate system.
- *
- * Each supervisor is given a rectangle of tiles it potentially controls.
- * These tiles are labeled using a relative coordinate system with (0,0) as
- * the upper left tile regardless of their physical location on the chip.
- *
- * This call returns both the size of that rectangle and the position
- * within that rectangle of the querying tile.
- *
- * Not all tiles within that rectangle may be available to the supervisor;
- * to get the precise set of available tiles, you must also call
- * hv_inquire_tiles(HV_INQ_TILES_AVAIL, ...).
- **/
-HV_Topology hv_inquire_topology(void);
-
-/** Sets of tiles we can retrieve with hv_inquire_tiles().
- *
- * These numbers are part of the binary API and guaranteed not to change.
- */
-typedef enum {
- /** An invalid value; do not use. */
- _HV_INQ_TILES_RESERVED = 0,
-
- /** All available tiles within the supervisor's tile rectangle. */
- HV_INQ_TILES_AVAIL = 1,
-
- /** The set of tiles used for hash-for-home caching. */
- HV_INQ_TILES_HFH_CACHE = 2,
-
- /** The set of tiles that can be legally used as a LOTAR for a PTE. */
- HV_INQ_TILES_LOTAR = 3,
-
- /** The set of "shared" driver tiles that the hypervisor may
- * periodically interrupt. */
- HV_INQ_TILES_SHARED = 4
-} HV_InqTileSet;
-
-/** Returns specific information about various sets of tiles within the
- * supervisor's tile rectangle.
- *
- * @param set Which set of tiles to retrieve.
- * @param cpumask Pointer to a returned bitmask (in row-major order,
- * supervisor-relative) of tiles. The low bit of the first word
- * corresponds to the tile at the upper left-hand corner of the
- * supervisor's rectangle. In order for the supervisor to know the
- * buffer length to supply, it should first call hv_inquire_topology.
- * @param length Number of bytes available for the returned bitmask.
- **/
-HV_Errno hv_inquire_tiles(HV_InqTileSet set, HV_VirtAddr cpumask, int length);
-
-
-/** An identifier for a memory controller. Multiple memory controllers
- * may be connected to one chip, and this uniquely identifies each one.
- */
-typedef int HV_MemoryController;
-
-/** A range of physical memory. */
-typedef struct
-{
- HV_PhysAddr start; /**< Starting address. */
- __hv64 size; /**< Size in bytes. */
- HV_MemoryController controller; /**< Which memory controller owns this. */
-} HV_PhysAddrRange;
-
-/** Returns information about a range of physical memory.
- *
- * hv_inquire_physical() returns one of the ranges of client
- * physical addresses which are available to this client.
- *
- * The first range is retrieved by specifying an idx of 0, and
- * successive ranges are returned with subsequent idx values. Ranges
- * are ordered by increasing start address (i.e., as idx increases,
- * so does start), do not overlap, and do not touch (i.e., the
- * available memory is described with the fewest possible ranges).
- *
- * If an out-of-range idx value is specified, the returned size will be zero.
- * A client can count the number of ranges by increasing idx until the
- * returned size is zero. There will always be at least one valid range.
- *
- * Some clients might not be prepared to deal with more than one
- * physical address range; they still ought to call this routine and
- * issue a warning message if they're given more than one range, on the
- * theory that whoever configured the hypervisor to provide that memory
- * should know that it's being wasted.
- */
-HV_PhysAddrRange hv_inquire_physical(int idx);
-
-/** Possible DIMM types. */
-typedef enum
-{
- NO_DIMM = 0, /**< No DIMM */
- DDR2 = 1, /**< DDR2 */
- DDR3 = 2 /**< DDR3 */
-} HV_DIMM_Type;
-
-#ifdef __tilegx__
-
-/** Log2 of minimum DIMM bytes supported by the memory controller. */
-#define HV_MSH_MIN_DIMM_SIZE_SHIFT 29
-
-/** Max number of DIMMs contained by one memory controller. */
-#define HV_MSH_MAX_DIMMS 8
-
-#else
-
-/** Log2 of minimum DIMM bytes supported by the memory controller. */
-#define HV_MSH_MIN_DIMM_SIZE_SHIFT 26
-
-/** Max number of DIMMs contained by one memory controller. */
-#define HV_MSH_MAX_DIMMS 2
-
-#endif
-
-/** Number of bits to right-shift to get the DIMM type. */
-#define HV_DIMM_TYPE_SHIFT 0
-
-/** Bits to mask to get the DIMM type. */
-#define HV_DIMM_TYPE_MASK 0xf
-
-/** Number of bits to right-shift to get the DIMM size. */
-#define HV_DIMM_SIZE_SHIFT 4
-
-/** Bits to mask to get the DIMM size. */
-#define HV_DIMM_SIZE_MASK 0xf
-
-/** Memory controller information. */
-typedef struct
-{
- HV_Coord coord; /**< Relative tile coordinates of the port used by a
- specified tile to communicate with this controller. */
- __hv64 speed; /**< Speed of this controller in bytes per second. */
-} HV_MemoryControllerInfo;
-
-/** Returns information about a particular memory controller.
- *
- * hv_inquire_memory_controller(coord,idx) returns information about a
- * particular controller. Two pieces of information are returned:
- * - The relative coordinates of the port on the controller that the specified
- * tile would use to contact it. The relative coordinates may lie
- * outside the supervisor's rectangle, i.e. the controller may not
- * be attached to a node managed by the querying node's supervisor.
- * In particular note that x or y may be negative.
- * - The speed of the memory controller. (This is a not-to-exceed value
- * based on the raw hardware data rate, and may not be achievable in
- * practice; it is provided to give clients information on the relative
- * performance of the available controllers.)
- *
- * Clients should avoid calling this interface with invalid values.
- * A client who does may be terminated.
- * @param coord Tile for which to calculate the relative port position.
- * @param controller Index of the controller; identical to value returned
- * from other routines like hv_inquire_physical.
- * @return Information about the controller.
- */
-HV_MemoryControllerInfo hv_inquire_memory_controller(HV_Coord coord,
- int controller);
-
-
-/** A range of virtual memory. */
-typedef struct
-{
- HV_VirtAddr start; /**< Starting address. */
- __hv64 size; /**< Size in bytes. */
-} HV_VirtAddrRange;
-
-/** Returns information about a range of virtual memory.
- *
- * hv_inquire_virtual() returns one of the ranges of client
- * virtual addresses which are available to this client.
- *
- * The first range is retrieved by specifying an idx of 0, and
- * successive ranges are returned with subsequent idx values. Ranges
- * are ordered by increasing start address (i.e., as idx increases,
- * so does start), do not overlap, and do not touch (i.e., the
- * available memory is described with the fewest possible ranges).
- *
- * If an out-of-range idx value is specified, the returned size will be zero.
- * A client can count the number of ranges by increasing idx until the
- * returned size is zero. There will always be at least one valid range.
- *
- * Some clients may well have various virtual addresses hardwired
- * into themselves; for instance, their instruction stream may
- * have been compiled expecting to live at a particular address.
- * Such clients should use this interface to verify they've been
- * given the virtual address space they expect, and issue a (potentially
- * fatal) warning message otherwise.
- *
- * Note that the returned size is a __hv64, not a __hv32, so it is
- * possible to express a single range spanning the entire 32-bit
- * address space.
- */
-HV_VirtAddrRange hv_inquire_virtual(int idx);
-
-
-/** A range of ASID values. */
-typedef struct
-{
- HV_ASID start; /**< First ASID in the range. */
- unsigned int size; /**< Number of ASIDs. Zero for an invalid range. */
-} HV_ASIDRange;
-
-/** Returns information about a range of ASIDs.
- *
- * hv_inquire_asid() returns one of the ranges of address
- * space identifiers which are available to this client.
- *
- * The first range is retrieved by specifying an idx of 0, and
- * successive ranges are returned with subsequent idx values. Ranges
- * are ordered by increasing start value (i.e., as idx increases,
- * so does start), do not overlap, and do not touch (i.e., the
- * available ASIDs are described with the fewest possible ranges).
- *
- * If an out-of-range idx value is specified, the returned size will be zero.
- * A client can count the number of ranges by increasing idx until the
- * returned size is zero. There will always be at least one valid range.
- */
-HV_ASIDRange hv_inquire_asid(int idx);
-
-
-/** Waits for at least the specified number of nanoseconds then returns.
- *
- * NOTE: this deprecated function currently assumes a 750 MHz clock,
- * and is thus not generally suitable for use. New code should call
- * hv_sysconf(HV_SYSCONF_CPU_SPEED), compute a cycle count to wait for,
- * and delay by looping while checking the cycle counter SPR.
- *
- * @param nanosecs The number of nanoseconds to sleep.
- */
-void hv_nanosleep(int nanosecs);
-
-
-/** Reads a character from the console without blocking.
- *
- * @return A value from 0-255 indicates the value successfully read.
- * A negative value means no value was ready.
- */
-int hv_console_read_if_ready(void);
-
-
-/** Writes a character to the console, blocking if the console is busy.
- *
- * This call cannot fail. If the console is broken for some reason,
- * output will simply vanish.
- * @param byte Character to write.
- */
-void hv_console_putc(int byte);
-
-
-/** Writes a string to the console, blocking if the console is busy.
- * @param bytes Pointer to characters to write.
- * @param len Number of characters to write.
- * @return Number of characters written, or HV_EFAULT if the buffer is invalid.
- */
-int hv_console_write(HV_VirtAddr bytes, int len);
-
-
-/** Dispatch the next interrupt from the client downcall mechanism.
- *
- * The hypervisor uses downcalls to notify the client of asynchronous
- * events. Some of these events are hypervisor-created (like incoming
- * messages). Some are regular interrupts which initially occur in
- * the hypervisor, and are normally handled directly by the client;
- * when these occur in a client's interrupt critical section, they must
- * be delivered through the downcall mechanism.
- *
- * A downcall is initially delivered to the client as an INTCTRL_CL
- * interrupt, where CL is the client's PL. Upon entry to the INTCTRL_CL
- * vector, the client must immediately invoke the hv_downcall_dispatch
- * service. This service will not return; instead it will cause one of
- * the client's actual downcall-handling interrupt vectors to be entered.
- * The EX_CONTEXT registers in the client will be set so that when the
- * client irets, it will return to the code which was interrupted by the
- * INTCTRL_CL interrupt.
- *
- * Under some circumstances, the firing of INTCTRL_CL can race with
- * the lowering of a device interrupt. In such a case, the
- * hv_downcall_dispatch service may issue an iret instruction instead
- * of entering one of the client's actual downcall-handling interrupt
- * vectors. This will return execution to the location that was
- * interrupted by INTCTRL_CL.
- *
- * Any saving of registers should be done by the actual handling
- * vectors; no registers should be changed by the INTCTRL_CL handler.
- * In particular, the client should not use a jal instruction to invoke
- * the hv_downcall_dispatch service, as that would overwrite the client's
- * lr register. Note that the hv_downcall_dispatch service may overwrite
- * one or more of the client's system save registers.
- *
- * The client must not modify the INTCTRL_CL_STATUS SPR. The hypervisor
- * will set this register to cause a downcall to happen, and will clear
- * it when no further downcalls are pending.
- *
- * When a downcall vector is entered, the INTCTRL_CL interrupt will be
- * masked. When the client is done processing a downcall, and is ready
- * to accept another, it must unmask this interrupt; if more downcalls
- * are pending, this will cause the INTCTRL_CL vector to be reentered.
- * Currently the following interrupt vectors can be entered through a
- * downcall:
- *
- * INT_MESSAGE_RCV_DWNCL (hypervisor message available)
- * INT_DEV_INTR_DWNCL (device interrupt)
- * INT_DMATLB_MISS_DWNCL (DMA TLB miss)
- * INT_SNITLB_MISS_DWNCL (SNI TLB miss)
- * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation)
- */
-void hv_downcall_dispatch(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/** We use actual interrupt vectors which never occur (they're only there
- * to allow setting MPLs for related SPRs) for our downcall vectors.
- */
-/** Message receive downcall interrupt vector */
-#define INT_MESSAGE_RCV_DWNCL INT_BOOT_ACCESS
-/** DMA TLB miss downcall interrupt vector */
-#define INT_DMATLB_MISS_DWNCL INT_DMA_ASID
-/** Static nework processor instruction TLB miss interrupt vector */
-#define INT_SNITLB_MISS_DWNCL INT_SNI_ASID
-/** DMA TLB access violation downcall interrupt vector */
-#define INT_DMATLB_ACCESS_DWNCL INT_DMA_CPL
-/** Device interrupt downcall interrupt vector */
-#define INT_DEV_INTR_DWNCL INT_WORLD_ACCESS
-/** NMI downcall interrupt vector */
-#define INT_NMI_DWNCL 64
-
-#define HV_NMI_FLAG_FORCE 0x1 /**< Force an NMI downcall regardless of
- the ICS bit of the client. */
-
-#ifndef __ASSEMBLER__
-
-/** Requests the inode for a specific full pathname.
- *
- * Performs a lookup in the hypervisor filesystem for a given filename.
- * Multiple calls with the same filename will always return the same inode.
- * If there is no such filename, HV_ENOENT is returned.
- * A bad filename pointer may result in HV_EFAULT instead.
- *
- * @param filename Constant pointer to name of requested file
- * @return Inode of requested file
- */
-int hv_fs_findfile(HV_VirtAddr filename);
-
-
-/** Data returned from an fstat request.
- * Note that this structure should be no more than 40 bytes in size so
- * that it can always be returned completely in registers.
- */
-typedef struct
-{
- int size; /**< Size of file (or HV_Errno on error) */
- unsigned int flags; /**< Flags (see HV_FS_FSTAT_FLAGS) */
-} HV_FS_StatInfo;
-
-/** Bitmask flags for fstat request */
-typedef enum
-{
- HV_FS_ISDIR = 0x0001 /**< Is the entry a directory? */
-} HV_FS_FSTAT_FLAGS;
-
-/** Get stat information on a given file inode.
- *
- * Return information on the file with the given inode.
- *
- * IF the HV_FS_ISDIR bit is set, the "file" is a directory. Reading
- * it will return NUL-separated filenames (no directory part) relative
- * to the path to the inode of the directory "file". These can be
- * appended to the path to the directory "file" after a forward slash
- * to create additional filenames. Note that it is not required
- * that all valid paths be decomposable into valid parent directories;
- * a filesystem may validly have just a few files, none of which have
- * HV_FS_ISDIR set. However, if clients may wish to enumerate the
- * files in the filesystem, it is recommended to include all the
- * appropriate parent directory "files" to give a consistent view.
- *
- * An invalid file inode will cause an HV_EBADF error to be returned.
- *
- * @param inode The inode number of the query
- * @return An HV_FS_StatInfo structure
- */
-HV_FS_StatInfo hv_fs_fstat(int inode);
-
-
-/** Read data from a specific hypervisor file.
- * On error, may return HV_EBADF for a bad inode or HV_EFAULT for a bad buf.
- * Reads near the end of the file will return fewer bytes than requested.
- * Reads at or beyond the end of a file will return zero.
- *
- * @param inode the hypervisor file to read
- * @param buf the buffer to read data into
- * @param length the number of bytes of data to read
- * @param offset the offset into the file to read the data from
- * @return number of bytes successfully read, or an HV_Errno code
- */
-int hv_fs_pread(int inode, HV_VirtAddr buf, int length, int offset);
-
-
-/** Read a 64-bit word from the specified physical address.
- * The address must be 8-byte aligned.
- * Specifying an invalid physical address will lead to client termination.
- * @param addr The physical address to read
- * @param access The PTE describing how to read the memory
- * @return The 64-bit value read from the given address
- */
-unsigned long long hv_physaddr_read64(HV_PhysAddr addr, HV_PTE access);
-
-
-/** Write a 64-bit word to the specified physical address.
- * The address must be 8-byte aligned.
- * Specifying an invalid physical address will lead to client termination.
- * @param addr The physical address to write
- * @param access The PTE that says how to write the memory
- * @param val The 64-bit value to write to the given address
- */
-void hv_physaddr_write64(HV_PhysAddr addr, HV_PTE access,
- unsigned long long val);
-
-
-/** Get the value of the command-line for the supervisor, if any.
- * This will not include the filename of the booted supervisor, but may
- * include configured-in boot arguments or the hv_restart() arguments.
- * If the buffer is not long enough the hypervisor will NUL the first
- * character of the buffer but not write any other data.
- * @param buf The virtual address to write the command-line string to.
- * @param length The length of buf, in characters.
- * @return The actual length of the command line, including the trailing NUL
- * (may be larger than "length").
- */
-int hv_get_command_line(HV_VirtAddr buf, int length);
-
-
-/** Set a new value for the command-line for the supervisor, which will
- * be returned from subsequent invocations of hv_get_command_line() on
- * this tile.
- * @param buf The virtual address to read the command-line string from.
- * @param length The length of buf, in characters; must be no more than
- * HV_COMMAND_LINE_LEN.
- * @return Zero if successful, or a hypervisor error code.
- */
-HV_Errno hv_set_command_line(HV_VirtAddr buf, int length);
-
-/** Maximum size of a command line passed to hv_set_command_line(); note
- * that a line returned from hv_get_command_line() could be larger than
- * this.*/
-#define HV_COMMAND_LINE_LEN 256
-
-/** Tell the hypervisor how to cache non-priority pages
- * (its own as well as pages explicitly represented in page tables).
- * Normally these will be represented as red/black pages, but
- * when the supervisor starts to allocate "priority" pages in the PTE
- * the hypervisor will need to start marking those pages as (e.g.) "red"
- * and non-priority pages as either "black" (if they cache-alias
- * with the existing priority pages) or "red/black" (if they don't).
- * The bitmask provides information on which parts of the cache
- * have been used for pinned pages so far on this tile; if (1 << N)
- * appears in the bitmask, that indicates that a 4KB region of the
- * cache starting at (N * 4KB) is in use by a "priority" page.
- * The portion of cache used by a particular page can be computed
- * by taking the page's PA, modulo CHIP_L2_CACHE_SIZE(), and setting
- * all the "4KB" bits corresponding to the actual page size.
- * @param bitmask A bitmap of priority page set values
- */
-void hv_set_caching(unsigned long bitmask);
-
-
-/** Zero out a specified number of pages.
- * The va and size must both be multiples of 4096.
- * Caches are bypassed and memory is directly set to zero.
- * This API is implemented only in the magic hypervisor and is intended
- * to provide a performance boost to the minimal supervisor by
- * giving it a fast way to zero memory pages when allocating them.
- * @param va Virtual address where the page has been mapped
- * @param size Number of bytes (must be a page size multiple)
- */
-void hv_bzero_page(HV_VirtAddr va, unsigned int size);
-
-
-/** State object for the hypervisor messaging subsystem. */
-typedef struct
-{
-#if CHIP_VA_WIDTH() > 32
- __hv64 opaque[2]; /**< No user-serviceable parts inside */
-#else
- __hv32 opaque[2]; /**< No user-serviceable parts inside */
-#endif
-}
-HV_MsgState;
-
-/** Register to receive incoming messages.
- *
- * This routine configures the current tile so that it can receive
- * incoming messages. It must be called before the client can receive
- * messages with the hv_receive_message routine, and must be called on
- * each tile which will receive messages.
- *
- * msgstate is the virtual address of a state object of type HV_MsgState.
- * Once the state is registered, the client must not read or write the
- * state object; doing so will cause undefined results.
- *
- * If this routine is called with msgstate set to 0, the client's message
- * state will be freed and it will no longer be able to receive messages.
- * Note that this may cause the loss of any as-yet-undelivered messages
- * for the client.
- *
- * If another client attempts to send a message to a client which has
- * not yet called hv_register_message_state, or which has freed its
- * message state, the message will not be delivered, as if the client
- * had insufficient buffering.
- *
- * This routine returns HV_OK if the registration was successful, and
- * HV_EINVAL if the supplied state object is unsuitable. Note that some
- * errors may not be detected during this routine, but might be detected
- * during a subsequent message delivery.
- * @param msgstate State object.
- **/
-HV_Errno hv_register_message_state(HV_MsgState* msgstate);
-
-/** Possible message recipient states. */
-typedef enum
-{
- HV_TO_BE_SENT, /**< Not sent (not attempted, or recipient not ready) */
- HV_SENT, /**< Successfully sent */
- HV_BAD_RECIP /**< Bad recipient coordinates (permanent error) */
-} HV_Recip_State;
-
-/** Message recipient. */
-typedef struct
-{
- /** X coordinate, relative to supervisor's top-left coordinate */
- unsigned int x:11;
-
- /** Y coordinate, relative to supervisor's top-left coordinate */
- unsigned int y:11;
-
- /** Status of this recipient */
- HV_Recip_State state:10;
-} HV_Recipient;
-
-/** Send a message to a set of recipients.
- *
- * This routine sends a message to a set of recipients.
- *
- * recips is an array of HV_Recipient structures. Each specifies a tile,
- * and a message state; initially, it is expected that the state will
- * be set to HV_TO_BE_SENT. nrecip specifies the number of recipients
- * in the recips array.
- *
- * For each recipient whose state is HV_TO_BE_SENT, the hypervisor attempts
- * to send that tile the specified message. In order to successfully
- * receive the message, the receiver must be a valid tile to which the
- * sender has access, must not be the sending tile itself, and must have
- * sufficient free buffer space. (The hypervisor guarantees that each
- * tile which has called hv_register_message_state() will be able to
- * buffer one message from every other tile which can legally send to it;
- * more space may be provided but is not guaranteed.) If an invalid tile
- * is specified, the recipient's state is set to HV_BAD_RECIP; this is a
- * permanent delivery error. If the message is successfully delivered
- * to the recipient's buffer, the recipient's state is set to HV_SENT.
- * Otherwise, the recipient's state is unchanged. Message delivery is
- * synchronous; all attempts to send messages are completed before this
- * routine returns.
- *
- * If no permanent delivery errors were encountered, the routine returns
- * the number of messages successfully sent: that is, the number of
- * recipients whose states changed from HV_TO_BE_SENT to HV_SENT during
- * this operation. If any permanent delivery errors were encountered,
- * the routine returns HV_ERECIP. In the event of permanent delivery
- * errors, it may be the case that delivery was not attempted to all
- * recipients; if any messages were successfully delivered, however,
- * recipients' state values will be updated appropriately.
- *
- * It is explicitly legal to specify a recipient structure whose state
- * is not HV_TO_BE_SENT; such a recipient is ignored. One suggested way
- * of using hv_send_message to send a message to multiple tiles is to set
- * up a list of recipients, and then call the routine repeatedly with the
- * same list, each time accumulating the number of messages successfully
- * sent, until all messages are sent, a permanent error is encountered,
- * or the desired number of attempts have been made. When used in this
- * way, the routine will deliver each message no more than once to each
- * recipient.
- *
- * Note that a message being successfully delivered to the recipient's
- * buffer space does not guarantee that it is received by the recipient,
- * either immediately or at any time in the future; the recipient might
- * never call hv_receive_message, or could register a different state
- * buffer, losing the message.
- *
- * Specifying the same recipient more than once in the recipient list
- * is an error, which will not result in an error return but which may
- * or may not result in more than one message being delivered to the
- * recipient tile.
- *
- * buf and buflen specify the message to be sent. buf is a virtual address
- * which must be currently mapped in the client's page table; if not, the
- * routine returns HV_EFAULT. buflen must be greater than zero and less
- * than or equal to HV_MAX_MESSAGE_SIZE, and nrecip must be less than the
- * number of tiles to which the sender has access; if not, the routine
- * returns HV_EINVAL.
- * @param recips List of recipients.
- * @param nrecip Number of recipients.
- * @param buf Address of message data.
- * @param buflen Length of message data.
- **/
-int hv_send_message(HV_Recipient *recips, int nrecip,
- HV_VirtAddr buf, int buflen);
-
-/** Maximum hypervisor message size, in bytes */
-#define HV_MAX_MESSAGE_SIZE 28
-
-
-/** Return value from hv_receive_message() */
-typedef struct
-{
- int msglen; /**< Message length in bytes, or an error code */
- __hv32 source; /**< Code identifying message sender (HV_MSG_xxx) */
-} HV_RcvMsgInfo;
-
-#define HV_MSG_TILE 0x0 /**< Message source is another tile */
-#define HV_MSG_INTR 0x1 /**< Message source is a driver interrupt */
-
-/** Receive a message.
- *
- * This routine retrieves a message from the client's incoming message
- * buffer.
- *
- * Multiple messages sent from a particular sending tile to a particular
- * receiving tile are received in the order that they were sent; however,
- * no ordering is guaranteed between messages sent by different tiles.
- *
- * Whenever the a client's message buffer is empty, the first message
- * subsequently received will cause the client's MESSAGE_RCV_DWNCL
- * interrupt vector to be invoked through the interrupt downcall mechanism
- * (see the description of the hv_downcall_dispatch() routine for details
- * on downcalls).
- *
- * Another message-available downcall will not occur until a call to
- * this routine is made when the message buffer is empty, and a message
- * subsequently arrives. Note that such a downcall could occur while
- * this routine is executing. If the calling code does not wish this
- * to happen, it is recommended that this routine be called with the
- * INTCTRL_1 interrupt masked, or inside an interrupt critical section.
- *
- * msgstate is the value previously passed to hv_register_message_state().
- * buf is the virtual address of the buffer into which the message will
- * be written; buflen is the length of the buffer.
- *
- * This routine returns an HV_RcvMsgInfo structure. The msglen member
- * of that structure is the length of the message received, zero if no
- * message is available, or HV_E2BIG if the message is too large for the
- * specified buffer. If the message is too large, it is not consumed,
- * and may be retrieved by a subsequent call to this routine specifying
- * a sufficiently large buffer. A buffer which is HV_MAX_MESSAGE_SIZE
- * bytes long is guaranteed to be able to receive any possible message.
- *
- * The source member of the HV_RcvMsgInfo structure describes the sender
- * of the message. For messages sent by another client tile via an
- * hv_send_message() call, this value is HV_MSG_TILE; for messages sent
- * as a result of a device interrupt, this value is HV_MSG_INTR.
- */
-
-HV_RcvMsgInfo hv_receive_message(HV_MsgState msgstate, HV_VirtAddr buf,
- int buflen);
-
-
-/** Start remaining tiles owned by this supervisor. Initially, only one tile
- * executes the client program; after it calls this service, the other tiles
- * are started. This allows the initial tile to do one-time configuration
- * of shared data structures without having to lock them against simultaneous
- * access.
- */
-void hv_start_all_tiles(void);
-
-
-/** Open a hypervisor device.
- *
- * This service initializes an I/O device and its hypervisor driver software,
- * and makes it available for use. The open operation is per-device per-chip;
- * once it has been performed, the device handle returned may be used in other
- * device services calls made by any tile.
- *
- * @param name Name of the device. A base device name is just a text string
- * (say, "pcie"). If there is more than one instance of a device, the
- * base name is followed by a slash and a device number (say, "pcie/0").
- * Some devices may support further structure beneath those components;
- * most notably, devices which require control operations do so by
- * supporting reads and/or writes to a control device whose name
- * includes a trailing "/ctl" (say, "pcie/0/ctl").
- * @param flags Flags (HV_DEV_xxx).
- * @return A positive integer device handle, or a negative error code.
- */
-int hv_dev_open(HV_VirtAddr name, __hv32 flags);
-
-
-/** Close a hypervisor device.
- *
- * This service uninitializes an I/O device and its hypervisor driver
- * software, and makes it unavailable for use. The close operation is
- * per-device per-chip; once it has been performed, the device is no longer
- * available. Normally there is no need to ever call the close service.
- *
- * @param devhdl Device handle of the device to be closed.
- * @return Zero if the close is successful, otherwise, a negative error code.
- */
-int hv_dev_close(int devhdl);
-
-
-/** Read data from a hypervisor device synchronously.
- *
- * This service transfers data from a hypervisor device to a memory buffer.
- * When the service returns, the data has been written from the memory buffer,
- * and the buffer will not be further modified by the driver.
- *
- * No ordering is guaranteed between requests issued from different tiles.
- *
- * Devices may choose to support both the synchronous and asynchronous read
- * operations, only one of them, or neither of them.
- *
- * @param devhdl Device handle of the device to be read from.
- * @param flags Flags (HV_DEV_xxx).
- * @param va Virtual address of the target data buffer. This buffer must
- * be mapped in the currently installed page table; if not, HV_EFAULT
- * may be returned.
- * @param len Number of bytes to be transferred.
- * @param offset Driver-dependent offset. For a random-access device, this is
- * often a byte offset from the beginning of the device; in other cases,
- * like on a control device, it may have a different meaning.
- * @return A non-negative value if the read was at least partially successful;
- * otherwise, a negative error code. The precise interpretation of
- * the return value is driver-dependent, but many drivers will return
- * the number of bytes successfully transferred.
- */
-int hv_dev_pread(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
- __hv64 offset);
-
-#define HV_DEV_NB_EMPTY 0x1 /**< Don't block when no bytes of data can
- be transferred. */
-#define HV_DEV_NB_PARTIAL 0x2 /**< Don't block when some bytes, but not all
- of the requested bytes, can be
- transferred. */
-#define HV_DEV_NOCACHE 0x4 /**< The caller warrants that none of the
- cache lines which might contain data
- from the requested buffer are valid.
- Useful with asynchronous operations
- only. */
-
-#define HV_DEV_ALLFLAGS (HV_DEV_NB_EMPTY | HV_DEV_NB_PARTIAL | \
- HV_DEV_NOCACHE) /**< All HV_DEV_xxx flags */
-
-/** Write data to a hypervisor device synchronously.
- *
- * This service transfers data from a memory buffer to a hypervisor device.
- * When the service returns, the data has been read from the memory buffer,
- * and the buffer may be overwritten by the client; the data may not
- * necessarily have been conveyed to the actual hardware I/O interface.
- *
- * No ordering is guaranteed between requests issued from different tiles.
- *
- * Devices may choose to support both the synchronous and asynchronous write
- * operations, only one of them, or neither of them.
- *
- * @param devhdl Device handle of the device to be written to.
- * @param flags Flags (HV_DEV_xxx).
- * @param va Virtual address of the source data buffer. This buffer must
- * be mapped in the currently installed page table; if not, HV_EFAULT
- * may be returned.
- * @param len Number of bytes to be transferred.
- * @param offset Driver-dependent offset. For a random-access device, this is
- * often a byte offset from the beginning of the device; in other cases,
- * like on a control device, it may have a different meaning.
- * @return A non-negative value if the write was at least partially successful;
- * otherwise, a negative error code. The precise interpretation of
- * the return value is driver-dependent, but many drivers will return
- * the number of bytes successfully transferred.
- */
-int hv_dev_pwrite(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
- __hv64 offset);
-
-
-/** Interrupt arguments, used in the asynchronous I/O interfaces. */
-#if CHIP_VA_WIDTH() > 32
-typedef __hv64 HV_IntArg;
-#else
-typedef __hv32 HV_IntArg;
-#endif
-
-/** Interrupt messages are delivered via the mechanism as normal messages,
- * but have a message source of HV_DEV_INTR. The message is formatted
- * as an HV_IntrMsg structure.
- */
-
-typedef struct
-{
- HV_IntArg intarg; /**< Interrupt argument, passed to the poll/preada/pwritea
- services */
- HV_IntArg intdata; /**< Interrupt-specific interrupt data */
-} HV_IntrMsg;
-
-/** Request an interrupt message when a device condition is satisfied.
- *
- * This service requests that an interrupt message be delivered to the
- * requesting tile when a device becomes readable or writable, or when any
- * data queued to the device via previous write operations from this tile
- * has been actually sent out on the hardware I/O interface. Devices may
- * choose to support any, all, or none of the available conditions.
- *
- * If multiple conditions are specified, only one message will be
- * delivered. If the event mask delivered to that interrupt handler
- * indicates that some of the conditions have not yet occurred, the
- * client must issue another poll() call if it wishes to wait for those
- * conditions.
- *
- * Only one poll may be outstanding per device handle per tile. If more than
- * one tile is polling on the same device and condition, they will all be
- * notified when it happens. Because of this, clients may not assume that
- * the condition signaled is necessarily still true when they request a
- * subsequent service; for instance, the readable data which caused the
- * poll call to interrupt may have been read by another tile in the interim.
- *
- * The notification interrupt message could come directly, or via the
- * downcall (intctrl1) method, depending on what the tile is doing
- * when the condition is satisfied. Note that it is possible for the
- * requested interrupt to be delivered after this service is called but
- * before it returns.
- *
- * @param devhdl Device handle of the device to be polled.
- * @param events Flags denoting the events which will cause the interrupt to
- * be delivered (HV_DEVPOLL_xxx).
- * @param intarg Value which will be delivered as the intarg member of the
- * eventual interrupt message; the intdata member will be set to a
- * mask of HV_DEVPOLL_xxx values indicating which conditions have been
- * satisifed.
- * @return Zero if the interrupt was successfully scheduled; otherwise, a
- * negative error code.
- */
-int hv_dev_poll(int devhdl, __hv32 events, HV_IntArg intarg);
-
-#define HV_DEVPOLL_READ 0x1 /**< Test device for readability */
-#define HV_DEVPOLL_WRITE 0x2 /**< Test device for writability */
-#define HV_DEVPOLL_FLUSH 0x4 /**< Test device for output drained */
-
-
-/** Cancel a request for an interrupt when a device event occurs.
- *
- * This service requests that no interrupt be delivered when the events
- * noted in the last-issued poll() call happen. Once this service returns,
- * the interrupt has been canceled; however, it is possible for the interrupt
- * to be delivered after this service is called but before it returns.
- *
- * @param devhdl Device handle of the device on which to cancel polling.
- * @return Zero if the poll was successfully canceled; otherwise, a negative
- * error code.
- */
-int hv_dev_poll_cancel(int devhdl);
-
-
-/** NMI information */
-typedef struct
-{
- /** Result: negative error, or HV_NMI_RESULT_xxx. */
- int result;
-
- /** PC from interrupted remote core (if result != HV_NMI_RESULT_FAIL_HV). */
- HV_VirtAddr pc;
-
-} HV_NMI_Info;
-
-/** NMI issued successfully. */
-#define HV_NMI_RESULT_OK 0
-
-/** NMI not issued: remote tile running at client PL with ICS set. */
-#define HV_NMI_RESULT_FAIL_ICS 1
-
-/** NMI not issued: remote tile waiting in hypervisor. */
-#define HV_NMI_RESULT_FAIL_HV 2
-
-/** Force an NMI downcall regardless of the ICS bit of the client. */
-#define HV_NMI_FLAG_FORCE 0x1
-
-/** Send an NMI interrupt request to a particular tile.
- *
- * This will cause the NMI to be issued on the remote tile regardless
- * of the state of the client interrupt mask. However, if the remote
- * tile is in the hypervisor, it will not execute the NMI, and
- * HV_NMI_RESULT_FAIL_HV will be returned. Similarly, if the remote
- * tile is in a client interrupt critical section at the time of the
- * NMI, it will not execute the NMI, and HV_NMI_RESULT_FAIL_ICS will
- * be returned. In this second case, however, if HV_NMI_FLAG_FORCE
- * is set in flags, then the remote tile will enter its NMI interrupt
- * vector regardless. Forcing the NMI vector during an interrupt
- * critical section will mean that the client can not safely continue
- * execution after handling the interrupt.
- *
- * @param tile Tile to which the NMI request is sent.
- * @param info NMI information which is defined by and interpreted by the
- * supervisor, is passed to the specified tile, and is
- * stored in the SPR register SYSTEM_SAVE_{CLIENT_PL}_2 on the
- * specified tile when entering the NMI handler routine.
- * Typically, this parameter stores the NMI type, or an aligned
- * VA plus some special bits, etc.
- * @param flags Flags (HV_NMI_FLAG_xxx).
- * @return Information about the requested NMI.
- */
-HV_NMI_Info hv_send_nmi(HV_Coord tile, unsigned long info, __hv64 flags);
-
-
-/** Scatter-gather list for preada/pwritea calls. */
-typedef struct
-#if CHIP_VA_WIDTH() <= 32
-__attribute__ ((packed, aligned(4)))
-#endif
-{
- HV_PhysAddr pa; /**< Client physical address of the buffer segment. */
- HV_PTE pte; /**< Page table entry describing the caching and location
- override characteristics of the buffer segment. Some
- drivers ignore this element and will require that
- the NOCACHE flag be set on their requests. */
- __hv32 len; /**< Length of the buffer segment. */
-} HV_SGL;
-
-#define HV_SGL_MAXLEN 16 /**< Maximum number of entries in a scatter-gather
- list */
-
-/** Read data from a hypervisor device asynchronously.
- *
- * This service transfers data from a hypervisor device to a memory buffer.
- * When the service returns, the read has been scheduled. When the read
- * completes, an interrupt message will be delivered, and the buffer will
- * not be further modified by the driver.
- *
- * The number of possible outstanding asynchronous requests is defined by
- * each driver, but it is recommended that it be at least two requests
- * per tile per device.
- *
- * No ordering is guaranteed between synchronous and asynchronous requests,
- * even those issued on the same tile.
- *
- * The completion interrupt message could come directly, or via the downcall
- * (intctrl1) method, depending on what the tile is doing when the read
- * completes. Interrupts do not coalesce; one is delivered for each
- * asynchronous I/O request. Note that it is possible for the requested
- * interrupt to be delivered after this service is called but before it
- * returns.
- *
- * Devices may choose to support both the synchronous and asynchronous read
- * operations, only one of them, or neither of them.
- *
- * @param devhdl Device handle of the device to be read from.
- * @param flags Flags (HV_DEV_xxx).
- * @param sgl_len Number of elements in the scatter-gather list.
- * @param sgl Scatter-gather list describing the memory to which data will be
- * written.
- * @param offset Driver-dependent offset. For a random-access device, this is
- * often a byte offset from the beginning of the device; in other cases,
- * like on a control device, it may have a different meaning.
- * @param intarg Value which will be delivered as the intarg member of the
- * eventual interrupt message; the intdata member will be set to the
- * normal return value from the read request.
- * @return Zero if the read was successfully scheduled; otherwise, a negative
- * error code. Note that some drivers may choose to pre-validate
- * their arguments, and may thus detect certain device error
- * conditions at this time rather than when the completion notification
- * occurs, but this is not required.
- */
-int hv_dev_preada(int devhdl, __hv32 flags, __hv32 sgl_len,
- HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
-
-
-/** Write data to a hypervisor device asynchronously.
- *
- * This service transfers data from a memory buffer to a hypervisor
- * device. When the service returns, the write has been scheduled.
- * When the write completes, an interrupt message will be delivered,
- * and the buffer may be overwritten by the client; the data may not
- * necessarily have been conveyed to the actual hardware I/O interface.
- *
- * The number of possible outstanding asynchronous requests is defined by
- * each driver, but it is recommended that it be at least two requests
- * per tile per device.
- *
- * No ordering is guaranteed between synchronous and asynchronous requests,
- * even those issued on the same tile.
- *
- * The completion interrupt message could come directly, or via the downcall
- * (intctrl1) method, depending on what the tile is doing when the read
- * completes. Interrupts do not coalesce; one is delivered for each
- * asynchronous I/O request. Note that it is possible for the requested
- * interrupt to be delivered after this service is called but before it
- * returns.
- *
- * Devices may choose to support both the synchronous and asynchronous write
- * operations, only one of them, or neither of them.
- *
- * @param devhdl Device handle of the device to be read from.
- * @param flags Flags (HV_DEV_xxx).
- * @param sgl_len Number of elements in the scatter-gather list.
- * @param sgl Scatter-gather list describing the memory from which data will be
- * read.
- * @param offset Driver-dependent offset. For a random-access device, this is
- * often a byte offset from the beginning of the device; in other cases,
- * like on a control device, it may have a different meaning.
- * @param intarg Value which will be delivered as the intarg member of the
- * eventual interrupt message; the intdata member will be set to the
- * normal return value from the write request.
- * @return Zero if the write was successfully scheduled; otherwise, a negative
- * error code. Note that some drivers may choose to pre-validate
- * their arguments, and may thus detect certain device error
- * conditions at this time rather than when the completion notification
- * occurs, but this is not required.
- */
-int hv_dev_pwritea(int devhdl, __hv32 flags, __hv32 sgl_len,
- HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
-
-
-/** Define a pair of tile and ASID to identify a user process context. */
-typedef struct
-{
- /** X coordinate, relative to supervisor's top-left coordinate */
- unsigned int x:11;
-
- /** Y coordinate, relative to supervisor's top-left coordinate */
- unsigned int y:11;
-
- /** ASID of the process on this x,y tile */
- HV_ASID asid:10;
-} HV_Remote_ASID;
-
-/** Flush cache and/or TLB state on remote tiles.
- *
- * @param cache_pa Client physical address to flush from cache (ignored if
- * the length encoded in cache_control is zero, or if
- * HV_FLUSH_EVICT_L2 is set, or if cache_cpumask is NULL).
- * @param cache_control This argument allows you to specify a length of
- * physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN).
- * You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache.
- * You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache.
- * HV_FLUSH_ALL flushes all caches.
- * @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of
- * tile indices to perform cache flush on. The low bit of the first
- * word corresponds to the tile at the upper left-hand corner of the
- * supervisor's rectangle. If passed as a NULL pointer, equivalent
- * to an empty bitmask. On chips which support hash-for-home caching,
- * if passed as -1, equivalent to a mask containing tiles which could
- * be doing hash-for-home caching.
- * @param tlb_va Virtual address to flush from TLB (ignored if
- * tlb_length is zero or tlb_cpumask is NULL).
- * @param tlb_length Number of bytes of data to flush from the TLB.
- * @param tlb_pgsize Page size to use for TLB flushes.
- * tlb_va and tlb_length need not be aligned to this size.
- * @param tlb_cpumask Bitmask for tlb flush, like cache_cpumask.
- * If passed as a NULL pointer, equivalent to an empty bitmask.
- * @param asids Pointer to an HV_Remote_ASID array of tile/ASID pairs to flush.
- * @param asidcount Number of HV_Remote_ASID entries in asids[].
- * @return Zero for success, or else HV_EINVAL or HV_EFAULT for errors that
- * are detected while parsing the arguments.
- */
-int hv_flush_remote(HV_PhysAddr cache_pa, unsigned long cache_control,
- unsigned long* cache_cpumask,
- HV_VirtAddr tlb_va, unsigned long tlb_length,
- unsigned long tlb_pgsize, unsigned long* tlb_cpumask,
- HV_Remote_ASID* asids, int asidcount);
-
-/** Include in cache_control to ensure a flush of the entire L2. */
-#define HV_FLUSH_EVICT_L2 (1UL << 31)
-
-/** Include in cache_control to ensure a flush of the entire L1I. */
-#define HV_FLUSH_EVICT_L1I (1UL << 30)
-
-/** Maximum legal size to use for the "length" component of cache_control. */
-#define HV_FLUSH_MAX_CACHE_LEN ((1UL << 30) - 1)
-
-/** Use for cache_control to ensure a flush of all caches. */
-#define HV_FLUSH_ALL -1UL
-
-#else /* __ASSEMBLER__ */
-
-/** Include in cache_control to ensure a flush of the entire L2. */
-#define HV_FLUSH_EVICT_L2 (1 << 31)
-
-/** Include in cache_control to ensure a flush of the entire L1I. */
-#define HV_FLUSH_EVICT_L1I (1 << 30)
-
-/** Maximum legal size to use for the "length" component of cache_control. */
-#define HV_FLUSH_MAX_CACHE_LEN ((1 << 30) - 1)
-
-/** Use for cache_control to ensure a flush of all caches. */
-#define HV_FLUSH_ALL -1
-
-#endif /* __ASSEMBLER__ */
-
-#ifndef __ASSEMBLER__
-
-/** Return a 64-bit value corresponding to the PTE if needed */
-#define hv_pte_val(pte) ((pte).val)
-
-/** Cast a 64-bit value to an HV_PTE */
-#define hv_pte(val) ((HV_PTE) { val })
-
-#endif /* !__ASSEMBLER__ */
-
-
-/** Bits in the size of an HV_PTE */
-#define HV_LOG2_PTE_SIZE 3
-
-/** Size of an HV_PTE */
-#define HV_PTE_SIZE (1 << HV_LOG2_PTE_SIZE)
-
-
-/* Bits in HV_PTE's low word. */
-#define HV_PTE_INDEX_PRESENT 0 /**< PTE is valid */
-#define HV_PTE_INDEX_MIGRATING 1 /**< Page is migrating */
-#define HV_PTE_INDEX_CLIENT0 2 /**< Page client state 0 */
-#define HV_PTE_INDEX_CLIENT1 3 /**< Page client state 1 */
-#define HV_PTE_INDEX_NC 4 /**< L1$/L2$ incoherent with L3$ */
-#define HV_PTE_INDEX_NO_ALLOC_L1 5 /**< Page is uncached in local L1$ */
-#define HV_PTE_INDEX_NO_ALLOC_L2 6 /**< Page is uncached in local L2$ */
-#define HV_PTE_INDEX_CACHED_PRIORITY 7 /**< Page is priority cached */
-#define HV_PTE_INDEX_PAGE 8 /**< PTE describes a page */
-#define HV_PTE_INDEX_GLOBAL 9 /**< Page is global */
-#define HV_PTE_INDEX_USER 10 /**< Page is user-accessible */
-#define HV_PTE_INDEX_ACCESSED 11 /**< Page has been accessed */
-#define HV_PTE_INDEX_DIRTY 12 /**< Page has been written */
- /* Bits 13-14 are reserved for
- future use. */
-#define HV_PTE_INDEX_SUPER 15 /**< Pages ganged together for TLB */
-#define HV_PTE_INDEX_MODE 16 /**< Page mode; see HV_PTE_MODE_xxx */
-#define HV_PTE_MODE_BITS 3 /**< Number of bits in mode */
-#define HV_PTE_INDEX_CLIENT2 19 /**< Page client state 2 */
-#define HV_PTE_INDEX_LOTAR 20 /**< Page's LOTAR; must be high bits
- of word */
-#define HV_PTE_LOTAR_BITS 12 /**< Number of bits in a LOTAR */
-
-/* Bits in HV_PTE's high word. */
-#define HV_PTE_INDEX_READABLE 32 /**< Page is readable */
-#define HV_PTE_INDEX_WRITABLE 33 /**< Page is writable */
-#define HV_PTE_INDEX_EXECUTABLE 34 /**< Page is executable */
-#define HV_PTE_INDEX_PTFN 35 /**< Page's PTFN; must be high bits
- of word */
-#define HV_PTE_PTFN_BITS 29 /**< Number of bits in a PTFN */
-
-/*
- * Legal values for the PTE's mode field
- */
-/** Data is not resident in any caches; loads and stores access memory
- * directly.
- */
-#define HV_PTE_MODE_UNCACHED 1
-
-/** Data is resident in the tile's local L1 and/or L2 caches; if a load
- * or store misses there, it goes to memory.
- *
- * The copy in the local L1$/L2$ is not invalidated when the copy in
- * memory is changed.
- */
-#define HV_PTE_MODE_CACHE_NO_L3 2
-
-/** Data is resident in the tile's local L1 and/or L2 caches. If a load
- * or store misses there, it goes to an L3 cache in a designated tile;
- * if it misses there, it goes to memory.
- *
- * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
- * when the copy in the remote L3$ is changed. Otherwise, such
- * invalidation will not occur.
- *
- * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
- * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
- * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
- */
-#define HV_PTE_MODE_CACHE_TILE_L3 3
-
-/** Data is resident in the tile's local L1 and/or L2 caches. If a load
- * or store misses there, it goes to an L3 cache in one of a set of
- * designated tiles; if it misses there, it goes to memory. Which tile
- * is chosen from the set depends upon a hash function applied to the
- * physical address. This mode is not supported on chips for which
- * CHIP_HAS_CBOX_HOME_MAP() is 0.
- *
- * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
- * when the copy in the remote L3$ is changed. Otherwise, such
- * invalidation will not occur.
- *
- * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
- * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
- * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
- */
-#define HV_PTE_MODE_CACHE_HASH_L3 4
-
-/** Data is not resident in memory; accesses are instead made to an I/O
- * device, whose tile coordinates are given by the PTE's LOTAR field.
- * This mode is only supported on chips for which CHIP_HAS_MMIO() is 1.
- * The EXECUTABLE bit may not be set in an MMIO PTE.
- */
-#define HV_PTE_MODE_MMIO 5
-
-
-/* C wants 1ULL so it is typed as __hv64, but the assembler needs just numbers.
- * The assembler can't handle shifts greater than 31, but treats them
- * as shifts mod 32, so assembler code must be aware of which word
- * the bit belongs in when using these macros.
- */
-#ifdef __ASSEMBLER__
-#define __HV_PTE_ONE 1 /**< One, for assembler */
-#else
-#define __HV_PTE_ONE 1ULL /**< One, for C */
-#endif
-
-/** Is this PTE present?
- *
- * If this bit is set, this PTE represents a valid translation or level-2
- * page table pointer. Otherwise, the page table does not contain a
- * translation for the subject virtual pages.
- *
- * If this bit is not set, the other bits in the PTE are not
- * interpreted by the hypervisor, and may contain any value.
- */
-#define HV_PTE_PRESENT (__HV_PTE_ONE << HV_PTE_INDEX_PRESENT)
-
-/** Does this PTE map a page?
- *
- * If this bit is set in a level-0 page table, the entry should be
- * interpreted as a level-2 page table entry mapping a jumbo page.
- *
- * If this bit is set in a level-1 page table, the entry should be
- * interpreted as a level-2 page table entry mapping a large page.
- *
- * This bit should not be modified by the client while PRESENT is set, as
- * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
- *
- * In a level-2 page table, this bit is ignored and must be zero.
- */
-#define HV_PTE_PAGE (__HV_PTE_ONE << HV_PTE_INDEX_PAGE)
-
-/** Does this PTE implicitly reference multiple pages?
- *
- * If this bit is set in the page table (either in the level-2 page table,
- * or in a higher level page table in conjunction with the PAGE bit)
- * then the PTE specifies a range of contiguous pages, not a single page.
- * The hv_set_pte_super_shift() allows you to specify the count for
- * each level of the page table.
- *
- * Note: this bit is not supported on TILEPro systems.
- */
-#define HV_PTE_SUPER (__HV_PTE_ONE << HV_PTE_INDEX_SUPER)
-
-/** Is this a global (non-ASID) mapping?
- *
- * If this bit is set, the translations established by this PTE will
- * not be flushed from the TLB by the hv_flush_asid() service; they
- * will be flushed by the hv_flush_page() or hv_flush_pages() services.
- *
- * Setting this bit for translations which are identical in all page
- * tables (for instance, code and data belonging to a client OS) can
- * be very beneficial, as it will reduce the number of TLB misses.
- * Note that, while it is not an error which will be detected by the
- * hypervisor, it is an extremely bad idea to set this bit for
- * translations which are _not_ identical in all page tables.
- *
- * This bit should not be modified by the client while PRESENT is set, as
- * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_GLOBAL (__HV_PTE_ONE << HV_PTE_INDEX_GLOBAL)
-
-/** Is this mapping accessible to users?
- *
- * If this bit is set, code running at any PL will be permitted to
- * access the virtual addresses mapped by this PTE. Otherwise, only
- * code running at PL 1 or above will be allowed to do so.
- *
- * This bit should not be modified by the client while PRESENT is set, as
- * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_USER (__HV_PTE_ONE << HV_PTE_INDEX_USER)
-
-/** Has this mapping been accessed?
- *
- * This bit is set by the hypervisor when the memory described by the
- * translation is accessed for the first time. It is never cleared by
- * the hypervisor, but may be cleared by the client. After the bit
- * has been cleared, subsequent references are not guaranteed to set
- * it again until the translation has been flushed from the TLB.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_ACCESSED (__HV_PTE_ONE << HV_PTE_INDEX_ACCESSED)
-
-/** Is this mapping dirty?
- *
- * This bit is set by the hypervisor when the memory described by the
- * translation is written for the first time. It is never cleared by
- * the hypervisor, but may be cleared by the client. After the bit
- * has been cleared, subsequent references are not guaranteed to set
- * it again until the translation has been flushed from the TLB.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_DIRTY (__HV_PTE_ONE << HV_PTE_INDEX_DIRTY)
-
-/** Migrating bit in PTE.
- *
- * This bit is guaranteed not to be inspected or modified by the
- * hypervisor. The name is indicative of the suggested use by the client
- * to tag pages whose L3 cache is being migrated from one cpu to another.
- */
-#define HV_PTE_MIGRATING (__HV_PTE_ONE << HV_PTE_INDEX_MIGRATING)
-
-/** Client-private bit in PTE.
- *
- * This bit is guaranteed not to be inspected or modified by the
- * hypervisor.
- */
-#define HV_PTE_CLIENT0 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT0)
-
-/** Client-private bit in PTE.
- *
- * This bit is guaranteed not to be inspected or modified by the
- * hypervisor.
- */
-#define HV_PTE_CLIENT1 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT1)
-
-/** Client-private bit in PTE.
- *
- * This bit is guaranteed not to be inspected or modified by the
- * hypervisor.
- */
-#define HV_PTE_CLIENT2 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT2)
-
-/** Non-coherent (NC) bit in PTE.
- *
- * If this bit is set, the mapping that is set up will be non-coherent
- * (also known as non-inclusive). This means that changes to the L3
- * cache will not cause a local copy to be invalidated. It is generally
- * recommended only for read-only mappings.
- *
- * In level-1 PTEs, if the Page bit is clear, this bit determines how the
- * level-2 page table is accessed.
- */
-#define HV_PTE_NC (__HV_PTE_ONE << HV_PTE_INDEX_NC)
-
-/** Is this page prevented from filling the L1$?
- *
- * If this bit is set, the page described by the PTE will not be cached
- * the local cpu's L1 cache.
- *
- * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
- * it is illegal to use this attribute, and may cause client termination.
- *
- * In level-1 PTEs, if the Page bit is clear, this bit
- * determines how the level-2 page table is accessed.
- */
-#define HV_PTE_NO_ALLOC_L1 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L1)
-
-/** Is this page prevented from filling the L2$?
- *
- * If this bit is set, the page described by the PTE will not be cached
- * the local cpu's L2 cache.
- *
- * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
- * it is illegal to use this attribute, and may cause client termination.
- *
- * In level-1 PTEs, if the Page bit is clear, this bit determines how the
- * level-2 page table is accessed.
- */
-#define HV_PTE_NO_ALLOC_L2 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L2)
-
-/** Is this a priority page?
- *
- * If this bit is set, the page described by the PTE will be given
- * priority in the cache. Normally this translates into allowing the
- * page to use only the "red" half of the cache. The client may wish to
- * then use the hv_set_caching service to specify that other pages which
- * alias this page will use only the "black" half of the cache.
- *
- * If the Cached Priority bit is clear, the hypervisor uses the
- * current hv_set_caching() value to choose how to cache the page.
- *
- * It is illegal to set the Cached Priority bit if the Non-Cached bit
- * is set and the Cached Remotely bit is clear, i.e. if requests to
- * the page map directly to memory.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_CACHED_PRIORITY (__HV_PTE_ONE << \
- HV_PTE_INDEX_CACHED_PRIORITY)
-
-/** Is this a readable mapping?
- *
- * If this bit is set, code will be permitted to read from (e.g.,
- * issue load instructions against) the virtual addresses mapped by
- * this PTE.
- *
- * It is illegal for this bit to be clear if the Writable bit is set.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_READABLE (__HV_PTE_ONE << HV_PTE_INDEX_READABLE)
-
-/** Is this a writable mapping?
- *
- * If this bit is set, code will be permitted to write to (e.g., issue
- * store instructions against) the virtual addresses mapped by this
- * PTE.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_WRITABLE (__HV_PTE_ONE << HV_PTE_INDEX_WRITABLE)
-
-/** Is this an executable mapping?
- *
- * If this bit is set, code will be permitted to execute from
- * (e.g., jump to) the virtual addresses mapped by this PTE.
- *
- * This bit applies to any processor on the tile, if there are more
- * than one.
- *
- * This bit is ignored in level-1 PTEs unless the Page bit is set.
- */
-#define HV_PTE_EXECUTABLE (__HV_PTE_ONE << HV_PTE_INDEX_EXECUTABLE)
-
-/** The width of a LOTAR's x or y bitfield. */
-#define HV_LOTAR_WIDTH 11
-
-/** Converts an x,y pair to a LOTAR value. */
-#define HV_XY_TO_LOTAR(x, y) ((HV_LOTAR)(((x) << HV_LOTAR_WIDTH) | (y)))
-
-/** Extracts the X component of a lotar. */
-#define HV_LOTAR_X(lotar) ((lotar) >> HV_LOTAR_WIDTH)
-
-/** Extracts the Y component of a lotar. */
-#define HV_LOTAR_Y(lotar) ((lotar) & ((1 << HV_LOTAR_WIDTH) - 1))
-
-#ifndef __ASSEMBLER__
-
-/** Define accessor functions for a PTE bit. */
-#define _HV_BIT(name, bit) \
-static __inline int \
-hv_pte_get_##name(HV_PTE pte) \
-{ \
- return (pte.val >> HV_PTE_INDEX_##bit) & 1; \
-} \
- \
-static __inline HV_PTE \
-hv_pte_set_##name(HV_PTE pte) \
-{ \
- pte.val |= 1ULL << HV_PTE_INDEX_##bit; \
- return pte; \
-} \
- \
-static __inline HV_PTE \
-hv_pte_clear_##name(HV_PTE pte) \
-{ \
- pte.val &= ~(1ULL << HV_PTE_INDEX_##bit); \
- return pte; \
-}
-
-/* Generate accessors to get, set, and clear various PTE flags.
- */
-_HV_BIT(present, PRESENT)
-_HV_BIT(page, PAGE)
-_HV_BIT(super, SUPER)
-_HV_BIT(client0, CLIENT0)
-_HV_BIT(client1, CLIENT1)
-_HV_BIT(client2, CLIENT2)
-_HV_BIT(migrating, MIGRATING)
-_HV_BIT(nc, NC)
-_HV_BIT(readable, READABLE)
-_HV_BIT(writable, WRITABLE)
-_HV_BIT(executable, EXECUTABLE)
-_HV_BIT(accessed, ACCESSED)
-_HV_BIT(dirty, DIRTY)
-_HV_BIT(no_alloc_l1, NO_ALLOC_L1)
-_HV_BIT(no_alloc_l2, NO_ALLOC_L2)
-_HV_BIT(cached_priority, CACHED_PRIORITY)
-_HV_BIT(global, GLOBAL)
-_HV_BIT(user, USER)
-
-#undef _HV_BIT
-
-/** Get the page mode from the PTE.
- *
- * This field generally determines whether and how accesses to the page
- * are cached; the HV_PTE_MODE_xxx symbols define the legal values for the
- * page mode. The NC, NO_ALLOC_L1, and NO_ALLOC_L2 bits modify this
- * general policy.
- */
-static __inline unsigned int
-hv_pte_get_mode(const HV_PTE pte)
-{
- return (((__hv32) pte.val) >> HV_PTE_INDEX_MODE) &
- ((1 << HV_PTE_MODE_BITS) - 1);
-}
-
-/** Set the page mode into a PTE. See hv_pte_get_mode. */
-static __inline HV_PTE
-hv_pte_set_mode(HV_PTE pte, unsigned int val)
-{
- pte.val &= ~(((1ULL << HV_PTE_MODE_BITS) - 1) << HV_PTE_INDEX_MODE);
- pte.val |= val << HV_PTE_INDEX_MODE;
- return pte;
-}
-
-/** Get the page frame number from the PTE.
- *
- * This field contains the upper bits of the CPA (client physical
- * address) of the target page; the complete CPA is this field with
- * HV_LOG2_PAGE_TABLE_ALIGN zero bits appended to it.
- *
- * For all PTEs in the lowest-level page table, and for all PTEs with
- * the Page bit set in all page tables, the CPA must be aligned modulo
- * the relevant page size.
- */
-static __inline unsigned long
-hv_pte_get_ptfn(const HV_PTE pte)
-{
- return pte.val >> HV_PTE_INDEX_PTFN;
-}
-
-/** Set the page table frame number into a PTE. See hv_pte_get_ptfn. */
-static __inline HV_PTE
-hv_pte_set_ptfn(HV_PTE pte, unsigned long val)
-{
- pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS)-1) << HV_PTE_INDEX_PTFN);
- pte.val |= (__hv64) val << HV_PTE_INDEX_PTFN;
- return pte;
-}
-
-/** Get the client physical address from the PTE. See hv_pte_set_ptfn. */
-static __inline HV_PhysAddr
-hv_pte_get_pa(const HV_PTE pte)
-{
- return (__hv64) hv_pte_get_ptfn(pte) << HV_LOG2_PAGE_TABLE_ALIGN;
-}
-
-/** Set the client physical address into a PTE. See hv_pte_get_ptfn. */
-static __inline HV_PTE
-hv_pte_set_pa(HV_PTE pte, HV_PhysAddr pa)
-{
- return hv_pte_set_ptfn(pte, pa >> HV_LOG2_PAGE_TABLE_ALIGN);
-}
-
-
-/** Get the remote tile caching this page.
- *
- * Specifies the remote tile which is providing the L3 cache for this page.
- *
- * This field is ignored unless the page mode is HV_PTE_MODE_CACHE_TILE_L3.
- *
- * In level-1 PTEs, if the Page bit is clear, this field determines how the
- * level-2 page table is accessed.
- */
-static __inline unsigned int
-hv_pte_get_lotar(const HV_PTE pte)
-{
- unsigned int lotar = ((__hv32) pte.val) >> HV_PTE_INDEX_LOTAR;
-
- return HV_XY_TO_LOTAR( (lotar >> (HV_PTE_LOTAR_BITS / 2)),
- (lotar & ((1 << (HV_PTE_LOTAR_BITS / 2)) - 1)) );
-}
-
-
-/** Set the remote tile caching a page into a PTE. See hv_pte_get_lotar. */
-static __inline HV_PTE
-hv_pte_set_lotar(HV_PTE pte, unsigned int val)
-{
- unsigned int x = HV_LOTAR_X(val);
- unsigned int y = HV_LOTAR_Y(val);
-
- pte.val &= ~(((1ULL << HV_PTE_LOTAR_BITS)-1) << HV_PTE_INDEX_LOTAR);
- pte.val |= (x << (HV_PTE_INDEX_LOTAR + HV_PTE_LOTAR_BITS / 2)) |
- (y << HV_PTE_INDEX_LOTAR);
- return pte;
-}
-
-#endif /* !__ASSEMBLER__ */
-
-/** Converts a client physical address to a ptfn. */
-#define HV_CPA_TO_PTFN(p) ((p) >> HV_LOG2_PAGE_TABLE_ALIGN)
-
-/** Converts a ptfn to a client physical address. */
-#define HV_PTFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_TABLE_ALIGN)
-
-#if CHIP_VA_WIDTH() > 32
-
-/*
- * Note that we currently do not allow customizing the page size
- * of the L0 pages, but fix them at 4GB, so we do not use the
- * "_HV_xxx" nomenclature for the L0 macros.
- */
-
-/** Log number of HV_PTE entries in L0 page table */
-#define HV_LOG2_L0_ENTRIES (CHIP_VA_WIDTH() - HV_LOG2_L1_SPAN)
-
-/** Number of HV_PTE entries in L0 page table */
-#define HV_L0_ENTRIES (1 << HV_LOG2_L0_ENTRIES)
-
-/** Log size of L0 page table in bytes */
-#define HV_LOG2_L0_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L0_ENTRIES)
-
-/** Size of L0 page table in bytes */
-#define HV_L0_SIZE (1 << HV_LOG2_L0_SIZE)
-
-#ifdef __ASSEMBLER__
-
-/** Index in L0 for a specific VA */
-#define HV_L0_INDEX(va) \
- (((va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
-
-#else
-
-/** Index in L1 for a specific VA */
-#define HV_L0_INDEX(va) \
- (((HV_VirtAddr)(va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
-
-#endif
-
-#endif /* CHIP_VA_WIDTH() > 32 */
-
-/** Log number of HV_PTE entries in L1 page table */
-#define _HV_LOG2_L1_ENTRIES(log2_page_size_large) \
- (HV_LOG2_L1_SPAN - log2_page_size_large)
-
-/** Number of HV_PTE entries in L1 page table */
-#define _HV_L1_ENTRIES(log2_page_size_large) \
- (1 << _HV_LOG2_L1_ENTRIES(log2_page_size_large))
-
-/** Log size of L1 page table in bytes */
-#define _HV_LOG2_L1_SIZE(log2_page_size_large) \
- (HV_LOG2_PTE_SIZE + _HV_LOG2_L1_ENTRIES(log2_page_size_large))
-
-/** Size of L1 page table in bytes */
-#define _HV_L1_SIZE(log2_page_size_large) \
- (1 << _HV_LOG2_L1_SIZE(log2_page_size_large))
-
-/** Log number of HV_PTE entries in level-2 page table */
-#define _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \
- (log2_page_size_large - log2_page_size_small)
-
-/** Number of HV_PTE entries in level-2 page table */
-#define _HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \
- (1 << _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small))
-
-/** Log size of level-2 page table in bytes */
-#define _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small) \
- (HV_LOG2_PTE_SIZE + \
- _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small))
-
-/** Size of level-2 page table in bytes */
-#define _HV_L2_SIZE(log2_page_size_large, log2_page_size_small) \
- (1 << _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small))
-
-#ifdef __ASSEMBLER__
-
-#if CHIP_VA_WIDTH() > 32
-
-/** Index in L1 for a specific VA */
-#define _HV_L1_INDEX(va, log2_page_size_large) \
- (((va) >> log2_page_size_large) & (_HV_L1_ENTRIES(log2_page_size_large) - 1))
-
-#else /* CHIP_VA_WIDTH() > 32 */
-
-/** Index in L1 for a specific VA */
-#define _HV_L1_INDEX(va, log2_page_size_large) \
- (((va) >> log2_page_size_large))
-
-#endif /* CHIP_VA_WIDTH() > 32 */
-
-/** Index in level-2 page table for a specific VA */
-#define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \
- (((va) >> log2_page_size_small) & \
- (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1))
-
-#else /* __ASSEMBLER __ */
-
-#if CHIP_VA_WIDTH() > 32
-
-/** Index in L1 for a specific VA */
-#define _HV_L1_INDEX(va, log2_page_size_large) \
- (((HV_VirtAddr)(va) >> log2_page_size_large) & \
- (_HV_L1_ENTRIES(log2_page_size_large) - 1))
-
-#else /* CHIP_VA_WIDTH() > 32 */
-
-/** Index in L1 for a specific VA */
-#define _HV_L1_INDEX(va, log2_page_size_large) \
- (((HV_VirtAddr)(va) >> log2_page_size_large))
-
-#endif /* CHIP_VA_WIDTH() > 32 */
-
-/** Index in level-2 page table for a specific VA */
-#define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \
- (((HV_VirtAddr)(va) >> log2_page_size_small) & \
- (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1))
-
-#endif /* __ASSEMBLER __ */
-
-/** Position of the PFN field within the PTE (subset of the PTFN). */
-#define _HV_PTE_INDEX_PFN(log2_page_size) \
- (HV_PTE_INDEX_PTFN + (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
-
-/** Length of the PFN field within the PTE (subset of the PTFN). */
-#define _HV_PTE_INDEX_PFN_BITS(log2_page_size) \
- (HV_PTE_INDEX_PTFN_BITS - (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
-
-/** Converts a client physical address to a pfn. */
-#define _HV_CPA_TO_PFN(p, log2_page_size) ((p) >> log2_page_size)
-
-/** Converts a pfn to a client physical address. */
-#define _HV_PFN_TO_CPA(p, log2_page_size) \
- (((HV_PhysAddr)(p)) << log2_page_size)
-
-/** Converts a ptfn to a pfn. */
-#define _HV_PTFN_TO_PFN(p, log2_page_size) \
- ((p) >> (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
-
-/** Converts a pfn to a ptfn. */
-#define _HV_PFN_TO_PTFN(p, log2_page_size) \
- ((p) << (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
-
-#endif /* _HV_HV_H */
diff --git a/arch/tile/include/hv/iorpc.h b/arch/tile/include/hv/iorpc.h
deleted file mode 100644
index ddf1604482b3..000000000000
--- a/arch/tile/include/hv/iorpc.h
+++ /dev/null
@@ -1,714 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-#ifndef _HV_IORPC_H_
-#define _HV_IORPC_H_
-
-/**
- *
- * Error codes and struct definitions for the IO RPC library.
- *
- * The hypervisor's IO RPC component provides a convenient way for
- * driver authors to proxy system calls between user space, linux, and
- * the hypervisor driver. The core of the system is a set of Python
- * files that take ".idl" files as input and generates the following
- * source code:
- *
- * - _rpc_call() routines for use in userspace IO libraries. These
- * routines take an argument list specified in the .idl file, pack the
- * arguments in to a buffer, and read or write that buffer via the
- * Linux iorpc driver.
- *
- * - dispatch_read() and dispatch_write() routines that hypervisor
- * drivers can use to implement most of their dev_pread() and
- * dev_pwrite() methods. These routines decode the incoming parameter
- * blob, permission check and translate parameters where appropriate,
- * and then invoke a callback routine for whichever RPC call has
- * arrived. The driver simply implements the set of callback
- * routines.
- *
- * The IO RPC system also includes the Linux 'iorpc' driver, which
- * proxies calls between the userspace library and the hypervisor
- * driver. The Linux driver is almost entirely device agnostic; it
- * watches for special flags indicating cases where a memory buffer
- * address might need to be translated, etc. As a result, driver
- * writers can avoid many of the problem cases related to registering
- * hardware resources like memory pages or interrupts. However, the
- * drivers must be careful to obey the conventions documented below in
- * order to work properly with the generic Linux iorpc driver.
- *
- * @section iorpc_domains Service Domains
- *
- * All iorpc-based drivers must support a notion of service domains.
- * A service domain is basically an application context - state
- * indicating resources that are allocated to that particular app
- * which it may access and (perhaps) other applications may not
- * access. Drivers can support any number of service domains they
- * choose. In some cases the design is limited by a number of service
- * domains supported by the IO hardware; in other cases the service
- * domains are a purely software concept and the driver chooses a
- * maximum number of domains based on how much state memory it is
- * willing to preallocate.
- *
- * For example, the mPIPE driver only supports as many service domains
- * as are supported by the mPIPE hardware. This limitation is
- * required because the hardware implements its own MMIO protection
- * scheme to allow large MMIO mappings while still protecting small
- * register ranges within the page that should only be accessed by the
- * hypervisor.
- *
- * In contrast, drivers with no hardware service domain limitations
- * (for instance the TRIO shim) can implement an arbitrary number of
- * service domains. In these cases, each service domain is limited to
- * a carefully restricted set of legal MMIO addresses if necessary to
- * keep one application from corrupting another application's state.
- *
- * @section iorpc_conventions System Call Conventions
- *
- * The driver's open routine is responsible for allocating a new
- * service domain for each hv_dev_open() call. By convention, the
- * return value from open() should be the service domain number on
- * success, or GXIO_ERR_NO_SVC_DOM if no more service domains are
- * available.
- *
- * The implementations of hv_dev_pread() and hv_dev_pwrite() are
- * responsible for validating the devhdl value passed up by the
- * client. Since the device handle returned by hv_dev_open() should
- * embed the positive service domain number, drivers should make sure
- * that DRV_HDL2BITS(devhdl) is a legal service domain. If the client
- * passes an illegal service domain number, the routine should return
- * GXIO_ERR_INVAL_SVC_DOM. Once the service domain number has been
- * validated, the driver can copy to/from the client buffer and call
- * the dispatch_read() or dispatch_write() methods created by the RPC
- * generator.
- *
- * The hv_dev_close() implementation should reset all service domain
- * state and put the service domain back on a free list for
- * reallocation by a future application. In most cases, this will
- * require executing a hardware reset or drain flow and denying any
- * MMIO regions that were created for the service domain.
- *
- * @section iorpc_data Special Data Types
- *
- * The .idl file syntax allows the creation of syscalls with special
- * parameters that require permission checks or translations as part
- * of the system call path. Because of limitations in the code
- * generator, APIs are generally limited to just one of these special
- * parameters per system call, and they are sometimes required to be
- * the first or last parameter to the call. Special parameters
- * include:
- *
- * @subsection iorpc_mem_buffer MEM_BUFFER
- *
- * The MEM_BUFFER() datatype allows user space to "register" memory
- * buffers with a device. Registering memory accomplishes two tasks:
- * Linux keeps track of all buffers that might be modified by a
- * hardware device, and the hardware device drivers bind registered
- * buffers to particular hardware resources like ingress NotifRings.
- * The MEM_BUFFER() idl syntax can take extra flags like ALIGN_64KB,
- * ALIGN_SELF_SIZE, and FLAGS indicating that memory buffers must have
- * certain alignment or that the user should be able to pass a "memory
- * flags" word specifying attributes like nt_hint or IO cache pinning.
- * The parser will accept multiple MEM_BUFFER() flags.
- *
- * Implementations must obey the following conventions when
- * registering memory buffers via the iorpc flow. These rules are a
- * result of the Linux driver implementation, which needs to keep
- * track of how many times a particular page has been registered with
- * the hardware so that it can release the page when all those
- * registrations are cleared.
- *
- * - Memory registrations that refer to a resource which has already
- * been bound must return GXIO_ERR_ALREADY_INIT. Thus, it is an
- * error to register memory twice without resetting (i.e. closing) the
- * resource in between. This convention keeps the Linux driver from
- * having to track which particular devices a page is bound to.
- *
- * - At present, a memory registration is only cleared when the
- * service domain is reset. In this case, the Linux driver simply
- * closes the HV device file handle and then decrements the reference
- * counts of all pages that were previously registered with the
- * device.
- *
- * - In the future, we may add a mechanism for unregistering memory.
- * One possible implementation would require that the user specify
- * which buffer is currently registered. The HV would then verify
- * that that page was actually the one currently mapped and return
- * success or failure to Linux, which would then only decrement the
- * page reference count if the addresses were mapped. Another scheme
- * might allow Linux to pass a token to the HV to be returned when the
- * resource is unmapped.
- *
- * @subsection iorpc_interrupt INTERRUPT
- *
- * The INTERRUPT .idl datatype allows the client to bind hardware
- * interrupts to a particular combination of IPI parameters - CPU, IPI
- * PL, and event bit number. This data is passed via a special
- * datatype so that the Linux driver can validate the CPU and PL and
- * the HV generic iorpc code can translate client CPUs to real CPUs.
- *
- * @subsection iorpc_pollfd_setup POLLFD_SETUP
- *
- * The POLLFD_SETUP .idl datatype allows the client to set up hardware
- * interrupt bindings which are received by Linux but which are made
- * visible to user processes as state transitions on a file descriptor;
- * this allows user processes to use Linux primitives, such as poll(), to
- * await particular hardware events. This data is passed via a special
- * datatype so that the Linux driver may recognize the pollable file
- * descriptor and translate it to a set of interrupt target information,
- * and so that the HV generic iorpc code can translate client CPUs to real
- * CPUs.
- *
- * @subsection iorpc_pollfd POLLFD
- *
- * The POLLFD .idl datatype allows manipulation of hardware interrupt
- * bindings set up via the POLLFD_SETUP datatype; common operations are
- * resetting the state of the requested interrupt events, and unbinding any
- * bound interrupts. This data is passed via a special datatype so that
- * the Linux driver may recognize the pollable file descriptor and
- * translate it to an interrupt identifier previously supplied by the
- * hypervisor as the result of an earlier pollfd_setup operation.
- *
- * @subsection iorpc_blob BLOB
- *
- * The BLOB .idl datatype allows the client to write an arbitrary
- * length string of bytes up to the hypervisor driver. This can be
- * useful for passing up large, arbitrarily structured data like
- * classifier programs. The iorpc stack takes care of validating the
- * buffer VA and CPA as the data passes up to the hypervisor. Unlike
- * MEM_BUFFER(), the buffer is not registered - Linux does not bump
- * page refcounts and the HV driver should not reuse the buffer once
- * the system call is complete.
- *
- * @section iorpc_translation Translating User Space Calls
- *
- * The ::iorpc_offset structure describes the formatting of the offset
- * that is passed to pread() or pwrite() as part of the generated RPC code.
- * When the user calls up to Linux, the rpc code fills in all the fields of
- * the offset, including a 16-bit opcode, a 16 bit format indicator, and 32
- * bits of user-specified "sub-offset". The opcode indicates which syscall
- * is being requested. The format indicates whether there is a "prefix
- * struct" at the start of the memory buffer passed to pwrite(), and if so
- * what data is in that prefix struct. These prefix structs are used to
- * implement special datatypes like MEM_BUFFER() and INTERRUPT - we arrange
- * to put data that needs translation and permission checks at the start of
- * the buffer so that the Linux driver and generic portions of the HV iorpc
- * code can easily access the data. The 32 bits of user-specified
- * "sub-offset" are most useful for pread() calls where the user needs to
- * also pass in a few bits indicating which register to read, etc.
- *
- * The Linux iorpc driver watches for system calls that contain prefix
- * structs so that it can translate parameters and bump reference
- * counts as appropriate. It does not (currently) have any knowledge
- * of the per-device opcodes - it doesn't care what operation you're
- * doing to mPIPE, so long as it can do all the generic book-keeping.
- * The hv/iorpc.h header file defines all of the generic encoding bits
- * needed to translate iorpc calls without knowing which particular
- * opcode is being issued.
- *
- * @section iorpc_globals Global iorpc Calls
- *
- * Implementing mmap() required adding some special iorpc syscalls
- * that are only called by the Linux driver, never by userspace.
- * These include get_mmio_base() and check_mmio_offset(). These
- * routines are described in globals.idl and must be included in every
- * iorpc driver. By providing these routines in every driver, Linux's
- * mmap implementation can easily get the PTE bits it needs and
- * validate the PA offset without needing to know the per-device
- * opcodes to perform those tasks.
- *
- * @section iorpc_kernel Supporting gxio APIs in the Kernel
- *
- * The iorpc code generator also supports generation of kernel code
- * implementing the gxio APIs. This capability is currently used by
- * the mPIPE network driver, and will likely be used by the TRIO root
- * complex and endpoint drivers and perhaps an in-kernel crypto
- * driver. Each driver that wants to instantiate iorpc calls in the
- * kernel needs to generate a kernel version of the generate rpc code
- * and (probably) copy any related gxio source files into the kernel.
- * The mPIPE driver provides a good example of this pattern.
- */
-
-#ifdef __KERNEL__
-#include <linux/stddef.h>
-#else
-#include <stddef.h>
-#endif
-
-#if defined(__HV__)
-#include <hv/hypervisor.h>
-#elif defined(__KERNEL__)
-#include <hv/hypervisor.h>
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-
-/** Code indicating translation services required within the RPC path.
- * These indicate whether there is a translatable struct at the start
- * of the RPC buffer and what information that struct contains.
- */
-enum iorpc_format_e
-{
- /** No translation required, no prefix struct. */
- IORPC_FORMAT_NONE,
-
- /** No translation required, no prefix struct, no access to this
- * operation from user space. */
- IORPC_FORMAT_NONE_NOUSER,
-
- /** Prefix struct contains user VA and size. */
- IORPC_FORMAT_USER_MEM,
-
- /** Prefix struct contains CPA, size, and homing bits. */
- IORPC_FORMAT_KERNEL_MEM,
-
- /** Prefix struct contains interrupt. */
- IORPC_FORMAT_KERNEL_INTERRUPT,
-
- /** Prefix struct contains user-level interrupt. */
- IORPC_FORMAT_USER_INTERRUPT,
-
- /** Prefix struct contains pollfd_setup (interrupt information). */
- IORPC_FORMAT_KERNEL_POLLFD_SETUP,
-
- /** Prefix struct contains user-level pollfd_setup (file descriptor). */
- IORPC_FORMAT_USER_POLLFD_SETUP,
-
- /** Prefix struct contains pollfd (interrupt cookie). */
- IORPC_FORMAT_KERNEL_POLLFD,
-
- /** Prefix struct contains user-level pollfd (file descriptor). */
- IORPC_FORMAT_USER_POLLFD,
-};
-
-
-/** Generate an opcode given format and code. */
-#define IORPC_OPCODE(FORMAT, CODE) (((FORMAT) << 16) | (CODE))
-
-/** The offset passed through the read() and write() system calls
- combines an opcode with 32 bits of user-specified offset. */
-union iorpc_offset
-{
-#ifndef __BIG_ENDIAN__
- uint64_t offset; /**< All bits. */
-
- struct
- {
- uint16_t code; /**< RPC code. */
- uint16_t format; /**< iorpc_format_e */
- uint32_t sub_offset; /**< caller-specified offset. */
- };
-
- uint32_t opcode; /**< Opcode combines code & format. */
-#else
- uint64_t offset; /**< All bits. */
-
- struct
- {
- uint32_t sub_offset; /**< caller-specified offset. */
- uint16_t format; /**< iorpc_format_e */
- uint16_t code; /**< RPC code. */
- };
-
- struct
- {
- uint32_t padding;
- uint32_t opcode; /**< Opcode combines code & format. */
- };
-#endif
-};
-
-
-/** Homing and cache hinting bits that can be used by IO devices. */
-struct iorpc_mem_attr
-{
- unsigned int lotar_x:4; /**< lotar X bits (or Gx page_mask). */
- unsigned int lotar_y:4; /**< lotar Y bits (or Gx page_offset). */
- unsigned int hfh:1; /**< Uses hash-for-home. */
- unsigned int nt_hint:1; /**< Non-temporal hint. */
- unsigned int io_pin:1; /**< Only fill 'IO' cache ways. */
-};
-
-/** Set the nt_hint bit. */
-#define IORPC_MEM_BUFFER_FLAG_NT_HINT (1 << 0)
-
-/** Set the IO pin bit. */
-#define IORPC_MEM_BUFFER_FLAG_IO_PIN (1 << 1)
-
-
-/** A structure used to describe memory registration. Different
- protection levels describe memory differently, so this union
- contains all the different possible descriptions. As a request
- moves up the call chain, each layer translates from one
- description format to the next. In particular, the Linux iorpc
- driver translates user VAs into CPAs and homing parameters. */
-union iorpc_mem_buffer
-{
- struct
- {
- uint64_t va; /**< User virtual address. */
- uint64_t size; /**< Buffer size. */
- unsigned int flags; /**< nt_hint, IO pin. */
- }
- user; /**< Buffer as described by user apps. */
-
- struct
- {
- unsigned long long cpa; /**< Client physical address. */
-#if defined(__KERNEL__) || defined(__HV__)
- size_t size; /**< Buffer size. */
- HV_PTE pte; /**< PTE describing memory homing. */
-#else
- uint64_t size;
- uint64_t pte;
-#endif
- unsigned int flags; /**< nt_hint, IO pin. */
- }
- kernel; /**< Buffer as described by kernel. */
-
- struct
- {
- unsigned long long pa; /**< Physical address. */
- size_t size; /**< Buffer size. */
- struct iorpc_mem_attr attr; /**< Homing and locality hint bits. */
- }
- hv; /**< Buffer parameters for HV driver. */
-};
-
-
-/** A structure used to describe interrupts. The format differs slightly
- * for user and kernel interrupts. As with the mem_buffer_t, translation
- * between the formats is done at each level. */
-union iorpc_interrupt
-{
- struct
- {
- int cpu; /**< CPU. */
- int event; /**< evt_num */
- }
- user; /**< Interrupt as described by user applications. */
-
- struct
- {
- int x; /**< X coord. */
- int y; /**< Y coord. */
- int ipi; /**< int_num */
- int event; /**< evt_num */
- }
- kernel; /**< Interrupt as described by the kernel. */
-
-};
-
-
-/** A structure used to describe interrupts used with poll(). The format
- * differs significantly for requests from user to kernel, and kernel to
- * hypervisor. As with the mem_buffer_t, translation between the formats
- * is done at each level. */
-union iorpc_pollfd_setup
-{
- struct
- {
- int fd; /**< Pollable file descriptor. */
- }
- user; /**< pollfd_setup as described by user applications. */
-
- struct
- {
- int x; /**< X coord. */
- int y; /**< Y coord. */
- int ipi; /**< int_num */
- int event; /**< evt_num */
- }
- kernel; /**< pollfd_setup as described by the kernel. */
-
-};
-
-
-/** A structure used to describe previously set up interrupts used with
- * poll(). The format differs significantly for requests from user to
- * kernel, and kernel to hypervisor. As with the mem_buffer_t, translation
- * between the formats is done at each level. */
-union iorpc_pollfd
-{
- struct
- {
- int fd; /**< Pollable file descriptor. */
- }
- user; /**< pollfd as described by user applications. */
-
- struct
- {
- int cookie; /**< hv cookie returned by the pollfd_setup operation. */
- }
- kernel; /**< pollfd as described by the kernel. */
-
-};
-
-
-/** The various iorpc devices use error codes from -1100 to -1299.
- *
- * This range is distinct from netio (-700 to -799), the hypervisor
- * (-800 to -899), tilepci (-900 to -999), ilib (-1000 to -1099),
- * gxcr (-1300 to -1399) and gxpci (-1400 to -1499).
- */
-enum gxio_err_e {
-
- /** Largest iorpc error number. */
- GXIO_ERR_MAX = -1101,
-
-
- /********************************************************/
- /* Generic Error Codes */
- /********************************************************/
-
- /** Bad RPC opcode - possible version incompatibility. */
- GXIO_ERR_OPCODE = -1101,
-
- /** Invalid parameter. */
- GXIO_ERR_INVAL = -1102,
-
- /** Memory buffer did not meet alignment requirements. */
- GXIO_ERR_ALIGNMENT = -1103,
-
- /** Memory buffers must be coherent and cacheable. */
- GXIO_ERR_COHERENCE = -1104,
-
- /** Resource already initialized. */
- GXIO_ERR_ALREADY_INIT = -1105,
-
- /** No service domains available. */
- GXIO_ERR_NO_SVC_DOM = -1106,
-
- /** Illegal service domain number. */
- GXIO_ERR_INVAL_SVC_DOM = -1107,
-
- /** Illegal MMIO address. */
- GXIO_ERR_MMIO_ADDRESS = -1108,
-
- /** Illegal interrupt binding. */
- GXIO_ERR_INTERRUPT = -1109,
-
- /** Unreasonable client memory. */
- GXIO_ERR_CLIENT_MEMORY = -1110,
-
- /** No more IOTLB entries. */
- GXIO_ERR_IOTLB_ENTRY = -1111,
-
- /** Invalid memory size. */
- GXIO_ERR_INVAL_MEMORY_SIZE = -1112,
-
- /** Unsupported operation. */
- GXIO_ERR_UNSUPPORTED_OP = -1113,
-
- /** Insufficient DMA credits. */
- GXIO_ERR_DMA_CREDITS = -1114,
-
- /** Operation timed out. */
- GXIO_ERR_TIMEOUT = -1115,
-
- /** No such device or object. */
- GXIO_ERR_NO_DEVICE = -1116,
-
- /** Device or resource busy. */
- GXIO_ERR_BUSY = -1117,
-
- /** I/O error. */
- GXIO_ERR_IO = -1118,
-
- /** Permissions error. */
- GXIO_ERR_PERM = -1119,
-
-
-
- /********************************************************/
- /* Test Device Error Codes */
- /********************************************************/
-
- /** Illegal register number. */
- GXIO_TEST_ERR_REG_NUMBER = -1120,
-
- /** Illegal buffer slot. */
- GXIO_TEST_ERR_BUFFER_SLOT = -1121,
-
-
- /********************************************************/
- /* MPIPE Error Codes */
- /********************************************************/
-
-
- /** Invalid buffer size. */
- GXIO_MPIPE_ERR_INVAL_BUFFER_SIZE = -1131,
-
- /** Cannot allocate buffer stack. */
- GXIO_MPIPE_ERR_NO_BUFFER_STACK = -1140,
-
- /** Invalid buffer stack number. */
- GXIO_MPIPE_ERR_BAD_BUFFER_STACK = -1141,
-
- /** Cannot allocate NotifRing. */
- GXIO_MPIPE_ERR_NO_NOTIF_RING = -1142,
-
- /** Invalid NotifRing number. */
- GXIO_MPIPE_ERR_BAD_NOTIF_RING = -1143,
-
- /** Cannot allocate NotifGroup. */
- GXIO_MPIPE_ERR_NO_NOTIF_GROUP = -1144,
-
- /** Invalid NotifGroup number. */
- GXIO_MPIPE_ERR_BAD_NOTIF_GROUP = -1145,
-
- /** Cannot allocate bucket. */
- GXIO_MPIPE_ERR_NO_BUCKET = -1146,
-
- /** Invalid bucket number. */
- GXIO_MPIPE_ERR_BAD_BUCKET = -1147,
-
- /** Cannot allocate eDMA ring. */
- GXIO_MPIPE_ERR_NO_EDMA_RING = -1148,
-
- /** Invalid eDMA ring number. */
- GXIO_MPIPE_ERR_BAD_EDMA_RING = -1149,
-
- /** Invalid channel number. */
- GXIO_MPIPE_ERR_BAD_CHANNEL = -1150,
-
- /** Bad configuration. */
- GXIO_MPIPE_ERR_BAD_CONFIG = -1151,
-
- /** Empty iqueue. */
- GXIO_MPIPE_ERR_IQUEUE_EMPTY = -1152,
-
- /** Empty rules. */
- GXIO_MPIPE_ERR_RULES_EMPTY = -1160,
-
- /** Full rules. */
- GXIO_MPIPE_ERR_RULES_FULL = -1161,
-
- /** Corrupt rules. */
- GXIO_MPIPE_ERR_RULES_CORRUPT = -1162,
-
- /** Invalid rules. */
- GXIO_MPIPE_ERR_RULES_INVALID = -1163,
-
- /** Classifier is too big. */
- GXIO_MPIPE_ERR_CLASSIFIER_TOO_BIG = -1170,
-
- /** Classifier is too complex. */
- GXIO_MPIPE_ERR_CLASSIFIER_TOO_COMPLEX = -1171,
-
- /** Classifier has bad header. */
- GXIO_MPIPE_ERR_CLASSIFIER_BAD_HEADER = -1172,
-
- /** Classifier has bad contents. */
- GXIO_MPIPE_ERR_CLASSIFIER_BAD_CONTENTS = -1173,
-
- /** Classifier encountered invalid symbol. */
- GXIO_MPIPE_ERR_CLASSIFIER_INVAL_SYMBOL = -1174,
-
- /** Classifier encountered invalid bounds. */
- GXIO_MPIPE_ERR_CLASSIFIER_INVAL_BOUNDS = -1175,
-
- /** Classifier encountered invalid relocation. */
- GXIO_MPIPE_ERR_CLASSIFIER_INVAL_RELOCATION = -1176,
-
- /** Classifier encountered undefined symbol. */
- GXIO_MPIPE_ERR_CLASSIFIER_UNDEF_SYMBOL = -1177,
-
-
- /********************************************************/
- /* TRIO Error Codes */
- /********************************************************/
-
- /** Cannot allocate memory map region. */
- GXIO_TRIO_ERR_NO_MEMORY_MAP = -1180,
-
- /** Invalid memory map region number. */
- GXIO_TRIO_ERR_BAD_MEMORY_MAP = -1181,
-
- /** Cannot allocate scatter queue. */
- GXIO_TRIO_ERR_NO_SCATTER_QUEUE = -1182,
-
- /** Invalid scatter queue number. */
- GXIO_TRIO_ERR_BAD_SCATTER_QUEUE = -1183,
-
- /** Cannot allocate push DMA ring. */
- GXIO_TRIO_ERR_NO_PUSH_DMA_RING = -1184,
-
- /** Invalid push DMA ring index. */
- GXIO_TRIO_ERR_BAD_PUSH_DMA_RING = -1185,
-
- /** Cannot allocate pull DMA ring. */
- GXIO_TRIO_ERR_NO_PULL_DMA_RING = -1186,
-
- /** Invalid pull DMA ring index. */
- GXIO_TRIO_ERR_BAD_PULL_DMA_RING = -1187,
-
- /** Cannot allocate PIO region. */
- GXIO_TRIO_ERR_NO_PIO = -1188,
-
- /** Invalid PIO region index. */
- GXIO_TRIO_ERR_BAD_PIO = -1189,
-
- /** Cannot allocate ASID. */
- GXIO_TRIO_ERR_NO_ASID = -1190,
-
- /** Invalid ASID. */
- GXIO_TRIO_ERR_BAD_ASID = -1191,
-
-
- /********************************************************/
- /* MICA Error Codes */
- /********************************************************/
-
- /** No such accelerator type. */
- GXIO_MICA_ERR_BAD_ACCEL_TYPE = -1220,
-
- /** Cannot allocate context. */
- GXIO_MICA_ERR_NO_CONTEXT = -1221,
-
- /** PKA command queue is full, can't add another command. */
- GXIO_MICA_ERR_PKA_CMD_QUEUE_FULL = -1222,
-
- /** PKA result queue is empty, can't get a result from the queue. */
- GXIO_MICA_ERR_PKA_RESULT_QUEUE_EMPTY = -1223,
-
- /********************************************************/
- /* GPIO Error Codes */
- /********************************************************/
-
- /** Pin not available. Either the physical pin does not exist, or
- * it is reserved by the hypervisor for system usage. */
- GXIO_GPIO_ERR_PIN_UNAVAILABLE = -1240,
-
- /** Pin busy. The pin exists, and is available for use via GXIO, but
- * it has been attached by some other process or driver. */
- GXIO_GPIO_ERR_PIN_BUSY = -1241,
-
- /** Cannot access unattached pin. One or more of the pins being
- * manipulated by this call are not attached to the requesting
- * context. */
- GXIO_GPIO_ERR_PIN_UNATTACHED = -1242,
-
- /** Invalid I/O mode for pin. The wiring of the pin in the system
- * is such that the I/O mode or electrical control parameters
- * requested could cause damage. */
- GXIO_GPIO_ERR_PIN_INVALID_MODE = -1243,
-
- /** Smallest iorpc error number. */
- GXIO_ERR_MIN = -1299
-};
-
-
-#endif /* !_HV_IORPC_H_ */
diff --git a/arch/tile/include/hv/netio_errors.h b/arch/tile/include/hv/netio_errors.h
deleted file mode 100644
index e1591bff61b5..000000000000
--- a/arch/tile/include/hv/netio_errors.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * Error codes returned from NetIO routines.
- */
-
-#ifndef __NETIO_ERRORS_H__
-#define __NETIO_ERRORS_H__
-
-/**
- * @addtogroup error
- *
- * @brief The error codes returned by NetIO functions.
- *
- * NetIO functions return 0 (defined as ::NETIO_NO_ERROR) on success, and
- * a negative value if an error occurs.
- *
- * In cases where a NetIO function failed due to a error reported by
- * system libraries, the error code will be the negation of the
- * system errno at the time of failure. The @ref netio_strerror()
- * function will deliver error strings for both NetIO and system error
- * codes.
- *
- * @{
- */
-
-/** The set of all NetIO errors. */
-typedef enum
-{
- /** Operation successfully completed. */
- NETIO_NO_ERROR = 0,
-
- /** A packet was successfully retrieved from an input queue. */
- NETIO_PKT = 0,
-
- /** Largest NetIO error number. */
- NETIO_ERR_MAX = -701,
-
- /** The tile is not registered with the IPP. */
- NETIO_NOT_REGISTERED = -701,
-
- /** No packet was available to retrieve from the input queue. */
- NETIO_NOPKT = -702,
-
- /** The requested function is not implemented. */
- NETIO_NOT_IMPLEMENTED = -703,
-
- /** On a registration operation, the target queue already has the maximum
- * number of tiles registered for it, and no more may be added. On a
- * packet send operation, the output queue is full and nothing more can
- * be queued until some of the queued packets are actually transmitted. */
- NETIO_QUEUE_FULL = -704,
-
- /** The calling process or thread is not bound to exactly one CPU. */
- NETIO_BAD_AFFINITY = -705,
-
- /** Cannot allocate memory on requested controllers. */
- NETIO_CANNOT_HOME = -706,
-
- /** On a registration operation, the IPP specified is not configured
- * to support the options requested; for instance, the application
- * wants a specific type of tagged headers which the configured IPP
- * doesn't support. Or, the supplied configuration information is
- * not self-consistent, or is out of range; for instance, specifying
- * both NETIO_RECV and NETIO_NO_RECV, or asking for more than
- * NETIO_MAX_SEND_BUFFERS to be preallocated. On a VLAN or bucket
- * configure operation, the number of items, or the base item, was
- * out of range.
- */
- NETIO_BAD_CONFIG = -707,
-
- /** Too many tiles have registered to transmit packets. */
- NETIO_TOOMANY_XMIT = -708,
-
- /** Packet transmission was attempted on a queue which was registered
- with transmit disabled. */
- NETIO_UNREG_XMIT = -709,
-
- /** This tile is already registered with the IPP. */
- NETIO_ALREADY_REGISTERED = -710,
-
- /** The Ethernet link is down. The application should try again later. */
- NETIO_LINK_DOWN = -711,
-
- /** An invalid memory buffer has been specified. This may be an unmapped
- * virtual address, or one which does not meet alignment requirements.
- * For netio_input_register(), this error may be returned when multiple
- * processes specify different memory regions to be used for NetIO
- * buffers. That can happen if these processes specify explicit memory
- * regions with the ::NETIO_FIXED_BUFFER_VA flag, or if tmc_cmem_init()
- * has not been called by a common ancestor of the processes.
- */
- NETIO_FAULT = -712,
-
- /** Cannot combine user-managed shared memory and cache coherence. */
- NETIO_BAD_CACHE_CONFIG = -713,
-
- /** Smallest NetIO error number. */
- NETIO_ERR_MIN = -713,
-
-#ifndef __DOXYGEN__
- /** Used internally to mean that no response is needed; never returned to
- * an application. */
- NETIO_NO_RESPONSE = 1
-#endif
-} netio_error_t;
-
-/** @} */
-
-#endif /* __NETIO_ERRORS_H__ */
diff --git a/arch/tile/include/hv/netio_intf.h b/arch/tile/include/hv/netio_intf.h
deleted file mode 100644
index 8d20972aba2c..000000000000
--- a/arch/tile/include/hv/netio_intf.h
+++ /dev/null
@@ -1,2975 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * NetIO interface structures and macros.
- */
-
-#ifndef __NETIO_INTF_H__
-#define __NETIO_INTF_H__
-
-#include <hv/netio_errors.h>
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-#if !defined(__HV__) && !defined(__BOGUX__) && !defined(__KERNEL__)
-#include <assert.h>
-#define netio_assert assert /**< Enable assertions from macros */
-#else
-#define netio_assert(...) ((void)(0)) /**< Disable assertions from macros */
-#endif
-
-/*
- * If none of these symbols are defined, we're building libnetio in an
- * environment where we have pthreads, so we'll enable locking.
- */
-#if !defined(__HV__) && !defined(__BOGUX__) && !defined(__KERNEL__) && \
- !defined(__NEWLIB__)
-#define _NETIO_PTHREAD /**< Include a mutex in netio_queue_t below */
-
-/*
- * If NETIO_UNLOCKED is defined, we don't do use per-cpu locks on
- * per-packet NetIO operations. We still do pthread locking on things
- * like netio_input_register, though. This is used for building
- * libnetio_unlocked.
- */
-#ifndef NETIO_UNLOCKED
-
-/* Avoid PLT overhead by using our own inlined per-cpu lock. */
-#include <sched.h>
-typedef int _netio_percpu_mutex_t;
-
-static __inline int
-_netio_percpu_mutex_init(_netio_percpu_mutex_t* lock)
-{
- *lock = 0;
- return 0;
-}
-
-static __inline int
-_netio_percpu_mutex_lock(_netio_percpu_mutex_t* lock)
-{
- while (__builtin_expect(__insn_tns(lock), 0))
- sched_yield();
- return 0;
-}
-
-static __inline int
-_netio_percpu_mutex_unlock(_netio_percpu_mutex_t* lock)
-{
- *lock = 0;
- return 0;
-}
-
-#else /* NETIO_UNLOCKED */
-
-/* Don't do any locking for per-packet NetIO operations. */
-typedef int _netio_percpu_mutex_t;
-#define _netio_percpu_mutex_init(L)
-#define _netio_percpu_mutex_lock(L)
-#define _netio_percpu_mutex_unlock(L)
-
-#endif /* NETIO_UNLOCKED */
-#endif /* !__HV__, !__BOGUX, !__KERNEL__, !__NEWLIB__ */
-
-/** How many tiles can register for a given queue.
- * @ingroup setup */
-#define NETIO_MAX_TILES_PER_QUEUE 64
-
-
-/** Largest permissible queue identifier.
- * @ingroup setup */
-#define NETIO_MAX_QUEUE_ID 255
-
-
-#ifndef __DOXYGEN__
-
-/* Metadata packet checksum/ethertype flags. */
-
-/** The L4 checksum has not been calculated. */
-#define _NETIO_PKT_NO_L4_CSUM_SHIFT 0
-#define _NETIO_PKT_NO_L4_CSUM_RMASK 1
-#define _NETIO_PKT_NO_L4_CSUM_MASK \
- (_NETIO_PKT_NO_L4_CSUM_RMASK << _NETIO_PKT_NO_L4_CSUM_SHIFT)
-
-/** The L3 checksum has not been calculated. */
-#define _NETIO_PKT_NO_L3_CSUM_SHIFT 1
-#define _NETIO_PKT_NO_L3_CSUM_RMASK 1
-#define _NETIO_PKT_NO_L3_CSUM_MASK \
- (_NETIO_PKT_NO_L3_CSUM_RMASK << _NETIO_PKT_NO_L3_CSUM_SHIFT)
-
-/** The L3 checksum is incorrect (or perhaps has not been calculated). */
-#define _NETIO_PKT_BAD_L3_CSUM_SHIFT 2
-#define _NETIO_PKT_BAD_L3_CSUM_RMASK 1
-#define _NETIO_PKT_BAD_L3_CSUM_MASK \
- (_NETIO_PKT_BAD_L3_CSUM_RMASK << _NETIO_PKT_BAD_L3_CSUM_SHIFT)
-
-/** The Ethernet packet type is unrecognized. */
-#define _NETIO_PKT_TYPE_UNRECOGNIZED_SHIFT 3
-#define _NETIO_PKT_TYPE_UNRECOGNIZED_RMASK 1
-#define _NETIO_PKT_TYPE_UNRECOGNIZED_MASK \
- (_NETIO_PKT_TYPE_UNRECOGNIZED_RMASK << \
- _NETIO_PKT_TYPE_UNRECOGNIZED_SHIFT)
-
-/* Metadata packet type flags. */
-
-/** Where the packet type bits are; this field is the index into
- * _netio_pkt_info. */
-#define _NETIO_PKT_TYPE_SHIFT 4
-#define _NETIO_PKT_TYPE_RMASK 0x3F
-
-/** How many VLAN tags the packet has, and, if we have two, which one we
- * actually grouped on. A VLAN within a proprietary (Marvell or Broadcom)
- * tag is counted here. */
-#define _NETIO_PKT_VLAN_SHIFT 4
-#define _NETIO_PKT_VLAN_RMASK 0x3
-#define _NETIO_PKT_VLAN_MASK \
- (_NETIO_PKT_VLAN_RMASK << _NETIO_PKT_VLAN_SHIFT)
-#define _NETIO_PKT_VLAN_NONE 0 /* No VLAN tag. */
-#define _NETIO_PKT_VLAN_ONE 1 /* One VLAN tag. */
-#define _NETIO_PKT_VLAN_TWO_OUTER 2 /* Two VLAN tags, outer one used. */
-#define _NETIO_PKT_VLAN_TWO_INNER 3 /* Two VLAN tags, inner one used. */
-
-/** Which proprietary tags the packet has. */
-#define _NETIO_PKT_TAG_SHIFT 6
-#define _NETIO_PKT_TAG_RMASK 0x3
-#define _NETIO_PKT_TAG_MASK \
- (_NETIO_PKT_TAG_RMASK << _NETIO_PKT_TAG_SHIFT)
-#define _NETIO_PKT_TAG_NONE 0 /* No proprietary tags. */
-#define _NETIO_PKT_TAG_MRVL 1 /* Marvell HyperG.Stack tags. */
-#define _NETIO_PKT_TAG_MRVL_EXT 2 /* HyperG.Stack extended tags. */
-#define _NETIO_PKT_TAG_BRCM 3 /* Broadcom HiGig tags. */
-
-/** Whether a packet has an LLC + SNAP header. */
-#define _NETIO_PKT_SNAP_SHIFT 8
-#define _NETIO_PKT_SNAP_RMASK 0x1
-#define _NETIO_PKT_SNAP_MASK \
- (_NETIO_PKT_SNAP_RMASK << _NETIO_PKT_SNAP_SHIFT)
-
-/* NOTE: Bits 9 and 10 are unused. */
-
-/** Length of any custom data before the L2 header, in words. */
-#define _NETIO_PKT_CUSTOM_LEN_SHIFT 11
-#define _NETIO_PKT_CUSTOM_LEN_RMASK 0x1F
-#define _NETIO_PKT_CUSTOM_LEN_MASK \
- (_NETIO_PKT_CUSTOM_LEN_RMASK << _NETIO_PKT_CUSTOM_LEN_SHIFT)
-
-/** The L4 checksum is incorrect (or perhaps has not been calculated). */
-#define _NETIO_PKT_BAD_L4_CSUM_SHIFT 16
-#define _NETIO_PKT_BAD_L4_CSUM_RMASK 0x1
-#define _NETIO_PKT_BAD_L4_CSUM_MASK \
- (_NETIO_PKT_BAD_L4_CSUM_RMASK << _NETIO_PKT_BAD_L4_CSUM_SHIFT)
-
-/** Length of the L2 header, in words. */
-#define _NETIO_PKT_L2_LEN_SHIFT 17
-#define _NETIO_PKT_L2_LEN_RMASK 0x1F
-#define _NETIO_PKT_L2_LEN_MASK \
- (_NETIO_PKT_L2_LEN_RMASK << _NETIO_PKT_L2_LEN_SHIFT)
-
-
-/* Flags in minimal packet metadata. */
-
-/** We need an eDMA checksum on this packet. */
-#define _NETIO_PKT_NEED_EDMA_CSUM_SHIFT 0
-#define _NETIO_PKT_NEED_EDMA_CSUM_RMASK 1
-#define _NETIO_PKT_NEED_EDMA_CSUM_MASK \
- (_NETIO_PKT_NEED_EDMA_CSUM_RMASK << _NETIO_PKT_NEED_EDMA_CSUM_SHIFT)
-
-/* Data within the packet information table. */
-
-/* Note that, for efficiency, code which uses these fields assumes that none
- * of the shift values below are zero. See uses below for an explanation. */
-
-/** Offset within the L2 header of the innermost ethertype (in halfwords). */
-#define _NETIO_PKT_INFO_ETYPE_SHIFT 6
-#define _NETIO_PKT_INFO_ETYPE_RMASK 0x1F
-
-/** Offset within the L2 header of the VLAN tag (in halfwords). */
-#define _NETIO_PKT_INFO_VLAN_SHIFT 11
-#define _NETIO_PKT_INFO_VLAN_RMASK 0x1F
-
-#endif
-
-
-/** The size of a memory buffer representing a small packet.
- * @ingroup egress */
-#define SMALL_PACKET_SIZE 256
-
-/** The size of a memory buffer representing a large packet.
- * @ingroup egress */
-#define LARGE_PACKET_SIZE 2048
-
-/** The size of a memory buffer representing a jumbo packet.
- * @ingroup egress */
-#define JUMBO_PACKET_SIZE (12 * 1024)
-
-
-/* Common ethertypes.
- * @ingroup ingress */
-/** @{ */
-/** The ethertype of IPv4. */
-#define ETHERTYPE_IPv4 (0x0800)
-/** The ethertype of ARP. */
-#define ETHERTYPE_ARP (0x0806)
-/** The ethertype of VLANs. */
-#define ETHERTYPE_VLAN (0x8100)
-/** The ethertype of a Q-in-Q header. */
-#define ETHERTYPE_Q_IN_Q (0x9100)
-/** The ethertype of IPv6. */
-#define ETHERTYPE_IPv6 (0x86DD)
-/** The ethertype of MPLS. */
-#define ETHERTYPE_MPLS (0x8847)
-/** @} */
-
-
-/** The possible return values of NETIO_PKT_STATUS.
- * @ingroup ingress
- */
-typedef enum
-{
- /** No problems were detected with this packet. */
- NETIO_PKT_STATUS_OK,
- /** The packet is undersized; this is expected behavior if the packet's
- * ethertype is unrecognized, but otherwise the packet is likely corrupt. */
- NETIO_PKT_STATUS_UNDERSIZE,
- /** The packet is oversized and some trailing bytes have been discarded.
- This is expected behavior for short packets, since it's impossible to
- precisely determine the amount of padding which may have been added to
- them to make them meet the minimum Ethernet packet size. */
- NETIO_PKT_STATUS_OVERSIZE,
- /** The packet was judged to be corrupt by hardware (for instance, it had
- a bad CRC, or part of it was discarded due to lack of buffer space in
- the I/O shim) and should be discarded. */
- NETIO_PKT_STATUS_BAD
-} netio_pkt_status_t;
-
-
-/** Log2 of how many buckets we have. */
-#define NETIO_LOG2_NUM_BUCKETS (10)
-
-/** How many buckets we have.
- * @ingroup ingress */
-#define NETIO_NUM_BUCKETS (1 << NETIO_LOG2_NUM_BUCKETS)
-
-
-/**
- * @brief A group-to-bucket identifier.
- *
- * @ingroup setup
- *
- * This tells us what to do with a given group.
- */
-typedef union {
- /** The header broken down into bits. */
- struct {
- /** Whether we should balance on L4, if available */
- unsigned int __balance_on_l4:1;
- /** Whether we should balance on L3, if available */
- unsigned int __balance_on_l3:1;
- /** Whether we should balance on L2, if available */
- unsigned int __balance_on_l2:1;
- /** Reserved for future use */
- unsigned int __reserved:1;
- /** The base bucket to use to send traffic */
- unsigned int __bucket_base:NETIO_LOG2_NUM_BUCKETS;
- /** The mask to apply to the balancing value. This must be one less
- * than a power of two, e.g. 0x3 or 0xFF.
- */
- unsigned int __bucket_mask:NETIO_LOG2_NUM_BUCKETS;
- /** Pad to 32 bits */
- unsigned int __padding:(32 - 4 - 2 * NETIO_LOG2_NUM_BUCKETS);
- } bits;
- /** To send out the IDN. */
- unsigned int word;
-}
-netio_group_t;
-
-
-/**
- * @brief A VLAN-to-bucket identifier.
- *
- * @ingroup setup
- *
- * This tells us what to do with a given VLAN.
- */
-typedef netio_group_t netio_vlan_t;
-
-
-/**
- * A bucket-to-queue mapping.
- * @ingroup setup
- */
-typedef unsigned char netio_bucket_t;
-
-
-/**
- * A packet size can always fit in a netio_size_t.
- * @ingroup setup
- */
-typedef unsigned int netio_size_t;
-
-
-/**
- * @brief Ethernet standard (ingress) packet metadata.
- *
- * @ingroup ingress
- *
- * This is additional data associated with each packet.
- * This structure is opaque and accessed through the @ref ingress.
- *
- * Also, the buffer population operation currently assumes that standard
- * metadata is at least as large as minimal metadata, and will need to be
- * modified if that is no longer the case.
- */
-typedef struct
-{
-#ifdef __DOXYGEN__
- /** This structure is opaque. */
- unsigned char opaque[24];
-#else
- /** The overall ordinal of the packet */
- unsigned int __packet_ordinal;
- /** The ordinal of the packet within the group */
- unsigned int __group_ordinal;
- /** The best flow hash IPP could compute. */
- unsigned int __flow_hash;
- /** Flags pertaining to checksum calculation, packet type, etc. */
- unsigned int __flags;
- /** The first word of "user data". */
- unsigned int __user_data_0;
- /** The second word of "user data". */
- unsigned int __user_data_1;
-#endif
-}
-netio_pkt_metadata_t;
-
-
-/** To ensure that the L3 header is aligned mod 4, the L2 header should be
- * aligned mod 4 plus 2, since every supported L2 header is 4n + 2 bytes
- * long. The standard way to do this is to simply add 2 bytes of padding
- * before the L2 header.
- */
-#define NETIO_PACKET_PADDING 2
-
-
-
-/**
- * @brief Ethernet minimal (egress) packet metadata.
- *
- * @ingroup egress
- *
- * This structure represents information about packets which have
- * been processed by @ref netio_populate_buffer() or
- * @ref netio_populate_prepend_buffer(). This structure is opaque
- * and accessed through the @ref egress.
- *
- * @internal This structure is actually copied into the memory used by
- * standard metadata, which is assumed to be large enough.
- */
-typedef struct
-{
-#ifdef __DOXYGEN__
- /** This structure is opaque. */
- unsigned char opaque[14];
-#else
- /** The offset of the L2 header from the start of the packet data. */
- unsigned short l2_offset;
- /** The offset of the L3 header from the start of the packet data. */
- unsigned short l3_offset;
- /** Where to write the checksum. */
- unsigned char csum_location;
- /** Where to start checksumming from. */
- unsigned char csum_start;
- /** Flags pertaining to checksum calculation etc. */
- unsigned short flags;
- /** The L2 length of the packet. */
- unsigned short l2_length;
- /** The checksum with which to seed the checksum generator. */
- unsigned short csum_seed;
- /** How much to checksum. */
- unsigned short csum_length;
-#endif
-}
-netio_pkt_minimal_metadata_t;
-
-
-#ifndef __DOXYGEN__
-
-/**
- * @brief An I/O notification header.
- *
- * This is the first word of data received from an I/O shim in a notification
- * packet. It contains framing and status information.
- */
-typedef union
-{
- unsigned int word; /**< The whole word. */
- /** The various fields. */
- struct
- {
- unsigned int __channel:7; /**< Resource channel. */
- unsigned int __type:4; /**< Type. */
- unsigned int __ack:1; /**< Whether an acknowledgement is needed. */
- unsigned int __reserved:1; /**< Reserved. */
- unsigned int __protocol:1; /**< A protocol-specific word is added. */
- unsigned int __status:2; /**< Status of the transfer. */
- unsigned int __framing:2; /**< Framing of the transfer. */
- unsigned int __transfer_size:14; /**< Transfer size in bytes (total). */
- } bits;
-}
-__netio_pkt_notif_t;
-
-
-/**
- * Returns the base address of the packet.
- */
-#define _NETIO_PKT_HANDLE_BASE(p) \
- ((unsigned char*)((p).word & 0xFFFFFFC0))
-
-/**
- * Returns the base address of the packet.
- */
-#define _NETIO_PKT_BASE(p) \
- _NETIO_PKT_HANDLE_BASE(p->__packet)
-
-/**
- * @brief An I/O notification packet (second word)
- *
- * This is the second word of data received from an I/O shim in a notification
- * packet. This is the virtual address of the packet buffer, plus some flag
- * bits. (The virtual address of the packet is always 256-byte aligned so we
- * have room for 8 bits' worth of flags in the low 8 bits.)
- *
- * @internal
- * NOTE: The low two bits must contain "__queue", so the "packet size"
- * (SIZE_SMALL, SIZE_LARGE, or SIZE_JUMBO) can be determined quickly.
- *
- * If __addr or __offset are moved, _NETIO_PKT_BASE
- * (defined right below this) must be changed.
- */
-typedef union
-{
- unsigned int word; /**< The whole word. */
- /** The various fields. */
- struct
- {
- /** Which queue the packet will be returned to once it is sent back to
- the IPP. This is one of the SIZE_xxx values. */
- unsigned int __queue:2;
-
- /** The IPP handle of the sending IPP. */
- unsigned int __ipp_handle:2;
-
- /** Reserved for future use. */
- unsigned int __reserved:1;
-
- /** If 1, this packet has minimal (egress) metadata; otherwise, it
- has standard (ingress) metadata. */
- unsigned int __minimal:1;
-
- /** Offset of the metadata within the packet. This value is multiplied
- * by 64 and added to the base packet address to get the metadata
- * address. Note that this field is aligned within the word such that
- * you can easily extract the metadata address with a 26-bit mask. */
- unsigned int __offset:2;
-
- /** The top 24 bits of the packet's virtual address. */
- unsigned int __addr:24;
- } bits;
-}
-__netio_pkt_handle_t;
-
-#endif /* !__DOXYGEN__ */
-
-
-/**
- * @brief A handle for an I/O packet's storage.
- * @ingroup ingress
- *
- * netio_pkt_handle_t encodes the concept of a ::netio_pkt_t with its
- * packet metadata removed. It is a much smaller type that exists to
- * facilitate applications where the full ::netio_pkt_t type is too
- * large, such as those that cache enormous numbers of packets or wish
- * to transmit packet descriptors over the UDN.
- *
- * Because there is no metadata, most ::netio_pkt_t operations cannot be
- * performed on a netio_pkt_handle_t. It supports only
- * netio_free_handle() (to free the buffer) and
- * NETIO_PKT_CUSTOM_DATA_H() (to access a pointer to its contents).
- * The application must acquire any additional metadata it wants from the
- * original ::netio_pkt_t and record it separately.
- *
- * A netio_pkt_handle_t can be extracted from a ::netio_pkt_t by calling
- * NETIO_PKT_HANDLE(). An invalid handle (analogous to NULL) can be
- * created by assigning the value ::NETIO_PKT_HANDLE_NONE. A handle can
- * be tested for validity with NETIO_PKT_HANDLE_IS_VALID().
- */
-typedef struct
-{
- unsigned int word; /**< Opaque bits. */
-} netio_pkt_handle_t;
-
-/**
- * @brief A packet descriptor.
- *
- * @ingroup ingress
- * @ingroup egress
- *
- * This data structure represents a packet. The structure is manipulated
- * through the @ref ingress and the @ref egress.
- *
- * While the contents of a netio_pkt_t are opaque, the structure itself is
- * portable. This means that it may be shared between all tiles which have
- * done a netio_input_register() call for the interface on which the pkt_t
- * was initially received (via netio_get_packet()) or retrieved (via
- * netio_get_buffer()). The contents of a netio_pkt_t can be transmitted to
- * another tile via shared memory, or via a UDN message, or by other means.
- * The destination tile may then use the pkt_t as if it had originally been
- * received locally; it may read or write the packet's data, read its
- * metadata, free the packet, send the packet, transfer the netio_pkt_t to
- * yet another tile, and so forth.
- *
- * Once a netio_pkt_t has been transferred to a second tile, the first tile
- * should not reference the original copy; in particular, if more than one
- * tile frees or sends the same netio_pkt_t, the IPP's packet free lists will
- * become corrupted. Note also that each tile which reads or modifies
- * packet data must obey the memory coherency rules outlined in @ref input.
- */
-typedef struct
-{
-#ifdef __DOXYGEN__
- /** This structure is opaque. */
- unsigned char opaque[32];
-#else
- /** For an ingress packet (one with standard metadata), this is the
- * notification header we got from the I/O shim. For an egress packet
- * (one with minimal metadata), this word is zero if the packet has not
- * been populated, and nonzero if it has. */
- __netio_pkt_notif_t __notif_header;
-
- /** Virtual address of the packet buffer, plus state flags. */
- __netio_pkt_handle_t __packet;
-
- /** Metadata associated with the packet. */
- netio_pkt_metadata_t __metadata;
-#endif
-}
-netio_pkt_t;
-
-
-#ifndef __DOXYGEN__
-
-#define __NETIO_PKT_NOTIF_HEADER(pkt) ((pkt)->__notif_header)
-#define __NETIO_PKT_IPP_HANDLE(pkt) ((pkt)->__packet.bits.__ipp_handle)
-#define __NETIO_PKT_QUEUE(pkt) ((pkt)->__packet.bits.__queue)
-#define __NETIO_PKT_NOTIF_HEADER_M(mda, pkt) ((pkt)->__notif_header)
-#define __NETIO_PKT_IPP_HANDLE_M(mda, pkt) ((pkt)->__packet.bits.__ipp_handle)
-#define __NETIO_PKT_MINIMAL(pkt) ((pkt)->__packet.bits.__minimal)
-#define __NETIO_PKT_QUEUE_M(mda, pkt) ((pkt)->__packet.bits.__queue)
-#define __NETIO_PKT_FLAGS_M(mda, pkt) ((mda)->__flags)
-
-/* Packet information table, used by the attribute access functions below. */
-extern const uint16_t _netio_pkt_info[];
-
-#endif /* __DOXYGEN__ */
-
-
-#ifndef __DOXYGEN__
-/* These macros are deprecated and will disappear in a future MDE release. */
-#define NETIO_PKT_GOOD_CHECKSUM(pkt) \
- NETIO_PKT_L4_CSUM_CORRECT(pkt)
-#define NETIO_PKT_GOOD_CHECKSUM_M(mda, pkt) \
- NETIO_PKT_L4_CSUM_CORRECT_M(mda, pkt)
-#endif /* __DOXYGEN__ */
-
-
-/* Packet attribute access functions. */
-
-/** Return a pointer to the metadata for a packet.
- * @ingroup ingress
- *
- * Calling this function once and passing the result to other retrieval
- * functions with a "_M" suffix usually improves performance. This
- * function must be called on an 'ingress' packet (i.e. one retrieved
- * by @ref netio_get_packet(), on which @ref netio_populate_buffer() or
- * @ref netio_populate_prepend_buffer have not been called). Use of this
- * function on an 'egress' packet will cause an assertion failure.
- *
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to the packet's standard metadata.
- */
-static __inline netio_pkt_metadata_t*
-NETIO_PKT_METADATA(netio_pkt_t* pkt)
-{
- netio_assert(!pkt->__packet.bits.__minimal);
- return &pkt->__metadata;
-}
-
-
-/** Return a pointer to the minimal metadata for a packet.
- * @ingroup egress
- *
- * Calling this function once and passing the result to other retrieval
- * functions with a "_MM" suffix usually improves performance. This
- * function must be called on an 'egress' packet (i.e. one on which
- * @ref netio_populate_buffer() or @ref netio_populate_prepend_buffer()
- * have been called, or one retrieved by @ref netio_get_buffer()). Use of
- * this function on an 'ingress' packet will cause an assertion failure.
- *
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to the packet's standard metadata.
- */
-static __inline netio_pkt_minimal_metadata_t*
-NETIO_PKT_MINIMAL_METADATA(netio_pkt_t* pkt)
-{
- netio_assert(pkt->__packet.bits.__minimal);
- return (netio_pkt_minimal_metadata_t*) &pkt->__metadata;
-}
-
-
-/** Determine whether a packet has 'minimal' metadata.
- * @ingroup pktfuncs
- *
- * This function will return nonzero if the packet is an 'egress'
- * packet (i.e. one on which @ref netio_populate_buffer() or
- * @ref netio_populate_prepend_buffer() have been called, or one
- * retrieved by @ref netio_get_buffer()), and zero if the packet
- * is an 'ingress' packet (i.e. one retrieved by @ref netio_get_packet(),
- * which has not been converted into an 'egress' packet).
- *
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the packet has minimal metadata.
- */
-static __inline unsigned int
-NETIO_PKT_IS_MINIMAL(netio_pkt_t* pkt)
-{
- return pkt->__packet.bits.__minimal;
-}
-
-
-/** Return a handle for a packet's storage.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return A handle for the packet's storage.
- */
-static __inline netio_pkt_handle_t
-NETIO_PKT_HANDLE(netio_pkt_t* pkt)
-{
- netio_pkt_handle_t h;
- h.word = pkt->__packet.word;
- return h;
-}
-
-
-/** A special reserved value indicating the absence of a packet handle.
- *
- * @ingroup pktfuncs
- */
-#define NETIO_PKT_HANDLE_NONE ((netio_pkt_handle_t) { 0 })
-
-
-/** Test whether a packet handle is valid.
- *
- * Applications may wish to use the reserved value NETIO_PKT_HANDLE_NONE
- * to indicate no packet at all. This function tests to see if a packet
- * handle is a real handle, not this special reserved value.
- *
- * @ingroup pktfuncs
- *
- * @param[in] handle Handle on which to operate.
- * @return One if the packet handle is valid, else zero.
- */
-static __inline unsigned int
-NETIO_PKT_HANDLE_IS_VALID(netio_pkt_handle_t handle)
-{
- return handle.word != 0;
-}
-
-
-
-/** Return a pointer to the start of the packet's custom header.
- * A custom header may or may not be present, depending upon the IPP; its
- * contents and alignment are also IPP-dependent. Currently, none of the
- * standard IPPs supplied by Tilera produce a custom header. If present,
- * the custom header precedes the L2 header in the packet buffer.
- * @ingroup ingress
- *
- * @param[in] handle Handle on which to operate.
- * @return A pointer to start of the packet.
- */
-static __inline unsigned char*
-NETIO_PKT_CUSTOM_DATA_H(netio_pkt_handle_t handle)
-{
- return _NETIO_PKT_HANDLE_BASE(handle) + NETIO_PACKET_PADDING;
-}
-
-
-/** Return the length of the packet's custom header.
- * A custom header may or may not be present, depending upon the IPP; its
- * contents and alignment are also IPP-dependent. Currently, none of the
- * standard IPPs supplied by Tilera produce a custom header. If present,
- * the custom header precedes the L2 header in the packet buffer.
- *
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet's custom header, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_CUSTOM_HEADER_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- /*
- * Note that we effectively need to extract a quantity from the flags word
- * which is measured in words, and then turn it into bytes by shifting
- * it left by 2. We do this all at once by just shifting right two less
- * bits, and shifting the mask up two bits.
- */
- return ((mda->__flags >> (_NETIO_PKT_CUSTOM_LEN_SHIFT - 2)) &
- (_NETIO_PKT_CUSTOM_LEN_RMASK << 2));
-}
-
-
-/** Return the length of the packet, starting with the custom header.
- * A custom header may or may not be present, depending upon the IPP; its
- * contents and alignment are also IPP-dependent. Currently, none of the
- * standard IPPs supplied by Tilera produce a custom header. If present,
- * the custom header precedes the L2 header in the packet buffer.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_CUSTOM_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return (__NETIO_PKT_NOTIF_HEADER(pkt).bits.__transfer_size -
- NETIO_PACKET_PADDING);
-}
-
-
-/** Return a pointer to the start of the packet's custom header.
- * A custom header may or may not be present, depending upon the IPP; its
- * contents and alignment are also IPP-dependent. Currently, none of the
- * standard IPPs supplied by Tilera produce a custom header. If present,
- * the custom header precedes the L2 header in the packet buffer.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to start of the packet.
- */
-static __inline unsigned char*
-NETIO_PKT_CUSTOM_DATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return NETIO_PKT_CUSTOM_DATA_H(NETIO_PKT_HANDLE(pkt));
-}
-
-
-/** Return the length of the packet's L2 (Ethernet plus VLAN or SNAP) header.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet's L2 header, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L2_HEADER_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- /*
- * Note that we effectively need to extract a quantity from the flags word
- * which is measured in words, and then turn it into bytes by shifting
- * it left by 2. We do this all at once by just shifting right two less
- * bits, and shifting the mask up two bits. We then add two bytes.
- */
- return ((mda->__flags >> (_NETIO_PKT_L2_LEN_SHIFT - 2)) &
- (_NETIO_PKT_L2_LEN_RMASK << 2)) + 2;
-}
-
-
-/** Return the length of the packet, starting with the L2 (Ethernet) header.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L2_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return (NETIO_PKT_CUSTOM_LENGTH_M(mda, pkt) -
- NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda,pkt));
-}
-
-
-/** Return a pointer to the start of the packet's L2 (Ethernet) header.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to start of the packet.
- */
-static __inline unsigned char*
-NETIO_PKT_L2_DATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return (NETIO_PKT_CUSTOM_DATA_M(mda, pkt) +
- NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda, pkt));
-}
-
-
-/** Retrieve the length of the packet, starting with the L3 (generally,
- * the IP) header.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Length of the packet's L3 header and data, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L3_LENGTH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return (NETIO_PKT_L2_LENGTH_M(mda, pkt) -
- NETIO_PKT_L2_HEADER_LENGTH_M(mda,pkt));
-}
-
-
-/** Return a pointer to the packet's L3 (generally, the IP) header.
- * @ingroup ingress
- *
- * Note that we guarantee word alignment of the L3 header.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to the packet's L3 header.
- */
-static __inline unsigned char*
-NETIO_PKT_L3_DATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return (NETIO_PKT_L2_DATA_M(mda, pkt) +
- NETIO_PKT_L2_HEADER_LENGTH_M(mda, pkt));
-}
-
-
-/** Return the ordinal of the packet.
- * @ingroup ingress
- *
- * Each packet is given an ordinal number when it is delivered by the IPP.
- * In the medium term, the ordinal is unique and monotonically increasing,
- * being incremented by 1 for each packet; the ordinal of the first packet
- * delivered after the IPP starts is zero. (Since the ordinal is of finite
- * size, given enough input packets, it will eventually wrap around to zero;
- * in the long term, therefore, ordinals are not unique.) The ordinals
- * handed out by different IPPs are not disjoint, so two packets from
- * different IPPs may have identical ordinals. Packets dropped by the
- * IPP or by the I/O shim are not assigned ordinals.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's per-IPP packet ordinal.
- */
-static __inline unsigned int
-NETIO_PKT_ORDINAL_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return mda->__packet_ordinal;
-}
-
-
-/** Return the per-group ordinal of the packet.
- * @ingroup ingress
- *
- * Each packet is given a per-group ordinal number when it is
- * delivered by the IPP. By default, the group is the packet's VLAN,
- * although IPP can be recompiled to use different values. In
- * the medium term, the ordinal is unique and monotonically
- * increasing, being incremented by 1 for each packet; the ordinal of
- * the first packet distributed to a particular group is zero.
- * (Since the ordinal is of finite size, given enough input packets,
- * it will eventually wrap around to zero; in the long term,
- * therefore, ordinals are not unique.) The ordinals handed out by
- * different IPPs are not disjoint, so two packets from different IPPs
- * may have identical ordinals; similarly, packets distributed to
- * different groups may have identical ordinals. Packets dropped by
- * the IPP or by the I/O shim are not assigned ordinals.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's per-IPP, per-group ordinal.
- */
-static __inline unsigned int
-NETIO_PKT_GROUP_ORDINAL_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return mda->__group_ordinal;
-}
-
-
-/** Return the VLAN ID assigned to the packet.
- * @ingroup ingress
- *
- * This value is usually contained within the packet header.
- *
- * This value will be zero if the packet does not have a VLAN tag, or if
- * this value was not extracted from the packet.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's VLAN ID.
- */
-static __inline unsigned short
-NETIO_PKT_VLAN_ID_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- int vl = (mda->__flags >> _NETIO_PKT_VLAN_SHIFT) & _NETIO_PKT_VLAN_RMASK;
- unsigned short* pkt_p;
- int index;
- unsigned short val;
-
- if (vl == _NETIO_PKT_VLAN_NONE)
- return 0;
-
- pkt_p = (unsigned short*) NETIO_PKT_L2_DATA_M(mda, pkt);
- index = (mda->__flags >> _NETIO_PKT_TYPE_SHIFT) & _NETIO_PKT_TYPE_RMASK;
-
- val = pkt_p[(_netio_pkt_info[index] >> _NETIO_PKT_INFO_VLAN_SHIFT) &
- _NETIO_PKT_INFO_VLAN_RMASK];
-
-#ifdef __TILECC__
- return (__insn_bytex(val) >> 16) & 0xFFF;
-#else
- return (__builtin_bswap32(val) >> 16) & 0xFFF;
-#endif
-}
-
-
-/** Return the ethertype of the packet.
- * @ingroup ingress
- *
- * This value is usually contained within the packet header.
- *
- * This value is reliable if @ref NETIO_PKT_ETHERTYPE_RECOGNIZED_M()
- * returns true, and otherwise, may not be well defined.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's ethertype.
- */
-static __inline unsigned short
-NETIO_PKT_ETHERTYPE_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- unsigned short* pkt_p = (unsigned short*) NETIO_PKT_L2_DATA_M(mda, pkt);
- int index = (mda->__flags >> _NETIO_PKT_TYPE_SHIFT) & _NETIO_PKT_TYPE_RMASK;
-
- unsigned short val =
- pkt_p[(_netio_pkt_info[index] >> _NETIO_PKT_INFO_ETYPE_SHIFT) &
- _NETIO_PKT_INFO_ETYPE_RMASK];
-
- return __builtin_bswap32(val) >> 16;
-}
-
-
-/** Return the flow hash computed on the packet.
- * @ingroup ingress
- *
- * For TCP and UDP packets, this hash is calculated by hashing together
- * the "5-tuple" values, specifically the source IP address, destination
- * IP address, protocol type, source port and destination port.
- * The hash value is intended to be helpful for millions of distinct
- * flows.
- *
- * For IPv4 or IPv6 packets which are neither TCP nor UDP, the flow hash is
- * derived by hashing together the source and destination IP addresses.
- *
- * For MPLS-encapsulated packets, the flow hash is derived by hashing
- * the first MPLS label.
- *
- * For all other packets the flow hash is computed from the source
- * and destination Ethernet addresses.
- *
- * The hash is symmetric, meaning it produces the same value if the
- * source and destination are swapped. The only exceptions are
- * tunneling protocols 0x04 (IP in IP Encapsulation), 0x29 (Simple
- * Internet Protocol), 0x2F (General Routing Encapsulation) and 0x32
- * (Encap Security Payload), which use only the destination address
- * since the source address is not meaningful.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's 32-bit flow hash.
- */
-static __inline unsigned int
-NETIO_PKT_FLOW_HASH_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return mda->__flow_hash;
-}
-
-
-/** Return the first word of "user data" for the packet.
- *
- * The contents of the user data words depend on the IPP.
- *
- * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the first
- * word of user data contains the least significant bits of the 64-bit
- * arrival cycle count (see @c get_cycle_count_low()).
- *
- * See the <em>System Programmer's Guide</em> for details.
- *
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's first word of "user data".
- */
-static __inline unsigned int
-NETIO_PKT_USER_DATA_0_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return mda->__user_data_0;
-}
-
-
-/** Return the second word of "user data" for the packet.
- *
- * The contents of the user data words depend on the IPP.
- *
- * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the second
- * word of user data contains the most significant bits of the 64-bit
- * arrival cycle count (see @c get_cycle_count_high()).
- *
- * See the <em>System Programmer's Guide</em> for details.
- *
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's second word of "user data".
- */
-static __inline unsigned int
-NETIO_PKT_USER_DATA_1_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return mda->__user_data_1;
-}
-
-
-/** Determine whether the L4 (TCP/UDP) checksum was calculated.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the L4 checksum was calculated.
- */
-static __inline unsigned int
-NETIO_PKT_L4_CSUM_CALCULATED_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return !(mda->__flags & _NETIO_PKT_NO_L4_CSUM_MASK);
-}
-
-
-/** Determine whether the L4 (TCP/UDP) checksum was calculated and found to
- * be correct.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the checksum was calculated and is correct.
- */
-static __inline unsigned int
-NETIO_PKT_L4_CSUM_CORRECT_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return !(mda->__flags &
- (_NETIO_PKT_BAD_L4_CSUM_MASK | _NETIO_PKT_NO_L4_CSUM_MASK));
-}
-
-
-/** Determine whether the L3 (IP) checksum was calculated.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the L3 (IP) checksum was calculated.
-*/
-static __inline unsigned int
-NETIO_PKT_L3_CSUM_CALCULATED_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return !(mda->__flags & _NETIO_PKT_NO_L3_CSUM_MASK);
-}
-
-
-/** Determine whether the L3 (IP) checksum was calculated and found to be
- * correct.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the checksum was calculated and is correct.
- */
-static __inline unsigned int
-NETIO_PKT_L3_CSUM_CORRECT_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return !(mda->__flags &
- (_NETIO_PKT_BAD_L3_CSUM_MASK | _NETIO_PKT_NO_L3_CSUM_MASK));
-}
-
-
-/** Determine whether the ethertype was recognized and L3 packet data was
- * processed.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the ethertype was recognized and L3 packet data was
- * processed.
- */
-static __inline unsigned int
-NETIO_PKT_ETHERTYPE_RECOGNIZED_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return !(mda->__flags & _NETIO_PKT_TYPE_UNRECOGNIZED_MASK);
-}
-
-
-/** Retrieve the status of a packet and any errors that may have occurred
- * during ingress processing (length mismatches, CRC errors, etc.).
- * @ingroup ingress
- *
- * Note that packets for which @ref NETIO_PKT_ETHERTYPE_RECOGNIZED()
- * returns zero are always reported as underlength, as there is no a priori
- * means to determine their length. Normally, applications should use
- * @ref NETIO_PKT_BAD_M() instead of explicitly checking status with this
- * function.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The packet's status.
- */
-static __inline netio_pkt_status_t
-NETIO_PKT_STATUS_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return (netio_pkt_status_t) __NETIO_PKT_NOTIF_HEADER(pkt).bits.__status;
-}
-
-
-/** Report whether a packet is bad (i.e., was shorter than expected based on
- * its headers, or had a bad CRC).
- * @ingroup ingress
- *
- * Note that this function does not verify L3 or L4 checksums.
- *
- * @param[in] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the packet is bad and should be discarded.
- */
-static __inline unsigned int
-NETIO_PKT_BAD_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return ((NETIO_PKT_STATUS_M(mda, pkt) & 1) &&
- (NETIO_PKT_ETHERTYPE_RECOGNIZED_M(mda, pkt) ||
- NETIO_PKT_STATUS_M(mda, pkt) == NETIO_PKT_STATUS_BAD));
-}
-
-
-/** Return the length of the packet, starting with the L2 (Ethernet) header.
- * @ingroup egress
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L2_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
-{
- return mmd->l2_length;
-}
-
-
-/** Return the length of the L2 (Ethernet) header.
- * @ingroup egress
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet's L2 header, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L2_HEADER_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd,
- netio_pkt_t* pkt)
-{
- return mmd->l3_offset - mmd->l2_offset;
-}
-
-
-/** Return the length of the packet, starting with the L3 (IP) header.
- * @ingroup egress
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @return Length of the packet's L3 header and data, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L3_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
-{
- return (NETIO_PKT_L2_LENGTH_MM(mmd, pkt) -
- NETIO_PKT_L2_HEADER_LENGTH_MM(mmd, pkt));
-}
-
-
-/** Return a pointer to the packet's L3 (generally, the IP) header.
- * @ingroup egress
- *
- * Note that we guarantee word alignment of the L3 header.
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to the packet's L3 header.
- */
-static __inline unsigned char*
-NETIO_PKT_L3_DATA_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
-{
- return _NETIO_PKT_BASE(pkt) + mmd->l3_offset;
-}
-
-
-/** Return a pointer to the packet's L2 (Ethernet) header.
- * @ingroup egress
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to start of the packet.
- */
-static __inline unsigned char*
-NETIO_PKT_L2_DATA_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
-{
- return _NETIO_PKT_BASE(pkt) + mmd->l2_offset;
-}
-
-
-/** Retrieve the status of a packet and any errors that may have occurred
- * during ingress processing (length mismatches, CRC errors, etc.).
- * @ingroup ingress
- *
- * Note that packets for which @ref NETIO_PKT_ETHERTYPE_RECOGNIZED()
- * returns zero are always reported as underlength, as there is no a priori
- * means to determine their length. Normally, applications should use
- * @ref NETIO_PKT_BAD() instead of explicitly checking status with this
- * function.
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's status.
- */
-static __inline netio_pkt_status_t
-NETIO_PKT_STATUS(netio_pkt_t* pkt)
-{
- netio_assert(!pkt->__packet.bits.__minimal);
-
- return (netio_pkt_status_t) __NETIO_PKT_NOTIF_HEADER(pkt).bits.__status;
-}
-
-
-/** Report whether a packet is bad (i.e., was shorter than expected based on
- * its headers, or had a bad CRC).
- * @ingroup ingress
- *
- * Note that this function does not verify L3 or L4 checksums.
- *
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the packet is bad and should be discarded.
- */
-static __inline unsigned int
-NETIO_PKT_BAD(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_BAD_M(mda, pkt);
-}
-
-
-/** Return the length of the packet's custom header.
- * A custom header may or may not be present, depending upon the IPP; its
- * contents and alignment are also IPP-dependent. Currently, none of the
- * standard IPPs supplied by Tilera produce a custom header. If present,
- * the custom header precedes the L2 header in the packet buffer.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet's custom header, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_CUSTOM_HEADER_LENGTH(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda, pkt);
-}
-
-
-/** Return the length of the packet, starting with the custom header.
- * A custom header may or may not be present, depending upon the IPP; its
- * contents and alignment are also IPP-dependent. Currently, none of the
- * standard IPPs supplied by Tilera produce a custom header. If present,
- * the custom header precedes the L2 header in the packet buffer.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_CUSTOM_LENGTH(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_CUSTOM_LENGTH_M(mda, pkt);
-}
-
-
-/** Return a pointer to the packet's custom header.
- * A custom header may or may not be present, depending upon the IPP; its
- * contents and alignment are also IPP-dependent. Currently, none of the
- * standard IPPs supplied by Tilera produce a custom header. If present,
- * the custom header precedes the L2 header in the packet buffer.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to start of the packet.
- */
-static __inline unsigned char*
-NETIO_PKT_CUSTOM_DATA(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_CUSTOM_DATA_M(mda, pkt);
-}
-
-
-/** Return the length of the packet's L2 (Ethernet plus VLAN or SNAP) header.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet's L2 header, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L2_HEADER_LENGTH(netio_pkt_t* pkt)
-{
- if (NETIO_PKT_IS_MINIMAL(pkt))
- {
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- return NETIO_PKT_L2_HEADER_LENGTH_MM(mmd, pkt);
- }
- else
- {
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L2_HEADER_LENGTH_M(mda, pkt);
- }
-}
-
-
-/** Return the length of the packet, starting with the L2 (Ethernet) header.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return The length of the packet, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L2_LENGTH(netio_pkt_t* pkt)
-{
- if (NETIO_PKT_IS_MINIMAL(pkt))
- {
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- return NETIO_PKT_L2_LENGTH_MM(mmd, pkt);
- }
- else
- {
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L2_LENGTH_M(mda, pkt);
- }
-}
-
-
-/** Return a pointer to the packet's L2 (Ethernet) header.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to start of the packet.
- */
-static __inline unsigned char*
-NETIO_PKT_L2_DATA(netio_pkt_t* pkt)
-{
- if (NETIO_PKT_IS_MINIMAL(pkt))
- {
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- return NETIO_PKT_L2_DATA_MM(mmd, pkt);
- }
- else
- {
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L2_DATA_M(mda, pkt);
- }
-}
-
-
-/** Retrieve the length of the packet, starting with the L3 (generally, the IP)
- * header.
- * @ingroup pktfuncs
- *
- * @param[in] pkt Packet on which to operate.
- * @return Length of the packet's L3 header and data, in bytes.
- */
-static __inline netio_size_t
-NETIO_PKT_L3_LENGTH(netio_pkt_t* pkt)
-{
- if (NETIO_PKT_IS_MINIMAL(pkt))
- {
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- return NETIO_PKT_L3_LENGTH_MM(mmd, pkt);
- }
- else
- {
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L3_LENGTH_M(mda, pkt);
- }
-}
-
-
-/** Return a pointer to the packet's L3 (generally, the IP) header.
- * @ingroup pktfuncs
- *
- * Note that we guarantee word alignment of the L3 header.
- *
- * @param[in] pkt Packet on which to operate.
- * @return A pointer to the packet's L3 header.
- */
-static __inline unsigned char*
-NETIO_PKT_L3_DATA(netio_pkt_t* pkt)
-{
- if (NETIO_PKT_IS_MINIMAL(pkt))
- {
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- return NETIO_PKT_L3_DATA_MM(mmd, pkt);
- }
- else
- {
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L3_DATA_M(mda, pkt);
- }
-}
-
-
-/** Return the ordinal of the packet.
- * @ingroup ingress
- *
- * Each packet is given an ordinal number when it is delivered by the IPP.
- * In the medium term, the ordinal is unique and monotonically increasing,
- * being incremented by 1 for each packet; the ordinal of the first packet
- * delivered after the IPP starts is zero. (Since the ordinal is of finite
- * size, given enough input packets, it will eventually wrap around to zero;
- * in the long term, therefore, ordinals are not unique.) The ordinals
- * handed out by different IPPs are not disjoint, so two packets from
- * different IPPs may have identical ordinals. Packets dropped by the
- * IPP or by the I/O shim are not assigned ordinals.
- *
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's per-IPP packet ordinal.
- */
-static __inline unsigned int
-NETIO_PKT_ORDINAL(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_ORDINAL_M(mda, pkt);
-}
-
-
-/** Return the per-group ordinal of the packet.
- * @ingroup ingress
- *
- * Each packet is given a per-group ordinal number when it is
- * delivered by the IPP. By default, the group is the packet's VLAN,
- * although IPP can be recompiled to use different values. In
- * the medium term, the ordinal is unique and monotonically
- * increasing, being incremented by 1 for each packet; the ordinal of
- * the first packet distributed to a particular group is zero.
- * (Since the ordinal is of finite size, given enough input packets,
- * it will eventually wrap around to zero; in the long term,
- * therefore, ordinals are not unique.) The ordinals handed out by
- * different IPPs are not disjoint, so two packets from different IPPs
- * may have identical ordinals; similarly, packets distributed to
- * different groups may have identical ordinals. Packets dropped by
- * the IPP or by the I/O shim are not assigned ordinals.
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's per-IPP, per-group ordinal.
- */
-static __inline unsigned int
-NETIO_PKT_GROUP_ORDINAL(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_GROUP_ORDINAL_M(mda, pkt);
-}
-
-
-/** Return the VLAN ID assigned to the packet.
- * @ingroup ingress
- *
- * This is usually also contained within the packet header. If the packet
- * does not have a VLAN tag, the VLAN ID returned by this function is zero.
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's VLAN ID.
- */
-static __inline unsigned short
-NETIO_PKT_VLAN_ID(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_VLAN_ID_M(mda, pkt);
-}
-
-
-/** Return the ethertype of the packet.
- * @ingroup ingress
- *
- * This value is reliable if @ref NETIO_PKT_ETHERTYPE_RECOGNIZED()
- * returns true, and otherwise, may not be well defined.
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's ethertype.
- */
-static __inline unsigned short
-NETIO_PKT_ETHERTYPE(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_ETHERTYPE_M(mda, pkt);
-}
-
-
-/** Return the flow hash computed on the packet.
- * @ingroup ingress
- *
- * For TCP and UDP packets, this hash is calculated by hashing together
- * the "5-tuple" values, specifically the source IP address, destination
- * IP address, protocol type, source port and destination port.
- * The hash value is intended to be helpful for millions of distinct
- * flows.
- *
- * For IPv4 or IPv6 packets which are neither TCP nor UDP, the flow hash is
- * derived by hashing together the source and destination IP addresses.
- *
- * For MPLS-encapsulated packets, the flow hash is derived by hashing
- * the first MPLS label.
- *
- * For all other packets the flow hash is computed from the source
- * and destination Ethernet addresses.
- *
- * The hash is symmetric, meaning it produces the same value if the
- * source and destination are swapped. The only exceptions are
- * tunneling protocols 0x04 (IP in IP Encapsulation), 0x29 (Simple
- * Internet Protocol), 0x2F (General Routing Encapsulation) and 0x32
- * (Encap Security Payload), which use only the destination address
- * since the source address is not meaningful.
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's 32-bit flow hash.
- */
-static __inline unsigned int
-NETIO_PKT_FLOW_HASH(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_FLOW_HASH_M(mda, pkt);
-}
-
-
-/** Return the first word of "user data" for the packet.
- *
- * The contents of the user data words depend on the IPP.
- *
- * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the first
- * word of user data contains the least significant bits of the 64-bit
- * arrival cycle count (see @c get_cycle_count_low()).
- *
- * See the <em>System Programmer's Guide</em> for details.
- *
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's first word of "user data".
- */
-static __inline unsigned int
-NETIO_PKT_USER_DATA_0(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_USER_DATA_0_M(mda, pkt);
-}
-
-
-/** Return the second word of "user data" for the packet.
- *
- * The contents of the user data words depend on the IPP.
- *
- * When using the standard ipp1, ipp2, or ipp4 sub-drivers, the second
- * word of user data contains the most significant bits of the 64-bit
- * arrival cycle count (see @c get_cycle_count_high()).
- *
- * See the <em>System Programmer's Guide</em> for details.
- *
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- * @return The packet's second word of "user data".
- */
-static __inline unsigned int
-NETIO_PKT_USER_DATA_1(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_USER_DATA_1_M(mda, pkt);
-}
-
-
-/** Determine whether the L4 (TCP/UDP) checksum was calculated.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the L4 checksum was calculated.
- */
-static __inline unsigned int
-NETIO_PKT_L4_CSUM_CALCULATED(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L4_CSUM_CALCULATED_M(mda, pkt);
-}
-
-
-/** Determine whether the L4 (TCP/UDP) checksum was calculated and found to
- * be correct.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the checksum was calculated and is correct.
- */
-static __inline unsigned int
-NETIO_PKT_L4_CSUM_CORRECT(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L4_CSUM_CORRECT_M(mda, pkt);
-}
-
-
-/** Determine whether the L3 (IP) checksum was calculated.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the L3 (IP) checksum was calculated.
-*/
-static __inline unsigned int
-NETIO_PKT_L3_CSUM_CALCULATED(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L3_CSUM_CALCULATED_M(mda, pkt);
-}
-
-
-/** Determine whether the L3 (IP) checksum was calculated and found to be
- * correct.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the checksum was calculated and is correct.
- */
-static __inline unsigned int
-NETIO_PKT_L3_CSUM_CORRECT(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_L3_CSUM_CORRECT_M(mda, pkt);
-}
-
-
-/** Determine whether the Ethertype was recognized and L3 packet data was
- * processed.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- * @return Nonzero if the Ethertype was recognized and L3 packet data was
- * processed.
- */
-static __inline unsigned int
-NETIO_PKT_ETHERTYPE_RECOGNIZED(netio_pkt_t* pkt)
-{
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_ETHERTYPE_RECOGNIZED_M(mda, pkt);
-}
-
-
-/** Set an egress packet's L2 length, using a metadata pointer to speed the
- * computation.
- * @ingroup egress
- *
- * @param[in,out] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @param[in] len Packet L2 length, in bytes.
- */
-static __inline void
-NETIO_PKT_SET_L2_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt,
- int len)
-{
- mmd->l2_length = len;
-}
-
-
-/** Set an egress packet's L2 length.
- * @ingroup egress
- *
- * @param[in,out] pkt Packet on which to operate.
- * @param[in] len Packet L2 length, in bytes.
- */
-static __inline void
-NETIO_PKT_SET_L2_LENGTH(netio_pkt_t* pkt, int len)
-{
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- NETIO_PKT_SET_L2_LENGTH_MM(mmd, pkt, len);
-}
-
-
-/** Set an egress packet's L2 header length, using a metadata pointer to
- * speed the computation.
- * @ingroup egress
- *
- * It is not normally necessary to call this routine; only the L2 length,
- * not the header length, is needed to transmit a packet. It may be useful if
- * the egress packet will later be processed by code which expects to use
- * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload.
- *
- * @param[in,out] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @param[in] len Packet L2 header length, in bytes.
- */
-static __inline void
-NETIO_PKT_SET_L2_HEADER_LENGTH_MM(netio_pkt_minimal_metadata_t* mmd,
- netio_pkt_t* pkt, int len)
-{
- mmd->l3_offset = mmd->l2_offset + len;
-}
-
-
-/** Set an egress packet's L2 header length.
- * @ingroup egress
- *
- * It is not normally necessary to call this routine; only the L2 length,
- * not the header length, is needed to transmit a packet. It may be useful if
- * the egress packet will later be processed by code which expects to use
- * functions like @ref NETIO_PKT_L3_DATA() to get a pointer to the L3 payload.
- *
- * @param[in,out] pkt Packet on which to operate.
- * @param[in] len Packet L2 header length, in bytes.
- */
-static __inline void
-NETIO_PKT_SET_L2_HEADER_LENGTH(netio_pkt_t* pkt, int len)
-{
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- NETIO_PKT_SET_L2_HEADER_LENGTH_MM(mmd, pkt, len);
-}
-
-
-/** Set up an egress packet for hardware checksum computation, using a
- * metadata pointer to speed the operation.
- * @ingroup egress
- *
- * NetIO provides the ability to automatically calculate a standard
- * 16-bit Internet checksum on transmitted packets. The application
- * may specify the point in the packet where the checksum starts, the
- * number of bytes to be checksummed, and the two bytes in the packet
- * which will be replaced with the completed checksum. (If the range
- * of bytes to be checksummed includes the bytes to be replaced, the
- * initial values of those bytes will be included in the checksum.)
- *
- * For some protocols, the packet checksum covers data which is not present
- * in the packet, or is at least not contiguous to the main data payload.
- * For instance, the TCP checksum includes a "pseudo-header" which includes
- * the source and destination IP addresses of the packet. To accommodate
- * this, the checksum engine may be "seeded" with an initial value, which
- * the application would need to compute based on the specific protocol's
- * requirements. Note that the seed is given in host byte order (little-
- * endian), not network byte order (big-endian); code written to compute a
- * pseudo-header checksum in network byte order will need to byte-swap it
- * before use as the seed.
- *
- * Note that the checksum is computed as part of the transmission process,
- * so it will not be present in the packet upon completion of this routine.
- *
- * @param[in,out] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- * @param[in] start Offset within L2 packet of the first byte to include in
- * the checksum.
- * @param[in] length Number of bytes to include in the checksum.
- * the checksum.
- * @param[in] location Offset within L2 packet of the first of the two bytes
- * to be replaced with the calculated checksum.
- * @param[in] seed Initial value of the running checksum before any of the
- * packet data is added.
- */
-static __inline void
-NETIO_PKT_DO_EGRESS_CSUM_MM(netio_pkt_minimal_metadata_t* mmd,
- netio_pkt_t* pkt, int start, int length,
- int location, uint16_t seed)
-{
- mmd->csum_start = start;
- mmd->csum_length = length;
- mmd->csum_location = location;
- mmd->csum_seed = seed;
- mmd->flags |= _NETIO_PKT_NEED_EDMA_CSUM_MASK;
-}
-
-
-/** Set up an egress packet for hardware checksum computation.
- * @ingroup egress
- *
- * NetIO provides the ability to automatically calculate a standard
- * 16-bit Internet checksum on transmitted packets. The application
- * may specify the point in the packet where the checksum starts, the
- * number of bytes to be checksummed, and the two bytes in the packet
- * which will be replaced with the completed checksum. (If the range
- * of bytes to be checksummed includes the bytes to be replaced, the
- * initial values of those bytes will be included in the checksum.)
- *
- * For some protocols, the packet checksum covers data which is not present
- * in the packet, or is at least not contiguous to the main data payload.
- * For instance, the TCP checksum includes a "pseudo-header" which includes
- * the source and destination IP addresses of the packet. To accommodate
- * this, the checksum engine may be "seeded" with an initial value, which
- * the application would need to compute based on the specific protocol's
- * requirements. Note that the seed is given in host byte order (little-
- * endian), not network byte order (big-endian); code written to compute a
- * pseudo-header checksum in network byte order will need to byte-swap it
- * before use as the seed.
- *
- * Note that the checksum is computed as part of the transmission process,
- * so it will not be present in the packet upon completion of this routine.
- *
- * @param[in,out] pkt Packet on which to operate.
- * @param[in] start Offset within L2 packet of the first byte to include in
- * the checksum.
- * @param[in] length Number of bytes to include in the checksum.
- * the checksum.
- * @param[in] location Offset within L2 packet of the first of the two bytes
- * to be replaced with the calculated checksum.
- * @param[in] seed Initial value of the running checksum before any of the
- * packet data is added.
- */
-static __inline void
-NETIO_PKT_DO_EGRESS_CSUM(netio_pkt_t* pkt, int start, int length,
- int location, uint16_t seed)
-{
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- NETIO_PKT_DO_EGRESS_CSUM_MM(mmd, pkt, start, length, location, seed);
-}
-
-
-/** Return the number of bytes which could be prepended to a packet, using a
- * metadata pointer to speed the operation.
- * See @ref netio_populate_prepend_buffer() to get a full description of
- * prepending.
- *
- * @param[in,out] mda Pointer to packet's standard metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline int
-NETIO_PKT_PREPEND_AVAIL_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
- return (pkt->__packet.bits.__offset << 6) +
- NETIO_PKT_CUSTOM_HEADER_LENGTH_M(mda, pkt);
-}
-
-
-/** Return the number of bytes which could be prepended to a packet, using a
- * metadata pointer to speed the operation.
- * See @ref netio_populate_prepend_buffer() to get a full description of
- * prepending.
- * @ingroup egress
- *
- * @param[in,out] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline int
-NETIO_PKT_PREPEND_AVAIL_MM(netio_pkt_minimal_metadata_t* mmd, netio_pkt_t* pkt)
-{
- return (pkt->__packet.bits.__offset << 6) + mmd->l2_offset;
-}
-
-
-/** Return the number of bytes which could be prepended to a packet.
- * See @ref netio_populate_prepend_buffer() to get a full description of
- * prepending.
- * @ingroup egress
- *
- * @param[in] pkt Packet on which to operate.
- */
-static __inline int
-NETIO_PKT_PREPEND_AVAIL(netio_pkt_t* pkt)
-{
- if (NETIO_PKT_IS_MINIMAL(pkt))
- {
- netio_pkt_minimal_metadata_t* mmd = NETIO_PKT_MINIMAL_METADATA(pkt);
-
- return NETIO_PKT_PREPEND_AVAIL_MM(mmd, pkt);
- }
- else
- {
- netio_pkt_metadata_t* mda = NETIO_PKT_METADATA(pkt);
-
- return NETIO_PKT_PREPEND_AVAIL_M(mda, pkt);
- }
-}
-
-
-/** Flush a packet's minimal metadata from the cache, using a metadata pointer
- * to speed the operation.
- * @ingroup egress
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_MINIMAL_METADATA_MM(netio_pkt_minimal_metadata_t* mmd,
- netio_pkt_t* pkt)
-{
-}
-
-
-/** Invalidate a packet's minimal metadata from the cache, using a metadata
- * pointer to speed the operation.
- * @ingroup egress
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_INV_MINIMAL_METADATA_MM(netio_pkt_minimal_metadata_t* mmd,
- netio_pkt_t* pkt)
-{
-}
-
-
-/** Flush and then invalidate a packet's minimal metadata from the cache,
- * using a metadata pointer to speed the operation.
- * @ingroup egress
- *
- * @param[in] mmd Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_INV_MINIMAL_METADATA_MM(netio_pkt_minimal_metadata_t* mmd,
- netio_pkt_t* pkt)
-{
-}
-
-
-/** Flush a packet's metadata from the cache, using a metadata pointer
- * to speed the operation.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's minimal metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_METADATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
-}
-
-
-/** Invalidate a packet's metadata from the cache, using a metadata
- * pointer to speed the operation.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_INV_METADATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
-}
-
-
-/** Flush and then invalidate a packet's metadata from the cache,
- * using a metadata pointer to speed the operation.
- * @ingroup ingress
- *
- * @param[in] mda Pointer to packet's metadata.
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_INV_METADATA_M(netio_pkt_metadata_t* mda, netio_pkt_t* pkt)
-{
-}
-
-
-/** Flush a packet's minimal metadata from the cache.
- * @ingroup egress
- *
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_MINIMAL_METADATA(netio_pkt_t* pkt)
-{
-}
-
-
-/** Invalidate a packet's minimal metadata from the cache.
- * @ingroup egress
- *
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_INV_MINIMAL_METADATA(netio_pkt_t* pkt)
-{
-}
-
-
-/** Flush and then invalidate a packet's minimal metadata from the cache.
- * @ingroup egress
- *
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_INV_MINIMAL_METADATA(netio_pkt_t* pkt)
-{
-}
-
-
-/** Flush a packet's metadata from the cache.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_METADATA(netio_pkt_t* pkt)
-{
-}
-
-
-/** Invalidate a packet's metadata from the cache.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_INV_METADATA(netio_pkt_t* pkt)
-{
-}
-
-
-/** Flush and then invalidate a packet's metadata from the cache.
- * @ingroup ingress
- *
- * @param[in] pkt Packet on which to operate.
- */
-static __inline void
-NETIO_PKT_FLUSH_INV_METADATA(netio_pkt_t* pkt)
-{
-}
-
-/** Number of NUMA nodes we can distribute buffers to.
- * @ingroup setup */
-#define NETIO_NUM_NODE_WEIGHTS 16
-
-/**
- * @brief An object for specifying the characteristics of NetIO communication
- * endpoint.
- *
- * @ingroup setup
- *
- * The @ref netio_input_register() function uses this structure to define
- * how an application tile will communicate with an IPP.
- *
- *
- * Future updates to NetIO may add new members to this structure,
- * which can affect the success of the registration operation. Thus,
- * if dynamically initializing the structure, applications are urged to
- * zero it out first, for example:
- *
- * @code
- * netio_input_config_t config;
- * memset(&config, 0, sizeof (config));
- * config.flags = NETIO_RECV | NETIO_XMIT_CSUM | NETIO_TAG_NONE;
- * config.num_receive_packets = NETIO_MAX_RECEIVE_PKTS;
- * config.queue_id = 0;
- * .
- * .
- * .
- * @endcode
- *
- * since that guarantees that any unused structure members, including
- * members which did not exist when the application was first developed,
- * will not have unexpected values.
- *
- * If statically initializing the structure, we strongly recommend use of
- * C99-style named initializers, for example:
- *
- * @code
- * netio_input_config_t config = {
- * .flags = NETIO_RECV | NETIO_XMIT_CSUM | NETIO_TAG_NONE,
- * .num_receive_packets = NETIO_MAX_RECEIVE_PKTS,
- * .queue_id = 0,
- * },
- * @endcode
- *
- * instead of the old-style structure initialization:
- *
- * @code
- * // Bad example! Currently equivalent to the above, but don't do this.
- * netio_input_config_t config = {
- * NETIO_RECV | NETIO_XMIT_CSUM | NETIO_TAG_NONE, NETIO_MAX_RECEIVE_PKTS, 0
- * },
- * @endcode
- *
- * since the C99 style requires no changes to the code if elements of the
- * config structure are rearranged. (It also makes the initialization much
- * easier to understand.)
- *
- * Except for items which address a particular tile's transmit or receive
- * characteristics, such as the ::NETIO_RECV flag, applications are advised
- * to specify the same set of configuration data on all registrations.
- * This prevents differing results if multiple tiles happen to do their
- * registration operations in a different order on different invocations of
- * the application. This is particularly important for things like link
- * management flags, and buffer size and homing specifications.
- *
- * Unless the ::NETIO_FIXED_BUFFER_VA flag is specified in flags, the NetIO
- * buffer pool is automatically created and mapped into the application's
- * virtual address space at an address chosen by the operating system,
- * using the common memory (cmem) facility in the Tilera Multicore
- * Components library. The cmem facility allows multiple processes to gain
- * access to shared memory which is mapped into each process at an
- * identical virtual address. In order for this to work, the processes
- * must have a common ancestor, which must create the common memory using
- * tmc_cmem_init().
- *
- * In programs using the iLib process creation API, or in programs which use
- * only one process (which include programs using the pthreads library),
- * tmc_cmem_init() is called automatically. All other applications
- * must call it explicitly, before any child processes which might call
- * netio_input_register() are created.
- */
-typedef struct
-{
- /** Registration characteristics.
-
- This value determines several characteristics of the registration;
- flags for different types of behavior are ORed together to make the
- final flag value. Generally applications should specify exactly
- one flag from each of the following categories:
-
- - Whether the application will be receiving packets on this queue
- (::NETIO_RECV or ::NETIO_NO_RECV).
-
- - Whether the application will be transmitting packets on this queue,
- and if so, whether it will request egress checksum calculation
- (::NETIO_XMIT, ::NETIO_XMIT_CSUM, or ::NETIO_NO_XMIT). It is
- legal to call netio_get_buffer() without one of the XMIT flags,
- as long as ::NETIO_RECV is specified; in this case, the retrieved
- buffers must be passed to another tile for transmission.
-
- - Whether the application expects any vendor-specific tags in
- its packets' L2 headers (::NETIO_TAG_NONE, ::NETIO_TAG_BRCM,
- or ::NETIO_TAG_MRVL). This must match the configuration of the
- target IPP.
-
- To accommodate applications written to previous versions of the NetIO
- interface, none of the flags above are currently required; if omitted,
- NetIO behaves more or less as if ::NETIO_RECV | ::NETIO_XMIT_CSUM |
- ::NETIO_TAG_NONE were used. However, explicit specification of
- the relevant flags allows NetIO to do a better job of resource
- allocation, allows earlier detection of certain configuration errors,
- and may enable advanced features or higher performance in the future,
- so their use is strongly recommended.
-
- Note that specifying ::NETIO_NO_RECV along with ::NETIO_NO_XMIT
- is a special case, intended primarily for use by programs which
- retrieve network statistics or do link management operations.
- When these flags are both specified, the resulting queue may not
- be used with NetIO routines other than netio_get(), netio_set(),
- and netio_input_unregister(). See @ref link for more information
- on link management.
-
- Other flags are optional; their use is described below.
- */
- int flags;
-
- /** Interface name. This is a string which identifies the specific
- Ethernet controller hardware to be used. The format of the string
- is a device type and a device index, separated by a slash; so,
- the first 10 Gigabit Ethernet controller is named "xgbe/0", while
- the second 10/100/1000 Megabit Ethernet controller is named "gbe/1".
- */
- const char* interface;
-
- /** Receive packet queue size. This specifies the maximum number
- of ingress packets that can be received on this queue without
- being retrieved by @ref netio_get_packet(). If the IPP's distribution
- algorithm calls for a packet to be sent to this queue, and this
- number of packets are already pending there, the new packet
- will either be discarded, or sent to another tile registered
- for the same queue_id (see @ref drops). This value must
- be at least ::NETIO_MIN_RECEIVE_PKTS, can always be at least
- ::NETIO_MAX_RECEIVE_PKTS, and may be larger than that on certain
- interfaces.
- */
- int num_receive_packets;
-
- /** The queue ID being requested. Legal values for this range from 0
- to ::NETIO_MAX_QUEUE_ID, inclusive. ::NETIO_MAX_QUEUE_ID is always
- greater than or equal to the number of tiles; this allows one queue
- for each tile, plus at least one additional queue. Some applications
- may wish to use the additional queue as a destination for unwanted
- packets, since packets delivered to queues for which no tiles have
- registered are discarded.
- */
- unsigned int queue_id;
-
- /** Maximum number of small send buffers to be held in the local empty
- buffer cache. This specifies the size of the area which holds
- empty small egress buffers requested from the IPP but not yet
- retrieved via @ref netio_get_buffer(). This value must be greater
- than zero if the application will ever use @ref netio_get_buffer()
- to allocate empty small egress buffers; it may be no larger than
- ::NETIO_MAX_SEND_BUFFERS. See @ref epp for more details on empty
- buffer caching.
- */
- int num_send_buffers_small_total;
-
- /** Number of small send buffers to be preallocated at registration.
- If this value is nonzero, the specified number of empty small egress
- buffers will be requested from the IPP during the netio_input_register
- operation; this may speed the execution of @ref netio_get_buffer().
- This may be no larger than @ref num_send_buffers_small_total. See @ref
- epp for more details on empty buffer caching.
- */
- int num_send_buffers_small_prealloc;
-
- /** Maximum number of large send buffers to be held in the local empty
- buffer cache. This specifies the size of the area which holds empty
- large egress buffers requested from the IPP but not yet retrieved via
- @ref netio_get_buffer(). This value must be greater than zero if the
- application will ever use @ref netio_get_buffer() to allocate empty
- large egress buffers; it may be no larger than ::NETIO_MAX_SEND_BUFFERS.
- See @ref epp for more details on empty buffer caching.
- */
- int num_send_buffers_large_total;
-
- /** Number of large send buffers to be preallocated at registration.
- If this value is nonzero, the specified number of empty large egress
- buffers will be requested from the IPP during the netio_input_register
- operation; this may speed the execution of @ref netio_get_buffer().
- This may be no larger than @ref num_send_buffers_large_total. See @ref
- epp for more details on empty buffer caching.
- */
- int num_send_buffers_large_prealloc;
-
- /** Maximum number of jumbo send buffers to be held in the local empty
- buffer cache. This specifies the size of the area which holds empty
- jumbo egress buffers requested from the IPP but not yet retrieved via
- @ref netio_get_buffer(). This value must be greater than zero if the
- application will ever use @ref netio_get_buffer() to allocate empty
- jumbo egress buffers; it may be no larger than ::NETIO_MAX_SEND_BUFFERS.
- See @ref epp for more details on empty buffer caching.
- */
- int num_send_buffers_jumbo_total;
-
- /** Number of jumbo send buffers to be preallocated at registration.
- If this value is nonzero, the specified number of empty jumbo egress
- buffers will be requested from the IPP during the netio_input_register
- operation; this may speed the execution of @ref netio_get_buffer().
- This may be no larger than @ref num_send_buffers_jumbo_total. See @ref
- epp for more details on empty buffer caching.
- */
- int num_send_buffers_jumbo_prealloc;
-
- /** Total packet buffer size. This determines the total size, in bytes,
- of the NetIO buffer pool. Note that the maximum number of available
- buffers of each size is determined during hypervisor configuration
- (see the <em>System Programmer's Guide</em> for details); this just
- influences how much host memory is allocated for those buffers.
-
- The buffer pool is allocated from common memory, which will be
- automatically initialized if needed. If your buffer pool is larger
- than 240 MB, you might need to explicitly call @c tmc_cmem_init(),
- as described in the Application Libraries Reference Manual (UG227).
-
- Packet buffers are currently allocated in chunks of 16 MB; this
- value will be rounded up to the next larger multiple of 16 MB.
- If this value is zero, a default of 32 MB will be used; this was
- the value used by previous versions of NetIO. Note that taking this
- default also affects the placement of buffers on Linux NUMA nodes.
- See @ref buffer_node_weights for an explanation of buffer placement.
-
- In order to successfully allocate packet buffers, Linux must have
- available huge pages on the relevant Linux NUMA nodes. See the
- <em>System Programmer's Guide</em> for information on configuring
- huge page support in Linux.
- */
- uint64_t total_buffer_size;
-
- /** Buffer placement weighting factors.
-
- This array specifies the relative amount of buffering to place
- on each of the available Linux NUMA nodes. This array is
- indexed by the NUMA node, and the values in the array are
- proportional to the amount of buffer space to allocate on that
- node.
-
- If memory striping is enabled in the Hypervisor, then there is
- only one logical NUMA node (node 0). In that case, NetIO will by
- default ignore the suggested buffer node weights, and buffers
- will be striped across the physical memory controllers. See
- UG209 System Programmer's Guide for a description of the
- hypervisor option that controls memory striping.
-
- If memory striping is disabled, then there are up to four NUMA
- nodes, corresponding to the four DDRAM controllers in the TILE
- processor architecture. See UG100 Tile Processor Architecture
- Overview for a diagram showing the location of each of the DDRAM
- controllers relative to the tile array.
-
- For instance, if memory striping is disabled, the following
- configuration strucure:
-
- @code
- netio_input_config_t config = {
- .
- .
- .
- .total_buffer_size = 4 * 16 * 1024 * 1024;
- .buffer_node_weights = { 1, 0, 1, 0 },
- },
- @endcode
-
- would result in 32 MB of buffers being placed on controller 0, and
- 32 MB on controller 2. (Since buffers are allocated in units of
- 16 MB, some sets of weights will not be able to be matched exactly.)
-
- For the weights to be effective, @ref total_buffer_size must be
- nonzero. If @ref total_buffer_size is zero, causing the default
- 32 MB of buffer space to be used, then any specified weights will
- be ignored, and buffers will positioned as they were in previous
- versions of NetIO:
-
- - For xgbe/0 and gbe/0, 16 MB of buffers will be placed on controller 1,
- and the other 16 MB will be placed on controller 2.
-
- - For xgbe/1 and gbe/1, 16 MB of buffers will be placed on controller 2,
- and the other 16 MB will be placed on controller 3.
-
- If @ref total_buffer_size is nonzero, but all weights are zero,
- then all buffer space will be allocated on Linux NUMA node zero.
-
- By default, the specified buffer placement is treated as a hint;
- if sufficient free memory is not available on the specified
- controllers, the buffers will be allocated elsewhere. However,
- if the ::NETIO_STRICT_HOMING flag is specified in @ref flags, then a
- failure to allocate buffer space exactly as requested will cause the
- registration operation to fail with an error of ::NETIO_CANNOT_HOME.
-
- Note that maximal network performance cannot be achieved with
- only one memory controller.
- */
- uint8_t buffer_node_weights[NETIO_NUM_NODE_WEIGHTS];
-
- /** Fixed virtual address for packet buffers. Only valid when
- ::NETIO_FIXED_BUFFER_VA is specified in @ref flags; see the
- description of that flag for details.
- */
- void* fixed_buffer_va;
-
- /**
- Maximum number of outstanding send packet requests. This value is
- only relevant when an EPP is in use; it determines the number of
- slots in the EPP's outgoing packet queue which this tile is allowed
- to consume, and thus the number of packets which may be sent before
- the sending tile must wait for an acknowledgment from the EPP.
- Modifying this value is generally only helpful when using @ref
- netio_send_packet_vector(), where it can help improve performance by
- allowing a single vector send operation to process more packets.
- Typically it is not specified, and the default, which divides the
- outgoing packet slots evenly between all tiles on the chip, is used.
-
- If a registration asks for more outgoing packet queue slots than are
- available, ::NETIO_TOOMANY_XMIT will be returned. The total number
- of packet queue slots which are available for all tiles for each EPP
- is subject to change, but is currently ::NETIO_TOTAL_SENDS_OUTSTANDING.
-
-
- This value is ignored if ::NETIO_XMIT is not specified in flags.
- If you want to specify a large value here for a specific tile, you are
- advised to specify NETIO_NO_XMIT on other, non-transmitting tiles so
- that they do not consume a default number of packet slots. Any tile
- transmitting is required to have at least ::NETIO_MIN_SENDS_OUTSTANDING
- slots allocated to it; values less than that will be silently
- increased by the NetIO library.
- */
- int num_sends_outstanding;
-}
-netio_input_config_t;
-
-
-/** Registration flags; used in the @ref netio_input_config_t structure.
- * @addtogroup setup
- */
-/** @{ */
-
-/** Fail a registration request if we can't put packet buffers
- on the specified memory controllers. */
-#define NETIO_STRICT_HOMING 0x00000002
-
-/** This application expects no tags on its L2 headers. */
-#define NETIO_TAG_NONE 0x00000004
-
-/** This application expects Marvell extended tags on its L2 headers. */
-#define NETIO_TAG_MRVL 0x00000008
-
-/** This application expects Broadcom tags on its L2 headers. */
-#define NETIO_TAG_BRCM 0x00000010
-
-/** This registration may call routines which receive packets. */
-#define NETIO_RECV 0x00000020
-
-/** This registration may not call routines which receive packets. */
-#define NETIO_NO_RECV 0x00000040
-
-/** This registration may call routines which transmit packets. */
-#define NETIO_XMIT 0x00000080
-
-/** This registration may call routines which transmit packets with
- checksum acceleration. */
-#define NETIO_XMIT_CSUM 0x00000100
-
-/** This registration may not call routines which transmit packets. */
-#define NETIO_NO_XMIT 0x00000200
-
-/** This registration wants NetIO buffers mapped at an application-specified
- virtual address.
-
- NetIO buffers are by default created by the TMC common memory facility,
- which must be configured by a common ancestor of all processes sharing
- a network interface. When this flag is specified, NetIO buffers are
- instead mapped at an address chosen by the application (and specified
- in @ref netio_input_config_t::fixed_buffer_va). This allows multiple
- unrelated but cooperating processes to share a NetIO interface.
- All processes sharing the same interface must specify this flag,
- and all must specify the same fixed virtual address.
-
- @ref netio_input_config_t::fixed_buffer_va must be a
- multiple of 16 MB, and the packet buffers will occupy @ref
- netio_input_config_t::total_buffer_size bytes of virtual address
- space, beginning at that address. If any of those virtual addresses
- are currently occupied by other memory objects, like application or
- shared library code or data, @ref netio_input_register() will return
- ::NETIO_FAULT. While it is impossible to provide a fixed_buffer_va
- which will work for all applications, a good first guess might be to
- use 0xb0000000 minus @ref netio_input_config_t::total_buffer_size.
- If that fails, it might be helpful to consult the running application's
- virtual address description file (/proc/<em>pid</em>/maps) to see
- which regions of virtual address space are available.
- */
-#define NETIO_FIXED_BUFFER_VA 0x00000400
-
-/** This registration call will not complete unless the network link
- is up. The process will wait several seconds for this to happen (the
- precise interval is link-dependent), but if the link does not come up,
- ::NETIO_LINK_DOWN will be returned. This flag is the default if
- ::NETIO_NOREQUIRE_LINK_UP is not specified. Note that this flag by
- itself does not request that the link be brought up; that can be done
- with the ::NETIO_AUTO_LINK_UPDN or ::NETIO_AUTO_LINK_UP flags (the
- latter is the default if no NETIO_AUTO_LINK_xxx flags are specified),
- or by explicitly setting the link's desired state via netio_set().
- If the link is not brought up by one of those methods, and this flag
- is specified, the registration operation will return ::NETIO_LINK_DOWN.
- This flag is ignored if it is specified along with ::NETIO_NO_XMIT and
- ::NETIO_NO_RECV. See @ref link for more information on link
- management.
- */
-#define NETIO_REQUIRE_LINK_UP 0x00000800
-
-/** This registration call will complete even if the network link is not up.
- Whenever the link is not up, packets will not be sent or received:
- netio_get_packet() will return ::NETIO_NOPKT once all queued packets
- have been drained, and netio_send_packet() and similar routines will
- return NETIO_QUEUE_FULL once the outgoing packet queue in the EPP
- or the I/O shim is full. See @ref link for more information on link
- management.
- */
-#define NETIO_NOREQUIRE_LINK_UP 0x00001000
-
-#ifndef __DOXYGEN__
-/*
- * These are part of the implementation of the NETIO_AUTO_LINK_xxx flags,
- * but should not be used directly by applications, and are thus not
- * documented.
- */
-#define _NETIO_AUTO_UP 0x00002000
-#define _NETIO_AUTO_DN 0x00004000
-#define _NETIO_AUTO_PRESENT 0x00008000
-#endif
-
-/** Set the desired state of the link to up, allowing any speeds which are
- supported by the link hardware, as part of this registration operation.
- Do not take down the link automatically. This is the default if
- no other NETIO_AUTO_LINK_xxx flags are specified. This flag is ignored
- if it is specified along with ::NETIO_NO_XMIT and ::NETIO_NO_RECV.
- See @ref link for more information on link management.
- */
-#define NETIO_AUTO_LINK_UP (_NETIO_AUTO_PRESENT | _NETIO_AUTO_UP)
-
-/** Set the desired state of the link to up, allowing any speeds which are
- supported by the link hardware, as part of this registration operation.
- Set the desired state of the link to down the next time no tiles are
- registered for packet reception or transmission. This flag is ignored
- if it is specified along with ::NETIO_NO_XMIT and ::NETIO_NO_RECV.
- See @ref link for more information on link management.
- */
-#define NETIO_AUTO_LINK_UPDN (_NETIO_AUTO_PRESENT | _NETIO_AUTO_UP | \
- _NETIO_AUTO_DN)
-
-/** Set the desired state of the link to down the next time no tiles are
- registered for packet reception or transmission. This flag is ignored
- if it is specified along with ::NETIO_NO_XMIT and ::NETIO_NO_RECV.
- See @ref link for more information on link management.
- */
-#define NETIO_AUTO_LINK_DN (_NETIO_AUTO_PRESENT | _NETIO_AUTO_DN)
-
-/** Do not bring up the link automatically as part of this registration
- operation. Do not take down the link automatically. This flag
- is ignored if it is specified along with ::NETIO_NO_XMIT and
- ::NETIO_NO_RECV. See @ref link for more information on link management.
- */
-#define NETIO_AUTO_LINK_NONE _NETIO_AUTO_PRESENT
-
-
-/** Minimum number of receive packets. */
-#define NETIO_MIN_RECEIVE_PKTS 16
-
-/** Lower bound on the maximum number of receive packets; may be higher
- than this on some interfaces. */
-#define NETIO_MAX_RECEIVE_PKTS 128
-
-/** Maximum number of send buffers, per packet size. */
-#define NETIO_MAX_SEND_BUFFERS 16
-
-/** Number of EPP queue slots, and thus outstanding sends, per EPP. */
-#define NETIO_TOTAL_SENDS_OUTSTANDING 2015
-
-/** Minimum number of EPP queue slots, and thus outstanding sends, per
- * transmitting tile. */
-#define NETIO_MIN_SENDS_OUTSTANDING 16
-
-
-/**@}*/
-
-#ifndef __DOXYGEN__
-
-/**
- * An object for providing Ethernet packets to a process.
- */
-struct __netio_queue_impl_t;
-
-/**
- * An object for managing the user end of a NetIO queue.
- */
-struct __netio_queue_user_impl_t;
-
-#endif /* !__DOXYGEN__ */
-
-
-/** A netio_queue_t describes a NetIO communications endpoint.
- * @ingroup setup
- */
-typedef struct
-{
-#ifdef __DOXYGEN__
- uint8_t opaque[8]; /**< This is an opaque structure. */
-#else
- struct __netio_queue_impl_t* __system_part; /**< The system part. */
- struct __netio_queue_user_impl_t* __user_part; /**< The user part. */
-#ifdef _NETIO_PTHREAD
- _netio_percpu_mutex_t lock; /**< Queue lock. */
-#endif
-#endif
-}
-netio_queue_t;
-
-
-/**
- * @brief Packet send context.
- *
- * @ingroup egress
- *
- * Packet send context for use with netio_send_packet_prepare and _commit.
- */
-typedef struct
-{
-#ifdef __DOXYGEN__
- uint8_t opaque[44]; /**< This is an opaque structure. */
-#else
- uint8_t flags; /**< Defined below */
- uint8_t datalen; /**< Number of valid words pointed to by data. */
- uint32_t request[9]; /**< Request to be sent to the EPP or shim. Note
- that this is smaller than the 11-word maximum
- request size, since some constant values are
- not saved in the context. */
- uint32_t *data; /**< Data to be sent to the EPP or shim via IDN. */
-#endif
-}
-netio_send_pkt_context_t;
-
-
-#ifndef __DOXYGEN__
-#define SEND_PKT_CTX_USE_EPP 1 /**< We're sending to an EPP. */
-#define SEND_PKT_CTX_SEND_CSUM 2 /**< Request includes a checksum. */
-#endif
-
-/**
- * @brief Packet vector entry.
- *
- * @ingroup egress
- *
- * This data structure is used with netio_send_packet_vector() to send multiple
- * packets with one NetIO call. The structure should be initialized by
- * calling netio_pkt_vector_set(), rather than by setting the fields
- * directly.
- *
- * This structure is guaranteed to be a power of two in size, no
- * bigger than one L2 cache line, and to be aligned modulo its size.
- */
-typedef struct
-#ifndef __DOXYGEN__
-__attribute__((aligned(8)))
-#endif
-{
- /** Reserved for use by the user application. When initialized with
- * the netio_set_pkt_vector_entry() function, this field is guaranteed
- * to be visible to readers only after all other fields are already
- * visible. This way it can be used as a valid flag or generation
- * counter. */
- uint8_t user_data;
-
- /* Structure members below this point should not be accessed directly by
- * applications, as they may change in the future. */
-
- /** Low 8 bits of the packet address to send. The high bits are
- * acquired from the 'handle' field. */
- uint8_t buffer_address_low;
-
- /** Number of bytes to transmit. */
- uint16_t size;
-
- /** The raw handle from a netio_pkt_t. If this is NETIO_PKT_HANDLE_NONE,
- * this vector entry will be skipped and no packet will be transmitted. */
- netio_pkt_handle_t handle;
-}
-netio_pkt_vector_entry_t;
-
-
-/**
- * @brief Initialize fields in a packet vector entry.
- *
- * @ingroup egress
- *
- * @param[out] v Pointer to the vector entry to be initialized.
- * @param[in] pkt Packet to be transmitted when the vector entry is passed to
- * netio_send_packet_vector(). Note that the packet's attributes
- * (e.g., its L2 offset and length) are captured at the time this
- * routine is called; subsequent changes in those attributes will not
- * be reflected in the packet which is actually transmitted.
- * Changes in the packet's contents, however, will be so reflected.
- * If this is NULL, no packet will be transmitted.
- * @param[in] user_data User data to be set in the vector entry.
- * This function guarantees that the "user_data" field will become
- * visible to a reader only after all other fields have become visible.
- * This allows a structure in a ring buffer to be written and read
- * by a polling reader without any locks or other synchronization.
- */
-static __inline void
-netio_pkt_vector_set(volatile netio_pkt_vector_entry_t* v, netio_pkt_t* pkt,
- uint8_t user_data)
-{
- if (pkt)
- {
- if (NETIO_PKT_IS_MINIMAL(pkt))
- {
- netio_pkt_minimal_metadata_t* mmd =
- (netio_pkt_minimal_metadata_t*) &pkt->__metadata;
- v->buffer_address_low = (uintptr_t) NETIO_PKT_L2_DATA_MM(mmd, pkt) & 0xFF;
- v->size = NETIO_PKT_L2_LENGTH_MM(mmd, pkt);
- }
- else
- {
- netio_pkt_metadata_t* mda = &pkt->__metadata;
- v->buffer_address_low = (uintptr_t) NETIO_PKT_L2_DATA_M(mda, pkt) & 0xFF;
- v->size = NETIO_PKT_L2_LENGTH_M(mda, pkt);
- }
- v->handle.word = pkt->__packet.word;
- }
- else
- {
- v->handle.word = 0; /* Set handle to NETIO_PKT_HANDLE_NONE. */
- }
-
- __asm__("" : : : "memory");
-
- v->user_data = user_data;
-}
-
-
-/**
- * Flags and structures for @ref netio_get() and @ref netio_set().
- * @ingroup config
- */
-
-/** @{ */
-/** Parameter class; addr is a NETIO_PARAM_xxx value. */
-#define NETIO_PARAM 0
-/** Interface MAC address. This address is only valid with @ref netio_get().
- * The value is a 6-byte MAC address. Depending upon the overall system
- * design, a MAC address may or may not be available for each interface. */
-#define NETIO_PARAM_MAC 0
-
-/** Determine whether to suspend output on the receipt of pause frames.
- * If the value is nonzero, the I/O shim will suspend output when a pause
- * frame is received. If the value is zero, pause frames will be ignored. */
-#define NETIO_PARAM_PAUSE_IN 1
-
-/** Determine whether to send pause frames if the I/O shim packet FIFOs are
- * nearly full. If the value is zero, pause frames are not sent. If
- * the value is nonzero, it is the delay value which will be sent in any
- * pause frames which are output, in units of 512 bit times. */
-#define NETIO_PARAM_PAUSE_OUT 2
-
-/** Jumbo frame support. The value is a 4-byte integer. If the value is
- * nonzero, the MAC will accept frames of up to 10240 bytes. If the value
- * is zero, the MAC will only accept frames of up to 1544 bytes. */
-#define NETIO_PARAM_JUMBO 3
-
-/** I/O shim's overflow statistics register. The value is two 16-bit integers.
- * The first 16-bit value (or the low 16 bits, if the value is treated as a
- * 32-bit number) is the count of packets which were completely dropped and
- * not delivered by the shim. The second 16-bit value (or the high 16 bits,
- * if the value is treated as a 32-bit number) is the count of packets
- * which were truncated and thus only partially delivered by the shim. This
- * register is automatically reset to zero after it has been read.
- */
-#define NETIO_PARAM_OVERFLOW 4
-
-/** IPP statistics. This address is only valid with @ref netio_get(). The
- * value is a netio_stat_t structure. Unlike the I/O shim statistics, the
- * IPP statistics are not all reset to zero on read; see the description
- * of the netio_stat_t for details. */
-#define NETIO_PARAM_STAT 5
-
-/** Possible link state. The value is a combination of "NETIO_LINK_xxx"
- * flags. With @ref netio_get(), this will indicate which flags are
- * actually supported by the hardware.
- *
- * For historical reasons, specifying this value to netio_set() will have
- * the same behavior as using ::NETIO_PARAM_LINK_CONFIG, but this usage is
- * discouraged.
- */
-#define NETIO_PARAM_LINK_POSSIBLE_STATE 6
-
-/** Link configuration. The value is a combination of "NETIO_LINK_xxx" flags.
- * With @ref netio_set(), this will attempt to immediately bring up the
- * link using whichever of the requested flags are supported by the
- * hardware, or take down the link if the flags are zero; if this is
- * not possible, an error will be returned. Many programs will want
- * to use ::NETIO_PARAM_LINK_DESIRED_STATE instead.
- *
- * For historical reasons, specifying this value to netio_get() will
- * have the same behavior as using ::NETIO_PARAM_LINK_POSSIBLE_STATE,
- * but this usage is discouraged.
- */
-#define NETIO_PARAM_LINK_CONFIG NETIO_PARAM_LINK_POSSIBLE_STATE
-
-/** Current link state. This address is only valid with @ref netio_get().
- * The value is zero or more of the "NETIO_LINK_xxx" flags, ORed together.
- * If the link is down, the value ANDed with NETIO_LINK_SPEED will be
- * zero; if the link is up, the value ANDed with NETIO_LINK_SPEED will
- * result in exactly one of the NETIO_LINK_xxx values, indicating the
- * current speed. */
-#define NETIO_PARAM_LINK_CURRENT_STATE 7
-
-/** Variant symbol for current state, retained for compatibility with
- * pre-MDE-2.1 programs. */
-#define NETIO_PARAM_LINK_STATUS NETIO_PARAM_LINK_CURRENT_STATE
-
-/** Packet Coherence protocol. This address is only valid with @ref netio_get().
- * The value is nonzero if the interface is configured for cache-coherent DMA.
- */
-#define NETIO_PARAM_COHERENT 8
-
-/** Desired link state. The value is a conbination of "NETIO_LINK_xxx"
- * flags, which specify the desired state for the link. With @ref
- * netio_set(), this will, in the background, attempt to bring up the link
- * using whichever of the requested flags are reasonable, or take down the
- * link if the flags are zero. The actual link up or down operation may
- * happen after this call completes. If the link state changes in the
- * future, the system will continue to try to get back to the desired link
- * state; for instance, if the link is brought up successfully, and then
- * the network cable is disconnected, the link will go down. However, the
- * desired state of the link is still up, so if the cable is reconnected,
- * the link will be brought up again.
- *
- * With @ref netio_get(), this will indicate the desired state for the
- * link, as set with a previous netio_set() call, or implicitly by a
- * netio_input_register() or netio_input_unregister() operation. This may
- * not reflect the current state of the link; to get that, use
- * ::NETIO_PARAM_LINK_CURRENT_STATE. */
-#define NETIO_PARAM_LINK_DESIRED_STATE 9
-
-/** NetIO statistics structure. Retrieved using the ::NETIO_PARAM_STAT
- * address passed to @ref netio_get(). */
-typedef struct
-{
- /** Number of packets which have been received by the IPP and forwarded
- * to a tile's receive queue for processing. This value wraps at its
- * maximum, and is not cleared upon read. */
- uint32_t packets_received;
-
- /** Number of packets which have been dropped by the IPP, because they could
- * not be received, or could not be forwarded to a tile. The former happens
- * when the IPP does not have a free packet buffer of suitable size for an
- * incoming frame. The latter happens when all potential destination tiles
- * for a packet, as defined by the group, bucket, and queue configuration,
- * have full receive queues. This value wraps at its maximum, and is not
- * cleared upon read. */
- uint32_t packets_dropped;
-
- /*
- * Note: the #defines after each of the following four one-byte values
- * denote their location within the third word of the netio_stat_t. They
- * are intended for use only by the IPP implementation and are thus omitted
- * from the Doxygen output.
- */
-
- /** Number of packets dropped because no worker was able to accept a new
- * packet. This value saturates at its maximum, and is cleared upon
- * read. */
- uint8_t drops_no_worker;
-#ifndef __DOXYGEN__
-#define NETIO_STAT_DROPS_NO_WORKER 0
-#endif
-
- /** Number of packets dropped because no small buffers were available.
- * This value saturates at its maximum, and is cleared upon read. */
- uint8_t drops_no_smallbuf;
-#ifndef __DOXYGEN__
-#define NETIO_STAT_DROPS_NO_SMALLBUF 1
-#endif
-
- /** Number of packets dropped because no large buffers were available.
- * This value saturates at its maximum, and is cleared upon read. */
- uint8_t drops_no_largebuf;
-#ifndef __DOXYGEN__
-#define NETIO_STAT_DROPS_NO_LARGEBUF 2
-#endif
-
- /** Number of packets dropped because no jumbo buffers were available.
- * This value saturates at its maximum, and is cleared upon read. */
- uint8_t drops_no_jumbobuf;
-#ifndef __DOXYGEN__
-#define NETIO_STAT_DROPS_NO_JUMBOBUF 3
-#endif
-}
-netio_stat_t;
-
-
-/** Link can run, should run, or is running at 10 Mbps. */
-#define NETIO_LINK_10M 0x01
-
-/** Link can run, should run, or is running at 100 Mbps. */
-#define NETIO_LINK_100M 0x02
-
-/** Link can run, should run, or is running at 1 Gbps. */
-#define NETIO_LINK_1G 0x04
-
-/** Link can run, should run, or is running at 10 Gbps. */
-#define NETIO_LINK_10G 0x08
-
-/** Link should run at the highest speed supported by the link and by
- * the device connected to the link. Only usable as a value for
- * the link's desired state; never returned as a value for the current
- * or possible states. */
-#define NETIO_LINK_ANYSPEED 0x10
-
-/** All legal link speeds. */
-#define NETIO_LINK_SPEED (NETIO_LINK_10M | \
- NETIO_LINK_100M | \
- NETIO_LINK_1G | \
- NETIO_LINK_10G | \
- NETIO_LINK_ANYSPEED)
-
-
-/** MAC register class. Addr is a register offset within the MAC.
- * Registers within the XGbE and GbE MACs are documented in the Tile
- * Processor I/O Device Guide (UG104). MAC registers start at address
- * 0x4000, and do not include the MAC_INTERFACE registers. */
-#define NETIO_MAC 1
-
-/** MDIO register class (IEEE 802.3 clause 22 format). Addr is the "addr"
- * member of a netio_mdio_addr_t structure. */
-#define NETIO_MDIO 2
-
-/** MDIO register class (IEEE 802.3 clause 45 format). Addr is the "addr"
- * member of a netio_mdio_addr_t structure. */
-#define NETIO_MDIO_CLAUSE45 3
-
-/** NetIO MDIO address type. Retrieved or provided using the ::NETIO_MDIO
- * address passed to @ref netio_get() or @ref netio_set(). */
-typedef union
-{
- struct
- {
- unsigned int reg:16; /**< MDIO register offset. For clause 22 access,
- must be less than 32. */
- unsigned int phy:5; /**< Which MDIO PHY to access. */
- unsigned int dev:5; /**< Which MDIO device to access within that PHY.
- Applicable for clause 45 access only; ignored
- for clause 22 access. */
- }
- bits; /**< Container for bitfields. */
- uint64_t addr; /**< Value to pass to @ref netio_get() or
- * @ref netio_set(). */
-}
-netio_mdio_addr_t;
-
-/** @} */
-
-#endif /* __NETIO_INTF_H__ */
diff --git a/arch/tile/include/hv/syscall_public.h b/arch/tile/include/hv/syscall_public.h
deleted file mode 100644
index 9cc0837e69fd..000000000000
--- a/arch/tile/include/hv/syscall_public.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file syscall.h
- * Indices for the hypervisor system calls that are intended to be called
- * directly, rather than only through hypervisor-generated "glue" code.
- */
-
-#ifndef _SYS_HV_INCLUDE_SYSCALL_PUBLIC_H
-#define _SYS_HV_INCLUDE_SYSCALL_PUBLIC_H
-
-/** Fast syscall flag bit location. When this bit is set, the hypervisor
- * handles the syscall specially.
- */
-#define HV_SYS_FAST_SHIFT 14
-
-/** Fast syscall flag bit mask. */
-#define HV_SYS_FAST_MASK (1 << HV_SYS_FAST_SHIFT)
-
-/** Bit location for flagging fast syscalls that can be called from PL0. */
-#define HV_SYS_FAST_PLO_SHIFT 13
-
-/** Fast syscall allowing PL0 bit mask. */
-#define HV_SYS_FAST_PL0_MASK (1 << HV_SYS_FAST_PLO_SHIFT)
-
-/** Perform an MF that waits for all victims to reach DRAM. */
-#define HV_SYS_fence_incoherent (51 | HV_SYS_FAST_MASK \
- | HV_SYS_FAST_PL0_MASK)
-
-#endif /* !_SYS_HV_INCLUDE_SYSCALL_PUBLIC_H */
diff --git a/arch/tile/include/uapi/arch/abi.h b/arch/tile/include/uapi/arch/abi.h
deleted file mode 100644
index df161a484730..000000000000
--- a/arch/tile/include/uapi/arch/abi.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * ABI-related register definitions.
- */
-
-#ifndef __ARCH_ABI_H__
-
-#ifndef __tile__ /* support uncommon use of arch headers in non-tile builds */
-# include <arch/chip.h>
-# define __INT_REG_BITS CHIP_WORD_SIZE()
-#endif
-
-#include <arch/intreg.h>
-
-/* __need_int_reg_t is deprecated: just include <arch/intreg.h> */
-#ifndef __need_int_reg_t
-
-#define __ARCH_ABI_H__
-
-#ifndef __ASSEMBLER__
-/** Unsigned type that can hold a register. */
-typedef __uint_reg_t uint_reg_t;
-
-/** Signed type that can hold a register. */
-typedef __int_reg_t int_reg_t;
-#endif
-
-/** String prefix to use for printf(). */
-#define INT_REG_FMT __INT_REG_FMT
-
-/** Number of bits in a register. */
-#define INT_REG_BITS __INT_REG_BITS
-
-
-/* Registers 0 - 55 are "normal", but some perform special roles. */
-
-#define TREG_FP 52 /**< Frame pointer. */
-#define TREG_TP 53 /**< Thread pointer. */
-#define TREG_SP 54 /**< Stack pointer. */
-#define TREG_LR 55 /**< Link to calling function PC. */
-
-/** Index of last normal general-purpose register. */
-#define TREG_LAST_GPR 55
-
-/* Registers 56 - 62 are "special" network registers. */
-
-#define TREG_SN 56 /**< Static network access. */
-#define TREG_IDN0 57 /**< IDN demux 0 access. */
-#define TREG_IDN1 58 /**< IDN demux 1 access. */
-#define TREG_UDN0 59 /**< UDN demux 0 access. */
-#define TREG_UDN1 60 /**< UDN demux 1 access. */
-#define TREG_UDN2 61 /**< UDN demux 2 access. */
-#define TREG_UDN3 62 /**< UDN demux 3 access. */
-
-/* Register 63 is the "special" zero register. */
-
-#define TREG_ZERO 63 /**< "Zero" register; always reads as "0". */
-
-
-/** By convention, this register is used to hold the syscall number. */
-#define TREG_SYSCALL_NR 10
-
-/** Name of register that holds the syscall number, for use in assembly. */
-#define TREG_SYSCALL_NR_NAME r10
-
-
-/**
- * The ABI requires callers to allocate a caller state save area of
- * this many bytes at the bottom of each stack frame.
- */
-#define C_ABI_SAVE_AREA_SIZE (2 * (INT_REG_BITS / 8))
-
-/**
- * The operand to an 'info' opcode directing the backtracer to not
- * try to find the calling frame.
- */
-#define INFO_OP_CANNOT_BACKTRACE 2
-
-
-#endif /* !__need_int_reg_t */
-
-/* Make sure we later can get all the definitions and declarations. */
-#undef __need_int_reg_t
-
-#endif /* !__ARCH_ABI_H__ */
diff --git a/arch/tile/include/uapi/arch/chip.h b/arch/tile/include/uapi/arch/chip.h
deleted file mode 100644
index 7f55c6856c89..000000000000
--- a/arch/tile/include/uapi/arch/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#if __tile_chip__ == 1
-#include <arch/chip_tilepro.h>
-#elif defined(__tilegx__)
-#include <arch/chip_tilegx.h>
-#else
-#error Unexpected Tilera chip type
-#endif
diff --git a/arch/tile/include/uapi/arch/chip_tilegx.h b/arch/tile/include/uapi/arch/chip_tilegx.h
deleted file mode 100644
index c2a71a43b21c..000000000000
--- a/arch/tile/include/uapi/arch/chip_tilegx.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * @file
- * Global header file.
- * This header file specifies defines for TILE-Gx.
- */
-
-#ifndef __ARCH_CHIP_H__
-#define __ARCH_CHIP_H__
-
-/** Specify chip version.
- * When possible, prefer the CHIP_xxx symbols below for future-proofing.
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip__ symbol.
- */
-#define TILE_CHIP 10
-
-/** Specify chip revision.
- * This provides for the case of a respin of a particular chip type;
- * the normal value for this symbol is "0".
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip_rev__ symbol.
- */
-#define TILE_CHIP_REV 0
-
-/** The name of this architecture. */
-#define CHIP_ARCH_NAME "tilegx"
-
-/** The ELF e_machine type for binaries for this chip. */
-#define CHIP_ELF_TYPE() EM_TILEGX
-
-/** The alternate ELF e_machine type for binaries for this chip. */
-#define CHIP_COMPAT_ELF_TYPE() 0x2597
-
-/** What is the native word size of the machine? */
-#define CHIP_WORD_SIZE() 64
-
-/** How many bits of a virtual address are used. Extra bits must be
- * the sign extension of the low bits.
- */
-#define CHIP_VA_WIDTH() 42
-
-/** How many bits are in a physical address? */
-#define CHIP_PA_WIDTH() 40
-
-/** Size of the L2 cache, in bytes. */
-#define CHIP_L2_CACHE_SIZE() 262144
-
-/** Log size of an L2 cache line in bytes. */
-#define CHIP_L2_LOG_LINE_SIZE() 6
-
-/** Size of an L2 cache line, in bytes. */
-#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
-
-/** Associativity of the L2 cache. */
-#define CHIP_L2_ASSOC() 8
-
-/** Size of the L1 data cache, in bytes. */
-#define CHIP_L1D_CACHE_SIZE() 32768
-
-/** Log size of an L1 data cache line in bytes. */
-#define CHIP_L1D_LOG_LINE_SIZE() 6
-
-/** Size of an L1 data cache line, in bytes. */
-#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
-
-/** Associativity of the L1 data cache. */
-#define CHIP_L1D_ASSOC() 2
-
-/** Size of the L1 instruction cache, in bytes. */
-#define CHIP_L1I_CACHE_SIZE() 32768
-
-/** Log size of an L1 instruction cache line in bytes. */
-#define CHIP_L1I_LOG_LINE_SIZE() 6
-
-/** Size of an L1 instruction cache line, in bytes. */
-#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
-
-/** Associativity of the L1 instruction cache. */
-#define CHIP_L1I_ASSOC() 2
-
-/** Stride with which flush instructions must be issued. */
-#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which inv instructions must be issued. */
-#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which finv instructions must be issued. */
-#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Can the local cache coherently cache data that is homed elsewhere? */
-#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
-
-/** How many simultaneous outstanding victims can the L2 cache have? */
-#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
-
-/** Does the TLB support the NC and NOALLOC bits? */
-#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
-
-/** Does the chip support hash-for-home caching? */
-#define CHIP_HAS_CBOX_HOME_MAP() 1
-
-/** Number of entries in the chip's home map tables. */
-#define CHIP_CBOX_HOME_MAP_SIZE() 128
-
-/** Do uncacheable requests miss in the cache regardless of whether
- * there is matching data? */
-#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
-
-/** Does the mf instruction wait for victims? */
-#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
-
-/** Does the chip have an "inv" instruction that doesn't also flush? */
-#define CHIP_HAS_INV() 1
-
-/** Does the chip have a "wh64" instruction? */
-#define CHIP_HAS_WH64() 1
-
-/** Does this chip have a 'dword_align' instruction? */
-#define CHIP_HAS_DWORD_ALIGN() 0
-
-/** Number of performance counters. */
-#define CHIP_PERFORMANCE_COUNTERS() 4
-
-/** Does this chip have auxiliary performance counters? */
-#define CHIP_HAS_AUX_PERF_COUNTERS() 1
-
-/** Is the CBOX_MSR1 SPR supported? */
-#define CHIP_HAS_CBOX_MSR1() 0
-
-/** Is the TILE_RTF_HWM SPR supported? */
-#define CHIP_HAS_TILE_RTF_HWM() 1
-
-/** Is the TILE_WRITE_PENDING SPR supported? */
-#define CHIP_HAS_TILE_WRITE_PENDING() 0
-
-/** Is the PROC_STATUS SPR supported? */
-#define CHIP_HAS_PROC_STATUS_SPR() 1
-
-/** Is the DSTREAM_PF SPR supported? */
-#define CHIP_HAS_DSTREAM_PF() 1
-
-/** Log of the number of mshims we have. */
-#define CHIP_LOG_NUM_MSHIMS() 2
-
-/** Are the bases of the interrupt vector areas fixed? */
-#define CHIP_HAS_FIXED_INTVEC_BASE() 0
-
-/** Are the interrupt masks split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_INTR_MASK() 0
-
-/** Is the cycle count split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_CYCLE() 0
-
-/** Does the chip have a static network? */
-#define CHIP_HAS_SN() 0
-
-/** Does the chip have a static network processor? */
-#define CHIP_HAS_SN_PROC() 0
-
-/** Size of the L1 static network processor instruction cache, in bytes. */
-/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
-
-/** Does the chip have DMA support in each tile? */
-#define CHIP_HAS_TILE_DMA() 0
-
-/** Does the chip have the second revision of the directly accessible
- * dynamic networks? This encapsulates a number of characteristics,
- * including the absence of the catch-all, the absence of inline message
- * tags, the absence of support for network context-switching, and so on.
- */
-#define CHIP_HAS_REV1_XDN() 1
-
-/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
-#define CHIP_HAS_CMPEXCH() 1
-
-/** Does the chip have memory-mapped I/O support? */
-#define CHIP_HAS_MMIO() 1
-
-/** Does the chip have post-completion interrupts? */
-#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
-
-/** Does the chip have native single step support? */
-#define CHIP_HAS_SINGLE_STEP() 1
-
-#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
-
-/** How many entries are present in the instruction TLB? */
-#define CHIP_ITLB_ENTRIES() 16
-
-/** How many entries are present in the data TLB? */
-#define CHIP_DTLB_ENTRIES() 32
-
-/** How many MAF entries does the XAUI shim have? */
-#define CHIP_XAUI_MAF_ENTRIES() 32
-
-/** Does the memory shim have a source-id table? */
-#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
-
-/** Does the L1 instruction cache clear on reset? */
-#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
-
-/** Does the chip come out of reset with valid coordinates on all tiles?
- * Note that if defined, this also implies that the upper left is 1,1.
- */
-#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
-
-/** Does the chip have unified packet formats? */
-#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
-
-/** Does the chip support write reordering? */
-#define CHIP_HAS_WRITE_REORDERING() 1
-
-/** Does the chip support Y-X routing as well as X-Y? */
-#define CHIP_HAS_Y_X_ROUTING() 1
-
-/** Is INTCTRL_3 managed with the correct MPL? */
-#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
-
-/** Is it possible to configure the chip to be big-endian? */
-#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
-
-/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
-#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
-
-/** Is the DIAG_TRACE_WAY SPR supported? */
-#define CHIP_HAS_DIAG_TRACE_WAY() 0
-
-/** Is the MEM_STRIPE_CONFIG SPR supported? */
-#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
-
-/** Are the TLB_PERF SPRs supported? */
-#define CHIP_HAS_TLB_PERF() 1
-
-/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
-#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
-
-/** Does the chip support rev1 DMA packets? */
-#define CHIP_HAS_REV1_DMA_PACKETS() 1
-
-/** Does the chip have an IPI shim? */
-#define CHIP_HAS_IPI() 1
-
-#endif /* !__OPEN_SOURCE__ */
-#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/uapi/arch/chip_tilepro.h b/arch/tile/include/uapi/arch/chip_tilepro.h
deleted file mode 100644
index a8a3ed144dfe..000000000000
--- a/arch/tile/include/uapi/arch/chip_tilepro.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * @file
- * Global header file.
- * This header file specifies defines for TILEPro.
- */
-
-#ifndef __ARCH_CHIP_H__
-#define __ARCH_CHIP_H__
-
-/** Specify chip version.
- * When possible, prefer the CHIP_xxx symbols below for future-proofing.
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip__ symbol.
- */
-#define TILE_CHIP 1
-
-/** Specify chip revision.
- * This provides for the case of a respin of a particular chip type;
- * the normal value for this symbol is "0".
- * This is intended for cross-compiling; native compilation should
- * use the predefined __tile_chip_rev__ symbol.
- */
-#define TILE_CHIP_REV 0
-
-/** The name of this architecture. */
-#define CHIP_ARCH_NAME "tilepro"
-
-/** The ELF e_machine type for binaries for this chip. */
-#define CHIP_ELF_TYPE() EM_TILEPRO
-
-/** The alternate ELF e_machine type for binaries for this chip. */
-#define CHIP_COMPAT_ELF_TYPE() 0x2507
-
-/** What is the native word size of the machine? */
-#define CHIP_WORD_SIZE() 32
-
-/** How many bits of a virtual address are used. Extra bits must be
- * the sign extension of the low bits.
- */
-#define CHIP_VA_WIDTH() 32
-
-/** How many bits are in a physical address? */
-#define CHIP_PA_WIDTH() 36
-
-/** Size of the L2 cache, in bytes. */
-#define CHIP_L2_CACHE_SIZE() 65536
-
-/** Log size of an L2 cache line in bytes. */
-#define CHIP_L2_LOG_LINE_SIZE() 6
-
-/** Size of an L2 cache line, in bytes. */
-#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
-
-/** Associativity of the L2 cache. */
-#define CHIP_L2_ASSOC() 4
-
-/** Size of the L1 data cache, in bytes. */
-#define CHIP_L1D_CACHE_SIZE() 8192
-
-/** Log size of an L1 data cache line in bytes. */
-#define CHIP_L1D_LOG_LINE_SIZE() 4
-
-/** Size of an L1 data cache line, in bytes. */
-#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
-
-/** Associativity of the L1 data cache. */
-#define CHIP_L1D_ASSOC() 2
-
-/** Size of the L1 instruction cache, in bytes. */
-#define CHIP_L1I_CACHE_SIZE() 16384
-
-/** Log size of an L1 instruction cache line in bytes. */
-#define CHIP_L1I_LOG_LINE_SIZE() 6
-
-/** Size of an L1 instruction cache line, in bytes. */
-#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
-
-/** Associativity of the L1 instruction cache. */
-#define CHIP_L1I_ASSOC() 1
-
-/** Stride with which flush instructions must be issued. */
-#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which inv instructions must be issued. */
-#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Stride with which finv instructions must be issued. */
-#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
-
-/** Can the local cache coherently cache data that is homed elsewhere? */
-#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
-
-/** How many simultaneous outstanding victims can the L2 cache have? */
-#define CHIP_MAX_OUTSTANDING_VICTIMS() 4
-
-/** Does the TLB support the NC and NOALLOC bits? */
-#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
-
-/** Does the chip support hash-for-home caching? */
-#define CHIP_HAS_CBOX_HOME_MAP() 1
-
-/** Number of entries in the chip's home map tables. */
-#define CHIP_CBOX_HOME_MAP_SIZE() 64
-
-/** Do uncacheable requests miss in the cache regardless of whether
- * there is matching data? */
-#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
-
-/** Does the mf instruction wait for victims? */
-#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
-
-/** Does the chip have an "inv" instruction that doesn't also flush? */
-#define CHIP_HAS_INV() 1
-
-/** Does the chip have a "wh64" instruction? */
-#define CHIP_HAS_WH64() 1
-
-/** Does this chip have a 'dword_align' instruction? */
-#define CHIP_HAS_DWORD_ALIGN() 1
-
-/** Number of performance counters. */
-#define CHIP_PERFORMANCE_COUNTERS() 4
-
-/** Does this chip have auxiliary performance counters? */
-#define CHIP_HAS_AUX_PERF_COUNTERS() 1
-
-/** Is the CBOX_MSR1 SPR supported? */
-#define CHIP_HAS_CBOX_MSR1() 1
-
-/** Is the TILE_RTF_HWM SPR supported? */
-#define CHIP_HAS_TILE_RTF_HWM() 1
-
-/** Is the TILE_WRITE_PENDING SPR supported? */
-#define CHIP_HAS_TILE_WRITE_PENDING() 1
-
-/** Is the PROC_STATUS SPR supported? */
-#define CHIP_HAS_PROC_STATUS_SPR() 1
-
-/** Is the DSTREAM_PF SPR supported? */
-#define CHIP_HAS_DSTREAM_PF() 0
-
-/** Log of the number of mshims we have. */
-#define CHIP_LOG_NUM_MSHIMS() 2
-
-/** Are the bases of the interrupt vector areas fixed? */
-#define CHIP_HAS_FIXED_INTVEC_BASE() 1
-
-/** Are the interrupt masks split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_INTR_MASK() 1
-
-/** Is the cycle count split up into 2 SPRs? */
-#define CHIP_HAS_SPLIT_CYCLE() 1
-
-/** Does the chip have a static network? */
-#define CHIP_HAS_SN() 1
-
-/** Does the chip have a static network processor? */
-#define CHIP_HAS_SN_PROC() 0
-
-/** Size of the L1 static network processor instruction cache, in bytes. */
-/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 1 */
-
-/** Does the chip have DMA support in each tile? */
-#define CHIP_HAS_TILE_DMA() 1
-
-/** Does the chip have the second revision of the directly accessible
- * dynamic networks? This encapsulates a number of characteristics,
- * including the absence of the catch-all, the absence of inline message
- * tags, the absence of support for network context-switching, and so on.
- */
-#define CHIP_HAS_REV1_XDN() 0
-
-/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
-#define CHIP_HAS_CMPEXCH() 0
-
-/** Does the chip have memory-mapped I/O support? */
-#define CHIP_HAS_MMIO() 0
-
-/** Does the chip have post-completion interrupts? */
-#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0
-
-/** Does the chip have native single step support? */
-#define CHIP_HAS_SINGLE_STEP() 0
-
-#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
-
-/** How many entries are present in the instruction TLB? */
-#define CHIP_ITLB_ENTRIES() 16
-
-/** How many entries are present in the data TLB? */
-#define CHIP_DTLB_ENTRIES() 16
-
-/** How many MAF entries does the XAUI shim have? */
-#define CHIP_XAUI_MAF_ENTRIES() 32
-
-/** Does the memory shim have a source-id table? */
-#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
-
-/** Does the L1 instruction cache clear on reset? */
-#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
-
-/** Does the chip come out of reset with valid coordinates on all tiles?
- * Note that if defined, this also implies that the upper left is 1,1.
- */
-#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
-
-/** Does the chip have unified packet formats? */
-#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
-
-/** Does the chip support write reordering? */
-#define CHIP_HAS_WRITE_REORDERING() 1
-
-/** Does the chip support Y-X routing as well as X-Y? */
-#define CHIP_HAS_Y_X_ROUTING() 1
-
-/** Is INTCTRL_3 managed with the correct MPL? */
-#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
-
-/** Is it possible to configure the chip to be big-endian? */
-#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
-
-/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
-#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 1
-
-/** Is the DIAG_TRACE_WAY SPR supported? */
-#define CHIP_HAS_DIAG_TRACE_WAY() 1
-
-/** Is the MEM_STRIPE_CONFIG SPR supported? */
-#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
-
-/** Are the TLB_PERF SPRs supported? */
-#define CHIP_HAS_TLB_PERF() 1
-
-/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
-#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 1
-
-/** Does the chip support rev1 DMA packets? */
-#define CHIP_HAS_REV1_DMA_PACKETS() 1
-
-/** Does the chip have an IPI shim? */
-#define CHIP_HAS_IPI() 0
-
-#endif /* !__OPEN_SOURCE__ */
-#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/uapi/arch/icache.h b/arch/tile/include/uapi/arch/icache.h
deleted file mode 100644
index ff85a5d77f16..000000000000
--- a/arch/tile/include/uapi/arch/icache.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- */
-
-/**
- * @file
- *
- * Support for invalidating bytes in the instruction cache.
- */
-
-#ifndef __ARCH_ICACHE_H__
-#define __ARCH_ICACHE_H__
-
-#include <arch/chip.h>
-
-
-/**
- * Invalidate the instruction cache for the given range of memory.
- *
- * @param addr The start of memory to be invalidated.
- * @param size The number of bytes to be invalidated.
- * @param page_size The system's page size, e.g. getpagesize() in userspace.
- * This value must be a power of two no larger than the page containing
- * the code to be invalidated. If the value is smaller than the actual page
- * size, this function will still work, but may run slower than necessary.
- */
-static __inline void
-invalidate_icache(const void* addr, unsigned long size,
- unsigned long page_size)
-{
- const unsigned long cache_way_size =
- CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
- unsigned long max_useful_size;
- const char* start, *end;
- long num_passes;
-
- if (__builtin_expect(size == 0, 0))
- return;
-
-#ifdef __tilegx__
- /* Limit the number of bytes visited to avoid redundant iterations. */
- max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
-
- /* No PA aliasing is possible, so one pass always suffices. */
- num_passes = 1;
-#else
- /* Limit the number of bytes visited to avoid redundant iterations. */
- max_useful_size = cache_way_size;
-
- /*
- * Compute how many passes we need (we'll treat 0 as if it were 1).
- * This works because we know the page size is a power of two.
- */
- num_passes = cache_way_size >> __builtin_ctzl(page_size);
-#endif
-
- if (__builtin_expect(size > max_useful_size, 0))
- size = max_useful_size;
-
- /* Locate the first and last bytes to be invalidated. */
- start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
- end = (const char*)addr + size - 1;
-
- __insn_mf();
-
- do
- {
- const char* p;
-
- for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
- __insn_icoh(p);
-
- start += page_size;
- end += page_size;
- }
- while (--num_passes > 0);
-
- __insn_drain();
-}
-
-
-#endif /* __ARCH_ICACHE_H__ */
diff --git a/arch/tile/include/uapi/arch/interrupts.h b/arch/tile/include/uapi/arch/interrupts.h
deleted file mode 100644
index c288b5d82b4d..000000000000
--- a/arch/tile/include/uapi/arch/interrupts.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifdef __tilegx__
-#include <arch/interrupts_64.h>
-#else
-#include <arch/interrupts_32.h>
-#endif
diff --git a/arch/tile/include/uapi/arch/interrupts_32.h b/arch/tile/include/uapi/arch/interrupts_32.h
deleted file mode 100644
index a748752cec16..000000000000
--- a/arch/tile/include/uapi/arch/interrupts_32.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __ARCH_INTERRUPTS_H__
-#define __ARCH_INTERRUPTS_H__
-
-#ifndef __KERNEL__
-/** Mask for an interrupt. */
-/* Note: must handle breaking interrupts into high and low words manually. */
-#define INT_MASK_LO(intno) (1 << (intno))
-#define INT_MASK_HI(intno) (1 << ((intno) - 32))
-
-#ifndef __ASSEMBLER__
-#define INT_MASK(intno) (1ULL << (intno))
-#endif
-#endif
-
-
-/** Where a given interrupt executes */
-#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
-
-/** Where to store a vector for a given interrupt. */
-#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
-
-/** The base address of user-level interrupts. */
-#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
-
-
-/** Additional synthetic interrupt. */
-#define INT_BREAKPOINT (63)
-
-#define INT_ITLB_MISS 0
-#define INT_MEM_ERROR 1
-#define INT_ILL 2
-#define INT_GPV 3
-#define INT_SN_ACCESS 4
-#define INT_IDN_ACCESS 5
-#define INT_UDN_ACCESS 6
-#define INT_IDN_REFILL 7
-#define INT_UDN_REFILL 8
-#define INT_IDN_COMPLETE 9
-#define INT_UDN_COMPLETE 10
-#define INT_SWINT_3 11
-#define INT_SWINT_2 12
-#define INT_SWINT_1 13
-#define INT_SWINT_0 14
-#define INT_UNALIGN_DATA 15
-#define INT_DTLB_MISS 16
-#define INT_DTLB_ACCESS 17
-#define INT_DMATLB_MISS 18
-#define INT_DMATLB_ACCESS 19
-#define INT_SNITLB_MISS 20
-#define INT_SN_NOTIFY 21
-#define INT_SN_FIREWALL 22
-#define INT_IDN_FIREWALL 23
-#define INT_UDN_FIREWALL 24
-#define INT_TILE_TIMER 25
-#define INT_IDN_TIMER 26
-#define INT_UDN_TIMER 27
-#define INT_DMA_NOTIFY 28
-#define INT_IDN_CA 29
-#define INT_UDN_CA 30
-#define INT_IDN_AVAIL 31
-#define INT_UDN_AVAIL 32
-#define INT_PERF_COUNT 33
-#define INT_INTCTRL_3 34
-#define INT_INTCTRL_2 35
-#define INT_INTCTRL_1 36
-#define INT_INTCTRL_0 37
-#define INT_BOOT_ACCESS 38
-#define INT_WORLD_ACCESS 39
-#define INT_I_ASID 40
-#define INT_D_ASID 41
-#define INT_DMA_ASID 42
-#define INT_SNI_ASID 43
-#define INT_DMA_CPL 44
-#define INT_SN_CPL 45
-#define INT_DOUBLE_FAULT 46
-#define INT_SN_STATIC_ACCESS 47
-#define INT_AUX_PERF_COUNT 48
-
-#define NUM_INTERRUPTS 49
-
-#ifndef __ASSEMBLER__
-#define QUEUED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#define NONQUEUED_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define CRITICAL_MASKED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#define CRITICAL_UNMASKED_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define MASKABLE_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#define UNMASKABLE_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define SYNC_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_SN_ACCESS) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_IDN_REFILL) | \
- (1ULL << INT_UDN_REFILL) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_SN_STATIC_ACCESS) | \
- 0)
-#define NON_SYNC_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_DMATLB_MISS) | \
- (1ULL << INT_DMATLB_ACCESS) | \
- (1ULL << INT_SNITLB_MISS) | \
- (1ULL << INT_SN_NOTIFY) | \
- (1ULL << INT_SN_FIREWALL) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_DMA_NOTIFY) | \
- (1ULL << INT_IDN_CA) | \
- (1ULL << INT_UDN_CA) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DMA_ASID) | \
- (1ULL << INT_SNI_ASID) | \
- (1ULL << INT_DMA_CPL) | \
- (1ULL << INT_SN_CPL) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- 0)
-#endif /* !__ASSEMBLER__ */
-#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/uapi/arch/interrupts_64.h b/arch/tile/include/uapi/arch/interrupts_64.h
deleted file mode 100644
index 142eaff3c244..000000000000
--- a/arch/tile/include/uapi/arch/interrupts_64.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __ARCH_INTERRUPTS_H__
-#define __ARCH_INTERRUPTS_H__
-
-#ifndef __KERNEL__
-/** Mask for an interrupt. */
-#ifdef __ASSEMBLER__
-/* Note: must handle breaking interrupts into high and low words manually. */
-#define INT_MASK(intno) (1 << (intno))
-#else
-#define INT_MASK(intno) (1ULL << (intno))
-#endif
-#endif
-
-
-/** Where a given interrupt executes */
-#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
-
-/** Where to store a vector for a given interrupt. */
-#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
-
-/** The base address of user-level interrupts. */
-#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
-
-
-/** Additional synthetic interrupt. */
-#define INT_BREAKPOINT (63)
-
-#define INT_MEM_ERROR 0
-#define INT_SINGLE_STEP_3 1
-#define INT_SINGLE_STEP_2 2
-#define INT_SINGLE_STEP_1 3
-#define INT_SINGLE_STEP_0 4
-#define INT_IDN_COMPLETE 5
-#define INT_UDN_COMPLETE 6
-#define INT_ITLB_MISS 7
-#define INT_ILL 8
-#define INT_GPV 9
-#define INT_IDN_ACCESS 10
-#define INT_UDN_ACCESS 11
-#define INT_SWINT_3 12
-#define INT_SWINT_2 13
-#define INT_SWINT_1 14
-#define INT_SWINT_0 15
-#define INT_ILL_TRANS 16
-#define INT_UNALIGN_DATA 17
-#define INT_DTLB_MISS 18
-#define INT_DTLB_ACCESS 19
-#define INT_IDN_FIREWALL 20
-#define INT_UDN_FIREWALL 21
-#define INT_TILE_TIMER 22
-#define INT_AUX_TILE_TIMER 23
-#define INT_IDN_TIMER 24
-#define INT_UDN_TIMER 25
-#define INT_IDN_AVAIL 26
-#define INT_UDN_AVAIL 27
-#define INT_IPI_3 28
-#define INT_IPI_2 29
-#define INT_IPI_1 30
-#define INT_IPI_0 31
-#define INT_PERF_COUNT 32
-#define INT_AUX_PERF_COUNT 33
-#define INT_INTCTRL_3 34
-#define INT_INTCTRL_2 35
-#define INT_INTCTRL_1 36
-#define INT_INTCTRL_0 37
-#define INT_BOOT_ACCESS 38
-#define INT_WORLD_ACCESS 39
-#define INT_I_ASID 40
-#define INT_D_ASID 41
-#define INT_DOUBLE_FAULT 42
-
-#define NUM_INTERRUPTS 43
-
-#ifndef __ASSEMBLER__
-#define QUEUED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#define NONQUEUED_INTERRUPTS ( \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- 0)
-#define CRITICAL_MASKED_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- 0)
-#define CRITICAL_UNMASKED_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#define MASKABLE_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- 0)
-#define UNMASKABLE_INTERRUPTS ( \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#define SYNC_INTERRUPTS ( \
- (1ULL << INT_SINGLE_STEP_3) | \
- (1ULL << INT_SINGLE_STEP_2) | \
- (1ULL << INT_SINGLE_STEP_1) | \
- (1ULL << INT_SINGLE_STEP_0) | \
- (1ULL << INT_IDN_COMPLETE) | \
- (1ULL << INT_UDN_COMPLETE) | \
- (1ULL << INT_ITLB_MISS) | \
- (1ULL << INT_ILL) | \
- (1ULL << INT_GPV) | \
- (1ULL << INT_IDN_ACCESS) | \
- (1ULL << INT_UDN_ACCESS) | \
- (1ULL << INT_SWINT_3) | \
- (1ULL << INT_SWINT_2) | \
- (1ULL << INT_SWINT_1) | \
- (1ULL << INT_SWINT_0) | \
- (1ULL << INT_ILL_TRANS) | \
- (1ULL << INT_UNALIGN_DATA) | \
- (1ULL << INT_DTLB_MISS) | \
- (1ULL << INT_DTLB_ACCESS) | \
- 0)
-#define NON_SYNC_INTERRUPTS ( \
- (1ULL << INT_MEM_ERROR) | \
- (1ULL << INT_IDN_FIREWALL) | \
- (1ULL << INT_UDN_FIREWALL) | \
- (1ULL << INT_TILE_TIMER) | \
- (1ULL << INT_AUX_TILE_TIMER) | \
- (1ULL << INT_IDN_TIMER) | \
- (1ULL << INT_UDN_TIMER) | \
- (1ULL << INT_IDN_AVAIL) | \
- (1ULL << INT_UDN_AVAIL) | \
- (1ULL << INT_IPI_3) | \
- (1ULL << INT_IPI_2) | \
- (1ULL << INT_IPI_1) | \
- (1ULL << INT_IPI_0) | \
- (1ULL << INT_PERF_COUNT) | \
- (1ULL << INT_AUX_PERF_COUNT) | \
- (1ULL << INT_INTCTRL_3) | \
- (1ULL << INT_INTCTRL_2) | \
- (1ULL << INT_INTCTRL_1) | \
- (1ULL << INT_INTCTRL_0) | \
- (1ULL << INT_BOOT_ACCESS) | \
- (1ULL << INT_WORLD_ACCESS) | \
- (1ULL << INT_I_ASID) | \
- (1ULL << INT_D_ASID) | \
- (1ULL << INT_DOUBLE_FAULT) | \
- 0)
-#endif /* !__ASSEMBLER__ */
-#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/uapi/arch/intreg.h b/arch/tile/include/uapi/arch/intreg.h
deleted file mode 100644
index 5387fb645bb8..000000000000
--- a/arch/tile/include/uapi/arch/intreg.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2017 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * Provide types and defines for the type that can hold a register,
- * in the implementation namespace.
- */
-
-#ifndef __ARCH_INTREG_H__
-#define __ARCH_INTREG_H__
-
-/*
- * Get number of bits in a register. __INT_REG_BITS may be defined
- * prior to including this header to force a particular bit width.
- */
-
-#ifndef __INT_REG_BITS
-# if defined __tilegx__
-# define __INT_REG_BITS 64
-# elif defined __tilepro__
-# define __INT_REG_BITS 32
-# else
-# error Unrecognized architecture
-# endif
-#endif
-
-#if __INT_REG_BITS == 64
-
-# ifndef __ASSEMBLER__
-/** Unsigned type that can hold a register. */
-typedef unsigned long long __uint_reg_t;
-
-/** Signed type that can hold a register. */
-typedef long long __int_reg_t;
-# endif
-
-/** String prefix to use for printf(). */
-# define __INT_REG_FMT "ll"
-
-#elif __INT_REG_BITS == 32
-
-# ifndef __ASSEMBLER__
-/** Unsigned type that can hold a register. */
-typedef unsigned long __uint_reg_t;
-
-/** Signed type that can hold a register. */
-typedef long __int_reg_t;
-# endif
-
-/** String prefix to use for printf(). */
-# define __INT_REG_FMT "l"
-
-#else
-# error Unrecognized value of __INT_REG_BITS
-#endif
-
-#endif /* !__ARCH_INTREG_H__ */
diff --git a/arch/tile/include/uapi/arch/opcode.h b/arch/tile/include/uapi/arch/opcode.h
deleted file mode 100644
index a9ce5961a028..000000000000
--- a/arch/tile/include/uapi/arch/opcode.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#if defined(__tilepro__)
-#include <arch/opcode_tilepro.h>
-#elif defined(__tilegx__)
-#include <arch/opcode_tilegx.h>
-#else
-#error Unexpected Tilera chip type
-#endif
diff --git a/arch/tile/include/uapi/arch/opcode_tilegx.h b/arch/tile/include/uapi/arch/opcode_tilegx.h
deleted file mode 100644
index 948ea544567f..000000000000
--- a/arch/tile/include/uapi/arch/opcode_tilegx.h
+++ /dev/null
@@ -1,1407 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* TILE-Gx opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-#ifndef __ARCH_OPCODE_H__
-#define __ARCH_OPCODE_H__
-
-#ifndef __ASSEMBLER__
-
-typedef unsigned long long tilegx_bundle_bits;
-
-/* These are the bits that determine if a bundle is in the X encoding. */
-#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
-
-enum
-{
- /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
- TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
-
- /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
- TILEGX_NUM_PIPELINE_ENCODINGS = 5,
-
- /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
- TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
-
- /* Instructions take this many bytes. */
- TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
-
- /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
- TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
-
- /* Bundles should be aligned modulo this number of bytes. */
- TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
- (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
-
- /* Number of registers (some are magic, such as network I/O). */
- TILEGX_NUM_REGISTERS = 64,
-};
-
-/* Make a few "tile_" variables to simplify common code between
- architectures. */
-
-typedef tilegx_bundle_bits tile_bundle_bits;
-#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
-#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
- TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_BPT_BUNDLE TILEGX_BPT_BUNDLE
-
-/* 64-bit pattern for a { bpt ; nop } bundle. */
-#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-
-static __inline unsigned int
-get_BFEnd_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 24)) & 0xf);
-}
-
-static __inline unsigned int
-get_BFStart_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3f);
-}
-
-static __inline unsigned int
-get_BrOff_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 37)) & 0x0001ffc0);
-}
-
-static __inline unsigned int
-get_BrType_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 54)) & 0x1f);
-}
-
-static __inline unsigned int
-get_Dest_Imm8_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 43)) & 0x000000c0);
-}
-
-static __inline unsigned int
-get_Dest_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Imm16_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm16_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 51)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_JumpOff_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x7ffffff);
-}
-
-static __inline unsigned int
-get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 58)) & 0x1);
-}
-
-static __inline unsigned int
-get_MF_Imm14_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3fff);
-}
-
-static __inline unsigned int
-get_MT_Imm14_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 37)) & 0x00003fc0);
-}
-
-static __inline unsigned int
-get_Mode(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 62)) & 0x3);
-}
-
-static __inline unsigned int
-get_Opcode_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 28)) & 0x7);
-}
-
-static __inline unsigned int
-get_Opcode_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 59)) & 0x7);
-}
-
-static __inline unsigned int
-get_Opcode_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 27)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 58)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y2(tilegx_bundle_bits n)
-{
- return (((n >> 26)) & 0x00000001) |
- (((unsigned int)(n >> 56)) & 0x00000002);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3);
-}
-
-static __inline unsigned int
-get_ShAmt_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShAmt_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline unsigned int
-get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3);
-}
-
-static __inline unsigned int
-get_SrcA_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y2(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcBDest_Y2(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 51)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-
-static __inline int
-sign_extend(int n, int num_bits)
-{
- int shift = (int)(sizeof(int) * 8 - num_bits);
- return (n << shift) >> shift;
-}
-
-
-
-static __inline tilegx_bundle_bits
-create_BFEnd_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_BFOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 24);
-}
-
-static __inline tilegx_bundle_bits
-create_BFStart_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_BrOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_BrType_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilegx_bundle_bits
-create_Dest_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm16_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xffff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm16_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8OpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 20);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8OpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 51);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_Imm8_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_JumpOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
-}
-
-static __inline tilegx_bundle_bits
-create_JumpOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x1)) << 58);
-}
-
-static __inline tilegx_bundle_bits
-create_MF_Imm14_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_MT_Imm14_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_Mode(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 62);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7) << 28);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x7)) << 59);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 27);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0xf)) << 58);
-}
-
-static __inline tilegx_bundle_bits
-create_Opcode_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x00000001) << 26) |
- (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_RRROpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_ShAmt_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilegx_bundle_bits
-create_ShiftOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcA_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 20);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcBDest_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_SrcB_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilegx_bundle_bits
-create_UnaryOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
-}
-
-
-enum
-{
- ADDI_IMM8_OPCODE_X0 = 1,
- ADDI_IMM8_OPCODE_X1 = 1,
- ADDI_OPCODE_Y0 = 0,
- ADDI_OPCODE_Y1 = 1,
- ADDLI_OPCODE_X0 = 1,
- ADDLI_OPCODE_X1 = 0,
- ADDXI_IMM8_OPCODE_X0 = 2,
- ADDXI_IMM8_OPCODE_X1 = 2,
- ADDXI_OPCODE_Y0 = 1,
- ADDXI_OPCODE_Y1 = 2,
- ADDXLI_OPCODE_X0 = 2,
- ADDXLI_OPCODE_X1 = 1,
- ADDXSC_RRR_0_OPCODE_X0 = 1,
- ADDXSC_RRR_0_OPCODE_X1 = 1,
- ADDX_RRR_0_OPCODE_X0 = 2,
- ADDX_RRR_0_OPCODE_X1 = 2,
- ADDX_RRR_0_OPCODE_Y0 = 0,
- ADDX_RRR_0_OPCODE_Y1 = 0,
- ADD_RRR_0_OPCODE_X0 = 3,
- ADD_RRR_0_OPCODE_X1 = 3,
- ADD_RRR_0_OPCODE_Y0 = 1,
- ADD_RRR_0_OPCODE_Y1 = 1,
- ANDI_IMM8_OPCODE_X0 = 3,
- ANDI_IMM8_OPCODE_X1 = 3,
- ANDI_OPCODE_Y0 = 2,
- ANDI_OPCODE_Y1 = 3,
- AND_RRR_0_OPCODE_X0 = 4,
- AND_RRR_0_OPCODE_X1 = 4,
- AND_RRR_5_OPCODE_Y0 = 0,
- AND_RRR_5_OPCODE_Y1 = 0,
- BEQZT_BRANCH_OPCODE_X1 = 16,
- BEQZ_BRANCH_OPCODE_X1 = 17,
- BFEXTS_BF_OPCODE_X0 = 4,
- BFEXTU_BF_OPCODE_X0 = 5,
- BFINS_BF_OPCODE_X0 = 6,
- BF_OPCODE_X0 = 3,
- BGEZT_BRANCH_OPCODE_X1 = 18,
- BGEZ_BRANCH_OPCODE_X1 = 19,
- BGTZT_BRANCH_OPCODE_X1 = 20,
- BGTZ_BRANCH_OPCODE_X1 = 21,
- BLBCT_BRANCH_OPCODE_X1 = 22,
- BLBC_BRANCH_OPCODE_X1 = 23,
- BLBST_BRANCH_OPCODE_X1 = 24,
- BLBS_BRANCH_OPCODE_X1 = 25,
- BLEZT_BRANCH_OPCODE_X1 = 26,
- BLEZ_BRANCH_OPCODE_X1 = 27,
- BLTZT_BRANCH_OPCODE_X1 = 28,
- BLTZ_BRANCH_OPCODE_X1 = 29,
- BNEZT_BRANCH_OPCODE_X1 = 30,
- BNEZ_BRANCH_OPCODE_X1 = 31,
- BRANCH_OPCODE_X1 = 2,
- CMOVEQZ_RRR_0_OPCODE_X0 = 5,
- CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
- CMOVNEZ_RRR_0_OPCODE_X0 = 6,
- CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
- CMPEQI_IMM8_OPCODE_X0 = 4,
- CMPEQI_IMM8_OPCODE_X1 = 4,
- CMPEQI_OPCODE_Y0 = 3,
- CMPEQI_OPCODE_Y1 = 4,
- CMPEQ_RRR_0_OPCODE_X0 = 7,
- CMPEQ_RRR_0_OPCODE_X1 = 5,
- CMPEQ_RRR_3_OPCODE_Y0 = 0,
- CMPEQ_RRR_3_OPCODE_Y1 = 2,
- CMPEXCH4_RRR_0_OPCODE_X1 = 6,
- CMPEXCH_RRR_0_OPCODE_X1 = 7,
- CMPLES_RRR_0_OPCODE_X0 = 8,
- CMPLES_RRR_0_OPCODE_X1 = 8,
- CMPLES_RRR_2_OPCODE_Y0 = 0,
- CMPLES_RRR_2_OPCODE_Y1 = 0,
- CMPLEU_RRR_0_OPCODE_X0 = 9,
- CMPLEU_RRR_0_OPCODE_X1 = 9,
- CMPLEU_RRR_2_OPCODE_Y0 = 1,
- CMPLEU_RRR_2_OPCODE_Y1 = 1,
- CMPLTSI_IMM8_OPCODE_X0 = 5,
- CMPLTSI_IMM8_OPCODE_X1 = 5,
- CMPLTSI_OPCODE_Y0 = 4,
- CMPLTSI_OPCODE_Y1 = 5,
- CMPLTS_RRR_0_OPCODE_X0 = 10,
- CMPLTS_RRR_0_OPCODE_X1 = 10,
- CMPLTS_RRR_2_OPCODE_Y0 = 2,
- CMPLTS_RRR_2_OPCODE_Y1 = 2,
- CMPLTUI_IMM8_OPCODE_X0 = 6,
- CMPLTUI_IMM8_OPCODE_X1 = 6,
- CMPLTU_RRR_0_OPCODE_X0 = 11,
- CMPLTU_RRR_0_OPCODE_X1 = 11,
- CMPLTU_RRR_2_OPCODE_Y0 = 3,
- CMPLTU_RRR_2_OPCODE_Y1 = 3,
- CMPNE_RRR_0_OPCODE_X0 = 12,
- CMPNE_RRR_0_OPCODE_X1 = 12,
- CMPNE_RRR_3_OPCODE_Y0 = 1,
- CMPNE_RRR_3_OPCODE_Y1 = 3,
- CMULAF_RRR_0_OPCODE_X0 = 13,
- CMULA_RRR_0_OPCODE_X0 = 14,
- CMULFR_RRR_0_OPCODE_X0 = 15,
- CMULF_RRR_0_OPCODE_X0 = 16,
- CMULHR_RRR_0_OPCODE_X0 = 17,
- CMULH_RRR_0_OPCODE_X0 = 18,
- CMUL_RRR_0_OPCODE_X0 = 19,
- CNTLZ_UNARY_OPCODE_X0 = 1,
- CNTLZ_UNARY_OPCODE_Y0 = 1,
- CNTTZ_UNARY_OPCODE_X0 = 2,
- CNTTZ_UNARY_OPCODE_Y0 = 2,
- CRC32_32_RRR_0_OPCODE_X0 = 20,
- CRC32_8_RRR_0_OPCODE_X0 = 21,
- DBLALIGN2_RRR_0_OPCODE_X0 = 22,
- DBLALIGN2_RRR_0_OPCODE_X1 = 13,
- DBLALIGN4_RRR_0_OPCODE_X0 = 23,
- DBLALIGN4_RRR_0_OPCODE_X1 = 14,
- DBLALIGN6_RRR_0_OPCODE_X0 = 24,
- DBLALIGN6_RRR_0_OPCODE_X1 = 15,
- DBLALIGN_RRR_0_OPCODE_X0 = 25,
- DRAIN_UNARY_OPCODE_X1 = 1,
- DTLBPR_UNARY_OPCODE_X1 = 2,
- EXCH4_RRR_0_OPCODE_X1 = 16,
- EXCH_RRR_0_OPCODE_X1 = 17,
- FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
- FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
- FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
- FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
- FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
- FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
- FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
- FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
- FETCHADD4_RRR_0_OPCODE_X1 = 18,
- FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
- FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
- FETCHADD_RRR_0_OPCODE_X1 = 21,
- FETCHAND4_RRR_0_OPCODE_X1 = 22,
- FETCHAND_RRR_0_OPCODE_X1 = 23,
- FETCHOR4_RRR_0_OPCODE_X1 = 24,
- FETCHOR_RRR_0_OPCODE_X1 = 25,
- FINV_UNARY_OPCODE_X1 = 3,
- FLUSHWB_UNARY_OPCODE_X1 = 4,
- FLUSH_UNARY_OPCODE_X1 = 5,
- FNOP_UNARY_OPCODE_X0 = 3,
- FNOP_UNARY_OPCODE_X1 = 6,
- FNOP_UNARY_OPCODE_Y0 = 3,
- FNOP_UNARY_OPCODE_Y1 = 8,
- FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
- FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
- FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
- FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
- FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
- FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
- FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
- FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
- ICOH_UNARY_OPCODE_X1 = 7,
- ILL_UNARY_OPCODE_X1 = 8,
- ILL_UNARY_OPCODE_Y1 = 9,
- IMM8_OPCODE_X0 = 4,
- IMM8_OPCODE_X1 = 3,
- INV_UNARY_OPCODE_X1 = 9,
- IRET_UNARY_OPCODE_X1 = 10,
- JALRP_UNARY_OPCODE_X1 = 11,
- JALRP_UNARY_OPCODE_Y1 = 10,
- JALR_UNARY_OPCODE_X1 = 12,
- JALR_UNARY_OPCODE_Y1 = 11,
- JAL_JUMP_OPCODE_X1 = 0,
- JRP_UNARY_OPCODE_X1 = 13,
- JRP_UNARY_OPCODE_Y1 = 12,
- JR_UNARY_OPCODE_X1 = 14,
- JR_UNARY_OPCODE_Y1 = 13,
- JUMP_OPCODE_X1 = 4,
- J_JUMP_OPCODE_X1 = 1,
- LD1S_ADD_IMM8_OPCODE_X1 = 7,
- LD1S_OPCODE_Y2 = 0,
- LD1S_UNARY_OPCODE_X1 = 15,
- LD1U_ADD_IMM8_OPCODE_X1 = 8,
- LD1U_OPCODE_Y2 = 1,
- LD1U_UNARY_OPCODE_X1 = 16,
- LD2S_ADD_IMM8_OPCODE_X1 = 9,
- LD2S_OPCODE_Y2 = 2,
- LD2S_UNARY_OPCODE_X1 = 17,
- LD2U_ADD_IMM8_OPCODE_X1 = 10,
- LD2U_OPCODE_Y2 = 3,
- LD2U_UNARY_OPCODE_X1 = 18,
- LD4S_ADD_IMM8_OPCODE_X1 = 11,
- LD4S_OPCODE_Y2 = 1,
- LD4S_UNARY_OPCODE_X1 = 19,
- LD4U_ADD_IMM8_OPCODE_X1 = 12,
- LD4U_OPCODE_Y2 = 2,
- LD4U_UNARY_OPCODE_X1 = 20,
- LDNA_ADD_IMM8_OPCODE_X1 = 21,
- LDNA_UNARY_OPCODE_X1 = 21,
- LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
- LDNT1S_UNARY_OPCODE_X1 = 22,
- LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
- LDNT1U_UNARY_OPCODE_X1 = 23,
- LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
- LDNT2S_UNARY_OPCODE_X1 = 24,
- LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
- LDNT2U_UNARY_OPCODE_X1 = 25,
- LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
- LDNT4S_UNARY_OPCODE_X1 = 26,
- LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
- LDNT4U_UNARY_OPCODE_X1 = 27,
- LDNT_ADD_IMM8_OPCODE_X1 = 19,
- LDNT_UNARY_OPCODE_X1 = 28,
- LD_ADD_IMM8_OPCODE_X1 = 20,
- LD_OPCODE_Y2 = 3,
- LD_UNARY_OPCODE_X1 = 29,
- LNK_UNARY_OPCODE_X1 = 30,
- LNK_UNARY_OPCODE_Y1 = 14,
- MFSPR_IMM8_OPCODE_X1 = 22,
- MF_UNARY_OPCODE_X1 = 31,
- MM_BF_OPCODE_X0 = 7,
- MNZ_RRR_0_OPCODE_X0 = 40,
- MNZ_RRR_0_OPCODE_X1 = 26,
- MNZ_RRR_4_OPCODE_Y0 = 2,
- MNZ_RRR_4_OPCODE_Y1 = 2,
- MODE_OPCODE_YA2 = 1,
- MODE_OPCODE_YB2 = 2,
- MODE_OPCODE_YC2 = 3,
- MTSPR_IMM8_OPCODE_X1 = 23,
- MULAX_RRR_0_OPCODE_X0 = 41,
- MULAX_RRR_3_OPCODE_Y0 = 2,
- MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
- MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
- MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
- MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
- MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
- MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
- MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
- MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
- MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
- MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
- MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
- MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
- MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
- MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
- MULX_RRR_0_OPCODE_X0 = 52,
- MULX_RRR_3_OPCODE_Y0 = 3,
- MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
- MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
- MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
- MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
- MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
- MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
- MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
- MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
- MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
- MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
- MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
- MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
- MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
- MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
- MZ_RRR_0_OPCODE_X0 = 63,
- MZ_RRR_0_OPCODE_X1 = 27,
- MZ_RRR_4_OPCODE_Y0 = 3,
- MZ_RRR_4_OPCODE_Y1 = 3,
- NAP_UNARY_OPCODE_X1 = 32,
- NOP_UNARY_OPCODE_X0 = 5,
- NOP_UNARY_OPCODE_X1 = 33,
- NOP_UNARY_OPCODE_Y0 = 5,
- NOP_UNARY_OPCODE_Y1 = 15,
- NOR_RRR_0_OPCODE_X0 = 64,
- NOR_RRR_0_OPCODE_X1 = 28,
- NOR_RRR_5_OPCODE_Y0 = 1,
- NOR_RRR_5_OPCODE_Y1 = 1,
- ORI_IMM8_OPCODE_X0 = 7,
- ORI_IMM8_OPCODE_X1 = 24,
- OR_RRR_0_OPCODE_X0 = 65,
- OR_RRR_0_OPCODE_X1 = 29,
- OR_RRR_5_OPCODE_Y0 = 2,
- OR_RRR_5_OPCODE_Y1 = 2,
- PCNT_UNARY_OPCODE_X0 = 6,
- PCNT_UNARY_OPCODE_Y0 = 6,
- REVBITS_UNARY_OPCODE_X0 = 7,
- REVBITS_UNARY_OPCODE_Y0 = 7,
- REVBYTES_UNARY_OPCODE_X0 = 8,
- REVBYTES_UNARY_OPCODE_Y0 = 8,
- ROTLI_SHIFT_OPCODE_X0 = 1,
- ROTLI_SHIFT_OPCODE_X1 = 1,
- ROTLI_SHIFT_OPCODE_Y0 = 0,
- ROTLI_SHIFT_OPCODE_Y1 = 0,
- ROTL_RRR_0_OPCODE_X0 = 66,
- ROTL_RRR_0_OPCODE_X1 = 30,
- ROTL_RRR_6_OPCODE_Y0 = 0,
- ROTL_RRR_6_OPCODE_Y1 = 0,
- RRR_0_OPCODE_X0 = 5,
- RRR_0_OPCODE_X1 = 5,
- RRR_0_OPCODE_Y0 = 5,
- RRR_0_OPCODE_Y1 = 6,
- RRR_1_OPCODE_Y0 = 6,
- RRR_1_OPCODE_Y1 = 7,
- RRR_2_OPCODE_Y0 = 7,
- RRR_2_OPCODE_Y1 = 8,
- RRR_3_OPCODE_Y0 = 8,
- RRR_3_OPCODE_Y1 = 9,
- RRR_4_OPCODE_Y0 = 9,
- RRR_4_OPCODE_Y1 = 10,
- RRR_5_OPCODE_Y0 = 10,
- RRR_5_OPCODE_Y1 = 11,
- RRR_6_OPCODE_Y0 = 11,
- RRR_6_OPCODE_Y1 = 12,
- RRR_7_OPCODE_Y0 = 12,
- RRR_7_OPCODE_Y1 = 13,
- RRR_8_OPCODE_Y0 = 13,
- RRR_9_OPCODE_Y0 = 14,
- SHIFT_OPCODE_X0 = 6,
- SHIFT_OPCODE_X1 = 6,
- SHIFT_OPCODE_Y0 = 15,
- SHIFT_OPCODE_Y1 = 14,
- SHL16INSLI_OPCODE_X0 = 7,
- SHL16INSLI_OPCODE_X1 = 7,
- SHL1ADDX_RRR_0_OPCODE_X0 = 67,
- SHL1ADDX_RRR_0_OPCODE_X1 = 31,
- SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
- SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
- SHL1ADD_RRR_0_OPCODE_X0 = 68,
- SHL1ADD_RRR_0_OPCODE_X1 = 32,
- SHL1ADD_RRR_1_OPCODE_Y0 = 0,
- SHL1ADD_RRR_1_OPCODE_Y1 = 0,
- SHL2ADDX_RRR_0_OPCODE_X0 = 69,
- SHL2ADDX_RRR_0_OPCODE_X1 = 33,
- SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
- SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
- SHL2ADD_RRR_0_OPCODE_X0 = 70,
- SHL2ADD_RRR_0_OPCODE_X1 = 34,
- SHL2ADD_RRR_1_OPCODE_Y0 = 1,
- SHL2ADD_RRR_1_OPCODE_Y1 = 1,
- SHL3ADDX_RRR_0_OPCODE_X0 = 71,
- SHL3ADDX_RRR_0_OPCODE_X1 = 35,
- SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
- SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
- SHL3ADD_RRR_0_OPCODE_X0 = 72,
- SHL3ADD_RRR_0_OPCODE_X1 = 36,
- SHL3ADD_RRR_1_OPCODE_Y0 = 2,
- SHL3ADD_RRR_1_OPCODE_Y1 = 2,
- SHLI_SHIFT_OPCODE_X0 = 2,
- SHLI_SHIFT_OPCODE_X1 = 2,
- SHLI_SHIFT_OPCODE_Y0 = 1,
- SHLI_SHIFT_OPCODE_Y1 = 1,
- SHLXI_SHIFT_OPCODE_X0 = 3,
- SHLXI_SHIFT_OPCODE_X1 = 3,
- SHLX_RRR_0_OPCODE_X0 = 73,
- SHLX_RRR_0_OPCODE_X1 = 37,
- SHL_RRR_0_OPCODE_X0 = 74,
- SHL_RRR_0_OPCODE_X1 = 38,
- SHL_RRR_6_OPCODE_Y0 = 1,
- SHL_RRR_6_OPCODE_Y1 = 1,
- SHRSI_SHIFT_OPCODE_X0 = 4,
- SHRSI_SHIFT_OPCODE_X1 = 4,
- SHRSI_SHIFT_OPCODE_Y0 = 2,
- SHRSI_SHIFT_OPCODE_Y1 = 2,
- SHRS_RRR_0_OPCODE_X0 = 75,
- SHRS_RRR_0_OPCODE_X1 = 39,
- SHRS_RRR_6_OPCODE_Y0 = 2,
- SHRS_RRR_6_OPCODE_Y1 = 2,
- SHRUI_SHIFT_OPCODE_X0 = 5,
- SHRUI_SHIFT_OPCODE_X1 = 5,
- SHRUI_SHIFT_OPCODE_Y0 = 3,
- SHRUI_SHIFT_OPCODE_Y1 = 3,
- SHRUXI_SHIFT_OPCODE_X0 = 6,
- SHRUXI_SHIFT_OPCODE_X1 = 6,
- SHRUX_RRR_0_OPCODE_X0 = 76,
- SHRUX_RRR_0_OPCODE_X1 = 40,
- SHRU_RRR_0_OPCODE_X0 = 77,
- SHRU_RRR_0_OPCODE_X1 = 41,
- SHRU_RRR_6_OPCODE_Y0 = 3,
- SHRU_RRR_6_OPCODE_Y1 = 3,
- SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
- ST1_ADD_IMM8_OPCODE_X1 = 25,
- ST1_OPCODE_Y2 = 0,
- ST1_RRR_0_OPCODE_X1 = 42,
- ST2_ADD_IMM8_OPCODE_X1 = 26,
- ST2_OPCODE_Y2 = 1,
- ST2_RRR_0_OPCODE_X1 = 43,
- ST4_ADD_IMM8_OPCODE_X1 = 27,
- ST4_OPCODE_Y2 = 2,
- ST4_RRR_0_OPCODE_X1 = 44,
- STNT1_ADD_IMM8_OPCODE_X1 = 28,
- STNT1_RRR_0_OPCODE_X1 = 45,
- STNT2_ADD_IMM8_OPCODE_X1 = 29,
- STNT2_RRR_0_OPCODE_X1 = 46,
- STNT4_ADD_IMM8_OPCODE_X1 = 30,
- STNT4_RRR_0_OPCODE_X1 = 47,
- STNT_ADD_IMM8_OPCODE_X1 = 31,
- STNT_RRR_0_OPCODE_X1 = 48,
- ST_ADD_IMM8_OPCODE_X1 = 32,
- ST_OPCODE_Y2 = 3,
- ST_RRR_0_OPCODE_X1 = 49,
- SUBXSC_RRR_0_OPCODE_X0 = 79,
- SUBXSC_RRR_0_OPCODE_X1 = 50,
- SUBX_RRR_0_OPCODE_X0 = 80,
- SUBX_RRR_0_OPCODE_X1 = 51,
- SUBX_RRR_0_OPCODE_Y0 = 2,
- SUBX_RRR_0_OPCODE_Y1 = 2,
- SUB_RRR_0_OPCODE_X0 = 81,
- SUB_RRR_0_OPCODE_X1 = 52,
- SUB_RRR_0_OPCODE_Y0 = 3,
- SUB_RRR_0_OPCODE_Y1 = 3,
- SWINT0_UNARY_OPCODE_X1 = 34,
- SWINT1_UNARY_OPCODE_X1 = 35,
- SWINT2_UNARY_OPCODE_X1 = 36,
- SWINT3_UNARY_OPCODE_X1 = 37,
- TBLIDXB0_UNARY_OPCODE_X0 = 9,
- TBLIDXB0_UNARY_OPCODE_Y0 = 9,
- TBLIDXB1_UNARY_OPCODE_X0 = 10,
- TBLIDXB1_UNARY_OPCODE_Y0 = 10,
- TBLIDXB2_UNARY_OPCODE_X0 = 11,
- TBLIDXB2_UNARY_OPCODE_Y0 = 11,
- TBLIDXB3_UNARY_OPCODE_X0 = 12,
- TBLIDXB3_UNARY_OPCODE_Y0 = 12,
- UNARY_RRR_0_OPCODE_X0 = 82,
- UNARY_RRR_0_OPCODE_X1 = 53,
- UNARY_RRR_1_OPCODE_Y0 = 3,
- UNARY_RRR_1_OPCODE_Y1 = 3,
- V1ADDI_IMM8_OPCODE_X0 = 8,
- V1ADDI_IMM8_OPCODE_X1 = 33,
- V1ADDUC_RRR_0_OPCODE_X0 = 83,
- V1ADDUC_RRR_0_OPCODE_X1 = 54,
- V1ADD_RRR_0_OPCODE_X0 = 84,
- V1ADD_RRR_0_OPCODE_X1 = 55,
- V1ADIFFU_RRR_0_OPCODE_X0 = 85,
- V1AVGU_RRR_0_OPCODE_X0 = 86,
- V1CMPEQI_IMM8_OPCODE_X0 = 9,
- V1CMPEQI_IMM8_OPCODE_X1 = 34,
- V1CMPEQ_RRR_0_OPCODE_X0 = 87,
- V1CMPEQ_RRR_0_OPCODE_X1 = 56,
- V1CMPLES_RRR_0_OPCODE_X0 = 88,
- V1CMPLES_RRR_0_OPCODE_X1 = 57,
- V1CMPLEU_RRR_0_OPCODE_X0 = 89,
- V1CMPLEU_RRR_0_OPCODE_X1 = 58,
- V1CMPLTSI_IMM8_OPCODE_X0 = 10,
- V1CMPLTSI_IMM8_OPCODE_X1 = 35,
- V1CMPLTS_RRR_0_OPCODE_X0 = 90,
- V1CMPLTS_RRR_0_OPCODE_X1 = 59,
- V1CMPLTUI_IMM8_OPCODE_X0 = 11,
- V1CMPLTUI_IMM8_OPCODE_X1 = 36,
- V1CMPLTU_RRR_0_OPCODE_X0 = 91,
- V1CMPLTU_RRR_0_OPCODE_X1 = 60,
- V1CMPNE_RRR_0_OPCODE_X0 = 92,
- V1CMPNE_RRR_0_OPCODE_X1 = 61,
- V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
- V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
- V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
- V1DDOTPU_RRR_0_OPCODE_X0 = 162,
- V1DOTPA_RRR_0_OPCODE_X0 = 95,
- V1DOTPUA_RRR_0_OPCODE_X0 = 163,
- V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
- V1DOTPUS_RRR_0_OPCODE_X0 = 97,
- V1DOTPU_RRR_0_OPCODE_X0 = 164,
- V1DOTP_RRR_0_OPCODE_X0 = 98,
- V1INT_H_RRR_0_OPCODE_X0 = 99,
- V1INT_H_RRR_0_OPCODE_X1 = 62,
- V1INT_L_RRR_0_OPCODE_X0 = 100,
- V1INT_L_RRR_0_OPCODE_X1 = 63,
- V1MAXUI_IMM8_OPCODE_X0 = 12,
- V1MAXUI_IMM8_OPCODE_X1 = 37,
- V1MAXU_RRR_0_OPCODE_X0 = 101,
- V1MAXU_RRR_0_OPCODE_X1 = 64,
- V1MINUI_IMM8_OPCODE_X0 = 13,
- V1MINUI_IMM8_OPCODE_X1 = 38,
- V1MINU_RRR_0_OPCODE_X0 = 102,
- V1MINU_RRR_0_OPCODE_X1 = 65,
- V1MNZ_RRR_0_OPCODE_X0 = 103,
- V1MNZ_RRR_0_OPCODE_X1 = 66,
- V1MULTU_RRR_0_OPCODE_X0 = 104,
- V1MULUS_RRR_0_OPCODE_X0 = 105,
- V1MULU_RRR_0_OPCODE_X0 = 106,
- V1MZ_RRR_0_OPCODE_X0 = 107,
- V1MZ_RRR_0_OPCODE_X1 = 67,
- V1SADAU_RRR_0_OPCODE_X0 = 108,
- V1SADU_RRR_0_OPCODE_X0 = 109,
- V1SHLI_SHIFT_OPCODE_X0 = 7,
- V1SHLI_SHIFT_OPCODE_X1 = 7,
- V1SHL_RRR_0_OPCODE_X0 = 110,
- V1SHL_RRR_0_OPCODE_X1 = 68,
- V1SHRSI_SHIFT_OPCODE_X0 = 8,
- V1SHRSI_SHIFT_OPCODE_X1 = 8,
- V1SHRS_RRR_0_OPCODE_X0 = 111,
- V1SHRS_RRR_0_OPCODE_X1 = 69,
- V1SHRUI_SHIFT_OPCODE_X0 = 9,
- V1SHRUI_SHIFT_OPCODE_X1 = 9,
- V1SHRU_RRR_0_OPCODE_X0 = 112,
- V1SHRU_RRR_0_OPCODE_X1 = 70,
- V1SUBUC_RRR_0_OPCODE_X0 = 113,
- V1SUBUC_RRR_0_OPCODE_X1 = 71,
- V1SUB_RRR_0_OPCODE_X0 = 114,
- V1SUB_RRR_0_OPCODE_X1 = 72,
- V2ADDI_IMM8_OPCODE_X0 = 14,
- V2ADDI_IMM8_OPCODE_X1 = 39,
- V2ADDSC_RRR_0_OPCODE_X0 = 115,
- V2ADDSC_RRR_0_OPCODE_X1 = 73,
- V2ADD_RRR_0_OPCODE_X0 = 116,
- V2ADD_RRR_0_OPCODE_X1 = 74,
- V2ADIFFS_RRR_0_OPCODE_X0 = 117,
- V2AVGS_RRR_0_OPCODE_X0 = 118,
- V2CMPEQI_IMM8_OPCODE_X0 = 15,
- V2CMPEQI_IMM8_OPCODE_X1 = 40,
- V2CMPEQ_RRR_0_OPCODE_X0 = 119,
- V2CMPEQ_RRR_0_OPCODE_X1 = 75,
- V2CMPLES_RRR_0_OPCODE_X0 = 120,
- V2CMPLES_RRR_0_OPCODE_X1 = 76,
- V2CMPLEU_RRR_0_OPCODE_X0 = 121,
- V2CMPLEU_RRR_0_OPCODE_X1 = 77,
- V2CMPLTSI_IMM8_OPCODE_X0 = 16,
- V2CMPLTSI_IMM8_OPCODE_X1 = 41,
- V2CMPLTS_RRR_0_OPCODE_X0 = 122,
- V2CMPLTS_RRR_0_OPCODE_X1 = 78,
- V2CMPLTUI_IMM8_OPCODE_X0 = 17,
- V2CMPLTUI_IMM8_OPCODE_X1 = 42,
- V2CMPLTU_RRR_0_OPCODE_X0 = 123,
- V2CMPLTU_RRR_0_OPCODE_X1 = 79,
- V2CMPNE_RRR_0_OPCODE_X0 = 124,
- V2CMPNE_RRR_0_OPCODE_X1 = 80,
- V2DOTPA_RRR_0_OPCODE_X0 = 125,
- V2DOTP_RRR_0_OPCODE_X0 = 126,
- V2INT_H_RRR_0_OPCODE_X0 = 127,
- V2INT_H_RRR_0_OPCODE_X1 = 81,
- V2INT_L_RRR_0_OPCODE_X0 = 128,
- V2INT_L_RRR_0_OPCODE_X1 = 82,
- V2MAXSI_IMM8_OPCODE_X0 = 18,
- V2MAXSI_IMM8_OPCODE_X1 = 43,
- V2MAXS_RRR_0_OPCODE_X0 = 129,
- V2MAXS_RRR_0_OPCODE_X1 = 83,
- V2MINSI_IMM8_OPCODE_X0 = 19,
- V2MINSI_IMM8_OPCODE_X1 = 44,
- V2MINS_RRR_0_OPCODE_X0 = 130,
- V2MINS_RRR_0_OPCODE_X1 = 84,
- V2MNZ_RRR_0_OPCODE_X0 = 131,
- V2MNZ_RRR_0_OPCODE_X1 = 85,
- V2MULFSC_RRR_0_OPCODE_X0 = 132,
- V2MULS_RRR_0_OPCODE_X0 = 133,
- V2MULTS_RRR_0_OPCODE_X0 = 134,
- V2MZ_RRR_0_OPCODE_X0 = 135,
- V2MZ_RRR_0_OPCODE_X1 = 86,
- V2PACKH_RRR_0_OPCODE_X0 = 136,
- V2PACKH_RRR_0_OPCODE_X1 = 87,
- V2PACKL_RRR_0_OPCODE_X0 = 137,
- V2PACKL_RRR_0_OPCODE_X1 = 88,
- V2PACKUC_RRR_0_OPCODE_X0 = 138,
- V2PACKUC_RRR_0_OPCODE_X1 = 89,
- V2SADAS_RRR_0_OPCODE_X0 = 139,
- V2SADAU_RRR_0_OPCODE_X0 = 140,
- V2SADS_RRR_0_OPCODE_X0 = 141,
- V2SADU_RRR_0_OPCODE_X0 = 142,
- V2SHLI_SHIFT_OPCODE_X0 = 10,
- V2SHLI_SHIFT_OPCODE_X1 = 10,
- V2SHLSC_RRR_0_OPCODE_X0 = 143,
- V2SHLSC_RRR_0_OPCODE_X1 = 90,
- V2SHL_RRR_0_OPCODE_X0 = 144,
- V2SHL_RRR_0_OPCODE_X1 = 91,
- V2SHRSI_SHIFT_OPCODE_X0 = 11,
- V2SHRSI_SHIFT_OPCODE_X1 = 11,
- V2SHRS_RRR_0_OPCODE_X0 = 145,
- V2SHRS_RRR_0_OPCODE_X1 = 92,
- V2SHRUI_SHIFT_OPCODE_X0 = 12,
- V2SHRUI_SHIFT_OPCODE_X1 = 12,
- V2SHRU_RRR_0_OPCODE_X0 = 146,
- V2SHRU_RRR_0_OPCODE_X1 = 93,
- V2SUBSC_RRR_0_OPCODE_X0 = 147,
- V2SUBSC_RRR_0_OPCODE_X1 = 94,
- V2SUB_RRR_0_OPCODE_X0 = 148,
- V2SUB_RRR_0_OPCODE_X1 = 95,
- V4ADDSC_RRR_0_OPCODE_X0 = 149,
- V4ADDSC_RRR_0_OPCODE_X1 = 96,
- V4ADD_RRR_0_OPCODE_X0 = 150,
- V4ADD_RRR_0_OPCODE_X1 = 97,
- V4INT_H_RRR_0_OPCODE_X0 = 151,
- V4INT_H_RRR_0_OPCODE_X1 = 98,
- V4INT_L_RRR_0_OPCODE_X0 = 152,
- V4INT_L_RRR_0_OPCODE_X1 = 99,
- V4PACKSC_RRR_0_OPCODE_X0 = 153,
- V4PACKSC_RRR_0_OPCODE_X1 = 100,
- V4SHLSC_RRR_0_OPCODE_X0 = 154,
- V4SHLSC_RRR_0_OPCODE_X1 = 101,
- V4SHL_RRR_0_OPCODE_X0 = 155,
- V4SHL_RRR_0_OPCODE_X1 = 102,
- V4SHRS_RRR_0_OPCODE_X0 = 156,
- V4SHRS_RRR_0_OPCODE_X1 = 103,
- V4SHRU_RRR_0_OPCODE_X0 = 157,
- V4SHRU_RRR_0_OPCODE_X1 = 104,
- V4SUBSC_RRR_0_OPCODE_X0 = 158,
- V4SUBSC_RRR_0_OPCODE_X1 = 105,
- V4SUB_RRR_0_OPCODE_X0 = 159,
- V4SUB_RRR_0_OPCODE_X1 = 106,
- WH64_UNARY_OPCODE_X1 = 38,
- XORI_IMM8_OPCODE_X0 = 20,
- XORI_IMM8_OPCODE_X1 = 45,
- XOR_RRR_0_OPCODE_X0 = 160,
- XOR_RRR_0_OPCODE_X1 = 107,
- XOR_RRR_5_OPCODE_Y0 = 3,
- XOR_RRR_5_OPCODE_Y1 = 3
-};
-
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __ARCH_OPCODE_H__ */
diff --git a/arch/tile/include/uapi/arch/opcode_tilepro.h b/arch/tile/include/uapi/arch/opcode_tilepro.h
deleted file mode 100644
index 0d633688de63..000000000000
--- a/arch/tile/include/uapi/arch/opcode_tilepro.h
+++ /dev/null
@@ -1,1473 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/* TILEPro opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-#ifndef __ARCH_OPCODE_H__
-#define __ARCH_OPCODE_H__
-
-#ifndef __ASSEMBLER__
-
-typedef unsigned long long tilepro_bundle_bits;
-
-/* This is the bit that determines if a bundle is in the Y encoding. */
-#define TILEPRO_BUNDLE_Y_ENCODING_MASK ((tilepro_bundle_bits)1 << 63)
-
-enum
-{
- /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
- TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
-
- /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
- TILEPRO_NUM_PIPELINE_ENCODINGS = 5,
-
- /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */
- TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
-
- /* Instructions take this many bytes. */
- TILEPRO_BUNDLE_SIZE_IN_BYTES = 1 << TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES,
-
- /* Log base 2 of TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES. */
- TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
-
- /* Bundles should be aligned modulo this number of bytes. */
- TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES =
- (1 << TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
-
- /* Log base 2 of TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES. */
- TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
-
- /* Static network instructions take this many bytes. */
- TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES =
- (1 << TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
-
- /* Number of registers (some are magic, such as network I/O). */
- TILEPRO_NUM_REGISTERS = 64,
-
- /* Number of static network registers. */
- TILEPRO_NUM_SN_REGISTERS = 4
-};
-
-/* Make a few "tile_" variables to simplify common code between
- architectures. */
-
-typedef tilepro_bundle_bits tile_bundle_bits;
-#define TILE_BUNDLE_SIZE_IN_BYTES TILEPRO_BUNDLE_SIZE_IN_BYTES
-#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
- TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
-#define TILE_BPT_BUNDLE TILEPRO_BPT_BUNDLE
-
-/* 64-bit pattern for a { bpt ; nop } bundle. */
-#define TILEPRO_BPT_BUNDLE 0x400b3cae70166000ULL
-
-static __inline unsigned int
-get_BrOff_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_BrOff_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000);
-}
-
-static __inline unsigned int
-get_BrType_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0xf);
-}
-
-static __inline unsigned int
-get_Dest_Imm8_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 43)) & 0x000000c0);
-}
-
-static __inline unsigned int
-get_Dest_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 2)) & 0x3);
-}
-
-static __inline unsigned int
-get_Dest_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Dest_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Imm16_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm16_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xffff);
-}
-
-static __inline unsigned int
-get_Imm8_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0xff);
-}
-
-static __inline unsigned int
-get_ImmOpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0x7f);
-}
-
-static __inline unsigned int
-get_ImmOpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 51)) & 0x7f);
-}
-
-static __inline unsigned int
-get_ImmRROpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 8)) & 0x3);
-}
-
-static __inline unsigned int
-get_JOffLong_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000) |
- (((unsigned int)(n >> 14)) & 0x001e0000) |
- (((unsigned int)(n >> 16)) & 0x07e00000) |
- (((unsigned int)(n >> 31)) & 0x18000000);
-}
-
-static __inline unsigned int
-get_JOff_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000) |
- (((unsigned int)(n >> 14)) & 0x001e0000) |
- (((unsigned int)(n >> 16)) & 0x07e00000) |
- (((unsigned int)(n >> 31)) & 0x08000000);
-}
-
-static __inline unsigned int
-get_MF_Imm15_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x00003fff) |
- (((unsigned int)(n >> 44)) & 0x00004000);
-}
-
-static __inline unsigned int
-get_MMEnd_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMEnd_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMStart_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 23)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMStart_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 54)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MT_Imm15_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 37)) & 0x00003fc0) |
- (((unsigned int)(n >> 44)) & 0x00004000);
-}
-
-static __inline unsigned int
-get_Mode(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 63)) & 0x1);
-}
-
-static __inline unsigned int
-get_NoRegOpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 10)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Opcode_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 28)) & 0x7);
-}
-
-static __inline unsigned int
-get_Opcode_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 59)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 27)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 59)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_Y2(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 56)) & 0x7);
-}
-
-static __inline unsigned int
-get_RROpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 4)) & 0xf);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x1ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x1ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x3);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x3);
-}
-
-static __inline unsigned int
-get_RouteOpcodeExtension_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_S_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 27)) & 0x1);
-}
-
-static __inline unsigned int
-get_S_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 58)) & 0x1);
-}
-
-static __inline unsigned int
-get_ShAmt_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_ShAmt_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_ShAmt_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_SrcA_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 6)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcA_Y2(tilepro_bundle_bits n)
-{
- return (((n >> 26)) & 0x00000001) |
- (((unsigned int)(n >> 50)) & 0x0000003e);
-}
-
-static __inline unsigned int
-get_SrcBDest_Y2(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x3f);
-}
-
-static __inline unsigned int
-get_SrcB_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Src_SN(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_X0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 17)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_X1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 48)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_Y0(tilepro_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 17)) & 0x7);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_Y1(tilepro_bundle_bits n)
-{
- return (((unsigned int)(n >> 48)) & 0x7);
-}
-
-
-static __inline int
-sign_extend(int n, int num_bits)
-{
- int shift = (int)(sizeof(int) * 8 - num_bits);
- return (n << shift) >> shift;
-}
-
-
-
-static __inline tilepro_bundle_bits
-create_BrOff_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_BrOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tilepro_bundle_bits)(n & 0x00018000)) << 20);
-}
-
-static __inline tilepro_bundle_bits
-create_BrType_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xf)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilepro_bundle_bits)(n & 0x000000c0)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 2);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Dest_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm16_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xffff) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm16_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xffff)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_Imm8_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_ImmOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7f) << 20);
-}
-
-static __inline tilepro_bundle_bits
-create_ImmOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x7f)) << 51);
-}
-
-static __inline tilepro_bundle_bits
-create_ImmRROpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 8);
-}
-
-static __inline tilepro_bundle_bits
-create_JOffLong_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tilepro_bundle_bits)(n & 0x00018000)) << 20) |
- (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) |
- (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) |
- (((tilepro_bundle_bits)(n & 0x18000000)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_JOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tilepro_bundle_bits)(n & 0x00018000)) << 20) |
- (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) |
- (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) |
- (((tilepro_bundle_bits)(n & 0x08000000)) << 31);
-}
-
-static __inline tilepro_bundle_bits
-create_MF_Imm15_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x00003fff)) << 37) |
- (((tilepro_bundle_bits)(n & 0x00004000)) << 44);
-}
-
-static __inline tilepro_bundle_bits
-create_MMEnd_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 18);
-}
-
-static __inline tilepro_bundle_bits
-create_MMEnd_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 49);
-}
-
-static __inline tilepro_bundle_bits
-create_MMStart_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 23);
-}
-
-static __inline tilepro_bundle_bits
-create_MMStart_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 54);
-}
-
-static __inline tilepro_bundle_bits
-create_MT_Imm15_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tilepro_bundle_bits)(n & 0x00003fc0)) << 37) |
- (((tilepro_bundle_bits)(n & 0x00004000)) << 44);
-}
-
-static __inline tilepro_bundle_bits
-create_Mode(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1)) << 63);
-}
-
-static __inline tilepro_bundle_bits
-create_NoRegOpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 10);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7) << 28);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xf)) << 59);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 27);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0xf)) << 59);
-}
-
-static __inline tilepro_bundle_bits
-create_Opcode_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x7)) << 56);
-}
-
-static __inline tilepro_bundle_bits
-create_RROpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 4);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1ff) << 18);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1ff)) << 49);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 18);
-}
-
-static __inline tilepro_bundle_bits
-create_RRROpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3)) << 49);
-}
-
-static __inline tilepro_bundle_bits
-create_RouteOpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_S_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1) << 27);
-}
-
-static __inline tilepro_bundle_bits
-create_S_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1)) << 58);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_ShAmt_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 6);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 37);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcA_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x00000001) << 26) |
- (((tilepro_bundle_bits)(n & 0x0000003e)) << 50);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcBDest_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 20);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_SrcB_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_Src_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 0);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
-}
-
-static __inline tilepro_bundle_bits
-create_UnOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 17);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x3ff)) << 48);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7) << 17);
-}
-
-static __inline tilepro_bundle_bits
-create_UnShOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tilepro_bundle_bits)(n & 0x7)) << 48);
-}
-
-
-enum
-{
- ADDBS_U_SPECIAL_0_OPCODE_X0 = 98,
- ADDBS_U_SPECIAL_0_OPCODE_X1 = 68,
- ADDB_SPECIAL_0_OPCODE_X0 = 1,
- ADDB_SPECIAL_0_OPCODE_X1 = 1,
- ADDHS_SPECIAL_0_OPCODE_X0 = 99,
- ADDHS_SPECIAL_0_OPCODE_X1 = 69,
- ADDH_SPECIAL_0_OPCODE_X0 = 2,
- ADDH_SPECIAL_0_OPCODE_X1 = 2,
- ADDIB_IMM_0_OPCODE_X0 = 1,
- ADDIB_IMM_0_OPCODE_X1 = 1,
- ADDIH_IMM_0_OPCODE_X0 = 2,
- ADDIH_IMM_0_OPCODE_X1 = 2,
- ADDI_IMM_0_OPCODE_X0 = 3,
- ADDI_IMM_0_OPCODE_X1 = 3,
- ADDI_IMM_1_OPCODE_SN = 1,
- ADDI_OPCODE_Y0 = 9,
- ADDI_OPCODE_Y1 = 7,
- ADDLIS_OPCODE_X0 = 1,
- ADDLIS_OPCODE_X1 = 2,
- ADDLI_OPCODE_X0 = 2,
- ADDLI_OPCODE_X1 = 3,
- ADDS_SPECIAL_0_OPCODE_X0 = 96,
- ADDS_SPECIAL_0_OPCODE_X1 = 66,
- ADD_SPECIAL_0_OPCODE_X0 = 3,
- ADD_SPECIAL_0_OPCODE_X1 = 3,
- ADD_SPECIAL_0_OPCODE_Y0 = 0,
- ADD_SPECIAL_0_OPCODE_Y1 = 0,
- ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4,
- ADIFFH_SPECIAL_0_OPCODE_X0 = 5,
- ANDI_IMM_0_OPCODE_X0 = 1,
- ANDI_IMM_0_OPCODE_X1 = 4,
- ANDI_OPCODE_Y0 = 10,
- ANDI_OPCODE_Y1 = 8,
- AND_SPECIAL_0_OPCODE_X0 = 6,
- AND_SPECIAL_0_OPCODE_X1 = 4,
- AND_SPECIAL_2_OPCODE_Y0 = 0,
- AND_SPECIAL_2_OPCODE_Y1 = 0,
- AULI_OPCODE_X0 = 3,
- AULI_OPCODE_X1 = 4,
- AVGB_U_SPECIAL_0_OPCODE_X0 = 7,
- AVGH_SPECIAL_0_OPCODE_X0 = 8,
- BBNST_BRANCH_OPCODE_X1 = 15,
- BBNS_BRANCH_OPCODE_X1 = 14,
- BBNS_OPCODE_SN = 63,
- BBST_BRANCH_OPCODE_X1 = 13,
- BBS_BRANCH_OPCODE_X1 = 12,
- BBS_OPCODE_SN = 62,
- BGEZT_BRANCH_OPCODE_X1 = 7,
- BGEZ_BRANCH_OPCODE_X1 = 6,
- BGEZ_OPCODE_SN = 61,
- BGZT_BRANCH_OPCODE_X1 = 5,
- BGZ_BRANCH_OPCODE_X1 = 4,
- BGZ_OPCODE_SN = 58,
- BITX_UN_0_SHUN_0_OPCODE_X0 = 1,
- BITX_UN_0_SHUN_0_OPCODE_Y0 = 1,
- BLEZT_BRANCH_OPCODE_X1 = 11,
- BLEZ_BRANCH_OPCODE_X1 = 10,
- BLEZ_OPCODE_SN = 59,
- BLZT_BRANCH_OPCODE_X1 = 9,
- BLZ_BRANCH_OPCODE_X1 = 8,
- BLZ_OPCODE_SN = 60,
- BNZT_BRANCH_OPCODE_X1 = 3,
- BNZ_BRANCH_OPCODE_X1 = 2,
- BNZ_OPCODE_SN = 57,
- BPT_NOREG_RR_IMM_0_OPCODE_SN = 1,
- BRANCH_OPCODE_X1 = 5,
- BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2,
- BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2,
- BZT_BRANCH_OPCODE_X1 = 1,
- BZ_BRANCH_OPCODE_X1 = 0,
- BZ_OPCODE_SN = 56,
- CLZ_UN_0_SHUN_0_OPCODE_X0 = 3,
- CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3,
- CRC32_32_SPECIAL_0_OPCODE_X0 = 9,
- CRC32_8_SPECIAL_0_OPCODE_X0 = 10,
- CTZ_UN_0_SHUN_0_OPCODE_X0 = 4,
- CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4,
- DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1,
- DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2,
- DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95,
- FINV_UN_0_SHUN_0_OPCODE_X1 = 3,
- FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4,
- FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3,
- FNOP_UN_0_SHUN_0_OPCODE_X0 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_X1 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1,
- HALT_NOREG_RR_IMM_0_OPCODE_SN = 0,
- ICOH_UN_0_SHUN_0_OPCODE_X1 = 6,
- ILL_UN_0_SHUN_0_OPCODE_X1 = 7,
- ILL_UN_0_SHUN_0_OPCODE_Y1 = 2,
- IMM_0_OPCODE_SN = 0,
- IMM_0_OPCODE_X0 = 4,
- IMM_0_OPCODE_X1 = 6,
- IMM_1_OPCODE_SN = 1,
- IMM_OPCODE_0_X0 = 5,
- INTHB_SPECIAL_0_OPCODE_X0 = 11,
- INTHB_SPECIAL_0_OPCODE_X1 = 5,
- INTHH_SPECIAL_0_OPCODE_X0 = 12,
- INTHH_SPECIAL_0_OPCODE_X1 = 6,
- INTLB_SPECIAL_0_OPCODE_X0 = 13,
- INTLB_SPECIAL_0_OPCODE_X1 = 7,
- INTLH_SPECIAL_0_OPCODE_X0 = 14,
- INTLH_SPECIAL_0_OPCODE_X1 = 8,
- INV_UN_0_SHUN_0_OPCODE_X1 = 8,
- IRET_UN_0_SHUN_0_OPCODE_X1 = 9,
- JALB_OPCODE_X1 = 13,
- JALF_OPCODE_X1 = 12,
- JALRP_SPECIAL_0_OPCODE_X1 = 9,
- JALRR_IMM_1_OPCODE_SN = 3,
- JALR_RR_IMM_0_OPCODE_SN = 5,
- JALR_SPECIAL_0_OPCODE_X1 = 10,
- JB_OPCODE_X1 = 11,
- JF_OPCODE_X1 = 10,
- JRP_SPECIAL_0_OPCODE_X1 = 11,
- JRR_IMM_1_OPCODE_SN = 2,
- JR_RR_IMM_0_OPCODE_SN = 4,
- JR_SPECIAL_0_OPCODE_X1 = 12,
- LBADD_IMM_0_OPCODE_X1 = 22,
- LBADD_U_IMM_0_OPCODE_X1 = 23,
- LB_OPCODE_Y2 = 0,
- LB_UN_0_SHUN_0_OPCODE_X1 = 10,
- LB_U_OPCODE_Y2 = 1,
- LB_U_UN_0_SHUN_0_OPCODE_X1 = 11,
- LHADD_IMM_0_OPCODE_X1 = 24,
- LHADD_U_IMM_0_OPCODE_X1 = 25,
- LH_OPCODE_Y2 = 2,
- LH_UN_0_SHUN_0_OPCODE_X1 = 12,
- LH_U_OPCODE_Y2 = 3,
- LH_U_UN_0_SHUN_0_OPCODE_X1 = 13,
- LNK_SPECIAL_0_OPCODE_X1 = 13,
- LWADD_IMM_0_OPCODE_X1 = 26,
- LWADD_NA_IMM_0_OPCODE_X1 = 27,
- LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24,
- LW_OPCODE_Y2 = 4,
- LW_UN_0_SHUN_0_OPCODE_X1 = 14,
- MAXB_U_SPECIAL_0_OPCODE_X0 = 15,
- MAXB_U_SPECIAL_0_OPCODE_X1 = 14,
- MAXH_SPECIAL_0_OPCODE_X0 = 16,
- MAXH_SPECIAL_0_OPCODE_X1 = 15,
- MAXIB_U_IMM_0_OPCODE_X0 = 4,
- MAXIB_U_IMM_0_OPCODE_X1 = 5,
- MAXIH_IMM_0_OPCODE_X0 = 5,
- MAXIH_IMM_0_OPCODE_X1 = 6,
- MFSPR_IMM_0_OPCODE_X1 = 7,
- MF_UN_0_SHUN_0_OPCODE_X1 = 15,
- MINB_U_SPECIAL_0_OPCODE_X0 = 17,
- MINB_U_SPECIAL_0_OPCODE_X1 = 16,
- MINH_SPECIAL_0_OPCODE_X0 = 18,
- MINH_SPECIAL_0_OPCODE_X1 = 17,
- MINIB_U_IMM_0_OPCODE_X0 = 6,
- MINIB_U_IMM_0_OPCODE_X1 = 8,
- MINIH_IMM_0_OPCODE_X0 = 7,
- MINIH_IMM_0_OPCODE_X1 = 9,
- MM_OPCODE_X0 = 6,
- MM_OPCODE_X1 = 7,
- MNZB_SPECIAL_0_OPCODE_X0 = 19,
- MNZB_SPECIAL_0_OPCODE_X1 = 18,
- MNZH_SPECIAL_0_OPCODE_X0 = 20,
- MNZH_SPECIAL_0_OPCODE_X1 = 19,
- MNZ_SPECIAL_0_OPCODE_X0 = 21,
- MNZ_SPECIAL_0_OPCODE_X1 = 20,
- MNZ_SPECIAL_1_OPCODE_Y0 = 0,
- MNZ_SPECIAL_1_OPCODE_Y1 = 1,
- MOVEI_IMM_1_OPCODE_SN = 0,
- MOVE_RR_IMM_0_OPCODE_SN = 8,
- MTSPR_IMM_0_OPCODE_X1 = 10,
- MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22,
- MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0,
- MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23,
- MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24,
- MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1,
- MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25,
- MULHH_SS_SPECIAL_0_OPCODE_X0 = 26,
- MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0,
- MULHH_SU_SPECIAL_0_OPCODE_X0 = 27,
- MULHH_UU_SPECIAL_0_OPCODE_X0 = 28,
- MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1,
- MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29,
- MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30,
- MULHLA_US_SPECIAL_0_OPCODE_X0 = 31,
- MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32,
- MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33,
- MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0,
- MULHL_SS_SPECIAL_0_OPCODE_X0 = 34,
- MULHL_SU_SPECIAL_0_OPCODE_X0 = 35,
- MULHL_US_SPECIAL_0_OPCODE_X0 = 36,
- MULHL_UU_SPECIAL_0_OPCODE_X0 = 37,
- MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38,
- MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2,
- MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39,
- MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40,
- MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3,
- MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41,
- MULLL_SS_SPECIAL_0_OPCODE_X0 = 42,
- MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2,
- MULLL_SU_SPECIAL_0_OPCODE_X0 = 43,
- MULLL_UU_SPECIAL_0_OPCODE_X0 = 44,
- MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3,
- MVNZ_SPECIAL_0_OPCODE_X0 = 45,
- MVNZ_SPECIAL_1_OPCODE_Y0 = 1,
- MVZ_SPECIAL_0_OPCODE_X0 = 46,
- MVZ_SPECIAL_1_OPCODE_Y0 = 2,
- MZB_SPECIAL_0_OPCODE_X0 = 47,
- MZB_SPECIAL_0_OPCODE_X1 = 21,
- MZH_SPECIAL_0_OPCODE_X0 = 48,
- MZH_SPECIAL_0_OPCODE_X1 = 22,
- MZ_SPECIAL_0_OPCODE_X0 = 49,
- MZ_SPECIAL_0_OPCODE_X1 = 23,
- MZ_SPECIAL_1_OPCODE_Y0 = 3,
- MZ_SPECIAL_1_OPCODE_Y1 = 2,
- NAP_UN_0_SHUN_0_OPCODE_X1 = 16,
- NOP_NOREG_RR_IMM_0_OPCODE_SN = 2,
- NOP_UN_0_SHUN_0_OPCODE_X0 = 6,
- NOP_UN_0_SHUN_0_OPCODE_X1 = 17,
- NOP_UN_0_SHUN_0_OPCODE_Y0 = 6,
- NOP_UN_0_SHUN_0_OPCODE_Y1 = 3,
- NOREG_RR_IMM_0_OPCODE_SN = 0,
- NOR_SPECIAL_0_OPCODE_X0 = 50,
- NOR_SPECIAL_0_OPCODE_X1 = 24,
- NOR_SPECIAL_2_OPCODE_Y0 = 1,
- NOR_SPECIAL_2_OPCODE_Y1 = 1,
- ORI_IMM_0_OPCODE_X0 = 8,
- ORI_IMM_0_OPCODE_X1 = 11,
- ORI_OPCODE_Y0 = 11,
- ORI_OPCODE_Y1 = 9,
- OR_SPECIAL_0_OPCODE_X0 = 51,
- OR_SPECIAL_0_OPCODE_X1 = 25,
- OR_SPECIAL_2_OPCODE_Y0 = 2,
- OR_SPECIAL_2_OPCODE_Y1 = 2,
- PACKBS_U_SPECIAL_0_OPCODE_X0 = 103,
- PACKBS_U_SPECIAL_0_OPCODE_X1 = 73,
- PACKHB_SPECIAL_0_OPCODE_X0 = 52,
- PACKHB_SPECIAL_0_OPCODE_X1 = 26,
- PACKHS_SPECIAL_0_OPCODE_X0 = 102,
- PACKHS_SPECIAL_0_OPCODE_X1 = 72,
- PACKLB_SPECIAL_0_OPCODE_X0 = 53,
- PACKLB_SPECIAL_0_OPCODE_X1 = 27,
- PCNT_UN_0_SHUN_0_OPCODE_X0 = 7,
- PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7,
- RLI_SHUN_0_OPCODE_X0 = 1,
- RLI_SHUN_0_OPCODE_X1 = 1,
- RLI_SHUN_0_OPCODE_Y0 = 1,
- RLI_SHUN_0_OPCODE_Y1 = 1,
- RL_SPECIAL_0_OPCODE_X0 = 54,
- RL_SPECIAL_0_OPCODE_X1 = 28,
- RL_SPECIAL_3_OPCODE_Y0 = 0,
- RL_SPECIAL_3_OPCODE_Y1 = 0,
- RR_IMM_0_OPCODE_SN = 0,
- S1A_SPECIAL_0_OPCODE_X0 = 55,
- S1A_SPECIAL_0_OPCODE_X1 = 29,
- S1A_SPECIAL_0_OPCODE_Y0 = 1,
- S1A_SPECIAL_0_OPCODE_Y1 = 1,
- S2A_SPECIAL_0_OPCODE_X0 = 56,
- S2A_SPECIAL_0_OPCODE_X1 = 30,
- S2A_SPECIAL_0_OPCODE_Y0 = 2,
- S2A_SPECIAL_0_OPCODE_Y1 = 2,
- S3A_SPECIAL_0_OPCODE_X0 = 57,
- S3A_SPECIAL_0_OPCODE_X1 = 31,
- S3A_SPECIAL_5_OPCODE_Y0 = 1,
- S3A_SPECIAL_5_OPCODE_Y1 = 1,
- SADAB_U_SPECIAL_0_OPCODE_X0 = 58,
- SADAH_SPECIAL_0_OPCODE_X0 = 59,
- SADAH_U_SPECIAL_0_OPCODE_X0 = 60,
- SADB_U_SPECIAL_0_OPCODE_X0 = 61,
- SADH_SPECIAL_0_OPCODE_X0 = 62,
- SADH_U_SPECIAL_0_OPCODE_X0 = 63,
- SBADD_IMM_0_OPCODE_X1 = 28,
- SB_OPCODE_Y2 = 5,
- SB_SPECIAL_0_OPCODE_X1 = 32,
- SEQB_SPECIAL_0_OPCODE_X0 = 64,
- SEQB_SPECIAL_0_OPCODE_X1 = 33,
- SEQH_SPECIAL_0_OPCODE_X0 = 65,
- SEQH_SPECIAL_0_OPCODE_X1 = 34,
- SEQIB_IMM_0_OPCODE_X0 = 9,
- SEQIB_IMM_0_OPCODE_X1 = 12,
- SEQIH_IMM_0_OPCODE_X0 = 10,
- SEQIH_IMM_0_OPCODE_X1 = 13,
- SEQI_IMM_0_OPCODE_X0 = 11,
- SEQI_IMM_0_OPCODE_X1 = 14,
- SEQI_OPCODE_Y0 = 12,
- SEQI_OPCODE_Y1 = 10,
- SEQ_SPECIAL_0_OPCODE_X0 = 66,
- SEQ_SPECIAL_0_OPCODE_X1 = 35,
- SEQ_SPECIAL_5_OPCODE_Y0 = 2,
- SEQ_SPECIAL_5_OPCODE_Y1 = 2,
- SHADD_IMM_0_OPCODE_X1 = 29,
- SHL8II_IMM_0_OPCODE_SN = 3,
- SHLB_SPECIAL_0_OPCODE_X0 = 67,
- SHLB_SPECIAL_0_OPCODE_X1 = 36,
- SHLH_SPECIAL_0_OPCODE_X0 = 68,
- SHLH_SPECIAL_0_OPCODE_X1 = 37,
- SHLIB_SHUN_0_OPCODE_X0 = 2,
- SHLIB_SHUN_0_OPCODE_X1 = 2,
- SHLIH_SHUN_0_OPCODE_X0 = 3,
- SHLIH_SHUN_0_OPCODE_X1 = 3,
- SHLI_SHUN_0_OPCODE_X0 = 4,
- SHLI_SHUN_0_OPCODE_X1 = 4,
- SHLI_SHUN_0_OPCODE_Y0 = 2,
- SHLI_SHUN_0_OPCODE_Y1 = 2,
- SHL_SPECIAL_0_OPCODE_X0 = 69,
- SHL_SPECIAL_0_OPCODE_X1 = 38,
- SHL_SPECIAL_3_OPCODE_Y0 = 1,
- SHL_SPECIAL_3_OPCODE_Y1 = 1,
- SHR1_RR_IMM_0_OPCODE_SN = 9,
- SHRB_SPECIAL_0_OPCODE_X0 = 70,
- SHRB_SPECIAL_0_OPCODE_X1 = 39,
- SHRH_SPECIAL_0_OPCODE_X0 = 71,
- SHRH_SPECIAL_0_OPCODE_X1 = 40,
- SHRIB_SHUN_0_OPCODE_X0 = 5,
- SHRIB_SHUN_0_OPCODE_X1 = 5,
- SHRIH_SHUN_0_OPCODE_X0 = 6,
- SHRIH_SHUN_0_OPCODE_X1 = 6,
- SHRI_SHUN_0_OPCODE_X0 = 7,
- SHRI_SHUN_0_OPCODE_X1 = 7,
- SHRI_SHUN_0_OPCODE_Y0 = 3,
- SHRI_SHUN_0_OPCODE_Y1 = 3,
- SHR_SPECIAL_0_OPCODE_X0 = 72,
- SHR_SPECIAL_0_OPCODE_X1 = 41,
- SHR_SPECIAL_3_OPCODE_Y0 = 2,
- SHR_SPECIAL_3_OPCODE_Y1 = 2,
- SHUN_0_OPCODE_X0 = 7,
- SHUN_0_OPCODE_X1 = 8,
- SHUN_0_OPCODE_Y0 = 13,
- SHUN_0_OPCODE_Y1 = 11,
- SH_OPCODE_Y2 = 6,
- SH_SPECIAL_0_OPCODE_X1 = 42,
- SLTB_SPECIAL_0_OPCODE_X0 = 73,
- SLTB_SPECIAL_0_OPCODE_X1 = 43,
- SLTB_U_SPECIAL_0_OPCODE_X0 = 74,
- SLTB_U_SPECIAL_0_OPCODE_X1 = 44,
- SLTEB_SPECIAL_0_OPCODE_X0 = 75,
- SLTEB_SPECIAL_0_OPCODE_X1 = 45,
- SLTEB_U_SPECIAL_0_OPCODE_X0 = 76,
- SLTEB_U_SPECIAL_0_OPCODE_X1 = 46,
- SLTEH_SPECIAL_0_OPCODE_X0 = 77,
- SLTEH_SPECIAL_0_OPCODE_X1 = 47,
- SLTEH_U_SPECIAL_0_OPCODE_X0 = 78,
- SLTEH_U_SPECIAL_0_OPCODE_X1 = 48,
- SLTE_SPECIAL_0_OPCODE_X0 = 79,
- SLTE_SPECIAL_0_OPCODE_X1 = 49,
- SLTE_SPECIAL_4_OPCODE_Y0 = 0,
- SLTE_SPECIAL_4_OPCODE_Y1 = 0,
- SLTE_U_SPECIAL_0_OPCODE_X0 = 80,
- SLTE_U_SPECIAL_0_OPCODE_X1 = 50,
- SLTE_U_SPECIAL_4_OPCODE_Y0 = 1,
- SLTE_U_SPECIAL_4_OPCODE_Y1 = 1,
- SLTH_SPECIAL_0_OPCODE_X0 = 81,
- SLTH_SPECIAL_0_OPCODE_X1 = 51,
- SLTH_U_SPECIAL_0_OPCODE_X0 = 82,
- SLTH_U_SPECIAL_0_OPCODE_X1 = 52,
- SLTIB_IMM_0_OPCODE_X0 = 12,
- SLTIB_IMM_0_OPCODE_X1 = 15,
- SLTIB_U_IMM_0_OPCODE_X0 = 13,
- SLTIB_U_IMM_0_OPCODE_X1 = 16,
- SLTIH_IMM_0_OPCODE_X0 = 14,
- SLTIH_IMM_0_OPCODE_X1 = 17,
- SLTIH_U_IMM_0_OPCODE_X0 = 15,
- SLTIH_U_IMM_0_OPCODE_X1 = 18,
- SLTI_IMM_0_OPCODE_X0 = 16,
- SLTI_IMM_0_OPCODE_X1 = 19,
- SLTI_OPCODE_Y0 = 14,
- SLTI_OPCODE_Y1 = 12,
- SLTI_U_IMM_0_OPCODE_X0 = 17,
- SLTI_U_IMM_0_OPCODE_X1 = 20,
- SLTI_U_OPCODE_Y0 = 15,
- SLTI_U_OPCODE_Y1 = 13,
- SLT_SPECIAL_0_OPCODE_X0 = 83,
- SLT_SPECIAL_0_OPCODE_X1 = 53,
- SLT_SPECIAL_4_OPCODE_Y0 = 2,
- SLT_SPECIAL_4_OPCODE_Y1 = 2,
- SLT_U_SPECIAL_0_OPCODE_X0 = 84,
- SLT_U_SPECIAL_0_OPCODE_X1 = 54,
- SLT_U_SPECIAL_4_OPCODE_Y0 = 3,
- SLT_U_SPECIAL_4_OPCODE_Y1 = 3,
- SNEB_SPECIAL_0_OPCODE_X0 = 85,
- SNEB_SPECIAL_0_OPCODE_X1 = 55,
- SNEH_SPECIAL_0_OPCODE_X0 = 86,
- SNEH_SPECIAL_0_OPCODE_X1 = 56,
- SNE_SPECIAL_0_OPCODE_X0 = 87,
- SNE_SPECIAL_0_OPCODE_X1 = 57,
- SNE_SPECIAL_5_OPCODE_Y0 = 3,
- SNE_SPECIAL_5_OPCODE_Y1 = 3,
- SPECIAL_0_OPCODE_X0 = 0,
- SPECIAL_0_OPCODE_X1 = 1,
- SPECIAL_0_OPCODE_Y0 = 1,
- SPECIAL_0_OPCODE_Y1 = 1,
- SPECIAL_1_OPCODE_Y0 = 2,
- SPECIAL_1_OPCODE_Y1 = 2,
- SPECIAL_2_OPCODE_Y0 = 3,
- SPECIAL_2_OPCODE_Y1 = 3,
- SPECIAL_3_OPCODE_Y0 = 4,
- SPECIAL_3_OPCODE_Y1 = 4,
- SPECIAL_4_OPCODE_Y0 = 5,
- SPECIAL_4_OPCODE_Y1 = 5,
- SPECIAL_5_OPCODE_Y0 = 6,
- SPECIAL_5_OPCODE_Y1 = 6,
- SPECIAL_6_OPCODE_Y0 = 7,
- SPECIAL_7_OPCODE_Y0 = 8,
- SRAB_SPECIAL_0_OPCODE_X0 = 88,
- SRAB_SPECIAL_0_OPCODE_X1 = 58,
- SRAH_SPECIAL_0_OPCODE_X0 = 89,
- SRAH_SPECIAL_0_OPCODE_X1 = 59,
- SRAIB_SHUN_0_OPCODE_X0 = 8,
- SRAIB_SHUN_0_OPCODE_X1 = 8,
- SRAIH_SHUN_0_OPCODE_X0 = 9,
- SRAIH_SHUN_0_OPCODE_X1 = 9,
- SRAI_SHUN_0_OPCODE_X0 = 10,
- SRAI_SHUN_0_OPCODE_X1 = 10,
- SRAI_SHUN_0_OPCODE_Y0 = 4,
- SRAI_SHUN_0_OPCODE_Y1 = 4,
- SRA_SPECIAL_0_OPCODE_X0 = 90,
- SRA_SPECIAL_0_OPCODE_X1 = 60,
- SRA_SPECIAL_3_OPCODE_Y0 = 3,
- SRA_SPECIAL_3_OPCODE_Y1 = 3,
- SUBBS_U_SPECIAL_0_OPCODE_X0 = 100,
- SUBBS_U_SPECIAL_0_OPCODE_X1 = 70,
- SUBB_SPECIAL_0_OPCODE_X0 = 91,
- SUBB_SPECIAL_0_OPCODE_X1 = 61,
- SUBHS_SPECIAL_0_OPCODE_X0 = 101,
- SUBHS_SPECIAL_0_OPCODE_X1 = 71,
- SUBH_SPECIAL_0_OPCODE_X0 = 92,
- SUBH_SPECIAL_0_OPCODE_X1 = 62,
- SUBS_SPECIAL_0_OPCODE_X0 = 97,
- SUBS_SPECIAL_0_OPCODE_X1 = 67,
- SUB_SPECIAL_0_OPCODE_X0 = 93,
- SUB_SPECIAL_0_OPCODE_X1 = 63,
- SUB_SPECIAL_0_OPCODE_Y0 = 3,
- SUB_SPECIAL_0_OPCODE_Y1 = 3,
- SWADD_IMM_0_OPCODE_X1 = 30,
- SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18,
- SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19,
- SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20,
- SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21,
- SW_OPCODE_Y2 = 7,
- SW_SPECIAL_0_OPCODE_X1 = 64,
- TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8,
- TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8,
- TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9,
- TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9,
- TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10,
- TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10,
- TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11,
- TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11,
- TNS_UN_0_SHUN_0_OPCODE_X1 = 22,
- UN_0_SHUN_0_OPCODE_X0 = 11,
- UN_0_SHUN_0_OPCODE_X1 = 11,
- UN_0_SHUN_0_OPCODE_Y0 = 5,
- UN_0_SHUN_0_OPCODE_Y1 = 5,
- WH64_UN_0_SHUN_0_OPCODE_X1 = 23,
- XORI_IMM_0_OPCODE_X0 = 2,
- XORI_IMM_0_OPCODE_X1 = 21,
- XOR_SPECIAL_0_OPCODE_X0 = 94,
- XOR_SPECIAL_0_OPCODE_X1 = 65,
- XOR_SPECIAL_2_OPCODE_Y0 = 3,
- XOR_SPECIAL_2_OPCODE_Y1 = 3
-};
-
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __ARCH_OPCODE_H__ */
diff --git a/arch/tile/include/uapi/arch/sim.h b/arch/tile/include/uapi/arch/sim.h
deleted file mode 100644
index c4183dcd2ea7..000000000000
--- a/arch/tile/include/uapi/arch/sim.h
+++ /dev/null
@@ -1,644 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * Provides an API for controlling the simulator at runtime.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- *
- * An API for controlling the simulator at runtime.
- *
- * The simulator's behavior can be modified while it is running.
- * For example, human-readable trace output can be enabled and disabled
- * around code of interest.
- *
- * There are two ways to modify simulator behavior:
- * programmatically, by calling various sim_* functions, and
- * interactively, by entering commands like "sim set functional true"
- * at the tile-monitor prompt. Typing "sim help" at that prompt provides
- * a list of interactive commands.
- *
- * All interactive commands can also be executed programmatically by
- * passing a string to the sim_command function.
- */
-
-#ifndef __ARCH_SIM_H__
-#define __ARCH_SIM_H__
-
-#include <arch/sim_def.h>
-#include <arch/abi.h>
-
-#ifndef __ASSEMBLER__
-
-#include <arch/spr_def.h>
-
-
-/**
- * Return true if the current program is running under a simulator,
- * rather than on real hardware. If running on hardware, other "sim_xxx()"
- * calls have no useful effect.
- */
-static inline int
-sim_is_simulator(void)
-{
- return __insn_mfspr(SPR_SIM_CONTROL) != 0;
-}
-
-
-/**
- * Checkpoint the simulator state to a checkpoint file.
- *
- * The checkpoint file name is either the default or the name specified
- * on the command line with "--checkpoint-file".
- */
-static __inline void
-sim_checkpoint(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_CHECKPOINT);
-}
-
-
-/**
- * Report whether or not various kinds of simulator tracing are enabled.
- *
- * @return The bitwise OR of these values:
- *
- * SIM_TRACE_CYCLES (--trace-cycles),
- * SIM_TRACE_ROUTER (--trace-router),
- * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
- * SIM_TRACE_DISASM (--trace-disasm),
- * SIM_TRACE_STALL_INFO (--trace-stall-info)
- * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
- * SIM_TRACE_L2_CACHE (--trace-l2)
- * SIM_TRACE_LINES (--trace-lines)
- */
-static __inline unsigned int
-sim_get_tracing(void)
-{
- return __insn_mfspr(SPR_SIM_CONTROL) & SIM_TRACE_FLAG_MASK;
-}
-
-
-/**
- * Turn on or off different kinds of simulator tracing.
- *
- * @param mask Either one of these special values:
- *
- * SIM_TRACE_NONE (turns off tracing),
- * SIM_TRACE_ALL (turns on all possible tracing).
- *
- * or the bitwise OR of these values:
- *
- * SIM_TRACE_CYCLES (--trace-cycles),
- * SIM_TRACE_ROUTER (--trace-router),
- * SIM_TRACE_REGISTER_WRITES (--trace-register-writes),
- * SIM_TRACE_DISASM (--trace-disasm),
- * SIM_TRACE_STALL_INFO (--trace-stall-info)
- * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller)
- * SIM_TRACE_L2_CACHE (--trace-l2)
- * SIM_TRACE_LINES (--trace-lines)
- */
-static __inline void
-sim_set_tracing(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_TRACE_SPR_ARG(mask));
-}
-
-
-/**
- * Request dumping of different kinds of simulator state.
- *
- * @param mask Either this special value:
- *
- * SIM_DUMP_ALL (dump all known state)
- *
- * or the bitwise OR of these values:
- *
- * SIM_DUMP_REGS (the register file),
- * SIM_DUMP_SPRS (the SPRs),
- * SIM_DUMP_ITLB (the iTLB),
- * SIM_DUMP_DTLB (the dTLB),
- * SIM_DUMP_L1I (the L1 I-cache),
- * SIM_DUMP_L1D (the L1 D-cache),
- * SIM_DUMP_L2 (the L2 cache),
- * SIM_DUMP_SNREGS (the switch register file),
- * SIM_DUMP_SNITLB (the switch iTLB),
- * SIM_DUMP_SNL1I (the switch L1 I-cache),
- * SIM_DUMP_BACKTRACE (the current backtrace)
- */
-static __inline void
-sim_dump(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_DUMP_SPR_ARG(mask));
-}
-
-
-/**
- * Print a string to the simulator stdout.
- *
- * @param str The string to be written.
- */
-static __inline void
-sim_print(const char* str)
-{
- for ( ; *str != '\0'; str++)
- {
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (*str << _SIM_CONTROL_OPERATOR_BITS));
- }
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS));
-}
-
-
-/**
- * Print a string to the simulator stdout.
- *
- * @param str The string to be written (a newline is automatically added).
- */
-static __inline void
-sim_print_string(const char* str)
-{
- for ( ; *str != '\0'; str++)
- {
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (*str << _SIM_CONTROL_OPERATOR_BITS));
- }
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC |
- (SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS));
-}
-
-
-/**
- * Execute a simulator command string.
- *
- * Type 'sim help' at the tile-monitor prompt to learn what commands
- * are available. Note the use of the tile-monitor "sim" command to
- * pass commands to the simulator.
- *
- * The argument to sim_command() does not include the leading "sim"
- * prefix used at the tile-monitor prompt; for example, you might call
- * sim_command("trace disasm").
- */
-static __inline void
-sim_command(const char* str)
-{
- int c;
- do
- {
- c = *str++;
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_COMMAND |
- (c << _SIM_CONTROL_OPERATOR_BITS));
- }
- while (c);
-}
-
-
-
-#ifndef __DOXYGEN__
-
-/**
- * The underlying implementation of "_sim_syscall()".
- *
- * We use extra "and" instructions to ensure that all the values
- * we are passing to the simulator are actually valid in the registers
- * (i.e. returned from memory) prior to the SIM_CONTROL spr.
- */
-static __inline long _sim_syscall0(int val)
-{
- long result;
- __asm__ __volatile__ ("mtspr SIM_CONTROL, r0"
- : "=R00" (result) : "R00" (val));
- return result;
-}
-
-static __inline long _sim_syscall1(int val, long arg1)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result) : "R00" (val), "R01" (arg1));
- return result;
-}
-
-static __inline long _sim_syscall2(int val, long arg1, long arg2)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2));
- return result;
-}
-
-/* Note that _sim_syscall3() and higher are technically at risk of
- receiving an interrupt right before the mtspr bundle, in which case
- the register values for arguments 3 and up may still be in flight
- to the core from a stack frame reload. */
-
-static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r3, r3 };"
- "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2),
- "R03" (arg3));
- return result;
-}
-
-static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3,
- long arg4)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r3, r4 };"
- "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2),
- "R03" (arg3), "R04" (arg4));
- return result;
-}
-
-static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3,
- long arg4, long arg5)
-{
- long result;
- __asm__ __volatile__ ("{ and zero, r3, r4; and zero, r5, r5 };"
- "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }"
- : "=R00" (result)
- : "R00" (val), "R01" (arg1), "R02" (arg2),
- "R03" (arg3), "R04" (arg4), "R05" (arg5));
- return result;
-}
-
-/**
- * Make a special syscall to the simulator itself, if running under
- * simulation. This is used as the implementation of other functions
- * and should not be used outside this file.
- *
- * @param syscall_num The simulator syscall number.
- * @param nr The number of additional arguments provided.
- *
- * @return Varies by syscall.
- */
-#define _sim_syscall(syscall_num, nr, args...) \
- _sim_syscall##nr( \
- ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \
- ##args)
-
-
-/* Values for the "access_mask" parameters below. */
-#define SIM_WATCHPOINT_READ 1
-#define SIM_WATCHPOINT_WRITE 2
-#define SIM_WATCHPOINT_EXECUTE 4
-
-
-static __inline int
-sim_add_watchpoint(unsigned int process_id,
- unsigned long address,
- unsigned long size,
- unsigned int access_mask,
- unsigned long user_data)
-{
- return _sim_syscall(SIM_SYSCALL_ADD_WATCHPOINT, 5, process_id,
- address, size, access_mask, user_data);
-}
-
-
-static __inline int
-sim_remove_watchpoint(unsigned int process_id,
- unsigned long address,
- unsigned long size,
- unsigned int access_mask,
- unsigned long user_data)
-{
- return _sim_syscall(SIM_SYSCALL_REMOVE_WATCHPOINT, 5, process_id,
- address, size, access_mask, user_data);
-}
-
-
-/**
- * Return value from sim_query_watchpoint.
- */
-struct SimQueryWatchpointStatus
-{
- /**
- * 0 if a watchpoint fired, 1 if no watchpoint fired, or -1 for
- * error (meaning a bad process_id).
- */
- int syscall_status;
-
- /**
- * The address of the watchpoint that fired (this is the address
- * passed to sim_add_watchpoint, not an address within that range
- * that actually triggered the watchpoint).
- */
- unsigned long address;
-
- /** The arbitrary user_data installed by sim_add_watchpoint. */
- unsigned long user_data;
-};
-
-
-static __inline struct SimQueryWatchpointStatus
-sim_query_watchpoint(unsigned int process_id)
-{
- struct SimQueryWatchpointStatus status;
- long val = SIM_CONTROL_SYSCALL |
- (SIM_SYSCALL_QUERY_WATCHPOINT << _SIM_CONTROL_OPERATOR_BITS);
- __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }"
- : "=R00" (status.syscall_status),
- "=R01" (status.address),
- "=R02" (status.user_data)
- : "R00" (val), "R01" (process_id));
- return status;
-}
-
-
-/* On the simulator, confirm lines have been evicted everywhere. */
-static __inline void
-sim_validate_lines_evicted(unsigned long long pa, unsigned long length)
-{
-#ifdef __LP64__
- _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 2, pa, length);
-#else
- _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 4,
- 0 /* dummy */, (long)(pa), (long)(pa >> 32), length);
-#endif
-}
-
-
-/* Return the current CPU speed in cycles per second. */
-static __inline long
-sim_query_cpu_speed(void)
-{
- return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0);
-}
-
-#endif /* !__DOXYGEN__ */
-
-
-
-
-/**
- * Modify the shaping parameters of a shim.
- *
- * @param shim The shim to modify. One of:
- * SIM_CONTROL_SHAPING_GBE_0
- * SIM_CONTROL_SHAPING_GBE_1
- * SIM_CONTROL_SHAPING_GBE_2
- * SIM_CONTROL_SHAPING_GBE_3
- * SIM_CONTROL_SHAPING_XGBE_0
- * SIM_CONTROL_SHAPING_XGBE_1
- *
- * @param type The type of shaping. This should be the same type of
- * shaping that is already in place on the shim. One of:
- * SIM_CONTROL_SHAPING_MULTIPLIER
- * SIM_CONTROL_SHAPING_PPS
- * SIM_CONTROL_SHAPING_BPS
- *
- * @param units The magnitude of the rate. One of:
- * SIM_CONTROL_SHAPING_UNITS_SINGLE
- * SIM_CONTROL_SHAPING_UNITS_KILO
- * SIM_CONTROL_SHAPING_UNITS_MEGA
- * SIM_CONTROL_SHAPING_UNITS_GIGA
- *
- * @param rate The rate to which to change it. This must fit in
- * SIM_CONTROL_SHAPING_RATE_BITS bits or a warning is issued and
- * the shaping is not changed.
- *
- * @return 0 if no problems were detected in the arguments to sim_set_shaping
- * or 1 if problems were detected (for example, rate does not fit in 17 bits).
- */
-static __inline int
-sim_set_shaping(unsigned shim,
- unsigned type,
- unsigned units,
- unsigned rate)
-{
- if ((rate & ~((1 << SIM_CONTROL_SHAPING_RATE_BITS) - 1)) != 0)
- return 1;
-
- __insn_mtspr(SPR_SIM_CONTROL, SIM_SHAPING_SPR_ARG(shim, type, units, rate));
- return 0;
-}
-
-#ifdef __tilegx__
-
-/** Enable a set of mPIPE links. Pass a -1 link_mask to enable all links. */
-static __inline void
-sim_enable_mpipe_links(unsigned mpipe, unsigned long link_mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL,
- (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
- (mpipe << 8) | (1 << 16) | ((uint_reg_t)link_mask << 32)));
-}
-
-/** Disable a set of mPIPE links. Pass a -1 link_mask to disable all links. */
-static __inline void
-sim_disable_mpipe_links(unsigned mpipe, unsigned long link_mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL,
- (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE |
- (mpipe << 8) | (0 << 16) | ((uint_reg_t)link_mask << 32)));
-}
-
-#endif /* __tilegx__ */
-
-
-/*
- * An API for changing "functional" mode.
- */
-
-#ifndef __DOXYGEN__
-
-#define sim_enable_functional() \
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_ENABLE_FUNCTIONAL)
-
-#define sim_disable_functional() \
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_DISABLE_FUNCTIONAL)
-
-#endif /* __DOXYGEN__ */
-
-
-/*
- * Profiler support.
- */
-
-/**
- * Turn profiling on for the current task.
- *
- * Note that this has no effect if run in an environment without
- * profiling support (thus, the proper flags to the simulator must
- * be supplied).
- */
-static __inline void
-sim_profiler_enable(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_ENABLE);
-}
-
-
-/** Turn profiling off for the current task. */
-static __inline void
-sim_profiler_disable(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_DISABLE);
-}
-
-
-/**
- * Turn profiling on or off for the current task.
- *
- * @param enabled If true, turns on profiling. If false, turns it off.
- *
- * Note that this has no effect if run in an environment without
- * profiling support (thus, the proper flags to the simulator must
- * be supplied).
- */
-static __inline void
-sim_profiler_set_enabled(int enabled)
-{
- int val =
- enabled ? SIM_CONTROL_PROFILER_ENABLE : SIM_CONTROL_PROFILER_DISABLE;
- __insn_mtspr(SPR_SIM_CONTROL, val);
-}
-
-
-/**
- * Return true if and only if profiling is currently enabled
- * for the current task.
- *
- * This returns false even if sim_profiler_enable() was called
- * if the current execution environment does not support profiling.
- */
-static __inline int
-sim_profiler_is_enabled(void)
-{
- return ((__insn_mfspr(SPR_SIM_CONTROL) & SIM_PROFILER_ENABLED_MASK) != 0);
-}
-
-
-/**
- * Reset profiling counters to zero for the current task.
- *
- * Resetting can be done while profiling is enabled. It does not affect
- * the chip-wide profiling counters.
- */
-static __inline void
-sim_profiler_clear(void)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_CLEAR);
-}
-
-
-/**
- * Enable specified chip-level profiling counters.
- *
- * Does not affect the per-task profiling counters.
- *
- * @param mask Either this special value:
- *
- * SIM_CHIP_ALL (enables all chip-level components).
- *
- * or the bitwise OR of these values:
- *
- * SIM_CHIP_MEMCTL (enable all memory controllers)
- * SIM_CHIP_XAUI (enable all XAUI controllers)
- * SIM_CHIP_MPIPE (enable all MPIPE controllers)
- */
-static __inline void
-sim_profiler_chip_enable(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask));
-}
-
-
-/**
- * Disable specified chip-level profiling counters.
- *
- * Does not affect the per-task profiling counters.
- *
- * @param mask Either this special value:
- *
- * SIM_CHIP_ALL (disables all chip-level components).
- *
- * or the bitwise OR of these values:
- *
- * SIM_CHIP_MEMCTL (disable all memory controllers)
- * SIM_CHIP_XAUI (disable all XAUI controllers)
- * SIM_CHIP_MPIPE (disable all MPIPE controllers)
- */
-static __inline void
-sim_profiler_chip_disable(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask));
-}
-
-
-/**
- * Reset specified chip-level profiling counters to zero.
- *
- * Does not affect the per-task profiling counters.
- *
- * @param mask Either this special value:
- *
- * SIM_CHIP_ALL (clears all chip-level components).
- *
- * or the bitwise OR of these values:
- *
- * SIM_CHIP_MEMCTL (clear all memory controllers)
- * SIM_CHIP_XAUI (clear all XAUI controllers)
- * SIM_CHIP_MPIPE (clear all MPIPE controllers)
- */
-static __inline void
-sim_profiler_chip_clear(unsigned int mask)
-{
- __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask));
-}
-
-
-/*
- * Event support.
- */
-
-#ifndef __DOXYGEN__
-
-static __inline void
-sim_event_begin(unsigned int x)
-{
-#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
- __insn_mtspr(SPR_EVENT_BEGIN, x);
-#endif
-}
-
-static __inline void
-sim_event_end(unsigned int x)
-{
-#if defined(__tile__) && !defined(__NO_EVENT_SPR__)
- __insn_mtspr(SPR_EVENT_END, x);
-#endif
-}
-
-#endif /* !__DOXYGEN__ */
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* !__ARCH_SIM_H__ */
-
-/** @} */
diff --git a/arch/tile/include/uapi/arch/sim_def.h b/arch/tile/include/uapi/arch/sim_def.h
deleted file mode 100644
index f74f9943770d..000000000000
--- a/arch/tile/include/uapi/arch/sim_def.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file
- *
- * Some low-level simulator definitions.
- */
-
-#ifndef __ARCH_SIM_DEF_H__
-#define __ARCH_SIM_DEF_H__
-
-
-/**
- * Internal: the low bits of the SIM_CONTROL_* SPR values specify
- * the operation to perform, and the remaining bits are
- * an operation-specific parameter (often unused).
- */
-#define _SIM_CONTROL_OPERATOR_BITS 8
-
-
-/*
- * Values which can be written to SPR_SIM_CONTROL.
- */
-
-/** If written to SPR_SIM_CONTROL, stops profiling. */
-#define SIM_CONTROL_PROFILER_DISABLE 0
-
-/** If written to SPR_SIM_CONTROL, starts profiling. */
-#define SIM_CONTROL_PROFILER_ENABLE 1
-
-/** If written to SPR_SIM_CONTROL, clears profiling counters. */
-#define SIM_CONTROL_PROFILER_CLEAR 2
-
-/** If written to SPR_SIM_CONTROL, checkpoints the simulator. */
-#define SIM_CONTROL_CHECKPOINT 3
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
- * sets the tracing mask to the given mask. See "sim_set_tracing()".
- */
-#define SIM_CONTROL_SET_TRACING 4
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8),
- * dumps the requested items of machine state to the log.
- */
-#define SIM_CONTROL_DUMP 5
-
-/** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */
-#define SIM_CONTROL_PROFILER_CHIP_CLEAR 6
-
-/** If written to SPR_SIM_CONTROL, disables chip-level profiling. */
-#define SIM_CONTROL_PROFILER_CHIP_DISABLE 7
-
-/** If written to SPR_SIM_CONTROL, enables chip-level profiling. */
-#define SIM_CONTROL_PROFILER_CHIP_ENABLE 8
-
-/** If written to SPR_SIM_CONTROL, enables chip-level functional mode */
-#define SIM_CONTROL_ENABLE_FUNCTIONAL 9
-
-/** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */
-#define SIM_CONTROL_DISABLE_FUNCTIONAL 10
-
-/**
- * If written to SPR_SIM_CONTROL, enables chip-level functional mode.
- * All tiles must perform this write for functional mode to be enabled.
- * Ignored in naked boot mode unless --functional is specified.
- * WARNING: Only the hypervisor startup code should use this!
- */
-#define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * writes a string directly to the simulator output. Written to once for
- * each character in the string, plus a final NUL. Instead of NUL,
- * you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY".
- */
-/* ISSUE: Document the meaning of "newline", and the handling of NUL. */
-#define SIM_CONTROL_PUTC 12
-
-/**
- * If written to SPR_SIM_CONTROL, clears the --grind-coherence state for
- * this core. This is intended to be used before a loop that will
- * invalidate the cache by loading new data and evicting all current data.
- * Generally speaking, this API should only be used by system code.
- */
-#define SIM_CONTROL_GRINDER_CLEAR 13
-
-/** If written to SPR_SIM_CONTROL, shuts down the simulator. */
-#define SIM_CONTROL_SHUTDOWN 14
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * indicates that a fork syscall just created the given process.
- */
-#define SIM_CONTROL_OS_FORK 15
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * indicates that an exit syscall was just executed by the given process.
- */
-#define SIM_CONTROL_OS_EXIT 16
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * indicates that the OS just switched to the given process.
- */
-#define SIM_CONTROL_OS_SWITCH 17
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that an exec syscall was just executed. Written to once for
- * each character in the executable name, plus a final NUL.
- */
-#define SIM_CONTROL_OS_EXEC 18
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that an interpreter (PT_INTERP) was loaded. Written to once
- * for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a
- * hex load address starting with "0x", and "PATH" is the executable name.
- */
-#define SIM_CONTROL_OS_INTERP 19
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that a dll was loaded. Written to once for each character
- * in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load
- * address starting with "0x", and "PATH" is the executable name.
- */
-#define SIM_CONTROL_DLOPEN 20
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8),
- * indicates that a dll was unloaded. Written to once for each character
- * in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load
- * address starting with "0x".
- */
-#define SIM_CONTROL_DLCLOSE 21
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8),
- * indicates whether to allow data reads to remotely-cached
- * dirty cache lines to be cached locally without grinder warnings or
- * assertions (used by Linux kernel fast memcpy).
- */
-#define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22
-
-/** If written to SPR_SIM_CONTROL, enables memory tracing. */
-#define SIM_CONTROL_ENABLE_MEM_LOGGING 23
-
-/** If written to SPR_SIM_CONTROL, disables memory tracing. */
-#define SIM_CONTROL_DISABLE_MEM_LOGGING 24
-
-/**
- * If written to SPR_SIM_CONTROL, changes the shaping parameters of one of
- * the gbe or xgbe shims. Must specify the shim id, the type, the units, and
- * the rate, as defined in SIM_SHAPING_SPR_ARG.
- */
-#define SIM_CONTROL_SHAPING 25
-
-/**
- * If written to SPR_SIM_CONTROL, combined with character (shifted by 8),
- * requests that a simulator command be executed. Written to once for each
- * character in the command, plus a final NUL.
- */
-#define SIM_CONTROL_COMMAND 26
-
-/**
- * If written to SPR_SIM_CONTROL, indicates that the simulated system
- * is panicking, to allow debugging via --debug-on-panic.
- */
-#define SIM_CONTROL_PANIC 27
-
-/**
- * If written to SPR_SIM_CONTROL, triggers a simulator syscall.
- * See "sim_syscall()" for more info.
- */
-#define SIM_CONTROL_SYSCALL 32
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8),
- * provides the pid that subsequent SIM_CONTROL_OS_FORK writes should
- * use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH.
- */
-#define SIM_CONTROL_OS_FORK_PARENT 33
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
- * (shifted by 8), clears the pending magic data section. The cleared
- * pending magic data section and any subsequently appended magic bytes
- * will only take effect when the classifier blast programmer is run.
- */
-#define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
- * (shifted by 8) and a byte of data (shifted by 16), appends that byte
- * to the shim's pending magic data section. The pending magic data
- * section takes effect when the classifier blast programmer is run.
- */
-#define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35
-
-/**
- * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number
- * (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a
- * mask of links (shifted by 32), enable or disable the corresponding
- * mPIPE links.
- */
-#define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36
-
-
-/*
- * Syscall numbers for use with "sim_syscall()".
- */
-
-/** Syscall number for sim_add_watchpoint(). */
-#define SIM_SYSCALL_ADD_WATCHPOINT 2
-
-/** Syscall number for sim_remove_watchpoint(). */
-#define SIM_SYSCALL_REMOVE_WATCHPOINT 3
-
-/** Syscall number for sim_query_watchpoint(). */
-#define SIM_SYSCALL_QUERY_WATCHPOINT 4
-
-/**
- * Syscall number that asserts that the cache lines whose 64-bit PA
- * is passed as the second argument to sim_syscall(), and over a
- * range passed as the third argument, are no longer in cache.
- * The simulator raises an error if this is not the case.
- */
-#define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5
-
-/** Syscall number for sim_query_cpu_speed(). */
-#define SIM_SYSCALL_QUERY_CPU_SPEED 6
-
-
-/*
- * Bit masks which can be shifted by 8, combined with
- * SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Enable --trace-cycle when passed to simulator_set_tracing(). */
-#define SIM_TRACE_CYCLES 0x01
-
-/** Enable --trace-router when passed to simulator_set_tracing(). */
-#define SIM_TRACE_ROUTER 0x02
-
-/** Enable --trace-register-writes when passed to simulator_set_tracing(). */
-#define SIM_TRACE_REGISTER_WRITES 0x04
-
-/** Enable --trace-disasm when passed to simulator_set_tracing(). */
-#define SIM_TRACE_DISASM 0x08
-
-/** Enable --trace-stall-info when passed to simulator_set_tracing(). */
-#define SIM_TRACE_STALL_INFO 0x10
-
-/** Enable --trace-memory-controller when passed to simulator_set_tracing(). */
-#define SIM_TRACE_MEMORY_CONTROLLER 0x20
-
-/** Enable --trace-l2 when passed to simulator_set_tracing(). */
-#define SIM_TRACE_L2_CACHE 0x40
-
-/** Enable --trace-lines when passed to simulator_set_tracing(). */
-#define SIM_TRACE_LINES 0x80
-
-/** Turn off all tracing when passed to simulator_set_tracing(). */
-#define SIM_TRACE_NONE 0
-
-/** Turn on all tracing when passed to simulator_set_tracing(). */
-#define SIM_TRACE_ALL (-1)
-
-/** @} */
-
-/** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */
-#define SIM_TRACE_SPR_ARG(mask) \
- (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-
-/*
- * Bit masks which can be shifted by 8, combined with
- * SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Dump the general-purpose registers. */
-#define SIM_DUMP_REGS 0x001
-
-/** Dump the SPRs. */
-#define SIM_DUMP_SPRS 0x002
-
-/** Dump the ITLB. */
-#define SIM_DUMP_ITLB 0x004
-
-/** Dump the DTLB. */
-#define SIM_DUMP_DTLB 0x008
-
-/** Dump the L1 I-cache. */
-#define SIM_DUMP_L1I 0x010
-
-/** Dump the L1 D-cache. */
-#define SIM_DUMP_L1D 0x020
-
-/** Dump the L2 cache. */
-#define SIM_DUMP_L2 0x040
-
-/** Dump the switch registers. */
-#define SIM_DUMP_SNREGS 0x080
-
-/** Dump the switch ITLB. */
-#define SIM_DUMP_SNITLB 0x100
-
-/** Dump the switch L1 I-cache. */
-#define SIM_DUMP_SNL1I 0x200
-
-/** Dump the current backtrace. */
-#define SIM_DUMP_BACKTRACE 0x400
-
-/** Only dump valid lines in caches. */
-#define SIM_DUMP_VALID_LINES 0x800
-
-/** Dump everything that is dumpable. */
-#define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES)
-
-/** @} */
-
-/** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */
-#define SIM_DUMP_SPR_ARG(mask) \
- (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-
-/*
- * Bit masks which can be shifted by 8, combined with
- * SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL.
- */
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the memory controllers. */
-#define SIM_CHIP_MEMCTL 0x001
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */
-#define SIM_CHIP_XAUI 0x002
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */
-#define SIM_CHIP_PCIE 0x004
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */
-#define SIM_CHIP_MPIPE 0x008
-
-/** Use with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */
-#define SIM_CHIP_TRIO 0x010
-
-/** Reference all chip devices. */
-#define SIM_CHIP_ALL (-1)
-
-/** @} */
-
-/** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */
-#define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \
- (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-/** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/
-#define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \
- (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-/** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */
-#define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \
- (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS))
-
-
-
-/* Shim bitrate controls. */
-
-/** The number of bits used to store the shim id. */
-#define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3
-
-/**
- * @addtogroup arch_sim
- * @{
- */
-
-/** Change the gbe 0 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_0 0x0
-
-/** Change the gbe 1 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_1 0x1
-
-/** Change the gbe 2 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_2 0x2
-
-/** Change the gbe 3 bitrate. */
-#define SIM_CONTROL_SHAPING_GBE_3 0x3
-
-/** Change the xgbe 0 bitrate. */
-#define SIM_CONTROL_SHAPING_XGBE_0 0x4
-
-/** Change the xgbe 1 bitrate. */
-#define SIM_CONTROL_SHAPING_XGBE_1 0x5
-
-/** The type of shaping to do. */
-#define SIM_CONTROL_SHAPING_TYPE_BITS 2
-
-/** Control the multiplier. */
-#define SIM_CONTROL_SHAPING_MULTIPLIER 0
-
-/** Control the PPS. */
-#define SIM_CONTROL_SHAPING_PPS 1
-
-/** Control the BPS. */
-#define SIM_CONTROL_SHAPING_BPS 2
-
-/** The number of bits for the units for the shaping parameter. */
-#define SIM_CONTROL_SHAPING_UNITS_BITS 2
-
-/** Provide a number in single units. */
-#define SIM_CONTROL_SHAPING_UNITS_SINGLE 0
-
-/** Provide a number in kilo units. */
-#define SIM_CONTROL_SHAPING_UNITS_KILO 1
-
-/** Provide a number in mega units. */
-#define SIM_CONTROL_SHAPING_UNITS_MEGA 2
-
-/** Provide a number in giga units. */
-#define SIM_CONTROL_SHAPING_UNITS_GIGA 3
-
-/** @} */
-
-/** How many bits are available for the rate. */
-#define SIM_CONTROL_SHAPING_RATE_BITS \
- (32 - (_SIM_CONTROL_OPERATOR_BITS + \
- SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
- SIM_CONTROL_SHAPING_TYPE_BITS + \
- SIM_CONTROL_SHAPING_UNITS_BITS))
-
-/** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */
-#define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \
- (SIM_CONTROL_SHAPING | \
- ((shim) | \
- ((type) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS)) | \
- ((units) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
- SIM_CONTROL_SHAPING_TYPE_BITS)) | \
- ((rate) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \
- SIM_CONTROL_SHAPING_TYPE_BITS + \
- SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS)
-
-
-/*
- * Values returned when reading SPR_SIM_CONTROL.
- * ISSUE: These names should share a longer common prefix.
- */
-
-/**
- * When reading SPR_SIM_CONTROL, the mask of simulator tracing bits
- * (SIM_TRACE_xxx values).
- */
-#define SIM_TRACE_FLAG_MASK 0xFFFF
-
-/** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */
-#define SIM_PROFILER_ENABLED_MASK 0x10000
-
-
-/*
- * Special arguments for "SIM_CONTROL_PUTC".
- */
-
-/**
- * Flag value for forcing a PUTC string-flush, including
- * coordinate/cycle prefix and newline.
- */
-#define SIM_PUTC_FLUSH_STRING 0x100
-
-/**
- * Flag value for forcing a PUTC binary-data-flush, which skips the
- * prefix and does not append a newline.
- */
-#define SIM_PUTC_FLUSH_BINARY 0x101
-
-
-#endif /* __ARCH_SIM_DEF_H__ */
diff --git a/arch/tile/include/uapi/arch/spr_def.h b/arch/tile/include/uapi/arch/spr_def.h
deleted file mode 100644
index 743428615cda..000000000000
--- a/arch/tile/include/uapi/arch/spr_def.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI__ARCH_SPR_DEF_H__
-#define _UAPI__ARCH_SPR_DEF_H__
-
-/* Include the proper base SPR definition file. */
-#ifdef __tilegx__
-#include <arch/spr_def_64.h>
-#else
-#include <arch/spr_def_32.h>
-#endif
-
-
-#endif /* _UAPI__ARCH_SPR_DEF_H__ */
diff --git a/arch/tile/include/uapi/arch/spr_def_32.h b/arch/tile/include/uapi/arch/spr_def_32.h
deleted file mode 100644
index 64122d6160e1..000000000000
--- a/arch/tile/include/uapi/arch/spr_def_32.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __DOXYGEN__
-
-#ifndef __ARCH_SPR_DEF_32_H__
-#define __ARCH_SPR_DEF_32_H__
-
-#define SPR_AUX_PERF_COUNT_0 0x6005
-#define SPR_AUX_PERF_COUNT_1 0x6006
-#define SPR_AUX_PERF_COUNT_CTL 0x6007
-#define SPR_AUX_PERF_COUNT_STS 0x6008
-#define SPR_CYCLE_HIGH 0x4e06
-#define SPR_CYCLE_LOW 0x4e07
-#define SPR_DMA_BYTE 0x3900
-#define SPR_DMA_CHUNK_SIZE 0x3901
-#define SPR_DMA_CTR 0x3902
-#define SPR_DMA_CTR__REQUEST_MASK 0x1
-#define SPR_DMA_CTR__SUSPEND_MASK 0x2
-#define SPR_DMA_DST_ADDR 0x3903
-#define SPR_DMA_DST_CHUNK_ADDR 0x3904
-#define SPR_DMA_SRC_ADDR 0x3905
-#define SPR_DMA_SRC_CHUNK_ADDR 0x3906
-#define SPR_DMA_STATUS__DONE_MASK 0x1
-#define SPR_DMA_STATUS__BUSY_MASK 0x2
-#define SPR_DMA_STATUS__RUNNING_MASK 0x10
-#define SPR_DMA_STRIDE 0x3907
-#define SPR_DMA_USER_STATUS 0x3908
-#define SPR_DONE 0x4e08
-#define SPR_EVENT_BEGIN 0x4e0d
-#define SPR_EVENT_END 0x4e0e
-#define SPR_EX_CONTEXT_0_0 0x4a05
-#define SPR_EX_CONTEXT_0_1 0x4a06
-#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_1_0 0x4805
-#define SPR_EX_CONTEXT_1_1 0x4806
-#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_2_0 0x4605
-#define SPR_EX_CONTEXT_2_1 0x4606
-#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
-#define SPR_FAIL 0x4e09
-#define SPR_IDN_AVAIL_EN 0x3e05
-#define SPR_IDN_CA_DATA 0x0b00
-#define SPR_IDN_DATA_AVAIL 0x0b03
-#define SPR_IDN_DEADLOCK_TIMEOUT 0x3406
-#define SPR_IDN_DEMUX_CA_COUNT 0x0a05
-#define SPR_IDN_DEMUX_COUNT_0 0x0a06
-#define SPR_IDN_DEMUX_COUNT_1 0x0a07
-#define SPR_IDN_DEMUX_CTL 0x0a08
-#define SPR_IDN_DEMUX_QUEUE_SEL 0x0a0a
-#define SPR_IDN_DEMUX_STATUS 0x0a0b
-#define SPR_IDN_DEMUX_WRITE_FIFO 0x0a0c
-#define SPR_IDN_DIRECTION_PROTECT 0x2e05
-#define SPR_IDN_PENDING 0x0a0e
-#define SPR_IDN_REFILL_EN 0x0e05
-#define SPR_IDN_SP_FIFO_DATA 0x0a0f
-#define SPR_IDN_SP_FIFO_SEL 0x0a10
-#define SPR_IDN_SP_FREEZE 0x0a11
-#define SPR_IDN_SP_FREEZE__SP_FRZ_MASK 0x1
-#define SPR_IDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
-#define SPR_IDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
-#define SPR_IDN_SP_STATE 0x0a12
-#define SPR_IDN_TAG_0 0x0a13
-#define SPR_IDN_TAG_1 0x0a14
-#define SPR_IDN_TAG_VALID 0x0a15
-#define SPR_IDN_TILE_COORD 0x0a16
-#define SPR_INTCTRL_0_STATUS 0x4a07
-#define SPR_INTCTRL_1_STATUS 0x4807
-#define SPR_INTCTRL_2_STATUS 0x4607
-#define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a
-#define SPR_INTERRUPT_MASK_0_0 0x4a08
-#define SPR_INTERRUPT_MASK_0_1 0x4a09
-#define SPR_INTERRUPT_MASK_1_0 0x4809
-#define SPR_INTERRUPT_MASK_1_1 0x480a
-#define SPR_INTERRUPT_MASK_2_0 0x4608
-#define SPR_INTERRUPT_MASK_2_1 0x4609
-#define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a
-#define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b
-#define SPR_INTERRUPT_MASK_RESET_1_0 0x480b
-#define SPR_INTERRUPT_MASK_RESET_1_1 0x480c
-#define SPR_INTERRUPT_MASK_RESET_2_0 0x460a
-#define SPR_INTERRUPT_MASK_RESET_2_1 0x460b
-#define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c
-#define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d
-#define SPR_INTERRUPT_MASK_SET_1_0 0x480d
-#define SPR_INTERRUPT_MASK_SET_1_1 0x480e
-#define SPR_INTERRUPT_MASK_SET_2_0 0x460c
-#define SPR_INTERRUPT_MASK_SET_2_1 0x460d
-#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x6000
-#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x6001
-#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x6002
-#define SPR_MPL_DMA_CPL_SET_0 0x5800
-#define SPR_MPL_DMA_CPL_SET_1 0x5801
-#define SPR_MPL_DMA_CPL_SET_2 0x5802
-#define SPR_MPL_DMA_NOTIFY_SET_0 0x3800
-#define SPR_MPL_DMA_NOTIFY_SET_1 0x3801
-#define SPR_MPL_DMA_NOTIFY_SET_2 0x3802
-#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
-#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
-#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
-#define SPR_MPL_IDN_AVAIL_SET_0 0x3e00
-#define SPR_MPL_IDN_AVAIL_SET_1 0x3e01
-#define SPR_MPL_IDN_AVAIL_SET_2 0x3e02
-#define SPR_MPL_IDN_CA_SET_0 0x3a00
-#define SPR_MPL_IDN_CA_SET_1 0x3a01
-#define SPR_MPL_IDN_CA_SET_2 0x3a02
-#define SPR_MPL_IDN_COMPLETE_SET_0 0x1200
-#define SPR_MPL_IDN_COMPLETE_SET_1 0x1201
-#define SPR_MPL_IDN_COMPLETE_SET_2 0x1202
-#define SPR_MPL_IDN_FIREWALL_SET_0 0x2e00
-#define SPR_MPL_IDN_FIREWALL_SET_1 0x2e01
-#define SPR_MPL_IDN_FIREWALL_SET_2 0x2e02
-#define SPR_MPL_IDN_REFILL_SET_0 0x0e00
-#define SPR_MPL_IDN_REFILL_SET_1 0x0e01
-#define SPR_MPL_IDN_REFILL_SET_2 0x0e02
-#define SPR_MPL_IDN_TIMER_SET_0 0x3400
-#define SPR_MPL_IDN_TIMER_SET_1 0x3401
-#define SPR_MPL_IDN_TIMER_SET_2 0x3402
-#define SPR_MPL_INTCTRL_0_SET_0 0x4a00
-#define SPR_MPL_INTCTRL_0_SET_1 0x4a01
-#define SPR_MPL_INTCTRL_0_SET_2 0x4a02
-#define SPR_MPL_INTCTRL_1_SET_0 0x4800
-#define SPR_MPL_INTCTRL_1_SET_1 0x4801
-#define SPR_MPL_INTCTRL_1_SET_2 0x4802
-#define SPR_MPL_INTCTRL_2_SET_0 0x4600
-#define SPR_MPL_INTCTRL_2_SET_1 0x4601
-#define SPR_MPL_INTCTRL_2_SET_2 0x4602
-#define SPR_MPL_PERF_COUNT_SET_0 0x4200
-#define SPR_MPL_PERF_COUNT_SET_1 0x4201
-#define SPR_MPL_PERF_COUNT_SET_2 0x4202
-#define SPR_MPL_SN_ACCESS_SET_0 0x0800
-#define SPR_MPL_SN_ACCESS_SET_1 0x0801
-#define SPR_MPL_SN_ACCESS_SET_2 0x0802
-#define SPR_MPL_SN_CPL_SET_0 0x5a00
-#define SPR_MPL_SN_CPL_SET_1 0x5a01
-#define SPR_MPL_SN_CPL_SET_2 0x5a02
-#define SPR_MPL_SN_FIREWALL_SET_0 0x2c00
-#define SPR_MPL_SN_FIREWALL_SET_1 0x2c01
-#define SPR_MPL_SN_FIREWALL_SET_2 0x2c02
-#define SPR_MPL_SN_NOTIFY_SET_0 0x2a00
-#define SPR_MPL_SN_NOTIFY_SET_1 0x2a01
-#define SPR_MPL_SN_NOTIFY_SET_2 0x2a02
-#define SPR_MPL_UDN_ACCESS_SET_0 0x0c00
-#define SPR_MPL_UDN_ACCESS_SET_1 0x0c01
-#define SPR_MPL_UDN_ACCESS_SET_2 0x0c02
-#define SPR_MPL_UDN_AVAIL_SET_0 0x4000
-#define SPR_MPL_UDN_AVAIL_SET_1 0x4001
-#define SPR_MPL_UDN_AVAIL_SET_2 0x4002
-#define SPR_MPL_UDN_CA_SET_0 0x3c00
-#define SPR_MPL_UDN_CA_SET_1 0x3c01
-#define SPR_MPL_UDN_CA_SET_2 0x3c02
-#define SPR_MPL_UDN_COMPLETE_SET_0 0x1400
-#define SPR_MPL_UDN_COMPLETE_SET_1 0x1401
-#define SPR_MPL_UDN_COMPLETE_SET_2 0x1402
-#define SPR_MPL_UDN_FIREWALL_SET_0 0x3000
-#define SPR_MPL_UDN_FIREWALL_SET_1 0x3001
-#define SPR_MPL_UDN_FIREWALL_SET_2 0x3002
-#define SPR_MPL_UDN_REFILL_SET_0 0x1000
-#define SPR_MPL_UDN_REFILL_SET_1 0x1001
-#define SPR_MPL_UDN_REFILL_SET_2 0x1002
-#define SPR_MPL_UDN_TIMER_SET_0 0x3600
-#define SPR_MPL_UDN_TIMER_SET_1 0x3601
-#define SPR_MPL_UDN_TIMER_SET_2 0x3602
-#define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00
-#define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01
-#define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02
-#define SPR_PASS 0x4e0b
-#define SPR_PERF_COUNT_0 0x4205
-#define SPR_PERF_COUNT_1 0x4206
-#define SPR_PERF_COUNT_CTL 0x4207
-#define SPR_PERF_COUNT_DN_CTL 0x4210
-#define SPR_PERF_COUNT_STS 0x4208
-#define SPR_PROC_STATUS 0x4f00
-#define SPR_SIM_CONTROL 0x4e0c
-#define SPR_SNCTL 0x0805
-#define SPR_SNCTL__FRZFABRIC_MASK 0x1
-#define SPR_SNSTATIC 0x080c
-#define SPR_SYSTEM_SAVE_0_0 0x4b00
-#define SPR_SYSTEM_SAVE_0_1 0x4b01
-#define SPR_SYSTEM_SAVE_0_2 0x4b02
-#define SPR_SYSTEM_SAVE_0_3 0x4b03
-#define SPR_SYSTEM_SAVE_1_0 0x4900
-#define SPR_SYSTEM_SAVE_1_1 0x4901
-#define SPR_SYSTEM_SAVE_1_2 0x4902
-#define SPR_SYSTEM_SAVE_1_3 0x4903
-#define SPR_SYSTEM_SAVE_2_0 0x4700
-#define SPR_SYSTEM_SAVE_2_1 0x4701
-#define SPR_SYSTEM_SAVE_2_2 0x4702
-#define SPR_SYSTEM_SAVE_2_3 0x4703
-#define SPR_TILE_COORD 0x4c17
-#define SPR_TILE_RTF_HWM 0x4e10
-#define SPR_TILE_TIMER_CONTROL 0x3205
-#define SPR_TILE_WRITE_PENDING 0x4e0f
-#define SPR_UDN_AVAIL_EN 0x4005
-#define SPR_UDN_CA_DATA 0x0d00
-#define SPR_UDN_DATA_AVAIL 0x0d03
-#define SPR_UDN_DEADLOCK_TIMEOUT 0x3606
-#define SPR_UDN_DEMUX_CA_COUNT 0x0c05
-#define SPR_UDN_DEMUX_COUNT_0 0x0c06
-#define SPR_UDN_DEMUX_COUNT_1 0x0c07
-#define SPR_UDN_DEMUX_COUNT_2 0x0c08
-#define SPR_UDN_DEMUX_COUNT_3 0x0c09
-#define SPR_UDN_DEMUX_CTL 0x0c0a
-#define SPR_UDN_DEMUX_QUEUE_SEL 0x0c0c
-#define SPR_UDN_DEMUX_STATUS 0x0c0d
-#define SPR_UDN_DEMUX_WRITE_FIFO 0x0c0e
-#define SPR_UDN_DIRECTION_PROTECT 0x3005
-#define SPR_UDN_PENDING 0x0c10
-#define SPR_UDN_REFILL_EN 0x1005
-#define SPR_UDN_SP_FIFO_DATA 0x0c11
-#define SPR_UDN_SP_FIFO_SEL 0x0c12
-#define SPR_UDN_SP_FREEZE 0x0c13
-#define SPR_UDN_SP_FREEZE__SP_FRZ_MASK 0x1
-#define SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2
-#define SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4
-#define SPR_UDN_SP_STATE 0x0c14
-#define SPR_UDN_TAG_0 0x0c15
-#define SPR_UDN_TAG_1 0x0c16
-#define SPR_UDN_TAG_2 0x0c17
-#define SPR_UDN_TAG_3 0x0c18
-#define SPR_UDN_TAG_VALID 0x0c19
-#define SPR_UDN_TILE_COORD 0x0c1a
-#define SPR_WATCH_CTL 0x4209
-#define SPR_WATCH_MASK 0x420a
-#define SPR_WATCH_VAL 0x420b
-
-#endif /* !defined(__ARCH_SPR_DEF_32_H__) */
-
-#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/uapi/arch/spr_def_64.h b/arch/tile/include/uapi/arch/spr_def_64.h
deleted file mode 100644
index d183cbb31aa7..000000000000
--- a/arch/tile/include/uapi/arch/spr_def_64.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef __DOXYGEN__
-
-#ifndef __ARCH_SPR_DEF_64_H__
-#define __ARCH_SPR_DEF_64_H__
-
-#define SPR_AUX_PERF_COUNT_0 0x2105
-#define SPR_AUX_PERF_COUNT_1 0x2106
-#define SPR_AUX_PERF_COUNT_CTL 0x2107
-#define SPR_AUX_PERF_COUNT_STS 0x2108
-#define SPR_CMPEXCH_VALUE 0x2780
-#define SPR_CYCLE 0x2781
-#define SPR_DONE 0x2705
-#define SPR_DSTREAM_PF 0x2706
-#define SPR_EVENT_BEGIN 0x2782
-#define SPR_EVENT_END 0x2783
-#define SPR_EX_CONTEXT_0_0 0x2580
-#define SPR_EX_CONTEXT_0_1 0x2581
-#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_1_0 0x2480
-#define SPR_EX_CONTEXT_1_1 0x2481
-#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
-#define SPR_EX_CONTEXT_2_0 0x2380
-#define SPR_EX_CONTEXT_2_1 0x2381
-#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
-#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
-#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
-#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
-#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
-#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
-#define SPR_FAIL 0x2707
-#define SPR_IDN_AVAIL_EN 0x1a05
-#define SPR_IDN_DATA_AVAIL 0x0a80
-#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806
-#define SPR_IDN_DEMUX_COUNT_0 0x0a05
-#define SPR_IDN_DEMUX_COUNT_1 0x0a06
-#define SPR_IDN_DIRECTION_PROTECT 0x1405
-#define SPR_IDN_PENDING 0x0a08
-#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
-#define SPR_INTCTRL_0_STATUS 0x2505
-#define SPR_INTCTRL_1_STATUS 0x2405
-#define SPR_INTCTRL_2_STATUS 0x2305
-#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
-#define SPR_INTERRUPT_MASK_0 0x2506
-#define SPR_INTERRUPT_MASK_1 0x2406
-#define SPR_INTERRUPT_MASK_2 0x2306
-#define SPR_INTERRUPT_MASK_RESET_0 0x2507
-#define SPR_INTERRUPT_MASK_RESET_1 0x2407
-#define SPR_INTERRUPT_MASK_RESET_2 0x2307
-#define SPR_INTERRUPT_MASK_SET_0 0x2508
-#define SPR_INTERRUPT_MASK_SET_1 0x2408
-#define SPR_INTERRUPT_MASK_SET_2 0x2308
-#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
-#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
-#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
-#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
-#define SPR_IPI_EVENT_0 0x1f05
-#define SPR_IPI_EVENT_1 0x1e05
-#define SPR_IPI_EVENT_2 0x1d05
-#define SPR_IPI_EVENT_RESET_0 0x1f06
-#define SPR_IPI_EVENT_RESET_1 0x1e06
-#define SPR_IPI_EVENT_RESET_2 0x1d06
-#define SPR_IPI_EVENT_SET_0 0x1f07
-#define SPR_IPI_EVENT_SET_1 0x1e07
-#define SPR_IPI_EVENT_SET_2 0x1d07
-#define SPR_IPI_MASK_0 0x1f08
-#define SPR_IPI_MASK_1 0x1e08
-#define SPR_IPI_MASK_2 0x1d08
-#define SPR_IPI_MASK_RESET_0 0x1f09
-#define SPR_IPI_MASK_RESET_1 0x1e09
-#define SPR_IPI_MASK_RESET_2 0x1d09
-#define SPR_IPI_MASK_SET_0 0x1f0a
-#define SPR_IPI_MASK_SET_1 0x1e0a
-#define SPR_IPI_MASK_SET_2 0x1d0a
-#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100
-#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101
-#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102
-#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
-#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
-#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
-#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
-#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
-#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
-#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00
-#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01
-#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02
-#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500
-#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501
-#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502
-#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400
-#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401
-#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402
-#define SPR_MPL_IDN_TIMER_SET_0 0x1800
-#define SPR_MPL_IDN_TIMER_SET_1 0x1801
-#define SPR_MPL_IDN_TIMER_SET_2 0x1802
-#define SPR_MPL_INTCTRL_0_SET_0 0x2500
-#define SPR_MPL_INTCTRL_0_SET_1 0x2501
-#define SPR_MPL_INTCTRL_0_SET_2 0x2502
-#define SPR_MPL_INTCTRL_1_SET_0 0x2400
-#define SPR_MPL_INTCTRL_1_SET_1 0x2401
-#define SPR_MPL_INTCTRL_1_SET_2 0x2402
-#define SPR_MPL_INTCTRL_2_SET_0 0x2300
-#define SPR_MPL_INTCTRL_2_SET_1 0x2301
-#define SPR_MPL_INTCTRL_2_SET_2 0x2302
-#define SPR_MPL_IPI_0 0x1f04
-#define SPR_MPL_IPI_0_SET_0 0x1f00
-#define SPR_MPL_IPI_0_SET_1 0x1f01
-#define SPR_MPL_IPI_0_SET_2 0x1f02
-#define SPR_MPL_IPI_1 0x1e04
-#define SPR_MPL_IPI_1_SET_0 0x1e00
-#define SPR_MPL_IPI_1_SET_1 0x1e01
-#define SPR_MPL_IPI_1_SET_2 0x1e02
-#define SPR_MPL_IPI_2 0x1d04
-#define SPR_MPL_IPI_2_SET_0 0x1d00
-#define SPR_MPL_IPI_2_SET_1 0x1d01
-#define SPR_MPL_IPI_2_SET_2 0x1d02
-#define SPR_MPL_PERF_COUNT_SET_0 0x2000
-#define SPR_MPL_PERF_COUNT_SET_1 0x2001
-#define SPR_MPL_PERF_COUNT_SET_2 0x2002
-#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
-#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
-#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
-#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
-#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
-#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
-#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
-#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
-#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
-#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
-#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
-#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
-#define SPR_MPL_UDN_TIMER_SET_0 0x1900
-#define SPR_MPL_UDN_TIMER_SET_1 0x1901
-#define SPR_MPL_UDN_TIMER_SET_2 0x1902
-#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
-#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
-#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
-#define SPR_PASS 0x2709
-#define SPR_PERF_COUNT_0 0x2005
-#define SPR_PERF_COUNT_1 0x2006
-#define SPR_PERF_COUNT_CTL 0x2007
-#define SPR_PERF_COUNT_DN_CTL 0x2008
-#define SPR_PERF_COUNT_STS 0x2009
-#define SPR_PROC_STATUS 0x2784
-#define SPR_SIM_CONTROL 0x2785
-#define SPR_SINGLE_STEP_CONTROL_0 0x0405
-#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
-#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
-#define SPR_SINGLE_STEP_CONTROL_1 0x0305
-#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
-#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
-#define SPR_SINGLE_STEP_CONTROL_2 0x0205
-#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
-#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
-#define SPR_SINGLE_STEP_EN_0_0 0x250a
-#define SPR_SINGLE_STEP_EN_0_1 0x240a
-#define SPR_SINGLE_STEP_EN_0_2 0x230a
-#define SPR_SINGLE_STEP_EN_1_0 0x250b
-#define SPR_SINGLE_STEP_EN_1_1 0x240b
-#define SPR_SINGLE_STEP_EN_1_2 0x230b
-#define SPR_SINGLE_STEP_EN_2_0 0x250c
-#define SPR_SINGLE_STEP_EN_2_1 0x240c
-#define SPR_SINGLE_STEP_EN_2_2 0x230c
-#define SPR_SYSTEM_SAVE_0_0 0x2582
-#define SPR_SYSTEM_SAVE_0_1 0x2583
-#define SPR_SYSTEM_SAVE_0_2 0x2584
-#define SPR_SYSTEM_SAVE_0_3 0x2585
-#define SPR_SYSTEM_SAVE_1_0 0x2482
-#define SPR_SYSTEM_SAVE_1_1 0x2483
-#define SPR_SYSTEM_SAVE_1_2 0x2484
-#define SPR_SYSTEM_SAVE_1_3 0x2485
-#define SPR_SYSTEM_SAVE_2_0 0x2382
-#define SPR_SYSTEM_SAVE_2_1 0x2383
-#define SPR_SYSTEM_SAVE_2_2 0x2384
-#define SPR_SYSTEM_SAVE_2_3 0x2385
-#define SPR_TILE_COORD 0x270b
-#define SPR_TILE_RTF_HWM 0x270c
-#define SPR_TILE_TIMER_CONTROL 0x1605
-#define SPR_UDN_AVAIL_EN 0x1b05
-#define SPR_UDN_DATA_AVAIL 0x0b80
-#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
-#define SPR_UDN_DEMUX_COUNT_0 0x0b05
-#define SPR_UDN_DEMUX_COUNT_1 0x0b06
-#define SPR_UDN_DEMUX_COUNT_2 0x0b07
-#define SPR_UDN_DEMUX_COUNT_3 0x0b08
-#define SPR_UDN_DIRECTION_PROTECT 0x1505
-#define SPR_UDN_PENDING 0x0b0a
-#define SPR_WATCH_MASK 0x200a
-#define SPR_WATCH_VAL 0x200b
-
-#endif /* !defined(__ARCH_SPR_DEF_64_H__) */
-
-#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/uapi/asm/Kbuild b/arch/tile/include/uapi/asm/Kbuild
deleted file mode 100644
index cc439612bcd5..000000000000
--- a/arch/tile/include/uapi/asm/Kbuild
+++ /dev/null
@@ -1,24 +0,0 @@
-# UAPI Header export list
-include include/uapi/asm-generic/Kbuild.asm
-
-generic-y += bpf_perf_event.h
-generic-y += errno.h
-generic-y += fcntl.h
-generic-y += ioctl.h
-generic-y += ioctls.h
-generic-y += ipcbuf.h
-generic-y += msgbuf.h
-generic-y += param.h
-generic-y += poll.h
-generic-y += posix_types.h
-generic-y += resource.h
-generic-y += sembuf.h
-generic-y += shmbuf.h
-generic-y += shmparam.h
-generic-y += socket.h
-generic-y += sockios.h
-generic-y += statfs.h
-generic-y += termbits.h
-generic-y += termios.h
-generic-y += types.h
-generic-y += ucontext.h
diff --git a/arch/tile/include/uapi/asm/auxvec.h b/arch/tile/include/uapi/asm/auxvec.h
deleted file mode 100644
index 922383ce8f4f..000000000000
--- a/arch/tile/include/uapi/asm/auxvec.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_AUXVEC_H
-#define _ASM_TILE_AUXVEC_H
-
-/* The vDSO location. */
-#define AT_SYSINFO_EHDR 33
-
-#define AT_VECTOR_SIZE_ARCH 1 /* entries in ARCH_DLINFO */
-
-#endif /* _ASM_TILE_AUXVEC_H */
diff --git a/arch/tile/include/uapi/asm/bitsperlong.h b/arch/tile/include/uapi/asm/bitsperlong.h
deleted file mode 100644
index 57cca78c0fbb..000000000000
--- a/arch/tile/include/uapi/asm/bitsperlong.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_BITSPERLONG_H
-#define _ASM_TILE_BITSPERLONG_H
-
-#ifdef __LP64__
-# define __BITS_PER_LONG 64
-#else
-# define __BITS_PER_LONG 32
-#endif
-
-#include <asm-generic/bitsperlong.h>
-
-#endif /* _ASM_TILE_BITSPERLONG_H */
diff --git a/arch/tile/include/uapi/asm/byteorder.h b/arch/tile/include/uapi/asm/byteorder.h
deleted file mode 100644
index d508e61c1e56..000000000000
--- a/arch/tile/include/uapi/asm/byteorder.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#if defined (__BIG_ENDIAN__)
-#include <linux/byteorder/big_endian.h>
-#else
-#include <linux/byteorder/little_endian.h>
-#endif
diff --git a/arch/tile/include/uapi/asm/cachectl.h b/arch/tile/include/uapi/asm/cachectl.h
deleted file mode 100644
index ed8bac28a1b9..000000000000
--- a/arch/tile/include/uapi/asm/cachectl.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_CACHECTL_H
-#define _ASM_TILE_CACHECTL_H
-
-/*
- * Options for cacheflush system call.
- *
- * The ICACHE flush is performed on all cores currently running the
- * current process's address space. The intent is for user
- * applications to be able to modify code, invoke the system call,
- * then allow arbitrary other threads in the same address space to see
- * the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE()
- * or more invalidates the entire icache on all cores in the address
- * spaces. (Note: currently this option invalidates the entire icache
- * regardless of the requested address and length, but we may choose
- * to honor the arguments at some point.)
- *
- * Flush and invalidation of memory can normally be performed with the
- * __insn_flush() and __insn_finv() instructions from userspace.
- * The DCACHE option to the system call allows userspace
- * to flush the entire L1+L2 data cache from the core. In this case,
- * the address and length arguments are not used. The DCACHE flush is
- * restricted to the current core, not all cores in the address space.
- */
-#define ICACHE (1<<0) /* invalidate L1 instruction cache */
-#define DCACHE (1<<1) /* flush and invalidate data cache */
-#define BCACHE (ICACHE|DCACHE) /* flush both caches */
-
-#endif /* _ASM_TILE_CACHECTL_H */
diff --git a/arch/tile/include/uapi/asm/hardwall.h b/arch/tile/include/uapi/asm/hardwall.h
deleted file mode 100644
index f02e9132ae71..000000000000
--- a/arch/tile/include/uapi/asm/hardwall.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Provide methods for access control of per-cpu resources like
- * UDN, IDN, or IPI.
- */
-
-#ifndef _UAPI_ASM_TILE_HARDWALL_H
-#define _UAPI_ASM_TILE_HARDWALL_H
-
-#include <arch/chip.h>
-#include <linux/ioctl.h>
-
-#define HARDWALL_IOCTL_BASE 0xa2
-
-/*
- * The HARDWALL_CREATE() ioctl is a macro with a "size" argument.
- * The resulting ioctl value is passed to the kernel in conjunction
- * with a pointer to a standard kernel bitmask of cpus.
- * For network resources (UDN or IDN) the bitmask must physically
- * represent a rectangular configuration on the chip.
- * The "size" is the number of bytes of cpu mask data.
- */
-#define _HARDWALL_CREATE 1
-#define HARDWALL_CREATE(size) \
- _IOC(_IOC_READ, HARDWALL_IOCTL_BASE, _HARDWALL_CREATE, (size))
-
-#define _HARDWALL_ACTIVATE 2
-#define HARDWALL_ACTIVATE \
- _IO(HARDWALL_IOCTL_BASE, _HARDWALL_ACTIVATE)
-
-#define _HARDWALL_DEACTIVATE 3
-#define HARDWALL_DEACTIVATE \
- _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE)
-
-#define _HARDWALL_GET_ID 4
-#define HARDWALL_GET_ID \
- _IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID)
-
-
-#endif /* _UAPI_ASM_TILE_HARDWALL_H */
diff --git a/arch/tile/include/uapi/asm/kvm_para.h b/arch/tile/include/uapi/asm/kvm_para.h
deleted file mode 100644
index baacc4996d18..000000000000
--- a/arch/tile/include/uapi/asm/kvm_para.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#include <asm-generic/kvm_para.h>
diff --git a/arch/tile/include/uapi/asm/mman.h b/arch/tile/include/uapi/asm/mman.h
deleted file mode 100644
index 9b7add95926b..000000000000
--- a/arch/tile/include/uapi/asm/mman.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_MMAN_H
-#define _ASM_TILE_MMAN_H
-
-#include <asm-generic/mman-common.h>
-#include <arch/chip.h>
-
-/* Standard Linux flags */
-
-#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */
-#define MAP_NONBLOCK 0x0080 /* do not block on IO */
-#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
-#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */
-#define MAP_LOCKED 0x0200 /* pages are locked */
-#define MAP_NORESERVE 0x0400 /* don't check for reservations */
-#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
-#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
-#define MAP_HUGETLB 0x4000 /* create a huge page mapping */
-
-
-/*
- * Flags for mlockall
- */
-#define MCL_CURRENT 1 /* lock all current mappings */
-#define MCL_FUTURE 2 /* lock all future mappings */
-#define MCL_ONFAULT 4 /* lock all pages that are faulted in */
-
-
-#endif /* _ASM_TILE_MMAN_H */
diff --git a/arch/tile/include/uapi/asm/ptrace.h b/arch/tile/include/uapi/asm/ptrace.h
deleted file mode 100644
index 667ed742f4dd..000000000000
--- a/arch/tile/include/uapi/asm/ptrace.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI_ASM_TILE_PTRACE_H
-#define _UAPI_ASM_TILE_PTRACE_H
-
-#include <arch/chip.h>
-#include <arch/abi.h>
-
-/* These must match struct pt_regs, below. */
-#if CHIP_WORD_SIZE() == 32
-#define PTREGS_OFFSET_REG(n) ((n)*4)
-#else
-#define PTREGS_OFFSET_REG(n) ((n)*8)
-#endif
-#define PTREGS_OFFSET_BASE 0
-#define PTREGS_OFFSET_TP PTREGS_OFFSET_REG(53)
-#define PTREGS_OFFSET_SP PTREGS_OFFSET_REG(54)
-#define PTREGS_OFFSET_LR PTREGS_OFFSET_REG(55)
-#define PTREGS_NR_GPRS 56
-#define PTREGS_OFFSET_PC PTREGS_OFFSET_REG(56)
-#define PTREGS_OFFSET_EX1 PTREGS_OFFSET_REG(57)
-#define PTREGS_OFFSET_FAULTNUM PTREGS_OFFSET_REG(58)
-#define PTREGS_OFFSET_ORIG_R0 PTREGS_OFFSET_REG(59)
-#define PTREGS_OFFSET_FLAGS PTREGS_OFFSET_REG(60)
-#if CHIP_HAS_CMPEXCH()
-#define PTREGS_OFFSET_CMPEXCH PTREGS_OFFSET_REG(61)
-#endif
-#define PTREGS_SIZE PTREGS_OFFSET_REG(64)
-
-
-#ifndef __ASSEMBLY__
-
-#ifndef __KERNEL__
-/* Provide appropriate length type to userspace regardless of -m32/-m64. */
-typedef uint_reg_t pt_reg_t;
-#endif
-
-/*
- * This struct defines the way the registers are stored on the stack during a
- * system call or exception. "struct sigcontext" has the same shape.
- */
-struct pt_regs {
- union {
- /* Saved main processor registers; 56..63 are special. */
- pt_reg_t regs[56];
- struct {
- pt_reg_t __regs[53];
- pt_reg_t tp; /* aliases regs[TREG_TP] */
- pt_reg_t sp; /* aliases regs[TREG_SP] */
- pt_reg_t lr; /* aliases regs[TREG_LR] */
- };
- };
-
- /* Saved special registers. */
- pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */
- pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
- pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
- pt_reg_t orig_r0; /* r0 at syscall entry, else zero */
- pt_reg_t flags; /* flags (see below) */
-#if !CHIP_HAS_CMPEXCH()
- pt_reg_t pad[3];
-#else
- pt_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
- pt_reg_t pad[2];
-#endif
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define PTRACE_GETREGS 12
-#define PTRACE_SETREGS 13
-#define PTRACE_GETFPREGS 14
-#define PTRACE_SETFPREGS 15
-
-/* Support TILE-specific ptrace options, with events starting at 16. */
-#define PTRACE_EVENT_MIGRATE 16
-#define PTRACE_O_TRACEMIGRATE (1 << PTRACE_EVENT_MIGRATE)
-
-/*
- * Flag bits in pt_regs.flags that are part of the ptrace API.
- * We start our numbering higher up to avoid confusion with the
- * non-ABI kernel-internal values that use the low 16 bits.
- */
-#define PT_FLAGS_COMPAT 0x10000 /* process is an -m32 compat process */
-
-#endif /* _UAPI_ASM_TILE_PTRACE_H */
diff --git a/arch/tile/include/uapi/asm/setup.h b/arch/tile/include/uapi/asm/setup.h
deleted file mode 100644
index 6d1dfdddad6c..000000000000
--- a/arch/tile/include/uapi/asm/setup.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI_ASM_TILE_SETUP_H
-#define _UAPI_ASM_TILE_SETUP_H
-
-#define COMMAND_LINE_SIZE 2048
-
-
-#endif /* _UAPI_ASM_TILE_SETUP_H */
diff --git a/arch/tile/include/uapi/asm/sigcontext.h b/arch/tile/include/uapi/asm/sigcontext.h
deleted file mode 100644
index 4003d5cc9202..000000000000
--- a/arch/tile/include/uapi/asm/sigcontext.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SIGCONTEXT_H
-#define _ASM_TILE_SIGCONTEXT_H
-
-/* Don't pollute the namespace since <signal.h> includes this file. */
-#define __need_int_reg_t
-#include <arch/abi.h>
-
-/*
- * struct sigcontext has the same shape as struct pt_regs,
- * but is simplified since we know the fault is from userspace.
- */
-struct sigcontext {
- __extension__ union {
- /* General-purpose registers. */
- __uint_reg_t gregs[56];
- __extension__ struct {
- __uint_reg_t __gregs[53];
- __uint_reg_t tp; /* Aliases gregs[TREG_TP]. */
- __uint_reg_t sp; /* Aliases gregs[TREG_SP]. */
- __uint_reg_t lr; /* Aliases gregs[TREG_LR]. */
- };
- };
- __uint_reg_t pc; /* Program counter. */
- __uint_reg_t ics; /* In Interrupt Critical Section? */
- __uint_reg_t faultnum; /* Fault number. */
- __uint_reg_t pad[5];
-};
-
-#endif /* _ASM_TILE_SIGCONTEXT_H */
diff --git a/arch/tile/include/uapi/asm/siginfo.h b/arch/tile/include/uapi/asm/siginfo.h
deleted file mode 100644
index a812fcbf4267..000000000000
--- a/arch/tile/include/uapi/asm/siginfo.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SIGINFO_H
-#define _ASM_TILE_SIGINFO_H
-
-#define __ARCH_SI_TRAPNO
-
-#ifdef __LP64__
-# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
-#endif
-
-#include <asm-generic/siginfo.h>
-
-#endif /* _ASM_TILE_SIGINFO_H */
diff --git a/arch/tile/include/uapi/asm/signal.h b/arch/tile/include/uapi/asm/signal.h
deleted file mode 100644
index 7b3c814e00f0..000000000000
--- a/arch/tile/include/uapi/asm/signal.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _UAPI_ASM_TILE_SIGNAL_H
-#define _UAPI_ASM_TILE_SIGNAL_H
-
-/* Do not notify a ptracer when this signal is handled. */
-#define SA_NOPTRACE 0x02000000u
-
-/* Used in earlier Tilera releases, so keeping for binary compatibility. */
-#define SA_RESTORER 0x04000000u
-
-#include <asm-generic/signal.h>
-
-
-#endif /* _UAPI_ASM_TILE_SIGNAL_H */
diff --git a/arch/tile/include/uapi/asm/stat.h b/arch/tile/include/uapi/asm/stat.h
deleted file mode 100644
index ea03de7d67aa..000000000000
--- a/arch/tile/include/uapi/asm/stat.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
-#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
-#endif
-#include <asm-generic/stat.h>
diff --git a/arch/tile/include/uapi/asm/swab.h b/arch/tile/include/uapi/asm/swab.h
deleted file mode 100644
index 36952353a31d..000000000000
--- a/arch/tile/include/uapi/asm/swab.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#ifndef _ASM_TILE_SWAB_H
-#define _ASM_TILE_SWAB_H
-
-/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
-#define __arch_swab32(x) __builtin_bswap32(x)
-#define __arch_swab64(x) __builtin_bswap64(x)
-#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
-
-#endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/uapi/asm/unistd.h b/arch/tile/include/uapi/asm/unistd.h
deleted file mode 100644
index 1a169ec92ef8..000000000000
--- a/arch/tile/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#define __ARCH_WANT_RENAMEAT
-#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
-/* Use the flavor of this syscall that matches the 32-bit API better. */
-#define __ARCH_WANT_SYNC_FILE_RANGE2
-#endif
-
-/* Use the standard ABI for syscalls. */
-#include <asm-generic/unistd.h>
-
-#define NR_syscalls __NR_syscalls
-
-/* Additional Tilera-specific syscalls. */
-#define __NR_cacheflush (__NR_arch_specific_syscall + 1)
-__SYSCALL(__NR_cacheflush, sys_cacheflush)
-
-#ifndef __tilegx__
-/* "Fast" syscalls provide atomic support for 32-bit chips. */
-#define __NR_FAST_cmpxchg -1
-#define __NR_FAST_atomic_update -2
-#define __NR_FAST_cmpxchg64 -3
-#define __NR_cmpxchg_badaddr (__NR_arch_specific_syscall + 0)
-__SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
-#endif
diff --git a/arch/tile/kernel/Makefile b/arch/tile/kernel/Makefile
deleted file mode 100644
index 3e43d78731a8..000000000000
--- a/arch/tile/kernel/Makefile
+++ /dev/null
@@ -1,38 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for the Linux/TILE kernel.
-#
-
-extra-y := vmlinux.lds head_$(BITS).o
-obj-y := backtrace.o entry.o hvglue.o irq.o messaging.o \
- pci-dma.o proc.o process.o ptrace.o reboot.o \
- setup.o signal.o single_step.o stack.o sys.o \
- sysfs.o time.o traps.o unaligned.o vdso.o \
- intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o
-
-ifdef CONFIG_FUNCTION_TRACER
-CFLAGS_REMOVE_ftrace.o = -pg
-CFLAGS_REMOVE_early_printk.o = -pg
-endif
-
-obj-$(CONFIG_HARDWALL) += hardwall.o
-obj-$(CONFIG_COMPAT) += compat.o compat_signal.o
-obj-$(CONFIG_SMP) += smpboot.o smp.o tlb.o
-obj-$(CONFIG_MODULES) += module.o
-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
-obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel_$(BITS).o
-ifdef CONFIG_TILEGX
-obj-$(CONFIG_PCI) += pci_gx.o
-else
-obj-$(CONFIG_PCI) += pci.o
-endif
-obj-$(CONFIG_PERF_EVENTS) += perf_event.o
-obj-$(CONFIG_USE_PMC) += pmc.o
-obj-$(CONFIG_TILE_USB) += usb.o
-obj-$(CONFIG_TILE_HVGLUE_TRACE) += hvglue_trace.o
-obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o mcount_64.o
-obj-$(CONFIG_KPROBES) += kprobes.o
-obj-$(CONFIG_KGDB) += kgdb.o
-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
-
-obj-y += vdso/
diff --git a/arch/tile/kernel/asm-offsets.c b/arch/tile/kernel/asm-offsets.c
deleted file mode 100644
index 375e7c321eef..000000000000
--- a/arch/tile/kernel/asm-offsets.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Generates definitions from c-type structures used by assembly sources.
- */
-
-/* Check for compatible compiler early in the build. */
-#ifdef CONFIG_TILEGX
-# ifndef __tilegx__
-# error Can only build TILE-Gx configurations with tilegx compiler
-# endif
-# ifndef __LP64__
-# error Must not specify -m32 when building the TILE-Gx kernel
-# endif
-#else
-# ifdef __tilegx__
-# error Can not build TILEPro configurations with tilegx compiler
-# endif
-#endif
-
-#include <linux/kbuild.h>
-#include <linux/thread_info.h>
-#include <linux/sched.h>
-#include <linux/hardirq.h>
-#include <linux/ptrace.h>
-#include <hv/hypervisor.h>
-
-void foo(void)
-{
- DEFINE(SINGLESTEP_STATE_BUFFER_OFFSET,
- offsetof(struct single_step_state, buffer));
- DEFINE(SINGLESTEP_STATE_FLAGS_OFFSET,
- offsetof(struct single_step_state, flags));
- DEFINE(SINGLESTEP_STATE_ORIG_PC_OFFSET,
- offsetof(struct single_step_state, orig_pc));
- DEFINE(SINGLESTEP_STATE_NEXT_PC_OFFSET,
- offsetof(struct single_step_state, next_pc));
- DEFINE(SINGLESTEP_STATE_BRANCH_NEXT_PC_OFFSET,
- offsetof(struct single_step_state, branch_next_pc));
- DEFINE(SINGLESTEP_STATE_UPDATE_VALUE_OFFSET,
- offsetof(struct single_step_state, update_value));
-
- DEFINE(THREAD_INFO_TASK_OFFSET,
- offsetof(struct thread_info, task));
- DEFINE(THREAD_INFO_FLAGS_OFFSET,
- offsetof(struct thread_info, flags));
- DEFINE(THREAD_INFO_STATUS_OFFSET,
- offsetof(struct thread_info, status));
- DEFINE(THREAD_INFO_HOMECACHE_CPU_OFFSET,
- offsetof(struct thread_info, homecache_cpu));
- DEFINE(THREAD_INFO_PREEMPT_COUNT_OFFSET,
- offsetof(struct thread_info, preempt_count));
- DEFINE(THREAD_INFO_STEP_STATE_OFFSET,
- offsetof(struct thread_info, step_state));
-#ifdef __tilegx__
- DEFINE(THREAD_INFO_UNALIGN_JIT_BASE_OFFSET,
- offsetof(struct thread_info, unalign_jit_base));
- DEFINE(THREAD_INFO_UNALIGN_JIT_TMP_OFFSET,
- offsetof(struct thread_info, unalign_jit_tmp));
-#endif
-
- DEFINE(TASK_STRUCT_THREAD_KSP_OFFSET,
- offsetof(struct task_struct, thread.ksp));
- DEFINE(TASK_STRUCT_THREAD_PC_OFFSET,
- offsetof(struct task_struct, thread.pc));
-
- DEFINE(HV_TOPOLOGY_WIDTH_OFFSET,
- offsetof(HV_Topology, width));
- DEFINE(HV_TOPOLOGY_HEIGHT_OFFSET,
- offsetof(HV_Topology, height));
-
- DEFINE(IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET,
- offsetof(irq_cpustat_t, irq_syscall_count));
-}
diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c
deleted file mode 100644
index f8b74ca83b92..000000000000
--- a/arch/tile/kernel/backtrace.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <asm/byteorder.h>
-#include <asm/backtrace.h>
-#include <asm/tile-desc.h>
-#include <arch/abi.h>
-
-#ifdef __tilegx__
-#define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE
-#define tile_decoded_instruction tilegx_decoded_instruction
-#define tile_mnemonic tilegx_mnemonic
-#define parse_insn_tile parse_insn_tilegx
-#define TILE_OPC_IRET TILEGX_OPC_IRET
-#define TILE_OPC_ADDI TILEGX_OPC_ADDI
-#define TILE_OPC_ADDLI TILEGX_OPC_ADDLI
-#define TILE_OPC_INFO TILEGX_OPC_INFO
-#define TILE_OPC_INFOL TILEGX_OPC_INFOL
-#define TILE_OPC_JRP TILEGX_OPC_JRP
-#define TILE_OPC_MOVE TILEGX_OPC_MOVE
-#define OPCODE_STORE TILEGX_OPC_ST
-typedef long long bt_int_reg_t;
-#else
-#define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE
-#define tile_decoded_instruction tilepro_decoded_instruction
-#define tile_mnemonic tilepro_mnemonic
-#define parse_insn_tile parse_insn_tilepro
-#define TILE_OPC_IRET TILEPRO_OPC_IRET
-#define TILE_OPC_ADDI TILEPRO_OPC_ADDI
-#define TILE_OPC_ADDLI TILEPRO_OPC_ADDLI
-#define TILE_OPC_INFO TILEPRO_OPC_INFO
-#define TILE_OPC_INFOL TILEPRO_OPC_INFOL
-#define TILE_OPC_JRP TILEPRO_OPC_JRP
-#define TILE_OPC_MOVE TILEPRO_OPC_MOVE
-#define OPCODE_STORE TILEPRO_OPC_SW
-typedef int bt_int_reg_t;
-#endif
-
-/* A decoded bundle used for backtracer analysis. */
-struct BacktraceBundle {
- tile_bundle_bits bits;
- int num_insns;
- struct tile_decoded_instruction
- insns[TILE_MAX_INSTRUCTIONS_PER_BUNDLE];
-};
-
-
-/* Locates an instruction inside the given bundle that
- * has the specified mnemonic, and whose first 'num_operands_to_match'
- * operands exactly match those in 'operand_values'.
- */
-static const struct tile_decoded_instruction *find_matching_insn(
- const struct BacktraceBundle *bundle,
- tile_mnemonic mnemonic,
- const int *operand_values,
- int num_operands_to_match)
-{
- int i, j;
- bool match;
-
- for (i = 0; i < bundle->num_insns; i++) {
- const struct tile_decoded_instruction *insn =
- &bundle->insns[i];
-
- if (insn->opcode->mnemonic != mnemonic)
- continue;
-
- match = true;
- for (j = 0; j < num_operands_to_match; j++) {
- if (operand_values[j] != insn->operand_values[j]) {
- match = false;
- break;
- }
- }
-
- if (match)
- return insn;
- }
-
- return NULL;
-}
-
-/* Does this bundle contain an 'iret' instruction? */
-static inline bool bt_has_iret(const struct BacktraceBundle *bundle)
-{
- return find_matching_insn(bundle, TILE_OPC_IRET, NULL, 0) != NULL;
-}
-
-/* Does this bundle contain an 'addi sp, sp, OFFSET' or
- * 'addli sp, sp, OFFSET' instruction, and if so, what is OFFSET?
- */
-static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
-{
- static const int vals[2] = { TREG_SP, TREG_SP };
-
- const struct tile_decoded_instruction *insn =
- find_matching_insn(bundle, TILE_OPC_ADDI, vals, 2);
- if (insn == NULL)
- insn = find_matching_insn(bundle, TILE_OPC_ADDLI, vals, 2);
-#ifdef __tilegx__
- if (insn == NULL)
- insn = find_matching_insn(bundle, TILEGX_OPC_ADDXLI, vals, 2);
- if (insn == NULL)
- insn = find_matching_insn(bundle, TILEGX_OPC_ADDXI, vals, 2);
-#endif
- if (insn == NULL)
- return false;
-
- *adjust = insn->operand_values[2];
- return true;
-}
-
-/* Does this bundle contain any 'info OP' or 'infol OP'
- * instruction, and if so, what are their OP? Note that OP is interpreted
- * as an unsigned value by this code since that's what the caller wants.
- * Returns the number of info ops found.
- */
-static int bt_get_info_ops(const struct BacktraceBundle *bundle,
- int operands[MAX_INFO_OPS_PER_BUNDLE])
-{
- int num_ops = 0;
- int i;
-
- for (i = 0; i < bundle->num_insns; i++) {
- const struct tile_decoded_instruction *insn =
- &bundle->insns[i];
-
- if (insn->opcode->mnemonic == TILE_OPC_INFO ||
- insn->opcode->mnemonic == TILE_OPC_INFOL) {
- operands[num_ops++] = insn->operand_values[0];
- }
- }
-
- return num_ops;
-}
-
-/* Does this bundle contain a jrp instruction, and if so, to which
- * register is it jumping?
- */
-static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg)
-{
- const struct tile_decoded_instruction *insn =
- find_matching_insn(bundle, TILE_OPC_JRP, NULL, 0);
- if (insn == NULL)
- return false;
-
- *target_reg = insn->operand_values[0];
- return true;
-}
-
-/* Does this bundle modify the specified register in any way? */
-static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg)
-{
- int i, j;
- for (i = 0; i < bundle->num_insns; i++) {
- const struct tile_decoded_instruction *insn =
- &bundle->insns[i];
-
- if (insn->opcode->implicitly_written_register == reg)
- return true;
-
- for (j = 0; j < insn->opcode->num_operands; j++)
- if (insn->operands[j]->is_dest_reg &&
- insn->operand_values[j] == reg)
- return true;
- }
-
- return false;
-}
-
-/* Does this bundle modify sp? */
-static inline bool bt_modifies_sp(const struct BacktraceBundle *bundle)
-{
- return bt_modifies_reg(bundle, TREG_SP);
-}
-
-/* Does this bundle modify lr? */
-static inline bool bt_modifies_lr(const struct BacktraceBundle *bundle)
-{
- return bt_modifies_reg(bundle, TREG_LR);
-}
-
-/* Does this bundle contain the instruction 'move fp, sp'? */
-static inline bool bt_has_move_r52_sp(const struct BacktraceBundle *bundle)
-{
- static const int vals[2] = { 52, TREG_SP };
- return find_matching_insn(bundle, TILE_OPC_MOVE, vals, 2) != NULL;
-}
-
-/* Does this bundle contain a store of lr to sp? */
-static inline bool bt_has_sw_sp_lr(const struct BacktraceBundle *bundle)
-{
- static const int vals[2] = { TREG_SP, TREG_LR };
- return find_matching_insn(bundle, OPCODE_STORE, vals, 2) != NULL;
-}
-
-#ifdef __tilegx__
-/* Track moveli values placed into registers. */
-static inline void bt_update_moveli(const struct BacktraceBundle *bundle,
- int moveli_args[])
-{
- int i;
- for (i = 0; i < bundle->num_insns; i++) {
- const struct tile_decoded_instruction *insn =
- &bundle->insns[i];
-
- if (insn->opcode->mnemonic == TILEGX_OPC_MOVELI) {
- int reg = insn->operand_values[0];
- moveli_args[reg] = insn->operand_values[1];
- }
- }
-}
-
-/* Does this bundle contain an 'add sp, sp, reg' instruction
- * from a register that we saw a moveli into, and if so, what
- * is the value in the register?
- */
-static bool bt_has_add_sp(const struct BacktraceBundle *bundle, int *adjust,
- int moveli_args[])
-{
- static const int vals[2] = { TREG_SP, TREG_SP };
-
- const struct tile_decoded_instruction *insn =
- find_matching_insn(bundle, TILEGX_OPC_ADDX, vals, 2);
- if (insn) {
- int reg = insn->operand_values[2];
- if (moveli_args[reg]) {
- *adjust = moveli_args[reg];
- return true;
- }
- }
- return false;
-}
-#endif
-
-/* Locates the caller's PC and SP for a program starting at the
- * given address.
- */
-static void find_caller_pc_and_caller_sp(CallerLocation *location,
- const unsigned long start_pc,
- BacktraceMemoryReader read_memory_func,
- void *read_memory_func_extra)
-{
- /* Have we explicitly decided what the sp is,
- * rather than just the default?
- */
- bool sp_determined = false;
-
- /* Has any bundle seen so far modified lr? */
- bool lr_modified = false;
-
- /* Have we seen a move from sp to fp? */
- bool sp_moved_to_r52 = false;
-
- /* Have we seen a terminating bundle? */
- bool seen_terminating_bundle = false;
-
- /* Cut down on round-trip reading overhead by reading several
- * bundles at a time.
- */
- tile_bundle_bits prefetched_bundles[32];
- int num_bundles_prefetched = 0;
- int next_bundle = 0;
- unsigned long pc;
-
-#ifdef __tilegx__
- /* Naively try to track moveli values to support addx for -m32. */
- int moveli_args[TILEGX_NUM_REGISTERS] = { 0 };
-#endif
-
- /* Default to assuming that the caller's sp is the current sp.
- * This is necessary to handle the case where we start backtracing
- * right at the end of the epilog.
- */
- location->sp_location = SP_LOC_OFFSET;
- location->sp_offset = 0;
-
- /* Default to having no idea where the caller PC is. */
- location->pc_location = PC_LOC_UNKNOWN;
-
- /* Don't even try if the PC is not aligned. */
- if (start_pc % TILE_BUNDLE_ALIGNMENT_IN_BYTES != 0)
- return;
-
- for (pc = start_pc;; pc += sizeof(tile_bundle_bits)) {
-
- struct BacktraceBundle bundle;
- int num_info_ops, info_operands[MAX_INFO_OPS_PER_BUNDLE];
- int one_ago, jrp_reg;
- bool has_jrp;
-
- if (next_bundle >= num_bundles_prefetched) {
- /* Prefetch some bytes, but don't cross a page
- * boundary since that might cause a read failure we
- * don't care about if we only need the first few
- * bytes. Note: we don't care what the actual page
- * size is; using the minimum possible page size will
- * prevent any problems.
- */
- unsigned int bytes_to_prefetch = 4096 - (pc & 4095);
- if (bytes_to_prefetch > sizeof prefetched_bundles)
- bytes_to_prefetch = sizeof prefetched_bundles;
-
- if (!read_memory_func(prefetched_bundles, pc,
- bytes_to_prefetch,
- read_memory_func_extra)) {
- if (pc == start_pc) {
- /* The program probably called a bad
- * address, such as a NULL pointer.
- * So treat this as if we are at the
- * start of the function prolog so the
- * backtrace will show how we got here.
- */
- location->pc_location = PC_LOC_IN_LR;
- return;
- }
-
- /* Unreadable address. Give up. */
- break;
- }
-
- next_bundle = 0;
- num_bundles_prefetched =
- bytes_to_prefetch / sizeof(tile_bundle_bits);
- }
-
- /*
- * Decode the next bundle.
- * TILE always stores instruction bundles in little-endian
- * mode, even when the chip is running in big-endian mode.
- */
- bundle.bits = le64_to_cpu(prefetched_bundles[next_bundle++]);
- bundle.num_insns =
- parse_insn_tile(bundle.bits, pc, bundle.insns);
- num_info_ops = bt_get_info_ops(&bundle, info_operands);
-
- /* First look at any one_ago info ops if they are interesting,
- * since they should shadow any non-one-ago info ops.
- */
- for (one_ago = (pc != start_pc) ? 1 : 0;
- one_ago >= 0; one_ago--) {
- int i;
- for (i = 0; i < num_info_ops; i++) {
- int info_operand = info_operands[i];
- if (info_operand < CALLER_UNKNOWN_BASE) {
- /* Weird; reserved value, ignore it. */
- continue;
- }
-
- /* Skip info ops which are not in the
- * "one_ago" mode we want right now.
- */
- if (((info_operand & ONE_BUNDLE_AGO_FLAG) != 0)
- != (one_ago != 0))
- continue;
-
- /* Clear the flag to make later checking
- * easier. */
- info_operand &= ~ONE_BUNDLE_AGO_FLAG;
-
- /* Default to looking at PC_IN_LR_FLAG. */
- if (info_operand & PC_IN_LR_FLAG)
- location->pc_location =
- PC_LOC_IN_LR;
- else
- location->pc_location =
- PC_LOC_ON_STACK;
-
- switch (info_operand) {
- case CALLER_UNKNOWN_BASE:
- location->pc_location = PC_LOC_UNKNOWN;
- location->sp_location = SP_LOC_UNKNOWN;
- return;
-
- case CALLER_SP_IN_R52_BASE:
- case CALLER_SP_IN_R52_BASE | PC_IN_LR_FLAG:
- location->sp_location = SP_LOC_IN_R52;
- return;
-
- default:
- {
- const unsigned int val = info_operand
- - CALLER_SP_OFFSET_BASE;
- const unsigned int sp_offset =
- (val >> NUM_INFO_OP_FLAGS) * 8;
- if (sp_offset < 32768) {
- /* This is a properly encoded
- * SP offset. */
- location->sp_location =
- SP_LOC_OFFSET;
- location->sp_offset =
- sp_offset;
- return;
- } else {
- /* This looked like an SP
- * offset, but it's outside
- * the legal range, so this
- * must be an unrecognized
- * info operand. Ignore it.
- */
- }
- }
- break;
- }
- }
- }
-
- if (seen_terminating_bundle) {
- /* We saw a terminating bundle during the previous
- * iteration, so we were only looking for an info op.
- */
- break;
- }
-
- if (bundle.bits == 0) {
- /* Wacky terminating bundle. Stop looping, and hope
- * we've already seen enough to find the caller.
- */
- break;
- }
-
- /*
- * Try to determine caller's SP.
- */
-
- if (!sp_determined) {
- int adjust;
- if (bt_has_addi_sp(&bundle, &adjust)
-#ifdef __tilegx__
- || bt_has_add_sp(&bundle, &adjust, moveli_args)
-#endif
- ) {
- location->sp_location = SP_LOC_OFFSET;
-
- if (adjust <= 0) {
- /* We are in prolog about to adjust
- * SP. */
- location->sp_offset = 0;
- } else {
- /* We are in epilog restoring SP. */
- location->sp_offset = adjust;
- }
-
- sp_determined = true;
- } else {
- if (bt_has_move_r52_sp(&bundle)) {
- /* Maybe in prolog, creating an
- * alloca-style frame. But maybe in
- * the middle of a fixed-size frame
- * clobbering r52 with SP.
- */
- sp_moved_to_r52 = true;
- }
-
- if (bt_modifies_sp(&bundle)) {
- if (sp_moved_to_r52) {
- /* We saw SP get saved into
- * r52 earlier (or now), which
- * must have been in the
- * prolog, so we now know that
- * SP is still holding the
- * caller's sp value.
- */
- location->sp_location =
- SP_LOC_OFFSET;
- location->sp_offset = 0;
- } else {
- /* Someone must have saved
- * aside the caller's SP value
- * into r52, so r52 holds the
- * current value.
- */
- location->sp_location =
- SP_LOC_IN_R52;
- }
- sp_determined = true;
- }
- }
-
-#ifdef __tilegx__
- /* Track moveli arguments for -m32 mode. */
- bt_update_moveli(&bundle, moveli_args);
-#endif
- }
-
- if (bt_has_iret(&bundle)) {
- /* This is a terminating bundle. */
- seen_terminating_bundle = true;
- continue;
- }
-
- /*
- * Try to determine caller's PC.
- */
-
- jrp_reg = -1;
- has_jrp = bt_has_jrp(&bundle, &jrp_reg);
- if (has_jrp)
- seen_terminating_bundle = true;
-
- if (location->pc_location == PC_LOC_UNKNOWN) {
- if (has_jrp) {
- if (jrp_reg == TREG_LR && !lr_modified) {
- /* Looks like a leaf function, or else
- * lr is already restored. */
- location->pc_location =
- PC_LOC_IN_LR;
- } else {
- location->pc_location =
- PC_LOC_ON_STACK;
- }
- } else if (bt_has_sw_sp_lr(&bundle)) {
- /* In prolog, spilling initial lr to stack. */
- location->pc_location = PC_LOC_IN_LR;
- } else if (bt_modifies_lr(&bundle)) {
- lr_modified = true;
- }
- }
- }
-}
-
-/* Initializes a backtracer to start from the given location.
- *
- * If the frame pointer cannot be determined it is set to -1.
- *
- * state: The state to be filled in.
- * read_memory_func: A callback that reads memory.
- * read_memory_func_extra: An arbitrary argument to read_memory_func.
- * pc: The current PC.
- * lr: The current value of the 'lr' register.
- * sp: The current value of the 'sp' register.
- * r52: The current value of the 'r52' register.
- */
-void backtrace_init(BacktraceIterator *state,
- BacktraceMemoryReader read_memory_func,
- void *read_memory_func_extra,
- unsigned long pc, unsigned long lr,
- unsigned long sp, unsigned long r52)
-{
- CallerLocation location;
- unsigned long fp, initial_frame_caller_pc;
-
- /* Find out where we are in the initial frame. */
- find_caller_pc_and_caller_sp(&location, pc,
- read_memory_func, read_memory_func_extra);
-
- switch (location.sp_location) {
- case SP_LOC_UNKNOWN:
- /* Give up. */
- fp = -1;
- break;
-
- case SP_LOC_IN_R52:
- fp = r52;
- break;
-
- case SP_LOC_OFFSET:
- fp = sp + location.sp_offset;
- break;
-
- default:
- /* Give up. */
- fp = -1;
- break;
- }
-
- /* If the frame pointer is not aligned to the basic word size
- * something terrible happened and we should mark it as invalid.
- */
- if (fp % sizeof(bt_int_reg_t) != 0)
- fp = -1;
-
- /* -1 means "don't know initial_frame_caller_pc". */
- initial_frame_caller_pc = -1;
-
- switch (location.pc_location) {
- case PC_LOC_UNKNOWN:
- /* Give up. */
- fp = -1;
- break;
-
- case PC_LOC_IN_LR:
- if (lr == 0 || lr % TILE_BUNDLE_ALIGNMENT_IN_BYTES != 0) {
- /* Give up. */
- fp = -1;
- } else {
- initial_frame_caller_pc = lr;
- }
- break;
-
- case PC_LOC_ON_STACK:
- /* Leave initial_frame_caller_pc as -1,
- * meaning check the stack.
- */
- break;
-
- default:
- /* Give up. */
- fp = -1;
- break;
- }
-
- state->pc = pc;
- state->sp = sp;
- state->fp = fp;
- state->initial_frame_caller_pc = initial_frame_caller_pc;
- state->read_memory_func = read_memory_func;
- state->read_memory_func_extra = read_memory_func_extra;
-}
-
-/* Handle the case where the register holds more bits than the VA. */
-static bool valid_addr_reg(bt_int_reg_t reg)
-{
- return ((unsigned long)reg == reg);
-}
-
-/* Advances the backtracing state to the calling frame, returning
- * true iff successful.
- */
-bool backtrace_next(BacktraceIterator *state)
-{
- unsigned long next_fp, next_pc;
- bt_int_reg_t next_frame[2];
-
- if (state->fp == -1) {
- /* No parent frame. */
- return false;
- }
-
- /* Try to read the frame linkage data chaining to the next function. */
- if (!state->read_memory_func(&next_frame, state->fp, sizeof next_frame,
- state->read_memory_func_extra)) {
- return false;
- }
-
- next_fp = next_frame[1];
- if (!valid_addr_reg(next_frame[1]) ||
- next_fp % sizeof(bt_int_reg_t) != 0) {
- /* Caller's frame pointer is suspect, so give up. */
- return false;
- }
-
- if (state->initial_frame_caller_pc != -1) {
- /* We must be in the initial stack frame and already know the
- * caller PC.
- */
- next_pc = state->initial_frame_caller_pc;
-
- /* Force reading stack next time, in case we were in the
- * initial frame. We don't do this above just to paranoidly
- * avoid changing the struct at all when we return false.
- */
- state->initial_frame_caller_pc = -1;
- } else {
- /* Get the caller PC from the frame linkage area. */
- next_pc = next_frame[0];
- if (!valid_addr_reg(next_frame[0]) || next_pc == 0 ||
- next_pc % TILE_BUNDLE_ALIGNMENT_IN_BYTES != 0) {
- /* The PC is suspect, so give up. */
- return false;
- }
- }
-
- /* Update state to become the caller's stack frame. */
- state->pc = next_pc;
- state->sp = state->fp;
- state->fp = next_fp;
-
- return true;
-}
diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c
deleted file mode 100644
index bdaf71d31a4a..000000000000
--- a/arch/tile/kernel/compat.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/* Adjust unistd.h to provide 32-bit numbers and functions. */
-#define __SYSCALL_COMPAT
-
-#include <linux/compat.h>
-#include <linux/syscalls.h>
-#include <linux/kdev_t.h>
-#include <linux/fs.h>
-#include <linux/fcntl.h>
-#include <linux/uaccess.h>
-#include <linux/signal.h>
-#include <asm/syscalls.h>
-#include <asm/byteorder.h>
-
-/*
- * Syscalls that take 64-bit numbers traditionally take them in 32-bit
- * "high" and "low" value parts on 32-bit architectures.
- * In principle, one could imagine passing some register arguments as
- * fully 64-bit on TILE-Gx in 32-bit mode, but it seems easier to
- * adopt the usual convention.
- */
-
-#ifdef __BIG_ENDIAN
-#define SYSCALL_PAIR(name) u32, name ## _hi, u32, name ## _lo
-#else
-#define SYSCALL_PAIR(name) u32, name ## _lo, u32, name ## _hi
-#endif
-
-COMPAT_SYSCALL_DEFINE4(truncate64, char __user *, filename, u32, dummy,
- SYSCALL_PAIR(length))
-{
- return sys_truncate(filename, ((loff_t)length_hi << 32) | length_lo);
-}
-
-COMPAT_SYSCALL_DEFINE4(ftruncate64, unsigned int, fd, u32, dummy,
- SYSCALL_PAIR(length))
-{
- return sys_ftruncate(fd, ((loff_t)length_hi << 32) | length_lo);
-}
-
-COMPAT_SYSCALL_DEFINE6(pread64, unsigned int, fd, char __user *, ubuf,
- size_t, count, u32, dummy, SYSCALL_PAIR(offset))
-{
- return sys_pread64(fd, ubuf, count,
- ((loff_t)offset_hi << 32) | offset_lo);
-}
-
-COMPAT_SYSCALL_DEFINE6(pwrite64, unsigned int, fd, char __user *, ubuf,
- size_t, count, u32, dummy, SYSCALL_PAIR(offset))
-{
- return sys_pwrite64(fd, ubuf, count,
- ((loff_t)offset_hi << 32) | offset_lo);
-}
-
-COMPAT_SYSCALL_DEFINE6(sync_file_range2, int, fd, unsigned int, flags,
- SYSCALL_PAIR(offset), SYSCALL_PAIR(nbytes))
-{
- return sys_sync_file_range(fd, ((loff_t)offset_hi << 32) | offset_lo,
- ((loff_t)nbytes_hi << 32) | nbytes_lo,
- flags);
-}
-
-COMPAT_SYSCALL_DEFINE6(fallocate, int, fd, int, mode,
- SYSCALL_PAIR(offset), SYSCALL_PAIR(len))
-{
- return sys_fallocate(fd, mode, ((loff_t)offset_hi << 32) | offset_lo,
- ((loff_t)len_hi << 32) | len_lo);
-}
-
-/*
- * Avoid bug in generic sys_llseek() that specifies offset_high and
- * offset_low as "unsigned long", thus making it possible to pass
- * a sign-extended high 32 bits in offset_low.
- * Note that we do not use SYSCALL_PAIR here since glibc passes the
- * high and low parts explicitly in that order.
- */
-COMPAT_SYSCALL_DEFINE5(llseek, unsigned int, fd, unsigned int, offset_high,
- unsigned int, offset_low, loff_t __user *, result,
- unsigned int, origin)
-{
- return sys_llseek(fd, offset_high, offset_low, result, origin);
-}
-
-/* Provide the compat syscall number to call mapping. */
-#undef __SYSCALL
-#define __SYSCALL(nr, call) [nr] = (call),
-
-/* See comments in sys.c */
-#define compat_sys_fadvise64_64 sys32_fadvise64_64
-#define compat_sys_readahead sys32_readahead
-#define sys_llseek compat_sys_llseek
-
-/* Call the assembly trampolines where necessary. */
-#define compat_sys_rt_sigreturn _compat_sys_rt_sigreturn
-#define sys_clone _sys_clone
-
-/*
- * Note that we can't include <linux/unistd.h> here since the header
- * guard will defeat us; <asm/unistd.h> checks for __SYSCALL as well.
- */
-void *compat_sys_call_table[__NR_syscalls] = {
- [0 ... __NR_syscalls-1] = sys_ni_syscall,
-#include <asm/unistd.h>
-};
diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c
deleted file mode 100644
index a703bd0e0488..000000000000
--- a/arch/tile/kernel/compat_signal.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/personality.h>
-#include <linux/suspend.h>
-#include <linux/ptrace.h>
-#include <linux/elf.h>
-#include <linux/compat.h>
-#include <linux/syscalls.h>
-#include <linux/uaccess.h>
-#include <asm/processor.h>
-#include <asm/ucontext.h>
-#include <asm/sigframe.h>
-#include <asm/syscalls.h>
-#include <asm/vdso.h>
-#include <arch/interrupts.h>
-
-struct compat_ucontext {
- compat_ulong_t uc_flags;
- compat_uptr_t uc_link;
- struct compat_sigaltstack uc_stack;
- struct sigcontext uc_mcontext;
- sigset_t uc_sigmask; /* mask last for extensibility */
-};
-
-struct compat_rt_sigframe {
- unsigned char save_area[C_ABI_SAVE_AREA_SIZE]; /* caller save area */
- struct compat_siginfo info;
- struct compat_ucontext uc;
-};
-
-/* The assembly shim for this function arranges to ignore the return value. */
-long compat_sys_rt_sigreturn(void)
-{
- struct pt_regs *regs = current_pt_regs();
- struct compat_rt_sigframe __user *frame =
- (struct compat_rt_sigframe __user *) compat_ptr(regs->sp);
- sigset_t set;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
- goto badframe;
-
- if (compat_restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return 0;
-
-badframe:
- signal_fault("bad sigreturn frame", regs, frame, 0);
- return 0;
-}
-
-/*
- * Determine which stack to use..
- */
-static inline void __user *compat_get_sigframe(struct k_sigaction *ka,
- struct pt_regs *regs,
- size_t frame_size)
-{
- unsigned long sp;
-
- /* Default to using normal stack */
- sp = (unsigned long)compat_ptr(regs->sp);
-
- /*
- * If we are on the alternate signal stack and would overflow
- * it, don't. Return an always-bogus address instead so we
- * will die with SIGSEGV.
- */
- if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size)))
- return (void __user __force *)-1UL;
-
- /* This is the X/Open sanctioned signal stack switching. */
- if (ka->sa.sa_flags & SA_ONSTACK) {
- if (sas_ss_flags(sp) == 0)
- sp = current->sas_ss_sp + current->sas_ss_size;
- }
-
- sp -= frame_size;
- /*
- * Align the stack pointer according to the TILE ABI,
- * i.e. so that on function entry (sp & 15) == 0.
- */
- sp &= -16UL;
- return (void __user *) sp;
-}
-
-int compat_setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- unsigned long restorer;
- struct compat_rt_sigframe __user *frame;
- int err = 0, sig = ksig->sig;
-
- frame = compat_get_sigframe(&ksig->ka, regs, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- goto err;
-
- /* Always write at least the signal number for the stack backtracer. */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO) {
- /* At sigreturn time, restore the callee-save registers too. */
- err |= copy_siginfo_to_user32(&frame->info, &ksig->info);
- regs->flags |= PT_FLAGS_RESTORE_REGS;
- } else {
- err |= __put_user(ksig->info.si_signo, &frame->info.si_signo);
- }
-
- /* Create the ucontext. */
- err |= __clear_user(&frame->save_area, sizeof(frame->save_area));
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(0, &frame->uc.uc_link);
- err |= __compat_save_altstack(&frame->uc.uc_stack, regs->sp);
- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs);
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
- if (err)
- goto err;
-
- restorer = VDSO_SYM(&__vdso_rt_sigreturn);
- if (ksig->ka.sa.sa_flags & SA_RESTORER)
- restorer = ptr_to_compat_reg(ksig->ka.sa.sa_restorer);
-
- /*
- * Set up registers for signal handler.
- * Registers that we don't modify keep the value they had from
- * user-space at the time we took the signal.
- * We always pass siginfo and mcontext, regardless of SA_SIGINFO,
- * since some things rely on this (e.g. glibc's debug/segfault.c).
- */
- regs->pc = ptr_to_compat_reg(ksig->ka.sa.sa_handler);
- regs->ex1 = PL_ICS_EX1(USER_PL, 1); /* set crit sec in handler */
- regs->sp = ptr_to_compat_reg(frame);
- regs->lr = restorer;
- regs->regs[0] = (unsigned long) sig;
- regs->regs[1] = ptr_to_compat_reg(&frame->info);
- regs->regs[2] = ptr_to_compat_reg(&frame->uc);
- regs->flags |= PT_FLAGS_CALLER_SAVES;
- return 0;
-
-err:
- trace_unhandled_signal("bad sigreturn frame", regs,
- (unsigned long)frame, SIGSEGV);
- return -EFAULT;
-}
diff --git a/arch/tile/kernel/early_printk.c b/arch/tile/kernel/early_printk.c
deleted file mode 100644
index aefb2c086726..000000000000
--- a/arch/tile/kernel/early_printk.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/console.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/irqflags.h>
-#include <linux/printk.h>
-#include <asm/setup.h>
-#include <hv/hypervisor.h>
-
-static void early_hv_write(struct console *con, const char *s, unsigned n)
-{
- tile_console_write(s, n);
-
- /*
- * Convert NL to NLCR (close enough to CRNL) during early boot.
- * We assume newlines are at the ends of strings, which turns out
- * to be good enough for early boot console output.
- */
- if (n && s[n-1] == '\n')
- tile_console_write("\r", 1);
-}
-
-static struct console early_hv_console = {
- .name = "earlyhv",
- .write = early_hv_write,
- .flags = CON_PRINTBUFFER | CON_BOOT,
- .index = -1,
-};
-
-void early_panic(const char *fmt, ...)
-{
- struct va_format vaf;
- va_list args;
-
- arch_local_irq_disable_all();
-
- va_start(args, fmt);
-
- vaf.fmt = fmt;
- vaf.va = &args;
-
- early_printk("Kernel panic - not syncing: %pV", &vaf);
-
- va_end(args);
-
- dump_stack();
- hv_halt();
-}
-
-static int __init setup_early_printk(char *str)
-{
- if (early_console)
- return 1;
-
- early_console = &early_hv_console;
- register_console(early_console);
-
- return 0;
-}
-
-early_param("earlyprintk", setup_early_printk);
diff --git a/arch/tile/kernel/entry.S b/arch/tile/kernel/entry.S
deleted file mode 100644
index 101de132e363..000000000000
--- a/arch/tile/kernel/entry.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/linkage.h>
-#include <linux/unistd.h>
-#include <asm/irqflags.h>
-#include <asm/processor.h>
-#include <arch/abi.h>
-#include <arch/spr_def.h>
-
-#ifdef __tilegx__
-#define bnzt bnezt
-#endif
-
-STD_ENTRY(current_text_addr)
- { move r0, lr; jrp lr }
- STD_ENDPROC(current_text_addr)
-
-STD_ENTRY(KBacktraceIterator_init_current)
- { move r2, lr; lnk r1 }
- { move r4, r52; addli r1, r1, KBacktraceIterator_init_current - . }
- { move r3, sp; j _KBacktraceIterator_init_current }
- jrp lr /* keep backtracer happy */
- STD_ENDPROC(KBacktraceIterator_init_current)
-
-/* Loop forever on a nap during SMP boot. */
-STD_ENTRY(smp_nap)
- nap
- nop /* avoid provoking the icache prefetch with a jump */
- j smp_nap /* we are not architecturally guaranteed not to exit nap */
- jrp lr /* clue in the backtracer */
- STD_ENDPROC(smp_nap)
-
-/*
- * Enable interrupts racelessly and then nap until interrupted.
- * Architecturally, we are guaranteed that enabling interrupts via
- * mtspr to INTERRUPT_CRITICAL_SECTION only interrupts at the next PC.
- * This function's _cpu_idle_nap address is special; see intvec.S.
- * When interrupted at _cpu_idle_nap, we bump the PC forward 8, and
- * as a result return to the function that called _cpu_idle().
- */
-STD_ENTRY_SECTION(_cpu_idle, .cpuidle.text)
- movei r1, 1
- IRQ_ENABLE_LOAD(r2, r3)
- mtspr INTERRUPT_CRITICAL_SECTION, r1
- IRQ_ENABLE_APPLY(r2, r3) /* unmask, but still with ICS set */
- mtspr INTERRUPT_CRITICAL_SECTION, zero
- .global _cpu_idle_nap
-_cpu_idle_nap:
- nap
- nop /* avoid provoking the icache prefetch with a jump */
- jrp lr
- STD_ENDPROC(_cpu_idle)
diff --git a/arch/tile/kernel/ftrace.c b/arch/tile/kernel/ftrace.c
deleted file mode 100644
index b827a418b155..000000000000
--- a/arch/tile/kernel/ftrace.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE-Gx specific ftrace support
- */
-
-#include <linux/ftrace.h>
-#include <linux/uaccess.h>
-
-#include <asm/cacheflush.h>
-#include <asm/ftrace.h>
-#include <asm/sections.h>
-#include <asm/insn.h>
-
-#include <arch/opcode.h>
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
-static int machine_stopped __read_mostly;
-
-int ftrace_arch_code_modify_prepare(void)
-{
- machine_stopped = 1;
- return 0;
-}
-
-int ftrace_arch_code_modify_post_process(void)
-{
- flush_icache_range(0, CHIP_L1I_CACHE_SIZE());
- machine_stopped = 0;
- return 0;
-}
-
-/*
- * Put { move r10, lr; jal ftrace_caller } in a bundle, this lets dynamic
- * tracer just add one cycle overhead to every kernel function when disabled.
- */
-static unsigned long ftrace_gen_branch(unsigned long pc, unsigned long addr,
- bool link)
-{
- tilegx_bundle_bits opcode_x0, opcode_x1;
- long pcrel_by_instr = (addr - pc) >> TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES;
-
- if (link) {
- /* opcode: jal addr */
- opcode_x1 =
- create_Opcode_X1(JUMP_OPCODE_X1) |
- create_JumpOpcodeExtension_X1(JAL_JUMP_OPCODE_X1) |
- create_JumpOff_X1(pcrel_by_instr);
- } else {
- /* opcode: j addr */
- opcode_x1 =
- create_Opcode_X1(JUMP_OPCODE_X1) |
- create_JumpOpcodeExtension_X1(J_JUMP_OPCODE_X1) |
- create_JumpOff_X1(pcrel_by_instr);
- }
-
- /*
- * Also put { move r10, lr; jal ftrace_stub } in a bundle, which
- * is used to replace the instruction in address ftrace_call.
- */
- if (addr == FTRACE_ADDR || addr == (unsigned long)ftrace_stub) {
- /* opcode: or r10, lr, zero */
- opcode_x0 =
- create_Dest_X0(10) |
- create_SrcA_X0(TREG_LR) |
- create_SrcB_X0(TREG_ZERO) |
- create_RRROpcodeExtension_X0(OR_RRR_0_OPCODE_X0) |
- create_Opcode_X0(RRR_0_OPCODE_X0);
- } else {
- /* opcode: fnop */
- opcode_x0 =
- create_UnaryOpcodeExtension_X0(FNOP_UNARY_OPCODE_X0) |
- create_RRROpcodeExtension_X0(UNARY_RRR_0_OPCODE_X0) |
- create_Opcode_X0(RRR_0_OPCODE_X0);
- }
-
- return opcode_x1 | opcode_x0;
-}
-
-static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec)
-{
- return NOP();
-}
-
-static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
-{
- return ftrace_gen_branch(pc, addr, true);
-}
-
-static int ftrace_modify_code(unsigned long pc, unsigned long old,
- unsigned long new)
-{
- unsigned long pc_wr;
-
- /* Check if the address is in kernel text space and module space. */
- if (!kernel_text_address(pc))
- return -EINVAL;
-
- /* Operate on writable kernel text mapping. */
- pc_wr = ktext_writable_addr(pc);
-
- if (probe_kernel_write((void *)pc_wr, &new, MCOUNT_INSN_SIZE))
- return -EPERM;
-
- smp_wmb();
-
- if (!machine_stopped && num_online_cpus() > 1)
- flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
-
- return 0;
-}
-
-int ftrace_update_ftrace_func(ftrace_func_t func)
-{
- unsigned long pc, old;
- unsigned long new;
- int ret;
-
- pc = (unsigned long)&ftrace_call;
- memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE);
- new = ftrace_call_replace(pc, (unsigned long)func);
-
- ret = ftrace_modify_code(pc, old, new);
-
- return ret;
-}
-
-int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
-{
- unsigned long new, old;
- unsigned long ip = rec->ip;
-
- old = ftrace_nop_replace(rec);
- new = ftrace_call_replace(ip, addr);
-
- return ftrace_modify_code(rec->ip, old, new);
-}
-
-int ftrace_make_nop(struct module *mod,
- struct dyn_ftrace *rec, unsigned long addr)
-{
- unsigned long ip = rec->ip;
- unsigned long old;
- unsigned long new;
- int ret;
-
- old = ftrace_call_replace(ip, addr);
- new = ftrace_nop_replace(rec);
- ret = ftrace_modify_code(ip, old, new);
-
- return ret;
-}
-
-int __init ftrace_dyn_arch_init(void)
-{
- return 0;
-}
-#endif /* CONFIG_DYNAMIC_FTRACE */
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
- unsigned long frame_pointer)
-{
- unsigned long return_hooker = (unsigned long) &return_to_handler;
- struct ftrace_graph_ent trace;
- unsigned long old;
- int err;
-
- if (unlikely(atomic_read(&current->tracing_graph_pause)))
- return;
-
- old = *parent;
- *parent = return_hooker;
-
- err = ftrace_push_return_trace(old, self_addr, &trace.depth,
- frame_pointer, NULL);
- if (err == -EBUSY) {
- *parent = old;
- return;
- }
-
- trace.func = self_addr;
-
- /* Only trace if the calling function expects to */
- if (!ftrace_graph_entry(&trace)) {
- current->curr_ret_stack--;
- *parent = old;
- }
-}
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-extern unsigned long ftrace_graph_call;
-
-static int __ftrace_modify_caller(unsigned long *callsite,
- void (*func) (void), bool enable)
-{
- unsigned long caller_fn = (unsigned long) func;
- unsigned long pc = (unsigned long) callsite;
- unsigned long branch = ftrace_gen_branch(pc, caller_fn, false);
- unsigned long nop = NOP();
- unsigned long old = enable ? nop : branch;
- unsigned long new = enable ? branch : nop;
-
- return ftrace_modify_code(pc, old, new);
-}
-
-static int ftrace_modify_graph_caller(bool enable)
-{
- int ret;
-
- ret = __ftrace_modify_caller(&ftrace_graph_call,
- ftrace_graph_caller,
- enable);
-
- return ret;
-}
-
-int ftrace_enable_ftrace_graph_caller(void)
-{
- return ftrace_modify_graph_caller(true);
-}
-
-int ftrace_disable_ftrace_graph_caller(void)
-{
- return ftrace_modify_graph_caller(false);
-}
-#endif /* CONFIG_DYNAMIC_FTRACE */
-#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/tile/kernel/hardwall.c b/arch/tile/kernel/hardwall.c
deleted file mode 100644
index 2fd1694ac1d0..000000000000
--- a/arch/tile/kernel/hardwall.c
+++ /dev/null
@@ -1,1096 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/fs.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
-#include <linux/rwsem.h>
-#include <linux/kprobes.h>
-#include <linux/sched.h>
-#include <linux/hardirq.h>
-#include <linux/uaccess.h>
-#include <linux/smp.h>
-#include <linux/cdev.h>
-#include <linux/compat.h>
-#include <asm/hardwall.h>
-#include <asm/traps.h>
-#include <asm/siginfo.h>
-#include <asm/irq_regs.h>
-
-#include <arch/interrupts.h>
-#include <arch/spr_def.h>
-
-
-/*
- * Implement a per-cpu "hardwall" resource class such as UDN or IPI.
- * We use "hardwall" nomenclature throughout for historical reasons.
- * The lock here controls access to the list data structure as well as
- * to the items on the list.
- */
-struct hardwall_type {
- int index;
- int is_xdn;
- int is_idn;
- int disabled;
- const char *name;
- struct list_head list;
- spinlock_t lock;
- struct proc_dir_entry *proc_dir;
-};
-
-enum hardwall_index {
- HARDWALL_UDN = 0,
-#ifndef __tilepro__
- HARDWALL_IDN = 1,
- HARDWALL_IPI = 2,
-#endif
- _HARDWALL_TYPES
-};
-
-static struct hardwall_type hardwall_types[] = {
- { /* user-space access to UDN */
- 0,
- 1,
- 0,
- 0,
- "udn",
- LIST_HEAD_INIT(hardwall_types[HARDWALL_UDN].list),
- __SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_UDN].lock),
- NULL
- },
-#ifndef __tilepro__
- { /* user-space access to IDN */
- 1,
- 1,
- 1,
- 1, /* disabled pending hypervisor support */
- "idn",
- LIST_HEAD_INIT(hardwall_types[HARDWALL_IDN].list),
- __SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_IDN].lock),
- NULL
- },
- { /* access to user-space IPI */
- 2,
- 0,
- 0,
- 0,
- "ipi",
- LIST_HEAD_INIT(hardwall_types[HARDWALL_IPI].list),
- __SPIN_LOCK_UNLOCKED(hardwall_types[HARDWALL_IPI].lock),
- NULL
- },
-#endif
-};
-
-/*
- * This data structure tracks the cpu data, etc., associated
- * one-to-one with a "struct file *" from opening a hardwall device file.
- * Note that the file's private data points back to this structure.
- */
-struct hardwall_info {
- struct list_head list; /* for hardwall_types.list */
- struct list_head task_head; /* head of tasks in this hardwall */
- struct hardwall_type *type; /* type of this resource */
- struct cpumask cpumask; /* cpus reserved */
- int id; /* integer id for this hardwall */
- int teardown_in_progress; /* are we tearing this one down? */
-
- /* Remaining fields only valid for user-network resources. */
- int ulhc_x; /* upper left hand corner x coord */
- int ulhc_y; /* upper left hand corner y coord */
- int width; /* rectangle width */
- int height; /* rectangle height */
-#if CHIP_HAS_REV1_XDN()
- atomic_t xdn_pending_count; /* cores in phase 1 of drain */
-#endif
-};
-
-
-/* /proc/tile/hardwall */
-static struct proc_dir_entry *hardwall_proc_dir;
-
-/* Functions to manage files in /proc/tile/hardwall. */
-static void hardwall_add_proc(struct hardwall_info *);
-static void hardwall_remove_proc(struct hardwall_info *);
-
-/* Allow disabling UDN access. */
-static int __init noudn(char *str)
-{
- pr_info("User-space UDN access is disabled\n");
- hardwall_types[HARDWALL_UDN].disabled = 1;
- return 0;
-}
-early_param("noudn", noudn);
-
-#ifndef __tilepro__
-/* Allow disabling IDN access. */
-static int __init noidn(char *str)
-{
- pr_info("User-space IDN access is disabled\n");
- hardwall_types[HARDWALL_IDN].disabled = 1;
- return 0;
-}
-early_param("noidn", noidn);
-
-/* Allow disabling IPI access. */
-static int __init noipi(char *str)
-{
- pr_info("User-space IPI access is disabled\n");
- hardwall_types[HARDWALL_IPI].disabled = 1;
- return 0;
-}
-early_param("noipi", noipi);
-#endif
-
-
-/*
- * Low-level primitives for UDN/IDN
- */
-
-#ifdef __tilepro__
-#define mtspr_XDN(hwt, name, val) \
- do { (void)(hwt); __insn_mtspr(SPR_UDN_##name, (val)); } while (0)
-#define mtspr_MPL_XDN(hwt, name, val) \
- do { (void)(hwt); __insn_mtspr(SPR_MPL_UDN_##name, (val)); } while (0)
-#define mfspr_XDN(hwt, name) \
- ((void)(hwt), __insn_mfspr(SPR_UDN_##name))
-#else
-#define mtspr_XDN(hwt, name, val) \
- do { \
- if ((hwt)->is_idn) \
- __insn_mtspr(SPR_IDN_##name, (val)); \
- else \
- __insn_mtspr(SPR_UDN_##name, (val)); \
- } while (0)
-#define mtspr_MPL_XDN(hwt, name, val) \
- do { \
- if ((hwt)->is_idn) \
- __insn_mtspr(SPR_MPL_IDN_##name, (val)); \
- else \
- __insn_mtspr(SPR_MPL_UDN_##name, (val)); \
- } while (0)
-#define mfspr_XDN(hwt, name) \
- ((hwt)->is_idn ? __insn_mfspr(SPR_IDN_##name) : __insn_mfspr(SPR_UDN_##name))
-#endif
-
-/* Set a CPU bit if the CPU is online. */
-#define cpu_online_set(cpu, dst) do { \
- if (cpu_online(cpu)) \
- cpumask_set_cpu(cpu, dst); \
-} while (0)
-
-
-/* Does the given rectangle contain the given x,y coordinate? */
-static int contains(struct hardwall_info *r, int x, int y)
-{
- return (x >= r->ulhc_x && x < r->ulhc_x + r->width) &&
- (y >= r->ulhc_y && y < r->ulhc_y + r->height);
-}
-
-/* Compute the rectangle parameters and validate the cpumask. */
-static int check_rectangle(struct hardwall_info *r, struct cpumask *mask)
-{
- int x, y, cpu, ulhc, lrhc;
-
- /* The first cpu is the ULHC, the last the LRHC. */
- ulhc = find_first_bit(cpumask_bits(mask), nr_cpumask_bits);
- lrhc = find_last_bit(cpumask_bits(mask), nr_cpumask_bits);
-
- /* Compute the rectangle attributes from the cpus. */
- r->ulhc_x = cpu_x(ulhc);
- r->ulhc_y = cpu_y(ulhc);
- r->width = cpu_x(lrhc) - r->ulhc_x + 1;
- r->height = cpu_y(lrhc) - r->ulhc_y + 1;
-
- /* Width and height must be positive */
- if (r->width <= 0 || r->height <= 0)
- return -EINVAL;
-
- /* Confirm that the cpumask is exactly the rectangle. */
- for (y = 0, cpu = 0; y < smp_height; ++y)
- for (x = 0; x < smp_width; ++x, ++cpu)
- if (cpumask_test_cpu(cpu, mask) != contains(r, x, y))
- return -EINVAL;
-
- /*
- * Note that offline cpus can't be drained when this user network
- * rectangle eventually closes. We used to detect this
- * situation and print a warning, but it annoyed users and
- * they ignored it anyway, so now we just return without a
- * warning.
- */
- return 0;
-}
-
-/*
- * Hardware management of hardwall setup, teardown, trapping,
- * and enabling/disabling PL0 access to the networks.
- */
-
-/* Bit field values to mask together for writes to SPR_XDN_DIRECTION_PROTECT */
-enum direction_protect {
- N_PROTECT = (1 << 0),
- E_PROTECT = (1 << 1),
- S_PROTECT = (1 << 2),
- W_PROTECT = (1 << 3),
- C_PROTECT = (1 << 4),
-};
-
-static inline int xdn_which_interrupt(struct hardwall_type *hwt)
-{
-#ifndef __tilepro__
- if (hwt->is_idn)
- return INT_IDN_FIREWALL;
-#endif
- return INT_UDN_FIREWALL;
-}
-
-static void enable_firewall_interrupts(struct hardwall_type *hwt)
-{
- arch_local_irq_unmask_now(xdn_which_interrupt(hwt));
-}
-
-static void disable_firewall_interrupts(struct hardwall_type *hwt)
-{
- arch_local_irq_mask_now(xdn_which_interrupt(hwt));
-}
-
-/* Set up hardwall on this cpu based on the passed hardwall_info. */
-static void hardwall_setup_func(void *info)
-{
- struct hardwall_info *r = info;
- struct hardwall_type *hwt = r->type;
-
- int cpu = smp_processor_id(); /* on_each_cpu disables preemption */
- int x = cpu_x(cpu);
- int y = cpu_y(cpu);
- int bits = 0;
- if (x == r->ulhc_x)
- bits |= W_PROTECT;
- if (x == r->ulhc_x + r->width - 1)
- bits |= E_PROTECT;
- if (y == r->ulhc_y)
- bits |= N_PROTECT;
- if (y == r->ulhc_y + r->height - 1)
- bits |= S_PROTECT;
- BUG_ON(bits == 0);
- mtspr_XDN(hwt, DIRECTION_PROTECT, bits);
- enable_firewall_interrupts(hwt);
-}
-
-/* Set up all cpus on edge of rectangle to enable/disable hardwall SPRs. */
-static void hardwall_protect_rectangle(struct hardwall_info *r)
-{
- int x, y, cpu, delta;
- struct cpumask rect_cpus;
-
- cpumask_clear(&rect_cpus);
-
- /* First include the top and bottom edges */
- cpu = r->ulhc_y * smp_width + r->ulhc_x;
- delta = (r->height - 1) * smp_width;
- for (x = 0; x < r->width; ++x, ++cpu) {
- cpu_online_set(cpu, &rect_cpus);
- cpu_online_set(cpu + delta, &rect_cpus);
- }
-
- /* Then the left and right edges */
- cpu -= r->width;
- delta = r->width - 1;
- for (y = 0; y < r->height; ++y, cpu += smp_width) {
- cpu_online_set(cpu, &rect_cpus);
- cpu_online_set(cpu + delta, &rect_cpus);
- }
-
- /* Then tell all the cpus to set up their protection SPR */
- on_each_cpu_mask(&rect_cpus, hardwall_setup_func, r, 1);
-}
-
-/* Entered from INT_xDN_FIREWALL interrupt vector with irqs disabled. */
-void __kprobes do_hardwall_trap(struct pt_regs* regs, int fault_num)
-{
- struct hardwall_info *rect;
- struct hardwall_type *hwt;
- struct task_struct *p;
- struct siginfo info;
- int cpu = smp_processor_id();
- int found_processes;
- struct pt_regs *old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- /* Figure out which network trapped. */
- switch (fault_num) {
-#ifndef __tilepro__
- case INT_IDN_FIREWALL:
- hwt = &hardwall_types[HARDWALL_IDN];
- break;
-#endif
- case INT_UDN_FIREWALL:
- hwt = &hardwall_types[HARDWALL_UDN];
- break;
- default:
- BUG();
- }
- BUG_ON(hwt->disabled);
-
- /* This tile trapped a network access; find the rectangle. */
- spin_lock(&hwt->lock);
- list_for_each_entry(rect, &hwt->list, list) {
- if (cpumask_test_cpu(cpu, &rect->cpumask))
- break;
- }
-
- /*
- * It shouldn't be possible not to find this cpu on the
- * rectangle list, since only cpus in rectangles get hardwalled.
- * The hardwall is only removed after the user network is drained.
- */
- BUG_ON(&rect->list == &hwt->list);
-
- /*
- * If we already started teardown on this hardwall, don't worry;
- * the abort signal has been sent and we are just waiting for things
- * to quiesce.
- */
- if (rect->teardown_in_progress) {
- pr_notice("cpu %d: detected %s hardwall violation %#lx while teardown already in progress\n",
- cpu, hwt->name,
- (long)mfspr_XDN(hwt, DIRECTION_PROTECT));
- goto done;
- }
-
- /*
- * Kill off any process that is activated in this rectangle.
- * We bypass security to deliver the signal, since it must be
- * one of the activated processes that generated the user network
- * message that caused this trap, and all the activated
- * processes shared a single open file so are pretty tightly
- * bound together from a security point of view to begin with.
- */
- rect->teardown_in_progress = 1;
- wmb(); /* Ensure visibility of rectangle before notifying processes. */
- pr_notice("cpu %d: detected %s hardwall violation %#lx...\n",
- cpu, hwt->name, (long)mfspr_XDN(hwt, DIRECTION_PROTECT));
- info.si_signo = SIGILL;
- info.si_errno = 0;
- info.si_code = ILL_HARDWALL;
- found_processes = 0;
- list_for_each_entry(p, &rect->task_head,
- thread.hardwall[hwt->index].list) {
- BUG_ON(p->thread.hardwall[hwt->index].info != rect);
- if (!(p->flags & PF_EXITING)) {
- found_processes = 1;
- pr_notice("hardwall: killing %d\n", p->pid);
- do_send_sig_info(info.si_signo, &info, p, false);
- }
- }
- if (!found_processes)
- pr_notice("hardwall: no associated processes!\n");
-
- done:
- spin_unlock(&hwt->lock);
-
- /*
- * We have to disable firewall interrupts now, or else when we
- * return from this handler, we will simply re-interrupt back to
- * it. However, we can't clear the protection bits, since we
- * haven't yet drained the network, and that would allow packets
- * to cross out of the hardwall region.
- */
- disable_firewall_interrupts(hwt);
-
- irq_exit();
- set_irq_regs(old_regs);
-}
-
-/* Allow access from user space to the user network. */
-void grant_hardwall_mpls(struct hardwall_type *hwt)
-{
-#ifndef __tilepro__
- if (!hwt->is_xdn) {
- __insn_mtspr(SPR_MPL_IPI_0_SET_0, 1);
- return;
- }
-#endif
- mtspr_MPL_XDN(hwt, ACCESS_SET_0, 1);
- mtspr_MPL_XDN(hwt, AVAIL_SET_0, 1);
- mtspr_MPL_XDN(hwt, COMPLETE_SET_0, 1);
- mtspr_MPL_XDN(hwt, TIMER_SET_0, 1);
-#if !CHIP_HAS_REV1_XDN()
- mtspr_MPL_XDN(hwt, REFILL_SET_0, 1);
- mtspr_MPL_XDN(hwt, CA_SET_0, 1);
-#endif
-}
-
-/* Deny access from user space to the user network. */
-void restrict_hardwall_mpls(struct hardwall_type *hwt)
-{
-#ifndef __tilepro__
- if (!hwt->is_xdn) {
- __insn_mtspr(SPR_MPL_IPI_0_SET_1, 1);
- return;
- }
-#endif
- mtspr_MPL_XDN(hwt, ACCESS_SET_1, 1);
- mtspr_MPL_XDN(hwt, AVAIL_SET_1, 1);
- mtspr_MPL_XDN(hwt, COMPLETE_SET_1, 1);
- mtspr_MPL_XDN(hwt, TIMER_SET_1, 1);
-#if !CHIP_HAS_REV1_XDN()
- mtspr_MPL_XDN(hwt, REFILL_SET_1, 1);
- mtspr_MPL_XDN(hwt, CA_SET_1, 1);
-#endif
-}
-
-/* Restrict or deny as necessary for the task we're switching to. */
-void hardwall_switch_tasks(struct task_struct *prev,
- struct task_struct *next)
-{
- int i;
- for (i = 0; i < HARDWALL_TYPES; ++i) {
- if (prev->thread.hardwall[i].info != NULL) {
- if (next->thread.hardwall[i].info == NULL)
- restrict_hardwall_mpls(&hardwall_types[i]);
- } else if (next->thread.hardwall[i].info != NULL) {
- grant_hardwall_mpls(&hardwall_types[i]);
- }
- }
-}
-
-/* Does this task have the right to IPI the given cpu? */
-int hardwall_ipi_valid(int cpu)
-{
-#ifdef __tilegx__
- struct hardwall_info *info =
- current->thread.hardwall[HARDWALL_IPI].info;
- return info && cpumask_test_cpu(cpu, &info->cpumask);
-#else
- return 0;
-#endif
-}
-
-/*
- * Code to create, activate, deactivate, and destroy hardwall resources.
- */
-
-/* Create a hardwall for the given resource */
-static struct hardwall_info *hardwall_create(struct hardwall_type *hwt,
- size_t size,
- const unsigned char __user *bits)
-{
- struct hardwall_info *iter, *info;
- struct cpumask mask;
- unsigned long flags;
- int rc;
-
- /* Reject crazy sizes out of hand, a la sys_mbind(). */
- if (size > PAGE_SIZE)
- return ERR_PTR(-EINVAL);
-
- /* Copy whatever fits into a cpumask. */
- if (copy_from_user(&mask, bits, min(sizeof(struct cpumask), size)))
- return ERR_PTR(-EFAULT);
-
- /*
- * If the size was short, clear the rest of the mask;
- * otherwise validate that the rest of the user mask was zero
- * (we don't try hard to be efficient when validating huge masks).
- */
- if (size < sizeof(struct cpumask)) {
- memset((char *)&mask + size, 0, sizeof(struct cpumask) - size);
- } else if (size > sizeof(struct cpumask)) {
- size_t i;
- for (i = sizeof(struct cpumask); i < size; ++i) {
- char c;
- if (get_user(c, &bits[i]))
- return ERR_PTR(-EFAULT);
- if (c)
- return ERR_PTR(-EINVAL);
- }
- }
-
- /* Allocate a new hardwall_info optimistically. */
- info = kmalloc(sizeof(struct hardwall_info),
- GFP_KERNEL | __GFP_ZERO);
- if (info == NULL)
- return ERR_PTR(-ENOMEM);
- INIT_LIST_HEAD(&info->task_head);
- info->type = hwt;
-
- /* Compute the rectangle size and validate that it's plausible. */
- cpumask_copy(&info->cpumask, &mask);
- info->id = find_first_bit(cpumask_bits(&mask), nr_cpumask_bits);
- if (hwt->is_xdn) {
- rc = check_rectangle(info, &mask);
- if (rc != 0) {
- kfree(info);
- return ERR_PTR(rc);
- }
- }
-
- /*
- * Eliminate cpus that are not part of this Linux client.
- * Note that this allows for configurations that we might not want to
- * support, such as one client on every even cpu, another client on
- * every odd cpu.
- */
- cpumask_and(&info->cpumask, &info->cpumask, cpu_online_mask);
-
- /* Confirm it doesn't overlap and add it to the list. */
- spin_lock_irqsave(&hwt->lock, flags);
- list_for_each_entry(iter, &hwt->list, list) {
- if (cpumask_intersects(&iter->cpumask, &info->cpumask)) {
- spin_unlock_irqrestore(&hwt->lock, flags);
- kfree(info);
- return ERR_PTR(-EBUSY);
- }
- }
- list_add_tail(&info->list, &hwt->list);
- spin_unlock_irqrestore(&hwt->lock, flags);
-
- /* Set up appropriate hardwalling on all affected cpus. */
- if (hwt->is_xdn)
- hardwall_protect_rectangle(info);
-
- /* Create a /proc/tile/hardwall entry. */
- hardwall_add_proc(info);
-
- return info;
-}
-
-/* Activate a given hardwall on this cpu for this process. */
-static int hardwall_activate(struct hardwall_info *info)
-{
- int cpu;
- unsigned long flags;
- struct task_struct *p = current;
- struct thread_struct *ts = &p->thread;
- struct hardwall_type *hwt;
-
- /* Require a hardwall. */
- if (info == NULL)
- return -ENODATA;
-
- /* Not allowed to activate a hardwall that is being torn down. */
- if (info->teardown_in_progress)
- return -EINVAL;
-
- /*
- * Get our affinity; if we're not bound to this tile uniquely,
- * we can't access the network registers.
- */
- if (cpumask_weight(&p->cpus_allowed) != 1)
- return -EPERM;
-
- /* Make sure we are bound to a cpu assigned to this resource. */
- cpu = smp_processor_id();
- BUG_ON(cpumask_first(&p->cpus_allowed) != cpu);
- if (!cpumask_test_cpu(cpu, &info->cpumask))
- return -EINVAL;
-
- /* If we are already bound to this hardwall, it's a no-op. */
- hwt = info->type;
- if (ts->hardwall[hwt->index].info) {
- BUG_ON(ts->hardwall[hwt->index].info != info);
- return 0;
- }
-
- /* Success! This process gets to use the resource on this cpu. */
- ts->hardwall[hwt->index].info = info;
- spin_lock_irqsave(&hwt->lock, flags);
- list_add(&ts->hardwall[hwt->index].list, &info->task_head);
- spin_unlock_irqrestore(&hwt->lock, flags);
- grant_hardwall_mpls(hwt);
- printk(KERN_DEBUG "Pid %d (%s) activated for %s hardwall: cpu %d\n",
- p->pid, p->comm, hwt->name, cpu);
- return 0;
-}
-
-/*
- * Deactivate a task's hardwall. Must hold lock for hardwall_type.
- * This method may be called from exit_thread(), so we don't want to
- * rely on too many fields of struct task_struct still being valid.
- * We assume the cpus_allowed, pid, and comm fields are still valid.
- */
-static void _hardwall_deactivate(struct hardwall_type *hwt,
- struct task_struct *task)
-{
- struct thread_struct *ts = &task->thread;
-
- if (cpumask_weight(&task->cpus_allowed) != 1) {
- pr_err("pid %d (%s) releasing %s hardwall with an affinity mask containing %d cpus!\n",
- task->pid, task->comm, hwt->name,
- cpumask_weight(&task->cpus_allowed));
- BUG();
- }
-
- BUG_ON(ts->hardwall[hwt->index].info == NULL);
- ts->hardwall[hwt->index].info = NULL;
- list_del(&ts->hardwall[hwt->index].list);
- if (task == current)
- restrict_hardwall_mpls(hwt);
-}
-
-/* Deactivate a task's hardwall. */
-static int hardwall_deactivate(struct hardwall_type *hwt,
- struct task_struct *task)
-{
- unsigned long flags;
- int activated;
-
- spin_lock_irqsave(&hwt->lock, flags);
- activated = (task->thread.hardwall[hwt->index].info != NULL);
- if (activated)
- _hardwall_deactivate(hwt, task);
- spin_unlock_irqrestore(&hwt->lock, flags);
-
- if (!activated)
- return -EINVAL;
-
- printk(KERN_DEBUG "Pid %d (%s) deactivated for %s hardwall: cpu %d\n",
- task->pid, task->comm, hwt->name, raw_smp_processor_id());
- return 0;
-}
-
-void hardwall_deactivate_all(struct task_struct *task)
-{
- int i;
- for (i = 0; i < HARDWALL_TYPES; ++i)
- if (task->thread.hardwall[i].info)
- hardwall_deactivate(&hardwall_types[i], task);
-}
-
-/* Stop the switch before draining the network. */
-static void stop_xdn_switch(void *arg)
-{
-#if !CHIP_HAS_REV1_XDN()
- /* Freeze the switch and the demux. */
- __insn_mtspr(SPR_UDN_SP_FREEZE,
- SPR_UDN_SP_FREEZE__SP_FRZ_MASK |
- SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK |
- SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK);
-#else
- /*
- * Drop all packets bound for the core or off the edge.
- * We rely on the normal hardwall protection setup code
- * to have set the low four bits to trigger firewall interrupts,
- * and shift those bits up to trigger "drop on send" semantics,
- * plus adding "drop on send to core" for all switches.
- * In practice it seems the switches latch the DIRECTION_PROTECT
- * SPR so they won't start dropping if they're already
- * delivering the last message to the core, but it doesn't
- * hurt to enable it here.
- */
- struct hardwall_type *hwt = arg;
- unsigned long protect = mfspr_XDN(hwt, DIRECTION_PROTECT);
- mtspr_XDN(hwt, DIRECTION_PROTECT, (protect | C_PROTECT) << 5);
-#endif
-}
-
-static void empty_xdn_demuxes(struct hardwall_type *hwt)
-{
-#ifndef __tilepro__
- if (hwt->is_idn) {
- while (__insn_mfspr(SPR_IDN_DATA_AVAIL) & (1 << 0))
- (void) __tile_idn0_receive();
- while (__insn_mfspr(SPR_IDN_DATA_AVAIL) & (1 << 1))
- (void) __tile_idn1_receive();
- return;
- }
-#endif
- while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 0))
- (void) __tile_udn0_receive();
- while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 1))
- (void) __tile_udn1_receive();
- while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 2))
- (void) __tile_udn2_receive();
- while (__insn_mfspr(SPR_UDN_DATA_AVAIL) & (1 << 3))
- (void) __tile_udn3_receive();
-}
-
-/* Drain all the state from a stopped switch. */
-static void drain_xdn_switch(void *arg)
-{
- struct hardwall_info *info = arg;
- struct hardwall_type *hwt = info->type;
-
-#if CHIP_HAS_REV1_XDN()
- /*
- * The switches have been configured to drop any messages
- * destined for cores (or off the edge of the rectangle).
- * But the current message may continue to be delivered,
- * so we wait until all the cores have finished any pending
- * messages before we stop draining.
- */
- int pending = mfspr_XDN(hwt, PENDING);
- while (pending--) {
- empty_xdn_demuxes(hwt);
- if (hwt->is_idn)
- __tile_idn_send(0);
- else
- __tile_udn_send(0);
- }
- atomic_dec(&info->xdn_pending_count);
- while (atomic_read(&info->xdn_pending_count))
- empty_xdn_demuxes(hwt);
-#else
- int i;
- int from_tile_words, ca_count;
-
- /* Empty out the 5 switch point fifos. */
- for (i = 0; i < 5; i++) {
- int words, j;
- __insn_mtspr(SPR_UDN_SP_FIFO_SEL, i);
- words = __insn_mfspr(SPR_UDN_SP_STATE) & 0xF;
- for (j = 0; j < words; j++)
- (void) __insn_mfspr(SPR_UDN_SP_FIFO_DATA);
- BUG_ON((__insn_mfspr(SPR_UDN_SP_STATE) & 0xF) != 0);
- }
-
- /* Dump out the 3 word fifo at top. */
- from_tile_words = (__insn_mfspr(SPR_UDN_DEMUX_STATUS) >> 10) & 0x3;
- for (i = 0; i < from_tile_words; i++)
- (void) __insn_mfspr(SPR_UDN_DEMUX_WRITE_FIFO);
-
- /* Empty out demuxes. */
- empty_xdn_demuxes(hwt);
-
- /* Empty out catch all. */
- ca_count = __insn_mfspr(SPR_UDN_DEMUX_CA_COUNT);
- for (i = 0; i < ca_count; i++)
- (void) __insn_mfspr(SPR_UDN_CA_DATA);
- BUG_ON(__insn_mfspr(SPR_UDN_DEMUX_CA_COUNT) != 0);
-
- /* Clear demux logic. */
- __insn_mtspr(SPR_UDN_DEMUX_CTL, 1);
-
- /*
- * Write switch state; experimentation indicates that 0xc3000
- * is an idle switch point.
- */
- for (i = 0; i < 5; i++) {
- __insn_mtspr(SPR_UDN_SP_FIFO_SEL, i);
- __insn_mtspr(SPR_UDN_SP_STATE, 0xc3000);
- }
-#endif
-}
-
-/* Reset random XDN state registers at boot up and during hardwall teardown. */
-static void reset_xdn_network_state(struct hardwall_type *hwt)
-{
- if (hwt->disabled)
- return;
-
- /* Clear out other random registers so we have a clean slate. */
- mtspr_XDN(hwt, DIRECTION_PROTECT, 0);
- mtspr_XDN(hwt, AVAIL_EN, 0);
- mtspr_XDN(hwt, DEADLOCK_TIMEOUT, 0);
-
-#if !CHIP_HAS_REV1_XDN()
- /* Reset UDN coordinates to their standard value */
- {
- unsigned int cpu = smp_processor_id();
- unsigned int x = cpu_x(cpu);
- unsigned int y = cpu_y(cpu);
- __insn_mtspr(SPR_UDN_TILE_COORD, (x << 18) | (y << 7));
- }
-
- /* Set demux tags to predefined values and enable them. */
- __insn_mtspr(SPR_UDN_TAG_VALID, 0xf);
- __insn_mtspr(SPR_UDN_TAG_0, (1 << 0));
- __insn_mtspr(SPR_UDN_TAG_1, (1 << 1));
- __insn_mtspr(SPR_UDN_TAG_2, (1 << 2));
- __insn_mtspr(SPR_UDN_TAG_3, (1 << 3));
-
- /* Set other rev0 random registers to a clean state. */
- __insn_mtspr(SPR_UDN_REFILL_EN, 0);
- __insn_mtspr(SPR_UDN_DEMUX_QUEUE_SEL, 0);
- __insn_mtspr(SPR_UDN_SP_FIFO_SEL, 0);
-
- /* Start the switch and demux. */
- __insn_mtspr(SPR_UDN_SP_FREEZE, 0);
-#endif
-}
-
-void reset_network_state(void)
-{
- reset_xdn_network_state(&hardwall_types[HARDWALL_UDN]);
-#ifndef __tilepro__
- reset_xdn_network_state(&hardwall_types[HARDWALL_IDN]);
-#endif
-}
-
-/* Restart an XDN switch after draining. */
-static void restart_xdn_switch(void *arg)
-{
- struct hardwall_type *hwt = arg;
-
-#if CHIP_HAS_REV1_XDN()
- /* One last drain step to avoid races with injection and draining. */
- empty_xdn_demuxes(hwt);
-#endif
-
- reset_xdn_network_state(hwt);
-
- /* Disable firewall interrupts. */
- disable_firewall_interrupts(hwt);
-}
-
-/* Last reference to a hardwall is gone, so clear the network. */
-static void hardwall_destroy(struct hardwall_info *info)
-{
- struct task_struct *task;
- struct hardwall_type *hwt;
- unsigned long flags;
-
- /* Make sure this file actually represents a hardwall. */
- if (info == NULL)
- return;
-
- /*
- * Deactivate any remaining tasks. It's possible to race with
- * some other thread that is exiting and hasn't yet called
- * deactivate (when freeing its thread_info), so we carefully
- * deactivate any remaining tasks before freeing the
- * hardwall_info object itself.
- */
- hwt = info->type;
- info->teardown_in_progress = 1;
- spin_lock_irqsave(&hwt->lock, flags);
- list_for_each_entry(task, &info->task_head,
- thread.hardwall[hwt->index].list)
- _hardwall_deactivate(hwt, task);
- spin_unlock_irqrestore(&hwt->lock, flags);
-
- if (hwt->is_xdn) {
- /* Configure the switches for draining the user network. */
- printk(KERN_DEBUG
- "Clearing %s hardwall rectangle %dx%d %d,%d\n",
- hwt->name, info->width, info->height,
- info->ulhc_x, info->ulhc_y);
- on_each_cpu_mask(&info->cpumask, stop_xdn_switch, hwt, 1);
-
- /* Drain the network. */
-#if CHIP_HAS_REV1_XDN()
- atomic_set(&info->xdn_pending_count,
- cpumask_weight(&info->cpumask));
- on_each_cpu_mask(&info->cpumask, drain_xdn_switch, info, 0);
-#else
- on_each_cpu_mask(&info->cpumask, drain_xdn_switch, info, 1);
-#endif
-
- /* Restart switch and disable firewall. */
- on_each_cpu_mask(&info->cpumask, restart_xdn_switch, hwt, 1);
- }
-
- /* Remove the /proc/tile/hardwall entry. */
- hardwall_remove_proc(info);
-
- /* Now free the hardwall from the list. */
- spin_lock_irqsave(&hwt->lock, flags);
- BUG_ON(!list_empty(&info->task_head));
- list_del(&info->list);
- spin_unlock_irqrestore(&hwt->lock, flags);
- kfree(info);
-}
-
-
-static int hardwall_proc_show(struct seq_file *sf, void *v)
-{
- struct hardwall_info *info = sf->private;
-
- seq_printf(sf, "%*pbl\n", cpumask_pr_args(&info->cpumask));
- return 0;
-}
-
-static int hardwall_proc_open(struct inode *inode,
- struct file *file)
-{
- return single_open(file, hardwall_proc_show, PDE_DATA(inode));
-}
-
-static const struct file_operations hardwall_proc_fops = {
- .open = hardwall_proc_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static void hardwall_add_proc(struct hardwall_info *info)
-{
- char buf[64];
- snprintf(buf, sizeof(buf), "%d", info->id);
- proc_create_data(buf, 0444, info->type->proc_dir,
- &hardwall_proc_fops, info);
-}
-
-static void hardwall_remove_proc(struct hardwall_info *info)
-{
- char buf[64];
- snprintf(buf, sizeof(buf), "%d", info->id);
- remove_proc_entry(buf, info->type->proc_dir);
-}
-
-int proc_pid_hardwall(struct seq_file *m, struct pid_namespace *ns,
- struct pid *pid, struct task_struct *task)
-{
- int i;
- int n = 0;
- for (i = 0; i < HARDWALL_TYPES; ++i) {
- struct hardwall_info *info = task->thread.hardwall[i].info;
- if (info)
- seq_printf(m, "%s: %d\n", info->type->name, info->id);
- }
- return n;
-}
-
-void proc_tile_hardwall_init(struct proc_dir_entry *root)
-{
- int i;
- for (i = 0; i < HARDWALL_TYPES; ++i) {
- struct hardwall_type *hwt = &hardwall_types[i];
- if (hwt->disabled)
- continue;
- if (hardwall_proc_dir == NULL)
- hardwall_proc_dir = proc_mkdir("hardwall", root);
- hwt->proc_dir = proc_mkdir(hwt->name, hardwall_proc_dir);
- }
-}
-
-
-/*
- * Character device support via ioctl/close.
- */
-
-static long hardwall_ioctl(struct file *file, unsigned int a, unsigned long b)
-{
- struct hardwall_info *info = file->private_data;
- int minor = iminor(file->f_mapping->host);
- struct hardwall_type* hwt;
-
- if (_IOC_TYPE(a) != HARDWALL_IOCTL_BASE)
- return -EINVAL;
-
- BUILD_BUG_ON(HARDWALL_TYPES != _HARDWALL_TYPES);
- BUILD_BUG_ON(HARDWALL_TYPES !=
- sizeof(hardwall_types)/sizeof(hardwall_types[0]));
-
- if (minor < 0 || minor >= HARDWALL_TYPES)
- return -EINVAL;
- hwt = &hardwall_types[minor];
- WARN_ON(info && hwt != info->type);
-
- switch (_IOC_NR(a)) {
- case _HARDWALL_CREATE:
- if (hwt->disabled)
- return -ENOSYS;
- if (info != NULL)
- return -EALREADY;
- info = hardwall_create(hwt, _IOC_SIZE(a),
- (const unsigned char __user *)b);
- if (IS_ERR(info))
- return PTR_ERR(info);
- file->private_data = info;
- return 0;
-
- case _HARDWALL_ACTIVATE:
- return hardwall_activate(info);
-
- case _HARDWALL_DEACTIVATE:
- if (current->thread.hardwall[hwt->index].info != info)
- return -EINVAL;
- return hardwall_deactivate(hwt, current);
-
- case _HARDWALL_GET_ID:
- return info ? info->id : -EINVAL;
-
- default:
- return -EINVAL;
- }
-}
-
-#ifdef CONFIG_COMPAT
-static long hardwall_compat_ioctl(struct file *file,
- unsigned int a, unsigned long b)
-{
- /* Sign-extend the argument so it can be used as a pointer. */
- return hardwall_ioctl(file, a, (unsigned long)compat_ptr(b));
-}
-#endif
-
-/* The user process closed the file; revoke access to user networks. */
-static int hardwall_flush(struct file *file, fl_owner_t owner)
-{
- struct hardwall_info *info = file->private_data;
- struct task_struct *task, *tmp;
- unsigned long flags;
-
- if (info) {
- /*
- * NOTE: if multiple threads are activated on this hardwall
- * file, the other threads will continue having access to the
- * user network until they are context-switched out and back
- * in again.
- *
- * NOTE: A NULL files pointer means the task is being torn
- * down, so in that case we also deactivate it.
- */
- struct hardwall_type *hwt = info->type;
- spin_lock_irqsave(&hwt->lock, flags);
- list_for_each_entry_safe(task, tmp, &info->task_head,
- thread.hardwall[hwt->index].list) {
- if (task->files == owner || task->files == NULL)
- _hardwall_deactivate(hwt, task);
- }
- spin_unlock_irqrestore(&hwt->lock, flags);
- }
-
- return 0;
-}
-
-/* This hardwall is gone, so destroy it. */
-static int hardwall_release(struct inode *inode, struct file *file)
-{
- hardwall_destroy(file->private_data);
- return 0;
-}
-
-static const struct file_operations dev_hardwall_fops = {
- .open = nonseekable_open,
- .unlocked_ioctl = hardwall_ioctl,
-#ifdef CONFIG_COMPAT
- .compat_ioctl = hardwall_compat_ioctl,
-#endif
- .flush = hardwall_flush,
- .release = hardwall_release,
-};
-
-static struct cdev hardwall_dev;
-
-static int __init dev_hardwall_init(void)
-{
- int rc;
- dev_t dev;
-
- rc = alloc_chrdev_region(&dev, 0, HARDWALL_TYPES, "hardwall");
- if (rc < 0)
- return rc;
- cdev_init(&hardwall_dev, &dev_hardwall_fops);
- rc = cdev_add(&hardwall_dev, dev, HARDWALL_TYPES);
- if (rc < 0)
- return rc;
-
- return 0;
-}
-late_initcall(dev_hardwall_init);
diff --git a/arch/tile/kernel/head_32.S b/arch/tile/kernel/head_32.S
deleted file mode 100644
index 8d5b40ff2922..000000000000
--- a/arch/tile/kernel/head_32.S
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE startup code.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/thread_info.h>
-#include <asm/processor.h>
-#include <asm/asm-offsets.h>
-#include <hv/hypervisor.h>
-#include <arch/chip.h>
-#include <arch/spr_def.h>
-
-/*
- * This module contains the entry code for kernel images. It performs the
- * minimal setup needed to call the generic C routines.
- */
-
- __HEAD
-ENTRY(_start)
- /* Notify the hypervisor of what version of the API we want */
- {
- movei r1, TILE_CHIP
- movei r2, TILE_CHIP_REV
- }
- {
- moveli r0, _HV_VERSION_OLD_HV_INIT
- jal _hv_init
- }
- /* Get a reasonable default ASID in r0 */
- {
- move r0, zero
- jal _hv_inquire_asid
- }
- /* Install the default page table */
- {
- moveli r6, lo16(swapper_pgprot - PAGE_OFFSET)
- move r4, r0 /* use starting ASID of range for this page table */
- }
- {
- moveli r0, lo16(swapper_pg_dir - PAGE_OFFSET)
- auli r6, r6, ha16(swapper_pgprot - PAGE_OFFSET)
- }
- {
- lw r2, r6
- addi r6, r6, 4
- }
- {
- lw r3, r6
- auli r0, r0, ha16(swapper_pg_dir - PAGE_OFFSET)
- }
- {
- finv r6
- move r1, zero /* high 32 bits of CPA is zero */
- }
- {
- moveli lr, lo16(1f)
- moveli r5, CTX_PAGE_FLAG
- }
- {
- auli lr, lr, ha16(1f)
- j _hv_install_context
- }
-1:
-
- /* Get our processor number and save it away in SAVE_K_0. */
- jal _hv_inquire_topology
- mulll_uu r4, r1, r2 /* r1 == y, r2 == width */
- add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */
-
-#ifdef CONFIG_SMP
- /*
- * Load up our per-cpu offset. When the first (master) tile
- * boots, this value is still zero, so we will load boot_pc
- * with start_kernel, and boot_sp at the top of init_stack.
- * The master tile initializes the per-cpu offset array, so that
- * when subsequent (secondary) tiles boot, they will instead load
- * from their per-cpu versions of boot_sp and boot_pc.
- */
- moveli r5, lo16(__per_cpu_offset)
- auli r5, r5, ha16(__per_cpu_offset)
- s2a r5, r4, r5
- lw r5, r5
- bnz r5, 1f
-
- /*
- * Save the width and height to the smp_topology variable
- * for later use.
- */
- moveli r0, lo16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
- auli r0, r0, ha16(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
- {
- sw r0, r2
- addi r0, r0, (HV_TOPOLOGY_HEIGHT_OFFSET - HV_TOPOLOGY_WIDTH_OFFSET)
- }
- sw r0, r3
-1:
-#else
- move r5, zero
-#endif
-
- /* Load and go with the correct pc and sp. */
- {
- addli r1, r5, lo16(boot_sp)
- addli r0, r5, lo16(boot_pc)
- }
- {
- auli r1, r1, ha16(boot_sp)
- auli r0, r0, ha16(boot_pc)
- }
- lw r0, r0
- lw sp, r1
- or r4, sp, r4
- mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
- {
- move lr, zero /* stop backtraces in the called function */
- jr r0
- }
- ENDPROC(_start)
-
-__PAGE_ALIGNED_BSS
- .align PAGE_SIZE
-ENTRY(empty_zero_page)
- .fill PAGE_SIZE,1,0
- END(empty_zero_page)
-
- .macro PTE va, cpa, bits1, no_org=0
- .ifeq \no_org
- .org swapper_pg_dir + PGD_INDEX(\va) * HV_PTE_SIZE
- .endif
- .word HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED | \
- (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
- .word (\bits1) | (HV_CPA_TO_PTFN(\cpa) << (HV_PTE_INDEX_PTFN - 32))
- .endm
-
-__PAGE_ALIGNED_DATA
- .align PAGE_SIZE
-ENTRY(swapper_pg_dir)
- /*
- * All data pages from PAGE_OFFSET to MEM_USER_INTRPT are mapped as
- * VA = PA + PAGE_OFFSET. We remap things with more precise access
- * permissions and more respect for size of RAM later.
- */
- .set addr, 0
- .rept (MEM_USER_INTRPT - PAGE_OFFSET) >> PGDIR_SHIFT
- PTE addr + PAGE_OFFSET, addr, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
- (1 << (HV_PTE_INDEX_WRITABLE - 32))
- .set addr, addr + PGDIR_SIZE
- .endr
-
- /* The true text VAs are mapped as VA = PA + MEM_SV_START */
- PTE MEM_SV_START, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
- (1 << (HV_PTE_INDEX_EXECUTABLE - 32))
- .org swapper_pg_dir + PGDIR_SIZE
- END(swapper_pg_dir)
-
- /*
- * Isolate swapper_pgprot to its own cache line, since each cpu
- * starting up will read it using VA-is-PA and local homing.
- * This would otherwise likely conflict with other data on the cache
- * line, once we have set its permanent home in the page tables.
- */
- __INITDATA
- .align CHIP_L2_LINE_SIZE()
-ENTRY(swapper_pgprot)
- PTE 0, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
- (1 << (HV_PTE_INDEX_WRITABLE - 32)), 1
- .align CHIP_L2_LINE_SIZE()
- END(swapper_pgprot)
diff --git a/arch/tile/kernel/head_64.S b/arch/tile/kernel/head_64.S
deleted file mode 100644
index bd0e12f283f3..000000000000
--- a/arch/tile/kernel/head_64.S
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE startup code.
- */
-
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/thread_info.h>
-#include <asm/processor.h>
-#include <asm/asm-offsets.h>
-#include <hv/hypervisor.h>
-#include <arch/chip.h>
-#include <arch/spr_def.h>
-
-/* Extract two 32-bit bit values that were read into one register. */
-#ifdef __BIG_ENDIAN__
-#define GET_FIRST_INT(rd, rs) shrsi rd, rs, 32
-#define GET_SECOND_INT(rd, rs) addxi rd, rs, 0
-#else
-#define GET_FIRST_INT(rd, rs) addxi rd, rs, 0
-#define GET_SECOND_INT(rd, rs) shrsi rd, rs, 32
-#endif
-
-/*
- * This module contains the entry code for kernel images. It performs the
- * minimal setup needed to call the generic C routines.
- */
-
- __HEAD
-ENTRY(_start)
- /* Notify the hypervisor of what version of the API we want */
- {
-#if KERNEL_PL == 1 && _HV_VERSION == 13
- /* Support older hypervisors by asking for API version 12. */
- movei r0, _HV_VERSION_OLD_HV_INIT
-#else
- movei r0, _HV_VERSION
-#endif
- movei r1, TILE_CHIP
- }
- {
- movei r2, TILE_CHIP_REV
- movei r3, KERNEL_PL
- }
- jal _hv_init
- /* Get a reasonable default ASID in r0 */
- {
- move r0, zero
- jal _hv_inquire_asid
- }
-
- /*
- * Install the default page table. The relocation required to
- * statically define the table is a bit too complex, so we have
- * to plug in the pointer from the L0 to the L1 table by hand.
- * We only do this on the first cpu to boot, though, since the
- * other CPUs should see a properly-constructed page table.
- */
- {
- GET_FIRST_INT(r2, r0) /* ASID for hv_install_context */
- moveli r4, hw1_last(swapper_pgprot - PAGE_OFFSET)
- }
- {
- shl16insli r4, r4, hw0(swapper_pgprot - PAGE_OFFSET)
- }
- {
- ld r1, r4 /* access_pte for hv_install_context */
- }
- {
- moveli r0, hw1_last(.Lsv_data_pmd - PAGE_OFFSET)
- moveli r6, hw1_last(temp_data_pmd - PAGE_OFFSET)
- }
- {
- /* After initializing swapper_pgprot, HV_PTE_GLOBAL is set. */
- bfextu r7, r1, HV_PTE_INDEX_GLOBAL, HV_PTE_INDEX_GLOBAL
- finv r4
- }
- bnez r7, .Lno_write
- {
- shl16insli r0, r0, hw0(.Lsv_data_pmd - PAGE_OFFSET)
- shl16insli r6, r6, hw0(temp_data_pmd - PAGE_OFFSET)
- }
- {
- /* Cut off the low bits of the PT address. */
- shrui r6, r6, HV_LOG2_PAGE_TABLE_ALIGN
- /* Start with our access pte. */
- move r5, r1
- }
- {
- /* Stuff the address into the page table pointer slot of the PTE. */
- bfins r5, r6, HV_PTE_INDEX_PTFN, \
- HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
- }
- {
- /* Store the L0 data PTE. */
- st r0, r5
- addli r6, r6, (temp_code_pmd - temp_data_pmd) >> \
- HV_LOG2_PAGE_TABLE_ALIGN
- }
- {
- addli r0, r0, .Lsv_code_pmd - .Lsv_data_pmd
- bfins r5, r6, HV_PTE_INDEX_PTFN, \
- HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
- }
- /* Store the L0 code PTE. */
- st r0, r5
-
-.Lno_write:
- moveli lr, hw2_last(1f)
- {
- shl16insli lr, lr, hw1(1f)
- moveli r0, hw1_last(swapper_pg_dir - PAGE_OFFSET)
- }
- {
- shl16insli lr, lr, hw0(1f)
- shl16insli r0, r0, hw0(swapper_pg_dir - PAGE_OFFSET)
- }
- {
- moveli r3, CTX_PAGE_FLAG
- j _hv_install_context
- }
-1:
-
- /* Install the interrupt base. */
- moveli r0, hw2_last(intrpt_start)
- shl16insli r0, r0, hw1(intrpt_start)
- shl16insli r0, r0, hw0(intrpt_start)
- mtspr SPR_INTERRUPT_VECTOR_BASE_K, r0
-
- /* Get our processor number and save it away in SAVE_K_0. */
- jal _hv_inquire_topology
- {
- GET_FIRST_INT(r5, r1) /* r5 = width */
- GET_SECOND_INT(r4, r0) /* r4 = y */
- }
- {
- GET_FIRST_INT(r6, r0) /* r6 = x */
- mul_lu_lu r4, r4, r5
- }
- {
- add r4, r4, r6 /* r4 == cpu == y*width + x */
- }
-
-#ifdef CONFIG_SMP
- /*
- * Load up our per-cpu offset. When the first (master) tile
- * boots, this value is still zero, so we will load boot_pc
- * with start_kernel, and boot_sp with at the top of init_stack.
- * The master tile initializes the per-cpu offset array, so that
- * when subsequent (secondary) tiles boot, they will instead load
- * from their per-cpu versions of boot_sp and boot_pc.
- */
- moveli r5, hw2_last(__per_cpu_offset)
- shl16insli r5, r5, hw1(__per_cpu_offset)
- shl16insli r5, r5, hw0(__per_cpu_offset)
- shl3add r5, r4, r5
- ld r5, r5
- bnez r5, 1f
-
- /*
- * Save the width and height to the smp_topology variable
- * for later use.
- */
- moveli r0, hw2_last(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
- shl16insli r0, r0, hw1(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
- shl16insli r0, r0, hw0(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
- st r0, r1
-1:
-#else
- move r5, zero
-#endif
-
- /* Load and go with the correct pc and sp. */
- {
- moveli r1, hw2_last(boot_sp)
- moveli r0, hw2_last(boot_pc)
- }
- {
- shl16insli r1, r1, hw1(boot_sp)
- shl16insli r0, r0, hw1(boot_pc)
- }
- {
- shl16insli r1, r1, hw0(boot_sp)
- shl16insli r0, r0, hw0(boot_pc)
- }
- {
- add r1, r1, r5
- add r0, r0, r5
- }
- ld r0, r0
- ld sp, r1
- shli r4, r4, CPU_SHIFT
- bfins r4, sp, 0, CPU_SHIFT-1
- mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
- {
- move lr, zero /* stop backtraces in the called function */
- jr r0
- }
- ENDPROC(_start)
-
-__PAGE_ALIGNED_BSS
- .align PAGE_SIZE
-ENTRY(empty_zero_page)
- .fill PAGE_SIZE,1,0
- END(empty_zero_page)
-
- .macro PTE cpa, bits1
- .quad HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED |\
- HV_PTE_GLOBAL | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE) |\
- (\bits1) | (HV_CPA_TO_PTFN(\cpa) << HV_PTE_INDEX_PTFN)
- .endm
-
-__PAGE_ALIGNED_DATA
- .align PAGE_SIZE
-ENTRY(swapper_pg_dir)
- .org swapper_pg_dir + PGD_INDEX(PAGE_OFFSET) * HV_PTE_SIZE
-.Lsv_data_pmd:
- .quad 0 /* PTE temp_data_pmd - PAGE_OFFSET, 0 */
- .org swapper_pg_dir + PGD_INDEX(MEM_SV_START) * HV_PTE_SIZE
-.Lsv_code_pmd:
- .quad 0 /* PTE temp_code_pmd - PAGE_OFFSET, 0 */
- .org swapper_pg_dir + SIZEOF_PGD
- END(swapper_pg_dir)
-
- .align HV_PAGE_TABLE_ALIGN
-ENTRY(temp_data_pmd)
- /*
- * We fill the PAGE_OFFSET pmd with huge pages with
- * VA = PA + PAGE_OFFSET. We remap things with more precise access
- * permissions later.
- */
- .set addr, 0
- .rept PTRS_PER_PMD
- PTE addr, HV_PTE_READABLE | HV_PTE_WRITABLE
- .set addr, addr + HPAGE_SIZE
- .endr
- .org temp_data_pmd + SIZEOF_PMD
- END(temp_data_pmd)
-
- .align HV_PAGE_TABLE_ALIGN
-ENTRY(temp_code_pmd)
- /*
- * We fill the MEM_SV_START pmd with huge pages with
- * VA = PA + PAGE_OFFSET. We remap things with more precise access
- * permissions later.
- */
- .set addr, 0
- .rept PTRS_PER_PMD
- PTE addr, HV_PTE_READABLE | HV_PTE_EXECUTABLE
- .set addr, addr + HPAGE_SIZE
- .endr
- .org temp_code_pmd + SIZEOF_PMD
- END(temp_code_pmd)
-
- /*
- * Isolate swapper_pgprot to its own cache line, since each cpu
- * starting up will read it using VA-is-PA and local homing.
- * This would otherwise likely conflict with other data on the cache
- * line, once we have set its permanent home in the page tables.
- */
- __INITDATA
- .align CHIP_L2_LINE_SIZE()
-ENTRY(swapper_pgprot)
- .quad HV_PTE_PRESENT | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
- .align CHIP_L2_LINE_SIZE()
- END(swapper_pgprot)
diff --git a/arch/tile/kernel/hvglue.S b/arch/tile/kernel/hvglue.S
deleted file mode 100644
index 70c661448638..000000000000
--- a/arch/tile/kernel/hvglue.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Hypervisor call vector addresses; see <hv/hypervisor.h> */
-.macro gensym sym, val, size
-.org \val
-.global _\sym
-.type _\sym,function
-_\sym:
-.size _\sym,\size
-#ifndef CONFIG_TILE_HVGLUE_TRACE
-.globl \sym
-.set \sym,_\sym
-#endif
-.endm
-
-.section .hvglue,"x",@nobits
-.align 8
-gensym hv_init, 0x20, 32
-gensym hv_install_context, 0x40, 32
-gensym hv_sysconf, 0x60, 32
-gensym hv_get_rtc, 0x80, 32
-gensym hv_set_rtc, 0xa0, 32
-gensym hv_flush_asid, 0xc0, 32
-gensym hv_flush_page, 0xe0, 32
-gensym hv_flush_pages, 0x100, 32
-gensym hv_restart, 0x120, 32
-gensym hv_halt, 0x140, 32
-gensym hv_power_off, 0x160, 32
-gensym hv_inquire_physical, 0x180, 32
-gensym hv_inquire_memory_controller, 0x1a0, 32
-gensym hv_inquire_virtual, 0x1c0, 32
-gensym hv_inquire_asid, 0x1e0, 32
-gensym hv_nanosleep, 0x200, 32
-gensym hv_console_read_if_ready, 0x220, 32
-gensym hv_console_write, 0x240, 32
-gensym hv_downcall_dispatch, 0x260, 32
-gensym hv_inquire_topology, 0x280, 32
-gensym hv_fs_findfile, 0x2a0, 32
-gensym hv_fs_fstat, 0x2c0, 32
-gensym hv_fs_pread, 0x2e0, 32
-gensym hv_physaddr_read64, 0x300, 32
-gensym hv_physaddr_write64, 0x320, 32
-gensym hv_get_command_line, 0x340, 32
-gensym hv_set_caching, 0x360, 32
-gensym hv_bzero_page, 0x380, 32
-gensym hv_register_message_state, 0x3a0, 32
-gensym hv_send_message, 0x3c0, 32
-gensym hv_receive_message, 0x3e0, 32
-gensym hv_inquire_context, 0x400, 32
-gensym hv_start_all_tiles, 0x420, 32
-gensym hv_dev_open, 0x440, 32
-gensym hv_dev_close, 0x460, 32
-gensym hv_dev_pread, 0x480, 32
-gensym hv_dev_pwrite, 0x4a0, 32
-gensym hv_dev_poll, 0x4c0, 32
-gensym hv_dev_poll_cancel, 0x4e0, 32
-gensym hv_dev_preada, 0x500, 32
-gensym hv_dev_pwritea, 0x520, 32
-gensym hv_flush_remote, 0x540, 32
-gensym hv_console_putc, 0x560, 32
-gensym hv_inquire_tiles, 0x580, 32
-gensym hv_confstr, 0x5a0, 32
-gensym hv_reexec, 0x5c0, 32
-gensym hv_set_command_line, 0x5e0, 32
-gensym hv_clear_intr, 0x600, 32
-gensym hv_enable_intr, 0x620, 32
-gensym hv_disable_intr, 0x640, 32
-gensym hv_raise_intr, 0x660, 32
-gensym hv_trigger_ipi, 0x680, 32
-gensym hv_store_mapping, 0x6a0, 32
-gensym hv_inquire_realpa, 0x6c0, 32
-gensym hv_flush_all, 0x6e0, 32
-gensym hv_get_ipi_pte, 0x700, 32
-gensym hv_set_pte_super_shift, 0x720, 32
-gensym hv_console_set_ipi, 0x7e0, 32
-gensym hv_send_nmi, 0x820, 32
-gensym hv_glue_internals, 0x820, 30688
diff --git a/arch/tile/kernel/hvglue_trace.c b/arch/tile/kernel/hvglue_trace.c
deleted file mode 100644
index add0d71395c6..000000000000
--- a/arch/tile/kernel/hvglue_trace.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/*
- * Pull in the hypervisor header so we declare all the ABI functions
- * with the underscore versions, then undef the names so that we can
- * provide our own wrapper versions.
- */
-#define hv_init _hv_init
-#define hv_install_context _hv_install_context
-#define hv_sysconf _hv_sysconf
-#define hv_get_rtc _hv_get_rtc
-#define hv_set_rtc _hv_set_rtc
-#define hv_flush_asid _hv_flush_asid
-#define hv_flush_page _hv_flush_page
-#define hv_flush_pages _hv_flush_pages
-#define hv_restart _hv_restart
-#define hv_halt _hv_halt
-#define hv_power_off _hv_power_off
-#define hv_inquire_physical _hv_inquire_physical
-#define hv_inquire_memory_controller _hv_inquire_memory_controller
-#define hv_inquire_virtual _hv_inquire_virtual
-#define hv_inquire_asid _hv_inquire_asid
-#define hv_nanosleep _hv_nanosleep
-#define hv_console_read_if_ready _hv_console_read_if_ready
-#define hv_console_write _hv_console_write
-#define hv_downcall_dispatch _hv_downcall_dispatch
-#define hv_inquire_topology _hv_inquire_topology
-#define hv_fs_findfile _hv_fs_findfile
-#define hv_fs_fstat _hv_fs_fstat
-#define hv_fs_pread _hv_fs_pread
-#define hv_physaddr_read64 _hv_physaddr_read64
-#define hv_physaddr_write64 _hv_physaddr_write64
-#define hv_get_command_line _hv_get_command_line
-#define hv_set_caching _hv_set_caching
-#define hv_bzero_page _hv_bzero_page
-#define hv_register_message_state _hv_register_message_state
-#define hv_send_message _hv_send_message
-#define hv_receive_message _hv_receive_message
-#define hv_inquire_context _hv_inquire_context
-#define hv_start_all_tiles _hv_start_all_tiles
-#define hv_dev_open _hv_dev_open
-#define hv_dev_close _hv_dev_close
-#define hv_dev_pread _hv_dev_pread
-#define hv_dev_pwrite _hv_dev_pwrite
-#define hv_dev_poll _hv_dev_poll
-#define hv_dev_poll_cancel _hv_dev_poll_cancel
-#define hv_dev_preada _hv_dev_preada
-#define hv_dev_pwritea _hv_dev_pwritea
-#define hv_flush_remote _hv_flush_remote
-#define hv_console_putc _hv_console_putc
-#define hv_inquire_tiles _hv_inquire_tiles
-#define hv_confstr _hv_confstr
-#define hv_reexec _hv_reexec
-#define hv_set_command_line _hv_set_command_line
-#define hv_clear_intr _hv_clear_intr
-#define hv_enable_intr _hv_enable_intr
-#define hv_disable_intr _hv_disable_intr
-#define hv_raise_intr _hv_raise_intr
-#define hv_trigger_ipi _hv_trigger_ipi
-#define hv_store_mapping _hv_store_mapping
-#define hv_inquire_realpa _hv_inquire_realpa
-#define hv_flush_all _hv_flush_all
-#define hv_get_ipi_pte _hv_get_ipi_pte
-#define hv_set_pte_super_shift _hv_set_pte_super_shift
-#define hv_console_set_ipi _hv_console_set_ipi
-#define hv_send_nmi _hv_send_nmi
-#include <hv/hypervisor.h>
-#undef hv_init
-#undef hv_install_context
-#undef hv_sysconf
-#undef hv_get_rtc
-#undef hv_set_rtc
-#undef hv_flush_asid
-#undef hv_flush_page
-#undef hv_flush_pages
-#undef hv_restart
-#undef hv_halt
-#undef hv_power_off
-#undef hv_inquire_physical
-#undef hv_inquire_memory_controller
-#undef hv_inquire_virtual
-#undef hv_inquire_asid
-#undef hv_nanosleep
-#undef hv_console_read_if_ready
-#undef hv_console_write
-#undef hv_downcall_dispatch
-#undef hv_inquire_topology
-#undef hv_fs_findfile
-#undef hv_fs_fstat
-#undef hv_fs_pread
-#undef hv_physaddr_read64
-#undef hv_physaddr_write64
-#undef hv_get_command_line
-#undef hv_set_caching
-#undef hv_bzero_page
-#undef hv_register_message_state
-#undef hv_send_message
-#undef hv_receive_message
-#undef hv_inquire_context
-#undef hv_start_all_tiles
-#undef hv_dev_open
-#undef hv_dev_close
-#undef hv_dev_pread
-#undef hv_dev_pwrite
-#undef hv_dev_poll
-#undef hv_dev_poll_cancel
-#undef hv_dev_preada
-#undef hv_dev_pwritea
-#undef hv_flush_remote
-#undef hv_console_putc
-#undef hv_inquire_tiles
-#undef hv_confstr
-#undef hv_reexec
-#undef hv_set_command_line
-#undef hv_clear_intr
-#undef hv_enable_intr
-#undef hv_disable_intr
-#undef hv_raise_intr
-#undef hv_trigger_ipi
-#undef hv_store_mapping
-#undef hv_inquire_realpa
-#undef hv_flush_all
-#undef hv_get_ipi_pte
-#undef hv_set_pte_super_shift
-#undef hv_console_set_ipi
-#undef hv_send_nmi
-
-/*
- * Provide macros based on <linux/syscalls.h> to provide a wrapper
- * function that invokes the same function with an underscore prefix.
- * We can't use the existing __SC_xxx macros because we need to
- * support up to nine arguments rather than up to six, and also this
- * way the file stands alone from possible changes in the
- * implementation of <linux/syscalls.h>.
- */
-#define HV_WRAP0(type, name) \
- type name(void); \
- type name(void) \
- { \
- return _##name(); \
- }
-#define __HV_DECL1(t1, a1) t1 a1
-#define __HV_DECL2(t2, a2, ...) t2 a2, __HV_DECL1(__VA_ARGS__)
-#define __HV_DECL3(t3, a3, ...) t3 a3, __HV_DECL2(__VA_ARGS__)
-#define __HV_DECL4(t4, a4, ...) t4 a4, __HV_DECL3(__VA_ARGS__)
-#define __HV_DECL5(t5, a5, ...) t5 a5, __HV_DECL4(__VA_ARGS__)
-#define __HV_DECL6(t6, a6, ...) t6 a6, __HV_DECL5(__VA_ARGS__)
-#define __HV_DECL7(t7, a7, ...) t7 a7, __HV_DECL6(__VA_ARGS__)
-#define __HV_DECL8(t8, a8, ...) t8 a8, __HV_DECL7(__VA_ARGS__)
-#define __HV_DECL9(t9, a9, ...) t9 a9, __HV_DECL8(__VA_ARGS__)
-#define __HV_PASS1(t1, a1) a1
-#define __HV_PASS2(t2, a2, ...) a2, __HV_PASS1(__VA_ARGS__)
-#define __HV_PASS3(t3, a3, ...) a3, __HV_PASS2(__VA_ARGS__)
-#define __HV_PASS4(t4, a4, ...) a4, __HV_PASS3(__VA_ARGS__)
-#define __HV_PASS5(t5, a5, ...) a5, __HV_PASS4(__VA_ARGS__)
-#define __HV_PASS6(t6, a6, ...) a6, __HV_PASS5(__VA_ARGS__)
-#define __HV_PASS7(t7, a7, ...) a7, __HV_PASS6(__VA_ARGS__)
-#define __HV_PASS8(t8, a8, ...) a8, __HV_PASS7(__VA_ARGS__)
-#define __HV_PASS9(t9, a9, ...) a9, __HV_PASS8(__VA_ARGS__)
-#define HV_WRAPx(x, type, name, ...) \
- type name(__HV_DECL##x(__VA_ARGS__)); \
- type name(__HV_DECL##x(__VA_ARGS__)) \
- { \
- return _##name(__HV_PASS##x(__VA_ARGS__)); \
- }
-#define HV_WRAP1(type, name, ...) HV_WRAPx(1, type, name, __VA_ARGS__)
-#define HV_WRAP2(type, name, ...) HV_WRAPx(2, type, name, __VA_ARGS__)
-#define HV_WRAP3(type, name, ...) HV_WRAPx(3, type, name, __VA_ARGS__)
-#define HV_WRAP4(type, name, ...) HV_WRAPx(4, type, name, __VA_ARGS__)
-#define HV_WRAP5(type, name, ...) HV_WRAPx(5, type, name, __VA_ARGS__)
-#define HV_WRAP6(type, name, ...) HV_WRAPx(6, type, name, __VA_ARGS__)
-#define HV_WRAP7(type, name, ...) HV_WRAPx(7, type, name, __VA_ARGS__)
-#define HV_WRAP8(type, name, ...) HV_WRAPx(8, type, name, __VA_ARGS__)
-#define HV_WRAP9(type, name, ...) HV_WRAPx(9, type, name, __VA_ARGS__)
-
-/* List all the hypervisor API functions. */
-HV_WRAP4(void, hv_init, HV_VersionNumber, interface_version_number,
- int, chip_num, int, chip_rev_num, int, client_pl)
-HV_WRAP1(long, hv_sysconf, HV_SysconfQuery, query)
-HV_WRAP3(int, hv_confstr, HV_ConfstrQuery, query, HV_VirtAddr, buf, int, len)
-#if CHIP_HAS_IPI()
-HV_WRAP3(int, hv_get_ipi_pte, HV_Coord, tile, int, pl, HV_PTE*, pte)
-HV_WRAP3(int, hv_console_set_ipi, int, ipi, int, event, HV_Coord, coord);
-#else
-HV_WRAP1(void, hv_enable_intr, HV_IntrMask, enab_mask)
-HV_WRAP1(void, hv_disable_intr, HV_IntrMask, disab_mask)
-HV_WRAP1(void, hv_clear_intr, HV_IntrMask, clear_mask)
-HV_WRAP1(void, hv_raise_intr, HV_IntrMask, raise_mask)
-HV_WRAP2(HV_Errno, hv_trigger_ipi, HV_Coord, tile, int, interrupt)
-#endif /* !CHIP_HAS_IPI() */
-HV_WRAP3(int, hv_store_mapping, HV_VirtAddr, va, unsigned int, len,
- HV_PhysAddr, pa)
-HV_WRAP2(HV_PhysAddr, hv_inquire_realpa, HV_PhysAddr, cpa, unsigned int, len)
-HV_WRAP0(HV_RTCTime, hv_get_rtc)
-HV_WRAP1(void, hv_set_rtc, HV_RTCTime, time)
-HV_WRAP4(int, hv_install_context, HV_PhysAddr, page_table, HV_PTE, access,
- HV_ASID, asid, __hv32, flags)
-HV_WRAP2(int, hv_set_pte_super_shift, int, level, int, log2_count)
-HV_WRAP0(HV_Context, hv_inquire_context)
-HV_WRAP1(int, hv_flush_asid, HV_ASID, asid)
-HV_WRAP2(int, hv_flush_page, HV_VirtAddr, address, HV_PageSize, page_size)
-HV_WRAP3(int, hv_flush_pages, HV_VirtAddr, start, HV_PageSize, page_size,
- unsigned long, size)
-HV_WRAP1(int, hv_flush_all, int, preserve_global)
-HV_WRAP2(void, hv_restart, HV_VirtAddr, cmd, HV_VirtAddr, args)
-HV_WRAP0(void, hv_halt)
-HV_WRAP0(void, hv_power_off)
-HV_WRAP1(int, hv_reexec, HV_PhysAddr, entry)
-HV_WRAP0(HV_Topology, hv_inquire_topology)
-HV_WRAP3(HV_Errno, hv_inquire_tiles, HV_InqTileSet, set, HV_VirtAddr, cpumask,
- int, length)
-HV_WRAP1(HV_PhysAddrRange, hv_inquire_physical, int, idx)
-HV_WRAP2(HV_MemoryControllerInfo, hv_inquire_memory_controller, HV_Coord, coord,
- int, controller)
-HV_WRAP1(HV_VirtAddrRange, hv_inquire_virtual, int, idx)
-HV_WRAP1(HV_ASIDRange, hv_inquire_asid, int, idx)
-HV_WRAP1(void, hv_nanosleep, int, nanosecs)
-HV_WRAP0(int, hv_console_read_if_ready)
-HV_WRAP1(void, hv_console_putc, int, byte)
-HV_WRAP2(int, hv_console_write, HV_VirtAddr, bytes, int, len)
-HV_WRAP0(void, hv_downcall_dispatch)
-HV_WRAP1(int, hv_fs_findfile, HV_VirtAddr, filename)
-HV_WRAP1(HV_FS_StatInfo, hv_fs_fstat, int, inode)
-HV_WRAP4(int, hv_fs_pread, int, inode, HV_VirtAddr, buf,
- int, length, int, offset)
-HV_WRAP2(unsigned long long, hv_physaddr_read64, HV_PhysAddr, addr,
- HV_PTE, access)
-HV_WRAP3(void, hv_physaddr_write64, HV_PhysAddr, addr, HV_PTE, access,
- unsigned long long, val)
-HV_WRAP2(int, hv_get_command_line, HV_VirtAddr, buf, int, length)
-HV_WRAP2(HV_Errno, hv_set_command_line, HV_VirtAddr, buf, int, length)
-HV_WRAP1(void, hv_set_caching, unsigned long, bitmask)
-HV_WRAP2(void, hv_bzero_page, HV_VirtAddr, va, unsigned int, size)
-HV_WRAP1(HV_Errno, hv_register_message_state, HV_MsgState*, msgstate)
-HV_WRAP4(int, hv_send_message, HV_Recipient *, recips, int, nrecip,
- HV_VirtAddr, buf, int, buflen)
-HV_WRAP3(HV_RcvMsgInfo, hv_receive_message, HV_MsgState, msgstate,
- HV_VirtAddr, buf, int, buflen)
-HV_WRAP0(void, hv_start_all_tiles)
-HV_WRAP2(int, hv_dev_open, HV_VirtAddr, name, __hv32, flags)
-HV_WRAP1(int, hv_dev_close, int, devhdl)
-HV_WRAP5(int, hv_dev_pread, int, devhdl, __hv32, flags, HV_VirtAddr, va,
- __hv32, len, __hv64, offset)
-HV_WRAP5(int, hv_dev_pwrite, int, devhdl, __hv32, flags, HV_VirtAddr, va,
- __hv32, len, __hv64, offset)
-HV_WRAP3(int, hv_dev_poll, int, devhdl, __hv32, events, HV_IntArg, intarg)
-HV_WRAP1(int, hv_dev_poll_cancel, int, devhdl)
-HV_WRAP6(int, hv_dev_preada, int, devhdl, __hv32, flags, __hv32, sgl_len,
- HV_SGL *, sglp, __hv64, offset, HV_IntArg, intarg)
-HV_WRAP6(int, hv_dev_pwritea, int, devhdl, __hv32, flags, __hv32, sgl_len,
- HV_SGL *, sglp, __hv64, offset, HV_IntArg, intarg)
-HV_WRAP9(int, hv_flush_remote, HV_PhysAddr, cache_pa,
- unsigned long, cache_control, unsigned long*, cache_cpumask,
- HV_VirtAddr, tlb_va, unsigned long, tlb_length,
- unsigned long, tlb_pgsize, unsigned long*, tlb_cpumask,
- HV_Remote_ASID*, asids, int, asidcount)
-HV_WRAP3(HV_NMI_Info, hv_send_nmi, HV_Coord, tile, unsigned long, info,
- __hv64, flags)
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
deleted file mode 100644
index 9ff75e3a318a..000000000000
--- a/arch/tile/kernel/intvec_32.S
+++ /dev/null
@@ -1,1906 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Linux interrupt vectors.
- */
-
-#include <linux/linkage.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/unistd.h>
-#include <asm/ptrace.h>
-#include <asm/thread_info.h>
-#include <asm/irqflags.h>
-#include <asm/atomic_32.h>
-#include <asm/asm-offsets.h>
-#include <hv/hypervisor.h>
-#include <arch/abi.h>
-#include <arch/interrupts.h>
-#include <arch/spr_def.h>
-
-#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
-
-#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
-
- .macro push_reg reg, ptr=sp, delta=-4
- {
- sw \ptr, \reg
- addli \ptr, \ptr, \delta
- }
- .endm
-
- .macro pop_reg reg, ptr=sp, delta=4
- {
- lw \reg, \ptr
- addli \ptr, \ptr, \delta
- }
- .endm
-
- .macro pop_reg_zero reg, zreg, ptr=sp, delta=4
- {
- move \zreg, zero
- lw \reg, \ptr
- addi \ptr, \ptr, \delta
- }
- .endm
-
- .macro push_extra_callee_saves reg
- PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
- push_reg r51, \reg
- push_reg r50, \reg
- push_reg r49, \reg
- push_reg r48, \reg
- push_reg r47, \reg
- push_reg r46, \reg
- push_reg r45, \reg
- push_reg r44, \reg
- push_reg r43, \reg
- push_reg r42, \reg
- push_reg r41, \reg
- push_reg r40, \reg
- push_reg r39, \reg
- push_reg r38, \reg
- push_reg r37, \reg
- push_reg r36, \reg
- push_reg r35, \reg
- push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
- .endm
-
- .macro panic str
- .pushsection .rodata, "a"
-1:
- .asciz "\str"
- .popsection
- {
- moveli r0, lo16(1b)
- }
- {
- auli r0, r0, ha16(1b)
- jal panic
- }
- .endm
-
-#ifdef __COLLECT_LINKER_FEEDBACK__
- .pushsection .text.intvec_feedback,"ax"
-intvec_feedback:
- .popsection
-#endif
-
- /*
- * Default interrupt handler.
- *
- * vecnum is where we'll put this code.
- * c_routine is the C routine we'll call.
- *
- * The C routine is passed two arguments:
- * - A pointer to the pt_regs state.
- * - The interrupt vector number.
- *
- * The "processing" argument specifies the code for processing
- * the interrupt. Defaults to "handle_interrupt".
- */
- .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
- .org (\vecnum << 8)
-intvec_\vecname:
- .ifc \vecnum, INT_SWINT_1
- blz TREG_SYSCALL_NR_NAME, sys_cmpxchg
- .endif
-
- /* Temporarily save a register so we have somewhere to work. */
-
- mtspr SPR_SYSTEM_SAVE_K_1, r0
- mfspr r0, SPR_EX_CONTEXT_K_1
-
- /* The cmpxchg code clears sp to force us to reset it here on fault. */
- {
- bz sp, 2f
- andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
- }
-
- .ifc \vecnum, INT_DOUBLE_FAULT
- /*
- * For double-faults from user-space, fall through to the normal
- * register save and stack setup path. Otherwise, it's the
- * hypervisor giving us one last chance to dump diagnostics, and we
- * branch to the kernel_double_fault routine to do so.
- */
- bz r0, 1f
- j _kernel_double_fault
-1:
- .else
- /*
- * If we're coming from user-space, then set sp to the top of
- * the kernel stack. Otherwise, assume sp is already valid.
- */
- {
- bnz r0, 0f
- move r0, sp
- }
- .endif
-
- .ifc \c_routine, do_page_fault
- /*
- * The page_fault handler may be downcalled directly by the
- * hypervisor even when Linux is running and has ICS set.
- *
- * In this case the contents of EX_CONTEXT_K_1 reflect the
- * previous fault and can't be relied on to choose whether or
- * not to reinitialize the stack pointer. So we add a test
- * to see whether SYSTEM_SAVE_K_2 has the high bit set,
- * and if so we don't reinitialize sp, since we must be coming
- * from Linux. (In fact the precise case is !(val & ~1),
- * but any Linux PC has to have the high bit set.)
- *
- * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
- * any path that turns into a downcall to one of our TLB handlers.
- */
- mfspr r0, SPR_SYSTEM_SAVE_K_2
- {
- blz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
- move r0, sp
- }
- .endif
-
-2:
- /*
- * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
- * the current stack top in the higher bits. So we recover
- * our stack top by just masking off the low bits, then
- * point sp at the top aligned address on the actual stack page.
- */
- mfspr r0, SPR_SYSTEM_SAVE_K_0
- mm r0, r0, zero, LOG2_NR_CPU_IDS, 31
-
-0:
- /*
- * Align the stack mod 64 so we can properly predict what
- * cache lines we need to write-hint to reduce memory fetch
- * latency as we enter the kernel. The layout of memory is
- * as follows, with cache line 0 at the lowest VA, and cache
- * line 4 just below the r0 value this "andi" computes.
- * Note that we never write to cache line 4, and we skip
- * cache line 1 for syscalls.
- *
- * cache line 4: ptregs padding (two words)
- * cache line 3: r46...lr, pc, ex1, faultnum, orig_r0, flags, pad
- * cache line 2: r30...r45
- * cache line 1: r14...r29
- * cache line 0: 2 x frame, r0..r13
- */
-#if STACK_TOP_DELTA != 64
-#error STACK_TOP_DELTA must be 64 for assumptions here and in task_pt_regs()
-#endif
- andi r0, r0, -64
-
- /*
- * Push the first four registers on the stack, so that we can set
- * them to vector-unique values before we jump to the common code.
- *
- * Registers are pushed on the stack as a struct pt_regs,
- * with the sp initially just above the struct, and when we're
- * done, sp points to the base of the struct, minus
- * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
- *
- * This routine saves just the first four registers, plus the
- * stack context so we can do proper backtracing right away,
- * and defers to handle_interrupt to save the rest.
- * The backtracer needs pc, ex1, lr, sp, r52, and faultnum.
- */
- addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
- wh64 r0 /* cache line 3 */
- {
- sw r0, lr
- addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
- }
- {
- sw r0, sp
- addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
- }
- {
- sw sp, r52
- addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
- }
- wh64 sp /* cache line 0 */
- {
- sw sp, r1
- addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
- }
- {
- sw sp, r2
- addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
- }
- {
- sw sp, r3
- addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
- }
- mfspr r0, SPR_EX_CONTEXT_K_0
- .ifc \processing,handle_syscall
- /*
- * Bump the saved PC by one bundle so that when we return, we won't
- * execute the same swint instruction again. We need to do this while
- * we're in the critical section.
- */
- addi r0, r0, 8
- .endif
- {
- sw sp, r0
- addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
- }
- mfspr r0, SPR_EX_CONTEXT_K_1
- {
- sw sp, r0
- addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
- /*
- * Use r0 for syscalls so it's a temporary; use r1 for interrupts
- * so that it gets passed through unchanged to the handler routine.
- * Note that the .if conditional confusingly spans bundles.
- */
- .ifc \processing,handle_syscall
- movei r0, \vecnum
- }
- {
- sw sp, r0
- .else
- movei r1, \vecnum
- }
- {
- sw sp, r1
- .endif
- addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
- }
- mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
- {
- sw sp, r0
- addi sp, sp, -PTREGS_OFFSET_REG(0) - 4
- }
- {
- sw sp, zero /* write zero into "Next SP" frame pointer */
- addi sp, sp, -4 /* leave SP pointing at bottom of frame */
- }
- .ifc \processing,handle_syscall
- j handle_syscall
- .else
- /*
- * Capture per-interrupt SPR context to registers.
- * We overload the meaning of r3 on this path such that if its bit 31
- * is set, we have to mask all interrupts including NMIs before
- * clearing the interrupt critical section bit.
- * See discussion below at "finish_interrupt_save".
- */
- .ifc \c_routine, do_page_fault
- mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
- mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
- .else
- .ifc \vecnum, INT_DOUBLE_FAULT
- {
- mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
- movei r3, 0
- }
- .else
- .ifc \c_routine, do_trap
- {
- mfspr r2, GPV_REASON
- movei r3, 0
- }
- .else
- .ifc \c_routine, handle_perf_interrupt
- {
- mfspr r2, PERF_COUNT_STS
- movei r3, -1 /* not used, but set for consistency */
- }
- .else
- .ifc \c_routine, handle_perf_interrupt
- {
- mfspr r2, AUX_PERF_COUNT_STS
- movei r3, -1 /* not used, but set for consistency */
- }
- .else
- movei r3, 0
- .endif
- .endif
- .endif
- .endif
- .endif
- /* Put function pointer in r0 */
- moveli r0, lo16(\c_routine)
- {
- auli r0, r0, ha16(\c_routine)
- j \processing
- }
- .endif
- ENDPROC(intvec_\vecname)
-
-#ifdef __COLLECT_LINKER_FEEDBACK__
- .pushsection .text.intvec_feedback,"ax"
- .org (\vecnum << 5)
- FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt, 1 << 8)
- jrp lr
- .popsection
-#endif
-
- .endm
-
-
- /*
- * Save the rest of the registers that we didn't save in the actual
- * vector itself. We can't use r0-r10 inclusive here.
- */
- .macro finish_interrupt_save, function
-
- /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
- PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
- {
- .ifc \function,handle_syscall
- sw r52, r0
- .else
- sw r52, zero
- .endif
- PTREGS_PTR(r52, PTREGS_OFFSET_TP)
- }
-
- /*
- * For ordinary syscalls, we save neither caller- nor callee-
- * save registers, since the syscall invoker doesn't expect the
- * caller-saves to be saved, and the called kernel functions will
- * take care of saving the callee-saves for us.
- *
- * For interrupts we save just the caller-save registers. Saving
- * them is required (since the "caller" can't save them). Again,
- * the called kernel functions will restore the callee-save
- * registers for us appropriately.
- *
- * On return, we normally restore nothing special for syscalls,
- * and just the caller-save registers for interrupts.
- *
- * However, there are some important caveats to all this:
- *
- * - We always save a few callee-save registers to give us
- * some scratchpad registers to carry across function calls.
- *
- * - fork/vfork/etc require us to save all the callee-save
- * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
- *
- * - We always save r0..r5 and r10 for syscalls, since we need
- * to reload them a bit later for the actual kernel call, and
- * since we might need them for -ERESTARTNOINTR, etc.
- *
- * - Before invoking a signal handler, we save the unsaved
- * callee-save registers so they are visible to the
- * signal handler or any ptracer.
- *
- * - If the unsaved callee-save registers are modified, we set
- * a bit in pt_regs so we know to reload them from pt_regs
- * and not just rely on the kernel function unwinding.
- * (Done for ptrace register writes and SA_SIGINFO handler.)
- */
- {
- sw r52, tp
- PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
- }
- wh64 r52 /* cache line 2 */
- push_reg r33, r52
- push_reg r32, r52
- push_reg r31, r52
- .ifc \function,handle_syscall
- push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
- push_reg TREG_SYSCALL_NR_NAME, r52, \
- PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
- .else
-
- push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
- wh64 r52 /* cache line 1 */
- push_reg r29, r52
- push_reg r28, r52
- push_reg r27, r52
- push_reg r26, r52
- push_reg r25, r52
- push_reg r24, r52
- push_reg r23, r52
- push_reg r22, r52
- push_reg r21, r52
- push_reg r20, r52
- push_reg r19, r52
- push_reg r18, r52
- push_reg r17, r52
- push_reg r16, r52
- push_reg r15, r52
- push_reg r14, r52
- push_reg r13, r52
- push_reg r12, r52
- push_reg r11, r52
- push_reg r10, r52
- push_reg r9, r52
- push_reg r8, r52
- push_reg r7, r52
- push_reg r6, r52
-
- .endif
-
- push_reg r5, r52
- sw r52, r4
-
- /* Load tp with our per-cpu offset. */
-#ifdef CONFIG_SMP
- {
- mfspr r20, SPR_SYSTEM_SAVE_K_0
- moveli r21, lo16(__per_cpu_offset)
- }
- {
- auli r21, r21, ha16(__per_cpu_offset)
- mm r20, r20, zero, 0, LOG2_NR_CPU_IDS-1
- }
- s2a r20, r20, r21
- lw tp, r20
-#else
- move tp, zero
-#endif
-
- /*
- * If we will be returning to the kernel, we will need to
- * reset the interrupt masks to the state they had before.
- * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
- * We load flags in r32 here so we can jump to .Lrestore_regs
- * directly after do_page_fault_ics() if necessary.
- */
- mfspr r32, SPR_EX_CONTEXT_K_1
- {
- andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
- PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
- }
- bzt r32, 1f /* zero if from user space */
- IRQS_DISABLED(r32) /* zero if irqs enabled */
-#if PT_FLAGS_DISABLE_IRQ != 1
-# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
-#endif
-1:
- .ifnc \function,handle_syscall
- /* Record the fact that we saved the caller-save registers above. */
- ori r32, r32, PT_FLAGS_CALLER_SAVES
- .endif
- sw r21, r32
-
-#ifdef __COLLECT_LINKER_FEEDBACK__
- /*
- * Notify the feedback routines that we were in the
- * appropriate fixed interrupt vector area. Note that we
- * still have ICS set at this point, so we can't invoke any
- * atomic operations or we will panic. The feedback
- * routines internally preserve r0..r10 and r30 up.
- */
- .ifnc \function,handle_syscall
- shli r20, r1, 5
- .else
- moveli r20, INT_SWINT_1 << 5
- .endif
- addli r20, r20, lo16(intvec_feedback)
- auli r20, r20, ha16(intvec_feedback)
- jalr r20
-
- /* And now notify the feedback routines that we are here. */
- FEEDBACK_ENTER(\function)
-#endif
-
- /*
- * we've captured enough state to the stack (including in
- * particular our EX_CONTEXT state) that we can now release
- * the interrupt critical section and replace it with our
- * standard "interrupts disabled" mask value. This allows
- * synchronous interrupts (and profile interrupts) to punch
- * through from this point onwards.
- *
- * If bit 31 of r3 is set during a non-NMI interrupt, we know we
- * are on the path where the hypervisor has punched through our
- * ICS with a page fault, so we call out to do_page_fault_ics()
- * to figure out what to do with it. If the fault was in
- * an atomic op, we unlock the atomic lock, adjust the
- * saved register state a little, and return "zero" in r4,
- * falling through into the normal page-fault interrupt code.
- * If the fault was in a kernel-space atomic operation, then
- * do_page_fault_ics() resolves it itself, returns "one" in r4,
- * and as a result goes directly to restoring registers and iret,
- * without trying to adjust the interrupt masks at all.
- * The do_page_fault_ics() API involves passing and returning
- * a five-word struct (in registers) to avoid writing the
- * save and restore code here.
- */
- .ifc \function,handle_nmi
- IRQ_DISABLE_ALL(r20)
- .else
- .ifnc \function,handle_syscall
- bgezt r3, 1f
- {
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- jal do_page_fault_ics
- }
- FEEDBACK_REENTER(\function)
- bzt r4, 1f
- j .Lrestore_regs
-1:
- .endif
- IRQ_DISABLE(r20, r21)
- .endif
- mtspr INTERRUPT_CRITICAL_SECTION, zero
-
- /*
- * Prepare the first 256 stack bytes to be rapidly accessible
- * without having to fetch the background data. We don't really
- * know how far to write-hint, but kernel stacks generally
- * aren't that big, and write-hinting here does take some time.
- */
- addi r52, sp, -64
- {
- wh64 r52
- addi r52, r52, -64
- }
- {
- wh64 r52
- addi r52, r52, -64
- }
- {
- wh64 r52
- addi r52, r52, -64
- }
- wh64 r52
-
-#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
- .ifnc \function,handle_nmi
- /*
- * We finally have enough state set up to notify the irq
- * tracing code that irqs were disabled on entry to the handler.
- * The TRACE_IRQS_OFF call clobbers registers r0-r29.
- * For syscalls, we already have the register state saved away
- * on the stack, so we don't bother to do any register saves here,
- * and later we pop the registers back off the kernel stack.
- * For interrupt handlers, save r0-r3 in callee-saved registers.
- */
- .ifnc \function,handle_syscall
- { move r30, r0; move r31, r1 }
- { move r32, r2; move r33, r3 }
- .endif
- TRACE_IRQS_OFF
-#ifdef CONFIG_CONTEXT_TRACKING
- jal context_tracking_user_exit
-#endif
- .ifnc \function,handle_syscall
- { move r0, r30; move r1, r31 }
- { move r2, r32; move r3, r33 }
- .endif
- .endif
-#endif
-
- .endm
-
- .macro check_single_stepping, kind, not_single_stepping
- /*
- * Check for single stepping in user-level priv
- * kind can be "normal", "ill", or "syscall"
- * At end, if fall-thru
- * r29: thread_info->step_state
- * r28: &pt_regs->pc
- * r27: pt_regs->pc
- * r26: thread_info->step_state->buffer
- */
-
- /* Check for single stepping */
- GET_THREAD_INFO(r29)
- {
- /* Get pointer to field holding step state */
- addi r29, r29, THREAD_INFO_STEP_STATE_OFFSET
-
- /* Get pointer to EX1 in register state */
- PTREGS_PTR(r27, PTREGS_OFFSET_EX1)
- }
- {
- /* Get pointer to field holding PC */
- PTREGS_PTR(r28, PTREGS_OFFSET_PC)
-
- /* Load the pointer to the step state */
- lw r29, r29
- }
- /* Load EX1 */
- lw r27, r27
- {
- /* Points to flags */
- addi r23, r29, SINGLESTEP_STATE_FLAGS_OFFSET
-
- /* No single stepping if there is no step state structure */
- bzt r29, \not_single_stepping
- }
- {
- /* mask off ICS and any other high bits */
- andi r27, r27, SPR_EX_CONTEXT_1_1__PL_MASK
-
- /* Load pointer to single step instruction buffer */
- lw r26, r29
- }
- /* Check priv state */
- bnz r27, \not_single_stepping
-
- /* Get flags */
- lw r22, r23
- {
- /* Branch if single-step mode not enabled */
- bbnst r22, \not_single_stepping
-
- /* Clear enabled flag */
- andi r22, r22, ~SINGLESTEP_STATE_MASK_IS_ENABLED
- }
- .ifc \kind,normal
- {
- /* Load PC */
- lw r27, r28
-
- /* Point to the entry containing the original PC */
- addi r24, r29, SINGLESTEP_STATE_ORIG_PC_OFFSET
- }
- {
- /* Disable single stepping flag */
- sw r23, r22
- }
- {
- /* Get the original pc */
- lw r24, r24
-
- /* See if the PC is at the start of the single step buffer */
- seq r25, r26, r27
- }
- /*
- * NOTE: it is really expected that the PC be in the single step buffer
- * at this point
- */
- bzt r25, \not_single_stepping
-
- /* Restore the original PC */
- sw r28, r24
- .else
- .ifc \kind,syscall
- {
- /* Load PC */
- lw r27, r28
-
- /* Point to the entry containing the next PC */
- addi r24, r29, SINGLESTEP_STATE_NEXT_PC_OFFSET
- }
- {
- /* Increment the stopped PC by the bundle size */
- addi r26, r26, 8
-
- /* Disable single stepping flag */
- sw r23, r22
- }
- {
- /* Get the next pc */
- lw r24, r24
-
- /*
- * See if the PC is one bundle past the start of the
- * single step buffer
- */
- seq r25, r26, r27
- }
- {
- /*
- * NOTE: it is really expected that the PC be in the
- * single step buffer at this point
- */
- bzt r25, \not_single_stepping
- }
- /* Set to the next PC */
- sw r28, r24
- .else
- {
- /* Point to 3rd bundle in buffer */
- addi r25, r26, 16
-
- /* Load PC */
- lw r27, r28
- }
- {
- /* Disable single stepping flag */
- sw r23, r22
-
- /* See if the PC is in the single step buffer */
- slte_u r24, r26, r27
- }
- {
- slte_u r25, r27, r25
-
- /*
- * NOTE: it is really expected that the PC be in the
- * single step buffer at this point
- */
- bzt r24, \not_single_stepping
- }
- bzt r25, \not_single_stepping
- .endif
- .endif
- .endm
-
- /*
- * Redispatch a downcall.
- */
- .macro dc_dispatch vecnum, vecname
- .org (\vecnum << 8)
-intvec_\vecname:
- j _hv_downcall_dispatch
- ENDPROC(intvec_\vecname)
- .endm
-
- /*
- * Common code for most interrupts. The C function we're eventually
- * going to is in r0, and the faultnum is in r1; the original
- * values for those registers are on the stack.
- */
- .pushsection .text.handle_interrupt,"ax"
-handle_interrupt:
- finish_interrupt_save handle_interrupt
-
- /*
- * Check for if we are single stepping in user level. If so, then
- * we need to restore the PC.
- */
-
- check_single_stepping normal, .Ldispatch_interrupt
-.Ldispatch_interrupt:
-
- /* Jump to the C routine; it should enable irqs as soon as possible. */
- {
- jalr r0
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- }
- FEEDBACK_REENTER(handle_interrupt)
- {
- movei r30, 0 /* not an NMI */
- j interrupt_return
- }
- STD_ENDPROC(handle_interrupt)
-
-/*
- * This routine takes a boolean in r30 indicating if this is an NMI.
- * If so, we also expect a boolean in r31 indicating whether to
- * re-enable the oprofile interrupts.
- *
- * Note that .Lresume_userspace is jumped to directly in several
- * places, and we need to make sure r30 is set correctly in those
- * callers as well.
- */
-STD_ENTRY(interrupt_return)
- /* If we're resuming to kernel space, don't check thread flags. */
- {
- bnz r30, .Lrestore_all /* NMIs don't special-case user-space */
- PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
- }
- lw r29, r29
- andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
- bzt r29, .Lresume_userspace
-
-#ifdef CONFIG_PREEMPT
- /* Returning to kernel space. Check if we need preemption. */
- GET_THREAD_INFO(r29)
- addli r28, r29, THREAD_INFO_FLAGS_OFFSET
- {
- lw r28, r28
- addli r29, r29, THREAD_INFO_PREEMPT_COUNT_OFFSET
- }
- {
- andi r28, r28, _TIF_NEED_RESCHED
- lw r29, r29
- }
- bzt r28, 1f
- bnz r29, 1f
- /* Disable interrupts explicitly for preemption. */
- IRQ_DISABLE(r20,r21)
- TRACE_IRQS_OFF
- jal preempt_schedule_irq
- FEEDBACK_REENTER(interrupt_return)
-1:
-#endif
-
- /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
- {
- PTREGS_PTR(r29, PTREGS_OFFSET_PC)
- moveli r27, lo16(_cpu_idle_nap)
- }
- {
- lw r28, r29
- auli r27, r27, ha16(_cpu_idle_nap)
- }
- {
- seq r27, r27, r28
- }
- {
- bbns r27, .Lrestore_all
- addi r28, r28, 8
- }
- sw r29, r28
- j .Lrestore_all
-
-.Lresume_userspace:
- FEEDBACK_REENTER(interrupt_return)
-
- /*
- * Disable interrupts so as to make sure we don't
- * miss an interrupt that sets any of the thread flags (like
- * need_resched or sigpending) between sampling and the iret.
- * Routines like schedule() or do_signal() may re-enable
- * interrupts before returning.
- */
- IRQ_DISABLE(r20, r21)
- TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
-
- /*
- * See if there are any work items (including single-shot items)
- * to do. If so, save the callee-save registers to pt_regs
- * and then dispatch to C code.
- */
- GET_THREAD_INFO(r21)
- {
- addi r22, r21, THREAD_INFO_FLAGS_OFFSET
- moveli r20, lo16(_TIF_ALLWORK_MASK)
- }
- {
- lw r22, r22
- auli r20, r20, ha16(_TIF_ALLWORK_MASK)
- }
- and r1, r22, r20
- {
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- bzt r1, .Lrestore_all
- }
- push_extra_callee_saves r0
- jal prepare_exit_to_usermode
-
- /*
- * In the NMI case we
- * omit the call to single_process_check_nohz, which normally checks
- * to see if we should start or stop the scheduler tick, because
- * we can't call arbitrary Linux code from an NMI context.
- * We always call the homecache TLB deferral code to re-trigger
- * the deferral mechanism.
- *
- * The other chunk of responsibility this code has is to reset the
- * interrupt masks appropriately to reset irqs and NMIs. We have
- * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
- * lockdep-type stuff, but we can't set ICS until afterwards, since
- * ICS can only be used in very tight chunks of code to avoid
- * tripping over various assertions that it is off.
- *
- * (There is what looks like a window of vulnerability here since
- * we might take a profile interrupt between the two SPR writes
- * that set the mask, but since we write the low SPR word first,
- * and our interrupt entry code checks the low SPR word, any
- * profile interrupt will actually disable interrupts in both SPRs
- * before returning, which is OK.)
- */
-.Lrestore_all:
- PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
- {
- lw r0, r0
- PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
- }
- {
- andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
- lw r32, r32
- }
- bnz r0, 1f
- j 2f
-#if PT_FLAGS_DISABLE_IRQ != 1
-# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use bbnst below
-#endif
-1: bbnst r32, 2f
- IRQ_DISABLE(r20,r21)
- TRACE_IRQS_OFF
- movei r0, 1
- mtspr INTERRUPT_CRITICAL_SECTION, r0
- bzt r30, .Lrestore_regs
- j 3f
-2: TRACE_IRQS_ON
- movei r0, 1
- mtspr INTERRUPT_CRITICAL_SECTION, r0
- IRQ_ENABLE(r20, r21)
- bzt r30, .Lrestore_regs
-3:
-
- /* We are relying on INT_PERF_COUNT at 33, and AUX_PERF_COUNT at 48 */
- {
- moveli r0, lo16(1 << (INT_PERF_COUNT - 32))
- bz r31, .Lrestore_regs
- }
- auli r0, r0, ha16(1 << (INT_AUX_PERF_COUNT - 32))
- mtspr SPR_INTERRUPT_MASK_RESET_K_1, r0
-
- /*
- * We now commit to returning from this interrupt, since we will be
- * doing things like setting EX_CONTEXT SPRs and unwinding the stack
- * frame. No calls should be made to any other code after this point.
- * This code should only be entered with ICS set.
- * r32 must still be set to ptregs.flags.
- * We launch loads to each cache line separately first, so we can
- * get some parallelism out of the memory subsystem.
- * We start zeroing caller-saved registers throughout, since
- * that will save some cycles if this turns out to be a syscall.
- */
-.Lrestore_regs:
- FEEDBACK_REENTER(interrupt_return) /* called from elsewhere */
-
- /*
- * Rotate so we have one high bit and one low bit to test.
- * - low bit says whether to restore all the callee-saved registers,
- * or just r30-r33, and r52 up.
- * - high bit (i.e. sign bit) says whether to restore all the
- * caller-saved registers, or just r0.
- */
-#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
-# error Rotate trick does not work :-)
-#endif
- {
- rli r20, r32, 30
- PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
- }
-
- /*
- * Load cache lines 0, 2, and 3 in that order, then use
- * the last loaded value, which makes it likely that the other
- * cache lines have also loaded, at which point we should be
- * able to safely read all the remaining words on those cache
- * lines without waiting for the memory subsystem.
- */
- pop_reg_zero r0, r28, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
- pop_reg_zero r30, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(30)
- pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
- pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1
- {
- mtspr SPR_EX_CONTEXT_K_0, r21
- move r5, zero
- }
- {
- mtspr SPR_EX_CONTEXT_K_1, lr
- andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
- }
-
- /* Restore callee-saveds that we actually use. */
- pop_reg_zero r52, r6, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_REG(52)
- pop_reg_zero r31, r7
- pop_reg_zero r32, r8
- pop_reg_zero r33, r9, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
-
- /*
- * If we modified other callee-saveds, restore them now.
- * This is rare, but could be via ptrace or signal handler.
- */
- {
- move r10, zero
- bbs r20, .Lrestore_callees
- }
-.Lcontinue_restore_regs:
-
- /* Check if we're returning from a syscall. */
- {
- move r11, zero
- blzt r20, 1f /* no, so go restore callee-save registers */
- }
-
- /*
- * Check if we're returning to userspace.
- * Note that if we're not, we don't worry about zeroing everything.
- */
- {
- addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
- bnz lr, .Lkernel_return
- }
-
- /*
- * On return from syscall, we've restored r0 from pt_regs, but we
- * clear the remainder of the caller-saved registers. We could
- * restore the syscall arguments, but there's not much point,
- * and it ensures user programs aren't trying to use the
- * caller-saves if we clear them, as well as avoiding leaking
- * kernel pointers into userspace.
- */
- pop_reg_zero lr, r12, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
- pop_reg_zero tp, r13, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
- {
- lw sp, sp
- move r14, zero
- move r15, zero
- }
- { move r16, zero; move r17, zero }
- { move r18, zero; move r19, zero }
- { move r20, zero; move r21, zero }
- { move r22, zero; move r23, zero }
- { move r24, zero; move r25, zero }
- { move r26, zero; move r27, zero }
-
- /* Set r1 to errno if we are returning an error, otherwise zero. */
- {
- moveli r29, 4096
- sub r1, zero, r0
- }
- slt_u r29, r1, r29
- {
- mnz r1, r29, r1
- move r29, zero
- }
- iret
-
- /*
- * Not a syscall, so restore caller-saved registers.
- * First kick off a load for cache line 1, which we're touching
- * for the first time here.
- */
- .align 64
-1: pop_reg r29, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(29)
- pop_reg r1
- pop_reg r2
- pop_reg r3
- pop_reg r4
- pop_reg r5
- pop_reg r6
- pop_reg r7
- pop_reg r8
- pop_reg r9
- pop_reg r10
- pop_reg r11
- pop_reg r12
- pop_reg r13
- pop_reg r14
- pop_reg r15
- pop_reg r16
- pop_reg r17
- pop_reg r18
- pop_reg r19
- pop_reg r20
- pop_reg r21
- pop_reg r22
- pop_reg r23
- pop_reg r24
- pop_reg r25
- pop_reg r26
- pop_reg r27
- pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
- /* r29 already restored above */
- bnz lr, .Lkernel_return
- pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
- pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
- lw sp, sp
- iret
-
- /*
- * We can't restore tp when in kernel mode, since a thread might
- * have migrated from another cpu and brought a stale tp value.
- */
-.Lkernel_return:
- pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
- lw sp, sp
- iret
-
- /* Restore callee-saved registers from r34 to r51. */
-.Lrestore_callees:
- addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
- pop_reg r34
- pop_reg r35
- pop_reg r36
- pop_reg r37
- pop_reg r38
- pop_reg r39
- pop_reg r40
- pop_reg r41
- pop_reg r42
- pop_reg r43
- pop_reg r44
- pop_reg r45
- pop_reg r46
- pop_reg r47
- pop_reg r48
- pop_reg r49
- pop_reg r50
- pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
- j .Lcontinue_restore_regs
- STD_ENDPROC(interrupt_return)
-
- /*
- * Some interrupts don't check for single stepping
- */
- .pushsection .text.handle_interrupt_no_single_step,"ax"
-handle_interrupt_no_single_step:
- finish_interrupt_save handle_interrupt_no_single_step
- {
- jalr r0
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- }
- FEEDBACK_REENTER(handle_interrupt_no_single_step)
- {
- movei r30, 0 /* not an NMI */
- j interrupt_return
- }
- STD_ENDPROC(handle_interrupt_no_single_step)
-
- /*
- * "NMI" interrupts mask ALL interrupts before calling the
- * handler, and don't check thread flags, etc., on the way
- * back out. In general, the only things we do here for NMIs
- * are the register save/restore, fixing the PC if we were
- * doing single step, and the dataplane kernel-TLB management.
- * We don't (for example) deal with start/stop of the sched tick.
- */
- .pushsection .text.handle_nmi,"ax"
-handle_nmi:
- finish_interrupt_save handle_nmi
- check_single_stepping normal, .Ldispatch_nmi
-.Ldispatch_nmi:
- {
- jalr r0
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- }
- FEEDBACK_REENTER(handle_nmi)
- {
- movei r30, 1
- seq r31, r0, zero
- }
- j interrupt_return
- STD_ENDPROC(handle_nmi)
-
- /*
- * Parallel code for syscalls to handle_interrupt.
- */
- .pushsection .text.handle_syscall,"ax"
-handle_syscall:
- finish_interrupt_save handle_syscall
-
- /*
- * Check for if we are single stepping in user level. If so, then
- * we need to restore the PC.
- */
- check_single_stepping syscall, .Ldispatch_syscall
-.Ldispatch_syscall:
-
- /* Enable irqs. */
- TRACE_IRQS_ON
- IRQ_ENABLE(r20, r21)
-
- /* Bump the counter for syscalls made on this tile. */
- moveli r20, lo16(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
- auli r20, r20, ha16(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
- add r20, r20, tp
- lw r21, r20
- addi r21, r21, 1
- {
- sw r20, r21
- GET_THREAD_INFO(r31)
- }
-
- /* Trace syscalls, if requested. */
- addi r31, r31, THREAD_INFO_FLAGS_OFFSET
- lw r30, r31
- andi r30, r30, _TIF_SYSCALL_TRACE
- bzt r30, .Lrestore_syscall_regs
- {
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- jal do_syscall_trace_enter
- }
- FEEDBACK_REENTER(handle_syscall)
- blz r0, .Lsyscall_sigreturn_skip
-
- /*
- * We always reload our registers from the stack at this
- * point. They might be valid, if we didn't build with
- * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
- * doing syscall tracing, but there are enough cases now that it
- * seems simplest just to do the reload unconditionally.
- */
-.Lrestore_syscall_regs:
- PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
- pop_reg r0, r11
- pop_reg r1, r11
- pop_reg r2, r11
- pop_reg r3, r11
- pop_reg r4, r11
- pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
- pop_reg TREG_SYSCALL_NR_NAME, r11
-
- /* Ensure that the syscall number is within the legal range. */
- moveli r21, __NR_syscalls
- {
- slt_u r21, TREG_SYSCALL_NR_NAME, r21
- moveli r20, lo16(sys_call_table)
- }
- {
- bbns r21, .Linvalid_syscall
- auli r20, r20, ha16(sys_call_table)
- }
- s2a r20, TREG_SYSCALL_NR_NAME, r20
- lw r20, r20
-
- /* Jump to syscall handler. */
- jalr r20
-.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
-
- /*
- * Write our r0 onto the stack so it gets restored instead
- * of whatever the user had there before.
- */
- PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
- sw r29, r0
-
-.Lsyscall_sigreturn_skip:
- FEEDBACK_REENTER(handle_syscall)
-
- /* Do syscall trace again, if requested. */
- lw r30, r31
- andi r30, r30, _TIF_SYSCALL_TRACE
- bzt r30, 1f
- {
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- jal do_syscall_trace_exit
- }
- FEEDBACK_REENTER(handle_syscall)
-1: {
- movei r30, 0 /* not an NMI */
- j .Lresume_userspace /* jump into middle of interrupt_return */
- }
-
-.Linvalid_syscall:
- /* Report an invalid syscall back to the user program */
- {
- PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
- movei r28, -ENOSYS
- }
- sw r29, r28
- {
- movei r30, 0 /* not an NMI */
- j .Lresume_userspace /* jump into middle of interrupt_return */
- }
- STD_ENDPROC(handle_syscall)
-
- /* Return the address for oprofile to suppress in backtraces. */
-STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
- lnk r0
- {
- addli r0, r0, .Lhandle_syscall_link - .
- jrp lr
- }
- STD_ENDPROC(handle_syscall_link_address)
-
-STD_ENTRY(ret_from_fork)
- jal sim_notify_fork
- jal schedule_tail
- FEEDBACK_REENTER(ret_from_fork)
- {
- movei r30, 0 /* not an NMI */
- j .Lresume_userspace /* jump into middle of interrupt_return */
- }
- STD_ENDPROC(ret_from_fork)
-
-STD_ENTRY(ret_from_kernel_thread)
- jal sim_notify_fork
- jal schedule_tail
- FEEDBACK_REENTER(ret_from_fork)
- {
- move r0, r31
- jalr r30
- }
- FEEDBACK_REENTER(ret_from_kernel_thread)
- {
- movei r30, 0 /* not an NMI */
- j interrupt_return
- }
- STD_ENDPROC(ret_from_kernel_thread)
-
- /*
- * Code for ill interrupt.
- */
- .pushsection .text.handle_ill,"ax"
-handle_ill:
- finish_interrupt_save handle_ill
-
- /*
- * Check for if we are single stepping in user level. If so, then
- * we need to restore the PC.
- */
- check_single_stepping ill, .Ldispatch_normal_ill
-
- {
- /* See if the PC is the 1st bundle in the buffer */
- seq r25, r27, r26
-
- /* Point to the 2nd bundle in the buffer */
- addi r26, r26, 8
- }
- {
- /* Point to the original pc */
- addi r24, r29, SINGLESTEP_STATE_ORIG_PC_OFFSET
-
- /* Branch if the PC is the 1st bundle in the buffer */
- bnz r25, 3f
- }
- {
- /* See if the PC is the 2nd bundle of the buffer */
- seq r25, r27, r26
-
- /* Set PC to next instruction */
- addi r24, r29, SINGLESTEP_STATE_NEXT_PC_OFFSET
- }
- {
- /* Point to flags */
- addi r25, r29, SINGLESTEP_STATE_FLAGS_OFFSET
-
- /* Branch if PC is in the second bundle */
- bz r25, 2f
- }
- /* Load flags */
- lw r25, r25
- {
- /*
- * Get the offset for the register to restore
- * Note: the lower bound is 2, so we have implicit scaling by 4.
- * No multiplication of the register number by the size of a register
- * is needed.
- */
- mm r27, r25, zero, SINGLESTEP_STATE_TARGET_LB, \
- SINGLESTEP_STATE_TARGET_UB
-
- /* Mask Rewrite_LR */
- andi r25, r25, SINGLESTEP_STATE_MASK_UPDATE
- }
- {
- addi r29, r29, SINGLESTEP_STATE_UPDATE_VALUE_OFFSET
-
- /* Don't rewrite temp register */
- bz r25, 3f
- }
- {
- /* Get the temp value */
- lw r29, r29
-
- /* Point to where the register is stored */
- add r27, r27, sp
- }
-
- /* Add in the C ABI save area size to the register offset */
- addi r27, r27, C_ABI_SAVE_AREA_SIZE
-
- /* Restore the user's register with the temp value */
- sw r27, r29
- j 3f
-
-2:
- /* Must be in the third bundle */
- addi r24, r29, SINGLESTEP_STATE_BRANCH_NEXT_PC_OFFSET
-
-3:
- /* set PC and continue */
- lw r26, r24
- {
- sw r28, r26
- GET_THREAD_INFO(r0)
- }
-
- /*
- * Clear TIF_SINGLESTEP to prevent recursion if we execute an ill.
- * The normal non-arch flow redundantly clears TIF_SINGLESTEP, but we
- * need to clear it here and can't really impose on all other arches.
- * So what's another write between friends?
- */
-
- addi r1, r0, THREAD_INFO_FLAGS_OFFSET
- {
- lw r2, r1
- addi r0, r0, THREAD_INFO_TASK_OFFSET /* currently a no-op */
- }
- andi r2, r2, ~_TIF_SINGLESTEP
- sw r1, r2
-
- /* Issue a sigtrap */
- {
- lw r0, r0 /* indirect thru thread_info to get task_info*/
- addi r1, sp, C_ABI_SAVE_AREA_SIZE /* put ptregs pointer into r1 */
- }
-
- jal send_sigtrap /* issue a SIGTRAP */
- FEEDBACK_REENTER(handle_ill)
- {
- movei r30, 0 /* not an NMI */
- j .Lresume_userspace /* jump into middle of interrupt_return */
- }
-
-.Ldispatch_normal_ill:
- {
- jalr r0
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- }
- FEEDBACK_REENTER(handle_ill)
- {
- movei r30, 0 /* not an NMI */
- j interrupt_return
- }
- STD_ENDPROC(handle_ill)
-
-/* Various stub interrupt handlers and syscall handlers */
-
-STD_ENTRY_LOCAL(_kernel_double_fault)
- mfspr r1, SPR_EX_CONTEXT_K_0
- move r2, lr
- move r3, sp
- move r4, r52
- addi sp, sp, -C_ABI_SAVE_AREA_SIZE
- j kernel_double_fault
- STD_ENDPROC(_kernel_double_fault)
-
-STD_ENTRY_LOCAL(bad_intr)
- mfspr r2, SPR_EX_CONTEXT_K_0
- panic "Unhandled interrupt %#x: PC %#lx"
- STD_ENDPROC(bad_intr)
-
-/*
- * Special-case sigreturn to not write r0 to the stack on return.
- * This is technically more efficient, but it also avoids difficulties
- * in the 64-bit OS when handling 32-bit compat code, since we must not
- * sign-extend r0 for the sigreturn return-value case.
- */
-#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
- STD_ENTRY(_##x); \
- addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
- { \
- PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
- j x \
- }; \
- STD_ENDPROC(_##x)
-
-PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
-
-/* Save additional callee-saves to pt_regs and jump to standard function. */
-STD_ENTRY(_sys_clone)
- push_extra_callee_saves r4
- j sys_clone
- STD_ENDPROC(_sys_clone)
-
-/*
- * This entrypoint is taken for the cmpxchg and atomic_update fast
- * swints. We may wish to generalize it to other fast swints at some
- * point, but for now there are just two very similar ones, which
- * makes it faster.
- *
- * The fast swint code is designed to have a small footprint. It does
- * not save or restore any GPRs, counting on the caller-save registers
- * to be available to it on entry. It does not modify any callee-save
- * registers (including "lr"). It does not check what PL it is being
- * called at, so you'd better not call it other than at PL0.
- * The <atomic.h> wrapper assumes it only clobbers r20-r29, so if
- * it ever is necessary to use more registers, be aware.
- *
- * It does not use the stack, but since it might be re-interrupted by
- * a page fault which would assume the stack was valid, it does
- * save/restore the stack pointer and zero it out to make sure it gets reset.
- * Since we always keep interrupts disabled, the hypervisor won't
- * clobber our EX_CONTEXT_K_x registers, so we don't save/restore them
- * (other than to advance the PC on return).
- *
- * We have to manually validate the user vs kernel address range
- * (since at PL1 we can read/write both), and for performance reasons
- * we don't allow cmpxchg on the fc000000 memory region, since we only
- * validate that the user address is below PAGE_OFFSET.
- *
- * We place it in the __HEAD section to ensure it is relatively
- * near to the intvec_SWINT_1 code (reachable by a conditional branch).
- *
- * Our use of ATOMIC_LOCK_REG here must match do_page_fault_ics().
- *
- * As we do in lib/atomic_asm_32.S, we bypass a store if the value we
- * would store is the same as the value we just loaded.
- */
- __HEAD
- .align 64
- /* Align much later jump on the start of a cache line. */
- nop
-#if PAGE_SIZE >= 0x10000
- nop
-#endif
-ENTRY(sys_cmpxchg)
-
- /*
- * Save "sp" and set it zero for any possible page fault.
- *
- * HACK: We want to both zero sp and check r0's alignment,
- * so we do both at once. If "sp" becomes nonzero we
- * know r0 is unaligned and branch to the error handler that
- * restores sp, so this is OK.
- *
- * ICS is disabled right now so having a garbage but nonzero
- * sp is OK, since we won't execute any faulting instructions
- * when it is nonzero.
- */
- {
- move r27, sp
- andi sp, r0, 3
- }
-
- /*
- * Get the lock address in ATOMIC_LOCK_REG, and also validate that the
- * address is less than PAGE_OFFSET, since that won't trap at PL1.
- * We only use bits less than PAGE_SHIFT to avoid having to worry
- * about aliasing among multiple mappings of the same physical page,
- * and we ignore the low 3 bits so we have one lock that covers
- * both a cmpxchg64() and a cmpxchg() on either its low or high word.
- * NOTE: this must match __atomic_hashed_lock() in lib/atomic_32.c.
- */
-
-#if (PAGE_OFFSET & 0xffff) != 0
-# error Code here assumes PAGE_OFFSET can be loaded with just hi16()
-#endif
-
- {
- /* Check for unaligned input. */
- bnz sp, .Lcmpxchg_badaddr
- auli r23, zero, hi16(PAGE_OFFSET) /* hugepage-aligned */
- }
- {
- /*
- * Slide bits into position for 'mm'. We want to ignore
- * the low 3 bits of r0, and consider only the next
- * ATOMIC_HASH_SHIFT bits.
- * Because of C pointer arithmetic, we want to compute this:
- *
- * ((char*)atomic_locks +
- * (((r0 >> 3) & ((1 << ATOMIC_HASH_SHIFT) - 1)) << 2))
- *
- * Instead of two shifts we just ">> 1", and use 'mm'
- * to ignore the low and high bits we don't want.
- */
- shri r25, r0, 1
-
- slt_u r23, r0, r23
-
- /*
- * Ensure that the TLB is loaded before we take out the lock.
- * This will start fetching the value all the way into our L1
- * as well (and if it gets modified before we grab the lock,
- * it will be invalidated from our cache before we reload it).
- */
- lw r26, r0
- }
- {
- auli r21, zero, ha16(atomic_locks)
-
- bbns r23, .Lcmpxchg_badaddr
- }
-#if PAGE_SIZE < 0x10000
- /* atomic_locks is page-aligned so for big pages we don't need this. */
- addli r21, r21, lo16(atomic_locks)
-#endif
- {
- /*
- * Insert the hash bits into the page-aligned pointer.
- * ATOMIC_HASH_SHIFT is so big that we don't actually hash
- * the unmasked address bits, as that may cause unnecessary
- * collisions.
- */
- mm ATOMIC_LOCK_REG_NAME, r25, r21, 2, (ATOMIC_HASH_SHIFT + 2) - 1
-
- seqi r23, TREG_SYSCALL_NR_NAME, __NR_FAST_cmpxchg64
- }
- {
- /* Branch away at this point if we're doing a 64-bit cmpxchg. */
- bbs r23, .Lcmpxchg64
- andi r23, r0, 7 /* Precompute alignment for cmpxchg64. */
- }
- {
- /*
- * We very carefully align the code that actually runs with
- * the lock held (twelve bundles) so that we know it is all in
- * the icache when we start. This instruction (the jump) is
- * at the start of the first cache line, address zero mod 64;
- * we jump to the very end of the second cache line to get that
- * line loaded in the icache, then fall through to issue the tns
- * in the third cache line, at which point it's all cached.
- * Note that is for performance, not correctness.
- */
- j .Lcmpxchg32_tns
- }
-
-/* Symbol for do_page_fault_ics() to use to compare against the PC. */
-.global __sys_cmpxchg_grab_lock
-__sys_cmpxchg_grab_lock:
-
- /*
- * Perform the actual cmpxchg or atomic_update.
- */
-.Ldo_cmpxchg32:
- {
- lw r21, r0
- seqi r23, TREG_SYSCALL_NR_NAME, __NR_FAST_atomic_update
- move r24, r2
- }
- {
- seq r22, r21, r1 /* See if cmpxchg matches. */
- and r25, r21, r1 /* If atomic_update, compute (*mem & mask) */
- }
- {
- or r22, r22, r23 /* Skip compare branch for atomic_update. */
- add r25, r25, r2 /* Compute (*mem & mask) + addend. */
- }
- {
- mvnz r24, r23, r25 /* Use atomic_update value if appropriate. */
- bbns r22, .Lcmpxchg32_nostore
- }
- seq r22, r24, r21 /* Are we storing the value we loaded? */
- bbs r22, .Lcmpxchg32_nostore
- sw r0, r24
-
- /* The following instruction is the start of the second cache line. */
- /* Do slow mtspr here so the following "mf" waits less. */
- {
- move sp, r27
- mtspr SPR_EX_CONTEXT_K_0, r28
- }
- mf
-
- {
- move r0, r21
- sw ATOMIC_LOCK_REG_NAME, zero
- }
- iret
-
- /* Duplicated code here in the case where we don't overlap "mf" */
-.Lcmpxchg32_nostore:
- {
- move r0, r21
- sw ATOMIC_LOCK_REG_NAME, zero
- }
- {
- move sp, r27
- mtspr SPR_EX_CONTEXT_K_0, r28
- }
- iret
-
- /*
- * The locking code is the same for 32-bit cmpxchg/atomic_update,
- * and for 64-bit cmpxchg. We provide it as a macro and put
- * it into both versions. We can't share the code literally
- * since it depends on having the right branch-back address.
- */
- .macro cmpxchg_lock, bitwidth
-
- /* Lock; if we succeed, jump back up to the read-modify-write. */
-#ifdef CONFIG_SMP
- tns r21, ATOMIC_LOCK_REG_NAME
-#else
- /*
- * Non-SMP preserves all the lock infrastructure, to keep the
- * code simpler for the interesting (SMP) case. However, we do
- * one small optimization here and in atomic_asm.S, which is
- * to fake out acquiring the actual lock in the atomic_lock table.
- */
- movei r21, 0
-#endif
-
- /* Issue the slow SPR here while the tns result is in flight. */
- mfspr r28, SPR_EX_CONTEXT_K_0
-
- {
- addi r28, r28, 8 /* return to the instruction after the swint1 */
- bzt r21, .Ldo_cmpxchg\bitwidth
- }
- /*
- * The preceding instruction is the last thing that must be
- * hot in the icache before we do the "tns" above.
- */
-
-#ifdef CONFIG_SMP
- /*
- * We failed to acquire the tns lock on our first try. Now use
- * bounded exponential backoff to retry, like __atomic_spinlock().
- */
- {
- moveli r23, 2048 /* maximum backoff time in cycles */
- moveli r25, 32 /* starting backoff time in cycles */
- }
-1: mfspr r26, CYCLE_LOW /* get start point for this backoff */
-2: mfspr r22, CYCLE_LOW /* test to see if we've backed off enough */
- sub r22, r22, r26
- slt r22, r22, r25
- bbst r22, 2b
- {
- shli r25, r25, 1 /* double the backoff; retry the tns */
- tns r21, ATOMIC_LOCK_REG_NAME
- }
- slt r26, r23, r25 /* is the proposed backoff too big? */
- {
- mvnz r25, r26, r23
- bzt r21, .Ldo_cmpxchg\bitwidth
- }
- j 1b
-#endif /* CONFIG_SMP */
- .endm
-
-.Lcmpxchg32_tns:
- /*
- * This is the last instruction on the second cache line.
- * The nop here loads the second line, then we fall through
- * to the tns to load the third line before we take the lock.
- */
- nop
- cmpxchg_lock 32
-
- /*
- * This code is invoked from sys_cmpxchg after most of the
- * preconditions have been checked. We still need to check
- * that r0 is 8-byte aligned, since if it's not we won't
- * actually be atomic. However, ATOMIC_LOCK_REG has the atomic
- * lock pointer and r27/r28 have the saved SP/PC.
- * r23 is holding "r0 & 7" so we can test for alignment.
- * The compare value is in r2/r3; the new value is in r4/r5.
- * On return, we must put the old value in r0/r1.
- */
- .align 64
-.Lcmpxchg64:
- {
- bzt r23, .Lcmpxchg64_tns
- }
- j .Lcmpxchg_badaddr
-
-.Ldo_cmpxchg64:
- {
- lw r21, r0
- addi r25, r0, 4
- }
- {
- lw r1, r25
- }
- seq r26, r21, r2
- {
- bz r26, .Lcmpxchg64_mismatch
- seq r26, r1, r3
- }
- {
- bz r26, .Lcmpxchg64_mismatch
- }
- sw r0, r4
- sw r25, r5
-
- /*
- * The 32-bit path provides optimized "match" and "mismatch"
- * iret paths, but we don't have enough bundles in this cache line
- * to do that, so we just make even the "mismatch" path do an "mf".
- */
-.Lcmpxchg64_mismatch:
- {
- move sp, r27
- mtspr SPR_EX_CONTEXT_K_0, r28
- }
- mf
- {
- move r0, r21
- sw ATOMIC_LOCK_REG_NAME, zero
- }
- iret
-
-.Lcmpxchg64_tns:
- cmpxchg_lock 64
-
-
- /*
- * Reset sp and revector to sys_cmpxchg_badaddr(), which will
- * just raise the appropriate signal and exit. Doing it this
- * way means we don't have to duplicate the code in intvec.S's
- * int_hand macro that locates the top of the stack.
- */
-.Lcmpxchg_badaddr:
- {
- moveli TREG_SYSCALL_NR_NAME, __NR_cmpxchg_badaddr
- move sp, r27
- }
- j intvec_SWINT_1
- ENDPROC(sys_cmpxchg)
- ENTRY(__sys_cmpxchg_end)
-
-
-/* The single-step support may need to read all the registers. */
-int_unalign:
- push_extra_callee_saves r0
- j do_trap
-
-/* Include .intrpt array of interrupt vectors */
- .section ".intrpt", "ax"
-
-#ifndef CONFIG_USE_PMC
-#define handle_perf_interrupt bad_intr
-#endif
-
-#ifndef CONFIG_HARDWALL
-#define do_hardwall_trap bad_intr
-#endif
-
- int_hand INT_ITLB_MISS, ITLB_MISS, \
- do_page_fault, handle_interrupt_no_single_step
- int_hand INT_MEM_ERROR, MEM_ERROR, bad_intr
- int_hand INT_ILL, ILL, do_trap, handle_ill
- int_hand INT_GPV, GPV, do_trap
- int_hand INT_SN_ACCESS, SN_ACCESS, do_trap
- int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
- int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
- int_hand INT_IDN_REFILL, IDN_REFILL, bad_intr
- int_hand INT_UDN_REFILL, UDN_REFILL, bad_intr
- int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
- int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
- int_hand INT_SWINT_3, SWINT_3, do_trap
- int_hand INT_SWINT_2, SWINT_2, do_trap
- int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
- int_hand INT_SWINT_0, SWINT_0, do_trap
- int_hand INT_UNALIGN_DATA, UNALIGN_DATA, int_unalign
- int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
- int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
- int_hand INT_DMATLB_MISS, DMATLB_MISS, do_page_fault
- int_hand INT_DMATLB_ACCESS, DMATLB_ACCESS, do_page_fault
- int_hand INT_SNITLB_MISS, SNITLB_MISS, do_page_fault
- int_hand INT_SN_NOTIFY, SN_NOTIFY, bad_intr
- int_hand INT_SN_FIREWALL, SN_FIREWALL, do_hardwall_trap
- int_hand INT_IDN_FIREWALL, IDN_FIREWALL, bad_intr
- int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
- int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
- int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
- int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
- int_hand INT_DMA_NOTIFY, DMA_NOTIFY, bad_intr
- int_hand INT_IDN_CA, IDN_CA, bad_intr
- int_hand INT_UDN_CA, UDN_CA, bad_intr
- int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
- int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
- int_hand INT_PERF_COUNT, PERF_COUNT, \
- handle_perf_interrupt, handle_nmi
- int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
-#if CONFIG_KERNEL_PL == 2
- dc_dispatch INT_INTCTRL_2, INTCTRL_2
- int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
-#else
- int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
- dc_dispatch INT_INTCTRL_1, INTCTRL_1
-#endif
- int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
- int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
- hv_message_intr
- int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, \
- tile_dev_intr
- int_hand INT_I_ASID, I_ASID, bad_intr
- int_hand INT_D_ASID, D_ASID, bad_intr
- int_hand INT_DMATLB_MISS_DWNCL, DMATLB_MISS_DWNCL, \
- do_page_fault
- int_hand INT_SNITLB_MISS_DWNCL, SNITLB_MISS_DWNCL, \
- do_page_fault
- int_hand INT_DMATLB_ACCESS_DWNCL, DMATLB_ACCESS_DWNCL, \
- do_page_fault
- int_hand INT_SN_CPL, SN_CPL, bad_intr
- int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
- int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
- handle_perf_interrupt, handle_nmi
-
- /* Synthetic interrupt delivered only by the simulator */
- int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
deleted file mode 100644
index 3b51bdf37d11..000000000000
--- a/arch/tile/kernel/intvec_64.S
+++ /dev/null
@@ -1,1564 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Linux interrupt vectors.
- */
-
-#include <linux/linkage.h>
-#include <linux/errno.h>
-#include <linux/unistd.h>
-#include <linux/init.h>
-#include <asm/ptrace.h>
-#include <asm/thread_info.h>
-#include <asm/irqflags.h>
-#include <asm/asm-offsets.h>
-#include <asm/types.h>
-#include <asm/traps.h>
-#include <asm/signal.h>
-#include <hv/hypervisor.h>
-#include <arch/abi.h>
-#include <arch/interrupts.h>
-#include <arch/spr_def.h>
-
-#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
-
-#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
-
-#if CONFIG_KERNEL_PL == 1 || CONFIG_KERNEL_PL == 2
-/*
- * Set "result" non-zero if ex1 holds the PL of the kernel
- * (with or without ICS being set). Note this works only
- * because we never find the PL at level 3.
- */
-# define IS_KERNEL_EX1(result, ex1) andi result, ex1, CONFIG_KERNEL_PL
-#else
-# error Recode IS_KERNEL_EX1 for CONFIG_KERNEL_PL
-#endif
-
- .macro push_reg reg, ptr=sp, delta=-8
- {
- st \ptr, \reg
- addli \ptr, \ptr, \delta
- }
- .endm
-
- .macro pop_reg reg, ptr=sp, delta=8
- {
- ld \reg, \ptr
- addli \ptr, \ptr, \delta
- }
- .endm
-
- .macro pop_reg_zero reg, zreg, ptr=sp, delta=8
- {
- move \zreg, zero
- ld \reg, \ptr
- addi \ptr, \ptr, \delta
- }
- .endm
-
- .macro push_extra_callee_saves reg
- PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
- push_reg r51, \reg
- push_reg r50, \reg
- push_reg r49, \reg
- push_reg r48, \reg
- push_reg r47, \reg
- push_reg r46, \reg
- push_reg r45, \reg
- push_reg r44, \reg
- push_reg r43, \reg
- push_reg r42, \reg
- push_reg r41, \reg
- push_reg r40, \reg
- push_reg r39, \reg
- push_reg r38, \reg
- push_reg r37, \reg
- push_reg r36, \reg
- push_reg r35, \reg
- push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
- .endm
-
- .macro panic str
- .pushsection .rodata, "a"
-1:
- .asciz "\str"
- .popsection
- {
- moveli r0, hw2_last(1b)
- }
- {
- shl16insli r0, r0, hw1(1b)
- }
- {
- shl16insli r0, r0, hw0(1b)
- jal panic
- }
- .endm
-
- /*
- * Unalign data exception fast handling: In order to handle
- * unaligned data access, a fast JIT version is generated and stored
- * in a specific area in user space. We first need to do a quick poke
- * to see if the JIT is available. We use certain bits in the fault
- * PC (3 to 9 is used for 16KB page size) as index to address the JIT
- * code area. The first 64bit word is the fault PC, and the 2nd one is
- * the fault bundle itself. If these 2 words both match, then we
- * directly "iret" to JIT code. If not, a slow path is invoked to
- * generate new JIT code. Note: the current JIT code WILL be
- * overwritten if it existed. So, ideally we can handle 128 unalign
- * fixups via JIT. For lookup efficiency and to effectively support
- * tight loops with multiple unaligned reference, a simple
- * direct-mapped cache is used.
- *
- * SPR_EX_CONTEXT_K_0 is modified to return to JIT code.
- * SPR_EX_CONTEXT_K_1 has ICS set.
- * SPR_EX_CONTEXT_0_0 is setup to user program's next PC.
- * SPR_EX_CONTEXT_0_1 = 0.
- */
- .macro int_hand_unalign_fast vecnum, vecname
- .org (\vecnum << 8)
-intvec_\vecname:
- /* Put r3 in SPR_SYSTEM_SAVE_K_1. */
- mtspr SPR_SYSTEM_SAVE_K_1, r3
-
- mfspr r3, SPR_EX_CONTEXT_K_1
- /*
- * Examine if exception comes from user without ICS set.
- * If not, just go directly to the slow path.
- */
- bnez r3, hand_unalign_slow_nonuser
-
- mfspr r3, SPR_SYSTEM_SAVE_K_0
-
- /* Get &thread_info->unalign_jit_tmp[0] in r3. */
- bfexts r3, r3, 0, CPU_SHIFT-1
- mm r3, zero, LOG2_THREAD_SIZE, 63
- addli r3, r3, THREAD_INFO_UNALIGN_JIT_TMP_OFFSET
-
- /*
- * Save r0, r1, r2 into thread_info array r3 points to
- * from low to high memory in order.
- */
- st_add r3, r0, 8
- st_add r3, r1, 8
- {
- st_add r3, r2, 8
- andi r2, sp, 7
- }
-
- /* Save stored r3 value so we can revert it on a page fault. */
- mfspr r1, SPR_SYSTEM_SAVE_K_1
- st r3, r1
-
- {
- /* Generate a SIGBUS if sp is not 8-byte aligned. */
- bnez r2, hand_unalign_slow_badsp
- }
-
- /*
- * Get the thread_info in r0; load r1 with pc. Set the low bit of sp
- * as an indicator to the page fault code in case we fault.
- */
- {
- ori sp, sp, 1
- mfspr r1, SPR_EX_CONTEXT_K_0
- }
-
- /* Add the jit_info offset in thread_info; extract r1 [3:9] into r2. */
- {
- addli r0, r3, THREAD_INFO_UNALIGN_JIT_BASE_OFFSET - \
- (THREAD_INFO_UNALIGN_JIT_TMP_OFFSET + (3 * 8))
- bfextu r2, r1, 3, (2 + PAGE_SHIFT - UNALIGN_JIT_SHIFT)
- }
-
- /* Load the jit_info; multiply r2 by 128. */
- {
- ld r0, r0
- shli r2, r2, UNALIGN_JIT_SHIFT
- }
-
- /*
- * If r0 is NULL, the JIT page is not mapped, so go to slow path;
- * add offset r2 to r0 at the same time.
- */
- {
- beqz r0, hand_unalign_slow
- add r2, r0, r2
- }
-
- /*
- * We are loading from userspace (both the JIT info PC and
- * instruction word, and the instruction word we executed)
- * and since either could fault while holding the interrupt
- * critical section, we must tag this region and check it in
- * do_page_fault() to handle it properly.
- */
-ENTRY(__start_unalign_asm_code)
-
- /* Load first word of JIT in r0 and increment r2 by 8. */
- ld_add r0, r2, 8
-
- /*
- * Compare the PC with the 1st word in JIT; load the fault bundle
- * into r1.
- */
- {
- cmpeq r0, r0, r1
- ld r1, r1
- }
-
- /* Go to slow path if PC doesn't match. */
- beqz r0, hand_unalign_slow
-
- /*
- * Load the 2nd word of JIT, which is supposed to be the fault
- * bundle for a cache hit. Increment r2; after this bundle r2 will
- * point to the potential start of the JIT code we want to run.
- */
- ld_add r0, r2, 8
-
- /* No further accesses to userspace are done after this point. */
-ENTRY(__end_unalign_asm_code)
-
- /* Compare the real bundle with what is saved in the JIT area. */
- {
- cmpeq r0, r1, r0
- mtspr SPR_EX_CONTEXT_0_1, zero
- }
-
- /* Go to slow path if the fault bundle does not match. */
- beqz r0, hand_unalign_slow
-
- /*
- * A cache hit is found.
- * r2 points to start of JIT code (3rd word).
- * r0 is the fault pc.
- * r1 is the fault bundle.
- * Reset the low bit of sp.
- */
- {
- mfspr r0, SPR_EX_CONTEXT_K_0
- andi sp, sp, ~1
- }
-
- /* Write r2 into EX_CONTEXT_K_0 and increment PC. */
- {
- mtspr SPR_EX_CONTEXT_K_0, r2
- addi r0, r0, 8
- }
-
- /*
- * Set ICS on kernel EX_CONTEXT_K_1 in order to "iret" to
- * user with ICS set. This way, if the JIT fixup causes another
- * unalign exception (which shouldn't be possible) the user
- * process will be terminated with SIGBUS. Also, our fixup will
- * run without interleaving with external interrupts.
- * Each fixup is at most 14 bundles, so it won't hold ICS for long.
- */
- {
- movei r1, PL_ICS_EX1(USER_PL, 1)
- mtspr SPR_EX_CONTEXT_0_0, r0
- }
-
- {
- mtspr SPR_EX_CONTEXT_K_1, r1
- addi r3, r3, -(3 * 8)
- }
-
- /* Restore r0..r3. */
- ld_add r0, r3, 8
- ld_add r1, r3, 8
- ld_add r2, r3, 8
- ld r3, r3
-
- iret
- ENDPROC(intvec_\vecname)
- .endm
-
-#ifdef __COLLECT_LINKER_FEEDBACK__
- .pushsection .text.intvec_feedback,"ax"
-intvec_feedback:
- .popsection
-#endif
-
- /*
- * Default interrupt handler.
- *
- * vecnum is where we'll put this code.
- * c_routine is the C routine we'll call.
- *
- * The C routine is passed two arguments:
- * - A pointer to the pt_regs state.
- * - The interrupt vector number.
- *
- * The "processing" argument specifies the code for processing
- * the interrupt. Defaults to "handle_interrupt".
- */
- .macro __int_hand vecnum, vecname, c_routine,processing=handle_interrupt
-intvec_\vecname:
- /* Temporarily save a register so we have somewhere to work. */
-
- mtspr SPR_SYSTEM_SAVE_K_1, r0
- mfspr r0, SPR_EX_CONTEXT_K_1
-
- /*
- * The unalign data fastpath code sets the low bit in sp to
- * force us to reset it here on fault.
- */
- {
- blbs sp, 2f
- IS_KERNEL_EX1(r0, r0)
- }
-
- .ifc \vecnum, INT_DOUBLE_FAULT
- /*
- * For double-faults from user-space, fall through to the normal
- * register save and stack setup path. Otherwise, it's the
- * hypervisor giving us one last chance to dump diagnostics, and we
- * branch to the kernel_double_fault routine to do so.
- */
- beqz r0, 1f
- j _kernel_double_fault
-1:
- .else
- /*
- * If we're coming from user-space, then set sp to the top of
- * the kernel stack. Otherwise, assume sp is already valid.
- */
- {
- bnez r0, 0f
- move r0, sp
- }
- .endif
-
- .ifc \c_routine, do_page_fault
- /*
- * The page_fault handler may be downcalled directly by the
- * hypervisor even when Linux is running and has ICS set.
- *
- * In this case the contents of EX_CONTEXT_K_1 reflect the
- * previous fault and can't be relied on to choose whether or
- * not to reinitialize the stack pointer. So we add a test
- * to see whether SYSTEM_SAVE_K_2 has the high bit set,
- * and if so we don't reinitialize sp, since we must be coming
- * from Linux. (In fact the precise case is !(val & ~1),
- * but any Linux PC has to have the high bit set.)
- *
- * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
- * any path that turns into a downcall to one of our TLB handlers.
- *
- * FIXME: if we end up never using this path, perhaps we should
- * prevent the hypervisor from generating downcalls in this case.
- * The advantage of getting a downcall is we can panic in Linux.
- */
- mfspr r0, SPR_SYSTEM_SAVE_K_2
- {
- bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
- move r0, sp
- }
- .endif
-
-2:
- /*
- * SYSTEM_SAVE_K_0 holds the cpu number in the high bits, and
- * the current stack top in the lower bits. So we recover
- * our starting stack value by sign-extending the low bits, then
- * point sp at the top aligned address on the actual stack page.
- */
- mfspr r0, SPR_SYSTEM_SAVE_K_0
- bfexts r0, r0, 0, CPU_SHIFT-1
-
-0:
- /*
- * Align the stack mod 64 so we can properly predict what
- * cache lines we need to write-hint to reduce memory fetch
- * latency as we enter the kernel. The layout of memory is
- * as follows, with cache line 0 at the lowest VA, and cache
- * line 8 just below the r0 value this "andi" computes.
- * Note that we never write to cache line 8, and we skip
- * cache lines 1-3 for syscalls.
- *
- * cache line 8: ptregs padding (two words)
- * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
- * cache line 6: r46...r53 (tp)
- * cache line 5: r38...r45
- * cache line 4: r30...r37
- * cache line 3: r22...r29
- * cache line 2: r14...r21
- * cache line 1: r6...r13
- * cache line 0: 2 x frame, r0..r5
- */
-#if STACK_TOP_DELTA != 64
-#error STACK_TOP_DELTA must be 64 for assumptions here and in task_pt_regs()
-#endif
- andi r0, r0, -64
-
- /*
- * Push the first four registers on the stack, so that we can set
- * them to vector-unique values before we jump to the common code.
- *
- * Registers are pushed on the stack as a struct pt_regs,
- * with the sp initially just above the struct, and when we're
- * done, sp points to the base of the struct, minus
- * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
- *
- * This routine saves just the first four registers, plus the
- * stack context so we can do proper backtracing right away,
- * and defers to handle_interrupt to save the rest.
- * The backtracer needs pc, ex1, lr, sp, r52, and faultnum,
- * and needs sp set to its final location at the bottom of
- * the stack frame.
- */
- addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
- wh64 r0 /* cache line 7 */
- {
- st r0, lr
- addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
- }
- {
- st r0, sp
- addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
- }
- wh64 sp /* cache line 6 */
- {
- st sp, r52
- addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
- }
- wh64 sp /* cache line 0 */
- {
- st sp, r1
- addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
- }
- {
- st sp, r2
- addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
- }
- {
- st sp, r3
- addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
- }
- mfspr r0, SPR_EX_CONTEXT_K_0
- .ifc \processing,handle_syscall
- /*
- * Bump the saved PC by one bundle so that when we return, we won't
- * execute the same swint instruction again. We need to do this while
- * we're in the critical section.
- */
- addi r0, r0, 8
- .endif
- {
- st sp, r0
- addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
- }
- mfspr r0, SPR_EX_CONTEXT_K_1
- {
- st sp, r0
- addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
- /*
- * Use r0 for syscalls so it's a temporary; use r1 for interrupts
- * so that it gets passed through unchanged to the handler routine.
- * Note that the .if conditional confusingly spans bundles.
- */
- .ifc \processing,handle_syscall
- movei r0, \vecnum
- }
- {
- st sp, r0
- .else
- movei r1, \vecnum
- }
- {
- st sp, r1
- .endif
- addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
- }
- mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
- {
- st sp, r0
- addi sp, sp, -PTREGS_OFFSET_REG(0) - 8
- }
- {
- st sp, zero /* write zero into "Next SP" frame pointer */
- addi sp, sp, -8 /* leave SP pointing at bottom of frame */
- }
- .ifc \processing,handle_syscall
- j handle_syscall
- .else
- /* Capture per-interrupt SPR context to registers. */
- .ifc \c_routine, do_page_fault
- mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
- mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
- .else
- .ifc \vecnum, INT_ILL_TRANS
- mfspr r2, ILL_VA_PC
- .else
- .ifc \vecnum, INT_DOUBLE_FAULT
- mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
- .else
- .ifc \c_routine, do_trap
- mfspr r2, GPV_REASON
- .else
- .ifc \c_routine, handle_perf_interrupt
- mfspr r2, PERF_COUNT_STS
- .else
- .ifc \c_routine, handle_perf_interrupt
- mfspr r2, AUX_PERF_COUNT_STS
- .endif
- .ifc \c_routine, do_nmi
- mfspr r2, SPR_SYSTEM_SAVE_K_2 /* nmi type */
- .else
- .endif
- .endif
- .endif
- .endif
- .endif
- .endif
- /* Put function pointer in r0 */
- moveli r0, hw2_last(\c_routine)
- shl16insli r0, r0, hw1(\c_routine)
- {
- shl16insli r0, r0, hw0(\c_routine)
- j \processing
- }
- .endif
- ENDPROC(intvec_\vecname)
-
-#ifdef __COLLECT_LINKER_FEEDBACK__
- .pushsection .text.intvec_feedback,"ax"
- .org (\vecnum << 5)
- FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt, 1 << 8)
- jrp lr
- .popsection
-#endif
-
- .endm
-
-
- /*
- * Save the rest of the registers that we didn't save in the actual
- * vector itself. We can't use r0-r10 inclusive here.
- */
- .macro finish_interrupt_save, function
-
- /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
- PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
- {
- .ifc \function,handle_syscall
- st r52, r0
- .else
- st r52, zero
- .endif
- PTREGS_PTR(r52, PTREGS_OFFSET_TP)
- }
- st r52, tp
- {
- mfspr tp, CMPEXCH_VALUE
- PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
- }
-
- /*
- * For ordinary syscalls, we save neither caller- nor callee-
- * save registers, since the syscall invoker doesn't expect the
- * caller-saves to be saved, and the called kernel functions will
- * take care of saving the callee-saves for us.
- *
- * For interrupts we save just the caller-save registers. Saving
- * them is required (since the "caller" can't save them). Again,
- * the called kernel functions will restore the callee-save
- * registers for us appropriately.
- *
- * On return, we normally restore nothing special for syscalls,
- * and just the caller-save registers for interrupts.
- *
- * However, there are some important caveats to all this:
- *
- * - We always save a few callee-save registers to give us
- * some scratchpad registers to carry across function calls.
- *
- * - fork/vfork/etc require us to save all the callee-save
- * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
- *
- * - We always save r0..r5 and r10 for syscalls, since we need
- * to reload them a bit later for the actual kernel call, and
- * since we might need them for -ERESTARTNOINTR, etc.
- *
- * - Before invoking a signal handler, we save the unsaved
- * callee-save registers so they are visible to the
- * signal handler or any ptracer.
- *
- * - If the unsaved callee-save registers are modified, we set
- * a bit in pt_regs so we know to reload them from pt_regs
- * and not just rely on the kernel function unwinding.
- * (Done for ptrace register writes and SA_SIGINFO handler.)
- */
- {
- st r52, tp
- PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
- }
- wh64 r52 /* cache line 4 */
- push_reg r33, r52
- push_reg r32, r52
- push_reg r31, r52
- .ifc \function,handle_syscall
- push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
- push_reg TREG_SYSCALL_NR_NAME, r52, \
- PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
- .else
-
- push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
- wh64 r52 /* cache line 3 */
- push_reg r29, r52
- push_reg r28, r52
- push_reg r27, r52
- push_reg r26, r52
- push_reg r25, r52
- push_reg r24, r52
- push_reg r23, r52
- push_reg r22, r52
- wh64 r52 /* cache line 2 */
- push_reg r21, r52
- push_reg r20, r52
- push_reg r19, r52
- push_reg r18, r52
- push_reg r17, r52
- push_reg r16, r52
- push_reg r15, r52
- push_reg r14, r52
- wh64 r52 /* cache line 1 */
- push_reg r13, r52
- push_reg r12, r52
- push_reg r11, r52
- push_reg r10, r52
- push_reg r9, r52
- push_reg r8, r52
- push_reg r7, r52
- push_reg r6, r52
-
- .endif
-
- push_reg r5, r52
- st r52, r4
-
- /*
- * If we will be returning to the kernel, we will need to
- * reset the interrupt masks to the state they had before.
- * Set DISABLE_IRQ in flags iff we came from kernel pl with
- * irqs disabled.
- */
- mfspr r32, SPR_EX_CONTEXT_K_1
- {
- IS_KERNEL_EX1(r32, r32)
- PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
- }
- beqzt r32, 1f /* zero if from user space */
- IRQS_DISABLED(r32) /* zero if irqs enabled */
-#if PT_FLAGS_DISABLE_IRQ != 1
-# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
-#endif
-1:
- .ifnc \function,handle_syscall
- /* Record the fact that we saved the caller-save registers above. */
- ori r32, r32, PT_FLAGS_CALLER_SAVES
- .endif
- st r21, r32
-
- /*
- * we've captured enough state to the stack (including in
- * particular our EX_CONTEXT state) that we can now release
- * the interrupt critical section and replace it with our
- * standard "interrupts disabled" mask value. This allows
- * synchronous interrupts (and profile interrupts) to punch
- * through from this point onwards.
- *
- * It's important that no code before this point touch memory
- * other than our own stack (to keep the invariant that this
- * is all that gets touched under ICS), and that no code after
- * this point reference any interrupt-specific SPR, in particular
- * the EX_CONTEXT_K_ values.
- */
- .ifc \function,handle_nmi
- IRQ_DISABLE_ALL(r20)
- .else
- IRQ_DISABLE(r20, r21)
- .endif
- mtspr INTERRUPT_CRITICAL_SECTION, zero
-
- /* Load tp with our per-cpu offset. */
-#ifdef CONFIG_SMP
- {
- mfspr r20, SPR_SYSTEM_SAVE_K_0
- moveli r21, hw2_last(__per_cpu_offset)
- }
- {
- shl16insli r21, r21, hw1(__per_cpu_offset)
- bfextu r20, r20, CPU_SHIFT, 63
- }
- shl16insli r21, r21, hw0(__per_cpu_offset)
- shl3add r20, r20, r21
- ld tp, r20
-#else
- move tp, zero
-#endif
-
-#ifdef __COLLECT_LINKER_FEEDBACK__
- /*
- * Notify the feedback routines that we were in the
- * appropriate fixed interrupt vector area. Note that we
- * still have ICS set at this point, so we can't invoke any
- * atomic operations or we will panic. The feedback
- * routines internally preserve r0..r10 and r30 up.
- */
- .ifnc \function,handle_syscall
- shli r20, r1, 5
- .else
- moveli r20, INT_SWINT_1 << 5
- .endif
- moveli r21, hw2_last(intvec_feedback)
- shl16insli r21, r21, hw1(intvec_feedback)
- shl16insli r21, r21, hw0(intvec_feedback)
- add r20, r20, r21
- jalr r20
-
- /* And now notify the feedback routines that we are here. */
- FEEDBACK_ENTER(\function)
-#endif
-
- /*
- * Prepare the first 256 stack bytes to be rapidly accessible
- * without having to fetch the background data.
- */
- addi r52, sp, -64
- {
- wh64 r52
- addi r52, r52, -64
- }
- {
- wh64 r52
- addi r52, r52, -64
- }
- {
- wh64 r52
- addi r52, r52, -64
- }
- wh64 r52
-
-#if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
- .ifnc \function,handle_nmi
- /*
- * We finally have enough state set up to notify the irq
- * tracing code that irqs were disabled on entry to the handler.
- * The TRACE_IRQS_OFF call clobbers registers r0-r29.
- * For syscalls, we already have the register state saved away
- * on the stack, so we don't bother to do any register saves here,
- * and later we pop the registers back off the kernel stack.
- * For interrupt handlers, save r0-r3 in callee-saved registers.
- */
- .ifnc \function,handle_syscall
- { move r30, r0; move r31, r1 }
- { move r32, r2; move r33, r3 }
- .endif
- TRACE_IRQS_OFF
-#ifdef CONFIG_CONTEXT_TRACKING
- jal context_tracking_user_exit
-#endif
- .ifnc \function,handle_syscall
- { move r0, r30; move r1, r31 }
- { move r2, r32; move r3, r33 }
- .endif
- .endif
-#endif
-
- .endm
-
- /*
- * Redispatch a downcall.
- */
- .macro dc_dispatch vecnum, vecname
- .org (\vecnum << 8)
-intvec_\vecname:
- j _hv_downcall_dispatch
- ENDPROC(intvec_\vecname)
- .endm
-
- /*
- * Common code for most interrupts. The C function we're eventually
- * going to is in r0, and the faultnum is in r1; the original
- * values for those registers are on the stack.
- */
- .pushsection .text.handle_interrupt,"ax"
-handle_interrupt:
- finish_interrupt_save handle_interrupt
-
- /* Jump to the C routine; it should enable irqs as soon as possible. */
- {
- jalr r0
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- }
- FEEDBACK_REENTER(handle_interrupt)
- {
- movei r30, 0 /* not an NMI */
- j interrupt_return
- }
- STD_ENDPROC(handle_interrupt)
-
-/*
- * This routine takes a boolean in r30 indicating if this is an NMI.
- * If so, we also expect a boolean in r31 indicating whether to
- * re-enable the oprofile interrupts.
- *
- * Note that .Lresume_userspace is jumped to directly in several
- * places, and we need to make sure r30 is set correctly in those
- * callers as well.
- */
-STD_ENTRY(interrupt_return)
- /* If we're resuming to kernel space, don't check thread flags. */
- {
- bnez r30, .Lrestore_all /* NMIs don't special-case user-space */
- PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
- }
- ld r29, r29
- IS_KERNEL_EX1(r29, r29)
- {
- beqzt r29, .Lresume_userspace
- move r29, sp
- }
-
-#ifdef CONFIG_PREEMPT
- /* Returning to kernel space. Check if we need preemption. */
- EXTRACT_THREAD_INFO(r29)
- addli r28, r29, THREAD_INFO_FLAGS_OFFSET
- {
- ld r28, r28
- addli r29, r29, THREAD_INFO_PREEMPT_COUNT_OFFSET
- }
- {
- andi r28, r28, _TIF_NEED_RESCHED
- ld4s r29, r29
- }
- beqzt r28, 1f
- bnez r29, 1f
- /* Disable interrupts explicitly for preemption. */
- IRQ_DISABLE(r20,r21)
- TRACE_IRQS_OFF
- jal preempt_schedule_irq
- FEEDBACK_REENTER(interrupt_return)
-1:
-#endif
-
- /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
- {
- moveli r27, hw2_last(_cpu_idle_nap)
- PTREGS_PTR(r29, PTREGS_OFFSET_PC)
- }
- {
- ld r28, r29
- shl16insli r27, r27, hw1(_cpu_idle_nap)
- }
- {
- shl16insli r27, r27, hw0(_cpu_idle_nap)
- }
- {
- cmpeq r27, r27, r28
- }
- {
- blbc r27, .Lrestore_all
- addi r28, r28, 8
- }
- st r29, r28
- j .Lrestore_all
-
-.Lresume_userspace:
- FEEDBACK_REENTER(interrupt_return)
-
- /*
- * Disable interrupts so as to make sure we don't
- * miss an interrupt that sets any of the thread flags (like
- * need_resched or sigpending) between sampling and the iret.
- * Routines like schedule() or do_signal() may re-enable
- * interrupts before returning.
- */
- IRQ_DISABLE(r20, r21)
- TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
-
- /*
- * See if there are any work items (including single-shot items)
- * to do. If so, save the callee-save registers to pt_regs
- * and then dispatch to C code.
- */
- move r21, sp
- EXTRACT_THREAD_INFO(r21)
- {
- addi r22, r21, THREAD_INFO_FLAGS_OFFSET
- moveli r20, hw1_last(_TIF_ALLWORK_MASK)
- }
- {
- ld r22, r22
- shl16insli r20, r20, hw0(_TIF_ALLWORK_MASK)
- }
- and r1, r22, r20
- {
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- beqzt r1, .Lrestore_all
- }
- push_extra_callee_saves r0
- jal prepare_exit_to_usermode
-
- /*
- * In the NMI case we
- * omit the call to single_process_check_nohz, which normally checks
- * to see if we should start or stop the scheduler tick, because
- * we can't call arbitrary Linux code from an NMI context.
- * We always call the homecache TLB deferral code to re-trigger
- * the deferral mechanism.
- *
- * The other chunk of responsibility this code has is to reset the
- * interrupt masks appropriately to reset irqs and NMIs. We have
- * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
- * lockdep-type stuff, but we can't set ICS until afterwards, since
- * ICS can only be used in very tight chunks of code to avoid
- * tripping over various assertions that it is off.
- */
-.Lrestore_all:
- PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
- {
- ld r0, r0
- PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
- }
- {
- IS_KERNEL_EX1(r0, r0)
- ld r32, r32
- }
- bnez r0, 1f
- j 2f
-#if PT_FLAGS_DISABLE_IRQ != 1
-# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
-#endif
-1: blbct r32, 2f
- IRQ_DISABLE(r20,r21)
- TRACE_IRQS_OFF
- movei r0, 1
- mtspr INTERRUPT_CRITICAL_SECTION, r0
- beqzt r30, .Lrestore_regs
- j 3f
-2: TRACE_IRQS_ON
- IRQ_ENABLE_LOAD(r20, r21)
- movei r0, 1
- mtspr INTERRUPT_CRITICAL_SECTION, r0
- IRQ_ENABLE_APPLY(r20, r21)
- beqzt r30, .Lrestore_regs
-3:
-
-#if INT_PERF_COUNT + 1 != INT_AUX_PERF_COUNT
-# error Bad interrupt assumption
-#endif
- {
- movei r0, 3 /* two adjacent bits for the PERF_COUNT mask */
- beqz r31, .Lrestore_regs
- }
- shli r0, r0, INT_PERF_COUNT
- mtspr SPR_INTERRUPT_MASK_RESET_K, r0
-
- /*
- * We now commit to returning from this interrupt, since we will be
- * doing things like setting EX_CONTEXT SPRs and unwinding the stack
- * frame. No calls should be made to any other code after this point.
- * This code should only be entered with ICS set.
- * r32 must still be set to ptregs.flags.
- * We launch loads to each cache line separately first, so we can
- * get some parallelism out of the memory subsystem.
- * We start zeroing caller-saved registers throughout, since
- * that will save some cycles if this turns out to be a syscall.
- */
-.Lrestore_regs:
-
- /*
- * Rotate so we have one high bit and one low bit to test.
- * - low bit says whether to restore all the callee-saved registers,
- * or just r30-r33, and r52 up.
- * - high bit (i.e. sign bit) says whether to restore all the
- * caller-saved registers, or just r0.
- */
-#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
-# error Rotate trick does not work :-)
-#endif
- {
- rotli r20, r32, 62
- PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
- }
-
- /*
- * Load cache lines 0, 4, 6 and 7, in that order, then use
- * the last loaded value, which makes it likely that the other
- * cache lines have also loaded, at which point we should be
- * able to safely read all the remaining words on those cache
- * lines without waiting for the memory subsystem.
- */
- pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
- pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
- pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
- pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
- pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
- {
- mtspr CMPEXCH_VALUE, r21
- move r4, zero
- }
- pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
- {
- mtspr SPR_EX_CONTEXT_K_1, lr
- IS_KERNEL_EX1(lr, lr)
- }
- {
- mtspr SPR_EX_CONTEXT_K_0, r21
- move r5, zero
- }
-
- /* Restore callee-saveds that we actually use. */
- pop_reg_zero r31, r6
- pop_reg_zero r32, r7
- pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
-
- /*
- * If we modified other callee-saveds, restore them now.
- * This is rare, but could be via ptrace or signal handler.
- */
- {
- move r9, zero
- blbs r20, .Lrestore_callees
- }
-.Lcontinue_restore_regs:
-
- /* Check if we're returning from a syscall. */
- {
- move r10, zero
- bltzt r20, 1f /* no, so go restore callee-save registers */
- }
-
- /*
- * Check if we're returning to userspace.
- * Note that if we're not, we don't worry about zeroing everything.
- */
- {
- addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
- bnez lr, .Lkernel_return
- }
-
- /*
- * On return from syscall, we've restored r0 from pt_regs, but we
- * clear the remainder of the caller-saved registers. We could
- * restore the syscall arguments, but there's not much point,
- * and it ensures user programs aren't trying to use the
- * caller-saves if we clear them, as well as avoiding leaking
- * kernel pointers into userspace.
- */
- pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
- pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
- {
- ld sp, sp
- move r13, zero
- move r14, zero
- }
- { move r15, zero; move r16, zero }
- { move r17, zero; move r18, zero }
- { move r19, zero; move r20, zero }
- { move r21, zero; move r22, zero }
- { move r23, zero; move r24, zero }
- { move r25, zero; move r26, zero }
-
- /* Set r1 to errno if we are returning an error, otherwise zero. */
- {
- moveli r29, 4096
- sub r1, zero, r0
- }
- {
- move r28, zero
- cmpltu r29, r1, r29
- }
- {
- mnz r1, r29, r1
- move r29, zero
- }
- iret
-
- /*
- * Not a syscall, so restore caller-saved registers.
- * First kick off loads for cache lines 1-3, which we're touching
- * for the first time here.
- */
- .align 64
-1: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
- pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
- pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
- pop_reg r1
- pop_reg r2
- pop_reg r3
- pop_reg r4
- pop_reg r5
- pop_reg r6
- pop_reg r7
- pop_reg r8
- pop_reg r9
- pop_reg r10
- pop_reg r11
- pop_reg r12, sp, 16
- /* r13 already restored above */
- pop_reg r14
- pop_reg r15
- pop_reg r16
- pop_reg r17
- pop_reg r18
- pop_reg r19
- pop_reg r20, sp, 16
- /* r21 already restored above */
- pop_reg r22
- pop_reg r23
- pop_reg r24
- pop_reg r25
- pop_reg r26
- pop_reg r27
- pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
- /* r29 already restored above */
- bnez lr, .Lkernel_return
- pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
- pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
- ld sp, sp
- iret
-
- /*
- * We can't restore tp when in kernel mode, since a thread might
- * have migrated from another cpu and brought a stale tp value.
- */
-.Lkernel_return:
- pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
- ld sp, sp
- iret
-
- /* Restore callee-saved registers from r34 to r51. */
-.Lrestore_callees:
- addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
- pop_reg r34
- pop_reg r35
- pop_reg r36
- pop_reg r37
- pop_reg r38
- pop_reg r39
- pop_reg r40
- pop_reg r41
- pop_reg r42
- pop_reg r43
- pop_reg r44
- pop_reg r45
- pop_reg r46
- pop_reg r47
- pop_reg r48
- pop_reg r49
- pop_reg r50
- pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
- j .Lcontinue_restore_regs
- STD_ENDPROC(interrupt_return)
-
- /*
- * "NMI" interrupts mask ALL interrupts before calling the
- * handler, and don't check thread flags, etc., on the way
- * back out. In general, the only things we do here for NMIs
- * are register save/restore and dataplane kernel-TLB management.
- * We don't (for example) deal with start/stop of the sched tick.
- */
- .pushsection .text.handle_nmi,"ax"
-handle_nmi:
- finish_interrupt_save handle_nmi
- {
- jalr r0
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- }
- FEEDBACK_REENTER(handle_nmi)
- {
- movei r30, 1
- cmpeq r31, r0, zero
- }
- j interrupt_return
- STD_ENDPROC(handle_nmi)
-
- /*
- * Parallel code for syscalls to handle_interrupt.
- */
- .pushsection .text.handle_syscall,"ax"
-handle_syscall:
- finish_interrupt_save handle_syscall
-
- /* Enable irqs. */
- TRACE_IRQS_ON
- IRQ_ENABLE(r20, r21)
-
- /* Bump the counter for syscalls made on this tile. */
- moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
- shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
- shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
- add r20, r20, tp
- ld4s r21, r20
- {
- addi r21, r21, 1
- move r31, sp
- }
- {
- st4 r20, r21
- EXTRACT_THREAD_INFO(r31)
- }
-
- /* Trace syscalls, if requested. */
- addi r31, r31, THREAD_INFO_FLAGS_OFFSET
- {
- ld r30, r31
- moveli r32, _TIF_SYSCALL_ENTRY_WORK
- }
- and r30, r30, r32
- {
- addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
- beqzt r30, .Lrestore_syscall_regs
- }
- {
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- jal do_syscall_trace_enter
- }
- FEEDBACK_REENTER(handle_syscall)
- bltz r0, .Lsyscall_sigreturn_skip
-
- /*
- * We always reload our registers from the stack at this
- * point. They might be valid, if we didn't build with
- * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
- * doing syscall tracing, but there are enough cases now that it
- * seems simplest just to do the reload unconditionally.
- */
-.Lrestore_syscall_regs:
- {
- ld r30, r30
- PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
- }
- pop_reg r0, r11
- pop_reg r1, r11
- pop_reg r2, r11
- pop_reg r3, r11
- pop_reg r4, r11
- pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
- {
- ld TREG_SYSCALL_NR_NAME, r11
- moveli r21, __NR_syscalls
- }
-
- /* Ensure that the syscall number is within the legal range. */
- {
- moveli r20, hw2(sys_call_table)
-#ifdef CONFIG_COMPAT
- blbs r30, .Lcompat_syscall
-#endif
- }
- {
- cmpltu r21, TREG_SYSCALL_NR_NAME, r21
- shl16insli r20, r20, hw1(sys_call_table)
- }
- {
- blbc r21, .Linvalid_syscall
- shl16insli r20, r20, hw0(sys_call_table)
- }
-.Lload_syscall_pointer:
- shl3add r20, TREG_SYSCALL_NR_NAME, r20
- ld r20, r20
-
- /* Jump to syscall handler. */
- jalr r20
-.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
-
- /*
- * Write our r0 onto the stack so it gets restored instead
- * of whatever the user had there before.
- * In compat mode, sign-extend r0 before storing it.
- */
- {
- PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
- blbct r30, 1f
- }
- addxi r0, r0, 0
-1: st r29, r0
-
-.Lsyscall_sigreturn_skip:
- FEEDBACK_REENTER(handle_syscall)
-
- /* Do syscall trace again, if requested. */
- {
- ld r30, r31
- moveli r32, _TIF_SYSCALL_EXIT_WORK
- }
- and r0, r30, r32
- {
- andi r0, r30, _TIF_SINGLESTEP
- beqzt r0, 1f
- }
- {
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- jal do_syscall_trace_exit
- }
- FEEDBACK_REENTER(handle_syscall)
- andi r0, r30, _TIF_SINGLESTEP
-
-1: beqzt r0, 2f
-
- /* Single stepping -- notify ptrace. */
- {
- movei r0, SIGTRAP
- jal ptrace_notify
- }
- FEEDBACK_REENTER(handle_syscall)
-
-2: {
- movei r30, 0 /* not an NMI */
- j .Lresume_userspace /* jump into middle of interrupt_return */
- }
-
-#ifdef CONFIG_COMPAT
-.Lcompat_syscall:
- /*
- * Load the base of the compat syscall table in r20, and
- * range-check the syscall number (duplicated from 64-bit path).
- * Sign-extend all the user's passed arguments to make them consistent.
- * Also save the original "r(n)" values away in "r(11+n)" in
- * case the syscall table entry wants to validate them.
- */
- moveli r20, hw2(compat_sys_call_table)
- {
- cmpltu r21, TREG_SYSCALL_NR_NAME, r21
- shl16insli r20, r20, hw1(compat_sys_call_table)
- }
- {
- blbc r21, .Linvalid_syscall
- shl16insli r20, r20, hw0(compat_sys_call_table)
- }
- { move r11, r0; addxi r0, r0, 0 }
- { move r12, r1; addxi r1, r1, 0 }
- { move r13, r2; addxi r2, r2, 0 }
- { move r14, r3; addxi r3, r3, 0 }
- { move r15, r4; addxi r4, r4, 0 }
- { move r16, r5; addxi r5, r5, 0 }
- j .Lload_syscall_pointer
-#endif
-
-.Linvalid_syscall:
- /* Report an invalid syscall back to the user program */
- {
- PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
- movei r28, -ENOSYS
- }
- st r29, r28
- {
- movei r30, 0 /* not an NMI */
- j .Lresume_userspace /* jump into middle of interrupt_return */
- }
- STD_ENDPROC(handle_syscall)
-
- /* Return the address for oprofile to suppress in backtraces. */
-STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
- lnk r0
- {
- addli r0, r0, .Lhandle_syscall_link - .
- jrp lr
- }
- STD_ENDPROC(handle_syscall_link_address)
-
-STD_ENTRY(ret_from_fork)
- jal sim_notify_fork
- jal schedule_tail
- FEEDBACK_REENTER(ret_from_fork)
- {
- movei r30, 0 /* not an NMI */
- j .Lresume_userspace /* jump into middle of interrupt_return */
- }
- STD_ENDPROC(ret_from_fork)
-
-STD_ENTRY(ret_from_kernel_thread)
- jal sim_notify_fork
- jal schedule_tail
- FEEDBACK_REENTER(ret_from_fork)
- {
- move r0, r31
- jalr r30
- }
- FEEDBACK_REENTER(ret_from_kernel_thread)
- {
- movei r30, 0 /* not an NMI */
- j interrupt_return
- }
- STD_ENDPROC(ret_from_kernel_thread)
-
-/* Various stub interrupt handlers and syscall handlers */
-
-STD_ENTRY_LOCAL(_kernel_double_fault)
- mfspr r1, SPR_EX_CONTEXT_K_0
- move r2, lr
- move r3, sp
- move r4, r52
- addi sp, sp, -C_ABI_SAVE_AREA_SIZE
- j kernel_double_fault
- STD_ENDPROC(_kernel_double_fault)
-
-STD_ENTRY_LOCAL(bad_intr)
- mfspr r2, SPR_EX_CONTEXT_K_0
- panic "Unhandled interrupt %#x: PC %#lx"
- STD_ENDPROC(bad_intr)
-
-/*
- * Special-case sigreturn to not write r0 to the stack on return.
- * This is technically more efficient, but it also avoids difficulties
- * in the 64-bit OS when handling 32-bit compat code, since we must not
- * sign-extend r0 for the sigreturn return-value case.
- */
-#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
- STD_ENTRY(_##x); \
- addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
- { \
- PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
- j x \
- }; \
- STD_ENDPROC(_##x)
-
-PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
-#ifdef CONFIG_COMPAT
-PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
-#endif
-
-/* Save additional callee-saves to pt_regs and jump to standard function. */
-STD_ENTRY(_sys_clone)
- push_extra_callee_saves r4
- j sys_clone
- STD_ENDPROC(_sys_clone)
-
- /*
- * Recover r3, r2, r1 and r0 here saved by unalign fast vector.
- * The vector area limit is 32 bundles, so we handle the reload here.
- * r0, r1, r2 are in thread_info from low to high memory in order.
- * r3 points to location the original r3 was saved.
- * We put this code in the __HEAD section so it can be reached
- * via a conditional branch from the fast path.
- */
- __HEAD
-hand_unalign_slow:
- andi sp, sp, ~1
-hand_unalign_slow_badsp:
- addi r3, r3, -(3 * 8)
- ld_add r0, r3, 8
- ld_add r1, r3, 8
- ld r2, r3
-hand_unalign_slow_nonuser:
- mfspr r3, SPR_SYSTEM_SAVE_K_1
- __int_hand INT_UNALIGN_DATA, UNALIGN_DATA_SLOW, int_unalign
-
-/* The unaligned data support needs to read all the registers. */
-int_unalign:
- push_extra_callee_saves r0
- j do_unaligned
-ENDPROC(hand_unalign_slow)
-
-/* Fill the return address stack with nonzero entries. */
-STD_ENTRY(fill_ra_stack)
- {
- move r0, lr
- jal 1f
- }
-1: jal 2f
-2: jal 3f
-3: jal 4f
-4: jrp r0
- STD_ENDPROC(fill_ra_stack)
-
- .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
- .org (\vecnum << 8)
- __int_hand \vecnum, \vecname, \c_routine, \processing
- .endm
-
-/* Include .intrpt array of interrupt vectors */
- .section ".intrpt", "ax"
- .global intrpt_start
-intrpt_start:
-
-#ifndef CONFIG_USE_PMC
-#define handle_perf_interrupt bad_intr
-#endif
-
-#ifndef CONFIG_HARDWALL
-#define do_hardwall_trap bad_intr
-#endif
-
- int_hand INT_MEM_ERROR, MEM_ERROR, do_trap
- int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
-#if CONFIG_KERNEL_PL == 2
- int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
- int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
-#else
- int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
- int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
-#endif
- int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
- int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
- int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
- int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault
- int_hand INT_ILL, ILL, do_trap
- int_hand INT_GPV, GPV, do_trap
- int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
- int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
- int_hand INT_SWINT_3, SWINT_3, do_trap
- int_hand INT_SWINT_2, SWINT_2, do_trap
- int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
- int_hand INT_SWINT_0, SWINT_0, do_trap
- int_hand INT_ILL_TRANS, ILL_TRANS, do_trap
- int_hand_unalign_fast INT_UNALIGN_DATA, UNALIGN_DATA
- int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
- int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
- int_hand INT_IDN_FIREWALL, IDN_FIREWALL, do_hardwall_trap
- int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
- int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
- int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
- int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
- int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
- int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
- int_hand INT_IPI_3, IPI_3, bad_intr
-#if CONFIG_KERNEL_PL == 2
- int_hand INT_IPI_2, IPI_2, tile_dev_intr
- int_hand INT_IPI_1, IPI_1, bad_intr
-#else
- int_hand INT_IPI_2, IPI_2, bad_intr
- int_hand INT_IPI_1, IPI_1, tile_dev_intr
-#endif
- int_hand INT_IPI_0, IPI_0, bad_intr
- int_hand INT_PERF_COUNT, PERF_COUNT, \
- handle_perf_interrupt, handle_nmi
- int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
- handle_perf_interrupt, handle_nmi
- int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
-#if CONFIG_KERNEL_PL == 2
- dc_dispatch INT_INTCTRL_2, INTCTRL_2
- int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
-#else
- int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
- dc_dispatch INT_INTCTRL_1, INTCTRL_1
-#endif
- int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
- int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
- hv_message_intr
- int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
- int_hand INT_I_ASID, I_ASID, bad_intr
- int_hand INT_D_ASID, D_ASID, bad_intr
- int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
-
- /* Synthetic interrupt delivered only by the simulator */
- int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint
- /* Synthetic interrupt delivered by hv */
- int_hand INT_NMI_DWNCL, NMI_DWNCL, do_nmi, handle_nmi
diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c
deleted file mode 100644
index 22044fc691ef..000000000000
--- a/arch/tile/kernel/irq.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/seq_file.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/uaccess.h>
-#include <hv/drv_pcie_rc_intf.h>
-#include <arch/spr_def.h>
-#include <asm/traps.h>
-#include <linux/perf_event.h>
-
-/* Bit-flag stored in irq_desc->chip_data to indicate HW-cleared irqs. */
-#define IS_HW_CLEARED 1
-
-/*
- * The set of interrupts we enable for arch_local_irq_enable().
- * This is initialized to have just a single interrupt that the kernel
- * doesn't actually use as a sentinel. During kernel init,
- * interrupts are added as the kernel gets prepared to support them.
- * NOTE: we could probably initialize them all statically up front.
- */
-DEFINE_PER_CPU(unsigned long long, interrupts_enabled_mask) =
- INITIAL_INTERRUPTS_ENABLED;
-EXPORT_PER_CPU_SYMBOL(interrupts_enabled_mask);
-
-/* Define per-tile device interrupt statistics state. */
-DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
-EXPORT_PER_CPU_SYMBOL(irq_stat);
-
-/*
- * Define per-tile irq disable mask; the hardware/HV only has a single
- * mask that we use to implement both masking and disabling.
- */
-static DEFINE_PER_CPU(unsigned long, irq_disable_mask)
- ____cacheline_internodealigned_in_smp;
-
-/*
- * Per-tile IRQ nesting depth. Used to make sure we enable newly
- * enabled IRQs before exiting the outermost interrupt.
- */
-static DEFINE_PER_CPU(int, irq_depth);
-
-#if CHIP_HAS_IPI()
-/* Use SPRs to manipulate device interrupts. */
-#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask)
-#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask)
-#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask)
-#else
-/* Use HV to manipulate device interrupts. */
-#define mask_irqs(irq_mask) hv_disable_intr(irq_mask)
-#define unmask_irqs(irq_mask) hv_enable_intr(irq_mask)
-#define clear_irqs(irq_mask) hv_clear_intr(irq_mask)
-#endif
-
-/*
- * The interrupt handling path, implemented in terms of HV interrupt
- * emulation on TILEPro, and IPI hardware on TILE-Gx.
- * Entered with interrupts disabled.
- */
-void tile_dev_intr(struct pt_regs *regs, int intnum)
-{
- int depth = __this_cpu_inc_return(irq_depth);
- unsigned long original_irqs;
- unsigned long remaining_irqs;
- struct pt_regs *old_regs;
-
-#if CHIP_HAS_IPI()
- /*
- * Pending interrupts are listed in an SPR. We might be
- * nested, so be sure to only handle irqs that weren't already
- * masked by a previous interrupt. Then, mask out the ones
- * we're going to handle.
- */
- unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K);
- original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked;
- __insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs);
-#else
- /*
- * Hypervisor performs the equivalent of the Gx code above and
- * then puts the pending interrupt mask into a system save reg
- * for us to find.
- */
- original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3);
-#endif
- remaining_irqs = original_irqs;
-
- /* Track time spent here in an interrupt context. */
- old_regs = set_irq_regs(regs);
- irq_enter();
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
- /* Debugging check for stack overflow: less than 1/8th stack free? */
- {
- long sp = stack_pointer - (long) current_thread_info();
- if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
- pr_emerg("%s: stack overflow: %ld\n",
- __func__, sp - sizeof(struct thread_info));
- dump_stack();
- }
- }
-#endif
- while (remaining_irqs) {
- unsigned long irq = __ffs(remaining_irqs);
- remaining_irqs &= ~(1UL << irq);
-
- /* Count device irqs; Linux IPIs are counted elsewhere. */
- if (irq != IRQ_RESCHEDULE)
- __this_cpu_inc(irq_stat.irq_dev_intr_count);
-
- generic_handle_irq(irq);
- }
-
- /*
- * If we weren't nested, turn on all enabled interrupts,
- * including any that were reenabled during interrupt
- * handling.
- */
- if (depth == 1)
- unmask_irqs(~__this_cpu_read(irq_disable_mask));
-
- __this_cpu_dec(irq_depth);
-
- /*
- * Track time spent against the current process again and
- * process any softirqs if they are waiting.
- */
- irq_exit();
- set_irq_regs(old_regs);
-}
-
-
-/*
- * Remove an irq from the disabled mask. If we're in an interrupt
- * context, defer enabling the HW interrupt until we leave.
- */
-static void tile_irq_chip_enable(struct irq_data *d)
-{
- get_cpu_var(irq_disable_mask) &= ~(1UL << d->irq);
- if (__this_cpu_read(irq_depth) == 0)
- unmask_irqs(1UL << d->irq);
- put_cpu_var(irq_disable_mask);
-}
-
-/*
- * Add an irq to the disabled mask. We disable the HW interrupt
- * immediately so that there's no possibility of it firing. If we're
- * in an interrupt context, the return path is careful to avoid
- * unmasking a newly disabled interrupt.
- */
-static void tile_irq_chip_disable(struct irq_data *d)
-{
- get_cpu_var(irq_disable_mask) |= (1UL << d->irq);
- mask_irqs(1UL << d->irq);
- put_cpu_var(irq_disable_mask);
-}
-
-/* Mask an interrupt. */
-static void tile_irq_chip_mask(struct irq_data *d)
-{
- mask_irqs(1UL << d->irq);
-}
-
-/* Unmask an interrupt. */
-static void tile_irq_chip_unmask(struct irq_data *d)
-{
- unmask_irqs(1UL << d->irq);
-}
-
-/*
- * Clear an interrupt before processing it so that any new assertions
- * will trigger another irq.
- */
-static void tile_irq_chip_ack(struct irq_data *d)
-{
- if ((unsigned long)irq_data_get_irq_chip_data(d) != IS_HW_CLEARED)
- clear_irqs(1UL << d->irq);
-}
-
-/*
- * For per-cpu interrupts, we need to avoid unmasking any interrupts
- * that we disabled via disable_percpu_irq().
- */
-static void tile_irq_chip_eoi(struct irq_data *d)
-{
- if (!(__this_cpu_read(irq_disable_mask) & (1UL << d->irq)))
- unmask_irqs(1UL << d->irq);
-}
-
-static struct irq_chip tile_irq_chip = {
- .name = "tile_irq_chip",
- .irq_enable = tile_irq_chip_enable,
- .irq_disable = tile_irq_chip_disable,
- .irq_ack = tile_irq_chip_ack,
- .irq_eoi = tile_irq_chip_eoi,
- .irq_mask = tile_irq_chip_mask,
- .irq_unmask = tile_irq_chip_unmask,
-};
-
-void __init init_IRQ(void)
-{
- ipi_init();
-}
-
-void setup_irq_regs(void)
-{
- /* Enable interrupt delivery. */
- unmask_irqs(~0UL);
-#if CHIP_HAS_IPI()
- arch_local_irq_unmask(INT_IPI_K);
-#endif
-}
-
-void tile_irq_activate(unsigned int irq, int tile_irq_type)
-{
- /*
- * We use handle_level_irq() by default because the pending
- * interrupt vector (whether modeled by the HV on
- * TILEPro or implemented in hardware on TILE-Gx) has
- * level-style semantics for each bit. An interrupt fires
- * whenever a bit is high, not just at edges.
- */
- irq_flow_handler_t handle = handle_level_irq;
- if (tile_irq_type == TILE_IRQ_PERCPU)
- handle = handle_percpu_irq;
- irq_set_chip_and_handler(irq, &tile_irq_chip, handle);
-
- /*
- * Flag interrupts that are hardware-cleared so that ack()
- * won't clear them.
- */
- if (tile_irq_type == TILE_IRQ_HW_CLEAR)
- irq_set_chip_data(irq, (void *)IS_HW_CLEARED);
-}
-EXPORT_SYMBOL(tile_irq_activate);
-
-
-void ack_bad_irq(unsigned int irq)
-{
- pr_err("unexpected IRQ trap at vector %02x\n", irq);
-}
-
-/*
- * /proc/interrupts printing:
- */
-int arch_show_interrupts(struct seq_file *p, int prec)
-{
-#ifdef CONFIG_PERF_EVENTS
- int i;
-
- seq_printf(p, "%*s: ", prec, "PMI");
-
- for_each_online_cpu(i)
- seq_printf(p, "%10llu ", per_cpu(perf_irqs, i));
- seq_puts(p, " perf_events\n");
-#endif
- return 0;
-}
-
-#if CHIP_HAS_IPI()
-int arch_setup_hwirq(unsigned int irq, int node)
-{
- return irq >= NR_IRQS ? -EINVAL : 0;
-}
-
-void arch_teardown_hwirq(unsigned int irq) { }
-#endif
diff --git a/arch/tile/kernel/jump_label.c b/arch/tile/kernel/jump_label.c
deleted file mode 100644
index 93931a46625b..000000000000
--- a/arch/tile/kernel/jump_label.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2015 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * jump label TILE-Gx support
- */
-
-#include <linux/jump_label.h>
-#include <linux/memory.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/cpu.h>
-
-#include <asm/cacheflush.h>
-#include <asm/insn.h>
-
-#ifdef HAVE_JUMP_LABEL
-
-static void __jump_label_transform(struct jump_entry *e,
- enum jump_label_type type)
-{
- tilegx_bundle_bits opcode;
- /* Operate on writable kernel text mapping. */
- unsigned long pc_wr = ktext_writable_addr(e->code);
-
- if (type == JUMP_LABEL_JMP)
- opcode = tilegx_gen_branch(e->code, e->target, false);
- else
- opcode = NOP();
-
- *(tilegx_bundle_bits *)pc_wr = opcode;
- /* Make sure that above mem writes were issued towards the memory. */
- smp_wmb();
-}
-
-void arch_jump_label_transform(struct jump_entry *e,
- enum jump_label_type type)
-{
- mutex_lock(&text_mutex);
-
- __jump_label_transform(e, type);
- flush_icache_range(e->code, e->code + sizeof(tilegx_bundle_bits));
-
- mutex_unlock(&text_mutex);
-}
-
-__init_or_module void arch_jump_label_transform_static(struct jump_entry *e,
- enum jump_label_type type)
-{
- __jump_label_transform(e, type);
-}
-
-#endif /* HAVE_JUMP_LABEL */
diff --git a/arch/tile/kernel/kgdb.c b/arch/tile/kernel/kgdb.c
deleted file mode 100644
index d4eb5fb2df9d..000000000000
--- a/arch/tile/kernel/kgdb.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE-Gx KGDB support.
- */
-
-#include <linux/ptrace.h>
-#include <linux/kgdb.h>
-#include <linux/kdebug.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/sched/task_stack.h>
-
-#include <asm/cacheflush.h>
-
-static tile_bundle_bits singlestep_insn = TILEGX_BPT_BUNDLE | DIE_SSTEPBP;
-static unsigned long stepped_addr;
-static tile_bundle_bits stepped_instr;
-
-struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
- { "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[0])},
- { "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[1])},
- { "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[2])},
- { "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[3])},
- { "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[4])},
- { "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[5])},
- { "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[6])},
- { "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[7])},
- { "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[8])},
- { "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[9])},
- { "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[10])},
- { "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[11])},
- { "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[12])},
- { "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[13])},
- { "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[14])},
- { "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[15])},
- { "r16", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[16])},
- { "r17", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[17])},
- { "r18", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[18])},
- { "r19", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[19])},
- { "r20", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[20])},
- { "r21", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[21])},
- { "r22", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[22])},
- { "r23", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[23])},
- { "r24", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[24])},
- { "r25", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[25])},
- { "r26", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[26])},
- { "r27", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[27])},
- { "r28", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[28])},
- { "r29", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[29])},
- { "r30", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[30])},
- { "r31", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[31])},
- { "r32", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[32])},
- { "r33", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[33])},
- { "r34", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[34])},
- { "r35", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[35])},
- { "r36", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[36])},
- { "r37", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[37])},
- { "r38", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[38])},
- { "r39", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[39])},
- { "r40", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[40])},
- { "r41", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[41])},
- { "r42", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[42])},
- { "r43", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[43])},
- { "r44", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[44])},
- { "r45", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[45])},
- { "r46", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[46])},
- { "r47", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[47])},
- { "r48", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[48])},
- { "r49", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[49])},
- { "r50", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[50])},
- { "r51", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[51])},
- { "r52", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[52])},
- { "tp", GDB_SIZEOF_REG, offsetof(struct pt_regs, tp)},
- { "sp", GDB_SIZEOF_REG, offsetof(struct pt_regs, sp)},
- { "lr", GDB_SIZEOF_REG, offsetof(struct pt_regs, lr)},
- { "sn", GDB_SIZEOF_REG, -1},
- { "idn0", GDB_SIZEOF_REG, -1},
- { "idn1", GDB_SIZEOF_REG, -1},
- { "udn0", GDB_SIZEOF_REG, -1},
- { "udn1", GDB_SIZEOF_REG, -1},
- { "udn2", GDB_SIZEOF_REG, -1},
- { "udn3", GDB_SIZEOF_REG, -1},
- { "zero", GDB_SIZEOF_REG, -1},
- { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, pc)},
- { "faultnum", GDB_SIZEOF_REG, offsetof(struct pt_regs, faultnum)},
-};
-
-char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
-{
- if (regno >= DBG_MAX_REG_NUM || regno < 0)
- return NULL;
-
- if (dbg_reg_def[regno].offset != -1)
- memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
- dbg_reg_def[regno].size);
- else
- memset(mem, 0, dbg_reg_def[regno].size);
- return dbg_reg_def[regno].name;
-}
-
-int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
-{
- if (regno >= DBG_MAX_REG_NUM || regno < 0)
- return -EINVAL;
-
- if (dbg_reg_def[regno].offset != -1)
- memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
- dbg_reg_def[regno].size);
- return 0;
-}
-
-/*
- * Similar to pt_regs_to_gdb_regs() except that process is sleeping and so
- * we may not be able to get all the info.
- */
-void
-sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
-{
- struct pt_regs *thread_regs;
- const int NGPRS = TREG_LAST_GPR + 1;
-
- if (task == NULL)
- return;
-
- thread_regs = task_pt_regs(task);
- memcpy(gdb_regs, thread_regs, NGPRS * sizeof(unsigned long));
- memset(&gdb_regs[NGPRS], 0,
- (TILEGX_PC_REGNUM - NGPRS) * sizeof(unsigned long));
- gdb_regs[TILEGX_PC_REGNUM] = thread_regs->pc;
- gdb_regs[TILEGX_FAULTNUM_REGNUM] = thread_regs->faultnum;
-}
-
-void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
-{
- regs->pc = pc;
-}
-
-static void kgdb_call_nmi_hook(void *ignored)
-{
- kgdb_nmicallback(raw_smp_processor_id(), NULL);
-}
-
-void kgdb_roundup_cpus(unsigned long flags)
-{
- local_irq_enable();
- smp_call_function(kgdb_call_nmi_hook, NULL, 0);
- local_irq_disable();
-}
-
-/*
- * Convert a kernel address to the writable kernel text mapping.
- */
-static unsigned long writable_address(unsigned long addr)
-{
- unsigned long ret = 0;
-
- if (core_kernel_text(addr))
- ret = ktext_writable_addr(addr);
- else if (is_module_text_address(addr))
- ret = addr;
- else
- pr_err("Unknown virtual address 0x%lx\n", addr);
-
- return ret;
-}
-
-/*
- * Calculate the new address for after a step.
- */
-static unsigned long get_step_address(struct pt_regs *regs)
-{
- int src_reg;
- int jump_off;
- int br_off;
- unsigned long addr;
- unsigned int opcode;
- tile_bundle_bits bundle;
-
- /* Move to the next instruction by default. */
- addr = regs->pc + TILEGX_BUNDLE_SIZE_IN_BYTES;
- bundle = *(unsigned long *)instruction_pointer(regs);
-
- /* 0: X mode, Otherwise: Y mode. */
- if (bundle & TILEGX_BUNDLE_MODE_MASK) {
- if (get_Opcode_Y1(bundle) == RRR_1_OPCODE_Y1 &&
- get_RRROpcodeExtension_Y1(bundle) ==
- UNARY_RRR_1_OPCODE_Y1) {
- opcode = get_UnaryOpcodeExtension_Y1(bundle);
-
- switch (opcode) {
- case JALR_UNARY_OPCODE_Y1:
- case JALRP_UNARY_OPCODE_Y1:
- case JR_UNARY_OPCODE_Y1:
- case JRP_UNARY_OPCODE_Y1:
- src_reg = get_SrcA_Y1(bundle);
- dbg_get_reg(src_reg, &addr, regs);
- break;
- }
- }
- } else if (get_Opcode_X1(bundle) == RRR_0_OPCODE_X1) {
- if (get_RRROpcodeExtension_X1(bundle) ==
- UNARY_RRR_0_OPCODE_X1) {
- opcode = get_UnaryOpcodeExtension_X1(bundle);
-
- switch (opcode) {
- case JALR_UNARY_OPCODE_X1:
- case JALRP_UNARY_OPCODE_X1:
- case JR_UNARY_OPCODE_X1:
- case JRP_UNARY_OPCODE_X1:
- src_reg = get_SrcA_X1(bundle);
- dbg_get_reg(src_reg, &addr, regs);
- break;
- }
- }
- } else if (get_Opcode_X1(bundle) == JUMP_OPCODE_X1) {
- opcode = get_JumpOpcodeExtension_X1(bundle);
-
- switch (opcode) {
- case JAL_JUMP_OPCODE_X1:
- case J_JUMP_OPCODE_X1:
- jump_off = sign_extend(get_JumpOff_X1(bundle), 27);
- addr = regs->pc +
- (jump_off << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES);
- break;
- }
- } else if (get_Opcode_X1(bundle) == BRANCH_OPCODE_X1) {
- br_off = 0;
- opcode = get_BrType_X1(bundle);
-
- switch (opcode) {
- case BEQZT_BRANCH_OPCODE_X1:
- case BEQZ_BRANCH_OPCODE_X1:
- if (get_SrcA_X1(bundle) == 0)
- br_off = get_BrOff_X1(bundle);
- break;
- case BGEZT_BRANCH_OPCODE_X1:
- case BGEZ_BRANCH_OPCODE_X1:
- if (get_SrcA_X1(bundle) >= 0)
- br_off = get_BrOff_X1(bundle);
- break;
- case BGTZT_BRANCH_OPCODE_X1:
- case BGTZ_BRANCH_OPCODE_X1:
- if (get_SrcA_X1(bundle) > 0)
- br_off = get_BrOff_X1(bundle);
- break;
- case BLBCT_BRANCH_OPCODE_X1:
- case BLBC_BRANCH_OPCODE_X1:
- if (!(get_SrcA_X1(bundle) & 1))
- br_off = get_BrOff_X1(bundle);
- break;
- case BLBST_BRANCH_OPCODE_X1:
- case BLBS_BRANCH_OPCODE_X1:
- if (get_SrcA_X1(bundle) & 1)
- br_off = get_BrOff_X1(bundle);
- break;
- case BLEZT_BRANCH_OPCODE_X1:
- case BLEZ_BRANCH_OPCODE_X1:
- if (get_SrcA_X1(bundle) <= 0)
- br_off = get_BrOff_X1(bundle);
- break;
- case BLTZT_BRANCH_OPCODE_X1:
- case BLTZ_BRANCH_OPCODE_X1:
- if (get_SrcA_X1(bundle) < 0)
- br_off = get_BrOff_X1(bundle);
- break;
- case BNEZT_BRANCH_OPCODE_X1:
- case BNEZ_BRANCH_OPCODE_X1:
- if (get_SrcA_X1(bundle) != 0)
- br_off = get_BrOff_X1(bundle);
- break;
- }
-
- if (br_off != 0) {
- br_off = sign_extend(br_off, 17);
- addr = regs->pc +
- (br_off << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES);
- }
- }
-
- return addr;
-}
-
-/*
- * Replace the next instruction after the current instruction with a
- * breakpoint instruction.
- */
-static void do_single_step(struct pt_regs *regs)
-{
- unsigned long addr_wr;
-
- /* Determine where the target instruction will send us to. */
- stepped_addr = get_step_address(regs);
- probe_kernel_read((char *)&stepped_instr, (char *)stepped_addr,
- BREAK_INSTR_SIZE);
-
- addr_wr = writable_address(stepped_addr);
- probe_kernel_write((char *)addr_wr, (char *)&singlestep_insn,
- BREAK_INSTR_SIZE);
- smp_wmb();
- flush_icache_range(stepped_addr, stepped_addr + BREAK_INSTR_SIZE);
-}
-
-static void undo_single_step(struct pt_regs *regs)
-{
- unsigned long addr_wr;
-
- if (stepped_instr == 0)
- return;
-
- addr_wr = writable_address(stepped_addr);
- probe_kernel_write((char *)addr_wr, (char *)&stepped_instr,
- BREAK_INSTR_SIZE);
- stepped_instr = 0;
- smp_wmb();
- flush_icache_range(stepped_addr, stepped_addr + BREAK_INSTR_SIZE);
-}
-
-/*
- * Calls linux_debug_hook before the kernel dies. If KGDB is enabled,
- * then try to fall into the debugger.
- */
-static int
-kgdb_notify(struct notifier_block *self, unsigned long cmd, void *ptr)
-{
- int ret;
- unsigned long flags;
- struct die_args *args = (struct die_args *)ptr;
- struct pt_regs *regs = args->regs;
-
-#ifdef CONFIG_KPROBES
- /*
- * Return immediately if the kprobes fault notifier has set
- * DIE_PAGE_FAULT.
- */
- if (cmd == DIE_PAGE_FAULT)
- return NOTIFY_DONE;
-#endif /* CONFIG_KPROBES */
-
- switch (cmd) {
- case DIE_BREAK:
- case DIE_COMPILED_BPT:
- break;
- case DIE_SSTEPBP:
- local_irq_save(flags);
- kgdb_handle_exception(0, SIGTRAP, 0, regs);
- local_irq_restore(flags);
- return NOTIFY_STOP;
- default:
- /* Userspace events, ignore. */
- if (user_mode(regs))
- return NOTIFY_DONE;
- }
-
- local_irq_save(flags);
- ret = kgdb_handle_exception(args->trapnr, args->signr, args->err, regs);
- local_irq_restore(flags);
- if (ret)
- return NOTIFY_DONE;
-
- return NOTIFY_STOP;
-}
-
-static struct notifier_block kgdb_notifier = {
- .notifier_call = kgdb_notify,
-};
-
-/*
- * kgdb_arch_handle_exception - Handle architecture specific GDB packets.
- * @vector: The error vector of the exception that happened.
- * @signo: The signal number of the exception that happened.
- * @err_code: The error code of the exception that happened.
- * @remcom_in_buffer: The buffer of the packet we have read.
- * @remcom_out_buffer: The buffer of %BUFMAX bytes to write a packet into.
- * @regs: The &struct pt_regs of the current process.
- *
- * This function MUST handle the 'c' and 's' command packets,
- * as well packets to set / remove a hardware breakpoint, if used.
- * If there are additional packets which the hardware needs to handle,
- * they are handled here. The code should return -1 if it wants to
- * process more packets, and a %0 or %1 if it wants to exit from the
- * kgdb callback.
- */
-int kgdb_arch_handle_exception(int vector, int signo, int err_code,
- char *remcom_in_buffer, char *remcom_out_buffer,
- struct pt_regs *regs)
-{
- char *ptr;
- unsigned long address;
-
- /* Undo any stepping we may have done. */
- undo_single_step(regs);
-
- switch (remcom_in_buffer[0]) {
- case 'c':
- case 's':
- case 'D':
- case 'k':
- /*
- * Try to read optional parameter, pc unchanged if no parm.
- * If this was a compiled-in breakpoint, we need to move
- * to the next instruction or we will just breakpoint
- * over and over again.
- */
- ptr = &remcom_in_buffer[1];
- if (kgdb_hex2long(&ptr, &address))
- regs->pc = address;
- else if (*(unsigned long *)regs->pc == compiled_bpt)
- regs->pc += BREAK_INSTR_SIZE;
-
- if (remcom_in_buffer[0] == 's') {
- do_single_step(regs);
- kgdb_single_step = 1;
- atomic_set(&kgdb_cpu_doing_single_step,
- raw_smp_processor_id());
- } else
- atomic_set(&kgdb_cpu_doing_single_step, -1);
-
- return 0;
- }
-
- return -1; /* this means that we do not want to exit from the handler */
-}
-
-struct kgdb_arch arch_kgdb_ops;
-
-/*
- * kgdb_arch_init - Perform any architecture specific initialization.
- *
- * This function will handle the initialization of any architecture
- * specific callbacks.
- */
-int kgdb_arch_init(void)
-{
- tile_bundle_bits bundle = TILEGX_BPT_BUNDLE;
-
- memcpy(arch_kgdb_ops.gdb_bpt_instr, &bundle, BREAK_INSTR_SIZE);
- return register_die_notifier(&kgdb_notifier);
-}
-
-/*
- * kgdb_arch_exit - Perform any architecture specific uninitialization.
- *
- * This function will handle the uninitialization of any architecture
- * specific callbacks, for dynamic registration and unregistration.
- */
-void kgdb_arch_exit(void)
-{
- unregister_die_notifier(&kgdb_notifier);
-}
-
-int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
-{
- int err;
- unsigned long addr_wr = writable_address(bpt->bpt_addr);
-
- if (addr_wr == 0)
- return -1;
-
- err = probe_kernel_read(bpt->saved_instr, (char *)bpt->bpt_addr,
- BREAK_INSTR_SIZE);
- if (err)
- return err;
-
- err = probe_kernel_write((char *)addr_wr, arch_kgdb_ops.gdb_bpt_instr,
- BREAK_INSTR_SIZE);
- smp_wmb();
- flush_icache_range((unsigned long)bpt->bpt_addr,
- (unsigned long)bpt->bpt_addr + BREAK_INSTR_SIZE);
- return err;
-}
-
-int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
-{
- int err;
- unsigned long addr_wr = writable_address(bpt->bpt_addr);
-
- if (addr_wr == 0)
- return -1;
-
- err = probe_kernel_write((char *)addr_wr, (char *)bpt->saved_instr,
- BREAK_INSTR_SIZE);
- smp_wmb();
- flush_icache_range((unsigned long)bpt->bpt_addr,
- (unsigned long)bpt->bpt_addr + BREAK_INSTR_SIZE);
- return err;
-}
diff --git a/arch/tile/kernel/kprobes.c b/arch/tile/kernel/kprobes.c
deleted file mode 100644
index c68694bb1ad2..000000000000
--- a/arch/tile/kernel/kprobes.c
+++ /dev/null
@@ -1,527 +0,0 @@
-/*
- * arch/tile/kernel/kprobes.c
- * Kprobes on TILE-Gx
- *
- * Some portions copied from the MIPS version.
- *
- * Copyright (C) IBM Corporation, 2002, 2004
- * Copyright 2006 Sony Corp.
- * Copyright 2010 Cavium Networks
- *
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/kprobes.h>
-#include <linux/kdebug.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/uaccess.h>
-#include <asm/cacheflush.h>
-
-#include <arch/opcode.h>
-
-DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
-DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
-
-tile_bundle_bits breakpoint_insn = TILEGX_BPT_BUNDLE;
-tile_bundle_bits breakpoint2_insn = TILEGX_BPT_BUNDLE | DIE_SSTEPBP;
-
-/*
- * Check whether instruction is branch or jump, or if executing it
- * has different results depending on where it is executed (e.g. lnk).
- */
-static int __kprobes insn_has_control(kprobe_opcode_t insn)
-{
- if (get_Mode(insn) != 0) { /* Y-format bundle */
- if (get_Opcode_Y1(insn) != RRR_1_OPCODE_Y1 ||
- get_RRROpcodeExtension_Y1(insn) != UNARY_RRR_1_OPCODE_Y1)
- return 0;
-
- switch (get_UnaryOpcodeExtension_Y1(insn)) {
- case JALRP_UNARY_OPCODE_Y1:
- case JALR_UNARY_OPCODE_Y1:
- case JRP_UNARY_OPCODE_Y1:
- case JR_UNARY_OPCODE_Y1:
- case LNK_UNARY_OPCODE_Y1:
- return 1;
- default:
- return 0;
- }
- }
-
- switch (get_Opcode_X1(insn)) {
- case BRANCH_OPCODE_X1: /* branch instructions */
- case JUMP_OPCODE_X1: /* jump instructions: j and jal */
- return 1;
-
- case RRR_0_OPCODE_X1: /* other jump instructions */
- if (get_RRROpcodeExtension_X1(insn) != UNARY_RRR_0_OPCODE_X1)
- return 0;
- switch (get_UnaryOpcodeExtension_X1(insn)) {
- case JALRP_UNARY_OPCODE_X1:
- case JALR_UNARY_OPCODE_X1:
- case JRP_UNARY_OPCODE_X1:
- case JR_UNARY_OPCODE_X1:
- case LNK_UNARY_OPCODE_X1:
- return 1;
- default:
- return 0;
- }
- default:
- return 0;
- }
-}
-
-int __kprobes arch_prepare_kprobe(struct kprobe *p)
-{
- unsigned long addr = (unsigned long)p->addr;
-
- if (addr & (sizeof(kprobe_opcode_t) - 1))
- return -EINVAL;
-
- if (insn_has_control(*p->addr)) {
- pr_notice("Kprobes for control instructions are not supported\n");
- return -EINVAL;
- }
-
- /* insn: must be on special executable page on tile. */
- p->ainsn.insn = get_insn_slot();
- if (!p->ainsn.insn)
- return -ENOMEM;
-
- /*
- * In the kprobe->ainsn.insn[] array we store the original
- * instruction at index zero and a break trap instruction at
- * index one.
- */
- memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
- p->ainsn.insn[1] = breakpoint2_insn;
- p->opcode = *p->addr;
-
- return 0;
-}
-
-void __kprobes arch_arm_kprobe(struct kprobe *p)
-{
- unsigned long addr_wr;
-
- /* Operate on writable kernel text mapping. */
- addr_wr = ktext_writable_addr(p->addr);
-
- if (probe_kernel_write((void *)addr_wr, &breakpoint_insn,
- sizeof(breakpoint_insn)))
- pr_err("%s: failed to enable kprobe\n", __func__);
-
- smp_wmb();
- flush_insn_slot(p);
-}
-
-void __kprobes arch_disarm_kprobe(struct kprobe *kp)
-{
- unsigned long addr_wr;
-
- /* Operate on writable kernel text mapping. */
- addr_wr = ktext_writable_addr(kp->addr);
-
- if (probe_kernel_write((void *)addr_wr, &kp->opcode,
- sizeof(kp->opcode)))
- pr_err("%s: failed to enable kprobe\n", __func__);
-
- smp_wmb();
- flush_insn_slot(kp);
-}
-
-void __kprobes arch_remove_kprobe(struct kprobe *p)
-{
- if (p->ainsn.insn) {
- free_insn_slot(p->ainsn.insn, 0);
- p->ainsn.insn = NULL;
- }
-}
-
-static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb)
-{
- kcb->prev_kprobe.kp = kprobe_running();
- kcb->prev_kprobe.status = kcb->kprobe_status;
- kcb->prev_kprobe.saved_pc = kcb->kprobe_saved_pc;
-}
-
-static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb)
-{
- __this_cpu_write(current_kprobe, kcb->prev_kprobe.kp);
- kcb->kprobe_status = kcb->prev_kprobe.status;
- kcb->kprobe_saved_pc = kcb->prev_kprobe.saved_pc;
-}
-
-static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
- struct kprobe_ctlblk *kcb)
-{
- __this_cpu_write(current_kprobe, p);
- kcb->kprobe_saved_pc = regs->pc;
-}
-
-static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
-{
- /* Single step inline if the instruction is a break. */
- if (p->opcode == breakpoint_insn ||
- p->opcode == breakpoint2_insn)
- regs->pc = (unsigned long)p->addr;
- else
- regs->pc = (unsigned long)&p->ainsn.insn[0];
-}
-
-static int __kprobes kprobe_handler(struct pt_regs *regs)
-{
- struct kprobe *p;
- int ret = 0;
- kprobe_opcode_t *addr;
- struct kprobe_ctlblk *kcb;
-
- addr = (kprobe_opcode_t *)regs->pc;
-
- /*
- * We don't want to be preempted for the entire
- * duration of kprobe processing.
- */
- preempt_disable();
- kcb = get_kprobe_ctlblk();
-
- /* Check we're not actually recursing. */
- if (kprobe_running()) {
- p = get_kprobe(addr);
- if (p) {
- if (kcb->kprobe_status == KPROBE_HIT_SS &&
- p->ainsn.insn[0] == breakpoint_insn) {
- goto no_kprobe;
- }
- /*
- * We have reentered the kprobe_handler(), since
- * another probe was hit while within the handler.
- * We here save the original kprobes variables and
- * just single step on the instruction of the new probe
- * without calling any user handlers.
- */
- save_previous_kprobe(kcb);
- set_current_kprobe(p, regs, kcb);
- kprobes_inc_nmissed_count(p);
- prepare_singlestep(p, regs);
- kcb->kprobe_status = KPROBE_REENTER;
- return 1;
- } else {
- if (*addr != breakpoint_insn) {
- /*
- * The breakpoint instruction was removed by
- * another cpu right after we hit, no further
- * handling of this interrupt is appropriate.
- */
- ret = 1;
- goto no_kprobe;
- }
- p = __this_cpu_read(current_kprobe);
- if (p->break_handler && p->break_handler(p, regs))
- goto ss_probe;
- }
- goto no_kprobe;
- }
-
- p = get_kprobe(addr);
- if (!p) {
- if (*addr != breakpoint_insn) {
- /*
- * The breakpoint instruction was removed right
- * after we hit it. Another cpu has removed
- * either a probepoint or a debugger breakpoint
- * at this address. In either case, no further
- * handling of this interrupt is appropriate.
- */
- ret = 1;
- }
- /* Not one of ours: let kernel handle it. */
- goto no_kprobe;
- }
-
- set_current_kprobe(p, regs, kcb);
- kcb->kprobe_status = KPROBE_HIT_ACTIVE;
-
- if (p->pre_handler && p->pre_handler(p, regs)) {
- /* Handler has already set things up, so skip ss setup. */
- return 1;
- }
-
-ss_probe:
- prepare_singlestep(p, regs);
- kcb->kprobe_status = KPROBE_HIT_SS;
- return 1;
-
-no_kprobe:
- preempt_enable_no_resched();
- return ret;
-}
-
-/*
- * Called after single-stepping. p->addr is the address of the
- * instruction that has been replaced by the breakpoint. To avoid the
- * SMP problems that can occur when we temporarily put back the
- * original opcode to single-step, we single-stepped a copy of the
- * instruction. The address of this copy is p->ainsn.insn.
- *
- * This function prepares to return from the post-single-step
- * breakpoint trap.
- */
-static void __kprobes resume_execution(struct kprobe *p,
- struct pt_regs *regs,
- struct kprobe_ctlblk *kcb)
-{
- unsigned long orig_pc = kcb->kprobe_saved_pc;
- regs->pc = orig_pc + 8;
-}
-
-static inline int post_kprobe_handler(struct pt_regs *regs)
-{
- struct kprobe *cur = kprobe_running();
- struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
-
- if (!cur)
- return 0;
-
- if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
- kcb->kprobe_status = KPROBE_HIT_SSDONE;
- cur->post_handler(cur, regs, 0);
- }
-
- resume_execution(cur, regs, kcb);
-
- /* Restore back the original saved kprobes variables and continue. */
- if (kcb->kprobe_status == KPROBE_REENTER) {
- restore_previous_kprobe(kcb);
- goto out;
- }
- reset_current_kprobe();
-out:
- preempt_enable_no_resched();
-
- return 1;
-}
-
-static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
-{
- struct kprobe *cur = kprobe_running();
- struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
-
- if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
- return 1;
-
- if (kcb->kprobe_status & KPROBE_HIT_SS) {
- /*
- * We are here because the instruction being single
- * stepped caused a page fault. We reset the current
- * kprobe and the ip points back to the probe address
- * and allow the page fault handler to continue as a
- * normal page fault.
- */
- resume_execution(cur, regs, kcb);
- reset_current_kprobe();
- preempt_enable_no_resched();
- }
- return 0;
-}
-
-/*
- * Wrapper routine for handling exceptions.
- */
-int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
- unsigned long val, void *data)
-{
- struct die_args *args = (struct die_args *)data;
- int ret = NOTIFY_DONE;
-
- switch (val) {
- case DIE_BREAK:
- if (kprobe_handler(args->regs))
- ret = NOTIFY_STOP;
- break;
- case DIE_SSTEPBP:
- if (post_kprobe_handler(args->regs))
- ret = NOTIFY_STOP;
- break;
- case DIE_PAGE_FAULT:
- /* kprobe_running() needs smp_processor_id(). */
- preempt_disable();
-
- if (kprobe_running()
- && kprobe_fault_handler(args->regs, args->trapnr))
- ret = NOTIFY_STOP;
- preempt_enable();
- break;
- default:
- break;
- }
- return ret;
-}
-
-int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
-{
- struct jprobe *jp = container_of(p, struct jprobe, kp);
- struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
-
- kcb->jprobe_saved_regs = *regs;
- kcb->jprobe_saved_sp = regs->sp;
-
- memcpy(kcb->jprobes_stack, (void *)kcb->jprobe_saved_sp,
- MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
-
- regs->pc = (unsigned long)(jp->entry);
-
- return 1;
-}
-
-/* Defined in the inline asm below. */
-void jprobe_return_end(void);
-
-void __kprobes jprobe_return(void)
-{
- asm volatile(
- "bpt\n\t"
- ".globl jprobe_return_end\n"
- "jprobe_return_end:\n");
-}
-
-int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
-{
- struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
-
- if (regs->pc >= (unsigned long)jprobe_return &&
- regs->pc <= (unsigned long)jprobe_return_end) {
- *regs = kcb->jprobe_saved_regs;
- memcpy((void *)kcb->jprobe_saved_sp, kcb->jprobes_stack,
- MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
- preempt_enable_no_resched();
-
- return 1;
- }
- return 0;
-}
-
-/*
- * Function return probe trampoline:
- * - init_kprobes() establishes a probepoint here
- * - When the probed function returns, this probe causes the
- * handlers to fire
- */
-static void __used kretprobe_trampoline_holder(void)
-{
- asm volatile(
- "nop\n\t"
- ".global kretprobe_trampoline\n"
- "kretprobe_trampoline:\n\t"
- "nop\n\t"
- : : : "memory");
-}
-
-void kretprobe_trampoline(void);
-
-void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
- struct pt_regs *regs)
-{
- ri->ret_addr = (kprobe_opcode_t *) regs->lr;
-
- /* Replace the return addr with trampoline addr */
- regs->lr = (unsigned long)kretprobe_trampoline;
-}
-
-/*
- * Called when the probe at kretprobe trampoline is hit.
- */
-static int __kprobes trampoline_probe_handler(struct kprobe *p,
- struct pt_regs *regs)
-{
- struct kretprobe_instance *ri = NULL;
- struct hlist_head *head, empty_rp;
- struct hlist_node *tmp;
- unsigned long flags, orig_ret_address = 0;
- unsigned long trampoline_address = (unsigned long)kretprobe_trampoline;
-
- INIT_HLIST_HEAD(&empty_rp);
- kretprobe_hash_lock(current, &head, &flags);
-
- /*
- * It is possible to have multiple instances associated with a given
- * task either because multiple functions in the call path have
- * a return probe installed on them, and/or more than one return
- * return probe was registered for a target function.
- *
- * We can handle this because:
- * - instances are always inserted at the head of the list
- * - when multiple return probes are registered for the same
- * function, the first instance's ret_addr will point to the
- * real return address, and all the rest will point to
- * kretprobe_trampoline
- */
- hlist_for_each_entry_safe(ri, tmp, head, hlist) {
- if (ri->task != current)
- /* another task is sharing our hash bucket */
- continue;
-
- if (ri->rp && ri->rp->handler)
- ri->rp->handler(ri, regs);
-
- orig_ret_address = (unsigned long)ri->ret_addr;
- recycle_rp_inst(ri, &empty_rp);
-
- if (orig_ret_address != trampoline_address) {
- /*
- * This is the real return address. Any other
- * instances associated with this task are for
- * other calls deeper on the call stack
- */
- break;
- }
- }
-
- kretprobe_assert(ri, orig_ret_address, trampoline_address);
- instruction_pointer(regs) = orig_ret_address;
-
- reset_current_kprobe();
- kretprobe_hash_unlock(current, &flags);
- preempt_enable_no_resched();
-
- hlist_for_each_entry_safe(ri, tmp, &empty_rp, hlist) {
- hlist_del(&ri->hlist);
- kfree(ri);
- }
- /*
- * By returning a non-zero value, we are telling
- * kprobe_handler() that we don't want the post_handler
- * to run (and have re-enabled preemption)
- */
- return 1;
-}
-
-int __kprobes arch_trampoline_kprobe(struct kprobe *p)
-{
- if (p->addr == (kprobe_opcode_t *)kretprobe_trampoline)
- return 1;
-
- return 0;
-}
-
-static struct kprobe trampoline_p = {
- .addr = (kprobe_opcode_t *)kretprobe_trampoline,
- .pre_handler = trampoline_probe_handler
-};
-
-int __init arch_init_kprobes(void)
-{
- register_kprobe(&trampoline_p);
- return 0;
-}
diff --git a/arch/tile/kernel/machine_kexec.c b/arch/tile/kernel/machine_kexec.c
deleted file mode 100644
index 008aa2faef55..000000000000
--- a/arch/tile/kernel/machine_kexec.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * based on machine_kexec.c from other architectures in linux-2.6.18
- */
-
-#include <linux/mm.h>
-#include <linux/kexec.h>
-#include <linux/delay.h>
-#include <linux/reboot.h>
-#include <linux/errno.h>
-#include <linux/vmalloc.h>
-#include <linux/cpumask.h>
-#include <linux/kernel.h>
-#include <linux/elf.h>
-#include <linux/highmem.h>
-#include <linux/mmu_context.h>
-#include <linux/io.h>
-#include <linux/timex.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/cacheflush.h>
-#include <asm/checksum.h>
-#include <asm/tlbflush.h>
-#include <asm/homecache.h>
-#include <hv/hypervisor.h>
-
-
-/*
- * This stuff is not in elf.h and is not in any other kernel include.
- * This stuff is needed below in the little boot notes parser to
- * extract the command line so we can pass it to the hypervisor.
- */
-struct Elf32_Bhdr {
- Elf32_Word b_signature;
- Elf32_Word b_size;
- Elf32_Half b_checksum;
- Elf32_Half b_records;
-};
-#define ELF_BOOT_MAGIC 0x0E1FB007
-#define EBN_COMMAND_LINE 0x00000004
-#define roundupsz(X) (((X) + 3) & ~3)
-
-/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
-
-
-void machine_shutdown(void)
-{
- /*
- * Normally we would stop all the other processors here, but
- * the check in machine_kexec_prepare below ensures we'll only
- * get this far if we've been booted with "nosmp" on the
- * command line or without CONFIG_SMP so there's nothing to do
- * here (for now).
- */
-}
-
-void machine_crash_shutdown(struct pt_regs *regs)
-{
- /*
- * Cannot happen. This type of kexec is disabled on this
- * architecture (and enforced in machine_kexec_prepare below).
- */
-}
-
-
-int machine_kexec_prepare(struct kimage *image)
-{
- if (num_online_cpus() > 1) {
- pr_warn("%s: detected attempt to kexec with num_online_cpus() > 1\n",
- __func__);
- return -ENOSYS;
- }
- if (image->type != KEXEC_TYPE_DEFAULT) {
- pr_warn("%s: detected attempt to kexec with unsupported type: %d\n",
- __func__, image->type);
- return -ENOSYS;
- }
- return 0;
-}
-
-void machine_kexec_cleanup(struct kimage *image)
-{
- /*
- * We did nothing in machine_kexec_prepare,
- * so we have nothing to do here.
- */
-}
-
-/*
- * If we can find elf boot notes on this page, return the command
- * line. Otherwise, silently return null. Somewhat kludgy, but no
- * good way to do this without significantly rearchitecting the
- * architecture-independent kexec code.
- */
-
-static unsigned char *kexec_bn2cl(void *pg)
-{
- struct Elf32_Bhdr *bhdrp;
- Elf32_Nhdr *nhdrp;
- unsigned char *desc;
- unsigned char *command_line;
- __sum16 csum;
-
- bhdrp = (struct Elf32_Bhdr *) pg;
-
- /*
- * This routine is invoked for every source page, so make
- * sure to quietly ignore every impossible page.
- */
- if (bhdrp->b_signature != ELF_BOOT_MAGIC ||
- bhdrp->b_size > PAGE_SIZE)
- return 0;
-
- /*
- * If we get a checksum mismatch, warn with the checksum
- * so we can diagnose better.
- */
- csum = ip_compute_csum(pg, bhdrp->b_size);
- if (csum != 0) {
- pr_warn("%s: bad checksum %#x (size %d)\n",
- __func__, csum, bhdrp->b_size);
- return 0;
- }
-
- nhdrp = (Elf32_Nhdr *) (bhdrp + 1);
-
- while (nhdrp->n_type != EBN_COMMAND_LINE) {
-
- desc = (unsigned char *) (nhdrp + 1);
- desc += roundupsz(nhdrp->n_descsz);
-
- nhdrp = (Elf32_Nhdr *) desc;
-
- /* still in bounds? */
- if ((unsigned char *) (nhdrp + 1) >
- ((unsigned char *) pg) + bhdrp->b_size) {
-
- pr_info("%s: out of bounds\n", __func__);
- return 0;
- }
- }
-
- command_line = (unsigned char *) (nhdrp + 1);
- desc = command_line;
-
- while (*desc != '\0') {
- desc++;
- if (((unsigned long)desc & PAGE_MASK) != (unsigned long)pg) {
- pr_info("%s: ran off end of page\n", __func__);
- return 0;
- }
- }
-
- return command_line;
-}
-
-static void kexec_find_and_set_command_line(struct kimage *image)
-{
- kimage_entry_t *ptr, entry;
-
- unsigned char *command_line = 0;
- unsigned char *r;
- HV_Errno hverr;
-
- for (ptr = &image->head;
- (entry = *ptr) && !(entry & IND_DONE);
- ptr = (entry & IND_INDIRECTION) ?
- phys_to_virt((entry & PAGE_MASK)) : ptr + 1) {
-
- if ((entry & IND_SOURCE)) {
- void *va =
- kmap_atomic_pfn(entry >> PAGE_SHIFT);
- r = kexec_bn2cl(va);
- if (r) {
- command_line = r;
- break;
- }
- kunmap_atomic(va);
- }
- }
-
- if (command_line != 0) {
- pr_info("setting new command line to \"%s\"\n", command_line);
-
- hverr = hv_set_command_line(
- (HV_VirtAddr) command_line, strlen(command_line));
- kunmap_atomic(command_line);
- } else {
- pr_info("%s: no command line found; making empty\n", __func__);
- hverr = hv_set_command_line((HV_VirtAddr) command_line, 0);
- }
- if (hverr)
- pr_warn("%s: hv_set_command_line returned error: %d\n",
- __func__, hverr);
-}
-
-/*
- * The kexec code range-checks all its PAs, so to avoid having it run
- * amok and allocate memory and then sequester it from every other
- * controller, we force it to come from controller zero. We also
- * disable the oom-killer since if we do end up running out of memory,
- * that almost certainly won't help.
- */
-struct page *kimage_alloc_pages_arch(gfp_t gfp_mask, unsigned int order)
-{
- gfp_mask |= __GFP_THISNODE | __GFP_NORETRY;
- return alloc_pages_node(0, gfp_mask, order);
-}
-
-/*
- * Address range in which pa=va mapping is set in setup_quasi_va_is_pa().
- * For tilepro, PAGE_OFFSET is used since this is the largest possbile value
- * for tilepro, while for tilegx, we limit it to entire middle level page
- * table which we assume has been allocated and is undoubtedly large enough.
- */
-#ifndef __tilegx__
-#define QUASI_VA_IS_PA_ADDR_RANGE PAGE_OFFSET
-#else
-#define QUASI_VA_IS_PA_ADDR_RANGE PGDIR_SIZE
-#endif
-
-static void setup_quasi_va_is_pa(void)
-{
- HV_PTE pte;
- unsigned long i;
-
- /*
- * Flush our TLB to prevent conflicts between the previous contents
- * and the new stuff we're about to add.
- */
- local_flush_tlb_all();
-
- /*
- * setup VA is PA, at least up to QUASI_VA_IS_PA_ADDR_RANGE.
- * Note here we assume that level-1 page table is defined by
- * HPAGE_SIZE.
- */
- pte = hv_pte(_PAGE_KERNEL | _PAGE_HUGE_PAGE);
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
- for (i = 0; i < (QUASI_VA_IS_PA_ADDR_RANGE >> HPAGE_SHIFT); i++) {
- unsigned long vaddr = i << HPAGE_SHIFT;
- pgd_t *pgd = pgd_offset(current->mm, vaddr);
- pud_t *pud = pud_offset(pgd, vaddr);
- pte_t *ptep = (pte_t *) pmd_offset(pud, vaddr);
- unsigned long pfn = i << (HPAGE_SHIFT - PAGE_SHIFT);
-
- if (pfn_valid(pfn))
- __set_pte(ptep, pfn_pte(pfn, pte));
- }
-}
-
-
-void machine_kexec(struct kimage *image)
-{
- void *reboot_code_buffer;
- pte_t *ptep;
- void (*rnk)(unsigned long, void *, unsigned long)
- __noreturn;
-
- /* Mask all interrupts before starting to reboot. */
- interrupt_mask_set_mask(~0ULL);
-
- kexec_find_and_set_command_line(image);
-
- /*
- * Adjust the home caching of the control page to be cached on
- * this cpu, and copy the assembly helper into the control
- * code page, which we map in the vmalloc area.
- */
- homecache_change_page_home(image->control_code_page, 0,
- smp_processor_id());
- reboot_code_buffer = page_address(image->control_code_page);
- BUG_ON(reboot_code_buffer == NULL);
- ptep = virt_to_pte(NULL, (unsigned long)reboot_code_buffer);
- __set_pte(ptep, pte_mkexec(*ptep));
- memcpy(reboot_code_buffer, relocate_new_kernel,
- relocate_new_kernel_size);
- __flush_icache_range(
- (unsigned long) reboot_code_buffer,
- (unsigned long) reboot_code_buffer + relocate_new_kernel_size);
-
- setup_quasi_va_is_pa();
-
- /* now call it */
- rnk = reboot_code_buffer;
- (*rnk)(image->head, reboot_code_buffer, image->start);
-}
diff --git a/arch/tile/kernel/mcount_64.S b/arch/tile/kernel/mcount_64.S
deleted file mode 100644
index 6c6702451962..000000000000
--- a/arch/tile/kernel/mcount_64.S
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE-Gx specific __mcount support
- */
-
-#include <linux/linkage.h>
-#include <asm/ftrace.h>
-
-#define REGSIZE 8
-
- .text
- .global __mcount
-
- .macro MCOUNT_SAVE_REGS
- addli sp, sp, -REGSIZE
- {
- st sp, lr
- addli r29, sp, - (12 * REGSIZE)
- }
- {
- addli sp, sp, - (13 * REGSIZE)
- st r29, sp
- }
- addli r29, r29, REGSIZE
- { st r29, r0; addli r29, r29, REGSIZE }
- { st r29, r1; addli r29, r29, REGSIZE }
- { st r29, r2; addli r29, r29, REGSIZE }
- { st r29, r3; addli r29, r29, REGSIZE }
- { st r29, r4; addli r29, r29, REGSIZE }
- { st r29, r5; addli r29, r29, REGSIZE }
- { st r29, r6; addli r29, r29, REGSIZE }
- { st r29, r7; addli r29, r29, REGSIZE }
- { st r29, r8; addli r29, r29, REGSIZE }
- { st r29, r9; addli r29, r29, REGSIZE }
- { st r29, r10; addli r29, r29, REGSIZE }
- .endm
-
- .macro MCOUNT_RESTORE_REGS
- addli r29, sp, (2 * REGSIZE)
- { ld r0, r29; addli r29, r29, REGSIZE }
- { ld r1, r29; addli r29, r29, REGSIZE }
- { ld r2, r29; addli r29, r29, REGSIZE }
- { ld r3, r29; addli r29, r29, REGSIZE }
- { ld r4, r29; addli r29, r29, REGSIZE }
- { ld r5, r29; addli r29, r29, REGSIZE }
- { ld r6, r29; addli r29, r29, REGSIZE }
- { ld r7, r29; addli r29, r29, REGSIZE }
- { ld r8, r29; addli r29, r29, REGSIZE }
- { ld r9, r29; addli r29, r29, REGSIZE }
- { ld r10, r29; addli lr, sp, (13 * REGSIZE) }
- { ld lr, lr; addli sp, sp, (14 * REGSIZE) }
- .endm
-
- .macro RETURN_BACK
- { move r12, lr; move lr, r10 }
- jrp r12
- .endm
-
-#ifdef CONFIG_DYNAMIC_FTRACE
-
- .align 64
-STD_ENTRY(__mcount)
-__mcount:
- j ftrace_stub
-STD_ENDPROC(__mcount)
-
- .align 64
-STD_ENTRY(ftrace_caller)
- MCOUNT_SAVE_REGS
-
- /* arg1: self return address */
- /* arg2: parent's return address */
- /* arg3: ftrace_ops */
- /* arg4: regs (but make it NULL) */
- { move r0, lr; moveli r2, hw2_last(function_trace_op) }
- { move r1, r10; shl16insli r2, r2, hw1(function_trace_op) }
- { movei r3, 0; shl16insli r2, r2, hw0(function_trace_op) }
- ld r2,r2
-
- .global ftrace_call
-ftrace_call:
- /*
- * a placeholder for the call to a real tracing function, i.e.
- * ftrace_trace_function()
- */
- nop
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
- .global ftrace_graph_call
-ftrace_graph_call:
- /*
- * a placeholder for the call to a real tracing function, i.e.
- * ftrace_graph_caller()
- */
- nop
-#endif
- MCOUNT_RESTORE_REGS
- .global ftrace_stub
-ftrace_stub:
- RETURN_BACK
-STD_ENDPROC(ftrace_caller)
-
-#else /* ! CONFIG_DYNAMIC_FTRACE */
-
- .align 64
-STD_ENTRY(__mcount)
- {
- moveli r11, hw2_last(ftrace_trace_function)
- moveli r13, hw2_last(ftrace_stub)
- }
- {
- shl16insli r11, r11, hw1(ftrace_trace_function)
- shl16insli r13, r13, hw1(ftrace_stub)
- }
- {
- shl16insli r11, r11, hw0(ftrace_trace_function)
- shl16insli r13, r13, hw0(ftrace_stub)
- }
-
- ld r11, r11
- sub r14, r13, r11
- bnez r14, static_trace
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
- moveli r15, hw2_last(ftrace_graph_return)
- shl16insli r15, r15, hw1(ftrace_graph_return)
- shl16insli r15, r15, hw0(ftrace_graph_return)
- ld r15, r15
- sub r15, r15, r13
- bnez r15, ftrace_graph_caller
-
- {
- moveli r16, hw2_last(ftrace_graph_entry)
- moveli r17, hw2_last(ftrace_graph_entry_stub)
- }
- {
- shl16insli r16, r16, hw1(ftrace_graph_entry)
- shl16insli r17, r17, hw1(ftrace_graph_entry_stub)
- }
- {
- shl16insli r16, r16, hw0(ftrace_graph_entry)
- shl16insli r17, r17, hw0(ftrace_graph_entry_stub)
- }
- ld r16, r16
- sub r17, r16, r17
- bnez r17, ftrace_graph_caller
-
-#endif
- RETURN_BACK
-
-static_trace:
- MCOUNT_SAVE_REGS
-
- /* arg1: self return address */
- /* arg2: parent's return address */
- { move r0, lr; move r1, r10 }
-
- /* call ftrace_trace_function() */
- jalr r11
-
- MCOUNT_RESTORE_REGS
-
- .global ftrace_stub
-ftrace_stub:
- RETURN_BACK
-STD_ENDPROC(__mcount)
-
-#endif /* ! CONFIG_DYNAMIC_FTRACE */
-
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-
-STD_ENTRY(ftrace_graph_caller)
-ftrace_graph_caller:
-#ifndef CONFIG_DYNAMIC_FTRACE
- MCOUNT_SAVE_REGS
-#endif
-
- /* arg1: Get the location of the parent's return address */
- addi r0, sp, 12 * REGSIZE
- /* arg2: Get self return address */
- move r1, lr
-
- jal prepare_ftrace_return
-
- MCOUNT_RESTORE_REGS
- RETURN_BACK
-STD_ENDPROC(ftrace_graph_caller)
-
- .global return_to_handler
-return_to_handler:
- MCOUNT_SAVE_REGS
-
- jal ftrace_return_to_handler
- /* restore the real parent address */
- move r11, r0
-
- MCOUNT_RESTORE_REGS
- jr r11
-
-#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/tile/kernel/messaging.c b/arch/tile/kernel/messaging.c
deleted file mode 100644
index 7475af3aacec..000000000000
--- a/arch/tile/kernel/messaging.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/percpu.h>
-#include <linux/smp.h>
-#include <linux/hardirq.h>
-#include <linux/ptrace.h>
-#include <asm/hv_driver.h>
-#include <asm/irq_regs.h>
-#include <asm/traps.h>
-#include <hv/hypervisor.h>
-#include <arch/interrupts.h>
-
-/* All messages are stored here */
-static DEFINE_PER_CPU(HV_MsgState, msg_state);
-
-void init_messaging(void)
-{
- /* Allocate storage for messages in kernel space */
- HV_MsgState *state = this_cpu_ptr(&msg_state);
- int rc = hv_register_message_state(state);
- if (rc != HV_OK)
- panic("hv_register_message_state: error %d", rc);
-
- /* Make sure downcall interrupts will be enabled. */
- arch_local_irq_unmask(INT_INTCTRL_K);
-}
-
-void hv_message_intr(struct pt_regs *regs, int intnum)
-{
- /*
- * We enter with interrupts disabled and leave them disabled,
- * to match expectations of called functions (e.g.
- * do_ccupdate_local() in mm/slab.c). This is also consistent
- * with normal call entry for device interrupts.
- */
-
- int message[HV_MAX_MESSAGE_SIZE/sizeof(int)];
- HV_RcvMsgInfo rmi;
- int nmsgs = 0;
-
- /* Track time spent here in an interrupt context */
- struct pt_regs *old_regs = set_irq_regs(regs);
- irq_enter();
-
-#ifdef CONFIG_DEBUG_STACKOVERFLOW
- /* Debugging check for stack overflow: less than 1/8th stack free? */
- {
- long sp = stack_pointer - (long) current_thread_info();
- if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
- pr_emerg("%s: stack overflow: %ld\n",
- __func__, sp - sizeof(struct thread_info));
- dump_stack();
- }
- }
-#endif
-
- while (1) {
- HV_MsgState *state = this_cpu_ptr(&msg_state);
- rmi = hv_receive_message(*state, (HV_VirtAddr) message,
- sizeof(message));
- if (rmi.msglen == 0)
- break;
-
- if (rmi.msglen < 0)
- panic("hv_receive_message failed: %d", rmi.msglen);
-
- ++nmsgs;
-
- if (rmi.source == HV_MSG_TILE) {
- int tag;
-
- /* we just send tags for now */
- BUG_ON(rmi.msglen != sizeof(int));
-
- tag = message[0];
-#ifdef CONFIG_SMP
- evaluate_message(message[0]);
-#else
- panic("Received IPI message %d in UP mode", tag);
-#endif
- } else if (rmi.source == HV_MSG_INTR) {
- HV_IntrMsg *him = (HV_IntrMsg *)message;
- struct hv_driver_cb *cb =
- (struct hv_driver_cb *)him->intarg;
- cb->callback(cb, him->intdata);
- __this_cpu_inc(irq_stat.irq_hv_msg_count);
- }
- }
-
- /*
- * We shouldn't have gotten a message downcall with no
- * messages available.
- */
- if (nmsgs == 0)
- panic("Message downcall invoked with no messages!");
-
- /*
- * Track time spent against the current process again and
- * process any softirqs if they are waiting.
- */
- irq_exit();
- set_irq_regs(old_regs);
-}
diff --git a/arch/tile/kernel/module.c b/arch/tile/kernel/module.c
deleted file mode 100644
index 09233fbe7801..000000000000
--- a/arch/tile/kernel/module.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Based on i386 version, copyright (C) 2001 Rusty Russell.
- */
-
-#include <linux/moduleloader.h>
-#include <linux/elf.h>
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/pgtable.h>
-#include <asm/homecache.h>
-#include <arch/opcode.h>
-
-#ifdef MODULE_DEBUG
-#define DEBUGP printk
-#else
-#define DEBUGP(fmt...)
-#endif
-
-/*
- * Allocate some address space in the range MEM_MODULE_START to
- * MEM_MODULE_END and populate it with memory.
- */
-void *module_alloc(unsigned long size)
-{
- struct page **pages;
- pgprot_t prot_rwx = __pgprot(_PAGE_KERNEL | _PAGE_KERNEL_EXEC);
- struct vm_struct *area;
- int i = 0;
- int npages;
-
- npages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
- pages = kmalloc_array(npages, sizeof(*pages), GFP_KERNEL);
- if (pages == NULL)
- return NULL;
- for (; i < npages; ++i) {
- pages[i] = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
- if (!pages[i])
- goto free_pages;
- }
-
- area = __get_vm_area(size, VM_ALLOC, MEM_MODULE_START, MEM_MODULE_END);
- if (!area)
- goto free_pages;
- area->nr_pages = npages;
- area->pages = pages;
-
- if (map_vm_area(area, prot_rwx, pages)) {
- vunmap(area->addr);
- goto free_pages;
- }
-
- return area->addr;
- free_pages:
- while (--i >= 0)
- __free_page(pages[i]);
- kfree(pages);
- return NULL;
-}
-
-
-/* Free memory returned from module_alloc */
-void module_memfree(void *module_region)
-{
- vfree(module_region);
-
- /* Globally flush the L1 icache. */
- flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
- 0, 0, 0, NULL, NULL, 0);
-
- /*
- * FIXME: Add module_arch_freeing_init to trim exception
- * table entries.
- */
-}
-
-#ifdef __tilegx__
-/*
- * Validate that the high 16 bits of "value" is just the sign-extension of
- * the low 48 bits.
- */
-static int validate_hw2_last(long value, struct module *me)
-{
- if (((value << 16) >> 16) != value) {
- pr_warn("module %s: Out of range HW2_LAST value %#lx\n",
- me->name, value);
- return 0;
- }
- return 1;
-}
-
-/*
- * Validate that "value" isn't too big to hold in a JumpOff relocation.
- */
-static int validate_jumpoff(long value)
-{
- /* Determine size of jump offset. */
- int shift = __builtin_clzl(get_JumpOff_X1(create_JumpOff_X1(-1)));
-
- /* Check to see if it fits into the relocation slot. */
- long f = get_JumpOff_X1(create_JumpOff_X1(value));
- f = (f << shift) >> shift;
-
- return f == value;
-}
-#endif
-
-int apply_relocate_add(Elf_Shdr *sechdrs,
- const char *strtab,
- unsigned int symindex,
- unsigned int relsec,
- struct module *me)
-{
- unsigned int i;
- Elf_Rela *rel = (void *)sechdrs[relsec].sh_addr;
- Elf_Sym *sym;
- u64 *location;
- unsigned long value;
-
- DEBUGP("Applying relocate section %u to %u\n", relsec,
- sechdrs[relsec].sh_info);
- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
- /* This is where to make the change */
- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
- + rel[i].r_offset;
- /*
- * This is the symbol it is referring to.
- * Note that all undefined symbols have been resolved.
- */
- sym = (Elf_Sym *)sechdrs[symindex].sh_addr
- + ELF_R_SYM(rel[i].r_info);
- value = sym->st_value + rel[i].r_addend;
-
- switch (ELF_R_TYPE(rel[i].r_info)) {
-
-#ifdef __LITTLE_ENDIAN
-# define MUNGE(func) \
- (*location = ((*location & ~func(-1)) | func(value)))
-#else
-/*
- * Instructions are always little-endian, so when we read them as data,
- * we have to swap them around before and after modifying them.
- */
-# define MUNGE(func) \
- (*location = swab64((swab64(*location) & ~func(-1)) | func(value)))
-#endif
-
-#ifndef __tilegx__
- case R_TILE_32:
- *(uint32_t *)location = value;
- break;
- case R_TILE_IMM16_X0_HA:
- value = (value + 0x8000) >> 16;
- /*FALLTHROUGH*/
- case R_TILE_IMM16_X0_LO:
- MUNGE(create_Imm16_X0);
- break;
- case R_TILE_IMM16_X1_HA:
- value = (value + 0x8000) >> 16;
- /*FALLTHROUGH*/
- case R_TILE_IMM16_X1_LO:
- MUNGE(create_Imm16_X1);
- break;
- case R_TILE_JOFFLONG_X1:
- value -= (unsigned long) location; /* pc-relative */
- value = (long) value >> 3; /* count by instrs */
- MUNGE(create_JOffLong_X1);
- break;
-#else
- case R_TILEGX_64:
- *location = value;
- break;
- case R_TILEGX_IMM16_X0_HW2_LAST:
- if (!validate_hw2_last(value, me))
- return -ENOEXEC;
- value >>= 16;
- /*FALLTHROUGH*/
- case R_TILEGX_IMM16_X0_HW1:
- value >>= 16;
- /*FALLTHROUGH*/
- case R_TILEGX_IMM16_X0_HW0:
- MUNGE(create_Imm16_X0);
- break;
- case R_TILEGX_IMM16_X1_HW2_LAST:
- if (!validate_hw2_last(value, me))
- return -ENOEXEC;
- value >>= 16;
- /*FALLTHROUGH*/
- case R_TILEGX_IMM16_X1_HW1:
- value >>= 16;
- /*FALLTHROUGH*/
- case R_TILEGX_IMM16_X1_HW0:
- MUNGE(create_Imm16_X1);
- break;
- case R_TILEGX_JUMPOFF_X1:
- value -= (unsigned long) location; /* pc-relative */
- value = (long) value >> 3; /* count by instrs */
- if (!validate_jumpoff(value)) {
- pr_warn("module %s: Out of range jump to %#llx at %#llx (%p)\n",
- me->name,
- sym->st_value + rel[i].r_addend,
- rel[i].r_offset, location);
- return -ENOEXEC;
- }
- MUNGE(create_JumpOff_X1);
- break;
-#endif
-
-#undef MUNGE
-
- default:
- pr_err("module %s: Unknown relocation: %d\n",
- me->name, (int) ELF_R_TYPE(rel[i].r_info));
- return -ENOEXEC;
- }
- }
- return 0;
-}
diff --git a/arch/tile/kernel/pci-dma.c b/arch/tile/kernel/pci-dma.c
deleted file mode 100644
index 6a1efe5543fa..000000000000
--- a/arch/tile/kernel/pci-dma.c
+++ /dev/null
@@ -1,607 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/mm.h>
-#include <linux/dma-mapping.h>
-#include <linux/swiotlb.h>
-#include <linux/vmalloc.h>
-#include <linux/export.h>
-#include <asm/tlbflush.h>
-#include <asm/homecache.h>
-
-/* Generic DMA mapping functions: */
-
-/*
- * Allocate what Linux calls "coherent" memory. On TILEPro this is
- * uncached memory; on TILE-Gx it is hash-for-home memory.
- */
-#ifdef __tilepro__
-#define PAGE_HOME_DMA PAGE_HOME_UNCACHED
-#else
-#define PAGE_HOME_DMA PAGE_HOME_HASH
-#endif
-
-static void *tile_dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp,
- unsigned long attrs)
-{
- u64 dma_mask = (dev && dev->coherent_dma_mask) ?
- dev->coherent_dma_mask : DMA_BIT_MASK(32);
- int node = dev ? dev_to_node(dev) : 0;
- int order = get_order(size);
- struct page *pg;
- dma_addr_t addr;
-
- gfp |= __GFP_ZERO;
-
- /*
- * If the mask specifies that the memory be in the first 4 GB, then
- * we force the allocation to come from the DMA zone. We also
- * force the node to 0 since that's the only node where the DMA
- * zone isn't empty. If the mask size is smaller than 32 bits, we
- * may still not be able to guarantee a suitable memory address, in
- * which case we will return NULL. But such devices are uncommon.
- */
- if (dma_mask <= DMA_BIT_MASK(32)) {
- gfp |= GFP_DMA32;
- node = 0;
- }
-
- pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_DMA);
- if (pg == NULL)
- return NULL;
-
- addr = page_to_phys(pg);
- if (addr + size > dma_mask) {
- __homecache_free_pages(pg, order);
- return NULL;
- }
-
- *dma_handle = addr;
-
- return page_address(pg);
-}
-
-/*
- * Free memory that was allocated with tile_dma_alloc_coherent.
- */
-static void tile_dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle,
- unsigned long attrs)
-{
- homecache_free_pages((unsigned long)vaddr, get_order(size));
-}
-
-/*
- * The map routines "map" the specified address range for DMA
- * accesses. The memory belongs to the device after this call is
- * issued, until it is unmapped with dma_unmap_single.
- *
- * We don't need to do any mapping, we just flush the address range
- * out of the cache and return a DMA address.
- *
- * The unmap routines do whatever is necessary before the processor
- * accesses the memory again, and must be called before the driver
- * touches the memory. We can get away with a cache invalidate if we
- * can count on nothing having been touched.
- */
-
-/* Set up a single page for DMA access. */
-static void __dma_prep_page(struct page *page, unsigned long offset,
- size_t size, enum dma_data_direction direction)
-{
- /*
- * Flush the page from cache if necessary.
- * On tilegx, data is delivered to hash-for-home L3; on tilepro,
- * data is delivered direct to memory.
- *
- * NOTE: If we were just doing DMA_TO_DEVICE we could optimize
- * this to be a "flush" not a "finv" and keep some of the
- * state in cache across the DMA operation, but it doesn't seem
- * worth creating the necessary flush_buffer_xxx() infrastructure.
- */
- int home = page_home(page);
- switch (home) {
- case PAGE_HOME_HASH:
-#ifdef __tilegx__
- return;
-#endif
- break;
- case PAGE_HOME_UNCACHED:
-#ifdef __tilepro__
- return;
-#endif
- break;
- case PAGE_HOME_IMMUTABLE:
- /* Should be going to the device only. */
- BUG_ON(direction == DMA_FROM_DEVICE ||
- direction == DMA_BIDIRECTIONAL);
- return;
- case PAGE_HOME_INCOHERENT:
- /* Incoherent anyway, so no need to work hard here. */
- return;
- default:
- BUG_ON(home < 0 || home >= NR_CPUS);
- break;
- }
- homecache_finv_page(page);
-
-#ifdef DEBUG_ALIGNMENT
- /* Warn if the region isn't cacheline aligned. */
- if (offset & (L2_CACHE_BYTES - 1) || (size & (L2_CACHE_BYTES - 1)))
- pr_warn("Unaligned DMA to non-hfh memory: PA %#llx/%#lx\n",
- PFN_PHYS(page_to_pfn(page)) + offset, size);
-#endif
-}
-
-/* Make the page ready to be read by the core. */
-static void __dma_complete_page(struct page *page, unsigned long offset,
- size_t size, enum dma_data_direction direction)
-{
-#ifdef __tilegx__
- switch (page_home(page)) {
- case PAGE_HOME_HASH:
- /* I/O device delivered data the way the cpu wanted it. */
- break;
- case PAGE_HOME_INCOHERENT:
- /* Incoherent anyway, so no need to work hard here. */
- break;
- case PAGE_HOME_IMMUTABLE:
- /* Extra read-only copies are not a problem. */
- break;
- default:
- /* Flush the bogus hash-for-home I/O entries to memory. */
- homecache_finv_map_page(page, PAGE_HOME_HASH);
- break;
- }
-#endif
-}
-
-static void __dma_prep_pa_range(dma_addr_t dma_addr, size_t size,
- enum dma_data_direction direction)
-{
- struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
- unsigned long offset = dma_addr & (PAGE_SIZE - 1);
- size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
-
- while (size != 0) {
- __dma_prep_page(page, offset, bytes, direction);
- size -= bytes;
- ++page;
- offset = 0;
- bytes = min((size_t)PAGE_SIZE, size);
- }
-}
-
-static void __dma_complete_pa_range(dma_addr_t dma_addr, size_t size,
- enum dma_data_direction direction)
-{
- struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
- unsigned long offset = dma_addr & (PAGE_SIZE - 1);
- size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
-
- while (size != 0) {
- __dma_complete_page(page, offset, bytes, direction);
- size -= bytes;
- ++page;
- offset = 0;
- bytes = min((size_t)PAGE_SIZE, size);
- }
-}
-
-static int tile_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
-
- WARN_ON(nents == 0 || sglist->length == 0);
-
- for_each_sg(sglist, sg, nents, i) {
- sg->dma_address = sg_phys(sg);
-#ifdef CONFIG_NEED_SG_DMA_LENGTH
- sg->dma_length = sg->length;
-#endif
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
- __dma_prep_pa_range(sg->dma_address, sg->length, direction);
- }
-
- return nents;
-}
-
-static void tile_dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
- for_each_sg(sglist, sg, nents, i) {
- sg->dma_address = sg_phys(sg);
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- continue;
- __dma_complete_pa_range(sg->dma_address, sg->length,
- direction);
- }
-}
-
-static dma_addr_t tile_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction,
- unsigned long attrs)
-{
- BUG_ON(!valid_dma_direction(direction));
-
- BUG_ON(offset + size > PAGE_SIZE);
- if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
- __dma_prep_page(page, offset, size, direction);
-
- return page_to_pa(page) + offset;
-}
-
-static void tile_dma_unmap_page(struct device *dev, dma_addr_t dma_address,
- size_t size, enum dma_data_direction direction,
- unsigned long attrs)
-{
- BUG_ON(!valid_dma_direction(direction));
-
- if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
- return;
-
- __dma_complete_page(pfn_to_page(PFN_DOWN(dma_address)),
- dma_address & (PAGE_SIZE - 1), size, direction);
-}
-
-static void tile_dma_sync_single_for_cpu(struct device *dev,
- dma_addr_t dma_handle,
- size_t size,
- enum dma_data_direction direction)
-{
- BUG_ON(!valid_dma_direction(direction));
-
- __dma_complete_pa_range(dma_handle, size, direction);
-}
-
-static void tile_dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle, size_t size,
- enum dma_data_direction direction)
-{
- __dma_prep_pa_range(dma_handle, size, direction);
-}
-
-static void tile_dma_sync_sg_for_cpu(struct device *dev,
- struct scatterlist *sglist, int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
- WARN_ON(nelems == 0 || sglist->length == 0);
-
- for_each_sg(sglist, sg, nelems, i) {
- dma_sync_single_for_cpu(dev, sg->dma_address,
- sg_dma_len(sg), direction);
- }
-}
-
-static void tile_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sglist, int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
- WARN_ON(nelems == 0 || sglist->length == 0);
-
- for_each_sg(sglist, sg, nelems, i) {
- dma_sync_single_for_device(dev, sg->dma_address,
- sg_dma_len(sg), direction);
- }
-}
-
-static const struct dma_map_ops tile_default_dma_map_ops = {
- .alloc = tile_dma_alloc_coherent,
- .free = tile_dma_free_coherent,
- .map_page = tile_dma_map_page,
- .unmap_page = tile_dma_unmap_page,
- .map_sg = tile_dma_map_sg,
- .unmap_sg = tile_dma_unmap_sg,
- .sync_single_for_cpu = tile_dma_sync_single_for_cpu,
- .sync_single_for_device = tile_dma_sync_single_for_device,
- .sync_sg_for_cpu = tile_dma_sync_sg_for_cpu,
- .sync_sg_for_device = tile_dma_sync_sg_for_device,
-};
-
-const struct dma_map_ops *tile_dma_map_ops = &tile_default_dma_map_ops;
-EXPORT_SYMBOL(tile_dma_map_ops);
-
-/* Generic PCI DMA mapping functions */
-
-static void *tile_pci_dma_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_handle, gfp_t gfp,
- unsigned long attrs)
-{
- int node = dev_to_node(dev);
- int order = get_order(size);
- struct page *pg;
- dma_addr_t addr;
-
- gfp |= __GFP_ZERO;
-
- pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_DMA);
- if (pg == NULL)
- return NULL;
-
- addr = page_to_phys(pg);
-
- *dma_handle = addr + get_dma_offset(dev);
-
- return page_address(pg);
-}
-
-/*
- * Free memory that was allocated with tile_pci_dma_alloc_coherent.
- */
-static void tile_pci_dma_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_handle,
- unsigned long attrs)
-{
- homecache_free_pages((unsigned long)vaddr, get_order(size));
-}
-
-static int tile_pci_dma_map_sg(struct device *dev, struct scatterlist *sglist,
- int nents, enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
-
- WARN_ON(nents == 0 || sglist->length == 0);
-
- for_each_sg(sglist, sg, nents, i) {
- sg->dma_address = sg_phys(sg);
- __dma_prep_pa_range(sg->dma_address, sg->length, direction);
-
- sg->dma_address = sg->dma_address + get_dma_offset(dev);
-#ifdef CONFIG_NEED_SG_DMA_LENGTH
- sg->dma_length = sg->length;
-#endif
- }
-
- return nents;
-}
-
-static void tile_pci_dma_unmap_sg(struct device *dev,
- struct scatterlist *sglist, int nents,
- enum dma_data_direction direction,
- unsigned long attrs)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
- for_each_sg(sglist, sg, nents, i) {
- sg->dma_address = sg_phys(sg);
- __dma_complete_pa_range(sg->dma_address, sg->length,
- direction);
- }
-}
-
-static dma_addr_t tile_pci_dma_map_page(struct device *dev, struct page *page,
- unsigned long offset, size_t size,
- enum dma_data_direction direction,
- unsigned long attrs)
-{
- BUG_ON(!valid_dma_direction(direction));
-
- BUG_ON(offset + size > PAGE_SIZE);
- __dma_prep_page(page, offset, size, direction);
-
- return page_to_pa(page) + offset + get_dma_offset(dev);
-}
-
-static void tile_pci_dma_unmap_page(struct device *dev, dma_addr_t dma_address,
- size_t size,
- enum dma_data_direction direction,
- unsigned long attrs)
-{
- BUG_ON(!valid_dma_direction(direction));
-
- dma_address -= get_dma_offset(dev);
-
- __dma_complete_page(pfn_to_page(PFN_DOWN(dma_address)),
- dma_address & (PAGE_SIZE - 1), size, direction);
-}
-
-static void tile_pci_dma_sync_single_for_cpu(struct device *dev,
- dma_addr_t dma_handle,
- size_t size,
- enum dma_data_direction direction)
-{
- BUG_ON(!valid_dma_direction(direction));
-
- dma_handle -= get_dma_offset(dev);
-
- __dma_complete_pa_range(dma_handle, size, direction);
-}
-
-static void tile_pci_dma_sync_single_for_device(struct device *dev,
- dma_addr_t dma_handle,
- size_t size,
- enum dma_data_direction
- direction)
-{
- dma_handle -= get_dma_offset(dev);
-
- __dma_prep_pa_range(dma_handle, size, direction);
-}
-
-static void tile_pci_dma_sync_sg_for_cpu(struct device *dev,
- struct scatterlist *sglist,
- int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
- WARN_ON(nelems == 0 || sglist->length == 0);
-
- for_each_sg(sglist, sg, nelems, i) {
- dma_sync_single_for_cpu(dev, sg->dma_address,
- sg_dma_len(sg), direction);
- }
-}
-
-static void tile_pci_dma_sync_sg_for_device(struct device *dev,
- struct scatterlist *sglist,
- int nelems,
- enum dma_data_direction direction)
-{
- struct scatterlist *sg;
- int i;
-
- BUG_ON(!valid_dma_direction(direction));
- WARN_ON(nelems == 0 || sglist->length == 0);
-
- for_each_sg(sglist, sg, nelems, i) {
- dma_sync_single_for_device(dev, sg->dma_address,
- sg_dma_len(sg), direction);
- }
-}
-
-static const struct dma_map_ops tile_pci_default_dma_map_ops = {
- .alloc = tile_pci_dma_alloc_coherent,
- .free = tile_pci_dma_free_coherent,
- .map_page = tile_pci_dma_map_page,
- .unmap_page = tile_pci_dma_unmap_page,
- .map_sg = tile_pci_dma_map_sg,
- .unmap_sg = tile_pci_dma_unmap_sg,
- .sync_single_for_cpu = tile_pci_dma_sync_single_for_cpu,
- .sync_single_for_device = tile_pci_dma_sync_single_for_device,
- .sync_sg_for_cpu = tile_pci_dma_sync_sg_for_cpu,
- .sync_sg_for_device = tile_pci_dma_sync_sg_for_device,
-};
-
-const struct dma_map_ops *gx_pci_dma_map_ops = &tile_pci_default_dma_map_ops;
-EXPORT_SYMBOL(gx_pci_dma_map_ops);
-
-/* PCI DMA mapping functions for legacy PCI devices */
-
-#ifdef CONFIG_SWIOTLB
-static const struct dma_map_ops pci_hybrid_dma_ops = {
- .alloc = swiotlb_alloc,
- .free = swiotlb_free,
- .map_page = tile_pci_dma_map_page,
- .unmap_page = tile_pci_dma_unmap_page,
- .map_sg = tile_pci_dma_map_sg,
- .unmap_sg = tile_pci_dma_unmap_sg,
- .sync_single_for_cpu = tile_pci_dma_sync_single_for_cpu,
- .sync_single_for_device = tile_pci_dma_sync_single_for_device,
- .sync_sg_for_cpu = tile_pci_dma_sync_sg_for_cpu,
- .sync_sg_for_device = tile_pci_dma_sync_sg_for_device,
-};
-
-const struct dma_map_ops *gx_legacy_pci_dma_map_ops = &swiotlb_dma_ops;
-const struct dma_map_ops *gx_hybrid_pci_dma_map_ops = &pci_hybrid_dma_ops;
-#else
-const struct dma_map_ops *gx_legacy_pci_dma_map_ops;
-const struct dma_map_ops *gx_hybrid_pci_dma_map_ops;
-#endif
-EXPORT_SYMBOL(gx_legacy_pci_dma_map_ops);
-EXPORT_SYMBOL(gx_hybrid_pci_dma_map_ops);
-
-int dma_set_mask(struct device *dev, u64 mask)
-{
- const struct dma_map_ops *dma_ops = get_dma_ops(dev);
-
- /*
- * For PCI devices with 64-bit DMA addressing capability, promote
- * the dma_ops to hybrid, with the consistent memory DMA space limited
- * to 32-bit. For 32-bit capable devices, limit the streaming DMA
- * address range to max_direct_dma_addr.
- */
- if (dma_ops == gx_pci_dma_map_ops ||
- dma_ops == gx_hybrid_pci_dma_map_ops ||
- dma_ops == gx_legacy_pci_dma_map_ops) {
- if (mask == DMA_BIT_MASK(64) &&
- dma_ops == gx_legacy_pci_dma_map_ops)
- set_dma_ops(dev, gx_hybrid_pci_dma_map_ops);
- else if (mask > dev->archdata.max_direct_dma_addr)
- mask = dev->archdata.max_direct_dma_addr;
- }
-
- if (!dev->dma_mask || !dma_supported(dev, mask))
- return -EIO;
-
- *dev->dma_mask = mask;
-
- return 0;
-}
-EXPORT_SYMBOL(dma_set_mask);
-
-#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
-int dma_set_coherent_mask(struct device *dev, u64 mask)
-{
- const struct dma_map_ops *dma_ops = get_dma_ops(dev);
-
- /*
- * For PCI devices with 64-bit DMA addressing capability, promote
- * the dma_ops to full capability for both streams and consistent
- * memory access. For 32-bit capable devices, limit the consistent
- * memory DMA range to max_direct_dma_addr.
- */
- if (dma_ops == gx_pci_dma_map_ops ||
- dma_ops == gx_hybrid_pci_dma_map_ops ||
- dma_ops == gx_legacy_pci_dma_map_ops) {
- if (mask == DMA_BIT_MASK(64))
- set_dma_ops(dev, gx_pci_dma_map_ops);
- else if (mask > dev->archdata.max_direct_dma_addr)
- mask = dev->archdata.max_direct_dma_addr;
- }
-
- if (!dma_supported(dev, mask))
- return -EIO;
- dev->coherent_dma_mask = mask;
- return 0;
-}
-EXPORT_SYMBOL(dma_set_coherent_mask);
-#endif
-
-#ifdef ARCH_HAS_DMA_GET_REQUIRED_MASK
-/*
- * The generic dma_get_required_mask() uses the highest physical address
- * (max_pfn) to provide the hint to the PCI drivers regarding 32-bit or
- * 64-bit DMA configuration. Since TILEGx has I/O TLB/MMU, allowing the
- * DMAs to use the full 64-bit PCI address space and not limited by
- * the physical memory space, we always let the PCI devices use
- * 64-bit DMA if they have that capability, by returning the 64-bit
- * DMA mask here. The device driver has the option to use 32-bit DMA if
- * the device is not capable of 64-bit DMA.
- */
-u64 dma_get_required_mask(struct device *dev)
-{
- return DMA_BIT_MASK(64);
-}
-EXPORT_SYMBOL_GPL(dma_get_required_mask);
-#endif
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
deleted file mode 100644
index bbf81579b1f8..000000000000
--- a/arch/tile/kernel/pci.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/init.h>
-#include <linux/capability.h>
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/uaccess.h>
-#include <linux/export.h>
-
-#include <asm/processor.h>
-#include <asm/sections.h>
-#include <asm/byteorder.h>
-#include <asm/hv_driver.h>
-#include <hv/drv_pcie_rc_intf.h>
-
-
-/*
- * Initialization flow and process
- * -------------------------------
- *
- * This files contains the routines to search for PCI buses,
- * enumerate the buses, and configure any attached devices.
- *
- * There are two entry points here:
- * 1) tile_pci_init
- * This sets up the pci_controller structs, and opens the
- * FDs to the hypervisor. This is called from setup_arch() early
- * in the boot process.
- * 2) pcibios_init
- * This probes the PCI bus(es) for any attached hardware. It's
- * called by subsys_initcall. All of the real work is done by the
- * generic Linux PCI layer.
- *
- */
-
-static int pci_probe = 1;
-
-/*
- * This flag tells if the platform is TILEmpower that needs
- * special configuration for the PLX switch chip.
- */
-int __ro_after_init tile_plx_gen1;
-
-static struct pci_controller controllers[TILE_NUM_PCIE];
-static int num_controllers;
-static int pci_scan_flags[TILE_NUM_PCIE];
-
-static struct pci_ops tile_cfg_ops;
-
-
-/*
- * Open a FD to the hypervisor PCI device.
- *
- * controller_id is the controller number, config type is 0 or 1 for
- * config0 or config1 operations.
- */
-static int tile_pcie_open(int controller_id, int config_type)
-{
- char filename[32];
- int fd;
-
- sprintf(filename, "pcie/%d/config%d", controller_id, config_type);
-
- fd = hv_dev_open((HV_VirtAddr)filename, 0);
-
- return fd;
-}
-
-
-/*
- * Get the IRQ numbers from the HV and set up the handlers for them.
- */
-static int tile_init_irqs(int controller_id, struct pci_controller *controller)
-{
- char filename[32];
- int fd;
- int ret;
- int x;
- struct pcie_rc_config rc_config;
-
- sprintf(filename, "pcie/%d/ctl", controller_id);
- fd = hv_dev_open((HV_VirtAddr)filename, 0);
- if (fd < 0) {
- pr_err("PCI: hv_dev_open(%s) failed\n", filename);
- return -1;
- }
- ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config),
- sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF);
- hv_dev_close(fd);
- if (ret != sizeof(rc_config)) {
- pr_err("PCI: wanted %zd bytes, got %d\n",
- sizeof(rc_config), ret);
- return -1;
- }
- /* Record irq_base so that we can map INTx to IRQ # later. */
- controller->irq_base = rc_config.intr;
-
- for (x = 0; x < 4; x++)
- tile_irq_activate(rc_config.intr + x,
- TILE_IRQ_HW_CLEAR);
-
- if (rc_config.plx_gen1)
- controller->plx_gen1 = 1;
-
- return 0;
-}
-
-/*
- * First initialization entry point, called from setup_arch().
- *
- * Find valid controllers and fill in pci_controller structs for each
- * of them.
- *
- * Returns the number of controllers discovered.
- */
-int __init tile_pci_init(void)
-{
- int i;
-
- if (!pci_probe) {
- pr_info("PCI: disabled by boot argument\n");
- return 0;
- }
-
- pr_info("PCI: Searching for controllers...\n");
-
- /* Re-init number of PCIe controllers to support hot-plug feature. */
- num_controllers = 0;
-
- /* Do any configuration we need before using the PCIe */
-
- for (i = 0; i < TILE_NUM_PCIE; i++) {
- /*
- * To see whether we need a real config op based on
- * the results of pcibios_init(), to support PCIe hot-plug.
- */
- if (pci_scan_flags[i] == 0) {
- int hv_cfg_fd0 = -1;
- int hv_cfg_fd1 = -1;
- int hv_mem_fd = -1;
- char name[32];
- struct pci_controller *controller;
-
- /*
- * Open the fd to the HV. If it fails then this
- * device doesn't exist.
- */
- hv_cfg_fd0 = tile_pcie_open(i, 0);
- if (hv_cfg_fd0 < 0)
- continue;
- hv_cfg_fd1 = tile_pcie_open(i, 1);
- if (hv_cfg_fd1 < 0) {
- pr_err("PCI: Couldn't open config fd to HV for controller %d\n",
- i);
- goto err_cont;
- }
-
- sprintf(name, "pcie/%d/mem", i);
- hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
- if (hv_mem_fd < 0) {
- pr_err("PCI: Could not open mem fd to HV!\n");
- goto err_cont;
- }
-
- pr_info("PCI: Found PCI controller #%d\n", i);
-
- controller = &controllers[i];
-
- controller->index = i;
- controller->hv_cfg_fd[0] = hv_cfg_fd0;
- controller->hv_cfg_fd[1] = hv_cfg_fd1;
- controller->hv_mem_fd = hv_mem_fd;
- controller->last_busno = 0xff;
- controller->ops = &tile_cfg_ops;
-
- num_controllers++;
- continue;
-
-err_cont:
- if (hv_cfg_fd0 >= 0)
- hv_dev_close(hv_cfg_fd0);
- if (hv_cfg_fd1 >= 0)
- hv_dev_close(hv_cfg_fd1);
- if (hv_mem_fd >= 0)
- hv_dev_close(hv_mem_fd);
- continue;
- }
- }
-
- /*
- * Before using the PCIe, see if we need to do any platform-specific
- * configuration, such as the PLX switch Gen 1 issue on TILEmpower.
- */
- for (i = 0; i < num_controllers; i++) {
- struct pci_controller *controller = &controllers[i];
-
- if (controller->plx_gen1)
- tile_plx_gen1 = 1;
- }
-
- return num_controllers;
-}
-
-/*
- * (pin - 1) converts from the PCI standard's [1:4] convention to
- * a normal [0:3] range.
- */
-static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- struct pci_controller *controller =
- (struct pci_controller *)dev->sysdata;
- return (pin - 1) + controller->irq_base;
-}
-
-
-static void fixup_read_and_payload_sizes(void)
-{
- struct pci_dev *dev = NULL;
- int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
- int max_read_size = PCI_EXP_DEVCTL_READRQ_512B;
- u16 new_values;
-
- /* Scan for the smallest maximum payload size. */
- for_each_pci_dev(dev) {
- if (!pci_is_pcie(dev))
- continue;
-
- if (dev->pcie_mpss < smallest_max_payload)
- smallest_max_payload = dev->pcie_mpss;
- }
-
- /* Now, set the max_payload_size for all devices to that value. */
- new_values = max_read_size | (smallest_max_payload << 5);
- for_each_pci_dev(dev)
- pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
- PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ,
- new_values);
-}
-
-
-/*
- * Second PCI initialization entry point, called by subsys_initcall.
- *
- * The controllers have been set up by the time we get here, by a call to
- * tile_pci_init.
- */
-int __init pcibios_init(void)
-{
- struct pci_host_bridge *bridge;
- int i;
-
- pr_info("PCI: Probing PCI hardware\n");
-
- /*
- * Delay a bit in case devices aren't ready. Some devices are
- * known to require at least 20ms here, but we use a more
- * conservative value.
- */
- msleep(250);
-
- /* Scan all of the recorded PCI controllers. */
- for (i = 0; i < TILE_NUM_PCIE; i++) {
- /*
- * Do real pcibios init ops if the controller is initialized
- * by tile_pci_init() successfully and not initialized by
- * pcibios_init() yet to support PCIe hot-plug.
- */
- if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
- struct pci_controller *controller = &controllers[i];
- struct pci_bus *bus;
- LIST_HEAD(resources);
-
- if (tile_init_irqs(i, controller)) {
- pr_err("PCI: Could not initialize IRQs\n");
- continue;
- }
-
- pr_info("PCI: initializing controller #%d\n", i);
-
- pci_add_resource(&resources, &ioport_resource);
- pci_add_resource(&resources, &iomem_resource);
-
- bridge = pci_alloc_host_bridge(0);
- if (!bridge)
- break;
-
- list_splice_init(&resources, &bridge->windows);
- bridge->dev.parent = NULL;
- bridge->sysdata = controller;
- bridge->busnr = 0;
- bridge->ops = controller->ops;
- bridge->swizzle_irq = pci_common_swizzle;
- bridge->map_irq = tile_map_irq;
-
- pci_scan_root_bus_bridge(bridge);
- bus = bridge->bus;
- controller->root_bus = bus;
- controller->last_busno = bus->busn_res.end;
- }
- }
-
- /*
- * This comes from the generic Linux PCI driver.
- *
- * It allocates all of the resources (I/O memory, etc)
- * associated with the devices read in above.
- */
- pci_assign_unassigned_resources();
-
- /* Configure the max_read_size and max_payload_size values. */
- fixup_read_and_payload_sizes();
-
- /* Record the I/O resources in the PCI controller structure. */
- for (i = 0; i < TILE_NUM_PCIE; i++) {
- /*
- * Do real pcibios init ops if the controller is initialized
- * by tile_pci_init() successfully and not initialized by
- * pcibios_init() yet to support PCIe hot-plug.
- */
- if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
- struct pci_bus *root_bus = controllers[i].root_bus;
- struct pci_bus *next_bus;
- struct pci_dev *dev;
-
- pci_bus_add_devices(root_bus);
-
- list_for_each_entry(dev, &root_bus->devices, bus_list) {
- /*
- * Find the PCI host controller, ie. the 1st
- * bridge.
- */
- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
- (PCI_SLOT(dev->devfn) == 0)) {
- next_bus = dev->subordinate;
- controllers[i].mem_resources[0] =
- *next_bus->resource[0];
- controllers[i].mem_resources[1] =
- *next_bus->resource[1];
- controllers[i].mem_resources[2] =
- *next_bus->resource[2];
-
- /* Setup flags. */
- pci_scan_flags[i] = 1;
-
- break;
- }
- }
- }
- }
-
- return 0;
-}
-subsys_initcall(pcibios_init);
-
-void pcibios_set_master(struct pci_dev *dev)
-{
- /* No special bus mastering setup handling. */
-}
-
-/* Process any "pci=" kernel boot arguments. */
-char *__init pcibios_setup(char *str)
-{
- if (!strcmp(str, "off")) {
- pci_probe = 0;
- return NULL;
- }
- return str;
-}
-
-/*
- * Enable memory and/or address decoding, as appropriate, for the
- * device described by the 'dev' struct.
- *
- * This is called from the generic PCI layer, and can be called
- * for bridges or endpoints.
- */
-int pcibios_enable_device(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- u8 header_type;
- int i;
- struct resource *r;
-
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
- /*
- * For bridges, we enable both memory and I/O decoding
- * in call cases.
- */
- cmd |= PCI_COMMAND_IO;
- cmd |= PCI_COMMAND_MEMORY;
- } else {
- /*
- * For endpoints, we enable memory and/or I/O decoding
- * only if they have a memory resource of that type.
- */
- for (i = 0; i < 6; i++) {
- r = &dev->resource[i];
- if (r->flags & IORESOURCE_UNSET) {
- pr_err("PCI: Device %s not available because of resource collisions\n",
- pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- }
-
- /*
- * We only write the command if it changed.
- */
- if (cmd != old_cmd)
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- return 0;
-}
-
-/****************************************************************
- *
- * Tile PCI config space read/write routines
- *
- ****************************************************************/
-
-/*
- * These are the normal read and write ops
- * These are expanded with macros from pci_bus_read_config_byte() etc.
- *
- * devfn is the combined PCI slot & function.
- *
- * offset is in bytes, from the start of config space for the
- * specified bus & slot.
- */
-
-static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
- int size, u32 *val)
-{
- struct pci_controller *controller = bus->sysdata;
- int busnum = bus->number & 0xff;
- int slot = (devfn >> 3) & 0x1f;
- int function = devfn & 0x7;
- u32 addr;
- int config_mode = 1;
-
- /*
- * There is no bridge between the Tile and bus 0, so we
- * use config0 to talk to bus 0.
- *
- * If we're talking to a bus other than zero then we
- * must have found a bridge.
- */
- if (busnum == 0) {
- /*
- * We fake an empty slot for (busnum == 0) && (slot > 0),
- * since there is only one slot on bus 0.
- */
- if (slot) {
- *val = 0xFFFFFFFF;
- return 0;
- }
- config_mode = 0;
- }
-
- addr = busnum << 20; /* Bus in 27:20 */
- addr |= slot << 15; /* Slot (device) in 19:15 */
- addr |= function << 12; /* Function is in 14:12 */
- addr |= (offset & 0xFFF); /* byte address in 0:11 */
-
- return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0,
- (HV_VirtAddr)(val), size, addr);
-}
-
-
-/*
- * See tile_cfg_read() for relevant comments.
- * Note that "val" is the value to write, not a pointer to that value.
- */
-static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
- int size, u32 val)
-{
- struct pci_controller *controller = bus->sysdata;
- int busnum = bus->number & 0xff;
- int slot = (devfn >> 3) & 0x1f;
- int function = devfn & 0x7;
- u32 addr;
- int config_mode = 1;
- HV_VirtAddr valp = (HV_VirtAddr)&val;
-
- /*
- * For bus 0 slot 0 we use config 0 accesses.
- */
- if (busnum == 0) {
- /*
- * We fake an empty slot for (busnum == 0) && (slot > 0),
- * since there is only one slot on bus 0.
- */
- if (slot)
- return 0;
- config_mode = 0;
- }
-
- addr = busnum << 20; /* Bus in 27:20 */
- addr |= slot << 15; /* Slot (device) in 19:15 */
- addr |= function << 12; /* Function is in 14:12 */
- addr |= (offset & 0xFFF); /* byte address in 0:11 */
-
-#ifdef __BIG_ENDIAN
- /* Point to the correct part of the 32-bit "val". */
- valp += 4 - size;
-#endif
-
- return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0,
- valp, size, addr);
-}
-
-
-static struct pci_ops tile_cfg_ops = {
- .read = tile_cfg_read,
- .write = tile_cfg_write,
-};
-
-
-/*
- * In the following, each PCI controller's mem_resources[1]
- * represents its (non-prefetchable) PCI memory resource.
- * mem_resources[0] and mem_resources[2] refer to its PCI I/O and
- * prefetchable PCI memory resources, respectively.
- * For more details, see pci_setup_bridge() in setup-bus.c.
- * By comparing the target PCI memory address against the
- * end address of controller 0, we can determine the controller
- * that should accept the PCI memory access.
- */
-#define TILE_READ(size, type) \
-type _tile_read##size(unsigned long addr) \
-{ \
- type val; \
- int idx = 0; \
- if (addr > controllers[0].mem_resources[1].end && \
- addr > controllers[0].mem_resources[2].end) \
- idx = 1; \
- if (hv_dev_pread(controllers[idx].hv_mem_fd, 0, \
- (HV_VirtAddr)(&val), sizeof(type), addr)) \
- pr_err("PCI: read %zd bytes at 0x%lX failed\n", \
- sizeof(type), addr); \
- return val; \
-} \
-EXPORT_SYMBOL(_tile_read##size)
-
-TILE_READ(b, u8);
-TILE_READ(w, u16);
-TILE_READ(l, u32);
-TILE_READ(q, u64);
-
-#define TILE_WRITE(size, type) \
-void _tile_write##size(type val, unsigned long addr) \
-{ \
- int idx = 0; \
- if (addr > controllers[0].mem_resources[1].end && \
- addr > controllers[0].mem_resources[2].end) \
- idx = 1; \
- if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0, \
- (HV_VirtAddr)(&val), sizeof(type), addr)) \
- pr_err("PCI: write %zd bytes at 0x%lX failed\n", \
- sizeof(type), addr); \
-} \
-EXPORT_SYMBOL(_tile_write##size)
-
-TILE_WRITE(b, u8);
-TILE_WRITE(w, u16);
-TILE_WRITE(l, u32);
-TILE_WRITE(q, u64);
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
deleted file mode 100644
index 9aa238ac7b35..000000000000
--- a/arch/tile/kernel/pci_gx.c
+++ /dev/null
@@ -1,1592 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/mmzone.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/init.h>
-#include <linux/capability.h>
-#include <linux/sched.h>
-#include <linux/errno.h>
-#include <linux/irq.h>
-#include <linux/msi.h>
-#include <linux/io.h>
-#include <linux/uaccess.h>
-#include <linux/ctype.h>
-
-#include <asm/processor.h>
-#include <asm/sections.h>
-#include <asm/byteorder.h>
-
-#include <gxio/iorpc_globals.h>
-#include <gxio/kiorpc.h>
-#include <gxio/trio.h>
-#include <gxio/iorpc_trio.h>
-#include <hv/drv_trio_intf.h>
-
-#include <arch/sim.h>
-
-/*
- * This file contains the routines to search for PCI buses,
- * enumerate the buses, and configure any attached devices.
- */
-
-#define DEBUG_PCI_CFG 0
-
-#if DEBUG_PCI_CFG
-#define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
- pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
- size, val, bus, dev, func, offset & 0xFFF);
-#define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
- pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
- size, val, bus, dev, func, offset & 0xFFF);
-#else
-#define TRACE_CFG_WR(...)
-#define TRACE_CFG_RD(...)
-#endif
-
-static int pci_probe = 1;
-
-/* Information on the PCIe RC ports configuration. */
-static int pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
-
-/*
- * On some platforms with one or more Gx endpoint ports, we need to
- * delay the PCIe RC port probe for a few seconds to work around
- * a HW PCIe link-training bug. The exact delay is specified with
- * a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
- * where T is the TRIO instance number, P is the port number and S is
- * the delay in seconds. If the argument is specified, but the delay is
- * not provided, the value will be DEFAULT_RC_DELAY.
- */
-static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
-
-/* Default number of seconds that the PCIe RC port probe can be delayed. */
-#define DEFAULT_RC_DELAY 10
-
-/* The PCI I/O space size in each PCI domain. */
-#define IO_SPACE_SIZE 0x10000
-
-/* Provide shorter versions of some very long constant names. */
-#define AUTO_CONFIG_RC \
- TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC
-#define AUTO_CONFIG_RC_G1 \
- TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1
-#define AUTO_CONFIG_EP \
- TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT
-#define AUTO_CONFIG_EP_G1 \
- TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
-
-/* Array of the PCIe ports configuration info obtained from the BIB. */
-struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO];
-
-/* Number of configured TRIO instances. */
-int num_trio_shims;
-
-/* All drivers share the TRIO contexts defined here. */
-gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
-
-/* Pointer to an array of PCIe RC controllers. */
-struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
-int num_rc_controllers;
-
-static struct pci_ops tile_cfg_ops;
-
-/* Mask of CPUs that should receive PCIe interrupts. */
-static struct cpumask intr_cpus_map;
-
-/*
- * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
- * For now, we simply send interrupts to non-dataplane CPUs.
- * We may implement methods to allow user to specify the target CPUs,
- * e.g. via boot arguments.
- */
-static int tile_irq_cpu(int irq)
-{
- unsigned int count;
- int i = 0;
- int cpu;
-
- count = cpumask_weight(&intr_cpus_map);
- if (unlikely(count == 0)) {
- pr_warn("intr_cpus_map empty, interrupts will be delivered to dataplane tiles\n");
- return irq % (smp_height * smp_width);
- }
-
- count = irq % count;
- for_each_cpu(cpu, &intr_cpus_map) {
- if (i++ == count)
- break;
- }
- return cpu;
-}
-
-/* Open a file descriptor to the TRIO shim. */
-static int tile_pcie_open(int trio_index)
-{
- gxio_trio_context_t *context = &trio_contexts[trio_index];
- int ret;
- int mac;
-
- /* This opens a file descriptor to the TRIO shim. */
- ret = gxio_trio_init(context, trio_index);
- if (ret < 0)
- goto gxio_trio_init_failure;
-
- /* Allocate an ASID for the kernel. */
- ret = gxio_trio_alloc_asids(context, 1, 0, 0);
- if (ret < 0) {
- pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
- trio_index);
- goto asid_alloc_failure;
- }
-
- context->asid = ret;
-
-#ifdef USE_SHARED_PCIE_CONFIG_REGION
- /*
- * Alloc a PIO region for config access, shared by all MACs per TRIO.
- * This shouldn't fail since the kernel is supposed to the first
- * client of the TRIO's PIO regions.
- */
- ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
- if (ret < 0) {
- pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
- trio_index);
- goto pio_alloc_failure;
- }
-
- context->pio_cfg_index = ret;
-
- /*
- * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
- * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
- */
- ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
- 0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
- if (ret < 0) {
- pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
- trio_index);
- goto pio_alloc_failure;
- }
-#endif
-
- /* Get the properties of the PCIe ports on this TRIO instance. */
- ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]);
- if (ret < 0) {
- pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d, on TRIO %d\n",
- ret, trio_index);
- goto get_port_property_failure;
- }
-
- context->mmio_base_mac =
- iorpc_ioremap(context->fd, 0, HV_TRIO_CONFIG_IOREMAP_SIZE);
- if (context->mmio_base_mac == NULL) {
- pr_err("PCI: TRIO config space mapping failure, error %d, on TRIO %d\n",
- ret, trio_index);
- ret = -ENOMEM;
-
- goto trio_mmio_mapping_failure;
- }
-
- /* Check the port strap state which will override the BIB setting. */
- for (mac = 0; mac < TILEGX_TRIO_PCIES; mac++) {
- TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
- unsigned int reg_offset;
-
- /* Ignore ports that are not specified in the BIB. */
- if (!pcie_ports[trio_index].ports[mac].allow_rc &&
- !pcie_ports[trio_index].ports[mac].allow_ep)
- continue;
-
- reg_offset =
- (TRIO_PCIE_INTFC_PORT_CONFIG <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- port_config.word =
- __gxio_mmio_read(context->mmio_base_mac + reg_offset);
-
- if (port_config.strap_state != AUTO_CONFIG_RC &&
- port_config.strap_state != AUTO_CONFIG_RC_G1) {
- /*
- * If this is really intended to be an EP port, record
- * it so that the endpoint driver will know about it.
- */
- if (port_config.strap_state == AUTO_CONFIG_EP ||
- port_config.strap_state == AUTO_CONFIG_EP_G1)
- pcie_ports[trio_index].ports[mac].allow_ep = 1;
- }
- }
-
- return ret;
-
-trio_mmio_mapping_failure:
-get_port_property_failure:
-asid_alloc_failure:
-#ifdef USE_SHARED_PCIE_CONFIG_REGION
-pio_alloc_failure:
-#endif
- hv_dev_close(context->fd);
-gxio_trio_init_failure:
- context->fd = -1;
-
- return ret;
-}
-
-static int __init tile_trio_init(void)
-{
- int i;
-
- /* We loop over all the TRIO shims. */
- for (i = 0; i < TILEGX_NUM_TRIO; i++) {
- if (tile_pcie_open(i) < 0)
- continue;
- num_trio_shims++;
- }
-
- return 0;
-}
-postcore_initcall(tile_trio_init);
-
-static void tilegx_legacy_irq_ack(struct irq_data *d)
-{
- __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
-}
-
-static void tilegx_legacy_irq_mask(struct irq_data *d)
-{
- __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
-}
-
-static void tilegx_legacy_irq_unmask(struct irq_data *d)
-{
- __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
-}
-
-static struct irq_chip tilegx_legacy_irq_chip = {
- .name = "tilegx_legacy_irq",
- .irq_ack = tilegx_legacy_irq_ack,
- .irq_mask = tilegx_legacy_irq_mask,
- .irq_unmask = tilegx_legacy_irq_unmask,
-
- /* TBD: support set_affinity. */
-};
-
-/*
- * This is a wrapper function of the kernel level-trigger interrupt
- * handler handle_level_irq() for PCI legacy interrupts. The TRIO
- * is configured such that only INTx Assert interrupts are proxied
- * to Linux which just calls handle_level_irq() after clearing the
- * MAC INTx Assert status bit associated with this interrupt.
- */
-static void trio_handle_level_irq(struct irq_desc *desc)
-{
- struct pci_controller *controller = irq_desc_get_handler_data(desc);
- gxio_trio_context_t *trio_context = controller->trio;
- uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
- int mac = controller->mac;
- unsigned int reg_offset;
- uint64_t level_mask;
-
- handle_level_irq(desc);
-
- /*
- * Clear the INTx Level status, otherwise future interrupts are
- * not sent.
- */
- reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
-
- __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
-}
-
-/*
- * Create kernel irqs and set up the handlers for the legacy interrupts.
- * Also some minimum initialization for the MSI support.
- */
-static int tile_init_irqs(struct pci_controller *controller)
-{
- int i;
- int j;
- int irq;
- int result;
-
- cpumask_copy(&intr_cpus_map, cpu_online_mask);
-
-
- for (i = 0; i < 4; i++) {
- gxio_trio_context_t *context = controller->trio;
- int cpu;
-
- /* Ask the kernel to allocate an IRQ. */
- irq = irq_alloc_hwirq(-1);
- if (!irq) {
- pr_err("PCI: no free irq vectors, failed for %d\n", i);
- goto free_irqs;
- }
- controller->irq_intx_table[i] = irq;
-
- /* Distribute the 4 IRQs to different tiles. */
- cpu = tile_irq_cpu(irq);
-
- /* Configure the TRIO intr binding for this IRQ. */
- result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
- cpu_y(cpu), KERNEL_PL,
- irq, controller->mac, i);
- if (result < 0) {
- pr_err("PCI: MAC intx config failed for %d\n", i);
-
- goto free_irqs;
- }
-
- /* Register the IRQ handler with the kernel. */
- irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
- trio_handle_level_irq);
- irq_set_chip_data(irq, (void *)(uint64_t)i);
- irq_set_handler_data(irq, controller);
- }
-
- return 0;
-
-free_irqs:
- for (j = 0; j < i; j++)
- irq_free_hwirq(controller->irq_intx_table[j]);
-
- return -1;
-}
-
-/*
- * Return 1 if the port is strapped to operate in RC mode.
- */
-static int
-strapped_for_rc(gxio_trio_context_t *trio_context, int mac)
-{
- TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
- unsigned int reg_offset;
-
- /* Check the port configuration. */
- reg_offset =
- (TRIO_PCIE_INTFC_PORT_CONFIG <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
- port_config.word =
- __gxio_mmio_read(trio_context->mmio_base_mac + reg_offset);
-
- if (port_config.strap_state == AUTO_CONFIG_RC ||
- port_config.strap_state == AUTO_CONFIG_RC_G1)
- return 1;
- else
- return 0;
-}
-
-/*
- * Find valid controllers and fill in pci_controller structs for each
- * of them.
- *
- * Return the number of controllers discovered.
- */
-int __init tile_pci_init(void)
-{
- int ctl_index = 0;
- int i, j;
-
- if (!pci_probe) {
- pr_info("PCI: disabled by boot argument\n");
- return 0;
- }
-
- pr_info("PCI: Searching for controllers...\n");
-
- if (num_trio_shims == 0 || sim_is_simulator())
- return 0;
-
- /*
- * Now determine which PCIe ports are configured to operate in RC
- * mode. There is a difference in the port configuration capability
- * between the Gx36 and Gx72 devices.
- *
- * The Gx36 has configuration capability for each of the 3 PCIe
- * interfaces (disable, auto endpoint, auto RC, etc.).
- * On the Gx72, you can only select one of the 3 PCIe interfaces per
- * TRIO to train automatically. Further, the allowable training modes
- * are reduced to four options (auto endpoint, auto RC, stream x1,
- * stream x4).
- *
- * For Gx36 ports, it must be allowed to be in RC mode by the
- * Board Information Block, and the hardware strapping pins must be
- * set to RC mode.
- *
- * For Gx72 ports, the port will operate in RC mode if either of the
- * following is true:
- * 1. It is allowed to be in RC mode by the Board Information Block,
- * and the BIB doesn't allow the EP mode.
- * 2. It is allowed to be in either the RC or the EP mode by the BIB,
- * and the hardware strapping pin is set to RC mode.
- */
- for (i = 0; i < TILEGX_NUM_TRIO; i++) {
- gxio_trio_context_t *context = &trio_contexts[i];
-
- if (context->fd < 0)
- continue;
-
- for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
- int is_rc = 0;
-
- if (pcie_ports[i].is_gx72 &&
- pcie_ports[i].ports[j].allow_rc) {
- if (!pcie_ports[i].ports[j].allow_ep ||
- strapped_for_rc(context, j))
- is_rc = 1;
- } else if (pcie_ports[i].ports[j].allow_rc &&
- strapped_for_rc(context, j)) {
- is_rc = 1;
- }
- if (is_rc) {
- pcie_rc[i][j] = 1;
- num_rc_controllers++;
- }
- }
- }
-
- /* Return if no PCIe ports are configured to operate in RC mode. */
- if (num_rc_controllers == 0)
- return 0;
-
- /* Set the TRIO pointer and MAC index for each PCIe RC port. */
- for (i = 0; i < TILEGX_NUM_TRIO; i++) {
- for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
- if (pcie_rc[i][j]) {
- pci_controllers[ctl_index].trio =
- &trio_contexts[i];
- pci_controllers[ctl_index].mac = j;
- pci_controllers[ctl_index].trio_index = i;
- ctl_index++;
- if (ctl_index == num_rc_controllers)
- goto out;
- }
- }
- }
-
-out:
- /* Configure each PCIe RC port. */
- for (i = 0; i < num_rc_controllers; i++) {
-
- /* Configure the PCIe MAC to run in RC mode. */
- struct pci_controller *controller = &pci_controllers[i];
-
- controller->index = i;
- controller->ops = &tile_cfg_ops;
-
- controller->io_space.start = PCIBIOS_MIN_IO +
- (i * IO_SPACE_SIZE);
- controller->io_space.end = controller->io_space.start +
- IO_SPACE_SIZE - 1;
- BUG_ON(controller->io_space.end > IO_SPACE_LIMIT);
- controller->io_space.flags = IORESOURCE_IO;
- snprintf(controller->io_space_name,
- sizeof(controller->io_space_name),
- "PCI I/O domain %d", i);
- controller->io_space.name = controller->io_space_name;
-
- /*
- * The PCI memory resource is located above the PA space.
- * For every host bridge, the BAR window or the MMIO aperture
- * is in range [3GB, 4GB - 1] of a 4GB space beyond the
- * PA space.
- */
- controller->mem_offset = TILE_PCI_MEM_START +
- (i * TILE_PCI_BAR_WINDOW_TOP);
- controller->mem_space.start = controller->mem_offset +
- TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
- controller->mem_space.end = controller->mem_offset +
- TILE_PCI_BAR_WINDOW_TOP - 1;
- controller->mem_space.flags = IORESOURCE_MEM;
- snprintf(controller->mem_space_name,
- sizeof(controller->mem_space_name),
- "PCI mem domain %d", i);
- controller->mem_space.name = controller->mem_space_name;
- }
-
- return num_rc_controllers;
-}
-
-/*
- * (pin - 1) converts from the PCI standard's [1:4] convention to
- * a normal [0:3] range.
- */
-static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
-{
- struct pci_controller *controller =
- (struct pci_controller *)dev->sysdata;
- return controller->irq_intx_table[pin - 1];
-}
-
-static void fixup_read_and_payload_sizes(struct pci_controller *controller)
-{
- gxio_trio_context_t *trio_context = controller->trio;
- struct pci_bus *root_bus = controller->root_bus;
- TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
- TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
- unsigned int reg_offset;
- struct pci_bus *child;
- int mac;
- int err;
-
- mac = controller->mac;
-
- /* Set our max read request size to be 4KB. */
- reg_offset =
- (TRIO_PCIE_RC_DEVICE_CONTROL <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
- reg_offset);
- dev_control.max_read_req_sz = 5;
- __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
- dev_control.word);
-
- /*
- * Set the max payload size supported by this Gx PCIe MAC.
- * Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
- * experiments have shown that setting MPS to 256 yields the
- * best performance.
- */
- reg_offset =
- (TRIO_PCIE_RC_DEVICE_CAP <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
- reg_offset);
- rc_dev_cap.mps_sup = 1;
- __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
- rc_dev_cap.word);
-
- /* Configure PCI Express MPS setting. */
- list_for_each_entry(child, &root_bus->children, node)
- pcie_bus_configure_settings(child);
-
- /*
- * Set the mac_config register in trio based on the MPS/MRS of the link.
- */
- reg_offset =
- (TRIO_PCIE_RC_DEVICE_CONTROL <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
- reg_offset);
-
- err = gxio_trio_set_mps_mrs(trio_context,
- dev_control.max_payload_size,
- dev_control.max_read_req_sz,
- mac);
- if (err < 0) {
- pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, MAC %d on TRIO %d\n",
- mac, controller->trio_index);
- }
-}
-
-static int setup_pcie_rc_delay(char *str)
-{
- unsigned long delay = 0;
- unsigned long trio_index;
- unsigned long mac;
-
- if (str == NULL || !isdigit(*str))
- return -EINVAL;
- trio_index = simple_strtoul(str, (char **)&str, 10);
- if (trio_index >= TILEGX_NUM_TRIO)
- return -EINVAL;
-
- if (*str != ',')
- return -EINVAL;
-
- str++;
- if (!isdigit(*str))
- return -EINVAL;
- mac = simple_strtoul(str, (char **)&str, 10);
- if (mac >= TILEGX_TRIO_PCIES)
- return -EINVAL;
-
- if (*str != '\0') {
- if (*str != ',')
- return -EINVAL;
-
- str++;
- if (!isdigit(*str))
- return -EINVAL;
- delay = simple_strtoul(str, (char **)&str, 10);
- }
-
- rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
- return 0;
-}
-early_param("pcie_rc_delay", setup_pcie_rc_delay);
-
-/* PCI initialization entry point, called by subsys_initcall. */
-int __init pcibios_init(void)
-{
- resource_size_t offset;
- LIST_HEAD(resources);
- int next_busno;
- struct pci_host_bridge *bridge;
- int i;
-
- tile_pci_init();
-
- if (num_rc_controllers == 0)
- return 0;
-
- /*
- * Delay a bit in case devices aren't ready. Some devices are
- * known to require at least 20ms here, but we use a more
- * conservative value.
- */
- msleep(250);
-
- /* Scan all of the recorded PCI controllers. */
- for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
- struct pci_controller *controller = &pci_controllers[i];
- gxio_trio_context_t *trio_context = controller->trio;
- TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
- TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
- struct pci_bus *bus;
- unsigned int reg_offset;
- unsigned int class_code_revision;
- int trio_index;
- int mac;
- int ret;
-
- if (trio_context->fd < 0)
- continue;
-
- trio_index = controller->trio_index;
- mac = controller->mac;
-
- /*
- * Check for PCIe link-up status to decide if we need
- * to force the link to come up.
- */
- reg_offset =
- (TRIO_PCIE_INTFC_PORT_STATUS <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- port_status.word =
- __gxio_mmio_read(trio_context->mmio_base_mac +
- reg_offset);
- if (!port_status.dl_up) {
- if (rc_delay[trio_index][mac]) {
- pr_info("Delaying PCIe RC TRIO init %d sec on MAC %d on TRIO %d\n",
- rc_delay[trio_index][mac], mac,
- trio_index);
- msleep(rc_delay[trio_index][mac] * 1000);
- }
- ret = gxio_trio_force_rc_link_up(trio_context, mac);
- if (ret < 0)
- pr_err("PCI: PCIE_FORCE_LINK_UP failure, MAC %d on TRIO %d\n",
- mac, trio_index);
- }
-
- pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n",
- i, trio_index, controller->mac);
-
- /* Delay the bus probe if needed. */
- if (rc_delay[trio_index][mac]) {
- pr_info("Delaying PCIe RC bus enumerating %d sec on MAC %d on TRIO %d\n",
- rc_delay[trio_index][mac], mac, trio_index);
- msleep(rc_delay[trio_index][mac] * 1000);
- } else {
- /*
- * Wait a bit here because some EP devices
- * take longer to come up.
- */
- msleep(1000);
- }
-
- /* Check for PCIe link-up status again. */
- port_status.word =
- __gxio_mmio_read(trio_context->mmio_base_mac +
- reg_offset);
- if (!port_status.dl_up) {
- if (pcie_ports[trio_index].ports[mac].removable) {
- pr_info("PCI: link is down, MAC %d on TRIO %d\n",
- mac, trio_index);
- pr_info("This is expected if no PCIe card is connected to this link\n");
- } else
- pr_err("PCI: link is down, MAC %d on TRIO %d\n",
- mac, trio_index);
- continue;
- }
-
- /*
- * Ensure that the link can come out of L1 power down state.
- * Strictly speaking, this is needed only in the case of
- * heavy RC-initiated DMAs.
- */
- reg_offset =
- (TRIO_PCIE_INTFC_TX_FIFO_CTL <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
- tx_fifo_ctl.word =
- __gxio_mmio_read(trio_context->mmio_base_mac +
- reg_offset);
- tx_fifo_ctl.min_p_credits = 0;
- __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
- tx_fifo_ctl.word);
-
- /*
- * Change the device ID so that Linux bus crawl doesn't confuse
- * the internal bridge with any Tilera endpoints.
- */
- reg_offset =
- (TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
- (TILERA_GX36_RC_DEV_ID <<
- TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
- TILERA_VENDOR_ID);
-
- /* Set the internal P2P bridge class code. */
- reg_offset =
- (TRIO_PCIE_RC_REVISION_ID <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
- TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- class_code_revision =
- __gxio_mmio_read32(trio_context->mmio_base_mac +
- reg_offset);
- class_code_revision = (class_code_revision & 0xff) |
- (PCI_CLASS_BRIDGE_PCI << 16);
-
- __gxio_mmio_write32(trio_context->mmio_base_mac +
- reg_offset, class_code_revision);
-
-#ifdef USE_SHARED_PCIE_CONFIG_REGION
-
- /* Map in the MMIO space for the PIO region. */
- offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
- (((unsigned long long)mac) <<
- TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
-
-#else
-
- /* Alloc a PIO region for PCI config access per MAC. */
- ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
- if (ret < 0) {
- pr_err("PCI: PCI CFG PIO alloc failure for mac %d on TRIO %d, give up\n",
- mac, trio_index);
-
- continue;
- }
-
- trio_context->pio_cfg_index[mac] = ret;
-
- /* For PIO CFG, the bus_address_hi parameter is 0. */
- ret = gxio_trio_init_pio_region_aux(trio_context,
- trio_context->pio_cfg_index[mac],
- mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
- if (ret < 0) {
- pr_err("PCI: PCI CFG PIO init failure for mac %d on TRIO %d, give up\n",
- mac, trio_index);
-
- continue;
- }
-
- offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
- (((unsigned long long)mac) <<
- TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
-
-#endif
-
- /*
- * To save VMALLOC space, we take advantage of the fact that
- * bit 29 in the PIO CFG address format is reserved 0. With
- * TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30,
- * this cuts VMALLOC space usage from 1GB to 512MB per mac.
- */
- trio_context->mmio_base_pio_cfg[mac] =
- iorpc_ioremap(trio_context->fd, offset, (1UL <<
- (TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1)));
- if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
- pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
- mac, trio_index);
-
- continue;
- }
-
- /* Initialize the PCIe interrupts. */
- if (tile_init_irqs(controller)) {
- pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
- mac, trio_index);
-
- continue;
- }
-
- /*
- * The PCI memory resource is located above the PA space.
- * The memory range for the PCI root bus should not overlap
- * with the physical RAM.
- */
- pci_add_resource_offset(&resources, &controller->mem_space,
- controller->mem_offset);
- pci_add_resource(&resources, &controller->io_space);
- controller->first_busno = next_busno;
-
- bridge = pci_alloc_host_bridge(0);
- if (!bridge)
- break;
-
- list_splice_init(&resources, &bridge->windows);
- bridge->dev.parent = NULL;
- bridge->sysdata = controller;
- bridge->busnr = next_busno;
- bridge->ops = controller->ops;
- bridge->swizzle_irq = pci_common_swizzle;
- bridge->map_irq = tile_map_irq;
-
- pci_scan_root_bus_bridge(bridge);
- bus = bridge->bus;
- controller->root_bus = bus;
- next_busno = bus->busn_res.end + 1;
- }
-
- /*
- * This comes from the generic Linux PCI driver.
- *
- * It allocates all of the resources (I/O memory, etc)
- * associated with the devices read in above.
- */
- pci_assign_unassigned_resources();
-
- /* Record the I/O resources in the PCI controller structure. */
- for (i = 0; i < num_rc_controllers; i++) {
- struct pci_controller *controller = &pci_controllers[i];
- gxio_trio_context_t *trio_context = controller->trio;
- struct pci_bus *root_bus = pci_controllers[i].root_bus;
- int ret;
- int j;
-
- /*
- * Skip controllers that are not properly initialized or
- * have down links.
- */
- if (root_bus == NULL)
- continue;
-
- /* Configure the max_payload_size values for this domain. */
- fixup_read_and_payload_sizes(controller);
-
- /* Alloc a PIO region for PCI memory access for each RC port. */
- ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
- if (ret < 0) {
- pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, give up\n",
- controller->trio_index, controller->mac);
-
- continue;
- }
-
- controller->pio_mem_index = ret;
-
- /*
- * For PIO MEM, the bus_address_hi parameter is hard-coded 0
- * because we always assign 32-bit PCI bus BAR ranges.
- */
- ret = gxio_trio_init_pio_region_aux(trio_context,
- controller->pio_mem_index,
- controller->mac,
- 0,
- 0);
- if (ret < 0) {
- pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, give up\n",
- controller->trio_index, controller->mac);
-
- continue;
- }
-
-#ifdef CONFIG_TILE_PCI_IO
- /*
- * Alloc a PIO region for PCI I/O space access for each RC port.
- */
- ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
- if (ret < 0) {
- pr_err("PCI: I/O PIO alloc failure on TRIO %d mac %d, give up\n",
- controller->trio_index, controller->mac);
-
- continue;
- }
-
- controller->pio_io_index = ret;
-
- /*
- * For PIO IO, the bus_address_hi parameter is hard-coded 0
- * because PCI I/O address space is 32-bit.
- */
- ret = gxio_trio_init_pio_region_aux(trio_context,
- controller->pio_io_index,
- controller->mac,
- 0,
- HV_TRIO_PIO_FLAG_IO_SPACE);
- if (ret < 0) {
- pr_err("PCI: I/O PIO init failure on TRIO %d mac %d, give up\n",
- controller->trio_index, controller->mac);
-
- continue;
- }
-#endif
-
- /*
- * Configure a Mem-Map region for each memory controller so
- * that Linux can map all of its PA space to the PCI bus.
- * Use the IOMMU to handle hash-for-home memory.
- */
- for_each_online_node(j) {
- unsigned long start_pfn = node_start_pfn[j];
- unsigned long end_pfn = node_end_pfn[j];
- unsigned long nr_pages = end_pfn - start_pfn;
-
- ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
- 0);
- if (ret < 0) {
- pr_err("PCI: Mem-Map alloc failure on TRIO %d mac %d for MC %d, give up\n",
- controller->trio_index, controller->mac,
- j);
-
- goto alloc_mem_map_failed;
- }
-
- controller->mem_maps[j] = ret;
-
- /*
- * Initialize the Mem-Map and the I/O MMU so that all
- * the physical memory can be accessed by the endpoint
- * devices. The base bus address is set to the base CPA
- * of this memory controller plus an offset (see pci.h).
- * The region's base VA is set to the base CPA. The
- * I/O MMU table essentially translates the CPA to
- * the real PA. Implicitly, for node 0, we create
- * a separate Mem-Map region that serves as the inbound
- * window for legacy 32-bit devices. This is a direct
- * map of the low 4GB CPA space.
- */
- ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
- controller->mem_maps[j],
- start_pfn << PAGE_SHIFT,
- nr_pages << PAGE_SHIFT,
- trio_context->asid,
- controller->mac,
- (start_pfn << PAGE_SHIFT) +
- TILE_PCI_MEM_MAP_BASE_OFFSET,
- j,
- GXIO_TRIO_ORDER_MODE_UNORDERED);
- if (ret < 0) {
- pr_err("PCI: Mem-Map init failure on TRIO %d mac %d for MC %d, give up\n",
- controller->trio_index, controller->mac,
- j);
-
- goto alloc_mem_map_failed;
- }
- continue;
-
-alloc_mem_map_failed:
- break;
- }
-
- pci_bus_add_devices(root_bus);
- }
-
- return 0;
-}
-subsys_initcall(pcibios_init);
-
-/* Process any "pci=" kernel boot arguments. */
-char *__init pcibios_setup(char *str)
-{
- if (!strcmp(str, "off")) {
- pci_probe = 0;
- return NULL;
- }
- return str;
-}
-
-/*
- * Called for each device after PCI setup is done.
- * We initialize the PCI device capabilities conservatively, assuming that
- * all devices can only address the 32-bit DMA space. The exception here is
- * that the device dma_offset is set to the value that matches the 64-bit
- * capable devices. This is OK because dma_offset is not used by legacy
- * dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops.
- * This implementation matches the kernel design of setting PCI devices'
- * coherent_dma_mask to 0xffffffffull by default, allowing the device drivers
- * to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)).
- */
-static void pcibios_fixup_final(struct pci_dev *pdev)
-{
- set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops);
- set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
- pdev->dev.archdata.max_direct_dma_addr =
- TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
- pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
-
-/* Map a PCI MMIO bus address into VA space. */
-void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
-{
- struct pci_controller *controller = NULL;
- resource_size_t bar_start;
- resource_size_t bar_end;
- resource_size_t offset;
- resource_size_t start;
- resource_size_t end;
- int trio_fd;
- int i;
-
- start = phys_addr;
- end = phys_addr + size - 1;
-
- /*
- * By searching phys_addr in each controller's mem_space, we can
- * determine the controller that should accept the PCI memory access.
- */
- for (i = 0; i < num_rc_controllers; i++) {
- /*
- * Skip controllers that are not properly initialized or
- * have down links.
- */
- if (pci_controllers[i].root_bus == NULL)
- continue;
-
- bar_start = pci_controllers[i].mem_space.start;
- bar_end = pci_controllers[i].mem_space.end;
-
- if ((start >= bar_start) && (end <= bar_end)) {
- controller = &pci_controllers[i];
- break;
- }
- }
-
- if (controller == NULL)
- return NULL;
-
- trio_fd = controller->trio->fd;
-
- /* Convert the resource start to the bus address offset. */
- start = phys_addr - controller->mem_offset;
-
- offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
-
- /* We need to keep the PCI bus address's in-page offset in the VA. */
- return iorpc_ioremap(trio_fd, offset, size) +
- (start & (PAGE_SIZE - 1));
-}
-EXPORT_SYMBOL(ioremap);
-
-#ifdef CONFIG_TILE_PCI_IO
-/* Map a PCI I/O address into VA space. */
-void __iomem *ioport_map(unsigned long port, unsigned int size)
-{
- struct pci_controller *controller = NULL;
- resource_size_t bar_start;
- resource_size_t bar_end;
- resource_size_t offset;
- resource_size_t start;
- resource_size_t end;
- int trio_fd;
- int i;
-
- start = port;
- end = port + size - 1;
-
- /*
- * By searching the port in each controller's io_space, we can
- * determine the controller that should accept the PCI I/O access.
- */
- for (i = 0; i < num_rc_controllers; i++) {
- /*
- * Skip controllers that are not properly initialized or
- * have down links.
- */
- if (pci_controllers[i].root_bus == NULL)
- continue;
-
- bar_start = pci_controllers[i].io_space.start;
- bar_end = pci_controllers[i].io_space.end;
-
- if ((start >= bar_start) && (end <= bar_end)) {
- controller = &pci_controllers[i];
- break;
- }
- }
-
- if (controller == NULL)
- return NULL;
-
- trio_fd = controller->trio->fd;
-
- /* Convert the resource start to the bus address offset. */
- port -= controller->io_space.start;
-
- offset = HV_TRIO_PIO_OFFSET(controller->pio_io_index) + port;
-
- /* We need to keep the PCI bus address's in-page offset in the VA. */
- return iorpc_ioremap(trio_fd, offset, size) + (port & (PAGE_SIZE - 1));
-}
-EXPORT_SYMBOL(ioport_map);
-
-void ioport_unmap(void __iomem *addr)
-{
- iounmap(addr);
-}
-EXPORT_SYMBOL(ioport_unmap);
-#endif
-
-void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
-{
- iounmap(addr);
-}
-EXPORT_SYMBOL(pci_iounmap);
-
-/****************************************************************
- *
- * Tile PCI config space read/write routines
- *
- ****************************************************************/
-
-/*
- * These are the normal read and write ops
- * These are expanded with macros from pci_bus_read_config_byte() etc.
- *
- * devfn is the combined PCI device & function.
- *
- * offset is in bytes, from the start of config space for the
- * specified bus & device.
- */
-static int tile_cfg_read(struct pci_bus *bus, unsigned int devfn, int offset,
- int size, u32 *val)
-{
- struct pci_controller *controller = bus->sysdata;
- gxio_trio_context_t *trio_context = controller->trio;
- int busnum = bus->number & 0xff;
- int device = PCI_SLOT(devfn);
- int function = PCI_FUNC(devfn);
- int config_type = 1;
- TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
- void *mmio_addr;
-
- /*
- * Map all accesses to the local device on root bus into the
- * MMIO space of the MAC. Accesses to the downstream devices
- * go to the PIO space.
- */
- if (pci_is_root_bus(bus)) {
- if (device == 0) {
- /*
- * This is the internal downstream P2P bridge,
- * access directly.
- */
- unsigned int reg_offset;
-
- reg_offset = ((offset & 0xFFF) <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
- << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (controller->mac <<
- TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- mmio_addr = trio_context->mmio_base_mac + reg_offset;
-
- goto valid_device;
-
- } else {
- /*
- * We fake an empty device for (device > 0),
- * since there is only one device on bus 0.
- */
- goto invalid_device;
- }
- }
-
- /*
- * Accesses to the directly attached device have to be
- * sent as type-0 configs.
- */
- if (busnum == (controller->first_busno + 1)) {
- /*
- * There is only one device off of our built-in P2P bridge.
- */
- if (device != 0)
- goto invalid_device;
-
- config_type = 0;
- }
-
- cfg_addr.word = 0;
- cfg_addr.reg_addr = (offset & 0xFFF);
- cfg_addr.fn = function;
- cfg_addr.dev = device;
- cfg_addr.bus = busnum;
- cfg_addr.type = config_type;
-
- /*
- * Note that we don't set the mac field in cfg_addr because the
- * mapping is per port.
- */
- mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
- cfg_addr.word;
-
-valid_device:
-
- switch (size) {
- case 4:
- *val = __gxio_mmio_read32(mmio_addr);
- break;
-
- case 2:
- *val = __gxio_mmio_read16(mmio_addr);
- break;
-
- case 1:
- *val = __gxio_mmio_read8(mmio_addr);
- break;
-
- default:
- return PCIBIOS_FUNC_NOT_SUPPORTED;
- }
-
- TRACE_CFG_RD(size, *val, busnum, device, function, offset);
-
- return 0;
-
-invalid_device:
-
- switch (size) {
- case 4:
- *val = 0xFFFFFFFF;
- break;
-
- case 2:
- *val = 0xFFFF;
- break;
-
- case 1:
- *val = 0xFF;
- break;
-
- default:
- return PCIBIOS_FUNC_NOT_SUPPORTED;
- }
-
- return 0;
-}
-
-
-/*
- * See tile_cfg_read() for relevant comments.
- * Note that "val" is the value to write, not a pointer to that value.
- */
-static int tile_cfg_write(struct pci_bus *bus, unsigned int devfn, int offset,
- int size, u32 val)
-{
- struct pci_controller *controller = bus->sysdata;
- gxio_trio_context_t *trio_context = controller->trio;
- int busnum = bus->number & 0xff;
- int device = PCI_SLOT(devfn);
- int function = PCI_FUNC(devfn);
- int config_type = 1;
- TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
- void *mmio_addr;
- u32 val_32 = (u32)val;
- u16 val_16 = (u16)val;
- u8 val_8 = (u8)val;
-
- /*
- * Map all accesses to the local device on root bus into the
- * MMIO space of the MAC. Accesses to the downstream devices
- * go to the PIO space.
- */
- if (pci_is_root_bus(bus)) {
- if (device == 0) {
- /*
- * This is the internal downstream P2P bridge,
- * access directly.
- */
- unsigned int reg_offset;
-
- reg_offset = ((offset & 0xFFF) <<
- TRIO_CFG_REGION_ADDR__REG_SHIFT) |
- (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
- << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
- (controller->mac <<
- TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
-
- mmio_addr = trio_context->mmio_base_mac + reg_offset;
-
- goto valid_device;
-
- } else {
- /*
- * We fake an empty device for (device > 0),
- * since there is only one device on bus 0.
- */
- goto invalid_device;
- }
- }
-
- /*
- * Accesses to the directly attached device have to be
- * sent as type-0 configs.
- */
- if (busnum == (controller->first_busno + 1)) {
- /*
- * There is only one device off of our built-in P2P bridge.
- */
- if (device != 0)
- goto invalid_device;
-
- config_type = 0;
- }
-
- cfg_addr.word = 0;
- cfg_addr.reg_addr = (offset & 0xFFF);
- cfg_addr.fn = function;
- cfg_addr.dev = device;
- cfg_addr.bus = busnum;
- cfg_addr.type = config_type;
-
- /*
- * Note that we don't set the mac field in cfg_addr because the
- * mapping is per port.
- */
- mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
- cfg_addr.word;
-
-valid_device:
-
- switch (size) {
- case 4:
- __gxio_mmio_write32(mmio_addr, val_32);
- TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
- break;
-
- case 2:
- __gxio_mmio_write16(mmio_addr, val_16);
- TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
- break;
-
- case 1:
- __gxio_mmio_write8(mmio_addr, val_8);
- TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
- break;
-
- default:
- return PCIBIOS_FUNC_NOT_SUPPORTED;
- }
-
-invalid_device:
-
- return 0;
-}
-
-
-static struct pci_ops tile_cfg_ops = {
- .read = tile_cfg_read,
- .write = tile_cfg_write,
-};
-
-
-/* MSI support starts here. */
-static unsigned int tilegx_msi_startup(struct irq_data *d)
-{
- if (irq_data_get_msi_desc(d))
- pci_msi_unmask_irq(d);
-
- return 0;
-}
-
-static void tilegx_msi_ack(struct irq_data *d)
-{
- __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
-}
-
-static void tilegx_msi_mask(struct irq_data *d)
-{
- pci_msi_mask_irq(d);
- __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
-}
-
-static void tilegx_msi_unmask(struct irq_data *d)
-{
- __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
- pci_msi_unmask_irq(d);
-}
-
-static struct irq_chip tilegx_msi_chip = {
- .name = "tilegx_msi",
- .irq_startup = tilegx_msi_startup,
- .irq_ack = tilegx_msi_ack,
- .irq_mask = tilegx_msi_mask,
- .irq_unmask = tilegx_msi_unmask,
-
- /* TBD: support set_affinity. */
-};
-
-int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
-{
- struct pci_controller *controller;
- gxio_trio_context_t *trio_context;
- struct msi_msg msg;
- int default_irq;
- uint64_t mem_map_base;
- uint64_t mem_map_limit;
- u64 msi_addr;
- int mem_map;
- int cpu;
- int irq;
- int ret;
-
- irq = irq_alloc_hwirq(-1);
- if (!irq)
- return -ENOSPC;
-
- /*
- * Since we use a 64-bit Mem-Map to accept the MSI write, we fail
- * devices that are not capable of generating a 64-bit message address.
- * These devices will fall back to using the legacy interrupts.
- * Most PCIe endpoint devices do support 64-bit message addressing.
- */
- if (desc->msi_attrib.is_64 == 0) {
- dev_info(&pdev->dev, "64-bit MSI message address not supported, falling back to legacy interrupts\n");
-
- ret = -ENOMEM;
- goto is_64_failure;
- }
-
- default_irq = desc->msi_attrib.default_irq;
- controller = irq_get_handler_data(default_irq);
-
- BUG_ON(!controller);
-
- trio_context = controller->trio;
-
- /*
- * Allocate a scatter-queue that will accept the MSI write and
- * trigger the TILE-side interrupts. We use the scatter-queue regions
- * before the mem map regions, because the latter are needed by more
- * applications.
- */
- mem_map = gxio_trio_alloc_scatter_queues(trio_context, 1, 0, 0);
- if (mem_map >= 0) {
- TRIO_MAP_SQ_DOORBELL_FMT_t doorbell_template = {{
- .pop = 0,
- .doorbell = 1,
- }};
-
- mem_map += TRIO_NUM_MAP_MEM_REGIONS;
- mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
- mem_map * MEM_MAP_INTR_REGION_SIZE;
- mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
-
- msi_addr = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 8;
- msg.data = (unsigned int)doorbell_template.word;
- } else {
- /* SQ regions are out, allocate from map mem regions. */
- mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
- if (mem_map < 0) {
- dev_info(&pdev->dev, "%s Mem-Map alloc failure - failed to initialize MSI interrupts - falling back to legacy interrupts\n",
- desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
- ret = -ENOMEM;
- goto msi_mem_map_alloc_failure;
- }
-
- mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
- mem_map * MEM_MAP_INTR_REGION_SIZE;
- mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
-
- msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 -
- TRIO_MAP_MEM_REG_INT0;
-
- msg.data = mem_map;
- }
-
- /* We try to distribute different IRQs to different tiles. */
- cpu = tile_irq_cpu(irq);
-
- /*
- * Now call up to the HV to configure the MSI interrupt and
- * set up the IPI binding.
- */
- ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
- KERNEL_PL, irq, controller->mac,
- mem_map, mem_map_base, mem_map_limit,
- trio_context->asid);
- if (ret < 0) {
- dev_info(&pdev->dev, "HV MSI config failed\n");
-
- goto hv_msi_config_failure;
- }
-
- irq_set_msi_desc(irq, desc);
-
- msg.address_hi = msi_addr >> 32;
- msg.address_lo = msi_addr & 0xffffffff;
-
- pci_write_msi_msg(irq, &msg);
- irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
- irq_set_handler_data(irq, controller);
-
- return 0;
-
-hv_msi_config_failure:
- /* Free mem-map */
-msi_mem_map_alloc_failure:
-is_64_failure:
- irq_free_hwirq(irq);
- return ret;
-}
-
-void arch_teardown_msi_irq(unsigned int irq)
-{
- irq_free_hwirq(irq);
-}
diff --git a/arch/tile/kernel/perf_event.c b/arch/tile/kernel/perf_event.c
deleted file mode 100644
index 6394c1ccb68e..000000000000
--- a/arch/tile/kernel/perf_event.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-/*
- * Copyright 2014 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- * Perf_events support for Tile processor.
- *
- * This code is based upon the x86 perf event
- * code, which is:
- *
- * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
- * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
- * Copyright (C) 2009 Jaswinder Singh Rajput
- * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
- * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
- * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
- * Copyright (C) 2009 Google, Inc., Stephane Eranian
- */
-
-#include <linux/kprobes.h>
-#include <linux/kernel.h>
-#include <linux/kdebug.h>
-#include <linux/mutex.h>
-#include <linux/bitmap.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/perf_event.h>
-#include <linux/atomic.h>
-#include <asm/traps.h>
-#include <asm/stack.h>
-#include <asm/pmc.h>
-#include <hv/hypervisor.h>
-
-#define TILE_MAX_COUNTERS 4
-
-#define PERF_COUNT_0_IDX 0
-#define PERF_COUNT_1_IDX 1
-#define AUX_PERF_COUNT_0_IDX 2
-#define AUX_PERF_COUNT_1_IDX 3
-
-struct cpu_hw_events {
- int n_events;
- struct perf_event *events[TILE_MAX_COUNTERS]; /* counter order */
- struct perf_event *event_list[TILE_MAX_COUNTERS]; /* enabled
- order */
- int assign[TILE_MAX_COUNTERS];
- unsigned long active_mask[BITS_TO_LONGS(TILE_MAX_COUNTERS)];
- unsigned long used_mask;
-};
-
-/* TILE arch specific performance monitor unit */
-struct tile_pmu {
- const char *name;
- int version;
- const int *hw_events; /* generic hw events table */
- /* generic hw cache events table */
- const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX];
- int (*map_hw_event)(u64); /*method used to map
- hw events */
- int (*map_cache_event)(u64); /*method used to map
- cache events */
-
- u64 max_period; /* max sampling period */
- u64 cntval_mask; /* counter width mask */
- int cntval_bits; /* counter width */
- int max_events; /* max generic hw events
- in map */
- int num_counters; /* number base + aux counters */
- int num_base_counters; /* number base counters */
-};
-
-DEFINE_PER_CPU(u64, perf_irqs);
-static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-#define TILE_OP_UNSUPP (-1)
-
-#ifndef __tilegx__
-/* TILEPro hardware events map */
-static const int tile_hw_event_map[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = 0x01, /* ONE */
- [PERF_COUNT_HW_INSTRUCTIONS] = 0x06, /* MP_BUNDLE_RETIRED */
- [PERF_COUNT_HW_CACHE_REFERENCES] = TILE_OP_UNSUPP,
- [PERF_COUNT_HW_CACHE_MISSES] = TILE_OP_UNSUPP,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x16, /*
- MP_CONDITIONAL_BRANCH_ISSUED */
- [PERF_COUNT_HW_BRANCH_MISSES] = 0x14, /*
- MP_CONDITIONAL_BRANCH_MISSPREDICT */
- [PERF_COUNT_HW_BUS_CYCLES] = TILE_OP_UNSUPP,
-};
-#else
-/* TILEGx hardware events map */
-static const int tile_hw_event_map[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = 0x181, /* ONE */
- [PERF_COUNT_HW_INSTRUCTIONS] = 0xdb, /* INSTRUCTION_BUNDLE */
- [PERF_COUNT_HW_CACHE_REFERENCES] = TILE_OP_UNSUPP,
- [PERF_COUNT_HW_CACHE_MISSES] = TILE_OP_UNSUPP,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0xd9, /*
- COND_BRANCH_PRED_CORRECT */
- [PERF_COUNT_HW_BRANCH_MISSES] = 0xda, /*
- COND_BRANCH_PRED_INCORRECT */
- [PERF_COUNT_HW_BUS_CYCLES] = TILE_OP_UNSUPP,
-};
-#endif
-
-#define C(x) PERF_COUNT_HW_CACHE_##x
-
-/*
- * Generalized hw caching related hw_event table, filled
- * in on a per model basis. A value of -1 means
- * 'not supported', any other value means the
- * raw hw_event ID.
- */
-#ifndef __tilegx__
-/* TILEPro hardware cache event map */
-static const int tile_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-[C(L1D)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = 0x21, /* RD_MISS */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = 0x22, /* WR_MISS */
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0x12, /* MP_ICACHE_HIT_ISSUED */
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(DTLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0x1d, /* TLB_CNT */
- [C(RESULT_MISS)] = 0x20, /* TLB_EXCEPTION */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0x13, /* MP_ITLB_HIT_ISSUED */
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-};
-#else
-/* TILEGx hardware events map */
-static const int tile_cache_event_map[PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-[C(L1D)] = {
- /*
- * Like some other architectures (e.g. ARM), the performance
- * counters don't differentiate between read and write
- * accesses/misses, so this isn't strictly correct, but it's the
- * best we can do. Writes and reads get combined.
- */
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = 0x44, /* RD_MISS */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = 0x45, /* WR_MISS */
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(L1I)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(LL)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(DTLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = 0x40, /* TLB_CNT */
- [C(RESULT_MISS)] = 0x43, /* TLB_EXCEPTION */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = 0x40, /* TLB_CNT */
- [C(RESULT_MISS)] = 0x43, /* TLB_EXCEPTION */
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(ITLB)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = 0xd4, /* ITLB_MISS_INT */
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = 0xd4, /* ITLB_MISS_INT */
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-[C(BPU)] = {
- [C(OP_READ)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_WRITE)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
- [C(OP_PREFETCH)] = {
- [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
- [C(RESULT_MISS)] = TILE_OP_UNSUPP,
- },
-},
-};
-#endif
-
-static atomic_t tile_active_events;
-static DEFINE_MUTEX(perf_intr_reserve_mutex);
-
-static int tile_map_hw_event(u64 config);
-static int tile_map_cache_event(u64 config);
-
-static int tile_pmu_handle_irq(struct pt_regs *regs, int fault);
-
-/*
- * To avoid new_raw_count getting larger then pre_raw_count
- * in tile_perf_event_update(), we limit the value of max_period to 2^31 - 1.
- */
-static const struct tile_pmu tilepmu = {
-#ifndef __tilegx__
- .name = "tilepro",
-#else
- .name = "tilegx",
-#endif
- .max_events = ARRAY_SIZE(tile_hw_event_map),
- .map_hw_event = tile_map_hw_event,
- .hw_events = tile_hw_event_map,
- .map_cache_event = tile_map_cache_event,
- .cache_events = &tile_cache_event_map,
- .cntval_bits = 32,
- .cntval_mask = (1ULL << 32) - 1,
- .max_period = (1ULL << 31) - 1,
- .num_counters = TILE_MAX_COUNTERS,
- .num_base_counters = TILE_BASE_COUNTERS,
-};
-
-static const struct tile_pmu *tile_pmu __read_mostly;
-
-/*
- * Check whether perf event is enabled.
- */
-int tile_perf_enabled(void)
-{
- return atomic_read(&tile_active_events) != 0;
-}
-
-/*
- * Read Performance Counters.
- */
-static inline u64 read_counter(int idx)
-{
- u64 val = 0;
-
- /* __insn_mfspr() only takes an immediate argument */
- switch (idx) {
- case PERF_COUNT_0_IDX:
- val = __insn_mfspr(SPR_PERF_COUNT_0);
- break;
- case PERF_COUNT_1_IDX:
- val = __insn_mfspr(SPR_PERF_COUNT_1);
- break;
- case AUX_PERF_COUNT_0_IDX:
- val = __insn_mfspr(SPR_AUX_PERF_COUNT_0);
- break;
- case AUX_PERF_COUNT_1_IDX:
- val = __insn_mfspr(SPR_AUX_PERF_COUNT_1);
- break;
- default:
- WARN_ON_ONCE(idx > AUX_PERF_COUNT_1_IDX ||
- idx < PERF_COUNT_0_IDX);
- }
-
- return val;
-}
-
-/*
- * Write Performance Counters.
- */
-static inline void write_counter(int idx, u64 value)
-{
- /* __insn_mtspr() only takes an immediate argument */
- switch (idx) {
- case PERF_COUNT_0_IDX:
- __insn_mtspr(SPR_PERF_COUNT_0, value);
- break;
- case PERF_COUNT_1_IDX:
- __insn_mtspr(SPR_PERF_COUNT_1, value);
- break;
- case AUX_PERF_COUNT_0_IDX:
- __insn_mtspr(SPR_AUX_PERF_COUNT_0, value);
- break;
- case AUX_PERF_COUNT_1_IDX:
- __insn_mtspr(SPR_AUX_PERF_COUNT_1, value);
- break;
- default:
- WARN_ON_ONCE(idx > AUX_PERF_COUNT_1_IDX ||
- idx < PERF_COUNT_0_IDX);
- }
-}
-
-/*
- * Enable performance event by setting
- * Performance Counter Control registers.
- */
-static inline void tile_pmu_enable_event(struct perf_event *event)
-{
- struct hw_perf_event *hwc = &event->hw;
- unsigned long cfg, mask;
- int shift, idx = hwc->idx;
-
- /*
- * prevent early activation from tile_pmu_start() in hw_perf_enable
- */
-
- if (WARN_ON_ONCE(idx == -1))
- return;
-
- if (idx < tile_pmu->num_base_counters)
- cfg = __insn_mfspr(SPR_PERF_COUNT_CTL);
- else
- cfg = __insn_mfspr(SPR_AUX_PERF_COUNT_CTL);
-
- switch (idx) {
- case PERF_COUNT_0_IDX:
- case AUX_PERF_COUNT_0_IDX:
- mask = TILE_EVENT_MASK;
- shift = 0;
- break;
- case PERF_COUNT_1_IDX:
- case AUX_PERF_COUNT_1_IDX:
- mask = TILE_EVENT_MASK << 16;
- shift = 16;
- break;
- default:
- WARN_ON_ONCE(idx < PERF_COUNT_0_IDX ||
- idx > AUX_PERF_COUNT_1_IDX);
- return;
- }
-
- /* Clear mask bits to enable the event. */
- cfg &= ~mask;
- cfg |= hwc->config << shift;
-
- if (idx < tile_pmu->num_base_counters)
- __insn_mtspr(SPR_PERF_COUNT_CTL, cfg);
- else
- __insn_mtspr(SPR_AUX_PERF_COUNT_CTL, cfg);
-}
-
-/*
- * Disable performance event by clearing
- * Performance Counter Control registers.
- */
-static inline void tile_pmu_disable_event(struct perf_event *event)
-{
- struct hw_perf_event *hwc = &event->hw;
- unsigned long cfg, mask;
- int idx = hwc->idx;
-
- if (idx == -1)
- return;
-
- if (idx < tile_pmu->num_base_counters)
- cfg = __insn_mfspr(SPR_PERF_COUNT_CTL);
- else
- cfg = __insn_mfspr(SPR_AUX_PERF_COUNT_CTL);
-
- switch (idx) {
- case PERF_COUNT_0_IDX:
- case AUX_PERF_COUNT_0_IDX:
- mask = TILE_PLM_MASK;
- break;
- case PERF_COUNT_1_IDX:
- case AUX_PERF_COUNT_1_IDX:
- mask = TILE_PLM_MASK << 16;
- break;
- default:
- WARN_ON_ONCE(idx < PERF_COUNT_0_IDX ||
- idx > AUX_PERF_COUNT_1_IDX);
- return;
- }
-
- /* Set mask bits to disable the event. */
- cfg |= mask;
-
- if (idx < tile_pmu->num_base_counters)
- __insn_mtspr(SPR_PERF_COUNT_CTL, cfg);
- else
- __insn_mtspr(SPR_AUX_PERF_COUNT_CTL, cfg);
-}
-
-/*
- * Propagate event elapsed time into the generic event.
- * Can only be executed on the CPU where the event is active.
- * Returns the delta events processed.
- */
-static u64 tile_perf_event_update(struct perf_event *event)
-{
- struct hw_perf_event *hwc = &event->hw;
- int shift = 64 - tile_pmu->cntval_bits;
- u64 prev_raw_count, new_raw_count;
- u64 oldval;
- int idx = hwc->idx;
- u64 delta;
-
- /*
- * Careful: an NMI might modify the previous event value.
- *
- * Our tactic to handle this is to first atomically read and
- * exchange a new raw count - then add that new-prev delta
- * count to the generic event atomically:
- */
-again:
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = read_counter(idx);
-
- oldval = local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count);
- if (oldval != prev_raw_count)
- goto again;
-
- /*
- * Now we have the new raw value and have updated the prev
- * timestamp already. We can now calculate the elapsed delta
- * (event-)time and add that to the generic event.
- *
- * Careful, not all hw sign-extends above the physical width
- * of the count.
- */
- delta = (new_raw_count << shift) - (prev_raw_count << shift);
- delta >>= shift;
-
- local64_add(delta, &event->count);
- local64_sub(delta, &hwc->period_left);
-
- return new_raw_count;
-}
-
-/*
- * Set the next IRQ period, based on the hwc->period_left value.
- * To be called with the event disabled in hw:
- */
-static int tile_event_set_period(struct perf_event *event)
-{
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
- s64 left = local64_read(&hwc->period_left);
- s64 period = hwc->sample_period;
- int ret = 0;
-
- /*
- * If we are way outside a reasonable range then just skip forward:
- */
- if (unlikely(left <= -period)) {
- left = period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
-
- if (unlikely(left <= 0)) {
- left += period;
- local64_set(&hwc->period_left, left);
- hwc->last_period = period;
- ret = 1;
- }
- if (left > tile_pmu->max_period)
- left = tile_pmu->max_period;
-
- /*
- * The hw event starts counting from this event offset,
- * mark it to be able to extra future deltas:
- */
- local64_set(&hwc->prev_count, (u64)-left);
-
- write_counter(idx, (u64)(-left) & tile_pmu->cntval_mask);
-
- perf_event_update_userpage(event);
-
- return ret;
-}
-
-/*
- * Stop the event but do not release the PMU counter
- */
-static void tile_pmu_stop(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc = &event->hw;
- int idx = hwc->idx;
-
- if (__test_and_clear_bit(idx, cpuc->active_mask)) {
- tile_pmu_disable_event(event);
- cpuc->events[hwc->idx] = NULL;
- WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
- hwc->state |= PERF_HES_STOPPED;
- }
-
- if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
- /*
- * Drain the remaining delta count out of a event
- * that we are disabling:
- */
- tile_perf_event_update(event);
- hwc->state |= PERF_HES_UPTODATE;
- }
-}
-
-/*
- * Start an event (without re-assigning counter)
- */
-static void tile_pmu_start(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- int idx = event->hw.idx;
-
- if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
- return;
-
- if (WARN_ON_ONCE(idx == -1))
- return;
-
- if (flags & PERF_EF_RELOAD) {
- WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
- tile_event_set_period(event);
- }
-
- event->hw.state = 0;
-
- cpuc->events[idx] = event;
- __set_bit(idx, cpuc->active_mask);
-
- unmask_pmc_interrupts();
-
- tile_pmu_enable_event(event);
-
- perf_event_update_userpage(event);
-}
-
-/*
- * Add a single event to the PMU.
- *
- * The event is added to the group of enabled events
- * but only if it can be scehduled with existing events.
- */
-static int tile_pmu_add(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct hw_perf_event *hwc;
- unsigned long mask;
- int b, max_cnt;
-
- hwc = &event->hw;
-
- /*
- * We are full.
- */
- if (cpuc->n_events == tile_pmu->num_counters)
- return -ENOSPC;
-
- cpuc->event_list[cpuc->n_events] = event;
- cpuc->n_events++;
-
- hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
- if (!(flags & PERF_EF_START))
- hwc->state |= PERF_HES_ARCH;
-
- /*
- * Find first empty counter.
- */
- max_cnt = tile_pmu->num_counters;
- mask = ~cpuc->used_mask;
-
- /* Find next free counter. */
- b = find_next_bit(&mask, max_cnt, 0);
-
- /* Should not happen. */
- if (WARN_ON_ONCE(b == max_cnt))
- return -ENOSPC;
-
- /*
- * Assign counter to event.
- */
- event->hw.idx = b;
- __set_bit(b, &cpuc->used_mask);
-
- /*
- * Start if requested.
- */
- if (flags & PERF_EF_START)
- tile_pmu_start(event, PERF_EF_RELOAD);
-
- return 0;
-}
-
-/*
- * Delete a single event from the PMU.
- *
- * The event is deleted from the group of enabled events.
- * If it is the last event, disable PMU interrupt.
- */
-static void tile_pmu_del(struct perf_event *event, int flags)
-{
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- int i;
-
- /*
- * Remove event from list, compact list if necessary.
- */
- for (i = 0; i < cpuc->n_events; i++) {
- if (cpuc->event_list[i] == event) {
- while (++i < cpuc->n_events)
- cpuc->event_list[i-1] = cpuc->event_list[i];
- --cpuc->n_events;
- cpuc->events[event->hw.idx] = NULL;
- __clear_bit(event->hw.idx, &cpuc->used_mask);
- tile_pmu_stop(event, PERF_EF_UPDATE);
- break;
- }
- }
- /*
- * If there are no events left, then mask PMU interrupt.
- */
- if (cpuc->n_events == 0)
- mask_pmc_interrupts();
- perf_event_update_userpage(event);
-}
-
-/*
- * Propagate event elapsed time into the event.
- */
-static inline void tile_pmu_read(struct perf_event *event)
-{
- tile_perf_event_update(event);
-}
-
-/*
- * Map generic events to Tile PMU.
- */
-static int tile_map_hw_event(u64 config)
-{
- if (config >= tile_pmu->max_events)
- return -EINVAL;
- return tile_pmu->hw_events[config];
-}
-
-/*
- * Map generic hardware cache events to Tile PMU.
- */
-static int tile_map_cache_event(u64 config)
-{
- unsigned int cache_type, cache_op, cache_result;
- int code;
-
- if (!tile_pmu->cache_events)
- return -ENOENT;
-
- cache_type = (config >> 0) & 0xff;
- if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
- return -EINVAL;
-
- cache_op = (config >> 8) & 0xff;
- if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
- return -EINVAL;
-
- cache_result = (config >> 16) & 0xff;
- if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
- return -EINVAL;
-
- code = (*tile_pmu->cache_events)[cache_type][cache_op][cache_result];
- if (code == TILE_OP_UNSUPP)
- return -EINVAL;
-
- return code;
-}
-
-static void tile_event_destroy(struct perf_event *event)
-{
- if (atomic_dec_return(&tile_active_events) == 0)
- release_pmc_hardware();
-}
-
-static int __tile_event_init(struct perf_event *event)
-{
- struct perf_event_attr *attr = &event->attr;
- struct hw_perf_event *hwc = &event->hw;
- int code;
-
- switch (attr->type) {
- case PERF_TYPE_HARDWARE:
- code = tile_pmu->map_hw_event(attr->config);
- break;
- case PERF_TYPE_HW_CACHE:
- code = tile_pmu->map_cache_event(attr->config);
- break;
- case PERF_TYPE_RAW:
- code = attr->config & TILE_EVENT_MASK;
- break;
- default:
- /* Should not happen. */
- return -EOPNOTSUPP;
- }
-
- if (code < 0)
- return code;
-
- hwc->config = code;
- hwc->idx = -1;
-
- if (attr->exclude_user)
- hwc->config |= TILE_CTL_EXCL_USER;
-
- if (attr->exclude_kernel)
- hwc->config |= TILE_CTL_EXCL_KERNEL;
-
- if (attr->exclude_hv)
- hwc->config |= TILE_CTL_EXCL_HV;
-
- if (!hwc->sample_period) {
- hwc->sample_period = tile_pmu->max_period;
- hwc->last_period = hwc->sample_period;
- local64_set(&hwc->period_left, hwc->sample_period);
- }
- event->destroy = tile_event_destroy;
- return 0;
-}
-
-static int tile_event_init(struct perf_event *event)
-{
- int err = 0;
- perf_irq_t old_irq_handler = NULL;
-
- if (atomic_inc_return(&tile_active_events) == 1)
- old_irq_handler = reserve_pmc_hardware(tile_pmu_handle_irq);
-
- if (old_irq_handler) {
- pr_warn("PMC hardware busy (reserved by oprofile)\n");
-
- atomic_dec(&tile_active_events);
- return -EBUSY;
- }
-
- switch (event->attr.type) {
- case PERF_TYPE_RAW:
- case PERF_TYPE_HARDWARE:
- case PERF_TYPE_HW_CACHE:
- break;
-
- default:
- return -ENOENT;
- }
-
- err = __tile_event_init(event);
- if (err) {
- if (event->destroy)
- event->destroy(event);
- }
- return err;
-}
-
-static struct pmu tilera_pmu = {
- .event_init = tile_event_init,
- .add = tile_pmu_add,
- .del = tile_pmu_del,
-
- .start = tile_pmu_start,
- .stop = tile_pmu_stop,
-
- .read = tile_pmu_read,
-};
-
-/*
- * PMU's IRQ handler, PMU has 2 interrupts, they share the same handler.
- */
-int tile_pmu_handle_irq(struct pt_regs *regs, int fault)
-{
- struct perf_sample_data data;
- struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
- struct perf_event *event;
- struct hw_perf_event *hwc;
- u64 val;
- unsigned long status;
- int bit;
-
- __this_cpu_inc(perf_irqs);
-
- if (!atomic_read(&tile_active_events))
- return 0;
-
- status = pmc_get_overflow();
- pmc_ack_overflow(status);
-
- for_each_set_bit(bit, &status, tile_pmu->num_counters) {
-
- event = cpuc->events[bit];
-
- if (!event)
- continue;
-
- if (!test_bit(bit, cpuc->active_mask))
- continue;
-
- hwc = &event->hw;
-
- val = tile_perf_event_update(event);
- if (val & (1ULL << (tile_pmu->cntval_bits - 1)))
- continue;
-
- perf_sample_data_init(&data, 0, event->hw.last_period);
- if (!tile_event_set_period(event))
- continue;
-
- if (perf_event_overflow(event, &data, regs))
- tile_pmu_stop(event, 0);
- }
-
- return 0;
-}
-
-static bool __init supported_pmu(void)
-{
- tile_pmu = &tilepmu;
- return true;
-}
-
-int __init init_hw_perf_events(void)
-{
- supported_pmu();
- perf_pmu_register(&tilera_pmu, "cpu", PERF_TYPE_RAW);
- return 0;
-}
-arch_initcall(init_hw_perf_events);
-
-/* Callchain handling code. */
-
-/*
- * Tile specific backtracing code for perf_events.
- */
-static inline void perf_callchain(struct perf_callchain_entry_ctx *entry,
- struct pt_regs *regs)
-{
- struct KBacktraceIterator kbt;
- unsigned int i;
-
- /*
- * Get the address just after the "jalr" instruction that
- * jumps to the handler for a syscall. When we find this
- * address in a backtrace, we silently ignore it, which gives
- * us a one-step backtrace connection from the sys_xxx()
- * function in the kernel to the xxx() function in libc.
- * Otherwise, we lose the ability to properly attribute time
- * from the libc calls to the kernel implementations, since
- * oprofile only considers PCs from backtraces a pair at a time.
- */
- unsigned long handle_syscall_pc = handle_syscall_link_address();
-
- KBacktraceIterator_init(&kbt, NULL, regs);
- kbt.profile = 1;
-
- /*
- * The sample for the pc is already recorded. Now we are adding the
- * address of the callsites on the stack. Our iterator starts
- * with the frame of the (already sampled) call site. If our
- * iterator contained a "return address" field, we could have just
- * used it and wouldn't have needed to skip the first
- * frame. That's in effect what the arm and x86 versions do.
- * Instead we peel off the first iteration to get the equivalent
- * behavior.
- */
-
- if (KBacktraceIterator_end(&kbt))
- return;
- KBacktraceIterator_next(&kbt);
-
- /*
- * Set stack depth to 16 for user and kernel space respectively, that
- * is, total 32 stack frames.
- */
- for (i = 0; i < 16; ++i) {
- unsigned long pc;
- if (KBacktraceIterator_end(&kbt))
- break;
- pc = kbt.it.pc;
- if (pc != handle_syscall_pc)
- perf_callchain_store(entry, pc);
- KBacktraceIterator_next(&kbt);
- }
-}
-
-void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
- struct pt_regs *regs)
-{
- perf_callchain(entry, regs);
-}
-
-void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
- struct pt_regs *regs)
-{
- perf_callchain(entry, regs);
-}
diff --git a/arch/tile/kernel/pmc.c b/arch/tile/kernel/pmc.c
deleted file mode 100644
index 81cf8743a3f3..000000000000
--- a/arch/tile/kernel/pmc.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2014 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/atomic.h>
-
-#include <asm/processor.h>
-#include <asm/pmc.h>
-
-perf_irq_t perf_irq = NULL;
-int handle_perf_interrupt(struct pt_regs *regs, int fault)
-{
- int retval;
-
- if (!perf_irq)
- panic("Unexpected PERF_COUNT interrupt %d\n", fault);
-
- retval = perf_irq(regs, fault);
- return retval;
-}
-
-/* Reserve PMC hardware if it is available. */
-perf_irq_t reserve_pmc_hardware(perf_irq_t new_perf_irq)
-{
- return cmpxchg(&perf_irq, NULL, new_perf_irq);
-}
-EXPORT_SYMBOL(reserve_pmc_hardware);
-
-/* Release PMC hardware. */
-void release_pmc_hardware(void)
-{
- perf_irq = NULL;
-}
-EXPORT_SYMBOL(release_pmc_hardware);
-
-
-/*
- * Get current overflow status of each performance counter,
- * and auxiliary performance counter.
- */
-unsigned long
-pmc_get_overflow(void)
-{
- unsigned long status;
-
- /*
- * merge base+aux into a single vector
- */
- status = __insn_mfspr(SPR_PERF_COUNT_STS);
- status |= __insn_mfspr(SPR_AUX_PERF_COUNT_STS) << TILE_BASE_COUNTERS;
- return status;
-}
-
-/*
- * Clear the status bit for the corresponding counter, if written
- * with a one.
- */
-void
-pmc_ack_overflow(unsigned long status)
-{
- /*
- * clear overflow status by writing ones
- */
- __insn_mtspr(SPR_PERF_COUNT_STS, status);
- __insn_mtspr(SPR_AUX_PERF_COUNT_STS, status >> TILE_BASE_COUNTERS);
-}
-
-/*
- * The perf count interrupts are masked and unmasked explicitly,
- * and only here. The normal irq_enable() does not enable them,
- * and irq_disable() does not disable them. That lets these
- * routines drive the perf count interrupts orthogonally.
- *
- * We also mask the perf count interrupts on entry to the perf count
- * interrupt handler in assembly code, and by default unmask them
- * again (with interrupt critical section protection) just before
- * returning from the interrupt. If the perf count handler returns
- * a non-zero error code, then we don't re-enable them before returning.
- *
- * For Pro, we rely on both interrupts being in the same word to update
- * them atomically so we never have one enabled and one disabled.
- */
-
-#if CHIP_HAS_SPLIT_INTR_MASK()
-# if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32
-# error Fix assumptions about which word PERF_COUNT interrupts are in
-# endif
-#endif
-
-static inline unsigned long long pmc_mask(void)
-{
- unsigned long long mask = 1ULL << INT_PERF_COUNT;
- mask |= 1ULL << INT_AUX_PERF_COUNT;
- return mask;
-}
-
-void unmask_pmc_interrupts(void)
-{
- interrupt_mask_reset_mask(pmc_mask());
-}
-
-void mask_pmc_interrupts(void)
-{
- interrupt_mask_set_mask(pmc_mask());
-}
diff --git a/arch/tile/kernel/proc.c b/arch/tile/kernel/proc.c
deleted file mode 100644
index 7983e9868df6..000000000000
--- a/arch/tile/kernel/proc.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/smp.h>
-#include <linux/seq_file.h>
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/timex.h>
-#include <linux/delay.h>
-#include <linux/fs.h>
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-#include <linux/hardirq.h>
-#include <linux/hugetlb.h>
-#include <linux/mman.h>
-#include <asm/unaligned.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/sections.h>
-#include <asm/homecache.h>
-#include <asm/hardwall.h>
-#include <arch/chip.h>
-
-
-/*
- * Support /proc/cpuinfo
- */
-
-#define cpu_to_ptr(n) ((void *)((long)(n)+1))
-#define ptr_to_cpu(p) ((long)(p) - 1)
-
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
- int n = ptr_to_cpu(v);
-
- if (n == 0) {
- seq_printf(m, "cpu count\t: %d\n", num_online_cpus());
- seq_printf(m, "cpu list\t: %*pbl\n",
- cpumask_pr_args(cpu_online_mask));
- seq_printf(m, "model name\t: %s\n", chip_model);
- seq_printf(m, "flags\t\t:\n"); /* nothing for now */
- seq_printf(m, "cpu MHz\t\t: %llu.%06llu\n",
- get_clock_rate() / 1000000,
- (get_clock_rate() % 1000000));
- seq_printf(m, "bogomips\t: %lu.%02lu\n\n",
- loops_per_jiffy/(500000/HZ),
- (loops_per_jiffy/(5000/HZ)) % 100);
- }
-
-#ifdef CONFIG_SMP
- if (!cpu_online(n))
- return 0;
-#endif
-
- seq_printf(m, "processor\t: %d\n", n);
-
- /* Print only num_online_cpus() blank lines total. */
- if (cpumask_next(n, cpu_online_mask) < nr_cpu_ids)
- seq_printf(m, "\n");
-
- return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
- return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
-}
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
- ++*pos;
- return c_start(m, pos);
-}
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
- .show = show_cpuinfo,
-};
-
-/*
- * Support /proc/tile directory
- */
-
-static int __init proc_tile_init(void)
-{
- struct proc_dir_entry *root = proc_mkdir("tile", NULL);
- if (root == NULL)
- return 0;
-
- proc_tile_hardwall_init(root);
-
- return 0;
-}
-
-arch_initcall(proc_tile_init);
-
-/*
- * Support /proc/sys/tile directory
- */
-
-static struct ctl_table unaligned_subtable[] = {
- {
- .procname = "enabled",
- .data = &unaligned_fixup,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = &proc_dointvec
- },
- {
- .procname = "printk",
- .data = &unaligned_printk,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = &proc_dointvec
- },
- {
- .procname = "count",
- .data = &unaligned_fixup_count,
- .maxlen = sizeof(int),
- .mode = 0644,
- .proc_handler = &proc_dointvec
- },
- {}
-};
-
-static struct ctl_table unaligned_table[] = {
- {
- .procname = "unaligned_fixup",
- .mode = 0555,
- .child = unaligned_subtable
- },
- {}
-};
-
-static struct ctl_path tile_path[] = {
- { .procname = "tile" },
- { }
-};
-
-static int __init proc_sys_tile_init(void)
-{
- register_sysctl_paths(tile_path, unaligned_table);
- return 0;
-}
-
-arch_initcall(proc_sys_tile_init);
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
deleted file mode 100644
index f0a0e18e4dfb..000000000000
--- a/arch/tile/kernel/process.c
+++ /dev/null
@@ -1,659 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/preempt.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/kprobes.h>
-#include <linux/elfcore.h>
-#include <linux/tick.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/compat.h>
-#include <linux/nmi.h>
-#include <linux/syscalls.h>
-#include <linux/kernel.h>
-#include <linux/tracehook.h>
-#include <linux/signal.h>
-#include <linux/delay.h>
-#include <linux/context_tracking.h>
-#include <asm/stack.h>
-#include <asm/switch_to.h>
-#include <asm/homecache.h>
-#include <asm/syscalls.h>
-#include <asm/traps.h>
-#include <asm/setup.h>
-#include <linux/uaccess.h>
-#ifdef CONFIG_HARDWALL
-#include <asm/hardwall.h>
-#endif
-#include <arch/chip.h>
-#include <arch/abi.h>
-#include <arch/sim_def.h>
-
-/*
- * Use the (x86) "idle=poll" option to prefer low latency when leaving the
- * idle loop over low power while in the idle loop, e.g. if we have
- * one thread per core and we want to get threads out of futex waits fast.
- */
-static int __init idle_setup(char *str)
-{
- if (!str)
- return -EINVAL;
-
- if (!strcmp(str, "poll")) {
- pr_info("using polling idle threads\n");
- cpu_idle_poll_ctrl(true);
- return 0;
- } else if (!strcmp(str, "halt")) {
- return 0;
- }
- return -1;
-}
-early_param("idle", idle_setup);
-
-void arch_cpu_idle(void)
-{
- __this_cpu_write(irq_stat.idle_timestamp, jiffies);
- _cpu_idle();
-}
-
-/*
- * Release a thread_info structure
- */
-void arch_release_thread_stack(unsigned long *stack)
-{
- struct thread_info *info = (void *)stack;
- struct single_step_state *step_state = info->step_state;
-
- if (step_state) {
-
- /*
- * FIXME: we don't munmap step_state->buffer
- * because the mm_struct for this process (info->task->mm)
- * has already been zeroed in exit_mm(). Keeping a
- * reference to it here seems like a bad move, so this
- * means we can't munmap() the buffer, and therefore if we
- * ptrace multiple threads in a process, we will slowly
- * leak user memory. (Note that as soon as the last
- * thread in a process dies, we will reclaim all user
- * memory including single-step buffers in the usual way.)
- * We should either assign a kernel VA to this buffer
- * somehow, or we should associate the buffer(s) with the
- * mm itself so we can clean them up that way.
- */
- kfree(step_state);
- }
-}
-
-static void save_arch_state(struct thread_struct *t);
-
-int copy_thread(unsigned long clone_flags, unsigned long sp,
- unsigned long arg, struct task_struct *p)
-{
- struct pt_regs *childregs = task_pt_regs(p);
- unsigned long ksp;
- unsigned long *callee_regs;
-
- /*
- * Set up the stack and stack pointer appropriately for the
- * new child to find itself woken up in __switch_to().
- * The callee-saved registers must be on the stack to be read;
- * the new task will then jump to assembly support to handle
- * calling schedule_tail(), etc., and (for userspace tasks)
- * returning to the context set up in the pt_regs.
- */
- ksp = (unsigned long) childregs;
- ksp -= C_ABI_SAVE_AREA_SIZE; /* interrupt-entry save area */
- ((long *)ksp)[0] = ((long *)ksp)[1] = 0;
- ksp -= CALLEE_SAVED_REGS_COUNT * sizeof(unsigned long);
- callee_regs = (unsigned long *)ksp;
- ksp -= C_ABI_SAVE_AREA_SIZE; /* __switch_to() save area */
- ((long *)ksp)[0] = ((long *)ksp)[1] = 0;
- p->thread.ksp = ksp;
-
- /* Record the pid of the task that created this one. */
- p->thread.creator_pid = current->pid;
-
- if (unlikely(p->flags & PF_KTHREAD)) {
- /* kernel thread */
- memset(childregs, 0, sizeof(struct pt_regs));
- memset(&callee_regs[2], 0,
- (CALLEE_SAVED_REGS_COUNT - 2) * sizeof(unsigned long));
- callee_regs[0] = sp; /* r30 = function */
- callee_regs[1] = arg; /* r31 = arg */
- p->thread.pc = (unsigned long) ret_from_kernel_thread;
- return 0;
- }
-
- /*
- * Start new thread in ret_from_fork so it schedules properly
- * and then return from interrupt like the parent.
- */
- p->thread.pc = (unsigned long) ret_from_fork;
-
- /*
- * Do not clone step state from the parent; each thread
- * must make its own lazily.
- */
- task_thread_info(p)->step_state = NULL;
-
-#ifdef __tilegx__
- /*
- * Do not clone unalign jit fixup from the parent; each thread
- * must allocate its own on demand.
- */
- task_thread_info(p)->unalign_jit_base = NULL;
-#endif
-
- /*
- * Copy the registers onto the kernel stack so the
- * return-from-interrupt code will reload it into registers.
- */
- *childregs = *current_pt_regs();
- childregs->regs[0] = 0; /* return value is zero */
- if (sp)
- childregs->sp = sp; /* override with new user stack pointer */
- memcpy(callee_regs, &childregs->regs[CALLEE_SAVED_FIRST_REG],
- CALLEE_SAVED_REGS_COUNT * sizeof(unsigned long));
-
- /* Save user stack top pointer so we can ID the stack vm area later. */
- p->thread.usp0 = childregs->sp;
-
- /*
- * If CLONE_SETTLS is set, set "tp" in the new task to "r4",
- * which is passed in as arg #5 to sys_clone().
- */
- if (clone_flags & CLONE_SETTLS)
- childregs->tp = childregs->regs[4];
-
-
-#if CHIP_HAS_TILE_DMA()
- /*
- * No DMA in the new thread. We model this on the fact that
- * fork() clears the pending signals, alarms, and aio for the child.
- */
- memset(&p->thread.tile_dma_state, 0, sizeof(struct tile_dma_state));
- memset(&p->thread.dma_async_tlb, 0, sizeof(struct async_tlb));
-#endif
-
- /* New thread has its miscellaneous processor state bits clear. */
- p->thread.proc_status = 0;
-
-#ifdef CONFIG_HARDWALL
- /* New thread does not own any networks. */
- memset(&p->thread.hardwall[0], 0,
- sizeof(struct hardwall_task) * HARDWALL_TYPES);
-#endif
-
-
- /*
- * Start the new thread with the current architecture state
- * (user interrupt masks, etc.).
- */
- save_arch_state(&p->thread);
-
- return 0;
-}
-
-int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
-{
- task_thread_info(tsk)->align_ctl = val;
- return 0;
-}
-
-int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
-{
- return put_user(task_thread_info(tsk)->align_ctl,
- (unsigned int __user *)adr);
-}
-
-static struct task_struct corrupt_current = { .comm = "<corrupt>" };
-
-/*
- * Return "current" if it looks plausible, or else a pointer to a dummy.
- * This can be helpful if we are just trying to emit a clean panic.
- */
-struct task_struct *validate_current(void)
-{
- struct task_struct *tsk = current;
- if (unlikely((unsigned long)tsk < PAGE_OFFSET ||
- (high_memory && (void *)tsk > high_memory) ||
- ((unsigned long)tsk & (__alignof__(*tsk) - 1)) != 0)) {
- pr_err("Corrupt 'current' %p (sp %#lx)\n", tsk, stack_pointer);
- tsk = &corrupt_current;
- }
- return tsk;
-}
-
-/* Take and return the pointer to the previous task, for schedule_tail(). */
-struct task_struct *sim_notify_fork(struct task_struct *prev)
-{
- struct task_struct *tsk = current;
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_FORK_PARENT |
- (tsk->thread.creator_pid << _SIM_CONTROL_OPERATOR_BITS));
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_FORK |
- (tsk->pid << _SIM_CONTROL_OPERATOR_BITS));
- return prev;
-}
-
-int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
-{
- struct pt_regs *ptregs = task_pt_regs(tsk);
- elf_core_copy_regs(regs, ptregs);
- return 1;
-}
-
-#if CHIP_HAS_TILE_DMA()
-
-/* Allow user processes to access the DMA SPRs */
-void grant_dma_mpls(void)
-{
-#if CONFIG_KERNEL_PL == 2
- __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
- __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
-#else
- __insn_mtspr(SPR_MPL_DMA_CPL_SET_0, 1);
- __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_0, 1);
-#endif
-}
-
-/* Forbid user processes from accessing the DMA SPRs */
-void restrict_dma_mpls(void)
-{
-#if CONFIG_KERNEL_PL == 2
- __insn_mtspr(SPR_MPL_DMA_CPL_SET_2, 1);
- __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_2, 1);
-#else
- __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1);
- __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1);
-#endif
-}
-
-/* Pause the DMA engine, then save off its state registers. */
-static void save_tile_dma_state(struct tile_dma_state *dma)
-{
- unsigned long state = __insn_mfspr(SPR_DMA_USER_STATUS);
- unsigned long post_suspend_state;
-
- /* If we're running, suspend the engine. */
- if ((state & DMA_STATUS_MASK) == SPR_DMA_STATUS__RUNNING_MASK)
- __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__SUSPEND_MASK);
-
- /*
- * Wait for the engine to idle, then save regs. Note that we
- * want to record the "running" bit from before suspension,
- * and the "done" bit from after, so that we can properly
- * distinguish a case where the user suspended the engine from
- * the case where the kernel suspended as part of the context
- * swap.
- */
- do {
- post_suspend_state = __insn_mfspr(SPR_DMA_USER_STATUS);
- } while (post_suspend_state & SPR_DMA_STATUS__BUSY_MASK);
-
- dma->src = __insn_mfspr(SPR_DMA_SRC_ADDR);
- dma->src_chunk = __insn_mfspr(SPR_DMA_SRC_CHUNK_ADDR);
- dma->dest = __insn_mfspr(SPR_DMA_DST_ADDR);
- dma->dest_chunk = __insn_mfspr(SPR_DMA_DST_CHUNK_ADDR);
- dma->strides = __insn_mfspr(SPR_DMA_STRIDE);
- dma->chunk_size = __insn_mfspr(SPR_DMA_CHUNK_SIZE);
- dma->byte = __insn_mfspr(SPR_DMA_BYTE);
- dma->status = (state & SPR_DMA_STATUS__RUNNING_MASK) |
- (post_suspend_state & SPR_DMA_STATUS__DONE_MASK);
-}
-
-/* Restart a DMA that was running before we were context-switched out. */
-static void restore_tile_dma_state(struct thread_struct *t)
-{
- const struct tile_dma_state *dma = &t->tile_dma_state;
-
- /*
- * The only way to restore the done bit is to run a zero
- * length transaction.
- */
- if ((dma->status & SPR_DMA_STATUS__DONE_MASK) &&
- !(__insn_mfspr(SPR_DMA_USER_STATUS) & SPR_DMA_STATUS__DONE_MASK)) {
- __insn_mtspr(SPR_DMA_BYTE, 0);
- __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__REQUEST_MASK);
- while (__insn_mfspr(SPR_DMA_USER_STATUS) &
- SPR_DMA_STATUS__BUSY_MASK)
- ;
- }
-
- __insn_mtspr(SPR_DMA_SRC_ADDR, dma->src);
- __insn_mtspr(SPR_DMA_SRC_CHUNK_ADDR, dma->src_chunk);
- __insn_mtspr(SPR_DMA_DST_ADDR, dma->dest);
- __insn_mtspr(SPR_DMA_DST_CHUNK_ADDR, dma->dest_chunk);
- __insn_mtspr(SPR_DMA_STRIDE, dma->strides);
- __insn_mtspr(SPR_DMA_CHUNK_SIZE, dma->chunk_size);
- __insn_mtspr(SPR_DMA_BYTE, dma->byte);
-
- /*
- * Restart the engine if we were running and not done.
- * Clear a pending async DMA fault that we were waiting on return
- * to user space to execute, since we expect the DMA engine
- * to regenerate those faults for us now. Note that we don't
- * try to clear the TIF_ASYNC_TLB flag, since it's relatively
- * harmless if set, and it covers both DMA and the SN processor.
- */
- if ((dma->status & DMA_STATUS_MASK) == SPR_DMA_STATUS__RUNNING_MASK) {
- t->dma_async_tlb.fault_num = 0;
- __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__REQUEST_MASK);
- }
-}
-
-#endif
-
-static void save_arch_state(struct thread_struct *t)
-{
-#if CHIP_HAS_SPLIT_INTR_MASK()
- t->interrupt_mask = __insn_mfspr(SPR_INTERRUPT_MASK_0_0) |
- ((u64)__insn_mfspr(SPR_INTERRUPT_MASK_0_1) << 32);
-#else
- t->interrupt_mask = __insn_mfspr(SPR_INTERRUPT_MASK_0);
-#endif
- t->ex_context[0] = __insn_mfspr(SPR_EX_CONTEXT_0_0);
- t->ex_context[1] = __insn_mfspr(SPR_EX_CONTEXT_0_1);
- t->system_save[0] = __insn_mfspr(SPR_SYSTEM_SAVE_0_0);
- t->system_save[1] = __insn_mfspr(SPR_SYSTEM_SAVE_0_1);
- t->system_save[2] = __insn_mfspr(SPR_SYSTEM_SAVE_0_2);
- t->system_save[3] = __insn_mfspr(SPR_SYSTEM_SAVE_0_3);
- t->intctrl_0 = __insn_mfspr(SPR_INTCTRL_0_STATUS);
- t->proc_status = __insn_mfspr(SPR_PROC_STATUS);
-#if !CHIP_HAS_FIXED_INTVEC_BASE()
- t->interrupt_vector_base = __insn_mfspr(SPR_INTERRUPT_VECTOR_BASE_0);
-#endif
- t->tile_rtf_hwm = __insn_mfspr(SPR_TILE_RTF_HWM);
-#if CHIP_HAS_DSTREAM_PF()
- t->dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
-#endif
-}
-
-static void restore_arch_state(const struct thread_struct *t)
-{
-#if CHIP_HAS_SPLIT_INTR_MASK()
- __insn_mtspr(SPR_INTERRUPT_MASK_0_0, (u32) t->interrupt_mask);
- __insn_mtspr(SPR_INTERRUPT_MASK_0_1, t->interrupt_mask >> 32);
-#else
- __insn_mtspr(SPR_INTERRUPT_MASK_0, t->interrupt_mask);
-#endif
- __insn_mtspr(SPR_EX_CONTEXT_0_0, t->ex_context[0]);
- __insn_mtspr(SPR_EX_CONTEXT_0_1, t->ex_context[1]);
- __insn_mtspr(SPR_SYSTEM_SAVE_0_0, t->system_save[0]);
- __insn_mtspr(SPR_SYSTEM_SAVE_0_1, t->system_save[1]);
- __insn_mtspr(SPR_SYSTEM_SAVE_0_2, t->system_save[2]);
- __insn_mtspr(SPR_SYSTEM_SAVE_0_3, t->system_save[3]);
- __insn_mtspr(SPR_INTCTRL_0_STATUS, t->intctrl_0);
- __insn_mtspr(SPR_PROC_STATUS, t->proc_status);
-#if !CHIP_HAS_FIXED_INTVEC_BASE()
- __insn_mtspr(SPR_INTERRUPT_VECTOR_BASE_0, t->interrupt_vector_base);
-#endif
- __insn_mtspr(SPR_TILE_RTF_HWM, t->tile_rtf_hwm);
-#if CHIP_HAS_DSTREAM_PF()
- __insn_mtspr(SPR_DSTREAM_PF, t->dstream_pf);
-#endif
-}
-
-
-void _prepare_arch_switch(struct task_struct *next)
-{
-#if CHIP_HAS_TILE_DMA()
- struct tile_dma_state *dma = &current->thread.tile_dma_state;
- if (dma->enabled)
- save_tile_dma_state(dma);
-#endif
-}
-
-
-struct task_struct *__sched _switch_to(struct task_struct *prev,
- struct task_struct *next)
-{
- /* DMA state is already saved; save off other arch state. */
- save_arch_state(&prev->thread);
-
-#if CHIP_HAS_TILE_DMA()
- /*
- * Restore DMA in new task if desired.
- * Note that it is only safe to restart here since interrupts
- * are disabled, so we can't take any DMATLB miss or access
- * interrupts before we have finished switching stacks.
- */
- if (next->thread.tile_dma_state.enabled) {
- restore_tile_dma_state(&next->thread);
- grant_dma_mpls();
- } else {
- restrict_dma_mpls();
- }
-#endif
-
- /* Restore other arch state. */
- restore_arch_state(&next->thread);
-
-#ifdef CONFIG_HARDWALL
- /* Enable or disable access to the network registers appropriately. */
- hardwall_switch_tasks(prev, next);
-#endif
-
- /* Notify the simulator of task exit. */
- if (unlikely(prev->state == TASK_DEAD))
- __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT |
- (prev->pid << _SIM_CONTROL_OPERATOR_BITS));
-
- /*
- * Switch kernel SP, PC, and callee-saved registers.
- * In the context of the new task, return the old task pointer
- * (i.e. the task that actually called __switch_to).
- * Pass the value to use for SYSTEM_SAVE_K_0 when we reset our sp.
- */
- return __switch_to(prev, next, next_current_ksp0(next));
-}
-
-/*
- * This routine is called on return from interrupt if any of the
- * TIF_ALLWORK_MASK flags are set in thread_info->flags. It is
- * entered with interrupts disabled so we don't miss an event that
- * modified the thread_info flags. We loop until all the tested flags
- * are clear. Note that the function is called on certain conditions
- * that are not listed in the loop condition here (e.g. SINGLESTEP)
- * which guarantees we will do those things once, and redo them if any
- * of the other work items is re-done, but won't continue looping if
- * all the other work is done.
- */
-void prepare_exit_to_usermode(struct pt_regs *regs, u32 thread_info_flags)
-{
- if (WARN_ON(!user_mode(regs)))
- return;
-
- do {
- local_irq_enable();
-
- if (thread_info_flags & _TIF_NEED_RESCHED)
- schedule();
-
-#if CHIP_HAS_TILE_DMA()
- if (thread_info_flags & _TIF_ASYNC_TLB)
- do_async_page_fault(regs);
-#endif
-
- if (thread_info_flags & _TIF_SIGPENDING)
- do_signal(regs);
-
- if (thread_info_flags & _TIF_NOTIFY_RESUME) {
- clear_thread_flag(TIF_NOTIFY_RESUME);
- tracehook_notify_resume(regs);
- }
-
- local_irq_disable();
- thread_info_flags = READ_ONCE(current_thread_info()->flags);
-
- } while (thread_info_flags & _TIF_WORK_MASK);
-
- if (thread_info_flags & _TIF_SINGLESTEP) {
- single_step_once(regs);
-#ifndef __tilegx__
- /*
- * FIXME: on tilepro, since we enable interrupts in
- * this routine, it's possible that we miss a signal
- * or other asynchronous event.
- */
- local_irq_disable();
-#endif
- }
-
- user_enter();
-}
-
-unsigned long get_wchan(struct task_struct *p)
-{
- struct KBacktraceIterator kbt;
-
- if (!p || p == current || p->state == TASK_RUNNING)
- return 0;
-
- for (KBacktraceIterator_init(&kbt, p, NULL);
- !KBacktraceIterator_end(&kbt);
- KBacktraceIterator_next(&kbt)) {
- if (!in_sched_functions(kbt.it.pc))
- return kbt.it.pc;
- }
-
- return 0;
-}
-
-/* Flush thread state. */
-void flush_thread(void)
-{
- /* Nothing */
-}
-
-/*
- * Free current thread data structures etc..
- */
-void exit_thread(struct task_struct *tsk)
-{
-#ifdef CONFIG_HARDWALL
- /*
- * Remove the task from the list of tasks that are associated
- * with any live hardwalls. (If the task that is exiting held
- * the last reference to a hardwall fd, it would already have
- * been released and deactivated at this point.)
- */
- hardwall_deactivate_all(tsk);
-#endif
-}
-
-void tile_show_regs(struct pt_regs *regs)
-{
- int i;
-#ifdef __tilegx__
- for (i = 0; i < 17; i++)
- pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
- i, regs->regs[i], i+18, regs->regs[i+18],
- i+36, regs->regs[i+36]);
- pr_err(" r17: "REGFMT" r35: "REGFMT" tp : "REGFMT"\n",
- regs->regs[17], regs->regs[35], regs->tp);
- pr_err(" sp : "REGFMT" lr : "REGFMT"\n", regs->sp, regs->lr);
-#else
- for (i = 0; i < 13; i++)
- pr_err(" r%-2d: "REGFMT" r%-2d: "REGFMT
- " r%-2d: "REGFMT" r%-2d: "REGFMT"\n",
- i, regs->regs[i], i+14, regs->regs[i+14],
- i+27, regs->regs[i+27], i+40, regs->regs[i+40]);
- pr_err(" r13: "REGFMT" tp : "REGFMT" sp : "REGFMT" lr : "REGFMT"\n",
- regs->regs[13], regs->tp, regs->sp, regs->lr);
-#endif
- pr_err(" pc : "REGFMT" ex1: %ld faultnum: %ld flags:%s%s%s%s\n",
- regs->pc, regs->ex1, regs->faultnum,
- is_compat_task() ? " compat" : "",
- (regs->flags & PT_FLAGS_DISABLE_IRQ) ? " noirq" : "",
- !(regs->flags & PT_FLAGS_CALLER_SAVES) ? " nocallersave" : "",
- (regs->flags & PT_FLAGS_RESTORE_REGS) ? " restoreregs" : "");
-}
-
-void show_regs(struct pt_regs *regs)
-{
- struct KBacktraceIterator kbt;
-
- show_regs_print_info(KERN_DEFAULT);
- tile_show_regs(regs);
-
- KBacktraceIterator_init(&kbt, NULL, regs);
- tile_show_stack(&kbt);
-}
-
-#ifdef __tilegx__
-void nmi_raise_cpu_backtrace(struct cpumask *in_mask)
-{
- struct cpumask mask;
- HV_Coord tile;
- unsigned int timeout;
- int cpu;
- HV_NMI_Info info[NR_CPUS];
-
- /* Tentatively dump stack on remote tiles via NMI. */
- timeout = 100;
- cpumask_copy(&mask, in_mask);
- while (!cpumask_empty(&mask) && timeout) {
- for_each_cpu(cpu, &mask) {
- tile.x = cpu_x(cpu);
- tile.y = cpu_y(cpu);
- info[cpu] = hv_send_nmi(tile, TILE_NMI_DUMP_STACK, 0);
- if (info[cpu].result == HV_NMI_RESULT_OK)
- cpumask_clear_cpu(cpu, &mask);
- }
-
- mdelay(10);
- touch_softlockup_watchdog();
- timeout--;
- }
-
- /* Warn about cpus stuck in ICS. */
- if (!cpumask_empty(&mask)) {
- for_each_cpu(cpu, &mask) {
-
- /* Clear the bit as if nmi_cpu_backtrace() ran. */
- cpumask_clear_cpu(cpu, in_mask);
-
- switch (info[cpu].result) {
- case HV_NMI_RESULT_FAIL_ICS:
- pr_warn("Skipping stack dump of cpu %d in ICS at pc %#llx\n",
- cpu, info[cpu].pc);
- break;
- case HV_NMI_RESULT_FAIL_HV:
- pr_warn("Skipping stack dump of cpu %d in hypervisor\n",
- cpu);
- break;
- case HV_ENOSYS:
- WARN_ONCE(1, "Hypervisor too old to allow remote stack dumps.\n");
- break;
- default: /* should not happen */
- pr_warn("Skipping stack dump of cpu %d [%d,%#llx]\n",
- cpu, info[cpu].result, info[cpu].pc);
- break;
- }
- }
- }
-}
-
-void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
-{
- nmi_trigger_cpumask_backtrace(mask, exclude_self,
- nmi_raise_cpu_backtrace);
-}
-#endif /* __tilegx_ */
diff --git a/arch/tile/kernel/ptrace.c b/arch/tile/kernel/ptrace.c
deleted file mode 100644
index d516d61751c2..000000000000
--- a/arch/tile/kernel/ptrace.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Copied from i386: Ross Biro 1/23/92
- */
-
-#include <linux/kernel.h>
-#include <linux/ptrace.h>
-#include <linux/kprobes.h>
-#include <linux/compat.h>
-#include <linux/uaccess.h>
-#include <linux/regset.h>
-#include <linux/elf.h>
-#include <linux/tracehook.h>
-#include <linux/context_tracking.h>
-#include <linux/sched/task_stack.h>
-
-#include <asm/traps.h>
-#include <arch/chip.h>
-
-#define CREATE_TRACE_POINTS
-#include <trace/events/syscalls.h>
-
-void user_enable_single_step(struct task_struct *child)
-{
- set_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-void user_disable_single_step(struct task_struct *child)
-{
- clear_tsk_thread_flag(child, TIF_SINGLESTEP);
-}
-
-/*
- * Called by kernel/ptrace.c when detaching..
- */
-void ptrace_disable(struct task_struct *child)
-{
- clear_tsk_thread_flag(child, TIF_SINGLESTEP);
-
- /*
- * These two are currently unused, but will be set by arch_ptrace()
- * and used in the syscall assembly when we do support them.
- */
- clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
-}
-
-/*
- * Get registers from task and ready the result for userspace.
- * Note that we localize the API issues to getregs() and putregs() at
- * some cost in performance, e.g. we need a full pt_regs copy for
- * PEEKUSR, and two copies for POKEUSR. But in general we expect
- * GETREGS/PUTREGS to be the API of choice anyway.
- */
-static char *getregs(struct task_struct *child, struct pt_regs *uregs)
-{
- *uregs = *task_pt_regs(child);
-
- /* Set up flags ABI bits. */
- uregs->flags = 0;
-#ifdef CONFIG_COMPAT
- if (task_thread_info(child)->status & TS_COMPAT)
- uregs->flags |= PT_FLAGS_COMPAT;
-#endif
-
- return (char *)uregs;
-}
-
-/* Put registers back to task. */
-static void putregs(struct task_struct *child, struct pt_regs *uregs)
-{
- struct pt_regs *regs = task_pt_regs(child);
-
- /* Don't allow overwriting the kernel-internal flags word. */
- uregs->flags = regs->flags;
-
- /* Only allow setting the ICS bit in the ex1 word. */
- uregs->ex1 = PL_ICS_EX1(USER_PL, EX1_ICS(uregs->ex1));
-
- *regs = *uregs;
-}
-
-enum tile_regset {
- REGSET_GPR,
-};
-
-static int tile_gpr_get(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- void *kbuf, void __user *ubuf)
-{
- struct pt_regs regs;
-
- getregs(target, &regs);
-
- return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &regs, 0,
- sizeof(regs));
-}
-
-static int tile_gpr_set(struct task_struct *target,
- const struct user_regset *regset,
- unsigned int pos, unsigned int count,
- const void *kbuf, const void __user *ubuf)
-{
- int ret;
- struct pt_regs regs = *task_pt_regs(target);
-
- ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &regs, 0,
- sizeof(regs));
- if (ret)
- return ret;
-
- putregs(target, &regs);
-
- return 0;
-}
-
-static const struct user_regset tile_user_regset[] = {
- [REGSET_GPR] = {
- .core_note_type = NT_PRSTATUS,
- .n = ELF_NGREG,
- .size = sizeof(elf_greg_t),
- .align = sizeof(elf_greg_t),
- .get = tile_gpr_get,
- .set = tile_gpr_set,
- },
-};
-
-static const struct user_regset_view tile_user_regset_view = {
- .name = CHIP_ARCH_NAME,
- .e_machine = ELF_ARCH,
- .ei_osabi = ELF_OSABI,
- .regsets = tile_user_regset,
- .n = ARRAY_SIZE(tile_user_regset),
-};
-
-const struct user_regset_view *task_user_regset_view(struct task_struct *task)
-{
- return &tile_user_regset_view;
-}
-
-long arch_ptrace(struct task_struct *child, long request,
- unsigned long addr, unsigned long data)
-{
- unsigned long __user *datap = (long __user __force *)data;
- unsigned long tmp;
- long ret = -EIO;
- char *childreg;
- struct pt_regs copyregs;
-
- switch (request) {
-
- case PTRACE_PEEKUSR: /* Read register from pt_regs. */
- if (addr >= PTREGS_SIZE)
- break;
- childreg = getregs(child, &copyregs) + addr;
-#ifdef CONFIG_COMPAT
- if (is_compat_task()) {
- if (addr & (sizeof(compat_long_t)-1))
- break;
- ret = put_user(*(compat_long_t *)childreg,
- (compat_long_t __user *)datap);
- } else
-#endif
- {
- if (addr & (sizeof(long)-1))
- break;
- ret = put_user(*(long *)childreg, datap);
- }
- break;
-
- case PTRACE_POKEUSR: /* Write register in pt_regs. */
- if (addr >= PTREGS_SIZE)
- break;
- childreg = getregs(child, &copyregs) + addr;
-#ifdef CONFIG_COMPAT
- if (is_compat_task()) {
- if (addr & (sizeof(compat_long_t)-1))
- break;
- *(compat_long_t *)childreg = data;
- } else
-#endif
- {
- if (addr & (sizeof(long)-1))
- break;
- *(long *)childreg = data;
- }
- putregs(child, &copyregs);
- ret = 0;
- break;
-
- case PTRACE_GETREGS: /* Get all registers from the child. */
- ret = copy_regset_to_user(child, &tile_user_regset_view,
- REGSET_GPR, 0,
- sizeof(struct pt_regs), datap);
- break;
-
- case PTRACE_SETREGS: /* Set all registers in the child. */
- ret = copy_regset_from_user(child, &tile_user_regset_view,
- REGSET_GPR, 0,
- sizeof(struct pt_regs), datap);
- break;
-
- case PTRACE_GETFPREGS: /* Get the child FPU state. */
- case PTRACE_SETFPREGS: /* Set the child FPU state. */
- break;
-
- case PTRACE_SETOPTIONS:
- /* Support TILE-specific ptrace options. */
- BUILD_BUG_ON(PTRACE_O_MASK_TILE & PTRACE_O_MASK);
- tmp = data & PTRACE_O_MASK_TILE;
- data &= ~PTRACE_O_MASK_TILE;
- ret = ptrace_request(child, request, addr, data);
- if (ret == 0) {
- unsigned int flags = child->ptrace;
- flags &= ~(PTRACE_O_MASK_TILE << PT_OPT_FLAG_SHIFT);
- flags |= (tmp << PT_OPT_FLAG_SHIFT);
- child->ptrace = flags;
- }
- break;
-
- default:
-#ifdef CONFIG_COMPAT
- if (task_thread_info(current)->status & TS_COMPAT) {
- ret = compat_ptrace_request(child, request,
- addr, data);
- break;
- }
-#endif
- ret = ptrace_request(child, request, addr, data);
- break;
- }
-
- return ret;
-}
-
-#ifdef CONFIG_COMPAT
-/* Not used; we handle compat issues in arch_ptrace() directly. */
-long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
- compat_ulong_t addr, compat_ulong_t data)
-{
- BUG();
-}
-#endif
-
-int do_syscall_trace_enter(struct pt_regs *regs)
-{
- u32 work = READ_ONCE(current_thread_info()->flags);
-
- if ((work & _TIF_SYSCALL_TRACE) &&
- tracehook_report_syscall_entry(regs)) {
- regs->regs[TREG_SYSCALL_NR] = -1;
- return -1;
- }
-
- if (secure_computing(NULL) == -1)
- return -1;
-
- if (work & _TIF_SYSCALL_TRACEPOINT)
- trace_sys_enter(regs, regs->regs[TREG_SYSCALL_NR]);
-
- return regs->regs[TREG_SYSCALL_NR];
-}
-
-void do_syscall_trace_exit(struct pt_regs *regs)
-{
- long errno;
-
- /*
- * The standard tile calling convention returns the value (or negative
- * errno) in r0, and zero (or positive errno) in r1.
- * It saves a couple of cycles on the hot path to do this work in
- * registers only as we return, rather than updating the in-memory
- * struct ptregs.
- */
- errno = (long) regs->regs[0];
- if (errno < 0 && errno > -4096)
- regs->regs[1] = -errno;
- else
- regs->regs[1] = 0;
-
- if (test_thread_flag(TIF_SYSCALL_TRACE))
- tracehook_report_syscall_exit(regs, 0);
-
- if (test_thread_flag(TIF_SYSCALL_TRACEPOINT))
- trace_sys_exit(regs, regs->regs[0]);
-}
-
-void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs)
-{
- struct siginfo info;
-
- memset(&info, 0, sizeof(info));
- info.si_signo = SIGTRAP;
- info.si_code = TRAP_BRKPT;
- info.si_addr = (void __user *) regs->pc;
-
- /* Send us the fakey SIGTRAP */
- force_sig_info(SIGTRAP, &info, tsk);
-}
-
-/* Handle synthetic interrupt delivered only by the simulator. */
-void __kprobes do_breakpoint(struct pt_regs* regs, int fault_num)
-{
- send_sigtrap(current, regs);
-}
diff --git a/arch/tile/kernel/reboot.c b/arch/tile/kernel/reboot.c
deleted file mode 100644
index 6c5d2c070a12..000000000000
--- a/arch/tile/kernel/reboot.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/stddef.h>
-#include <linux/reboot.h>
-#include <linux/smp.h>
-#include <linux/pm.h>
-#include <linux/export.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <hv/hypervisor.h>
-
-#ifndef CONFIG_SMP
-#define smp_send_stop()
-#endif
-
-void machine_halt(void)
-{
- arch_local_irq_disable_all();
- smp_send_stop();
- hv_halt();
-}
-
-void machine_power_off(void)
-{
- arch_local_irq_disable_all();
- smp_send_stop();
- hv_power_off();
-}
-
-void machine_restart(char *cmd)
-{
- arch_local_irq_disable_all();
- smp_send_stop();
- hv_restart((HV_VirtAddr) "vmlinux", (HV_VirtAddr) cmd);
-}
-
-/* No interesting distinction to be made here. */
-void (*pm_power_off)(void) = NULL;
-EXPORT_SYMBOL(pm_power_off);
diff --git a/arch/tile/kernel/regs_32.S b/arch/tile/kernel/regs_32.S
deleted file mode 100644
index 542cae17a93a..000000000000
--- a/arch/tile/kernel/regs_32.S
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/asm-offsets.h>
-#include <arch/spr_def.h>
-#include <asm/processor.h>
-#include <asm/switch_to.h>
-
-/*
- * See <asm/switch_to.h>; called with prev and next task_struct pointers.
- * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
- *
- * We want to save pc/sp in "prev", and get the new pc/sp from "next".
- * We also need to save all the callee-saved registers on the stack.
- *
- * Intel enables/disables access to the hardware cycle counter in
- * seccomp (secure computing) environments if necessary, based on
- * has_secure_computing(). We might want to do this at some point,
- * though it would require virtualizing the other SPRs under WORLD_ACCESS.
- *
- * Since we're saving to the stack, we omit sp from this list.
- * And for parallels with other architectures, we save lr separately,
- * in the thread_struct itself (as the "pc" field).
- *
- * This code also needs to be aligned with process.c copy_thread()
- */
-
-#if CALLEE_SAVED_REGS_COUNT != 24
-# error Mismatch between <asm/switch_to.h> and kernel/entry.S
-#endif
-#define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 4)
-
-#define SAVE_REG(r) { sw r12, r; addi r12, r12, 4 }
-#define LOAD_REG(r) { lw r, r12; addi r12, r12, 4 }
-#define FOR_EACH_CALLEE_SAVED_REG(f) \
- f(r30); f(r31); \
- f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
- f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
- f(r48); f(r49); f(r50); f(r51); f(r52);
-
-STD_ENTRY_SECTION(__switch_to, .sched.text)
- {
- move r10, sp
- sw sp, lr
- addi sp, sp, -FRAME_SIZE
- }
- {
- addi r11, sp, 4
- addi r12, sp, 8
- }
- {
- sw r11, r10
- addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
- }
- {
- lw r13, r4 /* Load new sp to a temp register early. */
- addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
- }
- FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
- {
- sw r3, sp
- addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
- }
- {
- sw r3, lr
- addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
- }
- {
- lw lr, r4
- addi r12, r13, 8
- }
- {
- /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
- move sp, r13
- mtspr SPR_SYSTEM_SAVE_K_0, r2
- }
- FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
-.L__switch_to_pc:
- {
- addi sp, sp, FRAME_SIZE
- jrp lr /* r0 is still valid here, so return it */
- }
- STD_ENDPROC(__switch_to)
-
-/* Return a suitable address for the backtracer for suspended threads */
-STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
- lnk r0
- {
- addli r0, r0, .L__switch_to_pc - .
- jrp lr
- }
- STD_ENDPROC(get_switch_to_pc)
-
-STD_ENTRY(get_pt_regs)
- .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
- r8, r9, r10, r11, r12, r13, r14, r15, \
- r16, r17, r18, r19, r20, r21, r22, r23, \
- r24, r25, r26, r27, r28, r29, r30, r31, \
- r32, r33, r34, r35, r36, r37, r38, r39, \
- r40, r41, r42, r43, r44, r45, r46, r47, \
- r48, r49, r50, r51, r52, tp, sp
- {
- sw r0, \reg
- addi r0, r0, 4
- }
- .endr
- {
- sw r0, lr
- addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
- }
- lnk r1
- {
- sw r0, r1
- addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
- }
- mfspr r1, INTERRUPT_CRITICAL_SECTION
- shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
- ori r1, r1, KERNEL_PL
- {
- sw r0, r1
- addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
- }
- {
- sw r0, zero /* clear faultnum */
- addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
- }
- {
- sw r0, zero /* clear orig_r0 */
- addli r0, r0, -PTREGS_OFFSET_ORIG_R0 /* restore r0 to base */
- }
- jrp lr
- STD_ENDPROC(get_pt_regs)
diff --git a/arch/tile/kernel/regs_64.S b/arch/tile/kernel/regs_64.S
deleted file mode 100644
index bbffcc6f340f..000000000000
--- a/arch/tile/kernel/regs_64.S
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/asm-offsets.h>
-#include <arch/spr_def.h>
-#include <asm/processor.h>
-#include <asm/switch_to.h>
-
-/*
- * See <asm/switch_to.h>; called with prev and next task_struct pointers.
- * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
- *
- * We want to save pc/sp in "prev", and get the new pc/sp from "next".
- * We also need to save all the callee-saved registers on the stack.
- *
- * Intel enables/disables access to the hardware cycle counter in
- * seccomp (secure computing) environments if necessary, based on
- * has_secure_computing(). We might want to do this at some point,
- * though it would require virtualizing the other SPRs under WORLD_ACCESS.
- *
- * Since we're saving to the stack, we omit sp from this list.
- * And for parallels with other architectures, we save lr separately,
- * in the thread_struct itself (as the "pc" field).
- *
- * This code also needs to be aligned with process.c copy_thread()
- */
-
-#if CALLEE_SAVED_REGS_COUNT != 24
-# error Mismatch between <asm/switch_to.h> and kernel/entry.S
-#endif
-#define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
-
-#define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
-#define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
-#define FOR_EACH_CALLEE_SAVED_REG(f) \
- f(r30); f(r31); \
- f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
- f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
- f(r48); f(r49); f(r50); f(r51); f(r52);
-
-STD_ENTRY_SECTION(__switch_to, .sched.text)
- {
- move r10, sp
- st sp, lr
- }
- {
- addli r11, sp, -FRAME_SIZE + 8
- addli sp, sp, -FRAME_SIZE
- }
- {
- st r11, r10
- addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
- }
- {
- ld r13, r4 /* Load new sp to a temp register early. */
- addi r12, sp, 16
- }
- FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
- addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
- {
- st r3, sp
- addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
- }
- {
- st r3, lr
- addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
- }
- {
- ld lr, r4
- addi r12, r13, 16
- }
- {
- /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
- move sp, r13
- mtspr SPR_SYSTEM_SAVE_K_0, r2
- }
- FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
-.L__switch_to_pc:
- {
- addli sp, sp, FRAME_SIZE
- jrp lr /* r0 is still valid here, so return it */
- }
- STD_ENDPROC(__switch_to)
-
-/* Return a suitable address for the backtracer for suspended threads */
-STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
- lnk r0
- {
- addli r0, r0, .L__switch_to_pc - .
- jrp lr
- }
- STD_ENDPROC(get_switch_to_pc)
-
-STD_ENTRY(get_pt_regs)
- .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
- r8, r9, r10, r11, r12, r13, r14, r15, \
- r16, r17, r18, r19, r20, r21, r22, r23, \
- r24, r25, r26, r27, r28, r29, r30, r31, \
- r32, r33, r34, r35, r36, r37, r38, r39, \
- r40, r41, r42, r43, r44, r45, r46, r47, \
- r48, r49, r50, r51, r52, tp, sp
- {
- st r0, \reg
- addi r0, r0, 8
- }
- .endr
- {
- st r0, lr
- addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
- }
- lnk r1
- {
- st r0, r1
- addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
- }
- mfspr r1, INTERRUPT_CRITICAL_SECTION
- shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
- ori r1, r1, KERNEL_PL
- {
- st r0, r1
- addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
- }
- {
- st r0, zero /* clear faultnum */
- addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
- }
- {
- st r0, zero /* clear orig_r0 */
- addli r0, r0, -PTREGS_OFFSET_ORIG_R0 /* restore r0 to base */
- }
- jrp lr
- STD_ENDPROC(get_pt_regs)
diff --git a/arch/tile/kernel/relocate_kernel_32.S b/arch/tile/kernel/relocate_kernel_32.S
deleted file mode 100644
index e44fbcf8cbd5..000000000000
--- a/arch/tile/kernel/relocate_kernel_32.S
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * copy new kernel into place and then call hv_reexec
- *
- */
-
-#include <linux/linkage.h>
-#include <arch/chip.h>
-#include <asm/page.h>
-#include <hv/hypervisor.h>
-
-#undef RELOCATE_NEW_KERNEL_VERBOSE
-
-STD_ENTRY(relocate_new_kernel)
-
- move r30, r0 /* page list */
- move r31, r1 /* address of page we are on */
- move r32, r2 /* start address of new kernel */
-
- shri r1, r1, PAGE_SHIFT
- addi r1, r1, 1
- shli sp, r1, PAGE_SHIFT
- addi sp, sp, -8
- /* we now have a stack (whether we need one or not) */
-
- moveli r40, lo16(hv_console_putc)
- auli r40, r40, ha16(hv_console_putc)
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'r'
- jalr r40
-
- moveli r0, '_'
- jalr r40
-
- moveli r0, 'n'
- jalr r40
-
- moveli r0, '_'
- jalr r40
-
- moveli r0, 'k'
- jalr r40
-
- moveli r0, '\n'
- jalr r40
-#endif
-
- /*
- * Throughout this code r30 is pointer to the element of page
- * list we are working on.
- *
- * Normally we get to the next element of the page list by
- * incrementing r30 by four. The exception is if the element
- * on the page list is an IND_INDIRECTION in which case we use
- * the element with the low bits masked off as the new value
- * of r30.
- *
- * To get this started, we need the value passed to us (which
- * will always be an IND_INDIRECTION) in memory somewhere with
- * r30 pointing at it. To do that, we push the value passed
- * to us on the stack and make r30 point to it.
- */
-
- sw sp, r30
- move r30, sp
- addi sp, sp, -8
-
- /*
- * On TILEPro, we need to flush all tiles' caches, since we may
- * have been doing hash-for-home caching there. Note that we
- * must do this _after_ we're completely done modifying any memory
- * other than our output buffer (which we know is locally cached).
- * We want the caches to be fully clean when we do the reexec,
- * because the hypervisor is going to do this flush again at that
- * point, and we don't want that second flush to overwrite any memory.
- */
- {
- move r0, zero /* cache_pa */
- move r1, zero
- }
- {
- auli r2, zero, ha16(HV_FLUSH_EVICT_L2) /* cache_control */
- movei r3, -1 /* cache_cpumask; -1 means all client tiles */
- }
- {
- move r4, zero /* tlb_va */
- move r5, zero /* tlb_length */
- }
- {
- move r6, zero /* tlb_pgsize */
- move r7, zero /* tlb_cpumask */
- }
- {
- move r8, zero /* asids */
- moveli r20, lo16(hv_flush_remote)
- }
- {
- move r9, zero /* asidcount */
- auli r20, r20, ha16(hv_flush_remote)
- }
-
- jalr r20
-
- /* r33 is destination pointer, default to zero */
-
- moveli r33, 0
-
-.Lloop: lw r10, r30
-
- andi r9, r10, 0xf /* low 4 bits tell us what type it is */
- xor r10, r10, r9 /* r10 is now value with low 4 bits stripped */
-
- seqi r0, r9, 0x1 /* IND_DESTINATION */
- bzt r0, .Ltry2
-
- move r33, r10
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'd'
- jalr r40
-#endif
-
- addi r30, r30, 4
- j .Lloop
-
-.Ltry2:
- seqi r0, r9, 0x2 /* IND_INDIRECTION */
- bzt r0, .Ltry4
-
- move r30, r10
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'i'
- jalr r40
-#endif
-
- j .Lloop
-
-.Ltry4:
- seqi r0, r9, 0x4 /* IND_DONE */
- bzt r0, .Ltry8
-
- mf
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'D'
- jalr r40
- moveli r0, '\n'
- jalr r40
-#endif
-
- move r0, r32
- moveli r1, 0 /* arg to hv_reexec is 64 bits */
-
- moveli r41, lo16(hv_reexec)
- auli r41, r41, ha16(hv_reexec)
-
- jalr r41
-
- /* we should not get here */
-
- moveli r0, '?'
- jalr r40
- moveli r0, '\n'
- jalr r40
-
- j .Lhalt
-
-.Ltry8: seqi r0, r9, 0x8 /* IND_SOURCE */
- bz r0, .Lerr /* unknown type */
-
- /* copy page at r10 to page at r33 */
-
- move r11, r33
-
- moveli r0, lo16(PAGE_SIZE)
- auli r0, r0, ha16(PAGE_SIZE)
- add r33, r33, r0
-
- /* copy word at r10 to word at r11 until r11 equals r33 */
-
- /* We know page size must be multiple of 16, so we can unroll
- * 16 times safely without any edge case checking.
- *
- * Issue a flush of the destination every 16 words to avoid
- * incoherence when starting the new kernel. (Now this is
- * just good paranoia because the hv_reexec call will also
- * take care of this.)
- */
-
-1:
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0; addi r11, r11, 4 }
- { lw r0, r10; addi r10, r10, 4 }
- { sw r11, r0 }
- { flush r11 ; addi r11, r11, 4 }
-
- seq r0, r33, r11
- bzt r0, 1b
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 's'
- jalr r40
-#endif
-
- addi r30, r30, 4
- j .Lloop
-
-
-.Lerr: moveli r0, 'e'
- jalr r40
- moveli r0, 'r'
- jalr r40
- moveli r0, 'r'
- jalr r40
- moveli r0, '\n'
- jalr r40
-.Lhalt:
- moveli r41, lo16(hv_halt)
- auli r41, r41, ha16(hv_halt)
-
- jalr r41
- STD_ENDPROC(relocate_new_kernel)
-
- .section .rodata,"a"
-
- .globl relocate_new_kernel_size
-relocate_new_kernel_size:
- .long .Lend_relocate_new_kernel - relocate_new_kernel
diff --git a/arch/tile/kernel/relocate_kernel_64.S b/arch/tile/kernel/relocate_kernel_64.S
deleted file mode 100644
index d9d8cf6176e8..000000000000
--- a/arch/tile/kernel/relocate_kernel_64.S
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * copy new kernel into place and then call hv_reexec
- *
- */
-
-#include <linux/linkage.h>
-#include <arch/chip.h>
-#include <asm/page.h>
-#include <hv/hypervisor.h>
-
-#undef RELOCATE_NEW_KERNEL_VERBOSE
-
-STD_ENTRY(relocate_new_kernel)
-
- move r30, r0 /* page list */
- move r31, r1 /* address of page we are on */
- move r32, r2 /* start address of new kernel */
-
- shrui r1, r1, PAGE_SHIFT
- addi r1, r1, 1
- shli sp, r1, PAGE_SHIFT
- addi sp, sp, -8
- /* we now have a stack (whether we need one or not) */
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r40, hw2_last(hv_console_putc)
- shl16insli r40, r40, hw1(hv_console_putc)
- shl16insli r40, r40, hw0(hv_console_putc)
-
- moveli r0, 'r'
- jalr r40
-
- moveli r0, '_'
- jalr r40
-
- moveli r0, 'n'
- jalr r40
-
- moveli r0, '_'
- jalr r40
-
- moveli r0, 'k'
- jalr r40
-
- moveli r0, '\n'
- jalr r40
-#endif
-
- /*
- * Throughout this code r30 is pointer to the element of page
- * list we are working on.
- *
- * Normally we get to the next element of the page list by
- * incrementing r30 by eight. The exception is if the element
- * on the page list is an IND_INDIRECTION in which case we use
- * the element with the low bits masked off as the new value
- * of r30.
- *
- * To get this started, we need the value passed to us (which
- * will always be an IND_INDIRECTION) in memory somewhere with
- * r30 pointing at it. To do that, we push the value passed
- * to us on the stack and make r30 point to it.
- */
-
- st sp, r30
- move r30, sp
- addi sp, sp, -16
-
- /*
- * On TILE-GX, we need to flush all tiles' caches, since we may
- * have been doing hash-for-home caching there. Note that we
- * must do this _after_ we're completely done modifying any memory
- * other than our output buffer (which we know is locally cached).
- * We want the caches to be fully clean when we do the reexec,
- * because the hypervisor is going to do this flush again at that
- * point, and we don't want that second flush to overwrite any memory.
- */
- {
- move r0, zero /* cache_pa */
- moveli r1, hw2_last(HV_FLUSH_EVICT_L2)
- }
- {
- shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
- movei r2, -1 /* cache_cpumask; -1 means all client tiles */
- }
- {
- shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2) /* cache_control */
- move r3, zero /* tlb_va */
- }
- {
- move r4, zero /* tlb_length */
- move r5, zero /* tlb_pgsize */
- }
- {
- move r6, zero /* tlb_cpumask */
- move r7, zero /* asids */
- }
- {
- moveli r20, hw2_last(hv_flush_remote)
- move r8, zero /* asidcount */
- }
- shl16insli r20, r20, hw1(hv_flush_remote)
- shl16insli r20, r20, hw0(hv_flush_remote)
-
- jalr r20
-
- /* r33 is destination pointer, default to zero */
-
- moveli r33, 0
-
-.Lloop: ld r10, r30
-
- andi r9, r10, 0xf /* low 4 bits tell us what type it is */
- xor r10, r10, r9 /* r10 is now value with low 4 bits stripped */
-
- cmpeqi r0, r9, 0x1 /* IND_DESTINATION */
- beqzt r0, .Ltry2
-
- move r33, r10
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'd'
- jalr r40
-#endif
-
- addi r30, r30, 8
- j .Lloop
-
-.Ltry2:
- cmpeqi r0, r9, 0x2 /* IND_INDIRECTION */
- beqzt r0, .Ltry4
-
- move r30, r10
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'i'
- jalr r40
-#endif
-
- j .Lloop
-
-.Ltry4:
- cmpeqi r0, r9, 0x4 /* IND_DONE */
- beqzt r0, .Ltry8
-
- mf
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'D'
- jalr r40
- moveli r0, '\n'
- jalr r40
-#endif
-
- move r0, r32
-
- moveli r41, hw2_last(hv_reexec)
- shl16insli r41, r41, hw1(hv_reexec)
- shl16insli r41, r41, hw0(hv_reexec)
-
- jalr r41
-
- /* we should not get here */
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, '?'
- jalr r40
- moveli r0, '\n'
- jalr r40
-#endif
-
- j .Lhalt
-
-.Ltry8: cmpeqi r0, r9, 0x8 /* IND_SOURCE */
- beqz r0, .Lerr /* unknown type */
-
- /* copy page at r10 to page at r33 */
-
- move r11, r33
-
- moveli r0, hw2_last(PAGE_SIZE)
- shl16insli r0, r0, hw1(PAGE_SIZE)
- shl16insli r0, r0, hw0(PAGE_SIZE)
- add r33, r33, r0
-
- /* copy word at r10 to word at r11 until r11 equals r33 */
-
- /* We know page size must be multiple of 8, so we can unroll
- * 8 times safely without any edge case checking.
- *
- * Issue a flush of the destination every 8 words to avoid
- * incoherence when starting the new kernel. (Now this is
- * just good paranoia because the hv_reexec call will also
- * take care of this.)
- */
-
-1:
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0; addi r11, r11, 8 }
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0; addi r11, r11, 8 }
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0; addi r11, r11, 8 }
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0; addi r11, r11, 8 }
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0; addi r11, r11, 8 }
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0; addi r11, r11, 8 }
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0; addi r11, r11, 8 }
- { ld r0, r10; addi r10, r10, 8 }
- { st r11, r0 }
- { flush r11 ; addi r11, r11, 8 }
-
- cmpeq r0, r33, r11
- beqzt r0, 1b
-
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 's'
- jalr r40
-#endif
-
- addi r30, r30, 8
- j .Lloop
-
-
-.Lerr:
-#ifdef RELOCATE_NEW_KERNEL_VERBOSE
- moveli r0, 'e'
- jalr r40
- moveli r0, 'r'
- jalr r40
- moveli r0, 'r'
- jalr r40
- moveli r0, '\n'
- jalr r40
-#endif
-.Lhalt:
- moveli r41, hw2_last(hv_halt)
- shl16insli r41, r41, hw1(hv_halt)
- shl16insli r41, r41, hw0(hv_halt)
-
- jalr r41
- STD_ENDPROC(relocate_new_kernel)
-
- .section .rodata,"a"
-
- .globl relocate_new_kernel_size
-relocate_new_kernel_size:
- .long .Lend_relocate_new_kernel - relocate_new_kernel
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
deleted file mode 100644
index eb4e198f6f93..000000000000
--- a/arch/tile/kernel/setup.c
+++ /dev/null
@@ -1,1743 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mmzone.h>
-#include <linux/bootmem.h>
-#include <linux/module.h>
-#include <linux/node.h>
-#include <linux/cpu.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
-#include <linux/kexec.h>
-#include <linux/pci.h>
-#include <linux/swiotlb.h>
-#include <linux/initrd.h>
-#include <linux/io.h>
-#include <linux/highmem.h>
-#include <linux/smp.h>
-#include <linux/timex.h>
-#include <linux/hugetlb.h>
-#include <linux/start_kernel.h>
-#include <linux/screen_info.h>
-#include <linux/tick.h>
-#include <asm/setup.h>
-#include <asm/sections.h>
-#include <asm/cacheflush.h>
-#include <asm/pgalloc.h>
-#include <asm/mmu_context.h>
-#include <hv/hypervisor.h>
-#include <arch/interrupts.h>
-
-/* <linux/smp.h> doesn't provide this definition. */
-#ifndef CONFIG_SMP
-#define setup_max_cpus 1
-#endif
-
-static inline int ABS(int x) { return x >= 0 ? x : -x; }
-
-/* Chip information */
-char chip_model[64] __ro_after_init;
-
-#ifdef CONFIG_VT
-struct screen_info screen_info;
-#endif
-
-struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
-EXPORT_SYMBOL(node_data);
-
-/* Information on the NUMA nodes that we compute early */
-unsigned long node_start_pfn[MAX_NUMNODES];
-unsigned long node_end_pfn[MAX_NUMNODES];
-unsigned long __initdata node_memmap_pfn[MAX_NUMNODES];
-unsigned long __initdata node_percpu_pfn[MAX_NUMNODES];
-unsigned long __initdata node_free_pfn[MAX_NUMNODES];
-
-static unsigned long __initdata node_percpu[MAX_NUMNODES];
-
-/*
- * per-CPU stack and boot info.
- */
-DEFINE_PER_CPU(unsigned long, boot_sp) =
- (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA;
-
-#ifdef CONFIG_SMP
-DEFINE_PER_CPU(unsigned long, boot_pc) = (unsigned long)start_kernel;
-#else
-/*
- * The variable must be __initdata since it references __init code.
- * With CONFIG_SMP it is per-cpu data, which is exempt from validation.
- */
-unsigned long __initdata boot_pc = (unsigned long)start_kernel;
-#endif
-
-#ifdef CONFIG_HIGHMEM
-/* Page frame index of end of lowmem on each controller. */
-unsigned long node_lowmem_end_pfn[MAX_NUMNODES];
-
-/* Number of pages that can be mapped into lowmem. */
-static unsigned long __initdata mappable_physpages;
-#endif
-
-/* Data on which physical memory controller corresponds to which NUMA node */
-int node_controller[MAX_NUMNODES] = { [0 ... MAX_NUMNODES-1] = -1 };
-
-#ifdef CONFIG_HIGHMEM
-/* Map information from VAs to PAs */
-unsigned long pbase_map[1 << (32 - HPAGE_SHIFT)]
- __ro_after_init __attribute__((aligned(L2_CACHE_BYTES)));
-EXPORT_SYMBOL(pbase_map);
-
-/* Map information from PAs to VAs */
-void *vbase_map[NR_PA_HIGHBIT_VALUES]
- __ro_after_init __attribute__((aligned(L2_CACHE_BYTES)));
-EXPORT_SYMBOL(vbase_map);
-#endif
-
-/* Node number as a function of the high PA bits */
-int highbits_to_node[NR_PA_HIGHBIT_VALUES] __ro_after_init;
-EXPORT_SYMBOL(highbits_to_node);
-
-static unsigned int __initdata maxmem_pfn = -1U;
-static unsigned int __initdata maxnodemem_pfn[MAX_NUMNODES] = {
- [0 ... MAX_NUMNODES-1] = -1U
-};
-static nodemask_t __initdata isolnodes;
-
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
-enum { DEFAULT_PCI_RESERVE_MB = 64 };
-static unsigned int __initdata pci_reserve_mb = DEFAULT_PCI_RESERVE_MB;
-unsigned long __initdata pci_reserve_start_pfn = -1U;
-unsigned long __initdata pci_reserve_end_pfn = -1U;
-#endif
-
-static int __init setup_maxmem(char *str)
-{
- unsigned long long maxmem;
- if (str == NULL || (maxmem = memparse(str, NULL)) == 0)
- return -EINVAL;
-
- maxmem_pfn = (maxmem >> HPAGE_SHIFT) << (HPAGE_SHIFT - PAGE_SHIFT);
- pr_info("Forcing RAM used to no more than %dMB\n",
- maxmem_pfn >> (20 - PAGE_SHIFT));
- return 0;
-}
-early_param("maxmem", setup_maxmem);
-
-static int __init setup_maxnodemem(char *str)
-{
- char *endp;
- unsigned long long maxnodemem;
- unsigned long node;
-
- node = str ? simple_strtoul(str, &endp, 0) : INT_MAX;
- if (node >= MAX_NUMNODES || *endp != ':')
- return -EINVAL;
-
- maxnodemem = memparse(endp+1, NULL);
- maxnodemem_pfn[node] = (maxnodemem >> HPAGE_SHIFT) <<
- (HPAGE_SHIFT - PAGE_SHIFT);
- pr_info("Forcing RAM used on node %ld to no more than %dMB\n",
- node, maxnodemem_pfn[node] >> (20 - PAGE_SHIFT));
- return 0;
-}
-early_param("maxnodemem", setup_maxnodemem);
-
-struct memmap_entry {
- u64 addr; /* start of memory segment */
- u64 size; /* size of memory segment */
-};
-static struct memmap_entry memmap_map[64];
-static int memmap_nr;
-
-static void add_memmap_region(u64 addr, u64 size)
-{
- if (memmap_nr >= ARRAY_SIZE(memmap_map)) {
- pr_err("Ooops! Too many entries in the memory map!\n");
- return;
- }
- memmap_map[memmap_nr].addr = addr;
- memmap_map[memmap_nr].size = size;
- memmap_nr++;
-}
-
-static int __init setup_memmap(char *p)
-{
- char *oldp;
- u64 start_at, mem_size;
-
- if (!p)
- return -EINVAL;
-
- if (!strncmp(p, "exactmap", 8)) {
- pr_err("\"memmap=exactmap\" not valid on tile\n");
- return 0;
- }
-
- oldp = p;
- mem_size = memparse(p, &p);
- if (p == oldp)
- return -EINVAL;
-
- if (*p == '@') {
- pr_err("\"memmap=nn@ss\" (force RAM) invalid on tile\n");
- } else if (*p == '#') {
- pr_err("\"memmap=nn#ss\" (force ACPI data) invalid on tile\n");
- } else if (*p == '$') {
- start_at = memparse(p+1, &p);
- add_memmap_region(start_at, mem_size);
- } else {
- if (mem_size == 0)
- return -EINVAL;
- maxmem_pfn = (mem_size >> HPAGE_SHIFT) <<
- (HPAGE_SHIFT - PAGE_SHIFT);
- }
- return *p == '\0' ? 0 : -EINVAL;
-}
-early_param("memmap", setup_memmap);
-
-static int __init setup_mem(char *str)
-{
- return setup_maxmem(str);
-}
-early_param("mem", setup_mem); /* compatibility with x86 */
-
-static int __init setup_isolnodes(char *str)
-{
- if (str == NULL || nodelist_parse(str, isolnodes) != 0)
- return -EINVAL;
-
- pr_info("Set isolnodes value to '%*pbl'\n",
- nodemask_pr_args(&isolnodes));
- return 0;
-}
-early_param("isolnodes", setup_isolnodes);
-
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
-static int __init setup_pci_reserve(char* str)
-{
- if (str == NULL || kstrtouint(str, 0, &pci_reserve_mb) != 0 ||
- pci_reserve_mb > 3 * 1024)
- return -EINVAL;
-
- pr_info("Reserving %dMB for PCIE root complex mappings\n",
- pci_reserve_mb);
- return 0;
-}
-early_param("pci_reserve", setup_pci_reserve);
-#endif
-
-#ifndef __tilegx__
-/*
- * vmalloc=size forces the vmalloc area to be exactly 'size' bytes.
- * This can be used to increase (or decrease) the vmalloc area.
- */
-static int __init parse_vmalloc(char *arg)
-{
- if (!arg)
- return -EINVAL;
-
- VMALLOC_RESERVE = (memparse(arg, &arg) + PGDIR_SIZE - 1) & PGDIR_MASK;
-
- /* See validate_va() for more on this test. */
- if ((long)_VMALLOC_START >= 0)
- early_panic("\"vmalloc=%#lx\" value too large: maximum %#lx\n",
- VMALLOC_RESERVE, _VMALLOC_END - 0x80000000UL);
-
- return 0;
-}
-early_param("vmalloc", parse_vmalloc);
-#endif
-
-#ifdef CONFIG_HIGHMEM
-/*
- * Determine for each controller where its lowmem is mapped and how much of
- * it is mapped there. On controller zero, the first few megabytes are
- * already mapped in as code at MEM_SV_START, so in principle we could
- * start our data mappings higher up, but for now we don't bother, to avoid
- * additional confusion.
- *
- * One question is whether, on systems with more than 768 Mb and
- * controllers of different sizes, to map in a proportionate amount of
- * each one, or to try to map the same amount from each controller.
- * (E.g. if we have three controllers with 256MB, 1GB, and 256MB
- * respectively, do we map 256MB from each, or do we map 128 MB, 512
- * MB, and 128 MB respectively?) For now we use a proportionate
- * solution like the latter.
- *
- * The VA/PA mapping demands that we align our decisions at 16 MB
- * boundaries so that we can rapidly convert VA to PA.
- */
-static void *__init setup_pa_va_mapping(void)
-{
- unsigned long curr_pages = 0;
- unsigned long vaddr = PAGE_OFFSET;
- nodemask_t highonlynodes = isolnodes;
- int i, j;
-
- memset(pbase_map, -1, sizeof(pbase_map));
- memset(vbase_map, -1, sizeof(vbase_map));
-
- /* Node zero cannot be isolated for LOWMEM purposes. */
- node_clear(0, highonlynodes);
-
- /* Count up the number of pages on non-highonlynodes controllers. */
- mappable_physpages = 0;
- for_each_online_node(i) {
- if (!node_isset(i, highonlynodes))
- mappable_physpages +=
- node_end_pfn[i] - node_start_pfn[i];
- }
-
- for_each_online_node(i) {
- unsigned long start = node_start_pfn[i];
- unsigned long end = node_end_pfn[i];
- unsigned long size = end - start;
- unsigned long vaddr_end;
-
- if (node_isset(i, highonlynodes)) {
- /* Mark this controller as having no lowmem. */
- node_lowmem_end_pfn[i] = start;
- continue;
- }
-
- curr_pages += size;
- if (mappable_physpages > MAXMEM_PFN) {
- vaddr_end = PAGE_OFFSET +
- (((u64)curr_pages * MAXMEM_PFN /
- mappable_physpages)
- << PAGE_SHIFT);
- } else {
- vaddr_end = PAGE_OFFSET + (curr_pages << PAGE_SHIFT);
- }
- for (j = 0; vaddr < vaddr_end; vaddr += HPAGE_SIZE, ++j) {
- unsigned long this_pfn =
- start + (j << HUGETLB_PAGE_ORDER);
- pbase_map[vaddr >> HPAGE_SHIFT] = this_pfn;
- if (vbase_map[__pfn_to_highbits(this_pfn)] ==
- (void *)-1)
- vbase_map[__pfn_to_highbits(this_pfn)] =
- (void *)(vaddr & HPAGE_MASK);
- }
- node_lowmem_end_pfn[i] = start + (j << HUGETLB_PAGE_ORDER);
- BUG_ON(node_lowmem_end_pfn[i] > end);
- }
-
- /* Return highest address of any mapped memory. */
- return (void *)vaddr;
-}
-#endif /* CONFIG_HIGHMEM */
-
-/*
- * Register our most important memory mappings with the debug stub.
- *
- * This is up to 4 mappings for lowmem, one mapping per memory
- * controller, plus one for our text segment.
- */
-static void store_permanent_mappings(void)
-{
- int i;
-
- for_each_online_node(i) {
- HV_PhysAddr pa = ((HV_PhysAddr)node_start_pfn[i]) << PAGE_SHIFT;
-#ifdef CONFIG_HIGHMEM
- HV_PhysAddr high_mapped_pa = node_lowmem_end_pfn[i];
-#else
- HV_PhysAddr high_mapped_pa = node_end_pfn[i];
-#endif
-
- unsigned long pages = high_mapped_pa - node_start_pfn[i];
- HV_VirtAddr addr = (HV_VirtAddr) __va(pa);
- hv_store_mapping(addr, pages << PAGE_SHIFT, pa);
- }
-
- hv_store_mapping((HV_VirtAddr)_text,
- (uint32_t)(_einittext - _text), 0);
-}
-
-/*
- * Use hv_inquire_physical() to populate node_{start,end}_pfn[]
- * and node_online_map, doing suitable sanity-checking.
- * Also set min_low_pfn, max_low_pfn, and max_pfn.
- */
-static void __init setup_memory(void)
-{
- int i, j;
- int highbits_seen[NR_PA_HIGHBIT_VALUES] = { 0 };
-#ifdef CONFIG_HIGHMEM
- long highmem_pages;
-#endif
-#ifndef __tilegx__
- int cap;
-#endif
-#if defined(CONFIG_HIGHMEM) || defined(__tilegx__)
- long lowmem_pages;
-#endif
- unsigned long physpages = 0;
-
- /* We are using a char to hold the cpu_2_node[] mapping */
- BUILD_BUG_ON(MAX_NUMNODES > 127);
-
- /* Discover the ranges of memory available to us */
- for (i = 0; ; ++i) {
- unsigned long start, size, end, highbits;
- HV_PhysAddrRange range = hv_inquire_physical(i);
- if (range.size == 0)
- break;
-#ifdef CONFIG_FLATMEM
- if (i > 0) {
- pr_err("Can't use discontiguous PAs: %#llx..%#llx\n",
- range.size, range.start + range.size);
- continue;
- }
-#endif
-#ifndef __tilegx__
- if ((unsigned long)range.start) {
- pr_err("Range not at 4GB multiple: %#llx..%#llx\n",
- range.start, range.start + range.size);
- continue;
- }
-#endif
- if ((range.start & (HPAGE_SIZE-1)) != 0 ||
- (range.size & (HPAGE_SIZE-1)) != 0) {
- unsigned long long start_pa = range.start;
- unsigned long long orig_size = range.size;
- range.start = (start_pa + HPAGE_SIZE - 1) & HPAGE_MASK;
- range.size -= (range.start - start_pa);
- range.size &= HPAGE_MASK;
- pr_err("Range not hugepage-aligned: %#llx..%#llx: now %#llx-%#llx\n",
- start_pa, start_pa + orig_size,
- range.start, range.start + range.size);
- }
- highbits = __pa_to_highbits(range.start);
- if (highbits >= NR_PA_HIGHBIT_VALUES) {
- pr_err("PA high bits too high: %#llx..%#llx\n",
- range.start, range.start + range.size);
- continue;
- }
- if (highbits_seen[highbits]) {
- pr_err("Range overlaps in high bits: %#llx..%#llx\n",
- range.start, range.start + range.size);
- continue;
- }
- highbits_seen[highbits] = 1;
- if (PFN_DOWN(range.size) > maxnodemem_pfn[i]) {
- int max_size = maxnodemem_pfn[i];
- if (max_size > 0) {
- pr_err("Maxnodemem reduced node %d to %d pages\n",
- i, max_size);
- range.size = PFN_PHYS(max_size);
- } else {
- pr_err("Maxnodemem disabled node %d\n", i);
- continue;
- }
- }
- if (physpages + PFN_DOWN(range.size) > maxmem_pfn) {
- int max_size = maxmem_pfn - physpages;
- if (max_size > 0) {
- pr_err("Maxmem reduced node %d to %d pages\n",
- i, max_size);
- range.size = PFN_PHYS(max_size);
- } else {
- pr_err("Maxmem disabled node %d\n", i);
- continue;
- }
- }
- if (i >= MAX_NUMNODES) {
- pr_err("Too many PA nodes (#%d): %#llx...%#llx\n",
- i, range.size, range.size + range.start);
- continue;
- }
-
- start = range.start >> PAGE_SHIFT;
- size = range.size >> PAGE_SHIFT;
- end = start + size;
-
-#ifndef __tilegx__
- if (((HV_PhysAddr)end << PAGE_SHIFT) !=
- (range.start + range.size)) {
- pr_err("PAs too high to represent: %#llx..%#llx\n",
- range.start, range.start + range.size);
- continue;
- }
-#endif
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
- /*
- * Blocks that overlap the pci reserved region must
- * have enough space to hold the maximum percpu data
- * region at the top of the range. If there isn't
- * enough space above the reserved region, just
- * truncate the node.
- */
- if (start <= pci_reserve_start_pfn &&
- end > pci_reserve_start_pfn) {
- unsigned int per_cpu_size =
- __per_cpu_end - __per_cpu_start;
- unsigned int percpu_pages =
- NR_CPUS * (PFN_UP(per_cpu_size) >> PAGE_SHIFT);
- if (end < pci_reserve_end_pfn + percpu_pages) {
- end = pci_reserve_start_pfn;
- pr_err("PCI mapping region reduced node %d to %ld pages\n",
- i, end - start);
- }
- }
-#endif
-
- for (j = __pfn_to_highbits(start);
- j <= __pfn_to_highbits(end - 1); j++)
- highbits_to_node[j] = i;
-
- node_start_pfn[i] = start;
- node_end_pfn[i] = end;
- node_controller[i] = range.controller;
- physpages += size;
- max_pfn = end;
-
- /* Mark node as online */
- node_set(i, node_online_map);
- node_set(i, node_possible_map);
- }
-
-#ifndef __tilegx__
- /*
- * For 4KB pages, mem_map "struct page" data is 1% of the size
- * of the physical memory, so can be quite big (640 MB for
- * four 16G zones). These structures must be mapped in
- * lowmem, and since we currently cap out at about 768 MB,
- * it's impractical to try to use this much address space.
- * For now, arbitrarily cap the amount of physical memory
- * we're willing to use at 8 million pages (32GB of 4KB pages).
- */
- cap = 8 * 1024 * 1024; /* 8 million pages */
- if (physpages > cap) {
- int num_nodes = num_online_nodes();
- int cap_each = cap / num_nodes;
- unsigned long dropped_pages = 0;
- for (i = 0; i < num_nodes; ++i) {
- int size = node_end_pfn[i] - node_start_pfn[i];
- if (size > cap_each) {
- dropped_pages += (size - cap_each);
- node_end_pfn[i] = node_start_pfn[i] + cap_each;
- }
- }
- physpages -= dropped_pages;
- pr_warn("Only using %ldMB memory - ignoring %ldMB\n",
- physpages >> (20 - PAGE_SHIFT),
- dropped_pages >> (20 - PAGE_SHIFT));
- pr_warn("Consider using a larger page size\n");
- }
-#endif
-
- /* Heap starts just above the last loaded address. */
- min_low_pfn = PFN_UP((unsigned long)_end - PAGE_OFFSET);
-
-#ifdef CONFIG_HIGHMEM
- /* Find where we map lowmem from each controller. */
- high_memory = setup_pa_va_mapping();
-
- /* Set max_low_pfn based on what node 0 can directly address. */
- max_low_pfn = node_lowmem_end_pfn[0];
-
- lowmem_pages = (mappable_physpages > MAXMEM_PFN) ?
- MAXMEM_PFN : mappable_physpages;
- highmem_pages = (long) (physpages - lowmem_pages);
-
- pr_notice("%ldMB HIGHMEM available\n",
- pages_to_mb(highmem_pages > 0 ? highmem_pages : 0));
- pr_notice("%ldMB LOWMEM available\n", pages_to_mb(lowmem_pages));
-#else
- /* Set max_low_pfn based on what node 0 can directly address. */
- max_low_pfn = node_end_pfn[0];
-
-#ifndef __tilegx__
- if (node_end_pfn[0] > MAXMEM_PFN) {
- pr_warn("Only using %ldMB LOWMEM\n", MAXMEM >> 20);
- pr_warn("Use a HIGHMEM enabled kernel\n");
- max_low_pfn = MAXMEM_PFN;
- max_pfn = MAXMEM_PFN;
- node_end_pfn[0] = MAXMEM_PFN;
- } else {
- pr_notice("%ldMB memory available\n",
- pages_to_mb(node_end_pfn[0]));
- }
- for (i = 1; i < MAX_NUMNODES; ++i) {
- node_start_pfn[i] = 0;
- node_end_pfn[i] = 0;
- }
- high_memory = __va(node_end_pfn[0]);
-#else
- lowmem_pages = 0;
- for (i = 0; i < MAX_NUMNODES; ++i) {
- int pages = node_end_pfn[i] - node_start_pfn[i];
- lowmem_pages += pages;
- if (pages)
- high_memory = pfn_to_kaddr(node_end_pfn[i]);
- }
- pr_notice("%ldMB memory available\n", pages_to_mb(lowmem_pages));
-#endif
-#endif
-}
-
-/*
- * On 32-bit machines, we only put bootmem on the low controller,
- * since PAs > 4GB can't be used in bootmem. In principle one could
- * imagine, e.g., multiple 1 GB controllers all of which could support
- * bootmem, but in practice using controllers this small isn't a
- * particularly interesting scenario, so we just keep it simple and
- * use only the first controller for bootmem on 32-bit machines.
- */
-static inline int node_has_bootmem(int nid)
-{
-#ifdef CONFIG_64BIT
- return 1;
-#else
- return nid == 0;
-#endif
-}
-
-static inline unsigned long alloc_bootmem_pfn(int nid,
- unsigned long size,
- unsigned long goal)
-{
- void *kva = __alloc_bootmem_node(NODE_DATA(nid), size,
- PAGE_SIZE, goal);
- unsigned long pfn = kaddr_to_pfn(kva);
- BUG_ON(goal && PFN_PHYS(pfn) != goal);
- return pfn;
-}
-
-static void __init setup_bootmem_allocator_node(int i)
-{
- unsigned long start, end, mapsize, mapstart;
-
- if (node_has_bootmem(i)) {
- NODE_DATA(i)->bdata = &bootmem_node_data[i];
- } else {
- /* Share controller zero's bdata for now. */
- NODE_DATA(i)->bdata = &bootmem_node_data[0];
- return;
- }
-
- /* Skip up to after the bss in node 0. */
- start = (i == 0) ? min_low_pfn : node_start_pfn[i];
-
- /* Only lowmem, if we're a HIGHMEM build. */
-#ifdef CONFIG_HIGHMEM
- end = node_lowmem_end_pfn[i];
-#else
- end = node_end_pfn[i];
-#endif
-
- /* No memory here. */
- if (end == start)
- return;
-
- /* Figure out where the bootmem bitmap is located. */
- mapsize = bootmem_bootmap_pages(end - start);
- if (i == 0) {
- /* Use some space right before the heap on node 0. */
- mapstart = start;
- start += mapsize;
- } else {
- /* Allocate bitmap on node 0 to avoid page table issues. */
- mapstart = alloc_bootmem_pfn(0, PFN_PHYS(mapsize), 0);
- }
-
- /* Initialize a node. */
- init_bootmem_node(NODE_DATA(i), mapstart, start, end);
-
- /* Free all the space back into the allocator. */
- free_bootmem(PFN_PHYS(start), PFN_PHYS(end - start));
-
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
- /*
- * Throw away any memory aliased by the PCI region.
- */
- if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start) {
- start = max(pci_reserve_start_pfn, start);
- end = min(pci_reserve_end_pfn, end);
- reserve_bootmem(PFN_PHYS(start), PFN_PHYS(end - start),
- BOOTMEM_EXCLUSIVE);
- }
-#endif
-}
-
-static void __init setup_bootmem_allocator(void)
-{
- int i;
- for (i = 0; i < MAX_NUMNODES; ++i)
- setup_bootmem_allocator_node(i);
-
- /* Reserve any memory excluded by "memmap" arguments. */
- for (i = 0; i < memmap_nr; ++i) {
- struct memmap_entry *m = &memmap_map[i];
- reserve_bootmem(m->addr, m->size, BOOTMEM_DEFAULT);
- }
-
-#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start) {
- /* Make sure the initrd memory region is not modified. */
- if (reserve_bootmem(initrd_start, initrd_end - initrd_start,
- BOOTMEM_EXCLUSIVE)) {
- pr_crit("The initrd memory region has been polluted. Disabling it.\n");
- initrd_start = 0;
- initrd_end = 0;
- } else {
- /*
- * Translate initrd_start & initrd_end from PA to VA for
- * future access.
- */
- initrd_start += PAGE_OFFSET;
- initrd_end += PAGE_OFFSET;
- }
- }
-#endif
-
-#ifdef CONFIG_KEXEC
- if (crashk_res.start != crashk_res.end)
- reserve_bootmem(crashk_res.start, resource_size(&crashk_res),
- BOOTMEM_DEFAULT);
-#endif
-}
-
-void *__init alloc_remap(int nid, unsigned long size)
-{
- int pages = node_end_pfn[nid] - node_start_pfn[nid];
- void *map = pfn_to_kaddr(node_memmap_pfn[nid]);
- BUG_ON(size != pages * sizeof(struct page));
- memset(map, 0, size);
- return map;
-}
-
-static int __init percpu_size(void)
-{
- int size = __per_cpu_end - __per_cpu_start;
- size += PERCPU_MODULE_RESERVE;
- size += PERCPU_DYNAMIC_EARLY_SIZE;
- if (size < PCPU_MIN_UNIT_SIZE)
- size = PCPU_MIN_UNIT_SIZE;
- size = roundup(size, PAGE_SIZE);
-
- /* In several places we assume the per-cpu data fits on a huge page. */
- BUG_ON(kdata_huge && size > HPAGE_SIZE);
- return size;
-}
-
-static void __init zone_sizes_init(void)
-{
- unsigned long zones_size[MAX_NR_ZONES] = { 0 };
- int size = percpu_size();
- int num_cpus = smp_height * smp_width;
- const unsigned long dma_end = (1UL << (32 - PAGE_SHIFT));
-
- int i;
-
- for (i = 0; i < num_cpus; ++i)
- node_percpu[cpu_to_node(i)] += size;
-
- for_each_online_node(i) {
- unsigned long start = node_start_pfn[i];
- unsigned long end = node_end_pfn[i];
-#ifdef CONFIG_HIGHMEM
- unsigned long lowmem_end = node_lowmem_end_pfn[i];
-#else
- unsigned long lowmem_end = end;
-#endif
- int memmap_size = (end - start) * sizeof(struct page);
- node_free_pfn[i] = start;
-
- /*
- * Set aside pages for per-cpu data and the mem_map array.
- *
- * Since the per-cpu data requires special homecaching,
- * if we are in kdata_huge mode, we put it at the end of
- * the lowmem region. If we're not in kdata_huge mode,
- * we take the per-cpu pages from the bottom of the
- * controller, since that avoids fragmenting a huge page
- * that users might want. We always take the memmap
- * from the bottom of the controller, since with
- * kdata_huge that lets it be under a huge TLB entry.
- *
- * If the user has requested isolnodes for a controller,
- * though, there'll be no lowmem, so we just alloc_bootmem
- * the memmap. There will be no percpu memory either.
- */
- if (i != 0 && node_isset(i, isolnodes)) {
- node_memmap_pfn[i] =
- alloc_bootmem_pfn(0, memmap_size, 0);
- BUG_ON(node_percpu[i] != 0);
- } else if (node_has_bootmem(start)) {
- unsigned long goal = 0;
- node_memmap_pfn[i] =
- alloc_bootmem_pfn(i, memmap_size, 0);
- if (kdata_huge)
- goal = PFN_PHYS(lowmem_end) - node_percpu[i];
- if (node_percpu[i])
- node_percpu_pfn[i] =
- alloc_bootmem_pfn(i, node_percpu[i],
- goal);
- } else {
- /* In non-bootmem zones, just reserve some pages. */
- node_memmap_pfn[i] = node_free_pfn[i];
- node_free_pfn[i] += PFN_UP(memmap_size);
- if (!kdata_huge) {
- node_percpu_pfn[i] = node_free_pfn[i];
- node_free_pfn[i] += PFN_UP(node_percpu[i]);
- } else {
- node_percpu_pfn[i] =
- lowmem_end - PFN_UP(node_percpu[i]);
- }
- }
-
-#ifdef CONFIG_HIGHMEM
- if (start > lowmem_end) {
- zones_size[ZONE_NORMAL] = 0;
- zones_size[ZONE_HIGHMEM] = end - start;
- } else {
- zones_size[ZONE_NORMAL] = lowmem_end - start;
- zones_size[ZONE_HIGHMEM] = end - lowmem_end;
- }
-#else
- zones_size[ZONE_NORMAL] = end - start;
-#endif
-
- if (start < dma_end) {
- zones_size[ZONE_DMA32] = min(zones_size[ZONE_NORMAL],
- dma_end - start);
- zones_size[ZONE_NORMAL] -= zones_size[ZONE_DMA32];
- } else {
- zones_size[ZONE_DMA32] = 0;
- }
-
- /* Take zone metadata from controller 0 if we're isolnode. */
- if (node_isset(i, isolnodes))
- NODE_DATA(i)->bdata = &bootmem_node_data[0];
-
- free_area_init_node(i, zones_size, start, NULL);
- printk(KERN_DEBUG " Normal zone: %ld per-cpu pages\n",
- PFN_UP(node_percpu[i]));
-
- /* Track the type of memory on each node */
- if (zones_size[ZONE_NORMAL] || zones_size[ZONE_DMA32])
- node_set_state(i, N_NORMAL_MEMORY);
-#ifdef CONFIG_HIGHMEM
- if (end != start)
- node_set_state(i, N_HIGH_MEMORY);
-#endif
-
- node_set_online(i);
- }
-}
-
-#ifdef CONFIG_NUMA
-
-/* which logical CPUs are on which nodes */
-struct cpumask node_2_cpu_mask[MAX_NUMNODES] __ro_after_init;
-EXPORT_SYMBOL(node_2_cpu_mask);
-
-/* which node each logical CPU is on */
-char cpu_2_node[NR_CPUS] __ro_after_init __attribute__((aligned(L2_CACHE_BYTES)));
-EXPORT_SYMBOL(cpu_2_node);
-
-/* Return cpu_to_node() except for cpus not yet assigned, which return -1 */
-static int __init cpu_to_bound_node(int cpu, struct cpumask* unbound_cpus)
-{
- if (!cpu_possible(cpu) || cpumask_test_cpu(cpu, unbound_cpus))
- return -1;
- else
- return cpu_to_node(cpu);
-}
-
-/* Return number of immediately-adjacent tiles sharing the same NUMA node. */
-static int __init node_neighbors(int node, int cpu,
- struct cpumask *unbound_cpus)
-{
- int neighbors = 0;
- int w = smp_width;
- int h = smp_height;
- int x = cpu % w;
- int y = cpu / w;
- if (x > 0 && cpu_to_bound_node(cpu-1, unbound_cpus) == node)
- ++neighbors;
- if (x < w-1 && cpu_to_bound_node(cpu+1, unbound_cpus) == node)
- ++neighbors;
- if (y > 0 && cpu_to_bound_node(cpu-w, unbound_cpus) == node)
- ++neighbors;
- if (y < h-1 && cpu_to_bound_node(cpu+w, unbound_cpus) == node)
- ++neighbors;
- return neighbors;
-}
-
-static void __init setup_numa_mapping(void)
-{
- u8 distance[MAX_NUMNODES][NR_CPUS];
- HV_Coord coord;
- int cpu, node, cpus, i, x, y;
- int num_nodes = num_online_nodes();
- struct cpumask unbound_cpus;
- nodemask_t default_nodes;
-
- cpumask_clear(&unbound_cpus);
-
- /* Get set of nodes we will use for defaults */
- nodes_andnot(default_nodes, node_online_map, isolnodes);
- if (nodes_empty(default_nodes)) {
- BUG_ON(!node_isset(0, node_online_map));
- pr_err("Forcing NUMA node zero available as a default node\n");
- node_set(0, default_nodes);
- }
-
- /* Populate the distance[] array */
- memset(distance, -1, sizeof(distance));
- cpu = 0;
- for (coord.y = 0; coord.y < smp_height; ++coord.y) {
- for (coord.x = 0; coord.x < smp_width;
- ++coord.x, ++cpu) {
- BUG_ON(cpu >= nr_cpu_ids);
- if (!cpu_possible(cpu)) {
- cpu_2_node[cpu] = -1;
- continue;
- }
- for_each_node_mask(node, default_nodes) {
- HV_MemoryControllerInfo info =
- hv_inquire_memory_controller(
- coord, node_controller[node]);
- distance[node][cpu] =
- ABS(info.coord.x) + ABS(info.coord.y);
- }
- cpumask_set_cpu(cpu, &unbound_cpus);
- }
- }
- cpus = cpu;
-
- /*
- * Round-robin through the NUMA nodes until all the cpus are
- * assigned. We could be more clever here (e.g. create four
- * sorted linked lists on the same set of cpu nodes, and pull
- * off them in round-robin sequence, removing from all four
- * lists each time) but given the relatively small numbers
- * involved, O(n^2) seem OK for a one-time cost.
- */
- node = first_node(default_nodes);
- while (!cpumask_empty(&unbound_cpus)) {
- int best_cpu = -1;
- int best_distance = INT_MAX;
- for (cpu = 0; cpu < cpus; ++cpu) {
- if (cpumask_test_cpu(cpu, &unbound_cpus)) {
- /*
- * Compute metric, which is how much
- * closer the cpu is to this memory
- * controller than the others, shifted
- * up, and then the number of
- * neighbors already in the node as an
- * epsilon adjustment to try to keep
- * the nodes compact.
- */
- int d = distance[node][cpu] * num_nodes;
- for_each_node_mask(i, default_nodes) {
- if (i != node)
- d -= distance[i][cpu];
- }
- d *= 8; /* allow space for epsilon */
- d -= node_neighbors(node, cpu, &unbound_cpus);
- if (d < best_distance) {
- best_cpu = cpu;
- best_distance = d;
- }
- }
- }
- BUG_ON(best_cpu < 0);
- cpumask_set_cpu(best_cpu, &node_2_cpu_mask[node]);
- cpu_2_node[best_cpu] = node;
- cpumask_clear_cpu(best_cpu, &unbound_cpus);
- node = next_node_in(node, default_nodes);
- }
-
- /* Print out node assignments and set defaults for disabled cpus */
- cpu = 0;
- for (y = 0; y < smp_height; ++y) {
- printk(KERN_DEBUG "NUMA cpu-to-node row %d:", y);
- for (x = 0; x < smp_width; ++x, ++cpu) {
- if (cpu_to_node(cpu) < 0) {
- pr_cont(" -");
- cpu_2_node[cpu] = first_node(default_nodes);
- } else {
- pr_cont(" %d", cpu_to_node(cpu));
- }
- }
- pr_cont("\n");
- }
-}
-
-static struct cpu cpu_devices[NR_CPUS];
-
-static int __init topology_init(void)
-{
- int i;
-
- for_each_online_node(i)
- register_one_node(i);
-
- for (i = 0; i < smp_height * smp_width; ++i)
- register_cpu(&cpu_devices[i], i);
-
- return 0;
-}
-
-subsys_initcall(topology_init);
-
-#else /* !CONFIG_NUMA */
-
-#define setup_numa_mapping() do { } while (0)
-
-#endif /* CONFIG_NUMA */
-
-/*
- * Initialize hugepage support on this cpu. We do this on all cores
- * early in boot: before argument parsing for the boot cpu, and after
- * argument parsing but before the init functions run on the secondaries.
- * So the values we set up here in the hypervisor may be overridden on
- * the boot cpu as arguments are parsed.
- */
-static void init_super_pages(void)
-{
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
- int i;
- for (i = 0; i < HUGE_SHIFT_ENTRIES; ++i)
- hv_set_pte_super_shift(i, huge_shift[i]);
-#endif
-}
-
-/**
- * setup_cpu() - Do all necessary per-cpu, tile-specific initialization.
- * @boot: Is this the boot cpu?
- *
- * Called from setup_arch() on the boot cpu, or online_secondary().
- */
-void setup_cpu(int boot)
-{
- /* The boot cpu sets up its permanent mappings much earlier. */
- if (!boot)
- store_permanent_mappings();
-
- /* Allow asynchronous TLB interrupts. */
-#if CHIP_HAS_TILE_DMA()
- arch_local_irq_unmask(INT_DMATLB_MISS);
- arch_local_irq_unmask(INT_DMATLB_ACCESS);
-#endif
-#ifdef __tilegx__
- arch_local_irq_unmask(INT_SINGLE_STEP_K);
-#endif
-
- /*
- * Allow user access to many generic SPRs, like the cycle
- * counter, PASS/FAIL/DONE, INTERRUPT_CRITICAL_SECTION, etc.
- */
- __insn_mtspr(SPR_MPL_WORLD_ACCESS_SET_0, 1);
-
-#if CHIP_HAS_SN()
- /* Static network is not restricted. */
- __insn_mtspr(SPR_MPL_SN_ACCESS_SET_0, 1);
-#endif
-
- /*
- * Set the MPL for interrupt control 0 & 1 to the corresponding
- * values. This includes access to the SYSTEM_SAVE and EX_CONTEXT
- * SPRs, as well as the interrupt mask.
- */
- __insn_mtspr(SPR_MPL_INTCTRL_0_SET_0, 1);
- __insn_mtspr(SPR_MPL_INTCTRL_1_SET_1, 1);
-
- /* Initialize IRQ support for this cpu. */
- setup_irq_regs();
-
-#ifdef CONFIG_HARDWALL
- /* Reset the network state on this cpu. */
- reset_network_state();
-#endif
-
- init_super_pages();
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-
-static int __initdata set_initramfs_file;
-static char __initdata initramfs_file[128] = "initramfs";
-
-static int __init setup_initramfs_file(char *str)
-{
- if (str == NULL)
- return -EINVAL;
- strncpy(initramfs_file, str, sizeof(initramfs_file) - 1);
- set_initramfs_file = 1;
-
- return 0;
-}
-early_param("initramfs_file", setup_initramfs_file);
-
-/*
- * We look for a file called "initramfs" in the hvfs. If there is one, we
- * allocate some memory for it and it will be unpacked to the initramfs.
- * If it's compressed, the initd code will uncompress it first.
- */
-static void __init load_hv_initrd(void)
-{
- HV_FS_StatInfo stat;
- int fd, rc;
- void *initrd;
-
- /* If initrd has already been set, skip initramfs file in hvfs. */
- if (initrd_start)
- return;
-
- fd = hv_fs_findfile((HV_VirtAddr) initramfs_file);
- if (fd == HV_ENOENT) {
- if (set_initramfs_file) {
- pr_warn("No such hvfs initramfs file '%s'\n",
- initramfs_file);
- return;
- } else {
- /* Try old backwards-compatible name. */
- fd = hv_fs_findfile((HV_VirtAddr)"initramfs.cpio.gz");
- if (fd == HV_ENOENT)
- return;
- }
- }
- BUG_ON(fd < 0);
- stat = hv_fs_fstat(fd);
- BUG_ON(stat.size < 0);
- if (stat.flags & HV_FS_ISDIR) {
- pr_warn("Ignoring hvfs file '%s': it's a directory\n",
- initramfs_file);
- return;
- }
- initrd = alloc_bootmem_pages(stat.size);
- rc = hv_fs_pread(fd, (HV_VirtAddr) initrd, stat.size, 0);
- if (rc != stat.size) {
- pr_err("Error reading %d bytes from hvfs file '%s': %d\n",
- stat.size, initramfs_file, rc);
- free_initrd_mem((unsigned long) initrd, stat.size);
- return;
- }
- initrd_start = (unsigned long) initrd;
- initrd_end = initrd_start + stat.size;
-}
-
-void __init free_initrd_mem(unsigned long begin, unsigned long end)
-{
- free_bootmem_late(__pa(begin), end - begin);
-}
-
-static int __init setup_initrd(char *str)
-{
- char *endp;
- unsigned long initrd_size;
-
- initrd_size = str ? simple_strtoul(str, &endp, 0) : 0;
- if (initrd_size == 0 || *endp != '@')
- return -EINVAL;
-
- initrd_start = simple_strtoul(endp+1, &endp, 0);
- if (initrd_start == 0)
- return -EINVAL;
-
- initrd_end = initrd_start + initrd_size;
-
- return 0;
-}
-early_param("initrd", setup_initrd);
-
-#else
-static inline void load_hv_initrd(void) {}
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-static void __init validate_hv(void)
-{
- /*
- * It may already be too late, but let's check our built-in
- * configuration against what the hypervisor is providing.
- */
- unsigned long glue_size = hv_sysconf(HV_SYSCONF_GLUE_SIZE);
- int hv_page_size = hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL);
- int hv_hpage_size = hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE);
- HV_ASIDRange asid_range;
-
-#ifndef CONFIG_SMP
- HV_Topology topology = hv_inquire_topology();
- BUG_ON(topology.coord.x != 0 || topology.coord.y != 0);
- if (topology.width != 1 || topology.height != 1) {
- pr_warn("Warning: booting UP kernel on %dx%d grid; will ignore all but first tile\n",
- topology.width, topology.height);
- }
-#endif
-
- if (PAGE_OFFSET + HV_GLUE_START_CPA + glue_size > (unsigned long)_text)
- early_panic("Hypervisor glue size %ld is too big!\n",
- glue_size);
- if (hv_page_size != PAGE_SIZE)
- early_panic("Hypervisor page size %#x != our %#lx\n",
- hv_page_size, PAGE_SIZE);
- if (hv_hpage_size != HPAGE_SIZE)
- early_panic("Hypervisor huge page size %#x != our %#lx\n",
- hv_hpage_size, HPAGE_SIZE);
-
-#ifdef CONFIG_SMP
- /*
- * Some hypervisor APIs take a pointer to a bitmap array
- * whose size is at least the number of cpus on the chip.
- * We use a struct cpumask for this, so it must be big enough.
- */
- if ((smp_height * smp_width) > nr_cpu_ids)
- early_panic("Hypervisor %d x %d grid too big for Linux NR_CPUS %u\n",
- smp_height, smp_width, nr_cpu_ids);
-#endif
-
- /*
- * Check that we're using allowed ASIDs, and initialize the
- * various asid variables to their appropriate initial states.
- */
- asid_range = hv_inquire_asid(0);
- min_asid = asid_range.start;
- __this_cpu_write(current_asid, min_asid);
- max_asid = asid_range.start + asid_range.size - 1;
-
- if (hv_confstr(HV_CONFSTR_CHIP_MODEL, (HV_VirtAddr)chip_model,
- sizeof(chip_model)) < 0) {
- pr_err("Warning: HV_CONFSTR_CHIP_MODEL not available\n");
- strlcpy(chip_model, "unknown", sizeof(chip_model));
- }
-}
-
-static void __init validate_va(void)
-{
-#ifndef __tilegx__ /* FIXME: GX: probably some validation relevant here */
- /*
- * Similarly, make sure we're only using allowed VAs.
- * We assume we can contiguously use MEM_USER_INTRPT .. MEM_HV_START,
- * and 0 .. KERNEL_HIGH_VADDR.
- * In addition, make sure we CAN'T use the end of memory, since
- * we use the last chunk of each pgd for the pgd_list.
- */
- int i, user_kernel_ok = 0;
- unsigned long max_va = 0;
- unsigned long list_va =
- ((PGD_LIST_OFFSET / sizeof(pgd_t)) << PGDIR_SHIFT);
-
- for (i = 0; ; ++i) {
- HV_VirtAddrRange range = hv_inquire_virtual(i);
- if (range.size == 0)
- break;
- if (range.start <= MEM_USER_INTRPT &&
- range.start + range.size >= MEM_HV_START)
- user_kernel_ok = 1;
- if (range.start == 0)
- max_va = range.size;
- BUG_ON(range.start + range.size > list_va);
- }
- if (!user_kernel_ok)
- early_panic("Hypervisor not configured for user/kernel VAs\n");
- if (max_va == 0)
- early_panic("Hypervisor not configured for low VAs\n");
- if (max_va < KERNEL_HIGH_VADDR)
- early_panic("Hypervisor max VA %#lx smaller than %#lx\n",
- max_va, KERNEL_HIGH_VADDR);
-
- /* Kernel PCs must have their high bit set; see intvec.S. */
- if ((long)VMALLOC_START >= 0)
- early_panic("Linux VMALLOC region below the 2GB line (%#lx)!\n"
- "Reconfigure the kernel with smaller VMALLOC_RESERVE\n",
- VMALLOC_START);
-#endif
-}
-
-/*
- * cpu_lotar_map lists all the cpus that are valid for the supervisor
- * to cache data on at a page level, i.e. what cpus can be placed in
- * the LOTAR field of a PTE. It is equivalent to the set of possible
- * cpus plus any other cpus that are willing to share their cache.
- * It is set by hv_inquire_tiles(HV_INQ_TILES_LOTAR).
- */
-struct cpumask __ro_after_init cpu_lotar_map;
-EXPORT_SYMBOL(cpu_lotar_map);
-
-/*
- * hash_for_home_map lists all the tiles that hash-for-home data
- * will be cached on. Note that this may includes tiles that are not
- * valid for this supervisor to use otherwise (e.g. if a hypervisor
- * device is being shared between multiple supervisors).
- * It is set by hv_inquire_tiles(HV_INQ_TILES_HFH_CACHE).
- */
-struct cpumask hash_for_home_map;
-EXPORT_SYMBOL(hash_for_home_map);
-
-/*
- * cpu_cacheable_map lists all the cpus whose caches the hypervisor can
- * flush on our behalf. It is set to cpu_possible_mask OR'ed with
- * hash_for_home_map, and it is what should be passed to
- * hv_flush_remote() to flush all caches. Note that if there are
- * dedicated hypervisor driver tiles that have authorized use of their
- * cache, those tiles will only appear in cpu_lotar_map, NOT in
- * cpu_cacheable_map, as they are a special case.
- */
-struct cpumask __ro_after_init cpu_cacheable_map;
-EXPORT_SYMBOL(cpu_cacheable_map);
-
-static __initdata struct cpumask disabled_map;
-
-static int __init disabled_cpus(char *str)
-{
- int boot_cpu = smp_processor_id();
-
- if (str == NULL || cpulist_parse_crop(str, &disabled_map) != 0)
- return -EINVAL;
- if (cpumask_test_cpu(boot_cpu, &disabled_map)) {
- pr_err("disabled_cpus: can't disable boot cpu %d\n", boot_cpu);
- cpumask_clear_cpu(boot_cpu, &disabled_map);
- }
- return 0;
-}
-
-early_param("disabled_cpus", disabled_cpus);
-
-void __init print_disabled_cpus(void)
-{
- if (!cpumask_empty(&disabled_map))
- pr_info("CPUs not available for Linux: %*pbl\n",
- cpumask_pr_args(&disabled_map));
-}
-
-static void __init setup_cpu_maps(void)
-{
- struct cpumask hv_disabled_map, cpu_possible_init;
- int boot_cpu = smp_processor_id();
- int cpus, i, rc;
-
- /* Learn which cpus are allowed by the hypervisor. */
- rc = hv_inquire_tiles(HV_INQ_TILES_AVAIL,
- (HV_VirtAddr) cpumask_bits(&cpu_possible_init),
- sizeof(cpu_cacheable_map));
- if (rc < 0)
- early_panic("hv_inquire_tiles(AVAIL) failed: rc %d\n", rc);
- if (!cpumask_test_cpu(boot_cpu, &cpu_possible_init))
- early_panic("Boot CPU %d disabled by hypervisor!\n", boot_cpu);
-
- /* Compute the cpus disabled by the hvconfig file. */
- cpumask_complement(&hv_disabled_map, &cpu_possible_init);
-
- /* Include them with the cpus disabled by "disabled_cpus". */
- cpumask_or(&disabled_map, &disabled_map, &hv_disabled_map);
-
- /*
- * Disable every cpu after "setup_max_cpus". But don't mark
- * as disabled the cpus that are outside of our initial rectangle,
- * since that turns out to be confusing.
- */
- cpus = 1; /* this cpu */
- cpumask_set_cpu(boot_cpu, &disabled_map); /* ignore this cpu */
- for (i = 0; cpus < setup_max_cpus; ++i)
- if (!cpumask_test_cpu(i, &disabled_map))
- ++cpus;
- for (; i < smp_height * smp_width; ++i)
- cpumask_set_cpu(i, &disabled_map);
- cpumask_clear_cpu(boot_cpu, &disabled_map); /* reset this cpu */
- for (i = smp_height * smp_width; i < NR_CPUS; ++i)
- cpumask_clear_cpu(i, &disabled_map);
-
- /*
- * Setup cpu_possible map as every cpu allocated to us, minus
- * the results of any "disabled_cpus" settings.
- */
- cpumask_andnot(&cpu_possible_init, &cpu_possible_init, &disabled_map);
- init_cpu_possible(&cpu_possible_init);
-
- /* Learn which cpus are valid for LOTAR caching. */
- rc = hv_inquire_tiles(HV_INQ_TILES_LOTAR,
- (HV_VirtAddr) cpumask_bits(&cpu_lotar_map),
- sizeof(cpu_lotar_map));
- if (rc < 0) {
- pr_err("warning: no HV_INQ_TILES_LOTAR; using AVAIL\n");
- cpu_lotar_map = *cpu_possible_mask;
- }
-
- /* Retrieve set of CPUs used for hash-for-home caching */
- rc = hv_inquire_tiles(HV_INQ_TILES_HFH_CACHE,
- (HV_VirtAddr) hash_for_home_map.bits,
- sizeof(hash_for_home_map));
- if (rc < 0)
- early_panic("hv_inquire_tiles(HFH_CACHE) failed: rc %d\n", rc);
- cpumask_or(&cpu_cacheable_map, cpu_possible_mask, &hash_for_home_map);
-}
-
-
-static int __init dataplane(char *str)
-{
- pr_warn("WARNING: dataplane support disabled in this kernel\n");
- return 0;
-}
-
-early_param("dataplane", dataplane);
-
-#ifdef CONFIG_NO_HZ_FULL
-/* Warn if hypervisor shared cpus are marked as nohz_full. */
-static int __init check_nohz_full_cpus(void)
-{
- struct cpumask shared;
- int cpu;
-
- if (hv_inquire_tiles(HV_INQ_TILES_SHARED,
- (HV_VirtAddr) shared.bits, sizeof(shared)) < 0) {
- pr_warn("WARNING: No support for inquiring hv shared tiles\n");
- return 0;
- }
- for_each_cpu(cpu, &shared) {
- if (tick_nohz_full_cpu(cpu))
- pr_warn("WARNING: nohz_full cpu %d receives hypervisor interrupts!\n",
- cpu);
- }
- return 0;
-}
-arch_initcall(check_nohz_full_cpus);
-#endif
-
-#ifdef CONFIG_CMDLINE_BOOL
-static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
-#endif
-
-void __init setup_arch(char **cmdline_p)
-{
- int len;
-
-#if defined(CONFIG_CMDLINE_BOOL) && defined(CONFIG_CMDLINE_OVERRIDE)
- len = hv_get_command_line((HV_VirtAddr) boot_command_line,
- COMMAND_LINE_SIZE);
- if (boot_command_line[0])
- pr_warn("WARNING: ignoring dynamic command line \"%s\"\n",
- boot_command_line);
- strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
-#else
- char *hv_cmdline;
-#if defined(CONFIG_CMDLINE_BOOL)
- if (builtin_cmdline[0]) {
- int builtin_len = strlcpy(boot_command_line, builtin_cmdline,
- COMMAND_LINE_SIZE);
- if (builtin_len < COMMAND_LINE_SIZE-1)
- boot_command_line[builtin_len++] = ' ';
- hv_cmdline = &boot_command_line[builtin_len];
- len = COMMAND_LINE_SIZE - builtin_len;
- } else
-#endif
- {
- hv_cmdline = boot_command_line;
- len = COMMAND_LINE_SIZE;
- }
- len = hv_get_command_line((HV_VirtAddr) hv_cmdline, len);
- if (len < 0 || len > COMMAND_LINE_SIZE)
- early_panic("hv_get_command_line failed: %d\n", len);
-#endif
-
- *cmdline_p = boot_command_line;
-
- /* Set disabled_map and setup_max_cpus very early */
- parse_early_param();
-
- /* Make sure the kernel is compatible with the hypervisor. */
- validate_hv();
- validate_va();
-
- setup_cpu_maps();
-
-
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
- /*
- * Initialize the PCI structures. This is done before memory
- * setup so that we know whether or not a pci_reserve region
- * is necessary.
- */
- if (tile_pci_init() == 0)
- pci_reserve_mb = 0;
-
- /* PCI systems reserve a region just below 4GB for mapping iomem. */
- pci_reserve_end_pfn = (1 << (32 - PAGE_SHIFT));
- pci_reserve_start_pfn = pci_reserve_end_pfn -
- (pci_reserve_mb << (20 - PAGE_SHIFT));
-#endif
-
- init_mm.start_code = (unsigned long) _text;
- init_mm.end_code = (unsigned long) _etext;
- init_mm.end_data = (unsigned long) _edata;
- init_mm.brk = (unsigned long) _end;
-
- setup_memory();
- store_permanent_mappings();
- setup_bootmem_allocator();
-
- /*
- * NOTE: before this point _nobody_ is allowed to allocate
- * any memory using the bootmem allocator.
- */
-
-#ifdef CONFIG_SWIOTLB
- swiotlb_init(0);
-#endif
-
- paging_init();
- setup_numa_mapping();
- zone_sizes_init();
- set_page_homes();
- setup_cpu(1);
- setup_clock();
- load_hv_initrd();
-}
-
-
-/*
- * Set up per-cpu memory.
- */
-
-unsigned long __per_cpu_offset[NR_CPUS] __ro_after_init;
-EXPORT_SYMBOL(__per_cpu_offset);
-
-static size_t __initdata pfn_offset[MAX_NUMNODES] = { 0 };
-static unsigned long __initdata percpu_pfn[NR_CPUS] = { 0 };
-
-/*
- * As the percpu code allocates pages, we return the pages from the
- * end of the node for the specified cpu.
- */
-static void *__init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
-{
- int nid = cpu_to_node(cpu);
- unsigned long pfn = node_percpu_pfn[nid] + pfn_offset[nid];
-
- BUG_ON(size % PAGE_SIZE != 0);
- pfn_offset[nid] += size / PAGE_SIZE;
- BUG_ON(node_percpu[nid] < size);
- node_percpu[nid] -= size;
- if (percpu_pfn[cpu] == 0)
- percpu_pfn[cpu] = pfn;
- return pfn_to_kaddr(pfn);
-}
-
-/*
- * Pages reserved for percpu memory are not freeable, and in any case we are
- * on a short path to panic() in setup_per_cpu_area() at this point anyway.
- */
-static void __init pcpu_fc_free(void *ptr, size_t size)
-{
-}
-
-/*
- * Set up vmalloc page tables using bootmem for the percpu code.
- */
-static void __init pcpu_fc_populate_pte(unsigned long addr)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
-
- BUG_ON(pgd_addr_invalid(addr));
- if (addr < VMALLOC_START || addr >= VMALLOC_END)
- panic("PCPU addr %#lx outside vmalloc range %#lx..%#lx; try increasing CONFIG_VMALLOC_RESERVE\n",
- addr, VMALLOC_START, VMALLOC_END);
-
- pgd = swapper_pg_dir + pgd_index(addr);
- pud = pud_offset(pgd, addr);
- BUG_ON(!pud_present(*pud));
- pmd = pmd_offset(pud, addr);
- if (pmd_present(*pmd)) {
- BUG_ON(pmd_huge_page(*pmd));
- } else {
- pte = __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE,
- HV_PAGE_TABLE_ALIGN, 0);
- pmd_populate_kernel(&init_mm, pmd, pte);
- }
-}
-
-void __init setup_per_cpu_areas(void)
-{
- struct page *pg;
- unsigned long delta, pfn, lowmem_va;
- unsigned long size = percpu_size();
- char *ptr;
- int rc, cpu, i;
-
- rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE, pcpu_fc_alloc,
- pcpu_fc_free, pcpu_fc_populate_pte);
- if (rc < 0)
- panic("Cannot initialize percpu area (err=%d)", rc);
-
- delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
- for_each_possible_cpu(cpu) {
- __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
-
- /* finv the copy out of cache so we can change homecache */
- ptr = pcpu_base_addr + pcpu_unit_offsets[cpu];
- __finv_buffer(ptr, size);
- pfn = percpu_pfn[cpu];
-
- /* Rewrite the page tables to cache on that cpu */
- pg = pfn_to_page(pfn);
- for (i = 0; i < size; i += PAGE_SIZE, ++pfn, ++pg) {
-
- /* Update the vmalloc mapping and page home. */
- unsigned long addr = (unsigned long)ptr + i;
- pte_t *ptep = virt_to_kpte(addr);
- pte_t pte = *ptep;
- BUG_ON(pfn != pte_pfn(pte));
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_TILE_L3);
- pte = set_remote_cache_cpu(pte, cpu);
- set_pte_at(&init_mm, addr, ptep, pte);
-
- /* Update the lowmem mapping for consistency. */
- lowmem_va = (unsigned long)pfn_to_kaddr(pfn);
- ptep = virt_to_kpte(lowmem_va);
- if (pte_huge(*ptep)) {
- printk(KERN_DEBUG "early shatter of huge page at %#lx\n",
- lowmem_va);
- shatter_pmd((pmd_t *)ptep);
- ptep = virt_to_kpte(lowmem_va);
- BUG_ON(pte_huge(*ptep));
- }
- BUG_ON(pfn != pte_pfn(*ptep));
- set_pte_at(&init_mm, lowmem_va, ptep, pte);
- }
- }
-
- /* Set our thread pointer appropriately. */
- set_my_cpu_offset(__per_cpu_offset[smp_processor_id()]);
-
- /* Make sure the finv's have completed. */
- mb_incoherent();
-
- /* Flush the TLB so we reference it properly from here on out. */
- local_flush_tlb_all();
-}
-
-static struct resource data_resource = {
- .name = "Kernel data",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
-};
-
-static struct resource code_resource = {
- .name = "Kernel code",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
-};
-
-/*
- * On Pro, we reserve all resources above 4GB so that PCI won't try to put
- * mappings above 4GB.
- */
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
-static struct resource* __init
-insert_non_bus_resource(void)
-{
- struct resource *res =
- kzalloc(sizeof(struct resource), GFP_ATOMIC);
- if (!res)
- return NULL;
- res->name = "Non-Bus Physical Address Space";
- res->start = (1ULL << 32);
- res->end = -1LL;
- res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
- if (insert_resource(&iomem_resource, res)) {
- kfree(res);
- return NULL;
- }
- return res;
-}
-#endif
-
-static struct resource* __init
-insert_ram_resource(u64 start_pfn, u64 end_pfn, bool reserved)
-{
- struct resource *res =
- kzalloc(sizeof(struct resource), GFP_ATOMIC);
- if (!res)
- return NULL;
- res->start = start_pfn << PAGE_SHIFT;
- res->end = (end_pfn << PAGE_SHIFT) - 1;
- res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
- if (reserved) {
- res->name = "Reserved";
- } else {
- res->name = "System RAM";
- res->flags |= IORESOURCE_SYSRAM;
- }
- if (insert_resource(&iomem_resource, res)) {
- kfree(res);
- return NULL;
- }
- return res;
-}
-
-/*
- * Request address space for all standard resources
- *
- * If the system includes PCI root complex drivers, we need to create
- * a window just below 4GB where PCI BARs can be mapped.
- */
-static int __init request_standard_resources(void)
-{
- int i;
- enum { CODE_DELTA = MEM_SV_START - PAGE_OFFSET };
-
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
- insert_non_bus_resource();
-#endif
-
- for_each_online_node(i) {
- u64 start_pfn = node_start_pfn[i];
- u64 end_pfn = node_end_pfn[i];
-
-#if defined(CONFIG_PCI) && !defined(__tilegx__)
- if (start_pfn <= pci_reserve_start_pfn &&
- end_pfn > pci_reserve_start_pfn) {
- if (end_pfn > pci_reserve_end_pfn)
- insert_ram_resource(pci_reserve_end_pfn,
- end_pfn, 0);
- end_pfn = pci_reserve_start_pfn;
- }
-#endif
- insert_ram_resource(start_pfn, end_pfn, 0);
- }
-
- code_resource.start = __pa(_text - CODE_DELTA);
- code_resource.end = __pa(_etext - CODE_DELTA)-1;
- data_resource.start = __pa(_sdata);
- data_resource.end = __pa(_end)-1;
-
- insert_resource(&iomem_resource, &code_resource);
- insert_resource(&iomem_resource, &data_resource);
-
- /* Mark any "memmap" regions busy for the resource manager. */
- for (i = 0; i < memmap_nr; ++i) {
- struct memmap_entry *m = &memmap_map[i];
- insert_ram_resource(PFN_DOWN(m->addr),
- PFN_UP(m->addr + m->size - 1), 1);
- }
-
-#ifdef CONFIG_KEXEC
- insert_resource(&iomem_resource, &crashk_res);
-#endif
-
- return 0;
-}
-
-subsys_initcall(request_standard_resources);
diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c
deleted file mode 100644
index f2bf557bb005..000000000000
--- a/arch/tile/kernel/signal.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/*
- * Copyright (C) 1991, 1992 Linus Torvalds
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task_stack.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/personality.h>
-#include <linux/suspend.h>
-#include <linux/ptrace.h>
-#include <linux/elf.h>
-#include <linux/compat.h>
-#include <linux/syscalls.h>
-#include <linux/uaccess.h>
-#include <asm/processor.h>
-#include <asm/ucontext.h>
-#include <asm/sigframe.h>
-#include <asm/syscalls.h>
-#include <asm/vdso.h>
-#include <arch/interrupts.h>
-
-#define DEBUG_SIG 0
-
-/*
- * Do a signal return; undo the signal stack.
- */
-
-int restore_sigcontext(struct pt_regs *regs,
- struct sigcontext __user *sc)
-{
- int err;
-
- /* Always make any pending restarted system calls return -EINTR */
- current->restart_block.fn = do_no_restart_syscall;
-
- /*
- * Enforce that sigcontext is like pt_regs, and doesn't mess
- * up our stack alignment rules.
- */
- BUILD_BUG_ON(sizeof(struct sigcontext) != sizeof(struct pt_regs));
- BUILD_BUG_ON(sizeof(struct sigcontext) % 8 != 0);
- err = __copy_from_user(regs, sc, sizeof(*regs));
-
- /* Ensure that the PL is always set to USER_PL. */
- regs->ex1 = PL_ICS_EX1(USER_PL, EX1_ICS(regs->ex1));
-
- regs->faultnum = INT_SWINT_1_SIGRETURN;
-
- return err;
-}
-
-void signal_fault(const char *type, struct pt_regs *regs,
- void __user *frame, int sig)
-{
- trace_unhandled_signal(type, regs, (unsigned long)frame, SIGSEGV);
- force_sigsegv(sig, current);
-}
-
-/* The assembly shim for this function arranges to ignore the return value. */
-SYSCALL_DEFINE0(rt_sigreturn)
-{
- struct pt_regs *regs = current_pt_regs();
- struct rt_sigframe __user *frame =
- (struct rt_sigframe __user *)(regs->sp);
- sigset_t set;
-
- if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
- goto badframe;
- if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
- goto badframe;
-
- set_current_blocked(&set);
-
- if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
- goto badframe;
-
- if (restore_altstack(&frame->uc.uc_stack))
- goto badframe;
-
- return 0;
-
-badframe:
- signal_fault("bad sigreturn frame", regs, frame, 0);
- return 0;
-}
-
-/*
- * Set up a signal frame.
- */
-
-int setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs)
-{
- return __copy_to_user(sc, regs, sizeof(*regs));
-}
-
-/*
- * Determine which stack to use..
- */
-static inline void __user *get_sigframe(struct k_sigaction *ka,
- struct pt_regs *regs,
- size_t frame_size)
-{
- unsigned long sp;
-
- /* Default to using normal stack */
- sp = regs->sp;
-
- /*
- * If we are on the alternate signal stack and would overflow
- * it, don't. Return an always-bogus address instead so we
- * will die with SIGSEGV.
- */
- if (on_sig_stack(sp) && !likely(on_sig_stack(sp - frame_size)))
- return (void __user __force *)-1UL;
-
- /* This is the X/Open sanctioned signal stack switching. */
- if (ka->sa.sa_flags & SA_ONSTACK) {
- if (sas_ss_flags(sp) == 0)
- sp = current->sas_ss_sp + current->sas_ss_size;
- }
-
- sp -= frame_size;
- /*
- * Align the stack pointer according to the TILE ABI,
- * i.e. so that on function entry (sp & 15) == 0.
- */
- sp &= -16UL;
- return (void __user *) sp;
-}
-
-static int setup_rt_frame(struct ksignal *ksig, sigset_t *set,
- struct pt_regs *regs)
-{
- unsigned long restorer;
- struct rt_sigframe __user *frame;
- int err = 0, sig = ksig->sig;
-
- frame = get_sigframe(&ksig->ka, regs, sizeof(*frame));
-
- if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
- goto err;
-
- /* Always write at least the signal number for the stack backtracer. */
- if (ksig->ka.sa.sa_flags & SA_SIGINFO) {
- /* At sigreturn time, restore the callee-save registers too. */
- err |= copy_siginfo_to_user(&frame->info, &ksig->info);
- regs->flags |= PT_FLAGS_RESTORE_REGS;
- } else {
- err |= __put_user(ksig->info.si_signo, &frame->info.si_signo);
- }
-
- /* Create the ucontext. */
- err |= __clear_user(&frame->save_area, sizeof(frame->save_area));
- err |= __put_user(0, &frame->uc.uc_flags);
- err |= __put_user(NULL, &frame->uc.uc_link);
- err |= __save_altstack(&frame->uc.uc_stack, regs->sp);
- err |= setup_sigcontext(&frame->uc.uc_mcontext, regs);
- err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
- if (err)
- goto err;
-
- restorer = VDSO_SYM(&__vdso_rt_sigreturn);
- if (ksig->ka.sa.sa_flags & SA_RESTORER)
- restorer = (unsigned long) ksig->ka.sa.sa_restorer;
-
- /*
- * Set up registers for signal handler.
- * Registers that we don't modify keep the value they had from
- * user-space at the time we took the signal.
- * We always pass siginfo and mcontext, regardless of SA_SIGINFO,
- * since some things rely on this (e.g. glibc's debug/segfault.c).
- */
- regs->pc = (unsigned long) ksig->ka.sa.sa_handler;
- regs->ex1 = PL_ICS_EX1(USER_PL, 1); /* set crit sec in handler */
- regs->sp = (unsigned long) frame;
- regs->lr = restorer;
- regs->regs[0] = (unsigned long) sig;
- regs->regs[1] = (unsigned long) &frame->info;
- regs->regs[2] = (unsigned long) &frame->uc;
- regs->flags |= PT_FLAGS_CALLER_SAVES;
- return 0;
-
-err:
- trace_unhandled_signal("bad sigreturn frame", regs,
- (unsigned long)frame, SIGSEGV);
- return -EFAULT;
-}
-
-/*
- * OK, we're invoking a handler
- */
-
-static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
-{
- sigset_t *oldset = sigmask_to_save();
- int ret;
-
- /* Are we from a system call? */
- if (regs->faultnum == INT_SWINT_1) {
- /* If so, check system call restarting.. */
- switch (regs->regs[0]) {
- case -ERESTART_RESTARTBLOCK:
- case -ERESTARTNOHAND:
- regs->regs[0] = -EINTR;
- break;
-
- case -ERESTARTSYS:
- if (!(ksig->ka.sa.sa_flags & SA_RESTART)) {
- regs->regs[0] = -EINTR;
- break;
- }
- /* fallthrough */
- case -ERESTARTNOINTR:
- /* Reload caller-saves to restore r0..r5 and r10. */
- regs->flags |= PT_FLAGS_CALLER_SAVES;
- regs->regs[0] = regs->orig_r0;
- regs->pc -= 8;
- }
- }
-
- /* Set up the stack frame */
-#ifdef CONFIG_COMPAT
- if (is_compat_task())
- ret = compat_setup_rt_frame(ksig, oldset, regs);
- else
-#endif
- ret = setup_rt_frame(ksig, oldset, regs);
-
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
-}
-
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- */
-void do_signal(struct pt_regs *regs)
-{
- struct ksignal ksig;
-
- /*
- * i386 will check if we're coming from kernel mode and bail out
- * here. In my experience this just turns weird crashes into
- * weird spin-hangs. But if we find a case where this seems
- * helpful, we can reinstate the check on "!user_mode(regs)".
- */
-
- if (get_signal(&ksig)) {
- /* Whee! Actually deliver the signal. */
- handle_signal(&ksig, regs);
- goto done;
- }
-
- /* Did we come from a system call? */
- if (regs->faultnum == INT_SWINT_1) {
- /* Restart the system call - no handlers present */
- switch (regs->regs[0]) {
- case -ERESTARTNOHAND:
- case -ERESTARTSYS:
- case -ERESTARTNOINTR:
- regs->flags |= PT_FLAGS_CALLER_SAVES;
- regs->regs[0] = regs->orig_r0;
- regs->pc -= 8;
- break;
-
- case -ERESTART_RESTARTBLOCK:
- regs->flags |= PT_FLAGS_CALLER_SAVES;
- regs->regs[TREG_SYSCALL_NR] = __NR_restart_syscall;
- regs->pc -= 8;
- break;
- }
- }
-
- /* If there's no signal to deliver, just put the saved sigmask back. */
- restore_saved_sigmask();
-
-done:
- /* Avoid double syscall restart if there are nested signals. */
- regs->faultnum = INT_SWINT_1_SIGRETURN;
-}
-
-int show_unhandled_signals = 1;
-
-static int __init crashinfo(char *str)
-{
- const char *word;
-
- if (*str == '\0')
- show_unhandled_signals = 2;
- else if (*str != '=' || kstrtoint(++str, 0, &show_unhandled_signals) != 0)
- return 0;
-
- switch (show_unhandled_signals) {
- case 0:
- word = "No";
- break;
- case 1:
- word = "One-line";
- break;
- default:
- word = "Detailed";
- break;
- }
- pr_info("%s crash reports will be generated on the console\n", word);
- return 1;
-}
-__setup("crashinfo", crashinfo);
-
-static void dump_mem(void __user *address)
-{
- void __user *addr;
- enum { region_size = 256, bytes_per_line = 16 };
- int i, j, k;
- int found_readable_mem = 0;
-
- if (!access_ok(VERIFY_READ, address, 1)) {
- pr_err("Not dumping at address 0x%lx (kernel address)\n",
- (unsigned long)address);
- return;
- }
-
- addr = (void __user *)
- (((unsigned long)address & -bytes_per_line) - region_size/2);
- if (addr > address)
- addr = NULL;
- for (i = 0; i < region_size;
- addr += bytes_per_line, i += bytes_per_line) {
- unsigned char buf[bytes_per_line];
- char line[100];
- if (copy_from_user(buf, addr, bytes_per_line))
- continue;
- if (!found_readable_mem) {
- pr_err("Dumping memory around address 0x%lx:\n",
- (unsigned long)address);
- found_readable_mem = 1;
- }
- j = sprintf(line, REGFMT ":", (unsigned long)addr);
- for (k = 0; k < bytes_per_line; ++k)
- j += sprintf(&line[j], " %02x", buf[k]);
- pr_err("%s\n", line);
- }
- if (!found_readable_mem)
- pr_err("No readable memory around address 0x%lx\n",
- (unsigned long)address);
-}
-
-void trace_unhandled_signal(const char *type, struct pt_regs *regs,
- unsigned long address, int sig)
-{
- struct task_struct *tsk = current;
-
- if (show_unhandled_signals == 0)
- return;
-
- /* If the signal is handled, don't show it here. */
- if (!is_global_init(tsk)) {
- void __user *handler =
- tsk->sighand->action[sig-1].sa.sa_handler;
- if (handler != SIG_IGN && handler != SIG_DFL)
- return;
- }
-
- /* Rate-limit the one-line output, not the detailed output. */
- if (show_unhandled_signals <= 1 && !printk_ratelimit())
- return;
-
- printk("%s%s[%d]: %s at %lx pc "REGFMT" signal %d",
- task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
- tsk->comm, task_pid_nr(tsk), type, address, regs->pc, sig);
-
- print_vma_addr(KERN_CONT " in ", regs->pc);
-
- printk(KERN_CONT "\n");
-
- if (show_unhandled_signals > 1) {
- switch (sig) {
- case SIGILL:
- case SIGFPE:
- case SIGSEGV:
- case SIGBUS:
- pr_err("User crash: signal %d, trap %ld, address 0x%lx\n",
- sig, regs->faultnum, address);
- show_regs(regs);
- dump_mem((void __user *)address);
- break;
- default:
- pr_err("User crash: signal %d, trap %ld\n",
- sig, regs->faultnum);
- break;
- }
- }
-}
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c
deleted file mode 100644
index 479d8033a801..000000000000
--- a/arch/tile/kernel/single_step.c
+++ /dev/null
@@ -1,786 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * A code-rewriter that enables instruction single-stepping.
- */
-
-#include <linux/smp.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/thread_info.h>
-#include <linux/uaccess.h>
-#include <linux/mman.h>
-#include <linux/types.h>
-#include <linux/err.h>
-#include <linux/prctl.h>
-#include <asm/cacheflush.h>
-#include <asm/traps.h>
-#include <linux/uaccess.h>
-#include <asm/unaligned.h>
-#include <arch/abi.h>
-#include <arch/spr_def.h>
-#include <arch/opcode.h>
-
-
-#ifndef __tilegx__ /* Hardware support for single step unavailable. */
-
-#define signExtend17(val) sign_extend((val), 17)
-#define TILE_X1_MASK (0xffffffffULL << 31)
-
-enum mem_op {
- MEMOP_NONE,
- MEMOP_LOAD,
- MEMOP_STORE,
- MEMOP_LOAD_POSTINCR,
- MEMOP_STORE_POSTINCR
-};
-
-static inline tilepro_bundle_bits set_BrOff_X1(tilepro_bundle_bits n,
- s32 offset)
-{
- tilepro_bundle_bits result;
-
- /* mask out the old offset */
- tilepro_bundle_bits mask = create_BrOff_X1(-1);
- result = n & (~mask);
-
- /* or in the new offset */
- result |= create_BrOff_X1(offset);
-
- return result;
-}
-
-static inline tilepro_bundle_bits move_X1(tilepro_bundle_bits n, int dest,
- int src)
-{
- tilepro_bundle_bits result;
- tilepro_bundle_bits op;
-
- result = n & (~TILE_X1_MASK);
-
- op = create_Opcode_X1(SPECIAL_0_OPCODE_X1) |
- create_RRROpcodeExtension_X1(OR_SPECIAL_0_OPCODE_X1) |
- create_Dest_X1(dest) |
- create_SrcB_X1(TREG_ZERO) |
- create_SrcA_X1(src) ;
-
- result |= op;
- return result;
-}
-
-static inline tilepro_bundle_bits nop_X1(tilepro_bundle_bits n)
-{
- return move_X1(n, TREG_ZERO, TREG_ZERO);
-}
-
-static inline tilepro_bundle_bits addi_X1(
- tilepro_bundle_bits n, int dest, int src, int imm)
-{
- n &= ~TILE_X1_MASK;
-
- n |= (create_SrcA_X1(src) |
- create_Dest_X1(dest) |
- create_Imm8_X1(imm) |
- create_S_X1(0) |
- create_Opcode_X1(IMM_0_OPCODE_X1) |
- create_ImmOpcodeExtension_X1(ADDI_IMM_0_OPCODE_X1));
-
- return n;
-}
-
-static tilepro_bundle_bits rewrite_load_store_unaligned(
- struct single_step_state *state,
- tilepro_bundle_bits bundle,
- struct pt_regs *regs,
- enum mem_op mem_op,
- int size, int sign_ext)
-{
- unsigned char __user *addr;
- int val_reg, addr_reg, err, val;
- int align_ctl;
-
- align_ctl = unaligned_fixup;
- switch (task_thread_info(current)->align_ctl) {
- case PR_UNALIGN_NOPRINT:
- align_ctl = 1;
- break;
- case PR_UNALIGN_SIGBUS:
- align_ctl = 0;
- break;
- }
-
- /* Get address and value registers */
- if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) {
- addr_reg = get_SrcA_Y2(bundle);
- val_reg = get_SrcBDest_Y2(bundle);
- } else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
- addr_reg = get_SrcA_X1(bundle);
- val_reg = get_Dest_X1(bundle);
- } else {
- addr_reg = get_SrcA_X1(bundle);
- val_reg = get_SrcB_X1(bundle);
- }
-
- /*
- * If registers are not GPRs, don't try to handle it.
- *
- * FIXME: we could handle non-GPR loads by getting the real value
- * from memory, writing it to the single step buffer, using a
- * temp_reg to hold a pointer to that memory, then executing that
- * instruction and resetting temp_reg. For non-GPR stores, it's a
- * little trickier; we could use the single step buffer for that
- * too, but we'd have to add some more state bits so that we could
- * call back in here to copy that value to the real target. For
- * now, we just handle the simple case.
- */
- if ((val_reg >= PTREGS_NR_GPRS &&
- (val_reg != TREG_ZERO ||
- mem_op == MEMOP_LOAD ||
- mem_op == MEMOP_LOAD_POSTINCR)) ||
- addr_reg >= PTREGS_NR_GPRS)
- return bundle;
-
- /* If it's aligned, don't handle it specially */
- addr = (void __user *)regs->regs[addr_reg];
- if (((unsigned long)addr % size) == 0)
- return bundle;
-
- /*
- * Return SIGBUS with the unaligned address, if requested.
- * Note that we return SIGBUS even for completely invalid addresses
- * as long as they are in fact unaligned; this matches what the
- * tilepro hardware would be doing, if it could provide us with the
- * actual bad address in an SPR, which it doesn't.
- */
- if (align_ctl == 0) {
- siginfo_t info;
-
- clear_siginfo(&info);
- info.si_signo = SIGBUS;
- info.si_code = BUS_ADRALN;
- info.si_addr = addr;
-
- trace_unhandled_signal("unaligned trap", regs,
- (unsigned long)addr, SIGBUS);
- force_sig_info(info.si_signo, &info, current);
- return (tilepro_bundle_bits) 0;
- }
-
- /* Handle unaligned load/store */
- if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
- unsigned short val_16;
- switch (size) {
- case 2:
- err = copy_from_user(&val_16, addr, sizeof(val_16));
- val = sign_ext ? ((short)val_16) : val_16;
- break;
- case 4:
- err = copy_from_user(&val, addr, sizeof(val));
- break;
- default:
- BUG();
- }
- if (err == 0) {
- state->update_reg = val_reg;
- state->update_value = val;
- state->update = 1;
- }
- } else {
- unsigned short val_16;
- val = (val_reg == TREG_ZERO) ? 0 : regs->regs[val_reg];
- switch (size) {
- case 2:
- val_16 = val;
- err = copy_to_user(addr, &val_16, sizeof(val_16));
- break;
- case 4:
- err = copy_to_user(addr, &val, sizeof(val));
- break;
- default:
- BUG();
- }
- }
-
- if (err) {
- siginfo_t info;
-
- clear_siginfo(&info);
- info.si_signo = SIGBUS;
- info.si_code = BUS_ADRALN;
- info.si_addr = addr;
-
- trace_unhandled_signal("bad address for unaligned fixup", regs,
- (unsigned long)addr, SIGBUS);
- force_sig_info(info.si_signo, &info, current);
- return (tilepro_bundle_bits) 0;
- }
-
- if (unaligned_printk || unaligned_fixup_count == 0) {
- pr_info("Process %d/%s: PC %#lx: Fixup of unaligned %s at %#lx\n",
- current->pid, current->comm, regs->pc,
- mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR ?
- "load" : "store",
- (unsigned long)addr);
- if (!unaligned_printk) {
-#define P pr_info
-P("\n");
-P("Unaligned fixups in the kernel will slow your application considerably.\n");
-P("To find them, write a \"1\" to /proc/sys/tile/unaligned_fixup/printk,\n");
-P("which requests the kernel show all unaligned fixups, or write a \"0\"\n");
-P("to /proc/sys/tile/unaligned_fixup/enabled, in which case each unaligned\n");
-P("access will become a SIGBUS you can debug. No further warnings will be\n");
-P("shown so as to avoid additional slowdown, but you can track the number\n");
-P("of fixups performed via /proc/sys/tile/unaligned_fixup/count.\n");
-P("Use the tile-addr2line command (see \"info addr2line\") to decode PCs.\n");
-P("\n");
-#undef P
- }
- }
- ++unaligned_fixup_count;
-
- if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) {
- /* Convert the Y2 instruction to a prefetch. */
- bundle &= ~(create_SrcBDest_Y2(-1) |
- create_Opcode_Y2(-1));
- bundle |= (create_SrcBDest_Y2(TREG_ZERO) |
- create_Opcode_Y2(LW_OPCODE_Y2));
- /* Replace the load postincr with an addi */
- } else if (mem_op == MEMOP_LOAD_POSTINCR) {
- bundle = addi_X1(bundle, addr_reg, addr_reg,
- get_Imm8_X1(bundle));
- /* Replace the store postincr with an addi */
- } else if (mem_op == MEMOP_STORE_POSTINCR) {
- bundle = addi_X1(bundle, addr_reg, addr_reg,
- get_Dest_Imm8_X1(bundle));
- } else {
- /* Convert the X1 instruction to a nop. */
- bundle &= ~(create_Opcode_X1(-1) |
- create_UnShOpcodeExtension_X1(-1) |
- create_UnOpcodeExtension_X1(-1));
- bundle |= (create_Opcode_X1(SHUN_0_OPCODE_X1) |
- create_UnShOpcodeExtension_X1(
- UN_0_SHUN_0_OPCODE_X1) |
- create_UnOpcodeExtension_X1(
- NOP_UN_0_SHUN_0_OPCODE_X1));
- }
-
- return bundle;
-}
-
-/*
- * Called after execve() has started the new image. This allows us
- * to reset the info state. Note that the the mmap'ed memory, if there
- * was any, has already been unmapped by the exec.
- */
-void single_step_execve(void)
-{
- struct thread_info *ti = current_thread_info();
- kfree(ti->step_state);
- ti->step_state = NULL;
-}
-
-/*
- * single_step_once() - entry point when single stepping has been triggered.
- * @regs: The machine register state
- *
- * When we arrive at this routine via a trampoline, the single step
- * engine copies the executing bundle to the single step buffer.
- * If the instruction is a condition branch, then the target is
- * reset to one past the next instruction. If the instruction
- * sets the lr, then that is noted. If the instruction is a jump
- * or call, then the new target pc is preserved and the current
- * bundle instruction set to null.
- *
- * The necessary post-single-step rewriting information is stored in
- * single_step_state-> We use data segment values because the
- * stack will be rewound when we run the rewritten single-stepped
- * instruction.
- */
-void single_step_once(struct pt_regs *regs)
-{
- extern tilepro_bundle_bits __single_step_ill_insn;
- extern tilepro_bundle_bits __single_step_j_insn;
- extern tilepro_bundle_bits __single_step_addli_insn;
- extern tilepro_bundle_bits __single_step_auli_insn;
- struct thread_info *info = (void *)current_thread_info();
- struct single_step_state *state = info->step_state;
- int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
- tilepro_bundle_bits __user *buffer, *pc;
- tilepro_bundle_bits bundle;
- int temp_reg;
- int target_reg = TREG_LR;
- int err;
- enum mem_op mem_op = MEMOP_NONE;
- int size = 0, sign_ext = 0; /* happy compiler */
- int align_ctl;
-
- align_ctl = unaligned_fixup;
- switch (task_thread_info(current)->align_ctl) {
- case PR_UNALIGN_NOPRINT:
- align_ctl = 1;
- break;
- case PR_UNALIGN_SIGBUS:
- align_ctl = 0;
- break;
- }
-
- asm(
-" .pushsection .rodata.single_step\n"
-" .align 8\n"
-" .globl __single_step_ill_insn\n"
-"__single_step_ill_insn:\n"
-" ill\n"
-" .globl __single_step_addli_insn\n"
-"__single_step_addli_insn:\n"
-" { nop; addli r0, zero, 0 }\n"
-" .globl __single_step_auli_insn\n"
-"__single_step_auli_insn:\n"
-" { nop; auli r0, r0, 0 }\n"
-" .globl __single_step_j_insn\n"
-"__single_step_j_insn:\n"
-" j .\n"
-" .popsection\n"
- );
-
- /*
- * Enable interrupts here to allow touching userspace and the like.
- * The callers expect this: do_trap() already has interrupts
- * enabled, and do_work_pending() handles functions that enable
- * interrupts internally.
- */
- local_irq_enable();
-
- if (state == NULL) {
- /* allocate a page of writable, executable memory */
- state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL);
- if (state == NULL) {
- pr_err("Out of kernel memory trying to single-step\n");
- return;
- }
-
- /* allocate a cache line of writable, executable memory */
- buffer = (void __user *) vm_mmap(NULL, 0, 64,
- PROT_EXEC | PROT_READ | PROT_WRITE,
- MAP_PRIVATE | MAP_ANONYMOUS,
- 0);
-
- if (IS_ERR((void __force *)buffer)) {
- kfree(state);
- pr_err("Out of kernel pages trying to single-step\n");
- return;
- }
-
- state->buffer = buffer;
- state->is_enabled = 0;
-
- info->step_state = state;
-
- /* Validate our stored instruction patterns */
- BUG_ON(get_Opcode_X1(__single_step_addli_insn) !=
- ADDLI_OPCODE_X1);
- BUG_ON(get_Opcode_X1(__single_step_auli_insn) !=
- AULI_OPCODE_X1);
- BUG_ON(get_SrcA_X1(__single_step_addli_insn) != TREG_ZERO);
- BUG_ON(get_Dest_X1(__single_step_addli_insn) != 0);
- BUG_ON(get_JOffLong_X1(__single_step_j_insn) != 0);
- }
-
- /*
- * If we are returning from a syscall, we still haven't hit the
- * "ill" for the swint1 instruction. So back the PC up to be
- * pointing at the swint1, but we'll actually return directly
- * back to the "ill" so we come back in via SIGILL as if we
- * had "executed" the swint1 without ever being in kernel space.
- */
- if (regs->faultnum == INT_SWINT_1)
- regs->pc -= 8;
-
- pc = (tilepro_bundle_bits __user *)(regs->pc);
- if (get_user(bundle, pc) != 0) {
- pr_err("Couldn't read instruction at %p trying to step\n", pc);
- return;
- }
-
- /* We'll follow the instruction with 2 ill op bundles */
- state->orig_pc = (unsigned long)pc;
- state->next_pc = (unsigned long)(pc + 1);
- state->branch_next_pc = 0;
- state->update = 0;
-
- if (!(bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK)) {
- /* two wide, check for control flow */
- int opcode = get_Opcode_X1(bundle);
-
- switch (opcode) {
- /* branches */
- case BRANCH_OPCODE_X1:
- {
- s32 offset = signExtend17(get_BrOff_X1(bundle));
-
- /*
- * For branches, we use a rewriting trick to let the
- * hardware evaluate whether the branch is taken or
- * untaken. We record the target offset and then
- * rewrite the branch instruction to target 1 insn
- * ahead if the branch is taken. We then follow the
- * rewritten branch with two bundles, each containing
- * an "ill" instruction. The supervisor examines the
- * pc after the single step code is executed, and if
- * the pc is the first ill instruction, then the
- * branch (if any) was not taken. If the pc is the
- * second ill instruction, then the branch was
- * taken. The new pc is computed for these cases, and
- * inserted into the registers for the thread. If
- * the pc is the start of the single step code, then
- * an exception or interrupt was taken before the
- * code started processing, and the same "original"
- * pc is restored. This change, different from the
- * original implementation, has the advantage of
- * executing a single user instruction.
- */
- state->branch_next_pc = (unsigned long)(pc + offset);
-
- /* rewrite branch offset to go forward one bundle */
- bundle = set_BrOff_X1(bundle, 2);
- }
- break;
-
- /* jumps */
- case JALB_OPCODE_X1:
- case JALF_OPCODE_X1:
- state->update = 1;
- state->next_pc =
- (unsigned long) (pc + get_JOffLong_X1(bundle));
- break;
-
- case JB_OPCODE_X1:
- case JF_OPCODE_X1:
- state->next_pc =
- (unsigned long) (pc + get_JOffLong_X1(bundle));
- bundle = nop_X1(bundle);
- break;
-
- case SPECIAL_0_OPCODE_X1:
- switch (get_RRROpcodeExtension_X1(bundle)) {
- /* jump-register */
- case JALRP_SPECIAL_0_OPCODE_X1:
- case JALR_SPECIAL_0_OPCODE_X1:
- state->update = 1;
- state->next_pc =
- regs->regs[get_SrcA_X1(bundle)];
- break;
-
- case JRP_SPECIAL_0_OPCODE_X1:
- case JR_SPECIAL_0_OPCODE_X1:
- state->next_pc =
- regs->regs[get_SrcA_X1(bundle)];
- bundle = nop_X1(bundle);
- break;
-
- case LNK_SPECIAL_0_OPCODE_X1:
- state->update = 1;
- target_reg = get_Dest_X1(bundle);
- break;
-
- /* stores */
- case SH_SPECIAL_0_OPCODE_X1:
- mem_op = MEMOP_STORE;
- size = 2;
- break;
-
- case SW_SPECIAL_0_OPCODE_X1:
- mem_op = MEMOP_STORE;
- size = 4;
- break;
- }
- break;
-
- /* loads and iret */
- case SHUN_0_OPCODE_X1:
- if (get_UnShOpcodeExtension_X1(bundle) ==
- UN_0_SHUN_0_OPCODE_X1) {
- switch (get_UnOpcodeExtension_X1(bundle)) {
- case LH_UN_0_SHUN_0_OPCODE_X1:
- mem_op = MEMOP_LOAD;
- size = 2;
- sign_ext = 1;
- break;
-
- case LH_U_UN_0_SHUN_0_OPCODE_X1:
- mem_op = MEMOP_LOAD;
- size = 2;
- sign_ext = 0;
- break;
-
- case LW_UN_0_SHUN_0_OPCODE_X1:
- mem_op = MEMOP_LOAD;
- size = 4;
- break;
-
- case IRET_UN_0_SHUN_0_OPCODE_X1:
- {
- unsigned long ex0_0 = __insn_mfspr(
- SPR_EX_CONTEXT_0_0);
- unsigned long ex0_1 = __insn_mfspr(
- SPR_EX_CONTEXT_0_1);
- /*
- * Special-case it if we're iret'ing
- * to PL0 again. Otherwise just let
- * it run and it will generate SIGILL.
- */
- if (EX1_PL(ex0_1) == USER_PL) {
- state->next_pc = ex0_0;
- regs->ex1 = ex0_1;
- bundle = nop_X1(bundle);
- }
- }
- }
- }
- break;
-
- /* postincrement operations */
- case IMM_0_OPCODE_X1:
- switch (get_ImmOpcodeExtension_X1(bundle)) {
- case LWADD_IMM_0_OPCODE_X1:
- mem_op = MEMOP_LOAD_POSTINCR;
- size = 4;
- break;
-
- case LHADD_IMM_0_OPCODE_X1:
- mem_op = MEMOP_LOAD_POSTINCR;
- size = 2;
- sign_ext = 1;
- break;
-
- case LHADD_U_IMM_0_OPCODE_X1:
- mem_op = MEMOP_LOAD_POSTINCR;
- size = 2;
- sign_ext = 0;
- break;
-
- case SWADD_IMM_0_OPCODE_X1:
- mem_op = MEMOP_STORE_POSTINCR;
- size = 4;
- break;
-
- case SHADD_IMM_0_OPCODE_X1:
- mem_op = MEMOP_STORE_POSTINCR;
- size = 2;
- break;
-
- default:
- break;
- }
- break;
- }
-
- if (state->update) {
- /*
- * Get an available register. We start with a
- * bitmask with 1's for available registers.
- * We truncate to the low 32 registers since
- * we are guaranteed to have set bits in the
- * low 32 bits, then use ctz to pick the first.
- */
- u32 mask = (u32) ~((1ULL << get_Dest_X0(bundle)) |
- (1ULL << get_SrcA_X0(bundle)) |
- (1ULL << get_SrcB_X0(bundle)) |
- (1ULL << target_reg));
- temp_reg = __builtin_ctz(mask);
- state->update_reg = temp_reg;
- state->update_value = regs->regs[temp_reg];
- regs->regs[temp_reg] = (unsigned long) (pc+1);
- regs->flags |= PT_FLAGS_RESTORE_REGS;
- bundle = move_X1(bundle, target_reg, temp_reg);
- }
- } else {
- int opcode = get_Opcode_Y2(bundle);
-
- switch (opcode) {
- /* loads */
- case LH_OPCODE_Y2:
- mem_op = MEMOP_LOAD;
- size = 2;
- sign_ext = 1;
- break;
-
- case LH_U_OPCODE_Y2:
- mem_op = MEMOP_LOAD;
- size = 2;
- sign_ext = 0;
- break;
-
- case LW_OPCODE_Y2:
- mem_op = MEMOP_LOAD;
- size = 4;
- break;
-
- /* stores */
- case SH_OPCODE_Y2:
- mem_op = MEMOP_STORE;
- size = 2;
- break;
-
- case SW_OPCODE_Y2:
- mem_op = MEMOP_STORE;
- size = 4;
- break;
- }
- }
-
- /*
- * Check if we need to rewrite an unaligned load/store.
- * Returning zero is a special value meaning we generated a signal.
- */
- if (mem_op != MEMOP_NONE && align_ctl >= 0) {
- bundle = rewrite_load_store_unaligned(state, bundle, regs,
- mem_op, size, sign_ext);
- if (bundle == 0)
- return;
- }
-
- /* write the bundle to our execution area */
- buffer = state->buffer;
- err = __put_user(bundle, buffer++);
-
- /*
- * If we're really single-stepping, we take an INT_ILL after.
- * If we're just handling an unaligned access, we can just
- * jump directly back to where we were in user code.
- */
- if (is_single_step) {
- err |= __put_user(__single_step_ill_insn, buffer++);
- err |= __put_user(__single_step_ill_insn, buffer++);
- } else {
- long delta;
-
- if (state->update) {
- /* We have some state to update; do it inline */
- int ha16;
- bundle = __single_step_addli_insn;
- bundle |= create_Dest_X1(state->update_reg);
- bundle |= create_Imm16_X1(state->update_value);
- err |= __put_user(bundle, buffer++);
- bundle = __single_step_auli_insn;
- bundle |= create_Dest_X1(state->update_reg);
- bundle |= create_SrcA_X1(state->update_reg);
- ha16 = (state->update_value + 0x8000) >> 16;
- bundle |= create_Imm16_X1(ha16);
- err |= __put_user(bundle, buffer++);
- state->update = 0;
- }
-
- /* End with a jump back to the next instruction */
- delta = ((regs->pc + TILEPRO_BUNDLE_SIZE_IN_BYTES) -
- (unsigned long)buffer) >>
- TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES;
- bundle = __single_step_j_insn;
- bundle |= create_JOffLong_X1(delta);
- err |= __put_user(bundle, buffer++);
- }
-
- if (err) {
- pr_err("Fault when writing to single-step buffer\n");
- return;
- }
-
- /*
- * Flush the buffer.
- * We do a local flush only, since this is a thread-specific buffer.
- */
- __flush_icache_range((unsigned long)state->buffer,
- (unsigned long)buffer);
-
- /* Indicate enabled */
- state->is_enabled = is_single_step;
- regs->pc = (unsigned long)state->buffer;
-
- /* Fault immediately if we are coming back from a syscall. */
- if (regs->faultnum == INT_SWINT_1)
- regs->pc += 8;
-}
-
-#else
-
-static DEFINE_PER_CPU(unsigned long, ss_saved_pc);
-
-
-/*
- * Called directly on the occasion of an interrupt.
- *
- * If the process doesn't have single step set, then we use this as an
- * opportunity to turn single step off.
- *
- * It has been mentioned that we could conditionally turn off single stepping
- * on each entry into the kernel and rely on single_step_once to turn it
- * on for the processes that matter (as we already do), but this
- * implementation is somewhat more efficient in that we muck with registers
- * once on a bum interrupt rather than on every entry into the kernel.
- *
- * If SINGLE_STEP_CONTROL_K has CANCELED set, then an interrupt occurred,
- * so we have to run through this process again before we can say that an
- * instruction has executed.
- *
- * swint will set CANCELED, but it's a legitimate instruction. Fortunately
- * it changes the PC. If it hasn't changed, then we know that the interrupt
- * wasn't generated by swint and we'll need to run this process again before
- * we can say an instruction has executed.
- *
- * If either CANCELED == 0 or the PC's changed, we send out SIGTRAPs and get
- * on with our lives.
- */
-
-void gx_singlestep_handle(struct pt_regs *regs, int fault_num)
-{
- unsigned long *ss_pc = this_cpu_ptr(&ss_saved_pc);
- struct thread_info *info = (void *)current_thread_info();
- int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
- unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
-
- if (is_single_step == 0) {
- __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 0);
-
- } else if ((*ss_pc != regs->pc) ||
- (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) {
-
- control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
- control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
- __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
- send_sigtrap(current, regs);
- }
-}
-
-
-/*
- * Called from need_singlestep. Set up the control registers and the enable
- * register, then return back.
- */
-
-void single_step_once(struct pt_regs *regs)
-{
- unsigned long *ss_pc = this_cpu_ptr(&ss_saved_pc);
- unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
-
- *ss_pc = regs->pc;
- control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
- control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
- __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
- __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 1 << USER_PL);
-}
-
-void single_step_execve(void)
-{
- /* Nothing */
-}
-
-#endif /* !__tilegx__ */
diff --git a/arch/tile/kernel/smp.c b/arch/tile/kernel/smp.c
deleted file mode 100644
index 94a62e1197ce..000000000000
--- a/arch/tile/kernel/smp.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE SMP support routines.
- */
-
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irq_work.h>
-#include <linux/module.h>
-#include <asm/cacheflush.h>
-#include <asm/homecache.h>
-
-/*
- * We write to width and height with a single store in head_NN.S,
- * so make the variable aligned to "long".
- */
-HV_Topology smp_topology __ro_after_init __aligned(sizeof(long));
-EXPORT_SYMBOL(smp_topology);
-
-#if CHIP_HAS_IPI()
-static unsigned long __iomem *ipi_mappings[NR_CPUS];
-#endif
-
-/* Does messaging work correctly to the local cpu? */
-bool self_interrupt_ok;
-
-/*
- * Top-level send_IPI*() functions to send messages to other cpus.
- */
-
-/* Set by smp_send_stop() to avoid recursive panics. */
-static int stopping_cpus;
-
-static void __send_IPI_many(HV_Recipient *recip, int nrecip, int tag)
-{
- int sent = 0;
- while (sent < nrecip) {
- int rc = hv_send_message(recip, nrecip,
- (HV_VirtAddr)&tag, sizeof(tag));
- if (rc < 0) {
- if (!stopping_cpus) /* avoid recursive panic */
- panic("hv_send_message returned %d", rc);
- break;
- }
- WARN_ONCE(rc == 0, "hv_send_message() returned zero\n");
- sent += rc;
- }
-}
-
-void send_IPI_single(int cpu, int tag)
-{
- HV_Recipient recip = {
- .y = cpu / smp_width,
- .x = cpu % smp_width,
- .state = HV_TO_BE_SENT
- };
- __send_IPI_many(&recip, 1, tag);
-}
-
-void send_IPI_many(const struct cpumask *mask, int tag)
-{
- HV_Recipient recip[NR_CPUS];
- int cpu;
- int nrecip = 0;
- int my_cpu = smp_processor_id();
- for_each_cpu(cpu, mask) {
- HV_Recipient *r;
- BUG_ON(cpu == my_cpu);
- r = &recip[nrecip++];
- r->y = cpu / smp_width;
- r->x = cpu % smp_width;
- r->state = HV_TO_BE_SENT;
- }
- __send_IPI_many(recip, nrecip, tag);
-}
-
-void send_IPI_allbutself(int tag)
-{
- struct cpumask mask;
- cpumask_copy(&mask, cpu_online_mask);
- cpumask_clear_cpu(smp_processor_id(), &mask);
- send_IPI_many(&mask, tag);
-}
-
-/*
- * Functions related to starting/stopping cpus.
- */
-
-/* Handler to start the current cpu. */
-static void smp_start_cpu_interrupt(void)
-{
- get_irq_regs()->pc = start_cpu_function_addr;
-}
-
-/* Handler to stop the current cpu. */
-static void smp_stop_cpu_interrupt(void)
-{
- arch_local_irq_disable_all();
- set_cpu_online(smp_processor_id(), 0);
- for (;;)
- asm("nap; nop");
-}
-
-/* This function calls the 'stop' function on all other CPUs in the system. */
-void smp_send_stop(void)
-{
- stopping_cpus = 1;
- send_IPI_allbutself(MSG_TAG_STOP_CPU);
-}
-
-/* On panic, just wait; we may get an smp_send_stop() later on. */
-void panic_smp_self_stop(void)
-{
- while (1)
- asm("nap; nop");
-}
-
-/*
- * Dispatch code called from hv_message_intr() for HV_MSG_TILE hv messages.
- */
-void evaluate_message(int tag)
-{
- switch (tag) {
- case MSG_TAG_START_CPU: /* Start up a cpu */
- smp_start_cpu_interrupt();
- break;
-
- case MSG_TAG_STOP_CPU: /* Sent to shut down slave CPU's */
- smp_stop_cpu_interrupt();
- break;
-
- case MSG_TAG_CALL_FUNCTION_MANY: /* Call function on cpumask */
- generic_smp_call_function_interrupt();
- break;
-
- case MSG_TAG_CALL_FUNCTION_SINGLE: /* Call function on one other CPU */
- generic_smp_call_function_single_interrupt();
- break;
-
- case MSG_TAG_IRQ_WORK: /* Invoke IRQ work */
- irq_work_run();
- break;
-
- default:
- panic("Unknown IPI message tag %d", tag);
- break;
- }
-}
-
-
-/*
- * flush_icache_range() code uses smp_call_function().
- */
-
-struct ipi_flush {
- unsigned long start;
- unsigned long end;
-};
-
-static void ipi_flush_icache_range(void *info)
-{
- struct ipi_flush *flush = (struct ipi_flush *) info;
- __flush_icache_range(flush->start, flush->end);
-}
-
-void flush_icache_range(unsigned long start, unsigned long end)
-{
- struct ipi_flush flush = { start, end };
-
- /* If invoked with irqs disabled, we can not issue IPIs. */
- if (irqs_disabled())
- flush_remote(0, HV_FLUSH_EVICT_L1I, NULL, 0, 0, 0,
- NULL, NULL, 0);
- else {
- preempt_disable();
- on_each_cpu(ipi_flush_icache_range, &flush, 1);
- preempt_enable();
- }
-}
-EXPORT_SYMBOL(flush_icache_range);
-
-
-#ifdef CONFIG_IRQ_WORK
-void arch_irq_work_raise(void)
-{
- if (arch_irq_work_has_interrupt())
- send_IPI_single(smp_processor_id(), MSG_TAG_IRQ_WORK);
-}
-#endif
-
-
-/* Called when smp_send_reschedule() triggers IRQ_RESCHEDULE. */
-static irqreturn_t handle_reschedule_ipi(int irq, void *token)
-{
- __this_cpu_inc(irq_stat.irq_resched_count);
- scheduler_ipi();
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction resched_action = {
- .handler = handle_reschedule_ipi,
- .name = "resched",
- .dev_id = handle_reschedule_ipi /* unique token */,
-};
-
-void __init ipi_init(void)
-{
- int cpu = smp_processor_id();
- HV_Recipient recip = { .y = cpu_y(cpu), .x = cpu_x(cpu),
- .state = HV_TO_BE_SENT };
- int tag = MSG_TAG_CALL_FUNCTION_SINGLE;
-
- /*
- * Test if we can message ourselves for arch_irq_work_raise.
- * This functionality is only available in the Tilera hypervisor
- * in versions 4.3.4 and following.
- */
- if (hv_send_message(&recip, 1, (HV_VirtAddr)&tag, sizeof(tag)) == 1)
- self_interrupt_ok = true;
- else
- pr_warn("Older hypervisor: disabling fast irq_work_raise\n");
-
-#if CHIP_HAS_IPI()
- /* Map IPI trigger MMIO addresses. */
- for_each_possible_cpu(cpu) {
- HV_Coord tile;
- HV_PTE pte;
- unsigned long offset;
-
- tile.x = cpu_x(cpu);
- tile.y = cpu_y(cpu);
- if (hv_get_ipi_pte(tile, KERNEL_PL, &pte) != 0)
- panic("Failed to initialize IPI for cpu %d\n", cpu);
-
- offset = PFN_PHYS(pte_pfn(pte));
- ipi_mappings[cpu] = ioremap_prot(offset, PAGE_SIZE, pte);
- }
-#endif
-
- /* Bind handle_reschedule_ipi() to IRQ_RESCHEDULE. */
- tile_irq_activate(IRQ_RESCHEDULE, TILE_IRQ_PERCPU);
- BUG_ON(setup_irq(IRQ_RESCHEDULE, &resched_action));
-}
-
-#if CHIP_HAS_IPI()
-
-void smp_send_reschedule(int cpu)
-{
- WARN_ON(cpu_is_offline(cpu));
-
- /*
- * We just want to do an MMIO store. The traditional writeq()
- * functions aren't really correct here, since they're always
- * directed at the PCI shim. For now, just do a raw store,
- * casting away the __iomem attribute.
- */
- ((unsigned long __force *)ipi_mappings[cpu])[IRQ_RESCHEDULE] = 0;
-}
-
-#else
-
-void smp_send_reschedule(int cpu)
-{
- HV_Coord coord;
-
- WARN_ON(cpu_is_offline(cpu));
-
- coord.y = cpu_y(cpu);
- coord.x = cpu_x(cpu);
- hv_trigger_ipi(coord, IRQ_RESCHEDULE);
-}
-
-#endif /* CHIP_HAS_IPI() */
diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c
deleted file mode 100644
index 869c22e57561..000000000000
--- a/arch/tile/kernel/smpboot.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/sched/mm.h>
-#include <linux/sched/task.h>
-#include <linux/kernel_stat.h>
-#include <linux/bootmem.h>
-#include <linux/notifier.h>
-#include <linux/cpu.h>
-#include <linux/percpu.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/irq.h>
-#include <asm/mmu_context.h>
-#include <asm/tlbflush.h>
-#include <asm/sections.h>
-
-/* State of each CPU. */
-static DEFINE_PER_CPU(int, cpu_state) = { 0 };
-
-/* The messaging code jumps to this pointer during boot-up */
-unsigned long start_cpu_function_addr;
-
-/* Called very early during startup to mark boot cpu as online */
-void __init smp_prepare_boot_cpu(void)
-{
- int cpu = smp_processor_id();
- set_cpu_online(cpu, 1);
- set_cpu_present(cpu, 1);
- __this_cpu_write(cpu_state, CPU_ONLINE);
-
- init_messaging();
-}
-
-static void start_secondary(void);
-
-/*
- * Called at the top of init() to launch all the other CPUs.
- * They run free to complete their initialization and then wait
- * until they get an IPI from the boot cpu to come online.
- */
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
- long rc;
- int cpu, cpu_count;
- int boot_cpu = smp_processor_id();
-
- current_thread_info()->cpu = boot_cpu;
-
- /*
- * Pin this task to the boot CPU while we bring up the others,
- * just to make sure we don't uselessly migrate as they come up.
- */
- rc = sched_setaffinity(current->pid, cpumask_of(boot_cpu));
- if (rc != 0)
- pr_err("Couldn't set init affinity to boot cpu (%ld)\n", rc);
-
- /* Print information about disabled and dataplane cpus. */
- print_disabled_cpus();
-
- /*
- * Tell the messaging subsystem how to respond to the
- * startup message. We use a level of indirection to avoid
- * confusing the linker with the fact that the messaging
- * subsystem is calling __init code.
- */
- start_cpu_function_addr = (unsigned long) &online_secondary;
-
- /* Set up thread context for all new processors. */
- cpu_count = 1;
- for (cpu = 0; cpu < NR_CPUS; ++cpu) {
- struct task_struct *idle;
-
- if (cpu == boot_cpu)
- continue;
-
- if (!cpu_possible(cpu)) {
- /*
- * Make this processor do nothing on boot.
- * Note that we don't give the boot_pc function
- * a stack, so it has to be assembly code.
- */
- per_cpu(boot_sp, cpu) = 0;
- per_cpu(boot_pc, cpu) = (unsigned long) smp_nap;
- continue;
- }
-
- /* Create a new idle thread to run start_secondary() */
- idle = fork_idle(cpu);
- if (IS_ERR(idle))
- panic("failed fork for CPU %d", cpu);
- idle->thread.pc = (unsigned long) start_secondary;
-
- /* Make this thread the boot thread for this processor */
- per_cpu(boot_sp, cpu) = task_ksp0(idle);
- per_cpu(boot_pc, cpu) = idle->thread.pc;
-
- ++cpu_count;
- }
- BUG_ON(cpu_count > (max_cpus ? max_cpus : 1));
-
- /* Fire up the other tiles, if any */
- init_cpu_present(cpu_possible_mask);
- if (cpumask_weight(cpu_present_mask) > 1) {
- mb(); /* make sure all data is visible to new processors */
- hv_start_all_tiles();
- }
-}
-
-static __initdata struct cpumask init_affinity;
-
-static __init int reset_init_affinity(void)
-{
- long rc = sched_setaffinity(current->pid, &init_affinity);
- if (rc != 0)
- pr_warn("couldn't reset init affinity (%ld)\n", rc);
- return 0;
-}
-late_initcall(reset_init_affinity);
-
-static struct cpumask cpu_started;
-
-/*
- * Activate a secondary processor. Very minimal; don't add anything
- * to this path without knowing what you're doing, since SMP booting
- * is pretty fragile.
- */
-static void start_secondary(void)
-{
- int cpuid;
-
- preempt_disable();
-
- cpuid = smp_processor_id();
-
- /* Set our thread pointer appropriately. */
- set_my_cpu_offset(__per_cpu_offset[cpuid]);
-
- /*
- * In large machines even this will slow us down, since we
- * will be contending for for the printk spinlock.
- */
- /* printk(KERN_DEBUG "Initializing CPU#%d\n", cpuid); */
-
- /* Initialize the current asid for our first page table. */
- __this_cpu_write(current_asid, min_asid);
-
- /* Set up this thread as another owner of the init_mm */
- mmgrab(&init_mm);
- current->active_mm = &init_mm;
- if (current->mm)
- BUG();
- enter_lazy_tlb(&init_mm, current);
-
- /* Allow hypervisor messages to be received */
- init_messaging();
- local_irq_enable();
-
- /* Indicate that we're ready to come up. */
- /* Must not do this before we're ready to receive messages */
- if (cpumask_test_and_set_cpu(cpuid, &cpu_started)) {
- pr_warn("CPU#%d already started!\n", cpuid);
- for (;;)
- local_irq_enable();
- }
-
- smp_nap();
-}
-
-/*
- * Bring a secondary processor online.
- */
-void online_secondary(void)
-{
- /*
- * low-memory mappings have been cleared, flush them from
- * the local TLBs too.
- */
- local_flush_tlb();
-
- BUG_ON(in_interrupt());
-
- /* This must be done before setting cpu_online_mask */
- wmb();
-
- notify_cpu_starting(smp_processor_id());
-
- set_cpu_online(smp_processor_id(), 1);
- __this_cpu_write(cpu_state, CPU_ONLINE);
-
- /* Set up tile-specific state for this cpu. */
- setup_cpu(0);
-
- /* Set up tile-timer clock-event device on this cpu */
- setup_tile_timer();
-
- cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
-}
-
-int __cpu_up(unsigned int cpu, struct task_struct *tidle)
-{
- /* Wait 5s total for all CPUs for them to come online */
- static int timeout;
- for (; !cpumask_test_cpu(cpu, &cpu_started); timeout++) {
- if (timeout >= 50000) {
- pr_info("skipping unresponsive cpu%d\n", cpu);
- local_irq_enable();
- return -EIO;
- }
- udelay(100);
- }
-
- local_irq_enable();
- per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
-
- /* Unleash the CPU! */
- send_IPI_single(cpu, MSG_TAG_START_CPU);
- while (!cpumask_test_cpu(cpu, cpu_online_mask))
- cpu_relax();
- return 0;
-}
-
-static void panic_start_cpu(void)
-{
- panic("Received a MSG_START_CPU IPI after boot finished.");
-}
-
-void __init smp_cpus_done(unsigned int max_cpus)
-{
- int cpu, next, rc;
-
- /* Reset the response to a (now illegal) MSG_START_CPU IPI. */
- start_cpu_function_addr = (unsigned long) &panic_start_cpu;
-
- cpumask_copy(&init_affinity, cpu_online_mask);
-
- /*
- * Pin ourselves to a single cpu in the initial affinity set
- * so that kernel mappings for the rootfs are not in the dataplane,
- * if set, and to avoid unnecessary migrating during bringup.
- * Use the last cpu just in case the whole chip has been
- * isolated from the scheduler, to keep init away from likely
- * more useful user code. This also ensures that work scheduled
- * via schedule_delayed_work() in the init routines will land
- * on this cpu.
- */
- for (cpu = cpumask_first(&init_affinity);
- (next = cpumask_next(cpu, &init_affinity)) < nr_cpu_ids;
- cpu = next)
- ;
- rc = sched_setaffinity(current->pid, cpumask_of(cpu));
- if (rc != 0)
- pr_err("Couldn't set init affinity to cpu %d (%d)\n", cpu, rc);
-}
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
deleted file mode 100644
index 94ecbc6676e5..000000000000
--- a/arch/tile/kernel/stack.c
+++ /dev/null
@@ -1,539 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task_stack.h>
-#include <linux/kernel.h>
-#include <linux/kprobes.h>
-#include <linux/module.h>
-#include <linux/pfn.h>
-#include <linux/kallsyms.h>
-#include <linux/stacktrace.h>
-#include <linux/uaccess.h>
-#include <linux/mmzone.h>
-#include <linux/dcache.h>
-#include <linux/fs.h>
-#include <linux/hardirq.h>
-#include <linux/string.h>
-#include <asm/backtrace.h>
-#include <asm/page.h>
-#include <asm/ucontext.h>
-#include <asm/switch_to.h>
-#include <asm/sigframe.h>
-#include <asm/stack.h>
-#include <asm/vdso.h>
-#include <arch/abi.h>
-#include <arch/interrupts.h>
-
-#define KBT_ONGOING 0 /* Backtrace still ongoing */
-#define KBT_DONE 1 /* Backtrace cleanly completed */
-#define KBT_RUNNING 2 /* Can't run backtrace on a running task */
-#define KBT_LOOP 3 /* Backtrace entered a loop */
-
-/* Is address on the specified kernel stack? */
-static int in_kernel_stack(struct KBacktraceIterator *kbt, unsigned long sp)
-{
- ulong kstack_base = (ulong) kbt->task->stack;
- if (kstack_base == 0) /* corrupt task pointer; just follow stack... */
- return sp >= PAGE_OFFSET && sp < (unsigned long)high_memory;
- return sp >= kstack_base && sp < kstack_base + THREAD_SIZE;
-}
-
-/* Callback for backtracer; basically a glorified memcpy */
-static bool read_memory_func(void *result, unsigned long address,
- unsigned int size, void *vkbt)
-{
- int retval;
- struct KBacktraceIterator *kbt = (struct KBacktraceIterator *)vkbt;
-
- if (address == 0)
- return 0;
- if (__kernel_text_address(address)) {
- /* OK to read kernel code. */
- } else if (address >= PAGE_OFFSET) {
- /* We only tolerate kernel-space reads of this task's stack */
- if (!in_kernel_stack(kbt, address))
- return 0;
- } else if (!kbt->is_current) {
- return 0; /* can't read from other user address spaces */
- }
- pagefault_disable();
- retval = __copy_from_user_inatomic(result,
- (void __user __force *)address,
- size);
- pagefault_enable();
- return (retval == 0);
-}
-
-/* Return a pt_regs pointer for a valid fault handler frame */
-static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
-{
- char fault[64];
- unsigned long sp = kbt->it.sp;
- struct pt_regs *p;
-
- if (sp % sizeof(long) != 0)
- return NULL;
- if (!in_kernel_stack(kbt, sp))
- return NULL;
- if (!in_kernel_stack(kbt, sp + C_ABI_SAVE_AREA_SIZE + PTREGS_SIZE-1))
- return NULL;
- p = (struct pt_regs *)(sp + C_ABI_SAVE_AREA_SIZE);
- if (kbt->verbose) { /* else we aren't going to use it */
- if (p->faultnum == INT_SWINT_1 ||
- p->faultnum == INT_SWINT_1_SIGRETURN)
- snprintf(fault, sizeof(fault),
- "syscall %ld", p->regs[TREG_SYSCALL_NR]);
- else
- snprintf(fault, sizeof(fault),
- "interrupt %ld", p->faultnum);
- }
- if (EX1_PL(p->ex1) == KERNEL_PL &&
- __kernel_text_address(p->pc) &&
- in_kernel_stack(kbt, p->sp) &&
- p->sp >= sp) {
- if (kbt->verbose)
- pr_err(" <%s while in kernel mode>\n", fault);
- } else if (user_mode(p) &&
- p->sp < PAGE_OFFSET && p->sp != 0) {
- if (kbt->verbose)
- pr_err(" <%s while in user mode>\n", fault);
- } else {
- if (kbt->verbose && (p->pc != 0 || p->sp != 0 || p->ex1 != 0))
- pr_err(" (odd fault: pc %#lx, sp %#lx, ex1 %#lx?)\n",
- p->pc, p->sp, p->ex1);
- return NULL;
- }
- if (kbt->profile && ((1ULL << p->faultnum) & QUEUED_INTERRUPTS) != 0)
- return NULL;
- return p;
-}
-
-/* Is the iterator pointing to a sigreturn trampoline? */
-static int is_sigreturn(struct KBacktraceIterator *kbt)
-{
- return kbt->task->mm &&
- (kbt->it.pc == ((ulong)kbt->task->mm->context.vdso_base +
- (ulong)&__vdso_rt_sigreturn));
-}
-
-/* Return a pt_regs pointer for a valid signal handler frame */
-static struct pt_regs *valid_sigframe(struct KBacktraceIterator* kbt,
- struct rt_sigframe* kframe)
-{
- BacktraceIterator *b = &kbt->it;
-
- if (is_sigreturn(kbt) && b->sp < PAGE_OFFSET &&
- b->sp % sizeof(long) == 0) {
- int retval;
- pagefault_disable();
- retval = __copy_from_user_inatomic(
- kframe, (void __user __force *)b->sp,
- sizeof(*kframe));
- pagefault_enable();
- if (retval != 0 ||
- (unsigned int)(kframe->info.si_signo) >= _NSIG)
- return NULL;
- if (kbt->verbose) {
- pr_err(" <received signal %d>\n",
- kframe->info.si_signo);
- }
- return (struct pt_regs *)&kframe->uc.uc_mcontext;
- }
- return NULL;
-}
-
-static int KBacktraceIterator_restart(struct KBacktraceIterator *kbt)
-{
- struct pt_regs *p;
- struct rt_sigframe kframe;
-
- p = valid_fault_handler(kbt);
- if (p == NULL)
- p = valid_sigframe(kbt, &kframe);
- if (p == NULL)
- return 0;
- backtrace_init(&kbt->it, read_memory_func, kbt,
- p->pc, p->lr, p->sp, p->regs[52]);
- kbt->new_context = 1;
- return 1;
-}
-
-/* Find a frame that isn't a sigreturn, if there is one. */
-static int KBacktraceIterator_next_item_inclusive(
- struct KBacktraceIterator *kbt)
-{
- for (;;) {
- do {
- if (!is_sigreturn(kbt))
- return KBT_ONGOING;
- } while (backtrace_next(&kbt->it));
-
- if (!KBacktraceIterator_restart(kbt))
- return KBT_DONE;
- }
-}
-
-/*
- * If the current sp is on a page different than what we recorded
- * as the top-of-kernel-stack last time we context switched, we have
- * probably blown the stack, and nothing is going to work out well.
- * If we can at least get out a warning, that may help the debug,
- * though we probably won't be able to backtrace into the code that
- * actually did the recursive damage.
- */
-static void validate_stack(struct pt_regs *regs)
-{
- int cpu = raw_smp_processor_id();
- unsigned long ksp0 = get_current_ksp0();
- unsigned long ksp0_base = ksp0 & -THREAD_SIZE;
- unsigned long sp = stack_pointer;
-
- if (EX1_PL(regs->ex1) == KERNEL_PL && regs->sp >= ksp0) {
- pr_err("WARNING: cpu %d: kernel stack %#lx..%#lx underrun!\n"
- " sp %#lx (%#lx in caller), caller pc %#lx, lr %#lx\n",
- cpu, ksp0_base, ksp0, sp, regs->sp, regs->pc, regs->lr);
- }
-
- else if (sp < ksp0_base + sizeof(struct thread_info)) {
- pr_err("WARNING: cpu %d: kernel stack %#lx..%#lx overrun!\n"
- " sp %#lx (%#lx in caller), caller pc %#lx, lr %#lx\n",
- cpu, ksp0_base, ksp0, sp, regs->sp, regs->pc, regs->lr);
- }
-}
-
-void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
- struct task_struct *t, struct pt_regs *regs)
-{
- unsigned long pc, lr, sp, r52;
- int is_current;
-
- /*
- * Set up callback information. We grab the kernel stack base
- * so we will allow reads of that address range.
- */
- is_current = (t == NULL || t == current);
- kbt->is_current = is_current;
- if (is_current)
- t = validate_current();
- kbt->task = t;
- kbt->verbose = 0; /* override in caller if desired */
- kbt->profile = 0; /* override in caller if desired */
- kbt->end = KBT_ONGOING;
- kbt->new_context = 1;
- if (is_current)
- validate_stack(regs);
-
- if (regs == NULL) {
- if (is_current || t->state == TASK_RUNNING) {
- /* Can't do this; we need registers */
- kbt->end = KBT_RUNNING;
- return;
- }
- pc = get_switch_to_pc();
- lr = t->thread.pc;
- sp = t->thread.ksp;
- r52 = 0;
- } else {
- pc = regs->pc;
- lr = regs->lr;
- sp = regs->sp;
- r52 = regs->regs[52];
- }
-
- backtrace_init(&kbt->it, read_memory_func, kbt, pc, lr, sp, r52);
- kbt->end = KBacktraceIterator_next_item_inclusive(kbt);
-}
-EXPORT_SYMBOL(KBacktraceIterator_init);
-
-int KBacktraceIterator_end(struct KBacktraceIterator *kbt)
-{
- return kbt->end != KBT_ONGOING;
-}
-EXPORT_SYMBOL(KBacktraceIterator_end);
-
-void KBacktraceIterator_next(struct KBacktraceIterator *kbt)
-{
- unsigned long old_pc = kbt->it.pc, old_sp = kbt->it.sp;
- kbt->new_context = 0;
- if (!backtrace_next(&kbt->it) && !KBacktraceIterator_restart(kbt)) {
- kbt->end = KBT_DONE;
- return;
- }
- kbt->end = KBacktraceIterator_next_item_inclusive(kbt);
- if (old_pc == kbt->it.pc && old_sp == kbt->it.sp) {
- /* Trapped in a loop; give up. */
- kbt->end = KBT_LOOP;
- }
-}
-EXPORT_SYMBOL(KBacktraceIterator_next);
-
-static void describe_addr(struct KBacktraceIterator *kbt,
- unsigned long address,
- int have_mmap_sem, char *buf, size_t bufsize)
-{
- struct vm_area_struct *vma;
- size_t namelen, remaining;
- unsigned long size, offset, adjust;
- char *p, *modname;
- const char *name;
- int rc;
-
- /*
- * Look one byte back for every caller frame (i.e. those that
- * aren't a new context) so we look up symbol data for the
- * call itself, not the following instruction, which may be on
- * a different line (or in a different function).
- */
- adjust = !kbt->new_context;
- address -= adjust;
-
- if (address >= PAGE_OFFSET) {
- /* Handle kernel symbols. */
- BUG_ON(bufsize < KSYM_NAME_LEN);
- name = kallsyms_lookup(address, &size, &offset,
- &modname, buf);
- if (name == NULL) {
- buf[0] = '\0';
- return;
- }
- namelen = strlen(buf);
- remaining = (bufsize - 1) - namelen;
- p = buf + namelen;
- rc = snprintf(p, remaining, "+%#lx/%#lx ",
- offset + adjust, size);
- if (modname && rc < remaining)
- snprintf(p + rc, remaining - rc, "[%s] ", modname);
- buf[bufsize-1] = '\0';
- return;
- }
-
- /* If we don't have the mmap_sem, we can't show any more info. */
- buf[0] = '\0';
- if (!have_mmap_sem)
- return;
-
- /* Find vma info. */
- vma = find_vma(kbt->task->mm, address);
- if (vma == NULL || address < vma->vm_start) {
- snprintf(buf, bufsize, "[unmapped address] ");
- return;
- }
-
- if (vma->vm_file) {
- p = file_path(vma->vm_file, buf, bufsize);
- if (IS_ERR(p))
- p = "?";
- name = kbasename(p);
- } else {
- name = "anon";
- }
-
- /* Generate a string description of the vma info. */
- namelen = strlen(name);
- remaining = (bufsize - 1) - namelen;
- memmove(buf, name, namelen);
- snprintf(buf + namelen, remaining, "[%lx+%lx] ",
- vma->vm_start, vma->vm_end - vma->vm_start);
-}
-
-/*
- * Avoid possible crash recursion during backtrace. If it happens, it
- * makes it easy to lose the actual root cause of the failure, so we
- * put a simple guard on all the backtrace loops.
- */
-static bool start_backtrace(void)
-{
- if (current_thread_info()->in_backtrace) {
- pr_err("Backtrace requested while in backtrace!\n");
- return false;
- }
- current_thread_info()->in_backtrace = true;
- return true;
-}
-
-static void end_backtrace(void)
-{
- current_thread_info()->in_backtrace = false;
-}
-
-/*
- * This method wraps the backtracer's more generic support.
- * It is only invoked from the architecture-specific code; show_stack()
- * and dump_stack() are architecture-independent entry points.
- */
-void tile_show_stack(struct KBacktraceIterator *kbt)
-{
- int i;
- int have_mmap_sem = 0;
-
- if (!start_backtrace())
- return;
- kbt->verbose = 1;
- i = 0;
- for (; !KBacktraceIterator_end(kbt); KBacktraceIterator_next(kbt)) {
- char namebuf[KSYM_NAME_LEN+100];
- unsigned long address = kbt->it.pc;
-
- /*
- * Try to acquire the mmap_sem as we pass into userspace.
- * If we're in an interrupt context, don't even try, since
- * it's not safe to call e.g. d_path() from an interrupt,
- * since it uses spin locks without disabling interrupts.
- * Note we test "kbt->task == current", not "kbt->is_current",
- * since we're checking that "current" will work in d_path().
- */
- if (kbt->task == current && address < PAGE_OFFSET &&
- !have_mmap_sem && kbt->task->mm && !in_interrupt()) {
- have_mmap_sem =
- down_read_trylock(&kbt->task->mm->mmap_sem);
- }
-
- describe_addr(kbt, address, have_mmap_sem,
- namebuf, sizeof(namebuf));
-
- pr_err(" frame %d: 0x%lx %s(sp 0x%lx)\n",
- i++, address, namebuf, (unsigned long)(kbt->it.sp));
-
- if (i >= 100) {
- pr_err("Stack dump truncated (%d frames)\n", i);
- break;
- }
- }
- if (kbt->end == KBT_LOOP)
- pr_err("Stack dump stopped; next frame identical to this one\n");
- if (have_mmap_sem)
- up_read(&kbt->task->mm->mmap_sem);
- end_backtrace();
-}
-EXPORT_SYMBOL(tile_show_stack);
-
-static struct pt_regs *regs_to_pt_regs(struct pt_regs *regs,
- ulong pc, ulong lr, ulong sp, ulong r52)
-{
- memset(regs, 0, sizeof(struct pt_regs));
- regs->pc = pc;
- regs->lr = lr;
- regs->sp = sp;
- regs->regs[52] = r52;
- return regs;
-}
-
-/* Deprecated function currently only used by kernel_double_fault(). */
-void _dump_stack(int dummy, ulong pc, ulong lr, ulong sp, ulong r52)
-{
- struct KBacktraceIterator kbt;
- struct pt_regs regs;
-
- regs_to_pt_regs(&regs, pc, lr, sp, r52);
- KBacktraceIterator_init(&kbt, NULL, &regs);
- tile_show_stack(&kbt);
-}
-
-/* This is called from KBacktraceIterator_init_current() */
-void _KBacktraceIterator_init_current(struct KBacktraceIterator *kbt, ulong pc,
- ulong lr, ulong sp, ulong r52)
-{
- struct pt_regs regs;
- KBacktraceIterator_init(kbt, NULL,
- regs_to_pt_regs(&regs, pc, lr, sp, r52));
-}
-
-/*
- * Called from sched_show_task() with task != NULL, or dump_stack()
- * with task == NULL. The esp argument is always NULL.
- */
-void show_stack(struct task_struct *task, unsigned long *esp)
-{
- struct KBacktraceIterator kbt;
- if (task == NULL || task == current) {
- KBacktraceIterator_init_current(&kbt);
- KBacktraceIterator_next(&kbt); /* don't show first frame */
- } else {
- KBacktraceIterator_init(&kbt, task, NULL);
- }
- tile_show_stack(&kbt);
-}
-
-#ifdef CONFIG_STACKTRACE
-
-/* Support generic Linux stack API too */
-
-static void save_stack_trace_common(struct task_struct *task,
- struct pt_regs *regs,
- bool user,
- struct stack_trace *trace)
-{
- struct KBacktraceIterator kbt;
- int skip = trace->skip;
- int i = 0;
-
- if (!start_backtrace())
- goto done;
- if (regs != NULL) {
- KBacktraceIterator_init(&kbt, NULL, regs);
- } else if (task == NULL || task == current) {
- KBacktraceIterator_init_current(&kbt);
- skip++; /* don't show KBacktraceIterator_init_current */
- } else {
- KBacktraceIterator_init(&kbt, task, NULL);
- }
- for (; !KBacktraceIterator_end(&kbt); KBacktraceIterator_next(&kbt)) {
- if (skip) {
- --skip;
- continue;
- }
- if (i >= trace->max_entries ||
- (!user && kbt.it.pc < PAGE_OFFSET))
- break;
- trace->entries[i++] = kbt.it.pc;
- }
- end_backtrace();
-done:
- if (i < trace->max_entries)
- trace->entries[i++] = ULONG_MAX;
- trace->nr_entries = i;
-}
-
-void save_stack_trace_tsk(struct task_struct *task, struct stack_trace *trace)
-{
- save_stack_trace_common(task, NULL, false, trace);
-}
-EXPORT_SYMBOL(save_stack_trace_tsk);
-
-void save_stack_trace(struct stack_trace *trace)
-{
- save_stack_trace_common(NULL, NULL, false, trace);
-}
-EXPORT_SYMBOL_GPL(save_stack_trace);
-
-void save_stack_trace_regs(struct pt_regs *regs, struct stack_trace *trace)
-{
- save_stack_trace_common(NULL, regs, false, trace);
-}
-
-void save_stack_trace_user(struct stack_trace *trace)
-{
- /* Trace user stack if we are not a kernel thread. */
- if (current->mm)
- save_stack_trace_common(NULL, task_pt_regs(current),
- true, trace);
- else if (trace->nr_entries < trace->max_entries)
- trace->entries[trace->nr_entries++] = ULONG_MAX;
-}
-#endif
-
-/* In entry.S */
-EXPORT_SYMBOL(KBacktraceIterator_init_current);
diff --git a/arch/tile/kernel/sys.c b/arch/tile/kernel/sys.c
deleted file mode 100644
index c7418dcbbb08..000000000000
--- a/arch/tile/kernel/sys.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on the Linux/TILE
- * platform.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/mempolicy.h>
-#include <linux/binfmts.h>
-#include <linux/fs.h>
-#include <linux/compat.h>
-#include <linux/uaccess.h>
-#include <linux/signal.h>
-#include <asm/syscalls.h>
-#include <asm/pgtable.h>
-#include <asm/homecache.h>
-#include <asm/cachectl.h>
-#include <asm/byteorder.h>
-#include <arch/chip.h>
-
-SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, len,
- unsigned long, flags)
-{
- /* DCACHE is not particularly effective if not bound to one cpu. */
- if (flags & DCACHE)
- homecache_evict(cpumask_of(raw_smp_processor_id()));
-
- if (flags & ICACHE)
- flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(current->mm),
- 0, 0, 0, NULL, NULL, 0);
- return 0;
-}
-
-/*
- * Syscalls that pass 64-bit values on 32-bit systems normally
- * pass them as (low,high) word packed into the immediately adjacent
- * registers. If the low word naturally falls on an even register,
- * our ABI makes it work correctly; if not, we adjust it here.
- * Handling it here means we don't have to fix uclibc AND glibc AND
- * any other standard libcs we want to support.
- */
-
-#if !defined(__tilegx__) || defined(CONFIG_COMPAT)
-
-#ifdef __BIG_ENDIAN
-#define SYSCALL_PAIR(name) u32 name ## _hi, u32 name ## _lo
-#else
-#define SYSCALL_PAIR(name) u32 name ## _lo, u32 name ## _hi
-#endif
-
-ssize_t sys32_readahead(int fd, SYSCALL_PAIR(offset), u32 count)
-{
- return sys_readahead(fd, ((loff_t)offset_hi << 32) | offset_lo, count);
-}
-
-int sys32_fadvise64_64(int fd, SYSCALL_PAIR(offset),
- SYSCALL_PAIR(len), int advice)
-{
- return sys_fadvise64_64(fd, ((loff_t)offset_hi << 32) | offset_lo,
- ((loff_t)len_hi << 32) | len_lo, advice);
-}
-
-#endif /* 32-bit syscall wrappers */
-
-/* Note: used by the compat code even in 64-bit Linux. */
-SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len,
- unsigned long, prot, unsigned long, flags,
- unsigned long, fd, unsigned long, off_4k)
-{
-#define PAGE_ADJUST (PAGE_SHIFT - 12)
- if (off_4k & ((1 << PAGE_ADJUST) - 1))
- return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- off_4k >> PAGE_ADJUST);
-}
-
-#ifdef __tilegx__
-SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
- unsigned long, prot, unsigned long, flags,
- unsigned long, fd, off_t, offset)
-{
- if (offset & ((1 << PAGE_SHIFT) - 1))
- return -EINVAL;
- return sys_mmap_pgoff(addr, len, prot, flags, fd,
- offset >> PAGE_SHIFT);
-}
-#endif
-
-
-/* Provide the actual syscall number to call mapping. */
-#undef __SYSCALL
-#define __SYSCALL(nr, call) [nr] = (call),
-
-#ifndef __tilegx__
-/* See comments at the top of the file. */
-#define sys_fadvise64_64 sys32_fadvise64_64
-#define sys_readahead sys32_readahead
-#endif
-
-/* Call the assembly trampolines where necessary. */
-#undef sys_rt_sigreturn
-#define sys_rt_sigreturn _sys_rt_sigreturn
-#define sys_clone _sys_clone
-
-/*
- * Note that we can't include <linux/unistd.h> here since the header
- * guard will defeat us; <asm/unistd.h> checks for __SYSCALL as well.
- */
-void *sys_call_table[__NR_syscalls] = {
- [0 ... __NR_syscalls-1] = sys_ni_syscall,
-#include <asm/unistd.h>
-};
diff --git a/arch/tile/kernel/sysfs.c b/arch/tile/kernel/sysfs.c
deleted file mode 100644
index b09456a3d77a..000000000000
--- a/arch/tile/kernel/sysfs.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * /sys entry support.
- */
-
-#include <linux/device.h>
-#include <linux/cpu.h>
-#include <linux/slab.h>
-#include <linux/smp.h>
-#include <linux/stat.h>
-#include <hv/hypervisor.h>
-
-/* Return a string queried from the hypervisor, truncated to page size. */
-static ssize_t get_hv_confstr(char *page, int query)
-{
- ssize_t n = hv_confstr(query, (unsigned long)page, PAGE_SIZE - 1);
- n = n < 0 ? 0 : min(n, (ssize_t)PAGE_SIZE - 1) - 1;
- if (n)
- page[n++] = '\n';
- page[n] = '\0';
- return n;
-}
-
-static ssize_t chip_width_show(struct device *dev,
- struct device_attribute *attr,
- char *page)
-{
- return sprintf(page, "%u\n", smp_width);
-}
-static DEVICE_ATTR_RO(chip_width);
-
-static ssize_t chip_height_show(struct device *dev,
- struct device_attribute *attr,
- char *page)
-{
- return sprintf(page, "%u\n", smp_height);
-}
-static DEVICE_ATTR_RO(chip_height);
-
-static ssize_t chip_serial_show(struct device *dev,
- struct device_attribute *attr,
- char *page)
-{
- return get_hv_confstr(page, HV_CONFSTR_CHIP_SERIAL_NUM);
-}
-static DEVICE_ATTR_RO(chip_serial);
-
-static ssize_t chip_revision_show(struct device *dev,
- struct device_attribute *attr,
- char *page)
-{
- return get_hv_confstr(page, HV_CONFSTR_CHIP_REV);
-}
-static DEVICE_ATTR_RO(chip_revision);
-
-
-static ssize_t type_show(struct device *dev,
- struct device_attribute *attr,
- char *page)
-{
- return sprintf(page, "tilera\n");
-}
-static DEVICE_ATTR_RO(type);
-
-#define HV_CONF_ATTR(name, conf) \
- static ssize_t name ## _show(struct device *dev, \
- struct device_attribute *attr, \
- char *page) \
- { \
- return get_hv_confstr(page, conf); \
- } \
- static DEVICE_ATTR(name, 0444, name ## _show, NULL);
-
-HV_CONF_ATTR(version, HV_CONFSTR_HV_SW_VER)
-HV_CONF_ATTR(config_version, HV_CONFSTR_HV_CONFIG_VER)
-
-HV_CONF_ATTR(board_part, HV_CONFSTR_BOARD_PART_NUM)
-HV_CONF_ATTR(board_serial, HV_CONFSTR_BOARD_SERIAL_NUM)
-HV_CONF_ATTR(board_revision, HV_CONFSTR_BOARD_REV)
-HV_CONF_ATTR(board_description, HV_CONFSTR_BOARD_DESC)
-HV_CONF_ATTR(mezz_part, HV_CONFSTR_MEZZ_PART_NUM)
-HV_CONF_ATTR(mezz_serial, HV_CONFSTR_MEZZ_SERIAL_NUM)
-HV_CONF_ATTR(mezz_revision, HV_CONFSTR_MEZZ_REV)
-HV_CONF_ATTR(mezz_description, HV_CONFSTR_MEZZ_DESC)
-HV_CONF_ATTR(cpumod_part, HV_CONFSTR_CPUMOD_PART_NUM)
-HV_CONF_ATTR(cpumod_serial, HV_CONFSTR_CPUMOD_SERIAL_NUM)
-HV_CONF_ATTR(cpumod_revision, HV_CONFSTR_CPUMOD_REV)
-HV_CONF_ATTR(cpumod_description,HV_CONFSTR_CPUMOD_DESC)
-HV_CONF_ATTR(switch_control, HV_CONFSTR_SWITCH_CONTROL)
-
-static struct attribute *board_attrs[] = {
- &dev_attr_board_part.attr,
- &dev_attr_board_serial.attr,
- &dev_attr_board_revision.attr,
- &dev_attr_board_description.attr,
- &dev_attr_mezz_part.attr,
- &dev_attr_mezz_serial.attr,
- &dev_attr_mezz_revision.attr,
- &dev_attr_mezz_description.attr,
- &dev_attr_cpumod_part.attr,
- &dev_attr_cpumod_serial.attr,
- &dev_attr_cpumod_revision.attr,
- &dev_attr_cpumod_description.attr,
- &dev_attr_switch_control.attr,
- NULL
-};
-
-static struct attribute_group board_attr_group = {
- .name = "board",
- .attrs = board_attrs,
-};
-
-
-static struct bin_attribute hvconfig_bin;
-
-static ssize_t
-hvconfig_bin_read(struct file *filp, struct kobject *kobj,
- struct bin_attribute *bin_attr,
- char *buf, loff_t off, size_t count)
-{
- static size_t size;
-
- /* Lazily learn the true size (minus the trailing NUL). */
- if (size == 0)
- size = hv_confstr(HV_CONFSTR_HV_CONFIG, 0, 0) - 1;
-
- /* Check and adjust input parameters. */
- if (off > size)
- return -EINVAL;
- if (count > size - off)
- count = size - off;
-
- if (count) {
- /* Get a copy of the hvc and copy out the relevant portion. */
- char *hvc;
-
- size = off + count;
- hvc = kmalloc(size, GFP_KERNEL);
- if (hvc == NULL)
- return -ENOMEM;
- hv_confstr(HV_CONFSTR_HV_CONFIG, (unsigned long)hvc, size);
- memcpy(buf, hvc + off, count);
- kfree(hvc);
- }
-
- return count;
-}
-
-static ssize_t hv_stats_show(struct device *dev,
- struct device_attribute *attr,
- char *page)
-{
- int cpu = dev->id;
- long lotar = HV_XY_TO_LOTAR(cpu_x(cpu), cpu_y(cpu));
-
- ssize_t n = hv_confstr(HV_CONFSTR_HV_STATS,
- (unsigned long)page, PAGE_SIZE - 1,
- lotar, 0);
- n = n < 0 ? 0 : min(n, (ssize_t)PAGE_SIZE - 1);
- page[n] = '\0';
- return n;
-}
-
-static ssize_t hv_stats_store(struct device *dev,
- struct device_attribute *attr,
- const char *page,
- size_t count)
-{
- int cpu = dev->id;
- long lotar = HV_XY_TO_LOTAR(cpu_x(cpu), cpu_y(cpu));
-
- ssize_t n = hv_confstr(HV_CONFSTR_HV_STATS, 0, 0, lotar, 1);
- return n < 0 ? n : count;
-}
-
-static DEVICE_ATTR_RW(hv_stats);
-
-static int hv_stats_device_add(struct device *dev, struct subsys_interface *sif)
-{
- int err, cpu = dev->id;
-
- if (!cpu_online(cpu))
- return 0;
-
- err = sysfs_create_file(&dev->kobj, &dev_attr_hv_stats.attr);
-
- return err;
-}
-
-static void hv_stats_device_remove(struct device *dev,
- struct subsys_interface *sif)
-{
- int cpu = dev->id;
-
- if (cpu_online(cpu))
- sysfs_remove_file(&dev->kobj, &dev_attr_hv_stats.attr);
-}
-
-
-static struct subsys_interface hv_stats_interface = {
- .name = "hv_stats",
- .subsys = &cpu_subsys,
- .add_dev = hv_stats_device_add,
- .remove_dev = hv_stats_device_remove,
-};
-
-static int __init create_sysfs_entries(void)
-{
- int err = 0;
-
-#define create_cpu_attr(name) \
- if (!err) \
- err = device_create_file(cpu_subsys.dev_root, &dev_attr_##name);
- create_cpu_attr(chip_width);
- create_cpu_attr(chip_height);
- create_cpu_attr(chip_serial);
- create_cpu_attr(chip_revision);
-
-#define create_hv_attr(name) \
- if (!err) \
- err = sysfs_create_file(hypervisor_kobj, &dev_attr_##name.attr);
- create_hv_attr(type);
- create_hv_attr(version);
- create_hv_attr(config_version);
-
- if (!err)
- err = sysfs_create_group(hypervisor_kobj, &board_attr_group);
-
- if (!err) {
- sysfs_bin_attr_init(&hvconfig_bin);
- hvconfig_bin.attr.name = "hvconfig";
- hvconfig_bin.attr.mode = S_IRUGO;
- hvconfig_bin.read = hvconfig_bin_read;
- hvconfig_bin.size = PAGE_SIZE;
- err = sysfs_create_bin_file(hypervisor_kobj, &hvconfig_bin);
- }
-
- if (!err) {
- /*
- * Don't bother adding the hv_stats files on each CPU if
- * our hypervisor doesn't supply statistics.
- */
- int cpu = raw_smp_processor_id();
- long lotar = HV_XY_TO_LOTAR(cpu_x(cpu), cpu_y(cpu));
- char dummy;
- ssize_t n = hv_confstr(HV_CONFSTR_HV_STATS,
- (unsigned long) &dummy, 1,
- lotar, 0);
- if (n >= 0)
- err = subsys_interface_register(&hv_stats_interface);
- }
-
- return err;
-}
-subsys_initcall(create_sysfs_entries);
diff --git a/arch/tile/kernel/tile-desc_32.c b/arch/tile/kernel/tile-desc_32.c
deleted file mode 100644
index dd7bd1d8563c..000000000000
--- a/arch/tile/kernel/tile-desc_32.c
+++ /dev/null
@@ -1,2605 +0,0 @@
-/* TILEPro opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
-#define BFD_RELOC(x) -1
-
-/* Special registers. */
-#define TREG_LR 55
-#define TREG_SN 56
-#define TREG_ZERO 63
-
-#include <linux/stddef.h>
-#include <asm/tile-desc.h>
-
-const struct tilepro_opcode tilepro_opcodes[395] =
-{
- { "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "info", TILEPRO_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
- { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
- },
- { "infol", TILEPRO_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
- { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "j", TILEPRO_OPC_J, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } },
- },
- { "jal", TILEPRO_OPC_JAL, 0x2, 1, TREG_LR, 1,
- { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } },
- },
- { "move", TILEPRO_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
- { { 7, 8 }, { 9, 10 }, { 11, 12 }, { 13, 14 }, { 0, } },
- },
- { "move.sn", TILEPRO_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1,
- { { 7, 8 }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "movei", TILEPRO_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
- { { 7, 0 }, { 9, 1 }, { 11, 2 }, { 13, 3 }, { 0, } },
- },
- { "movei.sn", TILEPRO_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1,
- { { 7, 0 }, { 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "moveli", TILEPRO_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
- { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "moveli.sn", TILEPRO_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1,
- { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "movelis", TILEPRO_OPC_MOVELIS, 0x3, 2, TREG_SN, 1,
- { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch", TILEPRO_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 15 } },
- },
- { "raise", TILEPRO_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "add", TILEPRO_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "add.sn", TILEPRO_OPC_ADD_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addb", TILEPRO_OPC_ADDB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addb.sn", TILEPRO_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addbs_u", TILEPRO_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addbs_u.sn", TILEPRO_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addh", TILEPRO_OPC_ADDH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addh.sn", TILEPRO_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addhs", TILEPRO_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addhs.sn", TILEPRO_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "addi", TILEPRO_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
- },
- { "addi.sn", TILEPRO_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "addib", TILEPRO_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "addib.sn", TILEPRO_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "addih", TILEPRO_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "addih.sn", TILEPRO_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "addli", TILEPRO_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "addli.sn", TILEPRO_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "addlis", TILEPRO_OPC_ADDLIS, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "adds", TILEPRO_OPC_ADDS, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "adds.sn", TILEPRO_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "adiffb_u", TILEPRO_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "adiffb_u.sn", TILEPRO_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "adiffh", TILEPRO_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "adiffh.sn", TILEPRO_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "and", TILEPRO_OPC_AND, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "and.sn", TILEPRO_OPC_AND_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "andi", TILEPRO_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
- },
- { "andi.sn", TILEPRO_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "auli", TILEPRO_OPC_AULI, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "avgb_u", TILEPRO_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "avgb_u.sn", TILEPRO_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "avgh", TILEPRO_OPC_AVGH, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "avgh.sn", TILEPRO_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "bbns", TILEPRO_OPC_BBNS, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bbns.sn", TILEPRO_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bbnst", TILEPRO_OPC_BBNST, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bbnst.sn", TILEPRO_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bbs", TILEPRO_OPC_BBS, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bbs.sn", TILEPRO_OPC_BBS_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bbst", TILEPRO_OPC_BBST, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bbst.sn", TILEPRO_OPC_BBST_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgez", TILEPRO_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgez.sn", TILEPRO_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgezt", TILEPRO_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgezt.sn", TILEPRO_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgz", TILEPRO_OPC_BGZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgz.sn", TILEPRO_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgzt", TILEPRO_OPC_BGZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgzt.sn", TILEPRO_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bitx", TILEPRO_OPC_BITX, 0x5, 2, TREG_ZERO, 1,
- { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
- },
- { "bitx.sn", TILEPRO_OPC_BITX_SN, 0x1, 2, TREG_SN, 1,
- { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "blez", TILEPRO_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blez.sn", TILEPRO_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blezt", TILEPRO_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blezt.sn", TILEPRO_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blz", TILEPRO_OPC_BLZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blz.sn", TILEPRO_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blzt", TILEPRO_OPC_BLZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blzt.sn", TILEPRO_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bnz", TILEPRO_OPC_BNZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bnz.sn", TILEPRO_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bnzt", TILEPRO_OPC_BNZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bnzt.sn", TILEPRO_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bytex", TILEPRO_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1,
- { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
- },
- { "bytex.sn", TILEPRO_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1,
- { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "bz", TILEPRO_OPC_BZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bz.sn", TILEPRO_OPC_BZ_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bzt", TILEPRO_OPC_BZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bzt.sn", TILEPRO_OPC_BZT_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "clz", TILEPRO_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
- { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
- },
- { "clz.sn", TILEPRO_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1,
- { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "crc32_32", TILEPRO_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "crc32_32.sn", TILEPRO_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "crc32_8", TILEPRO_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "crc32_8.sn", TILEPRO_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "ctz", TILEPRO_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
- { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
- },
- { "ctz.sn", TILEPRO_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1,
- { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "drain", TILEPRO_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "dtlbpr", TILEPRO_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "dword_align", TILEPRO_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "dword_align.sn", TILEPRO_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "finv", TILEPRO_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "flush", TILEPRO_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "fnop", TILEPRO_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
- { { }, { }, { }, { }, { 0, } },
- },
- { "icoh", TILEPRO_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "ill", TILEPRO_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { }, { 0, } },
- },
- { "inthb", TILEPRO_OPC_INTHB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "inthb.sn", TILEPRO_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "inthh", TILEPRO_OPC_INTHH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "inthh.sn", TILEPRO_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "intlb", TILEPRO_OPC_INTLB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "intlb.sn", TILEPRO_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "intlh", TILEPRO_OPC_INTLH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "intlh.sn", TILEPRO_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "inv", TILEPRO_OPC_INV, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "iret", TILEPRO_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "jalb", TILEPRO_OPC_JALB, 0x2, 1, TREG_LR, 1,
- { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
- },
- { "jalf", TILEPRO_OPC_JALF, 0x2, 1, TREG_LR, 1,
- { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
- },
- { "jalr", TILEPRO_OPC_JALR, 0x2, 1, TREG_LR, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "jalrp", TILEPRO_OPC_JALRP, 0x2, 1, TREG_LR, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "jb", TILEPRO_OPC_JB, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
- },
- { "jf", TILEPRO_OPC_JF, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } },
- },
- { "jr", TILEPRO_OPC_JR, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "jrp", TILEPRO_OPC_JRP, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lb", TILEPRO_OPC_LB, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
- },
- { "lb.sn", TILEPRO_OPC_LB_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lb_u", TILEPRO_OPC_LB_U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
- },
- { "lb_u.sn", TILEPRO_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lbadd", TILEPRO_OPC_LBADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lbadd.sn", TILEPRO_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lbadd_u", TILEPRO_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lbadd_u.sn", TILEPRO_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lh", TILEPRO_OPC_LH, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
- },
- { "lh.sn", TILEPRO_OPC_LH_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lh_u", TILEPRO_OPC_LH_U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
- },
- { "lh_u.sn", TILEPRO_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lhadd", TILEPRO_OPC_LHADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lhadd.sn", TILEPRO_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lhadd_u", TILEPRO_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lhadd_u.sn", TILEPRO_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lnk", TILEPRO_OPC_LNK, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "lnk.sn", TILEPRO_OPC_LNK_SN, 0x2, 1, TREG_SN, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "lw", TILEPRO_OPC_LW, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } },
- },
- { "lw.sn", TILEPRO_OPC_LW_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lw_na", TILEPRO_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lw_na.sn", TILEPRO_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "lwadd", TILEPRO_OPC_LWADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lwadd.sn", TILEPRO_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lwadd_na", TILEPRO_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lwadd_na.sn", TILEPRO_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1,
- { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxb_u", TILEPRO_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxb_u.sn", TILEPRO_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxh", TILEPRO_OPC_MAXH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxh.sn", TILEPRO_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxib_u", TILEPRO_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxib_u.sn", TILEPRO_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxih", TILEPRO_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "maxih.sn", TILEPRO_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "mf", TILEPRO_OPC_MF, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "mfspr", TILEPRO_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 25 }, { 0, }, { 0, }, { 0, } },
- },
- { "minb_u", TILEPRO_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "minb_u.sn", TILEPRO_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "minh", TILEPRO_OPC_MINH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "minh.sn", TILEPRO_OPC_MINH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "minib_u", TILEPRO_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "minib_u.sn", TILEPRO_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "minih", TILEPRO_OPC_MINIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "minih.sn", TILEPRO_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "mm", TILEPRO_OPC_MM, 0x3, 5, TREG_ZERO, 1,
- { { 7, 8, 16, 26, 27 }, { 9, 10, 17, 28, 29 }, { 0, }, { 0, }, { 0, } },
- },
- { "mnz", TILEPRO_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "mnz.sn", TILEPRO_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mnzb", TILEPRO_OPC_MNZB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mnzb.sn", TILEPRO_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mnzh", TILEPRO_OPC_MNZH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mnzh.sn", TILEPRO_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mtspr", TILEPRO_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 30, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhh_ss", TILEPRO_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
- },
- { "mulhh_ss.sn", TILEPRO_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhh_su", TILEPRO_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhh_su.sn", TILEPRO_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhh_uu", TILEPRO_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
- },
- { "mulhh_uu.sn", TILEPRO_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhha_ss", TILEPRO_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
- },
- { "mulhha_ss.sn", TILEPRO_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhha_su", TILEPRO_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhha_su.sn", TILEPRO_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhha_uu", TILEPRO_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
- },
- { "mulhha_uu.sn", TILEPRO_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhhsa_uu", TILEPRO_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhhsa_uu.sn", TILEPRO_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_ss", TILEPRO_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_ss.sn", TILEPRO_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_su", TILEPRO_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_su.sn", TILEPRO_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_us", TILEPRO_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_us.sn", TILEPRO_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_uu", TILEPRO_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhl_uu.sn", TILEPRO_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_ss", TILEPRO_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_ss.sn", TILEPRO_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_su", TILEPRO_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_su.sn", TILEPRO_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_us", TILEPRO_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_us.sn", TILEPRO_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_uu", TILEPRO_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhla_uu.sn", TILEPRO_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulhlsa_uu", TILEPRO_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
- },
- { "mulhlsa_uu.sn", TILEPRO_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulll_ss", TILEPRO_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
- },
- { "mulll_ss.sn", TILEPRO_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulll_su", TILEPRO_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulll_su.sn", TILEPRO_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulll_uu", TILEPRO_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } },
- },
- { "mulll_uu.sn", TILEPRO_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mullla_ss", TILEPRO_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
- },
- { "mullla_ss.sn", TILEPRO_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mullla_su", TILEPRO_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mullla_su.sn", TILEPRO_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mullla_uu", TILEPRO_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
- },
- { "mullla_uu.sn", TILEPRO_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulllsa_uu", TILEPRO_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mulllsa_uu.sn", TILEPRO_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mvnz", TILEPRO_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
- },
- { "mvnz.sn", TILEPRO_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mvz", TILEPRO_OPC_MVZ, 0x5, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } },
- },
- { "mvz.sn", TILEPRO_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mz", TILEPRO_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "mz.sn", TILEPRO_OPC_MZ_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mzb", TILEPRO_OPC_MZB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mzb.sn", TILEPRO_OPC_MZB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mzh", TILEPRO_OPC_MZH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "mzh.sn", TILEPRO_OPC_MZH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "nap", TILEPRO_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "nop", TILEPRO_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
- { { }, { }, { }, { }, { 0, } },
- },
- { "nor", TILEPRO_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "nor.sn", TILEPRO_OPC_NOR_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "or", TILEPRO_OPC_OR, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "or.sn", TILEPRO_OPC_OR_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "ori", TILEPRO_OPC_ORI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
- },
- { "ori.sn", TILEPRO_OPC_ORI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "packbs_u", TILEPRO_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "packbs_u.sn", TILEPRO_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "packhb", TILEPRO_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "packhb.sn", TILEPRO_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "packhs", TILEPRO_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "packhs.sn", TILEPRO_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "packlb", TILEPRO_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "packlb.sn", TILEPRO_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "pcnt", TILEPRO_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
- { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } },
- },
- { "pcnt.sn", TILEPRO_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1,
- { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "rl", TILEPRO_OPC_RL, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "rl.sn", TILEPRO_OPC_RL_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "rli", TILEPRO_OPC_RLI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
- },
- { "rli.sn", TILEPRO_OPC_RLI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "s1a", TILEPRO_OPC_S1A, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "s1a.sn", TILEPRO_OPC_S1A_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "s2a", TILEPRO_OPC_S2A, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "s2a.sn", TILEPRO_OPC_S2A_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "s3a", TILEPRO_OPC_S3A, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "s3a.sn", TILEPRO_OPC_S3A_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sadab_u", TILEPRO_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadab_u.sn", TILEPRO_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadah", TILEPRO_OPC_SADAH, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadah.sn", TILEPRO_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadah_u", TILEPRO_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadah_u.sn", TILEPRO_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1,
- { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadb_u", TILEPRO_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadb_u.sn", TILEPRO_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadh", TILEPRO_OPC_SADH, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadh.sn", TILEPRO_OPC_SADH_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadh_u", TILEPRO_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sadh_u.sn", TILEPRO_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "sb", TILEPRO_OPC_SB, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
- },
- { "sbadd", TILEPRO_OPC_SBADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } },
- },
- { "seq", TILEPRO_OPC_SEQ, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "seq.sn", TILEPRO_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqb", TILEPRO_OPC_SEQB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqb.sn", TILEPRO_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqh", TILEPRO_OPC_SEQH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqh.sn", TILEPRO_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqi", TILEPRO_OPC_SEQI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
- },
- { "seqi.sn", TILEPRO_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqib", TILEPRO_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqib.sn", TILEPRO_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqih", TILEPRO_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "seqih.sn", TILEPRO_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sh", TILEPRO_OPC_SH, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
- },
- { "shadd", TILEPRO_OPC_SHADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } },
- },
- { "shl", TILEPRO_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "shl.sn", TILEPRO_OPC_SHL_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlb", TILEPRO_OPC_SHLB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlb.sn", TILEPRO_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlh", TILEPRO_OPC_SHLH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlh.sn", TILEPRO_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shli", TILEPRO_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
- },
- { "shli.sn", TILEPRO_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlib", TILEPRO_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlib.sn", TILEPRO_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlih", TILEPRO_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlih.sn", TILEPRO_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shr", TILEPRO_OPC_SHR, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "shr.sn", TILEPRO_OPC_SHR_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrb", TILEPRO_OPC_SHRB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrb.sn", TILEPRO_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrh", TILEPRO_OPC_SHRH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrh.sn", TILEPRO_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shri", TILEPRO_OPC_SHRI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
- },
- { "shri.sn", TILEPRO_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrib", TILEPRO_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrib.sn", TILEPRO_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrih", TILEPRO_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrih.sn", TILEPRO_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "slt", TILEPRO_OPC_SLT, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "slt.sn", TILEPRO_OPC_SLT_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slt_u", TILEPRO_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "slt_u.sn", TILEPRO_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltb", TILEPRO_OPC_SLTB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltb.sn", TILEPRO_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltb_u", TILEPRO_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltb_u.sn", TILEPRO_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slte", TILEPRO_OPC_SLTE, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "slte.sn", TILEPRO_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slte_u", TILEPRO_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "slte_u.sn", TILEPRO_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteb", TILEPRO_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteb.sn", TILEPRO_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteb_u", TILEPRO_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteb_u.sn", TILEPRO_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteh", TILEPRO_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteh.sn", TILEPRO_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteh_u", TILEPRO_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slteh_u.sn", TILEPRO_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slth", TILEPRO_OPC_SLTH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slth.sn", TILEPRO_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slth_u", TILEPRO_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slth_u.sn", TILEPRO_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "slti", TILEPRO_OPC_SLTI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
- },
- { "slti.sn", TILEPRO_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "slti_u", TILEPRO_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } },
- },
- { "slti_u.sn", TILEPRO_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltib", TILEPRO_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltib.sn", TILEPRO_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltib_u", TILEPRO_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltib_u.sn", TILEPRO_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltih", TILEPRO_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltih.sn", TILEPRO_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltih_u", TILEPRO_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sltih_u.sn", TILEPRO_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "sne", TILEPRO_OPC_SNE, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "sne.sn", TILEPRO_OPC_SNE_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sneb", TILEPRO_OPC_SNEB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sneb.sn", TILEPRO_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sneh", TILEPRO_OPC_SNEH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sneh.sn", TILEPRO_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sra", TILEPRO_OPC_SRA, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "sra.sn", TILEPRO_OPC_SRA_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "srab", TILEPRO_OPC_SRAB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "srab.sn", TILEPRO_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "srah", TILEPRO_OPC_SRAH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "srah.sn", TILEPRO_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "srai", TILEPRO_OPC_SRAI, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } },
- },
- { "srai.sn", TILEPRO_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "sraib", TILEPRO_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "sraib.sn", TILEPRO_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "sraih", TILEPRO_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "sraih.sn", TILEPRO_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } },
- },
- { "sub", TILEPRO_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "sub.sn", TILEPRO_OPC_SUB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subb", TILEPRO_OPC_SUBB, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subb.sn", TILEPRO_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subbs_u", TILEPRO_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subbs_u.sn", TILEPRO_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subh", TILEPRO_OPC_SUBH, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subh.sn", TILEPRO_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subhs", TILEPRO_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subhs.sn", TILEPRO_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subs", TILEPRO_OPC_SUBS, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "subs.sn", TILEPRO_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "sw", TILEPRO_OPC_SW, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } },
- },
- { "swadd", TILEPRO_OPC_SWADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } },
- },
- { "swint0", TILEPRO_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "swint1", TILEPRO_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "swint2", TILEPRO_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "swint3", TILEPRO_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "tblidxb0", TILEPRO_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
- { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
- },
- { "tblidxb0.sn", TILEPRO_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1,
- { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "tblidxb1", TILEPRO_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
- { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
- },
- { "tblidxb1.sn", TILEPRO_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1,
- { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "tblidxb2", TILEPRO_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
- { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
- },
- { "tblidxb2.sn", TILEPRO_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1,
- { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "tblidxb3", TILEPRO_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
- { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } },
- },
- { "tblidxb3.sn", TILEPRO_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1,
- { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "tns", TILEPRO_OPC_TNS, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "tns.sn", TILEPRO_OPC_TNS_SN, 0x2, 2, TREG_SN, 1,
- { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "wh64", TILEPRO_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } },
- },
- { "xor", TILEPRO_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } },
- },
- { "xor.sn", TILEPRO_OPC_XOR_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "xori", TILEPRO_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "xori.sn", TILEPRO_OPC_XORI_SN, 0x3, 3, TREG_SN, 1,
- { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { NULL, TILEPRO_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
- }
-};
-#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
-#define CHILD(array_index) (TILEPRO_OPC_NONE + (array_index))
-
-static const unsigned short decode_X0_fsm[1153] =
-{
- BITFIELD(22, 9) /* index 0 */,
- CHILD(513), CHILD(530), CHILD(547), CHILD(564), CHILD(596), CHILD(613),
- CHILD(630), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(663), CHILD(680), CHILD(697),
- CHILD(714), CHILD(746), CHILD(763), CHILD(780), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813),
- CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828),
- CHILD(828), CHILD(828), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(873), CHILD(878), CHILD(883), CHILD(903), CHILD(908),
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(913),
- CHILD(918), CHILD(923), CHILD(943), CHILD(948), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(953), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(988), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(993), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1076), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(18, 4) /* index 513 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB, TILEPRO_OPC_ADDH, TILEPRO_OPC_ADD,
- TILEPRO_OPC_ADIFFB_U, TILEPRO_OPC_ADIFFH, TILEPRO_OPC_AND,
- TILEPRO_OPC_AVGB_U, TILEPRO_OPC_AVGH, TILEPRO_OPC_CRC32_32,
- TILEPRO_OPC_CRC32_8, TILEPRO_OPC_INTHB, TILEPRO_OPC_INTHH,
- TILEPRO_OPC_INTLB, TILEPRO_OPC_INTLH, TILEPRO_OPC_MAXB_U,
- BITFIELD(18, 4) /* index 530 */,
- TILEPRO_OPC_MAXH, TILEPRO_OPC_MINB_U, TILEPRO_OPC_MINH, TILEPRO_OPC_MNZB,
- TILEPRO_OPC_MNZH, TILEPRO_OPC_MNZ, TILEPRO_OPC_MULHHA_SS,
- TILEPRO_OPC_MULHHA_SU, TILEPRO_OPC_MULHHA_UU, TILEPRO_OPC_MULHHSA_UU,
- TILEPRO_OPC_MULHH_SS, TILEPRO_OPC_MULHH_SU, TILEPRO_OPC_MULHH_UU,
- TILEPRO_OPC_MULHLA_SS, TILEPRO_OPC_MULHLA_SU, TILEPRO_OPC_MULHLA_US,
- BITFIELD(18, 4) /* index 547 */,
- TILEPRO_OPC_MULHLA_UU, TILEPRO_OPC_MULHLSA_UU, TILEPRO_OPC_MULHL_SS,
- TILEPRO_OPC_MULHL_SU, TILEPRO_OPC_MULHL_US, TILEPRO_OPC_MULHL_UU,
- TILEPRO_OPC_MULLLA_SS, TILEPRO_OPC_MULLLA_SU, TILEPRO_OPC_MULLLA_UU,
- TILEPRO_OPC_MULLLSA_UU, TILEPRO_OPC_MULLL_SS, TILEPRO_OPC_MULLL_SU,
- TILEPRO_OPC_MULLL_UU, TILEPRO_OPC_MVNZ, TILEPRO_OPC_MVZ, TILEPRO_OPC_MZB,
- BITFIELD(18, 4) /* index 564 */,
- TILEPRO_OPC_MZH, TILEPRO_OPC_MZ, TILEPRO_OPC_NOR, CHILD(581),
- TILEPRO_OPC_PACKHB, TILEPRO_OPC_PACKLB, TILEPRO_OPC_RL, TILEPRO_OPC_S1A,
- TILEPRO_OPC_S2A, TILEPRO_OPC_S3A, TILEPRO_OPC_SADAB_U, TILEPRO_OPC_SADAH,
- TILEPRO_OPC_SADAH_U, TILEPRO_OPC_SADB_U, TILEPRO_OPC_SADH,
- TILEPRO_OPC_SADH_U,
- BITFIELD(12, 2) /* index 581 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(586),
- BITFIELD(14, 2) /* index 586 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(591),
- BITFIELD(16, 2) /* index 591 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE,
- BITFIELD(18, 4) /* index 596 */,
- TILEPRO_OPC_SEQB, TILEPRO_OPC_SEQH, TILEPRO_OPC_SEQ, TILEPRO_OPC_SHLB,
- TILEPRO_OPC_SHLH, TILEPRO_OPC_SHL, TILEPRO_OPC_SHRB, TILEPRO_OPC_SHRH,
- TILEPRO_OPC_SHR, TILEPRO_OPC_SLTB, TILEPRO_OPC_SLTB_U, TILEPRO_OPC_SLTEB,
- TILEPRO_OPC_SLTEB_U, TILEPRO_OPC_SLTEH, TILEPRO_OPC_SLTEH_U,
- TILEPRO_OPC_SLTE,
- BITFIELD(18, 4) /* index 613 */,
- TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLTH, TILEPRO_OPC_SLTH_U, TILEPRO_OPC_SLT,
- TILEPRO_OPC_SLT_U, TILEPRO_OPC_SNEB, TILEPRO_OPC_SNEH, TILEPRO_OPC_SNE,
- TILEPRO_OPC_SRAB, TILEPRO_OPC_SRAH, TILEPRO_OPC_SRA, TILEPRO_OPC_SUBB,
- TILEPRO_OPC_SUBH, TILEPRO_OPC_SUB, TILEPRO_OPC_XOR, TILEPRO_OPC_DWORD_ALIGN,
- BITFIELD(18, 3) /* index 630 */,
- CHILD(639), CHILD(642), CHILD(645), CHILD(648), CHILD(651), CHILD(654),
- CHILD(657), CHILD(660),
- BITFIELD(21, 1) /* index 639 */,
- TILEPRO_OPC_ADDS, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 642 */,
- TILEPRO_OPC_SUBS, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 645 */,
- TILEPRO_OPC_ADDBS_U, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 648 */,
- TILEPRO_OPC_ADDHS, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 651 */,
- TILEPRO_OPC_SUBBS_U, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 654 */,
- TILEPRO_OPC_SUBHS, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 657 */,
- TILEPRO_OPC_PACKHS, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 660 */,
- TILEPRO_OPC_PACKBS_U, TILEPRO_OPC_NONE,
- BITFIELD(18, 4) /* index 663 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB_SN, TILEPRO_OPC_ADDH_SN,
- TILEPRO_OPC_ADD_SN, TILEPRO_OPC_ADIFFB_U_SN, TILEPRO_OPC_ADIFFH_SN,
- TILEPRO_OPC_AND_SN, TILEPRO_OPC_AVGB_U_SN, TILEPRO_OPC_AVGH_SN,
- TILEPRO_OPC_CRC32_32_SN, TILEPRO_OPC_CRC32_8_SN, TILEPRO_OPC_INTHB_SN,
- TILEPRO_OPC_INTHH_SN, TILEPRO_OPC_INTLB_SN, TILEPRO_OPC_INTLH_SN,
- TILEPRO_OPC_MAXB_U_SN,
- BITFIELD(18, 4) /* index 680 */,
- TILEPRO_OPC_MAXH_SN, TILEPRO_OPC_MINB_U_SN, TILEPRO_OPC_MINH_SN,
- TILEPRO_OPC_MNZB_SN, TILEPRO_OPC_MNZH_SN, TILEPRO_OPC_MNZ_SN,
- TILEPRO_OPC_MULHHA_SS_SN, TILEPRO_OPC_MULHHA_SU_SN,
- TILEPRO_OPC_MULHHA_UU_SN, TILEPRO_OPC_MULHHSA_UU_SN,
- TILEPRO_OPC_MULHH_SS_SN, TILEPRO_OPC_MULHH_SU_SN, TILEPRO_OPC_MULHH_UU_SN,
- TILEPRO_OPC_MULHLA_SS_SN, TILEPRO_OPC_MULHLA_SU_SN,
- TILEPRO_OPC_MULHLA_US_SN,
- BITFIELD(18, 4) /* index 697 */,
- TILEPRO_OPC_MULHLA_UU_SN, TILEPRO_OPC_MULHLSA_UU_SN,
- TILEPRO_OPC_MULHL_SS_SN, TILEPRO_OPC_MULHL_SU_SN, TILEPRO_OPC_MULHL_US_SN,
- TILEPRO_OPC_MULHL_UU_SN, TILEPRO_OPC_MULLLA_SS_SN, TILEPRO_OPC_MULLLA_SU_SN,
- TILEPRO_OPC_MULLLA_UU_SN, TILEPRO_OPC_MULLLSA_UU_SN,
- TILEPRO_OPC_MULLL_SS_SN, TILEPRO_OPC_MULLL_SU_SN, TILEPRO_OPC_MULLL_UU_SN,
- TILEPRO_OPC_MVNZ_SN, TILEPRO_OPC_MVZ_SN, TILEPRO_OPC_MZB_SN,
- BITFIELD(18, 4) /* index 714 */,
- TILEPRO_OPC_MZH_SN, TILEPRO_OPC_MZ_SN, TILEPRO_OPC_NOR_SN, CHILD(731),
- TILEPRO_OPC_PACKHB_SN, TILEPRO_OPC_PACKLB_SN, TILEPRO_OPC_RL_SN,
- TILEPRO_OPC_S1A_SN, TILEPRO_OPC_S2A_SN, TILEPRO_OPC_S3A_SN,
- TILEPRO_OPC_SADAB_U_SN, TILEPRO_OPC_SADAH_SN, TILEPRO_OPC_SADAH_U_SN,
- TILEPRO_OPC_SADB_U_SN, TILEPRO_OPC_SADH_SN, TILEPRO_OPC_SADH_U_SN,
- BITFIELD(12, 2) /* index 731 */,
- TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(736),
- BITFIELD(14, 2) /* index 736 */,
- TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(741),
- BITFIELD(16, 2) /* index 741 */,
- TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN,
- TILEPRO_OPC_MOVE_SN,
- BITFIELD(18, 4) /* index 746 */,
- TILEPRO_OPC_SEQB_SN, TILEPRO_OPC_SEQH_SN, TILEPRO_OPC_SEQ_SN,
- TILEPRO_OPC_SHLB_SN, TILEPRO_OPC_SHLH_SN, TILEPRO_OPC_SHL_SN,
- TILEPRO_OPC_SHRB_SN, TILEPRO_OPC_SHRH_SN, TILEPRO_OPC_SHR_SN,
- TILEPRO_OPC_SLTB_SN, TILEPRO_OPC_SLTB_U_SN, TILEPRO_OPC_SLTEB_SN,
- TILEPRO_OPC_SLTEB_U_SN, TILEPRO_OPC_SLTEH_SN, TILEPRO_OPC_SLTEH_U_SN,
- TILEPRO_OPC_SLTE_SN,
- BITFIELD(18, 4) /* index 763 */,
- TILEPRO_OPC_SLTE_U_SN, TILEPRO_OPC_SLTH_SN, TILEPRO_OPC_SLTH_U_SN,
- TILEPRO_OPC_SLT_SN, TILEPRO_OPC_SLT_U_SN, TILEPRO_OPC_SNEB_SN,
- TILEPRO_OPC_SNEH_SN, TILEPRO_OPC_SNE_SN, TILEPRO_OPC_SRAB_SN,
- TILEPRO_OPC_SRAH_SN, TILEPRO_OPC_SRA_SN, TILEPRO_OPC_SUBB_SN,
- TILEPRO_OPC_SUBH_SN, TILEPRO_OPC_SUB_SN, TILEPRO_OPC_XOR_SN,
- TILEPRO_OPC_DWORD_ALIGN_SN,
- BITFIELD(18, 3) /* index 780 */,
- CHILD(789), CHILD(792), CHILD(795), CHILD(798), CHILD(801), CHILD(804),
- CHILD(807), CHILD(810),
- BITFIELD(21, 1) /* index 789 */,
- TILEPRO_OPC_ADDS_SN, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 792 */,
- TILEPRO_OPC_SUBS_SN, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 795 */,
- TILEPRO_OPC_ADDBS_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 798 */,
- TILEPRO_OPC_ADDHS_SN, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 801 */,
- TILEPRO_OPC_SUBBS_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 804 */,
- TILEPRO_OPC_SUBHS_SN, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 807 */,
- TILEPRO_OPC_PACKHS_SN, TILEPRO_OPC_NONE,
- BITFIELD(21, 1) /* index 810 */,
- TILEPRO_OPC_PACKBS_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(6, 2) /* index 813 */,
- TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN,
- CHILD(818),
- BITFIELD(8, 2) /* index 818 */,
- TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN,
- CHILD(823),
- BITFIELD(10, 2) /* index 823 */,
- TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN,
- TILEPRO_OPC_MOVELI_SN,
- BITFIELD(6, 2) /* index 828 */,
- TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(833),
- BITFIELD(8, 2) /* index 833 */,
- TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(838),
- BITFIELD(10, 2) /* index 838 */,
- TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_MOVELI,
- BITFIELD(0, 2) /* index 843 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(848),
- BITFIELD(2, 2) /* index 848 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(853),
- BITFIELD(4, 2) /* index 853 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(858),
- BITFIELD(6, 2) /* index 858 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(863),
- BITFIELD(8, 2) /* index 863 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(868),
- BITFIELD(10, 2) /* index 868 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_INFOL,
- BITFIELD(20, 2) /* index 873 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB, TILEPRO_OPC_ADDIH, TILEPRO_OPC_ADDI,
- BITFIELD(20, 2) /* index 878 */,
- TILEPRO_OPC_MAXIB_U, TILEPRO_OPC_MAXIH, TILEPRO_OPC_MINIB_U,
- TILEPRO_OPC_MINIH,
- BITFIELD(20, 2) /* index 883 */,
- CHILD(888), TILEPRO_OPC_SEQIB, TILEPRO_OPC_SEQIH, TILEPRO_OPC_SEQI,
- BITFIELD(6, 2) /* index 888 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(893),
- BITFIELD(8, 2) /* index 893 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(898),
- BITFIELD(10, 2) /* index 898 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI,
- BITFIELD(20, 2) /* index 903 */,
- TILEPRO_OPC_SLTIB, TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH,
- TILEPRO_OPC_SLTIH_U,
- BITFIELD(20, 2) /* index 908 */,
- TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(20, 2) /* index 913 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN,
- TILEPRO_OPC_ADDI_SN,
- BITFIELD(20, 2) /* index 918 */,
- TILEPRO_OPC_MAXIB_U_SN, TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MINIB_U_SN,
- TILEPRO_OPC_MINIH_SN,
- BITFIELD(20, 2) /* index 923 */,
- CHILD(928), TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN,
- BITFIELD(6, 2) /* index 928 */,
- TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(933),
- BITFIELD(8, 2) /* index 933 */,
- TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(938),
- BITFIELD(10, 2) /* index 938 */,
- TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN,
- TILEPRO_OPC_MOVEI_SN,
- BITFIELD(20, 2) /* index 943 */,
- TILEPRO_OPC_SLTIB_SN, TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN,
- TILEPRO_OPC_SLTIH_U_SN,
- BITFIELD(20, 2) /* index 948 */,
- TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE,
- BITFIELD(20, 2) /* index 953 */,
- TILEPRO_OPC_NONE, CHILD(958), TILEPRO_OPC_XORI, TILEPRO_OPC_NONE,
- BITFIELD(0, 2) /* index 958 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(963),
- BITFIELD(2, 2) /* index 963 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(968),
- BITFIELD(4, 2) /* index 968 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(973),
- BITFIELD(6, 2) /* index 973 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(978),
- BITFIELD(8, 2) /* index 978 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(983),
- BITFIELD(10, 2) /* index 983 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO,
- BITFIELD(20, 2) /* index 988 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_XORI_SN,
- TILEPRO_OPC_NONE,
- BITFIELD(17, 5) /* index 993 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_RLI, TILEPRO_OPC_SHLIB, TILEPRO_OPC_SHLIH,
- TILEPRO_OPC_SHLI, TILEPRO_OPC_SHRIB, TILEPRO_OPC_SHRIH, TILEPRO_OPC_SHRI,
- TILEPRO_OPC_SRAIB, TILEPRO_OPC_SRAIH, TILEPRO_OPC_SRAI, CHILD(1026),
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(12, 4) /* index 1026 */,
- TILEPRO_OPC_NONE, CHILD(1043), CHILD(1046), CHILD(1049), CHILD(1052),
- CHILD(1055), CHILD(1058), CHILD(1061), CHILD(1064), CHILD(1067),
- CHILD(1070), CHILD(1073), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1043 */,
- TILEPRO_OPC_BITX, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1046 */,
- TILEPRO_OPC_BYTEX, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1049 */,
- TILEPRO_OPC_CLZ, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1052 */,
- TILEPRO_OPC_CTZ, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1055 */,
- TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1058 */,
- TILEPRO_OPC_NOP, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1061 */,
- TILEPRO_OPC_PCNT, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1064 */,
- TILEPRO_OPC_TBLIDXB0, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1067 */,
- TILEPRO_OPC_TBLIDXB1, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1070 */,
- TILEPRO_OPC_TBLIDXB2, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1073 */,
- TILEPRO_OPC_TBLIDXB3, TILEPRO_OPC_NONE,
- BITFIELD(17, 5) /* index 1076 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_RLI_SN, TILEPRO_OPC_SHLIB_SN,
- TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_SHRIB_SN,
- TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_SRAIB_SN,
- TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_SRAI_SN, CHILD(1109), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(12, 4) /* index 1109 */,
- TILEPRO_OPC_NONE, CHILD(1126), CHILD(1129), CHILD(1132), CHILD(1135),
- CHILD(1055), CHILD(1058), CHILD(1138), CHILD(1141), CHILD(1144),
- CHILD(1147), CHILD(1150), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1126 */,
- TILEPRO_OPC_BITX_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1129 */,
- TILEPRO_OPC_BYTEX_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1132 */,
- TILEPRO_OPC_CLZ_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1135 */,
- TILEPRO_OPC_CTZ_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1138 */,
- TILEPRO_OPC_PCNT_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1141 */,
- TILEPRO_OPC_TBLIDXB0_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1144 */,
- TILEPRO_OPC_TBLIDXB1_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1147 */,
- TILEPRO_OPC_TBLIDXB2_SN, TILEPRO_OPC_NONE,
- BITFIELD(16, 1) /* index 1150 */,
- TILEPRO_OPC_TBLIDXB3_SN, TILEPRO_OPC_NONE,
-};
-
-static const unsigned short decode_X1_fsm[1540] =
-{
- BITFIELD(54, 9) /* index 0 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- CHILD(513), CHILD(561), CHILD(594), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(641),
- CHILD(689), CHILD(722), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(766),
- CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
- CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
- CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
- CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
- CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766),
- CHILD(766), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
- CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
- CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
- CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
- CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781), CHILD(781),
- CHILD(781), CHILD(781), CHILD(781), CHILD(796), CHILD(796), CHILD(796),
- CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
- CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
- CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
- CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796),
- CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(796), CHILD(826),
- CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826),
- CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826), CHILD(826),
- CHILD(826), CHILD(826), CHILD(826), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843),
- CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932),
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- CHILD(941), CHILD(950), CHILD(974), CHILD(983), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM,
- TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(992),
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1334),
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J,
- TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL,
- TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(49, 5) /* index 513 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB, TILEPRO_OPC_ADDH, TILEPRO_OPC_ADD,
- TILEPRO_OPC_AND, TILEPRO_OPC_INTHB, TILEPRO_OPC_INTHH, TILEPRO_OPC_INTLB,
- TILEPRO_OPC_INTLH, TILEPRO_OPC_JALRP, TILEPRO_OPC_JALR, TILEPRO_OPC_JRP,
- TILEPRO_OPC_JR, TILEPRO_OPC_LNK, TILEPRO_OPC_MAXB_U, TILEPRO_OPC_MAXH,
- TILEPRO_OPC_MINB_U, TILEPRO_OPC_MINH, TILEPRO_OPC_MNZB, TILEPRO_OPC_MNZH,
- TILEPRO_OPC_MNZ, TILEPRO_OPC_MZB, TILEPRO_OPC_MZH, TILEPRO_OPC_MZ,
- TILEPRO_OPC_NOR, CHILD(546), TILEPRO_OPC_PACKHB, TILEPRO_OPC_PACKLB,
- TILEPRO_OPC_RL, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_S3A,
- BITFIELD(43, 2) /* index 546 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(551),
- BITFIELD(45, 2) /* index 551 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(556),
- BITFIELD(47, 2) /* index 556 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE,
- BITFIELD(49, 5) /* index 561 */,
- TILEPRO_OPC_SB, TILEPRO_OPC_SEQB, TILEPRO_OPC_SEQH, TILEPRO_OPC_SEQ,
- TILEPRO_OPC_SHLB, TILEPRO_OPC_SHLH, TILEPRO_OPC_SHL, TILEPRO_OPC_SHRB,
- TILEPRO_OPC_SHRH, TILEPRO_OPC_SHR, TILEPRO_OPC_SH, TILEPRO_OPC_SLTB,
- TILEPRO_OPC_SLTB_U, TILEPRO_OPC_SLTEB, TILEPRO_OPC_SLTEB_U,
- TILEPRO_OPC_SLTEH, TILEPRO_OPC_SLTEH_U, TILEPRO_OPC_SLTE,
- TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLTH, TILEPRO_OPC_SLTH_U, TILEPRO_OPC_SLT,
- TILEPRO_OPC_SLT_U, TILEPRO_OPC_SNEB, TILEPRO_OPC_SNEH, TILEPRO_OPC_SNE,
- TILEPRO_OPC_SRAB, TILEPRO_OPC_SRAH, TILEPRO_OPC_SRA, TILEPRO_OPC_SUBB,
- TILEPRO_OPC_SUBH, TILEPRO_OPC_SUB,
- BITFIELD(49, 4) /* index 594 */,
- CHILD(611), CHILD(614), CHILD(617), CHILD(620), CHILD(623), CHILD(626),
- CHILD(629), CHILD(632), CHILD(635), CHILD(638), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 611 */,
- TILEPRO_OPC_SW, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 614 */,
- TILEPRO_OPC_XOR, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 617 */,
- TILEPRO_OPC_ADDS, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 620 */,
- TILEPRO_OPC_SUBS, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 623 */,
- TILEPRO_OPC_ADDBS_U, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 626 */,
- TILEPRO_OPC_ADDHS, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 629 */,
- TILEPRO_OPC_SUBBS_U, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 632 */,
- TILEPRO_OPC_SUBHS, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 635 */,
- TILEPRO_OPC_PACKHS, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 638 */,
- TILEPRO_OPC_PACKBS_U, TILEPRO_OPC_NONE,
- BITFIELD(49, 5) /* index 641 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB_SN, TILEPRO_OPC_ADDH_SN,
- TILEPRO_OPC_ADD_SN, TILEPRO_OPC_AND_SN, TILEPRO_OPC_INTHB_SN,
- TILEPRO_OPC_INTHH_SN, TILEPRO_OPC_INTLB_SN, TILEPRO_OPC_INTLH_SN,
- TILEPRO_OPC_JALRP, TILEPRO_OPC_JALR, TILEPRO_OPC_JRP, TILEPRO_OPC_JR,
- TILEPRO_OPC_LNK_SN, TILEPRO_OPC_MAXB_U_SN, TILEPRO_OPC_MAXH_SN,
- TILEPRO_OPC_MINB_U_SN, TILEPRO_OPC_MINH_SN, TILEPRO_OPC_MNZB_SN,
- TILEPRO_OPC_MNZH_SN, TILEPRO_OPC_MNZ_SN, TILEPRO_OPC_MZB_SN,
- TILEPRO_OPC_MZH_SN, TILEPRO_OPC_MZ_SN, TILEPRO_OPC_NOR_SN, CHILD(674),
- TILEPRO_OPC_PACKHB_SN, TILEPRO_OPC_PACKLB_SN, TILEPRO_OPC_RL_SN,
- TILEPRO_OPC_S1A_SN, TILEPRO_OPC_S2A_SN, TILEPRO_OPC_S3A_SN,
- BITFIELD(43, 2) /* index 674 */,
- TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(679),
- BITFIELD(45, 2) /* index 679 */,
- TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(684),
- BITFIELD(47, 2) /* index 684 */,
- TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN,
- TILEPRO_OPC_MOVE_SN,
- BITFIELD(49, 5) /* index 689 */,
- TILEPRO_OPC_SB, TILEPRO_OPC_SEQB_SN, TILEPRO_OPC_SEQH_SN,
- TILEPRO_OPC_SEQ_SN, TILEPRO_OPC_SHLB_SN, TILEPRO_OPC_SHLH_SN,
- TILEPRO_OPC_SHL_SN, TILEPRO_OPC_SHRB_SN, TILEPRO_OPC_SHRH_SN,
- TILEPRO_OPC_SHR_SN, TILEPRO_OPC_SH, TILEPRO_OPC_SLTB_SN,
- TILEPRO_OPC_SLTB_U_SN, TILEPRO_OPC_SLTEB_SN, TILEPRO_OPC_SLTEB_U_SN,
- TILEPRO_OPC_SLTEH_SN, TILEPRO_OPC_SLTEH_U_SN, TILEPRO_OPC_SLTE_SN,
- TILEPRO_OPC_SLTE_U_SN, TILEPRO_OPC_SLTH_SN, TILEPRO_OPC_SLTH_U_SN,
- TILEPRO_OPC_SLT_SN, TILEPRO_OPC_SLT_U_SN, TILEPRO_OPC_SNEB_SN,
- TILEPRO_OPC_SNEH_SN, TILEPRO_OPC_SNE_SN, TILEPRO_OPC_SRAB_SN,
- TILEPRO_OPC_SRAH_SN, TILEPRO_OPC_SRA_SN, TILEPRO_OPC_SUBB_SN,
- TILEPRO_OPC_SUBH_SN, TILEPRO_OPC_SUB_SN,
- BITFIELD(49, 4) /* index 722 */,
- CHILD(611), CHILD(739), CHILD(742), CHILD(745), CHILD(748), CHILD(751),
- CHILD(754), CHILD(757), CHILD(760), CHILD(763), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 739 */,
- TILEPRO_OPC_XOR_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 742 */,
- TILEPRO_OPC_ADDS_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 745 */,
- TILEPRO_OPC_SUBS_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 748 */,
- TILEPRO_OPC_ADDBS_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 751 */,
- TILEPRO_OPC_ADDHS_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 754 */,
- TILEPRO_OPC_SUBBS_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 757 */,
- TILEPRO_OPC_SUBHS_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 760 */,
- TILEPRO_OPC_PACKHS_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 763 */,
- TILEPRO_OPC_PACKBS_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(37, 2) /* index 766 */,
- TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN,
- CHILD(771),
- BITFIELD(39, 2) /* index 771 */,
- TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN,
- CHILD(776),
- BITFIELD(41, 2) /* index 776 */,
- TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN,
- TILEPRO_OPC_MOVELI_SN,
- BITFIELD(37, 2) /* index 781 */,
- TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(786),
- BITFIELD(39, 2) /* index 786 */,
- TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(791),
- BITFIELD(41, 2) /* index 791 */,
- TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_MOVELI,
- BITFIELD(31, 2) /* index 796 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(801),
- BITFIELD(33, 2) /* index 801 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(806),
- BITFIELD(35, 2) /* index 806 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(811),
- BITFIELD(37, 2) /* index 811 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(816),
- BITFIELD(39, 2) /* index 816 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(821),
- BITFIELD(41, 2) /* index 821 */,
- TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_INFOL,
- BITFIELD(31, 4) /* index 826 */,
- TILEPRO_OPC_BZ, TILEPRO_OPC_BZT, TILEPRO_OPC_BNZ, TILEPRO_OPC_BNZT,
- TILEPRO_OPC_BGZ, TILEPRO_OPC_BGZT, TILEPRO_OPC_BGEZ, TILEPRO_OPC_BGEZT,
- TILEPRO_OPC_BLZ, TILEPRO_OPC_BLZT, TILEPRO_OPC_BLEZ, TILEPRO_OPC_BLEZT,
- TILEPRO_OPC_BBS, TILEPRO_OPC_BBST, TILEPRO_OPC_BBNS, TILEPRO_OPC_BBNST,
- BITFIELD(31, 4) /* index 843 */,
- TILEPRO_OPC_BZ_SN, TILEPRO_OPC_BZT_SN, TILEPRO_OPC_BNZ_SN,
- TILEPRO_OPC_BNZT_SN, TILEPRO_OPC_BGZ_SN, TILEPRO_OPC_BGZT_SN,
- TILEPRO_OPC_BGEZ_SN, TILEPRO_OPC_BGEZT_SN, TILEPRO_OPC_BLZ_SN,
- TILEPRO_OPC_BLZT_SN, TILEPRO_OPC_BLEZ_SN, TILEPRO_OPC_BLEZT_SN,
- TILEPRO_OPC_BBS_SN, TILEPRO_OPC_BBST_SN, TILEPRO_OPC_BBNS_SN,
- TILEPRO_OPC_BBNST_SN,
- BITFIELD(51, 3) /* index 860 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB, TILEPRO_OPC_ADDIH, TILEPRO_OPC_ADDI,
- CHILD(869), TILEPRO_OPC_MAXIB_U, TILEPRO_OPC_MAXIH, TILEPRO_OPC_MFSPR,
- BITFIELD(31, 2) /* index 869 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(874),
- BITFIELD(33, 2) /* index 874 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(879),
- BITFIELD(35, 2) /* index 879 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(884),
- BITFIELD(37, 2) /* index 884 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(889),
- BITFIELD(39, 2) /* index 889 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(894),
- BITFIELD(41, 2) /* index 894 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO,
- BITFIELD(51, 3) /* index 899 */,
- TILEPRO_OPC_MINIB_U, TILEPRO_OPC_MINIH, TILEPRO_OPC_MTSPR, CHILD(908),
- TILEPRO_OPC_SEQIB, TILEPRO_OPC_SEQIH, TILEPRO_OPC_SEQI, TILEPRO_OPC_SLTIB,
- BITFIELD(37, 2) /* index 908 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(913),
- BITFIELD(39, 2) /* index 913 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(918),
- BITFIELD(41, 2) /* index 918 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI,
- BITFIELD(51, 3) /* index 923 */,
- TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH, TILEPRO_OPC_SLTIH_U,
- TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_XORI, TILEPRO_OPC_LBADD,
- TILEPRO_OPC_LBADD_U,
- BITFIELD(51, 3) /* index 932 */,
- TILEPRO_OPC_LHADD, TILEPRO_OPC_LHADD_U, TILEPRO_OPC_LWADD,
- TILEPRO_OPC_LWADD_NA, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD,
- TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE,
- BITFIELD(51, 3) /* index 941 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN,
- TILEPRO_OPC_ADDI_SN, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_MAXIB_U_SN,
- TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MFSPR,
- BITFIELD(51, 3) /* index 950 */,
- TILEPRO_OPC_MINIB_U_SN, TILEPRO_OPC_MINIH_SN, TILEPRO_OPC_MTSPR, CHILD(959),
- TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN,
- TILEPRO_OPC_SLTIB_SN,
- BITFIELD(37, 2) /* index 959 */,
- TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(964),
- BITFIELD(39, 2) /* index 964 */,
- TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(969),
- BITFIELD(41, 2) /* index 969 */,
- TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN,
- TILEPRO_OPC_MOVEI_SN,
- BITFIELD(51, 3) /* index 974 */,
- TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN, TILEPRO_OPC_SLTIH_U_SN,
- TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_XORI_SN,
- TILEPRO_OPC_LBADD_SN, TILEPRO_OPC_LBADD_U_SN,
- BITFIELD(51, 3) /* index 983 */,
- TILEPRO_OPC_LHADD_SN, TILEPRO_OPC_LHADD_U_SN, TILEPRO_OPC_LWADD_SN,
- TILEPRO_OPC_LWADD_NA_SN, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD,
- TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE,
- BITFIELD(46, 7) /* index 992 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1124),
- CHILD(1124), CHILD(1124), CHILD(1124), CHILD(1127), CHILD(1127),
- CHILD(1127), CHILD(1127), CHILD(1130), CHILD(1130), CHILD(1130),
- CHILD(1130), CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1133),
- CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1139),
- CHILD(1139), CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142),
- CHILD(1142), CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145),
- CHILD(1145), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148),
- CHILD(1151), CHILD(1242), CHILD(1290), CHILD(1323), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1121 */,
- TILEPRO_OPC_RLI, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1124 */,
- TILEPRO_OPC_SHLIB, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1127 */,
- TILEPRO_OPC_SHLIH, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1130 */,
- TILEPRO_OPC_SHLI, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1133 */,
- TILEPRO_OPC_SHRIB, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1136 */,
- TILEPRO_OPC_SHRIH, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1139 */,
- TILEPRO_OPC_SHRI, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1142 */,
- TILEPRO_OPC_SRAIB, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1145 */,
- TILEPRO_OPC_SRAIH, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1148 */,
- TILEPRO_OPC_SRAI, TILEPRO_OPC_NONE,
- BITFIELD(43, 3) /* index 1151 */,
- TILEPRO_OPC_NONE, CHILD(1160), CHILD(1163), CHILD(1166), CHILD(1169),
- CHILD(1172), CHILD(1175), CHILD(1178),
- BITFIELD(53, 1) /* index 1160 */,
- TILEPRO_OPC_DRAIN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1163 */,
- TILEPRO_OPC_DTLBPR, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1166 */,
- TILEPRO_OPC_FINV, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1169 */,
- TILEPRO_OPC_FLUSH, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1172 */,
- TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1175 */,
- TILEPRO_OPC_ICOH, TILEPRO_OPC_NONE,
- BITFIELD(31, 2) /* index 1178 */,
- CHILD(1183), CHILD(1211), CHILD(1239), CHILD(1239),
- BITFIELD(53, 1) /* index 1183 */,
- CHILD(1186), TILEPRO_OPC_NONE,
- BITFIELD(33, 2) /* index 1186 */,
- TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1191),
- BITFIELD(35, 2) /* index 1191 */,
- TILEPRO_OPC_ILL, CHILD(1196), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
- BITFIELD(37, 2) /* index 1196 */,
- TILEPRO_OPC_ILL, CHILD(1201), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
- BITFIELD(39, 2) /* index 1201 */,
- TILEPRO_OPC_ILL, CHILD(1206), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
- BITFIELD(41, 2) /* index 1206 */,
- TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_BPT, TILEPRO_OPC_ILL,
- BITFIELD(53, 1) /* index 1211 */,
- CHILD(1214), TILEPRO_OPC_NONE,
- BITFIELD(33, 2) /* index 1214 */,
- TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1219),
- BITFIELD(35, 2) /* index 1219 */,
- TILEPRO_OPC_ILL, CHILD(1224), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
- BITFIELD(37, 2) /* index 1224 */,
- TILEPRO_OPC_ILL, CHILD(1229), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
- BITFIELD(39, 2) /* index 1229 */,
- TILEPRO_OPC_ILL, CHILD(1234), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL,
- BITFIELD(41, 2) /* index 1234 */,
- TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_RAISE, TILEPRO_OPC_ILL,
- BITFIELD(53, 1) /* index 1239 */,
- TILEPRO_OPC_ILL, TILEPRO_OPC_NONE,
- BITFIELD(43, 3) /* index 1242 */,
- CHILD(1251), CHILD(1254), CHILD(1257), CHILD(1275), CHILD(1278),
- CHILD(1281), CHILD(1284), CHILD(1287),
- BITFIELD(53, 1) /* index 1251 */,
- TILEPRO_OPC_INV, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1254 */,
- TILEPRO_OPC_IRET, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1257 */,
- CHILD(1260), TILEPRO_OPC_NONE,
- BITFIELD(31, 2) /* index 1260 */,
- TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1265),
- BITFIELD(33, 2) /* index 1265 */,
- TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1270),
- BITFIELD(35, 2) /* index 1270 */,
- TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH,
- BITFIELD(53, 1) /* index 1275 */,
- TILEPRO_OPC_LB_U, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1278 */,
- TILEPRO_OPC_LH, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1281 */,
- TILEPRO_OPC_LH_U, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1284 */,
- TILEPRO_OPC_LW, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1287 */,
- TILEPRO_OPC_MF, TILEPRO_OPC_NONE,
- BITFIELD(43, 3) /* index 1290 */,
- CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311),
- CHILD(1314), CHILD(1317), CHILD(1320),
- BITFIELD(53, 1) /* index 1299 */,
- TILEPRO_OPC_NAP, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1302 */,
- TILEPRO_OPC_NOP, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1305 */,
- TILEPRO_OPC_SWINT0, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1308 */,
- TILEPRO_OPC_SWINT1, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1311 */,
- TILEPRO_OPC_SWINT2, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1314 */,
- TILEPRO_OPC_SWINT3, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1317 */,
- TILEPRO_OPC_TNS, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1320 */,
- TILEPRO_OPC_WH64, TILEPRO_OPC_NONE,
- BITFIELD(43, 2) /* index 1323 */,
- CHILD(1328), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(45, 1) /* index 1328 */,
- CHILD(1331), TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1331 */,
- TILEPRO_OPC_LW_NA, TILEPRO_OPC_NONE,
- BITFIELD(46, 7) /* index 1334 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1466),
- CHILD(1466), CHILD(1466), CHILD(1466), CHILD(1469), CHILD(1469),
- CHILD(1469), CHILD(1469), CHILD(1472), CHILD(1472), CHILD(1472),
- CHILD(1472), CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1475),
- CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1481),
- CHILD(1481), CHILD(1481), CHILD(1481), CHILD(1484), CHILD(1484),
- CHILD(1484), CHILD(1484), CHILD(1487), CHILD(1487), CHILD(1487),
- CHILD(1487), CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1490),
- CHILD(1151), CHILD(1493), CHILD(1517), CHILD(1529), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1463 */,
- TILEPRO_OPC_RLI_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1466 */,
- TILEPRO_OPC_SHLIB_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1469 */,
- TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1472 */,
- TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1475 */,
- TILEPRO_OPC_SHRIB_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1478 */,
- TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1481 */,
- TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1484 */,
- TILEPRO_OPC_SRAIB_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1487 */,
- TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1490 */,
- TILEPRO_OPC_SRAI_SN, TILEPRO_OPC_NONE,
- BITFIELD(43, 3) /* index 1493 */,
- CHILD(1251), CHILD(1254), CHILD(1502), CHILD(1505), CHILD(1508),
- CHILD(1511), CHILD(1514), CHILD(1287),
- BITFIELD(53, 1) /* index 1502 */,
- TILEPRO_OPC_LB_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1505 */,
- TILEPRO_OPC_LB_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1508 */,
- TILEPRO_OPC_LH_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1511 */,
- TILEPRO_OPC_LH_U_SN, TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1514 */,
- TILEPRO_OPC_LW_SN, TILEPRO_OPC_NONE,
- BITFIELD(43, 3) /* index 1517 */,
- CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311),
- CHILD(1314), CHILD(1526), CHILD(1320),
- BITFIELD(53, 1) /* index 1526 */,
- TILEPRO_OPC_TNS_SN, TILEPRO_OPC_NONE,
- BITFIELD(43, 2) /* index 1529 */,
- CHILD(1534), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(45, 1) /* index 1534 */,
- CHILD(1537), TILEPRO_OPC_NONE,
- BITFIELD(53, 1) /* index 1537 */,
- TILEPRO_OPC_LW_NA_SN, TILEPRO_OPC_NONE,
-};
-
-static const unsigned short decode_Y0_fsm[168] =
-{
- BITFIELD(27, 4) /* index 0 */,
- TILEPRO_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52),
- CHILD(57), CHILD(62), CHILD(67), TILEPRO_OPC_ADDI, CHILD(72), CHILD(102),
- TILEPRO_OPC_SEQI, CHILD(117), TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U,
- BITFIELD(18, 2) /* index 17 */,
- TILEPRO_OPC_ADD, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_SUB,
- BITFIELD(18, 2) /* index 22 */,
- TILEPRO_OPC_MNZ, TILEPRO_OPC_MVNZ, TILEPRO_OPC_MVZ, TILEPRO_OPC_MZ,
- BITFIELD(18, 2) /* index 27 */,
- TILEPRO_OPC_AND, TILEPRO_OPC_NOR, CHILD(32), TILEPRO_OPC_XOR,
- BITFIELD(12, 2) /* index 32 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(37),
- BITFIELD(14, 2) /* index 37 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(42),
- BITFIELD(16, 2) /* index 42 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE,
- BITFIELD(18, 2) /* index 47 */,
- TILEPRO_OPC_RL, TILEPRO_OPC_SHL, TILEPRO_OPC_SHR, TILEPRO_OPC_SRA,
- BITFIELD(18, 2) /* index 52 */,
- TILEPRO_OPC_SLTE, TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLT, TILEPRO_OPC_SLT_U,
- BITFIELD(18, 2) /* index 57 */,
- TILEPRO_OPC_MULHLSA_UU, TILEPRO_OPC_S3A, TILEPRO_OPC_SEQ, TILEPRO_OPC_SNE,
- BITFIELD(18, 2) /* index 62 */,
- TILEPRO_OPC_MULHH_SS, TILEPRO_OPC_MULHH_UU, TILEPRO_OPC_MULLL_SS,
- TILEPRO_OPC_MULLL_UU,
- BITFIELD(18, 2) /* index 67 */,
- TILEPRO_OPC_MULHHA_SS, TILEPRO_OPC_MULHHA_UU, TILEPRO_OPC_MULLLA_SS,
- TILEPRO_OPC_MULLLA_UU,
- BITFIELD(0, 2) /* index 72 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(77),
- BITFIELD(2, 2) /* index 77 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(82),
- BITFIELD(4, 2) /* index 82 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(87),
- BITFIELD(6, 2) /* index 87 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(92),
- BITFIELD(8, 2) /* index 92 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(97),
- BITFIELD(10, 2) /* index 97 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO,
- BITFIELD(6, 2) /* index 102 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(107),
- BITFIELD(8, 2) /* index 107 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(112),
- BITFIELD(10, 2) /* index 112 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI,
- BITFIELD(15, 5) /* index 117 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, TILEPRO_OPC_RLI,
- TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI,
- TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI,
- TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI,
- CHILD(150), CHILD(159), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(12, 3) /* index 150 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_BITX, TILEPRO_OPC_BYTEX, TILEPRO_OPC_CLZ,
- TILEPRO_OPC_CTZ, TILEPRO_OPC_FNOP, TILEPRO_OPC_NOP, TILEPRO_OPC_PCNT,
- BITFIELD(12, 3) /* index 159 */,
- TILEPRO_OPC_TBLIDXB0, TILEPRO_OPC_TBLIDXB1, TILEPRO_OPC_TBLIDXB2,
- TILEPRO_OPC_TBLIDXB3, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE,
-};
-
-static const unsigned short decode_Y1_fsm[140] =
-{
- BITFIELD(59, 4) /* index 0 */,
- TILEPRO_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52),
- CHILD(57), TILEPRO_OPC_ADDI, CHILD(62), CHILD(92), TILEPRO_OPC_SEQI,
- CHILD(107), TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE,
- BITFIELD(49, 2) /* index 17 */,
- TILEPRO_OPC_ADD, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_SUB,
- BITFIELD(49, 2) /* index 22 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_MNZ, TILEPRO_OPC_MZ, TILEPRO_OPC_NONE,
- BITFIELD(49, 2) /* index 27 */,
- TILEPRO_OPC_AND, TILEPRO_OPC_NOR, CHILD(32), TILEPRO_OPC_XOR,
- BITFIELD(43, 2) /* index 32 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(37),
- BITFIELD(45, 2) /* index 37 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(42),
- BITFIELD(47, 2) /* index 42 */,
- TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE,
- BITFIELD(49, 2) /* index 47 */,
- TILEPRO_OPC_RL, TILEPRO_OPC_SHL, TILEPRO_OPC_SHR, TILEPRO_OPC_SRA,
- BITFIELD(49, 2) /* index 52 */,
- TILEPRO_OPC_SLTE, TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLT, TILEPRO_OPC_SLT_U,
- BITFIELD(49, 2) /* index 57 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_S3A, TILEPRO_OPC_SEQ, TILEPRO_OPC_SNE,
- BITFIELD(31, 2) /* index 62 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(67),
- BITFIELD(33, 2) /* index 67 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(72),
- BITFIELD(35, 2) /* index 72 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(77),
- BITFIELD(37, 2) /* index 77 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(82),
- BITFIELD(39, 2) /* index 82 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(87),
- BITFIELD(41, 2) /* index 87 */,
- TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO,
- BITFIELD(37, 2) /* index 92 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(97),
- BITFIELD(39, 2) /* index 97 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(102),
- BITFIELD(41, 2) /* index 102 */,
- TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI,
- BITFIELD(48, 3) /* index 107 */,
- TILEPRO_OPC_NONE, TILEPRO_OPC_RLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHRI,
- TILEPRO_OPC_SRAI, CHILD(116), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(43, 3) /* index 116 */,
- TILEPRO_OPC_NONE, CHILD(125), CHILD(130), CHILD(135), TILEPRO_OPC_NONE,
- TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(46, 2) /* index 125 */,
- TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(46, 2) /* index 130 */,
- TILEPRO_OPC_ILL, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
- BITFIELD(46, 2) /* index 135 */,
- TILEPRO_OPC_NOP, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE,
-};
-
-static const unsigned short decode_Y2_fsm[24] =
-{
- BITFIELD(56, 3) /* index 0 */,
- CHILD(9), TILEPRO_OPC_LB_U, TILEPRO_OPC_LH, TILEPRO_OPC_LH_U,
- TILEPRO_OPC_LW, TILEPRO_OPC_SB, TILEPRO_OPC_SH, TILEPRO_OPC_SW,
- BITFIELD(20, 2) /* index 9 */,
- TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(14),
- BITFIELD(22, 2) /* index 14 */,
- TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(19),
- BITFIELD(24, 2) /* index 19 */,
- TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH,
-};
-
-#undef BITFIELD
-#undef CHILD
-const unsigned short * const
-tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS] =
-{
- decode_X0_fsm,
- decode_X1_fsm,
- decode_Y0_fsm,
- decode_Y1_fsm,
- decode_Y2_fsm
-};
-const struct tilepro_operand tilepro_operands[43] =
-{
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_X0),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_X0, get_Imm8_X0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_X1),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_X1, get_Imm8_X1
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_Y0),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_Y0, get_Imm8_Y0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_Y1),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_Y1, get_Imm8_Y1
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM16_X0),
- 16, 1, 0, 0, 0, 0,
- create_Imm16_X0, get_Imm16_X0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM16_X1),
- 16, 1, 0, 0, 0, 0,
- create_Imm16_X1, get_Imm16_X1
- },
- {
- TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(TILEPRO_JOFFLONG_X1),
- 29, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
- create_JOffLong_X1, get_JOffLong_X1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_X0, get_Dest_X0
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_X0, get_SrcA_X0
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_X1, get_Dest_X1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_X1, get_SrcA_X1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_Y0, get_Dest_Y0
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y0, get_SrcA_Y0
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_Y1, get_Dest_Y1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y1, get_SrcA_Y1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y2, get_SrcA_Y2
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_X0, get_SrcB_X0
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_X1, get_SrcB_X1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_Y0, get_SrcB_Y0
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_Y1, get_SrcB_Y1
- },
- {
- TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(TILEPRO_BROFF_X1),
- 17, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
- create_BrOff_X1, get_BrOff_X1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_Dest_X0, get_Dest_X0
- },
- {
- TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(NONE),
- 28, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
- create_JOff_X1, get_JOff_X1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_SrcBDest_Y2, get_SrcBDest_Y2
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_SrcA_X1, get_SrcA_X1
- },
- {
- TILEPRO_OP_TYPE_SPR, BFD_RELOC(TILEPRO_MF_IMM15_X1),
- 15, 0, 0, 0, 0, 0,
- create_MF_Imm15_X1, get_MF_Imm15_X1
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMSTART_X0),
- 5, 0, 0, 0, 0, 0,
- create_MMStart_X0, get_MMStart_X0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMEND_X0),
- 5, 0, 0, 0, 0, 0,
- create_MMEnd_X0, get_MMEnd_X0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMSTART_X1),
- 5, 0, 0, 0, 0, 0,
- create_MMStart_X1, get_MMStart_X1
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMEND_X1),
- 5, 0, 0, 0, 0, 0,
- create_MMEnd_X1, get_MMEnd_X1
- },
- {
- TILEPRO_OP_TYPE_SPR, BFD_RELOC(TILEPRO_MT_IMM15_X1),
- 15, 0, 0, 0, 0, 0,
- create_MT_Imm15_X1, get_MT_Imm15_X1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_Dest_Y0, get_Dest_Y0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_X0),
- 5, 0, 0, 0, 0, 0,
- create_ShAmt_X0, get_ShAmt_X0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_X1),
- 5, 0, 0, 0, 0, 0,
- create_ShAmt_X1, get_ShAmt_X1
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_Y0),
- 5, 0, 0, 0, 0, 0,
- create_ShAmt_Y0, get_ShAmt_Y0
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_Y1),
- 5, 0, 0, 0, 0, 0,
- create_ShAmt_Y1, get_ShAmt_Y1
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcBDest_Y2, get_SrcBDest_Y2
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_DEST_IMM8_X1),
- 8, 1, 0, 0, 0, 0,
- create_Dest_Imm8_X1, get_Dest_Imm8_X1
- },
- {
- TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(NONE),
- 10, 1, 0, 0, 1, TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES,
- create_BrOff_SN, get_BrOff_SN
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
- 8, 0, 0, 0, 0, 0,
- create_Imm8_SN, get_Imm8_SN
- },
- {
- TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_SN, get_Imm8_SN
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 2, 0, 0, 1, 0, 0,
- create_Dest_SN, get_Dest_SN
- },
- {
- TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 2, 0, 1, 0, 0, 0,
- create_Src_SN, get_Src_SN
- }
-};
-
-
-
-
-/* Given a set of bundle bits and a specific pipe, returns which
- * instruction the bundle contains in that pipe.
- */
-const struct tilepro_opcode *
-find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe)
-{
- const unsigned short *table = tilepro_bundle_decoder_fsms[pipe];
- int index = 0;
-
- while (1)
- {
- unsigned short bitspec = table[index];
- unsigned int bitfield =
- ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
-
- unsigned short next = table[index + 1 + bitfield];
- if (next <= TILEPRO_OPC_NONE)
- return &tilepro_opcodes[next];
-
- index = next - TILEPRO_OPC_NONE;
- }
-}
-
-
-int
-parse_insn_tilepro(tilepro_bundle_bits bits,
- unsigned int pc,
- struct tilepro_decoded_instruction
- decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE])
-{
- int num_instructions = 0;
- int pipe;
-
- int min_pipe, max_pipe;
- if ((bits & TILEPRO_BUNDLE_Y_ENCODING_MASK) == 0)
- {
- min_pipe = TILEPRO_PIPELINE_X0;
- max_pipe = TILEPRO_PIPELINE_X1;
- }
- else
- {
- min_pipe = TILEPRO_PIPELINE_Y0;
- max_pipe = TILEPRO_PIPELINE_Y2;
- }
-
- /* For each pipe, find an instruction that fits. */
- for (pipe = min_pipe; pipe <= max_pipe; pipe++)
- {
- const struct tilepro_opcode *opc;
- struct tilepro_decoded_instruction *d;
- int i;
-
- d = &decoded[num_instructions++];
- opc = find_opcode (bits, (tilepro_pipeline)pipe);
- d->opcode = opc;
-
- /* Decode each operand, sign extending, etc. as appropriate. */
- for (i = 0; i < opc->num_operands; i++)
- {
- const struct tilepro_operand *op =
- &tilepro_operands[opc->operands[pipe][i]];
- int opval = op->extract (bits);
- if (op->is_signed)
- {
- /* Sign-extend the operand. */
- int shift = (int)((sizeof(int) * 8) - op->num_bits);
- opval = (opval << shift) >> shift;
- }
-
- /* Adjust PC-relative scaled branch offsets. */
- if (op->type == TILEPRO_OP_TYPE_ADDRESS)
- {
- opval *= TILEPRO_BUNDLE_SIZE_IN_BYTES;
- opval += (int)pc;
- }
-
- /* Record the final value. */
- d->operands[i] = op;
- d->operand_values[i] = opval;
- }
- }
-
- return num_instructions;
-}
diff --git a/arch/tile/kernel/tile-desc_64.c b/arch/tile/kernel/tile-desc_64.c
deleted file mode 100644
index 65b5f8aca706..000000000000
--- a/arch/tile/kernel/tile-desc_64.c
+++ /dev/null
@@ -1,2218 +0,0 @@
-/* TILE-Gx opcode information.
- *
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- *
- *
- *
- *
- */
-
-/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
-#define BFD_RELOC(x) -1
-
-/* Special registers. */
-#define TREG_LR 55
-#define TREG_SN 56
-#define TREG_ZERO 63
-
-#include <linux/stddef.h>
-#include <asm/tile-desc.h>
-
-const struct tilegx_opcode tilegx_opcodes[334] =
-{
- { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
- { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
- },
- { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
- { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
- { { 6, 7 }, { 8, 9 }, { 10, 11 }, { 12, 13 }, { 0, } },
- },
- { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
- { { 6, 0 }, { 8, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
- },
- { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
- { { 6, 4 }, { 8, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
- },
- { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
- },
- { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
- },
- { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
- },
- { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
- },
- { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
- },
- { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
- },
- { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
- },
- { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
- },
- { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
- },
- { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
- { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
- { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
- { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
- },
- { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
- { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
- },
- { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
- },
- { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
- },
- { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
- },
- { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
- },
- { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
- { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
- },
- { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
- { { }, { }, { }, { }, { 0, } },
- },
- { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
- { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
- },
- { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { }, { 0, } },
- },
- { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
- },
- { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
- { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
- },
- { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
- { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
- },
- { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
- { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
- },
- { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
- },
- { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
- },
- { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
- },
- { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
- },
- { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
- },
- { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
- },
- { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
- },
- { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
- },
- { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
- },
- { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
- { { 0, }, { 8 }, { 0, }, { 12 }, { 0, } },
- },
- { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 8, 27 }, { 0, }, { 0, }, { 0, } },
- },
- { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
- { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 28, 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
- },
- { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
- },
- { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
- },
- { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
- },
- { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
- },
- { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
- },
- { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
- },
- { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
- },
- { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
- },
- { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
- },
- { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
- { { }, { }, { }, { }, { 0, } },
- },
- { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
- { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
- },
- { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
- { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
- },
- { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
- { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
- },
- { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
- },
- { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
- },
- { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
- },
- { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
- },
- { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
- },
- { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
- },
- { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
- },
- { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
- },
- { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
- },
- { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
- { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
- { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
- },
- { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
- { { 0, }, { }, { 0, }, { 0, }, { 0, } },
- },
- { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
- { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
- },
- { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
- { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
- },
- { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
- { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
- },
- { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
- { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
- },
- { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
- { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
- },
- { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
- },
- { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
- { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
- },
- { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
- { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
- },
- { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
- { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
- },
- { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
- }
-};
-#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
-#define CHILD(array_index) (TILEGX_OPC_NONE + (array_index))
-
-static const unsigned short decode_X0_fsm[936] =
-{
- BITFIELD(22, 9) /* index 0 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS,
- TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU,
- TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS,
- TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM,
- TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578),
- CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671),
- CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865),
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
- BITFIELD(6, 2) /* index 513 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
- BITFIELD(8, 2) /* index 518 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
- BITFIELD(10, 2) /* index 523 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
- BITFIELD(20, 2) /* index 528 */,
- TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
- BITFIELD(6, 2) /* index 533 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
- BITFIELD(8, 2) /* index 538 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
- BITFIELD(10, 2) /* index 543 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(0, 2) /* index 548 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
- BITFIELD(2, 2) /* index 553 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
- BITFIELD(4, 2) /* index 558 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
- BITFIELD(6, 2) /* index 563 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
- BITFIELD(8, 2) /* index 568 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
- BITFIELD(10, 2) /* index 573 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(20, 2) /* index 578 */,
- TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI,
- BITFIELD(20, 2) /* index 583 */,
- TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI,
- TILEGX_OPC_V1CMPLTUI,
- BITFIELD(20, 2) /* index 588 */,
- TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI,
- TILEGX_OPC_V2CMPEQI,
- BITFIELD(20, 2) /* index 593 */,
- TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI,
- TILEGX_OPC_V2MINSI,
- BITFIELD(20, 2) /* index 598 */,
- TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(18, 4) /* index 603 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
- TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR,
- BITFIELD(18, 4) /* index 620 */,
- TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL,
- TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2,
- TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN,
- TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS,
- TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1,
- TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS,
- BITFIELD(18, 4) /* index 637 */,
- TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN,
- TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2,
- TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2,
- TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX,
- TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS,
- TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS,
- BITFIELD(18, 4) /* index 654 */,
- TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU,
- TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS,
- TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU,
- TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU,
- TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU,
- TILEGX_OPC_MZ,
- BITFIELD(18, 4) /* index 671 */,
- TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
- TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES,
- TILEGX_OPC_SUBXSC,
- BITFIELD(12, 2) /* index 688 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693),
- BITFIELD(14, 2) /* index 693 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698),
- BITFIELD(16, 2) /* index 698 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(18, 4) /* index 703 */,
- TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU,
- TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA,
- BITFIELD(12, 4) /* index 720 */,
- TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757),
- CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787),
- CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 737 */,
- TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 742 */,
- TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 747 */,
- TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 752 */,
- TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 757 */,
- TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 762 */,
- TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 767 */,
- TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 772 */,
- TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 777 */,
- TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 782 */,
- TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 787 */,
- TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(16, 2) /* index 792 */,
- TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(18, 4) /* index 797 */,
- TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP,
- TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU,
- TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS,
- TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU,
- TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS,
- BITFIELD(18, 4) /* index 814 */,
- TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC,
- TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS,
- TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU,
- TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE,
- TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H,
- BITFIELD(18, 4) /* index 831 */,
- TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ,
- TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ,
- TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
- TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS,
- TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC,
- BITFIELD(18, 4) /* index 848 */,
- TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC,
- TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
- TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
- TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
- TILEGX_OPC_V4SUB,
- BITFIELD(18, 3) /* index 865 */,
- CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 874 */,
- TILEGX_OPC_XOR, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 877 */,
- TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 880 */,
- TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 883 */,
- TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE,
- BITFIELD(21, 1) /* index 886 */,
- TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE,
- BITFIELD(18, 4) /* index 889 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
- TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
- TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
- TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE,
- BITFIELD(0, 2) /* index 906 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(911),
- BITFIELD(2, 2) /* index 911 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(916),
- BITFIELD(4, 2) /* index 916 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(921),
- BITFIELD(6, 2) /* index 921 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(926),
- BITFIELD(8, 2) /* index 926 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(931),
- BITFIELD(10, 2) /* index 931 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- TILEGX_OPC_INFOL,
-};
-
-static const unsigned short decode_X1_fsm[1206] =
-{
- BITFIELD(53, 9) /* index 0 */,
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
- CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
- TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT,
- TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT,
- TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT,
- TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT,
- TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
- TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
- TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
- TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
- TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
- CHILD(598), CHILD(663), CHILD(683), CHILD(688), CHILD(693), CHILD(698),
- CHILD(703), CHILD(708), CHILD(713), CHILD(718), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
- TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
- CHILD(723), CHILD(740), CHILD(772), CHILD(789), CHILD(1108), CHILD(1125),
- CHILD(1142), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1159), TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
- CHILD(1176),
- BITFIELD(37, 2) /* index 513 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
- BITFIELD(39, 2) /* index 518 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
- BITFIELD(41, 2) /* index 523 */,
- TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
- BITFIELD(51, 2) /* index 528 */,
- TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
- BITFIELD(37, 2) /* index 533 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
- BITFIELD(39, 2) /* index 538 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
- BITFIELD(41, 2) /* index 543 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(31, 2) /* index 548 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
- BITFIELD(33, 2) /* index 553 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
- BITFIELD(35, 2) /* index 558 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
- BITFIELD(37, 2) /* index 563 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
- BITFIELD(39, 2) /* index 568 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
- BITFIELD(41, 2) /* index 573 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(51, 2) /* index 578 */,
- TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583),
- BITFIELD(31, 2) /* index 583 */,
- TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588),
- BITFIELD(33, 2) /* index 588 */,
- TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593),
- BITFIELD(35, 2) /* index 593 */,
- TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD,
- TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
- BITFIELD(51, 2) /* index 598 */,
- CHILD(603), CHILD(618), CHILD(633), CHILD(648),
- BITFIELD(31, 2) /* index 603 */,
- TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608),
- BITFIELD(33, 2) /* index 608 */,
- TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613),
- BITFIELD(35, 2) /* index 613 */,
- TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD,
- TILEGX_OPC_PREFETCH_ADD_L1,
- BITFIELD(31, 2) /* index 618 */,
- TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623),
- BITFIELD(33, 2) /* index 623 */,
- TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628),
- BITFIELD(35, 2) /* index 628 */,
- TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD,
- TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
- BITFIELD(31, 2) /* index 633 */,
- TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638),
- BITFIELD(33, 2) /* index 638 */,
- TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
- BITFIELD(35, 2) /* index 643 */,
- TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
- TILEGX_OPC_PREFETCH_ADD_L2,
- BITFIELD(31, 2) /* index 648 */,
- TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(653),
- BITFIELD(33, 2) /* index 653 */,
- TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(658),
- BITFIELD(35, 2) /* index 658 */,
- TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
- TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
- BITFIELD(51, 2) /* index 663 */,
- CHILD(668), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
- TILEGX_OPC_LDNT2S_ADD,
- BITFIELD(31, 2) /* index 668 */,
- TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(673),
- BITFIELD(33, 2) /* index 673 */,
- TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(678),
- BITFIELD(35, 2) /* index 678 */,
- TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
- TILEGX_OPC_PREFETCH_ADD_L3,
- BITFIELD(51, 2) /* index 683 */,
- TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
- TILEGX_OPC_LDNT_ADD,
- BITFIELD(51, 2) /* index 688 */,
- TILEGX_OPC_LD_ADD, TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
- BITFIELD(51, 2) /* index 693 */,
- TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
- BITFIELD(51, 2) /* index 698 */,
- TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
- TILEGX_OPC_STNT_ADD,
- BITFIELD(51, 2) /* index 703 */,
- TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
- TILEGX_OPC_V1CMPLTSI,
- BITFIELD(51, 2) /* index 708 */,
- TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
- TILEGX_OPC_V2ADDI,
- BITFIELD(51, 2) /* index 713 */,
- TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
- TILEGX_OPC_V2MAXSI,
- BITFIELD(51, 2) /* index 718 */,
- TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(49, 4) /* index 723 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
- TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
- TILEGX_OPC_DBLALIGN6,
- BITFIELD(49, 4) /* index 740 */,
- TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
- TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
- TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
- TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
- CHILD(757), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
- BITFIELD(43, 2) /* index 757 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(762),
- BITFIELD(45, 2) /* index 762 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(767),
- BITFIELD(47, 2) /* index 767 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(49, 4) /* index 772 */,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
- TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
- TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
- TILEGX_OPC_STNT4,
- BITFIELD(46, 7) /* index 789 */,
- TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
- TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
- TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
- TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
- TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
- TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
- TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
- TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
- TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
- TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(918), CHILD(927),
- CHILD(1006), CHILD(1090), CHILD(1099), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
- TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
- TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
- TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
- TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
- TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
- TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
- TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
- TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
- TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
- TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
- TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
- TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
- TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
- TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
- BITFIELD(43, 3) /* index 918 */,
- TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
- TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
- BITFIELD(43, 3) /* index 927 */,
- CHILD(936), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
- TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(991),
- BITFIELD(31, 2) /* index 936 */,
- CHILD(941), CHILD(966), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(33, 2) /* index 941 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(946),
- BITFIELD(35, 2) /* index 946 */,
- TILEGX_OPC_ILL, CHILD(951), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(37, 2) /* index 951 */,
- TILEGX_OPC_ILL, CHILD(956), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(39, 2) /* index 956 */,
- TILEGX_OPC_ILL, CHILD(961), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(41, 2) /* index 961 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
- BITFIELD(33, 2) /* index 966 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(971),
- BITFIELD(35, 2) /* index 971 */,
- TILEGX_OPC_ILL, CHILD(976), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(37, 2) /* index 976 */,
- TILEGX_OPC_ILL, CHILD(981), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(39, 2) /* index 981 */,
- TILEGX_OPC_ILL, CHILD(986), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
- BITFIELD(41, 2) /* index 986 */,
- TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
- BITFIELD(31, 2) /* index 991 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(996),
- BITFIELD(33, 2) /* index 996 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1001),
- BITFIELD(35, 2) /* index 1001 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
- TILEGX_OPC_PREFETCH_L1_FAULT,
- BITFIELD(43, 3) /* index 1006 */,
- CHILD(1015), CHILD(1030), CHILD(1045), CHILD(1060), CHILD(1075),
- TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
- BITFIELD(31, 2) /* index 1015 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1020),
- BITFIELD(33, 2) /* index 1020 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1025),
- BITFIELD(35, 2) /* index 1025 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
- BITFIELD(31, 2) /* index 1030 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1035),
- BITFIELD(33, 2) /* index 1035 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1040),
- BITFIELD(35, 2) /* index 1040 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
- TILEGX_OPC_PREFETCH_L2_FAULT,
- BITFIELD(31, 2) /* index 1045 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1050),
- BITFIELD(33, 2) /* index 1050 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1055),
- BITFIELD(35, 2) /* index 1055 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
- BITFIELD(31, 2) /* index 1060 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1065),
- BITFIELD(33, 2) /* index 1065 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1070),
- BITFIELD(35, 2) /* index 1070 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
- TILEGX_OPC_PREFETCH_L3_FAULT,
- BITFIELD(31, 2) /* index 1075 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1080),
- BITFIELD(33, 2) /* index 1080 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1085),
- BITFIELD(35, 2) /* index 1085 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
- BITFIELD(43, 3) /* index 1090 */,
- TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
- TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
- BITFIELD(43, 3) /* index 1099 */,
- TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
- TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
- BITFIELD(49, 4) /* index 1108 */,
- TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
- TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
- TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
- TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
- TILEGX_OPC_V2CMPLTU,
- BITFIELD(49, 4) /* index 1125 */,
- TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
- TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
- TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
- TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
- TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
- BITFIELD(49, 4) /* index 1142 */,
- TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
- TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
- TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
- TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(49, 4) /* index 1159 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
- TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
- TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
- TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE,
- BITFIELD(31, 2) /* index 1176 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1181),
- BITFIELD(33, 2) /* index 1181 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1186),
- BITFIELD(35, 2) /* index 1186 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1191),
- BITFIELD(37, 2) /* index 1191 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1196),
- BITFIELD(39, 2) /* index 1196 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- CHILD(1201),
- BITFIELD(41, 2) /* index 1201 */,
- TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
- TILEGX_OPC_INFOL,
-};
-
-static const unsigned short decode_Y0_fsm[178] =
-{
- BITFIELD(27, 4) /* index 0 */,
- CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
- TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123),
- CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168),
- CHILD(173),
- BITFIELD(6, 2) /* index 17 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
- BITFIELD(8, 2) /* index 22 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
- BITFIELD(10, 2) /* index 27 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(0, 2) /* index 32 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
- BITFIELD(2, 2) /* index 37 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
- BITFIELD(4, 2) /* index 42 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
- BITFIELD(6, 2) /* index 47 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
- BITFIELD(8, 2) /* index 52 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
- BITFIELD(10, 2) /* index 57 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(18, 2) /* index 62 */,
- TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
- BITFIELD(15, 5) /* index 67 */,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100),
- CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(12, 3) /* index 100 */,
- TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP,
- TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT,
- TILEGX_OPC_REVBITS,
- BITFIELD(12, 3) /* index 109 */,
- TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1,
- TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- TILEGX_OPC_NONE,
- BITFIELD(18, 2) /* index 118 */,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- BITFIELD(18, 2) /* index 123 */,
- TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX,
- BITFIELD(18, 2) /* index 128 */,
- TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
- BITFIELD(18, 2) /* index 133 */,
- TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR,
- BITFIELD(12, 2) /* index 138 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143),
- BITFIELD(14, 2) /* index 143 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148),
- BITFIELD(16, 2) /* index 148 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(18, 2) /* index 153 */,
- TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
- BITFIELD(18, 2) /* index 158 */,
- TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
- TILEGX_OPC_SHL3ADDX,
- BITFIELD(18, 2) /* index 163 */,
- TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS,
- TILEGX_OPC_MUL_LU_LU,
- BITFIELD(18, 2) /* index 168 */,
- TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS,
- TILEGX_OPC_MULA_LU_LU,
- BITFIELD(18, 2) /* index 173 */,
- TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
-};
-
-static const unsigned short decode_Y1_fsm[167] =
-{
- BITFIELD(58, 4) /* index 0 */,
- TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
- TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122),
- CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE,
- BITFIELD(37, 2) /* index 17 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
- BITFIELD(39, 2) /* index 22 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
- BITFIELD(41, 2) /* index 27 */,
- TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
- BITFIELD(31, 2) /* index 32 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
- BITFIELD(33, 2) /* index 37 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
- BITFIELD(35, 2) /* index 42 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
- BITFIELD(37, 2) /* index 47 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
- BITFIELD(39, 2) /* index 52 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
- BITFIELD(41, 2) /* index 57 */,
- TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
- BITFIELD(49, 2) /* index 62 */,
- TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
- BITFIELD(47, 4) /* index 67 */,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
- TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
- TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD,
- TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84),
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
- BITFIELD(43, 3) /* index 84 */,
- CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108),
- CHILD(111), CHILD(114),
- BITFIELD(46, 1) /* index 93 */,
- TILEGX_OPC_NONE, TILEGX_OPC_FNOP,
- BITFIELD(46, 1) /* index 96 */,
- TILEGX_OPC_NONE, TILEGX_OPC_ILL,
- BITFIELD(46, 1) /* index 99 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JALRP,
- BITFIELD(46, 1) /* index 102 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JALR,
- BITFIELD(46, 1) /* index 105 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JRP,
- BITFIELD(46, 1) /* index 108 */,
- TILEGX_OPC_NONE, TILEGX_OPC_JR,
- BITFIELD(46, 1) /* index 111 */,
- TILEGX_OPC_NONE, TILEGX_OPC_LNK,
- BITFIELD(46, 1) /* index 114 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NOP,
- BITFIELD(49, 2) /* index 117 */,
- TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
- BITFIELD(49, 2) /* index 122 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE,
- BITFIELD(49, 2) /* index 127 */,
- TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
- BITFIELD(49, 2) /* index 132 */,
- TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR,
- BITFIELD(43, 2) /* index 137 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142),
- BITFIELD(45, 2) /* index 142 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147),
- BITFIELD(47, 2) /* index 147 */,
- TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
- BITFIELD(49, 2) /* index 152 */,
- TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
- BITFIELD(49, 2) /* index 157 */,
- TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
- TILEGX_OPC_SHL3ADDX,
- BITFIELD(49, 2) /* index 162 */,
- TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
-};
-
-static const unsigned short decode_Y2_fsm[118] =
-{
- BITFIELD(62, 2) /* index 0 */,
- TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109),
- BITFIELD(55, 3) /* index 5 */,
- CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40),
- CHILD(43),
- BITFIELD(26, 1) /* index 14 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1U,
- BITFIELD(26, 1) /* index 17 */,
- CHILD(20), CHILD(30),
- BITFIELD(51, 2) /* index 20 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25),
- BITFIELD(53, 2) /* index 25 */,
- TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
- TILEGX_OPC_PREFETCH_L1_FAULT,
- BITFIELD(51, 2) /* index 30 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35),
- BITFIELD(53, 2) /* index 35 */,
- TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
- BITFIELD(26, 1) /* index 40 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2U,
- BITFIELD(26, 1) /* index 43 */,
- CHILD(46), CHILD(56),
- BITFIELD(51, 2) /* index 46 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51),
- BITFIELD(53, 2) /* index 51 */,
- TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
- TILEGX_OPC_PREFETCH_L2_FAULT,
- BITFIELD(51, 2) /* index 56 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61),
- BITFIELD(53, 2) /* index 61 */,
- TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
- BITFIELD(56, 2) /* index 66 */,
- CHILD(71), CHILD(74), CHILD(90), CHILD(93),
- BITFIELD(26, 1) /* index 71 */,
- TILEGX_OPC_NONE, TILEGX_OPC_LD4S,
- BITFIELD(26, 1) /* index 74 */,
- TILEGX_OPC_NONE, CHILD(77),
- BITFIELD(51, 2) /* index 77 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82),
- BITFIELD(53, 2) /* index 82 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87),
- BITFIELD(55, 1) /* index 87 */,
- TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT,
- BITFIELD(26, 1) /* index 90 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD,
- BITFIELD(26, 1) /* index 93 */,
- CHILD(96), TILEGX_OPC_LD,
- BITFIELD(51, 2) /* index 96 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101),
- BITFIELD(53, 2) /* index 101 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106),
- BITFIELD(55, 1) /* index 106 */,
- TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
- BITFIELD(26, 1) /* index 109 */,
- CHILD(112), CHILD(115),
- BITFIELD(57, 1) /* index 112 */,
- TILEGX_OPC_ST1, TILEGX_OPC_ST4,
- BITFIELD(57, 1) /* index 115 */,
- TILEGX_OPC_ST2, TILEGX_OPC_ST,
-};
-
-#undef BITFIELD
-#undef CHILD
-const unsigned short * const
-tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] =
-{
- decode_X0_fsm,
- decode_X1_fsm,
- decode_Y0_fsm,
- decode_Y1_fsm,
- decode_Y2_fsm
-};
-const struct tilegx_operand tilegx_operands[35] =
-{
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_X0, get_Imm8_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_X1, get_Imm8_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_Y0, get_Imm8_Y0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1),
- 8, 1, 0, 0, 0, 0,
- create_Imm8_Y1, get_Imm8_Y1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST),
- 16, 1, 0, 0, 0, 0,
- create_Imm16_X0, get_Imm16_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST),
- 16, 1, 0, 0, 0, 0,
- create_Imm16_X1, get_Imm16_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_X0, get_Dest_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_X0, get_SrcA_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_X1, get_Dest_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_X1, get_SrcA_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_Y0, get_Dest_Y0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y0, get_SrcA_Y0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_Dest_Y1, get_Dest_Y1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y1, get_SrcA_Y1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcA_Y2, get_SrcA_Y2
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_SrcA_X1, get_SrcA_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_X0, get_SrcB_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_X1, get_SrcB_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_Y0, get_SrcB_Y0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcB_Y1, get_SrcB_Y1
- },
- {
- TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1),
- 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
- create_BrOff_X1, get_BrOff_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0),
- 6, 0, 0, 0, 0, 0,
- create_BFStart_X0, get_BFStart_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0),
- 6, 0, 0, 0, 0, 0,
- create_BFEnd_X0, get_BFEnd_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_Dest_X0, get_Dest_X0
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 1, 0, 0,
- create_Dest_Y0, get_Dest_Y0
- },
- {
- TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1),
- 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
- create_JumpOff_X1, get_JumpOff_X1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 0, 1, 0, 0,
- create_SrcBDest_Y2, get_SrcBDest_Y2
- },
- {
- TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1),
- 14, 0, 0, 0, 0, 0,
- create_MF_Imm14_X1, get_MF_Imm14_X1
- },
- {
- TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1),
- 14, 0, 0, 0, 0, 0,
- create_MT_Imm14_X1, get_MT_Imm14_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_X0, get_ShAmt_X0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_X1, get_ShAmt_X1
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_Y0, get_ShAmt_Y0
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1),
- 6, 0, 0, 0, 0, 0,
- create_ShAmt_Y1, get_ShAmt_Y1
- },
- {
- TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
- 6, 0, 1, 0, 0, 0,
- create_SrcBDest_Y2, get_SrcBDest_Y2
- },
- {
- TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1),
- 8, 1, 0, 0, 0, 0,
- create_Dest_Imm8_X1, get_Dest_Imm8_X1
- }
-};
-
-
-
-
-/* Given a set of bundle bits and the lookup FSM for a specific pipe,
- * returns which instruction the bundle contains in that pipe.
- */
-static const struct tilegx_opcode *
-find_opcode(tilegx_bundle_bits bits, const unsigned short *table)
-{
- int index = 0;
-
- while (1)
- {
- unsigned short bitspec = table[index];
- unsigned int bitfield =
- ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
-
- unsigned short next = table[index + 1 + bitfield];
- if (next <= TILEGX_OPC_NONE)
- return &tilegx_opcodes[next];
-
- index = next - TILEGX_OPC_NONE;
- }
-}
-
-
-int
-parse_insn_tilegx(tilegx_bundle_bits bits,
- unsigned long long pc,
- struct tilegx_decoded_instruction
- decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE])
-{
- int num_instructions = 0;
- int pipe;
-
- int min_pipe, max_pipe;
- if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0)
- {
- min_pipe = TILEGX_PIPELINE_X0;
- max_pipe = TILEGX_PIPELINE_X1;
- }
- else
- {
- min_pipe = TILEGX_PIPELINE_Y0;
- max_pipe = TILEGX_PIPELINE_Y2;
- }
-
- /* For each pipe, find an instruction that fits. */
- for (pipe = min_pipe; pipe <= max_pipe; pipe++)
- {
- const struct tilegx_opcode *opc;
- struct tilegx_decoded_instruction *d;
- int i;
-
- d = &decoded[num_instructions++];
- opc = find_opcode (bits, tilegx_bundle_decoder_fsms[pipe]);
- d->opcode = opc;
-
- /* Decode each operand, sign extending, etc. as appropriate. */
- for (i = 0; i < opc->num_operands; i++)
- {
- const struct tilegx_operand *op =
- &tilegx_operands[opc->operands[pipe][i]];
- int raw_opval = op->extract (bits);
- long long opval;
-
- if (op->is_signed)
- {
- /* Sign-extend the operand. */
- int shift = (int)((sizeof(int) * 8) - op->num_bits);
- raw_opval = (raw_opval << shift) >> shift;
- }
-
- /* Adjust PC-relative scaled branch offsets. */
- if (op->type == TILEGX_OP_TYPE_ADDRESS)
- opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc;
- else
- opval = raw_opval;
-
- /* Record the final value. */
- d->operands[i] = op;
- d->operand_values[i] = opval;
- }
- }
-
- return num_instructions;
-}
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
deleted file mode 100644
index f95d65f3162b..000000000000
--- a/arch/tile/kernel/time.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Support the cycle counter clocksource and tile timer clock event device.
- */
-
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/hardirq.h>
-#include <linux/sched.h>
-#include <linux/sched/clock.h>
-#include <linux/smp.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/timekeeper_internal.h>
-#include <asm/irq_regs.h>
-#include <asm/traps.h>
-#include <asm/vdso.h>
-#include <hv/hypervisor.h>
-#include <arch/interrupts.h>
-#include <arch/spr_def.h>
-
-
-/*
- * Define the cycle counter clock source.
- */
-
-/* How many cycles per second we are running at. */
-static cycles_t cycles_per_sec __ro_after_init;
-
-cycles_t get_clock_rate(void)
-{
- return cycles_per_sec;
-}
-
-#if CHIP_HAS_SPLIT_CYCLE()
-cycles_t get_cycles(void)
-{
- unsigned int high = __insn_mfspr(SPR_CYCLE_HIGH);
- unsigned int low = __insn_mfspr(SPR_CYCLE_LOW);
- unsigned int high2 = __insn_mfspr(SPR_CYCLE_HIGH);
-
- while (unlikely(high != high2)) {
- low = __insn_mfspr(SPR_CYCLE_LOW);
- high = high2;
- high2 = __insn_mfspr(SPR_CYCLE_HIGH);
- }
-
- return (((cycles_t)high) << 32) | low;
-}
-EXPORT_SYMBOL(get_cycles);
-#endif
-
-/*
- * We use a relatively small shift value so that sched_clock()
- * won't wrap around very often.
- */
-#define SCHED_CLOCK_SHIFT 10
-
-static unsigned long sched_clock_mult __ro_after_init;
-
-static cycles_t clocksource_get_cycles(struct clocksource *cs)
-{
- return get_cycles();
-}
-
-static struct clocksource cycle_counter_cs = {
- .name = "cycle counter",
- .rating = 300,
- .read = clocksource_get_cycles,
- .mask = CLOCKSOURCE_MASK(64),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-/*
- * Called very early from setup_arch() to set cycles_per_sec.
- * We initialize it early so we can use it to set up loops_per_jiffy.
- */
-void __init setup_clock(void)
-{
- cycles_per_sec = hv_sysconf(HV_SYSCONF_CPU_SPEED);
- sched_clock_mult =
- clocksource_hz2mult(cycles_per_sec, SCHED_CLOCK_SHIFT);
-}
-
-void __init calibrate_delay(void)
-{
- loops_per_jiffy = get_clock_rate() / HZ;
- pr_info("Clock rate yields %lu.%02lu BogoMIPS (lpj=%lu)\n",
- loops_per_jiffy / (500000 / HZ),
- (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy);
-}
-
-/* Called fairly late in init/main.c, but before we go smp. */
-void __init time_init(void)
-{
- /* Initialize and register the clock source. */
- clocksource_register_hz(&cycle_counter_cs, cycles_per_sec);
-
- /* Start up the tile-timer interrupt source on the boot cpu. */
- setup_tile_timer();
-}
-
-/*
- * Define the tile timer clock event device. The timer is driven by
- * the TILE_TIMER_CONTROL register, which consists of a 31-bit down
- * counter, plus bit 31, which signifies that the counter has wrapped
- * from zero to (2**31) - 1. The INT_TILE_TIMER interrupt will be
- * raised as long as bit 31 is set.
- *
- * The TILE_MINSEC value represents the largest range of real-time
- * we can possibly cover with the timer, based on MAX_TICK combined
- * with the slowest reasonable clock rate we might run at.
- */
-
-#define MAX_TICK 0x7fffffff /* we have 31 bits of countdown timer */
-#define TILE_MINSEC 5 /* timer covers no more than 5 seconds */
-
-static int tile_timer_set_next_event(unsigned long ticks,
- struct clock_event_device *evt)
-{
- BUG_ON(ticks > MAX_TICK);
- __insn_mtspr(SPR_TILE_TIMER_CONTROL, ticks);
- arch_local_irq_unmask_now(INT_TILE_TIMER);
- return 0;
-}
-
-/*
- * Whenever anyone tries to change modes, we just mask interrupts
- * and wait for the next event to get set.
- */
-static int tile_timer_shutdown(struct clock_event_device *evt)
-{
- arch_local_irq_mask_now(INT_TILE_TIMER);
- return 0;
-}
-
-/*
- * Set min_delta_ns to 1 microsecond, since it takes about
- * that long to fire the interrupt.
- */
-static DEFINE_PER_CPU(struct clock_event_device, tile_timer) = {
- .name = "tile timer",
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .min_delta_ns = 1000,
- .min_delta_ticks = 1,
- .max_delta_ticks = MAX_TICK,
- .rating = 100,
- .irq = -1,
- .set_next_event = tile_timer_set_next_event,
- .set_state_shutdown = tile_timer_shutdown,
- .set_state_oneshot = tile_timer_shutdown,
- .set_state_oneshot_stopped = tile_timer_shutdown,
- .tick_resume = tile_timer_shutdown,
-};
-
-void setup_tile_timer(void)
-{
- struct clock_event_device *evt = this_cpu_ptr(&tile_timer);
-
- /* Fill in fields that are speed-specific. */
- clockevents_calc_mult_shift(evt, cycles_per_sec, TILE_MINSEC);
- evt->max_delta_ns = clockevent_delta2ns(MAX_TICK, evt);
-
- /* Mark as being for this cpu only. */
- evt->cpumask = cpumask_of(smp_processor_id());
-
- /* Start out with timer not firing. */
- arch_local_irq_mask_now(INT_TILE_TIMER);
-
- /* Register tile timer. */
- clockevents_register_device(evt);
-}
-
-/* Called from the interrupt vector. */
-void do_timer_interrupt(struct pt_regs *regs, int fault_num)
-{
- struct pt_regs *old_regs = set_irq_regs(regs);
- struct clock_event_device *evt = this_cpu_ptr(&tile_timer);
-
- /*
- * Mask the timer interrupt here, since we are a oneshot timer
- * and there are now by definition no events pending.
- */
- arch_local_irq_mask(INT_TILE_TIMER);
-
- /* Track time spent here in an interrupt context */
- irq_enter();
-
- /* Track interrupt count. */
- __this_cpu_inc(irq_stat.irq_timer_count);
-
- /* Call the generic timer handler */
- evt->event_handler(evt);
-
- /*
- * Track time spent against the current process again and
- * process any softirqs if they are waiting.
- */
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-/*
- * Scheduler clock - returns current time in nanosec units.
- * Note that with LOCKDEP, this is called during lockdep_init(), and
- * we will claim that sched_clock() is zero for a little while, until
- * we run setup_clock(), above.
- */
-unsigned long long sched_clock(void)
-{
- return mult_frac(get_cycles(),
- sched_clock_mult, 1ULL << SCHED_CLOCK_SHIFT);
-}
-
-int setup_profiling_timer(unsigned int multiplier)
-{
- return -EINVAL;
-}
-
-/*
- * Use the tile timer to convert nsecs to core clock cycles, relying
- * on it having the same frequency as SPR_CYCLE.
- */
-cycles_t ns2cycles(unsigned long nsecs)
-{
- /*
- * We do not have to disable preemption here as each core has the same
- * clock frequency.
- */
- struct clock_event_device *dev = raw_cpu_ptr(&tile_timer);
-
- /*
- * as in clocksource.h and x86's timer.h, we split the calculation
- * into 2 parts to avoid unecessary overflow of the intermediate
- * value. This will not lead to any loss of precision.
- */
- u64 quot = (u64)nsecs >> dev->shift;
- u64 rem = (u64)nsecs & ((1ULL << dev->shift) - 1);
- return quot * dev->mult + ((rem * dev->mult) >> dev->shift);
-}
-
-void update_vsyscall_tz(void)
-{
- write_seqcount_begin(&vdso_data->tz_seq);
- vdso_data->tz_minuteswest = sys_tz.tz_minuteswest;
- vdso_data->tz_dsttime = sys_tz.tz_dsttime;
- write_seqcount_end(&vdso_data->tz_seq);
-}
-
-void update_vsyscall(struct timekeeper *tk)
-{
- if (tk->tkr_mono.clock != &cycle_counter_cs)
- return;
-
- write_seqcount_begin(&vdso_data->tb_seq);
-
- vdso_data->cycle_last = tk->tkr_mono.cycle_last;
- vdso_data->mask = tk->tkr_mono.mask;
- vdso_data->mult = tk->tkr_mono.mult;
- vdso_data->shift = tk->tkr_mono.shift;
-
- vdso_data->wall_time_sec = tk->xtime_sec;
- vdso_data->wall_time_snsec = tk->tkr_mono.xtime_nsec;
-
- vdso_data->monotonic_time_sec = tk->xtime_sec
- + tk->wall_to_monotonic.tv_sec;
- vdso_data->monotonic_time_snsec = tk->tkr_mono.xtime_nsec
- + ((u64)tk->wall_to_monotonic.tv_nsec
- << tk->tkr_mono.shift);
- while (vdso_data->monotonic_time_snsec >=
- (((u64)NSEC_PER_SEC) << tk->tkr_mono.shift)) {
- vdso_data->monotonic_time_snsec -=
- ((u64)NSEC_PER_SEC) << tk->tkr_mono.shift;
- vdso_data->monotonic_time_sec++;
- }
-
- vdso_data->wall_time_coarse_sec = tk->xtime_sec;
- vdso_data->wall_time_coarse_nsec = (long)(tk->tkr_mono.xtime_nsec >>
- tk->tkr_mono.shift);
-
- vdso_data->monotonic_time_coarse_sec =
- vdso_data->wall_time_coarse_sec + tk->wall_to_monotonic.tv_sec;
- vdso_data->monotonic_time_coarse_nsec =
- vdso_data->wall_time_coarse_nsec + tk->wall_to_monotonic.tv_nsec;
-
- while (vdso_data->monotonic_time_coarse_nsec >= NSEC_PER_SEC) {
- vdso_data->monotonic_time_coarse_nsec -= NSEC_PER_SEC;
- vdso_data->monotonic_time_coarse_sec++;
- }
-
- write_seqcount_end(&vdso_data->tb_seq);
-}
diff --git a/arch/tile/kernel/tlb.c b/arch/tile/kernel/tlb.c
deleted file mode 100644
index f23b53515671..000000000000
--- a/arch/tile/kernel/tlb.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/cpumask.h>
-#include <linux/module.h>
-#include <linux/hugetlb.h>
-#include <asm/tlbflush.h>
-#include <asm/homecache.h>
-#include <hv/hypervisor.h>
-
-/* From tlbflush.h */
-DEFINE_PER_CPU(int, current_asid);
-int min_asid, max_asid;
-
-/*
- * Note that we flush the L1I (for VM_EXEC pages) as well as the TLB
- * so that when we are unmapping an executable page, we also flush it.
- * Combined with flushing the L1I at context switch time, this means
- * we don't have to do any other icache flushes.
- */
-
-void flush_tlb_mm(struct mm_struct *mm)
-{
- HV_Remote_ASID asids[NR_CPUS];
- int i = 0, cpu;
- for_each_cpu(cpu, mm_cpumask(mm)) {
- HV_Remote_ASID *asid = &asids[i++];
- asid->y = cpu / smp_topology.width;
- asid->x = cpu % smp_topology.width;
- asid->asid = per_cpu(current_asid, cpu);
- }
- flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(mm),
- 0, 0, 0, NULL, asids, i);
-}
-
-void flush_tlb_current_task(void)
-{
- flush_tlb_mm(current->mm);
-}
-
-void flush_tlb_page_mm(struct vm_area_struct *vma, struct mm_struct *mm,
- unsigned long va)
-{
- unsigned long size = vma_kernel_pagesize(vma);
- int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
- flush_remote(0, cache, mm_cpumask(mm),
- va, size, size, mm_cpumask(mm), NULL, 0);
-}
-
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
-{
- flush_tlb_page_mm(vma, vma->vm_mm, va);
-}
-EXPORT_SYMBOL(flush_tlb_page);
-
-void flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
-{
- unsigned long size = vma_kernel_pagesize(vma);
- struct mm_struct *mm = vma->vm_mm;
- int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
- flush_remote(0, cache, mm_cpumask(mm), start, end - start, size,
- mm_cpumask(mm), NULL, 0);
-}
-
-void flush_tlb_all(void)
-{
- int i;
- for (i = 0; ; ++i) {
- HV_VirtAddrRange r = hv_inquire_virtual(i);
- if (r.size == 0)
- break;
- flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
- r.start, r.size, PAGE_SIZE, cpu_online_mask,
- NULL, 0);
- flush_remote(0, 0, NULL,
- r.start, r.size, HPAGE_SIZE, cpu_online_mask,
- NULL, 0);
- }
-}
-
-/*
- * Callers need to flush the L1I themselves if necessary, e.g. for
- * kernel module unload. Otherwise we assume callers are not using
- * executable pgprot_t's. Using EVICT_L1I means that dataplane cpus
- * will get an unnecessary interrupt otherwise.
- */
-void flush_tlb_kernel_range(unsigned long start, unsigned long end)
-{
- flush_remote(0, 0, NULL,
- start, end - start, PAGE_SIZE, cpu_online_mask, NULL, 0);
-}
diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c
deleted file mode 100644
index 83a7186198d7..000000000000
--- a/arch/tile/kernel/traps.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/kernel.h>
-#include <linux/kprobes.h>
-#include <linux/kdebug.h>
-#include <linux/module.h>
-#include <linux/reboot.h>
-#include <linux/uaccess.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/nmi.h>
-#include <asm/stack.h>
-#include <asm/traps.h>
-#include <asm/setup.h>
-
-#include <arch/interrupts.h>
-#include <arch/spr_def.h>
-#include <arch/opcode.h>
-
-void __init trap_init(void)
-{
- /* Nothing needed here since we link code at .intrpt */
-}
-
-int unaligned_fixup = 1;
-
-static int __init setup_unaligned_fixup(char *str)
-{
- /*
- * Say "=-1" to completely disable it. If you just do "=0", we
- * will still parse the instruction, then fire a SIGBUS with
- * the correct address from inside the single_step code.
- */
- if (kstrtoint(str, 0, &unaligned_fixup) != 0)
- return 0;
-
- pr_info("Fixups for unaligned data accesses are %s\n",
- unaligned_fixup >= 0 ?
- (unaligned_fixup ? "enabled" : "disabled") :
- "completely disabled");
- return 1;
-}
-__setup("unaligned_fixup=", setup_unaligned_fixup);
-
-#if CHIP_HAS_TILE_DMA()
-
-static int dma_disabled;
-
-static int __init nodma(char *str)
-{
- pr_info("User-space DMA is disabled\n");
- dma_disabled = 1;
- return 1;
-}
-__setup("nodma", nodma);
-
-/* How to decode SPR_GPV_REASON */
-#define IRET_ERROR (1U << 31)
-#define MT_ERROR (1U << 30)
-#define MF_ERROR (1U << 29)
-#define SPR_INDEX ((1U << 15) - 1)
-#define SPR_MPL_SHIFT 9 /* starting bit position for MPL encoded in SPR */
-
-/*
- * See if this GPV is just to notify the kernel of SPR use and we can
- * retry the user instruction after adjusting some MPLs suitably.
- */
-static int retry_gpv(unsigned int gpv_reason)
-{
- int mpl;
-
- if (gpv_reason & IRET_ERROR)
- return 0;
-
- BUG_ON((gpv_reason & (MT_ERROR|MF_ERROR)) == 0);
- mpl = (gpv_reason & SPR_INDEX) >> SPR_MPL_SHIFT;
- if (mpl == INT_DMA_NOTIFY && !dma_disabled) {
- /* User is turning on DMA. Allow it and retry. */
- printk(KERN_DEBUG "Process %d/%s is now enabled for DMA\n",
- current->pid, current->comm);
- BUG_ON(current->thread.tile_dma_state.enabled);
- current->thread.tile_dma_state.enabled = 1;
- grant_dma_mpls();
- return 1;
- }
-
- return 0;
-}
-
-#endif /* CHIP_HAS_TILE_DMA() */
-
-extern tile_bundle_bits bpt_code;
-
-asm(".pushsection .rodata.bpt_code,\"a\";"
- ".align 8;"
- "bpt_code: bpt;"
- ".size bpt_code,.-bpt_code;"
- ".popsection");
-
-static int special_ill(tile_bundle_bits bundle, int *sigp, int *codep)
-{
- int sig, code, maxcode;
-
- if (bundle == bpt_code) {
- *sigp = SIGTRAP;
- *codep = TRAP_BRKPT;
- return 1;
- }
-
- /* If it's a "raise" bundle, then "ill" must be in pipe X1. */
-#ifdef __tilegx__
- if ((bundle & TILEGX_BUNDLE_MODE_MASK) != 0)
- return 0;
- if (get_Opcode_X1(bundle) != RRR_0_OPCODE_X1)
- return 0;
- if (get_RRROpcodeExtension_X1(bundle) != UNARY_RRR_0_OPCODE_X1)
- return 0;
- if (get_UnaryOpcodeExtension_X1(bundle) != ILL_UNARY_OPCODE_X1)
- return 0;
-#else
- if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK)
- return 0;
- if (get_Opcode_X1(bundle) != SHUN_0_OPCODE_X1)
- return 0;
- if (get_UnShOpcodeExtension_X1(bundle) != UN_0_SHUN_0_OPCODE_X1)
- return 0;
- if (get_UnOpcodeExtension_X1(bundle) != ILL_UN_0_SHUN_0_OPCODE_X1)
- return 0;
-#endif
-
- /* Check that the magic distinguishers are set to mean "raise". */
- if (get_Dest_X1(bundle) != 29 || get_SrcA_X1(bundle) != 37)
- return 0;
-
- /* There must be an "addli zero, zero, VAL" in X0. */
- if (get_Opcode_X0(bundle) != ADDLI_OPCODE_X0)
- return 0;
- if (get_Dest_X0(bundle) != TREG_ZERO)
- return 0;
- if (get_SrcA_X0(bundle) != TREG_ZERO)
- return 0;
-
- /*
- * Validate the proposed signal number and si_code value.
- * Note that we embed these in the static instruction itself
- * so that we perturb the register state as little as possible
- * at the time of the actual fault; it's unlikely you'd ever
- * need to dynamically choose which kind of fault to raise
- * from user space.
- */
- sig = get_Imm16_X0(bundle) & 0x3f;
- switch (sig) {
- case SIGILL:
- maxcode = NSIGILL;
- break;
- case SIGFPE:
- maxcode = NSIGFPE;
- break;
- case SIGSEGV:
- maxcode = NSIGSEGV;
- break;
- case SIGBUS:
- maxcode = NSIGBUS;
- break;
- case SIGTRAP:
- maxcode = NSIGTRAP;
- break;
- default:
- return 0;
- }
- code = (get_Imm16_X0(bundle) >> 6) & 0xf;
- if (code <= 0 || code > maxcode)
- return 0;
-
- /* Make it the requested signal. */
- *sigp = sig;
- *codep = code;
- return 1;
-}
-
-static const char *const int_name[] = {
- [INT_MEM_ERROR] = "Memory error",
- [INT_ILL] = "Illegal instruction",
- [INT_GPV] = "General protection violation",
- [INT_UDN_ACCESS] = "UDN access",
- [INT_IDN_ACCESS] = "IDN access",
-#if CHIP_HAS_SN()
- [INT_SN_ACCESS] = "SN access",
-#endif
- [INT_SWINT_3] = "Software interrupt 3",
- [INT_SWINT_2] = "Software interrupt 2",
- [INT_SWINT_0] = "Software interrupt 0",
- [INT_UNALIGN_DATA] = "Unaligned data",
- [INT_DOUBLE_FAULT] = "Double fault",
-#ifdef __tilegx__
- [INT_ILL_TRANS] = "Illegal virtual address",
-#endif
-};
-
-static int do_bpt(struct pt_regs *regs)
-{
- unsigned long bundle, bcode, bpt;
-
- bundle = *(unsigned long *)instruction_pointer(regs);
-
- /*
- * bpt shoule be { bpt; nop }, which is 0x286a44ae51485000ULL.
- * we encode the unused least significant bits for other purpose.
- */
- bpt = bundle & ~((1ULL << 12) - 1);
- if (bpt != TILE_BPT_BUNDLE)
- return 0;
-
- bcode = bundle & ((1ULL << 12) - 1);
- /*
- * notify the kprobe handlers, if instruction is likely to
- * pertain to them.
- */
- switch (bcode) {
- /* breakpoint_insn */
- case 0:
- notify_die(DIE_BREAK, "debug", regs, bundle,
- INT_ILL, SIGTRAP);
- break;
- /* compiled_bpt */
- case DIE_COMPILED_BPT:
- notify_die(DIE_COMPILED_BPT, "debug", regs, bundle,
- INT_ILL, SIGTRAP);
- break;
- /* breakpoint2_insn */
- case DIE_SSTEPBP:
- notify_die(DIE_SSTEPBP, "single_step", regs, bundle,
- INT_ILL, SIGTRAP);
- break;
- default:
- return 0;
- }
-
- return 1;
-}
-
-void __kprobes do_trap(struct pt_regs *regs, int fault_num,
- unsigned long reason)
-{
- siginfo_t info;
- int signo, code;
- unsigned long address = 0;
- tile_bundle_bits instr;
- int is_kernel = !user_mode(regs);
-
- clear_siginfo(&info);
-
- /* Handle breakpoints, etc. */
- if (is_kernel && fault_num == INT_ILL && do_bpt(regs))
- return;
-
- /* Re-enable interrupts, if they were previously enabled. */
- if (!(regs->flags & PT_FLAGS_DISABLE_IRQ))
- local_irq_enable();
-
- /*
- * If it hits in kernel mode and we can't fix it up, just exit the
- * current process and hope for the best.
- */
- if (is_kernel) {
- const char *name;
- char buf[100];
- if (fixup_exception(regs)) /* ILL_TRANS or UNALIGN_DATA */
- return;
- if (fault_num >= 0 &&
- fault_num < ARRAY_SIZE(int_name) &&
- int_name[fault_num] != NULL)
- name = int_name[fault_num];
- else
- name = "Unknown interrupt";
- if (fault_num == INT_GPV)
- snprintf(buf, sizeof(buf), "; GPV_REASON %#lx", reason);
-#ifdef __tilegx__
- else if (fault_num == INT_ILL_TRANS)
- snprintf(buf, sizeof(buf), "; address %#lx", reason);
-#endif
- else
- buf[0] = '\0';
- pr_alert("Kernel took bad trap %d (%s) at PC %#lx%s\n",
- fault_num, name, regs->pc, buf);
- show_regs(regs);
- do_exit(SIGKILL); /* FIXME: implement i386 die() */
- }
-
- switch (fault_num) {
- case INT_MEM_ERROR:
- signo = SIGBUS;
- code = BUS_OBJERR;
- break;
- case INT_ILL:
- if (copy_from_user(&instr, (void __user *)regs->pc,
- sizeof(instr))) {
- pr_err("Unreadable instruction for INT_ILL: %#lx\n",
- regs->pc);
- do_exit(SIGKILL);
- }
- if (!special_ill(instr, &signo, &code)) {
- signo = SIGILL;
- code = ILL_ILLOPC;
- }
- address = regs->pc;
- break;
- case INT_GPV:
-#if CHIP_HAS_TILE_DMA()
- if (retry_gpv(reason))
- return;
-#endif
- /*FALLTHROUGH*/
- case INT_UDN_ACCESS:
- case INT_IDN_ACCESS:
-#if CHIP_HAS_SN()
- case INT_SN_ACCESS:
-#endif
- signo = SIGILL;
- code = ILL_PRVREG;
- address = regs->pc;
- break;
- case INT_SWINT_3:
- case INT_SWINT_2:
- case INT_SWINT_0:
- signo = SIGILL;
- code = ILL_ILLTRP;
- address = regs->pc;
- break;
- case INT_UNALIGN_DATA:
-#ifndef __tilegx__ /* Emulated support for single step debugging */
- if (unaligned_fixup >= 0) {
- struct single_step_state *state =
- current_thread_info()->step_state;
- if (!state ||
- (void __user *)(regs->pc) != state->buffer) {
- single_step_once(regs);
- return;
- }
- }
-#endif
- signo = SIGBUS;
- code = BUS_ADRALN;
- address = 0;
- break;
- case INT_DOUBLE_FAULT:
- /*
- * For double fault, "reason" is actually passed as
- * SYSTEM_SAVE_K_2, the hypervisor's double-fault info, so
- * we can provide the original fault number rather than
- * the uninteresting "INT_DOUBLE_FAULT" so the user can
- * learn what actually struck while PL0 ICS was set.
- */
- fault_num = reason;
- signo = SIGILL;
- code = ILL_DBLFLT;
- address = regs->pc;
- break;
-#ifdef __tilegx__
- case INT_ILL_TRANS: {
- /* Avoid a hardware erratum with the return address stack. */
- fill_ra_stack();
-
- signo = SIGSEGV;
- address = reason;
- code = SEGV_MAPERR;
- break;
- }
-#endif
- default:
- panic("Unexpected do_trap interrupt number %d", fault_num);
- }
-
- info.si_signo = signo;
- info.si_code = code;
- info.si_addr = (void __user *)address;
- if (signo == SIGILL)
- info.si_trapno = fault_num;
- if (signo != SIGTRAP)
- trace_unhandled_signal("trap", regs, address, signo);
- force_sig_info(signo, &info, current);
-}
-
-void do_nmi(struct pt_regs *regs, int fault_num, unsigned long reason)
-{
- nmi_enter();
- switch (reason) {
-#ifdef arch_trigger_cpumask_backtrace
- case TILE_NMI_DUMP_STACK:
- nmi_cpu_backtrace(regs);
- break;
-#endif
- default:
- panic("Unexpected do_nmi type %ld", reason);
- }
- nmi_exit();
-}
-
-/* Deprecated function currently only used here. */
-extern void _dump_stack(int dummy, ulong pc, ulong lr, ulong sp, ulong r52);
-
-void kernel_double_fault(int dummy, ulong pc, ulong lr, ulong sp, ulong r52)
-{
- _dump_stack(dummy, pc, lr, sp, r52);
- pr_emerg("Double fault: exiting\n");
- machine_halt();
-}
diff --git a/arch/tile/kernel/unaligned.c b/arch/tile/kernel/unaligned.c
deleted file mode 100644
index 77a0b6b6a2a1..000000000000
--- a/arch/tile/kernel/unaligned.c
+++ /dev/null
@@ -1,1603 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * A code-rewriter that handles unaligned exception.
- */
-
-#include <linux/smp.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/thread_info.h>
-#include <linux/uaccess.h>
-#include <linux/mman.h>
-#include <linux/types.h>
-#include <linux/err.h>
-#include <linux/extable.h>
-#include <linux/compat.h>
-#include <linux/prctl.h>
-#include <asm/cacheflush.h>
-#include <asm/traps.h>
-#include <linux/uaccess.h>
-#include <asm/unaligned.h>
-#include <arch/abi.h>
-#include <arch/spr_def.h>
-#include <arch/opcode.h>
-
-
-/*
- * This file handles unaligned exception for tile-Gx. The tilepro's unaligned
- * exception is supported out of single_step.c
- */
-
-int unaligned_printk;
-
-static int __init setup_unaligned_printk(char *str)
-{
- long val;
- if (kstrtol(str, 0, &val) != 0)
- return 0;
- unaligned_printk = val;
- pr_info("Printk for each unaligned data accesses is %s\n",
- unaligned_printk ? "enabled" : "disabled");
- return 1;
-}
-__setup("unaligned_printk=", setup_unaligned_printk);
-
-unsigned int unaligned_fixup_count;
-
-#ifdef __tilegx__
-
-/*
- * Unalign data jit fixup code fragement. Reserved space is 128 bytes.
- * The 1st 64-bit word saves fault PC address, 2nd word is the fault
- * instruction bundle followed by 14 JIT bundles.
- */
-
-struct unaligned_jit_fragment {
- unsigned long pc;
- tilegx_bundle_bits bundle;
- tilegx_bundle_bits insn[14];
-};
-
-/*
- * Check if a nop or fnop at bundle's pipeline X0.
- */
-
-static bool is_bundle_x0_nop(tilegx_bundle_bits bundle)
-{
- return (((get_UnaryOpcodeExtension_X0(bundle) ==
- NOP_UNARY_OPCODE_X0) &&
- (get_RRROpcodeExtension_X0(bundle) ==
- UNARY_RRR_0_OPCODE_X0) &&
- (get_Opcode_X0(bundle) ==
- RRR_0_OPCODE_X0)) ||
- ((get_UnaryOpcodeExtension_X0(bundle) ==
- FNOP_UNARY_OPCODE_X0) &&
- (get_RRROpcodeExtension_X0(bundle) ==
- UNARY_RRR_0_OPCODE_X0) &&
- (get_Opcode_X0(bundle) ==
- RRR_0_OPCODE_X0)));
-}
-
-/*
- * Check if nop or fnop at bundle's pipeline X1.
- */
-
-static bool is_bundle_x1_nop(tilegx_bundle_bits bundle)
-{
- return (((get_UnaryOpcodeExtension_X1(bundle) ==
- NOP_UNARY_OPCODE_X1) &&
- (get_RRROpcodeExtension_X1(bundle) ==
- UNARY_RRR_0_OPCODE_X1) &&
- (get_Opcode_X1(bundle) ==
- RRR_0_OPCODE_X1)) ||
- ((get_UnaryOpcodeExtension_X1(bundle) ==
- FNOP_UNARY_OPCODE_X1) &&
- (get_RRROpcodeExtension_X1(bundle) ==
- UNARY_RRR_0_OPCODE_X1) &&
- (get_Opcode_X1(bundle) ==
- RRR_0_OPCODE_X1)));
-}
-
-/*
- * Check if nop or fnop at bundle's Y0 pipeline.
- */
-
-static bool is_bundle_y0_nop(tilegx_bundle_bits bundle)
-{
- return (((get_UnaryOpcodeExtension_Y0(bundle) ==
- NOP_UNARY_OPCODE_Y0) &&
- (get_RRROpcodeExtension_Y0(bundle) ==
- UNARY_RRR_1_OPCODE_Y0) &&
- (get_Opcode_Y0(bundle) ==
- RRR_1_OPCODE_Y0)) ||
- ((get_UnaryOpcodeExtension_Y0(bundle) ==
- FNOP_UNARY_OPCODE_Y0) &&
- (get_RRROpcodeExtension_Y0(bundle) ==
- UNARY_RRR_1_OPCODE_Y0) &&
- (get_Opcode_Y0(bundle) ==
- RRR_1_OPCODE_Y0)));
-}
-
-/*
- * Check if nop or fnop at bundle's pipeline Y1.
- */
-
-static bool is_bundle_y1_nop(tilegx_bundle_bits bundle)
-{
- return (((get_UnaryOpcodeExtension_Y1(bundle) ==
- NOP_UNARY_OPCODE_Y1) &&
- (get_RRROpcodeExtension_Y1(bundle) ==
- UNARY_RRR_1_OPCODE_Y1) &&
- (get_Opcode_Y1(bundle) ==
- RRR_1_OPCODE_Y1)) ||
- ((get_UnaryOpcodeExtension_Y1(bundle) ==
- FNOP_UNARY_OPCODE_Y1) &&
- (get_RRROpcodeExtension_Y1(bundle) ==
- UNARY_RRR_1_OPCODE_Y1) &&
- (get_Opcode_Y1(bundle) ==
- RRR_1_OPCODE_Y1)));
-}
-
-/*
- * Test if a bundle's y0 and y1 pipelines are both nop or fnop.
- */
-
-static bool is_y0_y1_nop(tilegx_bundle_bits bundle)
-{
- return is_bundle_y0_nop(bundle) && is_bundle_y1_nop(bundle);
-}
-
-/*
- * Test if a bundle's x0 and x1 pipelines are both nop or fnop.
- */
-
-static bool is_x0_x1_nop(tilegx_bundle_bits bundle)
-{
- return is_bundle_x0_nop(bundle) && is_bundle_x1_nop(bundle);
-}
-
-/*
- * Find the destination, source registers of fault unalign access instruction
- * at X1 or Y2. Also, allocate up to 3 scratch registers clob1, clob2 and
- * clob3, which are guaranteed different from any register used in the fault
- * bundle. r_alias is used to return if the other instructions other than the
- * unalign load/store shares same register with ra, rb and rd.
- */
-
-static void find_regs(tilegx_bundle_bits bundle, uint64_t *rd, uint64_t *ra,
- uint64_t *rb, uint64_t *clob1, uint64_t *clob2,
- uint64_t *clob3, bool *r_alias)
-{
- int i;
- uint64_t reg;
- uint64_t reg_map = 0, alias_reg_map = 0, map;
- bool alias = false;
-
- /*
- * Parse fault bundle, find potential used registers and mark
- * corresponding bits in reg_map and alias_map. These 2 bit maps
- * are used to find the scratch registers and determine if there
- * is register alias.
- */
- if (bundle & TILEGX_BUNDLE_MODE_MASK) { /* Y Mode Bundle. */
-
- reg = get_SrcA_Y2(bundle);
- reg_map |= 1ULL << reg;
- *ra = reg;
- reg = get_SrcBDest_Y2(bundle);
- reg_map |= 1ULL << reg;
-
- if (rd) {
- /* Load. */
- *rd = reg;
- alias_reg_map = (1ULL << *rd) | (1ULL << *ra);
- } else {
- /* Store. */
- *rb = reg;
- alias_reg_map = (1ULL << *ra) | (1ULL << *rb);
- }
-
- if (!is_bundle_y1_nop(bundle)) {
- reg = get_SrcA_Y1(bundle);
- reg_map |= (1ULL << reg);
- map = (1ULL << reg);
-
- reg = get_SrcB_Y1(bundle);
- reg_map |= (1ULL << reg);
- map |= (1ULL << reg);
-
- reg = get_Dest_Y1(bundle);
- reg_map |= (1ULL << reg);
- map |= (1ULL << reg);
-
- if (map & alias_reg_map)
- alias = true;
- }
-
- if (!is_bundle_y0_nop(bundle)) {
- reg = get_SrcA_Y0(bundle);
- reg_map |= (1ULL << reg);
- map = (1ULL << reg);
-
- reg = get_SrcB_Y0(bundle);
- reg_map |= (1ULL << reg);
- map |= (1ULL << reg);
-
- reg = get_Dest_Y0(bundle);
- reg_map |= (1ULL << reg);
- map |= (1ULL << reg);
-
- if (map & alias_reg_map)
- alias = true;
- }
- } else { /* X Mode Bundle. */
-
- reg = get_SrcA_X1(bundle);
- reg_map |= (1ULL << reg);
- *ra = reg;
- if (rd) {
- /* Load. */
- reg = get_Dest_X1(bundle);
- reg_map |= (1ULL << reg);
- *rd = reg;
- alias_reg_map = (1ULL << *rd) | (1ULL << *ra);
- } else {
- /* Store. */
- reg = get_SrcB_X1(bundle);
- reg_map |= (1ULL << reg);
- *rb = reg;
- alias_reg_map = (1ULL << *ra) | (1ULL << *rb);
- }
-
- if (!is_bundle_x0_nop(bundle)) {
- reg = get_SrcA_X0(bundle);
- reg_map |= (1ULL << reg);
- map = (1ULL << reg);
-
- reg = get_SrcB_X0(bundle);
- reg_map |= (1ULL << reg);
- map |= (1ULL << reg);
-
- reg = get_Dest_X0(bundle);
- reg_map |= (1ULL << reg);
- map |= (1ULL << reg);
-
- if (map & alias_reg_map)
- alias = true;
- }
- }
-
- /*
- * "alias" indicates if the unalign access registers have collision
- * with others in the same bundle. We jsut simply test all register
- * operands case (RRR), ignored the case with immidate. If a bundle
- * has no register alias, we may do fixup in a simple or fast manner.
- * So if an immidata field happens to hit with a register, we may end
- * up fall back to the generic handling.
- */
-
- *r_alias = alias;
-
- /* Flip bits on reg_map. */
- reg_map ^= -1ULL;
-
- /* Scan reg_map lower 54(TREG_SP) bits to find 3 set bits. */
- for (i = 0; i < TREG_SP; i++) {
- if (reg_map & (0x1ULL << i)) {
- if (*clob1 == -1) {
- *clob1 = i;
- } else if (*clob2 == -1) {
- *clob2 = i;
- } else if (*clob3 == -1) {
- *clob3 = i;
- return;
- }
- }
- }
-}
-
-/*
- * Sanity check for register ra, rb, rd, clob1/2/3. Return true if any of them
- * is unexpected.
- */
-
-static bool check_regs(uint64_t rd, uint64_t ra, uint64_t rb,
- uint64_t clob1, uint64_t clob2, uint64_t clob3)
-{
- bool unexpected = false;
- if ((ra >= 56) && (ra != TREG_ZERO))
- unexpected = true;
-
- if ((clob1 >= 56) || (clob2 >= 56) || (clob3 >= 56))
- unexpected = true;
-
- if (rd != -1) {
- if ((rd >= 56) && (rd != TREG_ZERO))
- unexpected = true;
- } else {
- if ((rb >= 56) && (rb != TREG_ZERO))
- unexpected = true;
- }
- return unexpected;
-}
-
-
-#define GX_INSN_X0_MASK ((1ULL << 31) - 1)
-#define GX_INSN_X1_MASK (((1ULL << 31) - 1) << 31)
-#define GX_INSN_Y0_MASK ((0xFULL << 27) | (0xFFFFFULL))
-#define GX_INSN_Y1_MASK (GX_INSN_Y0_MASK << 31)
-#define GX_INSN_Y2_MASK ((0x7FULL << 51) | (0x7FULL << 20))
-
-#ifdef __LITTLE_ENDIAN
-#define GX_INSN_BSWAP(_bundle_) (_bundle_)
-#else
-#define GX_INSN_BSWAP(_bundle_) swab64(_bundle_)
-#endif /* __LITTLE_ENDIAN */
-
-/*
- * __JIT_CODE(.) creates template bundles in .rodata.unalign_data section.
- * The corresponding static function jix_x#_###(.) generates partial or
- * whole bundle based on the template and given arguments.
- */
-
-#define __JIT_CODE(_X_) \
- asm (".pushsection .rodata.unalign_data, \"a\"\n" \
- _X_"\n" \
- ".popsection\n")
-
-__JIT_CODE("__unalign_jit_x1_mtspr: {mtspr 0, r0}");
-static tilegx_bundle_bits jit_x1_mtspr(int spr, int reg)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_mtspr;
- return (GX_INSN_BSWAP(__unalign_jit_x1_mtspr) & GX_INSN_X1_MASK) |
- create_MT_Imm14_X1(spr) | create_SrcA_X1(reg);
-}
-
-__JIT_CODE("__unalign_jit_x1_mfspr: {mfspr r0, 0}");
-static tilegx_bundle_bits jit_x1_mfspr(int reg, int spr)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_mfspr;
- return (GX_INSN_BSWAP(__unalign_jit_x1_mfspr) & GX_INSN_X1_MASK) |
- create_MF_Imm14_X1(spr) | create_Dest_X1(reg);
-}
-
-__JIT_CODE("__unalign_jit_x0_addi: {addi r0, r0, 0; iret}");
-static tilegx_bundle_bits jit_x0_addi(int rd, int ra, int imm8)
-{
- extern tilegx_bundle_bits __unalign_jit_x0_addi;
- return (GX_INSN_BSWAP(__unalign_jit_x0_addi) & GX_INSN_X0_MASK) |
- create_Dest_X0(rd) | create_SrcA_X0(ra) |
- create_Imm8_X0(imm8);
-}
-
-__JIT_CODE("__unalign_jit_x1_ldna: {ldna r0, r0}");
-static tilegx_bundle_bits jit_x1_ldna(int rd, int ra)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_ldna;
- return (GX_INSN_BSWAP(__unalign_jit_x1_ldna) & GX_INSN_X1_MASK) |
- create_Dest_X1(rd) | create_SrcA_X1(ra);
-}
-
-__JIT_CODE("__unalign_jit_x0_dblalign: {dblalign r0, r0 ,r0}");
-static tilegx_bundle_bits jit_x0_dblalign(int rd, int ra, int rb)
-{
- extern tilegx_bundle_bits __unalign_jit_x0_dblalign;
- return (GX_INSN_BSWAP(__unalign_jit_x0_dblalign) & GX_INSN_X0_MASK) |
- create_Dest_X0(rd) | create_SrcA_X0(ra) |
- create_SrcB_X0(rb);
-}
-
-__JIT_CODE("__unalign_jit_x1_iret: {iret}");
-static tilegx_bundle_bits jit_x1_iret(void)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_iret;
- return GX_INSN_BSWAP(__unalign_jit_x1_iret) & GX_INSN_X1_MASK;
-}
-
-__JIT_CODE("__unalign_jit_x01_fnop: {fnop;fnop}");
-static tilegx_bundle_bits jit_x0_fnop(void)
-{
- extern tilegx_bundle_bits __unalign_jit_x01_fnop;
- return GX_INSN_BSWAP(__unalign_jit_x01_fnop) & GX_INSN_X0_MASK;
-}
-
-static tilegx_bundle_bits jit_x1_fnop(void)
-{
- extern tilegx_bundle_bits __unalign_jit_x01_fnop;
- return GX_INSN_BSWAP(__unalign_jit_x01_fnop) & GX_INSN_X1_MASK;
-}
-
-__JIT_CODE("__unalign_jit_y2_dummy: {fnop; fnop; ld zero, sp}");
-static tilegx_bundle_bits jit_y2_dummy(void)
-{
- extern tilegx_bundle_bits __unalign_jit_y2_dummy;
- return GX_INSN_BSWAP(__unalign_jit_y2_dummy) & GX_INSN_Y2_MASK;
-}
-
-static tilegx_bundle_bits jit_y1_fnop(void)
-{
- extern tilegx_bundle_bits __unalign_jit_y2_dummy;
- return GX_INSN_BSWAP(__unalign_jit_y2_dummy) & GX_INSN_Y1_MASK;
-}
-
-__JIT_CODE("__unalign_jit_x1_st1_add: {st1_add r1, r0, 0}");
-static tilegx_bundle_bits jit_x1_st1_add(int ra, int rb, int imm8)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_st1_add;
- return (GX_INSN_BSWAP(__unalign_jit_x1_st1_add) &
- (~create_SrcA_X1(-1)) &
- GX_INSN_X1_MASK) | create_SrcA_X1(ra) |
- create_SrcB_X1(rb) | create_Dest_Imm8_X1(imm8);
-}
-
-__JIT_CODE("__unalign_jit_x1_st: {crc32_8 r1, r0, r0; st r0, r0}");
-static tilegx_bundle_bits jit_x1_st(int ra, int rb)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_st;
- return (GX_INSN_BSWAP(__unalign_jit_x1_st) & GX_INSN_X1_MASK) |
- create_SrcA_X1(ra) | create_SrcB_X1(rb);
-}
-
-__JIT_CODE("__unalign_jit_x1_st_add: {st_add r1, r0, 0}");
-static tilegx_bundle_bits jit_x1_st_add(int ra, int rb, int imm8)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_st_add;
- return (GX_INSN_BSWAP(__unalign_jit_x1_st_add) &
- (~create_SrcA_X1(-1)) &
- GX_INSN_X1_MASK) | create_SrcA_X1(ra) |
- create_SrcB_X1(rb) | create_Dest_Imm8_X1(imm8);
-}
-
-__JIT_CODE("__unalign_jit_x1_ld: {crc32_8 r1, r0, r0; ld r0, r0}");
-static tilegx_bundle_bits jit_x1_ld(int rd, int ra)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_ld;
- return (GX_INSN_BSWAP(__unalign_jit_x1_ld) & GX_INSN_X1_MASK) |
- create_Dest_X1(rd) | create_SrcA_X1(ra);
-}
-
-__JIT_CODE("__unalign_jit_x1_ld_add: {ld_add r1, r0, 0}");
-static tilegx_bundle_bits jit_x1_ld_add(int rd, int ra, int imm8)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_ld_add;
- return (GX_INSN_BSWAP(__unalign_jit_x1_ld_add) &
- (~create_Dest_X1(-1)) &
- GX_INSN_X1_MASK) | create_Dest_X1(rd) |
- create_SrcA_X1(ra) | create_Imm8_X1(imm8);
-}
-
-__JIT_CODE("__unalign_jit_x0_bfexts: {bfexts r0, r0, 0, 0}");
-static tilegx_bundle_bits jit_x0_bfexts(int rd, int ra, int bfs, int bfe)
-{
- extern tilegx_bundle_bits __unalign_jit_x0_bfexts;
- return (GX_INSN_BSWAP(__unalign_jit_x0_bfexts) &
- GX_INSN_X0_MASK) |
- create_Dest_X0(rd) | create_SrcA_X0(ra) |
- create_BFStart_X0(bfs) | create_BFEnd_X0(bfe);
-}
-
-__JIT_CODE("__unalign_jit_x0_bfextu: {bfextu r0, r0, 0, 0}");
-static tilegx_bundle_bits jit_x0_bfextu(int rd, int ra, int bfs, int bfe)
-{
- extern tilegx_bundle_bits __unalign_jit_x0_bfextu;
- return (GX_INSN_BSWAP(__unalign_jit_x0_bfextu) &
- GX_INSN_X0_MASK) |
- create_Dest_X0(rd) | create_SrcA_X0(ra) |
- create_BFStart_X0(bfs) | create_BFEnd_X0(bfe);
-}
-
-__JIT_CODE("__unalign_jit_x1_addi: {bfextu r1, r1, 0, 0; addi r0, r0, 0}");
-static tilegx_bundle_bits jit_x1_addi(int rd, int ra, int imm8)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_addi;
- return (GX_INSN_BSWAP(__unalign_jit_x1_addi) & GX_INSN_X1_MASK) |
- create_Dest_X1(rd) | create_SrcA_X1(ra) |
- create_Imm8_X1(imm8);
-}
-
-__JIT_CODE("__unalign_jit_x0_shrui: {shrui r0, r0, 0; iret}");
-static tilegx_bundle_bits jit_x0_shrui(int rd, int ra, int imm6)
-{
- extern tilegx_bundle_bits __unalign_jit_x0_shrui;
- return (GX_INSN_BSWAP(__unalign_jit_x0_shrui) &
- GX_INSN_X0_MASK) |
- create_Dest_X0(rd) | create_SrcA_X0(ra) |
- create_ShAmt_X0(imm6);
-}
-
-__JIT_CODE("__unalign_jit_x0_rotli: {rotli r0, r0, 0; iret}");
-static tilegx_bundle_bits jit_x0_rotli(int rd, int ra, int imm6)
-{
- extern tilegx_bundle_bits __unalign_jit_x0_rotli;
- return (GX_INSN_BSWAP(__unalign_jit_x0_rotli) &
- GX_INSN_X0_MASK) |
- create_Dest_X0(rd) | create_SrcA_X0(ra) |
- create_ShAmt_X0(imm6);
-}
-
-__JIT_CODE("__unalign_jit_x1_bnezt: {bnezt r0, __unalign_jit_x1_bnezt}");
-static tilegx_bundle_bits jit_x1_bnezt(int ra, int broff)
-{
- extern tilegx_bundle_bits __unalign_jit_x1_bnezt;
- return (GX_INSN_BSWAP(__unalign_jit_x1_bnezt) &
- GX_INSN_X1_MASK) |
- create_SrcA_X1(ra) | create_BrOff_X1(broff);
-}
-
-#undef __JIT_CODE
-
-/*
- * This function generates unalign fixup JIT.
- *
- * We first find unalign load/store instruction's destination, source
- * registers: ra, rb and rd. and 3 scratch registers by calling
- * find_regs(...). 3 scratch clobbers should not alias with any register
- * used in the fault bundle. Then analyze the fault bundle to determine
- * if it's a load or store, operand width, branch or address increment etc.
- * At last generated JIT is copied into JIT code area in user space.
- */
-
-static
-void jit_bundle_gen(struct pt_regs *regs, tilegx_bundle_bits bundle,
- int align_ctl)
-{
- struct thread_info *info = current_thread_info();
- struct unaligned_jit_fragment frag;
- struct unaligned_jit_fragment *jit_code_area;
- tilegx_bundle_bits bundle_2 = 0;
- /* If bundle_2_enable = false, bundle_2 is fnop/nop operation. */
- bool bundle_2_enable = true;
- uint64_t ra = -1, rb = -1, rd = -1, clob1 = -1, clob2 = -1, clob3 = -1;
- /*
- * Indicate if the unalign access
- * instruction's registers hit with
- * others in the same bundle.
- */
- bool alias = false;
- bool load_n_store = true;
- bool load_store_signed = false;
- unsigned int load_store_size = 8;
- bool y1_br = false; /* True, for a branch in same bundle at Y1.*/
- int y1_br_reg = 0;
- /* True for link operation. i.e. jalr or lnk at Y1 */
- bool y1_lr = false;
- int y1_lr_reg = 0;
- bool x1_add = false;/* True, for load/store ADD instruction at X1*/
- int x1_add_imm8 = 0;
- bool unexpected = false;
- int n = 0, k;
-
- jit_code_area =
- (struct unaligned_jit_fragment *)(info->unalign_jit_base);
-
- memset((void *)&frag, 0, sizeof(frag));
-
- /* 0: X mode, Otherwise: Y mode. */
- if (bundle & TILEGX_BUNDLE_MODE_MASK) {
- unsigned int mod, opcode;
-
- if (get_Opcode_Y1(bundle) == RRR_1_OPCODE_Y1 &&
- get_RRROpcodeExtension_Y1(bundle) ==
- UNARY_RRR_1_OPCODE_Y1) {
-
- opcode = get_UnaryOpcodeExtension_Y1(bundle);
-
- /*
- * Test "jalr", "jalrp", "jr", "jrp" instruction at Y1
- * pipeline.
- */
- switch (opcode) {
- case JALR_UNARY_OPCODE_Y1:
- case JALRP_UNARY_OPCODE_Y1:
- y1_lr = true;
- y1_lr_reg = 55; /* Link register. */
- /* FALLTHROUGH */
- case JR_UNARY_OPCODE_Y1:
- case JRP_UNARY_OPCODE_Y1:
- y1_br = true;
- y1_br_reg = get_SrcA_Y1(bundle);
- break;
- case LNK_UNARY_OPCODE_Y1:
- /* "lnk" at Y1 pipeline. */
- y1_lr = true;
- y1_lr_reg = get_Dest_Y1(bundle);
- break;
- }
- }
-
- opcode = get_Opcode_Y2(bundle);
- mod = get_Mode(bundle);
-
- /*
- * bundle_2 is bundle after making Y2 as a dummy operation
- * - ld zero, sp
- */
- bundle_2 = (bundle & (~GX_INSN_Y2_MASK)) | jit_y2_dummy();
-
- /* Make Y1 as fnop if Y1 is a branch or lnk operation. */
- if (y1_br || y1_lr) {
- bundle_2 &= ~(GX_INSN_Y1_MASK);
- bundle_2 |= jit_y1_fnop();
- }
-
- if (is_y0_y1_nop(bundle_2))
- bundle_2_enable = false;
-
- if (mod == MODE_OPCODE_YC2) {
- /* Store. */
- load_n_store = false;
- load_store_size = 1 << opcode;
- load_store_signed = false;
- find_regs(bundle, 0, &ra, &rb, &clob1, &clob2,
- &clob3, &alias);
- if (load_store_size > 8)
- unexpected = true;
- } else {
- /* Load. */
- load_n_store = true;
- if (mod == MODE_OPCODE_YB2) {
- switch (opcode) {
- case LD_OPCODE_Y2:
- load_store_signed = false;
- load_store_size = 8;
- break;
- case LD4S_OPCODE_Y2:
- load_store_signed = true;
- load_store_size = 4;
- break;
- case LD4U_OPCODE_Y2:
- load_store_signed = false;
- load_store_size = 4;
- break;
- default:
- unexpected = true;
- }
- } else if (mod == MODE_OPCODE_YA2) {
- if (opcode == LD2S_OPCODE_Y2) {
- load_store_signed = true;
- load_store_size = 2;
- } else if (opcode == LD2U_OPCODE_Y2) {
- load_store_signed = false;
- load_store_size = 2;
- } else
- unexpected = true;
- } else
- unexpected = true;
- find_regs(bundle, &rd, &ra, &rb, &clob1, &clob2,
- &clob3, &alias);
- }
- } else {
- unsigned int opcode;
-
- /* bundle_2 is bundle after making X1 as "fnop". */
- bundle_2 = (bundle & (~GX_INSN_X1_MASK)) | jit_x1_fnop();
-
- if (is_x0_x1_nop(bundle_2))
- bundle_2_enable = false;
-
- if (get_Opcode_X1(bundle) == RRR_0_OPCODE_X1) {
- opcode = get_UnaryOpcodeExtension_X1(bundle);
-
- if (get_RRROpcodeExtension_X1(bundle) ==
- UNARY_RRR_0_OPCODE_X1) {
- load_n_store = true;
- find_regs(bundle, &rd, &ra, &rb, &clob1,
- &clob2, &clob3, &alias);
-
- switch (opcode) {
- case LD_UNARY_OPCODE_X1:
- load_store_signed = false;
- load_store_size = 8;
- break;
- case LD4S_UNARY_OPCODE_X1:
- load_store_signed = true;
- /* FALLTHROUGH */
- case LD4U_UNARY_OPCODE_X1:
- load_store_size = 4;
- break;
-
- case LD2S_UNARY_OPCODE_X1:
- load_store_signed = true;
- /* FALLTHROUGH */
- case LD2U_UNARY_OPCODE_X1:
- load_store_size = 2;
- break;
- default:
- unexpected = true;
- }
- } else {
- load_n_store = false;
- load_store_signed = false;
- find_regs(bundle, 0, &ra, &rb,
- &clob1, &clob2, &clob3,
- &alias);
-
- opcode = get_RRROpcodeExtension_X1(bundle);
- switch (opcode) {
- case ST_RRR_0_OPCODE_X1:
- load_store_size = 8;
- break;
- case ST4_RRR_0_OPCODE_X1:
- load_store_size = 4;
- break;
- case ST2_RRR_0_OPCODE_X1:
- load_store_size = 2;
- break;
- default:
- unexpected = true;
- }
- }
- } else if (get_Opcode_X1(bundle) == IMM8_OPCODE_X1) {
- load_n_store = true;
- opcode = get_Imm8OpcodeExtension_X1(bundle);
- switch (opcode) {
- case LD_ADD_IMM8_OPCODE_X1:
- load_store_size = 8;
- break;
-
- case LD4S_ADD_IMM8_OPCODE_X1:
- load_store_signed = true;
- /* FALLTHROUGH */
- case LD4U_ADD_IMM8_OPCODE_X1:
- load_store_size = 4;
- break;
-
- case LD2S_ADD_IMM8_OPCODE_X1:
- load_store_signed = true;
- /* FALLTHROUGH */
- case LD2U_ADD_IMM8_OPCODE_X1:
- load_store_size = 2;
- break;
-
- case ST_ADD_IMM8_OPCODE_X1:
- load_n_store = false;
- load_store_size = 8;
- break;
- case ST4_ADD_IMM8_OPCODE_X1:
- load_n_store = false;
- load_store_size = 4;
- break;
- case ST2_ADD_IMM8_OPCODE_X1:
- load_n_store = false;
- load_store_size = 2;
- break;
- default:
- unexpected = true;
- }
-
- if (!unexpected) {
- x1_add = true;
- if (load_n_store)
- x1_add_imm8 = get_Imm8_X1(bundle);
- else
- x1_add_imm8 = get_Dest_Imm8_X1(bundle);
- }
-
- find_regs(bundle, load_n_store ? (&rd) : NULL,
- &ra, &rb, &clob1, &clob2, &clob3, &alias);
- } else
- unexpected = true;
- }
-
- /*
- * Some sanity check for register numbers extracted from fault bundle.
- */
- if (check_regs(rd, ra, rb, clob1, clob2, clob3) == true)
- unexpected = true;
-
- /* Give warning if register ra has an aligned address. */
- if (!unexpected)
- WARN_ON(!((load_store_size - 1) & (regs->regs[ra])));
-
-
- /*
- * Fault came from kernel space, here we only need take care of
- * unaligned "get_user/put_user" macros defined in "uaccess.h".
- * Basically, we will handle bundle like this:
- * {ld/2u/4s rd, ra; movei rx, 0} or {st/2/4 ra, rb; movei rx, 0}
- * (Refer to file "arch/tile/include/asm/uaccess.h" for details).
- * For either load or store, byte-wise operation is performed by calling
- * get_user() or put_user(). If the macro returns non-zero value,
- * set the value to rx, otherwise set zero to rx. Finally make pc point
- * to next bundle and return.
- */
-
- if (EX1_PL(regs->ex1) != USER_PL) {
-
- unsigned long rx = 0;
- unsigned long x = 0, ret = 0;
-
- if (y1_br || y1_lr || x1_add ||
- (load_store_signed !=
- (load_n_store && load_store_size == 4))) {
- /* No branch, link, wrong sign-ext or load/store add. */
- unexpected = true;
- } else if (!unexpected) {
- if (bundle & TILEGX_BUNDLE_MODE_MASK) {
- /*
- * Fault bundle is Y mode.
- * Check if the Y1 and Y0 is the form of
- * { movei rx, 0; nop/fnop }, if yes,
- * find the rx.
- */
-
- if ((get_Opcode_Y1(bundle) == ADDI_OPCODE_Y1)
- && (get_SrcA_Y1(bundle) == TREG_ZERO) &&
- (get_Imm8_Y1(bundle) == 0) &&
- is_bundle_y0_nop(bundle)) {
- rx = get_Dest_Y1(bundle);
- } else if ((get_Opcode_Y0(bundle) ==
- ADDI_OPCODE_Y0) &&
- (get_SrcA_Y0(bundle) == TREG_ZERO) &&
- (get_Imm8_Y0(bundle) == 0) &&
- is_bundle_y1_nop(bundle)) {
- rx = get_Dest_Y0(bundle);
- } else {
- unexpected = true;
- }
- } else {
- /*
- * Fault bundle is X mode.
- * Check if the X0 is 'movei rx, 0',
- * if yes, find the rx.
- */
-
- if ((get_Opcode_X0(bundle) == IMM8_OPCODE_X0)
- && (get_Imm8OpcodeExtension_X0(bundle) ==
- ADDI_IMM8_OPCODE_X0) &&
- (get_SrcA_X0(bundle) == TREG_ZERO) &&
- (get_Imm8_X0(bundle) == 0)) {
- rx = get_Dest_X0(bundle);
- } else {
- unexpected = true;
- }
- }
-
- /* rx should be less than 56. */
- if (!unexpected && (rx >= 56))
- unexpected = true;
- }
-
- if (!search_exception_tables(regs->pc)) {
- /* No fixup in the exception tables for the pc. */
- unexpected = true;
- }
-
- if (unexpected) {
- /* Unexpected unalign kernel fault. */
- struct task_struct *tsk = validate_current();
-
- bust_spinlocks(1);
-
- show_regs(regs);
-
- if (unlikely(tsk->pid < 2)) {
- panic("Kernel unalign fault running %s!",
- tsk->pid ? "init" : "the idle task");
- }
-#ifdef SUPPORT_DIE
- die("Oops", regs);
-#endif
- bust_spinlocks(1);
-
- do_group_exit(SIGKILL);
-
- } else {
- unsigned long i, b = 0;
- unsigned char *ptr =
- (unsigned char *)regs->regs[ra];
- if (load_n_store) {
- /* handle get_user(x, ptr) */
- for (i = 0; i < load_store_size; i++) {
- ret = get_user(b, ptr++);
- if (!ret) {
- /* Success! update x. */
-#ifdef __LITTLE_ENDIAN
- x |= (b << (8 * i));
-#else
- x <<= 8;
- x |= b;
-#endif /* __LITTLE_ENDIAN */
- } else {
- x = 0;
- break;
- }
- }
-
- /* Sign-extend 4-byte loads. */
- if (load_store_size == 4)
- x = (long)(int)x;
-
- /* Set register rd. */
- regs->regs[rd] = x;
-
- /* Set register rx. */
- regs->regs[rx] = ret;
-
- /* Bump pc. */
- regs->pc += 8;
-
- } else {
- /* Handle put_user(x, ptr) */
- x = regs->regs[rb];
-#ifdef __LITTLE_ENDIAN
- b = x;
-#else
- /*
- * Swap x in order to store x from low
- * to high memory same as the
- * little-endian case.
- */
- switch (load_store_size) {
- case 8:
- b = swab64(x);
- break;
- case 4:
- b = swab32(x);
- break;
- case 2:
- b = swab16(x);
- break;
- }
-#endif /* __LITTLE_ENDIAN */
- for (i = 0; i < load_store_size; i++) {
- ret = put_user(b, ptr++);
- if (ret)
- break;
- /* Success! shift 1 byte. */
- b >>= 8;
- }
- /* Set register rx. */
- regs->regs[rx] = ret;
-
- /* Bump pc. */
- regs->pc += 8;
- }
- }
-
- unaligned_fixup_count++;
-
- if (unaligned_printk) {
- pr_info("%s/%d - Unalign fixup for kernel access to userspace %lx\n",
- current->comm, current->pid, regs->regs[ra]);
- }
-
- /* Done! Return to the exception handler. */
- return;
- }
-
- if ((align_ctl == 0) || unexpected) {
- siginfo_t info;
-
- clear_siginfo(&info);
- info.si_signo = SIGBUS;
- info.si_code = BUS_ADRALN;
- info.si_addr = (unsigned char __user *)0;
-
- if (unaligned_printk)
- pr_info("Unalign bundle: unexp @%llx, %llx\n",
- (unsigned long long)regs->pc,
- (unsigned long long)bundle);
-
- if (ra < 56) {
- unsigned long uaa = (unsigned long)regs->regs[ra];
- /* Set bus Address. */
- info.si_addr = (unsigned char __user *)uaa;
- }
-
- unaligned_fixup_count++;
-
- trace_unhandled_signal("unaligned fixup trap", regs,
- (unsigned long)info.si_addr, SIGBUS);
- force_sig_info(info.si_signo, &info, current);
- return;
- }
-
-#ifdef __LITTLE_ENDIAN
-#define UA_FIXUP_ADDR_DELTA 1
-#define UA_FIXUP_BFEXT_START(_B_) 0
-#define UA_FIXUP_BFEXT_END(_B_) (8 * (_B_) - 1)
-#else /* __BIG_ENDIAN */
-#define UA_FIXUP_ADDR_DELTA -1
-#define UA_FIXUP_BFEXT_START(_B_) (64 - 8 * (_B_))
-#define UA_FIXUP_BFEXT_END(_B_) 63
-#endif /* __LITTLE_ENDIAN */
-
-
-
- if ((ra != rb) && (rd != TREG_SP) && !alias &&
- !y1_br && !y1_lr && !x1_add) {
- /*
- * Simple case: ra != rb and no register alias found,
- * and no branch or link. This will be the majority.
- * We can do a little better for simplae case than the
- * generic scheme below.
- */
- if (!load_n_store) {
- /*
- * Simple store: ra != rb, no need for scratch register.
- * Just store and rotate to right bytewise.
- */
-#ifdef __BIG_ENDIAN
- frag.insn[n++] =
- jit_x0_addi(ra, ra, load_store_size - 1) |
- jit_x1_fnop();
-#endif /* __BIG_ENDIAN */
- for (k = 0; k < load_store_size; k++) {
- /* Store a byte. */
- frag.insn[n++] =
- jit_x0_rotli(rb, rb, 56) |
- jit_x1_st1_add(ra, rb,
- UA_FIXUP_ADDR_DELTA);
- }
-#ifdef __BIG_ENDIAN
- frag.insn[n] = jit_x1_addi(ra, ra, 1);
-#else
- frag.insn[n] = jit_x1_addi(ra, ra,
- -1 * load_store_size);
-#endif /* __LITTLE_ENDIAN */
-
- if (load_store_size == 8) {
- frag.insn[n] |= jit_x0_fnop();
- } else if (load_store_size == 4) {
- frag.insn[n] |= jit_x0_rotli(rb, rb, 32);
- } else { /* = 2 */
- frag.insn[n] |= jit_x0_rotli(rb, rb, 16);
- }
- n++;
- if (bundle_2_enable)
- frag.insn[n++] = bundle_2;
- frag.insn[n++] = jit_x0_fnop() | jit_x1_iret();
- } else {
- if (rd == ra) {
- /* Use two clobber registers: clob1/2. */
- frag.insn[n++] =
- jit_x0_addi(TREG_SP, TREG_SP, -16) |
- jit_x1_fnop();
- frag.insn[n++] =
- jit_x0_addi(clob1, ra, 7) |
- jit_x1_st_add(TREG_SP, clob1, -8);
- frag.insn[n++] =
- jit_x0_addi(clob2, ra, 0) |
- jit_x1_st(TREG_SP, clob2);
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ldna(rd, ra);
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ldna(clob1, clob1);
- /*
- * Note: we must make sure that rd must not
- * be sp. Recover clob1/2 from stack.
- */
- frag.insn[n++] =
- jit_x0_dblalign(rd, clob1, clob2) |
- jit_x1_ld_add(clob2, TREG_SP, 8);
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ld_add(clob1, TREG_SP, 16);
- } else {
- /* Use one clobber register: clob1 only. */
- frag.insn[n++] =
- jit_x0_addi(TREG_SP, TREG_SP, -16) |
- jit_x1_fnop();
- frag.insn[n++] =
- jit_x0_addi(clob1, ra, 7) |
- jit_x1_st(TREG_SP, clob1);
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ldna(rd, ra);
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ldna(clob1, clob1);
- /*
- * Note: we must make sure that rd must not
- * be sp. Recover clob1 from stack.
- */
- frag.insn[n++] =
- jit_x0_dblalign(rd, clob1, ra) |
- jit_x1_ld_add(clob1, TREG_SP, 16);
- }
-
- if (bundle_2_enable)
- frag.insn[n++] = bundle_2;
- /*
- * For non 8-byte load, extract corresponding bytes and
- * signed extension.
- */
- if (load_store_size == 4) {
- if (load_store_signed)
- frag.insn[n++] =
- jit_x0_bfexts(
- rd, rd,
- UA_FIXUP_BFEXT_START(4),
- UA_FIXUP_BFEXT_END(4)) |
- jit_x1_fnop();
- else
- frag.insn[n++] =
- jit_x0_bfextu(
- rd, rd,
- UA_FIXUP_BFEXT_START(4),
- UA_FIXUP_BFEXT_END(4)) |
- jit_x1_fnop();
- } else if (load_store_size == 2) {
- if (load_store_signed)
- frag.insn[n++] =
- jit_x0_bfexts(
- rd, rd,
- UA_FIXUP_BFEXT_START(2),
- UA_FIXUP_BFEXT_END(2)) |
- jit_x1_fnop();
- else
- frag.insn[n++] =
- jit_x0_bfextu(
- rd, rd,
- UA_FIXUP_BFEXT_START(2),
- UA_FIXUP_BFEXT_END(2)) |
- jit_x1_fnop();
- }
-
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_iret();
- }
- } else if (!load_n_store) {
-
- /*
- * Generic memory store cases: use 3 clobber registers.
- *
- * Alloc space for saveing clob2,1,3 on user's stack.
- * register clob3 points to where clob2 saved, followed by
- * clob1 and 3 from high to low memory.
- */
- frag.insn[n++] =
- jit_x0_addi(TREG_SP, TREG_SP, -32) |
- jit_x1_fnop();
- frag.insn[n++] =
- jit_x0_addi(clob3, TREG_SP, 16) |
- jit_x1_st_add(TREG_SP, clob3, 8);
-#ifdef __LITTLE_ENDIAN
- frag.insn[n++] =
- jit_x0_addi(clob1, ra, 0) |
- jit_x1_st_add(TREG_SP, clob1, 8);
-#else
- frag.insn[n++] =
- jit_x0_addi(clob1, ra, load_store_size - 1) |
- jit_x1_st_add(TREG_SP, clob1, 8);
-#endif
- if (load_store_size == 8) {
- /*
- * We save one byte a time, not for fast, but compact
- * code. After each store, data source register shift
- * right one byte. unchanged after 8 stores.
- */
- frag.insn[n++] =
- jit_x0_addi(clob2, TREG_ZERO, 7) |
- jit_x1_st_add(TREG_SP, clob2, 16);
- frag.insn[n++] =
- jit_x0_rotli(rb, rb, 56) |
- jit_x1_st1_add(clob1, rb, UA_FIXUP_ADDR_DELTA);
- frag.insn[n++] =
- jit_x0_addi(clob2, clob2, -1) |
- jit_x1_bnezt(clob2, -1);
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_addi(clob2, y1_br_reg, 0);
- } else if (load_store_size == 4) {
- frag.insn[n++] =
- jit_x0_addi(clob2, TREG_ZERO, 3) |
- jit_x1_st_add(TREG_SP, clob2, 16);
- frag.insn[n++] =
- jit_x0_rotli(rb, rb, 56) |
- jit_x1_st1_add(clob1, rb, UA_FIXUP_ADDR_DELTA);
- frag.insn[n++] =
- jit_x0_addi(clob2, clob2, -1) |
- jit_x1_bnezt(clob2, -1);
- /*
- * same as 8-byte case, but need shift another 4
- * byte to recover rb for 4-byte store.
- */
- frag.insn[n++] = jit_x0_rotli(rb, rb, 32) |
- jit_x1_addi(clob2, y1_br_reg, 0);
- } else { /* =2 */
- frag.insn[n++] =
- jit_x0_addi(clob2, rb, 0) |
- jit_x1_st_add(TREG_SP, clob2, 16);
- for (k = 0; k < 2; k++) {
- frag.insn[n++] =
- jit_x0_shrui(rb, rb, 8) |
- jit_x1_st1_add(clob1, rb,
- UA_FIXUP_ADDR_DELTA);
- }
- frag.insn[n++] =
- jit_x0_addi(rb, clob2, 0) |
- jit_x1_addi(clob2, y1_br_reg, 0);
- }
-
- if (bundle_2_enable)
- frag.insn[n++] = bundle_2;
-
- if (y1_lr) {
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_mfspr(y1_lr_reg,
- SPR_EX_CONTEXT_0_0);
- }
- if (y1_br) {
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_mtspr(SPR_EX_CONTEXT_0_0,
- clob2);
- }
- if (x1_add) {
- frag.insn[n++] =
- jit_x0_addi(ra, ra, x1_add_imm8) |
- jit_x1_ld_add(clob2, clob3, -8);
- } else {
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ld_add(clob2, clob3, -8);
- }
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ld_add(clob1, clob3, -8);
- frag.insn[n++] = jit_x0_fnop() | jit_x1_ld(clob3, clob3);
- frag.insn[n++] = jit_x0_fnop() | jit_x1_iret();
-
- } else {
- /*
- * Generic memory load cases.
- *
- * Alloc space for saveing clob1,2,3 on user's stack.
- * register clob3 points to where clob1 saved, followed
- * by clob2 and 3 from high to low memory.
- */
-
- frag.insn[n++] =
- jit_x0_addi(TREG_SP, TREG_SP, -32) |
- jit_x1_fnop();
- frag.insn[n++] =
- jit_x0_addi(clob3, TREG_SP, 16) |
- jit_x1_st_add(TREG_SP, clob3, 8);
- frag.insn[n++] =
- jit_x0_addi(clob2, ra, 0) |
- jit_x1_st_add(TREG_SP, clob2, 8);
-
- if (y1_br) {
- frag.insn[n++] =
- jit_x0_addi(clob1, y1_br_reg, 0) |
- jit_x1_st_add(TREG_SP, clob1, 16);
- } else {
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_st_add(TREG_SP, clob1, 16);
- }
-
- if (bundle_2_enable)
- frag.insn[n++] = bundle_2;
-
- if (y1_lr) {
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_mfspr(y1_lr_reg,
- SPR_EX_CONTEXT_0_0);
- }
-
- if (y1_br) {
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_mtspr(SPR_EX_CONTEXT_0_0,
- clob1);
- }
-
- frag.insn[n++] =
- jit_x0_addi(clob1, clob2, 7) |
- jit_x1_ldna(rd, clob2);
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ldna(clob1, clob1);
- frag.insn[n++] =
- jit_x0_dblalign(rd, clob1, clob2) |
- jit_x1_ld_add(clob1, clob3, -8);
- if (x1_add) {
- frag.insn[n++] =
- jit_x0_addi(ra, ra, x1_add_imm8) |
- jit_x1_ld_add(clob2, clob3, -8);
- } else {
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ld_add(clob2, clob3, -8);
- }
-
- frag.insn[n++] =
- jit_x0_fnop() |
- jit_x1_ld(clob3, clob3);
-
- if (load_store_size == 4) {
- if (load_store_signed)
- frag.insn[n++] =
- jit_x0_bfexts(
- rd, rd,
- UA_FIXUP_BFEXT_START(4),
- UA_FIXUP_BFEXT_END(4)) |
- jit_x1_fnop();
- else
- frag.insn[n++] =
- jit_x0_bfextu(
- rd, rd,
- UA_FIXUP_BFEXT_START(4),
- UA_FIXUP_BFEXT_END(4)) |
- jit_x1_fnop();
- } else if (load_store_size == 2) {
- if (load_store_signed)
- frag.insn[n++] =
- jit_x0_bfexts(
- rd, rd,
- UA_FIXUP_BFEXT_START(2),
- UA_FIXUP_BFEXT_END(2)) |
- jit_x1_fnop();
- else
- frag.insn[n++] =
- jit_x0_bfextu(
- rd, rd,
- UA_FIXUP_BFEXT_START(2),
- UA_FIXUP_BFEXT_END(2)) |
- jit_x1_fnop();
- }
-
- frag.insn[n++] = jit_x0_fnop() | jit_x1_iret();
- }
-
- /* Max JIT bundle count is 14. */
- WARN_ON(n > 14);
-
- if (!unexpected) {
- int status = 0;
- int idx = (regs->pc >> 3) &
- ((1ULL << (PAGE_SHIFT - UNALIGN_JIT_SHIFT)) - 1);
-
- frag.pc = regs->pc;
- frag.bundle = bundle;
-
- if (unaligned_printk) {
- pr_info("%s/%d, Unalign fixup: pc=%lx bundle=%lx %d %d %d %d %d %d %d %d\n",
- current->comm, current->pid,
- (unsigned long)frag.pc,
- (unsigned long)frag.bundle,
- (int)alias, (int)rd, (int)ra,
- (int)rb, (int)bundle_2_enable,
- (int)y1_lr, (int)y1_br, (int)x1_add);
-
- for (k = 0; k < n; k += 2)
- pr_info("[%d] %016llx %016llx\n",
- k, (unsigned long long)frag.insn[k],
- (unsigned long long)frag.insn[k+1]);
- }
-
- /* Swap bundle byte order for big endian sys. */
-#ifdef __BIG_ENDIAN
- frag.bundle = GX_INSN_BSWAP(frag.bundle);
- for (k = 0; k < n; k++)
- frag.insn[k] = GX_INSN_BSWAP(frag.insn[k]);
-#endif /* __BIG_ENDIAN */
-
- status = copy_to_user((void __user *)&jit_code_area[idx],
- &frag, sizeof(frag));
- if (status) {
- /* Fail to copy JIT into user land. send SIGSEGV. */
- siginfo_t info;
-
- clear_siginfo(&info);
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_MAPERR;
- info.si_addr = (void __user *)&jit_code_area[idx];
-
- pr_warn("Unalign fixup: pid=%d %s jit_code_area=%llx\n",
- current->pid, current->comm,
- (unsigned long long)&jit_code_area[idx]);
-
- trace_unhandled_signal("segfault in unalign fixup",
- regs,
- (unsigned long)info.si_addr,
- SIGSEGV);
- force_sig_info(info.si_signo, &info, current);
- return;
- }
-
-
- /* Do a cheaper increment, not accurate. */
- unaligned_fixup_count++;
- __flush_icache_range((unsigned long)&jit_code_area[idx],
- (unsigned long)&jit_code_area[idx] +
- sizeof(frag));
-
- /* Setup SPR_EX_CONTEXT_0_0/1 for returning to user program.*/
- __insn_mtspr(SPR_EX_CONTEXT_0_0, regs->pc + 8);
- __insn_mtspr(SPR_EX_CONTEXT_0_1, PL_ICS_EX1(USER_PL, 0));
-
- /* Modify pc at the start of new JIT. */
- regs->pc = (unsigned long)&jit_code_area[idx].insn[0];
- /* Set ICS in SPR_EX_CONTEXT_K_1. */
- regs->ex1 = PL_ICS_EX1(USER_PL, 1);
- }
-}
-
-
-/*
- * C function to generate unalign data JIT. Called from unalign data
- * interrupt handler.
- *
- * First check if unalign fix is disabled or exception did not not come from
- * user space or sp register points to unalign address, if true, generate a
- * SIGBUS. Then map a page into user space as JIT area if it is not mapped
- * yet. Genenerate JIT code by calling jit_bundle_gen(). After that return
- * back to exception handler.
- *
- * The exception handler will "iret" to new generated JIT code after
- * restoring caller saved registers. In theory, the JIT code will perform
- * another "iret" to resume user's program.
- */
-
-void do_unaligned(struct pt_regs *regs, int vecnum)
-{
- tilegx_bundle_bits __user *pc;
- tilegx_bundle_bits bundle;
- struct thread_info *info = current_thread_info();
- int align_ctl;
-
- /* Checks the per-process unaligned JIT flags */
- align_ctl = unaligned_fixup;
- switch (task_thread_info(current)->align_ctl) {
- case PR_UNALIGN_NOPRINT:
- align_ctl = 1;
- break;
- case PR_UNALIGN_SIGBUS:
- align_ctl = 0;
- break;
- }
-
- /* Enable iterrupt in order to access user land. */
- local_irq_enable();
-
- /*
- * The fault came from kernel space. Two choices:
- * (a) unaligned_fixup < 1, we will first call get/put_user fixup
- * to return -EFAULT. If no fixup, simply panic the kernel.
- * (b) unaligned_fixup >=1, we will try to fix the unaligned access
- * if it was triggered by get_user/put_user() macros. Panic the
- * kernel if it is not fixable.
- */
-
- if (EX1_PL(regs->ex1) != USER_PL) {
-
- if (align_ctl < 1) {
- unaligned_fixup_count++;
- /* If exception came from kernel, try fix it up. */
- if (fixup_exception(regs)) {
- if (unaligned_printk)
- pr_info("Unalign fixup: %d %llx @%llx\n",
- (int)unaligned_fixup,
- (unsigned long long)regs->ex1,
- (unsigned long long)regs->pc);
- } else {
- /* Not fixable. Go panic. */
- panic("Unalign exception in Kernel. pc=%lx",
- regs->pc);
- }
- } else {
- /*
- * Try to fix the exception. If we can't, panic the
- * kernel.
- */
- bundle = GX_INSN_BSWAP(
- *((tilegx_bundle_bits *)(regs->pc)));
- jit_bundle_gen(regs, bundle, align_ctl);
- }
- return;
- }
-
- /*
- * Fault came from user with ICS or stack is not aligned.
- * If so, we will trigger SIGBUS.
- */
- if ((regs->sp & 0x7) || (regs->ex1) || (align_ctl < 0)) {
- siginfo_t info;
-
- clear_siginfo(&info);
- info.si_signo = SIGBUS;
- info.si_code = BUS_ADRALN;
- info.si_addr = (unsigned char __user *)0;
-
- if (unaligned_printk)
- pr_info("Unalign fixup: %d %llx @%llx\n",
- (int)unaligned_fixup,
- (unsigned long long)regs->ex1,
- (unsigned long long)regs->pc);
-
- unaligned_fixup_count++;
-
- trace_unhandled_signal("unaligned fixup trap", regs, 0, SIGBUS);
- force_sig_info(info.si_signo, &info, current);
- return;
- }
-
-
- /* Read the bundle caused the exception! */
- pc = (tilegx_bundle_bits __user *)(regs->pc);
- if (get_user(bundle, pc) != 0) {
- /* Probably never be here since pc is valid user address.*/
- siginfo_t info;
-
- clear_siginfo(&info);
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_MAPERR;
- info.si_addr = (void __user *)pc;
-
- pr_err("Couldn't read instruction at %p trying to step\n", pc);
- trace_unhandled_signal("segfault in unalign fixup", regs,
- (unsigned long)info.si_addr, SIGSEGV);
- force_sig_info(info.si_signo, &info, current);
- return;
- }
-
- if (!info->unalign_jit_base) {
- void __user *user_page;
-
- /*
- * Allocate a page in userland.
- * For 64-bit processes we try to place the mapping far
- * from anything else that might be going on (specifically
- * 64 GB below the top of the user address space). If it
- * happens not to be possible to put it there, it's OK;
- * the kernel will choose another location and we'll
- * remember it for later.
- */
- if (is_compat_task())
- user_page = NULL;
- else
- user_page = (void __user *)(TASK_SIZE - (1UL << 36)) +
- (current->pid << PAGE_SHIFT);
-
- user_page = (void __user *) vm_mmap(NULL,
- (unsigned long)user_page,
- PAGE_SIZE,
- PROT_EXEC | PROT_READ |
- PROT_WRITE,
-#ifdef CONFIG_HOMECACHE
- MAP_CACHE_HOME_TASK |
-#endif
- MAP_PRIVATE |
- MAP_ANONYMOUS,
- 0);
-
- if (IS_ERR((void __force *)user_page)) {
- pr_err("Out of kernel pages trying do_mmap\n");
- return;
- }
-
- /* Save the address in the thread_info struct */
- info->unalign_jit_base = user_page;
- if (unaligned_printk)
- pr_info("Unalign bundle: %d:%d, allocate page @%llx\n",
- raw_smp_processor_id(), current->pid,
- (unsigned long long)user_page);
- }
-
- /* Generate unalign JIT */
- jit_bundle_gen(regs, GX_INSN_BSWAP(bundle), align_ctl);
-}
-
-#endif /* __tilegx__ */
diff --git a/arch/tile/kernel/usb.c b/arch/tile/kernel/usb.c
deleted file mode 100644
index 9f1e05e12255..000000000000
--- a/arch/tile/kernel/usb.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Register the Tile-Gx USB interfaces as platform devices.
- *
- * The actual USB driver is just some glue (in
- * drivers/usb/host/[eo]hci-tilegx.c) which makes the registers available
- * to the standard kernel EHCI and OHCI drivers.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/usb/tilegx.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/types.h>
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-#define USB_HOST_DEF(unit, type, dmamask) \
- static struct \
- tilegx_usb_platform_data tilegx_usb_platform_data_ ## type ## \
- hci ## unit = { \
- .dev_index = unit, \
- }; \
- \
- static struct platform_device tilegx_usb_ ## type ## hci ## unit = { \
- .name = "tilegx-" #type "hci", \
- .id = unit, \
- .dev = { \
- .dma_mask = dmamask, \
- .coherent_dma_mask = DMA_BIT_MASK(32), \
- .platform_data = \
- &tilegx_usb_platform_data_ ## type ## hci ## \
- unit, \
- }, \
- };
-
-USB_HOST_DEF(0, e, &ehci_dmamask)
-USB_HOST_DEF(0, o, NULL)
-USB_HOST_DEF(1, e, &ehci_dmamask)
-USB_HOST_DEF(1, o, NULL)
-
-#undef USB_HOST_DEF
-
-static struct platform_device *tilegx_usb_devices[] __initdata = {
- &tilegx_usb_ehci0,
- &tilegx_usb_ehci1,
- &tilegx_usb_ohci0,
- &tilegx_usb_ohci1,
-};
-
-/** Add our set of possible USB devices. */
-static int __init tilegx_usb_init(void)
-{
- platform_add_devices(tilegx_usb_devices,
- ARRAY_SIZE(tilegx_usb_devices));
-
- return 0;
-}
-arch_initcall(tilegx_usb_init);
diff --git a/arch/tile/kernel/vdso.c b/arch/tile/kernel/vdso.c
deleted file mode 100644
index 5bc51d7dfdcb..000000000000
--- a/arch/tile/kernel/vdso.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/binfmts.h>
-#include <linux/compat.h>
-#include <linux/elf.h>
-#include <linux/mm.h>
-#include <linux/pagemap.h>
-
-#include <asm/vdso.h>
-#include <asm/mman.h>
-#include <asm/sections.h>
-
-#include <arch/sim.h>
-
-/* The alignment of the vDSO. */
-#define VDSO_ALIGNMENT PAGE_SIZE
-
-
-static unsigned int vdso_pages;
-static struct page **vdso_pagelist;
-
-#ifdef CONFIG_COMPAT
-static unsigned int vdso32_pages;
-static struct page **vdso32_pagelist;
-#endif
-static int vdso_ready;
-
-/*
- * The vdso data page.
- */
-static union {
- struct vdso_data data;
- u8 page[PAGE_SIZE];
-} vdso_data_store __page_aligned_data;
-
-struct vdso_data *vdso_data = &vdso_data_store.data;
-
-static unsigned int __read_mostly vdso_enabled = 1;
-
-static struct page **vdso_setup(void *vdso_kbase, unsigned int pages)
-{
- int i;
- struct page **pagelist;
-
- pagelist = kzalloc(sizeof(struct page *) * (pages + 1), GFP_KERNEL);
- BUG_ON(pagelist == NULL);
- for (i = 0; i < pages - 1; i++) {
- struct page *pg = virt_to_page(vdso_kbase + i*PAGE_SIZE);
- ClearPageReserved(pg);
- pagelist[i] = pg;
- }
- pagelist[pages - 1] = virt_to_page(vdso_data);
- pagelist[pages] = NULL;
-
- return pagelist;
-}
-
-static int __init vdso_init(void)
-{
- int data_pages = sizeof(vdso_data_store) >> PAGE_SHIFT;
-
- /*
- * We can disable vDSO support generally, but we need to retain
- * one page to support the two-bundle (16-byte) rt_sigreturn path.
- */
- if (!vdso_enabled) {
- size_t offset = (unsigned long)&__vdso_rt_sigreturn;
- static struct page *sigret_page;
- sigret_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
- BUG_ON(sigret_page == NULL);
- vdso_pagelist = &sigret_page;
- vdso_pages = 1;
- BUG_ON(offset >= PAGE_SIZE);
- memcpy(page_address(sigret_page) + offset,
- vdso_start + offset, 16);
-#ifdef CONFIG_COMPAT
- vdso32_pages = vdso_pages;
- vdso32_pagelist = vdso_pagelist;
-#endif
- vdso_ready = 1;
- return 0;
- }
-
- vdso_pages = (vdso_end - vdso_start) >> PAGE_SHIFT;
- vdso_pages += data_pages;
- vdso_pagelist = vdso_setup(vdso_start, vdso_pages);
-
-#ifdef CONFIG_COMPAT
- vdso32_pages = (vdso32_end - vdso32_start) >> PAGE_SHIFT;
- vdso32_pages += data_pages;
- vdso32_pagelist = vdso_setup(vdso32_start, vdso32_pages);
-#endif
-
- smp_wmb();
- vdso_ready = 1;
-
- return 0;
-}
-arch_initcall(vdso_init);
-
-const char *arch_vma_name(struct vm_area_struct *vma)
-{
- if (vma->vm_mm && vma->vm_start == VDSO_BASE)
- return "[vdso]";
-#ifndef __tilegx__
- if (vma->vm_start == MEM_USER_INTRPT)
- return "[intrpt]";
-#endif
- return NULL;
-}
-
-int setup_vdso_pages(void)
-{
- struct page **pagelist;
- unsigned long pages;
- struct mm_struct *mm = current->mm;
- unsigned long vdso_base = 0;
- int retval = 0;
-
- if (!vdso_ready)
- return 0;
-
- mm->context.vdso_base = 0;
-
- pagelist = vdso_pagelist;
- pages = vdso_pages;
-#ifdef CONFIG_COMPAT
- if (is_compat_task()) {
- pagelist = vdso32_pagelist;
- pages = vdso32_pages;
- }
-#endif
-
- /*
- * vDSO has a problem and was disabled, just don't "enable" it for the
- * process.
- */
- if (pages == 0)
- return 0;
-
- vdso_base = get_unmapped_area(NULL, vdso_base,
- (pages << PAGE_SHIFT) +
- ((VDSO_ALIGNMENT - 1) & PAGE_MASK),
- 0, 0);
- if (IS_ERR_VALUE(vdso_base)) {
- retval = vdso_base;
- return retval;
- }
-
- /* Add required alignment. */
- vdso_base = ALIGN(vdso_base, VDSO_ALIGNMENT);
-
- /*
- * Put vDSO base into mm struct. We need to do this before calling
- * install_special_mapping or the perf counter mmap tracking code
- * will fail to recognise it as a vDSO (since arch_vma_name fails).
- */
- mm->context.vdso_base = vdso_base;
-
- /*
- * our vma flags don't have VM_WRITE so by default, the process isn't
- * allowed to write those pages.
- * gdb can break that with ptrace interface, and thus trigger COW on
- * those pages but it's then your responsibility to never do that on
- * the "data" page of the vDSO or you'll stop getting kernel updates
- * and your nice userland gettimeofday will be totally dead.
- * It's fine to use that for setting breakpoints in the vDSO code
- * pages though
- */
- retval = install_special_mapping(mm, vdso_base,
- pages << PAGE_SHIFT,
- VM_READ|VM_EXEC |
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC,
- pagelist);
- if (retval)
- mm->context.vdso_base = 0;
-
- return retval;
-}
-
-static __init int vdso_func(char *s)
-{
- return kstrtouint(s, 0, &vdso_enabled);
-}
-__setup("vdso=", vdso_func);
diff --git a/arch/tile/kernel/vdso/Makefile b/arch/tile/kernel/vdso/Makefile
deleted file mode 100644
index b596a7396382..000000000000
--- a/arch/tile/kernel/vdso/Makefile
+++ /dev/null
@@ -1,117 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-# Symbols present in the vdso
-vdso-syms = rt_sigreturn gettimeofday
-
-# Files to link into the vdso
-obj-vdso = $(patsubst %, v%.o, $(vdso-syms))
-
-# Build rules
-targets := $(obj-vdso) vdso.so vdso.so.dbg vdso.lds vdso-dummy.o
-obj-vdso := $(addprefix $(obj)/, $(obj-vdso))
-
-# vdso32 is only for tilegx -m32 compat task.
-VDSO32-$(CONFIG_COMPAT) := y
-
-obj-y += vdso.o vdso-syms.o
-obj-$(VDSO32-y) += vdso32.o
-CPPFLAGS_vdso.lds += -P -C -U$(ARCH)
-
-# vDSO code runs in userspace and -pg doesn't help with profiling anyway.
-CFLAGS_REMOVE_vdso.o = -pg
-CFLAGS_REMOVE_vdso32.o = -pg
-CFLAGS_REMOVE_vrt_sigreturn.o = -pg
-CFLAGS_REMOVE_vrt_sigreturn32.o = -pg
-CFLAGS_REMOVE_vgettimeofday.o = -pg
-CFLAGS_REMOVE_vgettimeofday32.o = -pg
-
-ifdef CONFIG_FEEDBACK_COLLECT
-# vDSO code runs in userspace, not collecting feedback data.
-CFLAGS_REMOVE_vdso.o = -ffeedback-generate
-CFLAGS_REMOVE_vdso32.o = -ffeedback-generate
-CFLAGS_REMOVE_vrt_sigreturn.o = -ffeedback-generate
-CFLAGS_REMOVE_vrt_sigreturn32.o = -ffeedback-generate
-CFLAGS_REMOVE_vgettimeofday.o = -ffeedback-generate
-CFLAGS_REMOVE_vgettimeofday32.o = -ffeedback-generate
-endif
-
-# Disable gcov profiling for VDSO code
-GCOV_PROFILE := n
-
-# Force dependency
-$(obj)/vdso.o: $(obj)/vdso.so
-
-# link rule for the .so file, .lds has to be first
-SYSCFLAGS_vdso.so.dbg = $(c_flags)
-$(obj)/vdso.so.dbg: $(src)/vdso.lds $(obj-vdso) FORCE
- $(call if_changed,vdsold)
-
-# We also create a special relocatable object that should mirror the symbol
-# table and layout of the linked DSO. With ld -R we can then refer to
-# these symbols in the kernel code rather than hand-coded addresses.
-
-SYSCFLAGS_vdso.so.dbg = -shared -s -Wl,-soname=linux-vdso.so.1 \
- $(call cc-ldoption, -Wl$(comma)--hash-style=both)
-SYSCFLAGS_vdso_dummy.o = -r
-$(obj)/vdso-dummy.o: $(src)/vdso.lds $(obj)/vrt_sigreturn.o FORCE
- $(call if_changed,vdsold)
-
-LDFLAGS_vdso-syms.o := -r -R
-$(obj)/vdso-syms.o: $(obj)/vdso-dummy.o FORCE
- $(call if_changed,ld)
-
-# strip rule for the .so file
-$(obj)/%.so: OBJCOPYFLAGS := -S
-$(obj)/%.so: $(obj)/%.so.dbg FORCE
- $(call if_changed,objcopy)
-
-# actual build commands
-# The DSO images are built using a special linker script
-# Add -lgcc so tilepro gets static muldi3 and lshrdi3 definitions.
-# Make sure only to export the intended __vdso_xxx symbol offsets.
-quiet_cmd_vdsold = VDSOLD $@
- cmd_vdsold = $(CC) $(KCFLAGS) -nostdlib $(SYSCFLAGS_$(@F)) \
- -Wl,-T,$(filter-out FORCE,$^) -o $@.tmp -lgcc && \
- $(CROSS_COMPILE)objcopy \
- $(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@
-
-# install commands for the unstripped file
-quiet_cmd_vdso_install = INSTALL $@
- cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@
-
-vdso.so: $(obj)/vdso.so.dbg
- @mkdir -p $(MODLIB)/vdso
- $(call cmd,vdso_install)
-
-vdso32.so: $(obj)/vdso32.so.dbg
- $(call cmd,vdso_install)
-
-vdso_install: vdso.so
-vdso32_install: vdso32.so
-
-
-KBUILD_AFLAGS_32 := $(filter-out -m64,$(KBUILD_AFLAGS))
-KBUILD_AFLAGS_32 += -m32 -s
-KBUILD_CFLAGS_32 := $(filter-out -m64,$(KBUILD_CFLAGS))
-KBUILD_CFLAGS_32 += -m32 -fPIC -shared
-
-obj-vdso32 = $(patsubst %, v%32.o, $(vdso-syms))
-
-targets += $(obj-vdso32) vdso32.so vdso32.so.dbg
-obj-vdso32 := $(addprefix $(obj)/, $(obj-vdso32))
-
-$(obj-vdso32:%=%): KBUILD_AFLAGS = $(KBUILD_AFLAGS_32)
-$(obj-vdso32:%=%): KBUILD_CFLAGS = $(KBUILD_CFLAGS_32)
-
-$(obj)/vgettimeofday32.o: $(obj)/vgettimeofday.c FORCE
- $(call if_changed_rule,cc_o_c)
-
-$(obj)/vrt_sigreturn32.o: $(obj)/vrt_sigreturn.S FORCE
- $(call if_changed,as_o_S)
-
-# Force dependency
-$(obj)/vdso32.o: $(obj)/vdso32.so
-
-SYSCFLAGS_vdso32.so.dbg = -m32 -shared -s -Wl,-soname=linux-vdso32.so.1 \
- $(call cc-ldoption, -Wl$(comma)--hash-style=both)
-$(obj)/vdso32.so.dbg: $(src)/vdso.lds $(obj-vdso32) FORCE
- $(call if_changed,vdsold)
diff --git a/arch/tile/kernel/vdso/vdso.S b/arch/tile/kernel/vdso/vdso.S
deleted file mode 100644
index 3467adb41630..000000000000
--- a/arch/tile/kernel/vdso/vdso.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <asm/page.h>
-
- __PAGE_ALIGNED_DATA
-
- .global vdso_start, vdso_end
- .align PAGE_SIZE
-vdso_start:
- .incbin "arch/tile/kernel/vdso/vdso.so"
- .align PAGE_SIZE
-vdso_end:
-
- .previous
diff --git a/arch/tile/kernel/vdso/vdso.lds.S b/arch/tile/kernel/vdso/vdso.lds.S
deleted file mode 100644
index 731529f3f06f..000000000000
--- a/arch/tile/kernel/vdso/vdso.lds.S
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#define VDSO_VERSION_STRING LINUX_2.6
-
-
-OUTPUT_ARCH(tile)
-
-/* The ELF entry point can be used to set the AT_SYSINFO value. */
-ENTRY(__vdso_rt_sigreturn);
-
-
-SECTIONS
-{
- . = SIZEOF_HEADERS;
-
- .hash : { *(.hash) } :text
- .gnu.hash : { *(.gnu.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .gnu.version : { *(.gnu.version) }
- .gnu.version_d : { *(.gnu.version_d) }
- .gnu.version_r : { *(.gnu.version_r) }
-
- .note : { *(.note.*) } :text :note
- .dynamic : { *(.dynamic) } :text :dynamic
-
- .eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr
- .eh_frame : { KEEP (*(.eh_frame)) } :text
-
- .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
-
- /*
- * This linker script is used both with -r and with -shared.
- * For the layouts to match, we need to skip more than enough
- * space for the dynamic symbol table et al. If this amount
- * is insufficient, ld -shared will barf. Just increase it here.
- */
- . = 0x1000;
- .text : { *(.text .text.*) } :text
-
- .data : {
- *(.got.plt) *(.got)
- *(.data .data.* .gnu.linkonce.d.*)
- *(.dynbss)
- *(.bss .bss.* .gnu.linkonce.b.*)
- }
-}
-
-
-/*
- * We must supply the ELF program headers explicitly to get just one
- * PT_LOAD segment, and set the flags explicitly to make segments read-only.
- */
-PHDRS
-{
- text PT_LOAD FLAGS(5) FILEHDR PHDRS; /* PF_R|PF_X */
- dynamic PT_DYNAMIC FLAGS(4); /* PF_R */
- note PT_NOTE FLAGS(4); /* PF_R */
- eh_frame_hdr PT_GNU_EH_FRAME;
-}
-
-
-/*
- * This controls what userland symbols we export from the vDSO.
- */
-VERSION
-{
- VDSO_VERSION_STRING {
- global:
- __vdso_rt_sigreturn;
- __vdso_gettimeofday;
- gettimeofday;
- __vdso_clock_gettime;
- clock_gettime;
- local:*;
- };
-}
diff --git a/arch/tile/kernel/vdso/vdso32.S b/arch/tile/kernel/vdso/vdso32.S
deleted file mode 100644
index 1d1ac3257e11..000000000000
--- a/arch/tile/kernel/vdso/vdso32.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <asm/page.h>
-
- __PAGE_ALIGNED_DATA
-
- .global vdso32_start, vdso32_end
- .align PAGE_SIZE
-vdso32_start:
- .incbin "arch/tile/kernel/vdso/vdso32.so"
- .align PAGE_SIZE
-vdso32_end:
-
- .previous
diff --git a/arch/tile/kernel/vdso/vgettimeofday.c b/arch/tile/kernel/vdso/vgettimeofday.c
deleted file mode 100644
index e63310c49742..000000000000
--- a/arch/tile/kernel/vdso/vgettimeofday.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#define VDSO_BUILD /* avoid some shift warnings for -m32 in <asm/page.h> */
-#include <linux/time.h>
-#include <asm/timex.h>
-#include <asm/unistd.h>
-#include <asm/vdso.h>
-
-#if CHIP_HAS_SPLIT_CYCLE()
-static inline cycles_t get_cycles_inline(void)
-{
- unsigned int high = __insn_mfspr(SPR_CYCLE_HIGH);
- unsigned int low = __insn_mfspr(SPR_CYCLE_LOW);
- unsigned int high2 = __insn_mfspr(SPR_CYCLE_HIGH);
-
- while (unlikely(high != high2)) {
- low = __insn_mfspr(SPR_CYCLE_LOW);
- high = high2;
- high2 = __insn_mfspr(SPR_CYCLE_HIGH);
- }
-
- return (((cycles_t)high) << 32) | low;
-}
-#define get_cycles get_cycles_inline
-#endif
-
-struct syscall_return_value {
- long value;
- long error;
-};
-
-/*
- * Find out the vDSO data page address in the process address space.
- */
-inline unsigned long get_datapage(void)
-{
- unsigned long ret;
-
- /* vdso data page located in the 2nd vDSO page. */
- asm volatile ("lnk %0" : "=r"(ret));
- ret &= ~(PAGE_SIZE - 1);
- ret += PAGE_SIZE;
-
- return ret;
-}
-
-static inline u64 vgetsns(struct vdso_data *vdso)
-{
- return ((get_cycles() - vdso->cycle_last) & vdso->mask) * vdso->mult;
-}
-
-static inline int do_realtime(struct vdso_data *vdso, struct timespec *ts)
-{
- unsigned count;
- u64 ns;
-
- do {
- count = raw_read_seqcount_begin(&vdso->tb_seq);
- ts->tv_sec = vdso->wall_time_sec;
- ns = vdso->wall_time_snsec;
- ns += vgetsns(vdso);
- ns >>= vdso->shift;
- } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
-
- ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
- ts->tv_nsec = ns;
-
- return 0;
-}
-
-static inline int do_monotonic(struct vdso_data *vdso, struct timespec *ts)
-{
- unsigned count;
- u64 ns;
-
- do {
- count = raw_read_seqcount_begin(&vdso->tb_seq);
- ts->tv_sec = vdso->monotonic_time_sec;
- ns = vdso->monotonic_time_snsec;
- ns += vgetsns(vdso);
- ns >>= vdso->shift;
- } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
-
- ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
- ts->tv_nsec = ns;
-
- return 0;
-}
-
-static inline int do_realtime_coarse(struct vdso_data *vdso,
- struct timespec *ts)
-{
- unsigned count;
-
- do {
- count = raw_read_seqcount_begin(&vdso->tb_seq);
- ts->tv_sec = vdso->wall_time_coarse_sec;
- ts->tv_nsec = vdso->wall_time_coarse_nsec;
- } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
-
- return 0;
-}
-
-static inline int do_monotonic_coarse(struct vdso_data *vdso,
- struct timespec *ts)
-{
- unsigned count;
-
- do {
- count = raw_read_seqcount_begin(&vdso->tb_seq);
- ts->tv_sec = vdso->monotonic_time_coarse_sec;
- ts->tv_nsec = vdso->monotonic_time_coarse_nsec;
- } while (unlikely(read_seqcount_retry(&vdso->tb_seq, count)));
-
- return 0;
-}
-
-struct syscall_return_value __vdso_gettimeofday(struct timeval *tv,
- struct timezone *tz)
-{
- struct syscall_return_value ret = { 0, 0 };
- unsigned count;
- struct vdso_data *vdso = (struct vdso_data *)get_datapage();
-
- /* The use of the timezone is obsolete, normally tz is NULL. */
- if (unlikely(tz != NULL)) {
- do {
- count = raw_read_seqcount_begin(&vdso->tz_seq);
- tz->tz_minuteswest = vdso->tz_minuteswest;
- tz->tz_dsttime = vdso->tz_dsttime;
- } while (unlikely(read_seqcount_retry(&vdso->tz_seq, count)));
- }
-
- if (unlikely(tv == NULL))
- return ret;
-
- do_realtime(vdso, (struct timespec *)tv);
- tv->tv_usec /= 1000;
-
- return ret;
-}
-
-int gettimeofday(struct timeval *tv, struct timezone *tz)
- __attribute__((weak, alias("__vdso_gettimeofday")));
-
-static struct syscall_return_value vdso_fallback_gettime(long clock,
- struct timespec *ts)
-{
- struct syscall_return_value ret;
- __asm__ __volatile__ (
- "swint1"
- : "=R00" (ret.value), "=R01" (ret.error)
- : "R10" (__NR_clock_gettime), "R00" (clock), "R01" (ts)
- : "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r11", "r12", "r13", "r14", "r15",
- "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "r26", "r27", "r28", "r29", "memory");
- return ret;
-}
-
-struct syscall_return_value __vdso_clock_gettime(clockid_t clock,
- struct timespec *ts)
-{
- struct vdso_data *vdso = (struct vdso_data *)get_datapage();
- struct syscall_return_value ret = { 0, 0 };
-
- switch (clock) {
- case CLOCK_REALTIME:
- do_realtime(vdso, ts);
- return ret;
- case CLOCK_MONOTONIC:
- do_monotonic(vdso, ts);
- return ret;
- case CLOCK_REALTIME_COARSE:
- do_realtime_coarse(vdso, ts);
- return ret;
- case CLOCK_MONOTONIC_COARSE:
- do_monotonic_coarse(vdso, ts);
- return ret;
- default:
- return vdso_fallback_gettime(clock, ts);
- }
-}
-
-int clock_gettime(clockid_t clock, struct timespec *ts)
- __attribute__((weak, alias("__vdso_clock_gettime")));
diff --git a/arch/tile/kernel/vdso/vrt_sigreturn.S b/arch/tile/kernel/vdso/vrt_sigreturn.S
deleted file mode 100644
index 6326caf4a039..000000000000
--- a/arch/tile/kernel/vdso/vrt_sigreturn.S
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2012 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/linkage.h>
-#include <arch/abi.h>
-#include <asm/unistd.h>
-
-/*
- * Note that libc has a copy of this function that it uses to compare
- * against the PC when a stack backtrace ends, so if this code is
- * changed, the libc implementation(s) should also be updated.
- */
-ENTRY(__vdso_rt_sigreturn)
- moveli TREG_SYSCALL_NR_NAME, __NR_rt_sigreturn
- swint1
- /* We don't use ENDPROC to avoid tagging this symbol as FUNC,
- * which confuses the perf tool.
- */
- END(__vdso_rt_sigreturn)
diff --git a/arch/tile/kernel/vmlinux.lds.S b/arch/tile/kernel/vmlinux.lds.S
deleted file mode 100644
index 3558d981e336..000000000000
--- a/arch/tile/kernel/vmlinux.lds.S
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <asm-generic/vmlinux.lds.h>
-#include <asm/page.h>
-#include <asm/cache.h>
-#include <asm/thread_info.h>
-#include <hv/hypervisor.h>
-
-/* Text loads starting from the supervisor interrupt vector address. */
-#define TEXT_OFFSET MEM_SV_START
-
-OUTPUT_ARCH(tile)
-ENTRY(_start)
-jiffies = jiffies_64;
-
-PHDRS
-{
- intrpt PT_LOAD ;
- text PT_LOAD ;
- data PT_LOAD ;
-}
-SECTIONS
-{
- /* Text is loaded with a different VA than data; start with text. */
- #undef LOAD_OFFSET
- #define LOAD_OFFSET TEXT_OFFSET
-
- /* Interrupt vectors */
- .intrpt (LOAD_OFFSET) : AT ( 0 ) /* put at the start of physical memory */
- {
- _text = .;
- *(.intrpt)
- } :intrpt =0
-
- /* Hypervisor call vectors */
- . = ALIGN(0x10000);
- .hvglue : AT (ADDR(.hvglue) - LOAD_OFFSET) {
- *(.hvglue)
- } :NONE
-
- /* Now the real code */
- . = ALIGN(0x20000);
- _stext = .;
- .text : AT (ADDR(.text) - LOAD_OFFSET) {
- HEAD_TEXT
- SCHED_TEXT
- CPUIDLE_TEXT
- LOCK_TEXT
- KPROBES_TEXT
- IRQENTRY_TEXT
- SOFTIRQENTRY_TEXT
- __fix_text_end = .; /* tile-cpack won't rearrange before this */
- ALIGN_FUNCTION();
- *(.hottext*)
- TEXT_TEXT
- *(.text.*)
- *(.coldtext*)
- *(.fixup)
- *(.gnu.warning)
- } :text =0
- _etext = .;
-
- /* "Init" is divided into two areas with very different virtual addresses. */
- INIT_TEXT_SECTION(PAGE_SIZE)
-
- /*
- * Some things, like the __jump_table, may contain symbol references
- * to __exit text, so include such text in the final image if so.
- * In that case we also override the _einittext from INIT_TEXT_SECTION.
- */
-#ifdef CONFIG_JUMP_LABEL
- .exit.text : {
- EXIT_TEXT
- _einittext = .;
- }
-#endif
-
- /* Now we skip back to PAGE_OFFSET for the data. */
- . = (. - TEXT_OFFSET + PAGE_OFFSET);
- #undef LOAD_OFFSET
- #define LOAD_OFFSET PAGE_OFFSET
-
- . = ALIGN(PAGE_SIZE);
- __init_begin = .;
- INIT_DATA_SECTION(16) :data =0
- PERCPU_SECTION(L2_CACHE_BYTES)
- . = ALIGN(PAGE_SIZE);
- __init_end = .;
-
- _sdata = .; /* Start of data section */
- RO_DATA_SECTION(PAGE_SIZE)
- RW_DATA_SECTION(L2_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
- _edata = .;
-
- EXCEPTION_TABLE(L2_CACHE_BYTES)
- NOTES
-
-
- BSS_SECTION(8, PAGE_SIZE, 1)
- _end = . ;
-
- STABS_DEBUG
- DWARF_DEBUG
-
- DISCARDS
-}
diff --git a/arch/tile/kvm/Kconfig b/arch/tile/kvm/Kconfig
deleted file mode 100644
index efce89a8473b..000000000000
--- a/arch/tile/kvm/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# KVM configuration
-#
-
-source "virt/kvm/Kconfig"
-
-menuconfig VIRTUALIZATION
- bool "Virtualization"
- ---help---
- Say Y here to get to see options for using your Linux host to run
- other operating systems inside virtual machines (guests).
- This option alone does not add any kernel code.
-
- If you say N, all options in this submenu will be skipped and
- disabled.
-
-if VIRTUALIZATION
-
-config KVM
- tristate "Kernel-based Virtual Machine (KVM) support"
- depends on HAVE_KVM && MODULES
- select PREEMPT_NOTIFIERS
- select ANON_INODES
- select SRCU
- ---help---
- Support hosting paravirtualized guest machines.
-
- This module provides access to the hardware capabilities through
- a character device node named /dev/kvm.
-
- To compile this as a module, choose M here: the module
- will be called kvm.
-
- If unsure, say N.
-
-source drivers/vhost/Kconfig
-
-endif # VIRTUALIZATION
diff --git a/arch/tile/lib/Makefile b/arch/tile/lib/Makefile
deleted file mode 100644
index 815a1fdeb2e4..000000000000
--- a/arch/tile/lib/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-#
-# Makefile for TILE-specific library files..
-#
-
-lib-y = cacheflush.o checksum.o cpumask.o delay.o uaccess.o \
- memmove.o memcpy_$(BITS).o memchr_$(BITS).o memset_$(BITS).o \
- strchr_$(BITS).o strlen_$(BITS).o strnlen_$(BITS).o
-
-lib-$(CONFIG_TILEGX) += memcpy_user_64.o
-lib-$(CONFIG_TILEPRO) += atomic_32.o atomic_asm_32.o
-lib-$(CONFIG_SMP) += spinlock_$(BITS).o usercopy_$(BITS).o
-
-obj-$(CONFIG_MODULES) += exports.o
-
-# The finv_buffer_remote() and copy_{to,from}_user() routines can't
-# have -pg added, since they both rely on being leaf functions.
-CFLAGS_REMOVE_cacheflush.o = -pg
-CFLAGS_REMOVE_memcpy_user_64.o = -pg
diff --git a/arch/tile/lib/atomic_32.c b/arch/tile/lib/atomic_32.c
deleted file mode 100644
index f8128800dbf5..000000000000
--- a/arch/tile/lib/atomic_32.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/cache.h>
-#include <linux/delay.h>
-#include <linux/uaccess.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/atomic.h>
-#include <arch/chip.h>
-
-/* This page is remapped on startup to be hash-for-home. */
-int atomic_locks[PAGE_SIZE / sizeof(int)] __page_aligned_bss;
-
-int *__atomic_hashed_lock(volatile void *v)
-{
- /* NOTE: this code must match "sys_cmpxchg" in kernel/intvec_32.S */
- /*
- * Use bits [3, 3 + ATOMIC_HASH_SHIFT) as the lock index.
- * Using mm works here because atomic_locks is page aligned.
- */
- unsigned long ptr = __insn_mm((unsigned long)v >> 1,
- (unsigned long)atomic_locks,
- 2, (ATOMIC_HASH_SHIFT + 2) - 1);
- return (int *)ptr;
-}
-
-#ifdef CONFIG_SMP
-/* Return whether the passed pointer is a valid atomic lock pointer. */
-static int is_atomic_lock(int *p)
-{
- return p >= &atomic_locks[0] && p < &atomic_locks[ATOMIC_HASH_SIZE];
-}
-
-void __atomic_fault_unlock(int *irqlock_word)
-{
- BUG_ON(!is_atomic_lock(irqlock_word));
- BUG_ON(*irqlock_word != 1);
- *irqlock_word = 0;
-}
-
-#endif /* CONFIG_SMP */
-
-static inline int *__atomic_setup(volatile void *v)
-{
- /* Issue a load to the target to bring it into cache. */
- *(volatile int *)v;
- return __atomic_hashed_lock(v);
-}
-
-int _atomic_xchg(int *v, int n)
-{
- return __atomic32_xchg(v, __atomic_setup(v), n).val;
-}
-EXPORT_SYMBOL(_atomic_xchg);
-
-int _atomic_xchg_add(int *v, int i)
-{
- return __atomic32_xchg_add(v, __atomic_setup(v), i).val;
-}
-EXPORT_SYMBOL(_atomic_xchg_add);
-
-int _atomic_xchg_add_unless(int *v, int a, int u)
-{
- /*
- * Note: argument order is switched here since it is easier
- * to use the first argument consistently as the "old value"
- * in the assembly, as is done for _atomic_cmpxchg().
- */
- return __atomic32_xchg_add_unless(v, __atomic_setup(v), u, a).val;
-}
-EXPORT_SYMBOL(_atomic_xchg_add_unless);
-
-int _atomic_cmpxchg(int *v, int o, int n)
-{
- return __atomic32_cmpxchg(v, __atomic_setup(v), o, n).val;
-}
-EXPORT_SYMBOL(_atomic_cmpxchg);
-
-unsigned long _atomic_fetch_or(volatile unsigned long *p, unsigned long mask)
-{
- return __atomic32_fetch_or((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_or);
-
-unsigned long _atomic_fetch_and(volatile unsigned long *p, unsigned long mask)
-{
- return __atomic32_fetch_and((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_and);
-
-unsigned long _atomic_fetch_andn(volatile unsigned long *p, unsigned long mask)
-{
- return __atomic32_fetch_andn((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_andn);
-
-unsigned long _atomic_fetch_xor(volatile unsigned long *p, unsigned long mask)
-{
- return __atomic32_fetch_xor((int *)p, __atomic_setup(p), mask).val;
-}
-EXPORT_SYMBOL(_atomic_fetch_xor);
-
-
-long long _atomic64_xchg(long long *v, long long n)
-{
- return __atomic64_xchg(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_xchg);
-
-long long _atomic64_xchg_add(long long *v, long long i)
-{
- return __atomic64_xchg_add(v, __atomic_setup(v), i);
-}
-EXPORT_SYMBOL(_atomic64_xchg_add);
-
-long long _atomic64_xchg_add_unless(long long *v, long long a, long long u)
-{
- /*
- * Note: argument order is switched here since it is easier
- * to use the first argument consistently as the "old value"
- * in the assembly, as is done for _atomic_cmpxchg().
- */
- return __atomic64_xchg_add_unless(v, __atomic_setup(v), u, a);
-}
-EXPORT_SYMBOL(_atomic64_xchg_add_unless);
-
-long long _atomic64_cmpxchg(long long *v, long long o, long long n)
-{
- return __atomic64_cmpxchg(v, __atomic_setup(v), o, n);
-}
-EXPORT_SYMBOL(_atomic64_cmpxchg);
-
-long long _atomic64_fetch_and(long long *v, long long n)
-{
- return __atomic64_fetch_and(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_fetch_and);
-
-long long _atomic64_fetch_or(long long *v, long long n)
-{
- return __atomic64_fetch_or(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_fetch_or);
-
-long long _atomic64_fetch_xor(long long *v, long long n)
-{
- return __atomic64_fetch_xor(v, __atomic_setup(v), n);
-}
-EXPORT_SYMBOL(_atomic64_fetch_xor);
-
-/*
- * If any of the atomic or futex routines hit a bad address (not in
- * the page tables at kernel PL) this routine is called. The futex
- * routines are never used on kernel space, and the normal atomics and
- * bitops are never used on user space. So a fault on kernel space
- * must be fatal, but a fault on userspace is a futex fault and we
- * need to return -EFAULT. Note that the context this routine is
- * invoked in is the context of the "_atomic_xxx()" routines called
- * by the functions in this file.
- */
-struct __get_user __atomic_bad_address(int __user *addr)
-{
- if (unlikely(!access_ok(VERIFY_WRITE, addr, sizeof(int))))
- panic("Bad address used for kernel atomic op: %p\n", addr);
- return (struct __get_user) { .err = -EFAULT };
-}
-
-
-void __init __init_atomic_per_cpu(void)
-{
- /* Validate power-of-two and "bigger than cpus" assumption */
- BUILD_BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1));
- BUG_ON(ATOMIC_HASH_SIZE < nr_cpu_ids);
-
- /*
- * On TILEPro we prefer to use a single hash-for-home
- * page, since this means atomic operations are less
- * likely to encounter a TLB fault and thus should
- * in general perform faster. You may wish to disable
- * this in situations where few hash-for-home tiles
- * are configured.
- */
- BUG_ON((unsigned long)atomic_locks % PAGE_SIZE != 0);
-
- /* The locks must all fit on one page. */
- BUILD_BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE);
-
- /*
- * We use the page offset of the atomic value's address as
- * an index into atomic_locks, excluding the low 3 bits.
- * That should not produce more indices than ATOMIC_HASH_SIZE.
- */
- BUILD_BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE);
-}
diff --git a/arch/tile/lib/atomic_asm_32.S b/arch/tile/lib/atomic_asm_32.S
deleted file mode 100644
index 94709ab41ed8..000000000000
--- a/arch/tile/lib/atomic_asm_32.S
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Support routines for atomic operations. Each function takes:
- *
- * r0: address to manipulate
- * r1: pointer to atomic lock guarding this operation (for ATOMIC_LOCK_REG)
- * r2: new value to write, or for cmpxchg/add_unless, value to compare against
- * r3: (cmpxchg/xchg_add_unless) new value to write or add;
- * (atomic64 ops) high word of value to write
- * r4/r5: (cmpxchg64/add_unless64) new value to write or add
- *
- * The 32-bit routines return a "struct __get_user" so that the futex code
- * has an opportunity to return -EFAULT to the user if needed.
- * The 64-bit routines just return a "long long" with the value,
- * since they are only used from kernel space and don't expect to fault.
- * Support for 16-bit ops is included in the framework but we don't provide any.
- *
- * Note that the caller is advised to issue a suitable L1 or L2
- * prefetch on the address being manipulated to avoid extra stalls.
- * In addition, the hot path is on two icache lines, and we start with
- * a jump to the second line to make sure they are both in cache so
- * that we never stall waiting on icache fill while holding the lock.
- * (This doesn't work out with most 64-bit ops, since they consume
- * too many bundles, so may take an extra i-cache stall.)
- *
- * These routines set the INTERRUPT_CRITICAL_SECTION bit, just
- * like sys_cmpxchg(), so that NMIs like PERF_COUNT will not interrupt
- * the code, just page faults.
- *
- * If the load or store faults in a way that can be directly fixed in
- * the do_page_fault_ics() handler (e.g. a vmalloc reference) we fix it
- * directly, return to the instruction that faulted, and retry it.
- *
- * If the load or store faults in a way that potentially requires us
- * to release the atomic lock, then retry (e.g. a migrating PTE), we
- * reset the PC in do_page_fault_ics() to the "tns" instruction so
- * that on return we will reacquire the lock and restart the op. We
- * are somewhat overloading the exception_table_entry notion by doing
- * this, since those entries are not normally used for migrating PTEs.
- *
- * If the main page fault handler discovers a bad address, it will see
- * the PC pointing to the "tns" instruction (due to the earlier
- * exception_table_entry processing in do_page_fault_ics), and
- * re-reset the PC to the fault handler, atomic_bad_address(), which
- * effectively takes over from the atomic op and can either return a
- * bad "struct __get_user" (for user addresses) or can just panic (for
- * bad kernel addresses).
- *
- * Note that if the value we would store is the same as what we
- * loaded, we bypass the store. Other platforms with true atomics can
- * make the guarantee that a non-atomic __clear_bit(), for example,
- * can safely race with an atomic test_and_set_bit(); this example is
- * from bit_spinlock.h in slub_lock() / slub_unlock(). We can't do
- * that on Tile since the "atomic" op is really just a
- * read/modify/write, and can race with the non-atomic
- * read/modify/write. However, if we can short-circuit the write when
- * it is not needed, in the atomic case, we avoid the race.
- */
-
-#include <linux/linkage.h>
-#include <asm/atomic_32.h>
-#include <asm/page.h>
-#include <asm/processor.h>
-
- .section .text.atomic,"ax"
-ENTRY(__start_atomic_asm_code)
-
- .macro atomic_op, name, bitwidth, body
- .align 64
-STD_ENTRY_SECTION(__atomic\name, .text.atomic)
- {
- movei r24, 1
- j 4f /* branch to second cache line */
- }
-1: {
- .ifc \bitwidth,16
- lh r22, r0
- .else
- lw r22, r0
- addi r28, r0, 4
- .endif
- }
- .ifc \bitwidth,64
- lw r23, r28
- .endif
- \body /* set r24, and r25 if 64-bit */
- {
- seq r26, r22, r24
- seq r27, r23, r25
- }
- .ifc \bitwidth,64
- bbnst r27, 2f
- .endif
- bbs r26, 3f /* skip write-back if it's the same value */
-2: {
- .ifc \bitwidth,16
- sh r0, r24
- .else
- sw r0, r24
- .endif
- }
- .ifc \bitwidth,64
- sw r28, r25
- .endif
- mf
-3: {
- move r0, r22
- .ifc \bitwidth,64
- move r1, r23
- .else
- move r1, zero
- .endif
- sw ATOMIC_LOCK_REG_NAME, zero
- }
- mtspr INTERRUPT_CRITICAL_SECTION, zero
- jrp lr
-4: {
- move ATOMIC_LOCK_REG_NAME, r1
- mtspr INTERRUPT_CRITICAL_SECTION, r24
- }
-#ifndef CONFIG_SMP
- j 1b /* no atomic locks */
-#else
- {
- tns r21, ATOMIC_LOCK_REG_NAME
- moveli r23, 2048 /* maximum backoff time in cycles */
- }
- {
- bzt r21, 1b /* branch if lock acquired */
- moveli r25, 32 /* starting backoff time in cycles */
- }
-5: mtspr INTERRUPT_CRITICAL_SECTION, zero
- mfspr r26, CYCLE_LOW /* get start point for this backoff */
-6: mfspr r22, CYCLE_LOW /* test to see if we've backed off enough */
- sub r22, r22, r26
- slt r22, r22, r25
- bbst r22, 6b
- {
- mtspr INTERRUPT_CRITICAL_SECTION, r24
- shli r25, r25, 1 /* double the backoff; retry the tns */
- }
- {
- tns r21, ATOMIC_LOCK_REG_NAME
- slt r26, r23, r25 /* is the proposed backoff too big? */
- }
- {
- bzt r21, 1b /* branch if lock acquired */
- mvnz r25, r26, r23
- }
- j 5b
-#endif
- STD_ENDPROC(__atomic\name)
- .ifc \bitwidth,32
- .pushsection __ex_table,"a"
- .align 4
- .word 1b, __atomic\name
- .word 2b, __atomic\name
- .word __atomic\name, __atomic_bad_address
- .popsection
- .endif
- .endm
-
-
-/*
- * Use __atomic32 prefix to avoid collisions with GCC builtin __atomic functions.
- */
-
-atomic_op 32_cmpxchg, 32, "seq r26, r22, r2; { bbns r26, 3f; move r24, r3 }"
-atomic_op 32_xchg, 32, "move r24, r2"
-atomic_op 32_xchg_add, 32, "add r24, r22, r2"
-atomic_op 32_xchg_add_unless, 32, \
- "sne r26, r22, r2; { bbns r26, 3f; add r24, r22, r3 }"
-atomic_op 32_fetch_or, 32, "or r24, r22, r2"
-atomic_op 32_fetch_and, 32, "and r24, r22, r2"
-atomic_op 32_fetch_andn, 32, "nor r2, r2, zero; and r24, r22, r2"
-atomic_op 32_fetch_xor, 32, "xor r24, r22, r2"
-
-atomic_op 64_cmpxchg, 64, "{ seq r26, r22, r2; seq r27, r23, r3 }; \
- { bbns r26, 3f; move r24, r4 }; { bbns r27, 3f; move r25, r5 }"
-atomic_op 64_xchg, 64, "{ move r24, r2; move r25, r3 }"
-atomic_op 64_xchg_add, 64, "{ add r24, r22, r2; add r25, r23, r3 }; \
- slt_u r26, r24, r22; add r25, r25, r26"
-atomic_op 64_xchg_add_unless, 64, \
- "{ sne r26, r22, r2; sne r27, r23, r3 }; \
- { bbns r26, 3f; add r24, r22, r4 }; \
- { bbns r27, 3f; add r25, r23, r5 }; \
- slt_u r26, r24, r22; add r25, r25, r26"
-atomic_op 64_fetch_or, 64, "{ or r24, r22, r2; or r25, r23, r3 }"
-atomic_op 64_fetch_and, 64, "{ and r24, r22, r2; and r25, r23, r3 }"
-atomic_op 64_fetch_xor, 64, "{ xor r24, r22, r2; xor r25, r23, r3 }"
-
- jrp lr /* happy backtracer */
-
-ENTRY(__end_atomic_asm_code)
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
deleted file mode 100644
index c1ebc1065fc1..000000000000
--- a/arch/tile/lib/cacheflush.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/export.h>
-#include <asm/page.h>
-#include <asm/cacheflush.h>
-#include <arch/icache.h>
-#include <arch/spr_def.h>
-
-
-void __flush_icache_range(unsigned long start, unsigned long end)
-{
- invalidate_icache((const void *)start, end - start, PAGE_SIZE);
-}
-
-
-/* Force a load instruction to issue. */
-static inline void force_load(char *p)
-{
- *(volatile char *)p;
-}
-
-/*
- * Flush and invalidate a VA range that is homed remotely on a single
- * core (if "!hfh") or homed via hash-for-home (if "hfh"), waiting
- * until the memory controller holds the flushed values.
- */
-void __attribute__((optimize("omit-frame-pointer")))
-finv_buffer_remote(void *buffer, size_t size, int hfh)
-{
- char *p, *base;
- size_t step_size, load_count;
-
- /*
- * On TILEPro the striping granularity is a fixed 8KB; on
- * TILE-Gx it is configurable, and we rely on the fact that
- * the hypervisor always configures maximum striping, so that
- * bits 9 and 10 of the PA are part of the stripe function, so
- * every 512 bytes we hit a striping boundary.
- *
- */
-#ifdef __tilegx__
- const unsigned long STRIPE_WIDTH = 512;
-#else
- const unsigned long STRIPE_WIDTH = 8192;
-#endif
-
-#ifdef __tilegx__
- /*
- * On TILE-Gx, we must disable the dstream prefetcher before doing
- * a cache flush; otherwise, we could end up with data in the cache
- * that we don't want there. Note that normally we'd do an mf
- * after the SPR write to disabling the prefetcher, but we do one
- * below, before any further loads, so there's no need to do it
- * here.
- */
- uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
- __insn_mtspr(SPR_DSTREAM_PF, 0);
-#endif
-
- /*
- * Flush and invalidate the buffer out of the local L1/L2
- * and request the home cache to flush and invalidate as well.
- */
- __finv_buffer(buffer, size);
-
- /*
- * Wait for the home cache to acknowledge that it has processed
- * all the flush-and-invalidate requests. This does not mean
- * that the flushed data has reached the memory controller yet,
- * but it does mean the home cache is processing the flushes.
- */
- __insn_mf();
-
- /*
- * Issue a load to the last cache line, which can't complete
- * until all the previously-issued flushes to the same memory
- * controller have also completed. If we weren't striping
- * memory, that one load would be sufficient, but since we may
- * be, we also need to back up to the last load issued to
- * another memory controller, which would be the point where
- * we crossed a "striping" boundary (the granularity of striping
- * across memory controllers). Keep backing up and doing this
- * until we are before the beginning of the buffer, or have
- * hit all the controllers.
- *
- * If we are flushing a hash-for-home buffer, it's even worse.
- * Each line may be homed on a different tile, and each tile
- * may have up to four lines that are on different
- * controllers. So as we walk backwards, we have to touch
- * enough cache lines to satisfy these constraints. In
- * practice this ends up being close enough to "load from
- * every cache line on a full memory stripe on each
- * controller" that we simply do that, to simplify the logic.
- *
- * On TILE-Gx the hash-for-home function is much more complex,
- * with the upshot being we can't readily guarantee we have
- * hit both entries in the 128-entry AMT that were hit by any
- * load in the entire range, so we just re-load them all.
- * With larger buffers, we may want to consider using a hypervisor
- * trap to issue loads directly to each hash-for-home tile for
- * each controller (doing it from Linux would trash the TLB).
- */
- if (hfh) {
- step_size = L2_CACHE_BYTES;
-#ifdef __tilegx__
- load_count = (size + L2_CACHE_BYTES - 1) / L2_CACHE_BYTES;
-#else
- load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
- (1 << CHIP_LOG_NUM_MSHIMS());
-#endif
- } else {
- step_size = STRIPE_WIDTH;
- load_count = (1 << CHIP_LOG_NUM_MSHIMS());
- }
-
- /* Load the last byte of the buffer. */
- p = (char *)buffer + size - 1;
- force_load(p);
-
- /* Bump down to the end of the previous stripe or cache line. */
- p -= step_size;
- p = (char *)((unsigned long)p | (step_size - 1));
-
- /* Figure out how far back we need to go. */
- base = p - (step_size * (load_count - 2));
- if ((unsigned long)base < (unsigned long)buffer)
- base = buffer;
-
- /* Fire all the loads we need. */
- for (; p >= base; p -= step_size)
- force_load(p);
-
- /*
- * Repeat, but with finv's instead of loads, to get rid of the
- * data we just loaded into our own cache and the old home L3.
- * The finv's are guaranteed not to actually flush the data in
- * the buffer back to their home, since we just read it, so the
- * lines are clean in cache; we will only invalidate those lines.
- */
- p = (char *)buffer + size - 1;
- __insn_finv(p);
- p -= step_size;
- p = (char *)((unsigned long)p | (step_size - 1));
- for (; p >= base; p -= step_size)
- __insn_finv(p);
-
- /* Wait for these finv's (and thus the first finvs) to be done. */
- __insn_mf();
-
-#ifdef __tilegx__
- /* Reenable the prefetcher. */
- __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
-#endif
-}
-EXPORT_SYMBOL_GPL(finv_buffer_remote);
diff --git a/arch/tile/lib/checksum.c b/arch/tile/lib/checksum.c
deleted file mode 100644
index c3ca3e64d9d9..000000000000
--- a/arch/tile/lib/checksum.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- * Support code for the main lib/checksum.c.
- */
-
-#include <net/checksum.h>
-#include <linux/module.h>
-
-__wsum do_csum(const unsigned char *buff, int len)
-{
- int odd, count;
- unsigned long result = 0;
-
- if (len <= 0)
- goto out;
- odd = 1 & (unsigned long) buff;
- if (odd) {
- result = (*buff << 8);
- len--;
- buff++;
- }
- count = len >> 1; /* nr of 16-bit words.. */
- if (count) {
- if (2 & (unsigned long) buff) {
- result += *(const unsigned short *)buff;
- count--;
- len -= 2;
- buff += 2;
- }
- count >>= 1; /* nr of 32-bit words.. */
- if (count) {
-#ifdef __tilegx__
- if (4 & (unsigned long) buff) {
- unsigned int w = *(const unsigned int *)buff;
- result = __insn_v2sadau(result, w, 0);
- count--;
- len -= 4;
- buff += 4;
- }
- count >>= 1; /* nr of 64-bit words.. */
-#endif
-
- /*
- * This algorithm could wrap around for very
- * large buffers, but those should be impossible.
- */
- BUG_ON(count >= 65530);
-
- while (count) {
- unsigned long w = *(const unsigned long *)buff;
- count--;
- buff += sizeof(w);
-#ifdef __tilegx__
- result = __insn_v2sadau(result, w, 0);
-#else
- result = __insn_sadah_u(result, w, 0);
-#endif
- }
-#ifdef __tilegx__
- if (len & 4) {
- unsigned int w = *(const unsigned int *)buff;
- result = __insn_v2sadau(result, w, 0);
- buff += 4;
- }
-#endif
- }
- if (len & 2) {
- result += *(const unsigned short *) buff;
- buff += 2;
- }
- }
- if (len & 1)
- result += *buff;
- result = csum_long(result);
- if (odd)
- result = swab16(result);
-out:
- return result;
-}
diff --git a/arch/tile/lib/cpumask.c b/arch/tile/lib/cpumask.c
deleted file mode 100644
index 75947edccb26..000000000000
--- a/arch/tile/lib/cpumask.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/cpumask.h>
-#include <linux/ctype.h>
-#include <linux/errno.h>
-#include <linux/smp.h>
-#include <linux/export.h>
-
-/*
- * Allow cropping out bits beyond the end of the array.
- * Move to "lib" directory if more clients want to use this routine.
- */
-int bitmap_parselist_crop(const char *bp, unsigned long *maskp, int nmaskbits)
-{
- unsigned a, b;
-
- bitmap_zero(maskp, nmaskbits);
- do {
- if (!isdigit(*bp))
- return -EINVAL;
- a = simple_strtoul(bp, (char **)&bp, 10);
- b = a;
- if (*bp == '-') {
- bp++;
- if (!isdigit(*bp))
- return -EINVAL;
- b = simple_strtoul(bp, (char **)&bp, 10);
- }
- if (!(a <= b))
- return -EINVAL;
- if (b >= nmaskbits)
- b = nmaskbits-1;
- while (a <= b) {
- set_bit(a, maskp);
- a++;
- }
- if (*bp == ',')
- bp++;
- } while (*bp != '\0' && *bp != '\n');
- return 0;
-}
-EXPORT_SYMBOL(bitmap_parselist_crop);
diff --git a/arch/tile/lib/delay.c b/arch/tile/lib/delay.c
deleted file mode 100644
index cdacdd11d360..000000000000
--- a/arch/tile/lib/delay.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/delay.h>
-#include <linux/thread_info.h>
-#include <asm/timex.h>
-
-void __udelay(unsigned long usecs)
-{
- if (usecs > ULONG_MAX / 1000) {
- WARN_ON_ONCE(usecs > ULONG_MAX / 1000);
- usecs = ULONG_MAX / 1000;
- }
- __ndelay(usecs * 1000);
-}
-EXPORT_SYMBOL(__udelay);
-
-void __ndelay(unsigned long nsecs)
-{
- cycles_t target = get_cycles();
- target += ns2cycles(nsecs);
- while (get_cycles() < target)
- cpu_relax();
-}
-EXPORT_SYMBOL(__ndelay);
-
-void __delay(unsigned long cycles)
-{
- cycles_t target = get_cycles() + cycles;
- while (get_cycles() < target)
- cpu_relax();
-}
-EXPORT_SYMBOL(__delay);
diff --git a/arch/tile/lib/exports.c b/arch/tile/lib/exports.c
deleted file mode 100644
index ecce8e177e3f..000000000000
--- a/arch/tile/lib/exports.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Exports from assembler code and from libtile-cc.
- */
-
-#include <linux/module.h>
-
-/* arch/tile/lib/usercopy.S */
-#include <linux/uaccess.h>
-EXPORT_SYMBOL(clear_user_asm);
-EXPORT_SYMBOL(flush_user_asm);
-EXPORT_SYMBOL(finv_user_asm);
-
-/* arch/tile/kernel/entry.S */
-#include <linux/kernel.h>
-#include <asm/processor.h>
-EXPORT_SYMBOL(current_text_addr);
-
-/* arch/tile/kernel/head.S */
-EXPORT_SYMBOL(empty_zero_page);
-
-#ifdef CONFIG_FUNCTION_TRACER
-/* arch/tile/kernel/mcount_64.S */
-#include <asm/ftrace.h>
-EXPORT_SYMBOL(__mcount);
-#endif /* CONFIG_FUNCTION_TRACER */
-
-/* arch/tile/lib/, various memcpy files */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(raw_copy_to_user);
-EXPORT_SYMBOL(raw_copy_from_user);
-#ifdef __tilegx__
-EXPORT_SYMBOL(raw_copy_in_user);
-#endif
-
-/* hypervisor glue */
-#include <hv/hypervisor.h>
-EXPORT_SYMBOL(hv_dev_open);
-EXPORT_SYMBOL(hv_dev_pread);
-EXPORT_SYMBOL(hv_dev_pwrite);
-EXPORT_SYMBOL(hv_dev_preada);
-EXPORT_SYMBOL(hv_dev_pwritea);
-EXPORT_SYMBOL(hv_dev_poll);
-EXPORT_SYMBOL(hv_dev_poll_cancel);
-EXPORT_SYMBOL(hv_dev_close);
-EXPORT_SYMBOL(hv_sysconf);
-EXPORT_SYMBOL(hv_confstr);
-EXPORT_SYMBOL(hv_get_rtc);
-EXPORT_SYMBOL(hv_set_rtc);
-
-/* libgcc.a */
-uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);
-EXPORT_SYMBOL(__udivsi3);
-int32_t __divsi3(int32_t dividend, int32_t divisor);
-EXPORT_SYMBOL(__divsi3);
-uint64_t __udivdi3(uint64_t dividend, uint64_t divisor);
-EXPORT_SYMBOL(__udivdi3);
-int64_t __divdi3(int64_t dividend, int64_t divisor);
-EXPORT_SYMBOL(__divdi3);
-uint32_t __umodsi3(uint32_t dividend, uint32_t divisor);
-EXPORT_SYMBOL(__umodsi3);
-int32_t __modsi3(int32_t dividend, int32_t divisor);
-EXPORT_SYMBOL(__modsi3);
-uint64_t __umoddi3(uint64_t dividend, uint64_t divisor);
-EXPORT_SYMBOL(__umoddi3);
-int64_t __moddi3(int64_t dividend, int64_t divisor);
-EXPORT_SYMBOL(__moddi3);
-#ifdef __tilegx__
-typedef int TItype __attribute__((mode(TI)));
-TItype __multi3(TItype a, TItype b);
-EXPORT_SYMBOL(__multi3); /* required for gcc 7 and later */
-#else
-int64_t __muldi3(int64_t, int64_t);
-EXPORT_SYMBOL(__muldi3);
-uint64_t __lshrdi3(uint64_t, unsigned int);
-EXPORT_SYMBOL(__lshrdi3);
-uint64_t __ashrdi3(uint64_t, unsigned int);
-EXPORT_SYMBOL(__ashrdi3);
-uint64_t __ashldi3(uint64_t, unsigned int);
-EXPORT_SYMBOL(__ashldi3);
-int __ffsdi2(uint64_t);
-EXPORT_SYMBOL(__ffsdi2);
-#endif
diff --git a/arch/tile/lib/memchr_32.c b/arch/tile/lib/memchr_32.c
deleted file mode 100644
index cc3d9badf030..000000000000
--- a/arch/tile/lib/memchr_32.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-
-void *memchr(const void *s, int c, size_t n)
-{
- const uint32_t *last_word_ptr;
- const uint32_t *p;
- const char *last_byte_ptr;
- uintptr_t s_int;
- uint32_t goal, before_mask, v, bits;
- char *ret;
-
- if (__builtin_expect(n == 0, 0)) {
- /* Don't dereference any memory if the array is empty. */
- return NULL;
- }
-
- /* Get an aligned pointer. */
- s_int = (uintptr_t) s;
- p = (const uint32_t *)(s_int & -4);
-
- /* Create four copies of the byte for which we are looking. */
- goal = 0x01010101 * (uint8_t) c;
-
- /* Read the first word, but munge it so that bytes before the array
- * will not match goal.
- *
- * Note that this shift count expression works because we know
- * shift counts are taken mod 32.
- */
- before_mask = (1 << (s_int << 3)) - 1;
- v = (*p | before_mask) ^ (goal & before_mask);
-
- /* Compute the address of the last byte. */
- last_byte_ptr = (const char *)s + n - 1;
-
- /* Compute the address of the word containing the last byte. */
- last_word_ptr = (const uint32_t *)((uintptr_t) last_byte_ptr & -4);
-
- while ((bits = __insn_seqb(v, goal)) == 0) {
- if (__builtin_expect(p == last_word_ptr, 0)) {
- /* We already read the last word in the array,
- * so give up.
- */
- return NULL;
- }
- v = *++p;
- }
-
- /* We found a match, but it might be in a byte past the end
- * of the array.
- */
- ret = ((char *)p) + (__insn_ctz(bits) >> 3);
- return (ret <= last_byte_ptr) ? ret : NULL;
-}
-EXPORT_SYMBOL(memchr);
diff --git a/arch/tile/lib/memchr_64.c b/arch/tile/lib/memchr_64.c
deleted file mode 100644
index f8196b3a950e..000000000000
--- a/arch/tile/lib/memchr_64.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include "string-endian.h"
-
-void *memchr(const void *s, int c, size_t n)
-{
- const uint64_t *last_word_ptr;
- const uint64_t *p;
- const char *last_byte_ptr;
- uintptr_t s_int;
- uint64_t goal, before_mask, v, bits;
- char *ret;
-
- if (__builtin_expect(n == 0, 0)) {
- /* Don't dereference any memory if the array is empty. */
- return NULL;
- }
-
- /* Get an aligned pointer. */
- s_int = (uintptr_t) s;
- p = (const uint64_t *)(s_int & -8);
-
- /* Create eight copies of the byte for which we are looking. */
- goal = copy_byte(c);
-
- /* Read the first word, but munge it so that bytes before the array
- * will not match goal.
- */
- before_mask = MASK(s_int);
- v = (*p | before_mask) ^ (goal & before_mask);
-
- /* Compute the address of the last byte. */
- last_byte_ptr = (const char *)s + n - 1;
-
- /* Compute the address of the word containing the last byte. */
- last_word_ptr = (const uint64_t *)((uintptr_t) last_byte_ptr & -8);
-
- while ((bits = __insn_v1cmpeq(v, goal)) == 0) {
- if (__builtin_expect(p == last_word_ptr, 0)) {
- /* We already read the last word in the array,
- * so give up.
- */
- return NULL;
- }
- v = *++p;
- }
-
- /* We found a match, but it might be in a byte past the end
- * of the array.
- */
- ret = ((char *)p) + (CFZ(bits) >> 3);
- return (ret <= last_byte_ptr) ? ret : NULL;
-}
-EXPORT_SYMBOL(memchr);
diff --git a/arch/tile/lib/memcpy_32.S b/arch/tile/lib/memcpy_32.S
deleted file mode 100644
index 270f1267cd18..000000000000
--- a/arch/tile/lib/memcpy_32.S
+++ /dev/null
@@ -1,544 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <arch/chip.h>
-
-
-/*
- * This file shares the implementation of the userspace memcpy and
- * the kernel's memcpy, copy_to_user and copy_from_user.
- */
-
-#include <linux/linkage.h>
-
-#define IS_MEMCPY 0
-#define IS_COPY_FROM_USER 1
-#define IS_COPY_TO_USER -1
-
- .section .text.memcpy_common, "ax"
- .align 64
-
-/* Use this to preface each bundle that can cause an exception so
- * the kernel can clean up properly. The special cleanup code should
- * not use these, since it knows what it is doing.
- */
-#define EX \
- .pushsection __ex_table, "a"; \
- .align 4; \
- .word 9f, memcpy_common_fixup; \
- .popsection; \
- 9
-
-
-/* raw_copy_from_user takes the kernel target address in r0,
- * the user source in r1, and the bytes to copy in r2.
- * It returns the number of uncopiable bytes (hopefully zero) in r0.
- */
-ENTRY(raw_copy_from_user)
-.type raw_copy_from_user, @function
- FEEDBACK_ENTER_EXPLICIT(raw_copy_from_user, \
- .text.memcpy_common, \
- .Lend_memcpy_common - raw_copy_from_user)
- { movei r29, IS_COPY_FROM_USER; j memcpy_common }
- .size raw_copy_from_user, . - raw_copy_from_user
-
-/* raw_copy_to_user takes the user target address in r0,
- * the kernel source in r1, and the bytes to copy in r2.
- * It returns the number of uncopiable bytes (hopefully zero) in r0.
- */
-ENTRY(raw_copy_to_user)
-.type raw_copy_to_user, @function
- FEEDBACK_REENTER(raw_copy_from_user)
- { movei r29, IS_COPY_TO_USER; j memcpy_common }
- .size raw_copy_to_user, . - raw_copy_to_user
-
-ENTRY(memcpy)
-.type memcpy, @function
- FEEDBACK_REENTER(raw_copy_from_user)
- { movei r29, IS_MEMCPY }
- .size memcpy, . - memcpy
- /* Fall through */
-
- .type memcpy_common, @function
-memcpy_common:
- /* On entry, r29 holds one of the IS_* macro values from above. */
-
-
- /* r0 is the dest, r1 is the source, r2 is the size. */
-
- /* Save aside original dest so we can return it at the end. */
- { sw sp, lr; move r23, r0; or r4, r0, r1 }
-
- /* Check for an empty size. */
- { bz r2, .Ldone; andi r4, r4, 3 }
-
- /* Save aside original values in case of a fault. */
- { move r24, r1; move r25, r2 }
- move r27, lr
-
- /* Check for an unaligned source or dest. */
- { bnz r4, .Lcopy_unaligned_maybe_many; addli r4, r2, -256 }
-
-.Lcheck_aligned_copy_size:
- /* If we are copying < 256 bytes, branch to simple case. */
- { blzt r4, .Lcopy_8_check; slti_u r8, r2, 8 }
-
- /* Copying >= 256 bytes, so jump to complex prefetching loop. */
- { andi r6, r1, 63; j .Lcopy_many }
-
-/*
- *
- * Aligned 4 byte at a time copy loop
- *
- */
-
-.Lcopy_8_loop:
- /* Copy two words at a time to hide load latency. */
-EX: { lw r3, r1; addi r1, r1, 4; slti_u r8, r2, 16 }
-EX: { lw r4, r1; addi r1, r1, 4 }
-EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
-EX: { sw r0, r4; addi r0, r0, 4; addi r2, r2, -4 }
-.Lcopy_8_check:
- { bzt r8, .Lcopy_8_loop; slti_u r4, r2, 4 }
-
- /* Copy odd leftover word, if any. */
- { bnzt r4, .Lcheck_odd_stragglers }
-EX: { lw r3, r1; addi r1, r1, 4 }
-EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
-
-.Lcheck_odd_stragglers:
- { bnz r2, .Lcopy_unaligned_few }
-
-.Ldone:
- /* For memcpy return original dest address, else zero. */
- { mz r0, r29, r23; jrp lr }
-
-
-/*
- *
- * Prefetching multiple cache line copy handler (for large transfers).
- *
- */
-
- /* Copy words until r1 is cache-line-aligned. */
-.Lalign_loop:
-EX: { lw r3, r1; addi r1, r1, 4 }
- { andi r6, r1, 63 }
-EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
-.Lcopy_many:
- { bnzt r6, .Lalign_loop; addi r9, r0, 63 }
-
- { addi r3, r1, 60; andi r9, r9, -64 }
-
- /* No need to prefetch dst, we'll just do the wh64
- * right before we copy a line.
- */
-EX: { lw r5, r3; addi r3, r3, 64; movei r4, 1 }
- /* Intentionally stall for a few cycles to leave L2 cache alone. */
- { bnzt zero, .; move r27, lr }
-EX: { lw r6, r3; addi r3, r3, 64 }
- /* Intentionally stall for a few cycles to leave L2 cache alone. */
- { bnzt zero, . }
-EX: { lw r7, r3; addi r3, r3, 64 }
- /* Intentionally stall for a few cycles to leave L2 cache alone. */
- { bz zero, .Lbig_loop2 }
-
- /* On entry to this loop:
- * - r0 points to the start of dst line 0
- * - r1 points to start of src line 0
- * - r2 >= (256 - 60), only the first time the loop trips.
- * - r3 contains r1 + 128 + 60 [pointer to end of source line 2]
- * This is our prefetch address. When we get near the end
- * rather than prefetching off the end this is changed to point
- * to some "safe" recently loaded address.
- * - r5 contains *(r1 + 60) [i.e. last word of source line 0]
- * - r6 contains *(r1 + 64 + 60) [i.e. last word of source line 1]
- * - r9 contains ((r0 + 63) & -64)
- * [start of next dst cache line.]
- */
-
-.Lbig_loop:
- { jal .Lcopy_line2; add r15, r1, r2 }
-
-.Lbig_loop2:
- /* Copy line 0, first stalling until r5 is ready. */
-EX: { move r12, r5; lw r16, r1 }
- { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
- /* Prefetch several lines ahead. */
-EX: { lw r5, r3; addi r3, r3, 64 }
- { jal .Lcopy_line }
-
- /* Copy line 1, first stalling until r6 is ready. */
-EX: { move r12, r6; lw r16, r1 }
- { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
- /* Prefetch several lines ahead. */
-EX: { lw r6, r3; addi r3, r3, 64 }
- { jal .Lcopy_line }
-
- /* Copy line 2, first stalling until r7 is ready. */
-EX: { move r12, r7; lw r16, r1 }
- { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 }
- /* Prefetch several lines ahead. */
-EX: { lw r7, r3; addi r3, r3, 64 }
- /* Use up a caches-busy cycle by jumping back to the top of the
- * loop. Might as well get it out of the way now.
- */
- { j .Lbig_loop }
-
-
- /* On entry:
- * - r0 points to the destination line.
- * - r1 points to the source line.
- * - r3 is the next prefetch address.
- * - r9 holds the last address used for wh64.
- * - r12 = WORD_15
- * - r16 = WORD_0.
- * - r17 == r1 + 16.
- * - r27 holds saved lr to restore.
- *
- * On exit:
- * - r0 is incremented by 64.
- * - r1 is incremented by 64, unless that would point to a word
- * beyond the end of the source array, in which case it is redirected
- * to point to an arbitrary word already in the cache.
- * - r2 is decremented by 64.
- * - r3 is unchanged, unless it points to a word beyond the
- * end of the source array, in which case it is redirected
- * to point to an arbitrary word already in the cache.
- * Redirecting is OK since if we are that close to the end
- * of the array we will not come back to this subroutine
- * and use the contents of the prefetched address.
- * - r4 is nonzero iff r2 >= 64.
- * - r9 is incremented by 64, unless it points beyond the
- * end of the last full destination cache line, in which
- * case it is redirected to a "safe address" that can be
- * clobbered (sp - 64)
- * - lr contains the value in r27.
- */
-
-/* r26 unused */
-
-.Lcopy_line:
- /* TODO: when r3 goes past the end, we would like to redirect it
- * to prefetch the last partial cache line (if any) just once, for the
- * benefit of the final cleanup loop. But we don't want to
- * prefetch that line more than once, or subsequent prefetches
- * will go into the RTF. But then .Lbig_loop should unconditionally
- * branch to top of loop to execute final prefetch, and its
- * nop should become a conditional branch.
- */
-
- /* We need two non-memory cycles here to cover the resources
- * used by the loads initiated by the caller.
- */
- { add r15, r1, r2 }
-.Lcopy_line2:
- { slt_u r13, r3, r15; addi r17, r1, 16 }
-
- /* NOTE: this will stall for one cycle as L1 is busy. */
-
- /* Fill second L1D line. */
-EX: { lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */
-
- /* Prepare destination line for writing. */
-EX: { wh64 r9; addi r9, r9, 64 }
- /* Load seven words that are L1D hits to cover wh64 L2 usage. */
-
- /* Load the three remaining words from the last L1D line, which
- * we know has already filled the L1D.
- */
-EX: { lw r4, r1; addi r1, r1, 4; addi r20, r1, 16 } /* r4 = WORD_12 */
-EX: { lw r8, r1; addi r1, r1, 4; slt_u r13, r20, r15 }/* r8 = WORD_13 */
-EX: { lw r11, r1; addi r1, r1, -52; mvz r20, r13, r1 } /* r11 = WORD_14 */
-
- /* Load the three remaining words from the first L1D line, first
- * stalling until it has filled by "looking at" r16.
- */
-EX: { lw r13, r1; addi r1, r1, 4; move zero, r16 } /* r13 = WORD_1 */
-EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_2 */
-EX: { lw r15, r1; addi r1, r1, 8; addi r10, r0, 60 } /* r15 = WORD_3 */
-
- /* Load second word from the second L1D line, first
- * stalling until it has filled by "looking at" r17.
- */
-EX: { lw r19, r1; addi r1, r1, 4; move zero, r17 } /* r19 = WORD_5 */
-
- /* Store last word to the destination line, potentially dirtying it
- * for the first time, which keeps the L2 busy for two cycles.
- */
-EX: { sw r10, r12 } /* store(WORD_15) */
-
- /* Use two L1D hits to cover the sw L2 access above. */
-EX: { lw r10, r1; addi r1, r1, 4 } /* r10 = WORD_6 */
-EX: { lw r12, r1; addi r1, r1, 4 } /* r12 = WORD_7 */
-
- /* Fill third L1D line. */
-EX: { lw r18, r1; addi r1, r1, 4 } /* r18 = WORD_8 */
-
- /* Store first L1D line. */
-EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */
-EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */
-EX: { sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */
-EX: { sw r0, r15; addi r0, r0, 4; addi r13, sp, -64 } /* store(WORD_3) */
- /* Store second L1D line. */
-EX: { sw r0, r17; addi r0, r0, 4; mvz r9, r16, r13 }/* store(WORD_4) */
-EX: { sw r0, r19; addi r0, r0, 4 } /* store(WORD_5) */
-EX: { sw r0, r10; addi r0, r0, 4 } /* store(WORD_6) */
-EX: { sw r0, r12; addi r0, r0, 4 } /* store(WORD_7) */
-
-EX: { lw r13, r1; addi r1, r1, 4; move zero, r18 } /* r13 = WORD_9 */
-EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_10 */
-EX: { lw r15, r1; move r1, r20 } /* r15 = WORD_11 */
-
- /* Store third L1D line. */
-EX: { sw r0, r18; addi r0, r0, 4 } /* store(WORD_8) */
-EX: { sw r0, r13; addi r0, r0, 4 } /* store(WORD_9) */
-EX: { sw r0, r14; addi r0, r0, 4 } /* store(WORD_10) */
-EX: { sw r0, r15; addi r0, r0, 4 } /* store(WORD_11) */
-
- /* Store rest of fourth L1D line. */
-EX: { sw r0, r4; addi r0, r0, 4 } /* store(WORD_12) */
- {
-EX: sw r0, r8 /* store(WORD_13) */
- addi r0, r0, 4
- /* Will r2 be > 64 after we subtract 64 below? */
- shri r4, r2, 7
- }
- {
-EX: sw r0, r11 /* store(WORD_14) */
- addi r0, r0, 8
- /* Record 64 bytes successfully copied. */
- addi r2, r2, -64
- }
-
- { jrp lr; move lr, r27 }
-
- /* Convey to the backtrace library that the stack frame is size
- * zero, and the real return address is on the stack rather than
- * in 'lr'.
- */
- { info 8 }
-
- .align 64
-.Lcopy_unaligned_maybe_many:
- /* Skip the setup overhead if we aren't copying many bytes. */
- { slti_u r8, r2, 20; sub r4, zero, r0 }
- { bnzt r8, .Lcopy_unaligned_few; andi r4, r4, 3 }
- { bz r4, .Ldest_is_word_aligned; add r18, r1, r2 }
-
-/*
- *
- * unaligned 4 byte at a time copy handler.
- *
- */
-
- /* Copy single bytes until r0 == 0 mod 4, so we can store words. */
-.Lalign_dest_loop:
-EX: { lb_u r3, r1; addi r1, r1, 1; addi r4, r4, -1 }
-EX: { sb r0, r3; addi r0, r0, 1; addi r2, r2, -1 }
- { bnzt r4, .Lalign_dest_loop; andi r3, r1, 3 }
-
- /* If source and dest are now *both* aligned, do an aligned copy. */
- { bz r3, .Lcheck_aligned_copy_size; addli r4, r2, -256 }
-
-.Ldest_is_word_aligned:
-
-EX: { andi r8, r0, 63; lwadd_na r6, r1, 4}
- { slti_u r9, r2, 64; bz r8, .Ldest_is_L2_line_aligned }
-
- /* This copies unaligned words until either there are fewer
- * than 4 bytes left to copy, or until the destination pointer
- * is cache-aligned, whichever comes first.
- *
- * On entry:
- * - r0 is the next store address.
- * - r1 points 4 bytes past the load address corresponding to r0.
- * - r2 >= 4
- * - r6 is the next aligned word loaded.
- */
-.Lcopy_unaligned_src_words:
-EX: { lwadd_na r7, r1, 4; slti_u r8, r2, 4 + 4 }
- /* stall */
- { dword_align r6, r7, r1; slti_u r9, r2, 64 + 4 }
-EX: { swadd r0, r6, 4; addi r2, r2, -4 }
- { bnz r8, .Lcleanup_unaligned_words; andi r8, r0, 63 }
- { bnzt r8, .Lcopy_unaligned_src_words; move r6, r7 }
-
- /* On entry:
- * - r0 is the next store address.
- * - r1 points 4 bytes past the load address corresponding to r0.
- * - r2 >= 4 (# of bytes left to store).
- * - r6 is the next aligned src word value.
- * - r9 = (r2 < 64U).
- * - r18 points one byte past the end of source memory.
- */
-.Ldest_is_L2_line_aligned:
-
- {
- /* Not a full cache line remains. */
- bnz r9, .Lcleanup_unaligned_words
- move r7, r6
- }
-
- /* r2 >= 64 */
-
- /* Kick off two prefetches, but don't go past the end. */
- { addi r3, r1, 63 - 4; addi r8, r1, 64 + 63 - 4 }
- { prefetch r3; move r3, r8; slt_u r8, r8, r18 }
- { mvz r3, r8, r1; addi r8, r3, 64 }
- { prefetch r3; move r3, r8; slt_u r8, r8, r18 }
- { mvz r3, r8, r1; movei r17, 0 }
-
-.Lcopy_unaligned_line:
- /* Prefetch another line. */
- { prefetch r3; addi r15, r1, 60; addi r3, r3, 64 }
- /* Fire off a load of the last word we are about to copy. */
-EX: { lw_na r15, r15; slt_u r8, r3, r18 }
-
-EX: { mvz r3, r8, r1; wh64 r0 }
-
- /* This loop runs twice.
- *
- * On entry:
- * - r17 is even before the first iteration, and odd before
- * the second. It is incremented inside the loop. Encountering
- * an even value at the end of the loop makes it stop.
- */
-.Lcopy_half_an_unaligned_line:
-EX: {
- /* Stall until the last byte is ready. In the steady state this
- * guarantees all words to load below will be in the L2 cache, which
- * avoids shunting the loads to the RTF.
- */
- move zero, r15
- lwadd_na r7, r1, 16
- }
-EX: { lwadd_na r11, r1, 12 }
-EX: { lwadd_na r14, r1, -24 }
-EX: { lwadd_na r8, r1, 4 }
-EX: { lwadd_na r9, r1, 4 }
-EX: {
- lwadd_na r10, r1, 8
- /* r16 = (r2 < 64), after we subtract 32 from r2 below. */
- slti_u r16, r2, 64 + 32
- }
-EX: { lwadd_na r12, r1, 4; addi r17, r17, 1 }
-EX: { lwadd_na r13, r1, 8; dword_align r6, r7, r1 }
-EX: { swadd r0, r6, 4; dword_align r7, r8, r1 }
-EX: { swadd r0, r7, 4; dword_align r8, r9, r1 }
-EX: { swadd r0, r8, 4; dword_align r9, r10, r1 }
-EX: { swadd r0, r9, 4; dword_align r10, r11, r1 }
-EX: { swadd r0, r10, 4; dword_align r11, r12, r1 }
-EX: { swadd r0, r11, 4; dword_align r12, r13, r1 }
-EX: { swadd r0, r12, 4; dword_align r13, r14, r1 }
-EX: { swadd r0, r13, 4; addi r2, r2, -32 }
- { move r6, r14; bbst r17, .Lcopy_half_an_unaligned_line }
-
- { bzt r16, .Lcopy_unaligned_line; move r7, r6 }
-
- /* On entry:
- * - r0 is the next store address.
- * - r1 points 4 bytes past the load address corresponding to r0.
- * - r2 >= 0 (# of bytes left to store).
- * - r7 is the next aligned src word value.
- */
-.Lcleanup_unaligned_words:
- /* Handle any trailing bytes. */
- { bz r2, .Lcopy_unaligned_done; slti_u r8, r2, 4 }
- { bzt r8, .Lcopy_unaligned_src_words; move r6, r7 }
-
- /* Move r1 back to the point where it corresponds to r0. */
- { addi r1, r1, -4 }
-
- /* Fall through */
-
-/*
- *
- * 1 byte at a time copy handler.
- *
- */
-
-.Lcopy_unaligned_few:
-EX: { lb_u r3, r1; addi r1, r1, 1 }
-EX: { sb r0, r3; addi r0, r0, 1; addi r2, r2, -1 }
- { bnzt r2, .Lcopy_unaligned_few }
-
-.Lcopy_unaligned_done:
-
- /* For memcpy return original dest address, else zero. */
- { mz r0, r29, r23; jrp lr }
-
-.Lend_memcpy_common:
- .size memcpy_common, .Lend_memcpy_common - memcpy_common
-
- .section .fixup,"ax"
-memcpy_common_fixup:
- .type memcpy_common_fixup, @function
-
- /* Skip any bytes we already successfully copied.
- * r2 (num remaining) is correct, but r0 (dst) and r1 (src)
- * may not be quite right because of unrolling and prefetching.
- * So we need to recompute their values as the address just
- * after the last byte we are sure was successfully loaded and
- * then stored.
- */
-
- /* Determine how many bytes we successfully copied. */
- { sub r3, r25, r2 }
-
- /* Add this to the original r0 and r1 to get their new values. */
- { add r0, r23, r3; add r1, r24, r3 }
-
- { bzt r29, memcpy_fixup_loop }
- { blzt r29, copy_to_user_fixup_loop }
-
-copy_from_user_fixup_loop:
- /* Try copying the rest one byte at a time, expecting a load fault. */
-.Lcfu: { lb_u r3, r1; addi r1, r1, 1 }
- { sb r0, r3; addi r0, r0, 1; addi r2, r2, -1 }
- { bnzt r2, copy_from_user_fixup_loop }
-
-.Lcopy_from_user_fixup_zero_remainder:
- move lr, r27
- { move r0, r2; jrp lr }
-
-copy_to_user_fixup_loop:
- /* Try copying the rest one byte at a time, expecting a store fault. */
- { lb_u r3, r1; addi r1, r1, 1 }
-.Lctu: { sb r0, r3; addi r0, r0, 1; addi r2, r2, -1 }
- { bnzt r2, copy_to_user_fixup_loop }
-.Lcopy_to_user_fixup_done:
- move lr, r27
- { move r0, r2; jrp lr }
-
-memcpy_fixup_loop:
- /* Try copying the rest one byte at a time. We expect a disastrous
- * fault to happen since we are in fixup code, but let it happen.
- */
- { lb_u r3, r1; addi r1, r1, 1 }
- { sb r0, r3; addi r0, r0, 1; addi r2, r2, -1 }
- { bnzt r2, memcpy_fixup_loop }
- /* This should be unreachable, we should have faulted again.
- * But be paranoid and handle it in case some interrupt changed
- * the TLB or something.
- */
- move lr, r27
- { move r0, r23; jrp lr }
-
- .size memcpy_common_fixup, . - memcpy_common_fixup
-
- .section __ex_table,"a"
- .align 4
- .word .Lcfu, .Lcopy_from_user_fixup_zero_remainder
- .word .Lctu, .Lcopy_to_user_fixup_done
diff --git a/arch/tile/lib/memcpy_64.c b/arch/tile/lib/memcpy_64.c
deleted file mode 100644
index 4815354b8cd2..000000000000
--- a/arch/tile/lib/memcpy_64.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-/* EXPORT_SYMBOL() is in arch/tile/lib/exports.c since this should be asm. */
-
-/* Must be 8 bytes in size. */
-#define op_t uint64_t
-
-/* Threshold value for when to enter the unrolled loops. */
-#define OP_T_THRES 16
-
-#if CHIP_L2_LINE_SIZE() != 64
-#error "Assumes 64 byte line size"
-#endif
-
-/* How many cache lines ahead should we prefetch? */
-#define PREFETCH_LINES_AHEAD 4
-
-/*
- * Provide "base versions" of load and store for the normal code path.
- * The kernel provides other versions for userspace copies.
- */
-#define ST(p, v) (*(p) = (v))
-#define LD(p) (*(p))
-
-#ifndef USERCOPY_FUNC
-#define ST1 ST
-#define ST2 ST
-#define ST4 ST
-#define ST8 ST
-#define LD1 LD
-#define LD2 LD
-#define LD4 LD
-#define LD8 LD
-#define RETVAL dstv
-void *memcpy(void *__restrict dstv, const void *__restrict srcv, size_t n)
-#else
-/*
- * Special kernel version will provide implementation of the LDn/STn
- * macros to return a count of uncopied bytes due to mm fault.
- */
-#define RETVAL 0
-int __attribute__((optimize("omit-frame-pointer")))
-USERCOPY_FUNC(void *__restrict dstv, const void *__restrict srcv, size_t n)
-#endif
-{
- char *__restrict dst1 = (char *)dstv;
- const char *__restrict src1 = (const char *)srcv;
- const char *__restrict src1_end;
- const char *__restrict prefetch;
- op_t *__restrict dst8; /* 8-byte pointer to destination memory. */
- op_t final; /* Final bytes to write to trailing word, if any */
- long i;
-
- if (n < 16) {
- for (; n; n--)
- ST1(dst1++, LD1(src1++));
- return RETVAL;
- }
-
- /*
- * Locate the end of source memory we will copy. Don't
- * prefetch past this.
- */
- src1_end = src1 + n - 1;
-
- /* Prefetch ahead a few cache lines, but not past the end. */
- prefetch = src1;
- for (i = 0; i < PREFETCH_LINES_AHEAD; i++) {
- __insn_prefetch(prefetch);
- prefetch += CHIP_L2_LINE_SIZE();
- prefetch = (prefetch < src1_end) ? prefetch : src1;
- }
-
- /* Copy bytes until dst is word-aligned. */
- for (; (uintptr_t)dst1 & (sizeof(op_t) - 1); n--)
- ST1(dst1++, LD1(src1++));
-
- /* 8-byte pointer to destination memory. */
- dst8 = (op_t *)dst1;
-
- if (__builtin_expect((uintptr_t)src1 & (sizeof(op_t) - 1), 0)) {
- /* Unaligned copy. */
-
- op_t tmp0 = 0, tmp1 = 0, tmp2, tmp3;
- const op_t *src8 = (const op_t *) ((uintptr_t)src1 &
- -sizeof(op_t));
- const void *srci = (void *)src1;
- int m;
-
- m = (CHIP_L2_LINE_SIZE() << 2) -
- (((uintptr_t)dst8) & ((CHIP_L2_LINE_SIZE() << 2) - 1));
- m = (n < m) ? n : m;
- m /= sizeof(op_t);
-
- /* Copy until 'dst' is cache-line-aligned. */
- n -= (sizeof(op_t) * m);
-
- switch (m % 4) {
- case 0:
- if (__builtin_expect(!m, 0))
- goto _M0;
- tmp1 = LD8(src8++);
- tmp2 = LD8(src8++);
- goto _8B3;
- case 2:
- m += 2;
- tmp3 = LD8(src8++);
- tmp0 = LD8(src8++);
- goto _8B1;
- case 3:
- m += 1;
- tmp2 = LD8(src8++);
- tmp3 = LD8(src8++);
- goto _8B2;
- case 1:
- m--;
- tmp0 = LD8(src8++);
- tmp1 = LD8(src8++);
- if (__builtin_expect(!m, 0))
- goto _8B0;
- }
-
- do {
- tmp2 = LD8(src8++);
- tmp0 = __insn_dblalign(tmp0, tmp1, srci);
- ST8(dst8++, tmp0);
-_8B3:
- tmp3 = LD8(src8++);
- tmp1 = __insn_dblalign(tmp1, tmp2, srci);
- ST8(dst8++, tmp1);
-_8B2:
- tmp0 = LD8(src8++);
- tmp2 = __insn_dblalign(tmp2, tmp3, srci);
- ST8(dst8++, tmp2);
-_8B1:
- tmp1 = LD8(src8++);
- tmp3 = __insn_dblalign(tmp3, tmp0, srci);
- ST8(dst8++, tmp3);
- m -= 4;
- } while (m);
-
-_8B0:
- tmp0 = __insn_dblalign(tmp0, tmp1, srci);
- ST8(dst8++, tmp0);
- src8--;
-
-_M0:
- if (__builtin_expect(n >= CHIP_L2_LINE_SIZE(), 0)) {
- op_t tmp4, tmp5, tmp6, tmp7, tmp8;
-
- prefetch = ((const char *)src8) +
- CHIP_L2_LINE_SIZE() * PREFETCH_LINES_AHEAD;
-
- for (tmp0 = LD8(src8++); n >= CHIP_L2_LINE_SIZE();
- n -= CHIP_L2_LINE_SIZE()) {
- /* Prefetch and advance to next line to
- prefetch, but don't go past the end. */
- __insn_prefetch(prefetch);
-
- /* Make sure prefetch got scheduled
- earlier. */
- __asm__ ("" : : : "memory");
-
- prefetch += CHIP_L2_LINE_SIZE();
- prefetch = (prefetch < src1_end) ? prefetch :
- (const char *) src8;
-
- tmp1 = LD8(src8++);
- tmp2 = LD8(src8++);
- tmp3 = LD8(src8++);
- tmp4 = LD8(src8++);
- tmp5 = LD8(src8++);
- tmp6 = LD8(src8++);
- tmp7 = LD8(src8++);
- tmp8 = LD8(src8++);
-
- tmp0 = __insn_dblalign(tmp0, tmp1, srci);
- tmp1 = __insn_dblalign(tmp1, tmp2, srci);
- tmp2 = __insn_dblalign(tmp2, tmp3, srci);
- tmp3 = __insn_dblalign(tmp3, tmp4, srci);
- tmp4 = __insn_dblalign(tmp4, tmp5, srci);
- tmp5 = __insn_dblalign(tmp5, tmp6, srci);
- tmp6 = __insn_dblalign(tmp6, tmp7, srci);
- tmp7 = __insn_dblalign(tmp7, tmp8, srci);
-
- __insn_wh64(dst8);
-
- ST8(dst8++, tmp0);
- ST8(dst8++, tmp1);
- ST8(dst8++, tmp2);
- ST8(dst8++, tmp3);
- ST8(dst8++, tmp4);
- ST8(dst8++, tmp5);
- ST8(dst8++, tmp6);
- ST8(dst8++, tmp7);
-
- tmp0 = tmp8;
- }
- src8--;
- }
-
- /* Copy the rest 8-byte chunks. */
- if (n >= sizeof(op_t)) {
- tmp0 = LD8(src8++);
- for (; n >= sizeof(op_t); n -= sizeof(op_t)) {
- tmp1 = LD8(src8++);
- tmp0 = __insn_dblalign(tmp0, tmp1, srci);
- ST8(dst8++, tmp0);
- tmp0 = tmp1;
- }
- src8--;
- }
-
- if (n == 0)
- return RETVAL;
-
- tmp0 = LD8(src8++);
- tmp1 = ((const char *)src8 <= src1_end)
- ? LD8((op_t *)src8) : 0;
- final = __insn_dblalign(tmp0, tmp1, srci);
-
- } else {
- /* Aligned copy. */
-
- const op_t *__restrict src8 = (const op_t *)src1;
-
- /* src8 and dst8 are both word-aligned. */
- if (n >= CHIP_L2_LINE_SIZE()) {
- /* Copy until 'dst' is cache-line-aligned. */
- for (; (uintptr_t)dst8 & (CHIP_L2_LINE_SIZE() - 1);
- n -= sizeof(op_t))
- ST8(dst8++, LD8(src8++));
-
- for (; n >= CHIP_L2_LINE_SIZE(); ) {
- op_t tmp0, tmp1, tmp2, tmp3;
- op_t tmp4, tmp5, tmp6, tmp7;
-
- /*
- * Prefetch and advance to next line
- * to prefetch, but don't go past the
- * end.
- */
- __insn_prefetch(prefetch);
-
- /* Make sure prefetch got scheduled
- earlier. */
- __asm__ ("" : : : "memory");
-
- prefetch += CHIP_L2_LINE_SIZE();
- prefetch = (prefetch < src1_end) ? prefetch :
- (const char *)src8;
-
- /*
- * Do all the loads before wh64. This
- * is necessary if [src8, src8+7] and
- * [dst8, dst8+7] share the same cache
- * line and dst8 <= src8, as can be
- * the case when called from memmove,
- * or with code tested on x86 whose
- * memcpy always works with forward
- * copies.
- */
- tmp0 = LD8(src8++);
- tmp1 = LD8(src8++);
- tmp2 = LD8(src8++);
- tmp3 = LD8(src8++);
- tmp4 = LD8(src8++);
- tmp5 = LD8(src8++);
- tmp6 = LD8(src8++);
- tmp7 = LD8(src8++);
-
- /* wh64 and wait for tmp7 load completion. */
- __asm__ ("move %0, %0; wh64 %1\n"
- : : "r"(tmp7), "r"(dst8));
-
- ST8(dst8++, tmp0);
- ST8(dst8++, tmp1);
- ST8(dst8++, tmp2);
- ST8(dst8++, tmp3);
- ST8(dst8++, tmp4);
- ST8(dst8++, tmp5);
- ST8(dst8++, tmp6);
- ST8(dst8++, tmp7);
-
- n -= CHIP_L2_LINE_SIZE();
- }
-#if CHIP_L2_LINE_SIZE() != 64
-# error "Fix code that assumes particular L2 cache line size."
-#endif
- }
-
- for (; n >= sizeof(op_t); n -= sizeof(op_t))
- ST8(dst8++, LD8(src8++));
-
- if (__builtin_expect(n == 0, 1))
- return RETVAL;
-
- final = LD8(src8);
- }
-
- /* n != 0 if we get here. Write out any trailing bytes. */
- dst1 = (char *)dst8;
-#ifndef __BIG_ENDIAN__
- if (n & 4) {
- ST4((uint32_t *)dst1, final);
- dst1 += 4;
- final >>= 32;
- n &= 3;
- }
- if (n & 2) {
- ST2((uint16_t *)dst1, final);
- dst1 += 2;
- final >>= 16;
- n &= 1;
- }
- if (n)
- ST1((uint8_t *)dst1, final);
-#else
- if (n & 4) {
- ST4((uint32_t *)dst1, final >> 32);
- dst1 += 4;
- }
- else
- {
- final >>= 32;
- }
- if (n & 2) {
- ST2((uint16_t *)dst1, final >> 16);
- dst1 += 2;
- }
- else
- {
- final >>= 16;
- }
- if (n & 1)
- ST1((uint8_t *)dst1, final >> 8);
-#endif
-
- return RETVAL;
-}
-
-#ifdef USERCOPY_FUNC
-#undef ST1
-#undef ST2
-#undef ST4
-#undef ST8
-#undef LD1
-#undef LD2
-#undef LD4
-#undef LD8
-#undef USERCOPY_FUNC
-#endif
diff --git a/arch/tile/lib/memcpy_user_64.c b/arch/tile/lib/memcpy_user_64.c
deleted file mode 100644
index a3fea9fd973e..000000000000
--- a/arch/tile/lib/memcpy_user_64.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Do memcpy(), but trap and return "n" when a load or store faults.
- *
- * Note: this idiom only works when memcpy() compiles to a leaf function.
- * Here leaf function not only means it does not have calls, but also
- * requires no stack operations (sp, stack frame pointer) and no
- * use of callee-saved registers, else "jrp lr" will be incorrect since
- * unwinding stack frame is bypassed. Since memcpy() is not complex so
- * these conditions are satisfied here, but we need to be careful when
- * modifying this file. This is not a clean solution but is the best
- * one so far.
- *
- * Also note that we are capturing "n" from the containing scope here.
- */
-
-#define _ST(p, inst, v) \
- ({ \
- asm("1: " #inst " %0, %1;" \
- ".pushsection .coldtext,\"ax\";" \
- "2: { move r0, %2; jrp lr };" \
- ".section __ex_table,\"a\";" \
- ".align 8;" \
- ".quad 1b, 2b;" \
- ".popsection" \
- : "=m" (*(p)) : "r" (v), "r" (n)); \
- })
-
-#define _LD(p, inst) \
- ({ \
- unsigned long __v; \
- asm("1: " #inst " %0, %1;" \
- ".pushsection .coldtext,\"ax\";" \
- "2: { move r0, %2; jrp lr };" \
- ".section __ex_table,\"a\";" \
- ".align 8;" \
- ".quad 1b, 2b;" \
- ".popsection" \
- : "=r" (__v) : "m" (*(p)), "r" (n)); \
- __v; \
- })
-
-#define USERCOPY_FUNC raw_copy_to_user
-#define ST1(p, v) _ST((p), st1, (v))
-#define ST2(p, v) _ST((p), st2, (v))
-#define ST4(p, v) _ST((p), st4, (v))
-#define ST8(p, v) _ST((p), st, (v))
-#define LD1 LD
-#define LD2 LD
-#define LD4 LD
-#define LD8 LD
-#include "memcpy_64.c"
-
-#define USERCOPY_FUNC raw_copy_from_user
-#define ST1 ST
-#define ST2 ST
-#define ST4 ST
-#define ST8 ST
-#define LD1(p) _LD((p), ld1u)
-#define LD2(p) _LD((p), ld2u)
-#define LD4(p) _LD((p), ld4u)
-#define LD8(p) _LD((p), ld)
-#include "memcpy_64.c"
-
-#define USERCOPY_FUNC raw_copy_in_user
-#define ST1(p, v) _ST((p), st1, (v))
-#define ST2(p, v) _ST((p), st2, (v))
-#define ST4(p, v) _ST((p), st4, (v))
-#define ST8(p, v) _ST((p), st, (v))
-#define LD1(p) _LD((p), ld1u)
-#define LD2(p) _LD((p), ld2u)
-#define LD4(p) _LD((p), ld4u)
-#define LD8(p) _LD((p), ld)
-#include "memcpy_64.c"
diff --git a/arch/tile/lib/memmove.c b/arch/tile/lib/memmove.c
deleted file mode 100644
index fd615ae6ade7..000000000000
--- a/arch/tile/lib/memmove.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-
-void *memmove(void *dest, const void *src, size_t n)
-{
- if ((const char *)src >= (char *)dest + n
- || (char *)dest >= (const char *)src + n) {
- /* We found no overlap, so let memcpy do all the heavy
- * lifting (prefetching, etc.)
- */
- return memcpy(dest, src, n);
- }
-
- if (n != 0) {
- const uint8_t *in;
- uint8_t x;
- uint8_t *out;
- int stride;
-
- if (src < dest) {
- /* copy backwards */
- in = (const uint8_t *)src + n - 1;
- out = (uint8_t *)dest + n - 1;
- stride = -1;
- } else {
- /* copy forwards */
- in = (const uint8_t *)src;
- out = (uint8_t *)dest;
- stride = 1;
- }
-
- /* Manually software-pipeline this loop. */
- x = *in;
- in += stride;
-
- while (--n != 0) {
- *out = x;
- out += stride;
- x = *in;
- in += stride;
- }
-
- *out = x;
- }
-
- return dest;
-}
-EXPORT_SYMBOL(memmove);
diff --git a/arch/tile/lib/memset_32.c b/arch/tile/lib/memset_32.c
deleted file mode 100644
index 2042bfe6595f..000000000000
--- a/arch/tile/lib/memset_32.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <arch/chip.h>
-
-void *memset(void *s, int c, size_t n)
-{
- uint32_t *out32;
- int n32;
- uint32_t v16, v32;
- uint8_t *out8 = s;
- int to_align32;
-
- /* Experimentation shows that a trivial tight loop is a win up until
- * around a size of 20, where writing a word at a time starts to win.
- */
-#define BYTE_CUTOFF 20
-
-#if BYTE_CUTOFF < 3
- /* This must be at least at least this big, or some code later
- * on doesn't work.
- */
-#error "BYTE_CUTOFF is too small"
-#endif
-
- if (n < BYTE_CUTOFF) {
- /* Strangely, this turns out to be the tightest way to
- * write this loop.
- */
- if (n != 0) {
- do {
- /* Strangely, combining these into one line
- * performs worse.
- */
- *out8 = c;
- out8++;
- } while (--n != 0);
- }
-
- return s;
- }
-
- /* Align 'out8'. We know n >= 3 so this won't write past the end. */
- while (((uintptr_t) out8 & 3) != 0) {
- *out8++ = c;
- --n;
- }
-
- /* Align 'n'. */
- while (n & 3)
- out8[--n] = c;
-
- out32 = (uint32_t *) out8;
- n32 = n >> 2;
-
- /* Tile input byte out to 32 bits. */
- v16 = __insn_intlb(c, c);
- v32 = __insn_intlh(v16, v16);
-
- /* This must be at least 8 or the following loop doesn't work. */
-#define CACHE_LINE_SIZE_IN_WORDS (CHIP_L2_LINE_SIZE() / 4)
-
- /* Determine how many words we need to emit before the 'out32'
- * pointer becomes aligned modulo the cache line size.
- */
- to_align32 =
- (-((uintptr_t)out32 >> 2)) & (CACHE_LINE_SIZE_IN_WORDS - 1);
-
- /* Only bother aligning and using wh64 if there is at least
- * one full cache line to process. This check also prevents
- * overrunning the end of the buffer with alignment words.
- */
- if (to_align32 <= n32 - CACHE_LINE_SIZE_IN_WORDS) {
- int lines_left;
-
- /* Align out32 mod the cache line size so we can use wh64. */
- n32 -= to_align32;
- for (; to_align32 != 0; to_align32--) {
- *out32 = v32;
- out32++;
- }
-
- /* Use unsigned divide to turn this into a right shift. */
- lines_left = (unsigned)n32 / CACHE_LINE_SIZE_IN_WORDS;
-
- do {
- /* Only wh64 a few lines at a time, so we don't
- * exceed the maximum number of victim lines.
- */
- int x = ((lines_left < CHIP_MAX_OUTSTANDING_VICTIMS())
- ? lines_left
- : CHIP_MAX_OUTSTANDING_VICTIMS());
- uint32_t *wh = out32;
- int i = x;
- int j;
-
- lines_left -= x;
-
- do {
- __insn_wh64(wh);
- wh += CACHE_LINE_SIZE_IN_WORDS;
- } while (--i);
-
- for (j = x * (CACHE_LINE_SIZE_IN_WORDS / 4);
- j != 0; j--) {
- *out32++ = v32;
- *out32++ = v32;
- *out32++ = v32;
- *out32++ = v32;
- }
- } while (lines_left != 0);
-
- /* We processed all full lines above, so only this many
- * words remain to be processed.
- */
- n32 &= CACHE_LINE_SIZE_IN_WORDS - 1;
- }
-
- /* Now handle any leftover values. */
- if (n32 != 0) {
- do {
- *out32 = v32;
- out32++;
- } while (--n32 != 0);
- }
-
- return s;
-}
-EXPORT_SYMBOL(memset);
diff --git a/arch/tile/lib/memset_64.c b/arch/tile/lib/memset_64.c
deleted file mode 100644
index 03ef69cd73de..000000000000
--- a/arch/tile/lib/memset_64.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <arch/chip.h>
-#include "string-endian.h"
-
-void *memset(void *s, int c, size_t n)
-{
- uint64_t *out64;
- int n64, to_align64;
- uint64_t v64;
- uint8_t *out8 = s;
-
- /* Experimentation shows that a trivial tight loop is a win up until
- * around a size of 20, where writing a word at a time starts to win.
- */
-#define BYTE_CUTOFF 20
-
-#if BYTE_CUTOFF < 7
- /* This must be at least at least this big, or some code later
- * on doesn't work.
- */
-#error "BYTE_CUTOFF is too small"
-#endif
-
- if (n < BYTE_CUTOFF) {
- /* Strangely, this turns out to be the tightest way to
- * write this loop.
- */
- if (n != 0) {
- do {
- /* Strangely, combining these into one line
- * performs worse.
- */
- *out8 = c;
- out8++;
- } while (--n != 0);
- }
-
- return s;
- }
-
- /* Align 'out8'. We know n >= 7 so this won't write past the end. */
- while (((uintptr_t) out8 & 7) != 0) {
- *out8++ = c;
- --n;
- }
-
- /* Align 'n'. */
- while (n & 7)
- out8[--n] = c;
-
- out64 = (uint64_t *) out8;
- n64 = n >> 3;
-
- /* Tile input byte out to 64 bits. */
- v64 = copy_byte(c);
-
- /* This must be at least 8 or the following loop doesn't work. */
-#define CACHE_LINE_SIZE_IN_DOUBLEWORDS (CHIP_L2_LINE_SIZE() / 8)
-
- /* Determine how many words we need to emit before the 'out32'
- * pointer becomes aligned modulo the cache line size.
- */
- to_align64 = (-((uintptr_t)out64 >> 3)) &
- (CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1);
-
- /* Only bother aligning and using wh64 if there is at least
- * one full cache line to process. This check also prevents
- * overrunning the end of the buffer with alignment words.
- */
- if (to_align64 <= n64 - CACHE_LINE_SIZE_IN_DOUBLEWORDS) {
- int lines_left;
-
- /* Align out64 mod the cache line size so we can use wh64. */
- n64 -= to_align64;
- for (; to_align64 != 0; to_align64--) {
- *out64 = v64;
- out64++;
- }
-
- /* Use unsigned divide to turn this into a right shift. */
- lines_left = (unsigned)n64 / CACHE_LINE_SIZE_IN_DOUBLEWORDS;
-
- do {
- /* Only wh64 a few lines at a time, so we don't
- * exceed the maximum number of victim lines.
- */
- int x = ((lines_left < CHIP_MAX_OUTSTANDING_VICTIMS())
- ? lines_left
- : CHIP_MAX_OUTSTANDING_VICTIMS());
- uint64_t *wh = out64;
- int i = x;
- int j;
-
- lines_left -= x;
-
- do {
- __insn_wh64(wh);
- wh += CACHE_LINE_SIZE_IN_DOUBLEWORDS;
- } while (--i);
-
- for (j = x * (CACHE_LINE_SIZE_IN_DOUBLEWORDS / 4);
- j != 0; j--) {
- *out64++ = v64;
- *out64++ = v64;
- *out64++ = v64;
- *out64++ = v64;
- }
- } while (lines_left != 0);
-
- /* We processed all full lines above, so only this many
- * words remain to be processed.
- */
- n64 &= CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1;
- }
-
- /* Now handle any leftover values. */
- if (n64 != 0) {
- do {
- *out64 = v64;
- out64++;
- } while (--n64 != 0);
- }
-
- return s;
-}
-EXPORT_SYMBOL(memset);
diff --git a/arch/tile/lib/spinlock_32.c b/arch/tile/lib/spinlock_32.c
deleted file mode 100644
index db9333f2447c..000000000000
--- a/arch/tile/lib/spinlock_32.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <asm/processor.h>
-#include <arch/spr_def.h>
-
-#include "spinlock_common.h"
-
-void arch_spin_lock(arch_spinlock_t *lock)
-{
- int my_ticket;
- int iterations = 0;
- int delta;
-
- while ((my_ticket = __insn_tns((void *)&lock->next_ticket)) & 1)
- delay_backoff(iterations++);
-
- /* Increment the next ticket number, implicitly releasing tns lock. */
- lock->next_ticket = my_ticket + TICKET_QUANTUM;
-
- /* Wait until it's our turn. */
- while ((delta = my_ticket - lock->current_ticket) != 0)
- relax((128 / CYCLES_PER_RELAX_LOOP) * delta);
-}
-EXPORT_SYMBOL(arch_spin_lock);
-
-int arch_spin_trylock(arch_spinlock_t *lock)
-{
- /*
- * Grab a ticket; no need to retry if it's busy, we'll just
- * treat that the same as "locked", since someone else
- * will lock it momentarily anyway.
- */
- int my_ticket = __insn_tns((void *)&lock->next_ticket);
-
- if (my_ticket == lock->current_ticket) {
- /* Not currently locked, so lock it by keeping this ticket. */
- lock->next_ticket = my_ticket + TICKET_QUANTUM;
- /* Success! */
- return 1;
- }
-
- if (!(my_ticket & 1)) {
- /* Release next_ticket. */
- lock->next_ticket = my_ticket;
- }
-
- return 0;
-}
-EXPORT_SYMBOL(arch_spin_trylock);
-
-/*
- * The low byte is always reserved to be the marker for a "tns" operation
- * since the low bit is set to "1" by a tns. The next seven bits are
- * zeroes. The next byte holds the "next" writer value, i.e. the ticket
- * available for the next task that wants to write. The third byte holds
- * the current writer value, i.e. the writer who holds the current ticket.
- * If current == next == 0, there are no interested writers.
- */
-#define WR_NEXT_SHIFT _WR_NEXT_SHIFT
-#define WR_CURR_SHIFT _WR_CURR_SHIFT
-#define WR_WIDTH _WR_WIDTH
-#define WR_MASK ((1 << WR_WIDTH) - 1)
-
-/*
- * The last eight bits hold the active reader count. This has to be
- * zero before a writer can start to write.
- */
-#define RD_COUNT_SHIFT _RD_COUNT_SHIFT
-#define RD_COUNT_WIDTH _RD_COUNT_WIDTH
-#define RD_COUNT_MASK ((1 << RD_COUNT_WIDTH) - 1)
-
-
-/*
- * We can get the read lock if everything but the reader bits (which
- * are in the high part of the word) is zero, i.e. no active or
- * waiting writers, no tns.
- *
- * We guard the tns/store-back with an interrupt critical section to
- * preserve the semantic that the same read lock can be acquired in an
- * interrupt context.
- */
-int arch_read_trylock(arch_rwlock_t *rwlock)
-{
- u32 val;
- __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 1);
- val = __insn_tns((int *)&rwlock->lock);
- if (likely((val << _RD_COUNT_WIDTH) == 0)) {
- val += 1 << RD_COUNT_SHIFT;
- rwlock->lock = val;
- __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
- BUG_ON(val == 0); /* we don't expect wraparound */
- return 1;
- }
- if ((val & 1) == 0)
- rwlock->lock = val;
- __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
- return 0;
-}
-EXPORT_SYMBOL(arch_read_trylock);
-
-/*
- * Spin doing arch_read_trylock() until we acquire the lock.
- * ISSUE: This approach can permanently starve readers. A reader who sees
- * a writer could instead take a ticket lock (just like a writer would),
- * and atomically enter read mode (with 1 reader) when it gets the ticket.
- * This way both readers and writers would always make forward progress
- * in a finite time.
- */
-void arch_read_lock(arch_rwlock_t *rwlock)
-{
- u32 iterations = 0;
- while (unlikely(!arch_read_trylock(rwlock)))
- delay_backoff(iterations++);
-}
-EXPORT_SYMBOL(arch_read_lock);
-
-void arch_read_unlock(arch_rwlock_t *rwlock)
-{
- u32 val, iterations = 0;
-
- mb(); /* guarantee anything modified under the lock is visible */
- for (;;) {
- __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 1);
- val = __insn_tns((int *)&rwlock->lock);
- if (likely((val & 1) == 0)) {
- rwlock->lock = val - (1 << _RD_COUNT_SHIFT);
- __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
- break;
- }
- __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0);
- delay_backoff(iterations++);
- }
-}
-EXPORT_SYMBOL(arch_read_unlock);
-
-/*
- * We don't need an interrupt critical section here (unlike for
- * arch_read_lock) since we should never use a bare write lock where
- * it could be interrupted by code that could try to re-acquire it.
- */
-void arch_write_lock(arch_rwlock_t *rwlock)
-{
- /*
- * The trailing underscore on this variable (and curr_ below)
- * reminds us that the high bits are garbage; we mask them out
- * when we compare them.
- */
- u32 my_ticket_;
- u32 iterations = 0;
- u32 val = __insn_tns((int *)&rwlock->lock);
-
- if (likely(val == 0)) {
- rwlock->lock = 1 << _WR_NEXT_SHIFT;
- return;
- }
-
- /*
- * Wait until there are no readers, then bump up the next
- * field and capture the ticket value.
- */
- for (;;) {
- if (!(val & 1)) {
- if ((val >> RD_COUNT_SHIFT) == 0)
- break;
- rwlock->lock = val;
- }
- delay_backoff(iterations++);
- val = __insn_tns((int *)&rwlock->lock);
- }
-
- /* Take out the next ticket and extract my ticket value. */
- rwlock->lock = __insn_addb(val, 1 << WR_NEXT_SHIFT);
- my_ticket_ = val >> WR_NEXT_SHIFT;
-
- /* Wait until the "current" field matches our ticket. */
- for (;;) {
- u32 curr_ = val >> WR_CURR_SHIFT;
- u32 delta = ((my_ticket_ - curr_) & WR_MASK);
- if (likely(delta == 0))
- break;
-
- /* Delay based on how many lock-holders are still out there. */
- relax((256 / CYCLES_PER_RELAX_LOOP) * delta);
-
- /*
- * Get a non-tns value to check; we don't need to tns
- * it ourselves. Since we're not tns'ing, we retry
- * more rapidly to get a valid value.
- */
- while ((val = rwlock->lock) & 1)
- relax(4);
- }
-}
-EXPORT_SYMBOL(arch_write_lock);
-
-int arch_write_trylock(arch_rwlock_t *rwlock)
-{
- u32 val = __insn_tns((int *)&rwlock->lock);
-
- /*
- * If a tns is in progress, or there's a waiting or active locker,
- * or active readers, we can't take the lock, so give up.
- */
- if (unlikely(val != 0)) {
- if (!(val & 1))
- rwlock->lock = val;
- return 0;
- }
-
- /* Set the "next" field to mark it locked. */
- rwlock->lock = 1 << _WR_NEXT_SHIFT;
- return 1;
-}
-EXPORT_SYMBOL(arch_write_trylock);
-
-void arch_write_unlock(arch_rwlock_t *rwlock)
-{
- u32 val, eq, mask;
-
- mb(); /* guarantee anything modified under the lock is visible */
- val = __insn_tns((int *)&rwlock->lock);
- if (likely(val == (1 << _WR_NEXT_SHIFT))) {
- rwlock->lock = 0;
- return;
- }
- while (unlikely(val & 1)) {
- /* Limited backoff since we are the highest-priority task. */
- relax(4);
- val = __insn_tns((int *)&rwlock->lock);
- }
- mask = 1 << WR_CURR_SHIFT;
- val = __insn_addb(val, mask);
- eq = __insn_seqb(val, val << (WR_CURR_SHIFT - WR_NEXT_SHIFT));
- val = __insn_mz(eq & mask, val);
- rwlock->lock = val;
-}
-EXPORT_SYMBOL(arch_write_unlock);
diff --git a/arch/tile/lib/spinlock_64.c b/arch/tile/lib/spinlock_64.c
deleted file mode 100644
index de414c22892f..000000000000
--- a/arch/tile/lib/spinlock_64.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <asm/processor.h>
-
-#include "spinlock_common.h"
-
-/*
- * Read the spinlock value without allocating in our cache and without
- * causing an invalidation to another cpu with a copy of the cacheline.
- * This is important when we are spinning waiting for the lock.
- */
-static inline u32 arch_spin_read_noalloc(void *lock)
-{
- return atomic_cmpxchg((atomic_t *)lock, -1, -1);
-}
-
-/*
- * Wait until the high bits (current) match my ticket.
- * If we notice the overflow bit set on entry, we clear it.
- */
-void arch_spin_lock_slow(arch_spinlock_t *lock, u32 my_ticket)
-{
- if (unlikely(my_ticket & __ARCH_SPIN_NEXT_OVERFLOW)) {
- __insn_fetchand4(&lock->lock, ~__ARCH_SPIN_NEXT_OVERFLOW);
- my_ticket &= ~__ARCH_SPIN_NEXT_OVERFLOW;
- }
-
- for (;;) {
- u32 val = arch_spin_read_noalloc(lock);
- u32 delta = my_ticket - arch_spin_current(val);
- if (delta == 0)
- return;
- relax((128 / CYCLES_PER_RELAX_LOOP) * delta);
- }
-}
-EXPORT_SYMBOL(arch_spin_lock_slow);
-
-/*
- * Check the lock to see if it is plausible, and try to get it with cmpxchg().
- */
-int arch_spin_trylock(arch_spinlock_t *lock)
-{
- u32 val = arch_spin_read_noalloc(lock);
- if (unlikely(arch_spin_current(val) != arch_spin_next(val)))
- return 0;
- return cmpxchg(&lock->lock, val, (val + 1) & ~__ARCH_SPIN_NEXT_OVERFLOW)
- == val;
-}
-EXPORT_SYMBOL(arch_spin_trylock);
-
-
-/*
- * If the read lock fails due to a writer, we retry periodically
- * until the value is positive and we write our incremented reader count.
- */
-void __read_lock_failed(arch_rwlock_t *rw)
-{
- u32 val;
- int iterations = 0;
- do {
- delay_backoff(iterations++);
- val = __insn_fetchaddgez4(&rw->lock, 1);
- } while (unlikely(arch_write_val_locked(val)));
-}
-EXPORT_SYMBOL(__read_lock_failed);
-
-/*
- * If we failed because there were readers, clear the "writer" bit
- * so we don't block additional readers. Otherwise, there was another
- * writer anyway, so our "fetchor" made no difference. Then wait,
- * issuing periodic fetchor instructions, till we get the lock.
- */
-void __write_lock_failed(arch_rwlock_t *rw, u32 val)
-{
- int iterations = 0;
- do {
- if (!arch_write_val_locked(val))
- val = __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
- delay_backoff(iterations++);
- val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
- } while (val != 0);
-}
-EXPORT_SYMBOL(__write_lock_failed);
diff --git a/arch/tile/lib/spinlock_common.h b/arch/tile/lib/spinlock_common.h
deleted file mode 100644
index 6ac37509faca..000000000000
--- a/arch/tile/lib/spinlock_common.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- * This file is included into spinlock_32.c or _64.c.
- */
-
-/*
- * The mfspr in __spinlock_relax() is 5 or 6 cycles plus 2 for loop
- * overhead.
- */
-#ifdef __tilegx__
-#define CYCLES_PER_RELAX_LOOP 7
-#else
-#define CYCLES_PER_RELAX_LOOP 8
-#endif
-
-/*
- * Idle the core for CYCLES_PER_RELAX_LOOP * iterations cycles.
- */
-static inline void
-relax(int iterations)
-{
- for (/*above*/; iterations > 0; iterations--)
- __insn_mfspr(SPR_PASS);
- barrier();
-}
-
-/* Perform bounded exponential backoff.*/
-static void delay_backoff(int iterations)
-{
- u32 exponent, loops;
-
- /*
- * 2^exponent is how many times we go around the loop,
- * which takes 8 cycles. We want to start with a 16- to 31-cycle
- * loop, so we need to go around minimum 2 = 2^1 times, so we
- * bias the original value up by 1.
- */
- exponent = iterations + 1;
-
- /*
- * Don't allow exponent to exceed 7, so we have 128 loops,
- * or 1,024 (to 2,047) cycles, as our maximum.
- */
- if (exponent > 8)
- exponent = 8;
-
- loops = 1 << exponent;
-
- /* Add a randomness factor so two cpus never get in lock step. */
- loops += __insn_crc32_32(stack_pointer, get_cycles_low()) &
- (loops - 1);
-
- relax(loops);
-}
diff --git a/arch/tile/lib/strchr_32.c b/arch/tile/lib/strchr_32.c
deleted file mode 100644
index 841fe6963019..000000000000
--- a/arch/tile/lib/strchr_32.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-
-char *strchr(const char *s, int c)
-{
- int z, g;
-
- /* Get an aligned pointer. */
- const uintptr_t s_int = (uintptr_t) s;
- const uint32_t *p = (const uint32_t *)(s_int & -4);
-
- /* Create four copies of the byte for which we are looking. */
- const uint32_t goal = 0x01010101 * (uint8_t) c;
-
- /* Read the first aligned word, but force bytes before the string to
- * match neither zero nor goal (we make sure the high bit of each
- * byte is 1, and the low 7 bits are all the opposite of the goal
- * byte).
- *
- * Note that this shift count expression works because we know shift
- * counts are taken mod 32.
- */
- const uint32_t before_mask = (1 << (s_int << 3)) - 1;
- uint32_t v = (*p | before_mask) ^ (goal & __insn_shrib(before_mask, 1));
-
- uint32_t zero_matches, goal_matches;
- while (1) {
- /* Look for a terminating '\0'. */
- zero_matches = __insn_seqb(v, 0);
-
- /* Look for the goal byte. */
- goal_matches = __insn_seqb(v, goal);
-
- if (__builtin_expect(zero_matches | goal_matches, 0))
- break;
-
- v = *++p;
- }
-
- z = __insn_ctz(zero_matches);
- g = __insn_ctz(goal_matches);
-
- /* If we found c before '\0' we got a match. Note that if c == '\0'
- * then g == z, and we correctly return the address of the '\0'
- * rather than NULL.
- */
- return (g <= z) ? ((char *)p) + (g >> 3) : NULL;
-}
-EXPORT_SYMBOL(strchr);
diff --git a/arch/tile/lib/strchr_64.c b/arch/tile/lib/strchr_64.c
deleted file mode 100644
index fe6e31c06f8d..000000000000
--- a/arch/tile/lib/strchr_64.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include "string-endian.h"
-
-char *strchr(const char *s, int c)
-{
- int z, g;
-
- /* Get an aligned pointer. */
- const uintptr_t s_int = (uintptr_t) s;
- const uint64_t *p = (const uint64_t *)(s_int & -8);
-
- /* Create eight copies of the byte for which we are looking. */
- const uint64_t goal = copy_byte(c);
-
- /* Read the first aligned word, but force bytes before the string to
- * match neither zero nor goal (we make sure the high bit of each
- * byte is 1, and the low 7 bits are all the opposite of the goal
- * byte).
- */
- const uint64_t before_mask = MASK(s_int);
- uint64_t v = (*p | before_mask) ^ (goal & __insn_v1shrui(before_mask, 1));
-
- uint64_t zero_matches, goal_matches;
- while (1) {
- /* Look for a terminating '\0'. */
- zero_matches = __insn_v1cmpeqi(v, 0);
-
- /* Look for the goal byte. */
- goal_matches = __insn_v1cmpeq(v, goal);
-
- if (__builtin_expect((zero_matches | goal_matches) != 0, 0))
- break;
-
- v = *++p;
- }
-
- z = CFZ(zero_matches);
- g = CFZ(goal_matches);
-
- /* If we found c before '\0' we got a match. Note that if c == '\0'
- * then g == z, and we correctly return the address of the '\0'
- * rather than NULL.
- */
- return (g <= z) ? ((char *)p) + (g >> 3) : NULL;
-}
-EXPORT_SYMBOL(strchr);
diff --git a/arch/tile/lib/string-endian.h b/arch/tile/lib/string-endian.h
deleted file mode 100644
index 2e49cbfe9371..000000000000
--- a/arch/tile/lib/string-endian.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Provide a mask based on the pointer alignment that
- * sets up non-zero bytes before the beginning of the string.
- * The MASK expression works because shift counts are taken mod 64.
- * Also, specify how to count "first" and "last" bits
- * when the bits have been read as a word.
- */
-
-#include <asm/byteorder.h>
-
-#ifdef __LITTLE_ENDIAN
-#define MASK(x) (__insn_shl(1ULL, (x << 3)) - 1)
-#define NULMASK(x) ((2ULL << x) - 1)
-#define CFZ(x) __insn_ctz(x)
-#define REVCZ(x) __insn_clz(x)
-#else
-#define MASK(x) (__insn_shl(-2LL, ((-x << 3) - 1)))
-#define NULMASK(x) (-2LL << (63 - x))
-#define CFZ(x) __insn_clz(x)
-#define REVCZ(x) __insn_ctz(x)
-#endif
-
-/*
- * Create eight copies of the byte in a uint64_t. Byte Shuffle uses
- * the bytes of srcB as the index into the dest vector to select a
- * byte. With all indices of zero, the first byte is copied into all
- * the other bytes.
- */
-static inline uint64_t copy_byte(uint8_t byte)
-{
- return __insn_shufflebytes(byte, 0, 0);
-}
diff --git a/arch/tile/lib/strlen_32.c b/arch/tile/lib/strlen_32.c
deleted file mode 100644
index f26f88e11e4a..000000000000
--- a/arch/tile/lib/strlen_32.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-
-size_t strlen(const char *s)
-{
- /* Get an aligned pointer. */
- const uintptr_t s_int = (uintptr_t) s;
- const uint32_t *p = (const uint32_t *)(s_int & -4);
-
- /* Read the first word, but force bytes before the string to be nonzero.
- * This expression works because we know shift counts are taken mod 32.
- */
- uint32_t v = *p | ((1 << (s_int << 3)) - 1);
-
- uint32_t bits;
- while ((bits = __insn_seqb(v, 0)) == 0)
- v = *++p;
-
- return ((const char *)p) + (__insn_ctz(bits) >> 3) - s;
-}
-EXPORT_SYMBOL(strlen);
diff --git a/arch/tile/lib/strlen_64.c b/arch/tile/lib/strlen_64.c
deleted file mode 100644
index 9583fc3361fa..000000000000
--- a/arch/tile/lib/strlen_64.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include "string-endian.h"
-
-size_t strlen(const char *s)
-{
- /* Get an aligned pointer. */
- const uintptr_t s_int = (uintptr_t) s;
- const uint64_t *p = (const uint64_t *)(s_int & -8);
-
- /* Read and MASK the first word. */
- uint64_t v = *p | MASK(s_int);
-
- uint64_t bits;
- while ((bits = __insn_v1cmpeqi(v, 0)) == 0)
- v = *++p;
-
- return ((const char *)p) + (CFZ(bits) >> 3) - s;
-}
-EXPORT_SYMBOL(strlen);
diff --git a/arch/tile/lib/strnlen_32.c b/arch/tile/lib/strnlen_32.c
deleted file mode 100644
index 1434141d9e01..000000000000
--- a/arch/tile/lib/strnlen_32.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-
-size_t strnlen(const char *s, size_t count)
-{
- /* Get an aligned pointer. */
- const uintptr_t s_int = (uintptr_t) s;
- const uint32_t *p = (const uint32_t *)(s_int & -4);
- size_t bytes_read = sizeof(*p) - (s_int & (sizeof(*p) - 1));
- size_t len;
- uint32_t v, bits;
-
- /* Avoid page fault risk by not reading any bytes when count is 0. */
- if (count == 0)
- return 0;
-
- /* Read first word, but force bytes before the string to be nonzero. */
- v = *p | ((1 << ((s_int << 3) & 31)) - 1);
-
- while ((bits = __insn_seqb(v, 0)) == 0) {
- if (bytes_read >= count) {
- /* Read COUNT bytes and didn't find the terminator. */
- return count;
- }
- v = *++p;
- bytes_read += sizeof(v);
- }
-
- len = ((const char *) p) + (__insn_ctz(bits) >> 3) - s;
- return (len < count ? len : count);
-}
-EXPORT_SYMBOL(strnlen);
diff --git a/arch/tile/lib/strnlen_64.c b/arch/tile/lib/strnlen_64.c
deleted file mode 100644
index 2e8de6a5136f..000000000000
--- a/arch/tile/lib/strnlen_64.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright 2013 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include "string-endian.h"
-
-size_t strnlen(const char *s, size_t count)
-{
- /* Get an aligned pointer. */
- const uintptr_t s_int = (uintptr_t) s;
- const uint64_t *p = (const uint64_t *)(s_int & -8);
- size_t bytes_read = sizeof(*p) - (s_int & (sizeof(*p) - 1));
- size_t len;
- uint64_t v, bits;
-
- /* Avoid page fault risk by not reading any bytes when count is 0. */
- if (count == 0)
- return 0;
-
- /* Read and MASK the first word. */
- v = *p | MASK(s_int);
-
- while ((bits = __insn_v1cmpeqi(v, 0)) == 0) {
- if (bytes_read >= count) {
- /* Read COUNT bytes and didn't find the terminator. */
- return count;
- }
- v = *++p;
- bytes_read += sizeof(v);
- }
-
- len = ((const char *) p) + (CFZ(bits) >> 3) - s;
- return (len < count ? len : count);
-}
-EXPORT_SYMBOL(strnlen);
diff --git a/arch/tile/lib/uaccess.c b/arch/tile/lib/uaccess.c
deleted file mode 100644
index 030abe3ee4f1..000000000000
--- a/arch/tile/lib/uaccess.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/uaccess.h>
-#include <linux/module.h>
-
-int __range_ok(unsigned long addr, unsigned long size)
-{
- unsigned long limit = current_thread_info()->addr_limit.seg;
- return !((addr < limit && size <= limit - addr) ||
- is_arch_mappable_range(addr, size));
-}
-EXPORT_SYMBOL(__range_ok);
diff --git a/arch/tile/lib/usercopy_32.S b/arch/tile/lib/usercopy_32.S
deleted file mode 100644
index db93ad5fae25..000000000000
--- a/arch/tile/lib/usercopy_32.S
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/linkage.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <arch/chip.h>
-
-/* Access user memory, but use MMU to avoid propagating kernel exceptions. */
-
-/*
- * clear_user_asm takes the user target address in r0 and the
- * number of bytes to zero in r1.
- * It returns the number of uncopiable bytes (hopefully zero) in r0.
- * Note that we don't use a separate .fixup section here since we fall
- * through into the "fixup" code as the last straight-line bundle anyway.
- */
-STD_ENTRY(clear_user_asm)
- { bz r1, 2f; or r2, r0, r1 }
- andi r2, r2, 3
- bzt r2, .Lclear_aligned_user_asm
-1: { sb r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
- bnzt r1, 1b
-2: { move r0, r1; jrp lr }
- .pushsection __ex_table,"a"
- .align 4
- .word 1b, 2b
- .popsection
-
-.Lclear_aligned_user_asm:
-1: { sw r0, zero; addi r0, r0, 4; addi r1, r1, -4 }
- bnzt r1, 1b
-2: { move r0, r1; jrp lr }
- STD_ENDPROC(clear_user_asm)
- .pushsection __ex_table,"a"
- .align 4
- .word 1b, 2b
- .popsection
-
-/*
- * flush_user_asm takes the user target address in r0 and the
- * number of bytes to flush in r1.
- * It returns the number of unflushable bytes (hopefully zero) in r0.
- */
-STD_ENTRY(flush_user_asm)
- bz r1, 2f
- { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
- { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
- { and r0, r0, r2; and r1, r1, r2 }
- { sub r1, r1, r0 }
-1: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
- { addi r0, r0, CHIP_FLUSH_STRIDE(); bnzt r1, 1b }
-2: { move r0, r1; jrp lr }
- STD_ENDPROC(flush_user_asm)
- .pushsection __ex_table,"a"
- .align 4
- .word 1b, 2b
- .popsection
-
-/*
- * finv_user_asm takes the user target address in r0 and the
- * number of bytes to flush-invalidate in r1.
- * It returns the number of not finv'able bytes (hopefully zero) in r0.
- */
-STD_ENTRY(finv_user_asm)
- bz r1, 2f
- { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
- { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
- { and r0, r0, r2; and r1, r1, r2 }
- { sub r1, r1, r0 }
-1: { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
- { addi r0, r0, CHIP_FINV_STRIDE(); bnzt r1, 1b }
-2: { move r0, r1; jrp lr }
- STD_ENDPROC(finv_user_asm)
- .pushsection __ex_table,"a"
- .align 4
- .word 1b, 2b
- .popsection
diff --git a/arch/tile/lib/usercopy_64.S b/arch/tile/lib/usercopy_64.S
deleted file mode 100644
index 9322dc551e91..000000000000
--- a/arch/tile/lib/usercopy_64.S
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/linkage.h>
-#include <asm/errno.h>
-#include <asm/cache.h>
-#include <arch/chip.h>
-
-/* Access user memory, but use MMU to avoid propagating kernel exceptions. */
-
-/*
- * clear_user_asm takes the user target address in r0 and the
- * number of bytes to zero in r1.
- * It returns the number of uncopiable bytes (hopefully zero) in r0.
- * Note that we don't use a separate .fixup section here since we fall
- * through into the "fixup" code as the last straight-line bundle anyway.
- */
-STD_ENTRY(clear_user_asm)
- { beqz r1, 2f; or r2, r0, r1 }
- andi r2, r2, 7
- beqzt r2, .Lclear_aligned_user_asm
-1: { st1 r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
- bnezt r1, 1b
-2: { move r0, r1; jrp lr }
- .pushsection __ex_table,"a"
- .align 8
- .quad 1b, 2b
- .popsection
-
-.Lclear_aligned_user_asm:
-1: { st r0, zero; addi r0, r0, 8; addi r1, r1, -8 }
- bnezt r1, 1b
-2: { move r0, r1; jrp lr }
- STD_ENDPROC(clear_user_asm)
- .pushsection __ex_table,"a"
- .align 8
- .quad 1b, 2b
- .popsection
-
-/*
- * flush_user_asm takes the user target address in r0 and the
- * number of bytes to flush in r1.
- * It returns the number of unflushable bytes (hopefully zero) in r0.
- */
-STD_ENTRY(flush_user_asm)
- beqz r1, 2f
- { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
- { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
- { and r0, r0, r2; and r1, r1, r2 }
- { sub r1, r1, r0 }
-1: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
- { addi r0, r0, CHIP_FLUSH_STRIDE(); bnezt r1, 1b }
-2: { move r0, r1; jrp lr }
- STD_ENDPROC(flush_user_asm)
- .pushsection __ex_table,"a"
- .align 8
- .quad 1b, 2b
- .popsection
-
-/*
- * finv_user_asm takes the user target address in r0 and the
- * number of bytes to flush-invalidate in r1.
- * It returns the number of not finv'able bytes (hopefully zero) in r0.
- */
-STD_ENTRY(finv_user_asm)
- beqz r1, 2f
- { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
- { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
- { and r0, r0, r2; and r1, r1, r2 }
- { sub r1, r1, r0 }
-1: { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
- { addi r0, r0, CHIP_FINV_STRIDE(); bnezt r1, 1b }
-2: { move r0, r1; jrp lr }
- STD_ENDPROC(finv_user_asm)
- .pushsection __ex_table,"a"
- .align 8
- .quad 1b, 2b
- .popsection
diff --git a/arch/tile/mm/Makefile b/arch/tile/mm/Makefile
deleted file mode 100644
index e252aeddc17d..000000000000
--- a/arch/tile/mm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Makefile for the linux tile-specific parts of the memory manager.
-#
-
-obj-y := init.o pgtable.o fault.o extable.o elf.o \
- mmap.o homecache.o migrate_$(BITS).o
-
-obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
-obj-$(CONFIG_HIGHMEM) += highmem.o
diff --git a/arch/tile/mm/elf.c b/arch/tile/mm/elf.c
deleted file mode 100644
index 889901824400..000000000000
--- a/arch/tile/mm/elf.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/mm.h>
-#include <linux/pagemap.h>
-#include <linux/binfmts.h>
-#include <linux/compat.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/elf.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/sections.h>
-#include <asm/vdso.h>
-#include <arch/sim.h>
-
-/* Notify a running simulator, if any, that an exec just occurred. */
-static void sim_notify_exec(const char *binary_name)
-{
- unsigned char c;
- do {
- c = *binary_name++;
- __insn_mtspr(SPR_SIM_CONTROL,
- (SIM_CONTROL_OS_EXEC
- | (c << _SIM_CONTROL_OPERATOR_BITS)));
-
- } while (c);
-}
-
-static int notify_exec(struct mm_struct *mm)
-{
- int ret = 0;
- char *buf, *path;
- struct vm_area_struct *vma;
- struct file *exe_file;
-
- if (!sim_is_simulator())
- return 1;
-
- buf = (char *) __get_free_page(GFP_KERNEL);
- if (buf == NULL)
- return 0;
-
- exe_file = get_mm_exe_file(mm);
- if (exe_file == NULL)
- goto done_free;
-
- path = file_path(exe_file, buf, PAGE_SIZE);
- if (IS_ERR(path))
- goto done_put;
-
- down_read(&mm->mmap_sem);
- for (vma = current->mm->mmap; ; vma = vma->vm_next) {
- if (vma == NULL) {
- up_read(&mm->mmap_sem);
- goto done_put;
- }
- if (vma->vm_file == exe_file)
- break;
- }
-
- /*
- * Notify simulator of an ET_DYN object so we know the load address.
- * The somewhat cryptic overuse of SIM_CONTROL_DLOPEN allows us
- * to be backward-compatible with older simulator releases.
- */
- if (vma->vm_start == (ELF_ET_DYN_BASE & PAGE_MASK)) {
- char buf[64];
- int i;
-
- snprintf(buf, sizeof(buf), "0x%lx:@", vma->vm_start);
- for (i = 0; ; ++i) {
- char c = buf[i];
- __insn_mtspr(SPR_SIM_CONTROL,
- (SIM_CONTROL_DLOPEN
- | (c << _SIM_CONTROL_OPERATOR_BITS)));
- if (c == '\0') {
- ret = 1; /* success */
- break;
- }
- }
- }
- up_read(&mm->mmap_sem);
-
- sim_notify_exec(path);
-done_put:
- fput(exe_file);
-done_free:
- free_page((unsigned long)buf);
- return ret;
-}
-
-/* Notify a running simulator, if any, that we loaded an interpreter. */
-static void sim_notify_interp(unsigned long load_addr)
-{
- size_t i;
- for (i = 0; i < sizeof(load_addr); i++) {
- unsigned char c = load_addr >> (i * 8);
- __insn_mtspr(SPR_SIM_CONTROL,
- (SIM_CONTROL_OS_INTERP
- | (c << _SIM_CONTROL_OPERATOR_BITS)));
- }
-}
-
-
-int arch_setup_additional_pages(struct linux_binprm *bprm,
- int executable_stack)
-{
- struct mm_struct *mm = current->mm;
- int retval = 0;
-
- /*
- * Notify the simulator that an exec just occurred.
- * If we can't find the filename of the mapping, just use
- * whatever was passed as the linux_binprm filename.
- */
- if (!notify_exec(mm))
- sim_notify_exec(bprm->filename);
-
- down_write(&mm->mmap_sem);
-
- retval = setup_vdso_pages();
-
-#ifndef __tilegx__
- /*
- * Set up a user-interrupt mapping here; the user can't
- * create one themselves since it is above TASK_SIZE.
- * We make it unwritable by default, so the model for adding
- * interrupt vectors always involves an mprotect.
- */
- if (!retval) {
- unsigned long addr = MEM_USER_INTRPT;
- addr = mmap_region(NULL, addr, INTRPT_SIZE,
- VM_READ|VM_EXEC|
- VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC, 0, NULL);
- if (addr > (unsigned long) -PAGE_SIZE)
- retval = (int) addr;
- }
-#endif
-
- up_write(&mm->mmap_sem);
-
- return retval;
-}
-
-
-void elf_plat_init(struct pt_regs *regs, unsigned long load_addr)
-{
- /* Zero all registers. */
- memset(regs, 0, sizeof(*regs));
-
- /* Report the interpreter's load address. */
- sim_notify_interp(load_addr);
-}
diff --git a/arch/tile/mm/extable.c b/arch/tile/mm/extable.c
deleted file mode 100644
index aeaf20c7aaa4..000000000000
--- a/arch/tile/mm/extable.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/extable.h>
-#include <linux/spinlock.h>
-#include <linux/uaccess.h>
-
-int fixup_exception(struct pt_regs *regs)
-{
- const struct exception_table_entry *fixup;
-
- fixup = search_exception_tables(regs->pc);
- if (fixup) {
- regs->pc = fixup->fixup;
- return 1;
- }
-
- return 0;
-}
diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c
deleted file mode 100644
index f58fa06a2214..000000000000
--- a/arch/tile/mm/fault.c
+++ /dev/null
@@ -1,924 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * From i386 code copyright (C) 1995 Linus Torvalds
- */
-
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/sched/debug.h>
-#include <linux/sched/task.h>
-#include <linux/sched/task_stack.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/tty.h>
-#include <linux/vt_kern.h> /* For unblank_screen() */
-#include <linux/highmem.h>
-#include <linux/extable.h>
-#include <linux/kprobes.h>
-#include <linux/hugetlb.h>
-#include <linux/syscalls.h>
-#include <linux/uaccess.h>
-#include <linux/kdebug.h>
-
-#include <asm/pgalloc.h>
-#include <asm/sections.h>
-#include <asm/traps.h>
-#include <asm/syscalls.h>
-
-#include <arch/interrupts.h>
-
-static noinline void force_sig_info_fault(const char *type, int si_signo,
- int si_code, unsigned long address,
- int fault_num,
- struct task_struct *tsk,
- struct pt_regs *regs)
-{
- siginfo_t info;
-
- if (unlikely(tsk->pid < 2)) {
- panic("Signal %d (code %d) at %#lx sent to %s!",
- si_signo, si_code & 0xffff, address,
- is_idle_task(tsk) ? "the idle task" : "init");
- }
-
- info.si_signo = si_signo;
- info.si_errno = 0;
- info.si_code = si_code;
- info.si_addr = (void __user *)address;
- info.si_trapno = fault_num;
- trace_unhandled_signal(type, regs, address, si_signo);
- force_sig_info(si_signo, &info, tsk);
-}
-
-#ifndef __tilegx__
-/*
- * Synthesize the fault a PL0 process would get by doing a word-load of
- * an unaligned address or a high kernel address.
- */
-SYSCALL_DEFINE1(cmpxchg_badaddr, unsigned long, address)
-{
- struct pt_regs *regs = current_pt_regs();
-
- if (address >= PAGE_OFFSET)
- force_sig_info_fault("atomic segfault", SIGSEGV, SEGV_MAPERR,
- address, INT_DTLB_MISS, current, regs);
- else
- force_sig_info_fault("atomic alignment fault", SIGBUS,
- BUS_ADRALN, address,
- INT_UNALIGN_DATA, current, regs);
-
- /*
- * Adjust pc to point at the actual instruction, which is unusual
- * for syscalls normally, but is appropriate when we are claiming
- * that a syscall swint1 caused a page fault or bus error.
- */
- regs->pc -= 8;
-
- /*
- * Mark this as a caller-save interrupt, like a normal page fault,
- * so that when we go through the signal handler path we will
- * properly restore r0, r1, and r2 for the signal handler arguments.
- */
- regs->flags |= PT_FLAGS_CALLER_SAVES;
-
- return 0;
-}
-#endif
-
-static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address)
-{
- unsigned index = pgd_index(address);
- pgd_t *pgd_k;
- pud_t *pud, *pud_k;
- pmd_t *pmd, *pmd_k;
-
- pgd += index;
- pgd_k = init_mm.pgd + index;
-
- if (!pgd_present(*pgd_k))
- return NULL;
-
- pud = pud_offset(pgd, address);
- pud_k = pud_offset(pgd_k, address);
- if (!pud_present(*pud_k))
- return NULL;
-
- pmd = pmd_offset(pud, address);
- pmd_k = pmd_offset(pud_k, address);
- if (!pmd_present(*pmd_k))
- return NULL;
- if (!pmd_present(*pmd))
- set_pmd(pmd, *pmd_k);
- else
- BUG_ON(pmd_ptfn(*pmd) != pmd_ptfn(*pmd_k));
- return pmd_k;
-}
-
-/*
- * Handle a fault on the vmalloc area.
- */
-static inline int vmalloc_fault(pgd_t *pgd, unsigned long address)
-{
- pmd_t *pmd_k;
- pte_t *pte_k;
-
- /* Make sure we are in vmalloc area */
- if (!(address >= VMALLOC_START && address < VMALLOC_END))
- return -1;
-
- /*
- * Synchronize this task's top level page-table
- * with the 'reference' page table.
- */
- pmd_k = vmalloc_sync_one(pgd, address);
- if (!pmd_k)
- return -1;
- pte_k = pte_offset_kernel(pmd_k, address);
- if (!pte_present(*pte_k))
- return -1;
- return 0;
-}
-
-/* Wait until this PTE has completed migration. */
-static void wait_for_migration(pte_t *pte)
-{
- if (pte_migrating(*pte)) {
- /*
- * Wait until the migrater fixes up this pte.
- * We scale the loop count by the clock rate so we'll wait for
- * a few seconds here.
- */
- int retries = 0;
- int bound = get_clock_rate();
- while (pte_migrating(*pte)) {
- barrier();
- if (++retries > bound)
- panic("Hit migrating PTE (%#llx) and page PFN %#lx still migrating",
- pte->val, pte_pfn(*pte));
- }
- }
-}
-
-/*
- * It's not generally safe to use "current" to get the page table pointer,
- * since we might be running an oprofile interrupt in the middle of a
- * task switch.
- */
-static pgd_t *get_current_pgd(void)
-{
- HV_Context ctx = hv_inquire_context();
- unsigned long pgd_pfn = ctx.page_table >> PAGE_SHIFT;
- struct page *pgd_page = pfn_to_page(pgd_pfn);
- BUG_ON(PageHighMem(pgd_page));
- return (pgd_t *) __va(ctx.page_table);
-}
-
-/*
- * We can receive a page fault from a migrating PTE at any time.
- * Handle it by just waiting until the fault resolves.
- *
- * It's also possible to get a migrating kernel PTE that resolves
- * itself during the downcall from hypervisor to Linux. We just check
- * here to see if the PTE seems valid, and if so we retry it.
- *
- * NOTE! We MUST NOT take any locks for this case. We may be in an
- * interrupt or a critical region, and must do as little as possible.
- * Similarly, we can't use atomic ops here, since we may be handling a
- * fault caused by an atomic op access.
- *
- * If we find a migrating PTE while we're in an NMI context, and we're
- * at a PC that has a registered exception handler, we don't wait,
- * since this thread may (e.g.) have been interrupted while migrating
- * its own stack, which would then cause us to self-deadlock.
- */
-static int handle_migrating_pte(pgd_t *pgd, int fault_num,
- unsigned long address, unsigned long pc,
- int is_kernel_mode, int write)
-{
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- pte_t pteval;
-
- if (pgd_addr_invalid(address))
- return 0;
-
- pgd += pgd_index(address);
- pud = pud_offset(pgd, address);
- if (!pud || !pud_present(*pud))
- return 0;
- pmd = pmd_offset(pud, address);
- if (!pmd || !pmd_present(*pmd))
- return 0;
- pte = pmd_huge_page(*pmd) ? ((pte_t *)pmd) :
- pte_offset_kernel(pmd, address);
- pteval = *pte;
- if (pte_migrating(pteval)) {
- if (in_nmi() && search_exception_tables(pc))
- return 0;
- wait_for_migration(pte);
- return 1;
- }
-
- if (!is_kernel_mode || !pte_present(pteval))
- return 0;
- if (fault_num == INT_ITLB_MISS) {
- if (pte_exec(pteval))
- return 1;
- } else if (write) {
- if (pte_write(pteval))
- return 1;
- } else {
- if (pte_read(pteval))
- return 1;
- }
-
- return 0;
-}
-
-/*
- * This routine is responsible for faulting in user pages.
- * It passes the work off to one of the appropriate routines.
- * It returns true if the fault was successfully handled.
- */
-static int handle_page_fault(struct pt_regs *regs,
- int fault_num,
- int is_page_fault,
- unsigned long address,
- int write)
-{
- struct task_struct *tsk;
- struct mm_struct *mm;
- struct vm_area_struct *vma;
- unsigned long stack_offset;
- int fault;
- int si_code;
- int is_kernel_mode;
- pgd_t *pgd;
- unsigned int flags;
-
- /* on TILE, protection faults are always writes */
- if (!is_page_fault)
- write = 1;
-
- flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
-
- is_kernel_mode = !user_mode(regs);
-
- tsk = validate_current();
-
- /*
- * Check to see if we might be overwriting the stack, and bail
- * out if so. The page fault code is a relatively likely
- * place to get trapped in an infinite regress, and once we
- * overwrite the whole stack, it becomes very hard to recover.
- */
- stack_offset = stack_pointer & (THREAD_SIZE-1);
- if (stack_offset < THREAD_SIZE / 8) {
- pr_alert("Potential stack overrun: sp %#lx\n", stack_pointer);
- show_regs(regs);
- pr_alert("Killing current process %d/%s\n",
- tsk->pid, tsk->comm);
- do_group_exit(SIGKILL);
- }
-
- /*
- * Early on, we need to check for migrating PTE entries;
- * see homecache.c. If we find a migrating PTE, we wait until
- * the backing page claims to be done migrating, then we proceed.
- * For kernel PTEs, we rewrite the PTE and return and retry.
- * Otherwise, we treat the fault like a normal "no PTE" fault,
- * rather than trying to patch up the existing PTE.
- */
- pgd = get_current_pgd();
- if (handle_migrating_pte(pgd, fault_num, address, regs->pc,
- is_kernel_mode, write))
- return 1;
-
- si_code = SEGV_MAPERR;
-
- /*
- * We fault-in kernel-space virtual memory on-demand. The
- * 'reference' page table is init_mm.pgd.
- *
- * NOTE! We MUST NOT take any locks for this case. We may
- * be in an interrupt or a critical region, and should
- * only copy the information from the master page table,
- * nothing more.
- *
- * This verifies that the fault happens in kernel space
- * and that the fault was not a protection fault.
- */
- if (unlikely(address >= TASK_SIZE &&
- !is_arch_mappable_range(address, 0))) {
- if (is_kernel_mode && is_page_fault &&
- vmalloc_fault(pgd, address) >= 0)
- return 1;
- /*
- * Don't take the mm semaphore here. If we fixup a prefetch
- * fault we could otherwise deadlock.
- */
- mm = NULL; /* happy compiler */
- vma = NULL;
- goto bad_area_nosemaphore;
- }
-
- /*
- * If we're trying to touch user-space addresses, we must
- * be either at PL0, or else with interrupts enabled in the
- * kernel, so either way we can re-enable interrupts here
- * unless we are doing atomic access to user space with
- * interrupts disabled.
- */
- if (!(regs->flags & PT_FLAGS_DISABLE_IRQ))
- local_irq_enable();
-
- mm = tsk->mm;
-
- /*
- * If we're in an interrupt, have no user context or are running in an
- * region with pagefaults disabled then we must not take the fault.
- */
- if (pagefault_disabled() || !mm) {
- vma = NULL; /* happy compiler */
- goto bad_area_nosemaphore;
- }
-
- if (!is_kernel_mode)
- flags |= FAULT_FLAG_USER;
-
- /*
- * When running in the kernel we expect faults to occur only to
- * addresses in user space. All other faults represent errors in the
- * kernel and should generate an OOPS. Unfortunately, in the case of an
- * erroneous fault occurring in a code path which already holds mmap_sem
- * we will deadlock attempting to validate the fault against the
- * address space. Luckily the kernel only validly references user
- * space from well defined areas of code, which are listed in the
- * exceptions table.
- *
- * As the vast majority of faults will be valid we will only perform
- * the source reference check when there is a possibility of a deadlock.
- * Attempt to lock the address space, if we cannot we then validate the
- * source. If this is invalid we can skip the address space check,
- * thus avoiding the deadlock.
- */
- if (!down_read_trylock(&mm->mmap_sem)) {
- if (is_kernel_mode &&
- !search_exception_tables(regs->pc)) {
- vma = NULL; /* happy compiler */
- goto bad_area_nosemaphore;
- }
-
-retry:
- down_read(&mm->mmap_sem);
- }
-
- vma = find_vma(mm, address);
- if (!vma)
- goto bad_area;
- if (vma->vm_start <= address)
- goto good_area;
- if (!(vma->vm_flags & VM_GROWSDOWN))
- goto bad_area;
- if (regs->sp < PAGE_OFFSET) {
- /*
- * accessing the stack below sp is always a bug.
- */
- if (address < regs->sp)
- goto bad_area;
- }
- if (expand_stack(vma, address))
- goto bad_area;
-
-/*
- * Ok, we have a good vm_area for this memory access, so
- * we can handle it..
- */
-good_area:
- si_code = SEGV_ACCERR;
- if (fault_num == INT_ITLB_MISS) {
- if (!(vma->vm_flags & VM_EXEC))
- goto bad_area;
- } else if (write) {
-#ifdef TEST_VERIFY_AREA
- if (!is_page_fault && regs->cs == KERNEL_CS)
- pr_err("WP fault at " REGFMT "\n", regs->eip);
-#endif
- if (!(vma->vm_flags & VM_WRITE))
- goto bad_area;
- flags |= FAULT_FLAG_WRITE;
- } else {
- if (!is_page_fault || !(vma->vm_flags & VM_READ))
- goto bad_area;
- }
-
- /*
- * If for any reason at all we couldn't handle the fault,
- * make sure we exit gracefully rather than endlessly redo
- * the fault.
- */
- fault = handle_mm_fault(vma, address, flags);
-
- if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
- return 0;
-
- if (unlikely(fault & VM_FAULT_ERROR)) {
- if (fault & VM_FAULT_OOM)
- goto out_of_memory;
- else if (fault & VM_FAULT_SIGSEGV)
- goto bad_area;
- else if (fault & VM_FAULT_SIGBUS)
- goto do_sigbus;
- BUG();
- }
- if (flags & FAULT_FLAG_ALLOW_RETRY) {
- if (fault & VM_FAULT_MAJOR)
- tsk->maj_flt++;
- else
- tsk->min_flt++;
- if (fault & VM_FAULT_RETRY) {
- flags &= ~FAULT_FLAG_ALLOW_RETRY;
- flags |= FAULT_FLAG_TRIED;
-
- /*
- * No need to up_read(&mm->mmap_sem) as we would
- * have already released it in __lock_page_or_retry
- * in mm/filemap.c.
- */
- goto retry;
- }
- }
-
-#if CHIP_HAS_TILE_DMA()
- /* If this was a DMA TLB fault, restart the DMA engine. */
- switch (fault_num) {
- case INT_DMATLB_MISS:
- case INT_DMATLB_MISS_DWNCL:
- case INT_DMATLB_ACCESS:
- case INT_DMATLB_ACCESS_DWNCL:
- __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__REQUEST_MASK);
- break;
- }
-#endif
-
- up_read(&mm->mmap_sem);
- return 1;
-
-/*
- * Something tried to access memory that isn't in our memory map..
- * Fix it, but check if it's kernel or user first..
- */
-bad_area:
- up_read(&mm->mmap_sem);
-
-bad_area_nosemaphore:
- /* User mode accesses just cause a SIGSEGV */
- if (!is_kernel_mode) {
- /*
- * It's possible to have interrupts off here.
- */
- local_irq_enable();
-
- force_sig_info_fault("segfault", SIGSEGV, si_code, address,
- fault_num, tsk, regs);
- return 0;
- }
-
-no_context:
- /* Are we prepared to handle this kernel fault? */
- if (fixup_exception(regs))
- return 0;
-
-/*
- * Oops. The kernel tried to access some bad page. We'll have to
- * terminate things with extreme prejudice.
- */
-
- bust_spinlocks(1);
-
- /* FIXME: no lookup_address() yet */
-#ifdef SUPPORT_LOOKUP_ADDRESS
- if (fault_num == INT_ITLB_MISS) {
- pte_t *pte = lookup_address(address);
-
- if (pte && pte_present(*pte) && !pte_exec_kernel(*pte))
- pr_crit("kernel tried to execute non-executable page - exploit attempt? (uid: %d)\n",
- current->uid);
- }
-#endif
- if (address < PAGE_SIZE)
- pr_alert("Unable to handle kernel NULL pointer dereference\n");
- else
- pr_alert("Unable to handle kernel paging request\n");
- pr_alert(" at virtual address " REGFMT ", pc " REGFMT "\n",
- address, regs->pc);
-
- show_regs(regs);
-
- if (unlikely(tsk->pid < 2)) {
- panic("Kernel page fault running %s!",
- is_idle_task(tsk) ? "the idle task" : "init");
- }
-
- /*
- * More FIXME: we should probably copy the i386 here and
- * implement a generic die() routine. Not today.
- */
-#ifdef SUPPORT_DIE
- die("Oops", regs);
-#endif
- bust_spinlocks(1);
-
- do_group_exit(SIGKILL);
-
-/*
- * We ran out of memory, or some other thing happened to us that made
- * us unable to handle the page fault gracefully.
- */
-out_of_memory:
- up_read(&mm->mmap_sem);
- if (is_kernel_mode)
- goto no_context;
- pagefault_out_of_memory();
- return 0;
-
-do_sigbus:
- up_read(&mm->mmap_sem);
-
- /* Kernel mode? Handle exceptions or die */
- if (is_kernel_mode)
- goto no_context;
-
- force_sig_info_fault("bus error", SIGBUS, BUS_ADRERR, address,
- fault_num, tsk, regs);
- return 0;
-}
-
-#ifndef __tilegx__
-
-/* We must release ICS before panicking or we won't get anywhere. */
-#define ics_panic(fmt, ...) \
-do { \
- __insn_mtspr(SPR_INTERRUPT_CRITICAL_SECTION, 0); \
- panic(fmt, ##__VA_ARGS__); \
-} while (0)
-
-/*
- * When we take an ITLB or DTLB fault or access violation in the
- * supervisor while the critical section bit is set, the hypervisor is
- * reluctant to write new values into the EX_CONTEXT_K_x registers,
- * since that might indicate we have not yet squirreled the SPR
- * contents away and can thus safely take a recursive interrupt.
- * Accordingly, the hypervisor passes us the PC via SYSTEM_SAVE_K_2.
- *
- * Note that this routine is called before homecache_tlb_defer_enter(),
- * which means that we can properly unlock any atomics that might
- * be used there (good), but also means we must be very sensitive
- * to not touch any data structures that might be located in memory
- * that could migrate, as we could be entering the kernel on a dataplane
- * cpu that has been deferring kernel TLB updates. This means, for
- * example, that we can't migrate init_mm or its pgd.
- */
-struct intvec_state do_page_fault_ics(struct pt_regs *regs, int fault_num,
- unsigned long address,
- unsigned long info)
-{
- unsigned long pc = info & ~1;
- int write = info & 1;
- pgd_t *pgd = get_current_pgd();
-
- /* Retval is 1 at first since we will handle the fault fully. */
- struct intvec_state state = {
- do_page_fault, fault_num, address, write, 1
- };
-
- /* Validate that we are plausibly in the right routine. */
- if ((pc & 0x7) != 0 || pc < PAGE_OFFSET ||
- (fault_num != INT_DTLB_MISS &&
- fault_num != INT_DTLB_ACCESS)) {
- unsigned long old_pc = regs->pc;
- regs->pc = pc;
- ics_panic("Bad ICS page fault args: old PC %#lx, fault %d/%d at %#lx",
- old_pc, fault_num, write, address);
- }
-
- /* We might be faulting on a vmalloc page, so check that first. */
- if (fault_num != INT_DTLB_ACCESS && vmalloc_fault(pgd, address) >= 0)
- return state;
-
- /*
- * If we faulted with ICS set in sys_cmpxchg, we are providing
- * a user syscall service that should generate a signal on
- * fault. We didn't set up a kernel stack on initial entry to
- * sys_cmpxchg, but instead had one set up by the fault, which
- * (because sys_cmpxchg never releases ICS) came to us via the
- * SYSTEM_SAVE_K_2 mechanism, and thus EX_CONTEXT_K_[01] are
- * still referencing the original user code. We release the
- * atomic lock and rewrite pt_regs so that it appears that we
- * came from user-space directly, and after we finish the
- * fault we'll go back to user space and re-issue the swint.
- * This way the backtrace information is correct if we need to
- * emit a stack dump at any point while handling this.
- *
- * Must match register use in sys_cmpxchg().
- */
- if (pc >= (unsigned long) sys_cmpxchg &&
- pc < (unsigned long) __sys_cmpxchg_end) {
-#ifdef CONFIG_SMP
- /* Don't unlock before we could have locked. */
- if (pc >= (unsigned long)__sys_cmpxchg_grab_lock) {
- int *lock_ptr = (int *)(regs->regs[ATOMIC_LOCK_REG]);
- __atomic_fault_unlock(lock_ptr);
- }
-#endif
- regs->sp = regs->regs[27];
- }
-
- /*
- * We can also fault in the atomic assembly, in which
- * case we use the exception table to do the first-level fixup.
- * We may re-fixup again in the real fault handler if it
- * turns out the faulting address is just bad, and not,
- * for example, migrating.
- */
- else if (pc >= (unsigned long) __start_atomic_asm_code &&
- pc < (unsigned long) __end_atomic_asm_code) {
- const struct exception_table_entry *fixup;
-#ifdef CONFIG_SMP
- /* Unlock the atomic lock. */
- int *lock_ptr = (int *)(regs->regs[ATOMIC_LOCK_REG]);
- __atomic_fault_unlock(lock_ptr);
-#endif
- fixup = search_exception_tables(pc);
- if (!fixup)
- ics_panic("ICS atomic fault not in table: PC %#lx, fault %d",
- pc, fault_num);
- regs->pc = fixup->fixup;
- regs->ex1 = PL_ICS_EX1(KERNEL_PL, 0);
- }
-
- /*
- * Now that we have released the atomic lock (if necessary),
- * it's safe to spin if the PTE that caused the fault was migrating.
- */
- if (fault_num == INT_DTLB_ACCESS)
- write = 1;
- if (handle_migrating_pte(pgd, fault_num, address, pc, 1, write))
- return state;
-
- /* Return zero so that we continue on with normal fault handling. */
- state.retval = 0;
- return state;
-}
-
-#endif /* !__tilegx__ */
-
-/*
- * This routine handles page faults. It determines the address, and the
- * problem, and then passes it handle_page_fault() for normal DTLB and
- * ITLB issues, and for DMA or SN processor faults when we are in user
- * space. For the latter, if we're in kernel mode, we just save the
- * interrupt away appropriately and return immediately. We can't do
- * page faults for user code while in kernel mode.
- */
-static inline void __do_page_fault(struct pt_regs *regs, int fault_num,
- unsigned long address, unsigned long write)
-{
- int is_page_fault;
-
-#ifdef CONFIG_KPROBES
- /*
- * This is to notify the fault handler of the kprobes. The
- * exception code is redundant as it is also carried in REGS,
- * but we pass it anyhow.
- */
- if (notify_die(DIE_PAGE_FAULT, "page fault", regs, -1,
- regs->faultnum, SIGSEGV) == NOTIFY_STOP)
- return;
-#endif
-
-#ifdef __tilegx__
- /*
- * We don't need early do_page_fault_ics() support, since unlike
- * Pro we don't need to worry about unlocking the atomic locks.
- * There is only one current case in GX where we touch any memory
- * under ICS other than our own kernel stack, and we handle that
- * here. (If we crash due to trying to touch our own stack,
- * we're in too much trouble for C code to help out anyway.)
- */
- if (write & ~1) {
- unsigned long pc = write & ~1;
- if (pc >= (unsigned long) __start_unalign_asm_code &&
- pc < (unsigned long) __end_unalign_asm_code) {
- struct thread_info *ti = current_thread_info();
- /*
- * Our EX_CONTEXT is still what it was from the
- * initial unalign exception, but now we've faulted
- * on the JIT page. We would like to complete the
- * page fault however is appropriate, and then retry
- * the instruction that caused the unalign exception.
- * Our state has been "corrupted" by setting the low
- * bit in "sp", and stashing r0..r3 in the
- * thread_info area, so we revert all of that, then
- * continue as if this were a normal page fault.
- */
- regs->sp &= ~1UL;
- regs->regs[0] = ti->unalign_jit_tmp[0];
- regs->regs[1] = ti->unalign_jit_tmp[1];
- regs->regs[2] = ti->unalign_jit_tmp[2];
- regs->regs[3] = ti->unalign_jit_tmp[3];
- write &= 1;
- } else {
- pr_alert("%s/%d: ICS set at page fault at %#lx: %#lx\n",
- current->comm, current->pid, pc, address);
- show_regs(regs);
- do_group_exit(SIGKILL);
- }
- }
-#else
- /* This case should have been handled by do_page_fault_ics(). */
- BUG_ON(write & ~1);
-#endif
-
-#if CHIP_HAS_TILE_DMA()
- /*
- * If it's a DMA fault, suspend the transfer while we're
- * handling the miss; we'll restart after it's handled. If we
- * don't suspend, it's possible that this process could swap
- * out and back in, and restart the engine since the DMA is
- * still 'running'.
- */
- if (fault_num == INT_DMATLB_MISS ||
- fault_num == INT_DMATLB_ACCESS ||
- fault_num == INT_DMATLB_MISS_DWNCL ||
- fault_num == INT_DMATLB_ACCESS_DWNCL) {
- __insn_mtspr(SPR_DMA_CTR, SPR_DMA_CTR__SUSPEND_MASK);
- while (__insn_mfspr(SPR_DMA_USER_STATUS) &
- SPR_DMA_STATUS__BUSY_MASK)
- ;
- }
-#endif
-
- /* Validate fault num and decide if this is a first-time page fault. */
- switch (fault_num) {
- case INT_ITLB_MISS:
- case INT_DTLB_MISS:
-#if CHIP_HAS_TILE_DMA()
- case INT_DMATLB_MISS:
- case INT_DMATLB_MISS_DWNCL:
-#endif
- is_page_fault = 1;
- break;
-
- case INT_DTLB_ACCESS:
-#if CHIP_HAS_TILE_DMA()
- case INT_DMATLB_ACCESS:
- case INT_DMATLB_ACCESS_DWNCL:
-#endif
- is_page_fault = 0;
- break;
-
- default:
- panic("Bad fault number %d in do_page_fault", fault_num);
- }
-
-#if CHIP_HAS_TILE_DMA()
- if (!user_mode(regs)) {
- struct async_tlb *async;
- switch (fault_num) {
-#if CHIP_HAS_TILE_DMA()
- case INT_DMATLB_MISS:
- case INT_DMATLB_ACCESS:
- case INT_DMATLB_MISS_DWNCL:
- case INT_DMATLB_ACCESS_DWNCL:
- async = &current->thread.dma_async_tlb;
- break;
-#endif
- default:
- async = NULL;
- }
- if (async) {
-
- /*
- * No vmalloc check required, so we can allow
- * interrupts immediately at this point.
- */
- local_irq_enable();
-
- set_thread_flag(TIF_ASYNC_TLB);
- if (async->fault_num != 0) {
- panic("Second async fault %d; old fault was %d (%#lx/%ld)",
- fault_num, async->fault_num,
- address, write);
- }
- BUG_ON(fault_num == 0);
- async->fault_num = fault_num;
- async->is_fault = is_page_fault;
- async->is_write = write;
- async->address = address;
- return;
- }
- }
-#endif
-
- handle_page_fault(regs, fault_num, is_page_fault, address, write);
-}
-
-void do_page_fault(struct pt_regs *regs, int fault_num,
- unsigned long address, unsigned long write)
-{
- __do_page_fault(regs, fault_num, address, write);
-}
-
-#if CHIP_HAS_TILE_DMA()
-/*
- * This routine effectively re-issues asynchronous page faults
- * when we are returning to user space.
- */
-void do_async_page_fault(struct pt_regs *regs)
-{
- struct async_tlb *async = &current->thread.dma_async_tlb;
-
- /*
- * Clear thread flag early. If we re-interrupt while processing
- * code here, we will reset it and recall this routine before
- * returning to user space.
- */
- clear_thread_flag(TIF_ASYNC_TLB);
-
- if (async->fault_num) {
- /*
- * Clear async->fault_num before calling the page-fault
- * handler so that if we re-interrupt before returning
- * from the function we have somewhere to put the
- * information from the new interrupt.
- */
- int fault_num = async->fault_num;
- async->fault_num = 0;
- handle_page_fault(regs, fault_num, async->is_fault,
- async->address, async->is_write);
- }
-}
-#endif /* CHIP_HAS_TILE_DMA() */
-
-
-void vmalloc_sync_all(void)
-{
-#ifdef __tilegx__
- /* Currently all L1 kernel pmd's are static and shared. */
- BUILD_BUG_ON(pgd_index(VMALLOC_END - PAGE_SIZE) !=
- pgd_index(VMALLOC_START));
-#else
- /*
- * Note that races in the updates of insync and start aren't
- * problematic: insync can only get set bits added, and updates to
- * start are only improving performance (without affecting correctness
- * if undone).
- */
- static DECLARE_BITMAP(insync, PTRS_PER_PGD);
- static unsigned long start = PAGE_OFFSET;
- unsigned long address;
-
- BUILD_BUG_ON(PAGE_OFFSET & ~PGDIR_MASK);
- for (address = start; address >= PAGE_OFFSET; address += PGDIR_SIZE) {
- if (!test_bit(pgd_index(address), insync)) {
- unsigned long flags;
- struct list_head *pos;
-
- spin_lock_irqsave(&pgd_lock, flags);
- list_for_each(pos, &pgd_list)
- if (!vmalloc_sync_one(list_to_pgd(pos),
- address)) {
- /* Must be at first entry in list. */
- BUG_ON(pos != pgd_list.next);
- break;
- }
- spin_unlock_irqrestore(&pgd_lock, flags);
- if (pos != pgd_list.next)
- set_bit(pgd_index(address), insync);
- }
- if (address == start && test_bit(pgd_index(address), insync))
- start = address + PGDIR_SIZE;
- }
-#endif
-}
diff --git a/arch/tile/mm/highmem.c b/arch/tile/mm/highmem.c
deleted file mode 100644
index eca28551b22d..000000000000
--- a/arch/tile/mm/highmem.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/highmem.h>
-#include <linux/module.h>
-#include <linux/pagemap.h>
-#include <asm/homecache.h>
-
-#define kmap_get_pte(vaddr) \
- pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)),\
- (vaddr)), (vaddr))
-
-
-void *kmap(struct page *page)
-{
- void *kva;
- unsigned long flags;
- pte_t *ptep;
-
- might_sleep();
- if (!PageHighMem(page))
- return page_address(page);
- kva = kmap_high(page);
-
- /*
- * Rewrite the PTE under the lock. This ensures that the page
- * is not currently migrating.
- */
- ptep = kmap_get_pte((unsigned long)kva);
- flags = homecache_kpte_lock();
- set_pte_at(&init_mm, kva, ptep, mk_pte(page, page_to_kpgprot(page)));
- homecache_kpte_unlock(flags);
-
- return kva;
-}
-EXPORT_SYMBOL(kmap);
-
-void kunmap(struct page *page)
-{
- if (in_interrupt())
- BUG();
- if (!PageHighMem(page))
- return;
- kunmap_high(page);
-}
-EXPORT_SYMBOL(kunmap);
-
-/*
- * Describe a single atomic mapping of a page on a given cpu at a
- * given address, and allow it to be linked into a list.
- */
-struct atomic_mapped_page {
- struct list_head list;
- struct page *page;
- int cpu;
- unsigned long va;
-};
-
-static spinlock_t amp_lock = __SPIN_LOCK_UNLOCKED(&amp_lock);
-static struct list_head amp_list = LIST_HEAD_INIT(amp_list);
-
-/*
- * Combining this structure with a per-cpu declaration lets us give
- * each cpu an atomic_mapped_page structure per type.
- */
-struct kmap_amps {
- struct atomic_mapped_page per_type[KM_TYPE_NR];
-};
-static DEFINE_PER_CPU(struct kmap_amps, amps);
-
-/*
- * Add a page and va, on this cpu, to the list of kmap_atomic pages,
- * and write the new pte to memory. Writing the new PTE under the
- * lock guarantees that it is either on the list before migration starts
- * (if we won the race), or set_pte() sets the migrating bit in the PTE
- * (if we lost the race). And doing it under the lock guarantees
- * that when kmap_atomic_fix_one_pte() comes along, it finds a valid
- * PTE in memory, iff the mapping is still on the amp_list.
- *
- * Finally, doing it under the lock lets us safely examine the page
- * to see if it is immutable or not, for the generic kmap_atomic() case.
- * If we examine it earlier we are exposed to a race where it looks
- * writable earlier, but becomes immutable before we write the PTE.
- */
-static void kmap_atomic_register(struct page *page, int type,
- unsigned long va, pte_t *ptep, pte_t pteval)
-{
- unsigned long flags;
- struct atomic_mapped_page *amp;
-
- flags = homecache_kpte_lock();
- spin_lock(&amp_lock);
-
- /* With interrupts disabled, now fill in the per-cpu info. */
- amp = this_cpu_ptr(&amps.per_type[type]);
- amp->page = page;
- amp->cpu = smp_processor_id();
- amp->va = va;
-
- /* For generic kmap_atomic(), choose the PTE writability now. */
- if (!pte_read(pteval))
- pteval = mk_pte(page, page_to_kpgprot(page));
-
- list_add(&amp->list, &amp_list);
- set_pte(ptep, pteval);
-
- spin_unlock(&amp_lock);
- homecache_kpte_unlock(flags);
-}
-
-/*
- * Remove a page and va, on this cpu, from the list of kmap_atomic pages.
- * Linear-time search, but we count on the lists being short.
- * We don't need to adjust the PTE under the lock (as opposed to the
- * kmap_atomic_register() case), since we're just unconditionally
- * zeroing the PTE after it's off the list.
- */
-static void kmap_atomic_unregister(struct page *page, unsigned long va)
-{
- unsigned long flags;
- struct atomic_mapped_page *amp;
- int cpu = smp_processor_id();
- spin_lock_irqsave(&amp_lock, flags);
- list_for_each_entry(amp, &amp_list, list) {
- if (amp->page == page && amp->cpu == cpu && amp->va == va)
- break;
- }
- BUG_ON(&amp->list == &amp_list);
- list_del(&amp->list);
- spin_unlock_irqrestore(&amp_lock, flags);
-}
-
-/* Helper routine for kmap_atomic_fix_kpte(), below. */
-static void kmap_atomic_fix_one_kpte(struct atomic_mapped_page *amp,
- int finished)
-{
- pte_t *ptep = kmap_get_pte(amp->va);
- if (!finished) {
- set_pte(ptep, pte_mkmigrate(*ptep));
- flush_remote(0, 0, NULL, amp->va, PAGE_SIZE, PAGE_SIZE,
- cpumask_of(amp->cpu), NULL, 0);
- } else {
- /*
- * Rewrite a default kernel PTE for this page.
- * We rely on the fact that set_pte() writes the
- * present+migrating bits last.
- */
- pte_t pte = mk_pte(amp->page, page_to_kpgprot(amp->page));
- set_pte(ptep, pte);
- }
-}
-
-/*
- * This routine is a helper function for homecache_fix_kpte(); see
- * its comments for more information on the "finished" argument here.
- *
- * Note that we hold the lock while doing the remote flushes, which
- * will stall any unrelated cpus trying to do kmap_atomic operations.
- * We could just update the PTEs under the lock, and save away copies
- * of the structs (or just the va+cpu), then flush them after we
- * release the lock, but it seems easier just to do it all under the lock.
- */
-void kmap_atomic_fix_kpte(struct page *page, int finished)
-{
- struct atomic_mapped_page *amp;
- unsigned long flags;
- spin_lock_irqsave(&amp_lock, flags);
- list_for_each_entry(amp, &amp_list, list) {
- if (amp->page == page)
- kmap_atomic_fix_one_kpte(amp, finished);
- }
- spin_unlock_irqrestore(&amp_lock, flags);
-}
-
-/*
- * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap
- * because the kmap code must perform a global TLB invalidation when
- * the kmap pool wraps.
- *
- * Note that they may be slower than on x86 (etc.) because unlike on
- * those platforms, we do have to take a global lock to map and unmap
- * pages on Tile (see above).
- *
- * When holding an atomic kmap is is not legal to sleep, so atomic
- * kmaps are appropriate for short, tight code paths only.
- */
-void *kmap_atomic_prot(struct page *page, pgprot_t prot)
-{
- unsigned long vaddr;
- int idx, type;
- pte_t *pte;
-
- preempt_disable();
- pagefault_disable();
-
- /* Avoid icache flushes by disallowing atomic executable mappings. */
- BUG_ON(pte_exec(prot));
-
- if (!PageHighMem(page))
- return page_address(page);
-
- type = kmap_atomic_idx_push();
- idx = type + KM_TYPE_NR*smp_processor_id();
- vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
- pte = kmap_get_pte(vaddr);
- BUG_ON(!pte_none(*pte));
-
- /* Register that this page is mapped atomically on this cpu. */
- kmap_atomic_register(page, type, vaddr, pte, mk_pte(page, prot));
-
- return (void *)vaddr;
-}
-EXPORT_SYMBOL(kmap_atomic_prot);
-
-void *kmap_atomic(struct page *page)
-{
- /* PAGE_NONE is a magic value that tells us to check immutability. */
- return kmap_atomic_prot(page, PAGE_NONE);
-}
-EXPORT_SYMBOL(kmap_atomic);
-
-void __kunmap_atomic(void *kvaddr)
-{
- unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
-
- if (vaddr >= __fix_to_virt(FIX_KMAP_END) &&
- vaddr <= __fix_to_virt(FIX_KMAP_BEGIN)) {
- pte_t *pte = kmap_get_pte(vaddr);
- pte_t pteval = *pte;
- int idx, type;
-
- type = kmap_atomic_idx();
- idx = type + KM_TYPE_NR*smp_processor_id();
-
- /*
- * Force other mappings to Oops if they try to access this pte
- * without first remapping it. Keeping stale mappings around
- * is a bad idea.
- */
- BUG_ON(!pte_present(pteval) && !pte_migrating(pteval));
- kmap_atomic_unregister(pte_page(pteval), vaddr);
- kpte_clear_flush(pte, vaddr);
- kmap_atomic_idx_pop();
- } else {
- /* Must be a lowmem page */
- BUG_ON(vaddr < PAGE_OFFSET);
- BUG_ON(vaddr >= (unsigned long)high_memory);
- }
-
- pagefault_enable();
- preempt_enable();
-}
-EXPORT_SYMBOL(__kunmap_atomic);
-
-/*
- * This API is supposed to allow us to map memory without a "struct page".
- * Currently we don't support this, though this may change in the future.
- */
-void *kmap_atomic_pfn(unsigned long pfn)
-{
- return kmap_atomic(pfn_to_page(pfn));
-}
-void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot)
-{
- return kmap_atomic_prot(pfn_to_page(pfn), prot);
-}
diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c
deleted file mode 100644
index 4432f31e8479..000000000000
--- a/arch/tile/mm/homecache.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * This code maintains the "home" for each page in the system.
- */
-
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/bootmem.h>
-#include <linux/rmap.h>
-#include <linux/pagemap.h>
-#include <linux/mutex.h>
-#include <linux/interrupt.h>
-#include <linux/sysctl.h>
-#include <linux/pagevec.h>
-#include <linux/ptrace.h>
-#include <linux/timex.h>
-#include <linux/cache.h>
-#include <linux/smp.h>
-#include <linux/module.h>
-#include <linux/hugetlb.h>
-
-#include <asm/page.h>
-#include <asm/sections.h>
-#include <asm/tlbflush.h>
-#include <asm/pgalloc.h>
-#include <asm/homecache.h>
-
-#include <arch/sim.h>
-
-#include "migrate.h"
-
-
-/*
- * The noallocl2 option suppresses all use of the L2 cache to cache
- * locally from a remote home.
- */
-static int __ro_after_init noallocl2;
-static int __init set_noallocl2(char *str)
-{
- noallocl2 = 1;
- return 0;
-}
-early_param("noallocl2", set_noallocl2);
-
-
-/*
- * Update the irq_stat for cpus that we are going to interrupt
- * with TLB or cache flushes. Also handle removing dataplane cpus
- * from the TLB flush set, and setting dataplane_tlb_state instead.
- */
-static void hv_flush_update(const struct cpumask *cache_cpumask,
- struct cpumask *tlb_cpumask,
- unsigned long tlb_va, unsigned long tlb_length,
- HV_Remote_ASID *asids, int asidcount)
-{
- struct cpumask mask;
- int i, cpu;
-
- cpumask_clear(&mask);
- if (cache_cpumask)
- cpumask_or(&mask, &mask, cache_cpumask);
- if (tlb_cpumask && tlb_length) {
- cpumask_or(&mask, &mask, tlb_cpumask);
- }
-
- for (i = 0; i < asidcount; ++i)
- cpumask_set_cpu(asids[i].y * smp_width + asids[i].x, &mask);
-
- /*
- * Don't bother to update atomically; losing a count
- * here is not that critical.
- */
- for_each_cpu(cpu, &mask)
- ++per_cpu(irq_stat, cpu).irq_hv_flush_count;
-}
-
-/*
- * This wrapper function around hv_flush_remote() does several things:
- *
- * - Provides a return value error-checking panic path, since
- * there's never any good reason for hv_flush_remote() to fail.
- * - Accepts a 32-bit PFN rather than a 64-bit PA, which generally
- * is the type that Linux wants to pass around anyway.
- * - Canonicalizes that lengths of zero make cpumasks NULL.
- * - Handles deferring TLB flushes for dataplane tiles.
- * - Tracks remote interrupts in the per-cpu irq_cpustat_t.
- *
- * Note that we have to wait until the cache flush completes before
- * updating the per-cpu last_cache_flush word, since otherwise another
- * concurrent flush can race, conclude the flush has already
- * completed, and start to use the page while it's still dirty
- * remotely (running concurrently with the actual evict, presumably).
- */
-void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
- const struct cpumask *cache_cpumask_orig,
- HV_VirtAddr tlb_va, unsigned long tlb_length,
- unsigned long tlb_pgsize,
- const struct cpumask *tlb_cpumask_orig,
- HV_Remote_ASID *asids, int asidcount)
-{
- int rc;
- struct cpumask cache_cpumask_copy, tlb_cpumask_copy;
- struct cpumask *cache_cpumask, *tlb_cpumask;
- HV_PhysAddr cache_pa;
-
- mb(); /* provided just to simplify "magic hypervisor" mode */
-
- /*
- * Canonicalize and copy the cpumasks.
- */
- if (cache_cpumask_orig && cache_control) {
- cpumask_copy(&cache_cpumask_copy, cache_cpumask_orig);
- cache_cpumask = &cache_cpumask_copy;
- } else {
- cpumask_clear(&cache_cpumask_copy);
- cache_cpumask = NULL;
- }
- if (cache_cpumask == NULL)
- cache_control = 0;
- if (tlb_cpumask_orig && tlb_length) {
- cpumask_copy(&tlb_cpumask_copy, tlb_cpumask_orig);
- tlb_cpumask = &tlb_cpumask_copy;
- } else {
- cpumask_clear(&tlb_cpumask_copy);
- tlb_cpumask = NULL;
- }
-
- hv_flush_update(cache_cpumask, tlb_cpumask, tlb_va, tlb_length,
- asids, asidcount);
- cache_pa = (HV_PhysAddr)cache_pfn << PAGE_SHIFT;
- rc = hv_flush_remote(cache_pa, cache_control,
- cpumask_bits(cache_cpumask),
- tlb_va, tlb_length, tlb_pgsize,
- cpumask_bits(tlb_cpumask),
- asids, asidcount);
- if (rc == 0)
- return;
-
- pr_err("hv_flush_remote(%#llx, %#lx, %p [%*pb], %#lx, %#lx, %#lx, %p [%*pb], %p, %d) = %d\n",
- cache_pa, cache_control, cache_cpumask,
- cpumask_pr_args(&cache_cpumask_copy),
- (unsigned long)tlb_va, tlb_length, tlb_pgsize, tlb_cpumask,
- cpumask_pr_args(&tlb_cpumask_copy), asids, asidcount, rc);
- panic("Unsafe to continue.");
-}
-
-static void homecache_finv_page_va(void* va, int home)
-{
- int cpu = get_cpu();
- if (home == cpu) {
- finv_buffer_local(va, PAGE_SIZE);
- } else if (home == PAGE_HOME_HASH) {
- finv_buffer_remote(va, PAGE_SIZE, 1);
- } else {
- BUG_ON(home < 0 || home >= NR_CPUS);
- finv_buffer_remote(va, PAGE_SIZE, 0);
- }
- put_cpu();
-}
-
-void homecache_finv_map_page(struct page *page, int home)
-{
- unsigned long flags;
- unsigned long va;
- pte_t *ptep;
- pte_t pte;
-
- if (home == PAGE_HOME_UNCACHED)
- return;
- local_irq_save(flags);
-#ifdef CONFIG_HIGHMEM
- va = __fix_to_virt(FIX_KMAP_BEGIN + kmap_atomic_idx_push() +
- (KM_TYPE_NR * smp_processor_id()));
-#else
- va = __fix_to_virt(FIX_HOMECACHE_BEGIN + smp_processor_id());
-#endif
- ptep = virt_to_kpte(va);
- pte = pfn_pte(page_to_pfn(page), PAGE_KERNEL);
- __set_pte(ptep, pte_set_home(pte, home));
- homecache_finv_page_va((void *)va, home);
- __pte_clear(ptep);
- hv_flush_page(va, PAGE_SIZE);
-#ifdef CONFIG_HIGHMEM
- kmap_atomic_idx_pop();
-#endif
- local_irq_restore(flags);
-}
-
-static void homecache_finv_page_home(struct page *page, int home)
-{
- if (!PageHighMem(page) && home == page_home(page))
- homecache_finv_page_va(page_address(page), home);
- else
- homecache_finv_map_page(page, home);
-}
-
-static inline bool incoherent_home(int home)
-{
- return home == PAGE_HOME_IMMUTABLE || home == PAGE_HOME_INCOHERENT;
-}
-
-static void homecache_finv_page_internal(struct page *page, int force_map)
-{
- int home = page_home(page);
- if (home == PAGE_HOME_UNCACHED)
- return;
- if (incoherent_home(home)) {
- int cpu;
- for_each_cpu(cpu, &cpu_cacheable_map)
- homecache_finv_map_page(page, cpu);
- } else if (force_map) {
- /* Force if, e.g., the normal mapping is migrating. */
- homecache_finv_map_page(page, home);
- } else {
- homecache_finv_page_home(page, home);
- }
- sim_validate_lines_evicted(PFN_PHYS(page_to_pfn(page)), PAGE_SIZE);
-}
-
-void homecache_finv_page(struct page *page)
-{
- homecache_finv_page_internal(page, 0);
-}
-
-void homecache_evict(const struct cpumask *mask)
-{
- flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
-}
-
-/* Report the home corresponding to a given PTE. */
-static int pte_to_home(pte_t pte)
-{
- if (hv_pte_get_nc(pte))
- return PAGE_HOME_IMMUTABLE;
- switch (hv_pte_get_mode(pte)) {
- case HV_PTE_MODE_CACHE_TILE_L3:
- return get_remote_cache_cpu(pte);
- case HV_PTE_MODE_CACHE_NO_L3:
- return PAGE_HOME_INCOHERENT;
- case HV_PTE_MODE_UNCACHED:
- return PAGE_HOME_UNCACHED;
- case HV_PTE_MODE_CACHE_HASH_L3:
- return PAGE_HOME_HASH;
- }
- panic("Bad PTE %#llx\n", pte.val);
-}
-
-/* Update the home of a PTE if necessary (can also be used for a pgprot_t). */
-pte_t pte_set_home(pte_t pte, int home)
-{
-#if CHIP_HAS_MMIO()
- /* Check for MMIO mappings and pass them through. */
- if (hv_pte_get_mode(pte) == HV_PTE_MODE_MMIO)
- return pte;
-#endif
-
-
- /*
- * Only immutable pages get NC mappings. If we have a
- * non-coherent PTE, but the underlying page is not
- * immutable, it's likely the result of a forced
- * caching setting running up against ptrace setting
- * the page to be writable underneath. In this case,
- * just keep the PTE coherent.
- */
- if (hv_pte_get_nc(pte) && home != PAGE_HOME_IMMUTABLE) {
- pte = hv_pte_clear_nc(pte);
- pr_err("non-immutable page incoherently referenced: %#llx\n",
- pte.val);
- }
-
- switch (home) {
-
- case PAGE_HOME_UNCACHED:
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
- break;
-
- case PAGE_HOME_INCOHERENT:
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
- break;
-
- case PAGE_HOME_IMMUTABLE:
- /*
- * We could home this page anywhere, since it's immutable,
- * but by default just home it to follow "hash_default".
- */
- BUG_ON(hv_pte_get_writable(pte));
- if (pte_get_forcecache(pte)) {
- /* Upgrade "force any cpu" to "No L3" for immutable. */
- if (hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_TILE_L3
- && pte_get_anyhome(pte)) {
- pte = hv_pte_set_mode(pte,
- HV_PTE_MODE_CACHE_NO_L3);
- }
- } else
- if (hash_default)
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
- else
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_NO_L3);
- pte = hv_pte_set_nc(pte);
- break;
-
- case PAGE_HOME_HASH:
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_HASH_L3);
- break;
-
- default:
- BUG_ON(home < 0 || home >= NR_CPUS ||
- !cpu_is_valid_lotar(home));
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_CACHE_TILE_L3);
- pte = set_remote_cache_cpu(pte, home);
- break;
- }
-
- if (noallocl2)
- pte = hv_pte_set_no_alloc_l2(pte);
-
- /* Simplify "no local and no l3" to "uncached" */
- if (hv_pte_get_no_alloc_l2(pte) && hv_pte_get_no_alloc_l1(pte) &&
- hv_pte_get_mode(pte) == HV_PTE_MODE_CACHE_NO_L3) {
- pte = hv_pte_set_mode(pte, HV_PTE_MODE_UNCACHED);
- }
-
- /* Checking this case here gives a better panic than from the hv. */
- BUG_ON(hv_pte_get_mode(pte) == 0);
-
- return pte;
-}
-EXPORT_SYMBOL(pte_set_home);
-
-/*
- * The routines in this section are the "static" versions of the normal
- * dynamic homecaching routines; they just set the home cache
- * of a kernel page once, and require a full-chip cache/TLB flush,
- * so they're not suitable for anything but infrequent use.
- */
-
-int page_home(struct page *page)
-{
- if (PageHighMem(page)) {
- return PAGE_HOME_HASH;
- } else {
- unsigned long kva = (unsigned long)page_address(page);
- return pte_to_home(*virt_to_kpte(kva));
- }
-}
-EXPORT_SYMBOL(page_home);
-
-void homecache_change_page_home(struct page *page, int order, int home)
-{
- int i, pages = (1 << order);
- unsigned long kva;
-
- BUG_ON(PageHighMem(page));
- BUG_ON(page_count(page) > 1);
- BUG_ON(page_mapcount(page) != 0);
- kva = (unsigned long) page_address(page);
- flush_remote(0, HV_FLUSH_EVICT_L2, &cpu_cacheable_map,
- kva, pages * PAGE_SIZE, PAGE_SIZE, cpu_online_mask,
- NULL, 0);
-
- for (i = 0; i < pages; ++i, kva += PAGE_SIZE) {
- pte_t *ptep = virt_to_kpte(kva);
- pte_t pteval = *ptep;
- BUG_ON(!pte_present(pteval) || pte_huge(pteval));
- __set_pte(ptep, pte_set_home(pteval, home));
- }
-}
-EXPORT_SYMBOL(homecache_change_page_home);
-
-struct page *homecache_alloc_pages(gfp_t gfp_mask,
- unsigned int order, int home)
-{
- struct page *page;
- BUG_ON(gfp_mask & __GFP_HIGHMEM); /* must be lowmem */
- page = alloc_pages(gfp_mask, order);
- if (page)
- homecache_change_page_home(page, order, home);
- return page;
-}
-EXPORT_SYMBOL(homecache_alloc_pages);
-
-struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
- unsigned int order, int home)
-{
- struct page *page;
- BUG_ON(gfp_mask & __GFP_HIGHMEM); /* must be lowmem */
- page = alloc_pages_node(nid, gfp_mask, order);
- if (page)
- homecache_change_page_home(page, order, home);
- return page;
-}
-
-void __homecache_free_pages(struct page *page, unsigned int order)
-{
- if (put_page_testzero(page)) {
- homecache_change_page_home(page, order, PAGE_HOME_HASH);
- if (order == 0) {
- free_unref_page(page);
- } else {
- init_page_count(page);
- __free_pages(page, order);
- }
- }
-}
-EXPORT_SYMBOL(__homecache_free_pages);
-
-void homecache_free_pages(unsigned long addr, unsigned int order)
-{
- if (addr != 0) {
- VM_BUG_ON(!virt_addr_valid((void *)addr));
- __homecache_free_pages(virt_to_page((void *)addr), order);
- }
-}
-EXPORT_SYMBOL(homecache_free_pages);
diff --git a/arch/tile/mm/hugetlbpage.c b/arch/tile/mm/hugetlbpage.c
deleted file mode 100644
index 0986d426a413..000000000000
--- a/arch/tile/mm/hugetlbpage.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * TILE Huge TLB Page Support for Kernel.
- * Taken from i386 hugetlb implementation:
- * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
- */
-
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/mm.h>
-#include <linux/sched/mm.h>
-#include <linux/hugetlb.h>
-#include <linux/pagemap.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/sysctl.h>
-#include <linux/mman.h>
-#include <asm/tlb.h>
-#include <asm/tlbflush.h>
-#include <asm/setup.h>
-
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
-
-/*
- * Provide an additional huge page size (in addition to the regular default
- * huge page size) if no "hugepagesz" arguments are specified.
- * Note that it must be smaller than the default huge page size so
- * that it's possible to allocate them on demand from the buddy allocator.
- * You can change this to 64K (on a 16K build), 256K, 1M, or 4M,
- * or not define it at all.
- */
-#define ADDITIONAL_HUGE_SIZE (1024 * 1024UL)
-
-/* "Extra" page-size multipliers, one per level of the page table. */
-int huge_shift[HUGE_SHIFT_ENTRIES] = {
-#ifdef ADDITIONAL_HUGE_SIZE
-#define ADDITIONAL_HUGE_SHIFT __builtin_ctzl(ADDITIONAL_HUGE_SIZE / PAGE_SIZE)
- [HUGE_SHIFT_PAGE] = ADDITIONAL_HUGE_SHIFT
-#endif
-};
-
-#endif
-
-pte_t *huge_pte_alloc(struct mm_struct *mm,
- unsigned long addr, unsigned long sz)
-{
- pgd_t *pgd;
- pud_t *pud;
-
- addr &= -sz; /* Mask off any low bits in the address. */
-
- pgd = pgd_offset(mm, addr);
- pud = pud_alloc(mm, pgd, addr);
-
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
- if (sz >= PGDIR_SIZE) {
- BUG_ON(sz != PGDIR_SIZE &&
- sz != PGDIR_SIZE << huge_shift[HUGE_SHIFT_PGDIR]);
- return (pte_t *)pud;
- } else {
- pmd_t *pmd = pmd_alloc(mm, pud, addr);
- if (sz >= PMD_SIZE) {
- BUG_ON(sz != PMD_SIZE &&
- sz != (PMD_SIZE << huge_shift[HUGE_SHIFT_PMD]));
- return (pte_t *)pmd;
- }
- else {
- if (sz != PAGE_SIZE << huge_shift[HUGE_SHIFT_PAGE])
- panic("Unexpected page size %#lx\n", sz);
- return pte_alloc_map(mm, pmd, addr);
- }
- }
-#else
- BUG_ON(sz != PMD_SIZE);
- return (pte_t *) pmd_alloc(mm, pud, addr);
-#endif
-}
-
-static pte_t *get_pte(pte_t *base, int index, int level)
-{
- pte_t *ptep = base + index;
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
- if (!pte_present(*ptep) && huge_shift[level] != 0) {
- unsigned long mask = -1UL << huge_shift[level];
- pte_t *super_ptep = base + (index & mask);
- pte_t pte = *super_ptep;
- if (pte_present(pte) && pte_super(pte))
- ptep = super_ptep;
- }
-#endif
- return ptep;
-}
-
-pte_t *huge_pte_offset(struct mm_struct *mm,
- unsigned long addr, unsigned long sz)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
- pte_t *pte;
-#endif
-
- /* Get the top-level page table entry. */
- pgd = (pgd_t *)get_pte((pte_t *)mm->pgd, pgd_index(addr), 0);
-
- /* We don't have four levels. */
- pud = pud_offset(pgd, addr);
-#ifndef __PAGETABLE_PUD_FOLDED
-# error support fourth page table level
-#endif
- if (!pud_present(*pud))
- return NULL;
-
- /* Check for an L0 huge PTE, if we have three levels. */
-#ifndef __PAGETABLE_PMD_FOLDED
- if (pud_huge(*pud))
- return (pte_t *)pud;
-
- pmd = (pmd_t *)get_pte((pte_t *)pud_page_vaddr(*pud),
- pmd_index(addr), 1);
- if (!pmd_present(*pmd))
- return NULL;
-#else
- pmd = pmd_offset(pud, addr);
-#endif
-
- /* Check for an L1 huge PTE. */
- if (pmd_huge(*pmd))
- return (pte_t *)pmd;
-
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
- /* Check for an L2 huge PTE. */
- pte = get_pte((pte_t *)pmd_page_vaddr(*pmd), pte_index(addr), 2);
- if (!pte_present(*pte))
- return NULL;
- if (pte_super(*pte))
- return pte;
-#endif
-
- return NULL;
-}
-
-int pmd_huge(pmd_t pmd)
-{
- return !!(pmd_val(pmd) & _PAGE_HUGE_PAGE);
-}
-
-int pud_huge(pud_t pud)
-{
- return !!(pud_val(pud) & _PAGE_HUGE_PAGE);
-}
-
-#ifdef HAVE_ARCH_HUGETLB_UNMAPPED_AREA
-static unsigned long hugetlb_get_unmapped_area_bottomup(struct file *file,
- unsigned long addr, unsigned long len,
- unsigned long pgoff, unsigned long flags)
-{
- struct hstate *h = hstate_file(file);
- struct vm_unmapped_area_info info;
-
- info.flags = 0;
- info.length = len;
- info.low_limit = TASK_UNMAPPED_BASE;
- info.high_limit = TASK_SIZE;
- info.align_mask = PAGE_MASK & ~huge_page_mask(h);
- info.align_offset = 0;
- return vm_unmapped_area(&info);
-}
-
-static unsigned long hugetlb_get_unmapped_area_topdown(struct file *file,
- unsigned long addr0, unsigned long len,
- unsigned long pgoff, unsigned long flags)
-{
- struct hstate *h = hstate_file(file);
- struct vm_unmapped_area_info info;
- unsigned long addr;
-
- info.flags = VM_UNMAPPED_AREA_TOPDOWN;
- info.length = len;
- info.low_limit = PAGE_SIZE;
- info.high_limit = current->mm->mmap_base;
- info.align_mask = PAGE_MASK & ~huge_page_mask(h);
- info.align_offset = 0;
- addr = vm_unmapped_area(&info);
-
- /*
- * A failed mmap() very likely causes application failure,
- * so fall back to the bottom-up function here. This scenario
- * can happen with large stack limits and large mmap()
- * allocations.
- */
- if (addr & ~PAGE_MASK) {
- VM_BUG_ON(addr != -ENOMEM);
- info.flags = 0;
- info.low_limit = TASK_UNMAPPED_BASE;
- info.high_limit = TASK_SIZE;
- addr = vm_unmapped_area(&info);
- }
-
- return addr;
-}
-
-unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
- unsigned long len, unsigned long pgoff, unsigned long flags)
-{
- struct hstate *h = hstate_file(file);
- struct mm_struct *mm = current->mm;
- struct vm_area_struct *vma;
-
- if (len & ~huge_page_mask(h))
- return -EINVAL;
- if (len > TASK_SIZE)
- return -ENOMEM;
-
- if (flags & MAP_FIXED) {
- if (prepare_hugepage_range(file, addr, len))
- return -EINVAL;
- return addr;
- }
-
- if (addr) {
- addr = ALIGN(addr, huge_page_size(h));
- vma = find_vma(mm, addr);
- if (TASK_SIZE - len >= addr &&
- (!vma || addr + len <= vm_start_gap(vma)))
- return addr;
- }
- if (current->mm->get_unmapped_area == arch_get_unmapped_area)
- return hugetlb_get_unmapped_area_bottomup(file, addr, len,
- pgoff, flags);
- else
- return hugetlb_get_unmapped_area_topdown(file, addr, len,
- pgoff, flags);
-}
-#endif /* HAVE_ARCH_HUGETLB_UNMAPPED_AREA */
-
-#ifdef CONFIG_HUGETLB_SUPER_PAGES
-static __init int __setup_hugepagesz(unsigned long ps)
-{
- int log_ps = __builtin_ctzl(ps);
- int level, base_shift;
-
- if ((1UL << log_ps) != ps || (log_ps & 1) != 0) {
- pr_warn("Not enabling %ld byte huge pages; must be a power of four\n",
- ps);
- return -EINVAL;
- }
-
- if (ps > 64*1024*1024*1024UL) {
- pr_warn("Not enabling %ld MB huge pages; largest legal value is 64 GB\n",
- ps >> 20);
- return -EINVAL;
- } else if (ps >= PUD_SIZE) {
- static long hv_jpage_size;
- if (hv_jpage_size == 0)
- hv_jpage_size = hv_sysconf(HV_SYSCONF_PAGE_SIZE_JUMBO);
- if (hv_jpage_size != PUD_SIZE) {
- pr_warn("Not enabling >= %ld MB huge pages: hypervisor reports size %ld\n",
- PUD_SIZE >> 20, hv_jpage_size);
- return -EINVAL;
- }
- level = 0;
- base_shift = PUD_SHIFT;
- } else if (ps >= PMD_SIZE) {
- level = 1;
- base_shift = PMD_SHIFT;
- } else if (ps > PAGE_SIZE) {
- level = 2;
- base_shift = PAGE_SHIFT;
- } else {
- pr_err("hugepagesz: huge page size %ld too small\n", ps);
- return -EINVAL;
- }
-
- if (log_ps != base_shift) {
- int shift_val = log_ps - base_shift;
- if (huge_shift[level] != 0) {
- int old_shift = base_shift + huge_shift[level];
- pr_warn("Not enabling %ld MB huge pages; already have size %ld MB\n",
- ps >> 20, (1UL << old_shift) >> 20);
- return -EINVAL;
- }
- if (hv_set_pte_super_shift(level, shift_val) != 0) {
- pr_warn("Not enabling %ld MB huge pages; no hypervisor support\n",
- ps >> 20);
- return -EINVAL;
- }
- printk(KERN_DEBUG "Enabled %ld MB huge pages\n", ps >> 20);
- huge_shift[level] = shift_val;
- }
-
- hugetlb_add_hstate(log_ps - PAGE_SHIFT);
-
- return 0;
-}
-
-static bool saw_hugepagesz;
-
-static __init int setup_hugepagesz(char *opt)
-{
- int rc;
-
- if (!saw_hugepagesz) {
- saw_hugepagesz = true;
- memset(huge_shift, 0, sizeof(huge_shift));
- }
- rc = __setup_hugepagesz(memparse(opt, NULL));
- if (rc)
- hugetlb_bad_size();
- return rc;
-}
-__setup("hugepagesz=", setup_hugepagesz);
-
-#ifdef ADDITIONAL_HUGE_SIZE
-/*
- * Provide an additional huge page size if no "hugepagesz" args are given.
- * In that case, all the cores have properly set up their hv super_shift
- * already, but we need to notify the hugetlb code to enable the
- * new huge page size from the Linux point of view.
- */
-static __init int add_default_hugepagesz(void)
-{
- if (!saw_hugepagesz) {
- BUILD_BUG_ON(ADDITIONAL_HUGE_SIZE >= PMD_SIZE ||
- ADDITIONAL_HUGE_SIZE <= PAGE_SIZE);
- BUILD_BUG_ON((PAGE_SIZE << ADDITIONAL_HUGE_SHIFT) !=
- ADDITIONAL_HUGE_SIZE);
- BUILD_BUG_ON(ADDITIONAL_HUGE_SHIFT & 1);
- hugetlb_add_hstate(ADDITIONAL_HUGE_SHIFT);
- }
- return 0;
-}
-arch_initcall(add_default_hugepagesz);
-#endif
-
-#endif /* CONFIG_HUGETLB_SUPER_PAGES */
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
deleted file mode 100644
index 5f757e04bcd2..000000000000
--- a/arch/tile/mm/init.c
+++ /dev/null
@@ -1,956 +0,0 @@
-/*
- * Copyright (C) 1995 Linus Torvalds
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/hugetlb.h>
-#include <linux/swap.h>
-#include <linux/smp.h>
-#include <linux/init.h>
-#include <linux/highmem.h>
-#include <linux/pagemap.h>
-#include <linux/poison.h>
-#include <linux/bootmem.h>
-#include <linux/slab.h>
-#include <linux/proc_fs.h>
-#include <linux/efi.h>
-#include <linux/memory_hotplug.h>
-#include <linux/uaccess.h>
-#include <asm/mmu_context.h>
-#include <asm/processor.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/dma.h>
-#include <asm/fixmap.h>
-#include <asm/tlb.h>
-#include <asm/tlbflush.h>
-#include <asm/sections.h>
-#include <asm/setup.h>
-#include <asm/homecache.h>
-#include <hv/hypervisor.h>
-#include <arch/chip.h>
-
-#include "migrate.h"
-
-#define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
-
-#ifndef __tilegx__
-unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE;
-EXPORT_SYMBOL(VMALLOC_RESERVE);
-#endif
-
-/* Create an L2 page table */
-static pte_t * __init alloc_pte(void)
-{
- return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0);
-}
-
-/*
- * L2 page tables per controller. We allocate these all at once from
- * the bootmem allocator and store them here. This saves on kernel L2
- * page table memory, compared to allocating a full 64K page per L2
- * page table, and also means that in cases where we use huge pages,
- * we are guaranteed to later be able to shatter those huge pages and
- * switch to using these page tables instead, without requiring
- * further allocation. Each l2_ptes[] entry points to the first page
- * table for the first hugepage-size piece of memory on the
- * controller; other page tables are just indexed directly, i.e. the
- * L2 page tables are contiguous in memory for each controller.
- */
-static pte_t *l2_ptes[MAX_NUMNODES];
-static int num_l2_ptes[MAX_NUMNODES];
-
-static void init_prealloc_ptes(int node, int pages)
-{
- BUG_ON(pages & (PTRS_PER_PTE - 1));
- if (pages) {
- num_l2_ptes[node] = pages;
- l2_ptes[node] = __alloc_bootmem(pages * sizeof(pte_t),
- HV_PAGE_TABLE_ALIGN, 0);
- }
-}
-
-pte_t *get_prealloc_pte(unsigned long pfn)
-{
- int node = pfn_to_nid(pfn);
- pfn &= ~(-1UL << (NR_PA_HIGHBIT_SHIFT - PAGE_SHIFT));
- BUG_ON(node >= MAX_NUMNODES);
- BUG_ON(pfn >= num_l2_ptes[node]);
- return &l2_ptes[node][pfn];
-}
-
-/*
- * What caching do we expect pages from the heap to have when
- * they are allocated during bootup? (Once we've installed the
- * "real" swapper_pg_dir.)
- */
-static int initial_heap_home(void)
-{
- if (hash_default)
- return PAGE_HOME_HASH;
- return smp_processor_id();
-}
-
-/*
- * Place a pointer to an L2 page table in a middle page
- * directory entry.
- */
-static void __init assign_pte(pmd_t *pmd, pte_t *page_table)
-{
- phys_addr_t pa = __pa(page_table);
- unsigned long l2_ptfn = pa >> HV_LOG2_PAGE_TABLE_ALIGN;
- pte_t pteval = hv_pte_set_ptfn(__pgprot(_PAGE_TABLE), l2_ptfn);
- BUG_ON((pa & (HV_PAGE_TABLE_ALIGN-1)) != 0);
- pteval = pte_set_home(pteval, initial_heap_home());
- *(pte_t *)pmd = pteval;
- if (page_table != (pte_t *)pmd_page_vaddr(*pmd))
- BUG();
-}
-
-#ifdef __tilegx__
-
-static inline pmd_t *alloc_pmd(void)
-{
- return __alloc_bootmem(L1_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0);
-}
-
-static inline void assign_pmd(pud_t *pud, pmd_t *pmd)
-{
- assign_pte((pmd_t *)pud, (pte_t *)pmd);
-}
-
-#endif /* __tilegx__ */
-
-/* Replace the given pmd with a full PTE table. */
-void __init shatter_pmd(pmd_t *pmd)
-{
- pte_t *pte = get_prealloc_pte(pte_pfn(*(pte_t *)pmd));
- assign_pte(pmd, pte);
-}
-
-#ifdef __tilegx__
-static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
-{
- pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
- if (pud_none(*pud))
- assign_pmd(pud, alloc_pmd());
- return pmd_offset(pud, va);
-}
-#else
-static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
-{
- return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
-}
-#endif
-
-/*
- * This function initializes a certain range of kernel virtual memory
- * with new bootmem page tables, everywhere page tables are missing in
- * the given range.
- */
-
-/*
- * NOTE: The pagetables are allocated contiguous on the physical space
- * so we can cache the place of the first one and move around without
- * checking the pgd every time.
- */
-static void __init page_table_range_init(unsigned long start,
- unsigned long end, pgd_t *pgd)
-{
- unsigned long vaddr;
- start = round_down(start, PMD_SIZE);
- end = round_up(end, PMD_SIZE);
- for (vaddr = start; vaddr < end; vaddr += PMD_SIZE) {
- pmd_t *pmd = get_pmd(pgd, vaddr);
- if (pmd_none(*pmd))
- assign_pte(pmd, alloc_pte());
- }
-}
-
-
-static int __initdata ktext_hash = 1; /* .text pages */
-static int __initdata kdata_hash = 1; /* .data and .bss pages */
-int __ro_after_init hash_default = 1; /* kernel allocator pages */
-EXPORT_SYMBOL(hash_default);
-int __ro_after_init kstack_hash = 1; /* if no homecaching, use h4h */
-
-/*
- * CPUs to use to for striping the pages of kernel data. If hash-for-home
- * is available, this is only relevant if kcache_hash sets up the
- * .data and .bss to be page-homed, and we don't want the default mode
- * of using the full set of kernel cpus for the striping.
- */
-static __initdata struct cpumask kdata_mask;
-static __initdata int kdata_arg_seen;
-
-int __ro_after_init kdata_huge; /* if no homecaching, small pages */
-
-
-/* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */
-static pgprot_t __init construct_pgprot(pgprot_t prot, int home)
-{
- prot = pte_set_home(prot, home);
- if (home == PAGE_HOME_IMMUTABLE) {
- if (ktext_hash)
- prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_HASH_L3);
- else
- prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_NO_L3);
- }
- return prot;
-}
-
-/*
- * For a given kernel data VA, how should it be cached?
- * We return the complete pgprot_t with caching bits set.
- */
-static pgprot_t __init init_pgprot(ulong address)
-{
- int cpu;
- unsigned long page;
- enum { CODE_DELTA = MEM_SV_START - PAGE_OFFSET };
-
- /* For kdata=huge, everything is just hash-for-home. */
- if (kdata_huge)
- return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
-
- /*
- * We map the aliased pages of permanent text so we can
- * update them if necessary, for ftrace, etc.
- */
- if (address < (ulong) _sinittext - CODE_DELTA)
- return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
-
- /* We map read-only data non-coherent for performance. */
- if ((address >= (ulong) __start_rodata &&
- address < (ulong) __end_rodata) ||
- address == (ulong) empty_zero_page) {
- return construct_pgprot(PAGE_KERNEL_RO, PAGE_HOME_IMMUTABLE);
- }
-
-#ifndef __tilegx__
- /* Force the atomic_locks[] array page to be hash-for-home. */
- if (address == (ulong) atomic_locks)
- return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
-#endif
-
- /*
- * Everything else that isn't data or bss is heap, so mark it
- * with the initial heap home (hash-for-home, or this cpu). This
- * includes any addresses after the loaded image and any address before
- * __init_end, since we already captured the case of text before
- * _sinittext, and __pa(einittext) is approximately __pa(__init_begin).
- *
- * All the LOWMEM pages that we mark this way will get their
- * struct page homecache properly marked later, in set_page_homes().
- * The HIGHMEM pages we leave with a default zero for their
- * homes, but with a zero free_time we don't have to actually
- * do a flush action the first time we use them, either.
- */
- if (address >= (ulong) _end || address < (ulong) __init_end)
- return construct_pgprot(PAGE_KERNEL, initial_heap_home());
-
- /* Use hash-for-home if requested for data/bss. */
- if (kdata_hash)
- return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
-
- /*
- * Otherwise we just hand out consecutive cpus. To avoid
- * requiring this function to hold state, we just walk forward from
- * __end_rodata by PAGE_SIZE, skipping the readonly and init data, to
- * reach the requested address, while walking cpu home around
- * kdata_mask. This is typically no more than a dozen or so iterations.
- */
- page = (((ulong)__end_rodata) + PAGE_SIZE - 1) & PAGE_MASK;
- BUG_ON(address < page || address >= (ulong)_end);
- cpu = cpumask_first(&kdata_mask);
- for (; page < address; page += PAGE_SIZE) {
- if (page >= (ulong)&init_thread_union &&
- page < (ulong)&init_thread_union + THREAD_SIZE)
- continue;
- if (page == (ulong)empty_zero_page)
- continue;
-#ifndef __tilegx__
- if (page == (ulong)atomic_locks)
- continue;
-#endif
- cpu = cpumask_next(cpu, &kdata_mask);
- if (cpu == NR_CPUS)
- cpu = cpumask_first(&kdata_mask);
- }
- return construct_pgprot(PAGE_KERNEL, cpu);
-}
-
-/*
- * This function sets up how we cache the kernel text. If we have
- * hash-for-home support, normally that is used instead (see the
- * kcache_hash boot flag for more information). But if we end up
- * using a page-based caching technique, this option sets up the
- * details of that. In addition, the "ktext=nocache" option may
- * always be used to disable local caching of text pages, if desired.
- */
-
-static int __initdata ktext_arg_seen;
-static int __initdata ktext_small;
-static int __initdata ktext_local;
-static int __initdata ktext_all;
-static int __initdata ktext_nondataplane;
-static int __initdata ktext_nocache;
-static struct cpumask __initdata ktext_mask;
-
-static int __init setup_ktext(char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- /* If you have a leading "nocache", turn off ktext caching */
- if (strncmp(str, "nocache", 7) == 0) {
- ktext_nocache = 1;
- pr_info("ktext: disabling local caching of kernel text\n");
- str += 7;
- if (*str == ',')
- ++str;
- if (*str == '\0')
- return 0;
- }
-
- ktext_arg_seen = 1;
-
- /* Default setting: use a huge page */
- if (strcmp(str, "huge") == 0)
- pr_info("ktext: using one huge locally cached page\n");
-
- /* Pay TLB cost but get no cache benefit: cache small pages locally */
- else if (strcmp(str, "local") == 0) {
- ktext_small = 1;
- ktext_local = 1;
- pr_info("ktext: using small pages with local caching\n");
- }
-
- /* Neighborhood cache ktext pages on all cpus. */
- else if (strcmp(str, "all") == 0) {
- ktext_small = 1;
- ktext_all = 1;
- pr_info("ktext: using maximal caching neighborhood\n");
- }
-
-
- /* Neighborhood ktext pages on specified mask */
- else if (cpulist_parse(str, &ktext_mask) == 0) {
- if (cpumask_weight(&ktext_mask) > 1) {
- ktext_small = 1;
- pr_info("ktext: using caching neighborhood %*pbl with small pages\n",
- cpumask_pr_args(&ktext_mask));
- } else {
- pr_info("ktext: caching on cpu %*pbl with one huge page\n",
- cpumask_pr_args(&ktext_mask));
- }
- }
-
- else if (*str)
- return -EINVAL;
-
- return 0;
-}
-
-early_param("ktext", setup_ktext);
-
-
-static inline pgprot_t ktext_set_nocache(pgprot_t prot)
-{
- if (!ktext_nocache)
- prot = hv_pte_set_nc(prot);
- else
- prot = hv_pte_set_no_alloc_l2(prot);
- return prot;
-}
-
-/* Temporary page table we use for staging. */
-static pgd_t pgtables[PTRS_PER_PGD]
- __attribute__((aligned(HV_PAGE_TABLE_ALIGN)));
-
-/*
- * This maps the physical memory to kernel virtual address space, a total
- * of max_low_pfn pages, by creating page tables starting from address
- * PAGE_OFFSET.
- *
- * This routine transitions us from using a set of compiled-in large
- * pages to using some more precise caching, including removing access
- * to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START)
- * marking read-only data as locally cacheable, striping the remaining
- * .data and .bss across all the available tiles, and removing access
- * to pages above the top of RAM (thus ensuring a page fault from a bad
- * virtual address rather than a hypervisor shoot down for accessing
- * memory outside the assigned limits).
- */
-static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
-{
- unsigned long long irqmask;
- unsigned long address, pfn;
- pmd_t *pmd;
- pte_t *pte;
- int pte_ofs;
- const struct cpumask *my_cpu_mask = cpumask_of(smp_processor_id());
- struct cpumask kstripe_mask;
- int rc, i;
-
- if (ktext_arg_seen && ktext_hash) {
- pr_warn("warning: \"ktext\" boot argument ignored if \"kcache_hash\" sets up text hash-for-home\n");
- ktext_small = 0;
- }
-
- if (kdata_arg_seen && kdata_hash) {
- pr_warn("warning: \"kdata\" boot argument ignored if \"kcache_hash\" sets up data hash-for-home\n");
- }
-
- if (kdata_huge && !hash_default) {
- pr_warn("warning: disabling \"kdata=huge\"; requires kcache_hash=all or =allbutstack\n");
- kdata_huge = 0;
- }
-
- /*
- * Set up a mask for cpus to use for kernel striping.
- * This is normally all cpus, but minus dataplane cpus if any.
- * If the dataplane covers the whole chip, we stripe over
- * the whole chip too.
- */
- cpumask_copy(&kstripe_mask, cpu_possible_mask);
- if (!kdata_arg_seen)
- kdata_mask = kstripe_mask;
-
- /* Allocate and fill in L2 page tables */
- for (i = 0; i < MAX_NUMNODES; ++i) {
-#ifdef CONFIG_HIGHMEM
- unsigned long end_pfn = node_lowmem_end_pfn[i];
-#else
- unsigned long end_pfn = node_end_pfn[i];
-#endif
- unsigned long end_huge_pfn = 0;
-
- /* Pre-shatter the last huge page to allow per-cpu pages. */
- if (kdata_huge)
- end_huge_pfn = end_pfn - (HPAGE_SIZE >> PAGE_SHIFT);
-
- pfn = node_start_pfn[i];
-
- /* Allocate enough memory to hold L2 page tables for node. */
- init_prealloc_ptes(i, end_pfn - pfn);
-
- address = (unsigned long) pfn_to_kaddr(pfn);
- while (pfn < end_pfn) {
- BUG_ON(address & (HPAGE_SIZE-1));
- pmd = get_pmd(pgtables, address);
- pte = get_prealloc_pte(pfn);
- if (pfn < end_huge_pfn) {
- pgprot_t prot = init_pgprot(address);
- *(pte_t *)pmd = pte_mkhuge(pfn_pte(pfn, prot));
- for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
- pfn++, pte_ofs++, address += PAGE_SIZE)
- pte[pte_ofs] = pfn_pte(pfn, prot);
- } else {
- if (kdata_huge)
- printk(KERN_DEBUG "pre-shattered huge page at %#lx\n",
- address);
- for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
- pfn++, pte_ofs++, address += PAGE_SIZE) {
- pgprot_t prot = init_pgprot(address);
- pte[pte_ofs] = pfn_pte(pfn, prot);
- }
- assign_pte(pmd, pte);
- }
- }
- }
-
- /*
- * Set or check ktext_map now that we have cpu_possible_mask
- * and kstripe_mask to work with.
- */
- if (ktext_all)
- cpumask_copy(&ktext_mask, cpu_possible_mask);
- else if (ktext_nondataplane)
- ktext_mask = kstripe_mask;
- else if (!cpumask_empty(&ktext_mask)) {
- /* Sanity-check any mask that was requested */
- struct cpumask bad;
- cpumask_andnot(&bad, &ktext_mask, cpu_possible_mask);
- cpumask_and(&ktext_mask, &ktext_mask, cpu_possible_mask);
- if (!cpumask_empty(&bad))
- pr_info("ktext: not using unavailable cpus %*pbl\n",
- cpumask_pr_args(&bad));
- if (cpumask_empty(&ktext_mask)) {
- pr_warn("ktext: no valid cpus; caching on %d\n",
- smp_processor_id());
- cpumask_copy(&ktext_mask,
- cpumask_of(smp_processor_id()));
- }
- }
-
- address = MEM_SV_START;
- pmd = get_pmd(pgtables, address);
- pfn = 0; /* code starts at PA 0 */
- if (ktext_small) {
- /* Allocate an L2 PTE for the kernel text */
- int cpu = 0;
- pgprot_t prot = construct_pgprot(PAGE_KERNEL_EXEC,
- PAGE_HOME_IMMUTABLE);
-
- if (ktext_local) {
- if (ktext_nocache)
- prot = hv_pte_set_mode(prot,
- HV_PTE_MODE_UNCACHED);
- else
- prot = hv_pte_set_mode(prot,
- HV_PTE_MODE_CACHE_NO_L3);
- } else {
- prot = hv_pte_set_mode(prot,
- HV_PTE_MODE_CACHE_TILE_L3);
- cpu = cpumask_first(&ktext_mask);
-
- prot = ktext_set_nocache(prot);
- }
-
- BUG_ON(address != (unsigned long)_text);
- pte = NULL;
- for (; address < (unsigned long)_einittext;
- pfn++, address += PAGE_SIZE) {
- pte_ofs = pte_index(address);
- if (pte_ofs == 0) {
- if (pte)
- assign_pte(pmd++, pte);
- pte = alloc_pte();
- }
- if (!ktext_local) {
- prot = set_remote_cache_cpu(prot, cpu);
- cpu = cpumask_next(cpu, &ktext_mask);
- if (cpu == NR_CPUS)
- cpu = cpumask_first(&ktext_mask);
- }
- pte[pte_ofs] = pfn_pte(pfn, prot);
- }
- if (pte)
- assign_pte(pmd, pte);
- } else {
- pte_t pteval = pfn_pte(0, PAGE_KERNEL_EXEC);
- pteval = pte_mkhuge(pteval);
- if (ktext_hash) {
- pteval = hv_pte_set_mode(pteval,
- HV_PTE_MODE_CACHE_HASH_L3);
- pteval = ktext_set_nocache(pteval);
- } else
- if (cpumask_weight(&ktext_mask) == 1) {
- pteval = set_remote_cache_cpu(pteval,
- cpumask_first(&ktext_mask));
- pteval = hv_pte_set_mode(pteval,
- HV_PTE_MODE_CACHE_TILE_L3);
- pteval = ktext_set_nocache(pteval);
- } else if (ktext_nocache)
- pteval = hv_pte_set_mode(pteval,
- HV_PTE_MODE_UNCACHED);
- else
- pteval = hv_pte_set_mode(pteval,
- HV_PTE_MODE_CACHE_NO_L3);
- for (; address < (unsigned long)_einittext;
- pfn += PFN_DOWN(HPAGE_SIZE), address += HPAGE_SIZE)
- *(pte_t *)(pmd++) = pfn_pte(pfn, pteval);
- }
-
- /* Set swapper_pgprot here so it is flushed to memory right away. */
- swapper_pgprot = init_pgprot((unsigned long)swapper_pg_dir);
-
- /*
- * Since we may be changing the caching of the stack and page
- * table itself, we invoke an assembly helper to do the
- * following steps:
- *
- * - flush the cache so we start with an empty slate
- * - install pgtables[] as the real page table
- * - flush the TLB so the new page table takes effect
- */
- irqmask = interrupt_mask_save_mask();
- interrupt_mask_set_mask(-1ULL);
- rc = flush_and_install_context(__pa(pgtables),
- init_pgprot((unsigned long)pgtables),
- __this_cpu_read(current_asid),
- cpumask_bits(my_cpu_mask));
- interrupt_mask_restore_mask(irqmask);
- BUG_ON(rc != 0);
-
- /* Copy the page table back to the normal swapper_pg_dir. */
- memcpy(pgd_base, pgtables, sizeof(pgtables));
- __install_page_table(pgd_base, __this_cpu_read(current_asid),
- swapper_pgprot);
-
- /*
- * We just read swapper_pgprot and thus brought it into the cache,
- * with its new home & caching mode. When we start the other CPUs,
- * they're going to reference swapper_pgprot via their initial fake
- * VA-is-PA mappings, which cache everything locally. At that
- * time, if it's in our cache with a conflicting home, the
- * simulator's coherence checker will complain. So, flush it out
- * of our cache; we're not going to ever use it again anyway.
- */
- __insn_finv(&swapper_pgprot);
-}
-
-/*
- * devmem_is_allowed() checks to see if /dev/mem access to a certain address
- * is valid. The argument is a physical page number.
- *
- * On Tile, the only valid things for which we can just hand out unchecked
- * PTEs are the kernel code and data. Anything else might change its
- * homing with time, and we wouldn't know to adjust the /dev/mem PTEs.
- * Note that init_thread_union is released to heap soon after boot,
- * so we include it in the init data.
- *
- * For TILE-Gx, we might want to consider allowing access to PA
- * regions corresponding to PCI space, etc.
- */
-int devmem_is_allowed(unsigned long pagenr)
-{
- return pagenr < kaddr_to_pfn(_end) &&
- !(pagenr >= kaddr_to_pfn(&init_thread_union) ||
- pagenr < kaddr_to_pfn(__init_end)) &&
- !(pagenr >= kaddr_to_pfn(_sinittext) ||
- pagenr <= kaddr_to_pfn(_einittext-1));
-}
-
-#ifdef CONFIG_HIGHMEM
-static void __init permanent_kmaps_init(pgd_t *pgd_base)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- unsigned long vaddr;
-
- vaddr = PKMAP_BASE;
- page_table_range_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
-
- pgd = swapper_pg_dir + pgd_index(vaddr);
- pud = pud_offset(pgd, vaddr);
- pmd = pmd_offset(pud, vaddr);
- pte = pte_offset_kernel(pmd, vaddr);
- pkmap_page_table = pte;
-}
-#endif /* CONFIG_HIGHMEM */
-
-
-#ifndef CONFIG_64BIT
-static void __init init_free_pfn_range(unsigned long start, unsigned long end)
-{
- unsigned long pfn;
- struct page *page = pfn_to_page(start);
-
- for (pfn = start; pfn < end; ) {
- /* Optimize by freeing pages in large batches */
- int order = __ffs(pfn);
- int count, i;
- struct page *p;
-
- if (order >= MAX_ORDER)
- order = MAX_ORDER-1;
- count = 1 << order;
- while (pfn + count > end) {
- count >>= 1;
- --order;
- }
- for (p = page, i = 0; i < count; ++i, ++p) {
- __ClearPageReserved(p);
- /*
- * Hacky direct set to avoid unnecessary
- * lock take/release for EVERY page here.
- */
- p->_refcount.counter = 0;
- p->_mapcount.counter = -1;
- }
- init_page_count(page);
- __free_pages(page, order);
- adjust_managed_page_count(page, count);
-
- page += count;
- pfn += count;
- }
-}
-
-static void __init set_non_bootmem_pages_init(void)
-{
- struct zone *z;
- for_each_zone(z) {
- unsigned long start, end;
- int nid = z->zone_pgdat->node_id;
-#ifdef CONFIG_HIGHMEM
- int idx = zone_idx(z);
-#endif
-
- start = z->zone_start_pfn;
- end = start + z->spanned_pages;
- start = max(start, node_free_pfn[nid]);
- start = max(start, max_low_pfn);
-
-#ifdef CONFIG_HIGHMEM
- if (idx == ZONE_HIGHMEM)
- totalhigh_pages += z->spanned_pages;
-#endif
- if (kdata_huge) {
- unsigned long percpu_pfn = node_percpu_pfn[nid];
- if (start < percpu_pfn && end > percpu_pfn)
- end = percpu_pfn;
- }
-#ifdef CONFIG_PCI
- if (start <= pci_reserve_start_pfn &&
- end > pci_reserve_start_pfn) {
- if (end > pci_reserve_end_pfn)
- init_free_pfn_range(pci_reserve_end_pfn, end);
- end = pci_reserve_start_pfn;
- }
-#endif
- init_free_pfn_range(start, end);
- }
-}
-#endif
-
-/*
- * paging_init() sets up the page tables - note that all of lowmem is
- * already mapped by head.S.
- */
-void __init paging_init(void)
-{
-#ifdef __tilegx__
- pud_t *pud;
-#endif
- pgd_t *pgd_base = swapper_pg_dir;
-
- kernel_physical_mapping_init(pgd_base);
-
- /* Fixed mappings, only the page table structure has to be created. */
- page_table_range_init(fix_to_virt(__end_of_fixed_addresses - 1),
- FIXADDR_TOP, pgd_base);
-
-#ifdef CONFIG_HIGHMEM
- permanent_kmaps_init(pgd_base);
-#endif
-
-#ifdef __tilegx__
- /*
- * Since GX allocates just one pmd_t array worth of vmalloc space,
- * we go ahead and allocate it statically here, then share it
- * globally. As a result we don't have to worry about any task
- * changing init_mm once we get up and running, and there's no
- * need for e.g. vmalloc_sync_all().
- */
- BUILD_BUG_ON(pgd_index(VMALLOC_START) != pgd_index(VMALLOC_END - 1));
- pud = pud_offset(pgd_base + pgd_index(VMALLOC_START), VMALLOC_START);
- assign_pmd(pud, alloc_pmd());
-#endif
-}
-
-
-/*
- * Walk the kernel page tables and derive the page_home() from
- * the PTEs, so that set_pte() can properly validate the caching
- * of all PTEs it sees.
- */
-void __init set_page_homes(void)
-{
-}
-
-static void __init set_max_mapnr_init(void)
-{
-#ifdef CONFIG_FLATMEM
- max_mapnr = max_low_pfn;
-#endif
-}
-
-void __init mem_init(void)
-{
- int i;
-#ifndef __tilegx__
- void *last;
-#endif
-
-#ifdef CONFIG_FLATMEM
- BUG_ON(!mem_map);
-#endif
-
-#ifdef CONFIG_HIGHMEM
- /* check that fixmap and pkmap do not overlap */
- if (PKMAP_ADDR(LAST_PKMAP-1) >= FIXADDR_START) {
- pr_err("fixmap and kmap areas overlap - this will crash\n");
- pr_err("pkstart: %lxh pkend: %lxh fixstart %lxh\n",
- PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP-1), FIXADDR_START);
- BUG();
- }
-#endif
-
- set_max_mapnr_init();
-
- /* this will put all bootmem onto the freelists */
- free_all_bootmem();
-
-#ifndef CONFIG_64BIT
- /* count all remaining LOWMEM and give all HIGHMEM to page allocator */
- set_non_bootmem_pages_init();
-#endif
-
- mem_init_print_info(NULL);
-
- /*
- * In debug mode, dump some interesting memory mappings.
- */
-#ifdef CONFIG_HIGHMEM
- printk(KERN_DEBUG " KMAP %#lx - %#lx\n",
- FIXADDR_START, FIXADDR_TOP + PAGE_SIZE - 1);
- printk(KERN_DEBUG " PKMAP %#lx - %#lx\n",
- PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP) - 1);
-#endif
- printk(KERN_DEBUG " VMALLOC %#lx - %#lx\n",
- _VMALLOC_START, _VMALLOC_END - 1);
-#ifdef __tilegx__
- for (i = MAX_NUMNODES-1; i >= 0; --i) {
- struct pglist_data *node = &node_data[i];
- if (node->node_present_pages) {
- unsigned long start = (unsigned long)
- pfn_to_kaddr(node->node_start_pfn);
- unsigned long end = start +
- (node->node_present_pages << PAGE_SHIFT);
- printk(KERN_DEBUG " MEM%d %#lx - %#lx\n",
- i, start, end - 1);
- }
- }
-#else
- last = high_memory;
- for (i = MAX_NUMNODES-1; i >= 0; --i) {
- if ((unsigned long)vbase_map[i] != -1UL) {
- printk(KERN_DEBUG " LOWMEM%d %#lx - %#lx\n",
- i, (unsigned long) (vbase_map[i]),
- (unsigned long) (last-1));
- last = vbase_map[i];
- }
- }
-#endif
-
-#ifndef __tilegx__
- /*
- * Convert from using one lock for all atomic operations to
- * one per cpu.
- */
- __init_atomic_per_cpu();
-#endif
-}
-
-struct kmem_cache *pgd_cache;
-
-void __init pgtable_cache_init(void)
-{
- pgd_cache = kmem_cache_create("pgd", SIZEOF_PGD, SIZEOF_PGD, 0, NULL);
- if (!pgd_cache)
- panic("pgtable_cache_init(): Cannot create pgd cache");
-}
-
-static long __ro_after_init initfree = 1;
-static bool __ro_after_init set_initfree_done;
-
-/* Select whether to free (1) or mark unusable (0) the __init pages. */
-static int __init set_initfree(char *str)
-{
- long val;
- if (kstrtol(str, 0, &val) == 0) {
- set_initfree_done = true;
- initfree = val;
- pr_info("initfree: %s free init pages\n",
- initfree ? "will" : "won't");
- }
- return 1;
-}
-__setup("initfree=", set_initfree);
-
-static void free_init_pages(char *what, unsigned long begin, unsigned long end)
-{
- unsigned long addr = (unsigned long) begin;
-
- /* Prefer user request first */
- if (!set_initfree_done) {
- if (debug_pagealloc_enabled())
- initfree = 0;
- }
- if (kdata_huge && !initfree) {
- pr_warn("Warning: ignoring initfree=0: incompatible with kdata=huge\n");
- initfree = 1;
- }
- end = (end + PAGE_SIZE - 1) & PAGE_MASK;
- local_flush_tlb_pages(NULL, begin, PAGE_SIZE, end - begin);
- for (addr = begin; addr < end; addr += PAGE_SIZE) {
- /*
- * Note we just reset the home here directly in the
- * page table. We know this is safe because our caller
- * just flushed the caches on all the other cpus,
- * and they won't be touching any of these pages.
- */
- int pfn = kaddr_to_pfn((void *)addr);
- struct page *page = pfn_to_page(pfn);
- pte_t *ptep = virt_to_kpte(addr);
- if (!initfree) {
- /*
- * If debugging page accesses then do not free
- * this memory but mark them not present - any
- * buggy init-section access will create a
- * kernel page fault:
- */
- pte_clear(&init_mm, addr, ptep);
- continue;
- }
- if (pte_huge(*ptep))
- BUG_ON(!kdata_huge);
- else
- set_pte_at(&init_mm, addr, ptep,
- pfn_pte(pfn, PAGE_KERNEL));
- memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
- free_reserved_page(page);
- }
- pr_info("Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
-}
-
-void free_initmem(void)
-{
- const unsigned long text_delta = MEM_SV_START - PAGE_OFFSET;
-
- /*
- * Evict the cache on all cores to avoid incoherence.
- * We are guaranteed that no one will touch the init pages any more.
- */
- homecache_evict(&cpu_cacheable_map);
-
- /* Free the data pages that we won't use again after init. */
- free_init_pages("unused kernel data",
- (unsigned long)__init_begin,
- (unsigned long)__init_end);
-
- /*
- * Free the pages mapped from 0xc0000000 that correspond to code
- * pages from MEM_SV_START that we won't use again after init.
- */
- free_init_pages("unused kernel text",
- (unsigned long)_sinittext - text_delta,
- (unsigned long)_einittext - text_delta);
- /* Do a global TLB flush so everyone sees the changes. */
- flush_tlb_all();
-}
diff --git a/arch/tile/mm/migrate.h b/arch/tile/mm/migrate.h
deleted file mode 100644
index 91683d97917e..000000000000
--- a/arch/tile/mm/migrate.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Structure definitions for migration, exposed here for use by
- * arch/tile/kernel/asm-offsets.c.
- */
-
-#ifndef MM_MIGRATE_H
-#define MM_MIGRATE_H
-
-#include <linux/cpumask.h>
-#include <hv/hypervisor.h>
-
-/*
- * This function is used as a helper when setting up the initial
- * page table (swapper_pg_dir).
- *
- * You must mask ALL interrupts prior to invoking this code, since
- * you can't legally touch the stack during the cache flush.
- */
-extern int flush_and_install_context(HV_PhysAddr page_table, HV_PTE access,
- HV_ASID asid,
- const unsigned long *cpumask);
-
-/*
- * This function supports migration as a "helper" as follows:
- *
- * - Set the stack PTE itself to "migrating".
- * - Do a global TLB flush for (va,length) and the specified ASIDs.
- * - Do a cache-evict on all necessary cpus.
- * - Write the new stack PTE.
- *
- * Note that any non-NULL pointers must not point to the page that
- * is handled by the stack_pte itself.
- *
- * You must mask ALL interrupts prior to invoking this code, since
- * you can't legally touch the stack during the cache flush.
- */
-extern int homecache_migrate_stack_and_flush(pte_t stack_pte, unsigned long va,
- size_t length, pte_t *stack_ptep,
- const struct cpumask *cache_cpumask,
- const struct cpumask *tlb_cpumask,
- HV_Remote_ASID *asids,
- int asidcount);
-
-#endif /* MM_MIGRATE_H */
diff --git a/arch/tile/mm/migrate_32.S b/arch/tile/mm/migrate_32.S
deleted file mode 100644
index 772085491bf9..000000000000
--- a/arch/tile/mm/migrate_32.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * This routine is a helper for migrating the home of a set of pages to
- * a new cpu. See the documentation in homecache.c for more information.
- */
-
-#include <linux/linkage.h>
-#include <linux/threads.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-#include <asm/types.h>
-#include <asm/asm-offsets.h>
-#include <hv/hypervisor.h>
-
- .text
-
-/*
- * First, some definitions that apply to all the code in the file.
- */
-
-/* Locals (caller-save) */
-#define r_tmp r10
-#define r_save_sp r11
-
-/* What we save where in the stack frame; must include all callee-saves. */
-#define FRAME_SP 4
-#define FRAME_R30 8
-#define FRAME_R31 12
-#define FRAME_R32 16
-#define FRAME_R33 20
-#define FRAME_R34 24
-#define FRAME_SIZE 28
-
-
-
-
-/*
- * On entry:
- *
- * r0 low word of the new context PA to install (moved to r_context_lo)
- * r1 high word of the new context PA to install (moved to r_context_hi)
- * r2 low word of PTE to use for context access (moved to r_access_lo)
- * r3 high word of PTE to use for context access (moved to r_access_lo)
- * r4 ASID to use for new context (moved to r_asid)
- * r5 pointer to cpumask with just this cpu set in it (r_my_cpumask)
- */
-
-/* Arguments (caller-save) */
-#define r_context_lo_in r0
-#define r_context_hi_in r1
-#define r_access_lo_in r2
-#define r_access_hi_in r3
-#define r_asid_in r4
-#define r_my_cpumask r5
-
-/* Locals (callee-save); must not be more than FRAME_xxx above. */
-#define r_context_lo r30
-#define r_context_hi r31
-#define r_access_lo r32
-#define r_access_hi r33
-#define r_asid r34
-
-STD_ENTRY(flush_and_install_context)
- /*
- * Create a stack frame; we can't touch it once we flush the
- * cache until we install the new page table and flush the TLB.
- */
- {
- move r_save_sp, sp
- sw sp, lr
- addi sp, sp, -FRAME_SIZE
- }
- addi r_tmp, sp, FRAME_SP
- {
- sw r_tmp, r_save_sp
- addi r_tmp, sp, FRAME_R30
- }
- {
- sw r_tmp, r30
- addi r_tmp, sp, FRAME_R31
- }
- {
- sw r_tmp, r31
- addi r_tmp, sp, FRAME_R32
- }
- {
- sw r_tmp, r32
- addi r_tmp, sp, FRAME_R33
- }
- {
- sw r_tmp, r33
- addi r_tmp, sp, FRAME_R34
- }
- sw r_tmp, r34
-
- /* Move some arguments to callee-save registers. */
- {
- move r_context_lo, r_context_lo_in
- move r_context_hi, r_context_hi_in
- }
- {
- move r_access_lo, r_access_lo_in
- move r_access_hi, r_access_hi_in
- }
- move r_asid, r_asid_in
-
- /* First, flush our L2 cache. */
- {
- move r0, zero /* cache_pa */
- move r1, zero
- }
- {
- auli r2, zero, ha16(HV_FLUSH_EVICT_L2) /* cache_control */
- move r3, r_my_cpumask /* cache_cpumask */
- }
- {
- move r4, zero /* tlb_va */
- move r5, zero /* tlb_length */
- }
- {
- move r6, zero /* tlb_pgsize */
- move r7, zero /* tlb_cpumask */
- }
- {
- move r8, zero /* asids */
- move r9, zero /* asidcount */
- }
- jal _hv_flush_remote
- bnz r0, .Ldone
-
- /* Now install the new page table. */
- {
- move r0, r_context_lo
- move r1, r_context_hi
- }
- {
- move r2, r_access_lo
- move r3, r_access_hi
- }
- {
- move r4, r_asid
- moveli r5, HV_CTX_DIRECTIO | CTX_PAGE_FLAG
- }
- jal _hv_install_context
- bnz r0, .Ldone
-
- /* Finally, flush the TLB. */
- {
- movei r0, 0 /* preserve_global */
- jal hv_flush_all
- }
-
-.Ldone:
- /* Restore the callee-saved registers and return. */
- addli lr, sp, FRAME_SIZE
- {
- lw lr, lr
- addli r_tmp, sp, FRAME_R30
- }
- {
- lw r30, r_tmp
- addli r_tmp, sp, FRAME_R31
- }
- {
- lw r31, r_tmp
- addli r_tmp, sp, FRAME_R32
- }
- {
- lw r32, r_tmp
- addli r_tmp, sp, FRAME_R33
- }
- {
- lw r33, r_tmp
- addli r_tmp, sp, FRAME_R34
- }
- {
- lw r34, r_tmp
- addi sp, sp, FRAME_SIZE
- }
- jrp lr
- STD_ENDPROC(flush_and_install_context)
diff --git a/arch/tile/mm/migrate_64.S b/arch/tile/mm/migrate_64.S
deleted file mode 100644
index a49eee38f872..000000000000
--- a/arch/tile/mm/migrate_64.S
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2011 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * This routine is a helper for migrating the home of a set of pages to
- * a new cpu. See the documentation in homecache.c for more information.
- */
-
-#include <linux/linkage.h>
-#include <linux/threads.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
-#include <asm/types.h>
-#include <asm/asm-offsets.h>
-#include <hv/hypervisor.h>
-
- .text
-
-/*
- * First, some definitions that apply to all the code in the file.
- */
-
-/* Locals (caller-save) */
-#define r_tmp r10
-#define r_save_sp r11
-
-/* What we save where in the stack frame; must include all callee-saves. */
-#define FRAME_SP 8
-#define FRAME_R30 16
-#define FRAME_R31 24
-#define FRAME_R32 32
-#define FRAME_SIZE 40
-
-
-
-
-/*
- * On entry:
- *
- * r0 the new context PA to install (moved to r_context)
- * r1 PTE to use for context access (moved to r_access)
- * r2 ASID to use for new context (moved to r_asid)
- * r3 pointer to cpumask with just this cpu set in it (r_my_cpumask)
- */
-
-/* Arguments (caller-save) */
-#define r_context_in r0
-#define r_access_in r1
-#define r_asid_in r2
-#define r_my_cpumask r3
-
-/* Locals (callee-save); must not be more than FRAME_xxx above. */
-#define r_context r30
-#define r_access r31
-#define r_asid r32
-
-/*
- * Caller-save locals and frame constants are the same as
- * for homecache_migrate_stack_and_flush.
- */
-
-STD_ENTRY(flush_and_install_context)
- /*
- * Create a stack frame; we can't touch it once we flush the
- * cache until we install the new page table and flush the TLB.
- */
- {
- move r_save_sp, sp
- st sp, lr
- addi sp, sp, -FRAME_SIZE
- }
- addi r_tmp, sp, FRAME_SP
- {
- st r_tmp, r_save_sp
- addi r_tmp, sp, FRAME_R30
- }
- {
- st r_tmp, r30
- addi r_tmp, sp, FRAME_R31
- }
- {
- st r_tmp, r31
- addi r_tmp, sp, FRAME_R32
- }
- st r_tmp, r32
-
- /* Move some arguments to callee-save registers. */
- {
- move r_context, r_context_in
- move r_access, r_access_in
- }
- move r_asid, r_asid_in
-
- /* First, flush our L2 cache. */
- {
- move r0, zero /* cache_pa */
- moveli r1, hw2_last(HV_FLUSH_EVICT_L2) /* cache_control */
- }
- {
- shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
- move r2, r_my_cpumask /* cache_cpumask */
- }
- {
- shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2)
- move r3, zero /* tlb_va */
- }
- {
- move r4, zero /* tlb_length */
- move r5, zero /* tlb_pgsize */
- }
- {
- move r6, zero /* tlb_cpumask */
- move r7, zero /* asids */
- }
- {
- move r8, zero /* asidcount */
- jal _hv_flush_remote
- }
- bnez r0, 1f
-
- /* Now install the new page table. */
- {
- move r0, r_context
- move r1, r_access
- }
- {
- move r2, r_asid
- moveli r3, HV_CTX_DIRECTIO | CTX_PAGE_FLAG
- }
- jal _hv_install_context
- bnez r0, 1f
-
- /* Finally, flush the TLB. */
- {
- movei r0, 0 /* preserve_global */
- jal hv_flush_all
- }
-
-1: /* Restore the callee-saved registers and return. */
- addli lr, sp, FRAME_SIZE
- {
- ld lr, lr
- addli r_tmp, sp, FRAME_R30
- }
- {
- ld r30, r_tmp
- addli r_tmp, sp, FRAME_R31
- }
- {
- ld r31, r_tmp
- addli r_tmp, sp, FRAME_R32
- }
- {
- ld r32, r_tmp
- addi sp, sp, FRAME_SIZE
- }
- jrp lr
- STD_ENDPROC(flush_and_install_context)
diff --git a/arch/tile/mm/mmap.c b/arch/tile/mm/mmap.c
deleted file mode 100644
index 8ab28167c44b..000000000000
--- a/arch/tile/mm/mmap.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- *
- * Taken from the i386 architecture and simplified.
- */
-
-#include <linux/mm.h>
-#include <linux/random.h>
-#include <linux/limits.h>
-#include <linux/sched/signal.h>
-#include <linux/sched/mm.h>
-#include <linux/mman.h>
-#include <linux/compat.h>
-
-/*
- * Top of mmap area (just below the process stack).
- *
- * Leave an at least ~128 MB hole.
- */
-#define MIN_GAP (128*1024*1024)
-#define MAX_GAP (TASK_SIZE/6*5)
-
-static inline unsigned long mmap_base(struct mm_struct *mm)
-{
- unsigned long gap = rlimit(RLIMIT_STACK);
- unsigned long random_factor = 0;
-
- if (current->flags & PF_RANDOMIZE)
- random_factor = get_random_int() % (1024*1024);
-
- if (gap < MIN_GAP)
- gap = MIN_GAP;
- else if (gap > MAX_GAP)
- gap = MAX_GAP;
-
- return PAGE_ALIGN(TASK_SIZE - gap - random_factor);
-}
-
-/*
- * This function, called very early during the creation of a new
- * process VM image, sets up which VM layout function to use:
- */
-void arch_pick_mmap_layout(struct mm_struct *mm)
-{
-#if !defined(__tilegx__)
- int is_32bit = 1;
-#elif defined(CONFIG_COMPAT)
- int is_32bit = is_compat_task();
-#else
- int is_32bit = 0;
-#endif
- unsigned long random_factor = 0UL;
-
- /*
- * 8 bits of randomness in 32bit mmaps, 24 address space bits
- * 12 bits of randomness in 64bit mmaps, 28 address space bits
- */
- if (current->flags & PF_RANDOMIZE) {
- if (is_32bit)
- random_factor = get_random_int() % (1<<8);
- else
- random_factor = get_random_int() % (1<<12);
-
- random_factor <<= PAGE_SHIFT;
- }
-
- /*
- * Use standard layout if the expected stack growth is unlimited
- * or we are running native 64 bits.
- */
- if (rlimit(RLIMIT_STACK) == RLIM_INFINITY) {
- mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
- mm->get_unmapped_area = arch_get_unmapped_area;
- } else {
- mm->mmap_base = mmap_base(mm);
- mm->get_unmapped_area = arch_get_unmapped_area_topdown;
- }
-}
-
-unsigned long arch_randomize_brk(struct mm_struct *mm)
-{
- return randomize_page(mm->brk, 0x02000000);
-}
diff --git a/arch/tile/mm/pgtable.c b/arch/tile/mm/pgtable.c
deleted file mode 100644
index ec5576fd3a86..000000000000
--- a/arch/tile/mm/pgtable.c
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/highmem.h>
-#include <linux/slab.h>
-#include <linux/pagemap.h>
-#include <linux/spinlock.h>
-#include <linux/cpumask.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/vmalloc.h>
-#include <linux/smp.h>
-
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-#include <asm/fixmap.h>
-#include <asm/tlb.h>
-#include <asm/tlbflush.h>
-#include <asm/homecache.h>
-
-#define K(x) ((x) << (PAGE_SHIFT-10))
-
-/**
- * shatter_huge_page() - ensure a given address is mapped by a small page.
- *
- * This function converts a huge PTE mapping kernel LOWMEM into a bunch
- * of small PTEs with the same caching. No cache flush required, but we
- * must do a global TLB flush.
- *
- * Any caller that wishes to modify a kernel mapping that might
- * have been made with a huge page should call this function,
- * since doing so properly avoids race conditions with installing the
- * newly-shattered page and then flushing all the TLB entries.
- *
- * @addr: Address at which to shatter any existing huge page.
- */
-void shatter_huge_page(unsigned long addr)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- unsigned long flags = 0; /* happy compiler */
-#ifdef __PAGETABLE_PMD_FOLDED
- struct list_head *pos;
-#endif
-
- /* Get a pointer to the pmd entry that we need to change. */
- addr &= HPAGE_MASK;
- BUG_ON(pgd_addr_invalid(addr));
- BUG_ON(addr < PAGE_OFFSET); /* only for kernel LOWMEM */
- pgd = swapper_pg_dir + pgd_index(addr);
- pud = pud_offset(pgd, addr);
- BUG_ON(!pud_present(*pud));
- pmd = pmd_offset(pud, addr);
- BUG_ON(!pmd_present(*pmd));
- if (!pmd_huge_page(*pmd))
- return;
-
- spin_lock_irqsave(&init_mm.page_table_lock, flags);
- if (!pmd_huge_page(*pmd)) {
- /* Lost the race to convert the huge page. */
- spin_unlock_irqrestore(&init_mm.page_table_lock, flags);
- return;
- }
-
- /* Shatter the huge page into the preallocated L2 page table. */
- pmd_populate_kernel(&init_mm, pmd, get_prealloc_pte(pmd_pfn(*pmd)));
-
-#ifdef __PAGETABLE_PMD_FOLDED
- /* Walk every pgd on the system and update the pmd there. */
- spin_lock(&pgd_lock);
- list_for_each(pos, &pgd_list) {
- pmd_t *copy_pmd;
- pgd = list_to_pgd(pos) + pgd_index(addr);
- pud = pud_offset(pgd, addr);
- copy_pmd = pmd_offset(pud, addr);
- __set_pmd(copy_pmd, *pmd);
- }
- spin_unlock(&pgd_lock);
-#endif
-
- /* Tell every cpu to notice the change. */
- flush_remote(0, 0, NULL, addr, HPAGE_SIZE, HPAGE_SIZE,
- cpu_possible_mask, NULL, 0);
-
- /* Hold the lock until the TLB flush is finished to avoid races. */
- spin_unlock_irqrestore(&init_mm.page_table_lock, flags);
-}
-
-/*
- * List of all pgd's needed so it can invalidate entries in both cached
- * and uncached pgd's. This is essentially codepath-based locking
- * against pageattr.c; it is the unique case in which a valid change
- * of kernel pagetables can't be lazily synchronized by vmalloc faults.
- * vmalloc faults work because attached pagetables are never freed.
- *
- * The lock is always taken with interrupts disabled, unlike on x86
- * and other platforms, because we need to take the lock in
- * shatter_huge_page(), which may be called from an interrupt context.
- * We are not at risk from the tlbflush IPI deadlock that was seen on
- * x86, since we use the flush_remote() API to have the hypervisor do
- * the TLB flushes regardless of irq disabling.
- */
-DEFINE_SPINLOCK(pgd_lock);
-LIST_HEAD(pgd_list);
-
-static inline void pgd_list_add(pgd_t *pgd)
-{
- list_add(pgd_to_list(pgd), &pgd_list);
-}
-
-static inline void pgd_list_del(pgd_t *pgd)
-{
- list_del(pgd_to_list(pgd));
-}
-
-#define KERNEL_PGD_INDEX_START pgd_index(PAGE_OFFSET)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_INDEX_START)
-
-static void pgd_ctor(pgd_t *pgd)
-{
- unsigned long flags;
-
- memset(pgd, 0, KERNEL_PGD_INDEX_START*sizeof(pgd_t));
- spin_lock_irqsave(&pgd_lock, flags);
-
-#ifndef __tilegx__
- /*
- * Check that the user interrupt vector has no L2.
- * It never should for the swapper, and new page tables
- * should always start with an empty user interrupt vector.
- */
- BUG_ON(((u64 *)swapper_pg_dir)[pgd_index(MEM_USER_INTRPT)] != 0);
-#endif
-
- memcpy(pgd + KERNEL_PGD_INDEX_START,
- swapper_pg_dir + KERNEL_PGD_INDEX_START,
- KERNEL_PGD_PTRS * sizeof(pgd_t));
-
- pgd_list_add(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
-}
-
-static void pgd_dtor(pgd_t *pgd)
-{
- unsigned long flags; /* can be called from interrupt context */
-
- spin_lock_irqsave(&pgd_lock, flags);
- pgd_list_del(pgd);
- spin_unlock_irqrestore(&pgd_lock, flags);
-}
-
-pgd_t *pgd_alloc(struct mm_struct *mm)
-{
- pgd_t *pgd = kmem_cache_alloc(pgd_cache, GFP_KERNEL);
- if (pgd)
- pgd_ctor(pgd);
- return pgd;
-}
-
-void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
- pgd_dtor(pgd);
- kmem_cache_free(pgd_cache, pgd);
-}
-
-
-#define L2_USER_PGTABLE_PAGES (1 << L2_USER_PGTABLE_ORDER)
-
-struct page *pgtable_alloc_one(struct mm_struct *mm, unsigned long address,
- int order)
-{
- gfp_t flags = GFP_KERNEL|__GFP_ZERO;
- struct page *p;
- int i;
-
- p = alloc_pages(flags, L2_USER_PGTABLE_ORDER);
- if (p == NULL)
- return NULL;
-
- if (!pgtable_page_ctor(p)) {
- __free_pages(p, L2_USER_PGTABLE_ORDER);
- return NULL;
- }
-
- /*
- * Make every page have a page_count() of one, not just the first.
- * We don't use __GFP_COMP since it doesn't look like it works
- * correctly with tlb_remove_page().
- */
- for (i = 1; i < order; ++i) {
- init_page_count(p+i);
- inc_zone_page_state(p+i, NR_PAGETABLE);
- }
-
- return p;
-}
-
-/*
- * Free page immediately (used in __pte_alloc if we raced with another
- * process). We have to correct whatever pte_alloc_one() did before
- * returning the pages to the allocator.
- */
-void pgtable_free(struct mm_struct *mm, struct page *p, int order)
-{
- int i;
-
- pgtable_page_dtor(p);
- __free_page(p);
-
- for (i = 1; i < order; ++i) {
- __free_page(p+i);
- dec_zone_page_state(p+i, NR_PAGETABLE);
- }
-}
-
-void __pgtable_free_tlb(struct mmu_gather *tlb, struct page *pte,
- unsigned long address, int order)
-{
- int i;
-
- pgtable_page_dtor(pte);
- tlb_remove_page(tlb, pte);
-
- for (i = 1; i < order; ++i) {
- tlb_remove_page(tlb, pte + i);
- dec_zone_page_state(pte + i, NR_PAGETABLE);
- }
-}
-
-#ifndef __tilegx__
-
-/*
- * FIXME: needs to be atomic vs hypervisor writes. For now we make the
- * window of vulnerability a bit smaller by doing an unlocked 8-bit update.
- */
-int ptep_test_and_clear_young(struct vm_area_struct *vma,
- unsigned long addr, pte_t *ptep)
-{
-#if HV_PTE_INDEX_ACCESSED < 8 || HV_PTE_INDEX_ACCESSED >= 16
-# error Code assumes HV_PTE "accessed" bit in second byte
-#endif
- u8 *tmp = (u8 *)ptep;
- u8 second_byte = tmp[1];
- if (!(second_byte & (1 << (HV_PTE_INDEX_ACCESSED - 8))))
- return 0;
- tmp[1] = second_byte & ~(1 << (HV_PTE_INDEX_ACCESSED - 8));
- return 1;
-}
-
-/*
- * This implementation is atomic vs hypervisor writes, since the hypervisor
- * always writes the low word (where "accessed" and "dirty" are) and this
- * routine only writes the high word.
- */
-void ptep_set_wrprotect(struct mm_struct *mm,
- unsigned long addr, pte_t *ptep)
-{
-#if HV_PTE_INDEX_WRITABLE < 32
-# error Code assumes HV_PTE "writable" bit in high word
-#endif
- u32 *tmp = (u32 *)ptep;
- tmp[1] = tmp[1] & ~(1 << (HV_PTE_INDEX_WRITABLE - 32));
-}
-
-#endif
-
-/*
- * Return a pointer to the PTE that corresponds to the given
- * address in the given page table. A NULL page table just uses
- * the standard kernel page table; the preferred API in this case
- * is virt_to_kpte().
- *
- * The returned pointer can point to a huge page in other levels
- * of the page table than the bottom, if the huge page is present
- * in the page table. For bottom-level PTEs, the returned pointer
- * can point to a PTE that is either present or not.
- */
-pte_t *virt_to_pte(struct mm_struct* mm, unsigned long addr)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
-
- if (pgd_addr_invalid(addr))
- return NULL;
-
- pgd = mm ? pgd_offset(mm, addr) : swapper_pg_dir + pgd_index(addr);
- pud = pud_offset(pgd, addr);
- if (!pud_present(*pud))
- return NULL;
- if (pud_huge_page(*pud))
- return (pte_t *)pud;
- pmd = pmd_offset(pud, addr);
- if (!pmd_present(*pmd))
- return NULL;
- if (pmd_huge_page(*pmd))
- return (pte_t *)pmd;
- return pte_offset_kernel(pmd, addr);
-}
-EXPORT_SYMBOL(virt_to_pte);
-
-pte_t *virt_to_kpte(unsigned long kaddr)
-{
- BUG_ON(kaddr < PAGE_OFFSET);
- return virt_to_pte(NULL, kaddr);
-}
-EXPORT_SYMBOL(virt_to_kpte);
-
-pgprot_t set_remote_cache_cpu(pgprot_t prot, int cpu)
-{
- unsigned int width = smp_width;
- int x = cpu % width;
- int y = cpu / width;
- BUG_ON(y >= smp_height);
- BUG_ON(hv_pte_get_mode(prot) != HV_PTE_MODE_CACHE_TILE_L3);
- BUG_ON(cpu < 0 || cpu >= NR_CPUS);
- BUG_ON(!cpu_is_valid_lotar(cpu));
- return hv_pte_set_lotar(prot, HV_XY_TO_LOTAR(x, y));
-}
-
-int get_remote_cache_cpu(pgprot_t prot)
-{
- HV_LOTAR lotar = hv_pte_get_lotar(prot);
- int x = HV_LOTAR_X(lotar);
- int y = HV_LOTAR_Y(lotar);
- BUG_ON(hv_pte_get_mode(prot) != HV_PTE_MODE_CACHE_TILE_L3);
- return x + y * smp_width;
-}
-
-/*
- * Convert a kernel VA to a PA and homing information.
- */
-int va_to_cpa_and_pte(void *va, unsigned long long *cpa, pte_t *pte)
-{
- struct page *page = virt_to_page(va);
- pte_t null_pte = { 0 };
-
- *cpa = __pa(va);
-
- /* Note that this is not writing a page table, just returning a pte. */
- *pte = pte_set_home(null_pte, page_home(page));
-
- return 0; /* return non-zero if not hfh? */
-}
-EXPORT_SYMBOL(va_to_cpa_and_pte);
-
-void __set_pte(pte_t *ptep, pte_t pte)
-{
-#ifdef __tilegx__
- *ptep = pte;
-#else
-# if HV_PTE_INDEX_PRESENT >= 32 || HV_PTE_INDEX_MIGRATING >= 32
-# error Must write the present and migrating bits last
-# endif
- if (pte_present(pte)) {
- ((u32 *)ptep)[1] = (u32)(pte_val(pte) >> 32);
- barrier();
- ((u32 *)ptep)[0] = (u32)(pte_val(pte));
- } else {
- ((u32 *)ptep)[0] = (u32)(pte_val(pte));
- barrier();
- ((u32 *)ptep)[1] = (u32)(pte_val(pte) >> 32);
- }
-#endif /* __tilegx__ */
-}
-
-void set_pte(pte_t *ptep, pte_t pte)
-{
- if (pte_present(pte) &&
- (!CHIP_HAS_MMIO() || hv_pte_get_mode(pte) != HV_PTE_MODE_MMIO)) {
- /* The PTE actually references physical memory. */
- unsigned long pfn = pte_pfn(pte);
- if (pfn_valid(pfn)) {
- /* Update the home of the PTE from the struct page. */
- pte = pte_set_home(pte, page_home(pfn_to_page(pfn)));
- } else if (hv_pte_get_mode(pte) == 0) {
- /* remap_pfn_range(), etc, must supply PTE mode. */
- panic("set_pte(): out-of-range PFN and mode 0\n");
- }
- }
-
- __set_pte(ptep, pte);
-}
-
-/* Can this mm load a PTE with cached_priority set? */
-static inline int mm_is_priority_cached(struct mm_struct *mm)
-{
- return mm->context.priority_cached != 0;
-}
-
-/*
- * Add a priority mapping to an mm_context and
- * notify the hypervisor if this is the first one.
- */
-void start_mm_caching(struct mm_struct *mm)
-{
- if (!mm_is_priority_cached(mm)) {
- mm->context.priority_cached = -1UL;
- hv_set_caching(-1UL);
- }
-}
-
-/*
- * Validate and return the priority_cached flag. We know if it's zero
- * that we don't need to scan, since we immediately set it non-zero
- * when we first consider a MAP_CACHE_PRIORITY mapping.
- *
- * We only _try_ to acquire the mmap_sem semaphore; if we can't acquire it,
- * since we're in an interrupt context (servicing switch_mm) we don't
- * worry about it and don't unset the "priority_cached" field.
- * Presumably we'll come back later and have more luck and clear
- * the value then; for now we'll just keep the cache marked for priority.
- */
-static unsigned long update_priority_cached(struct mm_struct *mm)
-{
- if (mm->context.priority_cached && down_write_trylock(&mm->mmap_sem)) {
- struct vm_area_struct *vm;
- for (vm = mm->mmap; vm; vm = vm->vm_next) {
- if (hv_pte_get_cached_priority(vm->vm_page_prot))
- break;
- }
- if (vm == NULL)
- mm->context.priority_cached = 0;
- up_write(&mm->mmap_sem);
- }
- return mm->context.priority_cached;
-}
-
-/* Set caching correctly for an mm that we are switching to. */
-void check_mm_caching(struct mm_struct *prev, struct mm_struct *next)
-{
- if (!mm_is_priority_cached(next)) {
- /*
- * If the new mm doesn't use priority caching, just see if we
- * need the hv_set_caching(), or can assume it's already zero.
- */
- if (mm_is_priority_cached(prev))
- hv_set_caching(0);
- } else {
- hv_set_caching(update_priority_cached(next));
- }
-}
-
-#if CHIP_HAS_MMIO()
-
-/* Map an arbitrary MMIO address, homed according to pgprot, into VA space. */
-void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size,
- pgprot_t home)
-{
- void *addr;
- struct vm_struct *area;
- unsigned long offset, last_addr;
- pgprot_t pgprot;
-
- /* Don't allow wraparound or zero size */
- last_addr = phys_addr + size - 1;
- if (!size || last_addr < phys_addr)
- return NULL;
-
- /* Create a read/write, MMIO VA mapping homed at the requested shim. */
- pgprot = PAGE_KERNEL;
- pgprot = hv_pte_set_mode(pgprot, HV_PTE_MODE_MMIO);
- pgprot = hv_pte_set_lotar(pgprot, hv_pte_get_lotar(home));
-
- /*
- * Mappings have to be page-aligned
- */
- offset = phys_addr & ~PAGE_MASK;
- phys_addr &= PAGE_MASK;
- size = PAGE_ALIGN(last_addr+1) - phys_addr;
-
- /*
- * Ok, go for it..
- */
- area = get_vm_area(size, VM_IOREMAP /* | other flags? */);
- if (!area)
- return NULL;
- area->phys_addr = phys_addr;
- addr = area->addr;
- if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size,
- phys_addr, pgprot)) {
- free_vm_area(area);
- return NULL;
- }
- return (__force void __iomem *) (offset + (char *)addr);
-}
-EXPORT_SYMBOL(ioremap_prot);
-
-#if !defined(CONFIG_PCI) || !defined(CONFIG_TILEGX)
-/* ioremap is conditionally declared in pci_gx.c */
-
-void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
-{
- return NULL;
-}
-EXPORT_SYMBOL(ioremap);
-
-#endif
-
-/* Unmap an MMIO VA mapping. */
-void iounmap(volatile void __iomem *addr_in)
-{
- volatile void __iomem *addr = (volatile void __iomem *)
- (PAGE_MASK & (unsigned long __force)addr_in);
-#if 1
- vunmap((void * __force)addr);
-#else
- /* x86 uses this complicated flow instead of vunmap(). Is
- * there any particular reason we should do the same? */
- struct vm_struct *p, *o;
-
- /* Use the vm area unlocked, assuming the caller
- ensures there isn't another iounmap for the same address
- in parallel. Reuse of the virtual address is prevented by
- leaving it in the global lists until we're done with it.
- cpa takes care of the direct mappings. */
- p = find_vm_area((void *)addr);
-
- if (!p) {
- pr_err("iounmap: bad address %p\n", addr);
- dump_stack();
- return;
- }
-
- /* Finally remove it */
- o = remove_vm_area((void *)addr);
- BUG_ON(p != o || o == NULL);
- kfree(p);
-#endif
-}
-EXPORT_SYMBOL(iounmap);
-
-#endif /* CHIP_HAS_MMIO() */
diff --git a/arch/um/kernel/syscall.c b/arch/um/kernel/syscall.c
index 6258676bed85..35f7047bdebc 100644
--- a/arch/um/kernel/syscall.c
+++ b/arch/um/kernel/syscall.c
@@ -22,7 +22,7 @@ long old_mmap(unsigned long addr, unsigned long len,
if (offset & ~PAGE_MASK)
goto out;
- err = sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+ err = ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
out:
return err;
}
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a9f0048b880a..a29df2353da5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -29,6 +29,7 @@ config X86_64
select HAVE_ARCH_SOFT_DIRTY
select MODULES_USE_ELF_RELA
select X86_DEV_DMA_OPS
+ select ARCH_HAS_SYSCALL_WRAPPER
#
# Arch settings
@@ -54,7 +55,6 @@ config X86
select ARCH_HAS_FORTIFY_SOURCE
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_HAS_KCOV if X86_64
- select ARCH_HAS_PHYS_TO_DMA
select ARCH_HAS_MEMBARRIER_SYNC_CORE
select ARCH_HAS_PMEM_API if X86_64
select ARCH_HAS_REFCOUNT
@@ -83,6 +83,7 @@ config X86
select CLOCKSOURCE_VALIDATE_LAST_CYCLE
select CLOCKSOURCE_WATCHDOG
select DCACHE_WORD_ACCESS
+ select DMA_DIRECT_OPS
select EDAC_ATOMIC_SCRUB
select EDAC_SUPPORT
select GENERIC_CLOCKEVENTS
@@ -393,17 +394,6 @@ config X86_FEATURE_NAMES
If in doubt, say Y.
-config X86_FAST_FEATURE_TESTS
- bool "Fast CPU feature tests" if EMBEDDED
- default y
- ---help---
- Some fast-paths in the kernel depend on the capabilities of the CPU.
- Say Y here for the kernel to patch in the appropriate code at runtime
- based on the capabilities of the CPU. The infrastructure for patching
- code at runtime takes up some additional space; space-constrained
- embedded systems may wish to say N here to produce smaller, slightly
- slower code.
-
config X86_X2APIC
bool "Support x2apic"
depends on X86_LOCAL_APIC && X86_64 && (IRQ_REMAP || HYPERVISOR_GUEST)
@@ -691,6 +681,7 @@ config X86_SUPPORTS_MEMORY_FAILURE
config STA2X11
bool "STA2X11 Companion Chip Support"
depends on X86_32_NON_STANDARD && PCI
+ select ARCH_HAS_PHYS_TO_DMA
select X86_DEV_DMA_OPS
select X86_DMA_REMAP
select SWIOTLB
@@ -1472,6 +1463,8 @@ config X86_PAE
config X86_5LEVEL
bool "Enable 5-level page tables support"
+ select DYNAMIC_MEMORY_LAYOUT
+ select SPARSEMEM_VMEMMAP
depends on X86_64
---help---
5-level paging enables access to larger address space:
@@ -1480,8 +1473,8 @@ config X86_5LEVEL
It will be supported by future Intel CPUs.
- Note: a kernel with this option enabled can only be booted
- on machines that support the feature.
+ A kernel with the option enabled can be booted on machines that
+ support 4- or 5-level paging.
See Documentation/x86/x86_64/5level-paging.txt for more
information.
@@ -1606,10 +1599,6 @@ config ARCH_HAVE_MEMORY_PRESENT
def_bool y
depends on X86_32 && DISCONTIGMEM
-config NEED_NODE_MEMMAP_SIZE
- def_bool y
- depends on X86_32 && (DISCONTIGMEM || SPARSEMEM)
-
config ARCH_FLATMEM_ENABLE
def_bool y
depends on X86_32 && !NUMA
@@ -2185,10 +2174,17 @@ config PHYSICAL_ALIGN
Don't change this unless you know what you are doing.
+config DYNAMIC_MEMORY_LAYOUT
+ bool
+ ---help---
+ This option makes base addresses of vmalloc and vmemmap as well as
+ __PAGE_OFFSET movable during boot.
+
config RANDOMIZE_MEMORY
bool "Randomize the kernel memory sections"
depends on X86_64
depends on RANDOMIZE_BASE
+ select DYNAMIC_MEMORY_LAYOUT
default RANDOMIZE_BASE
---help---
Randomizes the base virtual address of kernel memory sections
@@ -2307,7 +2303,7 @@ choice
it can be used to assist security vulnerability exploitation.
This setting can be changed at boot time via the kernel command
- line parameter vsyscall=[native|emulate|none].
+ line parameter vsyscall=[emulate|none].
On a system with recent enough glibc (2.14 or newer) and no
static binaries, you can say None without a performance penalty
@@ -2315,15 +2311,6 @@ choice
If unsure, select "Emulate".
- config LEGACY_VSYSCALL_NATIVE
- bool "Native"
- help
- Actual executable code is located in the fixed vsyscall
- address mapping, implementing time() efficiently. Since
- this makes the mapping executable, it can be used during
- security vulnerability exploitation (traditionally as
- ROP gadgets). This configuration is not recommended.
-
config LEGACY_VSYSCALL_EMULATE
bool "Emulate"
help
@@ -2641,8 +2628,10 @@ config PCI_DIRECT
depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC || PCI_GOMMCONFIG))
config PCI_MMCONFIG
- def_bool y
- depends on X86_32 && PCI && (ACPI || SFI) && (PCI_GOMMCONFIG || PCI_GOANY)
+ bool "Support mmconfig PCI config space access" if X86_64
+ default y
+ depends on PCI && (ACPI || SFI || JAILHOUSE_GUEST)
+ depends on X86_64 || (PCI_GOANY || PCI_GOMMCONFIG)
config PCI_OLPC
def_bool y
@@ -2657,9 +2646,9 @@ config PCI_DOMAINS
def_bool y
depends on PCI
-config PCI_MMCONFIG
- bool "Support mmconfig PCI config space access"
- depends on X86_64 && PCI && ACPI
+config MMCONF_FAM10H
+ def_bool y
+ depends on X86_64 && PCI_MMCONFIG && ACPI
config PCI_CNB20LE_QUIRK
bool "Read CNB20LE Host Bridge Windows" if EXPERT
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 8b8d2297d486..638411f22267 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -315,19 +315,6 @@ config X86_L1_CACHE_SHIFT
default "4" if MELAN || M486 || MGEODEGX1
default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
-config X86_PPRO_FENCE
- bool "PentiumPro memory ordering errata workaround"
- depends on M686 || M586MMX || M586TSC || M586 || M486 || MGEODEGX1
- ---help---
- Old PentiumPro multiprocessor systems had errata that could cause
- memory operations to violate the x86 ordering standard in rare cases.
- Enabling this option will attempt to work around some (but not all)
- occurrences of this problem, at the cost of much heavier spinlock and
- memory barrier operations.
-
- If unsure, say n here. Even distro kernels should think twice before
- enabling this: there are few systems, and an unlikely bug.
-
config X86_F00F_BUG
def_bool y
depends on M586MMX || M586TSC || M586 || M486
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 498c1b812300..60135cbd905c 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -31,8 +31,7 @@ endif
CODE16GCC_CFLAGS := -m32 -Wa,$(srctree)/arch/x86/boot/code16gcc.h
M16_CFLAGS := $(call cc-option, -m16, $(CODE16GCC_CFLAGS))
-REALMODE_CFLAGS := $(M16_CFLAGS) -g -Os -D__KERNEL__ \
- -DDISABLE_BRANCH_PROFILING \
+REALMODE_CFLAGS := $(M16_CFLAGS) -g -Os -DDISABLE_BRANCH_PROFILING \
-Wall -Wstrict-prototypes -march=i386 -mregparm=3 \
-fno-strict-aliasing -fomit-frame-pointer -fno-pic \
-mno-mmx -mno-sse
@@ -181,6 +180,10 @@ ifdef CONFIG_FUNCTION_GRAPH_TRACER
endif
endif
+ifndef CC_HAVE_ASM_GOTO
+ $(error Compiler lacks asm-goto support.)
+endif
+
#
# Jump labels need '-maccumulate-outgoing-args' for gcc < 4.5.2 to prevent a
# GCC bug (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46226). There's no way
@@ -223,6 +226,15 @@ KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr)
LDFLAGS := -m elf_$(UTS_MACHINE)
+#
+# The 64-bit kernel must be aligned to 2MB. Pass -z max-page-size=0x200000 to
+# the linker to force 2MB page size regardless of the default page size used
+# by the linker.
+#
+ifdef CONFIG_X86_64
+LDFLAGS += $(call ld-option, -z max-page-size=0x200000)
+endif
+
# Speed up the build
KBUILD_CFLAGS += -pipe
# Workaround for a gcc prelease that unfortunately was shipped in a suse release
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index f25e1530e064..fa42f895fdde 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -26,7 +26,7 @@ KCOV_INSTRUMENT := n
targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \
vmlinux.bin.xz vmlinux.bin.lzo vmlinux.bin.lz4
-KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ -O2
+KBUILD_CFLAGS := -m$(BITS) -O2
KBUILD_CFLAGS += -fno-strict-aliasing $(call cc-option, -fPIE, -fPIC)
KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
cflags-$(CONFIG_X86_32) := -march=i386
@@ -78,7 +78,7 @@ vmlinux-objs-y := $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
vmlinux-objs-$(CONFIG_EARLY_PRINTK) += $(obj)/early_serial_console.o
vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr.o
ifdef CONFIG_X86_64
- vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/pagetable.o
+ vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr_64.o
vmlinux-objs-y += $(obj)/mem_encrypt.o
vmlinux-objs-y += $(obj)/pgtable_64.o
endif
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 886a9115af62..47d3efff6805 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -421,9 +421,10 @@ static void retrieve_apple_device_properties(struct boot_params *boot_params)
}
}
+static const efi_char16_t apple[] = L"Apple";
+
static void setup_quirks(struct boot_params *boot_params)
{
- efi_char16_t const apple[] = { 'A', 'p', 'p', 'l', 'e', 0 };
efi_char16_t *fw_vendor = (efi_char16_t *)(unsigned long)
efi_table_attr(efi_system_table, fw_vendor, sys_table);
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index fc313e29fe2c..fca012baba19 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -33,6 +33,7 @@
#include <asm/processor-flags.h>
#include <asm/asm-offsets.h>
#include <asm/bootparam.h>
+#include "pgtable.h"
/*
* Locally defined symbols should be marked hidden:
@@ -304,55 +305,77 @@ ENTRY(startup_64)
/* Set up the stack */
leaq boot_stack_end(%rbx), %rsp
-#ifdef CONFIG_X86_5LEVEL
/*
- * Check if we need to enable 5-level paging.
- * RSI holds real mode data and need to be preserved across
- * a function call.
+ * At this point we are in long mode with 4-level paging enabled,
+ * but we might want to enable 5-level paging or vice versa.
+ *
+ * The problem is that we cannot do it directly. Setting or clearing
+ * CR4.LA57 in long mode would trigger #GP. So we need to switch off
+ * long mode and paging first.
+ *
+ * We also need a trampoline in lower memory to switch over from
+ * 4- to 5-level paging for cases when the bootloader puts the kernel
+ * above 4G, but didn't enable 5-level paging for us.
+ *
+ * The same trampoline can be used to switch from 5- to 4-level paging
+ * mode, like when starting 4-level paging kernel via kexec() when
+ * original kernel worked in 5-level paging mode.
+ *
+ * For the trampoline, we need the top page table to reside in lower
+ * memory as we don't have a way to load 64-bit values into CR3 in
+ * 32-bit mode.
+ *
+ * We go though the trampoline even if we don't have to: if we're
+ * already in a desired paging mode. This way the trampoline code gets
+ * tested on every boot.
*/
- pushq %rsi
- call l5_paging_required
- popq %rsi
- /* If l5_paging_required() returned zero, we're done here. */
- cmpq $0, %rax
- je lvl5
+ /* Make sure we have GDT with 32-bit code segment */
+ leaq gdt(%rip), %rax
+ movq %rax, gdt64+2(%rip)
+ lgdt gdt64(%rip)
/*
- * At this point we are in long mode with 4-level paging enabled,
- * but we want to enable 5-level paging.
+ * paging_prepare() sets up the trampoline and checks if we need to
+ * enable 5-level paging.
*
- * The problem is that we cannot do it directly. Setting LA57 in
- * long mode would trigger #GP. So we need to switch off long mode
- * first.
+ * Address of the trampoline is returned in RAX.
+ * Non zero RDX on return means we need to enable 5-level paging.
*
- * NOTE: This is not going to work if bootloader put us above 4G
- * limit.
- *
- * The first step is go into compatibility mode.
+ * RSI holds real mode data and needs to be preserved across
+ * this function call.
*/
+ pushq %rsi
+ call paging_prepare
+ popq %rsi
- /* Clear additional page table */
- leaq lvl5_pgtable(%rbx), %rdi
- xorq %rax, %rax
- movq $(PAGE_SIZE/8), %rcx
- rep stosq
+ /* Save the trampoline address in RCX */
+ movq %rax, %rcx
/*
- * Setup current CR3 as the first and only entry in a new top level
- * page table.
+ * Load the address of trampoline_return() into RDI.
+ * It will be used by the trampoline to return to the main code.
*/
- movq %cr3, %rdi
- leaq 0x7 (%rdi), %rax
- movq %rax, lvl5_pgtable(%rbx)
+ leaq trampoline_return(%rip), %rdi
/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
pushq $__KERNEL32_CS
- leaq compatible_mode(%rip), %rax
+ leaq TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax
pushq %rax
lretq
-lvl5:
-#endif
+trampoline_return:
+ /* Restore the stack, the 32-bit trampoline uses its own stack */
+ leaq boot_stack_end(%rbx), %rsp
+
+ /*
+ * cleanup_trampoline() would restore trampoline memory.
+ *
+ * RSI holds real mode data and needs to be preserved across
+ * this function call.
+ */
+ pushq %rsi
+ call cleanup_trampoline
+ popq %rsi
/* Zero EFLAGS */
pushq $0
@@ -490,46 +513,82 @@ relocated:
jmp *%rax
.code32
-#ifdef CONFIG_X86_5LEVEL
-compatible_mode:
- /* Setup data and stack segments */
+/*
+ * This is the 32-bit trampoline that will be copied over to low memory.
+ *
+ * RDI contains the return address (might be above 4G).
+ * ECX contains the base address of the trampoline memory.
+ * Non zero RDX on return means we need to enable 5-level paging.
+ */
+ENTRY(trampoline_32bit_src)
+ /* Set up data and stack segments */
movl $__KERNEL_DS, %eax
movl %eax, %ds
movl %eax, %ss
+ /* Set up new stack */
+ leal TRAMPOLINE_32BIT_STACK_END(%ecx), %esp
+
/* Disable paging */
movl %cr0, %eax
btrl $X86_CR0_PG_BIT, %eax
movl %eax, %cr0
- /* Point CR3 to 5-level paging */
- leal lvl5_pgtable(%ebx), %eax
- movl %eax, %cr3
+ /* Check what paging mode we want to be in after the trampoline */
+ cmpl $0, %edx
+ jz 1f
- /* Enable PAE and LA57 mode */
+ /* We want 5-level paging: don't touch CR3 if it already points to 5-level page tables */
+ movl %cr4, %eax
+ testl $X86_CR4_LA57, %eax
+ jnz 3f
+ jmp 2f
+1:
+ /* We want 4-level paging: don't touch CR3 if it already points to 4-level page tables */
movl %cr4, %eax
- orl $(X86_CR4_PAE | X86_CR4_LA57), %eax
+ testl $X86_CR4_LA57, %eax
+ jz 3f
+2:
+ /* Point CR3 to the trampoline's new top level page table */
+ leal TRAMPOLINE_32BIT_PGTABLE_OFFSET(%ecx), %eax
+ movl %eax, %cr3
+3:
+ /* Enable PAE and LA57 (if required) paging modes */
+ movl $X86_CR4_PAE, %eax
+ cmpl $0, %edx
+ jz 1f
+ orl $X86_CR4_LA57, %eax
+1:
movl %eax, %cr4
- /* Calculate address we are running at */
- call 1f
-1: popl %edi
- subl $1b, %edi
+ /* Calculate address of paging_enabled() once we are executing in the trampoline */
+ leal paging_enabled - trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_OFFSET(%ecx), %eax
- /* Prepare stack for far return to Long Mode */
+ /* Prepare the stack for far return to Long Mode */
pushl $__KERNEL_CS
- leal lvl5(%edi), %eax
- push %eax
+ pushl %eax
- /* Enable paging back */
+ /* Enable paging again */
movl $(X86_CR0_PG | X86_CR0_PE), %eax
movl %eax, %cr0
lret
-#endif
+ .code64
+paging_enabled:
+ /* Return from the trampoline */
+ jmp *%rdi
+
+ /*
+ * The trampoline code has a size limit.
+ * Make sure we fail to compile if the trampoline code grows
+ * beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.
+ */
+ .org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE
+
+ .code32
no_longmode:
- /* This isn't an x86-64 CPU so hang */
+ /* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */
1:
hlt
jmp 1b
@@ -537,6 +596,11 @@ no_longmode:
#include "../../kernel/verify_cpu.S"
.data
+gdt64:
+ .word gdt_end - gdt
+ .long 0
+ .word 0
+ .quad 0
gdt:
.word gdt_end - gdt
.long gdt
@@ -585,7 +649,3 @@ boot_stack_end:
.balign 4096
pgtable:
.fill BOOT_PGT_SIZE, 1, 0
-#ifdef CONFIG_X86_5LEVEL
-lvl5_pgtable:
- .fill PAGE_SIZE, 1, 0
-#endif
diff --git a/arch/x86/boot/compressed/kaslr.c b/arch/x86/boot/compressed/kaslr.c
index 8199a6187251..66e42a098d70 100644
--- a/arch/x86/boot/compressed/kaslr.c
+++ b/arch/x86/boot/compressed/kaslr.c
@@ -46,6 +46,12 @@
#define STATIC
#include <linux/decompress/mm.h>
+#ifdef CONFIG_X86_5LEVEL
+unsigned int pgtable_l5_enabled __ro_after_init;
+unsigned int pgdir_shift __ro_after_init = 39;
+unsigned int ptrs_per_p4d __ro_after_init = 1;
+#endif
+
extern unsigned long get_cmd_line_ptr(void);
/* Simplified build-specific string for starting entropy. */
@@ -723,6 +729,14 @@ void choose_random_location(unsigned long input,
return;
}
+#ifdef CONFIG_X86_5LEVEL
+ if (__read_cr4() & X86_CR4_LA57) {
+ pgtable_l5_enabled = 1;
+ pgdir_shift = 48;
+ ptrs_per_p4d = 512;
+ }
+#endif
+
boot_params->hdr.loadflags |= KASLR_FLAG;
/* Prepare to add new identity pagetables on demand. */
diff --git a/arch/x86/boot/compressed/pagetable.c b/arch/x86/boot/compressed/kaslr_64.c
index b5e5e02f8cde..522d11431433 100644
--- a/arch/x86/boot/compressed/pagetable.c
+++ b/arch/x86/boot/compressed/kaslr_64.c
@@ -16,13 +16,6 @@
#define __pa(x) ((unsigned long)(x))
#define __va(x) ((void *)((unsigned long)(x)))
-/*
- * The pgtable.h and mm/ident_map.c includes make use of the SME related
- * information which is not used in the compressed image support. Un-define
- * the SME support to avoid any compile and link errors.
- */
-#undef CONFIG_AMD_MEM_ENCRYPT
-
/* No PAGE_TABLE_ISOLATION support needed either: */
#undef CONFIG_PAGE_TABLE_ISOLATION
@@ -85,13 +78,14 @@ static struct x86_mapping_info mapping_info;
/* Locates and clears a region for a new top level page table. */
void initialize_identity_maps(void)
{
- unsigned long sev_me_mask = get_sev_encryption_mask();
+ /* If running as an SEV guest, the encryption mask is required. */
+ set_sev_encryption_mask();
/* Init mapping_info with run-time function/buffer pointers. */
mapping_info.alloc_pgt_page = alloc_pgt_page;
mapping_info.context = &pgt_data;
- mapping_info.page_flag = __PAGE_KERNEL_LARGE_EXEC | sev_me_mask;
- mapping_info.kernpg_flag = _KERNPG_TABLE | sev_me_mask;
+ mapping_info.page_flag = __PAGE_KERNEL_LARGE_EXEC | sme_me_mask;
+ mapping_info.kernpg_flag = _KERNPG_TABLE;
/*
* It should be impossible for this not to already be true,
diff --git a/arch/x86/boot/compressed/mem_encrypt.S b/arch/x86/boot/compressed/mem_encrypt.S
index 54f5f6625a73..eaa843a52907 100644
--- a/arch/x86/boot/compressed/mem_encrypt.S
+++ b/arch/x86/boot/compressed/mem_encrypt.S
@@ -88,9 +88,7 @@ ENTRY(get_sev_encryption_bit)
ENDPROC(get_sev_encryption_bit)
.code64
-ENTRY(get_sev_encryption_mask)
- xor %rax, %rax
-
+ENTRY(set_sev_encryption_mask)
#ifdef CONFIG_AMD_MEM_ENCRYPT
push %rbp
push %rdx
@@ -101,9 +99,7 @@ ENTRY(get_sev_encryption_mask)
testl %eax, %eax
jz .Lno_sev_mask
- xor %rdx, %rdx
- bts %rax, %rdx /* Create the encryption mask */
- mov %rdx, %rax /* ... and return it */
+ bts %rax, sme_me_mask(%rip) /* Create the encryption mask */
.Lno_sev_mask:
movq %rbp, %rsp /* Restore original stack pointer */
@@ -112,9 +108,16 @@ ENTRY(get_sev_encryption_mask)
pop %rbp
#endif
+ xor %rax, %rax
ret
-ENDPROC(get_sev_encryption_mask)
+ENDPROC(set_sev_encryption_mask)
.data
enc_bit:
.int 0xffffffff
+
+#ifdef CONFIG_AMD_MEM_ENCRYPT
+ .balign 8
+GLOBAL(sme_me_mask)
+ .quad 0
+#endif
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 98761a1576ce..8dd1d5ccae58 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -14,6 +14,7 @@
#include "misc.h"
#include "error.h"
+#include "pgtable.h"
#include "../string.h"
#include "../voffset.h"
@@ -169,16 +170,6 @@ void __puthex(unsigned long value)
}
}
-static bool l5_supported(void)
-{
- /* Check if leaf 7 is supported. */
- if (native_cpuid_eax(0) < 7)
- return 0;
-
- /* Check if la57 is supported. */
- return native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31));
-}
-
#if CONFIG_X86_NEED_RELOCS
static void handle_relocations(void *output, unsigned long output_len,
unsigned long virt_addr)
@@ -309,6 +300,10 @@ static void parse_elf(void *output)
switch (phdr->p_type) {
case PT_LOAD:
+#ifdef CONFIG_X86_64
+ if ((phdr->p_align % 0x200000) != 0)
+ error("Alignment of LOAD segment isn't multiple of 2MB");
+#endif
#ifdef CONFIG_RELOCATABLE
dest = output;
dest += (phdr->p_paddr - LOAD_PHYSICAL_ADDR);
@@ -372,12 +367,6 @@ asmlinkage __visible void *extract_kernel(void *rmode, memptr heap,
console_init();
debug_putstr("early console in extract_kernel\n");
- if (IS_ENABLED(CONFIG_X86_5LEVEL) && !l5_supported()) {
- error("This linux kernel as configured requires 5-level paging\n"
- "This CPU does not support the required 'cr4.la57' feature\n"
- "Unable to boot - please use a kernel appropriate for your CPU\n");
- }
-
free_mem_ptr = heap; /* Heap */
free_mem_end_ptr = heap + BOOT_HEAP_SIZE;
@@ -388,6 +377,11 @@ asmlinkage __visible void *extract_kernel(void *rmode, memptr heap,
debug_putaddr(output_len);
debug_putaddr(kernel_total_size);
+#ifdef CONFIG_X86_64
+ /* Report address of 32-bit trampoline */
+ debug_putaddr(trampoline_32bit);
+#endif
+
/*
* The memory hole needed for the kernel is the larger of either
* the entire decompressed kernel plus relocation table, or the
diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h
index 9d323dc6b159..9e11be4cae19 100644
--- a/arch/x86/boot/compressed/misc.h
+++ b/arch/x86/boot/compressed/misc.h
@@ -12,6 +12,11 @@
#undef CONFIG_PARAVIRT_SPINLOCKS
#undef CONFIG_KASAN
+#ifdef CONFIG_X86_5LEVEL
+/* cpu_feature_enabled() cannot be used that early */
+#define pgtable_l5_enabled __pgtable_l5_enabled
+#endif
+
#include <linux/linkage.h>
#include <linux/screen_info.h>
#include <linux/elf.h>
@@ -109,6 +114,6 @@ static inline void console_init(void)
{ }
#endif
-unsigned long get_sev_encryption_mask(void);
+void set_sev_encryption_mask(void);
#endif
diff --git a/arch/x86/boot/compressed/pgtable.h b/arch/x86/boot/compressed/pgtable.h
new file mode 100644
index 000000000000..91f75638f6e6
--- /dev/null
+++ b/arch/x86/boot/compressed/pgtable.h
@@ -0,0 +1,20 @@
+#ifndef BOOT_COMPRESSED_PAGETABLE_H
+#define BOOT_COMPRESSED_PAGETABLE_H
+
+#define TRAMPOLINE_32BIT_SIZE (2 * PAGE_SIZE)
+
+#define TRAMPOLINE_32BIT_PGTABLE_OFFSET 0
+
+#define TRAMPOLINE_32BIT_CODE_OFFSET PAGE_SIZE
+#define TRAMPOLINE_32BIT_CODE_SIZE 0x60
+
+#define TRAMPOLINE_32BIT_STACK_END TRAMPOLINE_32BIT_SIZE
+
+#ifndef __ASSEMBLER__
+
+extern unsigned long *trampoline_32bit;
+
+extern void trampoline_32bit_src(void *return_ptr);
+
+#endif /* __ASSEMBLER__ */
+#endif /* BOOT_COMPRESSED_PAGETABLE_H */
diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index b4469a37e9a1..32af1cbcd903 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -1,4 +1,6 @@
#include <asm/processor.h>
+#include "pgtable.h"
+#include "../string.h"
/*
* __force_order is used by special_insns.h asm code to force instruction
@@ -9,20 +11,144 @@
*/
unsigned long __force_order;
-int l5_paging_required(void)
+#define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */
+#define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */
+
+struct paging_config {
+ unsigned long trampoline_start;
+ unsigned long l5_required;
+};
+
+/* Buffer to preserve trampoline memory */
+static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
+
+/*
+ * The page table is going to be used instead of page table in the trampoline
+ * memory.
+ *
+ * It must not be in BSS as BSS is cleared after cleanup_trampoline().
+ */
+static char top_pgtable[PAGE_SIZE] __aligned(PAGE_SIZE) __section(.data);
+
+/*
+ * Trampoline address will be printed by extract_kernel() for debugging
+ * purposes.
+ *
+ * Avoid putting the pointer into .bss as it will be cleared between
+ * paging_prepare() and extract_kernel().
+ */
+unsigned long *trampoline_32bit __section(.data);
+
+struct paging_config paging_prepare(void)
{
- /* Check if leaf 7 is supported. */
+ struct paging_config paging_config = {};
+ unsigned long bios_start, ebda_start;
+
+ /*
+ * Check if LA57 is desired and supported.
+ *
+ * There are two parts to the check:
+ * - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
+ * - if the machine supports 5-level paging:
+ * + CPUID leaf 7 is supported
+ * + the leaf has the feature bit set
+ *
+ * That's substitute for boot_cpu_has() in early boot code.
+ */
+ if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
+ native_cpuid_eax(0) >= 7 &&
+ (native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
+ paging_config.l5_required = 1;
+ }
+
+ /*
+ * Find a suitable spot for the trampoline.
+ * This code is based on reserve_bios_regions().
+ */
+
+ ebda_start = *(unsigned short *)0x40e << 4;
+ bios_start = *(unsigned short *)0x413 << 10;
- if (native_cpuid_eax(0) < 7)
- return 0;
+ if (bios_start < BIOS_START_MIN || bios_start > BIOS_START_MAX)
+ bios_start = BIOS_START_MAX;
+
+ if (ebda_start > BIOS_START_MIN && ebda_start < bios_start)
+ bios_start = ebda_start;
+
+ /* Place the trampoline just below the end of low memory, aligned to 4k */
+ paging_config.trampoline_start = bios_start - TRAMPOLINE_32BIT_SIZE;
+ paging_config.trampoline_start = round_down(paging_config.trampoline_start, PAGE_SIZE);
+
+ trampoline_32bit = (unsigned long *)paging_config.trampoline_start;
+
+ /* Preserve trampoline memory */
+ memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE);
+
+ /* Clear trampoline memory first */
+ memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE);
+
+ /* Copy trampoline code in place */
+ memcpy(trampoline_32bit + TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long),
+ &trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE);
+
+ /*
+ * The code below prepares page table in trampoline memory.
+ *
+ * The new page table will be used by trampoline code for switching
+ * from 4- to 5-level paging or vice versa.
+ *
+ * If switching is not required, the page table is unused: trampoline
+ * code wouldn't touch CR3.
+ */
+
+ /*
+ * We are not going to use the page table in trampoline memory if we
+ * are already in the desired paging mode.
+ */
+ if (paging_config.l5_required == !!(native_read_cr4() & X86_CR4_LA57))
+ goto out;
+
+ if (paging_config.l5_required) {
+ /*
+ * For 4- to 5-level paging transition, set up current CR3 as
+ * the first and the only entry in a new top-level page table.
+ */
+ trampoline_32bit[TRAMPOLINE_32BIT_PGTABLE_OFFSET] = __native_read_cr3() | _PAGE_TABLE_NOENC;
+ } else {
+ unsigned long src;
+
+ /*
+ * For 5- to 4-level paging transition, copy page table pointed
+ * by first entry in the current top-level page table as our
+ * new top-level page table.
+ *
+ * We cannot just point to the page table from trampoline as it
+ * may be above 4G.
+ */
+ src = *(unsigned long *)__native_read_cr3() & PAGE_MASK;
+ memcpy(trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long),
+ (void *)src, PAGE_SIZE);
+ }
+
+out:
+ return paging_config;
+}
+
+void cleanup_trampoline(void)
+{
+ void *trampoline_pgtable;
- /* Check if la57 is supported. */
- if (!(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
- return 0;
+ trampoline_pgtable = trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET;
- /* Check if 5-level paging has already been enabled. */
- if (native_read_cr4() & X86_CR4_LA57)
- return 0;
+ /*
+ * Move the top level page table out of trampoline memory,
+ * if it's there.
+ */
+ if ((void *)__native_read_cr3() == trampoline_pgtable) {
+ memcpy(top_pgtable, trampoline_pgtable, PAGE_SIZE);
+ native_write_cr3((unsigned long)top_pgtable);
+ }
- return 1;
+ /* Restore trampoline memory */
+ memcpy(trampoline_32bit, trampoline_save, TRAMPOLINE_32BIT_SIZE);
}
diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h
index be63330c5511..352e70cd33e8 100644
--- a/arch/x86/entry/calling.h
+++ b/arch/x86/entry/calling.h
@@ -114,7 +114,9 @@ For 32-bit we have the following conventions - kernel is built with
pushq %rsi /* pt_regs->si */
.endif
pushq \rdx /* pt_regs->dx */
+ xorl %edx, %edx /* nospec dx */
pushq %rcx /* pt_regs->cx */
+ xorl %ecx, %ecx /* nospec cx */
pushq \rax /* pt_regs->ax */
pushq %r8 /* pt_regs->r8 */
xorl %r8d, %r8d /* nospec r8 */
diff --git a/arch/x86/entry/common.c b/arch/x86/entry/common.c
index 74f6eee15179..fbf6a6c3fd2d 100644
--- a/arch/x86/entry/common.c
+++ b/arch/x86/entry/common.c
@@ -266,14 +266,13 @@ __visible inline void syscall_return_slowpath(struct pt_regs *regs)
}
#ifdef CONFIG_X86_64
-__visible void do_syscall_64(struct pt_regs *regs)
+__visible void do_syscall_64(unsigned long nr, struct pt_regs *regs)
{
- struct thread_info *ti = current_thread_info();
- unsigned long nr = regs->orig_ax;
+ struct thread_info *ti;
enter_from_user_mode();
local_irq_enable();
-
+ ti = current_thread_info();
if (READ_ONCE(ti->flags) & _TIF_WORK_SYSCALL_ENTRY)
nr = syscall_trace_enter(regs);
@@ -282,11 +281,10 @@ __visible void do_syscall_64(struct pt_regs *regs)
* table. The only functional difference is the x32 bit in
* regs->orig_ax, which changes the behavior of some syscalls.
*/
- if (likely((nr & __SYSCALL_MASK) < NR_syscalls)) {
- nr = array_index_nospec(nr & __SYSCALL_MASK, NR_syscalls);
- regs->ax = sys_call_table[nr](
- regs->di, regs->si, regs->dx,
- regs->r10, regs->r8, regs->r9);
+ nr &= __SYSCALL_MASK;
+ if (likely(nr < NR_syscalls)) {
+ nr = array_index_nospec(nr, NR_syscalls);
+ regs->ax = sys_call_table[nr](regs);
}
syscall_return_slowpath(regs);
@@ -321,6 +319,9 @@ static __always_inline void do_syscall_32_irqs_on(struct pt_regs *regs)
if (likely(nr < IA32_NR_syscalls)) {
nr = array_index_nospec(nr, IA32_NR_syscalls);
+#ifdef CONFIG_IA32_EMULATION
+ regs->ax = ia32_sys_call_table[nr](regs);
+#else
/*
* It's possible that a 32-bit syscall implementation
* takes a 64-bit parameter but nonetheless assumes that
@@ -331,6 +332,7 @@ static __always_inline void do_syscall_32_irqs_on(struct pt_regs *regs)
(unsigned int)regs->bx, (unsigned int)regs->cx,
(unsigned int)regs->dx, (unsigned int)regs->si,
(unsigned int)regs->di, (unsigned int)regs->bp);
+#endif /* CONFIG_IA32_EMULATION */
}
syscall_return_slowpath(regs);
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 805f52703ee3..6cfe38665f3c 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -233,7 +233,8 @@ GLOBAL(entry_SYSCALL_64_after_hwframe)
TRACE_IRQS_OFF
/* IRQs are off. */
- movq %rsp, %rdi
+ movq %rax, %rdi
+ movq %rsp, %rsi
call do_syscall_64 /* returns with IRQs disabled */
TRACE_IRQS_IRETQ /* we're about to change IF */
@@ -260,8 +261,13 @@ GLOBAL(entry_SYSCALL_64_after_hwframe)
* Change top bits to match most significant bit (47th or 56th bit
* depending on paging mode) in the address.
*/
+#ifdef CONFIG_X86_5LEVEL
+ ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
+ "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
+#else
shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
+#endif
/* If this changed %rcx, it was not canonical */
cmpq %rcx, %r11
@@ -1138,7 +1144,7 @@ apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \
#endif /* CONFIG_HYPERV */
idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
-idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
+idtentry int3 do_int3 has_error_code=0
idtentry stack_segment do_stack_segment has_error_code=1
#ifdef CONFIG_XEN
diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S
index e811dd9c5e99..9af927e59d49 100644
--- a/arch/x86/entry/entry_64_compat.S
+++ b/arch/x86/entry/entry_64_compat.S
@@ -220,8 +220,11 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe)
pushq %rax /* pt_regs->orig_ax */
pushq %rdi /* pt_regs->di */
pushq %rsi /* pt_regs->si */
+ xorl %esi, %esi /* nospec si */
pushq %rdx /* pt_regs->dx */
+ xorl %edx, %edx /* nospec dx */
pushq %rbp /* pt_regs->cx (stashed in bp) */
+ xorl %ecx, %ecx /* nospec cx */
pushq $-ENOSYS /* pt_regs->ax */
pushq $0 /* pt_regs->r8 = 0 */
xorl %r8d, %r8d /* nospec r8 */
@@ -363,12 +366,13 @@ ENTRY(entry_INT80_compat)
pushq 2*8(%rdi) /* regs->ip */
pushq 1*8(%rdi) /* regs->orig_ax */
- movq (%rdi), %rdi /* restore %rdi */
-
- pushq %rdi /* pt_regs->di */
+ pushq (%rdi) /* pt_regs->di */
pushq %rsi /* pt_regs->si */
+ xorl %esi, %esi /* nospec si */
pushq %rdx /* pt_regs->dx */
+ xorl %edx, %edx /* nospec dx */
pushq %rcx /* pt_regs->cx */
+ xorl %ecx, %ecx /* nospec cx */
pushq $-ENOSYS /* pt_regs->ax */
pushq $0 /* pt_regs->r8 = 0 */
xorl %r8d, %r8d /* nospec r8 */
@@ -406,15 +410,3 @@ ENTRY(entry_INT80_compat)
TRACE_IRQS_ON
jmp swapgs_restore_regs_and_return_to_usermode
END(entry_INT80_compat)
-
-ENTRY(stub32_clone)
- /*
- * The 32-bit clone ABI is: clone(..., int tls_val, int *child_tidptr).
- * The 64-bit clone ABI is: clone(..., int *child_tidptr, int tls_val).
- *
- * The native 64-bit kernel's sys_clone() implements the latter,
- * so we need to swap arguments here before calling it:
- */
- xchg %r8, %rcx
- jmp sys_clone
-ENDPROC(stub32_clone)
diff --git a/arch/x86/entry/syscall_32.c b/arch/x86/entry/syscall_32.c
index 95c294963612..aa3336a7cb15 100644
--- a/arch/x86/entry/syscall_32.c
+++ b/arch/x86/entry/syscall_32.c
@@ -7,14 +7,23 @@
#include <asm/asm-offsets.h>
#include <asm/syscall.h>
-#define __SYSCALL_I386(nr, sym, qual) extern asmlinkage long sym(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long) ;
+#ifdef CONFIG_IA32_EMULATION
+/* On X86_64, we use struct pt_regs * to pass parameters to syscalls */
+#define __SYSCALL_I386(nr, sym, qual) extern asmlinkage long sym(const struct pt_regs *);
+
+/* this is a lie, but it does not hurt as sys_ni_syscall just returns -EINVAL */
+extern asmlinkage long sys_ni_syscall(const struct pt_regs *);
+
+#else /* CONFIG_IA32_EMULATION */
+#define __SYSCALL_I386(nr, sym, qual) extern asmlinkage long sym(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
+extern asmlinkage long sys_ni_syscall(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
+#endif /* CONFIG_IA32_EMULATION */
+
#include <asm/syscalls_32.h>
#undef __SYSCALL_I386
#define __SYSCALL_I386(nr, sym, qual) [nr] = sym,
-extern asmlinkage long sys_ni_syscall(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
-
__visible const sys_call_ptr_t ia32_sys_call_table[__NR_syscall_compat_max+1] = {
/*
* Smells like a compiler bug -- it doesn't work
diff --git a/arch/x86/entry/syscall_64.c b/arch/x86/entry/syscall_64.c
index c176d2fab1da..d5252bc1e380 100644
--- a/arch/x86/entry/syscall_64.c
+++ b/arch/x86/entry/syscall_64.c
@@ -7,14 +7,14 @@
#include <asm/asm-offsets.h>
#include <asm/syscall.h>
-#define __SYSCALL_64(nr, sym, qual) extern asmlinkage long sym(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
+/* this is a lie, but it does not hurt as sys_ni_syscall just returns -EINVAL */
+extern asmlinkage long sys_ni_syscall(const struct pt_regs *);
+#define __SYSCALL_64(nr, sym, qual) extern asmlinkage long sym(const struct pt_regs *);
#include <asm/syscalls_64.h>
#undef __SYSCALL_64
#define __SYSCALL_64(nr, sym, qual) [nr] = sym,
-extern long sys_ni_syscall(unsigned long, unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
-
asmlinkage const sys_call_ptr_t sys_call_table[__NR_syscall_max+1] = {
/*
* Smells like a compiler bug -- it doesn't work
diff --git a/arch/x86/entry/syscalls/syscall_32.tbl b/arch/x86/entry/syscalls/syscall_32.tbl
index 448ac2161112..d6b27dab1b30 100644
--- a/arch/x86/entry/syscalls/syscall_32.tbl
+++ b/arch/x86/entry/syscalls/syscall_32.tbl
@@ -4,390 +4,395 @@
# The format is:
# <number> <abi> <name> <entry point> <compat entry point>
#
+# The __ia32_sys and __ia32_compat_sys stubs are created on-the-fly for
+# sys_*() system calls and compat_sys_*() compat system calls if
+# IA32_EMULATION is defined, and expect struct pt_regs *regs as their only
+# parameter.
+#
# The abi is always "i386" for this file.
#
-0 i386 restart_syscall sys_restart_syscall
-1 i386 exit sys_exit
-2 i386 fork sys_fork sys_fork
-3 i386 read sys_read
-4 i386 write sys_write
-5 i386 open sys_open compat_sys_open
-6 i386 close sys_close
-7 i386 waitpid sys_waitpid sys32_waitpid
-8 i386 creat sys_creat
-9 i386 link sys_link
-10 i386 unlink sys_unlink
-11 i386 execve sys_execve compat_sys_execve
-12 i386 chdir sys_chdir
-13 i386 time sys_time compat_sys_time
-14 i386 mknod sys_mknod
-15 i386 chmod sys_chmod
-16 i386 lchown sys_lchown16
+0 i386 restart_syscall sys_restart_syscall __ia32_sys_restart_syscall
+1 i386 exit sys_exit __ia32_sys_exit
+2 i386 fork sys_fork __ia32_sys_fork
+3 i386 read sys_read __ia32_sys_read
+4 i386 write sys_write __ia32_sys_write
+5 i386 open sys_open __ia32_compat_sys_open
+6 i386 close sys_close __ia32_sys_close
+7 i386 waitpid sys_waitpid __ia32_sys_waitpid
+8 i386 creat sys_creat __ia32_sys_creat
+9 i386 link sys_link __ia32_sys_link
+10 i386 unlink sys_unlink __ia32_sys_unlink
+11 i386 execve sys_execve __ia32_compat_sys_execve
+12 i386 chdir sys_chdir __ia32_sys_chdir
+13 i386 time sys_time __ia32_compat_sys_time
+14 i386 mknod sys_mknod __ia32_sys_mknod
+15 i386 chmod sys_chmod __ia32_sys_chmod
+16 i386 lchown sys_lchown16 __ia32_sys_lchown16
17 i386 break
-18 i386 oldstat sys_stat
-19 i386 lseek sys_lseek compat_sys_lseek
-20 i386 getpid sys_getpid
-21 i386 mount sys_mount compat_sys_mount
-22 i386 umount sys_oldumount
-23 i386 setuid sys_setuid16
-24 i386 getuid sys_getuid16
-25 i386 stime sys_stime compat_sys_stime
-26 i386 ptrace sys_ptrace compat_sys_ptrace
-27 i386 alarm sys_alarm
-28 i386 oldfstat sys_fstat
-29 i386 pause sys_pause
-30 i386 utime sys_utime compat_sys_utime
+18 i386 oldstat sys_stat __ia32_sys_stat
+19 i386 lseek sys_lseek __ia32_compat_sys_lseek
+20 i386 getpid sys_getpid __ia32_sys_getpid
+21 i386 mount sys_mount __ia32_compat_sys_mount
+22 i386 umount sys_oldumount __ia32_sys_oldumount
+23 i386 setuid sys_setuid16 __ia32_sys_setuid16
+24 i386 getuid sys_getuid16 __ia32_sys_getuid16
+25 i386 stime sys_stime __ia32_compat_sys_stime
+26 i386 ptrace sys_ptrace __ia32_compat_sys_ptrace
+27 i386 alarm sys_alarm __ia32_sys_alarm
+28 i386 oldfstat sys_fstat __ia32_sys_fstat
+29 i386 pause sys_pause __ia32_sys_pause
+30 i386 utime sys_utime __ia32_compat_sys_utime
31 i386 stty
32 i386 gtty
-33 i386 access sys_access
-34 i386 nice sys_nice
+33 i386 access sys_access __ia32_sys_access
+34 i386 nice sys_nice __ia32_sys_nice
35 i386 ftime
-36 i386 sync sys_sync
-37 i386 kill sys_kill
-38 i386 rename sys_rename
-39 i386 mkdir sys_mkdir
-40 i386 rmdir sys_rmdir
-41 i386 dup sys_dup
-42 i386 pipe sys_pipe
-43 i386 times sys_times compat_sys_times
+36 i386 sync sys_sync __ia32_sys_sync
+37 i386 kill sys_kill __ia32_sys_kill
+38 i386 rename sys_rename __ia32_sys_rename
+39 i386 mkdir sys_mkdir __ia32_sys_mkdir
+40 i386 rmdir sys_rmdir __ia32_sys_rmdir
+41 i386 dup sys_dup __ia32_sys_dup
+42 i386 pipe sys_pipe __ia32_sys_pipe
+43 i386 times sys_times __ia32_compat_sys_times
44 i386 prof
-45 i386 brk sys_brk
-46 i386 setgid sys_setgid16
-47 i386 getgid sys_getgid16
-48 i386 signal sys_signal
-49 i386 geteuid sys_geteuid16
-50 i386 getegid sys_getegid16
-51 i386 acct sys_acct
-52 i386 umount2 sys_umount
+45 i386 brk sys_brk __ia32_sys_brk
+46 i386 setgid sys_setgid16 __ia32_sys_setgid16
+47 i386 getgid sys_getgid16 __ia32_sys_getgid16
+48 i386 signal sys_signal __ia32_sys_signal
+49 i386 geteuid sys_geteuid16 __ia32_sys_geteuid16
+50 i386 getegid sys_getegid16 __ia32_sys_getegid16
+51 i386 acct sys_acct __ia32_sys_acct
+52 i386 umount2 sys_umount __ia32_sys_umount
53 i386 lock
-54 i386 ioctl sys_ioctl compat_sys_ioctl
-55 i386 fcntl sys_fcntl compat_sys_fcntl64
+54 i386 ioctl sys_ioctl __ia32_compat_sys_ioctl
+55 i386 fcntl sys_fcntl __ia32_compat_sys_fcntl64
56 i386 mpx
-57 i386 setpgid sys_setpgid
+57 i386 setpgid sys_setpgid __ia32_sys_setpgid
58 i386 ulimit
-59 i386 oldolduname sys_olduname
-60 i386 umask sys_umask
-61 i386 chroot sys_chroot
-62 i386 ustat sys_ustat compat_sys_ustat
-63 i386 dup2 sys_dup2
-64 i386 getppid sys_getppid
-65 i386 getpgrp sys_getpgrp
-66 i386 setsid sys_setsid
-67 i386 sigaction sys_sigaction compat_sys_sigaction
-68 i386 sgetmask sys_sgetmask
-69 i386 ssetmask sys_ssetmask
-70 i386 setreuid sys_setreuid16
-71 i386 setregid sys_setregid16
-72 i386 sigsuspend sys_sigsuspend sys_sigsuspend
-73 i386 sigpending sys_sigpending compat_sys_sigpending
-74 i386 sethostname sys_sethostname
-75 i386 setrlimit sys_setrlimit compat_sys_setrlimit
-76 i386 getrlimit sys_old_getrlimit compat_sys_old_getrlimit
-77 i386 getrusage sys_getrusage compat_sys_getrusage
-78 i386 gettimeofday sys_gettimeofday compat_sys_gettimeofday
-79 i386 settimeofday sys_settimeofday compat_sys_settimeofday
-80 i386 getgroups sys_getgroups16
-81 i386 setgroups sys_setgroups16
-82 i386 select sys_old_select compat_sys_old_select
-83 i386 symlink sys_symlink
-84 i386 oldlstat sys_lstat
-85 i386 readlink sys_readlink
-86 i386 uselib sys_uselib
-87 i386 swapon sys_swapon
-88 i386 reboot sys_reboot
-89 i386 readdir sys_old_readdir compat_sys_old_readdir
-90 i386 mmap sys_old_mmap sys32_mmap
-91 i386 munmap sys_munmap
-92 i386 truncate sys_truncate compat_sys_truncate
-93 i386 ftruncate sys_ftruncate compat_sys_ftruncate
-94 i386 fchmod sys_fchmod
-95 i386 fchown sys_fchown16
-96 i386 getpriority sys_getpriority
-97 i386 setpriority sys_setpriority
+59 i386 oldolduname sys_olduname __ia32_sys_olduname
+60 i386 umask sys_umask __ia32_sys_umask
+61 i386 chroot sys_chroot __ia32_sys_chroot
+62 i386 ustat sys_ustat __ia32_compat_sys_ustat
+63 i386 dup2 sys_dup2 __ia32_sys_dup2
+64 i386 getppid sys_getppid __ia32_sys_getppid
+65 i386 getpgrp sys_getpgrp __ia32_sys_getpgrp
+66 i386 setsid sys_setsid __ia32_sys_setsid
+67 i386 sigaction sys_sigaction __ia32_compat_sys_sigaction
+68 i386 sgetmask sys_sgetmask __ia32_sys_sgetmask
+69 i386 ssetmask sys_ssetmask __ia32_sys_ssetmask
+70 i386 setreuid sys_setreuid16 __ia32_sys_setreuid16
+71 i386 setregid sys_setregid16 __ia32_sys_setregid16
+72 i386 sigsuspend sys_sigsuspend __ia32_sys_sigsuspend
+73 i386 sigpending sys_sigpending __ia32_compat_sys_sigpending
+74 i386 sethostname sys_sethostname __ia32_sys_sethostname
+75 i386 setrlimit sys_setrlimit __ia32_compat_sys_setrlimit
+76 i386 getrlimit sys_old_getrlimit __ia32_compat_sys_old_getrlimit
+77 i386 getrusage sys_getrusage __ia32_compat_sys_getrusage
+78 i386 gettimeofday sys_gettimeofday __ia32_compat_sys_gettimeofday
+79 i386 settimeofday sys_settimeofday __ia32_compat_sys_settimeofday
+80 i386 getgroups sys_getgroups16 __ia32_sys_getgroups16
+81 i386 setgroups sys_setgroups16 __ia32_sys_setgroups16
+82 i386 select sys_old_select __ia32_compat_sys_old_select
+83 i386 symlink sys_symlink __ia32_sys_symlink
+84 i386 oldlstat sys_lstat __ia32_sys_lstat
+85 i386 readlink sys_readlink __ia32_sys_readlink
+86 i386 uselib sys_uselib __ia32_sys_uselib
+87 i386 swapon sys_swapon __ia32_sys_swapon
+88 i386 reboot sys_reboot __ia32_sys_reboot
+89 i386 readdir sys_old_readdir __ia32_compat_sys_old_readdir
+90 i386 mmap sys_old_mmap __ia32_compat_sys_x86_mmap
+91 i386 munmap sys_munmap __ia32_sys_munmap
+92 i386 truncate sys_truncate __ia32_compat_sys_truncate
+93 i386 ftruncate sys_ftruncate __ia32_compat_sys_ftruncate
+94 i386 fchmod sys_fchmod __ia32_sys_fchmod
+95 i386 fchown sys_fchown16 __ia32_sys_fchown16
+96 i386 getpriority sys_getpriority __ia32_sys_getpriority
+97 i386 setpriority sys_setpriority __ia32_sys_setpriority
98 i386 profil
-99 i386 statfs sys_statfs compat_sys_statfs
-100 i386 fstatfs sys_fstatfs compat_sys_fstatfs
-101 i386 ioperm sys_ioperm
-102 i386 socketcall sys_socketcall compat_sys_socketcall
-103 i386 syslog sys_syslog
-104 i386 setitimer sys_setitimer compat_sys_setitimer
-105 i386 getitimer sys_getitimer compat_sys_getitimer
-106 i386 stat sys_newstat compat_sys_newstat
-107 i386 lstat sys_newlstat compat_sys_newlstat
-108 i386 fstat sys_newfstat compat_sys_newfstat
-109 i386 olduname sys_uname
-110 i386 iopl sys_iopl
-111 i386 vhangup sys_vhangup
+99 i386 statfs sys_statfs __ia32_compat_sys_statfs
+100 i386 fstatfs sys_fstatfs __ia32_compat_sys_fstatfs
+101 i386 ioperm sys_ioperm __ia32_sys_ioperm
+102 i386 socketcall sys_socketcall __ia32_compat_sys_socketcall
+103 i386 syslog sys_syslog __ia32_sys_syslog
+104 i386 setitimer sys_setitimer __ia32_compat_sys_setitimer
+105 i386 getitimer sys_getitimer __ia32_compat_sys_getitimer
+106 i386 stat sys_newstat __ia32_compat_sys_newstat
+107 i386 lstat sys_newlstat __ia32_compat_sys_newlstat
+108 i386 fstat sys_newfstat __ia32_compat_sys_newfstat
+109 i386 olduname sys_uname __ia32_sys_uname
+110 i386 iopl sys_iopl __ia32_sys_iopl
+111 i386 vhangup sys_vhangup __ia32_sys_vhangup
112 i386 idle
113 i386 vm86old sys_vm86old sys_ni_syscall
-114 i386 wait4 sys_wait4 compat_sys_wait4
-115 i386 swapoff sys_swapoff
-116 i386 sysinfo sys_sysinfo compat_sys_sysinfo
-117 i386 ipc sys_ipc compat_sys_ipc
-118 i386 fsync sys_fsync
+114 i386 wait4 sys_wait4 __ia32_compat_sys_wait4
+115 i386 swapoff sys_swapoff __ia32_sys_swapoff
+116 i386 sysinfo sys_sysinfo __ia32_compat_sys_sysinfo
+117 i386 ipc sys_ipc __ia32_compat_sys_ipc
+118 i386 fsync sys_fsync __ia32_sys_fsync
119 i386 sigreturn sys_sigreturn sys32_sigreturn
-120 i386 clone sys_clone stub32_clone
-121 i386 setdomainname sys_setdomainname
-122 i386 uname sys_newuname
-123 i386 modify_ldt sys_modify_ldt
-124 i386 adjtimex sys_adjtimex compat_sys_adjtimex
-125 i386 mprotect sys_mprotect
-126 i386 sigprocmask sys_sigprocmask compat_sys_sigprocmask
+120 i386 clone sys_clone __ia32_compat_sys_x86_clone
+121 i386 setdomainname sys_setdomainname __ia32_sys_setdomainname
+122 i386 uname sys_newuname __ia32_sys_newuname
+123 i386 modify_ldt sys_modify_ldt __ia32_sys_modify_ldt
+124 i386 adjtimex sys_adjtimex __ia32_compat_sys_adjtimex
+125 i386 mprotect sys_mprotect __ia32_sys_mprotect
+126 i386 sigprocmask sys_sigprocmask __ia32_compat_sys_sigprocmask
127 i386 create_module
-128 i386 init_module sys_init_module
-129 i386 delete_module sys_delete_module
+128 i386 init_module sys_init_module __ia32_sys_init_module
+129 i386 delete_module sys_delete_module __ia32_sys_delete_module
130 i386 get_kernel_syms
-131 i386 quotactl sys_quotactl sys32_quotactl
-132 i386 getpgid sys_getpgid
-133 i386 fchdir sys_fchdir
-134 i386 bdflush sys_bdflush
-135 i386 sysfs sys_sysfs
-136 i386 personality sys_personality
+131 i386 quotactl sys_quotactl __ia32_compat_sys_quotactl32
+132 i386 getpgid sys_getpgid __ia32_sys_getpgid
+133 i386 fchdir sys_fchdir __ia32_sys_fchdir
+134 i386 bdflush sys_bdflush __ia32_sys_bdflush
+135 i386 sysfs sys_sysfs __ia32_sys_sysfs
+136 i386 personality sys_personality __ia32_sys_personality
137 i386 afs_syscall
-138 i386 setfsuid sys_setfsuid16
-139 i386 setfsgid sys_setfsgid16
-140 i386 _llseek sys_llseek
-141 i386 getdents sys_getdents compat_sys_getdents
-142 i386 _newselect sys_select compat_sys_select
-143 i386 flock sys_flock
-144 i386 msync sys_msync
-145 i386 readv sys_readv compat_sys_readv
-146 i386 writev sys_writev compat_sys_writev
-147 i386 getsid sys_getsid
-148 i386 fdatasync sys_fdatasync
-149 i386 _sysctl sys_sysctl compat_sys_sysctl
-150 i386 mlock sys_mlock
-151 i386 munlock sys_munlock
-152 i386 mlockall sys_mlockall
-153 i386 munlockall sys_munlockall
-154 i386 sched_setparam sys_sched_setparam
-155 i386 sched_getparam sys_sched_getparam
-156 i386 sched_setscheduler sys_sched_setscheduler
-157 i386 sched_getscheduler sys_sched_getscheduler
-158 i386 sched_yield sys_sched_yield
-159 i386 sched_get_priority_max sys_sched_get_priority_max
-160 i386 sched_get_priority_min sys_sched_get_priority_min
-161 i386 sched_rr_get_interval sys_sched_rr_get_interval compat_sys_sched_rr_get_interval
-162 i386 nanosleep sys_nanosleep compat_sys_nanosleep
-163 i386 mremap sys_mremap
-164 i386 setresuid sys_setresuid16
-165 i386 getresuid sys_getresuid16
+138 i386 setfsuid sys_setfsuid16 __ia32_sys_setfsuid16
+139 i386 setfsgid sys_setfsgid16 __ia32_sys_setfsgid16
+140 i386 _llseek sys_llseek __ia32_sys_llseek
+141 i386 getdents sys_getdents __ia32_compat_sys_getdents
+142 i386 _newselect sys_select __ia32_compat_sys_select
+143 i386 flock sys_flock __ia32_sys_flock
+144 i386 msync sys_msync __ia32_sys_msync
+145 i386 readv sys_readv __ia32_compat_sys_readv
+146 i386 writev sys_writev __ia32_compat_sys_writev
+147 i386 getsid sys_getsid __ia32_sys_getsid
+148 i386 fdatasync sys_fdatasync __ia32_sys_fdatasync
+149 i386 _sysctl sys_sysctl __ia32_compat_sys_sysctl
+150 i386 mlock sys_mlock __ia32_sys_mlock
+151 i386 munlock sys_munlock __ia32_sys_munlock
+152 i386 mlockall sys_mlockall __ia32_sys_mlockall
+153 i386 munlockall sys_munlockall __ia32_sys_munlockall
+154 i386 sched_setparam sys_sched_setparam __ia32_sys_sched_setparam
+155 i386 sched_getparam sys_sched_getparam __ia32_sys_sched_getparam
+156 i386 sched_setscheduler sys_sched_setscheduler __ia32_sys_sched_setscheduler
+157 i386 sched_getscheduler sys_sched_getscheduler __ia32_sys_sched_getscheduler
+158 i386 sched_yield sys_sched_yield __ia32_sys_sched_yield
+159 i386 sched_get_priority_max sys_sched_get_priority_max __ia32_sys_sched_get_priority_max
+160 i386 sched_get_priority_min sys_sched_get_priority_min __ia32_sys_sched_get_priority_min
+161 i386 sched_rr_get_interval sys_sched_rr_get_interval __ia32_compat_sys_sched_rr_get_interval
+162 i386 nanosleep sys_nanosleep __ia32_compat_sys_nanosleep
+163 i386 mremap sys_mremap __ia32_sys_mremap
+164 i386 setresuid sys_setresuid16 __ia32_sys_setresuid16
+165 i386 getresuid sys_getresuid16 __ia32_sys_getresuid16
166 i386 vm86 sys_vm86 sys_ni_syscall
167 i386 query_module
-168 i386 poll sys_poll
+168 i386 poll sys_poll __ia32_sys_poll
169 i386 nfsservctl
-170 i386 setresgid sys_setresgid16
-171 i386 getresgid sys_getresgid16
-172 i386 prctl sys_prctl
+170 i386 setresgid sys_setresgid16 __ia32_sys_setresgid16
+171 i386 getresgid sys_getresgid16 __ia32_sys_getresgid16
+172 i386 prctl sys_prctl __ia32_sys_prctl
173 i386 rt_sigreturn sys_rt_sigreturn sys32_rt_sigreturn
-174 i386 rt_sigaction sys_rt_sigaction compat_sys_rt_sigaction
-175 i386 rt_sigprocmask sys_rt_sigprocmask
-176 i386 rt_sigpending sys_rt_sigpending compat_sys_rt_sigpending
-177 i386 rt_sigtimedwait sys_rt_sigtimedwait compat_sys_rt_sigtimedwait
-178 i386 rt_sigqueueinfo sys_rt_sigqueueinfo compat_sys_rt_sigqueueinfo
-179 i386 rt_sigsuspend sys_rt_sigsuspend
-180 i386 pread64 sys_pread64 sys32_pread
-181 i386 pwrite64 sys_pwrite64 sys32_pwrite
-182 i386 chown sys_chown16
-183 i386 getcwd sys_getcwd
-184 i386 capget sys_capget
-185 i386 capset sys_capset
-186 i386 sigaltstack sys_sigaltstack compat_sys_sigaltstack
-187 i386 sendfile sys_sendfile compat_sys_sendfile
+174 i386 rt_sigaction sys_rt_sigaction __ia32_compat_sys_rt_sigaction
+175 i386 rt_sigprocmask sys_rt_sigprocmask __ia32_sys_rt_sigprocmask
+176 i386 rt_sigpending sys_rt_sigpending __ia32_compat_sys_rt_sigpending
+177 i386 rt_sigtimedwait sys_rt_sigtimedwait __ia32_compat_sys_rt_sigtimedwait
+178 i386 rt_sigqueueinfo sys_rt_sigqueueinfo __ia32_compat_sys_rt_sigqueueinfo
+179 i386 rt_sigsuspend sys_rt_sigsuspend __ia32_sys_rt_sigsuspend
+180 i386 pread64 sys_pread64 __ia32_compat_sys_x86_pread
+181 i386 pwrite64 sys_pwrite64 __ia32_compat_sys_x86_pwrite
+182 i386 chown sys_chown16 __ia32_sys_chown16
+183 i386 getcwd sys_getcwd __ia32_sys_getcwd
+184 i386 capget sys_capget __ia32_sys_capget
+185 i386 capset sys_capset __ia32_sys_capset
+186 i386 sigaltstack sys_sigaltstack __ia32_compat_sys_sigaltstack
+187 i386 sendfile sys_sendfile __ia32_compat_sys_sendfile
188 i386 getpmsg
189 i386 putpmsg
-190 i386 vfork sys_vfork sys_vfork
-191 i386 ugetrlimit sys_getrlimit compat_sys_getrlimit
-192 i386 mmap2 sys_mmap_pgoff
-193 i386 truncate64 sys_truncate64 sys32_truncate64
-194 i386 ftruncate64 sys_ftruncate64 sys32_ftruncate64
-195 i386 stat64 sys_stat64 sys32_stat64
-196 i386 lstat64 sys_lstat64 sys32_lstat64
-197 i386 fstat64 sys_fstat64 sys32_fstat64
-198 i386 lchown32 sys_lchown
-199 i386 getuid32 sys_getuid
-200 i386 getgid32 sys_getgid
-201 i386 geteuid32 sys_geteuid
-202 i386 getegid32 sys_getegid
-203 i386 setreuid32 sys_setreuid
-204 i386 setregid32 sys_setregid
-205 i386 getgroups32 sys_getgroups
-206 i386 setgroups32 sys_setgroups
-207 i386 fchown32 sys_fchown
-208 i386 setresuid32 sys_setresuid
-209 i386 getresuid32 sys_getresuid
-210 i386 setresgid32 sys_setresgid
-211 i386 getresgid32 sys_getresgid
-212 i386 chown32 sys_chown
-213 i386 setuid32 sys_setuid
-214 i386 setgid32 sys_setgid
-215 i386 setfsuid32 sys_setfsuid
-216 i386 setfsgid32 sys_setfsgid
-217 i386 pivot_root sys_pivot_root
-218 i386 mincore sys_mincore
-219 i386 madvise sys_madvise
-220 i386 getdents64 sys_getdents64
-221 i386 fcntl64 sys_fcntl64 compat_sys_fcntl64
+190 i386 vfork sys_vfork __ia32_sys_vfork
+191 i386 ugetrlimit sys_getrlimit __ia32_compat_sys_getrlimit
+192 i386 mmap2 sys_mmap_pgoff __ia32_sys_mmap_pgoff
+193 i386 truncate64 sys_truncate64 __ia32_compat_sys_x86_truncate64
+194 i386 ftruncate64 sys_ftruncate64 __ia32_compat_sys_x86_ftruncate64
+195 i386 stat64 sys_stat64 __ia32_compat_sys_x86_stat64
+196 i386 lstat64 sys_lstat64 __ia32_compat_sys_x86_lstat64
+197 i386 fstat64 sys_fstat64 __ia32_compat_sys_x86_fstat64
+198 i386 lchown32 sys_lchown __ia32_sys_lchown
+199 i386 getuid32 sys_getuid __ia32_sys_getuid
+200 i386 getgid32 sys_getgid __ia32_sys_getgid
+201 i386 geteuid32 sys_geteuid __ia32_sys_geteuid
+202 i386 getegid32 sys_getegid __ia32_sys_getegid
+203 i386 setreuid32 sys_setreuid __ia32_sys_setreuid
+204 i386 setregid32 sys_setregid __ia32_sys_setregid
+205 i386 getgroups32 sys_getgroups __ia32_sys_getgroups
+206 i386 setgroups32 sys_setgroups __ia32_sys_setgroups
+207 i386 fchown32 sys_fchown __ia32_sys_fchown
+208 i386 setresuid32 sys_setresuid __ia32_sys_setresuid
+209 i386 getresuid32 sys_getresuid __ia32_sys_getresuid
+210 i386 setresgid32 sys_setresgid __ia32_sys_setresgid
+211 i386 getresgid32 sys_getresgid __ia32_sys_getresgid
+212 i386 chown32 sys_chown __ia32_sys_chown
+213 i386 setuid32 sys_setuid __ia32_sys_setuid
+214 i386 setgid32 sys_setgid __ia32_sys_setgid
+215 i386 setfsuid32 sys_setfsuid __ia32_sys_setfsuid
+216 i386 setfsgid32 sys_setfsgid __ia32_sys_setfsgid
+217 i386 pivot_root sys_pivot_root __ia32_sys_pivot_root
+218 i386 mincore sys_mincore __ia32_sys_mincore
+219 i386 madvise sys_madvise __ia32_sys_madvise
+220 i386 getdents64 sys_getdents64 __ia32_sys_getdents64
+221 i386 fcntl64 sys_fcntl64 __ia32_compat_sys_fcntl64
# 222 is unused
# 223 is unused
-224 i386 gettid sys_gettid
-225 i386 readahead sys_readahead sys32_readahead
-226 i386 setxattr sys_setxattr
-227 i386 lsetxattr sys_lsetxattr
-228 i386 fsetxattr sys_fsetxattr
-229 i386 getxattr sys_getxattr
-230 i386 lgetxattr sys_lgetxattr
-231 i386 fgetxattr sys_fgetxattr
-232 i386 listxattr sys_listxattr
-233 i386 llistxattr sys_llistxattr
-234 i386 flistxattr sys_flistxattr
-235 i386 removexattr sys_removexattr
-236 i386 lremovexattr sys_lremovexattr
-237 i386 fremovexattr sys_fremovexattr
-238 i386 tkill sys_tkill
-239 i386 sendfile64 sys_sendfile64
-240 i386 futex sys_futex compat_sys_futex
-241 i386 sched_setaffinity sys_sched_setaffinity compat_sys_sched_setaffinity
-242 i386 sched_getaffinity sys_sched_getaffinity compat_sys_sched_getaffinity
-243 i386 set_thread_area sys_set_thread_area
-244 i386 get_thread_area sys_get_thread_area
-245 i386 io_setup sys_io_setup compat_sys_io_setup
-246 i386 io_destroy sys_io_destroy
-247 i386 io_getevents sys_io_getevents compat_sys_io_getevents
-248 i386 io_submit sys_io_submit compat_sys_io_submit
-249 i386 io_cancel sys_io_cancel
-250 i386 fadvise64 sys_fadvise64 sys32_fadvise64
+224 i386 gettid sys_gettid __ia32_sys_gettid
+225 i386 readahead sys_readahead __ia32_compat_sys_x86_readahead
+226 i386 setxattr sys_setxattr __ia32_sys_setxattr
+227 i386 lsetxattr sys_lsetxattr __ia32_sys_lsetxattr
+228 i386 fsetxattr sys_fsetxattr __ia32_sys_fsetxattr
+229 i386 getxattr sys_getxattr __ia32_sys_getxattr
+230 i386 lgetxattr sys_lgetxattr __ia32_sys_lgetxattr
+231 i386 fgetxattr sys_fgetxattr __ia32_sys_fgetxattr
+232 i386 listxattr sys_listxattr __ia32_sys_listxattr
+233 i386 llistxattr sys_llistxattr __ia32_sys_llistxattr
+234 i386 flistxattr sys_flistxattr __ia32_sys_flistxattr
+235 i386 removexattr sys_removexattr __ia32_sys_removexattr
+236 i386 lremovexattr sys_lremovexattr __ia32_sys_lremovexattr
+237 i386 fremovexattr sys_fremovexattr __ia32_sys_fremovexattr
+238 i386 tkill sys_tkill __ia32_sys_tkill
+239 i386 sendfile64 sys_sendfile64 __ia32_sys_sendfile64
+240 i386 futex sys_futex __ia32_compat_sys_futex
+241 i386 sched_setaffinity sys_sched_setaffinity __ia32_compat_sys_sched_setaffinity
+242 i386 sched_getaffinity sys_sched_getaffinity __ia32_compat_sys_sched_getaffinity
+243 i386 set_thread_area sys_set_thread_area __ia32_sys_set_thread_area
+244 i386 get_thread_area sys_get_thread_area __ia32_sys_get_thread_area
+245 i386 io_setup sys_io_setup __ia32_compat_sys_io_setup
+246 i386 io_destroy sys_io_destroy __ia32_sys_io_destroy
+247 i386 io_getevents sys_io_getevents __ia32_compat_sys_io_getevents
+248 i386 io_submit sys_io_submit __ia32_compat_sys_io_submit
+249 i386 io_cancel sys_io_cancel __ia32_sys_io_cancel
+250 i386 fadvise64 sys_fadvise64 __ia32_compat_sys_x86_fadvise64
# 251 is available for reuse (was briefly sys_set_zone_reclaim)
-252 i386 exit_group sys_exit_group
-253 i386 lookup_dcookie sys_lookup_dcookie compat_sys_lookup_dcookie
-254 i386 epoll_create sys_epoll_create
-255 i386 epoll_ctl sys_epoll_ctl
-256 i386 epoll_wait sys_epoll_wait
-257 i386 remap_file_pages sys_remap_file_pages
-258 i386 set_tid_address sys_set_tid_address
-259 i386 timer_create sys_timer_create compat_sys_timer_create
-260 i386 timer_settime sys_timer_settime compat_sys_timer_settime
-261 i386 timer_gettime sys_timer_gettime compat_sys_timer_gettime
-262 i386 timer_getoverrun sys_timer_getoverrun
-263 i386 timer_delete sys_timer_delete
-264 i386 clock_settime sys_clock_settime compat_sys_clock_settime
-265 i386 clock_gettime sys_clock_gettime compat_sys_clock_gettime
-266 i386 clock_getres sys_clock_getres compat_sys_clock_getres
-267 i386 clock_nanosleep sys_clock_nanosleep compat_sys_clock_nanosleep
-268 i386 statfs64 sys_statfs64 compat_sys_statfs64
-269 i386 fstatfs64 sys_fstatfs64 compat_sys_fstatfs64
-270 i386 tgkill sys_tgkill
-271 i386 utimes sys_utimes compat_sys_utimes
-272 i386 fadvise64_64 sys_fadvise64_64 sys32_fadvise64_64
+252 i386 exit_group sys_exit_group __ia32_sys_exit_group
+253 i386 lookup_dcookie sys_lookup_dcookie __ia32_compat_sys_lookup_dcookie
+254 i386 epoll_create sys_epoll_create __ia32_sys_epoll_create
+255 i386 epoll_ctl sys_epoll_ctl __ia32_sys_epoll_ctl
+256 i386 epoll_wait sys_epoll_wait __ia32_sys_epoll_wait
+257 i386 remap_file_pages sys_remap_file_pages __ia32_sys_remap_file_pages
+258 i386 set_tid_address sys_set_tid_address __ia32_sys_set_tid_address
+259 i386 timer_create sys_timer_create __ia32_compat_sys_timer_create
+260 i386 timer_settime sys_timer_settime __ia32_compat_sys_timer_settime
+261 i386 timer_gettime sys_timer_gettime __ia32_compat_sys_timer_gettime
+262 i386 timer_getoverrun sys_timer_getoverrun __ia32_sys_timer_getoverrun
+263 i386 timer_delete sys_timer_delete __ia32_sys_timer_delete
+264 i386 clock_settime sys_clock_settime __ia32_compat_sys_clock_settime
+265 i386 clock_gettime sys_clock_gettime __ia32_compat_sys_clock_gettime
+266 i386 clock_getres sys_clock_getres __ia32_compat_sys_clock_getres
+267 i386 clock_nanosleep sys_clock_nanosleep __ia32_compat_sys_clock_nanosleep
+268 i386 statfs64 sys_statfs64 __ia32_compat_sys_statfs64
+269 i386 fstatfs64 sys_fstatfs64 __ia32_compat_sys_fstatfs64
+270 i386 tgkill sys_tgkill __ia32_sys_tgkill
+271 i386 utimes sys_utimes __ia32_compat_sys_utimes
+272 i386 fadvise64_64 sys_fadvise64_64 __ia32_compat_sys_x86_fadvise64_64
273 i386 vserver
-274 i386 mbind sys_mbind
-275 i386 get_mempolicy sys_get_mempolicy compat_sys_get_mempolicy
-276 i386 set_mempolicy sys_set_mempolicy
-277 i386 mq_open sys_mq_open compat_sys_mq_open
-278 i386 mq_unlink sys_mq_unlink
-279 i386 mq_timedsend sys_mq_timedsend compat_sys_mq_timedsend
-280 i386 mq_timedreceive sys_mq_timedreceive compat_sys_mq_timedreceive
-281 i386 mq_notify sys_mq_notify compat_sys_mq_notify
-282 i386 mq_getsetattr sys_mq_getsetattr compat_sys_mq_getsetattr
-283 i386 kexec_load sys_kexec_load compat_sys_kexec_load
-284 i386 waitid sys_waitid compat_sys_waitid
+274 i386 mbind sys_mbind __ia32_sys_mbind
+275 i386 get_mempolicy sys_get_mempolicy __ia32_compat_sys_get_mempolicy
+276 i386 set_mempolicy sys_set_mempolicy __ia32_sys_set_mempolicy
+277 i386 mq_open sys_mq_open __ia32_compat_sys_mq_open
+278 i386 mq_unlink sys_mq_unlink __ia32_sys_mq_unlink
+279 i386 mq_timedsend sys_mq_timedsend __ia32_compat_sys_mq_timedsend
+280 i386 mq_timedreceive sys_mq_timedreceive __ia32_compat_sys_mq_timedreceive
+281 i386 mq_notify sys_mq_notify __ia32_compat_sys_mq_notify
+282 i386 mq_getsetattr sys_mq_getsetattr __ia32_compat_sys_mq_getsetattr
+283 i386 kexec_load sys_kexec_load __ia32_compat_sys_kexec_load
+284 i386 waitid sys_waitid __ia32_compat_sys_waitid
# 285 sys_setaltroot
-286 i386 add_key sys_add_key
-287 i386 request_key sys_request_key
-288 i386 keyctl sys_keyctl compat_sys_keyctl
-289 i386 ioprio_set sys_ioprio_set
-290 i386 ioprio_get sys_ioprio_get
-291 i386 inotify_init sys_inotify_init
-292 i386 inotify_add_watch sys_inotify_add_watch
-293 i386 inotify_rm_watch sys_inotify_rm_watch
-294 i386 migrate_pages sys_migrate_pages
-295 i386 openat sys_openat compat_sys_openat
-296 i386 mkdirat sys_mkdirat
-297 i386 mknodat sys_mknodat
-298 i386 fchownat sys_fchownat
-299 i386 futimesat sys_futimesat compat_sys_futimesat
-300 i386 fstatat64 sys_fstatat64 sys32_fstatat
-301 i386 unlinkat sys_unlinkat
-302 i386 renameat sys_renameat
-303 i386 linkat sys_linkat
-304 i386 symlinkat sys_symlinkat
-305 i386 readlinkat sys_readlinkat
-306 i386 fchmodat sys_fchmodat
-307 i386 faccessat sys_faccessat
-308 i386 pselect6 sys_pselect6 compat_sys_pselect6
-309 i386 ppoll sys_ppoll compat_sys_ppoll
-310 i386 unshare sys_unshare
-311 i386 set_robust_list sys_set_robust_list compat_sys_set_robust_list
-312 i386 get_robust_list sys_get_robust_list compat_sys_get_robust_list
-313 i386 splice sys_splice
-314 i386 sync_file_range sys_sync_file_range sys32_sync_file_range
-315 i386 tee sys_tee
-316 i386 vmsplice sys_vmsplice compat_sys_vmsplice
-317 i386 move_pages sys_move_pages compat_sys_move_pages
-318 i386 getcpu sys_getcpu
-319 i386 epoll_pwait sys_epoll_pwait
-320 i386 utimensat sys_utimensat compat_sys_utimensat
-321 i386 signalfd sys_signalfd compat_sys_signalfd
-322 i386 timerfd_create sys_timerfd_create
-323 i386 eventfd sys_eventfd
-324 i386 fallocate sys_fallocate sys32_fallocate
-325 i386 timerfd_settime sys_timerfd_settime compat_sys_timerfd_settime
-326 i386 timerfd_gettime sys_timerfd_gettime compat_sys_timerfd_gettime
-327 i386 signalfd4 sys_signalfd4 compat_sys_signalfd4
-328 i386 eventfd2 sys_eventfd2
-329 i386 epoll_create1 sys_epoll_create1
-330 i386 dup3 sys_dup3
-331 i386 pipe2 sys_pipe2
-332 i386 inotify_init1 sys_inotify_init1
-333 i386 preadv sys_preadv compat_sys_preadv
-334 i386 pwritev sys_pwritev compat_sys_pwritev
-335 i386 rt_tgsigqueueinfo sys_rt_tgsigqueueinfo compat_sys_rt_tgsigqueueinfo
-336 i386 perf_event_open sys_perf_event_open
-337 i386 recvmmsg sys_recvmmsg compat_sys_recvmmsg
-338 i386 fanotify_init sys_fanotify_init
-339 i386 fanotify_mark sys_fanotify_mark compat_sys_fanotify_mark
-340 i386 prlimit64 sys_prlimit64
-341 i386 name_to_handle_at sys_name_to_handle_at
-342 i386 open_by_handle_at sys_open_by_handle_at compat_sys_open_by_handle_at
-343 i386 clock_adjtime sys_clock_adjtime compat_sys_clock_adjtime
-344 i386 syncfs sys_syncfs
-345 i386 sendmmsg sys_sendmmsg compat_sys_sendmmsg
-346 i386 setns sys_setns
-347 i386 process_vm_readv sys_process_vm_readv compat_sys_process_vm_readv
-348 i386 process_vm_writev sys_process_vm_writev compat_sys_process_vm_writev
-349 i386 kcmp sys_kcmp
-350 i386 finit_module sys_finit_module
-351 i386 sched_setattr sys_sched_setattr
-352 i386 sched_getattr sys_sched_getattr
-353 i386 renameat2 sys_renameat2
-354 i386 seccomp sys_seccomp
-355 i386 getrandom sys_getrandom
-356 i386 memfd_create sys_memfd_create
-357 i386 bpf sys_bpf
-358 i386 execveat sys_execveat compat_sys_execveat
-359 i386 socket sys_socket
-360 i386 socketpair sys_socketpair
-361 i386 bind sys_bind
-362 i386 connect sys_connect
-363 i386 listen sys_listen
-364 i386 accept4 sys_accept4
-365 i386 getsockopt sys_getsockopt compat_sys_getsockopt
-366 i386 setsockopt sys_setsockopt compat_sys_setsockopt
-367 i386 getsockname sys_getsockname
-368 i386 getpeername sys_getpeername
-369 i386 sendto sys_sendto
-370 i386 sendmsg sys_sendmsg compat_sys_sendmsg
-371 i386 recvfrom sys_recvfrom compat_sys_recvfrom
-372 i386 recvmsg sys_recvmsg compat_sys_recvmsg
-373 i386 shutdown sys_shutdown
-374 i386 userfaultfd sys_userfaultfd
-375 i386 membarrier sys_membarrier
-376 i386 mlock2 sys_mlock2
-377 i386 copy_file_range sys_copy_file_range
-378 i386 preadv2 sys_preadv2 compat_sys_preadv2
-379 i386 pwritev2 sys_pwritev2 compat_sys_pwritev2
-380 i386 pkey_mprotect sys_pkey_mprotect
-381 i386 pkey_alloc sys_pkey_alloc
-382 i386 pkey_free sys_pkey_free
-383 i386 statx sys_statx
-384 i386 arch_prctl sys_arch_prctl compat_sys_arch_prctl
+286 i386 add_key sys_add_key __ia32_sys_add_key
+287 i386 request_key sys_request_key __ia32_sys_request_key
+288 i386 keyctl sys_keyctl __ia32_compat_sys_keyctl
+289 i386 ioprio_set sys_ioprio_set __ia32_sys_ioprio_set
+290 i386 ioprio_get sys_ioprio_get __ia32_sys_ioprio_get
+291 i386 inotify_init sys_inotify_init __ia32_sys_inotify_init
+292 i386 inotify_add_watch sys_inotify_add_watch __ia32_sys_inotify_add_watch
+293 i386 inotify_rm_watch sys_inotify_rm_watch __ia32_sys_inotify_rm_watch
+294 i386 migrate_pages sys_migrate_pages __ia32_sys_migrate_pages
+295 i386 openat sys_openat __ia32_compat_sys_openat
+296 i386 mkdirat sys_mkdirat __ia32_sys_mkdirat
+297 i386 mknodat sys_mknodat __ia32_sys_mknodat
+298 i386 fchownat sys_fchownat __ia32_sys_fchownat
+299 i386 futimesat sys_futimesat __ia32_compat_sys_futimesat
+300 i386 fstatat64 sys_fstatat64 __ia32_compat_sys_x86_fstatat
+301 i386 unlinkat sys_unlinkat __ia32_sys_unlinkat
+302 i386 renameat sys_renameat __ia32_sys_renameat
+303 i386 linkat sys_linkat __ia32_sys_linkat
+304 i386 symlinkat sys_symlinkat __ia32_sys_symlinkat
+305 i386 readlinkat sys_readlinkat __ia32_sys_readlinkat
+306 i386 fchmodat sys_fchmodat __ia32_sys_fchmodat
+307 i386 faccessat sys_faccessat __ia32_sys_faccessat
+308 i386 pselect6 sys_pselect6 __ia32_compat_sys_pselect6
+309 i386 ppoll sys_ppoll __ia32_compat_sys_ppoll
+310 i386 unshare sys_unshare __ia32_sys_unshare
+311 i386 set_robust_list sys_set_robust_list __ia32_compat_sys_set_robust_list
+312 i386 get_robust_list sys_get_robust_list __ia32_compat_sys_get_robust_list
+313 i386 splice sys_splice __ia32_sys_splice
+314 i386 sync_file_range sys_sync_file_range __ia32_compat_sys_x86_sync_file_range
+315 i386 tee sys_tee __ia32_sys_tee
+316 i386 vmsplice sys_vmsplice __ia32_compat_sys_vmsplice
+317 i386 move_pages sys_move_pages __ia32_compat_sys_move_pages
+318 i386 getcpu sys_getcpu __ia32_sys_getcpu
+319 i386 epoll_pwait sys_epoll_pwait __ia32_sys_epoll_pwait
+320 i386 utimensat sys_utimensat __ia32_compat_sys_utimensat
+321 i386 signalfd sys_signalfd __ia32_compat_sys_signalfd
+322 i386 timerfd_create sys_timerfd_create __ia32_sys_timerfd_create
+323 i386 eventfd sys_eventfd __ia32_sys_eventfd
+324 i386 fallocate sys_fallocate __ia32_compat_sys_x86_fallocate
+325 i386 timerfd_settime sys_timerfd_settime __ia32_compat_sys_timerfd_settime
+326 i386 timerfd_gettime sys_timerfd_gettime __ia32_compat_sys_timerfd_gettime
+327 i386 signalfd4 sys_signalfd4 __ia32_compat_sys_signalfd4
+328 i386 eventfd2 sys_eventfd2 __ia32_sys_eventfd2
+329 i386 epoll_create1 sys_epoll_create1 __ia32_sys_epoll_create1
+330 i386 dup3 sys_dup3 __ia32_sys_dup3
+331 i386 pipe2 sys_pipe2 __ia32_sys_pipe2
+332 i386 inotify_init1 sys_inotify_init1 __ia32_sys_inotify_init1
+333 i386 preadv sys_preadv __ia32_compat_sys_preadv
+334 i386 pwritev sys_pwritev __ia32_compat_sys_pwritev
+335 i386 rt_tgsigqueueinfo sys_rt_tgsigqueueinfo __ia32_compat_sys_rt_tgsigqueueinfo
+336 i386 perf_event_open sys_perf_event_open __ia32_sys_perf_event_open
+337 i386 recvmmsg sys_recvmmsg __ia32_compat_sys_recvmmsg
+338 i386 fanotify_init sys_fanotify_init __ia32_sys_fanotify_init
+339 i386 fanotify_mark sys_fanotify_mark __ia32_compat_sys_fanotify_mark
+340 i386 prlimit64 sys_prlimit64 __ia32_sys_prlimit64
+341 i386 name_to_handle_at sys_name_to_handle_at __ia32_sys_name_to_handle_at
+342 i386 open_by_handle_at sys_open_by_handle_at __ia32_compat_sys_open_by_handle_at
+343 i386 clock_adjtime sys_clock_adjtime __ia32_compat_sys_clock_adjtime
+344 i386 syncfs sys_syncfs __ia32_sys_syncfs
+345 i386 sendmmsg sys_sendmmsg __ia32_compat_sys_sendmmsg
+346 i386 setns sys_setns __ia32_sys_setns
+347 i386 process_vm_readv sys_process_vm_readv __ia32_compat_sys_process_vm_readv
+348 i386 process_vm_writev sys_process_vm_writev __ia32_compat_sys_process_vm_writev
+349 i386 kcmp sys_kcmp __ia32_sys_kcmp
+350 i386 finit_module sys_finit_module __ia32_sys_finit_module
+351 i386 sched_setattr sys_sched_setattr __ia32_sys_sched_setattr
+352 i386 sched_getattr sys_sched_getattr __ia32_sys_sched_getattr
+353 i386 renameat2 sys_renameat2 __ia32_sys_renameat2
+354 i386 seccomp sys_seccomp __ia32_sys_seccomp
+355 i386 getrandom sys_getrandom __ia32_sys_getrandom
+356 i386 memfd_create sys_memfd_create __ia32_sys_memfd_create
+357 i386 bpf sys_bpf __ia32_sys_bpf
+358 i386 execveat sys_execveat __ia32_compat_sys_execveat
+359 i386 socket sys_socket __ia32_sys_socket
+360 i386 socketpair sys_socketpair __ia32_sys_socketpair
+361 i386 bind sys_bind __ia32_sys_bind
+362 i386 connect sys_connect __ia32_sys_connect
+363 i386 listen sys_listen __ia32_sys_listen
+364 i386 accept4 sys_accept4 __ia32_sys_accept4
+365 i386 getsockopt sys_getsockopt __ia32_compat_sys_getsockopt
+366 i386 setsockopt sys_setsockopt __ia32_compat_sys_setsockopt
+367 i386 getsockname sys_getsockname __ia32_sys_getsockname
+368 i386 getpeername sys_getpeername __ia32_sys_getpeername
+369 i386 sendto sys_sendto __ia32_sys_sendto
+370 i386 sendmsg sys_sendmsg __ia32_compat_sys_sendmsg
+371 i386 recvfrom sys_recvfrom __ia32_compat_sys_recvfrom
+372 i386 recvmsg sys_recvmsg __ia32_compat_sys_recvmsg
+373 i386 shutdown sys_shutdown __ia32_sys_shutdown
+374 i386 userfaultfd sys_userfaultfd __ia32_sys_userfaultfd
+375 i386 membarrier sys_membarrier __ia32_sys_membarrier
+376 i386 mlock2 sys_mlock2 __ia32_sys_mlock2
+377 i386 copy_file_range sys_copy_file_range __ia32_sys_copy_file_range
+378 i386 preadv2 sys_preadv2 __ia32_compat_sys_preadv2
+379 i386 pwritev2 sys_pwritev2 __ia32_compat_sys_pwritev2
+380 i386 pkey_mprotect sys_pkey_mprotect __ia32_sys_pkey_mprotect
+381 i386 pkey_alloc sys_pkey_alloc __ia32_sys_pkey_alloc
+382 i386 pkey_free sys_pkey_free __ia32_sys_pkey_free
+383 i386 statx sys_statx __ia32_sys_statx
+384 i386 arch_prctl sys_arch_prctl __ia32_compat_sys_arch_prctl
diff --git a/arch/x86/entry/syscalls/syscall_64.tbl b/arch/x86/entry/syscalls/syscall_64.tbl
index 5aef183e2f85..4dfe42666d0c 100644
--- a/arch/x86/entry/syscalls/syscall_64.tbl
+++ b/arch/x86/entry/syscalls/syscall_64.tbl
@@ -4,379 +4,383 @@
# The format is:
# <number> <abi> <name> <entry point>
#
+# The __x64_sys_*() stubs are created on-the-fly for sys_*() system calls
+#
# The abi is "common", "64" or "x32" for this file.
#
-0 common read sys_read
-1 common write sys_write
-2 common open sys_open
-3 common close sys_close
-4 common stat sys_newstat
-5 common fstat sys_newfstat
-6 common lstat sys_newlstat
-7 common poll sys_poll
-8 common lseek sys_lseek
-9 common mmap sys_mmap
-10 common mprotect sys_mprotect
-11 common munmap sys_munmap
-12 common brk sys_brk
-13 64 rt_sigaction sys_rt_sigaction
-14 common rt_sigprocmask sys_rt_sigprocmask
-15 64 rt_sigreturn sys_rt_sigreturn/ptregs
-16 64 ioctl sys_ioctl
-17 common pread64 sys_pread64
-18 common pwrite64 sys_pwrite64
-19 64 readv sys_readv
-20 64 writev sys_writev
-21 common access sys_access
-22 common pipe sys_pipe
-23 common select sys_select
-24 common sched_yield sys_sched_yield
-25 common mremap sys_mremap
-26 common msync sys_msync
-27 common mincore sys_mincore
-28 common madvise sys_madvise
-29 common shmget sys_shmget
-30 common shmat sys_shmat
-31 common shmctl sys_shmctl
-32 common dup sys_dup
-33 common dup2 sys_dup2
-34 common pause sys_pause
-35 common nanosleep sys_nanosleep
-36 common getitimer sys_getitimer
-37 common alarm sys_alarm
-38 common setitimer sys_setitimer
-39 common getpid sys_getpid
-40 common sendfile sys_sendfile64
-41 common socket sys_socket
-42 common connect sys_connect
-43 common accept sys_accept
-44 common sendto sys_sendto
-45 64 recvfrom sys_recvfrom
-46 64 sendmsg sys_sendmsg
-47 64 recvmsg sys_recvmsg
-48 common shutdown sys_shutdown
-49 common bind sys_bind
-50 common listen sys_listen
-51 common getsockname sys_getsockname
-52 common getpeername sys_getpeername
-53 common socketpair sys_socketpair
-54 64 setsockopt sys_setsockopt
-55 64 getsockopt sys_getsockopt
-56 common clone sys_clone/ptregs
-57 common fork sys_fork/ptregs
-58 common vfork sys_vfork/ptregs
-59 64 execve sys_execve/ptregs
-60 common exit sys_exit
-61 common wait4 sys_wait4
-62 common kill sys_kill
-63 common uname sys_newuname
-64 common semget sys_semget
-65 common semop sys_semop
-66 common semctl sys_semctl
-67 common shmdt sys_shmdt
-68 common msgget sys_msgget
-69 common msgsnd sys_msgsnd
-70 common msgrcv sys_msgrcv
-71 common msgctl sys_msgctl
-72 common fcntl sys_fcntl
-73 common flock sys_flock
-74 common fsync sys_fsync
-75 common fdatasync sys_fdatasync
-76 common truncate sys_truncate
-77 common ftruncate sys_ftruncate
-78 common getdents sys_getdents
-79 common getcwd sys_getcwd
-80 common chdir sys_chdir
-81 common fchdir sys_fchdir
-82 common rename sys_rename
-83 common mkdir sys_mkdir
-84 common rmdir sys_rmdir
-85 common creat sys_creat
-86 common link sys_link
-87 common unlink sys_unlink
-88 common symlink sys_symlink
-89 common readlink sys_readlink
-90 common chmod sys_chmod
-91 common fchmod sys_fchmod
-92 common chown sys_chown
-93 common fchown sys_fchown
-94 common lchown sys_lchown
-95 common umask sys_umask
-96 common gettimeofday sys_gettimeofday
-97 common getrlimit sys_getrlimit
-98 common getrusage sys_getrusage
-99 common sysinfo sys_sysinfo
-100 common times sys_times
-101 64 ptrace sys_ptrace
-102 common getuid sys_getuid
-103 common syslog sys_syslog
-104 common getgid sys_getgid
-105 common setuid sys_setuid
-106 common setgid sys_setgid
-107 common geteuid sys_geteuid
-108 common getegid sys_getegid
-109 common setpgid sys_setpgid
-110 common getppid sys_getppid
-111 common getpgrp sys_getpgrp
-112 common setsid sys_setsid
-113 common setreuid sys_setreuid
-114 common setregid sys_setregid
-115 common getgroups sys_getgroups
-116 common setgroups sys_setgroups
-117 common setresuid sys_setresuid
-118 common getresuid sys_getresuid
-119 common setresgid sys_setresgid
-120 common getresgid sys_getresgid
-121 common getpgid sys_getpgid
-122 common setfsuid sys_setfsuid
-123 common setfsgid sys_setfsgid
-124 common getsid sys_getsid
-125 common capget sys_capget
-126 common capset sys_capset
-127 64 rt_sigpending sys_rt_sigpending
-128 64 rt_sigtimedwait sys_rt_sigtimedwait
-129 64 rt_sigqueueinfo sys_rt_sigqueueinfo
-130 common rt_sigsuspend sys_rt_sigsuspend
-131 64 sigaltstack sys_sigaltstack
-132 common utime sys_utime
-133 common mknod sys_mknod
+0 common read __x64_sys_read
+1 common write __x64_sys_write
+2 common open __x64_sys_open
+3 common close __x64_sys_close
+4 common stat __x64_sys_newstat
+5 common fstat __x64_sys_newfstat
+6 common lstat __x64_sys_newlstat
+7 common poll __x64_sys_poll
+8 common lseek __x64_sys_lseek
+9 common mmap __x64_sys_mmap
+10 common mprotect __x64_sys_mprotect
+11 common munmap __x64_sys_munmap
+12 common brk __x64_sys_brk
+13 64 rt_sigaction __x64_sys_rt_sigaction
+14 common rt_sigprocmask __x64_sys_rt_sigprocmask
+15 64 rt_sigreturn __x64_sys_rt_sigreturn/ptregs
+16 64 ioctl __x64_sys_ioctl
+17 common pread64 __x64_sys_pread64
+18 common pwrite64 __x64_sys_pwrite64
+19 64 readv __x64_sys_readv
+20 64 writev __x64_sys_writev
+21 common access __x64_sys_access
+22 common pipe __x64_sys_pipe
+23 common select __x64_sys_select
+24 common sched_yield __x64_sys_sched_yield
+25 common mremap __x64_sys_mremap
+26 common msync __x64_sys_msync
+27 common mincore __x64_sys_mincore
+28 common madvise __x64_sys_madvise
+29 common shmget __x64_sys_shmget
+30 common shmat __x64_sys_shmat
+31 common shmctl __x64_sys_shmctl
+32 common dup __x64_sys_dup
+33 common dup2 __x64_sys_dup2
+34 common pause __x64_sys_pause
+35 common nanosleep __x64_sys_nanosleep
+36 common getitimer __x64_sys_getitimer
+37 common alarm __x64_sys_alarm
+38 common setitimer __x64_sys_setitimer
+39 common getpid __x64_sys_getpid
+40 common sendfile __x64_sys_sendfile64
+41 common socket __x64_sys_socket
+42 common connect __x64_sys_connect
+43 common accept __x64_sys_accept
+44 common sendto __x64_sys_sendto
+45 64 recvfrom __x64_sys_recvfrom
+46 64 sendmsg __x64_sys_sendmsg
+47 64 recvmsg __x64_sys_recvmsg
+48 common shutdown __x64_sys_shutdown
+49 common bind __x64_sys_bind
+50 common listen __x64_sys_listen
+51 common getsockname __x64_sys_getsockname
+52 common getpeername __x64_sys_getpeername
+53 common socketpair __x64_sys_socketpair
+54 64 setsockopt __x64_sys_setsockopt
+55 64 getsockopt __x64_sys_getsockopt
+56 common clone __x64_sys_clone/ptregs
+57 common fork __x64_sys_fork/ptregs
+58 common vfork __x64_sys_vfork/ptregs
+59 64 execve __x64_sys_execve/ptregs
+60 common exit __x64_sys_exit
+61 common wait4 __x64_sys_wait4
+62 common kill __x64_sys_kill
+63 common uname __x64_sys_newuname
+64 common semget __x64_sys_semget
+65 common semop __x64_sys_semop
+66 common semctl __x64_sys_semctl
+67 common shmdt __x64_sys_shmdt
+68 common msgget __x64_sys_msgget
+69 common msgsnd __x64_sys_msgsnd
+70 common msgrcv __x64_sys_msgrcv
+71 common msgctl __x64_sys_msgctl
+72 common fcntl __x64_sys_fcntl
+73 common flock __x64_sys_flock
+74 common fsync __x64_sys_fsync
+75 common fdatasync __x64_sys_fdatasync
+76 common truncate __x64_sys_truncate
+77 common ftruncate __x64_sys_ftruncate
+78 common getdents __x64_sys_getdents
+79 common getcwd __x64_sys_getcwd
+80 common chdir __x64_sys_chdir
+81 common fchdir __x64_sys_fchdir
+82 common rename __x64_sys_rename
+83 common mkdir __x64_sys_mkdir
+84 common rmdir __x64_sys_rmdir
+85 common creat __x64_sys_creat
+86 common link __x64_sys_link
+87 common unlink __x64_sys_unlink
+88 common symlink __x64_sys_symlink
+89 common readlink __x64_sys_readlink
+90 common chmod __x64_sys_chmod
+91 common fchmod __x64_sys_fchmod
+92 common chown __x64_sys_chown
+93 common fchown __x64_sys_fchown
+94 common lchown __x64_sys_lchown
+95 common umask __x64_sys_umask
+96 common gettimeofday __x64_sys_gettimeofday
+97 common getrlimit __x64_sys_getrlimit
+98 common getrusage __x64_sys_getrusage
+99 common sysinfo __x64_sys_sysinfo
+100 common times __x64_sys_times
+101 64 ptrace __x64_sys_ptrace
+102 common getuid __x64_sys_getuid
+103 common syslog __x64_sys_syslog
+104 common getgid __x64_sys_getgid
+105 common setuid __x64_sys_setuid
+106 common setgid __x64_sys_setgid
+107 common geteuid __x64_sys_geteuid
+108 common getegid __x64_sys_getegid
+109 common setpgid __x64_sys_setpgid
+110 common getppid __x64_sys_getppid
+111 common getpgrp __x64_sys_getpgrp
+112 common setsid __x64_sys_setsid
+113 common setreuid __x64_sys_setreuid
+114 common setregid __x64_sys_setregid
+115 common getgroups __x64_sys_getgroups
+116 common setgroups __x64_sys_setgroups
+117 common setresuid __x64_sys_setresuid
+118 common getresuid __x64_sys_getresuid
+119 common setresgid __x64_sys_setresgid
+120 common getresgid __x64_sys_getresgid
+121 common getpgid __x64_sys_getpgid
+122 common setfsuid __x64_sys_setfsuid
+123 common setfsgid __x64_sys_setfsgid
+124 common getsid __x64_sys_getsid
+125 common capget __x64_sys_capget
+126 common capset __x64_sys_capset
+127 64 rt_sigpending __x64_sys_rt_sigpending
+128 64 rt_sigtimedwait __x64_sys_rt_sigtimedwait
+129 64 rt_sigqueueinfo __x64_sys_rt_sigqueueinfo
+130 common rt_sigsuspend __x64_sys_rt_sigsuspend
+131 64 sigaltstack __x64_sys_sigaltstack
+132 common utime __x64_sys_utime
+133 common mknod __x64_sys_mknod
134 64 uselib
-135 common personality sys_personality
-136 common ustat sys_ustat
-137 common statfs sys_statfs
-138 common fstatfs sys_fstatfs
-139 common sysfs sys_sysfs
-140 common getpriority sys_getpriority
-141 common setpriority sys_setpriority
-142 common sched_setparam sys_sched_setparam
-143 common sched_getparam sys_sched_getparam
-144 common sched_setscheduler sys_sched_setscheduler
-145 common sched_getscheduler sys_sched_getscheduler
-146 common sched_get_priority_max sys_sched_get_priority_max
-147 common sched_get_priority_min sys_sched_get_priority_min
-148 common sched_rr_get_interval sys_sched_rr_get_interval
-149 common mlock sys_mlock
-150 common munlock sys_munlock
-151 common mlockall sys_mlockall
-152 common munlockall sys_munlockall
-153 common vhangup sys_vhangup
-154 common modify_ldt sys_modify_ldt
-155 common pivot_root sys_pivot_root
-156 64 _sysctl sys_sysctl
-157 common prctl sys_prctl
-158 common arch_prctl sys_arch_prctl
-159 common adjtimex sys_adjtimex
-160 common setrlimit sys_setrlimit
-161 common chroot sys_chroot
-162 common sync sys_sync
-163 common acct sys_acct
-164 common settimeofday sys_settimeofday
-165 common mount sys_mount
-166 common umount2 sys_umount
-167 common swapon sys_swapon
-168 common swapoff sys_swapoff
-169 common reboot sys_reboot
-170 common sethostname sys_sethostname
-171 common setdomainname sys_setdomainname
-172 common iopl sys_iopl/ptregs
-173 common ioperm sys_ioperm
+135 common personality __x64_sys_personality
+136 common ustat __x64_sys_ustat
+137 common statfs __x64_sys_statfs
+138 common fstatfs __x64_sys_fstatfs
+139 common sysfs __x64_sys_sysfs
+140 common getpriority __x64_sys_getpriority
+141 common setpriority __x64_sys_setpriority
+142 common sched_setparam __x64_sys_sched_setparam
+143 common sched_getparam __x64_sys_sched_getparam
+144 common sched_setscheduler __x64_sys_sched_setscheduler
+145 common sched_getscheduler __x64_sys_sched_getscheduler
+146 common sched_get_priority_max __x64_sys_sched_get_priority_max
+147 common sched_get_priority_min __x64_sys_sched_get_priority_min
+148 common sched_rr_get_interval __x64_sys_sched_rr_get_interval
+149 common mlock __x64_sys_mlock
+150 common munlock __x64_sys_munlock
+151 common mlockall __x64_sys_mlockall
+152 common munlockall __x64_sys_munlockall
+153 common vhangup __x64_sys_vhangup
+154 common modify_ldt __x64_sys_modify_ldt
+155 common pivot_root __x64_sys_pivot_root
+156 64 _sysctl __x64_sys_sysctl
+157 common prctl __x64_sys_prctl
+158 common arch_prctl __x64_sys_arch_prctl
+159 common adjtimex __x64_sys_adjtimex
+160 common setrlimit __x64_sys_setrlimit
+161 common chroot __x64_sys_chroot
+162 common sync __x64_sys_sync
+163 common acct __x64_sys_acct
+164 common settimeofday __x64_sys_settimeofday
+165 common mount __x64_sys_mount
+166 common umount2 __x64_sys_umount
+167 common swapon __x64_sys_swapon
+168 common swapoff __x64_sys_swapoff
+169 common reboot __x64_sys_reboot
+170 common sethostname __x64_sys_sethostname
+171 common setdomainname __x64_sys_setdomainname
+172 common iopl __x64_sys_iopl/ptregs
+173 common ioperm __x64_sys_ioperm
174 64 create_module
-175 common init_module sys_init_module
-176 common delete_module sys_delete_module
+175 common init_module __x64_sys_init_module
+176 common delete_module __x64_sys_delete_module
177 64 get_kernel_syms
178 64 query_module
-179 common quotactl sys_quotactl
+179 common quotactl __x64_sys_quotactl
180 64 nfsservctl
181 common getpmsg
182 common putpmsg
183 common afs_syscall
184 common tuxcall
185 common security
-186 common gettid sys_gettid
-187 common readahead sys_readahead
-188 common setxattr sys_setxattr
-189 common lsetxattr sys_lsetxattr
-190 common fsetxattr sys_fsetxattr
-191 common getxattr sys_getxattr
-192 common lgetxattr sys_lgetxattr
-193 common fgetxattr sys_fgetxattr
-194 common listxattr sys_listxattr
-195 common llistxattr sys_llistxattr
-196 common flistxattr sys_flistxattr
-197 common removexattr sys_removexattr
-198 common lremovexattr sys_lremovexattr
-199 common fremovexattr sys_fremovexattr
-200 common tkill sys_tkill
-201 common time sys_time
-202 common futex sys_futex
-203 common sched_setaffinity sys_sched_setaffinity
-204 common sched_getaffinity sys_sched_getaffinity
+186 common gettid __x64_sys_gettid
+187 common readahead __x64_sys_readahead
+188 common setxattr __x64_sys_setxattr
+189 common lsetxattr __x64_sys_lsetxattr
+190 common fsetxattr __x64_sys_fsetxattr
+191 common getxattr __x64_sys_getxattr
+192 common lgetxattr __x64_sys_lgetxattr
+193 common fgetxattr __x64_sys_fgetxattr
+194 common listxattr __x64_sys_listxattr
+195 common llistxattr __x64_sys_llistxattr
+196 common flistxattr __x64_sys_flistxattr
+197 common removexattr __x64_sys_removexattr
+198 common lremovexattr __x64_sys_lremovexattr
+199 common fremovexattr __x64_sys_fremovexattr
+200 common tkill __x64_sys_tkill
+201 common time __x64_sys_time
+202 common futex __x64_sys_futex
+203 common sched_setaffinity __x64_sys_sched_setaffinity
+204 common sched_getaffinity __x64_sys_sched_getaffinity
205 64 set_thread_area
-206 64 io_setup sys_io_setup
-207 common io_destroy sys_io_destroy
-208 common io_getevents sys_io_getevents
-209 64 io_submit sys_io_submit
-210 common io_cancel sys_io_cancel
+206 64 io_setup __x64_sys_io_setup
+207 common io_destroy __x64_sys_io_destroy
+208 common io_getevents __x64_sys_io_getevents
+209 64 io_submit __x64_sys_io_submit
+210 common io_cancel __x64_sys_io_cancel
211 64 get_thread_area
-212 common lookup_dcookie sys_lookup_dcookie
-213 common epoll_create sys_epoll_create
+212 common lookup_dcookie __x64_sys_lookup_dcookie
+213 common epoll_create __x64_sys_epoll_create
214 64 epoll_ctl_old
215 64 epoll_wait_old
-216 common remap_file_pages sys_remap_file_pages
-217 common getdents64 sys_getdents64
-218 common set_tid_address sys_set_tid_address
-219 common restart_syscall sys_restart_syscall
-220 common semtimedop sys_semtimedop
-221 common fadvise64 sys_fadvise64
-222 64 timer_create sys_timer_create
-223 common timer_settime sys_timer_settime
-224 common timer_gettime sys_timer_gettime
-225 common timer_getoverrun sys_timer_getoverrun
-226 common timer_delete sys_timer_delete
-227 common clock_settime sys_clock_settime
-228 common clock_gettime sys_clock_gettime
-229 common clock_getres sys_clock_getres
-230 common clock_nanosleep sys_clock_nanosleep
-231 common exit_group sys_exit_group
-232 common epoll_wait sys_epoll_wait
-233 common epoll_ctl sys_epoll_ctl
-234 common tgkill sys_tgkill
-235 common utimes sys_utimes
+216 common remap_file_pages __x64_sys_remap_file_pages
+217 common getdents64 __x64_sys_getdents64
+218 common set_tid_address __x64_sys_set_tid_address
+219 common restart_syscall __x64_sys_restart_syscall
+220 common semtimedop __x64_sys_semtimedop
+221 common fadvise64 __x64_sys_fadvise64
+222 64 timer_create __x64_sys_timer_create
+223 common timer_settime __x64_sys_timer_settime
+224 common timer_gettime __x64_sys_timer_gettime
+225 common timer_getoverrun __x64_sys_timer_getoverrun
+226 common timer_delete __x64_sys_timer_delete
+227 common clock_settime __x64_sys_clock_settime
+228 common clock_gettime __x64_sys_clock_gettime
+229 common clock_getres __x64_sys_clock_getres
+230 common clock_nanosleep __x64_sys_clock_nanosleep
+231 common exit_group __x64_sys_exit_group
+232 common epoll_wait __x64_sys_epoll_wait
+233 common epoll_ctl __x64_sys_epoll_ctl
+234 common tgkill __x64_sys_tgkill
+235 common utimes __x64_sys_utimes
236 64 vserver
-237 common mbind sys_mbind
-238 common set_mempolicy sys_set_mempolicy
-239 common get_mempolicy sys_get_mempolicy
-240 common mq_open sys_mq_open
-241 common mq_unlink sys_mq_unlink
-242 common mq_timedsend sys_mq_timedsend
-243 common mq_timedreceive sys_mq_timedreceive
-244 64 mq_notify sys_mq_notify
-245 common mq_getsetattr sys_mq_getsetattr
-246 64 kexec_load sys_kexec_load
-247 64 waitid sys_waitid
-248 common add_key sys_add_key
-249 common request_key sys_request_key
-250 common keyctl sys_keyctl
-251 common ioprio_set sys_ioprio_set
-252 common ioprio_get sys_ioprio_get
-253 common inotify_init sys_inotify_init
-254 common inotify_add_watch sys_inotify_add_watch
-255 common inotify_rm_watch sys_inotify_rm_watch
-256 common migrate_pages sys_migrate_pages
-257 common openat sys_openat
-258 common mkdirat sys_mkdirat
-259 common mknodat sys_mknodat
-260 common fchownat sys_fchownat
-261 common futimesat sys_futimesat
-262 common newfstatat sys_newfstatat
-263 common unlinkat sys_unlinkat
-264 common renameat sys_renameat
-265 common linkat sys_linkat
-266 common symlinkat sys_symlinkat
-267 common readlinkat sys_readlinkat
-268 common fchmodat sys_fchmodat
-269 common faccessat sys_faccessat
-270 common pselect6 sys_pselect6
-271 common ppoll sys_ppoll
-272 common unshare sys_unshare
-273 64 set_robust_list sys_set_robust_list
-274 64 get_robust_list sys_get_robust_list
-275 common splice sys_splice
-276 common tee sys_tee
-277 common sync_file_range sys_sync_file_range
-278 64 vmsplice sys_vmsplice
-279 64 move_pages sys_move_pages
-280 common utimensat sys_utimensat
-281 common epoll_pwait sys_epoll_pwait
-282 common signalfd sys_signalfd
-283 common timerfd_create sys_timerfd_create
-284 common eventfd sys_eventfd
-285 common fallocate sys_fallocate
-286 common timerfd_settime sys_timerfd_settime
-287 common timerfd_gettime sys_timerfd_gettime
-288 common accept4 sys_accept4
-289 common signalfd4 sys_signalfd4
-290 common eventfd2 sys_eventfd2
-291 common epoll_create1 sys_epoll_create1
-292 common dup3 sys_dup3
-293 common pipe2 sys_pipe2
-294 common inotify_init1 sys_inotify_init1
-295 64 preadv sys_preadv
-296 64 pwritev sys_pwritev
-297 64 rt_tgsigqueueinfo sys_rt_tgsigqueueinfo
-298 common perf_event_open sys_perf_event_open
-299 64 recvmmsg sys_recvmmsg
-300 common fanotify_init sys_fanotify_init
-301 common fanotify_mark sys_fanotify_mark
-302 common prlimit64 sys_prlimit64
-303 common name_to_handle_at sys_name_to_handle_at
-304 common open_by_handle_at sys_open_by_handle_at
-305 common clock_adjtime sys_clock_adjtime
-306 common syncfs sys_syncfs
-307 64 sendmmsg sys_sendmmsg
-308 common setns sys_setns
-309 common getcpu sys_getcpu
-310 64 process_vm_readv sys_process_vm_readv
-311 64 process_vm_writev sys_process_vm_writev
-312 common kcmp sys_kcmp
-313 common finit_module sys_finit_module
-314 common sched_setattr sys_sched_setattr
-315 common sched_getattr sys_sched_getattr
-316 common renameat2 sys_renameat2
-317 common seccomp sys_seccomp
-318 common getrandom sys_getrandom
-319 common memfd_create sys_memfd_create
-320 common kexec_file_load sys_kexec_file_load
-321 common bpf sys_bpf
-322 64 execveat sys_execveat/ptregs
-323 common userfaultfd sys_userfaultfd
-324 common membarrier sys_membarrier
-325 common mlock2 sys_mlock2
-326 common copy_file_range sys_copy_file_range
-327 64 preadv2 sys_preadv2
-328 64 pwritev2 sys_pwritev2
-329 common pkey_mprotect sys_pkey_mprotect
-330 common pkey_alloc sys_pkey_alloc
-331 common pkey_free sys_pkey_free
-332 common statx sys_statx
+237 common mbind __x64_sys_mbind
+238 common set_mempolicy __x64_sys_set_mempolicy
+239 common get_mempolicy __x64_sys_get_mempolicy
+240 common mq_open __x64_sys_mq_open
+241 common mq_unlink __x64_sys_mq_unlink
+242 common mq_timedsend __x64_sys_mq_timedsend
+243 common mq_timedreceive __x64_sys_mq_timedreceive
+244 64 mq_notify __x64_sys_mq_notify
+245 common mq_getsetattr __x64_sys_mq_getsetattr
+246 64 kexec_load __x64_sys_kexec_load
+247 64 waitid __x64_sys_waitid
+248 common add_key __x64_sys_add_key
+249 common request_key __x64_sys_request_key
+250 common keyctl __x64_sys_keyctl
+251 common ioprio_set __x64_sys_ioprio_set
+252 common ioprio_get __x64_sys_ioprio_get
+253 common inotify_init __x64_sys_inotify_init
+254 common inotify_add_watch __x64_sys_inotify_add_watch
+255 common inotify_rm_watch __x64_sys_inotify_rm_watch
+256 common migrate_pages __x64_sys_migrate_pages
+257 common openat __x64_sys_openat
+258 common mkdirat __x64_sys_mkdirat
+259 common mknodat __x64_sys_mknodat
+260 common fchownat __x64_sys_fchownat
+261 common futimesat __x64_sys_futimesat
+262 common newfstatat __x64_sys_newfstatat
+263 common unlinkat __x64_sys_unlinkat
+264 common renameat __x64_sys_renameat
+265 common linkat __x64_sys_linkat
+266 common symlinkat __x64_sys_symlinkat
+267 common readlinkat __x64_sys_readlinkat
+268 common fchmodat __x64_sys_fchmodat
+269 common faccessat __x64_sys_faccessat
+270 common pselect6 __x64_sys_pselect6
+271 common ppoll __x64_sys_ppoll
+272 common unshare __x64_sys_unshare
+273 64 set_robust_list __x64_sys_set_robust_list
+274 64 get_robust_list __x64_sys_get_robust_list
+275 common splice __x64_sys_splice
+276 common tee __x64_sys_tee
+277 common sync_file_range __x64_sys_sync_file_range
+278 64 vmsplice __x64_sys_vmsplice
+279 64 move_pages __x64_sys_move_pages
+280 common utimensat __x64_sys_utimensat
+281 common epoll_pwait __x64_sys_epoll_pwait
+282 common signalfd __x64_sys_signalfd
+283 common timerfd_create __x64_sys_timerfd_create
+284 common eventfd __x64_sys_eventfd
+285 common fallocate __x64_sys_fallocate
+286 common timerfd_settime __x64_sys_timerfd_settime
+287 common timerfd_gettime __x64_sys_timerfd_gettime
+288 common accept4 __x64_sys_accept4
+289 common signalfd4 __x64_sys_signalfd4
+290 common eventfd2 __x64_sys_eventfd2
+291 common epoll_create1 __x64_sys_epoll_create1
+292 common dup3 __x64_sys_dup3
+293 common pipe2 __x64_sys_pipe2
+294 common inotify_init1 __x64_sys_inotify_init1
+295 64 preadv __x64_sys_preadv
+296 64 pwritev __x64_sys_pwritev
+297 64 rt_tgsigqueueinfo __x64_sys_rt_tgsigqueueinfo
+298 common perf_event_open __x64_sys_perf_event_open
+299 64 recvmmsg __x64_sys_recvmmsg
+300 common fanotify_init __x64_sys_fanotify_init
+301 common fanotify_mark __x64_sys_fanotify_mark
+302 common prlimit64 __x64_sys_prlimit64
+303 common name_to_handle_at __x64_sys_name_to_handle_at
+304 common open_by_handle_at __x64_sys_open_by_handle_at
+305 common clock_adjtime __x64_sys_clock_adjtime
+306 common syncfs __x64_sys_syncfs
+307 64 sendmmsg __x64_sys_sendmmsg
+308 common setns __x64_sys_setns
+309 common getcpu __x64_sys_getcpu
+310 64 process_vm_readv __x64_sys_process_vm_readv
+311 64 process_vm_writev __x64_sys_process_vm_writev
+312 common kcmp __x64_sys_kcmp
+313 common finit_module __x64_sys_finit_module
+314 common sched_setattr __x64_sys_sched_setattr
+315 common sched_getattr __x64_sys_sched_getattr
+316 common renameat2 __x64_sys_renameat2
+317 common seccomp __x64_sys_seccomp
+318 common getrandom __x64_sys_getrandom
+319 common memfd_create __x64_sys_memfd_create
+320 common kexec_file_load __x64_sys_kexec_file_load
+321 common bpf __x64_sys_bpf
+322 64 execveat __x64_sys_execveat/ptregs
+323 common userfaultfd __x64_sys_userfaultfd
+324 common membarrier __x64_sys_membarrier
+325 common mlock2 __x64_sys_mlock2
+326 common copy_file_range __x64_sys_copy_file_range
+327 64 preadv2 __x64_sys_preadv2
+328 64 pwritev2 __x64_sys_pwritev2
+329 common pkey_mprotect __x64_sys_pkey_mprotect
+330 common pkey_alloc __x64_sys_pkey_alloc
+331 common pkey_free __x64_sys_pkey_free
+332 common statx __x64_sys_statx
#
# x32-specific system call numbers start at 512 to avoid cache impact
-# for native 64-bit operation.
+# for native 64-bit operation. The __x32_compat_sys stubs are created
+# on-the-fly for compat_sys_*() compatibility system calls if X86_X32
+# is defined.
#
-512 x32 rt_sigaction compat_sys_rt_sigaction
+512 x32 rt_sigaction __x32_compat_sys_rt_sigaction
513 x32 rt_sigreturn sys32_x32_rt_sigreturn
-514 x32 ioctl compat_sys_ioctl
-515 x32 readv compat_sys_readv
-516 x32 writev compat_sys_writev
-517 x32 recvfrom compat_sys_recvfrom
-518 x32 sendmsg compat_sys_sendmsg
-519 x32 recvmsg compat_sys_recvmsg
-520 x32 execve compat_sys_execve/ptregs
-521 x32 ptrace compat_sys_ptrace
-522 x32 rt_sigpending compat_sys_rt_sigpending
-523 x32 rt_sigtimedwait compat_sys_rt_sigtimedwait
-524 x32 rt_sigqueueinfo compat_sys_rt_sigqueueinfo
-525 x32 sigaltstack compat_sys_sigaltstack
-526 x32 timer_create compat_sys_timer_create
-527 x32 mq_notify compat_sys_mq_notify
-528 x32 kexec_load compat_sys_kexec_load
-529 x32 waitid compat_sys_waitid
-530 x32 set_robust_list compat_sys_set_robust_list
-531 x32 get_robust_list compat_sys_get_robust_list
-532 x32 vmsplice compat_sys_vmsplice
-533 x32 move_pages compat_sys_move_pages
-534 x32 preadv compat_sys_preadv64
-535 x32 pwritev compat_sys_pwritev64
-536 x32 rt_tgsigqueueinfo compat_sys_rt_tgsigqueueinfo
-537 x32 recvmmsg compat_sys_recvmmsg
-538 x32 sendmmsg compat_sys_sendmmsg
-539 x32 process_vm_readv compat_sys_process_vm_readv
-540 x32 process_vm_writev compat_sys_process_vm_writev
-541 x32 setsockopt compat_sys_setsockopt
-542 x32 getsockopt compat_sys_getsockopt
-543 x32 io_setup compat_sys_io_setup
-544 x32 io_submit compat_sys_io_submit
-545 x32 execveat compat_sys_execveat/ptregs
-546 x32 preadv2 compat_sys_preadv64v2
-547 x32 pwritev2 compat_sys_pwritev64v2
+514 x32 ioctl __x32_compat_sys_ioctl
+515 x32 readv __x32_compat_sys_readv
+516 x32 writev __x32_compat_sys_writev
+517 x32 recvfrom __x32_compat_sys_recvfrom
+518 x32 sendmsg __x32_compat_sys_sendmsg
+519 x32 recvmsg __x32_compat_sys_recvmsg
+520 x32 execve __x32_compat_sys_execve/ptregs
+521 x32 ptrace __x32_compat_sys_ptrace
+522 x32 rt_sigpending __x32_compat_sys_rt_sigpending
+523 x32 rt_sigtimedwait __x32_compat_sys_rt_sigtimedwait
+524 x32 rt_sigqueueinfo __x32_compat_sys_rt_sigqueueinfo
+525 x32 sigaltstack __x32_compat_sys_sigaltstack
+526 x32 timer_create __x32_compat_sys_timer_create
+527 x32 mq_notify __x32_compat_sys_mq_notify
+528 x32 kexec_load __x32_compat_sys_kexec_load
+529 x32 waitid __x32_compat_sys_waitid
+530 x32 set_robust_list __x32_compat_sys_set_robust_list
+531 x32 get_robust_list __x32_compat_sys_get_robust_list
+532 x32 vmsplice __x32_compat_sys_vmsplice
+533 x32 move_pages __x32_compat_sys_move_pages
+534 x32 preadv __x32_compat_sys_preadv64
+535 x32 pwritev __x32_compat_sys_pwritev64
+536 x32 rt_tgsigqueueinfo __x32_compat_sys_rt_tgsigqueueinfo
+537 x32 recvmmsg __x32_compat_sys_recvmmsg
+538 x32 sendmmsg __x32_compat_sys_sendmmsg
+539 x32 process_vm_readv __x32_compat_sys_process_vm_readv
+540 x32 process_vm_writev __x32_compat_sys_process_vm_writev
+541 x32 setsockopt __x32_compat_sys_setsockopt
+542 x32 getsockopt __x32_compat_sys_getsockopt
+543 x32 io_setup __x32_compat_sys_io_setup
+544 x32 io_submit __x32_compat_sys_io_submit
+545 x32 execveat __x32_compat_sys_execveat/ptregs
+546 x32 preadv2 __x32_compat_sys_preadv64v2
+547 x32 pwritev2 __x32_compat_sys_pwritev64v2
diff --git a/arch/x86/entry/syscalls/syscalltbl.sh b/arch/x86/entry/syscalls/syscalltbl.sh
index d71ef4bd3615..94fcd1951aca 100644
--- a/arch/x86/entry/syscalls/syscalltbl.sh
+++ b/arch/x86/entry/syscalls/syscalltbl.sh
@@ -25,15 +25,27 @@ emit() {
nr="$2"
entry="$3"
compat="$4"
+ umlentry=""
if [ "$abi" = "64" -a -n "$compat" ]; then
echo "a compat entry for a 64-bit syscall makes no sense" >&2
exit 1
fi
+ # For CONFIG_UML, we need to strip the __x64_sys prefix
+ if [ "$abi" = "64" -a "${entry}" != "${entry#__x64_sys}" ]; then
+ umlentry="sys${entry#__x64_sys}"
+ fi
+
if [ -z "$compat" ]; then
- if [ -n "$entry" ]; then
+ if [ -n "$entry" -a -z "$umlentry" ]; then
syscall_macro "$abi" "$nr" "$entry"
+ elif [ -n "$umlentry" ]; then # implies -n "$entry"
+ echo "#ifdef CONFIG_X86"
+ syscall_macro "$abi" "$nr" "$entry"
+ echo "#else /* CONFIG_UML */"
+ syscall_macro "$abi" "$nr" "$umlentry"
+ echo "#endif"
fi
else
echo "#ifdef CONFIG_X86_32"
diff --git a/arch/x86/entry/vdso/vdso32/vclock_gettime.c b/arch/x86/entry/vdso/vdso32/vclock_gettime.c
index 7780bbfb06ef..9242b28418d5 100644
--- a/arch/x86/entry/vdso/vdso32/vclock_gettime.c
+++ b/arch/x86/entry/vdso/vdso32/vclock_gettime.c
@@ -5,8 +5,6 @@
#undef CONFIG_OPTIMIZE_INLINING
#endif
-#undef CONFIG_X86_PPRO_FENCE
-
#ifdef CONFIG_X86_64
/*
diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c
index 577fa8adb785..70b7845434cb 100644
--- a/arch/x86/entry/vsyscall/vsyscall_64.c
+++ b/arch/x86/entry/vsyscall/vsyscall_64.c
@@ -42,10 +42,8 @@
#define CREATE_TRACE_POINTS
#include "vsyscall_trace.h"
-static enum { EMULATE, NATIVE, NONE } vsyscall_mode =
-#if defined(CONFIG_LEGACY_VSYSCALL_NATIVE)
- NATIVE;
-#elif defined(CONFIG_LEGACY_VSYSCALL_NONE)
+static enum { EMULATE, NONE } vsyscall_mode =
+#ifdef CONFIG_LEGACY_VSYSCALL_NONE
NONE;
#else
EMULATE;
@@ -56,8 +54,6 @@ static int __init vsyscall_setup(char *str)
if (str) {
if (!strcmp("emulate", str))
vsyscall_mode = EMULATE;
- else if (!strcmp("native", str))
- vsyscall_mode = NATIVE;
else if (!strcmp("none", str))
vsyscall_mode = NONE;
else
@@ -131,6 +127,7 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
int vsyscall_nr, syscall_nr, tmp;
int prev_sig_on_uaccess_err;
long ret;
+ unsigned long orig_dx;
/*
* No point in checking CS -- the only way to get here is a user mode
@@ -139,10 +136,6 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
WARN_ON_ONCE(address != regs->ip);
- /* This should be unreachable in NATIVE mode. */
- if (WARN_ON(vsyscall_mode == NATIVE))
- return false;
-
if (vsyscall_mode == NONE) {
warn_bad_vsyscall(KERN_INFO, regs,
"vsyscall attempted with vsyscall=none");
@@ -235,19 +228,22 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
ret = -EFAULT;
switch (vsyscall_nr) {
case 0:
- ret = sys_gettimeofday(
- (struct timeval __user *)regs->di,
- (struct timezone __user *)regs->si);
+ /* this decodes regs->di and regs->si on its own */
+ ret = __x64_sys_gettimeofday(regs);
break;
case 1:
- ret = sys_time((time_t __user *)regs->di);
+ /* this decodes regs->di on its own */
+ ret = __x64_sys_time(regs);
break;
case 2:
- ret = sys_getcpu((unsigned __user *)regs->di,
- (unsigned __user *)regs->si,
- NULL);
+ /* while we could clobber regs->dx, we didn't in the past... */
+ orig_dx = regs->dx;
+ regs->dx = 0;
+ /* this decodes regs->di, regs->si and regs->dx on its own */
+ ret = __x64_sys_getcpu(regs);
+ regs->dx = orig_dx;
break;
}
@@ -355,7 +351,7 @@ void __init set_vsyscall_pgtable_user_bits(pgd_t *root)
set_pgd(pgd, __pgd(pgd_val(*pgd) | _PAGE_USER));
p4d = p4d_offset(pgd, VSYSCALL_ADDR);
#if CONFIG_PGTABLE_LEVELS >= 5
- p4d->p4d |= _PAGE_USER;
+ set_p4d(p4d, __p4d(p4d_val(*p4d) | _PAGE_USER));
#endif
pud = pud_offset(p4d, VSYSCALL_ADDR);
set_pud(pud, __pud(pud_val(*pud) | _PAGE_USER));
@@ -370,9 +366,7 @@ void __init map_vsyscall(void)
if (vsyscall_mode != NONE) {
__set_fixmap(VSYSCALL_PAGE, physaddr_vsyscall,
- vsyscall_mode == NATIVE
- ? PAGE_KERNEL_VSYSCALL
- : PAGE_KERNEL_VVAR);
+ PAGE_KERNEL_VVAR);
set_vsyscall_pgtable_user_bits(swapper_pg_dir);
}
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 140d33288e78..a6006e7bb729 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -48,7 +48,7 @@ DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
.enabled = 1,
};
-struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE;
+DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
u64 __read_mostly hw_cache_event_ids
[PERF_COUNT_HW_CACHE_MAX]
@@ -990,7 +990,7 @@ static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader,
if (!dogrp)
return n;
- list_for_each_entry(event, &leader->sibling_list, group_entry) {
+ for_each_sibling_event(event, leader) {
if (!is_x86_event(event) ||
event->state <= PERF_EVENT_STATE_OFF)
continue;
@@ -1156,16 +1156,13 @@ int x86_perf_event_set_period(struct perf_event *event)
per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
- if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) ||
- local64_read(&hwc->prev_count) != (u64)-left) {
- /*
- * The hw event starts counting from this event offset,
- * mark it to be able to extra future deltas:
- */
- local64_set(&hwc->prev_count, (u64)-left);
+ /*
+ * The hw event starts counting from this event offset,
+ * mark it to be able to extra future deltas:
+ */
+ local64_set(&hwc->prev_count, (u64)-left);
- wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
- }
+ wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
/*
* Due to erratum on certan cpu we need
@@ -1884,6 +1881,8 @@ early_initcall(init_hw_perf_events);
static inline void x86_pmu_read(struct perf_event *event)
{
+ if (x86_pmu.read)
+ return x86_pmu.read(event);
x86_perf_event_update(event);
}
@@ -2118,7 +2117,8 @@ static int x86_pmu_event_init(struct perf_event *event)
event->destroy(event);
}
- if (READ_ONCE(x86_pmu.attr_rdpmc))
+ if (READ_ONCE(x86_pmu.attr_rdpmc) &&
+ !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
return err;
@@ -2206,9 +2206,9 @@ static ssize_t set_attr_rdpmc(struct device *cdev,
* but only root can trigger it, so it's okay.
*/
if (val == 2)
- static_key_slow_inc(&rdpmc_always_available);
+ static_branch_inc(&rdpmc_always_available_key);
else
- static_key_slow_dec(&rdpmc_always_available);
+ static_branch_dec(&rdpmc_always_available_key);
on_each_cpu(refresh_pce, NULL, 1);
}
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 56457cb73448..607bf565a90c 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2060,6 +2060,14 @@ static void intel_pmu_del_event(struct perf_event *event)
intel_pmu_pebs_del(event);
}
+static void intel_pmu_read_event(struct perf_event *event)
+{
+ if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
+ intel_pmu_auto_reload_read(event);
+ else
+ x86_perf_event_update(event);
+}
+
static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
{
int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
@@ -2201,16 +2209,23 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
int bit, loops;
u64 status;
int handled;
+ int pmu_enabled;
cpuc = this_cpu_ptr(&cpu_hw_events);
/*
+ * Save the PMU state.
+ * It needs to be restored when leaving the handler.
+ */
+ pmu_enabled = cpuc->enabled;
+ /*
* No known reason to not always do late ACK,
* but just in case do it opt-in.
*/
if (!x86_pmu.late_ack)
apic_write(APIC_LVTPC, APIC_DM_NMI);
intel_bts_disable_local();
+ cpuc->enabled = 0;
__intel_pmu_disable_all();
handled = intel_pmu_drain_bts_buffer();
handled += intel_bts_interrupt();
@@ -2320,7 +2335,8 @@ again:
done:
/* Only restore PMU state when it's active. See x86_pmu_disable(). */
- if (cpuc->enabled)
+ cpuc->enabled = pmu_enabled;
+ if (pmu_enabled)
__intel_pmu_enable_all(0, true);
intel_bts_enable_local();
@@ -2952,9 +2968,9 @@ static void intel_pebs_aliases_skl(struct perf_event *event)
return intel_pebs_aliases_precdist(event);
}
-static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
+static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
{
- unsigned long flags = x86_pmu.free_running_flags;
+ unsigned long flags = x86_pmu.large_pebs_flags;
if (event->attr.use_clockid)
flags &= ~PERF_SAMPLE_TIME;
@@ -2976,8 +2992,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
if (!event->attr.freq) {
event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
if (!(event->attr.sample_type &
- ~intel_pmu_free_running_flags(event)))
- event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
+ ~intel_pmu_large_pebs_flags(event)))
+ event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
}
if (x86_pmu.pebs_aliases)
x86_pmu.pebs_aliases(event);
@@ -3188,13 +3204,13 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
* Therefore the effective (average) period matches the requested period,
* despite coarser hardware granularity.
*/
-static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
+static u64 bdw_limit_period(struct perf_event *event, u64 left)
{
if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
X86_CONFIG(.event=0xc0, .umask=0x01)) {
if (left < 128)
left = 128;
- left &= ~0x3fu;
+ left &= ~0x3fULL;
}
return left;
}
@@ -3460,7 +3476,7 @@ static __initconst const struct x86_pmu core_pmu = {
.event_map = intel_pmu_event_map,
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
.apic = 1,
- .free_running_flags = PEBS_FREERUNNING_FLAGS,
+ .large_pebs_flags = LARGE_PEBS_FLAGS,
/*
* Intel PMCs cannot be accessed sanely above 32-bit width,
@@ -3495,6 +3511,7 @@ static __initconst const struct x86_pmu intel_pmu = {
.disable = intel_pmu_disable_event,
.add = intel_pmu_add_event,
.del = intel_pmu_del_event,
+ .read = intel_pmu_read_event,
.hw_config = intel_pmu_hw_config,
.schedule_events = x86_schedule_events,
.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
@@ -3502,7 +3519,7 @@ static __initconst const struct x86_pmu intel_pmu = {
.event_map = intel_pmu_event_map,
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
.apic = 1,
- .free_running_flags = PEBS_FREERUNNING_FLAGS,
+ .large_pebs_flags = LARGE_PEBS_FLAGS,
/*
* Intel PMCs cannot be accessed sanely above 32 bit width,
* so we install an artificial 1<<31 period regardless of
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index 72db0664a53d..9aca448bb8e6 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -40,50 +40,51 @@
* Model specific counters:
* MSR_CORE_C1_RES: CORE C1 Residency Counter
* perf code: 0x00
- * Available model: SLM,AMT,GLM
+ * Available model: SLM,AMT,GLM,CNL
* Scope: Core (each processor core has a MSR)
* MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
* perf code: 0x01
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
+ CNL
* Scope: Core
* MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter
* perf code: 0x02
- * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM
+ * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,
+ * SKL,KNL,GLM,CNL
* Scope: Core
* MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter
* perf code: 0x03
- * Available model: SNB,IVB,HSW,BDW,SKL
+ * Available model: SNB,IVB,HSW,BDW,SKL,CNL
* Scope: Core
* MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter.
* perf code: 0x00
- * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM
+ * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter.
* perf code: 0x01
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL
- * GLM
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,
+ * GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter.
* perf code: 0x02
* Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW
- * SKL,KNL,GLM
+ * SKL,KNL,GLM,CNL
* Scope: Package (physical package)
* MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
* perf code: 0x03
- * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL
+ * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL
* Scope: Package (physical package)
* MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
* perf code: 0x04
- * Available model: HSW ULT only
+ * Available model: HSW ULT,CNL
* Scope: Package (physical package)
* MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
* perf code: 0x05
- * Available model: HSW ULT only
+ * Available model: HSW ULT,CNL
* Scope: Package (physical package)
* MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
* perf code: 0x06
- * Available model: HSW ULT, GLM
+ * Available model: HSW ULT,GLM,CNL
* Scope: Package (physical package)
*
*/
@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = {
BIT(PERF_CSTATE_PKG_C10_RES),
};
+static const struct cstate_model cnl_cstates __initconst = {
+ .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
+ BIT(PERF_CSTATE_CORE_C3_RES) |
+ BIT(PERF_CSTATE_CORE_C6_RES) |
+ BIT(PERF_CSTATE_CORE_C7_RES),
+
+ .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
+ BIT(PERF_CSTATE_PKG_C3_RES) |
+ BIT(PERF_CSTATE_PKG_C6_RES) |
+ BIT(PERF_CSTATE_PKG_C7_RES) |
+ BIT(PERF_CSTATE_PKG_C8_RES) |
+ BIT(PERF_CSTATE_PKG_C9_RES) |
+ BIT(PERF_CSTATE_PKG_C10_RES),
+};
+
static const struct cstate_model slm_cstates __initconst = {
.core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
BIT(PERF_CSTATE_CORE_C6_RES),
@@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
+
X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 18c25ab28557..da6780122786 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -935,7 +935,7 @@ void intel_pmu_pebs_add(struct perf_event *event)
bool needed_cb = pebs_needs_sched_cb(cpuc);
cpuc->n_pebs++;
- if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
+ if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
cpuc->n_large_pebs++;
pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
@@ -975,7 +975,7 @@ void intel_pmu_pebs_del(struct perf_event *event)
bool needed_cb = pebs_needs_sched_cb(cpuc);
cpuc->n_pebs--;
- if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
+ if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
cpuc->n_large_pebs--;
pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
@@ -1153,6 +1153,7 @@ static void setup_pebs_sample_data(struct perf_event *event,
if (pebs == NULL)
return;
+ regs->flags &= ~PERF_EFLAGS_EXACT;
sample_type = event->attr.sample_type;
dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
@@ -1197,7 +1198,6 @@ static void setup_pebs_sample_data(struct perf_event *event,
*/
*regs = *iregs;
regs->flags = pebs->flags;
- set_linear_ip(regs, pebs->ip);
if (sample_type & PERF_SAMPLE_REGS_INTR) {
regs->ax = pebs->ax;
@@ -1233,13 +1233,22 @@ static void setup_pebs_sample_data(struct perf_event *event,
#endif
}
- if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
- regs->ip = pebs->real_ip;
- regs->flags |= PERF_EFLAGS_EXACT;
- } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
- regs->flags |= PERF_EFLAGS_EXACT;
- else
- regs->flags &= ~PERF_EFLAGS_EXACT;
+ if (event->attr.precise_ip > 1) {
+ /* Haswell and later have the eventing IP, so use it: */
+ if (x86_pmu.intel_cap.pebs_format >= 2) {
+ set_linear_ip(regs, pebs->real_ip);
+ regs->flags |= PERF_EFLAGS_EXACT;
+ } else {
+ /* Otherwise use PEBS off-by-1 IP: */
+ set_linear_ip(regs, pebs->ip);
+
+ /* ... and try to fix it up using the LBR entries: */
+ if (intel_pmu_pebs_fixup_ip(regs))
+ regs->flags |= PERF_EFLAGS_EXACT;
+ }
+ } else
+ set_linear_ip(regs, pebs->ip);
+
if ((sample_type & (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) &&
x86_pmu.intel_cap.pebs_format >= 1)
@@ -1306,17 +1315,93 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit)
return NULL;
}
+void intel_pmu_auto_reload_read(struct perf_event *event)
+{
+ WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
+
+ perf_pmu_disable(event->pmu);
+ intel_pmu_drain_pebs_buffer();
+ perf_pmu_enable(event->pmu);
+}
+
+/*
+ * Special variant of intel_pmu_save_and_restart() for auto-reload.
+ */
+static int
+intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
+{
+ struct hw_perf_event *hwc = &event->hw;
+ int shift = 64 - x86_pmu.cntval_bits;
+ u64 period = hwc->sample_period;
+ u64 prev_raw_count, new_raw_count;
+ s64 new, old;
+
+ WARN_ON(!period);
+
+ /*
+ * drain_pebs() only happens when the PMU is disabled.
+ */
+ WARN_ON(this_cpu_read(cpu_hw_events.enabled));
+
+ prev_raw_count = local64_read(&hwc->prev_count);
+ rdpmcl(hwc->event_base_rdpmc, new_raw_count);
+ local64_set(&hwc->prev_count, new_raw_count);
+
+ /*
+ * Since the counter increments a negative counter value and
+ * overflows on the sign switch, giving the interval:
+ *
+ * [-period, 0]
+ *
+ * the difference between two consequtive reads is:
+ *
+ * A) value2 - value1;
+ * when no overflows have happened in between,
+ *
+ * B) (0 - value1) + (value2 - (-period));
+ * when one overflow happened in between,
+ *
+ * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
+ * when @n overflows happened in between.
+ *
+ * Here A) is the obvious difference, B) is the extension to the
+ * discrete interval, where the first term is to the top of the
+ * interval and the second term is from the bottom of the next
+ * interval and C) the extension to multiple intervals, where the
+ * middle term is the whole intervals covered.
+ *
+ * An equivalent of C, by reduction, is:
+ *
+ * value2 - value1 + n * period
+ */
+ new = ((s64)(new_raw_count << shift) >> shift);
+ old = ((s64)(prev_raw_count << shift) >> shift);
+ local64_add(new - old + count * period, &event->count);
+
+ perf_event_update_userpage(event);
+
+ return 0;
+}
+
static void __intel_pmu_pebs_event(struct perf_event *event,
struct pt_regs *iregs,
void *base, void *top,
int bit, int count)
{
+ struct hw_perf_event *hwc = &event->hw;
struct perf_sample_data data;
struct pt_regs regs;
void *at = get_next_pebs_record_by_bit(base, top, bit);
- if (!intel_pmu_save_and_restart(event) &&
- !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
+ if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
+ /*
+ * Now, auto-reload is only enabled in fixed period mode.
+ * The reload value is always hwc->sample_period.
+ * May need to change it, if auto-reload is enabled in
+ * freq mode later.
+ */
+ intel_pmu_save_and_restart_reload(event, count);
+ } else if (!intel_pmu_save_and_restart(event))
return;
while (count > 1) {
@@ -1368,8 +1453,11 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
return;
n = top - at;
- if (n <= 0)
+ if (n <= 0) {
+ if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
+ intel_pmu_save_and_restart_reload(event, 0);
return;
+ }
__intel_pmu_pebs_event(event, iregs, at, top, 0, n);
}
@@ -1392,8 +1480,22 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
ds->pebs_index = ds->pebs_buffer_base;
- if (unlikely(base >= top))
+ if (unlikely(base >= top)) {
+ /*
+ * The drain_pebs() could be called twice in a short period
+ * for auto-reload event in pmu::read(). There are no
+ * overflows have happened in between.
+ * It needs to call intel_pmu_save_and_restart_reload() to
+ * update the event->count for this case.
+ */
+ for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled,
+ x86_pmu.max_pebs_events) {
+ event = cpuc->events[bit];
+ if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
+ intel_pmu_save_and_restart_reload(event, 0);
+ }
return;
+ }
for (at = base; at < top; at += x86_pmu.pebs_record_size) {
struct pebs_record_nhm *p = at;
@@ -1530,7 +1632,7 @@ void __init intel_ds_init(void)
x86_pmu.pebs_record_size =
sizeof(struct pebs_record_skl);
x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
- x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
+ x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
break;
default:
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index 81fd41d5a0d9..3b993942a0e4 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -1186,8 +1186,12 @@ static int pt_event_addr_filters_validate(struct list_head *filters)
int range = 0;
list_for_each_entry(filter, filters, entry) {
- /* PT doesn't support single address triggers */
- if (!filter->range || !filter->size)
+ /*
+ * PT doesn't support single address triggers and
+ * 'start' filters.
+ */
+ if (!filter->size ||
+ filter->action == PERF_ADDR_FILTER_ACTION_START)
return -EOPNOTSUPP;
if (!filter->inode) {
@@ -1227,7 +1231,10 @@ static void pt_event_addr_filters_sync(struct perf_event *event)
filters->filter[range].msr_a = msr_a;
filters->filter[range].msr_b = msr_b;
- filters->filter[range].config = filter->filter ? 1 : 2;
+ if (filter->action == PERF_ADDR_FILTER_ACTION_FILTER)
+ filters->filter[range].config = 1;
+ else
+ filters->filter[range].config = 2;
range++;
}
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index a2efb490f743..32f3e9423e99 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -774,6 +774,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = {
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_MOBILE, skl_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_KABYLAKE_DESKTOP, skl_rapl_init),
+ X86_RAPL_MODEL_MATCH(INTEL_FAM6_CANNONLAKE_MOBILE, skl_rapl_init),
+
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init),
X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_DENVERTON, hsw_rapl_init),
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 7874c980d569..a7956fc7ca1d 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -354,7 +354,7 @@ uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader,
if (!dogrp)
return n;
- list_for_each_entry(event, &leader->sibling_list, group_entry) {
+ for_each_sibling_event(event, leader) {
if (!is_box_event(box, event) ||
event->state <= PERF_EVENT_STATE_OFF)
continue;
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 6d8044ab1060..c98b943e58b4 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -3343,6 +3343,7 @@ static struct extra_reg skx_uncore_cha_extra_regs[] = {
SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4),
SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8),
SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8),
+ SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3),
EVENT_EXTRA_END
};
@@ -3562,24 +3563,27 @@ static struct intel_uncore_type *skx_msr_uncores[] = {
NULL,
};
+/*
+ * To determine the number of CHAs, it should read bits 27:0 in the CAPID6
+ * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083.
+ */
+#define SKX_CAPID6 0x9c
+#define SKX_CHA_BIT_MASK GENMASK(27, 0)
+
static int skx_count_chabox(void)
{
- struct pci_dev *chabox_dev = NULL;
- int bus, count = 0;
+ struct pci_dev *dev = NULL;
+ u32 val = 0;
- while (1) {
- chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev);
- if (!chabox_dev)
- break;
- if (count == 0)
- bus = chabox_dev->bus->number;
- if (bus != chabox_dev->bus->number)
- break;
- count++;
- }
+ dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev);
+ if (!dev)
+ goto out;
- pci_dev_put(chabox_dev);
- return count;
+ pci_read_config_dword(dev, SKX_CAPID6, &val);
+ val &= SKX_CHA_BIT_MASK;
+out:
+ pci_dev_put(dev);
+ return hweight32(val);
}
void skx_uncore_cpu_init(void)
@@ -3606,7 +3610,7 @@ static struct intel_uncore_type skx_uncore_imc = {
};
static struct attribute *skx_upi_uncore_formats_attr[] = {
- &format_attr_event_ext.attr,
+ &format_attr_event.attr,
&format_attr_umask_ext.attr,
&format_attr_edge.attr,
&format_attr_inv.attr,
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 18e2628e2d8f..e7edf19e64c2 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -188,10 +188,11 @@ static inline u64 msr_read_counter(struct perf_event *event)
if (event->hw.event_base)
rdmsrl(event->hw.event_base, now);
else
- rdtscll(now);
+ now = rdtsc_ordered();
return now;
}
+
static void msr_event_update(struct perf_event *event)
{
u64 prev, now;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 78f91ec1056e..9f3711470ec1 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -69,7 +69,7 @@ struct event_constraint {
#define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
#define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
#define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
-#define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */
+#define PERF_X86_EVENT_LARGE_PEBS 0x0800 /* use large PEBS */
struct amd_nb {
@@ -88,7 +88,7 @@ struct amd_nb {
* REGS_USER can be handled for events limited to ring 3.
*
*/
-#define PEBS_FREERUNNING_FLAGS \
+#define LARGE_PEBS_FLAGS \
(PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
@@ -520,6 +520,7 @@ struct x86_pmu {
void (*disable)(struct perf_event *);
void (*add)(struct perf_event *);
void (*del)(struct perf_event *);
+ void (*read)(struct perf_event *event);
int (*hw_config)(struct perf_event *event);
int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
unsigned eventsel;
@@ -557,7 +558,7 @@ struct x86_pmu {
struct x86_pmu_quirk *quirks;
int perfctr_second_write;
bool late_ack;
- unsigned (*limit_period)(struct perf_event *event, unsigned l);
+ u64 (*limit_period)(struct perf_event *event, u64 l);
/*
* sysfs attrs
@@ -608,7 +609,7 @@ struct x86_pmu {
struct event_constraint *pebs_constraints;
void (*pebs_aliases)(struct perf_event *event);
int max_pebs_events;
- unsigned long free_running_flags;
+ unsigned long large_pebs_flags;
/*
* Intel LBR
@@ -923,6 +924,8 @@ void intel_pmu_pebs_disable_all(void);
void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
+void intel_pmu_auto_reload_read(struct perf_event *event);
+
void intel_ds_init(void);
void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c
index 41c671854642..86b1341cba9a 100644
--- a/arch/x86/ia32/ia32_signal.c
+++ b/arch/x86/ia32/ia32_signal.c
@@ -33,7 +33,6 @@
#include <asm/vdso.h>
#include <asm/sigframe.h>
#include <asm/sighandling.h>
-#include <asm/sys_ia32.h>
#include <asm/smap.h>
/*
diff --git a/arch/x86/ia32/sys_ia32.c b/arch/x86/ia32/sys_ia32.c
index 96cd33bbfc85..11ef7b7c9cc8 100644
--- a/arch/x86/ia32/sys_ia32.c
+++ b/arch/x86/ia32/sys_ia32.c
@@ -41,27 +41,28 @@
#include <linux/highuid.h>
#include <linux/sysctl.h>
#include <linux/slab.h>
+#include <linux/sched/task.h>
#include <asm/mman.h>
#include <asm/types.h>
#include <linux/uaccess.h>
#include <linux/atomic.h>
#include <asm/vgtod.h>
-#include <asm/sys_ia32.h>
+#include <asm/ia32.h>
#define AA(__x) ((unsigned long)(__x))
-asmlinkage long sys32_truncate64(const char __user *filename,
- unsigned long offset_low,
- unsigned long offset_high)
+COMPAT_SYSCALL_DEFINE3(x86_truncate64, const char __user *, filename,
+ unsigned long, offset_low, unsigned long, offset_high)
{
- return sys_truncate(filename, ((loff_t) offset_high << 32) | offset_low);
+ return ksys_truncate(filename,
+ ((loff_t) offset_high << 32) | offset_low);
}
-asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long offset_low,
- unsigned long offset_high)
+COMPAT_SYSCALL_DEFINE3(x86_ftruncate64, unsigned int, fd,
+ unsigned long, offset_low, unsigned long, offset_high)
{
- return sys_ftruncate(fd, ((loff_t) offset_high << 32) | offset_low);
+ return ksys_ftruncate(fd, ((loff_t) offset_high << 32) | offset_low);
}
/*
@@ -96,8 +97,8 @@ static int cp_stat64(struct stat64 __user *ubuf, struct kstat *stat)
return 0;
}
-asmlinkage long sys32_stat64(const char __user *filename,
- struct stat64 __user *statbuf)
+COMPAT_SYSCALL_DEFINE2(x86_stat64, const char __user *, filename,
+ struct stat64 __user *, statbuf)
{
struct kstat stat;
int ret = vfs_stat(filename, &stat);
@@ -107,8 +108,8 @@ asmlinkage long sys32_stat64(const char __user *filename,
return ret;
}
-asmlinkage long sys32_lstat64(const char __user *filename,
- struct stat64 __user *statbuf)
+COMPAT_SYSCALL_DEFINE2(x86_lstat64, const char __user *, filename,
+ struct stat64 __user *, statbuf)
{
struct kstat stat;
int ret = vfs_lstat(filename, &stat);
@@ -117,7 +118,8 @@ asmlinkage long sys32_lstat64(const char __user *filename,
return ret;
}
-asmlinkage long sys32_fstat64(unsigned int fd, struct stat64 __user *statbuf)
+COMPAT_SYSCALL_DEFINE2(x86_fstat64, unsigned int, fd,
+ struct stat64 __user *, statbuf)
{
struct kstat stat;
int ret = vfs_fstat(fd, &stat);
@@ -126,8 +128,9 @@ asmlinkage long sys32_fstat64(unsigned int fd, struct stat64 __user *statbuf)
return ret;
}
-asmlinkage long sys32_fstatat(unsigned int dfd, const char __user *filename,
- struct stat64 __user *statbuf, int flag)
+COMPAT_SYSCALL_DEFINE4(x86_fstatat, unsigned int, dfd,
+ const char __user *, filename,
+ struct stat64 __user *, statbuf, int, flag)
{
struct kstat stat;
int error;
@@ -153,7 +156,7 @@ struct mmap_arg_struct32 {
unsigned int offset;
};
-asmlinkage long sys32_mmap(struct mmap_arg_struct32 __user *arg)
+COMPAT_SYSCALL_DEFINE1(x86_mmap, struct mmap_arg_struct32 __user *, arg)
{
struct mmap_arg_struct32 a;
@@ -163,29 +166,23 @@ asmlinkage long sys32_mmap(struct mmap_arg_struct32 __user *arg)
if (a.offset & ~PAGE_MASK)
return -EINVAL;
- return sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
+ return ksys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
a.offset>>PAGE_SHIFT);
}
-asmlinkage long sys32_waitpid(compat_pid_t pid, unsigned int __user *stat_addr,
- int options)
-{
- return compat_sys_wait4(pid, stat_addr, options, NULL);
-}
-
/* warning: next two assume little endian */
-asmlinkage long sys32_pread(unsigned int fd, char __user *ubuf, u32 count,
- u32 poslo, u32 poshi)
+COMPAT_SYSCALL_DEFINE5(x86_pread, unsigned int, fd, char __user *, ubuf,
+ u32, count, u32, poslo, u32, poshi)
{
- return sys_pread64(fd, ubuf, count,
- ((loff_t)AA(poshi) << 32) | AA(poslo));
+ return ksys_pread64(fd, ubuf, count,
+ ((loff_t)AA(poshi) << 32) | AA(poslo));
}
-asmlinkage long sys32_pwrite(unsigned int fd, const char __user *ubuf,
- u32 count, u32 poslo, u32 poshi)
+COMPAT_SYSCALL_DEFINE5(x86_pwrite, unsigned int, fd, const char __user *, ubuf,
+ u32, count, u32, poslo, u32, poshi)
{
- return sys_pwrite64(fd, ubuf, count,
- ((loff_t)AA(poshi) << 32) | AA(poslo));
+ return ksys_pwrite64(fd, ubuf, count,
+ ((loff_t)AA(poshi) << 32) | AA(poslo));
}
@@ -193,40 +190,53 @@ asmlinkage long sys32_pwrite(unsigned int fd, const char __user *ubuf,
* Some system calls that need sign extended arguments. This could be
* done by a generic wrapper.
*/
-long sys32_fadvise64_64(int fd, __u32 offset_low, __u32 offset_high,
- __u32 len_low, __u32 len_high, int advice)
+COMPAT_SYSCALL_DEFINE6(x86_fadvise64_64, int, fd, __u32, offset_low,
+ __u32, offset_high, __u32, len_low, __u32, len_high,
+ int, advice)
+{
+ return ksys_fadvise64_64(fd,
+ (((u64)offset_high)<<32) | offset_low,
+ (((u64)len_high)<<32) | len_low,
+ advice);
+}
+
+COMPAT_SYSCALL_DEFINE4(x86_readahead, int, fd, unsigned int, off_lo,
+ unsigned int, off_hi, size_t, count)
{
- return sys_fadvise64_64(fd,
- (((u64)offset_high)<<32) | offset_low,
- (((u64)len_high)<<32) | len_low,
- advice);
+ return ksys_readahead(fd, ((u64)off_hi << 32) | off_lo, count);
}
-asmlinkage ssize_t sys32_readahead(int fd, unsigned off_lo, unsigned off_hi,
- size_t count)
+COMPAT_SYSCALL_DEFINE6(x86_sync_file_range, int, fd, unsigned int, off_low,
+ unsigned int, off_hi, unsigned int, n_low,
+ unsigned int, n_hi, int, flags)
{
- return sys_readahead(fd, ((u64)off_hi << 32) | off_lo, count);
+ return ksys_sync_file_range(fd,
+ ((u64)off_hi << 32) | off_low,
+ ((u64)n_hi << 32) | n_low, flags);
}
-asmlinkage long sys32_sync_file_range(int fd, unsigned off_low, unsigned off_hi,
- unsigned n_low, unsigned n_hi, int flags)
+COMPAT_SYSCALL_DEFINE5(x86_fadvise64, int, fd, unsigned int, offset_lo,
+ unsigned int, offset_hi, size_t, len, int, advice)
{
- return sys_sync_file_range(fd,
- ((u64)off_hi << 32) | off_low,
- ((u64)n_hi << 32) | n_low, flags);
+ return ksys_fadvise64_64(fd, ((u64)offset_hi << 32) | offset_lo,
+ len, advice);
}
-asmlinkage long sys32_fadvise64(int fd, unsigned offset_lo, unsigned offset_hi,
- size_t len, int advice)
+COMPAT_SYSCALL_DEFINE6(x86_fallocate, int, fd, int, mode,
+ unsigned int, offset_lo, unsigned int, offset_hi,
+ unsigned int, len_lo, unsigned int, len_hi)
{
- return sys_fadvise64_64(fd, ((u64)offset_hi << 32) | offset_lo,
- len, advice);
+ return ksys_fallocate(fd, mode, ((u64)offset_hi << 32) | offset_lo,
+ ((u64)len_hi << 32) | len_lo);
}
-asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_lo,
- unsigned offset_hi, unsigned len_lo,
- unsigned len_hi)
+/*
+ * The 32-bit clone ABI is CONFIG_CLONE_BACKWARDS
+ */
+COMPAT_SYSCALL_DEFINE5(x86_clone, unsigned long, clone_flags,
+ unsigned long, newsp, int __user *, parent_tidptr,
+ unsigned long, tls_val, int __user *, child_tidptr)
{
- return sys_fallocate(fd, mode, ((u64)offset_hi << 32) | offset_lo,
- ((u64)len_hi << 32) | len_lo);
+ return _do_fork(clone_flags, newsp, 0, parent_tidptr, child_tidptr,
+ tls_val);
}
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 11881726ed37..a303d7b7d763 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -31,6 +31,7 @@
#include <asm/mmu.h>
#include <asm/mpspec.h>
#include <asm/realmode.h>
+#include <asm/x86_init.h>
#ifdef CONFIG_ACPI_APEI
# include <asm/pgtable_types.h>
@@ -133,6 +134,14 @@ static inline bool acpi_has_cpu_in_madt(void)
return !!acpi_lapic;
}
+#define ACPI_HAVE_ARCH_GET_ROOT_POINTER
+static inline u64 acpi_arch_get_root_pointer(void)
+{
+ return x86_init.acpi.get_root_pointer();
+}
+
+void acpi_generic_reduced_hw_init(void);
+
#else /* !CONFIG_ACPI */
#define acpi_lapic 0
@@ -142,6 +151,8 @@ static inline void acpi_noirq_set(void) { }
static inline void acpi_disable_pci(void) { }
static inline void disable_acpi(void) { }
+static inline void acpi_generic_reduced_hw_init(void) { }
+
#endif /* !CONFIG_ACPI */
#define ARCH_HAS_POWER_INIT 1
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index cf5961ca8677..4cd6a3b71824 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -218,13 +218,11 @@ static inline int alternatives_text_reserved(void *start, void *end)
*/
#define alternative_call_2(oldfunc, newfunc1, feature1, newfunc2, feature2, \
output, input...) \
-{ \
asm volatile (ALTERNATIVE_2("call %P[old]", "call %P[new1]", feature1,\
"call %P[new2]", feature2) \
: output, ASM_CALL_CONSTRAINT \
: [old] "i" (oldfunc), [new1] "i" (newfunc1), \
- [new2] "i" (newfunc2), ## input); \
-}
+ [new2] "i" (newfunc2), ## input)
/*
* use this macro(s) if you need more than one output parameter
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index f01eef8b392e..08acd954f00e 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -138,7 +138,6 @@ extern void lapic_shutdown(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void apic_intr_mode_init(void);
-extern void setup_local_APIC(void);
extern void init_apic_mappings(void);
void register_lapic_address(unsigned long address);
extern void setup_boot_APIC_clock(void);
@@ -183,6 +182,7 @@ static inline void disable_local_APIC(void) { }
# define setup_boot_APIC_clock x86_init_noop
# define setup_secondary_APIC_clock x86_init_noop
static inline void lapic_update_tsc_freq(void) { }
+static inline void init_bsp_APIC(void) { }
static inline void apic_intr_mode_init(void) { }
static inline void lapic_assign_system_vectors(void) { }
static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
@@ -304,12 +304,6 @@ struct apic {
u32 irq_delivery_mode;
u32 irq_dest_mode;
- /* Functions and data related to vector allocation */
- void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
- const struct cpumask *mask);
- int (*cpu_mask_to_apicid)(const struct cpumask *cpumask,
- struct irq_data *irqdata,
- unsigned int *apicid);
u32 (*calc_dest_apicid)(unsigned int cpu);
/* ICR related functions */
@@ -499,17 +493,7 @@ extern void default_setup_apic_routing(void);
extern u32 apic_default_calc_apicid(unsigned int cpu);
extern u32 apic_flat_calc_apicid(unsigned int cpu);
-extern int flat_cpu_mask_to_apicid(const struct cpumask *cpumask,
- struct irq_data *irqdata,
- unsigned int *apicid);
-extern int default_cpu_mask_to_apicid(const struct cpumask *cpumask,
- struct irq_data *irqdata,
- unsigned int *apicid);
extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
-extern void flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
- const struct cpumask *mask);
-extern void default_vector_allocation_domain(int cpu, struct cpumask *retmask,
- const struct cpumask *mask);
extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int phys_apicid);
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index 72759f131cc5..0db6bec95489 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -17,36 +17,40 @@
#define ATOMIC_INIT(i) { (i) }
/**
- * atomic_read - read atomic variable
+ * arch_atomic_read - read atomic variable
* @v: pointer of type atomic_t
*
* Atomically reads the value of @v.
*/
-static __always_inline int atomic_read(const atomic_t *v)
+static __always_inline int arch_atomic_read(const atomic_t *v)
{
+ /*
+ * Note for KASAN: we deliberately don't use READ_ONCE_NOCHECK() here,
+ * it's non-inlined function that increases binary size and stack usage.
+ */
return READ_ONCE((v)->counter);
}
/**
- * atomic_set - set atomic variable
+ * arch_atomic_set - set atomic variable
* @v: pointer of type atomic_t
* @i: required value
*
* Atomically sets the value of @v to @i.
*/
-static __always_inline void atomic_set(atomic_t *v, int i)
+static __always_inline void arch_atomic_set(atomic_t *v, int i)
{
WRITE_ONCE(v->counter, i);
}
/**
- * atomic_add - add integer to atomic variable
+ * arch_atomic_add - add integer to atomic variable
* @i: integer value to add
* @v: pointer of type atomic_t
*
* Atomically adds @i to @v.
*/
-static __always_inline void atomic_add(int i, atomic_t *v)
+static __always_inline void arch_atomic_add(int i, atomic_t *v)
{
asm volatile(LOCK_PREFIX "addl %1,%0"
: "+m" (v->counter)
@@ -54,13 +58,13 @@ static __always_inline void atomic_add(int i, atomic_t *v)
}
/**
- * atomic_sub - subtract integer from atomic variable
+ * arch_atomic_sub - subtract integer from atomic variable
* @i: integer value to subtract
* @v: pointer of type atomic_t
*
* Atomically subtracts @i from @v.
*/
-static __always_inline void atomic_sub(int i, atomic_t *v)
+static __always_inline void arch_atomic_sub(int i, atomic_t *v)
{
asm volatile(LOCK_PREFIX "subl %1,%0"
: "+m" (v->counter)
@@ -68,7 +72,7 @@ static __always_inline void atomic_sub(int i, atomic_t *v)
}
/**
- * atomic_sub_and_test - subtract value from variable and test result
+ * arch_atomic_sub_and_test - subtract value from variable and test result
* @i: integer value to subtract
* @v: pointer of type atomic_t
*
@@ -76,63 +80,63 @@ static __always_inline void atomic_sub(int i, atomic_t *v)
* true if the result is zero, or false for all
* other cases.
*/
-static __always_inline bool atomic_sub_and_test(int i, atomic_t *v)
+static __always_inline bool arch_atomic_sub_and_test(int i, atomic_t *v)
{
GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, "er", i, "%0", e);
}
/**
- * atomic_inc - increment atomic variable
+ * arch_atomic_inc - increment atomic variable
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1.
*/
-static __always_inline void atomic_inc(atomic_t *v)
+static __always_inline void arch_atomic_inc(atomic_t *v)
{
asm volatile(LOCK_PREFIX "incl %0"
: "+m" (v->counter));
}
/**
- * atomic_dec - decrement atomic variable
+ * arch_atomic_dec - decrement atomic variable
* @v: pointer of type atomic_t
*
* Atomically decrements @v by 1.
*/
-static __always_inline void atomic_dec(atomic_t *v)
+static __always_inline void arch_atomic_dec(atomic_t *v)
{
asm volatile(LOCK_PREFIX "decl %0"
: "+m" (v->counter));
}
/**
- * atomic_dec_and_test - decrement and test
+ * arch_atomic_dec_and_test - decrement and test
* @v: pointer of type atomic_t
*
* Atomically decrements @v by 1 and
* returns true if the result is 0, or false for all other
* cases.
*/
-static __always_inline bool atomic_dec_and_test(atomic_t *v)
+static __always_inline bool arch_atomic_dec_and_test(atomic_t *v)
{
GEN_UNARY_RMWcc(LOCK_PREFIX "decl", v->counter, "%0", e);
}
/**
- * atomic_inc_and_test - increment and test
+ * arch_atomic_inc_and_test - increment and test
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
-static __always_inline bool atomic_inc_and_test(atomic_t *v)
+static __always_inline bool arch_atomic_inc_and_test(atomic_t *v)
{
GEN_UNARY_RMWcc(LOCK_PREFIX "incl", v->counter, "%0", e);
}
/**
- * atomic_add_negative - add and test if negative
+ * arch_atomic_add_negative - add and test if negative
* @i: integer value to add
* @v: pointer of type atomic_t
*
@@ -140,65 +144,65 @@ static __always_inline bool atomic_inc_and_test(atomic_t *v)
* if the result is negative, or false when
* result is greater than or equal to zero.
*/
-static __always_inline bool atomic_add_negative(int i, atomic_t *v)
+static __always_inline bool arch_atomic_add_negative(int i, atomic_t *v)
{
GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, "er", i, "%0", s);
}
/**
- * atomic_add_return - add integer and return
+ * arch_atomic_add_return - add integer and return
* @i: integer value to add
* @v: pointer of type atomic_t
*
* Atomically adds @i to @v and returns @i + @v
*/
-static __always_inline int atomic_add_return(int i, atomic_t *v)
+static __always_inline int arch_atomic_add_return(int i, atomic_t *v)
{
return i + xadd(&v->counter, i);
}
/**
- * atomic_sub_return - subtract integer and return
+ * arch_atomic_sub_return - subtract integer and return
* @v: pointer of type atomic_t
* @i: integer value to subtract
*
* Atomically subtracts @i from @v and returns @v - @i
*/
-static __always_inline int atomic_sub_return(int i, atomic_t *v)
+static __always_inline int arch_atomic_sub_return(int i, atomic_t *v)
{
- return atomic_add_return(-i, v);
+ return arch_atomic_add_return(-i, v);
}
-#define atomic_inc_return(v) (atomic_add_return(1, v))
-#define atomic_dec_return(v) (atomic_sub_return(1, v))
+#define arch_atomic_inc_return(v) (arch_atomic_add_return(1, v))
+#define arch_atomic_dec_return(v) (arch_atomic_sub_return(1, v))
-static __always_inline int atomic_fetch_add(int i, atomic_t *v)
+static __always_inline int arch_atomic_fetch_add(int i, atomic_t *v)
{
return xadd(&v->counter, i);
}
-static __always_inline int atomic_fetch_sub(int i, atomic_t *v)
+static __always_inline int arch_atomic_fetch_sub(int i, atomic_t *v)
{
return xadd(&v->counter, -i);
}
-static __always_inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+static __always_inline int arch_atomic_cmpxchg(atomic_t *v, int old, int new)
{
- return cmpxchg(&v->counter, old, new);
+ return arch_cmpxchg(&v->counter, old, new);
}
-#define atomic_try_cmpxchg atomic_try_cmpxchg
-static __always_inline bool atomic_try_cmpxchg(atomic_t *v, int *old, int new)
+#define arch_atomic_try_cmpxchg arch_atomic_try_cmpxchg
+static __always_inline bool arch_atomic_try_cmpxchg(atomic_t *v, int *old, int new)
{
return try_cmpxchg(&v->counter, old, new);
}
-static inline int atomic_xchg(atomic_t *v, int new)
+static inline int arch_atomic_xchg(atomic_t *v, int new)
{
return xchg(&v->counter, new);
}
-static inline void atomic_and(int i, atomic_t *v)
+static inline void arch_atomic_and(int i, atomic_t *v)
{
asm volatile(LOCK_PREFIX "andl %1,%0"
: "+m" (v->counter)
@@ -206,16 +210,16 @@ static inline void atomic_and(int i, atomic_t *v)
: "memory");
}
-static inline int atomic_fetch_and(int i, atomic_t *v)
+static inline int arch_atomic_fetch_and(int i, atomic_t *v)
{
- int val = atomic_read(v);
+ int val = arch_atomic_read(v);
- do { } while (!atomic_try_cmpxchg(v, &val, val & i));
+ do { } while (!arch_atomic_try_cmpxchg(v, &val, val & i));
return val;
}
-static inline void atomic_or(int i, atomic_t *v)
+static inline void arch_atomic_or(int i, atomic_t *v)
{
asm volatile(LOCK_PREFIX "orl %1,%0"
: "+m" (v->counter)
@@ -223,16 +227,16 @@ static inline void atomic_or(int i, atomic_t *v)
: "memory");
}
-static inline int atomic_fetch_or(int i, atomic_t *v)
+static inline int arch_atomic_fetch_or(int i, atomic_t *v)
{
- int val = atomic_read(v);
+ int val = arch_atomic_read(v);
- do { } while (!atomic_try_cmpxchg(v, &val, val | i));
+ do { } while (!arch_atomic_try_cmpxchg(v, &val, val | i));
return val;
}
-static inline void atomic_xor(int i, atomic_t *v)
+static inline void arch_atomic_xor(int i, atomic_t *v)
{
asm volatile(LOCK_PREFIX "xorl %1,%0"
: "+m" (v->counter)
@@ -240,17 +244,17 @@ static inline void atomic_xor(int i, atomic_t *v)
: "memory");
}
-static inline int atomic_fetch_xor(int i, atomic_t *v)
+static inline int arch_atomic_fetch_xor(int i, atomic_t *v)
{
- int val = atomic_read(v);
+ int val = arch_atomic_read(v);
- do { } while (!atomic_try_cmpxchg(v, &val, val ^ i));
+ do { } while (!arch_atomic_try_cmpxchg(v, &val, val ^ i));
return val;
}
/**
- * __atomic_add_unless - add unless the number is already a given value
+ * __arch_atomic_add_unless - add unless the number is already a given value
* @v: pointer of type atomic_t
* @a: the amount to add to v...
* @u: ...unless v is equal to u.
@@ -258,14 +262,14 @@ static inline int atomic_fetch_xor(int i, atomic_t *v)
* Atomically adds @a to @v, so long as @v was not already @u.
* Returns the old value of @v.
*/
-static __always_inline int __atomic_add_unless(atomic_t *v, int a, int u)
+static __always_inline int __arch_atomic_add_unless(atomic_t *v, int a, int u)
{
- int c = atomic_read(v);
+ int c = arch_atomic_read(v);
do {
if (unlikely(c == u))
break;
- } while (!atomic_try_cmpxchg(v, &c, c + a));
+ } while (!arch_atomic_try_cmpxchg(v, &c, c + a));
return c;
}
@@ -276,4 +280,6 @@ static __always_inline int __atomic_add_unless(atomic_t *v, int a, int u)
# include <asm/atomic64_64.h>
#endif
+#include <asm-generic/atomic-instrumented.h>
+
#endif /* _ASM_X86_ATOMIC_H */
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
index 97c46b8169b7..46e1ef17d92d 100644
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -62,7 +62,7 @@ ATOMIC64_DECL(add_unless);
#undef ATOMIC64_EXPORT
/**
- * atomic64_cmpxchg - cmpxchg atomic64 variable
+ * arch_atomic64_cmpxchg - cmpxchg atomic64 variable
* @v: pointer to type atomic64_t
* @o: expected value
* @n: new value
@@ -71,20 +71,21 @@ ATOMIC64_DECL(add_unless);
* the old value.
*/
-static inline long long atomic64_cmpxchg(atomic64_t *v, long long o, long long n)
+static inline long long arch_atomic64_cmpxchg(atomic64_t *v, long long o,
+ long long n)
{
- return cmpxchg64(&v->counter, o, n);
+ return arch_cmpxchg64(&v->counter, o, n);
}
/**
- * atomic64_xchg - xchg atomic64 variable
+ * arch_atomic64_xchg - xchg atomic64 variable
* @v: pointer to type atomic64_t
* @n: value to assign
*
* Atomically xchgs the value of @v to @n and returns
* the old value.
*/
-static inline long long atomic64_xchg(atomic64_t *v, long long n)
+static inline long long arch_atomic64_xchg(atomic64_t *v, long long n)
{
long long o;
unsigned high = (unsigned)(n >> 32);
@@ -96,13 +97,13 @@ static inline long long atomic64_xchg(atomic64_t *v, long long n)
}
/**
- * atomic64_set - set atomic64 variable
+ * arch_atomic64_set - set atomic64 variable
* @v: pointer to type atomic64_t
* @i: value to assign
*
* Atomically sets the value of @v to @n.
*/
-static inline void atomic64_set(atomic64_t *v, long long i)
+static inline void arch_atomic64_set(atomic64_t *v, long long i)
{
unsigned high = (unsigned)(i >> 32);
unsigned low = (unsigned)i;
@@ -112,12 +113,12 @@ static inline void atomic64_set(atomic64_t *v, long long i)
}
/**
- * atomic64_read - read atomic64 variable
+ * arch_atomic64_read - read atomic64 variable
* @v: pointer to type atomic64_t
*
* Atomically reads the value of @v and returns it.
*/
-static inline long long atomic64_read(const atomic64_t *v)
+static inline long long arch_atomic64_read(const atomic64_t *v)
{
long long r;
alternative_atomic64(read, "=&A" (r), "c" (v) : "memory");
@@ -125,13 +126,13 @@ static inline long long atomic64_read(const atomic64_t *v)
}
/**
- * atomic64_add_return - add and return
+ * arch_atomic64_add_return - add and return
* @i: integer value to add
* @v: pointer to type atomic64_t
*
* Atomically adds @i to @v and returns @i + *@v
*/
-static inline long long atomic64_add_return(long long i, atomic64_t *v)
+static inline long long arch_atomic64_add_return(long long i, atomic64_t *v)
{
alternative_atomic64(add_return,
ASM_OUTPUT2("+A" (i), "+c" (v)),
@@ -142,7 +143,7 @@ static inline long long atomic64_add_return(long long i, atomic64_t *v)
/*
* Other variants with different arithmetic operators:
*/
-static inline long long atomic64_sub_return(long long i, atomic64_t *v)
+static inline long long arch_atomic64_sub_return(long long i, atomic64_t *v)
{
alternative_atomic64(sub_return,
ASM_OUTPUT2("+A" (i), "+c" (v)),
@@ -150,7 +151,7 @@ static inline long long atomic64_sub_return(long long i, atomic64_t *v)
return i;
}
-static inline long long atomic64_inc_return(atomic64_t *v)
+static inline long long arch_atomic64_inc_return(atomic64_t *v)
{
long long a;
alternative_atomic64(inc_return, "=&A" (a),
@@ -158,7 +159,7 @@ static inline long long atomic64_inc_return(atomic64_t *v)
return a;
}
-static inline long long atomic64_dec_return(atomic64_t *v)
+static inline long long arch_atomic64_dec_return(atomic64_t *v)
{
long long a;
alternative_atomic64(dec_return, "=&A" (a),
@@ -167,13 +168,13 @@ static inline long long atomic64_dec_return(atomic64_t *v)
}
/**
- * atomic64_add - add integer to atomic64 variable
+ * arch_atomic64_add - add integer to atomic64 variable
* @i: integer value to add
* @v: pointer to type atomic64_t
*
* Atomically adds @i to @v.
*/
-static inline long long atomic64_add(long long i, atomic64_t *v)
+static inline long long arch_atomic64_add(long long i, atomic64_t *v)
{
__alternative_atomic64(add, add_return,
ASM_OUTPUT2("+A" (i), "+c" (v)),
@@ -182,13 +183,13 @@ static inline long long atomic64_add(long long i, atomic64_t *v)
}
/**
- * atomic64_sub - subtract the atomic64 variable
+ * arch_atomic64_sub - subtract the atomic64 variable
* @i: integer value to subtract
* @v: pointer to type atomic64_t
*
* Atomically subtracts @i from @v.
*/
-static inline long long atomic64_sub(long long i, atomic64_t *v)
+static inline long long arch_atomic64_sub(long long i, atomic64_t *v)
{
__alternative_atomic64(sub, sub_return,
ASM_OUTPUT2("+A" (i), "+c" (v)),
@@ -197,7 +198,7 @@ static inline long long atomic64_sub(long long i, atomic64_t *v)
}
/**
- * atomic64_sub_and_test - subtract value from variable and test result
+ * arch_atomic64_sub_and_test - subtract value from variable and test result
* @i: integer value to subtract
* @v: pointer to type atomic64_t
*
@@ -205,46 +206,46 @@ static inline long long atomic64_sub(long long i, atomic64_t *v)
* true if the result is zero, or false for all
* other cases.
*/
-static inline int atomic64_sub_and_test(long long i, atomic64_t *v)
+static inline int arch_atomic64_sub_and_test(long long i, atomic64_t *v)
{
- return atomic64_sub_return(i, v) == 0;
+ return arch_atomic64_sub_return(i, v) == 0;
}
/**
- * atomic64_inc - increment atomic64 variable
+ * arch_atomic64_inc - increment atomic64 variable
* @v: pointer to type atomic64_t
*
* Atomically increments @v by 1.
*/
-static inline void atomic64_inc(atomic64_t *v)
+static inline void arch_atomic64_inc(atomic64_t *v)
{
__alternative_atomic64(inc, inc_return, /* no output */,
"S" (v) : "memory", "eax", "ecx", "edx");
}
/**
- * atomic64_dec - decrement atomic64 variable
+ * arch_atomic64_dec - decrement atomic64 variable
* @v: pointer to type atomic64_t
*
* Atomically decrements @v by 1.
*/
-static inline void atomic64_dec(atomic64_t *v)
+static inline void arch_atomic64_dec(atomic64_t *v)
{
__alternative_atomic64(dec, dec_return, /* no output */,
"S" (v) : "memory", "eax", "ecx", "edx");
}
/**
- * atomic64_dec_and_test - decrement and test
+ * arch_atomic64_dec_and_test - decrement and test
* @v: pointer to type atomic64_t
*
* Atomically decrements @v by 1 and
* returns true if the result is 0, or false for all other
* cases.
*/
-static inline int atomic64_dec_and_test(atomic64_t *v)
+static inline int arch_atomic64_dec_and_test(atomic64_t *v)
{
- return atomic64_dec_return(v) == 0;
+ return arch_atomic64_dec_return(v) == 0;
}
/**
@@ -255,13 +256,13 @@ static inline int atomic64_dec_and_test(atomic64_t *v)
* and returns true if the result is zero, or false for all
* other cases.
*/
-static inline int atomic64_inc_and_test(atomic64_t *v)
+static inline int arch_atomic64_inc_and_test(atomic64_t *v)
{
- return atomic64_inc_return(v) == 0;
+ return arch_atomic64_inc_return(v) == 0;
}
/**
- * atomic64_add_negative - add and test if negative
+ * arch_atomic64_add_negative - add and test if negative
* @i: integer value to add
* @v: pointer to type atomic64_t
*
@@ -269,13 +270,13 @@ static inline int atomic64_inc_and_test(atomic64_t *v)
* if the result is negative, or false when
* result is greater than or equal to zero.
*/
-static inline int atomic64_add_negative(long long i, atomic64_t *v)
+static inline int arch_atomic64_add_negative(long long i, atomic64_t *v)
{
- return atomic64_add_return(i, v) < 0;
+ return arch_atomic64_add_return(i, v) < 0;
}
/**
- * atomic64_add_unless - add unless the number is a given value
+ * arch_atomic64_add_unless - add unless the number is a given value
* @v: pointer of type atomic64_t
* @a: the amount to add to v...
* @u: ...unless v is equal to u.
@@ -283,7 +284,8 @@ static inline int atomic64_add_negative(long long i, atomic64_t *v)
* Atomically adds @a to @v, so long as it was not @u.
* Returns non-zero if the add was done, zero otherwise.
*/
-static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
+static inline int arch_atomic64_add_unless(atomic64_t *v, long long a,
+ long long u)
{
unsigned low = (unsigned)u;
unsigned high = (unsigned)(u >> 32);
@@ -294,7 +296,7 @@ static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
}
-static inline int atomic64_inc_not_zero(atomic64_t *v)
+static inline int arch_atomic64_inc_not_zero(atomic64_t *v)
{
int r;
alternative_atomic64(inc_not_zero, "=&a" (r),
@@ -302,7 +304,7 @@ static inline int atomic64_inc_not_zero(atomic64_t *v)
return r;
}
-static inline long long atomic64_dec_if_positive(atomic64_t *v)
+static inline long long arch_atomic64_dec_if_positive(atomic64_t *v)
{
long long r;
alternative_atomic64(dec_if_positive, "=&A" (r),
@@ -313,70 +315,70 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v)
#undef alternative_atomic64
#undef __alternative_atomic64
-static inline void atomic64_and(long long i, atomic64_t *v)
+static inline void arch_atomic64_and(long long i, atomic64_t *v)
{
long long old, c = 0;
- while ((old = atomic64_cmpxchg(v, c, c & i)) != c)
+ while ((old = arch_atomic64_cmpxchg(v, c, c & i)) != c)
c = old;
}
-static inline long long atomic64_fetch_and(long long i, atomic64_t *v)
+static inline long long arch_atomic64_fetch_and(long long i, atomic64_t *v)
{
long long old, c = 0;
- while ((old = atomic64_cmpxchg(v, c, c & i)) != c)
+ while ((old = arch_atomic64_cmpxchg(v, c, c & i)) != c)
c = old;
return old;
}
-static inline void atomic64_or(long long i, atomic64_t *v)
+static inline void arch_atomic64_or(long long i, atomic64_t *v)
{
long long old, c = 0;
- while ((old = atomic64_cmpxchg(v, c, c | i)) != c)
+ while ((old = arch_atomic64_cmpxchg(v, c, c | i)) != c)
c = old;
}
-static inline long long atomic64_fetch_or(long long i, atomic64_t *v)
+static inline long long arch_atomic64_fetch_or(long long i, atomic64_t *v)
{
long long old, c = 0;
- while ((old = atomic64_cmpxchg(v, c, c | i)) != c)
+ while ((old = arch_atomic64_cmpxchg(v, c, c | i)) != c)
c = old;
return old;
}
-static inline void atomic64_xor(long long i, atomic64_t *v)
+static inline void arch_atomic64_xor(long long i, atomic64_t *v)
{
long long old, c = 0;
- while ((old = atomic64_cmpxchg(v, c, c ^ i)) != c)
+ while ((old = arch_atomic64_cmpxchg(v, c, c ^ i)) != c)
c = old;
}
-static inline long long atomic64_fetch_xor(long long i, atomic64_t *v)
+static inline long long arch_atomic64_fetch_xor(long long i, atomic64_t *v)
{
long long old, c = 0;
- while ((old = atomic64_cmpxchg(v, c, c ^ i)) != c)
+ while ((old = arch_atomic64_cmpxchg(v, c, c ^ i)) != c)
c = old;
return old;
}
-static inline long long atomic64_fetch_add(long long i, atomic64_t *v)
+static inline long long arch_atomic64_fetch_add(long long i, atomic64_t *v)
{
long long old, c = 0;
- while ((old = atomic64_cmpxchg(v, c, c + i)) != c)
+ while ((old = arch_atomic64_cmpxchg(v, c, c + i)) != c)
c = old;
return old;
}
-#define atomic64_fetch_sub(i, v) atomic64_fetch_add(-(i), (v))
+#define arch_atomic64_fetch_sub(i, v) arch_atomic64_fetch_add(-(i), (v))
#endif /* _ASM_X86_ATOMIC64_32_H */
diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h
index 738495caf05f..6106b59d3260 100644
--- a/arch/x86/include/asm/atomic64_64.h
+++ b/arch/x86/include/asm/atomic64_64.h
@@ -11,37 +11,37 @@
#define ATOMIC64_INIT(i) { (i) }
/**
- * atomic64_read - read atomic64 variable
+ * arch_atomic64_read - read atomic64 variable
* @v: pointer of type atomic64_t
*
* Atomically reads the value of @v.
* Doesn't imply a read memory barrier.
*/
-static inline long atomic64_read(const atomic64_t *v)
+static inline long arch_atomic64_read(const atomic64_t *v)
{
return READ_ONCE((v)->counter);
}
/**
- * atomic64_set - set atomic64 variable
+ * arch_atomic64_set - set atomic64 variable
* @v: pointer to type atomic64_t
* @i: required value
*
* Atomically sets the value of @v to @i.
*/
-static inline void atomic64_set(atomic64_t *v, long i)
+static inline void arch_atomic64_set(atomic64_t *v, long i)
{
WRITE_ONCE(v->counter, i);
}
/**
- * atomic64_add - add integer to atomic64 variable
+ * arch_atomic64_add - add integer to atomic64 variable
* @i: integer value to add
* @v: pointer to type atomic64_t
*
* Atomically adds @i to @v.
*/
-static __always_inline void atomic64_add(long i, atomic64_t *v)
+static __always_inline void arch_atomic64_add(long i, atomic64_t *v)
{
asm volatile(LOCK_PREFIX "addq %1,%0"
: "=m" (v->counter)
@@ -49,13 +49,13 @@ static __always_inline void atomic64_add(long i, atomic64_t *v)
}
/**
- * atomic64_sub - subtract the atomic64 variable
+ * arch_atomic64_sub - subtract the atomic64 variable
* @i: integer value to subtract
* @v: pointer to type atomic64_t
*
* Atomically subtracts @i from @v.
*/
-static inline void atomic64_sub(long i, atomic64_t *v)
+static inline void arch_atomic64_sub(long i, atomic64_t *v)
{
asm volatile(LOCK_PREFIX "subq %1,%0"
: "=m" (v->counter)
@@ -63,7 +63,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
}
/**
- * atomic64_sub_and_test - subtract value from variable and test result
+ * arch_atomic64_sub_and_test - subtract value from variable and test result
* @i: integer value to subtract
* @v: pointer to type atomic64_t
*
@@ -71,18 +71,18 @@ static inline void atomic64_sub(long i, atomic64_t *v)
* true if the result is zero, or false for all
* other cases.
*/
-static inline bool atomic64_sub_and_test(long i, atomic64_t *v)
+static inline bool arch_atomic64_sub_and_test(long i, atomic64_t *v)
{
GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, "er", i, "%0", e);
}
/**
- * atomic64_inc - increment atomic64 variable
+ * arch_atomic64_inc - increment atomic64 variable
* @v: pointer to type atomic64_t
*
* Atomically increments @v by 1.
*/
-static __always_inline void atomic64_inc(atomic64_t *v)
+static __always_inline void arch_atomic64_inc(atomic64_t *v)
{
asm volatile(LOCK_PREFIX "incq %0"
: "=m" (v->counter)
@@ -90,12 +90,12 @@ static __always_inline void atomic64_inc(atomic64_t *v)
}
/**
- * atomic64_dec - decrement atomic64 variable
+ * arch_atomic64_dec - decrement atomic64 variable
* @v: pointer to type atomic64_t
*
* Atomically decrements @v by 1.
*/
-static __always_inline void atomic64_dec(atomic64_t *v)
+static __always_inline void arch_atomic64_dec(atomic64_t *v)
{
asm volatile(LOCK_PREFIX "decq %0"
: "=m" (v->counter)
@@ -103,33 +103,33 @@ static __always_inline void atomic64_dec(atomic64_t *v)
}
/**
- * atomic64_dec_and_test - decrement and test
+ * arch_atomic64_dec_and_test - decrement and test
* @v: pointer to type atomic64_t
*
* Atomically decrements @v by 1 and
* returns true if the result is 0, or false for all other
* cases.
*/
-static inline bool atomic64_dec_and_test(atomic64_t *v)
+static inline bool arch_atomic64_dec_and_test(atomic64_t *v)
{
GEN_UNARY_RMWcc(LOCK_PREFIX "decq", v->counter, "%0", e);
}
/**
- * atomic64_inc_and_test - increment and test
+ * arch_atomic64_inc_and_test - increment and test
* @v: pointer to type atomic64_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
-static inline bool atomic64_inc_and_test(atomic64_t *v)
+static inline bool arch_atomic64_inc_and_test(atomic64_t *v)
{
GEN_UNARY_RMWcc(LOCK_PREFIX "incq", v->counter, "%0", e);
}
/**
- * atomic64_add_negative - add and test if negative
+ * arch_atomic64_add_negative - add and test if negative
* @i: integer value to add
* @v: pointer to type atomic64_t
*
@@ -137,59 +137,59 @@ static inline bool atomic64_inc_and_test(atomic64_t *v)
* if the result is negative, or false when
* result is greater than or equal to zero.
*/
-static inline bool atomic64_add_negative(long i, atomic64_t *v)
+static inline bool arch_atomic64_add_negative(long i, atomic64_t *v)
{
GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, "er", i, "%0", s);
}
/**
- * atomic64_add_return - add and return
+ * arch_atomic64_add_return - add and return
* @i: integer value to add
* @v: pointer to type atomic64_t
*
* Atomically adds @i to @v and returns @i + @v
*/
-static __always_inline long atomic64_add_return(long i, atomic64_t *v)
+static __always_inline long arch_atomic64_add_return(long i, atomic64_t *v)
{
return i + xadd(&v->counter, i);
}
-static inline long atomic64_sub_return(long i, atomic64_t *v)
+static inline long arch_atomic64_sub_return(long i, atomic64_t *v)
{
- return atomic64_add_return(-i, v);
+ return arch_atomic64_add_return(-i, v);
}
-static inline long atomic64_fetch_add(long i, atomic64_t *v)
+static inline long arch_atomic64_fetch_add(long i, atomic64_t *v)
{
return xadd(&v->counter, i);
}
-static inline long atomic64_fetch_sub(long i, atomic64_t *v)
+static inline long arch_atomic64_fetch_sub(long i, atomic64_t *v)
{
return xadd(&v->counter, -i);
}
-#define atomic64_inc_return(v) (atomic64_add_return(1, (v)))
-#define atomic64_dec_return(v) (atomic64_sub_return(1, (v)))
+#define arch_atomic64_inc_return(v) (arch_atomic64_add_return(1, (v)))
+#define arch_atomic64_dec_return(v) (arch_atomic64_sub_return(1, (v)))
-static inline long atomic64_cmpxchg(atomic64_t *v, long old, long new)
+static inline long arch_atomic64_cmpxchg(atomic64_t *v, long old, long new)
{
- return cmpxchg(&v->counter, old, new);
+ return arch_cmpxchg(&v->counter, old, new);
}
-#define atomic64_try_cmpxchg atomic64_try_cmpxchg
-static __always_inline bool atomic64_try_cmpxchg(atomic64_t *v, s64 *old, long new)
+#define arch_atomic64_try_cmpxchg arch_atomic64_try_cmpxchg
+static __always_inline bool arch_atomic64_try_cmpxchg(atomic64_t *v, s64 *old, long new)
{
return try_cmpxchg(&v->counter, old, new);
}
-static inline long atomic64_xchg(atomic64_t *v, long new)
+static inline long arch_atomic64_xchg(atomic64_t *v, long new)
{
return xchg(&v->counter, new);
}
/**
- * atomic64_add_unless - add unless the number is a given value
+ * arch_atomic64_add_unless - add unless the number is a given value
* @v: pointer of type atomic64_t
* @a: the amount to add to v...
* @u: ...unless v is equal to u.
@@ -197,37 +197,37 @@ static inline long atomic64_xchg(atomic64_t *v, long new)
* Atomically adds @a to @v, so long as it was not @u.
* Returns the old value of @v.
*/
-static inline bool atomic64_add_unless(atomic64_t *v, long a, long u)
+static inline bool arch_atomic64_add_unless(atomic64_t *v, long a, long u)
{
- s64 c = atomic64_read(v);
+ s64 c = arch_atomic64_read(v);
do {
if (unlikely(c == u))
return false;
- } while (!atomic64_try_cmpxchg(v, &c, c + a));
+ } while (!arch_atomic64_try_cmpxchg(v, &c, c + a));
return true;
}
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+#define arch_atomic64_inc_not_zero(v) arch_atomic64_add_unless((v), 1, 0)
/*
- * atomic64_dec_if_positive - decrement by 1 if old value positive
+ * arch_atomic64_dec_if_positive - decrement by 1 if old value positive
* @v: pointer of type atomic_t
*
* The function returns the old value of *v minus 1, even if
* the atomic variable, v, was not decremented.
*/
-static inline long atomic64_dec_if_positive(atomic64_t *v)
+static inline long arch_atomic64_dec_if_positive(atomic64_t *v)
{
- s64 dec, c = atomic64_read(v);
+ s64 dec, c = arch_atomic64_read(v);
do {
dec = c - 1;
if (unlikely(dec < 0))
break;
- } while (!atomic64_try_cmpxchg(v, &c, dec));
+ } while (!arch_atomic64_try_cmpxchg(v, &c, dec));
return dec;
}
-static inline void atomic64_and(long i, atomic64_t *v)
+static inline void arch_atomic64_and(long i, atomic64_t *v)
{
asm volatile(LOCK_PREFIX "andq %1,%0"
: "+m" (v->counter)
@@ -235,16 +235,16 @@ static inline void atomic64_and(long i, atomic64_t *v)
: "memory");
}
-static inline long atomic64_fetch_and(long i, atomic64_t *v)
+static inline long arch_atomic64_fetch_and(long i, atomic64_t *v)
{
- s64 val = atomic64_read(v);
+ s64 val = arch_atomic64_read(v);
do {
- } while (!atomic64_try_cmpxchg(v, &val, val & i));
+ } while (!arch_atomic64_try_cmpxchg(v, &val, val & i));
return val;
}
-static inline void atomic64_or(long i, atomic64_t *v)
+static inline void arch_atomic64_or(long i, atomic64_t *v)
{
asm volatile(LOCK_PREFIX "orq %1,%0"
: "+m" (v->counter)
@@ -252,16 +252,16 @@ static inline void atomic64_or(long i, atomic64_t *v)
: "memory");
}
-static inline long atomic64_fetch_or(long i, atomic64_t *v)
+static inline long arch_atomic64_fetch_or(long i, atomic64_t *v)
{
- s64 val = atomic64_read(v);
+ s64 val = arch_atomic64_read(v);
do {
- } while (!atomic64_try_cmpxchg(v, &val, val | i));
+ } while (!arch_atomic64_try_cmpxchg(v, &val, val | i));
return val;
}
-static inline void atomic64_xor(long i, atomic64_t *v)
+static inline void arch_atomic64_xor(long i, atomic64_t *v)
{
asm volatile(LOCK_PREFIX "xorq %1,%0"
: "+m" (v->counter)
@@ -269,12 +269,12 @@ static inline void atomic64_xor(long i, atomic64_t *v)
: "memory");
}
-static inline long atomic64_fetch_xor(long i, atomic64_t *v)
+static inline long arch_atomic64_fetch_xor(long i, atomic64_t *v)
{
- s64 val = atomic64_read(v);
+ s64 val = arch_atomic64_read(v);
do {
- } while (!atomic64_try_cmpxchg(v, &val, val ^ i));
+ } while (!arch_atomic64_try_cmpxchg(v, &val, val ^ i));
return val;
}
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
index e1259f043ae9..042b5e892ed1 100644
--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -52,11 +52,7 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
#define barrier_nospec() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
"lfence", X86_FEATURE_LFENCE_RDTSC)
-#ifdef CONFIG_X86_PPRO_FENCE
-#define dma_rmb() rmb()
-#else
#define dma_rmb() barrier()
-#endif
#define dma_wmb() barrier()
#ifdef CONFIG_X86_32
@@ -68,30 +64,6 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
#define __smp_wmb() barrier()
#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
-#if defined(CONFIG_X86_PPRO_FENCE)
-
-/*
- * For this option x86 doesn't have a strong TSO memory
- * model and we should fall back to full barriers.
- */
-
-#define __smp_store_release(p, v) \
-do { \
- compiletime_assert_atomic_type(*p); \
- __smp_mb(); \
- WRITE_ONCE(*p, v); \
-} while (0)
-
-#define __smp_load_acquire(p) \
-({ \
- typeof(*p) ___p1 = READ_ONCE(*p); \
- compiletime_assert_atomic_type(*p); \
- __smp_mb(); \
- ___p1; \
-})
-
-#else /* regular x86 TSO memory ordering */
-
#define __smp_store_release(p, v) \
do { \
compiletime_assert_atomic_type(*p); \
@@ -107,8 +79,6 @@ do { \
___p1; \
})
-#endif
-
/* Atomic operations are already serializing on x86 */
#define __smp_mb__before_atomic() barrier()
#define __smp_mb__after_atomic() barrier()
diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h
index 56bd436ed01b..e3efd8a06066 100644
--- a/arch/x86/include/asm/cmpxchg.h
+++ b/arch/x86/include/asm/cmpxchg.h
@@ -145,13 +145,13 @@ extern void __add_wrong_size(void)
# include <asm/cmpxchg_64.h>
#endif
-#define cmpxchg(ptr, old, new) \
+#define arch_cmpxchg(ptr, old, new) \
__cmpxchg(ptr, old, new, sizeof(*(ptr)))
-#define sync_cmpxchg(ptr, old, new) \
+#define arch_sync_cmpxchg(ptr, old, new) \
__sync_cmpxchg(ptr, old, new, sizeof(*(ptr)))
-#define cmpxchg_local(ptr, old, new) \
+#define arch_cmpxchg_local(ptr, old, new) \
__cmpxchg_local(ptr, old, new, sizeof(*(ptr)))
@@ -221,7 +221,7 @@ extern void __add_wrong_size(void)
#define __try_cmpxchg(ptr, pold, new, size) \
__raw_try_cmpxchg((ptr), (pold), (new), (size), LOCK_PREFIX)
-#define try_cmpxchg(ptr, pold, new) \
+#define try_cmpxchg(ptr, pold, new) \
__try_cmpxchg((ptr), (pold), (new), sizeof(*(ptr)))
/*
@@ -250,10 +250,10 @@ extern void __add_wrong_size(void)
__ret; \
})
-#define cmpxchg_double(p1, p2, o1, o2, n1, n2) \
+#define arch_cmpxchg_double(p1, p2, o1, o2, n1, n2) \
__cmpxchg_double(LOCK_PREFIX, p1, p2, o1, o2, n1, n2)
-#define cmpxchg_double_local(p1, p2, o1, o2, n1, n2) \
+#define arch_cmpxchg_double_local(p1, p2, o1, o2, n1, n2) \
__cmpxchg_double(, p1, p2, o1, o2, n1, n2)
#endif /* ASM_X86_CMPXCHG_H */
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index 1732704f0445..1a2eafca7038 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -36,10 +36,10 @@ static inline void set_64bit(volatile u64 *ptr, u64 value)
}
#ifdef CONFIG_X86_CMPXCHG64
-#define cmpxchg64(ptr, o, n) \
+#define arch_cmpxchg64(ptr, o, n) \
((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
(unsigned long long)(n)))
-#define cmpxchg64_local(ptr, o, n) \
+#define arch_cmpxchg64_local(ptr, o, n) \
((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \
(unsigned long long)(n)))
#endif
@@ -76,7 +76,7 @@ static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
* to simulate the cmpxchg8b on the 80386 and 80486 CPU.
*/
-#define cmpxchg64(ptr, o, n) \
+#define arch_cmpxchg64(ptr, o, n) \
({ \
__typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) __old = (o); \
@@ -93,7 +93,7 @@ static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
__ret; })
-#define cmpxchg64_local(ptr, o, n) \
+#define arch_cmpxchg64_local(ptr, o, n) \
({ \
__typeof__(*(ptr)) __ret; \
__typeof__(*(ptr)) __old = (o); \
diff --git a/arch/x86/include/asm/cmpxchg_64.h b/arch/x86/include/asm/cmpxchg_64.h
index 03cad196a301..bfca3b346c74 100644
--- a/arch/x86/include/asm/cmpxchg_64.h
+++ b/arch/x86/include/asm/cmpxchg_64.h
@@ -7,13 +7,13 @@ static inline void set_64bit(volatile u64 *ptr, u64 val)
*ptr = val;
}
-#define cmpxchg64(ptr, o, n) \
+#define arch_cmpxchg64(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg((ptr), (o), (n)); \
})
-#define cmpxchg64_local(ptr, o, n) \
+#define arch_cmpxchg64_local(ptr, o, n) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg_local((ptr), (o), (n)); \
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 736771c9822e..b27da9602a6d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -140,7 +140,6 @@ extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit);
#define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit)
-#if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS)
/*
* Static testing of CPU features. Used the same as boot_cpu_has().
* These will statically patch the target code for additional
@@ -196,13 +195,6 @@ t_no:
boot_cpu_has(bit) : \
_static_cpu_has(bit) \
)
-#else
-/*
- * Fall back to dynamic for gcc versions which don't support asm goto. Should be
- * a minority now anyway.
- */
-#define static_cpu_has(bit) boot_cpu_has(bit)
-#endif
#define cpu_has_bug(c, bit) cpu_has(c, (bit))
#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index f41079da38c5..d554c11e01ff 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -316,6 +316,7 @@
#define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */
#define X86_FEATURE_AVX512_VNNI (16*32+11) /* Vector Neural Network Instructions */
#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
+#define X86_FEATURE_TME (16*32+13) /* Intel Total Memory Encryption */
#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
@@ -328,6 +329,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
diff --git a/arch/x86/include/asm/device.h b/arch/x86/include/asm/device.h
index 5e12c63b47aa..a8f6c809d9b1 100644
--- a/arch/x86/include/asm/device.h
+++ b/arch/x86/include/asm/device.h
@@ -6,6 +6,9 @@ struct dev_archdata {
#if defined(CONFIG_INTEL_IOMMU) || defined(CONFIG_AMD_IOMMU)
void *iommu; /* hook for IOMMU specific extension */
#endif
+#ifdef CONFIG_STA2X11
+ bool is_sta2x11;
+#endif
};
#if defined(CONFIG_X86_DEV_DMA_OPS) && defined(CONFIG_PCI_DOMAINS)
diff --git a/arch/x86/include/asm/dma-direct.h b/arch/x86/include/asm/dma-direct.h
index 1295bc622ebe..1a19251eaac9 100644
--- a/arch/x86/include/asm/dma-direct.h
+++ b/arch/x86/include/asm/dma-direct.h
@@ -2,29 +2,8 @@
#ifndef ASM_X86_DMA_DIRECT_H
#define ASM_X86_DMA_DIRECT_H 1
-#include <linux/mem_encrypt.h>
-
-#ifdef CONFIG_X86_DMA_REMAP /* Platform code defines bridge-specific code */
bool dma_capable(struct device *dev, dma_addr_t addr, size_t size);
-dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
-phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
-#else
-static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
-{
- if (!dev->dma_mask)
- return 0;
-
- return addr + size - 1 <= *dev->dma_mask;
-}
-
-static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
-{
- return __sme_set(paddr);
-}
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr);
-static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
-{
- return __sme_clr(daddr);
-}
-#endif /* CONFIG_X86_DMA_REMAP */
#endif /* ASM_X86_DMA_DIRECT_H */
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index 6277c83c0eb1..89ce4bfd241f 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -36,37 +36,4 @@ int arch_dma_supported(struct device *dev, u64 mask);
bool arch_dma_alloc_attrs(struct device **dev, gfp_t *gfp);
#define arch_dma_alloc_attrs arch_dma_alloc_attrs
-extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_addr, gfp_t flag,
- unsigned long attrs);
-
-extern void dma_generic_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_addr,
- unsigned long attrs);
-
-static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
- gfp_t gfp)
-{
- unsigned long dma_mask = 0;
-
- dma_mask = dev->coherent_dma_mask;
- if (!dma_mask)
- dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);
-
- return dma_mask;
-}
-
-static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
-{
- unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
-
- if (dma_mask <= DMA_BIT_MASK(24))
- gfp |= GFP_DMA;
-#ifdef CONFIG_X86_64
- if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
- gfp |= GFP_DMA32;
-#endif
- return gfp;
-}
-
#endif
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index a399c1ebf6f0..cec5fae23eb3 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -7,6 +7,7 @@
#include <asm/processor-flags.h>
#include <asm/tlb.h>
#include <asm/nospec-branch.h>
+#include <asm/mmu_context.h>
/*
* We map the EFI regions needed for runtime services non-contiguously,
@@ -69,14 +70,13 @@ extern asmlinkage u64 efi_call(void *fp, ...);
#define efi_call_phys(f, args...) efi_call((f), args)
/*
- * Scratch space used for switching the pagetable in the EFI stub
+ * struct efi_scratch - Scratch space used while switching to/from efi_mm
+ * @phys_stack: stack used during EFI Mixed Mode
+ * @prev_mm: store/restore stolen mm_struct while switching to/from efi_mm
*/
struct efi_scratch {
- u64 r15;
- u64 prev_cr3;
- pgd_t *efi_pgt;
- bool use_pgd;
- u64 phys_stack;
+ u64 phys_stack;
+ struct mm_struct *prev_mm;
} __packed;
#define arch_efi_call_virt_setup() \
@@ -86,11 +86,8 @@ struct efi_scratch {
__kernel_fpu_begin(); \
firmware_restrict_branch_speculation_start(); \
\
- if (efi_scratch.use_pgd) { \
- efi_scratch.prev_cr3 = __read_cr3(); \
- write_cr3((unsigned long)efi_scratch.efi_pgt); \
- __flush_tlb_all(); \
- } \
+ if (!efi_enabled(EFI_OLD_MEMMAP)) \
+ efi_switch_mm(&efi_mm); \
})
#define arch_efi_call_virt(p, f, args...) \
@@ -98,10 +95,8 @@ struct efi_scratch {
#define arch_efi_call_virt_teardown() \
({ \
- if (efi_scratch.use_pgd) { \
- write_cr3(efi_scratch.prev_cr3); \
- __flush_tlb_all(); \
- } \
+ if (!efi_enabled(EFI_OLD_MEMMAP)) \
+ efi_switch_mm(efi_scratch.prev_mm); \
\
firmware_restrict_branch_speculation_end(); \
__kernel_fpu_end(); \
@@ -144,6 +139,7 @@ extern void __init efi_dump_pagetable(void);
extern void __init efi_apply_memmap_quirks(void);
extern int __init efi_reuse_config(u64 tables, int nr_tables);
extern void efi_delete_dummy_variable(void);
+extern void efi_switch_mm(struct mm_struct *mm);
struct efi_setup_data {
u64 fw_vendor;
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 2851077b6051..32e666e1231e 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -36,6 +36,7 @@ extern asmlinkage void kvm_posted_intr_wakeup_ipi(void);
extern asmlinkage void kvm_posted_intr_nested_ipi(void);
extern asmlinkage void error_interrupt(void);
extern asmlinkage void irq_work_interrupt(void);
+extern asmlinkage void uv_bau_message_intr1(void);
extern asmlinkage void spurious_interrupt(void);
extern asmlinkage void thermal_interrupt(void);
diff --git a/arch/x86/include/asm/intel_pconfig.h b/arch/x86/include/asm/intel_pconfig.h
new file mode 100644
index 000000000000..3cb002b1d0f9
--- /dev/null
+++ b/arch/x86/include/asm/intel_pconfig.h
@@ -0,0 +1,65 @@
+#ifndef _ASM_X86_INTEL_PCONFIG_H
+#define _ASM_X86_INTEL_PCONFIG_H
+
+#include <asm/asm.h>
+#include <asm/processor.h>
+
+enum pconfig_target {
+ INVALID_TARGET = 0,
+ MKTME_TARGET = 1,
+ PCONFIG_TARGET_NR
+};
+
+int pconfig_target_supported(enum pconfig_target target);
+
+enum pconfig_leaf {
+ MKTME_KEY_PROGRAM = 0,
+ PCONFIG_LEAF_INVALID,
+};
+
+#define PCONFIG ".byte 0x0f, 0x01, 0xc5"
+
+/* Defines and structure for MKTME_KEY_PROGRAM of PCONFIG instruction */
+
+/* mktme_key_program::keyid_ctrl COMMAND, bits [7:0] */
+#define MKTME_KEYID_SET_KEY_DIRECT 0
+#define MKTME_KEYID_SET_KEY_RANDOM 1
+#define MKTME_KEYID_CLEAR_KEY 2
+#define MKTME_KEYID_NO_ENCRYPT 3
+
+/* mktme_key_program::keyid_ctrl ENC_ALG, bits [23:8] */
+#define MKTME_AES_XTS_128 (1 << 8)
+
+/* Return codes from the PCONFIG MKTME_KEY_PROGRAM */
+#define MKTME_PROG_SUCCESS 0
+#define MKTME_INVALID_PROG_CMD 1
+#define MKTME_ENTROPY_ERROR 2
+#define MKTME_INVALID_KEYID 3
+#define MKTME_INVALID_ENC_ALG 4
+#define MKTME_DEVICE_BUSY 5
+
+/* Hardware requires the structure to be 256 byte alinged. Otherwise #GP(0). */
+struct mktme_key_program {
+ u16 keyid;
+ u32 keyid_ctrl;
+ u8 __rsvd[58];
+ u8 key_field_1[64];
+ u8 key_field_2[64];
+} __packed __aligned(256);
+
+static inline int mktme_key_program(struct mktme_key_program *key_program)
+{
+ unsigned long rax = MKTME_KEY_PROGRAM;
+
+ if (!pconfig_target_supported(MKTME_TARGET))
+ return -ENXIO;
+
+ asm volatile(PCONFIG
+ : "=a" (rax), "=b" (key_program)
+ : "0" (rax), "1" (key_program)
+ : "memory", "cc");
+
+ return rax;
+}
+
+#endif /* _ASM_X86_INTEL_PCONFIG_H */
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 95e948627fd0..f6e5b9375d8c 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -232,21 +232,6 @@ extern void set_iounmap_nonlazy(void);
*/
#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
-/*
- * Cache management
- *
- * This needed for two cases
- * 1. Out of order aware processors
- * 2. Accidentally out of order processors (PPro errata #51)
- */
-
-static inline void flush_write_buffers(void)
-{
-#if defined(CONFIG_X86_PPRO_FENCE)
- asm volatile("lock; addl $0,0(%%esp)": : :"memory");
-#endif
-}
-
#endif /* __KERNEL__ */
extern void native_io_delay(void);
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index a8834dd546cd..fd20a2334885 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -183,16 +183,17 @@ extern void disable_ioapic_support(void);
extern void __init io_apic_init_mappings(void);
extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
-extern void native_disable_io_apic(void);
+extern void native_restore_boot_irq_mode(void);
static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
{
- return x86_io_apic_ops.read(apic, reg);
+ return x86_apic_ops.io_apic_read(apic, reg);
}
extern void setup_IO_APIC(void);
extern void enable_IO_APIC(void);
-extern void disable_IO_APIC(void);
+extern void clear_IO_APIC(void);
+extern void restore_boot_irq_mode(void);
extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
extern void print_IO_APICs(void);
#else /* !CONFIG_X86_IO_APIC */
@@ -228,10 +229,11 @@ static inline void mp_save_irq(struct mpc_intsrc *m) { }
static inline void disable_ioapic_support(void) { }
static inline void io_apic_init_mappings(void) { }
#define native_io_apic_read NULL
-#define native_disable_io_apic NULL
+#define native_restore_boot_irq_mode NULL
static inline void setup_IO_APIC(void) { }
static inline void enable_IO_APIC(void) { }
+static inline void restore_boot_irq_mode(void) { }
#endif
diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h
index 1e5d5d92eb40..baedab8ac538 100644
--- a/arch/x86/include/asm/iommu.h
+++ b/arch/x86/include/asm/iommu.h
@@ -2,13 +2,10 @@
#ifndef _ASM_X86_IOMMU_H
#define _ASM_X86_IOMMU_H
-extern const struct dma_map_ops nommu_dma_ops;
extern int force_iommu, no_iommu;
extern int iommu_detected;
extern int iommu_pass_through;
-int x86_dma_supported(struct device *dev, u64 mask);
-
/* 10 seconds */
#define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000)
diff --git a/arch/x86/include/asm/jailhouse_para.h b/arch/x86/include/asm/jailhouse_para.h
index 875b54376689..b885a961a150 100644
--- a/arch/x86/include/asm/jailhouse_para.h
+++ b/arch/x86/include/asm/jailhouse_para.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL2.0 */
/*
- * Jailhouse paravirt_ops implementation
+ * Jailhouse paravirt detection
*
* Copyright (c) Siemens AG, 2015-2017
*
diff --git a/arch/x86/include/asm/kaslr.h b/arch/x86/include/asm/kaslr.h
index 460991e3b529..db7ba2feb947 100644
--- a/arch/x86/include/asm/kaslr.h
+++ b/arch/x86/include/asm/kaslr.h
@@ -5,10 +5,6 @@
unsigned long kaslr_get_random_long(const char *purpose);
#ifdef CONFIG_RANDOMIZE_MEMORY
-extern unsigned long page_offset_base;
-extern unsigned long vmalloc_base;
-extern unsigned long vmemmap_base;
-
void kernel_randomize_memory(void);
#else
static inline void kernel_randomize_memory(void) { }
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 96ea4b5ba658..8c7b3e5a2d01 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -138,58 +138,6 @@ struct mce_log_buffer {
struct mce entry[MCE_LOG_LEN];
};
-struct mca_config {
- bool dont_log_ce;
- bool cmci_disabled;
- bool lmce_disabled;
- bool ignore_ce;
- bool disabled;
- bool ser;
- bool recovery;
- bool bios_cmci_threshold;
- u8 banks;
- s8 bootlog;
- int tolerant;
- int monarch_timeout;
- int panic_timeout;
- u32 rip_msr;
-};
-
-struct mce_vendor_flags {
- /*
- * Indicates that overflow conditions are not fatal, when set.
- */
- __u64 overflow_recov : 1,
-
- /*
- * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
- * Recovery. It indicates support for data poisoning in HW and deferred
- * error interrupts.
- */
- succor : 1,
-
- /*
- * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
- * the register space for each MCA bank and also increases number of
- * banks. Also, to accommodate the new banks and registers, the MCA
- * register space is moved to a new MSR range.
- */
- smca : 1,
-
- __reserved_0 : 61;
-};
-
-struct mca_msr_regs {
- u32 (*ctl) (int bank);
- u32 (*status) (int bank);
- u32 (*addr) (int bank);
- u32 (*misc) (int bank);
-};
-
-extern struct mce_vendor_flags mce_flags;
-
-extern struct mca_msr_regs msr_ops;
-
enum mce_notifier_prios {
MCE_PRIO_FIRST = INT_MAX,
MCE_PRIO_SRAO = INT_MAX - 1,
@@ -346,6 +294,7 @@ enum smca_bank_types {
SMCA_IF, /* Instruction Fetch */
SMCA_L2_CACHE, /* L2 Cache */
SMCA_DE, /* Decoder Unit */
+ SMCA_RESERVED, /* Reserved */
SMCA_EX, /* Execution Unit */
SMCA_FP, /* Floating Point */
SMCA_L3_CACHE, /* L3 Cache */
diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h
index 22c5f3e6f820..c0643831706e 100644
--- a/arch/x86/include/asm/mem_encrypt.h
+++ b/arch/x86/include/asm/mem_encrypt.h
@@ -22,6 +22,7 @@
#ifdef CONFIG_AMD_MEM_ENCRYPT
extern u64 sme_me_mask;
+extern bool sev_enabled;
void sme_encrypt_execute(unsigned long encrypted_kernel_vaddr,
unsigned long decrypted_kernel_vaddr,
@@ -48,8 +49,6 @@ int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size);
/* Architecture __weak replacement functions */
void __init mem_encrypt_init(void);
-void swiotlb_set_mem_attributes(void *vaddr, unsigned long size);
-
bool sme_active(void);
bool sev_active(void);
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 7fb1047d61c7..2b7cc5397f80 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -6,20 +6,6 @@
#include <linux/earlycpio.h>
#include <linux/initrd.h>
-#define native_rdmsr(msr, val1, val2) \
-do { \
- u64 __val = __rdmsr((msr)); \
- (void)((val1) = (u32)__val); \
- (void)((val2) = (u32)(__val >> 32)); \
-} while (0)
-
-#define native_wrmsr(msr, low, high) \
- __wrmsr(msr, low, high)
-
-#define native_wrmsrl(msr, val) \
- __wrmsr((msr), (u32)((u64)(val)), \
- (u32)((u64)(val) >> 32))
-
struct ucode_patch {
struct list_head plist;
void *data; /* Intel uses only this one */
@@ -39,6 +25,7 @@ struct device;
enum ucode_state {
UCODE_OK = 0,
+ UCODE_NEW,
UCODE_UPDATED,
UCODE_NFOUND,
UCODE_ERROR,
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 1de72ce514cd..57e3785d0d26 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -24,11 +24,12 @@ static inline void paravirt_activate_mm(struct mm_struct *prev,
#endif /* !CONFIG_PARAVIRT */
#ifdef CONFIG_PERF_EVENTS
-extern struct static_key rdpmc_always_available;
+
+DECLARE_STATIC_KEY_FALSE(rdpmc_always_available_key);
static inline void load_mm_cr4(struct mm_struct *mm)
{
- if (static_key_false(&rdpmc_always_available) ||
+ if (static_branch_unlikely(&rdpmc_always_available_key) ||
atomic_read(&mm->context.perf_rdpmc_allowed))
cr4_set_bits(X86_CR4_PCE);
else
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 30df295f6d94..04addd6e0a4a 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -108,6 +108,20 @@ static inline void notrace __wrmsr(unsigned int msr, u32 low, u32 high)
: : "c" (msr), "a"(low), "d" (high) : "memory");
}
+#define native_rdmsr(msr, val1, val2) \
+do { \
+ u64 __val = __rdmsr((msr)); \
+ (void)((val1) = (u32)__val); \
+ (void)((val2) = (u32)(__val >> 32)); \
+} while (0)
+
+#define native_wrmsr(msr, low, high) \
+ __wrmsr(msr, low, high)
+
+#define native_wrmsrl(msr, val) \
+ __wrmsr((msr), (u32)((u64)(val)), \
+ (u32)((u64)(val) >> 32))
+
static inline unsigned long long native_read_msr(unsigned int msr)
{
unsigned long long val;
@@ -218,9 +232,6 @@ static __always_inline unsigned long long rdtsc_ordered(void)
return rdtsc();
}
-/* Deprecated, keep it for a cycle for easier merging: */
-#define rdtscll(now) do { (now) = rdtsc_ordered(); } while (0)
-
static inline unsigned long long native_read_pmc(int counter)
{
DECLARE_ARGS(val, low, high);
diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
index d0dabeae0505..f928ad9b143f 100644
--- a/arch/x86/include/asm/nospec-branch.h
+++ b/arch/x86/include/asm/nospec-branch.h
@@ -183,7 +183,10 @@
* otherwise we'll run out of registers. We don't care about CET
* here, anyway.
*/
-# define CALL_NOSPEC ALTERNATIVE("call *%[thunk_target]\n", \
+# define CALL_NOSPEC \
+ ALTERNATIVE( \
+ ANNOTATE_RETPOLINE_SAFE \
+ "call *%[thunk_target]\n", \
" jmp 904f;\n" \
" .align 16\n" \
"901: call 903f;\n" \
diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h
index d652a3808065..939b1cff4a7b 100644
--- a/arch/x86/include/asm/page_64.h
+++ b/arch/x86/include/asm/page_64.h
@@ -11,6 +11,10 @@
extern unsigned long max_pfn;
extern unsigned long phys_base;
+extern unsigned long page_offset_base;
+extern unsigned long vmalloc_base;
+extern unsigned long vmemmap_base;
+
static inline unsigned long __phys_addr_nodebug(unsigned long x)
{
unsigned long y = x - __START_KERNEL_map;
@@ -47,7 +51,7 @@ static inline void clear_page(void *page)
clear_page_erms, X86_FEATURE_ERMS,
"=D" (page),
"0" (page)
- : "memory", "rax", "rcx");
+ : "cc", "memory", "rax", "rcx");
}
void copy_page(void *to, void *from);
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index e1407312c412..2c5a966dc222 100644
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -37,26 +37,24 @@
* hypervisor to fit. Choosing 16 slots here is arbitrary, but it's
* what Xen requires.
*/
-#ifdef CONFIG_X86_5LEVEL
-#define __PAGE_OFFSET_BASE _AC(0xff10000000000000, UL)
-#else
-#define __PAGE_OFFSET_BASE _AC(0xffff880000000000, UL)
-#endif
+#define __PAGE_OFFSET_BASE_L5 _AC(0xff10000000000000, UL)
+#define __PAGE_OFFSET_BASE_L4 _AC(0xffff880000000000, UL)
-#ifdef CONFIG_RANDOMIZE_MEMORY
+#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
#define __PAGE_OFFSET page_offset_base
#else
-#define __PAGE_OFFSET __PAGE_OFFSET_BASE
-#endif /* CONFIG_RANDOMIZE_MEMORY */
+#define __PAGE_OFFSET __PAGE_OFFSET_BASE_L4
+#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
#define __START_KERNEL_map _AC(0xffffffff80000000, UL)
/* See Documentation/x86/x86_64/mm.txt for a description of the memory map. */
-#ifdef CONFIG_X86_5LEVEL
+
#define __PHYSICAL_MASK_SHIFT 52
-#define __VIRTUAL_MASK_SHIFT 56
+
+#ifdef CONFIG_X86_5LEVEL
+#define __VIRTUAL_MASK_SHIFT (pgtable_l5_enabled ? 56 : 47)
#else
-#define __PHYSICAL_MASK_SHIFT 46
#define __VIRTUAL_MASK_SHIFT 47
#endif
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index c83a2f418cea..9be2bf13825b 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -568,17 +568,22 @@ static inline p4dval_t p4d_val(p4d_t p4d)
return PVOP_CALLEE1(p4dval_t, pv_mmu_ops.p4d_val, p4d.p4d);
}
-static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
+static inline void __set_pgd(pgd_t *pgdp, pgd_t pgd)
{
- pgdval_t val = native_pgd_val(pgd);
-
- PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, val);
+ PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, native_pgd_val(pgd));
}
-static inline void pgd_clear(pgd_t *pgdp)
-{
- set_pgd(pgdp, __pgd(0));
-}
+#define set_pgd(pgdp, pgdval) do { \
+ if (pgtable_l5_enabled) \
+ __set_pgd(pgdp, pgdval); \
+ else \
+ set_p4d((p4d_t *)(pgdp), (p4d_t) { (pgdval).pgd }); \
+} while (0)
+
+#define pgd_clear(pgdp) do { \
+ if (pgtable_l5_enabled) \
+ set_pgd(pgdp, __pgd(0)); \
+} while (0)
#endif /* CONFIG_PGTABLE_LEVELS == 5 */
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index eb66fa9cd0fc..959d618dbb17 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -151,6 +151,8 @@ extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
phys_addr_t addr);
extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
+extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
+ int end, u64 addr);
extern struct list_head pci_mmcfg_list;
diff --git a/arch/x86/include/asm/pgalloc.h b/arch/x86/include/asm/pgalloc.h
index aff42e1da6ee..263c142a6a6c 100644
--- a/arch/x86/include/asm/pgalloc.h
+++ b/arch/x86/include/asm/pgalloc.h
@@ -167,6 +167,8 @@ static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
#if CONFIG_PGTABLE_LEVELS > 4
static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, p4d_t *p4d)
{
+ if (!pgtable_l5_enabled)
+ return;
paravirt_alloc_p4d(mm, __pa(p4d) >> PAGE_SHIFT);
set_pgd(pgd, __pgd(_PAGE_TABLE | __pa(p4d)));
}
@@ -191,7 +193,8 @@ extern void ___p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d);
static inline void __p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d,
unsigned long address)
{
- ___p4d_free_tlb(tlb, p4d);
+ if (pgtable_l5_enabled)
+ ___p4d_free_tlb(tlb, p4d);
}
#endif /* CONFIG_PGTABLE_LEVELS > 4 */
diff --git a/arch/x86/include/asm/pgtable-3level_types.h b/arch/x86/include/asm/pgtable-3level_types.h
index 876b4c77d983..6a59a6d0cc50 100644
--- a/arch/x86/include/asm/pgtable-3level_types.h
+++ b/arch/x86/include/asm/pgtable-3level_types.h
@@ -44,5 +44,6 @@ typedef union {
*/
#define PTRS_PER_PTE 512
+#define MAX_POSSIBLE_PHYSMEM_BITS 36
#endif /* _ASM_X86_PGTABLE_3LEVEL_DEFS_H */
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index b444d83cfc95..89d5c8886c85 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -65,7 +65,7 @@ extern pmdval_t early_pmd_flags;
#ifndef __PAGETABLE_P4D_FOLDED
#define set_pgd(pgdp, pgd) native_set_pgd(pgdp, pgd)
-#define pgd_clear(pgd) native_pgd_clear(pgd)
+#define pgd_clear(pgd) (pgtable_l5_enabled ? native_pgd_clear(pgd) : 0)
#endif
#ifndef set_p4d
@@ -859,6 +859,8 @@ static inline unsigned long p4d_index(unsigned long address)
#if CONFIG_PGTABLE_LEVELS > 4
static inline int pgd_present(pgd_t pgd)
{
+ if (!pgtable_l5_enabled)
+ return 1;
return pgd_flags(pgd) & _PAGE_PRESENT;
}
@@ -876,6 +878,8 @@ static inline unsigned long pgd_page_vaddr(pgd_t pgd)
/* to find an entry in a page-table-directory. */
static inline p4d_t *p4d_offset(pgd_t *pgd, unsigned long address)
{
+ if (!pgtable_l5_enabled)
+ return (p4d_t *)pgd;
return (p4d_t *)pgd_page_vaddr(*pgd) + p4d_index(address);
}
@@ -883,6 +887,9 @@ static inline int pgd_bad(pgd_t pgd)
{
unsigned long ignore_flags = _PAGE_USER;
+ if (!pgtable_l5_enabled)
+ return 0;
+
if (IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
ignore_flags |= _PAGE_NX;
@@ -891,6 +898,8 @@ static inline int pgd_bad(pgd_t pgd)
static inline int pgd_none(pgd_t pgd)
{
+ if (!pgtable_l5_enabled)
+ return 0;
/*
* There is no need to do a workaround for the KNL stray
* A/D bit erratum here. PGDs only point to page tables
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
index b3ec519e3982..88a056b01db4 100644
--- a/arch/x86/include/asm/pgtable_32.h
+++ b/arch/x86/include/asm/pgtable_32.h
@@ -34,6 +34,8 @@ static inline void check_pgt_cache(void) { }
void paging_init(void);
void sync_initial_page_table(void);
+static inline int pgd_large(pgd_t pgd) { return 0; }
+
/*
* Define this if things work differently on an i386 and an i486:
* it will (on an i486) warn about kernel memory accesses that are
diff --git a/arch/x86/include/asm/pgtable_32_types.h b/arch/x86/include/asm/pgtable_32_types.h
index 0777e18a1d23..e3225e83db7d 100644
--- a/arch/x86/include/asm/pgtable_32_types.h
+++ b/arch/x86/include/asm/pgtable_32_types.h
@@ -15,6 +15,8 @@
# include <asm/pgtable-2level_types.h>
#endif
+#define pgtable_l5_enabled 0
+
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE - 1))
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index 1149d2112b2e..877bc27718ae 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -218,29 +218,26 @@ static inline pgd_t pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd)
static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d)
{
-#if defined(CONFIG_PAGE_TABLE_ISOLATION) && !defined(CONFIG_X86_5LEVEL)
- p4dp->pgd = pti_set_user_pgd(&p4dp->pgd, p4d.pgd);
-#else
- *p4dp = p4d;
-#endif
+ pgd_t pgd;
+
+ if (pgtable_l5_enabled || !IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) {
+ *p4dp = p4d;
+ return;
+ }
+
+ pgd = native_make_pgd(native_p4d_val(p4d));
+ pgd = pti_set_user_pgd((pgd_t *)p4dp, pgd);
+ *p4dp = native_make_p4d(native_pgd_val(pgd));
}
static inline void native_p4d_clear(p4d_t *p4d)
{
-#ifdef CONFIG_X86_5LEVEL
native_set_p4d(p4d, native_make_p4d(0));
-#else
- native_set_p4d(p4d, (p4d_t) { .pgd = native_make_pgd(0)});
-#endif
}
static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
{
-#ifdef CONFIG_PAGE_TABLE_ISOLATION
*pgdp = pti_set_user_pgd(pgdp, pgd);
-#else
- *pgdp = pgd;
-#endif
}
static inline void native_pgd_clear(pgd_t *pgd)
diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
index 6b8f73dcbc2c..d5c21a382475 100644
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -20,6 +20,18 @@ typedef unsigned long pgprotval_t;
typedef struct { pteval_t pte; } pte_t;
+#ifdef CONFIG_X86_5LEVEL
+extern unsigned int __pgtable_l5_enabled;
+#ifndef pgtable_l5_enabled
+#define pgtable_l5_enabled cpu_feature_enabled(X86_FEATURE_LA57)
+#endif
+#else
+#define pgtable_l5_enabled 0
+#endif
+
+extern unsigned int pgdir_shift;
+extern unsigned int ptrs_per_p4d;
+
#endif /* !__ASSEMBLY__ */
#define SHARED_KERNEL_PMD 0
@@ -29,24 +41,28 @@ typedef struct { pteval_t pte; } pte_t;
/*
* PGDIR_SHIFT determines what a top-level page table entry can map
*/
-#define PGDIR_SHIFT 48
+#define PGDIR_SHIFT pgdir_shift
#define PTRS_PER_PGD 512
/*
* 4th level page in 5-level paging case
*/
-#define P4D_SHIFT 39
-#define PTRS_PER_P4D 512
-#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
-#define P4D_MASK (~(P4D_SIZE - 1))
+#define P4D_SHIFT 39
+#define MAX_PTRS_PER_P4D 512
+#define PTRS_PER_P4D ptrs_per_p4d
+#define P4D_SIZE (_AC(1, UL) << P4D_SHIFT)
+#define P4D_MASK (~(P4D_SIZE - 1))
+
+#define MAX_POSSIBLE_PHYSMEM_BITS 52
#else /* CONFIG_X86_5LEVEL */
/*
* PGDIR_SHIFT determines what a top-level page table entry can map
*/
-#define PGDIR_SHIFT 39
-#define PTRS_PER_PGD 512
+#define PGDIR_SHIFT 39
+#define PTRS_PER_PGD 512
+#define MAX_PTRS_PER_P4D 1
#endif /* CONFIG_X86_5LEVEL */
@@ -82,31 +98,33 @@ typedef struct { pteval_t pte; } pte_t;
* range must not overlap with anything except the KASAN shadow area, which
* is correct as KASAN disables KASLR.
*/
-#define MAXMEM _AC(__AC(1, UL) << MAX_PHYSMEM_BITS, UL)
+#define MAXMEM (1UL << MAX_PHYSMEM_BITS)
-#ifdef CONFIG_X86_5LEVEL
-# define VMALLOC_SIZE_TB _AC(12800, UL)
-# define __VMALLOC_BASE _AC(0xffa0000000000000, UL)
-# define __VMEMMAP_BASE _AC(0xffd4000000000000, UL)
-# define LDT_PGD_ENTRY _AC(-112, UL)
-# define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT)
-#else
-# define VMALLOC_SIZE_TB _AC(32, UL)
-# define __VMALLOC_BASE _AC(0xffffc90000000000, UL)
-# define __VMEMMAP_BASE _AC(0xffffea0000000000, UL)
-# define LDT_PGD_ENTRY _AC(-3, UL)
-# define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT)
-#endif
+#define LDT_PGD_ENTRY_L4 -3UL
+#define LDT_PGD_ENTRY_L5 -112UL
+#define LDT_PGD_ENTRY (pgtable_l5_enabled ? LDT_PGD_ENTRY_L5 : LDT_PGD_ENTRY_L4)
+#define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT)
+
+#define __VMALLOC_BASE_L4 0xffffc90000000000
+#define __VMALLOC_BASE_L5 0xffa0000000000000
+
+#define VMALLOC_SIZE_TB_L4 32UL
+#define VMALLOC_SIZE_TB_L5 12800UL
+
+#define __VMEMMAP_BASE_L4 0xffffea0000000000
+#define __VMEMMAP_BASE_L5 0xffd4000000000000
-#ifdef CONFIG_RANDOMIZE_MEMORY
+#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
# define VMALLOC_START vmalloc_base
+# define VMALLOC_SIZE_TB (pgtable_l5_enabled ? VMALLOC_SIZE_TB_L5 : VMALLOC_SIZE_TB_L4)
# define VMEMMAP_START vmemmap_base
#else
-# define VMALLOC_START __VMALLOC_BASE
-# define VMEMMAP_START __VMEMMAP_BASE
-#endif /* CONFIG_RANDOMIZE_MEMORY */
+# define VMALLOC_START __VMALLOC_BASE_L4
+# define VMALLOC_SIZE_TB VMALLOC_SIZE_TB_L4
+# define VMEMMAP_START __VMEMMAP_BASE_L4
+#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
-#define VMALLOC_END (VMALLOC_START + _AC((VMALLOC_SIZE_TB << 40) - 1, UL))
+#define VMALLOC_END (VMALLOC_START + (VMALLOC_SIZE_TB << 40) - 1)
#define MODULES_VADDR (__START_KERNEL_map + KERNEL_IMAGE_SIZE)
/* The module sections ends with the start of the fixmap */
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 246f15b4e64c..acfe755562a6 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -174,7 +174,6 @@ enum page_cache_mode {
#define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
#define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_NOCACHE)
-#define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER)
#define __PAGE_KERNEL_VVAR (__PAGE_KERNEL_RO | _PAGE_USER)
#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
@@ -206,7 +205,6 @@ enum page_cache_mode {
#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE | _PAGE_ENC)
#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE | _PAGE_ENC)
#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC | _PAGE_ENC)
-#define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL | _PAGE_ENC)
#define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR | _PAGE_ENC)
#define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO)
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index fb3a6de7440b..6847d85400a8 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -53,12 +53,6 @@
# define NEED_MOVBE 0
#endif
-#ifdef CONFIG_X86_5LEVEL
-# define NEED_LA57 (1<<(X86_FEATURE_LA57 & 31))
-#else
-# define NEED_LA57 0
-#endif
-
#ifdef CONFIG_X86_64
#ifdef CONFIG_PARAVIRT
/* Paravirtualized systems may not have PSE or PGE available */
@@ -104,7 +98,7 @@
#define REQUIRED_MASK13 0
#define REQUIRED_MASK14 0
#define REQUIRED_MASK15 0
-#define REQUIRED_MASK16 (NEED_LA57)
+#define REQUIRED_MASK16 0
#define REQUIRED_MASK17 0
#define REQUIRED_MASK18 0
#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
diff --git a/arch/x86/include/asm/sections.h b/arch/x86/include/asm/sections.h
index d6baf23782bc..5c019d23d06b 100644
--- a/arch/x86/include/asm/sections.h
+++ b/arch/x86/include/asm/sections.h
@@ -10,6 +10,7 @@ extern struct exception_table_entry __stop___ex_table[];
#if defined(CONFIG_X86_64)
extern char __end_rodata_hpage_align[];
+extern char __entry_trampoline_start[], __entry_trampoline_end[];
#endif
#endif /* _ASM_X86_SECTIONS_H */
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index a4189762b266..f75bff8f9d82 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -177,16 +177,6 @@ static inline int wbinvd_on_all_cpus(void)
extern unsigned disabled_cpus;
#ifdef CONFIG_X86_LOCAL_APIC
-
-#ifndef CONFIG_X86_64
-static inline int logical_smp_processor_id(void)
-{
- /* we don't want to mark this access volatile - bad code generation */
- return GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
-}
-
-#endif
-
extern int hard_smp_processor_id(void);
#else /* CONFIG_X86_LOCAL_APIC */
diff --git a/arch/x86/include/asm/sparsemem.h b/arch/x86/include/asm/sparsemem.h
index 4fc1e9d3c43e..4617a2bf123c 100644
--- a/arch/x86/include/asm/sparsemem.h
+++ b/arch/x86/include/asm/sparsemem.h
@@ -27,13 +27,8 @@
# endif
#else /* CONFIG_X86_32 */
# define SECTION_SIZE_BITS 27 /* matt - 128 is convenient right now */
-# ifdef CONFIG_X86_5LEVEL
-# define MAX_PHYSADDR_BITS 52
-# define MAX_PHYSMEM_BITS 52
-# else
-# define MAX_PHYSADDR_BITS 44
-# define MAX_PHYSMEM_BITS 46
-# endif
+# define MAX_PHYSADDR_BITS (pgtable_l5_enabled ? 52 : 44)
+# define MAX_PHYSMEM_BITS (pgtable_l5_enabled ? 52 : 46)
#endif
#endif /* CONFIG_SPARSEMEM */
diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h
index f73706878772..133d9425fced 100644
--- a/arch/x86/include/asm/stacktrace.h
+++ b/arch/x86/include/asm/stacktrace.h
@@ -87,8 +87,6 @@ get_stack_pointer(struct task_struct *task, struct pt_regs *regs)
void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
unsigned long *stack, char *log_lvl);
-extern unsigned int code_bytes;
-
/* The form of the top of the frame on the stack */
struct stack_frame {
struct stack_frame *next_frame;
diff --git a/arch/x86/include/asm/swiotlb.h b/arch/x86/include/asm/swiotlb.h
index 1c6a6cb230ff..ff6c92eff035 100644
--- a/arch/x86/include/asm/swiotlb.h
+++ b/arch/x86/include/asm/swiotlb.h
@@ -27,12 +27,4 @@ static inline void pci_swiotlb_late_init(void)
{
}
#endif
-
-extern void *x86_swiotlb_alloc_coherent(struct device *hwdev, size_t size,
- dma_addr_t *dma_handle, gfp_t flags,
- unsigned long attrs);
-extern void x86_swiotlb_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_addr,
- unsigned long attrs);
-
#endif /* _ASM_X86_SWIOTLB_H */
diff --git a/arch/x86/include/asm/sys_ia32.h b/arch/x86/include/asm/sys_ia32.h
deleted file mode 100644
index 82c34ee25a65..000000000000
--- a/arch/x86/include/asm/sys_ia32.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * sys_ia32.h - Linux ia32 syscall interfaces
- *
- * Copyright (c) 2008 Jaswinder Singh Rajput
- *
- * This file is released under the GPLv2.
- * See the file COPYING for more details.
- */
-
-#ifndef _ASM_X86_SYS_IA32_H
-#define _ASM_X86_SYS_IA32_H
-
-#ifdef CONFIG_COMPAT
-
-#include <linux/compiler.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-#include <linux/signal.h>
-#include <asm/compat.h>
-#include <asm/ia32.h>
-
-/* ia32/sys_ia32.c */
-asmlinkage long sys32_truncate64(const char __user *, unsigned long, unsigned long);
-asmlinkage long sys32_ftruncate64(unsigned int, unsigned long, unsigned long);
-
-asmlinkage long sys32_stat64(const char __user *, struct stat64 __user *);
-asmlinkage long sys32_lstat64(const char __user *, struct stat64 __user *);
-asmlinkage long sys32_fstat64(unsigned int, struct stat64 __user *);
-asmlinkage long sys32_fstatat(unsigned int, const char __user *,
- struct stat64 __user *, int);
-struct mmap_arg_struct32;
-asmlinkage long sys32_mmap(struct mmap_arg_struct32 __user *);
-
-asmlinkage long sys32_waitpid(compat_pid_t, unsigned int __user *, int);
-
-asmlinkage long sys32_pread(unsigned int, char __user *, u32, u32, u32);
-asmlinkage long sys32_pwrite(unsigned int, const char __user *, u32, u32, u32);
-
-long sys32_fadvise64_64(int, __u32, __u32, __u32, __u32, int);
-long sys32_vm86_warning(void);
-
-asmlinkage ssize_t sys32_readahead(int, unsigned, unsigned, size_t);
-asmlinkage long sys32_sync_file_range(int, unsigned, unsigned,
- unsigned, unsigned, int);
-asmlinkage long sys32_fadvise64(int, unsigned, unsigned, size_t, int);
-asmlinkage long sys32_fallocate(int, int, unsigned,
- unsigned, unsigned, unsigned);
-
-/* ia32/ia32_signal.c */
-asmlinkage long sys32_sigreturn(void);
-asmlinkage long sys32_rt_sigreturn(void);
-
-#endif /* CONFIG_COMPAT */
-
-#endif /* _ASM_X86_SYS_IA32_H */
diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h
index 03eedc21246d..d653139857af 100644
--- a/arch/x86/include/asm/syscall.h
+++ b/arch/x86/include/asm/syscall.h
@@ -20,9 +20,13 @@
#include <asm/thread_info.h> /* for TS_COMPAT */
#include <asm/unistd.h>
+#ifdef CONFIG_X86_64
+typedef asmlinkage long (*sys_call_ptr_t)(const struct pt_regs *);
+#else
typedef asmlinkage long (*sys_call_ptr_t)(unsigned long, unsigned long,
unsigned long, unsigned long,
unsigned long, unsigned long);
+#endif /* CONFIG_X86_64 */
extern const sys_call_ptr_t sys_call_table[];
#if defined(CONFIG_X86_32)
diff --git a/arch/x86/include/asm/syscall_wrapper.h b/arch/x86/include/asm/syscall_wrapper.h
new file mode 100644
index 000000000000..e046a405743d
--- /dev/null
+++ b/arch/x86/include/asm/syscall_wrapper.h
@@ -0,0 +1,209 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * syscall_wrapper.h - x86 specific wrappers to syscall definitions
+ */
+
+#ifndef _ASM_X86_SYSCALL_WRAPPER_H
+#define _ASM_X86_SYSCALL_WRAPPER_H
+
+/* Mapping of registers to parameters for syscalls on x86-64 and x32 */
+#define SC_X86_64_REGS_TO_ARGS(x, ...) \
+ __MAP(x,__SC_ARGS \
+ ,,regs->di,,regs->si,,regs->dx \
+ ,,regs->r10,,regs->r8,,regs->r9) \
+
+/* Mapping of registers to parameters for syscalls on i386 */
+#define SC_IA32_REGS_TO_ARGS(x, ...) \
+ __MAP(x,__SC_ARGS \
+ ,,(unsigned int)regs->bx,,(unsigned int)regs->cx \
+ ,,(unsigned int)regs->dx,,(unsigned int)regs->si \
+ ,,(unsigned int)regs->di,,(unsigned int)regs->bp)
+
+#ifdef CONFIG_IA32_EMULATION
+/*
+ * For IA32 emulation, we need to handle "compat" syscalls *and* create
+ * additional wrappers (aptly named __ia32_sys_xyzzy) which decode the
+ * ia32 regs in the proper order for shared or "common" syscalls. As some
+ * syscalls may not be implemented, we need to expand COND_SYSCALL in
+ * kernel/sys_ni.c and SYS_NI in kernel/time/posix-stubs.c to cover this
+ * case as well.
+ */
+#define __IA32_COMPAT_SYS_STUBx(x, name, ...) \
+ asmlinkage long __ia32_compat_sys##name(const struct pt_regs *regs);\
+ ALLOW_ERROR_INJECTION(__ia32_compat_sys##name, ERRNO); \
+ asmlinkage long __ia32_compat_sys##name(const struct pt_regs *regs)\
+ { \
+ return __se_compat_sys##name(SC_IA32_REGS_TO_ARGS(x,__VA_ARGS__));\
+ } \
+
+#define __IA32_SYS_STUBx(x, name, ...) \
+ asmlinkage long __ia32_sys##name(const struct pt_regs *regs); \
+ ALLOW_ERROR_INJECTION(__ia32_sys##name, ERRNO); \
+ asmlinkage long __ia32_sys##name(const struct pt_regs *regs) \
+ { \
+ return __se_sys##name(SC_IA32_REGS_TO_ARGS(x,__VA_ARGS__));\
+ }
+
+/*
+ * To keep the naming coherent, re-define SYSCALL_DEFINE0 to create an alias
+ * named __ia32_sys_*()
+ */
+#define SYSCALL_DEFINE0(sname) \
+ SYSCALL_METADATA(_##sname, 0); \
+ asmlinkage long __x64_sys_##sname(void); \
+ ALLOW_ERROR_INJECTION(__x64_sys_##sname, ERRNO); \
+ SYSCALL_ALIAS(__ia32_sys_##sname, __x64_sys_##sname); \
+ asmlinkage long __x64_sys_##sname(void)
+
+#define COND_SYSCALL(name) \
+ cond_syscall(__x64_sys_##name); \
+ cond_syscall(__ia32_sys_##name)
+
+#define SYS_NI(name) \
+ SYSCALL_ALIAS(__x64_sys_##name, sys_ni_posix_timers); \
+ SYSCALL_ALIAS(__ia32_sys_##name, sys_ni_posix_timers)
+
+#else /* CONFIG_IA32_EMULATION */
+#define __IA32_COMPAT_SYS_STUBx(x, name, ...)
+#define __IA32_SYS_STUBx(x, fullname, name, ...)
+#endif /* CONFIG_IA32_EMULATION */
+
+
+#ifdef CONFIG_X86_X32
+/*
+ * For the x32 ABI, we need to create a stub for compat_sys_*() which is aware
+ * of the x86-64-style parameter ordering of x32 syscalls. The syscalls common
+ * with x86_64 obviously do not need such care.
+ */
+#define __X32_COMPAT_SYS_STUBx(x, name, ...) \
+ asmlinkage long __x32_compat_sys##name(const struct pt_regs *regs);\
+ ALLOW_ERROR_INJECTION(__x32_compat_sys##name, ERRNO); \
+ asmlinkage long __x32_compat_sys##name(const struct pt_regs *regs)\
+ { \
+ return __se_compat_sys##name(SC_X86_64_REGS_TO_ARGS(x,__VA_ARGS__));\
+ } \
+
+#else /* CONFIG_X86_X32 */
+#define __X32_COMPAT_SYS_STUBx(x, name, ...)
+#endif /* CONFIG_X86_X32 */
+
+
+#ifdef CONFIG_COMPAT
+/*
+ * Compat means IA32_EMULATION and/or X86_X32. As they use a different
+ * mapping of registers to parameters, we need to generate stubs for each
+ * of them.
+ */
+#define COMPAT_SYSCALL_DEFINEx(x, name, ...) \
+ static long __se_compat_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)); \
+ static inline long __do_compat_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__));\
+ __IA32_COMPAT_SYS_STUBx(x, name, __VA_ARGS__) \
+ __X32_COMPAT_SYS_STUBx(x, name, __VA_ARGS__) \
+ static long __se_compat_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)) \
+ { \
+ return __do_compat_sys##name(__MAP(x,__SC_DELOUSE,__VA_ARGS__));\
+ } \
+ static inline long __do_compat_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__))
+
+/*
+ * As some compat syscalls may not be implemented, we need to expand
+ * COND_SYSCALL_COMPAT in kernel/sys_ni.c and COMPAT_SYS_NI in
+ * kernel/time/posix-stubs.c to cover this case as well.
+ */
+#define COND_SYSCALL_COMPAT(name) \
+ cond_syscall(__ia32_compat_sys_##name); \
+ cond_syscall(__x32_compat_sys_##name)
+
+#define COMPAT_SYS_NI(name) \
+ SYSCALL_ALIAS(__ia32_compat_sys_##name, sys_ni_posix_timers); \
+ SYSCALL_ALIAS(__x32_compat_sys_##name, sys_ni_posix_timers)
+
+#endif /* CONFIG_COMPAT */
+
+
+/*
+ * Instead of the generic __SYSCALL_DEFINEx() definition, this macro takes
+ * struct pt_regs *regs as the only argument of the syscall stub named
+ * __x64_sys_*(). It decodes just the registers it needs and passes them on to
+ * the __se_sys_*() wrapper performing sign extension and then to the
+ * __do_sys_*() function doing the actual job. These wrappers and functions
+ * are inlined (at least in very most cases), meaning that the assembly looks
+ * as follows (slightly re-ordered for better readability):
+ *
+ * <__x64_sys_recv>: <-- syscall with 4 parameters
+ * callq <__fentry__>
+ *
+ * mov 0x70(%rdi),%rdi <-- decode regs->di
+ * mov 0x68(%rdi),%rsi <-- decode regs->si
+ * mov 0x60(%rdi),%rdx <-- decode regs->dx
+ * mov 0x38(%rdi),%rcx <-- decode regs->r10
+ *
+ * xor %r9d,%r9d <-- clear %r9
+ * xor %r8d,%r8d <-- clear %r8
+ *
+ * callq __sys_recvfrom <-- do the actual work in __sys_recvfrom()
+ * which takes 6 arguments
+ *
+ * cltq <-- extend return value to 64-bit
+ * retq <-- return
+ *
+ * This approach avoids leaking random user-provided register content down
+ * the call chain.
+ *
+ * If IA32_EMULATION is enabled, this macro generates an additional wrapper
+ * named __ia32_sys_*() which decodes the struct pt_regs *regs according
+ * to the i386 calling convention (bx, cx, dx, si, di, bp).
+ */
+#define __SYSCALL_DEFINEx(x, name, ...) \
+ asmlinkage long __x64_sys##name(const struct pt_regs *regs); \
+ ALLOW_ERROR_INJECTION(__x64_sys##name, ERRNO); \
+ static long __se_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)); \
+ static inline long __do_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__));\
+ asmlinkage long __x64_sys##name(const struct pt_regs *regs) \
+ { \
+ return __se_sys##name(SC_X86_64_REGS_TO_ARGS(x,__VA_ARGS__));\
+ } \
+ __IA32_SYS_STUBx(x, name, __VA_ARGS__) \
+ static long __se_sys##name(__MAP(x,__SC_LONG,__VA_ARGS__)) \
+ { \
+ long ret = __do_sys##name(__MAP(x,__SC_CAST,__VA_ARGS__));\
+ __MAP(x,__SC_TEST,__VA_ARGS__); \
+ __PROTECT(x, ret,__MAP(x,__SC_ARGS,__VA_ARGS__)); \
+ return ret; \
+ } \
+ static inline long __do_sys##name(__MAP(x,__SC_DECL,__VA_ARGS__))
+
+/*
+ * As the generic SYSCALL_DEFINE0() macro does not decode any parameters for
+ * obvious reasons, and passing struct pt_regs *regs to it in %rdi does not
+ * hurt, we only need to re-define it here to keep the naming congruent to
+ * SYSCALL_DEFINEx() -- which is essential for the COND_SYSCALL() and SYS_NI()
+ * macros to work correctly.
+ */
+#ifndef SYSCALL_DEFINE0
+#define SYSCALL_DEFINE0(sname) \
+ SYSCALL_METADATA(_##sname, 0); \
+ asmlinkage long __x64_sys_##sname(void); \
+ ALLOW_ERROR_INJECTION(__x64_sys_##sname, ERRNO); \
+ asmlinkage long __x64_sys_##sname(void)
+#endif
+
+#ifndef COND_SYSCALL
+#define COND_SYSCALL(name) cond_syscall(__x64_sys_##name)
+#endif
+
+#ifndef SYS_NI
+#define SYS_NI(name) SYSCALL_ALIAS(__x64_sys_##name, sys_ni_posix_timers);
+#endif
+
+
+/*
+ * For VSYSCALLS, we need to declare these three syscalls with the new
+ * pt_regs-based calling convention for in-kernel use.
+ */
+struct pt_regs;
+asmlinkage long __x64_sys_getcpu(const struct pt_regs *regs);
+asmlinkage long __x64_sys_gettimeofday(const struct pt_regs *regs);
+asmlinkage long __x64_sys_time(const struct pt_regs *regs);
+
+#endif /* _ASM_X86_SYSCALL_WRAPPER_H */
diff --git a/arch/x86/include/asm/syscalls.h b/arch/x86/include/asm/syscalls.h
index bad25bb80679..9fa979dd0d9d 100644
--- a/arch/x86/include/asm/syscalls.h
+++ b/arch/x86/include/asm/syscalls.h
@@ -17,6 +17,13 @@
/* Common in X86_32 and X86_64 */
/* kernel/ioport.c */
+long ksys_ioperm(unsigned long from, unsigned long num, int turn_on);
+
+#ifdef CONFIG_X86_32
+/*
+ * These definitions are only valid on pure 32-bit systems; x86-64 uses a
+ * different syscall calling convention
+ */
asmlinkage long sys_ioperm(unsigned long, unsigned long, int);
asmlinkage long sys_iopl(unsigned int);
@@ -31,25 +38,14 @@ asmlinkage long sys_set_thread_area(struct user_desc __user *);
asmlinkage long sys_get_thread_area(struct user_desc __user *);
/* X86_32 only */
-#ifdef CONFIG_X86_32
/* kernel/signal.c */
-asmlinkage unsigned long sys_sigreturn(void);
+asmlinkage long sys_sigreturn(void);
/* kernel/vm86_32.c */
struct vm86_struct;
asmlinkage long sys_vm86old(struct vm86_struct __user *);
asmlinkage long sys_vm86(unsigned long, unsigned long);
-#else /* CONFIG_X86_32 */
-
-/* X86_64 only */
-/* kernel/process_64.c */
-asmlinkage long sys_arch_prctl(int, unsigned long);
-
-/* kernel/sys_x86_64.c */
-asmlinkage long sys_mmap(unsigned long, unsigned long, unsigned long,
- unsigned long, unsigned long, unsigned long);
-
#endif /* CONFIG_X86_32 */
#endif /* _ASM_X86_SYSCALLS_H */
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index cf5d53c3f9ea..2701d221583a 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -31,6 +31,7 @@ static inline cycles_t get_cycles(void)
}
extern struct system_counterval_t convert_art_to_tsc(u64 art);
+extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns);
extern void tsc_early_delay_calibrate(void);
extern void tsc_init(void);
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index ecb9ddef128f..62c79e26a59a 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -3833,7 +3833,7 @@ union uvh_rh_gam_mmioh_overlay_config0_mmr_u {
#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR uv_undefined("UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR")
#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x1603000UL
-#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x483000UL
+#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR 0x484000UL
#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR ( \
is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \
is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR : \
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 8b6780751132..5db8b0b10766 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -352,6 +352,7 @@ enum vmcs_field {
#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
+#define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */
#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
/* GUEST_INTERRUPTIBILITY_INFO flags. */
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index fc2f082ac635..199e15bd3ec5 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -131,6 +131,16 @@ struct x86_hyper_init {
};
/**
+ * struct x86_init_acpi - x86 ACPI init functions
+ * @get_root_pointer: get RSDP address
+ * @reduced_hw_early_init: hardware reduced platform early init
+ */
+struct x86_init_acpi {
+ u64 (*get_root_pointer)(void);
+ void (*reduced_hw_early_init)(void);
+};
+
+/**
* struct x86_init_ops - functions for platform specific setup
*
*/
@@ -144,6 +154,7 @@ struct x86_init_ops {
struct x86_init_iommu iommu;
struct x86_init_pci pci;
struct x86_hyper_init hyper;
+ struct x86_init_acpi acpi;
};
/**
@@ -274,16 +285,16 @@ struct x86_msi_ops {
void (*restore_msi_irqs)(struct pci_dev *dev);
};
-struct x86_io_apic_ops {
- unsigned int (*read) (unsigned int apic, unsigned int reg);
- void (*disable)(void);
+struct x86_apic_ops {
+ unsigned int (*io_apic_read) (unsigned int apic, unsigned int reg);
+ void (*restore)(void);
};
extern struct x86_init_ops x86_init;
extern struct x86_cpuinit_ops x86_cpuinit;
extern struct x86_platform_ops x86_platform;
extern struct x86_msi_ops x86_msi;
-extern struct x86_io_apic_ops x86_io_apic_ops;
+extern struct x86_apic_ops x86_apic_ops;
extern void x86_early_init_platform_quirks(void);
extern void x86_init_noop(void);
diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mce.h
index 91723461dc1f..955c2a2e1cf9 100644
--- a/arch/x86/include/uapi/asm/mce.h
+++ b/arch/x86/include/uapi/asm/mce.h
@@ -5,31 +5,36 @@
#include <linux/types.h>
#include <linux/ioctl.h>
-/* Fields are zero when not available */
+/*
+ * Fields are zero when not available. Also, this struct is shared with
+ * userspace mcelog and thus must keep existing fields at current offsets.
+ * Only add new fields to the end of the structure
+ */
struct mce {
- __u64 status;
- __u64 misc;
- __u64 addr;
- __u64 mcgstatus;
- __u64 ip;
- __u64 tsc; /* cpu time stamp counter */
- __u64 time; /* wall time_t when error was detected */
- __u8 cpuvendor; /* cpu vendor as encoded in system.h */
- __u8 inject_flags; /* software inject flags */
- __u8 severity;
+ __u64 status; /* Bank's MCi_STATUS MSR */
+ __u64 misc; /* Bank's MCi_MISC MSR */
+ __u64 addr; /* Bank's MCi_ADDR MSR */
+ __u64 mcgstatus; /* Machine Check Global Status MSR */
+ __u64 ip; /* Instruction Pointer when the error happened */
+ __u64 tsc; /* CPU time stamp counter */
+ __u64 time; /* Wall time_t when error was detected */
+ __u8 cpuvendor; /* Kernel's X86_VENDOR enum */
+ __u8 inject_flags; /* Software inject flags */
+ __u8 severity; /* Error severity */
__u8 pad;
- __u32 cpuid; /* CPUID 1 EAX */
- __u8 cs; /* code segment */
- __u8 bank; /* machine check bank */
- __u8 cpu; /* cpu number; obsolete; use extcpu now */
- __u8 finished; /* entry is valid */
- __u32 extcpu; /* linux cpu number that detected the error */
- __u32 socketid; /* CPU socket ID */
- __u32 apicid; /* CPU initial apic ID */
- __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
- __u64 synd; /* MCA_SYND MSR: only valid on SMCA systems */
- __u64 ipid; /* MCA_IPID MSR: only valid on SMCA systems */
- __u64 ppin; /* Protected Processor Inventory Number */
+ __u32 cpuid; /* CPUID 1 EAX */
+ __u8 cs; /* Code segment */
+ __u8 bank; /* Machine check bank reporting the error */
+ __u8 cpu; /* CPU number; obsoleted by extcpu */
+ __u8 finished; /* Entry is valid */
+ __u32 extcpu; /* Linux CPU number that detected the error */
+ __u32 socketid; /* CPU socket ID */
+ __u32 apicid; /* CPU initial APIC ID */
+ __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
+ __u64 synd; /* MCA_SYND MSR: only valid on SMCA systems */
+ __u64 ipid; /* MCA_IPID MSR: only valid on SMCA systems */
+ __u64 ppin; /* Protected Processor Inventory Number */
+ __u32 microcode; /* Microcode revision */
};
#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 29786c87e864..02d6f5cf4e70 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -57,7 +57,7 @@ obj-$(CONFIG_X86_ESPFIX64) += espfix_64.o
obj-$(CONFIG_SYSFS) += ksysfs.o
obj-y += bootflag.o e820.o
obj-y += pci-dma.o quirks.o topology.o kdebugfs.o
-obj-y += alternative.o i8253.o pci-nommu.o hw_breakpoint.o
+obj-y += alternative.o i8253.o hw_breakpoint.o
obj-y += tsc.o tsc_msr.o io_delay.o rtc.o
obj-y += pci-iommu_table.o
obj-y += resource.o
@@ -146,6 +146,6 @@ ifeq ($(CONFIG_X86_64),y)
obj-$(CONFIG_GART_IOMMU) += amd_gart_64.o aperture_64.o
obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o
- obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o
+ obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o
obj-y += vsmp_64.o
endif
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 5ee33a6e33bb..dde444f932c1 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -1379,17 +1379,21 @@ static int __init dmi_ignore_irq0_timer_override(const struct dmi_system_id *d)
*
* We initialize the Hardware-reduced ACPI model here:
*/
+void __init acpi_generic_reduced_hw_init(void)
+{
+ /*
+ * Override x86_init functions and bypass legacy PIC in
+ * hardware reduced ACPI mode.
+ */
+ x86_init.timers.timer_init = x86_init_noop;
+ x86_init.irqs.pre_vector_init = x86_init_noop;
+ legacy_pic = &null_legacy_pic;
+}
+
static void __init acpi_reduced_hw_init(void)
{
- if (acpi_gbl_reduced_hardware) {
- /*
- * Override x86_init functions and bypass legacy pic
- * in Hardware-reduced ACPI mode
- */
- x86_init.timers.timer_init = x86_init_noop;
- x86_init.irqs.pre_vector_init = x86_init_noop;
- legacy_pic = &null_legacy_pic;
- }
+ if (acpi_gbl_reduced_hardware)
+ x86_init.acpi.reduced_hw_early_init();
}
/*
diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c
index ecd486cb06ab..f299d8a479bb 100644
--- a/arch/x86/kernel/amd_gart_64.c
+++ b/arch/x86/kernel/amd_gart_64.c
@@ -480,30 +480,21 @@ static void *
gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
gfp_t flag, unsigned long attrs)
{
- dma_addr_t paddr;
- unsigned long align_mask;
- struct page *page;
-
- if (force_iommu && !(flag & GFP_DMA)) {
- flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
- page = alloc_pages(flag | __GFP_ZERO, get_order(size));
- if (!page)
- return NULL;
-
- align_mask = (1UL << get_order(size)) - 1;
- paddr = dma_map_area(dev, page_to_phys(page), size,
- DMA_BIDIRECTIONAL, align_mask);
-
- flush_gart();
- if (paddr != bad_dma_addr) {
- *dma_addr = paddr;
- return page_address(page);
- }
- __free_pages(page, get_order(size));
- } else
- return dma_generic_alloc_coherent(dev, size, dma_addr, flag,
- attrs);
+ void *vaddr;
+
+ vaddr = dma_direct_alloc(dev, size, dma_addr, flag, attrs);
+ if (!vaddr ||
+ !force_iommu || dev->coherent_dma_mask <= DMA_BIT_MASK(24))
+ return vaddr;
+ *dma_addr = dma_map_area(dev, virt_to_phys(vaddr), size,
+ DMA_BIDIRECTIONAL, (1UL << get_order(size)) - 1);
+ flush_gart();
+ if (unlikely(*dma_addr == bad_dma_addr))
+ goto out_free;
+ return vaddr;
+out_free:
+ dma_direct_free(dev, size, vaddr, *dma_addr, attrs);
return NULL;
}
@@ -513,7 +504,7 @@ gart_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_addr, unsigned long attrs)
{
gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, 0);
- dma_generic_free_coherent(dev, size, vaddr, dma_addr, attrs);
+ dma_direct_free(dev, size, vaddr, dma_addr, attrs);
}
static int gart_mapping_error(struct device *dev, dma_addr_t dma_addr)
@@ -705,7 +696,7 @@ static const struct dma_map_ops gart_dma_ops = {
.alloc = gart_alloc_coherent,
.free = gart_free_coherent,
.mapping_error = gart_mapping_error,
- .dma_supported = x86_dma_supported,
+ .dma_supported = dma_direct_supported,
};
static void gart_iommu_shutdown(void)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index b203af0855b5..2aabd4cb0e3f 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1408,22 +1408,69 @@ static void lapic_setup_esr(void)
oldvalue, value);
}
+static void apic_pending_intr_clear(void)
+{
+ long long max_loops = cpu_khz ? cpu_khz : 1000000;
+ unsigned long long tsc = 0, ntsc;
+ unsigned int queued;
+ unsigned long value;
+ int i, j, acked = 0;
+
+ if (boot_cpu_has(X86_FEATURE_TSC))
+ tsc = rdtsc();
+ /*
+ * After a crash, we no longer service the interrupts and a pending
+ * interrupt from previous kernel might still have ISR bit set.
+ *
+ * Most probably by now CPU has serviced that pending interrupt and
+ * it might not have done the ack_APIC_irq() because it thought,
+ * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
+ * does not clear the ISR bit and cpu thinks it has already serivced
+ * the interrupt. Hence a vector might get locked. It was noticed
+ * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
+ */
+ do {
+ queued = 0;
+ for (i = APIC_ISR_NR - 1; i >= 0; i--)
+ queued |= apic_read(APIC_IRR + i*0x10);
+
+ for (i = APIC_ISR_NR - 1; i >= 0; i--) {
+ value = apic_read(APIC_ISR + i*0x10);
+ for_each_set_bit(j, &value, 32) {
+ ack_APIC_irq();
+ acked++;
+ }
+ }
+ if (acked > 256) {
+ pr_err("LAPIC pending interrupts after %d EOI\n", acked);
+ break;
+ }
+ if (queued) {
+ if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
+ ntsc = rdtsc();
+ max_loops = (cpu_khz << 10) - (ntsc - tsc);
+ } else {
+ max_loops--;
+ }
+ }
+ } while (queued && max_loops > 0);
+ WARN_ON(max_loops <= 0);
+}
+
/**
* setup_local_APIC - setup the local APIC
*
* Used to setup local APIC while initializing BSP or bringing up APs.
* Always called with preemption disabled.
*/
-void setup_local_APIC(void)
+static void setup_local_APIC(void)
{
int cpu = smp_processor_id();
- unsigned int value, queued;
- int i, j, acked = 0;
- unsigned long long tsc = 0, ntsc;
- long long max_loops = cpu_khz ? cpu_khz : 1000000;
+ unsigned int value;
+#ifdef CONFIG_X86_32
+ int logical_apicid, ldr_apicid;
+#endif
- if (boot_cpu_has(X86_FEATURE_TSC))
- tsc = rdtsc();
if (disable_apic) {
disable_ioapic_support();
@@ -1460,11 +1507,11 @@ void setup_local_APIC(void)
* initialized during get_smp_config(), make sure it matches the
* actual value.
*/
- i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
- WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
+ logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
+ ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
+ WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid);
/* always use the value from LDR */
- early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
- logical_smp_processor_id();
+ early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
#endif
/*
@@ -1475,45 +1522,7 @@ void setup_local_APIC(void)
value &= ~APIC_TPRI_MASK;
apic_write(APIC_TASKPRI, value);
- /*
- * After a crash, we no longer service the interrupts and a pending
- * interrupt from previous kernel might still have ISR bit set.
- *
- * Most probably by now CPU has serviced that pending interrupt and
- * it might not have done the ack_APIC_irq() because it thought,
- * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
- * does not clear the ISR bit and cpu thinks it has already serivced
- * the interrupt. Hence a vector might get locked. It was noticed
- * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
- */
- do {
- queued = 0;
- for (i = APIC_ISR_NR - 1; i >= 0; i--)
- queued |= apic_read(APIC_IRR + i*0x10);
-
- for (i = APIC_ISR_NR - 1; i >= 0; i--) {
- value = apic_read(APIC_ISR + i*0x10);
- for (j = 31; j >= 0; j--) {
- if (value & (1<<j)) {
- ack_APIC_irq();
- acked++;
- }
- }
- }
- if (acked > 256) {
- printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
- acked);
- break;
- }
- if (queued) {
- if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
- ntsc = rdtsc();
- max_loops = (cpu_khz << 10) - (ntsc - tsc);
- } else
- max_loops--;
- }
- } while (queued && max_loops > 0);
- WARN_ON(max_loops <= 0);
+ apic_pending_intr_clear();
/*
* Now that we are all set up, enable the APIC
@@ -1570,7 +1579,7 @@ void setup_local_APIC(void)
* TODO: set up through-local-APIC from through-I/O-APIC? --macro
*/
value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
- if (!cpu && (pic_mode || !value)) {
+ if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
value = APIC_DM_EXTINT;
apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
} else {
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 7c5538769f7e..7553819c74c3 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -587,7 +587,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
mpc_ioapic_id(apic), pin);
}
-static void clear_IO_APIC (void)
+void clear_IO_APIC (void)
{
int apic, pin;
@@ -1410,7 +1410,7 @@ void __init enable_IO_APIC(void)
clear_IO_APIC();
}
-void native_disable_io_apic(void)
+void native_restore_boot_irq_mode(void)
{
/*
* If the i8259 is routed through an IOAPIC
@@ -1438,20 +1438,12 @@ void native_disable_io_apic(void)
disconnect_bsp_APIC(ioapic_i8259.pin != -1);
}
-/*
- * Not an __init, needed by the reboot code
- */
-void disable_IO_APIC(void)
+void restore_boot_irq_mode(void)
{
- /*
- * Clear the IO-APIC before rebooting:
- */
- clear_IO_APIC();
-
if (!nr_legacy_irqs())
return;
- x86_io_apic_ops.disable();
+ x86_apic_ops.restore();
}
#ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index e972405eb2b5..b5cf9e7b3830 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -14,7 +14,7 @@ int x2apic_phys;
static struct apic apic_x2apic_phys;
-static int set_x2apic_phys_mode(char *arg)
+static int __init set_x2apic_phys_mode(char *arg)
{
x2apic_phys = 1;
return 0;
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 570e8bb1f386..a66229f51b12 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -28,7 +28,7 @@ obj-y += cpuid-deps.o
obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o
-obj-$(CONFIG_CPU_SUP_INTEL) += intel.o
+obj-$(CONFIG_CPU_SUP_INTEL) += intel.o intel_pconfig.o
obj-$(CONFIG_CPU_SUP_AMD) += amd.o
obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f0e6456ca7d3..12bc0a1139da 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -716,7 +716,7 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
static void init_amd_gh(struct cpuinfo_x86 *c)
{
-#ifdef CONFIG_X86_64
+#ifdef CONFIG_MMCONF_FAM10H
/* do this for boot cpu */
if (c == &boot_cpu_data)
check_enable_amd_mmconf_dmi();
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index d19e903214b4..b9693b80fc21 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -105,7 +105,7 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
/*
* Early microcode releases for the Spectre v2 mitigation were broken.
* Information taken from;
- * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf
+ * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
* - https://kb.vmware.com/s/article/52345
* - Microcode revisions observed in the wild
* - Release note from 20180108 microcode release
@@ -123,7 +123,6 @@ static const struct sku_microcode spectre_bad_microcodes[] = {
{ INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
{ INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
{ INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
- { INTEL_FAM6_SKYLAKE_DESKTOP, 0x03, 0xc2 },
{ INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
{ INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
{ INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
@@ -144,6 +143,13 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
{
int i;
+ /*
+ * We know that the hypervisor lie to us on the microcode version so
+ * we may as well hope that it is running the correct version.
+ */
+ if (cpu_has(c, X86_FEATURE_HYPERVISOR))
+ return false;
+
for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
if (c->x86_model == spectre_bad_microcodes[i].model &&
c->x86_stepping == spectre_bad_microcodes[i].stepping)
@@ -503,6 +509,90 @@ static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
}
}
+#define MSR_IA32_TME_ACTIVATE 0x982
+
+/* Helpers to access TME_ACTIVATE MSR */
+#define TME_ACTIVATE_LOCKED(x) (x & 0x1)
+#define TME_ACTIVATE_ENABLED(x) (x & 0x2)
+
+#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
+#define TME_ACTIVATE_POLICY_AES_XTS_128 0
+
+#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
+
+#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
+#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
+
+/* Values for mktme_status (SW only construct) */
+#define MKTME_ENABLED 0
+#define MKTME_DISABLED 1
+#define MKTME_UNINITIALIZED 2
+static int mktme_status = MKTME_UNINITIALIZED;
+
+static void detect_tme(struct cpuinfo_x86 *c)
+{
+ u64 tme_activate, tme_policy, tme_crypto_algs;
+ int keyid_bits = 0, nr_keyids = 0;
+ static u64 tme_activate_cpu0 = 0;
+
+ rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
+
+ if (mktme_status != MKTME_UNINITIALIZED) {
+ if (tme_activate != tme_activate_cpu0) {
+ /* Broken BIOS? */
+ pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
+ pr_err_once("x86/tme: MKTME is not usable\n");
+ mktme_status = MKTME_DISABLED;
+
+ /* Proceed. We may need to exclude bits from x86_phys_bits. */
+ }
+ } else {
+ tme_activate_cpu0 = tme_activate;
+ }
+
+ if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
+ pr_info_once("x86/tme: not enabled by BIOS\n");
+ mktme_status = MKTME_DISABLED;
+ return;
+ }
+
+ if (mktme_status != MKTME_UNINITIALIZED)
+ goto detect_keyid_bits;
+
+ pr_info("x86/tme: enabled by BIOS\n");
+
+ tme_policy = TME_ACTIVATE_POLICY(tme_activate);
+ if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
+ pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
+
+ tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
+ if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
+ pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
+ tme_crypto_algs);
+ mktme_status = MKTME_DISABLED;
+ }
+detect_keyid_bits:
+ keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
+ nr_keyids = (1UL << keyid_bits) - 1;
+ if (nr_keyids) {
+ pr_info_once("x86/mktme: enabled by BIOS\n");
+ pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
+ } else {
+ pr_info_once("x86/mktme: disabled by BIOS\n");
+ }
+
+ if (mktme_status == MKTME_UNINITIALIZED) {
+ /* MKTME is usable */
+ mktme_status = MKTME_ENABLED;
+ }
+
+ /*
+ * KeyID bits effectively lower the number of physical address
+ * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
+ */
+ c->x86_phys_bits -= keyid_bits;
+}
+
static void init_intel_energy_perf(struct cpuinfo_x86 *c)
{
u64 epb;
@@ -673,6 +763,9 @@ static void init_intel(struct cpuinfo_x86 *c)
if (cpu_has(c, X86_FEATURE_VMX))
detect_vmx_virtcap(c);
+ if (cpu_has(c, X86_FEATURE_TME))
+ detect_tme(c);
+
init_intel_energy_perf(c);
init_intel_misc_features(c);
diff --git a/arch/x86/kernel/cpu/intel_pconfig.c b/arch/x86/kernel/cpu/intel_pconfig.c
new file mode 100644
index 000000000000..0771a905b286
--- /dev/null
+++ b/arch/x86/kernel/cpu/intel_pconfig.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel PCONFIG instruction support.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * Author:
+ * Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
+ */
+
+#include <asm/cpufeature.h>
+#include <asm/intel_pconfig.h>
+
+#define PCONFIG_CPUID 0x1b
+
+#define PCONFIG_CPUID_SUBLEAF_MASK ((1 << 12) - 1)
+
+/* Subleaf type (EAX) for PCONFIG CPUID leaf (0x1B) */
+enum {
+ PCONFIG_CPUID_SUBLEAF_INVALID = 0,
+ PCONFIG_CPUID_SUBLEAF_TARGETID = 1,
+};
+
+/* Bitmask of supported targets */
+static u64 targets_supported __read_mostly;
+
+int pconfig_target_supported(enum pconfig_target target)
+{
+ /*
+ * We would need to re-think the implementation once we get > 64
+ * PCONFIG targets. Spec allows up to 2^32 targets.
+ */
+ BUILD_BUG_ON(PCONFIG_TARGET_NR >= 64);
+
+ if (WARN_ON_ONCE(target >= 64))
+ return 0;
+ return targets_supported & (1ULL << target);
+}
+
+static int __init intel_pconfig_init(void)
+{
+ int subleaf;
+
+ if (!boot_cpu_has(X86_FEATURE_PCONFIG))
+ return 0;
+
+ /*
+ * Scan subleafs of PCONFIG CPUID leaf.
+ *
+ * Subleafs of the same type need not to be consecutive.
+ *
+ * Stop on the first invalid subleaf type. All subleafs after the first
+ * invalid are invalid too.
+ */
+ for (subleaf = 0; subleaf < INT_MAX; subleaf++) {
+ struct cpuid_regs regs;
+
+ cpuid_count(PCONFIG_CPUID, subleaf,
+ &regs.eax, &regs.ebx, &regs.ecx, &regs.edx);
+
+ switch (regs.eax & PCONFIG_CPUID_SUBLEAF_MASK) {
+ case PCONFIG_CPUID_SUBLEAF_INVALID:
+ /* Stop on the first invalid subleaf */
+ goto out;
+ case PCONFIG_CPUID_SUBLEAF_TARGETID:
+ /* Mark supported PCONFIG targets */
+ if (regs.ebx < 64)
+ targets_supported |= (1ULL << regs.ebx);
+ if (regs.ecx < 64)
+ targets_supported |= (1ULL << regs.ecx);
+ if (regs.edx < 64)
+ targets_supported |= (1ULL << regs.edx);
+ break;
+ default:
+ /* Unknown CPUID.PCONFIG subleaf: ignore */
+ break;
+ }
+ }
+out:
+ return 0;
+}
+arch_initcall(intel_pconfig_init);
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index 231ad23b24a9..475cb4f5f14f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -491,7 +491,7 @@ static void do_inject(void)
unsigned int cpu = i_mce.extcpu;
u8 b = i_mce.bank;
- rdtscll(i_mce.tsc);
+ i_mce.tsc = rdtsc_ordered();
if (i_mce.misc)
i_mce.status |= MCI_STATUS_MISCV;
diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index e956eb267061..374d1aa66952 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -113,8 +113,6 @@ static inline void mce_register_injector_chain(struct notifier_block *nb) { }
static inline void mce_unregister_injector_chain(struct notifier_block *nb) { }
#endif
-extern struct mca_config mca_cfg;
-
#ifndef CONFIG_X86_64
/*
* On 32-bit systems it would be difficult to safely unmap a poison page
@@ -130,4 +128,61 @@ static inline void mce_unmap_kpfn(unsigned long pfn) {}
#define mce_unmap_kpfn mce_unmap_kpfn
#endif
+struct mca_config {
+ bool dont_log_ce;
+ bool cmci_disabled;
+ bool ignore_ce;
+
+ __u64 lmce_disabled : 1,
+ disabled : 1,
+ ser : 1,
+ recovery : 1,
+ bios_cmci_threshold : 1,
+ __reserved : 59;
+
+ u8 banks;
+ s8 bootlog;
+ int tolerant;
+ int monarch_timeout;
+ int panic_timeout;
+ u32 rip_msr;
+};
+
+extern struct mca_config mca_cfg;
+
+struct mce_vendor_flags {
+ /*
+ * Indicates that overflow conditions are not fatal, when set.
+ */
+ __u64 overflow_recov : 1,
+
+ /*
+ * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
+ * Recovery. It indicates support for data poisoning in HW and deferred
+ * error interrupts.
+ */
+ succor : 1,
+
+ /*
+ * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
+ * the register space for each MCA bank and also increases number of
+ * banks. Also, to accommodate the new banks and registers, the MCA
+ * register space is moved to a new MSR range.
+ */
+ smca : 1,
+
+ __reserved_0 : 61;
+};
+
+extern struct mce_vendor_flags mce_flags;
+
+struct mca_msr_regs {
+ u32 (*ctl) (int bank);
+ u32 (*status) (int bank);
+ u32 (*addr) (int bank);
+ u32 (*misc) (int bank);
+};
+
+extern struct mca_msr_regs msr_ops;
+
#endif /* __X86_MCE_INTERNAL_H__ */
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 8ff94d1e2dce..42cf2880d0ed 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -56,6 +56,9 @@
static DEFINE_MUTEX(mce_log_mutex);
+/* sysfs synchronization */
+static DEFINE_MUTEX(mce_sysfs_mutex);
+
#define CREATE_TRACE_POINTS
#include <trace/events/mce.h>
@@ -130,6 +133,8 @@ void mce_setup(struct mce *m)
if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
rdmsrl(MSR_PPIN, m->ppin);
+
+ m->microcode = boot_cpu_data.microcode;
}
DEFINE_PER_CPU(struct mce, injectm);
@@ -262,13 +267,15 @@ static void __print_mce(struct mce *m)
*/
pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
- cpu_data(m->extcpu).microcode);
+ m->microcode);
}
static void print_mce(struct mce *m)
{
__print_mce(m);
- pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
+
+ if (m->cpuvendor != X86_VENDOR_AMD)
+ pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
}
#define PANIC_TIMEOUT 5 /* 5 seconds */
@@ -1088,19 +1095,7 @@ static void mce_unmap_kpfn(unsigned long pfn)
* a legal address.
*/
-/*
- * Build time check to see if we have a spare virtual bit. Don't want
- * to leave this until run time because most developers don't have a
- * system that can exercise this code path. This will only become a
- * problem if/when we move beyond 5-level page tables.
- *
- * Hard code "9" here because cpp doesn't grok ilog2(PTRS_PER_PGD)
- */
-#if PGDIR_SHIFT + 9 < 63
decoy_addr = (pfn << PAGE_SHIFT) + (PAGE_OFFSET ^ BIT(63));
-#else
-#error "no unused virtual bit available"
-#endif
if (set_memory_np(decoy_addr, 1))
pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
@@ -1511,7 +1506,7 @@ static int __mcheck_cpu_cap_init(void)
mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
if (cap & MCG_SER_P)
- mca_cfg.ser = true;
+ mca_cfg.ser = 1;
return 0;
}
@@ -1819,12 +1814,12 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
return;
if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
- mca_cfg.disabled = true;
+ mca_cfg.disabled = 1;
return;
}
if (mce_gen_pool_init()) {
- mca_cfg.disabled = true;
+ mca_cfg.disabled = 1;
pr_emerg("Couldn't allocate MCE records pool!\n");
return;
}
@@ -1902,11 +1897,11 @@ static int __init mcheck_enable(char *str)
if (*str == '=')
str++;
if (!strcmp(str, "off"))
- cfg->disabled = true;
+ cfg->disabled = 1;
else if (!strcmp(str, "no_cmci"))
cfg->cmci_disabled = true;
else if (!strcmp(str, "no_lmce"))
- cfg->lmce_disabled = true;
+ cfg->lmce_disabled = 1;
else if (!strcmp(str, "dont_log_ce"))
cfg->dont_log_ce = true;
else if (!strcmp(str, "ignore_ce"))
@@ -1914,9 +1909,9 @@ static int __init mcheck_enable(char *str)
else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
cfg->bootlog = (str[0] == 'b');
else if (!strcmp(str, "bios_cmci_threshold"))
- cfg->bios_cmci_threshold = true;
+ cfg->bios_cmci_threshold = 1;
else if (!strcmp(str, "recovery"))
- cfg->recovery = true;
+ cfg->recovery = 1;
else if (isdigit(str[0])) {
if (get_option(&str, &cfg->tolerant) == 2)
get_option(&str, &(cfg->monarch_timeout));
@@ -2086,6 +2081,7 @@ static ssize_t set_ignore_ce(struct device *s,
if (kstrtou64(buf, 0, &new) < 0)
return -EINVAL;
+ mutex_lock(&mce_sysfs_mutex);
if (mca_cfg.ignore_ce ^ !!new) {
if (new) {
/* disable ce features */
@@ -2098,6 +2094,8 @@ static ssize_t set_ignore_ce(struct device *s,
on_each_cpu(mce_enable_ce, (void *)1, 1);
}
}
+ mutex_unlock(&mce_sysfs_mutex);
+
return size;
}
@@ -2110,6 +2108,7 @@ static ssize_t set_cmci_disabled(struct device *s,
if (kstrtou64(buf, 0, &new) < 0)
return -EINVAL;
+ mutex_lock(&mce_sysfs_mutex);
if (mca_cfg.cmci_disabled ^ !!new) {
if (new) {
/* disable cmci */
@@ -2121,6 +2120,8 @@ static ssize_t set_cmci_disabled(struct device *s,
on_each_cpu(mce_enable_ce, NULL, 1);
}
}
+ mutex_unlock(&mce_sysfs_mutex);
+
return size;
}
@@ -2128,8 +2129,19 @@ static ssize_t store_int_with_restart(struct device *s,
struct device_attribute *attr,
const char *buf, size_t size)
{
- ssize_t ret = device_store_int(s, attr, buf, size);
+ unsigned long old_check_interval = check_interval;
+ ssize_t ret = device_store_ulong(s, attr, buf, size);
+
+ if (check_interval == old_check_interval)
+ return ret;
+
+ if (check_interval < 1)
+ check_interval = 1;
+
+ mutex_lock(&mce_sysfs_mutex);
mce_restart();
+ mutex_unlock(&mce_sysfs_mutex);
+
return ret;
}
@@ -2333,6 +2345,12 @@ static __init int mcheck_init_device(void)
{
int err;
+ /*
+ * Check if we have a spare virtual bit. This will only become
+ * a problem if/when we move beyond 5-level page tables.
+ */
+ MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
+
if (!mce_available(&boot_cpu_data)) {
err = -EIO;
goto err_out;
@@ -2381,7 +2399,7 @@ device_initcall_sync(mcheck_init_device);
*/
static int __init mcheck_disable(char *str)
{
- mca_cfg.disabled = true;
+ mca_cfg.disabled = 1;
return 1;
}
__setup("nomce", mcheck_disable);
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 0f32ad242324..f7666eef4a87 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -82,6 +82,7 @@ static struct smca_bank_name smca_names[] = {
[SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" },
[SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" },
[SMCA_DE] = { "decode_unit", "Decode Unit" },
+ [SMCA_RESERVED] = { "reserved", "Reserved" },
[SMCA_EX] = { "execution_unit", "Execution Unit" },
[SMCA_FP] = { "floating_point", "Floating Point Unit" },
[SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" },
@@ -110,14 +111,14 @@ const char *smca_get_long_name(enum smca_bank_types t)
}
EXPORT_SYMBOL_GPL(smca_get_long_name);
-static enum smca_bank_types smca_get_bank_type(struct mce *m)
+static enum smca_bank_types smca_get_bank_type(unsigned int bank)
{
struct smca_bank *b;
- if (m->bank >= N_SMCA_BANK_TYPES)
+ if (bank >= MAX_NR_BANKS)
return N_SMCA_BANK_TYPES;
- b = &smca_banks[m->bank];
+ b = &smca_banks[bank];
if (!b->hwid)
return N_SMCA_BANK_TYPES;
@@ -127,6 +128,9 @@ static enum smca_bank_types smca_get_bank_type(struct mce *m)
static struct smca_hwid smca_hwid_mcatypes[] = {
/* { bank_type, hwid_mcatype, xec_bitmap } */
+ /* Reserved type */
+ { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
+
/* ZN Core (HWID=0xB0) MCA types */
{ SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
{ SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
@@ -427,35 +431,58 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
wrmsr(MSR_CU_DEF_ERR, low, high);
}
+static u32 smca_get_block_address(unsigned int cpu, unsigned int bank,
+ unsigned int block)
+{
+ u32 low, high;
+ u32 addr = 0;
+
+ if (smca_get_bank_type(bank) == SMCA_RESERVED)
+ return addr;
+
+ if (!block)
+ return MSR_AMD64_SMCA_MCx_MISC(bank);
+
+ /*
+ * For SMCA enabled processors, BLKPTR field of the first MISC register
+ * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
+ */
+ if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
+ return addr;
+
+ if (!(low & MCI_CONFIG_MCAX))
+ return addr;
+
+ if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
+ (low & MASK_BLKPTR_LO))
+ return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
+
+ return addr;
+}
+
static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
unsigned int bank, unsigned int block)
{
u32 addr = 0, offset = 0;
- if (mce_flags.smca) {
- if (!block) {
- addr = MSR_AMD64_SMCA_MCx_MISC(bank);
- } else {
- /*
- * For SMCA enabled processors, BLKPTR field of the
- * first MISC register (MCx_MISC0) indicates presence of
- * additional MISC register set (MISC1-4).
- */
- u32 low, high;
+ if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
+ return addr;
- if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
- return addr;
+ /* Get address from already initialized block. */
+ if (per_cpu(threshold_banks, cpu)) {
+ struct threshold_bank *bankp = per_cpu(threshold_banks, cpu)[bank];
- if (!(low & MCI_CONFIG_MCAX))
- return addr;
+ if (bankp && bankp->blocks) {
+ struct threshold_block *blockp = &bankp->blocks[block];
- if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
- (low & MASK_BLKPTR_LO))
- addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
+ if (blockp)
+ return blockp->address;
}
- return addr;
}
+ if (mce_flags.smca)
+ return smca_get_block_address(cpu, bank, block);
+
/* Fall back to method we used for older processors: */
switch (block) {
case 0:
@@ -760,7 +787,7 @@ bool amd_mce_is_memory_error(struct mce *m)
u8 xec = (m->status >> 16) & 0x1f;
if (mce_flags.smca)
- return smca_get_bank_type(m) == SMCA_UMC && xec == 0x0;
+ return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;
return m->bank == 4 && xec == 0x8;
}
@@ -1063,7 +1090,7 @@ static struct kobj_type threshold_ktype = {
static const char *get_name(unsigned int bank, struct threshold_block *b)
{
- unsigned int bank_type;
+ enum smca_bank_types bank_type;
if (!mce_flags.smca) {
if (b && bank == 4)
@@ -1072,11 +1099,10 @@ static const char *get_name(unsigned int bank, struct threshold_block *b)
return th_names[bank];
}
- if (!smca_banks[bank].hwid)
+ bank_type = smca_get_bank_type(bank);
+ if (bank_type >= N_SMCA_BANK_TYPES)
return NULL;
- bank_type = smca_banks[bank].hwid->bank_type;
-
if (b && bank_type == SMCA_UMC) {
if (b->block < ARRAY_SIZE(smca_umc_block_names))
return smca_umc_block_names[b->block];
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index a998e1a7d46f..48179928ff38 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -339,7 +339,7 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
return -EINVAL;
ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size);
- if (ret != UCODE_OK)
+ if (ret > UCODE_UPDATED)
return -EINVAL;
return 0;
@@ -683,27 +683,35 @@ static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
static enum ucode_state
load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
{
+ struct ucode_patch *p;
enum ucode_state ret;
/* free old equiv table */
free_equiv_cpu_table();
ret = __load_microcode_amd(family, data, size);
-
- if (ret != UCODE_OK)
+ if (ret != UCODE_OK) {
cleanup();
+ return ret;
+ }
-#ifdef CONFIG_X86_32
- /* save BSP's matching patch for early load */
- if (save) {
- struct ucode_patch *p = find_patch(0);
- if (p) {
- memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
- memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data),
- PATCH_MAX_SIZE));
- }
+ p = find_patch(0);
+ if (!p) {
+ return ret;
+ } else {
+ if (boot_cpu_data.microcode == p->patch_id)
+ return ret;
+
+ ret = UCODE_NEW;
}
-#endif
+
+ /* save BSP's matching patch for early load */
+ if (!save)
+ return ret;
+
+ memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
+ memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE));
+
return ret;
}
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index aa1b9a422f2b..10c4fc2c91f8 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -22,13 +22,16 @@
#define pr_fmt(fmt) "microcode: " fmt
#include <linux/platform_device.h>
+#include <linux/stop_machine.h>
#include <linux/syscore_ops.h>
#include <linux/miscdevice.h>
#include <linux/capability.h>
#include <linux/firmware.h>
#include <linux/kernel.h>
+#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/cpu.h>
+#include <linux/nmi.h>
#include <linux/fs.h>
#include <linux/mm.h>
@@ -64,6 +67,11 @@ LIST_HEAD(microcode_cache);
*/
static DEFINE_MUTEX(microcode_mutex);
+/*
+ * Serialize late loading so that CPUs get updated one-by-one.
+ */
+static DEFINE_SPINLOCK(update_lock);
+
struct ucode_cpu_info ucode_cpu_info[NR_CPUS];
struct cpu_info_ctx {
@@ -373,26 +381,23 @@ static int collect_cpu_info(int cpu)
return ret;
}
-struct apply_microcode_ctx {
- enum ucode_state err;
-};
-
static void apply_microcode_local(void *arg)
{
- struct apply_microcode_ctx *ctx = arg;
+ enum ucode_state *err = arg;
- ctx->err = microcode_ops->apply_microcode(smp_processor_id());
+ *err = microcode_ops->apply_microcode(smp_processor_id());
}
static int apply_microcode_on_target(int cpu)
{
- struct apply_microcode_ctx ctx = { .err = 0 };
+ enum ucode_state err;
int ret;
- ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1);
- if (!ret)
- ret = ctx.err;
-
+ ret = smp_call_function_single(cpu, apply_microcode_local, &err, 1);
+ if (!ret) {
+ if (err == UCODE_ERROR)
+ ret = 1;
+ }
return ret;
}
@@ -489,19 +494,114 @@ static void __exit microcode_dev_exit(void)
/* fake device for request_firmware */
static struct platform_device *microcode_pdev;
-static enum ucode_state reload_for_cpu(int cpu)
+/*
+ * Late loading dance. Why the heavy-handed stomp_machine effort?
+ *
+ * - HT siblings must be idle and not execute other code while the other sibling
+ * is loading microcode in order to avoid any negative interactions caused by
+ * the loading.
+ *
+ * - In addition, microcode update on the cores must be serialized until this
+ * requirement can be relaxed in the future. Right now, this is conservative
+ * and good.
+ */
+#define SPINUNIT 100 /* 100 nsec */
+
+static int check_online_cpus(void)
{
- struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
- enum ucode_state ustate;
+ if (num_online_cpus() == num_present_cpus())
+ return 0;
- if (!uci->valid)
- return UCODE_OK;
+ pr_err("Not all CPUs online, aborting microcode update.\n");
+
+ return -EINVAL;
+}
+
+static atomic_t late_cpus_in;
+static atomic_t late_cpus_out;
+
+static int __wait_for_cpus(atomic_t *t, long long timeout)
+{
+ int all_cpus = num_online_cpus();
+
+ atomic_inc(t);
- ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev, true);
- if (ustate != UCODE_OK)
- return ustate;
+ while (atomic_read(t) < all_cpus) {
+ if (timeout < SPINUNIT) {
+ pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n",
+ all_cpus - atomic_read(t));
+ return 1;
+ }
- return apply_microcode_on_target(cpu);
+ ndelay(SPINUNIT);
+ timeout -= SPINUNIT;
+
+ touch_nmi_watchdog();
+ }
+ return 0;
+}
+
+/*
+ * Returns:
+ * < 0 - on error
+ * 0 - no update done
+ * 1 - microcode was updated
+ */
+static int __reload_late(void *info)
+{
+ int cpu = smp_processor_id();
+ enum ucode_state err;
+ int ret = 0;
+
+ /*
+ * Wait for all CPUs to arrive. A load will not be attempted unless all
+ * CPUs show up.
+ * */
+ if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC))
+ return -1;
+
+ spin_lock(&update_lock);
+ apply_microcode_local(&err);
+ spin_unlock(&update_lock);
+
+ if (err > UCODE_NFOUND) {
+ pr_warn("Error reloading microcode on CPU %d\n", cpu);
+ return -1;
+ /* siblings return UCODE_OK because their engine got updated already */
+ } else if (err == UCODE_UPDATED || err == UCODE_OK) {
+ ret = 1;
+ } else {
+ return ret;
+ }
+
+ /*
+ * Increase the wait timeout to a safe value here since we're
+ * serializing the microcode update and that could take a while on a
+ * large number of CPUs. And that is fine as the *actual* timeout will
+ * be determined by the last CPU finished updating and thus cut short.
+ */
+ if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC * num_online_cpus()))
+ panic("Timeout during microcode update!\n");
+
+ return ret;
+}
+
+/*
+ * Reload microcode late on all CPUs. Wait for a sec until they
+ * all gather together.
+ */
+static int microcode_reload_late(void)
+{
+ int ret;
+
+ atomic_set(&late_cpus_in, 0);
+ atomic_set(&late_cpus_out, 0);
+
+ ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask);
+ if (ret > 0)
+ microcode_check();
+
+ return ret;
}
static ssize_t reload_store(struct device *dev,
@@ -509,10 +609,9 @@ static ssize_t reload_store(struct device *dev,
const char *buf, size_t size)
{
enum ucode_state tmp_ret = UCODE_OK;
- bool do_callback = false;
+ int bsp = boot_cpu_data.cpu_index;
unsigned long val;
ssize_t ret = 0;
- int cpu;
ret = kstrtoul(buf, 0, &val);
if (ret)
@@ -521,29 +620,24 @@ static ssize_t reload_store(struct device *dev,
if (val != 1)
return size;
- get_online_cpus();
- mutex_lock(&microcode_mutex);
- for_each_online_cpu(cpu) {
- tmp_ret = reload_for_cpu(cpu);
- if (tmp_ret > UCODE_NFOUND) {
- pr_warn("Error reloading microcode on CPU %d\n", cpu);
-
- /* set retval for the first encountered reload error */
- if (!ret)
- ret = -EINVAL;
- }
+ tmp_ret = microcode_ops->request_microcode_fw(bsp, &microcode_pdev->dev, true);
+ if (tmp_ret != UCODE_NEW)
+ return size;
- if (tmp_ret == UCODE_UPDATED)
- do_callback = true;
- }
+ get_online_cpus();
- if (!ret && do_callback)
- microcode_check();
+ ret = check_online_cpus();
+ if (ret)
+ goto put;
+ mutex_lock(&microcode_mutex);
+ ret = microcode_reload_late();
mutex_unlock(&microcode_mutex);
+
+put:
put_online_cpus();
- if (!ret)
+ if (ret >= 0)
ret = size;
return ret;
@@ -611,10 +705,8 @@ static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw)
if (system_state != SYSTEM_RUNNING)
return UCODE_NFOUND;
- ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev,
- refresh_fw);
-
- if (ustate == UCODE_OK) {
+ ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev, refresh_fw);
+ if (ustate == UCODE_NEW) {
pr_debug("CPU%d updated upon init\n", cpu);
apply_microcode_on_target(cpu);
}
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 923054a6b760..32b8e5724f96 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -589,6 +589,23 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
if (!mc)
return 0;
+ /*
+ * Save us the MSR write below - which is a particular expensive
+ * operation - when the other hyperthread has updated the microcode
+ * already.
+ */
+ rev = intel_get_microcode_revision();
+ if (rev >= mc->hdr.rev) {
+ uci->cpu_sig.rev = rev;
+ return UCODE_OK;
+ }
+
+ /*
+ * Writeback and invalidate caches before updating microcode to avoid
+ * internal issues depending on what the microcode is updating.
+ */
+ native_wbinvd();
+
/* write microcode via MSR 0x79 */
native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -774,9 +791,9 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
static enum ucode_state apply_microcode_intel(int cpu)
{
+ struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
struct microcode_intel *mc;
- struct ucode_cpu_info *uci;
- struct cpuinfo_x86 *c;
static int prev_rev;
u32 rev;
@@ -784,15 +801,32 @@ static enum ucode_state apply_microcode_intel(int cpu)
if (WARN_ON(raw_smp_processor_id() != cpu))
return UCODE_ERROR;
- uci = ucode_cpu_info + cpu;
- mc = uci->mc;
+ /* Look for a newer patch in our cache: */
+ mc = find_patch(uci);
if (!mc) {
- /* Look for a newer patch in our cache: */
- mc = find_patch(uci);
+ mc = uci->mc;
if (!mc)
return UCODE_NFOUND;
}
+ /*
+ * Save us the MSR write below - which is a particular expensive
+ * operation - when the other hyperthread has updated the microcode
+ * already.
+ */
+ rev = intel_get_microcode_revision();
+ if (rev >= mc->hdr.rev) {
+ uci->cpu_sig.rev = rev;
+ c->microcode = rev;
+ return UCODE_OK;
+ }
+
+ /*
+ * Writeback and invalidate caches before updating microcode to avoid
+ * internal issues depending on what the microcode is updating.
+ */
+ native_wbinvd();
+
/* write microcode via MSR 0x79 */
wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -813,8 +847,6 @@ static enum ucode_state apply_microcode_intel(int cpu)
prev_rev = rev;
}
- c = &cpu_data(cpu);
-
uci->cpu_sig.rev = rev;
c->microcode = rev;
@@ -830,6 +862,7 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
unsigned int leftover = size;
unsigned int curr_mc_size = 0, new_mc_size = 0;
unsigned int csig, cpf;
+ enum ucode_state ret = UCODE_OK;
while (leftover) {
struct microcode_header_intel mc_header;
@@ -871,6 +904,7 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
new_mc = mc;
new_mc_size = mc_size;
mc = NULL; /* trigger new vmalloc */
+ ret = UCODE_NEW;
}
ucode_ptr += mc_size;
@@ -900,7 +934,7 @@ static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
cpu, new_rev, uci->cpu_sig.rev);
- return UCODE_OK;
+ return ret;
}
static int get_ucode_fw(void *to, const void *from, size_t n)
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 0931a105ffe1..1d300f96df4b 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -40,6 +40,7 @@
#include <linux/notifier.h>
#include <linux/uaccess.h>
#include <linux/gfp.h>
+#include <linux/completion.h>
#include <asm/processor.h>
#include <asm/msr.h>
@@ -47,19 +48,27 @@
static struct class *cpuid_class;
static enum cpuhp_state cpuhp_cpuid_state;
+struct cpuid_regs_done {
+ struct cpuid_regs regs;
+ struct completion done;
+};
+
static void cpuid_smp_cpuid(void *cmd_block)
{
- struct cpuid_regs *cmd = (struct cpuid_regs *)cmd_block;
+ struct cpuid_regs_done *cmd = cmd_block;
+
+ cpuid_count(cmd->regs.eax, cmd->regs.ecx,
+ &cmd->regs.eax, &cmd->regs.ebx,
+ &cmd->regs.ecx, &cmd->regs.edx);
- cpuid_count(cmd->eax, cmd->ecx,
- &cmd->eax, &cmd->ebx, &cmd->ecx, &cmd->edx);
+ complete(&cmd->done);
}
static ssize_t cpuid_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
char __user *tmp = buf;
- struct cpuid_regs cmd;
+ struct cpuid_regs_done cmd;
int cpu = iminor(file_inode(file));
u64 pos = *ppos;
ssize_t bytes = 0;
@@ -68,19 +77,28 @@ static ssize_t cpuid_read(struct file *file, char __user *buf,
if (count % 16)
return -EINVAL; /* Invalid chunk size */
+ init_completion(&cmd.done);
for (; count; count -= 16) {
- cmd.eax = pos;
- cmd.ecx = pos >> 32;
- err = smp_call_function_single(cpu, cpuid_smp_cpuid, &cmd, 1);
+ call_single_data_t csd = {
+ .func = cpuid_smp_cpuid,
+ .info = &cmd,
+ };
+
+ cmd.regs.eax = pos;
+ cmd.regs.ecx = pos >> 32;
+
+ err = smp_call_function_single_async(cpu, &csd);
if (err)
break;
- if (copy_to_user(tmp, &cmd, 16)) {
+ wait_for_completion(&cmd.done);
+ if (copy_to_user(tmp, &cmd.regs, 16)) {
err = -EFAULT;
break;
}
tmp += 16;
bytes += 16;
*ppos = ++pos;
+ reinit_completion(&cmd.done);
}
return bytes ? bytes : err;
diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c
index 10e74d4778a1..1f6680427ff0 100644
--- a/arch/x86/kernel/crash.c
+++ b/arch/x86/kernel/crash.c
@@ -199,9 +199,10 @@ void native_machine_crash_shutdown(struct pt_regs *regs)
#ifdef CONFIG_X86_IO_APIC
/* Prevent crash_kexec() from deadlocking on ioapic_lock. */
ioapic_zap_locks();
- disable_IO_APIC();
+ clear_IO_APIC();
#endif
lapic_shutdown();
+ restore_boot_irq_mode();
#ifdef CONFIG_HPET_TIMER
hpet_disable();
#endif
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 25de5f6ca997..f39f3a06c26f 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -11,6 +11,7 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
+#include <linux/libfdt.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/of_pci.h>
@@ -130,34 +131,52 @@ static void __init dtb_setup_hpet(void)
#endif
}
+#ifdef CONFIG_X86_LOCAL_APIC
+
+static void __init dtb_cpu_setup(void)
+{
+ struct device_node *dn;
+ u32 apic_id, version;
+ int ret;
+
+ version = GET_APIC_VERSION(apic_read(APIC_LVR));
+ for_each_node_by_type(dn, "cpu") {
+ ret = of_property_read_u32(dn, "reg", &apic_id);
+ if (ret < 0) {
+ pr_warn("%pOF: missing local APIC ID\n", dn);
+ continue;
+ }
+ generic_processor_info(apic_id, version);
+ }
+}
+
static void __init dtb_lapic_setup(void)
{
-#ifdef CONFIG_X86_LOCAL_APIC
struct device_node *dn;
struct resource r;
+ unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
int ret;
dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
- if (!dn)
- return;
-
- ret = of_address_to_resource(dn, 0, &r);
- if (WARN_ON(ret))
- return;
+ if (dn) {
+ ret = of_address_to_resource(dn, 0, &r);
+ if (WARN_ON(ret))
+ return;
+ lapic_addr = r.start;
+ }
/* Did the boot loader setup the local APIC ? */
if (!boot_cpu_has(X86_FEATURE_APIC)) {
- if (apic_force_enable(r.start))
+ if (apic_force_enable(lapic_addr))
return;
}
smp_found_config = 1;
pic_mode = 1;
- register_lapic_address(r.start);
- generic_processor_info(boot_cpu_physical_apicid,
- GET_APIC_VERSION(apic_read(APIC_LVR)));
-#endif
+ register_lapic_address(lapic_addr);
}
+#endif /* CONFIG_X86_LOCAL_APIC */
+
#ifdef CONFIG_X86_IO_APIC
static unsigned int ioapic_id;
@@ -194,19 +213,22 @@ static struct of_ioapic_type of_ioapic_type[] =
static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
unsigned int nr_irqs, void *arg)
{
- struct of_phandle_args *irq_data = (void *)arg;
+ struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
struct of_ioapic_type *it;
struct irq_alloc_info tmp;
+ int type_index;
- if (WARN_ON(irq_data->args_count < 2))
+ if (WARN_ON(fwspec->param_count < 2))
return -EINVAL;
- if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type))
+
+ type_index = fwspec->param[1];
+ if (type_index >= ARRAY_SIZE(of_ioapic_type))
return -EINVAL;
- it = &of_ioapic_type[irq_data->args[1]];
+ it = &of_ioapic_type[type_index];
ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
- tmp.ioapic_pin = irq_data->args[0];
+ tmp.ioapic_pin = fwspec->param[0];
return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
}
@@ -255,11 +277,14 @@ static void __init dtb_ioapic_setup(void) {}
static void __init dtb_apic_setup(void)
{
+#ifdef CONFIG_X86_LOCAL_APIC
dtb_lapic_setup();
+ dtb_cpu_setup();
+#endif
dtb_ioapic_setup();
}
-#ifdef CONFIG_OF_FLATTREE
+#ifdef CONFIG_OF_EARLY_FLATTREE
static void __init x86_flattree_get_config(void)
{
u32 size, map_len;
@@ -270,14 +295,15 @@ static void __init x86_flattree_get_config(void)
map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
- initial_boot_params = dt = early_memremap(initial_dtb, map_len);
- size = of_get_flat_dt_size();
+ dt = early_memremap(initial_dtb, map_len);
+ size = fdt_totalsize(dt);
if (map_len < size) {
early_memunmap(dt, map_len);
- initial_boot_params = dt = early_memremap(initial_dtb, size);
+ dt = early_memremap(initial_dtb, size);
map_len = size;
}
+ early_init_dt_verify(dt);
unflatten_and_copy_device_tree();
early_memunmap(dt, map_len);
}
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index a2d8a3908670..18fa9d74c182 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -24,7 +24,7 @@
int panic_on_unrecovered_nmi;
int panic_on_io_nmi;
-unsigned int code_bytes = 64;
+static unsigned int code_bytes = 64;
static int die_counter;
bool in_task_stack(unsigned long *stack, struct task_struct *task,
@@ -375,3 +375,50 @@ static int __init code_bytes_setup(char *s)
return 1;
}
__setup("code_bytes=", code_bytes_setup);
+
+void show_regs(struct pt_regs *regs)
+{
+ bool all = true;
+ int i;
+
+ show_regs_print_info(KERN_DEFAULT);
+
+ if (IS_ENABLED(CONFIG_X86_32))
+ all = !user_mode(regs);
+
+ __show_regs(regs, all);
+
+ /*
+ * When in-kernel, we also print out the stack and code at the
+ * time of the fault..
+ */
+ if (!user_mode(regs)) {
+ unsigned int code_prologue = code_bytes * 43 / 64;
+ unsigned int code_len = code_bytes;
+ unsigned char c;
+ u8 *ip;
+
+ show_trace_log_lvl(current, regs, NULL, KERN_DEFAULT);
+
+ printk(KERN_DEFAULT "Code: ");
+
+ ip = (u8 *)regs->ip - code_prologue;
+ if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) {
+ /* try starting at IP */
+ ip = (u8 *)regs->ip;
+ code_len = code_len - code_prologue + 1;
+ }
+ for (i = 0; i < code_len; i++, ip++) {
+ if (ip < (u8 *)PAGE_OFFSET ||
+ probe_kernel_address(ip, c)) {
+ pr_cont(" Bad RIP value.");
+ break;
+ }
+ if (ip == (u8 *)regs->ip)
+ pr_cont("<%02x> ", c);
+ else
+ pr_cont("%02x ", c);
+ }
+ }
+ pr_cont("\n");
+}
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index 04170f63e3a1..cd53f3030e40 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -127,45 +127,3 @@ unknown:
info->type = STACK_TYPE_UNKNOWN;
return -EINVAL;
}
-
-void show_regs(struct pt_regs *regs)
-{
- int i;
-
- show_regs_print_info(KERN_EMERG);
- __show_regs(regs, !user_mode(regs));
-
- /*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (!user_mode(regs)) {
- unsigned int code_prologue = code_bytes * 43 / 64;
- unsigned int code_len = code_bytes;
- unsigned char c;
- u8 *ip;
-
- show_trace_log_lvl(current, regs, NULL, KERN_EMERG);
-
- pr_emerg("Code:");
-
- ip = (u8 *)regs->ip - code_prologue;
- if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) {
- /* try starting at IP */
- ip = (u8 *)regs->ip;
- code_len = code_len - code_prologue + 1;
- }
- for (i = 0; i < code_len; i++, ip++) {
- if (ip < (u8 *)PAGE_OFFSET ||
- probe_kernel_address(ip, c)) {
- pr_cont(" Bad EIP value.");
- break;
- }
- if (ip == (u8 *)regs->ip)
- pr_cont(" <%02x>", c);
- else
- pr_cont(" %02x", c);
- }
- }
- pr_cont("\n");
-}
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 563e28d14f2c..5cdb9e84da57 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -149,45 +149,3 @@ unknown:
info->type = STACK_TYPE_UNKNOWN;
return -EINVAL;
}
-
-void show_regs(struct pt_regs *regs)
-{
- int i;
-
- show_regs_print_info(KERN_DEFAULT);
- __show_regs(regs, 1);
-
- /*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (!user_mode(regs)) {
- unsigned int code_prologue = code_bytes * 43 / 64;
- unsigned int code_len = code_bytes;
- unsigned char c;
- u8 *ip;
-
- show_trace_log_lvl(current, regs, NULL, KERN_DEFAULT);
-
- printk(KERN_DEFAULT "Code: ");
-
- ip = (u8 *)regs->ip - code_prologue;
- if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) {
- /* try starting at IP */
- ip = (u8 *)regs->ip;
- code_len = code_len - code_prologue + 1;
- }
- for (i = 0; i < code_len; i++, ip++) {
- if (ip < (u8 *)PAGE_OFFSET ||
- probe_kernel_address(ip, c)) {
- pr_cont(" Bad RIP value.");
- break;
- }
- if (ip == (u8 *)regs->ip)
- pr_cont("<%02x> ", c);
- else
- pr_cont("%02x ", c);
- }
- }
- pr_cont("\n");
-}
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 71c11ad5643e..6a2cb1442e05 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -924,6 +924,24 @@ static int __init parse_memmap_one(char *p)
} else if (*p == '!') {
start_at = memparse(p+1, &p);
e820__range_add(start_at, mem_size, E820_TYPE_PRAM);
+ } else if (*p == '%') {
+ enum e820_type from = 0, to = 0;
+
+ start_at = memparse(p + 1, &p);
+ if (*p == '-')
+ from = simple_strtoull(p + 1, &p, 0);
+ if (*p == '+')
+ to = simple_strtoull(p + 1, &p, 0);
+ if (*p != '\0')
+ return -EINVAL;
+ if (from && to)
+ e820__range_update(start_at, mem_size, from, to);
+ else if (to)
+ e820__range_add(start_at, mem_size, to);
+ else if (from)
+ e820__range_remove(start_at, mem_size, from, 1);
+ else
+ e820__range_remove(start_at, mem_size, 0, 0);
} else {
e820__range_remove(mem_size, ULLONG_MAX - mem_size, E820_TYPE_RAM, 1);
}
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 7ba5d819ebe3..0c855deee165 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -32,6 +32,11 @@
#include <asm/microcode.h>
#include <asm/kasan.h>
+#ifdef CONFIG_X86_5LEVEL
+#undef pgtable_l5_enabled
+#define pgtable_l5_enabled __pgtable_l5_enabled
+#endif
+
/*
* Manage page tables very early on.
*/
@@ -39,6 +44,24 @@ extern pmd_t early_dynamic_pgts[EARLY_DYNAMIC_PAGE_TABLES][PTRS_PER_PMD];
static unsigned int __initdata next_early_pgt;
pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
+#ifdef CONFIG_X86_5LEVEL
+unsigned int __pgtable_l5_enabled __ro_after_init;
+EXPORT_SYMBOL(__pgtable_l5_enabled);
+unsigned int pgdir_shift __ro_after_init = 39;
+EXPORT_SYMBOL(pgdir_shift);
+unsigned int ptrs_per_p4d __ro_after_init = 1;
+EXPORT_SYMBOL(ptrs_per_p4d);
+#endif
+
+#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
+unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
+EXPORT_SYMBOL(page_offset_base);
+unsigned long vmalloc_base __ro_after_init = __VMALLOC_BASE_L4;
+EXPORT_SYMBOL(vmalloc_base);
+unsigned long vmemmap_base __ro_after_init = __VMEMMAP_BASE_L4;
+EXPORT_SYMBOL(vmemmap_base);
+#endif
+
#define __head __section(.head.text)
static void __head *fixup_pointer(void *ptr, unsigned long physaddr)
@@ -46,6 +69,41 @@ static void __head *fixup_pointer(void *ptr, unsigned long physaddr)
return ptr - (void *)_text + (void *)physaddr;
}
+static unsigned long __head *fixup_long(void *ptr, unsigned long physaddr)
+{
+ return fixup_pointer(ptr, physaddr);
+}
+
+#ifdef CONFIG_X86_5LEVEL
+static unsigned int __head *fixup_int(void *ptr, unsigned long physaddr)
+{
+ return fixup_pointer(ptr, physaddr);
+}
+
+static bool __head check_la57_support(unsigned long physaddr)
+{
+ if (native_cpuid_eax(0) < 7)
+ return false;
+
+ if (!(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
+ return false;
+
+ *fixup_int(&pgtable_l5_enabled, physaddr) = 1;
+ *fixup_int(&pgdir_shift, physaddr) = 48;
+ *fixup_int(&ptrs_per_p4d, physaddr) = 512;
+ *fixup_long(&page_offset_base, physaddr) = __PAGE_OFFSET_BASE_L5;
+ *fixup_long(&vmalloc_base, physaddr) = __VMALLOC_BASE_L5;
+ *fixup_long(&vmemmap_base, physaddr) = __VMEMMAP_BASE_L5;
+
+ return true;
+}
+#else
+static bool __head check_la57_support(unsigned long physaddr)
+{
+ return false;
+}
+#endif
+
unsigned long __head __startup_64(unsigned long physaddr,
struct boot_params *bp)
{
@@ -55,9 +113,12 @@ unsigned long __head __startup_64(unsigned long physaddr,
p4dval_t *p4d;
pudval_t *pud;
pmdval_t *pmd, pmd_entry;
+ bool la57;
int i;
unsigned int *next_pgt_ptr;
+ la57 = check_la57_support(physaddr);
+
/* Is the address too large? */
if (physaddr >> MAX_PHYSMEM_BITS)
for (;;);
@@ -81,9 +142,14 @@ unsigned long __head __startup_64(unsigned long physaddr,
/* Fixup the physical addresses in the page table */
pgd = fixup_pointer(&early_top_pgt, physaddr);
- pgd[pgd_index(__START_KERNEL_map)] += load_delta;
-
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+ p = pgd + pgd_index(__START_KERNEL_map);
+ if (la57)
+ *p = (unsigned long)level4_kernel_pgt;
+ else
+ *p = (unsigned long)level3_kernel_pgt;
+ *p += _PAGE_TABLE_NOENC - __START_KERNEL_map + load_delta;
+
+ if (la57) {
p4d = fixup_pointer(&level4_kernel_pgt, physaddr);
p4d[511] += load_delta;
}
@@ -108,7 +174,7 @@ unsigned long __head __startup_64(unsigned long physaddr,
pgtable_flags = _KERNPG_TABLE_NOENC + sme_get_me_mask();
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+ if (la57) {
p4d = fixup_pointer(early_dynamic_pgts[next_early_pgt++], physaddr);
i = (physaddr >> PGDIR_SHIFT) % PTRS_PER_PGD;
@@ -154,8 +220,7 @@ unsigned long __head __startup_64(unsigned long physaddr,
* Fixup phys_base - remove the memory encryption mask to obtain
* the true physical address.
*/
- p = fixup_pointer(&phys_base, physaddr);
- *p += load_delta - sme_get_me_mask();
+ *fixup_long(&phys_base, physaddr) += load_delta - sme_get_me_mask();
/* Encrypt the kernel and related (if SME is active) */
sme_encrypt_kernel(bp);
@@ -206,7 +271,7 @@ again:
* critical -- __PAGE_OFFSET would point us back into the dynamic
* range and we might end up looping forever...
*/
- if (!IS_ENABLED(CONFIG_X86_5LEVEL))
+ if (!pgtable_l5_enabled)
p4d_p = pgd_p;
else if (pgd)
p4d_p = (p4dval_t *)((pgd & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
@@ -322,7 +387,7 @@ asmlinkage __visible void __init x86_64_start_kernel(char * real_mode_data)
BUILD_BUG_ON((__START_KERNEL_map & ~PMD_MASK) != 0);
BUILD_BUG_ON((MODULES_VADDR & ~PMD_MASK) != 0);
BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL));
- BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
+ MAYBE_BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
(__START_KERNEL & PGDIR_MASK)));
BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) <= MODULES_END);
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 0f545b3cf926..48385c1074a5 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -39,12 +39,12 @@
*
*/
+#define l4_index(x) (((x) >> 39) & 511)
#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
-#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
-PGD_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE)
-PGD_START_KERNEL = pgd_index(__START_KERNEL_map)
-#endif
+L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
+L4_START_KERNEL = l4_index(__START_KERNEL_map)
+
L3_START_KERNEL = pud_index(__START_KERNEL_map)
.text
@@ -125,7 +125,10 @@ ENTRY(secondary_startup_64)
/* Enable PAE mode, PGE and LA57 */
movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
#ifdef CONFIG_X86_5LEVEL
+ testl $1, __pgtable_l5_enabled(%rip)
+ jz 1f
orl $X86_CR4_LA57, %ecx
+1:
#endif
movq %rcx, %cr4
@@ -374,12 +377,7 @@ GLOBAL(name)
__INITDATA
NEXT_PGD_PAGE(early_top_pgt)
- .fill 511,8,0
-#ifdef CONFIG_X86_5LEVEL
- .quad level4_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
-#else
- .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
-#endif
+ .fill 512,8,0
.fill PTI_USER_PGD_FILL,8,0
NEXT_PAGE(early_dynamic_pgts)
@@ -390,9 +388,9 @@ NEXT_PAGE(early_dynamic_pgts)
#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
NEXT_PGD_PAGE(init_top_pgt)
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
- .org init_top_pgt + PGD_PAGE_OFFSET*8, 0
+ .org init_top_pgt + L4_PAGE_OFFSET*8, 0
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
- .org init_top_pgt + PGD_START_KERNEL*8, 0
+ .org init_top_pgt + L4_START_KERNEL*8, 0
/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
.fill PTI_USER_PGD_FILL,8,0
diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
index 56d99be3706a..2c3a1b4294eb 100644
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -140,6 +140,9 @@ static const __initconst struct idt_data apic_idts[] = {
# ifdef CONFIG_IRQ_WORK
INTG(IRQ_WORK_VECTOR, irq_work_interrupt),
# endif
+#ifdef CONFIG_X86_UV
+ INTG(UV_BAU_MESSAGE, uv_bau_message_intr1),
+#endif
INTG(SPURIOUS_APIC_VECTOR, spurious_interrupt),
INTG(ERROR_APIC_VECTOR, error_interrupt),
#endif
@@ -160,7 +163,6 @@ static const __initconst struct idt_data early_pf_idts[] = {
*/
static const __initconst struct idt_data dbg_idts[] = {
INTG(X86_TRAP_DB, debug),
- INTG(X86_TRAP_BP, int3),
};
#endif
@@ -183,7 +185,6 @@ gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
static const __initconst struct idt_data ist_idts[] = {
ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
- SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
#ifdef CONFIG_X86_MCE
ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
diff --git a/arch/x86/kernel/ioport.c b/arch/x86/kernel/ioport.c
index 2f723301eb58..0fe1c8782208 100644
--- a/arch/x86/kernel/ioport.c
+++ b/arch/x86/kernel/ioport.c
@@ -23,7 +23,7 @@
/*
* this changes the io permissions bitmap in the current task.
*/
-asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on)
+long ksys_ioperm(unsigned long from, unsigned long num, int turn_on)
{
struct thread_struct *t = &current->thread;
struct tss_struct *tss;
@@ -96,6 +96,11 @@ asmlinkage long sys_ioperm(unsigned long from, unsigned long num, int turn_on)
return 0;
}
+SYSCALL_DEFINE3(ioperm, unsigned long, from, unsigned long, num, int, turn_on)
+{
+ return ksys_ioperm(from, num, turn_on);
+}
+
/*
* sys_iopl has to be used when you want to access the IO ports
* beyond the 0x3ff range: to get the full 65536 ports bitmapped
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index a539410c4ea9..772196c1b8c4 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -61,9 +61,14 @@ void __init init_ISA_irqs(void)
struct irq_chip *chip = legacy_pic->chip;
int i;
-#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
+ /*
+ * Try to set up the through-local-APIC virtual wire mode earlier.
+ *
+ * On some 32-bit UP machines, whose APIC has been disabled by BIOS
+ * and then got re-enabled by "lapic", it hangs at boot time without this.
+ */
init_bsp_APIC();
-#endif
+
legacy_pic->init(0);
for (i = 0; i < nr_legacy_irqs(); i++)
diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c
index b68fd895235a..fa183a131edc 100644
--- a/arch/x86/kernel/jailhouse.c
+++ b/arch/x86/kernel/jailhouse.c
@@ -124,6 +124,14 @@ static int __init jailhouse_pci_arch_init(void)
if (pcibios_last_bus < 0)
pcibios_last_bus = 0xff;
+#ifdef CONFIG_PCI_MMCONFIG
+ if (setup_data.pci_mmconfig_base) {
+ pci_mmconfig_add(0, 0, pcibios_last_bus,
+ setup_data.pci_mmconfig_base);
+ pci_mmcfg_arch_init();
+ }
+#endif
+
return 0;
}
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index bd36f3c33cd0..0715f827607c 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -1168,10 +1168,18 @@ NOKPROBE_SYMBOL(longjmp_break_handler);
bool arch_within_kprobe_blacklist(unsigned long addr)
{
+ bool is_in_entry_trampoline_section = false;
+
+#ifdef CONFIG_X86_64
+ is_in_entry_trampoline_section =
+ (addr >= (unsigned long)__entry_trampoline_start &&
+ addr < (unsigned long)__entry_trampoline_end);
+#endif
return (addr >= (unsigned long)__kprobes_text_start &&
addr < (unsigned long)__kprobes_text_end) ||
(addr >= (unsigned long)__entry_text_start &&
- addr < (unsigned long)__entry_text_end);
+ addr < (unsigned long)__entry_text_end) ||
+ is_in_entry_trampoline_section;
}
int __init arch_init_kprobes(void)
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index bc1a27280c4b..fae86e36e399 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -546,7 +546,7 @@ static void __init kvm_guest_init(void)
}
if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) &&
- !kvm_para_has_feature(KVM_FEATURE_STEAL_TIME))
+ kvm_para_has_feature(KVM_FEATURE_STEAL_TIME))
pv_mmu_ops.flush_tlb_others = kvm_flush_tlb_others;
if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
@@ -635,7 +635,7 @@ static __init int kvm_setup_pv_tlb_flush(void)
int cpu;
if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) &&
- !kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) {
+ kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) {
for_each_possible_cpu(cpu) {
zalloc_cpumask_var_node(per_cpu_ptr(&__pv_tlb_mask, cpu),
GFP_KERNEL, cpu_to_node(cpu));
diff --git a/arch/x86/kernel/machine_kexec_32.c b/arch/x86/kernel/machine_kexec_32.c
index edfede768688..60cdec6628b0 100644
--- a/arch/x86/kernel/machine_kexec_32.c
+++ b/arch/x86/kernel/machine_kexec_32.c
@@ -195,11 +195,11 @@ void machine_kexec(struct kimage *image)
/*
* We need to put APICs in legacy mode so that we can
* get timer interrupts in second kernel. kexec/kdump
- * paths already have calls to disable_IO_APIC() in
- * one form or other. kexec jump path also need
- * one.
+ * paths already have calls to restore_boot_irq_mode()
+ * in one form or other. kexec jump path also need one.
*/
- disable_IO_APIC();
+ clear_IO_APIC();
+ restore_boot_irq_mode();
#endif
}
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index 3b7427aa7d85..93bd4fb603d1 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -293,11 +293,11 @@ void machine_kexec(struct kimage *image)
/*
* We need to put APICs in legacy mode so that we can
* get timer interrupts in second kernel. kexec/kdump
- * paths already have calls to disable_IO_APIC() in
- * one form or other. kexec jump path also need
- * one.
+ * paths already have calls to restore_boot_irq_mode()
+ * in one form or other. kexec jump path also need one.
*/
- disable_IO_APIC();
+ clear_IO_APIC();
+ restore_boot_irq_mode();
#endif
}
@@ -350,6 +350,7 @@ void arch_crash_save_vmcoreinfo(void)
{
VMCOREINFO_NUMBER(phys_base);
VMCOREINFO_SYMBOL(init_top_pgt);
+ VMCOREINFO_NUMBER(pgtable_l5_enabled);
#ifdef CONFIG_NUMA
VMCOREINFO_SYMBOL(node_data);
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index 35c461f21815..bbfc8b1e9104 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -33,6 +33,7 @@
#include <linux/string.h>
#include <linux/crash_dump.h>
#include <linux/dma-mapping.h>
+#include <linux/dma-direct.h>
#include <linux/bitmap.h>
#include <linux/pci_ids.h>
#include <linux/pci.h>
@@ -445,8 +446,6 @@ static void* calgary_alloc_coherent(struct device *dev, size_t size,
npages = size >> PAGE_SHIFT;
order = get_order(size);
- flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
-
/* alloc enough pages (and possibly more) */
ret = (void *)__get_free_pages(flag, order);
if (!ret)
@@ -493,7 +492,7 @@ static const struct dma_map_ops calgary_dma_ops = {
.map_page = calgary_map_page,
.unmap_page = calgary_unmap_page,
.mapping_error = calgary_mapping_error,
- .dma_supported = x86_dma_supported,
+ .dma_supported = dma_direct_supported,
};
static inline void __iomem * busno_to_bbar(unsigned char num)
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index df7ab02f959f..14437116ffea 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -18,7 +18,7 @@
static int forbid_dac __read_mostly;
-const struct dma_map_ops *dma_ops = &nommu_dma_ops;
+const struct dma_map_ops *dma_ops = &dma_direct_ops;
EXPORT_SYMBOL(dma_ops);
static int iommu_sac_force __read_mostly;
@@ -76,70 +76,12 @@ void __init pci_iommu_alloc(void)
}
}
}
-void *dma_generic_alloc_coherent(struct device *dev, size_t size,
- dma_addr_t *dma_addr, gfp_t flag,
- unsigned long attrs)
-{
- unsigned long dma_mask;
- struct page *page;
- unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
- dma_addr_t addr;
-
- dma_mask = dma_alloc_coherent_mask(dev, flag);
-
-again:
- page = NULL;
- /* CMA can be used only in the context which permits sleeping */
- if (gfpflags_allow_blocking(flag)) {
- page = dma_alloc_from_contiguous(dev, count, get_order(size),
- flag);
- if (page) {
- addr = phys_to_dma(dev, page_to_phys(page));
- if (addr + size > dma_mask) {
- dma_release_from_contiguous(dev, page, count);
- page = NULL;
- }
- }
- }
- /* fallback */
- if (!page)
- page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
- if (!page)
- return NULL;
-
- addr = phys_to_dma(dev, page_to_phys(page));
- if (addr + size > dma_mask) {
- __free_pages(page, get_order(size));
-
- if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
- flag = (flag & ~GFP_DMA32) | GFP_DMA;
- goto again;
- }
-
- return NULL;
- }
- memset(page_address(page), 0, size);
- *dma_addr = addr;
- return page_address(page);
-}
-
-void dma_generic_free_coherent(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_addr, unsigned long attrs)
-{
- unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
- struct page *page = virt_to_page(vaddr);
-
- if (!dma_release_from_contiguous(dev, page, count))
- free_pages((unsigned long)vaddr, get_order(size));
-}
bool arch_dma_alloc_attrs(struct device **dev, gfp_t *gfp)
{
if (!*dev)
*dev = &x86_dma_fallback_dev;
- *gfp = dma_alloc_coherent_gfp_flags(*dev, *gfp);
-
if (!is_device_dma_capable(*dev))
return false;
return true;
@@ -245,16 +187,6 @@ int arch_dma_supported(struct device *dev, u64 mask)
}
EXPORT_SYMBOL(arch_dma_supported);
-int x86_dma_supported(struct device *dev, u64 mask)
-{
- /* Copied from i386. Doesn't make much sense, because it will
- only work for pci_alloc_coherent.
- The caller just has to use GFP_DMA in this case. */
- if (mask < DMA_BIT_MASK(24))
- return 0;
- return 1;
-}
-
static int __init pci_iommu_init(void)
{
struct iommu_table_entry *p;
diff --git a/arch/x86/kernel/pci-nommu.c b/arch/x86/kernel/pci-nommu.c
index 618285e475c6..ac7ea3a8242f 100644
--- a/arch/x86/kernel/pci-nommu.c
+++ b/arch/x86/kernel/pci-nommu.c
@@ -37,7 +37,6 @@ static dma_addr_t nommu_map_page(struct device *dev, struct page *page,
WARN_ON(size == 0);
if (!check_addr("map_single", dev, bus, size))
return NOMMU_MAPPING_ERROR;
- flush_write_buffers();
return bus;
}
@@ -72,25 +71,9 @@ static int nommu_map_sg(struct device *hwdev, struct scatterlist *sg,
return 0;
s->dma_length = s->length;
}
- flush_write_buffers();
return nents;
}
-static void nommu_sync_single_for_device(struct device *dev,
- dma_addr_t addr, size_t size,
- enum dma_data_direction dir)
-{
- flush_write_buffers();
-}
-
-
-static void nommu_sync_sg_for_device(struct device *dev,
- struct scatterlist *sg, int nelems,
- enum dma_data_direction dir)
-{
- flush_write_buffers();
-}
-
static int nommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
return dma_addr == NOMMU_MAPPING_ERROR;
@@ -101,8 +84,6 @@ const struct dma_map_ops nommu_dma_ops = {
.free = dma_generic_free_coherent,
.map_sg = nommu_map_sg,
.map_page = nommu_map_page,
- .sync_single_for_device = nommu_sync_single_for_device,
- .sync_sg_for_device = nommu_sync_sg_for_device,
.is_phys = 1,
.mapping_error = nommu_mapping_error,
.dma_supported = x86_dma_supported,
diff --git a/arch/x86/kernel/pci-swiotlb.c b/arch/x86/kernel/pci-swiotlb.c
index 0ee0f8f34251..661583662430 100644
--- a/arch/x86/kernel/pci-swiotlb.c
+++ b/arch/x86/kernel/pci-swiotlb.c
@@ -17,52 +17,6 @@
int swiotlb __read_mostly;
-void *x86_swiotlb_alloc_coherent(struct device *hwdev, size_t size,
- dma_addr_t *dma_handle, gfp_t flags,
- unsigned long attrs)
-{
- void *vaddr;
-
- /*
- * Don't print a warning when the first allocation attempt fails.
- * swiotlb_alloc_coherent() will print a warning when the DMA
- * memory allocation ultimately failed.
- */
- flags |= __GFP_NOWARN;
-
- vaddr = dma_generic_alloc_coherent(hwdev, size, dma_handle, flags,
- attrs);
- if (vaddr)
- return vaddr;
-
- return swiotlb_alloc_coherent(hwdev, size, dma_handle, flags);
-}
-
-void x86_swiotlb_free_coherent(struct device *dev, size_t size,
- void *vaddr, dma_addr_t dma_addr,
- unsigned long attrs)
-{
- if (is_swiotlb_buffer(dma_to_phys(dev, dma_addr)))
- swiotlb_free_coherent(dev, size, vaddr, dma_addr);
- else
- dma_generic_free_coherent(dev, size, vaddr, dma_addr, attrs);
-}
-
-static const struct dma_map_ops x86_swiotlb_dma_ops = {
- .mapping_error = swiotlb_dma_mapping_error,
- .alloc = x86_swiotlb_alloc_coherent,
- .free = x86_swiotlb_free_coherent,
- .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
- .sync_single_for_device = swiotlb_sync_single_for_device,
- .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
- .sync_sg_for_device = swiotlb_sync_sg_for_device,
- .map_sg = swiotlb_map_sg_attrs,
- .unmap_sg = swiotlb_unmap_sg_attrs,
- .map_page = swiotlb_map_page,
- .unmap_page = swiotlb_unmap_page,
- .dma_supported = NULL,
-};
-
/*
* pci_swiotlb_detect_override - set swiotlb to 1 if necessary
*
@@ -112,7 +66,7 @@ void __init pci_swiotlb_init(void)
{
if (swiotlb) {
swiotlb_init(0);
- dma_ops = &x86_swiotlb_dma_ops;
+ dma_ops = &swiotlb_dma_ops;
}
}
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 2126b9d27c34..725624b6c0c0 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -666,7 +666,7 @@ void native_machine_shutdown(void)
* Even without the erratum, it still makes sense to quiet IO APIC
* before disabling Local APIC.
*/
- disable_IO_APIC();
+ clear_IO_APIC();
#endif
#ifdef CONFIG_SMP
@@ -680,6 +680,7 @@ void native_machine_shutdown(void)
#endif
lapic_shutdown();
+ restore_boot_irq_mode();
#ifdef CONFIG_HPET_TIMER
hpet_disable();
diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index 69ac9cb9cac6..f7b82ed7b5b5 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -41,11 +41,11 @@ EXPORT_SYMBOL(rtc_lock);
*/
int mach_set_rtc_mmss(const struct timespec *now)
{
- unsigned long nowtime = now->tv_sec;
+ unsigned long long nowtime = now->tv_sec;
struct rtc_time tm;
int retval = 0;
- rtc_time_to_tm(nowtime, &tm);
+ rtc_time64_to_tm(nowtime, &tm);
if (!rtc_valid_tm(&tm)) {
retval = mc146818_set_time(&tm);
if (retval)
@@ -53,7 +53,7 @@ int mach_set_rtc_mmss(const struct timespec *now)
__func__, retval);
} else {
printk(KERN_ERR
- "%s: Invalid RTC value: write of %lx to RTC failed\n",
+ "%s: Invalid RTC value: write of %llx to RTC failed\n",
__func__, nowtime);
retval = -EINVAL;
}
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 4c616be28506..6285697b6e56 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -189,9 +189,7 @@ struct ist_info ist_info;
#endif
#else
-struct cpuinfo_x86 boot_cpu_data __read_mostly = {
- .x86_phys_bits = MAX_PHYSMEM_BITS,
-};
+struct cpuinfo_x86 boot_cpu_data __read_mostly;
EXPORT_SYMBOL(boot_cpu_data);
#endif
@@ -851,6 +849,7 @@ void __init setup_arch(char **cmdline_p)
__flush_tlb_all();
#else
printk(KERN_INFO "Command line: %s\n", boot_command_line);
+ boot_cpu_data.x86_phys_bits = MAX_PHYSMEM_BITS;
#endif
/*
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 4cdc0b27ec82..da270b95fe4d 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -25,6 +25,7 @@
#include <linux/user-return-notifier.h>
#include <linux/uprobes.h>
#include <linux/context_tracking.h>
+#include <linux/syscalls.h>
#include <asm/processor.h>
#include <asm/ucontext.h>
@@ -601,7 +602,7 @@ static int x32_setup_rt_frame(struct ksignal *ksig,
* Do a signal return; undo the signal stack.
*/
#ifdef CONFIG_X86_32
-asmlinkage unsigned long sys_sigreturn(void)
+SYSCALL_DEFINE0(sigreturn)
{
struct pt_regs *regs = current_pt_regs();
struct sigframe __user *frame;
@@ -633,7 +634,7 @@ badframe:
}
#endif /* CONFIG_X86_32 */
-asmlinkage long sys_rt_sigreturn(void)
+SYSCALL_DEFINE0(rt_sigreturn)
{
struct pt_regs *regs = current_pt_regs();
struct rt_sigframe __user *frame;
diff --git a/arch/x86/kernel/sys_x86_64.c b/arch/x86/kernel/sys_x86_64.c
index 676774b9bb8d..a3f15ed545b5 100644
--- a/arch/x86/kernel/sys_x86_64.c
+++ b/arch/x86/kernel/sys_x86_64.c
@@ -97,7 +97,7 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
if (off & ~PAGE_MASK)
goto out;
- error = sys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
+ error = ksys_mmap_pgoff(addr, len, prot, flags, fd, off >> PAGE_SHIFT);
out:
return error;
}
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 3d9b2308e7fa..03f3d7695dac 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -577,7 +577,6 @@ do_general_protection(struct pt_regs *regs, long error_code)
}
NOKPROBE_SYMBOL(do_general_protection);
-/* May run on IST stack. */
dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
{
#ifdef CONFIG_DYNAMIC_FTRACE
@@ -592,6 +591,13 @@ dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
if (poke_int3_handler(regs))
return;
+ /*
+ * Use ist_enter despite the fact that we don't use an IST stack.
+ * We can be called from a kprobe in non-CONTEXT_KERNEL kernel
+ * mode or even during context tracking state changes.
+ *
+ * This means that we can't schedule. That's okay.
+ */
ist_enter(regs);
RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
@@ -609,15 +615,10 @@ dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
SIGTRAP) == NOTIFY_STOP)
goto exit;
- /*
- * Let others (NMI) know that the debug stack is in use
- * as we may switch to the interrupt stack.
- */
- debug_stack_usage_inc();
cond_local_irq_enable(regs);
do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
cond_local_irq_disable(regs);
- debug_stack_usage_dec();
+
exit:
ist_exit(regs);
}
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index fb4302738410..ef32297ff17e 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1179,6 +1179,45 @@ struct system_counterval_t convert_art_to_tsc(u64 art)
}
EXPORT_SYMBOL(convert_art_to_tsc);
+/**
+ * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC.
+ * @art_ns: ART (Always Running Timer) in unit of nanoseconds
+ *
+ * PTM requires all timestamps to be in units of nanoseconds. When user
+ * software requests a cross-timestamp, this function converts system timestamp
+ * to TSC.
+ *
+ * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set
+ * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check
+ * that this flag is set before conversion to TSC is attempted.
+ *
+ * Return:
+ * struct system_counterval_t - system counter value with the pointer to the
+ * corresponding clocksource
+ * @cycles: System counter value
+ * @cs: Clocksource corresponding to system counter value. Used
+ * by timekeeping code to verify comparibility of two cycle
+ * values.
+ */
+
+struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns)
+{
+ u64 tmp, res, rem;
+
+ rem = do_div(art_ns, USEC_PER_SEC);
+
+ res = art_ns * tsc_khz;
+ tmp = rem * tsc_khz;
+
+ do_div(tmp, USEC_PER_SEC);
+ res += tmp;
+
+ return (struct system_counterval_t) { .cs = art_related_clocksource,
+ .cycles = res};
+}
+EXPORT_SYMBOL(convert_art_ns_to_tsc);
+
+
static void tsc_refine_calibration_work(struct work_struct *work);
static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
/**
diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c
index 5edb27f1a2c4..9d0b5af7db91 100644
--- a/arch/x86/kernel/vm86_32.c
+++ b/arch/x86/kernel/vm86_32.c
@@ -727,7 +727,8 @@ void handle_vm86_fault(struct kernel_vm86_regs *regs, long error_code)
return;
check_vip:
- if (VEFLAGS & X86_EFLAGS_VIP) {
+ if ((VEFLAGS & (X86_EFLAGS_VIP | X86_EFLAGS_VIF)) ==
+ (X86_EFLAGS_VIP | X86_EFLAGS_VIF)) {
save_v86_state(regs, VM86_STI);
return;
}
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 9b138a06c1a4..795f3a80e576 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -102,7 +102,6 @@ SECTIONS
_stext = .;
/* bootstrapping code */
HEAD_TEXT
- . = ALIGN(8);
TEXT_TEXT
SCHED_TEXT
CPUIDLE_TEXT
@@ -118,9 +117,11 @@ SECTIONS
#ifdef CONFIG_X86_64
. = ALIGN(PAGE_SIZE);
+ VMLINUX_SYMBOL(__entry_trampoline_start) = .;
_entry_trampoline = .;
*(.entry_trampoline)
. = ALIGN(PAGE_SIZE);
+ VMLINUX_SYMBOL(__entry_trampoline_end) = .;
ASSERT(. - _entry_trampoline == PAGE_SIZE, "entry trampoline is too big");
#endif
@@ -198,7 +199,7 @@ SECTIONS
. = __vvar_beginning_hack + PAGE_SIZE;
} :data
- . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE);
+ . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE);
/* Init code and data - will be freed after init */
. = ALIGN(PAGE_SIZE);
@@ -366,8 +367,8 @@ SECTIONS
. = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */
_end = .;
- STABS_DEBUG
- DWARF_DEBUG
+ STABS_DEBUG
+ DWARF_DEBUG
/* Sections to be discarded */
DISCARDS
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 1151ccd72ce9..ebda84a91510 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -8,6 +8,7 @@
#include <linux/export.h>
#include <linux/pci.h>
+#include <asm/acpi.h>
#include <asm/bios_ebda.h>
#include <asm/paravirt.h>
#include <asm/pci_x86.h>
@@ -26,10 +27,11 @@
void x86_init_noop(void) { }
void __init x86_init_uint_noop(unsigned int unused) { }
-int __init iommu_init_noop(void) { return 0; }
-void iommu_shutdown_noop(void) { }
-bool __init bool_x86_init_noop(void) { return false; }
-void x86_op_int_noop(int cpu) { }
+static int __init iommu_init_noop(void) { return 0; }
+static void iommu_shutdown_noop(void) { }
+static bool __init bool_x86_init_noop(void) { return false; }
+static void x86_op_int_noop(int cpu) { }
+static u64 u64_x86_init_noop(void) { return 0; }
/*
* The platform setup functions are preset with the default functions
@@ -91,6 +93,11 @@ struct x86_init_ops x86_init __initdata = {
.x2apic_available = bool_x86_init_noop,
.init_mem_mapping = x86_init_noop,
},
+
+ .acpi = {
+ .get_root_pointer = u64_x86_init_noop,
+ .reduced_hw_early_init = acpi_generic_reduced_hw_init,
+ },
};
struct x86_cpuinit_ops x86_cpuinit = {
@@ -146,7 +153,7 @@ void arch_restore_msi_irqs(struct pci_dev *dev)
}
#endif
-struct x86_io_apic_ops x86_io_apic_ops __ro_after_init = {
- .read = native_io_apic_read,
- .disable = native_disable_io_apic,
+struct x86_apic_ops x86_apic_ops __ro_after_init = {
+ .io_apic_read = native_io_apic_read,
+ .restore = native_restore_boot_irq_mode,
};
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index f551962ac294..763bb3bade63 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -2770,8 +2770,10 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
else
pte_access &= ~ACC_WRITE_MASK;
+ if (!kvm_is_mmio_pfn(pfn))
+ spte |= shadow_me_mask;
+
spte |= (u64)pfn << PAGE_SHIFT;
- spte |= shadow_me_mask;
if (pte_access & ACC_WRITE_MASK) {
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index be9c839e2c89..9d2043f94e29 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -49,7 +49,6 @@
#include <asm/debugreg.h>
#include <asm/kvm_para.h>
#include <asm/irq_remapping.h>
-#include <asm/microcode.h>
#include <asm/nospec-branch.h>
#include <asm/virtext.h>
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 051dab74e4e9..92496b9b5f2b 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -51,7 +51,6 @@
#include <asm/apic.h>
#include <asm/irq_remapping.h>
#include <asm/mmu_context.h>
-#include <asm/microcode.h>
#include <asm/nospec-branch.h>
#include "trace.h"
@@ -1045,6 +1044,13 @@ static inline bool is_machine_check(u32 intr_info)
(INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
}
+/* Undocumented: icebp/int1 */
+static inline bool is_icebp(u32 intr_info)
+{
+ return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
+ == (INTR_TYPE_PRIV_SW_EXCEPTION | INTR_INFO_VALID_MASK);
+}
+
static inline bool cpu_has_vmx_msr_bitmap(void)
{
return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
@@ -6179,7 +6185,7 @@ static int handle_exception(struct kvm_vcpu *vcpu)
(KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
vcpu->arch.dr6 &= ~15;
vcpu->arch.dr6 |= dr6 | DR6_RTM;
- if (!(dr6 & ~DR6_RESERVED)) /* icebp */
+ if (is_icebp(intr_info))
skip_emulated_instruction(vcpu);
kvm_queue_exception(vcpu, DB_VECTOR);
@@ -10704,6 +10710,11 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
struct vcpu_vmx *vmx = to_vmx(vcpu);
u32 exec_control, vmcs12_exec_ctrl;
+ if (vmx->nested.dirty_vmcs12) {
+ prepare_vmcs02_full(vcpu, vmcs12, from_vmentry);
+ vmx->nested.dirty_vmcs12 = false;
+ }
+
/*
* First, the fields that are shadowed. This must be kept in sync
* with vmx_shadow_fields.h.
@@ -10941,11 +10952,6 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
/* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
vmx_set_efer(vcpu, vcpu->arch.efer);
- if (vmx->nested.dirty_vmcs12) {
- prepare_vmcs02_full(vcpu, vmcs12, from_vmentry);
- vmx->nested.dirty_vmcs12 = false;
- }
-
/* Shadow page tables on either EPT or shadow page tables. */
if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
entry_failure_code))
diff --git a/arch/x86/lib/clear_page_64.S b/arch/x86/lib/clear_page_64.S
index 81b1635d67de..88acd349911b 100644
--- a/arch/x86/lib/clear_page_64.S
+++ b/arch/x86/lib/clear_page_64.S
@@ -1,6 +1,4 @@
#include <linux/linkage.h>
-#include <asm/cpufeatures.h>
-#include <asm/alternative-asm.h>
#include <asm/export.h>
/*
diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c
index 693cce0be82d..fee8b9c0520c 100644
--- a/arch/x86/lib/msr-smp.c
+++ b/arch/x86/lib/msr-smp.c
@@ -2,6 +2,7 @@
#include <linux/export.h>
#include <linux/preempt.h>
#include <linux/smp.h>
+#include <linux/completion.h>
#include <asm/msr.h>
static void __rdmsr_on_cpu(void *info)
@@ -143,13 +144,19 @@ void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs)
}
EXPORT_SYMBOL(wrmsr_on_cpus);
+struct msr_info_completion {
+ struct msr_info msr;
+ struct completion done;
+};
+
/* These "safe" variants are slower and should be used when the target MSR
may not actually exist. */
static void __rdmsr_safe_on_cpu(void *info)
{
- struct msr_info *rv = info;
+ struct msr_info_completion *rv = info;
- rv->err = rdmsr_safe(rv->msr_no, &rv->reg.l, &rv->reg.h);
+ rv->msr.err = rdmsr_safe(rv->msr.msr_no, &rv->msr.reg.l, &rv->msr.reg.h);
+ complete(&rv->done);
}
static void __wrmsr_safe_on_cpu(void *info)
@@ -161,17 +168,26 @@ static void __wrmsr_safe_on_cpu(void *info)
int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
{
+ struct msr_info_completion rv;
+ call_single_data_t csd = {
+ .func = __rdmsr_safe_on_cpu,
+ .info = &rv,
+ };
int err;
- struct msr_info rv;
memset(&rv, 0, sizeof(rv));
+ init_completion(&rv.done);
+ rv.msr.msr_no = msr_no;
- rv.msr_no = msr_no;
- err = smp_call_function_single(cpu, __rdmsr_safe_on_cpu, &rv, 1);
- *l = rv.reg.l;
- *h = rv.reg.h;
+ err = smp_call_function_single_async(cpu, &csd);
+ if (!err) {
+ wait_for_completion(&rv.done);
+ err = rv.msr.err;
+ }
+ *l = rv.msr.reg.l;
+ *h = rv.msr.reg.h;
- return err ? err : rv.err;
+ return err;
}
EXPORT_SYMBOL(rdmsr_safe_on_cpu);
@@ -209,16 +225,13 @@ EXPORT_SYMBOL(wrmsrl_safe_on_cpu);
int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q)
{
+ u32 low, high;
int err;
- struct msr_info rv;
- memset(&rv, 0, sizeof(rv));
+ err = rdmsr_safe_on_cpu(cpu, msr_no, &low, &high);
+ *q = (u64)high << 32 | low;
- rv.msr_no = msr_no;
- err = smp_call_function_single(cpu, __rdmsr_safe_on_cpu, &rv, 1);
- *q = rv.reg.q;
-
- return err ? err : rv.err;
+ return err;
}
EXPORT_SYMBOL(rdmsrl_safe_on_cpu);
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index 27e9e90a8d35..4b101dd6e52f 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -1,12 +1,15 @@
# SPDX-License-Identifier: GPL-2.0
-# Kernel does not boot with instrumentation of tlb.c and mem_encrypt.c
-KCOV_INSTRUMENT_tlb.o := n
-KCOV_INSTRUMENT_mem_encrypt.o := n
+# Kernel does not boot with instrumentation of tlb.c and mem_encrypt*.c
+KCOV_INSTRUMENT_tlb.o := n
+KCOV_INSTRUMENT_mem_encrypt.o := n
+KCOV_INSTRUMENT_mem_encrypt_identity.o := n
-KASAN_SANITIZE_mem_encrypt.o := n
+KASAN_SANITIZE_mem_encrypt.o := n
+KASAN_SANITIZE_mem_encrypt_identity.o := n
ifdef CONFIG_FUNCTION_TRACER
-CFLAGS_REMOVE_mem_encrypt.o = -pg
+CFLAGS_REMOVE_mem_encrypt.o = -pg
+CFLAGS_REMOVE_mem_encrypt_identity.o = -pg
endif
obj-y := init.o init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o \
@@ -16,6 +19,7 @@ obj-y := init.o init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o \
nostackp := $(call cc-option, -fno-stack-protector)
CFLAGS_physaddr.o := $(nostackp)
CFLAGS_setup_nx.o := $(nostackp)
+CFLAGS_mem_encrypt_identity.o := $(nostackp)
CFLAGS_fault.o := -I$(src)/../include/asm/trace
@@ -47,4 +51,5 @@ obj-$(CONFIG_RANDOMIZE_MEMORY) += kaslr.o
obj-$(CONFIG_PAGE_TABLE_ISOLATION) += pti.o
obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt.o
+obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_identity.o
obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt_boot.o
diff --git a/arch/x86/mm/debug_pagetables.c b/arch/x86/mm/debug_pagetables.c
index 421f2664ffa0..225fe2f0bfec 100644
--- a/arch/x86/mm/debug_pagetables.c
+++ b/arch/x86/mm/debug_pagetables.c
@@ -1,4 +1,5 @@
#include <linux/debugfs.h>
+#include <linux/efi.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <asm/pgtable.h>
@@ -72,6 +73,30 @@ static const struct file_operations ptdump_curusr_fops = {
};
#endif
+#if defined(CONFIG_EFI) && defined(CONFIG_X86_64)
+static struct dentry *pe_efi;
+
+static int ptdump_show_efi(struct seq_file *m, void *v)
+{
+ if (efi_mm.pgd)
+ ptdump_walk_pgd_level_debugfs(m, efi_mm.pgd, false);
+ return 0;
+}
+
+static int ptdump_open_efi(struct inode *inode, struct file *filp)
+{
+ return single_open(filp, ptdump_show_efi, NULL);
+}
+
+static const struct file_operations ptdump_efi_fops = {
+ .owner = THIS_MODULE,
+ .open = ptdump_open_efi,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+#endif
+
static struct dentry *dir, *pe_knl, *pe_curknl;
static int __init pt_dump_debug_init(void)
@@ -96,6 +121,13 @@ static int __init pt_dump_debug_init(void)
if (!pe_curusr)
goto err;
#endif
+
+#if defined(CONFIG_EFI) && defined(CONFIG_X86_64)
+ pe_efi = debugfs_create_file("efi", 0400, dir, NULL, &ptdump_efi_fops);
+ if (!pe_efi)
+ goto err;
+#endif
+
return 0;
err:
debugfs_remove_recursive(dir);
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c
index 2a4849e92831..62a7e9f65dec 100644
--- a/arch/x86/mm/dump_pagetables.c
+++ b/arch/x86/mm/dump_pagetables.c
@@ -29,6 +29,7 @@
struct pg_state {
int level;
pgprot_t current_prot;
+ pgprotval_t effective_prot;
unsigned long start_address;
unsigned long current_address;
const struct addr_marker *marker;
@@ -85,11 +86,15 @@ static struct addr_marker address_markers[] = {
[VMALLOC_START_NR] = { 0UL, "vmalloc() Area" },
[VMEMMAP_START_NR] = { 0UL, "Vmemmap" },
#ifdef CONFIG_KASAN
- [KASAN_SHADOW_START_NR] = { KASAN_SHADOW_START, "KASAN shadow" },
- [KASAN_SHADOW_END_NR] = { KASAN_SHADOW_END, "KASAN shadow end" },
+ /*
+ * These fields get initialized with the (dynamic)
+ * KASAN_SHADOW_{START,END} values in pt_dump_init().
+ */
+ [KASAN_SHADOW_START_NR] = { 0UL, "KASAN shadow" },
+ [KASAN_SHADOW_END_NR] = { 0UL, "KASAN shadow end" },
#endif
#ifdef CONFIG_MODIFY_LDT_SYSCALL
- [LDT_NR] = { LDT_BASE_ADDR, "LDT remap" },
+ [LDT_NR] = { 0UL, "LDT remap" },
#endif
[CPU_ENTRY_AREA_NR] = { CPU_ENTRY_AREA_BASE,"CPU entry Area" },
#ifdef CONFIG_X86_ESPFIX64
@@ -231,9 +236,9 @@ static unsigned long normalize_addr(unsigned long u)
* print what we collected so far.
*/
static void note_page(struct seq_file *m, struct pg_state *st,
- pgprot_t new_prot, int level)
+ pgprot_t new_prot, pgprotval_t new_eff, int level)
{
- pgprotval_t prot, cur;
+ pgprotval_t prot, cur, eff;
static const char units[] = "BKMGTPE";
/*
@@ -243,23 +248,24 @@ static void note_page(struct seq_file *m, struct pg_state *st,
*/
prot = pgprot_val(new_prot);
cur = pgprot_val(st->current_prot);
+ eff = st->effective_prot;
if (!st->level) {
/* First entry */
st->current_prot = new_prot;
+ st->effective_prot = new_eff;
st->level = level;
st->marker = address_markers;
st->lines = 0;
pt_dump_seq_printf(m, st->to_dmesg, "---[ %s ]---\n",
st->marker->name);
- } else if (prot != cur || level != st->level ||
+ } else if (prot != cur || new_eff != eff || level != st->level ||
st->current_address >= st->marker[1].start_address) {
const char *unit = units;
unsigned long delta;
int width = sizeof(unsigned long) * 2;
- pgprotval_t pr = pgprot_val(st->current_prot);
- if (st->check_wx && (pr & _PAGE_RW) && !(pr & _PAGE_NX)) {
+ if (st->check_wx && (eff & _PAGE_RW) && !(eff & _PAGE_NX)) {
WARN_ONCE(1,
"x86/mm: Found insecure W+X mapping at address %p/%pS\n",
(void *)st->start_address,
@@ -313,21 +319,30 @@ static void note_page(struct seq_file *m, struct pg_state *st,
st->start_address = st->current_address;
st->current_prot = new_prot;
+ st->effective_prot = new_eff;
st->level = level;
}
}
-static void walk_pte_level(struct seq_file *m, struct pg_state *st, pmd_t addr, unsigned long P)
+static inline pgprotval_t effective_prot(pgprotval_t prot1, pgprotval_t prot2)
+{
+ return (prot1 & prot2 & (_PAGE_USER | _PAGE_RW)) |
+ ((prot1 | prot2) & _PAGE_NX);
+}
+
+static void walk_pte_level(struct seq_file *m, struct pg_state *st, pmd_t addr,
+ pgprotval_t eff_in, unsigned long P)
{
int i;
pte_t *start;
- pgprotval_t prot;
+ pgprotval_t prot, eff;
start = (pte_t *)pmd_page_vaddr(addr);
for (i = 0; i < PTRS_PER_PTE; i++) {
prot = pte_flags(*start);
+ eff = effective_prot(eff_in, prot);
st->current_address = normalize_addr(P + i * PTE_LEVEL_MULT);
- note_page(m, st, __pgprot(prot), 5);
+ note_page(m, st, __pgprot(prot), eff, 5);
start++;
}
}
@@ -344,12 +359,10 @@ static inline bool kasan_page_table(struct seq_file *m, struct pg_state *st,
void *pt)
{
if (__pa(pt) == __pa(kasan_zero_pmd) ||
-#ifdef CONFIG_X86_5LEVEL
- __pa(pt) == __pa(kasan_zero_p4d) ||
-#endif
+ (pgtable_l5_enabled && __pa(pt) == __pa(kasan_zero_p4d)) ||
__pa(pt) == __pa(kasan_zero_pud)) {
pgprotval_t prot = pte_flags(kasan_zero_pte[0]);
- note_page(m, st, __pgprot(prot), 5);
+ note_page(m, st, __pgprot(prot), 0, 5);
return true;
}
return false;
@@ -364,42 +377,45 @@ static inline bool kasan_page_table(struct seq_file *m, struct pg_state *st,
#if PTRS_PER_PMD > 1
-static void walk_pmd_level(struct seq_file *m, struct pg_state *st, pud_t addr, unsigned long P)
+static void walk_pmd_level(struct seq_file *m, struct pg_state *st, pud_t addr,
+ pgprotval_t eff_in, unsigned long P)
{
int i;
pmd_t *start, *pmd_start;
- pgprotval_t prot;
+ pgprotval_t prot, eff;
pmd_start = start = (pmd_t *)pud_page_vaddr(addr);
for (i = 0; i < PTRS_PER_PMD; i++) {
st->current_address = normalize_addr(P + i * PMD_LEVEL_MULT);
if (!pmd_none(*start)) {
+ prot = pmd_flags(*start);
+ eff = effective_prot(eff_in, prot);
if (pmd_large(*start) || !pmd_present(*start)) {
- prot = pmd_flags(*start);
- note_page(m, st, __pgprot(prot), 4);
+ note_page(m, st, __pgprot(prot), eff, 4);
} else if (!kasan_page_table(m, st, pmd_start)) {
- walk_pte_level(m, st, *start,
+ walk_pte_level(m, st, *start, eff,
P + i * PMD_LEVEL_MULT);
}
} else
- note_page(m, st, __pgprot(0), 4);
+ note_page(m, st, __pgprot(0), 0, 4);
start++;
}
}
#else
-#define walk_pmd_level(m,s,a,p) walk_pte_level(m,s,__pmd(pud_val(a)),p)
+#define walk_pmd_level(m,s,a,e,p) walk_pte_level(m,s,__pmd(pud_val(a)),e,p)
#define pud_large(a) pmd_large(__pmd(pud_val(a)))
#define pud_none(a) pmd_none(__pmd(pud_val(a)))
#endif
#if PTRS_PER_PUD > 1
-static void walk_pud_level(struct seq_file *m, struct pg_state *st, p4d_t addr, unsigned long P)
+static void walk_pud_level(struct seq_file *m, struct pg_state *st, p4d_t addr,
+ pgprotval_t eff_in, unsigned long P)
{
int i;
pud_t *start, *pud_start;
- pgprotval_t prot;
+ pgprotval_t prot, eff;
pud_t *prev_pud = NULL;
pud_start = start = (pud_t *)p4d_page_vaddr(addr);
@@ -407,15 +423,16 @@ static void walk_pud_level(struct seq_file *m, struct pg_state *st, p4d_t addr,
for (i = 0; i < PTRS_PER_PUD; i++) {
st->current_address = normalize_addr(P + i * PUD_LEVEL_MULT);
if (!pud_none(*start)) {
+ prot = pud_flags(*start);
+ eff = effective_prot(eff_in, prot);
if (pud_large(*start) || !pud_present(*start)) {
- prot = pud_flags(*start);
- note_page(m, st, __pgprot(prot), 3);
+ note_page(m, st, __pgprot(prot), eff, 3);
} else if (!kasan_page_table(m, st, pud_start)) {
- walk_pmd_level(m, st, *start,
+ walk_pmd_level(m, st, *start, eff,
P + i * PUD_LEVEL_MULT);
}
} else
- note_page(m, st, __pgprot(0), 3);
+ note_page(m, st, __pgprot(0), 0, 3);
prev_pud = start;
start++;
@@ -423,43 +440,43 @@ static void walk_pud_level(struct seq_file *m, struct pg_state *st, p4d_t addr,
}
#else
-#define walk_pud_level(m,s,a,p) walk_pmd_level(m,s,__pud(p4d_val(a)),p)
+#define walk_pud_level(m,s,a,e,p) walk_pmd_level(m,s,__pud(p4d_val(a)),e,p)
#define p4d_large(a) pud_large(__pud(p4d_val(a)))
#define p4d_none(a) pud_none(__pud(p4d_val(a)))
#endif
-#if PTRS_PER_P4D > 1
-
-static void walk_p4d_level(struct seq_file *m, struct pg_state *st, pgd_t addr, unsigned long P)
+static void walk_p4d_level(struct seq_file *m, struct pg_state *st, pgd_t addr,
+ pgprotval_t eff_in, unsigned long P)
{
int i;
p4d_t *start, *p4d_start;
- pgprotval_t prot;
+ pgprotval_t prot, eff;
+
+ if (PTRS_PER_P4D == 1)
+ return walk_pud_level(m, st, __p4d(pgd_val(addr)), eff_in, P);
p4d_start = start = (p4d_t *)pgd_page_vaddr(addr);
for (i = 0; i < PTRS_PER_P4D; i++) {
st->current_address = normalize_addr(P + i * P4D_LEVEL_MULT);
if (!p4d_none(*start)) {
+ prot = p4d_flags(*start);
+ eff = effective_prot(eff_in, prot);
if (p4d_large(*start) || !p4d_present(*start)) {
- prot = p4d_flags(*start);
- note_page(m, st, __pgprot(prot), 2);
+ note_page(m, st, __pgprot(prot), eff, 2);
} else if (!kasan_page_table(m, st, p4d_start)) {
- walk_pud_level(m, st, *start,
+ walk_pud_level(m, st, *start, eff,
P + i * P4D_LEVEL_MULT);
}
} else
- note_page(m, st, __pgprot(0), 2);
+ note_page(m, st, __pgprot(0), 0, 2);
start++;
}
}
-#else
-#define walk_p4d_level(m,s,a,p) walk_pud_level(m,s,__p4d(pgd_val(a)),p)
-#define pgd_large(a) p4d_large(__p4d(pgd_val(a)))
-#define pgd_none(a) p4d_none(__p4d(pgd_val(a)))
-#endif
+#define pgd_large(a) (pgtable_l5_enabled ? pgd_large(a) : p4d_large(__p4d(pgd_val(a))))
+#define pgd_none(a) (pgtable_l5_enabled ? pgd_none(a) : p4d_none(__p4d(pgd_val(a))))
static inline bool is_hypervisor_range(int idx)
{
@@ -483,7 +500,7 @@ static void ptdump_walk_pgd_level_core(struct seq_file *m, pgd_t *pgd,
#else
pgd_t *start = swapper_pg_dir;
#endif
- pgprotval_t prot;
+ pgprotval_t prot, eff;
int i;
struct pg_state st = {};
@@ -499,15 +516,20 @@ static void ptdump_walk_pgd_level_core(struct seq_file *m, pgd_t *pgd,
for (i = 0; i < PTRS_PER_PGD; i++) {
st.current_address = normalize_addr(i * PGD_LEVEL_MULT);
if (!pgd_none(*start) && !is_hypervisor_range(i)) {
+ prot = pgd_flags(*start);
+#ifdef CONFIG_X86_PAE
+ eff = _PAGE_USER | _PAGE_RW;
+#else
+ eff = prot;
+#endif
if (pgd_large(*start) || !pgd_present(*start)) {
- prot = pgd_flags(*start);
- note_page(m, &st, __pgprot(prot), 1);
+ note_page(m, &st, __pgprot(prot), eff, 1);
} else {
- walk_p4d_level(m, &st, *start,
+ walk_p4d_level(m, &st, *start, eff,
i * PGD_LEVEL_MULT);
}
} else
- note_page(m, &st, __pgprot(0), 1);
+ note_page(m, &st, __pgprot(0), 0, 1);
cond_resched();
start++;
@@ -515,7 +537,7 @@ static void ptdump_walk_pgd_level_core(struct seq_file *m, pgd_t *pgd,
/* Flush out the last page */
st.current_address = normalize_addr(PTRS_PER_PGD*PGD_LEVEL_MULT);
- note_page(m, &st, __pgprot(0), 0);
+ note_page(m, &st, __pgprot(0), 0, 0);
if (!checkwx)
return;
if (st.wx_pages)
@@ -570,6 +592,13 @@ static int __init pt_dump_init(void)
address_markers[LOW_KERNEL_NR].start_address = PAGE_OFFSET;
address_markers[VMALLOC_START_NR].start_address = VMALLOC_START;
address_markers[VMEMMAP_START_NR].start_address = VMEMMAP_START;
+#ifdef CONFIG_MODIFY_LDT_SYSCALL
+ address_markers[LDT_NR].start_address = LDT_BASE_ADDR;
+#endif
+#ifdef CONFIG_KASAN
+ address_markers[KASAN_SHADOW_START_NR].start_address = KASAN_SHADOW_START;
+ address_markers[KASAN_SHADOW_END_NR].start_address = KASAN_SHADOW_END;
+#endif
#endif
#ifdef CONFIG_X86_32
address_markers[VMALLOC_START_NR].start_address = VMALLOC_START;
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index c88573d90f3e..73bd8c95ac71 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -330,7 +330,7 @@ static noinline int vmalloc_fault(unsigned long address)
if (!pmd_k)
return -1;
- if (pmd_huge(*pmd_k))
+ if (pmd_large(*pmd_k))
return 0;
pte_k = pte_offset_kernel(pmd_k, address);
@@ -417,11 +417,11 @@ void vmalloc_sync_all(void)
*/
static noinline int vmalloc_fault(unsigned long address)
{
- pgd_t *pgd, *pgd_ref;
- p4d_t *p4d, *p4d_ref;
- pud_t *pud, *pud_ref;
- pmd_t *pmd, *pmd_ref;
- pte_t *pte, *pte_ref;
+ pgd_t *pgd, *pgd_k;
+ p4d_t *p4d, *p4d_k;
+ pud_t *pud;
+ pmd_t *pmd;
+ pte_t *pte;
/* Make sure we are in vmalloc area: */
if (!(address >= VMALLOC_START && address < VMALLOC_END))
@@ -435,73 +435,51 @@ static noinline int vmalloc_fault(unsigned long address)
* case just flush:
*/
pgd = (pgd_t *)__va(read_cr3_pa()) + pgd_index(address);
- pgd_ref = pgd_offset_k(address);
- if (pgd_none(*pgd_ref))
+ pgd_k = pgd_offset_k(address);
+ if (pgd_none(*pgd_k))
return -1;
- if (CONFIG_PGTABLE_LEVELS > 4) {
+ if (pgtable_l5_enabled) {
if (pgd_none(*pgd)) {
- set_pgd(pgd, *pgd_ref);
+ set_pgd(pgd, *pgd_k);
arch_flush_lazy_mmu_mode();
} else {
- BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_ref));
+ BUG_ON(pgd_page_vaddr(*pgd) != pgd_page_vaddr(*pgd_k));
}
}
/* With 4-level paging, copying happens on the p4d level. */
p4d = p4d_offset(pgd, address);
- p4d_ref = p4d_offset(pgd_ref, address);
- if (p4d_none(*p4d_ref))
+ p4d_k = p4d_offset(pgd_k, address);
+ if (p4d_none(*p4d_k))
return -1;
- if (p4d_none(*p4d) && CONFIG_PGTABLE_LEVELS == 4) {
- set_p4d(p4d, *p4d_ref);
+ if (p4d_none(*p4d) && !pgtable_l5_enabled) {
+ set_p4d(p4d, *p4d_k);
arch_flush_lazy_mmu_mode();
} else {
- BUG_ON(p4d_pfn(*p4d) != p4d_pfn(*p4d_ref));
+ BUG_ON(p4d_pfn(*p4d) != p4d_pfn(*p4d_k));
}
- /*
- * Below here mismatches are bugs because these lower tables
- * are shared:
- */
BUILD_BUG_ON(CONFIG_PGTABLE_LEVELS < 4);
pud = pud_offset(p4d, address);
- pud_ref = pud_offset(p4d_ref, address);
- if (pud_none(*pud_ref))
+ if (pud_none(*pud))
return -1;
- if (pud_none(*pud) || pud_pfn(*pud) != pud_pfn(*pud_ref))
- BUG();
-
- if (pud_huge(*pud))
+ if (pud_large(*pud))
return 0;
pmd = pmd_offset(pud, address);
- pmd_ref = pmd_offset(pud_ref, address);
- if (pmd_none(*pmd_ref))
+ if (pmd_none(*pmd))
return -1;
- if (pmd_none(*pmd) || pmd_pfn(*pmd) != pmd_pfn(*pmd_ref))
- BUG();
-
- if (pmd_huge(*pmd))
+ if (pmd_large(*pmd))
return 0;
- pte_ref = pte_offset_kernel(pmd_ref, address);
- if (!pte_present(*pte_ref))
- return -1;
-
pte = pte_offset_kernel(pmd, address);
-
- /*
- * Don't use pte_page here, because the mappings can point
- * outside mem_map, and the NUMA hash lookup cannot handle
- * that:
- */
- if (!pte_present(*pte) || pte_pfn(*pte) != pte_pfn(*pte_ref))
- BUG();
+ if (!pte_present(*pte))
+ return -1;
return 0;
}
@@ -699,7 +677,6 @@ show_fault_oops(struct pt_regs *regs, unsigned long error_code,
printk(KERN_CONT "paging request");
printk(KERN_CONT " at %px\n", (void *) address);
- printk(KERN_ALERT "IP: %pS\n", (void *)regs->ip);
dump_pagetable(address);
}
diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c
index ab33a32df2a8..9aa22be8331e 100644
--- a/arch/x86/mm/ident_map.c
+++ b/arch/x86/mm/ident_map.c
@@ -120,7 +120,7 @@ int kernel_ident_mapping_init(struct x86_mapping_info *info, pgd_t *pgd_page,
result = ident_p4d_init(info, p4d, addr, next);
if (result)
return result;
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+ if (pgtable_l5_enabled) {
set_pgd(pgd, __pgd(__pa(p4d) | info->kernpg_flag));
} else {
/*
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 8b72923f1d35..45241de66785 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -88,12 +88,7 @@ static int __init nonx32_setup(char *str)
}
__setup("noexec32=", nonx32_setup);
-/*
- * When memory was added make sure all the processes MM have
- * suitable PGD entries in the local PGD level page.
- */
-#ifdef CONFIG_X86_5LEVEL
-void sync_global_pgds(unsigned long start, unsigned long end)
+static void sync_global_pgds_l5(unsigned long start, unsigned long end)
{
unsigned long addr;
@@ -129,8 +124,8 @@ void sync_global_pgds(unsigned long start, unsigned long end)
spin_unlock(&pgd_lock);
}
}
-#else
-void sync_global_pgds(unsigned long start, unsigned long end)
+
+static void sync_global_pgds_l4(unsigned long start, unsigned long end)
{
unsigned long addr;
@@ -143,7 +138,7 @@ void sync_global_pgds(unsigned long start, unsigned long end)
* With folded p4d, pgd_none() is always false, we need to
* handle synchonization on p4d level.
*/
- BUILD_BUG_ON(pgd_none(*pgd_ref));
+ MAYBE_BUILD_BUG_ON(pgd_none(*pgd_ref));
p4d_ref = p4d_offset(pgd_ref, addr);
if (p4d_none(*p4d_ref))
@@ -173,7 +168,18 @@ void sync_global_pgds(unsigned long start, unsigned long end)
spin_unlock(&pgd_lock);
}
}
-#endif
+
+/*
+ * When memory was added make sure all the processes MM have
+ * suitable PGD entries in the local PGD level page.
+ */
+void sync_global_pgds(unsigned long start, unsigned long end)
+{
+ if (pgtable_l5_enabled)
+ sync_global_pgds_l5(start, end);
+ else
+ sync_global_pgds_l4(start, end);
+}
/*
* NOTE: This function is marked __ref because it calls __init function
@@ -632,7 +638,7 @@ phys_p4d_init(p4d_t *p4d_page, unsigned long paddr, unsigned long paddr_end,
unsigned long vaddr = (unsigned long)__va(paddr);
int i = p4d_index(vaddr);
- if (!IS_ENABLED(CONFIG_X86_5LEVEL))
+ if (!pgtable_l5_enabled)
return phys_pud_init((pud_t *) p4d_page, paddr, paddr_end, page_size_mask);
for (; i < PTRS_PER_P4D; i++, paddr = paddr_next) {
@@ -712,7 +718,7 @@ kernel_physical_mapping_init(unsigned long paddr_start,
page_size_mask);
spin_lock(&init_mm.page_table_lock);
- if (IS_ENABLED(CONFIG_X86_5LEVEL))
+ if (pgtable_l5_enabled)
pgd_populate(&init_mm, pgd, p4d);
else
p4d_populate(&init_mm, p4d_offset(pgd, vaddr), (pud_t *) p4d);
@@ -800,17 +806,11 @@ int arch_add_memory(int nid, u64 start, u64 size, struct vmem_altmap *altmap,
#define PAGE_INUSE 0xFD
-static void __meminit free_pagetable(struct page *page, int order,
- struct vmem_altmap *altmap)
+static void __meminit free_pagetable(struct page *page, int order)
{
unsigned long magic;
unsigned int nr_pages = 1 << order;
- if (altmap) {
- vmem_altmap_free(altmap, nr_pages);
- return;
- }
-
/* bootmem page has reserved flag */
if (PageReserved(page)) {
__ClearPageReserved(page);
@@ -826,9 +826,17 @@ static void __meminit free_pagetable(struct page *page, int order,
free_pages((unsigned long)page_address(page), order);
}
-static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd,
+static void __meminit free_hugepage_table(struct page *page,
struct vmem_altmap *altmap)
{
+ if (altmap)
+ vmem_altmap_free(altmap, PMD_SIZE / PAGE_SIZE);
+ else
+ free_pagetable(page, get_order(PMD_SIZE));
+}
+
+static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd)
+{
pte_t *pte;
int i;
@@ -839,14 +847,13 @@ static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd,
}
/* free a pte talbe */
- free_pagetable(pmd_page(*pmd), 0, altmap);
+ free_pagetable(pmd_page(*pmd), 0);
spin_lock(&init_mm.page_table_lock);
pmd_clear(pmd);
spin_unlock(&init_mm.page_table_lock);
}
-static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud,
- struct vmem_altmap *altmap)
+static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud)
{
pmd_t *pmd;
int i;
@@ -858,14 +865,13 @@ static void __meminit free_pmd_table(pmd_t *pmd_start, pud_t *pud,
}
/* free a pmd talbe */
- free_pagetable(pud_page(*pud), 0, altmap);
+ free_pagetable(pud_page(*pud), 0);
spin_lock(&init_mm.page_table_lock);
pud_clear(pud);
spin_unlock(&init_mm.page_table_lock);
}
-static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d,
- struct vmem_altmap *altmap)
+static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d)
{
pud_t *pud;
int i;
@@ -877,7 +883,7 @@ static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d,
}
/* free a pud talbe */
- free_pagetable(p4d_page(*p4d), 0, altmap);
+ free_pagetable(p4d_page(*p4d), 0);
spin_lock(&init_mm.page_table_lock);
p4d_clear(p4d);
spin_unlock(&init_mm.page_table_lock);
@@ -885,7 +891,7 @@ static void __meminit free_pud_table(pud_t *pud_start, p4d_t *p4d,
static void __meminit
remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
- struct vmem_altmap *altmap, bool direct)
+ bool direct)
{
unsigned long next, pages = 0;
pte_t *pte;
@@ -916,7 +922,7 @@ remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
* freed when offlining, or simplely not in use.
*/
if (!direct)
- free_pagetable(pte_page(*pte), 0, altmap);
+ free_pagetable(pte_page(*pte), 0);
spin_lock(&init_mm.page_table_lock);
pte_clear(&init_mm, addr, pte);
@@ -939,7 +945,7 @@ remove_pte_table(pte_t *pte_start, unsigned long addr, unsigned long end,
page_addr = page_address(pte_page(*pte));
if (!memchr_inv(page_addr, PAGE_INUSE, PAGE_SIZE)) {
- free_pagetable(pte_page(*pte), 0, altmap);
+ free_pagetable(pte_page(*pte), 0);
spin_lock(&init_mm.page_table_lock);
pte_clear(&init_mm, addr, pte);
@@ -974,9 +980,8 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
if (IS_ALIGNED(addr, PMD_SIZE) &&
IS_ALIGNED(next, PMD_SIZE)) {
if (!direct)
- free_pagetable(pmd_page(*pmd),
- get_order(PMD_SIZE),
- altmap);
+ free_hugepage_table(pmd_page(*pmd),
+ altmap);
spin_lock(&init_mm.page_table_lock);
pmd_clear(pmd);
@@ -989,9 +994,8 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
page_addr = page_address(pmd_page(*pmd));
if (!memchr_inv(page_addr, PAGE_INUSE,
PMD_SIZE)) {
- free_pagetable(pmd_page(*pmd),
- get_order(PMD_SIZE),
- altmap);
+ free_hugepage_table(pmd_page(*pmd),
+ altmap);
spin_lock(&init_mm.page_table_lock);
pmd_clear(pmd);
@@ -1003,8 +1007,8 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
}
pte_base = (pte_t *)pmd_page_vaddr(*pmd);
- remove_pte_table(pte_base, addr, next, altmap, direct);
- free_pte_table(pte_base, pmd, altmap);
+ remove_pte_table(pte_base, addr, next, direct);
+ free_pte_table(pte_base, pmd);
}
/* Call free_pmd_table() in remove_pud_table(). */
@@ -1033,8 +1037,7 @@ remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
IS_ALIGNED(next, PUD_SIZE)) {
if (!direct)
free_pagetable(pud_page(*pud),
- get_order(PUD_SIZE),
- altmap);
+ get_order(PUD_SIZE));
spin_lock(&init_mm.page_table_lock);
pud_clear(pud);
@@ -1048,8 +1051,7 @@ remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
if (!memchr_inv(page_addr, PAGE_INUSE,
PUD_SIZE)) {
free_pagetable(pud_page(*pud),
- get_order(PUD_SIZE),
- altmap);
+ get_order(PUD_SIZE));
spin_lock(&init_mm.page_table_lock);
pud_clear(pud);
@@ -1062,7 +1064,7 @@ remove_pud_table(pud_t *pud_start, unsigned long addr, unsigned long end,
pmd_base = pmd_offset(pud, 0);
remove_pmd_table(pmd_base, addr, next, direct, altmap);
- free_pmd_table(pmd_base, pud, altmap);
+ free_pmd_table(pmd_base, pud);
}
if (direct)
@@ -1093,8 +1095,8 @@ remove_p4d_table(p4d_t *p4d_start, unsigned long addr, unsigned long end,
* 5-level case we should free them. This code will have to change
* to adapt for boot-time switching between 4 and 5 level page tables.
*/
- if (CONFIG_PGTABLE_LEVELS == 5)
- free_pud_table(pud_base, p4d, altmap);
+ if (pgtable_l5_enabled)
+ free_pud_table(pud_base, p4d);
}
if (direct)
diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasan_init_64.c
index af6f2f9c6a26..d8ff013ea9d0 100644
--- a/arch/x86/mm/kasan_init_64.c
+++ b/arch/x86/mm/kasan_init_64.c
@@ -1,6 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
#define DISABLE_BRANCH_PROFILING
#define pr_fmt(fmt) "kasan: " fmt
+
+#ifdef CONFIG_X86_5LEVEL
+/* Too early to use cpu_feature_enabled() */
+#define pgtable_l5_enabled __pgtable_l5_enabled
+#endif
+
#include <linux/bootmem.h>
#include <linux/kasan.h>
#include <linux/kdebug.h>
@@ -19,7 +25,7 @@
extern struct range pfn_mapped[E820_MAX_ENTRIES];
-static p4d_t tmp_p4d_table[PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE);
+static p4d_t tmp_p4d_table[MAX_PTRS_PER_P4D] __initdata __aligned(PAGE_SIZE);
static __init void *early_alloc(size_t size, int nid, bool panic)
{
@@ -176,10 +182,10 @@ static void __init clear_pgds(unsigned long start,
* With folded p4d, pgd_clear() is nop, use p4d_clear()
* instead.
*/
- if (CONFIG_PGTABLE_LEVELS < 5)
- p4d_clear(p4d_offset(pgd, start));
- else
+ if (pgtable_l5_enabled)
pgd_clear(pgd);
+ else
+ p4d_clear(p4d_offset(pgd, start));
}
pgd = pgd_offset_k(start);
@@ -191,7 +197,7 @@ static inline p4d_t *early_p4d_offset(pgd_t *pgd, unsigned long addr)
{
unsigned long p4d;
- if (!IS_ENABLED(CONFIG_X86_5LEVEL))
+ if (!pgtable_l5_enabled)
return (p4d_t *)pgd;
p4d = __pa_nodebug(pgd_val(*pgd)) & PTE_PFN_MASK;
@@ -272,7 +278,7 @@ void __init kasan_early_init(void)
for (i = 0; i < PTRS_PER_PUD; i++)
kasan_zero_pud[i] = __pud(pud_val);
- for (i = 0; IS_ENABLED(CONFIG_X86_5LEVEL) && i < PTRS_PER_P4D; i++)
+ for (i = 0; pgtable_l5_enabled && i < PTRS_PER_P4D; i++)
kasan_zero_p4d[i] = __p4d(p4d_val);
kasan_map_early_shadow(early_top_pgt);
@@ -303,7 +309,7 @@ void __init kasan_init(void)
* bunch of things like kernel code, modules, EFI mapping, etc.
* We need to take extra steps to not overwrite them.
*/
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+ if (pgtable_l5_enabled) {
void *ptr;
ptr = (void *)pgd_page_vaddr(*pgd_offset_k(KASAN_SHADOW_END));
diff --git a/arch/x86/mm/kaslr.c b/arch/x86/mm/kaslr.c
index aedebd2ebf1e..615cc03ced84 100644
--- a/arch/x86/mm/kaslr.c
+++ b/arch/x86/mm/kaslr.c
@@ -34,23 +34,12 @@
#define TB_SHIFT 40
/*
- * Virtual address start and end range for randomization.
- *
* The end address could depend on more configuration options to make the
* highest amount of space for randomization available, but that's too hard
* to keep straight and caused issues already.
*/
-static const unsigned long vaddr_start = __PAGE_OFFSET_BASE;
static const unsigned long vaddr_end = CPU_ENTRY_AREA_BASE;
-/* Default values */
-unsigned long page_offset_base = __PAGE_OFFSET_BASE;
-EXPORT_SYMBOL(page_offset_base);
-unsigned long vmalloc_base = __VMALLOC_BASE;
-EXPORT_SYMBOL(vmalloc_base);
-unsigned long vmemmap_base = __VMEMMAP_BASE;
-EXPORT_SYMBOL(vmemmap_base);
-
/*
* Memory regions randomized by KASLR (except modules that use a separate logic
* earlier during boot). The list is ordered based on virtual addresses. This
@@ -60,8 +49,8 @@ static __initdata struct kaslr_memory_region {
unsigned long *base;
unsigned long size_tb;
} kaslr_regions[] = {
- { &page_offset_base, 1 << (__PHYSICAL_MASK_SHIFT - TB_SHIFT) /* Maximum */ },
- { &vmalloc_base, VMALLOC_SIZE_TB },
+ { &page_offset_base, 0 },
+ { &vmalloc_base, 0 },
{ &vmemmap_base, 1 },
};
@@ -84,11 +73,14 @@ static inline bool kaslr_memory_enabled(void)
void __init kernel_randomize_memory(void)
{
size_t i;
- unsigned long vaddr = vaddr_start;
+ unsigned long vaddr_start, vaddr;
unsigned long rand, memory_tb;
struct rnd_state rand_state;
unsigned long remain_entropy;
+ vaddr_start = pgtable_l5_enabled ? __PAGE_OFFSET_BASE_L5 : __PAGE_OFFSET_BASE_L4;
+ vaddr = vaddr_start;
+
/*
* These BUILD_BUG_ON checks ensure the memory layout is consistent
* with the vaddr_start/vaddr_end variables. These checks are very
@@ -101,6 +93,9 @@ void __init kernel_randomize_memory(void)
if (!kaslr_memory_enabled())
return;
+ kaslr_regions[0].size_tb = 1 << (__PHYSICAL_MASK_SHIFT - TB_SHIFT);
+ kaslr_regions[1].size_tb = VMALLOC_SIZE_TB;
+
/*
* Update Physical memory mapping to available and
* add padding if needed (especially for memory hotplug support).
@@ -129,7 +124,7 @@ void __init kernel_randomize_memory(void)
*/
entropy = remain_entropy / (ARRAY_SIZE(kaslr_regions) - i);
prandom_bytes_state(&rand_state, &rand, sizeof(rand));
- if (IS_ENABLED(CONFIG_X86_5LEVEL))
+ if (pgtable_l5_enabled)
entropy = (rand % (entropy + 1)) & P4D_MASK;
else
entropy = (rand % (entropy + 1)) & PUD_MASK;
@@ -141,7 +136,7 @@ void __init kernel_randomize_memory(void)
* randomization alignment.
*/
vaddr += get_padding(&kaslr_regions[i]);
- if (IS_ENABLED(CONFIG_X86_5LEVEL))
+ if (pgtable_l5_enabled)
vaddr = round_up(vaddr + 1, P4D_SIZE);
else
vaddr = round_up(vaddr + 1, PUD_SIZE);
@@ -217,7 +212,7 @@ void __meminit init_trampoline(void)
return;
}
- if (IS_ENABLED(CONFIG_X86_5LEVEL))
+ if (pgtable_l5_enabled)
init_trampoline_p4d();
else
init_trampoline_pud();
diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c
index 1a53071e2e17..b2de398d1fd3 100644
--- a/arch/x86/mm/mem_encrypt.c
+++ b/arch/x86/mm/mem_encrypt.c
@@ -25,17 +25,12 @@
#include <asm/bootparam.h>
#include <asm/set_memory.h>
#include <asm/cacheflush.h>
-#include <asm/sections.h>
#include <asm/processor-flags.h>
#include <asm/msr.h>
#include <asm/cmdline.h>
#include "mm_internal.h"
-static char sme_cmdline_arg[] __initdata = "mem_encrypt";
-static char sme_cmdline_on[] __initdata = "on";
-static char sme_cmdline_off[] __initdata = "off";
-
/*
* Since SME related variables are set early in the boot process they must
* reside in the .data section so as not to be zeroed out when the .bss
@@ -46,7 +41,7 @@ EXPORT_SYMBOL(sme_me_mask);
DEFINE_STATIC_KEY_FALSE(sev_enable_key);
EXPORT_SYMBOL_GPL(sev_enable_key);
-static bool sev_enabled __section(.data);
+bool sev_enabled __section(.data);
/* Buffer used for early in-place encryption by BSP, no locking needed */
static char sme_early_buffer[PAGE_SIZE] __aligned(PAGE_SIZE);
@@ -200,67 +195,6 @@ void __init sme_early_init(void)
swiotlb_force = SWIOTLB_FORCE;
}
-static void *sev_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
- gfp_t gfp, unsigned long attrs)
-{
- unsigned long dma_mask;
- unsigned int order;
- struct page *page;
- void *vaddr = NULL;
-
- dma_mask = dma_alloc_coherent_mask(dev, gfp);
- order = get_order(size);
-
- /*
- * Memory will be memset to zero after marking decrypted, so don't
- * bother clearing it before.
- */
- gfp &= ~__GFP_ZERO;
-
- page = alloc_pages_node(dev_to_node(dev), gfp, order);
- if (page) {
- dma_addr_t addr;
-
- /*
- * Since we will be clearing the encryption bit, check the
- * mask with it already cleared.
- */
- addr = __sme_clr(phys_to_dma(dev, page_to_phys(page)));
- if ((addr + size) > dma_mask) {
- __free_pages(page, get_order(size));
- } else {
- vaddr = page_address(page);
- *dma_handle = addr;
- }
- }
-
- if (!vaddr)
- vaddr = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
-
- if (!vaddr)
- return NULL;
-
- /* Clear the SME encryption bit for DMA use if not swiotlb area */
- if (!is_swiotlb_buffer(dma_to_phys(dev, *dma_handle))) {
- set_memory_decrypted((unsigned long)vaddr, 1 << order);
- memset(vaddr, 0, PAGE_SIZE << order);
- *dma_handle = __sme_clr(*dma_handle);
- }
-
- return vaddr;
-}
-
-static void sev_free(struct device *dev, size_t size, void *vaddr,
- dma_addr_t dma_handle, unsigned long attrs)
-{
- /* Set the SME encryption bit for re-use if not swiotlb area */
- if (!is_swiotlb_buffer(dma_to_phys(dev, dma_handle)))
- set_memory_encrypted((unsigned long)vaddr,
- 1 << get_order(size));
-
- swiotlb_free_coherent(dev, size, vaddr, dma_handle);
-}
-
static void __init __set_clr_pte_enc(pte_t *kpte, int level, bool enc)
{
pgprot_t old_prot, new_prot;
@@ -413,20 +347,6 @@ bool sev_active(void)
}
EXPORT_SYMBOL(sev_active);
-static const struct dma_map_ops sev_dma_ops = {
- .alloc = sev_alloc,
- .free = sev_free,
- .map_page = swiotlb_map_page,
- .unmap_page = swiotlb_unmap_page,
- .map_sg = swiotlb_map_sg_attrs,
- .unmap_sg = swiotlb_unmap_sg_attrs,
- .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
- .sync_single_for_device = swiotlb_sync_single_for_device,
- .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
- .sync_sg_for_device = swiotlb_sync_sg_for_device,
- .mapping_error = swiotlb_dma_mapping_error,
-};
-
/* Architecture __weak replacement functions */
void __init mem_encrypt_init(void)
{
@@ -437,12 +357,11 @@ void __init mem_encrypt_init(void)
swiotlb_update_mem_attributes();
/*
- * With SEV, DMA operations cannot use encryption. New DMA ops
- * are required in order to mark the DMA areas as decrypted or
- * to use bounce buffers.
+ * With SEV, DMA operations cannot use encryption, we need to use
+ * SWIOTLB to bounce buffer DMA operation.
*/
if (sev_active())
- dma_ops = &sev_dma_ops;
+ dma_ops = &swiotlb_dma_ops;
/*
* With SEV, we need to unroll the rep string I/O instructions.
@@ -455,582 +374,3 @@ void __init mem_encrypt_init(void)
: "Secure Memory Encryption (SME)");
}
-void swiotlb_set_mem_attributes(void *vaddr, unsigned long size)
-{
- WARN(PAGE_ALIGN(size) != size,
- "size is not page-aligned (%#lx)\n", size);
-
- /* Make the SWIOTLB buffer area decrypted */
- set_memory_decrypted((unsigned long)vaddr, size >> PAGE_SHIFT);
-}
-
-struct sme_populate_pgd_data {
- void *pgtable_area;
- pgd_t *pgd;
-
- pmdval_t pmd_flags;
- pteval_t pte_flags;
- unsigned long paddr;
-
- unsigned long vaddr;
- unsigned long vaddr_end;
-};
-
-static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
-{
- unsigned long pgd_start, pgd_end, pgd_size;
- pgd_t *pgd_p;
-
- pgd_start = ppd->vaddr & PGDIR_MASK;
- pgd_end = ppd->vaddr_end & PGDIR_MASK;
-
- pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
-
- pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
-
- memset(pgd_p, 0, pgd_size);
-}
-
-#define PGD_FLAGS _KERNPG_TABLE_NOENC
-#define P4D_FLAGS _KERNPG_TABLE_NOENC
-#define PUD_FLAGS _KERNPG_TABLE_NOENC
-#define PMD_FLAGS _KERNPG_TABLE_NOENC
-
-#define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
-
-#define PMD_FLAGS_DEC PMD_FLAGS_LARGE
-#define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
- (_PAGE_PAT | _PAGE_PWT))
-
-#define PMD_FLAGS_ENC (PMD_FLAGS_LARGE | _PAGE_ENC)
-
-#define PTE_FLAGS (__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
-
-#define PTE_FLAGS_DEC PTE_FLAGS
-#define PTE_FLAGS_DEC_WP ((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
- (_PAGE_PAT | _PAGE_PWT))
-
-#define PTE_FLAGS_ENC (PTE_FLAGS | _PAGE_ENC)
-
-static pmd_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
-{
- pgd_t *pgd_p;
- p4d_t *p4d_p;
- pud_t *pud_p;
- pmd_t *pmd_p;
-
- pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
- if (native_pgd_val(*pgd_p)) {
- if (IS_ENABLED(CONFIG_X86_5LEVEL))
- p4d_p = (p4d_t *)(native_pgd_val(*pgd_p) & ~PTE_FLAGS_MASK);
- else
- pud_p = (pud_t *)(native_pgd_val(*pgd_p) & ~PTE_FLAGS_MASK);
- } else {
- pgd_t pgd;
-
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
- p4d_p = ppd->pgtable_area;
- memset(p4d_p, 0, sizeof(*p4d_p) * PTRS_PER_P4D);
- ppd->pgtable_area += sizeof(*p4d_p) * PTRS_PER_P4D;
-
- pgd = native_make_pgd((pgdval_t)p4d_p + PGD_FLAGS);
- } else {
- pud_p = ppd->pgtable_area;
- memset(pud_p, 0, sizeof(*pud_p) * PTRS_PER_PUD);
- ppd->pgtable_area += sizeof(*pud_p) * PTRS_PER_PUD;
-
- pgd = native_make_pgd((pgdval_t)pud_p + PGD_FLAGS);
- }
- native_set_pgd(pgd_p, pgd);
- }
-
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
- p4d_p += p4d_index(ppd->vaddr);
- if (native_p4d_val(*p4d_p)) {
- pud_p = (pud_t *)(native_p4d_val(*p4d_p) & ~PTE_FLAGS_MASK);
- } else {
- p4d_t p4d;
-
- pud_p = ppd->pgtable_area;
- memset(pud_p, 0, sizeof(*pud_p) * PTRS_PER_PUD);
- ppd->pgtable_area += sizeof(*pud_p) * PTRS_PER_PUD;
-
- p4d = native_make_p4d((pudval_t)pud_p + P4D_FLAGS);
- native_set_p4d(p4d_p, p4d);
- }
- }
-
- pud_p += pud_index(ppd->vaddr);
- if (native_pud_val(*pud_p)) {
- if (native_pud_val(*pud_p) & _PAGE_PSE)
- return NULL;
-
- pmd_p = (pmd_t *)(native_pud_val(*pud_p) & ~PTE_FLAGS_MASK);
- } else {
- pud_t pud;
-
- pmd_p = ppd->pgtable_area;
- memset(pmd_p, 0, sizeof(*pmd_p) * PTRS_PER_PMD);
- ppd->pgtable_area += sizeof(*pmd_p) * PTRS_PER_PMD;
-
- pud = native_make_pud((pmdval_t)pmd_p + PUD_FLAGS);
- native_set_pud(pud_p, pud);
- }
-
- return pmd_p;
-}
-
-static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
-{
- pmd_t *pmd_p;
-
- pmd_p = sme_prepare_pgd(ppd);
- if (!pmd_p)
- return;
-
- pmd_p += pmd_index(ppd->vaddr);
- if (!native_pmd_val(*pmd_p) || !(native_pmd_val(*pmd_p) & _PAGE_PSE))
- native_set_pmd(pmd_p, native_make_pmd(ppd->paddr | ppd->pmd_flags));
-}
-
-static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
-{
- pmd_t *pmd_p;
- pte_t *pte_p;
-
- pmd_p = sme_prepare_pgd(ppd);
- if (!pmd_p)
- return;
-
- pmd_p += pmd_index(ppd->vaddr);
- if (native_pmd_val(*pmd_p)) {
- if (native_pmd_val(*pmd_p) & _PAGE_PSE)
- return;
-
- pte_p = (pte_t *)(native_pmd_val(*pmd_p) & ~PTE_FLAGS_MASK);
- } else {
- pmd_t pmd;
-
- pte_p = ppd->pgtable_area;
- memset(pte_p, 0, sizeof(*pte_p) * PTRS_PER_PTE);
- ppd->pgtable_area += sizeof(*pte_p) * PTRS_PER_PTE;
-
- pmd = native_make_pmd((pteval_t)pte_p + PMD_FLAGS);
- native_set_pmd(pmd_p, pmd);
- }
-
- pte_p += pte_index(ppd->vaddr);
- if (!native_pte_val(*pte_p))
- native_set_pte(pte_p, native_make_pte(ppd->paddr | ppd->pte_flags));
-}
-
-static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
-{
- while (ppd->vaddr < ppd->vaddr_end) {
- sme_populate_pgd_large(ppd);
-
- ppd->vaddr += PMD_PAGE_SIZE;
- ppd->paddr += PMD_PAGE_SIZE;
- }
-}
-
-static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
-{
- while (ppd->vaddr < ppd->vaddr_end) {
- sme_populate_pgd(ppd);
-
- ppd->vaddr += PAGE_SIZE;
- ppd->paddr += PAGE_SIZE;
- }
-}
-
-static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
- pmdval_t pmd_flags, pteval_t pte_flags)
-{
- unsigned long vaddr_end;
-
- ppd->pmd_flags = pmd_flags;
- ppd->pte_flags = pte_flags;
-
- /* Save original end value since we modify the struct value */
- vaddr_end = ppd->vaddr_end;
-
- /* If start is not 2MB aligned, create PTE entries */
- ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE);
- __sme_map_range_pte(ppd);
-
- /* Create PMD entries */
- ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK;
- __sme_map_range_pmd(ppd);
-
- /* If end is not 2MB aligned, create PTE entries */
- ppd->vaddr_end = vaddr_end;
- __sme_map_range_pte(ppd);
-}
-
-static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
-{
- __sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
-}
-
-static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
-{
- __sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
-}
-
-static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
-{
- __sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
-}
-
-static unsigned long __init sme_pgtable_calc(unsigned long len)
-{
- unsigned long p4d_size, pud_size, pmd_size, pte_size;
- unsigned long total;
-
- /*
- * Perform a relatively simplistic calculation of the pagetable
- * entries that are needed. Those mappings will be covered mostly
- * by 2MB PMD entries so we can conservatively calculate the required
- * number of P4D, PUD and PMD structures needed to perform the
- * mappings. For mappings that are not 2MB aligned, PTE mappings
- * would be needed for the start and end portion of the address range
- * that fall outside of the 2MB alignment. This results in, at most,
- * two extra pages to hold PTE entries for each range that is mapped.
- * Incrementing the count for each covers the case where the addresses
- * cross entries.
- */
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
- p4d_size = (ALIGN(len, PGDIR_SIZE) / PGDIR_SIZE) + 1;
- p4d_size *= sizeof(p4d_t) * PTRS_PER_P4D;
- pud_size = (ALIGN(len, P4D_SIZE) / P4D_SIZE) + 1;
- pud_size *= sizeof(pud_t) * PTRS_PER_PUD;
- } else {
- p4d_size = 0;
- pud_size = (ALIGN(len, PGDIR_SIZE) / PGDIR_SIZE) + 1;
- pud_size *= sizeof(pud_t) * PTRS_PER_PUD;
- }
- pmd_size = (ALIGN(len, PUD_SIZE) / PUD_SIZE) + 1;
- pmd_size *= sizeof(pmd_t) * PTRS_PER_PMD;
- pte_size = 2 * sizeof(pte_t) * PTRS_PER_PTE;
-
- total = p4d_size + pud_size + pmd_size + pte_size;
-
- /*
- * Now calculate the added pagetable structures needed to populate
- * the new pagetables.
- */
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
- p4d_size = ALIGN(total, PGDIR_SIZE) / PGDIR_SIZE;
- p4d_size *= sizeof(p4d_t) * PTRS_PER_P4D;
- pud_size = ALIGN(total, P4D_SIZE) / P4D_SIZE;
- pud_size *= sizeof(pud_t) * PTRS_PER_PUD;
- } else {
- p4d_size = 0;
- pud_size = ALIGN(total, PGDIR_SIZE) / PGDIR_SIZE;
- pud_size *= sizeof(pud_t) * PTRS_PER_PUD;
- }
- pmd_size = ALIGN(total, PUD_SIZE) / PUD_SIZE;
- pmd_size *= sizeof(pmd_t) * PTRS_PER_PMD;
-
- total += p4d_size + pud_size + pmd_size;
-
- return total;
-}
-
-void __init __nostackprotector sme_encrypt_kernel(struct boot_params *bp)
-{
- unsigned long workarea_start, workarea_end, workarea_len;
- unsigned long execute_start, execute_end, execute_len;
- unsigned long kernel_start, kernel_end, kernel_len;
- unsigned long initrd_start, initrd_end, initrd_len;
- struct sme_populate_pgd_data ppd;
- unsigned long pgtable_area_len;
- unsigned long decrypted_base;
-
- if (!sme_active())
- return;
-
- /*
- * Prepare for encrypting the kernel and initrd by building new
- * pagetables with the necessary attributes needed to encrypt the
- * kernel in place.
- *
- * One range of virtual addresses will map the memory occupied
- * by the kernel and initrd as encrypted.
- *
- * Another range of virtual addresses will map the memory occupied
- * by the kernel and initrd as decrypted and write-protected.
- *
- * The use of write-protect attribute will prevent any of the
- * memory from being cached.
- */
-
- /* Physical addresses gives us the identity mapped virtual addresses */
- kernel_start = __pa_symbol(_text);
- kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE);
- kernel_len = kernel_end - kernel_start;
-
- initrd_start = 0;
- initrd_end = 0;
- initrd_len = 0;
-#ifdef CONFIG_BLK_DEV_INITRD
- initrd_len = (unsigned long)bp->hdr.ramdisk_size |
- ((unsigned long)bp->ext_ramdisk_size << 32);
- if (initrd_len) {
- initrd_start = (unsigned long)bp->hdr.ramdisk_image |
- ((unsigned long)bp->ext_ramdisk_image << 32);
- initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
- initrd_len = initrd_end - initrd_start;
- }
-#endif
-
- /* Set the encryption workarea to be immediately after the kernel */
- workarea_start = kernel_end;
-
- /*
- * Calculate required number of workarea bytes needed:
- * executable encryption area size:
- * stack page (PAGE_SIZE)
- * encryption routine page (PAGE_SIZE)
- * intermediate copy buffer (PMD_PAGE_SIZE)
- * pagetable structures for the encryption of the kernel
- * pagetable structures for workarea (in case not currently mapped)
- */
- execute_start = workarea_start;
- execute_end = execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE;
- execute_len = execute_end - execute_start;
-
- /*
- * One PGD for both encrypted and decrypted mappings and a set of
- * PUDs and PMDs for each of the encrypted and decrypted mappings.
- */
- pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
- pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2;
- if (initrd_len)
- pgtable_area_len += sme_pgtable_calc(initrd_len) * 2;
-
- /* PUDs and PMDs needed in the current pagetables for the workarea */
- pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len);
-
- /*
- * The total workarea includes the executable encryption area and
- * the pagetable area. The start of the workarea is already 2MB
- * aligned, align the end of the workarea on a 2MB boundary so that
- * we don't try to create/allocate PTE entries from the workarea
- * before it is mapped.
- */
- workarea_len = execute_len + pgtable_area_len;
- workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE);
-
- /*
- * Set the address to the start of where newly created pagetable
- * structures (PGDs, PUDs and PMDs) will be allocated. New pagetable
- * structures are created when the workarea is added to the current
- * pagetables and when the new encrypted and decrypted kernel
- * mappings are populated.
- */
- ppd.pgtable_area = (void *)execute_end;
-
- /*
- * Make sure the current pagetable structure has entries for
- * addressing the workarea.
- */
- ppd.pgd = (pgd_t *)native_read_cr3_pa();
- ppd.paddr = workarea_start;
- ppd.vaddr = workarea_start;
- ppd.vaddr_end = workarea_end;
- sme_map_range_decrypted(&ppd);
-
- /* Flush the TLB - no globals so cr3 is enough */
- native_write_cr3(__native_read_cr3());
-
- /*
- * A new pagetable structure is being built to allow for the kernel
- * and initrd to be encrypted. It starts with an empty PGD that will
- * then be populated with new PUDs and PMDs as the encrypted and
- * decrypted kernel mappings are created.
- */
- ppd.pgd = ppd.pgtable_area;
- memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD);
- ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
-
- /*
- * A different PGD index/entry must be used to get different
- * pagetable entries for the decrypted mapping. Choose the next
- * PGD index and convert it to a virtual address to be used as
- * the base of the mapping.
- */
- decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
- if (initrd_len) {
- unsigned long check_base;
-
- check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
- decrypted_base = max(decrypted_base, check_base);
- }
- decrypted_base <<= PGDIR_SHIFT;
-
- /* Add encrypted kernel (identity) mappings */
- ppd.paddr = kernel_start;
- ppd.vaddr = kernel_start;
- ppd.vaddr_end = kernel_end;
- sme_map_range_encrypted(&ppd);
-
- /* Add decrypted, write-protected kernel (non-identity) mappings */
- ppd.paddr = kernel_start;
- ppd.vaddr = kernel_start + decrypted_base;
- ppd.vaddr_end = kernel_end + decrypted_base;
- sme_map_range_decrypted_wp(&ppd);
-
- if (initrd_len) {
- /* Add encrypted initrd (identity) mappings */
- ppd.paddr = initrd_start;
- ppd.vaddr = initrd_start;
- ppd.vaddr_end = initrd_end;
- sme_map_range_encrypted(&ppd);
- /*
- * Add decrypted, write-protected initrd (non-identity) mappings
- */
- ppd.paddr = initrd_start;
- ppd.vaddr = initrd_start + decrypted_base;
- ppd.vaddr_end = initrd_end + decrypted_base;
- sme_map_range_decrypted_wp(&ppd);
- }
-
- /* Add decrypted workarea mappings to both kernel mappings */
- ppd.paddr = workarea_start;
- ppd.vaddr = workarea_start;
- ppd.vaddr_end = workarea_end;
- sme_map_range_decrypted(&ppd);
-
- ppd.paddr = workarea_start;
- ppd.vaddr = workarea_start + decrypted_base;
- ppd.vaddr_end = workarea_end + decrypted_base;
- sme_map_range_decrypted(&ppd);
-
- /* Perform the encryption */
- sme_encrypt_execute(kernel_start, kernel_start + decrypted_base,
- kernel_len, workarea_start, (unsigned long)ppd.pgd);
-
- if (initrd_len)
- sme_encrypt_execute(initrd_start, initrd_start + decrypted_base,
- initrd_len, workarea_start,
- (unsigned long)ppd.pgd);
-
- /*
- * At this point we are running encrypted. Remove the mappings for
- * the decrypted areas - all that is needed for this is to remove
- * the PGD entry/entries.
- */
- ppd.vaddr = kernel_start + decrypted_base;
- ppd.vaddr_end = kernel_end + decrypted_base;
- sme_clear_pgd(&ppd);
-
- if (initrd_len) {
- ppd.vaddr = initrd_start + decrypted_base;
- ppd.vaddr_end = initrd_end + decrypted_base;
- sme_clear_pgd(&ppd);
- }
-
- ppd.vaddr = workarea_start + decrypted_base;
- ppd.vaddr_end = workarea_end + decrypted_base;
- sme_clear_pgd(&ppd);
-
- /* Flush the TLB - no globals so cr3 is enough */
- native_write_cr3(__native_read_cr3());
-}
-
-void __init __nostackprotector sme_enable(struct boot_params *bp)
-{
- const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off;
- unsigned int eax, ebx, ecx, edx;
- unsigned long feature_mask;
- bool active_by_default;
- unsigned long me_mask;
- char buffer[16];
- u64 msr;
-
- /* Check for the SME/SEV support leaf */
- eax = 0x80000000;
- ecx = 0;
- native_cpuid(&eax, &ebx, &ecx, &edx);
- if (eax < 0x8000001f)
- return;
-
-#define AMD_SME_BIT BIT(0)
-#define AMD_SEV_BIT BIT(1)
- /*
- * Set the feature mask (SME or SEV) based on whether we are
- * running under a hypervisor.
- */
- eax = 1;
- ecx = 0;
- native_cpuid(&eax, &ebx, &ecx, &edx);
- feature_mask = (ecx & BIT(31)) ? AMD_SEV_BIT : AMD_SME_BIT;
-
- /*
- * Check for the SME/SEV feature:
- * CPUID Fn8000_001F[EAX]
- * - Bit 0 - Secure Memory Encryption support
- * - Bit 1 - Secure Encrypted Virtualization support
- * CPUID Fn8000_001F[EBX]
- * - Bits 5:0 - Pagetable bit position used to indicate encryption
- */
- eax = 0x8000001f;
- ecx = 0;
- native_cpuid(&eax, &ebx, &ecx, &edx);
- if (!(eax & feature_mask))
- return;
-
- me_mask = 1UL << (ebx & 0x3f);
-
- /* Check if memory encryption is enabled */
- if (feature_mask == AMD_SME_BIT) {
- /* For SME, check the SYSCFG MSR */
- msr = __rdmsr(MSR_K8_SYSCFG);
- if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
- return;
- } else {
- /* For SEV, check the SEV MSR */
- msr = __rdmsr(MSR_AMD64_SEV);
- if (!(msr & MSR_AMD64_SEV_ENABLED))
- return;
-
- /* SEV state cannot be controlled by a command line option */
- sme_me_mask = me_mask;
- sev_enabled = true;
- return;
- }
-
- /*
- * Fixups have not been applied to phys_base yet and we're running
- * identity mapped, so we must obtain the address to the SME command
- * line argument data using rip-relative addressing.
- */
- asm ("lea sme_cmdline_arg(%%rip), %0"
- : "=r" (cmdline_arg)
- : "p" (sme_cmdline_arg));
- asm ("lea sme_cmdline_on(%%rip), %0"
- : "=r" (cmdline_on)
- : "p" (sme_cmdline_on));
- asm ("lea sme_cmdline_off(%%rip), %0"
- : "=r" (cmdline_off)
- : "p" (sme_cmdline_off));
-
- if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT))
- active_by_default = true;
- else
- active_by_default = false;
-
- cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr |
- ((u64)bp->ext_cmd_line_ptr << 32));
-
- cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer));
-
- if (!strncmp(buffer, cmdline_on, sizeof(buffer)))
- sme_me_mask = me_mask;
- else if (!strncmp(buffer, cmdline_off, sizeof(buffer)))
- sme_me_mask = 0;
- else
- sme_me_mask = active_by_default ? me_mask : 0;
-}
diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c
new file mode 100644
index 000000000000..1b2197d13832
--- /dev/null
+++ b/arch/x86/mm/mem_encrypt_identity.c
@@ -0,0 +1,564 @@
+/*
+ * AMD Memory Encryption Support
+ *
+ * Copyright (C) 2016 Advanced Micro Devices, Inc.
+ *
+ * Author: Tom Lendacky <thomas.lendacky@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define DISABLE_BRANCH_PROFILING
+
+/*
+ * Since we're dealing with identity mappings, physical and virtual
+ * addresses are the same, so override these defines which are ultimately
+ * used by the headers in misc.h.
+ */
+#define __pa(x) ((unsigned long)(x))
+#define __va(x) ((void *)((unsigned long)(x)))
+
+/*
+ * Special hack: we have to be careful, because no indirections are
+ * allowed here, and paravirt_ops is a kind of one. As it will only run in
+ * baremetal anyway, we just keep it from happening. (This list needs to
+ * be extended when new paravirt and debugging variants are added.)
+ */
+#undef CONFIG_PARAVIRT
+#undef CONFIG_PARAVIRT_SPINLOCKS
+
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/mem_encrypt.h>
+
+#include <asm/setup.h>
+#include <asm/sections.h>
+#include <asm/cmdline.h>
+
+#include "mm_internal.h"
+
+#define PGD_FLAGS _KERNPG_TABLE_NOENC
+#define P4D_FLAGS _KERNPG_TABLE_NOENC
+#define PUD_FLAGS _KERNPG_TABLE_NOENC
+#define PMD_FLAGS _KERNPG_TABLE_NOENC
+
+#define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
+
+#define PMD_FLAGS_DEC PMD_FLAGS_LARGE
+#define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
+ (_PAGE_PAT | _PAGE_PWT))
+
+#define PMD_FLAGS_ENC (PMD_FLAGS_LARGE | _PAGE_ENC)
+
+#define PTE_FLAGS (__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
+
+#define PTE_FLAGS_DEC PTE_FLAGS
+#define PTE_FLAGS_DEC_WP ((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
+ (_PAGE_PAT | _PAGE_PWT))
+
+#define PTE_FLAGS_ENC (PTE_FLAGS | _PAGE_ENC)
+
+struct sme_populate_pgd_data {
+ void *pgtable_area;
+ pgd_t *pgd;
+
+ pmdval_t pmd_flags;
+ pteval_t pte_flags;
+ unsigned long paddr;
+
+ unsigned long vaddr;
+ unsigned long vaddr_end;
+};
+
+static char sme_cmdline_arg[] __initdata = "mem_encrypt";
+static char sme_cmdline_on[] __initdata = "on";
+static char sme_cmdline_off[] __initdata = "off";
+
+static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
+{
+ unsigned long pgd_start, pgd_end, pgd_size;
+ pgd_t *pgd_p;
+
+ pgd_start = ppd->vaddr & PGDIR_MASK;
+ pgd_end = ppd->vaddr_end & PGDIR_MASK;
+
+ pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
+
+ pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
+
+ memset(pgd_p, 0, pgd_size);
+}
+
+static pud_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
+{
+ pgd_t *pgd;
+ p4d_t *p4d;
+ pud_t *pud;
+ pmd_t *pmd;
+
+ pgd = ppd->pgd + pgd_index(ppd->vaddr);
+ if (pgd_none(*pgd)) {
+ p4d = ppd->pgtable_area;
+ memset(p4d, 0, sizeof(*p4d) * PTRS_PER_P4D);
+ ppd->pgtable_area += sizeof(*p4d) * PTRS_PER_P4D;
+ set_pgd(pgd, __pgd(PGD_FLAGS | __pa(p4d)));
+ }
+
+ p4d = p4d_offset(pgd, ppd->vaddr);
+ if (p4d_none(*p4d)) {
+ pud = ppd->pgtable_area;
+ memset(pud, 0, sizeof(*pud) * PTRS_PER_PUD);
+ ppd->pgtable_area += sizeof(*pud) * PTRS_PER_PUD;
+ set_p4d(p4d, __p4d(P4D_FLAGS | __pa(pud)));
+ }
+
+ pud = pud_offset(p4d, ppd->vaddr);
+ if (pud_none(*pud)) {
+ pmd = ppd->pgtable_area;
+ memset(pmd, 0, sizeof(*pmd) * PTRS_PER_PMD);
+ ppd->pgtable_area += sizeof(*pmd) * PTRS_PER_PMD;
+ set_pud(pud, __pud(PUD_FLAGS | __pa(pmd)));
+ }
+
+ if (pud_large(*pud))
+ return NULL;
+
+ return pud;
+}
+
+static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
+{
+ pud_t *pud;
+ pmd_t *pmd;
+
+ pud = sme_prepare_pgd(ppd);
+ if (!pud)
+ return;
+
+ pmd = pmd_offset(pud, ppd->vaddr);
+ if (pmd_large(*pmd))
+ return;
+
+ set_pmd(pmd, __pmd(ppd->paddr | ppd->pmd_flags));
+}
+
+static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
+{
+ pud_t *pud;
+ pmd_t *pmd;
+ pte_t *pte;
+
+ pud = sme_prepare_pgd(ppd);
+ if (!pud)
+ return;
+
+ pmd = pmd_offset(pud, ppd->vaddr);
+ if (pmd_none(*pmd)) {
+ pte = ppd->pgtable_area;
+ memset(pte, 0, sizeof(pte) * PTRS_PER_PTE);
+ ppd->pgtable_area += sizeof(pte) * PTRS_PER_PTE;
+ set_pmd(pmd, __pmd(PMD_FLAGS | __pa(pte)));
+ }
+
+ if (pmd_large(*pmd))
+ return;
+
+ pte = pte_offset_map(pmd, ppd->vaddr);
+ if (pte_none(*pte))
+ set_pte(pte, __pte(ppd->paddr | ppd->pte_flags));
+}
+
+static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
+{
+ while (ppd->vaddr < ppd->vaddr_end) {
+ sme_populate_pgd_large(ppd);
+
+ ppd->vaddr += PMD_PAGE_SIZE;
+ ppd->paddr += PMD_PAGE_SIZE;
+ }
+}
+
+static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
+{
+ while (ppd->vaddr < ppd->vaddr_end) {
+ sme_populate_pgd(ppd);
+
+ ppd->vaddr += PAGE_SIZE;
+ ppd->paddr += PAGE_SIZE;
+ }
+}
+
+static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
+ pmdval_t pmd_flags, pteval_t pte_flags)
+{
+ unsigned long vaddr_end;
+
+ ppd->pmd_flags = pmd_flags;
+ ppd->pte_flags = pte_flags;
+
+ /* Save original end value since we modify the struct value */
+ vaddr_end = ppd->vaddr_end;
+
+ /* If start is not 2MB aligned, create PTE entries */
+ ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE);
+ __sme_map_range_pte(ppd);
+
+ /* Create PMD entries */
+ ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK;
+ __sme_map_range_pmd(ppd);
+
+ /* If end is not 2MB aligned, create PTE entries */
+ ppd->vaddr_end = vaddr_end;
+ __sme_map_range_pte(ppd);
+}
+
+static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
+{
+ __sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
+}
+
+static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
+{
+ __sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
+}
+
+static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
+{
+ __sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
+}
+
+static unsigned long __init sme_pgtable_calc(unsigned long len)
+{
+ unsigned long entries = 0, tables = 0;
+
+ /*
+ * Perform a relatively simplistic calculation of the pagetable
+ * entries that are needed. Those mappings will be covered mostly
+ * by 2MB PMD entries so we can conservatively calculate the required
+ * number of P4D, PUD and PMD structures needed to perform the
+ * mappings. For mappings that are not 2MB aligned, PTE mappings
+ * would be needed for the start and end portion of the address range
+ * that fall outside of the 2MB alignment. This results in, at most,
+ * two extra pages to hold PTE entries for each range that is mapped.
+ * Incrementing the count for each covers the case where the addresses
+ * cross entries.
+ */
+
+ /* PGDIR_SIZE is equal to P4D_SIZE on 4-level machine. */
+ if (PTRS_PER_P4D > 1)
+ entries += (DIV_ROUND_UP(len, PGDIR_SIZE) + 1) * sizeof(p4d_t) * PTRS_PER_P4D;
+ entries += (DIV_ROUND_UP(len, P4D_SIZE) + 1) * sizeof(pud_t) * PTRS_PER_PUD;
+ entries += (DIV_ROUND_UP(len, PUD_SIZE) + 1) * sizeof(pmd_t) * PTRS_PER_PMD;
+ entries += 2 * sizeof(pte_t) * PTRS_PER_PTE;
+
+ /*
+ * Now calculate the added pagetable structures needed to populate
+ * the new pagetables.
+ */
+
+ if (PTRS_PER_P4D > 1)
+ tables += DIV_ROUND_UP(entries, PGDIR_SIZE) * sizeof(p4d_t) * PTRS_PER_P4D;
+ tables += DIV_ROUND_UP(entries, P4D_SIZE) * sizeof(pud_t) * PTRS_PER_PUD;
+ tables += DIV_ROUND_UP(entries, PUD_SIZE) * sizeof(pmd_t) * PTRS_PER_PMD;
+
+ return entries + tables;
+}
+
+void __init sme_encrypt_kernel(struct boot_params *bp)
+{
+ unsigned long workarea_start, workarea_end, workarea_len;
+ unsigned long execute_start, execute_end, execute_len;
+ unsigned long kernel_start, kernel_end, kernel_len;
+ unsigned long initrd_start, initrd_end, initrd_len;
+ struct sme_populate_pgd_data ppd;
+ unsigned long pgtable_area_len;
+ unsigned long decrypted_base;
+
+ if (!sme_active())
+ return;
+
+ /*
+ * Prepare for encrypting the kernel and initrd by building new
+ * pagetables with the necessary attributes needed to encrypt the
+ * kernel in place.
+ *
+ * One range of virtual addresses will map the memory occupied
+ * by the kernel and initrd as encrypted.
+ *
+ * Another range of virtual addresses will map the memory occupied
+ * by the kernel and initrd as decrypted and write-protected.
+ *
+ * The use of write-protect attribute will prevent any of the
+ * memory from being cached.
+ */
+
+ /* Physical addresses gives us the identity mapped virtual addresses */
+ kernel_start = __pa_symbol(_text);
+ kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE);
+ kernel_len = kernel_end - kernel_start;
+
+ initrd_start = 0;
+ initrd_end = 0;
+ initrd_len = 0;
+#ifdef CONFIG_BLK_DEV_INITRD
+ initrd_len = (unsigned long)bp->hdr.ramdisk_size |
+ ((unsigned long)bp->ext_ramdisk_size << 32);
+ if (initrd_len) {
+ initrd_start = (unsigned long)bp->hdr.ramdisk_image |
+ ((unsigned long)bp->ext_ramdisk_image << 32);
+ initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
+ initrd_len = initrd_end - initrd_start;
+ }
+#endif
+
+ /* Set the encryption workarea to be immediately after the kernel */
+ workarea_start = kernel_end;
+
+ /*
+ * Calculate required number of workarea bytes needed:
+ * executable encryption area size:
+ * stack page (PAGE_SIZE)
+ * encryption routine page (PAGE_SIZE)
+ * intermediate copy buffer (PMD_PAGE_SIZE)
+ * pagetable structures for the encryption of the kernel
+ * pagetable structures for workarea (in case not currently mapped)
+ */
+ execute_start = workarea_start;
+ execute_end = execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE;
+ execute_len = execute_end - execute_start;
+
+ /*
+ * One PGD for both encrypted and decrypted mappings and a set of
+ * PUDs and PMDs for each of the encrypted and decrypted mappings.
+ */
+ pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
+ pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2;
+ if (initrd_len)
+ pgtable_area_len += sme_pgtable_calc(initrd_len) * 2;
+
+ /* PUDs and PMDs needed in the current pagetables for the workarea */
+ pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len);
+
+ /*
+ * The total workarea includes the executable encryption area and
+ * the pagetable area. The start of the workarea is already 2MB
+ * aligned, align the end of the workarea on a 2MB boundary so that
+ * we don't try to create/allocate PTE entries from the workarea
+ * before it is mapped.
+ */
+ workarea_len = execute_len + pgtable_area_len;
+ workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE);
+
+ /*
+ * Set the address to the start of where newly created pagetable
+ * structures (PGDs, PUDs and PMDs) will be allocated. New pagetable
+ * structures are created when the workarea is added to the current
+ * pagetables and when the new encrypted and decrypted kernel
+ * mappings are populated.
+ */
+ ppd.pgtable_area = (void *)execute_end;
+
+ /*
+ * Make sure the current pagetable structure has entries for
+ * addressing the workarea.
+ */
+ ppd.pgd = (pgd_t *)native_read_cr3_pa();
+ ppd.paddr = workarea_start;
+ ppd.vaddr = workarea_start;
+ ppd.vaddr_end = workarea_end;
+ sme_map_range_decrypted(&ppd);
+
+ /* Flush the TLB - no globals so cr3 is enough */
+ native_write_cr3(__native_read_cr3());
+
+ /*
+ * A new pagetable structure is being built to allow for the kernel
+ * and initrd to be encrypted. It starts with an empty PGD that will
+ * then be populated with new PUDs and PMDs as the encrypted and
+ * decrypted kernel mappings are created.
+ */
+ ppd.pgd = ppd.pgtable_area;
+ memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD);
+ ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
+
+ /*
+ * A different PGD index/entry must be used to get different
+ * pagetable entries for the decrypted mapping. Choose the next
+ * PGD index and convert it to a virtual address to be used as
+ * the base of the mapping.
+ */
+ decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
+ if (initrd_len) {
+ unsigned long check_base;
+
+ check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
+ decrypted_base = max(decrypted_base, check_base);
+ }
+ decrypted_base <<= PGDIR_SHIFT;
+
+ /* Add encrypted kernel (identity) mappings */
+ ppd.paddr = kernel_start;
+ ppd.vaddr = kernel_start;
+ ppd.vaddr_end = kernel_end;
+ sme_map_range_encrypted(&ppd);
+
+ /* Add decrypted, write-protected kernel (non-identity) mappings */
+ ppd.paddr = kernel_start;
+ ppd.vaddr = kernel_start + decrypted_base;
+ ppd.vaddr_end = kernel_end + decrypted_base;
+ sme_map_range_decrypted_wp(&ppd);
+
+ if (initrd_len) {
+ /* Add encrypted initrd (identity) mappings */
+ ppd.paddr = initrd_start;
+ ppd.vaddr = initrd_start;
+ ppd.vaddr_end = initrd_end;
+ sme_map_range_encrypted(&ppd);
+ /*
+ * Add decrypted, write-protected initrd (non-identity) mappings
+ */
+ ppd.paddr = initrd_start;
+ ppd.vaddr = initrd_start + decrypted_base;
+ ppd.vaddr_end = initrd_end + decrypted_base;
+ sme_map_range_decrypted_wp(&ppd);
+ }
+
+ /* Add decrypted workarea mappings to both kernel mappings */
+ ppd.paddr = workarea_start;
+ ppd.vaddr = workarea_start;
+ ppd.vaddr_end = workarea_end;
+ sme_map_range_decrypted(&ppd);
+
+ ppd.paddr = workarea_start;
+ ppd.vaddr = workarea_start + decrypted_base;
+ ppd.vaddr_end = workarea_end + decrypted_base;
+ sme_map_range_decrypted(&ppd);
+
+ /* Perform the encryption */
+ sme_encrypt_execute(kernel_start, kernel_start + decrypted_base,
+ kernel_len, workarea_start, (unsigned long)ppd.pgd);
+
+ if (initrd_len)
+ sme_encrypt_execute(initrd_start, initrd_start + decrypted_base,
+ initrd_len, workarea_start,
+ (unsigned long)ppd.pgd);
+
+ /*
+ * At this point we are running encrypted. Remove the mappings for
+ * the decrypted areas - all that is needed for this is to remove
+ * the PGD entry/entries.
+ */
+ ppd.vaddr = kernel_start + decrypted_base;
+ ppd.vaddr_end = kernel_end + decrypted_base;
+ sme_clear_pgd(&ppd);
+
+ if (initrd_len) {
+ ppd.vaddr = initrd_start + decrypted_base;
+ ppd.vaddr_end = initrd_end + decrypted_base;
+ sme_clear_pgd(&ppd);
+ }
+
+ ppd.vaddr = workarea_start + decrypted_base;
+ ppd.vaddr_end = workarea_end + decrypted_base;
+ sme_clear_pgd(&ppd);
+
+ /* Flush the TLB - no globals so cr3 is enough */
+ native_write_cr3(__native_read_cr3());
+}
+
+void __init sme_enable(struct boot_params *bp)
+{
+ const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off;
+ unsigned int eax, ebx, ecx, edx;
+ unsigned long feature_mask;
+ bool active_by_default;
+ unsigned long me_mask;
+ char buffer[16];
+ u64 msr;
+
+ /* Check for the SME/SEV support leaf */
+ eax = 0x80000000;
+ ecx = 0;
+ native_cpuid(&eax, &ebx, &ecx, &edx);
+ if (eax < 0x8000001f)
+ return;
+
+#define AMD_SME_BIT BIT(0)
+#define AMD_SEV_BIT BIT(1)
+ /*
+ * Set the feature mask (SME or SEV) based on whether we are
+ * running under a hypervisor.
+ */
+ eax = 1;
+ ecx = 0;
+ native_cpuid(&eax, &ebx, &ecx, &edx);
+ feature_mask = (ecx & BIT(31)) ? AMD_SEV_BIT : AMD_SME_BIT;
+
+ /*
+ * Check for the SME/SEV feature:
+ * CPUID Fn8000_001F[EAX]
+ * - Bit 0 - Secure Memory Encryption support
+ * - Bit 1 - Secure Encrypted Virtualization support
+ * CPUID Fn8000_001F[EBX]
+ * - Bits 5:0 - Pagetable bit position used to indicate encryption
+ */
+ eax = 0x8000001f;
+ ecx = 0;
+ native_cpuid(&eax, &ebx, &ecx, &edx);
+ if (!(eax & feature_mask))
+ return;
+
+ me_mask = 1UL << (ebx & 0x3f);
+
+ /* Check if memory encryption is enabled */
+ if (feature_mask == AMD_SME_BIT) {
+ /* For SME, check the SYSCFG MSR */
+ msr = __rdmsr(MSR_K8_SYSCFG);
+ if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
+ return;
+ } else {
+ /* For SEV, check the SEV MSR */
+ msr = __rdmsr(MSR_AMD64_SEV);
+ if (!(msr & MSR_AMD64_SEV_ENABLED))
+ return;
+
+ /* SEV state cannot be controlled by a command line option */
+ sme_me_mask = me_mask;
+ sev_enabled = true;
+ return;
+ }
+
+ /*
+ * Fixups have not been applied to phys_base yet and we're running
+ * identity mapped, so we must obtain the address to the SME command
+ * line argument data using rip-relative addressing.
+ */
+ asm ("lea sme_cmdline_arg(%%rip), %0"
+ : "=r" (cmdline_arg)
+ : "p" (sme_cmdline_arg));
+ asm ("lea sme_cmdline_on(%%rip), %0"
+ : "=r" (cmdline_on)
+ : "p" (sme_cmdline_on));
+ asm ("lea sme_cmdline_off(%%rip), %0"
+ : "=r" (cmdline_off)
+ : "p" (sme_cmdline_off));
+
+ if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT))
+ active_by_default = true;
+ else
+ active_by_default = false;
+
+ cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr |
+ ((u64)bp->ext_cmd_line_ptr << 32));
+
+ cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer));
+
+ if (!strncmp(buffer, cmdline_on, sizeof(buffer)))
+ sme_me_mask = me_mask;
+ else if (!strncmp(buffer, cmdline_off, sizeof(buffer)))
+ sme_me_mask = 0;
+ else
+ sme_me_mask = active_by_default ? me_mask : 0;
+}
diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c
index aca6295350f3..e8a4a09e20f1 100644
--- a/arch/x86/mm/numa_32.c
+++ b/arch/x86/mm/numa_32.c
@@ -60,17 +60,6 @@ void memory_present(int nid, unsigned long start, unsigned long end)
}
printk(KERN_CONT "\n");
}
-
-unsigned long node_memmap_size_bytes(int nid, unsigned long start_pfn,
- unsigned long end_pfn)
-{
- unsigned long nr_pages = end_pfn - start_pfn;
-
- if (!nr_pages)
- return 0;
-
- return (nr_pages + 1) * sizeof(struct page);
-}
#endif
extern unsigned long highend_pfn, highstart_pfn;
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 004abf9ebf12..34cda7e0551b 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -702,4 +702,52 @@ int pmd_clear_huge(pmd_t *pmd)
return 0;
}
+
+/**
+ * pud_free_pmd_page - Clear pud entry and free pmd page.
+ * @pud: Pointer to a PUD.
+ *
+ * Context: The pud range has been unmaped and TLB purged.
+ * Return: 1 if clearing the entry succeeded. 0 otherwise.
+ */
+int pud_free_pmd_page(pud_t *pud)
+{
+ pmd_t *pmd;
+ int i;
+
+ if (pud_none(*pud))
+ return 1;
+
+ pmd = (pmd_t *)pud_page_vaddr(*pud);
+
+ for (i = 0; i < PTRS_PER_PMD; i++)
+ if (!pmd_free_pte_page(&pmd[i]))
+ return 0;
+
+ pud_clear(pud);
+ free_page((unsigned long)pmd);
+
+ return 1;
+}
+
+/**
+ * pmd_free_pte_page - Clear pmd entry and free pte page.
+ * @pmd: Pointer to a PMD.
+ *
+ * Context: The pmd range has been unmaped and TLB purged.
+ * Return: 1 if clearing the entry succeeded. 0 otherwise.
+ */
+int pmd_free_pte_page(pmd_t *pmd)
+{
+ pte_t *pte;
+
+ if (pmd_none(*pmd))
+ return 1;
+
+ pte = (pte_t *)pmd_page_vaddr(*pmd);
+ pmd_clear(pmd);
+ free_page((unsigned long)pte);
+
+ return 1;
+}
#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c
index ce38f165489b..631507f0c198 100644
--- a/arch/x86/mm/pti.c
+++ b/arch/x86/mm/pti.c
@@ -332,7 +332,7 @@ static void __init pti_clone_user_shared(void)
}
/*
- * Clone the ESPFIX P4D into the user space visinble page table
+ * Clone the ESPFIX P4D into the user space visible page table
*/
static void __init pti_setup_espfix64(void)
{
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 7f1a51399674..e055d1a06699 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -157,7 +157,7 @@ static void sync_current_stack_to_mm(struct mm_struct *mm)
unsigned long sp = current_stack_pointer;
pgd_t *pgd = pgd_offset(mm, sp);
- if (CONFIG_PGTABLE_LEVELS > 4) {
+ if (pgtable_l5_enabled) {
if (unlikely(pgd_none(*pgd))) {
pgd_t *pgd_ref = pgd_offset_k(sp);
@@ -613,7 +613,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
{
int cpu;
- struct flush_tlb_info info = {
+ struct flush_tlb_info info __aligned(SMP_CACHE_BYTES) = {
.mm = mm,
};
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index 45e4eb5bcbb2..ce5b2ebd5701 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -1188,7 +1188,7 @@ skip_init_addrs:
* may converge on the last pass. In such case do one more
* pass to emit the final image
*/
- for (pass = 0; pass < 10 || image; pass++) {
+ for (pass = 0; pass < 20 || image; pass++) {
proglen = do_jit(prog, addrs, image, oldproglen, &ctx);
if (proglen <= 0) {
image = NULL;
@@ -1215,6 +1215,7 @@ skip_init_addrs:
}
}
oldproglen = proglen;
+ cond_resched();
}
if (bpf_jit_enable > 1)
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 7df49c40665e..5559dcaddd5e 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -140,12 +140,10 @@ static const struct dmi_system_id pci_crs_quirks[] __initconst = {
void __init pci_acpi_crs_quirks(void)
{
- int year;
+ int year = dmi_get_bios_year();
- if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && year < 2008) {
- if (iomem_resource.end <= 0xffffffff)
- pci_use_crs = false;
- }
+ if (year >= 0 && year < 2008 && iomem_resource.end <= 0xffffffff)
+ pci_use_crs = false;
dmi_check_system(pci_crs_quirks);
diff --git a/arch/x86/pci/direct.c b/arch/x86/pci/direct.c
index 2d9503323d10..a51074c55982 100644
--- a/arch/x86/pci/direct.c
+++ b/arch/x86/pci/direct.c
@@ -195,14 +195,13 @@ static const struct pci_raw_ops pci_direct_conf2 = {
static int __init pci_sanity_check(const struct pci_raw_ops *o)
{
u32 x = 0;
- int year, devfn;
+ int devfn;
if (pci_probe & PCI_NO_CHECKS)
return 1;
/* Assume Type 1 works for newer systems.
This handles machines that don't have anything on PCI Bus 0. */
- dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL);
- if (year >= 2001)
+ if (dmi_get_bios_year() >= 2001)
return 1;
for (devfn = 0; devfn < 0x100; devfn++) {
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index 1cb01abcb1be..dfbe6ac38830 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -4,6 +4,7 @@
#include <linux/init.h>
#include <linux/export.h>
#include <linux/pci.h>
+#include <asm/jailhouse_para.h>
#include <asm/pci_x86.h>
/*
@@ -34,13 +35,14 @@ int __init pci_legacy_init(void)
void pcibios_scan_specific_bus(int busn)
{
+ int stride = jailhouse_paravirt() ? 1 : 8;
int devfn;
u32 l;
if (pci_find_bus(0, busn))
return;
- for (devfn = 0; devfn < 256; devfn += 8) {
+ for (devfn = 0; devfn < 256; devfn += stride) {
if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) &&
l != 0x0000 && l != 0xffff) {
DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l);
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 96684d0adcf9..7389db538c30 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -94,8 +94,8 @@ static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
return new;
}
-static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
- int end, u64 addr)
+struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
+ int end, u64 addr)
{
struct pci_mmcfg_region *new;
@@ -547,19 +547,14 @@ static void __init pci_mmcfg_reject_broken(int early)
static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
struct acpi_mcfg_allocation *cfg)
{
- int year;
-
if (cfg->address < 0xFFFFFFFF)
return 0;
if (!strncmp(mcfg->header.oem_id, "SGI", 3))
return 0;
- if (mcfg->header.revision >= 1) {
- if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
- year >= 2010)
- return 0;
- }
+ if ((mcfg->header.revision >= 1) && (dmi_get_bios_year() >= 2010))
+ return 0;
pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
"is above 4GB, ignored\n", cfg->pci_segment,
diff --git a/arch/x86/pci/sta2x11-fixup.c b/arch/x86/pci/sta2x11-fixup.c
index 75577c1490c4..7a5bafb76d77 100644
--- a/arch/x86/pci/sta2x11-fixup.c
+++ b/arch/x86/pci/sta2x11-fixup.c
@@ -159,43 +159,6 @@ static dma_addr_t a2p(dma_addr_t a, struct pci_dev *pdev)
return p;
}
-/**
- * sta2x11_swiotlb_alloc_coherent - Allocate swiotlb bounce buffers
- * returns virtual address. This is the only "special" function here.
- * @dev: PCI device
- * @size: Size of the buffer
- * @dma_handle: DMA address
- * @flags: memory flags
- */
-static void *sta2x11_swiotlb_alloc_coherent(struct device *dev,
- size_t size,
- dma_addr_t *dma_handle,
- gfp_t flags,
- unsigned long attrs)
-{
- void *vaddr;
-
- vaddr = x86_swiotlb_alloc_coherent(dev, size, dma_handle, flags, attrs);
- *dma_handle = p2a(*dma_handle, to_pci_dev(dev));
- return vaddr;
-}
-
-/* We have our own dma_ops: the same as swiotlb but from alloc (above) */
-static const struct dma_map_ops sta2x11_dma_ops = {
- .alloc = sta2x11_swiotlb_alloc_coherent,
- .free = x86_swiotlb_free_coherent,
- .map_page = swiotlb_map_page,
- .unmap_page = swiotlb_unmap_page,
- .map_sg = swiotlb_map_sg_attrs,
- .unmap_sg = swiotlb_unmap_sg_attrs,
- .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
- .sync_single_for_device = swiotlb_sync_single_for_device,
- .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
- .sync_sg_for_device = swiotlb_sync_sg_for_device,
- .mapping_error = swiotlb_dma_mapping_error,
- .dma_supported = x86_dma_supported,
-};
-
/* At setup time, we use our own ops if the device is a ConneXt one */
static void sta2x11_setup_pdev(struct pci_dev *pdev)
{
@@ -205,7 +168,8 @@ static void sta2x11_setup_pdev(struct pci_dev *pdev)
return;
pci_set_consistent_dma_mask(pdev, STA2X11_AMBA_SIZE - 1);
pci_set_dma_mask(pdev, STA2X11_AMBA_SIZE - 1);
- pdev->dev.dma_ops = &sta2x11_dma_ops;
+ pdev->dev.dma_ops = &swiotlb_dma_ops;
+ pdev->dev.archdata.is_sta2x11 = true;
/* We must enable all devices as master, for audio DMA to work */
pci_set_master(pdev);
@@ -225,7 +189,7 @@ bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
struct sta2x11_mapping *map;
- if (dev->dma_ops != &sta2x11_dma_ops) {
+ if (!dev->archdata.is_sta2x11) {
if (!dev->dma_mask)
return false;
return addr + size - 1 <= *dev->dma_mask;
@@ -243,13 +207,13 @@ bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
}
/**
- * phys_to_dma - Return the DMA AMBA address used for this STA2x11 device
+ * __phys_to_dma - Return the DMA AMBA address used for this STA2x11 device
* @dev: device for a PCI device
* @paddr: Physical address
*/
-dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
- if (dev->dma_ops != &sta2x11_dma_ops)
+ if (!dev->archdata.is_sta2x11)
return paddr;
return p2a(paddr, to_pci_dev(dev));
}
@@ -259,9 +223,9 @@ dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
* @dev: device for a PCI device
* @daddr: STA2x11 AMBA DMA address
*/
-phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
- if (dev->dma_ops != &sta2x11_dma_ops)
+ if (!dev->archdata.is_sta2x11)
return daddr;
return a2p(daddr, to_pci_dev(dev));
}
diff --git a/arch/x86/platform/atom/punit_atom_debug.c b/arch/x86/platform/atom/punit_atom_debug.c
index d49d3be81953..034813d4ab1e 100644
--- a/arch/x86/platform/atom/punit_atom_debug.c
+++ b/arch/x86/platform/atom/punit_atom_debug.c
@@ -109,18 +109,7 @@ static int punit_dev_state_show(struct seq_file *seq_file, void *unused)
return 0;
}
-
-static int punit_dev_state_open(struct inode *inode, struct file *file)
-{
- return single_open(file, punit_dev_state_show, inode->i_private);
-}
-
-static const struct file_operations punit_dev_state_ops = {
- .open = punit_dev_state_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(punit_dev_state);
static struct dentry *punit_dbg_file;
@@ -132,9 +121,9 @@ static int punit_dbgfs_register(struct punit_device *punit_device)
if (!punit_dbg_file)
return -ENXIO;
- dev_state = debugfs_create_file("dev_power_state", S_IFREG | S_IRUGO,
+ dev_state = debugfs_create_file("dev_power_state", 0444,
punit_dbg_file, punit_device,
- &punit_dev_state_ops);
+ &punit_dev_state_fops);
if (!dev_state) {
pr_err("punit_dev_state register failed\n");
debugfs_remove(punit_dbg_file);
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index c310a8284358..bed7e7f4e44c 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -27,12 +27,14 @@
#include <linux/ioport.h>
#include <linux/mc146818rtc.h>
#include <linux/efi.h>
+#include <linux/export.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/ucs2_string.h>
#include <linux/mem_encrypt.h>
+#include <linux/sched/task.h>
#include <asm/setup.h>
#include <asm/page.h>
@@ -81,9 +83,8 @@ pgd_t * __init efi_call_phys_prolog(void)
int n_pgds, i, j;
if (!efi_enabled(EFI_OLD_MEMMAP)) {
- save_pgd = (pgd_t *)__read_cr3();
- write_cr3((unsigned long)efi_scratch.efi_pgt);
- goto out;
+ efi_switch_mm(&efi_mm);
+ return NULL;
}
early_code_mapping_set_exec(1);
@@ -155,8 +156,7 @@ void __init efi_call_phys_epilog(pgd_t *save_pgd)
pud_t *pud;
if (!efi_enabled(EFI_OLD_MEMMAP)) {
- write_cr3((unsigned long)save_pgd);
- __flush_tlb_all();
+ efi_switch_mm(efi_scratch.prev_mm);
return;
}
@@ -190,7 +190,7 @@ void __init efi_call_phys_epilog(pgd_t *save_pgd)
early_code_mapping_set_exec(0);
}
-static pgd_t *efi_pgd;
+EXPORT_SYMBOL_GPL(efi_mm);
/*
* We need our own copy of the higher levels of the page tables
@@ -203,7 +203,7 @@ static pgd_t *efi_pgd;
*/
int __init efi_alloc_page_tables(void)
{
- pgd_t *pgd;
+ pgd_t *pgd, *efi_pgd;
p4d_t *p4d;
pud_t *pud;
gfp_t gfp_mask;
@@ -225,12 +225,16 @@ int __init efi_alloc_page_tables(void)
pud = pud_alloc(&init_mm, p4d, EFI_VA_END);
if (!pud) {
- if (CONFIG_PGTABLE_LEVELS > 4)
+ if (pgtable_l5_enabled)
free_page((unsigned long) pgd_page_vaddr(*pgd));
- free_page((unsigned long)efi_pgd);
+ free_pages((unsigned long)efi_pgd, PGD_ALLOCATION_ORDER);
return -ENOMEM;
}
+ efi_mm.pgd = efi_pgd;
+ mm_init_cpumask(&efi_mm);
+ init_new_context(NULL, &efi_mm);
+
return 0;
}
@@ -243,6 +247,7 @@ void efi_sync_low_kernel_mappings(void)
pgd_t *pgd_k, *pgd_efi;
p4d_t *p4d_k, *p4d_efi;
pud_t *pud_k, *pud_efi;
+ pgd_t *efi_pgd = efi_mm.pgd;
if (efi_enabled(EFI_OLD_MEMMAP))
return;
@@ -255,8 +260,8 @@ void efi_sync_low_kernel_mappings(void)
* only span a single PGD entry and that the entry also maps
* other important kernel regions.
*/
- BUILD_BUG_ON(pgd_index(EFI_VA_END) != pgd_index(MODULES_END));
- BUILD_BUG_ON((EFI_VA_START & PGDIR_MASK) !=
+ MAYBE_BUILD_BUG_ON(pgd_index(EFI_VA_END) != pgd_index(MODULES_END));
+ MAYBE_BUILD_BUG_ON((EFI_VA_START & PGDIR_MASK) !=
(EFI_VA_END & PGDIR_MASK));
pgd_efi = efi_pgd + pgd_index(PAGE_OFFSET);
@@ -336,20 +341,12 @@ int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages)
unsigned long pfn, text, pf;
struct page *page;
unsigned npages;
- pgd_t *pgd;
+ pgd_t *pgd = efi_mm.pgd;
if (efi_enabled(EFI_OLD_MEMMAP))
return 0;
/*
- * Since the PGD is encrypted, set the encryption mask so that when
- * this value is loaded into cr3 the PGD will be decrypted during
- * the pagetable walk.
- */
- efi_scratch.efi_pgt = (pgd_t *)__sme_pa(efi_pgd);
- pgd = efi_pgd;
-
- /*
* It can happen that the physical address of new_memmap lands in memory
* which is not mapped in the EFI page table. Therefore we need to go
* and ident-map those pages containing the map before calling
@@ -362,8 +359,6 @@ int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages)
return 1;
}
- efi_scratch.use_pgd = true;
-
/*
* Certain firmware versions are way too sentimential and still believe
* they are exclusive and unquestionable owners of the first physical page,
@@ -417,7 +412,7 @@ static void __init __map_region(efi_memory_desc_t *md, u64 va)
{
unsigned long flags = _PAGE_RW;
unsigned long pfn;
- pgd_t *pgd = efi_pgd;
+ pgd_t *pgd = efi_mm.pgd;
if (!(md->attribute & EFI_MEMORY_WB))
flags |= _PAGE_PCD;
@@ -521,7 +516,7 @@ void __init parse_efi_setup(u64 phys_addr, u32 data_len)
static int __init efi_update_mappings(efi_memory_desc_t *md, unsigned long pf)
{
unsigned long pfn;
- pgd_t *pgd = efi_pgd;
+ pgd_t *pgd = efi_mm.pgd;
int err1, err2;
/* Update the 1:1 mapping */
@@ -618,10 +613,26 @@ void __init efi_dump_pagetable(void)
if (efi_enabled(EFI_OLD_MEMMAP))
ptdump_walk_pgd_level(NULL, swapper_pg_dir);
else
- ptdump_walk_pgd_level(NULL, efi_pgd);
+ ptdump_walk_pgd_level(NULL, efi_mm.pgd);
#endif
}
+/*
+ * Makes the calling thread switch to/from efi_mm context. Can be used
+ * for SetVirtualAddressMap() i.e. current->active_mm == init_mm as well
+ * as during efi runtime calls i.e current->active_mm == current_mm.
+ * We are not mm_dropping()/mm_grabbing() any mm, because we are not
+ * losing/creating any references.
+ */
+void efi_switch_mm(struct mm_struct *mm)
+{
+ task_lock(current);
+ efi_scratch.prev_mm = current->active_mm;
+ current->active_mm = mm;
+ switch_mm(efi_scratch.prev_mm, mm, NULL);
+ task_unlock(current);
+}
+
#ifdef CONFIG_EFI_MIXED
extern efi_status_t efi64_thunk(u32, ...);
@@ -675,16 +686,13 @@ efi_status_t efi_thunk_set_virtual_address_map(
efi_sync_low_kernel_mappings();
local_irq_save(flags);
- efi_scratch.prev_cr3 = __read_cr3();
- write_cr3((unsigned long)efi_scratch.efi_pgt);
- __flush_tlb_all();
+ efi_switch_mm(&efi_mm);
func = (u32)(unsigned long)phys_set_virtual_address_map;
status = efi64_thunk(func, memory_map_size, descriptor_size,
descriptor_version, virtual_map);
- write_cr3(efi_scratch.prev_cr3);
- __flush_tlb_all();
+ efi_switch_mm(efi_scratch.prev_mm);
local_irq_restore(flags);
return status;
diff --git a/arch/x86/platform/efi/efi_thunk_64.S b/arch/x86/platform/efi/efi_thunk_64.S
index 189b218da87c..46c58b08739c 100644
--- a/arch/x86/platform/efi/efi_thunk_64.S
+++ b/arch/x86/platform/efi/efi_thunk_64.S
@@ -33,7 +33,7 @@ ENTRY(efi64_thunk)
* Switch to 1:1 mapped 32-bit stack pointer.
*/
movq %rsp, efi_saved_sp(%rip)
- movq efi_scratch+25(%rip), %rsp
+ movq efi_scratch(%rip), %rsp
/*
* Calculate the physical address of the kernel text.
diff --git a/arch/x86/platform/efi/quirks.c b/arch/x86/platform/efi/quirks.c
index 5b513ccffde4..36c1f8b9f7e0 100644
--- a/arch/x86/platform/efi/quirks.c
+++ b/arch/x86/platform/efi/quirks.c
@@ -75,7 +75,7 @@ struct quark_security_header {
u32 rsvd[2];
};
-static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 };
+static const efi_char16_t efi_dummy_name[] = L"DUMMY";
static bool efi_no_storage_paranoia;
@@ -105,7 +105,8 @@ early_param("efi_no_storage_paranoia", setup_storage_paranoia);
*/
void efi_delete_dummy_variable(void)
{
- efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+ efi.set_variable((efi_char16_t *)efi_dummy_name,
+ &EFI_DUMMY_GUID,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
@@ -177,12 +178,13 @@ efi_status_t efi_query_variable_store(u32 attributes, unsigned long size,
* that by attempting to use more space than is available.
*/
unsigned long dummy_size = remaining_size + 1024;
- void *dummy = kzalloc(dummy_size, GFP_ATOMIC);
+ void *dummy = kzalloc(dummy_size, GFP_KERNEL);
if (!dummy)
return EFI_OUT_OF_RESOURCES;
- status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+ status = efi.set_variable((efi_char16_t *)efi_dummy_name,
+ &EFI_DUMMY_GUID,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index fb1df9488e98..2ebdf31d9996 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -199,6 +199,12 @@ void __init x86_intel_mid_early_setup(void)
legacy_pic = &null_legacy_pic;
+ /*
+ * Do nothing for now as everything needed done in
+ * x86_intel_mid_early_setup() below.
+ */
+ x86_init.acpi.reduced_hw_early_init = x86_init_noop;
+
pm_power_off = intel_mid_power_off;
machine_ops.emergency_restart = intel_mid_reboot;
diff --git a/arch/x86/platform/intel-quark/imr.c b/arch/x86/platform/intel-quark/imr.c
index 17d6d2296e4d..49828c2707ac 100644
--- a/arch/x86/platform/intel-quark/imr.c
+++ b/arch/x86/platform/intel-quark/imr.c
@@ -224,25 +224,7 @@ static int imr_dbgfs_state_show(struct seq_file *s, void *unused)
mutex_unlock(&idev->lock);
return ret;
}
-
-/**
- * imr_state_open - debugfs open callback.
- *
- * @inode: pointer to struct inode.
- * @file: pointer to struct file.
- * @return: result of single open.
- */
-static int imr_state_open(struct inode *inode, struct file *file)
-{
- return single_open(file, imr_dbgfs_state_show, inode->i_private);
-}
-
-static const struct file_operations imr_state_ops = {
- .open = imr_state_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(imr_dbgfs_state);
/**
* imr_debugfs_register - register debugfs hooks.
@@ -252,8 +234,8 @@ static const struct file_operations imr_state_ops = {
*/
static int imr_debugfs_register(struct imr_device *idev)
{
- idev->file = debugfs_create_file("imr_state", S_IFREG | S_IRUGO, NULL,
- idev, &imr_state_ops);
+ idev->file = debugfs_create_file("imr_state", 0444, NULL, idev,
+ &imr_dbgfs_state_fops);
return PTR_ERR_OR_ZERO(idev->file);
}
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index db77e087adaf..b36caae0fb2f 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -2255,8 +2255,6 @@ static int __init uv_bau_init(void)
init_uvhub(uvhub, vector, uv_base_pnode);
}
- alloc_intr_gate(vector, uv_bau_message_intr1);
-
for_each_possible_blade(uvhub) {
if (uv_blade_nr_possible_cpus(uvhub)) {
unsigned long val;
diff --git a/arch/x86/power/hibernate_64.c b/arch/x86/power/hibernate_64.c
index 0ef5e5204968..74a532989308 100644
--- a/arch/x86/power/hibernate_64.c
+++ b/arch/x86/power/hibernate_64.c
@@ -50,7 +50,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
{
pmd_t *pmd;
pud_t *pud;
- p4d_t *p4d;
+ p4d_t *p4d = NULL;
/*
* The new mapping only has to cover the page containing the image
@@ -66,7 +66,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
* tables used by the image kernel.
*/
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+ if (pgtable_l5_enabled) {
p4d = (p4d_t *)get_safe_page(GFP_ATOMIC);
if (!p4d)
return -ENOMEM;
@@ -84,7 +84,7 @@ static int set_up_temporary_text_mapping(pgd_t *pgd)
__pmd((jump_address_phys & PMD_MASK) | __PAGE_KERNEL_LARGE_EXEC));
set_pud(pud + pud_index(restore_jump_address),
__pud(__pa(pmd) | _KERNPG_TABLE));
- if (IS_ENABLED(CONFIG_X86_5LEVEL)) {
+ if (p4d) {
set_p4d(p4d + p4d_index(restore_jump_address), __p4d(__pa(pud) | _KERNPG_TABLE));
set_pgd(pgd + pgd_index(restore_jump_address), __pgd(__pa(p4d) | _KERNPG_TABLE));
} else {
diff --git a/arch/x86/purgatory/Makefile b/arch/x86/purgatory/Makefile
index 2f15a2ac4209..d70c15de417b 100644
--- a/arch/x86/purgatory/Makefile
+++ b/arch/x86/purgatory/Makefile
@@ -16,7 +16,7 @@ KCOV_INSTRUMENT := n
# in turn leaves some undefined symbols like __fentry__ in purgatory and not
# sure how to relocate those. Like kexec-tools, use custom flags.
-KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes -fno-zero-initialized-in-bss -fno-builtin -ffreestanding -c -MD -Os -mcmodel=large
+KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes -fno-zero-initialized-in-bss -fno-builtin -ffreestanding -c -Os -mcmodel=large
KBUILD_CFLAGS += -m$(BITS)
KBUILD_CFLAGS += $(call cc-option,-fno-PIE)
diff --git a/arch/x86/um/asm/barrier.h b/arch/x86/um/asm/barrier.h
index b7d73400ea29..f31e5d903161 100644
--- a/arch/x86/um/asm/barrier.h
+++ b/arch/x86/um/asm/barrier.h
@@ -30,11 +30,7 @@
#endif /* CONFIG_X86_32 */
-#ifdef CONFIG_X86_PPRO_FENCE
-#define dma_rmb() rmb()
-#else /* CONFIG_X86_PPRO_FENCE */
#define dma_rmb() barrier()
-#endif /* CONFIG_X86_PPRO_FENCE */
#define dma_wmb() barrier()
#include <asm-generic/barrier.h>
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index f605825a04ab..c1f98f32c45f 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -18,9 +18,6 @@ config XEN_PV
bool "Xen PV guest support"
default y
depends on XEN
- # XEN_PV is not ready to work with 5-level paging.
- # Changes to hypervisor are also required.
- depends on !X86_5LEVEL
select XEN_HAVE_PVMMU
select XEN_HAVE_VPMU
help
@@ -79,6 +76,4 @@ config XEN_DEBUG_FS
config XEN_PVH
bool "Support for running as a PVH guest"
depends on XEN && XEN_PVHVM && ACPI
- # Pre-built page tables are not ready to handle 5-level paging.
- depends on !X86_5LEVEL
def_bool n
diff --git a/arch/x86/xen/apic.c b/arch/x86/xen/apic.c
index 2fa79e2e73ea..5e53bfbe5823 100644
--- a/arch/x86/xen/apic.c
+++ b/arch/x86/xen/apic.c
@@ -215,7 +215,7 @@ static void __init xen_apic_check(void)
}
void __init xen_init_apic(void)
{
- x86_io_apic_ops.read = xen_io_apic_read;
+ x86_apic_ops.io_apic_read = xen_io_apic_read;
/* On PV guests the APIC CPUID bit is disabled so none of the
* routines end up executing. */
if (!xen_initial_domain())
diff --git a/arch/x86/xen/enlighten_pvh.c b/arch/x86/xen/enlighten_pvh.c
index 436c4f003e17..aa1c6a6831a9 100644
--- a/arch/x86/xen/enlighten_pvh.c
+++ b/arch/x86/xen/enlighten_pvh.c
@@ -6,6 +6,7 @@
#include <asm/io_apic.h>
#include <asm/hypervisor.h>
#include <asm/e820/api.h>
+#include <asm/x86_init.h>
#include <asm/xen/interface.h>
#include <asm/xen/hypercall.h>
@@ -16,15 +17,20 @@
/*
* PVH variables.
*
- * xen_pvh and pvh_bootparams need to live in data segment since they
- * are used after startup_{32|64}, which clear .bss, are invoked.
+ * xen_pvh pvh_bootparams and pvh_start_info need to live in data segment
+ * since they are used after startup_{32|64}, which clear .bss, are invoked.
*/
bool xen_pvh __attribute__((section(".data"))) = 0;
struct boot_params pvh_bootparams __attribute__((section(".data")));
+struct hvm_start_info pvh_start_info __attribute__((section(".data")));
-struct hvm_start_info pvh_start_info;
unsigned int pvh_start_info_sz = sizeof(pvh_start_info);
+static u64 pvh_get_root_pointer(void)
+{
+ return pvh_start_info.rsdp_paddr;
+}
+
static void __init init_pvh_bootparams(void)
{
struct xen_memory_map memmap;
@@ -71,6 +77,8 @@ static void __init init_pvh_bootparams(void)
*/
pvh_bootparams.hdr.version = 0x212;
pvh_bootparams.hdr.type_of_loader = (9 << 4) | 0; /* Xen loader */
+
+ x86_init.acpi.get_root_pointer = pvh_get_root_pointer;
}
/*
diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
index aae88fec9941..d20763472920 100644
--- a/arch/x86/xen/mmu_pv.c
+++ b/arch/x86/xen/mmu_pv.c
@@ -538,6 +538,22 @@ static void xen_set_p4d(p4d_t *ptr, p4d_t val)
xen_mc_issue(PARAVIRT_LAZY_MMU);
}
+
+#if CONFIG_PGTABLE_LEVELS >= 5
+__visible p4dval_t xen_p4d_val(p4d_t p4d)
+{
+ return pte_mfn_to_pfn(p4d.p4d);
+}
+PV_CALLEE_SAVE_REGS_THUNK(xen_p4d_val);
+
+__visible p4d_t xen_make_p4d(p4dval_t p4d)
+{
+ p4d = pte_pfn_to_mfn(p4d);
+
+ return native_make_p4d(p4d);
+}
+PV_CALLEE_SAVE_REGS_THUNK(xen_make_p4d);
+#endif /* CONFIG_PGTABLE_LEVELS >= 5 */
#endif /* CONFIG_X86_64 */
static int xen_pmd_walk(struct mm_struct *mm, pmd_t *pmd,
@@ -2411,6 +2427,11 @@ static const struct pv_mmu_ops xen_mmu_ops __initconst = {
.alloc_pud = xen_alloc_pmd_init,
.release_pud = xen_release_pmd_init,
+
+#if CONFIG_PGTABLE_LEVELS >= 5
+ .p4d_val = PV_CALLEE_SAVE(xen_p4d_val),
+ .make_p4d = PV_CALLEE_SAVE(xen_make_p4d),
+#endif
#endif /* CONFIG_X86_64 */
.activate_mm = xen_activate_mm,
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index c38e5a732d86..acc5bb2cf1c7 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -52,6 +52,7 @@ static inline void __iomem *ioremap_cache(unsigned long offset,
return xtensa_ioremap_cache(offset, size);
}
#define ioremap_cache ioremap_cache
+#define ioremap_nocache ioremap_nocache
#define ioremap_wc ioremap_nocache
#define ioremap_wt ioremap_nocache
diff --git a/arch/xtensa/kernel/syscall.c b/arch/xtensa/kernel/syscall.c
index 74afbf02d07e..8201748da05b 100644
--- a/arch/xtensa/kernel/syscall.c
+++ b/arch/xtensa/kernel/syscall.c
@@ -55,7 +55,7 @@ asmlinkage long xtensa_shmat(int shmid, char __user *shmaddr, int shmflg)
asmlinkage long xtensa_fadvise64_64(int fd, int advice,
unsigned long long offset, unsigned long long len)
{
- return sys_fadvise64_64(fd, offset, len, advice);
+ return ksys_fadvise64_64(fd, offset, len, advice);
}
#ifdef CONFIG_MMU